Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 24
- Errors: 0
- Kernel Errors: 32
- Boot result: PASS
1 19:21:28.908062 lava-dispatcher, installed at version: 2024.01
2 19:21:28.908272 start: 0 validate
3 19:21:28.908406 Start time: 2024-04-18 19:21:28.908399+00:00 (UTC)
4 19:21:28.908536 Using caching service: 'http://localhost/cache/?uri=%s'
5 19:21:28.908665 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-cros-ec%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 19:21:29.176247 Using caching service: 'http://localhost/cache/?uri=%s'
7 19:21:29.176415 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 19:22:03.460405 Using caching service: 'http://localhost/cache/?uri=%s'
9 19:22:03.461167 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 19:22:03.722881 Using caching service: 'http://localhost/cache/?uri=%s'
11 19:22:03.723743 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 19:22:13.990409 validate duration: 45.08
14 19:22:13.990676 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 19:22:13.990775 start: 1.1 download-retry (timeout 00:10:00) [common]
16 19:22:13.990862 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 19:22:13.990983 Not decompressing ramdisk as can be used compressed.
18 19:22:13.991066 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-cros-ec/20240313.0/arm64/rootfs.cpio.gz
19 19:22:13.991128 saving as /var/lib/lava/dispatcher/tmp/13420342/tftp-deploy-9up0a6oe/ramdisk/rootfs.cpio.gz
20 19:22:13.991190 total size: 39026414 (37 MB)
21 19:22:14.251878 progress 0 % (0 MB)
22 19:22:14.269422 progress 5 % (1 MB)
23 19:22:14.288361 progress 10 % (3 MB)
24 19:22:14.301073 progress 15 % (5 MB)
25 19:22:14.311279 progress 20 % (7 MB)
26 19:22:14.321681 progress 25 % (9 MB)
27 19:22:14.331957 progress 30 % (11 MB)
28 19:22:14.341970 progress 35 % (13 MB)
29 19:22:14.352135 progress 40 % (14 MB)
30 19:22:14.362189 progress 45 % (16 MB)
31 19:22:14.372342 progress 50 % (18 MB)
32 19:22:14.382805 progress 55 % (20 MB)
33 19:22:14.392719 progress 60 % (22 MB)
34 19:22:14.402795 progress 65 % (24 MB)
35 19:22:14.412709 progress 70 % (26 MB)
36 19:22:14.422838 progress 75 % (27 MB)
37 19:22:14.432807 progress 80 % (29 MB)
38 19:22:14.443192 progress 85 % (31 MB)
39 19:22:14.453336 progress 90 % (33 MB)
40 19:22:14.463421 progress 95 % (35 MB)
41 19:22:14.473492 progress 100 % (37 MB)
42 19:22:14.473808 37 MB downloaded in 0.48 s (77.12 MB/s)
43 19:22:14.473980 end: 1.1.1 http-download (duration 00:00:00) [common]
45 19:22:14.474234 end: 1.1 download-retry (duration 00:00:00) [common]
46 19:22:14.474324 start: 1.2 download-retry (timeout 00:10:00) [common]
47 19:22:14.474408 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 19:22:14.474550 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 19:22:14.474620 saving as /var/lib/lava/dispatcher/tmp/13420342/tftp-deploy-9up0a6oe/kernel/Image
50 19:22:14.474681 total size: 54286848 (51 MB)
51 19:22:14.474742 No compression specified
52 19:22:14.475871 progress 0 % (0 MB)
53 19:22:14.489956 progress 5 % (2 MB)
54 19:22:14.503955 progress 10 % (5 MB)
55 19:22:14.517800 progress 15 % (7 MB)
56 19:22:14.532080 progress 20 % (10 MB)
57 19:22:14.546115 progress 25 % (12 MB)
58 19:22:14.560143 progress 30 % (15 MB)
59 19:22:14.573907 progress 35 % (18 MB)
60 19:22:14.587830 progress 40 % (20 MB)
61 19:22:14.601815 progress 45 % (23 MB)
62 19:22:14.616116 progress 50 % (25 MB)
63 19:22:14.630313 progress 55 % (28 MB)
64 19:22:14.644278 progress 60 % (31 MB)
65 19:22:14.658296 progress 65 % (33 MB)
66 19:22:14.672566 progress 70 % (36 MB)
67 19:22:14.686570 progress 75 % (38 MB)
68 19:22:14.700610 progress 80 % (41 MB)
69 19:22:14.715234 progress 85 % (44 MB)
70 19:22:14.729537 progress 90 % (46 MB)
71 19:22:14.743137 progress 95 % (49 MB)
72 19:22:14.757234 progress 100 % (51 MB)
73 19:22:14.757547 51 MB downloaded in 0.28 s (183.03 MB/s)
74 19:22:14.757716 end: 1.2.1 http-download (duration 00:00:00) [common]
76 19:22:14.757994 end: 1.2 download-retry (duration 00:00:00) [common]
77 19:22:14.758120 start: 1.3 download-retry (timeout 00:09:59) [common]
78 19:22:14.758228 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 19:22:14.758399 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 19:22:14.758468 saving as /var/lib/lava/dispatcher/tmp/13420342/tftp-deploy-9up0a6oe/dtb/mt8192-asurada-spherion-r0.dtb
81 19:22:14.758529 total size: 47230 (0 MB)
82 19:22:14.758590 No compression specified
83 19:22:15.024406 progress 69 % (0 MB)
84 19:22:15.024736 progress 100 % (0 MB)
85 19:22:15.024932 0 MB downloaded in 0.27 s (0.17 MB/s)
86 19:22:15.025075 end: 1.3.1 http-download (duration 00:00:00) [common]
88 19:22:15.025471 end: 1.3 download-retry (duration 00:00:00) [common]
89 19:22:15.025625 start: 1.4 download-retry (timeout 00:09:59) [common]
90 19:22:15.025715 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 19:22:15.025850 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 19:22:15.025919 saving as /var/lib/lava/dispatcher/tmp/13420342/tftp-deploy-9up0a6oe/modules/modules.tar
93 19:22:15.025980 total size: 8631416 (8 MB)
94 19:22:15.026043 Using unxz to decompress xz
95 19:22:15.286777 progress 0 % (0 MB)
96 19:22:15.305821 progress 5 % (0 MB)
97 19:22:15.330732 progress 10 % (0 MB)
98 19:22:15.354901 progress 15 % (1 MB)
99 19:22:15.378394 progress 20 % (1 MB)
100 19:22:15.403262 progress 25 % (2 MB)
101 19:22:15.429065 progress 30 % (2 MB)
102 19:22:15.454082 progress 35 % (2 MB)
103 19:22:15.481042 progress 40 % (3 MB)
104 19:22:15.507008 progress 45 % (3 MB)
105 19:22:15.534822 progress 50 % (4 MB)
106 19:22:15.560175 progress 55 % (4 MB)
107 19:22:15.588615 progress 60 % (4 MB)
108 19:22:15.614202 progress 65 % (5 MB)
109 19:22:15.640537 progress 70 % (5 MB)
110 19:22:15.666475 progress 75 % (6 MB)
111 19:22:15.693501 progress 80 % (6 MB)
112 19:22:15.721114 progress 85 % (7 MB)
113 19:22:15.751268 progress 90 % (7 MB)
114 19:22:15.782151 progress 95 % (7 MB)
115 19:22:15.809889 progress 100 % (8 MB)
116 19:22:15.815542 8 MB downloaded in 0.79 s (10.43 MB/s)
117 19:22:15.815900 end: 1.4.1 http-download (duration 00:00:01) [common]
119 19:22:15.816317 end: 1.4 download-retry (duration 00:00:01) [common]
120 19:22:15.816458 start: 1.5 prepare-tftp-overlay (timeout 00:09:58) [common]
121 19:22:15.816613 start: 1.5.1 extract-nfsrootfs (timeout 00:09:58) [common]
122 19:22:15.816740 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 19:22:15.816880 start: 1.5.2 lava-overlay (timeout 00:09:58) [common]
124 19:22:15.817186 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/13420342/lava-overlay-9rfeuecd
125 19:22:15.817383 makedir: /var/lib/lava/dispatcher/tmp/13420342/lava-overlay-9rfeuecd/lava-13420342/bin
126 19:22:15.817547 makedir: /var/lib/lava/dispatcher/tmp/13420342/lava-overlay-9rfeuecd/lava-13420342/tests
127 19:22:15.817701 makedir: /var/lib/lava/dispatcher/tmp/13420342/lava-overlay-9rfeuecd/lava-13420342/results
128 19:22:15.817871 Creating /var/lib/lava/dispatcher/tmp/13420342/lava-overlay-9rfeuecd/lava-13420342/bin/lava-add-keys
129 19:22:15.818084 Creating /var/lib/lava/dispatcher/tmp/13420342/lava-overlay-9rfeuecd/lava-13420342/bin/lava-add-sources
130 19:22:15.818271 Creating /var/lib/lava/dispatcher/tmp/13420342/lava-overlay-9rfeuecd/lava-13420342/bin/lava-background-process-start
131 19:22:15.818459 Creating /var/lib/lava/dispatcher/tmp/13420342/lava-overlay-9rfeuecd/lava-13420342/bin/lava-background-process-stop
132 19:22:15.818650 Creating /var/lib/lava/dispatcher/tmp/13420342/lava-overlay-9rfeuecd/lava-13420342/bin/lava-common-functions
133 19:22:15.818834 Creating /var/lib/lava/dispatcher/tmp/13420342/lava-overlay-9rfeuecd/lava-13420342/bin/lava-echo-ipv4
134 19:22:15.819026 Creating /var/lib/lava/dispatcher/tmp/13420342/lava-overlay-9rfeuecd/lava-13420342/bin/lava-install-packages
135 19:22:15.819212 Creating /var/lib/lava/dispatcher/tmp/13420342/lava-overlay-9rfeuecd/lava-13420342/bin/lava-installed-packages
136 19:22:15.819395 Creating /var/lib/lava/dispatcher/tmp/13420342/lava-overlay-9rfeuecd/lava-13420342/bin/lava-os-build
137 19:22:15.819582 Creating /var/lib/lava/dispatcher/tmp/13420342/lava-overlay-9rfeuecd/lava-13420342/bin/lava-probe-channel
138 19:22:15.819764 Creating /var/lib/lava/dispatcher/tmp/13420342/lava-overlay-9rfeuecd/lava-13420342/bin/lava-probe-ip
139 19:22:15.819951 Creating /var/lib/lava/dispatcher/tmp/13420342/lava-overlay-9rfeuecd/lava-13420342/bin/lava-target-ip
140 19:22:15.820138 Creating /var/lib/lava/dispatcher/tmp/13420342/lava-overlay-9rfeuecd/lava-13420342/bin/lava-target-mac
141 19:22:15.820327 Creating /var/lib/lava/dispatcher/tmp/13420342/lava-overlay-9rfeuecd/lava-13420342/bin/lava-target-storage
142 19:22:15.820515 Creating /var/lib/lava/dispatcher/tmp/13420342/lava-overlay-9rfeuecd/lava-13420342/bin/lava-test-case
143 19:22:15.820702 Creating /var/lib/lava/dispatcher/tmp/13420342/lava-overlay-9rfeuecd/lava-13420342/bin/lava-test-event
144 19:22:15.820889 Creating /var/lib/lava/dispatcher/tmp/13420342/lava-overlay-9rfeuecd/lava-13420342/bin/lava-test-feedback
145 19:22:15.821079 Creating /var/lib/lava/dispatcher/tmp/13420342/lava-overlay-9rfeuecd/lava-13420342/bin/lava-test-raise
146 19:22:15.821268 Creating /var/lib/lava/dispatcher/tmp/13420342/lava-overlay-9rfeuecd/lava-13420342/bin/lava-test-reference
147 19:22:15.821457 Creating /var/lib/lava/dispatcher/tmp/13420342/lava-overlay-9rfeuecd/lava-13420342/bin/lava-test-runner
148 19:22:15.821653 Creating /var/lib/lava/dispatcher/tmp/13420342/lava-overlay-9rfeuecd/lava-13420342/bin/lava-test-set
149 19:22:15.821845 Creating /var/lib/lava/dispatcher/tmp/13420342/lava-overlay-9rfeuecd/lava-13420342/bin/lava-test-shell
150 19:22:15.822035 Updating /var/lib/lava/dispatcher/tmp/13420342/lava-overlay-9rfeuecd/lava-13420342/bin/lava-install-packages (oe)
151 19:22:15.822255 Updating /var/lib/lava/dispatcher/tmp/13420342/lava-overlay-9rfeuecd/lava-13420342/bin/lava-installed-packages (oe)
152 19:22:15.822437 Creating /var/lib/lava/dispatcher/tmp/13420342/lava-overlay-9rfeuecd/lava-13420342/environment
153 19:22:15.822588 LAVA metadata
154 19:22:15.822705 - LAVA_JOB_ID=13420342
155 19:22:15.822810 - LAVA_DISPATCHER_IP=192.168.201.1
156 19:22:15.822972 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:58) [common]
157 19:22:15.823079 skipped lava-vland-overlay
158 19:22:15.823199 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 19:22:15.823326 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:58) [common]
160 19:22:15.823430 skipped lava-multinode-overlay
161 19:22:15.823565 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 19:22:15.823719 start: 1.5.2.3 test-definition (timeout 00:09:58) [common]
163 19:22:15.823843 Loading test definitions
164 19:22:15.823990 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:58) [common]
165 19:22:15.824105 Using /lava-13420342 at stage 0
166 19:22:15.824577 uuid=13420342_1.5.2.3.1 testdef=None
167 19:22:15.824712 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 19:22:15.824844 start: 1.5.2.3.2 test-overlay (timeout 00:09:58) [common]
169 19:22:15.825625 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 19:22:15.825986 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:58) [common]
172 19:22:15.826940 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 19:22:15.827320 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:58) [common]
175 19:22:15.828231 runner path: /var/lib/lava/dispatcher/tmp/13420342/lava-overlay-9rfeuecd/lava-13420342/0/tests/0_cros-ec test_uuid 13420342_1.5.2.3.1
176 19:22:15.828453 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 19:22:15.828788 Creating lava-test-runner.conf files
179 19:22:15.828891 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/13420342/lava-overlay-9rfeuecd/lava-13420342/0 for stage 0
180 19:22:15.829026 - 0_cros-ec
181 19:22:15.829170 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 19:22:15.829303 start: 1.5.2.4 compress-overlay (timeout 00:09:58) [common]
183 19:22:15.839871 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 19:22:15.840063 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:58) [common]
185 19:22:15.840198 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 19:22:15.840331 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 19:22:15.840465 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:58) [common]
188 19:22:17.114479 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 19:22:17.114969 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
190 19:22:17.115134 extracting modules file /var/lib/lava/dispatcher/tmp/13420342/tftp-deploy-9up0a6oe/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13420342/extract-overlay-ramdisk-_rqmcijd/ramdisk
191 19:22:17.395966 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 19:22:17.396146 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 19:22:17.396241 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13420342/compress-overlay-6k9x0q_s/overlay-1.5.2.4.tar.gz to ramdisk
194 19:22:17.396313 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13420342/compress-overlay-6k9x0q_s/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/13420342/extract-overlay-ramdisk-_rqmcijd/ramdisk
195 19:22:17.403034 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 19:22:17.403155 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 19:22:17.403247 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 19:22:17.403337 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 19:22:17.403413 Building ramdisk /var/lib/lava/dispatcher/tmp/13420342/extract-overlay-ramdisk-_rqmcijd/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/13420342/extract-overlay-ramdisk-_rqmcijd/ramdisk
200 19:22:18.271886 >> 336160 blocks
201 19:22:23.564711 rename /var/lib/lava/dispatcher/tmp/13420342/extract-overlay-ramdisk-_rqmcijd/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/13420342/tftp-deploy-9up0a6oe/ramdisk/ramdisk.cpio.gz
202 19:22:23.565218 end: 1.5.7 compress-ramdisk (duration 00:00:06) [common]
203 19:22:23.565398 start: 1.5.8 prepare-kernel (timeout 00:09:50) [common]
204 19:22:23.565548 start: 1.5.8.1 prepare-fit (timeout 00:09:50) [common]
205 19:22:23.565697 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/13420342/tftp-deploy-9up0a6oe/kernel/Image'
206 19:22:37.592644 Returned 0 in 14 seconds
207 19:22:37.693301 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/13420342/tftp-deploy-9up0a6oe/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/13420342/tftp-deploy-9up0a6oe/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/13420342/tftp-deploy-9up0a6oe/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/13420342/tftp-deploy-9up0a6oe/kernel/image.itb
208 19:22:38.449588 output: FIT description: Kernel Image image with one or more FDT blobs
209 19:22:38.449957 output: Created: Thu Apr 18 20:22:38 2024
210 19:22:38.450033 output: Image 0 (kernel-1)
211 19:22:38.450095 output: Description:
212 19:22:38.450158 output: Created: Thu Apr 18 20:22:38 2024
213 19:22:38.450218 output: Type: Kernel Image
214 19:22:38.450274 output: Compression: lzma compressed
215 19:22:38.450330 output: Data Size: 12910355 Bytes = 12607.77 KiB = 12.31 MiB
216 19:22:38.450386 output: Architecture: AArch64
217 19:22:38.450440 output: OS: Linux
218 19:22:38.450495 output: Load Address: 0x00000000
219 19:22:38.450552 output: Entry Point: 0x00000000
220 19:22:38.450605 output: Hash algo: crc32
221 19:22:38.450661 output: Hash value: bbac8b0b
222 19:22:38.450717 output: Image 1 (fdt-1)
223 19:22:38.450773 output: Description: mt8192-asurada-spherion-r0
224 19:22:38.450825 output: Created: Thu Apr 18 20:22:38 2024
225 19:22:38.450876 output: Type: Flat Device Tree
226 19:22:38.450927 output: Compression: uncompressed
227 19:22:38.450978 output: Data Size: 47230 Bytes = 46.12 KiB = 0.05 MiB
228 19:22:38.451029 output: Architecture: AArch64
229 19:22:38.451079 output: Hash algo: crc32
230 19:22:38.451130 output: Hash value: 4bf0d1ac
231 19:22:38.451180 output: Image 2 (ramdisk-1)
232 19:22:38.451235 output: Description: unavailable
233 19:22:38.451287 output: Created: Thu Apr 18 20:22:38 2024
234 19:22:38.451340 output: Type: RAMDisk Image
235 19:22:38.451391 output: Compression: Unknown Compression
236 19:22:38.451442 output: Data Size: 52175825 Bytes = 50952.95 KiB = 49.76 MiB
237 19:22:38.451493 output: Architecture: AArch64
238 19:22:38.451543 output: OS: Linux
239 19:22:38.451594 output: Load Address: unavailable
240 19:22:38.451645 output: Entry Point: unavailable
241 19:22:38.451696 output: Hash algo: crc32
242 19:22:38.451746 output: Hash value: acfcb1e9
243 19:22:38.451797 output: Default Configuration: 'conf-1'
244 19:22:38.451847 output: Configuration 0 (conf-1)
245 19:22:38.451898 output: Description: mt8192-asurada-spherion-r0
246 19:22:38.451949 output: Kernel: kernel-1
247 19:22:38.452000 output: Init Ramdisk: ramdisk-1
248 19:22:38.452050 output: FDT: fdt-1
249 19:22:38.452101 output: Loadables: kernel-1
250 19:22:38.452151 output:
251 19:22:38.452347 end: 1.5.8.1 prepare-fit (duration 00:00:15) [common]
252 19:22:38.452446 end: 1.5.8 prepare-kernel (duration 00:00:15) [common]
253 19:22:38.452550 end: 1.5 prepare-tftp-overlay (duration 00:00:23) [common]
254 19:22:38.452651 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:36) [common]
255 19:22:38.452730 No LXC device requested
256 19:22:38.452807 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 19:22:38.452891 start: 1.7 deploy-device-env (timeout 00:09:36) [common]
258 19:22:38.452965 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 19:22:38.453031 Checking files for TFTP limit of 4294967296 bytes.
260 19:22:38.453565 end: 1 tftp-deploy (duration 00:00:24) [common]
261 19:22:38.453666 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 19:22:38.453758 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 19:22:38.453884 substitutions:
264 19:22:38.453950 - {DTB}: 13420342/tftp-deploy-9up0a6oe/dtb/mt8192-asurada-spherion-r0.dtb
265 19:22:38.454013 - {INITRD}: 13420342/tftp-deploy-9up0a6oe/ramdisk/ramdisk.cpio.gz
266 19:22:38.454072 - {KERNEL}: 13420342/tftp-deploy-9up0a6oe/kernel/Image
267 19:22:38.454132 - {LAVA_MAC}: None
268 19:22:38.454190 - {PRESEED_CONFIG}: None
269 19:22:38.454245 - {PRESEED_LOCAL}: None
270 19:22:38.454299 - {RAMDISK}: 13420342/tftp-deploy-9up0a6oe/ramdisk/ramdisk.cpio.gz
271 19:22:38.454353 - {ROOT_PART}: None
272 19:22:38.454406 - {ROOT}: None
273 19:22:38.454459 - {SERVER_IP}: 192.168.201.1
274 19:22:38.454511 - {TEE}: None
275 19:22:38.454568 Parsed boot commands:
276 19:22:38.454624 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 19:22:38.454796 Parsed boot commands: tftpboot 192.168.201.1 13420342/tftp-deploy-9up0a6oe/kernel/image.itb 13420342/tftp-deploy-9up0a6oe/kernel/cmdline
278 19:22:38.454883 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 19:22:38.454969 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 19:22:38.455057 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 19:22:38.455141 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 19:22:38.455209 Not connected, no need to disconnect.
283 19:22:38.455280 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 19:22:38.455360 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 19:22:38.455425 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
286 19:22:38.459264 Setting prompt string to ['lava-test: # ']
287 19:22:38.459626 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 19:22:38.459735 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 19:22:38.459833 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 19:22:38.459921 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 19:22:38.460180 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
292 19:22:43.595938 >> Command sent successfully.
293 19:22:43.598365 Returned 0 in 5 seconds
294 19:22:43.698761 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 19:22:43.699185 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 19:22:43.699314 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 19:22:43.699432 Setting prompt string to 'Starting depthcharge on Spherion...'
299 19:22:43.699528 Changing prompt to 'Starting depthcharge on Spherion...'
300 19:22:43.699608 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 19:22:43.699883 [Enter `^Ec?' for help]
302 19:22:44.101706
303 19:22:44.101854
304 19:22:44.101931 F0: 102B 0000
305 19:22:44.101997
306 19:22:44.102057 F3: 1001 0000 [0200]
307 19:22:44.104630
308 19:22:44.104728 F3: 1001 0000
309 19:22:44.104818
310 19:22:44.104904 F7: 102D 0000
311 19:22:44.104989
312 19:22:44.108146 F1: 0000 0000
313 19:22:44.108241
314 19:22:44.108331 V0: 0000 0000 [0001]
315 19:22:44.108420
316 19:22:44.111739 00: 0007 8000
317 19:22:44.111838
318 19:22:44.111923 01: 0000 0000
319 19:22:44.112009
320 19:22:44.114653 BP: 0C00 0209 [0000]
321 19:22:44.114756
322 19:22:44.114815 G0: 1182 0000
323 19:22:44.114871
324 19:22:44.117968 EC: 0000 0021 [4000]
325 19:22:44.118064
326 19:22:44.118151 S7: 0000 0000 [0000]
327 19:22:44.118235
328 19:22:44.121160 CC: 0000 0000 [0001]
329 19:22:44.121272
330 19:22:44.121364 T0: 0000 0040 [010F]
331 19:22:44.121481
332 19:22:44.124379 Jump to BL
333 19:22:44.124476
334 19:22:44.148311
335 19:22:44.148482
336 19:22:44.148577
337 19:22:44.158188 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 19:22:44.161336 ARM64: Exception handlers installed.
339 19:22:44.161470 ARM64: Testing exception
340 19:22:44.164955 ARM64: Done test exception
341 19:22:44.171515 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 19:22:44.181962 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 19:22:44.188445 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 19:22:44.199005 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 19:22:44.206136 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 19:22:44.216304 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 19:22:44.226075 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 19:22:44.232622 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 19:22:44.251157 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 19:22:44.254672 WDT: Last reset was cold boot
351 19:22:44.258077 SPI1(PAD0) initialized at 2873684 Hz
352 19:22:44.261609 SPI5(PAD0) initialized at 992727 Hz
353 19:22:44.264931 VBOOT: Loading verstage.
354 19:22:44.271425 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 19:22:44.274814 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 19:22:44.277969 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 19:22:44.281431 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 19:22:44.289130 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 19:22:44.295413 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 19:22:44.306607 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
361 19:22:44.306743
362 19:22:44.306813
363 19:22:44.316656 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 19:22:44.319646 ARM64: Exception handlers installed.
365 19:22:44.323131 ARM64: Testing exception
366 19:22:44.323257 ARM64: Done test exception
367 19:22:44.329687 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 19:22:44.333110 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 19:22:44.347065 Probing TPM: . done!
370 19:22:44.347208 TPM ready after 0 ms
371 19:22:44.354263 Connected to device vid:did:rid of 1ae0:0028:00
372 19:22:44.360915 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 19:22:44.451190 Initialized TPM device CR50 revision 0
374 19:22:44.461830 tlcl_send_startup: Startup return code is 0
375 19:22:44.470364 TPM: setup succeeded
376 19:22:44.487518 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 19:22:44.494355 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 19:22:44.506108 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 19:22:44.515755 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 19:22:44.518998 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 19:22:44.522909 in-header: 03 07 00 00 08 00 00 00
382 19:22:44.526754 in-data: aa e4 47 04 13 02 00 00
383 19:22:44.529898 Chrome EC: UHEPI supported
384 19:22:44.536674 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 19:22:44.539903 in-header: 03 ad 00 00 08 00 00 00
386 19:22:44.543318 in-data: 00 20 20 08 00 00 00 00
387 19:22:44.543414 Phase 1
388 19:22:44.549551 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 19:22:44.553148 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 19:22:44.560174 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 19:22:44.563741 Recovery requested (1009000e)
392 19:22:44.567888 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 19:22:44.575870 tlcl_extend: response is 0
394 19:22:44.585520 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 19:22:44.591325 tlcl_extend: response is 0
396 19:22:44.598334 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 19:22:44.618329 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 19:22:44.625006 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 19:22:44.625139
400 19:22:44.625206
401 19:22:44.635195 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 19:22:44.637973 ARM64: Exception handlers installed.
403 19:22:44.641478 ARM64: Testing exception
404 19:22:44.641617 ARM64: Done test exception
405 19:22:44.663305 pmic_efuse_setting: Set efuses in 11 msecs
406 19:22:44.667038 pmwrap_interface_init: Select PMIF_VLD_RDY
407 19:22:44.673676 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 19:22:44.676944 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 19:22:44.683624 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 19:22:44.686775 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 19:22:44.693199 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 19:22:44.696867 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 19:22:44.700196 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 19:22:44.706924 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 19:22:44.709924 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 19:22:44.717039 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 19:22:44.720491 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 19:22:44.723542 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 19:22:44.730370 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 19:22:44.737048 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 19:22:44.740025 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 19:22:44.746880 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 19:22:44.753339 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 19:22:44.756668 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 19:22:44.763457 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 19:22:44.770457 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 19:22:44.773924 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 19:22:44.780227 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 19:22:44.786962 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 19:22:44.790105 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 19:22:44.796672 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 19:22:44.803585 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 19:22:44.806990 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 19:22:44.813333 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 19:22:44.816864 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 19:22:44.823467 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 19:22:44.827026 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 19:22:44.833415 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 19:22:44.836559 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 19:22:44.843416 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 19:22:44.846394 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 19:22:44.853304 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 19:22:44.856766 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 19:22:44.863206 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 19:22:44.866864 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 19:22:44.870397 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 19:22:44.876735 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 19:22:44.880070 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 19:22:44.883687 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 19:22:44.890040 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 19:22:44.893489 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 19:22:44.897190 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 19:22:44.900400 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 19:22:44.907261 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 19:22:44.910218 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 19:22:44.913370 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 19:22:44.916645 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 19:22:44.926914 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 19:22:44.933425 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 19:22:44.940399 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 19:22:44.946800 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 19:22:44.956784 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 19:22:44.960423 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 19:22:44.963391 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 19:22:44.970396 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 19:22:44.976683 [RTC]rtc_enable_dcxo,68: con=0x406, osc32con=0xde6f, sec=0x2e
467 19:22:44.983515 [RTC]rtc_check_state,173: con=406, pwrkey1=a357, pwrkey2=67d2
468 19:22:44.986514 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
469 19:22:44.990179 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 19:22:45.001148 [RTC]rtc_get_frequency_meter,154: input=15, output=794
471 19:22:45.004049 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
472 19:22:45.010509 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
473 19:22:45.014042 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
474 19:22:45.017615 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
475 19:22:45.020421 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
476 19:22:45.024125 ADC[4]: Raw value=897040 ID=7
477 19:22:45.027341 ADC[3]: Raw value=213440 ID=1
478 19:22:45.030644 RAM Code: 0x71
479 19:22:45.034016 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
480 19:22:45.037345 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
481 19:22:45.047685 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
482 19:22:45.053737 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
483 19:22:45.057436 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
484 19:22:45.060783 in-header: 03 07 00 00 08 00 00 00
485 19:22:45.064116 in-data: aa e4 47 04 13 02 00 00
486 19:22:45.067063 Chrome EC: UHEPI supported
487 19:22:45.073595 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
488 19:22:45.077053 in-header: 03 ed 00 00 08 00 00 00
489 19:22:45.080443 in-data: 80 20 60 08 00 00 00 00
490 19:22:45.084079 MRC: failed to locate region type 0.
491 19:22:45.090750 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
492 19:22:45.090904 DRAM-K: Running full calibration
493 19:22:45.097569 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
494 19:22:45.100387 header.status = 0x0
495 19:22:45.104018 header.version = 0x6 (expected: 0x6)
496 19:22:45.106992 header.size = 0xd00 (expected: 0xd00)
497 19:22:45.107104 header.flags = 0x0
498 19:22:45.113944 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
499 19:22:45.132653 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
500 19:22:45.139793 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
501 19:22:45.143507 dram_init: ddr_geometry: 2
502 19:22:45.143687 [EMI] MDL number = 2
503 19:22:45.146392 [EMI] Get MDL freq = 0
504 19:22:45.149811 dram_init: ddr_type: 0
505 19:22:45.149942 is_discrete_lpddr4: 1
506 19:22:45.153868 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
507 19:22:45.153965
508 19:22:45.154032
509 19:22:45.157053 [Bian_co] ETT version 0.0.0.1
510 19:22:45.161155 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
511 19:22:45.161284
512 19:22:45.164522 dramc_set_vcore_voltage set vcore to 650000
513 19:22:45.168102 Read voltage for 800, 4
514 19:22:45.168243 Vio18 = 0
515 19:22:45.171465 Vcore = 650000
516 19:22:45.171606 Vdram = 0
517 19:22:45.171743 Vddq = 0
518 19:22:45.171863 Vmddr = 0
519 19:22:45.175348 dram_init: config_dvfs: 1
520 19:22:45.178636 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
521 19:22:45.185358 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
522 19:22:45.188849 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
523 19:22:45.192192 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
524 19:22:45.195551 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
525 19:22:45.201994 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
526 19:22:45.202123 MEM_TYPE=3, freq_sel=18
527 19:22:45.205149 sv_algorithm_assistance_LP4_1600
528 19:22:45.208616 ============ PULL DRAM RESETB DOWN ============
529 19:22:45.215076 ========== PULL DRAM RESETB DOWN end =========
530 19:22:45.218708 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
531 19:22:45.222115 ===================================
532 19:22:45.225122 LPDDR4 DRAM CONFIGURATION
533 19:22:45.228630 ===================================
534 19:22:45.228744 EX_ROW_EN[0] = 0x0
535 19:22:45.232041 EX_ROW_EN[1] = 0x0
536 19:22:45.232128 LP4Y_EN = 0x0
537 19:22:45.235582 WORK_FSP = 0x0
538 19:22:45.235673 WL = 0x2
539 19:22:45.238560 RL = 0x2
540 19:22:45.238646 BL = 0x2
541 19:22:45.242173 RPST = 0x0
542 19:22:45.242261 RD_PRE = 0x0
543 19:22:45.245652 WR_PRE = 0x1
544 19:22:45.245746 WR_PST = 0x0
545 19:22:45.249052 DBI_WR = 0x0
546 19:22:45.251998 DBI_RD = 0x0
547 19:22:45.252098 OTF = 0x1
548 19:22:45.255529 ===================================
549 19:22:45.258983 ===================================
550 19:22:45.259083 ANA top config
551 19:22:45.261995 ===================================
552 19:22:45.265789 DLL_ASYNC_EN = 0
553 19:22:45.268668 ALL_SLAVE_EN = 1
554 19:22:45.272355 NEW_RANK_MODE = 1
555 19:22:45.272466 DLL_IDLE_MODE = 1
556 19:22:45.275355 LP45_APHY_COMB_EN = 1
557 19:22:45.278900 TX_ODT_DIS = 1
558 19:22:45.282279 NEW_8X_MODE = 1
559 19:22:45.285729 ===================================
560 19:22:45.288857 ===================================
561 19:22:45.292138 data_rate = 1600
562 19:22:45.295500 CKR = 1
563 19:22:45.295623 DQ_P2S_RATIO = 8
564 19:22:45.298737 ===================================
565 19:22:45.302092 CA_P2S_RATIO = 8
566 19:22:45.305492 DQ_CA_OPEN = 0
567 19:22:45.308884 DQ_SEMI_OPEN = 0
568 19:22:45.312157 CA_SEMI_OPEN = 0
569 19:22:45.312256 CA_FULL_RATE = 0
570 19:22:45.315374 DQ_CKDIV4_EN = 1
571 19:22:45.318778 CA_CKDIV4_EN = 1
572 19:22:45.321991 CA_PREDIV_EN = 0
573 19:22:45.325314 PH8_DLY = 0
574 19:22:45.328893 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
575 19:22:45.329019 DQ_AAMCK_DIV = 4
576 19:22:45.332490 CA_AAMCK_DIV = 4
577 19:22:45.335401 CA_ADMCK_DIV = 4
578 19:22:45.338877 DQ_TRACK_CA_EN = 0
579 19:22:45.341871 CA_PICK = 800
580 19:22:45.345303 CA_MCKIO = 800
581 19:22:45.348842 MCKIO_SEMI = 0
582 19:22:45.348962 PLL_FREQ = 3068
583 19:22:45.351910 DQ_UI_PI_RATIO = 32
584 19:22:45.355318 CA_UI_PI_RATIO = 0
585 19:22:45.358740 ===================================
586 19:22:45.362455 ===================================
587 19:22:45.365283 memory_type:LPDDR4
588 19:22:45.365391 GP_NUM : 10
589 19:22:45.368797 SRAM_EN : 1
590 19:22:45.371798 MD32_EN : 0
591 19:22:45.374936 ===================================
592 19:22:45.375049 [ANA_INIT] >>>>>>>>>>>>>>
593 19:22:45.378514 <<<<<< [CONFIGURE PHASE]: ANA_TX
594 19:22:45.382158 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
595 19:22:45.385960 ===================================
596 19:22:45.389444 data_rate = 1600,PCW = 0X7600
597 19:22:45.392948 ===================================
598 19:22:45.396811 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
599 19:22:45.400429 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
600 19:22:45.407787 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
601 19:22:45.411576 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
602 19:22:45.415578 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
603 19:22:45.418916 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
604 19:22:45.419045 [ANA_INIT] flow start
605 19:22:45.423004 [ANA_INIT] PLL >>>>>>>>
606 19:22:45.426174 [ANA_INIT] PLL <<<<<<<<
607 19:22:45.426295 [ANA_INIT] MIDPI >>>>>>>>
608 19:22:45.429706 [ANA_INIT] MIDPI <<<<<<<<
609 19:22:45.432630 [ANA_INIT] DLL >>>>>>>>
610 19:22:45.432745 [ANA_INIT] flow end
611 19:22:45.436194 ============ LP4 DIFF to SE enter ============
612 19:22:45.442660 ============ LP4 DIFF to SE exit ============
613 19:22:45.442775 [ANA_INIT] <<<<<<<<<<<<<
614 19:22:45.446338 [Flow] Enable top DCM control >>>>>
615 19:22:45.449624 [Flow] Enable top DCM control <<<<<
616 19:22:45.453107 Enable DLL master slave shuffle
617 19:22:45.459460 ==============================================================
618 19:22:45.459602 Gating Mode config
619 19:22:45.465927 ==============================================================
620 19:22:45.469456 Config description:
621 19:22:45.476571 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
622 19:22:45.484008 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
623 19:22:45.490983 SELPH_MODE 0: By rank 1: By Phase
624 19:22:45.494525 ==============================================================
625 19:22:45.498088 GAT_TRACK_EN = 1
626 19:22:45.501399 RX_GATING_MODE = 2
627 19:22:45.504930 RX_GATING_TRACK_MODE = 2
628 19:22:45.509102 SELPH_MODE = 1
629 19:22:45.509208 PICG_EARLY_EN = 1
630 19:22:45.513043 VALID_LAT_VALUE = 1
631 19:22:45.519939 ==============================================================
632 19:22:45.524027 Enter into Gating configuration >>>>
633 19:22:45.524145 Exit from Gating configuration <<<<
634 19:22:45.527465 Enter into DVFS_PRE_config >>>>>
635 19:22:45.538651 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
636 19:22:45.542270 Exit from DVFS_PRE_config <<<<<
637 19:22:45.546147 Enter into PICG configuration >>>>
638 19:22:45.549836 Exit from PICG configuration <<<<
639 19:22:45.553251 [RX_INPUT] configuration >>>>>
640 19:22:45.553358 [RX_INPUT] configuration <<<<<
641 19:22:45.560898 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
642 19:22:45.564794 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
643 19:22:45.572587 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
644 19:22:45.576627 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
645 19:22:45.584278 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
646 19:22:45.590484 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
647 19:22:45.594096 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
648 19:22:45.597723 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
649 19:22:45.600733 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
650 19:22:45.607570 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
651 19:22:45.611173 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
652 19:22:45.614643 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
653 19:22:45.617858 ===================================
654 19:22:45.620817 LPDDR4 DRAM CONFIGURATION
655 19:22:45.624386 ===================================
656 19:22:45.624495 EX_ROW_EN[0] = 0x0
657 19:22:45.627936 EX_ROW_EN[1] = 0x0
658 19:22:45.628038 LP4Y_EN = 0x0
659 19:22:45.630956 WORK_FSP = 0x0
660 19:22:45.631058 WL = 0x2
661 19:22:45.634308 RL = 0x2
662 19:22:45.637238 BL = 0x2
663 19:22:45.637339 RPST = 0x0
664 19:22:45.640723 RD_PRE = 0x0
665 19:22:45.640825 WR_PRE = 0x1
666 19:22:45.644305 WR_PST = 0x0
667 19:22:45.644424 DBI_WR = 0x0
668 19:22:45.647256 DBI_RD = 0x0
669 19:22:45.647358 OTF = 0x1
670 19:22:45.650879 ===================================
671 19:22:45.654453 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
672 19:22:45.660615 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
673 19:22:45.664122 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
674 19:22:45.667358 ===================================
675 19:22:45.670847 LPDDR4 DRAM CONFIGURATION
676 19:22:45.673901 ===================================
677 19:22:45.673982 EX_ROW_EN[0] = 0x10
678 19:22:45.677559 EX_ROW_EN[1] = 0x0
679 19:22:45.677651 LP4Y_EN = 0x0
680 19:22:45.680991 WORK_FSP = 0x0
681 19:22:45.681082 WL = 0x2
682 19:22:45.684184 RL = 0x2
683 19:22:45.684278 BL = 0x2
684 19:22:45.687455 RPST = 0x0
685 19:22:45.687536 RD_PRE = 0x0
686 19:22:45.690876 WR_PRE = 0x1
687 19:22:45.690957 WR_PST = 0x0
688 19:22:45.694045 DBI_WR = 0x0
689 19:22:45.697348 DBI_RD = 0x0
690 19:22:45.697430 OTF = 0x1
691 19:22:45.700820 ===================================
692 19:22:45.708181 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
693 19:22:45.711599 nWR fixed to 40
694 19:22:45.711685 [ModeRegInit_LP4] CH0 RK0
695 19:22:45.715093 [ModeRegInit_LP4] CH0 RK1
696 19:22:45.719084 [ModeRegInit_LP4] CH1 RK0
697 19:22:45.719165 [ModeRegInit_LP4] CH1 RK1
698 19:22:45.722370 match AC timing 13
699 19:22:45.726466 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
700 19:22:45.730093 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
701 19:22:45.733745 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
702 19:22:45.741308 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
703 19:22:45.744480 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
704 19:22:45.744608 [EMI DOE] emi_dcm 0
705 19:22:45.751543 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
706 19:22:45.751658 ==
707 19:22:45.755623 Dram Type= 6, Freq= 0, CH_0, rank 0
708 19:22:45.759334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
709 19:22:45.759440 ==
710 19:22:45.762686 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
711 19:22:45.769104 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
712 19:22:45.778775 [CA 0] Center 38 (7~69) winsize 63
713 19:22:45.781705 [CA 1] Center 37 (7~68) winsize 62
714 19:22:45.785332 [CA 2] Center 35 (5~66) winsize 62
715 19:22:45.788226 [CA 3] Center 35 (5~66) winsize 62
716 19:22:45.791625 [CA 4] Center 34 (4~65) winsize 62
717 19:22:45.795177 [CA 5] Center 34 (4~65) winsize 62
718 19:22:45.795276
719 19:22:45.798665 [CmdBusTrainingLP45] Vref(ca) range 1: 32
720 19:22:45.798763
721 19:22:45.801634 [CATrainingPosCal] consider 1 rank data
722 19:22:45.804842 u2DelayCellTimex100 = 270/100 ps
723 19:22:45.808452 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
724 19:22:45.811883 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
725 19:22:45.818685 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
726 19:22:45.821575 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
727 19:22:45.825110 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
728 19:22:45.828421 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
729 19:22:45.828521
730 19:22:45.831640 CA PerBit enable=1, Macro0, CA PI delay=34
731 19:22:45.831738
732 19:22:45.835222 [CBTSetCACLKResult] CA Dly = 34
733 19:22:45.835323 CS Dly: 5 (0~36)
734 19:22:45.835412 ==
735 19:22:45.838425 Dram Type= 6, Freq= 0, CH_0, rank 1
736 19:22:45.845257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
737 19:22:45.845365 ==
738 19:22:45.848709 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
739 19:22:45.855176 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
740 19:22:45.864538 [CA 0] Center 38 (7~69) winsize 63
741 19:22:45.867943 [CA 1] Center 38 (7~69) winsize 63
742 19:22:45.871429 [CA 2] Center 35 (5~66) winsize 62
743 19:22:45.874415 [CA 3] Center 35 (5~66) winsize 62
744 19:22:45.877842 [CA 4] Center 34 (4~65) winsize 62
745 19:22:45.881315 [CA 5] Center 34 (4~65) winsize 62
746 19:22:45.881414
747 19:22:45.884887 [CmdBusTrainingLP45] Vref(ca) range 1: 32
748 19:22:45.884994
749 19:22:45.888326 [CATrainingPosCal] consider 2 rank data
750 19:22:45.891309 u2DelayCellTimex100 = 270/100 ps
751 19:22:45.894858 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
752 19:22:45.897862 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
753 19:22:45.904679 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
754 19:22:45.908144 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
755 19:22:45.911133 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
756 19:22:45.914593 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
757 19:22:45.914675
758 19:22:45.917952 CA PerBit enable=1, Macro0, CA PI delay=34
759 19:22:45.918031
760 19:22:45.921555 [CBTSetCACLKResult] CA Dly = 34
761 19:22:45.921656 CS Dly: 6 (0~38)
762 19:22:45.921750
763 19:22:45.924534 ----->DramcWriteLeveling(PI) begin...
764 19:22:45.928301 ==
765 19:22:45.928411 Dram Type= 6, Freq= 0, CH_0, rank 0
766 19:22:45.934777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
767 19:22:45.934895 ==
768 19:22:45.938122 Write leveling (Byte 0): 34 => 34
769 19:22:45.941472 Write leveling (Byte 1): 32 => 32
770 19:22:45.944608 DramcWriteLeveling(PI) end<-----
771 19:22:45.944711
772 19:22:45.944804 ==
773 19:22:45.947916 Dram Type= 6, Freq= 0, CH_0, rank 0
774 19:22:45.951160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
775 19:22:45.951271 ==
776 19:22:45.954444 [Gating] SW mode calibration
777 19:22:45.961347 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
778 19:22:45.964612 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
779 19:22:45.971153 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
780 19:22:45.974627 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
781 19:22:45.978213 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
782 19:22:45.984367 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
783 19:22:45.987713 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
784 19:22:45.991425 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
785 19:22:45.997903 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
786 19:22:46.001499 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 19:22:46.004586 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 19:22:46.010929 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 19:22:46.014481 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 19:22:46.017978 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 19:22:46.024404 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 19:22:46.028031 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 19:22:46.031064 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 19:22:46.037973 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 19:22:46.041413 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 19:22:46.044892 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
797 19:22:46.048917 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
798 19:22:46.055910 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
799 19:22:46.059428 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 19:22:46.063867 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 19:22:46.067594 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 19:22:46.071089 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 19:22:46.075030 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 19:22:46.078873 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 19:22:46.085916 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 19:22:46.089594 0 9 12 | B1->B0 | 2626 3131 | 0 0 | (0 0) (0 0)
807 19:22:46.093399 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
808 19:22:46.097005 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
809 19:22:46.101167 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
810 19:22:46.108154 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
811 19:22:46.112292 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 19:22:46.115812 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 19:22:46.119421 0 10 8 | B1->B0 | 3232 2f2f | 0 1 | (0 0) (1 0)
814 19:22:46.123342 0 10 12 | B1->B0 | 2f2f 2424 | 0 0 | (0 1) (0 0)
815 19:22:46.130552 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 19:22:46.134204 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 19:22:46.137344 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 19:22:46.140791 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 19:22:46.147675 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 19:22:46.151127 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 19:22:46.154456 0 11 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
822 19:22:46.161082 0 11 12 | B1->B0 | 3434 4040 | 1 0 | (0 0) (0 0)
823 19:22:46.164012 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
824 19:22:46.167616 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
825 19:22:46.174032 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
826 19:22:46.177444 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
827 19:22:46.180923 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 19:22:46.183915 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 19:22:46.190750 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 19:22:46.194063 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
831 19:22:46.197623 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
832 19:22:46.204252 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
833 19:22:46.207585 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
834 19:22:46.210616 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 19:22:46.217431 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 19:22:46.220391 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 19:22:46.224005 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 19:22:46.230786 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 19:22:46.234332 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 19:22:46.237275 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 19:22:46.243826 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 19:22:46.247249 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 19:22:46.250851 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 19:22:46.257712 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 19:22:46.260643 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
846 19:22:46.264026 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
847 19:22:46.267362 Total UI for P1: 0, mck2ui 16
848 19:22:46.271002 best dqsien dly found for B0: ( 0, 14, 8)
849 19:22:46.277745 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
850 19:22:46.277837 Total UI for P1: 0, mck2ui 16
851 19:22:46.280646 best dqsien dly found for B1: ( 0, 14, 12)
852 19:22:46.287549 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
853 19:22:46.290382 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
854 19:22:46.290468
855 19:22:46.293998 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
856 19:22:46.297444 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
857 19:22:46.300413 [Gating] SW calibration Done
858 19:22:46.300496 ==
859 19:22:46.303876 Dram Type= 6, Freq= 0, CH_0, rank 0
860 19:22:46.307415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
861 19:22:46.307526 ==
862 19:22:46.310860 RX Vref Scan: 0
863 19:22:46.310976
864 19:22:46.311042 RX Vref 0 -> 0, step: 1
865 19:22:46.311102
866 19:22:46.314109 RX Delay -130 -> 252, step: 16
867 19:22:46.317201 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
868 19:22:46.324503 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
869 19:22:46.327034 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
870 19:22:46.330669 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
871 19:22:46.334051 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
872 19:22:46.337036 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
873 19:22:46.343864 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
874 19:22:46.347294 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
875 19:22:46.350700 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
876 19:22:46.353663 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
877 19:22:46.357145 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
878 19:22:46.363989 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
879 19:22:46.366901 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
880 19:22:46.370720 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
881 19:22:46.374111 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
882 19:22:46.377009 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
883 19:22:46.377128 ==
884 19:22:46.380774 Dram Type= 6, Freq= 0, CH_0, rank 0
885 19:22:46.384492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
886 19:22:46.388031 ==
887 19:22:46.388158 DQS Delay:
888 19:22:46.388252 DQS0 = 0, DQS1 = 0
889 19:22:46.391650 DQM Delay:
890 19:22:46.391765 DQM0 = 82, DQM1 = 70
891 19:22:46.391864 DQ Delay:
892 19:22:46.395869 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
893 19:22:46.399321 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
894 19:22:46.403018 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
895 19:22:46.406898 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
896 19:22:46.407031
897 19:22:46.407125
898 19:22:46.407222 ==
899 19:22:46.410461 Dram Type= 6, Freq= 0, CH_0, rank 0
900 19:22:46.414712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
901 19:22:46.414846 ==
902 19:22:46.414962
903 19:22:46.415053
904 19:22:46.417685 TX Vref Scan disable
905 19:22:46.417799 == TX Byte 0 ==
906 19:22:46.424108 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
907 19:22:46.427647 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
908 19:22:46.427780 == TX Byte 1 ==
909 19:22:46.434353 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
910 19:22:46.437372 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
911 19:22:46.437476 ==
912 19:22:46.441063 Dram Type= 6, Freq= 0, CH_0, rank 0
913 19:22:46.444293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
914 19:22:46.444396 ==
915 19:22:46.455766 TX Vref=22, minBit 7, minWin=26, winSum=435
916 19:22:46.462788 TX Vref=24, minBit 4, minWin=27, winSum=439
917 19:22:46.466325 TX Vref=26, minBit 9, minWin=27, winSum=446
918 19:22:46.470462 TX Vref=28, minBit 5, minWin=27, winSum=442
919 19:22:46.473878 TX Vref=30, minBit 9, minWin=27, winSum=446
920 19:22:46.477180 TX Vref=32, minBit 2, minWin=27, winSum=444
921 19:22:46.480506 [TxChooseVref] Worse bit 9, Min win 27, Win sum 446, Final Vref 26
922 19:22:46.484178
923 19:22:46.484262 Final TX Range 1 Vref 26
924 19:22:46.484328
925 19:22:46.484389 ==
926 19:22:46.487656 Dram Type= 6, Freq= 0, CH_0, rank 0
927 19:22:46.491236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
928 19:22:46.491348 ==
929 19:22:46.491443
930 19:22:46.491533
931 19:22:46.495470 TX Vref Scan disable
932 19:22:46.498442 == TX Byte 0 ==
933 19:22:46.502718 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
934 19:22:46.506336 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
935 19:22:46.509806 == TX Byte 1 ==
936 19:22:46.513482 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
937 19:22:46.517294 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
938 19:22:46.517381
939 19:22:46.517447 [DATLAT]
940 19:22:46.517515 Freq=800, CH0 RK0
941 19:22:46.521336
942 19:22:46.521422 DATLAT Default: 0xa
943 19:22:46.521493 0, 0xFFFF, sum = 0
944 19:22:46.524636 1, 0xFFFF, sum = 0
945 19:22:46.524735 2, 0xFFFF, sum = 0
946 19:22:46.528763 3, 0xFFFF, sum = 0
947 19:22:46.528871 4, 0xFFFF, sum = 0
948 19:22:46.531804 5, 0xFFFF, sum = 0
949 19:22:46.531908 6, 0xFFFF, sum = 0
950 19:22:46.535463 7, 0xFFFF, sum = 0
951 19:22:46.535569 8, 0xFFFF, sum = 0
952 19:22:46.539615 9, 0x0, sum = 1
953 19:22:46.539725 10, 0x0, sum = 2
954 19:22:46.539824 11, 0x0, sum = 3
955 19:22:46.543323 12, 0x0, sum = 4
956 19:22:46.543431 best_step = 10
957 19:22:46.543524
958 19:22:46.543612 ==
959 19:22:46.546602 Dram Type= 6, Freq= 0, CH_0, rank 0
960 19:22:46.550397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
961 19:22:46.550501 ==
962 19:22:46.554010 RX Vref Scan: 1
963 19:22:46.554118
964 19:22:46.557821 Set Vref Range= 32 -> 127
965 19:22:46.557935
966 19:22:46.558031 RX Vref 32 -> 127, step: 1
967 19:22:46.558122
968 19:22:46.561719 RX Delay -111 -> 252, step: 8
969 19:22:46.561822
970 19:22:46.565245 Set Vref, RX VrefLevel [Byte0]: 32
971 19:22:46.568654 [Byte1]: 32
972 19:22:46.568756
973 19:22:46.573243 Set Vref, RX VrefLevel [Byte0]: 33
974 19:22:46.576163 [Byte1]: 33
975 19:22:46.576287
976 19:22:46.579438 Set Vref, RX VrefLevel [Byte0]: 34
977 19:22:46.583688 [Byte1]: 34
978 19:22:46.583799
979 19:22:46.587558 Set Vref, RX VrefLevel [Byte0]: 35
980 19:22:46.591030 [Byte1]: 35
981 19:22:46.591134
982 19:22:46.594610 Set Vref, RX VrefLevel [Byte0]: 36
983 19:22:46.598233 [Byte1]: 36
984 19:22:46.598339
985 19:22:46.601723 Set Vref, RX VrefLevel [Byte0]: 37
986 19:22:46.605290 [Byte1]: 37
987 19:22:46.609400
988 19:22:46.609505 Set Vref, RX VrefLevel [Byte0]: 38
989 19:22:46.612355 [Byte1]: 38
990 19:22:46.617126
991 19:22:46.617233 Set Vref, RX VrefLevel [Byte0]: 39
992 19:22:46.620513 [Byte1]: 39
993 19:22:46.624514
994 19:22:46.624700 Set Vref, RX VrefLevel [Byte0]: 40
995 19:22:46.627851 [Byte1]: 40
996 19:22:46.632052
997 19:22:46.632141 Set Vref, RX VrefLevel [Byte0]: 41
998 19:22:46.635751 [Byte1]: 41
999 19:22:46.639901
1000 19:22:46.639990 Set Vref, RX VrefLevel [Byte0]: 42
1001 19:22:46.643401 [Byte1]: 42
1002 19:22:46.647485
1003 19:22:46.647570 Set Vref, RX VrefLevel [Byte0]: 43
1004 19:22:46.651254 [Byte1]: 43
1005 19:22:46.655840
1006 19:22:46.655923 Set Vref, RX VrefLevel [Byte0]: 44
1007 19:22:46.659385 [Byte1]: 44
1008 19:22:46.662914
1009 19:22:46.662996 Set Vref, RX VrefLevel [Byte0]: 45
1010 19:22:46.666298 [Byte1]: 45
1011 19:22:46.670401
1012 19:22:46.670480 Set Vref, RX VrefLevel [Byte0]: 46
1013 19:22:46.673884 [Byte1]: 46
1014 19:22:46.677847
1015 19:22:46.677933 Set Vref, RX VrefLevel [Byte0]: 47
1016 19:22:46.681067 [Byte1]: 47
1017 19:22:46.685772
1018 19:22:46.685856 Set Vref, RX VrefLevel [Byte0]: 48
1019 19:22:46.689196 [Byte1]: 48
1020 19:22:46.693793
1021 19:22:46.693873 Set Vref, RX VrefLevel [Byte0]: 49
1022 19:22:46.696744 [Byte1]: 49
1023 19:22:46.701138
1024 19:22:46.701224 Set Vref, RX VrefLevel [Byte0]: 50
1025 19:22:46.705023 [Byte1]: 50
1026 19:22:46.708547
1027 19:22:46.708659 Set Vref, RX VrefLevel [Byte0]: 51
1028 19:22:46.712298 [Byte1]: 51
1029 19:22:46.716375
1030 19:22:46.716457 Set Vref, RX VrefLevel [Byte0]: 52
1031 19:22:46.719817 [Byte1]: 52
1032 19:22:46.723833
1033 19:22:46.723957 Set Vref, RX VrefLevel [Byte0]: 53
1034 19:22:46.727564 [Byte1]: 53
1035 19:22:46.731770
1036 19:22:46.731855 Set Vref, RX VrefLevel [Byte0]: 54
1037 19:22:46.734772 [Byte1]: 54
1038 19:22:46.739405
1039 19:22:46.739488 Set Vref, RX VrefLevel [Byte0]: 55
1040 19:22:46.742358 [Byte1]: 55
1041 19:22:46.746834
1042 19:22:46.746923 Set Vref, RX VrefLevel [Byte0]: 56
1043 19:22:46.750029 [Byte1]: 56
1044 19:22:46.754050
1045 19:22:46.754131 Set Vref, RX VrefLevel [Byte0]: 57
1046 19:22:46.757689 [Byte1]: 57
1047 19:22:46.761706
1048 19:22:46.761803 Set Vref, RX VrefLevel [Byte0]: 58
1049 19:22:46.765259 [Byte1]: 58
1050 19:22:46.769221
1051 19:22:46.769320 Set Vref, RX VrefLevel [Byte0]: 59
1052 19:22:46.773035 [Byte1]: 59
1053 19:22:46.776847
1054 19:22:46.776932 Set Vref, RX VrefLevel [Byte0]: 60
1055 19:22:46.780317 [Byte1]: 60
1056 19:22:46.784532
1057 19:22:46.784614 Set Vref, RX VrefLevel [Byte0]: 61
1058 19:22:46.787998 [Byte1]: 61
1059 19:22:46.792589
1060 19:22:46.792675 Set Vref, RX VrefLevel [Byte0]: 62
1061 19:22:46.795644 [Byte1]: 62
1062 19:22:46.800275
1063 19:22:46.800358 Set Vref, RX VrefLevel [Byte0]: 63
1064 19:22:46.803172 [Byte1]: 63
1065 19:22:46.807846
1066 19:22:46.807930 Set Vref, RX VrefLevel [Byte0]: 64
1067 19:22:46.810967 [Byte1]: 64
1068 19:22:46.815262
1069 19:22:46.815347 Set Vref, RX VrefLevel [Byte0]: 65
1070 19:22:46.818630 [Byte1]: 65
1071 19:22:46.822750
1072 19:22:46.822844 Set Vref, RX VrefLevel [Byte0]: 66
1073 19:22:46.826602 [Byte1]: 66
1074 19:22:46.830650
1075 19:22:46.830735 Set Vref, RX VrefLevel [Byte0]: 67
1076 19:22:46.834333 [Byte1]: 67
1077 19:22:46.838413
1078 19:22:46.838492 Set Vref, RX VrefLevel [Byte0]: 68
1079 19:22:46.841302 [Byte1]: 68
1080 19:22:46.846026
1081 19:22:46.846107 Set Vref, RX VrefLevel [Byte0]: 69
1082 19:22:46.848956 [Byte1]: 69
1083 19:22:46.853671
1084 19:22:46.853749 Set Vref, RX VrefLevel [Byte0]: 70
1085 19:22:46.856779 [Byte1]: 70
1086 19:22:46.861235
1087 19:22:46.861312 Set Vref, RX VrefLevel [Byte0]: 71
1088 19:22:46.864695 [Byte1]: 71
1089 19:22:46.868761
1090 19:22:46.868836 Set Vref, RX VrefLevel [Byte0]: 72
1091 19:22:46.872362 [Byte1]: 72
1092 19:22:46.876479
1093 19:22:46.876551 Set Vref, RX VrefLevel [Byte0]: 73
1094 19:22:46.879704 [Byte1]: 73
1095 19:22:46.883978
1096 19:22:46.884056 Set Vref, RX VrefLevel [Byte0]: 74
1097 19:22:46.887229 [Byte1]: 74
1098 19:22:46.891875
1099 19:22:46.891950 Set Vref, RX VrefLevel [Byte0]: 75
1100 19:22:46.895310 [Byte1]: 75
1101 19:22:46.899509
1102 19:22:46.899594 Set Vref, RX VrefLevel [Byte0]: 76
1103 19:22:46.902530 [Byte1]: 76
1104 19:22:46.907121
1105 19:22:46.907204 Set Vref, RX VrefLevel [Byte0]: 77
1106 19:22:46.910278 [Byte1]: 77
1107 19:22:46.914851
1108 19:22:46.914934 Set Vref, RX VrefLevel [Byte0]: 78
1109 19:22:46.918301 [Byte1]: 78
1110 19:22:46.922504
1111 19:22:46.922588 Set Vref, RX VrefLevel [Byte0]: 79
1112 19:22:46.925783 [Byte1]: 79
1113 19:22:46.930101
1114 19:22:46.930216 Set Vref, RX VrefLevel [Byte0]: 80
1115 19:22:46.933260 [Byte1]: 80
1116 19:22:46.937367
1117 19:22:46.937475 Final RX Vref Byte 0 = 60 to rank0
1118 19:22:46.941067 Final RX Vref Byte 1 = 57 to rank0
1119 19:22:46.944147 Final RX Vref Byte 0 = 60 to rank1
1120 19:22:46.947560 Final RX Vref Byte 1 = 57 to rank1==
1121 19:22:46.950935 Dram Type= 6, Freq= 0, CH_0, rank 0
1122 19:22:46.958023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1123 19:22:46.958112 ==
1124 19:22:46.958179 DQS Delay:
1125 19:22:46.958239 DQS0 = 0, DQS1 = 0
1126 19:22:46.961601 DQM Delay:
1127 19:22:46.961685 DQM0 = 82, DQM1 = 67
1128 19:22:46.961750 DQ Delay:
1129 19:22:46.965303 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1130 19:22:46.969153 DQ4 =80, DQ5 =68, DQ6 =92, DQ7 =92
1131 19:22:46.972559 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1132 19:22:46.975928 DQ12 =76, DQ13 =68, DQ14 =76, DQ15 =76
1133 19:22:46.976013
1134 19:22:46.976081
1135 19:22:46.983006 [DQSOSCAuto] RK0, (LSB)MR18= 0x2826, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 399 ps
1136 19:22:46.986577 CH0 RK0: MR19=606, MR18=2826
1137 19:22:46.993571 CH0_RK0: MR19=0x606, MR18=0x2826, DQSOSC=399, MR23=63, INC=92, DEC=61
1138 19:22:46.993696
1139 19:22:46.996854 ----->DramcWriteLeveling(PI) begin...
1140 19:22:46.996965 ==
1141 19:22:47.000277 Dram Type= 6, Freq= 0, CH_0, rank 1
1142 19:22:47.003364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1143 19:22:47.003449 ==
1144 19:22:47.006845 Write leveling (Byte 0): 33 => 33
1145 19:22:47.009842 Write leveling (Byte 1): 29 => 29
1146 19:22:47.013424 DramcWriteLeveling(PI) end<-----
1147 19:22:47.013559
1148 19:22:47.013642 ==
1149 19:22:47.016939 Dram Type= 6, Freq= 0, CH_0, rank 1
1150 19:22:47.020593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1151 19:22:47.023339 ==
1152 19:22:47.023421 [Gating] SW mode calibration
1153 19:22:47.030074 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1154 19:22:47.037054 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1155 19:22:47.040004 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1156 19:22:47.046513 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1157 19:22:47.050202 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1158 19:22:47.053270 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 19:22:47.059913 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 19:22:47.063464 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 19:22:47.067099 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 19:22:47.073432 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 19:22:47.076954 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 19:22:47.080258 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 19:22:47.083472 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 19:22:47.090337 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 19:22:47.093655 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 19:22:47.097023 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 19:22:47.103205 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 19:22:47.106455 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 19:22:47.110232 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 19:22:47.116710 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 19:22:47.120298 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1174 19:22:47.123329 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1175 19:22:47.130220 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 19:22:47.133296 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 19:22:47.136740 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 19:22:47.143356 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 19:22:47.146703 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 19:22:47.150075 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 19:22:47.156419 0 9 8 | B1->B0 | 2323 2e2e | 1 0 | (1 1) (0 0)
1182 19:22:47.160261 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 19:22:47.163162 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 19:22:47.169789 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 19:22:47.173308 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 19:22:47.176510 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 19:22:47.180036 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1188 19:22:47.186752 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
1189 19:22:47.190172 0 10 8 | B1->B0 | 2c2c 2727 | 1 0 | (1 0) (0 0)
1190 19:22:47.193370 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1191 19:22:47.199938 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 19:22:47.203582 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 19:22:47.206962 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 19:22:47.213289 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 19:22:47.216759 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 19:22:47.220495 0 11 4 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
1197 19:22:47.226890 0 11 8 | B1->B0 | 3333 3b3b | 1 0 | (0 0) (0 0)
1198 19:22:47.230438 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 19:22:47.233246 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 19:22:47.239773 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 19:22:47.243218 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 19:22:47.246750 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 19:22:47.253161 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 19:22:47.256662 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1205 19:22:47.260077 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1206 19:22:47.266774 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1207 19:22:47.269691 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 19:22:47.273326 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 19:22:47.279697 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 19:22:47.283411 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 19:22:47.286412 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 19:22:47.289965 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 19:22:47.296327 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 19:22:47.299849 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 19:22:47.303423 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 19:22:47.309893 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 19:22:47.313320 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 19:22:47.316865 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 19:22:47.323431 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 19:22:47.326853 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1221 19:22:47.330045 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1222 19:22:47.336422 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1223 19:22:47.336504 Total UI for P1: 0, mck2ui 16
1224 19:22:47.343421 best dqsien dly found for B0: ( 0, 14, 6)
1225 19:22:47.343504 Total UI for P1: 0, mck2ui 16
1226 19:22:47.350106 best dqsien dly found for B1: ( 0, 14, 10)
1227 19:22:47.353162 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1228 19:22:47.356616 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1229 19:22:47.356687
1230 19:22:47.360052 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1231 19:22:47.362969 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1232 19:22:47.366666 [Gating] SW calibration Done
1233 19:22:47.366740 ==
1234 19:22:47.369869 Dram Type= 6, Freq= 0, CH_0, rank 1
1235 19:22:47.373346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1236 19:22:47.373418 ==
1237 19:22:47.376305 RX Vref Scan: 0
1238 19:22:47.376373
1239 19:22:47.376433 RX Vref 0 -> 0, step: 1
1240 19:22:47.376496
1241 19:22:47.379875 RX Delay -130 -> 252, step: 16
1242 19:22:47.383439 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1243 19:22:47.389933 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1244 19:22:47.393412 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1245 19:22:47.396737 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1246 19:22:47.400089 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1247 19:22:47.403445 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
1248 19:22:47.409920 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1249 19:22:47.412897 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1250 19:22:47.416556 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1251 19:22:47.419981 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1252 19:22:47.422958 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1253 19:22:47.429755 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1254 19:22:47.432990 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
1255 19:22:47.436112 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1256 19:22:47.439677 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1257 19:22:47.443582 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1258 19:22:47.446396 ==
1259 19:22:47.446470 Dram Type= 6, Freq= 0, CH_0, rank 1
1260 19:22:47.452781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1261 19:22:47.452865 ==
1262 19:22:47.452931 DQS Delay:
1263 19:22:47.456244 DQS0 = 0, DQS1 = 0
1264 19:22:47.456323 DQM Delay:
1265 19:22:47.459652 DQM0 = 76, DQM1 = 68
1266 19:22:47.459730 DQ Delay:
1267 19:22:47.463238 DQ0 =77, DQ1 =77, DQ2 =69, DQ3 =69
1268 19:22:47.466684 DQ4 =77, DQ5 =61, DQ6 =85, DQ7 =93
1269 19:22:47.469592 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1270 19:22:47.473050 DQ12 =69, DQ13 =77, DQ14 =77, DQ15 =77
1271 19:22:47.473135
1272 19:22:47.473202
1273 19:22:47.473262 ==
1274 19:22:47.476433 Dram Type= 6, Freq= 0, CH_0, rank 1
1275 19:22:47.479711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1276 19:22:47.479793 ==
1277 19:22:47.479858
1278 19:22:47.479918
1279 19:22:47.483187 TX Vref Scan disable
1280 19:22:47.486713 == TX Byte 0 ==
1281 19:22:47.489748 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1282 19:22:47.493274 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1283 19:22:47.493384 == TX Byte 1 ==
1284 19:22:47.499981 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1285 19:22:47.503477 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1286 19:22:47.503559 ==
1287 19:22:47.506477 Dram Type= 6, Freq= 0, CH_0, rank 1
1288 19:22:47.510110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1289 19:22:47.510193 ==
1290 19:22:47.524320 TX Vref=22, minBit 0, minWin=27, winSum=434
1291 19:22:47.527836 TX Vref=24, minBit 2, minWin=27, winSum=440
1292 19:22:47.531327 TX Vref=26, minBit 1, minWin=27, winSum=442
1293 19:22:47.534117 TX Vref=28, minBit 3, minWin=27, winSum=445
1294 19:22:47.537680 TX Vref=30, minBit 1, minWin=27, winSum=447
1295 19:22:47.544319 TX Vref=32, minBit 2, minWin=27, winSum=444
1296 19:22:47.547501 [TxChooseVref] Worse bit 1, Min win 27, Win sum 447, Final Vref 30
1297 19:22:47.547584
1298 19:22:47.550814 Final TX Range 1 Vref 30
1299 19:22:47.550895
1300 19:22:47.550958 ==
1301 19:22:47.554302 Dram Type= 6, Freq= 0, CH_0, rank 1
1302 19:22:47.557673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1303 19:22:47.557755 ==
1304 19:22:47.560932
1305 19:22:47.561012
1306 19:22:47.561076 TX Vref Scan disable
1307 19:22:47.564536 == TX Byte 0 ==
1308 19:22:47.567690 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1309 19:22:47.574366 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1310 19:22:47.574448 == TX Byte 1 ==
1311 19:22:47.577490 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1312 19:22:47.584075 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1313 19:22:47.584157
1314 19:22:47.584221 [DATLAT]
1315 19:22:47.584295 Freq=800, CH0 RK1
1316 19:22:47.584397
1317 19:22:47.587589 DATLAT Default: 0xa
1318 19:22:47.587684 0, 0xFFFF, sum = 0
1319 19:22:47.591190 1, 0xFFFF, sum = 0
1320 19:22:47.591271 2, 0xFFFF, sum = 0
1321 19:22:47.594117 3, 0xFFFF, sum = 0
1322 19:22:47.594199 4, 0xFFFF, sum = 0
1323 19:22:47.597693 5, 0xFFFF, sum = 0
1324 19:22:47.601102 6, 0xFFFF, sum = 0
1325 19:22:47.601184 7, 0xFFFF, sum = 0
1326 19:22:47.604127 8, 0xFFFF, sum = 0
1327 19:22:47.604209 9, 0x0, sum = 1
1328 19:22:47.604274 10, 0x0, sum = 2
1329 19:22:47.607900 11, 0x0, sum = 3
1330 19:22:47.607981 12, 0x0, sum = 4
1331 19:22:47.611397 best_step = 10
1332 19:22:47.611476
1333 19:22:47.611540 ==
1334 19:22:47.614276 Dram Type= 6, Freq= 0, CH_0, rank 1
1335 19:22:47.617806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1336 19:22:47.617888 ==
1337 19:22:47.621240 RX Vref Scan: 0
1338 19:22:47.621344
1339 19:22:47.621435 RX Vref 0 -> 0, step: 1
1340 19:22:47.621567
1341 19:22:47.624450 RX Delay -111 -> 252, step: 8
1342 19:22:47.631560 iDelay=209, Bit 0, Center 76 (-39 ~ 192) 232
1343 19:22:47.635655 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1344 19:22:47.639229 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1345 19:22:47.642828 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1346 19:22:47.646525 iDelay=209, Bit 4, Center 76 (-39 ~ 192) 232
1347 19:22:47.650215 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1348 19:22:47.653927 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1349 19:22:47.657388 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1350 19:22:47.660465 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1351 19:22:47.667277 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1352 19:22:47.670716 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1353 19:22:47.673976 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1354 19:22:47.677366 iDelay=209, Bit 12, Center 76 (-39 ~ 192) 232
1355 19:22:47.680864 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1356 19:22:47.687293 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1357 19:22:47.690948 iDelay=209, Bit 15, Center 76 (-39 ~ 192) 232
1358 19:22:47.691029 ==
1359 19:22:47.694048 Dram Type= 6, Freq= 0, CH_0, rank 1
1360 19:22:47.697616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1361 19:22:47.697701 ==
1362 19:22:47.700566 DQS Delay:
1363 19:22:47.700646 DQS0 = 0, DQS1 = 0
1364 19:22:47.700710 DQM Delay:
1365 19:22:47.704143 DQM0 = 78, DQM1 = 70
1366 19:22:47.704224 DQ Delay:
1367 19:22:47.707163 DQ0 =76, DQ1 =84, DQ2 =76, DQ3 =72
1368 19:22:47.710810 DQ4 =76, DQ5 =64, DQ6 =88, DQ7 =92
1369 19:22:47.714247 DQ8 =60, DQ9 =56, DQ10 =72, DQ11 =64
1370 19:22:47.717269 DQ12 =76, DQ13 =76, DQ14 =80, DQ15 =76
1371 19:22:47.717351
1372 19:22:47.717415
1373 19:22:47.727304 [DQSOSCAuto] RK1, (LSB)MR18= 0x4c26, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 390 ps
1374 19:22:47.727447 CH0 RK1: MR19=606, MR18=4C26
1375 19:22:47.734275 CH0_RK1: MR19=0x606, MR18=0x4C26, DQSOSC=390, MR23=63, INC=97, DEC=64
1376 19:22:47.737457 [RxdqsGatingPostProcess] freq 800
1377 19:22:47.744044 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1378 19:22:47.747120 Pre-setting of DQS Precalculation
1379 19:22:47.750427 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1380 19:22:47.750506 ==
1381 19:22:47.753764 Dram Type= 6, Freq= 0, CH_1, rank 0
1382 19:22:47.757398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1383 19:22:47.760496 ==
1384 19:22:47.764027 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1385 19:22:47.770311 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1386 19:22:47.779260 [CA 0] Center 36 (6~66) winsize 61
1387 19:22:47.782456 [CA 1] Center 36 (6~67) winsize 62
1388 19:22:47.785936 [CA 2] Center 34 (4~64) winsize 61
1389 19:22:47.789357 [CA 3] Center 34 (4~64) winsize 61
1390 19:22:47.792552 [CA 4] Center 34 (4~64) winsize 61
1391 19:22:47.795803 [CA 5] Center 33 (3~64) winsize 62
1392 19:22:47.795887
1393 19:22:47.799414 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1394 19:22:47.799501
1395 19:22:47.802689 [CATrainingPosCal] consider 1 rank data
1396 19:22:47.806163 u2DelayCellTimex100 = 270/100 ps
1397 19:22:47.809105 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1398 19:22:47.812596 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1399 19:22:47.819026 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1400 19:22:47.822670 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1401 19:22:47.826150 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
1402 19:22:47.829551 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1403 19:22:47.829678
1404 19:22:47.832453 CA PerBit enable=1, Macro0, CA PI delay=33
1405 19:22:47.832535
1406 19:22:47.836022 [CBTSetCACLKResult] CA Dly = 33
1407 19:22:47.836107 CS Dly: 5 (0~36)
1408 19:22:47.839477 ==
1409 19:22:47.839561 Dram Type= 6, Freq= 0, CH_1, rank 1
1410 19:22:47.845966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1411 19:22:47.846054 ==
1412 19:22:47.849329 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1413 19:22:47.855985 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1414 19:22:47.865272 [CA 0] Center 36 (7~66) winsize 60
1415 19:22:47.869117 [CA 1] Center 37 (7~67) winsize 61
1416 19:22:47.872092 [CA 2] Center 34 (4~65) winsize 62
1417 19:22:47.875590 [CA 3] Center 33 (3~64) winsize 62
1418 19:22:47.878792 [CA 4] Center 34 (4~65) winsize 62
1419 19:22:47.882312 [CA 5] Center 33 (3~64) winsize 62
1420 19:22:47.882398
1421 19:22:47.885776 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1422 19:22:47.885862
1423 19:22:47.888984 [CATrainingPosCal] consider 2 rank data
1424 19:22:47.891894 u2DelayCellTimex100 = 270/100 ps
1425 19:22:47.895303 CA0 delay=36 (7~66),Diff = 3 PI (21 cell)
1426 19:22:47.898839 CA1 delay=37 (7~67),Diff = 4 PI (28 cell)
1427 19:22:47.905328 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1428 19:22:47.908854 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1429 19:22:47.912026 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
1430 19:22:47.915328 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1431 19:22:47.915415
1432 19:22:47.918988 CA PerBit enable=1, Macro0, CA PI delay=33
1433 19:22:47.919072
1434 19:22:47.921861 [CBTSetCACLKResult] CA Dly = 33
1435 19:22:47.921943 CS Dly: 6 (0~38)
1436 19:22:47.922008
1437 19:22:47.925359 ----->DramcWriteLeveling(PI) begin...
1438 19:22:47.928898 ==
1439 19:22:47.931865 Dram Type= 6, Freq= 0, CH_1, rank 0
1440 19:22:47.935364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1441 19:22:47.935451 ==
1442 19:22:47.938854 Write leveling (Byte 0): 30 => 30
1443 19:22:47.941848 Write leveling (Byte 1): 30 => 30
1444 19:22:47.945415 DramcWriteLeveling(PI) end<-----
1445 19:22:47.945493
1446 19:22:47.945629 ==
1447 19:22:47.948550 Dram Type= 6, Freq= 0, CH_1, rank 0
1448 19:22:47.951957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1449 19:22:47.952042 ==
1450 19:22:47.955568 [Gating] SW mode calibration
1451 19:22:47.962046 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1452 19:22:47.965357 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1453 19:22:47.972120 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1454 19:22:47.975392 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1455 19:22:47.978599 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1456 19:22:47.985375 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 19:22:47.988741 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 19:22:47.992135 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 19:22:47.998523 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 19:22:48.001819 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 19:22:48.005309 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 19:22:48.011877 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 19:22:48.015152 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 19:22:48.018726 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 19:22:48.025615 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 19:22:48.029134 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 19:22:48.032212 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 19:22:48.039013 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 19:22:48.041942 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 19:22:48.045595 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1471 19:22:48.048642 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1472 19:22:48.055692 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 19:22:48.058615 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 19:22:48.062269 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 19:22:48.068768 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 19:22:48.072422 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 19:22:48.075786 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 19:22:48.082294 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 19:22:48.085494 0 9 8 | B1->B0 | 2b2b 2929 | 1 0 | (0 0) (0 0)
1480 19:22:48.088924 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 19:22:48.095667 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 19:22:48.098712 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 19:22:48.102129 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 19:22:48.108546 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 19:22:48.111833 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1486 19:22:48.115481 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
1487 19:22:48.122116 0 10 8 | B1->B0 | 2e2e 2c2c | 1 0 | (1 0) (1 1)
1488 19:22:48.125624 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 19:22:48.128622 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 19:22:48.135082 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 19:22:48.138613 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 19:22:48.141934 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 19:22:48.148411 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 19:22:48.151940 0 11 4 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
1495 19:22:48.155507 0 11 8 | B1->B0 | 3737 3434 | 0 0 | (0 0) (1 1)
1496 19:22:48.158534 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 19:22:48.165472 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 19:22:48.168559 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 19:22:48.172073 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 19:22:48.178566 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 19:22:48.182025 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 19:22:48.185463 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1503 19:22:48.192020 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1504 19:22:48.195270 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1505 19:22:48.198880 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 19:22:48.205850 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 19:22:48.209319 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 19:22:48.212465 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 19:22:48.218867 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 19:22:48.222645 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 19:22:48.225644 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 19:22:48.228849 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 19:22:48.235641 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 19:22:48.239317 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 19:22:48.242503 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 19:22:48.248893 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 19:22:48.252388 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 19:22:48.255894 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1519 19:22:48.262466 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1520 19:22:48.265414 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1521 19:22:48.268961 Total UI for P1: 0, mck2ui 16
1522 19:22:48.272560 best dqsien dly found for B0: ( 0, 14, 6)
1523 19:22:48.275565 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1524 19:22:48.279032 Total UI for P1: 0, mck2ui 16
1525 19:22:48.282537 best dqsien dly found for B1: ( 0, 14, 10)
1526 19:22:48.285392 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1527 19:22:48.288987 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1528 19:22:48.289058
1529 19:22:48.295766 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1530 19:22:48.298929 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1531 19:22:48.299014 [Gating] SW calibration Done
1532 19:22:48.302423 ==
1533 19:22:48.305877 Dram Type= 6, Freq= 0, CH_1, rank 0
1534 19:22:48.308786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1535 19:22:48.308869 ==
1536 19:22:48.308934 RX Vref Scan: 0
1537 19:22:48.308995
1538 19:22:48.311946 RX Vref 0 -> 0, step: 1
1539 19:22:48.312057
1540 19:22:48.315793 RX Delay -130 -> 252, step: 16
1541 19:22:48.318837 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1542 19:22:48.322221 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1543 19:22:48.325611 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1544 19:22:48.332420 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1545 19:22:48.335316 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1546 19:22:48.339059 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1547 19:22:48.342266 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1548 19:22:48.345394 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1549 19:22:48.352298 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1550 19:22:48.355762 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1551 19:22:48.358657 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1552 19:22:48.362093 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1553 19:22:48.365658 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1554 19:22:48.372339 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1555 19:22:48.375415 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1556 19:22:48.378971 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1557 19:22:48.379058 ==
1558 19:22:48.382464 Dram Type= 6, Freq= 0, CH_1, rank 0
1559 19:22:48.385490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1560 19:22:48.388891 ==
1561 19:22:48.388972 DQS Delay:
1562 19:22:48.389036 DQS0 = 0, DQS1 = 0
1563 19:22:48.392456 DQM Delay:
1564 19:22:48.392538 DQM0 = 81, DQM1 = 73
1565 19:22:48.392602 DQ Delay:
1566 19:22:48.395311 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1567 19:22:48.398801 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1568 19:22:48.402349 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1569 19:22:48.405450 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1570 19:22:48.405567
1571 19:22:48.405632
1572 19:22:48.409004 ==
1573 19:22:48.412381 Dram Type= 6, Freq= 0, CH_1, rank 0
1574 19:22:48.415833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1575 19:22:48.415916 ==
1576 19:22:48.415980
1577 19:22:48.416040
1578 19:22:48.418696 TX Vref Scan disable
1579 19:22:48.418780 == TX Byte 0 ==
1580 19:22:48.422604 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1581 19:22:48.428802 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1582 19:22:48.428901 == TX Byte 1 ==
1583 19:22:48.432251 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1584 19:22:48.438690 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1585 19:22:48.438777 ==
1586 19:22:48.442321 Dram Type= 6, Freq= 0, CH_1, rank 0
1587 19:22:48.445624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1588 19:22:48.445707 ==
1589 19:22:48.458883 TX Vref=22, minBit 1, minWin=26, winSum=439
1590 19:22:48.462210 TX Vref=24, minBit 1, minWin=26, winSum=441
1591 19:22:48.465646 TX Vref=26, minBit 0, minWin=27, winSum=444
1592 19:22:48.468934 TX Vref=28, minBit 0, minWin=28, winSum=449
1593 19:22:48.472263 TX Vref=30, minBit 1, minWin=28, winSum=451
1594 19:22:48.475306 TX Vref=32, minBit 9, minWin=27, winSum=448
1595 19:22:48.482256 [TxChooseVref] Worse bit 1, Min win 28, Win sum 451, Final Vref 30
1596 19:22:48.482349
1597 19:22:48.485749 Final TX Range 1 Vref 30
1598 19:22:48.485833
1599 19:22:48.485897 ==
1600 19:22:48.488749 Dram Type= 6, Freq= 0, CH_1, rank 0
1601 19:22:48.492300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1602 19:22:48.492382 ==
1603 19:22:48.492471
1604 19:22:48.495173
1605 19:22:48.495254 TX Vref Scan disable
1606 19:22:48.498734 == TX Byte 0 ==
1607 19:22:48.502315 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1608 19:22:48.505240 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1609 19:22:48.508795 == TX Byte 1 ==
1610 19:22:48.512201 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1611 19:22:48.515308 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1612 19:22:48.518769
1613 19:22:48.518852 [DATLAT]
1614 19:22:48.518916 Freq=800, CH1 RK0
1615 19:22:48.518976
1616 19:22:48.522172 DATLAT Default: 0xa
1617 19:22:48.522278 0, 0xFFFF, sum = 0
1618 19:22:48.525125 1, 0xFFFF, sum = 0
1619 19:22:48.525208 2, 0xFFFF, sum = 0
1620 19:22:48.528914 3, 0xFFFF, sum = 0
1621 19:22:48.528998 4, 0xFFFF, sum = 0
1622 19:22:48.532029 5, 0xFFFF, sum = 0
1623 19:22:48.532185 6, 0xFFFF, sum = 0
1624 19:22:48.535245 7, 0xFFFF, sum = 0
1625 19:22:48.535328 8, 0xFFFF, sum = 0
1626 19:22:48.538682 9, 0x0, sum = 1
1627 19:22:48.538766 10, 0x0, sum = 2
1628 19:22:48.542204 11, 0x0, sum = 3
1629 19:22:48.542287 12, 0x0, sum = 4
1630 19:22:48.545111 best_step = 10
1631 19:22:48.545192
1632 19:22:48.545256 ==
1633 19:22:48.548723 Dram Type= 6, Freq= 0, CH_1, rank 0
1634 19:22:48.552255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1635 19:22:48.552338 ==
1636 19:22:48.555642 RX Vref Scan: 1
1637 19:22:48.555724
1638 19:22:48.555788 Set Vref Range= 32 -> 127
1639 19:22:48.555848
1640 19:22:48.558851 RX Vref 32 -> 127, step: 1
1641 19:22:48.558932
1642 19:22:48.562134 RX Delay -95 -> 252, step: 8
1643 19:22:48.562218
1644 19:22:48.565488 Set Vref, RX VrefLevel [Byte0]: 32
1645 19:22:48.568934 [Byte1]: 32
1646 19:22:48.569018
1647 19:22:48.571883 Set Vref, RX VrefLevel [Byte0]: 33
1648 19:22:48.575394 [Byte1]: 33
1649 19:22:48.578962
1650 19:22:48.579045 Set Vref, RX VrefLevel [Byte0]: 34
1651 19:22:48.582624 [Byte1]: 34
1652 19:22:48.586288
1653 19:22:48.586371 Set Vref, RX VrefLevel [Byte0]: 35
1654 19:22:48.590044 [Byte1]: 35
1655 19:22:48.594154
1656 19:22:48.594243 Set Vref, RX VrefLevel [Byte0]: 36
1657 19:22:48.597639 [Byte1]: 36
1658 19:22:48.601755
1659 19:22:48.601837 Set Vref, RX VrefLevel [Byte0]: 37
1660 19:22:48.604755 [Byte1]: 37
1661 19:22:48.609403
1662 19:22:48.609503 Set Vref, RX VrefLevel [Byte0]: 38
1663 19:22:48.612391 [Byte1]: 38
1664 19:22:48.617079
1665 19:22:48.617165 Set Vref, RX VrefLevel [Byte0]: 39
1666 19:22:48.620055 [Byte1]: 39
1667 19:22:48.624646
1668 19:22:48.624756 Set Vref, RX VrefLevel [Byte0]: 40
1669 19:22:48.627752 [Byte1]: 40
1670 19:22:48.632113
1671 19:22:48.632237 Set Vref, RX VrefLevel [Byte0]: 41
1672 19:22:48.635500 [Byte1]: 41
1673 19:22:48.639862
1674 19:22:48.639978 Set Vref, RX VrefLevel [Byte0]: 42
1675 19:22:48.642772 [Byte1]: 42
1676 19:22:48.647112
1677 19:22:48.647223 Set Vref, RX VrefLevel [Byte0]: 43
1678 19:22:48.650673 [Byte1]: 43
1679 19:22:48.654709
1680 19:22:48.654791 Set Vref, RX VrefLevel [Byte0]: 44
1681 19:22:48.658115 [Byte1]: 44
1682 19:22:48.662313
1683 19:22:48.662391 Set Vref, RX VrefLevel [Byte0]: 45
1684 19:22:48.665814 [Byte1]: 45
1685 19:22:48.670000
1686 19:22:48.670113 Set Vref, RX VrefLevel [Byte0]: 46
1687 19:22:48.673767 [Byte1]: 46
1688 19:22:48.677948
1689 19:22:48.678033 Set Vref, RX VrefLevel [Byte0]: 47
1690 19:22:48.680883 [Byte1]: 47
1691 19:22:48.685113
1692 19:22:48.685196 Set Vref, RX VrefLevel [Byte0]: 48
1693 19:22:48.688537 [Byte1]: 48
1694 19:22:48.692889
1695 19:22:48.692974 Set Vref, RX VrefLevel [Byte0]: 49
1696 19:22:48.696151 [Byte1]: 49
1697 19:22:48.700582
1698 19:22:48.700668 Set Vref, RX VrefLevel [Byte0]: 50
1699 19:22:48.703845 [Byte1]: 50
1700 19:22:48.707873
1701 19:22:48.707967 Set Vref, RX VrefLevel [Byte0]: 51
1702 19:22:48.711508 [Byte1]: 51
1703 19:22:48.715698
1704 19:22:48.715785 Set Vref, RX VrefLevel [Byte0]: 52
1705 19:22:48.719245 [Byte1]: 52
1706 19:22:48.723412
1707 19:22:48.723526 Set Vref, RX VrefLevel [Byte0]: 53
1708 19:22:48.726254 [Byte1]: 53
1709 19:22:48.731111
1710 19:22:48.731233 Set Vref, RX VrefLevel [Byte0]: 54
1711 19:22:48.734257 [Byte1]: 54
1712 19:22:48.738569
1713 19:22:48.738656 Set Vref, RX VrefLevel [Byte0]: 55
1714 19:22:48.741504 [Byte1]: 55
1715 19:22:48.746374
1716 19:22:48.746491 Set Vref, RX VrefLevel [Byte0]: 56
1717 19:22:48.749261 [Byte1]: 56
1718 19:22:48.753798
1719 19:22:48.753884 Set Vref, RX VrefLevel [Byte0]: 57
1720 19:22:48.756724 [Byte1]: 57
1721 19:22:48.761425
1722 19:22:48.761575 Set Vref, RX VrefLevel [Byte0]: 58
1723 19:22:48.764321 [Byte1]: 58
1724 19:22:48.768692
1725 19:22:48.768785 Set Vref, RX VrefLevel [Byte0]: 59
1726 19:22:48.772120 [Byte1]: 59
1727 19:22:48.776420
1728 19:22:48.776510 Set Vref, RX VrefLevel [Byte0]: 60
1729 19:22:48.779570 [Byte1]: 60
1730 19:22:48.784027
1731 19:22:48.784131 Set Vref, RX VrefLevel [Byte0]: 61
1732 19:22:48.787634 [Byte1]: 61
1733 19:22:48.791865
1734 19:22:48.791951 Set Vref, RX VrefLevel [Byte0]: 62
1735 19:22:48.794864 [Byte1]: 62
1736 19:22:48.799327
1737 19:22:48.799414 Set Vref, RX VrefLevel [Byte0]: 63
1738 19:22:48.802459 [Byte1]: 63
1739 19:22:48.806743
1740 19:22:48.806829 Set Vref, RX VrefLevel [Byte0]: 64
1741 19:22:48.810098 [Byte1]: 64
1742 19:22:48.814612
1743 19:22:48.814701 Set Vref, RX VrefLevel [Byte0]: 65
1744 19:22:48.817539 [Byte1]: 65
1745 19:22:48.822239
1746 19:22:48.822322 Set Vref, RX VrefLevel [Byte0]: 66
1747 19:22:48.825247 [Byte1]: 66
1748 19:22:48.829334
1749 19:22:48.829427 Set Vref, RX VrefLevel [Byte0]: 67
1750 19:22:48.832952 [Byte1]: 67
1751 19:22:48.837682
1752 19:22:48.837771 Set Vref, RX VrefLevel [Byte0]: 68
1753 19:22:48.840353 [Byte1]: 68
1754 19:22:48.844776
1755 19:22:48.844867 Set Vref, RX VrefLevel [Byte0]: 69
1756 19:22:48.848365 [Byte1]: 69
1757 19:22:48.852440
1758 19:22:48.852523 Set Vref, RX VrefLevel [Byte0]: 70
1759 19:22:48.855929 [Byte1]: 70
1760 19:22:48.860031
1761 19:22:48.860115 Set Vref, RX VrefLevel [Byte0]: 71
1762 19:22:48.863567 [Byte1]: 71
1763 19:22:48.867490
1764 19:22:48.867572 Set Vref, RX VrefLevel [Byte0]: 72
1765 19:22:48.870908 [Byte1]: 72
1766 19:22:48.875013
1767 19:22:48.875095 Set Vref, RX VrefLevel [Byte0]: 73
1768 19:22:48.878502 [Byte1]: 73
1769 19:22:48.882887
1770 19:22:48.882992 Set Vref, RX VrefLevel [Byte0]: 74
1771 19:22:48.885920 [Byte1]: 74
1772 19:22:48.890567
1773 19:22:48.890651 Final RX Vref Byte 0 = 57 to rank0
1774 19:22:48.893602 Final RX Vref Byte 1 = 57 to rank0
1775 19:22:48.897256 Final RX Vref Byte 0 = 57 to rank1
1776 19:22:48.900401 Final RX Vref Byte 1 = 57 to rank1==
1777 19:22:48.903824 Dram Type= 6, Freq= 0, CH_1, rank 0
1778 19:22:48.910417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1779 19:22:48.910524 ==
1780 19:22:48.910592 DQS Delay:
1781 19:22:48.910652 DQS0 = 0, DQS1 = 0
1782 19:22:48.913781 DQM Delay:
1783 19:22:48.913864 DQM0 = 81, DQM1 = 71
1784 19:22:48.917167 DQ Delay:
1785 19:22:48.920517 DQ0 =88, DQ1 =76, DQ2 =68, DQ3 =76
1786 19:22:48.920617 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
1787 19:22:48.923484 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =68
1788 19:22:48.927137 DQ12 =80, DQ13 =76, DQ14 =76, DQ15 =76
1789 19:22:48.930126
1790 19:22:48.930217
1791 19:22:48.937380 [DQSOSCAuto] RK0, (LSB)MR18= 0x1923, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 403 ps
1792 19:22:48.940394 CH1 RK0: MR19=606, MR18=1923
1793 19:22:48.946818 CH1_RK0: MR19=0x606, MR18=0x1923, DQSOSC=401, MR23=63, INC=91, DEC=61
1794 19:22:48.946918
1795 19:22:48.950201 ----->DramcWriteLeveling(PI) begin...
1796 19:22:48.950315 ==
1797 19:22:48.953957 Dram Type= 6, Freq= 0, CH_1, rank 1
1798 19:22:48.956973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1799 19:22:48.957109 ==
1800 19:22:48.960480 Write leveling (Byte 0): 29 => 29
1801 19:22:48.963580 Write leveling (Byte 1): 29 => 29
1802 19:22:48.967013 DramcWriteLeveling(PI) end<-----
1803 19:22:48.967110
1804 19:22:48.967206 ==
1805 19:22:48.970556 Dram Type= 6, Freq= 0, CH_1, rank 1
1806 19:22:48.974006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1807 19:22:48.974118 ==
1808 19:22:48.976920 [Gating] SW mode calibration
1809 19:22:48.983867 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1810 19:22:48.990682 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1811 19:22:48.993753 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1812 19:22:48.997128 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1813 19:22:49.003384 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 19:22:49.006886 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 19:22:49.010555 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 19:22:49.017113 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 19:22:49.020565 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 19:22:49.023908 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 19:22:49.030328 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 19:22:49.033763 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 19:22:49.037276 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 19:22:49.040281 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 19:22:49.047315 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 19:22:49.050256 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 19:22:49.053739 0 7 24 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
1826 19:22:49.060383 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 19:22:49.063729 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 19:22:49.066790 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1829 19:22:49.073541 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1830 19:22:49.077069 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 19:22:49.079885 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 19:22:49.087119 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 19:22:49.090002 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 19:22:49.093439 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 19:22:49.100061 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 19:22:49.103729 0 9 4 | B1->B0 | 2323 2d2d | 1 1 | (1 1) (1 1)
1837 19:22:49.106944 0 9 8 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
1838 19:22:49.113671 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1839 19:22:49.116714 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1840 19:22:49.120129 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1841 19:22:49.126762 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1842 19:22:49.130321 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1843 19:22:49.133389 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
1844 19:22:49.140146 0 10 4 | B1->B0 | 3030 2e2e | 1 1 | (1 0) (1 0)
1845 19:22:49.143786 0 10 8 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1846 19:22:49.146654 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 19:22:49.153773 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 19:22:49.156773 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 19:22:49.160220 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 19:22:49.163559 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 19:22:49.170377 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1852 19:22:49.173813 0 11 4 | B1->B0 | 2424 3a3a | 0 0 | (0 0) (0 0)
1853 19:22:49.177315 0 11 8 | B1->B0 | 4242 4646 | 1 0 | (0 0) (0 0)
1854 19:22:49.183976 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1855 19:22:49.186853 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1856 19:22:49.190460 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1857 19:22:49.196947 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1858 19:22:49.200507 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1859 19:22:49.204097 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 19:22:49.210432 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1861 19:22:49.213740 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 19:22:49.216854 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 19:22:49.223749 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 19:22:49.227027 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 19:22:49.230225 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 19:22:49.237300 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 19:22:49.240481 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 19:22:49.243952 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 19:22:49.246875 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 19:22:49.253686 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 19:22:49.257256 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 19:22:49.260246 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 19:22:49.267240 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 19:22:49.270461 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 19:22:49.273433 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 19:22:49.280273 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1877 19:22:49.283715 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1878 19:22:49.287245 Total UI for P1: 0, mck2ui 16
1879 19:22:49.290248 best dqsien dly found for B0: ( 0, 14, 4)
1880 19:22:49.293695 Total UI for P1: 0, mck2ui 16
1881 19:22:49.297290 best dqsien dly found for B1: ( 0, 14, 4)
1882 19:22:49.300374 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1883 19:22:49.303727 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1884 19:22:49.303809
1885 19:22:49.306735 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1886 19:22:49.310415 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1887 19:22:49.313739 [Gating] SW calibration Done
1888 19:22:49.313820 ==
1889 19:22:49.316722 Dram Type= 6, Freq= 0, CH_1, rank 1
1890 19:22:49.320353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1891 19:22:49.320435 ==
1892 19:22:49.323532 RX Vref Scan: 0
1893 19:22:49.323613
1894 19:22:49.326739 RX Vref 0 -> 0, step: 1
1895 19:22:49.326820
1896 19:22:49.330146 RX Delay -130 -> 252, step: 16
1897 19:22:49.333735 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1898 19:22:49.336992 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1899 19:22:49.340331 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1900 19:22:49.343821 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1901 19:22:49.350139 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1902 19:22:49.353233 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1903 19:22:49.356808 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1904 19:22:49.360405 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1905 19:22:49.363668 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1906 19:22:49.366968 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1907 19:22:49.373472 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1908 19:22:49.376952 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1909 19:22:49.380114 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1910 19:22:49.383234 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1911 19:22:49.390187 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1912 19:22:49.393696 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1913 19:22:49.393788 ==
1914 19:22:49.396629 Dram Type= 6, Freq= 0, CH_1, rank 1
1915 19:22:49.400155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1916 19:22:49.400263 ==
1917 19:22:49.400355 DQS Delay:
1918 19:22:49.403330 DQS0 = 0, DQS1 = 0
1919 19:22:49.403411 DQM Delay:
1920 19:22:49.406936 DQM0 = 80, DQM1 = 74
1921 19:22:49.407019 DQ Delay:
1922 19:22:49.409971 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =77
1923 19:22:49.413423 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1924 19:22:49.416839 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1925 19:22:49.420313 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1926 19:22:49.420391
1927 19:22:49.420454
1928 19:22:49.420513 ==
1929 19:22:49.423816 Dram Type= 6, Freq= 0, CH_1, rank 1
1930 19:22:49.427034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1931 19:22:49.430397 ==
1932 19:22:49.430480
1933 19:22:49.430543
1934 19:22:49.430603 TX Vref Scan disable
1935 19:22:49.433371 == TX Byte 0 ==
1936 19:22:49.436556 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1937 19:22:49.440504 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1938 19:22:49.443299 == TX Byte 1 ==
1939 19:22:49.446807 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1940 19:22:49.450433 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1941 19:22:49.453311 ==
1942 19:22:49.453392 Dram Type= 6, Freq= 0, CH_1, rank 1
1943 19:22:49.460238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1944 19:22:49.460321 ==
1945 19:22:49.471976 TX Vref=22, minBit 1, minWin=27, winSum=445
1946 19:22:49.475298 TX Vref=24, minBit 1, minWin=27, winSum=449
1947 19:22:49.478815 TX Vref=26, minBit 0, minWin=28, winSum=457
1948 19:22:49.482225 TX Vref=28, minBit 1, minWin=27, winSum=455
1949 19:22:49.485807 TX Vref=30, minBit 1, minWin=27, winSum=455
1950 19:22:49.488484 TX Vref=32, minBit 1, minWin=27, winSum=455
1951 19:22:49.495574 [TxChooseVref] Worse bit 0, Min win 28, Win sum 457, Final Vref 26
1952 19:22:49.495656
1953 19:22:49.498909 Final TX Range 1 Vref 26
1954 19:22:49.499030
1955 19:22:49.499094 ==
1956 19:22:49.501900 Dram Type= 6, Freq= 0, CH_1, rank 1
1957 19:22:49.505418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1958 19:22:49.505548 ==
1959 19:22:49.505629
1960 19:22:49.509076
1961 19:22:49.509158 TX Vref Scan disable
1962 19:22:49.511917 == TX Byte 0 ==
1963 19:22:49.515521 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1964 19:22:49.518542 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1965 19:22:49.521889 == TX Byte 1 ==
1966 19:22:49.525476 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1967 19:22:49.529016 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1968 19:22:49.529096
1969 19:22:49.532382 [DATLAT]
1970 19:22:49.532475 Freq=800, CH1 RK1
1971 19:22:49.532541
1972 19:22:49.535401 DATLAT Default: 0xa
1973 19:22:49.535482 0, 0xFFFF, sum = 0
1974 19:22:49.538865 1, 0xFFFF, sum = 0
1975 19:22:49.538949 2, 0xFFFF, sum = 0
1976 19:22:49.542069 3, 0xFFFF, sum = 0
1977 19:22:49.542151 4, 0xFFFF, sum = 0
1978 19:22:49.545550 5, 0xFFFF, sum = 0
1979 19:22:49.545671 6, 0xFFFF, sum = 0
1980 19:22:49.548681 7, 0xFFFF, sum = 0
1981 19:22:49.548826 8, 0xFFFF, sum = 0
1982 19:22:49.552347 9, 0x0, sum = 1
1983 19:22:49.552430 10, 0x0, sum = 2
1984 19:22:49.555526 11, 0x0, sum = 3
1985 19:22:49.555608 12, 0x0, sum = 4
1986 19:22:49.559044 best_step = 10
1987 19:22:49.559116
1988 19:22:49.559177 ==
1989 19:22:49.561952 Dram Type= 6, Freq= 0, CH_1, rank 1
1990 19:22:49.565378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1991 19:22:49.565474 ==
1992 19:22:49.569133 RX Vref Scan: 0
1993 19:22:49.569213
1994 19:22:49.569276 RX Vref 0 -> 0, step: 1
1995 19:22:49.569336
1996 19:22:49.571937 RX Delay -95 -> 252, step: 8
1997 19:22:49.579075 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
1998 19:22:49.582430 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
1999 19:22:49.585674 iDelay=209, Bit 2, Center 64 (-55 ~ 184) 240
2000 19:22:49.588805 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2001 19:22:49.592159 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2002 19:22:49.599079 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2003 19:22:49.602524 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2004 19:22:49.605828 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2005 19:22:49.608673 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
2006 19:22:49.612051 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2007 19:22:49.615664 iDelay=209, Bit 10, Center 76 (-47 ~ 200) 248
2008 19:22:49.622292 iDelay=209, Bit 11, Center 68 (-55 ~ 192) 248
2009 19:22:49.625780 iDelay=209, Bit 12, Center 84 (-39 ~ 208) 248
2010 19:22:49.629307 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2011 19:22:49.632165 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2012 19:22:49.638965 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2013 19:22:49.639051 ==
2014 19:22:49.642675 Dram Type= 6, Freq= 0, CH_1, rank 1
2015 19:22:49.646061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2016 19:22:49.646147 ==
2017 19:22:49.646212 DQS Delay:
2018 19:22:49.648868 DQS0 = 0, DQS1 = 0
2019 19:22:49.648950 DQM Delay:
2020 19:22:49.652483 DQM0 = 77, DQM1 = 74
2021 19:22:49.652563 DQ Delay:
2022 19:22:49.655646 DQ0 =80, DQ1 =72, DQ2 =64, DQ3 =72
2023 19:22:49.659352 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2024 19:22:49.662467 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =68
2025 19:22:49.666143 DQ12 =84, DQ13 =80, DQ14 =80, DQ15 =80
2026 19:22:49.666225
2027 19:22:49.666289
2028 19:22:49.672573 [DQSOSCAuto] RK1, (LSB)MR18= 0x223a, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
2029 19:22:49.676111 CH1 RK1: MR19=606, MR18=223A
2030 19:22:49.682552 CH1_RK1: MR19=0x606, MR18=0x223A, DQSOSC=395, MR23=63, INC=94, DEC=63
2031 19:22:49.686174 [RxdqsGatingPostProcess] freq 800
2032 19:22:49.689443 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2033 19:22:49.692725 Pre-setting of DQS Precalculation
2034 19:22:49.699618 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2035 19:22:49.706249 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2036 19:22:49.712538 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2037 19:22:49.712623
2038 19:22:49.712687
2039 19:22:49.716304 [Calibration Summary] 1600 Mbps
2040 19:22:49.716386 CH 0, Rank 0
2041 19:22:49.719244 SW Impedance : PASS
2042 19:22:49.722871 DUTY Scan : NO K
2043 19:22:49.722952 ZQ Calibration : PASS
2044 19:22:49.725936 Jitter Meter : NO K
2045 19:22:49.729232 CBT Training : PASS
2046 19:22:49.729338 Write leveling : PASS
2047 19:22:49.732748 RX DQS gating : PASS
2048 19:22:49.736234 RX DQ/DQS(RDDQC) : PASS
2049 19:22:49.736316 TX DQ/DQS : PASS
2050 19:22:49.739097 RX DATLAT : PASS
2051 19:22:49.742622 RX DQ/DQS(Engine): PASS
2052 19:22:49.742703 TX OE : NO K
2053 19:22:49.745672 All Pass.
2054 19:22:49.745753
2055 19:22:49.745817 CH 0, Rank 1
2056 19:22:49.749324 SW Impedance : PASS
2057 19:22:49.749429 DUTY Scan : NO K
2058 19:22:49.752703 ZQ Calibration : PASS
2059 19:22:49.756229 Jitter Meter : NO K
2060 19:22:49.756309 CBT Training : PASS
2061 19:22:49.759031 Write leveling : PASS
2062 19:22:49.759112 RX DQS gating : PASS
2063 19:22:49.762409 RX DQ/DQS(RDDQC) : PASS
2064 19:22:49.765831 TX DQ/DQS : PASS
2065 19:22:49.765913 RX DATLAT : PASS
2066 19:22:49.769204 RX DQ/DQS(Engine): PASS
2067 19:22:49.772433 TX OE : NO K
2068 19:22:49.772539 All Pass.
2069 19:22:49.772624
2070 19:22:49.772685 CH 1, Rank 0
2071 19:22:49.775711 SW Impedance : PASS
2072 19:22:49.779304 DUTY Scan : NO K
2073 19:22:49.779386 ZQ Calibration : PASS
2074 19:22:49.782330 Jitter Meter : NO K
2075 19:22:49.785655 CBT Training : PASS
2076 19:22:49.785736 Write leveling : PASS
2077 19:22:49.789103 RX DQS gating : PASS
2078 19:22:49.792236 RX DQ/DQS(RDDQC) : PASS
2079 19:22:49.792317 TX DQ/DQS : PASS
2080 19:22:49.795650 RX DATLAT : PASS
2081 19:22:49.799035 RX DQ/DQS(Engine): PASS
2082 19:22:49.799115 TX OE : NO K
2083 19:22:49.802397 All Pass.
2084 19:22:49.802478
2085 19:22:49.802542 CH 1, Rank 1
2086 19:22:49.805746 SW Impedance : PASS
2087 19:22:49.805827 DUTY Scan : NO K
2088 19:22:49.808767 ZQ Calibration : PASS
2089 19:22:49.808849 Jitter Meter : NO K
2090 19:22:49.812053 CBT Training : PASS
2091 19:22:49.815800 Write leveling : PASS
2092 19:22:49.815882 RX DQS gating : PASS
2093 19:22:49.818980 RX DQ/DQS(RDDQC) : PASS
2094 19:22:49.822300 TX DQ/DQS : PASS
2095 19:22:49.822383 RX DATLAT : PASS
2096 19:22:49.825788 RX DQ/DQS(Engine): PASS
2097 19:22:49.828842 TX OE : NO K
2098 19:22:49.828924 All Pass.
2099 19:22:49.828987
2100 19:22:49.832403 DramC Write-DBI off
2101 19:22:49.832486 PER_BANK_REFRESH: Hybrid Mode
2102 19:22:49.835366 TX_TRACKING: ON
2103 19:22:49.839062 [GetDramInforAfterCalByMRR] Vendor 6.
2104 19:22:49.842439 [GetDramInforAfterCalByMRR] Revision 606.
2105 19:22:49.845805 [GetDramInforAfterCalByMRR] Revision 2 0.
2106 19:22:49.845889 MR0 0x3b3b
2107 19:22:49.848975 MR8 0x5151
2108 19:22:49.852458 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2109 19:22:49.852541
2110 19:22:49.852605 MR0 0x3b3b
2111 19:22:49.852708 MR8 0x5151
2112 19:22:49.858924 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2113 19:22:49.859005
2114 19:22:49.865454 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2115 19:22:49.868808 [FAST_K] Save calibration result to emmc
2116 19:22:49.872101 [FAST_K] Save calibration result to emmc
2117 19:22:49.875556 dram_init: config_dvfs: 1
2118 19:22:49.878941 dramc_set_vcore_voltage set vcore to 662500
2119 19:22:49.882302 Read voltage for 1200, 2
2120 19:22:49.882382 Vio18 = 0
2121 19:22:49.885289 Vcore = 662500
2122 19:22:49.885396 Vdram = 0
2123 19:22:49.885487 Vddq = 0
2124 19:22:49.888759 Vmddr = 0
2125 19:22:49.892154 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2126 19:22:49.898748 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2127 19:22:49.898832 MEM_TYPE=3, freq_sel=15
2128 19:22:49.902158 sv_algorithm_assistance_LP4_1600
2129 19:22:49.905857 ============ PULL DRAM RESETB DOWN ============
2130 19:22:49.912327 ========== PULL DRAM RESETB DOWN end =========
2131 19:22:49.915844 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2132 19:22:49.918593 ===================================
2133 19:22:49.922090 LPDDR4 DRAM CONFIGURATION
2134 19:22:49.925500 ===================================
2135 19:22:49.925621 EX_ROW_EN[0] = 0x0
2136 19:22:49.929058 EX_ROW_EN[1] = 0x0
2137 19:22:49.929139 LP4Y_EN = 0x0
2138 19:22:49.932320 WORK_FSP = 0x0
2139 19:22:49.932403 WL = 0x4
2140 19:22:49.935657 RL = 0x4
2141 19:22:49.939240 BL = 0x2
2142 19:22:49.939322 RPST = 0x0
2143 19:22:49.942370 RD_PRE = 0x0
2144 19:22:49.942451 WR_PRE = 0x1
2145 19:22:49.945351 WR_PST = 0x0
2146 19:22:49.945457 DBI_WR = 0x0
2147 19:22:49.948684 DBI_RD = 0x0
2148 19:22:49.948779 OTF = 0x1
2149 19:22:49.952337 ===================================
2150 19:22:49.955249 ===================================
2151 19:22:49.958738 ANA top config
2152 19:22:49.958819 ===================================
2153 19:22:49.962105 DLL_ASYNC_EN = 0
2154 19:22:49.965773 ALL_SLAVE_EN = 0
2155 19:22:49.968745 NEW_RANK_MODE = 1
2156 19:22:49.972156 DLL_IDLE_MODE = 1
2157 19:22:49.972238 LP45_APHY_COMB_EN = 1
2158 19:22:49.975527 TX_ODT_DIS = 1
2159 19:22:49.979034 NEW_8X_MODE = 1
2160 19:22:49.982487 ===================================
2161 19:22:49.985946 ===================================
2162 19:22:49.989245 data_rate = 2400
2163 19:22:49.992015 CKR = 1
2164 19:22:49.992098 DQ_P2S_RATIO = 8
2165 19:22:49.995518 ===================================
2166 19:22:49.998968 CA_P2S_RATIO = 8
2167 19:22:50.002662 DQ_CA_OPEN = 0
2168 19:22:50.005612 DQ_SEMI_OPEN = 0
2169 19:22:50.009379 CA_SEMI_OPEN = 0
2170 19:22:50.012612 CA_FULL_RATE = 0
2171 19:22:50.012700 DQ_CKDIV4_EN = 0
2172 19:22:50.015423 CA_CKDIV4_EN = 0
2173 19:22:50.019062 CA_PREDIV_EN = 0
2174 19:22:50.022364 PH8_DLY = 17
2175 19:22:50.025754 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2176 19:22:50.029297 DQ_AAMCK_DIV = 4
2177 19:22:50.029380 CA_AAMCK_DIV = 4
2178 19:22:50.032099 CA_ADMCK_DIV = 4
2179 19:22:50.035676 DQ_TRACK_CA_EN = 0
2180 19:22:50.039137 CA_PICK = 1200
2181 19:22:50.042714 CA_MCKIO = 1200
2182 19:22:50.045800 MCKIO_SEMI = 0
2183 19:22:50.048724 PLL_FREQ = 2366
2184 19:22:50.048806 DQ_UI_PI_RATIO = 32
2185 19:22:50.051862 CA_UI_PI_RATIO = 0
2186 19:22:50.055519 ===================================
2187 19:22:50.058746 ===================================
2188 19:22:50.062166 memory_type:LPDDR4
2189 19:22:50.065595 GP_NUM : 10
2190 19:22:50.065678 SRAM_EN : 1
2191 19:22:50.068555 MD32_EN : 0
2192 19:22:50.072058 ===================================
2193 19:22:50.075675 [ANA_INIT] >>>>>>>>>>>>>>
2194 19:22:50.075757 <<<<<< [CONFIGURE PHASE]: ANA_TX
2195 19:22:50.078907 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2196 19:22:50.082251 ===================================
2197 19:22:50.085282 data_rate = 2400,PCW = 0X5b00
2198 19:22:50.088822 ===================================
2199 19:22:50.092303 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2200 19:22:50.098654 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2201 19:22:50.105390 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2202 19:22:50.108881 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2203 19:22:50.112531 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2204 19:22:50.115430 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2205 19:22:50.118874 [ANA_INIT] flow start
2206 19:22:50.118987 [ANA_INIT] PLL >>>>>>>>
2207 19:22:50.121986 [ANA_INIT] PLL <<<<<<<<
2208 19:22:50.125634 [ANA_INIT] MIDPI >>>>>>>>
2209 19:22:50.125717 [ANA_INIT] MIDPI <<<<<<<<
2210 19:22:50.129014 [ANA_INIT] DLL >>>>>>>>
2211 19:22:50.131853 [ANA_INIT] DLL <<<<<<<<
2212 19:22:50.131937 [ANA_INIT] flow end
2213 19:22:50.139107 ============ LP4 DIFF to SE enter ============
2214 19:22:50.142015 ============ LP4 DIFF to SE exit ============
2215 19:22:50.142115 [ANA_INIT] <<<<<<<<<<<<<
2216 19:22:50.145548 [Flow] Enable top DCM control >>>>>
2217 19:22:50.148485 [Flow] Enable top DCM control <<<<<
2218 19:22:50.152289 Enable DLL master slave shuffle
2219 19:22:50.158675 ==============================================================
2220 19:22:50.162010 Gating Mode config
2221 19:22:50.165323 ==============================================================
2222 19:22:50.168797 Config description:
2223 19:22:50.178552 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2224 19:22:50.185502 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2225 19:22:50.188651 SELPH_MODE 0: By rank 1: By Phase
2226 19:22:50.195177 ==============================================================
2227 19:22:50.198724 GAT_TRACK_EN = 1
2228 19:22:50.202095 RX_GATING_MODE = 2
2229 19:22:50.205031 RX_GATING_TRACK_MODE = 2
2230 19:22:50.205117 SELPH_MODE = 1
2231 19:22:50.208389 PICG_EARLY_EN = 1
2232 19:22:50.211914 VALID_LAT_VALUE = 1
2233 19:22:50.218374 ==============================================================
2234 19:22:50.221749 Enter into Gating configuration >>>>
2235 19:22:50.225271 Exit from Gating configuration <<<<
2236 19:22:50.228355 Enter into DVFS_PRE_config >>>>>
2237 19:22:50.238246 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2238 19:22:50.241463 Exit from DVFS_PRE_config <<<<<
2239 19:22:50.245205 Enter into PICG configuration >>>>
2240 19:22:50.248731 Exit from PICG configuration <<<<
2241 19:22:50.251648 [RX_INPUT] configuration >>>>>
2242 19:22:50.255238 [RX_INPUT] configuration <<<<<
2243 19:22:50.258168 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2244 19:22:50.265088 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2245 19:22:50.271806 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2246 19:22:50.278275 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2247 19:22:50.281635 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2248 19:22:50.288618 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2249 19:22:50.291278 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2250 19:22:50.298051 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2251 19:22:50.301410 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2252 19:22:50.305063 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2253 19:22:50.307990 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2254 19:22:50.314914 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2255 19:22:50.318106 ===================================
2256 19:22:50.318219 LPDDR4 DRAM CONFIGURATION
2257 19:22:50.321345 ===================================
2258 19:22:50.324794 EX_ROW_EN[0] = 0x0
2259 19:22:50.327904 EX_ROW_EN[1] = 0x0
2260 19:22:50.328011 LP4Y_EN = 0x0
2261 19:22:50.331635 WORK_FSP = 0x0
2262 19:22:50.331742 WL = 0x4
2263 19:22:50.334931 RL = 0x4
2264 19:22:50.335051 BL = 0x2
2265 19:22:50.337922 RPST = 0x0
2266 19:22:50.338024 RD_PRE = 0x0
2267 19:22:50.341374 WR_PRE = 0x1
2268 19:22:50.341500 WR_PST = 0x0
2269 19:22:50.344908 DBI_WR = 0x0
2270 19:22:50.345006 DBI_RD = 0x0
2271 19:22:50.348437 OTF = 0x1
2272 19:22:50.351108 ===================================
2273 19:22:50.354795 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2274 19:22:50.358373 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2275 19:22:50.364981 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2276 19:22:50.367805 ===================================
2277 19:22:50.367915 LPDDR4 DRAM CONFIGURATION
2278 19:22:50.371273 ===================================
2279 19:22:50.374406 EX_ROW_EN[0] = 0x10
2280 19:22:50.377820 EX_ROW_EN[1] = 0x0
2281 19:22:50.377930 LP4Y_EN = 0x0
2282 19:22:50.381399 WORK_FSP = 0x0
2283 19:22:50.381531 WL = 0x4
2284 19:22:50.384676 RL = 0x4
2285 19:22:50.384794 BL = 0x2
2286 19:22:50.387980 RPST = 0x0
2287 19:22:50.388099 RD_PRE = 0x0
2288 19:22:50.391221 WR_PRE = 0x1
2289 19:22:50.391330 WR_PST = 0x0
2290 19:22:50.394876 DBI_WR = 0x0
2291 19:22:50.394977 DBI_RD = 0x0
2292 19:22:50.398489 OTF = 0x1
2293 19:22:50.401385 ===================================
2294 19:22:50.407899 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2295 19:22:50.408035 ==
2296 19:22:50.411481 Dram Type= 6, Freq= 0, CH_0, rank 0
2297 19:22:50.414483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2298 19:22:50.414587 ==
2299 19:22:50.417887 [Duty_Offset_Calibration]
2300 19:22:50.417989 B0:2 B1:0 CA:3
2301 19:22:50.418087
2302 19:22:50.421372 [DutyScan_Calibration_Flow] k_type=0
2303 19:22:50.431212
2304 19:22:50.431327 ==CLK 0==
2305 19:22:50.434307 Final CLK duty delay cell = 0
2306 19:22:50.437667 [0] MAX Duty = 5062%(X100), DQS PI = 20
2307 19:22:50.440837 [0] MIN Duty = 4875%(X100), DQS PI = 58
2308 19:22:50.440922 [0] AVG Duty = 4968%(X100)
2309 19:22:50.444227
2310 19:22:50.444303 CH0 CLK Duty spec in!! Max-Min= 187%
2311 19:22:50.451495 [DutyScan_Calibration_Flow] ====Done====
2312 19:22:50.451607
2313 19:22:50.454340 [DutyScan_Calibration_Flow] k_type=1
2314 19:22:50.469414
2315 19:22:50.469619 ==DQS 0 ==
2316 19:22:50.473009 Final DQS duty delay cell = 0
2317 19:22:50.476468 [0] MAX Duty = 5062%(X100), DQS PI = 16
2318 19:22:50.479817 [0] MIN Duty = 4907%(X100), DQS PI = 2
2319 19:22:50.479926 [0] AVG Duty = 4984%(X100)
2320 19:22:50.482879
2321 19:22:50.482976 ==DQS 1 ==
2322 19:22:50.486114 Final DQS duty delay cell = -4
2323 19:22:50.490073 [-4] MAX Duty = 5000%(X100), DQS PI = 36
2324 19:22:50.493178 [-4] MIN Duty = 4875%(X100), DQS PI = 14
2325 19:22:50.496549 [-4] AVG Duty = 4937%(X100)
2326 19:22:50.496665
2327 19:22:50.499713 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2328 19:22:50.499834
2329 19:22:50.503408 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2330 19:22:50.506623 [DutyScan_Calibration_Flow] ====Done====
2331 19:22:50.506732
2332 19:22:50.509971 [DutyScan_Calibration_Flow] k_type=3
2333 19:22:50.527063
2334 19:22:50.527224 ==DQM 0 ==
2335 19:22:50.530434 Final DQM duty delay cell = 0
2336 19:22:50.533706 [0] MAX Duty = 5124%(X100), DQS PI = 12
2337 19:22:50.537417 [0] MIN Duty = 4876%(X100), DQS PI = 48
2338 19:22:50.540347 [0] AVG Duty = 5000%(X100)
2339 19:22:50.540466
2340 19:22:50.540562 ==DQM 1 ==
2341 19:22:50.543742 Final DQM duty delay cell = 4
2342 19:22:50.546859 [4] MAX Duty = 5124%(X100), DQS PI = 52
2343 19:22:50.550310 [4] MIN Duty = 5000%(X100), DQS PI = 12
2344 19:22:50.553862 [4] AVG Duty = 5062%(X100)
2345 19:22:50.553994
2346 19:22:50.556893 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2347 19:22:50.557002
2348 19:22:50.560375 CH0 DQM 1 Duty spec in!! Max-Min= 124%
2349 19:22:50.563873 [DutyScan_Calibration_Flow] ====Done====
2350 19:22:50.564005
2351 19:22:50.567198 [DutyScan_Calibration_Flow] k_type=2
2352 19:22:50.582102
2353 19:22:50.582227 ==DQ 0 ==
2354 19:22:50.585588 Final DQ duty delay cell = -4
2355 19:22:50.589115 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2356 19:22:50.592062 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2357 19:22:50.595468 [-4] AVG Duty = 4969%(X100)
2358 19:22:50.595561
2359 19:22:50.595627 ==DQ 1 ==
2360 19:22:50.598664 Final DQ duty delay cell = -4
2361 19:22:50.601987 [-4] MAX Duty = 4969%(X100), DQS PI = 0
2362 19:22:50.605352 [-4] MIN Duty = 4876%(X100), DQS PI = 20
2363 19:22:50.608745 [-4] AVG Duty = 4922%(X100)
2364 19:22:50.608830
2365 19:22:50.612310 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2366 19:22:50.612394
2367 19:22:50.615446 CH0 DQ 1 Duty spec in!! Max-Min= 93%
2368 19:22:50.618665 [DutyScan_Calibration_Flow] ====Done====
2369 19:22:50.618777 ==
2370 19:22:50.622088 Dram Type= 6, Freq= 0, CH_1, rank 0
2371 19:22:50.625621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2372 19:22:50.625706 ==
2373 19:22:50.629222 [Duty_Offset_Calibration]
2374 19:22:50.629305 B0:1 B1:-2 CA:0
2375 19:22:50.629371
2376 19:22:50.632155 [DutyScan_Calibration_Flow] k_type=0
2377 19:22:50.642823
2378 19:22:50.642936 ==CLK 0==
2379 19:22:50.646461 Final CLK duty delay cell = 0
2380 19:22:50.649293 [0] MAX Duty = 5031%(X100), DQS PI = 16
2381 19:22:50.652665 [0] MIN Duty = 4844%(X100), DQS PI = 2
2382 19:22:50.652749 [0] AVG Duty = 4937%(X100)
2383 19:22:50.655841
2384 19:22:50.655923 CH1 CLK Duty spec in!! Max-Min= 187%
2385 19:22:50.662410 [DutyScan_Calibration_Flow] ====Done====
2386 19:22:50.662494
2387 19:22:50.665820 [DutyScan_Calibration_Flow] k_type=1
2388 19:22:50.681112
2389 19:22:50.681225 ==DQS 0 ==
2390 19:22:50.684541 Final DQS duty delay cell = -4
2391 19:22:50.688040 [-4] MAX Duty = 5000%(X100), DQS PI = 24
2392 19:22:50.691115 [-4] MIN Duty = 4876%(X100), DQS PI = 48
2393 19:22:50.694695 [-4] AVG Duty = 4938%(X100)
2394 19:22:50.694778
2395 19:22:50.694844 ==DQS 1 ==
2396 19:22:50.698046 Final DQS duty delay cell = 0
2397 19:22:50.700962 [0] MAX Duty = 5062%(X100), DQS PI = 0
2398 19:22:50.704422 [0] MIN Duty = 4875%(X100), DQS PI = 26
2399 19:22:50.707777 [0] AVG Duty = 4968%(X100)
2400 19:22:50.707860
2401 19:22:50.710872 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2402 19:22:50.710953
2403 19:22:50.714483 CH1 DQS 1 Duty spec in!! Max-Min= 187%
2404 19:22:50.718089 [DutyScan_Calibration_Flow] ====Done====
2405 19:22:50.718172
2406 19:22:50.721357 [DutyScan_Calibration_Flow] k_type=3
2407 19:22:50.737751
2408 19:22:50.737872 ==DQM 0 ==
2409 19:22:50.741299 Final DQM duty delay cell = 0
2410 19:22:50.744734 [0] MAX Duty = 5000%(X100), DQS PI = 22
2411 19:22:50.748145 [0] MIN Duty = 4876%(X100), DQS PI = 0
2412 19:22:50.748228 [0] AVG Duty = 4938%(X100)
2413 19:22:50.751247
2414 19:22:50.751328 ==DQM 1 ==
2415 19:22:50.754749 Final DQM duty delay cell = 0
2416 19:22:50.758157 [0] MAX Duty = 5031%(X100), DQS PI = 36
2417 19:22:50.761394 [0] MIN Duty = 4907%(X100), DQS PI = 2
2418 19:22:50.761526 [0] AVG Duty = 4969%(X100)
2419 19:22:50.761607
2420 19:22:50.767648 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2421 19:22:50.767727
2422 19:22:50.771152 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2423 19:22:50.774524 [DutyScan_Calibration_Flow] ====Done====
2424 19:22:50.774600
2425 19:22:50.778009 [DutyScan_Calibration_Flow] k_type=2
2426 19:22:50.794415
2427 19:22:50.794523 ==DQ 0 ==
2428 19:22:50.797369 Final DQ duty delay cell = 0
2429 19:22:50.800871 [0] MAX Duty = 5062%(X100), DQS PI = 12
2430 19:22:50.804507 [0] MIN Duty = 4938%(X100), DQS PI = 56
2431 19:22:50.804589 [0] AVG Duty = 5000%(X100)
2432 19:22:50.804653
2433 19:22:50.807397 ==DQ 1 ==
2434 19:22:50.810825 Final DQ duty delay cell = 0
2435 19:22:50.814155 [0] MAX Duty = 5125%(X100), DQS PI = 36
2436 19:22:50.817386 [0] MIN Duty = 4969%(X100), DQS PI = 24
2437 19:22:50.817468 [0] AVG Duty = 5047%(X100)
2438 19:22:50.817581
2439 19:22:50.820771 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2440 19:22:50.824354
2441 19:22:50.827366 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2442 19:22:50.830828 [DutyScan_Calibration_Flow] ====Done====
2443 19:22:50.834207 nWR fixed to 30
2444 19:22:50.834298 [ModeRegInit_LP4] CH0 RK0
2445 19:22:50.838149 [ModeRegInit_LP4] CH0 RK1
2446 19:22:50.840936 [ModeRegInit_LP4] CH1 RK0
2447 19:22:50.841045 [ModeRegInit_LP4] CH1 RK1
2448 19:22:50.844151 match AC timing 7
2449 19:22:50.847525 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2450 19:22:50.851085 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2451 19:22:50.857852 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2452 19:22:50.861202 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2453 19:22:50.867534 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2454 19:22:50.867620 ==
2455 19:22:50.870871 Dram Type= 6, Freq= 0, CH_0, rank 0
2456 19:22:50.874136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2457 19:22:50.874220 ==
2458 19:22:50.881165 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2459 19:22:50.884045 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2460 19:22:50.894541 [CA 0] Center 40 (10~71) winsize 62
2461 19:22:50.897714 [CA 1] Center 39 (9~70) winsize 62
2462 19:22:50.901417 [CA 2] Center 36 (6~66) winsize 61
2463 19:22:50.904327 [CA 3] Center 35 (5~66) winsize 62
2464 19:22:50.907952 [CA 4] Center 34 (4~65) winsize 62
2465 19:22:50.911230 [CA 5] Center 33 (3~63) winsize 61
2466 19:22:50.911312
2467 19:22:50.914168 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2468 19:22:50.914263
2469 19:22:50.917679 [CATrainingPosCal] consider 1 rank data
2470 19:22:50.921116 u2DelayCellTimex100 = 270/100 ps
2471 19:22:50.924510 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2472 19:22:50.927818 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2473 19:22:50.934733 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2474 19:22:50.937667 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2475 19:22:50.941266 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2476 19:22:50.944742 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2477 19:22:50.944829
2478 19:22:50.948080 CA PerBit enable=1, Macro0, CA PI delay=33
2479 19:22:50.948162
2480 19:22:50.951318 [CBTSetCACLKResult] CA Dly = 33
2481 19:22:50.951399 CS Dly: 7 (0~38)
2482 19:22:50.954572 ==
2483 19:22:50.954653 Dram Type= 6, Freq= 0, CH_0, rank 1
2484 19:22:50.961164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2485 19:22:50.961250 ==
2486 19:22:50.964476 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2487 19:22:50.970668 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2488 19:22:50.980380 [CA 0] Center 40 (10~71) winsize 62
2489 19:22:50.983853 [CA 1] Center 39 (9~70) winsize 62
2490 19:22:50.987340 [CA 2] Center 35 (5~66) winsize 62
2491 19:22:50.990874 [CA 3] Center 35 (5~66) winsize 62
2492 19:22:50.993912 [CA 4] Center 34 (4~65) winsize 62
2493 19:22:50.997436 [CA 5] Center 33 (3~64) winsize 62
2494 19:22:50.997565
2495 19:22:51.000985 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2496 19:22:51.001082
2497 19:22:51.003738 [CATrainingPosCal] consider 2 rank data
2498 19:22:51.007379 u2DelayCellTimex100 = 270/100 ps
2499 19:22:51.010616 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2500 19:22:51.014058 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2501 19:22:51.020520 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2502 19:22:51.024091 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2503 19:22:51.027012 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2504 19:22:51.030551 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2505 19:22:51.030624
2506 19:22:51.033907 CA PerBit enable=1, Macro0, CA PI delay=33
2507 19:22:51.034016
2508 19:22:51.037106 [CBTSetCACLKResult] CA Dly = 33
2509 19:22:51.037187 CS Dly: 8 (0~40)
2510 19:22:51.037263
2511 19:22:51.040667 ----->DramcWriteLeveling(PI) begin...
2512 19:22:51.044095 ==
2513 19:22:51.044176 Dram Type= 6, Freq= 0, CH_0, rank 0
2514 19:22:51.050586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2515 19:22:51.050687 ==
2516 19:22:51.054109 Write leveling (Byte 0): 33 => 33
2517 19:22:51.057462 Write leveling (Byte 1): 30 => 30
2518 19:22:51.060735 DramcWriteLeveling(PI) end<-----
2519 19:22:51.060809
2520 19:22:51.060871 ==
2521 19:22:51.063748 Dram Type= 6, Freq= 0, CH_0, rank 0
2522 19:22:51.067157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2523 19:22:51.067231 ==
2524 19:22:51.070361 [Gating] SW mode calibration
2525 19:22:51.077517 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2526 19:22:51.080487 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2527 19:22:51.087609 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2528 19:22:51.090738 0 15 4 | B1->B0 | 2929 3434 | 0 0 | (0 0) (0 0)
2529 19:22:51.093920 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2530 19:22:51.100456 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2531 19:22:51.103900 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2532 19:22:51.107410 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2533 19:22:51.113951 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2534 19:22:51.117390 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2535 19:22:51.120555 1 0 0 | B1->B0 | 2e2e 2626 | 0 1 | (0 0) (1 0)
2536 19:22:51.127403 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2537 19:22:51.130989 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2538 19:22:51.133997 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2539 19:22:51.137520 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2540 19:22:51.144239 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2541 19:22:51.147612 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2542 19:22:51.150685 1 0 28 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
2543 19:22:51.157763 1 1 0 | B1->B0 | 2d2d 3434 | 0 0 | (0 0) (0 0)
2544 19:22:51.160807 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2545 19:22:51.164366 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2546 19:22:51.170930 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2547 19:22:51.174342 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2548 19:22:51.177688 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2549 19:22:51.184405 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2550 19:22:51.187755 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2551 19:22:51.191350 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2552 19:22:51.197497 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2553 19:22:51.201078 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 19:22:51.204105 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 19:22:51.210633 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 19:22:51.214107 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 19:22:51.217458 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 19:22:51.224376 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 19:22:51.227297 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 19:22:51.230875 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 19:22:51.237691 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 19:22:51.240656 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 19:22:51.244162 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 19:22:51.247623 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 19:22:51.254021 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 19:22:51.257697 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 19:22:51.260602 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2568 19:22:51.264196 Total UI for P1: 0, mck2ui 16
2569 19:22:51.267301 best dqsien dly found for B0: ( 1, 3, 30)
2570 19:22:51.273851 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2571 19:22:51.277628 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2572 19:22:51.280961 Total UI for P1: 0, mck2ui 16
2573 19:22:51.284500 best dqsien dly found for B1: ( 1, 4, 2)
2574 19:22:51.287341 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2575 19:22:51.291083 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2576 19:22:51.291166
2577 19:22:51.294149 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2578 19:22:51.297825 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2579 19:22:51.301238 [Gating] SW calibration Done
2580 19:22:51.301329 ==
2581 19:22:51.304150 Dram Type= 6, Freq= 0, CH_0, rank 0
2582 19:22:51.307572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2583 19:22:51.307672 ==
2584 19:22:51.310770 RX Vref Scan: 0
2585 19:22:51.310844
2586 19:22:51.314059 RX Vref 0 -> 0, step: 1
2587 19:22:51.314141
2588 19:22:51.314205 RX Delay -40 -> 252, step: 8
2589 19:22:51.320794 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2590 19:22:51.324337 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2591 19:22:51.327878 iDelay=200, Bit 2, Center 111 (32 ~ 191) 160
2592 19:22:51.330821 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2593 19:22:51.334307 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2594 19:22:51.341001 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2595 19:22:51.343991 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2596 19:22:51.347585 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2597 19:22:51.351124 iDelay=200, Bit 8, Center 95 (16 ~ 175) 160
2598 19:22:51.354506 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2599 19:22:51.360578 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2600 19:22:51.364227 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
2601 19:22:51.367346 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2602 19:22:51.370735 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2603 19:22:51.374404 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2604 19:22:51.380796 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2605 19:22:51.380877 ==
2606 19:22:51.383968 Dram Type= 6, Freq= 0, CH_0, rank 0
2607 19:22:51.387409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2608 19:22:51.387481 ==
2609 19:22:51.387541 DQS Delay:
2610 19:22:51.391100 DQS0 = 0, DQS1 = 0
2611 19:22:51.391181 DQM Delay:
2612 19:22:51.393954 DQM0 = 112, DQM1 = 103
2613 19:22:51.394048 DQ Delay:
2614 19:22:51.397560 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2615 19:22:51.400711 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2616 19:22:51.404186 DQ8 =95, DQ9 =87, DQ10 =103, DQ11 =99
2617 19:22:51.407250 DQ12 =107, DQ13 =107, DQ14 =115, DQ15 =111
2618 19:22:51.407325
2619 19:22:51.407386
2620 19:22:51.407449 ==
2621 19:22:51.410811 Dram Type= 6, Freq= 0, CH_0, rank 0
2622 19:22:51.417524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2623 19:22:51.417624 ==
2624 19:22:51.417687
2625 19:22:51.417751
2626 19:22:51.417806 TX Vref Scan disable
2627 19:22:51.420887 == TX Byte 0 ==
2628 19:22:51.424540 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2629 19:22:51.430950 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2630 19:22:51.431069 == TX Byte 1 ==
2631 19:22:51.434603 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2632 19:22:51.440930 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2633 19:22:51.441014 ==
2634 19:22:51.444260 Dram Type= 6, Freq= 0, CH_0, rank 0
2635 19:22:51.447590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2636 19:22:51.447710 ==
2637 19:22:51.459387 TX Vref=22, minBit 6, minWin=25, winSum=416
2638 19:22:51.462289 TX Vref=24, minBit 0, minWin=26, winSum=421
2639 19:22:51.465767 TX Vref=26, minBit 1, minWin=26, winSum=426
2640 19:22:51.468922 TX Vref=28, minBit 4, minWin=26, winSum=433
2641 19:22:51.472551 TX Vref=30, minBit 0, minWin=27, winSum=434
2642 19:22:51.476197 TX Vref=32, minBit 2, minWin=26, winSum=429
2643 19:22:51.482757 [TxChooseVref] Worse bit 0, Min win 27, Win sum 434, Final Vref 30
2644 19:22:51.482861
2645 19:22:51.485661 Final TX Range 1 Vref 30
2646 19:22:51.485847
2647 19:22:51.485908 ==
2648 19:22:51.488948 Dram Type= 6, Freq= 0, CH_0, rank 0
2649 19:22:51.492398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2650 19:22:51.492500 ==
2651 19:22:51.492589
2652 19:22:51.492675
2653 19:22:51.495921 TX Vref Scan disable
2654 19:22:51.499434 == TX Byte 0 ==
2655 19:22:51.502404 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2656 19:22:51.505961 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2657 19:22:51.509411 == TX Byte 1 ==
2658 19:22:51.512280 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2659 19:22:51.515666 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2660 19:22:51.515750
2661 19:22:51.518823 [DATLAT]
2662 19:22:51.518903 Freq=1200, CH0 RK0
2663 19:22:51.518968
2664 19:22:51.522143 DATLAT Default: 0xd
2665 19:22:51.522214 0, 0xFFFF, sum = 0
2666 19:22:51.525881 1, 0xFFFF, sum = 0
2667 19:22:51.525963 2, 0xFFFF, sum = 0
2668 19:22:51.528988 3, 0xFFFF, sum = 0
2669 19:22:51.529070 4, 0xFFFF, sum = 0
2670 19:22:51.532575 5, 0xFFFF, sum = 0
2671 19:22:51.532667 6, 0xFFFF, sum = 0
2672 19:22:51.535690 7, 0xFFFF, sum = 0
2673 19:22:51.539137 8, 0xFFFF, sum = 0
2674 19:22:51.539238 9, 0xFFFF, sum = 0
2675 19:22:51.542609 10, 0xFFFF, sum = 0
2676 19:22:51.542691 11, 0xFFFF, sum = 0
2677 19:22:51.545684 12, 0x0, sum = 1
2678 19:22:51.545778 13, 0x0, sum = 2
2679 19:22:51.545846 14, 0x0, sum = 3
2680 19:22:51.548961 15, 0x0, sum = 4
2681 19:22:51.549076 best_step = 13
2682 19:22:51.549149
2683 19:22:51.552388 ==
2684 19:22:51.552494 Dram Type= 6, Freq= 0, CH_0, rank 0
2685 19:22:51.559227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2686 19:22:51.559343 ==
2687 19:22:51.559439 RX Vref Scan: 1
2688 19:22:51.559529
2689 19:22:51.562758 Set Vref Range= 32 -> 127
2690 19:22:51.562827
2691 19:22:51.565755 RX Vref 32 -> 127, step: 1
2692 19:22:51.565829
2693 19:22:51.569256 RX Delay -37 -> 252, step: 4
2694 19:22:51.569350
2695 19:22:51.572652 Set Vref, RX VrefLevel [Byte0]: 32
2696 19:22:51.576107 [Byte1]: 32
2697 19:22:51.576180
2698 19:22:51.579033 Set Vref, RX VrefLevel [Byte0]: 33
2699 19:22:51.582580 [Byte1]: 33
2700 19:22:51.582660
2701 19:22:51.585441 Set Vref, RX VrefLevel [Byte0]: 34
2702 19:22:51.589025 [Byte1]: 34
2703 19:22:51.593770
2704 19:22:51.593862 Set Vref, RX VrefLevel [Byte0]: 35
2705 19:22:51.597095 [Byte1]: 35
2706 19:22:51.601705
2707 19:22:51.601792 Set Vref, RX VrefLevel [Byte0]: 36
2708 19:22:51.604717 [Byte1]: 36
2709 19:22:51.609348
2710 19:22:51.609420 Set Vref, RX VrefLevel [Byte0]: 37
2711 19:22:51.612875 [Byte1]: 37
2712 19:22:51.617653
2713 19:22:51.617724 Set Vref, RX VrefLevel [Byte0]: 38
2714 19:22:51.620602 [Byte1]: 38
2715 19:22:51.625441
2716 19:22:51.625558 Set Vref, RX VrefLevel [Byte0]: 39
2717 19:22:51.628972 [Byte1]: 39
2718 19:22:51.633478
2719 19:22:51.633602 Set Vref, RX VrefLevel [Byte0]: 40
2720 19:22:51.637078 [Byte1]: 40
2721 19:22:51.641304
2722 19:22:51.641402 Set Vref, RX VrefLevel [Byte0]: 41
2723 19:22:51.644867 [Byte1]: 41
2724 19:22:51.649775
2725 19:22:51.649847 Set Vref, RX VrefLevel [Byte0]: 42
2726 19:22:51.652928 [Byte1]: 42
2727 19:22:51.657405
2728 19:22:51.657502 Set Vref, RX VrefLevel [Byte0]: 43
2729 19:22:51.660668 [Byte1]: 43
2730 19:22:51.665581
2731 19:22:51.665660 Set Vref, RX VrefLevel [Byte0]: 44
2732 19:22:51.668762 [Byte1]: 44
2733 19:22:51.673293
2734 19:22:51.673367 Set Vref, RX VrefLevel [Byte0]: 45
2735 19:22:51.676904 [Byte1]: 45
2736 19:22:51.681406
2737 19:22:51.681506 Set Vref, RX VrefLevel [Byte0]: 46
2738 19:22:51.685035 [Byte1]: 46
2739 19:22:51.689241
2740 19:22:51.689311 Set Vref, RX VrefLevel [Byte0]: 47
2741 19:22:51.692715 [Byte1]: 47
2742 19:22:51.697418
2743 19:22:51.697544 Set Vref, RX VrefLevel [Byte0]: 48
2744 19:22:51.700738 [Byte1]: 48
2745 19:22:51.705759
2746 19:22:51.705839 Set Vref, RX VrefLevel [Byte0]: 49
2747 19:22:51.708762 [Byte1]: 49
2748 19:22:51.713405
2749 19:22:51.713485 Set Vref, RX VrefLevel [Byte0]: 50
2750 19:22:51.717010 [Byte1]: 50
2751 19:22:51.721811
2752 19:22:51.721894 Set Vref, RX VrefLevel [Byte0]: 51
2753 19:22:51.724596 [Byte1]: 51
2754 19:22:51.729384
2755 19:22:51.729463 Set Vref, RX VrefLevel [Byte0]: 52
2756 19:22:51.732790 [Byte1]: 52
2757 19:22:51.737490
2758 19:22:51.737595 Set Vref, RX VrefLevel [Byte0]: 53
2759 19:22:51.740631 [Byte1]: 53
2760 19:22:51.745412
2761 19:22:51.745492 Set Vref, RX VrefLevel [Byte0]: 54
2762 19:22:51.748802 [Byte1]: 54
2763 19:22:51.753568
2764 19:22:51.753647 Set Vref, RX VrefLevel [Byte0]: 55
2765 19:22:51.756568 [Byte1]: 55
2766 19:22:51.761812
2767 19:22:51.761891 Set Vref, RX VrefLevel [Byte0]: 56
2768 19:22:51.764926 [Byte1]: 56
2769 19:22:51.769781
2770 19:22:51.769861 Set Vref, RX VrefLevel [Byte0]: 57
2771 19:22:51.773001 [Byte1]: 57
2772 19:22:51.777439
2773 19:22:51.777560 Set Vref, RX VrefLevel [Byte0]: 58
2774 19:22:51.780865 [Byte1]: 58
2775 19:22:51.785466
2776 19:22:51.785579 Set Vref, RX VrefLevel [Byte0]: 59
2777 19:22:51.788708 [Byte1]: 59
2778 19:22:51.793434
2779 19:22:51.793570 Set Vref, RX VrefLevel [Byte0]: 60
2780 19:22:51.796892 [Byte1]: 60
2781 19:22:51.801431
2782 19:22:51.801558 Set Vref, RX VrefLevel [Byte0]: 61
2783 19:22:51.804905 [Byte1]: 61
2784 19:22:51.809527
2785 19:22:51.809612 Set Vref, RX VrefLevel [Byte0]: 62
2786 19:22:51.812923 [Byte1]: 62
2787 19:22:51.817715
2788 19:22:51.817786 Set Vref, RX VrefLevel [Byte0]: 63
2789 19:22:51.820759 [Byte1]: 63
2790 19:22:51.825448
2791 19:22:51.825527 Set Vref, RX VrefLevel [Byte0]: 64
2792 19:22:51.828891 [Byte1]: 64
2793 19:22:51.833667
2794 19:22:51.833735 Set Vref, RX VrefLevel [Byte0]: 65
2795 19:22:51.836606 [Byte1]: 65
2796 19:22:51.841284
2797 19:22:51.841356 Set Vref, RX VrefLevel [Byte0]: 66
2798 19:22:51.844855 [Byte1]: 66
2799 19:22:51.849758
2800 19:22:51.849837 Set Vref, RX VrefLevel [Byte0]: 67
2801 19:22:51.853070 [Byte1]: 67
2802 19:22:51.857670
2803 19:22:51.857742 Set Vref, RX VrefLevel [Byte0]: 68
2804 19:22:51.860598 [Byte1]: 68
2805 19:22:51.865294
2806 19:22:51.865372 Set Vref, RX VrefLevel [Byte0]: 69
2807 19:22:51.868718 [Byte1]: 69
2808 19:22:51.873250
2809 19:22:51.873351 Set Vref, RX VrefLevel [Byte0]: 70
2810 19:22:51.876549 [Byte1]: 70
2811 19:22:51.881321
2812 19:22:51.881442 Set Vref, RX VrefLevel [Byte0]: 71
2813 19:22:51.884834 [Byte1]: 71
2814 19:22:51.889599
2815 19:22:51.889686 Set Vref, RX VrefLevel [Byte0]: 72
2816 19:22:51.892871 [Byte1]: 72
2817 19:22:51.897672
2818 19:22:51.897747 Set Vref, RX VrefLevel [Byte0]: 73
2819 19:22:51.900802 [Byte1]: 73
2820 19:22:51.905772
2821 19:22:51.905850 Set Vref, RX VrefLevel [Byte0]: 74
2822 19:22:51.908733 [Byte1]: 74
2823 19:22:51.913884
2824 19:22:51.913960 Final RX Vref Byte 0 = 62 to rank0
2825 19:22:51.917098 Final RX Vref Byte 1 = 52 to rank0
2826 19:22:51.920419 Final RX Vref Byte 0 = 62 to rank1
2827 19:22:51.923572 Final RX Vref Byte 1 = 52 to rank1==
2828 19:22:51.926683 Dram Type= 6, Freq= 0, CH_0, rank 0
2829 19:22:51.933250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2830 19:22:51.933364 ==
2831 19:22:51.933466 DQS Delay:
2832 19:22:51.933573 DQS0 = 0, DQS1 = 0
2833 19:22:51.936818 DQM Delay:
2834 19:22:51.936897 DQM0 = 111, DQM1 = 101
2835 19:22:51.939869 DQ Delay:
2836 19:22:51.943417 DQ0 =110, DQ1 =112, DQ2 =112, DQ3 =106
2837 19:22:51.946447 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2838 19:22:51.949976 DQ8 =92, DQ9 =84, DQ10 =104, DQ11 =94
2839 19:22:51.953276 DQ12 =106, DQ13 =106, DQ14 =114, DQ15 =110
2840 19:22:51.953354
2841 19:22:51.953454
2842 19:22:51.960020 [DQSOSCAuto] RK0, (LSB)MR18= 0xff, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
2843 19:22:51.963457 CH0 RK0: MR19=403, MR18=FF
2844 19:22:51.970295 CH0_RK0: MR19=0x403, MR18=0xFF, DQSOSC=410, MR23=63, INC=39, DEC=26
2845 19:22:51.970385
2846 19:22:51.973121 ----->DramcWriteLeveling(PI) begin...
2847 19:22:51.973221 ==
2848 19:22:51.976458 Dram Type= 6, Freq= 0, CH_0, rank 1
2849 19:22:51.979790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2850 19:22:51.979866 ==
2851 19:22:51.983181 Write leveling (Byte 0): 32 => 32
2852 19:22:51.986726 Write leveling (Byte 1): 29 => 29
2853 19:22:51.990191 DramcWriteLeveling(PI) end<-----
2854 19:22:51.990288
2855 19:22:51.990374 ==
2856 19:22:51.993222 Dram Type= 6, Freq= 0, CH_0, rank 1
2857 19:22:51.996701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2858 19:22:52.000032 ==
2859 19:22:52.000107 [Gating] SW mode calibration
2860 19:22:52.010009 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2861 19:22:52.013439 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2862 19:22:52.016710 0 15 0 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
2863 19:22:52.023132 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2864 19:22:52.026592 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2865 19:22:52.029881 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2866 19:22:52.037547 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2867 19:22:52.040021 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2868 19:22:52.043514 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
2869 19:22:52.050261 0 15 28 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
2870 19:22:52.053137 1 0 0 | B1->B0 | 2424 2323 | 1 0 | (1 0) (0 0)
2871 19:22:52.056789 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2872 19:22:52.063185 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2873 19:22:52.066359 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2874 19:22:52.070110 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2875 19:22:52.073382 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2876 19:22:52.080102 1 0 24 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
2877 19:22:52.083616 1 0 28 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
2878 19:22:52.086451 1 1 0 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
2879 19:22:52.093316 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2880 19:22:52.096327 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2881 19:22:52.099764 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2882 19:22:52.106682 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2883 19:22:52.109869 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2884 19:22:52.113216 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2885 19:22:52.120288 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2886 19:22:52.123436 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2887 19:22:52.126411 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 19:22:52.133481 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 19:22:52.136423 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 19:22:52.140020 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 19:22:52.146306 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 19:22:52.149925 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 19:22:52.153030 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 19:22:52.159640 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 19:22:52.163053 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 19:22:52.166673 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2897 19:22:52.173075 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2898 19:22:52.176316 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2899 19:22:52.179491 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2900 19:22:52.183032 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2901 19:22:52.189526 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2902 19:22:52.193464 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2903 19:22:52.196123 Total UI for P1: 0, mck2ui 16
2904 19:22:52.199534 best dqsien dly found for B0: ( 1, 3, 26)
2905 19:22:52.203085 Total UI for P1: 0, mck2ui 16
2906 19:22:52.206653 best dqsien dly found for B1: ( 1, 3, 30)
2907 19:22:52.209947 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2908 19:22:52.212879 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2909 19:22:52.212982
2910 19:22:52.216598 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2911 19:22:52.219425 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2912 19:22:52.222923 [Gating] SW calibration Done
2913 19:22:52.223000 ==
2914 19:22:52.226527 Dram Type= 6, Freq= 0, CH_0, rank 1
2915 19:22:52.233174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2916 19:22:52.233281 ==
2917 19:22:52.233379 RX Vref Scan: 0
2918 19:22:52.233475
2919 19:22:52.236081 RX Vref 0 -> 0, step: 1
2920 19:22:52.236196
2921 19:22:52.239762 RX Delay -40 -> 252, step: 8
2922 19:22:52.243371 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2923 19:22:52.246480 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
2924 19:22:52.249957 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2925 19:22:52.252987 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2926 19:22:52.259614 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
2927 19:22:52.262998 iDelay=200, Bit 5, Center 99 (32 ~ 167) 136
2928 19:22:52.266209 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2929 19:22:52.270306 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2930 19:22:52.273219 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2931 19:22:52.276171 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2932 19:22:52.282930 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2933 19:22:52.286451 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2934 19:22:52.289772 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2935 19:22:52.292853 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2936 19:22:52.296297 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2937 19:22:52.303279 iDelay=200, Bit 15, Center 107 (32 ~ 183) 152
2938 19:22:52.303376 ==
2939 19:22:52.306499 Dram Type= 6, Freq= 0, CH_0, rank 1
2940 19:22:52.309801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2941 19:22:52.309890 ==
2942 19:22:52.309974 DQS Delay:
2943 19:22:52.312680 DQS0 = 0, DQS1 = 0
2944 19:22:52.312764 DQM Delay:
2945 19:22:52.316310 DQM0 = 111, DQM1 = 101
2946 19:22:52.316394 DQ Delay:
2947 19:22:52.319655 DQ0 =111, DQ1 =107, DQ2 =111, DQ3 =107
2948 19:22:52.323198 DQ4 =111, DQ5 =99, DQ6 =119, DQ7 =123
2949 19:22:52.326673 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
2950 19:22:52.329622 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =107
2951 19:22:52.329735
2952 19:22:52.329818
2953 19:22:52.333245 ==
2954 19:22:52.333352 Dram Type= 6, Freq= 0, CH_0, rank 1
2955 19:22:52.339482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2956 19:22:52.339567 ==
2957 19:22:52.339652
2958 19:22:52.339735
2959 19:22:52.343081 TX Vref Scan disable
2960 19:22:52.343163 == TX Byte 0 ==
2961 19:22:52.346061 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2962 19:22:52.352596 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2963 19:22:52.352702 == TX Byte 1 ==
2964 19:22:52.356085 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2965 19:22:52.363163 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2966 19:22:52.363312 ==
2967 19:22:52.366500 Dram Type= 6, Freq= 0, CH_0, rank 1
2968 19:22:52.369375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2969 19:22:52.369483 ==
2970 19:22:52.381922 TX Vref=22, minBit 1, minWin=25, winSum=424
2971 19:22:52.384782 TX Vref=24, minBit 1, minWin=26, winSum=432
2972 19:22:52.388371 TX Vref=26, minBit 0, minWin=27, winSum=437
2973 19:22:52.391825 TX Vref=28, minBit 8, minWin=26, winSum=437
2974 19:22:52.394834 TX Vref=30, minBit 1, minWin=27, winSum=441
2975 19:22:52.398438 TX Vref=32, minBit 8, minWin=26, winSum=440
2976 19:22:52.404796 [TxChooseVref] Worse bit 1, Min win 27, Win sum 441, Final Vref 30
2977 19:22:52.404908
2978 19:22:52.408071 Final TX Range 1 Vref 30
2979 19:22:52.408175
2980 19:22:52.408304 ==
2981 19:22:52.411445 Dram Type= 6, Freq= 0, CH_0, rank 1
2982 19:22:52.415393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2983 19:22:52.415469 ==
2984 19:22:52.415549
2985 19:22:52.418238
2986 19:22:52.418357 TX Vref Scan disable
2987 19:22:52.421618 == TX Byte 0 ==
2988 19:22:52.424982 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2989 19:22:52.428594 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2990 19:22:52.431550 == TX Byte 1 ==
2991 19:22:52.435147 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2992 19:22:52.438562 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2993 19:22:52.438646
2994 19:22:52.441398 [DATLAT]
2995 19:22:52.441501 Freq=1200, CH0 RK1
2996 19:22:52.441591
2997 19:22:52.444774 DATLAT Default: 0xd
2998 19:22:52.444873 0, 0xFFFF, sum = 0
2999 19:22:52.448427 1, 0xFFFF, sum = 0
3000 19:22:52.448528 2, 0xFFFF, sum = 0
3001 19:22:52.451998 3, 0xFFFF, sum = 0
3002 19:22:52.452100 4, 0xFFFF, sum = 0
3003 19:22:52.455010 5, 0xFFFF, sum = 0
3004 19:22:52.455103 6, 0xFFFF, sum = 0
3005 19:22:52.458586 7, 0xFFFF, sum = 0
3006 19:22:52.458671 8, 0xFFFF, sum = 0
3007 19:22:52.461633 9, 0xFFFF, sum = 0
3008 19:22:52.465233 10, 0xFFFF, sum = 0
3009 19:22:52.465320 11, 0xFFFF, sum = 0
3010 19:22:52.468549 12, 0x0, sum = 1
3011 19:22:52.468634 13, 0x0, sum = 2
3012 19:22:52.468738 14, 0x0, sum = 3
3013 19:22:52.472013 15, 0x0, sum = 4
3014 19:22:52.472102 best_step = 13
3015 19:22:52.472186
3016 19:22:52.475081 ==
3017 19:22:52.475165 Dram Type= 6, Freq= 0, CH_0, rank 1
3018 19:22:52.481520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3019 19:22:52.481648 ==
3020 19:22:52.481740 RX Vref Scan: 0
3021 19:22:52.481823
3022 19:22:52.485055 RX Vref 0 -> 0, step: 1
3023 19:22:52.485154
3024 19:22:52.488729 RX Delay -37 -> 252, step: 4
3025 19:22:52.491595 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3026 19:22:52.498504 iDelay=195, Bit 1, Center 110 (39 ~ 182) 144
3027 19:22:52.501763 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3028 19:22:52.504802 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3029 19:22:52.508094 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3030 19:22:52.511779 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3031 19:22:52.514872 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3032 19:22:52.521504 iDelay=195, Bit 7, Center 120 (47 ~ 194) 148
3033 19:22:52.524845 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3034 19:22:52.528572 iDelay=195, Bit 9, Center 84 (15 ~ 154) 140
3035 19:22:52.531606 iDelay=195, Bit 10, Center 104 (35 ~ 174) 140
3036 19:22:52.534873 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3037 19:22:52.541784 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3038 19:22:52.544940 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3039 19:22:52.548214 iDelay=195, Bit 14, Center 114 (47 ~ 182) 136
3040 19:22:52.551643 iDelay=195, Bit 15, Center 110 (43 ~ 178) 136
3041 19:22:52.551815 ==
3042 19:22:52.555247 Dram Type= 6, Freq= 0, CH_0, rank 1
3043 19:22:52.561394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3044 19:22:52.561630 ==
3045 19:22:52.561823 DQS Delay:
3046 19:22:52.565085 DQS0 = 0, DQS1 = 0
3047 19:22:52.565313 DQM Delay:
3048 19:22:52.565591 DQM0 = 111, DQM1 = 101
3049 19:22:52.568113 DQ Delay:
3050 19:22:52.571757 DQ0 =108, DQ1 =110, DQ2 =110, DQ3 =108
3051 19:22:52.574553 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =120
3052 19:22:52.578164 DQ8 =90, DQ9 =84, DQ10 =104, DQ11 =94
3053 19:22:52.581640 DQ12 =108, DQ13 =108, DQ14 =114, DQ15 =110
3054 19:22:52.582058
3055 19:22:52.582360
3056 19:22:52.591913 [DQSOSCAuto] RK1, (LSB)MR18= 0x12fa, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 403 ps
3057 19:22:52.592321 CH0 RK1: MR19=403, MR18=12FA
3058 19:22:52.598488 CH0_RK1: MR19=0x403, MR18=0x12FA, DQSOSC=403, MR23=63, INC=40, DEC=26
3059 19:22:52.601354 [RxdqsGatingPostProcess] freq 1200
3060 19:22:52.608265 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3061 19:22:52.611482 best DQS0 dly(2T, 0.5T) = (0, 11)
3062 19:22:52.614753 best DQS1 dly(2T, 0.5T) = (0, 12)
3063 19:22:52.617892 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3064 19:22:52.621316 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3065 19:22:52.621802 best DQS0 dly(2T, 0.5T) = (0, 11)
3066 19:22:52.624869 best DQS1 dly(2T, 0.5T) = (0, 11)
3067 19:22:52.628041 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3068 19:22:52.631277 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3069 19:22:52.634907 Pre-setting of DQS Precalculation
3070 19:22:52.641218 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3071 19:22:52.641639 ==
3072 19:22:52.645097 Dram Type= 6, Freq= 0, CH_1, rank 0
3073 19:22:52.647915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3074 19:22:52.648298 ==
3075 19:22:52.655028 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3076 19:22:52.660906 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3077 19:22:52.668098 [CA 0] Center 37 (7~67) winsize 61
3078 19:22:52.671654 [CA 1] Center 37 (7~68) winsize 62
3079 19:22:52.674627 [CA 2] Center 34 (4~64) winsize 61
3080 19:22:52.678307 [CA 3] Center 34 (4~64) winsize 61
3081 19:22:52.681607 [CA 4] Center 34 (4~64) winsize 61
3082 19:22:52.685079 [CA 5] Center 33 (3~63) winsize 61
3083 19:22:52.685452
3084 19:22:52.688044 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3085 19:22:52.688419
3086 19:22:52.691107 [CATrainingPosCal] consider 1 rank data
3087 19:22:52.694740 u2DelayCellTimex100 = 270/100 ps
3088 19:22:52.697924 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3089 19:22:52.701458 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3090 19:22:52.708066 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3091 19:22:52.711671 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3092 19:22:52.714762 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3093 19:22:52.718120 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3094 19:22:52.718501
3095 19:22:52.721289 CA PerBit enable=1, Macro0, CA PI delay=33
3096 19:22:52.721710
3097 19:22:52.724728 [CBTSetCACLKResult] CA Dly = 33
3098 19:22:52.724808 CS Dly: 6 (0~37)
3099 19:22:52.724872 ==
3100 19:22:52.727754 Dram Type= 6, Freq= 0, CH_1, rank 1
3101 19:22:52.734557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3102 19:22:52.734638 ==
3103 19:22:52.737751 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3104 19:22:52.744073 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3105 19:22:52.753293 [CA 0] Center 37 (7~67) winsize 61
3106 19:22:52.756557 [CA 1] Center 37 (7~68) winsize 62
3107 19:22:52.759803 [CA 2] Center 34 (4~65) winsize 62
3108 19:22:52.763438 [CA 3] Center 33 (3~64) winsize 62
3109 19:22:52.766693 [CA 4] Center 34 (4~65) winsize 62
3110 19:22:52.770006 [CA 5] Center 33 (3~63) winsize 61
3111 19:22:52.770169
3112 19:22:52.773525 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3113 19:22:52.773645
3114 19:22:52.777021 [CATrainingPosCal] consider 2 rank data
3115 19:22:52.779906 u2DelayCellTimex100 = 270/100 ps
3116 19:22:52.783535 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3117 19:22:52.787147 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3118 19:22:52.793537 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3119 19:22:52.796631 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3120 19:22:52.800343 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3121 19:22:52.803873 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3122 19:22:52.804164
3123 19:22:52.807107 CA PerBit enable=1, Macro0, CA PI delay=33
3124 19:22:52.807484
3125 19:22:52.810688 [CBTSetCACLKResult] CA Dly = 33
3126 19:22:52.811063 CS Dly: 7 (0~40)
3127 19:22:52.811363
3128 19:22:52.813579 ----->DramcWriteLeveling(PI) begin...
3129 19:22:52.816750 ==
3130 19:22:52.817125 Dram Type= 6, Freq= 0, CH_1, rank 0
3131 19:22:52.823614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3132 19:22:52.824042 ==
3133 19:22:52.826755 Write leveling (Byte 0): 26 => 26
3134 19:22:52.830488 Write leveling (Byte 1): 29 => 29
3135 19:22:52.833775 DramcWriteLeveling(PI) end<-----
3136 19:22:52.834165
3137 19:22:52.834542 ==
3138 19:22:52.837324 Dram Type= 6, Freq= 0, CH_1, rank 0
3139 19:22:52.840268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3140 19:22:52.840661 ==
3141 19:22:52.843968 [Gating] SW mode calibration
3142 19:22:52.850375 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3143 19:22:52.853554 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3144 19:22:52.860599 0 15 0 | B1->B0 | 3131 2f2e | 1 1 | (1 1) (1 1)
3145 19:22:52.863565 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3146 19:22:52.867010 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3147 19:22:52.873472 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3148 19:22:52.876789 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3149 19:22:52.880533 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3150 19:22:52.886778 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3151 19:22:52.890290 0 15 28 | B1->B0 | 2b2b 2f2f | 0 0 | (0 0) (0 0)
3152 19:22:52.893416 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3153 19:22:52.900233 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3154 19:22:52.903909 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3155 19:22:52.906920 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3156 19:22:52.913634 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3157 19:22:52.917014 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3158 19:22:52.920051 1 0 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3159 19:22:52.926824 1 0 28 | B1->B0 | 4040 3b3b | 0 1 | (0 0) (0 0)
3160 19:22:52.930494 1 1 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3161 19:22:52.933480 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3162 19:22:52.936996 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3163 19:22:52.943427 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3164 19:22:52.946978 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3165 19:22:52.950185 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3166 19:22:52.957285 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3167 19:22:52.960049 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3168 19:22:52.963520 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3169 19:22:52.970670 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 19:22:52.973693 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 19:22:52.977179 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 19:22:52.983443 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 19:22:52.986412 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 19:22:52.989717 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 19:22:52.996768 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 19:22:53.000064 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 19:22:53.003105 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 19:22:53.009927 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3179 19:22:53.013540 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3180 19:22:53.016448 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3181 19:22:53.023081 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3182 19:22:53.026621 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3183 19:22:53.030217 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3184 19:22:53.033687 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3185 19:22:53.036673 Total UI for P1: 0, mck2ui 16
3186 19:22:53.039861 best dqsien dly found for B0: ( 1, 3, 28)
3187 19:22:53.043346 Total UI for P1: 0, mck2ui 16
3188 19:22:53.046403 best dqsien dly found for B1: ( 1, 3, 28)
3189 19:22:53.050066 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3190 19:22:53.056249 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3191 19:22:53.056329
3192 19:22:53.059783 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3193 19:22:53.063161 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3194 19:22:53.066734 [Gating] SW calibration Done
3195 19:22:53.066815 ==
3196 19:22:53.069704 Dram Type= 6, Freq= 0, CH_1, rank 0
3197 19:22:53.073095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3198 19:22:53.073184 ==
3199 19:22:53.073249 RX Vref Scan: 0
3200 19:22:53.073308
3201 19:22:53.076619 RX Vref 0 -> 0, step: 1
3202 19:22:53.076699
3203 19:22:53.079627 RX Delay -40 -> 252, step: 8
3204 19:22:53.083224 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3205 19:22:53.086617 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3206 19:22:53.093142 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3207 19:22:53.096558 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3208 19:22:53.099660 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3209 19:22:53.103077 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3210 19:22:53.106423 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3211 19:22:53.112896 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3212 19:22:53.116857 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3213 19:22:53.119712 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3214 19:22:53.123382 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3215 19:22:53.126658 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3216 19:22:53.133153 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3217 19:22:53.136575 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3218 19:22:53.140153 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3219 19:22:53.143069 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3220 19:22:53.143153 ==
3221 19:22:53.146549 Dram Type= 6, Freq= 0, CH_1, rank 0
3222 19:22:53.150106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3223 19:22:53.153123 ==
3224 19:22:53.153228 DQS Delay:
3225 19:22:53.153322 DQS0 = 0, DQS1 = 0
3226 19:22:53.156828 DQM Delay:
3227 19:22:53.156908 DQM0 = 113, DQM1 = 105
3228 19:22:53.159827 DQ Delay:
3229 19:22:53.163236 DQ0 =119, DQ1 =107, DQ2 =99, DQ3 =115
3230 19:22:53.166765 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3231 19:22:53.170137 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =103
3232 19:22:53.173211 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =111
3233 19:22:53.173311
3234 19:22:53.173402
3235 19:22:53.173461 ==
3236 19:22:53.176795 Dram Type= 6, Freq= 0, CH_1, rank 0
3237 19:22:53.179851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3238 19:22:53.179966 ==
3239 19:22:53.180038
3240 19:22:53.180098
3241 19:22:53.183481 TX Vref Scan disable
3242 19:22:53.186327 == TX Byte 0 ==
3243 19:22:53.189951 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3244 19:22:53.193490 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3245 19:22:53.196441 == TX Byte 1 ==
3246 19:22:53.199879 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3247 19:22:53.203633 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3248 19:22:53.203714 ==
3249 19:22:53.206573 Dram Type= 6, Freq= 0, CH_1, rank 0
3250 19:22:53.209831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3251 19:22:53.213226 ==
3252 19:22:53.223384 TX Vref=22, minBit 11, minWin=24, winSum=409
3253 19:22:53.226763 TX Vref=24, minBit 11, minWin=24, winSum=414
3254 19:22:53.230194 TX Vref=26, minBit 8, minWin=25, winSum=422
3255 19:22:53.233382 TX Vref=28, minBit 9, minWin=25, winSum=425
3256 19:22:53.236679 TX Vref=30, minBit 9, minWin=25, winSum=428
3257 19:22:53.243363 TX Vref=32, minBit 9, minWin=25, winSum=424
3258 19:22:53.246389 [TxChooseVref] Worse bit 9, Min win 25, Win sum 428, Final Vref 30
3259 19:22:53.246475
3260 19:22:53.249845 Final TX Range 1 Vref 30
3261 19:22:53.249950
3262 19:22:53.250049 ==
3263 19:22:53.253280 Dram Type= 6, Freq= 0, CH_1, rank 0
3264 19:22:53.256931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3265 19:22:53.257009 ==
3266 19:22:53.259809
3267 19:22:53.259878
3268 19:22:53.259945 TX Vref Scan disable
3269 19:22:53.263452 == TX Byte 0 ==
3270 19:22:53.266405 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3271 19:22:53.269798 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3272 19:22:53.273222 == TX Byte 1 ==
3273 19:22:53.276795 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3274 19:22:53.279787 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3275 19:22:53.283153
3276 19:22:53.283233 [DATLAT]
3277 19:22:53.283297 Freq=1200, CH1 RK0
3278 19:22:53.283357
3279 19:22:53.286687 DATLAT Default: 0xd
3280 19:22:53.286767 0, 0xFFFF, sum = 0
3281 19:22:53.289758 1, 0xFFFF, sum = 0
3282 19:22:53.289839 2, 0xFFFF, sum = 0
3283 19:22:53.292815 3, 0xFFFF, sum = 0
3284 19:22:53.296426 4, 0xFFFF, sum = 0
3285 19:22:53.296509 5, 0xFFFF, sum = 0
3286 19:22:53.299945 6, 0xFFFF, sum = 0
3287 19:22:53.300027 7, 0xFFFF, sum = 0
3288 19:22:53.302868 8, 0xFFFF, sum = 0
3289 19:22:53.302949 9, 0xFFFF, sum = 0
3290 19:22:53.306571 10, 0xFFFF, sum = 0
3291 19:22:53.306652 11, 0xFFFF, sum = 0
3292 19:22:53.309484 12, 0x0, sum = 1
3293 19:22:53.309591 13, 0x0, sum = 2
3294 19:22:53.313006 14, 0x0, sum = 3
3295 19:22:53.313092 15, 0x0, sum = 4
3296 19:22:53.313161 best_step = 13
3297 19:22:53.316692
3298 19:22:53.316783 ==
3299 19:22:53.319954 Dram Type= 6, Freq= 0, CH_1, rank 0
3300 19:22:53.323249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3301 19:22:53.323348 ==
3302 19:22:53.323425 RX Vref Scan: 1
3303 19:22:53.323497
3304 19:22:53.326224 Set Vref Range= 32 -> 127
3305 19:22:53.326332
3306 19:22:53.329413 RX Vref 32 -> 127, step: 1
3307 19:22:53.329555
3308 19:22:53.333079 RX Delay -21 -> 252, step: 4
3309 19:22:53.333159
3310 19:22:53.336443 Set Vref, RX VrefLevel [Byte0]: 32
3311 19:22:53.339668 [Byte1]: 32
3312 19:22:53.339749
3313 19:22:53.343150 Set Vref, RX VrefLevel [Byte0]: 33
3314 19:22:53.346557 [Byte1]: 33
3315 19:22:53.349764
3316 19:22:53.349855 Set Vref, RX VrefLevel [Byte0]: 34
3317 19:22:53.353034 [Byte1]: 34
3318 19:22:53.357633
3319 19:22:53.357732 Set Vref, RX VrefLevel [Byte0]: 35
3320 19:22:53.360861 [Byte1]: 35
3321 19:22:53.365534
3322 19:22:53.365653 Set Vref, RX VrefLevel [Byte0]: 36
3323 19:22:53.369235 [Byte1]: 36
3324 19:22:53.373416
3325 19:22:53.373543 Set Vref, RX VrefLevel [Byte0]: 37
3326 19:22:53.377007 [Byte1]: 37
3327 19:22:53.381190
3328 19:22:53.381261 Set Vref, RX VrefLevel [Byte0]: 38
3329 19:22:53.384750 [Byte1]: 38
3330 19:22:53.389258
3331 19:22:53.389336 Set Vref, RX VrefLevel [Byte0]: 39
3332 19:22:53.392761 [Byte1]: 39
3333 19:22:53.397024
3334 19:22:53.397110 Set Vref, RX VrefLevel [Byte0]: 40
3335 19:22:53.400678 [Byte1]: 40
3336 19:22:53.405001
3337 19:22:53.405080 Set Vref, RX VrefLevel [Byte0]: 41
3338 19:22:53.408468 [Byte1]: 41
3339 19:22:53.413289
3340 19:22:53.413369 Set Vref, RX VrefLevel [Byte0]: 42
3341 19:22:53.416143 [Byte1]: 42
3342 19:22:53.421016
3343 19:22:53.421094 Set Vref, RX VrefLevel [Byte0]: 43
3344 19:22:53.424085 [Byte1]: 43
3345 19:22:53.428693
3346 19:22:53.428765 Set Vref, RX VrefLevel [Byte0]: 44
3347 19:22:53.432282 [Byte1]: 44
3348 19:22:53.436664
3349 19:22:53.436733 Set Vref, RX VrefLevel [Byte0]: 45
3350 19:22:53.440015 [Byte1]: 45
3351 19:22:53.444470
3352 19:22:53.444548 Set Vref, RX VrefLevel [Byte0]: 46
3353 19:22:53.447903 [Byte1]: 46
3354 19:22:53.452741
3355 19:22:53.452810 Set Vref, RX VrefLevel [Byte0]: 47
3356 19:22:53.456132 [Byte1]: 47
3357 19:22:53.460408
3358 19:22:53.460476 Set Vref, RX VrefLevel [Byte0]: 48
3359 19:22:53.463596 [Byte1]: 48
3360 19:22:53.468200
3361 19:22:53.468279 Set Vref, RX VrefLevel [Byte0]: 49
3362 19:22:53.471726 [Byte1]: 49
3363 19:22:53.476117
3364 19:22:53.476190 Set Vref, RX VrefLevel [Byte0]: 50
3365 19:22:53.479657 [Byte1]: 50
3366 19:22:53.484028
3367 19:22:53.484101 Set Vref, RX VrefLevel [Byte0]: 51
3368 19:22:53.487530 [Byte1]: 51
3369 19:22:53.492153
3370 19:22:53.492224 Set Vref, RX VrefLevel [Byte0]: 52
3371 19:22:53.495680 [Byte1]: 52
3372 19:22:53.500411
3373 19:22:53.500485 Set Vref, RX VrefLevel [Byte0]: 53
3374 19:22:53.503452 [Byte1]: 53
3375 19:22:53.508088
3376 19:22:53.508163 Set Vref, RX VrefLevel [Byte0]: 54
3377 19:22:53.511072 [Byte1]: 54
3378 19:22:53.515834
3379 19:22:53.515906 Set Vref, RX VrefLevel [Byte0]: 55
3380 19:22:53.519371 [Byte1]: 55
3381 19:22:53.524157
3382 19:22:53.524235 Set Vref, RX VrefLevel [Byte0]: 56
3383 19:22:53.527065 [Byte1]: 56
3384 19:22:53.531727
3385 19:22:53.531802 Set Vref, RX VrefLevel [Byte0]: 57
3386 19:22:53.535368 [Byte1]: 57
3387 19:22:53.539551
3388 19:22:53.539634 Set Vref, RX VrefLevel [Byte0]: 58
3389 19:22:53.543184 [Byte1]: 58
3390 19:22:53.547316
3391 19:22:53.547389 Set Vref, RX VrefLevel [Byte0]: 59
3392 19:22:53.550977 [Byte1]: 59
3393 19:22:53.555701
3394 19:22:53.555772 Set Vref, RX VrefLevel [Byte0]: 60
3395 19:22:53.558617 [Byte1]: 60
3396 19:22:53.563328
3397 19:22:53.563410 Set Vref, RX VrefLevel [Byte0]: 61
3398 19:22:53.566689 [Byte1]: 61
3399 19:22:53.571440
3400 19:22:53.571521 Set Vref, RX VrefLevel [Byte0]: 62
3401 19:22:53.574496 [Byte1]: 62
3402 19:22:53.579242
3403 19:22:53.579322 Set Vref, RX VrefLevel [Byte0]: 63
3404 19:22:53.582687 [Byte1]: 63
3405 19:22:53.587222
3406 19:22:53.587302 Set Vref, RX VrefLevel [Byte0]: 64
3407 19:22:53.591080 [Byte1]: 64
3408 19:22:53.595230
3409 19:22:53.595310 Set Vref, RX VrefLevel [Byte0]: 65
3410 19:22:53.598356 [Byte1]: 65
3411 19:22:53.603148
3412 19:22:53.603228 Final RX Vref Byte 0 = 59 to rank0
3413 19:22:53.606522 Final RX Vref Byte 1 = 47 to rank0
3414 19:22:53.609733 Final RX Vref Byte 0 = 59 to rank1
3415 19:22:53.612875 Final RX Vref Byte 1 = 47 to rank1==
3416 19:22:53.616011 Dram Type= 6, Freq= 0, CH_1, rank 0
3417 19:22:53.623191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3418 19:22:53.623286 ==
3419 19:22:53.623352 DQS Delay:
3420 19:22:53.623411 DQS0 = 0, DQS1 = 0
3421 19:22:53.626071 DQM Delay:
3422 19:22:53.626151 DQM0 = 115, DQM1 = 104
3423 19:22:53.629745 DQ Delay:
3424 19:22:53.633156 DQ0 =118, DQ1 =110, DQ2 =108, DQ3 =112
3425 19:22:53.636019 DQ4 =112, DQ5 =124, DQ6 =124, DQ7 =112
3426 19:22:53.639704 DQ8 =92, DQ9 =96, DQ10 =104, DQ11 =98
3427 19:22:53.642674 DQ12 =114, DQ13 =110, DQ14 =114, DQ15 =110
3428 19:22:53.642755
3429 19:22:53.642818
3430 19:22:53.652896 [DQSOSCAuto] RK0, (LSB)MR18= 0xf3fa, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 415 ps
3431 19:22:53.652977 CH1 RK0: MR19=303, MR18=F3FA
3432 19:22:53.659533 CH1_RK0: MR19=0x303, MR18=0xF3FA, DQSOSC=412, MR23=63, INC=38, DEC=25
3433 19:22:53.659614
3434 19:22:53.663064 ----->DramcWriteLeveling(PI) begin...
3435 19:22:53.663146 ==
3436 19:22:53.666025 Dram Type= 6, Freq= 0, CH_1, rank 1
3437 19:22:53.672536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3438 19:22:53.672618 ==
3439 19:22:53.676034 Write leveling (Byte 0): 24 => 24
3440 19:22:53.676114 Write leveling (Byte 1): 28 => 28
3441 19:22:53.679589 DramcWriteLeveling(PI) end<-----
3442 19:22:53.679669
3443 19:22:53.679732 ==
3444 19:22:53.682506 Dram Type= 6, Freq= 0, CH_1, rank 1
3445 19:22:53.689348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3446 19:22:53.689454 ==
3447 19:22:53.692832 [Gating] SW mode calibration
3448 19:22:53.699448 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3449 19:22:53.702320 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3450 19:22:53.709503 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3451 19:22:53.712275 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3452 19:22:53.715921 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3453 19:22:53.722529 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3454 19:22:53.725557 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3455 19:22:53.729382 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3456 19:22:53.735621 0 15 24 | B1->B0 | 3333 2525 | 1 0 | (1 0) (0 0)
3457 19:22:53.739013 0 15 28 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
3458 19:22:53.742562 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3459 19:22:53.745483 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3460 19:22:53.752292 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3461 19:22:53.755821 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3462 19:22:53.758872 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3463 19:22:53.765567 1 0 20 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
3464 19:22:53.768957 1 0 24 | B1->B0 | 2b2a 4444 | 1 0 | (1 1) (0 0)
3465 19:22:53.771941 1 0 28 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
3466 19:22:53.779036 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3467 19:22:53.781991 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3468 19:22:53.785568 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3469 19:22:53.792464 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3470 19:22:53.795860 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3471 19:22:53.798755 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3472 19:22:53.805185 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3473 19:22:53.808694 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3474 19:22:53.812179 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 19:22:53.818965 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 19:22:53.821933 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 19:22:53.825556 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 19:22:53.831804 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 19:22:53.834988 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 19:22:53.838518 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 19:22:53.844974 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 19:22:53.848310 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 19:22:53.851959 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 19:22:53.858585 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 19:22:53.861501 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 19:22:53.865243 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 19:22:53.871704 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3488 19:22:53.874703 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3489 19:22:53.878450 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3490 19:22:53.881381 Total UI for P1: 0, mck2ui 16
3491 19:22:53.884895 best dqsien dly found for B0: ( 1, 3, 22)
3492 19:22:53.888372 Total UI for P1: 0, mck2ui 16
3493 19:22:53.891502 best dqsien dly found for B1: ( 1, 3, 26)
3494 19:22:53.894932 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3495 19:22:53.898363 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3496 19:22:53.898453
3497 19:22:53.904766 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3498 19:22:53.908367 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3499 19:22:53.908448 [Gating] SW calibration Done
3500 19:22:53.911214 ==
3501 19:22:53.914683 Dram Type= 6, Freq= 0, CH_1, rank 1
3502 19:22:53.918308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3503 19:22:53.918389 ==
3504 19:22:53.918452 RX Vref Scan: 0
3505 19:22:53.918512
3506 19:22:53.921220 RX Vref 0 -> 0, step: 1
3507 19:22:53.921300
3508 19:22:53.924319 RX Delay -40 -> 252, step: 8
3509 19:22:53.927994 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3510 19:22:53.931330 iDelay=200, Bit 1, Center 103 (32 ~ 175) 144
3511 19:22:53.934417 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3512 19:22:53.940899 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3513 19:22:53.944313 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3514 19:22:53.947702 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3515 19:22:53.951302 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3516 19:22:53.954516 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3517 19:22:53.960798 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3518 19:22:53.964355 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3519 19:22:53.967483 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3520 19:22:53.970743 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
3521 19:22:53.974025 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3522 19:22:53.980907 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3523 19:22:53.984024 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3524 19:22:53.987403 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3525 19:22:53.987478 ==
3526 19:22:53.990783 Dram Type= 6, Freq= 0, CH_1, rank 1
3527 19:22:53.993763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3528 19:22:53.997301 ==
3529 19:22:53.997377 DQS Delay:
3530 19:22:53.997442 DQS0 = 0, DQS1 = 0
3531 19:22:54.000856 DQM Delay:
3532 19:22:54.000927 DQM0 = 110, DQM1 = 106
3533 19:22:54.003800 DQ Delay:
3534 19:22:54.007176 DQ0 =115, DQ1 =103, DQ2 =99, DQ3 =107
3535 19:22:54.010871 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =111
3536 19:22:54.013879 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =95
3537 19:22:54.017285 DQ12 =111, DQ13 =111, DQ14 =115, DQ15 =115
3538 19:22:54.017365
3539 19:22:54.017429
3540 19:22:54.017487 ==
3541 19:22:54.020683 Dram Type= 6, Freq= 0, CH_1, rank 1
3542 19:22:54.024113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3543 19:22:54.024194 ==
3544 19:22:54.024258
3545 19:22:54.024317
3546 19:22:54.027258 TX Vref Scan disable
3547 19:22:54.030648 == TX Byte 0 ==
3548 19:22:54.033732 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3549 19:22:54.037182 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3550 19:22:54.040752 == TX Byte 1 ==
3551 19:22:54.043750 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3552 19:22:54.047269 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3553 19:22:54.047349 ==
3554 19:22:54.050308 Dram Type= 6, Freq= 0, CH_1, rank 1
3555 19:22:54.053782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3556 19:22:54.056784 ==
3557 19:22:54.067573 TX Vref=22, minBit 9, minWin=25, winSum=423
3558 19:22:54.070959 TX Vref=24, minBit 9, minWin=25, winSum=424
3559 19:22:54.074170 TX Vref=26, minBit 0, minWin=26, winSum=429
3560 19:22:54.077073 TX Vref=28, minBit 0, minWin=26, winSum=430
3561 19:22:54.080556 TX Vref=30, minBit 8, minWin=26, winSum=436
3562 19:22:54.087580 TX Vref=32, minBit 8, minWin=25, winSum=430
3563 19:22:54.090577 [TxChooseVref] Worse bit 8, Min win 26, Win sum 436, Final Vref 30
3564 19:22:54.090689
3565 19:22:54.093769 Final TX Range 1 Vref 30
3566 19:22:54.093849
3567 19:22:54.093913 ==
3568 19:22:54.097522 Dram Type= 6, Freq= 0, CH_1, rank 1
3569 19:22:54.100439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3570 19:22:54.100521 ==
3571 19:22:54.103923
3572 19:22:54.104005
3573 19:22:54.104070 TX Vref Scan disable
3574 19:22:54.106962 == TX Byte 0 ==
3575 19:22:54.110301 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3576 19:22:54.117320 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3577 19:22:54.117396 == TX Byte 1 ==
3578 19:22:54.120333 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3579 19:22:54.127056 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3580 19:22:54.127139
3581 19:22:54.127204 [DATLAT]
3582 19:22:54.127265 Freq=1200, CH1 RK1
3583 19:22:54.127320
3584 19:22:54.130510 DATLAT Default: 0xd
3585 19:22:54.130580 0, 0xFFFF, sum = 0
3586 19:22:54.133634 1, 0xFFFF, sum = 0
3587 19:22:54.137113 2, 0xFFFF, sum = 0
3588 19:22:54.137197 3, 0xFFFF, sum = 0
3589 19:22:54.140000 4, 0xFFFF, sum = 0
3590 19:22:54.140067 5, 0xFFFF, sum = 0
3591 19:22:54.143623 6, 0xFFFF, sum = 0
3592 19:22:54.143701 7, 0xFFFF, sum = 0
3593 19:22:54.146640 8, 0xFFFF, sum = 0
3594 19:22:54.146715 9, 0xFFFF, sum = 0
3595 19:22:54.150206 10, 0xFFFF, sum = 0
3596 19:22:54.150275 11, 0xFFFF, sum = 0
3597 19:22:54.153692 12, 0x0, sum = 1
3598 19:22:54.153763 13, 0x0, sum = 2
3599 19:22:54.156952 14, 0x0, sum = 3
3600 19:22:54.157035 15, 0x0, sum = 4
3601 19:22:54.160153 best_step = 13
3602 19:22:54.160224
3603 19:22:54.160291 ==
3604 19:22:54.163241 Dram Type= 6, Freq= 0, CH_1, rank 1
3605 19:22:54.166761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3606 19:22:54.166836 ==
3607 19:22:54.166902 RX Vref Scan: 0
3608 19:22:54.169740
3609 19:22:54.169811 RX Vref 0 -> 0, step: 1
3610 19:22:54.169872
3611 19:22:54.173173 RX Delay -21 -> 252, step: 4
3612 19:22:54.179927 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3613 19:22:54.183408 iDelay=195, Bit 1, Center 108 (43 ~ 174) 132
3614 19:22:54.186578 iDelay=195, Bit 2, Center 104 (35 ~ 174) 140
3615 19:22:54.189679 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3616 19:22:54.193251 iDelay=195, Bit 4, Center 106 (35 ~ 178) 144
3617 19:22:54.199657 iDelay=195, Bit 5, Center 120 (47 ~ 194) 148
3618 19:22:54.202968 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3619 19:22:54.206873 iDelay=195, Bit 7, Center 108 (39 ~ 178) 140
3620 19:22:54.210145 iDelay=195, Bit 8, Center 94 (31 ~ 158) 128
3621 19:22:54.212950 iDelay=195, Bit 9, Center 102 (35 ~ 170) 136
3622 19:22:54.216295 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3623 19:22:54.223258 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3624 19:22:54.226197 iDelay=195, Bit 12, Center 116 (51 ~ 182) 132
3625 19:22:54.229654 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3626 19:22:54.233019 iDelay=195, Bit 14, Center 114 (51 ~ 178) 128
3627 19:22:54.239621 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3628 19:22:54.239721 ==
3629 19:22:54.243035 Dram Type= 6, Freq= 0, CH_1, rank 1
3630 19:22:54.246064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3631 19:22:54.246140 ==
3632 19:22:54.246202 DQS Delay:
3633 19:22:54.249724 DQS0 = 0, DQS1 = 0
3634 19:22:54.249795 DQM Delay:
3635 19:22:54.252653 DQM0 = 111, DQM1 = 108
3636 19:22:54.252724 DQ Delay:
3637 19:22:54.256223 DQ0 =114, DQ1 =108, DQ2 =104, DQ3 =108
3638 19:22:54.259329 DQ4 =106, DQ5 =120, DQ6 =122, DQ7 =108
3639 19:22:54.262842 DQ8 =94, DQ9 =102, DQ10 =110, DQ11 =100
3640 19:22:54.266369 DQ12 =116, DQ13 =116, DQ14 =114, DQ15 =116
3641 19:22:54.266436
3642 19:22:54.266497
3643 19:22:54.275936 [DQSOSCAuto] RK1, (LSB)MR18= 0xf909, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 412 ps
3644 19:22:54.279501 CH1 RK1: MR19=304, MR18=F909
3645 19:22:54.285921 CH1_RK1: MR19=0x304, MR18=0xF909, DQSOSC=406, MR23=63, INC=39, DEC=26
3646 19:22:54.285997 [RxdqsGatingPostProcess] freq 1200
3647 19:22:54.292877 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3648 19:22:54.295688 best DQS0 dly(2T, 0.5T) = (0, 11)
3649 19:22:54.299037 best DQS1 dly(2T, 0.5T) = (0, 11)
3650 19:22:54.302298 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3651 19:22:54.305863 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3652 19:22:54.309080 best DQS0 dly(2T, 0.5T) = (0, 11)
3653 19:22:54.312591 best DQS1 dly(2T, 0.5T) = (0, 11)
3654 19:22:54.315586 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3655 19:22:54.318937 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3656 19:22:54.322224 Pre-setting of DQS Precalculation
3657 19:22:54.325423 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3658 19:22:54.332321 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3659 19:22:54.342402 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3660 19:22:54.342480
3661 19:22:54.342552
3662 19:22:54.345495 [Calibration Summary] 2400 Mbps
3663 19:22:54.345604 CH 0, Rank 0
3664 19:22:54.348944 SW Impedance : PASS
3665 19:22:54.349047 DUTY Scan : NO K
3666 19:22:54.351929 ZQ Calibration : PASS
3667 19:22:54.355673 Jitter Meter : NO K
3668 19:22:54.355745 CBT Training : PASS
3669 19:22:54.359088 Write leveling : PASS
3670 19:22:54.359156 RX DQS gating : PASS
3671 19:22:54.362045 RX DQ/DQS(RDDQC) : PASS
3672 19:22:54.365368 TX DQ/DQS : PASS
3673 19:22:54.365435 RX DATLAT : PASS
3674 19:22:54.369039 RX DQ/DQS(Engine): PASS
3675 19:22:54.371973 TX OE : NO K
3676 19:22:54.372048 All Pass.
3677 19:22:54.372124
3678 19:22:54.372182 CH 0, Rank 1
3679 19:22:54.375506 SW Impedance : PASS
3680 19:22:54.378575 DUTY Scan : NO K
3681 19:22:54.378659 ZQ Calibration : PASS
3682 19:22:54.382268 Jitter Meter : NO K
3683 19:22:54.385370 CBT Training : PASS
3684 19:22:54.385436 Write leveling : PASS
3685 19:22:54.389089 RX DQS gating : PASS
3686 19:22:54.392024 RX DQ/DQS(RDDQC) : PASS
3687 19:22:54.392094 TX DQ/DQS : PASS
3688 19:22:54.395057 RX DATLAT : PASS
3689 19:22:54.398543 RX DQ/DQS(Engine): PASS
3690 19:22:54.398611 TX OE : NO K
3691 19:22:54.398687 All Pass.
3692 19:22:54.402057
3693 19:22:54.402124 CH 1, Rank 0
3694 19:22:54.405130 SW Impedance : PASS
3695 19:22:54.405210 DUTY Scan : NO K
3696 19:22:54.408711 ZQ Calibration : PASS
3697 19:22:54.411736 Jitter Meter : NO K
3698 19:22:54.411803 CBT Training : PASS
3699 19:22:54.415007 Write leveling : PASS
3700 19:22:54.415077 RX DQS gating : PASS
3701 19:22:54.418701 RX DQ/DQS(RDDQC) : PASS
3702 19:22:54.421975 TX DQ/DQS : PASS
3703 19:22:54.422041 RX DATLAT : PASS
3704 19:22:54.425337 RX DQ/DQS(Engine): PASS
3705 19:22:54.428396 TX OE : NO K
3706 19:22:54.428466 All Pass.
3707 19:22:54.428534
3708 19:22:54.428592 CH 1, Rank 1
3709 19:22:54.432009 SW Impedance : PASS
3710 19:22:54.435261 DUTY Scan : NO K
3711 19:22:54.435332 ZQ Calibration : PASS
3712 19:22:54.438747 Jitter Meter : NO K
3713 19:22:54.441769 CBT Training : PASS
3714 19:22:54.441847 Write leveling : PASS
3715 19:22:54.444971 RX DQS gating : PASS
3716 19:22:54.448427 RX DQ/DQS(RDDQC) : PASS
3717 19:22:54.448497 TX DQ/DQS : PASS
3718 19:22:54.451613 RX DATLAT : PASS
3719 19:22:54.455376 RX DQ/DQS(Engine): PASS
3720 19:22:54.455452 TX OE : NO K
3721 19:22:54.455515 All Pass.
3722 19:22:54.458307
3723 19:22:54.458377 DramC Write-DBI off
3724 19:22:54.462042 PER_BANK_REFRESH: Hybrid Mode
3725 19:22:54.462120 TX_TRACKING: ON
3726 19:22:54.471727 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3727 19:22:54.474670 [FAST_K] Save calibration result to emmc
3728 19:22:54.478294 dramc_set_vcore_voltage set vcore to 650000
3729 19:22:54.481870 Read voltage for 600, 5
3730 19:22:54.481946 Vio18 = 0
3731 19:22:54.484762 Vcore = 650000
3732 19:22:54.484842 Vdram = 0
3733 19:22:54.484907 Vddq = 0
3734 19:22:54.484973 Vmddr = 0
3735 19:22:54.491747 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3736 19:22:54.497824 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3737 19:22:54.497911 MEM_TYPE=3, freq_sel=19
3738 19:22:54.501348 sv_algorithm_assistance_LP4_1600
3739 19:22:54.504913 ============ PULL DRAM RESETB DOWN ============
3740 19:22:54.511465 ========== PULL DRAM RESETB DOWN end =========
3741 19:22:54.514949 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3742 19:22:54.517866 ===================================
3743 19:22:54.521154 LPDDR4 DRAM CONFIGURATION
3744 19:22:54.524533 ===================================
3745 19:22:54.524606 EX_ROW_EN[0] = 0x0
3746 19:22:54.527840 EX_ROW_EN[1] = 0x0
3747 19:22:54.527919 LP4Y_EN = 0x0
3748 19:22:54.531430 WORK_FSP = 0x0
3749 19:22:54.534939 WL = 0x2
3750 19:22:54.535014 RL = 0x2
3751 19:22:54.537814 BL = 0x2
3752 19:22:54.537911 RPST = 0x0
3753 19:22:54.541269 RD_PRE = 0x0
3754 19:22:54.541343 WR_PRE = 0x1
3755 19:22:54.544321 WR_PST = 0x0
3756 19:22:54.544393 DBI_WR = 0x0
3757 19:22:54.548085 DBI_RD = 0x0
3758 19:22:54.548155 OTF = 0x1
3759 19:22:54.550951 ===================================
3760 19:22:54.554200 ===================================
3761 19:22:54.557821 ANA top config
3762 19:22:54.561311 ===================================
3763 19:22:54.561395 DLL_ASYNC_EN = 0
3764 19:22:54.564313 ALL_SLAVE_EN = 1
3765 19:22:54.568050 NEW_RANK_MODE = 1
3766 19:22:54.571321 DLL_IDLE_MODE = 1
3767 19:22:54.571400 LP45_APHY_COMB_EN = 1
3768 19:22:54.574424 TX_ODT_DIS = 1
3769 19:22:54.577774 NEW_8X_MODE = 1
3770 19:22:54.580765 ===================================
3771 19:22:54.584299 ===================================
3772 19:22:54.587933 data_rate = 1200
3773 19:22:54.590981 CKR = 1
3774 19:22:54.593952 DQ_P2S_RATIO = 8
3775 19:22:54.597513 ===================================
3776 19:22:54.597616 CA_P2S_RATIO = 8
3777 19:22:54.600549 DQ_CA_OPEN = 0
3778 19:22:54.604189 DQ_SEMI_OPEN = 0
3779 19:22:54.607852 CA_SEMI_OPEN = 0
3780 19:22:54.610916 CA_FULL_RATE = 0
3781 19:22:54.613982 DQ_CKDIV4_EN = 1
3782 19:22:54.614065 CA_CKDIV4_EN = 1
3783 19:22:54.617427 CA_PREDIV_EN = 0
3784 19:22:54.620911 PH8_DLY = 0
3785 19:22:54.623815 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3786 19:22:54.627317 DQ_AAMCK_DIV = 4
3787 19:22:54.630298 CA_AAMCK_DIV = 4
3788 19:22:54.630379 CA_ADMCK_DIV = 4
3789 19:22:54.633719 DQ_TRACK_CA_EN = 0
3790 19:22:54.637107 CA_PICK = 600
3791 19:22:54.640242 CA_MCKIO = 600
3792 19:22:54.643830 MCKIO_SEMI = 0
3793 19:22:54.647010 PLL_FREQ = 2288
3794 19:22:54.650450 DQ_UI_PI_RATIO = 32
3795 19:22:54.650525 CA_UI_PI_RATIO = 0
3796 19:22:54.653831 ===================================
3797 19:22:54.657270 ===================================
3798 19:22:54.660471 memory_type:LPDDR4
3799 19:22:54.663872 GP_NUM : 10
3800 19:22:54.663947 SRAM_EN : 1
3801 19:22:54.666904 MD32_EN : 0
3802 19:22:54.670403 ===================================
3803 19:22:54.673437 [ANA_INIT] >>>>>>>>>>>>>>
3804 19:22:54.677000 <<<<<< [CONFIGURE PHASE]: ANA_TX
3805 19:22:54.679995 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3806 19:22:54.683374 ===================================
3807 19:22:54.683451 data_rate = 1200,PCW = 0X5800
3808 19:22:54.686981 ===================================
3809 19:22:54.690428 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3810 19:22:54.696800 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3811 19:22:54.703657 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3812 19:22:54.706617 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3813 19:22:54.709545 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3814 19:22:54.713164 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3815 19:22:54.716705 [ANA_INIT] flow start
3816 19:22:54.719787 [ANA_INIT] PLL >>>>>>>>
3817 19:22:54.719856 [ANA_INIT] PLL <<<<<<<<
3818 19:22:54.722869 [ANA_INIT] MIDPI >>>>>>>>
3819 19:22:54.726222 [ANA_INIT] MIDPI <<<<<<<<
3820 19:22:54.726313 [ANA_INIT] DLL >>>>>>>>
3821 19:22:54.729830 [ANA_INIT] flow end
3822 19:22:54.733251 ============ LP4 DIFF to SE enter ============
3823 19:22:54.736291 ============ LP4 DIFF to SE exit ============
3824 19:22:54.740102 [ANA_INIT] <<<<<<<<<<<<<
3825 19:22:54.742984 [Flow] Enable top DCM control >>>>>
3826 19:22:54.746578 [Flow] Enable top DCM control <<<<<
3827 19:22:54.749819 Enable DLL master slave shuffle
3828 19:22:54.756364 ==============================================================
3829 19:22:54.756445 Gating Mode config
3830 19:22:54.762886 ==============================================================
3831 19:22:54.762968 Config description:
3832 19:22:54.772933 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3833 19:22:54.779403 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3834 19:22:54.785978 SELPH_MODE 0: By rank 1: By Phase
3835 19:22:54.792513 ==============================================================
3836 19:22:54.792591 GAT_TRACK_EN = 1
3837 19:22:54.796091 RX_GATING_MODE = 2
3838 19:22:54.798887 RX_GATING_TRACK_MODE = 2
3839 19:22:54.802417 SELPH_MODE = 1
3840 19:22:54.805794 PICG_EARLY_EN = 1
3841 19:22:54.809654 VALID_LAT_VALUE = 1
3842 19:22:54.815683 ==============================================================
3843 19:22:54.819254 Enter into Gating configuration >>>>
3844 19:22:54.822264 Exit from Gating configuration <<<<
3845 19:22:54.825887 Enter into DVFS_PRE_config >>>>>
3846 19:22:54.835674 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3847 19:22:54.838828 Exit from DVFS_PRE_config <<<<<
3848 19:22:54.842414 Enter into PICG configuration >>>>
3849 19:22:54.845896 Exit from PICG configuration <<<<
3850 19:22:54.849412 [RX_INPUT] configuration >>>>>
3851 19:22:54.849572 [RX_INPUT] configuration <<<<<
3852 19:22:54.856029 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3853 19:22:54.862473 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3854 19:22:54.865733 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3855 19:22:54.872509 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3856 19:22:54.879021 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3857 19:22:54.885860 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3858 19:22:54.889389 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3859 19:22:54.892351 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3860 19:22:54.898982 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3861 19:22:54.902658 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3862 19:22:54.905479 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3863 19:22:54.909258 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3864 19:22:54.912174 ===================================
3865 19:22:54.915620 LPDDR4 DRAM CONFIGURATION
3866 19:22:54.918694 ===================================
3867 19:22:54.922090 EX_ROW_EN[0] = 0x0
3868 19:22:54.922170 EX_ROW_EN[1] = 0x0
3869 19:22:54.925845 LP4Y_EN = 0x0
3870 19:22:54.925925 WORK_FSP = 0x0
3871 19:22:54.929020 WL = 0x2
3872 19:22:54.929102 RL = 0x2
3873 19:22:54.932451 BL = 0x2
3874 19:22:54.935350 RPST = 0x0
3875 19:22:54.935425 RD_PRE = 0x0
3876 19:22:54.938892 WR_PRE = 0x1
3877 19:22:54.938968 WR_PST = 0x0
3878 19:22:54.942283 DBI_WR = 0x0
3879 19:22:54.942359 DBI_RD = 0x0
3880 19:22:54.945293 OTF = 0x1
3881 19:22:54.948310 ===================================
3882 19:22:54.951957 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3883 19:22:54.955024 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3884 19:22:54.962002 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3885 19:22:54.965049 ===================================
3886 19:22:54.965130 LPDDR4 DRAM CONFIGURATION
3887 19:22:54.968555 ===================================
3888 19:22:54.971407 EX_ROW_EN[0] = 0x10
3889 19:22:54.971488 EX_ROW_EN[1] = 0x0
3890 19:22:54.974732 LP4Y_EN = 0x0
3891 19:22:54.974812 WORK_FSP = 0x0
3892 19:22:54.977994 WL = 0x2
3893 19:22:54.981671 RL = 0x2
3894 19:22:54.981755 BL = 0x2
3895 19:22:54.985007 RPST = 0x0
3896 19:22:54.985089 RD_PRE = 0x0
3897 19:22:54.987776 WR_PRE = 0x1
3898 19:22:54.987856 WR_PST = 0x0
3899 19:22:54.991237 DBI_WR = 0x0
3900 19:22:54.991317 DBI_RD = 0x0
3901 19:22:54.995029 OTF = 0x1
3902 19:22:54.998053 ===================================
3903 19:22:55.004827 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3904 19:22:55.007835 nWR fixed to 30
3905 19:22:55.007922 [ModeRegInit_LP4] CH0 RK0
3906 19:22:55.011210 [ModeRegInit_LP4] CH0 RK1
3907 19:22:55.014817 [ModeRegInit_LP4] CH1 RK0
3908 19:22:55.014897 [ModeRegInit_LP4] CH1 RK1
3909 19:22:55.017829 match AC timing 17
3910 19:22:55.021390 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3911 19:22:55.024315 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3912 19:22:55.031584 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3913 19:22:55.034266 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3914 19:22:55.041087 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3915 19:22:55.041167 ==
3916 19:22:55.044160 Dram Type= 6, Freq= 0, CH_0, rank 0
3917 19:22:55.047595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3918 19:22:55.047702 ==
3919 19:22:55.054193 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3920 19:22:55.060789 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3921 19:22:55.064288 [CA 0] Center 37 (7~67) winsize 61
3922 19:22:55.067786 [CA 1] Center 37 (7~67) winsize 61
3923 19:22:55.070695 [CA 2] Center 35 (5~65) winsize 61
3924 19:22:55.074271 [CA 3] Center 35 (5~65) winsize 61
3925 19:22:55.077390 [CA 4] Center 34 (4~65) winsize 62
3926 19:22:55.080680 [CA 5] Center 34 (4~64) winsize 61
3927 19:22:55.080761
3928 19:22:55.083925 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3929 19:22:55.084005
3930 19:22:55.087461 [CATrainingPosCal] consider 1 rank data
3931 19:22:55.090878 u2DelayCellTimex100 = 270/100 ps
3932 19:22:55.093765 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3933 19:22:55.097208 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3934 19:22:55.100796 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3935 19:22:55.103706 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3936 19:22:55.107419 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3937 19:22:55.110794 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3938 19:22:55.110873
3939 19:22:55.117110 CA PerBit enable=1, Macro0, CA PI delay=34
3940 19:22:55.117189
3941 19:22:55.117251 [CBTSetCACLKResult] CA Dly = 34
3942 19:22:55.120231 CS Dly: 4 (0~35)
3943 19:22:55.120310 ==
3944 19:22:55.123921 Dram Type= 6, Freq= 0, CH_0, rank 1
3945 19:22:55.126955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3946 19:22:55.127036 ==
3947 19:22:55.133629 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3948 19:22:55.140164 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3949 19:22:55.143838 [CA 0] Center 37 (7~67) winsize 61
3950 19:22:55.146805 [CA 1] Center 37 (7~67) winsize 61
3951 19:22:55.149934 [CA 2] Center 35 (5~65) winsize 61
3952 19:22:55.153660 [CA 3] Center 35 (5~65) winsize 61
3953 19:22:55.156786 [CA 4] Center 34 (4~64) winsize 61
3954 19:22:55.159981 [CA 5] Center 34 (3~65) winsize 63
3955 19:22:55.160082
3956 19:22:55.163390 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3957 19:22:55.163464
3958 19:22:55.166459 [CATrainingPosCal] consider 2 rank data
3959 19:22:55.169984 u2DelayCellTimex100 = 270/100 ps
3960 19:22:55.173430 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3961 19:22:55.176507 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3962 19:22:55.180234 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3963 19:22:55.183152 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3964 19:22:55.186659 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
3965 19:22:55.193145 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3966 19:22:55.193224
3967 19:22:55.196447 CA PerBit enable=1, Macro0, CA PI delay=34
3968 19:22:55.196523
3969 19:22:55.199935 [CBTSetCACLKResult] CA Dly = 34
3970 19:22:55.200015 CS Dly: 5 (0~37)
3971 19:22:55.200080
3972 19:22:55.203476 ----->DramcWriteLeveling(PI) begin...
3973 19:22:55.203556 ==
3974 19:22:55.206468 Dram Type= 6, Freq= 0, CH_0, rank 0
3975 19:22:55.210082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3976 19:22:55.213197 ==
3977 19:22:55.216614 Write leveling (Byte 0): 32 => 32
3978 19:22:55.216694 Write leveling (Byte 1): 30 => 30
3979 19:22:55.220112 DramcWriteLeveling(PI) end<-----
3980 19:22:55.220191
3981 19:22:55.220253 ==
3982 19:22:55.223046 Dram Type= 6, Freq= 0, CH_0, rank 0
3983 19:22:55.229791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3984 19:22:55.229871 ==
3985 19:22:55.232860 [Gating] SW mode calibration
3986 19:22:55.240108 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3987 19:22:55.243097 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3988 19:22:55.249958 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3989 19:22:55.252832 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3990 19:22:55.256360 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3991 19:22:55.263094 0 9 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
3992 19:22:55.266564 0 9 16 | B1->B0 | 2f2f 2c2c | 1 0 | (1 1) (0 0)
3993 19:22:55.269774 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3994 19:22:55.275913 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3995 19:22:55.279378 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3996 19:22:55.282955 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3997 19:22:55.289664 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3998 19:22:55.292531 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3999 19:22:55.296001 0 10 12 | B1->B0 | 2323 2928 | 0 1 | (0 0) (1 1)
4000 19:22:55.299460 0 10 16 | B1->B0 | 3535 3c3c | 0 0 | (0 0) (0 0)
4001 19:22:55.306084 0 10 20 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
4002 19:22:55.309673 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4003 19:22:55.312627 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4004 19:22:55.319250 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4005 19:22:55.322819 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4006 19:22:55.325776 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4007 19:22:55.332375 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4008 19:22:55.335892 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4009 19:22:55.339259 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 19:22:55.345732 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 19:22:55.348923 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 19:22:55.352713 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 19:22:55.359225 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 19:22:55.362321 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 19:22:55.365900 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 19:22:55.372337 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 19:22:55.375810 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 19:22:55.379150 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 19:22:55.385355 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 19:22:55.389016 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 19:22:55.392464 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 19:22:55.398988 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 19:22:55.402109 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4024 19:22:55.405452 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4025 19:22:55.408767 Total UI for P1: 0, mck2ui 16
4026 19:22:55.412270 best dqsien dly found for B0: ( 0, 13, 12)
4027 19:22:55.418586 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4028 19:22:55.418666 Total UI for P1: 0, mck2ui 16
4029 19:22:55.425069 best dqsien dly found for B1: ( 0, 13, 16)
4030 19:22:55.428561 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4031 19:22:55.432186 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4032 19:22:55.432266
4033 19:22:55.435284 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4034 19:22:55.438872 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4035 19:22:55.441797 [Gating] SW calibration Done
4036 19:22:55.441876 ==
4037 19:22:55.445467 Dram Type= 6, Freq= 0, CH_0, rank 0
4038 19:22:55.448436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4039 19:22:55.448517 ==
4040 19:22:55.451773 RX Vref Scan: 0
4041 19:22:55.451845
4042 19:22:55.451905 RX Vref 0 -> 0, step: 1
4043 19:22:55.451963
4044 19:22:55.455471 RX Delay -230 -> 252, step: 16
4045 19:22:55.458764 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4046 19:22:55.465270 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4047 19:22:55.468344 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4048 19:22:55.471894 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4049 19:22:55.475264 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4050 19:22:55.481892 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4051 19:22:55.485400 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4052 19:22:55.488412 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4053 19:22:55.491802 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4054 19:22:55.498198 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4055 19:22:55.501414 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4056 19:22:55.505259 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4057 19:22:55.508183 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4058 19:22:55.514583 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4059 19:22:55.518006 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4060 19:22:55.521937 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4061 19:22:55.522018 ==
4062 19:22:55.524926 Dram Type= 6, Freq= 0, CH_0, rank 0
4063 19:22:55.527929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4064 19:22:55.528002 ==
4065 19:22:55.531493 DQS Delay:
4066 19:22:55.531574 DQS0 = 0, DQS1 = 0
4067 19:22:55.534554 DQM Delay:
4068 19:22:55.534634 DQM0 = 36, DQM1 = 29
4069 19:22:55.534697 DQ Delay:
4070 19:22:55.538029 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4071 19:22:55.541634 DQ4 =33, DQ5 =25, DQ6 =49, DQ7 =49
4072 19:22:55.544470 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4073 19:22:55.548105 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4074 19:22:55.548214
4075 19:22:55.548305
4076 19:22:55.551144 ==
4077 19:22:55.551229 Dram Type= 6, Freq= 0, CH_0, rank 0
4078 19:22:55.557769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4079 19:22:55.557875 ==
4080 19:22:55.557958
4081 19:22:55.558018
4082 19:22:55.561076 TX Vref Scan disable
4083 19:22:55.561188 == TX Byte 0 ==
4084 19:22:55.564644 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4085 19:22:55.571411 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4086 19:22:55.571492 == TX Byte 1 ==
4087 19:22:55.574402 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4088 19:22:55.581259 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4089 19:22:55.581365 ==
4090 19:22:55.584783 Dram Type= 6, Freq= 0, CH_0, rank 0
4091 19:22:55.588298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4092 19:22:55.588379 ==
4093 19:22:55.588442
4094 19:22:55.588501
4095 19:22:55.591232 TX Vref Scan disable
4096 19:22:55.594877 == TX Byte 0 ==
4097 19:22:55.597842 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4098 19:22:55.601419 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4099 19:22:55.604746 == TX Byte 1 ==
4100 19:22:55.607821 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4101 19:22:55.611134 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4102 19:22:55.611214
4103 19:22:55.614346 [DATLAT]
4104 19:22:55.614426 Freq=600, CH0 RK0
4105 19:22:55.614489
4106 19:22:55.617653 DATLAT Default: 0x9
4107 19:22:55.617736 0, 0xFFFF, sum = 0
4108 19:22:55.621026 1, 0xFFFF, sum = 0
4109 19:22:55.621108 2, 0xFFFF, sum = 0
4110 19:22:55.624534 3, 0xFFFF, sum = 0
4111 19:22:55.624616 4, 0xFFFF, sum = 0
4112 19:22:55.628087 5, 0xFFFF, sum = 0
4113 19:22:55.628169 6, 0xFFFF, sum = 0
4114 19:22:55.630959 7, 0xFFFF, sum = 0
4115 19:22:55.631040 8, 0x0, sum = 1
4116 19:22:55.634341 9, 0x0, sum = 2
4117 19:22:55.634423 10, 0x0, sum = 3
4118 19:22:55.637313 11, 0x0, sum = 4
4119 19:22:55.637394 best_step = 9
4120 19:22:55.637458
4121 19:22:55.637540 ==
4122 19:22:55.640860 Dram Type= 6, Freq= 0, CH_0, rank 0
4123 19:22:55.644013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4124 19:22:55.647430 ==
4125 19:22:55.647510 RX Vref Scan: 1
4126 19:22:55.647573
4127 19:22:55.651086 RX Vref 0 -> 0, step: 1
4128 19:22:55.651166
4129 19:22:55.654112 RX Delay -195 -> 252, step: 8
4130 19:22:55.654192
4131 19:22:55.657663 Set Vref, RX VrefLevel [Byte0]: 62
4132 19:22:55.660570 [Byte1]: 52
4133 19:22:55.660650
4134 19:22:55.664061 Final RX Vref Byte 0 = 62 to rank0
4135 19:22:55.667621 Final RX Vref Byte 1 = 52 to rank0
4136 19:22:55.670578 Final RX Vref Byte 0 = 62 to rank1
4137 19:22:55.674306 Final RX Vref Byte 1 = 52 to rank1==
4138 19:22:55.677226 Dram Type= 6, Freq= 0, CH_0, rank 0
4139 19:22:55.680763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4140 19:22:55.680844 ==
4141 19:22:55.684076 DQS Delay:
4142 19:22:55.684156 DQS0 = 0, DQS1 = 0
4143 19:22:55.684219 DQM Delay:
4144 19:22:55.687296 DQM0 = 35, DQM1 = 29
4145 19:22:55.687376 DQ Delay:
4146 19:22:55.690407 DQ0 =36, DQ1 =36, DQ2 =32, DQ3 =32
4147 19:22:55.693429 DQ4 =32, DQ5 =24, DQ6 =40, DQ7 =48
4148 19:22:55.696758 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4149 19:22:55.700251 DQ12 =36, DQ13 =36, DQ14 =40, DQ15 =36
4150 19:22:55.700341
4151 19:22:55.700405
4152 19:22:55.710373 [DQSOSCAuto] RK0, (LSB)MR18= 0x4342, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
4153 19:22:55.713648 CH0 RK0: MR19=808, MR18=4342
4154 19:22:55.716726 CH0_RK0: MR19=0x808, MR18=0x4342, DQSOSC=397, MR23=63, INC=166, DEC=110
4155 19:22:55.716815
4156 19:22:55.720426 ----->DramcWriteLeveling(PI) begin...
4157 19:22:55.723303 ==
4158 19:22:55.727012 Dram Type= 6, Freq= 0, CH_0, rank 1
4159 19:22:55.730199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4160 19:22:55.730373 ==
4161 19:22:55.733634 Write leveling (Byte 0): 33 => 33
4162 19:22:55.736907 Write leveling (Byte 1): 29 => 29
4163 19:22:55.740179 DramcWriteLeveling(PI) end<-----
4164 19:22:55.740279
4165 19:22:55.740373 ==
4166 19:22:55.743784 Dram Type= 6, Freq= 0, CH_0, rank 1
4167 19:22:55.746665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4168 19:22:55.746741 ==
4169 19:22:55.750347 [Gating] SW mode calibration
4170 19:22:55.756983 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4171 19:22:55.763452 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4172 19:22:55.766360 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4173 19:22:55.769963 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4174 19:22:55.773012 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4175 19:22:55.779952 0 9 12 | B1->B0 | 3333 2f2f | 1 1 | (1 1) (1 0)
4176 19:22:55.782930 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
4177 19:22:55.786555 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4178 19:22:55.793376 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4179 19:22:55.796190 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4180 19:22:55.800113 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4181 19:22:55.806370 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4182 19:22:55.809753 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4183 19:22:55.813106 0 10 12 | B1->B0 | 2c2c 3131 | 0 1 | (0 0) (0 0)
4184 19:22:55.819639 0 10 16 | B1->B0 | 3636 4646 | 0 0 | (1 1) (0 0)
4185 19:22:55.822904 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4186 19:22:55.826203 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4187 19:22:55.833104 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4188 19:22:55.836263 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4189 19:22:55.839516 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4190 19:22:55.846399 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4191 19:22:55.849597 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4192 19:22:55.852981 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4193 19:22:55.859806 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 19:22:55.862848 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 19:22:55.866293 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 19:22:55.872665 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 19:22:55.875787 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 19:22:55.879462 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 19:22:55.886131 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 19:22:55.889288 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 19:22:55.892733 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 19:22:55.899115 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 19:22:55.902662 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 19:22:55.905581 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 19:22:55.912297 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 19:22:55.915898 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 19:22:55.918869 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4208 19:22:55.922255 Total UI for P1: 0, mck2ui 16
4209 19:22:55.925860 best dqsien dly found for B0: ( 0, 13, 10)
4210 19:22:55.932251 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4211 19:22:55.932331 Total UI for P1: 0, mck2ui 16
4212 19:22:55.938428 best dqsien dly found for B1: ( 0, 13, 14)
4213 19:22:55.941852 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4214 19:22:55.945275 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4215 19:22:55.945376
4216 19:22:55.948643 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4217 19:22:55.951959 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4218 19:22:55.955164 [Gating] SW calibration Done
4219 19:22:55.955244 ==
4220 19:22:55.958569 Dram Type= 6, Freq= 0, CH_0, rank 1
4221 19:22:55.961737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4222 19:22:55.961818 ==
4223 19:22:55.965274 RX Vref Scan: 0
4224 19:22:55.965405
4225 19:22:55.965557 RX Vref 0 -> 0, step: 1
4226 19:22:55.965674
4227 19:22:55.968769 RX Delay -230 -> 252, step: 16
4228 19:22:55.975277 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4229 19:22:55.978721 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4230 19:22:55.981641 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4231 19:22:55.985214 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4232 19:22:55.991770 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4233 19:22:55.994554 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4234 19:22:55.998170 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4235 19:22:56.001746 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4236 19:22:56.004606 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4237 19:22:56.011202 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4238 19:22:56.014764 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4239 19:22:56.017737 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4240 19:22:56.021150 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4241 19:22:56.028042 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4242 19:22:56.031027 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4243 19:22:56.034317 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4244 19:22:56.034413 ==
4245 19:22:56.037660 Dram Type= 6, Freq= 0, CH_0, rank 1
4246 19:22:56.044321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4247 19:22:56.044430 ==
4248 19:22:56.044522 DQS Delay:
4249 19:22:56.044610 DQS0 = 0, DQS1 = 0
4250 19:22:56.047894 DQM Delay:
4251 19:22:56.047990 DQM0 = 38, DQM1 = 29
4252 19:22:56.051032 DQ Delay:
4253 19:22:56.054370 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4254 19:22:56.054486 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4255 19:22:56.057411 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =17
4256 19:22:56.060775 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4257 19:22:56.064179
4258 19:22:56.064275
4259 19:22:56.064384 ==
4260 19:22:56.067393 Dram Type= 6, Freq= 0, CH_0, rank 1
4261 19:22:56.070902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4262 19:22:56.071003 ==
4263 19:22:56.071091
4264 19:22:56.071180
4265 19:22:56.074247 TX Vref Scan disable
4266 19:22:56.074344 == TX Byte 0 ==
4267 19:22:56.080799 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4268 19:22:56.084445 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4269 19:22:56.084546 == TX Byte 1 ==
4270 19:22:56.091035 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4271 19:22:56.094180 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4272 19:22:56.094276 ==
4273 19:22:56.097082 Dram Type= 6, Freq= 0, CH_0, rank 1
4274 19:22:56.100733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4275 19:22:56.100838 ==
4276 19:22:56.100928
4277 19:22:56.101014
4278 19:22:56.103716 TX Vref Scan disable
4279 19:22:56.107726 == TX Byte 0 ==
4280 19:22:56.110772 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4281 19:22:56.117288 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4282 19:22:56.117400 == TX Byte 1 ==
4283 19:22:56.120339 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4284 19:22:56.126961 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4285 19:22:56.127063
4286 19:22:56.127155 [DATLAT]
4287 19:22:56.127242 Freq=600, CH0 RK1
4288 19:22:56.127342
4289 19:22:56.130550 DATLAT Default: 0x9
4290 19:22:56.130655 0, 0xFFFF, sum = 0
4291 19:22:56.134025 1, 0xFFFF, sum = 0
4292 19:22:56.137357 2, 0xFFFF, sum = 0
4293 19:22:56.137494 3, 0xFFFF, sum = 0
4294 19:22:56.140313 4, 0xFFFF, sum = 0
4295 19:22:56.140451 5, 0xFFFF, sum = 0
4296 19:22:56.143819 6, 0xFFFF, sum = 0
4297 19:22:56.143964 7, 0xFFFF, sum = 0
4298 19:22:56.147282 8, 0x0, sum = 1
4299 19:22:56.147429 9, 0x0, sum = 2
4300 19:22:56.147562 10, 0x0, sum = 3
4301 19:22:56.150309 11, 0x0, sum = 4
4302 19:22:56.150441 best_step = 9
4303 19:22:56.150557
4304 19:22:56.150672 ==
4305 19:22:56.153983 Dram Type= 6, Freq= 0, CH_0, rank 1
4306 19:22:56.160416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4307 19:22:56.160622 ==
4308 19:22:56.160754 RX Vref Scan: 0
4309 19:22:56.160878
4310 19:22:56.163631 RX Vref 0 -> 0, step: 1
4311 19:22:56.163719
4312 19:22:56.167128 RX Delay -195 -> 252, step: 8
4313 19:22:56.170398 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4314 19:22:56.177079 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4315 19:22:56.180113 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4316 19:22:56.183467 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4317 19:22:56.186614 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4318 19:22:56.193711 iDelay=205, Bit 5, Center 24 (-131 ~ 180) 312
4319 19:22:56.196588 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4320 19:22:56.200160 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4321 19:22:56.203728 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4322 19:22:56.206800 iDelay=205, Bit 9, Center 12 (-147 ~ 172) 320
4323 19:22:56.213255 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4324 19:22:56.216910 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4325 19:22:56.219974 iDelay=205, Bit 12, Center 32 (-131 ~ 196) 328
4326 19:22:56.223335 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4327 19:22:56.229876 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4328 19:22:56.232914 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4329 19:22:56.233011 ==
4330 19:22:56.236397 Dram Type= 6, Freq= 0, CH_0, rank 1
4331 19:22:56.239990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4332 19:22:56.240097 ==
4333 19:22:56.243153 DQS Delay:
4334 19:22:56.243250 DQS0 = 0, DQS1 = 0
4335 19:22:56.246608 DQM Delay:
4336 19:22:56.246712 DQM0 = 34, DQM1 = 27
4337 19:22:56.246803 DQ Delay:
4338 19:22:56.249421 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4339 19:22:56.253100 DQ4 =32, DQ5 =24, DQ6 =44, DQ7 =44
4340 19:22:56.256180 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4341 19:22:56.259560 DQ12 =32, DQ13 =36, DQ14 =36, DQ15 =36
4342 19:22:56.259663
4343 19:22:56.259753
4344 19:22:56.269836 [DQSOSCAuto] RK1, (LSB)MR18= 0x7342, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 388 ps
4345 19:22:56.272995 CH0 RK1: MR19=808, MR18=7342
4346 19:22:56.279328 CH0_RK1: MR19=0x808, MR18=0x7342, DQSOSC=388, MR23=63, INC=174, DEC=116
4347 19:22:56.279445 [RxdqsGatingPostProcess] freq 600
4348 19:22:56.285805 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4349 19:22:56.289538 Pre-setting of DQS Precalculation
4350 19:22:56.292896 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4351 19:22:56.296227 ==
4352 19:22:56.299597 Dram Type= 6, Freq= 0, CH_1, rank 0
4353 19:22:56.302590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4354 19:22:56.302690 ==
4355 19:22:56.306139 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4356 19:22:56.312608 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4357 19:22:56.316140 [CA 0] Center 35 (5~66) winsize 62
4358 19:22:56.319703 [CA 1] Center 35 (5~66) winsize 62
4359 19:22:56.323299 [CA 2] Center 34 (4~65) winsize 62
4360 19:22:56.326366 [CA 3] Center 34 (3~65) winsize 63
4361 19:22:56.329870 [CA 4] Center 34 (4~65) winsize 62
4362 19:22:56.332860 [CA 5] Center 33 (3~64) winsize 62
4363 19:22:56.332959
4364 19:22:56.336466 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4365 19:22:56.336540
4366 19:22:56.339555 [CATrainingPosCal] consider 1 rank data
4367 19:22:56.343212 u2DelayCellTimex100 = 270/100 ps
4368 19:22:56.346112 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4369 19:22:56.352780 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4370 19:22:56.356212 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4371 19:22:56.359490 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4372 19:22:56.362731 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4373 19:22:56.366048 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4374 19:22:56.366149
4375 19:22:56.369285 CA PerBit enable=1, Macro0, CA PI delay=33
4376 19:22:56.369386
4377 19:22:56.372413 [CBTSetCACLKResult] CA Dly = 33
4378 19:22:56.372513 CS Dly: 5 (0~36)
4379 19:22:56.376102 ==
4380 19:22:56.379181 Dram Type= 6, Freq= 0, CH_1, rank 1
4381 19:22:56.382636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4382 19:22:56.382733 ==
4383 19:22:56.389483 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4384 19:22:56.392235 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4385 19:22:56.396423 [CA 0] Center 36 (6~66) winsize 61
4386 19:22:56.399993 [CA 1] Center 36 (6~67) winsize 62
4387 19:22:56.403033 [CA 2] Center 34 (4~65) winsize 62
4388 19:22:56.406298 [CA 3] Center 34 (3~65) winsize 63
4389 19:22:56.409497 [CA 4] Center 34 (4~65) winsize 62
4390 19:22:56.413187 [CA 5] Center 33 (3~64) winsize 62
4391 19:22:56.413286
4392 19:22:56.416568 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4393 19:22:56.416649
4394 19:22:56.419476 [CATrainingPosCal] consider 2 rank data
4395 19:22:56.423274 u2DelayCellTimex100 = 270/100 ps
4396 19:22:56.426322 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4397 19:22:56.432888 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4398 19:22:56.436522 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4399 19:22:56.439460 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4400 19:22:56.443145 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4401 19:22:56.446154 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4402 19:22:56.446234
4403 19:22:56.449221 CA PerBit enable=1, Macro0, CA PI delay=33
4404 19:22:56.449300
4405 19:22:56.452708 [CBTSetCACLKResult] CA Dly = 33
4406 19:22:56.456356 CS Dly: 5 (0~36)
4407 19:22:56.456435
4408 19:22:56.459387 ----->DramcWriteLeveling(PI) begin...
4409 19:22:56.459467 ==
4410 19:22:56.462886 Dram Type= 6, Freq= 0, CH_1, rank 0
4411 19:22:56.465825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4412 19:22:56.465905 ==
4413 19:22:56.469126 Write leveling (Byte 0): 28 => 28
4414 19:22:56.472610 Write leveling (Byte 1): 29 => 29
4415 19:22:56.475825 DramcWriteLeveling(PI) end<-----
4416 19:22:56.475903
4417 19:22:56.475965 ==
4418 19:22:56.479013 Dram Type= 6, Freq= 0, CH_1, rank 0
4419 19:22:56.482485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4420 19:22:56.482564 ==
4421 19:22:56.485860 [Gating] SW mode calibration
4422 19:22:56.492376 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4423 19:22:56.499134 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4424 19:22:56.502235 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4425 19:22:56.505538 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4426 19:22:56.512083 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4427 19:22:56.515705 0 9 12 | B1->B0 | 2f2f 3131 | 0 0 | (0 0) (0 0)
4428 19:22:56.518574 0 9 16 | B1->B0 | 2727 2929 | 0 0 | (0 0) (0 0)
4429 19:22:56.525505 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4430 19:22:56.528949 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4431 19:22:56.531796 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4432 19:22:56.538752 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4433 19:22:56.541771 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4434 19:22:56.545331 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4435 19:22:56.551971 0 10 12 | B1->B0 | 2f2f 3030 | 0 0 | (0 0) (0 0)
4436 19:22:56.554893 0 10 16 | B1->B0 | 4444 4444 | 1 0 | (0 0) (0 0)
4437 19:22:56.558581 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4438 19:22:56.565320 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4439 19:22:56.568665 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4440 19:22:56.571479 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4441 19:22:56.578195 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4442 19:22:56.581493 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4443 19:22:56.584926 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4444 19:22:56.591834 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 19:22:56.595376 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 19:22:56.598576 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 19:22:56.604938 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 19:22:56.608393 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 19:22:56.611460 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 19:22:56.618034 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 19:22:56.621464 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 19:22:56.624956 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 19:22:56.631573 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 19:22:56.634606 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 19:22:56.638207 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 19:22:56.644450 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 19:22:56.648016 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 19:22:56.651314 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 19:22:56.654395 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 19:22:56.661057 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4461 19:22:56.664534 Total UI for P1: 0, mck2ui 16
4462 19:22:56.667692 best dqsien dly found for B1: ( 0, 13, 14)
4463 19:22:56.671266 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4464 19:22:56.674702 Total UI for P1: 0, mck2ui 16
4465 19:22:56.678209 best dqsien dly found for B0: ( 0, 13, 16)
4466 19:22:56.681155 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4467 19:22:56.684306 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4468 19:22:56.684384
4469 19:22:56.687744 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4470 19:22:56.694696 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4471 19:22:56.694776 [Gating] SW calibration Done
4472 19:22:56.694839 ==
4473 19:22:56.697937 Dram Type= 6, Freq= 0, CH_1, rank 0
4474 19:22:56.704026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4475 19:22:56.704141 ==
4476 19:22:56.704235 RX Vref Scan: 0
4477 19:22:56.704327
4478 19:22:56.707474 RX Vref 0 -> 0, step: 1
4479 19:22:56.707572
4480 19:22:56.710922 RX Delay -230 -> 252, step: 16
4481 19:22:56.714506 iDelay=218, Bit 0, Center 41 (-134 ~ 217) 352
4482 19:22:56.717824 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4483 19:22:56.720991 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4484 19:22:56.727331 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4485 19:22:56.731079 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4486 19:22:56.734064 iDelay=218, Bit 5, Center 41 (-134 ~ 217) 352
4487 19:22:56.737165 iDelay=218, Bit 6, Center 41 (-134 ~ 217) 352
4488 19:22:56.743715 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4489 19:22:56.747266 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4490 19:22:56.750780 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4491 19:22:56.753760 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4492 19:22:56.760273 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4493 19:22:56.763986 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4494 19:22:56.766978 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4495 19:22:56.770697 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4496 19:22:56.777119 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4497 19:22:56.777218 ==
4498 19:22:56.780569 Dram Type= 6, Freq= 0, CH_1, rank 0
4499 19:22:56.783698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4500 19:22:56.783807 ==
4501 19:22:56.783900 DQS Delay:
4502 19:22:56.787275 DQS0 = 0, DQS1 = 0
4503 19:22:56.787375 DQM Delay:
4504 19:22:56.790260 DQM0 = 36, DQM1 = 29
4505 19:22:56.790361 DQ Delay:
4506 19:22:56.793792 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4507 19:22:56.796654 DQ4 =33, DQ5 =41, DQ6 =41, DQ7 =33
4508 19:22:56.800131 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4509 19:22:56.803493 DQ12 =33, DQ13 =41, DQ14 =33, DQ15 =33
4510 19:22:56.803596
4511 19:22:56.803685
4512 19:22:56.803768 ==
4513 19:22:56.806826 Dram Type= 6, Freq= 0, CH_1, rank 0
4514 19:22:56.809937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4515 19:22:56.810033 ==
4516 19:22:56.813328
4517 19:22:56.813424
4518 19:22:56.813520 TX Vref Scan disable
4519 19:22:56.816703 == TX Byte 0 ==
4520 19:22:56.820274 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4521 19:22:56.823332 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4522 19:22:56.826744 == TX Byte 1 ==
4523 19:22:56.829606 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4524 19:22:56.832896 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4525 19:22:56.836626 ==
4526 19:22:56.836726 Dram Type= 6, Freq= 0, CH_1, rank 0
4527 19:22:56.843117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4528 19:22:56.843223 ==
4529 19:22:56.843315
4530 19:22:56.843400
4531 19:22:56.846185 TX Vref Scan disable
4532 19:22:56.846286 == TX Byte 0 ==
4533 19:22:56.853261 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4534 19:22:56.856241 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4535 19:22:56.856321 == TX Byte 1 ==
4536 19:22:56.862764 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4537 19:22:56.866355 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4538 19:22:56.866434
4539 19:22:56.866496 [DATLAT]
4540 19:22:56.869855 Freq=600, CH1 RK0
4541 19:22:56.869946
4542 19:22:56.870016 DATLAT Default: 0x9
4543 19:22:56.873026 0, 0xFFFF, sum = 0
4544 19:22:56.873113 1, 0xFFFF, sum = 0
4545 19:22:56.876493 2, 0xFFFF, sum = 0
4546 19:22:56.876573 3, 0xFFFF, sum = 0
4547 19:22:56.879390 4, 0xFFFF, sum = 0
4548 19:22:56.883021 5, 0xFFFF, sum = 0
4549 19:22:56.883101 6, 0xFFFF, sum = 0
4550 19:22:56.886012 7, 0xFFFF, sum = 0
4551 19:22:56.886092 8, 0x0, sum = 1
4552 19:22:56.886156 9, 0x0, sum = 2
4553 19:22:56.889381 10, 0x0, sum = 3
4554 19:22:56.889487 11, 0x0, sum = 4
4555 19:22:56.893078 best_step = 9
4556 19:22:56.893156
4557 19:22:56.893219 ==
4558 19:22:56.896089 Dram Type= 6, Freq= 0, CH_1, rank 0
4559 19:22:56.899044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4560 19:22:56.899123 ==
4561 19:22:56.902618 RX Vref Scan: 1
4562 19:22:56.902696
4563 19:22:56.902757 RX Vref 0 -> 0, step: 1
4564 19:22:56.902815
4565 19:22:56.906012 RX Delay -195 -> 252, step: 8
4566 19:22:56.906094
4567 19:22:56.908927 Set Vref, RX VrefLevel [Byte0]: 59
4568 19:22:56.912233 [Byte1]: 47
4569 19:22:56.916637
4570 19:22:56.916715 Final RX Vref Byte 0 = 59 to rank0
4571 19:22:56.920009 Final RX Vref Byte 1 = 47 to rank0
4572 19:22:56.923445 Final RX Vref Byte 0 = 59 to rank1
4573 19:22:56.926381 Final RX Vref Byte 1 = 47 to rank1==
4574 19:22:56.929784 Dram Type= 6, Freq= 0, CH_1, rank 0
4575 19:22:56.936326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4576 19:22:56.936406 ==
4577 19:22:56.936469 DQS Delay:
4578 19:22:56.936527 DQS0 = 0, DQS1 = 0
4579 19:22:56.939793 DQM Delay:
4580 19:22:56.939872 DQM0 = 38, DQM1 = 28
4581 19:22:56.943137 DQ Delay:
4582 19:22:56.946256 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4583 19:22:56.949598 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =36
4584 19:22:56.952984 DQ8 =12, DQ9 =20, DQ10 =28, DQ11 =20
4585 19:22:56.956562 DQ12 =40, DQ13 =36, DQ14 =36, DQ15 =36
4586 19:22:56.956661
4587 19:22:56.956752
4588 19:22:56.962804 [DQSOSCAuto] RK0, (LSB)MR18= 0x2230, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 403 ps
4589 19:22:56.966215 CH1 RK0: MR19=808, MR18=2230
4590 19:22:56.972796 CH1_RK0: MR19=0x808, MR18=0x2230, DQSOSC=400, MR23=63, INC=163, DEC=109
4591 19:22:56.972895
4592 19:22:56.976431 ----->DramcWriteLeveling(PI) begin...
4593 19:22:56.976531 ==
4594 19:22:56.979311 Dram Type= 6, Freq= 0, CH_1, rank 1
4595 19:22:56.982873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4596 19:22:56.982972 ==
4597 19:22:56.986234 Write leveling (Byte 0): 32 => 32
4598 19:22:56.989615 Write leveling (Byte 1): 32 => 32
4599 19:22:56.992697 DramcWriteLeveling(PI) end<-----
4600 19:22:56.992794
4601 19:22:56.992879 ==
4602 19:22:56.996109 Dram Type= 6, Freq= 0, CH_1, rank 1
4603 19:22:56.999208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4604 19:22:56.999307 ==
4605 19:22:57.002728 [Gating] SW mode calibration
4606 19:22:57.009313 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4607 19:22:57.015732 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4608 19:22:57.019087 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4609 19:22:57.026113 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4610 19:22:57.028974 0 9 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
4611 19:22:57.032911 0 9 12 | B1->B0 | 2f2f 2c2c | 1 0 | (1 0) (0 0)
4612 19:22:57.039210 0 9 16 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
4613 19:22:57.042275 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4614 19:22:57.045806 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4615 19:22:57.051981 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4616 19:22:57.055317 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4617 19:22:57.058989 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4618 19:22:57.065389 0 10 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
4619 19:22:57.069046 0 10 12 | B1->B0 | 2d2d 3939 | 1 0 | (0 0) (0 0)
4620 19:22:57.072054 0 10 16 | B1->B0 | 3f3f 4646 | 0 0 | (1 1) (0 0)
4621 19:22:57.078701 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4622 19:22:57.082329 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4623 19:22:57.085414 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4624 19:22:57.092031 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4625 19:22:57.095433 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4626 19:22:57.098894 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4627 19:22:57.105366 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 19:22:57.108442 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 19:22:57.112107 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 19:22:57.114978 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 19:22:57.122360 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 19:22:57.125150 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 19:22:57.128410 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 19:22:57.135279 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 19:22:57.138690 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 19:22:57.142032 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 19:22:57.148399 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 19:22:57.151406 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 19:22:57.154892 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 19:22:57.161283 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 19:22:57.164686 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 19:22:57.168036 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 19:22:57.174636 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4644 19:22:57.178236 Total UI for P1: 0, mck2ui 16
4645 19:22:57.181257 best dqsien dly found for B0: ( 0, 13, 10)
4646 19:22:57.184814 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4647 19:22:57.187946 Total UI for P1: 0, mck2ui 16
4648 19:22:57.191530 best dqsien dly found for B1: ( 0, 13, 12)
4649 19:22:57.194625 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4650 19:22:57.197656 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4651 19:22:57.197735
4652 19:22:57.201164 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4653 19:22:57.207739 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4654 19:22:57.207819 [Gating] SW calibration Done
4655 19:22:57.207881 ==
4656 19:22:57.211442 Dram Type= 6, Freq= 0, CH_1, rank 1
4657 19:22:57.217769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4658 19:22:57.217848 ==
4659 19:22:57.217910 RX Vref Scan: 0
4660 19:22:57.217969
4661 19:22:57.221367 RX Vref 0 -> 0, step: 1
4662 19:22:57.221470
4663 19:22:57.224265 RX Delay -230 -> 252, step: 16
4664 19:22:57.227872 iDelay=218, Bit 0, Center 41 (-134 ~ 217) 352
4665 19:22:57.230884 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4666 19:22:57.234340 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4667 19:22:57.241157 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4668 19:22:57.244539 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4669 19:22:57.247482 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4670 19:22:57.250891 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4671 19:22:57.257443 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4672 19:22:57.260811 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4673 19:22:57.264372 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4674 19:22:57.267396 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4675 19:22:57.274378 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4676 19:22:57.277439 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4677 19:22:57.280904 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4678 19:22:57.284379 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4679 19:22:57.290319 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4680 19:22:57.290393 ==
4681 19:22:57.293951 Dram Type= 6, Freq= 0, CH_1, rank 1
4682 19:22:57.296955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4683 19:22:57.297025 ==
4684 19:22:57.297085 DQS Delay:
4685 19:22:57.300584 DQS0 = 0, DQS1 = 0
4686 19:22:57.300679 DQM Delay:
4687 19:22:57.303757 DQM0 = 36, DQM1 = 29
4688 19:22:57.303858 DQ Delay:
4689 19:22:57.306795 DQ0 =41, DQ1 =33, DQ2 =17, DQ3 =33
4690 19:22:57.310427 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4691 19:22:57.314064 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4692 19:22:57.317093 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4693 19:22:57.317171
4694 19:22:57.317233
4695 19:22:57.317290 ==
4696 19:22:57.320694 Dram Type= 6, Freq= 0, CH_1, rank 1
4697 19:22:57.323767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4698 19:22:57.323846 ==
4699 19:22:57.323909
4700 19:22:57.323966
4701 19:22:57.327175 TX Vref Scan disable
4702 19:22:57.330452 == TX Byte 0 ==
4703 19:22:57.333902 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4704 19:22:57.337133 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4705 19:22:57.340467 == TX Byte 1 ==
4706 19:22:57.343808 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4707 19:22:57.347143 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4708 19:22:57.347232 ==
4709 19:22:57.350050 Dram Type= 6, Freq= 0, CH_1, rank 1
4710 19:22:57.356745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4711 19:22:57.356823 ==
4712 19:22:57.356886
4713 19:22:57.356944
4714 19:22:57.357000 TX Vref Scan disable
4715 19:22:57.361749 == TX Byte 0 ==
4716 19:22:57.364484 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4717 19:22:57.368112 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4718 19:22:57.371174 == TX Byte 1 ==
4719 19:22:57.374797 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4720 19:22:57.381374 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4721 19:22:57.381471
4722 19:22:57.381581 [DATLAT]
4723 19:22:57.381638 Freq=600, CH1 RK1
4724 19:22:57.381694
4725 19:22:57.384165 DATLAT Default: 0x9
4726 19:22:57.384228 0, 0xFFFF, sum = 0
4727 19:22:57.387536 1, 0xFFFF, sum = 0
4728 19:22:57.387605 2, 0xFFFF, sum = 0
4729 19:22:57.391384 3, 0xFFFF, sum = 0
4730 19:22:57.394388 4, 0xFFFF, sum = 0
4731 19:22:57.394468 5, 0xFFFF, sum = 0
4732 19:22:57.398029 6, 0xFFFF, sum = 0
4733 19:22:57.398109 7, 0xFFFF, sum = 0
4734 19:22:57.401079 8, 0x0, sum = 1
4735 19:22:57.401158 9, 0x0, sum = 2
4736 19:22:57.401221 10, 0x0, sum = 3
4737 19:22:57.404622 11, 0x0, sum = 4
4738 19:22:57.404702 best_step = 9
4739 19:22:57.404764
4740 19:22:57.404821 ==
4741 19:22:57.407694 Dram Type= 6, Freq= 0, CH_1, rank 1
4742 19:22:57.414317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4743 19:22:57.414429 ==
4744 19:22:57.414521 RX Vref Scan: 0
4745 19:22:57.414619
4746 19:22:57.417447 RX Vref 0 -> 0, step: 1
4747 19:22:57.417588
4748 19:22:57.420895 RX Delay -195 -> 252, step: 8
4749 19:22:57.424616 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4750 19:22:57.431116 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4751 19:22:57.434372 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4752 19:22:57.437732 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4753 19:22:57.441092 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4754 19:22:57.447711 iDelay=205, Bit 5, Center 44 (-115 ~ 204) 320
4755 19:22:57.450771 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4756 19:22:57.454359 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4757 19:22:57.457345 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4758 19:22:57.460592 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4759 19:22:57.467126 iDelay=205, Bit 10, Center 32 (-131 ~ 196) 328
4760 19:22:57.470524 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4761 19:22:57.474186 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4762 19:22:57.477292 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4763 19:22:57.483729 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4764 19:22:57.487477 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4765 19:22:57.487579 ==
4766 19:22:57.490601 Dram Type= 6, Freq= 0, CH_1, rank 1
4767 19:22:57.494025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4768 19:22:57.494105 ==
4769 19:22:57.497455 DQS Delay:
4770 19:22:57.497557 DQS0 = 0, DQS1 = 0
4771 19:22:57.497620 DQM Delay:
4772 19:22:57.500268 DQM0 = 36, DQM1 = 30
4773 19:22:57.500371 DQ Delay:
4774 19:22:57.503854 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4775 19:22:57.507370 DQ4 =32, DQ5 =44, DQ6 =48, DQ7 =36
4776 19:22:57.510895 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4777 19:22:57.513962 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4778 19:22:57.514041
4779 19:22:57.514103
4780 19:22:57.523721 [DQSOSCAuto] RK1, (LSB)MR18= 0x395a, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
4781 19:22:57.527292 CH1 RK1: MR19=808, MR18=395A
4782 19:22:57.530432 CH1_RK1: MR19=0x808, MR18=0x395A, DQSOSC=392, MR23=63, INC=170, DEC=113
4783 19:22:57.533493 [RxdqsGatingPostProcess] freq 600
4784 19:22:57.540300 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4785 19:22:57.543821 Pre-setting of DQS Precalculation
4786 19:22:57.546881 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4787 19:22:57.556775 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4788 19:22:57.563241 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4789 19:22:57.563346
4790 19:22:57.563439
4791 19:22:57.566899 [Calibration Summary] 1200 Mbps
4792 19:22:57.567004 CH 0, Rank 0
4793 19:22:57.570346 SW Impedance : PASS
4794 19:22:57.570446 DUTY Scan : NO K
4795 19:22:57.573154 ZQ Calibration : PASS
4796 19:22:57.576469 Jitter Meter : NO K
4797 19:22:57.576584 CBT Training : PASS
4798 19:22:57.579787 Write leveling : PASS
4799 19:22:57.583151 RX DQS gating : PASS
4800 19:22:57.583293 RX DQ/DQS(RDDQC) : PASS
4801 19:22:57.586688 TX DQ/DQS : PASS
4802 19:22:57.590097 RX DATLAT : PASS
4803 19:22:57.590248 RX DQ/DQS(Engine): PASS
4804 19:22:57.593468 TX OE : NO K
4805 19:22:57.593622 All Pass.
4806 19:22:57.593753
4807 19:22:57.596721 CH 0, Rank 1
4808 19:22:57.596838 SW Impedance : PASS
4809 19:22:57.600258 DUTY Scan : NO K
4810 19:22:57.600370 ZQ Calibration : PASS
4811 19:22:57.603143 Jitter Meter : NO K
4812 19:22:57.606774 CBT Training : PASS
4813 19:22:57.606860 Write leveling : PASS
4814 19:22:57.609675 RX DQS gating : PASS
4815 19:22:57.613209 RX DQ/DQS(RDDQC) : PASS
4816 19:22:57.613315 TX DQ/DQS : PASS
4817 19:22:57.616801 RX DATLAT : PASS
4818 19:22:57.619713 RX DQ/DQS(Engine): PASS
4819 19:22:57.619817 TX OE : NO K
4820 19:22:57.623372 All Pass.
4821 19:22:57.623477
4822 19:22:57.623573 CH 1, Rank 0
4823 19:22:57.626572 SW Impedance : PASS
4824 19:22:57.626667 DUTY Scan : NO K
4825 19:22:57.629638 ZQ Calibration : PASS
4826 19:22:57.633282 Jitter Meter : NO K
4827 19:22:57.633377 CBT Training : PASS
4828 19:22:57.636333 Write leveling : PASS
4829 19:22:57.639473 RX DQS gating : PASS
4830 19:22:57.639578 RX DQ/DQS(RDDQC) : PASS
4831 19:22:57.643218 TX DQ/DQS : PASS
4832 19:22:57.646408 RX DATLAT : PASS
4833 19:22:57.646488 RX DQ/DQS(Engine): PASS
4834 19:22:57.649866 TX OE : NO K
4835 19:22:57.649981 All Pass.
4836 19:22:57.650049
4837 19:22:57.652933 CH 1, Rank 1
4838 19:22:57.653047 SW Impedance : PASS
4839 19:22:57.656523 DUTY Scan : NO K
4840 19:22:57.656626 ZQ Calibration : PASS
4841 19:22:57.659365 Jitter Meter : NO K
4842 19:22:57.662809 CBT Training : PASS
4843 19:22:57.662882 Write leveling : PASS
4844 19:22:57.665815 RX DQS gating : PASS
4845 19:22:57.669387 RX DQ/DQS(RDDQC) : PASS
4846 19:22:57.669492 TX DQ/DQS : PASS
4847 19:22:57.672550 RX DATLAT : PASS
4848 19:22:57.676125 RX DQ/DQS(Engine): PASS
4849 19:22:57.676223 TX OE : NO K
4850 19:22:57.679128 All Pass.
4851 19:22:57.679217
4852 19:22:57.679281 DramC Write-DBI off
4853 19:22:57.682583 PER_BANK_REFRESH: Hybrid Mode
4854 19:22:57.686205 TX_TRACKING: ON
4855 19:22:57.692604 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4856 19:22:57.696186 [FAST_K] Save calibration result to emmc
4857 19:22:57.699044 dramc_set_vcore_voltage set vcore to 662500
4858 19:22:57.702732 Read voltage for 933, 3
4859 19:22:57.702819 Vio18 = 0
4860 19:22:57.705990 Vcore = 662500
4861 19:22:57.706074 Vdram = 0
4862 19:22:57.706146 Vddq = 0
4863 19:22:57.709271 Vmddr = 0
4864 19:22:57.712368 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4865 19:22:57.719600 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4866 19:22:57.719736 MEM_TYPE=3, freq_sel=17
4867 19:22:57.722938 sv_algorithm_assistance_LP4_1600
4868 19:22:57.729305 ============ PULL DRAM RESETB DOWN ============
4869 19:22:57.732475 ========== PULL DRAM RESETB DOWN end =========
4870 19:22:57.736024 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4871 19:22:57.739677 ===================================
4872 19:22:57.742659 LPDDR4 DRAM CONFIGURATION
4873 19:22:57.746243 ===================================
4874 19:22:57.746587 EX_ROW_EN[0] = 0x0
4875 19:22:57.749428 EX_ROW_EN[1] = 0x0
4876 19:22:57.752850 LP4Y_EN = 0x0
4877 19:22:57.753173 WORK_FSP = 0x0
4878 19:22:57.755799 WL = 0x3
4879 19:22:57.756390 RL = 0x3
4880 19:22:57.759228 BL = 0x2
4881 19:22:57.759642 RPST = 0x0
4882 19:22:57.762811 RD_PRE = 0x0
4883 19:22:57.763221 WR_PRE = 0x1
4884 19:22:57.766208 WR_PST = 0x0
4885 19:22:57.766750 DBI_WR = 0x0
4886 19:22:57.769196 DBI_RD = 0x0
4887 19:22:57.769648 OTF = 0x1
4888 19:22:57.772803 ===================================
4889 19:22:57.775752 ===================================
4890 19:22:57.779473 ANA top config
4891 19:22:57.782418 ===================================
4892 19:22:57.782833 DLL_ASYNC_EN = 0
4893 19:22:57.785957 ALL_SLAVE_EN = 1
4894 19:22:57.789497 NEW_RANK_MODE = 1
4895 19:22:57.792417 DLL_IDLE_MODE = 1
4896 19:22:57.795902 LP45_APHY_COMB_EN = 1
4897 19:22:57.796319 TX_ODT_DIS = 1
4898 19:22:57.799119 NEW_8X_MODE = 1
4899 19:22:57.802711 ===================================
4900 19:22:57.805579 ===================================
4901 19:22:57.809287 data_rate = 1866
4902 19:22:57.812270 CKR = 1
4903 19:22:57.815687 DQ_P2S_RATIO = 8
4904 19:22:57.818929 ===================================
4905 19:22:57.822198 CA_P2S_RATIO = 8
4906 19:22:57.822601 DQ_CA_OPEN = 0
4907 19:22:57.825754 DQ_SEMI_OPEN = 0
4908 19:22:57.829321 CA_SEMI_OPEN = 0
4909 19:22:57.832670 CA_FULL_RATE = 0
4910 19:22:57.835835 DQ_CKDIV4_EN = 1
4911 19:22:57.838830 CA_CKDIV4_EN = 1
4912 19:22:57.839292 CA_PREDIV_EN = 0
4913 19:22:57.842422 PH8_DLY = 0
4914 19:22:57.845669 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4915 19:22:57.849202 DQ_AAMCK_DIV = 4
4916 19:22:57.852293 CA_AAMCK_DIV = 4
4917 19:22:57.852893 CA_ADMCK_DIV = 4
4918 19:22:57.855814 DQ_TRACK_CA_EN = 0
4919 19:22:57.858762 CA_PICK = 933
4920 19:22:57.862376 CA_MCKIO = 933
4921 19:22:57.865189 MCKIO_SEMI = 0
4922 19:22:57.868635 PLL_FREQ = 3732
4923 19:22:57.872111 DQ_UI_PI_RATIO = 32
4924 19:22:57.872663 CA_UI_PI_RATIO = 0
4925 19:22:57.875745 ===================================
4926 19:22:57.878662 ===================================
4927 19:22:57.881965 memory_type:LPDDR4
4928 19:22:57.885141 GP_NUM : 10
4929 19:22:57.885221 SRAM_EN : 1
4930 19:22:57.888642 MD32_EN : 0
4931 19:22:57.891494 ===================================
4932 19:22:57.895162 [ANA_INIT] >>>>>>>>>>>>>>
4933 19:22:57.898371 <<<<<< [CONFIGURE PHASE]: ANA_TX
4934 19:22:57.901823 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4935 19:22:57.904700 ===================================
4936 19:22:57.907902 data_rate = 1866,PCW = 0X8f00
4937 19:22:57.911605 ===================================
4938 19:22:57.915222 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4939 19:22:57.918328 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4940 19:22:57.924825 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4941 19:22:57.927889 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4942 19:22:57.931333 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4943 19:22:57.934447 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4944 19:22:57.937828 [ANA_INIT] flow start
4945 19:22:57.941037 [ANA_INIT] PLL >>>>>>>>
4946 19:22:57.941117 [ANA_INIT] PLL <<<<<<<<
4947 19:22:57.944470 [ANA_INIT] MIDPI >>>>>>>>
4948 19:22:57.947974 [ANA_INIT] MIDPI <<<<<<<<
4949 19:22:57.948055 [ANA_INIT] DLL >>>>>>>>
4950 19:22:57.950886 [ANA_INIT] flow end
4951 19:22:57.954850 ============ LP4 DIFF to SE enter ============
4952 19:22:57.961297 ============ LP4 DIFF to SE exit ============
4953 19:22:57.961408 [ANA_INIT] <<<<<<<<<<<<<
4954 19:22:57.964490 [Flow] Enable top DCM control >>>>>
4955 19:22:57.967706 [Flow] Enable top DCM control <<<<<
4956 19:22:57.971058 Enable DLL master slave shuffle
4957 19:22:57.977531 ==============================================================
4958 19:22:57.977613 Gating Mode config
4959 19:22:57.984315 ==============================================================
4960 19:22:57.987280 Config description:
4961 19:22:57.994231 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4962 19:22:58.000895 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4963 19:22:58.007589 SELPH_MODE 0: By rank 1: By Phase
4964 19:22:58.013859 ==============================================================
4965 19:22:58.017186 GAT_TRACK_EN = 1
4966 19:22:58.017288 RX_GATING_MODE = 2
4967 19:22:58.020919 RX_GATING_TRACK_MODE = 2
4968 19:22:58.023953 SELPH_MODE = 1
4969 19:22:58.027699 PICG_EARLY_EN = 1
4970 19:22:58.030604 VALID_LAT_VALUE = 1
4971 19:22:58.037129 ==============================================================
4972 19:22:58.040694 Enter into Gating configuration >>>>
4973 19:22:58.043795 Exit from Gating configuration <<<<
4974 19:22:58.047224 Enter into DVFS_PRE_config >>>>>
4975 19:22:58.057274 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4976 19:22:58.060377 Exit from DVFS_PRE_config <<<<<
4977 19:22:58.064066 Enter into PICG configuration >>>>
4978 19:22:58.066872 Exit from PICG configuration <<<<
4979 19:22:58.070324 [RX_INPUT] configuration >>>>>
4980 19:22:58.073551 [RX_INPUT] configuration <<<<<
4981 19:22:58.076938 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4982 19:22:58.083476 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4983 19:22:58.090342 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4984 19:22:58.096943 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4985 19:22:58.099839 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4986 19:22:58.106849 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4987 19:22:58.110590 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4988 19:22:58.117031 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4989 19:22:58.119908 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4990 19:22:58.123453 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4991 19:22:58.126734 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4992 19:22:58.133233 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4993 19:22:58.136318 ===================================
4994 19:22:58.139733 LPDDR4 DRAM CONFIGURATION
4995 19:22:58.140153 ===================================
4996 19:22:58.143158 EX_ROW_EN[0] = 0x0
4997 19:22:58.146754 EX_ROW_EN[1] = 0x0
4998 19:22:58.147281 LP4Y_EN = 0x0
4999 19:22:58.149835 WORK_FSP = 0x0
5000 19:22:58.150288 WL = 0x3
5001 19:22:58.153291 RL = 0x3
5002 19:22:58.153792 BL = 0x2
5003 19:22:58.156303 RPST = 0x0
5004 19:22:58.156758 RD_PRE = 0x0
5005 19:22:58.160105 WR_PRE = 0x1
5006 19:22:58.160596 WR_PST = 0x0
5007 19:22:58.163166 DBI_WR = 0x0
5008 19:22:58.163695 DBI_RD = 0x0
5009 19:22:58.166814 OTF = 0x1
5010 19:22:58.169700 ===================================
5011 19:22:58.173214 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5012 19:22:58.176112 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5013 19:22:58.183583 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5014 19:22:58.186718 ===================================
5015 19:22:58.187230 LPDDR4 DRAM CONFIGURATION
5016 19:22:58.189615 ===================================
5017 19:22:58.193026 EX_ROW_EN[0] = 0x10
5018 19:22:58.196450 EX_ROW_EN[1] = 0x0
5019 19:22:58.197020 LP4Y_EN = 0x0
5020 19:22:58.199705 WORK_FSP = 0x0
5021 19:22:58.200241 WL = 0x3
5022 19:22:58.203275 RL = 0x3
5023 19:22:58.203693 BL = 0x2
5024 19:22:58.206264 RPST = 0x0
5025 19:22:58.206752 RD_PRE = 0x0
5026 19:22:58.209906 WR_PRE = 0x1
5027 19:22:58.210304 WR_PST = 0x0
5028 19:22:58.212929 DBI_WR = 0x0
5029 19:22:58.213305 DBI_RD = 0x0
5030 19:22:58.216011 OTF = 0x1
5031 19:22:58.219600 ===================================
5032 19:22:58.226190 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5033 19:22:58.229304 nWR fixed to 30
5034 19:22:58.229935 [ModeRegInit_LP4] CH0 RK0
5035 19:22:58.233059 [ModeRegInit_LP4] CH0 RK1
5036 19:22:58.236314 [ModeRegInit_LP4] CH1 RK0
5037 19:22:58.239440 [ModeRegInit_LP4] CH1 RK1
5038 19:22:58.239996 match AC timing 9
5039 19:22:58.246077 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5040 19:22:58.249548 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5041 19:22:58.252933 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5042 19:22:58.259367 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5043 19:22:58.262345 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5044 19:22:58.262447 ==
5045 19:22:58.265370 Dram Type= 6, Freq= 0, CH_0, rank 0
5046 19:22:58.268911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5047 19:22:58.269021 ==
5048 19:22:58.275555 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5049 19:22:58.282074 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5050 19:22:58.285517 [CA 0] Center 38 (8~69) winsize 62
5051 19:22:58.289167 [CA 1] Center 38 (7~69) winsize 63
5052 19:22:58.292346 [CA 2] Center 35 (5~66) winsize 62
5053 19:22:58.295371 [CA 3] Center 35 (5~65) winsize 61
5054 19:22:58.298956 [CA 4] Center 34 (3~65) winsize 63
5055 19:22:58.302368 [CA 5] Center 33 (3~64) winsize 62
5056 19:22:58.302476
5057 19:22:58.305768 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5058 19:22:58.305876
5059 19:22:58.308417 [CATrainingPosCal] consider 1 rank data
5060 19:22:58.311911 u2DelayCellTimex100 = 270/100 ps
5061 19:22:58.315557 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5062 19:22:58.319071 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5063 19:22:58.322207 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5064 19:22:58.325115 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5065 19:22:58.328743 CA4 delay=34 (3~65),Diff = 1 PI (6 cell)
5066 19:22:58.331855 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5067 19:22:58.331962
5068 19:22:58.338846 CA PerBit enable=1, Macro0, CA PI delay=33
5069 19:22:58.338947
5070 19:22:58.341963 [CBTSetCACLKResult] CA Dly = 33
5071 19:22:58.342043 CS Dly: 7 (0~38)
5072 19:22:58.342114 ==
5073 19:22:58.345407 Dram Type= 6, Freq= 0, CH_0, rank 1
5074 19:22:58.349005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5075 19:22:58.349112 ==
5076 19:22:58.355507 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5077 19:22:58.362133 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5078 19:22:58.365110 [CA 0] Center 38 (8~69) winsize 62
5079 19:22:58.368565 [CA 1] Center 38 (8~69) winsize 62
5080 19:22:58.372081 [CA 2] Center 35 (5~66) winsize 62
5081 19:22:58.375148 [CA 3] Center 35 (5~66) winsize 62
5082 19:22:58.378779 [CA 4] Center 34 (4~65) winsize 62
5083 19:22:58.381640 [CA 5] Center 33 (3~64) winsize 62
5084 19:22:58.381716
5085 19:22:58.384862 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5086 19:22:58.384938
5087 19:22:58.388344 [CATrainingPosCal] consider 2 rank data
5088 19:22:58.391873 u2DelayCellTimex100 = 270/100 ps
5089 19:22:58.394761 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5090 19:22:58.398469 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5091 19:22:58.401921 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5092 19:22:58.404894 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5093 19:22:58.408551 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5094 19:22:58.415011 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5095 19:22:58.415113
5096 19:22:58.418420 CA PerBit enable=1, Macro0, CA PI delay=33
5097 19:22:58.418494
5098 19:22:58.421249 [CBTSetCACLKResult] CA Dly = 33
5099 19:22:58.421356 CS Dly: 7 (0~38)
5100 19:22:58.421446
5101 19:22:58.424387 ----->DramcWriteLeveling(PI) begin...
5102 19:22:58.424500 ==
5103 19:22:58.427977 Dram Type= 6, Freq= 0, CH_0, rank 0
5104 19:22:58.434838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5105 19:22:58.434939 ==
5106 19:22:58.437975 Write leveling (Byte 0): 32 => 32
5107 19:22:58.438060 Write leveling (Byte 1): 30 => 30
5108 19:22:58.441276 DramcWriteLeveling(PI) end<-----
5109 19:22:58.441383
5110 19:22:58.444519 ==
5111 19:22:58.447672 Dram Type= 6, Freq= 0, CH_0, rank 0
5112 19:22:58.450950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5113 19:22:58.451032 ==
5114 19:22:58.454305 [Gating] SW mode calibration
5115 19:22:58.461038 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5116 19:22:58.464042 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5117 19:22:58.471044 0 14 0 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
5118 19:22:58.474277 0 14 4 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
5119 19:22:58.477891 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5120 19:22:58.484375 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5121 19:22:58.487395 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5122 19:22:58.491010 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5123 19:22:58.497479 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5124 19:22:58.500609 0 14 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5125 19:22:58.504136 0 15 0 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
5126 19:22:58.510928 0 15 4 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
5127 19:22:58.514382 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5128 19:22:58.517478 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5129 19:22:58.524080 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5130 19:22:58.527518 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5131 19:22:58.530891 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5132 19:22:58.537387 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5133 19:22:58.540673 1 0 0 | B1->B0 | 2424 3939 | 0 1 | (1 1) (0 0)
5134 19:22:58.543746 1 0 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5135 19:22:58.550466 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5136 19:22:58.553778 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5137 19:22:58.557076 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5138 19:22:58.563434 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5139 19:22:58.566784 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5140 19:22:58.570316 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5141 19:22:58.576951 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5142 19:22:58.580333 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5143 19:22:58.583561 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 19:22:58.587020 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 19:22:58.594067 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 19:22:58.596845 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 19:22:58.600282 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 19:22:58.606970 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 19:22:58.610572 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 19:22:58.613650 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 19:22:58.620029 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 19:22:58.623752 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 19:22:58.626724 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 19:22:58.633306 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 19:22:58.636943 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 19:22:58.639987 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5157 19:22:58.646611 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5158 19:22:58.646714 Total UI for P1: 0, mck2ui 16
5159 19:22:58.653179 best dqsien dly found for B0: ( 1, 2, 28)
5160 19:22:58.656699 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5161 19:22:58.660086 Total UI for P1: 0, mck2ui 16
5162 19:22:58.663134 best dqsien dly found for B1: ( 1, 3, 0)
5163 19:22:58.666731 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5164 19:22:58.669938 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5165 19:22:58.670053
5166 19:22:58.673048 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5167 19:22:58.676676 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5168 19:22:58.680040 [Gating] SW calibration Done
5169 19:22:58.680139 ==
5170 19:22:58.683035 Dram Type= 6, Freq= 0, CH_0, rank 0
5171 19:22:58.686247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5172 19:22:58.689883 ==
5173 19:22:58.689981 RX Vref Scan: 0
5174 19:22:58.690072
5175 19:22:58.693205 RX Vref 0 -> 0, step: 1
5176 19:22:58.693302
5177 19:22:58.693393 RX Delay -80 -> 252, step: 8
5178 19:22:58.699961 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5179 19:22:58.703526 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5180 19:22:58.706576 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5181 19:22:58.710109 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5182 19:22:58.713205 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5183 19:22:58.716277 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5184 19:22:58.722920 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5185 19:22:58.726672 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5186 19:22:58.730257 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5187 19:22:58.733199 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5188 19:22:58.736288 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5189 19:22:58.743277 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5190 19:22:58.746584 iDelay=208, Bit 12, Center 87 (-16 ~ 191) 208
5191 19:22:58.749876 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5192 19:22:58.752891 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5193 19:22:58.756081 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5194 19:22:58.759787 ==
5195 19:22:58.763191 Dram Type= 6, Freq= 0, CH_0, rank 0
5196 19:22:58.766113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5197 19:22:58.766257 ==
5198 19:22:58.766338 DQS Delay:
5199 19:22:58.769805 DQS0 = 0, DQS1 = 0
5200 19:22:58.769908 DQM Delay:
5201 19:22:58.772853 DQM0 = 95, DQM1 = 83
5202 19:22:58.772946 DQ Delay:
5203 19:22:58.775978 DQ0 =95, DQ1 =95, DQ2 =95, DQ3 =91
5204 19:22:58.779663 DQ4 =95, DQ5 =79, DQ6 =103, DQ7 =107
5205 19:22:58.783260 DQ8 =79, DQ9 =71, DQ10 =83, DQ11 =75
5206 19:22:58.785976 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =91
5207 19:22:58.786082
5208 19:22:58.786178
5209 19:22:58.786265 ==
5210 19:22:58.789598 Dram Type= 6, Freq= 0, CH_0, rank 0
5211 19:22:58.793147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5212 19:22:58.793255 ==
5213 19:22:58.793344
5214 19:22:58.793433
5215 19:22:58.796210 TX Vref Scan disable
5216 19:22:58.799269 == TX Byte 0 ==
5217 19:22:58.802863 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5218 19:22:58.805768 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5219 19:22:58.809292 == TX Byte 1 ==
5220 19:22:58.812746 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5221 19:22:58.816000 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5222 19:22:58.816100 ==
5223 19:22:58.819523 Dram Type= 6, Freq= 0, CH_0, rank 0
5224 19:22:58.825841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5225 19:22:58.825948 ==
5226 19:22:58.826038
5227 19:22:58.826124
5228 19:22:58.826220 TX Vref Scan disable
5229 19:22:58.830147 == TX Byte 0 ==
5230 19:22:58.833141 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5231 19:22:58.839833 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5232 19:22:58.839935 == TX Byte 1 ==
5233 19:22:58.842750 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5234 19:22:58.849676 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5235 19:22:58.849784
5236 19:22:58.849876 [DATLAT]
5237 19:22:58.849976 Freq=933, CH0 RK0
5238 19:22:58.850065
5239 19:22:58.852804 DATLAT Default: 0xd
5240 19:22:58.852901 0, 0xFFFF, sum = 0
5241 19:22:58.856210 1, 0xFFFF, sum = 0
5242 19:22:58.859337 2, 0xFFFF, sum = 0
5243 19:22:58.859443 3, 0xFFFF, sum = 0
5244 19:22:58.862945 4, 0xFFFF, sum = 0
5245 19:22:58.863058 5, 0xFFFF, sum = 0
5246 19:22:58.866013 6, 0xFFFF, sum = 0
5247 19:22:58.866120 7, 0xFFFF, sum = 0
5248 19:22:58.869280 8, 0xFFFF, sum = 0
5249 19:22:58.869388 9, 0xFFFF, sum = 0
5250 19:22:58.872441 10, 0x0, sum = 1
5251 19:22:58.872549 11, 0x0, sum = 2
5252 19:22:58.875944 12, 0x0, sum = 3
5253 19:22:58.876046 13, 0x0, sum = 4
5254 19:22:58.876139 best_step = 11
5255 19:22:58.876237
5256 19:22:58.879719 ==
5257 19:22:58.882738 Dram Type= 6, Freq= 0, CH_0, rank 0
5258 19:22:58.886453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5259 19:22:58.886560 ==
5260 19:22:58.886657 RX Vref Scan: 1
5261 19:22:58.886744
5262 19:22:58.889462 RX Vref 0 -> 0, step: 1
5263 19:22:58.889562
5264 19:22:58.892473 RX Delay -69 -> 252, step: 4
5265 19:22:58.892567
5266 19:22:58.895899 Set Vref, RX VrefLevel [Byte0]: 62
5267 19:22:58.899081 [Byte1]: 52
5268 19:22:58.899164
5269 19:22:58.902381 Final RX Vref Byte 0 = 62 to rank0
5270 19:22:58.905846 Final RX Vref Byte 1 = 52 to rank0
5271 19:22:58.909446 Final RX Vref Byte 0 = 62 to rank1
5272 19:22:58.912531 Final RX Vref Byte 1 = 52 to rank1==
5273 19:22:58.916050 Dram Type= 6, Freq= 0, CH_0, rank 0
5274 19:22:58.919169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5275 19:22:58.922195 ==
5276 19:22:58.922301 DQS Delay:
5277 19:22:58.922403 DQS0 = 0, DQS1 = 0
5278 19:22:58.925739 DQM Delay:
5279 19:22:58.925848 DQM0 = 95, DQM1 = 83
5280 19:22:58.929020 DQ Delay:
5281 19:22:58.932448 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =92
5282 19:22:58.935440 DQ4 =94, DQ5 =84, DQ6 =102, DQ7 =106
5283 19:22:58.938749 DQ8 =78, DQ9 =70, DQ10 =82, DQ11 =78
5284 19:22:58.942365 DQ12 =86, DQ13 =86, DQ14 =96, DQ15 =90
5285 19:22:58.942480
5286 19:22:58.942581
5287 19:22:58.949056 [DQSOSCAuto] RK0, (LSB)MR18= 0x1615, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 414 ps
5288 19:22:58.952012 CH0 RK0: MR19=505, MR18=1615
5289 19:22:58.958692 CH0_RK0: MR19=0x505, MR18=0x1615, DQSOSC=414, MR23=63, INC=63, DEC=42
5290 19:22:58.958776
5291 19:22:58.962347 ----->DramcWriteLeveling(PI) begin...
5292 19:22:58.962432 ==
5293 19:22:58.965567 Dram Type= 6, Freq= 0, CH_0, rank 1
5294 19:22:58.969022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5295 19:22:58.969109 ==
5296 19:22:58.972101 Write leveling (Byte 0): 32 => 32
5297 19:22:58.975639 Write leveling (Byte 1): 31 => 31
5298 19:22:58.978587 DramcWriteLeveling(PI) end<-----
5299 19:22:58.978669
5300 19:22:58.978734 ==
5301 19:22:58.982185 Dram Type= 6, Freq= 0, CH_0, rank 1
5302 19:22:58.985715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5303 19:22:58.985824 ==
5304 19:22:58.988709 [Gating] SW mode calibration
5305 19:22:58.995437 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5306 19:22:59.001863 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5307 19:22:59.005388 0 14 0 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
5308 19:22:59.011932 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5309 19:22:59.015363 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5310 19:22:59.018564 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5311 19:22:59.025097 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5312 19:22:59.028645 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5313 19:22:59.031467 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5314 19:22:59.035221 0 14 28 | B1->B0 | 3434 2d2d | 0 0 | (0 0) (0 1)
5315 19:22:59.041758 0 15 0 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0)
5316 19:22:59.045259 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5317 19:22:59.048245 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5318 19:22:59.054840 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5319 19:22:59.058225 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5320 19:22:59.062028 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5321 19:22:59.068652 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5322 19:22:59.071574 0 15 28 | B1->B0 | 2727 3b3b | 0 1 | (0 0) (0 0)
5323 19:22:59.074890 1 0 0 | B1->B0 | 3838 4646 | 1 0 | (0 0) (0 0)
5324 19:22:59.081639 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5325 19:22:59.084980 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5326 19:22:59.088536 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5327 19:22:59.095241 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5328 19:22:59.098202 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5329 19:22:59.101810 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5330 19:22:59.107834 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5331 19:22:59.111235 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5332 19:22:59.114818 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 19:22:59.121077 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 19:22:59.124556 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 19:22:59.128435 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 19:22:59.135108 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 19:22:59.138064 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 19:22:59.141185 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 19:22:59.147776 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 19:22:59.151311 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 19:22:59.154194 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 19:22:59.160956 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 19:22:59.164158 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 19:22:59.167542 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 19:22:59.174416 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5346 19:22:59.177485 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5347 19:22:59.181169 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5348 19:22:59.183971 Total UI for P1: 0, mck2ui 16
5349 19:22:59.187435 best dqsien dly found for B0: ( 1, 2, 26)
5350 19:22:59.193937 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5351 19:22:59.194027 Total UI for P1: 0, mck2ui 16
5352 19:22:59.200529 best dqsien dly found for B1: ( 1, 3, 0)
5353 19:22:59.204233 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5354 19:22:59.207313 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5355 19:22:59.207394
5356 19:22:59.210265 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5357 19:22:59.213885 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5358 19:22:59.217386 [Gating] SW calibration Done
5359 19:22:59.217491 ==
5360 19:22:59.220748 Dram Type= 6, Freq= 0, CH_0, rank 1
5361 19:22:59.224234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5362 19:22:59.224315 ==
5363 19:22:59.227244 RX Vref Scan: 0
5364 19:22:59.227324
5365 19:22:59.227387 RX Vref 0 -> 0, step: 1
5366 19:22:59.227446
5367 19:22:59.230734 RX Delay -80 -> 252, step: 8
5368 19:22:59.234052 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5369 19:22:59.240230 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5370 19:22:59.243583 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5371 19:22:59.247068 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5372 19:22:59.250210 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5373 19:22:59.253224 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5374 19:22:59.256788 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5375 19:22:59.263265 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5376 19:22:59.266849 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5377 19:22:59.270362 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5378 19:22:59.273074 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5379 19:22:59.276308 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5380 19:22:59.283244 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5381 19:22:59.286572 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5382 19:22:59.289925 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5383 19:22:59.293327 iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192
5384 19:22:59.293433 ==
5385 19:22:59.296696 Dram Type= 6, Freq= 0, CH_0, rank 1
5386 19:22:59.303207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5387 19:22:59.303289 ==
5388 19:22:59.303352 DQS Delay:
5389 19:22:59.306172 DQS0 = 0, DQS1 = 0
5390 19:22:59.306252 DQM Delay:
5391 19:22:59.306315 DQM0 = 91, DQM1 = 83
5392 19:22:59.309892 DQ Delay:
5393 19:22:59.312846 DQ0 =91, DQ1 =91, DQ2 =87, DQ3 =87
5394 19:22:59.316426 DQ4 =91, DQ5 =79, DQ6 =99, DQ7 =107
5395 19:22:59.319367 DQ8 =75, DQ9 =67, DQ10 =87, DQ11 =79
5396 19:22:59.322921 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =87
5397 19:22:59.323002
5398 19:22:59.323065
5399 19:22:59.323124 ==
5400 19:22:59.326331 Dram Type= 6, Freq= 0, CH_0, rank 1
5401 19:22:59.329669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5402 19:22:59.329750 ==
5403 19:22:59.329812
5404 19:22:59.329871
5405 19:22:59.333168 TX Vref Scan disable
5406 19:22:59.333248 == TX Byte 0 ==
5407 19:22:59.339046 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5408 19:22:59.342668 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5409 19:22:59.346175 == TX Byte 1 ==
5410 19:22:59.349323 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5411 19:22:59.352697 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5412 19:22:59.352778 ==
5413 19:22:59.356316 Dram Type= 6, Freq= 0, CH_0, rank 1
5414 19:22:59.359224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5415 19:22:59.362733 ==
5416 19:22:59.362813
5417 19:22:59.362876
5418 19:22:59.362934 TX Vref Scan disable
5419 19:22:59.365825 == TX Byte 0 ==
5420 19:22:59.369388 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5421 19:22:59.376026 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5422 19:22:59.376106 == TX Byte 1 ==
5423 19:22:59.379041 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5424 19:22:59.385723 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5425 19:22:59.385803
5426 19:22:59.385867 [DATLAT]
5427 19:22:59.385927 Freq=933, CH0 RK1
5428 19:22:59.385984
5429 19:22:59.389084 DATLAT Default: 0xb
5430 19:22:59.389164 0, 0xFFFF, sum = 0
5431 19:22:59.392342 1, 0xFFFF, sum = 0
5432 19:22:59.395675 2, 0xFFFF, sum = 0
5433 19:22:59.395759 3, 0xFFFF, sum = 0
5434 19:22:59.398877 4, 0xFFFF, sum = 0
5435 19:22:59.398959 5, 0xFFFF, sum = 0
5436 19:22:59.402689 6, 0xFFFF, sum = 0
5437 19:22:59.402818 7, 0xFFFF, sum = 0
5438 19:22:59.405419 8, 0xFFFF, sum = 0
5439 19:22:59.405550 9, 0xFFFF, sum = 0
5440 19:22:59.408625 10, 0x0, sum = 1
5441 19:22:59.408736 11, 0x0, sum = 2
5442 19:22:59.412286 12, 0x0, sum = 3
5443 19:22:59.412410 13, 0x0, sum = 4
5444 19:22:59.412504 best_step = 11
5445 19:22:59.415424
5446 19:22:59.415535 ==
5447 19:22:59.419117 Dram Type= 6, Freq= 0, CH_0, rank 1
5448 19:22:59.422271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5449 19:22:59.422383 ==
5450 19:22:59.422511 RX Vref Scan: 0
5451 19:22:59.422577
5452 19:22:59.425418 RX Vref 0 -> 0, step: 1
5453 19:22:59.425553
5454 19:22:59.428906 RX Delay -77 -> 252, step: 4
5455 19:22:59.435084 iDelay=199, Bit 0, Center 88 (-5 ~ 182) 188
5456 19:22:59.438562 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5457 19:22:59.442255 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5458 19:22:59.445179 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5459 19:22:59.448865 iDelay=199, Bit 4, Center 90 (-5 ~ 186) 192
5460 19:22:59.451975 iDelay=199, Bit 5, Center 80 (-13 ~ 174) 188
5461 19:22:59.458707 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5462 19:22:59.461667 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5463 19:22:59.465442 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5464 19:22:59.468425 iDelay=199, Bit 9, Center 68 (-21 ~ 158) 180
5465 19:22:59.471588 iDelay=199, Bit 10, Center 84 (-9 ~ 178) 188
5466 19:22:59.478470 iDelay=199, Bit 11, Center 76 (-13 ~ 166) 180
5467 19:22:59.481417 iDelay=199, Bit 12, Center 92 (-1 ~ 186) 188
5468 19:22:59.485181 iDelay=199, Bit 13, Center 92 (-1 ~ 186) 188
5469 19:22:59.488073 iDelay=199, Bit 14, Center 92 (-1 ~ 186) 188
5470 19:22:59.491643 iDelay=199, Bit 15, Center 92 (-1 ~ 186) 188
5471 19:22:59.494607 ==
5472 19:22:59.498168 Dram Type= 6, Freq= 0, CH_0, rank 1
5473 19:22:59.501211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5474 19:22:59.501312 ==
5475 19:22:59.501405 DQS Delay:
5476 19:22:59.504748 DQS0 = 0, DQS1 = 0
5477 19:22:59.504844 DQM Delay:
5478 19:22:59.508299 DQM0 = 92, DQM1 = 84
5479 19:22:59.508400 DQ Delay:
5480 19:22:59.511269 DQ0 =88, DQ1 =94, DQ2 =88, DQ3 =88
5481 19:22:59.514573 DQ4 =90, DQ5 =80, DQ6 =104, DQ7 =104
5482 19:22:59.517777 DQ8 =76, DQ9 =68, DQ10 =84, DQ11 =76
5483 19:22:59.521501 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
5484 19:22:59.521610
5485 19:22:59.521702
5486 19:22:59.527930 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e10, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 407 ps
5487 19:22:59.531103 CH0 RK1: MR19=505, MR18=2E10
5488 19:22:59.537759 CH0_RK1: MR19=0x505, MR18=0x2E10, DQSOSC=407, MR23=63, INC=65, DEC=43
5489 19:22:59.541212 [RxdqsGatingPostProcess] freq 933
5490 19:22:59.547704 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5491 19:22:59.547810 best DQS0 dly(2T, 0.5T) = (0, 10)
5492 19:22:59.551301 best DQS1 dly(2T, 0.5T) = (0, 11)
5493 19:22:59.554782 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5494 19:22:59.557909 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5495 19:22:59.560831 best DQS0 dly(2T, 0.5T) = (0, 10)
5496 19:22:59.564329 best DQS1 dly(2T, 0.5T) = (0, 11)
5497 19:22:59.567610 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5498 19:22:59.571161 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5499 19:22:59.574073 Pre-setting of DQS Precalculation
5500 19:22:59.580916 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5501 19:22:59.581022 ==
5502 19:22:59.584497 Dram Type= 6, Freq= 0, CH_1, rank 0
5503 19:22:59.587595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5504 19:22:59.587688 ==
5505 19:22:59.594242 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5506 19:22:59.597353 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5507 19:22:59.601331 [CA 0] Center 37 (7~67) winsize 61
5508 19:22:59.605038 [CA 1] Center 37 (7~68) winsize 62
5509 19:22:59.607955 [CA 2] Center 34 (5~64) winsize 60
5510 19:22:59.611444 [CA 3] Center 34 (5~64) winsize 60
5511 19:22:59.615013 [CA 4] Center 35 (5~65) winsize 61
5512 19:22:59.618074 [CA 5] Center 34 (4~64) winsize 61
5513 19:22:59.618156
5514 19:22:59.621789 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5515 19:22:59.621872
5516 19:22:59.624470 [CATrainingPosCal] consider 1 rank data
5517 19:22:59.627790 u2DelayCellTimex100 = 270/100 ps
5518 19:22:59.631186 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5519 19:22:59.638442 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5520 19:22:59.641585 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5521 19:22:59.644354 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5522 19:22:59.647710 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5523 19:22:59.651421 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5524 19:22:59.651534
5525 19:22:59.654776 CA PerBit enable=1, Macro0, CA PI delay=34
5526 19:22:59.654883
5527 19:22:59.657736 [CBTSetCACLKResult] CA Dly = 34
5528 19:22:59.657829 CS Dly: 6 (0~37)
5529 19:22:59.661249 ==
5530 19:22:59.664268 Dram Type= 6, Freq= 0, CH_1, rank 1
5531 19:22:59.667723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5532 19:22:59.667852 ==
5533 19:22:59.671235 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5534 19:22:59.677376 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5535 19:22:59.681859 [CA 0] Center 38 (8~68) winsize 61
5536 19:22:59.684850 [CA 1] Center 37 (7~68) winsize 62
5537 19:22:59.687821 [CA 2] Center 35 (5~65) winsize 61
5538 19:22:59.691413 [CA 3] Center 34 (4~64) winsize 61
5539 19:22:59.694488 [CA 4] Center 35 (5~65) winsize 61
5540 19:22:59.698174 [CA 5] Center 34 (4~64) winsize 61
5541 19:22:59.698317
5542 19:22:59.701079 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5543 19:22:59.701177
5544 19:22:59.704700 [CATrainingPosCal] consider 2 rank data
5545 19:22:59.708417 u2DelayCellTimex100 = 270/100 ps
5546 19:22:59.711408 CA0 delay=37 (8~67),Diff = 3 PI (18 cell)
5547 19:22:59.718033 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5548 19:22:59.721109 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5549 19:22:59.724586 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5550 19:22:59.727668 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5551 19:22:59.731310 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5552 19:22:59.731413
5553 19:22:59.734608 CA PerBit enable=1, Macro0, CA PI delay=34
5554 19:22:59.734716
5555 19:22:59.737955 [CBTSetCACLKResult] CA Dly = 34
5556 19:22:59.738056 CS Dly: 7 (0~39)
5557 19:22:59.740865
5558 19:22:59.744528 ----->DramcWriteLeveling(PI) begin...
5559 19:22:59.744636 ==
5560 19:22:59.747649 Dram Type= 6, Freq= 0, CH_1, rank 0
5561 19:22:59.750948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5562 19:22:59.751056 ==
5563 19:22:59.754382 Write leveling (Byte 0): 26 => 26
5564 19:22:59.757633 Write leveling (Byte 1): 27 => 27
5565 19:22:59.761375 DramcWriteLeveling(PI) end<-----
5566 19:22:59.761480
5567 19:22:59.761582 ==
5568 19:22:59.764247 Dram Type= 6, Freq= 0, CH_1, rank 0
5569 19:22:59.767511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5570 19:22:59.767616 ==
5571 19:22:59.771270 [Gating] SW mode calibration
5572 19:22:59.777458 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5573 19:22:59.784482 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5574 19:22:59.787413 0 14 0 | B1->B0 | 3333 3131 | 1 0 | (1 1) (0 0)
5575 19:22:59.790675 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5576 19:22:59.797348 0 14 8 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
5577 19:22:59.800981 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5578 19:22:59.803950 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5579 19:22:59.811060 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5580 19:22:59.814048 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5581 19:22:59.817562 0 14 28 | B1->B0 | 2f2f 2f2f | 1 1 | (1 0) (0 1)
5582 19:22:59.824240 0 15 0 | B1->B0 | 2424 2525 | 1 0 | (1 0) (1 0)
5583 19:22:59.827768 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5584 19:22:59.830784 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5585 19:22:59.834371 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5586 19:22:59.840980 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5587 19:22:59.843876 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5588 19:22:59.847609 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5589 19:22:59.854107 0 15 28 | B1->B0 | 3232 3635 | 1 1 | (1 1) (0 0)
5590 19:22:59.857142 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5591 19:22:59.860817 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5592 19:22:59.867759 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5593 19:22:59.870557 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5594 19:22:59.873875 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5595 19:22:59.880755 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5596 19:22:59.884037 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5597 19:22:59.887179 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5598 19:22:59.893849 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5599 19:22:59.897270 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 19:22:59.900619 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 19:22:59.907351 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 19:22:59.910792 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 19:22:59.913874 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 19:22:59.920555 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 19:22:59.923868 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 19:22:59.927556 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 19:22:59.934079 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 19:22:59.937124 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 19:22:59.940214 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 19:22:59.946778 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 19:22:59.950411 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 19:22:59.953876 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5613 19:22:59.960471 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5614 19:22:59.960554 Total UI for P1: 0, mck2ui 16
5615 19:22:59.963608 best dqsien dly found for B1: ( 1, 2, 24)
5616 19:22:59.970623 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5617 19:22:59.973408 Total UI for P1: 0, mck2ui 16
5618 19:22:59.976564 best dqsien dly found for B0: ( 1, 2, 28)
5619 19:22:59.980098 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5620 19:22:59.983025 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5621 19:22:59.983107
5622 19:22:59.986547 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5623 19:22:59.989847 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5624 19:22:59.993124 [Gating] SW calibration Done
5625 19:22:59.993208 ==
5626 19:22:59.996718 Dram Type= 6, Freq= 0, CH_1, rank 0
5627 19:22:59.999710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5628 19:23:00.002926 ==
5629 19:23:00.003008 RX Vref Scan: 0
5630 19:23:00.003074
5631 19:23:00.006086 RX Vref 0 -> 0, step: 1
5632 19:23:00.006168
5633 19:23:00.009423 RX Delay -80 -> 252, step: 8
5634 19:23:00.012984 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5635 19:23:00.015907 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5636 19:23:00.019375 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5637 19:23:00.022986 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5638 19:23:00.029279 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5639 19:23:00.032404 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5640 19:23:00.035987 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5641 19:23:00.039470 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5642 19:23:00.042460 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5643 19:23:00.046122 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5644 19:23:00.052759 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5645 19:23:00.055763 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5646 19:23:00.059431 iDelay=208, Bit 12, Center 95 (-8 ~ 199) 208
5647 19:23:00.062876 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5648 19:23:00.066147 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5649 19:23:00.072777 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5650 19:23:00.072858 ==
5651 19:23:00.075665 Dram Type= 6, Freq= 0, CH_1, rank 0
5652 19:23:00.079056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5653 19:23:00.079137 ==
5654 19:23:00.079201 DQS Delay:
5655 19:23:00.082697 DQS0 = 0, DQS1 = 0
5656 19:23:00.082777 DQM Delay:
5657 19:23:00.086066 DQM0 = 94, DQM1 = 86
5658 19:23:00.086146 DQ Delay:
5659 19:23:00.089153 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =87
5660 19:23:00.092062 DQ4 =91, DQ5 =103, DQ6 =107, DQ7 =91
5661 19:23:00.095666 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =83
5662 19:23:00.099120 DQ12 =95, DQ13 =91, DQ14 =91, DQ15 =91
5663 19:23:00.099200
5664 19:23:00.099264
5665 19:23:00.099322 ==
5666 19:23:00.101863 Dram Type= 6, Freq= 0, CH_1, rank 0
5667 19:23:00.105466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5668 19:23:00.108925 ==
5669 19:23:00.109005
5670 19:23:00.109068
5671 19:23:00.109161 TX Vref Scan disable
5672 19:23:00.111745 == TX Byte 0 ==
5673 19:23:00.115438 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5674 19:23:00.118985 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5675 19:23:00.122161 == TX Byte 1 ==
5676 19:23:00.125486 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5677 19:23:00.128600 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5678 19:23:00.131841 ==
5679 19:23:00.135496 Dram Type= 6, Freq= 0, CH_1, rank 0
5680 19:23:00.138803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5681 19:23:00.138906 ==
5682 19:23:00.139005
5683 19:23:00.139101
5684 19:23:00.141766 TX Vref Scan disable
5685 19:23:00.141860 == TX Byte 0 ==
5686 19:23:00.148354 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5687 19:23:00.151975 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5688 19:23:00.152078 == TX Byte 1 ==
5689 19:23:00.158450 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5690 19:23:00.162049 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5691 19:23:00.162149
5692 19:23:00.162248 [DATLAT]
5693 19:23:00.165063 Freq=933, CH1 RK0
5694 19:23:00.165161
5695 19:23:00.165256 DATLAT Default: 0xd
5696 19:23:00.168573 0, 0xFFFF, sum = 0
5697 19:23:00.168673 1, 0xFFFF, sum = 0
5698 19:23:00.171414 2, 0xFFFF, sum = 0
5699 19:23:00.171512 3, 0xFFFF, sum = 0
5700 19:23:00.175047 4, 0xFFFF, sum = 0
5701 19:23:00.175145 5, 0xFFFF, sum = 0
5702 19:23:00.178598 6, 0xFFFF, sum = 0
5703 19:23:00.181476 7, 0xFFFF, sum = 0
5704 19:23:00.181580 8, 0xFFFF, sum = 0
5705 19:23:00.184927 9, 0xFFFF, sum = 0
5706 19:23:00.185026 10, 0x0, sum = 1
5707 19:23:00.185126 11, 0x0, sum = 2
5708 19:23:00.188421 12, 0x0, sum = 3
5709 19:23:00.188531 13, 0x0, sum = 4
5710 19:23:00.191931 best_step = 11
5711 19:23:00.192027
5712 19:23:00.192123 ==
5713 19:23:00.194890 Dram Type= 6, Freq= 0, CH_1, rank 0
5714 19:23:00.198575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5715 19:23:00.198673 ==
5716 19:23:00.201490 RX Vref Scan: 1
5717 19:23:00.201591
5718 19:23:00.201674 RX Vref 0 -> 0, step: 1
5719 19:23:00.201752
5720 19:23:00.204983 RX Delay -69 -> 252, step: 4
5721 19:23:00.205077
5722 19:23:00.207954 Set Vref, RX VrefLevel [Byte0]: 59
5723 19:23:00.211422 [Byte1]: 47
5724 19:23:00.215669
5725 19:23:00.215767 Final RX Vref Byte 0 = 59 to rank0
5726 19:23:00.219263 Final RX Vref Byte 1 = 47 to rank0
5727 19:23:00.222183 Final RX Vref Byte 0 = 59 to rank1
5728 19:23:00.225558 Final RX Vref Byte 1 = 47 to rank1==
5729 19:23:00.229040 Dram Type= 6, Freq= 0, CH_1, rank 0
5730 19:23:00.235593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5731 19:23:00.235691 ==
5732 19:23:00.235790 DQS Delay:
5733 19:23:00.239250 DQS0 = 0, DQS1 = 0
5734 19:23:00.239355 DQM Delay:
5735 19:23:00.239443 DQM0 = 96, DQM1 = 88
5736 19:23:00.242266 DQ Delay:
5737 19:23:00.245776 DQ0 =102, DQ1 =92, DQ2 =84, DQ3 =92
5738 19:23:00.248825 DQ4 =94, DQ5 =108, DQ6 =106, DQ7 =94
5739 19:23:00.255633 DQ8 =72, DQ9 =80, DQ10 =88, DQ11 =82
5740 19:23:00.255744 DQ12 =96, DQ13 =94, DQ14 =98, DQ15 =94
5741 19:23:00.255842
5742 19:23:00.255933
5743 19:23:00.262282 [DQSOSCAuto] RK0, (LSB)MR18= 0x50d, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 420 ps
5744 19:23:00.265307 CH1 RK0: MR19=505, MR18=50D
5745 19:23:00.272031 CH1_RK0: MR19=0x505, MR18=0x50D, DQSOSC=417, MR23=63, INC=62, DEC=41
5746 19:23:00.272132
5747 19:23:00.275552 ----->DramcWriteLeveling(PI) begin...
5748 19:23:00.275654 ==
5749 19:23:00.278469 Dram Type= 6, Freq= 0, CH_1, rank 1
5750 19:23:00.281722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5751 19:23:00.281831 ==
5752 19:23:00.285085 Write leveling (Byte 0): 27 => 27
5753 19:23:00.288686 Write leveling (Byte 1): 28 => 28
5754 19:23:00.292116 DramcWriteLeveling(PI) end<-----
5755 19:23:00.292223
5756 19:23:00.292313 ==
5757 19:23:00.295489 Dram Type= 6, Freq= 0, CH_1, rank 1
5758 19:23:00.298185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5759 19:23:00.298285 ==
5760 19:23:00.301799 [Gating] SW mode calibration
5761 19:23:00.308440 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5762 19:23:00.314761 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5763 19:23:00.318356 0 14 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5764 19:23:00.324984 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5765 19:23:00.328390 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5766 19:23:00.331467 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5767 19:23:00.337979 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5768 19:23:00.341401 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5769 19:23:00.345088 0 14 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
5770 19:23:00.351419 0 14 28 | B1->B0 | 2525 2323 | 0 0 | (0 0) (1 0)
5771 19:23:00.354846 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5772 19:23:00.358103 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5773 19:23:00.364896 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5774 19:23:00.367980 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5775 19:23:00.371442 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5776 19:23:00.374917 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5777 19:23:00.381544 0 15 24 | B1->B0 | 2828 3a3a | 0 0 | (0 0) (0 0)
5778 19:23:00.384587 0 15 28 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
5779 19:23:00.388053 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5780 19:23:00.394773 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5781 19:23:00.397781 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5782 19:23:00.401298 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5783 19:23:00.407901 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5784 19:23:00.411045 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5785 19:23:00.414590 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5786 19:23:00.421123 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 19:23:00.424173 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 19:23:00.427833 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 19:23:00.434272 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 19:23:00.437882 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 19:23:00.440760 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 19:23:00.447466 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 19:23:00.451033 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 19:23:00.454495 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 19:23:00.461115 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 19:23:00.464137 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 19:23:00.467149 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 19:23:00.473856 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 19:23:00.477590 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 19:23:00.480841 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 19:23:00.487953 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5802 19:23:00.490799 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5803 19:23:00.493742 Total UI for P1: 0, mck2ui 16
5804 19:23:00.497498 best dqsien dly found for B0: ( 1, 2, 24)
5805 19:23:00.500835 Total UI for P1: 0, mck2ui 16
5806 19:23:00.503856 best dqsien dly found for B1: ( 1, 2, 26)
5807 19:23:00.507343 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5808 19:23:00.510707 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5809 19:23:00.510804
5810 19:23:00.513611 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5811 19:23:00.517122 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5812 19:23:00.520672 [Gating] SW calibration Done
5813 19:23:00.520770 ==
5814 19:23:00.523670 Dram Type= 6, Freq= 0, CH_1, rank 1
5815 19:23:00.527014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5816 19:23:00.530638 ==
5817 19:23:00.530735 RX Vref Scan: 0
5818 19:23:00.530830
5819 19:23:00.533648 RX Vref 0 -> 0, step: 1
5820 19:23:00.533743
5821 19:23:00.537130 RX Delay -80 -> 252, step: 8
5822 19:23:00.540159 iDelay=208, Bit 0, Center 95 (-8 ~ 199) 208
5823 19:23:00.543698 iDelay=208, Bit 1, Center 87 (-8 ~ 183) 192
5824 19:23:00.546773 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5825 19:23:00.550091 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5826 19:23:00.553503 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5827 19:23:00.560040 iDelay=208, Bit 5, Center 99 (0 ~ 199) 200
5828 19:23:00.563701 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5829 19:23:00.566624 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5830 19:23:00.570111 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5831 19:23:00.573818 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5832 19:23:00.580155 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5833 19:23:00.583501 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5834 19:23:00.586752 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5835 19:23:00.590156 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5836 19:23:00.593288 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5837 19:23:00.596886 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5838 19:23:00.599800 ==
5839 19:23:00.603225 Dram Type= 6, Freq= 0, CH_1, rank 1
5840 19:23:00.606358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5841 19:23:00.606455 ==
5842 19:23:00.606555 DQS Delay:
5843 19:23:00.609737 DQS0 = 0, DQS1 = 0
5844 19:23:00.609835 DQM Delay:
5845 19:23:00.613291 DQM0 = 93, DQM1 = 87
5846 19:23:00.613387 DQ Delay:
5847 19:23:00.616745 DQ0 =95, DQ1 =87, DQ2 =83, DQ3 =91
5848 19:23:00.620167 DQ4 =91, DQ5 =99, DQ6 =107, DQ7 =91
5849 19:23:00.623375 DQ8 =75, DQ9 =79, DQ10 =95, DQ11 =79
5850 19:23:00.626799 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =95
5851 19:23:00.626896
5852 19:23:00.626991
5853 19:23:00.627086 ==
5854 19:23:00.629957 Dram Type= 6, Freq= 0, CH_1, rank 1
5855 19:23:00.633355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5856 19:23:00.633452 ==
5857 19:23:00.633587
5858 19:23:00.633684
5859 19:23:00.636294 TX Vref Scan disable
5860 19:23:00.639809 == TX Byte 0 ==
5861 19:23:00.642835 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5862 19:23:00.646391 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5863 19:23:00.649929 == TX Byte 1 ==
5864 19:23:00.652831 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5865 19:23:00.656386 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5866 19:23:00.656486 ==
5867 19:23:00.659327 Dram Type= 6, Freq= 0, CH_1, rank 1
5868 19:23:00.666259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5869 19:23:00.666363 ==
5870 19:23:00.666462
5871 19:23:00.666558
5872 19:23:00.666653 TX Vref Scan disable
5873 19:23:00.670507 == TX Byte 0 ==
5874 19:23:00.673377 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5875 19:23:00.680208 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5876 19:23:00.680307 == TX Byte 1 ==
5877 19:23:00.683370 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5878 19:23:00.690363 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5879 19:23:00.690464
5880 19:23:00.690550 [DATLAT]
5881 19:23:00.690628 Freq=933, CH1 RK1
5882 19:23:00.690703
5883 19:23:00.693247 DATLAT Default: 0xb
5884 19:23:00.693344 0, 0xFFFF, sum = 0
5885 19:23:00.696599 1, 0xFFFF, sum = 0
5886 19:23:00.696696 2, 0xFFFF, sum = 0
5887 19:23:00.699958 3, 0xFFFF, sum = 0
5888 19:23:00.703418 4, 0xFFFF, sum = 0
5889 19:23:00.703518 5, 0xFFFF, sum = 0
5890 19:23:00.706364 6, 0xFFFF, sum = 0
5891 19:23:00.706472 7, 0xFFFF, sum = 0
5892 19:23:00.709925 8, 0xFFFF, sum = 0
5893 19:23:00.710024 9, 0xFFFF, sum = 0
5894 19:23:00.713272 10, 0x0, sum = 1
5895 19:23:00.713347 11, 0x0, sum = 2
5896 19:23:00.716705 12, 0x0, sum = 3
5897 19:23:00.716807 13, 0x0, sum = 4
5898 19:23:00.716905 best_step = 11
5899 19:23:00.719937
5900 19:23:00.720034 ==
5901 19:23:00.722892 Dram Type= 6, Freq= 0, CH_1, rank 1
5902 19:23:00.726277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5903 19:23:00.726350 ==
5904 19:23:00.726447 RX Vref Scan: 0
5905 19:23:00.726541
5906 19:23:00.729900 RX Vref 0 -> 0, step: 1
5907 19:23:00.729999
5908 19:23:00.732792 RX Delay -69 -> 252, step: 4
5909 19:23:00.739250 iDelay=203, Bit 0, Center 94 (-5 ~ 194) 200
5910 19:23:00.742741 iDelay=203, Bit 1, Center 86 (-9 ~ 182) 192
5911 19:23:00.746121 iDelay=203, Bit 2, Center 82 (-13 ~ 178) 192
5912 19:23:00.749501 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5913 19:23:00.752477 iDelay=203, Bit 4, Center 90 (-5 ~ 186) 192
5914 19:23:00.756085 iDelay=203, Bit 5, Center 100 (3 ~ 198) 196
5915 19:23:00.763020 iDelay=203, Bit 6, Center 106 (11 ~ 202) 192
5916 19:23:00.765791 iDelay=203, Bit 7, Center 90 (-5 ~ 186) 192
5917 19:23:00.769395 iDelay=203, Bit 8, Center 76 (-17 ~ 170) 188
5918 19:23:00.772928 iDelay=203, Bit 9, Center 80 (-13 ~ 174) 188
5919 19:23:00.775778 iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188
5920 19:23:00.782332 iDelay=203, Bit 11, Center 84 (-5 ~ 174) 180
5921 19:23:00.786002 iDelay=203, Bit 12, Center 100 (11 ~ 190) 180
5922 19:23:00.789680 iDelay=203, Bit 13, Center 100 (11 ~ 190) 180
5923 19:23:00.792260 iDelay=203, Bit 14, Center 98 (11 ~ 186) 176
5924 19:23:00.795676 iDelay=203, Bit 15, Center 98 (11 ~ 186) 176
5925 19:23:00.799249 ==
5926 19:23:00.802613 Dram Type= 6, Freq= 0, CH_1, rank 1
5927 19:23:00.805500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5928 19:23:00.805589 ==
5929 19:23:00.805651 DQS Delay:
5930 19:23:00.808940 DQS0 = 0, DQS1 = 0
5931 19:23:00.809020 DQM Delay:
5932 19:23:00.812621 DQM0 = 92, DQM1 = 91
5933 19:23:00.812693 DQ Delay:
5934 19:23:00.815723 DQ0 =94, DQ1 =86, DQ2 =82, DQ3 =88
5935 19:23:00.819145 DQ4 =90, DQ5 =100, DQ6 =106, DQ7 =90
5936 19:23:00.822469 DQ8 =76, DQ9 =80, DQ10 =92, DQ11 =84
5937 19:23:00.825460 DQ12 =100, DQ13 =100, DQ14 =98, DQ15 =98
5938 19:23:00.825593
5939 19:23:00.825690
5940 19:23:00.832379 [DQSOSCAuto] RK1, (LSB)MR18= 0xe23, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 417 ps
5941 19:23:00.835949 CH1 RK1: MR19=505, MR18=E23
5942 19:23:00.842512 CH1_RK1: MR19=0x505, MR18=0xE23, DQSOSC=410, MR23=63, INC=64, DEC=42
5943 19:23:00.845869 [RxdqsGatingPostProcess] freq 933
5944 19:23:00.852267 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5945 19:23:00.852346 best DQS0 dly(2T, 0.5T) = (0, 10)
5946 19:23:00.855283 best DQS1 dly(2T, 0.5T) = (0, 10)
5947 19:23:00.858804 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5948 19:23:00.862181 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5949 19:23:00.865690 best DQS0 dly(2T, 0.5T) = (0, 10)
5950 19:23:00.868770 best DQS1 dly(2T, 0.5T) = (0, 10)
5951 19:23:00.872165 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5952 19:23:00.875667 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5953 19:23:00.878433 Pre-setting of DQS Precalculation
5954 19:23:00.884984 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5955 19:23:00.891654 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5956 19:23:00.898396 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5957 19:23:00.898476
5958 19:23:00.898556
5959 19:23:00.901731 [Calibration Summary] 1866 Mbps
5960 19:23:00.901810 CH 0, Rank 0
5961 19:23:00.905240 SW Impedance : PASS
5962 19:23:00.908173 DUTY Scan : NO K
5963 19:23:00.908252 ZQ Calibration : PASS
5964 19:23:00.911554 Jitter Meter : NO K
5965 19:23:00.914772 CBT Training : PASS
5966 19:23:00.914851 Write leveling : PASS
5967 19:23:00.918490 RX DQS gating : PASS
5968 19:23:00.918570 RX DQ/DQS(RDDQC) : PASS
5969 19:23:00.922011 TX DQ/DQS : PASS
5970 19:23:00.924998 RX DATLAT : PASS
5971 19:23:00.925107 RX DQ/DQS(Engine): PASS
5972 19:23:00.928410 TX OE : NO K
5973 19:23:00.928490 All Pass.
5974 19:23:00.928571
5975 19:23:00.931674 CH 0, Rank 1
5976 19:23:00.931779 SW Impedance : PASS
5977 19:23:00.934963 DUTY Scan : NO K
5978 19:23:00.937968 ZQ Calibration : PASS
5979 19:23:00.938046 Jitter Meter : NO K
5980 19:23:00.941373 CBT Training : PASS
5981 19:23:00.944845 Write leveling : PASS
5982 19:23:00.944917 RX DQS gating : PASS
5983 19:23:00.947916 RX DQ/DQS(RDDQC) : PASS
5984 19:23:00.951717 TX DQ/DQS : PASS
5985 19:23:00.951800 RX DATLAT : PASS
5986 19:23:00.954925 RX DQ/DQS(Engine): PASS
5987 19:23:00.958394 TX OE : NO K
5988 19:23:00.958465 All Pass.
5989 19:23:00.958538
5990 19:23:00.958597 CH 1, Rank 0
5991 19:23:00.961318 SW Impedance : PASS
5992 19:23:00.964906 DUTY Scan : NO K
5993 19:23:00.964976 ZQ Calibration : PASS
5994 19:23:00.968341 Jitter Meter : NO K
5995 19:23:00.971242 CBT Training : PASS
5996 19:23:00.971336 Write leveling : PASS
5997 19:23:00.974658 RX DQS gating : PASS
5998 19:23:00.974731 RX DQ/DQS(RDDQC) : PASS
5999 19:23:00.978329 TX DQ/DQS : PASS
6000 19:23:00.981312 RX DATLAT : PASS
6001 19:23:00.981391 RX DQ/DQS(Engine): PASS
6002 19:23:00.984804 TX OE : NO K
6003 19:23:00.984884 All Pass.
6004 19:23:00.984946
6005 19:23:00.988316 CH 1, Rank 1
6006 19:23:00.988395 SW Impedance : PASS
6007 19:23:00.991327 DUTY Scan : NO K
6008 19:23:00.994948 ZQ Calibration : PASS
6009 19:23:00.995027 Jitter Meter : NO K
6010 19:23:00.997857 CBT Training : PASS
6011 19:23:01.001484 Write leveling : PASS
6012 19:23:01.001568 RX DQS gating : PASS
6013 19:23:01.004304 RX DQ/DQS(RDDQC) : PASS
6014 19:23:01.008144 TX DQ/DQS : PASS
6015 19:23:01.008225 RX DATLAT : PASS
6016 19:23:01.010935 RX DQ/DQS(Engine): PASS
6017 19:23:01.014530 TX OE : NO K
6018 19:23:01.014608 All Pass.
6019 19:23:01.014670
6020 19:23:01.014727 DramC Write-DBI off
6021 19:23:01.018008 PER_BANK_REFRESH: Hybrid Mode
6022 19:23:01.021384 TX_TRACKING: ON
6023 19:23:01.028093 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6024 19:23:01.031079 [FAST_K] Save calibration result to emmc
6025 19:23:01.037744 dramc_set_vcore_voltage set vcore to 650000
6026 19:23:01.037825 Read voltage for 400, 6
6027 19:23:01.041172 Vio18 = 0
6028 19:23:01.041271 Vcore = 650000
6029 19:23:01.041334 Vdram = 0
6030 19:23:01.044535 Vddq = 0
6031 19:23:01.044603 Vmddr = 0
6032 19:23:01.047754 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6033 19:23:01.054206 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6034 19:23:01.057687 MEM_TYPE=3, freq_sel=20
6035 19:23:01.057761 sv_algorithm_assistance_LP4_800
6036 19:23:01.064421 ============ PULL DRAM RESETB DOWN ============
6037 19:23:01.067603 ========== PULL DRAM RESETB DOWN end =========
6038 19:23:01.071039 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6039 19:23:01.074086 ===================================
6040 19:23:01.077488 LPDDR4 DRAM CONFIGURATION
6041 19:23:01.080624 ===================================
6042 19:23:01.084073 EX_ROW_EN[0] = 0x0
6043 19:23:01.084151 EX_ROW_EN[1] = 0x0
6044 19:23:01.087556 LP4Y_EN = 0x0
6045 19:23:01.087635 WORK_FSP = 0x0
6046 19:23:01.091001 WL = 0x2
6047 19:23:01.091079 RL = 0x2
6048 19:23:01.093949 BL = 0x2
6049 19:23:01.094028 RPST = 0x0
6050 19:23:01.097476 RD_PRE = 0x0
6051 19:23:01.097601 WR_PRE = 0x1
6052 19:23:01.100590 WR_PST = 0x0
6053 19:23:01.100669 DBI_WR = 0x0
6054 19:23:01.104218 DBI_RD = 0x0
6055 19:23:01.104296 OTF = 0x1
6056 19:23:01.107270 ===================================
6057 19:23:01.110814 ===================================
6058 19:23:01.114152 ANA top config
6059 19:23:01.117386 ===================================
6060 19:23:01.120591 DLL_ASYNC_EN = 0
6061 19:23:01.120670 ALL_SLAVE_EN = 1
6062 19:23:01.124010 NEW_RANK_MODE = 1
6063 19:23:01.127342 DLL_IDLE_MODE = 1
6064 19:23:01.130365 LP45_APHY_COMB_EN = 1
6065 19:23:01.133820 TX_ODT_DIS = 1
6066 19:23:01.133899 NEW_8X_MODE = 1
6067 19:23:01.137489 ===================================
6068 19:23:01.140585 ===================================
6069 19:23:01.143976 data_rate = 800
6070 19:23:01.147610 CKR = 1
6071 19:23:01.150512 DQ_P2S_RATIO = 4
6072 19:23:01.154115 ===================================
6073 19:23:01.157376 CA_P2S_RATIO = 4
6074 19:23:01.160320 DQ_CA_OPEN = 0
6075 19:23:01.160421 DQ_SEMI_OPEN = 1
6076 19:23:01.164239 CA_SEMI_OPEN = 1
6077 19:23:01.167182 CA_FULL_RATE = 0
6078 19:23:01.170581 DQ_CKDIV4_EN = 0
6079 19:23:01.173857 CA_CKDIV4_EN = 1
6080 19:23:01.177336 CA_PREDIV_EN = 0
6081 19:23:01.177415 PH8_DLY = 0
6082 19:23:01.180256 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6083 19:23:01.184024 DQ_AAMCK_DIV = 0
6084 19:23:01.186986 CA_AAMCK_DIV = 0
6085 19:23:01.190482 CA_ADMCK_DIV = 4
6086 19:23:01.190561 DQ_TRACK_CA_EN = 0
6087 19:23:01.193375 CA_PICK = 800
6088 19:23:01.196781 CA_MCKIO = 400
6089 19:23:01.200483 MCKIO_SEMI = 400
6090 19:23:01.203454 PLL_FREQ = 3016
6091 19:23:01.207070 DQ_UI_PI_RATIO = 32
6092 19:23:01.210151 CA_UI_PI_RATIO = 32
6093 19:23:01.213224 ===================================
6094 19:23:01.216596 ===================================
6095 19:23:01.220188 memory_type:LPDDR4
6096 19:23:01.220266 GP_NUM : 10
6097 19:23:01.223473 SRAM_EN : 1
6098 19:23:01.223551 MD32_EN : 0
6099 19:23:01.226736 ===================================
6100 19:23:01.229758 [ANA_INIT] >>>>>>>>>>>>>>
6101 19:23:01.233336 <<<<<< [CONFIGURE PHASE]: ANA_TX
6102 19:23:01.236615 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6103 19:23:01.240160 ===================================
6104 19:23:01.243152 data_rate = 800,PCW = 0X7400
6105 19:23:01.246728 ===================================
6106 19:23:01.250194 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6107 19:23:01.253096 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6108 19:23:01.266760 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6109 19:23:01.269890 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6110 19:23:01.272927 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6111 19:23:01.276205 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6112 19:23:01.279722 [ANA_INIT] flow start
6113 19:23:01.283087 [ANA_INIT] PLL >>>>>>>>
6114 19:23:01.283166 [ANA_INIT] PLL <<<<<<<<
6115 19:23:01.286457 [ANA_INIT] MIDPI >>>>>>>>
6116 19:23:01.289918 [ANA_INIT] MIDPI <<<<<<<<
6117 19:23:01.290023 [ANA_INIT] DLL >>>>>>>>
6118 19:23:01.292919 [ANA_INIT] flow end
6119 19:23:01.296372 ============ LP4 DIFF to SE enter ============
6120 19:23:01.303167 ============ LP4 DIFF to SE exit ============
6121 19:23:01.303247 [ANA_INIT] <<<<<<<<<<<<<
6122 19:23:01.306110 [Flow] Enable top DCM control >>>>>
6123 19:23:01.309761 [Flow] Enable top DCM control <<<<<
6124 19:23:01.312823 Enable DLL master slave shuffle
6125 19:23:01.319436 ==============================================================
6126 19:23:01.319515 Gating Mode config
6127 19:23:01.326007 ==============================================================
6128 19:23:01.329438 Config description:
6129 19:23:01.336162 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6130 19:23:01.342352 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6131 19:23:01.349142 SELPH_MODE 0: By rank 1: By Phase
6132 19:23:01.356066 ==============================================================
6133 19:23:01.359147 GAT_TRACK_EN = 0
6134 19:23:01.359229 RX_GATING_MODE = 2
6135 19:23:01.362746 RX_GATING_TRACK_MODE = 2
6136 19:23:01.365635 SELPH_MODE = 1
6137 19:23:01.368839 PICG_EARLY_EN = 1
6138 19:23:01.372324 VALID_LAT_VALUE = 1
6139 19:23:01.379000 ==============================================================
6140 19:23:01.382223 Enter into Gating configuration >>>>
6141 19:23:01.385822 Exit from Gating configuration <<<<
6142 19:23:01.389149 Enter into DVFS_PRE_config >>>>>
6143 19:23:01.398857 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6144 19:23:01.402184 Exit from DVFS_PRE_config <<<<<
6145 19:23:01.405465 Enter into PICG configuration >>>>
6146 19:23:01.408787 Exit from PICG configuration <<<<
6147 19:23:01.412581 [RX_INPUT] configuration >>>>>
6148 19:23:01.415539 [RX_INPUT] configuration <<<<<
6149 19:23:01.419135 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6150 19:23:01.425789 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6151 19:23:01.431943 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6152 19:23:01.435446 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6153 19:23:01.442340 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6154 19:23:01.448643 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6155 19:23:01.452021 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6156 19:23:01.458585 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6157 19:23:01.462059 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6158 19:23:01.465080 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6159 19:23:01.468662 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6160 19:23:01.475343 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6161 19:23:01.478341 ===================================
6162 19:23:01.478430 LPDDR4 DRAM CONFIGURATION
6163 19:23:01.481886 ===================================
6164 19:23:01.485174 EX_ROW_EN[0] = 0x0
6165 19:23:01.488465 EX_ROW_EN[1] = 0x0
6166 19:23:01.488545 LP4Y_EN = 0x0
6167 19:23:01.491912 WORK_FSP = 0x0
6168 19:23:01.491992 WL = 0x2
6169 19:23:01.494892 RL = 0x2
6170 19:23:01.494972 BL = 0x2
6171 19:23:01.498179 RPST = 0x0
6172 19:23:01.498259 RD_PRE = 0x0
6173 19:23:01.502037 WR_PRE = 0x1
6174 19:23:01.502117 WR_PST = 0x0
6175 19:23:01.504783 DBI_WR = 0x0
6176 19:23:01.504863 DBI_RD = 0x0
6177 19:23:01.508263 OTF = 0x1
6178 19:23:01.511636 ===================================
6179 19:23:01.515118 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6180 19:23:01.518396 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6181 19:23:01.524833 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6182 19:23:01.528520 ===================================
6183 19:23:01.528600 LPDDR4 DRAM CONFIGURATION
6184 19:23:01.531553 ===================================
6185 19:23:01.535127 EX_ROW_EN[0] = 0x10
6186 19:23:01.538028 EX_ROW_EN[1] = 0x0
6187 19:23:01.538107 LP4Y_EN = 0x0
6188 19:23:01.541126 WORK_FSP = 0x0
6189 19:23:01.541205 WL = 0x2
6190 19:23:01.544653 RL = 0x2
6191 19:23:01.544732 BL = 0x2
6192 19:23:01.548135 RPST = 0x0
6193 19:23:01.548215 RD_PRE = 0x0
6194 19:23:01.551546 WR_PRE = 0x1
6195 19:23:01.551626 WR_PST = 0x0
6196 19:23:01.554803 DBI_WR = 0x0
6197 19:23:01.554885 DBI_RD = 0x0
6198 19:23:01.558581 OTF = 0x1
6199 19:23:01.561387 ===================================
6200 19:23:01.567934 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6201 19:23:01.571301 nWR fixed to 30
6202 19:23:01.571385 [ModeRegInit_LP4] CH0 RK0
6203 19:23:01.574926 [ModeRegInit_LP4] CH0 RK1
6204 19:23:01.577892 [ModeRegInit_LP4] CH1 RK0
6205 19:23:01.577971 [ModeRegInit_LP4] CH1 RK1
6206 19:23:01.581403 match AC timing 19
6207 19:23:01.584923 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6208 19:23:01.587876 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6209 19:23:01.595114 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6210 19:23:01.597916 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6211 19:23:01.604712 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6212 19:23:01.604792 ==
6213 19:23:01.607976 Dram Type= 6, Freq= 0, CH_0, rank 0
6214 19:23:01.611279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6215 19:23:01.611361 ==
6216 19:23:01.618082 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6217 19:23:01.624330 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6218 19:23:01.627571 [CA 0] Center 36 (8~64) winsize 57
6219 19:23:01.627654 [CA 1] Center 36 (8~64) winsize 57
6220 19:23:01.630930 [CA 2] Center 36 (8~64) winsize 57
6221 19:23:01.634559 [CA 3] Center 36 (8~64) winsize 57
6222 19:23:01.637498 [CA 4] Center 36 (8~64) winsize 57
6223 19:23:01.641289 [CA 5] Center 36 (8~64) winsize 57
6224 19:23:01.641369
6225 19:23:01.644320 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6226 19:23:01.644401
6227 19:23:01.647327 [CATrainingPosCal] consider 1 rank data
6228 19:23:01.650789 u2DelayCellTimex100 = 270/100 ps
6229 19:23:01.654212 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6230 19:23:01.660773 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6231 19:23:01.664353 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6232 19:23:01.667317 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6233 19:23:01.670687 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6234 19:23:01.674136 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6235 19:23:01.674210
6236 19:23:01.677383 CA PerBit enable=1, Macro0, CA PI delay=36
6237 19:23:01.677479
6238 19:23:01.680887 [CBTSetCACLKResult] CA Dly = 36
6239 19:23:01.680967 CS Dly: 1 (0~32)
6240 19:23:01.683932 ==
6241 19:23:01.686875 Dram Type= 6, Freq= 0, CH_0, rank 1
6242 19:23:01.690563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6243 19:23:01.690645 ==
6244 19:23:01.697381 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6245 19:23:01.700162 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6246 19:23:01.703479 [CA 0] Center 36 (8~64) winsize 57
6247 19:23:01.707126 [CA 1] Center 36 (8~64) winsize 57
6248 19:23:01.710088 [CA 2] Center 36 (8~64) winsize 57
6249 19:23:01.713801 [CA 3] Center 36 (8~64) winsize 57
6250 19:23:01.716994 [CA 4] Center 36 (8~64) winsize 57
6251 19:23:01.720448 [CA 5] Center 36 (8~64) winsize 57
6252 19:23:01.720574
6253 19:23:01.723206 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6254 19:23:01.723326
6255 19:23:01.726913 [CATrainingPosCal] consider 2 rank data
6256 19:23:01.730171 u2DelayCellTimex100 = 270/100 ps
6257 19:23:01.733499 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6258 19:23:01.736753 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6259 19:23:01.740177 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6260 19:23:01.746639 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6261 19:23:01.750163 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6262 19:23:01.753239 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6263 19:23:01.753340
6264 19:23:01.756809 CA PerBit enable=1, Macro0, CA PI delay=36
6265 19:23:01.756893
6266 19:23:01.759666 [CBTSetCACLKResult] CA Dly = 36
6267 19:23:01.759738 CS Dly: 1 (0~32)
6268 19:23:01.759799
6269 19:23:01.763454 ----->DramcWriteLeveling(PI) begin...
6270 19:23:01.763546 ==
6271 19:23:01.766313 Dram Type= 6, Freq= 0, CH_0, rank 0
6272 19:23:01.773190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6273 19:23:01.773298 ==
6274 19:23:01.776256 Write leveling (Byte 0): 40 => 8
6275 19:23:01.779619 Write leveling (Byte 1): 40 => 8
6276 19:23:01.779700 DramcWriteLeveling(PI) end<-----
6277 19:23:01.783009
6278 19:23:01.783078 ==
6279 19:23:01.786485 Dram Type= 6, Freq= 0, CH_0, rank 0
6280 19:23:01.789359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6281 19:23:01.789456 ==
6282 19:23:01.792996 [Gating] SW mode calibration
6283 19:23:01.799620 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6284 19:23:01.802727 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6285 19:23:01.809372 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6286 19:23:01.812606 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6287 19:23:01.816063 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6288 19:23:01.823101 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6289 19:23:01.826061 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6290 19:23:01.829398 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6291 19:23:01.836197 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6292 19:23:01.839116 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6293 19:23:01.842627 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6294 19:23:01.846192 Total UI for P1: 0, mck2ui 16
6295 19:23:01.849081 best dqsien dly found for B0: ( 0, 14, 24)
6296 19:23:01.852438 Total UI for P1: 0, mck2ui 16
6297 19:23:01.856004 best dqsien dly found for B1: ( 0, 14, 24)
6298 19:23:01.859156 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6299 19:23:01.865457 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6300 19:23:01.865614
6301 19:23:01.869068 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6302 19:23:01.872508 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6303 19:23:01.875692 [Gating] SW calibration Done
6304 19:23:01.875859 ==
6305 19:23:01.879258 Dram Type= 6, Freq= 0, CH_0, rank 0
6306 19:23:01.882146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6307 19:23:01.882340 ==
6308 19:23:01.885495 RX Vref Scan: 0
6309 19:23:01.885759
6310 19:23:01.885942 RX Vref 0 -> 0, step: 1
6311 19:23:01.886111
6312 19:23:01.888989 RX Delay -410 -> 252, step: 16
6313 19:23:01.892372 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6314 19:23:01.898742 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6315 19:23:01.902334 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6316 19:23:01.905307 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6317 19:23:01.908965 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6318 19:23:01.915450 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6319 19:23:01.918560 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6320 19:23:01.921860 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6321 19:23:01.925395 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6322 19:23:01.932094 iDelay=230, Bit 9, Center -67 (-330 ~ 197) 528
6323 19:23:01.934941 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6324 19:23:01.938335 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6325 19:23:01.941790 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6326 19:23:01.948491 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6327 19:23:01.951830 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6328 19:23:01.955178 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6329 19:23:01.955253 ==
6330 19:23:01.958382 Dram Type= 6, Freq= 0, CH_0, rank 0
6331 19:23:01.964638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6332 19:23:01.964727 ==
6333 19:23:01.964788 DQS Delay:
6334 19:23:01.968217 DQS0 = 59, DQS1 = 67
6335 19:23:01.968284 DQM Delay:
6336 19:23:01.971550 DQM0 = 18, DQM1 = 16
6337 19:23:01.971620 DQ Delay:
6338 19:23:01.974612 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6339 19:23:01.978301 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6340 19:23:01.981271 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6341 19:23:01.985020 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6342 19:23:01.985092
6343 19:23:01.985151
6344 19:23:01.985213 ==
6345 19:23:01.987826 Dram Type= 6, Freq= 0, CH_0, rank 0
6346 19:23:01.991244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6347 19:23:01.991316 ==
6348 19:23:01.991375
6349 19:23:01.991431
6350 19:23:01.994940 TX Vref Scan disable
6351 19:23:01.995054 == TX Byte 0 ==
6352 19:23:02.001131 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6353 19:23:02.004732 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6354 19:23:02.004804 == TX Byte 1 ==
6355 19:23:02.011325 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6356 19:23:02.014323 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6357 19:23:02.014433 ==
6358 19:23:02.017808 Dram Type= 6, Freq= 0, CH_0, rank 0
6359 19:23:02.021399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6360 19:23:02.021472 ==
6361 19:23:02.021556
6362 19:23:02.021614
6363 19:23:02.024296 TX Vref Scan disable
6364 19:23:02.024367 == TX Byte 0 ==
6365 19:23:02.031146 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6366 19:23:02.034332 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6367 19:23:02.034410 == TX Byte 1 ==
6368 19:23:02.041136 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6369 19:23:02.044623 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6370 19:23:02.044698
6371 19:23:02.044759 [DATLAT]
6372 19:23:02.047612 Freq=400, CH0 RK0
6373 19:23:02.047679
6374 19:23:02.047746 DATLAT Default: 0xf
6375 19:23:02.050821 0, 0xFFFF, sum = 0
6376 19:23:02.050887 1, 0xFFFF, sum = 0
6377 19:23:02.054365 2, 0xFFFF, sum = 0
6378 19:23:02.054435 3, 0xFFFF, sum = 0
6379 19:23:02.057295 4, 0xFFFF, sum = 0
6380 19:23:02.057400 5, 0xFFFF, sum = 0
6381 19:23:02.060920 6, 0xFFFF, sum = 0
6382 19:23:02.061000 7, 0xFFFF, sum = 0
6383 19:23:02.063863 8, 0xFFFF, sum = 0
6384 19:23:02.067527 9, 0xFFFF, sum = 0
6385 19:23:02.067683 10, 0xFFFF, sum = 0
6386 19:23:02.070713 11, 0xFFFF, sum = 0
6387 19:23:02.070792 12, 0xFFFF, sum = 0
6388 19:23:02.073889 13, 0x0, sum = 1
6389 19:23:02.073996 14, 0x0, sum = 2
6390 19:23:02.077056 15, 0x0, sum = 3
6391 19:23:02.077162 16, 0x0, sum = 4
6392 19:23:02.077253 best_step = 14
6393 19:23:02.080506
6394 19:23:02.080623 ==
6395 19:23:02.084254 Dram Type= 6, Freq= 0, CH_0, rank 0
6396 19:23:02.087046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6397 19:23:02.087125 ==
6398 19:23:02.087187 RX Vref Scan: 1
6399 19:23:02.087244
6400 19:23:02.090314 RX Vref 0 -> 0, step: 1
6401 19:23:02.090392
6402 19:23:02.094065 RX Delay -375 -> 252, step: 8
6403 19:23:02.094171
6404 19:23:02.097346 Set Vref, RX VrefLevel [Byte0]: 62
6405 19:23:02.100276 [Byte1]: 52
6406 19:23:02.104257
6407 19:23:02.104335 Final RX Vref Byte 0 = 62 to rank0
6408 19:23:02.107832 Final RX Vref Byte 1 = 52 to rank0
6409 19:23:02.110927 Final RX Vref Byte 0 = 62 to rank1
6410 19:23:02.114453 Final RX Vref Byte 1 = 52 to rank1==
6411 19:23:02.117582 Dram Type= 6, Freq= 0, CH_0, rank 0
6412 19:23:02.124193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6413 19:23:02.124296 ==
6414 19:23:02.124393 DQS Delay:
6415 19:23:02.127543 DQS0 = 60, DQS1 = 68
6416 19:23:02.127614 DQM Delay:
6417 19:23:02.127678 DQM0 = 13, DQM1 = 14
6418 19:23:02.131016 DQ Delay:
6419 19:23:02.134010 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =8
6420 19:23:02.137400 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6421 19:23:02.137528 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6422 19:23:02.140714 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =24
6423 19:23:02.144405
6424 19:23:02.144476
6425 19:23:02.150926 [DQSOSCAuto] RK0, (LSB)MR18= 0x8b89, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
6426 19:23:02.154260 CH0 RK0: MR19=C0C, MR18=8B89
6427 19:23:02.161018 CH0_RK0: MR19=0xC0C, MR18=0x8B89, DQSOSC=392, MR23=63, INC=384, DEC=256
6428 19:23:02.161115 ==
6429 19:23:02.163963 Dram Type= 6, Freq= 0, CH_0, rank 1
6430 19:23:02.167724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6431 19:23:02.167815 ==
6432 19:23:02.170691 [Gating] SW mode calibration
6433 19:23:02.177381 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6434 19:23:02.183944 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6435 19:23:02.187270 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6436 19:23:02.190278 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6437 19:23:02.197320 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6438 19:23:02.200476 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6439 19:23:02.203834 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6440 19:23:02.210561 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6441 19:23:02.214024 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6442 19:23:02.217208 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6443 19:23:02.223799 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6444 19:23:02.223876 Total UI for P1: 0, mck2ui 16
6445 19:23:02.226896 best dqsien dly found for B0: ( 0, 14, 24)
6446 19:23:02.230477 Total UI for P1: 0, mck2ui 16
6447 19:23:02.233588 best dqsien dly found for B1: ( 0, 14, 24)
6448 19:23:02.240449 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6449 19:23:02.243510 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6450 19:23:02.243585
6451 19:23:02.247108 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6452 19:23:02.250503 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6453 19:23:02.253664 [Gating] SW calibration Done
6454 19:23:02.253771 ==
6455 19:23:02.257023 Dram Type= 6, Freq= 0, CH_0, rank 1
6456 19:23:02.260185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6457 19:23:02.260267 ==
6458 19:23:02.263436 RX Vref Scan: 0
6459 19:23:02.263544
6460 19:23:02.263637 RX Vref 0 -> 0, step: 1
6461 19:23:02.263730
6462 19:23:02.266596 RX Delay -410 -> 252, step: 16
6463 19:23:02.273303 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6464 19:23:02.276892 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6465 19:23:02.279816 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6466 19:23:02.283286 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6467 19:23:02.290152 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6468 19:23:02.293364 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6469 19:23:02.296268 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6470 19:23:02.299820 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6471 19:23:02.306305 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6472 19:23:02.309412 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6473 19:23:02.312800 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6474 19:23:02.316102 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6475 19:23:02.323029 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6476 19:23:02.326156 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6477 19:23:02.329249 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6478 19:23:02.332830 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6479 19:23:02.336207 ==
6480 19:23:02.339698 Dram Type= 6, Freq= 0, CH_0, rank 1
6481 19:23:02.342613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6482 19:23:02.342692 ==
6483 19:23:02.342755 DQS Delay:
6484 19:23:02.345801 DQS0 = 59, DQS1 = 59
6485 19:23:02.345879 DQM Delay:
6486 19:23:02.349325 DQM0 = 16, DQM1 = 10
6487 19:23:02.349404 DQ Delay:
6488 19:23:02.352417 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6489 19:23:02.355933 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6490 19:23:02.359349 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6491 19:23:02.362701 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6492 19:23:02.362779
6493 19:23:02.362841
6494 19:23:02.362898 ==
6495 19:23:02.365869 Dram Type= 6, Freq= 0, CH_0, rank 1
6496 19:23:02.369092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6497 19:23:02.369171 ==
6498 19:23:02.369234
6499 19:23:02.369291
6500 19:23:02.372595 TX Vref Scan disable
6501 19:23:02.372673 == TX Byte 0 ==
6502 19:23:02.379130 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6503 19:23:02.382800 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6504 19:23:02.382884 == TX Byte 1 ==
6505 19:23:02.389351 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6506 19:23:02.392352 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6507 19:23:02.392431 ==
6508 19:23:02.395836 Dram Type= 6, Freq= 0, CH_0, rank 1
6509 19:23:02.399279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6510 19:23:02.399357 ==
6511 19:23:02.399420
6512 19:23:02.399478
6513 19:23:02.402833 TX Vref Scan disable
6514 19:23:02.402943 == TX Byte 0 ==
6515 19:23:02.408943 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6516 19:23:02.412490 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6517 19:23:02.412567 == TX Byte 1 ==
6518 19:23:02.418858 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6519 19:23:02.422204 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6520 19:23:02.422314
6521 19:23:02.422375 [DATLAT]
6522 19:23:02.425544 Freq=400, CH0 RK1
6523 19:23:02.425635
6524 19:23:02.425698 DATLAT Default: 0xe
6525 19:23:02.429057 0, 0xFFFF, sum = 0
6526 19:23:02.429137 1, 0xFFFF, sum = 0
6527 19:23:02.432557 2, 0xFFFF, sum = 0
6528 19:23:02.432637 3, 0xFFFF, sum = 0
6529 19:23:02.435618 4, 0xFFFF, sum = 0
6530 19:23:02.435698 5, 0xFFFF, sum = 0
6531 19:23:02.439152 6, 0xFFFF, sum = 0
6532 19:23:02.439232 7, 0xFFFF, sum = 0
6533 19:23:02.442727 8, 0xFFFF, sum = 0
6534 19:23:02.445619 9, 0xFFFF, sum = 0
6535 19:23:02.445700 10, 0xFFFF, sum = 0
6536 19:23:02.449346 11, 0xFFFF, sum = 0
6537 19:23:02.449452 12, 0xFFFF, sum = 0
6538 19:23:02.452346 13, 0x0, sum = 1
6539 19:23:02.452425 14, 0x0, sum = 2
6540 19:23:02.455372 15, 0x0, sum = 3
6541 19:23:02.455451 16, 0x0, sum = 4
6542 19:23:02.455515 best_step = 14
6543 19:23:02.458848
6544 19:23:02.458942 ==
6545 19:23:02.462453 Dram Type= 6, Freq= 0, CH_0, rank 1
6546 19:23:02.465433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6547 19:23:02.465579 ==
6548 19:23:02.465680 RX Vref Scan: 0
6549 19:23:02.465739
6550 19:23:02.468984 RX Vref 0 -> 0, step: 1
6551 19:23:02.469062
6552 19:23:02.472190 RX Delay -359 -> 252, step: 8
6553 19:23:02.479472 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6554 19:23:02.482504 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6555 19:23:02.486095 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6556 19:23:02.489531 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6557 19:23:02.496257 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6558 19:23:02.499274 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6559 19:23:02.502538 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6560 19:23:02.505896 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6561 19:23:02.512253 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6562 19:23:02.515939 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6563 19:23:02.519186 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6564 19:23:02.522644 iDelay=217, Bit 11, Center -64 (-311 ~ 184) 496
6565 19:23:02.528966 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6566 19:23:02.532273 iDelay=217, Bit 13, Center -44 (-295 ~ 208) 504
6567 19:23:02.535759 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6568 19:23:02.542339 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6569 19:23:02.542419 ==
6570 19:23:02.545321 Dram Type= 6, Freq= 0, CH_0, rank 1
6571 19:23:02.548706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6572 19:23:02.548810 ==
6573 19:23:02.548901 DQS Delay:
6574 19:23:02.552462 DQS0 = 60, DQS1 = 72
6575 19:23:02.552540 DQM Delay:
6576 19:23:02.555309 DQM0 = 11, DQM1 = 17
6577 19:23:02.555387 DQ Delay:
6578 19:23:02.558856 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6579 19:23:02.561919 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6580 19:23:02.565430 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =8
6581 19:23:02.569042 DQ12 =24, DQ13 =28, DQ14 =28, DQ15 =24
6582 19:23:02.569121
6583 19:23:02.569182
6584 19:23:02.575020 [DQSOSCAuto] RK1, (LSB)MR18= 0xcb81, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 384 ps
6585 19:23:02.578482 CH0 RK1: MR19=C0C, MR18=CB81
6586 19:23:02.585067 CH0_RK1: MR19=0xC0C, MR18=0xCB81, DQSOSC=384, MR23=63, INC=400, DEC=267
6587 19:23:02.588573 [RxdqsGatingPostProcess] freq 400
6588 19:23:02.594936 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6589 19:23:02.598496 best DQS0 dly(2T, 0.5T) = (0, 10)
6590 19:23:02.598579 best DQS1 dly(2T, 0.5T) = (0, 10)
6591 19:23:02.601408 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6592 19:23:02.605029 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6593 19:23:02.608496 best DQS0 dly(2T, 0.5T) = (0, 10)
6594 19:23:02.611329 best DQS1 dly(2T, 0.5T) = (0, 10)
6595 19:23:02.615011 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6596 19:23:02.617940 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6597 19:23:02.621440 Pre-setting of DQS Precalculation
6598 19:23:02.628120 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6599 19:23:02.628199 ==
6600 19:23:02.631576 Dram Type= 6, Freq= 0, CH_1, rank 0
6601 19:23:02.634594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6602 19:23:02.634696 ==
6603 19:23:02.641360 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6604 19:23:02.647922 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6605 19:23:02.648001 [CA 0] Center 36 (8~64) winsize 57
6606 19:23:02.651518 [CA 1] Center 36 (8~64) winsize 57
6607 19:23:02.654455 [CA 2] Center 36 (8~64) winsize 57
6608 19:23:02.658057 [CA 3] Center 36 (8~64) winsize 57
6609 19:23:02.661123 [CA 4] Center 36 (8~64) winsize 57
6610 19:23:02.664734 [CA 5] Center 36 (8~64) winsize 57
6611 19:23:02.664813
6612 19:23:02.667673 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6613 19:23:02.667752
6614 19:23:02.671122 [CATrainingPosCal] consider 1 rank data
6615 19:23:02.674169 u2DelayCellTimex100 = 270/100 ps
6616 19:23:02.677813 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6617 19:23:02.684198 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6618 19:23:02.687295 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6619 19:23:02.690656 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6620 19:23:02.694277 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6621 19:23:02.697491 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6622 19:23:02.697602
6623 19:23:02.700605 CA PerBit enable=1, Macro0, CA PI delay=36
6624 19:23:02.700674
6625 19:23:02.704215 [CBTSetCACLKResult] CA Dly = 36
6626 19:23:02.704294 CS Dly: 1 (0~32)
6627 19:23:02.707645 ==
6628 19:23:02.710626 Dram Type= 6, Freq= 0, CH_1, rank 1
6629 19:23:02.714204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6630 19:23:02.714284 ==
6631 19:23:02.717654 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6632 19:23:02.723831 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6633 19:23:02.727431 [CA 0] Center 36 (8~64) winsize 57
6634 19:23:02.730558 [CA 1] Center 36 (8~64) winsize 57
6635 19:23:02.734018 [CA 2] Center 36 (8~64) winsize 57
6636 19:23:02.737548 [CA 3] Center 36 (8~64) winsize 57
6637 19:23:02.740545 [CA 4] Center 36 (8~64) winsize 57
6638 19:23:02.743872 [CA 5] Center 36 (8~64) winsize 57
6639 19:23:02.743952
6640 19:23:02.747152 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6641 19:23:02.747231
6642 19:23:02.750386 [CATrainingPosCal] consider 2 rank data
6643 19:23:02.753820 u2DelayCellTimex100 = 270/100 ps
6644 19:23:02.757227 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6645 19:23:02.760391 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6646 19:23:02.763593 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6647 19:23:02.767271 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6648 19:23:02.773799 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6649 19:23:02.777246 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6650 19:23:02.777317
6651 19:23:02.780249 CA PerBit enable=1, Macro0, CA PI delay=36
6652 19:23:02.780353
6653 19:23:02.783725 [CBTSetCACLKResult] CA Dly = 36
6654 19:23:02.783798 CS Dly: 1 (0~32)
6655 19:23:02.783859
6656 19:23:02.786804 ----->DramcWriteLeveling(PI) begin...
6657 19:23:02.786877 ==
6658 19:23:02.790460 Dram Type= 6, Freq= 0, CH_1, rank 0
6659 19:23:02.797124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6660 19:23:02.797204 ==
6661 19:23:02.800113 Write leveling (Byte 0): 40 => 8
6662 19:23:02.800214 Write leveling (Byte 1): 40 => 8
6663 19:23:02.803912 DramcWriteLeveling(PI) end<-----
6664 19:23:02.803991
6665 19:23:02.804058 ==
6666 19:23:02.807081 Dram Type= 6, Freq= 0, CH_1, rank 0
6667 19:23:02.813582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6668 19:23:02.813662 ==
6669 19:23:02.816630 [Gating] SW mode calibration
6670 19:23:02.823264 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6671 19:23:02.826545 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6672 19:23:02.833532 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6673 19:23:02.836463 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6674 19:23:02.839717 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6675 19:23:02.846821 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6676 19:23:02.849854 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6677 19:23:02.853431 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6678 19:23:02.859843 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6679 19:23:02.863198 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6680 19:23:02.866619 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6681 19:23:02.869725 Total UI for P1: 0, mck2ui 16
6682 19:23:02.873274 best dqsien dly found for B0: ( 0, 14, 24)
6683 19:23:02.876736 Total UI for P1: 0, mck2ui 16
6684 19:23:02.879963 best dqsien dly found for B1: ( 0, 14, 24)
6685 19:23:02.883016 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6686 19:23:02.886546 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6687 19:23:02.886648
6688 19:23:02.892984 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6689 19:23:02.896596 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6690 19:23:02.896694 [Gating] SW calibration Done
6691 19:23:02.899558 ==
6692 19:23:02.903111 Dram Type= 6, Freq= 0, CH_1, rank 0
6693 19:23:02.906815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6694 19:23:02.906884 ==
6695 19:23:02.906943 RX Vref Scan: 0
6696 19:23:02.907009
6697 19:23:02.909623 RX Vref 0 -> 0, step: 1
6698 19:23:02.909697
6699 19:23:02.913362 RX Delay -410 -> 252, step: 16
6700 19:23:02.916390 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6701 19:23:02.919675 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6702 19:23:02.926114 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6703 19:23:02.929723 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6704 19:23:02.932812 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6705 19:23:02.936184 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6706 19:23:02.943397 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6707 19:23:02.946122 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6708 19:23:02.949396 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6709 19:23:02.952969 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6710 19:23:02.959641 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6711 19:23:02.963225 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6712 19:23:02.966040 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6713 19:23:02.969615 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6714 19:23:02.976411 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6715 19:23:02.979390 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6716 19:23:02.979469 ==
6717 19:23:02.982684 Dram Type= 6, Freq= 0, CH_1, rank 0
6718 19:23:02.986297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6719 19:23:02.986389 ==
6720 19:23:02.989223 DQS Delay:
6721 19:23:02.989291 DQS0 = 51, DQS1 = 67
6722 19:23:02.992846 DQM Delay:
6723 19:23:02.992913 DQM0 = 13, DQM1 = 17
6724 19:23:02.992971 DQ Delay:
6725 19:23:02.996339 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6726 19:23:02.999389 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6727 19:23:03.002994 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6728 19:23:03.005935 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6729 19:23:03.006007
6730 19:23:03.006068
6731 19:23:03.006124 ==
6732 19:23:03.009608 Dram Type= 6, Freq= 0, CH_1, rank 0
6733 19:23:03.016152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6734 19:23:03.016236 ==
6735 19:23:03.016299
6736 19:23:03.016363
6737 19:23:03.016421 TX Vref Scan disable
6738 19:23:03.019571 == TX Byte 0 ==
6739 19:23:03.023002 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6740 19:23:03.026183 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6741 19:23:03.029238 == TX Byte 1 ==
6742 19:23:03.032865 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6743 19:23:03.035749 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6744 19:23:03.035829 ==
6745 19:23:03.039066 Dram Type= 6, Freq= 0, CH_1, rank 0
6746 19:23:03.046072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6747 19:23:03.046156 ==
6748 19:23:03.046221
6749 19:23:03.046279
6750 19:23:03.046335 TX Vref Scan disable
6751 19:23:03.049120 == TX Byte 0 ==
6752 19:23:03.052550 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6753 19:23:03.055870 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6754 19:23:03.059264 == TX Byte 1 ==
6755 19:23:03.062834 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6756 19:23:03.065879 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6757 19:23:03.065979
6758 19:23:03.069016 [DATLAT]
6759 19:23:03.069086 Freq=400, CH1 RK0
6760 19:23:03.069150
6761 19:23:03.072399 DATLAT Default: 0xf
6762 19:23:03.072492 0, 0xFFFF, sum = 0
6763 19:23:03.075488 1, 0xFFFF, sum = 0
6764 19:23:03.075558 2, 0xFFFF, sum = 0
6765 19:23:03.079122 3, 0xFFFF, sum = 0
6766 19:23:03.079225 4, 0xFFFF, sum = 0
6767 19:23:03.082203 5, 0xFFFF, sum = 0
6768 19:23:03.082299 6, 0xFFFF, sum = 0
6769 19:23:03.085837 7, 0xFFFF, sum = 0
6770 19:23:03.088825 8, 0xFFFF, sum = 0
6771 19:23:03.088922 9, 0xFFFF, sum = 0
6772 19:23:03.092412 10, 0xFFFF, sum = 0
6773 19:23:03.092482 11, 0xFFFF, sum = 0
6774 19:23:03.095724 12, 0xFFFF, sum = 0
6775 19:23:03.095803 13, 0x0, sum = 1
6776 19:23:03.099052 14, 0x0, sum = 2
6777 19:23:03.099123 15, 0x0, sum = 3
6778 19:23:03.102556 16, 0x0, sum = 4
6779 19:23:03.102652 best_step = 14
6780 19:23:03.102737
6781 19:23:03.102828 ==
6782 19:23:03.105485 Dram Type= 6, Freq= 0, CH_1, rank 0
6783 19:23:03.108853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6784 19:23:03.108922 ==
6785 19:23:03.112122 RX Vref Scan: 1
6786 19:23:03.112195
6787 19:23:03.115613 RX Vref 0 -> 0, step: 1
6788 19:23:03.115685
6789 19:23:03.115746 RX Delay -375 -> 252, step: 8
6790 19:23:03.115803
6791 19:23:03.118646 Set Vref, RX VrefLevel [Byte0]: 59
6792 19:23:03.122057 [Byte1]: 47
6793 19:23:03.128014
6794 19:23:03.128094 Final RX Vref Byte 0 = 59 to rank0
6795 19:23:03.130928 Final RX Vref Byte 1 = 47 to rank0
6796 19:23:03.134063 Final RX Vref Byte 0 = 59 to rank1
6797 19:23:03.137740 Final RX Vref Byte 1 = 47 to rank1==
6798 19:23:03.141224 Dram Type= 6, Freq= 0, CH_1, rank 0
6799 19:23:03.147587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6800 19:23:03.147661 ==
6801 19:23:03.147723 DQS Delay:
6802 19:23:03.150881 DQS0 = 56, DQS1 = 68
6803 19:23:03.151000 DQM Delay:
6804 19:23:03.151102 DQM0 = 12, DQM1 = 15
6805 19:23:03.153999 DQ Delay:
6806 19:23:03.157576 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6807 19:23:03.157655 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6808 19:23:03.161146 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =8
6809 19:23:03.164019 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6810 19:23:03.164091
6811 19:23:03.167649
6812 19:23:03.174204 [DQSOSCAuto] RK0, (LSB)MR18= 0x6579, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 397 ps
6813 19:23:03.177112 CH1 RK0: MR19=C0C, MR18=6579
6814 19:23:03.183744 CH1_RK0: MR19=0xC0C, MR18=0x6579, DQSOSC=394, MR23=63, INC=380, DEC=253
6815 19:23:03.183824 ==
6816 19:23:03.187396 Dram Type= 6, Freq= 0, CH_1, rank 1
6817 19:23:03.190374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6818 19:23:03.190450 ==
6819 19:23:03.193912 [Gating] SW mode calibration
6820 19:23:03.200326 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6821 19:23:03.206880 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6822 19:23:03.210382 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6823 19:23:03.213712 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6824 19:23:03.220428 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6825 19:23:03.223755 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6826 19:23:03.227017 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6827 19:23:03.233854 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6828 19:23:03.236828 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6829 19:23:03.240291 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6830 19:23:03.246539 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6831 19:23:03.246613 Total UI for P1: 0, mck2ui 16
6832 19:23:03.253302 best dqsien dly found for B0: ( 0, 14, 24)
6833 19:23:03.253400 Total UI for P1: 0, mck2ui 16
6834 19:23:03.256742 best dqsien dly found for B1: ( 0, 14, 24)
6835 19:23:03.263463 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6836 19:23:03.266497 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6837 19:23:03.266574
6838 19:23:03.269885 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6839 19:23:03.273166 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6840 19:23:03.276589 [Gating] SW calibration Done
6841 19:23:03.276668 ==
6842 19:23:03.279864 Dram Type= 6, Freq= 0, CH_1, rank 1
6843 19:23:03.282880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6844 19:23:03.282960 ==
6845 19:23:03.286545 RX Vref Scan: 0
6846 19:23:03.286623
6847 19:23:03.286685 RX Vref 0 -> 0, step: 1
6848 19:23:03.286743
6849 19:23:03.289633 RX Delay -410 -> 252, step: 16
6850 19:23:03.296290 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6851 19:23:03.299906 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6852 19:23:03.302732 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6853 19:23:03.306433 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6854 19:23:03.312782 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6855 19:23:03.316424 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6856 19:23:03.319343 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6857 19:23:03.322821 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6858 19:23:03.329335 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6859 19:23:03.333009 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6860 19:23:03.336144 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6861 19:23:03.339505 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6862 19:23:03.345873 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6863 19:23:03.349015 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6864 19:23:03.352572 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6865 19:23:03.355714 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6866 19:23:03.359164 ==
6867 19:23:03.362642 Dram Type= 6, Freq= 0, CH_1, rank 1
6868 19:23:03.365744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6869 19:23:03.365852 ==
6870 19:23:03.365918 DQS Delay:
6871 19:23:03.369294 DQS0 = 59, DQS1 = 59
6872 19:23:03.369388 DQM Delay:
6873 19:23:03.372288 DQM0 = 19, DQM1 = 12
6874 19:23:03.372380 DQ Delay:
6875 19:23:03.375843 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6876 19:23:03.379302 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6877 19:23:03.382628 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6878 19:23:03.385709 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6879 19:23:03.385793
6880 19:23:03.385853
6881 19:23:03.385910 ==
6882 19:23:03.389258 Dram Type= 6, Freq= 0, CH_1, rank 1
6883 19:23:03.392248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6884 19:23:03.392347 ==
6885 19:23:03.392434
6886 19:23:03.392517
6887 19:23:03.395779 TX Vref Scan disable
6888 19:23:03.395870 == TX Byte 0 ==
6889 19:23:03.402509 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6890 19:23:03.405569 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6891 19:23:03.405663 == TX Byte 1 ==
6892 19:23:03.412133 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6893 19:23:03.415437 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6894 19:23:03.415537 ==
6895 19:23:03.418631 Dram Type= 6, Freq= 0, CH_1, rank 1
6896 19:23:03.422191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6897 19:23:03.422276 ==
6898 19:23:03.422364
6899 19:23:03.422449
6900 19:23:03.425223 TX Vref Scan disable
6901 19:23:03.425313 == TX Byte 0 ==
6902 19:23:03.432244 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6903 19:23:03.435268 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6904 19:23:03.435373 == TX Byte 1 ==
6905 19:23:03.442178 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6906 19:23:03.445440 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6907 19:23:03.445560
6908 19:23:03.445622 [DATLAT]
6909 19:23:03.448622 Freq=400, CH1 RK1
6910 19:23:03.448716
6911 19:23:03.448802 DATLAT Default: 0xe
6912 19:23:03.451998 0, 0xFFFF, sum = 0
6913 19:23:03.452106 1, 0xFFFF, sum = 0
6914 19:23:03.455639 2, 0xFFFF, sum = 0
6915 19:23:03.455740 3, 0xFFFF, sum = 0
6916 19:23:03.458635 4, 0xFFFF, sum = 0
6917 19:23:03.458718 5, 0xFFFF, sum = 0
6918 19:23:03.461944 6, 0xFFFF, sum = 0
6919 19:23:03.465318 7, 0xFFFF, sum = 0
6920 19:23:03.465416 8, 0xFFFF, sum = 0
6921 19:23:03.468346 9, 0xFFFF, sum = 0
6922 19:23:03.468450 10, 0xFFFF, sum = 0
6923 19:23:03.471577 11, 0xFFFF, sum = 0
6924 19:23:03.471677 12, 0xFFFF, sum = 0
6925 19:23:03.475269 13, 0x0, sum = 1
6926 19:23:03.475368 14, 0x0, sum = 2
6927 19:23:03.478171 15, 0x0, sum = 3
6928 19:23:03.478244 16, 0x0, sum = 4
6929 19:23:03.481673 best_step = 14
6930 19:23:03.481766
6931 19:23:03.481860 ==
6932 19:23:03.485142 Dram Type= 6, Freq= 0, CH_1, rank 1
6933 19:23:03.488066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6934 19:23:03.488166 ==
6935 19:23:03.488228 RX Vref Scan: 0
6936 19:23:03.488293
6937 19:23:03.491393 RX Vref 0 -> 0, step: 1
6938 19:23:03.491488
6939 19:23:03.494549 RX Delay -359 -> 252, step: 8
6940 19:23:03.502391 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6941 19:23:03.505429 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
6942 19:23:03.508957 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
6943 19:23:03.511979 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6944 19:23:03.518976 iDelay=217, Bit 4, Center -48 (-303 ~ 208) 512
6945 19:23:03.521944 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
6946 19:23:03.525610 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6947 19:23:03.528523 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
6948 19:23:03.535580 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
6949 19:23:03.538535 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
6950 19:23:03.542211 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6951 19:23:03.548512 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6952 19:23:03.551710 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6953 19:23:03.555544 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6954 19:23:03.558794 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
6955 19:23:03.565103 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6956 19:23:03.565220 ==
6957 19:23:03.568651 Dram Type= 6, Freq= 0, CH_1, rank 1
6958 19:23:03.572184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6959 19:23:03.572285 ==
6960 19:23:03.572374 DQS Delay:
6961 19:23:03.575002 DQS0 = 60, DQS1 = 64
6962 19:23:03.575079 DQM Delay:
6963 19:23:03.578688 DQM0 = 12, DQM1 = 10
6964 19:23:03.578756 DQ Delay:
6965 19:23:03.582045 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6966 19:23:03.585404 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6967 19:23:03.588583 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6968 19:23:03.591647 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6969 19:23:03.591718
6970 19:23:03.591777
6971 19:23:03.598831 [DQSOSCAuto] RK1, (LSB)MR18= 0x86b5, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 393 ps
6972 19:23:03.601840 CH1 RK1: MR19=C0C, MR18=86B5
6973 19:23:03.608621 CH1_RK1: MR19=0xC0C, MR18=0x86B5, DQSOSC=387, MR23=63, INC=394, DEC=262
6974 19:23:03.611972 [RxdqsGatingPostProcess] freq 400
6975 19:23:03.618536 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6976 19:23:03.618615 best DQS0 dly(2T, 0.5T) = (0, 10)
6977 19:23:03.622223 best DQS1 dly(2T, 0.5T) = (0, 10)
6978 19:23:03.625054 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6979 19:23:03.628575 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6980 19:23:03.631486 best DQS0 dly(2T, 0.5T) = (0, 10)
6981 19:23:03.635023 best DQS1 dly(2T, 0.5T) = (0, 10)
6982 19:23:03.638592 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6983 19:23:03.641426 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6984 19:23:03.645070 Pre-setting of DQS Precalculation
6985 19:23:03.651585 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6986 19:23:03.658186 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6987 19:23:03.664604 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6988 19:23:03.664683
6989 19:23:03.664746
6990 19:23:03.668039 [Calibration Summary] 800 Mbps
6991 19:23:03.668120 CH 0, Rank 0
6992 19:23:03.671270 SW Impedance : PASS
6993 19:23:03.674611 DUTY Scan : NO K
6994 19:23:03.674690 ZQ Calibration : PASS
6995 19:23:03.678268 Jitter Meter : NO K
6996 19:23:03.681229 CBT Training : PASS
6997 19:23:03.681333 Write leveling : PASS
6998 19:23:03.684621 RX DQS gating : PASS
6999 19:23:03.684700 RX DQ/DQS(RDDQC) : PASS
7000 19:23:03.687926 TX DQ/DQS : PASS
7001 19:23:03.690942 RX DATLAT : PASS
7002 19:23:03.691021 RX DQ/DQS(Engine): PASS
7003 19:23:03.694421 TX OE : NO K
7004 19:23:03.694525 All Pass.
7005 19:23:03.694615
7006 19:23:03.697925 CH 0, Rank 1
7007 19:23:03.698007 SW Impedance : PASS
7008 19:23:03.700882 DUTY Scan : NO K
7009 19:23:03.704420 ZQ Calibration : PASS
7010 19:23:03.704493 Jitter Meter : NO K
7011 19:23:03.707419 CBT Training : PASS
7012 19:23:03.711008 Write leveling : NO K
7013 19:23:03.711087 RX DQS gating : PASS
7014 19:23:03.714442 RX DQ/DQS(RDDQC) : PASS
7015 19:23:03.717442 TX DQ/DQS : PASS
7016 19:23:03.717579 RX DATLAT : PASS
7017 19:23:03.721215 RX DQ/DQS(Engine): PASS
7018 19:23:03.724597 TX OE : NO K
7019 19:23:03.724685 All Pass.
7020 19:23:03.724749
7021 19:23:03.724832 CH 1, Rank 0
7022 19:23:03.727486 SW Impedance : PASS
7023 19:23:03.730917 DUTY Scan : NO K
7024 19:23:03.731048 ZQ Calibration : PASS
7025 19:23:03.734453 Jitter Meter : NO K
7026 19:23:03.737399 CBT Training : PASS
7027 19:23:03.737516 Write leveling : PASS
7028 19:23:03.741023 RX DQS gating : PASS
7029 19:23:03.743824 RX DQ/DQS(RDDQC) : PASS
7030 19:23:03.743934 TX DQ/DQS : PASS
7031 19:23:03.747508 RX DATLAT : PASS
7032 19:23:03.747625 RX DQ/DQS(Engine): PASS
7033 19:23:03.751080 TX OE : NO K
7034 19:23:03.751194 All Pass.
7035 19:23:03.751272
7036 19:23:03.753744 CH 1, Rank 1
7037 19:23:03.753851 SW Impedance : PASS
7038 19:23:03.757406 DUTY Scan : NO K
7039 19:23:03.760692 ZQ Calibration : PASS
7040 19:23:03.760799 Jitter Meter : NO K
7041 19:23:03.763702 CBT Training : PASS
7042 19:23:03.767214 Write leveling : NO K
7043 19:23:03.767314 RX DQS gating : PASS
7044 19:23:03.770678 RX DQ/DQS(RDDQC) : PASS
7045 19:23:03.773574 TX DQ/DQS : PASS
7046 19:23:03.773710 RX DATLAT : PASS
7047 19:23:03.777028 RX DQ/DQS(Engine): PASS
7048 19:23:03.780391 TX OE : NO K
7049 19:23:03.780507 All Pass.
7050 19:23:03.780602
7051 19:23:03.783647 DramC Write-DBI off
7052 19:23:03.783745 PER_BANK_REFRESH: Hybrid Mode
7053 19:23:03.787303 TX_TRACKING: ON
7054 19:23:03.793880 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7055 19:23:03.800318 [FAST_K] Save calibration result to emmc
7056 19:23:03.803488 dramc_set_vcore_voltage set vcore to 725000
7057 19:23:03.803572 Read voltage for 1600, 0
7058 19:23:03.806575 Vio18 = 0
7059 19:23:03.806687 Vcore = 725000
7060 19:23:03.806766 Vdram = 0
7061 19:23:03.810253 Vddq = 0
7062 19:23:03.810331 Vmddr = 0
7063 19:23:03.813324 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7064 19:23:03.820003 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7065 19:23:03.823549 MEM_TYPE=3, freq_sel=13
7066 19:23:03.826874 sv_algorithm_assistance_LP4_3733
7067 19:23:03.830020 ============ PULL DRAM RESETB DOWN ============
7068 19:23:03.833075 ========== PULL DRAM RESETB DOWN end =========
7069 19:23:03.839751 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7070 19:23:03.843345 ===================================
7071 19:23:03.843422 LPDDR4 DRAM CONFIGURATION
7072 19:23:03.846778 ===================================
7073 19:23:03.849816 EX_ROW_EN[0] = 0x0
7074 19:23:03.853427 EX_ROW_EN[1] = 0x0
7075 19:23:03.853539 LP4Y_EN = 0x0
7076 19:23:03.856422 WORK_FSP = 0x1
7077 19:23:03.856529 WL = 0x5
7078 19:23:03.859934 RL = 0x5
7079 19:23:03.860052 BL = 0x2
7080 19:23:03.862816 RPST = 0x0
7081 19:23:03.862899 RD_PRE = 0x0
7082 19:23:03.866343 WR_PRE = 0x1
7083 19:23:03.866438 WR_PST = 0x1
7084 19:23:03.869880 DBI_WR = 0x0
7085 19:23:03.869957 DBI_RD = 0x0
7086 19:23:03.872682 OTF = 0x1
7087 19:23:03.876207 ===================================
7088 19:23:03.879374 ===================================
7089 19:23:03.879448 ANA top config
7090 19:23:03.882973 ===================================
7091 19:23:03.885908 DLL_ASYNC_EN = 0
7092 19:23:03.889664 ALL_SLAVE_EN = 0
7093 19:23:03.889738 NEW_RANK_MODE = 1
7094 19:23:03.892500 DLL_IDLE_MODE = 1
7095 19:23:03.896141 LP45_APHY_COMB_EN = 1
7096 19:23:03.899094 TX_ODT_DIS = 0
7097 19:23:03.902747 NEW_8X_MODE = 1
7098 19:23:03.906066 ===================================
7099 19:23:03.909256 ===================================
7100 19:23:03.912487 data_rate = 3200
7101 19:23:03.912567 CKR = 1
7102 19:23:03.915933 DQ_P2S_RATIO = 8
7103 19:23:03.919402 ===================================
7104 19:23:03.922498 CA_P2S_RATIO = 8
7105 19:23:03.926021 DQ_CA_OPEN = 0
7106 19:23:03.929044 DQ_SEMI_OPEN = 0
7107 19:23:03.932081 CA_SEMI_OPEN = 0
7108 19:23:03.932162 CA_FULL_RATE = 0
7109 19:23:03.935583 DQ_CKDIV4_EN = 0
7110 19:23:03.939025 CA_CKDIV4_EN = 0
7111 19:23:03.942276 CA_PREDIV_EN = 0
7112 19:23:03.945300 PH8_DLY = 12
7113 19:23:03.948953 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7114 19:23:03.949031 DQ_AAMCK_DIV = 4
7115 19:23:03.952405 CA_AAMCK_DIV = 4
7116 19:23:03.955596 CA_ADMCK_DIV = 4
7117 19:23:03.959090 DQ_TRACK_CA_EN = 0
7118 19:23:03.961941 CA_PICK = 1600
7119 19:23:03.965406 CA_MCKIO = 1600
7120 19:23:03.969095 MCKIO_SEMI = 0
7121 19:23:03.969175 PLL_FREQ = 3068
7122 19:23:03.972007 DQ_UI_PI_RATIO = 32
7123 19:23:03.975580 CA_UI_PI_RATIO = 0
7124 19:23:03.978447 ===================================
7125 19:23:03.982055 ===================================
7126 19:23:03.985008 memory_type:LPDDR4
7127 19:23:03.988757 GP_NUM : 10
7128 19:23:03.988830 SRAM_EN : 1
7129 19:23:03.991724 MD32_EN : 0
7130 19:23:03.995068 ===================================
7131 19:23:03.995143 [ANA_INIT] >>>>>>>>>>>>>>
7132 19:23:03.998290 <<<<<< [CONFIGURE PHASE]: ANA_TX
7133 19:23:04.001644 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7134 19:23:04.005159 ===================================
7135 19:23:04.008157 data_rate = 3200,PCW = 0X7600
7136 19:23:04.011287 ===================================
7137 19:23:04.014718 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7138 19:23:04.021640 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7139 19:23:04.027976 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7140 19:23:04.031603 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7141 19:23:04.034672 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7142 19:23:04.037700 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7143 19:23:04.041266 [ANA_INIT] flow start
7144 19:23:04.041345 [ANA_INIT] PLL >>>>>>>>
7145 19:23:04.044855 [ANA_INIT] PLL <<<<<<<<
7146 19:23:04.047724 [ANA_INIT] MIDPI >>>>>>>>
7147 19:23:04.047822 [ANA_INIT] MIDPI <<<<<<<<
7148 19:23:04.051292 [ANA_INIT] DLL >>>>>>>>
7149 19:23:04.054905 [ANA_INIT] DLL <<<<<<<<
7150 19:23:04.054984 [ANA_INIT] flow end
7151 19:23:04.061219 ============ LP4 DIFF to SE enter ============
7152 19:23:04.064406 ============ LP4 DIFF to SE exit ============
7153 19:23:04.067739 [ANA_INIT] <<<<<<<<<<<<<
7154 19:23:04.071070 [Flow] Enable top DCM control >>>>>
7155 19:23:04.074621 [Flow] Enable top DCM control <<<<<
7156 19:23:04.077437 Enable DLL master slave shuffle
7157 19:23:04.080865 ==============================================================
7158 19:23:04.084317 Gating Mode config
7159 19:23:04.087371 ==============================================================
7160 19:23:04.090910 Config description:
7161 19:23:04.100488 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7162 19:23:04.107155 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7163 19:23:04.110590 SELPH_MODE 0: By rank 1: By Phase
7164 19:23:04.117407 ==============================================================
7165 19:23:04.120380 GAT_TRACK_EN = 1
7166 19:23:04.123972 RX_GATING_MODE = 2
7167 19:23:04.126780 RX_GATING_TRACK_MODE = 2
7168 19:23:04.130491 SELPH_MODE = 1
7169 19:23:04.133917 PICG_EARLY_EN = 1
7170 19:23:04.136759 VALID_LAT_VALUE = 1
7171 19:23:04.140395 ==============================================================
7172 19:23:04.143529 Enter into Gating configuration >>>>
7173 19:23:04.147304 Exit from Gating configuration <<<<
7174 19:23:04.150271 Enter into DVFS_PRE_config >>>>>
7175 19:23:04.163412 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7176 19:23:04.163496 Exit from DVFS_PRE_config <<<<<
7177 19:23:04.166963 Enter into PICG configuration >>>>
7178 19:23:04.170346 Exit from PICG configuration <<<<
7179 19:23:04.173092 [RX_INPUT] configuration >>>>>
7180 19:23:04.176576 [RX_INPUT] configuration <<<<<
7181 19:23:04.183072 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7182 19:23:04.186784 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7183 19:23:04.193191 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7184 19:23:04.199566 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7185 19:23:04.206314 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7186 19:23:04.213111 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7187 19:23:04.216782 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7188 19:23:04.219726 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7189 19:23:04.222781 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7190 19:23:04.229771 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7191 19:23:04.232955 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7192 19:23:04.236294 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7193 19:23:04.239552 ===================================
7194 19:23:04.242803 LPDDR4 DRAM CONFIGURATION
7195 19:23:04.246443 ===================================
7196 19:23:04.249329 EX_ROW_EN[0] = 0x0
7197 19:23:04.249437 EX_ROW_EN[1] = 0x0
7198 19:23:04.252876 LP4Y_EN = 0x0
7199 19:23:04.252987 WORK_FSP = 0x1
7200 19:23:04.255910 WL = 0x5
7201 19:23:04.256007 RL = 0x5
7202 19:23:04.259644 BL = 0x2
7203 19:23:04.259744 RPST = 0x0
7204 19:23:04.262613 RD_PRE = 0x0
7205 19:23:04.262708 WR_PRE = 0x1
7206 19:23:04.266174 WR_PST = 0x1
7207 19:23:04.266246 DBI_WR = 0x0
7208 19:23:04.269384 DBI_RD = 0x0
7209 19:23:04.269483 OTF = 0x1
7210 19:23:04.272641 ===================================
7211 19:23:04.279346 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7212 19:23:04.282339 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7213 19:23:04.286022 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7214 19:23:04.289040 ===================================
7215 19:23:04.292555 LPDDR4 DRAM CONFIGURATION
7216 19:23:04.295993 ===================================
7217 19:23:04.299271 EX_ROW_EN[0] = 0x10
7218 19:23:04.299373 EX_ROW_EN[1] = 0x0
7219 19:23:04.302256 LP4Y_EN = 0x0
7220 19:23:04.302331 WORK_FSP = 0x1
7221 19:23:04.305754 WL = 0x5
7222 19:23:04.305822 RL = 0x5
7223 19:23:04.308809 BL = 0x2
7224 19:23:04.308909 RPST = 0x0
7225 19:23:04.312376 RD_PRE = 0x0
7226 19:23:04.312446 WR_PRE = 0x1
7227 19:23:04.315615 WR_PST = 0x1
7228 19:23:04.315686 DBI_WR = 0x0
7229 19:23:04.318992 DBI_RD = 0x0
7230 19:23:04.319060 OTF = 0x1
7231 19:23:04.322339 ===================================
7232 19:23:04.328466 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7233 19:23:04.328567 ==
7234 19:23:04.331988 Dram Type= 6, Freq= 0, CH_0, rank 0
7235 19:23:04.338638 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7236 19:23:04.338719 ==
7237 19:23:04.338780 [Duty_Offset_Calibration]
7238 19:23:04.342242 B0:2 B1:0 CA:3
7239 19:23:04.342310
7240 19:23:04.344958 [DutyScan_Calibration_Flow] k_type=0
7241 19:23:04.354859
7242 19:23:04.354961 ==CLK 0==
7243 19:23:04.357938 Final CLK duty delay cell = 0
7244 19:23:04.361315 [0] MAX Duty = 5062%(X100), DQS PI = 22
7245 19:23:04.364386 [0] MIN Duty = 4907%(X100), DQS PI = 6
7246 19:23:04.364484 [0] AVG Duty = 4984%(X100)
7247 19:23:04.367911
7248 19:23:04.371332 CH0 CLK Duty spec in!! Max-Min= 155%
7249 19:23:04.374312 [DutyScan_Calibration_Flow] ====Done====
7250 19:23:04.374381
7251 19:23:04.377779 [DutyScan_Calibration_Flow] k_type=1
7252 19:23:04.394818
7253 19:23:04.394897 ==DQS 0 ==
7254 19:23:04.397881 Final DQS duty delay cell = 0
7255 19:23:04.400851 [0] MAX Duty = 5125%(X100), DQS PI = 30
7256 19:23:04.404396 [0] MIN Duty = 4875%(X100), DQS PI = 48
7257 19:23:04.404476 [0] AVG Duty = 5000%(X100)
7258 19:23:04.407967
7259 19:23:04.408071 ==DQS 1 ==
7260 19:23:04.411506 Final DQS duty delay cell = 0
7261 19:23:04.414423 [0] MAX Duty = 5156%(X100), DQS PI = 32
7262 19:23:04.417910 [0] MIN Duty = 5031%(X100), DQS PI = 10
7263 19:23:04.417982 [0] AVG Duty = 5093%(X100)
7264 19:23:04.420988
7265 19:23:04.424089 CH0 DQS 0 Duty spec in!! Max-Min= 250%
7266 19:23:04.424265
7267 19:23:04.428117 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7268 19:23:04.431795 [DutyScan_Calibration_Flow] ====Done====
7269 19:23:04.431874
7270 19:23:04.434368 [DutyScan_Calibration_Flow] k_type=3
7271 19:23:04.452334
7272 19:23:04.452420 ==DQM 0 ==
7273 19:23:04.455810 Final DQM duty delay cell = 0
7274 19:23:04.459111 [0] MAX Duty = 5156%(X100), DQS PI = 32
7275 19:23:04.462262 [0] MIN Duty = 4844%(X100), DQS PI = 48
7276 19:23:04.465545 [0] AVG Duty = 5000%(X100)
7277 19:23:04.465642
7278 19:23:04.465705 ==DQM 1 ==
7279 19:23:04.469297 Final DQM duty delay cell = 4
7280 19:23:04.472067 [4] MAX Duty = 5187%(X100), DQS PI = 60
7281 19:23:04.475560 [4] MIN Duty = 5000%(X100), DQS PI = 12
7282 19:23:04.479194 [4] AVG Duty = 5093%(X100)
7283 19:23:04.479274
7284 19:23:04.482108 CH0 DQM 0 Duty spec in!! Max-Min= 312%
7285 19:23:04.482178
7286 19:23:04.485736 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7287 19:23:04.488711 [DutyScan_Calibration_Flow] ====Done====
7288 19:23:04.488781
7289 19:23:04.491921 [DutyScan_Calibration_Flow] k_type=2
7290 19:23:04.509012
7291 19:23:04.509091 ==DQ 0 ==
7292 19:23:04.512372 Final DQ duty delay cell = -4
7293 19:23:04.515726 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7294 19:23:04.518754 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7295 19:23:04.522367 [-4] AVG Duty = 4938%(X100)
7296 19:23:04.522449
7297 19:23:04.522512 ==DQ 1 ==
7298 19:23:04.525413 Final DQ duty delay cell = 0
7299 19:23:04.528770 [0] MAX Duty = 5156%(X100), DQS PI = 60
7300 19:23:04.532132 [0] MIN Duty = 5000%(X100), DQS PI = 16
7301 19:23:04.532213 [0] AVG Duty = 5078%(X100)
7302 19:23:04.535620
7303 19:23:04.539182 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7304 19:23:04.539261
7305 19:23:04.542549 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7306 19:23:04.545251 [DutyScan_Calibration_Flow] ====Done====
7307 19:23:04.545329 ==
7308 19:23:04.549018 Dram Type= 6, Freq= 0, CH_1, rank 0
7309 19:23:04.552011 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7310 19:23:04.552110 ==
7311 19:23:04.555107 [Duty_Offset_Calibration]
7312 19:23:04.555202 B0:1 B1:-2 CA:0
7313 19:23:04.555288
7314 19:23:04.558734 [DutyScan_Calibration_Flow] k_type=0
7315 19:23:04.569699
7316 19:23:04.569777 ==CLK 0==
7317 19:23:04.572702 Final CLK duty delay cell = 0
7318 19:23:04.576290 [0] MAX Duty = 5062%(X100), DQS PI = 20
7319 19:23:04.579301 [0] MIN Duty = 4844%(X100), DQS PI = 0
7320 19:23:04.579380 [0] AVG Duty = 4953%(X100)
7321 19:23:04.582796
7322 19:23:04.585859 CH1 CLK Duty spec in!! Max-Min= 218%
7323 19:23:04.589448 [DutyScan_Calibration_Flow] ====Done====
7324 19:23:04.589550
7325 19:23:04.592558 [DutyScan_Calibration_Flow] k_type=1
7326 19:23:04.609098
7327 19:23:04.609177 ==DQS 0 ==
7328 19:23:04.612737 Final DQS duty delay cell = 0
7329 19:23:04.615570 [0] MAX Duty = 5187%(X100), DQS PI = 24
7330 19:23:04.618988 [0] MIN Duty = 5031%(X100), DQS PI = 54
7331 19:23:04.622558 [0] AVG Duty = 5109%(X100)
7332 19:23:04.622637
7333 19:23:04.622699 ==DQS 1 ==
7334 19:23:04.625467 Final DQS duty delay cell = 0
7335 19:23:04.629131 [0] MAX Duty = 5093%(X100), DQS PI = 60
7336 19:23:04.632057 [0] MIN Duty = 4844%(X100), DQS PI = 24
7337 19:23:04.635530 [0] AVG Duty = 4968%(X100)
7338 19:23:04.635613
7339 19:23:04.638998 CH1 DQS 0 Duty spec in!! Max-Min= 156%
7340 19:23:04.639082
7341 19:23:04.642455 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7342 19:23:04.645418 [DutyScan_Calibration_Flow] ====Done====
7343 19:23:04.645529
7344 19:23:04.648844 [DutyScan_Calibration_Flow] k_type=3
7345 19:23:04.666397
7346 19:23:04.666480 ==DQM 0 ==
7347 19:23:04.669366 Final DQM duty delay cell = 0
7348 19:23:04.672495 [0] MAX Duty = 5031%(X100), DQS PI = 24
7349 19:23:04.675968 [0] MIN Duty = 4813%(X100), DQS PI = 54
7350 19:23:04.679255 [0] AVG Duty = 4922%(X100)
7351 19:23:04.679335
7352 19:23:04.679398 ==DQM 1 ==
7353 19:23:04.682740 Final DQM duty delay cell = 0
7354 19:23:04.686103 [0] MAX Duty = 5062%(X100), DQS PI = 34
7355 19:23:04.689392 [0] MIN Duty = 4875%(X100), DQS PI = 24
7356 19:23:04.692715 [0] AVG Duty = 4968%(X100)
7357 19:23:04.692795
7358 19:23:04.695770 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7359 19:23:04.695841
7360 19:23:04.698858 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7361 19:23:04.702333 [DutyScan_Calibration_Flow] ====Done====
7362 19:23:04.702405
7363 19:23:04.705433 [DutyScan_Calibration_Flow] k_type=2
7364 19:23:04.722819
7365 19:23:04.722897 ==DQ 0 ==
7366 19:23:04.726511 Final DQ duty delay cell = 0
7367 19:23:04.729423 [0] MAX Duty = 5093%(X100), DQS PI = 22
7368 19:23:04.733099 [0] MIN Duty = 4907%(X100), DQS PI = 46
7369 19:23:04.736041 [0] AVG Duty = 5000%(X100)
7370 19:23:04.736134
7371 19:23:04.736220 ==DQ 1 ==
7372 19:23:04.739574 Final DQ duty delay cell = 0
7373 19:23:04.742862 [0] MAX Duty = 5125%(X100), DQS PI = 34
7374 19:23:04.746305 [0] MIN Duty = 4969%(X100), DQS PI = 24
7375 19:23:04.746373 [0] AVG Duty = 5047%(X100)
7376 19:23:04.749451
7377 19:23:04.753103 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7378 19:23:04.753185
7379 19:23:04.756062 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7380 19:23:04.759451 [DutyScan_Calibration_Flow] ====Done====
7381 19:23:04.762526 nWR fixed to 30
7382 19:23:04.762627 [ModeRegInit_LP4] CH0 RK0
7383 19:23:04.765961 [ModeRegInit_LP4] CH0 RK1
7384 19:23:04.769385 [ModeRegInit_LP4] CH1 RK0
7385 19:23:04.772692 [ModeRegInit_LP4] CH1 RK1
7386 19:23:04.772760 match AC timing 5
7387 19:23:04.779400 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7388 19:23:04.783086 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7389 19:23:04.785846 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7390 19:23:04.792716 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7391 19:23:04.796171 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7392 19:23:04.796273 [MiockJmeterHQA]
7393 19:23:04.796337
7394 19:23:04.799431 [DramcMiockJmeter] u1RxGatingPI = 0
7395 19:23:04.802551 0 : 4365, 4138
7396 19:23:04.802631 4 : 4253, 4026
7397 19:23:04.805988 8 : 4253, 4027
7398 19:23:04.806076 12 : 4252, 4027
7399 19:23:04.806160 16 : 4252, 4026
7400 19:23:04.809393 20 : 4363, 4138
7401 19:23:04.809523 24 : 4253, 4027
7402 19:23:04.812411 28 : 4363, 4137
7403 19:23:04.812494 32 : 4252, 4027
7404 19:23:04.816058 36 : 4252, 4026
7405 19:23:04.816169 40 : 4253, 4027
7406 19:23:04.816232 44 : 4255, 4030
7407 19:23:04.819486 48 : 4252, 4026
7408 19:23:04.819565 52 : 4250, 4026
7409 19:23:04.822316 56 : 4365, 4140
7410 19:23:04.822396 60 : 4250, 4027
7411 19:23:04.826178 64 : 4252, 4030
7412 19:23:04.826258 68 : 4250, 4027
7413 19:23:04.829388 72 : 4360, 4138
7414 19:23:04.829494 76 : 4250, 4027
7415 19:23:04.829653 80 : 4360, 4137
7416 19:23:04.832388 84 : 4250, 4027
7417 19:23:04.832467 88 : 4250, 4027
7418 19:23:04.836045 92 : 4250, 4027
7419 19:23:04.836126 96 : 4252, 4029
7420 19:23:04.838988 100 : 4360, 4137
7421 19:23:04.839074 104 : 4250, 3368
7422 19:23:04.842764 108 : 4250, 0
7423 19:23:04.842843 112 : 4250, 0
7424 19:23:04.842907 116 : 4361, 0
7425 19:23:04.845532 120 : 4250, 0
7426 19:23:04.845629 124 : 4253, 0
7427 19:23:04.845693 128 : 4250, 0
7428 19:23:04.849333 132 : 4252, 0
7429 19:23:04.849444 136 : 4363, 0
7430 19:23:04.852368 140 : 4250, 0
7431 19:23:04.852511 144 : 4249, 0
7432 19:23:04.852644 148 : 4253, 0
7433 19:23:04.855955 152 : 4361, 0
7434 19:23:04.856105 156 : 4361, 0
7435 19:23:04.858822 160 : 4250, 0
7436 19:23:04.858921 164 : 4250, 0
7437 19:23:04.858990 168 : 4250, 0
7438 19:23:04.862068 172 : 4252, 0
7439 19:23:04.862202 176 : 4250, 0
7440 19:23:04.865778 180 : 4250, 0
7441 19:23:04.865918 184 : 4253, 0
7442 19:23:04.866011 188 : 4360, 0
7443 19:23:04.868618 192 : 4250, 0
7444 19:23:04.868741 196 : 4250, 0
7445 19:23:04.872235 200 : 4250, 0
7446 19:23:04.872341 204 : 4361, 0
7447 19:23:04.872434 208 : 4360, 0
7448 19:23:04.875319 212 : 4250, 0
7449 19:23:04.875457 216 : 4360, 0
7450 19:23:04.875551 220 : 4361, 0
7451 19:23:04.878835 224 : 4250, 0
7452 19:23:04.878958 228 : 4250, 0
7453 19:23:04.882708 232 : 4250, 0
7454 19:23:04.882817 236 : 4249, 1108
7455 19:23:04.885604 240 : 4250, 4026
7456 19:23:04.885709 244 : 4362, 4140
7457 19:23:04.888814 248 : 4360, 4137
7458 19:23:04.888951 252 : 4248, 4024
7459 19:23:04.889075 256 : 4362, 4140
7460 19:23:04.892117 260 : 4360, 4137
7461 19:23:04.892220 264 : 4250, 4027
7462 19:23:04.895535 268 : 4250, 4027
7463 19:23:04.895638 272 : 4253, 4029
7464 19:23:04.898715 276 : 4250, 4026
7465 19:23:04.898824 280 : 4250, 4027
7466 19:23:04.902290 284 : 4250, 4027
7467 19:23:04.902371 288 : 4252, 4029
7468 19:23:04.905700 292 : 4250, 4026
7469 19:23:04.905782 296 : 4361, 4137
7470 19:23:04.908866 300 : 4360, 4138
7471 19:23:04.909028 304 : 4249, 4027
7472 19:23:04.911799 308 : 4362, 4140
7473 19:23:04.911909 312 : 4250, 4026
7474 19:23:04.912040 316 : 4250, 4027
7475 19:23:04.915253 320 : 4250, 4027
7476 19:23:04.915391 324 : 4253, 4029
7477 19:23:04.918460 328 : 4250, 4026
7478 19:23:04.918540 332 : 4250, 4027
7479 19:23:04.922004 336 : 4250, 4027
7480 19:23:04.922085 340 : 4252, 4029
7481 19:23:04.924973 344 : 4250, 4026
7482 19:23:04.925103 348 : 4361, 4137
7483 19:23:04.928527 352 : 4360, 4116
7484 19:23:04.928637 356 : 4249, 2799
7485 19:23:04.931744 360 : 4362, 1
7486 19:23:04.931854
7487 19:23:04.931947 MIOCK jitter meter ch=0
7488 19:23:04.932044
7489 19:23:04.934868 1T = (360-108) = 252 dly cells
7490 19:23:04.942040 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7491 19:23:04.942122 ==
7492 19:23:04.945064 Dram Type= 6, Freq= 0, CH_0, rank 0
7493 19:23:04.948290 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7494 19:23:04.948398 ==
7495 19:23:04.955285 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7496 19:23:04.958529 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7497 19:23:04.961735 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7498 19:23:04.968143 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7499 19:23:04.977762 [CA 0] Center 44 (14~75) winsize 62
7500 19:23:04.981368 [CA 1] Center 43 (13~74) winsize 62
7501 19:23:04.984629 [CA 2] Center 40 (11~69) winsize 59
7502 19:23:04.988079 [CA 3] Center 39 (10~69) winsize 60
7503 19:23:04.991442 [CA 4] Center 37 (8~67) winsize 60
7504 19:23:04.994820 [CA 5] Center 37 (8~66) winsize 59
7505 19:23:04.994920
7506 19:23:04.998162 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7507 19:23:04.998246
7508 19:23:05.001244 [CATrainingPosCal] consider 1 rank data
7509 19:23:05.004553 u2DelayCellTimex100 = 258/100 ps
7510 19:23:05.011056 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7511 19:23:05.014363 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7512 19:23:05.018316 CA2 delay=40 (11~69),Diff = 3 PI (11 cell)
7513 19:23:05.020866 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7514 19:23:05.024299 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7515 19:23:05.027515 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
7516 19:23:05.027616
7517 19:23:05.031319 CA PerBit enable=1, Macro0, CA PI delay=37
7518 19:23:05.031418
7519 19:23:05.034200 [CBTSetCACLKResult] CA Dly = 37
7520 19:23:05.037562 CS Dly: 11 (0~42)
7521 19:23:05.041158 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7522 19:23:05.044301 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7523 19:23:05.044402 ==
7524 19:23:05.047963 Dram Type= 6, Freq= 0, CH_0, rank 1
7525 19:23:05.054540 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7526 19:23:05.054625 ==
7527 19:23:05.057619 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7528 19:23:05.064174 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7529 19:23:05.067088 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7530 19:23:05.074174 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7531 19:23:05.082136 [CA 0] Center 44 (14~75) winsize 62
7532 19:23:05.085245 [CA 1] Center 43 (13~74) winsize 62
7533 19:23:05.088272 [CA 2] Center 39 (10~69) winsize 60
7534 19:23:05.091486 [CA 3] Center 39 (10~69) winsize 60
7535 19:23:05.095199 [CA 4] Center 37 (8~67) winsize 60
7536 19:23:05.098379 [CA 5] Center 36 (7~66) winsize 60
7537 19:23:05.098474
7538 19:23:05.101484 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7539 19:23:05.101586
7540 19:23:05.105049 [CATrainingPosCal] consider 2 rank data
7541 19:23:05.108115 u2DelayCellTimex100 = 258/100 ps
7542 19:23:05.114806 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7543 19:23:05.118336 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7544 19:23:05.121656 CA2 delay=40 (11~69),Diff = 3 PI (11 cell)
7545 19:23:05.125138 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7546 19:23:05.128287 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7547 19:23:05.131886 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
7548 19:23:05.131987
7549 19:23:05.134635 CA PerBit enable=1, Macro0, CA PI delay=37
7550 19:23:05.134704
7551 19:23:05.138406 [CBTSetCACLKResult] CA Dly = 37
7552 19:23:05.141769 CS Dly: 11 (0~43)
7553 19:23:05.144957 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7554 19:23:05.148336 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7555 19:23:05.148453
7556 19:23:05.151447 ----->DramcWriteLeveling(PI) begin...
7557 19:23:05.151527 ==
7558 19:23:05.154692 Dram Type= 6, Freq= 0, CH_0, rank 0
7559 19:23:05.161227 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7560 19:23:05.161337 ==
7561 19:23:05.164790 Write leveling (Byte 0): 33 => 33
7562 19:23:05.168264 Write leveling (Byte 1): 29 => 29
7563 19:23:05.168372 DramcWriteLeveling(PI) end<-----
7564 19:23:05.168495
7565 19:23:05.171616 ==
7566 19:23:05.174905 Dram Type= 6, Freq= 0, CH_0, rank 0
7567 19:23:05.178449 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7568 19:23:05.178531 ==
7569 19:23:05.181387 [Gating] SW mode calibration
7570 19:23:05.187855 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7571 19:23:05.191504 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7572 19:23:05.197504 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7573 19:23:05.201237 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7574 19:23:05.204205 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7575 19:23:05.210956 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7576 19:23:05.214517 1 4 16 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
7577 19:23:05.217764 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7578 19:23:05.224305 1 4 24 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
7579 19:23:05.227851 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7580 19:23:05.230690 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7581 19:23:05.237331 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7582 19:23:05.240971 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7583 19:23:05.244408 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7584 19:23:05.250816 1 5 16 | B1->B0 | 3434 2828 | 1 0 | (1 1) (1 0)
7585 19:23:05.254091 1 5 20 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
7586 19:23:05.257229 1 5 24 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
7587 19:23:05.264237 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7588 19:23:05.267101 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7589 19:23:05.270425 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7590 19:23:05.277264 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7591 19:23:05.280714 1 6 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7592 19:23:05.283985 1 6 16 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
7593 19:23:05.290636 1 6 20 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
7594 19:23:05.294263 1 6 24 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
7595 19:23:05.297295 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7596 19:23:05.303590 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7597 19:23:05.307331 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7598 19:23:05.310236 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7599 19:23:05.317052 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7600 19:23:05.320251 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7601 19:23:05.324000 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7602 19:23:05.330435 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7603 19:23:05.333794 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7604 19:23:05.336667 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7605 19:23:05.343443 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7606 19:23:05.347005 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7607 19:23:05.349982 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7608 19:23:05.356753 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7609 19:23:05.360532 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7610 19:23:05.363511 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7611 19:23:05.366707 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7612 19:23:05.373247 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7613 19:23:05.376639 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7614 19:23:05.379903 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7615 19:23:05.386622 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 19:23:05.390258 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7617 19:23:05.393422 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7618 19:23:05.396786 Total UI for P1: 0, mck2ui 16
7619 19:23:05.400034 best dqsien dly found for B0: ( 1, 9, 16)
7620 19:23:05.407085 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7621 19:23:05.410163 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7622 19:23:05.413454 1 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7623 19:23:05.416551 Total UI for P1: 0, mck2ui 16
7624 19:23:05.420178 best dqsien dly found for B1: ( 1, 9, 24)
7625 19:23:05.423339 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7626 19:23:05.426969 best DQS1 dly(MCK, UI, PI) = (1, 9, 24)
7627 19:23:05.427061
7628 19:23:05.433698 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7629 19:23:05.436468 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 24)
7630 19:23:05.440069 [Gating] SW calibration Done
7631 19:23:05.440164 ==
7632 19:23:05.443457 Dram Type= 6, Freq= 0, CH_0, rank 0
7633 19:23:05.446688 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7634 19:23:05.446770 ==
7635 19:23:05.446838 RX Vref Scan: 0
7636 19:23:05.446899
7637 19:23:05.450227 RX Vref 0 -> 0, step: 1
7638 19:23:05.450307
7639 19:23:05.453318 RX Delay 0 -> 252, step: 8
7640 19:23:05.456854 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7641 19:23:05.459969 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
7642 19:23:05.463498 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7643 19:23:05.469711 iDelay=200, Bit 3, Center 119 (64 ~ 175) 112
7644 19:23:05.473252 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
7645 19:23:05.476646 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
7646 19:23:05.479818 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
7647 19:23:05.482885 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
7648 19:23:05.489389 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7649 19:23:05.492947 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7650 19:23:05.496054 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7651 19:23:05.499778 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7652 19:23:05.506166 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
7653 19:23:05.509390 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7654 19:23:05.512966 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7655 19:23:05.515782 iDelay=200, Bit 15, Center 127 (72 ~ 183) 112
7656 19:23:05.515884 ==
7657 19:23:05.519598 Dram Type= 6, Freq= 0, CH_0, rank 0
7658 19:23:05.525994 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7659 19:23:05.526073 ==
7660 19:23:05.526146 DQS Delay:
7661 19:23:05.526206 DQS0 = 0, DQS1 = 0
7662 19:23:05.529216 DQM Delay:
7663 19:23:05.529320 DQM0 = 128, DQM1 = 123
7664 19:23:05.532485 DQ Delay:
7665 19:23:05.536351 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =119
7666 19:23:05.539371 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =143
7667 19:23:05.542273 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
7668 19:23:05.545967 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =127
7669 19:23:05.546061
7670 19:23:05.546163
7671 19:23:05.546252 ==
7672 19:23:05.548988 Dram Type= 6, Freq= 0, CH_0, rank 0
7673 19:23:05.552247 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7674 19:23:05.555702 ==
7675 19:23:05.555788
7676 19:23:05.555854
7677 19:23:05.555916 TX Vref Scan disable
7678 19:23:05.558732 == TX Byte 0 ==
7679 19:23:05.562419 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7680 19:23:05.565506 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7681 19:23:05.569194 == TX Byte 1 ==
7682 19:23:05.572138 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7683 19:23:05.575857 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7684 19:23:05.578891 ==
7685 19:23:05.581987 Dram Type= 6, Freq= 0, CH_0, rank 0
7686 19:23:05.585299 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7687 19:23:05.585407 ==
7688 19:23:05.598049
7689 19:23:05.601119 TX Vref early break, caculate TX vref
7690 19:23:05.604787 TX Vref=16, minBit 4, minWin=21, winSum=354
7691 19:23:05.607703 TX Vref=18, minBit 0, minWin=22, winSum=365
7692 19:23:05.611530 TX Vref=20, minBit 0, minWin=23, winSum=380
7693 19:23:05.614636 TX Vref=22, minBit 0, minWin=23, winSum=387
7694 19:23:05.618247 TX Vref=24, minBit 0, minWin=24, winSum=394
7695 19:23:05.624306 TX Vref=26, minBit 2, minWin=24, winSum=405
7696 19:23:05.627880 TX Vref=28, minBit 0, minWin=24, winSum=406
7697 19:23:05.630948 TX Vref=30, minBit 0, minWin=24, winSum=395
7698 19:23:05.634438 TX Vref=32, minBit 9, minWin=23, winSum=387
7699 19:23:05.637525 TX Vref=34, minBit 6, minWin=23, winSum=380
7700 19:23:05.644465 [TxChooseVref] Worse bit 0, Min win 24, Win sum 406, Final Vref 28
7701 19:23:05.644570
7702 19:23:05.647776 Final TX Range 0 Vref 28
7703 19:23:05.647889
7704 19:23:05.647980 ==
7705 19:23:05.650809 Dram Type= 6, Freq= 0, CH_0, rank 0
7706 19:23:05.654427 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7707 19:23:05.654513 ==
7708 19:23:05.654581
7709 19:23:05.654642
7710 19:23:05.657695 TX Vref Scan disable
7711 19:23:05.663959 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7712 19:23:05.664046 == TX Byte 0 ==
7713 19:23:05.667391 u2DelayCellOfst[0]=15 cells (4 PI)
7714 19:23:05.670965 u2DelayCellOfst[1]=22 cells (6 PI)
7715 19:23:05.673957 u2DelayCellOfst[2]=15 cells (4 PI)
7716 19:23:05.677166 u2DelayCellOfst[3]=15 cells (4 PI)
7717 19:23:05.680856 u2DelayCellOfst[4]=11 cells (3 PI)
7718 19:23:05.684563 u2DelayCellOfst[5]=0 cells (0 PI)
7719 19:23:05.687569 u2DelayCellOfst[6]=22 cells (6 PI)
7720 19:23:05.691043 u2DelayCellOfst[7]=22 cells (6 PI)
7721 19:23:05.693755 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7722 19:23:05.697141 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7723 19:23:05.700618 == TX Byte 1 ==
7724 19:23:05.704205 u2DelayCellOfst[8]=0 cells (0 PI)
7725 19:23:05.704288 u2DelayCellOfst[9]=3 cells (1 PI)
7726 19:23:05.707240 u2DelayCellOfst[10]=7 cells (2 PI)
7727 19:23:05.710276 u2DelayCellOfst[11]=7 cells (2 PI)
7728 19:23:05.713970 u2DelayCellOfst[12]=11 cells (3 PI)
7729 19:23:05.717012 u2DelayCellOfst[13]=11 cells (3 PI)
7730 19:23:05.720144 u2DelayCellOfst[14]=15 cells (4 PI)
7731 19:23:05.723813 u2DelayCellOfst[15]=11 cells (3 PI)
7732 19:23:05.726999 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7733 19:23:05.733653 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7734 19:23:05.733735 DramC Write-DBI on
7735 19:23:05.733821 ==
7736 19:23:05.736703 Dram Type= 6, Freq= 0, CH_0, rank 0
7737 19:23:05.743542 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7738 19:23:05.743626 ==
7739 19:23:05.743691
7740 19:23:05.743752
7741 19:23:05.743810 TX Vref Scan disable
7742 19:23:05.747797 == TX Byte 0 ==
7743 19:23:05.750818 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7744 19:23:05.753866 == TX Byte 1 ==
7745 19:23:05.757374 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7746 19:23:05.760557 DramC Write-DBI off
7747 19:23:05.760650
7748 19:23:05.760719 [DATLAT]
7749 19:23:05.760781 Freq=1600, CH0 RK0
7750 19:23:05.760841
7751 19:23:05.764051 DATLAT Default: 0xf
7752 19:23:05.764133 0, 0xFFFF, sum = 0
7753 19:23:05.767599 1, 0xFFFF, sum = 0
7754 19:23:05.770984 2, 0xFFFF, sum = 0
7755 19:23:05.771093 3, 0xFFFF, sum = 0
7756 19:23:05.773755 4, 0xFFFF, sum = 0
7757 19:23:05.773834 5, 0xFFFF, sum = 0
7758 19:23:05.777272 6, 0xFFFF, sum = 0
7759 19:23:05.777382 7, 0xFFFF, sum = 0
7760 19:23:05.780694 8, 0xFFFF, sum = 0
7761 19:23:05.780791 9, 0xFFFF, sum = 0
7762 19:23:05.783952 10, 0xFFFF, sum = 0
7763 19:23:05.784035 11, 0xFFFF, sum = 0
7764 19:23:05.787454 12, 0xFFFF, sum = 0
7765 19:23:05.787553 13, 0xEFFF, sum = 0
7766 19:23:05.790305 14, 0x0, sum = 1
7767 19:23:05.790389 15, 0x0, sum = 2
7768 19:23:05.793960 16, 0x0, sum = 3
7769 19:23:05.794044 17, 0x0, sum = 4
7770 19:23:05.797054 best_step = 15
7771 19:23:05.797138
7772 19:23:05.797203 ==
7773 19:23:05.800635 Dram Type= 6, Freq= 0, CH_0, rank 0
7774 19:23:05.803899 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7775 19:23:05.804012 ==
7776 19:23:05.807077 RX Vref Scan: 1
7777 19:23:05.807189
7778 19:23:05.807291 Set Vref Range= 24 -> 127
7779 19:23:05.807381
7780 19:23:05.810564 RX Vref 24 -> 127, step: 1
7781 19:23:05.810671
7782 19:23:05.813735 RX Delay 11 -> 252, step: 4
7783 19:23:05.813812
7784 19:23:05.817368 Set Vref, RX VrefLevel [Byte0]: 24
7785 19:23:05.820280 [Byte1]: 24
7786 19:23:05.820378
7787 19:23:05.823926 Set Vref, RX VrefLevel [Byte0]: 25
7788 19:23:05.826906 [Byte1]: 25
7789 19:23:05.830158
7790 19:23:05.830234 Set Vref, RX VrefLevel [Byte0]: 26
7791 19:23:05.833757 [Byte1]: 26
7792 19:23:05.837937
7793 19:23:05.838019 Set Vref, RX VrefLevel [Byte0]: 27
7794 19:23:05.841474 [Byte1]: 27
7795 19:23:05.845369
7796 19:23:05.845477 Set Vref, RX VrefLevel [Byte0]: 28
7797 19:23:05.848708 [Byte1]: 28
7798 19:23:05.853078
7799 19:23:05.853161 Set Vref, RX VrefLevel [Byte0]: 29
7800 19:23:05.856272 [Byte1]: 29
7801 19:23:05.860605
7802 19:23:05.860690 Set Vref, RX VrefLevel [Byte0]: 30
7803 19:23:05.864303 [Byte1]: 30
7804 19:23:05.868420
7805 19:23:05.868502 Set Vref, RX VrefLevel [Byte0]: 31
7806 19:23:05.871433 [Byte1]: 31
7807 19:23:05.876392
7808 19:23:05.876500 Set Vref, RX VrefLevel [Byte0]: 32
7809 19:23:05.879412 [Byte1]: 32
7810 19:23:05.883565
7811 19:23:05.883647 Set Vref, RX VrefLevel [Byte0]: 33
7812 19:23:05.886920 [Byte1]: 33
7813 19:23:05.891325
7814 19:23:05.891407 Set Vref, RX VrefLevel [Byte0]: 34
7815 19:23:05.894500 [Byte1]: 34
7816 19:23:05.898787
7817 19:23:05.898895 Set Vref, RX VrefLevel [Byte0]: 35
7818 19:23:05.901878 [Byte1]: 35
7819 19:23:05.906500
7820 19:23:05.906607 Set Vref, RX VrefLevel [Byte0]: 36
7821 19:23:05.910039 [Byte1]: 36
7822 19:23:05.913863
7823 19:23:05.913945 Set Vref, RX VrefLevel [Byte0]: 37
7824 19:23:05.917614 [Byte1]: 37
7825 19:23:05.921716
7826 19:23:05.921798 Set Vref, RX VrefLevel [Byte0]: 38
7827 19:23:05.924858 [Byte1]: 38
7828 19:23:05.929063
7829 19:23:05.929164 Set Vref, RX VrefLevel [Byte0]: 39
7830 19:23:05.932918 [Byte1]: 39
7831 19:23:05.936536
7832 19:23:05.936611 Set Vref, RX VrefLevel [Byte0]: 40
7833 19:23:05.940058 [Byte1]: 40
7834 19:23:05.944242
7835 19:23:05.944316 Set Vref, RX VrefLevel [Byte0]: 41
7836 19:23:05.947811 [Byte1]: 41
7837 19:23:05.951928
7838 19:23:05.952027 Set Vref, RX VrefLevel [Byte0]: 42
7839 19:23:05.955398 [Byte1]: 42
7840 19:23:05.959640
7841 19:23:05.959744 Set Vref, RX VrefLevel [Byte0]: 43
7842 19:23:05.963185 [Byte1]: 43
7843 19:23:05.967419
7844 19:23:05.967501 Set Vref, RX VrefLevel [Byte0]: 44
7845 19:23:05.970481 [Byte1]: 44
7846 19:23:05.975097
7847 19:23:05.975179 Set Vref, RX VrefLevel [Byte0]: 45
7848 19:23:05.978289 [Byte1]: 45
7849 19:23:05.982734
7850 19:23:05.982816 Set Vref, RX VrefLevel [Byte0]: 46
7851 19:23:05.986088 [Byte1]: 46
7852 19:23:05.990289
7853 19:23:05.990371 Set Vref, RX VrefLevel [Byte0]: 47
7854 19:23:05.993463 [Byte1]: 47
7855 19:23:05.997827
7856 19:23:05.997912 Set Vref, RX VrefLevel [Byte0]: 48
7857 19:23:06.000755 [Byte1]: 48
7858 19:23:06.005566
7859 19:23:06.005649 Set Vref, RX VrefLevel [Byte0]: 49
7860 19:23:06.009039 [Byte1]: 49
7861 19:23:06.013400
7862 19:23:06.013482 Set Vref, RX VrefLevel [Byte0]: 50
7863 19:23:06.016008 [Byte1]: 50
7864 19:23:06.020663
7865 19:23:06.020745 Set Vref, RX VrefLevel [Byte0]: 51
7866 19:23:06.023921 [Byte1]: 51
7867 19:23:06.028302
7868 19:23:06.028385 Set Vref, RX VrefLevel [Byte0]: 52
7869 19:23:06.031494 [Byte1]: 52
7870 19:23:06.035860
7871 19:23:06.035974 Set Vref, RX VrefLevel [Byte0]: 53
7872 19:23:06.039298 [Byte1]: 53
7873 19:23:06.043644
7874 19:23:06.043727 Set Vref, RX VrefLevel [Byte0]: 54
7875 19:23:06.046660 [Byte1]: 54
7876 19:23:06.050962
7877 19:23:06.051044 Set Vref, RX VrefLevel [Byte0]: 55
7878 19:23:06.054483 [Byte1]: 55
7879 19:23:06.058595
7880 19:23:06.058676 Set Vref, RX VrefLevel [Byte0]: 56
7881 19:23:06.061920 [Byte1]: 56
7882 19:23:06.066596
7883 19:23:06.066678 Set Vref, RX VrefLevel [Byte0]: 57
7884 19:23:06.069558 [Byte1]: 57
7885 19:23:06.073992
7886 19:23:06.074074 Set Vref, RX VrefLevel [Byte0]: 58
7887 19:23:06.077003 [Byte1]: 58
7888 19:23:06.081695
7889 19:23:06.081781 Set Vref, RX VrefLevel [Byte0]: 59
7890 19:23:06.084776 [Byte1]: 59
7891 19:23:06.088836
7892 19:23:06.088918 Set Vref, RX VrefLevel [Byte0]: 60
7893 19:23:06.092137 [Byte1]: 60
7894 19:23:06.096539
7895 19:23:06.096649 Set Vref, RX VrefLevel [Byte0]: 61
7896 19:23:06.100040 [Byte1]: 61
7897 19:23:06.104097
7898 19:23:06.104179 Set Vref, RX VrefLevel [Byte0]: 62
7899 19:23:06.107666 [Byte1]: 62
7900 19:23:06.111856
7901 19:23:06.111966 Set Vref, RX VrefLevel [Byte0]: 63
7902 19:23:06.115036 [Byte1]: 63
7903 19:23:06.119347
7904 19:23:06.119455 Set Vref, RX VrefLevel [Byte0]: 64
7905 19:23:06.122989 [Byte1]: 64
7906 19:23:06.127596
7907 19:23:06.127678 Set Vref, RX VrefLevel [Byte0]: 65
7908 19:23:06.130557 [Byte1]: 65
7909 19:23:06.134933
7910 19:23:06.135014 Set Vref, RX VrefLevel [Byte0]: 66
7911 19:23:06.138605 [Byte1]: 66
7912 19:23:06.142407
7913 19:23:06.142489 Set Vref, RX VrefLevel [Byte0]: 67
7914 19:23:06.145860 [Byte1]: 67
7915 19:23:06.150171
7916 19:23:06.150279 Set Vref, RX VrefLevel [Byte0]: 68
7917 19:23:06.153690 [Byte1]: 68
7918 19:23:06.158061
7919 19:23:06.158146 Set Vref, RX VrefLevel [Byte0]: 69
7920 19:23:06.161078 [Byte1]: 69
7921 19:23:06.165324
7922 19:23:06.165435 Set Vref, RX VrefLevel [Byte0]: 70
7923 19:23:06.168301 [Byte1]: 70
7924 19:23:06.172618
7925 19:23:06.172701 Set Vref, RX VrefLevel [Byte0]: 71
7926 19:23:06.176382 [Byte1]: 71
7927 19:23:06.180357
7928 19:23:06.180465 Set Vref, RX VrefLevel [Byte0]: 72
7929 19:23:06.183882 [Byte1]: 72
7930 19:23:06.188376
7931 19:23:06.188479 Set Vref, RX VrefLevel [Byte0]: 73
7932 19:23:06.191371 [Byte1]: 73
7933 19:23:06.195419
7934 19:23:06.195525 Set Vref, RX VrefLevel [Byte0]: 74
7935 19:23:06.198745 [Byte1]: 74
7936 19:23:06.203321
7937 19:23:06.203422 Set Vref, RX VrefLevel [Byte0]: 75
7938 19:23:06.206774 [Byte1]: 75
7939 19:23:06.210681
7940 19:23:06.210751 Set Vref, RX VrefLevel [Byte0]: 76
7941 19:23:06.214081 [Byte1]: 76
7942 19:23:06.218354
7943 19:23:06.218427 Set Vref, RX VrefLevel [Byte0]: 77
7944 19:23:06.222031 [Byte1]: 77
7945 19:23:06.226242
7946 19:23:06.226323 Set Vref, RX VrefLevel [Byte0]: 78
7947 19:23:06.229245 [Byte1]: 78
7948 19:23:06.234260
7949 19:23:06.234368 Set Vref, RX VrefLevel [Byte0]: 79
7950 19:23:06.237262 [Byte1]: 79
7951 19:23:06.241474
7952 19:23:06.241565 Set Vref, RX VrefLevel [Byte0]: 80
7953 19:23:06.244539 [Byte1]: 80
7954 19:23:06.248997
7955 19:23:06.249105 Final RX Vref Byte 0 = 64 to rank0
7956 19:23:06.252242 Final RX Vref Byte 1 = 61 to rank0
7957 19:23:06.255546 Final RX Vref Byte 0 = 64 to rank1
7958 19:23:06.259077 Final RX Vref Byte 1 = 61 to rank1==
7959 19:23:06.262100 Dram Type= 6, Freq= 0, CH_0, rank 0
7960 19:23:06.268926 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7961 19:23:06.269012 ==
7962 19:23:06.269078 DQS Delay:
7963 19:23:06.269139 DQS0 = 0, DQS1 = 0
7964 19:23:06.272062 DQM Delay:
7965 19:23:06.272176 DQM0 = 126, DQM1 = 120
7966 19:23:06.275646 DQ Delay:
7967 19:23:06.279025 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
7968 19:23:06.281962 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =138
7969 19:23:06.285456 DQ8 =112, DQ9 =108, DQ10 =120, DQ11 =114
7970 19:23:06.288613 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =128
7971 19:23:06.288710
7972 19:23:06.288799
7973 19:23:06.288885
7974 19:23:06.292261 [DramC_TX_OE_Calibration] TA2
7975 19:23:06.295353 Original DQ_B0 (3 6) =30, OEN = 27
7976 19:23:06.299011 Original DQ_B1 (3 6) =30, OEN = 27
7977 19:23:06.301991 24, 0x0, End_B0=24 End_B1=24
7978 19:23:06.302074 25, 0x0, End_B0=25 End_B1=25
7979 19:23:06.305420 26, 0x0, End_B0=26 End_B1=26
7980 19:23:06.308436 27, 0x0, End_B0=27 End_B1=27
7981 19:23:06.312197 28, 0x0, End_B0=28 End_B1=28
7982 19:23:06.315118 29, 0x0, End_B0=29 End_B1=29
7983 19:23:06.315202 30, 0x0, End_B0=30 End_B1=30
7984 19:23:06.318555 31, 0x5151, End_B0=30 End_B1=30
7985 19:23:06.322201 Byte0 end_step=30 best_step=27
7986 19:23:06.325173 Byte1 end_step=30 best_step=27
7987 19:23:06.328771 Byte0 TX OE(2T, 0.5T) = (3, 3)
7988 19:23:06.332198 Byte1 TX OE(2T, 0.5T) = (3, 3)
7989 19:23:06.332293
7990 19:23:06.332357
7991 19:23:06.338316 [DQSOSCAuto] RK0, (LSB)MR18= 0x1615, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
7992 19:23:06.341909 CH0 RK0: MR19=303, MR18=1615
7993 19:23:06.348569 CH0_RK0: MR19=0x303, MR18=0x1615, DQSOSC=398, MR23=63, INC=23, DEC=15
7994 19:23:06.348671
7995 19:23:06.352179 ----->DramcWriteLeveling(PI) begin...
7996 19:23:06.352275 ==
7997 19:23:06.355385 Dram Type= 6, Freq= 0, CH_0, rank 1
7998 19:23:06.358330 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7999 19:23:06.358429 ==
8000 19:23:06.361949 Write leveling (Byte 0): 32 => 32
8001 19:23:06.364948 Write leveling (Byte 1): 28 => 28
8002 19:23:06.368519 DramcWriteLeveling(PI) end<-----
8003 19:23:06.368667
8004 19:23:06.368763 ==
8005 19:23:06.371739 Dram Type= 6, Freq= 0, CH_0, rank 1
8006 19:23:06.375110 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8007 19:23:06.375272 ==
8008 19:23:06.378565 [Gating] SW mode calibration
8009 19:23:06.385003 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8010 19:23:06.391605 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8011 19:23:06.395061 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8012 19:23:06.401706 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8013 19:23:06.405005 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8014 19:23:06.407966 1 4 12 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
8015 19:23:06.411486 1 4 16 | B1->B0 | 2a29 3434 | 1 1 | (1 1) (1 1)
8016 19:23:06.418313 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8017 19:23:06.421439 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8018 19:23:06.424645 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8019 19:23:06.431599 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8020 19:23:06.434728 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8021 19:23:06.437848 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8022 19:23:06.444672 1 5 12 | B1->B0 | 3434 2828 | 1 1 | (1 1) (1 0)
8023 19:23:06.447729 1 5 16 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
8024 19:23:06.451007 1 5 20 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
8025 19:23:06.457968 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8026 19:23:06.461047 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8027 19:23:06.463962 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8028 19:23:06.470637 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8029 19:23:06.474172 1 6 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8030 19:23:06.477677 1 6 12 | B1->B0 | 2323 3f3f | 0 0 | (0 0) (0 0)
8031 19:23:06.484213 1 6 16 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
8032 19:23:06.487123 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8033 19:23:06.490709 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8034 19:23:06.497217 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8035 19:23:06.500441 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8036 19:23:06.503872 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8037 19:23:06.510736 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8038 19:23:06.514292 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8039 19:23:06.517370 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8040 19:23:06.523697 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8041 19:23:06.527247 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 19:23:06.530378 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 19:23:06.537021 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 19:23:06.540568 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 19:23:06.543962 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8046 19:23:06.550573 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8047 19:23:06.553684 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8048 19:23:06.557257 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 19:23:06.563921 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 19:23:06.567028 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 19:23:06.570519 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 19:23:06.577225 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 19:23:06.580210 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8054 19:23:06.583872 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8055 19:23:06.586658 Total UI for P1: 0, mck2ui 16
8056 19:23:06.590270 best dqsien dly found for B0: ( 1, 9, 8)
8057 19:23:06.593873 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8058 19:23:06.600205 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8059 19:23:06.603925 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8060 19:23:06.606828 Total UI for P1: 0, mck2ui 16
8061 19:23:06.610363 best dqsien dly found for B1: ( 1, 9, 18)
8062 19:23:06.613296 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8063 19:23:06.617015 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8064 19:23:06.617101
8065 19:23:06.620073 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8066 19:23:06.626757 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8067 19:23:06.626866 [Gating] SW calibration Done
8068 19:23:06.626975 ==
8069 19:23:06.630279 Dram Type= 6, Freq= 0, CH_0, rank 1
8070 19:23:06.636816 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8071 19:23:06.636905 ==
8072 19:23:06.637007 RX Vref Scan: 0
8073 19:23:06.637106
8074 19:23:06.640009 RX Vref 0 -> 0, step: 1
8075 19:23:06.640117
8076 19:23:06.643587 RX Delay 0 -> 252, step: 8
8077 19:23:06.646714 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8078 19:23:06.649998 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8079 19:23:06.653395 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8080 19:23:06.656949 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8081 19:23:06.663259 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8082 19:23:06.667225 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
8083 19:23:06.670219 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8084 19:23:06.673582 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8085 19:23:06.676760 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8086 19:23:06.683518 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8087 19:23:06.687022 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8088 19:23:06.689911 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8089 19:23:06.693423 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8090 19:23:06.697031 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8091 19:23:06.703610 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8092 19:23:06.706617 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8093 19:23:06.706690 ==
8094 19:23:06.710123 Dram Type= 6, Freq= 0, CH_0, rank 1
8095 19:23:06.713621 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8096 19:23:06.713709 ==
8097 19:23:06.716538 DQS Delay:
8098 19:23:06.716622 DQS0 = 0, DQS1 = 0
8099 19:23:06.716705 DQM Delay:
8100 19:23:06.720192 DQM0 = 127, DQM1 = 122
8101 19:23:06.720274 DQ Delay:
8102 19:23:06.723173 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =123
8103 19:23:06.726249 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
8104 19:23:06.733004 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
8105 19:23:06.736797 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =127
8106 19:23:06.736902
8107 19:23:06.736997
8108 19:23:06.737085 ==
8109 19:23:06.739815 Dram Type= 6, Freq= 0, CH_0, rank 1
8110 19:23:06.742812 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8111 19:23:06.742892 ==
8112 19:23:06.742975
8113 19:23:06.743057
8114 19:23:06.746330 TX Vref Scan disable
8115 19:23:06.749588 == TX Byte 0 ==
8116 19:23:06.752893 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8117 19:23:06.756421 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
8118 19:23:06.759459 == TX Byte 1 ==
8119 19:23:06.762914 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8120 19:23:06.766493 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8121 19:23:06.766573 ==
8122 19:23:06.769328 Dram Type= 6, Freq= 0, CH_0, rank 1
8123 19:23:06.772659 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8124 19:23:06.775647 ==
8125 19:23:06.787350
8126 19:23:06.790626 TX Vref early break, caculate TX vref
8127 19:23:06.794304 TX Vref=16, minBit 0, minWin=22, winSum=366
8128 19:23:06.797185 TX Vref=18, minBit 8, minWin=22, winSum=370
8129 19:23:06.800673 TX Vref=20, minBit 6, minWin=23, winSum=383
8130 19:23:06.803871 TX Vref=22, minBit 8, minWin=23, winSum=392
8131 19:23:06.807373 TX Vref=24, minBit 8, minWin=24, winSum=404
8132 19:23:06.814196 TX Vref=26, minBit 0, minWin=25, winSum=405
8133 19:23:06.816968 TX Vref=28, minBit 8, minWin=24, winSum=411
8134 19:23:06.820748 TX Vref=30, minBit 8, minWin=23, winSum=406
8135 19:23:06.824143 TX Vref=32, minBit 8, minWin=22, winSum=394
8136 19:23:06.827282 TX Vref=34, minBit 8, minWin=22, winSum=387
8137 19:23:06.834132 [TxChooseVref] Worse bit 0, Min win 25, Win sum 405, Final Vref 26
8138 19:23:06.834224
8139 19:23:06.837045 Final TX Range 0 Vref 26
8140 19:23:06.837128
8141 19:23:06.837218 ==
8142 19:23:06.840773 Dram Type= 6, Freq= 0, CH_0, rank 1
8143 19:23:06.843810 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8144 19:23:06.843888 ==
8145 19:23:06.843974
8146 19:23:06.844064
8147 19:23:06.847316 TX Vref Scan disable
8148 19:23:06.853764 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8149 19:23:06.853851 == TX Byte 0 ==
8150 19:23:06.857384 u2DelayCellOfst[0]=18 cells (5 PI)
8151 19:23:06.860338 u2DelayCellOfst[1]=22 cells (6 PI)
8152 19:23:06.863601 u2DelayCellOfst[2]=11 cells (3 PI)
8153 19:23:06.867287 u2DelayCellOfst[3]=15 cells (4 PI)
8154 19:23:06.870294 u2DelayCellOfst[4]=11 cells (3 PI)
8155 19:23:06.873831 u2DelayCellOfst[5]=0 cells (0 PI)
8156 19:23:06.877230 u2DelayCellOfst[6]=22 cells (6 PI)
8157 19:23:06.880145 u2DelayCellOfst[7]=22 cells (6 PI)
8158 19:23:06.883259 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8159 19:23:06.886874 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
8160 19:23:06.890033 == TX Byte 1 ==
8161 19:23:06.890105 u2DelayCellOfst[8]=0 cells (0 PI)
8162 19:23:06.893705 u2DelayCellOfst[9]=0 cells (0 PI)
8163 19:23:06.896787 u2DelayCellOfst[10]=7 cells (2 PI)
8164 19:23:06.900303 u2DelayCellOfst[11]=7 cells (2 PI)
8165 19:23:06.903558 u2DelayCellOfst[12]=15 cells (4 PI)
8166 19:23:06.906640 u2DelayCellOfst[13]=15 cells (4 PI)
8167 19:23:06.910214 u2DelayCellOfst[14]=15 cells (4 PI)
8168 19:23:06.913504 u2DelayCellOfst[15]=11 cells (3 PI)
8169 19:23:06.916990 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8170 19:23:06.923564 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8171 19:23:06.923672 DramC Write-DBI on
8172 19:23:06.923760 ==
8173 19:23:06.926813 Dram Type= 6, Freq= 0, CH_0, rank 1
8174 19:23:06.930079 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8175 19:23:06.933312 ==
8176 19:23:06.933436
8177 19:23:06.933540
8178 19:23:06.933630 TX Vref Scan disable
8179 19:23:06.937045 == TX Byte 0 ==
8180 19:23:06.940079 Update DQM dly =732 (2 ,6, 28) DQM OEN =(3 ,3)
8181 19:23:06.943687 == TX Byte 1 ==
8182 19:23:06.946619 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8183 19:23:06.950431 DramC Write-DBI off
8184 19:23:06.950540
8185 19:23:06.950644 [DATLAT]
8186 19:23:06.950733 Freq=1600, CH0 RK1
8187 19:23:06.950796
8188 19:23:06.953418 DATLAT Default: 0xf
8189 19:23:06.953498 0, 0xFFFF, sum = 0
8190 19:23:06.956989 1, 0xFFFF, sum = 0
8191 19:23:06.959917 2, 0xFFFF, sum = 0
8192 19:23:06.959999 3, 0xFFFF, sum = 0
8193 19:23:06.963650 4, 0xFFFF, sum = 0
8194 19:23:06.963734 5, 0xFFFF, sum = 0
8195 19:23:06.966993 6, 0xFFFF, sum = 0
8196 19:23:06.967075 7, 0xFFFF, sum = 0
8197 19:23:06.969826 8, 0xFFFF, sum = 0
8198 19:23:06.969920 9, 0xFFFF, sum = 0
8199 19:23:06.973336 10, 0xFFFF, sum = 0
8200 19:23:06.973418 11, 0xFFFF, sum = 0
8201 19:23:06.977108 12, 0xFFFF, sum = 0
8202 19:23:06.977218 13, 0xCFFF, sum = 0
8203 19:23:06.979852 14, 0x0, sum = 1
8204 19:23:06.979934 15, 0x0, sum = 2
8205 19:23:06.983256 16, 0x0, sum = 3
8206 19:23:06.983338 17, 0x0, sum = 4
8207 19:23:06.986799 best_step = 15
8208 19:23:06.986879
8209 19:23:06.986944 ==
8210 19:23:06.989780 Dram Type= 6, Freq= 0, CH_0, rank 1
8211 19:23:06.993289 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8212 19:23:06.993373 ==
8213 19:23:06.996264 RX Vref Scan: 0
8214 19:23:06.996345
8215 19:23:06.996413 RX Vref 0 -> 0, step: 1
8216 19:23:06.996495
8217 19:23:06.999792 RX Delay 3 -> 252, step: 4
8218 19:23:07.006255 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8219 19:23:07.009857 iDelay=191, Bit 1, Center 124 (71 ~ 178) 108
8220 19:23:07.012822 iDelay=191, Bit 2, Center 120 (67 ~ 174) 108
8221 19:23:07.016441 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8222 19:23:07.019277 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8223 19:23:07.026465 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8224 19:23:07.029324 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8225 19:23:07.032782 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8226 19:23:07.036372 iDelay=191, Bit 8, Center 110 (55 ~ 166) 112
8227 19:23:07.039592 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8228 19:23:07.045752 iDelay=191, Bit 10, Center 118 (59 ~ 178) 120
8229 19:23:07.049420 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8230 19:23:07.052444 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8231 19:23:07.056003 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8232 19:23:07.059463 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8233 19:23:07.065859 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8234 19:23:07.065943 ==
8235 19:23:07.069391 Dram Type= 6, Freq= 0, CH_0, rank 1
8236 19:23:07.072814 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8237 19:23:07.072897 ==
8238 19:23:07.072980 DQS Delay:
8239 19:23:07.076330 DQS0 = 0, DQS1 = 0
8240 19:23:07.076435 DQM Delay:
8241 19:23:07.079051 DQM0 = 124, DQM1 = 117
8242 19:23:07.079213 DQ Delay:
8243 19:23:07.082532 DQ0 =124, DQ1 =124, DQ2 =120, DQ3 =122
8244 19:23:07.085992 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8245 19:23:07.089309 DQ8 =110, DQ9 =104, DQ10 =118, DQ11 =112
8246 19:23:07.092721 DQ12 =124, DQ13 =122, DQ14 =128, DQ15 =124
8247 19:23:07.092803
8248 19:23:07.092886
8249 19:23:07.095893
8250 19:23:07.095974 [DramC_TX_OE_Calibration] TA2
8251 19:23:07.099323 Original DQ_B0 (3 6) =30, OEN = 27
8252 19:23:07.102525 Original DQ_B1 (3 6) =30, OEN = 27
8253 19:23:07.105458 24, 0x0, End_B0=24 End_B1=24
8254 19:23:07.108992 25, 0x0, End_B0=25 End_B1=25
8255 19:23:07.112527 26, 0x0, End_B0=26 End_B1=26
8256 19:23:07.112632 27, 0x0, End_B0=27 End_B1=27
8257 19:23:07.115657 28, 0x0, End_B0=28 End_B1=28
8258 19:23:07.118748 29, 0x0, End_B0=29 End_B1=29
8259 19:23:07.122291 30, 0x0, End_B0=30 End_B1=30
8260 19:23:07.125668 31, 0x4141, End_B0=30 End_B1=30
8261 19:23:07.125773 Byte0 end_step=30 best_step=27
8262 19:23:07.129022 Byte1 end_step=30 best_step=27
8263 19:23:07.132152 Byte0 TX OE(2T, 0.5T) = (3, 3)
8264 19:23:07.135389 Byte1 TX OE(2T, 0.5T) = (3, 3)
8265 19:23:07.135458
8266 19:23:07.135518
8267 19:23:07.145434 [DQSOSCAuto] RK1, (LSB)MR18= 0x2512, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
8268 19:23:07.145539 CH0 RK1: MR19=303, MR18=2512
8269 19:23:07.152095 CH0_RK1: MR19=0x303, MR18=0x2512, DQSOSC=391, MR23=63, INC=24, DEC=16
8270 19:23:07.155640 [RxdqsGatingPostProcess] freq 1600
8271 19:23:07.161780 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8272 19:23:07.165093 best DQS0 dly(2T, 0.5T) = (1, 1)
8273 19:23:07.168425 best DQS1 dly(2T, 0.5T) = (1, 1)
8274 19:23:07.172011 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8275 19:23:07.175169 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8276 19:23:07.175238 best DQS0 dly(2T, 0.5T) = (1, 1)
8277 19:23:07.178488 best DQS1 dly(2T, 0.5T) = (1, 1)
8278 19:23:07.181747 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8279 19:23:07.185106 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8280 19:23:07.188391 Pre-setting of DQS Precalculation
8281 19:23:07.194764 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8282 19:23:07.194837 ==
8283 19:23:07.198020 Dram Type= 6, Freq= 0, CH_1, rank 0
8284 19:23:07.201769 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8285 19:23:07.201845 ==
8286 19:23:07.207766 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8287 19:23:07.211429 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8288 19:23:07.214536 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8289 19:23:07.221126 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8290 19:23:07.230247 [CA 0] Center 42 (13~71) winsize 59
8291 19:23:07.233238 [CA 1] Center 42 (12~72) winsize 61
8292 19:23:07.236720 [CA 2] Center 38 (9~67) winsize 59
8293 19:23:07.240014 [CA 3] Center 37 (8~66) winsize 59
8294 19:23:07.243259 [CA 4] Center 37 (8~67) winsize 60
8295 19:23:07.246620 [CA 5] Center 36 (7~66) winsize 60
8296 19:23:07.246700
8297 19:23:07.250348 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8298 19:23:07.250427
8299 19:23:07.253701 [CATrainingPosCal] consider 1 rank data
8300 19:23:07.256476 u2DelayCellTimex100 = 258/100 ps
8301 19:23:07.259955 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8302 19:23:07.266597 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8303 19:23:07.270183 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8304 19:23:07.273068 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8305 19:23:07.276699 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8306 19:23:07.280097 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8307 19:23:07.280176
8308 19:23:07.283554 CA PerBit enable=1, Macro0, CA PI delay=36
8309 19:23:07.283634
8310 19:23:07.286648 [CBTSetCACLKResult] CA Dly = 36
8311 19:23:07.289944 CS Dly: 10 (0~41)
8312 19:23:07.292928 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8313 19:23:07.296628 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8314 19:23:07.296707 ==
8315 19:23:07.299891 Dram Type= 6, Freq= 0, CH_1, rank 1
8316 19:23:07.302932 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8317 19:23:07.306184 ==
8318 19:23:07.309661 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8319 19:23:07.313311 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8320 19:23:07.319623 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8321 19:23:07.323341 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8322 19:23:07.333548 [CA 0] Center 42 (13~71) winsize 59
8323 19:23:07.336529 [CA 1] Center 42 (12~72) winsize 61
8324 19:23:07.340125 [CA 2] Center 37 (8~67) winsize 60
8325 19:23:07.343117 [CA 3] Center 36 (7~66) winsize 60
8326 19:23:07.346674 [CA 4] Center 37 (7~67) winsize 61
8327 19:23:07.350004 [CA 5] Center 36 (6~66) winsize 61
8328 19:23:07.350083
8329 19:23:07.353325 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8330 19:23:07.353405
8331 19:23:07.356758 [CATrainingPosCal] consider 2 rank data
8332 19:23:07.359568 u2DelayCellTimex100 = 258/100 ps
8333 19:23:07.366429 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8334 19:23:07.369863 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8335 19:23:07.372902 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8336 19:23:07.376989 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8337 19:23:07.379336 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8338 19:23:07.383009 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8339 19:23:07.383090
8340 19:23:07.386039 CA PerBit enable=1, Macro0, CA PI delay=36
8341 19:23:07.386119
8342 19:23:07.389246 [CBTSetCACLKResult] CA Dly = 36
8343 19:23:07.392804 CS Dly: 11 (0~43)
8344 19:23:07.395980 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8345 19:23:07.399151 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8346 19:23:07.399245
8347 19:23:07.402431 ----->DramcWriteLeveling(PI) begin...
8348 19:23:07.402512 ==
8349 19:23:07.405762 Dram Type= 6, Freq= 0, CH_1, rank 0
8350 19:23:07.412281 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8351 19:23:07.412361 ==
8352 19:23:07.415693 Write leveling (Byte 0): 25 => 25
8353 19:23:07.418945 Write leveling (Byte 1): 28 => 28
8354 19:23:07.419024 DramcWriteLeveling(PI) end<-----
8355 19:23:07.419086
8356 19:23:07.422296 ==
8357 19:23:07.426105 Dram Type= 6, Freq= 0, CH_1, rank 0
8358 19:23:07.428966 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8359 19:23:07.429039 ==
8360 19:23:07.432439 [Gating] SW mode calibration
8361 19:23:07.439033 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8362 19:23:07.442428 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8363 19:23:07.449252 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8364 19:23:07.452285 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8365 19:23:07.455704 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8366 19:23:07.462039 1 4 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8367 19:23:07.465428 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
8368 19:23:07.468801 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8369 19:23:07.475774 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8370 19:23:07.478747 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8371 19:23:07.482380 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8372 19:23:07.488948 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8373 19:23:07.492075 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8374 19:23:07.495135 1 5 12 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 0)
8375 19:23:07.501908 1 5 16 | B1->B0 | 2727 2828 | 0 0 | (1 0) (1 0)
8376 19:23:07.505334 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8377 19:23:07.508464 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8378 19:23:07.515200 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8379 19:23:07.518284 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8380 19:23:07.522020 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8381 19:23:07.528207 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8382 19:23:07.531732 1 6 12 | B1->B0 | 3535 2e2e | 0 0 | (0 0) (0 0)
8383 19:23:07.534727 1 6 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8384 19:23:07.541387 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8385 19:23:07.544715 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8386 19:23:07.548576 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8387 19:23:07.554939 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8388 19:23:07.558018 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8389 19:23:07.561731 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8390 19:23:07.568136 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8391 19:23:07.571272 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8392 19:23:07.574567 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 19:23:07.581231 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 19:23:07.584598 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 19:23:07.588252 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 19:23:07.591361 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 19:23:07.598114 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 19:23:07.601067 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 19:23:07.607826 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 19:23:07.611416 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 19:23:07.614414 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 19:23:07.617469 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 19:23:07.624242 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 19:23:07.627991 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 19:23:07.631022 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 19:23:07.637475 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 19:23:07.640893 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8408 19:23:07.644461 Total UI for P1: 0, mck2ui 16
8409 19:23:07.647564 best dqsien dly found for B1: ( 1, 9, 14)
8410 19:23:07.651064 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8411 19:23:07.654144 Total UI for P1: 0, mck2ui 16
8412 19:23:07.657830 best dqsien dly found for B0: ( 1, 9, 16)
8413 19:23:07.660541 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8414 19:23:07.663928 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8415 19:23:07.664019
8416 19:23:07.670688 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8417 19:23:07.674165 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8418 19:23:07.677394 [Gating] SW calibration Done
8419 19:23:07.677471 ==
8420 19:23:07.680614 Dram Type= 6, Freq= 0, CH_1, rank 0
8421 19:23:07.684079 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8422 19:23:07.684189 ==
8423 19:23:07.684297 RX Vref Scan: 0
8424 19:23:07.687510
8425 19:23:07.687620 RX Vref 0 -> 0, step: 1
8426 19:23:07.687726
8427 19:23:07.690686 RX Delay 0 -> 252, step: 8
8428 19:23:07.694027 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8429 19:23:07.697375 iDelay=200, Bit 1, Center 127 (64 ~ 191) 128
8430 19:23:07.704059 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8431 19:23:07.707454 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8432 19:23:07.710473 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8433 19:23:07.713908 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8434 19:23:07.717087 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8435 19:23:07.723858 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8436 19:23:07.726986 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8437 19:23:07.730574 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8438 19:23:07.733738 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8439 19:23:07.736860 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8440 19:23:07.743485 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8441 19:23:07.746938 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8442 19:23:07.750608 iDelay=200, Bit 14, Center 131 (80 ~ 183) 104
8443 19:23:07.753604 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8444 19:23:07.753689 ==
8445 19:23:07.756734 Dram Type= 6, Freq= 0, CH_1, rank 0
8446 19:23:07.763796 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8447 19:23:07.763900 ==
8448 19:23:07.763996 DQS Delay:
8449 19:23:07.766737 DQS0 = 0, DQS1 = 0
8450 19:23:07.766813 DQM Delay:
8451 19:23:07.766878 DQM0 = 132, DQM1 = 125
8452 19:23:07.770559 DQ Delay:
8453 19:23:07.773395 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8454 19:23:07.776812 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8455 19:23:07.780278 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8456 19:23:07.783488 DQ12 =135, DQ13 =135, DQ14 =131, DQ15 =135
8457 19:23:07.783568
8458 19:23:07.783659
8459 19:23:07.783739 ==
8460 19:23:07.786596 Dram Type= 6, Freq= 0, CH_1, rank 0
8461 19:23:07.789861 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8462 19:23:07.793387 ==
8463 19:23:07.793465
8464 19:23:07.793559
8465 19:23:07.793627 TX Vref Scan disable
8466 19:23:07.796586 == TX Byte 0 ==
8467 19:23:07.800078 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8468 19:23:07.803519 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8469 19:23:07.806943 == TX Byte 1 ==
8470 19:23:07.810192 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8471 19:23:07.813178 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8472 19:23:07.816449 ==
8473 19:23:07.819895 Dram Type= 6, Freq= 0, CH_1, rank 0
8474 19:23:07.822889 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8475 19:23:07.822979 ==
8476 19:23:07.835241
8477 19:23:07.838882 TX Vref early break, caculate TX vref
8478 19:23:07.841783 TX Vref=16, minBit 1, minWin=22, winSum=364
8479 19:23:07.845016 TX Vref=18, minBit 10, minWin=22, winSum=375
8480 19:23:07.848582 TX Vref=20, minBit 10, minWin=23, winSum=387
8481 19:23:07.852053 TX Vref=22, minBit 5, minWin=24, winSum=400
8482 19:23:07.858720 TX Vref=24, minBit 13, minWin=24, winSum=407
8483 19:23:07.861748 TX Vref=26, minBit 1, minWin=25, winSum=416
8484 19:23:07.865421 TX Vref=28, minBit 1, minWin=25, winSum=418
8485 19:23:07.868339 TX Vref=30, minBit 0, minWin=25, winSum=417
8486 19:23:07.872023 TX Vref=32, minBit 5, minWin=24, winSum=407
8487 19:23:07.875159 TX Vref=34, minBit 1, minWin=23, winSum=396
8488 19:23:07.881494 [TxChooseVref] Worse bit 1, Min win 25, Win sum 418, Final Vref 28
8489 19:23:07.881585
8490 19:23:07.884843 Final TX Range 0 Vref 28
8491 19:23:07.884921
8492 19:23:07.885003 ==
8493 19:23:07.888427 Dram Type= 6, Freq= 0, CH_1, rank 0
8494 19:23:07.891489 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8495 19:23:07.891567 ==
8496 19:23:07.891659
8497 19:23:07.891739
8498 19:23:07.894857 TX Vref Scan disable
8499 19:23:07.901436 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8500 19:23:07.901564 == TX Byte 0 ==
8501 19:23:07.905041 u2DelayCellOfst[0]=18 cells (5 PI)
8502 19:23:07.908069 u2DelayCellOfst[1]=15 cells (4 PI)
8503 19:23:07.911685 u2DelayCellOfst[2]=0 cells (0 PI)
8504 19:23:07.914534 u2DelayCellOfst[3]=7 cells (2 PI)
8505 19:23:07.918153 u2DelayCellOfst[4]=7 cells (2 PI)
8506 19:23:07.921276 u2DelayCellOfst[5]=22 cells (6 PI)
8507 19:23:07.924445 u2DelayCellOfst[6]=18 cells (5 PI)
8508 19:23:07.927980 u2DelayCellOfst[7]=3 cells (1 PI)
8509 19:23:07.931261 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8510 19:23:07.934324 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8511 19:23:07.937773 == TX Byte 1 ==
8512 19:23:07.941296 u2DelayCellOfst[8]=0 cells (0 PI)
8513 19:23:07.941398 u2DelayCellOfst[9]=7 cells (2 PI)
8514 19:23:07.944569 u2DelayCellOfst[10]=15 cells (4 PI)
8515 19:23:07.947792 u2DelayCellOfst[11]=7 cells (2 PI)
8516 19:23:07.950840 u2DelayCellOfst[12]=18 cells (5 PI)
8517 19:23:07.954443 u2DelayCellOfst[13]=22 cells (6 PI)
8518 19:23:07.957805 u2DelayCellOfst[14]=22 cells (6 PI)
8519 19:23:07.961297 u2DelayCellOfst[15]=22 cells (6 PI)
8520 19:23:07.967894 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8521 19:23:07.970958 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8522 19:23:07.971032 DramC Write-DBI on
8523 19:23:07.971094 ==
8524 19:23:07.974528 Dram Type= 6, Freq= 0, CH_1, rank 0
8525 19:23:07.980961 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8526 19:23:07.981071 ==
8527 19:23:07.981174
8528 19:23:07.981268
8529 19:23:07.981357 TX Vref Scan disable
8530 19:23:07.985034 == TX Byte 0 ==
8531 19:23:07.987855 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8532 19:23:07.991379 == TX Byte 1 ==
8533 19:23:07.994668 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8534 19:23:07.998351 DramC Write-DBI off
8535 19:23:07.998426
8536 19:23:07.998488 [DATLAT]
8537 19:23:07.998551 Freq=1600, CH1 RK0
8538 19:23:07.998608
8539 19:23:08.001352 DATLAT Default: 0xf
8540 19:23:08.001450 0, 0xFFFF, sum = 0
8541 19:23:08.004607 1, 0xFFFF, sum = 0
8542 19:23:08.008305 2, 0xFFFF, sum = 0
8543 19:23:08.008405 3, 0xFFFF, sum = 0
8544 19:23:08.011752 4, 0xFFFF, sum = 0
8545 19:23:08.011861 5, 0xFFFF, sum = 0
8546 19:23:08.014688 6, 0xFFFF, sum = 0
8547 19:23:08.014782 7, 0xFFFF, sum = 0
8548 19:23:08.018503 8, 0xFFFF, sum = 0
8549 19:23:08.018604 9, 0xFFFF, sum = 0
8550 19:23:08.021434 10, 0xFFFF, sum = 0
8551 19:23:08.021547 11, 0xFFFF, sum = 0
8552 19:23:08.024612 12, 0xFFFF, sum = 0
8553 19:23:08.024703 13, 0x8FFF, sum = 0
8554 19:23:08.028179 14, 0x0, sum = 1
8555 19:23:08.028252 15, 0x0, sum = 2
8556 19:23:08.031310 16, 0x0, sum = 3
8557 19:23:08.031381 17, 0x0, sum = 4
8558 19:23:08.034465 best_step = 15
8559 19:23:08.034539
8560 19:23:08.034614 ==
8561 19:23:08.037522 Dram Type= 6, Freq= 0, CH_1, rank 0
8562 19:23:08.041139 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8563 19:23:08.041216 ==
8564 19:23:08.044111 RX Vref Scan: 1
8565 19:23:08.044185
8566 19:23:08.044255 Set Vref Range= 24 -> 127
8567 19:23:08.044315
8568 19:23:08.047770 RX Vref 24 -> 127, step: 1
8569 19:23:08.047844
8570 19:23:08.051328 RX Delay 11 -> 252, step: 4
8571 19:23:08.051420
8572 19:23:08.054337 Set Vref, RX VrefLevel [Byte0]: 24
8573 19:23:08.057471 [Byte1]: 24
8574 19:23:08.057566
8575 19:23:08.060801 Set Vref, RX VrefLevel [Byte0]: 25
8576 19:23:08.064261 [Byte1]: 25
8577 19:23:08.067416
8578 19:23:08.067496 Set Vref, RX VrefLevel [Byte0]: 26
8579 19:23:08.070911 [Byte1]: 26
8580 19:23:08.075254
8581 19:23:08.075358 Set Vref, RX VrefLevel [Byte0]: 27
8582 19:23:08.078792 [Byte1]: 27
8583 19:23:08.083079
8584 19:23:08.083163 Set Vref, RX VrefLevel [Byte0]: 28
8585 19:23:08.086068 [Byte1]: 28
8586 19:23:08.090283
8587 19:23:08.090390 Set Vref, RX VrefLevel [Byte0]: 29
8588 19:23:08.093820 [Byte1]: 29
8589 19:23:08.097875
8590 19:23:08.097954 Set Vref, RX VrefLevel [Byte0]: 30
8591 19:23:08.101527 [Byte1]: 30
8592 19:23:08.105742
8593 19:23:08.105819 Set Vref, RX VrefLevel [Byte0]: 31
8594 19:23:08.108745 [Byte1]: 31
8595 19:23:08.113287
8596 19:23:08.113370 Set Vref, RX VrefLevel [Byte0]: 32
8597 19:23:08.116584 [Byte1]: 32
8598 19:23:08.121311
8599 19:23:08.121419 Set Vref, RX VrefLevel [Byte0]: 33
8600 19:23:08.124176 [Byte1]: 33
8601 19:23:08.128480
8602 19:23:08.128563 Set Vref, RX VrefLevel [Byte0]: 34
8603 19:23:08.131973 [Byte1]: 34
8604 19:23:08.136171
8605 19:23:08.136261 Set Vref, RX VrefLevel [Byte0]: 35
8606 19:23:08.139319 [Byte1]: 35
8607 19:23:08.143608
8608 19:23:08.143695 Set Vref, RX VrefLevel [Byte0]: 36
8609 19:23:08.147184 [Byte1]: 36
8610 19:23:08.151393
8611 19:23:08.151482 Set Vref, RX VrefLevel [Byte0]: 37
8612 19:23:08.155191 [Byte1]: 37
8613 19:23:08.158743
8614 19:23:08.158827 Set Vref, RX VrefLevel [Byte0]: 38
8615 19:23:08.162421 [Byte1]: 38
8616 19:23:08.166428
8617 19:23:08.166535 Set Vref, RX VrefLevel [Byte0]: 39
8618 19:23:08.169742 [Byte1]: 39
8619 19:23:08.174280
8620 19:23:08.174388 Set Vref, RX VrefLevel [Byte0]: 40
8621 19:23:08.177294 [Byte1]: 40
8622 19:23:08.181641
8623 19:23:08.181718 Set Vref, RX VrefLevel [Byte0]: 41
8624 19:23:08.184840 [Byte1]: 41
8625 19:23:08.189361
8626 19:23:08.189462 Set Vref, RX VrefLevel [Byte0]: 42
8627 19:23:08.192769 [Byte1]: 42
8628 19:23:08.196839
8629 19:23:08.196939 Set Vref, RX VrefLevel [Byte0]: 43
8630 19:23:08.200642 [Byte1]: 43
8631 19:23:08.204666
8632 19:23:08.204765 Set Vref, RX VrefLevel [Byte0]: 44
8633 19:23:08.208128 [Byte1]: 44
8634 19:23:08.212541
8635 19:23:08.212643 Set Vref, RX VrefLevel [Byte0]: 45
8636 19:23:08.215480 [Byte1]: 45
8637 19:23:08.219758
8638 19:23:08.219859 Set Vref, RX VrefLevel [Byte0]: 46
8639 19:23:08.223352 [Byte1]: 46
8640 19:23:08.227715
8641 19:23:08.227813 Set Vref, RX VrefLevel [Byte0]: 47
8642 19:23:08.230571 [Byte1]: 47
8643 19:23:08.235227
8644 19:23:08.235304 Set Vref, RX VrefLevel [Byte0]: 48
8645 19:23:08.238342 [Byte1]: 48
8646 19:23:08.242588
8647 19:23:08.242668 Set Vref, RX VrefLevel [Byte0]: 49
8648 19:23:08.246314 [Byte1]: 49
8649 19:23:08.250612
8650 19:23:08.250714 Set Vref, RX VrefLevel [Byte0]: 50
8651 19:23:08.253572 [Byte1]: 50
8652 19:23:08.257960
8653 19:23:08.258060 Set Vref, RX VrefLevel [Byte0]: 51
8654 19:23:08.261019 [Byte1]: 51
8655 19:23:08.265774
8656 19:23:08.265862 Set Vref, RX VrefLevel [Byte0]: 52
8657 19:23:08.268777 [Byte1]: 52
8658 19:23:08.273596
8659 19:23:08.273700 Set Vref, RX VrefLevel [Byte0]: 53
8660 19:23:08.276553 [Byte1]: 53
8661 19:23:08.280814
8662 19:23:08.280922 Set Vref, RX VrefLevel [Byte0]: 54
8663 19:23:08.283984 [Byte1]: 54
8664 19:23:08.288567
8665 19:23:08.288664 Set Vref, RX VrefLevel [Byte0]: 55
8666 19:23:08.291701 [Byte1]: 55
8667 19:23:08.296104
8668 19:23:08.296202 Set Vref, RX VrefLevel [Byte0]: 56
8669 19:23:08.299533 [Byte1]: 56
8670 19:23:08.303602
8671 19:23:08.303710 Set Vref, RX VrefLevel [Byte0]: 57
8672 19:23:08.307240 [Byte1]: 57
8673 19:23:08.311317
8674 19:23:08.311390 Set Vref, RX VrefLevel [Byte0]: 58
8675 19:23:08.314380 [Byte1]: 58
8676 19:23:08.319105
8677 19:23:08.319208 Set Vref, RX VrefLevel [Byte0]: 59
8678 19:23:08.322070 [Byte1]: 59
8679 19:23:08.326582
8680 19:23:08.326685 Set Vref, RX VrefLevel [Byte0]: 60
8681 19:23:08.329628 [Byte1]: 60
8682 19:23:08.334205
8683 19:23:08.334275 Set Vref, RX VrefLevel [Byte0]: 61
8684 19:23:08.337645 [Byte1]: 61
8685 19:23:08.341872
8686 19:23:08.341967 Set Vref, RX VrefLevel [Byte0]: 62
8687 19:23:08.345117 [Byte1]: 62
8688 19:23:08.349389
8689 19:23:08.349488 Set Vref, RX VrefLevel [Byte0]: 63
8690 19:23:08.352980 [Byte1]: 63
8691 19:23:08.356726
8692 19:23:08.356822 Set Vref, RX VrefLevel [Byte0]: 64
8693 19:23:08.360351 [Byte1]: 64
8694 19:23:08.364538
8695 19:23:08.364639 Set Vref, RX VrefLevel [Byte0]: 65
8696 19:23:08.368160 [Byte1]: 65
8697 19:23:08.372322
8698 19:23:08.372418 Set Vref, RX VrefLevel [Byte0]: 66
8699 19:23:08.375838 [Byte1]: 66
8700 19:23:08.379943
8701 19:23:08.380036 Set Vref, RX VrefLevel [Byte0]: 67
8702 19:23:08.382995 [Byte1]: 67
8703 19:23:08.387314
8704 19:23:08.387411 Set Vref, RX VrefLevel [Byte0]: 68
8705 19:23:08.390965 [Byte1]: 68
8706 19:23:08.395124
8707 19:23:08.395220 Set Vref, RX VrefLevel [Byte0]: 69
8708 19:23:08.398114 [Byte1]: 69
8709 19:23:08.402407
8710 19:23:08.402504 Set Vref, RX VrefLevel [Byte0]: 70
8711 19:23:08.405657 [Byte1]: 70
8712 19:23:08.410276
8713 19:23:08.410378 Final RX Vref Byte 0 = 58 to rank0
8714 19:23:08.413484 Final RX Vref Byte 1 = 56 to rank0
8715 19:23:08.416581 Final RX Vref Byte 0 = 58 to rank1
8716 19:23:08.419759 Final RX Vref Byte 1 = 56 to rank1==
8717 19:23:08.423078 Dram Type= 6, Freq= 0, CH_1, rank 0
8718 19:23:08.429829 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8719 19:23:08.429930 ==
8720 19:23:08.430022 DQS Delay:
8721 19:23:08.433105 DQS0 = 0, DQS1 = 0
8722 19:23:08.433200 DQM Delay:
8723 19:23:08.433287 DQM0 = 131, DQM1 = 123
8724 19:23:08.436411 DQ Delay:
8725 19:23:08.439819 DQ0 =138, DQ1 =126, DQ2 =122, DQ3 =126
8726 19:23:08.442975 DQ4 =128, DQ5 =142, DQ6 =142, DQ7 =128
8727 19:23:08.446525 DQ8 =108, DQ9 =112, DQ10 =122, DQ11 =116
8728 19:23:08.449884 DQ12 =132, DQ13 =130, DQ14 =132, DQ15 =132
8729 19:23:08.449966
8730 19:23:08.450051
8731 19:23:08.450130
8732 19:23:08.452970 [DramC_TX_OE_Calibration] TA2
8733 19:23:08.456515 Original DQ_B0 (3 6) =30, OEN = 27
8734 19:23:08.459805 Original DQ_B1 (3 6) =30, OEN = 27
8735 19:23:08.463299 24, 0x0, End_B0=24 End_B1=24
8736 19:23:08.463385 25, 0x0, End_B0=25 End_B1=25
8737 19:23:08.466379 26, 0x0, End_B0=26 End_B1=26
8738 19:23:08.470007 27, 0x0, End_B0=27 End_B1=27
8739 19:23:08.473027 28, 0x0, End_B0=28 End_B1=28
8740 19:23:08.476602 29, 0x0, End_B0=29 End_B1=29
8741 19:23:08.476709 30, 0x0, End_B0=30 End_B1=30
8742 19:23:08.479382 31, 0x4545, End_B0=30 End_B1=30
8743 19:23:08.483022 Byte0 end_step=30 best_step=27
8744 19:23:08.486021 Byte1 end_step=30 best_step=27
8745 19:23:08.489622 Byte0 TX OE(2T, 0.5T) = (3, 3)
8746 19:23:08.493281 Byte1 TX OE(2T, 0.5T) = (3, 3)
8747 19:23:08.493379
8748 19:23:08.493466
8749 19:23:08.499368 [DQSOSCAuto] RK0, (LSB)MR18= 0xa0f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 404 ps
8750 19:23:08.502952 CH1 RK0: MR19=303, MR18=A0F
8751 19:23:08.509684 CH1_RK0: MR19=0x303, MR18=0xA0F, DQSOSC=402, MR23=63, INC=22, DEC=15
8752 19:23:08.509760
8753 19:23:08.512565 ----->DramcWriteLeveling(PI) begin...
8754 19:23:08.512664 ==
8755 19:23:08.516205 Dram Type= 6, Freq= 0, CH_1, rank 1
8756 19:23:08.519179 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8757 19:23:08.519278 ==
8758 19:23:08.523209 Write leveling (Byte 0): 25 => 25
8759 19:23:08.525983 Write leveling (Byte 1): 27 => 27
8760 19:23:08.529377 DramcWriteLeveling(PI) end<-----
8761 19:23:08.529480
8762 19:23:08.529613 ==
8763 19:23:08.532954 Dram Type= 6, Freq= 0, CH_1, rank 1
8764 19:23:08.535921 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8765 19:23:08.536022 ==
8766 19:23:08.539463 [Gating] SW mode calibration
8767 19:23:08.545727 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8768 19:23:08.552555 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8769 19:23:08.556003 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8770 19:23:08.562407 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8771 19:23:08.565619 1 4 8 | B1->B0 | 2322 3232 | 1 1 | (0 0) (1 1)
8772 19:23:08.569203 1 4 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8773 19:23:08.572154 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8774 19:23:08.579233 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8775 19:23:08.582208 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8776 19:23:08.585739 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8777 19:23:08.592428 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8778 19:23:08.595413 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8779 19:23:08.599093 1 5 8 | B1->B0 | 3434 2b2b | 1 0 | (1 0) (0 1)
8780 19:23:08.605740 1 5 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8781 19:23:08.608706 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8782 19:23:08.612266 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8783 19:23:08.618644 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8784 19:23:08.622306 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8785 19:23:08.625219 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8786 19:23:08.631880 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8787 19:23:08.635767 1 6 8 | B1->B0 | 2828 4444 | 0 0 | (0 0) (0 0)
8788 19:23:08.638702 1 6 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8789 19:23:08.645202 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8790 19:23:08.648814 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8791 19:23:08.651764 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8792 19:23:08.658937 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8793 19:23:08.661775 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8794 19:23:08.665492 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8795 19:23:08.671926 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8796 19:23:08.675545 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8797 19:23:08.679010 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 19:23:08.685238 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 19:23:08.688346 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 19:23:08.691586 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 19:23:08.698452 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 19:23:08.701793 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 19:23:08.705349 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 19:23:08.712007 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 19:23:08.714825 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 19:23:08.718292 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 19:23:08.724927 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 19:23:08.728478 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 19:23:08.731562 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 19:23:08.737926 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 19:23:08.741256 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8812 19:23:08.744754 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8813 19:23:08.748225 Total UI for P1: 0, mck2ui 16
8814 19:23:08.751163 best dqsien dly found for B0: ( 1, 9, 8)
8815 19:23:08.754813 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8816 19:23:08.758220 Total UI for P1: 0, mck2ui 16
8817 19:23:08.761249 best dqsien dly found for B1: ( 1, 9, 10)
8818 19:23:08.764275 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8819 19:23:08.771244 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8820 19:23:08.771347
8821 19:23:08.774728 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8822 19:23:08.778000 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8823 19:23:08.781450 [Gating] SW calibration Done
8824 19:23:08.781587 ==
8825 19:23:08.784457 Dram Type= 6, Freq= 0, CH_1, rank 1
8826 19:23:08.787974 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8827 19:23:08.788067 ==
8828 19:23:08.790895 RX Vref Scan: 0
8829 19:23:08.790992
8830 19:23:08.791080 RX Vref 0 -> 0, step: 1
8831 19:23:08.791162
8832 19:23:08.794610 RX Delay 0 -> 252, step: 8
8833 19:23:08.797504 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8834 19:23:08.800928 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8835 19:23:08.807623 iDelay=200, Bit 2, Center 115 (56 ~ 175) 120
8836 19:23:08.810987 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8837 19:23:08.814398 iDelay=200, Bit 4, Center 123 (64 ~ 183) 120
8838 19:23:08.817430 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8839 19:23:08.821175 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8840 19:23:08.827673 iDelay=200, Bit 7, Center 127 (64 ~ 191) 128
8841 19:23:08.830805 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8842 19:23:08.834392 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8843 19:23:08.837276 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8844 19:23:08.840968 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8845 19:23:08.847356 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8846 19:23:08.850733 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8847 19:23:08.854074 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8848 19:23:08.857021 iDelay=200, Bit 15, Center 135 (72 ~ 199) 128
8849 19:23:08.857115 ==
8850 19:23:08.860510 Dram Type= 6, Freq= 0, CH_1, rank 1
8851 19:23:08.867090 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8852 19:23:08.867193 ==
8853 19:23:08.867282 DQS Delay:
8854 19:23:08.870690 DQS0 = 0, DQS1 = 0
8855 19:23:08.870787 DQM Delay:
8856 19:23:08.874093 DQM0 = 128, DQM1 = 127
8857 19:23:08.874186 DQ Delay:
8858 19:23:08.877536 DQ0 =131, DQ1 =127, DQ2 =115, DQ3 =123
8859 19:23:08.880406 DQ4 =123, DQ5 =139, DQ6 =139, DQ7 =127
8860 19:23:08.883890 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8861 19:23:08.886978 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =135
8862 19:23:08.887104
8863 19:23:08.887194
8864 19:23:08.887279 ==
8865 19:23:08.890662 Dram Type= 6, Freq= 0, CH_1, rank 1
8866 19:23:08.897224 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8867 19:23:08.897323 ==
8868 19:23:08.897414
8869 19:23:08.897501
8870 19:23:08.897632 TX Vref Scan disable
8871 19:23:08.900226 == TX Byte 0 ==
8872 19:23:08.903861 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8873 19:23:08.910391 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8874 19:23:08.910468 == TX Byte 1 ==
8875 19:23:08.913729 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8876 19:23:08.917134 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8877 19:23:08.920256 ==
8878 19:23:08.923616 Dram Type= 6, Freq= 0, CH_1, rank 1
8879 19:23:08.927116 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8880 19:23:08.927214 ==
8881 19:23:08.939295
8882 19:23:08.942912 TX Vref early break, caculate TX vref
8883 19:23:08.945939 TX Vref=16, minBit 0, minWin=23, winSum=387
8884 19:23:08.949463 TX Vref=18, minBit 0, minWin=23, winSum=396
8885 19:23:08.952548 TX Vref=20, minBit 0, minWin=23, winSum=403
8886 19:23:08.955958 TX Vref=22, minBit 0, minWin=24, winSum=411
8887 19:23:08.959232 TX Vref=24, minBit 0, minWin=25, winSum=418
8888 19:23:08.965985 TX Vref=26, minBit 0, minWin=25, winSum=429
8889 19:23:08.968915 TX Vref=28, minBit 0, minWin=26, winSum=431
8890 19:23:08.972522 TX Vref=30, minBit 1, minWin=25, winSum=421
8891 19:23:08.975887 TX Vref=32, minBit 1, minWin=23, winSum=413
8892 19:23:08.979303 TX Vref=34, minBit 5, minWin=23, winSum=405
8893 19:23:08.985828 [TxChooseVref] Worse bit 0, Min win 26, Win sum 431, Final Vref 28
8894 19:23:08.985901
8895 19:23:08.989316 Final TX Range 0 Vref 28
8896 19:23:08.989409
8897 19:23:08.989496 ==
8898 19:23:08.992177 Dram Type= 6, Freq= 0, CH_1, rank 1
8899 19:23:08.995458 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8900 19:23:08.995554 ==
8901 19:23:08.995643
8902 19:23:08.995736
8903 19:23:08.999151 TX Vref Scan disable
8904 19:23:09.005818 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8905 19:23:09.005918 == TX Byte 0 ==
8906 19:23:09.008812 u2DelayCellOfst[0]=18 cells (5 PI)
8907 19:23:09.011955 u2DelayCellOfst[1]=11 cells (3 PI)
8908 19:23:09.015523 u2DelayCellOfst[2]=0 cells (0 PI)
8909 19:23:09.018870 u2DelayCellOfst[3]=7 cells (2 PI)
8910 19:23:09.022192 u2DelayCellOfst[4]=7 cells (2 PI)
8911 19:23:09.025709 u2DelayCellOfst[5]=18 cells (5 PI)
8912 19:23:09.028750 u2DelayCellOfst[6]=18 cells (5 PI)
8913 19:23:09.028846 u2DelayCellOfst[7]=7 cells (2 PI)
8914 19:23:09.035222 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8915 19:23:09.038622 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8916 19:23:09.041972 == TX Byte 1 ==
8917 19:23:09.042070 u2DelayCellOfst[8]=0 cells (0 PI)
8918 19:23:09.045388 u2DelayCellOfst[9]=7 cells (2 PI)
8919 19:23:09.048498 u2DelayCellOfst[10]=11 cells (3 PI)
8920 19:23:09.052185 u2DelayCellOfst[11]=7 cells (2 PI)
8921 19:23:09.055414 u2DelayCellOfst[12]=15 cells (4 PI)
8922 19:23:09.058421 u2DelayCellOfst[13]=18 cells (5 PI)
8923 19:23:09.062050 u2DelayCellOfst[14]=22 cells (6 PI)
8924 19:23:09.065436 u2DelayCellOfst[15]=22 cells (6 PI)
8925 19:23:09.068264 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8926 19:23:09.074922 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8927 19:23:09.075022 DramC Write-DBI on
8928 19:23:09.075112 ==
8929 19:23:09.078506 Dram Type= 6, Freq= 0, CH_1, rank 1
8930 19:23:09.081543 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8931 19:23:09.085063 ==
8932 19:23:09.085163
8933 19:23:09.085252
8934 19:23:09.085339 TX Vref Scan disable
8935 19:23:09.088614 == TX Byte 0 ==
8936 19:23:09.091595 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8937 19:23:09.095248 == TX Byte 1 ==
8938 19:23:09.098830 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8939 19:23:09.101426 DramC Write-DBI off
8940 19:23:09.101526
8941 19:23:09.101587 [DATLAT]
8942 19:23:09.101644 Freq=1600, CH1 RK1
8943 19:23:09.101701
8944 19:23:09.105171 DATLAT Default: 0xf
8945 19:23:09.105258 0, 0xFFFF, sum = 0
8946 19:23:09.108624 1, 0xFFFF, sum = 0
8947 19:23:09.108719 2, 0xFFFF, sum = 0
8948 19:23:09.111540 3, 0xFFFF, sum = 0
8949 19:23:09.115065 4, 0xFFFF, sum = 0
8950 19:23:09.115170 5, 0xFFFF, sum = 0
8951 19:23:09.118866 6, 0xFFFF, sum = 0
8952 19:23:09.118937 7, 0xFFFF, sum = 0
8953 19:23:09.121741 8, 0xFFFF, sum = 0
8954 19:23:09.121829 9, 0xFFFF, sum = 0
8955 19:23:09.125197 10, 0xFFFF, sum = 0
8956 19:23:09.125297 11, 0xFFFF, sum = 0
8957 19:23:09.128567 12, 0xFFFF, sum = 0
8958 19:23:09.128662 13, 0x8FFF, sum = 0
8959 19:23:09.131696 14, 0x0, sum = 1
8960 19:23:09.131803 15, 0x0, sum = 2
8961 19:23:09.135127 16, 0x0, sum = 3
8962 19:23:09.135225 17, 0x0, sum = 4
8963 19:23:09.138066 best_step = 15
8964 19:23:09.138156
8965 19:23:09.138256 ==
8966 19:23:09.141726 Dram Type= 6, Freq= 0, CH_1, rank 1
8967 19:23:09.144668 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8968 19:23:09.144742 ==
8969 19:23:09.148240 RX Vref Scan: 0
8970 19:23:09.148335
8971 19:23:09.148421 RX Vref 0 -> 0, step: 1
8972 19:23:09.148505
8973 19:23:09.151686 RX Delay 11 -> 252, step: 4
8974 19:23:09.154697 iDelay=195, Bit 0, Center 132 (79 ~ 186) 108
8975 19:23:09.161389 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
8976 19:23:09.164559 iDelay=195, Bit 2, Center 114 (59 ~ 170) 112
8977 19:23:09.168080 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8978 19:23:09.171596 iDelay=195, Bit 4, Center 122 (67 ~ 178) 112
8979 19:23:09.174336 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8980 19:23:09.181132 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
8981 19:23:09.184345 iDelay=195, Bit 7, Center 124 (67 ~ 182) 116
8982 19:23:09.187578 iDelay=195, Bit 8, Center 110 (51 ~ 170) 120
8983 19:23:09.191030 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8984 19:23:09.197576 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8985 19:23:09.200631 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8986 19:23:09.204141 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8987 19:23:09.207768 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8988 19:23:09.210700 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
8989 19:23:09.217211 iDelay=195, Bit 15, Center 134 (79 ~ 190) 112
8990 19:23:09.217314 ==
8991 19:23:09.220515 Dram Type= 6, Freq= 0, CH_1, rank 1
8992 19:23:09.224016 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8993 19:23:09.224088 ==
8994 19:23:09.224148 DQS Delay:
8995 19:23:09.227190 DQS0 = 0, DQS1 = 0
8996 19:23:09.227282 DQM Delay:
8997 19:23:09.230635 DQM0 = 127, DQM1 = 124
8998 19:23:09.230733 DQ Delay:
8999 19:23:09.234251 DQ0 =132, DQ1 =126, DQ2 =114, DQ3 =124
9000 19:23:09.237164 DQ4 =122, DQ5 =138, DQ6 =140, DQ7 =124
9001 19:23:09.240376 DQ8 =110, DQ9 =112, DQ10 =128, DQ11 =120
9002 19:23:09.244009 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =134
9003 19:23:09.247066
9004 19:23:09.247170
9005 19:23:09.247257
9006 19:23:09.247343 [DramC_TX_OE_Calibration] TA2
9007 19:23:09.250704 Original DQ_B0 (3 6) =30, OEN = 27
9008 19:23:09.253651 Original DQ_B1 (3 6) =30, OEN = 27
9009 19:23:09.257081 24, 0x0, End_B0=24 End_B1=24
9010 19:23:09.260055 25, 0x0, End_B0=25 End_B1=25
9011 19:23:09.263650 26, 0x0, End_B0=26 End_B1=26
9012 19:23:09.263748 27, 0x0, End_B0=27 End_B1=27
9013 19:23:09.267327 28, 0x0, End_B0=28 End_B1=28
9014 19:23:09.270182 29, 0x0, End_B0=29 End_B1=29
9015 19:23:09.273283 30, 0x0, End_B0=30 End_B1=30
9016 19:23:09.276896 31, 0x4141, End_B0=30 End_B1=30
9017 19:23:09.279962 Byte0 end_step=30 best_step=27
9018 19:23:09.280060 Byte1 end_step=30 best_step=27
9019 19:23:09.283702 Byte0 TX OE(2T, 0.5T) = (3, 3)
9020 19:23:09.286962 Byte1 TX OE(2T, 0.5T) = (3, 3)
9021 19:23:09.287055
9022 19:23:09.287143
9023 19:23:09.296789 [DQSOSCAuto] RK1, (LSB)MR18= 0xf1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 402 ps
9024 19:23:09.296889 CH1 RK1: MR19=303, MR18=F1C
9025 19:23:09.303354 CH1_RK1: MR19=0x303, MR18=0xF1C, DQSOSC=395, MR23=63, INC=23, DEC=15
9026 19:23:09.306363 [RxdqsGatingPostProcess] freq 1600
9027 19:23:09.313135 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9028 19:23:09.316641 best DQS0 dly(2T, 0.5T) = (1, 1)
9029 19:23:09.319580 best DQS1 dly(2T, 0.5T) = (1, 1)
9030 19:23:09.322890 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9031 19:23:09.326197 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9032 19:23:09.326291 best DQS0 dly(2T, 0.5T) = (1, 1)
9033 19:23:09.329933 best DQS1 dly(2T, 0.5T) = (1, 1)
9034 19:23:09.333018 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9035 19:23:09.336571 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9036 19:23:09.339602 Pre-setting of DQS Precalculation
9037 19:23:09.346513 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9038 19:23:09.352932 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9039 19:23:09.359429 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9040 19:23:09.359531
9041 19:23:09.359623
9042 19:23:09.362989 [Calibration Summary] 3200 Mbps
9043 19:23:09.363090 CH 0, Rank 0
9044 19:23:09.366027 SW Impedance : PASS
9045 19:23:09.369796 DUTY Scan : NO K
9046 19:23:09.369899 ZQ Calibration : PASS
9047 19:23:09.372665 Jitter Meter : NO K
9048 19:23:09.375924 CBT Training : PASS
9049 19:23:09.376020 Write leveling : PASS
9050 19:23:09.379529 RX DQS gating : PASS
9051 19:23:09.382620 RX DQ/DQS(RDDQC) : PASS
9052 19:23:09.382714 TX DQ/DQS : PASS
9053 19:23:09.386342 RX DATLAT : PASS
9054 19:23:09.389110 RX DQ/DQS(Engine): PASS
9055 19:23:09.389203 TX OE : PASS
9056 19:23:09.389300 All Pass.
9057 19:23:09.389389
9058 19:23:09.392424 CH 0, Rank 1
9059 19:23:09.395731 SW Impedance : PASS
9060 19:23:09.395828 DUTY Scan : NO K
9061 19:23:09.399362 ZQ Calibration : PASS
9062 19:23:09.399459 Jitter Meter : NO K
9063 19:23:09.402878 CBT Training : PASS
9064 19:23:09.405996 Write leveling : PASS
9065 19:23:09.406090 RX DQS gating : PASS
9066 19:23:09.409158 RX DQ/DQS(RDDQC) : PASS
9067 19:23:09.412253 TX DQ/DQS : PASS
9068 19:23:09.412349 RX DATLAT : PASS
9069 19:23:09.415994 RX DQ/DQS(Engine): PASS
9070 19:23:09.419248 TX OE : PASS
9071 19:23:09.419351 All Pass.
9072 19:23:09.419464
9073 19:23:09.419570 CH 1, Rank 0
9074 19:23:09.422309 SW Impedance : PASS
9075 19:23:09.425872 DUTY Scan : NO K
9076 19:23:09.425948 ZQ Calibration : PASS
9077 19:23:09.429030 Jitter Meter : NO K
9078 19:23:09.432232 CBT Training : PASS
9079 19:23:09.432327 Write leveling : PASS
9080 19:23:09.435434 RX DQS gating : PASS
9081 19:23:09.439176 RX DQ/DQS(RDDQC) : PASS
9082 19:23:09.439273 TX DQ/DQS : PASS
9083 19:23:09.442096 RX DATLAT : PASS
9084 19:23:09.442194 RX DQ/DQS(Engine): PASS
9085 19:23:09.445680 TX OE : PASS
9086 19:23:09.445751 All Pass.
9087 19:23:09.445827
9088 19:23:09.449034 CH 1, Rank 1
9089 19:23:09.449127 SW Impedance : PASS
9090 19:23:09.451971 DUTY Scan : NO K
9091 19:23:09.455359 ZQ Calibration : PASS
9092 19:23:09.455457 Jitter Meter : NO K
9093 19:23:09.458906 CBT Training : PASS
9094 19:23:09.462455 Write leveling : PASS
9095 19:23:09.462555 RX DQS gating : PASS
9096 19:23:09.465329 RX DQ/DQS(RDDQC) : PASS
9097 19:23:09.468869 TX DQ/DQS : PASS
9098 19:23:09.468967 RX DATLAT : PASS
9099 19:23:09.471968 RX DQ/DQS(Engine): PASS
9100 19:23:09.475619 TX OE : PASS
9101 19:23:09.475718 All Pass.
9102 19:23:09.475816
9103 19:23:09.479099 DramC Write-DBI on
9104 19:23:09.479199 PER_BANK_REFRESH: Hybrid Mode
9105 19:23:09.482125 TX_TRACKING: ON
9106 19:23:09.488760 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9107 19:23:09.498661 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9108 19:23:09.504977 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9109 19:23:09.508514 [FAST_K] Save calibration result to emmc
9110 19:23:09.512114 sync common calibartion params.
9111 19:23:09.515281 sync cbt_mode0:1, 1:1
9112 19:23:09.515383 dram_init: ddr_geometry: 2
9113 19:23:09.518235 dram_init: ddr_geometry: 2
9114 19:23:09.521776 dram_init: ddr_geometry: 2
9115 19:23:09.525258 0:dram_rank_size:100000000
9116 19:23:09.525354 1:dram_rank_size:100000000
9117 19:23:09.531651 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9118 19:23:09.535050 DFS_SHUFFLE_HW_MODE: ON
9119 19:23:09.538284 dramc_set_vcore_voltage set vcore to 725000
9120 19:23:09.538379 Read voltage for 1600, 0
9121 19:23:09.541541 Vio18 = 0
9122 19:23:09.541681 Vcore = 725000
9123 19:23:09.541771 Vdram = 0
9124 19:23:09.545076 Vddq = 0
9125 19:23:09.545170 Vmddr = 0
9126 19:23:09.548365 switch to 3200 Mbps bootup
9127 19:23:09.548461 [DramcRunTimeConfig]
9128 19:23:09.551607 PHYPLL
9129 19:23:09.551764 DPM_CONTROL_AFTERK: ON
9130 19:23:09.554822 PER_BANK_REFRESH: ON
9131 19:23:09.558262 REFRESH_OVERHEAD_REDUCTION: ON
9132 19:23:09.558361 CMD_PICG_NEW_MODE: OFF
9133 19:23:09.561242 XRTWTW_NEW_MODE: ON
9134 19:23:09.561336 XRTRTR_NEW_MODE: ON
9135 19:23:09.564623 TX_TRACKING: ON
9136 19:23:09.564765 RDSEL_TRACKING: OFF
9137 19:23:09.568060 DQS Precalculation for DVFS: ON
9138 19:23:09.571484 RX_TRACKING: OFF
9139 19:23:09.571581 HW_GATING DBG: ON
9140 19:23:09.574536 ZQCS_ENABLE_LP4: ON
9141 19:23:09.574630 RX_PICG_NEW_MODE: ON
9142 19:23:09.578153 TX_PICG_NEW_MODE: ON
9143 19:23:09.578249 ENABLE_RX_DCM_DPHY: ON
9144 19:23:09.581576 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9145 19:23:09.584652 DUMMY_READ_FOR_TRACKING: OFF
9146 19:23:09.587711 !!! SPM_CONTROL_AFTERK: OFF
9147 19:23:09.591375 !!! SPM could not control APHY
9148 19:23:09.591471 IMPEDANCE_TRACKING: ON
9149 19:23:09.594907 TEMP_SENSOR: ON
9150 19:23:09.595006 HW_SAVE_FOR_SR: OFF
9151 19:23:09.597922 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9152 19:23:09.601417 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9153 19:23:09.604140 Read ODT Tracking: ON
9154 19:23:09.607902 Refresh Rate DeBounce: ON
9155 19:23:09.607998 DFS_NO_QUEUE_FLUSH: ON
9156 19:23:09.611177 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9157 19:23:09.614696 ENABLE_DFS_RUNTIME_MRW: OFF
9158 19:23:09.617662 DDR_RESERVE_NEW_MODE: ON
9159 19:23:09.617758 MR_CBT_SWITCH_FREQ: ON
9160 19:23:09.620788 =========================
9161 19:23:09.639828 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9162 19:23:09.643024 dram_init: ddr_geometry: 2
9163 19:23:09.661138 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9164 19:23:09.664848 dram_init: dram init end (result: 0)
9165 19:23:09.671547 DRAM-K: Full calibration passed in 24567 msecs
9166 19:23:09.674428 MRC: failed to locate region type 0.
9167 19:23:09.674527 DRAM rank0 size:0x100000000,
9168 19:23:09.678258 DRAM rank1 size=0x100000000
9169 19:23:09.687516 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9170 19:23:09.694755 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9171 19:23:09.700923 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9172 19:23:09.707836 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9173 19:23:09.710848 DRAM rank0 size:0x100000000,
9174 19:23:09.714287 DRAM rank1 size=0x100000000
9175 19:23:09.714358 CBMEM:
9176 19:23:09.717819 IMD: root @ 0xfffff000 254 entries.
9177 19:23:09.721415 IMD: root @ 0xffffec00 62 entries.
9178 19:23:09.724428 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9179 19:23:09.727524 WARNING: RO_VPD is uninitialized or empty.
9180 19:23:09.734008 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9181 19:23:09.741274 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9182 19:23:09.754192 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9183 19:23:09.765762 BS: romstage times (exec / console): total (unknown) / 24034 ms
9184 19:23:09.765865
9185 19:23:09.765957
9186 19:23:09.775696 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9187 19:23:09.778759 ARM64: Exception handlers installed.
9188 19:23:09.782479 ARM64: Testing exception
9189 19:23:09.785185 ARM64: Done test exception
9190 19:23:09.785282 Enumerating buses...
9191 19:23:09.788862 Show all devs... Before device enumeration.
9192 19:23:09.792022 Root Device: enabled 1
9193 19:23:09.795644 CPU_CLUSTER: 0: enabled 1
9194 19:23:09.795741 CPU: 00: enabled 1
9195 19:23:09.798700 Compare with tree...
9196 19:23:09.798772 Root Device: enabled 1
9197 19:23:09.801785 CPU_CLUSTER: 0: enabled 1
9198 19:23:09.805333 CPU: 00: enabled 1
9199 19:23:09.805428 Root Device scanning...
9200 19:23:09.808419 scan_static_bus for Root Device
9201 19:23:09.811821 CPU_CLUSTER: 0 enabled
9202 19:23:09.815437 scan_static_bus for Root Device done
9203 19:23:09.818347 scan_bus: bus Root Device finished in 8 msecs
9204 19:23:09.818442 done
9205 19:23:09.825293 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9206 19:23:09.828312 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9207 19:23:09.834788 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9208 19:23:09.838463 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9209 19:23:09.841424 Allocating resources...
9210 19:23:09.845031 Reading resources...
9211 19:23:09.848605 Root Device read_resources bus 0 link: 0
9212 19:23:09.848708 DRAM rank0 size:0x100000000,
9213 19:23:09.851559 DRAM rank1 size=0x100000000
9214 19:23:09.854904 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9215 19:23:09.858047 CPU: 00 missing read_resources
9216 19:23:09.864693 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9217 19:23:09.868280 Root Device read_resources bus 0 link: 0 done
9218 19:23:09.868399 Done reading resources.
9219 19:23:09.874471 Show resources in subtree (Root Device)...After reading.
9220 19:23:09.878155 Root Device child on link 0 CPU_CLUSTER: 0
9221 19:23:09.881136 CPU_CLUSTER: 0 child on link 0 CPU: 00
9222 19:23:09.891384 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9223 19:23:09.891484 CPU: 00
9224 19:23:09.894651 Root Device assign_resources, bus 0 link: 0
9225 19:23:09.897704 CPU_CLUSTER: 0 missing set_resources
9226 19:23:09.904178 Root Device assign_resources, bus 0 link: 0 done
9227 19:23:09.904277 Done setting resources.
9228 19:23:09.911000 Show resources in subtree (Root Device)...After assigning values.
9229 19:23:09.914611 Root Device child on link 0 CPU_CLUSTER: 0
9230 19:23:09.917436 CPU_CLUSTER: 0 child on link 0 CPU: 00
9231 19:23:09.927844 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9232 19:23:09.927952 CPU: 00
9233 19:23:09.931003 Done allocating resources.
9234 19:23:09.937747 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9235 19:23:09.937845 Enabling resources...
9236 19:23:09.937947 done.
9237 19:23:09.944395 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9238 19:23:09.944469 Initializing devices...
9239 19:23:09.947246 Root Device init
9240 19:23:09.950861 init hardware done!
9241 19:23:09.950963 0x00000018: ctrlr->caps
9242 19:23:09.954386 52.000 MHz: ctrlr->f_max
9243 19:23:09.954487 0.400 MHz: ctrlr->f_min
9244 19:23:09.957387 0x40ff8080: ctrlr->voltages
9245 19:23:09.960735 sclk: 390625
9246 19:23:09.960804 Bus Width = 1
9247 19:23:09.960901 sclk: 390625
9248 19:23:09.963888 Bus Width = 1
9249 19:23:09.963983 Early init status = 3
9250 19:23:09.970897 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9251 19:23:09.973902 in-header: 03 fc 00 00 01 00 00 00
9252 19:23:09.977291 in-data: 00
9253 19:23:09.980860 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9254 19:23:09.985082 in-header: 03 fd 00 00 00 00 00 00
9255 19:23:09.988106 in-data:
9256 19:23:09.991770 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9257 19:23:09.995920 in-header: 03 fc 00 00 01 00 00 00
9258 19:23:09.999310 in-data: 00
9259 19:23:10.002308 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9260 19:23:10.007793 in-header: 03 fd 00 00 00 00 00 00
9261 19:23:10.011336 in-data:
9262 19:23:10.014599 [SSUSB] Setting up USB HOST controller...
9263 19:23:10.017825 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9264 19:23:10.021084 [SSUSB] phy power-on done.
9265 19:23:10.024227 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9266 19:23:10.031228 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9267 19:23:10.034396 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9268 19:23:10.040892 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9269 19:23:10.047504 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9270 19:23:10.054618 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9271 19:23:10.061093 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9272 19:23:10.067568 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9273 19:23:10.070987 SPM: binary array size = 0x9dc
9274 19:23:10.074223 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9275 19:23:10.080646 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9276 19:23:10.087626 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9277 19:23:10.094327 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9278 19:23:10.097127 configure_display: Starting display init
9279 19:23:10.131258 anx7625_power_on_init: Init interface.
9280 19:23:10.134611 anx7625_disable_pd_protocol: Disabled PD feature.
9281 19:23:10.137829 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9282 19:23:10.165993 anx7625_start_dp_work: Secure OCM version=00
9283 19:23:10.168888 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9284 19:23:10.183508 sp_tx_get_edid_block: EDID Block = 1
9285 19:23:10.286505 Extracted contents:
9286 19:23:10.289732 header: 00 ff ff ff ff ff ff 00
9287 19:23:10.292882 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9288 19:23:10.295967 version: 01 04
9289 19:23:10.299208 basic params: 95 1f 11 78 0a
9290 19:23:10.302936 chroma info: 76 90 94 55 54 90 27 21 50 54
9291 19:23:10.305891 established: 00 00 00
9292 19:23:10.312466 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9293 19:23:10.316006 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9294 19:23:10.322686 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9295 19:23:10.328906 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9296 19:23:10.335485 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9297 19:23:10.339332 extensions: 00
9298 19:23:10.339427 checksum: fb
9299 19:23:10.339514
9300 19:23:10.342605 Manufacturer: IVO Model 57d Serial Number 0
9301 19:23:10.345381 Made week 0 of 2020
9302 19:23:10.349001 EDID version: 1.4
9303 19:23:10.349098 Digital display
9304 19:23:10.352429 6 bits per primary color channel
9305 19:23:10.352533 DisplayPort interface
9306 19:23:10.355436 Maximum image size: 31 cm x 17 cm
9307 19:23:10.358860 Gamma: 220%
9308 19:23:10.358954 Check DPMS levels
9309 19:23:10.362326 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9310 19:23:10.368778 First detailed timing is preferred timing
9311 19:23:10.368881 Established timings supported:
9312 19:23:10.372252 Standard timings supported:
9313 19:23:10.375271 Detailed timings
9314 19:23:10.378907 Hex of detail: 383680a07038204018303c0035ae10000019
9315 19:23:10.385364 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9316 19:23:10.388334 0780 0798 07c8 0820 hborder 0
9317 19:23:10.391911 0438 043b 0447 0458 vborder 0
9318 19:23:10.395541 -hsync -vsync
9319 19:23:10.395641 Did detailed timing
9320 19:23:10.401883 Hex of detail: 000000000000000000000000000000000000
9321 19:23:10.404932 Manufacturer-specified data, tag 0
9322 19:23:10.408711 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9323 19:23:10.411521 ASCII string: InfoVision
9324 19:23:10.414990 Hex of detail: 000000fe00523134304e574635205248200a
9325 19:23:10.418651 ASCII string: R140NWF5 RH
9326 19:23:10.418748 Checksum
9327 19:23:10.421692 Checksum: 0xfb (valid)
9328 19:23:10.425154 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9329 19:23:10.428059 DSI data_rate: 832800000 bps
9330 19:23:10.434821 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9331 19:23:10.438427 anx7625_parse_edid: pixelclock(138800).
9332 19:23:10.441496 hactive(1920), hsync(48), hfp(24), hbp(88)
9333 19:23:10.444963 vactive(1080), vsync(12), vfp(3), vbp(17)
9334 19:23:10.448089 anx7625_dsi_config: config dsi.
9335 19:23:10.454902 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9336 19:23:10.468396 anx7625_dsi_config: success to config DSI
9337 19:23:10.471408 anx7625_dp_start: MIPI phy setup OK.
9338 19:23:10.474752 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9339 19:23:10.478485 mtk_ddp_mode_set invalid vrefresh 60
9340 19:23:10.481611 main_disp_path_setup
9341 19:23:10.481706 ovl_layer_smi_id_en
9342 19:23:10.484606 ovl_layer_smi_id_en
9343 19:23:10.484698 ccorr_config
9344 19:23:10.484790 aal_config
9345 19:23:10.488171 gamma_config
9346 19:23:10.488268 postmask_config
9347 19:23:10.491690 dither_config
9348 19:23:10.494770 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9349 19:23:10.501342 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9350 19:23:10.504928 Root Device init finished in 553 msecs
9351 19:23:10.508260 CPU_CLUSTER: 0 init
9352 19:23:10.514690 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9353 19:23:10.517964 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9354 19:23:10.521229 APU_MBOX 0x190000b0 = 0x10001
9355 19:23:10.524476 APU_MBOX 0x190001b0 = 0x10001
9356 19:23:10.528309 APU_MBOX 0x190005b0 = 0x10001
9357 19:23:10.531338 APU_MBOX 0x190006b0 = 0x10001
9358 19:23:10.534397 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9359 19:23:10.547262 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9360 19:23:10.559854 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9361 19:23:10.566418 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9362 19:23:10.577993 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9363 19:23:10.587248 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9364 19:23:10.590804 CPU_CLUSTER: 0 init finished in 81 msecs
9365 19:23:10.593799 Devices initialized
9366 19:23:10.597415 Show all devs... After init.
9367 19:23:10.597518 Root Device: enabled 1
9368 19:23:10.600374 CPU_CLUSTER: 0: enabled 1
9369 19:23:10.603420 CPU: 00: enabled 1
9370 19:23:10.607033 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9371 19:23:10.610031 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9372 19:23:10.613554 ELOG: NV offset 0x57f000 size 0x1000
9373 19:23:10.619974 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9374 19:23:10.626685 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9375 19:23:10.629910 ELOG: Event(17) added with size 13 at 2024-04-18 19:23:10 UTC
9376 19:23:10.636844 out: cmd=0x121: 03 db 21 01 00 00 00 00
9377 19:23:10.640083 in-header: 03 42 00 00 2c 00 00 00
9378 19:23:10.650111 in-data: 1b 6a 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9379 19:23:10.656151 ELOG: Event(A1) added with size 10 at 2024-04-18 19:23:10 UTC
9380 19:23:10.663193 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9381 19:23:10.669578 ELOG: Event(A0) added with size 9 at 2024-04-18 19:23:10 UTC
9382 19:23:10.672664 elog_add_boot_reason: Logged dev mode boot
9383 19:23:10.679837 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9384 19:23:10.679920 Finalize devices...
9385 19:23:10.682853 Devices finalized
9386 19:23:10.686450 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9387 19:23:10.689936 Writing coreboot table at 0xffe64000
9388 19:23:10.693182 0. 000000000010a000-0000000000113fff: RAMSTAGE
9389 19:23:10.699437 1. 0000000040000000-00000000400fffff: RAM
9390 19:23:10.702489 2. 0000000040100000-000000004032afff: RAMSTAGE
9391 19:23:10.706292 3. 000000004032b000-00000000545fffff: RAM
9392 19:23:10.709181 4. 0000000054600000-000000005465ffff: BL31
9393 19:23:10.712748 5. 0000000054660000-00000000ffe63fff: RAM
9394 19:23:10.719103 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9395 19:23:10.722555 7. 0000000100000000-000000023fffffff: RAM
9396 19:23:10.725551 Passing 5 GPIOs to payload:
9397 19:23:10.729064 NAME | PORT | POLARITY | VALUE
9398 19:23:10.735840 EC in RW | 0x000000aa | low | undefined
9399 19:23:10.739315 EC interrupt | 0x00000005 | low | undefined
9400 19:23:10.742374 TPM interrupt | 0x000000ab | high | undefined
9401 19:23:10.748942 SD card detect | 0x00000011 | high | undefined
9402 19:23:10.752514 speaker enable | 0x00000093 | high | undefined
9403 19:23:10.755701 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9404 19:23:10.759010 in-header: 03 f9 00 00 02 00 00 00
9405 19:23:10.762045 in-data: 02 00
9406 19:23:10.765598 ADC[4]: Raw value=897040 ID=7
9407 19:23:10.765710 ADC[3]: Raw value=212330 ID=1
9408 19:23:10.768666 RAM Code: 0x71
9409 19:23:10.772302 ADC[6]: Raw value=75092 ID=0
9410 19:23:10.772414 ADC[5]: Raw value=212700 ID=1
9411 19:23:10.775249 SKU Code: 0x1
9412 19:23:10.781899 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum aab5
9413 19:23:10.782001 coreboot table: 964 bytes.
9414 19:23:10.785576 IMD ROOT 0. 0xfffff000 0x00001000
9415 19:23:10.788951 IMD SMALL 1. 0xffffe000 0x00001000
9416 19:23:10.791907 RO MCACHE 2. 0xffffc000 0x00001104
9417 19:23:10.795343 CONSOLE 3. 0xfff7c000 0x00080000
9418 19:23:10.798761 FMAP 4. 0xfff7b000 0x00000452
9419 19:23:10.801604 TIME STAMP 5. 0xfff7a000 0x00000910
9420 19:23:10.805011 VBOOT WORK 6. 0xfff66000 0x00014000
9421 19:23:10.808649 RAMOOPS 7. 0xffe66000 0x00100000
9422 19:23:10.811641 COREBOOT 8. 0xffe64000 0x00002000
9423 19:23:10.815159 IMD small region:
9424 19:23:10.818671 IMD ROOT 0. 0xffffec00 0x00000400
9425 19:23:10.821347 VPD 1. 0xffffeb80 0x0000006c
9426 19:23:10.824877 MMC STATUS 2. 0xffffeb60 0x00000004
9427 19:23:10.828376 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9428 19:23:10.831917 Probing TPM: done!
9429 19:23:10.835510 Connected to device vid:did:rid of 1ae0:0028:00
9430 19:23:10.846113 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9431 19:23:10.849579 Initialized TPM device CR50 revision 0
9432 19:23:10.853325 Checking cr50 for pending updates
9433 19:23:10.856931 Reading cr50 TPM mode
9434 19:23:10.865938 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9435 19:23:10.871989 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9436 19:23:10.912734 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9437 19:23:10.915566 Checking segment from ROM address 0x40100000
9438 19:23:10.918575 Checking segment from ROM address 0x4010001c
9439 19:23:10.925330 Loading segment from ROM address 0x40100000
9440 19:23:10.925431 code (compression=0)
9441 19:23:10.935298 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9442 19:23:10.941999 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9443 19:23:10.942105 it's not compressed!
9444 19:23:10.948926 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9445 19:23:10.955119 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9446 19:23:10.972440 Loading segment from ROM address 0x4010001c
9447 19:23:10.972547 Entry Point 0x80000000
9448 19:23:10.975949 Loaded segments
9449 19:23:10.979539 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9450 19:23:10.985987 Jumping to boot code at 0x80000000(0xffe64000)
9451 19:23:10.992596 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9452 19:23:10.999556 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9453 19:23:11.007067 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9454 19:23:11.010388 Checking segment from ROM address 0x40100000
9455 19:23:11.014107 Checking segment from ROM address 0x4010001c
9456 19:23:11.020285 Loading segment from ROM address 0x40100000
9457 19:23:11.020384 code (compression=1)
9458 19:23:11.027243 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9459 19:23:11.037077 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9460 19:23:11.037180 using LZMA
9461 19:23:11.045504 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9462 19:23:11.052331 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9463 19:23:11.055609 Loading segment from ROM address 0x4010001c
9464 19:23:11.055705 Entry Point 0x54601000
9465 19:23:11.058849 Loaded segments
9466 19:23:11.061858 NOTICE: MT8192 bl31_setup
9467 19:23:11.069106 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9468 19:23:11.072225 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9469 19:23:11.075819 WARNING: region 0:
9470 19:23:11.079304 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9471 19:23:11.079448 WARNING: region 1:
9472 19:23:11.086074 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9473 19:23:11.089107 WARNING: region 2:
9474 19:23:11.092624 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9475 19:23:11.095722 WARNING: region 3:
9476 19:23:11.099413 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9477 19:23:11.102523 WARNING: region 4:
9478 19:23:11.106076 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9479 19:23:11.109386 WARNING: region 5:
9480 19:23:11.112749 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9481 19:23:11.115731 WARNING: region 6:
9482 19:23:11.119348 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9483 19:23:11.119456 WARNING: region 7:
9484 19:23:11.125475 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9485 19:23:11.132633 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9486 19:23:11.135911 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9487 19:23:11.139013 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9488 19:23:11.145966 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9489 19:23:11.149064 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9490 19:23:11.152655 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9491 19:23:11.158908 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9492 19:23:11.162110 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9493 19:23:11.169018 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9494 19:23:11.172563 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9495 19:23:11.175606 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9496 19:23:11.182231 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9497 19:23:11.185763 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9498 19:23:11.188880 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9499 19:23:11.195586 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9500 19:23:11.198691 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9501 19:23:11.205278 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9502 19:23:11.209014 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9503 19:23:11.211953 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9504 19:23:11.218702 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9505 19:23:11.222103 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9506 19:23:11.225677 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9507 19:23:11.232202 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9508 19:23:11.235691 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9509 19:23:11.242252 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9510 19:23:11.245758 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9511 19:23:11.248611 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9512 19:23:11.255340 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9513 19:23:11.258783 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9514 19:23:11.265211 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9515 19:23:11.268358 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9516 19:23:11.271711 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9517 19:23:11.278916 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9518 19:23:11.281872 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9519 19:23:11.284914 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9520 19:23:11.288501 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9521 19:23:11.295270 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9522 19:23:11.298679 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9523 19:23:11.302032 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9524 19:23:11.305554 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9525 19:23:11.312214 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9526 19:23:11.315350 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9527 19:23:11.318425 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9528 19:23:11.321930 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9529 19:23:11.328505 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9530 19:23:11.332086 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9531 19:23:11.335190 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9532 19:23:11.338662 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9533 19:23:11.345204 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9534 19:23:11.348619 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9535 19:23:11.355281 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9536 19:23:11.358263 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9537 19:23:11.364875 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9538 19:23:11.368124 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9539 19:23:11.371929 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9540 19:23:11.378459 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9541 19:23:11.382036 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9542 19:23:11.388552 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9543 19:23:11.391722 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9544 19:23:11.398239 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9545 19:23:11.401654 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9546 19:23:11.408444 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9547 19:23:11.411806 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9548 19:23:11.414863 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9549 19:23:11.421459 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9550 19:23:11.425082 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9551 19:23:11.431602 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9552 19:23:11.434908 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9553 19:23:11.441565 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9554 19:23:11.445147 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9555 19:23:11.448144 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9556 19:23:11.454748 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9557 19:23:11.458154 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9558 19:23:11.465154 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9559 19:23:11.468241 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9560 19:23:11.475091 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9561 19:23:11.478316 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9562 19:23:11.481590 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9563 19:23:11.488420 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9564 19:23:11.491490 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9565 19:23:11.497990 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9566 19:23:11.501566 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9567 19:23:11.507932 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9568 19:23:11.511403 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9569 19:23:11.517984 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9570 19:23:11.521709 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9571 19:23:11.524657 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9572 19:23:11.531328 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9573 19:23:11.534924 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9574 19:23:11.541408 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9575 19:23:11.544789 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9576 19:23:11.551287 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9577 19:23:11.554505 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9578 19:23:11.558019 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9579 19:23:11.564689 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9580 19:23:11.567933 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9581 19:23:11.574644 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9582 19:23:11.578256 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9583 19:23:11.581304 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9584 19:23:11.584774 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9585 19:23:11.591496 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9586 19:23:11.594660 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9587 19:23:11.598134 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9588 19:23:11.604867 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9589 19:23:11.608352 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9590 19:23:11.614472 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9591 19:23:11.617995 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9592 19:23:11.621503 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9593 19:23:11.627727 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9594 19:23:11.631344 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9595 19:23:11.638045 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9596 19:23:11.641012 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9597 19:23:11.644725 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9598 19:23:11.651075 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9599 19:23:11.654467 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9600 19:23:11.661087 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9601 19:23:11.664524 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9602 19:23:11.667484 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9603 19:23:11.670846 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9604 19:23:11.677775 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9605 19:23:11.681108 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9606 19:23:11.684669 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9607 19:23:11.687627 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9608 19:23:11.694154 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9609 19:23:11.697372 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9610 19:23:11.701125 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9611 19:23:11.707850 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9612 19:23:11.711231 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9613 19:23:11.717616 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9614 19:23:11.721094 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9615 19:23:11.724028 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9616 19:23:11.730943 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9617 19:23:11.734217 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9618 19:23:11.740825 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9619 19:23:11.744352 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9620 19:23:11.747304 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9621 19:23:11.754075 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9622 19:23:11.757478 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9623 19:23:11.763806 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9624 19:23:11.767597 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9625 19:23:11.770818 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9626 19:23:11.777685 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9627 19:23:11.780516 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9628 19:23:11.787287 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9629 19:23:11.790894 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9630 19:23:11.793927 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9631 19:23:11.800452 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9632 19:23:11.804084 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9633 19:23:11.807349 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9634 19:23:11.814073 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9635 19:23:11.817209 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9636 19:23:11.823708 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9637 19:23:11.827330 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9638 19:23:11.830306 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9639 19:23:11.836931 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9640 19:23:11.840413 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9641 19:23:11.847159 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9642 19:23:11.850235 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9643 19:23:11.853632 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9644 19:23:11.860326 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9645 19:23:11.863853 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9646 19:23:11.870502 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9647 19:23:11.874008 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9648 19:23:11.877262 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9649 19:23:11.883231 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9650 19:23:11.886717 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9651 19:23:11.893379 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9652 19:23:11.896953 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9653 19:23:11.899887 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9654 19:23:11.906966 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9655 19:23:11.909846 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9656 19:23:11.916654 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9657 19:23:11.919599 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9658 19:23:11.922930 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9659 19:23:11.929487 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9660 19:23:11.933093 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9661 19:23:11.939615 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9662 19:23:11.942736 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9663 19:23:11.946215 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9664 19:23:11.952959 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9665 19:23:11.956465 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9666 19:23:11.959515 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9667 19:23:11.966062 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9668 19:23:11.969548 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9669 19:23:11.976261 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9670 19:23:11.979721 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9671 19:23:11.982815 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9672 19:23:11.989597 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9673 19:23:11.992333 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9674 19:23:11.999178 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9675 19:23:12.002372 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9676 19:23:12.008971 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9677 19:23:12.012398 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9678 19:23:12.016197 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9679 19:23:12.022140 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9680 19:23:12.025657 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9681 19:23:12.032467 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9682 19:23:12.035891 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9683 19:23:12.042207 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9684 19:23:12.045780 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9685 19:23:12.048798 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9686 19:23:12.055316 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9687 19:23:12.058585 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9688 19:23:12.065258 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9689 19:23:12.068456 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9690 19:23:12.075299 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9691 19:23:12.078246 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9692 19:23:12.081710 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9693 19:23:12.088225 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9694 19:23:12.091637 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9695 19:23:12.098149 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9696 19:23:12.101666 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9697 19:23:12.104897 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9698 19:23:12.111589 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9699 19:23:12.114946 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9700 19:23:12.121071 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9701 19:23:12.124681 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9702 19:23:12.131305 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9703 19:23:12.134796 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9704 19:23:12.137894 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9705 19:23:12.144483 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9706 19:23:12.147593 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9707 19:23:12.154351 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9708 19:23:12.157919 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9709 19:23:12.164273 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9710 19:23:12.168025 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9711 19:23:12.170941 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9712 19:23:12.177967 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9713 19:23:12.180967 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9714 19:23:12.184546 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9715 19:23:12.191086 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9716 19:23:12.193986 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9717 19:23:12.197484 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9718 19:23:12.201003 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9719 19:23:12.207450 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9720 19:23:12.210504 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9721 19:23:12.217156 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9722 19:23:12.220272 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9723 19:23:12.224077 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9724 19:23:12.230752 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9725 19:23:12.234179 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9726 19:23:12.236911 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9727 19:23:12.243761 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9728 19:23:12.247361 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9729 19:23:12.250559 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9730 19:23:12.256960 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9731 19:23:12.260045 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9732 19:23:12.266637 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9733 19:23:12.270035 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9734 19:23:12.273248 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9735 19:23:12.280048 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9736 19:23:12.283631 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9737 19:23:12.289744 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9738 19:23:12.293178 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9739 19:23:12.296802 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9740 19:23:12.303392 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9741 19:23:12.306581 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9742 19:23:12.310087 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9743 19:23:12.316769 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9744 19:23:12.319681 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9745 19:23:12.323253 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9746 19:23:12.329797 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9747 19:23:12.333063 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9748 19:23:12.335888 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9749 19:23:12.342817 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9750 19:23:12.345922 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9751 19:23:12.352959 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9752 19:23:12.356547 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9753 19:23:12.359224 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9754 19:23:12.366107 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9755 19:23:12.369743 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9756 19:23:12.372728 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9757 19:23:12.375740 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9758 19:23:12.379200 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9759 19:23:12.385798 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9760 19:23:12.389357 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9761 19:23:12.392378 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9762 19:23:12.395834 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9763 19:23:12.402183 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9764 19:23:12.405961 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9765 19:23:12.408798 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9766 19:23:12.415767 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9767 19:23:12.418737 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9768 19:23:12.422272 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9769 19:23:12.429034 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9770 19:23:12.431952 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9771 19:23:12.438426 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9772 19:23:12.442210 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9773 19:23:12.448492 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9774 19:23:12.451851 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9775 19:23:12.454943 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9776 19:23:12.462125 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9777 19:23:12.465269 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9778 19:23:12.471970 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9779 19:23:12.474967 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9780 19:23:12.481447 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9781 19:23:12.485121 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9782 19:23:12.487823 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9783 19:23:12.494648 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9784 19:23:12.498047 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9785 19:23:12.504718 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9786 19:23:12.508231 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9787 19:23:12.511302 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9788 19:23:12.517710 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9789 19:23:12.521018 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9790 19:23:12.527631 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9791 19:23:12.531414 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9792 19:23:12.534412 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9793 19:23:12.541168 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9794 19:23:12.544676 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9795 19:23:12.551048 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9796 19:23:12.554472 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9797 19:23:12.560898 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9798 19:23:12.564086 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9799 19:23:12.567374 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9800 19:23:12.574213 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9801 19:23:12.577677 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9802 19:23:12.583696 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9803 19:23:12.587295 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9804 19:23:12.593843 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9805 19:23:12.597238 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9806 19:23:12.600544 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9807 19:23:12.607064 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9808 19:23:12.610490 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9809 19:23:12.614064 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9810 19:23:12.620722 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9811 19:23:12.623642 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9812 19:23:12.630623 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9813 19:23:12.633805 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9814 19:23:12.637268 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9815 19:23:12.643785 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9816 19:23:12.646946 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9817 19:23:12.653443 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9818 19:23:12.656765 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9819 19:23:12.663274 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9820 19:23:12.666533 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9821 19:23:12.673242 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9822 19:23:12.676863 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9823 19:23:12.679714 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9824 19:23:12.686693 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9825 19:23:12.690198 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9826 19:23:12.696662 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9827 19:23:12.699678 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9828 19:23:12.703299 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9829 19:23:12.709701 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9830 19:23:12.712951 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9831 19:23:12.719879 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9832 19:23:12.722800 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9833 19:23:12.725911 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9834 19:23:12.732863 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9835 19:23:12.736284 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9836 19:23:12.742886 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9837 19:23:12.746042 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9838 19:23:12.749685 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9839 19:23:12.755716 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9840 19:23:12.759496 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9841 19:23:12.765596 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9842 19:23:12.769018 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9843 19:23:12.775727 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9844 19:23:12.779026 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9845 19:23:12.785865 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9846 19:23:12.789393 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9847 19:23:12.792535 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9848 19:23:12.799661 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9849 19:23:12.802319 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9850 19:23:12.808948 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9851 19:23:12.812474 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9852 19:23:12.818957 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9853 19:23:12.822421 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9854 19:23:12.825688 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9855 19:23:12.832398 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9856 19:23:12.835432 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9857 19:23:12.842374 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9858 19:23:12.845200 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9859 19:23:12.851775 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9860 19:23:12.855375 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9861 19:23:12.861982 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9862 19:23:12.864959 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9863 19:23:12.868466 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9864 19:23:12.875329 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9865 19:23:12.878297 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9866 19:23:12.884819 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9867 19:23:12.888303 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9868 19:23:12.895087 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9869 19:23:12.898067 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9870 19:23:12.901359 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9871 19:23:12.908604 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9872 19:23:12.911428 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9873 19:23:12.917951 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9874 19:23:12.921668 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9875 19:23:12.928427 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9876 19:23:12.931263 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9877 19:23:12.937931 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9878 19:23:12.941319 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9879 19:23:12.944388 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9880 19:23:12.951171 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9881 19:23:12.954644 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9882 19:23:12.961245 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9883 19:23:12.964238 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9884 19:23:12.970911 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9885 19:23:12.974476 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9886 19:23:12.977727 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9887 19:23:12.984270 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9888 19:23:12.987764 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9889 19:23:12.994375 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9890 19:23:12.997292 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9891 19:23:13.003848 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9892 19:23:13.007465 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9893 19:23:13.013706 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9894 19:23:13.017183 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9895 19:23:13.024370 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9896 19:23:13.027127 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9897 19:23:13.033501 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9898 19:23:13.037133 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9899 19:23:13.043478 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9900 19:23:13.046720 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9901 19:23:13.053280 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9902 19:23:13.056759 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9903 19:23:13.063631 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9904 19:23:13.066635 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9905 19:23:13.073271 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9906 19:23:13.076776 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9907 19:23:13.083170 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9908 19:23:13.086649 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9909 19:23:13.093279 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9910 19:23:13.096245 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9911 19:23:13.102885 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9912 19:23:13.106548 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9913 19:23:13.112740 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9914 19:23:13.116107 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9915 19:23:13.123141 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9916 19:23:13.125986 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9917 19:23:13.133056 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9918 19:23:13.136323 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9919 19:23:13.139865 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9920 19:23:13.142893 INFO: [APUAPC] vio 0
9921 19:23:13.149666 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9922 19:23:13.152699 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9923 19:23:13.155898 INFO: [APUAPC] D0_APC_0: 0x400510
9924 19:23:13.159216 INFO: [APUAPC] D0_APC_1: 0x0
9925 19:23:13.162830 INFO: [APUAPC] D0_APC_2: 0x1540
9926 19:23:13.166213 INFO: [APUAPC] D0_APC_3: 0x0
9927 19:23:13.169345 INFO: [APUAPC] D1_APC_0: 0xffffffff
9928 19:23:13.173149 INFO: [APUAPC] D1_APC_1: 0xffffffff
9929 19:23:13.176618 INFO: [APUAPC] D1_APC_2: 0x3fffff
9930 19:23:13.176714 INFO: [APUAPC] D1_APC_3: 0x0
9931 19:23:13.183155 INFO: [APUAPC] D2_APC_0: 0xffffffff
9932 19:23:13.186190 INFO: [APUAPC] D2_APC_1: 0xffffffff
9933 19:23:13.189484 INFO: [APUAPC] D2_APC_2: 0x3fffff
9934 19:23:13.189586 INFO: [APUAPC] D2_APC_3: 0x0
9935 19:23:13.192937 INFO: [APUAPC] D3_APC_0: 0xffffffff
9936 19:23:13.195874 INFO: [APUAPC] D3_APC_1: 0xffffffff
9937 19:23:13.199490 INFO: [APUAPC] D3_APC_2: 0x3fffff
9938 19:23:13.203163 INFO: [APUAPC] D3_APC_3: 0x0
9939 19:23:13.206091 INFO: [APUAPC] D4_APC_0: 0xffffffff
9940 19:23:13.209164 INFO: [APUAPC] D4_APC_1: 0xffffffff
9941 19:23:13.212503 INFO: [APUAPC] D4_APC_2: 0x3fffff
9942 19:23:13.216125 INFO: [APUAPC] D4_APC_3: 0x0
9943 19:23:13.219094 INFO: [APUAPC] D5_APC_0: 0xffffffff
9944 19:23:13.222440 INFO: [APUAPC] D5_APC_1: 0xffffffff
9945 19:23:13.225856 INFO: [APUAPC] D5_APC_2: 0x3fffff
9946 19:23:13.229063 INFO: [APUAPC] D5_APC_3: 0x0
9947 19:23:13.232362 INFO: [APUAPC] D6_APC_0: 0xffffffff
9948 19:23:13.235387 INFO: [APUAPC] D6_APC_1: 0xffffffff
9949 19:23:13.238924 INFO: [APUAPC] D6_APC_2: 0x3fffff
9950 19:23:13.242058 INFO: [APUAPC] D6_APC_3: 0x0
9951 19:23:13.245672 INFO: [APUAPC] D7_APC_0: 0xffffffff
9952 19:23:13.248906 INFO: [APUAPC] D7_APC_1: 0xffffffff
9953 19:23:13.251742 INFO: [APUAPC] D7_APC_2: 0x3fffff
9954 19:23:13.255308 INFO: [APUAPC] D7_APC_3: 0x0
9955 19:23:13.258847 INFO: [APUAPC] D8_APC_0: 0xffffffff
9956 19:23:13.262023 INFO: [APUAPC] D8_APC_1: 0xffffffff
9957 19:23:13.265195 INFO: [APUAPC] D8_APC_2: 0x3fffff
9958 19:23:13.268258 INFO: [APUAPC] D8_APC_3: 0x0
9959 19:23:13.271821 INFO: [APUAPC] D9_APC_0: 0xffffffff
9960 19:23:13.274997 INFO: [APUAPC] D9_APC_1: 0xffffffff
9961 19:23:13.278314 INFO: [APUAPC] D9_APC_2: 0x3fffff
9962 19:23:13.281713 INFO: [APUAPC] D9_APC_3: 0x0
9963 19:23:13.285284 INFO: [APUAPC] D10_APC_0: 0xffffffff
9964 19:23:13.288299 INFO: [APUAPC] D10_APC_1: 0xffffffff
9965 19:23:13.291785 INFO: [APUAPC] D10_APC_2: 0x3fffff
9966 19:23:13.295132 INFO: [APUAPC] D10_APC_3: 0x0
9967 19:23:13.298344 INFO: [APUAPC] D11_APC_0: 0xffffffff
9968 19:23:13.301346 INFO: [APUAPC] D11_APC_1: 0xffffffff
9969 19:23:13.304964 INFO: [APUAPC] D11_APC_2: 0x3fffff
9970 19:23:13.308041 INFO: [APUAPC] D11_APC_3: 0x0
9971 19:23:13.311554 INFO: [APUAPC] D12_APC_0: 0xffffffff
9972 19:23:13.314685 INFO: [APUAPC] D12_APC_1: 0xffffffff
9973 19:23:13.318148 INFO: [APUAPC] D12_APC_2: 0x3fffff
9974 19:23:13.321236 INFO: [APUAPC] D12_APC_3: 0x0
9975 19:23:13.324720 INFO: [APUAPC] D13_APC_0: 0xffffffff
9976 19:23:13.327637 INFO: [APUAPC] D13_APC_1: 0xffffffff
9977 19:23:13.331311 INFO: [APUAPC] D13_APC_2: 0x3fffff
9978 19:23:13.334717 INFO: [APUAPC] D13_APC_3: 0x0
9979 19:23:13.337974 INFO: [APUAPC] D14_APC_0: 0xffffffff
9980 19:23:13.341319 INFO: [APUAPC] D14_APC_1: 0xffffffff
9981 19:23:13.344357 INFO: [APUAPC] D14_APC_2: 0x3fffff
9982 19:23:13.347411 INFO: [APUAPC] D14_APC_3: 0x0
9983 19:23:13.350923 INFO: [APUAPC] D15_APC_0: 0xffffffff
9984 19:23:13.354310 INFO: [APUAPC] D15_APC_1: 0xffffffff
9985 19:23:13.357664 INFO: [APUAPC] D15_APC_2: 0x3fffff
9986 19:23:13.360795 INFO: [APUAPC] D15_APC_3: 0x0
9987 19:23:13.364200 INFO: [APUAPC] APC_CON: 0x4
9988 19:23:13.367256 INFO: [NOCDAPC] D0_APC_0: 0x0
9989 19:23:13.370741 INFO: [NOCDAPC] D0_APC_1: 0x0
9990 19:23:13.374273 INFO: [NOCDAPC] D1_APC_0: 0x0
9991 19:23:13.377626 INFO: [NOCDAPC] D1_APC_1: 0xfff
9992 19:23:13.380870 INFO: [NOCDAPC] D2_APC_0: 0x0
9993 19:23:13.384112 INFO: [NOCDAPC] D2_APC_1: 0xfff
9994 19:23:13.387106 INFO: [NOCDAPC] D3_APC_0: 0x0
9995 19:23:13.387207 INFO: [NOCDAPC] D3_APC_1: 0xfff
9996 19:23:13.390685 INFO: [NOCDAPC] D4_APC_0: 0x0
9997 19:23:13.393814 INFO: [NOCDAPC] D4_APC_1: 0xfff
9998 19:23:13.397309 INFO: [NOCDAPC] D5_APC_0: 0x0
9999 19:23:13.400303 INFO: [NOCDAPC] D5_APC_1: 0xfff
10000 19:23:13.403669 INFO: [NOCDAPC] D6_APC_0: 0x0
10001 19:23:13.406990 INFO: [NOCDAPC] D6_APC_1: 0xfff
10002 19:23:13.410116 INFO: [NOCDAPC] D7_APC_0: 0x0
10003 19:23:13.413765 INFO: [NOCDAPC] D7_APC_1: 0xfff
10004 19:23:13.416785 INFO: [NOCDAPC] D8_APC_0: 0x0
10005 19:23:13.420292 INFO: [NOCDAPC] D8_APC_1: 0xfff
10006 19:23:13.420387 INFO: [NOCDAPC] D9_APC_0: 0x0
10007 19:23:13.423221 INFO: [NOCDAPC] D9_APC_1: 0xfff
10008 19:23:13.426829 INFO: [NOCDAPC] D10_APC_0: 0x0
10009 19:23:13.430154 INFO: [NOCDAPC] D10_APC_1: 0xfff
10010 19:23:13.433267 INFO: [NOCDAPC] D11_APC_0: 0x0
10011 19:23:13.436846 INFO: [NOCDAPC] D11_APC_1: 0xfff
10012 19:23:13.440364 INFO: [NOCDAPC] D12_APC_0: 0x0
10013 19:23:13.443225 INFO: [NOCDAPC] D12_APC_1: 0xfff
10014 19:23:13.446637 INFO: [NOCDAPC] D13_APC_0: 0x0
10015 19:23:13.450063 INFO: [NOCDAPC] D13_APC_1: 0xfff
10016 19:23:13.453052 INFO: [NOCDAPC] D14_APC_0: 0x0
10017 19:23:13.456671 INFO: [NOCDAPC] D14_APC_1: 0xfff
10018 19:23:13.459532 INFO: [NOCDAPC] D15_APC_0: 0x0
10019 19:23:13.462784 INFO: [NOCDAPC] D15_APC_1: 0xfff
10020 19:23:13.466423 INFO: [NOCDAPC] APC_CON: 0x4
10021 19:23:13.469433 INFO: [APUAPC] set_apusys_apc done
10022 19:23:13.472983 INFO: [DEVAPC] devapc_init done
10023 19:23:13.476652 INFO: GICv3 without legacy support detected.
10024 19:23:13.479457 INFO: ARM GICv3 driver initialized in EL3
10025 19:23:13.483074 INFO: Maximum SPI INTID supported: 639
10026 19:23:13.486140 INFO: BL31: Initializing runtime services
10027 19:23:13.492468 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10028 19:23:13.495967 INFO: SPM: enable CPC mode
10029 19:23:13.502564 INFO: mcdi ready for mcusys-off-idle and system suspend
10030 19:23:13.506308 INFO: BL31: Preparing for EL3 exit to normal world
10031 19:23:13.509274 INFO: Entry point address = 0x80000000
10032 19:23:13.512474 INFO: SPSR = 0x8
10033 19:23:13.517193
10034 19:23:13.517293
10035 19:23:13.517382
10036 19:23:13.520195 Starting depthcharge on Spherion...
10037 19:23:13.520287
10038 19:23:13.520373 Wipe memory regions:
10039 19:23:13.520456
10040 19:23:13.521269 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10041 19:23:13.521403 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10042 19:23:13.521514 Setting prompt string to ['asurada:']
10043 19:23:13.521654 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10044 19:23:13.523793 [0x00000040000000, 0x00000054600000)
10045 19:23:13.645886
10046 19:23:13.646030 [0x00000054660000, 0x00000080000000)
10047 19:23:13.906874
10048 19:23:13.907012 [0x000000821a7280, 0x000000ffe64000)
10049 19:23:14.651731
10050 19:23:14.651864 [0x00000100000000, 0x00000240000000)
10051 19:23:16.541872
10052 19:23:16.545424 Initializing XHCI USB controller at 0x11200000.
10053 19:23:17.583580
10054 19:23:17.586640 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10055 19:23:17.586723
10056 19:23:17.586786
10057 19:23:17.586844
10058 19:23:17.587131 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10060 19:23:17.687452 asurada: tftpboot 192.168.201.1 13420342/tftp-deploy-9up0a6oe/kernel/image.itb 13420342/tftp-deploy-9up0a6oe/kernel/cmdline
10061 19:23:17.687598 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10062 19:23:17.687683 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10063 19:23:17.691834 tftpboot 192.168.201.1 13420342/tftp-deploy-9up0a6oe/kernel/image.itbtp-deploy-9up0a6oe/kernel/cmdline
10064 19:23:17.691928
10065 19:23:17.692000 Waiting for link
10066 19:23:17.850216
10067 19:23:17.850848 R8152: Initializing
10068 19:23:17.851247
10069 19:23:17.853716 Version 6 (ocp_data = 5c30)
10070 19:23:17.854244
10071 19:23:17.856717 R8152: Done initializing
10072 19:23:17.857219
10073 19:23:17.857717 Adding net device
10074 19:23:19.951855
10075 19:23:19.952503 done.
10076 19:23:19.952963
10077 19:23:19.953477 MAC: 00:24:32:30:78:ff
10078 19:23:19.953996
10079 19:23:19.955402 Sending DHCP discover... done.
10080 19:23:19.955909
10081 19:23:19.958471 Waiting for reply... done.
10082 19:23:19.958978
10083 19:23:19.961505 Sending DHCP request... done.
10084 19:23:19.962119
10085 19:23:19.966927 Waiting for reply... done.
10086 19:23:19.967481
10087 19:23:19.968013 My ip is 192.168.201.21
10088 19:23:19.968387
10089 19:23:19.970619 The DHCP server ip is 192.168.201.1
10090 19:23:19.971066
10091 19:23:19.976715 TFTP server IP predefined by user: 192.168.201.1
10092 19:23:19.977145
10093 19:23:19.983379 Bootfile predefined by user: 13420342/tftp-deploy-9up0a6oe/kernel/image.itb
10094 19:23:19.983796
10095 19:23:19.986659 Sending tftp read request... done.
10096 19:23:19.987249
10097 19:23:19.993586 Waiting for the transfer...
10098 19:23:19.994189
10099 19:23:20.553360 00000000 ################################################################
10100 19:23:20.553525
10101 19:23:21.095317 00080000 ################################################################
10102 19:23:21.095463
10103 19:23:21.661198 00100000 ################################################################
10104 19:23:21.661336
10105 19:23:22.211988 00180000 ################################################################
10106 19:23:22.212126
10107 19:23:22.817009 00200000 ################################################################
10108 19:23:22.817140
10109 19:23:23.393448 00280000 ################################################################
10110 19:23:23.393625
10111 19:23:24.081350 00300000 ################################################################
10112 19:23:24.081986
10113 19:23:24.728207 00380000 ################################################################
10114 19:23:24.728352
10115 19:23:25.378857 00400000 ################################################################
10116 19:23:25.379340
10117 19:23:26.041793 00480000 ################################################################
10118 19:23:26.042440
10119 19:23:26.727033 00500000 ################################################################
10120 19:23:26.727531
10121 19:23:27.398699 00580000 ################################################################
10122 19:23:27.398839
10123 19:23:28.070628 00600000 ################################################################
10124 19:23:28.071113
10125 19:23:28.746037 00680000 ################################################################
10126 19:23:28.746599
10127 19:23:29.423791 00700000 ################################################################
10128 19:23:29.423932
10129 19:23:30.096448 00780000 ################################################################
10130 19:23:30.096958
10131 19:23:30.784335 00800000 ################################################################
10132 19:23:30.784862
10133 19:23:31.457535 00880000 ################################################################
10134 19:23:31.457758
10135 19:23:32.107985 00900000 ################################################################
10136 19:23:32.108116
10137 19:23:32.759658 00980000 ################################################################
10138 19:23:32.759821
10139 19:23:33.302744 00a00000 ################################################################
10140 19:23:33.303282
10141 19:23:33.998723 00a80000 ################################################################
10142 19:23:33.998867
10143 19:23:34.682231 00b00000 ################################################################
10144 19:23:34.682389
10145 19:23:35.362042 00b80000 ################################################################
10146 19:23:35.362529
10147 19:23:36.045312 00c00000 ################################################################
10148 19:23:36.045857
10149 19:23:36.719787 00c80000 ################################################################
10150 19:23:36.720078
10151 19:23:37.359211 00d00000 ################################################################
10152 19:23:37.359341
10153 19:23:37.993283 00d80000 ################################################################
10154 19:23:37.993898
10155 19:23:38.651962 00e00000 ################################################################
10156 19:23:38.652399
10157 19:23:39.279082 00e80000 ################################################################
10158 19:23:39.279587
10159 19:23:39.929027 00f00000 ################################################################
10160 19:23:39.929175
10161 19:23:40.604047 00f80000 ################################################################
10162 19:23:40.604702
10163 19:23:41.300323 01000000 ################################################################
10164 19:23:41.300831
10165 19:23:41.982851 01080000 ################################################################
10166 19:23:41.983335
10167 19:23:42.602800 01100000 ################################################################
10168 19:23:42.602933
10169 19:23:43.206657 01180000 ################################################################
10170 19:23:43.206811
10171 19:23:43.904853 01200000 ################################################################
10172 19:23:43.905383
10173 19:23:44.622540 01280000 ################################################################
10174 19:23:44.623110
10175 19:23:45.311945 01300000 ################################################################
10176 19:23:45.312613
10177 19:23:46.004873 01380000 ################################################################
10178 19:23:46.005582
10179 19:23:46.649644 01400000 ################################################################
10180 19:23:46.650214
10181 19:23:47.348478 01480000 ################################################################
10182 19:23:47.348991
10183 19:23:48.036916 01500000 ################################################################
10184 19:23:48.037610
10185 19:23:48.702864 01580000 ################################################################
10186 19:23:48.703009
10187 19:23:49.310723 01600000 ################################################################
10188 19:23:49.310898
10189 19:23:49.888716 01680000 ################################################################
10190 19:23:49.889319
10191 19:23:50.522045 01700000 ################################################################
10192 19:23:50.522683
10193 19:23:51.189633 01780000 ################################################################
10194 19:23:51.189802
10195 19:23:51.869284 01800000 ################################################################
10196 19:23:51.869420
10197 19:23:52.447852 01880000 ################################################################
10198 19:23:52.447983
10199 19:23:53.054778 01900000 ################################################################
10200 19:23:53.055466
10201 19:23:53.674863 01980000 ################################################################
10202 19:23:53.675395
10203 19:23:54.281248 01a00000 ################################################################
10204 19:23:54.281394
10205 19:23:54.860737 01a80000 ################################################################
10206 19:23:54.860885
10207 19:23:55.519577 01b00000 ################################################################
10208 19:23:55.520099
10209 19:23:56.175055 01b80000 ################################################################
10210 19:23:56.175609
10211 19:23:56.774916 01c00000 ################################################################
10212 19:23:56.775050
10213 19:23:57.344597 01c80000 ################################################################
10214 19:23:57.344748
10215 19:23:57.950725 01d00000 ################################################################
10216 19:23:57.950877
10217 19:23:58.550583 01d80000 ################################################################
10218 19:23:58.551302
10219 19:23:59.201353 01e00000 ################################################################
10220 19:23:59.201861
10221 19:23:59.800066 01e80000 ################################################################
10222 19:23:59.800568
10223 19:24:00.468336 01f00000 ################################################################
10224 19:24:00.468475
10225 19:24:01.031193 01f80000 ################################################################
10226 19:24:01.031353
10227 19:24:01.614865 02000000 ################################################################
10228 19:24:01.615028
10229 19:24:02.203564 02080000 ################################################################
10230 19:24:02.203733
10231 19:24:02.759885 02100000 ################################################################
10232 19:24:02.760036
10233 19:24:03.301728 02180000 ################################################################
10234 19:24:03.301883
10235 19:24:04.003641 02200000 ################################################################
10236 19:24:04.004219
10237 19:24:04.724905 02280000 ################################################################
10238 19:24:04.725485
10239 19:24:05.460384 02300000 ################################################################
10240 19:24:05.461185
10241 19:24:06.186075 02380000 ################################################################
10242 19:24:06.186715
10243 19:24:06.887136 02400000 ################################################################
10244 19:24:06.887642
10245 19:24:07.608959 02480000 ################################################################
10246 19:24:07.609463
10247 19:24:08.327447 02500000 ################################################################
10248 19:24:08.327998
10249 19:24:09.030796 02580000 ################################################################
10250 19:24:09.031354
10251 19:24:09.716658 02600000 ################################################################
10252 19:24:09.717267
10253 19:24:10.392926 02680000 ################################################################
10254 19:24:10.393085
10255 19:24:11.116926 02700000 ################################################################
10256 19:24:11.117479
10257 19:24:11.791070 02780000 ################################################################
10258 19:24:11.791218
10259 19:24:12.381921 02800000 ################################################################
10260 19:24:12.382090
10261 19:24:13.076439 02880000 ################################################################
10262 19:24:13.076947
10263 19:24:13.782997 02900000 ################################################################
10264 19:24:13.783525
10265 19:24:14.502344 02980000 ################################################################
10266 19:24:14.502847
10267 19:24:15.199400 02a00000 ################################################################
10268 19:24:15.199913
10269 19:24:15.903876 02a80000 ################################################################
10270 19:24:15.904379
10271 19:24:16.595190 02b00000 ################################################################
10272 19:24:16.595754
10273 19:24:17.299206 02b80000 ################################################################
10274 19:24:17.299757
10275 19:24:18.013487 02c00000 ################################################################
10276 19:24:18.014043
10277 19:24:18.714890 02c80000 ################################################################
10278 19:24:18.715555
10279 19:24:19.424151 02d00000 ################################################################
10280 19:24:19.424657
10281 19:24:20.128321 02d80000 ################################################################
10282 19:24:20.128895
10283 19:24:20.833068 02e00000 ################################################################
10284 19:24:20.833689
10285 19:24:21.534617 02e80000 ################################################################
10286 19:24:21.535128
10287 19:24:22.231764 02f00000 ################################################################
10288 19:24:22.232337
10289 19:24:22.942196 02f80000 ################################################################
10290 19:24:22.942816
10291 19:24:23.644050 03000000 ################################################################
10292 19:24:23.644769
10293 19:24:24.353258 03080000 ################################################################
10294 19:24:24.353957
10295 19:24:25.067286 03100000 ################################################################
10296 19:24:25.067847
10297 19:24:25.776690 03180000 ################################################################
10298 19:24:25.777206
10299 19:24:26.480274 03200000 ################################################################
10300 19:24:26.480818
10301 19:24:27.141437 03280000 ################################################################
10302 19:24:27.141632
10303 19:24:27.810556 03300000 ################################################################
10304 19:24:27.810698
10305 19:24:28.424714 03380000 ################################################################
10306 19:24:28.424859
10307 19:24:29.030345 03400000 ################################################################
10308 19:24:29.030934
10309 19:24:29.744106 03480000 ################################################################
10310 19:24:29.744724
10311 19:24:30.418473 03500000 ################################################################
10312 19:24:30.418608
10313 19:24:31.014930 03580000 ################################################################
10314 19:24:31.015077
10315 19:24:31.604130 03600000 ################################################################
10316 19:24:31.604277
10317 19:24:32.193630 03680000 ################################################################
10318 19:24:32.193779
10319 19:24:32.779587 03700000 ################################################################
10320 19:24:32.779777
10321 19:24:33.352320 03780000 ################################################################
10322 19:24:33.352506
10323 19:24:33.940793 03800000 ################################################################
10324 19:24:33.940941
10325 19:24:34.510550 03880000 ################################################################
10326 19:24:34.510696
10327 19:24:35.101103 03900000 ################################################################
10328 19:24:35.101250
10329 19:24:35.690326 03980000 ################################################################
10330 19:24:35.690496
10331 19:24:36.284567 03a00000 ################################################################
10332 19:24:36.284718
10333 19:24:36.859210 03a80000 ################################################################
10334 19:24:36.859358
10335 19:24:37.432576 03b00000 ################################################################
10336 19:24:37.432718
10337 19:24:37.997465 03b80000 ################################################################
10338 19:24:37.997676
10339 19:24:38.563921 03c00000 ################################################################
10340 19:24:38.564065
10341 19:24:39.130988 03c80000 ################################################################
10342 19:24:39.131133
10343 19:24:39.726472 03d00000 ################################################################
10344 19:24:39.726620
10345 19:24:40.315506 03d80000 ################################################################
10346 19:24:40.315675
10347 19:24:40.453700 03e00000 ################ done.
10348 19:24:40.453850
10349 19:24:40.456632 The bootfile was 65135446 bytes long.
10350 19:24:40.456737
10351 19:24:40.459912 Sending tftp read request... done.
10352 19:24:40.459995
10353 19:24:40.463275 Waiting for the transfer...
10354 19:24:40.463359
10355 19:24:40.463423 00000000 # done.
10356 19:24:40.463484
10357 19:24:40.470022 Command line loaded dynamically from TFTP file: 13420342/tftp-deploy-9up0a6oe/kernel/cmdline
10358 19:24:40.473299
10359 19:24:40.486352 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10360 19:24:40.486452
10361 19:24:40.486518 Loading FIT.
10362 19:24:40.486579
10363 19:24:40.489583 Image ramdisk-1 has 52175825 bytes.
10364 19:24:40.489666
10365 19:24:40.493016 Image fdt-1 has 47230 bytes.
10366 19:24:40.493097
10367 19:24:40.496493 Image kernel-1 has 12910355 bytes.
10368 19:24:40.496575
10369 19:24:40.503027 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10370 19:24:40.503113
10371 19:24:40.523208 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10372 19:24:40.523322
10373 19:24:40.526627 Choosing best match conf-1 for compat google,spherion-rev2.
10374 19:24:40.530956
10375 19:24:40.536211 Connected to device vid:did:rid of 1ae0:0028:00
10376 19:24:40.542687
10377 19:24:40.545958 tpm_get_response: command 0x17b, return code 0x0
10378 19:24:40.546043
10379 19:24:40.552639 ec_init: CrosEC protocol v3 supported (256, 248)
10380 19:24:40.552723
10381 19:24:40.556258 tpm_cleanup: add release locality here.
10382 19:24:40.556340
10383 19:24:40.559595 Shutting down all USB controllers.
10384 19:24:40.559677
10385 19:24:40.562932 Removing current net device
10386 19:24:40.563014
10387 19:24:40.566051 Exiting depthcharge with code 4 at timestamp: 116416031
10388 19:24:40.566133
10389 19:24:40.572611 LZMA decompressing kernel-1 to 0x821a6718
10390 19:24:40.572694
10391 19:24:40.576088 LZMA decompressing kernel-1 to 0x40000000
10392 19:24:42.169699
10393 19:24:42.169917 jumping to kernel
10394 19:24:42.170719 end: 2.2.4 bootloader-commands (duration 00:01:29) [common]
10395 19:24:42.170894 start: 2.2.5 auto-login-action (timeout 00:02:56) [common]
10396 19:24:42.171025 Setting prompt string to ['Linux version [0-9]']
10397 19:24:42.171144 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10398 19:24:42.171262 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10399 19:24:42.251794
10400 19:24:42.255260 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10401 19:24:42.258575 start: 2.2.5.1 login-action (timeout 00:02:56) [common]
10402 19:24:42.258683 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10403 19:24:42.258762 Setting prompt string to []
10404 19:24:42.258848 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10405 19:24:42.258931 Using line separator: #'\n'#
10406 19:24:42.258997 No login prompt set.
10407 19:24:42.259063 Parsing kernel messages
10408 19:24:42.259123 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10409 19:24:42.259235 [login-action] Waiting for messages, (timeout 00:02:56)
10410 19:24:42.259308 Waiting using forced prompt support (timeout 00:01:28)
10411 19:24:42.278761 [ 0.000000] Linux version 6.1.86-cip19 (KernelCI@build-j170728-arm64-gcc-10-defconfig-arm64-chromebook-wrkxq) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Apr 18 19:05:54 UTC 2024
10412 19:24:42.281434 [ 0.000000] random: crng init done
10413 19:24:42.288256 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10414 19:24:42.291742 [ 0.000000] efi: UEFI not found.
10415 19:24:42.297832 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10416 19:24:42.304806 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10417 19:24:42.315159 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10418 19:24:42.324714 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10419 19:24:42.331390 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10420 19:24:42.337666 [ 0.000000] printk: bootconsole [mtk8250] enabled
10421 19:24:42.344354 [ 0.000000] NUMA: No NUMA configuration found
10422 19:24:42.351197 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10423 19:24:42.353940 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10424 19:24:42.357337 [ 0.000000] Zone ranges:
10425 19:24:42.364372 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10426 19:24:42.367557 [ 0.000000] DMA32 empty
10427 19:24:42.373753 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10428 19:24:42.377330 [ 0.000000] Movable zone start for each node
10429 19:24:42.380330 [ 0.000000] Early memory node ranges
10430 19:24:42.387286 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10431 19:24:42.393492 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10432 19:24:42.400470 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10433 19:24:42.406785 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10434 19:24:42.413528 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10435 19:24:42.420385 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10436 19:24:42.476567 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10437 19:24:42.482907 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10438 19:24:42.489311 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10439 19:24:42.492510 [ 0.000000] psci: probing for conduit method from DT.
10440 19:24:42.499062 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10441 19:24:42.502285 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10442 19:24:42.509364 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10443 19:24:42.512840 [ 0.000000] psci: SMC Calling Convention v1.2
10444 19:24:42.519646 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10445 19:24:42.522558 [ 0.000000] Detected VIPT I-cache on CPU0
10446 19:24:42.529257 [ 0.000000] CPU features: detected: GIC system register CPU interface
10447 19:24:42.535636 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10448 19:24:42.542060 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10449 19:24:42.548955 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10450 19:24:42.558610 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10451 19:24:42.565391 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10452 19:24:42.568595 [ 0.000000] alternatives: applying boot alternatives
10453 19:24:42.575284 [ 0.000000] Fallback order for Node 0: 0
10454 19:24:42.581825 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10455 19:24:42.585088 [ 0.000000] Policy zone: Normal
10456 19:24:42.598368 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10457 19:24:42.608414 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10458 19:24:42.620628 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10459 19:24:42.630899 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10460 19:24:42.637273 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10461 19:24:42.640648 <6>[ 0.000000] software IO TLB: area num 8.
10462 19:24:42.696919 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10463 19:24:42.846348 <6>[ 0.000000] Memory: 7913616K/8385536K available (18048K kernel code, 4118K rwdata, 22288K rodata, 8448K init, 616K bss, 439152K reserved, 32768K cma-reserved)
10464 19:24:42.853367 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10465 19:24:42.859535 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10466 19:24:42.863214 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10467 19:24:42.869717 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10468 19:24:42.875791 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10469 19:24:42.879413 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10470 19:24:42.889294 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10471 19:24:42.896544 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10472 19:24:42.902795 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10473 19:24:42.909195 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10474 19:24:42.913180 <6>[ 0.000000] GICv3: 608 SPIs implemented
10475 19:24:42.915942 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10476 19:24:42.922842 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10477 19:24:42.925977 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10478 19:24:42.932689 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10479 19:24:42.946154 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10480 19:24:42.955653 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10481 19:24:42.965662 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10482 19:24:42.973149 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10483 19:24:42.986098 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10484 19:24:42.992544 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10485 19:24:42.999213 <6>[ 0.009227] Console: colour dummy device 80x25
10486 19:24:43.009077 <6>[ 0.013956] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10487 19:24:43.015964 <6>[ 0.024463] pid_max: default: 32768 minimum: 301
10488 19:24:43.019647 <6>[ 0.029365] LSM: Security Framework initializing
10489 19:24:43.025982 <6>[ 0.034304] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10490 19:24:43.036212 <6>[ 0.042134] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10491 19:24:43.045532 <6>[ 0.051548] cblist_init_generic: Setting adjustable number of callback queues.
10492 19:24:43.048951 <6>[ 0.058989] cblist_init_generic: Setting shift to 3 and lim to 1.
10493 19:24:43.058916 <6>[ 0.065366] cblist_init_generic: Setting adjustable number of callback queues.
10494 19:24:43.065659 <6>[ 0.072793] cblist_init_generic: Setting shift to 3 and lim to 1.
10495 19:24:43.069016 <6>[ 0.079194] rcu: Hierarchical SRCU implementation.
10496 19:24:43.075805 <6>[ 0.084209] rcu: Max phase no-delay instances is 1000.
10497 19:24:43.082750 <6>[ 0.091264] EFI services will not be available.
10498 19:24:43.086154 <6>[ 0.096215] smp: Bringing up secondary CPUs ...
10499 19:24:43.093823 <6>[ 0.101259] Detected VIPT I-cache on CPU1
10500 19:24:43.100090 <6>[ 0.101331] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10501 19:24:43.107303 <6>[ 0.101363] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10502 19:24:43.110755 <6>[ 0.101698] Detected VIPT I-cache on CPU2
10503 19:24:43.117224 <6>[ 0.101752] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10504 19:24:43.127241 <6>[ 0.101771] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10505 19:24:43.130581 <6>[ 0.102031] Detected VIPT I-cache on CPU3
10506 19:24:43.136904 <6>[ 0.102079] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10507 19:24:43.143473 <6>[ 0.102094] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10508 19:24:43.146877 <6>[ 0.102398] CPU features: detected: Spectre-v4
10509 19:24:43.152983 <6>[ 0.102404] CPU features: detected: Spectre-BHB
10510 19:24:43.156331 <6>[ 0.102410] Detected PIPT I-cache on CPU4
10511 19:24:43.163206 <6>[ 0.102467] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10512 19:24:43.169864 <6>[ 0.102483] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10513 19:24:43.176274 <6>[ 0.102776] Detected PIPT I-cache on CPU5
10514 19:24:43.182785 <6>[ 0.102837] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10515 19:24:43.189691 <6>[ 0.102853] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10516 19:24:43.192783 <6>[ 0.103130] Detected PIPT I-cache on CPU6
10517 19:24:43.199691 <6>[ 0.103195] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10518 19:24:43.206345 <6>[ 0.103211] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10519 19:24:43.213058 <6>[ 0.103504] Detected PIPT I-cache on CPU7
10520 19:24:43.220003 <6>[ 0.103568] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10521 19:24:43.226515 <6>[ 0.103584] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10522 19:24:43.229791 <6>[ 0.103631] smp: Brought up 1 node, 8 CPUs
10523 19:24:43.236089 <6>[ 0.244988] SMP: Total of 8 processors activated.
10524 19:24:43.239411 <6>[ 0.249909] CPU features: detected: 32-bit EL0 Support
10525 19:24:43.249794 <6>[ 0.255273] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10526 19:24:43.256180 <6>[ 0.264073] CPU features: detected: Common not Private translations
10527 19:24:43.262948 <6>[ 0.270549] CPU features: detected: CRC32 instructions
10528 19:24:43.266074 <6>[ 0.275932] CPU features: detected: RCpc load-acquire (LDAPR)
10529 19:24:43.272745 <6>[ 0.281892] CPU features: detected: LSE atomic instructions
10530 19:24:43.279520 <6>[ 0.287674] CPU features: detected: Privileged Access Never
10531 19:24:43.286042 <6>[ 0.293454] CPU features: detected: RAS Extension Support
10532 19:24:43.292224 <6>[ 0.299062] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10533 19:24:43.295496 <6>[ 0.306282] CPU: All CPU(s) started at EL2
10534 19:24:43.302380 <6>[ 0.310599] alternatives: applying system-wide alternatives
10535 19:24:43.311323 <6>[ 0.321440] devtmpfs: initialized
10536 19:24:43.323880 <6>[ 0.330359] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10537 19:24:43.334130 <6>[ 0.340319] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10538 19:24:43.340037 <6>[ 0.348553] pinctrl core: initialized pinctrl subsystem
10539 19:24:43.343501 <6>[ 0.355197] DMI not present or invalid.
10540 19:24:43.350255 <6>[ 0.359609] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10541 19:24:43.360031 <6>[ 0.366493] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10542 19:24:43.367225 <6>[ 0.374079] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10543 19:24:43.376533 <6>[ 0.382316] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10544 19:24:43.379767 <6>[ 0.390555] audit: initializing netlink subsys (disabled)
10545 19:24:43.389715 <5>[ 0.396250] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10546 19:24:43.396519 <6>[ 0.396946] thermal_sys: Registered thermal governor 'step_wise'
10547 19:24:43.402916 <6>[ 0.404215] thermal_sys: Registered thermal governor 'power_allocator'
10548 19:24:43.406604 <6>[ 0.410471] cpuidle: using governor menu
10549 19:24:43.412865 <6>[ 0.421429] NET: Registered PF_QIPCRTR protocol family
10550 19:24:43.419682 <6>[ 0.426914] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10551 19:24:43.426347 <6>[ 0.434016] ASID allocator initialised with 32768 entries
10552 19:24:43.429481 <6>[ 0.440579] Serial: AMBA PL011 UART driver
10553 19:24:43.439827 <4>[ 0.449311] Trying to register duplicate clock ID: 134
10554 19:24:43.494315 <6>[ 0.507068] KASLR enabled
10555 19:24:43.507923 <6>[ 0.514806] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10556 19:24:43.514770 <6>[ 0.521818] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10557 19:24:43.521668 <6>[ 0.528307] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10558 19:24:43.528067 <6>[ 0.535310] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10559 19:24:43.534343 <6>[ 0.541797] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10560 19:24:43.541585 <6>[ 0.548800] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10561 19:24:43.547616 <6>[ 0.555286] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10562 19:24:43.554291 <6>[ 0.562290] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10563 19:24:43.557239 <6>[ 0.569814] ACPI: Interpreter disabled.
10564 19:24:43.566395 <6>[ 0.576234] iommu: Default domain type: Translated
10565 19:24:43.572852 <6>[ 0.581345] iommu: DMA domain TLB invalidation policy: strict mode
10566 19:24:43.576095 <5>[ 0.588004] SCSI subsystem initialized
10567 19:24:43.582527 <6>[ 0.592167] usbcore: registered new interface driver usbfs
10568 19:24:43.589042 <6>[ 0.597900] usbcore: registered new interface driver hub
10569 19:24:43.592425 <6>[ 0.603454] usbcore: registered new device driver usb
10570 19:24:43.599420 <6>[ 0.609542] pps_core: LinuxPPS API ver. 1 registered
10571 19:24:43.609381 <6>[ 0.614736] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10572 19:24:43.612733 <6>[ 0.624080] PTP clock support registered
10573 19:24:43.615812 <6>[ 0.628322] EDAC MC: Ver: 3.0.0
10574 19:24:43.623268 <6>[ 0.633477] FPGA manager framework
10575 19:24:43.629694 <6>[ 0.637159] Advanced Linux Sound Architecture Driver Initialized.
10576 19:24:43.632991 <6>[ 0.643945] vgaarb: loaded
10577 19:24:43.640107 <6>[ 0.647117] clocksource: Switched to clocksource arch_sys_counter
10578 19:24:43.642731 <5>[ 0.653564] VFS: Disk quotas dquot_6.6.0
10579 19:24:43.649458 <6>[ 0.657752] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10580 19:24:43.652955 <6>[ 0.664940] pnp: PnP ACPI: disabled
10581 19:24:43.661671 <6>[ 0.671616] NET: Registered PF_INET protocol family
10582 19:24:43.671617 <6>[ 0.677208] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10583 19:24:43.682764 <6>[ 0.689529] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10584 19:24:43.693127 <6>[ 0.698341] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10585 19:24:43.699287 <6>[ 0.706311] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10586 19:24:43.709114 <6>[ 0.715014] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10587 19:24:43.716271 <6>[ 0.724767] TCP: Hash tables configured (established 65536 bind 65536)
10588 19:24:43.722576 <6>[ 0.731629] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10589 19:24:43.731975 <6>[ 0.738828] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10590 19:24:43.738965 <6>[ 0.746530] NET: Registered PF_UNIX/PF_LOCAL protocol family
10591 19:24:43.742156 <6>[ 0.752679] RPC: Registered named UNIX socket transport module.
10592 19:24:43.748763 <6>[ 0.758832] RPC: Registered udp transport module.
10593 19:24:43.751954 <6>[ 0.763763] RPC: Registered tcp transport module.
10594 19:24:43.758843 <6>[ 0.768692] RPC: Registered tcp NFSv4.1 backchannel transport module.
10595 19:24:43.765653 <6>[ 0.775357] PCI: CLS 0 bytes, default 64
10596 19:24:43.769151 <6>[ 0.779616] Unpacking initramfs...
10597 19:24:43.785378 <6>[ 0.791689] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10598 19:24:43.795008 <6>[ 0.800355] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10599 19:24:43.798460 <6>[ 0.809204] kvm [1]: IPA Size Limit: 40 bits
10600 19:24:43.805275 <6>[ 0.813733] kvm [1]: GICv3: no GICV resource entry
10601 19:24:43.808644 <6>[ 0.818754] kvm [1]: disabling GICv2 emulation
10602 19:24:43.815013 <6>[ 0.823440] kvm [1]: GIC system register CPU interface enabled
10603 19:24:43.821741 <6>[ 0.831152] kvm [1]: vgic interrupt IRQ18
10604 19:24:43.824765 <6>[ 0.835522] kvm [1]: VHE mode initialized successfully
10605 19:24:43.832259 <5>[ 0.841967] Initialise system trusted keyrings
10606 19:24:43.838653 <6>[ 0.846718] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10607 19:24:43.846678 <6>[ 0.856727] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10608 19:24:43.853717 <5>[ 0.863113] NFS: Registering the id_resolver key type
10609 19:24:43.856755 <5>[ 0.868408] Key type id_resolver registered
10610 19:24:43.863454 <5>[ 0.872819] Key type id_legacy registered
10611 19:24:43.869967 <6>[ 0.877099] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10612 19:24:43.876712 <6>[ 0.884021] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10613 19:24:43.883366 <6>[ 0.891753] 9p: Installing v9fs 9p2000 file system support
10614 19:24:43.920207 <5>[ 0.929863] Key type asymmetric registered
10615 19:24:43.923502 <5>[ 0.934190] Asymmetric key parser 'x509' registered
10616 19:24:43.932940 <6>[ 0.939328] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10617 19:24:43.936327 <6>[ 0.946955] io scheduler mq-deadline registered
10618 19:24:43.939721 <6>[ 0.951721] io scheduler kyber registered
10619 19:24:43.958922 <6>[ 0.968837] EINJ: ACPI disabled.
10620 19:24:43.991138 <4>[ 0.994502] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10621 19:24:44.000900 <4>[ 1.005117] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10622 19:24:44.015480 <6>[ 1.025486] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10623 19:24:44.023315 <6>[ 1.033403] printk: console [ttyS0] disabled
10624 19:24:44.051521 <6>[ 1.058033] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10625 19:24:44.058137 <6>[ 1.067505] printk: console [ttyS0] enabled
10626 19:24:44.061533 <6>[ 1.067505] printk: console [ttyS0] enabled
10627 19:24:44.068098 <6>[ 1.076400] printk: bootconsole [mtk8250] disabled
10628 19:24:44.071464 <6>[ 1.076400] printk: bootconsole [mtk8250] disabled
10629 19:24:44.077897 <6>[ 1.087469] SuperH (H)SCI(F) driver initialized
10630 19:24:44.081002 <6>[ 1.092748] msm_serial: driver initialized
10631 19:24:44.095184 <6>[ 1.101644] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10632 19:24:44.105106 <6>[ 1.110191] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10633 19:24:44.111729 <6>[ 1.118734] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10634 19:24:44.121561 <6>[ 1.127360] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10635 19:24:44.128174 <6>[ 1.136066] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10636 19:24:44.138178 <6>[ 1.144779] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10637 19:24:44.148212 <6>[ 1.153319] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10638 19:24:44.154447 <6>[ 1.162118] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10639 19:24:44.164545 <6>[ 1.170660] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10640 19:24:44.176388 <6>[ 1.186275] loop: module loaded
10641 19:24:44.182767 <6>[ 1.192167] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10642 19:24:44.204997 <4>[ 1.215158] mtk-pmic-keys: Failed to locate of_node [id: -1]
10643 19:24:44.211887 <6>[ 1.222012] megasas: 07.719.03.00-rc1
10644 19:24:44.221667 <6>[ 1.231732] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10645 19:24:44.232580 <6>[ 1.242491] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10646 19:24:44.249576 <6>[ 1.259330] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10647 19:24:44.306439 <6>[ 1.309427] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10648 19:24:45.982822 <6>[ 2.993217] Freeing initrd memory: 50948K
10649 19:24:45.994815 <6>[ 3.004959] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10650 19:24:46.005836 <6>[ 3.015957] tun: Universal TUN/TAP device driver, 1.6
10651 19:24:46.008922 <6>[ 3.022013] thunder_xcv, ver 1.0
10652 19:24:46.012262 <6>[ 3.025522] thunder_bgx, ver 1.0
10653 19:24:46.015629 <6>[ 3.029019] nicpf, ver 1.0
10654 19:24:46.026137 <6>[ 3.033053] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10655 19:24:46.029693 <6>[ 3.040529] hns3: Copyright (c) 2017 Huawei Corporation.
10656 19:24:46.032584 <6>[ 3.046115] hclge is initializing
10657 19:24:46.039495 <6>[ 3.049691] e1000: Intel(R) PRO/1000 Network Driver
10658 19:24:46.046019 <6>[ 3.054820] e1000: Copyright (c) 1999-2006 Intel Corporation.
10659 19:24:46.049484 <6>[ 3.060833] e1000e: Intel(R) PRO/1000 Network Driver
10660 19:24:46.056218 <6>[ 3.066049] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10661 19:24:46.062907 <6>[ 3.072237] igb: Intel(R) Gigabit Ethernet Network Driver
10662 19:24:46.069074 <6>[ 3.077887] igb: Copyright (c) 2007-2014 Intel Corporation.
10663 19:24:46.075729 <6>[ 3.083726] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10664 19:24:46.082530 <6>[ 3.090245] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10665 19:24:46.085848 <6>[ 3.096706] sky2: driver version 1.30
10666 19:24:46.092509 <6>[ 3.101711] VFIO - User Level meta-driver version: 0.3
10667 19:24:46.099940 <6>[ 3.109952] usbcore: registered new interface driver usb-storage
10668 19:24:46.106321 <6>[ 3.116401] usbcore: registered new device driver onboard-usb-hub
10669 19:24:46.115261 <6>[ 3.125526] mt6397-rtc mt6359-rtc: registered as rtc0
10670 19:24:46.125565 <6>[ 3.130988] mt6397-rtc mt6359-rtc: setting system clock to 2024-04-18T19:24:45 UTC (1713468285)
10671 19:24:46.128347 <6>[ 3.140560] i2c_dev: i2c /dev entries driver
10672 19:24:46.145777 <6>[ 3.152535] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10673 19:24:46.152597 <4>[ 3.161272] cpu cpu0: supply cpu not found, using dummy regulator
10674 19:24:46.158726 <4>[ 3.167718] cpu cpu1: supply cpu not found, using dummy regulator
10675 19:24:46.165277 <4>[ 3.174129] cpu cpu2: supply cpu not found, using dummy regulator
10676 19:24:46.171870 <4>[ 3.180525] cpu cpu3: supply cpu not found, using dummy regulator
10677 19:24:46.178615 <4>[ 3.186926] cpu cpu4: supply cpu not found, using dummy regulator
10678 19:24:46.185356 <4>[ 3.193324] cpu cpu5: supply cpu not found, using dummy regulator
10679 19:24:46.192083 <4>[ 3.199736] cpu cpu6: supply cpu not found, using dummy regulator
10680 19:24:46.198209 <4>[ 3.206132] cpu cpu7: supply cpu not found, using dummy regulator
10681 19:24:46.216263 <6>[ 3.226772] cpu cpu0: EM: created perf domain
10682 19:24:46.219696 <6>[ 3.231703] cpu cpu4: EM: created perf domain
10683 19:24:46.226865 <6>[ 3.237347] sdhci: Secure Digital Host Controller Interface driver
10684 19:24:46.233797 <6>[ 3.243781] sdhci: Copyright(c) Pierre Ossman
10685 19:24:46.240217 <6>[ 3.248736] Synopsys Designware Multimedia Card Interface Driver
10686 19:24:46.246749 <6>[ 3.255399] sdhci-pltfm: SDHCI platform and OF driver helper
10687 19:24:46.250265 <6>[ 3.255456] mmc0: CQHCI version 5.10
10688 19:24:46.256765 <6>[ 3.265467] ledtrig-cpu: registered to indicate activity on CPUs
10689 19:24:46.263230 <6>[ 3.272556] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10690 19:24:46.269806 <6>[ 3.279619] usbcore: registered new interface driver usbhid
10691 19:24:46.273428 <6>[ 3.285445] usbhid: USB HID core driver
10692 19:24:46.279911 <6>[ 3.289658] spi_master spi0: will run message pump with realtime priority
10693 19:24:46.321616 <6>[ 3.325659] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10694 19:24:46.340590 <6>[ 3.340846] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10695 19:24:46.347723 <6>[ 3.355629] cros-ec-spi spi0.0: Chrome EC device registered
10696 19:24:46.350897 <6>[ 3.361701] mmc0: Command Queue Engine enabled
10697 19:24:46.358025 <6>[ 3.366453] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10698 19:24:46.364279 <6>[ 3.374007] mmcblk0: mmc0:0001 DA4128 116 GiB
10699 19:24:46.372605 <6>[ 3.382882] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10700 19:24:46.379659 <6>[ 3.390116] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10701 19:24:46.386637 <6>[ 3.396051] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10702 19:24:46.396740 <6>[ 3.401209] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10703 19:24:46.403370 <6>[ 3.401943] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10704 19:24:46.406132 <6>[ 3.411798] NET: Registered PF_PACKET protocol family
10705 19:24:46.413083 <6>[ 3.422495] 9pnet: Installing 9P2000 support
10706 19:24:46.416418 <5>[ 3.427057] Key type dns_resolver registered
10707 19:24:46.419672 <6>[ 3.432022] registered taskstats version 1
10708 19:24:46.426250 <5>[ 3.436412] Loading compiled-in X.509 certificates
10709 19:24:46.454259 <4>[ 3.457984] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10710 19:24:46.464247 <4>[ 3.468705] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10711 19:24:46.470928 <3>[ 3.479333] debugfs: File 'uA_load' in directory '/' already present!
10712 19:24:46.477634 <3>[ 3.486049] debugfs: File 'min_uV' in directory '/' already present!
10713 19:24:46.484386 <3>[ 3.492664] debugfs: File 'max_uV' in directory '/' already present!
10714 19:24:46.490959 <3>[ 3.499275] debugfs: File 'constraint_flags' in directory '/' already present!
10715 19:24:46.502093 <3>[ 3.509068] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10716 19:24:46.511995 <6>[ 3.522007] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10717 19:24:46.518563 <6>[ 3.529034] xhci-mtk 11200000.usb: xHCI Host Controller
10718 19:24:46.525107 <6>[ 3.534547] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10719 19:24:46.535188 <6>[ 3.542394] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10720 19:24:46.541895 <6>[ 3.551815] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10721 19:24:46.548589 <6>[ 3.557885] xhci-mtk 11200000.usb: xHCI Host Controller
10722 19:24:46.555143 <6>[ 3.563359] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10723 19:24:46.562170 <6>[ 3.571004] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10724 19:24:46.568356 <6>[ 3.578622] hub 1-0:1.0: USB hub found
10725 19:24:46.571554 <6>[ 3.582633] hub 1-0:1.0: 1 port detected
10726 19:24:46.578081 <6>[ 3.586903] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10727 19:24:46.585113 <6>[ 3.595451] hub 2-0:1.0: USB hub found
10728 19:24:46.588704 <6>[ 3.599456] hub 2-0:1.0: 1 port detected
10729 19:24:46.596546 <6>[ 3.607018] mtk-msdc 11f70000.mmc: Got CD GPIO
10730 19:24:46.608202 <6>[ 3.615293] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10731 19:24:46.614870 <6>[ 3.623362] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10732 19:24:46.625124 <4>[ 3.631513] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10733 19:24:46.634777 <6>[ 3.641235] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10734 19:24:46.641275 <6>[ 3.649323] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10735 19:24:46.651045 <6>[ 3.657456] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10736 19:24:46.657921 <6>[ 3.665395] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10737 19:24:46.664523 <6>[ 3.673212] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10738 19:24:46.674578 <6>[ 3.681032] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10739 19:24:46.684470 <6>[ 3.691396] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10740 19:24:46.694425 <6>[ 3.699750] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10741 19:24:46.700638 <6>[ 3.708089] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10742 19:24:46.711067 <6>[ 3.716426] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10743 19:24:46.717715 <6>[ 3.724763] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10744 19:24:46.727384 <6>[ 3.733102] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10745 19:24:46.733940 <6>[ 3.741464] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10746 19:24:46.743880 <6>[ 3.749801] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10747 19:24:46.750379 <6>[ 3.758140] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10748 19:24:46.760304 <6>[ 3.766477] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10749 19:24:46.767076 <6>[ 3.774817] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10750 19:24:46.777058 <6>[ 3.783156] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10751 19:24:46.783649 <6>[ 3.791496] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10752 19:24:46.793291 <6>[ 3.799834] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10753 19:24:46.799716 <6>[ 3.808171] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10754 19:24:46.806867 <6>[ 3.816955] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10755 19:24:46.814018 <6>[ 3.824234] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10756 19:24:46.821060 <6>[ 3.831166] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10757 19:24:46.831183 <6>[ 3.838047] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10758 19:24:46.838167 <6>[ 3.845079] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10759 19:24:46.844036 <6>[ 3.851967] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10760 19:24:46.854028 <6>[ 3.861097] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10761 19:24:46.863922 <6>[ 3.870218] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10762 19:24:46.873723 <6>[ 3.879521] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10763 19:24:46.883655 <6>[ 3.888988] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10764 19:24:46.893818 <6>[ 3.898455] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10765 19:24:46.900469 <6>[ 3.907575] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10766 19:24:46.910342 <6>[ 3.917042] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10767 19:24:46.920149 <6>[ 3.926160] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10768 19:24:46.930319 <6>[ 3.935455] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10769 19:24:46.939868 <6>[ 3.945615] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10770 19:24:46.950140 <6>[ 3.957476] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10771 19:24:46.995986 <6>[ 4.003382] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10772 19:24:47.150821 <6>[ 4.161288] hub 1-1:1.0: USB hub found
10773 19:24:47.153972 <6>[ 4.165823] hub 1-1:1.0: 4 ports detected
10774 19:24:47.164306 <6>[ 4.174494] hub 1-1:1.0: USB hub found
10775 19:24:47.167394 <6>[ 4.178869] hub 1-1:1.0: 4 ports detected
10776 19:24:47.277410 <6>[ 4.283729] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10777 19:24:47.303067 <6>[ 4.313167] hub 2-1:1.0: USB hub found
10778 19:24:47.305952 <6>[ 4.317695] hub 2-1:1.0: 3 ports detected
10779 19:24:47.315512 <6>[ 4.325679] hub 2-1:1.0: USB hub found
10780 19:24:47.318349 <6>[ 4.330134] hub 2-1:1.0: 3 ports detected
10781 19:24:47.492438 <6>[ 4.499426] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10782 19:24:47.624681 <6>[ 4.635154] hub 1-1.4:1.0: USB hub found
10783 19:24:47.627789 <6>[ 4.639743] hub 1-1.4:1.0: 2 ports detected
10784 19:24:47.637169 <6>[ 4.647232] hub 1-1.4:1.0: USB hub found
10785 19:24:47.639917 <6>[ 4.651822] hub 1-1.4:1.0: 2 ports detected
10786 19:24:47.704150 <6>[ 4.711608] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10787 19:24:47.936328 <6>[ 4.943441] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10788 19:24:48.128136 <6>[ 5.135458] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10789 19:24:59.225402 <6>[ 16.240452] ALSA device list:
10790 19:24:59.231860 <6>[ 16.243746] No soundcards found.
10791 19:24:59.239942 <6>[ 16.251762] Freeing unused kernel memory: 8448K
10792 19:24:59.243206 <6>[ 16.257445] Run /init as init process
10793 19:24:59.282782 <6>[ 16.294409] NET: Registered PF_INET6 protocol family
10794 19:24:59.289473 <6>[ 16.300698] Segment Routing with IPv6
10795 19:24:59.292671 <6>[ 16.304643] In-situ OAM (IOAM) with IPv6
10796 19:24:59.334956 <30>[ 16.320402] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10797 19:24:59.341813 <30>[ 16.353584] systemd[1]: Detected architecture arm64.
10798 19:24:59.341937
10799 19:24:59.348281 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10800 19:24:59.348384
10801 19:24:59.348450
10802 19:24:59.363633 <30>[ 16.375445] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10803 19:24:59.489329 <30>[ 16.497686] systemd[1]: Queued start job for default target graphical.target.
10804 19:24:59.528710 <30>[ 16.536787] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10805 19:24:59.535286 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10806 19:24:59.535409
10807 19:24:59.555436 <30>[ 16.563917] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10808 19:24:59.562254 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10809 19:24:59.565297
10810 19:24:59.583623 <30>[ 16.591890] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10811 19:24:59.593475 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10812 19:24:59.593618
10813 19:24:59.611624 <30>[ 16.620302] systemd[1]: Created slice user.slice - User and Session Slice.
10814 19:24:59.618697 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10815 19:24:59.618821
10816 19:24:59.638434 <30>[ 16.643466] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10817 19:24:59.644692 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10818 19:24:59.644812
10819 19:24:59.666944 <30>[ 16.672081] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10820 19:24:59.673397 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10821 19:24:59.673531
10822 19:24:59.701196 <30>[ 16.699859] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10823 19:24:59.711039 <30>[ 16.719740] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10824 19:24:59.718183 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10825 19:24:59.718304
10826 19:24:59.735218 <30>[ 16.743762] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10827 19:24:59.741908 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10828 19:24:59.745295
10829 19:24:59.763664 <30>[ 16.771893] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10830 19:24:59.773404 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10831 19:24:59.773549
10832 19:24:59.788412 <30>[ 16.799979] systemd[1]: Reached target paths.target - Path Units.
10833 19:24:59.794954 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10834 19:24:59.798062
10835 19:24:59.815272 <30>[ 16.823852] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10836 19:24:59.821874 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10837 19:24:59.821996
10838 19:24:59.838671 <30>[ 16.847388] systemd[1]: Reached target slices.target - Slice Units.
10839 19:24:59.845143 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10840 19:24:59.845256
10841 19:24:59.859894 <30>[ 16.871892] systemd[1]: Reached target swap.target - Swaps.
10842 19:24:59.866936 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10843 19:24:59.867063
10844 19:24:59.887850 <30>[ 16.895897] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10845 19:24:59.897109 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10846 19:24:59.897253
10847 19:24:59.915541 <30>[ 16.923870] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10848 19:24:59.925244 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10849 19:24:59.925400
10850 19:24:59.945093 <30>[ 16.953493] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10851 19:24:59.954797 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10852 19:24:59.954929
10853 19:24:59.972068 <30>[ 16.980032] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10854 19:24:59.981384 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10855 19:24:59.981548
10856 19:24:59.999572 <30>[ 17.008022] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10857 19:25:00.006306 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10858 19:25:00.006455
10859 19:25:00.023428 <30>[ 17.032061] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10860 19:25:00.033489 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10861 19:25:00.033667
10862 19:25:00.052601 <30>[ 17.060818] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10863 19:25:00.062022 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10864 19:25:00.062159
10865 19:25:00.080328 <30>[ 17.088512] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10866 19:25:00.090013 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10867 19:25:00.090240
10868 19:25:00.130984 <30>[ 17.139496] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10869 19:25:00.137332 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10870 19:25:00.137478
10871 19:25:00.157957 <30>[ 17.166595] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10872 19:25:00.164479 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10873 19:25:00.164611
10874 19:25:00.187378 <30>[ 17.195978] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10875 19:25:00.194372 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10876 19:25:00.194514
10877 19:25:00.222000 <30>[ 17.223985] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10878 19:25:00.236130 <30>[ 17.244513] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10879 19:25:00.245930 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10880 19:25:00.246065
10881 19:25:00.268317 <30>[ 17.276621] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10882 19:25:00.274655 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10883 19:25:00.274777
10884 19:25:00.299856 <30>[ 17.308682] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10885 19:25:00.309690 Startin<6>[ 17.318060] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10886 19:25:00.316469 g [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10887 19:25:00.316596
10888 19:25:00.371582 <30>[ 17.380177] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10889 19:25:00.378109 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10890 19:25:00.378217
10891 19:25:00.404216 <30>[ 17.412676] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10892 19:25:00.410874 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10893 19:25:00.414256
10894 19:25:00.451051 <30>[ 17.459651] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10895 19:25:00.457519 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10896 19:25:00.457650
10897 19:25:00.483684 <30>[ 17.492094] systemd[1]: Starting systemd-journald.service - Journal Service...
10898 19:25:00.490264 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10899 19:25:00.490383
10900 19:25:00.509876 <30>[ 17.518233] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10901 19:25:00.515999 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10902 19:25:00.516111
10903 19:25:00.543122 <30>[ 17.547912] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10904 19:25:00.549213 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10905 19:25:00.549327
10906 19:25:00.603567 <30>[ 17.611998] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10907 19:25:00.613336 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10908 19:25:00.613475
10909 19:25:00.636197 <30>[ 17.644427] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10910 19:25:00.642907 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10911 19:25:00.643028
10912 19:25:00.670094 <30>[ 17.678849] systemd[1]: Started systemd-journald.service - Journal Service.
10913 19:25:00.676624 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10914 19:25:00.676738
10915 19:25:00.699033 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10916 19:25:00.699177
10917 19:25:00.715706 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10918 19:25:00.715856
10919 19:25:00.736312 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10920 19:25:00.736461
10921 19:25:00.756519 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10922 19:25:00.756670
10923 19:25:00.776649 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10924 19:25:00.776798
10925 19:25:00.800425 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10926 19:25:00.800575
10927 19:25:00.825945 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10928 19:25:00.826097
10929 19:25:00.852079 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10930 19:25:00.852228
10931 19:25:00.874290 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10932 19:25:00.874436
10933 19:25:00.896813 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10934 19:25:00.896960
10935 19:25:00.920576 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10936 19:25:00.920728
10937 19:25:00.945190 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10938 19:25:00.945342
10939 19:25:00.963831 See 'systemctl status systemd-remount-fs.service' for details.
10940 19:25:00.963976
10941 19:25:00.984189 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10942 19:25:00.984337
10943 19:25:01.005326 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10944 19:25:01.005503
10945 19:25:01.067602 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10946 19:25:01.067752
10947 19:25:01.091782 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10948 19:25:01.091930
10949 19:25:01.109337 <46>[ 18.118281] systemd-journald[190]: Received client request to flush runtime journal.
10950 19:25:01.122004 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10951 19:25:01.122151
10952 19:25:01.142408 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10953 19:25:01.142560
10954 19:25:01.166041 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10955 19:25:01.166187
10956 19:25:01.189598 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10957 19:25:01.189749
10958 19:25:01.208450 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10959 19:25:01.208619
10960 19:25:01.232732 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10961 19:25:01.232881
10962 19:25:01.252395 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10963 19:25:01.252552
10964 19:25:01.272261 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10965 19:25:01.272409
10966 19:25:01.315613 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10967 19:25:01.315765
10968 19:25:01.347757 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10969 19:25:01.347946
10970 19:25:01.371622 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10971 19:25:01.371770
10972 19:25:01.391062 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10973 19:25:01.391216
10974 19:25:01.435918 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10975 19:25:01.436067
10976 19:25:01.460970 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10977 19:25:01.461118
10978 19:25:01.486382 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10979 19:25:01.486535
10980 19:25:01.531124 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10981 19:25:01.531279
10982 19:25:01.558061 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10983 19:25:01.558212
10984 19:25:01.578758 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10985 19:25:01.578914
10986 19:25:01.633047 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10987 19:25:01.633197
10988 19:25:01.657362 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10989 19:25:01.657520
10990 19:25:01.701077 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10991 19:25:01.701227
10992 19:25:01.804112 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10993 19:25:01.804259
10994 19:25:01.824172 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10995 19:25:01.824319
10996 19:25:01.844673 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10997 19:25:01.844819
10998 19:25:01.868743 [[0;32m OK [0m] Started [0;1;39mfstrim.time<3>[ 18.878194] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10999 19:25:01.878784 r[0m - Discard <6>[ 18.878386] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
11000 19:25:01.888352 unused blocks on<3>[ 18.886471] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11001 19:25:01.888487 ce a week.
11002 19:25:01.888553
11003 19:25:01.895211 <3>[ 18.904630] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11004 19:25:01.905868 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11005 19:25:01.906032
11006 19:25:01.915872 <3>[ 18.923480] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11007 19:25:01.919259 <6>[ 18.926536] remoteproc remoteproc0: scp is available
11008 19:25:01.929340 <3>[ 18.931607] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11009 19:25:01.932830 <6>[ 18.936935] remoteproc remoteproc0: powering up scp
11010 19:25:01.938925 <6>[ 18.942488] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
11011 19:25:01.948852 <6>[ 18.942508] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
11012 19:25:01.958839 <6>[ 18.942513] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
11013 19:25:01.965691 <3>[ 18.944899] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11014 19:25:01.975425 <6>[ 18.950030] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
11015 19:25:01.981911 <3>[ 18.957591] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11016 19:25:01.988868 <6>[ 18.966291] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
11017 19:25:01.995865 <3>[ 18.974961] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11018 19:25:02.002239 <4>[ 18.980959] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
11019 19:25:02.011943 <4>[ 18.982817] elants_i2c 4-0010: supply vccio not found, using dummy regulator
11020 19:25:02.015213 <6>[ 19.007245] mc: Linux media interface: v0.10
11021 19:25:02.022075 <3>[ 19.016824] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11022 19:25:02.032156 <6>[ 19.035761] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
11023 19:25:02.044968 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message<3>[ 19.054233] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11024 19:25:02.048295 Bus Socket.
11025 19:25:02.048388
11026 19:25:02.054977 <3>[ 19.063826] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11027 19:25:02.061963 <6>[ 19.067619] videodev: Linux video capture interface: v2.00
11028 19:25:02.068346 <3>[ 19.073058] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11029 19:25:02.078407 <6>[ 19.078879] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
11030 19:25:02.085457 <4>[ 19.083484] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
11031 19:25:02.088828 <4>[ 19.083484] Fallback method does not support PEC.
11032 19:25:02.098733 <3>[ 19.087699] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11033 19:25:02.105660 <6>[ 19.093931] pci_bus 0000:00: root bus resource [bus 00-ff]
11034 19:25:02.112682 <6>[ 19.095385] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
11035 19:25:02.122774 <3>[ 19.098990] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11036 19:25:02.128930 <3>[ 19.107509] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11037 19:25:02.140158 <3>[ 19.107521] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11038 19:25:02.146357 <3>[ 19.107535] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11039 19:25:02.153157 <6>[ 19.108423] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
11040 19:25:02.159388 <6>[ 19.110215] usbcore: registered new device driver r8152-cfgselector
11041 19:25:02.166296 <6>[ 19.115622] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
11042 19:25:02.177278 <6>[ 19.121365] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
11043 19:25:02.183662 <6>[ 19.121376] remoteproc remoteproc0: remote processor scp is now up
11044 19:25:02.190010 <3>[ 19.121405] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11045 19:25:02.197116 <3>[ 19.121487] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11046 19:25:02.207344 <6>[ 19.122298] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
11047 19:25:02.213992 <6>[ 19.123621] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
11048 19:25:02.224755 <3>[ 19.127301] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11049 19:25:02.234686 <6>[ 19.130817] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
11050 19:25:02.242439 <3>[ 19.152939] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11051 19:25:02.248923 <6>[ 19.155783] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
11052 19:25:02.258632 <6>[ 19.172689] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
11053 19:25:02.265334 <6>[ 19.177510] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
11054 19:25:02.275526 <6>[ 19.185090] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
11055 19:25:02.282683 <3>[ 19.189304] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11056 19:25:02.289297 <6>[ 19.193127] pci 0000:00:00.0: supports D1 D2
11057 19:25:02.296229 <6>[ 19.199446] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
11058 19:25:02.305864 <4>[ 19.222559] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
11059 19:25:02.315851 <3>[ 19.223060] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11060 19:25:02.323055 <3>[ 19.223904] power_supply sbs-5-000b: driver failed to report `health' property: -6
11061 19:25:02.330088 <6>[ 19.223911] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11062 19:25:02.336466 <6>[ 19.225262] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
11063 19:25:02.342991 <6>[ 19.225740] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
11064 19:25:02.353194 <6>[ 19.225815] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
11065 19:25:02.359766 <6>[ 19.225852] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
11066 19:25:02.365854 <6>[ 19.225879] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11067 19:25:02.372852 <6>[ 19.226165] pci 0000:01:00.0: supports D1 D2
11068 19:25:02.379605 <6>[ 19.226176] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11069 19:25:02.385652 <4>[ 19.232193] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
11070 19:25:02.392526 <6>[ 19.239184] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11071 19:25:02.402752 <3>[ 19.246361] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11072 19:25:02.409836 <6>[ 19.251000] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11073 19:25:02.413275 <6>[ 19.251622] Bluetooth: Core ver 2.22
11074 19:25:02.420070 <6>[ 19.251681] NET: Registered PF_BLUETOOTH protocol family
11075 19:25:02.427243 <6>[ 19.251682] Bluetooth: HCI device and connection manager initialized
11076 19:25:02.430450 <6>[ 19.251698] Bluetooth: HCI socket layer initialized
11077 19:25:02.437071 <6>[ 19.251704] Bluetooth: L2CAP socket layer initialized
11078 19:25:02.440428 <6>[ 19.251715] Bluetooth: SCO socket layer initialized
11079 19:25:02.451214 <3>[ 19.261137] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11080 19:25:02.457789 <6>[ 19.261290] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11081 19:25:02.471744 <6>[ 19.262725] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11082 19:25:02.475152 <6>[ 19.262873] usbcore: registered new interface driver uvcvideo
11083 19:25:02.485338 <6>[ 19.266228] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11084 19:25:02.491560 <3>[ 19.299078] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11085 19:25:02.501862 <6>[ 19.301534] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11086 19:25:02.504806 <6>[ 19.302288] usbcore: registered new interface driver btusb
11087 19:25:02.518454 <4>[ 19.302967] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11088 19:25:02.521660 <3>[ 19.302980] Bluetooth: hci0: Failed to load firmware file (-2)
11089 19:25:02.528086 <3>[ 19.302985] Bluetooth: hci0: Failed to set up firmware (-2)
11090 19:25:02.538107 <4>[ 19.302991] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11091 19:25:02.544904 <6>[ 19.303842] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11092 19:25:02.551444 <6>[ 19.315316] r8152 2-1.3:1.0 eth0: v1.12.13
11093 19:25:02.558104 <6>[ 19.323535] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11094 19:25:02.564459 <6>[ 19.332671] usbcore: registered new interface driver r8152
11095 19:25:02.570915 <6>[ 19.340045] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11096 19:25:02.580841 <3>[ 19.341255] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11097 19:25:02.587484 <6>[ 19.376886] usbcore: registered new interface driver cdc_ether
11098 19:25:02.590859 <6>[ 19.383826] pci 0000:00:00.0: PCI bridge to [bus 01]
11099 19:25:02.597413 <6>[ 19.403649] usbcore: registered new interface driver r8153_ecm
11100 19:25:02.604383 <6>[ 19.410136] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11101 19:25:02.610451 <6>[ 19.410284] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11102 19:25:02.617147 <6>[ 19.434146] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
11103 19:25:02.624022 <6>[ 19.436924] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
11104 19:25:02.630493 [[0;32m OK [<6>[ 19.642001] pcieport 0000:00:00.0: AER: enabled with IRQ 283
11105 19:25:02.637091 0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11106 19:25:02.637205
11107 19:25:02.651617 <5>[ 19.660442] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11108 19:25:02.674790 <5>[ 19.683419] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11109 19:25:02.681450 <5>[ 19.690705] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
11110 19:25:02.691449 <4>[ 19.699233] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11111 19:25:02.697751 <6>[ 19.708207] cfg80211: failed to load regulatory.db
11112 19:25:02.712041 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11113 19:25:02.712188
11114 19:25:02.739407 [[0;32m OK [0m] Reached target [0;1;39mbasi<6>[ 19.748010] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11115 19:25:02.745848 c.target[0m - B<6>[ 19.756216] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11116 19:25:02.749132 asic System.
11117 19:25:02.749228
11118 19:25:02.772355 <6>[ 19.784262] mt7921e 0000:01:00.0: ASIC revision: 79610010
11119 19:25:02.809409 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11120 19:25:02.809610
11121 19:25:02.844457 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11122 19:25:02.844610
11123 19:25:02.866505 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11124 19:25:02.866651
11125 19:25:02.873288 <6>[ 19.883181] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
11126 19:25:02.876531 <6>[ 19.883181]
11127 19:25:02.886505 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11128 19:25:02.886630
11129 19:25:02.953479 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11130 19:25:02.953636
11131 19:25:02.973420 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11132 19:25:02.973550
11133 19:25:02.991607 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11134 19:25:02.991707
11135 19:25:03.008123 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11136 19:25:03.008215
11137 19:25:03.031701 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11138 19:25:03.031795
11139 19:25:03.096170 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11140 19:25:03.096294
11141 19:25:03.121477 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11142 19:25:03.121628
11143 19:25:03.142176 <6>[ 20.150959] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
11144 19:25:03.151907 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11145 19:25:03.151999
11146 19:25:03.168683 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11147 19:25:03.168783
11148 19:25:03.236209 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11149 19:25:03.236359
11150 19:25:03.254193 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11151 19:25:03.254282
11152 19:25:03.271320 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11153 19:25:03.271405
11154 19:25:03.287004 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11155 19:25:03.287089
11156 19:25:03.303089 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11157 19:25:03.303175
11158 19:25:03.360438 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11159 19:25:03.360576
11160 19:25:03.385712 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11161 19:25:03.385810
11162 19:25:03.409230 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11163 19:25:03.409336
11164 19:25:03.449375 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11165 19:25:03.449530
11166 19:25:03.503934
11167 19:25:03.504110
11168 19:25:03.507238 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11169 19:25:03.507339
11170 19:25:03.510146 debian-bookworm-arm64 login: root (automatic login)
11171 19:25:03.510256
11172 19:25:03.510370
11173 19:25:03.523888 Linux debian-bookworm-arm64 6.1.86-cip19 #1 SMP PREEMPT Thu Apr 18 19:05:54 UTC 2024 aarch64
11174 19:25:03.523984
11175 19:25:03.530870 The programs included with the Debian GNU/Linux system are free software;
11176 19:25:03.537285 the exact distribution terms for each program are described in the
11177 19:25:03.540412 individual files in /usr/share/doc/*/copyright.
11178 19:25:03.540494
11179 19:25:03.546952 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11180 19:25:03.550712 permitted by applicable law.
11181 19:25:03.551140 Matched prompt #10: / #
11183 19:25:03.551346 Setting prompt string to ['/ #']
11184 19:25:03.551439 end: 2.2.5.1 login-action (duration 00:00:21) [common]
11186 19:25:03.551632 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
11187 19:25:03.551720 start: 2.2.6 expect-shell-connection (timeout 00:02:35) [common]
11188 19:25:03.551790 Setting prompt string to ['/ #']
11189 19:25:03.551850 Forcing a shell prompt, looking for ['/ #']
11191 19:25:03.602084 / #
11192 19:25:03.602271 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11193 19:25:03.602349 Waiting using forced prompt support (timeout 00:02:30)
11194 19:25:03.606887
11195 19:25:03.607171 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11196 19:25:03.607270 start: 2.2.7 export-device-env (timeout 00:02:35) [common]
11197 19:25:03.607367 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11198 19:25:03.607454 end: 2.2 depthcharge-retry (duration 00:02:25) [common]
11199 19:25:03.607537 end: 2 depthcharge-action (duration 00:02:25) [common]
11200 19:25:03.607624 start: 3 lava-test-retry (timeout 00:05:00) [common]
11201 19:25:03.607707 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11202 19:25:03.607780 Using namespace: common
11204 19:25:03.708154 / # #
11205 19:25:03.708338 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11206 19:25:03.712970 #
11207 19:25:03.713252 Using /lava-13420342
11209 19:25:03.813582 / # export SHELL=/bin/sh
11210 19:25:03.818729 export SHELL=/bin/sh
11212 19:25:03.919277 / # . /lava-13420342/environment
11213 19:25:03.919486 <6>[ 20.877973] IPv6: ADDRCONF(NETDEV_CHANGE): enx0024323078ff: link becomes ready
11214 19:25:03.919559 <6>[ 20.886015] r8152 2-1.3:1.0 enx0024323078ff: carrier on
11215 19:25:03.924657 . /lava-13420342/environment
11217 19:25:04.025239 / # /lava-13420342/bin/lava-test-runner /lava-13420342/0
11218 19:25:04.025418 Test shell timeout: 10s (minimum of the action and connection timeout)
11219 19:25:04.025841 /lava-13420342/bin/lava-test-runner /lava-13420342/0<6>[ 21.031482] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11220 19:25:04.030528
11221 19:25:04.073656 + export TESTRUN_ID=0_cros-ec
11222 19:25:04.073809 +<8>[ 21.069037] <LAVA_SIGNAL_STARTRUN 0_cros-ec 13420342_1.5.2.3.1>
11223 19:25:04.073878 cd /lava-13420342/0/tests/0_cros-ec
11224 19:25:04.073936 + cat uuid
11225 19:25:04.073993 + UUID=13420342_1.5.2.3.1
11226 19:25:04.074049 + set +x
11227 19:25:04.074103 + python3 -m cros.runners.lava_runner -v
11228 19:25:04.074343 Received signal: <STARTRUN> 0_cros-ec 13420342_1.5.2.3.1
11229 19:25:04.074413 Starting test lava.0_cros-ec (13420342_1.5.2.3.1)
11230 19:25:04.074489 Skipping test definition patterns.
11231 19:25:04.510165 test_cros_ec_accel_iio_abi (cros.tests.cros_ec_accel.TestCrosECAccel.test_cros_ec_accel_iio_abi)
11232 19:25:04.517057 Checks the cros-ec accelerometer IIO ABI. ... skipped 'No cros-ec-accel found'
11233 19:25:04.517187
11234 19:25:04.523294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip>
11235 19:25:04.523552 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip
11237 19:25:04.533088 test_cros_ec_accel_iio_data_is_valid (cros.tests.cros_ec_accel.TestCrosECAccel.test_cros_ec_accel_iio_data_is_valid)
11238 19:25:04.542914 Validates accelerometer data by computing the magnitude. If the ... skipped 'No accelerometer found'
11239 19:25:04.543049
11240 19:25:04.550094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=skip>
11241 19:25:04.550358 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=skip
11243 19:25:04.559720 test_cros_ec_gyro_iio_abi (cros.tests.cros_ec_gyro.TestCrosECGyro.test_cros_ec_gyro_iio_abi)
11244 19:25:04.566496 Checks the cros-ec gyroscope IIO ABI. ... skipped 'No cros-ec-gyro found'
11245 19:25:04.566591
11246 19:25:04.573093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip>
11247 19:25:04.573357 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip
11249 19:25:04.579844 test_cros_ec_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_ec_abi)
11250 19:25:04.582560 Checks the standard ABI for the main Embedded Controller. ... ok
11251 19:25:04.586016
11252 19:25:04.589246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_abi RESULT=pass>
11253 19:25:04.589502 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_abi RESULT=pass
11255 19:25:04.596159 test_cros_ec_chardev (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_ec_chardev)
11256 19:25:04.602471 Checks the main Embedded controller character device. ... ok
11257 19:25:04.602561
11258 19:25:04.609041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_chardev RESULT=pass>
11259 19:25:04.609305 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_chardev RESULT=pass
11261 19:25:04.615901 test_cros_ec_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_ec_hello)
11262 19:25:04.622348 Checks basic comunication with the main Embedded controller. ... ok
11263 19:25:04.622443
11264 19:25:04.629078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_hello RESULT=pass>
11265 19:25:04.629339 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_hello RESULT=pass
11267 19:25:04.635493 test_cros_fp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_fp_abi)
11268 19:25:04.642484 Checks the standard ABI for the Fingerprint EC. ... skipped 'MCU cros_fp not supported'
11269 19:25:04.642586
11270 19:25:04.648924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_abi RESULT=skip>
11271 19:25:04.649187 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_abi RESULT=skip
11273 19:25:04.655333 test_cros_fp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_fp_hello)
11274 19:25:04.662292 Checks basic comunication with the fingerprint controller. ... skipped 'MCU cros_fp not found'
11275 19:25:04.662374
11276 19:25:04.668937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_hello RESULT=skip>
11277 19:25:04.669190 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_hello RESULT=skip
11279 19:25:04.675091 test_cros_fp_reboot (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_fp_reboot)
11280 19:25:04.681872 Test reboot command on Fingerprint MCU. ... skipped 'MCU cros_fp not found'
11281 19:25:04.681955
11282 19:25:04.688274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_reboot RESULT=skip>
11283 19:25:04.688530 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_reboot RESULT=skip
11285 19:25:04.695152 test_cros_pd_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_pd_abi)
11286 19:25:04.704736 Checks the standard ABI for the Power Delivery EC. ... skipped 'MCU cros_pd not supported'
11287 19:25:04.704818
11288 19:25:04.707991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_abi RESULT=skip>
11289 19:25:04.708243 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_abi RESULT=skip
11291 19:25:04.714978 test_cros_pd_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_pd_hello)
11292 19:25:04.724689 Checks basic comunication with the power delivery controller. ... skipped 'MCU cros_pd not found'
11293 19:25:04.724777
11294 19:25:04.731560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_hello RESULT=skip>
11295 19:25:04.731814 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_hello RESULT=skip
11297 19:25:04.737777 test_cros_tp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_tp_abi)
11298 19:25:04.744465 Checks the standard ABI for the Touchpad EC. ... skipped 'MCU cros_tp not supported'
11299 19:25:04.744564
11300 19:25:04.751205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_abi RESULT=skip>
11301 19:25:04.751460 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_abi RESULT=skip
11303 19:25:04.757686 test_cros_tp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_tp_hello)
11304 19:25:04.764043 Checks basic comunication with the touchpad controller. ... skipped 'MCU cros_tp not found'
11305 19:25:04.764125
11306 19:25:04.770913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_hello RESULT=skip>
11307 19:25:04.771167 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_hello RESULT=skip
11309 19:25:04.781134 test_cros_ec_pwm_backlight (cros.tests.cros_ec_pwm.TestCrosECPWM.test_cros_ec_pwm_backlight)
11310 19:25:04.787378 Check that the backlight is connected to a pwm of the EC and that ... skipped 'No backlight pwm found'
11311 19:25:04.787462
11312 19:25:04.793685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip>
11313 19:25:04.793941 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip
11315 19:25:04.804187 test_cros_ec_battery_abi (cros.tests.cros_ec_power.TestCrosECPower.test_cros_ec_battery_abi)
11316 19:25:04.806929 Check the cros battery ABI. ... skipped 'No BAT found'
11317 19:25:04.807011
11318 19:25:04.813982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip>
11319 19:25:04.814270 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip
11321 19:25:04.823528 test_cros_ec_usbpd_charger_abi (cros.tests.cros_ec_power.TestCrosECPower.test_cros_ec_usbpd_charger_abi)
11322 19:25:04.830453 Check the cros USBPD charger ABI. ... skipped 'No CROS_USBPD_CHARGER found'
11323 19:25:04.830537
11324 19:25:04.837197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip>
11325 19:25:04.837453 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip
11327 19:25:04.843617 test_cros_ec_rtc_abi (cros.tests.cros_ec_rtc.TestCrosECRTC.test_cros_ec_rtc_abi)
11328 19:25:04.853473 Check the cros RTC ABI. ... skipped 'EC_FEATURE_RTC not supported, skipping'
11329 19:25:04.853564
11330 19:25:04.856984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip>
11331 19:25:04.857239 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip
11333 19:25:04.867047 test_cros_ec_extcon_usbc_abi (cros.tests.cros_ec_extcon.TestCrosECextcon.test_cros_ec_extcon_usbc_abi)
11334 19:25:04.873755 Checks the cros-ec extcon ABI. ... skipped 'No extcon device found'
11335 19:25:04.873837
11336 19:25:04.880295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip>
11337 19:25:04.880376
11338 19:25:04.880611 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip
11340 19:25:04.886843 ----------<8>[ 21.898711] <LAVA_SIGNAL_ENDRUN 0_cros-ec 13420342_1.5.2.3.1>
11341 19:25:04.887093 Received signal: <ENDRUN> 0_cros-ec 13420342_1.5.2.3.1
11342 19:25:04.887172 Ending use of test pattern.
11343 19:25:04.887234 Ending test lava.0_cros-ec (13420342_1.5.2.3.1), duration 0.81
11345 19:25:04.893083 ------------------------------------------------------------
11346 19:25:04.896935 Ran 18 tests in 0.338s
11347 19:25:04.897014
11348 19:25:04.897076 OK (skipped=15)
11349 19:25:04.897136 + set +x
11350 19:25:04.899936 <LAVA_TEST_RUNNER EXIT>
11351 19:25:04.900185 ok: lava_test_shell seems to have completed
11352 19:25:04.900356 test_cros_ec_abi: pass
test_cros_ec_accel_iio_abi: skip
test_cros_ec_accel_iio_data_is_valid: skip
test_cros_ec_battery_abi: skip
test_cros_ec_chardev: pass
test_cros_ec_extcon_usbc_abi: skip
test_cros_ec_gyro_iio_abi: skip
test_cros_ec_hello: pass
test_cros_ec_pwm_backlight: skip
test_cros_ec_rtc_abi: skip
test_cros_ec_usbpd_charger_abi: skip
test_cros_fp_abi: skip
test_cros_fp_hello: skip
test_cros_fp_reboot: skip
test_cros_pd_abi: skip
test_cros_pd_hello: skip
test_cros_tp_abi: skip
test_cros_tp_hello: skip
11353 19:25:04.900453 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11354 19:25:04.900537 end: 3 lava-test-retry (duration 00:00:01) [common]
11355 19:25:04.900628 start: 4 finalize (timeout 00:07:09) [common]
11356 19:25:04.900754 start: 4.1 power-off (timeout 00:00:30) [common]
11357 19:25:04.900904 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
11358 19:25:04.976933 >> Command sent successfully.
11359 19:25:04.979457 Returned 0 in 0 seconds
11360 19:25:05.079844 end: 4.1 power-off (duration 00:00:00) [common]
11362 19:25:05.080282 start: 4.2 read-feedback (timeout 00:07:09) [common]
11363 19:25:05.080585 Listened to connection for namespace 'common' for up to 1s
11364 19:25:06.081551 Finalising connection for namespace 'common'
11365 19:25:06.081730 Disconnecting from shell: Finalise
11366 19:25:06.081805 / #
11367 19:25:06.182149 end: 4.2 read-feedback (duration 00:00:01) [common]
11368 19:25:06.182331 end: 4 finalize (duration 00:00:01) [common]
11369 19:25:06.182448 Cleaning after the job
11370 19:25:06.182551 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13420342/tftp-deploy-9up0a6oe/ramdisk
11371 19:25:06.188126 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13420342/tftp-deploy-9up0a6oe/kernel
11372 19:25:06.195291 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13420342/tftp-deploy-9up0a6oe/dtb
11373 19:25:06.195510 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13420342/tftp-deploy-9up0a6oe/modules
11374 19:25:06.201092 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/13420342
11375 19:25:06.288401 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/13420342
11376 19:25:06.288583 Job finished correctly