Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 24
- Errors: 0
- Kernel Errors: 35
- Boot result: PASS
1 19:25:19.767271 lava-dispatcher, installed at version: 2024.01
2 19:25:19.767492 start: 0 validate
3 19:25:19.767629 Start time: 2024-04-18 19:25:19.767621+00:00 (UTC)
4 19:25:19.767765 Using caching service: 'http://localhost/cache/?uri=%s'
5 19:25:19.767897 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 19:25:20.036101 Using caching service: 'http://localhost/cache/?uri=%s'
7 19:25:20.036276 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 19:25:20.303008 Using caching service: 'http://localhost/cache/?uri=%s'
9 19:25:20.303175 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 19:25:20.561301 Using caching service: 'http://localhost/cache/?uri=%s'
11 19:25:20.561489 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 19:25:20.830658 validate duration: 1.06
14 19:25:20.831108 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 19:25:20.831323 start: 1.1 download-retry (timeout 00:10:00) [common]
16 19:25:20.831490 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 19:25:20.831704 Not decompressing ramdisk as can be used compressed.
18 19:25:20.831869 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 19:25:20.831992 saving as /var/lib/lava/dispatcher/tmp/13420392/tftp-deploy-6dj1q895/ramdisk/rootfs.cpio.gz
20 19:25:20.832113 total size: 47897469 (45 MB)
21 19:25:20.834564 progress 0 % (0 MB)
22 19:25:20.857637 progress 5 % (2 MB)
23 19:25:20.873208 progress 10 % (4 MB)
24 19:25:20.885807 progress 15 % (6 MB)
25 19:25:20.898453 progress 20 % (9 MB)
26 19:25:20.911291 progress 25 % (11 MB)
27 19:25:20.923903 progress 30 % (13 MB)
28 19:25:20.936588 progress 35 % (16 MB)
29 19:25:20.949286 progress 40 % (18 MB)
30 19:25:20.961958 progress 45 % (20 MB)
31 19:25:20.974571 progress 50 % (22 MB)
32 19:25:20.987115 progress 55 % (25 MB)
33 19:25:21.000023 progress 60 % (27 MB)
34 19:25:21.012544 progress 65 % (29 MB)
35 19:25:21.025029 progress 70 % (32 MB)
36 19:25:21.037437 progress 75 % (34 MB)
37 19:25:21.049688 progress 80 % (36 MB)
38 19:25:21.061908 progress 85 % (38 MB)
39 19:25:21.074117 progress 90 % (41 MB)
40 19:25:21.086196 progress 95 % (43 MB)
41 19:25:21.098193 progress 100 % (45 MB)
42 19:25:21.098413 45 MB downloaded in 0.27 s (171.53 MB/s)
43 19:25:21.098577 end: 1.1.1 http-download (duration 00:00:00) [common]
45 19:25:21.098822 end: 1.1 download-retry (duration 00:00:00) [common]
46 19:25:21.098911 start: 1.2 download-retry (timeout 00:10:00) [common]
47 19:25:21.098997 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 19:25:21.099134 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 19:25:21.099205 saving as /var/lib/lava/dispatcher/tmp/13420392/tftp-deploy-6dj1q895/kernel/Image
50 19:25:21.099270 total size: 54286848 (51 MB)
51 19:25:21.099333 No compression specified
52 19:25:21.100550 progress 0 % (0 MB)
53 19:25:21.114851 progress 5 % (2 MB)
54 19:25:21.128919 progress 10 % (5 MB)
55 19:25:21.143023 progress 15 % (7 MB)
56 19:25:21.157064 progress 20 % (10 MB)
57 19:25:21.171095 progress 25 % (12 MB)
58 19:25:21.185090 progress 30 % (15 MB)
59 19:25:21.199171 progress 35 % (18 MB)
60 19:25:21.215600 progress 40 % (20 MB)
61 19:25:21.232214 progress 45 % (23 MB)
62 19:25:21.248332 progress 50 % (25 MB)
63 19:25:21.264359 progress 55 % (28 MB)
64 19:25:21.279521 progress 60 % (31 MB)
65 19:25:21.294572 progress 65 % (33 MB)
66 19:25:21.309788 progress 70 % (36 MB)
67 19:25:21.324706 progress 75 % (38 MB)
68 19:25:21.339475 progress 80 % (41 MB)
69 19:25:21.354648 progress 85 % (44 MB)
70 19:25:21.369592 progress 90 % (46 MB)
71 19:25:21.383774 progress 95 % (49 MB)
72 19:25:21.397573 progress 100 % (51 MB)
73 19:25:21.397817 51 MB downloaded in 0.30 s (173.42 MB/s)
74 19:25:21.397978 end: 1.2.1 http-download (duration 00:00:00) [common]
76 19:25:21.398233 end: 1.2 download-retry (duration 00:00:00) [common]
77 19:25:21.398328 start: 1.3 download-retry (timeout 00:09:59) [common]
78 19:25:21.398429 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 19:25:21.398571 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 19:25:21.398649 saving as /var/lib/lava/dispatcher/tmp/13420392/tftp-deploy-6dj1q895/dtb/mt8192-asurada-spherion-r0.dtb
81 19:25:21.398719 total size: 47230 (0 MB)
82 19:25:21.398782 No compression specified
83 19:25:21.400079 progress 69 % (0 MB)
84 19:25:21.400389 progress 100 % (0 MB)
85 19:25:21.400580 0 MB downloaded in 0.00 s (24.24 MB/s)
86 19:25:21.400758 end: 1.3.1 http-download (duration 00:00:00) [common]
88 19:25:21.401131 end: 1.3 download-retry (duration 00:00:00) [common]
89 19:25:21.401257 start: 1.4 download-retry (timeout 00:09:59) [common]
90 19:25:21.401427 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 19:25:21.401544 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 19:25:21.401613 saving as /var/lib/lava/dispatcher/tmp/13420392/tftp-deploy-6dj1q895/modules/modules.tar
93 19:25:21.401693 total size: 8631416 (8 MB)
94 19:25:21.401759 Using unxz to decompress xz
95 19:25:21.406215 progress 0 % (0 MB)
96 19:25:21.425162 progress 5 % (0 MB)
97 19:25:21.449973 progress 10 % (0 MB)
98 19:25:21.474902 progress 15 % (1 MB)
99 19:25:21.499155 progress 20 % (1 MB)
100 19:25:21.523384 progress 25 % (2 MB)
101 19:25:21.549264 progress 30 % (2 MB)
102 19:25:21.574839 progress 35 % (2 MB)
103 19:25:21.602318 progress 40 % (3 MB)
104 19:25:21.628298 progress 45 % (3 MB)
105 19:25:21.655587 progress 50 % (4 MB)
106 19:25:21.682142 progress 55 % (4 MB)
107 19:25:21.711723 progress 60 % (4 MB)
108 19:25:21.738948 progress 65 % (5 MB)
109 19:25:21.766553 progress 70 % (5 MB)
110 19:25:21.792469 progress 75 % (6 MB)
111 19:25:21.819466 progress 80 % (6 MB)
112 19:25:21.846808 progress 85 % (7 MB)
113 19:25:21.877366 progress 90 % (7 MB)
114 19:25:21.909446 progress 95 % (7 MB)
115 19:25:21.937901 progress 100 % (8 MB)
116 19:25:21.943895 8 MB downloaded in 0.54 s (15.18 MB/s)
117 19:25:21.944219 end: 1.4.1 http-download (duration 00:00:01) [common]
119 19:25:21.944538 end: 1.4 download-retry (duration 00:00:01) [common]
120 19:25:21.944648 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 19:25:21.944751 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 19:25:21.944836 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 19:25:21.944971 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 19:25:21.945248 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/13420392/lava-overlay-mr_gv1l1
125 19:25:21.945436 makedir: /var/lib/lava/dispatcher/tmp/13420392/lava-overlay-mr_gv1l1/lava-13420392/bin
126 19:25:21.945590 makedir: /var/lib/lava/dispatcher/tmp/13420392/lava-overlay-mr_gv1l1/lava-13420392/tests
127 19:25:21.945700 makedir: /var/lib/lava/dispatcher/tmp/13420392/lava-overlay-mr_gv1l1/lava-13420392/results
128 19:25:21.945823 Creating /var/lib/lava/dispatcher/tmp/13420392/lava-overlay-mr_gv1l1/lava-13420392/bin/lava-add-keys
129 19:25:21.945976 Creating /var/lib/lava/dispatcher/tmp/13420392/lava-overlay-mr_gv1l1/lava-13420392/bin/lava-add-sources
130 19:25:21.946111 Creating /var/lib/lava/dispatcher/tmp/13420392/lava-overlay-mr_gv1l1/lava-13420392/bin/lava-background-process-start
131 19:25:21.946245 Creating /var/lib/lava/dispatcher/tmp/13420392/lava-overlay-mr_gv1l1/lava-13420392/bin/lava-background-process-stop
132 19:25:21.946376 Creating /var/lib/lava/dispatcher/tmp/13420392/lava-overlay-mr_gv1l1/lava-13420392/bin/lava-common-functions
133 19:25:21.946503 Creating /var/lib/lava/dispatcher/tmp/13420392/lava-overlay-mr_gv1l1/lava-13420392/bin/lava-echo-ipv4
134 19:25:21.946636 Creating /var/lib/lava/dispatcher/tmp/13420392/lava-overlay-mr_gv1l1/lava-13420392/bin/lava-install-packages
135 19:25:21.946763 Creating /var/lib/lava/dispatcher/tmp/13420392/lava-overlay-mr_gv1l1/lava-13420392/bin/lava-installed-packages
136 19:25:21.946889 Creating /var/lib/lava/dispatcher/tmp/13420392/lava-overlay-mr_gv1l1/lava-13420392/bin/lava-os-build
137 19:25:21.947016 Creating /var/lib/lava/dispatcher/tmp/13420392/lava-overlay-mr_gv1l1/lava-13420392/bin/lava-probe-channel
138 19:25:21.947145 Creating /var/lib/lava/dispatcher/tmp/13420392/lava-overlay-mr_gv1l1/lava-13420392/bin/lava-probe-ip
139 19:25:21.947272 Creating /var/lib/lava/dispatcher/tmp/13420392/lava-overlay-mr_gv1l1/lava-13420392/bin/lava-target-ip
140 19:25:21.947398 Creating /var/lib/lava/dispatcher/tmp/13420392/lava-overlay-mr_gv1l1/lava-13420392/bin/lava-target-mac
141 19:25:21.947524 Creating /var/lib/lava/dispatcher/tmp/13420392/lava-overlay-mr_gv1l1/lava-13420392/bin/lava-target-storage
142 19:25:21.947655 Creating /var/lib/lava/dispatcher/tmp/13420392/lava-overlay-mr_gv1l1/lava-13420392/bin/lava-test-case
143 19:25:21.947799 Creating /var/lib/lava/dispatcher/tmp/13420392/lava-overlay-mr_gv1l1/lava-13420392/bin/lava-test-event
144 19:25:21.947962 Creating /var/lib/lava/dispatcher/tmp/13420392/lava-overlay-mr_gv1l1/lava-13420392/bin/lava-test-feedback
145 19:25:21.948124 Creating /var/lib/lava/dispatcher/tmp/13420392/lava-overlay-mr_gv1l1/lava-13420392/bin/lava-test-raise
146 19:25:21.948289 Creating /var/lib/lava/dispatcher/tmp/13420392/lava-overlay-mr_gv1l1/lava-13420392/bin/lava-test-reference
147 19:25:21.948449 Creating /var/lib/lava/dispatcher/tmp/13420392/lava-overlay-mr_gv1l1/lava-13420392/bin/lava-test-runner
148 19:25:21.948610 Creating /var/lib/lava/dispatcher/tmp/13420392/lava-overlay-mr_gv1l1/lava-13420392/bin/lava-test-set
149 19:25:21.948778 Creating /var/lib/lava/dispatcher/tmp/13420392/lava-overlay-mr_gv1l1/lava-13420392/bin/lava-test-shell
150 19:25:21.948914 Updating /var/lib/lava/dispatcher/tmp/13420392/lava-overlay-mr_gv1l1/lava-13420392/bin/lava-install-packages (oe)
151 19:25:21.949068 Updating /var/lib/lava/dispatcher/tmp/13420392/lava-overlay-mr_gv1l1/lava-13420392/bin/lava-installed-packages (oe)
152 19:25:21.949251 Creating /var/lib/lava/dispatcher/tmp/13420392/lava-overlay-mr_gv1l1/lava-13420392/environment
153 19:25:21.949392 LAVA metadata
154 19:25:21.949474 - LAVA_JOB_ID=13420392
155 19:25:21.949558 - LAVA_DISPATCHER_IP=192.168.201.1
156 19:25:21.949669 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 19:25:21.949746 skipped lava-vland-overlay
158 19:25:21.949824 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 19:25:21.949909 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 19:25:21.949975 skipped lava-multinode-overlay
161 19:25:21.950053 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 19:25:21.950140 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 19:25:21.950218 Loading test definitions
164 19:25:21.950313 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 19:25:21.950399 Using /lava-13420392 at stage 0
166 19:25:21.950727 uuid=13420392_1.5.2.3.1 testdef=None
167 19:25:21.950820 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 19:25:21.950909 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 19:25:21.951474 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 19:25:21.951709 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 19:25:21.952470 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 19:25:21.952858 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 19:25:21.953799 runner path: /var/lib/lava/dispatcher/tmp/13420392/lava-overlay-mr_gv1l1/lava-13420392/0/tests/0_igt-gpu-panfrost test_uuid 13420392_1.5.2.3.1
176 19:25:21.954005 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 19:25:21.954335 Creating lava-test-runner.conf files
179 19:25:21.954405 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/13420392/lava-overlay-mr_gv1l1/lava-13420392/0 for stage 0
180 19:25:21.954498 - 0_igt-gpu-panfrost
181 19:25:21.954598 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 19:25:21.954686 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 19:25:21.962727 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 19:25:21.962852 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 19:25:21.962945 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 19:25:21.963044 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 19:25:21.963136 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 19:25:23.772736 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
189 19:25:23.773186 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
190 19:25:23.773362 extracting modules file /var/lib/lava/dispatcher/tmp/13420392/tftp-deploy-6dj1q895/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13420392/extract-overlay-ramdisk-c12x1dd_/ramdisk
191 19:25:24.076854 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 19:25:24.077033 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 19:25:24.077140 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13420392/compress-overlay-lsdose9s/overlay-1.5.2.4.tar.gz to ramdisk
194 19:25:24.077212 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13420392/compress-overlay-lsdose9s/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/13420392/extract-overlay-ramdisk-c12x1dd_/ramdisk
195 19:25:24.084557 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 19:25:24.084702 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 19:25:24.084801 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 19:25:24.084902 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 19:25:24.084998 Building ramdisk /var/lib/lava/dispatcher/tmp/13420392/extract-overlay-ramdisk-c12x1dd_/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/13420392/extract-overlay-ramdisk-c12x1dd_/ramdisk
200 19:25:25.407395 >> 466207 blocks
201 19:25:32.022095 rename /var/lib/lava/dispatcher/tmp/13420392/extract-overlay-ramdisk-c12x1dd_/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/13420392/tftp-deploy-6dj1q895/ramdisk/ramdisk.cpio.gz
202 19:25:32.022552 end: 1.5.7 compress-ramdisk (duration 00:00:08) [common]
203 19:25:32.022684 start: 1.5.8 prepare-kernel (timeout 00:09:49) [common]
204 19:25:32.022793 start: 1.5.8.1 prepare-fit (timeout 00:09:49) [common]
205 19:25:32.022906 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/13420392/tftp-deploy-6dj1q895/kernel/Image'
206 19:25:45.694236 Returned 0 in 13 seconds
207 19:25:45.795234 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/13420392/tftp-deploy-6dj1q895/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/13420392/tftp-deploy-6dj1q895/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/13420392/tftp-deploy-6dj1q895/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/13420392/tftp-deploy-6dj1q895/kernel/image.itb
208 19:25:46.649734 output: FIT description: Kernel Image image with one or more FDT blobs
209 19:25:46.650116 output: Created: Thu Apr 18 20:25:46 2024
210 19:25:46.650191 output: Image 0 (kernel-1)
211 19:25:46.650256 output: Description:
212 19:25:46.650319 output: Created: Thu Apr 18 20:25:46 2024
213 19:25:46.650381 output: Type: Kernel Image
214 19:25:46.650441 output: Compression: lzma compressed
215 19:25:46.650499 output: Data Size: 12910355 Bytes = 12607.77 KiB = 12.31 MiB
216 19:25:46.650557 output: Architecture: AArch64
217 19:25:46.650615 output: OS: Linux
218 19:25:46.650682 output: Load Address: 0x00000000
219 19:25:46.650764 output: Entry Point: 0x00000000
220 19:25:46.650829 output: Hash algo: crc32
221 19:25:46.650889 output: Hash value: bbac8b0b
222 19:25:46.650980 output: Image 1 (fdt-1)
223 19:25:46.651041 output: Description: mt8192-asurada-spherion-r0
224 19:25:46.651098 output: Created: Thu Apr 18 20:25:46 2024
225 19:25:46.651153 output: Type: Flat Device Tree
226 19:25:46.651205 output: Compression: uncompressed
227 19:25:46.651258 output: Data Size: 47230 Bytes = 46.12 KiB = 0.05 MiB
228 19:25:46.651311 output: Architecture: AArch64
229 19:25:46.651364 output: Hash algo: crc32
230 19:25:46.651415 output: Hash value: 4bf0d1ac
231 19:25:46.651468 output: Image 2 (ramdisk-1)
232 19:25:46.651520 output: Description: unavailable
233 19:25:46.651582 output: Created: Thu Apr 18 20:25:46 2024
234 19:25:46.651635 output: Type: RAMDisk Image
235 19:25:46.651687 output: Compression: Unknown Compression
236 19:25:46.651747 output: Data Size: 61040325 Bytes = 59609.69 KiB = 58.21 MiB
237 19:25:46.651800 output: Architecture: AArch64
238 19:25:46.651853 output: OS: Linux
239 19:25:46.651913 output: Load Address: unavailable
240 19:25:46.651967 output: Entry Point: unavailable
241 19:25:46.652019 output: Hash algo: crc32
242 19:25:46.652078 output: Hash value: bd616f88
243 19:25:46.652137 output: Default Configuration: 'conf-1'
244 19:25:46.652190 output: Configuration 0 (conf-1)
245 19:25:46.652242 output: Description: mt8192-asurada-spherion-r0
246 19:25:46.652294 output: Kernel: kernel-1
247 19:25:46.652346 output: Init Ramdisk: ramdisk-1
248 19:25:46.652405 output: FDT: fdt-1
249 19:25:46.652458 output: Loadables: kernel-1
250 19:25:46.652509 output:
251 19:25:46.652723 end: 1.5.8.1 prepare-fit (duration 00:00:15) [common]
252 19:25:46.652866 end: 1.5.8 prepare-kernel (duration 00:00:15) [common]
253 19:25:46.652968 end: 1.5 prepare-tftp-overlay (duration 00:00:25) [common]
254 19:25:46.653065 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:34) [common]
255 19:25:46.653149 No LXC device requested
256 19:25:46.653230 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 19:25:46.653318 start: 1.7 deploy-device-env (timeout 00:09:34) [common]
258 19:25:46.653431 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 19:25:46.653520 Checking files for TFTP limit of 4294967296 bytes.
260 19:25:46.654052 end: 1 tftp-deploy (duration 00:00:26) [common]
261 19:25:46.654154 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 19:25:46.654247 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 19:25:46.654373 substitutions:
264 19:25:46.654440 - {DTB}: 13420392/tftp-deploy-6dj1q895/dtb/mt8192-asurada-spherion-r0.dtb
265 19:25:46.654508 - {INITRD}: 13420392/tftp-deploy-6dj1q895/ramdisk/ramdisk.cpio.gz
266 19:25:46.654568 - {KERNEL}: 13420392/tftp-deploy-6dj1q895/kernel/Image
267 19:25:46.654625 - {LAVA_MAC}: None
268 19:25:46.654690 - {PRESEED_CONFIG}: None
269 19:25:46.654747 - {PRESEED_LOCAL}: None
270 19:25:46.654809 - {RAMDISK}: 13420392/tftp-deploy-6dj1q895/ramdisk/ramdisk.cpio.gz
271 19:25:46.654865 - {ROOT_PART}: None
272 19:25:46.654919 - {ROOT}: None
273 19:25:46.654973 - {SERVER_IP}: 192.168.201.1
274 19:25:46.655027 - {TEE}: None
275 19:25:46.655081 Parsed boot commands:
276 19:25:46.655135 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 19:25:46.655318 Parsed boot commands: tftpboot 192.168.201.1 13420392/tftp-deploy-6dj1q895/kernel/image.itb 13420392/tftp-deploy-6dj1q895/kernel/cmdline
278 19:25:46.655407 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 19:25:46.655494 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 19:25:46.655583 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 19:25:46.655669 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 19:25:46.655742 Not connected, no need to disconnect.
283 19:25:46.655816 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 19:25:46.655895 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 19:25:46.655962 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
286 19:25:46.659685 Setting prompt string to ['lava-test: # ']
287 19:25:46.660048 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 19:25:46.660158 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 19:25:46.660259 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 19:25:46.660351 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 19:25:46.660553 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=reboot'
292 19:25:51.810638 >> Command sent successfully.
293 19:25:51.821442 Returned 0 in 5 seconds
294 19:25:51.922369 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 19:25:51.922735 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 19:25:51.922846 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 19:25:51.922952 Setting prompt string to 'Starting depthcharge on Spherion...'
299 19:25:51.923030 Changing prompt to 'Starting depthcharge on Spherion...'
300 19:25:51.923107 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 19:25:51.923407 [Enter `^Ec?' for help]
302 19:25:52.088123
303 19:25:52.088665
304 19:25:52.089084 F0: 102B 0000
305 19:25:52.089612
306 19:25:52.089951 F3: 1001 0000 [0200]
307 19:25:52.090288
308 19:25:52.091789 F3: 1001 0000
309 19:25:52.092347
310 19:25:52.092735 F7: 102D 0000
311 19:25:52.093139
312 19:25:52.093663 F1: 0000 0000
313 19:25:52.093987
314 19:25:52.095521 V0: 0000 0000 [0001]
315 19:25:52.096098
316 19:25:52.096467 00: 0007 8000
317 19:25:52.096877
318 19:25:52.099714 01: 0000 0000
319 19:25:52.100196
320 19:25:52.100544 BP: 0C00 0209 [0000]
321 19:25:52.100924
322 19:25:52.101274 G0: 1182 0000
323 19:25:52.103198
324 19:25:52.103632 EC: 0000 0021 [4000]
325 19:25:52.103981
326 19:25:52.106549 S7: 0000 0000 [0000]
327 19:25:52.107093
328 19:25:52.107482 CC: 0000 0000 [0001]
329 19:25:52.107834
330 19:25:52.110099 T0: 0000 0040 [010F]
331 19:25:52.110544
332 19:25:52.110970 Jump to BL
333 19:25:52.111314
334 19:25:52.134961
335 19:25:52.135412
336 19:25:52.135924
337 19:25:52.142751 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 19:25:52.146518 ARM64: Exception handlers installed.
339 19:25:52.149824 ARM64: Testing exception
340 19:25:52.153781 ARM64: Done test exception
341 19:25:52.159880 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 19:25:52.170513 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 19:25:52.177311 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 19:25:52.187085 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 19:25:52.193765 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 19:25:52.200694 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 19:25:52.211635 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 19:25:52.218339 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 19:25:52.237508 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 19:25:52.241026 WDT: Last reset was cold boot
351 19:25:52.244292 SPI1(PAD0) initialized at 2873684 Hz
352 19:25:52.247703 SPI5(PAD0) initialized at 992727 Hz
353 19:25:52.251243 VBOOT: Loading verstage.
354 19:25:52.257599 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 19:25:52.260928 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 19:25:52.264045 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 19:25:52.267589 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 19:25:52.274924 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 19:25:52.281529 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 19:25:52.293027 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 19:25:52.293707
362 19:25:52.294307
363 19:25:52.302859 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 19:25:52.305992 ARM64: Exception handlers installed.
365 19:25:52.309082 ARM64: Testing exception
366 19:25:52.309557 ARM64: Done test exception
367 19:25:52.315827 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 19:25:52.319681 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 19:25:52.333787 Probing TPM: . done!
370 19:25:52.334218 TPM ready after 0 ms
371 19:25:52.340413 Connected to device vid:did:rid of 1ae0:0028:00
372 19:25:52.347365 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
373 19:25:52.403931 Initialized TPM device CR50 revision 0
374 19:25:52.415747 tlcl_send_startup: Startup return code is 0
375 19:25:52.416237 TPM: setup succeeded
376 19:25:52.426807 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 19:25:52.435857 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 19:25:52.447486 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 19:25:52.457268 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 19:25:52.460961 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 19:25:52.468585 in-header: 03 07 00 00 08 00 00 00
382 19:25:52.471722 in-data: aa e4 47 04 13 02 00 00
383 19:25:52.475920 Chrome EC: UHEPI supported
384 19:25:52.482706 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 19:25:52.486683 in-header: 03 ad 00 00 08 00 00 00
386 19:25:52.490167 in-data: 00 20 20 08 00 00 00 00
387 19:25:52.490607 Phase 1
388 19:25:52.493641 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 19:25:52.501388 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 19:25:52.504573 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 19:25:52.508792 Recovery requested (1009000e)
392 19:25:52.517269 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 19:25:52.522892 tlcl_extend: response is 0
394 19:25:52.533526 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 19:25:52.539120 tlcl_extend: response is 0
396 19:25:52.546223 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 19:25:52.565901 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 19:25:52.572772 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 19:25:52.573217
400 19:25:52.573612
401 19:25:52.583093 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 19:25:52.586918 ARM64: Exception handlers installed.
403 19:25:52.587360 ARM64: Testing exception
404 19:25:52.590569 ARM64: Done test exception
405 19:25:52.611525 pmic_efuse_setting: Set efuses in 11 msecs
406 19:25:52.615262 pmwrap_interface_init: Select PMIF_VLD_RDY
407 19:25:52.621760 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 19:25:52.625003 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 19:25:52.632384 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 19:25:52.635922 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 19:25:52.639572 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 19:25:52.647186 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 19:25:52.650587 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 19:25:52.654306 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 19:25:52.658131 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 19:25:52.665266 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 19:25:52.668823 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 19:25:52.672552 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 19:25:52.676273 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 19:25:52.683739 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 19:25:52.690888 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 19:25:52.694669 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 19:25:52.702190 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 19:25:52.705813 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 19:25:52.713289 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 19:25:52.716476 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 19:25:52.723903 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 19:25:52.727607 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 19:25:52.734931 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 19:25:52.738604 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 19:25:52.745596 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 19:25:52.752937 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 19:25:52.756560 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 19:25:52.760309 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 19:25:52.767572 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 19:25:52.770989 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 19:25:52.774845 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 19:25:52.781893 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 19:25:52.786258 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 19:25:52.789723 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 19:25:52.797065 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 19:25:52.800509 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 19:25:52.807474 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 19:25:52.811118 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 19:25:52.814950 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 19:25:52.818040 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 19:25:52.825614 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 19:25:52.828667 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 19:25:52.832391 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 19:25:52.836435 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 19:25:52.840089 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 19:25:52.846860 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 19:25:52.850528 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 19:25:52.854318 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 19:25:52.857989 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 19:25:52.861487 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 19:25:52.864806 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 19:25:52.876140 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 19:25:52.883688 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 19:25:52.887395 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 19:25:52.894086 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 19:25:52.904963 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 19:25:52.908928 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 19:25:52.912359 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 19:25:52.916058 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 19:25:52.924949 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x12
467 19:25:52.928696 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 19:25:52.936702 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
469 19:25:52.940310 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 19:25:52.948733 [RTC]rtc_get_frequency_meter,154: input=15, output=834
471 19:25:52.958616 [RTC]rtc_get_frequency_meter,154: input=7, output=708
472 19:25:52.967784 [RTC]rtc_get_frequency_meter,154: input=11, output=771
473 19:25:52.977535 [RTC]rtc_get_frequency_meter,154: input=13, output=803
474 19:25:52.987177 [RTC]rtc_get_frequency_meter,154: input=12, output=788
475 19:25:52.996660 [RTC]rtc_get_frequency_meter,154: input=12, output=788
476 19:25:53.005907 [RTC]rtc_get_frequency_meter,154: input=13, output=803
477 19:25:53.009313 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
478 19:25:53.016835 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
479 19:25:53.020388 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 19:25:53.024228 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
481 19:25:53.027275 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 19:25:53.031065 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
483 19:25:53.035161 ADC[4]: Raw value=904509 ID=7
484 19:25:53.038714 ADC[3]: Raw value=214021 ID=1
485 19:25:53.038788 RAM Code: 0x71
486 19:25:53.042202 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 19:25:53.049579 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 19:25:53.057131 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 19:25:53.064727 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 19:25:53.068626 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 19:25:53.071834 in-header: 03 07 00 00 08 00 00 00
492 19:25:53.071940 in-data: aa e4 47 04 13 02 00 00
493 19:25:53.075539 Chrome EC: UHEPI supported
494 19:25:53.083222 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 19:25:53.086709 in-header: 03 ed 00 00 08 00 00 00
496 19:25:53.090365 in-data: 80 20 60 08 00 00 00 00
497 19:25:53.094032 MRC: failed to locate region type 0.
498 19:25:53.097401 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 19:25:53.101594 DRAM-K: Running full calibration
500 19:25:53.108851 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 19:25:53.112321 header.status = 0x0
502 19:25:53.112731 header.version = 0x6 (expected: 0x6)
503 19:25:53.116119 header.size = 0xd00 (expected: 0xd00)
504 19:25:53.120058 header.flags = 0x0
505 19:25:53.127063 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 19:25:53.143537 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
507 19:25:53.150549 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 19:25:53.154416 dram_init: ddr_geometry: 2
509 19:25:53.154949 [EMI] MDL number = 2
510 19:25:53.157390 [EMI] Get MDL freq = 0
511 19:25:53.157859 dram_init: ddr_type: 0
512 19:25:53.160429 is_discrete_lpddr4: 1
513 19:25:53.164174 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 19:25:53.164742
515 19:25:53.165168
516 19:25:53.167982 [Bian_co] ETT version 0.0.0.1
517 19:25:53.171556 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 19:25:53.172133
519 19:25:53.174561 dramc_set_vcore_voltage set vcore to 650000
520 19:25:53.178523 Read voltage for 800, 4
521 19:25:53.178983 Vio18 = 0
522 19:25:53.179326 Vcore = 650000
523 19:25:53.181488 Vdram = 0
524 19:25:53.181946 Vddq = 0
525 19:25:53.182333 Vmddr = 0
526 19:25:53.185254 dram_init: config_dvfs: 1
527 19:25:53.189074 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 19:25:53.196480 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 19:25:53.200129 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
530 19:25:53.203793 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
531 19:25:53.207249 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
532 19:25:53.211177 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
533 19:25:53.214472 MEM_TYPE=3, freq_sel=18
534 19:25:53.214931 sv_algorithm_assistance_LP4_1600
535 19:25:53.222126 ============ PULL DRAM RESETB DOWN ============
536 19:25:53.225073 ========== PULL DRAM RESETB DOWN end =========
537 19:25:53.228769 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 19:25:53.231908 ===================================
539 19:25:53.235052 LPDDR4 DRAM CONFIGURATION
540 19:25:53.238369 ===================================
541 19:25:53.238901 EX_ROW_EN[0] = 0x0
542 19:25:53.241681 EX_ROW_EN[1] = 0x0
543 19:25:53.242292 LP4Y_EN = 0x0
544 19:25:53.245260 WORK_FSP = 0x0
545 19:25:53.248187 WL = 0x2
546 19:25:53.248630 RL = 0x2
547 19:25:53.251637 BL = 0x2
548 19:25:53.252123 RPST = 0x0
549 19:25:53.255031 RD_PRE = 0x0
550 19:25:53.255506 WR_PRE = 0x1
551 19:25:53.258429 WR_PST = 0x0
552 19:25:53.258920 DBI_WR = 0x0
553 19:25:53.261869 DBI_RD = 0x0
554 19:25:53.262350 OTF = 0x1
555 19:25:53.264876 ===================================
556 19:25:53.268605 ===================================
557 19:25:53.271633 ANA top config
558 19:25:53.275422 ===================================
559 19:25:53.275950 DLL_ASYNC_EN = 0
560 19:25:53.278499 ALL_SLAVE_EN = 1
561 19:25:53.281641 NEW_RANK_MODE = 1
562 19:25:53.284855 DLL_IDLE_MODE = 1
563 19:25:53.285314 LP45_APHY_COMB_EN = 1
564 19:25:53.288471 TX_ODT_DIS = 1
565 19:25:53.291849 NEW_8X_MODE = 1
566 19:25:53.295048 ===================================
567 19:25:53.298176 ===================================
568 19:25:53.301971 data_rate = 1600
569 19:25:53.304811 CKR = 1
570 19:25:53.308335 DQ_P2S_RATIO = 8
571 19:25:53.311437 ===================================
572 19:25:53.312063 CA_P2S_RATIO = 8
573 19:25:53.315113 DQ_CA_OPEN = 0
574 19:25:53.318219 DQ_SEMI_OPEN = 0
575 19:25:53.321300 CA_SEMI_OPEN = 0
576 19:25:53.324609 CA_FULL_RATE = 0
577 19:25:53.327925 DQ_CKDIV4_EN = 1
578 19:25:53.328518 CA_CKDIV4_EN = 1
579 19:25:53.331179 CA_PREDIV_EN = 0
580 19:25:53.334702 PH8_DLY = 0
581 19:25:53.337943 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 19:25:53.341598 DQ_AAMCK_DIV = 4
583 19:25:53.344619 CA_AAMCK_DIV = 4
584 19:25:53.345257 CA_ADMCK_DIV = 4
585 19:25:53.347665 DQ_TRACK_CA_EN = 0
586 19:25:53.350846 CA_PICK = 800
587 19:25:53.354345 CA_MCKIO = 800
588 19:25:53.358134 MCKIO_SEMI = 0
589 19:25:53.361485 PLL_FREQ = 3068
590 19:25:53.361987 DQ_UI_PI_RATIO = 32
591 19:25:53.365217 CA_UI_PI_RATIO = 0
592 19:25:53.369000 ===================================
593 19:25:53.372760 ===================================
594 19:25:53.376234 memory_type:LPDDR4
595 19:25:53.376668 GP_NUM : 10
596 19:25:53.379643 SRAM_EN : 1
597 19:25:53.380155 MD32_EN : 0
598 19:25:53.383491 ===================================
599 19:25:53.387274 [ANA_INIT] >>>>>>>>>>>>>>
600 19:25:53.390879 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 19:25:53.394489 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 19:25:53.398109 ===================================
603 19:25:53.398544 data_rate = 1600,PCW = 0X7600
604 19:25:53.401159 ===================================
605 19:25:53.404255 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 19:25:53.410940 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 19:25:53.417873 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 19:25:53.421066 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 19:25:53.424782 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 19:25:53.427771 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 19:25:53.431425 [ANA_INIT] flow start
612 19:25:53.431901 [ANA_INIT] PLL >>>>>>>>
613 19:25:53.434398 [ANA_INIT] PLL <<<<<<<<
614 19:25:53.437888 [ANA_INIT] MIDPI >>>>>>>>
615 19:25:53.441145 [ANA_INIT] MIDPI <<<<<<<<
616 19:25:53.441775 [ANA_INIT] DLL >>>>>>>>
617 19:25:53.444385 [ANA_INIT] flow end
618 19:25:53.447553 ============ LP4 DIFF to SE enter ============
619 19:25:53.451326 ============ LP4 DIFF to SE exit ============
620 19:25:53.454359 [ANA_INIT] <<<<<<<<<<<<<
621 19:25:53.457537 [Flow] Enable top DCM control >>>>>
622 19:25:53.461198 [Flow] Enable top DCM control <<<<<
623 19:25:53.464237 Enable DLL master slave shuffle
624 19:25:53.471216 ==============================================================
625 19:25:53.471705 Gating Mode config
626 19:25:53.477756 ==============================================================
627 19:25:53.478387 Config description:
628 19:25:53.487595 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 19:25:53.494147 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 19:25:53.501003 SELPH_MODE 0: By rank 1: By Phase
631 19:25:53.504385 ==============================================================
632 19:25:53.507481 GAT_TRACK_EN = 1
633 19:25:53.510580 RX_GATING_MODE = 2
634 19:25:53.514176 RX_GATING_TRACK_MODE = 2
635 19:25:53.517221 SELPH_MODE = 1
636 19:25:53.521037 PICG_EARLY_EN = 1
637 19:25:53.524134 VALID_LAT_VALUE = 1
638 19:25:53.527168 ==============================================================
639 19:25:53.530738 Enter into Gating configuration >>>>
640 19:25:53.533665 Exit from Gating configuration <<<<
641 19:25:53.537564 Enter into DVFS_PRE_config >>>>>
642 19:25:53.550344 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 19:25:53.553559 Exit from DVFS_PRE_config <<<<<
644 19:25:53.556920 Enter into PICG configuration >>>>
645 19:25:53.560556 Exit from PICG configuration <<<<
646 19:25:53.561131 [RX_INPUT] configuration >>>>>
647 19:25:53.563621 [RX_INPUT] configuration <<<<<
648 19:25:53.570530 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 19:25:53.573658 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 19:25:53.580745 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 19:25:53.587701 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 19:25:53.594419 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 19:25:53.600750 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 19:25:53.604610 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 19:25:53.607273 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 19:25:53.610745 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 19:25:53.617817 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 19:25:53.620792 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 19:25:53.623907 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 19:25:53.627634 ===================================
661 19:25:53.630677 LPDDR4 DRAM CONFIGURATION
662 19:25:53.633969 ===================================
663 19:25:53.634416 EX_ROW_EN[0] = 0x0
664 19:25:53.637434 EX_ROW_EN[1] = 0x0
665 19:25:53.640312 LP4Y_EN = 0x0
666 19:25:53.640961 WORK_FSP = 0x0
667 19:25:53.643407 WL = 0x2
668 19:25:53.644013 RL = 0x2
669 19:25:53.647201 BL = 0x2
670 19:25:53.647944 RPST = 0x0
671 19:25:53.650370 RD_PRE = 0x0
672 19:25:53.650960 WR_PRE = 0x1
673 19:25:53.653999 WR_PST = 0x0
674 19:25:53.654618 DBI_WR = 0x0
675 19:25:53.656991 DBI_RD = 0x0
676 19:25:53.657629 OTF = 0x1
677 19:25:53.660419 ===================================
678 19:25:53.663875 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 19:25:53.669957 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 19:25:53.673556 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 19:25:53.676669 ===================================
682 19:25:53.680467 LPDDR4 DRAM CONFIGURATION
683 19:25:53.683437 ===================================
684 19:25:53.684130 EX_ROW_EN[0] = 0x10
685 19:25:53.687182 EX_ROW_EN[1] = 0x0
686 19:25:53.690598 LP4Y_EN = 0x0
687 19:25:53.691091 WORK_FSP = 0x0
688 19:25:53.693231 WL = 0x2
689 19:25:53.693755 RL = 0x2
690 19:25:53.696821 BL = 0x2
691 19:25:53.697381 RPST = 0x0
692 19:25:53.699935 RD_PRE = 0x0
693 19:25:53.700535 WR_PRE = 0x1
694 19:25:53.703793 WR_PST = 0x0
695 19:25:53.704344 DBI_WR = 0x0
696 19:25:53.706792 DBI_RD = 0x0
697 19:25:53.707242 OTF = 0x1
698 19:25:53.710238 ===================================
699 19:25:53.716412 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 19:25:53.720999 nWR fixed to 40
701 19:25:53.724534 [ModeRegInit_LP4] CH0 RK0
702 19:25:53.724972 [ModeRegInit_LP4] CH0 RK1
703 19:25:53.727637 [ModeRegInit_LP4] CH1 RK0
704 19:25:53.730776 [ModeRegInit_LP4] CH1 RK1
705 19:25:53.731228 match AC timing 13
706 19:25:53.737414 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 19:25:53.740943 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 19:25:53.744147 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 19:25:53.750960 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 19:25:53.754428 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 19:25:53.757363 [EMI DOE] emi_dcm 0
712 19:25:53.761031 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 19:25:53.761692 ==
714 19:25:53.764158 Dram Type= 6, Freq= 0, CH_0, rank 0
715 19:25:53.767603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 19:25:53.768067 ==
717 19:25:53.774335 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 19:25:53.780835 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 19:25:53.788840 [CA 0] Center 37 (7~68) winsize 62
720 19:25:53.791713 [CA 1] Center 36 (6~67) winsize 62
721 19:25:53.795128 [CA 2] Center 34 (4~65) winsize 62
722 19:25:53.798308 [CA 3] Center 34 (4~65) winsize 62
723 19:25:53.801864 [CA 4] Center 33 (3~64) winsize 62
724 19:25:53.804966 [CA 5] Center 33 (3~64) winsize 62
725 19:25:53.805605
726 19:25:53.808762 [CmdBusTrainingLP45] Vref(ca) range 1: 32
727 19:25:53.809316
728 19:25:53.811879 [CATrainingPosCal] consider 1 rank data
729 19:25:53.814938 u2DelayCellTimex100 = 270/100 ps
730 19:25:53.818702 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
731 19:25:53.821615 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
732 19:25:53.828638 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
733 19:25:53.832150 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
734 19:25:53.834956 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
735 19:25:53.838358 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 19:25:53.838793
737 19:25:53.841831 CA PerBit enable=1, Macro0, CA PI delay=33
738 19:25:53.842270
739 19:25:53.844787 [CBTSetCACLKResult] CA Dly = 33
740 19:25:53.845224 CS Dly: 7 (0~38)
741 19:25:53.848375 ==
742 19:25:53.851427 Dram Type= 6, Freq= 0, CH_0, rank 1
743 19:25:53.854407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 19:25:53.854841 ==
745 19:25:53.861437 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 19:25:53.864433 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 19:25:53.874447 [CA 0] Center 37 (6~68) winsize 63
748 19:25:53.878264 [CA 1] Center 37 (7~68) winsize 62
749 19:25:53.881454 [CA 2] Center 34 (4~65) winsize 62
750 19:25:53.884958 [CA 3] Center 34 (4~65) winsize 62
751 19:25:53.888264 [CA 4] Center 33 (3~64) winsize 62
752 19:25:53.891053 [CA 5] Center 33 (3~64) winsize 62
753 19:25:53.891489
754 19:25:53.894540 [CmdBusTrainingLP45] Vref(ca) range 1: 30
755 19:25:53.895023
756 19:25:53.897999 [CATrainingPosCal] consider 2 rank data
757 19:25:53.901433 u2DelayCellTimex100 = 270/100 ps
758 19:25:53.904680 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
759 19:25:53.911135 CA1 delay=37 (7~67),Diff = 4 PI (28 cell)
760 19:25:53.914937 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
761 19:25:53.918018 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
762 19:25:53.921217 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
763 19:25:53.924298 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 19:25:53.924762
765 19:25:53.928036 CA PerBit enable=1, Macro0, CA PI delay=33
766 19:25:53.928615
767 19:25:53.931160 [CBTSetCACLKResult] CA Dly = 33
768 19:25:53.931593 CS Dly: 7 (0~38)
769 19:25:53.934302
770 19:25:53.938003 ----->DramcWriteLeveling(PI) begin...
771 19:25:53.938457 ==
772 19:25:53.941443 Dram Type= 6, Freq= 0, CH_0, rank 0
773 19:25:53.944811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 19:25:53.945247 ==
775 19:25:53.948419 Write leveling (Byte 0): 30 => 30
776 19:25:53.952157 Write leveling (Byte 1): 30 => 30
777 19:25:53.952686 DramcWriteLeveling(PI) end<-----
778 19:25:53.953072
779 19:25:53.955223 ==
780 19:25:53.958817 Dram Type= 6, Freq= 0, CH_0, rank 0
781 19:25:53.962356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 19:25:53.962798 ==
783 19:25:53.965521 [Gating] SW mode calibration
784 19:25:53.972226 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 19:25:53.975716 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 19:25:53.979344 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 19:25:53.985644 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 19:25:53.989106 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
789 19:25:53.992254 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 19:25:53.999068 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 19:25:54.002171 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 19:25:54.005283 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 19:25:54.012048 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 19:25:54.015317 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 19:25:54.019031 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 19:25:54.025320 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 19:25:54.028454 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 19:25:54.032314 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 19:25:54.038951 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 19:25:54.042109 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 19:25:54.045103 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 19:25:54.052017 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 19:25:54.055119 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
804 19:25:54.058475 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
805 19:25:54.065218 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
806 19:25:54.068467 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 19:25:54.071533 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 19:25:54.078684 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 19:25:54.082010 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 19:25:54.085253 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 19:25:54.092216 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 19:25:54.095100 0 9 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (1 1)
813 19:25:54.098759 0 9 12 | B1->B0 | 2a2a 3434 | 1 1 | (1 1) (1 1)
814 19:25:54.104998 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 19:25:54.108826 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 19:25:54.111498 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 19:25:54.118273 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 19:25:54.121806 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 19:25:54.124770 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
820 19:25:54.131692 0 10 8 | B1->B0 | 3131 2f2f | 0 0 | (1 0) (1 1)
821 19:25:54.134892 0 10 12 | B1->B0 | 2727 2323 | 0 0 | (0 1) (0 0)
822 19:25:54.138591 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 19:25:54.141667 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 19:25:54.147966 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 19:25:54.151693 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 19:25:54.154892 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 19:25:54.161706 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 19:25:54.164687 0 11 8 | B1->B0 | 2424 3939 | 0 0 | (0 0) (0 0)
829 19:25:54.168388 0 11 12 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
830 19:25:54.174843 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 19:25:54.177984 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 19:25:54.181653 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 19:25:54.187983 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 19:25:54.191658 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 19:25:54.194996 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 19:25:54.201155 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
837 19:25:54.204553 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 19:25:54.207904 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 19:25:54.214648 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 19:25:54.218608 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 19:25:54.221460 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 19:25:54.227803 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 19:25:54.231345 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 19:25:54.234155 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 19:25:54.240976 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 19:25:54.244451 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 19:25:54.247680 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 19:25:54.254868 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 19:25:54.257741 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 19:25:54.260982 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 19:25:54.267699 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 19:25:54.270756 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
853 19:25:54.274228 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
854 19:25:54.277715 Total UI for P1: 0, mck2ui 16
855 19:25:54.280665 best dqsien dly found for B0: ( 0, 14, 6)
856 19:25:54.284661 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
857 19:25:54.287513 Total UI for P1: 0, mck2ui 16
858 19:25:54.291008 best dqsien dly found for B1: ( 0, 14, 10)
859 19:25:54.297322 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
860 19:25:54.300264 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
861 19:25:54.300698
862 19:25:54.303733 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
863 19:25:54.307336 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
864 19:25:54.310511 [Gating] SW calibration Done
865 19:25:54.310943 ==
866 19:25:54.313521 Dram Type= 6, Freq= 0, CH_0, rank 0
867 19:25:54.317074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
868 19:25:54.317676 ==
869 19:25:54.320581 RX Vref Scan: 0
870 19:25:54.321058
871 19:25:54.321558 RX Vref 0 -> 0, step: 1
872 19:25:54.321940
873 19:25:54.323622 RX Delay -130 -> 252, step: 16
874 19:25:54.326748 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
875 19:25:54.333251 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
876 19:25:54.337210 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
877 19:25:54.340090 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
878 19:25:54.343588 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
879 19:25:54.346954 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
880 19:25:54.353422 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
881 19:25:54.356575 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
882 19:25:54.359736 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
883 19:25:54.363544 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
884 19:25:54.366602 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
885 19:25:54.373439 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
886 19:25:54.376641 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
887 19:25:54.380189 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
888 19:25:54.383034 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
889 19:25:54.389674 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
890 19:25:54.390402 ==
891 19:25:54.393431 Dram Type= 6, Freq= 0, CH_0, rank 0
892 19:25:54.396591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
893 19:25:54.397233 ==
894 19:25:54.397811 DQS Delay:
895 19:25:54.399618 DQS0 = 0, DQS1 = 0
896 19:25:54.400238 DQM Delay:
897 19:25:54.402742 DQM0 = 85, DQM1 = 71
898 19:25:54.403427 DQ Delay:
899 19:25:54.406339 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
900 19:25:54.409483 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
901 19:25:54.413182 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
902 19:25:54.416148 DQ12 =69, DQ13 =77, DQ14 =85, DQ15 =77
903 19:25:54.416790
904 19:25:54.417377
905 19:25:54.417920 ==
906 19:25:54.419822 Dram Type= 6, Freq= 0, CH_0, rank 0
907 19:25:54.423515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
908 19:25:54.424109 ==
909 19:25:54.424682
910 19:25:54.425216
911 19:25:54.426049 TX Vref Scan disable
912 19:25:54.429438 == TX Byte 0 ==
913 19:25:54.432728 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
914 19:25:54.436368 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
915 19:25:54.439480 == TX Byte 1 ==
916 19:25:54.442706 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
917 19:25:54.445810 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
918 19:25:54.446245 ==
919 19:25:54.449605 Dram Type= 6, Freq= 0, CH_0, rank 0
920 19:25:54.455730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
921 19:25:54.456170 ==
922 19:25:54.467627 TX Vref=22, minBit 5, minWin=26, winSum=440
923 19:25:54.470820 TX Vref=24, minBit 3, minWin=27, winSum=440
924 19:25:54.474028 TX Vref=26, minBit 5, minWin=27, winSum=443
925 19:25:54.477634 TX Vref=28, minBit 8, minWin=27, winSum=445
926 19:25:54.480666 TX Vref=30, minBit 10, minWin=27, winSum=448
927 19:25:54.487301 TX Vref=32, minBit 9, minWin=26, winSum=440
928 19:25:54.490786 [TxChooseVref] Worse bit 10, Min win 27, Win sum 448, Final Vref 30
929 19:25:54.491377
930 19:25:54.494417 Final TX Range 1 Vref 30
931 19:25:54.494996
932 19:25:54.495546 ==
933 19:25:54.497624 Dram Type= 6, Freq= 0, CH_0, rank 0
934 19:25:54.500708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 19:25:54.503839 ==
936 19:25:54.504473
937 19:25:54.504910
938 19:25:54.505453 TX Vref Scan disable
939 19:25:54.507540 == TX Byte 0 ==
940 19:25:54.511302 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
941 19:25:54.517193 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
942 19:25:54.517712 == TX Byte 1 ==
943 19:25:54.521120 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
944 19:25:54.527327 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
945 19:25:54.527773
946 19:25:54.528112 [DATLAT]
947 19:25:54.528430 Freq=800, CH0 RK0
948 19:25:54.528736
949 19:25:54.530938 DATLAT Default: 0xa
950 19:25:54.531366 0, 0xFFFF, sum = 0
951 19:25:54.533996 1, 0xFFFF, sum = 0
952 19:25:54.537794 2, 0xFFFF, sum = 0
953 19:25:54.538234 3, 0xFFFF, sum = 0
954 19:25:54.540692 4, 0xFFFF, sum = 0
955 19:25:54.541207 5, 0xFFFF, sum = 0
956 19:25:54.543978 6, 0xFFFF, sum = 0
957 19:25:54.544414 7, 0xFFFF, sum = 0
958 19:25:54.547699 8, 0xFFFF, sum = 0
959 19:25:54.548136 9, 0x0, sum = 1
960 19:25:54.550889 10, 0x0, sum = 2
961 19:25:54.551345 11, 0x0, sum = 3
962 19:25:54.551699 12, 0x0, sum = 4
963 19:25:54.554215 best_step = 10
964 19:25:54.554665
965 19:25:54.555012 ==
966 19:25:54.557555 Dram Type= 6, Freq= 0, CH_0, rank 0
967 19:25:54.560765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
968 19:25:54.561319 ==
969 19:25:54.564160 RX Vref Scan: 1
970 19:25:54.564591
971 19:25:54.564930 Set Vref Range= 32 -> 127
972 19:25:54.567813
973 19:25:54.568240 RX Vref 32 -> 127, step: 1
974 19:25:54.568583
975 19:25:54.570544 RX Delay -111 -> 252, step: 8
976 19:25:54.570976
977 19:25:54.574087 Set Vref, RX VrefLevel [Byte0]: 32
978 19:25:54.577543 [Byte1]: 32
979 19:25:54.577974
980 19:25:54.581072 Set Vref, RX VrefLevel [Byte0]: 33
981 19:25:54.584847 [Byte1]: 33
982 19:25:54.588079
983 19:25:54.588509 Set Vref, RX VrefLevel [Byte0]: 34
984 19:25:54.591655 [Byte1]: 34
985 19:25:54.595952
986 19:25:54.596471 Set Vref, RX VrefLevel [Byte0]: 35
987 19:25:54.599139 [Byte1]: 35
988 19:25:54.603570
989 19:25:54.603998 Set Vref, RX VrefLevel [Byte0]: 36
990 19:25:54.606791 [Byte1]: 36
991 19:25:54.611224
992 19:25:54.611750 Set Vref, RX VrefLevel [Byte0]: 37
993 19:25:54.614234 [Byte1]: 37
994 19:25:54.619012
995 19:25:54.619463 Set Vref, RX VrefLevel [Byte0]: 38
996 19:25:54.622276 [Byte1]: 38
997 19:25:54.626602
998 19:25:54.627044 Set Vref, RX VrefLevel [Byte0]: 39
999 19:25:54.629786 [Byte1]: 39
1000 19:25:54.633627
1001 19:25:54.637402 Set Vref, RX VrefLevel [Byte0]: 40
1002 19:25:54.638021 [Byte1]: 40
1003 19:25:54.641730
1004 19:25:54.642173 Set Vref, RX VrefLevel [Byte0]: 41
1005 19:25:54.645399 [Byte1]: 41
1006 19:25:54.649031
1007 19:25:54.649511 Set Vref, RX VrefLevel [Byte0]: 42
1008 19:25:54.652576 [Byte1]: 42
1009 19:25:54.657281
1010 19:25:54.657770 Set Vref, RX VrefLevel [Byte0]: 43
1011 19:25:54.660246 [Byte1]: 43
1012 19:25:54.664393
1013 19:25:54.664918 Set Vref, RX VrefLevel [Byte0]: 44
1014 19:25:54.667807 [Byte1]: 44
1015 19:25:54.672220
1016 19:25:54.672833 Set Vref, RX VrefLevel [Byte0]: 45
1017 19:25:54.675646 [Byte1]: 45
1018 19:25:54.679736
1019 19:25:54.680366 Set Vref, RX VrefLevel [Byte0]: 46
1020 19:25:54.682861 [Byte1]: 46
1021 19:25:54.687487
1022 19:25:54.687967 Set Vref, RX VrefLevel [Byte0]: 47
1023 19:25:54.690266 [Byte1]: 47
1024 19:25:54.694510
1025 19:25:54.694626 Set Vref, RX VrefLevel [Byte0]: 48
1026 19:25:54.698110 [Byte1]: 48
1027 19:25:54.702390
1028 19:25:54.702482 Set Vref, RX VrefLevel [Byte0]: 49
1029 19:25:54.705933 [Byte1]: 49
1030 19:25:54.710067
1031 19:25:54.710179 Set Vref, RX VrefLevel [Byte0]: 50
1032 19:25:54.713121 [Byte1]: 50
1033 19:25:54.717560
1034 19:25:54.717667 Set Vref, RX VrefLevel [Byte0]: 51
1035 19:25:54.721015 [Byte1]: 51
1036 19:25:54.725161
1037 19:25:54.725260 Set Vref, RX VrefLevel [Byte0]: 52
1038 19:25:54.728300 [Byte1]: 52
1039 19:25:54.732773
1040 19:25:54.732849 Set Vref, RX VrefLevel [Byte0]: 53
1041 19:25:54.736415 [Byte1]: 53
1042 19:25:54.740878
1043 19:25:54.741024 Set Vref, RX VrefLevel [Byte0]: 54
1044 19:25:54.743896 [Byte1]: 54
1045 19:25:54.748600
1046 19:25:54.749061 Set Vref, RX VrefLevel [Byte0]: 55
1047 19:25:54.751709 [Byte1]: 55
1048 19:25:54.756240
1049 19:25:54.756659 Set Vref, RX VrefLevel [Byte0]: 56
1050 19:25:54.759834 [Byte1]: 56
1051 19:25:54.763827
1052 19:25:54.764390 Set Vref, RX VrefLevel [Byte0]: 57
1053 19:25:54.767358 [Byte1]: 57
1054 19:25:54.771670
1055 19:25:54.772248 Set Vref, RX VrefLevel [Byte0]: 58
1056 19:25:54.775065 [Byte1]: 58
1057 19:25:54.779059
1058 19:25:54.779511 Set Vref, RX VrefLevel [Byte0]: 59
1059 19:25:54.782525 [Byte1]: 59
1060 19:25:54.786608
1061 19:25:54.787061 Set Vref, RX VrefLevel [Byte0]: 60
1062 19:25:54.790317 [Byte1]: 60
1063 19:25:54.794999
1064 19:25:54.795424 Set Vref, RX VrefLevel [Byte0]: 61
1065 19:25:54.797913 [Byte1]: 61
1066 19:25:54.802278
1067 19:25:54.802720 Set Vref, RX VrefLevel [Byte0]: 62
1068 19:25:54.805286 [Byte1]: 62
1069 19:25:54.809911
1070 19:25:54.810375 Set Vref, RX VrefLevel [Byte0]: 63
1071 19:25:54.813408 [Byte1]: 63
1072 19:25:54.817652
1073 19:25:54.818095 Set Vref, RX VrefLevel [Byte0]: 64
1074 19:25:54.820760 [Byte1]: 64
1075 19:25:54.824844
1076 19:25:54.825267 Set Vref, RX VrefLevel [Byte0]: 65
1077 19:25:54.828619 [Byte1]: 65
1078 19:25:54.832889
1079 19:25:54.833315 Set Vref, RX VrefLevel [Byte0]: 66
1080 19:25:54.835946 [Byte1]: 66
1081 19:25:54.840347
1082 19:25:54.840855 Set Vref, RX VrefLevel [Byte0]: 67
1083 19:25:54.843451 [Byte1]: 67
1084 19:25:54.847776
1085 19:25:54.848198 Set Vref, RX VrefLevel [Byte0]: 68
1086 19:25:54.851595 [Byte1]: 68
1087 19:25:54.855925
1088 19:25:54.856425 Set Vref, RX VrefLevel [Byte0]: 69
1089 19:25:54.858895 [Byte1]: 69
1090 19:25:54.863051
1091 19:25:54.863520 Set Vref, RX VrefLevel [Byte0]: 70
1092 19:25:54.866713 [Byte1]: 70
1093 19:25:54.870920
1094 19:25:54.871418 Set Vref, RX VrefLevel [Byte0]: 71
1095 19:25:54.874556 [Byte1]: 71
1096 19:25:54.878916
1097 19:25:54.879340 Set Vref, RX VrefLevel [Byte0]: 72
1098 19:25:54.881653 [Byte1]: 72
1099 19:25:54.886255
1100 19:25:54.886786 Set Vref, RX VrefLevel [Byte0]: 73
1101 19:25:54.893096 [Byte1]: 73
1102 19:25:54.893653
1103 19:25:54.895824 Set Vref, RX VrefLevel [Byte0]: 74
1104 19:25:54.899038 [Byte1]: 74
1105 19:25:54.899470
1106 19:25:54.902703 Set Vref, RX VrefLevel [Byte0]: 75
1107 19:25:54.905575 [Byte1]: 75
1108 19:25:54.909200
1109 19:25:54.909682 Set Vref, RX VrefLevel [Byte0]: 76
1110 19:25:54.912834 [Byte1]: 76
1111 19:25:54.916705
1112 19:25:54.917131 Set Vref, RX VrefLevel [Byte0]: 77
1113 19:25:54.920665 [Byte1]: 77
1114 19:25:54.924946
1115 19:25:54.925511 Set Vref, RX VrefLevel [Byte0]: 78
1116 19:25:54.927730 [Byte1]: 78
1117 19:25:54.932134
1118 19:25:54.932620 Set Vref, RX VrefLevel [Byte0]: 79
1119 19:25:54.935381 [Byte1]: 79
1120 19:25:54.939699
1121 19:25:54.940125 Set Vref, RX VrefLevel [Byte0]: 80
1122 19:25:54.942798 [Byte1]: 80
1123 19:25:54.947877
1124 19:25:54.948329 Final RX Vref Byte 0 = 64 to rank0
1125 19:25:54.950985 Final RX Vref Byte 1 = 59 to rank0
1126 19:25:54.953980 Final RX Vref Byte 0 = 64 to rank1
1127 19:25:54.957131 Final RX Vref Byte 1 = 59 to rank1==
1128 19:25:54.960705 Dram Type= 6, Freq= 0, CH_0, rank 0
1129 19:25:54.967322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1130 19:25:54.967924 ==
1131 19:25:54.968425 DQS Delay:
1132 19:25:54.968811 DQS0 = 0, DQS1 = 0
1133 19:25:54.970532 DQM Delay:
1134 19:25:54.970996 DQM0 = 86, DQM1 = 75
1135 19:25:54.974168 DQ Delay:
1136 19:25:54.977179 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =84
1137 19:25:54.980691 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1138 19:25:54.984308 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1139 19:25:54.986993 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =84
1140 19:25:54.987531
1141 19:25:54.988014
1142 19:25:54.993827 [DQSOSCAuto] RK0, (LSB)MR18= 0x4325, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 393 ps
1143 19:25:54.997526 CH0 RK0: MR19=606, MR18=4325
1144 19:25:55.003364 CH0_RK0: MR19=0x606, MR18=0x4325, DQSOSC=393, MR23=63, INC=95, DEC=63
1145 19:25:55.003797
1146 19:25:55.047789 ----->DramcWriteLeveling(PI) begin...
1147 19:25:55.048477 ==
1148 19:25:55.048844 Dram Type= 6, Freq= 0, CH_0, rank 1
1149 19:25:55.049175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1150 19:25:55.049533 ==
1151 19:25:55.050170 Write leveling (Byte 0): 33 => 33
1152 19:25:55.050513 Write leveling (Byte 1): 33 => 33
1153 19:25:55.050824 DramcWriteLeveling(PI) end<-----
1154 19:25:55.051123
1155 19:25:55.051417 ==
1156 19:25:55.051715 Dram Type= 6, Freq= 0, CH_0, rank 1
1157 19:25:55.052071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1158 19:25:55.052367 ==
1159 19:25:55.052659 [Gating] SW mode calibration
1160 19:25:55.052953 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1161 19:25:55.053246 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1162 19:25:55.077368 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1163 19:25:55.078297 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1164 19:25:55.078679 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1165 19:25:55.079017 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1166 19:25:55.079337 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 19:25:55.079705 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 19:25:55.081685 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 19:25:55.082118 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 19:25:55.084765 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 19:25:55.091257 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 19:25:55.094990 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 19:25:55.097913 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 19:25:55.104649 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 19:25:55.107662 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 19:25:55.111279 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 19:25:55.117408 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 19:25:55.121131 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 19:25:55.123984 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1180 19:25:55.130740 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1181 19:25:55.134304 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 19:25:55.137540 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 19:25:55.144414 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 19:25:55.147044 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 19:25:55.151225 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 19:25:55.157089 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 19:25:55.160872 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 19:25:55.164140 0 9 8 | B1->B0 | 2323 3030 | 0 0 | (1 1) (0 0)
1189 19:25:55.170968 0 9 12 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
1190 19:25:55.173675 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1191 19:25:55.176827 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1192 19:25:55.183569 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1193 19:25:55.187276 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1194 19:25:55.190277 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1195 19:25:55.197978 0 10 4 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
1196 19:25:55.201128 0 10 8 | B1->B0 | 2f2f 2a2a | 1 0 | (1 0) (1 0)
1197 19:25:55.204918 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 19:25:55.208685 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 19:25:55.211627 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 19:25:55.219036 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 19:25:55.222713 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 19:25:55.225750 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 19:25:55.229447 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1204 19:25:55.236493 0 11 8 | B1->B0 | 2929 3e3e | 1 0 | (0 0) (0 0)
1205 19:25:55.239093 0 11 12 | B1->B0 | 3f3f 4646 | 0 0 | (1 1) (0 0)
1206 19:25:55.242567 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1207 19:25:55.249251 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1208 19:25:55.252325 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1209 19:25:55.256235 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1210 19:25:55.262171 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1211 19:25:55.266015 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1212 19:25:55.268984 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1213 19:25:55.275908 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1214 19:25:55.278897 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 19:25:55.282536 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 19:25:55.288743 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 19:25:55.292303 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 19:25:55.295636 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 19:25:55.302194 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 19:25:55.305782 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 19:25:55.308717 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 19:25:55.315557 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 19:25:55.319125 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 19:25:55.322307 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1225 19:25:55.329064 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1226 19:25:55.332074 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1227 19:25:55.335217 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1228 19:25:55.342120 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1229 19:25:55.342549 Total UI for P1: 0, mck2ui 16
1230 19:25:55.348498 best dqsien dly found for B0: ( 0, 14, 6)
1231 19:25:55.352259 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1232 19:25:55.355773 Total UI for P1: 0, mck2ui 16
1233 19:25:55.358907 best dqsien dly found for B1: ( 0, 14, 8)
1234 19:25:55.361813 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1235 19:25:55.365502 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1236 19:25:55.365946
1237 19:25:55.368600 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1238 19:25:55.372381 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1239 19:25:55.375564 [Gating] SW calibration Done
1240 19:25:55.375997 ==
1241 19:25:55.378825 Dram Type= 6, Freq= 0, CH_0, rank 1
1242 19:25:55.382188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1243 19:25:55.382661 ==
1244 19:25:55.385614 RX Vref Scan: 0
1245 19:25:55.386081
1246 19:25:55.388754 RX Vref 0 -> 0, step: 1
1247 19:25:55.389180
1248 19:25:55.389587 RX Delay -130 -> 252, step: 16
1249 19:25:55.395125 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1250 19:25:55.398726 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1251 19:25:55.401746 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1252 19:25:55.405424 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1253 19:25:55.408175 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1254 19:25:55.414750 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1255 19:25:55.418423 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1256 19:25:55.421604 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1257 19:25:55.425155 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1258 19:25:55.428175 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1259 19:25:55.434978 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1260 19:25:55.438065 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1261 19:25:55.441186 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1262 19:25:55.444973 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1263 19:25:55.451614 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1264 19:25:55.454456 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1265 19:25:55.454990 ==
1266 19:25:55.457953 Dram Type= 6, Freq= 0, CH_0, rank 1
1267 19:25:55.460916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1268 19:25:55.461369 ==
1269 19:25:55.464694 DQS Delay:
1270 19:25:55.465122 DQS0 = 0, DQS1 = 0
1271 19:25:55.465519 DQM Delay:
1272 19:25:55.467714 DQM0 = 83, DQM1 = 76
1273 19:25:55.468199 DQ Delay:
1274 19:25:55.471351 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
1275 19:25:55.474470 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1276 19:25:55.477327 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1277 19:25:55.481048 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1278 19:25:55.481510
1279 19:25:55.481854
1280 19:25:55.482175 ==
1281 19:25:55.483896 Dram Type= 6, Freq= 0, CH_0, rank 1
1282 19:25:55.490898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1283 19:25:55.491332 ==
1284 19:25:55.491676
1285 19:25:55.492024
1286 19:25:55.492384 TX Vref Scan disable
1287 19:25:55.494414 == TX Byte 0 ==
1288 19:25:55.497860 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1289 19:25:55.504624 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1290 19:25:55.505057 == TX Byte 1 ==
1291 19:25:55.507745 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1292 19:25:55.514063 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1293 19:25:55.514491 ==
1294 19:25:55.517534 Dram Type= 6, Freq= 0, CH_0, rank 1
1295 19:25:55.520521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1296 19:25:55.520954 ==
1297 19:25:55.533402 TX Vref=22, minBit 3, minWin=27, winSum=445
1298 19:25:55.536422 TX Vref=24, minBit 13, minWin=27, winSum=449
1299 19:25:55.540056 TX Vref=26, minBit 13, minWin=27, winSum=448
1300 19:25:55.543165 TX Vref=28, minBit 13, minWin=27, winSum=452
1301 19:25:55.547014 TX Vref=30, minBit 9, minWin=27, winSum=448
1302 19:25:55.553098 TX Vref=32, minBit 9, minWin=27, winSum=445
1303 19:25:55.556680 [TxChooseVref] Worse bit 13, Min win 27, Win sum 452, Final Vref 28
1304 19:25:55.557072
1305 19:25:55.559928 Final TX Range 1 Vref 28
1306 19:25:55.560288
1307 19:25:55.560539 ==
1308 19:25:55.562773 Dram Type= 6, Freq= 0, CH_0, rank 1
1309 19:25:55.569641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1310 19:25:55.569959 ==
1311 19:25:55.570206
1312 19:25:55.570431
1313 19:25:55.570647 TX Vref Scan disable
1314 19:25:55.573353 == TX Byte 0 ==
1315 19:25:55.576968 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1316 19:25:55.583198 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1317 19:25:55.583526 == TX Byte 1 ==
1318 19:25:55.586871 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1319 19:25:55.593249 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1320 19:25:55.593760
1321 19:25:55.594106 [DATLAT]
1322 19:25:55.594426 Freq=800, CH0 RK1
1323 19:25:55.594736
1324 19:25:55.596439 DATLAT Default: 0xa
1325 19:25:55.596879 0, 0xFFFF, sum = 0
1326 19:25:55.600301 1, 0xFFFF, sum = 0
1327 19:25:55.603454 2, 0xFFFF, sum = 0
1328 19:25:55.603917 3, 0xFFFF, sum = 0
1329 19:25:55.606233 4, 0xFFFF, sum = 0
1330 19:25:55.606670 5, 0xFFFF, sum = 0
1331 19:25:55.609552 6, 0xFFFF, sum = 0
1332 19:25:55.610127 7, 0xFFFF, sum = 0
1333 19:25:55.613014 8, 0xFFFF, sum = 0
1334 19:25:55.613491 9, 0x0, sum = 1
1335 19:25:55.616760 10, 0x0, sum = 2
1336 19:25:55.617194 11, 0x0, sum = 3
1337 19:25:55.619415 12, 0x0, sum = 4
1338 19:25:55.619875 best_step = 10
1339 19:25:55.620216
1340 19:25:55.620583 ==
1341 19:25:55.622930 Dram Type= 6, Freq= 0, CH_0, rank 1
1342 19:25:55.626023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1343 19:25:55.626453 ==
1344 19:25:55.629698 RX Vref Scan: 0
1345 19:25:55.630123
1346 19:25:55.632663 RX Vref 0 -> 0, step: 1
1347 19:25:55.633087
1348 19:25:55.633483 RX Delay -111 -> 252, step: 8
1349 19:25:55.640489 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
1350 19:25:55.643478 iDelay=209, Bit 1, Center 92 (-23 ~ 208) 232
1351 19:25:55.646549 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1352 19:25:55.650550 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1353 19:25:55.656380 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1354 19:25:55.660077 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1355 19:25:55.663239 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1356 19:25:55.666867 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1357 19:25:55.670504 iDelay=209, Bit 8, Center 68 (-47 ~ 184) 232
1358 19:25:55.676836 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1359 19:25:55.679995 iDelay=209, Bit 10, Center 80 (-39 ~ 200) 240
1360 19:25:55.683120 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1361 19:25:55.686624 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
1362 19:25:55.690272 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1363 19:25:55.696448 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
1364 19:25:55.699478 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1365 19:25:55.699990 ==
1366 19:25:55.703176 Dram Type= 6, Freq= 0, CH_0, rank 1
1367 19:25:55.706583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1368 19:25:55.707011 ==
1369 19:25:55.709445 DQS Delay:
1370 19:25:55.710084 DQS0 = 0, DQS1 = 0
1371 19:25:55.710599 DQM Delay:
1372 19:25:55.712718 DQM0 = 85, DQM1 = 76
1373 19:25:55.713317 DQ Delay:
1374 19:25:55.716264 DQ0 =84, DQ1 =92, DQ2 =80, DQ3 =84
1375 19:25:55.719602 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =92
1376 19:25:55.723191 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =68
1377 19:25:55.726082 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
1378 19:25:55.726518
1379 19:25:55.726877
1380 19:25:55.736073 [DQSOSCAuto] RK1, (LSB)MR18= 0x3e05, (MSB)MR19= 0x606, tDQSOscB0 = 408 ps tDQSOscB1 = 394 ps
1381 19:25:55.739523 CH0 RK1: MR19=606, MR18=3E05
1382 19:25:55.743158 CH0_RK1: MR19=0x606, MR18=0x3E05, DQSOSC=394, MR23=63, INC=95, DEC=63
1383 19:25:55.746377 [RxdqsGatingPostProcess] freq 800
1384 19:25:55.753101 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1385 19:25:55.756224 Pre-setting of DQS Precalculation
1386 19:25:55.759395 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1387 19:25:55.759857 ==
1388 19:25:55.762915 Dram Type= 6, Freq= 0, CH_1, rank 0
1389 19:25:55.769085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1390 19:25:55.769733 ==
1391 19:25:55.772783 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1392 19:25:55.779224 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1393 19:25:55.789105 [CA 0] Center 36 (6~67) winsize 62
1394 19:25:55.792100 [CA 1] Center 36 (6~67) winsize 62
1395 19:25:55.795673 [CA 2] Center 34 (4~65) winsize 62
1396 19:25:55.798773 [CA 3] Center 34 (3~65) winsize 63
1397 19:25:55.802037 [CA 4] Center 34 (4~65) winsize 62
1398 19:25:55.805642 [CA 5] Center 34 (4~65) winsize 62
1399 19:25:55.806110
1400 19:25:55.808638 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1401 19:25:55.809072
1402 19:25:55.811733 [CATrainingPosCal] consider 1 rank data
1403 19:25:55.815275 u2DelayCellTimex100 = 270/100 ps
1404 19:25:55.818200 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1405 19:25:55.825424 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1406 19:25:55.828279 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1407 19:25:55.831545 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1408 19:25:55.834856 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1409 19:25:55.838479 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1410 19:25:55.838913
1411 19:25:55.841590 CA PerBit enable=1, Macro0, CA PI delay=34
1412 19:25:55.842024
1413 19:25:55.844884 [CBTSetCACLKResult] CA Dly = 34
1414 19:25:55.845319 CS Dly: 5 (0~36)
1415 19:25:55.848448 ==
1416 19:25:55.851445 Dram Type= 6, Freq= 0, CH_1, rank 1
1417 19:25:55.855206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1418 19:25:55.855664 ==
1419 19:25:55.858253 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1420 19:25:55.865005 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1421 19:25:55.874918 [CA 0] Center 36 (6~67) winsize 62
1422 19:25:55.878747 [CA 1] Center 36 (6~67) winsize 62
1423 19:25:55.882216 [CA 2] Center 34 (4~65) winsize 62
1424 19:25:55.885802 [CA 3] Center 34 (3~65) winsize 63
1425 19:25:55.889702 [CA 4] Center 34 (4~65) winsize 62
1426 19:25:55.893375 [CA 5] Center 34 (3~65) winsize 63
1427 19:25:55.894015
1428 19:25:55.896905 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1429 19:25:55.897364
1430 19:25:55.900025 [CATrainingPosCal] consider 2 rank data
1431 19:25:55.903380 u2DelayCellTimex100 = 270/100 ps
1432 19:25:55.907163 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1433 19:25:55.910047 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1434 19:25:55.913848 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1435 19:25:55.916728 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1436 19:25:55.920182 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1437 19:25:55.923491 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1438 19:25:55.923994
1439 19:25:55.926455 CA PerBit enable=1, Macro0, CA PI delay=34
1440 19:25:55.926888
1441 19:25:55.930216 [CBTSetCACLKResult] CA Dly = 34
1442 19:25:55.933259 CS Dly: 6 (0~38)
1443 19:25:55.933776
1444 19:25:55.936748 ----->DramcWriteLeveling(PI) begin...
1445 19:25:55.937198 ==
1446 19:25:55.940401 Dram Type= 6, Freq= 0, CH_1, rank 0
1447 19:25:55.943390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1448 19:25:55.943841 ==
1449 19:25:55.946416 Write leveling (Byte 0): 25 => 25
1450 19:25:55.949945 Write leveling (Byte 1): 26 => 26
1451 19:25:55.953176 DramcWriteLeveling(PI) end<-----
1452 19:25:55.953601
1453 19:25:55.953931 ==
1454 19:25:55.956395 Dram Type= 6, Freq= 0, CH_1, rank 0
1455 19:25:55.960002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1456 19:25:55.960438 ==
1457 19:25:55.963609 [Gating] SW mode calibration
1458 19:25:55.970427 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1459 19:25:55.976413 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1460 19:25:55.979574 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1461 19:25:55.986512 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1462 19:25:55.989860 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 19:25:55.993252 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 19:25:55.999566 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 19:25:56.003221 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 19:25:56.006322 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 19:25:56.009565 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 19:25:56.016272 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 19:25:56.019941 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 19:25:56.023099 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 19:25:56.029411 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 19:25:56.033186 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 19:25:56.036241 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 19:25:56.042828 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 19:25:56.046119 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 19:25:56.049074 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 19:25:56.055931 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1478 19:25:56.059108 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 19:25:56.062490 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 19:25:56.068852 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 19:25:56.071933 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 19:25:56.075413 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 19:25:56.082560 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 19:25:56.085559 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 19:25:56.088495 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1486 19:25:56.095653 0 9 8 | B1->B0 | 2a2a 2f2f | 0 0 | (0 0) (0 0)
1487 19:25:56.098685 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1488 19:25:56.102354 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1489 19:25:56.108213 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1490 19:25:56.111832 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1491 19:25:56.114912 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1492 19:25:56.121664 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1493 19:25:56.124788 0 10 4 | B1->B0 | 3434 3131 | 0 0 | (0 0) (1 1)
1494 19:25:56.128483 0 10 8 | B1->B0 | 2d2d 2424 | 0 0 | (1 1) (0 0)
1495 19:25:56.135309 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 19:25:56.138077 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 19:25:56.141756 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 19:25:56.148557 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 19:25:56.151346 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 19:25:56.155161 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 19:25:56.161447 0 11 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1502 19:25:56.165123 0 11 8 | B1->B0 | 3a3a 4544 | 0 1 | (0 0) (0 0)
1503 19:25:56.168167 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1504 19:25:56.175254 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1505 19:25:56.178458 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1506 19:25:56.181422 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1507 19:25:56.188382 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1508 19:25:56.191489 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1509 19:25:56.195166 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1510 19:25:56.201770 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1511 19:25:56.204947 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 19:25:56.208005 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 19:25:56.214702 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 19:25:56.217727 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 19:25:56.221143 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 19:25:56.227726 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 19:25:56.230938 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 19:25:56.234734 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 19:25:56.241036 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 19:25:56.244346 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 19:25:56.248134 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1522 19:25:56.254235 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1523 19:25:56.257598 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1524 19:25:56.261193 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1525 19:25:56.267542 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1526 19:25:56.270701 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1527 19:25:56.274371 Total UI for P1: 0, mck2ui 16
1528 19:25:56.277536 best dqsien dly found for B0: ( 0, 14, 6)
1529 19:25:56.281264 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1530 19:25:56.284197 Total UI for P1: 0, mck2ui 16
1531 19:25:56.287374 best dqsien dly found for B1: ( 0, 14, 8)
1532 19:25:56.290945 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1533 19:25:56.293781 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1534 19:25:56.294358
1535 19:25:56.297522 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1536 19:25:56.304189 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1537 19:25:56.304713 [Gating] SW calibration Done
1538 19:25:56.305171 ==
1539 19:25:56.307315 Dram Type= 6, Freq= 0, CH_1, rank 0
1540 19:25:56.313921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1541 19:25:56.314506 ==
1542 19:25:56.315015 RX Vref Scan: 0
1543 19:25:56.315504
1544 19:25:56.317050 RX Vref 0 -> 0, step: 1
1545 19:25:56.317614
1546 19:25:56.320707 RX Delay -130 -> 252, step: 16
1547 19:25:56.323607 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1548 19:25:56.327243 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1549 19:25:56.330348 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1550 19:25:56.337309 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1551 19:25:56.340372 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1552 19:25:56.343590 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1553 19:25:56.347191 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1554 19:25:56.353448 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1555 19:25:56.356647 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1556 19:25:56.360362 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1557 19:25:56.363152 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1558 19:25:56.366654 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1559 19:25:56.373384 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1560 19:25:56.376523 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1561 19:25:56.380418 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1562 19:25:56.383397 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1563 19:25:56.383962 ==
1564 19:25:56.386653 Dram Type= 6, Freq= 0, CH_1, rank 0
1565 19:25:56.393506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1566 19:25:56.393959 ==
1567 19:25:56.394306 DQS Delay:
1568 19:25:56.396283 DQS0 = 0, DQS1 = 0
1569 19:25:56.396817 DQM Delay:
1570 19:25:56.397287 DQM0 = 89, DQM1 = 77
1571 19:25:56.399781 DQ Delay:
1572 19:25:56.403023 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1573 19:25:56.406690 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1574 19:25:56.409674 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1575 19:25:56.413242 DQ12 =85, DQ13 =77, DQ14 =85, DQ15 =85
1576 19:25:56.413752
1577 19:25:56.414101
1578 19:25:56.414445 ==
1579 19:25:56.416563 Dram Type= 6, Freq= 0, CH_1, rank 0
1580 19:25:56.419997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1581 19:25:56.420478 ==
1582 19:25:56.421080
1583 19:25:56.421640
1584 19:25:56.422655 TX Vref Scan disable
1585 19:25:56.426461 == TX Byte 0 ==
1586 19:25:56.429601 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1587 19:25:56.432791 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1588 19:25:56.436041 == TX Byte 1 ==
1589 19:25:56.439819 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1590 19:25:56.443260 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1591 19:25:56.443810 ==
1592 19:25:56.446459 Dram Type= 6, Freq= 0, CH_1, rank 0
1593 19:25:56.449578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1594 19:25:56.450219 ==
1595 19:25:56.463886 TX Vref=22, minBit 0, minWin=27, winSum=442
1596 19:25:56.467528 TX Vref=24, minBit 10, minWin=27, winSum=445
1597 19:25:56.470243 TX Vref=26, minBit 10, minWin=27, winSum=447
1598 19:25:56.473659 TX Vref=28, minBit 8, minWin=27, winSum=447
1599 19:25:56.476845 TX Vref=30, minBit 0, minWin=27, winSum=445
1600 19:25:56.483825 TX Vref=32, minBit 0, minWin=27, winSum=443
1601 19:25:56.486899 [TxChooseVref] Worse bit 10, Min win 27, Win sum 447, Final Vref 26
1602 19:25:56.487429
1603 19:25:56.490734 Final TX Range 1 Vref 26
1604 19:25:56.491166
1605 19:25:56.491501 ==
1606 19:25:56.493679 Dram Type= 6, Freq= 0, CH_1, rank 0
1607 19:25:56.496655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1608 19:25:56.500281 ==
1609 19:25:56.500711
1610 19:25:56.501050
1611 19:25:56.501408 TX Vref Scan disable
1612 19:25:56.504233 == TX Byte 0 ==
1613 19:25:56.507326 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1614 19:25:56.510877 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1615 19:25:56.514169 == TX Byte 1 ==
1616 19:25:56.517303 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1617 19:25:56.523669 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1618 19:25:56.524274
1619 19:25:56.524766 [DATLAT]
1620 19:25:56.525281 Freq=800, CH1 RK0
1621 19:25:56.525665
1622 19:25:56.527174 DATLAT Default: 0xa
1623 19:25:56.527767 0, 0xFFFF, sum = 0
1624 19:25:56.530039 1, 0xFFFF, sum = 0
1625 19:25:56.533379 2, 0xFFFF, sum = 0
1626 19:25:56.533821 3, 0xFFFF, sum = 0
1627 19:25:56.536871 4, 0xFFFF, sum = 0
1628 19:25:56.537306 5, 0xFFFF, sum = 0
1629 19:25:56.540113 6, 0xFFFF, sum = 0
1630 19:25:56.540692 7, 0xFFFF, sum = 0
1631 19:25:56.543234 8, 0xFFFF, sum = 0
1632 19:25:56.543672 9, 0x0, sum = 1
1633 19:25:56.547114 10, 0x0, sum = 2
1634 19:25:56.547550 11, 0x0, sum = 3
1635 19:25:56.549961 12, 0x0, sum = 4
1636 19:25:56.550552 best_step = 10
1637 19:25:56.551075
1638 19:25:56.551557 ==
1639 19:25:56.553775 Dram Type= 6, Freq= 0, CH_1, rank 0
1640 19:25:56.556810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1641 19:25:56.557439 ==
1642 19:25:56.560202 RX Vref Scan: 1
1643 19:25:56.560817
1644 19:25:56.563413 Set Vref Range= 32 -> 127
1645 19:25:56.563976
1646 19:25:56.564488 RX Vref 32 -> 127, step: 1
1647 19:25:56.565011
1648 19:25:56.566785 RX Delay -95 -> 252, step: 8
1649 19:25:56.567214
1650 19:25:56.569900 Set Vref, RX VrefLevel [Byte0]: 32
1651 19:25:56.573123 [Byte1]: 32
1652 19:25:56.576656
1653 19:25:56.577080 Set Vref, RX VrefLevel [Byte0]: 33
1654 19:25:56.579965 [Byte1]: 33
1655 19:25:56.584223
1656 19:25:56.584750 Set Vref, RX VrefLevel [Byte0]: 34
1657 19:25:56.587282 [Byte1]: 34
1658 19:25:56.591689
1659 19:25:56.592211 Set Vref, RX VrefLevel [Byte0]: 35
1660 19:25:56.595194 [Byte1]: 35
1661 19:25:56.599470
1662 19:25:56.599795 Set Vref, RX VrefLevel [Byte0]: 36
1663 19:25:56.602440 [Byte1]: 36
1664 19:25:56.606827
1665 19:25:56.607033 Set Vref, RX VrefLevel [Byte0]: 37
1666 19:25:56.609889 [Byte1]: 37
1667 19:25:56.614121
1668 19:25:56.614255 Set Vref, RX VrefLevel [Byte0]: 38
1669 19:25:56.617965 [Byte1]: 38
1670 19:25:56.622470
1671 19:25:56.622607 Set Vref, RX VrefLevel [Byte0]: 39
1672 19:25:56.625189 [Byte1]: 39
1673 19:25:56.629479
1674 19:25:56.629594 Set Vref, RX VrefLevel [Byte0]: 40
1675 19:25:56.633108 [Byte1]: 40
1676 19:25:56.636983
1677 19:25:56.637079 Set Vref, RX VrefLevel [Byte0]: 41
1678 19:25:56.640299 [Byte1]: 41
1679 19:25:56.644955
1680 19:25:56.645076 Set Vref, RX VrefLevel [Byte0]: 42
1681 19:25:56.647979 [Byte1]: 42
1682 19:25:56.652429
1683 19:25:56.652508 Set Vref, RX VrefLevel [Byte0]: 43
1684 19:25:56.655634 [Byte1]: 43
1685 19:25:56.659865
1686 19:25:56.659974 Set Vref, RX VrefLevel [Byte0]: 44
1687 19:25:56.662857 [Byte1]: 44
1688 19:25:56.667191
1689 19:25:56.667298 Set Vref, RX VrefLevel [Byte0]: 45
1690 19:25:56.670641 [Byte1]: 45
1691 19:25:56.674938
1692 19:25:56.675081 Set Vref, RX VrefLevel [Byte0]: 46
1693 19:25:56.678189 [Byte1]: 46
1694 19:25:56.682349
1695 19:25:56.682462 Set Vref, RX VrefLevel [Byte0]: 47
1696 19:25:56.686090 [Byte1]: 47
1697 19:25:56.690257
1698 19:25:56.690341 Set Vref, RX VrefLevel [Byte0]: 48
1699 19:25:56.693202 [Byte1]: 48
1700 19:25:56.697606
1701 19:25:56.697717 Set Vref, RX VrefLevel [Byte0]: 49
1702 19:25:56.701181 [Byte1]: 49
1703 19:25:56.705728
1704 19:25:56.705815 Set Vref, RX VrefLevel [Byte0]: 50
1705 19:25:56.709018 [Byte1]: 50
1706 19:25:56.713084
1707 19:25:56.713223 Set Vref, RX VrefLevel [Byte0]: 51
1708 19:25:56.716231 [Byte1]: 51
1709 19:25:56.720517
1710 19:25:56.720606 Set Vref, RX VrefLevel [Byte0]: 52
1711 19:25:56.724308 [Byte1]: 52
1712 19:25:56.728504
1713 19:25:56.728618 Set Vref, RX VrefLevel [Byte0]: 53
1714 19:25:56.731493 [Byte1]: 53
1715 19:25:56.735948
1716 19:25:56.736032 Set Vref, RX VrefLevel [Byte0]: 54
1717 19:25:56.738845 [Byte1]: 54
1718 19:25:56.743849
1719 19:25:56.743933 Set Vref, RX VrefLevel [Byte0]: 55
1720 19:25:56.746674 [Byte1]: 55
1721 19:25:56.750787
1722 19:25:56.750871 Set Vref, RX VrefLevel [Byte0]: 56
1723 19:25:56.754005 [Byte1]: 56
1724 19:25:56.758414
1725 19:25:56.758497 Set Vref, RX VrefLevel [Byte0]: 57
1726 19:25:56.762444 [Byte1]: 57
1727 19:25:56.766819
1728 19:25:56.767259 Set Vref, RX VrefLevel [Byte0]: 58
1729 19:25:56.769931 [Byte1]: 58
1730 19:25:56.774249
1731 19:25:56.774678 Set Vref, RX VrefLevel [Byte0]: 59
1732 19:25:56.777355 [Byte1]: 59
1733 19:25:56.781546
1734 19:25:56.782101 Set Vref, RX VrefLevel [Byte0]: 60
1735 19:25:56.785067 [Byte1]: 60
1736 19:25:56.788998
1737 19:25:56.789312 Set Vref, RX VrefLevel [Byte0]: 61
1738 19:25:56.792501 [Byte1]: 61
1739 19:25:56.796477
1740 19:25:56.796707 Set Vref, RX VrefLevel [Byte0]: 62
1741 19:25:56.799707 [Byte1]: 62
1742 19:25:56.804434
1743 19:25:56.804590 Set Vref, RX VrefLevel [Byte0]: 63
1744 19:25:56.807549 [Byte1]: 63
1745 19:25:56.811818
1746 19:25:56.811957 Set Vref, RX VrefLevel [Byte0]: 64
1747 19:25:56.814949 [Byte1]: 64
1748 19:25:56.819222
1749 19:25:56.819332 Set Vref, RX VrefLevel [Byte0]: 65
1750 19:25:56.822957 [Byte1]: 65
1751 19:25:56.827194
1752 19:25:56.827285 Set Vref, RX VrefLevel [Byte0]: 66
1753 19:25:56.830425 [Byte1]: 66
1754 19:25:56.834715
1755 19:25:56.834804 Set Vref, RX VrefLevel [Byte0]: 67
1756 19:25:56.837729 [Byte1]: 67
1757 19:25:56.842150
1758 19:25:56.842236 Set Vref, RX VrefLevel [Byte0]: 68
1759 19:25:56.845227 [Byte1]: 68
1760 19:25:56.849682
1761 19:25:56.849768 Set Vref, RX VrefLevel [Byte0]: 69
1762 19:25:56.853252 [Byte1]: 69
1763 19:25:56.857258
1764 19:25:56.857397 Set Vref, RX VrefLevel [Byte0]: 70
1765 19:25:56.860540 [Byte1]: 70
1766 19:25:56.864704
1767 19:25:56.864789 Set Vref, RX VrefLevel [Byte0]: 71
1768 19:25:56.868563 [Byte1]: 71
1769 19:25:56.872591
1770 19:25:56.872683 Set Vref, RX VrefLevel [Byte0]: 72
1771 19:25:56.875722 [Byte1]: 72
1772 19:25:56.880268
1773 19:25:56.880367 Set Vref, RX VrefLevel [Byte0]: 73
1774 19:25:56.884000 [Byte1]: 73
1775 19:25:56.888185
1776 19:25:56.888319 Set Vref, RX VrefLevel [Byte0]: 74
1777 19:25:56.890973 [Byte1]: 74
1778 19:25:56.895686
1779 19:25:56.895815 Set Vref, RX VrefLevel [Byte0]: 75
1780 19:25:56.898775 [Byte1]: 75
1781 19:25:56.903154
1782 19:25:56.903313 Final RX Vref Byte 0 = 57 to rank0
1783 19:25:56.906163 Final RX Vref Byte 1 = 64 to rank0
1784 19:25:56.909814 Final RX Vref Byte 0 = 57 to rank1
1785 19:25:56.913209 Final RX Vref Byte 1 = 64 to rank1==
1786 19:25:56.916568 Dram Type= 6, Freq= 0, CH_1, rank 0
1787 19:25:56.922890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1788 19:25:56.923080 ==
1789 19:25:56.923268 DQS Delay:
1790 19:25:56.923444 DQS0 = 0, DQS1 = 0
1791 19:25:56.926218 DQM Delay:
1792 19:25:56.926395 DQM0 = 86, DQM1 = 78
1793 19:25:56.929683 DQ Delay:
1794 19:25:56.933193 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1795 19:25:56.936042 DQ4 =80, DQ5 =100, DQ6 =100, DQ7 =80
1796 19:25:56.939661 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1797 19:25:56.942686 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =88
1798 19:25:56.942839
1799 19:25:56.942962
1800 19:25:56.949708 [DQSOSCAuto] RK0, (LSB)MR18= 0x311d, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
1801 19:25:56.952846 CH1 RK0: MR19=606, MR18=311D
1802 19:25:56.958962 CH1_RK0: MR19=0x606, MR18=0x311D, DQSOSC=397, MR23=63, INC=93, DEC=62
1803 19:25:56.959116
1804 19:25:56.962748 ----->DramcWriteLeveling(PI) begin...
1805 19:25:56.962890 ==
1806 19:25:56.965773 Dram Type= 6, Freq= 0, CH_1, rank 1
1807 19:25:56.969280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1808 19:25:56.969443 ==
1809 19:25:56.972258 Write leveling (Byte 0): 27 => 27
1810 19:25:56.975712 Write leveling (Byte 1): 30 => 30
1811 19:25:56.979211 DramcWriteLeveling(PI) end<-----
1812 19:25:56.979369
1813 19:25:56.979517 ==
1814 19:25:56.982208 Dram Type= 6, Freq= 0, CH_1, rank 1
1815 19:25:56.985420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1816 19:25:56.989096 ==
1817 19:25:56.989211 [Gating] SW mode calibration
1818 19:25:56.995252 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1819 19:25:57.002160 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1820 19:25:57.005475 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1821 19:25:57.011938 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1822 19:25:57.015199 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 19:25:57.018722 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 19:25:57.025369 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 19:25:57.028454 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 19:25:57.031901 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 19:25:57.038287 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 19:25:57.042000 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 19:25:57.045248 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 19:25:57.052012 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 19:25:57.055136 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 19:25:57.058171 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 19:25:57.065186 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 19:25:57.068336 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 19:25:57.071247 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 19:25:57.077994 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 19:25:57.081802 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1838 19:25:57.084622 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1839 19:25:57.091451 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 19:25:57.094545 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 19:25:57.097944 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 19:25:57.104742 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 19:25:57.107810 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 19:25:57.111328 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 19:25:57.114816 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 19:25:57.121615 0 9 8 | B1->B0 | 3232 2424 | 1 0 | (1 1) (0 0)
1847 19:25:57.124546 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1848 19:25:57.128399 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1849 19:25:57.134667 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1850 19:25:57.137902 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1851 19:25:57.141494 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1852 19:25:57.147821 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1853 19:25:57.151505 0 10 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1854 19:25:57.154698 0 10 8 | B1->B0 | 2424 2f2f | 0 1 | (1 0) (1 0)
1855 19:25:57.161223 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 19:25:57.164351 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 19:25:57.168150 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 19:25:57.174556 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 19:25:57.177992 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 19:25:57.181055 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 19:25:57.188117 0 11 4 | B1->B0 | 2525 2323 | 1 0 | (0 0) (0 0)
1862 19:25:57.191152 0 11 8 | B1->B0 | 3d3d 3333 | 0 0 | (0 0) (1 1)
1863 19:25:57.194706 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1864 19:25:57.201172 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1865 19:25:57.204588 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1866 19:25:57.207599 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1867 19:25:57.214329 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1868 19:25:57.217511 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1869 19:25:57.220837 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1870 19:25:57.227485 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1871 19:25:57.230889 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 19:25:57.234112 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 19:25:57.241030 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 19:25:57.244344 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 19:25:57.247408 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 19:25:57.254054 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 19:25:57.256957 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 19:25:57.260525 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 19:25:57.267045 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 19:25:57.270258 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 19:25:57.273452 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 19:25:57.280234 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 19:25:57.283288 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 19:25:57.287024 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 19:25:57.293278 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1886 19:25:57.297022 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1887 19:25:57.299910 Total UI for P1: 0, mck2ui 16
1888 19:25:57.303223 best dqsien dly found for B0: ( 0, 14, 4)
1889 19:25:57.306352 Total UI for P1: 0, mck2ui 16
1890 19:25:57.310025 best dqsien dly found for B1: ( 0, 14, 6)
1891 19:25:57.312996 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1892 19:25:57.316519 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1893 19:25:57.316948
1894 19:25:57.319872 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1895 19:25:57.322830 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1896 19:25:57.326650 [Gating] SW calibration Done
1897 19:25:57.327080 ==
1898 19:25:57.329671 Dram Type= 6, Freq= 0, CH_1, rank 1
1899 19:25:57.333270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1900 19:25:57.336757 ==
1901 19:25:57.337327 RX Vref Scan: 0
1902 19:25:57.337724
1903 19:25:57.339728 RX Vref 0 -> 0, step: 1
1904 19:25:57.340303
1905 19:25:57.342743 RX Delay -130 -> 252, step: 16
1906 19:25:57.346521 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1907 19:25:57.349704 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1908 19:25:57.353368 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1909 19:25:57.356572 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1910 19:25:57.363180 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1911 19:25:57.366593 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1912 19:25:57.369655 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1913 19:25:57.372773 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1914 19:25:57.375973 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1915 19:25:57.382673 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1916 19:25:57.385892 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1917 19:25:57.389114 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1918 19:25:57.392546 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1919 19:25:57.399434 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1920 19:25:57.402468 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1921 19:25:57.405645 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1922 19:25:57.406115 ==
1923 19:25:57.409313 Dram Type= 6, Freq= 0, CH_1, rank 1
1924 19:25:57.412396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1925 19:25:57.412825 ==
1926 19:25:57.415638 DQS Delay:
1927 19:25:57.416075 DQS0 = 0, DQS1 = 0
1928 19:25:57.419313 DQM Delay:
1929 19:25:57.419770 DQM0 = 87, DQM1 = 80
1930 19:25:57.420121 DQ Delay:
1931 19:25:57.422441 DQ0 =93, DQ1 =77, DQ2 =69, DQ3 =85
1932 19:25:57.425304 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1933 19:25:57.429148 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1934 19:25:57.432305 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =85
1935 19:25:57.432733
1936 19:25:57.435765
1937 19:25:57.436188 ==
1938 19:25:57.438663 Dram Type= 6, Freq= 0, CH_1, rank 1
1939 19:25:57.442056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1940 19:25:57.442487 ==
1941 19:25:57.442829
1942 19:25:57.443143
1943 19:25:57.445362 TX Vref Scan disable
1944 19:25:57.445798 == TX Byte 0 ==
1945 19:25:57.451974 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1946 19:25:57.455393 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1947 19:25:57.455823 == TX Byte 1 ==
1948 19:25:57.462405 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1949 19:25:57.465226 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1950 19:25:57.465714 ==
1951 19:25:57.468823 Dram Type= 6, Freq= 0, CH_1, rank 1
1952 19:25:57.471718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1953 19:25:57.472150 ==
1954 19:25:57.485780 TX Vref=22, minBit 1, minWin=27, winSum=445
1955 19:25:57.488888 TX Vref=24, minBit 8, minWin=27, winSum=446
1956 19:25:57.492318 TX Vref=26, minBit 8, minWin=27, winSum=450
1957 19:25:57.495929 TX Vref=28, minBit 8, minWin=27, winSum=453
1958 19:25:57.499314 TX Vref=30, minBit 8, minWin=27, winSum=453
1959 19:25:57.502558 TX Vref=32, minBit 0, minWin=28, winSum=451
1960 19:25:57.509131 [TxChooseVref] Worse bit 0, Min win 28, Win sum 451, Final Vref 32
1961 19:25:57.509672
1962 19:25:57.512156 Final TX Range 1 Vref 32
1963 19:25:57.512585
1964 19:25:57.512926 ==
1965 19:25:57.515395 Dram Type= 6, Freq= 0, CH_1, rank 1
1966 19:25:57.519132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1967 19:25:57.519606 ==
1968 19:25:57.522181
1969 19:25:57.522641
1970 19:25:57.522977 TX Vref Scan disable
1971 19:25:57.525773 == TX Byte 0 ==
1972 19:25:57.528742 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1973 19:25:57.535494 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1974 19:25:57.535957 == TX Byte 1 ==
1975 19:25:57.538720 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1976 19:25:57.545170 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1977 19:25:57.545665
1978 19:25:57.546012 [DATLAT]
1979 19:25:57.546335 Freq=800, CH1 RK1
1980 19:25:57.546643
1981 19:25:57.548818 DATLAT Default: 0xa
1982 19:25:57.549241 0, 0xFFFF, sum = 0
1983 19:25:57.551913 1, 0xFFFF, sum = 0
1984 19:25:57.555536 2, 0xFFFF, sum = 0
1985 19:25:57.555987 3, 0xFFFF, sum = 0
1986 19:25:57.558346 4, 0xFFFF, sum = 0
1987 19:25:57.558780 5, 0xFFFF, sum = 0
1988 19:25:57.561542 6, 0xFFFF, sum = 0
1989 19:25:57.561982 7, 0xFFFF, sum = 0
1990 19:25:57.565099 8, 0xFFFF, sum = 0
1991 19:25:57.565600 9, 0x0, sum = 1
1992 19:25:57.568180 10, 0x0, sum = 2
1993 19:25:57.568618 11, 0x0, sum = 3
1994 19:25:57.571605 12, 0x0, sum = 4
1995 19:25:57.572038 best_step = 10
1996 19:25:57.572379
1997 19:25:57.572697 ==
1998 19:25:57.575079 Dram Type= 6, Freq= 0, CH_1, rank 1
1999 19:25:57.578534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2000 19:25:57.578966 ==
2001 19:25:57.582008 RX Vref Scan: 0
2002 19:25:57.582542
2003 19:25:57.584947 RX Vref 0 -> 0, step: 1
2004 19:25:57.585562
2005 19:25:57.585911 RX Delay -95 -> 252, step: 8
2006 19:25:57.592324 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2007 19:25:57.595440 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2008 19:25:57.598876 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
2009 19:25:57.602084 iDelay=217, Bit 3, Center 88 (-23 ~ 200) 224
2010 19:25:57.608833 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2011 19:25:57.612054 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2012 19:25:57.615333 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2013 19:25:57.618865 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2014 19:25:57.621981 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2015 19:25:57.628677 iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232
2016 19:25:57.631833 iDelay=217, Bit 10, Center 80 (-39 ~ 200) 240
2017 19:25:57.635333 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
2018 19:25:57.638547 iDelay=217, Bit 12, Center 88 (-23 ~ 200) 224
2019 19:25:57.642107 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2020 19:25:57.648407 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2021 19:25:57.652056 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2022 19:25:57.652486 ==
2023 19:25:57.655204 Dram Type= 6, Freq= 0, CH_1, rank 1
2024 19:25:57.658186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2025 19:25:57.658618 ==
2026 19:25:57.662068 DQS Delay:
2027 19:25:57.662495 DQS0 = 0, DQS1 = 0
2028 19:25:57.662833 DQM Delay:
2029 19:25:57.665044 DQM0 = 87, DQM1 = 78
2030 19:25:57.665513 DQ Delay:
2031 19:25:57.668185 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =88
2032 19:25:57.671640 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2033 19:25:57.674732 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
2034 19:25:57.677962 DQ12 =88, DQ13 =84, DQ14 =84, DQ15 =88
2035 19:25:57.678564
2036 19:25:57.678929
2037 19:25:57.688043 [DQSOSCAuto] RK1, (LSB)MR18= 0x1911, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
2038 19:25:57.691051 CH1 RK1: MR19=606, MR18=1911
2039 19:25:57.694499 CH1_RK1: MR19=0x606, MR18=0x1911, DQSOSC=403, MR23=63, INC=90, DEC=60
2040 19:25:57.697742 [RxdqsGatingPostProcess] freq 800
2041 19:25:57.704893 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2042 19:25:57.708015 Pre-setting of DQS Precalculation
2043 19:25:57.711042 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2044 19:25:57.721222 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2045 19:25:57.727765 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2046 19:25:57.728195
2047 19:25:57.728531
2048 19:25:57.731569 [Calibration Summary] 1600 Mbps
2049 19:25:57.732087 CH 0, Rank 0
2050 19:25:57.734556 SW Impedance : PASS
2051 19:25:57.734987 DUTY Scan : NO K
2052 19:25:57.738071 ZQ Calibration : PASS
2053 19:25:57.740977 Jitter Meter : NO K
2054 19:25:57.741444 CBT Training : PASS
2055 19:25:57.744567 Write leveling : PASS
2056 19:25:57.747553 RX DQS gating : PASS
2057 19:25:57.747983 RX DQ/DQS(RDDQC) : PASS
2058 19:25:57.751362 TX DQ/DQS : PASS
2059 19:25:57.754368 RX DATLAT : PASS
2060 19:25:57.754796 RX DQ/DQS(Engine): PASS
2061 19:25:57.757527 TX OE : NO K
2062 19:25:57.757957 All Pass.
2063 19:25:57.758296
2064 19:25:57.761438 CH 0, Rank 1
2065 19:25:57.761868 SW Impedance : PASS
2066 19:25:57.764113 DUTY Scan : NO K
2067 19:25:57.767450 ZQ Calibration : PASS
2068 19:25:57.767879 Jitter Meter : NO K
2069 19:25:57.771128 CBT Training : PASS
2070 19:25:57.774575 Write leveling : PASS
2071 19:25:57.775117 RX DQS gating : PASS
2072 19:25:57.777247 RX DQ/DQS(RDDQC) : PASS
2073 19:25:57.777735 TX DQ/DQS : PASS
2074 19:25:57.780673 RX DATLAT : PASS
2075 19:25:57.784433 RX DQ/DQS(Engine): PASS
2076 19:25:57.784920 TX OE : NO K
2077 19:25:57.787303 All Pass.
2078 19:25:57.787728
2079 19:25:57.788064 CH 1, Rank 0
2080 19:25:57.790530 SW Impedance : PASS
2081 19:25:57.791045 DUTY Scan : NO K
2082 19:25:57.794320 ZQ Calibration : PASS
2083 19:25:57.797200 Jitter Meter : NO K
2084 19:25:57.797662 CBT Training : PASS
2085 19:25:57.800360 Write leveling : PASS
2086 19:25:57.804134 RX DQS gating : PASS
2087 19:25:57.804582 RX DQ/DQS(RDDQC) : PASS
2088 19:25:57.807269 TX DQ/DQS : PASS
2089 19:25:57.810615 RX DATLAT : PASS
2090 19:25:57.811045 RX DQ/DQS(Engine): PASS
2091 19:25:57.814196 TX OE : NO K
2092 19:25:57.814627 All Pass.
2093 19:25:57.814967
2094 19:25:57.817059 CH 1, Rank 1
2095 19:25:57.817520 SW Impedance : PASS
2096 19:25:57.820901 DUTY Scan : NO K
2097 19:25:57.823723 ZQ Calibration : PASS
2098 19:25:57.824154 Jitter Meter : NO K
2099 19:25:57.827266 CBT Training : PASS
2100 19:25:57.830288 Write leveling : PASS
2101 19:25:57.830768 RX DQS gating : PASS
2102 19:25:57.833759 RX DQ/DQS(RDDQC) : PASS
2103 19:25:57.837233 TX DQ/DQS : PASS
2104 19:25:57.837708 RX DATLAT : PASS
2105 19:25:57.840377 RX DQ/DQS(Engine): PASS
2106 19:25:57.840802 TX OE : NO K
2107 19:25:57.844041 All Pass.
2108 19:25:57.844469
2109 19:25:57.844807 DramC Write-DBI off
2110 19:25:57.847001 PER_BANK_REFRESH: Hybrid Mode
2111 19:25:57.850481 TX_TRACKING: ON
2112 19:25:57.853721 [GetDramInforAfterCalByMRR] Vendor 6.
2113 19:25:57.857315 [GetDramInforAfterCalByMRR] Revision 606.
2114 19:25:57.860579 [GetDramInforAfterCalByMRR] Revision 2 0.
2115 19:25:57.861005 MR0 0x3b3b
2116 19:25:57.861369 MR8 0x5151
2117 19:25:57.867260 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2118 19:25:57.867689
2119 19:25:57.868029 MR0 0x3b3b
2120 19:25:57.868346 MR8 0x5151
2121 19:25:57.870155 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2122 19:25:57.870590
2123 19:25:57.880101 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2124 19:25:57.883838 [FAST_K] Save calibration result to emmc
2125 19:25:57.886824 [FAST_K] Save calibration result to emmc
2126 19:25:57.890541 dram_init: config_dvfs: 1
2127 19:25:57.893426 dramc_set_vcore_voltage set vcore to 662500
2128 19:25:57.897135 Read voltage for 1200, 2
2129 19:25:57.897617 Vio18 = 0
2130 19:25:57.897962 Vcore = 662500
2131 19:25:57.900151 Vdram = 0
2132 19:25:57.900583 Vddq = 0
2133 19:25:57.900924 Vmddr = 0
2134 19:25:57.906589 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2135 19:25:57.910259 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2136 19:25:57.913295 MEM_TYPE=3, freq_sel=15
2137 19:25:57.916236 sv_algorithm_assistance_LP4_1600
2138 19:25:57.919649 ============ PULL DRAM RESETB DOWN ============
2139 19:25:57.926625 ========== PULL DRAM RESETB DOWN end =========
2140 19:25:57.929750 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2141 19:25:57.932956 ===================================
2142 19:25:57.936260 LPDDR4 DRAM CONFIGURATION
2143 19:25:57.939683 ===================================
2144 19:25:57.939807 EX_ROW_EN[0] = 0x0
2145 19:25:57.943077 EX_ROW_EN[1] = 0x0
2146 19:25:57.943214 LP4Y_EN = 0x0
2147 19:25:57.946161 WORK_FSP = 0x0
2148 19:25:57.946298 WL = 0x4
2149 19:25:57.949659 RL = 0x4
2150 19:25:57.949812 BL = 0x2
2151 19:25:57.952839 RPST = 0x0
2152 19:25:57.953015 RD_PRE = 0x0
2153 19:25:57.956426 WR_PRE = 0x1
2154 19:25:57.959449 WR_PST = 0x0
2155 19:25:57.959654 DBI_WR = 0x0
2156 19:25:57.963206 DBI_RD = 0x0
2157 19:25:57.963451 OTF = 0x1
2158 19:25:57.966262 ===================================
2159 19:25:57.969420 ===================================
2160 19:25:57.969793 ANA top config
2161 19:25:57.973257 ===================================
2162 19:25:57.976219 DLL_ASYNC_EN = 0
2163 19:25:57.979451 ALL_SLAVE_EN = 0
2164 19:25:57.983076 NEW_RANK_MODE = 1
2165 19:25:57.986331 DLL_IDLE_MODE = 1
2166 19:25:57.986759 LP45_APHY_COMB_EN = 1
2167 19:25:57.989280 TX_ODT_DIS = 1
2168 19:25:57.992436 NEW_8X_MODE = 1
2169 19:25:57.996014 ===================================
2170 19:25:57.999578 ===================================
2171 19:25:58.002702 data_rate = 2400
2172 19:25:58.005949 CKR = 1
2173 19:25:58.009420 DQ_P2S_RATIO = 8
2174 19:25:58.009856 ===================================
2175 19:25:58.012530 CA_P2S_RATIO = 8
2176 19:25:58.016067 DQ_CA_OPEN = 0
2177 19:25:58.019144 DQ_SEMI_OPEN = 0
2178 19:25:58.022828 CA_SEMI_OPEN = 0
2179 19:25:58.025726 CA_FULL_RATE = 0
2180 19:25:58.026198 DQ_CKDIV4_EN = 0
2181 19:25:58.029585 CA_CKDIV4_EN = 0
2182 19:25:58.032538 CA_PREDIV_EN = 0
2183 19:25:58.036086 PH8_DLY = 17
2184 19:25:58.039058 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2185 19:25:58.042376 DQ_AAMCK_DIV = 4
2186 19:25:58.042806 CA_AAMCK_DIV = 4
2187 19:25:58.045895 CA_ADMCK_DIV = 4
2188 19:25:58.049014 DQ_TRACK_CA_EN = 0
2189 19:25:58.052186 CA_PICK = 1200
2190 19:25:58.055919 CA_MCKIO = 1200
2191 19:25:58.059249 MCKIO_SEMI = 0
2192 19:25:58.062473 PLL_FREQ = 2366
2193 19:25:58.066022 DQ_UI_PI_RATIO = 32
2194 19:25:58.066452 CA_UI_PI_RATIO = 0
2195 19:25:58.068787 ===================================
2196 19:25:58.071976 ===================================
2197 19:25:58.075716 memory_type:LPDDR4
2198 19:25:58.078801 GP_NUM : 10
2199 19:25:58.079439 SRAM_EN : 1
2200 19:25:58.081996 MD32_EN : 0
2201 19:25:58.085697 ===================================
2202 19:25:58.088845 [ANA_INIT] >>>>>>>>>>>>>>
2203 19:25:58.091949 <<<<<< [CONFIGURE PHASE]: ANA_TX
2204 19:25:58.095737 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2205 19:25:58.098767 ===================================
2206 19:25:58.099191 data_rate = 2400,PCW = 0X5b00
2207 19:25:58.102197 ===================================
2208 19:25:58.105091 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2209 19:25:58.111860 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2210 19:25:58.118071 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2211 19:25:58.121142 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2212 19:25:58.124773 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2213 19:25:58.128284 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2214 19:25:58.131375 [ANA_INIT] flow start
2215 19:25:58.134553 [ANA_INIT] PLL >>>>>>>>
2216 19:25:58.134642 [ANA_INIT] PLL <<<<<<<<
2217 19:25:58.138251 [ANA_INIT] MIDPI >>>>>>>>
2218 19:25:58.141277 [ANA_INIT] MIDPI <<<<<<<<
2219 19:25:58.141401 [ANA_INIT] DLL >>>>>>>>
2220 19:25:58.144401 [ANA_INIT] DLL <<<<<<<<
2221 19:25:58.148137 [ANA_INIT] flow end
2222 19:25:58.151026 ============ LP4 DIFF to SE enter ============
2223 19:25:58.154683 ============ LP4 DIFF to SE exit ============
2224 19:25:58.157766 [ANA_INIT] <<<<<<<<<<<<<
2225 19:25:58.161094 [Flow] Enable top DCM control >>>>>
2226 19:25:58.164714 [Flow] Enable top DCM control <<<<<
2227 19:25:58.167630 Enable DLL master slave shuffle
2228 19:25:58.171357 ==============================================================
2229 19:25:58.174235 Gating Mode config
2230 19:25:58.181243 ==============================================================
2231 19:25:58.181355 Config description:
2232 19:25:58.191094 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2233 19:25:58.198083 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2234 19:25:58.201126 SELPH_MODE 0: By rank 1: By Phase
2235 19:25:58.207653 ==============================================================
2236 19:25:58.210654 GAT_TRACK_EN = 1
2237 19:25:58.214456 RX_GATING_MODE = 2
2238 19:25:58.217609 RX_GATING_TRACK_MODE = 2
2239 19:25:58.220685 SELPH_MODE = 1
2240 19:25:58.224083 PICG_EARLY_EN = 1
2241 19:25:58.227200 VALID_LAT_VALUE = 1
2242 19:25:58.231101 ==============================================================
2243 19:25:58.234010 Enter into Gating configuration >>>>
2244 19:25:58.237049 Exit from Gating configuration <<<<
2245 19:25:58.240949 Enter into DVFS_PRE_config >>>>>
2246 19:25:58.253824 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2247 19:25:58.256897 Exit from DVFS_PRE_config <<<<<
2248 19:25:58.260360 Enter into PICG configuration >>>>
2249 19:25:58.260444 Exit from PICG configuration <<<<
2250 19:25:58.264033 [RX_INPUT] configuration >>>>>
2251 19:25:58.266928 [RX_INPUT] configuration <<<<<
2252 19:25:58.273710 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2253 19:25:58.277300 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2254 19:25:58.283650 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2255 19:25:58.290517 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2256 19:25:58.296704 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2257 19:25:58.303579 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2258 19:25:58.306773 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2259 19:25:58.310347 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2260 19:25:58.316846 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2261 19:25:58.319902 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2262 19:25:58.323083 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2263 19:25:58.326647 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2264 19:25:58.329727 ===================================
2265 19:25:58.332877 LPDDR4 DRAM CONFIGURATION
2266 19:25:58.336594 ===================================
2267 19:25:58.339660 EX_ROW_EN[0] = 0x0
2268 19:25:58.339743 EX_ROW_EN[1] = 0x0
2269 19:25:58.343354 LP4Y_EN = 0x0
2270 19:25:58.343438 WORK_FSP = 0x0
2271 19:25:58.346456 WL = 0x4
2272 19:25:58.346539 RL = 0x4
2273 19:25:58.349530 BL = 0x2
2274 19:25:58.349613 RPST = 0x0
2275 19:25:58.353209 RD_PRE = 0x0
2276 19:25:58.353319 WR_PRE = 0x1
2277 19:25:58.356466 WR_PST = 0x0
2278 19:25:58.356548 DBI_WR = 0x0
2279 19:25:58.359448 DBI_RD = 0x0
2280 19:25:58.359531 OTF = 0x1
2281 19:25:58.363055 ===================================
2282 19:25:58.369753 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2283 19:25:58.372716 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2284 19:25:58.375836 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2285 19:25:58.379213 ===================================
2286 19:25:58.382661 LPDDR4 DRAM CONFIGURATION
2287 19:25:58.386102 ===================================
2288 19:25:58.389224 EX_ROW_EN[0] = 0x10
2289 19:25:58.389357 EX_ROW_EN[1] = 0x0
2290 19:25:58.392415 LP4Y_EN = 0x0
2291 19:25:58.392498 WORK_FSP = 0x0
2292 19:25:58.396128 WL = 0x4
2293 19:25:58.396213 RL = 0x4
2294 19:25:58.399188 BL = 0x2
2295 19:25:58.399271 RPST = 0x0
2296 19:25:58.402270 RD_PRE = 0x0
2297 19:25:58.402353 WR_PRE = 0x1
2298 19:25:58.405426 WR_PST = 0x0
2299 19:25:58.405509 DBI_WR = 0x0
2300 19:25:58.408841 DBI_RD = 0x0
2301 19:25:58.412244 OTF = 0x1
2302 19:25:58.415475 ===================================
2303 19:25:58.419108 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2304 19:25:58.419192 ==
2305 19:25:58.422441 Dram Type= 6, Freq= 0, CH_0, rank 0
2306 19:25:58.428797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2307 19:25:58.428882 ==
2308 19:25:58.428948 [Duty_Offset_Calibration]
2309 19:25:58.432435 B0:1 B1:-1 CA:0
2310 19:25:58.432518
2311 19:25:58.435297 [DutyScan_Calibration_Flow] k_type=0
2312 19:25:58.445083
2313 19:25:58.445192 ==CLK 0==
2314 19:25:58.448042 Final CLK duty delay cell = 0
2315 19:25:58.451927 [0] MAX Duty = 5094%(X100), DQS PI = 16
2316 19:25:58.454927 [0] MIN Duty = 4875%(X100), DQS PI = 8
2317 19:25:58.455010 [0] AVG Duty = 4984%(X100)
2318 19:25:58.458101
2319 19:25:58.461742 CH0 CLK Duty spec in!! Max-Min= 219%
2320 19:25:58.464734 [DutyScan_Calibration_Flow] ====Done====
2321 19:25:58.464815
2322 19:25:58.467871 [DutyScan_Calibration_Flow] k_type=1
2323 19:25:58.483502
2324 19:25:58.483589 ==DQS 0 ==
2325 19:25:58.486511 Final DQS duty delay cell = -4
2326 19:25:58.489938 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2327 19:25:58.493282 [-4] MIN Duty = 4875%(X100), DQS PI = 6
2328 19:25:58.496439 [-4] AVG Duty = 4968%(X100)
2329 19:25:58.496529
2330 19:25:58.496595 ==DQS 1 ==
2331 19:25:58.500178 Final DQS duty delay cell = 0
2332 19:25:58.503301 [0] MAX Duty = 5124%(X100), DQS PI = 6
2333 19:25:58.506288 [0] MIN Duty = 5000%(X100), DQS PI = 22
2334 19:25:58.510112 [0] AVG Duty = 5062%(X100)
2335 19:25:58.510195
2336 19:25:58.513112 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2337 19:25:58.513194
2338 19:25:58.516331 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2339 19:25:58.519954 [DutyScan_Calibration_Flow] ====Done====
2340 19:25:58.520037
2341 19:25:58.522821 [DutyScan_Calibration_Flow] k_type=3
2342 19:25:58.540823
2343 19:25:58.540914 ==DQM 0 ==
2344 19:25:58.544118 Final DQM duty delay cell = 0
2345 19:25:58.547468 [0] MAX Duty = 5062%(X100), DQS PI = 20
2346 19:25:58.551010 [0] MIN Duty = 4876%(X100), DQS PI = 8
2347 19:25:58.551130 [0] AVG Duty = 4969%(X100)
2348 19:25:58.554053
2349 19:25:58.554136 ==DQM 1 ==
2350 19:25:58.557205 Final DQM duty delay cell = 4
2351 19:25:58.560868 [4] MAX Duty = 5187%(X100), DQS PI = 14
2352 19:25:58.564158 [4] MIN Duty = 4969%(X100), DQS PI = 26
2353 19:25:58.567271 [4] AVG Duty = 5078%(X100)
2354 19:25:58.567355
2355 19:25:58.571031 CH0 DQM 0 Duty spec in!! Max-Min= 186%
2356 19:25:58.571114
2357 19:25:58.573940 CH0 DQM 1 Duty spec in!! Max-Min= 218%
2358 19:25:58.577735 [DutyScan_Calibration_Flow] ====Done====
2359 19:25:58.577819
2360 19:25:58.580500 [DutyScan_Calibration_Flow] k_type=2
2361 19:25:58.596138
2362 19:25:58.596249 ==DQ 0 ==
2363 19:25:58.598906 Final DQ duty delay cell = -4
2364 19:25:58.602301 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2365 19:25:58.606069 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2366 19:25:58.609110 [-4] AVG Duty = 4969%(X100)
2367 19:25:58.609193
2368 19:25:58.609258 ==DQ 1 ==
2369 19:25:58.612269 Final DQ duty delay cell = -4
2370 19:25:58.615901 [-4] MAX Duty = 5000%(X100), DQS PI = 56
2371 19:25:58.618973 [-4] MIN Duty = 4876%(X100), DQS PI = 16
2372 19:25:58.622699 [-4] AVG Duty = 4938%(X100)
2373 19:25:58.622783
2374 19:25:58.625777 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2375 19:25:58.625860
2376 19:25:58.628841 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2377 19:25:58.632356 [DutyScan_Calibration_Flow] ====Done====
2378 19:25:58.632439 ==
2379 19:25:58.635728 Dram Type= 6, Freq= 0, CH_1, rank 0
2380 19:25:58.639034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2381 19:25:58.639117 ==
2382 19:25:58.642444 [Duty_Offset_Calibration]
2383 19:25:58.642528 B0:-1 B1:1 CA:1
2384 19:25:58.642594
2385 19:25:58.645521 [DutyScan_Calibration_Flow] k_type=0
2386 19:25:58.656549
2387 19:25:58.656632 ==CLK 0==
2388 19:25:58.659548 Final CLK duty delay cell = 0
2389 19:25:58.663026 [0] MAX Duty = 5156%(X100), DQS PI = 22
2390 19:25:58.666206 [0] MIN Duty = 4969%(X100), DQS PI = 60
2391 19:25:58.669689 [0] AVG Duty = 5062%(X100)
2392 19:25:58.669773
2393 19:25:58.673272 CH1 CLK Duty spec in!! Max-Min= 187%
2394 19:25:58.676216 [DutyScan_Calibration_Flow] ====Done====
2395 19:25:58.676299
2396 19:25:58.679363 [DutyScan_Calibration_Flow] k_type=1
2397 19:25:58.695620
2398 19:25:58.695721 ==DQS 0 ==
2399 19:25:58.699428 Final DQS duty delay cell = 0
2400 19:25:58.702525 [0] MAX Duty = 5125%(X100), DQS PI = 48
2401 19:25:58.705935 [0] MIN Duty = 4907%(X100), DQS PI = 6
2402 19:25:58.706035 [0] AVG Duty = 5016%(X100)
2403 19:25:58.709167
2404 19:25:58.709266 ==DQS 1 ==
2405 19:25:58.712331 Final DQS duty delay cell = 0
2406 19:25:58.716009 [0] MAX Duty = 5062%(X100), DQS PI = 12
2407 19:25:58.719085 [0] MIN Duty = 4969%(X100), DQS PI = 56
2408 19:25:58.722257 [0] AVG Duty = 5015%(X100)
2409 19:25:58.722341
2410 19:25:58.725306 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2411 19:25:58.725430
2412 19:25:58.729063 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2413 19:25:58.732230 [DutyScan_Calibration_Flow] ====Done====
2414 19:25:58.732312
2415 19:25:58.735362 [DutyScan_Calibration_Flow] k_type=3
2416 19:25:58.751507
2417 19:25:58.751591 ==DQM 0 ==
2418 19:25:58.754572 Final DQM duty delay cell = -4
2419 19:25:58.758269 [-4] MAX Duty = 5062%(X100), DQS PI = 36
2420 19:25:58.761220 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2421 19:25:58.764361 [-4] AVG Duty = 4953%(X100)
2422 19:25:58.764445
2423 19:25:58.764511 ==DQM 1 ==
2424 19:25:58.768299 Final DQM duty delay cell = 0
2425 19:25:58.771212 [0] MAX Duty = 5125%(X100), DQS PI = 2
2426 19:25:58.774587 [0] MIN Duty = 4969%(X100), DQS PI = 28
2427 19:25:58.777941 [0] AVG Duty = 5047%(X100)
2428 19:25:58.778024
2429 19:25:58.781613 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2430 19:25:58.781696
2431 19:25:58.784705 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2432 19:25:58.787789 [DutyScan_Calibration_Flow] ====Done====
2433 19:25:58.787872
2434 19:25:58.790965 [DutyScan_Calibration_Flow] k_type=2
2435 19:25:58.807861
2436 19:25:58.807948 ==DQ 0 ==
2437 19:25:58.811604 Final DQ duty delay cell = 0
2438 19:25:58.814455 [0] MAX Duty = 5156%(X100), DQS PI = 28
2439 19:25:58.817707 [0] MIN Duty = 4876%(X100), DQS PI = 8
2440 19:25:58.817805 [0] AVG Duty = 5016%(X100)
2441 19:25:58.821339
2442 19:25:58.821423 ==DQ 1 ==
2443 19:25:58.824600 Final DQ duty delay cell = 0
2444 19:25:58.827745 [0] MAX Duty = 5093%(X100), DQS PI = 6
2445 19:25:58.831408 [0] MIN Duty = 4969%(X100), DQS PI = 34
2446 19:25:58.831492 [0] AVG Duty = 5031%(X100)
2447 19:25:58.831559
2448 19:25:58.834438 CH1 DQ 0 Duty spec in!! Max-Min= 280%
2449 19:25:58.838119
2450 19:25:58.841196 CH1 DQ 1 Duty spec in!! Max-Min= 124%
2451 19:25:58.844254 [DutyScan_Calibration_Flow] ====Done====
2452 19:25:58.847999 nWR fixed to 30
2453 19:25:58.848082 [ModeRegInit_LP4] CH0 RK0
2454 19:25:58.851008 [ModeRegInit_LP4] CH0 RK1
2455 19:25:58.854637 [ModeRegInit_LP4] CH1 RK0
2456 19:25:58.857542 [ModeRegInit_LP4] CH1 RK1
2457 19:25:58.857626 match AC timing 7
2458 19:25:58.860881 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2459 19:25:58.867513 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2460 19:25:58.870575 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2461 19:25:58.877369 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2462 19:25:58.880615 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2463 19:25:58.880699 ==
2464 19:25:58.884470 Dram Type= 6, Freq= 0, CH_0, rank 0
2465 19:25:58.887421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2466 19:25:58.887505 ==
2467 19:25:58.893949 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2468 19:25:58.900698 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2469 19:25:58.908276 [CA 0] Center 39 (9~70) winsize 62
2470 19:25:58.911348 [CA 1] Center 39 (9~69) winsize 61
2471 19:25:58.914828 [CA 2] Center 35 (5~66) winsize 62
2472 19:25:58.918017 [CA 3] Center 35 (5~66) winsize 62
2473 19:25:58.921405 [CA 4] Center 33 (4~63) winsize 60
2474 19:25:58.924677 [CA 5] Center 33 (3~63) winsize 61
2475 19:25:58.924880
2476 19:25:58.927868 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2477 19:25:58.928160
2478 19:25:58.931734 [CATrainingPosCal] consider 1 rank data
2479 19:25:58.934751 u2DelayCellTimex100 = 270/100 ps
2480 19:25:58.937756 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2481 19:25:58.941498 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2482 19:25:58.948559 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2483 19:25:58.951473 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2484 19:25:58.954585 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2485 19:25:58.958046 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2486 19:25:58.958477
2487 19:25:58.961170 CA PerBit enable=1, Macro0, CA PI delay=33
2488 19:25:58.961633
2489 19:25:58.964825 [CBTSetCACLKResult] CA Dly = 33
2490 19:25:58.965252 CS Dly: 8 (0~39)
2491 19:25:58.968156 ==
2492 19:25:58.971486 Dram Type= 6, Freq= 0, CH_0, rank 1
2493 19:25:58.975266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2494 19:25:58.975806 ==
2495 19:25:58.977922 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2496 19:25:58.984820 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2497 19:25:58.994196 [CA 0] Center 39 (8~70) winsize 63
2498 19:25:58.997392 [CA 1] Center 39 (9~70) winsize 62
2499 19:25:59.000712 [CA 2] Center 35 (5~66) winsize 62
2500 19:25:59.004156 [CA 3] Center 34 (4~65) winsize 62
2501 19:25:59.007219 [CA 4] Center 33 (3~64) winsize 62
2502 19:25:59.010426 [CA 5] Center 33 (3~63) winsize 61
2503 19:25:59.010856
2504 19:25:59.013531 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2505 19:25:59.013961
2506 19:25:59.017283 [CATrainingPosCal] consider 2 rank data
2507 19:25:59.020476 u2DelayCellTimex100 = 270/100 ps
2508 19:25:59.024072 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2509 19:25:59.030203 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2510 19:25:59.033643 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2511 19:25:59.036785 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2512 19:25:59.040069 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2513 19:25:59.043191 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2514 19:25:59.043618
2515 19:25:59.047020 CA PerBit enable=1, Macro0, CA PI delay=33
2516 19:25:59.047450
2517 19:25:59.050008 [CBTSetCACLKResult] CA Dly = 33
2518 19:25:59.053888 CS Dly: 8 (0~40)
2519 19:25:59.054319
2520 19:25:59.056912 ----->DramcWriteLeveling(PI) begin...
2521 19:25:59.057372 ==
2522 19:25:59.059930 Dram Type= 6, Freq= 0, CH_0, rank 0
2523 19:25:59.063545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2524 19:25:59.063978 ==
2525 19:25:59.066652 Write leveling (Byte 0): 32 => 32
2526 19:25:59.069682 Write leveling (Byte 1): 28 => 28
2527 19:25:59.073222 DramcWriteLeveling(PI) end<-----
2528 19:25:59.073679
2529 19:25:59.074021 ==
2530 19:25:59.076794 Dram Type= 6, Freq= 0, CH_0, rank 0
2531 19:25:59.079733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2532 19:25:59.080166 ==
2533 19:25:59.083062 [Gating] SW mode calibration
2534 19:25:59.090033 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2535 19:25:59.096133 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2536 19:25:59.099730 0 15 0 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
2537 19:25:59.102930 0 15 4 | B1->B0 | 2323 3434 | 1 1 | (0 0) (1 1)
2538 19:25:59.109649 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2539 19:25:59.112845 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2540 19:25:59.116504 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2541 19:25:59.123017 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2542 19:25:59.126355 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2543 19:25:59.129243 0 15 28 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 0)
2544 19:25:59.135867 1 0 0 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (0 0)
2545 19:25:59.139206 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2546 19:25:59.142313 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2547 19:25:59.149056 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2548 19:25:59.152504 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2549 19:25:59.155641 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2550 19:25:59.162085 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2551 19:25:59.165518 1 0 28 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
2552 19:25:59.168686 1 1 0 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
2553 19:25:59.175632 1 1 4 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
2554 19:25:59.178669 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2555 19:25:59.182297 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2556 19:25:59.188742 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2557 19:25:59.191674 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2558 19:25:59.195389 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2559 19:25:59.201576 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2560 19:25:59.205213 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2561 19:25:59.208358 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 19:25:59.215388 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 19:25:59.218448 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 19:25:59.222040 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 19:25:59.228613 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 19:25:59.232256 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 19:25:59.235314 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 19:25:59.241885 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 19:25:59.245145 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 19:25:59.248331 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 19:25:59.255659 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 19:25:59.258453 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 19:25:59.261688 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 19:25:59.265092 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 19:25:59.271535 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2576 19:25:59.274851 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2577 19:25:59.278499 Total UI for P1: 0, mck2ui 16
2578 19:25:59.281967 best dqsien dly found for B0: ( 1, 3, 28)
2579 19:25:59.284965 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2580 19:25:59.288954 Total UI for P1: 0, mck2ui 16
2581 19:25:59.291689 best dqsien dly found for B1: ( 1, 4, 0)
2582 19:25:59.295201 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2583 19:25:59.298163 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2584 19:25:59.301982
2585 19:25:59.305038 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2586 19:25:59.307954 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2587 19:25:59.311733 [Gating] SW calibration Done
2588 19:25:59.312217 ==
2589 19:25:59.314907 Dram Type= 6, Freq= 0, CH_0, rank 0
2590 19:25:59.318466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2591 19:25:59.318893 ==
2592 19:25:59.319228 RX Vref Scan: 0
2593 19:25:59.319542
2594 19:25:59.321727 RX Vref 0 -> 0, step: 1
2595 19:25:59.322192
2596 19:25:59.324687 RX Delay -40 -> 252, step: 8
2597 19:25:59.328257 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2598 19:25:59.331977 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2599 19:25:59.337869 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2600 19:25:59.341395 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2601 19:25:59.344957 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2602 19:25:59.348104 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2603 19:25:59.351290 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2604 19:25:59.358003 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2605 19:25:59.361446 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2606 19:25:59.364593 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2607 19:25:59.367716 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2608 19:25:59.371362 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2609 19:25:59.377586 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2610 19:25:59.380842 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2611 19:25:59.384610 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2612 19:25:59.387514 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2613 19:25:59.387944 ==
2614 19:25:59.391135 Dram Type= 6, Freq= 0, CH_0, rank 0
2615 19:25:59.397617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2616 19:25:59.398130 ==
2617 19:25:59.398624 DQS Delay:
2618 19:25:59.400621 DQS0 = 0, DQS1 = 0
2619 19:25:59.401227 DQM Delay:
2620 19:25:59.404206 DQM0 = 119, DQM1 = 106
2621 19:25:59.404845 DQ Delay:
2622 19:25:59.407485 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2623 19:25:59.410611 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =123
2624 19:25:59.414290 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2625 19:25:59.417371 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2626 19:25:59.417801
2627 19:25:59.418162
2628 19:25:59.418479 ==
2629 19:25:59.420460 Dram Type= 6, Freq= 0, CH_0, rank 0
2630 19:25:59.424069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2631 19:25:59.427263 ==
2632 19:25:59.427903
2633 19:25:59.428469
2634 19:25:59.429084 TX Vref Scan disable
2635 19:25:59.430923 == TX Byte 0 ==
2636 19:25:59.433876 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2637 19:25:59.437384 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2638 19:25:59.440467 == TX Byte 1 ==
2639 19:25:59.444228 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2640 19:25:59.447014 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2641 19:25:59.450716 ==
2642 19:25:59.453813 Dram Type= 6, Freq= 0, CH_0, rank 0
2643 19:25:59.456860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2644 19:25:59.457509 ==
2645 19:25:59.468280 TX Vref=22, minBit 13, minWin=24, winSum=411
2646 19:25:59.471996 TX Vref=24, minBit 1, minWin=25, winSum=418
2647 19:25:59.475219 TX Vref=26, minBit 13, minWin=25, winSum=425
2648 19:25:59.478293 TX Vref=28, minBit 1, minWin=26, winSum=428
2649 19:25:59.481386 TX Vref=30, minBit 5, minWin=26, winSum=430
2650 19:25:59.488217 TX Vref=32, minBit 5, minWin=26, winSum=429
2651 19:25:59.491661 [TxChooseVref] Worse bit 5, Min win 26, Win sum 430, Final Vref 30
2652 19:25:59.492125
2653 19:25:59.495047 Final TX Range 1 Vref 30
2654 19:25:59.495647
2655 19:25:59.496199 ==
2656 19:25:59.498037 Dram Type= 6, Freq= 0, CH_0, rank 0
2657 19:25:59.505031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2658 19:25:59.505584 ==
2659 19:25:59.506138
2660 19:25:59.506599
2661 19:25:59.506920 TX Vref Scan disable
2662 19:25:59.508651 == TX Byte 0 ==
2663 19:25:59.511500 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2664 19:25:59.518398 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2665 19:25:59.518854 == TX Byte 1 ==
2666 19:25:59.521248 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2667 19:25:59.528104 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2668 19:25:59.528677
2669 19:25:59.529176 [DATLAT]
2670 19:25:59.529608 Freq=1200, CH0 RK0
2671 19:25:59.529958
2672 19:25:59.531194 DATLAT Default: 0xd
2673 19:25:59.534910 0, 0xFFFF, sum = 0
2674 19:25:59.535500 1, 0xFFFF, sum = 0
2675 19:25:59.537878 2, 0xFFFF, sum = 0
2676 19:25:59.538310 3, 0xFFFF, sum = 0
2677 19:25:59.541327 4, 0xFFFF, sum = 0
2678 19:25:59.541814 5, 0xFFFF, sum = 0
2679 19:25:59.544473 6, 0xFFFF, sum = 0
2680 19:25:59.544926 7, 0xFFFF, sum = 0
2681 19:25:59.548163 8, 0xFFFF, sum = 0
2682 19:25:59.548743 9, 0xFFFF, sum = 0
2683 19:25:59.551116 10, 0xFFFF, sum = 0
2684 19:25:59.551576 11, 0xFFFF, sum = 0
2685 19:25:59.554631 12, 0x0, sum = 1
2686 19:25:59.555066 13, 0x0, sum = 2
2687 19:25:59.557743 14, 0x0, sum = 3
2688 19:25:59.558178 15, 0x0, sum = 4
2689 19:25:59.561635 best_step = 13
2690 19:25:59.562062
2691 19:25:59.562405 ==
2692 19:25:59.564686 Dram Type= 6, Freq= 0, CH_0, rank 0
2693 19:25:59.568075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2694 19:25:59.568651 ==
2695 19:25:59.569002 RX Vref Scan: 1
2696 19:25:59.571188
2697 19:25:59.571613 Set Vref Range= 32 -> 127
2698 19:25:59.571958
2699 19:25:59.574819 RX Vref 32 -> 127, step: 1
2700 19:25:59.575399
2701 19:25:59.577793 RX Delay -21 -> 252, step: 4
2702 19:25:59.578248
2703 19:25:59.581131 Set Vref, RX VrefLevel [Byte0]: 32
2704 19:25:59.584133 [Byte1]: 32
2705 19:25:59.584657
2706 19:25:59.587848 Set Vref, RX VrefLevel [Byte0]: 33
2707 19:25:59.590974 [Byte1]: 33
2708 19:25:59.594599
2709 19:25:59.595196 Set Vref, RX VrefLevel [Byte0]: 34
2710 19:25:59.597980 [Byte1]: 34
2711 19:25:59.602895
2712 19:25:59.603501 Set Vref, RX VrefLevel [Byte0]: 35
2713 19:25:59.605876 [Byte1]: 35
2714 19:25:59.610441
2715 19:25:59.610863 Set Vref, RX VrefLevel [Byte0]: 36
2716 19:25:59.614089 [Byte1]: 36
2717 19:25:59.618513
2718 19:25:59.618935 Set Vref, RX VrefLevel [Byte0]: 37
2719 19:25:59.621913 [Byte1]: 37
2720 19:25:59.626562
2721 19:25:59.626985 Set Vref, RX VrefLevel [Byte0]: 38
2722 19:25:59.632951 [Byte1]: 38
2723 19:25:59.633553
2724 19:25:59.636351 Set Vref, RX VrefLevel [Byte0]: 39
2725 19:25:59.639839 [Byte1]: 39
2726 19:25:59.640278
2727 19:25:59.642997 Set Vref, RX VrefLevel [Byte0]: 40
2728 19:25:59.646379 [Byte1]: 40
2729 19:25:59.650029
2730 19:25:59.650653 Set Vref, RX VrefLevel [Byte0]: 41
2731 19:25:59.653820 [Byte1]: 41
2732 19:25:59.658056
2733 19:25:59.658499 Set Vref, RX VrefLevel [Byte0]: 42
2734 19:25:59.661537 [Byte1]: 42
2735 19:25:59.666436
2736 19:25:59.666858 Set Vref, RX VrefLevel [Byte0]: 43
2737 19:25:59.669412 [Byte1]: 43
2738 19:25:59.674251
2739 19:25:59.674771 Set Vref, RX VrefLevel [Byte0]: 44
2740 19:25:59.677377 [Byte1]: 44
2741 19:25:59.682185
2742 19:25:59.682608 Set Vref, RX VrefLevel [Byte0]: 45
2743 19:25:59.685323 [Byte1]: 45
2744 19:25:59.690264
2745 19:25:59.690775 Set Vref, RX VrefLevel [Byte0]: 46
2746 19:25:59.693253 [Byte1]: 46
2747 19:25:59.698298
2748 19:25:59.698720 Set Vref, RX VrefLevel [Byte0]: 47
2749 19:25:59.701298 [Byte1]: 47
2750 19:25:59.705847
2751 19:25:59.706361 Set Vref, RX VrefLevel [Byte0]: 48
2752 19:25:59.709357 [Byte1]: 48
2753 19:25:59.713429
2754 19:25:59.713940 Set Vref, RX VrefLevel [Byte0]: 49
2755 19:25:59.716810 [Byte1]: 49
2756 19:25:59.721900
2757 19:25:59.722325 Set Vref, RX VrefLevel [Byte0]: 50
2758 19:25:59.724930 [Byte1]: 50
2759 19:25:59.729318
2760 19:25:59.729995 Set Vref, RX VrefLevel [Byte0]: 51
2761 19:25:59.732947 [Byte1]: 51
2762 19:25:59.737485
2763 19:25:59.738014 Set Vref, RX VrefLevel [Byte0]: 52
2764 19:25:59.740613 [Byte1]: 52
2765 19:25:59.745503
2766 19:25:59.745929 Set Vref, RX VrefLevel [Byte0]: 53
2767 19:25:59.748536 [Byte1]: 53
2768 19:25:59.753494
2769 19:25:59.753920 Set Vref, RX VrefLevel [Byte0]: 54
2770 19:25:59.756431 [Byte1]: 54
2771 19:25:59.761324
2772 19:25:59.761773 Set Vref, RX VrefLevel [Byte0]: 55
2773 19:25:59.764779 [Byte1]: 55
2774 19:25:59.769547
2775 19:25:59.769981 Set Vref, RX VrefLevel [Byte0]: 56
2776 19:25:59.772673 [Byte1]: 56
2777 19:25:59.781588
2778 19:25:59.782035 Set Vref, RX VrefLevel [Byte0]: 57
2779 19:25:59.782716 [Byte1]: 57
2780 19:25:59.785149
2781 19:25:59.785704 Set Vref, RX VrefLevel [Byte0]: 58
2782 19:25:59.788196 [Byte1]: 58
2783 19:25:59.793280
2784 19:25:59.793695 Set Vref, RX VrefLevel [Byte0]: 59
2785 19:25:59.796185 [Byte1]: 59
2786 19:25:59.801106
2787 19:25:59.801651 Set Vref, RX VrefLevel [Byte0]: 60
2788 19:25:59.804375 [Byte1]: 60
2789 19:25:59.809215
2790 19:25:59.809698 Set Vref, RX VrefLevel [Byte0]: 61
2791 19:25:59.811915 [Byte1]: 61
2792 19:25:59.816752
2793 19:25:59.817321 Set Vref, RX VrefLevel [Byte0]: 62
2794 19:25:59.820038 [Byte1]: 62
2795 19:25:59.824744
2796 19:25:59.825375 Set Vref, RX VrefLevel [Byte0]: 63
2797 19:25:59.830862 [Byte1]: 63
2798 19:25:59.831490
2799 19:25:59.834734 Set Vref, RX VrefLevel [Byte0]: 64
2800 19:25:59.837776 [Byte1]: 64
2801 19:25:59.838356
2802 19:25:59.840840 Set Vref, RX VrefLevel [Byte0]: 65
2803 19:25:59.844343 [Byte1]: 65
2804 19:25:59.848299
2805 19:25:59.848867 Set Vref, RX VrefLevel [Byte0]: 66
2806 19:25:59.851630 [Byte1]: 66
2807 19:25:59.856005
2808 19:25:59.856444 Set Vref, RX VrefLevel [Byte0]: 67
2809 19:25:59.859919 [Byte1]: 67
2810 19:25:59.864749
2811 19:25:59.865263 Set Vref, RX VrefLevel [Byte0]: 68
2812 19:25:59.867515 [Byte1]: 68
2813 19:25:59.872443
2814 19:25:59.872981 Set Vref, RX VrefLevel [Byte0]: 69
2815 19:25:59.875626 [Byte1]: 69
2816 19:25:59.880232
2817 19:25:59.880751 Set Vref, RX VrefLevel [Byte0]: 70
2818 19:25:59.883334 [Byte1]: 70
2819 19:25:59.888447
2820 19:25:59.888966 Set Vref, RX VrefLevel [Byte0]: 71
2821 19:25:59.891201 [Byte1]: 71
2822 19:25:59.896331
2823 19:25:59.896853 Set Vref, RX VrefLevel [Byte0]: 72
2824 19:25:59.899244 [Byte1]: 72
2825 19:25:59.904245
2826 19:25:59.904667 Set Vref, RX VrefLevel [Byte0]: 73
2827 19:25:59.907321 [Byte1]: 73
2828 19:25:59.912296
2829 19:25:59.912742 Set Vref, RX VrefLevel [Byte0]: 74
2830 19:25:59.915261 [Byte1]: 74
2831 19:25:59.919715
2832 19:25:59.920180 Set Vref, RX VrefLevel [Byte0]: 75
2833 19:25:59.923435 [Byte1]: 75
2834 19:25:59.927923
2835 19:25:59.928354 Set Vref, RX VrefLevel [Byte0]: 76
2836 19:25:59.931444 [Byte1]: 76
2837 19:25:59.935715
2838 19:25:59.936142 Set Vref, RX VrefLevel [Byte0]: 77
2839 19:25:59.938955 [Byte1]: 77
2840 19:25:59.943644
2841 19:25:59.944069 Set Vref, RX VrefLevel [Byte0]: 78
2842 19:25:59.946922 [Byte1]: 78
2843 19:25:59.951822
2844 19:25:59.952413 Final RX Vref Byte 0 = 57 to rank0
2845 19:25:59.954925 Final RX Vref Byte 1 = 48 to rank0
2846 19:25:59.957884 Final RX Vref Byte 0 = 57 to rank1
2847 19:25:59.961440 Final RX Vref Byte 1 = 48 to rank1==
2848 19:25:59.964715 Dram Type= 6, Freq= 0, CH_0, rank 0
2849 19:25:59.971026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2850 19:25:59.971590 ==
2851 19:25:59.972100 DQS Delay:
2852 19:25:59.974588 DQS0 = 0, DQS1 = 0
2853 19:25:59.975012 DQM Delay:
2854 19:25:59.975369 DQM0 = 118, DQM1 = 106
2855 19:25:59.978036 DQ Delay:
2856 19:25:59.981320 DQ0 =116, DQ1 =118, DQ2 =114, DQ3 =114
2857 19:25:59.984932 DQ4 =120, DQ5 =110, DQ6 =126, DQ7 =126
2858 19:25:59.988206 DQ8 =98, DQ9 =92, DQ10 =108, DQ11 =100
2859 19:25:59.991120 DQ12 =112, DQ13 =108, DQ14 =118, DQ15 =116
2860 19:25:59.991544
2861 19:25:59.991877
2862 19:26:00.000929 [DQSOSCAuto] RK0, (LSB)MR18= 0xdf9, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 405 ps
2863 19:26:00.001499 CH0 RK0: MR19=403, MR18=DF9
2864 19:26:00.007719 CH0_RK0: MR19=0x403, MR18=0xDF9, DQSOSC=405, MR23=63, INC=39, DEC=26
2865 19:26:00.008166
2866 19:26:00.010880 ----->DramcWriteLeveling(PI) begin...
2867 19:26:00.011308 ==
2868 19:26:00.014487 Dram Type= 6, Freq= 0, CH_0, rank 1
2869 19:26:00.017399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2870 19:26:00.021062 ==
2871 19:26:00.021524 Write leveling (Byte 0): 34 => 34
2872 19:26:00.023940 Write leveling (Byte 1): 28 => 28
2873 19:26:00.027575 DramcWriteLeveling(PI) end<-----
2874 19:26:00.028025
2875 19:26:00.028365 ==
2876 19:26:00.031077 Dram Type= 6, Freq= 0, CH_0, rank 1
2877 19:26:00.037472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2878 19:26:00.037907 ==
2879 19:26:00.040701 [Gating] SW mode calibration
2880 19:26:00.047689 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2881 19:26:00.050547 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2882 19:26:00.057356 0 15 0 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
2883 19:26:00.061067 0 15 4 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
2884 19:26:00.064028 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2885 19:26:00.070623 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2886 19:26:00.073603 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2887 19:26:00.077137 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2888 19:26:00.083841 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2889 19:26:00.086755 0 15 28 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
2890 19:26:00.090752 1 0 0 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (0 0)
2891 19:26:00.096720 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2892 19:26:00.099957 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2893 19:26:00.103290 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2894 19:26:00.110127 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2895 19:26:00.113235 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2896 19:26:00.116342 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2897 19:26:00.123040 1 0 28 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
2898 19:26:00.126544 1 1 0 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
2899 19:26:00.130234 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2900 19:26:00.136233 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2901 19:26:00.139870 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2902 19:26:00.143407 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2903 19:26:00.149419 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2904 19:26:00.153042 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2905 19:26:00.156182 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2906 19:26:00.162982 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2907 19:26:00.166531 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2908 19:26:00.169448 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2909 19:26:00.173141 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2910 19:26:00.179484 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2911 19:26:00.183045 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2912 19:26:00.186021 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2913 19:26:00.193065 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2914 19:26:00.196066 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2915 19:26:00.199523 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2916 19:26:00.206171 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2917 19:26:00.209432 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2918 19:26:00.213113 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2919 19:26:00.219442 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 19:26:00.222471 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 19:26:00.226230 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2922 19:26:00.232698 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2923 19:26:00.235812 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2924 19:26:00.239258 Total UI for P1: 0, mck2ui 16
2925 19:26:00.243079 best dqsien dly found for B0: ( 1, 3, 30)
2926 19:26:00.246351 Total UI for P1: 0, mck2ui 16
2927 19:26:00.249229 best dqsien dly found for B1: ( 1, 4, 0)
2928 19:26:00.252766 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2929 19:26:00.255944 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2930 19:26:00.256483
2931 19:26:00.259515 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2932 19:26:00.262693 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2933 19:26:00.265817 [Gating] SW calibration Done
2934 19:26:00.266244 ==
2935 19:26:00.269138 Dram Type= 6, Freq= 0, CH_0, rank 1
2936 19:26:00.272782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2937 19:26:00.275566 ==
2938 19:26:00.275991 RX Vref Scan: 0
2939 19:26:00.276367
2940 19:26:00.278808 RX Vref 0 -> 0, step: 1
2941 19:26:00.279229
2942 19:26:00.282614 RX Delay -40 -> 252, step: 8
2943 19:26:00.285721 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
2944 19:26:00.288549 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2945 19:26:00.292368 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2946 19:26:00.295338 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2947 19:26:00.302192 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2948 19:26:00.305619 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2949 19:26:00.308528 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2950 19:26:00.311573 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2951 19:26:00.315176 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2952 19:26:00.322039 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2953 19:26:00.324896 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2954 19:26:00.328552 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2955 19:26:00.332346 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2956 19:26:00.338248 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2957 19:26:00.341914 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2958 19:26:00.345495 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2959 19:26:00.346085 ==
2960 19:26:00.348363 Dram Type= 6, Freq= 0, CH_0, rank 1
2961 19:26:00.351391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2962 19:26:00.351878 ==
2963 19:26:00.355217 DQS Delay:
2964 19:26:00.355847 DQS0 = 0, DQS1 = 0
2965 19:26:00.358079 DQM Delay:
2966 19:26:00.358681 DQM0 = 118, DQM1 = 108
2967 19:26:00.359186 DQ Delay:
2968 19:26:00.361544 DQ0 =115, DQ1 =119, DQ2 =111, DQ3 =115
2969 19:26:00.367921 DQ4 =119, DQ5 =111, DQ6 =127, DQ7 =127
2970 19:26:00.371634 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
2971 19:26:00.374846 DQ12 =111, DQ13 =119, DQ14 =119, DQ15 =111
2972 19:26:00.375441
2973 19:26:00.375996
2974 19:26:00.376541 ==
2975 19:26:00.377923 Dram Type= 6, Freq= 0, CH_0, rank 1
2976 19:26:00.381536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2977 19:26:00.382092 ==
2978 19:26:00.382481
2979 19:26:00.382825
2980 19:26:00.384534 TX Vref Scan disable
2981 19:26:00.388322 == TX Byte 0 ==
2982 19:26:00.391355 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2983 19:26:00.394605 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2984 19:26:00.397800 == TX Byte 1 ==
2985 19:26:00.401032 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2986 19:26:00.404703 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2987 19:26:00.405396 ==
2988 19:26:00.407825 Dram Type= 6, Freq= 0, CH_0, rank 1
2989 19:26:00.411362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2990 19:26:00.414194 ==
2991 19:26:00.424957 TX Vref=22, minBit 4, minWin=25, winSum=417
2992 19:26:00.428288 TX Vref=24, minBit 0, minWin=26, winSum=421
2993 19:26:00.431940 TX Vref=26, minBit 2, minWin=26, winSum=427
2994 19:26:00.435106 TX Vref=28, minBit 10, minWin=26, winSum=431
2995 19:26:00.438271 TX Vref=30, minBit 4, minWin=26, winSum=431
2996 19:26:00.444380 TX Vref=32, minBit 10, minWin=26, winSum=432
2997 19:26:00.448146 [TxChooseVref] Worse bit 10, Min win 26, Win sum 432, Final Vref 32
2998 19:26:00.448787
2999 19:26:00.451332 Final TX Range 1 Vref 32
3000 19:26:00.451762
3001 19:26:00.452098 ==
3002 19:26:00.454332 Dram Type= 6, Freq= 0, CH_0, rank 1
3003 19:26:00.460792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3004 19:26:00.461398 ==
3005 19:26:00.462002
3006 19:26:00.462585
3007 19:26:00.463006 TX Vref Scan disable
3008 19:26:00.465111 == TX Byte 0 ==
3009 19:26:00.468151 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3010 19:26:00.475480 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3011 19:26:00.476162 == TX Byte 1 ==
3012 19:26:00.478404 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3013 19:26:00.484718 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3014 19:26:00.485427
3015 19:26:00.485943 [DATLAT]
3016 19:26:00.486417 Freq=1200, CH0 RK1
3017 19:26:00.486894
3018 19:26:00.488453 DATLAT Default: 0xd
3019 19:26:00.489132 0, 0xFFFF, sum = 0
3020 19:26:00.491659 1, 0xFFFF, sum = 0
3021 19:26:00.494967 2, 0xFFFF, sum = 0
3022 19:26:00.495524 3, 0xFFFF, sum = 0
3023 19:26:00.498531 4, 0xFFFF, sum = 0
3024 19:26:00.498964 5, 0xFFFF, sum = 0
3025 19:26:00.501439 6, 0xFFFF, sum = 0
3026 19:26:00.502016 7, 0xFFFF, sum = 0
3027 19:26:00.505223 8, 0xFFFF, sum = 0
3028 19:26:00.505750 9, 0xFFFF, sum = 0
3029 19:26:00.508161 10, 0xFFFF, sum = 0
3030 19:26:00.508740 11, 0xFFFF, sum = 0
3031 19:26:00.511461 12, 0x0, sum = 1
3032 19:26:00.511900 13, 0x0, sum = 2
3033 19:26:00.515186 14, 0x0, sum = 3
3034 19:26:00.515668 15, 0x0, sum = 4
3035 19:26:00.518218 best_step = 13
3036 19:26:00.518643
3037 19:26:00.518996 ==
3038 19:26:00.521540 Dram Type= 6, Freq= 0, CH_0, rank 1
3039 19:26:00.524927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3040 19:26:00.525667 ==
3041 19:26:00.526249 RX Vref Scan: 0
3042 19:26:00.527754
3043 19:26:00.528406 RX Vref 0 -> 0, step: 1
3044 19:26:00.528940
3045 19:26:00.531400 RX Delay -21 -> 252, step: 4
3046 19:26:00.537585 iDelay=195, Bit 0, Center 112 (47 ~ 178) 132
3047 19:26:00.541425 iDelay=195, Bit 1, Center 118 (47 ~ 190) 144
3048 19:26:00.544311 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3049 19:26:00.547681 iDelay=195, Bit 3, Center 112 (43 ~ 182) 140
3050 19:26:00.551112 iDelay=195, Bit 4, Center 116 (47 ~ 186) 140
3051 19:26:00.557801 iDelay=195, Bit 5, Center 110 (43 ~ 178) 136
3052 19:26:00.561136 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
3053 19:26:00.564390 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3054 19:26:00.568137 iDelay=195, Bit 8, Center 96 (27 ~ 166) 140
3055 19:26:00.571156 iDelay=195, Bit 9, Center 94 (27 ~ 162) 136
3056 19:26:00.574285 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3057 19:26:00.580773 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3058 19:26:00.584591 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3059 19:26:00.587641 iDelay=195, Bit 13, Center 114 (47 ~ 182) 136
3060 19:26:00.591208 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3061 19:26:00.597422 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3062 19:26:00.598102 ==
3063 19:26:00.601019 Dram Type= 6, Freq= 0, CH_0, rank 1
3064 19:26:00.604159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3065 19:26:00.604726 ==
3066 19:26:00.605248 DQS Delay:
3067 19:26:00.607204 DQS0 = 0, DQS1 = 0
3068 19:26:00.607767 DQM Delay:
3069 19:26:00.610808 DQM0 = 115, DQM1 = 107
3070 19:26:00.611253 DQ Delay:
3071 19:26:00.613844 DQ0 =112, DQ1 =118, DQ2 =110, DQ3 =112
3072 19:26:00.617036 DQ4 =116, DQ5 =110, DQ6 =124, DQ7 =124
3073 19:26:00.620885 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =100
3074 19:26:00.624054 DQ12 =112, DQ13 =114, DQ14 =118, DQ15 =116
3075 19:26:00.624485
3076 19:26:00.624823
3077 19:26:00.634033 [DQSOSCAuto] RK1, (LSB)MR18= 0xae5, (MSB)MR19= 0x403, tDQSOscB0 = 421 ps tDQSOscB1 = 406 ps
3078 19:26:00.637377 CH0 RK1: MR19=403, MR18=AE5
3079 19:26:00.640341 CH0_RK1: MR19=0x403, MR18=0xAE5, DQSOSC=406, MR23=63, INC=39, DEC=26
3080 19:26:00.644057 [RxdqsGatingPostProcess] freq 1200
3081 19:26:00.650132 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3082 19:26:00.654078 best DQS0 dly(2T, 0.5T) = (0, 11)
3083 19:26:00.657199 best DQS1 dly(2T, 0.5T) = (0, 12)
3084 19:26:00.660290 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3085 19:26:00.663631 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3086 19:26:00.666985 best DQS0 dly(2T, 0.5T) = (0, 11)
3087 19:26:00.670272 best DQS1 dly(2T, 0.5T) = (0, 12)
3088 19:26:00.673258 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3089 19:26:00.676941 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3090 19:26:00.680076 Pre-setting of DQS Precalculation
3091 19:26:00.683297 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3092 19:26:00.683744 ==
3093 19:26:00.686735 Dram Type= 6, Freq= 0, CH_1, rank 0
3094 19:26:00.690330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3095 19:26:00.690796 ==
3096 19:26:00.696351 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3097 19:26:00.703122 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3098 19:26:00.711288 [CA 0] Center 37 (7~67) winsize 61
3099 19:26:00.714240 [CA 1] Center 38 (8~68) winsize 61
3100 19:26:00.718040 [CA 2] Center 34 (4~64) winsize 61
3101 19:26:00.720990 [CA 3] Center 34 (4~64) winsize 61
3102 19:26:00.724087 [CA 4] Center 34 (4~65) winsize 62
3103 19:26:00.727893 [CA 5] Center 33 (3~64) winsize 62
3104 19:26:00.728322
3105 19:26:00.731071 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3106 19:26:00.731663
3107 19:26:00.734597 [CATrainingPosCal] consider 1 rank data
3108 19:26:00.737631 u2DelayCellTimex100 = 270/100 ps
3109 19:26:00.740517 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3110 19:26:00.747275 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3111 19:26:00.750539 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3112 19:26:00.754202 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3113 19:26:00.757415 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3114 19:26:00.760850 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3115 19:26:00.761374
3116 19:26:00.763840 CA PerBit enable=1, Macro0, CA PI delay=33
3117 19:26:00.764277
3118 19:26:00.767397 [CBTSetCACLKResult] CA Dly = 33
3119 19:26:00.770557 CS Dly: 5 (0~36)
3120 19:26:00.771080 ==
3121 19:26:00.773712 Dram Type= 6, Freq= 0, CH_1, rank 1
3122 19:26:00.777237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3123 19:26:00.777739 ==
3124 19:26:00.783619 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3125 19:26:00.786740 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3126 19:26:00.796716 [CA 0] Center 37 (7~68) winsize 62
3127 19:26:00.799901 [CA 1] Center 38 (8~68) winsize 61
3128 19:26:00.803042 [CA 2] Center 34 (4~65) winsize 62
3129 19:26:00.806483 [CA 3] Center 33 (3~64) winsize 62
3130 19:26:00.809683 [CA 4] Center 34 (3~65) winsize 63
3131 19:26:00.813148 [CA 5] Center 33 (3~64) winsize 62
3132 19:26:00.813662
3133 19:26:00.816368 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3134 19:26:00.816838
3135 19:26:00.819772 [CATrainingPosCal] consider 2 rank data
3136 19:26:00.822804 u2DelayCellTimex100 = 270/100 ps
3137 19:26:00.826078 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3138 19:26:00.832891 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3139 19:26:00.836013 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3140 19:26:00.839261 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3141 19:26:00.842891 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3142 19:26:00.846019 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3143 19:26:00.846286
3144 19:26:00.848909 CA PerBit enable=1, Macro0, CA PI delay=33
3145 19:26:00.849209
3146 19:26:00.852520 [CBTSetCACLKResult] CA Dly = 33
3147 19:26:00.855436 CS Dly: 7 (0~40)
3148 19:26:00.855678
3149 19:26:00.858701 ----->DramcWriteLeveling(PI) begin...
3150 19:26:00.858896 ==
3151 19:26:00.862246 Dram Type= 6, Freq= 0, CH_1, rank 0
3152 19:26:00.865923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3153 19:26:00.866073 ==
3154 19:26:00.868880 Write leveling (Byte 0): 23 => 23
3155 19:26:00.872419 Write leveling (Byte 1): 27 => 27
3156 19:26:00.875531 DramcWriteLeveling(PI) end<-----
3157 19:26:00.875653
3158 19:26:00.875746 ==
3159 19:26:00.878808 Dram Type= 6, Freq= 0, CH_1, rank 0
3160 19:26:00.882469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3161 19:26:00.882553 ==
3162 19:26:00.885691 [Gating] SW mode calibration
3163 19:26:00.892143 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3164 19:26:00.898354 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3165 19:26:00.902052 0 15 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
3166 19:26:00.905046 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3167 19:26:00.911722 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3168 19:26:00.915260 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3169 19:26:00.918241 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3170 19:26:00.925073 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3171 19:26:00.928423 0 15 24 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 0)
3172 19:26:00.931556 0 15 28 | B1->B0 | 2525 2323 | 0 0 | (1 0) (1 0)
3173 19:26:00.937973 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3174 19:26:00.941769 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3175 19:26:00.944687 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3176 19:26:00.951445 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3177 19:26:00.955142 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3178 19:26:00.958233 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3179 19:26:00.964386 1 0 24 | B1->B0 | 2423 3131 | 1 0 | (0 0) (1 1)
3180 19:26:00.968009 1 0 28 | B1->B0 | 4343 4646 | 1 0 | (0 0) (0 0)
3181 19:26:00.971476 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3182 19:26:00.977824 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3183 19:26:00.981492 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3184 19:26:00.984692 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3185 19:26:00.991032 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3186 19:26:00.994628 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3187 19:26:00.998264 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3188 19:26:01.004408 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3189 19:26:01.008202 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3190 19:26:01.011404 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3191 19:26:01.017514 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3192 19:26:01.021061 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3193 19:26:01.024679 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3194 19:26:01.031041 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3195 19:26:01.034301 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3196 19:26:01.037460 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3197 19:26:01.044364 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3198 19:26:01.047607 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3199 19:26:01.050649 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3200 19:26:01.057817 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3201 19:26:01.060964 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3202 19:26:01.063995 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 19:26:01.070756 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3204 19:26:01.073781 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3205 19:26:01.077140 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3206 19:26:01.080765 Total UI for P1: 0, mck2ui 16
3207 19:26:01.083867 best dqsien dly found for B0: ( 1, 3, 26)
3208 19:26:01.086951 Total UI for P1: 0, mck2ui 16
3209 19:26:01.090412 best dqsien dly found for B1: ( 1, 3, 26)
3210 19:26:01.093930 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3211 19:26:01.096889 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3212 19:26:01.096971
3213 19:26:01.100320 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3214 19:26:01.106696 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3215 19:26:01.106787 [Gating] SW calibration Done
3216 19:26:01.110403 ==
3217 19:26:01.110486 Dram Type= 6, Freq= 0, CH_1, rank 0
3218 19:26:01.116656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3219 19:26:01.116745 ==
3220 19:26:01.116818 RX Vref Scan: 0
3221 19:26:01.116918
3222 19:26:01.120297 RX Vref 0 -> 0, step: 1
3223 19:26:01.120403
3224 19:26:01.123398 RX Delay -40 -> 252, step: 8
3225 19:26:01.126968 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3226 19:26:01.129952 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3227 19:26:01.133149 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3228 19:26:01.139890 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3229 19:26:01.143480 iDelay=208, Bit 4, Center 111 (40 ~ 183) 144
3230 19:26:01.146534 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3231 19:26:01.150105 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3232 19:26:01.152870 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3233 19:26:01.159894 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3234 19:26:01.163200 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3235 19:26:01.166488 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3236 19:26:01.169868 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3237 19:26:01.173227 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3238 19:26:01.179794 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3239 19:26:01.182863 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3240 19:26:01.186367 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3241 19:26:01.186444 ==
3242 19:26:01.189299 Dram Type= 6, Freq= 0, CH_1, rank 0
3243 19:26:01.193095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3244 19:26:01.196123 ==
3245 19:26:01.196228 DQS Delay:
3246 19:26:01.196321 DQS0 = 0, DQS1 = 0
3247 19:26:01.199336 DQM Delay:
3248 19:26:01.199439 DQM0 = 117, DQM1 = 109
3249 19:26:01.202929 DQ Delay:
3250 19:26:01.206568 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =115
3251 19:26:01.209889 DQ4 =111, DQ5 =131, DQ6 =123, DQ7 =115
3252 19:26:01.212714 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =99
3253 19:26:01.215925 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =119
3254 19:26:01.216004
3255 19:26:01.216069
3256 19:26:01.216133 ==
3257 19:26:01.219556 Dram Type= 6, Freq= 0, CH_1, rank 0
3258 19:26:01.222566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3259 19:26:01.222647 ==
3260 19:26:01.222711
3261 19:26:01.222772
3262 19:26:01.226246 TX Vref Scan disable
3263 19:26:01.229262 == TX Byte 0 ==
3264 19:26:01.232383 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3265 19:26:01.235945 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3266 19:26:01.239122 == TX Byte 1 ==
3267 19:26:01.242353 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3268 19:26:01.245769 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3269 19:26:01.245856 ==
3270 19:26:01.248890 Dram Type= 6, Freq= 0, CH_1, rank 0
3271 19:26:01.255527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3272 19:26:01.255610 ==
3273 19:26:01.266035 TX Vref=22, minBit 11, minWin=24, winSum=414
3274 19:26:01.269581 TX Vref=24, minBit 10, minWin=25, winSum=424
3275 19:26:01.272718 TX Vref=26, minBit 9, minWin=25, winSum=426
3276 19:26:01.276436 TX Vref=28, minBit 9, minWin=26, winSum=433
3277 19:26:01.279376 TX Vref=30, minBit 9, minWin=25, winSum=428
3278 19:26:01.285933 TX Vref=32, minBit 9, minWin=25, winSum=426
3279 19:26:01.289060 [TxChooseVref] Worse bit 9, Min win 26, Win sum 433, Final Vref 28
3280 19:26:01.289166
3281 19:26:01.292639 Final TX Range 1 Vref 28
3282 19:26:01.292721
3283 19:26:01.292785 ==
3284 19:26:01.295635 Dram Type= 6, Freq= 0, CH_1, rank 0
3285 19:26:01.302511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3286 19:26:01.302591 ==
3287 19:26:01.302660
3288 19:26:01.302725
3289 19:26:01.302785 TX Vref Scan disable
3290 19:26:01.306135 == TX Byte 0 ==
3291 19:26:01.309619 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3292 19:26:01.316358 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3293 19:26:01.316443 == TX Byte 1 ==
3294 19:26:01.319399 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3295 19:26:01.326345 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3296 19:26:01.326425
3297 19:26:01.326490 [DATLAT]
3298 19:26:01.326554 Freq=1200, CH1 RK0
3299 19:26:01.326619
3300 19:26:01.329551 DATLAT Default: 0xd
3301 19:26:01.329621 0, 0xFFFF, sum = 0
3302 19:26:01.333103 1, 0xFFFF, sum = 0
3303 19:26:01.333179 2, 0xFFFF, sum = 0
3304 19:26:01.336169 3, 0xFFFF, sum = 0
3305 19:26:01.339297 4, 0xFFFF, sum = 0
3306 19:26:01.339379 5, 0xFFFF, sum = 0
3307 19:26:01.342456 6, 0xFFFF, sum = 0
3308 19:26:01.342536 7, 0xFFFF, sum = 0
3309 19:26:01.346128 8, 0xFFFF, sum = 0
3310 19:26:01.346203 9, 0xFFFF, sum = 0
3311 19:26:01.349136 10, 0xFFFF, sum = 0
3312 19:26:01.349208 11, 0xFFFF, sum = 0
3313 19:26:01.352843 12, 0x0, sum = 1
3314 19:26:01.352920 13, 0x0, sum = 2
3315 19:26:01.355979 14, 0x0, sum = 3
3316 19:26:01.356056 15, 0x0, sum = 4
3317 19:26:01.359433 best_step = 13
3318 19:26:01.359508
3319 19:26:01.359573 ==
3320 19:26:01.362419 Dram Type= 6, Freq= 0, CH_1, rank 0
3321 19:26:01.366105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3322 19:26:01.366183 ==
3323 19:26:01.366247 RX Vref Scan: 1
3324 19:26:01.369140
3325 19:26:01.369206 Set Vref Range= 32 -> 127
3326 19:26:01.369266
3327 19:26:01.372208 RX Vref 32 -> 127, step: 1
3328 19:26:01.372277
3329 19:26:01.375923 RX Delay -21 -> 252, step: 4
3330 19:26:01.375994
3331 19:26:01.379046 Set Vref, RX VrefLevel [Byte0]: 32
3332 19:26:01.381978 [Byte1]: 32
3333 19:26:01.382058
3334 19:26:01.385734 Set Vref, RX VrefLevel [Byte0]: 33
3335 19:26:01.388966 [Byte1]: 33
3336 19:26:01.392412
3337 19:26:01.392482 Set Vref, RX VrefLevel [Byte0]: 34
3338 19:26:01.396103 [Byte1]: 34
3339 19:26:01.400416
3340 19:26:01.400500 Set Vref, RX VrefLevel [Byte0]: 35
3341 19:26:01.403860 [Byte1]: 35
3342 19:26:01.408260
3343 19:26:01.408333 Set Vref, RX VrefLevel [Byte0]: 36
3344 19:26:01.411549 [Byte1]: 36
3345 19:26:01.416555
3346 19:26:01.416633 Set Vref, RX VrefLevel [Byte0]: 37
3347 19:26:01.419588 [Byte1]: 37
3348 19:26:01.424257
3349 19:26:01.424338 Set Vref, RX VrefLevel [Byte0]: 38
3350 19:26:01.427586 [Byte1]: 38
3351 19:26:01.432300
3352 19:26:01.432380 Set Vref, RX VrefLevel [Byte0]: 39
3353 19:26:01.435315 [Byte1]: 39
3354 19:26:01.440186
3355 19:26:01.440272 Set Vref, RX VrefLevel [Byte0]: 40
3356 19:26:01.443431 [Byte1]: 40
3357 19:26:01.448308
3358 19:26:01.448390 Set Vref, RX VrefLevel [Byte0]: 41
3359 19:26:01.451484 [Byte1]: 41
3360 19:26:01.455786
3361 19:26:01.455863 Set Vref, RX VrefLevel [Byte0]: 42
3362 19:26:01.459558 [Byte1]: 42
3363 19:26:01.463889
3364 19:26:01.463965 Set Vref, RX VrefLevel [Byte0]: 43
3365 19:26:01.467418 [Byte1]: 43
3366 19:26:01.471654
3367 19:26:01.471731 Set Vref, RX VrefLevel [Byte0]: 44
3368 19:26:01.475365 [Byte1]: 44
3369 19:26:01.480040
3370 19:26:01.480116 Set Vref, RX VrefLevel [Byte0]: 45
3371 19:26:01.483071 [Byte1]: 45
3372 19:26:01.487931
3373 19:26:01.488014 Set Vref, RX VrefLevel [Byte0]: 46
3374 19:26:01.491025 [Byte1]: 46
3375 19:26:01.495346
3376 19:26:01.495421 Set Vref, RX VrefLevel [Byte0]: 47
3377 19:26:01.498972 [Byte1]: 47
3378 19:26:01.503452
3379 19:26:01.503531 Set Vref, RX VrefLevel [Byte0]: 48
3380 19:26:01.506671 [Byte1]: 48
3381 19:26:01.511729
3382 19:26:01.511804 Set Vref, RX VrefLevel [Byte0]: 49
3383 19:26:01.514720 [Byte1]: 49
3384 19:26:01.519543
3385 19:26:01.519616 Set Vref, RX VrefLevel [Byte0]: 50
3386 19:26:01.522460 [Byte1]: 50
3387 19:26:01.527107
3388 19:26:01.527221 Set Vref, RX VrefLevel [Byte0]: 51
3389 19:26:01.530530 [Byte1]: 51
3390 19:26:01.535191
3391 19:26:01.535278 Set Vref, RX VrefLevel [Byte0]: 52
3392 19:26:01.538433 [Byte1]: 52
3393 19:26:01.543291
3394 19:26:01.546307 Set Vref, RX VrefLevel [Byte0]: 53
3395 19:26:01.549181 [Byte1]: 53
3396 19:26:01.549302
3397 19:26:01.552858 Set Vref, RX VrefLevel [Byte0]: 54
3398 19:26:01.556351 [Byte1]: 54
3399 19:26:01.556441
3400 19:26:01.559288 Set Vref, RX VrefLevel [Byte0]: 55
3401 19:26:01.562400 [Byte1]: 55
3402 19:26:01.566605
3403 19:26:01.566685 Set Vref, RX VrefLevel [Byte0]: 56
3404 19:26:01.570160 [Byte1]: 56
3405 19:26:01.575067
3406 19:26:01.575150 Set Vref, RX VrefLevel [Byte0]: 57
3407 19:26:01.578171 [Byte1]: 57
3408 19:26:01.582412
3409 19:26:01.582493 Set Vref, RX VrefLevel [Byte0]: 58
3410 19:26:01.586032 [Byte1]: 58
3411 19:26:01.590972
3412 19:26:01.591056 Set Vref, RX VrefLevel [Byte0]: 59
3413 19:26:01.593954 [Byte1]: 59
3414 19:26:01.598396
3415 19:26:01.598478 Set Vref, RX VrefLevel [Byte0]: 60
3416 19:26:01.601902 [Byte1]: 60
3417 19:26:01.606354
3418 19:26:01.606436 Set Vref, RX VrefLevel [Byte0]: 61
3419 19:26:01.609404 [Byte1]: 61
3420 19:26:01.614456
3421 19:26:01.614547 Set Vref, RX VrefLevel [Byte0]: 62
3422 19:26:01.617514 [Byte1]: 62
3423 19:26:01.622618
3424 19:26:01.622729 Set Vref, RX VrefLevel [Byte0]: 63
3425 19:26:01.625597 [Byte1]: 63
3426 19:26:01.630230
3427 19:26:01.630348 Set Vref, RX VrefLevel [Byte0]: 64
3428 19:26:01.633209 [Byte1]: 64
3429 19:26:01.637994
3430 19:26:01.638080 Set Vref, RX VrefLevel [Byte0]: 65
3431 19:26:01.641753 [Byte1]: 65
3432 19:26:01.645880
3433 19:26:01.645970 Set Vref, RX VrefLevel [Byte0]: 66
3434 19:26:01.649652 [Byte1]: 66
3435 19:26:01.653683
3436 19:26:01.653761 Set Vref, RX VrefLevel [Byte0]: 67
3437 19:26:01.657191 [Byte1]: 67
3438 19:26:01.661546
3439 19:26:01.661626 Set Vref, RX VrefLevel [Byte0]: 68
3440 19:26:01.664889 [Byte1]: 68
3441 19:26:01.669500
3442 19:26:01.669580 Set Vref, RX VrefLevel [Byte0]: 69
3443 19:26:01.672952 [Byte1]: 69
3444 19:26:01.677567
3445 19:26:01.677649 Final RX Vref Byte 0 = 48 to rank0
3446 19:26:01.680819 Final RX Vref Byte 1 = 53 to rank0
3447 19:26:01.684652 Final RX Vref Byte 0 = 48 to rank1
3448 19:26:01.688083 Final RX Vref Byte 1 = 53 to rank1==
3449 19:26:01.691082 Dram Type= 6, Freq= 0, CH_1, rank 0
3450 19:26:01.697759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3451 19:26:01.697844 ==
3452 19:26:01.697913 DQS Delay:
3453 19:26:01.697983 DQS0 = 0, DQS1 = 0
3454 19:26:01.701040 DQM Delay:
3455 19:26:01.701109 DQM0 = 115, DQM1 = 110
3456 19:26:01.704544 DQ Delay:
3457 19:26:01.707660 DQ0 =118, DQ1 =110, DQ2 =108, DQ3 =110
3458 19:26:01.710780 DQ4 =114, DQ5 =128, DQ6 =124, DQ7 =114
3459 19:26:01.713919 DQ8 =96, DQ9 =102, DQ10 =112, DQ11 =100
3460 19:26:01.717637 DQ12 =118, DQ13 =118, DQ14 =118, DQ15 =118
3461 19:26:01.717731
3462 19:26:01.717795
3463 19:26:01.727552 [DQSOSCAuto] RK0, (LSB)MR18= 0xfff3, (MSB)MR19= 0x303, tDQSOscB0 = 415 ps tDQSOscB1 = 410 ps
3464 19:26:01.727630 CH1 RK0: MR19=303, MR18=FFF3
3465 19:26:01.734003 CH1_RK0: MR19=0x303, MR18=0xFFF3, DQSOSC=410, MR23=63, INC=39, DEC=26
3466 19:26:01.734076
3467 19:26:01.737532 ----->DramcWriteLeveling(PI) begin...
3468 19:26:01.737603 ==
3469 19:26:01.740542 Dram Type= 6, Freq= 0, CH_1, rank 1
3470 19:26:01.747003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3471 19:26:01.747084 ==
3472 19:26:01.750031 Write leveling (Byte 0): 24 => 24
3473 19:26:01.753802 Write leveling (Byte 1): 28 => 28
3474 19:26:01.753873 DramcWriteLeveling(PI) end<-----
3475 19:26:01.756892
3476 19:26:01.756975 ==
3477 19:26:01.760089 Dram Type= 6, Freq= 0, CH_1, rank 1
3478 19:26:01.763778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3479 19:26:01.763861 ==
3480 19:26:01.766820 [Gating] SW mode calibration
3481 19:26:01.773554 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3482 19:26:01.780069 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3483 19:26:01.782970 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3484 19:26:01.786303 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3485 19:26:01.789525 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3486 19:26:01.796407 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3487 19:26:01.799696 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3488 19:26:01.803064 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3489 19:26:01.809534 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3490 19:26:01.813141 0 15 28 | B1->B0 | 2424 2828 | 0 0 | (1 0) (0 0)
3491 19:26:01.816212 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3492 19:26:01.823084 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3493 19:26:01.826208 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3494 19:26:01.829279 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3495 19:26:01.836197 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3496 19:26:01.839144 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3497 19:26:01.842841 1 0 24 | B1->B0 | 3434 2525 | 0 0 | (0 0) (0 0)
3498 19:26:01.848759 1 0 28 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
3499 19:26:01.852150 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3500 19:26:01.855647 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3501 19:26:01.862387 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3502 19:26:01.865440 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3503 19:26:01.872237 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3504 19:26:01.875546 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3505 19:26:01.878580 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3506 19:26:01.885190 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3507 19:26:01.888906 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3508 19:26:01.892027 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3509 19:26:01.898605 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3510 19:26:01.901714 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3511 19:26:01.905086 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3512 19:26:01.911628 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3513 19:26:01.915063 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3514 19:26:01.917824 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3515 19:26:01.924781 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3516 19:26:01.928025 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 19:26:01.931572 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 19:26:01.937721 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3519 19:26:01.941404 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3520 19:26:01.944494 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3521 19:26:01.950689 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3522 19:26:01.954315 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3523 19:26:01.957453 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3524 19:26:01.960658 Total UI for P1: 0, mck2ui 16
3525 19:26:01.964132 best dqsien dly found for B0: ( 1, 3, 28)
3526 19:26:01.967281 Total UI for P1: 0, mck2ui 16
3527 19:26:01.970560 best dqsien dly found for B1: ( 1, 3, 26)
3528 19:26:01.974261 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3529 19:26:01.977356 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3530 19:26:01.977447
3531 19:26:01.983901 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3532 19:26:01.986996 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3533 19:26:01.987073 [Gating] SW calibration Done
3534 19:26:01.990667 ==
3535 19:26:01.993723 Dram Type= 6, Freq= 0, CH_1, rank 1
3536 19:26:01.996815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3537 19:26:01.996916 ==
3538 19:26:01.997008 RX Vref Scan: 0
3539 19:26:01.997100
3540 19:26:02.000575 RX Vref 0 -> 0, step: 1
3541 19:26:02.000649
3542 19:26:02.003722 RX Delay -40 -> 252, step: 8
3543 19:26:02.006843 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3544 19:26:02.009990 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3545 19:26:02.017022 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3546 19:26:02.019853 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3547 19:26:02.023518 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3548 19:26:02.026481 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3549 19:26:02.029771 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3550 19:26:02.036509 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3551 19:26:02.039736 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3552 19:26:02.043162 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3553 19:26:02.046415 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3554 19:26:02.049539 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3555 19:26:02.056260 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3556 19:26:02.059400 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3557 19:26:02.062943 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3558 19:26:02.065830 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3559 19:26:02.065913 ==
3560 19:26:02.069133 Dram Type= 6, Freq= 0, CH_1, rank 1
3561 19:26:02.075822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3562 19:26:02.075908 ==
3563 19:26:02.075974 DQS Delay:
3564 19:26:02.078862 DQS0 = 0, DQS1 = 0
3565 19:26:02.078945 DQM Delay:
3566 19:26:02.082662 DQM0 = 115, DQM1 = 108
3567 19:26:02.082748 DQ Delay:
3568 19:26:02.085590 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3569 19:26:02.089414 DQ4 =115, DQ5 =123, DQ6 =127, DQ7 =115
3570 19:26:02.092462 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
3571 19:26:02.095478 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3572 19:26:02.095552
3573 19:26:02.095614
3574 19:26:02.095671 ==
3575 19:26:02.099210 Dram Type= 6, Freq= 0, CH_1, rank 1
3576 19:26:02.105721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3577 19:26:02.105798 ==
3578 19:26:02.105878
3579 19:26:02.105950
3580 19:26:02.106006 TX Vref Scan disable
3581 19:26:02.108796 == TX Byte 0 ==
3582 19:26:02.112030 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3583 19:26:02.115613 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3584 19:26:02.118599 == TX Byte 1 ==
3585 19:26:02.122048 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3586 19:26:02.128883 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3587 19:26:02.128966 ==
3588 19:26:02.131999 Dram Type= 6, Freq= 0, CH_1, rank 1
3589 19:26:02.135019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3590 19:26:02.135129 ==
3591 19:26:02.146442 TX Vref=22, minBit 9, minWin=25, winSum=425
3592 19:26:02.149793 TX Vref=24, minBit 8, minWin=25, winSum=426
3593 19:26:02.152993 TX Vref=26, minBit 9, minWin=26, winSum=433
3594 19:26:02.156451 TX Vref=28, minBit 9, minWin=26, winSum=434
3595 19:26:02.160061 TX Vref=30, minBit 9, minWin=25, winSum=437
3596 19:26:02.166359 TX Vref=32, minBit 8, minWin=26, winSum=434
3597 19:26:02.169360 [TxChooseVref] Worse bit 9, Min win 26, Win sum 434, Final Vref 28
3598 19:26:02.169452
3599 19:26:02.172995 Final TX Range 1 Vref 28
3600 19:26:02.173106
3601 19:26:02.173200 ==
3602 19:26:02.176109 Dram Type= 6, Freq= 0, CH_1, rank 1
3603 19:26:02.179771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3604 19:26:02.182449 ==
3605 19:26:02.182527
3606 19:26:02.182591
3607 19:26:02.182651 TX Vref Scan disable
3608 19:26:02.186533 == TX Byte 0 ==
3609 19:26:02.189617 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3610 19:26:02.196216 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3611 19:26:02.196310 == TX Byte 1 ==
3612 19:26:02.200094 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3613 19:26:02.205952 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3614 19:26:02.206074
3615 19:26:02.206143 [DATLAT]
3616 19:26:02.206205 Freq=1200, CH1 RK1
3617 19:26:02.206265
3618 19:26:02.209600 DATLAT Default: 0xd
3619 19:26:02.212674 0, 0xFFFF, sum = 0
3620 19:26:02.212828 1, 0xFFFF, sum = 0
3621 19:26:02.215982 2, 0xFFFF, sum = 0
3622 19:26:02.216084 3, 0xFFFF, sum = 0
3623 19:26:02.219602 4, 0xFFFF, sum = 0
3624 19:26:02.219727 5, 0xFFFF, sum = 0
3625 19:26:02.222700 6, 0xFFFF, sum = 0
3626 19:26:02.222789 7, 0xFFFF, sum = 0
3627 19:26:02.226213 8, 0xFFFF, sum = 0
3628 19:26:02.226312 9, 0xFFFF, sum = 0
3629 19:26:02.229226 10, 0xFFFF, sum = 0
3630 19:26:02.229376 11, 0xFFFF, sum = 0
3631 19:26:02.232622 12, 0x0, sum = 1
3632 19:26:02.232711 13, 0x0, sum = 2
3633 19:26:02.235844 14, 0x0, sum = 3
3634 19:26:02.235966 15, 0x0, sum = 4
3635 19:26:02.238996 best_step = 13
3636 19:26:02.239101
3637 19:26:02.239167 ==
3638 19:26:02.242810 Dram Type= 6, Freq= 0, CH_1, rank 1
3639 19:26:02.245790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3640 19:26:02.245879 ==
3641 19:26:02.249002 RX Vref Scan: 0
3642 19:26:02.249106
3643 19:26:02.249199 RX Vref 0 -> 0, step: 1
3644 19:26:02.249291
3645 19:26:02.252735 RX Delay -21 -> 252, step: 4
3646 19:26:02.258819 iDelay=199, Bit 0, Center 120 (55 ~ 186) 132
3647 19:26:02.262096 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3648 19:26:02.265686 iDelay=199, Bit 2, Center 106 (43 ~ 170) 128
3649 19:26:02.268678 iDelay=199, Bit 3, Center 112 (47 ~ 178) 132
3650 19:26:02.272004 iDelay=199, Bit 4, Center 114 (47 ~ 182) 136
3651 19:26:02.278488 iDelay=199, Bit 5, Center 128 (63 ~ 194) 132
3652 19:26:02.282141 iDelay=199, Bit 6, Center 130 (63 ~ 198) 136
3653 19:26:02.285325 iDelay=199, Bit 7, Center 114 (47 ~ 182) 136
3654 19:26:02.288324 iDelay=199, Bit 8, Center 96 (31 ~ 162) 132
3655 19:26:02.291730 iDelay=199, Bit 9, Center 98 (35 ~ 162) 128
3656 19:26:02.298276 iDelay=199, Bit 10, Center 110 (47 ~ 174) 128
3657 19:26:02.301702 iDelay=199, Bit 11, Center 98 (35 ~ 162) 128
3658 19:26:02.304854 iDelay=199, Bit 12, Center 118 (51 ~ 186) 136
3659 19:26:02.308047 iDelay=199, Bit 13, Center 116 (51 ~ 182) 132
3660 19:26:02.314623 iDelay=199, Bit 14, Center 116 (51 ~ 182) 132
3661 19:26:02.318234 iDelay=199, Bit 15, Center 118 (51 ~ 186) 136
3662 19:26:02.318313 ==
3663 19:26:02.321498 Dram Type= 6, Freq= 0, CH_1, rank 1
3664 19:26:02.324528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3665 19:26:02.324609 ==
3666 19:26:02.327759 DQS Delay:
3667 19:26:02.327865 DQS0 = 0, DQS1 = 0
3668 19:26:02.327958 DQM Delay:
3669 19:26:02.331263 DQM0 = 116, DQM1 = 108
3670 19:26:02.331398 DQ Delay:
3671 19:26:02.334645 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =112
3672 19:26:02.337701 DQ4 =114, DQ5 =128, DQ6 =130, DQ7 =114
3673 19:26:02.340700 DQ8 =96, DQ9 =98, DQ10 =110, DQ11 =98
3674 19:26:02.347704 DQ12 =118, DQ13 =116, DQ14 =116, DQ15 =118
3675 19:26:02.347813
3676 19:26:02.347906
3677 19:26:02.354052 [DQSOSCAuto] RK1, (LSB)MR18= 0xf2ed, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 415 ps
3678 19:26:02.357817 CH1 RK1: MR19=303, MR18=F2ED
3679 19:26:02.363840 CH1_RK1: MR19=0x303, MR18=0xF2ED, DQSOSC=415, MR23=63, INC=38, DEC=25
3680 19:26:02.367643 [RxdqsGatingPostProcess] freq 1200
3681 19:26:02.370753 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3682 19:26:02.373571 best DQS0 dly(2T, 0.5T) = (0, 11)
3683 19:26:02.377363 best DQS1 dly(2T, 0.5T) = (0, 11)
3684 19:26:02.380559 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3685 19:26:02.383612 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3686 19:26:02.387336 best DQS0 dly(2T, 0.5T) = (0, 11)
3687 19:26:02.390253 best DQS1 dly(2T, 0.5T) = (0, 11)
3688 19:26:02.393686 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3689 19:26:02.396837 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3690 19:26:02.400104 Pre-setting of DQS Precalculation
3691 19:26:02.406510 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3692 19:26:02.413198 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3693 19:26:02.419847 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3694 19:26:02.419927
3695 19:26:02.419991
3696 19:26:02.423023 [Calibration Summary] 2400 Mbps
3697 19:26:02.423098 CH 0, Rank 0
3698 19:26:02.426741 SW Impedance : PASS
3699 19:26:02.429901 DUTY Scan : NO K
3700 19:26:02.429983 ZQ Calibration : PASS
3701 19:26:02.433005 Jitter Meter : NO K
3702 19:26:02.436103 CBT Training : PASS
3703 19:26:02.436185 Write leveling : PASS
3704 19:26:02.439631 RX DQS gating : PASS
3705 19:26:02.442923 RX DQ/DQS(RDDQC) : PASS
3706 19:26:02.443000 TX DQ/DQS : PASS
3707 19:26:02.446502 RX DATLAT : PASS
3708 19:26:02.446580 RX DQ/DQS(Engine): PASS
3709 19:26:02.449589 TX OE : NO K
3710 19:26:02.449687 All Pass.
3711 19:26:02.449752
3712 19:26:02.452849 CH 0, Rank 1
3713 19:26:02.452945 SW Impedance : PASS
3714 19:26:02.456625 DUTY Scan : NO K
3715 19:26:02.459702 ZQ Calibration : PASS
3716 19:26:02.459789 Jitter Meter : NO K
3717 19:26:02.462746 CBT Training : PASS
3718 19:26:02.465745 Write leveling : PASS
3719 19:26:02.465841 RX DQS gating : PASS
3720 19:26:02.469496 RX DQ/DQS(RDDQC) : PASS
3721 19:26:02.472664 TX DQ/DQS : PASS
3722 19:26:02.472757 RX DATLAT : PASS
3723 19:26:02.475827 RX DQ/DQS(Engine): PASS
3724 19:26:02.478929 TX OE : NO K
3725 19:26:02.479004 All Pass.
3726 19:26:02.479076
3727 19:26:02.479138 CH 1, Rank 0
3728 19:26:02.482659 SW Impedance : PASS
3729 19:26:02.485658 DUTY Scan : NO K
3730 19:26:02.485729 ZQ Calibration : PASS
3731 19:26:02.489077 Jitter Meter : NO K
3732 19:26:02.492331 CBT Training : PASS
3733 19:26:02.492418 Write leveling : PASS
3734 19:26:02.495797 RX DQS gating : PASS
3735 19:26:02.498817 RX DQ/DQS(RDDQC) : PASS
3736 19:26:02.498899 TX DQ/DQS : PASS
3737 19:26:02.501908 RX DATLAT : PASS
3738 19:26:02.505182 RX DQ/DQS(Engine): PASS
3739 19:26:02.505264 TX OE : NO K
3740 19:26:02.508358 All Pass.
3741 19:26:02.508450
3742 19:26:02.508515 CH 1, Rank 1
3743 19:26:02.511762 SW Impedance : PASS
3744 19:26:02.511844 DUTY Scan : NO K
3745 19:26:02.515021 ZQ Calibration : PASS
3746 19:26:02.518277 Jitter Meter : NO K
3747 19:26:02.518361 CBT Training : PASS
3748 19:26:02.521948 Write leveling : PASS
3749 19:26:02.525228 RX DQS gating : PASS
3750 19:26:02.525340 RX DQ/DQS(RDDQC) : PASS
3751 19:26:02.528093 TX DQ/DQS : PASS
3752 19:26:02.531902 RX DATLAT : PASS
3753 19:26:02.531988 RX DQ/DQS(Engine): PASS
3754 19:26:02.535075 TX OE : NO K
3755 19:26:02.535153 All Pass.
3756 19:26:02.535217
3757 19:26:02.538293 DramC Write-DBI off
3758 19:26:02.542197 PER_BANK_REFRESH: Hybrid Mode
3759 19:26:02.542275 TX_TRACKING: ON
3760 19:26:02.551614 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3761 19:26:02.554472 [FAST_K] Save calibration result to emmc
3762 19:26:02.558037 dramc_set_vcore_voltage set vcore to 650000
3763 19:26:02.561347 Read voltage for 600, 5
3764 19:26:02.561437 Vio18 = 0
3765 19:26:02.561501 Vcore = 650000
3766 19:26:02.564360 Vdram = 0
3767 19:26:02.564430 Vddq = 0
3768 19:26:02.564490 Vmddr = 0
3769 19:26:02.571467 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3770 19:26:02.574568 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3771 19:26:02.577860 MEM_TYPE=3, freq_sel=19
3772 19:26:02.580792 sv_algorithm_assistance_LP4_1600
3773 19:26:02.584685 ============ PULL DRAM RESETB DOWN ============
3774 19:26:02.587670 ========== PULL DRAM RESETB DOWN end =========
3775 19:26:02.594421 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3776 19:26:02.597478 ===================================
3777 19:26:02.600859 LPDDR4 DRAM CONFIGURATION
3778 19:26:02.604132 ===================================
3779 19:26:02.604213 EX_ROW_EN[0] = 0x0
3780 19:26:02.607538 EX_ROW_EN[1] = 0x0
3781 19:26:02.607620 LP4Y_EN = 0x0
3782 19:26:02.610795 WORK_FSP = 0x0
3783 19:26:02.610911 WL = 0x2
3784 19:26:02.613994 RL = 0x2
3785 19:26:02.614090 BL = 0x2
3786 19:26:02.617241 RPST = 0x0
3787 19:26:02.617378 RD_PRE = 0x0
3788 19:26:02.620561 WR_PRE = 0x1
3789 19:26:02.620661 WR_PST = 0x0
3790 19:26:02.624354 DBI_WR = 0x0
3791 19:26:02.624427 DBI_RD = 0x0
3792 19:26:02.627491 OTF = 0x1
3793 19:26:02.630506 ===================================
3794 19:26:02.634282 ===================================
3795 19:26:02.634385 ANA top config
3796 19:26:02.637338 ===================================
3797 19:26:02.640536 DLL_ASYNC_EN = 0
3798 19:26:02.643743 ALL_SLAVE_EN = 1
3799 19:26:02.646881 NEW_RANK_MODE = 1
3800 19:26:02.650539 DLL_IDLE_MODE = 1
3801 19:26:02.650624 LP45_APHY_COMB_EN = 1
3802 19:26:02.653667 TX_ODT_DIS = 1
3803 19:26:02.657251 NEW_8X_MODE = 1
3804 19:26:02.660038 ===================================
3805 19:26:02.663392 ===================================
3806 19:26:02.666550 data_rate = 1200
3807 19:26:02.670254 CKR = 1
3808 19:26:02.673392 DQ_P2S_RATIO = 8
3809 19:26:02.673471 ===================================
3810 19:26:02.676606 CA_P2S_RATIO = 8
3811 19:26:02.679949 DQ_CA_OPEN = 0
3812 19:26:02.683471 DQ_SEMI_OPEN = 0
3813 19:26:02.686671 CA_SEMI_OPEN = 0
3814 19:26:02.690015 CA_FULL_RATE = 0
3815 19:26:02.693514 DQ_CKDIV4_EN = 1
3816 19:26:02.693602 CA_CKDIV4_EN = 1
3817 19:26:02.696674 CA_PREDIV_EN = 0
3818 19:26:02.699722 PH8_DLY = 0
3819 19:26:02.702826 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3820 19:26:02.706519 DQ_AAMCK_DIV = 4
3821 19:26:02.706603 CA_AAMCK_DIV = 4
3822 19:26:02.709630 CA_ADMCK_DIV = 4
3823 19:26:02.713281 DQ_TRACK_CA_EN = 0
3824 19:26:02.716427 CA_PICK = 600
3825 19:26:02.719388 CA_MCKIO = 600
3826 19:26:02.722966 MCKIO_SEMI = 0
3827 19:26:02.726061 PLL_FREQ = 2288
3828 19:26:02.729661 DQ_UI_PI_RATIO = 32
3829 19:26:02.729748 CA_UI_PI_RATIO = 0
3830 19:26:02.732925 ===================================
3831 19:26:02.736003 ===================================
3832 19:26:02.739870 memory_type:LPDDR4
3833 19:26:02.742814 GP_NUM : 10
3834 19:26:02.742896 SRAM_EN : 1
3835 19:26:02.745929 MD32_EN : 0
3836 19:26:02.749692 ===================================
3837 19:26:02.752820 [ANA_INIT] >>>>>>>>>>>>>>
3838 19:26:02.756180 <<<<<< [CONFIGURE PHASE]: ANA_TX
3839 19:26:02.759252 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3840 19:26:02.762594 ===================================
3841 19:26:02.762761 data_rate = 1200,PCW = 0X5800
3842 19:26:02.766023 ===================================
3843 19:26:02.768826 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3844 19:26:02.775621 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3845 19:26:02.782371 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3846 19:26:02.785455 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3847 19:26:02.788544 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3848 19:26:02.792089 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3849 19:26:02.795322 [ANA_INIT] flow start
3850 19:26:02.798512 [ANA_INIT] PLL >>>>>>>>
3851 19:26:02.798595 [ANA_INIT] PLL <<<<<<<<
3852 19:26:02.802141 [ANA_INIT] MIDPI >>>>>>>>
3853 19:26:02.805374 [ANA_INIT] MIDPI <<<<<<<<
3854 19:26:02.805452 [ANA_INIT] DLL >>>>>>>>
3855 19:26:02.808565 [ANA_INIT] flow end
3856 19:26:02.812067 ============ LP4 DIFF to SE enter ============
3857 19:26:02.818827 ============ LP4 DIFF to SE exit ============
3858 19:26:02.818909 [ANA_INIT] <<<<<<<<<<<<<
3859 19:26:02.821932 [Flow] Enable top DCM control >>>>>
3860 19:26:02.825049 [Flow] Enable top DCM control <<<<<
3861 19:26:02.828204 Enable DLL master slave shuffle
3862 19:26:02.835051 ==============================================================
3863 19:26:02.835129 Gating Mode config
3864 19:26:02.841402 ==============================================================
3865 19:26:02.845002 Config description:
3866 19:26:02.851295 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3867 19:26:02.861134 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3868 19:26:02.864915 SELPH_MODE 0: By rank 1: By Phase
3869 19:26:02.871058 ==============================================================
3870 19:26:02.874479 GAT_TRACK_EN = 1
3871 19:26:02.874558 RX_GATING_MODE = 2
3872 19:26:02.877926 RX_GATING_TRACK_MODE = 2
3873 19:26:02.880780 SELPH_MODE = 1
3874 19:26:02.884035 PICG_EARLY_EN = 1
3875 19:26:02.887541 VALID_LAT_VALUE = 1
3876 19:26:02.894101 ==============================================================
3877 19:26:02.897872 Enter into Gating configuration >>>>
3878 19:26:02.900987 Exit from Gating configuration <<<<
3879 19:26:02.903945 Enter into DVFS_PRE_config >>>>>
3880 19:26:02.913999 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3881 19:26:02.917208 Exit from DVFS_PRE_config <<<<<
3882 19:26:02.920674 Enter into PICG configuration >>>>
3883 19:26:02.923778 Exit from PICG configuration <<<<
3884 19:26:02.926965 [RX_INPUT] configuration >>>>>
3885 19:26:02.930593 [RX_INPUT] configuration <<<<<
3886 19:26:02.933782 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3887 19:26:02.940768 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3888 19:26:02.947073 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3889 19:26:02.953852 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3890 19:26:02.960148 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3891 19:26:02.963636 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3892 19:26:02.969907 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3893 19:26:02.973543 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3894 19:26:02.976612 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3895 19:26:02.980335 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3896 19:26:02.986650 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3897 19:26:02.989640 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3898 19:26:02.993260 ===================================
3899 19:26:02.996577 LPDDR4 DRAM CONFIGURATION
3900 19:26:02.999914 ===================================
3901 19:26:03.000017 EX_ROW_EN[0] = 0x0
3902 19:26:03.002950 EX_ROW_EN[1] = 0x0
3903 19:26:03.003053 LP4Y_EN = 0x0
3904 19:26:03.006154 WORK_FSP = 0x0
3905 19:26:03.006231 WL = 0x2
3906 19:26:03.009248 RL = 0x2
3907 19:26:03.009352 BL = 0x2
3908 19:26:03.012955 RPST = 0x0
3909 19:26:03.015989 RD_PRE = 0x0
3910 19:26:03.016068 WR_PRE = 0x1
3911 19:26:03.019750 WR_PST = 0x0
3912 19:26:03.019836 DBI_WR = 0x0
3913 19:26:03.022776 DBI_RD = 0x0
3914 19:26:03.022859 OTF = 0x1
3915 19:26:03.025746 ===================================
3916 19:26:03.029364 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3917 19:26:03.035730 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3918 19:26:03.039482 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3919 19:26:03.042622 ===================================
3920 19:26:03.045549 LPDDR4 DRAM CONFIGURATION
3921 19:26:03.049296 ===================================
3922 19:26:03.049387 EX_ROW_EN[0] = 0x10
3923 19:26:03.052359 EX_ROW_EN[1] = 0x0
3924 19:26:03.052432 LP4Y_EN = 0x0
3925 19:26:03.055833 WORK_FSP = 0x0
3926 19:26:03.055936 WL = 0x2
3927 19:26:03.059276 RL = 0x2
3928 19:26:03.062283 BL = 0x2
3929 19:26:03.062353 RPST = 0x0
3930 19:26:03.065898 RD_PRE = 0x0
3931 19:26:03.065976 WR_PRE = 0x1
3932 19:26:03.068695 WR_PST = 0x0
3933 19:26:03.068762 DBI_WR = 0x0
3934 19:26:03.072595 DBI_RD = 0x0
3935 19:26:03.072662 OTF = 0x1
3936 19:26:03.075293 ===================================
3937 19:26:03.081853 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3938 19:26:03.085970 nWR fixed to 30
3939 19:26:03.089118 [ModeRegInit_LP4] CH0 RK0
3940 19:26:03.089229 [ModeRegInit_LP4] CH0 RK1
3941 19:26:03.092988 [ModeRegInit_LP4] CH1 RK0
3942 19:26:03.095991 [ModeRegInit_LP4] CH1 RK1
3943 19:26:03.096075 match AC timing 17
3944 19:26:03.102622 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3945 19:26:03.105635 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3946 19:26:03.109030 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3947 19:26:03.115291 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3948 19:26:03.118769 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3949 19:26:03.118862 ==
3950 19:26:03.122297 Dram Type= 6, Freq= 0, CH_0, rank 0
3951 19:26:03.125251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3952 19:26:03.128732 ==
3953 19:26:03.131738 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3954 19:26:03.138789 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3955 19:26:03.142151 [CA 0] Center 36 (6~66) winsize 61
3956 19:26:03.145148 [CA 1] Center 36 (6~66) winsize 61
3957 19:26:03.148834 [CA 2] Center 34 (4~65) winsize 62
3958 19:26:03.151749 [CA 3] Center 34 (3~65) winsize 63
3959 19:26:03.154802 [CA 4] Center 33 (3~64) winsize 62
3960 19:26:03.158650 [CA 5] Center 33 (3~64) winsize 62
3961 19:26:03.158730
3962 19:26:03.161559 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3963 19:26:03.161627
3964 19:26:03.164841 [CATrainingPosCal] consider 1 rank data
3965 19:26:03.168411 u2DelayCellTimex100 = 270/100 ps
3966 19:26:03.171493 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3967 19:26:03.174880 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3968 19:26:03.181142 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3969 19:26:03.184480 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3970 19:26:03.188014 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3971 19:26:03.191154 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3972 19:26:03.191235
3973 19:26:03.194221 CA PerBit enable=1, Macro0, CA PI delay=33
3974 19:26:03.194294
3975 19:26:03.197400 [CBTSetCACLKResult] CA Dly = 33
3976 19:26:03.197472 CS Dly: 6 (0~37)
3977 19:26:03.201174 ==
3978 19:26:03.204289 Dram Type= 6, Freq= 0, CH_0, rank 1
3979 19:26:03.207362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3980 19:26:03.207436 ==
3981 19:26:03.214164 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3982 19:26:03.217102 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3983 19:26:03.221754 [CA 0] Center 35 (5~66) winsize 62
3984 19:26:03.224741 [CA 1] Center 36 (6~66) winsize 61
3985 19:26:03.227804 [CA 2] Center 33 (3~64) winsize 62
3986 19:26:03.231303 [CA 3] Center 33 (3~64) winsize 62
3987 19:26:03.234576 [CA 4] Center 33 (2~64) winsize 63
3988 19:26:03.237829 [CA 5] Center 33 (2~64) winsize 63
3989 19:26:03.237902
3990 19:26:03.241461 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3991 19:26:03.241556
3992 19:26:03.244435 [CATrainingPosCal] consider 2 rank data
3993 19:26:03.248080 u2DelayCellTimex100 = 270/100 ps
3994 19:26:03.251002 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3995 19:26:03.257728 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3996 19:26:03.261373 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
3997 19:26:03.264581 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3998 19:26:03.267627 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3999 19:26:03.271163 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4000 19:26:03.271239
4001 19:26:03.273837 CA PerBit enable=1, Macro0, CA PI delay=33
4002 19:26:03.273932
4003 19:26:03.277570 [CBTSetCACLKResult] CA Dly = 33
4004 19:26:03.280657 CS Dly: 5 (0~36)
4005 19:26:03.280725
4006 19:26:03.284142 ----->DramcWriteLeveling(PI) begin...
4007 19:26:03.284217 ==
4008 19:26:03.287340 Dram Type= 6, Freq= 0, CH_0, rank 0
4009 19:26:03.290827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4010 19:26:03.290901 ==
4011 19:26:03.293787 Write leveling (Byte 0): 31 => 31
4012 19:26:03.297276 Write leveling (Byte 1): 30 => 30
4013 19:26:03.300384 DramcWriteLeveling(PI) end<-----
4014 19:26:03.300485
4015 19:26:03.300617 ==
4016 19:26:03.304167 Dram Type= 6, Freq= 0, CH_0, rank 0
4017 19:26:03.307408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4018 19:26:03.307482 ==
4019 19:26:03.310367 [Gating] SW mode calibration
4020 19:26:03.317117 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4021 19:26:03.323340 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4022 19:26:03.326773 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4023 19:26:03.330207 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4024 19:26:03.336921 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4025 19:26:03.339981 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
4026 19:26:03.343187 0 9 16 | B1->B0 | 2e2e 2525 | 1 0 | (1 0) (1 0)
4027 19:26:03.349791 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4028 19:26:03.352968 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4029 19:26:03.356563 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4030 19:26:03.363261 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4031 19:26:03.366302 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4032 19:26:03.369485 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4033 19:26:03.376251 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4034 19:26:03.379297 0 10 16 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
4035 19:26:03.382494 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4036 19:26:03.389215 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4037 19:26:03.392262 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4038 19:26:03.399460 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4039 19:26:03.402190 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4040 19:26:03.405676 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4041 19:26:03.409450 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4042 19:26:03.415703 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4043 19:26:03.418822 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 19:26:03.425653 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 19:26:03.428967 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 19:26:03.431930 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 19:26:03.438436 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 19:26:03.441992 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 19:26:03.445226 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 19:26:03.452091 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 19:26:03.455252 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 19:26:03.458480 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 19:26:03.464830 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 19:26:03.468160 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 19:26:03.471590 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 19:26:03.478427 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 19:26:03.481602 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4058 19:26:03.484551 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4059 19:26:03.488037 Total UI for P1: 0, mck2ui 16
4060 19:26:03.491297 best dqsien dly found for B0: ( 0, 13, 12)
4061 19:26:03.494402 Total UI for P1: 0, mck2ui 16
4062 19:26:03.498129 best dqsien dly found for B1: ( 0, 13, 12)
4063 19:26:03.501205 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4064 19:26:03.504680 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4065 19:26:03.504762
4066 19:26:03.511264 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4067 19:26:03.514057 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4068 19:26:03.514137 [Gating] SW calibration Done
4069 19:26:03.517610 ==
4070 19:26:03.520875 Dram Type= 6, Freq= 0, CH_0, rank 0
4071 19:26:03.524125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4072 19:26:03.524211 ==
4073 19:26:03.524275 RX Vref Scan: 0
4074 19:26:03.524352
4075 19:26:03.527114 RX Vref 0 -> 0, step: 1
4076 19:26:03.527189
4077 19:26:03.531131 RX Delay -230 -> 252, step: 16
4078 19:26:03.533757 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4079 19:26:03.540447 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4080 19:26:03.543764 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4081 19:26:03.546815 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4082 19:26:03.550507 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4083 19:26:03.553580 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4084 19:26:03.560461 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4085 19:26:03.563438 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4086 19:26:03.566585 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4087 19:26:03.570247 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4088 19:26:03.576930 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4089 19:26:03.579856 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4090 19:26:03.583453 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4091 19:26:03.586463 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4092 19:26:03.593242 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4093 19:26:03.596758 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4094 19:26:03.596866 ==
4095 19:26:03.599953 Dram Type= 6, Freq= 0, CH_0, rank 0
4096 19:26:03.602916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4097 19:26:03.602994 ==
4098 19:26:03.606499 DQS Delay:
4099 19:26:03.606574 DQS0 = 0, DQS1 = 0
4100 19:26:03.606637 DQM Delay:
4101 19:26:03.609447 DQM0 = 43, DQM1 = 30
4102 19:26:03.609518 DQ Delay:
4103 19:26:03.612943 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4104 19:26:03.616377 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =49
4105 19:26:03.619406 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4106 19:26:03.622421 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4107 19:26:03.622502
4108 19:26:03.622567
4109 19:26:03.622634 ==
4110 19:26:03.625936 Dram Type= 6, Freq= 0, CH_0, rank 0
4111 19:26:03.632776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4112 19:26:03.632859 ==
4113 19:26:03.632924
4114 19:26:03.632989
4115 19:26:03.636022 TX Vref Scan disable
4116 19:26:03.636110 == TX Byte 0 ==
4117 19:26:03.639178 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4118 19:26:03.645987 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4119 19:26:03.646070 == TX Byte 1 ==
4120 19:26:03.652088 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4121 19:26:03.655622 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4122 19:26:03.655701 ==
4123 19:26:03.659330 Dram Type= 6, Freq= 0, CH_0, rank 0
4124 19:26:03.662342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4125 19:26:03.662414 ==
4126 19:26:03.662476
4127 19:26:03.662534
4128 19:26:03.665837 TX Vref Scan disable
4129 19:26:03.668942 == TX Byte 0 ==
4130 19:26:03.672082 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4131 19:26:03.675503 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4132 19:26:03.678464 == TX Byte 1 ==
4133 19:26:03.681888 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4134 19:26:03.685358 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4135 19:26:03.685440
4136 19:26:03.688656 [DATLAT]
4137 19:26:03.688829 Freq=600, CH0 RK0
4138 19:26:03.688953
4139 19:26:03.691851 DATLAT Default: 0x9
4140 19:26:03.691923 0, 0xFFFF, sum = 0
4141 19:26:03.694894 1, 0xFFFF, sum = 0
4142 19:26:03.694973 2, 0xFFFF, sum = 0
4143 19:26:03.698515 3, 0xFFFF, sum = 0
4144 19:26:03.698587 4, 0xFFFF, sum = 0
4145 19:26:03.701538 5, 0xFFFF, sum = 0
4146 19:26:03.701610 6, 0xFFFF, sum = 0
4147 19:26:03.704739 7, 0xFFFF, sum = 0
4148 19:26:03.704810 8, 0x0, sum = 1
4149 19:26:03.708128 9, 0x0, sum = 2
4150 19:26:03.708204 10, 0x0, sum = 3
4151 19:26:03.711653 11, 0x0, sum = 4
4152 19:26:03.711735 best_step = 9
4153 19:26:03.711796
4154 19:26:03.711854 ==
4155 19:26:03.714808 Dram Type= 6, Freq= 0, CH_0, rank 0
4156 19:26:03.721544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4157 19:26:03.721620 ==
4158 19:26:03.721682 RX Vref Scan: 1
4159 19:26:03.721748
4160 19:26:03.724909 RX Vref 0 -> 0, step: 1
4161 19:26:03.724989
4162 19:26:03.727911 RX Delay -195 -> 252, step: 8
4163 19:26:03.727988
4164 19:26:03.731391 Set Vref, RX VrefLevel [Byte0]: 57
4165 19:26:03.734456 [Byte1]: 48
4166 19:26:03.734531
4167 19:26:03.737592 Final RX Vref Byte 0 = 57 to rank0
4168 19:26:03.741261 Final RX Vref Byte 1 = 48 to rank0
4169 19:26:03.744459 Final RX Vref Byte 0 = 57 to rank1
4170 19:26:03.747639 Final RX Vref Byte 1 = 48 to rank1==
4171 19:26:03.750893 Dram Type= 6, Freq= 0, CH_0, rank 0
4172 19:26:03.754373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4173 19:26:03.754479 ==
4174 19:26:03.757538 DQS Delay:
4175 19:26:03.757612 DQS0 = 0, DQS1 = 0
4176 19:26:03.760964 DQM Delay:
4177 19:26:03.761035 DQM0 = 43, DQM1 = 32
4178 19:26:03.761094 DQ Delay:
4179 19:26:03.764461 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4180 19:26:03.767573 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =52
4181 19:26:03.771133 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =24
4182 19:26:03.774110 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =40
4183 19:26:03.774181
4184 19:26:03.774243
4185 19:26:03.784064 [DQSOSCAuto] RK0, (LSB)MR18= 0x5f38, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 391 ps
4186 19:26:03.787002 CH0 RK0: MR19=808, MR18=5F38
4187 19:26:03.793572 CH0_RK0: MR19=0x808, MR18=0x5F38, DQSOSC=391, MR23=63, INC=171, DEC=114
4188 19:26:03.793650
4189 19:26:03.796995 ----->DramcWriteLeveling(PI) begin...
4190 19:26:03.797104 ==
4191 19:26:03.800805 Dram Type= 6, Freq= 0, CH_0, rank 1
4192 19:26:03.803902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4193 19:26:03.804031 ==
4194 19:26:03.807042 Write leveling (Byte 0): 32 => 32
4195 19:26:03.810852 Write leveling (Byte 1): 31 => 31
4196 19:26:03.813806 DramcWriteLeveling(PI) end<-----
4197 19:26:03.813879
4198 19:26:03.813946 ==
4199 19:26:03.817190 Dram Type= 6, Freq= 0, CH_0, rank 1
4200 19:26:03.820646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4201 19:26:03.820733 ==
4202 19:26:03.823789 [Gating] SW mode calibration
4203 19:26:03.830460 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4204 19:26:03.836900 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4205 19:26:03.840367 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4206 19:26:03.843383 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4207 19:26:03.849946 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4208 19:26:03.853756 0 9 12 | B1->B0 | 3434 3232 | 1 0 | (0 1) (0 1)
4209 19:26:03.856951 0 9 16 | B1->B0 | 2f2f 2626 | 1 1 | (1 0) (1 0)
4210 19:26:03.863192 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4211 19:26:03.866911 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4212 19:26:03.870380 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4213 19:26:03.876835 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4214 19:26:03.880102 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4215 19:26:03.883069 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4216 19:26:03.889997 0 10 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4217 19:26:03.892898 0 10 16 | B1->B0 | 3b3b 3e3e | 1 0 | (0 0) (0 0)
4218 19:26:03.896019 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4219 19:26:03.902686 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4220 19:26:03.906101 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4221 19:26:03.909233 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4222 19:26:03.916089 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4223 19:26:03.919218 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4224 19:26:03.922848 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4225 19:26:03.929297 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4226 19:26:03.932431 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4227 19:26:03.935641 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4228 19:26:03.942264 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4229 19:26:03.945719 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4230 19:26:03.949133 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 19:26:03.955419 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4232 19:26:03.959045 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4233 19:26:03.962111 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4234 19:26:03.968981 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 19:26:03.971996 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 19:26:03.975620 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 19:26:03.981984 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 19:26:03.985134 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 19:26:03.988764 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 19:26:03.995502 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4241 19:26:03.998516 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4242 19:26:04.001640 Total UI for P1: 0, mck2ui 16
4243 19:26:04.005357 best dqsien dly found for B0: ( 0, 13, 12)
4244 19:26:04.008337 Total UI for P1: 0, mck2ui 16
4245 19:26:04.011815 best dqsien dly found for B1: ( 0, 13, 14)
4246 19:26:04.015189 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4247 19:26:04.018377 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4248 19:26:04.018480
4249 19:26:04.021344 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4250 19:26:04.028294 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4251 19:26:04.028407 [Gating] SW calibration Done
4252 19:26:04.028502 ==
4253 19:26:04.031936 Dram Type= 6, Freq= 0, CH_0, rank 1
4254 19:26:04.038200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4255 19:26:04.038281 ==
4256 19:26:04.038354 RX Vref Scan: 0
4257 19:26:04.038416
4258 19:26:04.041350 RX Vref 0 -> 0, step: 1
4259 19:26:04.041425
4260 19:26:04.045058 RX Delay -230 -> 252, step: 16
4261 19:26:04.048235 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4262 19:26:04.051277 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4263 19:26:04.058057 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4264 19:26:04.061347 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4265 19:26:04.064670 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4266 19:26:04.067604 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4267 19:26:04.071502 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4268 19:26:04.077830 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4269 19:26:04.080877 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4270 19:26:04.084495 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4271 19:26:04.087382 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4272 19:26:04.094271 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4273 19:26:04.097350 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4274 19:26:04.100869 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4275 19:26:04.103932 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4276 19:26:04.110924 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4277 19:26:04.111010 ==
4278 19:26:04.114063 Dram Type= 6, Freq= 0, CH_0, rank 1
4279 19:26:04.117180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4280 19:26:04.117297 ==
4281 19:26:04.117414 DQS Delay:
4282 19:26:04.120290 DQS0 = 0, DQS1 = 0
4283 19:26:04.120391 DQM Delay:
4284 19:26:04.123897 DQM0 = 41, DQM1 = 36
4285 19:26:04.124007 DQ Delay:
4286 19:26:04.126838 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =33
4287 19:26:04.130628 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4288 19:26:04.133805 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4289 19:26:04.136957 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =41
4290 19:26:04.137098
4291 19:26:04.137218
4292 19:26:04.137280 ==
4293 19:26:04.140399 Dram Type= 6, Freq= 0, CH_0, rank 1
4294 19:26:04.143605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4295 19:26:04.146657 ==
4296 19:26:04.146746
4297 19:26:04.146810
4298 19:26:04.146868 TX Vref Scan disable
4299 19:26:04.150409 == TX Byte 0 ==
4300 19:26:04.153582 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4301 19:26:04.160344 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4302 19:26:04.160423 == TX Byte 1 ==
4303 19:26:04.163439 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4304 19:26:04.169880 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4305 19:26:04.169964 ==
4306 19:26:04.173517 Dram Type= 6, Freq= 0, CH_0, rank 1
4307 19:26:04.176675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4308 19:26:04.176752 ==
4309 19:26:04.176823
4310 19:26:04.176883
4311 19:26:04.179640 TX Vref Scan disable
4312 19:26:04.183434 == TX Byte 0 ==
4313 19:26:04.186384 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4314 19:26:04.189578 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4315 19:26:04.193322 == TX Byte 1 ==
4316 19:26:04.196333 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4317 19:26:04.199863 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4318 19:26:04.199943
4319 19:26:04.200008 [DATLAT]
4320 19:26:04.202736 Freq=600, CH0 RK1
4321 19:26:04.202815
4322 19:26:04.206375 DATLAT Default: 0x9
4323 19:26:04.206459 0, 0xFFFF, sum = 0
4324 19:26:04.209458 1, 0xFFFF, sum = 0
4325 19:26:04.209534 2, 0xFFFF, sum = 0
4326 19:26:04.213144 3, 0xFFFF, sum = 0
4327 19:26:04.213225 4, 0xFFFF, sum = 0
4328 19:26:04.216283 5, 0xFFFF, sum = 0
4329 19:26:04.216358 6, 0xFFFF, sum = 0
4330 19:26:04.219449 7, 0xFFFF, sum = 0
4331 19:26:04.219562 8, 0x0, sum = 1
4332 19:26:04.223117 9, 0x0, sum = 2
4333 19:26:04.223231 10, 0x0, sum = 3
4334 19:26:04.226178 11, 0x0, sum = 4
4335 19:26:04.226282 best_step = 9
4336 19:26:04.226375
4337 19:26:04.226465 ==
4338 19:26:04.229231 Dram Type= 6, Freq= 0, CH_0, rank 1
4339 19:26:04.232599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4340 19:26:04.232703 ==
4341 19:26:04.236319 RX Vref Scan: 0
4342 19:26:04.236398
4343 19:26:04.239432 RX Vref 0 -> 0, step: 1
4344 19:26:04.239506
4345 19:26:04.239568 RX Delay -179 -> 252, step: 8
4346 19:26:04.246872 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4347 19:26:04.250124 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4348 19:26:04.253630 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4349 19:26:04.256788 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4350 19:26:04.263606 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4351 19:26:04.267229 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4352 19:26:04.270286 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4353 19:26:04.273463 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4354 19:26:04.280004 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4355 19:26:04.283635 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4356 19:26:04.286465 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4357 19:26:04.290000 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4358 19:26:04.293648 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4359 19:26:04.299896 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4360 19:26:04.303041 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4361 19:26:04.306681 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4362 19:26:04.306757 ==
4363 19:26:04.309650 Dram Type= 6, Freq= 0, CH_0, rank 1
4364 19:26:04.316046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4365 19:26:04.316124 ==
4366 19:26:04.316188 DQS Delay:
4367 19:26:04.319788 DQS0 = 0, DQS1 = 0
4368 19:26:04.319855 DQM Delay:
4369 19:26:04.319914 DQM0 = 42, DQM1 = 36
4370 19:26:04.323122 DQ Delay:
4371 19:26:04.326031 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4372 19:26:04.329122 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4373 19:26:04.332342 DQ8 =28, DQ9 =20, DQ10 =40, DQ11 =28
4374 19:26:04.336167 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =44
4375 19:26:04.336266
4376 19:26:04.336361
4377 19:26:04.342409 [DQSOSCAuto] RK1, (LSB)MR18= 0x5a0e, (MSB)MR19= 0x808, tDQSOscB0 = 407 ps tDQSOscB1 = 392 ps
4378 19:26:04.345626 CH0 RK1: MR19=808, MR18=5A0E
4379 19:26:04.352525 CH0_RK1: MR19=0x808, MR18=0x5A0E, DQSOSC=392, MR23=63, INC=170, DEC=113
4380 19:26:04.355612 [RxdqsGatingPostProcess] freq 600
4381 19:26:04.362492 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4382 19:26:04.362573 Pre-setting of DQS Precalculation
4383 19:26:04.368597 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4384 19:26:04.368676 ==
4385 19:26:04.372210 Dram Type= 6, Freq= 0, CH_1, rank 0
4386 19:26:04.375431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4387 19:26:04.375535 ==
4388 19:26:04.381945 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4389 19:26:04.388142 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4390 19:26:04.391812 [CA 0] Center 35 (5~66) winsize 62
4391 19:26:04.395307 [CA 1] Center 35 (5~66) winsize 62
4392 19:26:04.398209 [CA 2] Center 34 (4~65) winsize 62
4393 19:26:04.401912 [CA 3] Center 33 (3~64) winsize 62
4394 19:26:04.404988 [CA 4] Center 34 (4~65) winsize 62
4395 19:26:04.408120 [CA 5] Center 33 (3~64) winsize 62
4396 19:26:04.408205
4397 19:26:04.411740 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4398 19:26:04.411845
4399 19:26:04.414899 [CATrainingPosCal] consider 1 rank data
4400 19:26:04.417812 u2DelayCellTimex100 = 270/100 ps
4401 19:26:04.421047 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4402 19:26:04.424408 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4403 19:26:04.428115 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4404 19:26:04.431207 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4405 19:26:04.437476 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4406 19:26:04.440687 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4407 19:26:04.440756
4408 19:26:04.444313 CA PerBit enable=1, Macro0, CA PI delay=33
4409 19:26:04.444397
4410 19:26:04.447843 [CBTSetCACLKResult] CA Dly = 33
4411 19:26:04.447915 CS Dly: 5 (0~36)
4412 19:26:04.447977 ==
4413 19:26:04.450884 Dram Type= 6, Freq= 0, CH_1, rank 1
4414 19:26:04.457676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4415 19:26:04.457784 ==
4416 19:26:04.460834 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4417 19:26:04.467435 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4418 19:26:04.470819 [CA 0] Center 35 (5~66) winsize 62
4419 19:26:04.474287 [CA 1] Center 36 (6~66) winsize 61
4420 19:26:04.477252 [CA 2] Center 34 (4~65) winsize 62
4421 19:26:04.480357 [CA 3] Center 34 (4~65) winsize 62
4422 19:26:04.484145 [CA 4] Center 34 (4~65) winsize 62
4423 19:26:04.487151 [CA 5] Center 34 (3~65) winsize 63
4424 19:26:04.487255
4425 19:26:04.490130 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4426 19:26:04.490208
4427 19:26:04.493809 [CATrainingPosCal] consider 2 rank data
4428 19:26:04.496983 u2DelayCellTimex100 = 270/100 ps
4429 19:26:04.500463 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4430 19:26:04.506860 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4431 19:26:04.510071 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4432 19:26:04.513314 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4433 19:26:04.516448 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4434 19:26:04.520335 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4435 19:26:04.520436
4436 19:26:04.523301 CA PerBit enable=1, Macro0, CA PI delay=33
4437 19:26:04.523408
4438 19:26:04.526503 [CBTSetCACLKResult] CA Dly = 33
4439 19:26:04.529982 CS Dly: 5 (0~36)
4440 19:26:04.530090
4441 19:26:04.533235 ----->DramcWriteLeveling(PI) begin...
4442 19:26:04.533347 ==
4443 19:26:04.536466 Dram Type= 6, Freq= 0, CH_1, rank 0
4444 19:26:04.539862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4445 19:26:04.539968 ==
4446 19:26:04.542951 Write leveling (Byte 0): 29 => 29
4447 19:26:04.546708 Write leveling (Byte 1): 31 => 31
4448 19:26:04.549761 DramcWriteLeveling(PI) end<-----
4449 19:26:04.549836
4450 19:26:04.549899 ==
4451 19:26:04.552897 Dram Type= 6, Freq= 0, CH_1, rank 0
4452 19:26:04.556217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4453 19:26:04.556329 ==
4454 19:26:04.559581 [Gating] SW mode calibration
4455 19:26:04.566527 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4456 19:26:04.572602 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4457 19:26:04.576115 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4458 19:26:04.579443 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4459 19:26:04.586004 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4460 19:26:04.589000 0 9 12 | B1->B0 | 3333 2f2f | 1 1 | (1 1) (1 0)
4461 19:26:04.592610 0 9 16 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
4462 19:26:04.598772 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4463 19:26:04.602485 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4464 19:26:04.608640 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4465 19:26:04.612062 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4466 19:26:04.615095 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4467 19:26:04.622027 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4468 19:26:04.625151 0 10 12 | B1->B0 | 2d2d 3636 | 0 0 | (0 0) (0 0)
4469 19:26:04.628790 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4470 19:26:04.635149 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4471 19:26:04.638263 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4472 19:26:04.641776 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4473 19:26:04.648341 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4474 19:26:04.651981 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4475 19:26:04.654916 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4476 19:26:04.661503 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4477 19:26:04.664776 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 19:26:04.668192 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 19:26:04.674320 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 19:26:04.677987 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 19:26:04.681197 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 19:26:04.687414 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 19:26:04.690854 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 19:26:04.694649 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 19:26:04.700670 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 19:26:04.704275 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 19:26:04.707410 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 19:26:04.714271 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 19:26:04.717244 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 19:26:04.720782 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 19:26:04.727528 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 19:26:04.730604 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4493 19:26:04.733694 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4494 19:26:04.736755 Total UI for P1: 0, mck2ui 16
4495 19:26:04.740569 best dqsien dly found for B0: ( 0, 13, 12)
4496 19:26:04.743582 Total UI for P1: 0, mck2ui 16
4497 19:26:04.746864 best dqsien dly found for B1: ( 0, 13, 12)
4498 19:26:04.750667 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4499 19:26:04.753780 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4500 19:26:04.753856
4501 19:26:04.760176 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4502 19:26:04.763603 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4503 19:26:04.766665 [Gating] SW calibration Done
4504 19:26:04.766740 ==
4505 19:26:04.769880 Dram Type= 6, Freq= 0, CH_1, rank 0
4506 19:26:04.773249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4507 19:26:04.773353 ==
4508 19:26:04.773418 RX Vref Scan: 0
4509 19:26:04.773478
4510 19:26:04.776820 RX Vref 0 -> 0, step: 1
4511 19:26:04.776903
4512 19:26:04.779854 RX Delay -230 -> 252, step: 16
4513 19:26:04.783626 iDelay=218, Bit 0, Center 65 (-86 ~ 217) 304
4514 19:26:04.786833 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4515 19:26:04.793127 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4516 19:26:04.796536 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4517 19:26:04.800115 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4518 19:26:04.803080 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4519 19:26:04.809591 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4520 19:26:04.813206 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4521 19:26:04.816248 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4522 19:26:04.819611 iDelay=218, Bit 9, Center 33 (-134 ~ 201) 336
4523 19:26:04.823109 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4524 19:26:04.829207 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4525 19:26:04.832406 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4526 19:26:04.836185 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4527 19:26:04.842977 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4528 19:26:04.846016 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4529 19:26:04.846101 ==
4530 19:26:04.849224 Dram Type= 6, Freq= 0, CH_1, rank 0
4531 19:26:04.852354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4532 19:26:04.852466 ==
4533 19:26:04.855536 DQS Delay:
4534 19:26:04.855647 DQS0 = 0, DQS1 = 0
4535 19:26:04.855747 DQM Delay:
4536 19:26:04.858692 DQM0 = 49, DQM1 = 39
4537 19:26:04.858776 DQ Delay:
4538 19:26:04.862430 DQ0 =65, DQ1 =41, DQ2 =33, DQ3 =41
4539 19:26:04.865513 DQ4 =41, DQ5 =65, DQ6 =65, DQ7 =41
4540 19:26:04.869007 DQ8 =25, DQ9 =33, DQ10 =33, DQ11 =25
4541 19:26:04.872332 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4542 19:26:04.872438
4543 19:26:04.872533
4544 19:26:04.872631 ==
4545 19:26:04.875741 Dram Type= 6, Freq= 0, CH_1, rank 0
4546 19:26:04.882411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4547 19:26:04.882496 ==
4548 19:26:04.882561
4549 19:26:04.882621
4550 19:26:04.882678 TX Vref Scan disable
4551 19:26:04.885631 == TX Byte 0 ==
4552 19:26:04.889175 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4553 19:26:04.895487 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4554 19:26:04.895571 == TX Byte 1 ==
4555 19:26:04.899165 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4556 19:26:04.905241 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4557 19:26:04.905322 ==
4558 19:26:04.908727 Dram Type= 6, Freq= 0, CH_1, rank 0
4559 19:26:04.911731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4560 19:26:04.911805 ==
4561 19:26:04.911875
4562 19:26:04.911934
4563 19:26:04.915119 TX Vref Scan disable
4564 19:26:04.918526 == TX Byte 0 ==
4565 19:26:04.921967 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4566 19:26:04.925085 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4567 19:26:04.928098 == TX Byte 1 ==
4568 19:26:04.931746 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4569 19:26:04.935436 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4570 19:26:04.935524
4571 19:26:04.938377 [DATLAT]
4572 19:26:04.938456 Freq=600, CH1 RK0
4573 19:26:04.938520
4574 19:26:04.941538 DATLAT Default: 0x9
4575 19:26:04.941610 0, 0xFFFF, sum = 0
4576 19:26:04.945411 1, 0xFFFF, sum = 0
4577 19:26:04.945502 2, 0xFFFF, sum = 0
4578 19:26:04.948543 3, 0xFFFF, sum = 0
4579 19:26:04.948630 4, 0xFFFF, sum = 0
4580 19:26:04.951746 5, 0xFFFF, sum = 0
4581 19:26:04.951826 6, 0xFFFF, sum = 0
4582 19:26:04.954610 7, 0xFFFF, sum = 0
4583 19:26:04.954689 8, 0x0, sum = 1
4584 19:26:04.958371 9, 0x0, sum = 2
4585 19:26:04.958451 10, 0x0, sum = 3
4586 19:26:04.961326 11, 0x0, sum = 4
4587 19:26:04.961413 best_step = 9
4588 19:26:04.961485
4589 19:26:04.961546 ==
4590 19:26:04.964569 Dram Type= 6, Freq= 0, CH_1, rank 0
4591 19:26:04.968462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4592 19:26:04.968541 ==
4593 19:26:04.971430 RX Vref Scan: 1
4594 19:26:04.971503
4595 19:26:04.974574 RX Vref 0 -> 0, step: 1
4596 19:26:04.974648
4597 19:26:04.977618 RX Delay -179 -> 252, step: 8
4598 19:26:04.977698
4599 19:26:04.981145 Set Vref, RX VrefLevel [Byte0]: 48
4600 19:26:04.981267 [Byte1]: 53
4601 19:26:04.986113
4602 19:26:04.986226 Final RX Vref Byte 0 = 48 to rank0
4603 19:26:04.989662 Final RX Vref Byte 1 = 53 to rank0
4604 19:26:04.992584 Final RX Vref Byte 0 = 48 to rank1
4605 19:26:04.996490 Final RX Vref Byte 1 = 53 to rank1==
4606 19:26:04.999633 Dram Type= 6, Freq= 0, CH_1, rank 0
4607 19:26:05.005866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4608 19:26:05.005948 ==
4609 19:26:05.006015 DQS Delay:
4610 19:26:05.009295 DQS0 = 0, DQS1 = 0
4611 19:26:05.009393 DQM Delay:
4612 19:26:05.009457 DQM0 = 47, DQM1 = 37
4613 19:26:05.012365 DQ Delay:
4614 19:26:05.015857 DQ0 =56, DQ1 =40, DQ2 =36, DQ3 =44
4615 19:26:05.019477 DQ4 =44, DQ5 =60, DQ6 =56, DQ7 =44
4616 19:26:05.022259 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4617 19:26:05.025451 DQ12 =48, DQ13 =40, DQ14 =48, DQ15 =48
4618 19:26:05.025529
4619 19:26:05.025602
4620 19:26:05.032287 [DQSOSCAuto] RK0, (LSB)MR18= 0x482d, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
4621 19:26:05.035278 CH1 RK0: MR19=808, MR18=482D
4622 19:26:05.042008 CH1_RK0: MR19=0x808, MR18=0x482D, DQSOSC=396, MR23=63, INC=167, DEC=111
4623 19:26:05.042100
4624 19:26:05.045811 ----->DramcWriteLeveling(PI) begin...
4625 19:26:05.045897 ==
4626 19:26:05.048857 Dram Type= 6, Freq= 0, CH_1, rank 1
4627 19:26:05.051905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4628 19:26:05.051987 ==
4629 19:26:05.055168 Write leveling (Byte 0): 29 => 29
4630 19:26:05.058902 Write leveling (Byte 1): 30 => 30
4631 19:26:05.061942 DramcWriteLeveling(PI) end<-----
4632 19:26:05.062021
4633 19:26:05.062086 ==
4634 19:26:05.065131 Dram Type= 6, Freq= 0, CH_1, rank 1
4635 19:26:05.068258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4636 19:26:05.072146 ==
4637 19:26:05.072224 [Gating] SW mode calibration
4638 19:26:05.081573 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4639 19:26:05.085322 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4640 19:26:05.088323 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4641 19:26:05.094566 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4642 19:26:05.097997 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4643 19:26:05.101646 0 9 12 | B1->B0 | 2f2f 3333 | 1 1 | (0 0) (1 1)
4644 19:26:05.107775 0 9 16 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
4645 19:26:05.111509 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4646 19:26:05.114559 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4647 19:26:05.121662 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4648 19:26:05.124419 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4649 19:26:05.128089 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4650 19:26:05.134649 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4651 19:26:05.137857 0 10 12 | B1->B0 | 3131 2525 | 0 0 | (0 0) (0 0)
4652 19:26:05.141052 0 10 16 | B1->B0 | 4646 3e3e | 0 0 | (0 0) (0 0)
4653 19:26:05.147488 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4654 19:26:05.151087 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4655 19:26:05.154149 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4656 19:26:05.161078 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4657 19:26:05.164526 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4658 19:26:05.167506 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4659 19:26:05.174245 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4660 19:26:05.177444 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4661 19:26:05.180400 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4662 19:26:05.187476 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4663 19:26:05.190540 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4664 19:26:05.193640 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 19:26:05.200436 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4666 19:26:05.203377 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4667 19:26:05.207074 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4668 19:26:05.213360 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4669 19:26:05.217068 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4670 19:26:05.220056 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 19:26:05.226887 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 19:26:05.230468 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 19:26:05.233314 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 19:26:05.240173 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 19:26:05.243333 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4676 19:26:05.246650 Total UI for P1: 0, mck2ui 16
4677 19:26:05.249916 best dqsien dly found for B1: ( 0, 13, 10)
4678 19:26:05.253176 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4679 19:26:05.256566 Total UI for P1: 0, mck2ui 16
4680 19:26:05.259826 best dqsien dly found for B0: ( 0, 13, 14)
4681 19:26:05.263349 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4682 19:26:05.269581 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4683 19:26:05.269660
4684 19:26:05.272610 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4685 19:26:05.276481 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4686 19:26:05.279547 [Gating] SW calibration Done
4687 19:26:05.279648 ==
4688 19:26:05.282625 Dram Type= 6, Freq= 0, CH_1, rank 1
4689 19:26:05.286316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4690 19:26:05.286394 ==
4691 19:26:05.289464 RX Vref Scan: 0
4692 19:26:05.289572
4693 19:26:05.289667 RX Vref 0 -> 0, step: 1
4694 19:26:05.289736
4695 19:26:05.292706 RX Delay -230 -> 252, step: 16
4696 19:26:05.295768 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4697 19:26:05.302772 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4698 19:26:05.305637 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4699 19:26:05.309264 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4700 19:26:05.312368 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4701 19:26:05.319197 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4702 19:26:05.322403 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4703 19:26:05.325570 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4704 19:26:05.328761 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4705 19:26:05.332034 iDelay=218, Bit 9, Center 33 (-134 ~ 201) 336
4706 19:26:05.338862 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4707 19:26:05.341740 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4708 19:26:05.345100 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4709 19:26:05.351864 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4710 19:26:05.355431 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4711 19:26:05.358335 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4712 19:26:05.358451 ==
4713 19:26:05.361847 Dram Type= 6, Freq= 0, CH_1, rank 1
4714 19:26:05.365325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4715 19:26:05.365420 ==
4716 19:26:05.368138 DQS Delay:
4717 19:26:05.368235 DQS0 = 0, DQS1 = 0
4718 19:26:05.371394 DQM Delay:
4719 19:26:05.371465 DQM0 = 44, DQM1 = 39
4720 19:26:05.371526 DQ Delay:
4721 19:26:05.375236 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4722 19:26:05.378371 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4723 19:26:05.381441 DQ8 =17, DQ9 =33, DQ10 =41, DQ11 =25
4724 19:26:05.385126 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4725 19:26:05.385235
4726 19:26:05.385300
4727 19:26:05.388225 ==
4728 19:26:05.391363 Dram Type= 6, Freq= 0, CH_1, rank 1
4729 19:26:05.394621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4730 19:26:05.394694 ==
4731 19:26:05.394796
4732 19:26:05.394854
4733 19:26:05.398316 TX Vref Scan disable
4734 19:26:05.398387 == TX Byte 0 ==
4735 19:26:05.404675 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4736 19:26:05.408148 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4737 19:26:05.408246 == TX Byte 1 ==
4738 19:26:05.414690 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4739 19:26:05.417681 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4740 19:26:05.417767 ==
4741 19:26:05.421304 Dram Type= 6, Freq= 0, CH_1, rank 1
4742 19:26:05.424617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4743 19:26:05.424699 ==
4744 19:26:05.424764
4745 19:26:05.424860
4746 19:26:05.427699 TX Vref Scan disable
4747 19:26:05.430927 == TX Byte 0 ==
4748 19:26:05.434373 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4749 19:26:05.437758 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4750 19:26:05.440661 == TX Byte 1 ==
4751 19:26:05.443904 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4752 19:26:05.450980 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4753 19:26:05.451090
4754 19:26:05.451186 [DATLAT]
4755 19:26:05.451278 Freq=600, CH1 RK1
4756 19:26:05.451403
4757 19:26:05.454272 DATLAT Default: 0x9
4758 19:26:05.454446 0, 0xFFFF, sum = 0
4759 19:26:05.457155 1, 0xFFFF, sum = 0
4760 19:26:05.460462 2, 0xFFFF, sum = 0
4761 19:26:05.460568 3, 0xFFFF, sum = 0
4762 19:26:05.464070 4, 0xFFFF, sum = 0
4763 19:26:05.464177 5, 0xFFFF, sum = 0
4764 19:26:05.467076 6, 0xFFFF, sum = 0
4765 19:26:05.467183 7, 0xFFFF, sum = 0
4766 19:26:05.470269 8, 0x0, sum = 1
4767 19:26:05.470343 9, 0x0, sum = 2
4768 19:26:05.473779 10, 0x0, sum = 3
4769 19:26:05.473854 11, 0x0, sum = 4
4770 19:26:05.473917 best_step = 9
4771 19:26:05.473977
4772 19:26:05.477086 ==
4773 19:26:05.477163 Dram Type= 6, Freq= 0, CH_1, rank 1
4774 19:26:05.483536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4775 19:26:05.483624 ==
4776 19:26:05.483692 RX Vref Scan: 0
4777 19:26:05.483755
4778 19:26:05.486639 RX Vref 0 -> 0, step: 1
4779 19:26:05.486724
4780 19:26:05.489851 RX Delay -195 -> 252, step: 8
4781 19:26:05.496784 iDelay=213, Bit 0, Center 48 (-99 ~ 196) 296
4782 19:26:05.499713 iDelay=213, Bit 1, Center 40 (-107 ~ 188) 296
4783 19:26:05.503344 iDelay=213, Bit 2, Center 32 (-115 ~ 180) 296
4784 19:26:05.506452 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4785 19:26:05.510168 iDelay=213, Bit 4, Center 44 (-107 ~ 196) 304
4786 19:26:05.516345 iDelay=213, Bit 5, Center 56 (-91 ~ 204) 296
4787 19:26:05.519479 iDelay=213, Bit 6, Center 60 (-91 ~ 212) 304
4788 19:26:05.523180 iDelay=213, Bit 7, Center 44 (-107 ~ 196) 304
4789 19:26:05.526480 iDelay=213, Bit 8, Center 24 (-131 ~ 180) 312
4790 19:26:05.532918 iDelay=213, Bit 9, Center 24 (-131 ~ 180) 312
4791 19:26:05.535948 iDelay=213, Bit 10, Center 36 (-115 ~ 188) 304
4792 19:26:05.539801 iDelay=213, Bit 11, Center 28 (-123 ~ 180) 304
4793 19:26:05.542537 iDelay=213, Bit 12, Center 48 (-107 ~ 204) 312
4794 19:26:05.549127 iDelay=213, Bit 13, Center 44 (-107 ~ 196) 304
4795 19:26:05.552913 iDelay=213, Bit 14, Center 44 (-107 ~ 196) 304
4796 19:26:05.555811 iDelay=213, Bit 15, Center 48 (-107 ~ 204) 312
4797 19:26:05.555897 ==
4798 19:26:05.559472 Dram Type= 6, Freq= 0, CH_1, rank 1
4799 19:26:05.562685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4800 19:26:05.565668 ==
4801 19:26:05.565751 DQS Delay:
4802 19:26:05.565818 DQS0 = 0, DQS1 = 0
4803 19:26:05.568816 DQM Delay:
4804 19:26:05.568898 DQM0 = 45, DQM1 = 37
4805 19:26:05.572394 DQ Delay:
4806 19:26:05.575506 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4807 19:26:05.575589 DQ4 =44, DQ5 =56, DQ6 =60, DQ7 =44
4808 19:26:05.578856 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =28
4809 19:26:05.585271 DQ12 =48, DQ13 =44, DQ14 =44, DQ15 =48
4810 19:26:05.585422
4811 19:26:05.585520
4812 19:26:05.592138 [DQSOSCAuto] RK1, (LSB)MR18= 0x261b, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 402 ps
4813 19:26:05.595187 CH1 RK1: MR19=808, MR18=261B
4814 19:26:05.601569 CH1_RK1: MR19=0x808, MR18=0x261B, DQSOSC=402, MR23=63, INC=162, DEC=108
4815 19:26:05.605054 [RxdqsGatingPostProcess] freq 600
4816 19:26:05.608166 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4817 19:26:05.611315 Pre-setting of DQS Precalculation
4818 19:26:05.618176 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4819 19:26:05.624928 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4820 19:26:05.631112 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4821 19:26:05.631196
4822 19:26:05.631263
4823 19:26:05.634221 [Calibration Summary] 1200 Mbps
4824 19:26:05.637479 CH 0, Rank 0
4825 19:26:05.637562 SW Impedance : PASS
4826 19:26:05.641020 DUTY Scan : NO K
4827 19:26:05.644060 ZQ Calibration : PASS
4828 19:26:05.644144 Jitter Meter : NO K
4829 19:26:05.647589 CBT Training : PASS
4830 19:26:05.650723 Write leveling : PASS
4831 19:26:05.650806 RX DQS gating : PASS
4832 19:26:05.654303 RX DQ/DQS(RDDQC) : PASS
4833 19:26:05.654389 TX DQ/DQS : PASS
4834 19:26:05.657664 RX DATLAT : PASS
4835 19:26:05.660882 RX DQ/DQS(Engine): PASS
4836 19:26:05.660965 TX OE : NO K
4837 19:26:05.663876 All Pass.
4838 19:26:05.663959
4839 19:26:05.664025 CH 0, Rank 1
4840 19:26:05.667472 SW Impedance : PASS
4841 19:26:05.667555 DUTY Scan : NO K
4842 19:26:05.670627 ZQ Calibration : PASS
4843 19:26:05.673708 Jitter Meter : NO K
4844 19:26:05.673823 CBT Training : PASS
4845 19:26:05.677265 Write leveling : PASS
4846 19:26:05.680790 RX DQS gating : PASS
4847 19:26:05.680873 RX DQ/DQS(RDDQC) : PASS
4848 19:26:05.683578 TX DQ/DQS : PASS
4849 19:26:05.686906 RX DATLAT : PASS
4850 19:26:05.687012 RX DQ/DQS(Engine): PASS
4851 19:26:05.690401 TX OE : NO K
4852 19:26:05.690535 All Pass.
4853 19:26:05.690597
4854 19:26:05.693594 CH 1, Rank 0
4855 19:26:05.693708 SW Impedance : PASS
4856 19:26:05.697087 DUTY Scan : NO K
4857 19:26:05.700373 ZQ Calibration : PASS
4858 19:26:05.700461 Jitter Meter : NO K
4859 19:26:05.703445 CBT Training : PASS
4860 19:26:05.706920 Write leveling : PASS
4861 19:26:05.706998 RX DQS gating : PASS
4862 19:26:05.710060 RX DQ/DQS(RDDQC) : PASS
4863 19:26:05.713903 TX DQ/DQS : PASS
4864 19:26:05.713987 RX DATLAT : PASS
4865 19:26:05.717049 RX DQ/DQS(Engine): PASS
4866 19:26:05.717159 TX OE : NO K
4867 19:26:05.720099 All Pass.
4868 19:26:05.720181
4869 19:26:05.720277 CH 1, Rank 1
4870 19:26:05.723388 SW Impedance : PASS
4871 19:26:05.726961 DUTY Scan : NO K
4872 19:26:05.727060 ZQ Calibration : PASS
4873 19:26:05.730022 Jitter Meter : NO K
4874 19:26:05.730207 CBT Training : PASS
4875 19:26:05.733104 Write leveling : PASS
4876 19:26:05.736161 RX DQS gating : PASS
4877 19:26:05.736239 RX DQ/DQS(RDDQC) : PASS
4878 19:26:05.739943 TX DQ/DQS : PASS
4879 19:26:05.743224 RX DATLAT : PASS
4880 19:26:05.743309 RX DQ/DQS(Engine): PASS
4881 19:26:05.746286 TX OE : NO K
4882 19:26:05.746373 All Pass.
4883 19:26:05.746440
4884 19:26:05.749953 DramC Write-DBI off
4885 19:26:05.752950 PER_BANK_REFRESH: Hybrid Mode
4886 19:26:05.753062 TX_TRACKING: ON
4887 19:26:05.762607 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4888 19:26:05.765905 [FAST_K] Save calibration result to emmc
4889 19:26:05.769542 dramc_set_vcore_voltage set vcore to 662500
4890 19:26:05.772549 Read voltage for 933, 3
4891 19:26:05.772662 Vio18 = 0
4892 19:26:05.775621 Vcore = 662500
4893 19:26:05.775706 Vdram = 0
4894 19:26:05.775774 Vddq = 0
4895 19:26:05.775836 Vmddr = 0
4896 19:26:05.782556 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4897 19:26:05.789239 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4898 19:26:05.789361 MEM_TYPE=3, freq_sel=17
4899 19:26:05.792265 sv_algorithm_assistance_LP4_1600
4900 19:26:05.795427 ============ PULL DRAM RESETB DOWN ============
4901 19:26:05.801873 ========== PULL DRAM RESETB DOWN end =========
4902 19:26:05.805231 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4903 19:26:05.808763 ===================================
4904 19:26:05.812048 LPDDR4 DRAM CONFIGURATION
4905 19:26:05.815316 ===================================
4906 19:26:05.815402 EX_ROW_EN[0] = 0x0
4907 19:26:05.818549 EX_ROW_EN[1] = 0x0
4908 19:26:05.821787 LP4Y_EN = 0x0
4909 19:26:05.821873 WORK_FSP = 0x0
4910 19:26:05.824821 WL = 0x3
4911 19:26:05.824938 RL = 0x3
4912 19:26:05.828587 BL = 0x2
4913 19:26:05.828694 RPST = 0x0
4914 19:26:05.831490 RD_PRE = 0x0
4915 19:26:05.831599 WR_PRE = 0x1
4916 19:26:05.835188 WR_PST = 0x0
4917 19:26:05.835297 DBI_WR = 0x0
4918 19:26:05.838344 DBI_RD = 0x0
4919 19:26:05.838449 OTF = 0x1
4920 19:26:05.841399 ===================================
4921 19:26:05.845123 ===================================
4922 19:26:05.848235 ANA top config
4923 19:26:05.851475 ===================================
4924 19:26:05.851582 DLL_ASYNC_EN = 0
4925 19:26:05.854906 ALL_SLAVE_EN = 1
4926 19:26:05.857951 NEW_RANK_MODE = 1
4927 19:26:05.861547 DLL_IDLE_MODE = 1
4928 19:26:05.864669 LP45_APHY_COMB_EN = 1
4929 19:26:05.864785 TX_ODT_DIS = 1
4930 19:26:05.867561 NEW_8X_MODE = 1
4931 19:26:05.871283 ===================================
4932 19:26:05.874128 ===================================
4933 19:26:05.877977 data_rate = 1866
4934 19:26:05.880954 CKR = 1
4935 19:26:05.884040 DQ_P2S_RATIO = 8
4936 19:26:05.887850 ===================================
4937 19:26:05.890901 CA_P2S_RATIO = 8
4938 19:26:05.891005 DQ_CA_OPEN = 0
4939 19:26:05.894498 DQ_SEMI_OPEN = 0
4940 19:26:05.897547 CA_SEMI_OPEN = 0
4941 19:26:05.900592 CA_FULL_RATE = 0
4942 19:26:05.903946 DQ_CKDIV4_EN = 1
4943 19:26:05.907203 CA_CKDIV4_EN = 1
4944 19:26:05.907305 CA_PREDIV_EN = 0
4945 19:26:05.910791 PH8_DLY = 0
4946 19:26:05.913711 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4947 19:26:05.917212 DQ_AAMCK_DIV = 4
4948 19:26:05.920354 CA_AAMCK_DIV = 4
4949 19:26:05.923827 CA_ADMCK_DIV = 4
4950 19:26:05.927154 DQ_TRACK_CA_EN = 0
4951 19:26:05.927229 CA_PICK = 933
4952 19:26:05.930404 CA_MCKIO = 933
4953 19:26:05.933610 MCKIO_SEMI = 0
4954 19:26:05.937123 PLL_FREQ = 3732
4955 19:26:05.940396 DQ_UI_PI_RATIO = 32
4956 19:26:05.943519 CA_UI_PI_RATIO = 0
4957 19:26:05.946622 ===================================
4958 19:26:05.950426 ===================================
4959 19:26:05.953646 memory_type:LPDDR4
4960 19:26:05.953748 GP_NUM : 10
4961 19:26:05.956660 SRAM_EN : 1
4962 19:26:05.956761 MD32_EN : 0
4963 19:26:05.960228 ===================================
4964 19:26:05.963271 [ANA_INIT] >>>>>>>>>>>>>>
4965 19:26:05.967145 <<<<<< [CONFIGURE PHASE]: ANA_TX
4966 19:26:05.970257 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4967 19:26:05.973337 ===================================
4968 19:26:05.976343 data_rate = 1866,PCW = 0X8f00
4969 19:26:05.980022 ===================================
4970 19:26:05.983330 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4971 19:26:05.989822 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4972 19:26:05.993058 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4973 19:26:05.999292 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4974 19:26:06.003010 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4975 19:26:06.006108 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4976 19:26:06.006215 [ANA_INIT] flow start
4977 19:26:06.009229 [ANA_INIT] PLL >>>>>>>>
4978 19:26:06.012364 [ANA_INIT] PLL <<<<<<<<
4979 19:26:06.012471 [ANA_INIT] MIDPI >>>>>>>>
4980 19:26:06.015736 [ANA_INIT] MIDPI <<<<<<<<
4981 19:26:06.019362 [ANA_INIT] DLL >>>>>>>>
4982 19:26:06.019467 [ANA_INIT] flow end
4983 19:26:06.026106 ============ LP4 DIFF to SE enter ============
4984 19:26:06.029119 ============ LP4 DIFF to SE exit ============
4985 19:26:06.032219 [ANA_INIT] <<<<<<<<<<<<<
4986 19:26:06.035777 [Flow] Enable top DCM control >>>>>
4987 19:26:06.038595 [Flow] Enable top DCM control <<<<<
4988 19:26:06.041936 Enable DLL master slave shuffle
4989 19:26:06.045644 ==============================================================
4990 19:26:06.048506 Gating Mode config
4991 19:26:06.052050 ==============================================================
4992 19:26:06.055072 Config description:
4993 19:26:06.064973 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4994 19:26:06.071688 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4995 19:26:06.074781 SELPH_MODE 0: By rank 1: By Phase
4996 19:26:06.081666 ==============================================================
4997 19:26:06.084762 GAT_TRACK_EN = 1
4998 19:26:06.088061 RX_GATING_MODE = 2
4999 19:26:06.091544 RX_GATING_TRACK_MODE = 2
5000 19:26:06.094590 SELPH_MODE = 1
5001 19:26:06.098109 PICG_EARLY_EN = 1
5002 19:26:06.101606 VALID_LAT_VALUE = 1
5003 19:26:06.104844 ==============================================================
5004 19:26:06.108115 Enter into Gating configuration >>>>
5005 19:26:06.110952 Exit from Gating configuration <<<<
5006 19:26:06.114647 Enter into DVFS_PRE_config >>>>>
5007 19:26:06.127723 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5008 19:26:06.130893 Exit from DVFS_PRE_config <<<<<
5009 19:26:06.134076 Enter into PICG configuration >>>>
5010 19:26:06.134185 Exit from PICG configuration <<<<
5011 19:26:06.137756 [RX_INPUT] configuration >>>>>
5012 19:26:06.141025 [RX_INPUT] configuration <<<<<
5013 19:26:06.147217 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5014 19:26:06.150575 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5015 19:26:06.156942 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5016 19:26:06.164045 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5017 19:26:06.170242 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5018 19:26:06.177211 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5019 19:26:06.180169 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5020 19:26:06.183401 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5021 19:26:06.189980 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5022 19:26:06.193706 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5023 19:26:06.196698 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5024 19:26:06.200527 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5025 19:26:06.203642 ===================================
5026 19:26:06.206599 LPDDR4 DRAM CONFIGURATION
5027 19:26:06.209747 ===================================
5028 19:26:06.213163 EX_ROW_EN[0] = 0x0
5029 19:26:06.213269 EX_ROW_EN[1] = 0x0
5030 19:26:06.216553 LP4Y_EN = 0x0
5031 19:26:06.216655 WORK_FSP = 0x0
5032 19:26:06.219899 WL = 0x3
5033 19:26:06.220003 RL = 0x3
5034 19:26:06.223282 BL = 0x2
5035 19:26:06.226774 RPST = 0x0
5036 19:26:06.226864 RD_PRE = 0x0
5037 19:26:06.229865 WR_PRE = 0x1
5038 19:26:06.229939 WR_PST = 0x0
5039 19:26:06.232927 DBI_WR = 0x0
5040 19:26:06.233040 DBI_RD = 0x0
5041 19:26:06.236734 OTF = 0x1
5042 19:26:06.240060 ===================================
5043 19:26:06.242970 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5044 19:26:06.246204 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5045 19:26:06.249989 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5046 19:26:06.252987 ===================================
5047 19:26:06.255972 LPDDR4 DRAM CONFIGURATION
5048 19:26:06.259383 ===================================
5049 19:26:06.262763 EX_ROW_EN[0] = 0x10
5050 19:26:06.262844 EX_ROW_EN[1] = 0x0
5051 19:26:06.266164 LP4Y_EN = 0x0
5052 19:26:06.266242 WORK_FSP = 0x0
5053 19:26:06.269210 WL = 0x3
5054 19:26:06.269281 RL = 0x3
5055 19:26:06.272789 BL = 0x2
5056 19:26:06.275842 RPST = 0x0
5057 19:26:06.275920 RD_PRE = 0x0
5058 19:26:06.278869 WR_PRE = 0x1
5059 19:26:06.278946 WR_PST = 0x0
5060 19:26:06.282604 DBI_WR = 0x0
5061 19:26:06.282682 DBI_RD = 0x0
5062 19:26:06.285808 OTF = 0x1
5063 19:26:06.288872 ===================================
5064 19:26:06.295662 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5065 19:26:06.298732 nWR fixed to 30
5066 19:26:06.298811 [ModeRegInit_LP4] CH0 RK0
5067 19:26:06.302415 [ModeRegInit_LP4] CH0 RK1
5068 19:26:06.305453 [ModeRegInit_LP4] CH1 RK0
5069 19:26:06.308577 [ModeRegInit_LP4] CH1 RK1
5070 19:26:06.308650 match AC timing 9
5071 19:26:06.312344 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5072 19:26:06.318613 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5073 19:26:06.321653 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5074 19:26:06.328446 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5075 19:26:06.331790 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5076 19:26:06.331872 ==
5077 19:26:06.335013 Dram Type= 6, Freq= 0, CH_0, rank 0
5078 19:26:06.338293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5079 19:26:06.338379 ==
5080 19:26:06.344650 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5081 19:26:06.351696 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5082 19:26:06.354931 [CA 0] Center 37 (7~68) winsize 62
5083 19:26:06.357966 [CA 1] Center 37 (7~68) winsize 62
5084 19:26:06.361042 [CA 2] Center 34 (4~65) winsize 62
5085 19:26:06.364604 [CA 3] Center 34 (4~65) winsize 62
5086 19:26:06.368072 [CA 4] Center 33 (3~64) winsize 62
5087 19:26:06.371154 [CA 5] Center 33 (3~63) winsize 61
5088 19:26:06.371238
5089 19:26:06.374717 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5090 19:26:06.374795
5091 19:26:06.378159 [CATrainingPosCal] consider 1 rank data
5092 19:26:06.380860 u2DelayCellTimex100 = 270/100 ps
5093 19:26:06.384432 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5094 19:26:06.387785 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5095 19:26:06.391367 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5096 19:26:06.394390 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5097 19:26:06.397500 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5098 19:26:06.401167 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5099 19:26:06.404163
5100 19:26:06.407241 CA PerBit enable=1, Macro0, CA PI delay=33
5101 19:26:06.407316
5102 19:26:06.411173 [CBTSetCACLKResult] CA Dly = 33
5103 19:26:06.411256 CS Dly: 7 (0~38)
5104 19:26:06.411318 ==
5105 19:26:06.414026 Dram Type= 6, Freq= 0, CH_0, rank 1
5106 19:26:06.417145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5107 19:26:06.417217 ==
5108 19:26:06.424085 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5109 19:26:06.430746 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5110 19:26:06.433771 [CA 0] Center 37 (7~68) winsize 62
5111 19:26:06.436795 [CA 1] Center 37 (7~68) winsize 62
5112 19:26:06.440317 [CA 2] Center 34 (4~65) winsize 62
5113 19:26:06.443556 [CA 3] Center 34 (4~65) winsize 62
5114 19:26:06.446897 [CA 4] Center 33 (3~64) winsize 62
5115 19:26:06.450206 [CA 5] Center 32 (2~63) winsize 62
5116 19:26:06.450283
5117 19:26:06.453643 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5118 19:26:06.453739
5119 19:26:06.457060 [CATrainingPosCal] consider 2 rank data
5120 19:26:06.460450 u2DelayCellTimex100 = 270/100 ps
5121 19:26:06.463598 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5122 19:26:06.466872 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5123 19:26:06.469733 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5124 19:26:06.476561 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5125 19:26:06.479698 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5126 19:26:06.483199 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5127 19:26:06.483280
5128 19:26:06.486206 CA PerBit enable=1, Macro0, CA PI delay=33
5129 19:26:06.486307
5130 19:26:06.489462 [CBTSetCACLKResult] CA Dly = 33
5131 19:26:06.489564 CS Dly: 7 (0~39)
5132 19:26:06.489707
5133 19:26:06.493011 ----->DramcWriteLeveling(PI) begin...
5134 19:26:06.496141 ==
5135 19:26:06.496214 Dram Type= 6, Freq= 0, CH_0, rank 0
5136 19:26:06.503142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5137 19:26:06.503225 ==
5138 19:26:06.506265 Write leveling (Byte 0): 35 => 35
5139 19:26:06.509813 Write leveling (Byte 1): 29 => 29
5140 19:26:06.512790 DramcWriteLeveling(PI) end<-----
5141 19:26:06.512872
5142 19:26:06.512934 ==
5143 19:26:06.516583 Dram Type= 6, Freq= 0, CH_0, rank 0
5144 19:26:06.519673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5145 19:26:06.519746 ==
5146 19:26:06.522780 [Gating] SW mode calibration
5147 19:26:06.529547 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5148 19:26:06.535723 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5149 19:26:06.539353 0 14 0 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
5150 19:26:06.542517 0 14 4 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
5151 19:26:06.549087 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5152 19:26:06.552681 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5153 19:26:06.555396 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5154 19:26:06.562442 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5155 19:26:06.565195 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5156 19:26:06.568704 0 14 28 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
5157 19:26:06.575282 0 15 0 | B1->B0 | 3232 2424 | 1 0 | (1 0) (0 0)
5158 19:26:06.578542 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
5159 19:26:06.582011 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5160 19:26:06.588439 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5161 19:26:06.591964 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5162 19:26:06.594889 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5163 19:26:06.602140 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5164 19:26:06.605283 0 15 28 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
5165 19:26:06.608466 1 0 0 | B1->B0 | 2d2d 4545 | 0 0 | (0 0) (0 0)
5166 19:26:06.614908 1 0 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5167 19:26:06.618686 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5168 19:26:06.621733 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5169 19:26:06.627925 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5170 19:26:06.631615 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5171 19:26:06.634702 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5172 19:26:06.641649 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5173 19:26:06.644609 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5174 19:26:06.648389 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5175 19:26:06.654576 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 19:26:06.658080 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 19:26:06.661129 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 19:26:06.667726 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 19:26:06.671309 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 19:26:06.674297 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 19:26:06.680797 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 19:26:06.683926 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 19:26:06.687612 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 19:26:06.694131 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 19:26:06.697414 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 19:26:06.700775 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 19:26:06.707474 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 19:26:06.710596 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5189 19:26:06.713691 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5190 19:26:06.717523 Total UI for P1: 0, mck2ui 16
5191 19:26:06.720519 best dqsien dly found for B0: ( 1, 2, 28)
5192 19:26:06.727209 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5193 19:26:06.727294 Total UI for P1: 0, mck2ui 16
5194 19:26:06.730323 best dqsien dly found for B1: ( 1, 3, 0)
5195 19:26:06.737290 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5196 19:26:06.740433 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5197 19:26:06.740514
5198 19:26:06.743392 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5199 19:26:06.747198 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5200 19:26:06.750396 [Gating] SW calibration Done
5201 19:26:06.750480 ==
5202 19:26:06.753318 Dram Type= 6, Freq= 0, CH_0, rank 0
5203 19:26:06.756435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5204 19:26:06.756511 ==
5205 19:26:06.760183 RX Vref Scan: 0
5206 19:26:06.760257
5207 19:26:06.760325 RX Vref 0 -> 0, step: 1
5208 19:26:06.760386
5209 19:26:06.763261 RX Delay -80 -> 252, step: 8
5210 19:26:06.766681 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5211 19:26:06.773207 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5212 19:26:06.776337 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5213 19:26:06.780158 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5214 19:26:06.783109 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5215 19:26:06.786302 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5216 19:26:06.790030 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5217 19:26:06.796108 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5218 19:26:06.799376 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5219 19:26:06.802515 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5220 19:26:06.806399 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5221 19:26:06.809540 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5222 19:26:06.816077 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5223 19:26:06.819267 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5224 19:26:06.822249 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5225 19:26:06.825738 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5226 19:26:06.825854 ==
5227 19:26:06.828956 Dram Type= 6, Freq= 0, CH_0, rank 0
5228 19:26:06.835698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5229 19:26:06.835817 ==
5230 19:26:06.835917 DQS Delay:
5231 19:26:06.838904 DQS0 = 0, DQS1 = 0
5232 19:26:06.838990 DQM Delay:
5233 19:26:06.839057 DQM0 = 96, DQM1 = 85
5234 19:26:06.842050 DQ Delay:
5235 19:26:06.845853 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5236 19:26:06.848936 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =107
5237 19:26:06.852003 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5238 19:26:06.855122 DQ12 =87, DQ13 =91, DQ14 =95, DQ15 =91
5239 19:26:06.855208
5240 19:26:06.855275
5241 19:26:06.855337 ==
5242 19:26:06.858975 Dram Type= 6, Freq= 0, CH_0, rank 0
5243 19:26:06.862038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5244 19:26:06.862124 ==
5245 19:26:06.862191
5246 19:26:06.862254
5247 19:26:06.865263 TX Vref Scan disable
5248 19:26:06.868410 == TX Byte 0 ==
5249 19:26:06.871829 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5250 19:26:06.875358 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5251 19:26:06.878153 == TX Byte 1 ==
5252 19:26:06.881692 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5253 19:26:06.885381 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5254 19:26:06.885467 ==
5255 19:26:06.888484 Dram Type= 6, Freq= 0, CH_0, rank 0
5256 19:26:06.891671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5257 19:26:06.894884 ==
5258 19:26:06.894970
5259 19:26:06.895037
5260 19:26:06.895100 TX Vref Scan disable
5261 19:26:06.898534 == TX Byte 0 ==
5262 19:26:06.902225 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5263 19:26:06.908374 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5264 19:26:06.908467 == TX Byte 1 ==
5265 19:26:06.911757 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5266 19:26:06.918099 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5267 19:26:06.918185
5268 19:26:06.918253 [DATLAT]
5269 19:26:06.918316 Freq=933, CH0 RK0
5270 19:26:06.918377
5271 19:26:06.921381 DATLAT Default: 0xd
5272 19:26:06.925106 0, 0xFFFF, sum = 0
5273 19:26:06.925193 1, 0xFFFF, sum = 0
5274 19:26:06.928237 2, 0xFFFF, sum = 0
5275 19:26:06.928322 3, 0xFFFF, sum = 0
5276 19:26:06.931567 4, 0xFFFF, sum = 0
5277 19:26:06.931648 5, 0xFFFF, sum = 0
5278 19:26:06.935084 6, 0xFFFF, sum = 0
5279 19:26:06.935163 7, 0xFFFF, sum = 0
5280 19:26:06.937830 8, 0xFFFF, sum = 0
5281 19:26:06.937905 9, 0xFFFF, sum = 0
5282 19:26:06.941614 10, 0x0, sum = 1
5283 19:26:06.941696 11, 0x0, sum = 2
5284 19:26:06.944912 12, 0x0, sum = 3
5285 19:26:06.944988 13, 0x0, sum = 4
5286 19:26:06.947919 best_step = 11
5287 19:26:06.948000
5288 19:26:06.948072 ==
5289 19:26:06.950998 Dram Type= 6, Freq= 0, CH_0, rank 0
5290 19:26:06.954595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5291 19:26:06.954711 ==
5292 19:26:06.954808 RX Vref Scan: 1
5293 19:26:06.957897
5294 19:26:06.958019 RX Vref 0 -> 0, step: 1
5295 19:26:06.958089
5296 19:26:06.961449 RX Delay -61 -> 252, step: 4
5297 19:26:06.961522
5298 19:26:06.964514 Set Vref, RX VrefLevel [Byte0]: 57
5299 19:26:06.967595 [Byte1]: 48
5300 19:26:06.971505
5301 19:26:06.971584 Final RX Vref Byte 0 = 57 to rank0
5302 19:26:06.974461 Final RX Vref Byte 1 = 48 to rank0
5303 19:26:06.977974 Final RX Vref Byte 0 = 57 to rank1
5304 19:26:06.980918 Final RX Vref Byte 1 = 48 to rank1==
5305 19:26:06.984420 Dram Type= 6, Freq= 0, CH_0, rank 0
5306 19:26:06.991192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5307 19:26:06.991280 ==
5308 19:26:06.991347 DQS Delay:
5309 19:26:06.994327 DQS0 = 0, DQS1 = 0
5310 19:26:06.994415 DQM Delay:
5311 19:26:06.994511 DQM0 = 97, DQM1 = 84
5312 19:26:06.997302 DQ Delay:
5313 19:26:07.001055 DQ0 =96, DQ1 =98, DQ2 =92, DQ3 =92
5314 19:26:07.004225 DQ4 =98, DQ5 =88, DQ6 =106, DQ7 =106
5315 19:26:07.007957 DQ8 =76, DQ9 =72, DQ10 =86, DQ11 =78
5316 19:26:07.010967 DQ12 =88, DQ13 =88, DQ14 =98, DQ15 =92
5317 19:26:07.011051
5318 19:26:07.011117
5319 19:26:07.017351 [DQSOSCAuto] RK0, (LSB)MR18= 0x250c, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 410 ps
5320 19:26:07.021135 CH0 RK0: MR19=505, MR18=250C
5321 19:26:07.027159 CH0_RK0: MR19=0x505, MR18=0x250C, DQSOSC=410, MR23=63, INC=64, DEC=42
5322 19:26:07.027247
5323 19:26:07.030564 ----->DramcWriteLeveling(PI) begin...
5324 19:26:07.030645 ==
5325 19:26:07.034247 Dram Type= 6, Freq= 0, CH_0, rank 1
5326 19:26:07.037559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5327 19:26:07.037638 ==
5328 19:26:07.040896 Write leveling (Byte 0): 32 => 32
5329 19:26:07.043982 Write leveling (Byte 1): 32 => 32
5330 19:26:07.047556 DramcWriteLeveling(PI) end<-----
5331 19:26:07.047641
5332 19:26:07.047712 ==
5333 19:26:07.050458 Dram Type= 6, Freq= 0, CH_0, rank 1
5334 19:26:07.053652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5335 19:26:07.057273 ==
5336 19:26:07.057363 [Gating] SW mode calibration
5337 19:26:07.066748 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5338 19:26:07.070504 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5339 19:26:07.073617 0 14 0 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
5340 19:26:07.080418 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5341 19:26:07.083277 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5342 19:26:07.086849 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5343 19:26:07.093202 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5344 19:26:07.096576 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5345 19:26:07.100017 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5346 19:26:07.107031 0 14 28 | B1->B0 | 3333 2f2f | 1 0 | (1 0) (1 0)
5347 19:26:07.110007 0 15 0 | B1->B0 | 2f2f 2f2f | 0 0 | (1 1) (1 1)
5348 19:26:07.113152 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (1 1) (0 0)
5349 19:26:07.119982 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5350 19:26:07.123066 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5351 19:26:07.125983 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5352 19:26:07.132800 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5353 19:26:07.136301 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5354 19:26:07.139752 0 15 28 | B1->B0 | 2525 3232 | 0 0 | (0 0) (0 0)
5355 19:26:07.146144 1 0 0 | B1->B0 | 4343 4444 | 0 0 | (0 0) (0 0)
5356 19:26:07.149522 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5357 19:26:07.152535 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5358 19:26:07.159122 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5359 19:26:07.162617 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5360 19:26:07.166201 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5361 19:26:07.172322 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5362 19:26:07.175561 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5363 19:26:07.179144 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5364 19:26:07.185428 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5365 19:26:07.188985 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 19:26:07.192119 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 19:26:07.198406 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 19:26:07.202197 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 19:26:07.205132 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 19:26:07.212142 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 19:26:07.215282 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 19:26:07.218398 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 19:26:07.225141 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 19:26:07.228342 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 19:26:07.232187 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 19:26:07.238879 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 19:26:07.241560 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 19:26:07.244986 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5379 19:26:07.251593 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5380 19:26:07.251697 Total UI for P1: 0, mck2ui 16
5381 19:26:07.258086 best dqsien dly found for B0: ( 1, 2, 28)
5382 19:26:07.261734 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5383 19:26:07.265020 Total UI for P1: 0, mck2ui 16
5384 19:26:07.268064 best dqsien dly found for B1: ( 1, 3, 0)
5385 19:26:07.271242 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5386 19:26:07.274541 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5387 19:26:07.274627
5388 19:26:07.278211 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5389 19:26:07.281374 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5390 19:26:07.284440 [Gating] SW calibration Done
5391 19:26:07.284524 ==
5392 19:26:07.287618 Dram Type= 6, Freq= 0, CH_0, rank 1
5393 19:26:07.294327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5394 19:26:07.294414 ==
5395 19:26:07.294481 RX Vref Scan: 0
5396 19:26:07.294545
5397 19:26:07.298079 RX Vref 0 -> 0, step: 1
5398 19:26:07.298168
5399 19:26:07.300974 RX Delay -80 -> 252, step: 8
5400 19:26:07.304215 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5401 19:26:07.307801 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5402 19:26:07.311000 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5403 19:26:07.314050 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5404 19:26:07.320944 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5405 19:26:07.324138 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5406 19:26:07.327351 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5407 19:26:07.331043 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5408 19:26:07.334240 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5409 19:26:07.337165 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5410 19:26:07.343833 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5411 19:26:07.347094 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5412 19:26:07.350171 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5413 19:26:07.353580 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5414 19:26:07.356958 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5415 19:26:07.363802 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5416 19:26:07.363892 ==
5417 19:26:07.366617 Dram Type= 6, Freq= 0, CH_0, rank 1
5418 19:26:07.369972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5419 19:26:07.370061 ==
5420 19:26:07.370149 DQS Delay:
5421 19:26:07.373194 DQS0 = 0, DQS1 = 0
5422 19:26:07.373282 DQM Delay:
5423 19:26:07.376758 DQM0 = 96, DQM1 = 88
5424 19:26:07.376847 DQ Delay:
5425 19:26:07.380207 DQ0 =95, DQ1 =99, DQ2 =87, DQ3 =91
5426 19:26:07.383188 DQ4 =95, DQ5 =87, DQ6 =107, DQ7 =107
5427 19:26:07.386815 DQ8 =79, DQ9 =75, DQ10 =91, DQ11 =83
5428 19:26:07.389958 DQ12 =95, DQ13 =91, DQ14 =95, DQ15 =95
5429 19:26:07.390047
5430 19:26:07.390136
5431 19:26:07.390219 ==
5432 19:26:07.393180 Dram Type= 6, Freq= 0, CH_0, rank 1
5433 19:26:07.396254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5434 19:26:07.399792 ==
5435 19:26:07.399880
5436 19:26:07.399968
5437 19:26:07.400051 TX Vref Scan disable
5438 19:26:07.403015 == TX Byte 0 ==
5439 19:26:07.406455 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5440 19:26:07.409267 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5441 19:26:07.412882 == TX Byte 1 ==
5442 19:26:07.415947 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5443 19:26:07.419627 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5444 19:26:07.422828 ==
5445 19:26:07.425837 Dram Type= 6, Freq= 0, CH_0, rank 1
5446 19:26:07.429701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5447 19:26:07.429789 ==
5448 19:26:07.429857
5449 19:26:07.429919
5450 19:26:07.432723 TX Vref Scan disable
5451 19:26:07.432815 == TX Byte 0 ==
5452 19:26:07.439057 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5453 19:26:07.442888 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5454 19:26:07.442976 == TX Byte 1 ==
5455 19:26:07.449482 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5456 19:26:07.452746 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5457 19:26:07.452831
5458 19:26:07.452898 [DATLAT]
5459 19:26:07.455665 Freq=933, CH0 RK1
5460 19:26:07.455760
5461 19:26:07.455828 DATLAT Default: 0xb
5462 19:26:07.458741 0, 0xFFFF, sum = 0
5463 19:26:07.458828 1, 0xFFFF, sum = 0
5464 19:26:07.462295 2, 0xFFFF, sum = 0
5465 19:26:07.465287 3, 0xFFFF, sum = 0
5466 19:26:07.465400 4, 0xFFFF, sum = 0
5467 19:26:07.468523 5, 0xFFFF, sum = 0
5468 19:26:07.468608 6, 0xFFFF, sum = 0
5469 19:26:07.472020 7, 0xFFFF, sum = 0
5470 19:26:07.472130 8, 0xFFFF, sum = 0
5471 19:26:07.475463 9, 0xFFFF, sum = 0
5472 19:26:07.475559 10, 0x0, sum = 1
5473 19:26:07.478927 11, 0x0, sum = 2
5474 19:26:07.479007 12, 0x0, sum = 3
5475 19:26:07.482123 13, 0x0, sum = 4
5476 19:26:07.482199 best_step = 11
5477 19:26:07.482265
5478 19:26:07.482327 ==
5479 19:26:07.485305 Dram Type= 6, Freq= 0, CH_0, rank 1
5480 19:26:07.488614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5481 19:26:07.488698 ==
5482 19:26:07.492012 RX Vref Scan: 0
5483 19:26:07.492099
5484 19:26:07.495038 RX Vref 0 -> 0, step: 1
5485 19:26:07.495138
5486 19:26:07.495247 RX Delay -69 -> 252, step: 4
5487 19:26:07.503403 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5488 19:26:07.506459 iDelay=203, Bit 1, Center 96 (-1 ~ 194) 196
5489 19:26:07.510133 iDelay=203, Bit 2, Center 90 (-1 ~ 182) 184
5490 19:26:07.513042 iDelay=203, Bit 3, Center 94 (-1 ~ 190) 192
5491 19:26:07.516310 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5492 19:26:07.523166 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5493 19:26:07.526187 iDelay=203, Bit 6, Center 106 (11 ~ 202) 192
5494 19:26:07.529519 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5495 19:26:07.532613 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5496 19:26:07.536311 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5497 19:26:07.542571 iDelay=203, Bit 10, Center 86 (-9 ~ 182) 192
5498 19:26:07.545813 iDelay=203, Bit 11, Center 78 (-13 ~ 170) 184
5499 19:26:07.549545 iDelay=203, Bit 12, Center 92 (-1 ~ 186) 188
5500 19:26:07.552587 iDelay=203, Bit 13, Center 92 (-1 ~ 186) 188
5501 19:26:07.556290 iDelay=203, Bit 14, Center 100 (11 ~ 190) 180
5502 19:26:07.562462 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5503 19:26:07.562573 ==
5504 19:26:07.565553 Dram Type= 6, Freq= 0, CH_0, rank 1
5505 19:26:07.569095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5506 19:26:07.569202 ==
5507 19:26:07.569296 DQS Delay:
5508 19:26:07.572377 DQS0 = 0, DQS1 = 0
5509 19:26:07.572485 DQM Delay:
5510 19:26:07.575832 DQM0 = 95, DQM1 = 86
5511 19:26:07.575934 DQ Delay:
5512 19:26:07.578679 DQ0 =92, DQ1 =96, DQ2 =90, DQ3 =94
5513 19:26:07.582382 DQ4 =96, DQ5 =86, DQ6 =106, DQ7 =104
5514 19:26:07.585445 DQ8 =78, DQ9 =74, DQ10 =86, DQ11 =78
5515 19:26:07.589020 DQ12 =92, DQ13 =92, DQ14 =100, DQ15 =92
5516 19:26:07.589143
5517 19:26:07.589254
5518 19:26:07.598516 [DQSOSCAuto] RK1, (LSB)MR18= 0x22f2, (MSB)MR19= 0x504, tDQSOscB0 = 426 ps tDQSOscB1 = 411 ps
5519 19:26:07.598630 CH0 RK1: MR19=504, MR18=22F2
5520 19:26:07.605178 CH0_RK1: MR19=0x504, MR18=0x22F2, DQSOSC=411, MR23=63, INC=64, DEC=42
5521 19:26:07.608740 [RxdqsGatingPostProcess] freq 933
5522 19:26:07.614691 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5523 19:26:07.618212 best DQS0 dly(2T, 0.5T) = (0, 10)
5524 19:26:07.621680 best DQS1 dly(2T, 0.5T) = (0, 11)
5525 19:26:07.624576 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5526 19:26:07.628265 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5527 19:26:07.631442 best DQS0 dly(2T, 0.5T) = (0, 10)
5528 19:26:07.634515 best DQS1 dly(2T, 0.5T) = (0, 11)
5529 19:26:07.638147 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5530 19:26:07.641189 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5531 19:26:07.641286 Pre-setting of DQS Precalculation
5532 19:26:07.648080 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5533 19:26:07.648159 ==
5534 19:26:07.651202 Dram Type= 6, Freq= 0, CH_1, rank 0
5535 19:26:07.654270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5536 19:26:07.654346 ==
5537 19:26:07.661158 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5538 19:26:07.667845 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5539 19:26:07.670896 [CA 0] Center 36 (6~67) winsize 62
5540 19:26:07.674012 [CA 1] Center 37 (6~68) winsize 63
5541 19:26:07.677288 [CA 2] Center 34 (4~64) winsize 61
5542 19:26:07.680599 [CA 3] Center 33 (3~64) winsize 62
5543 19:26:07.684036 [CA 4] Center 34 (4~64) winsize 61
5544 19:26:07.687102 [CA 5] Center 33 (3~64) winsize 62
5545 19:26:07.687180
5546 19:26:07.690808 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5547 19:26:07.690888
5548 19:26:07.693836 [CATrainingPosCal] consider 1 rank data
5549 19:26:07.697467 u2DelayCellTimex100 = 270/100 ps
5550 19:26:07.700687 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5551 19:26:07.703645 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5552 19:26:07.706914 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5553 19:26:07.710251 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5554 19:26:07.717088 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5555 19:26:07.720094 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5556 19:26:07.720173
5557 19:26:07.723642 CA PerBit enable=1, Macro0, CA PI delay=33
5558 19:26:07.723728
5559 19:26:07.726882 [CBTSetCACLKResult] CA Dly = 33
5560 19:26:07.726969 CS Dly: 5 (0~36)
5561 19:26:07.727064 ==
5562 19:26:07.730295 Dram Type= 6, Freq= 0, CH_1, rank 1
5563 19:26:07.736695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5564 19:26:07.736803 ==
5565 19:26:07.739812 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5566 19:26:07.746879 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5567 19:26:07.749778 [CA 0] Center 36 (6~67) winsize 62
5568 19:26:07.752952 [CA 1] Center 37 (7~67) winsize 61
5569 19:26:07.756581 [CA 2] Center 34 (4~65) winsize 62
5570 19:26:07.759511 [CA 3] Center 33 (3~64) winsize 62
5571 19:26:07.763259 [CA 4] Center 34 (3~65) winsize 63
5572 19:26:07.766397 [CA 5] Center 33 (3~64) winsize 62
5573 19:26:07.766474
5574 19:26:07.769351 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5575 19:26:07.769428
5576 19:26:07.773259 [CATrainingPosCal] consider 2 rank data
5577 19:26:07.776280 u2DelayCellTimex100 = 270/100 ps
5578 19:26:07.779326 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5579 19:26:07.786029 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5580 19:26:07.789064 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5581 19:26:07.792384 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5582 19:26:07.795987 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5583 19:26:07.799099 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5584 19:26:07.799172
5585 19:26:07.802723 CA PerBit enable=1, Macro0, CA PI delay=33
5586 19:26:07.802793
5587 19:26:07.805867 [CBTSetCACLKResult] CA Dly = 33
5588 19:26:07.809132 CS Dly: 6 (0~39)
5589 19:26:07.809215
5590 19:26:07.812441 ----->DramcWriteLeveling(PI) begin...
5591 19:26:07.812513 ==
5592 19:26:07.815921 Dram Type= 6, Freq= 0, CH_1, rank 0
5593 19:26:07.819290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5594 19:26:07.819362 ==
5595 19:26:07.822604 Write leveling (Byte 0): 23 => 23
5596 19:26:07.825546 Write leveling (Byte 1): 31 => 31
5597 19:26:07.829011 DramcWriteLeveling(PI) end<-----
5598 19:26:07.829085
5599 19:26:07.829164 ==
5600 19:26:07.832579 Dram Type= 6, Freq= 0, CH_1, rank 0
5601 19:26:07.835651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5602 19:26:07.835731 ==
5603 19:26:07.838716 [Gating] SW mode calibration
5604 19:26:07.845264 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5605 19:26:07.852165 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5606 19:26:07.855412 0 14 0 | B1->B0 | 3130 3434 | 1 1 | (0 0) (1 1)
5607 19:26:07.858391 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5608 19:26:07.865083 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5609 19:26:07.868161 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5610 19:26:07.871815 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5611 19:26:07.878486 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5612 19:26:07.881710 0 14 24 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 1)
5613 19:26:07.884871 0 14 28 | B1->B0 | 2e2e 2a2a | 0 0 | (0 0) (1 1)
5614 19:26:07.891456 0 15 0 | B1->B0 | 2525 2323 | 0 0 | (1 1) (0 0)
5615 19:26:07.894811 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5616 19:26:07.897731 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5617 19:26:07.904393 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5618 19:26:07.908042 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5619 19:26:07.911096 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5620 19:26:07.917948 0 15 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5621 19:26:07.921358 0 15 28 | B1->B0 | 3232 3a3a | 0 0 | (0 0) (1 1)
5622 19:26:07.924060 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5623 19:26:07.930919 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5624 19:26:07.934313 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5625 19:26:07.937815 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5626 19:26:07.944005 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5627 19:26:07.947236 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5628 19:26:07.953842 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5629 19:26:07.957093 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5630 19:26:07.960391 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 19:26:07.967081 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 19:26:07.970579 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 19:26:07.973666 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 19:26:07.980294 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 19:26:07.983493 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 19:26:07.986549 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 19:26:07.993472 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 19:26:07.996515 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 19:26:08.000157 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 19:26:08.006560 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 19:26:08.009665 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 19:26:08.013245 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 19:26:08.019615 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 19:26:08.022682 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5645 19:26:08.025848 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5646 19:26:08.032598 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5647 19:26:08.032680 Total UI for P1: 0, mck2ui 16
5648 19:26:08.039249 best dqsien dly found for B0: ( 1, 2, 26)
5649 19:26:08.039359 Total UI for P1: 0, mck2ui 16
5650 19:26:08.045772 best dqsien dly found for B1: ( 1, 2, 26)
5651 19:26:08.048758 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5652 19:26:08.052044 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5653 19:26:08.052122
5654 19:26:08.055768 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5655 19:26:08.058792 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5656 19:26:08.061890 [Gating] SW calibration Done
5657 19:26:08.062001 ==
5658 19:26:08.065398 Dram Type= 6, Freq= 0, CH_1, rank 0
5659 19:26:08.068655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5660 19:26:08.068752 ==
5661 19:26:08.072144 RX Vref Scan: 0
5662 19:26:08.072243
5663 19:26:08.072333 RX Vref 0 -> 0, step: 1
5664 19:26:08.075014
5665 19:26:08.075111 RX Delay -80 -> 252, step: 8
5666 19:26:08.081802 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5667 19:26:08.084873 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5668 19:26:08.088687 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5669 19:26:08.091897 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5670 19:26:08.094945 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5671 19:26:08.098563 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5672 19:26:08.104638 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5673 19:26:08.108289 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5674 19:26:08.111222 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5675 19:26:08.114974 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5676 19:26:08.118010 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5677 19:26:08.124922 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5678 19:26:08.128042 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5679 19:26:08.131067 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5680 19:26:08.134776 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5681 19:26:08.137916 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5682 19:26:08.137988 ==
5683 19:26:08.140915 Dram Type= 6, Freq= 0, CH_1, rank 0
5684 19:26:08.147757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5685 19:26:08.147861 ==
5686 19:26:08.147941 DQS Delay:
5687 19:26:08.150874 DQS0 = 0, DQS1 = 0
5688 19:26:08.150950 DQM Delay:
5689 19:26:08.151012 DQM0 = 100, DQM1 = 91
5690 19:26:08.154424 DQ Delay:
5691 19:26:08.157505 DQ0 =107, DQ1 =95, DQ2 =95, DQ3 =95
5692 19:26:08.160873 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5693 19:26:08.164100 DQ8 =79, DQ9 =83, DQ10 =91, DQ11 =79
5694 19:26:08.167327 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5695 19:26:08.167408
5696 19:26:08.167481
5697 19:26:08.167543 ==
5698 19:26:08.170815 Dram Type= 6, Freq= 0, CH_1, rank 0
5699 19:26:08.173820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5700 19:26:08.173899 ==
5701 19:26:08.173963
5702 19:26:08.174024
5703 19:26:08.177371 TX Vref Scan disable
5704 19:26:08.180463 == TX Byte 0 ==
5705 19:26:08.184021 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5706 19:26:08.186824 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5707 19:26:08.190722 == TX Byte 1 ==
5708 19:26:08.193812 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5709 19:26:08.197035 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5710 19:26:08.197143 ==
5711 19:26:08.199989 Dram Type= 6, Freq= 0, CH_1, rank 0
5712 19:26:08.206662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5713 19:26:08.206764 ==
5714 19:26:08.206865
5715 19:26:08.206955
5716 19:26:08.207043 TX Vref Scan disable
5717 19:26:08.211084 == TX Byte 0 ==
5718 19:26:08.214494 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5719 19:26:08.221033 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5720 19:26:08.221116 == TX Byte 1 ==
5721 19:26:08.224177 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5722 19:26:08.230920 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5723 19:26:08.230999
5724 19:26:08.231070 [DATLAT]
5725 19:26:08.231132 Freq=933, CH1 RK0
5726 19:26:08.231192
5727 19:26:08.234070 DATLAT Default: 0xd
5728 19:26:08.234137 0, 0xFFFF, sum = 0
5729 19:26:08.237655 1, 0xFFFF, sum = 0
5730 19:26:08.240595 2, 0xFFFF, sum = 0
5731 19:26:08.240672 3, 0xFFFF, sum = 0
5732 19:26:08.244259 4, 0xFFFF, sum = 0
5733 19:26:08.244328 5, 0xFFFF, sum = 0
5734 19:26:08.247177 6, 0xFFFF, sum = 0
5735 19:26:08.247249 7, 0xFFFF, sum = 0
5736 19:26:08.250803 8, 0xFFFF, sum = 0
5737 19:26:08.250892 9, 0xFFFF, sum = 0
5738 19:26:08.253973 10, 0x0, sum = 1
5739 19:26:08.254056 11, 0x0, sum = 2
5740 19:26:08.256950 12, 0x0, sum = 3
5741 19:26:08.257061 13, 0x0, sum = 4
5742 19:26:08.260621 best_step = 11
5743 19:26:08.260698
5744 19:26:08.260762 ==
5745 19:26:08.263733 Dram Type= 6, Freq= 0, CH_1, rank 0
5746 19:26:08.267162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5747 19:26:08.267246 ==
5748 19:26:08.267319 RX Vref Scan: 1
5749 19:26:08.270075
5750 19:26:08.270176 RX Vref 0 -> 0, step: 1
5751 19:26:08.270280
5752 19:26:08.273291 RX Delay -61 -> 252, step: 4
5753 19:26:08.273391
5754 19:26:08.276713 Set Vref, RX VrefLevel [Byte0]: 48
5755 19:26:08.280323 [Byte1]: 53
5756 19:26:08.283711
5757 19:26:08.283793 Final RX Vref Byte 0 = 48 to rank0
5758 19:26:08.286857 Final RX Vref Byte 1 = 53 to rank0
5759 19:26:08.290354 Final RX Vref Byte 0 = 48 to rank1
5760 19:26:08.293410 Final RX Vref Byte 1 = 53 to rank1==
5761 19:26:08.296715 Dram Type= 6, Freq= 0, CH_1, rank 0
5762 19:26:08.303280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5763 19:26:08.303364 ==
5764 19:26:08.303432 DQS Delay:
5765 19:26:08.306551 DQS0 = 0, DQS1 = 0
5766 19:26:08.306636 DQM Delay:
5767 19:26:08.306711 DQM0 = 101, DQM1 = 94
5768 19:26:08.310121 DQ Delay:
5769 19:26:08.313304 DQ0 =106, DQ1 =96, DQ2 =92, DQ3 =98
5770 19:26:08.316353 DQ4 =98, DQ5 =112, DQ6 =108, DQ7 =98
5771 19:26:08.320150 DQ8 =80, DQ9 =84, DQ10 =94, DQ11 =86
5772 19:26:08.323051 DQ12 =102, DQ13 =100, DQ14 =104, DQ15 =104
5773 19:26:08.323132
5774 19:26:08.323220
5775 19:26:08.330057 [DQSOSCAuto] RK0, (LSB)MR18= 0x1505, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 415 ps
5776 19:26:08.333089 CH1 RK0: MR19=505, MR18=1505
5777 19:26:08.339901 CH1_RK0: MR19=0x505, MR18=0x1505, DQSOSC=415, MR23=63, INC=62, DEC=41
5778 19:26:08.339986
5779 19:26:08.343137 ----->DramcWriteLeveling(PI) begin...
5780 19:26:08.343213 ==
5781 19:26:08.346135 Dram Type= 6, Freq= 0, CH_1, rank 1
5782 19:26:08.349659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5783 19:26:08.352692 ==
5784 19:26:08.352774 Write leveling (Byte 0): 26 => 26
5785 19:26:08.356401 Write leveling (Byte 1): 25 => 25
5786 19:26:08.359484 DramcWriteLeveling(PI) end<-----
5787 19:26:08.359559
5788 19:26:08.359622 ==
5789 19:26:08.362769 Dram Type= 6, Freq= 0, CH_1, rank 1
5790 19:26:08.368934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5791 19:26:08.369016 ==
5792 19:26:08.372636 [Gating] SW mode calibration
5793 19:26:08.379114 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5794 19:26:08.382671 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5795 19:26:08.388743 0 14 0 | B1->B0 | 3333 3131 | 1 1 | (1 1) (1 1)
5796 19:26:08.392308 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5797 19:26:08.395497 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5798 19:26:08.402117 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5799 19:26:08.405482 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5800 19:26:08.408527 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5801 19:26:08.415295 0 14 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5802 19:26:08.418442 0 14 28 | B1->B0 | 2626 2f2f | 0 0 | (1 0) (1 0)
5803 19:26:08.421591 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5804 19:26:08.428681 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5805 19:26:08.431909 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5806 19:26:08.434832 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5807 19:26:08.441245 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5808 19:26:08.445080 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5809 19:26:08.448166 0 15 24 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
5810 19:26:08.454627 0 15 28 | B1->B0 | 3737 3131 | 0 0 | (1 1) (0 0)
5811 19:26:08.458356 1 0 0 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
5812 19:26:08.461346 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5813 19:26:08.467717 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5814 19:26:08.471535 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5815 19:26:08.474613 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5816 19:26:08.481217 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5817 19:26:08.484214 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5818 19:26:08.487991 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5819 19:26:08.494155 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5820 19:26:08.497507 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5821 19:26:08.501036 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5822 19:26:08.507275 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5823 19:26:08.510590 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5824 19:26:08.514110 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5825 19:26:08.520332 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5826 19:26:08.524010 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5827 19:26:08.527141 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5828 19:26:08.534136 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 19:26:08.537062 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 19:26:08.540237 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 19:26:08.546678 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 19:26:08.550393 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 19:26:08.553438 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 19:26:08.560162 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5835 19:26:08.563220 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5836 19:26:08.566909 Total UI for P1: 0, mck2ui 16
5837 19:26:08.570045 best dqsien dly found for B0: ( 1, 2, 28)
5838 19:26:08.573130 Total UI for P1: 0, mck2ui 16
5839 19:26:08.576850 best dqsien dly found for B1: ( 1, 2, 28)
5840 19:26:08.579945 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5841 19:26:08.583496 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5842 19:26:08.583580
5843 19:26:08.586545 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5844 19:26:08.589514 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5845 19:26:08.593250 [Gating] SW calibration Done
5846 19:26:08.593338 ==
5847 19:26:08.596430 Dram Type= 6, Freq= 0, CH_1, rank 1
5848 19:26:08.603069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5849 19:26:08.603155 ==
5850 19:26:08.603222 RX Vref Scan: 0
5851 19:26:08.603285
5852 19:26:08.606261 RX Vref 0 -> 0, step: 1
5853 19:26:08.606344
5854 19:26:08.609898 RX Delay -80 -> 252, step: 8
5855 19:26:08.612824 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5856 19:26:08.616502 iDelay=208, Bit 1, Center 91 (0 ~ 183) 184
5857 19:26:08.619275 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5858 19:26:08.622679 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5859 19:26:08.629625 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5860 19:26:08.632631 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5861 19:26:08.635704 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5862 19:26:08.639046 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5863 19:26:08.642583 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5864 19:26:08.648809 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5865 19:26:08.652259 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5866 19:26:08.655841 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5867 19:26:08.658861 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5868 19:26:08.662367 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5869 19:26:08.668660 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5870 19:26:08.671821 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5871 19:26:08.671936 ==
5872 19:26:08.675557 Dram Type= 6, Freq= 0, CH_1, rank 1
5873 19:26:08.678644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5874 19:26:08.678838 ==
5875 19:26:08.679005 DQS Delay:
5876 19:26:08.681994 DQS0 = 0, DQS1 = 0
5877 19:26:08.682093 DQM Delay:
5878 19:26:08.684791 DQM0 = 99, DQM1 = 91
5879 19:26:08.684873 DQ Delay:
5880 19:26:08.688596 DQ0 =103, DQ1 =91, DQ2 =91, DQ3 =95
5881 19:26:08.691619 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5882 19:26:08.694910 DQ8 =79, DQ9 =79, DQ10 =95, DQ11 =83
5883 19:26:08.698117 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =99
5884 19:26:08.698199
5885 19:26:08.698263
5886 19:26:08.698340 ==
5887 19:26:08.701143 Dram Type= 6, Freq= 0, CH_1, rank 1
5888 19:26:08.708087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5889 19:26:08.708186 ==
5890 19:26:08.708253
5891 19:26:08.708314
5892 19:26:08.708372 TX Vref Scan disable
5893 19:26:08.711712 == TX Byte 0 ==
5894 19:26:08.714645 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5895 19:26:08.721219 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5896 19:26:08.721314 == TX Byte 1 ==
5897 19:26:08.724440 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5898 19:26:08.731692 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5899 19:26:08.731804 ==
5900 19:26:08.734414 Dram Type= 6, Freq= 0, CH_1, rank 1
5901 19:26:08.738017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5902 19:26:08.738153 ==
5903 19:26:08.738260
5904 19:26:08.738360
5905 19:26:08.741165 TX Vref Scan disable
5906 19:26:08.744286 == TX Byte 0 ==
5907 19:26:08.748136 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5908 19:26:08.751051 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5909 19:26:08.754283 == TX Byte 1 ==
5910 19:26:08.757281 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5911 19:26:08.760790 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5912 19:26:08.760963
5913 19:26:08.761117 [DATLAT]
5914 19:26:08.764168 Freq=933, CH1 RK1
5915 19:26:08.764341
5916 19:26:08.767656 DATLAT Default: 0xb
5917 19:26:08.767857 0, 0xFFFF, sum = 0
5918 19:26:08.770615 1, 0xFFFF, sum = 0
5919 19:26:08.770821 2, 0xFFFF, sum = 0
5920 19:26:08.774311 3, 0xFFFF, sum = 0
5921 19:26:08.774515 4, 0xFFFF, sum = 0
5922 19:26:08.777569 5, 0xFFFF, sum = 0
5923 19:26:08.777772 6, 0xFFFF, sum = 0
5924 19:26:08.780811 7, 0xFFFF, sum = 0
5925 19:26:08.781013 8, 0xFFFF, sum = 0
5926 19:26:08.783951 9, 0xFFFF, sum = 0
5927 19:26:08.784173 10, 0x0, sum = 1
5928 19:26:08.787674 11, 0x0, sum = 2
5929 19:26:08.787918 12, 0x0, sum = 3
5930 19:26:08.790659 13, 0x0, sum = 4
5931 19:26:08.790903 best_step = 11
5932 19:26:08.791094
5933 19:26:08.791272 ==
5934 19:26:08.793832 Dram Type= 6, Freq= 0, CH_1, rank 1
5935 19:26:08.797651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5936 19:26:08.801108 ==
5937 19:26:08.801529 RX Vref Scan: 0
5938 19:26:08.801839
5939 19:26:08.804287 RX Vref 0 -> 0, step: 1
5940 19:26:08.804704
5941 19:26:08.807343 RX Delay -61 -> 252, step: 4
5942 19:26:08.810985 iDelay=207, Bit 0, Center 106 (19 ~ 194) 176
5943 19:26:08.814298 iDelay=207, Bit 1, Center 94 (7 ~ 182) 176
5944 19:26:08.820540 iDelay=207, Bit 2, Center 92 (7 ~ 178) 172
5945 19:26:08.823988 iDelay=207, Bit 3, Center 98 (15 ~ 182) 168
5946 19:26:08.826969 iDelay=207, Bit 4, Center 98 (7 ~ 190) 184
5947 19:26:08.830532 iDelay=207, Bit 5, Center 110 (23 ~ 198) 176
5948 19:26:08.833816 iDelay=207, Bit 6, Center 114 (23 ~ 206) 184
5949 19:26:08.836974 iDelay=207, Bit 7, Center 98 (7 ~ 190) 184
5950 19:26:08.843361 iDelay=207, Bit 8, Center 82 (-9 ~ 174) 184
5951 19:26:08.847057 iDelay=207, Bit 9, Center 84 (-5 ~ 174) 180
5952 19:26:08.850524 iDelay=207, Bit 10, Center 96 (7 ~ 186) 180
5953 19:26:08.853554 iDelay=207, Bit 11, Center 84 (-5 ~ 174) 180
5954 19:26:08.856635 iDelay=207, Bit 12, Center 102 (11 ~ 194) 184
5955 19:26:08.863584 iDelay=207, Bit 13, Center 100 (7 ~ 194) 188
5956 19:26:08.866579 iDelay=207, Bit 14, Center 98 (7 ~ 190) 184
5957 19:26:08.870019 iDelay=207, Bit 15, Center 100 (7 ~ 194) 188
5958 19:26:08.870439 ==
5959 19:26:08.873228 Dram Type= 6, Freq= 0, CH_1, rank 1
5960 19:26:08.876629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5961 19:26:08.877271 ==
5962 19:26:08.879648 DQS Delay:
5963 19:26:08.880148 DQS0 = 0, DQS1 = 0
5964 19:26:08.883148 DQM Delay:
5965 19:26:08.883573 DQM0 = 101, DQM1 = 93
5966 19:26:08.883910 DQ Delay:
5967 19:26:08.886364 DQ0 =106, DQ1 =94, DQ2 =92, DQ3 =98
5968 19:26:08.889685 DQ4 =98, DQ5 =110, DQ6 =114, DQ7 =98
5969 19:26:08.892743 DQ8 =82, DQ9 =84, DQ10 =96, DQ11 =84
5970 19:26:08.895775 DQ12 =102, DQ13 =100, DQ14 =98, DQ15 =100
5971 19:26:08.899489
5972 19:26:08.899570
5973 19:26:08.905910 [DQSOSCAuto] RK1, (LSB)MR18= 0x2fc, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 421 ps
5974 19:26:08.909025 CH1 RK1: MR19=504, MR18=2FC
5975 19:26:08.915927 CH1_RK1: MR19=0x504, MR18=0x2FC, DQSOSC=421, MR23=63, INC=61, DEC=40
5976 19:26:08.919053 [RxdqsGatingPostProcess] freq 933
5977 19:26:08.922149 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5978 19:26:08.925372 best DQS0 dly(2T, 0.5T) = (0, 10)
5979 19:26:08.928889 best DQS1 dly(2T, 0.5T) = (0, 10)
5980 19:26:08.932144 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5981 19:26:08.935572 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5982 19:26:08.938984 best DQS0 dly(2T, 0.5T) = (0, 10)
5983 19:26:08.942008 best DQS1 dly(2T, 0.5T) = (0, 10)
5984 19:26:08.945638 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5985 19:26:08.948534 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5986 19:26:08.952005 Pre-setting of DQS Precalculation
5987 19:26:08.954989 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5988 19:26:08.965232 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5989 19:26:08.971474 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5990 19:26:08.971556
5991 19:26:08.971620
5992 19:26:08.975133 [Calibration Summary] 1866 Mbps
5993 19:26:08.975215 CH 0, Rank 0
5994 19:26:08.978100 SW Impedance : PASS
5995 19:26:08.978182 DUTY Scan : NO K
5996 19:26:08.981751 ZQ Calibration : PASS
5997 19:26:08.984925 Jitter Meter : NO K
5998 19:26:08.985007 CBT Training : PASS
5999 19:26:08.988375 Write leveling : PASS
6000 19:26:08.991632 RX DQS gating : PASS
6001 19:26:08.991714 RX DQ/DQS(RDDQC) : PASS
6002 19:26:08.995049 TX DQ/DQS : PASS
6003 19:26:08.998168 RX DATLAT : PASS
6004 19:26:08.998249 RX DQ/DQS(Engine): PASS
6005 19:26:09.001185 TX OE : NO K
6006 19:26:09.001267 All Pass.
6007 19:26:09.001353
6008 19:26:09.004826 CH 0, Rank 1
6009 19:26:09.004907 SW Impedance : PASS
6010 19:26:09.007822 DUTY Scan : NO K
6011 19:26:09.010827 ZQ Calibration : PASS
6012 19:26:09.010912 Jitter Meter : NO K
6013 19:26:09.014680 CBT Training : PASS
6014 19:26:09.014798 Write leveling : PASS
6015 19:26:09.017608 RX DQS gating : PASS
6016 19:26:09.020710 RX DQ/DQS(RDDQC) : PASS
6017 19:26:09.020792 TX DQ/DQS : PASS
6018 19:26:09.024525 RX DATLAT : PASS
6019 19:26:09.027481 RX DQ/DQS(Engine): PASS
6020 19:26:09.027563 TX OE : NO K
6021 19:26:09.030906 All Pass.
6022 19:26:09.030987
6023 19:26:09.031051 CH 1, Rank 0
6024 19:26:09.033947 SW Impedance : PASS
6025 19:26:09.034028 DUTY Scan : NO K
6026 19:26:09.037233 ZQ Calibration : PASS
6027 19:26:09.040545 Jitter Meter : NO K
6028 19:26:09.040627 CBT Training : PASS
6029 19:26:09.043997 Write leveling : PASS
6030 19:26:09.047464 RX DQS gating : PASS
6031 19:26:09.047545 RX DQ/DQS(RDDQC) : PASS
6032 19:26:09.050328 TX DQ/DQS : PASS
6033 19:26:09.054000 RX DATLAT : PASS
6034 19:26:09.054081 RX DQ/DQS(Engine): PASS
6035 19:26:09.057076 TX OE : NO K
6036 19:26:09.057159 All Pass.
6037 19:26:09.057223
6038 19:26:09.060771 CH 1, Rank 1
6039 19:26:09.060852 SW Impedance : PASS
6040 19:26:09.063667 DUTY Scan : NO K
6041 19:26:09.067105 ZQ Calibration : PASS
6042 19:26:09.067187 Jitter Meter : NO K
6043 19:26:09.070308 CBT Training : PASS
6044 19:26:09.073530 Write leveling : PASS
6045 19:26:09.073611 RX DQS gating : PASS
6046 19:26:09.076503 RX DQ/DQS(RDDQC) : PASS
6047 19:26:09.080394 TX DQ/DQS : PASS
6048 19:26:09.080476 RX DATLAT : PASS
6049 19:26:09.083390 RX DQ/DQS(Engine): PASS
6050 19:26:09.087083 TX OE : NO K
6051 19:26:09.087166 All Pass.
6052 19:26:09.087231
6053 19:26:09.087290 DramC Write-DBI off
6054 19:26:09.090012 PER_BANK_REFRESH: Hybrid Mode
6055 19:26:09.093662 TX_TRACKING: ON
6056 19:26:09.100082 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6057 19:26:09.103388 [FAST_K] Save calibration result to emmc
6058 19:26:09.109880 dramc_set_vcore_voltage set vcore to 650000
6059 19:26:09.109961 Read voltage for 400, 6
6060 19:26:09.113006 Vio18 = 0
6061 19:26:09.113093 Vcore = 650000
6062 19:26:09.113159 Vdram = 0
6063 19:26:09.116626 Vddq = 0
6064 19:26:09.116708 Vmddr = 0
6065 19:26:09.119753 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6066 19:26:09.126658 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6067 19:26:09.129642 MEM_TYPE=3, freq_sel=20
6068 19:26:09.132784 sv_algorithm_assistance_LP4_800
6069 19:26:09.135920 ============ PULL DRAM RESETB DOWN ============
6070 19:26:09.139724 ========== PULL DRAM RESETB DOWN end =========
6071 19:26:09.146260 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6072 19:26:09.149198 ===================================
6073 19:26:09.149319 LPDDR4 DRAM CONFIGURATION
6074 19:26:09.152645 ===================================
6075 19:26:09.156076 EX_ROW_EN[0] = 0x0
6076 19:26:09.156158 EX_ROW_EN[1] = 0x0
6077 19:26:09.159147 LP4Y_EN = 0x0
6078 19:26:09.162246 WORK_FSP = 0x0
6079 19:26:09.162328 WL = 0x2
6080 19:26:09.166006 RL = 0x2
6081 19:26:09.166088 BL = 0x2
6082 19:26:09.169122 RPST = 0x0
6083 19:26:09.169203 RD_PRE = 0x0
6084 19:26:09.172060 WR_PRE = 0x1
6085 19:26:09.172143 WR_PST = 0x0
6086 19:26:09.175404 DBI_WR = 0x0
6087 19:26:09.175485 DBI_RD = 0x0
6088 19:26:09.178484 OTF = 0x1
6089 19:26:09.182224 ===================================
6090 19:26:09.185567 ===================================
6091 19:26:09.185649 ANA top config
6092 19:26:09.188610 ===================================
6093 19:26:09.191745 DLL_ASYNC_EN = 0
6094 19:26:09.195130 ALL_SLAVE_EN = 1
6095 19:26:09.198732 NEW_RANK_MODE = 1
6096 19:26:09.198814 DLL_IDLE_MODE = 1
6097 19:26:09.201811 LP45_APHY_COMB_EN = 1
6098 19:26:09.205416 TX_ODT_DIS = 1
6099 19:26:09.208436 NEW_8X_MODE = 1
6100 19:26:09.211686 ===================================
6101 19:26:09.214947 ===================================
6102 19:26:09.218260 data_rate = 800
6103 19:26:09.218341 CKR = 1
6104 19:26:09.221624 DQ_P2S_RATIO = 4
6105 19:26:09.224716 ===================================
6106 19:26:09.228438 CA_P2S_RATIO = 4
6107 19:26:09.231562 DQ_CA_OPEN = 0
6108 19:26:09.234415 DQ_SEMI_OPEN = 1
6109 19:26:09.238196 CA_SEMI_OPEN = 1
6110 19:26:09.238278 CA_FULL_RATE = 0
6111 19:26:09.241273 DQ_CKDIV4_EN = 0
6112 19:26:09.244458 CA_CKDIV4_EN = 1
6113 19:26:09.248039 CA_PREDIV_EN = 0
6114 19:26:09.251020 PH8_DLY = 0
6115 19:26:09.254722 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6116 19:26:09.254804 DQ_AAMCK_DIV = 0
6117 19:26:09.257556 CA_AAMCK_DIV = 0
6118 19:26:09.261158 CA_ADMCK_DIV = 4
6119 19:26:09.264416 DQ_TRACK_CA_EN = 0
6120 19:26:09.267829 CA_PICK = 800
6121 19:26:09.270894 CA_MCKIO = 400
6122 19:26:09.274482 MCKIO_SEMI = 400
6123 19:26:09.277628 PLL_FREQ = 3016
6124 19:26:09.277704 DQ_UI_PI_RATIO = 32
6125 19:26:09.281187 CA_UI_PI_RATIO = 32
6126 19:26:09.284115 ===================================
6127 19:26:09.287072 ===================================
6128 19:26:09.290954 memory_type:LPDDR4
6129 19:26:09.294194 GP_NUM : 10
6130 19:26:09.294288 SRAM_EN : 1
6131 19:26:09.297164 MD32_EN : 0
6132 19:26:09.300873 ===================================
6133 19:26:09.303709 [ANA_INIT] >>>>>>>>>>>>>>
6134 19:26:09.306866 <<<<<< [CONFIGURE PHASE]: ANA_TX
6135 19:26:09.310643 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6136 19:26:09.313902 ===================================
6137 19:26:09.313989 data_rate = 800,PCW = 0X7400
6138 19:26:09.316989 ===================================
6139 19:26:09.320370 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6140 19:26:09.327205 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6141 19:26:09.340407 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6142 19:26:09.343469 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6143 19:26:09.346626 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6144 19:26:09.349828 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6145 19:26:09.353556 [ANA_INIT] flow start
6146 19:26:09.353638 [ANA_INIT] PLL >>>>>>>>
6147 19:26:09.356507 [ANA_INIT] PLL <<<<<<<<
6148 19:26:09.359510 [ANA_INIT] MIDPI >>>>>>>>
6149 19:26:09.359626 [ANA_INIT] MIDPI <<<<<<<<
6150 19:26:09.363121 [ANA_INIT] DLL >>>>>>>>
6151 19:26:09.366216 [ANA_INIT] flow end
6152 19:26:09.369716 ============ LP4 DIFF to SE enter ============
6153 19:26:09.373131 ============ LP4 DIFF to SE exit ============
6154 19:26:09.376399 [ANA_INIT] <<<<<<<<<<<<<
6155 19:26:09.379289 [Flow] Enable top DCM control >>>>>
6156 19:26:09.382886 [Flow] Enable top DCM control <<<<<
6157 19:26:09.385943 Enable DLL master slave shuffle
6158 19:26:09.392556 ==============================================================
6159 19:26:09.392731 Gating Mode config
6160 19:26:09.399650 ==============================================================
6161 19:26:09.399853 Config description:
6162 19:26:09.409533 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6163 19:26:09.416381 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6164 19:26:09.422838 SELPH_MODE 0: By rank 1: By Phase
6165 19:26:09.426378 ==============================================================
6166 19:26:09.429074 GAT_TRACK_EN = 0
6167 19:26:09.432911 RX_GATING_MODE = 2
6168 19:26:09.435856 RX_GATING_TRACK_MODE = 2
6169 19:26:09.439100 SELPH_MODE = 1
6170 19:26:09.442256 PICG_EARLY_EN = 1
6171 19:26:09.445624 VALID_LAT_VALUE = 1
6172 19:26:09.452167 ==============================================================
6173 19:26:09.455336 Enter into Gating configuration >>>>
6174 19:26:09.459067 Exit from Gating configuration <<<<
6175 19:26:09.462257 Enter into DVFS_PRE_config >>>>>
6176 19:26:09.472315 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6177 19:26:09.475204 Exit from DVFS_PRE_config <<<<<
6178 19:26:09.478316 Enter into PICG configuration >>>>
6179 19:26:09.481985 Exit from PICG configuration <<<<
6180 19:26:09.485366 [RX_INPUT] configuration >>>>>
6181 19:26:09.485837 [RX_INPUT] configuration <<<<<
6182 19:26:09.491897 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6183 19:26:09.498357 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6184 19:26:09.504985 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6185 19:26:09.508179 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6186 19:26:09.514991 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6187 19:26:09.521091 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6188 19:26:09.524856 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6189 19:26:09.531381 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6190 19:26:09.534521 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6191 19:26:09.538055 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6192 19:26:09.541034 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6193 19:26:09.547692 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6194 19:26:09.551168 ===================================
6195 19:26:09.551575 LPDDR4 DRAM CONFIGURATION
6196 19:26:09.554082 ===================================
6197 19:26:09.557507 EX_ROW_EN[0] = 0x0
6198 19:26:09.560788 EX_ROW_EN[1] = 0x0
6199 19:26:09.561420 LP4Y_EN = 0x0
6200 19:26:09.563894 WORK_FSP = 0x0
6201 19:26:09.564370 WL = 0x2
6202 19:26:09.567490 RL = 0x2
6203 19:26:09.568087 BL = 0x2
6204 19:26:09.570672 RPST = 0x0
6205 19:26:09.571095 RD_PRE = 0x0
6206 19:26:09.574468 WR_PRE = 0x1
6207 19:26:09.574891 WR_PST = 0x0
6208 19:26:09.577267 DBI_WR = 0x0
6209 19:26:09.577719 DBI_RD = 0x0
6210 19:26:09.580809 OTF = 0x1
6211 19:26:09.583976 ===================================
6212 19:26:09.587076 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6213 19:26:09.590572 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6214 19:26:09.596986 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6215 19:26:09.600368 ===================================
6216 19:26:09.600794 LPDDR4 DRAM CONFIGURATION
6217 19:26:09.603812 ===================================
6218 19:26:09.606992 EX_ROW_EN[0] = 0x10
6219 19:26:09.610181 EX_ROW_EN[1] = 0x0
6220 19:26:09.610818 LP4Y_EN = 0x0
6221 19:26:09.613663 WORK_FSP = 0x0
6222 19:26:09.614168 WL = 0x2
6223 19:26:09.616878 RL = 0x2
6224 19:26:09.617306 BL = 0x2
6225 19:26:09.620448 RPST = 0x0
6226 19:26:09.620982 RD_PRE = 0x0
6227 19:26:09.623569 WR_PRE = 0x1
6228 19:26:09.624106 WR_PST = 0x0
6229 19:26:09.626635 DBI_WR = 0x0
6230 19:26:09.627258 DBI_RD = 0x0
6231 19:26:09.629846 OTF = 0x1
6232 19:26:09.633557 ===================================
6233 19:26:09.639794 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6234 19:26:09.643001 nWR fixed to 30
6235 19:26:09.646616 [ModeRegInit_LP4] CH0 RK0
6236 19:26:09.647265 [ModeRegInit_LP4] CH0 RK1
6237 19:26:09.649768 [ModeRegInit_LP4] CH1 RK0
6238 19:26:09.652794 [ModeRegInit_LP4] CH1 RK1
6239 19:26:09.653447 match AC timing 19
6240 19:26:09.659423 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6241 19:26:09.662923 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6242 19:26:09.666014 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6243 19:26:09.672667 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6244 19:26:09.676316 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6245 19:26:09.676764 ==
6246 19:26:09.679372 Dram Type= 6, Freq= 0, CH_0, rank 0
6247 19:26:09.683125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6248 19:26:09.683559 ==
6249 19:26:09.689126 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6250 19:26:09.696156 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6251 19:26:09.699218 [CA 0] Center 36 (8~64) winsize 57
6252 19:26:09.702921 [CA 1] Center 36 (8~64) winsize 57
6253 19:26:09.705921 [CA 2] Center 36 (8~64) winsize 57
6254 19:26:09.709282 [CA 3] Center 36 (8~64) winsize 57
6255 19:26:09.712133 [CA 4] Center 36 (8~64) winsize 57
6256 19:26:09.715574 [CA 5] Center 36 (8~64) winsize 57
6257 19:26:09.715998
6258 19:26:09.718876 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6259 19:26:09.719301
6260 19:26:09.722473 [CATrainingPosCal] consider 1 rank data
6261 19:26:09.726042 u2DelayCellTimex100 = 270/100 ps
6262 19:26:09.729299 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6263 19:26:09.732607 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6264 19:26:09.735752 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6265 19:26:09.738899 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6266 19:26:09.742205 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6267 19:26:09.745251 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6268 19:26:09.745837
6269 19:26:09.752308 CA PerBit enable=1, Macro0, CA PI delay=36
6270 19:26:09.752805
6271 19:26:09.753405 [CBTSetCACLKResult] CA Dly = 36
6272 19:26:09.755159 CS Dly: 1 (0~32)
6273 19:26:09.755585 ==
6274 19:26:09.758943 Dram Type= 6, Freq= 0, CH_0, rank 1
6275 19:26:09.762038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6276 19:26:09.762472 ==
6277 19:26:09.768781 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6278 19:26:09.775028 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6279 19:26:09.778170 [CA 0] Center 36 (8~64) winsize 57
6280 19:26:09.781940 [CA 1] Center 36 (8~64) winsize 57
6281 19:26:09.785067 [CA 2] Center 36 (8~64) winsize 57
6282 19:26:09.788212 [CA 3] Center 36 (8~64) winsize 57
6283 19:26:09.788662 [CA 4] Center 36 (8~64) winsize 57
6284 19:26:09.791773 [CA 5] Center 36 (8~64) winsize 57
6285 19:26:09.792355
6286 19:26:09.798236 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6287 19:26:09.798753
6288 19:26:09.801107 [CATrainingPosCal] consider 2 rank data
6289 19:26:09.804814 u2DelayCellTimex100 = 270/100 ps
6290 19:26:09.808100 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6291 19:26:09.811656 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6292 19:26:09.814493 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6293 19:26:09.817836 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6294 19:26:09.820737 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6295 19:26:09.824427 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6296 19:26:09.824986
6297 19:26:09.827488 CA PerBit enable=1, Macro0, CA PI delay=36
6298 19:26:09.828131
6299 19:26:09.830956 [CBTSetCACLKResult] CA Dly = 36
6300 19:26:09.833946 CS Dly: 1 (0~32)
6301 19:26:09.834407
6302 19:26:09.837448 ----->DramcWriteLeveling(PI) begin...
6303 19:26:09.837908 ==
6304 19:26:09.840633 Dram Type= 6, Freq= 0, CH_0, rank 0
6305 19:26:09.843873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6306 19:26:09.844181 ==
6307 19:26:09.847776 Write leveling (Byte 0): 40 => 8
6308 19:26:09.850640 Write leveling (Byte 1): 32 => 0
6309 19:26:09.854383 DramcWriteLeveling(PI) end<-----
6310 19:26:09.854687
6311 19:26:09.854927 ==
6312 19:26:09.857362 Dram Type= 6, Freq= 0, CH_0, rank 0
6313 19:26:09.860364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6314 19:26:09.860668 ==
6315 19:26:09.864269 [Gating] SW mode calibration
6316 19:26:09.870513 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6317 19:26:09.877406 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6318 19:26:09.880811 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6319 19:26:09.887382 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6320 19:26:09.890483 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6321 19:26:09.893582 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6322 19:26:09.900371 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6323 19:26:09.904032 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6324 19:26:09.907132 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6325 19:26:09.913896 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6326 19:26:09.917027 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6327 19:26:09.919840 Total UI for P1: 0, mck2ui 16
6328 19:26:09.923440 best dqsien dly found for B0: ( 0, 14, 24)
6329 19:26:09.926642 Total UI for P1: 0, mck2ui 16
6330 19:26:09.930252 best dqsien dly found for B1: ( 0, 14, 24)
6331 19:26:09.933134 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6332 19:26:09.936693 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6333 19:26:09.937138
6334 19:26:09.939779 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6335 19:26:09.943431 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6336 19:26:09.946453 [Gating] SW calibration Done
6337 19:26:09.946878 ==
6338 19:26:09.949837 Dram Type= 6, Freq= 0, CH_0, rank 0
6339 19:26:09.956454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6340 19:26:09.956888 ==
6341 19:26:09.957226 RX Vref Scan: 0
6342 19:26:09.957623
6343 19:26:09.959718 RX Vref 0 -> 0, step: 1
6344 19:26:09.960173
6345 19:26:09.962833 RX Delay -410 -> 252, step: 16
6346 19:26:09.966489 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6347 19:26:09.969560 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6348 19:26:09.975716 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6349 19:26:09.979138 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6350 19:26:09.982269 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6351 19:26:09.985302 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6352 19:26:09.992089 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6353 19:26:09.995172 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6354 19:26:09.998377 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6355 19:26:10.002092 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6356 19:26:10.009035 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6357 19:26:10.012359 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6358 19:26:10.015081 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6359 19:26:10.018604 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6360 19:26:10.025085 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6361 19:26:10.028817 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6362 19:26:10.028966 ==
6363 19:26:10.031969 Dram Type= 6, Freq= 0, CH_0, rank 0
6364 19:26:10.035188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6365 19:26:10.035313 ==
6366 19:26:10.038467 DQS Delay:
6367 19:26:10.038613 DQS0 = 43, DQS1 = 59
6368 19:26:10.041975 DQM Delay:
6369 19:26:10.042123 DQM0 = 10, DQM1 = 14
6370 19:26:10.044717 DQ Delay:
6371 19:26:10.044807 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6372 19:26:10.047849 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6373 19:26:10.051459 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6374 19:26:10.054699 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6375 19:26:10.054791
6376 19:26:10.054861
6377 19:26:10.054925 ==
6378 19:26:10.057956 Dram Type= 6, Freq= 0, CH_0, rank 0
6379 19:26:10.064747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6380 19:26:10.064843 ==
6381 19:26:10.064918
6382 19:26:10.065004
6383 19:26:10.067439 TX Vref Scan disable
6384 19:26:10.067534 == TX Byte 0 ==
6385 19:26:10.071112 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6386 19:26:10.077590 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6387 19:26:10.077685 == TX Byte 1 ==
6388 19:26:10.080667 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6389 19:26:10.087577 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6390 19:26:10.087672 ==
6391 19:26:10.090738 Dram Type= 6, Freq= 0, CH_0, rank 0
6392 19:26:10.093810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6393 19:26:10.093922 ==
6394 19:26:10.094011
6395 19:26:10.094095
6396 19:26:10.097180 TX Vref Scan disable
6397 19:26:10.097291 == TX Byte 0 ==
6398 19:26:10.103748 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6399 19:26:10.106892 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6400 19:26:10.107028 == TX Byte 1 ==
6401 19:26:10.113947 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6402 19:26:10.116873 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6403 19:26:10.116955
6404 19:26:10.117019 [DATLAT]
6405 19:26:10.120162 Freq=400, CH0 RK0
6406 19:26:10.120244
6407 19:26:10.120309 DATLAT Default: 0xf
6408 19:26:10.123539 0, 0xFFFF, sum = 0
6409 19:26:10.123640 1, 0xFFFF, sum = 0
6410 19:26:10.126938 2, 0xFFFF, sum = 0
6411 19:26:10.127021 3, 0xFFFF, sum = 0
6412 19:26:10.130059 4, 0xFFFF, sum = 0
6413 19:26:10.130143 5, 0xFFFF, sum = 0
6414 19:26:10.133316 6, 0xFFFF, sum = 0
6415 19:26:10.133422 7, 0xFFFF, sum = 0
6416 19:26:10.136527 8, 0xFFFF, sum = 0
6417 19:26:10.140293 9, 0xFFFF, sum = 0
6418 19:26:10.140377 10, 0xFFFF, sum = 0
6419 19:26:10.143210 11, 0xFFFF, sum = 0
6420 19:26:10.143293 12, 0xFFFF, sum = 0
6421 19:26:10.146197 13, 0x0, sum = 1
6422 19:26:10.146281 14, 0x0, sum = 2
6423 19:26:10.149744 15, 0x0, sum = 3
6424 19:26:10.149828 16, 0x0, sum = 4
6425 19:26:10.149894 best_step = 14
6426 19:26:10.152888
6427 19:26:10.152976 ==
6428 19:26:10.156709 Dram Type= 6, Freq= 0, CH_0, rank 0
6429 19:26:10.159715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6430 19:26:10.159799 ==
6431 19:26:10.159868 RX Vref Scan: 1
6432 19:26:10.159934
6433 19:26:10.162966 RX Vref 0 -> 0, step: 1
6434 19:26:10.163065
6435 19:26:10.166984 RX Delay -359 -> 252, step: 8
6436 19:26:10.167154
6437 19:26:10.169693 Set Vref, RX VrefLevel [Byte0]: 57
6438 19:26:10.172913 [Byte1]: 48
6439 19:26:10.177233
6440 19:26:10.177454 Final RX Vref Byte 0 = 57 to rank0
6441 19:26:10.180683 Final RX Vref Byte 1 = 48 to rank0
6442 19:26:10.183324 Final RX Vref Byte 0 = 57 to rank1
6443 19:26:10.186594 Final RX Vref Byte 1 = 48 to rank1==
6444 19:26:10.189941 Dram Type= 6, Freq= 0, CH_0, rank 0
6445 19:26:10.196933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6446 19:26:10.197109 ==
6447 19:26:10.197249 DQS Delay:
6448 19:26:10.200152 DQS0 = 48, DQS1 = 60
6449 19:26:10.200356 DQM Delay:
6450 19:26:10.200515 DQM0 = 12, DQM1 = 12
6451 19:26:10.203662 DQ Delay:
6452 19:26:10.206390 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =12
6453 19:26:10.209712 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6454 19:26:10.213301 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6455 19:26:10.216669 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6456 19:26:10.217059
6457 19:26:10.217399
6458 19:26:10.223486 [DQSOSCAuto] RK0, (LSB)MR18= 0xbb80, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 386 ps
6459 19:26:10.226571 CH0 RK0: MR19=C0C, MR18=BB80
6460 19:26:10.233407 CH0_RK0: MR19=0xC0C, MR18=0xBB80, DQSOSC=386, MR23=63, INC=396, DEC=264
6461 19:26:10.233838 ==
6462 19:26:10.236737 Dram Type= 6, Freq= 0, CH_0, rank 1
6463 19:26:10.240253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6464 19:26:10.240683 ==
6465 19:26:10.243354 [Gating] SW mode calibration
6466 19:26:10.250060 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6467 19:26:10.256230 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6468 19:26:10.259927 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6469 19:26:10.263368 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6470 19:26:10.269689 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6471 19:26:10.272747 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6472 19:26:10.275909 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6473 19:26:10.282830 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6474 19:26:10.285871 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6475 19:26:10.289379 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6476 19:26:10.295612 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6477 19:26:10.299001 Total UI for P1: 0, mck2ui 16
6478 19:26:10.302362 best dqsien dly found for B0: ( 0, 14, 24)
6479 19:26:10.305958 Total UI for P1: 0, mck2ui 16
6480 19:26:10.309107 best dqsien dly found for B1: ( 0, 14, 24)
6481 19:26:10.312190 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6482 19:26:10.315547 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6483 19:26:10.315977
6484 19:26:10.318996 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6485 19:26:10.322035 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6486 19:26:10.325601 [Gating] SW calibration Done
6487 19:26:10.326029 ==
6488 19:26:10.328720 Dram Type= 6, Freq= 0, CH_0, rank 1
6489 19:26:10.332453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6490 19:26:10.332997 ==
6491 19:26:10.335369 RX Vref Scan: 0
6492 19:26:10.335804
6493 19:26:10.338604 RX Vref 0 -> 0, step: 1
6494 19:26:10.339069
6495 19:26:10.339421 RX Delay -410 -> 252, step: 16
6496 19:26:10.345645 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6497 19:26:10.349114 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6498 19:26:10.352348 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6499 19:26:10.358833 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6500 19:26:10.362146 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6501 19:26:10.365064 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6502 19:26:10.368855 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6503 19:26:10.375041 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6504 19:26:10.378079 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6505 19:26:10.381891 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6506 19:26:10.384893 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6507 19:26:10.391828 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6508 19:26:10.394951 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6509 19:26:10.397980 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6510 19:26:10.401636 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6511 19:26:10.408275 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6512 19:26:10.408820 ==
6513 19:26:10.411398 Dram Type= 6, Freq= 0, CH_0, rank 1
6514 19:26:10.414658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6515 19:26:10.415192 ==
6516 19:26:10.417650 DQS Delay:
6517 19:26:10.418080 DQS0 = 43, DQS1 = 59
6518 19:26:10.418421 DQM Delay:
6519 19:26:10.421062 DQM0 = 10, DQM1 = 16
6520 19:26:10.421526 DQ Delay:
6521 19:26:10.424741 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6522 19:26:10.427711 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6523 19:26:10.430929 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6524 19:26:10.434430 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6525 19:26:10.435071
6526 19:26:10.435428
6527 19:26:10.435751 ==
6528 19:26:10.437723 Dram Type= 6, Freq= 0, CH_0, rank 1
6529 19:26:10.440832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6530 19:26:10.443981 ==
6531 19:26:10.444408
6532 19:26:10.444745
6533 19:26:10.445055 TX Vref Scan disable
6534 19:26:10.447762 == TX Byte 0 ==
6535 19:26:10.450942 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6536 19:26:10.454481 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6537 19:26:10.457604 == TX Byte 1 ==
6538 19:26:10.460641 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6539 19:26:10.464078 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6540 19:26:10.464598 ==
6541 19:26:10.467117 Dram Type= 6, Freq= 0, CH_0, rank 1
6542 19:26:10.474267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6543 19:26:10.474771 ==
6544 19:26:10.475257
6545 19:26:10.475715
6546 19:26:10.476175 TX Vref Scan disable
6547 19:26:10.476929 == TX Byte 0 ==
6548 19:26:10.480737 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6549 19:26:10.483749 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6550 19:26:10.486836 == TX Byte 1 ==
6551 19:26:10.490630 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6552 19:26:10.493854 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6553 19:26:10.494279
6554 19:26:10.496773 [DATLAT]
6555 19:26:10.497247 Freq=400, CH0 RK1
6556 19:26:10.497655
6557 19:26:10.500681 DATLAT Default: 0xe
6558 19:26:10.501229 0, 0xFFFF, sum = 0
6559 19:26:10.503578 1, 0xFFFF, sum = 0
6560 19:26:10.504023 2, 0xFFFF, sum = 0
6561 19:26:10.507435 3, 0xFFFF, sum = 0
6562 19:26:10.507964 4, 0xFFFF, sum = 0
6563 19:26:10.510154 5, 0xFFFF, sum = 0
6564 19:26:10.510604 6, 0xFFFF, sum = 0
6565 19:26:10.513855 7, 0xFFFF, sum = 0
6566 19:26:10.514315 8, 0xFFFF, sum = 0
6567 19:26:10.516784 9, 0xFFFF, sum = 0
6568 19:26:10.517240 10, 0xFFFF, sum = 0
6569 19:26:10.519861 11, 0xFFFF, sum = 0
6570 19:26:10.523632 12, 0xFFFF, sum = 0
6571 19:26:10.524069 13, 0x0, sum = 1
6572 19:26:10.526466 14, 0x0, sum = 2
6573 19:26:10.526995 15, 0x0, sum = 3
6574 19:26:10.527354 16, 0x0, sum = 4
6575 19:26:10.529838 best_step = 14
6576 19:26:10.530269
6577 19:26:10.530672 ==
6578 19:26:10.533216 Dram Type= 6, Freq= 0, CH_0, rank 1
6579 19:26:10.536671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6580 19:26:10.537100 ==
6581 19:26:10.540093 RX Vref Scan: 0
6582 19:26:10.540518
6583 19:26:10.540852 RX Vref 0 -> 0, step: 1
6584 19:26:10.543652
6585 19:26:10.544174 RX Delay -359 -> 252, step: 8
6586 19:26:10.552015 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6587 19:26:10.555142 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6588 19:26:10.558218 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6589 19:26:10.564744 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6590 19:26:10.567912 iDelay=217, Bit 4, Center -32 (-271 ~ 208) 480
6591 19:26:10.571322 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6592 19:26:10.574257 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6593 19:26:10.580832 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6594 19:26:10.584294 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6595 19:26:10.587555 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6596 19:26:10.590689 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6597 19:26:10.597549 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6598 19:26:10.600710 iDelay=217, Bit 12, Center -36 (-279 ~ 208) 488
6599 19:26:10.604311 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6600 19:26:10.607363 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6601 19:26:10.614276 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6602 19:26:10.614360 ==
6603 19:26:10.617122 Dram Type= 6, Freq= 0, CH_0, rank 1
6604 19:26:10.620936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6605 19:26:10.621020 ==
6606 19:26:10.621086 DQS Delay:
6607 19:26:10.624121 DQS0 = 44, DQS1 = 60
6608 19:26:10.624204 DQM Delay:
6609 19:26:10.627238 DQM0 = 9, DQM1 = 16
6610 19:26:10.627321 DQ Delay:
6611 19:26:10.630243 DQ0 =4, DQ1 =12, DQ2 =4, DQ3 =8
6612 19:26:10.634032 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6613 19:26:10.636711 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6614 19:26:10.640469 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6615 19:26:10.640918
6616 19:26:10.641258
6617 19:26:10.650609 [DQSOSCAuto] RK1, (LSB)MR18= 0xab39, (MSB)MR19= 0xc0c, tDQSOscB0 = 402 ps tDQSOscB1 = 388 ps
6618 19:26:10.651128 CH0 RK1: MR19=C0C, MR18=AB39
6619 19:26:10.657257 CH0_RK1: MR19=0xC0C, MR18=0xAB39, DQSOSC=388, MR23=63, INC=392, DEC=261
6620 19:26:10.660282 [RxdqsGatingPostProcess] freq 400
6621 19:26:10.667117 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6622 19:26:10.670246 best DQS0 dly(2T, 0.5T) = (0, 10)
6623 19:26:10.673701 best DQS1 dly(2T, 0.5T) = (0, 10)
6624 19:26:10.676710 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6625 19:26:10.680022 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6626 19:26:10.683793 best DQS0 dly(2T, 0.5T) = (0, 10)
6627 19:26:10.684394 best DQS1 dly(2T, 0.5T) = (0, 10)
6628 19:26:10.686571 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6629 19:26:10.690286 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6630 19:26:10.693191 Pre-setting of DQS Precalculation
6631 19:26:10.699990 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6632 19:26:10.700556 ==
6633 19:26:10.703175 Dram Type= 6, Freq= 0, CH_1, rank 0
6634 19:26:10.706860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6635 19:26:10.707297 ==
6636 19:26:10.712877 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6637 19:26:10.720049 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6638 19:26:10.723027 [CA 0] Center 36 (8~64) winsize 57
6639 19:26:10.726217 [CA 1] Center 36 (8~64) winsize 57
6640 19:26:10.729293 [CA 2] Center 36 (8~64) winsize 57
6641 19:26:10.733025 [CA 3] Center 36 (8~64) winsize 57
6642 19:26:10.733508 [CA 4] Center 36 (8~64) winsize 57
6643 19:26:10.736208 [CA 5] Center 36 (8~64) winsize 57
6644 19:26:10.736637
6645 19:26:10.742586 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6646 19:26:10.743077
6647 19:26:10.746219 [CATrainingPosCal] consider 1 rank data
6648 19:26:10.749418 u2DelayCellTimex100 = 270/100 ps
6649 19:26:10.752701 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6650 19:26:10.755902 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6651 19:26:10.759379 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6652 19:26:10.762742 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6653 19:26:10.766078 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6654 19:26:10.769127 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6655 19:26:10.769610
6656 19:26:10.772078 CA PerBit enable=1, Macro0, CA PI delay=36
6657 19:26:10.772507
6658 19:26:10.776098 [CBTSetCACLKResult] CA Dly = 36
6659 19:26:10.778878 CS Dly: 1 (0~32)
6660 19:26:10.779357 ==
6661 19:26:10.782303 Dram Type= 6, Freq= 0, CH_1, rank 1
6662 19:26:10.785213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6663 19:26:10.785787 ==
6664 19:26:10.792354 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6665 19:26:10.798642 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6666 19:26:10.801707 [CA 0] Center 36 (8~64) winsize 57
6667 19:26:10.805394 [CA 1] Center 36 (8~64) winsize 57
6668 19:26:10.808464 [CA 2] Center 36 (8~64) winsize 57
6669 19:26:10.808894 [CA 3] Center 36 (8~64) winsize 57
6670 19:26:10.811620 [CA 4] Center 36 (8~64) winsize 57
6671 19:26:10.815227 [CA 5] Center 36 (8~64) winsize 57
6672 19:26:10.815659
6673 19:26:10.821915 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6674 19:26:10.822347
6675 19:26:10.824919 [CATrainingPosCal] consider 2 rank data
6676 19:26:10.828002 u2DelayCellTimex100 = 270/100 ps
6677 19:26:10.831852 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6678 19:26:10.834916 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6679 19:26:10.837941 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6680 19:26:10.841715 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6681 19:26:10.845047 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6682 19:26:10.847904 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6683 19:26:10.848331
6684 19:26:10.851668 CA PerBit enable=1, Macro0, CA PI delay=36
6685 19:26:10.852097
6686 19:26:10.854585 [CBTSetCACLKResult] CA Dly = 36
6687 19:26:10.858046 CS Dly: 1 (0~32)
6688 19:26:10.858476
6689 19:26:10.861384 ----->DramcWriteLeveling(PI) begin...
6690 19:26:10.861821 ==
6691 19:26:10.864258 Dram Type= 6, Freq= 0, CH_1, rank 0
6692 19:26:10.868028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6693 19:26:10.868461 ==
6694 19:26:10.871056 Write leveling (Byte 0): 40 => 8
6695 19:26:10.874234 Write leveling (Byte 1): 32 => 0
6696 19:26:10.877962 DramcWriteLeveling(PI) end<-----
6697 19:26:10.878391
6698 19:26:10.878727 ==
6699 19:26:10.881021 Dram Type= 6, Freq= 0, CH_1, rank 0
6700 19:26:10.884163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6701 19:26:10.884591 ==
6702 19:26:10.887734 [Gating] SW mode calibration
6703 19:26:10.894301 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6704 19:26:10.900471 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6705 19:26:10.903533 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6706 19:26:10.910563 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6707 19:26:10.913552 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6708 19:26:10.917208 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6709 19:26:10.923648 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6710 19:26:10.926609 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6711 19:26:10.930008 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6712 19:26:10.936694 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6713 19:26:10.939502 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6714 19:26:10.943126 Total UI for P1: 0, mck2ui 16
6715 19:26:10.946313 best dqsien dly found for B0: ( 0, 14, 24)
6716 19:26:10.949790 Total UI for P1: 0, mck2ui 16
6717 19:26:10.952784 best dqsien dly found for B1: ( 0, 14, 24)
6718 19:26:10.955948 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6719 19:26:10.959596 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6720 19:26:10.959707
6721 19:26:10.962611 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6722 19:26:10.966074 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6723 19:26:10.969053 [Gating] SW calibration Done
6724 19:26:10.969159 ==
6725 19:26:10.972203 Dram Type= 6, Freq= 0, CH_1, rank 0
6726 19:26:10.979082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6727 19:26:10.979197 ==
6728 19:26:10.979293 RX Vref Scan: 0
6729 19:26:10.979386
6730 19:26:10.982612 RX Vref 0 -> 0, step: 1
6731 19:26:10.982695
6732 19:26:10.985766 RX Delay -410 -> 252, step: 16
6733 19:26:10.988769 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6734 19:26:10.992525 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6735 19:26:10.998658 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6736 19:26:11.002349 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6737 19:26:11.006033 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6738 19:26:11.008874 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6739 19:26:11.015244 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6740 19:26:11.018762 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6741 19:26:11.021952 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6742 19:26:11.025321 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6743 19:26:11.032066 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6744 19:26:11.035159 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6745 19:26:11.038245 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6746 19:26:11.045224 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6747 19:26:11.048274 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6748 19:26:11.051301 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6749 19:26:11.051385 ==
6750 19:26:11.054999 Dram Type= 6, Freq= 0, CH_1, rank 0
6751 19:26:11.057980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6752 19:26:11.058065 ==
6753 19:26:11.061729 DQS Delay:
6754 19:26:11.061812 DQS0 = 43, DQS1 = 51
6755 19:26:11.064870 DQM Delay:
6756 19:26:11.064946 DQM0 = 12, DQM1 = 14
6757 19:26:11.067967 DQ Delay:
6758 19:26:11.068050 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6759 19:26:11.071443 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6760 19:26:11.074728 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6761 19:26:11.077703 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6762 19:26:11.077787
6763 19:26:11.077853
6764 19:26:11.077928 ==
6765 19:26:11.081415 Dram Type= 6, Freq= 0, CH_1, rank 0
6766 19:26:11.087516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6767 19:26:11.087601 ==
6768 19:26:11.087667
6769 19:26:11.087728
6770 19:26:11.091041 TX Vref Scan disable
6771 19:26:11.091124 == TX Byte 0 ==
6772 19:26:11.094469 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6773 19:26:11.100579 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6774 19:26:11.100664 == TX Byte 1 ==
6775 19:26:11.104363 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6776 19:26:11.110701 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6777 19:26:11.110787 ==
6778 19:26:11.114147 Dram Type= 6, Freq= 0, CH_1, rank 0
6779 19:26:11.117137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6780 19:26:11.117220 ==
6781 19:26:11.117287
6782 19:26:11.117390
6783 19:26:11.120737 TX Vref Scan disable
6784 19:26:11.120820 == TX Byte 0 ==
6785 19:26:11.123783 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6786 19:26:11.130577 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6787 19:26:11.130661 == TX Byte 1 ==
6788 19:26:11.133710 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6789 19:26:11.140338 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6790 19:26:11.140422
6791 19:26:11.140488 [DATLAT]
6792 19:26:11.143436 Freq=400, CH1 RK0
6793 19:26:11.143519
6794 19:26:11.143585 DATLAT Default: 0xf
6795 19:26:11.147122 0, 0xFFFF, sum = 0
6796 19:26:11.147206 1, 0xFFFF, sum = 0
6797 19:26:11.150180 2, 0xFFFF, sum = 0
6798 19:26:11.150264 3, 0xFFFF, sum = 0
6799 19:26:11.153292 4, 0xFFFF, sum = 0
6800 19:26:11.153416 5, 0xFFFF, sum = 0
6801 19:26:11.156903 6, 0xFFFF, sum = 0
6802 19:26:11.156993 7, 0xFFFF, sum = 0
6803 19:26:11.159973 8, 0xFFFF, sum = 0
6804 19:26:11.160057 9, 0xFFFF, sum = 0
6805 19:26:11.163554 10, 0xFFFF, sum = 0
6806 19:26:11.163638 11, 0xFFFF, sum = 0
6807 19:26:11.166668 12, 0xFFFF, sum = 0
6808 19:26:11.166753 13, 0x0, sum = 1
6809 19:26:11.170369 14, 0x0, sum = 2
6810 19:26:11.170454 15, 0x0, sum = 3
6811 19:26:11.173546 16, 0x0, sum = 4
6812 19:26:11.173630 best_step = 14
6813 19:26:11.173696
6814 19:26:11.173757 ==
6815 19:26:11.176584 Dram Type= 6, Freq= 0, CH_1, rank 0
6816 19:26:11.183471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6817 19:26:11.183578 ==
6818 19:26:11.183645 RX Vref Scan: 1
6819 19:26:11.183707
6820 19:26:11.186499 RX Vref 0 -> 0, step: 1
6821 19:26:11.186582
6822 19:26:11.190194 RX Delay -343 -> 252, step: 8
6823 19:26:11.190277
6824 19:26:11.193298 Set Vref, RX VrefLevel [Byte0]: 48
6825 19:26:11.196349 [Byte1]: 53
6826 19:26:11.199863
6827 19:26:11.199951 Final RX Vref Byte 0 = 48 to rank0
6828 19:26:11.203079 Final RX Vref Byte 1 = 53 to rank0
6829 19:26:11.206663 Final RX Vref Byte 0 = 48 to rank1
6830 19:26:11.209621 Final RX Vref Byte 1 = 53 to rank1==
6831 19:26:11.213287 Dram Type= 6, Freq= 0, CH_1, rank 0
6832 19:26:11.219371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6833 19:26:11.219485 ==
6834 19:26:11.219554 DQS Delay:
6835 19:26:11.222808 DQS0 = 44, DQS1 = 56
6836 19:26:11.222890 DQM Delay:
6837 19:26:11.222956 DQM0 = 8, DQM1 = 12
6838 19:26:11.225801 DQ Delay:
6839 19:26:11.229604 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6840 19:26:11.232356 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =4
6841 19:26:11.232442 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6842 19:26:11.239217 DQ12 =24, DQ13 =20, DQ14 =16, DQ15 =20
6843 19:26:11.239301
6844 19:26:11.239367
6845 19:26:11.245814 [DQSOSCAuto] RK0, (LSB)MR18= 0x9369, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 391 ps
6846 19:26:11.248839 CH1 RK0: MR19=C0C, MR18=9369
6847 19:26:11.255640 CH1_RK0: MR19=0xC0C, MR18=0x9369, DQSOSC=391, MR23=63, INC=386, DEC=257
6848 19:26:11.255721 ==
6849 19:26:11.258747 Dram Type= 6, Freq= 0, CH_1, rank 1
6850 19:26:11.262302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6851 19:26:11.262407 ==
6852 19:26:11.265225 [Gating] SW mode calibration
6853 19:26:11.272293 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6854 19:26:11.278642 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6855 19:26:11.281657 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6856 19:26:11.285220 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6857 19:26:11.291586 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6858 19:26:11.294894 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6859 19:26:11.298490 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6860 19:26:11.304672 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6861 19:26:11.307950 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6862 19:26:11.315102 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6863 19:26:11.318382 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6864 19:26:11.321241 Total UI for P1: 0, mck2ui 16
6865 19:26:11.324658 best dqsien dly found for B0: ( 0, 14, 24)
6866 19:26:11.327656 Total UI for P1: 0, mck2ui 16
6867 19:26:11.331114 best dqsien dly found for B1: ( 0, 14, 24)
6868 19:26:11.334377 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6869 19:26:11.337930 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6870 19:26:11.338039
6871 19:26:11.341152 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6872 19:26:11.344023 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6873 19:26:11.347452 [Gating] SW calibration Done
6874 19:26:11.347539 ==
6875 19:26:11.350821 Dram Type= 6, Freq= 0, CH_1, rank 1
6876 19:26:11.354114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6877 19:26:11.357721 ==
6878 19:26:11.357833 RX Vref Scan: 0
6879 19:26:11.357927
6880 19:26:11.361035 RX Vref 0 -> 0, step: 1
6881 19:26:11.361133
6882 19:26:11.363903 RX Delay -410 -> 252, step: 16
6883 19:26:11.367436 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6884 19:26:11.370495 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6885 19:26:11.374220 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6886 19:26:11.380350 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6887 19:26:11.383785 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6888 19:26:11.387418 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6889 19:26:11.390628 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6890 19:26:11.397338 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6891 19:26:11.400427 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6892 19:26:11.403490 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6893 19:26:11.406807 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6894 19:26:11.413589 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6895 19:26:11.417107 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6896 19:26:11.420202 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6897 19:26:11.426788 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6898 19:26:11.430516 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6899 19:26:11.430631 ==
6900 19:26:11.433789 Dram Type= 6, Freq= 0, CH_1, rank 1
6901 19:26:11.436588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6902 19:26:11.436702 ==
6903 19:26:11.440345 DQS Delay:
6904 19:26:11.440475 DQS0 = 51, DQS1 = 51
6905 19:26:11.440575 DQM Delay:
6906 19:26:11.443343 DQM0 = 19, DQM1 = 14
6907 19:26:11.443475 DQ Delay:
6908 19:26:11.447269 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6909 19:26:11.450428 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6910 19:26:11.453548 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6911 19:26:11.456803 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6912 19:26:11.457371
6913 19:26:11.457942
6914 19:26:11.458287 ==
6915 19:26:11.460047 Dram Type= 6, Freq= 0, CH_1, rank 1
6916 19:26:11.466893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6917 19:26:11.467326 ==
6918 19:26:11.467669
6919 19:26:11.467985
6920 19:26:11.468282 TX Vref Scan disable
6921 19:26:11.469880 == TX Byte 0 ==
6922 19:26:11.473265 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6923 19:26:11.476268 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6924 19:26:11.480060 == TX Byte 1 ==
6925 19:26:11.483202 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6926 19:26:11.486389 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6927 19:26:11.486821 ==
6928 19:26:11.489949 Dram Type= 6, Freq= 0, CH_1, rank 1
6929 19:26:11.496409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6930 19:26:11.496521 ==
6931 19:26:11.496591
6932 19:26:11.496672
6933 19:26:11.496761 TX Vref Scan disable
6934 19:26:11.499541 == TX Byte 0 ==
6935 19:26:11.502639 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6936 19:26:11.505734 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6937 19:26:11.509455 == TX Byte 1 ==
6938 19:26:11.512508 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6939 19:26:11.516341 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6940 19:26:11.516425
6941 19:26:11.519289 [DATLAT]
6942 19:26:11.519372 Freq=400, CH1 RK1
6943 19:26:11.519439
6944 19:26:11.522383 DATLAT Default: 0xe
6945 19:26:11.522466 0, 0xFFFF, sum = 0
6946 19:26:11.525700 1, 0xFFFF, sum = 0
6947 19:26:11.525785 2, 0xFFFF, sum = 0
6948 19:26:11.529297 3, 0xFFFF, sum = 0
6949 19:26:11.529422 4, 0xFFFF, sum = 0
6950 19:26:11.532174 5, 0xFFFF, sum = 0
6951 19:26:11.532258 6, 0xFFFF, sum = 0
6952 19:26:11.535444 7, 0xFFFF, sum = 0
6953 19:26:11.538696 8, 0xFFFF, sum = 0
6954 19:26:11.538816 9, 0xFFFF, sum = 0
6955 19:26:11.542206 10, 0xFFFF, sum = 0
6956 19:26:11.542290 11, 0xFFFF, sum = 0
6957 19:26:11.545478 12, 0xFFFF, sum = 0
6958 19:26:11.545562 13, 0x0, sum = 1
6959 19:26:11.548872 14, 0x0, sum = 2
6960 19:26:11.548969 15, 0x0, sum = 3
6961 19:26:11.552372 16, 0x0, sum = 4
6962 19:26:11.552457 best_step = 14
6963 19:26:11.552524
6964 19:26:11.552585 ==
6965 19:26:11.555359 Dram Type= 6, Freq= 0, CH_1, rank 1
6966 19:26:11.559097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6967 19:26:11.559181 ==
6968 19:26:11.562324 RX Vref Scan: 0
6969 19:26:11.562406
6970 19:26:11.565161 RX Vref 0 -> 0, step: 1
6971 19:26:11.565243
6972 19:26:11.565308 RX Delay -343 -> 252, step: 8
6973 19:26:11.574402 iDelay=225, Bit 0, Center -32 (-271 ~ 208) 480
6974 19:26:11.577777 iDelay=225, Bit 1, Center -40 (-279 ~ 200) 480
6975 19:26:11.580786 iDelay=225, Bit 2, Center -48 (-287 ~ 192) 480
6976 19:26:11.587360 iDelay=225, Bit 3, Center -40 (-279 ~ 200) 480
6977 19:26:11.590477 iDelay=225, Bit 4, Center -36 (-279 ~ 208) 488
6978 19:26:11.594180 iDelay=225, Bit 5, Center -24 (-263 ~ 216) 480
6979 19:26:11.596999 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
6980 19:26:11.603624 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
6981 19:26:11.606793 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
6982 19:26:11.610582 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
6983 19:26:11.613531 iDelay=225, Bit 10, Center -40 (-287 ~ 208) 496
6984 19:26:11.620208 iDelay=225, Bit 11, Center -52 (-295 ~ 192) 488
6985 19:26:11.623363 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
6986 19:26:11.627089 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
6987 19:26:11.633337 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
6988 19:26:11.636558 iDelay=225, Bit 15, Center -32 (-279 ~ 216) 496
6989 19:26:11.636642 ==
6990 19:26:11.639557 Dram Type= 6, Freq= 0, CH_1, rank 1
6991 19:26:11.643157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6992 19:26:11.643241 ==
6993 19:26:11.646460 DQS Delay:
6994 19:26:11.646543 DQS0 = 48, DQS1 = 56
6995 19:26:11.646609 DQM Delay:
6996 19:26:11.649350 DQM0 = 12, DQM1 = 12
6997 19:26:11.649448 DQ Delay:
6998 19:26:11.652803 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6999 19:26:11.656098 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
7000 19:26:11.659416 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
7001 19:26:11.662807 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =24
7002 19:26:11.662891
7003 19:26:11.662957
7004 19:26:11.672625 [DQSOSCAuto] RK1, (LSB)MR18= 0x6655, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 396 ps
7005 19:26:11.672711 CH1 RK1: MR19=C0C, MR18=6655
7006 19:26:11.679135 CH1_RK1: MR19=0xC0C, MR18=0x6655, DQSOSC=396, MR23=63, INC=376, DEC=251
7007 19:26:11.682607 [RxdqsGatingPostProcess] freq 400
7008 19:26:11.689110 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7009 19:26:11.692382 best DQS0 dly(2T, 0.5T) = (0, 10)
7010 19:26:11.695484 best DQS1 dly(2T, 0.5T) = (0, 10)
7011 19:26:11.699082 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7012 19:26:11.702012 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7013 19:26:11.705507 best DQS0 dly(2T, 0.5T) = (0, 10)
7014 19:26:11.708512 best DQS1 dly(2T, 0.5T) = (0, 10)
7015 19:26:11.712323 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7016 19:26:11.715480 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7017 19:26:11.718555 Pre-setting of DQS Precalculation
7018 19:26:11.721753 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7019 19:26:11.728552 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7020 19:26:11.738169 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7021 19:26:11.738254
7022 19:26:11.738319
7023 19:26:11.738380 [Calibration Summary] 800 Mbps
7024 19:26:11.741813 CH 0, Rank 0
7025 19:26:11.741896 SW Impedance : PASS
7026 19:26:11.744894 DUTY Scan : NO K
7027 19:26:11.748101 ZQ Calibration : PASS
7028 19:26:11.748188 Jitter Meter : NO K
7029 19:26:11.751471 CBT Training : PASS
7030 19:26:11.755010 Write leveling : PASS
7031 19:26:11.755093 RX DQS gating : PASS
7032 19:26:11.758599 RX DQ/DQS(RDDQC) : PASS
7033 19:26:11.761564 TX DQ/DQS : PASS
7034 19:26:11.761648 RX DATLAT : PASS
7035 19:26:11.764558 RX DQ/DQS(Engine): PASS
7036 19:26:11.768022 TX OE : NO K
7037 19:26:11.768133 All Pass.
7038 19:26:11.768227
7039 19:26:11.768322 CH 0, Rank 1
7040 19:26:11.771430 SW Impedance : PASS
7041 19:26:11.774601 DUTY Scan : NO K
7042 19:26:11.774713 ZQ Calibration : PASS
7043 19:26:11.777638 Jitter Meter : NO K
7044 19:26:11.781307 CBT Training : PASS
7045 19:26:11.781417 Write leveling : NO K
7046 19:26:11.784466 RX DQS gating : PASS
7047 19:26:11.787525 RX DQ/DQS(RDDQC) : PASS
7048 19:26:11.787609 TX DQ/DQS : PASS
7049 19:26:11.791127 RX DATLAT : PASS
7050 19:26:11.794194 RX DQ/DQS(Engine): PASS
7051 19:26:11.794278 TX OE : NO K
7052 19:26:11.794344 All Pass.
7053 19:26:11.797610
7054 19:26:11.797693 CH 1, Rank 0
7055 19:26:11.801050 SW Impedance : PASS
7056 19:26:11.801133 DUTY Scan : NO K
7057 19:26:11.804211 ZQ Calibration : PASS
7058 19:26:11.807302 Jitter Meter : NO K
7059 19:26:11.807413 CBT Training : PASS
7060 19:26:11.810866 Write leveling : PASS
7061 19:26:11.813764 RX DQS gating : PASS
7062 19:26:11.813848 RX DQ/DQS(RDDQC) : PASS
7063 19:26:11.817289 TX DQ/DQS : PASS
7064 19:26:11.817455 RX DATLAT : PASS
7065 19:26:11.820320 RX DQ/DQS(Engine): PASS
7066 19:26:11.823617 TX OE : NO K
7067 19:26:11.823701 All Pass.
7068 19:26:11.823767
7069 19:26:11.826630 CH 1, Rank 1
7070 19:26:11.826713 SW Impedance : PASS
7071 19:26:11.830352 DUTY Scan : NO K
7072 19:26:11.830435 ZQ Calibration : PASS
7073 19:26:11.833650 Jitter Meter : NO K
7074 19:26:11.837160 CBT Training : PASS
7075 19:26:11.837244 Write leveling : NO K
7076 19:26:11.840309 RX DQS gating : PASS
7077 19:26:11.843416 RX DQ/DQS(RDDQC) : PASS
7078 19:26:11.843528 TX DQ/DQS : PASS
7079 19:26:11.847252 RX DATLAT : PASS
7080 19:26:11.850333 RX DQ/DQS(Engine): PASS
7081 19:26:11.850417 TX OE : NO K
7082 19:26:11.853450 All Pass.
7083 19:26:11.853540
7084 19:26:11.853628 DramC Write-DBI off
7085 19:26:11.856614 PER_BANK_REFRESH: Hybrid Mode
7086 19:26:11.859586 TX_TRACKING: ON
7087 19:26:11.866654 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7088 19:26:11.870020 [FAST_K] Save calibration result to emmc
7089 19:26:11.876274 dramc_set_vcore_voltage set vcore to 725000
7090 19:26:11.876384 Read voltage for 1600, 0
7091 19:26:11.876458 Vio18 = 0
7092 19:26:11.879687 Vcore = 725000
7093 19:26:11.879789 Vdram = 0
7094 19:26:11.879881 Vddq = 0
7095 19:26:11.883034 Vmddr = 0
7096 19:26:11.885990 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7097 19:26:11.892678 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7098 19:26:11.896037 MEM_TYPE=3, freq_sel=13
7099 19:26:11.899235 sv_algorithm_assistance_LP4_3733
7100 19:26:11.902560 ============ PULL DRAM RESETB DOWN ============
7101 19:26:11.906057 ========== PULL DRAM RESETB DOWN end =========
7102 19:26:11.909245 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7103 19:26:11.912375 ===================================
7104 19:26:11.916266 LPDDR4 DRAM CONFIGURATION
7105 19:26:11.919166 ===================================
7106 19:26:11.922177 EX_ROW_EN[0] = 0x0
7107 19:26:11.922288 EX_ROW_EN[1] = 0x0
7108 19:26:11.925631 LP4Y_EN = 0x0
7109 19:26:11.925742 WORK_FSP = 0x1
7110 19:26:11.929227 WL = 0x5
7111 19:26:11.929349 RL = 0x5
7112 19:26:11.932206 BL = 0x2
7113 19:26:11.932289 RPST = 0x0
7114 19:26:11.935893 RD_PRE = 0x0
7115 19:26:11.939018 WR_PRE = 0x1
7116 19:26:11.939101 WR_PST = 0x1
7117 19:26:11.941990 DBI_WR = 0x0
7118 19:26:11.942066 DBI_RD = 0x0
7119 19:26:11.945718 OTF = 0x1
7120 19:26:11.948801 ===================================
7121 19:26:11.951949 ===================================
7122 19:26:11.952033 ANA top config
7123 19:26:11.955048 ===================================
7124 19:26:11.958728 DLL_ASYNC_EN = 0
7125 19:26:11.961946 ALL_SLAVE_EN = 0
7126 19:26:11.962030 NEW_RANK_MODE = 1
7127 19:26:11.964993 DLL_IDLE_MODE = 1
7128 19:26:11.968129 LP45_APHY_COMB_EN = 1
7129 19:26:11.971646 TX_ODT_DIS = 0
7130 19:26:11.975087 NEW_8X_MODE = 1
7131 19:26:11.978080 ===================================
7132 19:26:11.981625 ===================================
7133 19:26:11.981738 data_rate = 3200
7134 19:26:11.984630 CKR = 1
7135 19:26:11.988278 DQ_P2S_RATIO = 8
7136 19:26:11.991142 ===================================
7137 19:26:11.994687 CA_P2S_RATIO = 8
7138 19:26:11.997958 DQ_CA_OPEN = 0
7139 19:26:12.001267 DQ_SEMI_OPEN = 0
7140 19:26:12.001398 CA_SEMI_OPEN = 0
7141 19:26:12.004804 CA_FULL_RATE = 0
7142 19:26:12.007755 DQ_CKDIV4_EN = 0
7143 19:26:12.011184 CA_CKDIV4_EN = 0
7144 19:26:12.014283 CA_PREDIV_EN = 0
7145 19:26:12.017886 PH8_DLY = 12
7146 19:26:12.021310 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7147 19:26:12.021451 DQ_AAMCK_DIV = 4
7148 19:26:12.024482 CA_AAMCK_DIV = 4
7149 19:26:12.027598 CA_ADMCK_DIV = 4
7150 19:26:12.031483 DQ_TRACK_CA_EN = 0
7151 19:26:12.034134 CA_PICK = 1600
7152 19:26:12.037749 CA_MCKIO = 1600
7153 19:26:12.040891 MCKIO_SEMI = 0
7154 19:26:12.040963 PLL_FREQ = 3068
7155 19:26:12.043909 DQ_UI_PI_RATIO = 32
7156 19:26:12.047704 CA_UI_PI_RATIO = 0
7157 19:26:12.050851 ===================================
7158 19:26:12.054148 ===================================
7159 19:26:12.057126 memory_type:LPDDR4
7160 19:26:12.060859 GP_NUM : 10
7161 19:26:12.060943 SRAM_EN : 1
7162 19:26:12.064049 MD32_EN : 0
7163 19:26:12.067099 ===================================
7164 19:26:12.067182 [ANA_INIT] >>>>>>>>>>>>>>
7165 19:26:12.070823 <<<<<< [CONFIGURE PHASE]: ANA_TX
7166 19:26:12.073962 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7167 19:26:12.077093 ===================================
7168 19:26:12.080907 data_rate = 3200,PCW = 0X7600
7169 19:26:12.083909 ===================================
7170 19:26:12.087288 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7171 19:26:12.093358 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7172 19:26:12.099969 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7173 19:26:12.103459 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7174 19:26:12.106325 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7175 19:26:12.109905 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7176 19:26:12.113288 [ANA_INIT] flow start
7177 19:26:12.113411 [ANA_INIT] PLL >>>>>>>>
7178 19:26:12.116389 [ANA_INIT] PLL <<<<<<<<
7179 19:26:12.119931 [ANA_INIT] MIDPI >>>>>>>>
7180 19:26:12.122886 [ANA_INIT] MIDPI <<<<<<<<
7181 19:26:12.122968 [ANA_INIT] DLL >>>>>>>>
7182 19:26:12.125966 [ANA_INIT] DLL <<<<<<<<
7183 19:26:12.129293 [ANA_INIT] flow end
7184 19:26:12.132679 ============ LP4 DIFF to SE enter ============
7185 19:26:12.136280 ============ LP4 DIFF to SE exit ============
7186 19:26:12.139189 [ANA_INIT] <<<<<<<<<<<<<
7187 19:26:12.142682 [Flow] Enable top DCM control >>>>>
7188 19:26:12.145812 [Flow] Enable top DCM control <<<<<
7189 19:26:12.148891 Enable DLL master slave shuffle
7190 19:26:12.152424 ==============================================================
7191 19:26:12.155517 Gating Mode config
7192 19:26:12.162413 ==============================================================
7193 19:26:12.162498 Config description:
7194 19:26:12.171973 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7195 19:26:12.178768 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7196 19:26:12.182480 SELPH_MODE 0: By rank 1: By Phase
7197 19:26:12.188786 ==============================================================
7198 19:26:12.192354 GAT_TRACK_EN = 1
7199 19:26:12.195550 RX_GATING_MODE = 2
7200 19:26:12.198764 RX_GATING_TRACK_MODE = 2
7201 19:26:12.202027 SELPH_MODE = 1
7202 19:26:12.205527 PICG_EARLY_EN = 1
7203 19:26:12.208462 VALID_LAT_VALUE = 1
7204 19:26:12.211997 ==============================================================
7205 19:26:12.214921 Enter into Gating configuration >>>>
7206 19:26:12.218424 Exit from Gating configuration <<<<
7207 19:26:12.222124 Enter into DVFS_PRE_config >>>>>
7208 19:26:12.234915 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7209 19:26:12.238277 Exit from DVFS_PRE_config <<<<<
7210 19:26:12.241528 Enter into PICG configuration >>>>
7211 19:26:12.241611 Exit from PICG configuration <<<<
7212 19:26:12.245165 [RX_INPUT] configuration >>>>>
7213 19:26:12.248040 [RX_INPUT] configuration <<<<<
7214 19:26:12.254617 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7215 19:26:12.258260 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7216 19:26:12.264432 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7217 19:26:12.271269 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7218 19:26:12.278122 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7219 19:26:12.284206 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7220 19:26:12.287767 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7221 19:26:12.290789 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7222 19:26:12.297526 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7223 19:26:12.300628 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7224 19:26:12.304070 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7225 19:26:12.310921 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7226 19:26:12.311005 ===================================
7227 19:26:12.313804 LPDDR4 DRAM CONFIGURATION
7228 19:26:12.317556 ===================================
7229 19:26:12.320517 EX_ROW_EN[0] = 0x0
7230 19:26:12.320600 EX_ROW_EN[1] = 0x0
7231 19:26:12.324026 LP4Y_EN = 0x0
7232 19:26:12.324110 WORK_FSP = 0x1
7233 19:26:12.327265 WL = 0x5
7234 19:26:12.327348 RL = 0x5
7235 19:26:12.330589 BL = 0x2
7236 19:26:12.333526 RPST = 0x0
7237 19:26:12.333609 RD_PRE = 0x0
7238 19:26:12.337208 WR_PRE = 0x1
7239 19:26:12.337292 WR_PST = 0x1
7240 19:26:12.340160 DBI_WR = 0x0
7241 19:26:12.340243 DBI_RD = 0x0
7242 19:26:12.343362 OTF = 0x1
7243 19:26:12.347069 ===================================
7244 19:26:12.349979 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7245 19:26:12.353215 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7246 19:26:12.359906 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7247 19:26:12.363113 ===================================
7248 19:26:12.363197 LPDDR4 DRAM CONFIGURATION
7249 19:26:12.366919 ===================================
7250 19:26:12.369949 EX_ROW_EN[0] = 0x10
7251 19:26:12.370031 EX_ROW_EN[1] = 0x0
7252 19:26:12.373035 LP4Y_EN = 0x0
7253 19:26:12.376785 WORK_FSP = 0x1
7254 19:26:12.376868 WL = 0x5
7255 19:26:12.380062 RL = 0x5
7256 19:26:12.380145 BL = 0x2
7257 19:26:12.383014 RPST = 0x0
7258 19:26:12.383096 RD_PRE = 0x0
7259 19:26:12.386746 WR_PRE = 0x1
7260 19:26:12.386829 WR_PST = 0x1
7261 19:26:12.389809 DBI_WR = 0x0
7262 19:26:12.389916 DBI_RD = 0x0
7263 19:26:12.392702 OTF = 0x1
7264 19:26:12.396595 ===================================
7265 19:26:12.402839 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7266 19:26:12.402924 ==
7267 19:26:12.405869 Dram Type= 6, Freq= 0, CH_0, rank 0
7268 19:26:12.409624 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7269 19:26:12.409708 ==
7270 19:26:12.412465 [Duty_Offset_Calibration]
7271 19:26:12.412547 B0:1 B1:-1 CA:0
7272 19:26:12.412613
7273 19:26:12.416010 [DutyScan_Calibration_Flow] k_type=0
7274 19:26:12.426544
7275 19:26:12.426628 ==CLK 0==
7276 19:26:12.430234 Final CLK duty delay cell = 0
7277 19:26:12.433225 [0] MAX Duty = 5124%(X100), DQS PI = 22
7278 19:26:12.436277 [0] MIN Duty = 4875%(X100), DQS PI = 10
7279 19:26:12.439859 [0] AVG Duty = 4999%(X100)
7280 19:26:12.439943
7281 19:26:12.443161 CH0 CLK Duty spec in!! Max-Min= 249%
7282 19:26:12.446174 [DutyScan_Calibration_Flow] ====Done====
7283 19:26:12.446257
7284 19:26:12.449243 [DutyScan_Calibration_Flow] k_type=1
7285 19:26:12.465949
7286 19:26:12.466040 ==DQS 0 ==
7287 19:26:12.469025 Final DQS duty delay cell = -4
7288 19:26:12.472309 [-4] MAX Duty = 4969%(X100), DQS PI = 18
7289 19:26:12.475681 [-4] MIN Duty = 4844%(X100), DQS PI = 48
7290 19:26:12.478889 [-4] AVG Duty = 4906%(X100)
7291 19:26:12.478972
7292 19:26:12.479039 ==DQS 1 ==
7293 19:26:12.482609 Final DQS duty delay cell = 0
7294 19:26:12.485750 [0] MAX Duty = 5156%(X100), DQS PI = 2
7295 19:26:12.488792 [0] MIN Duty = 5000%(X100), DQS PI = 20
7296 19:26:12.492723 [0] AVG Duty = 5078%(X100)
7297 19:26:12.492805
7298 19:26:12.495494 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7299 19:26:12.495577
7300 19:26:12.499215 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7301 19:26:12.502199 [DutyScan_Calibration_Flow] ====Done====
7302 19:26:12.502282
7303 19:26:12.505339 [DutyScan_Calibration_Flow] k_type=3
7304 19:26:12.523501
7305 19:26:12.523590 ==DQM 0 ==
7306 19:26:12.526434 Final DQM duty delay cell = 0
7307 19:26:12.529852 [0] MAX Duty = 5124%(X100), DQS PI = 22
7308 19:26:12.533141 [0] MIN Duty = 4938%(X100), DQS PI = 8
7309 19:26:12.536473 [0] AVG Duty = 5031%(X100)
7310 19:26:12.536555
7311 19:26:12.536620 ==DQM 1 ==
7312 19:26:12.539887 Final DQM duty delay cell = 0
7313 19:26:12.543128 [0] MAX Duty = 5000%(X100), DQS PI = 6
7314 19:26:12.546511 [0] MIN Duty = 4813%(X100), DQS PI = 20
7315 19:26:12.549788 [0] AVG Duty = 4906%(X100)
7316 19:26:12.549882
7317 19:26:12.552858 CH0 DQM 0 Duty spec in!! Max-Min= 186%
7318 19:26:12.552965
7319 19:26:12.556446 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7320 19:26:12.559297 [DutyScan_Calibration_Flow] ====Done====
7321 19:26:12.559400
7322 19:26:12.562617 [DutyScan_Calibration_Flow] k_type=2
7323 19:26:12.579546
7324 19:26:12.579775 ==DQ 0 ==
7325 19:26:12.583069 Final DQ duty delay cell = -4
7326 19:26:12.586278 [-4] MAX Duty = 5031%(X100), DQS PI = 24
7327 19:26:12.589557 [-4] MIN Duty = 4876%(X100), DQS PI = 52
7328 19:26:12.592738 [-4] AVG Duty = 4953%(X100)
7329 19:26:12.592982
7330 19:26:12.593174 ==DQ 1 ==
7331 19:26:12.596462 Final DQ duty delay cell = 0
7332 19:26:12.599386 [0] MAX Duty = 5125%(X100), DQS PI = 48
7333 19:26:12.603329 [0] MIN Duty = 4969%(X100), DQS PI = 38
7334 19:26:12.606396 [0] AVG Duty = 5047%(X100)
7335 19:26:12.606828
7336 19:26:12.609454 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7337 19:26:12.609987
7338 19:26:12.613151 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7339 19:26:12.616389 [DutyScan_Calibration_Flow] ====Done====
7340 19:26:12.616810 ==
7341 19:26:12.619615 Dram Type= 6, Freq= 0, CH_1, rank 0
7342 19:26:12.622642 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7343 19:26:12.623073 ==
7344 19:26:12.625832 [Duty_Offset_Calibration]
7345 19:26:12.626255 B0:-1 B1:1 CA:2
7346 19:26:12.629424
7347 19:26:12.632572 [DutyScan_Calibration_Flow] k_type=0
7348 19:26:12.640628
7349 19:26:12.641051 ==CLK 0==
7350 19:26:12.643982 Final CLK duty delay cell = 0
7351 19:26:12.647278 [0] MAX Duty = 5187%(X100), DQS PI = 22
7352 19:26:12.650700 [0] MIN Duty = 4969%(X100), DQS PI = 0
7353 19:26:12.651148 [0] AVG Duty = 5078%(X100)
7354 19:26:12.653829
7355 19:26:12.657253 CH1 CLK Duty spec in!! Max-Min= 218%
7356 19:26:12.660291 [DutyScan_Calibration_Flow] ====Done====
7357 19:26:12.660720
7358 19:26:12.663390 [DutyScan_Calibration_Flow] k_type=1
7359 19:26:12.679687
7360 19:26:12.679773 ==DQS 0 ==
7361 19:26:12.683392 Final DQS duty delay cell = 0
7362 19:26:12.686636 [0] MAX Duty = 5124%(X100), DQS PI = 18
7363 19:26:12.689944 [0] MIN Duty = 4907%(X100), DQS PI = 8
7364 19:26:12.692959 [0] AVG Duty = 5015%(X100)
7365 19:26:12.693041
7366 19:26:12.693106 ==DQS 1 ==
7367 19:26:12.696265 Final DQS duty delay cell = 0
7368 19:26:12.699752 [0] MAX Duty = 5093%(X100), DQS PI = 28
7369 19:26:12.703299 [0] MIN Duty = 4969%(X100), DQS PI = 56
7370 19:26:12.706223 [0] AVG Duty = 5031%(X100)
7371 19:26:12.706319
7372 19:26:12.710020 CH1 DQS 0 Duty spec in!! Max-Min= 217%
7373 19:26:12.710115
7374 19:26:12.713059 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7375 19:26:12.716340 [DutyScan_Calibration_Flow] ====Done====
7376 19:26:12.716453
7377 19:26:12.719295 [DutyScan_Calibration_Flow] k_type=3
7378 19:26:12.736910
7379 19:26:12.737086 ==DQM 0 ==
7380 19:26:12.740679 Final DQM duty delay cell = 0
7381 19:26:12.743521 [0] MAX Duty = 5218%(X100), DQS PI = 34
7382 19:26:12.747065 [0] MIN Duty = 5031%(X100), DQS PI = 8
7383 19:26:12.750061 [0] AVG Duty = 5124%(X100)
7384 19:26:12.750308
7385 19:26:12.750503 ==DQM 1 ==
7386 19:26:12.753424 Final DQM duty delay cell = 0
7387 19:26:12.756913 [0] MAX Duty = 5156%(X100), DQS PI = 8
7388 19:26:12.759740 [0] MIN Duty = 4938%(X100), DQS PI = 34
7389 19:26:12.763490 [0] AVG Duty = 5047%(X100)
7390 19:26:12.763943
7391 19:26:12.766610 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7392 19:26:12.767041
7393 19:26:12.770142 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7394 19:26:12.773392 [DutyScan_Calibration_Flow] ====Done====
7395 19:26:12.773913
7396 19:26:12.776607 [DutyScan_Calibration_Flow] k_type=2
7397 19:26:12.793735
7398 19:26:12.794265 ==DQ 0 ==
7399 19:26:12.797616 Final DQ duty delay cell = 0
7400 19:26:12.800374 [0] MAX Duty = 5187%(X100), DQS PI = 32
7401 19:26:12.803860 [0] MIN Duty = 4906%(X100), DQS PI = 8
7402 19:26:12.804365 [0] AVG Duty = 5046%(X100)
7403 19:26:12.807205
7404 19:26:12.807633 ==DQ 1 ==
7405 19:26:12.810418 Final DQ duty delay cell = 0
7406 19:26:12.813395 [0] MAX Duty = 5156%(X100), DQS PI = 8
7407 19:26:12.816721 [0] MIN Duty = 4969%(X100), DQS PI = 54
7408 19:26:12.817216 [0] AVG Duty = 5062%(X100)
7409 19:26:12.817648
7410 19:26:12.823532 CH1 DQ 0 Duty spec in!! Max-Min= 281%
7411 19:26:12.823964
7412 19:26:12.826497 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7413 19:26:12.830192 [DutyScan_Calibration_Flow] ====Done====
7414 19:26:12.833395 nWR fixed to 30
7415 19:26:12.833878 [ModeRegInit_LP4] CH0 RK0
7416 19:26:12.836573 [ModeRegInit_LP4] CH0 RK1
7417 19:26:12.840154 [ModeRegInit_LP4] CH1 RK0
7418 19:26:12.843138 [ModeRegInit_LP4] CH1 RK1
7419 19:26:12.843781 match AC timing 5
7420 19:26:12.850393 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7421 19:26:12.853200 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7422 19:26:12.856186 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7423 19:26:12.863252 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7424 19:26:12.866622 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7425 19:26:12.867092 [MiockJmeterHQA]
7426 19:26:12.867434
7427 19:26:12.869744 [DramcMiockJmeter] u1RxGatingPI = 0
7428 19:26:12.872697 0 : 4252, 4027
7429 19:26:12.873228 4 : 4363, 4138
7430 19:26:12.876281 8 : 4253, 4026
7431 19:26:12.876835 12 : 4363, 4138
7432 19:26:12.879163 16 : 4252, 4027
7433 19:26:12.879789 20 : 4252, 4027
7434 19:26:12.880383 24 : 4252, 4027
7435 19:26:12.883287 28 : 4255, 4029
7436 19:26:12.883854 32 : 4363, 4138
7437 19:26:12.886268 36 : 4252, 4027
7438 19:26:12.886879 40 : 4253, 4027
7439 19:26:12.888986 44 : 4253, 4027
7440 19:26:12.889614 48 : 4254, 4029
7441 19:26:12.892484 52 : 4253, 4026
7442 19:26:12.893104 56 : 4361, 4137
7443 19:26:12.893718 60 : 4361, 4137
7444 19:26:12.895596 64 : 4250, 4027
7445 19:26:12.896038 68 : 4250, 4027
7446 19:26:12.899236 72 : 4250, 4026
7447 19:26:12.899670 76 : 4250, 4026
7448 19:26:12.902511 80 : 4252, 4029
7449 19:26:12.902947 84 : 4360, 4138
7450 19:26:12.905678 88 : 4250, 4026
7451 19:26:12.906111 92 : 4250, 265
7452 19:26:12.906460 96 : 4361, 0
7453 19:26:12.909384 100 : 4250, 0
7454 19:26:12.909821 104 : 4250, 0
7455 19:26:12.912310 108 : 4252, 0
7456 19:26:12.912741 112 : 4252, 0
7457 19:26:12.913085 116 : 4250, 0
7458 19:26:12.915793 120 : 4252, 0
7459 19:26:12.916230 124 : 4252, 0
7460 19:26:12.916573 128 : 4250, 0
7461 19:26:12.918646 132 : 4252, 0
7462 19:26:12.919082 136 : 4252, 0
7463 19:26:12.921962 140 : 4253, 0
7464 19:26:12.922618 144 : 4250, 0
7465 19:26:12.923203 148 : 4252, 0
7466 19:26:12.925392 152 : 4252, 0
7467 19:26:12.926066 156 : 4250, 0
7468 19:26:12.928399 160 : 4252, 0
7469 19:26:12.928992 164 : 4252, 0
7470 19:26:12.929555 168 : 4250, 0
7471 19:26:12.932288 172 : 4252, 0
7472 19:26:12.932750 176 : 4252, 0
7473 19:26:12.935439 180 : 4250, 0
7474 19:26:12.936052 184 : 4363, 0
7475 19:26:12.936566 188 : 4363, 0
7476 19:26:12.938544 192 : 4253, 0
7477 19:26:12.939128 196 : 4360, 0
7478 19:26:12.942258 200 : 4252, 0
7479 19:26:12.942858 204 : 4252, 0
7480 19:26:12.943392 208 : 4250, 0
7481 19:26:12.945222 212 : 4252, 0
7482 19:26:12.945794 216 : 4253, 0
7483 19:26:12.948468 220 : 4250, 0
7484 19:26:12.949110 224 : 4252, 450
7485 19:26:12.949661 228 : 4360, 3881
7486 19:26:12.951984 232 : 4253, 4027
7487 19:26:12.952546 236 : 4252, 4027
7488 19:26:12.955081 240 : 4361, 4138
7489 19:26:12.955729 244 : 4250, 4027
7490 19:26:12.958218 248 : 4253, 4027
7491 19:26:12.958692 252 : 4252, 4027
7492 19:26:12.961841 256 : 4252, 4029
7493 19:26:12.962499 260 : 4250, 4027
7494 19:26:12.964702 264 : 4253, 4027
7495 19:26:12.965262 268 : 4361, 4137
7496 19:26:12.968426 272 : 4250, 4026
7497 19:26:12.969111 276 : 4250, 4026
7498 19:26:12.972039 280 : 4361, 4137
7499 19:26:12.972674 284 : 4250, 4027
7500 19:26:12.973266 288 : 4250, 4027
7501 19:26:12.974757 292 : 4363, 4139
7502 19:26:12.975331 296 : 4250, 4026
7503 19:26:12.978342 300 : 4250, 4027
7504 19:26:12.978681 304 : 4250, 4027
7505 19:26:12.981288 308 : 4252, 4029
7506 19:26:12.981637 312 : 4250, 4027
7507 19:26:12.985014 316 : 4250, 4027
7508 19:26:12.985485 320 : 4361, 4137
7509 19:26:12.988078 324 : 4250, 4026
7510 19:26:12.988511 328 : 4250, 4027
7511 19:26:12.990946 332 : 4361, 4137
7512 19:26:12.991356 336 : 4250, 3452
7513 19:26:12.994421 340 : 4250, 1762
7514 19:26:12.994790
7515 19:26:12.995196 MIOCK jitter meter ch=0
7516 19:26:12.995580
7517 19:26:12.997844 1T = (340-92) = 248 dly cells
7518 19:26:13.004280 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps
7519 19:26:13.004686 ==
7520 19:26:13.007911 Dram Type= 6, Freq= 0, CH_0, rank 0
7521 19:26:13.010947 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7522 19:26:13.011364 ==
7523 19:26:13.017613 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7524 19:26:13.020863 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7525 19:26:13.024380 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7526 19:26:13.030849 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7527 19:26:13.040820 [CA 0] Center 43 (13~74) winsize 62
7528 19:26:13.044053 [CA 1] Center 42 (12~73) winsize 62
7529 19:26:13.047055 [CA 2] Center 38 (9~68) winsize 60
7530 19:26:13.050176 [CA 3] Center 38 (8~68) winsize 61
7531 19:26:13.053926 [CA 4] Center 36 (7~66) winsize 60
7532 19:26:13.056912 [CA 5] Center 35 (6~65) winsize 60
7533 19:26:13.057434
7534 19:26:13.060674 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7535 19:26:13.061052
7536 19:26:13.066623 [CATrainingPosCal] consider 1 rank data
7537 19:26:13.067010 u2DelayCellTimex100 = 262/100 ps
7538 19:26:13.073403 CA0 delay=43 (13~74),Diff = 8 PI (29 cell)
7539 19:26:13.077096 CA1 delay=42 (12~73),Diff = 7 PI (26 cell)
7540 19:26:13.080031 CA2 delay=38 (9~68),Diff = 3 PI (11 cell)
7541 19:26:13.083418 CA3 delay=38 (8~68),Diff = 3 PI (11 cell)
7542 19:26:13.086618 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7543 19:26:13.090095 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7544 19:26:13.090539
7545 19:26:13.093180 CA PerBit enable=1, Macro0, CA PI delay=35
7546 19:26:13.093626
7547 19:26:13.096808 [CBTSetCACLKResult] CA Dly = 35
7548 19:26:13.100297 CS Dly: 11 (0~42)
7549 19:26:13.102972 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7550 19:26:13.106643 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7551 19:26:13.107029 ==
7552 19:26:13.109910 Dram Type= 6, Freq= 0, CH_0, rank 1
7553 19:26:13.116189 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7554 19:26:13.116606 ==
7555 19:26:13.119797 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7556 19:26:13.126473 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7557 19:26:13.129323 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7558 19:26:13.136041 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7559 19:26:13.144353 [CA 0] Center 42 (12~73) winsize 62
7560 19:26:13.147424 [CA 1] Center 43 (13~73) winsize 61
7561 19:26:13.150517 [CA 2] Center 37 (8~67) winsize 60
7562 19:26:13.154265 [CA 3] Center 37 (8~67) winsize 60
7563 19:26:13.157361 [CA 4] Center 35 (6~65) winsize 60
7564 19:26:13.160666 [CA 5] Center 35 (5~65) winsize 61
7565 19:26:13.161104
7566 19:26:13.164244 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7567 19:26:13.164638
7568 19:26:13.167209 [CATrainingPosCal] consider 2 rank data
7569 19:26:13.170823 u2DelayCellTimex100 = 262/100 ps
7570 19:26:13.177085 CA0 delay=43 (13~73),Diff = 8 PI (29 cell)
7571 19:26:13.180697 CA1 delay=43 (13~73),Diff = 8 PI (29 cell)
7572 19:26:13.183709 CA2 delay=38 (9~67),Diff = 3 PI (11 cell)
7573 19:26:13.186747 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7574 19:26:13.190331 CA4 delay=36 (7~65),Diff = 1 PI (3 cell)
7575 19:26:13.193453 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7576 19:26:13.193845
7577 19:26:13.197165 CA PerBit enable=1, Macro0, CA PI delay=35
7578 19:26:13.197630
7579 19:26:13.200151 [CBTSetCACLKResult] CA Dly = 35
7580 19:26:13.203384 CS Dly: 11 (0~43)
7581 19:26:13.207077 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7582 19:26:13.210141 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7583 19:26:13.210481
7584 19:26:13.213636 ----->DramcWriteLeveling(PI) begin...
7585 19:26:13.213945 ==
7586 19:26:13.216562 Dram Type= 6, Freq= 0, CH_0, rank 0
7587 19:26:13.223295 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7588 19:26:13.223611 ==
7589 19:26:13.226363 Write leveling (Byte 0): 34 => 34
7590 19:26:13.229999 Write leveling (Byte 1): 28 => 28
7591 19:26:13.232872 DramcWriteLeveling(PI) end<-----
7592 19:26:13.233179
7593 19:26:13.233492 ==
7594 19:26:13.236151 Dram Type= 6, Freq= 0, CH_0, rank 0
7595 19:26:13.240014 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7596 19:26:13.240414 ==
7597 19:26:13.242792 [Gating] SW mode calibration
7598 19:26:13.249416 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7599 19:26:13.256393 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7600 19:26:13.259500 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7601 19:26:13.262696 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7602 19:26:13.269767 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7603 19:26:13.272599 1 4 12 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (1 1)
7604 19:26:13.276230 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7605 19:26:13.282675 1 4 20 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
7606 19:26:13.285833 1 4 24 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
7607 19:26:13.289525 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7608 19:26:13.295914 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7609 19:26:13.299179 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7610 19:26:13.302466 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7611 19:26:13.309148 1 5 12 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (1 0)
7612 19:26:13.312308 1 5 16 | B1->B0 | 3434 2424 | 1 0 | (1 0) (0 0)
7613 19:26:13.315952 1 5 20 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
7614 19:26:13.322053 1 5 24 | B1->B0 | 2b2b 2323 | 0 0 | (1 1) (0 0)
7615 19:26:13.325576 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7616 19:26:13.328933 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7617 19:26:13.335086 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7618 19:26:13.338731 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7619 19:26:13.341797 1 6 12 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
7620 19:26:13.348387 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7621 19:26:13.351600 1 6 20 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
7622 19:26:13.355003 1 6 24 | B1->B0 | 4343 4646 | 1 0 | (0 0) (0 0)
7623 19:26:13.361136 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7624 19:26:13.364911 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7625 19:26:13.367952 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7626 19:26:13.374807 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7627 19:26:13.377800 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7628 19:26:13.381292 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7629 19:26:13.387842 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7630 19:26:13.391111 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7631 19:26:13.394801 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7632 19:26:13.401060 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7633 19:26:13.404708 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7634 19:26:13.407545 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7635 19:26:13.414494 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7636 19:26:13.417240 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7637 19:26:13.421096 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7638 19:26:13.427412 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7639 19:26:13.431986 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 19:26:13.434404 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7641 19:26:13.440607 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7642 19:26:13.443719 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7643 19:26:13.447474 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7644 19:26:13.454029 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7645 19:26:13.454504 Total UI for P1: 0, mck2ui 16
7646 19:26:13.459997 best dqsien dly found for B0: ( 1, 9, 10)
7647 19:26:13.463291 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7648 19:26:13.466905 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7649 19:26:13.473795 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7650 19:26:13.474317 Total UI for P1: 0, mck2ui 16
7651 19:26:13.480343 best dqsien dly found for B1: ( 1, 9, 20)
7652 19:26:13.483249 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7653 19:26:13.486725 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7654 19:26:13.487185
7655 19:26:13.489826 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7656 19:26:13.493505 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7657 19:26:13.496801 [Gating] SW calibration Done
7658 19:26:13.497415 ==
7659 19:26:13.499758 Dram Type= 6, Freq= 0, CH_0, rank 0
7660 19:26:13.502959 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7661 19:26:13.503415 ==
7662 19:26:13.506689 RX Vref Scan: 0
7663 19:26:13.507132
7664 19:26:13.507467 RX Vref 0 -> 0, step: 1
7665 19:26:13.509785
7666 19:26:13.510210 RX Delay 0 -> 252, step: 8
7667 19:26:13.512751 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7668 19:26:13.519271 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7669 19:26:13.522733 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7670 19:26:13.526239 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7671 19:26:13.529094 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7672 19:26:13.535628 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7673 19:26:13.539173 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
7674 19:26:13.542710 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7675 19:26:13.545428 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7676 19:26:13.549011 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7677 19:26:13.556125 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7678 19:26:13.559052 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7679 19:26:13.561969 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7680 19:26:13.565415 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7681 19:26:13.568920 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7682 19:26:13.575401 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7683 19:26:13.575843 ==
7684 19:26:13.578736 Dram Type= 6, Freq= 0, CH_0, rank 0
7685 19:26:13.581709 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7686 19:26:13.582158 ==
7687 19:26:13.582612 DQS Delay:
7688 19:26:13.585369 DQS0 = 0, DQS1 = 0
7689 19:26:13.585817 DQM Delay:
7690 19:26:13.588484 DQM0 = 134, DQM1 = 126
7691 19:26:13.588928 DQ Delay:
7692 19:26:13.592221 DQ0 =135, DQ1 =139, DQ2 =131, DQ3 =131
7693 19:26:13.595190 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =147
7694 19:26:13.598774 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =119
7695 19:26:13.605056 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
7696 19:26:13.605571
7697 19:26:13.605915
7698 19:26:13.606228 ==
7699 19:26:13.608811 Dram Type= 6, Freq= 0, CH_0, rank 0
7700 19:26:13.611931 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7701 19:26:13.612460 ==
7702 19:26:13.612806
7703 19:26:13.613123
7704 19:26:13.614994 TX Vref Scan disable
7705 19:26:13.615422 == TX Byte 0 ==
7706 19:26:13.621896 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7707 19:26:13.624845 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7708 19:26:13.625293 == TX Byte 1 ==
7709 19:26:13.631354 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7710 19:26:13.635246 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7711 19:26:13.635677 ==
7712 19:26:13.638178 Dram Type= 6, Freq= 0, CH_0, rank 0
7713 19:26:13.641581 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7714 19:26:13.642072 ==
7715 19:26:13.655772
7716 19:26:13.659004 TX Vref early break, caculate TX vref
7717 19:26:13.662760 TX Vref=16, minBit 4, minWin=22, winSum=373
7718 19:26:13.665813 TX Vref=18, minBit 1, minWin=23, winSum=388
7719 19:26:13.668908 TX Vref=20, minBit 1, minWin=24, winSum=395
7720 19:26:13.672401 TX Vref=22, minBit 5, minWin=24, winSum=404
7721 19:26:13.675554 TX Vref=24, minBit 0, minWin=25, winSum=409
7722 19:26:13.682182 TX Vref=26, minBit 2, minWin=25, winSum=415
7723 19:26:13.685479 TX Vref=28, minBit 0, minWin=25, winSum=417
7724 19:26:13.688957 TX Vref=30, minBit 0, minWin=25, winSum=412
7725 19:26:13.692336 TX Vref=32, minBit 0, minWin=24, winSum=405
7726 19:26:13.695267 TX Vref=34, minBit 4, minWin=22, winSum=390
7727 19:26:13.701977 [TxChooseVref] Worse bit 0, Min win 25, Win sum 417, Final Vref 28
7728 19:26:13.702436
7729 19:26:13.705292 Final TX Range 0 Vref 28
7730 19:26:13.705776
7731 19:26:13.706115 ==
7732 19:26:13.708910 Dram Type= 6, Freq= 0, CH_0, rank 0
7733 19:26:13.711963 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7734 19:26:13.712387 ==
7735 19:26:13.712755
7736 19:26:13.713100
7737 19:26:13.715084 TX Vref Scan disable
7738 19:26:13.721950 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
7739 19:26:13.722517 == TX Byte 0 ==
7740 19:26:13.724911 u2DelayCellOfst[0]=14 cells (4 PI)
7741 19:26:13.728424 u2DelayCellOfst[1]=18 cells (5 PI)
7742 19:26:13.731524 u2DelayCellOfst[2]=14 cells (4 PI)
7743 19:26:13.734959 u2DelayCellOfst[3]=14 cells (4 PI)
7744 19:26:13.738059 u2DelayCellOfst[4]=11 cells (3 PI)
7745 19:26:13.741712 u2DelayCellOfst[5]=0 cells (0 PI)
7746 19:26:13.744752 u2DelayCellOfst[6]=18 cells (5 PI)
7747 19:26:13.748060 u2DelayCellOfst[7]=22 cells (6 PI)
7748 19:26:13.751249 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7749 19:26:13.754367 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7750 19:26:13.757993 == TX Byte 1 ==
7751 19:26:13.760961 u2DelayCellOfst[8]=0 cells (0 PI)
7752 19:26:13.764435 u2DelayCellOfst[9]=3 cells (1 PI)
7753 19:26:13.767661 u2DelayCellOfst[10]=7 cells (2 PI)
7754 19:26:13.768250 u2DelayCellOfst[11]=0 cells (0 PI)
7755 19:26:13.771283 u2DelayCellOfst[12]=11 cells (3 PI)
7756 19:26:13.774184 u2DelayCellOfst[13]=11 cells (3 PI)
7757 19:26:13.777298 u2DelayCellOfst[14]=14 cells (4 PI)
7758 19:26:13.781121 u2DelayCellOfst[15]=11 cells (3 PI)
7759 19:26:13.787274 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7760 19:26:13.790850 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7761 19:26:13.791436 DramC Write-DBI on
7762 19:26:13.794456 ==
7763 19:26:13.797221 Dram Type= 6, Freq= 0, CH_0, rank 0
7764 19:26:13.800680 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7765 19:26:13.801294 ==
7766 19:26:13.801864
7767 19:26:13.802387
7768 19:26:13.803605 TX Vref Scan disable
7769 19:26:13.804183 == TX Byte 0 ==
7770 19:26:13.810366 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7771 19:26:13.810957 == TX Byte 1 ==
7772 19:26:13.813679 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7773 19:26:13.816626 DramC Write-DBI off
7774 19:26:13.817193
7775 19:26:13.817761 [DATLAT]
7776 19:26:13.820302 Freq=1600, CH0 RK0
7777 19:26:13.820797
7778 19:26:13.821082 DATLAT Default: 0xf
7779 19:26:13.823207 0, 0xFFFF, sum = 0
7780 19:26:13.823314 1, 0xFFFF, sum = 0
7781 19:26:13.826328 2, 0xFFFF, sum = 0
7782 19:26:13.829949 3, 0xFFFF, sum = 0
7783 19:26:13.830038 4, 0xFFFF, sum = 0
7784 19:26:13.833042 5, 0xFFFF, sum = 0
7785 19:26:13.833144 6, 0xFFFF, sum = 0
7786 19:26:13.836825 7, 0xFFFF, sum = 0
7787 19:26:13.836937 8, 0xFFFF, sum = 0
7788 19:26:13.839746 9, 0xFFFF, sum = 0
7789 19:26:13.839864 10, 0xFFFF, sum = 0
7790 19:26:13.842855 11, 0xFFFF, sum = 0
7791 19:26:13.842931 12, 0xFFFF, sum = 0
7792 19:26:13.846057 13, 0xFFFF, sum = 0
7793 19:26:13.846127 14, 0x0, sum = 1
7794 19:26:13.849766 15, 0x0, sum = 2
7795 19:26:13.849851 16, 0x0, sum = 3
7796 19:26:13.852942 17, 0x0, sum = 4
7797 19:26:13.853032 best_step = 15
7798 19:26:13.853108
7799 19:26:13.853206 ==
7800 19:26:13.856370 Dram Type= 6, Freq= 0, CH_0, rank 0
7801 19:26:13.862690 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7802 19:26:13.862801 ==
7803 19:26:13.862882 RX Vref Scan: 1
7804 19:26:13.862976
7805 19:26:13.865780 Set Vref Range= 24 -> 127
7806 19:26:13.865900
7807 19:26:13.869486 RX Vref 24 -> 127, step: 1
7808 19:26:13.869569
7809 19:26:13.869680 RX Delay 11 -> 252, step: 4
7810 19:26:13.869775
7811 19:26:13.872674 Set Vref, RX VrefLevel [Byte0]: 24
7812 19:26:13.875919 [Byte1]: 24
7813 19:26:13.879864
7814 19:26:13.879970 Set Vref, RX VrefLevel [Byte0]: 25
7815 19:26:13.882978 [Byte1]: 25
7816 19:26:13.887911
7817 19:26:13.888022 Set Vref, RX VrefLevel [Byte0]: 26
7818 19:26:13.891075 [Byte1]: 26
7819 19:26:13.895504
7820 19:26:13.895634 Set Vref, RX VrefLevel [Byte0]: 27
7821 19:26:13.898452 [Byte1]: 27
7822 19:26:13.902582
7823 19:26:13.906264 Set Vref, RX VrefLevel [Byte0]: 28
7824 19:26:13.909446 [Byte1]: 28
7825 19:26:13.909530
7826 19:26:13.912649 Set Vref, RX VrefLevel [Byte0]: 29
7827 19:26:13.915704 [Byte1]: 29
7828 19:26:13.915818
7829 19:26:13.919041 Set Vref, RX VrefLevel [Byte0]: 30
7830 19:26:13.922676 [Byte1]: 30
7831 19:26:13.925803
7832 19:26:13.925887 Set Vref, RX VrefLevel [Byte0]: 31
7833 19:26:13.929019 [Byte1]: 31
7834 19:26:13.933096
7835 19:26:13.933207 Set Vref, RX VrefLevel [Byte0]: 32
7836 19:26:13.936833 [Byte1]: 32
7837 19:26:13.940603
7838 19:26:13.940707 Set Vref, RX VrefLevel [Byte0]: 33
7839 19:26:13.944162 [Byte1]: 33
7840 19:26:13.948667
7841 19:26:13.948778 Set Vref, RX VrefLevel [Byte0]: 34
7842 19:26:13.951597 [Byte1]: 34
7843 19:26:13.956068
7844 19:26:13.956171 Set Vref, RX VrefLevel [Byte0]: 35
7845 19:26:13.959291 [Byte1]: 35
7846 19:26:13.963919
7847 19:26:13.964024 Set Vref, RX VrefLevel [Byte0]: 36
7848 19:26:13.966802 [Byte1]: 36
7849 19:26:13.971450
7850 19:26:13.971560 Set Vref, RX VrefLevel [Byte0]: 37
7851 19:26:13.974455 [Byte1]: 37
7852 19:26:13.979128
7853 19:26:13.979232 Set Vref, RX VrefLevel [Byte0]: 38
7854 19:26:13.982054 [Byte1]: 38
7855 19:26:13.986860
7856 19:26:13.986974 Set Vref, RX VrefLevel [Byte0]: 39
7857 19:26:13.990095 [Byte1]: 39
7858 19:26:13.994190
7859 19:26:13.994297 Set Vref, RX VrefLevel [Byte0]: 40
7860 19:26:13.997176 [Byte1]: 40
7861 19:26:14.002027
7862 19:26:14.002134 Set Vref, RX VrefLevel [Byte0]: 41
7863 19:26:14.005005 [Byte1]: 41
7864 19:26:14.009214
7865 19:26:14.009341 Set Vref, RX VrefLevel [Byte0]: 42
7866 19:26:14.012463 [Byte1]: 42
7867 19:26:14.016972
7868 19:26:14.017079 Set Vref, RX VrefLevel [Byte0]: 43
7869 19:26:14.020044 [Byte1]: 43
7870 19:26:14.025124
7871 19:26:14.025275 Set Vref, RX VrefLevel [Byte0]: 44
7872 19:26:14.028080 [Byte1]: 44
7873 19:26:14.032715
7874 19:26:14.032856 Set Vref, RX VrefLevel [Byte0]: 45
7875 19:26:14.039036 [Byte1]: 45
7876 19:26:14.039198
7877 19:26:14.042431 Set Vref, RX VrefLevel [Byte0]: 46
7878 19:26:14.045566 [Byte1]: 46
7879 19:26:14.045782
7880 19:26:14.049009 Set Vref, RX VrefLevel [Byte0]: 47
7881 19:26:14.052302 [Byte1]: 47
7882 19:26:14.055331
7883 19:26:14.055581 Set Vref, RX VrefLevel [Byte0]: 48
7884 19:26:14.059034 [Byte1]: 48
7885 19:26:14.062919
7886 19:26:14.063453 Set Vref, RX VrefLevel [Byte0]: 49
7887 19:26:14.066743 [Byte1]: 49
7888 19:26:14.070850
7889 19:26:14.071442 Set Vref, RX VrefLevel [Byte0]: 50
7890 19:26:14.074159 [Byte1]: 50
7891 19:26:14.078017
7892 19:26:14.078607 Set Vref, RX VrefLevel [Byte0]: 51
7893 19:26:14.081467 [Byte1]: 51
7894 19:26:14.086099
7895 19:26:14.086703 Set Vref, RX VrefLevel [Byte0]: 52
7896 19:26:14.089403 [Byte1]: 52
7897 19:26:14.093237
7898 19:26:14.093763 Set Vref, RX VrefLevel [Byte0]: 53
7899 19:26:14.096822 [Byte1]: 53
7900 19:26:14.101070
7901 19:26:14.101611 Set Vref, RX VrefLevel [Byte0]: 54
7902 19:26:14.103995 [Byte1]: 54
7903 19:26:14.108747
7904 19:26:14.109363 Set Vref, RX VrefLevel [Byte0]: 55
7905 19:26:14.112248 [Byte1]: 55
7906 19:26:14.116479
7907 19:26:14.116901 Set Vref, RX VrefLevel [Byte0]: 56
7908 19:26:14.119664 [Byte1]: 56
7909 19:26:14.123768
7910 19:26:14.124313 Set Vref, RX VrefLevel [Byte0]: 57
7911 19:26:14.127430 [Byte1]: 57
7912 19:26:14.131952
7913 19:26:14.132372 Set Vref, RX VrefLevel [Byte0]: 58
7914 19:26:14.135211 [Byte1]: 58
7915 19:26:14.139190
7916 19:26:14.139614 Set Vref, RX VrefLevel [Byte0]: 59
7917 19:26:14.142512 [Byte1]: 59
7918 19:26:14.146723
7919 19:26:14.147166 Set Vref, RX VrefLevel [Byte0]: 60
7920 19:26:14.150390 [Byte1]: 60
7921 19:26:14.154181
7922 19:26:14.154683 Set Vref, RX VrefLevel [Byte0]: 61
7923 19:26:14.157415 [Byte1]: 61
7924 19:26:14.161919
7925 19:26:14.162345 Set Vref, RX VrefLevel [Byte0]: 62
7926 19:26:14.165142 [Byte1]: 62
7927 19:26:14.169426
7928 19:26:14.170005 Set Vref, RX VrefLevel [Byte0]: 63
7929 19:26:14.173185 [Byte1]: 63
7930 19:26:14.177631
7931 19:26:14.178292 Set Vref, RX VrefLevel [Byte0]: 64
7932 19:26:14.180467 [Byte1]: 64
7933 19:26:14.184688
7934 19:26:14.185400 Set Vref, RX VrefLevel [Byte0]: 65
7935 19:26:14.188021 [Byte1]: 65
7936 19:26:14.192287
7937 19:26:14.192998 Set Vref, RX VrefLevel [Byte0]: 66
7938 19:26:14.195862 [Byte1]: 66
7939 19:26:14.200261
7940 19:26:14.200935 Set Vref, RX VrefLevel [Byte0]: 67
7941 19:26:14.203440 [Byte1]: 67
7942 19:26:14.207549
7943 19:26:14.208200 Set Vref, RX VrefLevel [Byte0]: 68
7944 19:26:14.211099 [Byte1]: 68
7945 19:26:14.215179
7946 19:26:14.215831 Set Vref, RX VrefLevel [Byte0]: 69
7947 19:26:14.218721 [Byte1]: 69
7948 19:26:14.223029
7949 19:26:14.223498 Set Vref, RX VrefLevel [Byte0]: 70
7950 19:26:14.226088 [Byte1]: 70
7951 19:26:14.230370
7952 19:26:14.230841 Set Vref, RX VrefLevel [Byte0]: 71
7953 19:26:14.233614 [Byte1]: 71
7954 19:26:14.237854
7955 19:26:14.238275 Set Vref, RX VrefLevel [Byte0]: 72
7956 19:26:14.241627 [Byte1]: 72
7957 19:26:14.245645
7958 19:26:14.246074 Set Vref, RX VrefLevel [Byte0]: 73
7959 19:26:14.249069 [Byte1]: 73
7960 19:26:14.253287
7961 19:26:14.253775 Set Vref, RX VrefLevel [Byte0]: 74
7962 19:26:14.256351 [Byte1]: 74
7963 19:26:14.260636
7964 19:26:14.261082 Set Vref, RX VrefLevel [Byte0]: 75
7965 19:26:14.264090 [Byte1]: 75
7966 19:26:14.268167
7967 19:26:14.268476 Set Vref, RX VrefLevel [Byte0]: 76
7968 19:26:14.271944 [Byte1]: 76
7969 19:26:14.276382
7970 19:26:14.276682 Set Vref, RX VrefLevel [Byte0]: 77
7971 19:26:14.279306 [Byte1]: 77
7972 19:26:14.283609
7973 19:26:14.283927 Set Vref, RX VrefLevel [Byte0]: 78
7974 19:26:14.287168 [Byte1]: 78
7975 19:26:14.291517
7976 19:26:14.291827 Final RX Vref Byte 0 = 65 to rank0
7977 19:26:14.294512 Final RX Vref Byte 1 = 56 to rank0
7978 19:26:14.297868 Final RX Vref Byte 0 = 65 to rank1
7979 19:26:14.301441 Final RX Vref Byte 1 = 56 to rank1==
7980 19:26:14.304456 Dram Type= 6, Freq= 0, CH_0, rank 0
7981 19:26:14.311175 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7982 19:26:14.311499 ==
7983 19:26:14.311751 DQS Delay:
7984 19:26:14.312004 DQS0 = 0, DQS1 = 0
7985 19:26:14.314367 DQM Delay:
7986 19:26:14.314689 DQM0 = 132, DQM1 = 123
7987 19:26:14.317979 DQ Delay:
7988 19:26:14.321100 DQ0 =130, DQ1 =136, DQ2 =130, DQ3 =132
7989 19:26:14.324320 DQ4 =132, DQ5 =122, DQ6 =140, DQ7 =140
7990 19:26:14.327417 DQ8 =114, DQ9 =110, DQ10 =124, DQ11 =118
7991 19:26:14.331392 DQ12 =128, DQ13 =128, DQ14 =134, DQ15 =130
7992 19:26:14.331721
7993 19:26:14.332111
7994 19:26:14.332473
7995 19:26:14.334261 [DramC_TX_OE_Calibration] TA2
7996 19:26:14.337490 Original DQ_B0 (3 6) =30, OEN = 27
7997 19:26:14.340701 Original DQ_B1 (3 6) =30, OEN = 27
7998 19:26:14.343759 24, 0x0, End_B0=24 End_B1=24
7999 19:26:14.347590 25, 0x0, End_B0=25 End_B1=25
8000 19:26:14.347870 26, 0x0, End_B0=26 End_B1=26
8001 19:26:14.350610 27, 0x0, End_B0=27 End_B1=27
8002 19:26:14.354160 28, 0x0, End_B0=28 End_B1=28
8003 19:26:14.357536 29, 0x0, End_B0=29 End_B1=29
8004 19:26:14.357824 30, 0x0, End_B0=30 End_B1=30
8005 19:26:14.360944 31, 0x4141, End_B0=30 End_B1=30
8006 19:26:14.363998 Byte0 end_step=30 best_step=27
8007 19:26:14.367013 Byte1 end_step=30 best_step=27
8008 19:26:14.370458 Byte0 TX OE(2T, 0.5T) = (3, 3)
8009 19:26:14.373438 Byte1 TX OE(2T, 0.5T) = (3, 3)
8010 19:26:14.373759
8011 19:26:14.374025
8012 19:26:14.380154 [DQSOSCAuto] RK0, (LSB)MR18= 0x2012, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 393 ps
8013 19:26:14.383783 CH0 RK0: MR19=303, MR18=2012
8014 19:26:14.390467 CH0_RK0: MR19=0x303, MR18=0x2012, DQSOSC=393, MR23=63, INC=23, DEC=15
8015 19:26:14.390871
8016 19:26:14.393653 ----->DramcWriteLeveling(PI) begin...
8017 19:26:14.393988 ==
8018 19:26:14.396725 Dram Type= 6, Freq= 0, CH_0, rank 1
8019 19:26:14.400318 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8020 19:26:14.400658 ==
8021 19:26:14.403647 Write leveling (Byte 0): 34 => 34
8022 19:26:14.406747 Write leveling (Byte 1): 31 => 31
8023 19:26:14.409997 DramcWriteLeveling(PI) end<-----
8024 19:26:14.410298
8025 19:26:14.410567 ==
8026 19:26:14.413597 Dram Type= 6, Freq= 0, CH_0, rank 1
8027 19:26:14.420049 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8028 19:26:14.420408 ==
8029 19:26:14.420673 [Gating] SW mode calibration
8030 19:26:14.429963 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8031 19:26:14.432876 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8032 19:26:14.436422 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8033 19:26:14.442816 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8034 19:26:14.446566 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8035 19:26:14.449678 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8036 19:26:14.456339 1 4 16 | B1->B0 | 2323 3131 | 0 1 | (0 0) (0 0)
8037 19:26:14.459485 1 4 20 | B1->B0 | 2a29 3434 | 1 1 | (0 0) (1 1)
8038 19:26:14.462557 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8039 19:26:14.469563 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8040 19:26:14.472765 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8041 19:26:14.475449 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8042 19:26:14.482089 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8043 19:26:14.485764 1 5 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8044 19:26:14.492485 1 5 16 | B1->B0 | 3434 2727 | 1 1 | (1 1) (1 0)
8045 19:26:14.495520 1 5 20 | B1->B0 | 3333 2323 | 0 0 | (0 0) (0 0)
8046 19:26:14.499191 1 5 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8047 19:26:14.502442 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8048 19:26:14.508929 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8049 19:26:14.512013 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8050 19:26:14.515264 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8051 19:26:14.521655 1 6 12 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
8052 19:26:14.525188 1 6 16 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
8053 19:26:14.528282 1 6 20 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
8054 19:26:14.535117 1 6 24 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8055 19:26:14.538438 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8056 19:26:14.542106 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8057 19:26:14.548483 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8058 19:26:14.551608 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8059 19:26:14.555274 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8060 19:26:14.561522 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8061 19:26:14.564701 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8062 19:26:14.568372 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8063 19:26:14.575113 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8064 19:26:14.578158 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8065 19:26:14.581738 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8066 19:26:14.587983 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8067 19:26:14.591271 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8068 19:26:14.594421 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8069 19:26:14.601181 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8070 19:26:14.604129 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8071 19:26:14.610860 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8072 19:26:14.614492 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8073 19:26:14.617554 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8074 19:26:14.624296 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8075 19:26:14.627497 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8076 19:26:14.630357 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8077 19:26:14.634046 Total UI for P1: 0, mck2ui 16
8078 19:26:14.637143 best dqsien dly found for B0: ( 1, 9, 12)
8079 19:26:14.640707 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8080 19:26:14.647555 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8081 19:26:14.650328 Total UI for P1: 0, mck2ui 16
8082 19:26:14.654182 best dqsien dly found for B1: ( 1, 9, 18)
8083 19:26:14.657179 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8084 19:26:14.660386 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8085 19:26:14.660820
8086 19:26:14.663652 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8087 19:26:14.667257 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8088 19:26:14.670522 [Gating] SW calibration Done
8089 19:26:14.671008 ==
8090 19:26:14.673476 Dram Type= 6, Freq= 0, CH_0, rank 1
8091 19:26:14.677144 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8092 19:26:14.680079 ==
8093 19:26:14.680645 RX Vref Scan: 0
8094 19:26:14.681126
8095 19:26:14.683368 RX Vref 0 -> 0, step: 1
8096 19:26:14.683895
8097 19:26:14.684385 RX Delay 0 -> 252, step: 8
8098 19:26:14.690226 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8099 19:26:14.693531 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8100 19:26:14.696780 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8101 19:26:14.699927 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8102 19:26:14.706682 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8103 19:26:14.709816 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8104 19:26:14.712874 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8105 19:26:14.716358 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8106 19:26:14.719490 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8107 19:26:14.726206 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8108 19:26:14.729976 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8109 19:26:14.732820 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8110 19:26:14.735923 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8111 19:26:14.739514 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8112 19:26:14.746000 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8113 19:26:14.749484 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8114 19:26:14.750026 ==
8115 19:26:14.752308 Dram Type= 6, Freq= 0, CH_0, rank 1
8116 19:26:14.755645 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8117 19:26:14.756143 ==
8118 19:26:14.759079 DQS Delay:
8119 19:26:14.759523 DQS0 = 0, DQS1 = 0
8120 19:26:14.762342 DQM Delay:
8121 19:26:14.762793 DQM0 = 133, DQM1 = 128
8122 19:26:14.763275 DQ Delay:
8123 19:26:14.766125 DQ0 =135, DQ1 =135, DQ2 =127, DQ3 =127
8124 19:26:14.772120 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8125 19:26:14.775424 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8126 19:26:14.779121 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
8127 19:26:14.779554
8128 19:26:14.780016
8129 19:26:14.780472 ==
8130 19:26:14.782052 Dram Type= 6, Freq= 0, CH_0, rank 1
8131 19:26:14.785240 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8132 19:26:14.785781 ==
8133 19:26:14.786265
8134 19:26:14.786744
8135 19:26:14.789025 TX Vref Scan disable
8136 19:26:14.792214 == TX Byte 0 ==
8137 19:26:14.795336 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8138 19:26:14.798941 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8139 19:26:14.802008 == TX Byte 1 ==
8140 19:26:14.805627 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8141 19:26:14.808561 Update DQM dly =987 (3 ,6, 27) DQM OEN =(3 ,3)
8142 19:26:14.809008 ==
8143 19:26:14.811845 Dram Type= 6, Freq= 0, CH_0, rank 1
8144 19:26:14.818664 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8145 19:26:14.819087 ==
8146 19:26:14.830256
8147 19:26:14.833374 TX Vref early break, caculate TX vref
8148 19:26:14.836413 TX Vref=16, minBit 1, minWin=22, winSum=378
8149 19:26:14.840150 TX Vref=18, minBit 1, minWin=23, winSum=390
8150 19:26:14.843073 TX Vref=20, minBit 1, minWin=23, winSum=396
8151 19:26:14.846144 TX Vref=22, minBit 2, minWin=23, winSum=401
8152 19:26:14.849875 TX Vref=24, minBit 0, minWin=24, winSum=413
8153 19:26:14.856463 TX Vref=26, minBit 0, minWin=24, winSum=415
8154 19:26:14.859760 TX Vref=28, minBit 1, minWin=24, winSum=411
8155 19:26:14.863202 TX Vref=30, minBit 1, minWin=24, winSum=403
8156 19:26:14.866330 TX Vref=32, minBit 0, minWin=23, winSum=398
8157 19:26:14.869542 TX Vref=34, minBit 2, minWin=23, winSum=392
8158 19:26:14.876076 [TxChooseVref] Worse bit 0, Min win 24, Win sum 415, Final Vref 26
8159 19:26:14.876531
8160 19:26:14.879184 Final TX Range 0 Vref 26
8161 19:26:14.879616
8162 19:26:14.880204 ==
8163 19:26:14.882761 Dram Type= 6, Freq= 0, CH_0, rank 1
8164 19:26:14.886105 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8165 19:26:14.886641 ==
8166 19:26:14.887015
8167 19:26:14.887330
8168 19:26:14.889152 TX Vref Scan disable
8169 19:26:14.896066 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8170 19:26:14.896544 == TX Byte 0 ==
8171 19:26:14.899055 u2DelayCellOfst[0]=14 cells (4 PI)
8172 19:26:14.902658 u2DelayCellOfst[1]=22 cells (6 PI)
8173 19:26:14.905914 u2DelayCellOfst[2]=14 cells (4 PI)
8174 19:26:14.909416 u2DelayCellOfst[3]=18 cells (5 PI)
8175 19:26:14.912626 u2DelayCellOfst[4]=11 cells (3 PI)
8176 19:26:14.915556 u2DelayCellOfst[5]=0 cells (0 PI)
8177 19:26:14.919055 u2DelayCellOfst[6]=22 cells (6 PI)
8178 19:26:14.922289 u2DelayCellOfst[7]=22 cells (6 PI)
8179 19:26:14.925608 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8180 19:26:14.928904 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8181 19:26:14.932164 == TX Byte 1 ==
8182 19:26:14.935084 u2DelayCellOfst[8]=0 cells (0 PI)
8183 19:26:14.938522 u2DelayCellOfst[9]=3 cells (1 PI)
8184 19:26:14.941704 u2DelayCellOfst[10]=11 cells (3 PI)
8185 19:26:14.944785 u2DelayCellOfst[11]=3 cells (1 PI)
8186 19:26:14.948617 u2DelayCellOfst[12]=14 cells (4 PI)
8187 19:26:14.951488 u2DelayCellOfst[13]=14 cells (4 PI)
8188 19:26:14.951925 u2DelayCellOfst[14]=18 cells (5 PI)
8189 19:26:14.954796 u2DelayCellOfst[15]=14 cells (4 PI)
8190 19:26:14.961666 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8191 19:26:14.964731 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
8192 19:26:14.968116 DramC Write-DBI on
8193 19:26:14.968555 ==
8194 19:26:14.971175 Dram Type= 6, Freq= 0, CH_0, rank 1
8195 19:26:14.974686 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8196 19:26:14.975233 ==
8197 19:26:14.975588
8198 19:26:14.975941
8199 19:26:14.978093 TX Vref Scan disable
8200 19:26:14.978515 == TX Byte 0 ==
8201 19:26:14.984740 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8202 19:26:14.985235 == TX Byte 1 ==
8203 19:26:14.987995 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
8204 19:26:14.991021 DramC Write-DBI off
8205 19:26:14.991514
8206 19:26:14.991852 [DATLAT]
8207 19:26:14.994308 Freq=1600, CH0 RK1
8208 19:26:14.994737
8209 19:26:14.995075 DATLAT Default: 0xf
8210 19:26:14.998023 0, 0xFFFF, sum = 0
8211 19:26:14.998491 1, 0xFFFF, sum = 0
8212 19:26:15.001142 2, 0xFFFF, sum = 0
8213 19:26:15.004174 3, 0xFFFF, sum = 0
8214 19:26:15.004686 4, 0xFFFF, sum = 0
8215 19:26:15.007645 5, 0xFFFF, sum = 0
8216 19:26:15.008102 6, 0xFFFF, sum = 0
8217 19:26:15.010843 7, 0xFFFF, sum = 0
8218 19:26:15.011349 8, 0xFFFF, sum = 0
8219 19:26:15.013945 9, 0xFFFF, sum = 0
8220 19:26:15.014374 10, 0xFFFF, sum = 0
8221 19:26:15.017098 11, 0xFFFF, sum = 0
8222 19:26:15.017619 12, 0xFFFF, sum = 0
8223 19:26:15.020887 13, 0xFFFF, sum = 0
8224 19:26:15.021316 14, 0x0, sum = 1
8225 19:26:15.024338 15, 0x0, sum = 2
8226 19:26:15.024780 16, 0x0, sum = 3
8227 19:26:15.027325 17, 0x0, sum = 4
8228 19:26:15.027788 best_step = 15
8229 19:26:15.028124
8230 19:26:15.028452 ==
8231 19:26:15.030554 Dram Type= 6, Freq= 0, CH_0, rank 1
8232 19:26:15.037273 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8233 19:26:15.037740 ==
8234 19:26:15.038082 RX Vref Scan: 0
8235 19:26:15.038398
8236 19:26:15.040910 RX Vref 0 -> 0, step: 1
8237 19:26:15.041537
8238 19:26:15.043794 RX Delay 11 -> 252, step: 4
8239 19:26:15.047117 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8240 19:26:15.050541 iDelay=195, Bit 1, Center 134 (79 ~ 190) 112
8241 19:26:15.056670 iDelay=195, Bit 2, Center 124 (71 ~ 178) 108
8242 19:26:15.060132 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
8243 19:26:15.063404 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8244 19:26:15.066907 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8245 19:26:15.069865 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8246 19:26:15.076755 iDelay=195, Bit 7, Center 140 (87 ~ 194) 108
8247 19:26:15.079937 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8248 19:26:15.083093 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8249 19:26:15.086611 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8250 19:26:15.089851 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8251 19:26:15.096312 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8252 19:26:15.099464 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8253 19:26:15.103293 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8254 19:26:15.106310 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8255 19:26:15.106844 ==
8256 19:26:15.109558 Dram Type= 6, Freq= 0, CH_0, rank 1
8257 19:26:15.116168 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8258 19:26:15.116660 ==
8259 19:26:15.117153 DQS Delay:
8260 19:26:15.119308 DQS0 = 0, DQS1 = 0
8261 19:26:15.119743 DQM Delay:
8262 19:26:15.123072 DQM0 = 130, DQM1 = 125
8263 19:26:15.123557 DQ Delay:
8264 19:26:15.126154 DQ0 =128, DQ1 =134, DQ2 =124, DQ3 =126
8265 19:26:15.129107 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =140
8266 19:26:15.132650 DQ8 =114, DQ9 =110, DQ10 =128, DQ11 =120
8267 19:26:15.135946 DQ12 =132, DQ13 =132, DQ14 =136, DQ15 =132
8268 19:26:15.136369
8269 19:26:15.136703
8270 19:26:15.137013
8271 19:26:15.139050 [DramC_TX_OE_Calibration] TA2
8272 19:26:15.142764 Original DQ_B0 (3 6) =30, OEN = 27
8273 19:26:15.145772 Original DQ_B1 (3 6) =30, OEN = 27
8274 19:26:15.149261 24, 0x0, End_B0=24 End_B1=24
8275 19:26:15.152549 25, 0x0, End_B0=25 End_B1=25
8276 19:26:15.153055 26, 0x0, End_B0=26 End_B1=26
8277 19:26:15.156084 27, 0x0, End_B0=27 End_B1=27
8278 19:26:15.158921 28, 0x0, End_B0=28 End_B1=28
8279 19:26:15.162314 29, 0x0, End_B0=29 End_B1=29
8280 19:26:15.165692 30, 0x0, End_B0=30 End_B1=30
8281 19:26:15.166125 31, 0x4141, End_B0=30 End_B1=30
8282 19:26:15.168885 Byte0 end_step=30 best_step=27
8283 19:26:15.172352 Byte1 end_step=30 best_step=27
8284 19:26:15.175317 Byte0 TX OE(2T, 0.5T) = (3, 3)
8285 19:26:15.178527 Byte1 TX OE(2T, 0.5T) = (3, 3)
8286 19:26:15.178952
8287 19:26:15.179290
8288 19:26:15.185481 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e02, (MSB)MR19= 0x303, tDQSOscB0 = 409 ps tDQSOscB1 = 394 ps
8289 19:26:15.188433 CH0 RK1: MR19=303, MR18=1E02
8290 19:26:15.195470 CH0_RK1: MR19=0x303, MR18=0x1E02, DQSOSC=394, MR23=63, INC=23, DEC=15
8291 19:26:15.198546 [RxdqsGatingPostProcess] freq 1600
8292 19:26:15.205234 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8293 19:26:15.208323 best DQS0 dly(2T, 0.5T) = (1, 1)
8294 19:26:15.208838 best DQS1 dly(2T, 0.5T) = (1, 1)
8295 19:26:15.211335 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8296 19:26:15.215005 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8297 19:26:15.217907 best DQS0 dly(2T, 0.5T) = (1, 1)
8298 19:26:15.221561 best DQS1 dly(2T, 0.5T) = (1, 1)
8299 19:26:15.224724 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8300 19:26:15.227784 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8301 19:26:15.230887 Pre-setting of DQS Precalculation
8302 19:26:15.237395 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8303 19:26:15.237621 ==
8304 19:26:15.241152 Dram Type= 6, Freq= 0, CH_1, rank 0
8305 19:26:15.244420 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8306 19:26:15.244648 ==
8307 19:26:15.250599 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8308 19:26:15.254331 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8309 19:26:15.257517 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8310 19:26:15.264147 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8311 19:26:15.272477 [CA 0] Center 41 (12~71) winsize 60
8312 19:26:15.275903 [CA 1] Center 42 (12~72) winsize 61
8313 19:26:15.279019 [CA 2] Center 37 (8~66) winsize 59
8314 19:26:15.282548 [CA 3] Center 36 (7~65) winsize 59
8315 19:26:15.285885 [CA 4] Center 37 (8~66) winsize 59
8316 19:26:15.288900 [CA 5] Center 36 (7~66) winsize 60
8317 19:26:15.289317
8318 19:26:15.292321 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8319 19:26:15.292737
8320 19:26:15.298994 [CATrainingPosCal] consider 1 rank data
8321 19:26:15.299445 u2DelayCellTimex100 = 262/100 ps
8322 19:26:15.305624 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8323 19:26:15.309052 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8324 19:26:15.312053 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8325 19:26:15.315203 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8326 19:26:15.318788 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8327 19:26:15.321889 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8328 19:26:15.322518
8329 19:26:15.324785 CA PerBit enable=1, Macro0, CA PI delay=36
8330 19:26:15.325389
8331 19:26:15.328480 [CBTSetCACLKResult] CA Dly = 36
8332 19:26:15.331558 CS Dly: 9 (0~40)
8333 19:26:15.334931 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8334 19:26:15.338409 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8335 19:26:15.339014 ==
8336 19:26:15.341470 Dram Type= 6, Freq= 0, CH_1, rank 1
8337 19:26:15.348457 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8338 19:26:15.348909 ==
8339 19:26:15.351430 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8340 19:26:15.357925 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8341 19:26:15.361261 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8342 19:26:15.368161 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8343 19:26:15.376149 [CA 0] Center 42 (13~71) winsize 59
8344 19:26:15.378920 [CA 1] Center 43 (13~73) winsize 61
8345 19:26:15.382608 [CA 2] Center 37 (8~67) winsize 60
8346 19:26:15.385497 [CA 3] Center 37 (7~67) winsize 61
8347 19:26:15.389435 [CA 4] Center 38 (9~67) winsize 59
8348 19:26:15.392226 [CA 5] Center 37 (8~67) winsize 60
8349 19:26:15.392701
8350 19:26:15.395473 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8351 19:26:15.396064
8352 19:26:15.402134 [CATrainingPosCal] consider 2 rank data
8353 19:26:15.402564 u2DelayCellTimex100 = 262/100 ps
8354 19:26:15.408610 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8355 19:26:15.412305 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8356 19:26:15.415057 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8357 19:26:15.418867 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8358 19:26:15.421856 CA4 delay=37 (9~66),Diff = 1 PI (3 cell)
8359 19:26:15.425604 CA5 delay=37 (8~66),Diff = 1 PI (3 cell)
8360 19:26:15.426183
8361 19:26:15.428584 CA PerBit enable=1, Macro0, CA PI delay=36
8362 19:26:15.429194
8363 19:26:15.431599 [CBTSetCACLKResult] CA Dly = 36
8364 19:26:15.435313 CS Dly: 10 (0~43)
8365 19:26:15.438581 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8366 19:26:15.441526 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8367 19:26:15.441995
8368 19:26:15.445086 ----->DramcWriteLeveling(PI) begin...
8369 19:26:15.445571 ==
8370 19:26:15.448260 Dram Type= 6, Freq= 0, CH_1, rank 0
8371 19:26:15.454801 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8372 19:26:15.455256 ==
8373 19:26:15.457831 Write leveling (Byte 0): 23 => 23
8374 19:26:15.461636 Write leveling (Byte 1): 26 => 26
8375 19:26:15.464761 DramcWriteLeveling(PI) end<-----
8376 19:26:15.465180
8377 19:26:15.465625 ==
8378 19:26:15.467882 Dram Type= 6, Freq= 0, CH_1, rank 0
8379 19:26:15.471020 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8380 19:26:15.471534 ==
8381 19:26:15.474489 [Gating] SW mode calibration
8382 19:26:15.481279 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8383 19:26:15.488281 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8384 19:26:15.491027 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8385 19:26:15.494526 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8386 19:26:15.501132 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8387 19:26:15.504409 1 4 12 | B1->B0 | 3030 3333 | 1 0 | (1 1) (0 0)
8388 19:26:15.507381 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8389 19:26:15.514093 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8390 19:26:15.517476 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8391 19:26:15.520677 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8392 19:26:15.527047 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8393 19:26:15.530832 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8394 19:26:15.533916 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8395 19:26:15.540453 1 5 12 | B1->B0 | 2e2e 2424 | 0 0 | (1 0) (1 0)
8396 19:26:15.543657 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8397 19:26:15.546847 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8398 19:26:15.553783 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8399 19:26:15.557106 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8400 19:26:15.560013 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8401 19:26:15.566744 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8402 19:26:15.569849 1 6 8 | B1->B0 | 2626 2828 | 0 0 | (0 0) (0 0)
8403 19:26:15.573651 1 6 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8404 19:26:15.580263 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8405 19:26:15.583485 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8406 19:26:15.586486 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8407 19:26:15.593239 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8408 19:26:15.596321 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8409 19:26:15.599884 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8410 19:26:15.606025 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8411 19:26:15.609540 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8412 19:26:15.613149 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8413 19:26:15.619432 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8414 19:26:15.623196 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8415 19:26:15.626001 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8416 19:26:15.632476 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8417 19:26:15.635882 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8418 19:26:15.639103 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8419 19:26:15.645733 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8420 19:26:15.648988 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8421 19:26:15.652586 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8422 19:26:15.658675 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8423 19:26:15.662247 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8424 19:26:15.665718 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8425 19:26:15.671849 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8426 19:26:15.675827 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8427 19:26:15.678791 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8428 19:26:15.685448 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8429 19:26:15.685874 Total UI for P1: 0, mck2ui 16
8430 19:26:15.692210 best dqsien dly found for B0: ( 1, 9, 10)
8431 19:26:15.692715 Total UI for P1: 0, mck2ui 16
8432 19:26:15.695235 best dqsien dly found for B1: ( 1, 9, 10)
8433 19:26:15.701994 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8434 19:26:15.704899 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8435 19:26:15.705265
8436 19:26:15.708630 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8437 19:26:15.711877 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8438 19:26:15.714891 [Gating] SW calibration Done
8439 19:26:15.715314 ==
8440 19:26:15.718385 Dram Type= 6, Freq= 0, CH_1, rank 0
8441 19:26:15.721886 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8442 19:26:15.722429 ==
8443 19:26:15.724771 RX Vref Scan: 0
8444 19:26:15.725193
8445 19:26:15.725673 RX Vref 0 -> 0, step: 1
8446 19:26:15.726009
8447 19:26:15.728402 RX Delay 0 -> 252, step: 8
8448 19:26:15.731432 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8449 19:26:15.738162 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8450 19:26:15.742259 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8451 19:26:15.744610 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8452 19:26:15.748350 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8453 19:26:15.751449 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8454 19:26:15.757987 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8455 19:26:15.761174 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8456 19:26:15.764605 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8457 19:26:15.767714 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8458 19:26:15.771389 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8459 19:26:15.777850 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8460 19:26:15.780977 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8461 19:26:15.784043 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8462 19:26:15.787451 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8463 19:26:15.793845 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8464 19:26:15.794296 ==
8465 19:26:15.797579 Dram Type= 6, Freq= 0, CH_1, rank 0
8466 19:26:15.800653 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8467 19:26:15.801271 ==
8468 19:26:15.801653 DQS Delay:
8469 19:26:15.803767 DQS0 = 0, DQS1 = 0
8470 19:26:15.804206 DQM Delay:
8471 19:26:15.807486 DQM0 = 137, DQM1 = 127
8472 19:26:15.807917 DQ Delay:
8473 19:26:15.810434 DQ0 =139, DQ1 =131, DQ2 =127, DQ3 =135
8474 19:26:15.814078 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8475 19:26:15.817117 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =119
8476 19:26:15.820456 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =135
8477 19:26:15.823733
8478 19:26:15.824199
8479 19:26:15.824539 ==
8480 19:26:15.827147 Dram Type= 6, Freq= 0, CH_1, rank 0
8481 19:26:15.830451 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8482 19:26:15.830882 ==
8483 19:26:15.831284
8484 19:26:15.831601
8485 19:26:15.833315 TX Vref Scan disable
8486 19:26:15.833829 == TX Byte 0 ==
8487 19:26:15.840404 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8488 19:26:15.843382 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8489 19:26:15.843852 == TX Byte 1 ==
8490 19:26:15.849887 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8491 19:26:15.853216 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8492 19:26:15.853716 ==
8493 19:26:15.856241 Dram Type= 6, Freq= 0, CH_1, rank 0
8494 19:26:15.860251 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8495 19:26:15.860865 ==
8496 19:26:15.873857
8497 19:26:15.877074 TX Vref early break, caculate TX vref
8498 19:26:15.880685 TX Vref=16, minBit 5, minWin=21, winSum=371
8499 19:26:15.883722 TX Vref=18, minBit 0, minWin=22, winSum=386
8500 19:26:15.886909 TX Vref=20, minBit 0, minWin=22, winSum=394
8501 19:26:15.890044 TX Vref=22, minBit 5, minWin=23, winSum=402
8502 19:26:15.893689 TX Vref=24, minBit 0, minWin=24, winSum=411
8503 19:26:15.900271 TX Vref=26, minBit 0, minWin=25, winSum=417
8504 19:26:15.903094 TX Vref=28, minBit 0, minWin=24, winSum=421
8505 19:26:15.906352 TX Vref=30, minBit 1, minWin=23, winSum=410
8506 19:26:15.910421 TX Vref=32, minBit 0, minWin=23, winSum=403
8507 19:26:15.913209 TX Vref=34, minBit 0, minWin=22, winSum=393
8508 19:26:15.919861 [TxChooseVref] Worse bit 0, Min win 25, Win sum 417, Final Vref 26
8509 19:26:15.920290
8510 19:26:15.922970 Final TX Range 0 Vref 26
8511 19:26:15.923465
8512 19:26:15.923849 ==
8513 19:26:15.926594 Dram Type= 6, Freq= 0, CH_1, rank 0
8514 19:26:15.929692 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8515 19:26:15.930224 ==
8516 19:26:15.930634
8517 19:26:15.931028
8518 19:26:15.932855 TX Vref Scan disable
8519 19:26:15.939404 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8520 19:26:15.939840 == TX Byte 0 ==
8521 19:26:15.942973 u2DelayCellOfst[0]=14 cells (4 PI)
8522 19:26:15.945956 u2DelayCellOfst[1]=11 cells (3 PI)
8523 19:26:15.949305 u2DelayCellOfst[2]=0 cells (0 PI)
8524 19:26:15.952896 u2DelayCellOfst[3]=3 cells (1 PI)
8525 19:26:15.956250 u2DelayCellOfst[4]=7 cells (2 PI)
8526 19:26:15.959601 u2DelayCellOfst[5]=18 cells (5 PI)
8527 19:26:15.962661 u2DelayCellOfst[6]=18 cells (5 PI)
8528 19:26:15.965846 u2DelayCellOfst[7]=3 cells (1 PI)
8529 19:26:15.969616 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8530 19:26:15.972485 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8531 19:26:15.975670 == TX Byte 1 ==
8532 19:26:15.979373 u2DelayCellOfst[8]=0 cells (0 PI)
8533 19:26:15.979843 u2DelayCellOfst[9]=3 cells (1 PI)
8534 19:26:15.982158 u2DelayCellOfst[10]=11 cells (3 PI)
8535 19:26:15.985472 u2DelayCellOfst[11]=3 cells (1 PI)
8536 19:26:15.989115 u2DelayCellOfst[12]=14 cells (4 PI)
8537 19:26:15.992338 u2DelayCellOfst[13]=14 cells (4 PI)
8538 19:26:15.995758 u2DelayCellOfst[14]=18 cells (5 PI)
8539 19:26:15.998845 u2DelayCellOfst[15]=18 cells (5 PI)
8540 19:26:16.005549 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8541 19:26:16.008729 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8542 19:26:16.009163 DramC Write-DBI on
8543 19:26:16.009642 ==
8544 19:26:16.012527 Dram Type= 6, Freq= 0, CH_1, rank 0
8545 19:26:16.018504 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8546 19:26:16.018955 ==
8547 19:26:16.019501
8548 19:26:16.019917
8549 19:26:16.022177 TX Vref Scan disable
8550 19:26:16.022607 == TX Byte 0 ==
8551 19:26:16.028824 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8552 19:26:16.029258 == TX Byte 1 ==
8553 19:26:16.031875 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8554 19:26:16.035074 DramC Write-DBI off
8555 19:26:16.035505
8556 19:26:16.035941 [DATLAT]
8557 19:26:16.038860 Freq=1600, CH1 RK0
8558 19:26:16.039295
8559 19:26:16.039747 DATLAT Default: 0xf
8560 19:26:16.041727 0, 0xFFFF, sum = 0
8561 19:26:16.042167 1, 0xFFFF, sum = 0
8562 19:26:16.045559 2, 0xFFFF, sum = 0
8563 19:26:16.045998 3, 0xFFFF, sum = 0
8564 19:26:16.048451 4, 0xFFFF, sum = 0
8565 19:26:16.048991 5, 0xFFFF, sum = 0
8566 19:26:16.051969 6, 0xFFFF, sum = 0
8567 19:26:16.052526 7, 0xFFFF, sum = 0
8568 19:26:16.054832 8, 0xFFFF, sum = 0
8569 19:26:16.055400 9, 0xFFFF, sum = 0
8570 19:26:16.058510 10, 0xFFFF, sum = 0
8571 19:26:16.061751 11, 0xFFFF, sum = 0
8572 19:26:16.062316 12, 0xFFFF, sum = 0
8573 19:26:16.065023 13, 0xFFFF, sum = 0
8574 19:26:16.065572 14, 0x0, sum = 1
8575 19:26:16.068391 15, 0x0, sum = 2
8576 19:26:16.068833 16, 0x0, sum = 3
8577 19:26:16.071388 17, 0x0, sum = 4
8578 19:26:16.071786 best_step = 15
8579 19:26:16.072237
8580 19:26:16.072636 ==
8581 19:26:16.074624 Dram Type= 6, Freq= 0, CH_1, rank 0
8582 19:26:16.078506 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8583 19:26:16.078993 ==
8584 19:26:16.081544 RX Vref Scan: 1
8585 19:26:16.081973
8586 19:26:16.084501 Set Vref Range= 24 -> 127
8587 19:26:16.084982
8588 19:26:16.085519 RX Vref 24 -> 127, step: 1
8589 19:26:16.085940
8590 19:26:16.088427 RX Delay 11 -> 252, step: 4
8591 19:26:16.088858
8592 19:26:16.091295 Set Vref, RX VrefLevel [Byte0]: 24
8593 19:26:16.094399 [Byte1]: 24
8594 19:26:16.097826
8595 19:26:16.098332 Set Vref, RX VrefLevel [Byte0]: 25
8596 19:26:16.101319 [Byte1]: 25
8597 19:26:16.105438
8598 19:26:16.105919 Set Vref, RX VrefLevel [Byte0]: 26
8599 19:26:16.108850 [Byte1]: 26
8600 19:26:16.113506
8601 19:26:16.113930 Set Vref, RX VrefLevel [Byte0]: 27
8602 19:26:16.116845 [Byte1]: 27
8603 19:26:16.120857
8604 19:26:16.121362 Set Vref, RX VrefLevel [Byte0]: 28
8605 19:26:16.123906 [Byte1]: 28
8606 19:26:16.128992
8607 19:26:16.129491 Set Vref, RX VrefLevel [Byte0]: 29
8608 19:26:16.131813 [Byte1]: 29
8609 19:26:16.136114
8610 19:26:16.136567 Set Vref, RX VrefLevel [Byte0]: 30
8611 19:26:16.139787 [Byte1]: 30
8612 19:26:16.143542
8613 19:26:16.143990 Set Vref, RX VrefLevel [Byte0]: 31
8614 19:26:16.146997 [Byte1]: 31
8615 19:26:16.151259
8616 19:26:16.151686 Set Vref, RX VrefLevel [Byte0]: 32
8617 19:26:16.154333 [Byte1]: 32
8618 19:26:16.158932
8619 19:26:16.159360 Set Vref, RX VrefLevel [Byte0]: 33
8620 19:26:16.162122 [Byte1]: 33
8621 19:26:16.166216
8622 19:26:16.166723 Set Vref, RX VrefLevel [Byte0]: 34
8623 19:26:16.169926 [Byte1]: 34
8624 19:26:16.173738
8625 19:26:16.174181 Set Vref, RX VrefLevel [Byte0]: 35
8626 19:26:16.177610 [Byte1]: 35
8627 19:26:16.182039
8628 19:26:16.182470 Set Vref, RX VrefLevel [Byte0]: 36
8629 19:26:16.185137 [Byte1]: 36
8630 19:26:16.189463
8631 19:26:16.189983 Set Vref, RX VrefLevel [Byte0]: 37
8632 19:26:16.192587 [Byte1]: 37
8633 19:26:16.196951
8634 19:26:16.197553 Set Vref, RX VrefLevel [Byte0]: 38
8635 19:26:16.200603 [Byte1]: 38
8636 19:26:16.204865
8637 19:26:16.205287 Set Vref, RX VrefLevel [Byte0]: 39
8638 19:26:16.207942 [Byte1]: 39
8639 19:26:16.211889
8640 19:26:16.212316 Set Vref, RX VrefLevel [Byte0]: 40
8641 19:26:16.215243 [Byte1]: 40
8642 19:26:16.219962
8643 19:26:16.220540 Set Vref, RX VrefLevel [Byte0]: 41
8644 19:26:16.222987 [Byte1]: 41
8645 19:26:16.227384
8646 19:26:16.227801 Set Vref, RX VrefLevel [Byte0]: 42
8647 19:26:16.230592 [Byte1]: 42
8648 19:26:16.235190
8649 19:26:16.235680 Set Vref, RX VrefLevel [Byte0]: 43
8650 19:26:16.238135 [Byte1]: 43
8651 19:26:16.242302
8652 19:26:16.242381 Set Vref, RX VrefLevel [Byte0]: 44
8653 19:26:16.245351 [Byte1]: 44
8654 19:26:16.249676
8655 19:26:16.249749 Set Vref, RX VrefLevel [Byte0]: 45
8656 19:26:16.253183 [Byte1]: 45
8657 19:26:16.257631
8658 19:26:16.257713 Set Vref, RX VrefLevel [Byte0]: 46
8659 19:26:16.260690 [Byte1]: 46
8660 19:26:16.265267
8661 19:26:16.265400 Set Vref, RX VrefLevel [Byte0]: 47
8662 19:26:16.268354 [Byte1]: 47
8663 19:26:16.272758
8664 19:26:16.272840 Set Vref, RX VrefLevel [Byte0]: 48
8665 19:26:16.275897 [Byte1]: 48
8666 19:26:16.280538
8667 19:26:16.280612 Set Vref, RX VrefLevel [Byte0]: 49
8668 19:26:16.283828 [Byte1]: 49
8669 19:26:16.288030
8670 19:26:16.288102 Set Vref, RX VrefLevel [Byte0]: 50
8671 19:26:16.291218 [Byte1]: 50
8672 19:26:16.295571
8673 19:26:16.295658 Set Vref, RX VrefLevel [Byte0]: 51
8674 19:26:16.298866 [Byte1]: 51
8675 19:26:16.303484
8676 19:26:16.303611 Set Vref, RX VrefLevel [Byte0]: 52
8677 19:26:16.306807 [Byte1]: 52
8678 19:26:16.311006
8679 19:26:16.311088 Set Vref, RX VrefLevel [Byte0]: 53
8680 19:26:16.313968 [Byte1]: 53
8681 19:26:16.318728
8682 19:26:16.318810 Set Vref, RX VrefLevel [Byte0]: 54
8683 19:26:16.321603 [Byte1]: 54
8684 19:26:16.326439
8685 19:26:16.326857 Set Vref, RX VrefLevel [Byte0]: 55
8686 19:26:16.329642 [Byte1]: 55
8687 19:26:16.333925
8688 19:26:16.334340 Set Vref, RX VrefLevel [Byte0]: 56
8689 19:26:16.337414 [Byte1]: 56
8690 19:26:16.341544
8691 19:26:16.342008 Set Vref, RX VrefLevel [Byte0]: 57
8692 19:26:16.345237 [Byte1]: 57
8693 19:26:16.349021
8694 19:26:16.349637 Set Vref, RX VrefLevel [Byte0]: 58
8695 19:26:16.352300 [Byte1]: 58
8696 19:26:16.356972
8697 19:26:16.357534 Set Vref, RX VrefLevel [Byte0]: 59
8698 19:26:16.360029 [Byte1]: 59
8699 19:26:16.365057
8700 19:26:16.365586 Set Vref, RX VrefLevel [Byte0]: 60
8701 19:26:16.368040 [Byte1]: 60
8702 19:26:16.372304
8703 19:26:16.372719 Set Vref, RX VrefLevel [Byte0]: 61
8704 19:26:16.375080 [Byte1]: 61
8705 19:26:16.380030
8706 19:26:16.380478 Set Vref, RX VrefLevel [Byte0]: 62
8707 19:26:16.383143 [Byte1]: 62
8708 19:26:16.387055
8709 19:26:16.387526 Set Vref, RX VrefLevel [Byte0]: 63
8710 19:26:16.390859 [Byte1]: 63
8711 19:26:16.395084
8712 19:26:16.395569 Set Vref, RX VrefLevel [Byte0]: 64
8713 19:26:16.398003 [Byte1]: 64
8714 19:26:16.402330
8715 19:26:16.402760 Set Vref, RX VrefLevel [Byte0]: 65
8716 19:26:16.405773 [Byte1]: 65
8717 19:26:16.410156
8718 19:26:16.410589 Set Vref, RX VrefLevel [Byte0]: 66
8719 19:26:16.413920 [Byte1]: 66
8720 19:26:16.418092
8721 19:26:16.418568 Set Vref, RX VrefLevel [Byte0]: 67
8722 19:26:16.421293 [Byte1]: 67
8723 19:26:16.425529
8724 19:26:16.425976 Set Vref, RX VrefLevel [Byte0]: 68
8725 19:26:16.428577 [Byte1]: 68
8726 19:26:16.433083
8727 19:26:16.433553 Set Vref, RX VrefLevel [Byte0]: 69
8728 19:26:16.436056 [Byte1]: 69
8729 19:26:16.440587
8730 19:26:16.441116 Set Vref, RX VrefLevel [Byte0]: 70
8731 19:26:16.444009 [Byte1]: 70
8732 19:26:16.448278
8733 19:26:16.448874 Set Vref, RX VrefLevel [Byte0]: 71
8734 19:26:16.451410 [Byte1]: 71
8735 19:26:16.456399
8736 19:26:16.456999 Set Vref, RX VrefLevel [Byte0]: 72
8737 19:26:16.458942 [Byte1]: 72
8738 19:26:16.463419
8739 19:26:16.464015 Set Vref, RX VrefLevel [Byte0]: 73
8740 19:26:16.466727 [Byte1]: 73
8741 19:26:16.471352
8742 19:26:16.471773 Set Vref, RX VrefLevel [Byte0]: 74
8743 19:26:16.474458 [Byte1]: 74
8744 19:26:16.478696
8745 19:26:16.479251 Final RX Vref Byte 0 = 53 to rank0
8746 19:26:16.482009 Final RX Vref Byte 1 = 60 to rank0
8747 19:26:16.485649 Final RX Vref Byte 0 = 53 to rank1
8748 19:26:16.488633 Final RX Vref Byte 1 = 60 to rank1==
8749 19:26:16.491743 Dram Type= 6, Freq= 0, CH_1, rank 0
8750 19:26:16.498086 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8751 19:26:16.498509 ==
8752 19:26:16.498846 DQS Delay:
8753 19:26:16.501886 DQS0 = 0, DQS1 = 0
8754 19:26:16.502304 DQM Delay:
8755 19:26:16.504899 DQM0 = 133, DQM1 = 127
8756 19:26:16.505661 DQ Delay:
8757 19:26:16.508007 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8758 19:26:16.511697 DQ4 =130, DQ5 =146, DQ6 =142, DQ7 =128
8759 19:26:16.514849 DQ8 =114, DQ9 =116, DQ10 =130, DQ11 =116
8760 19:26:16.517817 DQ12 =136, DQ13 =136, DQ14 =136, DQ15 =138
8761 19:26:16.518304
8762 19:26:16.518647
8763 19:26:16.518958
8764 19:26:16.521708 [DramC_TX_OE_Calibration] TA2
8765 19:26:16.524773 Original DQ_B0 (3 6) =30, OEN = 27
8766 19:26:16.527827 Original DQ_B1 (3 6) =30, OEN = 27
8767 19:26:16.531397 24, 0x0, End_B0=24 End_B1=24
8768 19:26:16.534507 25, 0x0, End_B0=25 End_B1=25
8769 19:26:16.534965 26, 0x0, End_B0=26 End_B1=26
8770 19:26:16.538136 27, 0x0, End_B0=27 End_B1=27
8771 19:26:16.541085 28, 0x0, End_B0=28 End_B1=28
8772 19:26:16.544497 29, 0x0, End_B0=29 End_B1=29
8773 19:26:16.544994 30, 0x0, End_B0=30 End_B1=30
8774 19:26:16.547859 31, 0x5151, End_B0=30 End_B1=30
8775 19:26:16.550827 Byte0 end_step=30 best_step=27
8776 19:26:16.553936 Byte1 end_step=30 best_step=27
8777 19:26:16.557651 Byte0 TX OE(2T, 0.5T) = (3, 3)
8778 19:26:16.560830 Byte1 TX OE(2T, 0.5T) = (3, 3)
8779 19:26:16.561297
8780 19:26:16.561767
8781 19:26:16.567450 [DQSOSCAuto] RK0, (LSB)MR18= 0x180e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
8782 19:26:16.570874 CH1 RK0: MR19=303, MR18=180E
8783 19:26:16.577148 CH1_RK0: MR19=0x303, MR18=0x180E, DQSOSC=397, MR23=63, INC=23, DEC=15
8784 19:26:16.577658
8785 19:26:16.580471 ----->DramcWriteLeveling(PI) begin...
8786 19:26:16.580953 ==
8787 19:26:16.583663 Dram Type= 6, Freq= 0, CH_1, rank 1
8788 19:26:16.586989 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8789 19:26:16.587477 ==
8790 19:26:16.590454 Write leveling (Byte 0): 24 => 24
8791 19:26:16.593683 Write leveling (Byte 1): 27 => 27
8792 19:26:16.596761 DramcWriteLeveling(PI) end<-----
8793 19:26:16.597477
8794 19:26:16.598013 ==
8795 19:26:16.600468 Dram Type= 6, Freq= 0, CH_1, rank 1
8796 19:26:16.606889 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8797 19:26:16.607336 ==
8798 19:26:16.607837 [Gating] SW mode calibration
8799 19:26:16.616788 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8800 19:26:16.619899 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8801 19:26:16.626774 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8802 19:26:16.630467 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8803 19:26:16.633301 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8804 19:26:16.636512 1 4 12 | B1->B0 | 3232 2323 | 0 0 | (0 0) (0 0)
8805 19:26:16.643427 1 4 16 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
8806 19:26:16.646280 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8807 19:26:16.653460 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8808 19:26:16.656373 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8809 19:26:16.659723 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8810 19:26:16.666350 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8811 19:26:16.669375 1 5 8 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 0)
8812 19:26:16.673134 1 5 12 | B1->B0 | 2828 3434 | 1 1 | (1 0) (1 0)
8813 19:26:16.679717 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8814 19:26:16.682713 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8815 19:26:16.685747 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8816 19:26:16.692746 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8817 19:26:16.696128 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8818 19:26:16.699661 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8819 19:26:16.705958 1 6 8 | B1->B0 | 2525 2323 | 1 0 | (0 0) (0 0)
8820 19:26:16.709538 1 6 12 | B1->B0 | 4545 2323 | 0 0 | (0 0) (0 0)
8821 19:26:16.712613 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8822 19:26:16.715856 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8823 19:26:16.722588 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8824 19:26:16.725691 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8825 19:26:16.732263 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8826 19:26:16.735793 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8827 19:26:16.738784 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8828 19:26:16.745672 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8829 19:26:16.749190 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8830 19:26:16.752029 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8831 19:26:16.758562 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8832 19:26:16.762147 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8833 19:26:16.765239 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8834 19:26:16.768726 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8835 19:26:16.775062 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8836 19:26:16.778651 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8837 19:26:16.785259 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8838 19:26:16.788958 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8839 19:26:16.791923 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8840 19:26:16.798319 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8841 19:26:16.801804 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8842 19:26:16.804945 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8843 19:26:16.807974 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8844 19:26:16.814720 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8845 19:26:16.818360 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8846 19:26:16.821499 Total UI for P1: 0, mck2ui 16
8847 19:26:16.824846 best dqsien dly found for B1: ( 1, 9, 8)
8848 19:26:16.828146 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8849 19:26:16.831255 Total UI for P1: 0, mck2ui 16
8850 19:26:16.834403 best dqsien dly found for B0: ( 1, 9, 14)
8851 19:26:16.841165 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8852 19:26:16.844228 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8853 19:26:16.844710
8854 19:26:16.847997 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8855 19:26:16.850968 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8856 19:26:16.854075 [Gating] SW calibration Done
8857 19:26:16.854504 ==
8858 19:26:16.857776 Dram Type= 6, Freq= 0, CH_1, rank 1
8859 19:26:16.860964 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8860 19:26:16.861440 ==
8861 19:26:16.864239 RX Vref Scan: 0
8862 19:26:16.864726
8863 19:26:16.865084 RX Vref 0 -> 0, step: 1
8864 19:26:16.865589
8865 19:26:16.867196 RX Delay 0 -> 252, step: 8
8866 19:26:16.870814 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8867 19:26:16.876981 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8868 19:26:16.880351 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8869 19:26:16.883592 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8870 19:26:16.887040 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8871 19:26:16.890332 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8872 19:26:16.896917 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8873 19:26:16.899982 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8874 19:26:16.903853 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8875 19:26:16.906810 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8876 19:26:16.910263 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8877 19:26:16.916925 iDelay=208, Bit 11, Center 123 (64 ~ 183) 120
8878 19:26:16.920055 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8879 19:26:16.923222 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8880 19:26:16.926659 iDelay=208, Bit 14, Center 135 (72 ~ 199) 128
8881 19:26:16.933306 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8882 19:26:16.933900 ==
8883 19:26:16.936170 Dram Type= 6, Freq= 0, CH_1, rank 1
8884 19:26:16.939756 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8885 19:26:16.940333 ==
8886 19:26:16.940738 DQS Delay:
8887 19:26:16.942904 DQS0 = 0, DQS1 = 0
8888 19:26:16.943477 DQM Delay:
8889 19:26:16.946619 DQM0 = 136, DQM1 = 130
8890 19:26:16.947150 DQ Delay:
8891 19:26:16.949743 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8892 19:26:16.952733 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8893 19:26:16.956396 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =123
8894 19:26:16.959553 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8895 19:26:16.960131
8896 19:26:16.962742
8897 19:26:16.963173 ==
8898 19:26:16.965722 Dram Type= 6, Freq= 0, CH_1, rank 1
8899 19:26:16.969637 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8900 19:26:16.970068 ==
8901 19:26:16.970412
8902 19:26:16.970730
8903 19:26:16.972655 TX Vref Scan disable
8904 19:26:16.973084 == TX Byte 0 ==
8905 19:26:16.979367 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8906 19:26:16.982252 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8907 19:26:16.982672 == TX Byte 1 ==
8908 19:26:16.988748 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8909 19:26:16.992205 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8910 19:26:16.992751 ==
8911 19:26:16.995757 Dram Type= 6, Freq= 0, CH_1, rank 1
8912 19:26:16.998931 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8913 19:26:16.999365 ==
8914 19:26:17.012437
8915 19:26:17.015490 TX Vref early break, caculate TX vref
8916 19:26:17.019255 TX Vref=16, minBit 6, minWin=22, winSum=382
8917 19:26:17.022478 TX Vref=18, minBit 1, minWin=23, winSum=395
8918 19:26:17.026204 TX Vref=20, minBit 6, minWin=23, winSum=401
8919 19:26:17.029166 TX Vref=22, minBit 1, minWin=24, winSum=407
8920 19:26:17.032325 TX Vref=24, minBit 5, minWin=24, winSum=417
8921 19:26:17.039236 TX Vref=26, minBit 0, minWin=25, winSum=421
8922 19:26:17.042120 TX Vref=28, minBit 0, minWin=24, winSum=423
8923 19:26:17.045474 TX Vref=30, minBit 0, minWin=24, winSum=417
8924 19:26:17.049071 TX Vref=32, minBit 0, minWin=24, winSum=408
8925 19:26:17.052269 TX Vref=34, minBit 0, minWin=23, winSum=394
8926 19:26:17.059062 [TxChooseVref] Worse bit 0, Min win 25, Win sum 421, Final Vref 26
8927 19:26:17.059583
8928 19:26:17.062029 Final TX Range 0 Vref 26
8929 19:26:17.062596
8930 19:26:17.063083 ==
8931 19:26:17.065105 Dram Type= 6, Freq= 0, CH_1, rank 1
8932 19:26:17.068727 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8933 19:26:17.069250 ==
8934 19:26:17.069654
8935 19:26:17.069977
8936 19:26:17.072156 TX Vref Scan disable
8937 19:26:17.078817 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8938 19:26:17.079247 == TX Byte 0 ==
8939 19:26:17.081927 u2DelayCellOfst[0]=22 cells (6 PI)
8940 19:26:17.085061 u2DelayCellOfst[1]=11 cells (3 PI)
8941 19:26:17.088538 u2DelayCellOfst[2]=0 cells (0 PI)
8942 19:26:17.091802 u2DelayCellOfst[3]=7 cells (2 PI)
8943 19:26:17.094614 u2DelayCellOfst[4]=11 cells (3 PI)
8944 19:26:17.098443 u2DelayCellOfst[5]=22 cells (6 PI)
8945 19:26:17.101327 u2DelayCellOfst[6]=22 cells (6 PI)
8946 19:26:17.105077 u2DelayCellOfst[7]=3 cells (1 PI)
8947 19:26:17.108358 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8948 19:26:17.111519 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8949 19:26:17.114854 == TX Byte 1 ==
8950 19:26:17.118191 u2DelayCellOfst[8]=0 cells (0 PI)
8951 19:26:17.121384 u2DelayCellOfst[9]=7 cells (2 PI)
8952 19:26:17.124395 u2DelayCellOfst[10]=11 cells (3 PI)
8953 19:26:17.124962 u2DelayCellOfst[11]=3 cells (1 PI)
8954 19:26:17.128292 u2DelayCellOfst[12]=14 cells (4 PI)
8955 19:26:17.131267 u2DelayCellOfst[13]=18 cells (5 PI)
8956 19:26:17.134325 u2DelayCellOfst[14]=18 cells (5 PI)
8957 19:26:17.137315 u2DelayCellOfst[15]=18 cells (5 PI)
8958 19:26:17.143819 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8959 19:26:17.146994 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8960 19:26:17.150671 DramC Write-DBI on
8961 19:26:17.151099 ==
8962 19:26:17.154149 Dram Type= 6, Freq= 0, CH_1, rank 1
8963 19:26:17.156920 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8964 19:26:17.157587 ==
8965 19:26:17.158149
8966 19:26:17.158498
8967 19:26:17.160479 TX Vref Scan disable
8968 19:26:17.160944 == TX Byte 0 ==
8969 19:26:17.166756 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8970 19:26:17.167273 == TX Byte 1 ==
8971 19:26:17.170053 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8972 19:26:17.173823 DramC Write-DBI off
8973 19:26:17.174270
8974 19:26:17.174692 [DATLAT]
8975 19:26:17.176839 Freq=1600, CH1 RK1
8976 19:26:17.177472
8977 19:26:17.177886 DATLAT Default: 0xf
8978 19:26:17.180373 0, 0xFFFF, sum = 0
8979 19:26:17.180839 1, 0xFFFF, sum = 0
8980 19:26:17.183428 2, 0xFFFF, sum = 0
8981 19:26:17.186478 3, 0xFFFF, sum = 0
8982 19:26:17.186934 4, 0xFFFF, sum = 0
8983 19:26:17.190265 5, 0xFFFF, sum = 0
8984 19:26:17.190700 6, 0xFFFF, sum = 0
8985 19:26:17.193255 7, 0xFFFF, sum = 0
8986 19:26:17.193758 8, 0xFFFF, sum = 0
8987 19:26:17.196379 9, 0xFFFF, sum = 0
8988 19:26:17.196829 10, 0xFFFF, sum = 0
8989 19:26:17.199922 11, 0xFFFF, sum = 0
8990 19:26:17.200359 12, 0xFFFF, sum = 0
8991 19:26:17.203368 13, 0xFFFF, sum = 0
8992 19:26:17.203806 14, 0x0, sum = 1
8993 19:26:17.206214 15, 0x0, sum = 2
8994 19:26:17.206649 16, 0x0, sum = 3
8995 19:26:17.209969 17, 0x0, sum = 4
8996 19:26:17.210410 best_step = 15
8997 19:26:17.210749
8998 19:26:17.211091 ==
8999 19:26:17.213105 Dram Type= 6, Freq= 0, CH_1, rank 1
9000 19:26:17.219572 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9001 19:26:17.220222 ==
9002 19:26:17.220704 RX Vref Scan: 0
9003 19:26:17.221157
9004 19:26:17.222771 RX Vref 0 -> 0, step: 1
9005 19:26:17.223338
9006 19:26:17.226463 RX Delay 11 -> 252, step: 4
9007 19:26:17.229894 iDelay=203, Bit 0, Center 138 (87 ~ 190) 104
9008 19:26:17.232297 iDelay=203, Bit 1, Center 128 (75 ~ 182) 108
9009 19:26:17.239398 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9010 19:26:17.242439 iDelay=203, Bit 3, Center 130 (79 ~ 182) 104
9011 19:26:17.246227 iDelay=203, Bit 4, Center 132 (75 ~ 190) 116
9012 19:26:17.249047 iDelay=203, Bit 5, Center 144 (91 ~ 198) 108
9013 19:26:17.252357 iDelay=203, Bit 6, Center 146 (91 ~ 202) 112
9014 19:26:17.258828 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9015 19:26:17.262248 iDelay=203, Bit 8, Center 112 (55 ~ 170) 116
9016 19:26:17.265147 iDelay=203, Bit 9, Center 116 (63 ~ 170) 108
9017 19:26:17.268837 iDelay=203, Bit 10, Center 126 (71 ~ 182) 112
9018 19:26:17.271773 iDelay=203, Bit 11, Center 116 (63 ~ 170) 108
9019 19:26:17.278915 iDelay=203, Bit 12, Center 136 (83 ~ 190) 108
9020 19:26:17.281821 iDelay=203, Bit 13, Center 134 (79 ~ 190) 112
9021 19:26:17.285633 iDelay=203, Bit 14, Center 134 (79 ~ 190) 112
9022 19:26:17.288632 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9023 19:26:17.289230 ==
9024 19:26:17.291763 Dram Type= 6, Freq= 0, CH_1, rank 1
9025 19:26:17.298608 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9026 19:26:17.299040 ==
9027 19:26:17.299386 DQS Delay:
9028 19:26:17.301600 DQS0 = 0, DQS1 = 0
9029 19:26:17.302168 DQM Delay:
9030 19:26:17.305032 DQM0 = 133, DQM1 = 126
9031 19:26:17.305635 DQ Delay:
9032 19:26:17.308104 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130
9033 19:26:17.311167 DQ4 =132, DQ5 =144, DQ6 =146, DQ7 =130
9034 19:26:17.314971 DQ8 =112, DQ9 =116, DQ10 =126, DQ11 =116
9035 19:26:17.318070 DQ12 =136, DQ13 =134, DQ14 =134, DQ15 =138
9036 19:26:17.318644
9037 19:26:17.319141
9038 19:26:17.319603
9039 19:26:17.321164 [DramC_TX_OE_Calibration] TA2
9040 19:26:17.324986 Original DQ_B0 (3 6) =30, OEN = 27
9041 19:26:17.327896 Original DQ_B1 (3 6) =30, OEN = 27
9042 19:26:17.331012 24, 0x0, End_B0=24 End_B1=24
9043 19:26:17.334907 25, 0x0, End_B0=25 End_B1=25
9044 19:26:17.335359 26, 0x0, End_B0=26 End_B1=26
9045 19:26:17.337824 27, 0x0, End_B0=27 End_B1=27
9046 19:26:17.341677 28, 0x0, End_B0=28 End_B1=28
9047 19:26:17.344897 29, 0x0, End_B0=29 End_B1=29
9048 19:26:17.347564 30, 0x0, End_B0=30 End_B1=30
9049 19:26:17.348006 31, 0x4545, End_B0=30 End_B1=30
9050 19:26:17.350790 Byte0 end_step=30 best_step=27
9051 19:26:17.354519 Byte1 end_step=30 best_step=27
9052 19:26:17.357478 Byte0 TX OE(2T, 0.5T) = (3, 3)
9053 19:26:17.360949 Byte1 TX OE(2T, 0.5T) = (3, 3)
9054 19:26:17.361431
9055 19:26:17.361798
9056 19:26:17.367356 [DQSOSCAuto] RK1, (LSB)MR18= 0xa07, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 404 ps
9057 19:26:17.370999 CH1 RK1: MR19=303, MR18=A07
9058 19:26:17.377434 CH1_RK1: MR19=0x303, MR18=0xA07, DQSOSC=404, MR23=63, INC=22, DEC=15
9059 19:26:17.380557 [RxdqsGatingPostProcess] freq 1600
9060 19:26:17.386974 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9061 19:26:17.390610 best DQS0 dly(2T, 0.5T) = (1, 1)
9062 19:26:17.391039 best DQS1 dly(2T, 0.5T) = (1, 1)
9063 19:26:17.393841 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9064 19:26:17.396850 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9065 19:26:17.400575 best DQS0 dly(2T, 0.5T) = (1, 1)
9066 19:26:17.403547 best DQS1 dly(2T, 0.5T) = (1, 1)
9067 19:26:17.407044 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9068 19:26:17.410238 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9069 19:26:17.413383 Pre-setting of DQS Precalculation
9070 19:26:17.416947 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9071 19:26:17.427084 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9072 19:26:17.433441 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9073 19:26:17.433876
9074 19:26:17.434243
9075 19:26:17.436484 [Calibration Summary] 3200 Mbps
9076 19:26:17.437034 CH 0, Rank 0
9077 19:26:17.439727 SW Impedance : PASS
9078 19:26:17.443630 DUTY Scan : NO K
9079 19:26:17.444245 ZQ Calibration : PASS
9080 19:26:17.446628 Jitter Meter : NO K
9081 19:26:17.447153 CBT Training : PASS
9082 19:26:17.450083 Write leveling : PASS
9083 19:26:17.453140 RX DQS gating : PASS
9084 19:26:17.453627 RX DQ/DQS(RDDQC) : PASS
9085 19:26:17.456675 TX DQ/DQS : PASS
9086 19:26:17.459617 RX DATLAT : PASS
9087 19:26:17.460158 RX DQ/DQS(Engine): PASS
9088 19:26:17.462871 TX OE : PASS
9089 19:26:17.463303 All Pass.
9090 19:26:17.463645
9091 19:26:17.466266 CH 0, Rank 1
9092 19:26:17.466719 SW Impedance : PASS
9093 19:26:17.469310 DUTY Scan : NO K
9094 19:26:17.472820 ZQ Calibration : PASS
9095 19:26:17.473249 Jitter Meter : NO K
9096 19:26:17.476039 CBT Training : PASS
9097 19:26:17.479260 Write leveling : PASS
9098 19:26:17.479726 RX DQS gating : PASS
9099 19:26:17.482701 RX DQ/DQS(RDDQC) : PASS
9100 19:26:17.486282 TX DQ/DQS : PASS
9101 19:26:17.486715 RX DATLAT : PASS
9102 19:26:17.489267 RX DQ/DQS(Engine): PASS
9103 19:26:17.492358 TX OE : PASS
9104 19:26:17.492786 All Pass.
9105 19:26:17.493127
9106 19:26:17.493490 CH 1, Rank 0
9107 19:26:17.496382 SW Impedance : PASS
9108 19:26:17.499089 DUTY Scan : NO K
9109 19:26:17.499525 ZQ Calibration : PASS
9110 19:26:17.502548 Jitter Meter : NO K
9111 19:26:17.505876 CBT Training : PASS
9112 19:26:17.506304 Write leveling : PASS
9113 19:26:17.509012 RX DQS gating : PASS
9114 19:26:17.512244 RX DQ/DQS(RDDQC) : PASS
9115 19:26:17.512673 TX DQ/DQS : PASS
9116 19:26:17.515242 RX DATLAT : PASS
9117 19:26:17.518730 RX DQ/DQS(Engine): PASS
9118 19:26:17.519398 TX OE : PASS
9119 19:26:17.521840 All Pass.
9120 19:26:17.522323
9121 19:26:17.522849 CH 1, Rank 1
9122 19:26:17.525652 SW Impedance : PASS
9123 19:26:17.526208 DUTY Scan : NO K
9124 19:26:17.528681 ZQ Calibration : PASS
9125 19:26:17.532037 Jitter Meter : NO K
9126 19:26:17.532568 CBT Training : PASS
9127 19:26:17.535219 Write leveling : PASS
9128 19:26:17.538855 RX DQS gating : PASS
9129 19:26:17.539322 RX DQ/DQS(RDDQC) : PASS
9130 19:26:17.542011 TX DQ/DQS : PASS
9131 19:26:17.542440 RX DATLAT : PASS
9132 19:26:17.545425 RX DQ/DQS(Engine): PASS
9133 19:26:17.548835 TX OE : PASS
9134 19:26:17.549425 All Pass.
9135 19:26:17.549781
9136 19:26:17.552015 DramC Write-DBI on
9137 19:26:17.552607 PER_BANK_REFRESH: Hybrid Mode
9138 19:26:17.554906 TX_TRACKING: ON
9139 19:26:17.564804 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9140 19:26:17.571542 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9141 19:26:17.578487 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9142 19:26:17.581279 [FAST_K] Save calibration result to emmc
9143 19:26:17.585055 sync common calibartion params.
9144 19:26:17.588217 sync cbt_mode0:1, 1:1
9145 19:26:17.588713 dram_init: ddr_geometry: 2
9146 19:26:17.591424 dram_init: ddr_geometry: 2
9147 19:26:17.594545 dram_init: ddr_geometry: 2
9148 19:26:17.597673 0:dram_rank_size:100000000
9149 19:26:17.598261 1:dram_rank_size:100000000
9150 19:26:17.604758 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9151 19:26:17.607913 DFS_SHUFFLE_HW_MODE: ON
9152 19:26:17.610957 dramc_set_vcore_voltage set vcore to 725000
9153 19:26:17.614500 Read voltage for 1600, 0
9154 19:26:17.615088 Vio18 = 0
9155 19:26:17.615599 Vcore = 725000
9156 19:26:17.618022 Vdram = 0
9157 19:26:17.618533 Vddq = 0
9158 19:26:17.619041 Vmddr = 0
9159 19:26:17.621119 switch to 3200 Mbps bootup
9160 19:26:17.621741 [DramcRunTimeConfig]
9161 19:26:17.624032 PHYPLL
9162 19:26:17.624608 DPM_CONTROL_AFTERK: ON
9163 19:26:17.627509 PER_BANK_REFRESH: ON
9164 19:26:17.630771 REFRESH_OVERHEAD_REDUCTION: ON
9165 19:26:17.631460 CMD_PICG_NEW_MODE: OFF
9166 19:26:17.634196 XRTWTW_NEW_MODE: ON
9167 19:26:17.634778 XRTRTR_NEW_MODE: ON
9168 19:26:17.637190 TX_TRACKING: ON
9169 19:26:17.637766 RDSEL_TRACKING: OFF
9170 19:26:17.640934 DQS Precalculation for DVFS: ON
9171 19:26:17.643975 RX_TRACKING: OFF
9172 19:26:17.644537 HW_GATING DBG: ON
9173 19:26:17.647732 ZQCS_ENABLE_LP4: ON
9174 19:26:17.648160 RX_PICG_NEW_MODE: ON
9175 19:26:17.650787 TX_PICG_NEW_MODE: ON
9176 19:26:17.653907 ENABLE_RX_DCM_DPHY: ON
9177 19:26:17.657187 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9178 19:26:17.657713 DUMMY_READ_FOR_TRACKING: OFF
9179 19:26:17.660790 !!! SPM_CONTROL_AFTERK: OFF
9180 19:26:17.663844 !!! SPM could not control APHY
9181 19:26:17.666968 IMPEDANCE_TRACKING: ON
9182 19:26:17.667570 TEMP_SENSOR: ON
9183 19:26:17.670686 HW_SAVE_FOR_SR: OFF
9184 19:26:17.671277 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9185 19:26:17.676804 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9186 19:26:17.677398 Read ODT Tracking: ON
9187 19:26:17.680429 Refresh Rate DeBounce: ON
9188 19:26:17.680917 DFS_NO_QUEUE_FLUSH: ON
9189 19:26:17.683727 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9190 19:26:17.686860 ENABLE_DFS_RUNTIME_MRW: OFF
9191 19:26:17.690226 DDR_RESERVE_NEW_MODE: ON
9192 19:26:17.693517 MR_CBT_SWITCH_FREQ: ON
9193 19:26:17.693944 =========================
9194 19:26:17.712951 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9195 19:26:17.716252 dram_init: ddr_geometry: 2
9196 19:26:17.734557 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9197 19:26:17.738130 dram_init: dram init end (result: 0)
9198 19:26:17.744362 DRAM-K: Full calibration passed in 24630 msecs
9199 19:26:17.747517 MRC: failed to locate region type 0.
9200 19:26:17.748103 DRAM rank0 size:0x100000000,
9201 19:26:17.751195 DRAM rank1 size=0x100000000
9202 19:26:17.761221 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9203 19:26:17.767553 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9204 19:26:17.774111 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9205 19:26:17.784166 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9206 19:26:17.784739 DRAM rank0 size:0x100000000,
9207 19:26:17.787399 DRAM rank1 size=0x100000000
9208 19:26:17.787840 CBMEM:
9209 19:26:17.790636 IMD: root @ 0xfffff000 254 entries.
9210 19:26:17.793592 IMD: root @ 0xffffec00 62 entries.
9211 19:26:17.797194 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9212 19:26:17.803676 WARNING: RO_VPD is uninitialized or empty.
9213 19:26:17.806794 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9214 19:26:17.814621 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9215 19:26:17.827403 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9216 19:26:17.838772 BS: romstage times (exec / console): total (unknown) / 24121 ms
9217 19:26:17.839221
9218 19:26:17.839566
9219 19:26:17.848642 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9220 19:26:17.851816 ARM64: Exception handlers installed.
9221 19:26:17.855253 ARM64: Testing exception
9222 19:26:17.858204 ARM64: Done test exception
9223 19:26:17.858407 Enumerating buses...
9224 19:26:17.861364 Show all devs... Before device enumeration.
9225 19:26:17.865056 Root Device: enabled 1
9226 19:26:17.868133 CPU_CLUSTER: 0: enabled 1
9227 19:26:17.868383 CPU: 00: enabled 1
9228 19:26:17.871239 Compare with tree...
9229 19:26:17.871561 Root Device: enabled 1
9230 19:26:17.875104 CPU_CLUSTER: 0: enabled 1
9231 19:26:17.878287 CPU: 00: enabled 1
9232 19:26:17.878560 Root Device scanning...
9233 19:26:17.881379 scan_static_bus for Root Device
9234 19:26:17.884975 CPU_CLUSTER: 0 enabled
9235 19:26:17.888177 scan_static_bus for Root Device done
9236 19:26:17.891068 scan_bus: bus Root Device finished in 8 msecs
9237 19:26:17.891288 done
9238 19:26:17.897897 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9239 19:26:17.900903 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9240 19:26:17.907427 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9241 19:26:17.914412 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9242 19:26:17.914567 Allocating resources...
9243 19:26:17.917223 Reading resources...
9244 19:26:17.920885 Root Device read_resources bus 0 link: 0
9245 19:26:17.924033 DRAM rank0 size:0x100000000,
9246 19:26:17.924187 DRAM rank1 size=0x100000000
9247 19:26:17.931010 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9248 19:26:17.931106 CPU: 00 missing read_resources
9249 19:26:17.937230 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9250 19:26:17.940823 Root Device read_resources bus 0 link: 0 done
9251 19:26:17.944078 Done reading resources.
9252 19:26:17.947260 Show resources in subtree (Root Device)...After reading.
9253 19:26:17.950362 Root Device child on link 0 CPU_CLUSTER: 0
9254 19:26:17.953548 CPU_CLUSTER: 0 child on link 0 CPU: 00
9255 19:26:17.963290 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9256 19:26:17.963401 CPU: 00
9257 19:26:17.970264 Root Device assign_resources, bus 0 link: 0
9258 19:26:17.973242 CPU_CLUSTER: 0 missing set_resources
9259 19:26:17.976818 Root Device assign_resources, bus 0 link: 0 done
9260 19:26:17.979918 Done setting resources.
9261 19:26:17.983576 Show resources in subtree (Root Device)...After assigning values.
9262 19:26:17.986848 Root Device child on link 0 CPU_CLUSTER: 0
9263 19:26:17.993037 CPU_CLUSTER: 0 child on link 0 CPU: 00
9264 19:26:17.999820 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9265 19:26:18.003171 CPU: 00
9266 19:26:18.003528 Done allocating resources.
9267 19:26:18.009813 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9268 19:26:18.012831 Enabling resources...
9269 19:26:18.013254 done.
9270 19:26:18.016271 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9271 19:26:18.019795 Initializing devices...
9272 19:26:18.020218 Root Device init
9273 19:26:18.023228 init hardware done!
9274 19:26:18.026003 0x00000018: ctrlr->caps
9275 19:26:18.026432 52.000 MHz: ctrlr->f_max
9276 19:26:18.029760 0.400 MHz: ctrlr->f_min
9277 19:26:18.032962 0x40ff8080: ctrlr->voltages
9278 19:26:18.033431 sclk: 390625
9279 19:26:18.033775 Bus Width = 1
9280 19:26:18.035833 sclk: 390625
9281 19:26:18.036252 Bus Width = 1
9282 19:26:18.039516 Early init status = 3
9283 19:26:18.042651 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9284 19:26:18.047128 in-header: 03 fc 00 00 01 00 00 00
9285 19:26:18.050260 in-data: 00
9286 19:26:18.053233 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9287 19:26:18.058900 in-header: 03 fd 00 00 00 00 00 00
9288 19:26:18.062367 in-data:
9289 19:26:18.065777 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9290 19:26:18.070116 in-header: 03 fc 00 00 01 00 00 00
9291 19:26:18.073245 in-data: 00
9292 19:26:18.076631 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9293 19:26:18.082009 in-header: 03 fd 00 00 00 00 00 00
9294 19:26:18.085435 in-data:
9295 19:26:18.088825 [SSUSB] Setting up USB HOST controller...
9296 19:26:18.091896 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9297 19:26:18.095292 [SSUSB] phy power-on done.
9298 19:26:18.098947 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9299 19:26:18.105108 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9300 19:26:18.108812 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9301 19:26:18.114868 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9302 19:26:18.121763 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9303 19:26:18.128340 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9304 19:26:18.134798 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9305 19:26:18.141687 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9306 19:26:18.144885 SPM: binary array size = 0x9dc
9307 19:26:18.147818 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9308 19:26:18.154838 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9309 19:26:18.161525 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9310 19:26:18.168031 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9311 19:26:18.170972 configure_display: Starting display init
9312 19:26:18.205273 anx7625_power_on_init: Init interface.
9313 19:26:18.208897 anx7625_disable_pd_protocol: Disabled PD feature.
9314 19:26:18.211717 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9315 19:26:18.239861 anx7625_start_dp_work: Secure OCM version=00
9316 19:26:18.243166 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9317 19:26:18.257952 sp_tx_get_edid_block: EDID Block = 1
9318 19:26:18.361082 Extracted contents:
9319 19:26:18.364504 header: 00 ff ff ff ff ff ff 00
9320 19:26:18.367401 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9321 19:26:18.370963 version: 01 04
9322 19:26:18.373861 basic params: 95 1f 11 78 0a
9323 19:26:18.377344 chroma info: 76 90 94 55 54 90 27 21 50 54
9324 19:26:18.380604 established: 00 00 00
9325 19:26:18.387311 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9326 19:26:18.390276 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9327 19:26:18.396801 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9328 19:26:18.403558 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9329 19:26:18.410303 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9330 19:26:18.413237 extensions: 00
9331 19:26:18.413713 checksum: fb
9332 19:26:18.414061
9333 19:26:18.416781 Manufacturer: IVO Model 57d Serial Number 0
9334 19:26:18.419962 Made week 0 of 2020
9335 19:26:18.420480 EDID version: 1.4
9336 19:26:18.423676 Digital display
9337 19:26:18.427348 6 bits per primary color channel
9338 19:26:18.427782 DisplayPort interface
9339 19:26:18.429797 Maximum image size: 31 cm x 17 cm
9340 19:26:18.433009 Gamma: 220%
9341 19:26:18.433584 Check DPMS levels
9342 19:26:18.436317 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9343 19:26:18.442972 First detailed timing is preferred timing
9344 19:26:18.443402 Established timings supported:
9345 19:26:18.446152 Standard timings supported:
9346 19:26:18.449852 Detailed timings
9347 19:26:18.452824 Hex of detail: 383680a07038204018303c0035ae10000019
9348 19:26:18.459342 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9349 19:26:18.462788 0780 0798 07c8 0820 hborder 0
9350 19:26:18.465552 0438 043b 0447 0458 vborder 0
9351 19:26:18.469099 -hsync -vsync
9352 19:26:18.469181 Did detailed timing
9353 19:26:18.475359 Hex of detail: 000000000000000000000000000000000000
9354 19:26:18.479104 Manufacturer-specified data, tag 0
9355 19:26:18.482103 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9356 19:26:18.485247 ASCII string: InfoVision
9357 19:26:18.488787 Hex of detail: 000000fe00523134304e574635205248200a
9358 19:26:18.492026 ASCII string: R140NWF5 RH
9359 19:26:18.492109 Checksum
9360 19:26:18.495249 Checksum: 0xfb (valid)
9361 19:26:18.498608 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9362 19:26:18.501906 DSI data_rate: 832800000 bps
9363 19:26:18.508801 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9364 19:26:18.511825 anx7625_parse_edid: pixelclock(138800).
9365 19:26:18.514952 hactive(1920), hsync(48), hfp(24), hbp(88)
9366 19:26:18.518203 vactive(1080), vsync(12), vfp(3), vbp(17)
9367 19:26:18.521791 anx7625_dsi_config: config dsi.
9368 19:26:18.528492 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9369 19:26:18.542246 anx7625_dsi_config: success to config DSI
9370 19:26:18.545427 anx7625_dp_start: MIPI phy setup OK.
9371 19:26:18.548827 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9372 19:26:18.551822 mtk_ddp_mode_set invalid vrefresh 60
9373 19:26:18.555165 main_disp_path_setup
9374 19:26:18.555316 ovl_layer_smi_id_en
9375 19:26:18.558595 ovl_layer_smi_id_en
9376 19:26:18.558709 ccorr_config
9377 19:26:18.558799 aal_config
9378 19:26:18.562215 gamma_config
9379 19:26:18.562316 postmask_config
9380 19:26:18.565257 dither_config
9381 19:26:18.568557 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9382 19:26:18.574739 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9383 19:26:18.578551 Root Device init finished in 554 msecs
9384 19:26:18.581533 CPU_CLUSTER: 0 init
9385 19:26:18.588151 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9386 19:26:18.594979 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9387 19:26:18.595063 APU_MBOX 0x190000b0 = 0x10001
9388 19:26:18.598050 APU_MBOX 0x190001b0 = 0x10001
9389 19:26:18.601618 APU_MBOX 0x190005b0 = 0x10001
9390 19:26:18.604770 APU_MBOX 0x190006b0 = 0x10001
9391 19:26:18.610882 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9392 19:26:18.621080 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9393 19:26:18.633793 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9394 19:26:18.640103 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9395 19:26:18.652080 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9396 19:26:18.661080 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9397 19:26:18.664586 CPU_CLUSTER: 0 init finished in 81 msecs
9398 19:26:18.667951 Devices initialized
9399 19:26:18.670746 Show all devs... After init.
9400 19:26:18.670843 Root Device: enabled 1
9401 19:26:18.674200 CPU_CLUSTER: 0: enabled 1
9402 19:26:18.677533 CPU: 00: enabled 1
9403 19:26:18.680983 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9404 19:26:18.684109 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9405 19:26:18.687784 ELOG: NV offset 0x57f000 size 0x1000
9406 19:26:18.694345 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9407 19:26:18.700835 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9408 19:26:18.704423 ELOG: Event(17) added with size 13 at 2024-04-18 19:26:19 UTC
9409 19:26:18.710575 out: cmd=0x121: 03 db 21 01 00 00 00 00
9410 19:26:18.714457 in-header: 03 99 00 00 2c 00 00 00
9411 19:26:18.727229 in-data: c6 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9412 19:26:18.730701 ELOG: Event(A1) added with size 10 at 2024-04-18 19:26:19 UTC
9413 19:26:18.737500 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9414 19:26:18.744072 ELOG: Event(A0) added with size 9 at 2024-04-18 19:26:19 UTC
9415 19:26:18.747200 elog_add_boot_reason: Logged dev mode boot
9416 19:26:18.753721 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9417 19:26:18.754432 Finalize devices...
9418 19:26:18.757116 Devices finalized
9419 19:26:18.760746 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9420 19:26:18.763734 Writing coreboot table at 0xffe64000
9421 19:26:18.770589 0. 000000000010a000-0000000000113fff: RAMSTAGE
9422 19:26:18.773688 1. 0000000040000000-00000000400fffff: RAM
9423 19:26:18.777238 2. 0000000040100000-000000004032afff: RAMSTAGE
9424 19:26:18.780221 3. 000000004032b000-00000000545fffff: RAM
9425 19:26:18.783503 4. 0000000054600000-000000005465ffff: BL31
9426 19:26:18.786768 5. 0000000054660000-00000000ffe63fff: RAM
9427 19:26:18.793166 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9428 19:26:18.796606 7. 0000000100000000-000000023fffffff: RAM
9429 19:26:18.800218 Passing 5 GPIOs to payload:
9430 19:26:18.803439 NAME | PORT | POLARITY | VALUE
9431 19:26:18.810084 EC in RW | 0x000000aa | low | undefined
9432 19:26:18.813056 EC interrupt | 0x00000005 | low | undefined
9433 19:26:18.819784 TPM interrupt | 0x000000ab | high | undefined
9434 19:26:18.823317 SD card detect | 0x00000011 | high | undefined
9435 19:26:18.826394 speaker enable | 0x00000093 | high | undefined
9436 19:26:18.829755 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9437 19:26:18.833315 in-header: 03 f9 00 00 02 00 00 00
9438 19:26:18.836419 in-data: 02 00
9439 19:26:18.839872 ADC[4]: Raw value=901552 ID=7
9440 19:26:18.843106 ADC[3]: Raw value=213282 ID=1
9441 19:26:18.843537 RAM Code: 0x71
9442 19:26:18.846837 ADC[6]: Raw value=75036 ID=0
9443 19:26:18.850031 ADC[5]: Raw value=212912 ID=1
9444 19:26:18.850598 SKU Code: 0x1
9445 19:26:18.856207 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 9e1
9446 19:26:18.856682 coreboot table: 964 bytes.
9447 19:26:18.859927 IMD ROOT 0. 0xfffff000 0x00001000
9448 19:26:18.862654 IMD SMALL 1. 0xffffe000 0x00001000
9449 19:26:18.866341 RO MCACHE 2. 0xffffc000 0x00001104
9450 19:26:18.869395 CONSOLE 3. 0xfff7c000 0x00080000
9451 19:26:18.873081 FMAP 4. 0xfff7b000 0x00000452
9452 19:26:18.876281 TIME STAMP 5. 0xfff7a000 0x00000910
9453 19:26:18.879169 VBOOT WORK 6. 0xfff66000 0x00014000
9454 19:26:18.882923 RAMOOPS 7. 0xffe66000 0x00100000
9455 19:26:18.885881 COREBOOT 8. 0xffe64000 0x00002000
9456 19:26:18.889050 IMD small region:
9457 19:26:18.892718 IMD ROOT 0. 0xffffec00 0x00000400
9458 19:26:18.896087 VPD 1. 0xffffeb80 0x0000006c
9459 19:26:18.898943 MMC STATUS 2. 0xffffeb60 0x00000004
9460 19:26:18.905553 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9461 19:26:18.906209 Probing TPM: done!
9462 19:26:18.912068 Connected to device vid:did:rid of 1ae0:0028:00
9463 19:26:18.918937 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9464 19:26:18.922000 Initialized TPM device CR50 revision 0
9465 19:26:18.926187 Checking cr50 for pending updates
9466 19:26:18.931513 Reading cr50 TPM mode
9467 19:26:18.939822 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9468 19:26:18.946436 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9469 19:26:18.986470 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9470 19:26:18.989522 Checking segment from ROM address 0x40100000
9471 19:26:18.993142 Checking segment from ROM address 0x4010001c
9472 19:26:18.999614 Loading segment from ROM address 0x40100000
9473 19:26:18.999720 code (compression=0)
9474 19:26:19.009283 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9475 19:26:19.015835 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9476 19:26:19.015947 it's not compressed!
9477 19:26:19.022596 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9478 19:26:19.029269 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9479 19:26:19.046797 Loading segment from ROM address 0x4010001c
9480 19:26:19.046911 Entry Point 0x80000000
9481 19:26:19.050249 Loaded segments
9482 19:26:19.053293 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9483 19:26:19.059935 Jumping to boot code at 0x80000000(0xffe64000)
9484 19:26:19.066722 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9485 19:26:19.072864 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9486 19:26:19.081252 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9487 19:26:19.084384 Checking segment from ROM address 0x40100000
9488 19:26:19.088070 Checking segment from ROM address 0x4010001c
9489 19:26:19.094289 Loading segment from ROM address 0x40100000
9490 19:26:19.094395 code (compression=1)
9491 19:26:19.101042 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9492 19:26:19.111199 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9493 19:26:19.111310 using LZMA
9494 19:26:19.119402 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9495 19:26:19.126003 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9496 19:26:19.129245 Loading segment from ROM address 0x4010001c
9497 19:26:19.133045 Entry Point 0x54601000
9498 19:26:19.133151 Loaded segments
9499 19:26:19.136059 NOTICE: MT8192 bl31_setup
9500 19:26:19.142941 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9501 19:26:19.146519 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9502 19:26:19.149769 WARNING: region 0:
9503 19:26:19.153357 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9504 19:26:19.153483 WARNING: region 1:
9505 19:26:19.159855 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9506 19:26:19.162878 WARNING: region 2:
9507 19:26:19.166081 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9508 19:26:19.169903 WARNING: region 3:
9509 19:26:19.172824 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9510 19:26:19.175971 WARNING: region 4:
9511 19:26:19.183050 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9512 19:26:19.183162 WARNING: region 5:
9513 19:26:19.186092 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9514 19:26:19.189769 WARNING: region 6:
9515 19:26:19.192858 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9516 19:26:19.196001 WARNING: region 7:
9517 19:26:19.199569 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9518 19:26:19.205799 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9519 19:26:19.209486 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9520 19:26:19.215914 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9521 19:26:19.218999 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9522 19:26:19.222607 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9523 19:26:19.229151 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9524 19:26:19.232113 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9525 19:26:19.235479 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9526 19:26:19.242351 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9527 19:26:19.245538 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9528 19:26:19.252012 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9529 19:26:19.255639 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9530 19:26:19.258582 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9531 19:26:19.265712 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9532 19:26:19.268882 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9533 19:26:19.271914 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9534 19:26:19.278838 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9535 19:26:19.281972 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9536 19:26:19.288318 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9537 19:26:19.291890 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9538 19:26:19.294987 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9539 19:26:19.301755 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9540 19:26:19.304888 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9541 19:26:19.311609 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9542 19:26:19.315631 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9543 19:26:19.318491 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9544 19:26:19.325091 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9545 19:26:19.328160 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9546 19:26:19.334932 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9547 19:26:19.338009 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9548 19:26:19.341456 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9549 19:26:19.347994 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9550 19:26:19.351320 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9551 19:26:19.354711 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9552 19:26:19.361332 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9553 19:26:19.364943 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9554 19:26:19.367914 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9555 19:26:19.371274 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9556 19:26:19.378079 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9557 19:26:19.381135 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9558 19:26:19.384396 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9559 19:26:19.387929 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9560 19:26:19.394585 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9561 19:26:19.398004 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9562 19:26:19.401010 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9563 19:26:19.404802 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9564 19:26:19.410943 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9565 19:26:19.414080 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9566 19:26:19.417939 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9567 19:26:19.424009 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9568 19:26:19.427911 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9569 19:26:19.434628 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9570 19:26:19.437919 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9571 19:26:19.443724 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9572 19:26:19.447485 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9573 19:26:19.450936 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9574 19:26:19.457368 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9575 19:26:19.460556 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9576 19:26:19.467279 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9577 19:26:19.470534 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9578 19:26:19.477090 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9579 19:26:19.480455 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9580 19:26:19.487211 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9581 19:26:19.490318 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9582 19:26:19.496937 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9583 19:26:19.500466 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9584 19:26:19.503507 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9585 19:26:19.510224 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9586 19:26:19.513253 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9587 19:26:19.520089 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9588 19:26:19.523203 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9589 19:26:19.530113 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9590 19:26:19.533070 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9591 19:26:19.536138 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9592 19:26:19.542938 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9593 19:26:19.546398 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9594 19:26:19.552813 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9595 19:26:19.556138 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9596 19:26:19.562686 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9597 19:26:19.566566 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9598 19:26:19.572653 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9599 19:26:19.576170 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9600 19:26:19.582542 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9601 19:26:19.586246 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9602 19:26:19.589481 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9603 19:26:19.595972 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9604 19:26:19.599097 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9605 19:26:19.605649 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9606 19:26:19.609159 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9607 19:26:19.615906 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9608 19:26:19.618959 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9609 19:26:19.622099 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9610 19:26:19.628976 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9611 19:26:19.632108 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9612 19:26:19.638779 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9613 19:26:19.641866 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9614 19:26:19.648504 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9615 19:26:19.652188 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9616 19:26:19.655611 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9617 19:26:19.658926 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9618 19:26:19.665606 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9619 19:26:19.668601 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9620 19:26:19.671680 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9621 19:26:19.678526 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9622 19:26:19.681735 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9623 19:26:19.688359 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9624 19:26:19.691501 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9625 19:26:19.698144 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9626 19:26:19.701862 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9627 19:26:19.704839 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9628 19:26:19.711408 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9629 19:26:19.715075 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9630 19:26:19.721169 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9631 19:26:19.724988 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9632 19:26:19.728164 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9633 19:26:19.734770 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9634 19:26:19.737974 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9635 19:26:19.740978 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9636 19:26:19.747858 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9637 19:26:19.750988 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9638 19:26:19.754708 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9639 19:26:19.757612 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9640 19:26:19.764245 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9641 19:26:19.767524 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9642 19:26:19.771070 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9643 19:26:19.777678 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9644 19:26:19.780684 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9645 19:26:19.787428 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9646 19:26:19.791076 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9647 19:26:19.794234 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9648 19:26:19.800436 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9649 19:26:19.803859 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9650 19:26:19.810430 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9651 19:26:19.813695 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9652 19:26:19.816943 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9653 19:26:19.823649 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9654 19:26:19.826999 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9655 19:26:19.830549 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9656 19:26:19.836882 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9657 19:26:19.840493 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9658 19:26:19.846718 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9659 19:26:19.850397 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9660 19:26:19.856528 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9661 19:26:19.860256 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9662 19:26:19.863490 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9663 19:26:19.870026 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9664 19:26:19.873132 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9665 19:26:19.880083 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9666 19:26:19.883352 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9667 19:26:19.886677 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9668 19:26:19.893008 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9669 19:26:19.896713 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9670 19:26:19.899808 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9671 19:26:19.906511 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9672 19:26:19.909864 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9673 19:26:19.916315 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9674 19:26:19.919591 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9675 19:26:19.925981 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9676 19:26:19.929292 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9677 19:26:19.932546 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9678 19:26:19.939243 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9679 19:26:19.942478 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9680 19:26:19.948737 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9681 19:26:19.952568 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9682 19:26:19.955533 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9683 19:26:19.962458 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9684 19:26:19.965445 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9685 19:26:19.972056 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9686 19:26:19.975341 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9687 19:26:19.978387 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9688 19:26:19.985242 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9689 19:26:19.988511 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9690 19:26:19.992016 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9691 19:26:19.998265 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9692 19:26:20.002029 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9693 19:26:20.008164 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9694 19:26:20.011883 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9695 19:26:20.018200 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9696 19:26:20.021838 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9697 19:26:20.024878 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9698 19:26:20.031379 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9699 19:26:20.034655 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9700 19:26:20.041290 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9701 19:26:20.044915 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9702 19:26:20.047951 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9703 19:26:20.054473 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9704 19:26:20.058238 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9705 19:26:20.064186 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9706 19:26:20.067495 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9707 19:26:20.070979 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9708 19:26:20.078117 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9709 19:26:20.081301 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9710 19:26:20.087862 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9711 19:26:20.091007 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9712 19:26:20.097456 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9713 19:26:20.100948 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9714 19:26:20.104342 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9715 19:26:20.110655 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9716 19:26:20.114426 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9717 19:26:20.121153 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9718 19:26:20.124195 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9719 19:26:20.130861 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9720 19:26:20.133736 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9721 19:26:20.137305 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9722 19:26:20.143606 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9723 19:26:20.147234 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9724 19:26:20.154081 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9725 19:26:20.157062 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9726 19:26:20.162961 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9727 19:26:20.166720 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9728 19:26:20.169844 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9729 19:26:20.176239 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9730 19:26:20.179924 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9731 19:26:20.186196 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9732 19:26:20.189673 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9733 19:26:20.196029 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9734 19:26:20.199600 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9735 19:26:20.202738 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9736 19:26:20.209377 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9737 19:26:20.212875 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9738 19:26:20.219127 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9739 19:26:20.222967 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9740 19:26:20.229110 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9741 19:26:20.232930 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9742 19:26:20.235923 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9743 19:26:20.242934 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9744 19:26:20.245909 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9745 19:26:20.252311 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9746 19:26:20.255424 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9747 19:26:20.259267 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9748 19:26:20.265594 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9749 19:26:20.269143 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9750 19:26:20.272057 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9751 19:26:20.275414 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9752 19:26:20.282001 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9753 19:26:20.285300 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9754 19:26:20.291884 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9755 19:26:20.294806 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9756 19:26:20.298641 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9757 19:26:20.304615 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9758 19:26:20.308276 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9759 19:26:20.311390 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9760 19:26:20.317753 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9761 19:26:20.321176 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9762 19:26:20.324367 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9763 19:26:20.331137 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9764 19:26:20.334287 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9765 19:26:20.340926 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9766 19:26:20.344413 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9767 19:26:20.347625 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9768 19:26:20.354481 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9769 19:26:20.357268 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9770 19:26:20.364200 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9771 19:26:20.367372 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9772 19:26:20.370932 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9773 19:26:20.377180 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9774 19:26:20.381009 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9775 19:26:20.383809 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9776 19:26:20.390510 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9777 19:26:20.394001 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9778 19:26:20.400383 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9779 19:26:20.403790 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9780 19:26:20.407401 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9781 19:26:20.413478 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9782 19:26:20.417253 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9783 19:26:20.420320 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9784 19:26:20.426577 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9785 19:26:20.429612 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9786 19:26:20.433225 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9787 19:26:20.439907 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9788 19:26:20.443017 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9789 19:26:20.446387 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9790 19:26:20.449708 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9791 19:26:20.452722 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9792 19:26:20.459426 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9793 19:26:20.462854 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9794 19:26:20.465796 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9795 19:26:20.472827 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9796 19:26:20.476024 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9797 19:26:20.479248 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9798 19:26:20.485876 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9799 19:26:20.489129 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9800 19:26:20.492080 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9801 19:26:20.498656 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9802 19:26:20.502106 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9803 19:26:20.508831 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9804 19:26:20.511867 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9805 19:26:20.514984 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9806 19:26:20.522109 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9807 19:26:20.525235 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9808 19:26:20.531720 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9809 19:26:20.535515 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9810 19:26:20.538297 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9811 19:26:20.544840 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9812 19:26:20.548659 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9813 19:26:20.555251 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9814 19:26:20.558027 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9815 19:26:20.561686 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9816 19:26:20.567996 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9817 19:26:20.571680 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9818 19:26:20.578466 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9819 19:26:20.581738 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9820 19:26:20.588037 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9821 19:26:20.591673 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9822 19:26:20.598542 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9823 19:26:20.601533 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9824 19:26:20.605310 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9825 19:26:20.611828 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9826 19:26:20.614935 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9827 19:26:20.621265 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9828 19:26:20.624400 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9829 19:26:20.628012 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9830 19:26:20.635000 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9831 19:26:20.637896 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9832 19:26:20.644783 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9833 19:26:20.647800 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9834 19:26:20.651061 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9835 19:26:20.657800 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9836 19:26:20.661034 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9837 19:26:20.667420 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9838 19:26:20.670832 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9839 19:26:20.674214 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9840 19:26:20.680787 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9841 19:26:20.683879 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9842 19:26:20.690828 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9843 19:26:20.693965 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9844 19:26:20.700704 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9845 19:26:20.703894 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9846 19:26:20.710867 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9847 19:26:20.713800 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9848 19:26:20.716911 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9849 19:26:20.723690 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9850 19:26:20.727008 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9851 19:26:20.733287 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9852 19:26:20.736661 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9853 19:26:20.740363 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9854 19:26:20.746827 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9855 19:26:20.750063 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9856 19:26:20.756680 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9857 19:26:20.760331 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9858 19:26:20.763299 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9859 19:26:20.770095 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9860 19:26:20.772937 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9861 19:26:20.779348 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9862 19:26:20.783211 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9863 19:26:20.789803 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9864 19:26:20.792879 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9865 19:26:20.796031 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9866 19:26:20.803070 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9867 19:26:20.806068 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9868 19:26:20.812756 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9869 19:26:20.815458 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9870 19:26:20.822678 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9871 19:26:20.825769 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9872 19:26:20.828956 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9873 19:26:20.835480 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9874 19:26:20.838533 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9875 19:26:20.845404 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9876 19:26:20.848982 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9877 19:26:20.855587 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9878 19:26:20.858603 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9879 19:26:20.861719 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9880 19:26:20.868532 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9881 19:26:20.872004 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9882 19:26:20.878447 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9883 19:26:20.881693 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9884 19:26:20.888024 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9885 19:26:20.891610 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9886 19:26:20.897855 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9887 19:26:20.901100 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9888 19:26:20.904843 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9889 19:26:20.911039 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9890 19:26:20.914721 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9891 19:26:20.921215 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9892 19:26:20.924090 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9893 19:26:20.930641 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9894 19:26:20.934401 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9895 19:26:20.940425 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9896 19:26:20.944154 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9897 19:26:20.950495 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9898 19:26:20.954210 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9899 19:26:20.957374 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9900 19:26:20.964036 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9901 19:26:20.967354 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9902 19:26:20.973956 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9903 19:26:20.976901 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9904 19:26:20.983737 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9905 19:26:20.987145 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9906 19:26:20.993308 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9907 19:26:20.996951 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9908 19:26:21.003338 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9909 19:26:21.006894 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9910 19:26:21.009823 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9911 19:26:21.016342 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9912 19:26:21.019585 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9913 19:26:21.026259 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9914 19:26:21.029310 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9915 19:26:21.035759 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9916 19:26:21.038961 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9917 19:26:21.045830 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9918 19:26:21.048937 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9919 19:26:21.052023 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9920 19:26:21.059025 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9921 19:26:21.062151 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9922 19:26:21.068950 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9923 19:26:21.072096 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9924 19:26:21.078547 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9925 19:26:21.082114 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9926 19:26:21.088497 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9927 19:26:21.091845 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9928 19:26:21.098973 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9929 19:26:21.101964 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9930 19:26:21.108533 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9931 19:26:21.111703 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9932 19:26:21.118589 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9933 19:26:21.121548 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9934 19:26:21.128219 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9935 19:26:21.131203 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9936 19:26:21.138110 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9937 19:26:21.141082 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9938 19:26:21.148081 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9939 19:26:21.150876 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9940 19:26:21.157828 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9941 19:26:21.160873 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9942 19:26:21.167931 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9943 19:26:21.170952 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9944 19:26:21.177224 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9945 19:26:21.180752 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9946 19:26:21.187382 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9947 19:26:21.190296 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9948 19:26:21.196994 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9949 19:26:21.200059 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9950 19:26:21.207021 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9951 19:26:21.209907 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9952 19:26:21.213520 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9953 19:26:21.217015 INFO: [APUAPC] vio 0
9954 19:26:21.223034 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9955 19:26:21.226441 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9956 19:26:21.229861 INFO: [APUAPC] D0_APC_0: 0x400510
9957 19:26:21.233480 INFO: [APUAPC] D0_APC_1: 0x0
9958 19:26:21.236604 INFO: [APUAPC] D0_APC_2: 0x1540
9959 19:26:21.239754 INFO: [APUAPC] D0_APC_3: 0x0
9960 19:26:21.243508 INFO: [APUAPC] D1_APC_0: 0xffffffff
9961 19:26:21.246486 INFO: [APUAPC] D1_APC_1: 0xffffffff
9962 19:26:21.249530 INFO: [APUAPC] D1_APC_2: 0x3fffff
9963 19:26:21.253048 INFO: [APUAPC] D1_APC_3: 0x0
9964 19:26:21.256674 INFO: [APUAPC] D2_APC_0: 0xffffffff
9965 19:26:21.260031 INFO: [APUAPC] D2_APC_1: 0xffffffff
9966 19:26:21.262951 INFO: [APUAPC] D2_APC_2: 0x3fffff
9967 19:26:21.266074 INFO: [APUAPC] D2_APC_3: 0x0
9968 19:26:21.269283 INFO: [APUAPC] D3_APC_0: 0xffffffff
9969 19:26:21.273002 INFO: [APUAPC] D3_APC_1: 0xffffffff
9970 19:26:21.276053 INFO: [APUAPC] D3_APC_2: 0x3fffff
9971 19:26:21.279162 INFO: [APUAPC] D3_APC_3: 0x0
9972 19:26:21.282951 INFO: [APUAPC] D4_APC_0: 0xffffffff
9973 19:26:21.286185 INFO: [APUAPC] D4_APC_1: 0xffffffff
9974 19:26:21.289216 INFO: [APUAPC] D4_APC_2: 0x3fffff
9975 19:26:21.292900 INFO: [APUAPC] D4_APC_3: 0x0
9976 19:26:21.295953 INFO: [APUAPC] D5_APC_0: 0xffffffff
9977 19:26:21.298903 INFO: [APUAPC] D5_APC_1: 0xffffffff
9978 19:26:21.302461 INFO: [APUAPC] D5_APC_2: 0x3fffff
9979 19:26:21.302615 INFO: [APUAPC] D5_APC_3: 0x0
9980 19:26:21.308940 INFO: [APUAPC] D6_APC_0: 0xffffffff
9981 19:26:21.311947 INFO: [APUAPC] D6_APC_1: 0xffffffff
9982 19:26:21.315621 INFO: [APUAPC] D6_APC_2: 0x3fffff
9983 19:26:21.315934 INFO: [APUAPC] D6_APC_3: 0x0
9984 19:26:21.322126 INFO: [APUAPC] D7_APC_0: 0xffffffff
9985 19:26:21.325947 INFO: [APUAPC] D7_APC_1: 0xffffffff
9986 19:26:21.328800 INFO: [APUAPC] D7_APC_2: 0x3fffff
9987 19:26:21.329236 INFO: [APUAPC] D7_APC_3: 0x0
9988 19:26:21.332279 INFO: [APUAPC] D8_APC_0: 0xffffffff
9989 19:26:21.338869 INFO: [APUAPC] D8_APC_1: 0xffffffff
9990 19:26:21.342016 INFO: [APUAPC] D8_APC_2: 0x3fffff
9991 19:26:21.342509 INFO: [APUAPC] D8_APC_3: 0x0
9992 19:26:21.345280 INFO: [APUAPC] D9_APC_0: 0xffffffff
9993 19:26:21.348736 INFO: [APUAPC] D9_APC_1: 0xffffffff
9994 19:26:21.352002 INFO: [APUAPC] D9_APC_2: 0x3fffff
9995 19:26:21.355126 INFO: [APUAPC] D9_APC_3: 0x0
9996 19:26:21.358981 INFO: [APUAPC] D10_APC_0: 0xffffffff
9997 19:26:21.361752 INFO: [APUAPC] D10_APC_1: 0xffffffff
9998 19:26:21.368790 INFO: [APUAPC] D10_APC_2: 0x3fffff
9999 19:26:21.369221 INFO: [APUAPC] D10_APC_3: 0x0
10000 19:26:21.371303 INFO: [APUAPC] D11_APC_0: 0xffffffff
10001 19:26:21.378261 INFO: [APUAPC] D11_APC_1: 0xffffffff
10002 19:26:21.381275 INFO: [APUAPC] D11_APC_2: 0x3fffff
10003 19:26:21.381760 INFO: [APUAPC] D11_APC_3: 0x0
10004 19:26:21.388302 INFO: [APUAPC] D12_APC_0: 0xffffffff
10005 19:26:21.391318 INFO: [APUAPC] D12_APC_1: 0xffffffff
10006 19:26:21.394897 INFO: [APUAPC] D12_APC_2: 0x3fffff
10007 19:26:21.398000 INFO: [APUAPC] D12_APC_3: 0x0
10008 19:26:21.400866 INFO: [APUAPC] D13_APC_0: 0xffffffff
10009 19:26:21.404622 INFO: [APUAPC] D13_APC_1: 0xffffffff
10010 19:26:21.407689 INFO: [APUAPC] D13_APC_2: 0x3fffff
10011 19:26:21.411279 INFO: [APUAPC] D13_APC_3: 0x0
10012 19:26:21.414128 INFO: [APUAPC] D14_APC_0: 0xffffffff
10013 19:26:21.417644 INFO: [APUAPC] D14_APC_1: 0xffffffff
10014 19:26:21.420707 INFO: [APUAPC] D14_APC_2: 0x3fffff
10015 19:26:21.424207 INFO: [APUAPC] D14_APC_3: 0x0
10016 19:26:21.427608 INFO: [APUAPC] D15_APC_0: 0xffffffff
10017 19:26:21.430579 INFO: [APUAPC] D15_APC_1: 0xffffffff
10018 19:26:21.434249 INFO: [APUAPC] D15_APC_2: 0x3fffff
10019 19:26:21.437267 INFO: [APUAPC] D15_APC_3: 0x0
10020 19:26:21.440338 INFO: [APUAPC] APC_CON: 0x4
10021 19:26:21.440761 INFO: [NOCDAPC] D0_APC_0: 0x0
10022 19:26:21.443773 INFO: [NOCDAPC] D0_APC_1: 0x0
10023 19:26:21.447149 INFO: [NOCDAPC] D1_APC_0: 0x0
10024 19:26:21.450286 INFO: [NOCDAPC] D1_APC_1: 0xfff
10025 19:26:21.453484 INFO: [NOCDAPC] D2_APC_0: 0x0
10026 19:26:21.457257 INFO: [NOCDAPC] D2_APC_1: 0xfff
10027 19:26:21.460581 INFO: [NOCDAPC] D3_APC_0: 0x0
10028 19:26:21.463766 INFO: [NOCDAPC] D3_APC_1: 0xfff
10029 19:26:21.466838 INFO: [NOCDAPC] D4_APC_0: 0x0
10030 19:26:21.470379 INFO: [NOCDAPC] D4_APC_1: 0xfff
10031 19:26:21.473472 INFO: [NOCDAPC] D5_APC_0: 0x0
10032 19:26:21.476890 INFO: [NOCDAPC] D5_APC_1: 0xfff
10033 19:26:21.477476 INFO: [NOCDAPC] D6_APC_0: 0x0
10034 19:26:21.480171 INFO: [NOCDAPC] D6_APC_1: 0xfff
10035 19:26:21.483464 INFO: [NOCDAPC] D7_APC_0: 0x0
10036 19:26:21.486425 INFO: [NOCDAPC] D7_APC_1: 0xfff
10037 19:26:21.490182 INFO: [NOCDAPC] D8_APC_0: 0x0
10038 19:26:21.493156 INFO: [NOCDAPC] D8_APC_1: 0xfff
10039 19:26:21.496465 INFO: [NOCDAPC] D9_APC_0: 0x0
10040 19:26:21.499523 INFO: [NOCDAPC] D9_APC_1: 0xfff
10041 19:26:21.503160 INFO: [NOCDAPC] D10_APC_0: 0x0
10042 19:26:21.506039 INFO: [NOCDAPC] D10_APC_1: 0xfff
10043 19:26:21.510071 INFO: [NOCDAPC] D11_APC_0: 0x0
10044 19:26:21.512946 INFO: [NOCDAPC] D11_APC_1: 0xfff
10045 19:26:21.516242 INFO: [NOCDAPC] D12_APC_0: 0x0
10046 19:26:21.519413 INFO: [NOCDAPC] D12_APC_1: 0xfff
10047 19:26:21.519847 INFO: [NOCDAPC] D13_APC_0: 0x0
10048 19:26:21.522949 INFO: [NOCDAPC] D13_APC_1: 0xfff
10049 19:26:21.526001 INFO: [NOCDAPC] D14_APC_0: 0x0
10050 19:26:21.529105 INFO: [NOCDAPC] D14_APC_1: 0xfff
10051 19:26:21.532745 INFO: [NOCDAPC] D15_APC_0: 0x0
10052 19:26:21.536012 INFO: [NOCDAPC] D15_APC_1: 0xfff
10053 19:26:21.539579 INFO: [NOCDAPC] APC_CON: 0x4
10054 19:26:21.542531 INFO: [APUAPC] set_apusys_apc done
10055 19:26:21.545576 INFO: [DEVAPC] devapc_init done
10056 19:26:21.549386 INFO: GICv3 without legacy support detected.
10057 19:26:21.555524 INFO: ARM GICv3 driver initialized in EL3
10058 19:26:21.559229 INFO: Maximum SPI INTID supported: 639
10059 19:26:21.562321 INFO: BL31: Initializing runtime services
10060 19:26:21.568923 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10061 19:26:21.569375 INFO: SPM: enable CPC mode
10062 19:26:21.575621 INFO: mcdi ready for mcusys-off-idle and system suspend
10063 19:26:21.578759 INFO: BL31: Preparing for EL3 exit to normal world
10064 19:26:21.585099 INFO: Entry point address = 0x80000000
10065 19:26:21.585563 INFO: SPSR = 0x8
10066 19:26:21.591696
10067 19:26:21.592218
10068 19:26:21.592656
10069 19:26:21.594847 Starting depthcharge on Spherion...
10070 19:26:21.595451
10071 19:26:21.595956 Wipe memory regions:
10072 19:26:21.596430
10073 19:26:21.599034 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10074 19:26:21.599696 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10075 19:26:21.600266 Setting prompt string to ['asurada:']
10076 19:26:21.600841 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10077 19:26:21.601720 [0x00000040000000, 0x00000054600000)
10078 19:26:21.720547
10079 19:26:21.721168 [0x00000054660000, 0x00000080000000)
10080 19:26:21.981290
10081 19:26:21.981827 [0x000000821a7280, 0x000000ffe64000)
10082 19:26:22.725996
10083 19:26:22.726155 [0x00000100000000, 0x00000240000000)
10084 19:26:24.615309
10085 19:26:24.618321 Initializing XHCI USB controller at 0x11200000.
10086 19:26:25.656437
10087 19:26:25.660071 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10088 19:26:25.660189
10089 19:26:25.660284
10090 19:26:25.660375
10091 19:26:25.660660 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10093 19:26:25.760998 asurada: tftpboot 192.168.201.1 13420392/tftp-deploy-6dj1q895/kernel/image.itb 13420392/tftp-deploy-6dj1q895/kernel/cmdline
10094 19:26:25.761197 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10095 19:26:25.761347 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10096 19:26:25.765824 tftpboot 192.168.201.1 13420392/tftp-deploy-6dj1q895/kernel/image.itp-deploy-6dj1q895/kernel/cmdline
10097 19:26:25.765934
10098 19:26:25.766063 Waiting for link
10099 19:26:25.926605
10100 19:26:25.927198 R8152: Initializing
10101 19:26:25.927695
10102 19:26:25.929735 Version 6 (ocp_data = 5c30)
10103 19:26:25.930104
10104 19:26:25.933093 R8152: Done initializing
10105 19:26:25.933577
10106 19:26:25.933901 Adding net device
10107 19:26:27.835895
10108 19:26:27.836079 done.
10109 19:26:27.836180
10110 19:26:27.836281 MAC: 00:e0:4c:68:02:81
10111 19:26:27.836374
10112 19:26:27.838593 Sending DHCP discover... done.
10113 19:26:27.838700
10114 19:26:36.687516 Waiting for reply... done.
10115 19:26:36.687694
10116 19:26:36.687798 Sending DHCP request... done.
10117 19:26:36.691083
10118 19:26:36.694793 Waiting for reply... done.
10119 19:26:36.694876
10120 19:26:36.694940 My ip is 192.168.201.14
10121 19:26:36.695000
10122 19:26:36.698481 The DHCP server ip is 192.168.201.1
10123 19:26:36.698571
10124 19:26:36.704849 TFTP server IP predefined by user: 192.168.201.1
10125 19:26:36.704952
10126 19:26:36.711499 Bootfile predefined by user: 13420392/tftp-deploy-6dj1q895/kernel/image.itb
10127 19:26:36.711607
10128 19:26:36.715059 Sending tftp read request... done.
10129 19:26:36.715174
10130 19:26:36.718455 Waiting for the transfer...
10131 19:26:36.718578
10132 19:26:37.258885 00000000 ################################################################
10133 19:26:37.259044
10134 19:26:37.790820 00080000 ################################################################
10135 19:26:37.791003
10136 19:26:38.325370 00100000 ################################################################
10137 19:26:38.325532
10138 19:26:38.866159 00180000 ################################################################
10139 19:26:38.866315
10140 19:26:39.455418 00200000 ################################################################
10141 19:26:39.455591
10142 19:26:40.085679 00280000 ################################################################
10143 19:26:40.085832
10144 19:26:40.625685 00300000 ################################################################
10145 19:26:40.625884
10146 19:26:41.157616 00380000 ################################################################
10147 19:26:41.157822
10148 19:26:41.702009 00400000 ################################################################
10149 19:26:41.702245
10150 19:26:42.244924 00480000 ################################################################
10151 19:26:42.245078
10152 19:26:42.803530 00500000 ################################################################
10153 19:26:42.803735
10154 19:26:43.344553 00580000 ################################################################
10155 19:26:43.344704
10156 19:26:43.881377 00600000 ################################################################
10157 19:26:43.881539
10158 19:26:44.433813 00680000 ################################################################
10159 19:26:44.433996
10160 19:26:44.972886 00700000 ################################################################
10161 19:26:44.973044
10162 19:26:45.511502 00780000 ################################################################
10163 19:26:45.511727
10164 19:26:46.034094 00800000 ################################################################
10165 19:26:46.034293
10166 19:26:46.560763 00880000 ################################################################
10167 19:26:46.560926
10168 19:26:47.086213 00900000 ################################################################
10169 19:26:47.086368
10170 19:26:47.620520 00980000 ################################################################
10171 19:26:47.620677
10172 19:26:48.147257 00a00000 ################################################################
10173 19:26:48.147430
10174 19:26:48.682915 00a80000 ################################################################
10175 19:26:48.683047
10176 19:26:49.229243 00b00000 ################################################################
10177 19:26:49.229402
10178 19:26:49.933822 00b80000 ################################################################
10179 19:26:49.934008
10180 19:26:50.278841 00c00000 ################################################################
10181 19:26:50.278979
10182 19:26:50.825122 00c80000 ################################################################
10183 19:26:50.825275
10184 19:26:51.372849 00d00000 ################################################################
10185 19:26:51.373057
10186 19:26:51.927108 00d80000 ################################################################
10187 19:26:51.927350
10188 19:26:52.477636 00e00000 ################################################################
10189 19:26:52.477785
10190 19:26:53.033259 00e80000 ################################################################
10191 19:26:53.033425
10192 19:26:53.582527 00f00000 ################################################################
10193 19:26:53.582668
10194 19:26:54.120797 00f80000 ################################################################
10195 19:26:54.120947
10196 19:26:54.658351 01000000 ################################################################
10197 19:26:54.658510
10198 19:26:55.216598 01080000 ################################################################
10199 19:26:55.216753
10200 19:26:55.767996 01100000 ################################################################
10201 19:26:55.768161
10202 19:26:56.300758 01180000 ################################################################
10203 19:26:56.300946
10204 19:26:56.830178 01200000 ################################################################
10205 19:26:56.830370
10206 19:26:57.355756 01280000 ################################################################
10207 19:26:57.355936
10208 19:26:57.882597 01300000 ################################################################
10209 19:26:57.882762
10210 19:26:58.409023 01380000 ################################################################
10211 19:26:58.409175
10212 19:26:58.969906 01400000 ################################################################
10213 19:26:58.970703
10214 19:26:59.578607 01480000 ################################################################
10215 19:26:59.579274
10216 19:27:00.125644 01500000 ################################################################
10217 19:27:00.125797
10218 19:27:00.675186 01580000 ################################################################
10219 19:27:00.675332
10220 19:27:01.204339 01600000 ################################################################
10221 19:27:01.204510
10222 19:27:01.724155 01680000 ################################################################
10223 19:27:01.724325
10224 19:27:02.257101 01700000 ################################################################
10225 19:27:02.257269
10226 19:27:02.794673 01780000 ################################################################
10227 19:27:02.794820
10228 19:27:03.313034 01800000 ################################################################
10229 19:27:03.313214
10230 19:27:03.837265 01880000 ################################################################
10231 19:27:03.837424
10232 19:27:04.368768 01900000 ################################################################
10233 19:27:04.368948
10234 19:27:04.899633 01980000 ################################################################
10235 19:27:04.899814
10236 19:27:05.437352 01a00000 ################################################################
10237 19:27:05.437518
10238 19:27:05.984810 01a80000 ################################################################
10239 19:27:05.984954
10240 19:27:06.526884 01b00000 ################################################################
10241 19:27:06.527117
10242 19:27:07.060001 01b80000 ################################################################
10243 19:27:07.060139
10244 19:27:07.598074 01c00000 ################################################################
10245 19:27:07.598282
10246 19:27:08.123260 01c80000 ################################################################
10247 19:27:08.123399
10248 19:27:08.679604 01d00000 ################################################################
10249 19:27:08.679744
10250 19:27:09.252799 01d80000 ################################################################
10251 19:27:09.252942
10252 19:27:09.810987 01e00000 ################################################################
10253 19:27:09.811140
10254 19:27:10.478222 01e80000 ################################################################
10255 19:27:10.478400
10256 19:27:10.974714 01f00000 ################################################################
10257 19:27:10.975017
10258 19:27:11.585071 01f80000 ################################################################
10259 19:27:11.585811
10260 19:27:12.187525 02000000 ################################################################
10261 19:27:12.188195
10262 19:27:12.780031 02080000 ################################################################
10263 19:27:12.780166
10264 19:27:13.323205 02100000 ################################################################
10265 19:27:13.323368
10266 19:27:13.899018 02180000 ################################################################
10267 19:27:13.899616
10268 19:27:14.432284 02200000 ################################################################
10269 19:27:14.432437
10270 19:27:14.960659 02280000 ################################################################
10271 19:27:14.960826
10272 19:27:15.507926 02300000 ################################################################
10273 19:27:15.508067
10274 19:27:16.165986 02380000 ################################################################
10275 19:27:16.166223
10276 19:27:16.614877 02400000 ################################################################
10277 19:27:16.615041
10278 19:27:17.150744 02480000 ################################################################
10279 19:27:17.150909
10280 19:27:17.675517 02500000 ################################################################
10281 19:27:17.675685
10282 19:27:18.278197 02580000 ################################################################
10283 19:27:18.278721
10284 19:27:18.834349 02600000 ################################################################
10285 19:27:18.834499
10286 19:27:19.401648 02680000 ################################################################
10287 19:27:19.402282
10288 19:27:19.981258 02700000 ################################################################
10289 19:27:19.981473
10290 19:27:20.512822 02780000 ################################################################
10291 19:27:20.512963
10292 19:27:21.032985 02800000 ################################################################
10293 19:27:21.033202
10294 19:27:21.567568 02880000 ################################################################
10295 19:27:21.567720
10296 19:27:22.115133 02900000 ################################################################
10297 19:27:22.115273
10298 19:27:22.652735 02980000 ################################################################
10299 19:27:22.652899
10300 19:27:23.206728 02a00000 ################################################################
10301 19:27:23.206867
10302 19:27:23.744604 02a80000 ################################################################
10303 19:27:23.744791
10304 19:27:24.292299 02b00000 ################################################################
10305 19:27:24.292451
10306 19:27:24.850887 02b80000 ################################################################
10307 19:27:24.851021
10308 19:27:25.382836 02c00000 ################################################################
10309 19:27:25.382985
10310 19:27:25.936953 02c80000 ################################################################
10311 19:27:25.937128
10312 19:27:26.489140 02d00000 ################################################################
10313 19:27:26.489278
10314 19:27:27.030682 02d80000 ################################################################
10315 19:27:27.030854
10316 19:27:27.577223 02e00000 ################################################################
10317 19:27:27.577432
10318 19:27:28.141648 02e80000 ################################################################
10319 19:27:28.141785
10320 19:27:28.700830 02f00000 ################################################################
10321 19:27:28.700965
10322 19:27:29.294654 02f80000 ################################################################
10323 19:27:29.295155
10324 19:27:29.903575 03000000 ################################################################
10325 19:27:29.903715
10326 19:27:30.441764 03080000 ################################################################
10327 19:27:30.441904
10328 19:27:31.004642 03100000 ################################################################
10329 19:27:31.004779
10330 19:27:31.589285 03180000 ################################################################
10331 19:27:31.589452
10332 19:27:32.164920 03200000 ################################################################
10333 19:27:32.165059
10334 19:27:32.724679 03280000 ################################################################
10335 19:27:32.724820
10336 19:27:33.304842 03300000 ################################################################
10337 19:27:33.304982
10338 19:27:33.904376 03380000 ################################################################
10339 19:27:33.904523
10340 19:27:34.497051 03400000 ################################################################
10341 19:27:34.497198
10342 19:27:35.086056 03480000 ################################################################
10343 19:27:35.086230
10344 19:27:35.693686 03500000 ################################################################
10345 19:27:35.693839
10346 19:27:36.299885 03580000 ################################################################
10347 19:27:36.300023
10348 19:27:36.841237 03600000 ################################################################
10349 19:27:36.841422
10350 19:27:37.401898 03680000 ################################################################
10351 19:27:37.402031
10352 19:27:38.018521 03700000 ################################################################
10353 19:27:38.019045
10354 19:27:38.564738 03780000 ################################################################
10355 19:27:38.564922
10356 19:27:39.128007 03800000 ################################################################
10357 19:27:39.128151
10358 19:27:39.682787 03880000 ################################################################
10359 19:27:39.682941
10360 19:27:40.267546 03900000 ################################################################
10361 19:27:40.267684
10362 19:27:40.833818 03980000 ################################################################
10363 19:27:40.833992
10364 19:27:41.406266 03a00000 ################################################################
10365 19:27:41.406463
10366 19:27:41.965886 03a80000 ################################################################
10367 19:27:41.966059
10368 19:27:42.554063 03b00000 ################################################################
10369 19:27:42.554223
10370 19:27:43.161532 03b80000 ################################################################
10371 19:27:43.162153
10372 19:27:43.766407 03c00000 ################################################################
10373 19:27:43.766556
10374 19:27:44.334192 03c80000 ################################################################
10375 19:27:44.334365
10376 19:27:44.892198 03d00000 ################################################################
10377 19:27:44.892406
10378 19:27:45.480482 03d80000 ################################################################
10379 19:27:45.480625
10380 19:27:46.099234 03e00000 ################################################################
10381 19:27:46.099719
10382 19:27:46.702586 03e80000 ################################################################
10383 19:27:46.702737
10384 19:27:47.290640 03f00000 ################################################################
10385 19:27:47.290836
10386 19:27:47.892803 03f80000 ################################################################
10387 19:27:47.892944
10388 19:27:48.494816 04000000 ################################################################
10389 19:27:48.494968
10390 19:27:49.077641 04080000 ################################################################
10391 19:27:49.077792
10392 19:27:49.731661 04100000 ################################################################
10393 19:27:49.731810
10394 19:27:50.304548 04180000 ################################################################
10395 19:27:50.304703
10396 19:27:50.849555 04200000 ################################################################
10397 19:27:50.849710
10398 19:27:51.453109 04280000 ################################################################
10399 19:27:51.453762
10400 19:27:52.043670 04300000 ################################################################
10401 19:27:52.043821
10402 19:27:52.586469 04380000 ################################################################
10403 19:27:52.586629
10404 19:27:53.145689 04400000 ################################################################
10405 19:27:53.145835
10406 19:27:53.698662 04480000 ################################################################
10407 19:27:53.698816
10408 19:27:54.232115 04500000 ################################################################
10409 19:27:54.232259
10410 19:27:54.772913 04580000 ################################################################
10411 19:27:54.773092
10412 19:27:55.300751 04600000 ################################################################
10413 19:27:55.300901
10414 19:27:55.377230 04680000 ########## done.
10415 19:27:55.377421
10416 19:27:55.380975 The bootfile was 73999946 bytes long.
10417 19:27:55.381059
10418 19:27:55.384176 Sending tftp read request... done.
10419 19:27:55.384288
10420 19:27:55.387294 Waiting for the transfer...
10421 19:27:55.387378
10422 19:27:55.387444 00000000 # done.
10423 19:27:55.387508
10424 19:27:55.397476 Command line loaded dynamically from TFTP file: 13420392/tftp-deploy-6dj1q895/kernel/cmdline
10425 19:27:55.397561
10426 19:27:55.410780 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10427 19:27:55.410867
10428 19:27:55.410933 Loading FIT.
10429 19:27:55.410994
10430 19:27:55.413576 Image ramdisk-1 has 61040325 bytes.
10431 19:27:55.413659
10432 19:27:55.416834 Image fdt-1 has 47230 bytes.
10433 19:27:55.416918
10434 19:27:55.420448 Image kernel-1 has 12910355 bytes.
10435 19:27:55.420523
10436 19:27:55.430319 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10437 19:27:55.430404
10438 19:27:55.446345 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10439 19:27:55.446435
10440 19:27:55.453449 Choosing best match conf-1 for compat google,spherion-rev2.
10441 19:27:55.453533
10442 19:27:55.460046 Connected to device vid:did:rid of 1ae0:0028:00
10443 19:27:55.467740
10444 19:27:55.470639 tpm_get_response: command 0x17b, return code 0x0
10445 19:27:55.470723
10446 19:27:55.474247 ec_init: CrosEC protocol v3 supported (256, 248)
10447 19:27:55.477903
10448 19:27:55.481615 tpm_cleanup: add release locality here.
10449 19:27:55.481699
10450 19:27:55.481765 Shutting down all USB controllers.
10451 19:27:55.484685
10452 19:27:55.484769 Removing current net device
10453 19:27:55.484836
10454 19:27:55.491407 Exiting depthcharge with code 4 at timestamp: 123352999
10455 19:27:55.491491
10456 19:27:55.494552 LZMA decompressing kernel-1 to 0x821a6718
10457 19:27:55.494636
10458 19:27:55.498088 LZMA decompressing kernel-1 to 0x40000000
10459 19:27:57.092185
10460 19:27:57.092343 jumping to kernel
10461 19:27:57.092873 end: 2.2.4 bootloader-commands (duration 00:01:35) [common]
10462 19:27:57.092975 start: 2.2.5 auto-login-action (timeout 00:02:50) [common]
10463 19:27:57.093068 Setting prompt string to ['Linux version [0-9]']
10464 19:27:57.093153 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10465 19:27:57.093221 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10466 19:27:57.174125
10467 19:27:57.177742 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10468 19:27:57.181200 start: 2.2.5.1 login-action (timeout 00:02:49) [common]
10469 19:27:57.181297 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10470 19:27:57.181414 Setting prompt string to []
10471 19:27:57.181497 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10472 19:27:57.181573 Using line separator: #'\n'#
10473 19:27:57.181635 No login prompt set.
10474 19:27:57.181698 Parsing kernel messages
10475 19:27:57.181755 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10476 19:27:57.181862 [login-action] Waiting for messages, (timeout 00:02:49)
10477 19:27:57.181928 Waiting using forced prompt support (timeout 00:01:25)
10478 19:27:57.201050 [ 0.000000] Linux version 6.1.86-cip19 (KernelCI@build-j170728-arm64-gcc-10-defconfig-arm64-chromebook-wrkxq) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Apr 18 19:05:54 UTC 2024
10479 19:27:57.203779 [ 0.000000] random: crng init done
10480 19:27:57.210691 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10481 19:27:57.214141 [ 0.000000] efi: UEFI not found.
10482 19:27:57.220634 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10483 19:27:57.230476 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10484 19:27:57.236781 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10485 19:27:57.246726 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10486 19:27:57.253274 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10487 19:27:57.259941 [ 0.000000] printk: bootconsole [mtk8250] enabled
10488 19:27:57.266768 [ 0.000000] NUMA: No NUMA configuration found
10489 19:27:57.273438 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10490 19:27:57.280064 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10491 19:27:57.280174 [ 0.000000] Zone ranges:
10492 19:27:57.286153 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10493 19:27:57.289917 [ 0.000000] DMA32 empty
10494 19:27:57.296366 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10495 19:27:57.299473 [ 0.000000] Movable zone start for each node
10496 19:27:57.303174 [ 0.000000] Early memory node ranges
10497 19:27:57.309467 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10498 19:27:57.316223 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10499 19:27:57.322607 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10500 19:27:57.329413 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10501 19:27:57.335602 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10502 19:27:57.342308 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10503 19:27:57.398955 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10504 19:27:57.405681 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10505 19:27:57.411945 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10506 19:27:57.415563 [ 0.000000] psci: probing for conduit method from DT.
10507 19:27:57.422187 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10508 19:27:57.425082 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10509 19:27:57.431761 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10510 19:27:57.435020 [ 0.000000] psci: SMC Calling Convention v1.2
10511 19:27:57.441787 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10512 19:27:57.444974 [ 0.000000] Detected VIPT I-cache on CPU0
10513 19:27:57.451884 [ 0.000000] CPU features: detected: GIC system register CPU interface
10514 19:27:57.457950 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10515 19:27:57.464599 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10516 19:27:57.471328 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10517 19:27:57.481117 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10518 19:27:57.487878 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10519 19:27:57.491002 [ 0.000000] alternatives: applying boot alternatives
10520 19:27:57.497261 [ 0.000000] Fallback order for Node 0: 0
10521 19:27:57.503853 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10522 19:27:57.507334 [ 0.000000] Policy zone: Normal
10523 19:27:57.520503 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10524 19:27:57.530418 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10525 19:27:57.542713 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10526 19:27:57.553195 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10527 19:27:57.559303 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10528 19:27:57.563068 <6>[ 0.000000] software IO TLB: area num 8.
10529 19:27:57.619267 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10530 19:27:57.768537 <6>[ 0.000000] Memory: 7904960K/8385536K available (18048K kernel code, 4118K rwdata, 22288K rodata, 8448K init, 616K bss, 447808K reserved, 32768K cma-reserved)
10531 19:27:57.775378 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10532 19:27:57.782239 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10533 19:27:57.784966 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10534 19:27:57.791839 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10535 19:27:57.798036 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10536 19:27:57.801766 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10537 19:27:57.811612 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10538 19:27:57.817902 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10539 19:27:57.824846 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10540 19:27:57.831464 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10541 19:27:57.834729 <6>[ 0.000000] GICv3: 608 SPIs implemented
10542 19:27:57.837760 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10543 19:27:57.844331 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10544 19:27:57.847902 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10545 19:27:57.854206 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10546 19:27:57.867472 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10547 19:27:57.880704 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10548 19:27:57.886881 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10549 19:27:57.895439 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10550 19:27:57.908100 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10551 19:27:57.914824 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10552 19:27:57.921706 <6>[ 0.009180] Console: colour dummy device 80x25
10553 19:27:57.931527 <6>[ 0.013899] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10554 19:27:57.937984 <6>[ 0.024341] pid_max: default: 32768 minimum: 301
10555 19:27:57.941103 <6>[ 0.029212] LSM: Security Framework initializing
10556 19:27:57.948006 <6>[ 0.034179] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10557 19:27:57.957550 <6>[ 0.041994] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10558 19:27:57.967349 <6>[ 0.051400] cblist_init_generic: Setting adjustable number of callback queues.
10559 19:27:57.973996 <6>[ 0.058889] cblist_init_generic: Setting shift to 3 and lim to 1.
10560 19:27:57.980621 <6>[ 0.065267] cblist_init_generic: Setting adjustable number of callback queues.
10561 19:27:57.987358 <6>[ 0.072693] cblist_init_generic: Setting shift to 3 and lim to 1.
10562 19:27:57.990941 <6>[ 0.079095] rcu: Hierarchical SRCU implementation.
10563 19:27:57.997656 <6>[ 0.084109] rcu: Max phase no-delay instances is 1000.
10564 19:27:58.003710 <6>[ 0.091129] EFI services will not be available.
10565 19:27:58.007165 <6>[ 0.096114] smp: Bringing up secondary CPUs ...
10566 19:27:58.015993 <6>[ 0.101158] Detected VIPT I-cache on CPU1
10567 19:27:58.022807 <6>[ 0.101228] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10568 19:27:58.029125 <6>[ 0.101262] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10569 19:27:58.032255 <6>[ 0.101594] Detected VIPT I-cache on CPU2
10570 19:27:58.042563 <6>[ 0.101647] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10571 19:27:58.049266 <6>[ 0.101665] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10572 19:27:58.052615 <6>[ 0.101926] Detected VIPT I-cache on CPU3
10573 19:27:58.059191 <6>[ 0.101975] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10574 19:27:58.065246 <6>[ 0.101989] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10575 19:27:58.071789 <6>[ 0.102293] CPU features: detected: Spectre-v4
10576 19:27:58.075294 <6>[ 0.102299] CPU features: detected: Spectre-BHB
10577 19:27:58.078415 <6>[ 0.102304] Detected PIPT I-cache on CPU4
10578 19:27:58.085219 <6>[ 0.102363] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10579 19:27:58.091696 <6>[ 0.102380] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10580 19:27:58.098600 <6>[ 0.102677] Detected PIPT I-cache on CPU5
10581 19:27:58.105032 <6>[ 0.102740] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10582 19:27:58.111463 <6>[ 0.102757] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10583 19:27:58.115251 <6>[ 0.103037] Detected PIPT I-cache on CPU6
10584 19:27:58.121320 <6>[ 0.103102] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10585 19:27:58.131440 <6>[ 0.103118] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10586 19:27:58.134647 <6>[ 0.103413] Detected PIPT I-cache on CPU7
10587 19:27:58.141018 <6>[ 0.103480] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10588 19:27:58.147698 <6>[ 0.103496] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10589 19:27:58.151142 <6>[ 0.103543] smp: Brought up 1 node, 8 CPUs
10590 19:27:58.157782 <6>[ 0.244881] SMP: Total of 8 processors activated.
10591 19:27:58.164402 <6>[ 0.249803] CPU features: detected: 32-bit EL0 Support
10592 19:27:58.171107 <6>[ 0.255200] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10593 19:27:58.177070 <6>[ 0.264000] CPU features: detected: Common not Private translations
10594 19:27:58.184012 <6>[ 0.270476] CPU features: detected: CRC32 instructions
10595 19:27:58.190410 <6>[ 0.275861] CPU features: detected: RCpc load-acquire (LDAPR)
10596 19:27:58.194001 <6>[ 0.281820] CPU features: detected: LSE atomic instructions
10597 19:27:58.200070 <6>[ 0.287602] CPU features: detected: Privileged Access Never
10598 19:27:58.206895 <6>[ 0.293418] CPU features: detected: RAS Extension Support
10599 19:27:58.213762 <6>[ 0.299026] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10600 19:27:58.216843 <6>[ 0.306294] CPU: All CPU(s) started at EL2
10601 19:27:58.223574 <6>[ 0.310637] alternatives: applying system-wide alternatives
10602 19:27:58.233596 <6>[ 0.321443] devtmpfs: initialized
10603 19:27:58.249646 <6>[ 0.330395] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10604 19:27:58.255712 <6>[ 0.340355] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10605 19:27:58.262590 <6>[ 0.348550] pinctrl core: initialized pinctrl subsystem
10606 19:27:58.265725 <6>[ 0.355197] DMI not present or invalid.
10607 19:27:58.272275 <6>[ 0.359612] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10608 19:27:58.282078 <6>[ 0.366449] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10609 19:27:58.288991 <6>[ 0.374038] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10610 19:27:58.298509 <6>[ 0.382264] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10611 19:27:58.302367 <6>[ 0.390502] audit: initializing netlink subsys (disabled)
10612 19:27:58.312099 <5>[ 0.396199] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10613 19:27:58.318368 <6>[ 0.396899] thermal_sys: Registered thermal governor 'step_wise'
10614 19:27:58.325098 <6>[ 0.404162] thermal_sys: Registered thermal governor 'power_allocator'
10615 19:27:58.328502 <6>[ 0.410415] cpuidle: using governor menu
10616 19:27:58.335457 <6>[ 0.421378] NET: Registered PF_QIPCRTR protocol family
10617 19:27:58.342031 <6>[ 0.426861] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10618 19:27:58.348146 <6>[ 0.433962] ASID allocator initialised with 32768 entries
10619 19:27:58.351826 <6>[ 0.440527] Serial: AMBA PL011 UART driver
10620 19:27:58.362041 <4>[ 0.449250] Trying to register duplicate clock ID: 134
10621 19:27:58.417834 <6>[ 0.508827] KASLR enabled
10622 19:27:58.432230 <6>[ 0.516508] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10623 19:27:58.438633 <6>[ 0.523523] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10624 19:27:58.445587 <6>[ 0.530014] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10625 19:27:58.452396 <6>[ 0.537020] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10626 19:27:58.458852 <6>[ 0.543505] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10627 19:27:58.465133 <6>[ 0.550511] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10628 19:27:58.471801 <6>[ 0.556997] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10629 19:27:58.478452 <6>[ 0.564002] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10630 19:27:58.481658 <6>[ 0.571524] ACPI: Interpreter disabled.
10631 19:27:58.490308 <6>[ 0.577947] iommu: Default domain type: Translated
10632 19:27:58.497120 <6>[ 0.583062] iommu: DMA domain TLB invalidation policy: strict mode
10633 19:27:58.500340 <5>[ 0.589729] SCSI subsystem initialized
10634 19:27:58.506733 <6>[ 0.593908] usbcore: registered new interface driver usbfs
10635 19:27:58.513540 <6>[ 0.599642] usbcore: registered new interface driver hub
10636 19:27:58.516860 <6>[ 0.605194] usbcore: registered new device driver usb
10637 19:27:58.523764 <6>[ 0.611295] pps_core: LinuxPPS API ver. 1 registered
10638 19:27:58.533393 <6>[ 0.616484] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10639 19:27:58.536593 <6>[ 0.625827] PTP clock support registered
10640 19:27:58.539915 <6>[ 0.630067] EDAC MC: Ver: 3.0.0
10641 19:27:58.547714 <6>[ 0.635197] FPGA manager framework
10642 19:27:58.554480 <6>[ 0.638875] Advanced Linux Sound Architecture Driver Initialized.
10643 19:27:58.557497 <6>[ 0.645668] vgaarb: loaded
10644 19:27:58.564319 <6>[ 0.648853] clocksource: Switched to clocksource arch_sys_counter
10645 19:27:58.567313 <5>[ 0.655302] VFS: Disk quotas dquot_6.6.0
10646 19:27:58.573845 <6>[ 0.659489] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10647 19:27:58.576920 <6>[ 0.666677] pnp: PnP ACPI: disabled
10648 19:27:58.585658 <6>[ 0.673357] NET: Registered PF_INET protocol family
10649 19:27:58.595392 <6>[ 0.678953] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10650 19:27:58.606936 <6>[ 0.691272] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10651 19:27:58.616811 <6>[ 0.700083] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10652 19:27:58.623224 <6>[ 0.708059] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10653 19:27:58.633115 <6>[ 0.716758] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10654 19:27:58.639843 <6>[ 0.726516] TCP: Hash tables configured (established 65536 bind 65536)
10655 19:27:58.646206 <6>[ 0.733382] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10656 19:27:58.656694 <6>[ 0.740580] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10657 19:27:58.662844 <6>[ 0.748281] NET: Registered PF_UNIX/PF_LOCAL protocol family
10658 19:27:58.669152 <6>[ 0.754437] RPC: Registered named UNIX socket transport module.
10659 19:27:58.672773 <6>[ 0.760591] RPC: Registered udp transport module.
10660 19:27:58.679349 <6>[ 0.765521] RPC: Registered tcp transport module.
10661 19:27:58.685996 <6>[ 0.770453] RPC: Registered tcp NFSv4.1 backchannel transport module.
10662 19:27:58.689464 <6>[ 0.777117] PCI: CLS 0 bytes, default 64
10663 19:27:58.692233 <6>[ 0.781467] Unpacking initramfs...
10664 19:27:58.716807 <6>[ 0.800973] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10665 19:27:58.726200 <6>[ 0.809663] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10666 19:27:58.729786 <6>[ 0.818483] kvm [1]: IPA Size Limit: 40 bits
10667 19:27:58.736134 <6>[ 0.823011] kvm [1]: GICv3: no GICV resource entry
10668 19:27:58.739500 <6>[ 0.828033] kvm [1]: disabling GICv2 emulation
10669 19:27:58.746356 <6>[ 0.832719] kvm [1]: GIC system register CPU interface enabled
10670 19:27:58.749314 <6>[ 0.838910] kvm [1]: vgic interrupt IRQ18
10671 19:27:58.755846 <6>[ 0.843286] kvm [1]: VHE mode initialized successfully
10672 19:27:58.762474 <5>[ 0.849840] Initialise system trusted keyrings
10673 19:27:58.769222 <6>[ 0.854620] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10674 19:27:58.777419 <6>[ 0.864710] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10675 19:27:58.783545 <5>[ 0.871135] NFS: Registering the id_resolver key type
10676 19:27:58.787280 <5>[ 0.876440] Key type id_resolver registered
10677 19:27:58.793794 <5>[ 0.880854] Key type id_legacy registered
10678 19:27:58.800001 <6>[ 0.885131] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10679 19:27:58.806675 <6>[ 0.892050] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10680 19:27:58.813065 <6>[ 0.899751] 9p: Installing v9fs 9p2000 file system support
10681 19:27:58.850720 <5>[ 0.938242] Key type asymmetric registered
10682 19:27:58.853927 <5>[ 0.942572] Asymmetric key parser 'x509' registered
10683 19:27:58.863595 <6>[ 0.947726] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10684 19:27:58.866976 <6>[ 0.955343] io scheduler mq-deadline registered
10685 19:27:58.870046 <6>[ 0.960108] io scheduler kyber registered
10686 19:27:58.889263 <6>[ 0.977110] EINJ: ACPI disabled.
10687 19:27:58.921799 <4>[ 1.002904] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10688 19:27:58.931574 <4>[ 1.013524] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10689 19:27:58.946548 <6>[ 1.034112] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10690 19:27:58.954549 <6>[ 1.042149] printk: console [ttyS0] disabled
10691 19:27:58.982364 <6>[ 1.066780] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10692 19:27:58.989141 <6>[ 1.076252] printk: console [ttyS0] enabled
10693 19:27:58.992370 <6>[ 1.076252] printk: console [ttyS0] enabled
10694 19:27:58.998668 <6>[ 1.085144] printk: bootconsole [mtk8250] disabled
10695 19:27:59.002470 <6>[ 1.085144] printk: bootconsole [mtk8250] disabled
10696 19:27:59.009087 <6>[ 1.096189] SuperH (H)SCI(F) driver initialized
10697 19:27:59.011923 <6>[ 1.101462] msm_serial: driver initialized
10698 19:27:59.026217 <6>[ 1.110358] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10699 19:27:59.035797 <6>[ 1.118908] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10700 19:27:59.042365 <6>[ 1.127450] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10701 19:27:59.052430 <6>[ 1.136076] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10702 19:27:59.062135 <6>[ 1.144784] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10703 19:27:59.068884 <6>[ 1.153498] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10704 19:27:59.078608 <6>[ 1.162038] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10705 19:27:59.085280 <6>[ 1.170836] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10706 19:27:59.094864 <6>[ 1.179378] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10707 19:27:59.107461 <6>[ 1.195005] loop: module loaded
10708 19:27:59.113670 <6>[ 1.200817] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10709 19:27:59.136481 <4>[ 1.224170] mtk-pmic-keys: Failed to locate of_node [id: -1]
10710 19:27:59.143398 <6>[ 1.231020] megasas: 07.719.03.00-rc1
10711 19:27:59.152842 <6>[ 1.240761] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10712 19:27:59.160520 <6>[ 1.248250] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10713 19:27:59.177115 <6>[ 1.264847] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10714 19:27:59.237569 <6>[ 1.318462] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10715 19:28:01.392626 <6>[ 3.480804] Freeing initrd memory: 59608K
10716 19:28:01.404431 <6>[ 3.492537] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10717 19:28:01.415770 <6>[ 3.503548] tun: Universal TUN/TAP device driver, 1.6
10718 19:28:01.418806 <6>[ 3.509613] thunder_xcv, ver 1.0
10719 19:28:01.421802 <6>[ 3.513121] thunder_bgx, ver 1.0
10720 19:28:01.425636 <6>[ 3.516614] nicpf, ver 1.0
10721 19:28:01.435892 <6>[ 3.520648] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10722 19:28:01.439403 <6>[ 3.528125] hns3: Copyright (c) 2017 Huawei Corporation.
10723 19:28:01.446214 <6>[ 3.533712] hclge is initializing
10724 19:28:01.449179 <6>[ 3.537288] e1000: Intel(R) PRO/1000 Network Driver
10725 19:28:01.455476 <6>[ 3.542417] e1000: Copyright (c) 1999-2006 Intel Corporation.
10726 19:28:01.462245 <6>[ 3.548434] e1000e: Intel(R) PRO/1000 Network Driver
10727 19:28:01.465342 <6>[ 3.553651] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10728 19:28:01.472129 <6>[ 3.559836] igb: Intel(R) Gigabit Ethernet Network Driver
10729 19:28:01.478956 <6>[ 3.565486] igb: Copyright (c) 2007-2014 Intel Corporation.
10730 19:28:01.485069 <6>[ 3.571324] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10731 19:28:01.491893 <6>[ 3.577842] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10732 19:28:01.494973 <6>[ 3.584308] sky2: driver version 1.30
10733 19:28:01.501546 <6>[ 3.589316] VFIO - User Level meta-driver version: 0.3
10734 19:28:01.509242 <6>[ 3.597575] usbcore: registered new interface driver usb-storage
10735 19:28:01.515745 <6>[ 3.604018] usbcore: registered new device driver onboard-usb-hub
10736 19:28:01.525071 <6>[ 3.613229] mt6397-rtc mt6359-rtc: registered as rtc0
10737 19:28:01.535124 <6>[ 3.618696] mt6397-rtc mt6359-rtc: setting system clock to 2024-04-18T19:28:01 UTC (1713468481)
10738 19:28:01.538785 <6>[ 3.628270] i2c_dev: i2c /dev entries driver
10739 19:28:01.555371 <6>[ 3.640078] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10740 19:28:01.561728 <4>[ 3.648818] cpu cpu0: supply cpu not found, using dummy regulator
10741 19:28:01.568683 <4>[ 3.655255] cpu cpu1: supply cpu not found, using dummy regulator
10742 19:28:01.575494 <4>[ 3.661660] cpu cpu2: supply cpu not found, using dummy regulator
10743 19:28:01.582049 <4>[ 3.668063] cpu cpu3: supply cpu not found, using dummy regulator
10744 19:28:01.588219 <4>[ 3.674465] cpu cpu4: supply cpu not found, using dummy regulator
10745 19:28:01.594948 <4>[ 3.680866] cpu cpu5: supply cpu not found, using dummy regulator
10746 19:28:01.601794 <4>[ 3.687276] cpu cpu6: supply cpu not found, using dummy regulator
10747 19:28:01.608306 <4>[ 3.693675] cpu cpu7: supply cpu not found, using dummy regulator
10748 19:28:01.626157 <6>[ 3.714321] cpu cpu0: EM: created perf domain
10749 19:28:01.629561 <6>[ 3.719273] cpu cpu4: EM: created perf domain
10750 19:28:01.636824 <6>[ 3.724906] sdhci: Secure Digital Host Controller Interface driver
10751 19:28:01.643284 <6>[ 3.731334] sdhci: Copyright(c) Pierre Ossman
10752 19:28:01.650194 <6>[ 3.736295] Synopsys Designware Multimedia Card Interface Driver
10753 19:28:01.656412 <6>[ 3.742943] sdhci-pltfm: SDHCI platform and OF driver helper
10754 19:28:01.660094 <6>[ 3.742993] mmc0: CQHCI version 5.10
10755 19:28:01.666910 <6>[ 3.752901] ledtrig-cpu: registered to indicate activity on CPUs
10756 19:28:01.673031 <6>[ 3.759918] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10757 19:28:01.679823 <6>[ 3.766964] usbcore: registered new interface driver usbhid
10758 19:28:01.682706 <6>[ 3.772790] usbhid: USB HID core driver
10759 19:28:01.689440 <6>[ 3.776988] spi_master spi0: will run message pump with realtime priority
10760 19:28:01.736963 <6>[ 3.818485] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10761 19:28:01.756899 <6>[ 3.834798] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10762 19:28:01.760395 <6>[ 3.848328] mmc0: Command Queue Engine enabled
10763 19:28:01.767155 <6>[ 3.849829] cros-ec-spi spi0.0: Chrome EC device registered
10764 19:28:01.773988 <6>[ 3.853077] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10765 19:28:01.777042 <6>[ 3.866220] mmcblk0: mmc0:0001 DA4128 116 GiB
10766 19:28:01.787517 <6>[ 3.872366] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10767 19:28:01.794173 <6>[ 3.875452] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10768 19:28:01.801063 <6>[ 3.882898] NET: Registered PF_PACKET protocol family
10769 19:28:01.804209 <6>[ 3.888872] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10770 19:28:01.810906 <6>[ 3.892996] 9pnet: Installing 9P2000 support
10771 19:28:01.813872 <6>[ 3.898769] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10772 19:28:01.820341 <5>[ 3.902680] Key type dns_resolver registered
10773 19:28:01.827126 <6>[ 3.908495] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10774 19:28:01.830328 <6>[ 3.912887] registered taskstats version 1
10775 19:28:01.834015 <5>[ 3.923264] Loading compiled-in X.509 certificates
10776 19:28:01.863857 <4>[ 3.945560] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10777 19:28:01.873873 <4>[ 3.956240] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10778 19:28:01.880921 <3>[ 3.966765] debugfs: File 'uA_load' in directory '/' already present!
10779 19:28:01.887053 <3>[ 3.973466] debugfs: File 'min_uV' in directory '/' already present!
10780 19:28:01.893739 <3>[ 3.980074] debugfs: File 'max_uV' in directory '/' already present!
10781 19:28:01.900238 <3>[ 3.986738] debugfs: File 'constraint_flags' in directory '/' already present!
10782 19:28:01.911746 <3>[ 3.996270] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10783 19:28:01.922199 <6>[ 4.010085] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10784 19:28:01.928851 <6>[ 4.016894] xhci-mtk 11200000.usb: xHCI Host Controller
10785 19:28:01.935264 <6>[ 4.022418] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10786 19:28:01.945724 <6>[ 4.030266] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10787 19:28:01.951941 <6>[ 4.039680] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10788 19:28:01.958502 <6>[ 4.045746] xhci-mtk 11200000.usb: xHCI Host Controller
10789 19:28:01.965494 <6>[ 4.051224] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10790 19:28:01.971735 <6>[ 4.058872] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10791 19:28:01.978375 <6>[ 4.066504] hub 1-0:1.0: USB hub found
10792 19:28:01.982051 <6>[ 4.070512] hub 1-0:1.0: 1 port detected
10793 19:28:01.991703 <6>[ 4.074791] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10794 19:28:01.995110 <6>[ 4.083340] hub 2-0:1.0: USB hub found
10795 19:28:01.998330 <6>[ 4.087345] hub 2-0:1.0: 1 port detected
10796 19:28:02.007642 <6>[ 4.095838] mtk-msdc 11f70000.mmc: Got CD GPIO
10797 19:28:02.020307 <6>[ 4.105011] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10798 19:28:02.027174 <6>[ 4.113119] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10799 19:28:02.036856 <4>[ 4.121019] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10800 19:28:02.046650 <6>[ 4.130559] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10801 19:28:02.053449 <6>[ 4.138639] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10802 19:28:02.060122 <6>[ 4.146662] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10803 19:28:02.070048 <6>[ 4.154574] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10804 19:28:02.076238 <6>[ 4.162411] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10805 19:28:02.086497 <6>[ 4.170230] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10806 19:28:02.096374 <6>[ 4.180551] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10807 19:28:02.102900 <6>[ 4.188906] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10808 19:28:02.112762 <6>[ 4.197287] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10809 19:28:02.119305 <6>[ 4.205628] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10810 19:28:02.128978 <6>[ 4.213979] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10811 19:28:02.138892 <6>[ 4.222318] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10812 19:28:02.145631 <6>[ 4.230667] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10813 19:28:02.155914 <6>[ 4.239006] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10814 19:28:02.162003 <6>[ 4.247352] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10815 19:28:02.171877 <6>[ 4.255690] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10816 19:28:02.178727 <6>[ 4.264027] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10817 19:28:02.188448 <6>[ 4.272369] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10818 19:28:02.195320 <6>[ 4.280708] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10819 19:28:02.205366 <6>[ 4.289045] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10820 19:28:02.212001 <6>[ 4.297382] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10821 19:28:02.218439 <6>[ 4.306146] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10822 19:28:02.225251 <6>[ 4.313338] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10823 19:28:02.231983 <6>[ 4.320121] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10824 19:28:02.242239 <6>[ 4.326880] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10825 19:28:02.248453 <6>[ 4.333799] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10826 19:28:02.255546 <6>[ 4.340678] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10827 19:28:02.264752 <6>[ 4.349807] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10828 19:28:02.275181 <6>[ 4.358945] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10829 19:28:02.284646 <6>[ 4.368244] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10830 19:28:02.295107 <6>[ 4.377711] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10831 19:28:02.304936 <6>[ 4.387179] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10832 19:28:02.311121 <6>[ 4.396299] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10833 19:28:02.321011 <6>[ 4.405765] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10834 19:28:02.331294 <6>[ 4.414883] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10835 19:28:02.340726 <6>[ 4.424179] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10836 19:28:02.350753 <6>[ 4.434340] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10837 19:28:02.361110 <6>[ 4.445951] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10838 19:28:02.388703 <6>[ 4.473395] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10839 19:28:02.416373 <6>[ 4.504626] hub 2-1:1.0: USB hub found
10840 19:28:02.420041 <6>[ 4.509105] hub 2-1:1.0: 3 ports detected
10841 19:28:02.428537 <6>[ 4.516474] hub 2-1:1.0: USB hub found
10842 19:28:02.431591 <6>[ 4.520797] hub 2-1:1.0: 3 ports detected
10843 19:28:02.540202 <6>[ 4.624996] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10844 19:28:02.695200 <6>[ 4.783311] hub 1-1:1.0: USB hub found
10845 19:28:02.698250 <6>[ 4.787819] hub 1-1:1.0: 4 ports detected
10846 19:28:02.706875 <6>[ 4.794987] hub 1-1:1.0: USB hub found
10847 19:28:02.710047 <6>[ 4.799451] hub 1-1:1.0: 4 ports detected
10848 19:28:02.776453 <6>[ 4.861339] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10849 19:28:03.032085 <6>[ 5.117148] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10850 19:28:03.164444 <6>[ 5.252935] hub 1-1.4:1.0: USB hub found
10851 19:28:03.168219 <6>[ 5.257586] hub 1-1.4:1.0: 2 ports detected
10852 19:28:03.177914 <6>[ 5.265843] hub 1-1.4:1.0: USB hub found
10853 19:28:03.181065 <6>[ 5.270484] hub 1-1.4:1.0: 2 ports detected
10854 19:28:03.480194 <6>[ 5.565137] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10855 19:28:03.672395 <6>[ 5.757221] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10856 19:28:14.657346 <6>[ 16.750204] ALSA device list:
10857 19:28:14.663640 <6>[ 16.753500] No soundcards found.
10858 19:28:14.672168 <6>[ 16.761490] Freeing unused kernel memory: 8448K
10859 19:28:14.675197 <6>[ 16.766965] Run /init as init process
10860 19:28:14.721054 <6>[ 16.810389] NET: Registered PF_INET6 protocol family
10861 19:28:14.727265 <6>[ 16.816683] Segment Routing with IPv6
10862 19:28:14.730924 <6>[ 16.820714] In-situ OAM (IOAM) with IPv6
10863 19:28:14.776174 <30>[ 16.839373] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10864 19:28:14.783094 <30>[ 16.872435] systemd[1]: Detected architecture arm64.
10865 19:28:14.783183
10866 19:28:14.789752 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10867 19:28:14.789837
10868 19:28:14.789943
10869 19:28:14.807412 <30>[ 16.897156] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10870 19:28:14.979338 <30>[ 17.065444] systemd[1]: Queued start job for default target graphical.target.
10871 19:28:15.032282 <30>[ 17.118472] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10872 19:28:15.038925 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10873 19:28:15.039021
10874 19:28:15.059313 <30>[ 17.145650] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10875 19:28:15.065983 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10876 19:28:15.069594
10877 19:28:15.087964 <30>[ 17.173992] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10878 19:28:15.097391 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10879 19:28:15.097479
10880 19:28:15.116665 <30>[ 17.202704] systemd[1]: Created slice user.slice - User and Session Slice.
10881 19:28:15.123410 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10882 19:28:15.123496
10883 19:28:15.147372 <30>[ 17.229939] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10884 19:28:15.157137 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10885 19:28:15.157227
10886 19:28:15.174600 <30>[ 17.257334] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10887 19:28:15.180836 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10888 19:28:15.180924
10889 19:28:15.209117 <30>[ 17.285703] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10890 19:28:15.219283 <30>[ 17.305608] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10891 19:28:15.226064 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10892 19:28:15.226149
10893 19:28:15.243094 <30>[ 17.329539] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10894 19:28:15.252794 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10895 19:28:15.252881
10896 19:28:15.271773 <30>[ 17.357659] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10897 19:28:15.281497 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10898 19:28:15.281584
10899 19:28:15.296419 <30>[ 17.385636] systemd[1]: Reached target paths.target - Path Units.
10900 19:28:15.303249 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10901 19:28:15.306336
10902 19:28:15.323215 <30>[ 17.409629] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10903 19:28:15.329932 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10904 19:28:15.330038
10905 19:28:15.343450 <30>[ 17.433124] systemd[1]: Reached target slices.target - Slice Units.
10906 19:28:15.353319 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10907 19:28:15.353432
10908 19:28:15.368499 <30>[ 17.457623] systemd[1]: Reached target swap.target - Swaps.
10909 19:28:15.374813 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10910 19:28:15.374901
10911 19:28:15.395312 <30>[ 17.481621] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10912 19:28:15.405344 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10913 19:28:15.405447
10914 19:28:15.423391 <30>[ 17.509598] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10915 19:28:15.433282 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10916 19:28:15.433452
10917 19:28:15.452910 <30>[ 17.539346] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10918 19:28:15.463080 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10919 19:28:15.463166
10920 19:28:15.479476 <30>[ 17.565923] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10921 19:28:15.489713 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10922 19:28:15.489802
10923 19:28:15.507356 <30>[ 17.593750] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10924 19:28:15.514131 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10925 19:28:15.514215
10926 19:28:15.531769 <30>[ 17.617778] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10927 19:28:15.541513 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10928 19:28:15.541599
10929 19:28:15.559323 <30>[ 17.645624] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10930 19:28:15.569291 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10931 19:28:15.569418
10932 19:28:15.611433 <30>[ 17.697318] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10933 19:28:15.617745 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10934 19:28:15.617839
10935 19:28:15.636558 <30>[ 17.722987] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10936 19:28:15.643536 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10937 19:28:15.643622
10938 19:28:15.665269 <30>[ 17.751815] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10939 19:28:15.672174 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10940 19:28:15.672262
10941 19:28:15.697837 <30>[ 17.777264] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10942 19:28:15.709321 <30>[ 17.795497] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10943 19:28:15.719050 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10944 19:28:15.719143
10945 19:28:15.738685 <30>[ 17.824973] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10946 19:28:15.744913 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10947 19:28:15.744999
10948 19:28:15.771554 <30>[ 17.858056] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10949 19:28:15.781302 Startin<6>[ 17.867399] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10950 19:28:15.788269 g [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10951 19:28:15.788354
10952 19:28:15.847597 <30>[ 17.933886] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10953 19:28:15.854257 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10954 19:28:15.854374
10955 19:28:15.880309 <30>[ 17.966517] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10956 19:28:15.886928 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10957 19:28:15.890040
10958 19:28:15.935641 <30>[ 18.021902] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10959 19:28:15.941832 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10960 19:28:15.941940
10961 19:28:15.971931 <30>[ 18.058285] systemd[1]: Starting systemd-journald.service - Journal Service...
10962 19:28:15.978558 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10963 19:28:15.978640
10964 19:28:15.997554 <30>[ 18.083791] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10965 19:28:16.003828 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10966 19:28:16.003937
10967 19:28:16.029134 <30>[ 18.112216] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10968 19:28:16.035765 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10969 19:28:16.035851
10970 19:28:16.059397 <30>[ 18.145536] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10971 19:28:16.069126 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10972 19:28:16.069214
10973 19:28:16.089997 <30>[ 18.176253] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10974 19:28:16.096429 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10975 19:28:16.096514
10976 19:28:16.120142 <30>[ 18.206313] systemd[1]: Started systemd-journald.service - Journal Service.
10977 19:28:16.126245 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10978 19:28:16.126332
10979 19:28:16.150048 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10980 19:28:16.150133
10981 19:28:16.168082 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10982 19:28:16.168170
10983 19:28:16.187819 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10984 19:28:16.187906
10985 19:28:16.208442 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10986 19:28:16.208529
10987 19:28:16.228689 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10988 19:28:16.228777
10989 19:28:16.250992 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10990 19:28:16.251078
10991 19:28:16.271123 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10992 19:28:16.271210
10993 19:28:16.290610 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10994 19:28:16.290730
10995 19:28:16.310773 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10996 19:28:16.310860
10997 19:28:16.330635 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10998 19:28:16.330729
10999 19:28:16.348969 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
11000 19:28:16.349055
11001 19:28:16.373555 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
11002 19:28:16.373641
11003 19:28:16.387608 See 'systemctl status systemd-remount-fs.service' for details.
11004 19:28:16.387692
11005 19:28:16.408585 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
11006 19:28:16.408674
11007 19:28:16.429365 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
11008 19:28:16.429476
11009 19:28:16.474908 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
11010 19:28:16.475013
11011 19:28:16.495847 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
11012 19:28:16.495941
11013 19:28:16.517057 <46>[ 18.603563] systemd-journald[187]: Received client request to flush runtime journal.
11014 19:28:16.523869 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
11015 19:28:16.523986
11016 19:28:16.551350 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
11017 19:28:16.551470
11018 19:28:16.576101 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
11019 19:28:16.576189
11020 19:28:16.601314 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
11021 19:28:16.601426
11022 19:28:16.620617 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11023 19:28:16.620707
11024 19:28:16.640541 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
11025 19:28:16.640628
11026 19:28:16.660707 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
11027 19:28:16.660799
11028 19:28:16.680703 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
11029 19:28:16.680796
11030 19:28:16.735239 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
11031 19:28:16.735356
11032 19:28:16.758067 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11033 19:28:16.758159
11034 19:28:16.775538 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11035 19:28:16.775626
11036 19:28:16.790727 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11037 19:28:16.790812
11038 19:28:16.831951 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11039 19:28:16.832054
11040 19:28:16.856825 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11041 19:28:16.856912
11042 19:28:16.881062 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11043 19:28:16.881180
11044 19:28:16.921717 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11045 19:28:16.921857
11046 19:28:16.941832 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11047 19:28:16.941916
11048 19:28:16.962610 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11049 19:28:16.962694
11050 19:28:17.006251 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11051 19:28:17.006345
11052 19:28:17.032237 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11053 19:28:17.032333
11054 19:28:17.067495 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11055 19:28:17.067583
11056 19:28:17.167317 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11057 19:28:17.167461
11058 19:28:17.183898 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11059 19:28:17.184005
11060 19:28:17.207674 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11061 19:28:17.207787
11062 19:28:17.227925 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11063 19:28:17.228019
11064 19:28:17.247281 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11065 19:28:17.247368
11066 19:28:17.264933 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11067 19:28:17.265021
11068 19:28:17.282903 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11069 19:28:17.282988
11070 19:28:17.301463 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11071 19:28:17.301548
11072 19:28:17.307724 <3>[ 19.395297] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11073 19:28:17.314639 <6>[ 19.403142] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
11074 19:28:17.324365 <3>[ 19.403509] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11075 19:28:17.331301 <6>[ 19.415184] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
11076 19:28:17.340769 <3>[ 19.418880] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11077 19:28:17.347738 <6>[ 19.426494] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
11078 19:28:17.357246 <3>[ 19.437718] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11079 19:28:17.361056 <6>[ 19.440201] remoteproc remoteproc0: scp is available
11080 19:28:17.367352 <6>[ 19.440276] remoteproc remoteproc0: powering up scp
11081 19:28:17.373915 <6>[ 19.440283] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
11082 19:28:17.380495 <6>[ 19.440302] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
11083 19:28:17.390411 <6>[ 19.443283] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
11084 19:28:17.397122 <3>[ 19.451333] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11085 19:28:17.406622 <3>[ 19.492503] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11086 19:28:17.413417 <3>[ 19.500584] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11087 19:28:17.423171 <3>[ 19.508666] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11088 19:28:17.433312 <3>[ 19.518231] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11089 19:28:17.439574 <6>[ 19.527953] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
11090 19:28:17.449551 <4>[ 19.528030] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
11091 19:28:17.456308 <3>[ 19.529014] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11092 19:28:17.466034 <3>[ 19.529024] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11093 19:28:17.472746 <3>[ 19.529028] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11094 19:28:17.475903 <6>[ 19.530051] mc: Linux media interface: v0.10
11095 19:28:17.486631 <3>[ 19.537734] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11096 19:28:17.493089 <4>[ 19.551872] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
11097 19:28:17.499711 <4>[ 19.551872] Fallback method does not support PEC.
11098 19:28:17.506505 <3>[ 19.559245] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11099 19:28:17.512645 <4>[ 19.561665] elants_i2c 4-0010: supply vccio not found, using dummy regulator
11100 19:28:17.522726 <6>[ 19.565654] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
11101 19:28:17.529364 <6>[ 19.565655] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
11102 19:28:17.535855 <6>[ 19.565673] remoteproc remoteproc0: remote processor scp is now up
11103 19:28:17.546028 <3>[ 19.603957] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11104 19:28:17.552503 <6>[ 19.606437] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
11105 19:28:17.558946 <6>[ 19.606448] pci_bus 0000:00: root bus resource [bus 00-ff]
11106 19:28:17.565592 <6>[ 19.606456] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
11107 19:28:17.575467 <6>[ 19.606462] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
11108 19:28:17.582335 <6>[ 19.606504] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
11109 19:28:17.588604 <6>[ 19.606526] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
11110 19:28:17.592288 <6>[ 19.606610] pci 0000:00:00.0: supports D1 D2
11111 19:28:17.598738 <6>[ 19.606615] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11112 19:28:17.608349 <3>[ 19.609015] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11113 19:28:17.615094 <3>[ 19.609022] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11114 19:28:17.624875 <3>[ 19.609031] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11115 19:28:17.631433 <6>[ 19.609711] usbcore: registered new device driver r8152-cfgselector
11116 19:28:17.638211 <3>[ 19.615221] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11117 19:28:17.645015 <6>[ 19.618638] videodev: Linux video capture interface: v2.00
11118 19:28:17.654754 <6>[ 19.621459] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
11119 19:28:17.664577 <6>[ 19.626297] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
11120 19:28:17.671206 <6>[ 19.630281] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
11121 19:28:17.681223 <6>[ 19.665689] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
11122 19:28:17.688375 <6>[ 19.669972] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
11123 19:28:17.694683 <6>[ 19.695204] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
11124 19:28:17.702350 <6>[ 19.702986] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
11125 19:28:17.708369 <6>[ 19.711899] Bluetooth: Core ver 2.22
11126 19:28:17.715249 <6>[ 19.719227] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
11127 19:28:17.721785 <6>[ 19.725761] NET: Registered PF_BLUETOOTH protocol family
11128 19:28:17.728243 <6>[ 19.728783] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11129 19:28:17.738796 <6>[ 19.730035] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11130 19:28:17.745027 <6>[ 19.730191] usbcore: registered new interface driver uvcvideo
11131 19:28:17.754882 <6>[ 19.733800] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11132 19:28:17.762071 <6>[ 19.733880] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
11133 19:28:17.765779 <6>[ 19.733940] pci 0000:01:00.0: supports D1 D2
11134 19:28:17.772330 <6>[ 19.733943] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11135 19:28:17.779177 <6>[ 19.739738] Bluetooth: HCI device and connection manager initialized
11136 19:28:17.788630 <6>[ 19.750226] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
11137 19:28:17.792341 <6>[ 19.758088] Bluetooth: HCI socket layer initialized
11138 19:28:17.801765 <6>[ 19.758121] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11139 19:28:17.809023 <6>[ 19.758153] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11140 19:28:17.815808 <6>[ 19.758156] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11141 19:28:17.825447 <6>[ 19.758165] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11142 19:28:17.832531 <6>[ 19.758178] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11143 19:28:17.842534 <6>[ 19.758190] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11144 19:28:17.846217 <6>[ 19.758202] pci 0000:00:00.0: PCI bridge to [bus 01]
11145 19:28:17.853112 <6>[ 19.758207] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11146 19:28:17.859401 <6>[ 19.758377] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11147 19:28:17.866084 <6>[ 19.758992] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
11148 19:28:17.872697 <6>[ 19.759324] pcieport 0000:00:00.0: AER: enabled with IRQ 282
11149 19:28:17.879633 <3>[ 19.774489] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11150 19:28:17.886156 <6>[ 19.776302] Bluetooth: L2CAP socket layer initialized
11151 19:28:17.892914 <5>[ 19.778318] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11152 19:28:17.899453 <6>[ 19.783437] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11153 19:28:17.909523 <3>[ 19.783506] power_supply sbs-5-000b: driver failed to report `temp' property: -6
11154 19:28:17.912732 <6>[ 19.790820] Bluetooth: SCO socket layer initialized
11155 19:28:17.922686 <3>[ 19.791856] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11156 19:28:17.929836 <5>[ 19.792504] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11157 19:28:17.936452 <5>[ 19.792750] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
11158 19:28:17.946776 <4>[ 19.792806] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11159 19:28:17.949776 <6>[ 19.792811] cfg80211: failed to load regulatory.db
11160 19:28:17.959701 <3>[ 19.810118] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11161 19:28:17.970187 <4>[ 19.819961] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
11162 19:28:17.976426 <3>[ 19.834246] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11163 19:28:17.986945 <4>[ 19.835077] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
11164 19:28:17.993054 <6>[ 19.836321] usbcore: registered new interface driver btusb
11165 19:28:18.003242 <4>[ 19.836760] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11166 19:28:18.007304 <3>[ 19.836768] Bluetooth: hci0: Failed to load firmware file (-2)
11167 19:28:18.013696 <3>[ 19.836771] Bluetooth: hci0: Failed to set up firmware (-2)
11168 19:28:18.023489 <4>[ 19.836775] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11169 19:28:18.033267 <3>[ 19.862234] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11170 19:28:18.040085 <6>[ 19.883998] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11171 19:28:18.049841 <3>[ 19.909499] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11172 19:28:18.056454 <6>[ 19.911587] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11173 19:28:18.059624 <6>[ 19.919677] r8152 2-1.3:1.0 eth0: v1.12.13
11174 19:28:18.069980 <3>[ 19.943353] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11175 19:28:18.073173 <6>[ 19.948727] usbcore: registered new interface driver r8152
11176 19:28:18.079855 <6>[ 19.948821] mt7921e 0000:01:00.0: ASIC revision: 79610010
11177 19:28:18.089567 <3>[ 19.978597] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11178 19:28:18.096026 <6>[ 19.995959] usbcore: registered new interface driver cdc_ether
11179 19:28:18.102662 <6>[ 20.045119] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
11180 19:28:18.106129 <6>[ 20.045119]
11181 19:28:18.112610 <6>[ 20.055277] usbcore: registered new interface driver r8153_ecm
11182 19:28:18.119229 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11183 19:28:18.119312
11184 19:28:18.168607 Starting [0;1;39msyste<6>[ 20.257309] r8152 2-1.3:1.0 enx00e04c680281: renamed from eth0
11185 19:28:18.174760 md-logind.se…ice[0m - User Login Management...
11186 19:28:18.174849
11187 19:28:18.200390 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11188 19:28:18.200484
11189 19:28:18.221938 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11190 19:28:18.222027
11191 19:28:18.235310 <6>[ 20.320889] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
11192 19:28:18.260900 <46>[ 20.334693] systemd-journald[187]: Data hash table of /var/log/journal/c3f909ee3e324895ab90ff2613af9260/system.journal has a fill level at 75.1 (1537 of 2047 items, 524288 file size, 341 bytes per hash table item), suggesting rotation.
11193 19:28:18.277709 [[0;32m OK [0m] Finished [0<46>[ 20.357841] systemd-journald[187]: /var/log/journal/c3f909ee3e324895ab90ff2613af9260/system.journal: Journal header limits reached or header out-of-date, rotating.
11194 19:28:18.283787 ;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11195 19:28:18.283872
11196 19:28:18.348358 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11197 19:28:18.348474
11198 19:28:18.371485 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11199 19:28:18.371580
11200 19:28:18.391417 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11201 19:28:18.391511
11202 19:28:18.415980 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11203 19:28:18.416069
11204 19:28:18.467947 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11205 19:28:18.468058
11206 19:28:18.489475 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11207 19:28:18.489563
11208 19:28:18.507955 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11209 19:28:18.508068
11210 19:28:18.523473 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11211 19:28:18.523606
11212 19:28:18.543841 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11213 19:28:18.543927
11214 19:28:18.600610 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11215 19:28:18.600722
11216 19:28:18.625770 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11217 19:28:18.625873
11218 19:28:18.651272 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11219 19:28:18.651435
11220 19:28:18.725341 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11221 19:28:18.725483
11222 19:28:18.745359 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11223 19:28:18.745462
11224 19:28:18.769827 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11225 19:28:18.769932
11226 19:28:18.804882
11227 19:28:18.804971
11228 19:28:18.807811 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11229 19:28:18.807896
11230 19:28:18.811452 debian-bookworm-arm64 login: root (automatic login)
11231 19:28:18.811538
11232 19:28:18.811604
11233 19:28:18.826176 Linux debian-bookworm-arm64 6.1.86-cip19 #1 SMP PREEMPT Thu Apr 18 19:05:54 UTC 2024 aarch64
11234 19:28:18.826265
11235 19:28:18.832386 The programs included with the Debian GNU/Linux system are free software;
11236 19:28:18.838986 the exact distribution terms for each program are described in the
11237 19:28:18.842581 individual files in /usr/share/doc/*/copyright.
11238 19:28:18.842666
11239 19:28:18.849114 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11240 19:28:18.852102 permitted by applicable law.
11241 19:28:18.852492 Matched prompt #10: / #
11243 19:28:18.852704 Setting prompt string to ['/ #']
11244 19:28:18.852799 end: 2.2.5.1 login-action (duration 00:00:22) [common]
11246 19:28:18.852998 end: 2.2.5 auto-login-action (duration 00:00:22) [common]
11247 19:28:18.853086 start: 2.2.6 expect-shell-connection (timeout 00:02:28) [common]
11248 19:28:18.853160 Setting prompt string to ['/ #']
11249 19:28:18.853221 Forcing a shell prompt, looking for ['/ #']
11251 19:28:18.903449 / #
11252 19:28:18.903566 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11253 19:28:18.903643 Waiting using forced prompt support (timeout 00:02:30)
11254 19:28:18.908431
11255 19:28:18.908704 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11256 19:28:18.908799 start: 2.2.7 export-device-env (timeout 00:02:28) [common]
11257 19:28:18.908893 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11258 19:28:18.908977 end: 2.2 depthcharge-retry (duration 00:02:32) [common]
11259 19:28:18.909061 end: 2 depthcharge-action (duration 00:02:32) [common]
11260 19:28:18.909146 start: 3 lava-test-retry (timeout 00:07:02) [common]
11261 19:28:18.909231 start: 3.1 lava-test-shell (timeout 00:07:02) [common]
11262 19:28:18.909305 Using namespace: common
11264 19:28:19.009705 / # #
11265 19:28:19.009873 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11266 19:28:19.015109 #
11267 19:28:19.015378 Using /lava-13420392
11269 19:28:19.115716 / # export SHELL=/bin/sh
11270 19:28:19.115931 export SHELL=/bin/sh<6>[ 21.185338] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11271 19:28:19.121281
11273 19:28:19.221865 / # . /lava-13420392/environment
11274 19:28:19.227436 . /lava-13420392/environment
11276 19:28:19.327985 / # /lava-13420392/bin/lava-test-runner /lava-13420392/0
11277 19:28:19.328136 Test shell timeout: 10s (minimum of the action and connection timeout)
11278 19:28:19.333193 /lava-13420392/bin/lava-test-runner /lava-13420392/0
11279 19:28:19.359342 + export TESTRUN_ID=0_igt-gpu-panf<8>[ 21.448758] <LAVA_SIGNAL_STARTRUN 0_igt-gpu-panfrost 13420392_1.5.2.3.1>
11280 19:28:19.359611 Received signal: <STARTRUN> 0_igt-gpu-panfrost 13420392_1.5.2.3.1
11281 19:28:19.359687 Starting test lava.0_igt-gpu-panfrost (13420392_1.5.2.3.1)
11282 19:28:19.359773 Skipping test definition patterns.
11283 19:28:19.363017 rost
11284 19:28:19.366293 + cd /lava-13420392/0/tests/0_igt-gpu-panfrost
11285 19:28:19.366377 + cat uuid
11286 19:28:19.369205 + UUID=13420392_1.5.2.3.1
11287 19:28:19.369289 + set +x
11288 19:28:19.379162 + IGT_FORCE_DRIVER=panfrost /usr/bin/igt-parser.sh panfrost_gem_new panfrost_get_param panfrost_prime panfrost_submit
11289 19:28:19.385841 <8>[ 21.474968] <LAVA_SIGNAL_TESTSET START panfrost_gem_new>
11290 19:28:19.386104 Received signal: <TESTSET> START panfrost_gem_new
11291 19:28:19.386179 Starting test_set panfrost_gem_new
11292 19:28:19.407934 <14>[ 21.497966] [IGT] panfrost_gem_new: executing
11293 19:28:19.414522 IGT-Version: 1.28-ga44ebfe (aarc<14>[ 21.505480] [IGT] panfrost_gem_new: exiting, ret=77
11294 19:28:19.417771 h64) (Linux: 6.1.86-cip19 aarch64)
11295 19:28:19.427614 Using IGT_SRANDOM=1713468499<8>[ 21.515531] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-4096 RESULT=skip>
11296 19:28:19.427874 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-4096 RESULT=skip
11298 19:28:19.430615 for randomisation
11299 19:28:19.437495 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11300 19:28:19.440943 Test requirement: !(fd<0)
11301 19:28:19.447357 No known gpu found for chipset <14>[ 21.537331] [IGT] panfrost_gem_new: executing
11302 19:28:19.450348 flags 0x32 (panfrost)
11303 19:28:19.454119 Last errn<14>[ 21.544567] [IGT] panfrost_gem_new: exiting, ret=77
11304 19:28:19.457248 o: 2, No such file or directory
11305 19:28:19.467418 [1mSubtest gem-new-4096: SKIP <8>[ 21.555178] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-0 RESULT=skip>
11306 19:28:19.467710 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-0 RESULT=skip
11308 19:28:19.470376 (0.000s)[0m
11309 19:28:19.473800 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11310 19:28:19.480427 Using IGT_SRANDOM=1713468499 for randomisation
11311 19:28:19.486684 Test requirement not met in fu<14>[ 21.576457] [IGT] panfrost_gem_new: executing
11312 19:28:19.493341 nction drm_open_driver, file ../<14>[ 21.583589] [IGT] panfrost_gem_new: exiting, ret=77
11313 19:28:19.496967 lib/drmtest.c:694:
11314 19:28:19.500059 Test requirement: !(fd<0)
11315 19:28:19.506887 No known gpu foun<8>[ 21.593966] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-zeroed RESULT=skip>
11316 19:28:19.507152 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-zeroed RESULT=skip
11318 19:28:19.513277 d for chipset flags 0x32 (panfro<8>[ 21.603534] <LAVA_SIGNAL_TESTSET STOP>
11319 19:28:19.513402 st)
11320 19:28:19.513647 Received signal: <TESTSET> STOP
11321 19:28:19.513716 Closing test_set panfrost_gem_new
11322 19:28:19.519547 Last errno: 2, No such file or directory
11323 19:28:19.522910 [1mSubtest gem-new-0: SKIP (0.000s)[0m
11324 19:28:19.525983 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11325 19:28:19.536475 Using IGT_SRANDOM=1713468499 for ra<8>[ 21.625536] <LAVA_SIGNAL_TESTSET START panfrost_get_param>
11326 19:28:19.536558 ndomisation
11327 19:28:19.536796 Received signal: <TESTSET> START panfrost_get_param
11328 19:28:19.536865 Starting test_set panfrost_get_param
11329 19:28:19.546503 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11330 19:28:19.546587 Test requirement: !(fd<0)
11331 19:28:19.555709 No known gpu found for chipset flags 0<14>[ 21.644094] [IGT] panfrost_get_param: executing
11332 19:28:19.555793 x32 (panfrost)
11333 19:28:19.562600 Last errno: 2, N<14>[ 21.652485] [IGT] panfrost_get_param: exiting, ret=77
11334 19:28:19.565793 o such file or directory
11335 19:28:19.575698 [1mSubtest gem-new-zeroed: SKIP (0.00<8>[ 21.663199] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=base-params RESULT=skip>
11336 19:28:19.575782 0s)[0m
11337 19:28:19.576019 Received signal: <TESTCASE> TEST_CASE_ID=base-params RESULT=skip
11339 19:28:19.582526 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11340 19:28:19.585250 Using IGT_SRANDOM=1713468499 for randomisation
11341 19:28:19.595319 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11342 19:28:19.598964 T<14>[ 21.688430] [IGT] panfrost_get_param: executing
11343 19:28:19.601853 est requirement: !(fd<0)
11344 19:28:19.608632 No kno<14>[ 21.696186] [IGT] panfrost_get_param: exiting, ret=77
11345 19:28:19.611670 wn gpu found for chipset flags 0x32 (panfrost)
11346 19:28:19.618558 Last errno: 2, N<8>[ 21.706922] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-param RESULT=skip>
11347 19:28:19.618814 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-param RESULT=skip
11349 19:28:19.621529 o such file or directory
11350 19:28:19.625027 [1mSubtest base-params: SKIP (0.000s)[0m
11351 19:28:19.631705 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11352 19:28:19.637880 Using IGT_SRANDOM=1713<14>[ 21.728699] [IGT] panfrost_get_param: executing
11353 19:28:19.641696 468499 for randomisation
11354 19:28:19.648095 Test r<14>[ 21.736048] [IGT] panfrost_get_param: exiting, ret=77
11355 19:28:19.654618 equirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11356 19:28:19.661502 Test<8>[ 21.747654] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-padding RESULT=skip>
11357 19:28:19.661758 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-padding RESULT=skip
11359 19:28:19.668033 requirement: !(<8>[ 21.757342] <LAVA_SIGNAL_TESTSET STOP>
11360 19:28:19.668116 fd<0)
11361 19:28:19.668351 Received signal: <TESTSET> STOP
11362 19:28:19.668418 Closing test_set panfrost_get_param
11363 19:28:19.671322 No known gpu found for chipset flags 0x32 (panfrost)
11364 19:28:19.674357 Last errno: 2, No such file or directory
11365 19:28:19.680876 [1mSubtest get-bad-param: SKIP (0.000s)[0m
11366 19:28:19.687642 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux<8>[ 21.777584] <LAVA_SIGNAL_TESTSET START panfrost_prime>
11367 19:28:19.687895 Received signal: <TESTSET> START panfrost_prime
11368 19:28:19.687966 Starting test_set panfrost_prime
11369 19:28:19.690712 : 6.1.86-cip19 aarch64)
11370 19:28:19.694040 Using IGT_SRANDOM=1713468499 for randomisation
11371 19:28:19.700795 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11372 19:28:19.707371 Test <14>[ 21.796782] [IGT] panfrost_prime: executing
11373 19:28:19.710539 requirement: !(fd<0)
11374 19:28:19.713635 No known g<14>[ 21.804373] [IGT] panfrost_prime: exiting, ret=77
11375 19:28:19.717043 pu found for chipset flags 0x32 (panfrost)
11376 19:28:19.726970 Last errno: 2, No su<8>[ 21.814679] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-prime-import RESULT=skip>
11377 19:28:19.727227 Received signal: <TESTCASE> TEST_CASE_ID=gem-prime-import RESULT=skip
11379 19:28:19.730252 ch file or directory
11380 19:28:19.733805 [1mSubtes<8>[ 21.824417] <LAVA_SIGNAL_TESTSET STOP>
11381 19:28:19.734058 Received signal: <TESTSET> STOP
11382 19:28:19.734126 Closing test_set panfrost_prime
11383 19:28:19.736698 t get-bad-padding: SKIP (0.000s)[0m
11384 19:28:19.743477 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11385 19:28:19.746933 Using IGT_SRANDOM=1713468499 for randomisation
11386 19:28:19.756957 Test requirement not met in function drm_open_driver, <8>[ 21.846611] <LAVA_SIGNAL_TESTSET START panfrost_submit>
11387 19:28:19.757243 Received signal: <TESTSET> START panfrost_submit
11388 19:28:19.757377 Starting test_set panfrost_submit
11389 19:28:19.760097 file ../lib/drmtest.c:694:
11390 19:28:19.763304 Test requirement: !(fd<0)
11391 19:28:19.766706 No known gpu found for chipset flags 0x32 (panfrost)
11392 19:28:19.769984 Last errno: 2, No such file or directory
11393 19:28:19.776701 [1mSubte<14>[ 21.866504] [IGT] panfrost_submit: executing
11394 19:28:19.783561 st gem-prime-import: SKIP (0.000<14>[ 21.874192] [IGT] panfrost_submit: exiting, ret=77
11395 19:28:19.786621 s)[0m
11396 19:28:19.796483 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip1<8>[ 21.884623] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit RESULT=skip>
11397 19:28:19.796761 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit RESULT=skip
11399 19:28:19.799619 9 aarch64)
11400 19:28:19.803131 Using IGT_SRANDOM=1713468499 for randomisation
11401 19:28:19.809760 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11402 19:28:19.816183 Test requirement: <14>[ 21.905019] [IGT] panfrost_submit: executing
11403 19:28:19.816289 !(fd<0)
11404 19:28:19.822760 No known gpu found for <14>[ 21.913193] [IGT] panfrost_submit: exiting, ret=77
11405 19:28:19.825927 chipset flags 0x32 (panfrost)
11406 19:28:19.835782 Last errno: 2, No such file or di<8>[ 21.923466] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip>
11407 19:28:19.836066 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip
11409 19:28:19.839468 rectory
11410 19:28:19.842475 [1mSubtest pan-submit: SKIP (0.000s)[0m
11411 19:28:19.848928 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11412 19:28:19.855803 Using IGT_SRANDOM=1713468499 for randomi<14>[ 21.945999] [IGT] panfrost_submit: executing
11413 19:28:19.855911 sation
11414 19:28:19.862108 Test requirement not met<14>[ 21.953311] [IGT] panfrost_submit: exiting, ret=77
11415 19:28:19.868727 in function drm_open_driver, file ../lib/drmtest.c:694:
11416 19:28:19.878514 Test r<8>[ 21.963419] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip>
11417 19:28:19.878622 equirement: !(fd<0)
11418 19:28:19.878889 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip
11420 19:28:19.885067 No known gpu found for chipset flags 0x32 (panfrost)
11421 19:28:19.888667 Last errno: 2, No such file or directory
11422 19:28:19.894940 [1mSubtest pan-submit-error-no-jc: SKIP (0<14>[ 21.986696] [IGT] panfrost_submit: executing
11423 19:28:19.898682 .000s)[0m
11424 19:28:19.904819 IGT-Version: 1.28-ga<14>[ 21.993691] [IGT] panfrost_submit: exiting, ret=77
11425 19:28:19.908578 44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11426 19:28:19.918687 Using IGT_SRANDO<8>[ 22.004285] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip>
11427 19:28:19.918960 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip
11429 19:28:19.921488 M=1713468499 for randomisation
11430 19:28:19.927879 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11431 19:28:19.931831 Test requirement: !(fd<0)
11432 19:28:19.938413 No known gpu found <14>[ 22.027201] [IGT] panfrost_submit: executing
11433 19:28:19.944695 for chipset flags 0x32 (panfrost<14>[ 22.034521] [IGT] panfrost_submit: exiting, ret=77
11434 19:28:19.944778 )
11435 19:28:19.948346 Last errno: 2, No such file or directory
11436 19:28:19.957837 [1mSubtest pan-sub<8>[ 22.044833] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip>
11437 19:28:19.958095 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip
11439 19:28:19.964737 mit-error-bad-in-syncs: SKIP (0.000s)[0m
11440 19:28:19.968195 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11441 19:28:19.974374 Using IGT_SRANDOM=1713468499 for randomisation
11442 19:28:19.977528 T<14>[ 22.068107] [IGT] panfrost_submit: executing
11443 19:28:19.987373 est requirement not met in funct<14>[ 22.075324] [IGT] panfrost_submit: exiting, ret=77
11444 19:28:19.990947 ion drm_open_driver, file ../lib/drmtest.c:694:
11445 19:28:20.000798 Test requiremen<8>[ 22.085624] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip>
11446 19:28:20.000882 t: !(fd<0)
11447 19:28:20.001126 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip
11449 19:28:20.007591 No known gpu found for chipset flags 0x32 (panfrost)
11450 19:28:20.010628 Last errno: 2, No such file or directory
11451 19:28:20.017364 [1mSubtest pan-submit-error-bad-bo-handles: SKIP (0<14>[ 22.108364] [IGT] panfrost_submit: executing
11452 19:28:20.020482 .000s)[0m
11453 19:28:20.027138 IGT-Version: 1.28-ga<14>[ 22.115978] [IGT] panfrost_submit: exiting, ret=77
11454 19:28:20.030581 44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11455 19:28:20.040428 Using IGT_SRANDO<8>[ 22.126172] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-reset RESULT=skip>
11456 19:28:20.040539 M=1713468499 for randomisation
11457 19:28:20.040781 Received signal: <TESTCASE> TEST_CASE_ID=pan-reset RESULT=skip
11459 19:28:20.050518 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11460 19:28:20.050602 Test requirement: !(fd<0)
11461 19:28:20.056675 No known gpu found <14>[ 22.146947] [IGT] panfrost_submit: executing
11462 19:28:20.066498 for chipset flags 0x32 (panfrost<14>[ 22.154959] [IGT] panfrost_submit: exiting, ret=77
11463 19:28:20.066600 )
11464 19:28:20.070320 Last errno: 2, No such file or directory
11465 19:28:20.079736 [1mSubtest pan-sub<8>[ 22.165327] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-and-close RESULT=skip>
11466 19:28:20.080010 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-and-close RESULT=skip
11468 19:28:20.083160 mit-error-bad-requirements: SKIP (0.000s)[0m
11469 19:28:20.089906 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11470 19:28:20.096338 Using IGT_SRANDOM=1713468499 for randomisatio<14>[ 22.187096] [IGT] panfrost_submit: executing
11471 19:28:20.096469 n
11472 19:28:20.106282 Test requirement not met in f<14>[ 22.194661] [IGT] panfrost_submit: exiting, ret=77
11473 19:28:20.109492 unction drm_open_driver, file ../lib/drmtest.c:694:
11474 19:28:20.119618 Test requir<8>[ 22.205086] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip>
11475 19:28:20.119717 ement: !(fd<0)
11476 19:28:20.119986 Received signal: <TESTCASE> TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip
11478 19:28:20.126111 No known gpu fou<8>[ 22.215301] <LAVA_SIGNAL_TESTSET STOP>
11479 19:28:20.126382 Received signal: <TESTSET> STOP
11480 19:28:20.126452 Closing test_set panfrost_submit
11481 19:28:20.132383 nd for chipset f<8>[ 22.221776] <LAVA_SIGNAL_ENDRUN 0_igt-gpu-panfrost 13420392_1.5.2.3.1>
11482 19:28:20.132734 Received signal: <ENDRUN> 0_igt-gpu-panfrost 13420392_1.5.2.3.1
11483 19:28:20.132816 Ending use of test pattern.
11484 19:28:20.132879 Ending test lava.0_igt-gpu-panfrost (13420392_1.5.2.3.1), duration 0.77
11486 19:28:20.136078 lags 0x32 (panfrost)
11487 19:28:20.138923 Last errno: 2, No such file or directory
11488 19:28:20.146040 [1mSubtest pan-submit-error-bad-out-sync: SKIP (0.000s)[0m
11489 19:28:20.152397 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11490 19:28:20.155435 Using IGT_SRANDOM=1713468499 for randomisation
11491 19:28:20.162256 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11492 19:28:20.165263 Test requirement: !(fd<0)
11493 19:28:20.168982 No known gpu found for chipset flags 0x32 (panfrost)
11494 19:28:20.171847 Last errno: 2, No such file or directory
11495 19:28:20.175311 [1mSubtest pan-reset: SKIP (0.000s)[0m
11496 19:28:20.182071 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11497 19:28:20.185131 Using IGT_SRANDOM=1713468500 for randomisation
11498 19:28:20.192294 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11499 19:28:20.195075 Test requirement: !(fd<0)
11500 19:28:20.201764 No known gpu found for chipset flags 0x32 (panfrost)
11501 19:28:20.205375 Last errno: 2, No such file or directory
11502 19:28:20.208179 [1mSubtest pan-submit-and-close: SKIP (0.000s)[0m
11503 19:28:20.215093 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11504 19:28:20.218073 Using IGT_SRANDOM=1713468500 for randomisation
11505 19:28:20.224816 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11506 19:28:20.228381 Test requirement: !(fd<0)
11507 19:28:20.231539 No known gpu found for chipset flags 0x32 (panfrost)
11508 19:28:20.238286 Last errno: 2, No such file or directory
11509 19:28:20.241444 [1mSubtest pan-unhandled-pagefault: SKIP (0.000s)[0m
11510 19:28:20.241529 + set +x
11511 19:28:20.244618 <LAVA_TEST_RUNNER EXIT>
11512 19:28:20.244876 ok: lava_test_shell seems to have completed
11513 19:28:20.245213 base-params:
result: skip
set: panfrost_get_param
gem-new-0:
result: skip
set: panfrost_gem_new
gem-new-4096:
result: skip
set: panfrost_gem_new
gem-new-zeroed:
result: skip
set: panfrost_gem_new
gem-prime-import:
result: skip
set: panfrost_prime
get-bad-padding:
result: skip
set: panfrost_get_param
get-bad-param:
result: skip
set: panfrost_get_param
pan-reset:
result: skip
set: panfrost_submit
pan-submit:
result: skip
set: panfrost_submit
pan-submit-and-close:
result: skip
set: panfrost_submit
pan-submit-error-bad-bo-handles:
result: skip
set: panfrost_submit
pan-submit-error-bad-in-syncs:
result: skip
set: panfrost_submit
pan-submit-error-bad-out-sync:
result: skip
set: panfrost_submit
pan-submit-error-bad-requirements:
result: skip
set: panfrost_submit
pan-submit-error-no-jc:
result: skip
set: panfrost_submit
pan-unhandled-pagefault:
result: skip
set: panfrost_submit
11514 19:28:20.245348 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11515 19:28:20.245443 end: 3 lava-test-retry (duration 00:00:01) [common]
11516 19:28:20.245545 start: 4 finalize (timeout 00:07:01) [common]
11517 19:28:20.245639 start: 4.1 power-off (timeout 00:00:30) [common]
11518 19:28:20.245807 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=off'
11519 19:28:20.321548 >> Command sent successfully.
11520 19:28:20.323969 Returned 0 in 0 seconds
11521 19:28:20.424359 end: 4.1 power-off (duration 00:00:00) [common]
11523 19:28:20.424763 start: 4.2 read-feedback (timeout 00:07:00) [common]
11524 19:28:20.425037 Listened to connection for namespace 'common' for up to 1s
11525 19:28:21.425410 Finalising connection for namespace 'common'
11526 19:28:21.425597 Disconnecting from shell: Finalise
11527 19:28:21.425681 / #
11528 19:28:21.525995 end: 4.2 read-feedback (duration 00:00:01) [common]
11529 19:28:21.526185 end: 4 finalize (duration 00:00:01) [common]
11530 19:28:21.526307 Cleaning after the job
11531 19:28:21.526423 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13420392/tftp-deploy-6dj1q895/ramdisk
11532 19:28:21.533510 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13420392/tftp-deploy-6dj1q895/kernel
11533 19:28:21.540817 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13420392/tftp-deploy-6dj1q895/dtb
11534 19:28:21.541003 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13420392/tftp-deploy-6dj1q895/modules
11535 19:28:21.546744 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/13420392
11536 19:28:21.670233 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/13420392
11537 19:28:21.670433 Job finished correctly