Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 24
- Errors: 0
- Kernel Errors: 33
- Boot result: PASS
1 19:25:26.625010 lava-dispatcher, installed at version: 2024.01
2 19:25:26.625236 start: 0 validate
3 19:25:26.625409 Start time: 2024-04-18 19:25:26.625401+00:00 (UTC)
4 19:25:26.625540 Using caching service: 'http://localhost/cache/?uri=%s'
5 19:25:26.625675 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 19:25:26.896011 Using caching service: 'http://localhost/cache/?uri=%s'
7 19:25:26.896183 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 19:25:52.898468 Using caching service: 'http://localhost/cache/?uri=%s'
9 19:25:52.899181 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 19:25:53.170788 Using caching service: 'http://localhost/cache/?uri=%s'
11 19:25:53.170941 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 19:25:56.942507 validate duration: 30.32
14 19:25:56.942773 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 19:25:56.942870 start: 1.1 download-retry (timeout 00:10:00) [common]
16 19:25:56.942957 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 19:25:56.943078 Not decompressing ramdisk as can be used compressed.
18 19:25:56.943161 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 19:25:56.943259 saving as /var/lib/lava/dispatcher/tmp/13420368/tftp-deploy-03xmkh_w/ramdisk/rootfs.cpio.gz
20 19:25:56.943321 total size: 47897469 (45 MB)
21 19:25:57.209719 progress 0 % (0 MB)
22 19:25:57.229973 progress 5 % (2 MB)
23 19:25:57.249992 progress 10 % (4 MB)
24 19:25:57.270055 progress 15 % (6 MB)
25 19:25:57.290000 progress 20 % (9 MB)
26 19:25:57.309985 progress 25 % (11 MB)
27 19:25:57.323249 progress 30 % (13 MB)
28 19:25:57.336664 progress 35 % (16 MB)
29 19:25:57.349943 progress 40 % (18 MB)
30 19:25:57.363535 progress 45 % (20 MB)
31 19:25:57.376157 progress 50 % (22 MB)
32 19:25:57.389160 progress 55 % (25 MB)
33 19:25:57.402758 progress 60 % (27 MB)
34 19:25:57.416038 progress 65 % (29 MB)
35 19:25:57.428712 progress 70 % (32 MB)
36 19:25:57.441034 progress 75 % (34 MB)
37 19:25:57.453469 progress 80 % (36 MB)
38 19:25:57.466649 progress 85 % (38 MB)
39 19:25:57.479870 progress 90 % (41 MB)
40 19:25:57.492783 progress 95 % (43 MB)
41 19:25:57.505709 progress 100 % (45 MB)
42 19:25:57.505972 45 MB downloaded in 0.56 s (81.18 MB/s)
43 19:25:57.506178 end: 1.1.1 http-download (duration 00:00:01) [common]
45 19:25:57.506471 end: 1.1 download-retry (duration 00:00:01) [common]
46 19:25:57.506566 start: 1.2 download-retry (timeout 00:09:59) [common]
47 19:25:57.506653 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 19:25:57.506794 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 19:25:57.506864 saving as /var/lib/lava/dispatcher/tmp/13420368/tftp-deploy-03xmkh_w/kernel/Image
50 19:25:57.506927 total size: 54286848 (51 MB)
51 19:25:57.506990 No compression specified
52 19:25:57.508104 progress 0 % (0 MB)
53 19:25:57.522151 progress 5 % (2 MB)
54 19:25:57.536985 progress 10 % (5 MB)
55 19:25:57.551919 progress 15 % (7 MB)
56 19:25:57.566862 progress 20 % (10 MB)
57 19:25:57.581854 progress 25 % (12 MB)
58 19:25:57.596620 progress 30 % (15 MB)
59 19:25:57.611681 progress 35 % (18 MB)
60 19:25:57.627136 progress 40 % (20 MB)
61 19:25:57.642200 progress 45 % (23 MB)
62 19:25:57.656281 progress 50 % (25 MB)
63 19:25:57.670291 progress 55 % (28 MB)
64 19:25:57.684659 progress 60 % (31 MB)
65 19:25:57.699448 progress 65 % (33 MB)
66 19:25:57.714388 progress 70 % (36 MB)
67 19:25:57.729011 progress 75 % (38 MB)
68 19:25:57.743754 progress 80 % (41 MB)
69 19:25:57.758688 progress 85 % (44 MB)
70 19:25:57.773678 progress 90 % (46 MB)
71 19:25:57.788274 progress 95 % (49 MB)
72 19:25:57.802194 progress 100 % (51 MB)
73 19:25:57.802497 51 MB downloaded in 0.30 s (175.16 MB/s)
74 19:25:57.802657 end: 1.2.1 http-download (duration 00:00:00) [common]
76 19:25:57.802892 end: 1.2 download-retry (duration 00:00:00) [common]
77 19:25:57.802980 start: 1.3 download-retry (timeout 00:09:59) [common]
78 19:25:57.803076 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 19:25:57.803217 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 19:25:57.803286 saving as /var/lib/lava/dispatcher/tmp/13420368/tftp-deploy-03xmkh_w/dtb/mt8192-asurada-spherion-r0.dtb
81 19:25:57.803348 total size: 47230 (0 MB)
82 19:25:57.803411 No compression specified
83 19:25:57.804535 progress 69 % (0 MB)
84 19:25:57.804877 progress 100 % (0 MB)
85 19:25:57.805057 0 MB downloaded in 0.00 s (26.40 MB/s)
86 19:25:57.805184 end: 1.3.1 http-download (duration 00:00:00) [common]
88 19:25:57.805410 end: 1.3 download-retry (duration 00:00:00) [common]
89 19:25:57.805500 start: 1.4 download-retry (timeout 00:09:59) [common]
90 19:25:57.805585 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 19:25:57.805700 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 19:25:57.805769 saving as /var/lib/lava/dispatcher/tmp/13420368/tftp-deploy-03xmkh_w/modules/modules.tar
93 19:25:57.805830 total size: 8631416 (8 MB)
94 19:25:57.805893 Using unxz to decompress xz
95 19:25:57.810267 progress 0 % (0 MB)
96 19:25:57.830806 progress 5 % (0 MB)
97 19:25:57.857458 progress 10 % (0 MB)
98 19:25:57.882144 progress 15 % (1 MB)
99 19:25:57.906448 progress 20 % (1 MB)
100 19:25:57.932763 progress 25 % (2 MB)
101 19:25:57.959356 progress 30 % (2 MB)
102 19:25:57.983825 progress 35 % (2 MB)
103 19:25:58.009638 progress 40 % (3 MB)
104 19:25:58.034149 progress 45 % (3 MB)
105 19:25:58.059443 progress 50 % (4 MB)
106 19:25:58.084925 progress 55 % (4 MB)
107 19:25:58.113753 progress 60 % (4 MB)
108 19:25:58.140414 progress 65 % (5 MB)
109 19:25:58.167405 progress 70 % (5 MB)
110 19:25:58.192852 progress 75 % (6 MB)
111 19:25:58.219643 progress 80 % (6 MB)
112 19:25:58.246233 progress 85 % (7 MB)
113 19:25:58.275395 progress 90 % (7 MB)
114 19:25:58.305052 progress 95 % (7 MB)
115 19:25:58.331778 progress 100 % (8 MB)
116 19:25:58.337227 8 MB downloaded in 0.53 s (15.49 MB/s)
117 19:25:58.337579 end: 1.4.1 http-download (duration 00:00:01) [common]
119 19:25:58.337990 end: 1.4 download-retry (duration 00:00:01) [common]
120 19:25:58.338129 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 19:25:58.338275 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 19:25:58.338413 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 19:25:58.338552 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 19:25:58.338861 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/13420368/lava-overlay-it9sry1k
125 19:25:58.339064 makedir: /var/lib/lava/dispatcher/tmp/13420368/lava-overlay-it9sry1k/lava-13420368/bin
126 19:25:58.339220 makedir: /var/lib/lava/dispatcher/tmp/13420368/lava-overlay-it9sry1k/lava-13420368/tests
127 19:25:58.339372 makedir: /var/lib/lava/dispatcher/tmp/13420368/lava-overlay-it9sry1k/lava-13420368/results
128 19:25:58.339543 Creating /var/lib/lava/dispatcher/tmp/13420368/lava-overlay-it9sry1k/lava-13420368/bin/lava-add-keys
129 19:25:58.339752 Creating /var/lib/lava/dispatcher/tmp/13420368/lava-overlay-it9sry1k/lava-13420368/bin/lava-add-sources
130 19:25:58.339945 Creating /var/lib/lava/dispatcher/tmp/13420368/lava-overlay-it9sry1k/lava-13420368/bin/lava-background-process-start
131 19:25:58.340137 Creating /var/lib/lava/dispatcher/tmp/13420368/lava-overlay-it9sry1k/lava-13420368/bin/lava-background-process-stop
132 19:25:58.340326 Creating /var/lib/lava/dispatcher/tmp/13420368/lava-overlay-it9sry1k/lava-13420368/bin/lava-common-functions
133 19:25:58.340516 Creating /var/lib/lava/dispatcher/tmp/13420368/lava-overlay-it9sry1k/lava-13420368/bin/lava-echo-ipv4
134 19:25:58.340703 Creating /var/lib/lava/dispatcher/tmp/13420368/lava-overlay-it9sry1k/lava-13420368/bin/lava-install-packages
135 19:25:58.340893 Creating /var/lib/lava/dispatcher/tmp/13420368/lava-overlay-it9sry1k/lava-13420368/bin/lava-installed-packages
136 19:25:58.341078 Creating /var/lib/lava/dispatcher/tmp/13420368/lava-overlay-it9sry1k/lava-13420368/bin/lava-os-build
137 19:25:58.341268 Creating /var/lib/lava/dispatcher/tmp/13420368/lava-overlay-it9sry1k/lava-13420368/bin/lava-probe-channel
138 19:25:58.341454 Creating /var/lib/lava/dispatcher/tmp/13420368/lava-overlay-it9sry1k/lava-13420368/bin/lava-probe-ip
139 19:25:58.341643 Creating /var/lib/lava/dispatcher/tmp/13420368/lava-overlay-it9sry1k/lava-13420368/bin/lava-target-ip
140 19:25:58.341830 Creating /var/lib/lava/dispatcher/tmp/13420368/lava-overlay-it9sry1k/lava-13420368/bin/lava-target-mac
141 19:25:58.342017 Creating /var/lib/lava/dispatcher/tmp/13420368/lava-overlay-it9sry1k/lava-13420368/bin/lava-target-storage
142 19:25:58.342209 Creating /var/lib/lava/dispatcher/tmp/13420368/lava-overlay-it9sry1k/lava-13420368/bin/lava-test-case
143 19:25:58.342405 Creating /var/lib/lava/dispatcher/tmp/13420368/lava-overlay-it9sry1k/lava-13420368/bin/lava-test-event
144 19:25:58.342592 Creating /var/lib/lava/dispatcher/tmp/13420368/lava-overlay-it9sry1k/lava-13420368/bin/lava-test-feedback
145 19:25:58.342782 Creating /var/lib/lava/dispatcher/tmp/13420368/lava-overlay-it9sry1k/lava-13420368/bin/lava-test-raise
146 19:25:58.342970 Creating /var/lib/lava/dispatcher/tmp/13420368/lava-overlay-it9sry1k/lava-13420368/bin/lava-test-reference
147 19:25:58.343162 Creating /var/lib/lava/dispatcher/tmp/13420368/lava-overlay-it9sry1k/lava-13420368/bin/lava-test-runner
148 19:25:58.343351 Creating /var/lib/lava/dispatcher/tmp/13420368/lava-overlay-it9sry1k/lava-13420368/bin/lava-test-set
149 19:25:58.343542 Creating /var/lib/lava/dispatcher/tmp/13420368/lava-overlay-it9sry1k/lava-13420368/bin/lava-test-shell
150 19:25:58.343738 Updating /var/lib/lava/dispatcher/tmp/13420368/lava-overlay-it9sry1k/lava-13420368/bin/lava-install-packages (oe)
151 19:25:58.343959 Updating /var/lib/lava/dispatcher/tmp/13420368/lava-overlay-it9sry1k/lava-13420368/bin/lava-installed-packages (oe)
152 19:25:58.344141 Creating /var/lib/lava/dispatcher/tmp/13420368/lava-overlay-it9sry1k/lava-13420368/environment
153 19:25:58.344294 LAVA metadata
154 19:25:58.344410 - LAVA_JOB_ID=13420368
155 19:25:58.344516 - LAVA_DISPATCHER_IP=192.168.201.1
156 19:25:58.344680 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 19:25:58.344787 skipped lava-vland-overlay
158 19:25:58.344917 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 19:25:58.345042 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 19:25:58.345144 skipped lava-multinode-overlay
161 19:25:58.345272 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 19:25:58.345405 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 19:25:58.345531 Loading test definitions
164 19:25:58.345672 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 19:25:58.345793 Using /lava-13420368 at stage 0
166 19:25:58.346277 uuid=13420368_1.5.2.3.1 testdef=None
167 19:25:58.346415 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 19:25:58.346549 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 19:25:58.347338 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 19:25:58.347690 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 19:25:58.348621 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 19:25:58.348983 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 19:25:58.349863 runner path: /var/lib/lava/dispatcher/tmp/13420368/lava-overlay-it9sry1k/lava-13420368/0/tests/0_igt-kms-mediatek test_uuid 13420368_1.5.2.3.1
176 19:25:58.350088 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 19:25:58.350428 Creating lava-test-runner.conf files
179 19:25:58.350506 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/13420368/lava-overlay-it9sry1k/lava-13420368/0 for stage 0
180 19:25:58.350613 - 0_igt-kms-mediatek
181 19:25:58.350727 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 19:25:58.350819 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 19:25:58.358920 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 19:25:58.359071 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 19:25:58.359183 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 19:25:58.359281 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 19:25:58.359376 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 19:26:00.184824 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
189 19:26:00.185231 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
190 19:26:00.185363 extracting modules file /var/lib/lava/dispatcher/tmp/13420368/tftp-deploy-03xmkh_w/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13420368/extract-overlay-ramdisk-eve729yh/ramdisk
191 19:26:00.419510 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 19:26:00.419697 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 19:26:00.419797 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13420368/compress-overlay-w83gt0sn/overlay-1.5.2.4.tar.gz to ramdisk
194 19:26:00.419873 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13420368/compress-overlay-w83gt0sn/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/13420368/extract-overlay-ramdisk-eve729yh/ramdisk
195 19:26:00.426635 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 19:26:00.426780 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 19:26:00.426880 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 19:26:00.426972 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 19:26:00.427061 Building ramdisk /var/lib/lava/dispatcher/tmp/13420368/extract-overlay-ramdisk-eve729yh/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/13420368/extract-overlay-ramdisk-eve729yh/ramdisk
200 19:26:01.708615 >> 466207 blocks
201 19:26:08.182991 rename /var/lib/lava/dispatcher/tmp/13420368/extract-overlay-ramdisk-eve729yh/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/13420368/tftp-deploy-03xmkh_w/ramdisk/ramdisk.cpio.gz
202 19:26:08.183523 end: 1.5.7 compress-ramdisk (duration 00:00:08) [common]
203 19:26:08.183695 start: 1.5.8 prepare-kernel (timeout 00:09:49) [common]
204 19:26:08.183844 start: 1.5.8.1 prepare-fit (timeout 00:09:49) [common]
205 19:26:08.184000 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/13420368/tftp-deploy-03xmkh_w/kernel/Image'
206 19:26:23.060983 Returned 0 in 14 seconds
207 19:26:23.161786 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/13420368/tftp-deploy-03xmkh_w/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/13420368/tftp-deploy-03xmkh_w/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/13420368/tftp-deploy-03xmkh_w/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/13420368/tftp-deploy-03xmkh_w/kernel/image.itb
208 19:26:24.050795 output: FIT description: Kernel Image image with one or more FDT blobs
209 19:26:24.051271 output: Created: Thu Apr 18 20:26:23 2024
210 19:26:24.051393 output: Image 0 (kernel-1)
211 19:26:24.051492 output: Description:
212 19:26:24.051590 output: Created: Thu Apr 18 20:26:23 2024
213 19:26:24.051691 output: Type: Kernel Image
214 19:26:24.051784 output: Compression: lzma compressed
215 19:26:24.051877 output: Data Size: 12910355 Bytes = 12607.77 KiB = 12.31 MiB
216 19:26:24.051995 output: Architecture: AArch64
217 19:26:24.052106 output: OS: Linux
218 19:26:24.052199 output: Load Address: 0x00000000
219 19:26:24.052321 output: Entry Point: 0x00000000
220 19:26:24.052411 output: Hash algo: crc32
221 19:26:24.052500 output: Hash value: bbac8b0b
222 19:26:24.052621 output: Image 1 (fdt-1)
223 19:26:24.052712 output: Description: mt8192-asurada-spherion-r0
224 19:26:24.052803 output: Created: Thu Apr 18 20:26:23 2024
225 19:26:24.052923 output: Type: Flat Device Tree
226 19:26:24.053011 output: Compression: uncompressed
227 19:26:24.053114 output: Data Size: 47230 Bytes = 46.12 KiB = 0.05 MiB
228 19:26:24.053218 output: Architecture: AArch64
229 19:26:24.053306 output: Hash algo: crc32
230 19:26:24.053408 output: Hash value: 4bf0d1ac
231 19:26:24.053511 output: Image 2 (ramdisk-1)
232 19:26:24.053599 output: Description: unavailable
233 19:26:24.053702 output: Created: Thu Apr 18 20:26:23 2024
234 19:26:24.053805 output: Type: RAMDisk Image
235 19:26:24.053892 output: Compression: Unknown Compression
236 19:26:24.053995 output: Data Size: 61054618 Bytes = 59623.65 KiB = 58.23 MiB
237 19:26:24.054099 output: Architecture: AArch64
238 19:26:24.054186 output: OS: Linux
239 19:26:24.054287 output: Load Address: unavailable
240 19:26:24.054401 output: Entry Point: unavailable
241 19:26:24.054489 output: Hash algo: crc32
242 19:26:24.054607 output: Hash value: f985c4aa
243 19:26:24.054695 output: Default Configuration: 'conf-1'
244 19:26:24.054781 output: Configuration 0 (conf-1)
245 19:26:24.054897 output: Description: mt8192-asurada-spherion-r0
246 19:26:24.054984 output: Kernel: kernel-1
247 19:26:24.055087 output: Init Ramdisk: ramdisk-1
248 19:26:24.055189 output: FDT: fdt-1
249 19:26:24.055274 output: Loadables: kernel-1
250 19:26:24.055376 output:
251 19:26:24.055671 end: 1.5.8.1 prepare-fit (duration 00:00:16) [common]
252 19:26:24.055828 end: 1.5.8 prepare-kernel (duration 00:00:16) [common]
253 19:26:24.056013 end: 1.5 prepare-tftp-overlay (duration 00:00:26) [common]
254 19:26:24.056168 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:33) [common]
255 19:26:24.056303 No LXC device requested
256 19:26:24.056422 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 19:26:24.056551 start: 1.7 deploy-device-env (timeout 00:09:33) [common]
258 19:26:24.056667 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 19:26:24.056775 Checking files for TFTP limit of 4294967296 bytes.
260 19:26:24.057469 end: 1 tftp-deploy (duration 00:00:27) [common]
261 19:26:24.057615 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 19:26:24.057744 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 19:26:24.057917 substitutions:
264 19:26:24.058014 - {DTB}: 13420368/tftp-deploy-03xmkh_w/dtb/mt8192-asurada-spherion-r0.dtb
265 19:26:24.058110 - {INITRD}: 13420368/tftp-deploy-03xmkh_w/ramdisk/ramdisk.cpio.gz
266 19:26:24.058201 - {KERNEL}: 13420368/tftp-deploy-03xmkh_w/kernel/Image
267 19:26:24.058291 - {LAVA_MAC}: None
268 19:26:24.058419 - {PRESEED_CONFIG}: None
269 19:26:24.058509 - {PRESEED_LOCAL}: None
270 19:26:24.058598 - {RAMDISK}: 13420368/tftp-deploy-03xmkh_w/ramdisk/ramdisk.cpio.gz
271 19:26:24.058688 - {ROOT_PART}: None
272 19:26:24.058777 - {ROOT}: None
273 19:26:24.058865 - {SERVER_IP}: 192.168.201.1
274 19:26:24.058953 - {TEE}: None
275 19:26:24.059041 Parsed boot commands:
276 19:26:24.059127 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 19:26:24.059377 Parsed boot commands: tftpboot 192.168.201.1 13420368/tftp-deploy-03xmkh_w/kernel/image.itb 13420368/tftp-deploy-03xmkh_w/kernel/cmdline
278 19:26:24.059506 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 19:26:24.059636 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 19:26:24.059770 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 19:26:24.059895 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 19:26:24.060001 Not connected, no need to disconnect.
283 19:26:24.060114 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 19:26:24.060241 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 19:26:24.060346 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
286 19:26:24.065194 Setting prompt string to ['lava-test: # ']
287 19:26:24.065736 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 19:26:24.065926 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 19:26:24.066099 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 19:26:24.066249 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 19:26:24.066613 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
292 19:26:29.209420 >> Command sent successfully.
293 19:26:29.212226 Returned 0 in 5 seconds
294 19:26:29.312661 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 19:26:29.313106 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 19:26:29.313237 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 19:26:29.313358 Setting prompt string to 'Starting depthcharge on Spherion...'
299 19:26:29.313458 Changing prompt to 'Starting depthcharge on Spherion...'
300 19:26:29.313560 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 19:26:29.313940 [Enter `^Ec?' for help]
302 19:26:29.714457
303 19:26:29.714621
304 19:26:29.714724 F0: 102B 0000
305 19:26:29.714818
306 19:26:29.714911 F3: 1001 0000 [0200]
307 19:26:29.717468
308 19:26:29.717575 F3: 1001 0000
309 19:26:29.717665
310 19:26:29.717752 F7: 102D 0000
311 19:26:29.717839
312 19:26:29.720938 F1: 0000 0000
313 19:26:29.721033
314 19:26:29.721100 V0: 0000 0000 [0001]
315 19:26:29.721163
316 19:26:29.724393 00: 0007 8000
317 19:26:29.724536
318 19:26:29.724634 01: 0000 0000
319 19:26:29.724727
320 19:26:29.727627 BP: 0C00 0209 [0000]
321 19:26:29.727720
322 19:26:29.727789 G0: 1182 0000
323 19:26:29.727852
324 19:26:29.731027 EC: 0000 0021 [4000]
325 19:26:29.731153
326 19:26:29.731250 S7: 0000 0000 [0000]
327 19:26:29.731340
328 19:26:29.734414 CC: 0000 0000 [0001]
329 19:26:29.734506
330 19:26:29.734573 T0: 0000 0040 [010F]
331 19:26:29.734640
332 19:26:29.737690 Jump to BL
333 19:26:29.737782
334 19:26:29.760777
335 19:26:29.760938
336 19:26:29.761008
337 19:26:29.771003 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 19:26:29.774192 ARM64: Exception handlers installed.
339 19:26:29.774355 ARM64: Testing exception
340 19:26:29.777507 ARM64: Done test exception
341 19:26:29.784495 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 19:26:29.794419 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 19:26:29.801483 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 19:26:29.811799 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 19:26:29.818650 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 19:26:29.829186 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 19:26:29.838740 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 19:26:29.845532 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 19:26:29.864471 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 19:26:29.867964 WDT: Last reset was cold boot
351 19:26:29.870613 SPI1(PAD0) initialized at 2873684 Hz
352 19:26:29.874473 SPI5(PAD0) initialized at 992727 Hz
353 19:26:29.877714 VBOOT: Loading verstage.
354 19:26:29.883755 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 19:26:29.887544 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 19:26:29.890602 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 19:26:29.893854 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 19:26:29.901277 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 19:26:29.908329 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 19:26:29.919280 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
361 19:26:29.919439
362 19:26:29.919515
363 19:26:29.929134 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 19:26:29.932409 ARM64: Exception handlers installed.
365 19:26:29.935645 ARM64: Testing exception
366 19:26:29.935753 ARM64: Done test exception
367 19:26:29.942219 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 19:26:29.945366 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 19:26:29.960123 Probing TPM: . done!
370 19:26:29.960289 TPM ready after 0 ms
371 19:26:29.966815 Connected to device vid:did:rid of 1ae0:0028:00
372 19:26:29.976968 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 19:26:30.039225 Initialized TPM device CR50 revision 0
374 19:26:30.066591 tlcl_send_startup: Startup return code is 0
375 19:26:30.066746 TPM: setup succeeded
376 19:26:30.080884 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 19:26:30.089542 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 19:26:30.103600 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 19:26:30.111893 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 19:26:30.115508 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 19:26:30.119261 in-header: 03 07 00 00 08 00 00 00
382 19:26:30.122642 in-data: aa e4 47 04 13 02 00 00
383 19:26:30.126546 Chrome EC: UHEPI supported
384 19:26:30.130686 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 19:26:30.134027 in-header: 03 ad 00 00 08 00 00 00
386 19:26:30.138721 in-data: 00 20 20 08 00 00 00 00
387 19:26:30.138860 Phase 1
388 19:26:30.142253 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 19:26:30.148119 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 19:26:30.155318 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 19:26:30.158513 Recovery requested (1009000e)
392 19:26:30.165201 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 19:26:30.170578 tlcl_extend: response is 0
394 19:26:30.173969 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 19:26:30.183915 tlcl_extend: response is 0
396 19:26:30.190637 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 19:26:30.211876 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 19:26:30.218541 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 19:26:30.218687
400 19:26:30.218757
401 19:26:30.228555 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 19:26:30.231761 ARM64: Exception handlers installed.
403 19:26:30.231884 ARM64: Testing exception
404 19:26:30.234930 ARM64: Done test exception
405 19:26:30.257049 pmic_efuse_setting: Set efuses in 11 msecs
406 19:26:30.260287 pmwrap_interface_init: Select PMIF_VLD_RDY
407 19:26:30.266926 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 19:26:30.270141 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 19:26:30.277458 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 19:26:30.280379 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 19:26:30.286719 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 19:26:30.290197 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 19:26:30.293465 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 19:26:30.300837 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 19:26:30.304062 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 19:26:30.310595 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 19:26:30.313954 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 19:26:30.317223 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 19:26:30.323870 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 19:26:30.330539 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 19:26:30.333619 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 19:26:30.340627 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 19:26:30.346891 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 19:26:30.350110 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 19:26:30.357024 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 19:26:30.364591 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 19:26:30.366944 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 19:26:30.373646 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 19:26:30.380470 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 19:26:30.383948 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 19:26:30.390704 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 19:26:30.397256 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 19:26:30.400496 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 19:26:30.406817 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 19:26:30.410079 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 19:26:30.416912 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 19:26:30.420082 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 19:26:30.426847 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 19:26:30.430215 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 19:26:30.436908 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 19:26:30.440198 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 19:26:30.446816 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 19:26:30.450200 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 19:26:30.456894 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 19:26:30.460178 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 19:26:30.463395 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 19:26:30.469977 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 19:26:30.473199 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 19:26:30.477051 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 19:26:30.483617 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 19:26:30.486772 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 19:26:30.490136 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 19:26:30.493515 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 19:26:30.499889 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 19:26:30.503207 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 19:26:30.506833 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 19:26:30.510074 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 19:26:30.520001 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 19:26:30.526594 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 19:26:30.533549 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 19:26:30.539903 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 19:26:30.549921 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 19:26:30.553285 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 19:26:30.556646 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 19:26:30.563308 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 19:26:30.569792 [RTC]rtc_enable_dcxo,68: con=0x406, osc32con=0xde70, sec=0x32
467 19:26:30.576711 [RTC]rtc_check_state,173: con=406, pwrkey1=a357, pwrkey2=67d2
468 19:26:30.579890 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 19:26:30.583189 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 19:26:30.594516 [RTC]rtc_get_frequency_meter,154: input=15, output=758
471 19:26:30.603862 [RTC]rtc_get_frequency_meter,154: input=23, output=944
472 19:26:30.613226 [RTC]rtc_get_frequency_meter,154: input=19, output=850
473 19:26:30.622617 [RTC]rtc_get_frequency_meter,154: input=17, output=806
474 19:26:30.632340 [RTC]rtc_get_frequency_meter,154: input=16, output=782
475 19:26:30.641855 [RTC]rtc_get_frequency_meter,154: input=16, output=781
476 19:26:30.651168 [RTC]rtc_get_frequency_meter,154: input=17, output=805
477 19:26:30.654489 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 19:26:30.661547 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 19:26:30.664701 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 19:26:30.668705 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
481 19:26:30.675062 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 19:26:30.678494 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
483 19:26:30.681768 ADC[4]: Raw value=906203 ID=7
484 19:26:30.681876 ADC[3]: Raw value=213441 ID=1
485 19:26:30.685093 RAM Code: 0x71
486 19:26:30.688532 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 19:26:30.695259 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 19:26:30.701828 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 19:26:30.708569 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 19:26:30.711861 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 19:26:30.715044 in-header: 03 07 00 00 08 00 00 00
492 19:26:30.718202 in-data: aa e4 47 04 13 02 00 00
493 19:26:30.722210 Chrome EC: UHEPI supported
494 19:26:30.728808 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 19:26:30.731608 in-header: 03 ed 00 00 08 00 00 00
496 19:26:30.735078 in-data: 80 20 60 08 00 00 00 00
497 19:26:30.738584 MRC: failed to locate region type 0.
498 19:26:30.744889 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 19:26:30.748234 DRAM-K: Running full calibration
500 19:26:30.754967 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 19:26:30.755088 header.status = 0x0
502 19:26:30.758791 header.version = 0x6 (expected: 0x6)
503 19:26:30.762226 header.size = 0xd00 (expected: 0xd00)
504 19:26:30.762388 header.flags = 0x0
505 19:26:30.770114 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 19:26:30.788412 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
507 19:26:30.795526 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 19:26:30.799014 dram_init: ddr_geometry: 2
509 19:26:30.799160 [EMI] MDL number = 2
510 19:26:30.802454 [EMI] Get MDL freq = 0
511 19:26:30.802550 dram_init: ddr_type: 0
512 19:26:30.805839 is_discrete_lpddr4: 1
513 19:26:30.809260 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 19:26:30.809359
515 19:26:30.809428
516 19:26:30.812496 [Bian_co] ETT version 0.0.0.1
517 19:26:30.815853 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 19:26:30.815948
519 19:26:30.819182 dramc_set_vcore_voltage set vcore to 650000
520 19:26:30.822195 Read voltage for 800, 4
521 19:26:30.822310 Vio18 = 0
522 19:26:30.825864 Vcore = 650000
523 19:26:30.825957 Vdram = 0
524 19:26:30.826039 Vddq = 0
525 19:26:30.828837 Vmddr = 0
526 19:26:30.828926 dram_init: config_dvfs: 1
527 19:26:30.835391 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 19:26:30.841974 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 19:26:30.845765 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
530 19:26:30.848711 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
531 19:26:30.852300 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
532 19:26:30.855644 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
533 19:26:30.858748 MEM_TYPE=3, freq_sel=18
534 19:26:30.861992 sv_algorithm_assistance_LP4_1600
535 19:26:30.865249 ============ PULL DRAM RESETB DOWN ============
536 19:26:30.868608 ========== PULL DRAM RESETB DOWN end =========
537 19:26:30.875210 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 19:26:30.878588 ===================================
539 19:26:30.878720 LPDDR4 DRAM CONFIGURATION
540 19:26:30.882263 ===================================
541 19:26:30.885557 EX_ROW_EN[0] = 0x0
542 19:26:30.885675 EX_ROW_EN[1] = 0x0
543 19:26:30.888459 LP4Y_EN = 0x0
544 19:26:30.888564 WORK_FSP = 0x0
545 19:26:30.892188 WL = 0x2
546 19:26:30.895648 RL = 0x2
547 19:26:30.895748 BL = 0x2
548 19:26:30.898774 RPST = 0x0
549 19:26:30.898886 RD_PRE = 0x0
550 19:26:30.902076 WR_PRE = 0x1
551 19:26:30.902188 WR_PST = 0x0
552 19:26:30.905389 DBI_WR = 0x0
553 19:26:30.905480 DBI_RD = 0x0
554 19:26:30.908512 OTF = 0x1
555 19:26:30.911909 ===================================
556 19:26:30.915304 ===================================
557 19:26:30.915408 ANA top config
558 19:26:30.918799 ===================================
559 19:26:30.921950 DLL_ASYNC_EN = 0
560 19:26:30.925258 ALL_SLAVE_EN = 1
561 19:26:30.925360 NEW_RANK_MODE = 1
562 19:26:30.929213 DLL_IDLE_MODE = 1
563 19:26:30.932244 LP45_APHY_COMB_EN = 1
564 19:26:30.935339 TX_ODT_DIS = 1
565 19:26:30.935443 NEW_8X_MODE = 1
566 19:26:30.938785 ===================================
567 19:26:30.942550 ===================================
568 19:26:30.945939 data_rate = 1600
569 19:26:30.949066 CKR = 1
570 19:26:30.952379 DQ_P2S_RATIO = 8
571 19:26:30.956317 ===================================
572 19:26:30.959428 CA_P2S_RATIO = 8
573 19:26:30.959527 DQ_CA_OPEN = 0
574 19:26:30.963079 DQ_SEMI_OPEN = 0
575 19:26:30.967232 CA_SEMI_OPEN = 0
576 19:26:30.970825 CA_FULL_RATE = 0
577 19:26:30.970951 DQ_CKDIV4_EN = 1
578 19:26:30.974560 CA_CKDIV4_EN = 1
579 19:26:30.977757 CA_PREDIV_EN = 0
580 19:26:30.981871 PH8_DLY = 0
581 19:26:30.981987 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 19:26:30.985317 DQ_AAMCK_DIV = 4
583 19:26:30.989419 CA_AAMCK_DIV = 4
584 19:26:30.993170 CA_ADMCK_DIV = 4
585 19:26:30.993293 DQ_TRACK_CA_EN = 0
586 19:26:30.996317 CA_PICK = 800
587 19:26:30.999385 CA_MCKIO = 800
588 19:26:31.002956 MCKIO_SEMI = 0
589 19:26:31.006230 PLL_FREQ = 3068
590 19:26:31.009478 DQ_UI_PI_RATIO = 32
591 19:26:31.009608 CA_UI_PI_RATIO = 0
592 19:26:31.012961 ===================================
593 19:26:31.016216 ===================================
594 19:26:31.019509 memory_type:LPDDR4
595 19:26:31.022792 GP_NUM : 10
596 19:26:31.022912 SRAM_EN : 1
597 19:26:31.026400 MD32_EN : 0
598 19:26:31.029766 ===================================
599 19:26:31.033034 [ANA_INIT] >>>>>>>>>>>>>>
600 19:26:31.036315 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 19:26:31.039873 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 19:26:31.042988 ===================================
603 19:26:31.043117 data_rate = 1600,PCW = 0X7600
604 19:26:31.046483 ===================================
605 19:26:31.049627 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 19:26:31.056393 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 19:26:31.063714 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 19:26:31.067448 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 19:26:31.071520 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 19:26:31.075307 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 19:26:31.075420 [ANA_INIT] flow start
612 19:26:31.078823 [ANA_INIT] PLL >>>>>>>>
613 19:26:31.078919 [ANA_INIT] PLL <<<<<<<<
614 19:26:31.082472 [ANA_INIT] MIDPI >>>>>>>>
615 19:26:31.086292 [ANA_INIT] MIDPI <<<<<<<<
616 19:26:31.086444 [ANA_INIT] DLL >>>>>>>>
617 19:26:31.090232 [ANA_INIT] flow end
618 19:26:31.093757 ============ LP4 DIFF to SE enter ============
619 19:26:31.097647 ============ LP4 DIFF to SE exit ============
620 19:26:31.101560 [ANA_INIT] <<<<<<<<<<<<<
621 19:26:31.101691 [Flow] Enable top DCM control >>>>>
622 19:26:31.105358 [Flow] Enable top DCM control <<<<<
623 19:26:31.109055 Enable DLL master slave shuffle
624 19:26:31.116705 ==============================================================
625 19:26:31.116845 Gating Mode config
626 19:26:31.123931 ==============================================================
627 19:26:31.124075 Config description:
628 19:26:31.135269 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 19:26:31.138679 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 19:26:31.146186 SELPH_MODE 0: By rank 1: By Phase
631 19:26:31.150974 ==============================================================
632 19:26:31.154767 GAT_TRACK_EN = 1
633 19:26:31.158208 RX_GATING_MODE = 2
634 19:26:31.158378 RX_GATING_TRACK_MODE = 2
635 19:26:31.161797 SELPH_MODE = 1
636 19:26:31.165438 PICG_EARLY_EN = 1
637 19:26:31.169099 VALID_LAT_VALUE = 1
638 19:26:31.175871 ==============================================================
639 19:26:31.179101 Enter into Gating configuration >>>>
640 19:26:31.182148 Exit from Gating configuration <<<<
641 19:26:31.182235 Enter into DVFS_PRE_config >>>>>
642 19:26:31.195774 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 19:26:31.198972 Exit from DVFS_PRE_config <<<<<
644 19:26:31.202268 Enter into PICG configuration >>>>
645 19:26:31.202381 Exit from PICG configuration <<<<
646 19:26:31.205697 [RX_INPUT] configuration >>>>>
647 19:26:31.208878 [RX_INPUT] configuration <<<<<
648 19:26:31.215999 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 19:26:31.219003 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 19:26:31.225908 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 19:26:31.232493 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 19:26:31.239233 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 19:26:31.246630 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 19:26:31.250099 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 19:26:31.253932 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 19:26:31.257786 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 19:26:31.262558 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 19:26:31.265854 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 19:26:31.269630 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 19:26:31.273076 ===================================
661 19:26:31.277122 LPDDR4 DRAM CONFIGURATION
662 19:26:31.280762 ===================================
663 19:26:31.280878 EX_ROW_EN[0] = 0x0
664 19:26:31.284134 EX_ROW_EN[1] = 0x0
665 19:26:31.284227 LP4Y_EN = 0x0
666 19:26:31.288079 WORK_FSP = 0x0
667 19:26:31.288173 WL = 0x2
668 19:26:31.288262 RL = 0x2
669 19:26:31.291762 BL = 0x2
670 19:26:31.291859 RPST = 0x0
671 19:26:31.296134 RD_PRE = 0x0
672 19:26:31.296244 WR_PRE = 0x1
673 19:26:31.299446 WR_PST = 0x0
674 19:26:31.299533 DBI_WR = 0x0
675 19:26:31.302916 DBI_RD = 0x0
676 19:26:31.303001 OTF = 0x1
677 19:26:31.306901 ===================================
678 19:26:31.311005 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 19:26:31.314446 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 19:26:31.318224 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 19:26:31.321989 ===================================
682 19:26:31.325674 LPDDR4 DRAM CONFIGURATION
683 19:26:31.330098 ===================================
684 19:26:31.330192 EX_ROW_EN[0] = 0x10
685 19:26:31.333345 EX_ROW_EN[1] = 0x0
686 19:26:31.333434 LP4Y_EN = 0x0
687 19:26:31.337289 WORK_FSP = 0x0
688 19:26:31.337378 WL = 0x2
689 19:26:31.340638 RL = 0x2
690 19:26:31.340725 BL = 0x2
691 19:26:31.344762 RPST = 0x0
692 19:26:31.344840 RD_PRE = 0x0
693 19:26:31.344905 WR_PRE = 0x1
694 19:26:31.348152 WR_PST = 0x0
695 19:26:31.348227 DBI_WR = 0x0
696 19:26:31.352191 DBI_RD = 0x0
697 19:26:31.352267 OTF = 0x1
698 19:26:31.356101 ===================================
699 19:26:31.362368 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 19:26:31.367015 nWR fixed to 40
701 19:26:31.370198 [ModeRegInit_LP4] CH0 RK0
702 19:26:31.370326 [ModeRegInit_LP4] CH0 RK1
703 19:26:31.373573 [ModeRegInit_LP4] CH1 RK0
704 19:26:31.373664 [ModeRegInit_LP4] CH1 RK1
705 19:26:31.376922 match AC timing 13
706 19:26:31.381022 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 19:26:31.384395 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 19:26:31.392059 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 19:26:31.395867 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 19:26:31.399521 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 19:26:31.402964 [EMI DOE] emi_dcm 0
712 19:26:31.406860 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 19:26:31.406963 ==
714 19:26:31.410773 Dram Type= 6, Freq= 0, CH_0, rank 0
715 19:26:31.414327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 19:26:31.414440 ==
717 19:26:31.417874 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 19:26:31.424751 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 19:26:31.433987 [CA 0] Center 36 (6~67) winsize 62
720 19:26:31.438113 [CA 1] Center 36 (6~67) winsize 62
721 19:26:31.441305 [CA 2] Center 34 (4~65) winsize 62
722 19:26:31.444993 [CA 3] Center 33 (3~64) winsize 62
723 19:26:31.448851 [CA 4] Center 33 (3~63) winsize 61
724 19:26:31.452441 [CA 5] Center 32 (2~62) winsize 61
725 19:26:31.452543
726 19:26:31.456425 [CmdBusTrainingLP45] Vref(ca) range 1: 32
727 19:26:31.456517
728 19:26:31.460494 [CATrainingPosCal] consider 1 rank data
729 19:26:31.460582 u2DelayCellTimex100 = 270/100 ps
730 19:26:31.464323 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
731 19:26:31.467757 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
732 19:26:31.471474 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
733 19:26:31.475380 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
734 19:26:31.479193 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
735 19:26:31.482702 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
736 19:26:31.482828
737 19:26:31.486655 CA PerBit enable=1, Macro0, CA PI delay=32
738 19:26:31.486772
739 19:26:31.490683 [CBTSetCACLKResult] CA Dly = 32
740 19:26:31.490801 CS Dly: 4 (0~35)
741 19:26:31.490922 ==
742 19:26:31.494940 Dram Type= 6, Freq= 0, CH_0, rank 1
743 19:26:31.498605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 19:26:31.498727 ==
745 19:26:31.505226 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 19:26:31.512288 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 19:26:31.520337 [CA 0] Center 36 (6~67) winsize 62
748 19:26:31.524172 [CA 1] Center 36 (6~67) winsize 62
749 19:26:31.527720 [CA 2] Center 34 (4~65) winsize 62
750 19:26:31.531408 [CA 3] Center 34 (4~65) winsize 62
751 19:26:31.535209 [CA 4] Center 33 (2~64) winsize 63
752 19:26:31.535335 [CA 5] Center 32 (2~63) winsize 62
753 19:26:31.539193
754 19:26:31.539315 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 19:26:31.543218
756 19:26:31.543333 [CATrainingPosCal] consider 2 rank data
757 19:26:31.546211 u2DelayCellTimex100 = 270/100 ps
758 19:26:31.550017 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
759 19:26:31.554174 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
760 19:26:31.557811 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
761 19:26:31.561145 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
762 19:26:31.564596 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
763 19:26:31.568488 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
764 19:26:31.568614
765 19:26:31.571852 CA PerBit enable=1, Macro0, CA PI delay=32
766 19:26:31.571966
767 19:26:31.576002 [CBTSetCACLKResult] CA Dly = 32
768 19:26:31.579738 CS Dly: 5 (0~37)
769 19:26:31.579855
770 19:26:31.583218 ----->DramcWriteLeveling(PI) begin...
771 19:26:31.583347 ==
772 19:26:31.583441 Dram Type= 6, Freq= 0, CH_0, rank 0
773 19:26:31.590636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 19:26:31.590803 ==
775 19:26:31.590901 Write leveling (Byte 0): 33 => 33
776 19:26:31.593989 Write leveling (Byte 1): 28 => 28
777 19:26:31.598677 DramcWriteLeveling(PI) end<-----
778 19:26:31.598830
779 19:26:31.598926 ==
780 19:26:31.602507 Dram Type= 6, Freq= 0, CH_0, rank 0
781 19:26:31.605640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 19:26:31.605852 ==
783 19:26:31.609461 [Gating] SW mode calibration
784 19:26:31.617271 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 19:26:31.621202 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 19:26:31.624872 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 19:26:31.628744 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
788 19:26:31.635665 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
789 19:26:31.639755 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 19:26:31.643312 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 19:26:31.647158 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 19:26:31.650990 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 19:26:31.658811 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 19:26:31.662115 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 19:26:31.666138 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 19:26:31.669893 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 19:26:31.673599 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 19:26:31.677072 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 19:26:31.684791 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 19:26:31.688035 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 19:26:31.692136 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 19:26:31.695603 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 19:26:31.699363 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
804 19:26:31.706569 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
805 19:26:31.710263 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 19:26:31.714074 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 19:26:31.718020 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 19:26:31.721190 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 19:26:31.725152 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 19:26:31.732532 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 19:26:31.736546 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 19:26:31.740506 0 9 8 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
813 19:26:31.743761 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
814 19:26:31.748322 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 19:26:31.751670 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 19:26:31.759301 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 19:26:31.762990 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 19:26:31.766490 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 19:26:31.770260 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
820 19:26:31.774207 0 10 8 | B1->B0 | 3131 2323 | 1 1 | (1 1) (1 0)
821 19:26:31.778160 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
822 19:26:31.785530 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 19:26:31.789158 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 19:26:31.792997 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 19:26:31.796256 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 19:26:31.800223 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 19:26:31.807567 0 11 4 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
828 19:26:31.810750 0 11 8 | B1->B0 | 2e2e 3c3c | 1 1 | (0 0) (0 0)
829 19:26:31.814352 0 11 12 | B1->B0 | 4242 4646 | 0 0 | (1 1) (0 0)
830 19:26:31.817323 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 19:26:31.824142 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 19:26:31.827494 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 19:26:31.830771 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 19:26:31.837212 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 19:26:31.840874 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 19:26:31.844020 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
837 19:26:31.850563 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 19:26:31.853783 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 19:26:31.857690 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 19:26:31.863850 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 19:26:31.867338 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 19:26:31.870606 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 19:26:31.877232 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 19:26:31.880625 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 19:26:31.883999 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 19:26:31.890928 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 19:26:31.894119 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 19:26:31.897133 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 19:26:31.903708 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 19:26:31.907744 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 19:26:31.910506 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 19:26:31.917179 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
853 19:26:31.917340 Total UI for P1: 0, mck2ui 16
854 19:26:31.920827 best dqsien dly found for B0: ( 0, 14, 6)
855 19:26:31.924486 Total UI for P1: 0, mck2ui 16
856 19:26:31.927460 best dqsien dly found for B1: ( 0, 14, 6)
857 19:26:31.930728 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
858 19:26:31.934226 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
859 19:26:31.937745
860 19:26:31.941179 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
861 19:26:31.944088 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
862 19:26:31.947812 [Gating] SW calibration Done
863 19:26:31.947935 ==
864 19:26:31.951339 Dram Type= 6, Freq= 0, CH_0, rank 0
865 19:26:31.954498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
866 19:26:31.954618 ==
867 19:26:31.954712 RX Vref Scan: 0
868 19:26:31.954804
869 19:26:31.957731 RX Vref 0 -> 0, step: 1
870 19:26:31.957860
871 19:26:31.960995 RX Delay -130 -> 252, step: 16
872 19:26:31.964063 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
873 19:26:31.967373 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
874 19:26:31.974171 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
875 19:26:31.977641 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
876 19:26:31.981265 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
877 19:26:31.984244 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
878 19:26:31.987476 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
879 19:26:31.990728 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
880 19:26:31.997336 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
881 19:26:32.001321 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
882 19:26:32.005222 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
883 19:26:32.008900 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
884 19:26:32.012846 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
885 19:26:32.016154 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
886 19:26:32.020198 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
887 19:26:32.023449 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
888 19:26:32.023576 ==
889 19:26:32.027479 Dram Type= 6, Freq= 0, CH_0, rank 0
890 19:26:32.030794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
891 19:26:32.034840 ==
892 19:26:32.034976 DQS Delay:
893 19:26:32.035071 DQS0 = 0, DQS1 = 0
894 19:26:32.038838 DQM Delay:
895 19:26:32.038968 DQM0 = 88, DQM1 = 81
896 19:26:32.039066 DQ Delay:
897 19:26:32.042025 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
898 19:26:32.045044 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
899 19:26:32.048464 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
900 19:26:32.051830 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
901 19:26:32.051951
902 19:26:32.052051
903 19:26:32.052147 ==
904 19:26:32.054875 Dram Type= 6, Freq= 0, CH_0, rank 0
905 19:26:32.061787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
906 19:26:32.061933 ==
907 19:26:32.062034
908 19:26:32.062129
909 19:26:32.062221 TX Vref Scan disable
910 19:26:32.065162 == TX Byte 0 ==
911 19:26:32.068666 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
912 19:26:32.075260 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
913 19:26:32.075416 == TX Byte 1 ==
914 19:26:32.078266 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
915 19:26:32.085166 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
916 19:26:32.085323 ==
917 19:26:32.088392 Dram Type= 6, Freq= 0, CH_0, rank 0
918 19:26:32.091864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
919 19:26:32.092000 ==
920 19:26:32.105057 TX Vref=22, minBit 9, minWin=27, winSum=449
921 19:26:32.108384 TX Vref=24, minBit 10, minWin=27, winSum=453
922 19:26:32.111453 TX Vref=26, minBit 9, minWin=27, winSum=455
923 19:26:32.114467 TX Vref=28, minBit 5, minWin=28, winSum=459
924 19:26:32.118483 TX Vref=30, minBit 5, minWin=28, winSum=458
925 19:26:32.124430 TX Vref=32, minBit 5, minWin=28, winSum=458
926 19:26:32.128361 [TxChooseVref] Worse bit 5, Min win 28, Win sum 459, Final Vref 28
927 19:26:32.128487
928 19:26:32.131587 Final TX Range 1 Vref 28
929 19:26:32.131693
930 19:26:32.131783 ==
931 19:26:32.134945 Dram Type= 6, Freq= 0, CH_0, rank 0
932 19:26:32.137800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
933 19:26:32.137909 ==
934 19:26:32.141007
935 19:26:32.141132
936 19:26:32.141221 TX Vref Scan disable
937 19:26:32.144929 == TX Byte 0 ==
938 19:26:32.148430 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
939 19:26:32.155080 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
940 19:26:32.155236 == TX Byte 1 ==
941 19:26:32.158484 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
942 19:26:32.161870 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
943 19:26:32.165153
944 19:26:32.165261 [DATLAT]
945 19:26:32.165331 Freq=800, CH0 RK0
946 19:26:32.165421
947 19:26:32.168294 DATLAT Default: 0xa
948 19:26:32.168390 0, 0xFFFF, sum = 0
949 19:26:32.171419 1, 0xFFFF, sum = 0
950 19:26:32.171522 2, 0xFFFF, sum = 0
951 19:26:32.175043 3, 0xFFFF, sum = 0
952 19:26:32.175170 4, 0xFFFF, sum = 0
953 19:26:32.178164 5, 0xFFFF, sum = 0
954 19:26:32.178271 6, 0xFFFF, sum = 0
955 19:26:32.181505 7, 0xFFFF, sum = 0
956 19:26:32.185295 8, 0xFFFF, sum = 0
957 19:26:32.185436 9, 0x0, sum = 1
958 19:26:32.185519 10, 0x0, sum = 2
959 19:26:32.189393 11, 0x0, sum = 3
960 19:26:32.189523 12, 0x0, sum = 4
961 19:26:32.192614 best_step = 10
962 19:26:32.192743
963 19:26:32.192825 ==
964 19:26:32.195651 Dram Type= 6, Freq= 0, CH_0, rank 0
965 19:26:32.199117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
966 19:26:32.199225 ==
967 19:26:32.199323 RX Vref Scan: 1
968 19:26:32.199400
969 19:26:32.202482 Set Vref Range= 32 -> 127
970 19:26:32.202586
971 19:26:32.205723 RX Vref 32 -> 127, step: 1
972 19:26:32.205810
973 19:26:32.209267 RX Delay -79 -> 252, step: 8
974 19:26:32.209356
975 19:26:32.212433 Set Vref, RX VrefLevel [Byte0]: 32
976 19:26:32.215991 [Byte1]: 32
977 19:26:32.216083
978 19:26:32.219035 Set Vref, RX VrefLevel [Byte0]: 33
979 19:26:32.222596 [Byte1]: 33
980 19:26:32.222700
981 19:26:32.225968 Set Vref, RX VrefLevel [Byte0]: 34
982 19:26:32.229018 [Byte1]: 34
983 19:26:32.232681
984 19:26:32.232771 Set Vref, RX VrefLevel [Byte0]: 35
985 19:26:32.235962 [Byte1]: 35
986 19:26:32.239995
987 19:26:32.240092 Set Vref, RX VrefLevel [Byte0]: 36
988 19:26:32.243298 [Byte1]: 36
989 19:26:32.247988
990 19:26:32.248080 Set Vref, RX VrefLevel [Byte0]: 37
991 19:26:32.251353 [Byte1]: 37
992 19:26:32.255413
993 19:26:32.255519 Set Vref, RX VrefLevel [Byte0]: 38
994 19:26:32.258597 [Byte1]: 38
995 19:26:32.262590
996 19:26:32.262697 Set Vref, RX VrefLevel [Byte0]: 39
997 19:26:32.265915 [Byte1]: 39
998 19:26:32.270587
999 19:26:32.270681 Set Vref, RX VrefLevel [Byte0]: 40
1000 19:26:32.274216 [Byte1]: 40
1001 19:26:32.277808
1002 19:26:32.277897 Set Vref, RX VrefLevel [Byte0]: 41
1003 19:26:32.281543 [Byte1]: 41
1004 19:26:32.285530
1005 19:26:32.285644 Set Vref, RX VrefLevel [Byte0]: 42
1006 19:26:32.289142 [Byte1]: 42
1007 19:26:32.293254
1008 19:26:32.293359 Set Vref, RX VrefLevel [Byte0]: 43
1009 19:26:32.296516 [Byte1]: 43
1010 19:26:32.300637
1011 19:26:32.300731 Set Vref, RX VrefLevel [Byte0]: 44
1012 19:26:32.303807 [Byte1]: 44
1013 19:26:32.308276
1014 19:26:32.308374 Set Vref, RX VrefLevel [Byte0]: 45
1015 19:26:32.311385 [Byte1]: 45
1016 19:26:32.315443
1017 19:26:32.315541 Set Vref, RX VrefLevel [Byte0]: 46
1018 19:26:32.319001 [Byte1]: 46
1019 19:26:32.322978
1020 19:26:32.323073 Set Vref, RX VrefLevel [Byte0]: 47
1021 19:26:32.326834 [Byte1]: 47
1022 19:26:32.331024
1023 19:26:32.331134 Set Vref, RX VrefLevel [Byte0]: 48
1024 19:26:32.333986 [Byte1]: 48
1025 19:26:32.338260
1026 19:26:32.338361 Set Vref, RX VrefLevel [Byte0]: 49
1027 19:26:32.341869 [Byte1]: 49
1028 19:26:32.346084
1029 19:26:32.346179 Set Vref, RX VrefLevel [Byte0]: 50
1030 19:26:32.349334 [Byte1]: 50
1031 19:26:32.353462
1032 19:26:32.353556 Set Vref, RX VrefLevel [Byte0]: 51
1033 19:26:32.356840 [Byte1]: 51
1034 19:26:32.360980
1035 19:26:32.361082 Set Vref, RX VrefLevel [Byte0]: 52
1036 19:26:32.364276 [Byte1]: 52
1037 19:26:32.369018
1038 19:26:32.369115 Set Vref, RX VrefLevel [Byte0]: 53
1039 19:26:32.371502 [Byte1]: 53
1040 19:26:32.376243
1041 19:26:32.376337 Set Vref, RX VrefLevel [Byte0]: 54
1042 19:26:32.379591 [Byte1]: 54
1043 19:26:32.383602
1044 19:26:32.383698 Set Vref, RX VrefLevel [Byte0]: 55
1045 19:26:32.386881 [Byte1]: 55
1046 19:26:32.391292
1047 19:26:32.391408 Set Vref, RX VrefLevel [Byte0]: 56
1048 19:26:32.394499 [Byte1]: 56
1049 19:26:32.398674
1050 19:26:32.398774 Set Vref, RX VrefLevel [Byte0]: 57
1051 19:26:32.401940 [Byte1]: 57
1052 19:26:32.406482
1053 19:26:32.406574 Set Vref, RX VrefLevel [Byte0]: 58
1054 19:26:32.409608 [Byte1]: 58
1055 19:26:32.414183
1056 19:26:32.414290 Set Vref, RX VrefLevel [Byte0]: 59
1057 19:26:32.417349 [Byte1]: 59
1058 19:26:32.421482
1059 19:26:32.424651 Set Vref, RX VrefLevel [Byte0]: 60
1060 19:26:32.424774 [Byte1]: 60
1061 19:26:32.429043
1062 19:26:32.429134 Set Vref, RX VrefLevel [Byte0]: 61
1063 19:26:32.432225 [Byte1]: 61
1064 19:26:32.436697
1065 19:26:32.436795 Set Vref, RX VrefLevel [Byte0]: 62
1066 19:26:32.439720 [Byte1]: 62
1067 19:26:32.443957
1068 19:26:32.444049 Set Vref, RX VrefLevel [Byte0]: 63
1069 19:26:32.447301 [Byte1]: 63
1070 19:26:32.451414
1071 19:26:32.451519 Set Vref, RX VrefLevel [Byte0]: 64
1072 19:26:32.454687 [Byte1]: 64
1073 19:26:32.459219
1074 19:26:32.459307 Set Vref, RX VrefLevel [Byte0]: 65
1075 19:26:32.462291 [Byte1]: 65
1076 19:26:32.466847
1077 19:26:32.466937 Set Vref, RX VrefLevel [Byte0]: 66
1078 19:26:32.470105 [Byte1]: 66
1079 19:26:32.474428
1080 19:26:32.474518 Set Vref, RX VrefLevel [Byte0]: 67
1081 19:26:32.477344 [Byte1]: 67
1082 19:26:32.481717
1083 19:26:32.481810 Set Vref, RX VrefLevel [Byte0]: 68
1084 19:26:32.485087 [Byte1]: 68
1085 19:26:32.489092
1086 19:26:32.489183 Set Vref, RX VrefLevel [Byte0]: 69
1087 19:26:32.493268 [Byte1]: 69
1088 19:26:32.496825
1089 19:26:32.496916 Set Vref, RX VrefLevel [Byte0]: 70
1090 19:26:32.500045 [Byte1]: 70
1091 19:26:32.504373
1092 19:26:32.504466 Set Vref, RX VrefLevel [Byte0]: 71
1093 19:26:32.508075 [Byte1]: 71
1094 19:26:32.512158
1095 19:26:32.512249 Set Vref, RX VrefLevel [Byte0]: 72
1096 19:26:32.515307 [Byte1]: 72
1097 19:26:32.519782
1098 19:26:32.519872 Set Vref, RX VrefLevel [Byte0]: 73
1099 19:26:32.522945 [Byte1]: 73
1100 19:26:32.526973
1101 19:26:32.527065 Set Vref, RX VrefLevel [Byte0]: 74
1102 19:26:32.530208 [Byte1]: 74
1103 19:26:32.534661
1104 19:26:32.534784 Set Vref, RX VrefLevel [Byte0]: 75
1105 19:26:32.537796 [Byte1]: 75
1106 19:26:32.542213
1107 19:26:32.542334 Set Vref, RX VrefLevel [Byte0]: 76
1108 19:26:32.545525 [Byte1]: 76
1109 19:26:32.549723
1110 19:26:32.549818 Final RX Vref Byte 0 = 57 to rank0
1111 19:26:32.552950 Final RX Vref Byte 1 = 56 to rank0
1112 19:26:32.556241 Final RX Vref Byte 0 = 57 to rank1
1113 19:26:32.559748 Final RX Vref Byte 1 = 56 to rank1==
1114 19:26:32.562812 Dram Type= 6, Freq= 0, CH_0, rank 0
1115 19:26:32.569522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1116 19:26:32.569625 ==
1117 19:26:32.569694 DQS Delay:
1118 19:26:32.569756 DQS0 = 0, DQS1 = 0
1119 19:26:32.572818 DQM Delay:
1120 19:26:32.572904 DQM0 = 92, DQM1 = 85
1121 19:26:32.576489 DQ Delay:
1122 19:26:32.579682 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1123 19:26:32.583616 DQ4 =96, DQ5 =80, DQ6 =100, DQ7 =100
1124 19:26:32.583709 DQ8 =72, DQ9 =76, DQ10 =88, DQ11 =76
1125 19:26:32.586780 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =92
1126 19:26:32.586893
1127 19:26:32.587027
1128 19:26:32.598027 [DQSOSCAuto] RK0, (LSB)MR18= 0x4c42, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 390 ps
1129 19:26:32.598173 CH0 RK0: MR19=606, MR18=4C42
1130 19:26:32.605113 CH0_RK0: MR19=0x606, MR18=0x4C42, DQSOSC=390, MR23=63, INC=97, DEC=64
1131 19:26:32.605229
1132 19:26:32.608245 ----->DramcWriteLeveling(PI) begin...
1133 19:26:32.608333 ==
1134 19:26:32.612275 Dram Type= 6, Freq= 0, CH_0, rank 1
1135 19:26:32.616128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1136 19:26:32.616220 ==
1137 19:26:32.619073 Write leveling (Byte 0): 32 => 32
1138 19:26:32.622231 Write leveling (Byte 1): 30 => 30
1139 19:26:32.626319 DramcWriteLeveling(PI) end<-----
1140 19:26:32.626422
1141 19:26:32.626487 ==
1142 19:26:32.628885 Dram Type= 6, Freq= 0, CH_0, rank 1
1143 19:26:32.632204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1144 19:26:32.635490 ==
1145 19:26:32.635576 [Gating] SW mode calibration
1146 19:26:32.642423 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1147 19:26:32.649379 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1148 19:26:32.652023 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1149 19:26:32.658945 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1150 19:26:32.662622 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1151 19:26:32.665921 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 19:26:32.672801 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 19:26:32.675355 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 19:26:32.678628 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 19:26:32.685578 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 19:26:32.688800 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 19:26:32.692093 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 19:26:32.696110 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 19:26:32.702798 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 19:26:32.705983 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 19:26:32.709197 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 19:26:32.716270 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 19:26:32.719128 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 19:26:32.722587 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 19:26:32.729321 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1166 19:26:32.732508 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1167 19:26:32.736110 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 19:26:32.742524 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 19:26:32.745812 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 19:26:32.749215 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 19:26:32.755979 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 19:26:32.759365 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 19:26:32.762602 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 19:26:32.765762 0 9 8 | B1->B0 | 3131 2727 | 0 0 | (0 0) (0 0)
1175 19:26:32.772722 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1176 19:26:32.776165 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1177 19:26:32.779380 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 19:26:32.786173 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 19:26:32.789547 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 19:26:32.792550 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 19:26:32.799557 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 19:26:32.802247 0 10 8 | B1->B0 | 2c2c 2e2e | 0 0 | (0 1) (0 1)
1183 19:26:32.806231 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 19:26:32.812835 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 19:26:32.816138 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 19:26:32.819551 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 19:26:32.826237 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 19:26:32.829550 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 19:26:32.832806 0 11 4 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1190 19:26:32.839171 0 11 8 | B1->B0 | 3e3e 3a3a | 0 0 | (0 0) (0 0)
1191 19:26:32.842704 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1192 19:26:32.846229 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1193 19:26:32.849569 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 19:26:32.856347 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 19:26:32.859205 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 19:26:32.862552 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 19:26:32.869357 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 19:26:32.872865 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1199 19:26:32.876249 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 19:26:32.882525 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 19:26:32.886191 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 19:26:32.889254 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 19:26:32.896102 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 19:26:32.899271 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 19:26:32.902903 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 19:26:32.909569 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 19:26:32.912807 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 19:26:32.916230 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 19:26:32.922866 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 19:26:32.926176 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 19:26:32.929551 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 19:26:32.936274 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 19:26:32.939512 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 19:26:32.942820 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1215 19:26:32.945966 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1216 19:26:32.949382 Total UI for P1: 0, mck2ui 16
1217 19:26:32.952592 best dqsien dly found for B0: ( 0, 14, 8)
1218 19:26:32.955938 Total UI for P1: 0, mck2ui 16
1219 19:26:32.959249 best dqsien dly found for B1: ( 0, 14, 8)
1220 19:26:32.962615 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1221 19:26:32.965965 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1222 19:26:32.969336
1223 19:26:32.973185 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1224 19:26:32.976431 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1225 19:26:32.976547 [Gating] SW calibration Done
1226 19:26:32.979581 ==
1227 19:26:32.982619 Dram Type= 6, Freq= 0, CH_0, rank 1
1228 19:26:32.985952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1229 19:26:32.986081 ==
1230 19:26:32.986161 RX Vref Scan: 0
1231 19:26:32.986221
1232 19:26:32.989178 RX Vref 0 -> 0, step: 1
1233 19:26:32.989248
1234 19:26:32.993069 RX Delay -130 -> 252, step: 16
1235 19:26:32.996220 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1236 19:26:32.999513 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1237 19:26:33.006138 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1238 19:26:33.009421 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1239 19:26:33.012680 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1240 19:26:33.016248 iDelay=222, Bit 5, Center 93 (-18 ~ 205) 224
1241 19:26:33.019930 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1242 19:26:33.022614 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1243 19:26:33.029540 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1244 19:26:33.033238 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1245 19:26:33.036038 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1246 19:26:33.039894 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1247 19:26:33.043237 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1248 19:26:33.049766 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1249 19:26:33.052974 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1250 19:26:33.056276 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1251 19:26:33.056371 ==
1252 19:26:33.059751 Dram Type= 6, Freq= 0, CH_0, rank 1
1253 19:26:33.062864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1254 19:26:33.062957 ==
1255 19:26:33.066165 DQS Delay:
1256 19:26:33.066252 DQS0 = 0, DQS1 = 0
1257 19:26:33.069648 DQM Delay:
1258 19:26:33.069763 DQM0 = 94, DQM1 = 85
1259 19:26:33.069842 DQ Delay:
1260 19:26:33.072896 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
1261 19:26:33.076282 DQ4 =93, DQ5 =93, DQ6 =93, DQ7 =101
1262 19:26:33.080119 DQ8 =77, DQ9 =69, DQ10 =85, DQ11 =77
1263 19:26:33.082947 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1264 19:26:33.083043
1265 19:26:33.083130
1266 19:26:33.086393 ==
1267 19:26:33.089666 Dram Type= 6, Freq= 0, CH_0, rank 1
1268 19:26:33.093021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1269 19:26:33.093137 ==
1270 19:26:33.093226
1271 19:26:33.093321
1272 19:26:33.096173 TX Vref Scan disable
1273 19:26:33.096287 == TX Byte 0 ==
1274 19:26:33.099543 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1275 19:26:33.106615 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1276 19:26:33.106740 == TX Byte 1 ==
1277 19:26:33.113207 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1278 19:26:33.116493 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1279 19:26:33.116589 ==
1280 19:26:33.119877 Dram Type= 6, Freq= 0, CH_0, rank 1
1281 19:26:33.123051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1282 19:26:33.123140 ==
1283 19:26:33.136572 TX Vref=22, minBit 0, minWin=28, winSum=449
1284 19:26:33.139697 TX Vref=24, minBit 1, minWin=28, winSum=456
1285 19:26:33.143078 TX Vref=26, minBit 1, minWin=28, winSum=455
1286 19:26:33.146572 TX Vref=28, minBit 4, minWin=28, winSum=457
1287 19:26:33.150028 TX Vref=30, minBit 4, minWin=28, winSum=458
1288 19:26:33.153056 TX Vref=32, minBit 1, minWin=28, winSum=452
1289 19:26:33.159828 [TxChooseVref] Worse bit 4, Min win 28, Win sum 458, Final Vref 30
1290 19:26:33.159953
1291 19:26:33.162982 Final TX Range 1 Vref 30
1292 19:26:33.163072
1293 19:26:33.163182 ==
1294 19:26:33.166182 Dram Type= 6, Freq= 0, CH_0, rank 1
1295 19:26:33.169978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1296 19:26:33.170077 ==
1297 19:26:33.170144
1298 19:26:33.172990
1299 19:26:33.173073 TX Vref Scan disable
1300 19:26:33.176529 == TX Byte 0 ==
1301 19:26:33.179915 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1302 19:26:33.183217 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1303 19:26:33.186448 == TX Byte 1 ==
1304 19:26:33.189865 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1305 19:26:33.193349 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1306 19:26:33.196773
1307 19:26:33.196869 [DATLAT]
1308 19:26:33.196935 Freq=800, CH0 RK1
1309 19:26:33.196995
1310 19:26:33.199870 DATLAT Default: 0xa
1311 19:26:33.199992 0, 0xFFFF, sum = 0
1312 19:26:33.203000 1, 0xFFFF, sum = 0
1313 19:26:33.203085 2, 0xFFFF, sum = 0
1314 19:26:33.207022 3, 0xFFFF, sum = 0
1315 19:26:33.207107 4, 0xFFFF, sum = 0
1316 19:26:33.210102 5, 0xFFFF, sum = 0
1317 19:26:33.210186 6, 0xFFFF, sum = 0
1318 19:26:33.213251 7, 0xFFFF, sum = 0
1319 19:26:33.213335 8, 0xFFFF, sum = 0
1320 19:26:33.216602 9, 0x0, sum = 1
1321 19:26:33.216691 10, 0x0, sum = 2
1322 19:26:33.219914 11, 0x0, sum = 3
1323 19:26:33.219998 12, 0x0, sum = 4
1324 19:26:33.223398 best_step = 10
1325 19:26:33.223482
1326 19:26:33.223547 ==
1327 19:26:33.226749 Dram Type= 6, Freq= 0, CH_0, rank 1
1328 19:26:33.229839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1329 19:26:33.229924 ==
1330 19:26:33.233179 RX Vref Scan: 0
1331 19:26:33.233265
1332 19:26:33.233337 RX Vref 0 -> 0, step: 1
1333 19:26:33.233399
1334 19:26:33.236473 RX Delay -95 -> 252, step: 8
1335 19:26:33.243053 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1336 19:26:33.247023 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1337 19:26:33.250275 iDelay=209, Bit 2, Center 92 (-15 ~ 200) 216
1338 19:26:33.254084 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1339 19:26:33.257913 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1340 19:26:33.261205 iDelay=209, Bit 5, Center 88 (-23 ~ 200) 224
1341 19:26:33.265036 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1342 19:26:33.268219 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1343 19:26:33.272101 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1344 19:26:33.275762 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
1345 19:26:33.283406 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1346 19:26:33.286519 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1347 19:26:33.290188 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1348 19:26:33.293515 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
1349 19:26:33.296817 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1350 19:26:33.303815 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1351 19:26:33.303964 ==
1352 19:26:33.306883 Dram Type= 6, Freq= 0, CH_0, rank 1
1353 19:26:33.310183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1354 19:26:33.310297 ==
1355 19:26:33.310434 DQS Delay:
1356 19:26:33.313415 DQS0 = 0, DQS1 = 0
1357 19:26:33.313499 DQM Delay:
1358 19:26:33.316933 DQM0 = 93, DQM1 = 83
1359 19:26:33.317050 DQ Delay:
1360 19:26:33.319826 DQ0 =92, DQ1 =96, DQ2 =92, DQ3 =88
1361 19:26:33.323239 DQ4 =92, DQ5 =88, DQ6 =100, DQ7 =100
1362 19:26:33.327110 DQ8 =76, DQ9 =76, DQ10 =84, DQ11 =76
1363 19:26:33.330283 DQ12 =84, DQ13 =88, DQ14 =92, DQ15 =88
1364 19:26:33.330463
1365 19:26:33.330556
1366 19:26:33.337054 [DQSOSCAuto] RK1, (LSB)MR18= 0x4514, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
1367 19:26:33.340539 CH0 RK1: MR19=606, MR18=4514
1368 19:26:33.346649 CH0_RK1: MR19=0x606, MR18=0x4514, DQSOSC=392, MR23=63, INC=96, DEC=64
1369 19:26:33.350015 [RxdqsGatingPostProcess] freq 800
1370 19:26:33.353488 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1371 19:26:33.356702 Pre-setting of DQS Precalculation
1372 19:26:33.363824 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1373 19:26:33.363939 ==
1374 19:26:33.367194 Dram Type= 6, Freq= 0, CH_1, rank 0
1375 19:26:33.370703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1376 19:26:33.370811 ==
1377 19:26:33.377065 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1378 19:26:33.383602 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1379 19:26:33.391675 [CA 0] Center 36 (6~67) winsize 62
1380 19:26:33.394752 [CA 1] Center 36 (6~67) winsize 62
1381 19:26:33.397849 [CA 2] Center 34 (4~65) winsize 62
1382 19:26:33.401679 [CA 3] Center 34 (4~65) winsize 62
1383 19:26:33.404905 [CA 4] Center 34 (4~65) winsize 62
1384 19:26:33.407984 [CA 5] Center 34 (4~64) winsize 61
1385 19:26:33.408077
1386 19:26:33.411598 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1387 19:26:33.411688
1388 19:26:33.414878 [CATrainingPosCal] consider 1 rank data
1389 19:26:33.417854 u2DelayCellTimex100 = 270/100 ps
1390 19:26:33.421464 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1391 19:26:33.424443 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1392 19:26:33.431515 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1393 19:26:33.434693 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1394 19:26:33.437790 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1395 19:26:33.441468 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1396 19:26:33.441564
1397 19:26:33.444483 CA PerBit enable=1, Macro0, CA PI delay=34
1398 19:26:33.444573
1399 19:26:33.448013 [CBTSetCACLKResult] CA Dly = 34
1400 19:26:33.448131 CS Dly: 6 (0~37)
1401 19:26:33.448245 ==
1402 19:26:33.451583 Dram Type= 6, Freq= 0, CH_1, rank 1
1403 19:26:33.458176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1404 19:26:33.458319 ==
1405 19:26:33.461350 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1406 19:26:33.467889 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1407 19:26:33.477904 [CA 0] Center 36 (6~67) winsize 62
1408 19:26:33.481190 [CA 1] Center 37 (6~68) winsize 63
1409 19:26:33.484233 [CA 2] Center 35 (4~66) winsize 63
1410 19:26:33.487456 [CA 3] Center 34 (4~65) winsize 62
1411 19:26:33.490735 [CA 4] Center 35 (5~65) winsize 61
1412 19:26:33.494054 [CA 5] Center 34 (4~65) winsize 62
1413 19:26:33.494171
1414 19:26:33.497717 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1415 19:26:33.497812
1416 19:26:33.500739 [CATrainingPosCal] consider 2 rank data
1417 19:26:33.504446 u2DelayCellTimex100 = 270/100 ps
1418 19:26:33.507508 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1419 19:26:33.510802 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1420 19:26:33.517470 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1421 19:26:33.521205 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1422 19:26:33.524445 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1423 19:26:33.527596 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1424 19:26:33.527687
1425 19:26:33.531416 CA PerBit enable=1, Macro0, CA PI delay=34
1426 19:26:33.531505
1427 19:26:33.534460 [CBTSetCACLKResult] CA Dly = 34
1428 19:26:33.534544 CS Dly: 6 (0~38)
1429 19:26:33.534610
1430 19:26:33.537819 ----->DramcWriteLeveling(PI) begin...
1431 19:26:33.541139 ==
1432 19:26:33.541289 Dram Type= 6, Freq= 0, CH_1, rank 0
1433 19:26:33.547824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1434 19:26:33.547918 ==
1435 19:26:33.550963 Write leveling (Byte 0): 27 => 27
1436 19:26:33.554646 Write leveling (Byte 1): 28 => 28
1437 19:26:33.554733 DramcWriteLeveling(PI) end<-----
1438 19:26:33.558152
1439 19:26:33.558237 ==
1440 19:26:33.561408 Dram Type= 6, Freq= 0, CH_1, rank 0
1441 19:26:33.564411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1442 19:26:33.564500 ==
1443 19:26:33.567540 [Gating] SW mode calibration
1444 19:26:33.574387 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1445 19:26:33.577734 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1446 19:26:33.584287 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1447 19:26:33.587559 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1448 19:26:33.591142 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 19:26:33.598058 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 19:26:33.601400 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 19:26:33.604782 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 19:26:33.611111 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 19:26:33.614665 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 19:26:33.617923 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 19:26:33.624374 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 19:26:33.627667 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 19:26:33.630930 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 19:26:33.637875 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 19:26:33.641129 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 19:26:33.644367 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 19:26:33.647714 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 19:26:33.654627 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1463 19:26:33.657831 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1464 19:26:33.661279 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1465 19:26:33.667862 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 19:26:33.671311 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 19:26:33.674696 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 19:26:33.681099 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 19:26:33.684247 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 19:26:33.687735 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 19:26:33.694473 0 9 4 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
1472 19:26:33.697687 0 9 8 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
1473 19:26:33.701337 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1474 19:26:33.707678 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1475 19:26:33.710782 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 19:26:33.714474 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 19:26:33.721020 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 19:26:33.724065 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 19:26:33.727696 0 10 4 | B1->B0 | 3131 2b2b | 0 0 | (0 1) (1 1)
1480 19:26:33.734051 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1481 19:26:33.737422 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 19:26:33.741353 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 19:26:33.747612 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 19:26:33.750788 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 19:26:33.754205 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 19:26:33.757494 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 19:26:33.764168 0 11 4 | B1->B0 | 2727 3939 | 1 1 | (0 0) (0 0)
1488 19:26:33.767516 0 11 8 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
1489 19:26:33.770866 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1490 19:26:33.777444 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1491 19:26:33.781366 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 19:26:33.784766 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 19:26:33.791437 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 19:26:33.794741 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 19:26:33.797855 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1496 19:26:33.804510 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1497 19:26:33.807836 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 19:26:33.811158 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 19:26:33.817723 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 19:26:33.820988 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 19:26:33.824672 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 19:26:33.828019 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 19:26:33.834918 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 19:26:33.838595 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 19:26:33.842016 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 19:26:33.848234 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 19:26:33.851709 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 19:26:33.854992 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 19:26:33.861630 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 19:26:33.864855 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 19:26:33.868367 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1512 19:26:33.874526 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1513 19:26:33.874692 Total UI for P1: 0, mck2ui 16
1514 19:26:33.881584 best dqsien dly found for B0: ( 0, 14, 4)
1515 19:26:33.881729 Total UI for P1: 0, mck2ui 16
1516 19:26:33.884924 best dqsien dly found for B1: ( 0, 14, 4)
1517 19:26:33.891671 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1518 19:26:33.894575 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1519 19:26:33.894675
1520 19:26:33.897829 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1521 19:26:33.901180 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1522 19:26:33.904524 [Gating] SW calibration Done
1523 19:26:33.904647 ==
1524 19:26:33.908276 Dram Type= 6, Freq= 0, CH_1, rank 0
1525 19:26:33.911664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1526 19:26:33.911801 ==
1527 19:26:33.911902 RX Vref Scan: 0
1528 19:26:33.914884
1529 19:26:33.915039 RX Vref 0 -> 0, step: 1
1530 19:26:33.915129
1531 19:26:33.918231 RX Delay -130 -> 252, step: 16
1532 19:26:33.921599 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1533 19:26:33.924981 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1534 19:26:33.931590 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1535 19:26:33.934751 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1536 19:26:33.938045 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1537 19:26:33.941264 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1538 19:26:33.944887 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1539 19:26:33.951589 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1540 19:26:33.955021 iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208
1541 19:26:33.958276 iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208
1542 19:26:33.961626 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1543 19:26:33.964842 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1544 19:26:33.971331 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1545 19:26:33.974936 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1546 19:26:33.978224 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1547 19:26:33.981167 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1548 19:26:33.981304 ==
1549 19:26:33.984694 Dram Type= 6, Freq= 0, CH_1, rank 0
1550 19:26:33.991289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1551 19:26:33.991443 ==
1552 19:26:33.991557 DQS Delay:
1553 19:26:33.991681 DQS0 = 0, DQS1 = 0
1554 19:26:33.994631 DQM Delay:
1555 19:26:33.994741 DQM0 = 93, DQM1 = 89
1556 19:26:33.997904 DQ Delay:
1557 19:26:34.001917 DQ0 =93, DQ1 =85, DQ2 =85, DQ3 =93
1558 19:26:34.004753 DQ4 =93, DQ5 =109, DQ6 =93, DQ7 =93
1559 19:26:34.007937 DQ8 =85, DQ9 =85, DQ10 =85, DQ11 =85
1560 19:26:34.011699 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1561 19:26:34.011841
1562 19:26:34.011947
1563 19:26:34.012041 ==
1564 19:26:34.015124 Dram Type= 6, Freq= 0, CH_1, rank 0
1565 19:26:34.018365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1566 19:26:34.018465 ==
1567 19:26:34.018533
1568 19:26:34.018594
1569 19:26:34.021711 TX Vref Scan disable
1570 19:26:34.021789 == TX Byte 0 ==
1571 19:26:34.028051 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1572 19:26:34.031321 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1573 19:26:34.031431 == TX Byte 1 ==
1574 19:26:34.037816 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1575 19:26:34.041318 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1576 19:26:34.041464 ==
1577 19:26:34.044546 Dram Type= 6, Freq= 0, CH_1, rank 0
1578 19:26:34.048039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1579 19:26:34.048152 ==
1580 19:26:34.061888 TX Vref=22, minBit 0, minWin=26, winSum=439
1581 19:26:34.065174 TX Vref=24, minBit 1, minWin=26, winSum=444
1582 19:26:34.068567 TX Vref=26, minBit 0, minWin=27, winSum=443
1583 19:26:34.072105 TX Vref=28, minBit 1, minWin=27, winSum=451
1584 19:26:34.075401 TX Vref=30, minBit 1, minWin=27, winSum=449
1585 19:26:34.078185 TX Vref=32, minBit 1, minWin=27, winSum=449
1586 19:26:34.085389 [TxChooseVref] Worse bit 1, Min win 27, Win sum 451, Final Vref 28
1587 19:26:34.085546
1588 19:26:34.088797 Final TX Range 1 Vref 28
1589 19:26:34.088892
1590 19:26:34.088972 ==
1591 19:26:34.092150 Dram Type= 6, Freq= 0, CH_1, rank 0
1592 19:26:34.095219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1593 19:26:34.095324 ==
1594 19:26:34.095392
1595 19:26:34.098469
1596 19:26:34.098567 TX Vref Scan disable
1597 19:26:34.102022 == TX Byte 0 ==
1598 19:26:34.105273 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1599 19:26:34.108642 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1600 19:26:34.112274 == TX Byte 1 ==
1601 19:26:34.115118 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1602 19:26:34.118481 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1603 19:26:34.118586
1604 19:26:34.121616 [DATLAT]
1605 19:26:34.121734 Freq=800, CH1 RK0
1606 19:26:34.121829
1607 19:26:34.125146 DATLAT Default: 0xa
1608 19:26:34.125264 0, 0xFFFF, sum = 0
1609 19:26:34.128477 1, 0xFFFF, sum = 0
1610 19:26:34.128603 2, 0xFFFF, sum = 0
1611 19:26:34.132271 3, 0xFFFF, sum = 0
1612 19:26:34.132386 4, 0xFFFF, sum = 0
1613 19:26:34.135302 5, 0xFFFF, sum = 0
1614 19:26:34.135402 6, 0xFFFF, sum = 0
1615 19:26:34.138457 7, 0xFFFF, sum = 0
1616 19:26:34.138553 8, 0xFFFF, sum = 0
1617 19:26:34.141726 9, 0x0, sum = 1
1618 19:26:34.141825 10, 0x0, sum = 2
1619 19:26:34.145695 11, 0x0, sum = 3
1620 19:26:34.145799 12, 0x0, sum = 4
1621 19:26:34.148571 best_step = 10
1622 19:26:34.148663
1623 19:26:34.148729 ==
1624 19:26:34.151883 Dram Type= 6, Freq= 0, CH_1, rank 0
1625 19:26:34.155237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1626 19:26:34.155341 ==
1627 19:26:34.158590 RX Vref Scan: 1
1628 19:26:34.158715
1629 19:26:34.158821 Set Vref Range= 32 -> 127
1630 19:26:34.158917
1631 19:26:34.162014 RX Vref 32 -> 127, step: 1
1632 19:26:34.162136
1633 19:26:34.165368 RX Delay -63 -> 252, step: 8
1634 19:26:34.165456
1635 19:26:34.168530 Set Vref, RX VrefLevel [Byte0]: 32
1636 19:26:34.171571 [Byte1]: 32
1637 19:26:34.171666
1638 19:26:34.175154 Set Vref, RX VrefLevel [Byte0]: 33
1639 19:26:34.178323 [Byte1]: 33
1640 19:26:34.181880
1641 19:26:34.181984 Set Vref, RX VrefLevel [Byte0]: 34
1642 19:26:34.185026 [Byte1]: 34
1643 19:26:34.189076
1644 19:26:34.189189 Set Vref, RX VrefLevel [Byte0]: 35
1645 19:26:34.192550 [Byte1]: 35
1646 19:26:34.197060
1647 19:26:34.197214 Set Vref, RX VrefLevel [Byte0]: 36
1648 19:26:34.200369 [Byte1]: 36
1649 19:26:34.204280
1650 19:26:34.204432 Set Vref, RX VrefLevel [Byte0]: 37
1651 19:26:34.207425 [Byte1]: 37
1652 19:26:34.212139
1653 19:26:34.212273 Set Vref, RX VrefLevel [Byte0]: 38
1654 19:26:34.215270 [Byte1]: 38
1655 19:26:34.219270
1656 19:26:34.219373 Set Vref, RX VrefLevel [Byte0]: 39
1657 19:26:34.223103 [Byte1]: 39
1658 19:26:34.226943
1659 19:26:34.227046 Set Vref, RX VrefLevel [Byte0]: 40
1660 19:26:34.230262 [Byte1]: 40
1661 19:26:34.234036
1662 19:26:34.234128 Set Vref, RX VrefLevel [Byte0]: 41
1663 19:26:34.237704 [Byte1]: 41
1664 19:26:34.241650
1665 19:26:34.241738 Set Vref, RX VrefLevel [Byte0]: 42
1666 19:26:34.245079 [Byte1]: 42
1667 19:26:34.249206
1668 19:26:34.249290 Set Vref, RX VrefLevel [Byte0]: 43
1669 19:26:34.252259 [Byte1]: 43
1670 19:26:34.256513
1671 19:26:34.256644 Set Vref, RX VrefLevel [Byte0]: 44
1672 19:26:34.259796 [Byte1]: 44
1673 19:26:34.264198
1674 19:26:34.264341 Set Vref, RX VrefLevel [Byte0]: 45
1675 19:26:34.267694 [Byte1]: 45
1676 19:26:34.271801
1677 19:26:34.271897 Set Vref, RX VrefLevel [Byte0]: 46
1678 19:26:34.275025 [Byte1]: 46
1679 19:26:34.279092
1680 19:26:34.279198 Set Vref, RX VrefLevel [Byte0]: 47
1681 19:26:34.282917 [Byte1]: 47
1682 19:26:34.287072
1683 19:26:34.287196 Set Vref, RX VrefLevel [Byte0]: 48
1684 19:26:34.290264 [Byte1]: 48
1685 19:26:34.294718
1686 19:26:34.294860 Set Vref, RX VrefLevel [Byte0]: 49
1687 19:26:34.297521 [Byte1]: 49
1688 19:26:34.301976
1689 19:26:34.302119 Set Vref, RX VrefLevel [Byte0]: 50
1690 19:26:34.305279 [Byte1]: 50
1691 19:26:34.309119
1692 19:26:34.309258 Set Vref, RX VrefLevel [Byte0]: 51
1693 19:26:34.312543 [Byte1]: 51
1694 19:26:34.316470
1695 19:26:34.316590 Set Vref, RX VrefLevel [Byte0]: 52
1696 19:26:34.320396 [Byte1]: 52
1697 19:26:34.324484
1698 19:26:34.324579 Set Vref, RX VrefLevel [Byte0]: 53
1699 19:26:34.327790 [Byte1]: 53
1700 19:26:34.331747
1701 19:26:34.331864 Set Vref, RX VrefLevel [Byte0]: 54
1702 19:26:34.335137 [Byte1]: 54
1703 19:26:34.339159
1704 19:26:34.339268 Set Vref, RX VrefLevel [Byte0]: 55
1705 19:26:34.342485 [Byte1]: 55
1706 19:26:34.347079
1707 19:26:34.347216 Set Vref, RX VrefLevel [Byte0]: 56
1708 19:26:34.350466 [Byte1]: 56
1709 19:26:34.354539
1710 19:26:34.354654 Set Vref, RX VrefLevel [Byte0]: 57
1711 19:26:34.358062 [Byte1]: 57
1712 19:26:34.361906
1713 19:26:34.362020 Set Vref, RX VrefLevel [Byte0]: 58
1714 19:26:34.364945 [Byte1]: 58
1715 19:26:34.369382
1716 19:26:34.369483 Set Vref, RX VrefLevel [Byte0]: 59
1717 19:26:34.372359 [Byte1]: 59
1718 19:26:34.376605
1719 19:26:34.376718 Set Vref, RX VrefLevel [Byte0]: 60
1720 19:26:34.380149 [Byte1]: 60
1721 19:26:34.384027
1722 19:26:34.384168 Set Vref, RX VrefLevel [Byte0]: 61
1723 19:26:34.387490 [Byte1]: 61
1724 19:26:34.392114
1725 19:26:34.392249 Set Vref, RX VrefLevel [Byte0]: 62
1726 19:26:34.395287 [Byte1]: 62
1727 19:26:34.399469
1728 19:26:34.399610 Set Vref, RX VrefLevel [Byte0]: 63
1729 19:26:34.402797 [Byte1]: 63
1730 19:26:34.406775
1731 19:26:34.406905 Set Vref, RX VrefLevel [Byte0]: 64
1732 19:26:34.410008 [Byte1]: 64
1733 19:26:34.413982
1734 19:26:34.414137 Set Vref, RX VrefLevel [Byte0]: 65
1735 19:26:34.417758 [Byte1]: 65
1736 19:26:34.421776
1737 19:26:34.421909 Set Vref, RX VrefLevel [Byte0]: 66
1738 19:26:34.424969 [Byte1]: 66
1739 19:26:34.429136
1740 19:26:34.429233 Set Vref, RX VrefLevel [Byte0]: 67
1741 19:26:34.432346 [Byte1]: 67
1742 19:26:34.436906
1743 19:26:34.437036 Set Vref, RX VrefLevel [Byte0]: 68
1744 19:26:34.440196 [Byte1]: 68
1745 19:26:34.444239
1746 19:26:34.444373 Set Vref, RX VrefLevel [Byte0]: 69
1747 19:26:34.447481 [Byte1]: 69
1748 19:26:34.451620
1749 19:26:34.451729 Set Vref, RX VrefLevel [Byte0]: 70
1750 19:26:34.454986 [Byte1]: 70
1751 19:26:34.458865
1752 19:26:34.458953 Set Vref, RX VrefLevel [Byte0]: 71
1753 19:26:34.462372 [Byte1]: 71
1754 19:26:34.466896
1755 19:26:34.467058 Set Vref, RX VrefLevel [Byte0]: 72
1756 19:26:34.470241 [Byte1]: 72
1757 19:26:34.474254
1758 19:26:34.474398 Final RX Vref Byte 0 = 58 to rank0
1759 19:26:34.477576 Final RX Vref Byte 1 = 53 to rank0
1760 19:26:34.480860 Final RX Vref Byte 0 = 58 to rank1
1761 19:26:34.484072 Final RX Vref Byte 1 = 53 to rank1==
1762 19:26:34.487380 Dram Type= 6, Freq= 0, CH_1, rank 0
1763 19:26:34.493986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1764 19:26:34.494125 ==
1765 19:26:34.494230 DQS Delay:
1766 19:26:34.494333 DQS0 = 0, DQS1 = 0
1767 19:26:34.497635 DQM Delay:
1768 19:26:34.497762 DQM0 = 95, DQM1 = 89
1769 19:26:34.501052 DQ Delay:
1770 19:26:34.504745 DQ0 =100, DQ1 =88, DQ2 =84, DQ3 =92
1771 19:26:34.507957 DQ4 =92, DQ5 =108, DQ6 =108, DQ7 =92
1772 19:26:34.511423 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1773 19:26:34.514531 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1774 19:26:34.514672
1775 19:26:34.514744
1776 19:26:34.521175 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e4a, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1777 19:26:34.524016 CH1 RK0: MR19=606, MR18=2E4A
1778 19:26:34.530819 CH1_RK0: MR19=0x606, MR18=0x2E4A, DQSOSC=391, MR23=63, INC=96, DEC=64
1779 19:26:34.530935
1780 19:26:34.534402 ----->DramcWriteLeveling(PI) begin...
1781 19:26:34.534483 ==
1782 19:26:34.537487 Dram Type= 6, Freq= 0, CH_1, rank 1
1783 19:26:34.541183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1784 19:26:34.541318 ==
1785 19:26:34.544369 Write leveling (Byte 0): 26 => 26
1786 19:26:34.547975 Write leveling (Byte 1): 27 => 27
1787 19:26:34.551270 DramcWriteLeveling(PI) end<-----
1788 19:26:34.551400
1789 19:26:34.551493 ==
1790 19:26:34.554701 Dram Type= 6, Freq= 0, CH_1, rank 1
1791 19:26:34.557973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1792 19:26:34.558063 ==
1793 19:26:34.561376 [Gating] SW mode calibration
1794 19:26:34.568183 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1795 19:26:34.574497 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1796 19:26:34.577858 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1797 19:26:34.581163 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1798 19:26:34.587759 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1799 19:26:34.591134 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1800 19:26:34.594451 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1801 19:26:34.601272 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1802 19:26:34.604494 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1803 19:26:34.607831 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1804 19:26:34.614788 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 19:26:34.617993 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 19:26:34.621417 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 19:26:34.624742 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 19:26:34.631193 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 19:26:34.634599 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 19:26:34.638121 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 19:26:34.644392 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 19:26:34.647970 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1813 19:26:34.651350 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1814 19:26:34.658080 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 19:26:34.661335 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 19:26:34.664349 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 19:26:34.671313 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 19:26:34.674727 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 19:26:34.678330 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 19:26:34.684920 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 19:26:34.688168 0 9 4 | B1->B0 | 2b2b 2323 | 1 0 | (1 1) (0 0)
1822 19:26:34.691542 0 9 8 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
1823 19:26:34.694812 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1824 19:26:34.701478 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1825 19:26:34.704716 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1826 19:26:34.708044 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1827 19:26:34.714751 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1828 19:26:34.717953 0 10 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1829 19:26:34.721431 0 10 4 | B1->B0 | 2626 3030 | 0 1 | (0 0) (1 0)
1830 19:26:34.728021 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1831 19:26:34.731035 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 19:26:34.734888 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 19:26:34.741388 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 19:26:34.744498 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 19:26:34.748113 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 19:26:34.754715 0 11 0 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1837 19:26:34.758086 0 11 4 | B1->B0 | 3c3c 3030 | 0 0 | (0 0) (0 0)
1838 19:26:34.761527 0 11 8 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
1839 19:26:34.767862 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1840 19:26:34.771128 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1841 19:26:34.774563 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1842 19:26:34.781179 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1843 19:26:34.785028 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1844 19:26:34.787985 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1845 19:26:34.794657 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1846 19:26:34.797900 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1847 19:26:34.801108 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1848 19:26:34.805052 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1849 19:26:34.811217 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1850 19:26:34.814476 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1851 19:26:34.817926 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1852 19:26:34.824594 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1853 19:26:34.827998 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 19:26:34.831345 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 19:26:34.837944 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 19:26:34.842010 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 19:26:34.844656 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 19:26:34.851324 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 19:26:34.854722 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 19:26:34.858172 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1861 19:26:34.864724 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1862 19:26:34.867976 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1863 19:26:34.871349 Total UI for P1: 0, mck2ui 16
1864 19:26:34.874773 best dqsien dly found for B0: ( 0, 14, 4)
1865 19:26:34.877917 Total UI for P1: 0, mck2ui 16
1866 19:26:34.881210 best dqsien dly found for B1: ( 0, 14, 2)
1867 19:26:34.884560 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1868 19:26:34.888503 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1869 19:26:34.888630
1870 19:26:34.891817 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1871 19:26:34.894985 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1872 19:26:34.898155 [Gating] SW calibration Done
1873 19:26:34.898277 ==
1874 19:26:34.901258 Dram Type= 6, Freq= 0, CH_1, rank 1
1875 19:26:34.904963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1876 19:26:34.905087 ==
1877 19:26:34.907886 RX Vref Scan: 0
1878 19:26:34.907990
1879 19:26:34.908093 RX Vref 0 -> 0, step: 1
1880 19:26:34.911760
1881 19:26:34.911880 RX Delay -130 -> 252, step: 16
1882 19:26:34.918323 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1883 19:26:34.921780 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1884 19:26:34.924848 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1885 19:26:34.928246 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1886 19:26:34.931578 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1887 19:26:34.934928 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1888 19:26:34.941687 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1889 19:26:34.944897 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1890 19:26:34.948240 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1891 19:26:34.951630 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1892 19:26:34.954949 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1893 19:26:34.961515 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1894 19:26:34.964630 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1895 19:26:34.967960 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1896 19:26:34.971258 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1897 19:26:34.978289 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1898 19:26:34.978407 ==
1899 19:26:34.981694 Dram Type= 6, Freq= 0, CH_1, rank 1
1900 19:26:34.984854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1901 19:26:34.984945 ==
1902 19:26:34.985033 DQS Delay:
1903 19:26:34.988091 DQS0 = 0, DQS1 = 0
1904 19:26:34.988222 DQM Delay:
1905 19:26:34.991602 DQM0 = 92, DQM1 = 89
1906 19:26:34.991748 DQ Delay:
1907 19:26:34.994839 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =85
1908 19:26:34.998199 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1909 19:26:35.001246 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =77
1910 19:26:35.004740 DQ12 =93, DQ13 =101, DQ14 =93, DQ15 =101
1911 19:26:35.004860
1912 19:26:35.004947
1913 19:26:35.005040 ==
1914 19:26:35.008499 Dram Type= 6, Freq= 0, CH_1, rank 1
1915 19:26:35.011431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1916 19:26:35.011520 ==
1917 19:26:35.011588
1918 19:26:35.015042
1919 19:26:35.015146 TX Vref Scan disable
1920 19:26:35.018637 == TX Byte 0 ==
1921 19:26:35.021750 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1922 19:26:35.024886 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1923 19:26:35.028317 == TX Byte 1 ==
1924 19:26:35.031348 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1925 19:26:35.034956 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1926 19:26:35.035052 ==
1927 19:26:35.038227 Dram Type= 6, Freq= 0, CH_1, rank 1
1928 19:26:35.044890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1929 19:26:35.045014 ==
1930 19:26:35.056868 TX Vref=22, minBit 1, minWin=26, winSum=441
1931 19:26:35.060148 TX Vref=24, minBit 1, minWin=26, winSum=444
1932 19:26:35.063515 TX Vref=26, minBit 0, minWin=27, winSum=445
1933 19:26:35.066866 TX Vref=28, minBit 0, minWin=27, winSum=450
1934 19:26:35.070095 TX Vref=30, minBit 2, minWin=27, winSum=448
1935 19:26:35.073471 TX Vref=32, minBit 2, minWin=27, winSum=447
1936 19:26:35.080267 [TxChooseVref] Worse bit 0, Min win 27, Win sum 450, Final Vref 28
1937 19:26:35.080369
1938 19:26:35.083495 Final TX Range 1 Vref 28
1939 19:26:35.083589
1940 19:26:35.083676 ==
1941 19:26:35.086814 Dram Type= 6, Freq= 0, CH_1, rank 1
1942 19:26:35.090179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1943 19:26:35.090288 ==
1944 19:26:35.090391
1945 19:26:35.090473
1946 19:26:35.093609 TX Vref Scan disable
1947 19:26:35.096782 == TX Byte 0 ==
1948 19:26:35.100101 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1949 19:26:35.103307 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1950 19:26:35.106514 == TX Byte 1 ==
1951 19:26:35.110214 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1952 19:26:35.113194 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1953 19:26:35.113287
1954 19:26:35.117204 [DATLAT]
1955 19:26:35.117291 Freq=800, CH1 RK1
1956 19:26:35.117379
1957 19:26:35.119975 DATLAT Default: 0xa
1958 19:26:35.120058 0, 0xFFFF, sum = 0
1959 19:26:35.123710 1, 0xFFFF, sum = 0
1960 19:26:35.123798 2, 0xFFFF, sum = 0
1961 19:26:35.126800 3, 0xFFFF, sum = 0
1962 19:26:35.126888 4, 0xFFFF, sum = 0
1963 19:26:35.129670 5, 0xFFFF, sum = 0
1964 19:26:35.129775 6, 0xFFFF, sum = 0
1965 19:26:35.133053 7, 0xFFFF, sum = 0
1966 19:26:35.136464 8, 0xFFFF, sum = 0
1967 19:26:35.136545 9, 0x0, sum = 1
1968 19:26:35.136608 10, 0x0, sum = 2
1969 19:26:35.140124 11, 0x0, sum = 3
1970 19:26:35.140293 12, 0x0, sum = 4
1971 19:26:35.143499 best_step = 10
1972 19:26:35.143580
1973 19:26:35.143663 ==
1974 19:26:35.146753 Dram Type= 6, Freq= 0, CH_1, rank 1
1975 19:26:35.150248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1976 19:26:35.150379 ==
1977 19:26:35.153668 RX Vref Scan: 0
1978 19:26:35.153747
1979 19:26:35.153826 RX Vref 0 -> 0, step: 1
1980 19:26:35.153900
1981 19:26:35.156397 RX Delay -79 -> 252, step: 8
1982 19:26:35.163483 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
1983 19:26:35.166688 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
1984 19:26:35.169984 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
1985 19:26:35.173187 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
1986 19:26:35.176447 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
1987 19:26:35.179797 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
1988 19:26:35.186580 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
1989 19:26:35.189864 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
1990 19:26:35.193171 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
1991 19:26:35.196506 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
1992 19:26:35.199669 iDelay=209, Bit 10, Center 88 (-15 ~ 192) 208
1993 19:26:35.206840 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
1994 19:26:35.210100 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
1995 19:26:35.213372 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
1996 19:26:35.216731 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
1997 19:26:35.219914 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
1998 19:26:35.223361 ==
1999 19:26:35.223489 Dram Type= 6, Freq= 0, CH_1, rank 1
2000 19:26:35.229924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2001 19:26:35.230021 ==
2002 19:26:35.230088 DQS Delay:
2003 19:26:35.233408 DQS0 = 0, DQS1 = 0
2004 19:26:35.233507 DQM Delay:
2005 19:26:35.233573 DQM0 = 97, DQM1 = 90
2006 19:26:35.236651 DQ Delay:
2007 19:26:35.240177 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2008 19:26:35.243235 DQ4 =92, DQ5 =108, DQ6 =108, DQ7 =96
2009 19:26:35.246732 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =88
2010 19:26:35.250093 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2011 19:26:35.250228
2012 19:26:35.250344
2013 19:26:35.256609 [DQSOSCAuto] RK1, (LSB)MR18= 0x4d17, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 390 ps
2014 19:26:35.259877 CH1 RK1: MR19=606, MR18=4D17
2015 19:26:35.266607 CH1_RK1: MR19=0x606, MR18=0x4D17, DQSOSC=390, MR23=63, INC=97, DEC=64
2016 19:26:35.269632 [RxdqsGatingPostProcess] freq 800
2017 19:26:35.273359 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2018 19:26:35.276676 Pre-setting of DQS Precalculation
2019 19:26:35.283468 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2020 19:26:35.289756 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2021 19:26:35.296539 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2022 19:26:35.296714
2023 19:26:35.296818
2024 19:26:35.299744 [Calibration Summary] 1600 Mbps
2025 19:26:35.299857 CH 0, Rank 0
2026 19:26:35.303094 SW Impedance : PASS
2027 19:26:35.307042 DUTY Scan : NO K
2028 19:26:35.307143 ZQ Calibration : PASS
2029 19:26:35.310187 Jitter Meter : NO K
2030 19:26:35.313491 CBT Training : PASS
2031 19:26:35.313585 Write leveling : PASS
2032 19:26:35.316626 RX DQS gating : PASS
2033 19:26:35.319988 RX DQ/DQS(RDDQC) : PASS
2034 19:26:35.320080 TX DQ/DQS : PASS
2035 19:26:35.323276 RX DATLAT : PASS
2036 19:26:35.326658 RX DQ/DQS(Engine): PASS
2037 19:26:35.326750 TX OE : NO K
2038 19:26:35.330013 All Pass.
2039 19:26:35.330101
2040 19:26:35.330203 CH 0, Rank 1
2041 19:26:35.333487 SW Impedance : PASS
2042 19:26:35.333592 DUTY Scan : NO K
2043 19:26:35.336584 ZQ Calibration : PASS
2044 19:26:35.336673 Jitter Meter : NO K
2045 19:26:35.339968 CBT Training : PASS
2046 19:26:35.343129 Write leveling : PASS
2047 19:26:35.343224 RX DQS gating : PASS
2048 19:26:35.346436 RX DQ/DQS(RDDQC) : PASS
2049 19:26:35.350245 TX DQ/DQS : PASS
2050 19:26:35.350349 RX DATLAT : PASS
2051 19:26:35.353586 RX DQ/DQS(Engine): PASS
2052 19:26:35.356872 TX OE : NO K
2053 19:26:35.356964 All Pass.
2054 19:26:35.357052
2055 19:26:35.357134 CH 1, Rank 0
2056 19:26:35.360081 SW Impedance : PASS
2057 19:26:35.363240 DUTY Scan : NO K
2058 19:26:35.363344 ZQ Calibration : PASS
2059 19:26:35.366697 Jitter Meter : NO K
2060 19:26:35.369953 CBT Training : PASS
2061 19:26:35.370070 Write leveling : PASS
2062 19:26:35.373913 RX DQS gating : PASS
2063 19:26:35.374021 RX DQ/DQS(RDDQC) : PASS
2064 19:26:35.376978 TX DQ/DQS : PASS
2065 19:26:35.380169 RX DATLAT : PASS
2066 19:26:35.380258 RX DQ/DQS(Engine): PASS
2067 19:26:35.383532 TX OE : NO K
2068 19:26:35.383635 All Pass.
2069 19:26:35.383721
2070 19:26:35.387008 CH 1, Rank 1
2071 19:26:35.387098 SW Impedance : PASS
2072 19:26:35.390271 DUTY Scan : NO K
2073 19:26:35.393405 ZQ Calibration : PASS
2074 19:26:35.393495 Jitter Meter : NO K
2075 19:26:35.396493 CBT Training : PASS
2076 19:26:35.400206 Write leveling : PASS
2077 19:26:35.400313 RX DQS gating : PASS
2078 19:26:35.403229 RX DQ/DQS(RDDQC) : PASS
2079 19:26:35.407087 TX DQ/DQS : PASS
2080 19:26:35.407183 RX DATLAT : PASS
2081 19:26:35.410268 RX DQ/DQS(Engine): PASS
2082 19:26:35.413398 TX OE : NO K
2083 19:26:35.413512 All Pass.
2084 19:26:35.413614
2085 19:26:35.413695 DramC Write-DBI off
2086 19:26:35.417064 PER_BANK_REFRESH: Hybrid Mode
2087 19:26:35.420082 TX_TRACKING: ON
2088 19:26:35.423367 [GetDramInforAfterCalByMRR] Vendor 6.
2089 19:26:35.426572 [GetDramInforAfterCalByMRR] Revision 606.
2090 19:26:35.430041 [GetDramInforAfterCalByMRR] Revision 2 0.
2091 19:26:35.430164 MR0 0x3b3b
2092 19:26:35.433275 MR8 0x5151
2093 19:26:35.436590 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2094 19:26:35.436698
2095 19:26:35.436805 MR0 0x3b3b
2096 19:26:35.436900 MR8 0x5151
2097 19:26:35.439982 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2098 19:26:35.443193
2099 19:26:35.449819 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2100 19:26:35.453581 [FAST_K] Save calibration result to emmc
2101 19:26:35.456969 [FAST_K] Save calibration result to emmc
2102 19:26:35.460259 dram_init: config_dvfs: 1
2103 19:26:35.463586 dramc_set_vcore_voltage set vcore to 662500
2104 19:26:35.466872 Read voltage for 1200, 2
2105 19:26:35.466958 Vio18 = 0
2106 19:26:35.469994 Vcore = 662500
2107 19:26:35.470078 Vdram = 0
2108 19:26:35.470143 Vddq = 0
2109 19:26:35.470204 Vmddr = 0
2110 19:26:35.476957 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2111 19:26:35.479827 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2112 19:26:35.483177 MEM_TYPE=3, freq_sel=15
2113 19:26:35.487242 sv_algorithm_assistance_LP4_1600
2114 19:26:35.490309 ============ PULL DRAM RESETB DOWN ============
2115 19:26:35.496722 ========== PULL DRAM RESETB DOWN end =========
2116 19:26:35.500471 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2117 19:26:35.503199 ===================================
2118 19:26:35.506427 LPDDR4 DRAM CONFIGURATION
2119 19:26:35.510250 ===================================
2120 19:26:35.510383 EX_ROW_EN[0] = 0x0
2121 19:26:35.513485 EX_ROW_EN[1] = 0x0
2122 19:26:35.513597 LP4Y_EN = 0x0
2123 19:26:35.516805 WORK_FSP = 0x0
2124 19:26:35.516916 WL = 0x4
2125 19:26:35.520046 RL = 0x4
2126 19:26:35.520157 BL = 0x2
2127 19:26:35.523833 RPST = 0x0
2128 19:26:35.523942 RD_PRE = 0x0
2129 19:26:35.526923 WR_PRE = 0x1
2130 19:26:35.527034 WR_PST = 0x0
2131 19:26:35.530342 DBI_WR = 0x0
2132 19:26:35.530450 DBI_RD = 0x0
2133 19:26:35.533653 OTF = 0x1
2134 19:26:35.536928 ===================================
2135 19:26:35.540281 ===================================
2136 19:26:35.540395 ANA top config
2137 19:26:35.543412 ===================================
2138 19:26:35.546649 DLL_ASYNC_EN = 0
2139 19:26:35.550036 ALL_SLAVE_EN = 0
2140 19:26:35.553505 NEW_RANK_MODE = 1
2141 19:26:35.553620 DLL_IDLE_MODE = 1
2142 19:26:35.556769 LP45_APHY_COMB_EN = 1
2143 19:26:35.560733 TX_ODT_DIS = 1
2144 19:26:35.563971 NEW_8X_MODE = 1
2145 19:26:35.567203 ===================================
2146 19:26:35.570660 ===================================
2147 19:26:35.573894 data_rate = 2400
2148 19:26:35.573985 CKR = 1
2149 19:26:35.577234 DQ_P2S_RATIO = 8
2150 19:26:35.580447 ===================================
2151 19:26:35.583885 CA_P2S_RATIO = 8
2152 19:26:35.586869 DQ_CA_OPEN = 0
2153 19:26:35.589893 DQ_SEMI_OPEN = 0
2154 19:26:35.593929 CA_SEMI_OPEN = 0
2155 19:26:35.594021 CA_FULL_RATE = 0
2156 19:26:35.597149 DQ_CKDIV4_EN = 0
2157 19:26:35.600223 CA_CKDIV4_EN = 0
2158 19:26:35.603787 CA_PREDIV_EN = 0
2159 19:26:35.606879 PH8_DLY = 17
2160 19:26:35.610281 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2161 19:26:35.610396 DQ_AAMCK_DIV = 4
2162 19:26:35.613566 CA_AAMCK_DIV = 4
2163 19:26:35.616791 CA_ADMCK_DIV = 4
2164 19:26:35.620735 DQ_TRACK_CA_EN = 0
2165 19:26:35.624056 CA_PICK = 1200
2166 19:26:35.627386 CA_MCKIO = 1200
2167 19:26:35.627484 MCKIO_SEMI = 0
2168 19:26:35.630773 PLL_FREQ = 2366
2169 19:26:35.634181 DQ_UI_PI_RATIO = 32
2170 19:26:35.637478 CA_UI_PI_RATIO = 0
2171 19:26:35.640212 ===================================
2172 19:26:35.644105 ===================================
2173 19:26:35.647203 memory_type:LPDDR4
2174 19:26:35.647294 GP_NUM : 10
2175 19:26:35.650314 SRAM_EN : 1
2176 19:26:35.650431 MD32_EN : 0
2177 19:26:35.654091 ===================================
2178 19:26:35.657610 [ANA_INIT] >>>>>>>>>>>>>>
2179 19:26:35.660712 <<<<<< [CONFIGURE PHASE]: ANA_TX
2180 19:26:35.663951 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2181 19:26:35.667488 ===================================
2182 19:26:35.670421 data_rate = 2400,PCW = 0X5b00
2183 19:26:35.674643 ===================================
2184 19:26:35.677427 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2185 19:26:35.680568 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2186 19:26:35.687138 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2187 19:26:35.693997 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2188 19:26:35.697257 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2189 19:26:35.700489 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2190 19:26:35.700621 [ANA_INIT] flow start
2191 19:26:35.703811 [ANA_INIT] PLL >>>>>>>>
2192 19:26:35.707083 [ANA_INIT] PLL <<<<<<<<
2193 19:26:35.707203 [ANA_INIT] MIDPI >>>>>>>>
2194 19:26:35.710725 [ANA_INIT] MIDPI <<<<<<<<
2195 19:26:35.713740 [ANA_INIT] DLL >>>>>>>>
2196 19:26:35.713869 [ANA_INIT] DLL <<<<<<<<
2197 19:26:35.717364 [ANA_INIT] flow end
2198 19:26:35.720577 ============ LP4 DIFF to SE enter ============
2199 19:26:35.724083 ============ LP4 DIFF to SE exit ============
2200 19:26:35.727452 [ANA_INIT] <<<<<<<<<<<<<
2201 19:26:35.730721 [Flow] Enable top DCM control >>>>>
2202 19:26:35.734098 [Flow] Enable top DCM control <<<<<
2203 19:26:35.737368 Enable DLL master slave shuffle
2204 19:26:35.744051 ==============================================================
2205 19:26:35.744172 Gating Mode config
2206 19:26:35.750553 ==============================================================
2207 19:26:35.750673 Config description:
2208 19:26:35.760524 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2209 19:26:35.767600 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2210 19:26:35.774218 SELPH_MODE 0: By rank 1: By Phase
2211 19:26:35.777560 ==============================================================
2212 19:26:35.780780 GAT_TRACK_EN = 1
2213 19:26:35.784532 RX_GATING_MODE = 2
2214 19:26:35.787333 RX_GATING_TRACK_MODE = 2
2215 19:26:35.790800 SELPH_MODE = 1
2216 19:26:35.794161 PICG_EARLY_EN = 1
2217 19:26:35.797660 VALID_LAT_VALUE = 1
2218 19:26:35.801017 ==============================================================
2219 19:26:35.804384 Enter into Gating configuration >>>>
2220 19:26:35.807677 Exit from Gating configuration <<<<
2221 19:26:35.811087 Enter into DVFS_PRE_config >>>>>
2222 19:26:35.824346 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2223 19:26:35.827513 Exit from DVFS_PRE_config <<<<<
2224 19:26:35.827637 Enter into PICG configuration >>>>
2225 19:26:35.831015 Exit from PICG configuration <<<<
2226 19:26:35.834201 [RX_INPUT] configuration >>>>>
2227 19:26:35.837872 [RX_INPUT] configuration <<<<<
2228 19:26:35.844581 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2229 19:26:35.847931 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2230 19:26:35.854605 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2231 19:26:35.861253 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2232 19:26:35.867751 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2233 19:26:35.874218 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2234 19:26:35.877590 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2235 19:26:35.880968 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2236 19:26:35.884276 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2237 19:26:35.890909 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2238 19:26:35.894114 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2239 19:26:35.897507 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2240 19:26:35.900753 ===================================
2241 19:26:35.904602 LPDDR4 DRAM CONFIGURATION
2242 19:26:35.907889 ===================================
2243 19:26:35.908008 EX_ROW_EN[0] = 0x0
2244 19:26:35.911135 EX_ROW_EN[1] = 0x0
2245 19:26:35.914768 LP4Y_EN = 0x0
2246 19:26:35.914878 WORK_FSP = 0x0
2247 19:26:35.917690 WL = 0x4
2248 19:26:35.917796 RL = 0x4
2249 19:26:35.921143 BL = 0x2
2250 19:26:35.921251 RPST = 0x0
2251 19:26:35.924396 RD_PRE = 0x0
2252 19:26:35.924505 WR_PRE = 0x1
2253 19:26:35.927563 WR_PST = 0x0
2254 19:26:35.927672 DBI_WR = 0x0
2255 19:26:35.931263 DBI_RD = 0x0
2256 19:26:35.931371 OTF = 0x1
2257 19:26:35.934614 ===================================
2258 19:26:35.937767 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2259 19:26:35.944180 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2260 19:26:35.947690 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2261 19:26:35.950877 ===================================
2262 19:26:35.954442 LPDDR4 DRAM CONFIGURATION
2263 19:26:35.957388 ===================================
2264 19:26:35.957505 EX_ROW_EN[0] = 0x10
2265 19:26:35.961047 EX_ROW_EN[1] = 0x0
2266 19:26:35.961162 LP4Y_EN = 0x0
2267 19:26:35.964497 WORK_FSP = 0x0
2268 19:26:35.964608 WL = 0x4
2269 19:26:35.967797 RL = 0x4
2270 19:26:35.967909 BL = 0x2
2271 19:26:35.971234 RPST = 0x0
2272 19:26:35.971344 RD_PRE = 0x0
2273 19:26:35.974584 WR_PRE = 0x1
2274 19:26:35.977833 WR_PST = 0x0
2275 19:26:35.977944 DBI_WR = 0x0
2276 19:26:35.981059 DBI_RD = 0x0
2277 19:26:35.981168 OTF = 0x1
2278 19:26:35.984290 ===================================
2279 19:26:35.990974 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2280 19:26:35.991108 ==
2281 19:26:35.994356 Dram Type= 6, Freq= 0, CH_0, rank 0
2282 19:26:35.997670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2283 19:26:35.997796 ==
2284 19:26:36.000875 [Duty_Offset_Calibration]
2285 19:26:36.000993 B0:2 B1:1 CA:1
2286 19:26:36.004159
2287 19:26:36.007249 [DutyScan_Calibration_Flow] k_type=0
2288 19:26:36.015176
2289 19:26:36.015310 ==CLK 0==
2290 19:26:36.018471 Final CLK duty delay cell = 0
2291 19:26:36.021814 [0] MAX Duty = 5218%(X100), DQS PI = 24
2292 19:26:36.025219 [0] MIN Duty = 4844%(X100), DQS PI = 48
2293 19:26:36.025343 [0] AVG Duty = 5031%(X100)
2294 19:26:36.028469
2295 19:26:36.032344 CH0 CLK Duty spec in!! Max-Min= 374%
2296 19:26:36.035382 [DutyScan_Calibration_Flow] ====Done====
2297 19:26:36.035510
2298 19:26:36.038281 [DutyScan_Calibration_Flow] k_type=1
2299 19:26:36.053736
2300 19:26:36.053900 ==DQS 0 ==
2301 19:26:36.057206 Final DQS duty delay cell = -4
2302 19:26:36.060512 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2303 19:26:36.063905 [-4] MIN Duty = 4751%(X100), DQS PI = 0
2304 19:26:36.067159 [-4] AVG Duty = 4937%(X100)
2305 19:26:36.067249
2306 19:26:36.067321 ==DQS 1 ==
2307 19:26:36.070225 Final DQS duty delay cell = 0
2308 19:26:36.073756 [0] MAX Duty = 5156%(X100), DQS PI = 62
2309 19:26:36.077169 [0] MIN Duty = 5000%(X100), DQS PI = 32
2310 19:26:36.080673 [0] AVG Duty = 5078%(X100)
2311 19:26:36.080764
2312 19:26:36.083644 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2313 19:26:36.083753
2314 19:26:36.087267 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2315 19:26:36.090583 [DutyScan_Calibration_Flow] ====Done====
2316 19:26:36.090684
2317 19:26:36.093875 [DutyScan_Calibration_Flow] k_type=3
2318 19:26:36.110947
2319 19:26:36.111093 ==DQM 0 ==
2320 19:26:36.114091 Final DQM duty delay cell = 0
2321 19:26:36.117478 [0] MAX Duty = 5156%(X100), DQS PI = 30
2322 19:26:36.120775 [0] MIN Duty = 4938%(X100), DQS PI = 0
2323 19:26:36.124129 [0] AVG Duty = 5047%(X100)
2324 19:26:36.124218
2325 19:26:36.124284 ==DQM 1 ==
2326 19:26:36.127365 Final DQM duty delay cell = 0
2327 19:26:36.130729 [0] MAX Duty = 5093%(X100), DQS PI = 0
2328 19:26:36.134092 [0] MIN Duty = 5031%(X100), DQS PI = 14
2329 19:26:36.134207 [0] AVG Duty = 5062%(X100)
2330 19:26:36.137491
2331 19:26:36.140713 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2332 19:26:36.140802
2333 19:26:36.143677 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2334 19:26:36.147055 [DutyScan_Calibration_Flow] ====Done====
2335 19:26:36.147144
2336 19:26:36.150488 [DutyScan_Calibration_Flow] k_type=2
2337 19:26:36.167426
2338 19:26:36.167558 ==DQ 0 ==
2339 19:26:36.170695 Final DQ duty delay cell = 0
2340 19:26:36.173939 [0] MAX Duty = 5031%(X100), DQS PI = 26
2341 19:26:36.177224 [0] MIN Duty = 4875%(X100), DQS PI = 62
2342 19:26:36.177315 [0] AVG Duty = 4953%(X100)
2343 19:26:36.177385
2344 19:26:36.180349 ==DQ 1 ==
2345 19:26:36.183867 Final DQ duty delay cell = 0
2346 19:26:36.187061 [0] MAX Duty = 5093%(X100), DQS PI = 24
2347 19:26:36.190672 [0] MIN Duty = 4907%(X100), DQS PI = 36
2348 19:26:36.190771 [0] AVG Duty = 5000%(X100)
2349 19:26:36.190839
2350 19:26:36.193718 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2351 19:26:36.193818
2352 19:26:36.196970 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2353 19:26:36.203835 [DutyScan_Calibration_Flow] ====Done====
2354 19:26:36.203951 ==
2355 19:26:36.206917 Dram Type= 6, Freq= 0, CH_1, rank 0
2356 19:26:36.210226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2357 19:26:36.210361 ==
2358 19:26:36.214132 [Duty_Offset_Calibration]
2359 19:26:36.214243 B0:1 B1:0 CA:0
2360 19:26:36.214353
2361 19:26:36.216966 [DutyScan_Calibration_Flow] k_type=0
2362 19:26:36.226066
2363 19:26:36.226209 ==CLK 0==
2364 19:26:36.229491 Final CLK duty delay cell = -4
2365 19:26:36.232874 [-4] MAX Duty = 5000%(X100), DQS PI = 20
2366 19:26:36.236205 [-4] MIN Duty = 4875%(X100), DQS PI = 50
2367 19:26:36.239514 [-4] AVG Duty = 4937%(X100)
2368 19:26:36.239605
2369 19:26:36.242968 CH1 CLK Duty spec in!! Max-Min= 125%
2370 19:26:36.246083 [DutyScan_Calibration_Flow] ====Done====
2371 19:26:36.246202
2372 19:26:36.249374 [DutyScan_Calibration_Flow] k_type=1
2373 19:26:36.266108
2374 19:26:36.266256 ==DQS 0 ==
2375 19:26:36.269289 Final DQS duty delay cell = 0
2376 19:26:36.272472 [0] MAX Duty = 5062%(X100), DQS PI = 10
2377 19:26:36.276371 [0] MIN Duty = 4875%(X100), DQS PI = 0
2378 19:26:36.276464 [0] AVG Duty = 4968%(X100)
2379 19:26:36.279659
2380 19:26:36.279745 ==DQS 1 ==
2381 19:26:36.282912 Final DQS duty delay cell = 0
2382 19:26:36.286110 [0] MAX Duty = 5187%(X100), DQS PI = 18
2383 19:26:36.289587 [0] MIN Duty = 4938%(X100), DQS PI = 12
2384 19:26:36.289687 [0] AVG Duty = 5062%(X100)
2385 19:26:36.292675
2386 19:26:36.296533 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2387 19:26:36.296659
2388 19:26:36.299862 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2389 19:26:36.303177 [DutyScan_Calibration_Flow] ====Done====
2390 19:26:36.303299
2391 19:26:36.305810 [DutyScan_Calibration_Flow] k_type=3
2392 19:26:36.322390
2393 19:26:36.322525 ==DQM 0 ==
2394 19:26:36.325891 Final DQM duty delay cell = 0
2395 19:26:36.329275 [0] MAX Duty = 5156%(X100), DQS PI = 8
2396 19:26:36.332729 [0] MIN Duty = 5000%(X100), DQS PI = 62
2397 19:26:36.336560 [0] AVG Duty = 5078%(X100)
2398 19:26:36.336677
2399 19:26:36.336776 ==DQM 1 ==
2400 19:26:36.339278 Final DQM duty delay cell = 0
2401 19:26:36.342450 [0] MAX Duty = 5031%(X100), DQS PI = 18
2402 19:26:36.346018 [0] MIN Duty = 4875%(X100), DQS PI = 36
2403 19:26:36.349268 [0] AVG Duty = 4953%(X100)
2404 19:26:36.349357
2405 19:26:36.352549 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2406 19:26:36.352637
2407 19:26:36.355817 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2408 19:26:36.359152 [DutyScan_Calibration_Flow] ====Done====
2409 19:26:36.359242
2410 19:26:36.362198 [DutyScan_Calibration_Flow] k_type=2
2411 19:26:36.378390
2412 19:26:36.378518 ==DQ 0 ==
2413 19:26:36.382153 Final DQ duty delay cell = -4
2414 19:26:36.385445 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2415 19:26:36.388952 [-4] MIN Duty = 4906%(X100), DQS PI = 44
2416 19:26:36.391531 [-4] AVG Duty = 4984%(X100)
2417 19:26:36.391661
2418 19:26:36.391770 ==DQ 1 ==
2419 19:26:36.395334 Final DQ duty delay cell = 0
2420 19:26:36.398464 [0] MAX Duty = 5125%(X100), DQS PI = 20
2421 19:26:36.401546 [0] MIN Duty = 4969%(X100), DQS PI = 12
2422 19:26:36.401673 [0] AVG Duty = 5047%(X100)
2423 19:26:36.404875
2424 19:26:36.408466 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2425 19:26:36.408561
2426 19:26:36.412183 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2427 19:26:36.415218 [DutyScan_Calibration_Flow] ====Done====
2428 19:26:36.418500 nWR fixed to 30
2429 19:26:36.418596 [ModeRegInit_LP4] CH0 RK0
2430 19:26:36.421722 [ModeRegInit_LP4] CH0 RK1
2431 19:26:36.424926 [ModeRegInit_LP4] CH1 RK0
2432 19:26:36.428265 [ModeRegInit_LP4] CH1 RK1
2433 19:26:36.428353 match AC timing 7
2434 19:26:36.432026 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2435 19:26:36.438552 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2436 19:26:36.441840 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2437 19:26:36.448670 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2438 19:26:36.451935 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2439 19:26:36.452057 ==
2440 19:26:36.454819 Dram Type= 6, Freq= 0, CH_0, rank 0
2441 19:26:36.458194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2442 19:26:36.458287 ==
2443 19:26:36.465321 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2444 19:26:36.471741 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2445 19:26:36.478663 [CA 0] Center 39 (8~70) winsize 63
2446 19:26:36.482008 [CA 1] Center 39 (8~70) winsize 63
2447 19:26:36.485207 [CA 2] Center 35 (5~66) winsize 62
2448 19:26:36.489124 [CA 3] Center 34 (4~65) winsize 62
2449 19:26:36.492449 [CA 4] Center 33 (3~64) winsize 62
2450 19:26:36.495089 [CA 5] Center 32 (3~62) winsize 60
2451 19:26:36.495207
2452 19:26:36.498579 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2453 19:26:36.498701
2454 19:26:36.501857 [CATrainingPosCal] consider 1 rank data
2455 19:26:36.505578 u2DelayCellTimex100 = 270/100 ps
2456 19:26:36.508683 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2457 19:26:36.512324 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2458 19:26:36.519221 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2459 19:26:36.522108 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2460 19:26:36.525386 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2461 19:26:36.528625 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2462 19:26:36.528722
2463 19:26:36.531945 CA PerBit enable=1, Macro0, CA PI delay=32
2464 19:26:36.532029
2465 19:26:36.535266 [CBTSetCACLKResult] CA Dly = 32
2466 19:26:36.535346 CS Dly: 6 (0~37)
2467 19:26:36.535437 ==
2468 19:26:36.539150 Dram Type= 6, Freq= 0, CH_0, rank 1
2469 19:26:36.545775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2470 19:26:36.545875 ==
2471 19:26:36.549082 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2472 19:26:36.555748 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2473 19:26:36.564266 [CA 0] Center 38 (8~69) winsize 62
2474 19:26:36.568189 [CA 1] Center 38 (8~69) winsize 62
2475 19:26:36.571066 [CA 2] Center 35 (5~66) winsize 62
2476 19:26:36.574212 [CA 3] Center 34 (4~65) winsize 62
2477 19:26:36.577531 [CA 4] Center 33 (3~64) winsize 62
2478 19:26:36.581049 [CA 5] Center 32 (3~62) winsize 60
2479 19:26:36.581140
2480 19:26:36.584332 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2481 19:26:36.584442
2482 19:26:36.587805 [CATrainingPosCal] consider 2 rank data
2483 19:26:36.591247 u2DelayCellTimex100 = 270/100 ps
2484 19:26:36.594413 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2485 19:26:36.597819 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2486 19:26:36.604685 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2487 19:26:36.607792 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2488 19:26:36.611080 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2489 19:26:36.614287 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2490 19:26:36.614394
2491 19:26:36.617865 CA PerBit enable=1, Macro0, CA PI delay=32
2492 19:26:36.617978
2493 19:26:36.620895 [CBTSetCACLKResult] CA Dly = 32
2494 19:26:36.621008 CS Dly: 6 (0~38)
2495 19:26:36.621114
2496 19:26:36.624786 ----->DramcWriteLeveling(PI) begin...
2497 19:26:36.627893 ==
2498 19:26:36.628007 Dram Type= 6, Freq= 0, CH_0, rank 0
2499 19:26:36.634521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2500 19:26:36.634664 ==
2501 19:26:36.637874 Write leveling (Byte 0): 34 => 34
2502 19:26:36.641245 Write leveling (Byte 1): 29 => 29
2503 19:26:36.641356 DramcWriteLeveling(PI) end<-----
2504 19:26:36.644531
2505 19:26:36.644658 ==
2506 19:26:36.648208 Dram Type= 6, Freq= 0, CH_0, rank 0
2507 19:26:36.651595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2508 19:26:36.651685 ==
2509 19:26:36.654842 [Gating] SW mode calibration
2510 19:26:36.661456 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2511 19:26:36.664593 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2512 19:26:36.671488 0 15 0 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
2513 19:26:36.674889 0 15 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
2514 19:26:36.677954 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2515 19:26:36.684815 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2516 19:26:36.687926 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2517 19:26:36.691206 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2518 19:26:36.697755 0 15 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
2519 19:26:36.701245 0 15 28 | B1->B0 | 3333 2424 | 1 0 | (1 1) (1 0)
2520 19:26:36.704644 1 0 0 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
2521 19:26:36.711540 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2522 19:26:36.714942 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2523 19:26:36.718069 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2524 19:26:36.724625 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2525 19:26:36.727866 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2526 19:26:36.731301 1 0 24 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
2527 19:26:36.737788 1 0 28 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
2528 19:26:36.741089 1 1 0 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
2529 19:26:36.744722 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2530 19:26:36.748131 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2531 19:26:36.754479 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2532 19:26:36.757802 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2533 19:26:36.761081 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2534 19:26:36.767654 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2535 19:26:36.770918 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2536 19:26:36.774262 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2537 19:26:36.780893 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2538 19:26:36.784326 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2539 19:26:36.787615 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2540 19:26:36.794339 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2541 19:26:36.797630 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2542 19:26:36.800968 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2543 19:26:36.807652 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2544 19:26:36.810998 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 19:26:36.814314 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 19:26:36.821228 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 19:26:36.824828 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 19:26:36.827615 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 19:26:36.834435 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 19:26:36.838251 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 19:26:36.841342 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2552 19:26:36.844563 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2553 19:26:36.847759 Total UI for P1: 0, mck2ui 16
2554 19:26:36.851405 best dqsien dly found for B0: ( 1, 3, 28)
2555 19:26:36.857907 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2556 19:26:36.858039 Total UI for P1: 0, mck2ui 16
2557 19:26:36.864382 best dqsien dly found for B1: ( 1, 4, 0)
2558 19:26:36.868040 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2559 19:26:36.871369 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2560 19:26:36.871491
2561 19:26:36.874530 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2562 19:26:36.878200 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2563 19:26:36.881567 [Gating] SW calibration Done
2564 19:26:36.881689 ==
2565 19:26:36.884421 Dram Type= 6, Freq= 0, CH_0, rank 0
2566 19:26:36.887733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2567 19:26:36.887849 ==
2568 19:26:36.891116 RX Vref Scan: 0
2569 19:26:36.891213
2570 19:26:36.891280 RX Vref 0 -> 0, step: 1
2571 19:26:36.891342
2572 19:26:36.894573 RX Delay -40 -> 252, step: 8
2573 19:26:36.897918 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2574 19:26:36.904630 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2575 19:26:36.907902 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2576 19:26:36.911243 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2577 19:26:36.914675 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2578 19:26:36.917971 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2579 19:26:36.924698 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2580 19:26:36.927920 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2581 19:26:36.931033 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2582 19:26:36.934482 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2583 19:26:36.938349 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2584 19:26:36.944479 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2585 19:26:36.948040 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2586 19:26:36.951669 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2587 19:26:36.954797 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2588 19:26:36.958403 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2589 19:26:36.958522 ==
2590 19:26:36.961611 Dram Type= 6, Freq= 0, CH_0, rank 0
2591 19:26:36.968174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2592 19:26:36.968347 ==
2593 19:26:36.968445 DQS Delay:
2594 19:26:36.971472 DQS0 = 0, DQS1 = 0
2595 19:26:36.971583 DQM Delay:
2596 19:26:36.974655 DQM0 = 121, DQM1 = 113
2597 19:26:36.974765 DQ Delay:
2598 19:26:36.978244 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2599 19:26:36.981459 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2600 19:26:36.984863 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2601 19:26:36.988296 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =119
2602 19:26:36.988412
2603 19:26:36.988508
2604 19:26:36.988598 ==
2605 19:26:36.991580 Dram Type= 6, Freq= 0, CH_0, rank 0
2606 19:26:36.994550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2607 19:26:36.998061 ==
2608 19:26:36.998152
2609 19:26:36.998217
2610 19:26:36.998308 TX Vref Scan disable
2611 19:26:37.001310 == TX Byte 0 ==
2612 19:26:37.004563 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2613 19:26:37.007877 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2614 19:26:37.011248 == TX Byte 1 ==
2615 19:26:37.014983 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2616 19:26:37.018282 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2617 19:26:37.021644 ==
2618 19:26:37.021730 Dram Type= 6, Freq= 0, CH_0, rank 0
2619 19:26:37.028404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2620 19:26:37.028500 ==
2621 19:26:37.039514 TX Vref=22, minBit 0, minWin=25, winSum=410
2622 19:26:37.043227 TX Vref=24, minBit 3, minWin=25, winSum=417
2623 19:26:37.045891 TX Vref=26, minBit 3, minWin=25, winSum=418
2624 19:26:37.049199 TX Vref=28, minBit 0, minWin=26, winSum=425
2625 19:26:37.052629 TX Vref=30, minBit 0, minWin=26, winSum=423
2626 19:26:37.059295 TX Vref=32, minBit 0, minWin=26, winSum=422
2627 19:26:37.062869 [TxChooseVref] Worse bit 0, Min win 26, Win sum 425, Final Vref 28
2628 19:26:37.062961
2629 19:26:37.066633 Final TX Range 1 Vref 28
2630 19:26:37.066721
2631 19:26:37.066786 ==
2632 19:26:37.069821 Dram Type= 6, Freq= 0, CH_0, rank 0
2633 19:26:37.072756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2634 19:26:37.072860 ==
2635 19:26:37.072960
2636 19:26:37.073052
2637 19:26:37.076581 TX Vref Scan disable
2638 19:26:37.079545 == TX Byte 0 ==
2639 19:26:37.083172 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2640 19:26:37.086229 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2641 19:26:37.089578 == TX Byte 1 ==
2642 19:26:37.092975 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2643 19:26:37.096191 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2644 19:26:37.096309
2645 19:26:37.099569 [DATLAT]
2646 19:26:37.099653 Freq=1200, CH0 RK0
2647 19:26:37.099719
2648 19:26:37.102885 DATLAT Default: 0xd
2649 19:26:37.102973 0, 0xFFFF, sum = 0
2650 19:26:37.106249 1, 0xFFFF, sum = 0
2651 19:26:37.106387 2, 0xFFFF, sum = 0
2652 19:26:37.109526 3, 0xFFFF, sum = 0
2653 19:26:37.109630 4, 0xFFFF, sum = 0
2654 19:26:37.112524 5, 0xFFFF, sum = 0
2655 19:26:37.112611 6, 0xFFFF, sum = 0
2656 19:26:37.116060 7, 0xFFFF, sum = 0
2657 19:26:37.116145 8, 0xFFFF, sum = 0
2658 19:26:37.119566 9, 0xFFFF, sum = 0
2659 19:26:37.122839 10, 0xFFFF, sum = 0
2660 19:26:37.122952 11, 0xFFFF, sum = 0
2661 19:26:37.126151 12, 0x0, sum = 1
2662 19:26:37.126266 13, 0x0, sum = 2
2663 19:26:37.126370 14, 0x0, sum = 3
2664 19:26:37.129585 15, 0x0, sum = 4
2665 19:26:37.129670 best_step = 13
2666 19:26:37.129736
2667 19:26:37.129796 ==
2668 19:26:37.132785 Dram Type= 6, Freq= 0, CH_0, rank 0
2669 19:26:37.139721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2670 19:26:37.139851 ==
2671 19:26:37.139932 RX Vref Scan: 1
2672 19:26:37.139993
2673 19:26:37.142961 Set Vref Range= 32 -> 127
2674 19:26:37.143047
2675 19:26:37.146235 RX Vref 32 -> 127, step: 1
2676 19:26:37.146358
2677 19:26:37.149538 RX Delay -13 -> 252, step: 4
2678 19:26:37.149622
2679 19:26:37.152843 Set Vref, RX VrefLevel [Byte0]: 32
2680 19:26:37.156198 [Byte1]: 32
2681 19:26:37.156283
2682 19:26:37.159471 Set Vref, RX VrefLevel [Byte0]: 33
2683 19:26:37.162844 [Byte1]: 33
2684 19:26:37.162931
2685 19:26:37.166212 Set Vref, RX VrefLevel [Byte0]: 34
2686 19:26:37.169635 [Byte1]: 34
2687 19:26:37.173504
2688 19:26:37.173591 Set Vref, RX VrefLevel [Byte0]: 35
2689 19:26:37.177111 [Byte1]: 35
2690 19:26:37.181017
2691 19:26:37.181103 Set Vref, RX VrefLevel [Byte0]: 36
2692 19:26:37.184640 [Byte1]: 36
2693 19:26:37.189375
2694 19:26:37.189461 Set Vref, RX VrefLevel [Byte0]: 37
2695 19:26:37.192230 [Byte1]: 37
2696 19:26:37.196701
2697 19:26:37.196836 Set Vref, RX VrefLevel [Byte0]: 38
2698 19:26:37.200081 [Byte1]: 38
2699 19:26:37.204761
2700 19:26:37.204892 Set Vref, RX VrefLevel [Byte0]: 39
2701 19:26:37.208222 [Byte1]: 39
2702 19:26:37.212903
2703 19:26:37.213045 Set Vref, RX VrefLevel [Byte0]: 40
2704 19:26:37.216210 [Byte1]: 40
2705 19:26:37.220861
2706 19:26:37.220989 Set Vref, RX VrefLevel [Byte0]: 41
2707 19:26:37.224389 [Byte1]: 41
2708 19:26:37.228412
2709 19:26:37.228496 Set Vref, RX VrefLevel [Byte0]: 42
2710 19:26:37.231731 [Byte1]: 42
2711 19:26:37.236723
2712 19:26:37.236807 Set Vref, RX VrefLevel [Byte0]: 43
2713 19:26:37.239830 [Byte1]: 43
2714 19:26:37.244504
2715 19:26:37.244586 Set Vref, RX VrefLevel [Byte0]: 44
2716 19:26:37.247838 [Byte1]: 44
2717 19:26:37.252192
2718 19:26:37.252302 Set Vref, RX VrefLevel [Byte0]: 45
2719 19:26:37.255511 [Byte1]: 45
2720 19:26:37.260408
2721 19:26:37.260516 Set Vref, RX VrefLevel [Byte0]: 46
2722 19:26:37.263581 [Byte1]: 46
2723 19:26:37.268194
2724 19:26:37.268303 Set Vref, RX VrefLevel [Byte0]: 47
2725 19:26:37.271765 [Byte1]: 47
2726 19:26:37.275798
2727 19:26:37.275906 Set Vref, RX VrefLevel [Byte0]: 48
2728 19:26:37.279191 [Byte1]: 48
2729 19:26:37.283607
2730 19:26:37.283714 Set Vref, RX VrefLevel [Byte0]: 49
2731 19:26:37.287560 [Byte1]: 49
2732 19:26:37.291842
2733 19:26:37.291950 Set Vref, RX VrefLevel [Byte0]: 50
2734 19:26:37.294909 [Byte1]: 50
2735 19:26:37.299343
2736 19:26:37.299454 Set Vref, RX VrefLevel [Byte0]: 51
2737 19:26:37.302981 [Byte1]: 51
2738 19:26:37.307239
2739 19:26:37.307353 Set Vref, RX VrefLevel [Byte0]: 52
2740 19:26:37.310901 [Byte1]: 52
2741 19:26:37.315442
2742 19:26:37.315557 Set Vref, RX VrefLevel [Byte0]: 53
2743 19:26:37.318761 [Byte1]: 53
2744 19:26:37.323470
2745 19:26:37.323583 Set Vref, RX VrefLevel [Byte0]: 54
2746 19:26:37.326937 [Byte1]: 54
2747 19:26:37.330928
2748 19:26:37.331052 Set Vref, RX VrefLevel [Byte0]: 55
2749 19:26:37.334276 [Byte1]: 55
2750 19:26:37.338916
2751 19:26:37.339030 Set Vref, RX VrefLevel [Byte0]: 56
2752 19:26:37.342117 [Byte1]: 56
2753 19:26:37.346907
2754 19:26:37.347051 Set Vref, RX VrefLevel [Byte0]: 57
2755 19:26:37.350152 [Byte1]: 57
2756 19:26:37.354677
2757 19:26:37.354792 Set Vref, RX VrefLevel [Byte0]: 58
2758 19:26:37.357940 [Byte1]: 58
2759 19:26:37.363037
2760 19:26:37.363203 Set Vref, RX VrefLevel [Byte0]: 59
2761 19:26:37.366129 [Byte1]: 59
2762 19:26:37.370795
2763 19:26:37.370917 Set Vref, RX VrefLevel [Byte0]: 60
2764 19:26:37.373827 [Byte1]: 60
2765 19:26:37.378451
2766 19:26:37.378589 Set Vref, RX VrefLevel [Byte0]: 61
2767 19:26:37.381833 [Byte1]: 61
2768 19:26:37.386294
2769 19:26:37.386427 Set Vref, RX VrefLevel [Byte0]: 62
2770 19:26:37.389694 [Byte1]: 62
2771 19:26:37.394408
2772 19:26:37.394535 Set Vref, RX VrefLevel [Byte0]: 63
2773 19:26:37.397601 [Byte1]: 63
2774 19:26:37.402123
2775 19:26:37.402252 Set Vref, RX VrefLevel [Byte0]: 64
2776 19:26:37.405874 [Byte1]: 64
2777 19:26:37.410385
2778 19:26:37.410477 Set Vref, RX VrefLevel [Byte0]: 65
2779 19:26:37.413650 [Byte1]: 65
2780 19:26:37.417756
2781 19:26:37.417846 Set Vref, RX VrefLevel [Byte0]: 66
2782 19:26:37.421355 [Byte1]: 66
2783 19:26:37.425479
2784 19:26:37.425598 Set Vref, RX VrefLevel [Byte0]: 67
2785 19:26:37.428930 [Byte1]: 67
2786 19:26:37.433546
2787 19:26:37.433633 Set Vref, RX VrefLevel [Byte0]: 68
2788 19:26:37.436926 [Byte1]: 68
2789 19:26:37.441711
2790 19:26:37.441800 Set Vref, RX VrefLevel [Byte0]: 69
2791 19:26:37.445147 [Byte1]: 69
2792 19:26:37.449801
2793 19:26:37.449893 Final RX Vref Byte 0 = 54 to rank0
2794 19:26:37.453185 Final RX Vref Byte 1 = 46 to rank0
2795 19:26:37.456306 Final RX Vref Byte 0 = 54 to rank1
2796 19:26:37.459602 Final RX Vref Byte 1 = 46 to rank1==
2797 19:26:37.462739 Dram Type= 6, Freq= 0, CH_0, rank 0
2798 19:26:37.469668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2799 19:26:37.469778 ==
2800 19:26:37.469868 DQS Delay:
2801 19:26:37.469949 DQS0 = 0, DQS1 = 0
2802 19:26:37.472698 DQM Delay:
2803 19:26:37.472773 DQM0 = 120, DQM1 = 110
2804 19:26:37.475881 DQ Delay:
2805 19:26:37.479292 DQ0 =120, DQ1 =124, DQ2 =118, DQ3 =118
2806 19:26:37.482575 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2807 19:26:37.485963 DQ8 =96, DQ9 =98, DQ10 =112, DQ11 =102
2808 19:26:37.489126 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =118
2809 19:26:37.489217
2810 19:26:37.489304
2811 19:26:37.496147 [DQSOSCAuto] RK0, (LSB)MR18= 0x1710, (MSB)MR19= 0x404, tDQSOscB0 = 403 ps tDQSOscB1 = 401 ps
2812 19:26:37.499689 CH0 RK0: MR19=404, MR18=1710
2813 19:26:37.505929 CH0_RK0: MR19=0x404, MR18=0x1710, DQSOSC=401, MR23=63, INC=40, DEC=27
2814 19:26:37.506039
2815 19:26:37.510031 ----->DramcWriteLeveling(PI) begin...
2816 19:26:37.510145 ==
2817 19:26:37.512767 Dram Type= 6, Freq= 0, CH_0, rank 1
2818 19:26:37.516336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2819 19:26:37.516427 ==
2820 19:26:37.519452 Write leveling (Byte 0): 34 => 34
2821 19:26:37.522799 Write leveling (Byte 1): 29 => 29
2822 19:26:37.526262 DramcWriteLeveling(PI) end<-----
2823 19:26:37.526358
2824 19:26:37.526424 ==
2825 19:26:37.529267 Dram Type= 6, Freq= 0, CH_0, rank 1
2826 19:26:37.535985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2827 19:26:37.536099 ==
2828 19:26:37.536194 [Gating] SW mode calibration
2829 19:26:37.546508 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2830 19:26:37.549919 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2831 19:26:37.553205 0 15 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
2832 19:26:37.559306 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2833 19:26:37.562621 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2834 19:26:37.566474 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2835 19:26:37.573164 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2836 19:26:37.576400 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2837 19:26:37.579519 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2838 19:26:37.586471 0 15 28 | B1->B0 | 3232 2f2f | 1 1 | (1 0) (1 0)
2839 19:26:37.589671 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
2840 19:26:37.593160 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2841 19:26:37.599466 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2842 19:26:37.602716 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2843 19:26:37.606079 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2844 19:26:37.612701 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2845 19:26:37.615851 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2846 19:26:37.619517 1 0 28 | B1->B0 | 3b3b 3d3d | 0 0 | (0 0) (0 0)
2847 19:26:37.626163 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2848 19:26:37.629612 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2849 19:26:37.633234 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2850 19:26:37.636210 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2851 19:26:37.642805 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2852 19:26:37.646213 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2853 19:26:37.649474 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2854 19:26:37.656704 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2855 19:26:37.660174 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2856 19:26:37.662735 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2857 19:26:37.669898 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2858 19:26:37.673241 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2859 19:26:37.676475 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2860 19:26:37.683165 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2861 19:26:37.686398 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2862 19:26:37.689803 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 19:26:37.696577 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 19:26:37.699873 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 19:26:37.703066 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 19:26:37.706754 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 19:26:37.713473 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 19:26:37.716915 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 19:26:37.720212 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 19:26:37.726842 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2871 19:26:37.730177 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2872 19:26:37.733497 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2873 19:26:37.736758 Total UI for P1: 0, mck2ui 16
2874 19:26:37.739980 best dqsien dly found for B0: ( 1, 3, 30)
2875 19:26:37.743818 Total UI for P1: 0, mck2ui 16
2876 19:26:37.746961 best dqsien dly found for B1: ( 1, 3, 30)
2877 19:26:37.750028 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2878 19:26:37.753390 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2879 19:26:37.753550
2880 19:26:37.756999 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2881 19:26:37.763572 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2882 19:26:37.763754 [Gating] SW calibration Done
2883 19:26:37.763852 ==
2884 19:26:37.766632 Dram Type= 6, Freq= 0, CH_0, rank 1
2885 19:26:37.773594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2886 19:26:37.773699 ==
2887 19:26:37.773767 RX Vref Scan: 0
2888 19:26:37.773828
2889 19:26:37.776778 RX Vref 0 -> 0, step: 1
2890 19:26:37.776871
2891 19:26:37.780360 RX Delay -40 -> 252, step: 8
2892 19:26:37.784029 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2893 19:26:37.787274 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2894 19:26:37.790531 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2895 19:26:37.796858 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2896 19:26:37.800532 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2897 19:26:37.803458 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2898 19:26:37.806629 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2899 19:26:37.809892 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2900 19:26:37.813605 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2901 19:26:37.820237 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2902 19:26:37.823726 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2903 19:26:37.826913 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2904 19:26:37.830054 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2905 19:26:37.836622 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2906 19:26:37.840121 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2907 19:26:37.843430 iDelay=200, Bit 15, Center 119 (56 ~ 183) 128
2908 19:26:37.843542 ==
2909 19:26:37.847252 Dram Type= 6, Freq= 0, CH_0, rank 1
2910 19:26:37.850468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2911 19:26:37.850581 ==
2912 19:26:37.853830 DQS Delay:
2913 19:26:37.853939 DQS0 = 0, DQS1 = 0
2914 19:26:37.854033 DQM Delay:
2915 19:26:37.856835 DQM0 = 122, DQM1 = 112
2916 19:26:37.856950 DQ Delay:
2917 19:26:37.860185 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2918 19:26:37.863509 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127
2919 19:26:37.869938 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2920 19:26:37.873718 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =119
2921 19:26:37.873835
2922 19:26:37.873930
2923 19:26:37.874021 ==
2924 19:26:37.876950 Dram Type= 6, Freq= 0, CH_0, rank 1
2925 19:26:37.880139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2926 19:26:37.880228 ==
2927 19:26:37.880315
2928 19:26:37.880421
2929 19:26:37.883703 TX Vref Scan disable
2930 19:26:37.883784 == TX Byte 0 ==
2931 19:26:37.890384 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2932 19:26:37.893761 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2933 19:26:37.893856 == TX Byte 1 ==
2934 19:26:37.900224 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2935 19:26:37.903592 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2936 19:26:37.903684 ==
2937 19:26:37.907144 Dram Type= 6, Freq= 0, CH_0, rank 1
2938 19:26:37.910504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2939 19:26:37.910591 ==
2940 19:26:37.923436 TX Vref=22, minBit 0, minWin=25, winSum=417
2941 19:26:37.926766 TX Vref=24, minBit 3, minWin=25, winSum=422
2942 19:26:37.930183 TX Vref=26, minBit 0, minWin=26, winSum=425
2943 19:26:37.933505 TX Vref=28, minBit 3, minWin=26, winSum=428
2944 19:26:37.936739 TX Vref=30, minBit 1, minWin=26, winSum=427
2945 19:26:37.940572 TX Vref=32, minBit 1, minWin=26, winSum=425
2946 19:26:37.947292 [TxChooseVref] Worse bit 3, Min win 26, Win sum 428, Final Vref 28
2947 19:26:37.947412
2948 19:26:37.950534 Final TX Range 1 Vref 28
2949 19:26:37.950622
2950 19:26:37.950708 ==
2951 19:26:37.953697 Dram Type= 6, Freq= 0, CH_0, rank 1
2952 19:26:37.956988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2953 19:26:37.957080 ==
2954 19:26:37.957169
2955 19:26:37.957269
2956 19:26:37.960298 TX Vref Scan disable
2957 19:26:37.963919 == TX Byte 0 ==
2958 19:26:37.967385 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2959 19:26:37.970712 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2960 19:26:37.973923 == TX Byte 1 ==
2961 19:26:37.977186 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2962 19:26:37.980364 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2963 19:26:37.980476
2964 19:26:37.983712 [DATLAT]
2965 19:26:37.983812 Freq=1200, CH0 RK1
2966 19:26:37.983906
2967 19:26:37.986849 DATLAT Default: 0xd
2968 19:26:37.986920 0, 0xFFFF, sum = 0
2969 19:26:37.990816 1, 0xFFFF, sum = 0
2970 19:26:37.990888 2, 0xFFFF, sum = 0
2971 19:26:37.994157 3, 0xFFFF, sum = 0
2972 19:26:37.994256 4, 0xFFFF, sum = 0
2973 19:26:37.997311 5, 0xFFFF, sum = 0
2974 19:26:37.997382 6, 0xFFFF, sum = 0
2975 19:26:38.000625 7, 0xFFFF, sum = 0
2976 19:26:38.000725 8, 0xFFFF, sum = 0
2977 19:26:38.003767 9, 0xFFFF, sum = 0
2978 19:26:38.003865 10, 0xFFFF, sum = 0
2979 19:26:38.007542 11, 0xFFFF, sum = 0
2980 19:26:38.007641 12, 0x0, sum = 1
2981 19:26:38.010554 13, 0x0, sum = 2
2982 19:26:38.010623 14, 0x0, sum = 3
2983 19:26:38.014182 15, 0x0, sum = 4
2984 19:26:38.014285 best_step = 13
2985 19:26:38.014359
2986 19:26:38.014418 ==
2987 19:26:38.017007 Dram Type= 6, Freq= 0, CH_0, rank 1
2988 19:26:38.023937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2989 19:26:38.024022 ==
2990 19:26:38.024087 RX Vref Scan: 0
2991 19:26:38.024148
2992 19:26:38.027447 RX Vref 0 -> 0, step: 1
2993 19:26:38.027519
2994 19:26:38.030781 RX Delay -13 -> 252, step: 4
2995 19:26:38.034331 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
2996 19:26:38.037428 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
2997 19:26:38.043856 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
2998 19:26:38.047604 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
2999 19:26:38.050947 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3000 19:26:38.054214 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3001 19:26:38.057442 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3002 19:26:38.060750 iDelay=195, Bit 7, Center 128 (63 ~ 194) 132
3003 19:26:38.067379 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3004 19:26:38.070544 iDelay=195, Bit 9, Center 96 (31 ~ 162) 132
3005 19:26:38.074094 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3006 19:26:38.077494 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3007 19:26:38.080576 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3008 19:26:38.087860 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3009 19:26:38.090568 iDelay=195, Bit 14, Center 120 (59 ~ 182) 124
3010 19:26:38.093948 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3011 19:26:38.094114 ==
3012 19:26:38.097309 Dram Type= 6, Freq= 0, CH_0, rank 1
3013 19:26:38.100560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3014 19:26:38.104262 ==
3015 19:26:38.104415 DQS Delay:
3016 19:26:38.104536 DQS0 = 0, DQS1 = 0
3017 19:26:38.107418 DQM Delay:
3018 19:26:38.107564 DQM0 = 121, DQM1 = 109
3019 19:26:38.110663 DQ Delay:
3020 19:26:38.114257 DQ0 =118, DQ1 =122, DQ2 =118, DQ3 =118
3021 19:26:38.117169 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =128
3022 19:26:38.120572 DQ8 =100, DQ9 =96, DQ10 =110, DQ11 =100
3023 19:26:38.123818 DQ12 =114, DQ13 =116, DQ14 =120, DQ15 =118
3024 19:26:38.123986
3025 19:26:38.124104
3026 19:26:38.130731 [DQSOSCAuto] RK1, (LSB)MR18= 0xfef, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 404 ps
3027 19:26:38.133917 CH0 RK1: MR19=403, MR18=FEF
3028 19:26:38.140633 CH0_RK1: MR19=0x403, MR18=0xFEF, DQSOSC=404, MR23=63, INC=40, DEC=26
3029 19:26:38.143833 [RxdqsGatingPostProcess] freq 1200
3030 19:26:38.150668 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3031 19:26:38.150837 best DQS0 dly(2T, 0.5T) = (0, 11)
3032 19:26:38.154197 best DQS1 dly(2T, 0.5T) = (0, 12)
3033 19:26:38.157355 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3034 19:26:38.160446 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3035 19:26:38.163729 best DQS0 dly(2T, 0.5T) = (0, 11)
3036 19:26:38.167005 best DQS1 dly(2T, 0.5T) = (0, 11)
3037 19:26:38.170395 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3038 19:26:38.174187 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3039 19:26:38.177356 Pre-setting of DQS Precalculation
3040 19:26:38.180862 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3041 19:26:38.184291 ==
3042 19:26:38.186947 Dram Type= 6, Freq= 0, CH_1, rank 0
3043 19:26:38.190618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3044 19:26:38.190776 ==
3045 19:26:38.194005 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3046 19:26:38.200466 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3047 19:26:38.209862 [CA 0] Center 37 (7~68) winsize 62
3048 19:26:38.212992 [CA 1] Center 37 (7~68) winsize 62
3049 19:26:38.216234 [CA 2] Center 34 (4~65) winsize 62
3050 19:26:38.219474 [CA 3] Center 34 (4~64) winsize 61
3051 19:26:38.222797 [CA 4] Center 34 (4~64) winsize 61
3052 19:26:38.226247 [CA 5] Center 33 (3~63) winsize 61
3053 19:26:38.226410
3054 19:26:38.229477 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3055 19:26:38.229632
3056 19:26:38.232840 [CATrainingPosCal] consider 1 rank data
3057 19:26:38.236030 u2DelayCellTimex100 = 270/100 ps
3058 19:26:38.239815 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3059 19:26:38.243355 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3060 19:26:38.249525 CA2 delay=34 (4~65),Diff = 1 PI (4 cell)
3061 19:26:38.253010 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3062 19:26:38.256103 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3063 19:26:38.259705 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3064 19:26:38.259862
3065 19:26:38.262790 CA PerBit enable=1, Macro0, CA PI delay=33
3066 19:26:38.262956
3067 19:26:38.266397 [CBTSetCACLKResult] CA Dly = 33
3068 19:26:38.266558 CS Dly: 7 (0~38)
3069 19:26:38.269301 ==
3070 19:26:38.269470 Dram Type= 6, Freq= 0, CH_1, rank 1
3071 19:26:38.276314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3072 19:26:38.276489 ==
3073 19:26:38.279660 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3074 19:26:38.286232 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3075 19:26:38.295417 [CA 0] Center 37 (7~68) winsize 62
3076 19:26:38.298167 [CA 1] Center 37 (7~68) winsize 62
3077 19:26:38.301818 [CA 2] Center 35 (5~65) winsize 61
3078 19:26:38.305155 [CA 3] Center 34 (4~65) winsize 62
3079 19:26:38.308572 [CA 4] Center 34 (4~65) winsize 62
3080 19:26:38.311826 [CA 5] Center 34 (4~64) winsize 61
3081 19:26:38.311986
3082 19:26:38.315148 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3083 19:26:38.315306
3084 19:26:38.318402 [CATrainingPosCal] consider 2 rank data
3085 19:26:38.322006 u2DelayCellTimex100 = 270/100 ps
3086 19:26:38.325231 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3087 19:26:38.328563 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3088 19:26:38.335156 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3089 19:26:38.338526 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3090 19:26:38.341863 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3091 19:26:38.345003 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3092 19:26:38.345162
3093 19:26:38.348880 CA PerBit enable=1, Macro0, CA PI delay=33
3094 19:26:38.349037
3095 19:26:38.352228 [CBTSetCACLKResult] CA Dly = 33
3096 19:26:38.352385 CS Dly: 8 (0~40)
3097 19:26:38.352530
3098 19:26:38.355494 ----->DramcWriteLeveling(PI) begin...
3099 19:26:38.358592 ==
3100 19:26:38.361703 Dram Type= 6, Freq= 0, CH_1, rank 0
3101 19:26:38.365157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3102 19:26:38.365266 ==
3103 19:26:38.368360 Write leveling (Byte 0): 26 => 26
3104 19:26:38.371598 Write leveling (Byte 1): 27 => 27
3105 19:26:38.375492 DramcWriteLeveling(PI) end<-----
3106 19:26:38.375566
3107 19:26:38.375628 ==
3108 19:26:38.378419 Dram Type= 6, Freq= 0, CH_1, rank 0
3109 19:26:38.381716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3110 19:26:38.381836 ==
3111 19:26:38.385008 [Gating] SW mode calibration
3112 19:26:38.391857 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3113 19:26:38.395272 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3114 19:26:38.401913 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3115 19:26:38.405211 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3116 19:26:38.408209 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3117 19:26:38.414956 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3118 19:26:38.418290 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3119 19:26:38.421559 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3120 19:26:38.428481 0 15 24 | B1->B0 | 3333 2929 | 1 1 | (1 0) (1 0)
3121 19:26:38.431642 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
3122 19:26:38.435133 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3123 19:26:38.441707 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3124 19:26:38.445128 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3125 19:26:38.448507 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3126 19:26:38.455545 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3127 19:26:38.458811 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3128 19:26:38.462127 1 0 24 | B1->B0 | 3030 3c3c | 0 0 | (1 1) (0 0)
3129 19:26:38.468818 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3130 19:26:38.471973 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3131 19:26:38.475273 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3132 19:26:38.478632 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3133 19:26:38.485195 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3134 19:26:38.488346 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3135 19:26:38.491923 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3136 19:26:38.498557 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3137 19:26:38.502402 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3138 19:26:38.505204 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3139 19:26:38.511870 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3140 19:26:38.515758 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3141 19:26:38.518947 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3142 19:26:38.525574 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3143 19:26:38.528864 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3144 19:26:38.532205 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3145 19:26:38.538766 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 19:26:38.542137 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 19:26:38.545611 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 19:26:38.551801 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 19:26:38.555255 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 19:26:38.558494 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 19:26:38.562430 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 19:26:38.568705 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3153 19:26:38.571965 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3154 19:26:38.575387 Total UI for P1: 0, mck2ui 16
3155 19:26:38.578723 best dqsien dly found for B0: ( 1, 3, 24)
3156 19:26:38.582376 Total UI for P1: 0, mck2ui 16
3157 19:26:38.585708 best dqsien dly found for B1: ( 1, 3, 24)
3158 19:26:38.588975 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3159 19:26:38.592408 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3160 19:26:38.592505
3161 19:26:38.595871 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3162 19:26:38.599143 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3163 19:26:38.602307 [Gating] SW calibration Done
3164 19:26:38.602394 ==
3165 19:26:38.605746 Dram Type= 6, Freq= 0, CH_1, rank 0
3166 19:26:38.608763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3167 19:26:38.612418 ==
3168 19:26:38.612537 RX Vref Scan: 0
3169 19:26:38.612660
3170 19:26:38.615513 RX Vref 0 -> 0, step: 1
3171 19:26:38.615586
3172 19:26:38.618882 RX Delay -40 -> 252, step: 8
3173 19:26:38.622189 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3174 19:26:38.625376 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3175 19:26:38.629450 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3176 19:26:38.632625 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3177 19:26:38.639105 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3178 19:26:38.642160 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3179 19:26:38.645526 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3180 19:26:38.648838 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3181 19:26:38.652219 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3182 19:26:38.655543 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3183 19:26:38.662217 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3184 19:26:38.665592 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3185 19:26:38.668917 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3186 19:26:38.672113 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3187 19:26:38.679178 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3188 19:26:38.682463 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3189 19:26:38.682537 ==
3190 19:26:38.685763 Dram Type= 6, Freq= 0, CH_1, rank 0
3191 19:26:38.688957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3192 19:26:38.689028 ==
3193 19:26:38.689089 DQS Delay:
3194 19:26:38.691949 DQS0 = 0, DQS1 = 0
3195 19:26:38.692018 DQM Delay:
3196 19:26:38.695339 DQM0 = 120, DQM1 = 116
3197 19:26:38.695415 DQ Delay:
3198 19:26:38.698641 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3199 19:26:38.701980 DQ4 =119, DQ5 =127, DQ6 =131, DQ7 =123
3200 19:26:38.705418 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3201 19:26:38.712483 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3202 19:26:38.712581
3203 19:26:38.712675
3204 19:26:38.712792 ==
3205 19:26:38.715694 Dram Type= 6, Freq= 0, CH_1, rank 0
3206 19:26:38.718984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3207 19:26:38.719083 ==
3208 19:26:38.719173
3209 19:26:38.719258
3210 19:26:38.722117 TX Vref Scan disable
3211 19:26:38.722213 == TX Byte 0 ==
3212 19:26:38.728887 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3213 19:26:38.732382 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3214 19:26:38.732484 == TX Byte 1 ==
3215 19:26:38.738630 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3216 19:26:38.741947 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3217 19:26:38.742036 ==
3218 19:26:38.745715 Dram Type= 6, Freq= 0, CH_1, rank 0
3219 19:26:38.748767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3220 19:26:38.748872 ==
3221 19:26:38.761280 TX Vref=22, minBit 9, minWin=24, winSum=410
3222 19:26:38.764710 TX Vref=24, minBit 11, minWin=25, winSum=420
3223 19:26:38.767949 TX Vref=26, minBit 12, minWin=25, winSum=426
3224 19:26:38.770696 TX Vref=28, minBit 9, minWin=25, winSum=427
3225 19:26:38.774167 TX Vref=30, minBit 1, minWin=26, winSum=430
3226 19:26:38.780703 TX Vref=32, minBit 2, minWin=26, winSum=430
3227 19:26:38.784608 [TxChooseVref] Worse bit 1, Min win 26, Win sum 430, Final Vref 30
3228 19:26:38.784707
3229 19:26:38.787766 Final TX Range 1 Vref 30
3230 19:26:38.787835
3231 19:26:38.787894 ==
3232 19:26:38.791064 Dram Type= 6, Freq= 0, CH_1, rank 0
3233 19:26:38.794518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3234 19:26:38.794591 ==
3235 19:26:38.797798
3236 19:26:38.797868
3237 19:26:38.797964 TX Vref Scan disable
3238 19:26:38.800964 == TX Byte 0 ==
3239 19:26:38.804117 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3240 19:26:38.807461 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3241 19:26:38.810807 == TX Byte 1 ==
3242 19:26:38.814210 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3243 19:26:38.817444 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3244 19:26:38.817534
3245 19:26:38.821346 [DATLAT]
3246 19:26:38.821419 Freq=1200, CH1 RK0
3247 19:26:38.821494
3248 19:26:38.824658 DATLAT Default: 0xd
3249 19:26:38.824756 0, 0xFFFF, sum = 0
3250 19:26:38.828185 1, 0xFFFF, sum = 0
3251 19:26:38.828285 2, 0xFFFF, sum = 0
3252 19:26:38.830788 3, 0xFFFF, sum = 0
3253 19:26:38.830893 4, 0xFFFF, sum = 0
3254 19:26:38.834157 5, 0xFFFF, sum = 0
3255 19:26:38.834269 6, 0xFFFF, sum = 0
3256 19:26:38.837787 7, 0xFFFF, sum = 0
3257 19:26:38.837895 8, 0xFFFF, sum = 0
3258 19:26:38.840938 9, 0xFFFF, sum = 0
3259 19:26:38.844390 10, 0xFFFF, sum = 0
3260 19:26:38.844501 11, 0xFFFF, sum = 0
3261 19:26:38.847679 12, 0x0, sum = 1
3262 19:26:38.847778 13, 0x0, sum = 2
3263 19:26:38.847876 14, 0x0, sum = 3
3264 19:26:38.851202 15, 0x0, sum = 4
3265 19:26:38.851287 best_step = 13
3266 19:26:38.851353
3267 19:26:38.854280 ==
3268 19:26:38.854421 Dram Type= 6, Freq= 0, CH_1, rank 0
3269 19:26:38.861413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3270 19:26:38.861513 ==
3271 19:26:38.861591 RX Vref Scan: 1
3272 19:26:38.861678
3273 19:26:38.864458 Set Vref Range= 32 -> 127
3274 19:26:38.864554
3275 19:26:38.867715 RX Vref 32 -> 127, step: 1
3276 19:26:38.867818
3277 19:26:38.871183 RX Delay -5 -> 252, step: 4
3278 19:26:38.871260
3279 19:26:38.874544 Set Vref, RX VrefLevel [Byte0]: 32
3280 19:26:38.877966 [Byte1]: 32
3281 19:26:38.878061
3282 19:26:38.881379 Set Vref, RX VrefLevel [Byte0]: 33
3283 19:26:38.884649 [Byte1]: 33
3284 19:26:38.884748
3285 19:26:38.887885 Set Vref, RX VrefLevel [Byte0]: 34
3286 19:26:38.891189 [Byte1]: 34
3287 19:26:38.894853
3288 19:26:38.894930 Set Vref, RX VrefLevel [Byte0]: 35
3289 19:26:38.898180 [Byte1]: 35
3290 19:26:38.903027
3291 19:26:38.903135 Set Vref, RX VrefLevel [Byte0]: 36
3292 19:26:38.906383 [Byte1]: 36
3293 19:26:38.910711
3294 19:26:38.910786 Set Vref, RX VrefLevel [Byte0]: 37
3295 19:26:38.914020 [Byte1]: 37
3296 19:26:38.918870
3297 19:26:38.918954 Set Vref, RX VrefLevel [Byte0]: 38
3298 19:26:38.921544 [Byte1]: 38
3299 19:26:38.926690
3300 19:26:38.926762 Set Vref, RX VrefLevel [Byte0]: 39
3301 19:26:38.929712 [Byte1]: 39
3302 19:26:38.934529
3303 19:26:38.934603 Set Vref, RX VrefLevel [Byte0]: 40
3304 19:26:38.937222 [Byte1]: 40
3305 19:26:38.941939
3306 19:26:38.942036 Set Vref, RX VrefLevel [Byte0]: 41
3307 19:26:38.945379 [Byte1]: 41
3308 19:26:38.949855
3309 19:26:38.949954 Set Vref, RX VrefLevel [Byte0]: 42
3310 19:26:38.953177 [Byte1]: 42
3311 19:26:38.957447
3312 19:26:38.957519 Set Vref, RX VrefLevel [Byte0]: 43
3313 19:26:38.960971 [Byte1]: 43
3314 19:26:38.965700
3315 19:26:38.965811 Set Vref, RX VrefLevel [Byte0]: 44
3316 19:26:38.968691 [Byte1]: 44
3317 19:26:38.973190
3318 19:26:38.973301 Set Vref, RX VrefLevel [Byte0]: 45
3319 19:26:38.976852 [Byte1]: 45
3320 19:26:38.981237
3321 19:26:38.981333 Set Vref, RX VrefLevel [Byte0]: 46
3322 19:26:38.984628 [Byte1]: 46
3323 19:26:38.988949
3324 19:26:38.989083 Set Vref, RX VrefLevel [Byte0]: 47
3325 19:26:38.992494 [Byte1]: 47
3326 19:26:38.997134
3327 19:26:38.997250 Set Vref, RX VrefLevel [Byte0]: 48
3328 19:26:39.000030 [Byte1]: 48
3329 19:26:39.004753
3330 19:26:39.004856 Set Vref, RX VrefLevel [Byte0]: 49
3331 19:26:39.007949 [Byte1]: 49
3332 19:26:39.012913
3333 19:26:39.013016 Set Vref, RX VrefLevel [Byte0]: 50
3334 19:26:39.016112 [Byte1]: 50
3335 19:26:39.020672
3336 19:26:39.020786 Set Vref, RX VrefLevel [Byte0]: 51
3337 19:26:39.023456 [Byte1]: 51
3338 19:26:39.028251
3339 19:26:39.028352 Set Vref, RX VrefLevel [Byte0]: 52
3340 19:26:39.031655 [Byte1]: 52
3341 19:26:39.036327
3342 19:26:39.036426 Set Vref, RX VrefLevel [Byte0]: 53
3343 19:26:39.039812 [Byte1]: 53
3344 19:26:39.043869
3345 19:26:39.044044 Set Vref, RX VrefLevel [Byte0]: 54
3346 19:26:39.047302 [Byte1]: 54
3347 19:26:39.052101
3348 19:26:39.052198 Set Vref, RX VrefLevel [Byte0]: 55
3349 19:26:39.054875 [Byte1]: 55
3350 19:26:39.059633
3351 19:26:39.059708 Set Vref, RX VrefLevel [Byte0]: 56
3352 19:26:39.063025 [Byte1]: 56
3353 19:26:39.067844
3354 19:26:39.067944 Set Vref, RX VrefLevel [Byte0]: 57
3355 19:26:39.070991 [Byte1]: 57
3356 19:26:39.075518
3357 19:26:39.075695 Set Vref, RX VrefLevel [Byte0]: 58
3358 19:26:39.078467 [Byte1]: 58
3359 19:26:39.083235
3360 19:26:39.083339 Set Vref, RX VrefLevel [Byte0]: 59
3361 19:26:39.086286 [Byte1]: 59
3362 19:26:39.090845
3363 19:26:39.090979 Set Vref, RX VrefLevel [Byte0]: 60
3364 19:26:39.094212 [Byte1]: 60
3365 19:26:39.099049
3366 19:26:39.099133 Set Vref, RX VrefLevel [Byte0]: 61
3367 19:26:39.102452 [Byte1]: 61
3368 19:26:39.106565
3369 19:26:39.106646 Set Vref, RX VrefLevel [Byte0]: 62
3370 19:26:39.109781 [Byte1]: 62
3371 19:26:39.114496
3372 19:26:39.114600 Set Vref, RX VrefLevel [Byte0]: 63
3373 19:26:39.117686 [Byte1]: 63
3374 19:26:39.122517
3375 19:26:39.122623 Set Vref, RX VrefLevel [Byte0]: 64
3376 19:26:39.125741 [Byte1]: 64
3377 19:26:39.130482
3378 19:26:39.130558 Set Vref, RX VrefLevel [Byte0]: 65
3379 19:26:39.133864 [Byte1]: 65
3380 19:26:39.138611
3381 19:26:39.138684 Set Vref, RX VrefLevel [Byte0]: 66
3382 19:26:39.141948 [Byte1]: 66
3383 19:26:39.145870
3384 19:26:39.145947 Set Vref, RX VrefLevel [Byte0]: 67
3385 19:26:39.149420 [Byte1]: 67
3386 19:26:39.154134
3387 19:26:39.154236 Set Vref, RX VrefLevel [Byte0]: 68
3388 19:26:39.157607 [Byte1]: 68
3389 19:26:39.161696
3390 19:26:39.161772 Final RX Vref Byte 0 = 54 to rank0
3391 19:26:39.165179 Final RX Vref Byte 1 = 54 to rank0
3392 19:26:39.168494 Final RX Vref Byte 0 = 54 to rank1
3393 19:26:39.172118 Final RX Vref Byte 1 = 54 to rank1==
3394 19:26:39.174879 Dram Type= 6, Freq= 0, CH_1, rank 0
3395 19:26:39.181837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3396 19:26:39.181939 ==
3397 19:26:39.182034 DQS Delay:
3398 19:26:39.182122 DQS0 = 0, DQS1 = 0
3399 19:26:39.185248 DQM Delay:
3400 19:26:39.185348 DQM0 = 120, DQM1 = 117
3401 19:26:39.188463 DQ Delay:
3402 19:26:39.191859 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =118
3403 19:26:39.195178 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =120
3404 19:26:39.198569 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =112
3405 19:26:39.201905 DQ12 =124, DQ13 =124, DQ14 =124, DQ15 =126
3406 19:26:39.202009
3407 19:26:39.202102
3408 19:26:39.208213 [DQSOSCAuto] RK0, (LSB)MR18= 0x114, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 409 ps
3409 19:26:39.211472 CH1 RK0: MR19=404, MR18=114
3410 19:26:39.218655 CH1_RK0: MR19=0x404, MR18=0x114, DQSOSC=402, MR23=63, INC=40, DEC=27
3411 19:26:39.218768
3412 19:26:39.221763 ----->DramcWriteLeveling(PI) begin...
3413 19:26:39.221843 ==
3414 19:26:39.224583 Dram Type= 6, Freq= 0, CH_1, rank 1
3415 19:26:39.228311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3416 19:26:39.231440 ==
3417 19:26:39.231546 Write leveling (Byte 0): 27 => 27
3418 19:26:39.234507 Write leveling (Byte 1): 28 => 28
3419 19:26:39.238434 DramcWriteLeveling(PI) end<-----
3420 19:26:39.238516
3421 19:26:39.238580 ==
3422 19:26:39.242741 Dram Type= 6, Freq= 0, CH_1, rank 1
3423 19:26:39.248336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3424 19:26:39.248429 ==
3425 19:26:39.251492 [Gating] SW mode calibration
3426 19:26:39.258154 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3427 19:26:39.261648 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3428 19:26:39.267768 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3429 19:26:39.271105 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3430 19:26:39.274710 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3431 19:26:39.281634 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3432 19:26:39.284423 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3433 19:26:39.287934 0 15 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3434 19:26:39.291211 0 15 24 | B1->B0 | 2727 3232 | 0 1 | (1 0) (1 0)
3435 19:26:39.297781 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3436 19:26:39.301260 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3437 19:26:39.304699 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3438 19:26:39.310799 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3439 19:26:39.314203 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3440 19:26:39.317448 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3441 19:26:39.324479 1 0 20 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
3442 19:26:39.327814 1 0 24 | B1->B0 | 4444 2b2b | 0 0 | (0 0) (1 1)
3443 19:26:39.330971 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3444 19:26:39.337951 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3445 19:26:39.341274 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3446 19:26:39.344022 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3447 19:26:39.350606 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3448 19:26:39.354507 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3449 19:26:39.357648 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3450 19:26:39.364248 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3451 19:26:39.367480 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3452 19:26:39.370885 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3453 19:26:39.377382 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3454 19:26:39.380561 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3455 19:26:39.384007 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3456 19:26:39.390805 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3457 19:26:39.394279 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3458 19:26:39.397557 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3459 19:26:39.403801 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3460 19:26:39.407273 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3461 19:26:39.410669 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 19:26:39.417110 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 19:26:39.420445 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 19:26:39.423683 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 19:26:39.430734 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3466 19:26:39.433982 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3467 19:26:39.437256 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3468 19:26:39.440490 Total UI for P1: 0, mck2ui 16
3469 19:26:39.443564 best dqsien dly found for B1: ( 1, 3, 22)
3470 19:26:39.450578 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3471 19:26:39.450654 Total UI for P1: 0, mck2ui 16
3472 19:26:39.454047 best dqsien dly found for B0: ( 1, 3, 26)
3473 19:26:39.460240 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3474 19:26:39.463634 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3475 19:26:39.463700
3476 19:26:39.466906 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3477 19:26:39.470427 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3478 19:26:39.473556 [Gating] SW calibration Done
3479 19:26:39.473623 ==
3480 19:26:39.477272 Dram Type= 6, Freq= 0, CH_1, rank 1
3481 19:26:39.480433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3482 19:26:39.480507 ==
3483 19:26:39.480567 RX Vref Scan: 0
3484 19:26:39.483631
3485 19:26:39.483696 RX Vref 0 -> 0, step: 1
3486 19:26:39.483752
3487 19:26:39.487364 RX Delay -40 -> 252, step: 8
3488 19:26:39.490417 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3489 19:26:39.493773 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3490 19:26:39.500541 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3491 19:26:39.503822 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3492 19:26:39.507101 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3493 19:26:39.510297 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3494 19:26:39.513420 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3495 19:26:39.520130 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3496 19:26:39.523595 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3497 19:26:39.526787 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3498 19:26:39.530099 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3499 19:26:39.533382 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3500 19:26:39.540328 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3501 19:26:39.543736 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3502 19:26:39.546505 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3503 19:26:39.550282 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3504 19:26:39.550375 ==
3505 19:26:39.553191 Dram Type= 6, Freq= 0, CH_1, rank 1
3506 19:26:39.559887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3507 19:26:39.559961 ==
3508 19:26:39.560022 DQS Delay:
3509 19:26:39.563030 DQS0 = 0, DQS1 = 0
3510 19:26:39.563096 DQM Delay:
3511 19:26:39.566876 DQM0 = 119, DQM1 = 117
3512 19:26:39.566942 DQ Delay:
3513 19:26:39.569562 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =115
3514 19:26:39.573127 DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =119
3515 19:26:39.576673 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =115
3516 19:26:39.579578 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3517 19:26:39.579644
3518 19:26:39.579702
3519 19:26:39.579798 ==
3520 19:26:39.582831 Dram Type= 6, Freq= 0, CH_1, rank 1
3521 19:26:39.589839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3522 19:26:39.589941 ==
3523 19:26:39.590032
3524 19:26:39.590117
3525 19:26:39.590203 TX Vref Scan disable
3526 19:26:39.593203 == TX Byte 0 ==
3527 19:26:39.596575 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3528 19:26:39.599850 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3529 19:26:39.603059 == TX Byte 1 ==
3530 19:26:39.606316 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3531 19:26:39.613150 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3532 19:26:39.613251 ==
3533 19:26:39.616548 Dram Type= 6, Freq= 0, CH_1, rank 1
3534 19:26:39.619826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3535 19:26:39.619925 ==
3536 19:26:39.630549 TX Vref=22, minBit 1, minWin=25, winSum=420
3537 19:26:39.633890 TX Vref=24, minBit 10, minWin=25, winSum=424
3538 19:26:39.637279 TX Vref=26, minBit 2, minWin=26, winSum=429
3539 19:26:39.640974 TX Vref=28, minBit 2, minWin=26, winSum=430
3540 19:26:39.644193 TX Vref=30, minBit 9, minWin=26, winSum=434
3541 19:26:39.650780 TX Vref=32, minBit 9, minWin=26, winSum=431
3542 19:26:39.654206 [TxChooseVref] Worse bit 9, Min win 26, Win sum 434, Final Vref 30
3543 19:26:39.654331
3544 19:26:39.657720 Final TX Range 1 Vref 30
3545 19:26:39.657795
3546 19:26:39.657858 ==
3547 19:26:39.661004 Dram Type= 6, Freq= 0, CH_1, rank 1
3548 19:26:39.664340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3549 19:26:39.664437 ==
3550 19:26:39.667443
3551 19:26:39.667514
3552 19:26:39.667576 TX Vref Scan disable
3553 19:26:39.670407 == TX Byte 0 ==
3554 19:26:39.673812 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3555 19:26:39.677531 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3556 19:26:39.680898 == TX Byte 1 ==
3557 19:26:39.683707 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3558 19:26:39.690937 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3559 19:26:39.691008
3560 19:26:39.691069 [DATLAT]
3561 19:26:39.691130 Freq=1200, CH1 RK1
3562 19:26:39.691189
3563 19:26:39.694019 DATLAT Default: 0xd
3564 19:26:39.694115 0, 0xFFFF, sum = 0
3565 19:26:39.697483 1, 0xFFFF, sum = 0
3566 19:26:39.697580 2, 0xFFFF, sum = 0
3567 19:26:39.700807 3, 0xFFFF, sum = 0
3568 19:26:39.704145 4, 0xFFFF, sum = 0
3569 19:26:39.704247 5, 0xFFFF, sum = 0
3570 19:26:39.707408 6, 0xFFFF, sum = 0
3571 19:26:39.707508 7, 0xFFFF, sum = 0
3572 19:26:39.710802 8, 0xFFFF, sum = 0
3573 19:26:39.710885 9, 0xFFFF, sum = 0
3574 19:26:39.714223 10, 0xFFFF, sum = 0
3575 19:26:39.714340 11, 0xFFFF, sum = 0
3576 19:26:39.717576 12, 0x0, sum = 1
3577 19:26:39.717649 13, 0x0, sum = 2
3578 19:26:39.720316 14, 0x0, sum = 3
3579 19:26:39.720388 15, 0x0, sum = 4
3580 19:26:39.720449 best_step = 13
3581 19:26:39.723663
3582 19:26:39.723762 ==
3583 19:26:39.726808 Dram Type= 6, Freq= 0, CH_1, rank 1
3584 19:26:39.730568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3585 19:26:39.730666 ==
3586 19:26:39.730757 RX Vref Scan: 0
3587 19:26:39.730843
3588 19:26:39.733628 RX Vref 0 -> 0, step: 1
3589 19:26:39.733697
3590 19:26:39.736750 RX Delay -5 -> 252, step: 4
3591 19:26:39.740287 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3592 19:26:39.747023 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3593 19:26:39.750292 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3594 19:26:39.753568 iDelay=195, Bit 3, Center 116 (59 ~ 174) 116
3595 19:26:39.756986 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3596 19:26:39.760457 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3597 19:26:39.767030 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3598 19:26:39.770427 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3599 19:26:39.773795 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3600 19:26:39.777164 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3601 19:26:39.780321 iDelay=195, Bit 10, Center 118 (59 ~ 178) 120
3602 19:26:39.786820 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3603 19:26:39.790510 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3604 19:26:39.793814 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3605 19:26:39.797081 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3606 19:26:39.800365 iDelay=195, Bit 15, Center 126 (67 ~ 186) 120
3607 19:26:39.803834 ==
3608 19:26:39.807208 Dram Type= 6, Freq= 0, CH_1, rank 1
3609 19:26:39.810563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3610 19:26:39.810640 ==
3611 19:26:39.810704 DQS Delay:
3612 19:26:39.813804 DQS0 = 0, DQS1 = 0
3613 19:26:39.813872 DQM Delay:
3614 19:26:39.816494 DQM0 = 120, DQM1 = 118
3615 19:26:39.816576 DQ Delay:
3616 19:26:39.819863 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3617 19:26:39.823200 DQ4 =116, DQ5 =130, DQ6 =130, DQ7 =120
3618 19:26:39.826572 DQ8 =106, DQ9 =108, DQ10 =118, DQ11 =112
3619 19:26:39.829848 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =126
3620 19:26:39.829929
3621 19:26:39.829993
3622 19:26:39.840042 [DQSOSCAuto] RK1, (LSB)MR18= 0x13f0, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 402 ps
3623 19:26:39.842719 CH1 RK1: MR19=403, MR18=13F0
3624 19:26:39.846630 CH1_RK1: MR19=0x403, MR18=0x13F0, DQSOSC=402, MR23=63, INC=40, DEC=27
3625 19:26:39.849383 [RxdqsGatingPostProcess] freq 1200
3626 19:26:39.855983 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3627 19:26:39.859799 best DQS0 dly(2T, 0.5T) = (0, 11)
3628 19:26:39.863008 best DQS1 dly(2T, 0.5T) = (0, 11)
3629 19:26:39.866079 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3630 19:26:39.869474 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3631 19:26:39.872838 best DQS0 dly(2T, 0.5T) = (0, 11)
3632 19:26:39.875987 best DQS1 dly(2T, 0.5T) = (0, 11)
3633 19:26:39.879269 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3634 19:26:39.882820 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3635 19:26:39.886172 Pre-setting of DQS Precalculation
3636 19:26:39.889323 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3637 19:26:39.895647 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3638 19:26:39.905707 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3639 19:26:39.905823
3640 19:26:39.905891
3641 19:26:39.909181 [Calibration Summary] 2400 Mbps
3642 19:26:39.909276 CH 0, Rank 0
3643 19:26:39.912421 SW Impedance : PASS
3644 19:26:39.912502 DUTY Scan : NO K
3645 19:26:39.915697 ZQ Calibration : PASS
3646 19:26:39.915778 Jitter Meter : NO K
3647 19:26:39.919176 CBT Training : PASS
3648 19:26:39.922516 Write leveling : PASS
3649 19:26:39.922597 RX DQS gating : PASS
3650 19:26:39.925855 RX DQ/DQS(RDDQC) : PASS
3651 19:26:39.929173 TX DQ/DQS : PASS
3652 19:26:39.929254 RX DATLAT : PASS
3653 19:26:39.932630 RX DQ/DQS(Engine): PASS
3654 19:26:39.935428 TX OE : NO K
3655 19:26:39.935509 All Pass.
3656 19:26:39.935573
3657 19:26:39.935633 CH 0, Rank 1
3658 19:26:39.938813 SW Impedance : PASS
3659 19:26:39.942263 DUTY Scan : NO K
3660 19:26:39.942378 ZQ Calibration : PASS
3661 19:26:39.945546 Jitter Meter : NO K
3662 19:26:39.948886 CBT Training : PASS
3663 19:26:39.948966 Write leveling : PASS
3664 19:26:39.952012 RX DQS gating : PASS
3665 19:26:39.955160 RX DQ/DQS(RDDQC) : PASS
3666 19:26:39.955240 TX DQ/DQS : PASS
3667 19:26:39.958955 RX DATLAT : PASS
3668 19:26:39.962454 RX DQ/DQS(Engine): PASS
3669 19:26:39.962535 TX OE : NO K
3670 19:26:39.962600 All Pass.
3671 19:26:39.965226
3672 19:26:39.965305 CH 1, Rank 0
3673 19:26:39.968616 SW Impedance : PASS
3674 19:26:39.968696 DUTY Scan : NO K
3675 19:26:39.971982 ZQ Calibration : PASS
3676 19:26:39.972063 Jitter Meter : NO K
3677 19:26:39.975419 CBT Training : PASS
3678 19:26:39.978719 Write leveling : PASS
3679 19:26:39.978800 RX DQS gating : PASS
3680 19:26:39.981961 RX DQ/DQS(RDDQC) : PASS
3681 19:26:39.985151 TX DQ/DQS : PASS
3682 19:26:39.985232 RX DATLAT : PASS
3683 19:26:39.988730 RX DQ/DQS(Engine): PASS
3684 19:26:39.992163 TX OE : NO K
3685 19:26:39.992245 All Pass.
3686 19:26:39.992310
3687 19:26:39.992371 CH 1, Rank 1
3688 19:26:39.995445 SW Impedance : PASS
3689 19:26:39.998689 DUTY Scan : NO K
3690 19:26:39.998769 ZQ Calibration : PASS
3691 19:26:40.001764 Jitter Meter : NO K
3692 19:26:40.005006 CBT Training : PASS
3693 19:26:40.005086 Write leveling : PASS
3694 19:26:40.008544 RX DQS gating : PASS
3695 19:26:40.011678 RX DQ/DQS(RDDQC) : PASS
3696 19:26:40.011759 TX DQ/DQS : PASS
3697 19:26:40.015526 RX DATLAT : PASS
3698 19:26:40.015607 RX DQ/DQS(Engine): PASS
3699 19:26:40.018447 TX OE : NO K
3700 19:26:40.018528 All Pass.
3701 19:26:40.018593
3702 19:26:40.021958 DramC Write-DBI off
3703 19:26:40.025183 PER_BANK_REFRESH: Hybrid Mode
3704 19:26:40.025263 TX_TRACKING: ON
3705 19:26:40.035252 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3706 19:26:40.038627 [FAST_K] Save calibration result to emmc
3707 19:26:40.042059 dramc_set_vcore_voltage set vcore to 650000
3708 19:26:40.045355 Read voltage for 600, 5
3709 19:26:40.045436 Vio18 = 0
3710 19:26:40.048738 Vcore = 650000
3711 19:26:40.048818 Vdram = 0
3712 19:26:40.048881 Vddq = 0
3713 19:26:40.048940 Vmddr = 0
3714 19:26:40.055454 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3715 19:26:40.061676 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3716 19:26:40.061758 MEM_TYPE=3, freq_sel=19
3717 19:26:40.065267 sv_algorithm_assistance_LP4_1600
3718 19:26:40.068537 ============ PULL DRAM RESETB DOWN ============
3719 19:26:40.075317 ========== PULL DRAM RESETB DOWN end =========
3720 19:26:40.078631 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3721 19:26:40.082243 ===================================
3722 19:26:40.084819 LPDDR4 DRAM CONFIGURATION
3723 19:26:40.088173 ===================================
3724 19:26:40.088254 EX_ROW_EN[0] = 0x0
3725 19:26:40.091608 EX_ROW_EN[1] = 0x0
3726 19:26:40.091688 LP4Y_EN = 0x0
3727 19:26:40.094899 WORK_FSP = 0x0
3728 19:26:40.094979 WL = 0x2
3729 19:26:40.098408 RL = 0x2
3730 19:26:40.098488 BL = 0x2
3731 19:26:40.101756 RPST = 0x0
3732 19:26:40.101836 RD_PRE = 0x0
3733 19:26:40.104935 WR_PRE = 0x1
3734 19:26:40.105015 WR_PST = 0x0
3735 19:26:40.108636 DBI_WR = 0x0
3736 19:26:40.134279 DBI_RD = 0x0
3737 19:26:40.134417 OTF = 0x1
3738 19:26:40.134498 ===================================
3739 19:26:40.134575 ===================================
3740 19:26:40.134649 ANA top config
3741 19:26:40.134705 ===================================
3742 19:26:40.134761 DLL_ASYNC_EN = 0
3743 19:26:40.134830 ALL_SLAVE_EN = 1
3744 19:26:40.134886 NEW_RANK_MODE = 1
3745 19:26:40.135132 DLL_IDLE_MODE = 1
3746 19:26:40.135194 LP45_APHY_COMB_EN = 1
3747 19:26:40.138208 TX_ODT_DIS = 1
3748 19:26:40.141250 NEW_8X_MODE = 1
3749 19:26:40.145152 ===================================
3750 19:26:40.148280 ===================================
3751 19:26:40.151564 data_rate = 1200
3752 19:26:40.154557 CKR = 1
3753 19:26:40.154639 DQ_P2S_RATIO = 8
3754 19:26:40.157813 ===================================
3755 19:26:40.161528 CA_P2S_RATIO = 8
3756 19:26:40.164956 DQ_CA_OPEN = 0
3757 19:26:40.167651 DQ_SEMI_OPEN = 0
3758 19:26:40.170997 CA_SEMI_OPEN = 0
3759 19:26:40.174843 CA_FULL_RATE = 0
3760 19:26:40.174924 DQ_CKDIV4_EN = 1
3761 19:26:40.178026 CA_CKDIV4_EN = 1
3762 19:26:40.181476 CA_PREDIV_EN = 0
3763 19:26:40.184247 PH8_DLY = 0
3764 19:26:40.187682 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3765 19:26:40.191141 DQ_AAMCK_DIV = 4
3766 19:26:40.191221 CA_AAMCK_DIV = 4
3767 19:26:40.194513 CA_ADMCK_DIV = 4
3768 19:26:40.197814 DQ_TRACK_CA_EN = 0
3769 19:26:40.201168 CA_PICK = 600
3770 19:26:40.204644 CA_MCKIO = 600
3771 19:26:40.208043 MCKIO_SEMI = 0
3772 19:26:40.210755 PLL_FREQ = 2288
3773 19:26:40.210828 DQ_UI_PI_RATIO = 32
3774 19:26:40.214249 CA_UI_PI_RATIO = 0
3775 19:26:40.217520 ===================================
3776 19:26:40.220916 ===================================
3777 19:26:40.224235 memory_type:LPDDR4
3778 19:26:40.227411 GP_NUM : 10
3779 19:26:40.227491 SRAM_EN : 1
3780 19:26:40.231287 MD32_EN : 0
3781 19:26:40.234541 ===================================
3782 19:26:40.237590 [ANA_INIT] >>>>>>>>>>>>>>
3783 19:26:40.237671 <<<<<< [CONFIGURE PHASE]: ANA_TX
3784 19:26:40.241266 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3785 19:26:40.244296 ===================================
3786 19:26:40.247919 data_rate = 1200,PCW = 0X5800
3787 19:26:40.251136 ===================================
3788 19:26:40.254439 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3789 19:26:40.260723 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3790 19:26:40.267657 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3791 19:26:40.270687 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3792 19:26:40.274023 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3793 19:26:40.277745 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3794 19:26:40.281184 [ANA_INIT] flow start
3795 19:26:40.281283 [ANA_INIT] PLL >>>>>>>>
3796 19:26:40.284217 [ANA_INIT] PLL <<<<<<<<
3797 19:26:40.287774 [ANA_INIT] MIDPI >>>>>>>>
3798 19:26:40.287844 [ANA_INIT] MIDPI <<<<<<<<
3799 19:26:40.291103 [ANA_INIT] DLL >>>>>>>>
3800 19:26:40.293934 [ANA_INIT] flow end
3801 19:26:40.297729 ============ LP4 DIFF to SE enter ============
3802 19:26:40.300424 ============ LP4 DIFF to SE exit ============
3803 19:26:40.303796 [ANA_INIT] <<<<<<<<<<<<<
3804 19:26:40.307229 [Flow] Enable top DCM control >>>>>
3805 19:26:40.310525 [Flow] Enable top DCM control <<<<<
3806 19:26:40.313970 Enable DLL master slave shuffle
3807 19:26:40.317456 ==============================================================
3808 19:26:40.320215 Gating Mode config
3809 19:26:40.326950 ==============================================================
3810 19:26:40.327068 Config description:
3811 19:26:40.337614 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3812 19:26:40.343640 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3813 19:26:40.350489 SELPH_MODE 0: By rank 1: By Phase
3814 19:26:40.353648 ==============================================================
3815 19:26:40.357424 GAT_TRACK_EN = 1
3816 19:26:40.360518 RX_GATING_MODE = 2
3817 19:26:40.363674 RX_GATING_TRACK_MODE = 2
3818 19:26:40.367022 SELPH_MODE = 1
3819 19:26:40.370246 PICG_EARLY_EN = 1
3820 19:26:40.373557 VALID_LAT_VALUE = 1
3821 19:26:40.376842 ==============================================================
3822 19:26:40.379982 Enter into Gating configuration >>>>
3823 19:26:40.383239 Exit from Gating configuration <<<<
3824 19:26:40.387165 Enter into DVFS_PRE_config >>>>>
3825 19:26:40.400021 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3826 19:26:40.403278 Exit from DVFS_PRE_config <<<<<
3827 19:26:40.406675 Enter into PICG configuration >>>>
3828 19:26:40.409750 Exit from PICG configuration <<<<
3829 19:26:40.409904 [RX_INPUT] configuration >>>>>
3830 19:26:40.413414 [RX_INPUT] configuration <<<<<
3831 19:26:40.419627 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3832 19:26:40.422996 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3833 19:26:40.429780 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3834 19:26:40.436323 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3835 19:26:40.443005 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3836 19:26:40.449714 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3837 19:26:40.452991 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3838 19:26:40.455895 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3839 19:26:40.462808 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3840 19:26:40.466197 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3841 19:26:40.469345 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3842 19:26:40.473036 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3843 19:26:40.476271 ===================================
3844 19:26:40.479651 LPDDR4 DRAM CONFIGURATION
3845 19:26:40.482826 ===================================
3846 19:26:40.485996 EX_ROW_EN[0] = 0x0
3847 19:26:40.486096 EX_ROW_EN[1] = 0x0
3848 19:26:40.489149 LP4Y_EN = 0x0
3849 19:26:40.489258 WORK_FSP = 0x0
3850 19:26:40.492461 WL = 0x2
3851 19:26:40.492561 RL = 0x2
3852 19:26:40.496208 BL = 0x2
3853 19:26:40.496311 RPST = 0x0
3854 19:26:40.499525 RD_PRE = 0x0
3855 19:26:40.499636 WR_PRE = 0x1
3856 19:26:40.502828 WR_PST = 0x0
3857 19:26:40.502903 DBI_WR = 0x0
3858 19:26:40.506262 DBI_RD = 0x0
3859 19:26:40.509094 OTF = 0x1
3860 19:26:40.509197 ===================================
3861 19:26:40.515896 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3862 19:26:40.519145 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3863 19:26:40.522819 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3864 19:26:40.525836 ===================================
3865 19:26:40.529243 LPDDR4 DRAM CONFIGURATION
3866 19:26:40.532470 ===================================
3867 19:26:40.536321 EX_ROW_EN[0] = 0x10
3868 19:26:40.536433 EX_ROW_EN[1] = 0x0
3869 19:26:40.539652 LP4Y_EN = 0x0
3870 19:26:40.539731 WORK_FSP = 0x0
3871 19:26:40.542817 WL = 0x2
3872 19:26:40.542926 RL = 0x2
3873 19:26:40.546169 BL = 0x2
3874 19:26:40.546276 RPST = 0x0
3875 19:26:40.549482 RD_PRE = 0x0
3876 19:26:40.549585 WR_PRE = 0x1
3877 19:26:40.552264 WR_PST = 0x0
3878 19:26:40.552368 DBI_WR = 0x0
3879 19:26:40.556256 DBI_RD = 0x0
3880 19:26:40.556364 OTF = 0x1
3881 19:26:40.559586 ===================================
3882 19:26:40.565882 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3883 19:26:40.570734 nWR fixed to 30
3884 19:26:40.574079 [ModeRegInit_LP4] CH0 RK0
3885 19:26:40.574168 [ModeRegInit_LP4] CH0 RK1
3886 19:26:40.577313 [ModeRegInit_LP4] CH1 RK0
3887 19:26:40.580441 [ModeRegInit_LP4] CH1 RK1
3888 19:26:40.580524 match AC timing 17
3889 19:26:40.587274 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3890 19:26:40.590585 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3891 19:26:40.593736 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3892 19:26:40.600955 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3893 19:26:40.604070 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3894 19:26:40.604155 ==
3895 19:26:40.607547 Dram Type= 6, Freq= 0, CH_0, rank 0
3896 19:26:40.610913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3897 19:26:40.610997 ==
3898 19:26:40.616928 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3899 19:26:40.623720 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3900 19:26:40.627171 [CA 0] Center 35 (5~66) winsize 62
3901 19:26:40.630362 [CA 1] Center 35 (5~66) winsize 62
3902 19:26:40.633619 [CA 2] Center 34 (3~65) winsize 63
3903 19:26:40.636898 [CA 3] Center 33 (3~64) winsize 62
3904 19:26:40.640713 [CA 4] Center 33 (2~64) winsize 63
3905 19:26:40.643712 [CA 5] Center 32 (2~63) winsize 62
3906 19:26:40.643802
3907 19:26:40.646811 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3908 19:26:40.646894
3909 19:26:40.650124 [CATrainingPosCal] consider 1 rank data
3910 19:26:40.653652 u2DelayCellTimex100 = 270/100 ps
3911 19:26:40.656940 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3912 19:26:40.660464 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3913 19:26:40.663163 CA2 delay=34 (3~65),Diff = 2 PI (19 cell)
3914 19:26:40.666948 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3915 19:26:40.670222 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3916 19:26:40.676894 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3917 19:26:40.677006
3918 19:26:40.679618 CA PerBit enable=1, Macro0, CA PI delay=32
3919 19:26:40.679702
3920 19:26:40.683604 [CBTSetCACLKResult] CA Dly = 32
3921 19:26:40.683687 CS Dly: 4 (0~35)
3922 19:26:40.683754 ==
3923 19:26:40.686371 Dram Type= 6, Freq= 0, CH_0, rank 1
3924 19:26:40.689675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3925 19:26:40.693378 ==
3926 19:26:40.696493 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3927 19:26:40.703462 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3928 19:26:40.706524 [CA 0] Center 35 (5~66) winsize 62
3929 19:26:40.709698 [CA 1] Center 35 (5~66) winsize 62
3930 19:26:40.713251 [CA 2] Center 34 (3~65) winsize 63
3931 19:26:40.716435 [CA 3] Center 33 (3~64) winsize 62
3932 19:26:40.719653 [CA 4] Center 33 (2~64) winsize 63
3933 19:26:40.723005 [CA 5] Center 32 (2~63) winsize 62
3934 19:26:40.723090
3935 19:26:40.726497 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3936 19:26:40.726580
3937 19:26:40.729830 [CATrainingPosCal] consider 2 rank data
3938 19:26:40.733164 u2DelayCellTimex100 = 270/100 ps
3939 19:26:40.736503 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3940 19:26:40.739286 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3941 19:26:40.745910 CA2 delay=34 (3~65),Diff = 2 PI (19 cell)
3942 19:26:40.749701 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3943 19:26:40.752951 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3944 19:26:40.756251 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3945 19:26:40.756335
3946 19:26:40.759392 CA PerBit enable=1, Macro0, CA PI delay=32
3947 19:26:40.759476
3948 19:26:40.762357 [CBTSetCACLKResult] CA Dly = 32
3949 19:26:40.762439 CS Dly: 4 (0~36)
3950 19:26:40.762506
3951 19:26:40.765851 ----->DramcWriteLeveling(PI) begin...
3952 19:26:40.769152 ==
3953 19:26:40.772362 Dram Type= 6, Freq= 0, CH_0, rank 0
3954 19:26:40.775690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3955 19:26:40.775774 ==
3956 19:26:40.779459 Write leveling (Byte 0): 35 => 35
3957 19:26:40.782834 Write leveling (Byte 1): 34 => 34
3958 19:26:40.785591 DramcWriteLeveling(PI) end<-----
3959 19:26:40.785673
3960 19:26:40.785739 ==
3961 19:26:40.788865 Dram Type= 6, Freq= 0, CH_0, rank 0
3962 19:26:40.792227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3963 19:26:40.792311 ==
3964 19:26:40.795607 [Gating] SW mode calibration
3965 19:26:40.802185 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3966 19:26:40.809348 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3967 19:26:40.812616 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3968 19:26:40.815967 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3969 19:26:40.822433 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
3970 19:26:40.825276 0 9 12 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
3971 19:26:40.828903 0 9 16 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
3972 19:26:40.835638 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3973 19:26:40.838927 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3974 19:26:40.842366 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3975 19:26:40.845760 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3976 19:26:40.851803 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3977 19:26:40.855202 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3978 19:26:40.858407 0 10 12 | B1->B0 | 2424 3131 | 0 0 | (0 0) (0 0)
3979 19:26:40.865172 0 10 16 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
3980 19:26:40.868482 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3981 19:26:40.871714 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3982 19:26:40.878605 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3983 19:26:40.882147 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3984 19:26:40.885495 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3985 19:26:40.891780 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3986 19:26:40.895140 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
3987 19:26:40.898400 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3988 19:26:40.905250 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3989 19:26:40.908389 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3990 19:26:40.911736 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3991 19:26:40.918164 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3992 19:26:40.921580 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3993 19:26:40.924990 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3994 19:26:40.931628 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 19:26:40.934713 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 19:26:40.938299 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 19:26:40.944922 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 19:26:40.948147 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 19:26:40.951551 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 19:26:40.958312 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 19:26:40.961695 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 19:26:40.965057 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4003 19:26:40.971660 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4004 19:26:40.971758 Total UI for P1: 0, mck2ui 16
4005 19:26:40.977628 best dqsien dly found for B0: ( 0, 13, 12)
4006 19:26:40.977712 Total UI for P1: 0, mck2ui 16
4007 19:26:40.984448 best dqsien dly found for B1: ( 0, 13, 14)
4008 19:26:40.987972 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4009 19:26:40.991336 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4010 19:26:40.991419
4011 19:26:40.994595 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4012 19:26:40.997661 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4013 19:26:41.001203 [Gating] SW calibration Done
4014 19:26:41.001286 ==
4015 19:26:41.004180 Dram Type= 6, Freq= 0, CH_0, rank 0
4016 19:26:41.007373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4017 19:26:41.007461 ==
4018 19:26:41.011103 RX Vref Scan: 0
4019 19:26:41.011198
4020 19:26:41.011265 RX Vref 0 -> 0, step: 1
4021 19:26:41.011325
4022 19:26:41.014240 RX Delay -230 -> 252, step: 16
4023 19:26:41.020927 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4024 19:26:41.023936 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4025 19:26:41.027567 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4026 19:26:41.030323 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4027 19:26:41.037090 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4028 19:26:41.040429 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4029 19:26:41.043664 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4030 19:26:41.047351 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4031 19:26:41.050562 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4032 19:26:41.057427 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4033 19:26:41.060610 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4034 19:26:41.063902 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4035 19:26:41.067141 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4036 19:26:41.073784 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4037 19:26:41.077109 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4038 19:26:41.080471 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4039 19:26:41.080566 ==
4040 19:26:41.083700 Dram Type= 6, Freq= 0, CH_0, rank 0
4041 19:26:41.087159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4042 19:26:41.090541 ==
4043 19:26:41.090632 DQS Delay:
4044 19:26:41.090698 DQS0 = 0, DQS1 = 0
4045 19:26:41.093438 DQM Delay:
4046 19:26:41.093510 DQM0 = 50, DQM1 = 45
4047 19:26:41.093573 DQ Delay:
4048 19:26:41.096834 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =41
4049 19:26:41.100346 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4050 19:26:41.103756 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4051 19:26:41.107156 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4052 19:26:41.107325
4053 19:26:41.110424
4054 19:26:41.110535 ==
4055 19:26:41.113798 Dram Type= 6, Freq= 0, CH_0, rank 0
4056 19:26:41.117007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4057 19:26:41.117135 ==
4058 19:26:41.117234
4059 19:26:41.117330
4060 19:26:41.120103 TX Vref Scan disable
4061 19:26:41.120207 == TX Byte 0 ==
4062 19:26:41.126781 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4063 19:26:41.130032 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4064 19:26:41.130166 == TX Byte 1 ==
4065 19:26:41.136999 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4066 19:26:41.140268 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4067 19:26:41.140400 ==
4068 19:26:41.143591 Dram Type= 6, Freq= 0, CH_0, rank 0
4069 19:26:41.146728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4070 19:26:41.146860 ==
4071 19:26:41.146954
4072 19:26:41.147054
4073 19:26:41.150061 TX Vref Scan disable
4074 19:26:41.153256 == TX Byte 0 ==
4075 19:26:41.156822 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4076 19:26:41.160014 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4077 19:26:41.163462 == TX Byte 1 ==
4078 19:26:41.166517 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4079 19:26:41.169755 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4080 19:26:41.169869
4081 19:26:41.173132 [DATLAT]
4082 19:26:41.173226 Freq=600, CH0 RK0
4083 19:26:41.173291
4084 19:26:41.176981 DATLAT Default: 0x9
4085 19:26:41.177055 0, 0xFFFF, sum = 0
4086 19:26:41.179728 1, 0xFFFF, sum = 0
4087 19:26:41.179813 2, 0xFFFF, sum = 0
4088 19:26:41.183104 3, 0xFFFF, sum = 0
4089 19:26:41.183189 4, 0xFFFF, sum = 0
4090 19:26:41.186385 5, 0xFFFF, sum = 0
4091 19:26:41.186485 6, 0xFFFF, sum = 0
4092 19:26:41.189806 7, 0xFFFF, sum = 0
4093 19:26:41.189879 8, 0x0, sum = 1
4094 19:26:41.193257 9, 0x0, sum = 2
4095 19:26:41.193361 10, 0x0, sum = 3
4096 19:26:41.196631 11, 0x0, sum = 4
4097 19:26:41.196736 best_step = 9
4098 19:26:41.196838
4099 19:26:41.196926 ==
4100 19:26:41.200055 Dram Type= 6, Freq= 0, CH_0, rank 0
4101 19:26:41.203465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4102 19:26:41.206215 ==
4103 19:26:41.206330 RX Vref Scan: 1
4104 19:26:41.206396
4105 19:26:41.209546 RX Vref 0 -> 0, step: 1
4106 19:26:41.209629
4107 19:26:41.212894 RX Delay -163 -> 252, step: 8
4108 19:26:41.212971
4109 19:26:41.216245 Set Vref, RX VrefLevel [Byte0]: 54
4110 19:26:41.219776 [Byte1]: 46
4111 19:26:41.219871
4112 19:26:41.223115 Final RX Vref Byte 0 = 54 to rank0
4113 19:26:41.226464 Final RX Vref Byte 1 = 46 to rank0
4114 19:26:41.229818 Final RX Vref Byte 0 = 54 to rank1
4115 19:26:41.232919 Final RX Vref Byte 1 = 46 to rank1==
4116 19:26:41.236307 Dram Type= 6, Freq= 0, CH_0, rank 0
4117 19:26:41.239665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4118 19:26:41.239739 ==
4119 19:26:41.243029 DQS Delay:
4120 19:26:41.243114 DQS0 = 0, DQS1 = 0
4121 19:26:41.243179 DQM Delay:
4122 19:26:41.246458 DQM0 = 52, DQM1 = 48
4123 19:26:41.246569 DQ Delay:
4124 19:26:41.249205 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =48
4125 19:26:41.252421 DQ4 =56, DQ5 =44, DQ6 =60, DQ7 =56
4126 19:26:41.256123 DQ8 =36, DQ9 =40, DQ10 =52, DQ11 =40
4127 19:26:41.259166 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =56
4128 19:26:41.259267
4129 19:26:41.259358
4130 19:26:41.269308 [DQSOSCAuto] RK0, (LSB)MR18= 0x796c, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 387 ps
4131 19:26:41.269415 CH0 RK0: MR19=808, MR18=796C
4132 19:26:41.276200 CH0_RK0: MR19=0x808, MR18=0x796C, DQSOSC=387, MR23=63, INC=175, DEC=116
4133 19:26:41.276335
4134 19:26:41.279215 ----->DramcWriteLeveling(PI) begin...
4135 19:26:41.282181 ==
4136 19:26:41.285718 Dram Type= 6, Freq= 0, CH_0, rank 1
4137 19:26:41.289124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4138 19:26:41.289244 ==
4139 19:26:41.292591 Write leveling (Byte 0): 35 => 35
4140 19:26:41.296144 Write leveling (Byte 1): 31 => 31
4141 19:26:41.299130 DramcWriteLeveling(PI) end<-----
4142 19:26:41.299231
4143 19:26:41.299327 ==
4144 19:26:41.302799 Dram Type= 6, Freq= 0, CH_0, rank 1
4145 19:26:41.305437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4146 19:26:41.305538 ==
4147 19:26:41.308918 [Gating] SW mode calibration
4148 19:26:41.315747 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4149 19:26:41.322511 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4150 19:26:41.325804 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4151 19:26:41.329098 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4152 19:26:41.332505 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4153 19:26:41.338993 0 9 12 | B1->B0 | 3434 3434 | 0 0 | (0 1) (0 1)
4154 19:26:41.342573 0 9 16 | B1->B0 | 2e2e 2424 | 0 0 | (1 1) (0 0)
4155 19:26:41.345888 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4156 19:26:41.352031 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4157 19:26:41.355460 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4158 19:26:41.358813 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4159 19:26:41.365711 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4160 19:26:41.369115 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4161 19:26:41.372473 0 10 12 | B1->B0 | 2a2a 2929 | 0 0 | (0 0) (0 0)
4162 19:26:41.379088 0 10 16 | B1->B0 | 3b3b 4444 | 1 1 | (0 0) (0 0)
4163 19:26:41.382368 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4164 19:26:41.385613 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4165 19:26:41.392197 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4166 19:26:41.395200 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4167 19:26:41.398746 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4168 19:26:41.405173 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4169 19:26:41.408870 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4170 19:26:41.411943 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4171 19:26:41.418526 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4172 19:26:41.422084 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4173 19:26:41.425054 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4174 19:26:41.431755 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4175 19:26:41.435015 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4176 19:26:41.438261 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4177 19:26:41.444837 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4178 19:26:41.448176 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4179 19:26:41.451493 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4180 19:26:41.458396 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 19:26:41.461720 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 19:26:41.465231 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 19:26:41.472024 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 19:26:41.475363 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 19:26:41.478571 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4186 19:26:41.481939 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4187 19:26:41.485306 Total UI for P1: 0, mck2ui 16
4188 19:26:41.488425 best dqsien dly found for B0: ( 0, 13, 12)
4189 19:26:41.491658 Total UI for P1: 0, mck2ui 16
4190 19:26:41.494883 best dqsien dly found for B1: ( 0, 13, 12)
4191 19:26:41.498261 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4192 19:26:41.504783 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4193 19:26:41.504863
4194 19:26:41.508163 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4195 19:26:41.511449 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4196 19:26:41.514653 [Gating] SW calibration Done
4197 19:26:41.514751 ==
4198 19:26:41.518001 Dram Type= 6, Freq= 0, CH_0, rank 1
4199 19:26:41.521749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4200 19:26:41.521823 ==
4201 19:26:41.524780 RX Vref Scan: 0
4202 19:26:41.524853
4203 19:26:41.524920 RX Vref 0 -> 0, step: 1
4204 19:26:41.524980
4205 19:26:41.528239 RX Delay -230 -> 252, step: 16
4206 19:26:41.531615 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4207 19:26:41.538495 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4208 19:26:41.541622 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4209 19:26:41.545259 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4210 19:26:41.548098 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4211 19:26:41.554366 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4212 19:26:41.557815 iDelay=218, Bit 6, Center 73 (-70 ~ 217) 288
4213 19:26:41.561077 iDelay=218, Bit 7, Center 73 (-70 ~ 217) 288
4214 19:26:41.564319 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4215 19:26:41.567770 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4216 19:26:41.574415 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4217 19:26:41.577581 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4218 19:26:41.580918 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4219 19:26:41.584310 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4220 19:26:41.591082 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4221 19:26:41.594251 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4222 19:26:41.594393 ==
4223 19:26:41.597515 Dram Type= 6, Freq= 0, CH_0, rank 1
4224 19:26:41.601059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4225 19:26:41.601162 ==
4226 19:26:41.604218 DQS Delay:
4227 19:26:41.604301 DQS0 = 0, DQS1 = 0
4228 19:26:41.604366 DQM Delay:
4229 19:26:41.607470 DQM0 = 55, DQM1 = 43
4230 19:26:41.607545 DQ Delay:
4231 19:26:41.610872 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4232 19:26:41.614174 DQ4 =57, DQ5 =41, DQ6 =73, DQ7 =73
4233 19:26:41.617510 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =33
4234 19:26:41.620896 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4235 19:26:41.620992
4236 19:26:41.621056
4237 19:26:41.621116 ==
4238 19:26:41.624275 Dram Type= 6, Freq= 0, CH_0, rank 1
4239 19:26:41.630877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4240 19:26:41.630981 ==
4241 19:26:41.631049
4242 19:26:41.631107
4243 19:26:41.631164 TX Vref Scan disable
4244 19:26:41.634210 == TX Byte 0 ==
4245 19:26:41.637647 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4246 19:26:41.644609 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4247 19:26:41.644687 == TX Byte 1 ==
4248 19:26:41.647699 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4249 19:26:41.654639 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4250 19:26:41.654722 ==
4251 19:26:41.657588 Dram Type= 6, Freq= 0, CH_0, rank 1
4252 19:26:41.661036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4253 19:26:41.661111 ==
4254 19:26:41.661178
4255 19:26:41.661237
4256 19:26:41.664152 TX Vref Scan disable
4257 19:26:41.667537 == TX Byte 0 ==
4258 19:26:41.671085 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4259 19:26:41.674589 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4260 19:26:41.677338 == TX Byte 1 ==
4261 19:26:41.680827 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4262 19:26:41.684214 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4263 19:26:41.684292
4264 19:26:41.684355 [DATLAT]
4265 19:26:41.687556 Freq=600, CH0 RK1
4266 19:26:41.687638
4267 19:26:41.687730 DATLAT Default: 0x9
4268 19:26:41.690710 0, 0xFFFF, sum = 0
4269 19:26:41.694188 1, 0xFFFF, sum = 0
4270 19:26:41.694289 2, 0xFFFF, sum = 0
4271 19:26:41.697573 3, 0xFFFF, sum = 0
4272 19:26:41.697649 4, 0xFFFF, sum = 0
4273 19:26:41.700897 5, 0xFFFF, sum = 0
4274 19:26:41.700981 6, 0xFFFF, sum = 0
4275 19:26:41.704105 7, 0xFFFF, sum = 0
4276 19:26:41.704195 8, 0x0, sum = 1
4277 19:26:41.704266 9, 0x0, sum = 2
4278 19:26:41.707883 10, 0x0, sum = 3
4279 19:26:41.708000 11, 0x0, sum = 4
4280 19:26:41.710968 best_step = 9
4281 19:26:41.711053
4282 19:26:41.711119 ==
4283 19:26:41.714332 Dram Type= 6, Freq= 0, CH_0, rank 1
4284 19:26:41.717705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4285 19:26:41.717779 ==
4286 19:26:41.720982 RX Vref Scan: 0
4287 19:26:41.721056
4288 19:26:41.721120 RX Vref 0 -> 0, step: 1
4289 19:26:41.724310
4290 19:26:41.724384 RX Delay -163 -> 252, step: 8
4291 19:26:41.731333 iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288
4292 19:26:41.734742 iDelay=197, Bit 1, Center 56 (-83 ~ 196) 280
4293 19:26:41.738126 iDelay=197, Bit 2, Center 52 (-91 ~ 196) 288
4294 19:26:41.741481 iDelay=197, Bit 3, Center 52 (-91 ~ 196) 288
4295 19:26:41.744895 iDelay=197, Bit 4, Center 52 (-91 ~ 196) 288
4296 19:26:41.751765 iDelay=197, Bit 5, Center 44 (-99 ~ 188) 288
4297 19:26:41.754978 iDelay=197, Bit 6, Center 56 (-83 ~ 196) 280
4298 19:26:41.758240 iDelay=197, Bit 7, Center 56 (-83 ~ 196) 280
4299 19:26:41.761588 iDelay=197, Bit 8, Center 36 (-107 ~ 180) 288
4300 19:26:41.764598 iDelay=197, Bit 9, Center 32 (-107 ~ 172) 280
4301 19:26:41.771360 iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280
4302 19:26:41.774430 iDelay=197, Bit 11, Center 40 (-99 ~ 180) 280
4303 19:26:41.777837 iDelay=197, Bit 12, Center 52 (-83 ~ 188) 272
4304 19:26:41.781104 iDelay=197, Bit 13, Center 48 (-91 ~ 188) 280
4305 19:26:41.787805 iDelay=197, Bit 14, Center 56 (-83 ~ 196) 280
4306 19:26:41.790899 iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288
4307 19:26:41.790977 ==
4308 19:26:41.794799 Dram Type= 6, Freq= 0, CH_0, rank 1
4309 19:26:41.797876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4310 19:26:41.797975 ==
4311 19:26:41.801451 DQS Delay:
4312 19:26:41.801551 DQS0 = 0, DQS1 = 0
4313 19:26:41.801664 DQM Delay:
4314 19:26:41.804331 DQM0 = 52, DQM1 = 45
4315 19:26:41.804439 DQ Delay:
4316 19:26:41.808031 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4317 19:26:41.811148 DQ4 =52, DQ5 =44, DQ6 =56, DQ7 =56
4318 19:26:41.814351 DQ8 =36, DQ9 =32, DQ10 =48, DQ11 =40
4319 19:26:41.818001 DQ12 =52, DQ13 =48, DQ14 =56, DQ15 =52
4320 19:26:41.818104
4321 19:26:41.818191
4322 19:26:41.827538 [DQSOSCAuto] RK1, (LSB)MR18= 0x6c2c, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 389 ps
4323 19:26:41.827653 CH0 RK1: MR19=808, MR18=6C2C
4324 19:26:41.834537 CH0_RK1: MR19=0x808, MR18=0x6C2C, DQSOSC=389, MR23=63, INC=173, DEC=115
4325 19:26:41.837904 [RxdqsGatingPostProcess] freq 600
4326 19:26:41.844168 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4327 19:26:41.847457 Pre-setting of DQS Precalculation
4328 19:26:41.850811 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4329 19:26:41.850910 ==
4330 19:26:41.854136 Dram Type= 6, Freq= 0, CH_1, rank 0
4331 19:26:41.860876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4332 19:26:41.860989 ==
4333 19:26:41.864084 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4334 19:26:41.870814 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4335 19:26:41.874013 [CA 0] Center 35 (5~66) winsize 62
4336 19:26:41.877208 [CA 1] Center 36 (5~67) winsize 63
4337 19:26:41.880685 [CA 2] Center 34 (4~65) winsize 62
4338 19:26:41.884305 [CA 3] Center 34 (3~65) winsize 63
4339 19:26:41.887258 [CA 4] Center 34 (4~65) winsize 62
4340 19:26:41.890682 [CA 5] Center 33 (3~64) winsize 62
4341 19:26:41.890779
4342 19:26:41.893981 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4343 19:26:41.894077
4344 19:26:41.897503 [CATrainingPosCal] consider 1 rank data
4345 19:26:41.900824 u2DelayCellTimex100 = 270/100 ps
4346 19:26:41.904218 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4347 19:26:41.907441 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
4348 19:26:41.913588 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4349 19:26:41.917473 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4350 19:26:41.920602 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4351 19:26:41.924249 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4352 19:26:41.924322
4353 19:26:41.927139 CA PerBit enable=1, Macro0, CA PI delay=33
4354 19:26:41.927214
4355 19:26:41.930202 [CBTSetCACLKResult] CA Dly = 33
4356 19:26:41.930272 CS Dly: 6 (0~37)
4357 19:26:41.930372 ==
4358 19:26:41.933799 Dram Type= 6, Freq= 0, CH_1, rank 1
4359 19:26:41.940301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4360 19:26:41.940373 ==
4361 19:26:41.943981 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4362 19:26:41.950740 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4363 19:26:41.953998 [CA 0] Center 36 (6~67) winsize 62
4364 19:26:41.957384 [CA 1] Center 36 (6~67) winsize 62
4365 19:26:41.960713 [CA 2] Center 35 (5~66) winsize 62
4366 19:26:41.964420 [CA 3] Center 35 (4~66) winsize 63
4367 19:26:41.967561 [CA 4] Center 34 (4~65) winsize 62
4368 19:26:41.970971 [CA 5] Center 34 (4~65) winsize 62
4369 19:26:41.971044
4370 19:26:41.973736 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4371 19:26:41.973839
4372 19:26:41.977095 [CATrainingPosCal] consider 2 rank data
4373 19:26:41.980476 u2DelayCellTimex100 = 270/100 ps
4374 19:26:41.983778 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4375 19:26:41.990236 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4376 19:26:41.993621 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4377 19:26:41.997308 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4378 19:26:42.000304 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4379 19:26:42.003796 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4380 19:26:42.003870
4381 19:26:42.007074 CA PerBit enable=1, Macro0, CA PI delay=34
4382 19:26:42.007161
4383 19:26:42.010447 [CBTSetCACLKResult] CA Dly = 34
4384 19:26:42.010527 CS Dly: 6 (0~38)
4385 19:26:42.013885
4386 19:26:42.017138 ----->DramcWriteLeveling(PI) begin...
4387 19:26:42.017216 ==
4388 19:26:42.020434 Dram Type= 6, Freq= 0, CH_1, rank 0
4389 19:26:42.023447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4390 19:26:42.023521 ==
4391 19:26:42.026833 Write leveling (Byte 0): 31 => 31
4392 19:26:42.030184 Write leveling (Byte 1): 31 => 31
4393 19:26:42.034002 DramcWriteLeveling(PI) end<-----
4394 19:26:42.034115
4395 19:26:42.034207 ==
4396 19:26:42.037105 Dram Type= 6, Freq= 0, CH_1, rank 0
4397 19:26:42.040354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4398 19:26:42.040434 ==
4399 19:26:42.043678 [Gating] SW mode calibration
4400 19:26:42.049934 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4401 19:26:42.056676 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4402 19:26:42.059946 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4403 19:26:42.063364 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4404 19:26:42.070175 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4405 19:26:42.073452 0 9 12 | B1->B0 | 3030 2d2d | 1 0 | (1 1) (0 0)
4406 19:26:42.076693 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4407 19:26:42.083452 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4408 19:26:42.086795 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4409 19:26:42.089522 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4410 19:26:42.096834 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4411 19:26:42.099569 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4412 19:26:42.103086 0 10 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
4413 19:26:42.109432 0 10 12 | B1->B0 | 3939 3a3a | 1 0 | (0 0) (1 1)
4414 19:26:42.112942 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4415 19:26:42.116683 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4416 19:26:42.119478 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4417 19:26:42.126220 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4418 19:26:42.129459 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4419 19:26:42.133241 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4420 19:26:42.139854 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4421 19:26:42.142917 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4422 19:26:42.146233 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4423 19:26:42.152918 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4424 19:26:42.156159 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4425 19:26:42.159856 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4426 19:26:42.166455 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4427 19:26:42.169713 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 19:26:42.172834 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 19:26:42.179308 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 19:26:42.182724 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 19:26:42.186184 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 19:26:42.192834 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 19:26:42.196297 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 19:26:42.199489 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 19:26:42.206164 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 19:26:42.209470 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 19:26:42.212806 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4438 19:26:42.216081 Total UI for P1: 0, mck2ui 16
4439 19:26:42.219156 best dqsien dly found for B0: ( 0, 13, 10)
4440 19:26:42.222643 Total UI for P1: 0, mck2ui 16
4441 19:26:42.225697 best dqsien dly found for B1: ( 0, 13, 10)
4442 19:26:42.228835 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4443 19:26:42.232152 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4444 19:26:42.232222
4445 19:26:42.239141 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4446 19:26:42.242499 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4447 19:26:42.242570 [Gating] SW calibration Done
4448 19:26:42.245660 ==
4449 19:26:42.248895 Dram Type= 6, Freq= 0, CH_1, rank 0
4450 19:26:42.252815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4451 19:26:42.252925 ==
4452 19:26:42.253060 RX Vref Scan: 0
4453 19:26:42.253147
4454 19:26:42.255924 RX Vref 0 -> 0, step: 1
4455 19:26:42.255992
4456 19:26:42.259232 RX Delay -230 -> 252, step: 16
4457 19:26:42.262655 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4458 19:26:42.265804 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4459 19:26:42.272219 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4460 19:26:42.275772 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4461 19:26:42.279017 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4462 19:26:42.282123 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4463 19:26:42.288987 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4464 19:26:42.292061 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4465 19:26:42.295460 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4466 19:26:42.298845 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4467 19:26:42.302171 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4468 19:26:42.308695 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4469 19:26:42.312146 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4470 19:26:42.315487 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4471 19:26:42.318954 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4472 19:26:42.325598 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4473 19:26:42.325675 ==
4474 19:26:42.328767 Dram Type= 6, Freq= 0, CH_1, rank 0
4475 19:26:42.332372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4476 19:26:42.332467 ==
4477 19:26:42.332578 DQS Delay:
4478 19:26:42.335520 DQS0 = 0, DQS1 = 0
4479 19:26:42.335584 DQM Delay:
4480 19:26:42.338796 DQM0 = 47, DQM1 = 46
4481 19:26:42.338864 DQ Delay:
4482 19:26:42.342107 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =41
4483 19:26:42.345525 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4484 19:26:42.348747 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4485 19:26:42.352084 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4486 19:26:42.352177
4487 19:26:42.352254
4488 19:26:42.352310 ==
4489 19:26:42.355418 Dram Type= 6, Freq= 0, CH_1, rank 0
4490 19:26:42.358713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4491 19:26:42.358780 ==
4492 19:26:42.358840
4493 19:26:42.361869
4494 19:26:42.361973 TX Vref Scan disable
4495 19:26:42.365097 == TX Byte 0 ==
4496 19:26:42.368461 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4497 19:26:42.371826 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4498 19:26:42.375177 == TX Byte 1 ==
4499 19:26:42.378449 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4500 19:26:42.382363 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4501 19:26:42.382433 ==
4502 19:26:42.385430 Dram Type= 6, Freq= 0, CH_1, rank 0
4503 19:26:42.391704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4504 19:26:42.391786 ==
4505 19:26:42.391852
4506 19:26:42.391910
4507 19:26:42.391966 TX Vref Scan disable
4508 19:26:42.396343 == TX Byte 0 ==
4509 19:26:42.400149 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4510 19:26:42.403491 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4511 19:26:42.406862 == TX Byte 1 ==
4512 19:26:42.409524 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4513 19:26:42.416674 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4514 19:26:42.416751
4515 19:26:42.416821 [DATLAT]
4516 19:26:42.416880 Freq=600, CH1 RK0
4517 19:26:42.416939
4518 19:26:42.419429 DATLAT Default: 0x9
4519 19:26:42.419498 0, 0xFFFF, sum = 0
4520 19:26:42.422815 1, 0xFFFF, sum = 0
4521 19:26:42.422884 2, 0xFFFF, sum = 0
4522 19:26:42.426178 3, 0xFFFF, sum = 0
4523 19:26:42.429524 4, 0xFFFF, sum = 0
4524 19:26:42.429594 5, 0xFFFF, sum = 0
4525 19:26:42.432822 6, 0xFFFF, sum = 0
4526 19:26:42.432890 7, 0xFFFF, sum = 0
4527 19:26:42.436443 8, 0x0, sum = 1
4528 19:26:42.436526 9, 0x0, sum = 2
4529 19:26:42.436617 10, 0x0, sum = 3
4530 19:26:42.439638 11, 0x0, sum = 4
4531 19:26:42.439707 best_step = 9
4532 19:26:42.439770
4533 19:26:42.439827 ==
4534 19:26:42.442625 Dram Type= 6, Freq= 0, CH_1, rank 0
4535 19:26:42.449331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4536 19:26:42.449411 ==
4537 19:26:42.449475 RX Vref Scan: 1
4538 19:26:42.449533
4539 19:26:42.453192 RX Vref 0 -> 0, step: 1
4540 19:26:42.453286
4541 19:26:42.456429 RX Delay -163 -> 252, step: 8
4542 19:26:42.456500
4543 19:26:42.459607 Set Vref, RX VrefLevel [Byte0]: 54
4544 19:26:42.462963 [Byte1]: 54
4545 19:26:42.463036
4546 19:26:42.466211 Final RX Vref Byte 0 = 54 to rank0
4547 19:26:42.469394 Final RX Vref Byte 1 = 54 to rank0
4548 19:26:42.472578 Final RX Vref Byte 0 = 54 to rank1
4549 19:26:42.476169 Final RX Vref Byte 1 = 54 to rank1==
4550 19:26:42.479518 Dram Type= 6, Freq= 0, CH_1, rank 0
4551 19:26:42.482297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4552 19:26:42.482410 ==
4553 19:26:42.485791 DQS Delay:
4554 19:26:42.485859 DQS0 = 0, DQS1 = 0
4555 19:26:42.489249 DQM Delay:
4556 19:26:42.489317 DQM0 = 48, DQM1 = 44
4557 19:26:42.489376 DQ Delay:
4558 19:26:42.492497 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4559 19:26:42.496229 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4560 19:26:42.499246 DQ8 =32, DQ9 =32, DQ10 =44, DQ11 =36
4561 19:26:42.502313 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4562 19:26:42.502484
4563 19:26:42.502625
4564 19:26:42.512504 [DQSOSCAuto] RK0, (LSB)MR18= 0x496f, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4565 19:26:42.515692 CH1 RK0: MR19=808, MR18=496F
4566 19:26:42.519507 CH1_RK0: MR19=0x808, MR18=0x496F, DQSOSC=389, MR23=63, INC=173, DEC=115
4567 19:26:42.522264
4568 19:26:42.525675 ----->DramcWriteLeveling(PI) begin...
4569 19:26:42.525752 ==
4570 19:26:42.529100 Dram Type= 6, Freq= 0, CH_1, rank 1
4571 19:26:42.532303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4572 19:26:42.532370 ==
4573 19:26:42.535679 Write leveling (Byte 0): 29 => 29
4574 19:26:42.539102 Write leveling (Byte 1): 28 => 28
4575 19:26:42.542514 DramcWriteLeveling(PI) end<-----
4576 19:26:42.542587
4577 19:26:42.542655 ==
4578 19:26:42.545263 Dram Type= 6, Freq= 0, CH_1, rank 1
4579 19:26:42.548882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4580 19:26:42.548950 ==
4581 19:26:42.552109 [Gating] SW mode calibration
4582 19:26:42.558949 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4583 19:26:42.565875 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4584 19:26:42.568561 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4585 19:26:42.572020 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4586 19:26:42.578972 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (0 1)
4587 19:26:42.582250 0 9 12 | B1->B0 | 3030 3030 | 1 1 | (1 1) (1 1)
4588 19:26:42.585343 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4589 19:26:42.592146 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4590 19:26:42.595078 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4591 19:26:42.598454 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4592 19:26:42.605563 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4593 19:26:42.608834 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4594 19:26:42.612006 0 10 8 | B1->B0 | 2929 2727 | 0 0 | (0 0) (0 0)
4595 19:26:42.618636 0 10 12 | B1->B0 | 3b3b 3737 | 0 0 | (0 0) (1 1)
4596 19:26:42.621720 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4597 19:26:42.625395 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4598 19:26:42.631739 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4599 19:26:42.635092 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4600 19:26:42.638400 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4601 19:26:42.641720 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4602 19:26:42.648511 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4603 19:26:42.651800 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4604 19:26:42.655104 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4605 19:26:42.661459 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4606 19:26:42.664755 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4607 19:26:42.668065 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4608 19:26:42.675059 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4609 19:26:42.678151 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4610 19:26:42.681359 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4611 19:26:42.688591 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4612 19:26:42.691433 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4613 19:26:42.695262 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4614 19:26:42.701816 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 19:26:42.704608 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 19:26:42.707849 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 19:26:42.714586 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 19:26:42.717862 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 19:26:42.721086 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4620 19:26:42.724880 Total UI for P1: 0, mck2ui 16
4621 19:26:42.728167 best dqsien dly found for B1: ( 0, 13, 10)
4622 19:26:42.734350 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4623 19:26:42.734432 Total UI for P1: 0, mck2ui 16
4624 19:26:42.741163 best dqsien dly found for B0: ( 0, 13, 12)
4625 19:26:42.744480 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4626 19:26:42.747847 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4627 19:26:42.747917
4628 19:26:42.751181 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4629 19:26:42.754672 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4630 19:26:42.758092 [Gating] SW calibration Done
4631 19:26:42.758184 ==
4632 19:26:42.761347 Dram Type= 6, Freq= 0, CH_1, rank 1
4633 19:26:42.764538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4634 19:26:42.764634 ==
4635 19:26:42.767716 RX Vref Scan: 0
4636 19:26:42.767855
4637 19:26:42.767944 RX Vref 0 -> 0, step: 1
4638 19:26:42.768036
4639 19:26:42.771171 RX Delay -230 -> 252, step: 16
4640 19:26:42.777889 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4641 19:26:42.781096 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4642 19:26:42.784330 iDelay=218, Bit 2, Center 41 (-102 ~ 185) 288
4643 19:26:42.788028 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4644 19:26:42.791182 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4645 19:26:42.797731 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4646 19:26:42.801040 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4647 19:26:42.804766 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4648 19:26:42.807958 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4649 19:26:42.811297 iDelay=218, Bit 9, Center 49 (-102 ~ 201) 304
4650 19:26:42.817794 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4651 19:26:42.821333 iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304
4652 19:26:42.824737 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4653 19:26:42.827920 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4654 19:26:42.834453 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4655 19:26:42.837749 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4656 19:26:42.837820 ==
4657 19:26:42.841194 Dram Type= 6, Freq= 0, CH_1, rank 1
4658 19:26:42.844422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4659 19:26:42.844500 ==
4660 19:26:42.848029 DQS Delay:
4661 19:26:42.848095 DQS0 = 0, DQS1 = 0
4662 19:26:42.848159 DQM Delay:
4663 19:26:42.851076 DQM0 = 51, DQM1 = 50
4664 19:26:42.851193 DQ Delay:
4665 19:26:42.854382 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4666 19:26:42.857832 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4667 19:26:42.861220 DQ8 =33, DQ9 =49, DQ10 =49, DQ11 =49
4668 19:26:42.864579 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4669 19:26:42.864657
4670 19:26:42.864720
4671 19:26:42.864787 ==
4672 19:26:42.867893 Dram Type= 6, Freq= 0, CH_1, rank 1
4673 19:26:42.874224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4674 19:26:42.874298 ==
4675 19:26:42.874414
4676 19:26:42.874473
4677 19:26:42.874529 TX Vref Scan disable
4678 19:26:42.877865 == TX Byte 0 ==
4679 19:26:42.881207 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4680 19:26:42.888291 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4681 19:26:42.888370 == TX Byte 1 ==
4682 19:26:42.891441 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4683 19:26:42.894492 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4684 19:26:42.898235 ==
4685 19:26:42.901512 Dram Type= 6, Freq= 0, CH_1, rank 1
4686 19:26:42.904859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4687 19:26:42.904958 ==
4688 19:26:42.905056
4689 19:26:42.905141
4690 19:26:42.908150 TX Vref Scan disable
4691 19:26:42.908220 == TX Byte 0 ==
4692 19:26:42.914507 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4693 19:26:42.917788 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4694 19:26:42.921216 == TX Byte 1 ==
4695 19:26:42.924388 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4696 19:26:42.927735 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4697 19:26:42.927808
4698 19:26:42.927871 [DATLAT]
4699 19:26:42.931146 Freq=600, CH1 RK1
4700 19:26:42.931216
4701 19:26:42.931276 DATLAT Default: 0x9
4702 19:26:42.934371 0, 0xFFFF, sum = 0
4703 19:26:42.934438 1, 0xFFFF, sum = 0
4704 19:26:42.937544 2, 0xFFFF, sum = 0
4705 19:26:42.941236 3, 0xFFFF, sum = 0
4706 19:26:42.941340 4, 0xFFFF, sum = 0
4707 19:26:42.944608 5, 0xFFFF, sum = 0
4708 19:26:42.944690 6, 0xFFFF, sum = 0
4709 19:26:42.948067 7, 0xFFFF, sum = 0
4710 19:26:42.948193 8, 0x0, sum = 1
4711 19:26:42.948298 9, 0x0, sum = 2
4712 19:26:42.950848 10, 0x0, sum = 3
4713 19:26:42.950952 11, 0x0, sum = 4
4714 19:26:42.954262 best_step = 9
4715 19:26:42.954380
4716 19:26:42.954445 ==
4717 19:26:42.957547 Dram Type= 6, Freq= 0, CH_1, rank 1
4718 19:26:42.961212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4719 19:26:42.961278 ==
4720 19:26:42.964185 RX Vref Scan: 0
4721 19:26:42.964259
4722 19:26:42.964320 RX Vref 0 -> 0, step: 1
4723 19:26:42.964383
4724 19:26:42.967711 RX Delay -163 -> 252, step: 8
4725 19:26:42.975157 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4726 19:26:42.978649 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4727 19:26:42.981611 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4728 19:26:42.984785 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4729 19:26:42.988449 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4730 19:26:42.994637 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4731 19:26:42.998056 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4732 19:26:43.001843 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4733 19:26:43.005147 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4734 19:26:43.011586 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4735 19:26:43.014874 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4736 19:26:43.018266 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4737 19:26:43.021663 iDelay=205, Bit 12, Center 56 (-91 ~ 204) 296
4738 19:26:43.025093 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4739 19:26:43.031245 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4740 19:26:43.034774 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4741 19:26:43.034845 ==
4742 19:26:43.038445 Dram Type= 6, Freq= 0, CH_1, rank 1
4743 19:26:43.041339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4744 19:26:43.041444 ==
4745 19:26:43.045145 DQS Delay:
4746 19:26:43.045217 DQS0 = 0, DQS1 = 0
4747 19:26:43.045295 DQM Delay:
4748 19:26:43.048218 DQM0 = 49, DQM1 = 46
4749 19:26:43.048292 DQ Delay:
4750 19:26:43.051411 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4751 19:26:43.054828 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =48
4752 19:26:43.058191 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4753 19:26:43.061587 DQ12 =56, DQ13 =52, DQ14 =52, DQ15 =56
4754 19:26:43.061681
4755 19:26:43.061775
4756 19:26:43.071401 [DQSOSCAuto] RK1, (LSB)MR18= 0x6d23, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 389 ps
4757 19:26:43.071479 CH1 RK1: MR19=808, MR18=6D23
4758 19:26:43.078214 CH1_RK1: MR19=0x808, MR18=0x6D23, DQSOSC=389, MR23=63, INC=173, DEC=115
4759 19:26:43.080952 [RxdqsGatingPostProcess] freq 600
4760 19:26:43.087781 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4761 19:26:43.090918 Pre-setting of DQS Precalculation
4762 19:26:43.094779 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4763 19:26:43.101052 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4764 19:26:43.111488 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4765 19:26:43.111592
4766 19:26:43.111664
4767 19:26:43.114692 [Calibration Summary] 1200 Mbps
4768 19:26:43.114846 CH 0, Rank 0
4769 19:26:43.117936 SW Impedance : PASS
4770 19:26:43.118045 DUTY Scan : NO K
4771 19:26:43.120753 ZQ Calibration : PASS
4772 19:26:43.124119 Jitter Meter : NO K
4773 19:26:43.124188 CBT Training : PASS
4774 19:26:43.127517 Write leveling : PASS
4775 19:26:43.130886 RX DQS gating : PASS
4776 19:26:43.130954 RX DQ/DQS(RDDQC) : PASS
4777 19:26:43.134368 TX DQ/DQS : PASS
4778 19:26:43.134435 RX DATLAT : PASS
4779 19:26:43.137749 RX DQ/DQS(Engine): PASS
4780 19:26:43.140900 TX OE : NO K
4781 19:26:43.140969 All Pass.
4782 19:26:43.141035
4783 19:26:43.141092 CH 0, Rank 1
4784 19:26:43.144032 SW Impedance : PASS
4785 19:26:43.147478 DUTY Scan : NO K
4786 19:26:43.147569 ZQ Calibration : PASS
4787 19:26:43.150897 Jitter Meter : NO K
4788 19:26:43.153835 CBT Training : PASS
4789 19:26:43.153949 Write leveling : PASS
4790 19:26:43.157344 RX DQS gating : PASS
4791 19:26:43.160918 RX DQ/DQS(RDDQC) : PASS
4792 19:26:43.161038 TX DQ/DQS : PASS
4793 19:26:43.163902 RX DATLAT : PASS
4794 19:26:43.167422 RX DQ/DQS(Engine): PASS
4795 19:26:43.167541 TX OE : NO K
4796 19:26:43.170465 All Pass.
4797 19:26:43.170588
4798 19:26:43.170688 CH 1, Rank 0
4799 19:26:43.173931 SW Impedance : PASS
4800 19:26:43.174059 DUTY Scan : NO K
4801 19:26:43.177249 ZQ Calibration : PASS
4802 19:26:43.180387 Jitter Meter : NO K
4803 19:26:43.180462 CBT Training : PASS
4804 19:26:43.184092 Write leveling : PASS
4805 19:26:43.187123 RX DQS gating : PASS
4806 19:26:43.187199 RX DQ/DQS(RDDQC) : PASS
4807 19:26:43.190486 TX DQ/DQS : PASS
4808 19:26:43.190558 RX DATLAT : PASS
4809 19:26:43.193835 RX DQ/DQS(Engine): PASS
4810 19:26:43.197200 TX OE : NO K
4811 19:26:43.197299 All Pass.
4812 19:26:43.197406
4813 19:26:43.197469 CH 1, Rank 1
4814 19:26:43.200366 SW Impedance : PASS
4815 19:26:43.204063 DUTY Scan : NO K
4816 19:26:43.204172 ZQ Calibration : PASS
4817 19:26:43.207139 Jitter Meter : NO K
4818 19:26:43.211102 CBT Training : PASS
4819 19:26:43.211201 Write leveling : PASS
4820 19:26:43.213892 RX DQS gating : PASS
4821 19:26:43.217218 RX DQ/DQS(RDDQC) : PASS
4822 19:26:43.217320 TX DQ/DQS : PASS
4823 19:26:43.220985 RX DATLAT : PASS
4824 19:26:43.224108 RX DQ/DQS(Engine): PASS
4825 19:26:43.224215 TX OE : NO K
4826 19:26:43.224311 All Pass.
4827 19:26:43.227588
4828 19:26:43.227703 DramC Write-DBI off
4829 19:26:43.230490 PER_BANK_REFRESH: Hybrid Mode
4830 19:26:43.230570 TX_TRACKING: ON
4831 19:26:43.240511 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4832 19:26:43.244006 [FAST_K] Save calibration result to emmc
4833 19:26:43.247566 dramc_set_vcore_voltage set vcore to 662500
4834 19:26:43.250884 Read voltage for 933, 3
4835 19:26:43.250985 Vio18 = 0
4836 19:26:43.253754 Vcore = 662500
4837 19:26:43.253862 Vdram = 0
4838 19:26:43.253960 Vddq = 0
4839 19:26:43.254028 Vmddr = 0
4840 19:26:43.260733 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4841 19:26:43.268190 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4842 19:26:43.268280 MEM_TYPE=3, freq_sel=17
4843 19:26:43.270498 sv_algorithm_assistance_LP4_1600
4844 19:26:43.273483 ============ PULL DRAM RESETB DOWN ============
4845 19:26:43.280386 ========== PULL DRAM RESETB DOWN end =========
4846 19:26:43.283927 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4847 19:26:43.287271 ===================================
4848 19:26:43.290691 LPDDR4 DRAM CONFIGURATION
4849 19:26:43.293823 ===================================
4850 19:26:43.293932 EX_ROW_EN[0] = 0x0
4851 19:26:43.297318 EX_ROW_EN[1] = 0x0
4852 19:26:43.297402 LP4Y_EN = 0x0
4853 19:26:43.300041 WORK_FSP = 0x0
4854 19:26:43.303706 WL = 0x3
4855 19:26:43.303790 RL = 0x3
4856 19:26:43.307023 BL = 0x2
4857 19:26:43.307107 RPST = 0x0
4858 19:26:43.310221 RD_PRE = 0x0
4859 19:26:43.310340 WR_PRE = 0x1
4860 19:26:43.313417 WR_PST = 0x0
4861 19:26:43.313539 DBI_WR = 0x0
4862 19:26:43.316547 DBI_RD = 0x0
4863 19:26:43.316655 OTF = 0x1
4864 19:26:43.319765 ===================================
4865 19:26:43.323233 ===================================
4866 19:26:43.326431 ANA top config
4867 19:26:43.330208 ===================================
4868 19:26:43.330322 DLL_ASYNC_EN = 0
4869 19:26:43.333298 ALL_SLAVE_EN = 1
4870 19:26:43.336676 NEW_RANK_MODE = 1
4871 19:26:43.339961 DLL_IDLE_MODE = 1
4872 19:26:43.340044 LP45_APHY_COMB_EN = 1
4873 19:26:43.343327 TX_ODT_DIS = 1
4874 19:26:43.346800 NEW_8X_MODE = 1
4875 19:26:43.350122 ===================================
4876 19:26:43.353417 ===================================
4877 19:26:43.356840 data_rate = 1866
4878 19:26:43.360180 CKR = 1
4879 19:26:43.362825 DQ_P2S_RATIO = 8
4880 19:26:43.366248 ===================================
4881 19:26:43.366342 CA_P2S_RATIO = 8
4882 19:26:43.369514 DQ_CA_OPEN = 0
4883 19:26:43.372757 DQ_SEMI_OPEN = 0
4884 19:26:43.376624 CA_SEMI_OPEN = 0
4885 19:26:43.379804 CA_FULL_RATE = 0
4886 19:26:43.383112 DQ_CKDIV4_EN = 1
4887 19:26:43.383195 CA_CKDIV4_EN = 1
4888 19:26:43.386246 CA_PREDIV_EN = 0
4889 19:26:43.389885 PH8_DLY = 0
4890 19:26:43.393094 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4891 19:26:43.396227 DQ_AAMCK_DIV = 4
4892 19:26:43.399530 CA_AAMCK_DIV = 4
4893 19:26:43.399612 CA_ADMCK_DIV = 4
4894 19:26:43.402727 DQ_TRACK_CA_EN = 0
4895 19:26:43.406599 CA_PICK = 933
4896 19:26:43.409362 CA_MCKIO = 933
4897 19:26:43.413224 MCKIO_SEMI = 0
4898 19:26:43.416373 PLL_FREQ = 3732
4899 19:26:43.419811 DQ_UI_PI_RATIO = 32
4900 19:26:43.419895 CA_UI_PI_RATIO = 0
4901 19:26:43.423025 ===================================
4902 19:26:43.426240 ===================================
4903 19:26:43.429653 memory_type:LPDDR4
4904 19:26:43.433110 GP_NUM : 10
4905 19:26:43.433193 SRAM_EN : 1
4906 19:26:43.436322 MD32_EN : 0
4907 19:26:43.439490 ===================================
4908 19:26:43.442807 [ANA_INIT] >>>>>>>>>>>>>>
4909 19:26:43.442890 <<<<<< [CONFIGURE PHASE]: ANA_TX
4910 19:26:43.449521 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4911 19:26:43.452845 ===================================
4912 19:26:43.452928 data_rate = 1866,PCW = 0X8f00
4913 19:26:43.456075 ===================================
4914 19:26:43.459454 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4915 19:26:43.466248 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4916 19:26:43.472920 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4917 19:26:43.476236 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4918 19:26:43.479568 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4919 19:26:43.482789 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4920 19:26:43.486139 [ANA_INIT] flow start
4921 19:26:43.486242 [ANA_INIT] PLL >>>>>>>>
4922 19:26:43.489403 [ANA_INIT] PLL <<<<<<<<
4923 19:26:43.492674 [ANA_INIT] MIDPI >>>>>>>>
4924 19:26:43.495970 [ANA_INIT] MIDPI <<<<<<<<
4925 19:26:43.496050 [ANA_INIT] DLL >>>>>>>>
4926 19:26:43.499496 [ANA_INIT] flow end
4927 19:26:43.502728 ============ LP4 DIFF to SE enter ============
4928 19:26:43.505787 ============ LP4 DIFF to SE exit ============
4929 19:26:43.509435 [ANA_INIT] <<<<<<<<<<<<<
4930 19:26:43.512691 [Flow] Enable top DCM control >>>>>
4931 19:26:43.515955 [Flow] Enable top DCM control <<<<<
4932 19:26:43.519254 Enable DLL master slave shuffle
4933 19:26:43.526183 ==============================================================
4934 19:26:43.526321 Gating Mode config
4935 19:26:43.532757 ==============================================================
4936 19:26:43.532841 Config description:
4937 19:26:43.542509 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4938 19:26:43.549414 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4939 19:26:43.555488 SELPH_MODE 0: By rank 1: By Phase
4940 19:26:43.558884 ==============================================================
4941 19:26:43.562198 GAT_TRACK_EN = 1
4942 19:26:43.565533 RX_GATING_MODE = 2
4943 19:26:43.568924 RX_GATING_TRACK_MODE = 2
4944 19:26:43.572538 SELPH_MODE = 1
4945 19:26:43.575266 PICG_EARLY_EN = 1
4946 19:26:43.578558 VALID_LAT_VALUE = 1
4947 19:26:43.582053 ==============================================================
4948 19:26:43.585406 Enter into Gating configuration >>>>
4949 19:26:43.588775 Exit from Gating configuration <<<<
4950 19:26:43.592175 Enter into DVFS_PRE_config >>>>>
4951 19:26:43.605719 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4952 19:26:43.608386 Exit from DVFS_PRE_config <<<<<
4953 19:26:43.612007 Enter into PICG configuration >>>>
4954 19:26:43.615249 Exit from PICG configuration <<<<
4955 19:26:43.615336 [RX_INPUT] configuration >>>>>
4956 19:26:43.618408 [RX_INPUT] configuration <<<<<
4957 19:26:43.625202 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4958 19:26:43.628755 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4959 19:26:43.635060 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4960 19:26:43.641703 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4961 19:26:43.648464 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4962 19:26:43.655256 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4963 19:26:43.658704 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4964 19:26:43.662162 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4965 19:26:43.668490 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4966 19:26:43.671825 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4967 19:26:43.675310 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4968 19:26:43.678771 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4969 19:26:43.681519 ===================================
4970 19:26:43.685099 LPDDR4 DRAM CONFIGURATION
4971 19:26:43.688608 ===================================
4972 19:26:43.692101 EX_ROW_EN[0] = 0x0
4973 19:26:43.692206 EX_ROW_EN[1] = 0x0
4974 19:26:43.694887 LP4Y_EN = 0x0
4975 19:26:43.694964 WORK_FSP = 0x0
4976 19:26:43.698223 WL = 0x3
4977 19:26:43.698334 RL = 0x3
4978 19:26:43.702198 BL = 0x2
4979 19:26:43.702306 RPST = 0x0
4980 19:26:43.705502 RD_PRE = 0x0
4981 19:26:43.705602 WR_PRE = 0x1
4982 19:26:43.708814 WR_PST = 0x0
4983 19:26:43.708911 DBI_WR = 0x0
4984 19:26:43.711409 DBI_RD = 0x0
4985 19:26:43.711513 OTF = 0x1
4986 19:26:43.715296 ===================================
4987 19:26:43.722115 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4988 19:26:43.724923 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4989 19:26:43.728395 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4990 19:26:43.731938 ===================================
4991 19:26:43.735051 LPDDR4 DRAM CONFIGURATION
4992 19:26:43.738063 ===================================
4993 19:26:43.741394 EX_ROW_EN[0] = 0x10
4994 19:26:43.741496 EX_ROW_EN[1] = 0x0
4995 19:26:43.744701 LP4Y_EN = 0x0
4996 19:26:43.744776 WORK_FSP = 0x0
4997 19:26:43.747882 WL = 0x3
4998 19:26:43.747983 RL = 0x3
4999 19:26:43.751503 BL = 0x2
5000 19:26:43.751616 RPST = 0x0
5001 19:26:43.754603 RD_PRE = 0x0
5002 19:26:43.754681 WR_PRE = 0x1
5003 19:26:43.758279 WR_PST = 0x0
5004 19:26:43.758395 DBI_WR = 0x0
5005 19:26:43.761517 DBI_RD = 0x0
5006 19:26:43.761621 OTF = 0x1
5007 19:26:43.764542 ===================================
5008 19:26:43.771579 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5009 19:26:43.775709 nWR fixed to 30
5010 19:26:43.779208 [ModeRegInit_LP4] CH0 RK0
5011 19:26:43.779313 [ModeRegInit_LP4] CH0 RK1
5012 19:26:43.782589 [ModeRegInit_LP4] CH1 RK0
5013 19:26:43.785949 [ModeRegInit_LP4] CH1 RK1
5014 19:26:43.786049 match AC timing 9
5015 19:26:43.792759 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5016 19:26:43.796317 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5017 19:26:43.799015 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5018 19:26:43.805591 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5019 19:26:43.809000 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5020 19:26:43.809114 ==
5021 19:26:43.812558 Dram Type= 6, Freq= 0, CH_0, rank 0
5022 19:26:43.815862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5023 19:26:43.815966 ==
5024 19:26:43.822382 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5025 19:26:43.828948 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5026 19:26:43.832194 [CA 0] Center 37 (6~68) winsize 63
5027 19:26:43.835624 [CA 1] Center 37 (7~68) winsize 62
5028 19:26:43.838941 [CA 2] Center 34 (4~65) winsize 62
5029 19:26:43.842319 [CA 3] Center 34 (3~65) winsize 63
5030 19:26:43.845609 [CA 4] Center 33 (3~64) winsize 62
5031 19:26:43.849349 [CA 5] Center 32 (2~62) winsize 61
5032 19:26:43.849426
5033 19:26:43.852589 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5034 19:26:43.852687
5035 19:26:43.855817 [CATrainingPosCal] consider 1 rank data
5036 19:26:43.858925 u2DelayCellTimex100 = 270/100 ps
5037 19:26:43.862512 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5038 19:26:43.865537 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5039 19:26:43.868667 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5040 19:26:43.872257 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5041 19:26:43.875355 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5042 19:26:43.881904 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5043 19:26:43.882005
5044 19:26:43.885341 CA PerBit enable=1, Macro0, CA PI delay=32
5045 19:26:43.885444
5046 19:26:43.888666 [CBTSetCACLKResult] CA Dly = 32
5047 19:26:43.888765 CS Dly: 5 (0~36)
5048 19:26:43.888855 ==
5049 19:26:43.892150 Dram Type= 6, Freq= 0, CH_0, rank 1
5050 19:26:43.894960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5051 19:26:43.898552 ==
5052 19:26:43.901951 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5053 19:26:43.908743 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5054 19:26:43.912121 [CA 0] Center 37 (6~68) winsize 63
5055 19:26:43.914917 [CA 1] Center 37 (6~68) winsize 63
5056 19:26:43.918309 [CA 2] Center 34 (4~65) winsize 62
5057 19:26:43.921795 [CA 3] Center 34 (3~65) winsize 63
5058 19:26:43.925318 [CA 4] Center 32 (2~63) winsize 62
5059 19:26:43.928082 [CA 5] Center 32 (2~62) winsize 61
5060 19:26:43.928179
5061 19:26:43.931976 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5062 19:26:43.932045
5063 19:26:43.935123 [CATrainingPosCal] consider 2 rank data
5064 19:26:43.938666 u2DelayCellTimex100 = 270/100 ps
5065 19:26:43.941410 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5066 19:26:43.944860 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5067 19:26:43.948198 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5068 19:26:43.954660 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5069 19:26:43.957963 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5070 19:26:43.961338 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5071 19:26:43.961433
5072 19:26:43.964794 CA PerBit enable=1, Macro0, CA PI delay=32
5073 19:26:43.964889
5074 19:26:43.968202 [CBTSetCACLKResult] CA Dly = 32
5075 19:26:43.968272 CS Dly: 5 (0~37)
5076 19:26:43.968335
5077 19:26:43.971320 ----->DramcWriteLeveling(PI) begin...
5078 19:26:43.974915 ==
5079 19:26:43.975010 Dram Type= 6, Freq= 0, CH_0, rank 0
5080 19:26:43.981451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5081 19:26:43.981524 ==
5082 19:26:43.985024 Write leveling (Byte 0): 35 => 35
5083 19:26:43.988324 Write leveling (Byte 1): 28 => 28
5084 19:26:43.991475 DramcWriteLeveling(PI) end<-----
5085 19:26:43.991546
5086 19:26:43.991606 ==
5087 19:26:43.994435 Dram Type= 6, Freq= 0, CH_0, rank 0
5088 19:26:43.997874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5089 19:26:43.997974 ==
5090 19:26:44.000981 [Gating] SW mode calibration
5091 19:26:44.007803 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5092 19:26:44.014525 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5093 19:26:44.017837 0 14 0 | B1->B0 | 2626 3434 | 1 1 | (1 1) (1 1)
5094 19:26:44.021226 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5095 19:26:44.024555 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5096 19:26:44.031312 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5097 19:26:44.034826 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5098 19:26:44.038019 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5099 19:26:44.044230 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5100 19:26:44.047559 0 14 28 | B1->B0 | 3434 2929 | 1 0 | (1 0) (0 0)
5101 19:26:44.050829 0 15 0 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (0 0)
5102 19:26:44.057448 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5103 19:26:44.060714 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5104 19:26:44.064538 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5105 19:26:44.071327 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5106 19:26:44.074108 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5107 19:26:44.077441 0 15 24 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
5108 19:26:44.084274 0 15 28 | B1->B0 | 2626 3b3b | 0 0 | (0 0) (0 0)
5109 19:26:44.087697 1 0 0 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5110 19:26:44.090796 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5111 19:26:44.097403 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5112 19:26:44.100705 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5113 19:26:44.104482 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5114 19:26:44.110570 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5115 19:26:44.113941 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5116 19:26:44.117251 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5117 19:26:44.124017 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5118 19:26:44.127618 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5119 19:26:44.130896 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5120 19:26:44.137697 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5121 19:26:44.140527 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5122 19:26:44.144073 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5123 19:26:44.147334 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5124 19:26:44.154264 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5125 19:26:44.157596 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 19:26:44.161138 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 19:26:44.167097 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 19:26:44.170497 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 19:26:44.174397 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 19:26:44.180489 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 19:26:44.183850 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5132 19:26:44.187520 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5133 19:26:44.191002 Total UI for P1: 0, mck2ui 16
5134 19:26:44.194244 best dqsien dly found for B0: ( 1, 2, 24)
5135 19:26:44.200796 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5136 19:26:44.204126 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5137 19:26:44.207529 Total UI for P1: 0, mck2ui 16
5138 19:26:44.210161 best dqsien dly found for B1: ( 1, 2, 30)
5139 19:26:44.213601 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5140 19:26:44.217111 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5141 19:26:44.217210
5142 19:26:44.220389 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5143 19:26:44.223484 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5144 19:26:44.227191 [Gating] SW calibration Done
5145 19:26:44.227275 ==
5146 19:26:44.230426 Dram Type= 6, Freq= 0, CH_0, rank 0
5147 19:26:44.236726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5148 19:26:44.236868 ==
5149 19:26:44.236960 RX Vref Scan: 0
5150 19:26:44.237078
5151 19:26:44.240175 RX Vref 0 -> 0, step: 1
5152 19:26:44.240312
5153 19:26:44.243627 RX Delay -80 -> 252, step: 8
5154 19:26:44.247116 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5155 19:26:44.249847 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5156 19:26:44.253209 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5157 19:26:44.256751 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5158 19:26:44.263280 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5159 19:26:44.267024 iDelay=208, Bit 5, Center 95 (8 ~ 183) 176
5160 19:26:44.269962 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5161 19:26:44.273335 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5162 19:26:44.276617 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5163 19:26:44.280109 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5164 19:26:44.286451 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5165 19:26:44.289922 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5166 19:26:44.293348 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5167 19:26:44.296810 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5168 19:26:44.299616 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5169 19:26:44.303095 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5170 19:26:44.306318 ==
5171 19:26:44.309731 Dram Type= 6, Freq= 0, CH_0, rank 0
5172 19:26:44.313109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5173 19:26:44.313214 ==
5174 19:26:44.313308 DQS Delay:
5175 19:26:44.316610 DQS0 = 0, DQS1 = 0
5176 19:26:44.316706 DQM Delay:
5177 19:26:44.319684 DQM0 = 105, DQM1 = 93
5178 19:26:44.319786 DQ Delay:
5179 19:26:44.323569 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5180 19:26:44.326211 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5181 19:26:44.329618 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =91
5182 19:26:44.332948 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5183 19:26:44.333056
5184 19:26:44.333147
5185 19:26:44.333238 ==
5186 19:26:44.336271 Dram Type= 6, Freq= 0, CH_0, rank 0
5187 19:26:44.339912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5188 19:26:44.340016 ==
5189 19:26:44.340113
5190 19:26:44.343163
5191 19:26:44.343239 TX Vref Scan disable
5192 19:26:44.346526 == TX Byte 0 ==
5193 19:26:44.349842 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5194 19:26:44.353134 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5195 19:26:44.356374 == TX Byte 1 ==
5196 19:26:44.359834 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5197 19:26:44.362642 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5198 19:26:44.362717 ==
5199 19:26:44.366235 Dram Type= 6, Freq= 0, CH_0, rank 0
5200 19:26:44.372636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5201 19:26:44.372744 ==
5202 19:26:44.372835
5203 19:26:44.372933
5204 19:26:44.373021 TX Vref Scan disable
5205 19:26:44.376891 == TX Byte 0 ==
5206 19:26:44.380804 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5207 19:26:44.386947 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5208 19:26:44.387028 == TX Byte 1 ==
5209 19:26:44.390413 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5210 19:26:44.397139 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5211 19:26:44.397244
5212 19:26:44.397336 [DATLAT]
5213 19:26:44.397426 Freq=933, CH0 RK0
5214 19:26:44.397514
5215 19:26:44.400625 DATLAT Default: 0xd
5216 19:26:44.400700 0, 0xFFFF, sum = 0
5217 19:26:44.404082 1, 0xFFFF, sum = 0
5218 19:26:44.404159 2, 0xFFFF, sum = 0
5219 19:26:44.406859 3, 0xFFFF, sum = 0
5220 19:26:44.410469 4, 0xFFFF, sum = 0
5221 19:26:44.410580 5, 0xFFFF, sum = 0
5222 19:26:44.413878 6, 0xFFFF, sum = 0
5223 19:26:44.413987 7, 0xFFFF, sum = 0
5224 19:26:44.416764 8, 0xFFFF, sum = 0
5225 19:26:44.416867 9, 0xFFFF, sum = 0
5226 19:26:44.420216 10, 0x0, sum = 1
5227 19:26:44.420322 11, 0x0, sum = 2
5228 19:26:44.423822 12, 0x0, sum = 3
5229 19:26:44.423927 13, 0x0, sum = 4
5230 19:26:44.424021 best_step = 11
5231 19:26:44.424109
5232 19:26:44.426869 ==
5233 19:26:44.430059 Dram Type= 6, Freq= 0, CH_0, rank 0
5234 19:26:44.433945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5235 19:26:44.434051 ==
5236 19:26:44.434150 RX Vref Scan: 1
5237 19:26:44.434240
5238 19:26:44.437180 RX Vref 0 -> 0, step: 1
5239 19:26:44.437281
5240 19:26:44.440305 RX Delay -53 -> 252, step: 4
5241 19:26:44.440414
5242 19:26:44.443862 Set Vref, RX VrefLevel [Byte0]: 54
5243 19:26:44.446557 [Byte1]: 46
5244 19:26:44.446635
5245 19:26:44.450062 Final RX Vref Byte 0 = 54 to rank0
5246 19:26:44.453432 Final RX Vref Byte 1 = 46 to rank0
5247 19:26:44.456769 Final RX Vref Byte 0 = 54 to rank1
5248 19:26:44.460160 Final RX Vref Byte 1 = 46 to rank1==
5249 19:26:44.463544 Dram Type= 6, Freq= 0, CH_0, rank 0
5250 19:26:44.466849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5251 19:26:44.469821 ==
5252 19:26:44.469923 DQS Delay:
5253 19:26:44.470014 DQS0 = 0, DQS1 = 0
5254 19:26:44.473389 DQM Delay:
5255 19:26:44.473512 DQM0 = 104, DQM1 = 94
5256 19:26:44.476704 DQ Delay:
5257 19:26:44.480169 DQ0 =104, DQ1 =104, DQ2 =102, DQ3 =102
5258 19:26:44.483700 DQ4 =104, DQ5 =96, DQ6 =114, DQ7 =110
5259 19:26:44.486423 DQ8 =84, DQ9 =84, DQ10 =96, DQ11 =88
5260 19:26:44.490357 DQ12 =100, DQ13 =98, DQ14 =106, DQ15 =102
5261 19:26:44.490458
5262 19:26:44.490561
5263 19:26:44.496695 [DQSOSCAuto] RK0, (LSB)MR18= 0x322a, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 406 ps
5264 19:26:44.499827 CH0 RK0: MR19=505, MR18=322A
5265 19:26:44.506319 CH0_RK0: MR19=0x505, MR18=0x322A, DQSOSC=406, MR23=63, INC=65, DEC=43
5266 19:26:44.506417
5267 19:26:44.509883 ----->DramcWriteLeveling(PI) begin...
5268 19:26:44.509968 ==
5269 19:26:44.513348 Dram Type= 6, Freq= 0, CH_0, rank 1
5270 19:26:44.516973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5271 19:26:44.517078 ==
5272 19:26:44.519849 Write leveling (Byte 0): 33 => 33
5273 19:26:44.523378 Write leveling (Byte 1): 29 => 29
5274 19:26:44.526865 DramcWriteLeveling(PI) end<-----
5275 19:26:44.526940
5276 19:26:44.527002 ==
5277 19:26:44.529622 Dram Type= 6, Freq= 0, CH_0, rank 1
5278 19:26:44.533326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5279 19:26:44.533407 ==
5280 19:26:44.536622 [Gating] SW mode calibration
5281 19:26:44.543358 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5282 19:26:44.549720 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5283 19:26:44.553035 0 14 0 | B1->B0 | 3434 3131 | 0 0 | (0 0) (1 1)
5284 19:26:44.559576 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5285 19:26:44.563031 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5286 19:26:44.566439 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5287 19:26:44.573153 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5288 19:26:44.576368 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5289 19:26:44.579654 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5290 19:26:44.585892 0 14 28 | B1->B0 | 2626 2f2f | 1 0 | (1 0) (0 1)
5291 19:26:44.589245 0 15 0 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
5292 19:26:44.592745 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5293 19:26:44.599537 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5294 19:26:44.602827 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5295 19:26:44.606123 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5296 19:26:44.612595 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5297 19:26:44.616213 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5298 19:26:44.619505 0 15 28 | B1->B0 | 3838 3636 | 0 1 | (0 0) (0 0)
5299 19:26:44.622917 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5300 19:26:44.629671 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5301 19:26:44.633115 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5302 19:26:44.636382 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5303 19:26:44.642679 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5304 19:26:44.646443 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5305 19:26:44.649733 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5306 19:26:44.656138 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5307 19:26:44.659582 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5308 19:26:44.662753 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5309 19:26:44.669490 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5310 19:26:44.672878 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5311 19:26:44.676322 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5312 19:26:44.682405 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5313 19:26:44.685939 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5314 19:26:44.689241 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5315 19:26:44.695812 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5316 19:26:44.698993 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5317 19:26:44.702790 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5318 19:26:44.709133 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 19:26:44.712336 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 19:26:44.715647 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 19:26:44.722616 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 19:26:44.725413 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5323 19:26:44.729089 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5324 19:26:44.732097 Total UI for P1: 0, mck2ui 16
5325 19:26:44.735827 best dqsien dly found for B1: ( 1, 2, 28)
5326 19:26:44.742497 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5327 19:26:44.742587 Total UI for P1: 0, mck2ui 16
5328 19:26:44.745830 best dqsien dly found for B0: ( 1, 3, 0)
5329 19:26:44.752295 best DQS0 dly(MCK, UI, PI) = (1, 3, 0)
5330 19:26:44.755419 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5331 19:26:44.755500
5332 19:26:44.758580 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 0)
5333 19:26:44.762306 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5334 19:26:44.765667 [Gating] SW calibration Done
5335 19:26:44.765747 ==
5336 19:26:44.768998 Dram Type= 6, Freq= 0, CH_0, rank 1
5337 19:26:44.772466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5338 19:26:44.772584 ==
5339 19:26:44.775655 RX Vref Scan: 0
5340 19:26:44.775751
5341 19:26:44.775828 RX Vref 0 -> 0, step: 1
5342 19:26:44.775888
5343 19:26:44.779036 RX Delay -80 -> 252, step: 8
5344 19:26:44.782446 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5345 19:26:44.785850 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5346 19:26:44.791907 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5347 19:26:44.795406 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5348 19:26:44.798791 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5349 19:26:44.802237 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5350 19:26:44.805725 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5351 19:26:44.809245 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5352 19:26:44.815450 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5353 19:26:44.818835 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5354 19:26:44.822218 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5355 19:26:44.825172 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5356 19:26:44.828396 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5357 19:26:44.832145 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5358 19:26:44.838749 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5359 19:26:44.841576 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5360 19:26:44.841654 ==
5361 19:26:44.845255 Dram Type= 6, Freq= 0, CH_0, rank 1
5362 19:26:44.848402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5363 19:26:44.848472 ==
5364 19:26:44.851970 DQS Delay:
5365 19:26:44.852044 DQS0 = 0, DQS1 = 0
5366 19:26:44.852118 DQM Delay:
5367 19:26:44.855277 DQM0 = 105, DQM1 = 93
5368 19:26:44.855351 DQ Delay:
5369 19:26:44.858367 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5370 19:26:44.861986 DQ4 =107, DQ5 =99, DQ6 =111, DQ7 =115
5371 19:26:44.865492 DQ8 =87, DQ9 =83, DQ10 =95, DQ11 =87
5372 19:26:44.868759 DQ12 =95, DQ13 =99, DQ14 =103, DQ15 =99
5373 19:26:44.868855
5374 19:26:44.868942
5375 19:26:44.869038 ==
5376 19:26:44.871708 Dram Type= 6, Freq= 0, CH_0, rank 1
5377 19:26:44.878288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5378 19:26:44.878403 ==
5379 19:26:44.878478
5380 19:26:44.878542
5381 19:26:44.882164 TX Vref Scan disable
5382 19:26:44.882267 == TX Byte 0 ==
5383 19:26:44.885420 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5384 19:26:44.891796 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5385 19:26:44.891870 == TX Byte 1 ==
5386 19:26:44.895435 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5387 19:26:44.901635 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5388 19:26:44.901717 ==
5389 19:26:44.905244 Dram Type= 6, Freq= 0, CH_0, rank 1
5390 19:26:44.907967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5391 19:26:44.908044 ==
5392 19:26:44.908106
5393 19:26:44.908191
5394 19:26:44.911444 TX Vref Scan disable
5395 19:26:44.914777 == TX Byte 0 ==
5396 19:26:44.918324 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5397 19:26:44.921858 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5398 19:26:44.924704 == TX Byte 1 ==
5399 19:26:44.927996 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5400 19:26:44.931769 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5401 19:26:44.931851
5402 19:26:44.935121 [DATLAT]
5403 19:26:44.935195 Freq=933, CH0 RK1
5404 19:26:44.935260
5405 19:26:44.938570 DATLAT Default: 0xb
5406 19:26:44.938647 0, 0xFFFF, sum = 0
5407 19:26:44.941309 1, 0xFFFF, sum = 0
5408 19:26:44.941412 2, 0xFFFF, sum = 0
5409 19:26:44.944752 3, 0xFFFF, sum = 0
5410 19:26:44.944858 4, 0xFFFF, sum = 0
5411 19:26:44.948182 5, 0xFFFF, sum = 0
5412 19:26:44.948272 6, 0xFFFF, sum = 0
5413 19:26:44.951603 7, 0xFFFF, sum = 0
5414 19:26:44.951729 8, 0xFFFF, sum = 0
5415 19:26:44.954770 9, 0xFFFF, sum = 0
5416 19:26:44.954845 10, 0x0, sum = 1
5417 19:26:44.958024 11, 0x0, sum = 2
5418 19:26:44.958097 12, 0x0, sum = 3
5419 19:26:44.961372 13, 0x0, sum = 4
5420 19:26:44.961549 best_step = 11
5421 19:26:44.961718
5422 19:26:44.961848 ==
5423 19:26:44.965056 Dram Type= 6, Freq= 0, CH_0, rank 1
5424 19:26:44.968183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5425 19:26:44.971639 ==
5426 19:26:44.971771 RX Vref Scan: 0
5427 19:26:44.971850
5428 19:26:44.974990 RX Vref 0 -> 0, step: 1
5429 19:26:44.975093
5430 19:26:44.975192 RX Delay -53 -> 252, step: 4
5431 19:26:44.982826 iDelay=199, Bit 0, Center 102 (15 ~ 190) 176
5432 19:26:44.986423 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5433 19:26:44.989614 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5434 19:26:44.992566 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5435 19:26:44.996249 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5436 19:26:45.002889 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5437 19:26:45.006104 iDelay=199, Bit 6, Center 108 (23 ~ 194) 172
5438 19:26:45.009529 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5439 19:26:45.012921 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5440 19:26:45.015702 iDelay=199, Bit 9, Center 82 (-1 ~ 166) 168
5441 19:26:45.022739 iDelay=199, Bit 10, Center 92 (11 ~ 174) 164
5442 19:26:45.026356 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164
5443 19:26:45.029145 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5444 19:26:45.032654 iDelay=199, Bit 13, Center 98 (15 ~ 182) 168
5445 19:26:45.035987 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5446 19:26:45.042856 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5447 19:26:45.042937 ==
5448 19:26:45.045583 Dram Type= 6, Freq= 0, CH_0, rank 1
5449 19:26:45.049119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5450 19:26:45.049242 ==
5451 19:26:45.049345 DQS Delay:
5452 19:26:45.052759 DQS0 = 0, DQS1 = 0
5453 19:26:45.052877 DQM Delay:
5454 19:26:45.055695 DQM0 = 104, DQM1 = 93
5455 19:26:45.055814 DQ Delay:
5456 19:26:45.059170 DQ0 =102, DQ1 =106, DQ2 =102, DQ3 =102
5457 19:26:45.062619 DQ4 =106, DQ5 =98, DQ6 =108, DQ7 =112
5458 19:26:45.065884 DQ8 =84, DQ9 =82, DQ10 =92, DQ11 =88
5459 19:26:45.069364 DQ12 =100, DQ13 =98, DQ14 =102, DQ15 =102
5460 19:26:45.069452
5461 19:26:45.069519
5462 19:26:45.079122 [DQSOSCAuto] RK1, (LSB)MR18= 0x2a02, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 408 ps
5463 19:26:45.082265 CH0 RK1: MR19=505, MR18=2A02
5464 19:26:45.085401 CH0_RK1: MR19=0x505, MR18=0x2A02, DQSOSC=408, MR23=63, INC=65, DEC=43
5465 19:26:45.088768 [RxdqsGatingPostProcess] freq 933
5466 19:26:45.095774 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5467 19:26:45.098620 best DQS0 dly(2T, 0.5T) = (0, 10)
5468 19:26:45.102158 best DQS1 dly(2T, 0.5T) = (0, 10)
5469 19:26:45.105524 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5470 19:26:45.108666 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5471 19:26:45.112490 best DQS0 dly(2T, 0.5T) = (0, 11)
5472 19:26:45.115504 best DQS1 dly(2T, 0.5T) = (0, 10)
5473 19:26:45.118958 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5474 19:26:45.121829 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5475 19:26:45.121910 Pre-setting of DQS Precalculation
5476 19:26:45.128601 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5477 19:26:45.128684 ==
5478 19:26:45.132313 Dram Type= 6, Freq= 0, CH_1, rank 0
5479 19:26:45.135902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5480 19:26:45.135984 ==
5481 19:26:45.141965 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5482 19:26:45.148780 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5483 19:26:45.152184 [CA 0] Center 36 (6~67) winsize 62
5484 19:26:45.155014 [CA 1] Center 36 (6~67) winsize 62
5485 19:26:45.158491 [CA 2] Center 34 (4~65) winsize 62
5486 19:26:45.162026 [CA 3] Center 34 (4~65) winsize 62
5487 19:26:45.165496 [CA 4] Center 34 (4~64) winsize 61
5488 19:26:45.168935 [CA 5] Center 33 (3~64) winsize 62
5489 19:26:45.169037
5490 19:26:45.171779 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5491 19:26:45.171887
5492 19:26:45.175419 [CATrainingPosCal] consider 1 rank data
5493 19:26:45.178752 u2DelayCellTimex100 = 270/100 ps
5494 19:26:45.182153 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5495 19:26:45.185460 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5496 19:26:45.188752 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5497 19:26:45.192103 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5498 19:26:45.194855 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5499 19:26:45.198231 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5500 19:26:45.198345
5501 19:26:45.205094 CA PerBit enable=1, Macro0, CA PI delay=33
5502 19:26:45.205222
5503 19:26:45.205322 [CBTSetCACLKResult] CA Dly = 33
5504 19:26:45.208556 CS Dly: 7 (0~38)
5505 19:26:45.208669 ==
5506 19:26:45.212215 Dram Type= 6, Freq= 0, CH_1, rank 1
5507 19:26:45.215649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5508 19:26:45.215760 ==
5509 19:26:45.221866 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5510 19:26:45.228612 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5511 19:26:45.231875 [CA 0] Center 36 (6~67) winsize 62
5512 19:26:45.234939 [CA 1] Center 37 (7~68) winsize 62
5513 19:26:45.238179 [CA 2] Center 35 (5~65) winsize 61
5514 19:26:45.241503 [CA 3] Center 34 (4~65) winsize 62
5515 19:26:45.244927 [CA 4] Center 34 (4~65) winsize 62
5516 19:26:45.248448 [CA 5] Center 33 (3~64) winsize 62
5517 19:26:45.248548
5518 19:26:45.251456 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5519 19:26:45.251557
5520 19:26:45.254998 [CATrainingPosCal] consider 2 rank data
5521 19:26:45.257923 u2DelayCellTimex100 = 270/100 ps
5522 19:26:45.261848 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5523 19:26:45.264613 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5524 19:26:45.268198 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5525 19:26:45.271600 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5526 19:26:45.274587 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5527 19:26:45.281498 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5528 19:26:45.281616
5529 19:26:45.284898 CA PerBit enable=1, Macro0, CA PI delay=33
5530 19:26:45.285000
5531 19:26:45.288341 [CBTSetCACLKResult] CA Dly = 33
5532 19:26:45.288455 CS Dly: 8 (0~40)
5533 19:26:45.288549
5534 19:26:45.290978 ----->DramcWriteLeveling(PI) begin...
5535 19:26:45.291088 ==
5536 19:26:45.294542 Dram Type= 6, Freq= 0, CH_1, rank 0
5537 19:26:45.301424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5538 19:26:45.301509 ==
5539 19:26:45.304259 Write leveling (Byte 0): 25 => 25
5540 19:26:45.304347 Write leveling (Byte 1): 27 => 27
5541 19:26:45.308168 DramcWriteLeveling(PI) end<-----
5542 19:26:45.308250
5543 19:26:45.308314 ==
5544 19:26:45.311265 Dram Type= 6, Freq= 0, CH_1, rank 0
5545 19:26:45.317774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5546 19:26:45.317860 ==
5547 19:26:45.321453 [Gating] SW mode calibration
5548 19:26:45.327538 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5549 19:26:45.330883 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5550 19:26:45.337786 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5551 19:26:45.341388 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5552 19:26:45.344178 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5553 19:26:45.351098 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5554 19:26:45.354255 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5555 19:26:45.357548 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5556 19:26:45.364122 0 14 24 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
5557 19:26:45.367314 0 14 28 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (1 0)
5558 19:26:45.371131 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5559 19:26:45.377471 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5560 19:26:45.380739 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5561 19:26:45.384060 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5562 19:26:45.390718 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5563 19:26:45.393978 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5564 19:26:45.397291 0 15 24 | B1->B0 | 2626 3636 | 0 0 | (0 0) (0 0)
5565 19:26:45.400834 0 15 28 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
5566 19:26:45.407232 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5567 19:26:45.410891 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5568 19:26:45.414276 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5569 19:26:45.420550 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5570 19:26:45.423801 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5571 19:26:45.426920 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5572 19:26:45.433782 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5573 19:26:45.437304 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5574 19:26:45.440523 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5575 19:26:45.447253 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5576 19:26:45.450603 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5577 19:26:45.453965 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5578 19:26:45.460364 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5579 19:26:45.463581 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5580 19:26:45.467053 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 19:26:45.473822 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 19:26:45.477133 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 19:26:45.480693 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 19:26:45.487205 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 19:26:45.490382 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 19:26:45.493321 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 19:26:45.500382 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 19:26:45.503442 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 19:26:45.507039 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5590 19:26:45.510239 Total UI for P1: 0, mck2ui 16
5591 19:26:45.513684 best dqsien dly found for B0: ( 1, 2, 26)
5592 19:26:45.519900 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5593 19:26:45.520020 Total UI for P1: 0, mck2ui 16
5594 19:26:45.523287 best dqsien dly found for B1: ( 1, 2, 28)
5595 19:26:45.529852 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5596 19:26:45.533402 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5597 19:26:45.533509
5598 19:26:45.536810 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5599 19:26:45.540137 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5600 19:26:45.543265 [Gating] SW calibration Done
5601 19:26:45.543343 ==
5602 19:26:45.546840 Dram Type= 6, Freq= 0, CH_1, rank 0
5603 19:26:45.550278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5604 19:26:45.550407 ==
5605 19:26:45.553514 RX Vref Scan: 0
5606 19:26:45.553610
5607 19:26:45.553705 RX Vref 0 -> 0, step: 1
5608 19:26:45.553799
5609 19:26:45.556931 RX Delay -80 -> 252, step: 8
5610 19:26:45.560205 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5611 19:26:45.563384 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5612 19:26:45.570120 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5613 19:26:45.573217 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5614 19:26:45.577170 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5615 19:26:45.580015 iDelay=208, Bit 5, Center 119 (32 ~ 207) 176
5616 19:26:45.583404 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5617 19:26:45.586824 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5618 19:26:45.593594 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5619 19:26:45.596888 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5620 19:26:45.600245 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5621 19:26:45.603394 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5622 19:26:45.606708 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5623 19:26:45.613459 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5624 19:26:45.616504 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5625 19:26:45.619951 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5626 19:26:45.620028 ==
5627 19:26:45.623196 Dram Type= 6, Freq= 0, CH_1, rank 0
5628 19:26:45.626236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5629 19:26:45.626371 ==
5630 19:26:45.630287 DQS Delay:
5631 19:26:45.630413 DQS0 = 0, DQS1 = 0
5632 19:26:45.633026 DQM Delay:
5633 19:26:45.633104 DQM0 = 103, DQM1 = 98
5634 19:26:45.633169 DQ Delay:
5635 19:26:45.636333 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5636 19:26:45.639777 DQ4 =99, DQ5 =119, DQ6 =111, DQ7 =103
5637 19:26:45.643110 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5638 19:26:45.649819 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5639 19:26:45.649896
5640 19:26:45.649964
5641 19:26:45.650025 ==
5642 19:26:45.653113 Dram Type= 6, Freq= 0, CH_1, rank 0
5643 19:26:45.656295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5644 19:26:45.656383 ==
5645 19:26:45.656445
5646 19:26:45.656508
5647 19:26:45.659408 TX Vref Scan disable
5648 19:26:45.659516 == TX Byte 0 ==
5649 19:26:45.666175 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5650 19:26:45.669965 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5651 19:26:45.670066 == TX Byte 1 ==
5652 19:26:45.676066 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5653 19:26:45.679796 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5654 19:26:45.679881 ==
5655 19:26:45.683075 Dram Type= 6, Freq= 0, CH_1, rank 0
5656 19:26:45.686226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5657 19:26:45.686344 ==
5658 19:26:45.686461
5659 19:26:45.686525
5660 19:26:45.689690 TX Vref Scan disable
5661 19:26:45.693195 == TX Byte 0 ==
5662 19:26:45.696548 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5663 19:26:45.699280 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5664 19:26:45.702661 == TX Byte 1 ==
5665 19:26:45.706088 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5666 19:26:45.709504 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5667 19:26:45.709580
5668 19:26:45.712774 [DATLAT]
5669 19:26:45.712854 Freq=933, CH1 RK0
5670 19:26:45.712916
5671 19:26:45.716065 DATLAT Default: 0xd
5672 19:26:45.716175 0, 0xFFFF, sum = 0
5673 19:26:45.719407 1, 0xFFFF, sum = 0
5674 19:26:45.719484 2, 0xFFFF, sum = 0
5675 19:26:45.722783 3, 0xFFFF, sum = 0
5676 19:26:45.722858 4, 0xFFFF, sum = 0
5677 19:26:45.726199 5, 0xFFFF, sum = 0
5678 19:26:45.726316 6, 0xFFFF, sum = 0
5679 19:26:45.729446 7, 0xFFFF, sum = 0
5680 19:26:45.732453 8, 0xFFFF, sum = 0
5681 19:26:45.732528 9, 0xFFFF, sum = 0
5682 19:26:45.732590 10, 0x0, sum = 1
5683 19:26:45.736067 11, 0x0, sum = 2
5684 19:26:45.736142 12, 0x0, sum = 3
5685 19:26:45.739042 13, 0x0, sum = 4
5686 19:26:45.739123 best_step = 11
5687 19:26:45.739188
5688 19:26:45.739254 ==
5689 19:26:45.742692 Dram Type= 6, Freq= 0, CH_1, rank 0
5690 19:26:45.749315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5691 19:26:45.749411 ==
5692 19:26:45.749475 RX Vref Scan: 1
5693 19:26:45.749534
5694 19:26:45.752496 RX Vref 0 -> 0, step: 1
5695 19:26:45.752571
5696 19:26:45.755912 RX Delay -45 -> 252, step: 4
5697 19:26:45.755985
5698 19:26:45.759321 Set Vref, RX VrefLevel [Byte0]: 54
5699 19:26:45.762619 [Byte1]: 54
5700 19:26:45.762698
5701 19:26:45.765797 Final RX Vref Byte 0 = 54 to rank0
5702 19:26:45.769122 Final RX Vref Byte 1 = 54 to rank0
5703 19:26:45.772443 Final RX Vref Byte 0 = 54 to rank1
5704 19:26:45.775596 Final RX Vref Byte 1 = 54 to rank1==
5705 19:26:45.779242 Dram Type= 6, Freq= 0, CH_1, rank 0
5706 19:26:45.782391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5707 19:26:45.782479 ==
5708 19:26:45.785358 DQS Delay:
5709 19:26:45.785466 DQS0 = 0, DQS1 = 0
5710 19:26:45.788777 DQM Delay:
5711 19:26:45.788877 DQM0 = 103, DQM1 = 100
5712 19:26:45.788978 DQ Delay:
5713 19:26:45.792524 DQ0 =106, DQ1 =98, DQ2 =94, DQ3 =100
5714 19:26:45.798796 DQ4 =102, DQ5 =112, DQ6 =112, DQ7 =104
5715 19:26:45.802050 DQ8 =90, DQ9 =90, DQ10 =100, DQ11 =94
5716 19:26:45.805519 DQ12 =108, DQ13 =108, DQ14 =108, DQ15 =108
5717 19:26:45.805590
5718 19:26:45.805649
5719 19:26:45.812300 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d35, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 412 ps
5720 19:26:45.815581 CH1 RK0: MR19=505, MR18=1D35
5721 19:26:45.822091 CH1_RK0: MR19=0x505, MR18=0x1D35, DQSOSC=405, MR23=63, INC=66, DEC=44
5722 19:26:45.822175
5723 19:26:45.825438 ----->DramcWriteLeveling(PI) begin...
5724 19:26:45.825514 ==
5725 19:26:45.828875 Dram Type= 6, Freq= 0, CH_1, rank 1
5726 19:26:45.832286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5727 19:26:45.832364 ==
5728 19:26:45.834999 Write leveling (Byte 0): 28 => 28
5729 19:26:45.838497 Write leveling (Byte 1): 29 => 29
5730 19:26:45.841810 DramcWriteLeveling(PI) end<-----
5731 19:26:45.841883
5732 19:26:45.841944 ==
5733 19:26:45.845147 Dram Type= 6, Freq= 0, CH_1, rank 1
5734 19:26:45.848348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5735 19:26:45.848448 ==
5736 19:26:45.851980 [Gating] SW mode calibration
5737 19:26:45.858278 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5738 19:26:45.864995 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5739 19:26:45.868542 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5740 19:26:45.875081 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5741 19:26:45.878488 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5742 19:26:45.881785 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5743 19:26:45.888340 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5744 19:26:45.891730 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5745 19:26:45.895024 0 14 24 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 0)
5746 19:26:45.901350 0 14 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 0)
5747 19:26:45.904428 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5748 19:26:45.908108 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5749 19:26:45.914938 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5750 19:26:45.917829 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5751 19:26:45.921235 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5752 19:26:45.927595 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5753 19:26:45.931019 0 15 24 | B1->B0 | 3838 2d2d | 0 0 | (1 1) (0 0)
5754 19:26:45.934338 0 15 28 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
5755 19:26:45.941131 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5756 19:26:45.944525 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5757 19:26:45.947946 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5758 19:26:45.954580 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5759 19:26:45.957851 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5760 19:26:45.960673 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5761 19:26:45.967857 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5762 19:26:45.970446 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5763 19:26:45.973834 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5764 19:26:45.980789 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5765 19:26:45.983810 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5766 19:26:45.987662 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5767 19:26:45.993854 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5768 19:26:45.997199 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5769 19:26:46.000595 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5770 19:26:46.007201 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5771 19:26:46.010235 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 19:26:46.013834 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 19:26:46.017340 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 19:26:46.024353 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 19:26:46.027619 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 19:26:46.030932 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 19:26:46.037122 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5778 19:26:46.040506 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5779 19:26:46.043918 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5780 19:26:46.047232 Total UI for P1: 0, mck2ui 16
5781 19:26:46.050789 best dqsien dly found for B0: ( 1, 2, 26)
5782 19:26:46.054107 Total UI for P1: 0, mck2ui 16
5783 19:26:46.056888 best dqsien dly found for B1: ( 1, 2, 26)
5784 19:26:46.060811 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5785 19:26:46.063609 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5786 19:26:46.063706
5787 19:26:46.070149 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5788 19:26:46.073350 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5789 19:26:46.076827 [Gating] SW calibration Done
5790 19:26:46.076925 ==
5791 19:26:46.080154 Dram Type= 6, Freq= 0, CH_1, rank 1
5792 19:26:46.083467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5793 19:26:46.083540 ==
5794 19:26:46.083618 RX Vref Scan: 0
5795 19:26:46.083697
5796 19:26:46.086763 RX Vref 0 -> 0, step: 1
5797 19:26:46.086842
5798 19:26:46.090158 RX Delay -80 -> 252, step: 8
5799 19:26:46.093816 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5800 19:26:46.096779 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5801 19:26:46.103629 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5802 19:26:46.106647 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5803 19:26:46.109895 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5804 19:26:46.113226 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5805 19:26:46.116658 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5806 19:26:46.119850 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5807 19:26:46.123712 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5808 19:26:46.130011 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5809 19:26:46.133163 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5810 19:26:46.136443 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5811 19:26:46.140290 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5812 19:26:46.143430 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5813 19:26:46.150007 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5814 19:26:46.153431 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5815 19:26:46.153507 ==
5816 19:26:46.156848 Dram Type= 6, Freq= 0, CH_1, rank 1
5817 19:26:46.160246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5818 19:26:46.160326 ==
5819 19:26:46.160405 DQS Delay:
5820 19:26:46.163558 DQS0 = 0, DQS1 = 0
5821 19:26:46.163655 DQM Delay:
5822 19:26:46.166893 DQM0 = 102, DQM1 = 98
5823 19:26:46.166993 DQ Delay:
5824 19:26:46.170134 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =99
5825 19:26:46.173477 DQ4 =95, DQ5 =115, DQ6 =115, DQ7 =99
5826 19:26:46.176716 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5827 19:26:46.179990 DQ12 =103, DQ13 =107, DQ14 =99, DQ15 =107
5828 19:26:46.180066
5829 19:26:46.180145
5830 19:26:46.180226 ==
5831 19:26:46.183385 Dram Type= 6, Freq= 0, CH_1, rank 1
5832 19:26:46.189549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5833 19:26:46.189658 ==
5834 19:26:46.189738
5835 19:26:46.189840
5836 19:26:46.189934 TX Vref Scan disable
5837 19:26:46.193435 == TX Byte 0 ==
5838 19:26:46.196851 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5839 19:26:46.203779 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5840 19:26:46.203865 == TX Byte 1 ==
5841 19:26:46.206455 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5842 19:26:46.212998 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5843 19:26:46.213101 ==
5844 19:26:46.216699 Dram Type= 6, Freq= 0, CH_1, rank 1
5845 19:26:46.219642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5846 19:26:46.219727 ==
5847 19:26:46.219809
5848 19:26:46.219885
5849 19:26:46.223339 TX Vref Scan disable
5850 19:26:46.223446 == TX Byte 0 ==
5851 19:26:46.229886 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5852 19:26:46.233084 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5853 19:26:46.233194 == TX Byte 1 ==
5854 19:26:46.240107 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5855 19:26:46.243108 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5856 19:26:46.243216
5857 19:26:46.243299 [DATLAT]
5858 19:26:46.246488 Freq=933, CH1 RK1
5859 19:26:46.246582
5860 19:26:46.246669 DATLAT Default: 0xb
5861 19:26:46.249740 0, 0xFFFF, sum = 0
5862 19:26:46.249837 1, 0xFFFF, sum = 0
5863 19:26:46.253563 2, 0xFFFF, sum = 0
5864 19:26:46.253661 3, 0xFFFF, sum = 0
5865 19:26:46.256791 4, 0xFFFF, sum = 0
5866 19:26:46.256866 5, 0xFFFF, sum = 0
5867 19:26:46.259562 6, 0xFFFF, sum = 0
5868 19:26:46.262939 7, 0xFFFF, sum = 0
5869 19:26:46.263036 8, 0xFFFF, sum = 0
5870 19:26:46.266307 9, 0xFFFF, sum = 0
5871 19:26:46.266394 10, 0x0, sum = 1
5872 19:26:46.266477 11, 0x0, sum = 2
5873 19:26:46.269645 12, 0x0, sum = 3
5874 19:26:46.269743 13, 0x0, sum = 4
5875 19:26:46.272866 best_step = 11
5876 19:26:46.272950
5877 19:26:46.273012 ==
5878 19:26:46.276187 Dram Type= 6, Freq= 0, CH_1, rank 1
5879 19:26:46.279500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5880 19:26:46.279579 ==
5881 19:26:46.282762 RX Vref Scan: 0
5882 19:26:46.282840
5883 19:26:46.282902 RX Vref 0 -> 0, step: 1
5884 19:26:46.286185
5885 19:26:46.286282 RX Delay -45 -> 252, step: 4
5886 19:26:46.293575 iDelay=203, Bit 0, Center 110 (27 ~ 194) 168
5887 19:26:46.296971 iDelay=203, Bit 1, Center 98 (15 ~ 182) 168
5888 19:26:46.300452 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5889 19:26:46.303844 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5890 19:26:46.307148 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5891 19:26:46.313802 iDelay=203, Bit 5, Center 116 (31 ~ 202) 172
5892 19:26:46.316556 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5893 19:26:46.319961 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5894 19:26:46.323308 iDelay=203, Bit 8, Center 92 (11 ~ 174) 164
5895 19:26:46.326555 iDelay=203, Bit 9, Center 88 (3 ~ 174) 172
5896 19:26:46.333528 iDelay=203, Bit 10, Center 100 (15 ~ 186) 172
5897 19:26:46.336525 iDelay=203, Bit 11, Center 94 (11 ~ 178) 168
5898 19:26:46.340248 iDelay=203, Bit 12, Center 110 (23 ~ 198) 176
5899 19:26:46.343728 iDelay=203, Bit 13, Center 108 (27 ~ 190) 164
5900 19:26:46.346792 iDelay=203, Bit 14, Center 104 (23 ~ 186) 164
5901 19:26:46.353449 iDelay=203, Bit 15, Center 110 (27 ~ 194) 168
5902 19:26:46.353565 ==
5903 19:26:46.356676 Dram Type= 6, Freq= 0, CH_1, rank 1
5904 19:26:46.359747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5905 19:26:46.359823 ==
5906 19:26:46.359912 DQS Delay:
5907 19:26:46.363362 DQS0 = 0, DQS1 = 0
5908 19:26:46.363498 DQM Delay:
5909 19:26:46.366558 DQM0 = 104, DQM1 = 100
5910 19:26:46.366637 DQ Delay:
5911 19:26:46.369894 DQ0 =110, DQ1 =98, DQ2 =94, DQ3 =100
5912 19:26:46.373172 DQ4 =100, DQ5 =116, DQ6 =114, DQ7 =104
5913 19:26:46.376566 DQ8 =92, DQ9 =88, DQ10 =100, DQ11 =94
5914 19:26:46.379870 DQ12 =110, DQ13 =108, DQ14 =104, DQ15 =110
5915 19:26:46.380022
5916 19:26:46.380105
5917 19:26:46.389809 [DQSOSCAuto] RK1, (LSB)MR18= 0x3003, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 406 ps
5918 19:26:46.393168 CH1 RK1: MR19=505, MR18=3003
5919 19:26:46.396475 CH1_RK1: MR19=0x505, MR18=0x3003, DQSOSC=406, MR23=63, INC=65, DEC=43
5920 19:26:46.399905 [RxdqsGatingPostProcess] freq 933
5921 19:26:46.406091 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5922 19:26:46.409526 best DQS0 dly(2T, 0.5T) = (0, 10)
5923 19:26:46.412847 best DQS1 dly(2T, 0.5T) = (0, 10)
5924 19:26:46.416649 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5925 19:26:46.419443 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5926 19:26:46.422827 best DQS0 dly(2T, 0.5T) = (0, 10)
5927 19:26:46.426270 best DQS1 dly(2T, 0.5T) = (0, 10)
5928 19:26:46.429541 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5929 19:26:46.433005 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5930 19:26:46.436229 Pre-setting of DQS Precalculation
5931 19:26:46.439351 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5932 19:26:46.446496 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5933 19:26:46.452646 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5934 19:26:46.452768
5935 19:26:46.452863
5936 19:26:46.456279 [Calibration Summary] 1866 Mbps
5937 19:26:46.459335 CH 0, Rank 0
5938 19:26:46.459440 SW Impedance : PASS
5939 19:26:46.462734 DUTY Scan : NO K
5940 19:26:46.465982 ZQ Calibration : PASS
5941 19:26:46.466058 Jitter Meter : NO K
5942 19:26:46.469287 CBT Training : PASS
5943 19:26:46.472397 Write leveling : PASS
5944 19:26:46.472503 RX DQS gating : PASS
5945 19:26:46.476193 RX DQ/DQS(RDDQC) : PASS
5946 19:26:46.479252 TX DQ/DQS : PASS
5947 19:26:46.479330 RX DATLAT : PASS
5948 19:26:46.482430 RX DQ/DQS(Engine): PASS
5949 19:26:46.486163 TX OE : NO K
5950 19:26:46.486243 All Pass.
5951 19:26:46.486315
5952 19:26:46.486385 CH 0, Rank 1
5953 19:26:46.488891 SW Impedance : PASS
5954 19:26:46.492235 DUTY Scan : NO K
5955 19:26:46.492312 ZQ Calibration : PASS
5956 19:26:46.495721 Jitter Meter : NO K
5957 19:26:46.495818 CBT Training : PASS
5958 19:26:46.499185 Write leveling : PASS
5959 19:26:46.502536 RX DQS gating : PASS
5960 19:26:46.502616 RX DQ/DQS(RDDQC) : PASS
5961 19:26:46.505717 TX DQ/DQS : PASS
5962 19:26:46.509159 RX DATLAT : PASS
5963 19:26:46.509244 RX DQ/DQS(Engine): PASS
5964 19:26:46.512738 TX OE : NO K
5965 19:26:46.512823 All Pass.
5966 19:26:46.512895
5967 19:26:46.516138 CH 1, Rank 0
5968 19:26:46.516223 SW Impedance : PASS
5969 19:26:46.518982 DUTY Scan : NO K
5970 19:26:46.522268 ZQ Calibration : PASS
5971 19:26:46.522353 Jitter Meter : NO K
5972 19:26:46.526138 CBT Training : PASS
5973 19:26:46.528833 Write leveling : PASS
5974 19:26:46.528907 RX DQS gating : PASS
5975 19:26:46.532317 RX DQ/DQS(RDDQC) : PASS
5976 19:26:46.535692 TX DQ/DQS : PASS
5977 19:26:46.535771 RX DATLAT : PASS
5978 19:26:46.538974 RX DQ/DQS(Engine): PASS
5979 19:26:46.539044 TX OE : NO K
5980 19:26:46.542500 All Pass.
5981 19:26:46.542586
5982 19:26:46.542652 CH 1, Rank 1
5983 19:26:46.545994 SW Impedance : PASS
5984 19:26:46.546077 DUTY Scan : NO K
5985 19:26:46.549381 ZQ Calibration : PASS
5986 19:26:46.552567 Jitter Meter : NO K
5987 19:26:46.552651 CBT Training : PASS
5988 19:26:46.555731 Write leveling : PASS
5989 19:26:46.558859 RX DQS gating : PASS
5990 19:26:46.558941 RX DQ/DQS(RDDQC) : PASS
5991 19:26:46.562359 TX DQ/DQS : PASS
5992 19:26:46.565541 RX DATLAT : PASS
5993 19:26:46.565626 RX DQ/DQS(Engine): PASS
5994 19:26:46.568701 TX OE : NO K
5995 19:26:46.568810 All Pass.
5996 19:26:46.568910
5997 19:26:46.572296 DramC Write-DBI off
5998 19:26:46.575983 PER_BANK_REFRESH: Hybrid Mode
5999 19:26:46.576081 TX_TRACKING: ON
6000 19:26:46.585735 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6001 19:26:46.589247 [FAST_K] Save calibration result to emmc
6002 19:26:46.592280 dramc_set_vcore_voltage set vcore to 650000
6003 19:26:46.595446 Read voltage for 400, 6
6004 19:26:46.595531 Vio18 = 0
6005 19:26:46.595618 Vcore = 650000
6006 19:26:46.598667 Vdram = 0
6007 19:26:46.598744 Vddq = 0
6008 19:26:46.598836 Vmddr = 0
6009 19:26:46.605688 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6010 19:26:46.609007 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6011 19:26:46.612465 MEM_TYPE=3, freq_sel=20
6012 19:26:46.615797 sv_algorithm_assistance_LP4_800
6013 19:26:46.619206 ============ PULL DRAM RESETB DOWN ============
6014 19:26:46.621881 ========== PULL DRAM RESETB DOWN end =========
6015 19:26:46.628756 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6016 19:26:46.631866 ===================================
6017 19:26:46.631952 LPDDR4 DRAM CONFIGURATION
6018 19:26:46.635237 ===================================
6019 19:26:46.638643 EX_ROW_EN[0] = 0x0
6020 19:26:46.642032 EX_ROW_EN[1] = 0x0
6021 19:26:46.642111 LP4Y_EN = 0x0
6022 19:26:46.645423 WORK_FSP = 0x0
6023 19:26:46.645505 WL = 0x2
6024 19:26:46.648853 RL = 0x2
6025 19:26:46.648936 BL = 0x2
6026 19:26:46.652253 RPST = 0x0
6027 19:26:46.652336 RD_PRE = 0x0
6028 19:26:46.654969 WR_PRE = 0x1
6029 19:26:46.655045 WR_PST = 0x0
6030 19:26:46.658866 DBI_WR = 0x0
6031 19:26:46.658951 DBI_RD = 0x0
6032 19:26:46.662242 OTF = 0x1
6033 19:26:46.665000 ===================================
6034 19:26:46.668260 ===================================
6035 19:26:46.668343 ANA top config
6036 19:26:46.671567 ===================================
6037 19:26:46.674900 DLL_ASYNC_EN = 0
6038 19:26:46.678241 ALL_SLAVE_EN = 1
6039 19:26:46.681657 NEW_RANK_MODE = 1
6040 19:26:46.681740 DLL_IDLE_MODE = 1
6041 19:26:46.684799 LP45_APHY_COMB_EN = 1
6042 19:26:46.688481 TX_ODT_DIS = 1
6043 19:26:46.691575 NEW_8X_MODE = 1
6044 19:26:46.694699 ===================================
6045 19:26:46.698095 ===================================
6046 19:26:46.701502 data_rate = 800
6047 19:26:46.701602 CKR = 1
6048 19:26:46.704719 DQ_P2S_RATIO = 4
6049 19:26:46.707913 ===================================
6050 19:26:46.711390 CA_P2S_RATIO = 4
6051 19:26:46.714757 DQ_CA_OPEN = 0
6052 19:26:46.718116 DQ_SEMI_OPEN = 1
6053 19:26:46.721231 CA_SEMI_OPEN = 1
6054 19:26:46.721314 CA_FULL_RATE = 0
6055 19:26:46.724861 DQ_CKDIV4_EN = 0
6056 19:26:46.728244 CA_CKDIV4_EN = 1
6057 19:26:46.731591 CA_PREDIV_EN = 0
6058 19:26:46.734758 PH8_DLY = 0
6059 19:26:46.738090 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6060 19:26:46.738196 DQ_AAMCK_DIV = 0
6061 19:26:46.741421 CA_AAMCK_DIV = 0
6062 19:26:46.744891 CA_ADMCK_DIV = 4
6063 19:26:46.747675 DQ_TRACK_CA_EN = 0
6064 19:26:46.751114 CA_PICK = 800
6065 19:26:46.754531 CA_MCKIO = 400
6066 19:26:46.758128 MCKIO_SEMI = 400
6067 19:26:46.760818 PLL_FREQ = 3016
6068 19:26:46.760894 DQ_UI_PI_RATIO = 32
6069 19:26:46.764207 CA_UI_PI_RATIO = 32
6070 19:26:46.767563 ===================================
6071 19:26:46.770795 ===================================
6072 19:26:46.774045 memory_type:LPDDR4
6073 19:26:46.777327 GP_NUM : 10
6074 19:26:46.777428 SRAM_EN : 1
6075 19:26:46.780649 MD32_EN : 0
6076 19:26:46.784549 ===================================
6077 19:26:46.787231 [ANA_INIT] >>>>>>>>>>>>>>
6078 19:26:46.787332 <<<<<< [CONFIGURE PHASE]: ANA_TX
6079 19:26:46.790542 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6080 19:26:46.794439 ===================================
6081 19:26:46.797688 data_rate = 800,PCW = 0X7400
6082 19:26:46.800757 ===================================
6083 19:26:46.804505 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6084 19:26:46.811224 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6085 19:26:46.820646 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6086 19:26:46.827380 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6087 19:26:46.830625 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6088 19:26:46.834297 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6089 19:26:46.834409 [ANA_INIT] flow start
6090 19:26:46.837672 [ANA_INIT] PLL >>>>>>>>
6091 19:26:46.840785 [ANA_INIT] PLL <<<<<<<<
6092 19:26:46.844260 [ANA_INIT] MIDPI >>>>>>>>
6093 19:26:46.844362 [ANA_INIT] MIDPI <<<<<<<<
6094 19:26:46.847197 [ANA_INIT] DLL >>>>>>>>
6095 19:26:46.847271 [ANA_INIT] flow end
6096 19:26:46.854227 ============ LP4 DIFF to SE enter ============
6097 19:26:46.857348 ============ LP4 DIFF to SE exit ============
6098 19:26:46.860859 [ANA_INIT] <<<<<<<<<<<<<
6099 19:26:46.864233 [Flow] Enable top DCM control >>>>>
6100 19:26:46.867604 [Flow] Enable top DCM control <<<<<
6101 19:26:46.870936 Enable DLL master slave shuffle
6102 19:26:46.873640 ==============================================================
6103 19:26:46.876997 Gating Mode config
6104 19:26:46.880252 ==============================================================
6105 19:26:46.883705 Config description:
6106 19:26:46.893707 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6107 19:26:46.900611 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6108 19:26:46.903846 SELPH_MODE 0: By rank 1: By Phase
6109 19:26:46.910152 ==============================================================
6110 19:26:46.913246 GAT_TRACK_EN = 0
6111 19:26:46.917149 RX_GATING_MODE = 2
6112 19:26:46.919909 RX_GATING_TRACK_MODE = 2
6113 19:26:46.923584 SELPH_MODE = 1
6114 19:26:46.926904 PICG_EARLY_EN = 1
6115 19:26:46.930285 VALID_LAT_VALUE = 1
6116 19:26:46.933687 ==============================================================
6117 19:26:46.937223 Enter into Gating configuration >>>>
6118 19:26:46.939837 Exit from Gating configuration <<<<
6119 19:26:46.943602 Enter into DVFS_PRE_config >>>>>
6120 19:26:46.953468 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6121 19:26:46.956622 Exit from DVFS_PRE_config <<<<<
6122 19:26:46.959770 Enter into PICG configuration >>>>
6123 19:26:46.963729 Exit from PICG configuration <<<<
6124 19:26:46.966584 [RX_INPUT] configuration >>>>>
6125 19:26:46.969874 [RX_INPUT] configuration <<<<<
6126 19:26:46.976858 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6127 19:26:46.980142 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6128 19:26:46.986743 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6129 19:26:46.993427 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6130 19:26:46.999958 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6131 19:26:47.006853 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6132 19:26:47.009587 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6133 19:26:47.012925 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6134 19:26:47.016268 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6135 19:26:47.023134 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6136 19:26:47.026335 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6137 19:26:47.029868 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6138 19:26:47.033258 ===================================
6139 19:26:47.036700 LPDDR4 DRAM CONFIGURATION
6140 19:26:47.039491 ===================================
6141 19:26:47.039576 EX_ROW_EN[0] = 0x0
6142 19:26:47.042860 EX_ROW_EN[1] = 0x0
6143 19:26:47.042943 LP4Y_EN = 0x0
6144 19:26:47.046365 WORK_FSP = 0x0
6145 19:26:47.049527 WL = 0x2
6146 19:26:47.049625 RL = 0x2
6147 19:26:47.053329 BL = 0x2
6148 19:26:47.053433 RPST = 0x0
6149 19:26:47.056287 RD_PRE = 0x0
6150 19:26:47.056388 WR_PRE = 0x1
6151 19:26:47.059358 WR_PST = 0x0
6152 19:26:47.059433 DBI_WR = 0x0
6153 19:26:47.062737 DBI_RD = 0x0
6154 19:26:47.062821 OTF = 0x1
6155 19:26:47.066270 ===================================
6156 19:26:47.069699 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6157 19:26:47.076517 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6158 19:26:47.079658 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6159 19:26:47.083284 ===================================
6160 19:26:47.086406 LPDDR4 DRAM CONFIGURATION
6161 19:26:47.089824 ===================================
6162 19:26:47.089899 EX_ROW_EN[0] = 0x10
6163 19:26:47.093291 EX_ROW_EN[1] = 0x0
6164 19:26:47.093393 LP4Y_EN = 0x0
6165 19:26:47.096014 WORK_FSP = 0x0
6166 19:26:47.096110 WL = 0x2
6167 19:26:47.099479 RL = 0x2
6168 19:26:47.099555 BL = 0x2
6169 19:26:47.102895 RPST = 0x0
6170 19:26:47.102969 RD_PRE = 0x0
6171 19:26:47.105957 WR_PRE = 0x1
6172 19:26:47.109748 WR_PST = 0x0
6173 19:26:47.109853 DBI_WR = 0x0
6174 19:26:47.113194 DBI_RD = 0x0
6175 19:26:47.113302 OTF = 0x1
6176 19:26:47.116604 ===================================
6177 19:26:47.122747 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6178 19:26:47.126661 nWR fixed to 30
6179 19:26:47.129866 [ModeRegInit_LP4] CH0 RK0
6180 19:26:47.129961 [ModeRegInit_LP4] CH0 RK1
6181 19:26:47.133205 [ModeRegInit_LP4] CH1 RK0
6182 19:26:47.136331 [ModeRegInit_LP4] CH1 RK1
6183 19:26:47.136409 match AC timing 19
6184 19:26:47.142820 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6185 19:26:47.146185 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6186 19:26:47.149549 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6187 19:26:47.156330 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6188 19:26:47.159593 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6189 19:26:47.159666 ==
6190 19:26:47.163136 Dram Type= 6, Freq= 0, CH_0, rank 0
6191 19:26:47.166156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6192 19:26:47.166253 ==
6193 19:26:47.172777 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6194 19:26:47.179506 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6195 19:26:47.182318 [CA 0] Center 36 (8~64) winsize 57
6196 19:26:47.185641 [CA 1] Center 36 (8~64) winsize 57
6197 19:26:47.189106 [CA 2] Center 36 (8~64) winsize 57
6198 19:26:47.192496 [CA 3] Center 36 (8~64) winsize 57
6199 19:26:47.195843 [CA 4] Center 36 (8~64) winsize 57
6200 19:26:47.195925 [CA 5] Center 36 (8~64) winsize 57
6201 19:26:47.195988
6202 19:26:47.202312 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6203 19:26:47.202401
6204 19:26:47.205989 [CATrainingPosCal] consider 1 rank data
6205 19:26:47.208914 u2DelayCellTimex100 = 270/100 ps
6206 19:26:47.212471 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6207 19:26:47.215443 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6208 19:26:47.218839 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6209 19:26:47.222079 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6210 19:26:47.225486 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6211 19:26:47.229139 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6212 19:26:47.229242
6213 19:26:47.232499 CA PerBit enable=1, Macro0, CA PI delay=36
6214 19:26:47.232575
6215 19:26:47.235693 [CBTSetCACLKResult] CA Dly = 36
6216 19:26:47.238757 CS Dly: 1 (0~32)
6217 19:26:47.238863 ==
6218 19:26:47.242107 Dram Type= 6, Freq= 0, CH_0, rank 1
6219 19:26:47.245901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6220 19:26:47.246000 ==
6221 19:26:47.252338 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6222 19:26:47.258404 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6223 19:26:47.261852 [CA 0] Center 36 (8~64) winsize 57
6224 19:26:47.265197 [CA 1] Center 36 (8~64) winsize 57
6225 19:26:47.265267 [CA 2] Center 36 (8~64) winsize 57
6226 19:26:47.268521 [CA 3] Center 36 (8~64) winsize 57
6227 19:26:47.272244 [CA 4] Center 36 (8~64) winsize 57
6228 19:26:47.275315 [CA 5] Center 36 (8~64) winsize 57
6229 19:26:47.275385
6230 19:26:47.278529 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6231 19:26:47.278603
6232 19:26:47.281993 [CATrainingPosCal] consider 2 rank data
6233 19:26:47.285422 u2DelayCellTimex100 = 270/100 ps
6234 19:26:47.288823 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6235 19:26:47.295456 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6236 19:26:47.298820 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6237 19:26:47.302253 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6238 19:26:47.305559 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6239 19:26:47.308755 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6240 19:26:47.308828
6241 19:26:47.312147 CA PerBit enable=1, Macro0, CA PI delay=36
6242 19:26:47.312256
6243 19:26:47.315268 [CBTSetCACLKResult] CA Dly = 36
6244 19:26:47.315347 CS Dly: 1 (0~32)
6245 19:26:47.318547
6246 19:26:47.321980 ----->DramcWriteLeveling(PI) begin...
6247 19:26:47.322088 ==
6248 19:26:47.325407 Dram Type= 6, Freq= 0, CH_0, rank 0
6249 19:26:47.328561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6250 19:26:47.328635 ==
6251 19:26:47.331638 Write leveling (Byte 0): 40 => 8
6252 19:26:47.335126 Write leveling (Byte 1): 40 => 8
6253 19:26:47.338179 DramcWriteLeveling(PI) end<-----
6254 19:26:47.338279
6255 19:26:47.338357 ==
6256 19:26:47.341551 Dram Type= 6, Freq= 0, CH_0, rank 0
6257 19:26:47.345115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6258 19:26:47.345186 ==
6259 19:26:47.348127 [Gating] SW mode calibration
6260 19:26:47.354696 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6261 19:26:47.361211 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6262 19:26:47.364919 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6263 19:26:47.368470 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6264 19:26:47.375022 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6265 19:26:47.378419 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6266 19:26:47.381687 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6267 19:26:47.388167 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6268 19:26:47.391585 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6269 19:26:47.394903 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6270 19:26:47.401200 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6271 19:26:47.401280 Total UI for P1: 0, mck2ui 16
6272 19:26:47.404712 best dqsien dly found for B0: ( 0, 14, 24)
6273 19:26:47.407920 Total UI for P1: 0, mck2ui 16
6274 19:26:47.411325 best dqsien dly found for B1: ( 0, 14, 24)
6275 19:26:47.414734 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6276 19:26:47.421177 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6277 19:26:47.421260
6278 19:26:47.424483 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6279 19:26:47.427883 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6280 19:26:47.431306 [Gating] SW calibration Done
6281 19:26:47.431403 ==
6282 19:26:47.434582 Dram Type= 6, Freq= 0, CH_0, rank 0
6283 19:26:47.437980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6284 19:26:47.438076 ==
6285 19:26:47.441253 RX Vref Scan: 0
6286 19:26:47.441335
6287 19:26:47.441399 RX Vref 0 -> 0, step: 1
6288 19:26:47.441497
6289 19:26:47.444487 RX Delay -410 -> 252, step: 16
6290 19:26:47.447686 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6291 19:26:47.454627 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6292 19:26:47.458098 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6293 19:26:47.461009 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6294 19:26:47.464369 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6295 19:26:47.470850 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6296 19:26:47.474578 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6297 19:26:47.477446 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6298 19:26:47.480680 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6299 19:26:47.487598 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6300 19:26:47.490792 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6301 19:26:47.494446 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6302 19:26:47.500747 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6303 19:26:47.504198 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6304 19:26:47.507497 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6305 19:26:47.510727 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6306 19:26:47.510810 ==
6307 19:26:47.514187 Dram Type= 6, Freq= 0, CH_0, rank 0
6308 19:26:47.520796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6309 19:26:47.520884 ==
6310 19:26:47.520952 DQS Delay:
6311 19:26:47.524076 DQS0 = 27, DQS1 = 35
6312 19:26:47.524158 DQM Delay:
6313 19:26:47.524235 DQM0 = 10, DQM1 = 12
6314 19:26:47.527439 DQ Delay:
6315 19:26:47.530872 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =8
6316 19:26:47.534172 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6317 19:26:47.534249 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6318 19:26:47.537627 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6319 19:26:47.537710
6320 19:26:47.541167
6321 19:26:47.541258 ==
6322 19:26:47.543937 Dram Type= 6, Freq= 0, CH_0, rank 0
6323 19:26:47.547470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6324 19:26:47.547582 ==
6325 19:26:47.547676
6326 19:26:47.547765
6327 19:26:47.550726 TX Vref Scan disable
6328 19:26:47.550799 == TX Byte 0 ==
6329 19:26:47.554054 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6330 19:26:47.560798 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6331 19:26:47.560880 == TX Byte 1 ==
6332 19:26:47.564338 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6333 19:26:47.570533 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6334 19:26:47.570620 ==
6335 19:26:47.573798 Dram Type= 6, Freq= 0, CH_0, rank 0
6336 19:26:47.577208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6337 19:26:47.577285 ==
6338 19:26:47.577352
6339 19:26:47.577412
6340 19:26:47.580545 TX Vref Scan disable
6341 19:26:47.580623 == TX Byte 0 ==
6342 19:26:47.583924 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6343 19:26:47.590694 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6344 19:26:47.590785 == TX Byte 1 ==
6345 19:26:47.594178 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6346 19:26:47.600808 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6347 19:26:47.600907
6348 19:26:47.600974 [DATLAT]
6349 19:26:47.601058 Freq=400, CH0 RK0
6350 19:26:47.604051
6351 19:26:47.604140 DATLAT Default: 0xf
6352 19:26:47.607292 0, 0xFFFF, sum = 0
6353 19:26:47.607385 1, 0xFFFF, sum = 0
6354 19:26:47.610477 2, 0xFFFF, sum = 0
6355 19:26:47.610559 3, 0xFFFF, sum = 0
6356 19:26:47.614046 4, 0xFFFF, sum = 0
6357 19:26:47.614154 5, 0xFFFF, sum = 0
6358 19:26:47.617452 6, 0xFFFF, sum = 0
6359 19:26:47.617559 7, 0xFFFF, sum = 0
6360 19:26:47.620394 8, 0xFFFF, sum = 0
6361 19:26:47.620498 9, 0xFFFF, sum = 0
6362 19:26:47.623829 10, 0xFFFF, sum = 0
6363 19:26:47.623934 11, 0xFFFF, sum = 0
6364 19:26:47.627073 12, 0xFFFF, sum = 0
6365 19:26:47.627178 13, 0x0, sum = 1
6366 19:26:47.630334 14, 0x0, sum = 2
6367 19:26:47.630426 15, 0x0, sum = 3
6368 19:26:47.633544 16, 0x0, sum = 4
6369 19:26:47.633623 best_step = 14
6370 19:26:47.633688
6371 19:26:47.633747 ==
6372 19:26:47.637306 Dram Type= 6, Freq= 0, CH_0, rank 0
6373 19:26:47.643459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6374 19:26:47.643551 ==
6375 19:26:47.643619 RX Vref Scan: 1
6376 19:26:47.643681
6377 19:26:47.646805 RX Vref 0 -> 0, step: 1
6378 19:26:47.646888
6379 19:26:47.650157 RX Delay -311 -> 252, step: 8
6380 19:26:47.650265
6381 19:26:47.653325 Set Vref, RX VrefLevel [Byte0]: 54
6382 19:26:47.657238 [Byte1]: 46
6383 19:26:47.657360
6384 19:26:47.660474 Final RX Vref Byte 0 = 54 to rank0
6385 19:26:47.663792 Final RX Vref Byte 1 = 46 to rank0
6386 19:26:47.666517 Final RX Vref Byte 0 = 54 to rank1
6387 19:26:47.669914 Final RX Vref Byte 1 = 46 to rank1==
6388 19:26:47.673326 Dram Type= 6, Freq= 0, CH_0, rank 0
6389 19:26:47.676731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6390 19:26:47.680186 ==
6391 19:26:47.680320 DQS Delay:
6392 19:26:47.680418 DQS0 = 28, DQS1 = 36
6393 19:26:47.683126 DQM Delay:
6394 19:26:47.683212 DQM0 = 11, DQM1 = 12
6395 19:26:47.686495 DQ Delay:
6396 19:26:47.686578 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =8
6397 19:26:47.689976 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6398 19:26:47.693324 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6399 19:26:47.696667 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6400 19:26:47.696751
6401 19:26:47.696817
6402 19:26:47.706435 [DQSOSCAuto] RK0, (LSB)MR18= 0xd6c2, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 383 ps
6403 19:26:47.709830 CH0 RK0: MR19=C0C, MR18=D6C2
6404 19:26:47.716523 CH0_RK0: MR19=0xC0C, MR18=0xD6C2, DQSOSC=383, MR23=63, INC=402, DEC=268
6405 19:26:47.716607 ==
6406 19:26:47.719955 Dram Type= 6, Freq= 0, CH_0, rank 1
6407 19:26:47.723222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6408 19:26:47.723306 ==
6409 19:26:47.726283 [Gating] SW mode calibration
6410 19:26:47.733106 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6411 19:26:47.736275 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6412 19:26:47.742977 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6413 19:26:47.746247 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6414 19:26:47.749429 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6415 19:26:47.756108 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6416 19:26:47.759480 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6417 19:26:47.763250 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6418 19:26:47.769389 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6419 19:26:47.772941 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6420 19:26:47.776324 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6421 19:26:47.779264 Total UI for P1: 0, mck2ui 16
6422 19:26:47.782969 best dqsien dly found for B0: ( 0, 14, 24)
6423 19:26:47.786061 Total UI for P1: 0, mck2ui 16
6424 19:26:47.789243 best dqsien dly found for B1: ( 0, 14, 24)
6425 19:26:47.792566 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6426 19:26:47.795820 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6427 19:26:47.799125
6428 19:26:47.802433 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6429 19:26:47.805734 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6430 19:26:47.809542 [Gating] SW calibration Done
6431 19:26:47.809623 ==
6432 19:26:47.812297 Dram Type= 6, Freq= 0, CH_0, rank 1
6433 19:26:47.815715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6434 19:26:47.815798 ==
6435 19:26:47.815892 RX Vref Scan: 0
6436 19:26:47.815953
6437 19:26:47.819187 RX Vref 0 -> 0, step: 1
6438 19:26:47.819268
6439 19:26:47.822588 RX Delay -410 -> 252, step: 16
6440 19:26:47.825996 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6441 19:26:47.832482 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6442 19:26:47.835958 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6443 19:26:47.839361 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6444 19:26:47.842659 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6445 19:26:47.849225 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6446 19:26:47.852649 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6447 19:26:47.855939 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6448 19:26:47.859268 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6449 19:26:47.865652 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6450 19:26:47.868844 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6451 19:26:47.872175 iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448
6452 19:26:47.875650 iDelay=230, Bit 12, Center -11 (-234 ~ 213) 448
6453 19:26:47.882224 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6454 19:26:47.885528 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6455 19:26:47.889332 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6456 19:26:47.889428 ==
6457 19:26:47.892156 Dram Type= 6, Freq= 0, CH_0, rank 1
6458 19:26:47.895563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6459 19:26:47.898903 ==
6460 19:26:47.898979 DQS Delay:
6461 19:26:47.899041 DQS0 = 19, DQS1 = 35
6462 19:26:47.902000 DQM Delay:
6463 19:26:47.902074 DQM0 = 5, DQM1 = 13
6464 19:26:47.905630 DQ Delay:
6465 19:26:47.905710 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6466 19:26:47.908626 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6467 19:26:47.912246 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6468 19:26:47.915533 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =16
6469 19:26:47.915615
6470 19:26:47.915682
6471 19:26:47.915749 ==
6472 19:26:47.918989 Dram Type= 6, Freq= 0, CH_0, rank 1
6473 19:26:47.925376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6474 19:26:47.925461 ==
6475 19:26:47.925527
6476 19:26:47.925628
6477 19:26:47.925685 TX Vref Scan disable
6478 19:26:47.929268 == TX Byte 0 ==
6479 19:26:47.932075 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6480 19:26:47.935292 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6481 19:26:47.939220 == TX Byte 1 ==
6482 19:26:47.942523 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6483 19:26:47.945359 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6484 19:26:47.945457 ==
6485 19:26:47.949172 Dram Type= 6, Freq= 0, CH_0, rank 1
6486 19:26:47.955675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6487 19:26:47.955776 ==
6488 19:26:47.955890
6489 19:26:47.955965
6490 19:26:47.956055 TX Vref Scan disable
6491 19:26:47.958439 == TX Byte 0 ==
6492 19:26:47.961870 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6493 19:26:47.965331 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6494 19:26:47.968645 == TX Byte 1 ==
6495 19:26:47.971794 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6496 19:26:47.975090 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6497 19:26:47.975173
6498 19:26:47.978463 [DATLAT]
6499 19:26:47.978543 Freq=400, CH0 RK1
6500 19:26:47.978607
6501 19:26:47.981739 DATLAT Default: 0xe
6502 19:26:47.981819 0, 0xFFFF, sum = 0
6503 19:26:47.984996 1, 0xFFFF, sum = 0
6504 19:26:47.985078 2, 0xFFFF, sum = 0
6505 19:26:47.988453 3, 0xFFFF, sum = 0
6506 19:26:47.988534 4, 0xFFFF, sum = 0
6507 19:26:47.991811 5, 0xFFFF, sum = 0
6508 19:26:47.991919 6, 0xFFFF, sum = 0
6509 19:26:47.995137 7, 0xFFFF, sum = 0
6510 19:26:47.995219 8, 0xFFFF, sum = 0
6511 19:26:47.998500 9, 0xFFFF, sum = 0
6512 19:26:48.001722 10, 0xFFFF, sum = 0
6513 19:26:48.001804 11, 0xFFFF, sum = 0
6514 19:26:48.005579 12, 0xFFFF, sum = 0
6515 19:26:48.005661 13, 0x0, sum = 1
6516 19:26:48.008462 14, 0x0, sum = 2
6517 19:26:48.008573 15, 0x0, sum = 3
6518 19:26:48.008670 16, 0x0, sum = 4
6519 19:26:48.011886 best_step = 14
6520 19:26:48.011967
6521 19:26:48.012060 ==
6522 19:26:48.015359 Dram Type= 6, Freq= 0, CH_0, rank 1
6523 19:26:48.018708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6524 19:26:48.018790 ==
6525 19:26:48.022152 RX Vref Scan: 0
6526 19:26:48.022232
6527 19:26:48.025436 RX Vref 0 -> 0, step: 1
6528 19:26:48.025517
6529 19:26:48.025580 RX Delay -311 -> 252, step: 8
6530 19:26:48.033756 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6531 19:26:48.036615 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6532 19:26:48.040465 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6533 19:26:48.043539 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6534 19:26:48.050133 iDelay=217, Bit 4, Center -12 (-239 ~ 216) 456
6535 19:26:48.053206 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6536 19:26:48.056663 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6537 19:26:48.059783 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6538 19:26:48.066735 iDelay=217, Bit 8, Center -32 (-247 ~ 184) 432
6539 19:26:48.070169 iDelay=217, Bit 9, Center -36 (-255 ~ 184) 440
6540 19:26:48.073385 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6541 19:26:48.076617 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6542 19:26:48.083190 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6543 19:26:48.086559 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6544 19:26:48.089955 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6545 19:26:48.096899 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6546 19:26:48.096980 ==
6547 19:26:48.099602 Dram Type= 6, Freq= 0, CH_0, rank 1
6548 19:26:48.103025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6549 19:26:48.103107 ==
6550 19:26:48.103171 DQS Delay:
6551 19:26:48.106347 DQS0 = 24, DQS1 = 36
6552 19:26:48.106428 DQM Delay:
6553 19:26:48.110069 DQM0 = 8, DQM1 = 13
6554 19:26:48.110150 DQ Delay:
6555 19:26:48.113234 DQ0 =8, DQ1 =8, DQ2 =4, DQ3 =8
6556 19:26:48.116576 DQ4 =12, DQ5 =0, DQ6 =12, DQ7 =16
6557 19:26:48.119981 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6558 19:26:48.123447 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6559 19:26:48.123528
6560 19:26:48.123591
6561 19:26:48.129586 [DQSOSCAuto] RK1, (LSB)MR18= 0xbf60, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 386 ps
6562 19:26:48.132962 CH0 RK1: MR19=C0C, MR18=BF60
6563 19:26:48.139819 CH0_RK1: MR19=0xC0C, MR18=0xBF60, DQSOSC=386, MR23=63, INC=396, DEC=264
6564 19:26:48.143271 [RxdqsGatingPostProcess] freq 400
6565 19:26:48.149405 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6566 19:26:48.149486 best DQS0 dly(2T, 0.5T) = (0, 10)
6567 19:26:48.152741 best DQS1 dly(2T, 0.5T) = (0, 10)
6568 19:26:48.156554 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6569 19:26:48.159667 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6570 19:26:48.163351 best DQS0 dly(2T, 0.5T) = (0, 10)
6571 19:26:48.166595 best DQS1 dly(2T, 0.5T) = (0, 10)
6572 19:26:48.169653 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6573 19:26:48.172762 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6574 19:26:48.176129 Pre-setting of DQS Precalculation
6575 19:26:48.179601 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6576 19:26:48.183020 ==
6577 19:26:48.186082 Dram Type= 6, Freq= 0, CH_1, rank 0
6578 19:26:48.189579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6579 19:26:48.189661 ==
6580 19:26:48.192767 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6581 19:26:48.199409 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6582 19:26:48.202782 [CA 0] Center 36 (8~64) winsize 57
6583 19:26:48.206270 [CA 1] Center 36 (8~64) winsize 57
6584 19:26:48.209456 [CA 2] Center 36 (8~64) winsize 57
6585 19:26:48.212653 [CA 3] Center 36 (8~64) winsize 57
6586 19:26:48.216578 [CA 4] Center 36 (8~64) winsize 57
6587 19:26:48.219731 [CA 5] Center 36 (8~64) winsize 57
6588 19:26:48.219869
6589 19:26:48.223171 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6590 19:26:48.223253
6591 19:26:48.226524 [CATrainingPosCal] consider 1 rank data
6592 19:26:48.229174 u2DelayCellTimex100 = 270/100 ps
6593 19:26:48.232654 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6594 19:26:48.236134 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6595 19:26:48.239679 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6596 19:26:48.242932 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6597 19:26:48.246284 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6598 19:26:48.252819 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6599 19:26:48.252901
6600 19:26:48.256262 CA PerBit enable=1, Macro0, CA PI delay=36
6601 19:26:48.256344
6602 19:26:48.259637 [CBTSetCACLKResult] CA Dly = 36
6603 19:26:48.259748 CS Dly: 1 (0~32)
6604 19:26:48.259812 ==
6605 19:26:48.262431 Dram Type= 6, Freq= 0, CH_1, rank 1
6606 19:26:48.265803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6607 19:26:48.268980 ==
6608 19:26:48.272741 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6609 19:26:48.279182 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6610 19:26:48.282607 [CA 0] Center 36 (8~64) winsize 57
6611 19:26:48.285959 [CA 1] Center 36 (8~64) winsize 57
6612 19:26:48.289381 [CA 2] Center 36 (8~64) winsize 57
6613 19:26:48.292904 [CA 3] Center 36 (8~64) winsize 57
6614 19:26:48.295641 [CA 4] Center 36 (8~64) winsize 57
6615 19:26:48.299128 [CA 5] Center 36 (8~64) winsize 57
6616 19:26:48.299212
6617 19:26:48.302502 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6618 19:26:48.302585
6619 19:26:48.305660 [CATrainingPosCal] consider 2 rank data
6620 19:26:48.309494 u2DelayCellTimex100 = 270/100 ps
6621 19:26:48.312529 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6622 19:26:48.316111 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6623 19:26:48.319156 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6624 19:26:48.322381 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6625 19:26:48.325894 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6626 19:26:48.329261 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6627 19:26:48.329343
6628 19:26:48.332537 CA PerBit enable=1, Macro0, CA PI delay=36
6629 19:26:48.335573
6630 19:26:48.335658 [CBTSetCACLKResult] CA Dly = 36
6631 19:26:48.338805 CS Dly: 1 (0~32)
6632 19:26:48.338891
6633 19:26:48.342226 ----->DramcWriteLeveling(PI) begin...
6634 19:26:48.342320 ==
6635 19:26:48.345542 Dram Type= 6, Freq= 0, CH_1, rank 0
6636 19:26:48.348891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6637 19:26:48.348975 ==
6638 19:26:48.352364 Write leveling (Byte 0): 40 => 8
6639 19:26:48.355894 Write leveling (Byte 1): 40 => 8
6640 19:26:48.359149 DramcWriteLeveling(PI) end<-----
6641 19:26:48.359235
6642 19:26:48.359321 ==
6643 19:26:48.362550 Dram Type= 6, Freq= 0, CH_1, rank 0
6644 19:26:48.365963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6645 19:26:48.366045 ==
6646 19:26:48.368601 [Gating] SW mode calibration
6647 19:26:48.375305 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6648 19:26:48.382474 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6649 19:26:48.385543 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6650 19:26:48.392097 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6651 19:26:48.395457 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6652 19:26:48.398842 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6653 19:26:48.405599 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6654 19:26:48.409022 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6655 19:26:48.411737 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6656 19:26:48.418512 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6657 19:26:48.421908 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6658 19:26:48.425449 Total UI for P1: 0, mck2ui 16
6659 19:26:48.428662 best dqsien dly found for B0: ( 0, 14, 24)
6660 19:26:48.431915 Total UI for P1: 0, mck2ui 16
6661 19:26:48.435244 best dqsien dly found for B1: ( 0, 14, 24)
6662 19:26:48.438497 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6663 19:26:48.441826 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6664 19:26:48.441911
6665 19:26:48.444996 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6666 19:26:48.448671 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6667 19:26:48.451831 [Gating] SW calibration Done
6668 19:26:48.451915 ==
6669 19:26:48.455178 Dram Type= 6, Freq= 0, CH_1, rank 0
6670 19:26:48.458157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6671 19:26:48.462160 ==
6672 19:26:48.462244 RX Vref Scan: 0
6673 19:26:48.462375
6674 19:26:48.465035 RX Vref 0 -> 0, step: 1
6675 19:26:48.465120
6676 19:26:48.468144 RX Delay -410 -> 252, step: 16
6677 19:26:48.471592 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6678 19:26:48.475038 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6679 19:26:48.478020 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6680 19:26:48.484757 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6681 19:26:48.488329 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6682 19:26:48.491398 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6683 19:26:48.494939 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6684 19:26:48.501296 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6685 19:26:48.504774 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6686 19:26:48.508119 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6687 19:26:48.511484 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6688 19:26:48.518391 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6689 19:26:48.521763 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6690 19:26:48.524480 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6691 19:26:48.527818 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6692 19:26:48.534548 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6693 19:26:48.534630 ==
6694 19:26:48.537741 Dram Type= 6, Freq= 0, CH_1, rank 0
6695 19:26:48.541528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6696 19:26:48.541624 ==
6697 19:26:48.541690 DQS Delay:
6698 19:26:48.544845 DQS0 = 35, DQS1 = 35
6699 19:26:48.544927 DQM Delay:
6700 19:26:48.547619 DQM0 = 17, DQM1 = 12
6701 19:26:48.547700 DQ Delay:
6702 19:26:48.551450 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =16
6703 19:26:48.554478 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6704 19:26:48.557977 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6705 19:26:48.561362 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =16
6706 19:26:48.561443
6707 19:26:48.561507
6708 19:26:48.561567 ==
6709 19:26:48.564645 Dram Type= 6, Freq= 0, CH_1, rank 0
6710 19:26:48.568122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6711 19:26:48.568204 ==
6712 19:26:48.568268
6713 19:26:48.571528
6714 19:26:48.571609 TX Vref Scan disable
6715 19:26:48.574843 == TX Byte 0 ==
6716 19:26:48.577551 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6717 19:26:48.580906 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6718 19:26:48.584211 == TX Byte 1 ==
6719 19:26:48.587438 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6720 19:26:48.591353 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6721 19:26:48.591434 ==
6722 19:26:48.594523 Dram Type= 6, Freq= 0, CH_1, rank 0
6723 19:26:48.597547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6724 19:26:48.597629 ==
6725 19:26:48.601400
6726 19:26:48.601481
6727 19:26:48.601545 TX Vref Scan disable
6728 19:26:48.604421 == TX Byte 0 ==
6729 19:26:48.607713 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6730 19:26:48.610791 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6731 19:26:48.614159 == TX Byte 1 ==
6732 19:26:48.617730 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6733 19:26:48.620801 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6734 19:26:48.620884
6735 19:26:48.620979 [DATLAT]
6736 19:26:48.624232 Freq=400, CH1 RK0
6737 19:26:48.624314
6738 19:26:48.627449 DATLAT Default: 0xf
6739 19:26:48.627531 0, 0xFFFF, sum = 0
6740 19:26:48.631258 1, 0xFFFF, sum = 0
6741 19:26:48.631341 2, 0xFFFF, sum = 0
6742 19:26:48.634532 3, 0xFFFF, sum = 0
6743 19:26:48.634641 4, 0xFFFF, sum = 0
6744 19:26:48.637384 5, 0xFFFF, sum = 0
6745 19:26:48.637473 6, 0xFFFF, sum = 0
6746 19:26:48.640728 7, 0xFFFF, sum = 0
6747 19:26:48.640814 8, 0xFFFF, sum = 0
6748 19:26:48.644568 9, 0xFFFF, sum = 0
6749 19:26:48.644653 10, 0xFFFF, sum = 0
6750 19:26:48.647773 11, 0xFFFF, sum = 0
6751 19:26:48.647858 12, 0xFFFF, sum = 0
6752 19:26:48.651113 13, 0x0, sum = 1
6753 19:26:48.651198 14, 0x0, sum = 2
6754 19:26:48.654518 15, 0x0, sum = 3
6755 19:26:48.654631 16, 0x0, sum = 4
6756 19:26:48.657259 best_step = 14
6757 19:26:48.657340
6758 19:26:48.657404 ==
6759 19:26:48.661119 Dram Type= 6, Freq= 0, CH_1, rank 0
6760 19:26:48.664249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6761 19:26:48.664323 ==
6762 19:26:48.664386 RX Vref Scan: 1
6763 19:26:48.667835
6764 19:26:48.667916 RX Vref 0 -> 0, step: 1
6765 19:26:48.667980
6766 19:26:48.671009 RX Delay -311 -> 252, step: 8
6767 19:26:48.671090
6768 19:26:48.674455 Set Vref, RX VrefLevel [Byte0]: 54
6769 19:26:48.677879 [Byte1]: 54
6770 19:26:48.681969
6771 19:26:48.682050 Final RX Vref Byte 0 = 54 to rank0
6772 19:26:48.685259 Final RX Vref Byte 1 = 54 to rank0
6773 19:26:48.688490 Final RX Vref Byte 0 = 54 to rank1
6774 19:26:48.691838 Final RX Vref Byte 1 = 54 to rank1==
6775 19:26:48.695025 Dram Type= 6, Freq= 0, CH_1, rank 0
6776 19:26:48.701751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6777 19:26:48.701833 ==
6778 19:26:48.701898 DQS Delay:
6779 19:26:48.705231 DQS0 = 32, DQS1 = 32
6780 19:26:48.705312 DQM Delay:
6781 19:26:48.705376 DQM0 = 13, DQM1 = 9
6782 19:26:48.708640 DQ Delay:
6783 19:26:48.711383 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6784 19:26:48.714800 DQ4 =12, DQ5 =24, DQ6 =20, DQ7 =12
6785 19:26:48.714881 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6786 19:26:48.718188 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6787 19:26:48.718269
6788 19:26:48.721520
6789 19:26:48.727957 [DQSOSCAuto] RK0, (LSB)MR18= 0x97d0, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 390 ps
6790 19:26:48.731110 CH1 RK0: MR19=C0C, MR18=97D0
6791 19:26:48.738265 CH1_RK0: MR19=0xC0C, MR18=0x97D0, DQSOSC=384, MR23=63, INC=400, DEC=267
6792 19:26:48.738389 ==
6793 19:26:48.741122 Dram Type= 6, Freq= 0, CH_1, rank 1
6794 19:26:48.744544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6795 19:26:48.744626 ==
6796 19:26:48.747700 [Gating] SW mode calibration
6797 19:26:48.754609 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6798 19:26:48.761602 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6799 19:26:48.764556 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6800 19:26:48.768009 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6801 19:26:48.774339 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6802 19:26:48.777973 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6803 19:26:48.781041 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6804 19:26:48.787662 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6805 19:26:48.791215 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6806 19:26:48.794499 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6807 19:26:48.801139 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6808 19:26:48.801221 Total UI for P1: 0, mck2ui 16
6809 19:26:48.804432 best dqsien dly found for B0: ( 0, 14, 24)
6810 19:26:48.807804 Total UI for P1: 0, mck2ui 16
6811 19:26:48.811161 best dqsien dly found for B1: ( 0, 14, 24)
6812 19:26:48.817177 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6813 19:26:48.820566 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6814 19:26:48.820667
6815 19:26:48.823854 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6816 19:26:48.827256 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6817 19:26:48.830635 [Gating] SW calibration Done
6818 19:26:48.830716 ==
6819 19:26:48.834126 Dram Type= 6, Freq= 0, CH_1, rank 1
6820 19:26:48.837397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6821 19:26:48.837478 ==
6822 19:26:48.840844 RX Vref Scan: 0
6823 19:26:48.840925
6824 19:26:48.840989 RX Vref 0 -> 0, step: 1
6825 19:26:48.841049
6826 19:26:48.844283 RX Delay -410 -> 252, step: 16
6827 19:26:48.850757 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6828 19:26:48.854168 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6829 19:26:48.857433 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6830 19:26:48.860228 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6831 19:26:48.867017 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6832 19:26:48.870570 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6833 19:26:48.874170 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6834 19:26:48.876824 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6835 19:26:48.880333 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6836 19:26:48.887105 iDelay=230, Bit 9, Center -27 (-266 ~ 213) 480
6837 19:26:48.890343 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6838 19:26:48.893565 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6839 19:26:48.897171 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6840 19:26:48.903626 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6841 19:26:48.906938 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6842 19:26:48.910450 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6843 19:26:48.910535 ==
6844 19:26:48.913665 Dram Type= 6, Freq= 0, CH_1, rank 1
6845 19:26:48.920149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6846 19:26:48.920235 ==
6847 19:26:48.920321 DQS Delay:
6848 19:26:48.923573 DQS0 = 35, DQS1 = 35
6849 19:26:48.923656 DQM Delay:
6850 19:26:48.923741 DQM0 = 18, DQM1 = 14
6851 19:26:48.926938 DQ Delay:
6852 19:26:48.930405 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6853 19:26:48.933771 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6854 19:26:48.933855 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6855 19:26:48.940634 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6856 19:26:48.940718
6857 19:26:48.940802
6858 19:26:48.940916 ==
6859 19:26:48.943878 Dram Type= 6, Freq= 0, CH_1, rank 1
6860 19:26:48.947245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6861 19:26:48.947326 ==
6862 19:26:48.947391
6863 19:26:48.947450
6864 19:26:48.949984 TX Vref Scan disable
6865 19:26:48.950066 == TX Byte 0 ==
6866 19:26:48.953364 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6867 19:26:48.960035 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6868 19:26:48.960117 == TX Byte 1 ==
6869 19:26:48.963416 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6870 19:26:48.970171 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6871 19:26:48.970252 ==
6872 19:26:48.973528 Dram Type= 6, Freq= 0, CH_1, rank 1
6873 19:26:48.976908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6874 19:26:48.976990 ==
6875 19:26:48.977054
6876 19:26:48.977114
6877 19:26:48.980322 TX Vref Scan disable
6878 19:26:48.980403 == TX Byte 0 ==
6879 19:26:48.987175 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6880 19:26:48.990390 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6881 19:26:48.990484 == TX Byte 1 ==
6882 19:26:48.993177 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6883 19:26:49.000148 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6884 19:26:49.000231
6885 19:26:49.000322 [DATLAT]
6886 19:26:49.003403 Freq=400, CH1 RK1
6887 19:26:49.003485
6888 19:26:49.003553 DATLAT Default: 0xe
6889 19:26:49.006382 0, 0xFFFF, sum = 0
6890 19:26:49.006468 1, 0xFFFF, sum = 0
6891 19:26:49.009887 2, 0xFFFF, sum = 0
6892 19:26:49.009980 3, 0xFFFF, sum = 0
6893 19:26:49.013633 4, 0xFFFF, sum = 0
6894 19:26:49.013718 5, 0xFFFF, sum = 0
6895 19:26:49.016637 6, 0xFFFF, sum = 0
6896 19:26:49.016722 7, 0xFFFF, sum = 0
6897 19:26:49.020015 8, 0xFFFF, sum = 0
6898 19:26:49.020101 9, 0xFFFF, sum = 0
6899 19:26:49.023128 10, 0xFFFF, sum = 0
6900 19:26:49.023214 11, 0xFFFF, sum = 0
6901 19:26:49.026640 12, 0xFFFF, sum = 0
6902 19:26:49.026726 13, 0x0, sum = 1
6903 19:26:49.029895 14, 0x0, sum = 2
6904 19:26:49.029981 15, 0x0, sum = 3
6905 19:26:49.033188 16, 0x0, sum = 4
6906 19:26:49.033273 best_step = 14
6907 19:26:49.033375
6908 19:26:49.033472 ==
6909 19:26:49.036560 Dram Type= 6, Freq= 0, CH_1, rank 1
6910 19:26:49.043365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6911 19:26:49.043451 ==
6912 19:26:49.043536 RX Vref Scan: 0
6913 19:26:49.043616
6914 19:26:49.046852 RX Vref 0 -> 0, step: 1
6915 19:26:49.046933
6916 19:26:49.050360 RX Delay -311 -> 252, step: 8
6917 19:26:49.056766 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6918 19:26:49.060053 iDelay=217, Bit 1, Center -20 (-239 ~ 200) 440
6919 19:26:49.063424 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6920 19:26:49.066686 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6921 19:26:49.072849 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6922 19:26:49.076170 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6923 19:26:49.079599 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6924 19:26:49.082966 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
6925 19:26:49.089774 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6926 19:26:49.093212 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6927 19:26:49.096474 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6928 19:26:49.099843 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
6929 19:26:49.106446 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6930 19:26:49.109793 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6931 19:26:49.113601 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6932 19:26:49.116175 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6933 19:26:49.116259 ==
6934 19:26:49.119268 Dram Type= 6, Freq= 0, CH_1, rank 1
6935 19:26:49.126177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6936 19:26:49.126262 ==
6937 19:26:49.126389 DQS Delay:
6938 19:26:49.129372 DQS0 = 28, DQS1 = 32
6939 19:26:49.129457 DQM Delay:
6940 19:26:49.133317 DQM0 = 11, DQM1 = 11
6941 19:26:49.133400 DQ Delay:
6942 19:26:49.135930 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6943 19:26:49.139314 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =12
6944 19:26:49.139399 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6945 19:26:49.146455 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6946 19:26:49.146553
6947 19:26:49.146638
6948 19:26:49.152631 [DQSOSCAuto] RK1, (LSB)MR18= 0xc455, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 385 ps
6949 19:26:49.156468 CH1 RK1: MR19=C0C, MR18=C455
6950 19:26:49.162547 CH1_RK1: MR19=0xC0C, MR18=0xC455, DQSOSC=385, MR23=63, INC=398, DEC=265
6951 19:26:49.166065 [RxdqsGatingPostProcess] freq 400
6952 19:26:49.169575 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6953 19:26:49.172812 best DQS0 dly(2T, 0.5T) = (0, 10)
6954 19:26:49.175798 best DQS1 dly(2T, 0.5T) = (0, 10)
6955 19:26:49.178989 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6956 19:26:49.182674 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6957 19:26:49.185987 best DQS0 dly(2T, 0.5T) = (0, 10)
6958 19:26:49.189441 best DQS1 dly(2T, 0.5T) = (0, 10)
6959 19:26:49.192806 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6960 19:26:49.196195 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6961 19:26:49.198970 Pre-setting of DQS Precalculation
6962 19:26:49.202423 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6963 19:26:49.212363 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6964 19:26:49.219094 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6965 19:26:49.219177
6966 19:26:49.219257
6967 19:26:49.222317 [Calibration Summary] 800 Mbps
6968 19:26:49.222445 CH 0, Rank 0
6969 19:26:49.225429 SW Impedance : PASS
6970 19:26:49.225524 DUTY Scan : NO K
6971 19:26:49.228823 ZQ Calibration : PASS
6972 19:26:49.232310 Jitter Meter : NO K
6973 19:26:49.232423 CBT Training : PASS
6974 19:26:49.235539 Write leveling : PASS
6975 19:26:49.238876 RX DQS gating : PASS
6976 19:26:49.238973 RX DQ/DQS(RDDQC) : PASS
6977 19:26:49.242114 TX DQ/DQS : PASS
6978 19:26:49.245531 RX DATLAT : PASS
6979 19:26:49.245628 RX DQ/DQS(Engine): PASS
6980 19:26:49.248742 TX OE : NO K
6981 19:26:49.248838 All Pass.
6982 19:26:49.248902
6983 19:26:49.252225 CH 0, Rank 1
6984 19:26:49.252306 SW Impedance : PASS
6985 19:26:49.255645 DUTY Scan : NO K
6986 19:26:49.255729 ZQ Calibration : PASS
6987 19:26:49.259068 Jitter Meter : NO K
6988 19:26:49.261745 CBT Training : PASS
6989 19:26:49.261828 Write leveling : NO K
6990 19:26:49.265109 RX DQS gating : PASS
6991 19:26:49.268880 RX DQ/DQS(RDDQC) : PASS
6992 19:26:49.268981 TX DQ/DQS : PASS
6993 19:26:49.272493 RX DATLAT : PASS
6994 19:26:49.275018 RX DQ/DQS(Engine): PASS
6995 19:26:49.275102 TX OE : NO K
6996 19:26:49.278851 All Pass.
6997 19:26:49.278934
6998 19:26:49.278999 CH 1, Rank 0
6999 19:26:49.281977 SW Impedance : PASS
7000 19:26:49.282077 DUTY Scan : NO K
7001 19:26:49.285284 ZQ Calibration : PASS
7002 19:26:49.288554 Jitter Meter : NO K
7003 19:26:49.288637 CBT Training : PASS
7004 19:26:49.291733 Write leveling : PASS
7005 19:26:49.295148 RX DQS gating : PASS
7006 19:26:49.295231 RX DQ/DQS(RDDQC) : PASS
7007 19:26:49.298576 TX DQ/DQS : PASS
7008 19:26:49.301877 RX DATLAT : PASS
7009 19:26:49.301960 RX DQ/DQS(Engine): PASS
7010 19:26:49.305115 TX OE : NO K
7011 19:26:49.305199 All Pass.
7012 19:26:49.305265
7013 19:26:49.308399 CH 1, Rank 1
7014 19:26:49.308499 SW Impedance : PASS
7015 19:26:49.311599 DUTY Scan : NO K
7016 19:26:49.311683 ZQ Calibration : PASS
7017 19:26:49.314932 Jitter Meter : NO K
7018 19:26:49.318597 CBT Training : PASS
7019 19:26:49.318681 Write leveling : NO K
7020 19:26:49.321634 RX DQS gating : PASS
7021 19:26:49.324946 RX DQ/DQS(RDDQC) : PASS
7022 19:26:49.325030 TX DQ/DQS : PASS
7023 19:26:49.328300 RX DATLAT : PASS
7024 19:26:49.331457 RX DQ/DQS(Engine): PASS
7025 19:26:49.331566 TX OE : NO K
7026 19:26:49.334772 All Pass.
7027 19:26:49.334855
7028 19:26:49.334938 DramC Write-DBI off
7029 19:26:49.338782 PER_BANK_REFRESH: Hybrid Mode
7030 19:26:49.338867 TX_TRACKING: ON
7031 19:26:49.348095 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7032 19:26:49.351941 [FAST_K] Save calibration result to emmc
7033 19:26:49.355348 dramc_set_vcore_voltage set vcore to 725000
7034 19:26:49.358106 Read voltage for 1600, 0
7035 19:26:49.358213 Vio18 = 0
7036 19:26:49.361559 Vcore = 725000
7037 19:26:49.361642 Vdram = 0
7038 19:26:49.361706 Vddq = 0
7039 19:26:49.364887 Vmddr = 0
7040 19:26:49.368237 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7041 19:26:49.374859 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7042 19:26:49.374938 MEM_TYPE=3, freq_sel=13
7043 19:26:49.378541 sv_algorithm_assistance_LP4_3733
7044 19:26:49.384925 ============ PULL DRAM RESETB DOWN ============
7045 19:26:49.388094 ========== PULL DRAM RESETB DOWN end =========
7046 19:26:49.391481 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7047 19:26:49.394797 ===================================
7048 19:26:49.398184 LPDDR4 DRAM CONFIGURATION
7049 19:26:49.401550 ===================================
7050 19:26:49.401633 EX_ROW_EN[0] = 0x0
7051 19:26:49.404974 EX_ROW_EN[1] = 0x0
7052 19:26:49.408275 LP4Y_EN = 0x0
7053 19:26:49.408378 WORK_FSP = 0x1
7054 19:26:49.411582 WL = 0x5
7055 19:26:49.411657 RL = 0x5
7056 19:26:49.414409 BL = 0x2
7057 19:26:49.414486 RPST = 0x0
7058 19:26:49.418044 RD_PRE = 0x0
7059 19:26:49.418147 WR_PRE = 0x1
7060 19:26:49.421171 WR_PST = 0x1
7061 19:26:49.421276 DBI_WR = 0x0
7062 19:26:49.424216 DBI_RD = 0x0
7063 19:26:49.424290 OTF = 0x1
7064 19:26:49.427588 ===================================
7065 19:26:49.431151 ===================================
7066 19:26:49.434681 ANA top config
7067 19:26:49.437900 ===================================
7068 19:26:49.441147 DLL_ASYNC_EN = 0
7069 19:26:49.441250 ALL_SLAVE_EN = 0
7070 19:26:49.444258 NEW_RANK_MODE = 1
7071 19:26:49.447780 DLL_IDLE_MODE = 1
7072 19:26:49.451390 LP45_APHY_COMB_EN = 1
7073 19:26:49.451475 TX_ODT_DIS = 0
7074 19:26:49.454282 NEW_8X_MODE = 1
7075 19:26:49.457882 ===================================
7076 19:26:49.461190 ===================================
7077 19:26:49.464620 data_rate = 3200
7078 19:26:49.468087 CKR = 1
7079 19:26:49.471432 DQ_P2S_RATIO = 8
7080 19:26:49.474668 ===================================
7081 19:26:49.474777 CA_P2S_RATIO = 8
7082 19:26:49.477894 DQ_CA_OPEN = 0
7083 19:26:49.481302 DQ_SEMI_OPEN = 0
7084 19:26:49.484142 CA_SEMI_OPEN = 0
7085 19:26:49.487499 CA_FULL_RATE = 0
7086 19:26:49.490677 DQ_CKDIV4_EN = 0
7087 19:26:49.490760 CA_CKDIV4_EN = 0
7088 19:26:49.494590 CA_PREDIV_EN = 0
7089 19:26:49.497801 PH8_DLY = 12
7090 19:26:49.501276 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7091 19:26:49.504046 DQ_AAMCK_DIV = 4
7092 19:26:49.507482 CA_AAMCK_DIV = 4
7093 19:26:49.507566 CA_ADMCK_DIV = 4
7094 19:26:49.510776 DQ_TRACK_CA_EN = 0
7095 19:26:49.514135 CA_PICK = 1600
7096 19:26:49.517397 CA_MCKIO = 1600
7097 19:26:49.520739 MCKIO_SEMI = 0
7098 19:26:49.523913 PLL_FREQ = 3068
7099 19:26:49.527401 DQ_UI_PI_RATIO = 32
7100 19:26:49.530783 CA_UI_PI_RATIO = 0
7101 19:26:49.534164 ===================================
7102 19:26:49.537660 ===================================
7103 19:26:49.537736 memory_type:LPDDR4
7104 19:26:49.540400 GP_NUM : 10
7105 19:26:49.544216 SRAM_EN : 1
7106 19:26:49.544299 MD32_EN : 0
7107 19:26:49.547465 ===================================
7108 19:26:49.550494 [ANA_INIT] >>>>>>>>>>>>>>
7109 19:26:49.553434 <<<<<< [CONFIGURE PHASE]: ANA_TX
7110 19:26:49.557037 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7111 19:26:49.560352 ===================================
7112 19:26:49.563609 data_rate = 3200,PCW = 0X7600
7113 19:26:49.567260 ===================================
7114 19:26:49.570423 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7115 19:26:49.573582 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7116 19:26:49.580375 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7117 19:26:49.583138 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7118 19:26:49.586627 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7119 19:26:49.593196 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7120 19:26:49.593279 [ANA_INIT] flow start
7121 19:26:49.596491 [ANA_INIT] PLL >>>>>>>>
7122 19:26:49.596576 [ANA_INIT] PLL <<<<<<<<
7123 19:26:49.599691 [ANA_INIT] MIDPI >>>>>>>>
7124 19:26:49.602993 [ANA_INIT] MIDPI <<<<<<<<
7125 19:26:49.606450 [ANA_INIT] DLL >>>>>>>>
7126 19:26:49.606532 [ANA_INIT] DLL <<<<<<<<
7127 19:26:49.609798 [ANA_INIT] flow end
7128 19:26:49.613179 ============ LP4 DIFF to SE enter ============
7129 19:26:49.616599 ============ LP4 DIFF to SE exit ============
7130 19:26:49.619940 [ANA_INIT] <<<<<<<<<<<<<
7131 19:26:49.623337 [Flow] Enable top DCM control >>>>>
7132 19:26:49.626646 [Flow] Enable top DCM control <<<<<
7133 19:26:49.629877 Enable DLL master slave shuffle
7134 19:26:49.636734 ==============================================================
7135 19:26:49.636831 Gating Mode config
7136 19:26:49.642864 ==============================================================
7137 19:26:49.642946 Config description:
7138 19:26:49.653024 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7139 19:26:49.660009 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7140 19:26:49.666117 SELPH_MODE 0: By rank 1: By Phase
7141 19:26:49.669513 ==============================================================
7142 19:26:49.672731 GAT_TRACK_EN = 1
7143 19:26:49.676208 RX_GATING_MODE = 2
7144 19:26:49.679410 RX_GATING_TRACK_MODE = 2
7145 19:26:49.682626 SELPH_MODE = 1
7146 19:26:49.686257 PICG_EARLY_EN = 1
7147 19:26:49.689772 VALID_LAT_VALUE = 1
7148 19:26:49.696090 ==============================================================
7149 19:26:49.699473 Enter into Gating configuration >>>>
7150 19:26:49.703085 Exit from Gating configuration <<<<
7151 19:26:49.703167 Enter into DVFS_PRE_config >>>>>
7152 19:26:49.715868 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7153 19:26:49.719106 Exit from DVFS_PRE_config <<<<<
7154 19:26:49.722285 Enter into PICG configuration >>>>
7155 19:26:49.726117 Exit from PICG configuration <<<<
7156 19:26:49.726218 [RX_INPUT] configuration >>>>>
7157 19:26:49.729197 [RX_INPUT] configuration <<<<<
7158 19:26:49.735906 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7159 19:26:49.738979 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7160 19:26:49.745493 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7161 19:26:49.752362 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7162 19:26:49.759196 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7163 19:26:49.765823 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7164 19:26:49.768974 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7165 19:26:49.772410 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7166 19:26:49.779057 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7167 19:26:49.782508 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7168 19:26:49.785828 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7169 19:26:49.792465 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7170 19:26:49.792547 ===================================
7171 19:26:49.795212 LPDDR4 DRAM CONFIGURATION
7172 19:26:49.798587 ===================================
7173 19:26:49.801960 EX_ROW_EN[0] = 0x0
7174 19:26:49.802041 EX_ROW_EN[1] = 0x0
7175 19:26:49.805360 LP4Y_EN = 0x0
7176 19:26:49.805441 WORK_FSP = 0x1
7177 19:26:49.808746 WL = 0x5
7178 19:26:49.808827 RL = 0x5
7179 19:26:49.812440 BL = 0x2
7180 19:26:49.812522 RPST = 0x0
7181 19:26:49.815517 RD_PRE = 0x0
7182 19:26:49.818831 WR_PRE = 0x1
7183 19:26:49.818933 WR_PST = 0x1
7184 19:26:49.822259 DBI_WR = 0x0
7185 19:26:49.822385 DBI_RD = 0x0
7186 19:26:49.825591 OTF = 0x1
7187 19:26:49.828754 ===================================
7188 19:26:49.831766 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7189 19:26:49.835478 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7190 19:26:49.838936 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7191 19:26:49.842149 ===================================
7192 19:26:49.844990 LPDDR4 DRAM CONFIGURATION
7193 19:26:49.848469 ===================================
7194 19:26:49.851975 EX_ROW_EN[0] = 0x10
7195 19:26:49.852050 EX_ROW_EN[1] = 0x0
7196 19:26:49.855159 LP4Y_EN = 0x0
7197 19:26:49.855235 WORK_FSP = 0x1
7198 19:26:49.858416 WL = 0x5
7199 19:26:49.858488 RL = 0x5
7200 19:26:49.862037 BL = 0x2
7201 19:26:49.862139 RPST = 0x0
7202 19:26:49.864964 RD_PRE = 0x0
7203 19:26:49.865052 WR_PRE = 0x1
7204 19:26:49.868316 WR_PST = 0x1
7205 19:26:49.871650 DBI_WR = 0x0
7206 19:26:49.871731 DBI_RD = 0x0
7207 19:26:49.874823 OTF = 0x1
7208 19:26:49.878144 ===================================
7209 19:26:49.881420 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7210 19:26:49.884720 ==
7211 19:26:49.884809 Dram Type= 6, Freq= 0, CH_0, rank 0
7212 19:26:49.891551 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7213 19:26:49.891625 ==
7214 19:26:49.891690 [Duty_Offset_Calibration]
7215 19:26:49.894846 B0:2 B1:1 CA:1
7216 19:26:49.894922
7217 19:26:49.898074 [DutyScan_Calibration_Flow] k_type=0
7218 19:26:49.908307
7219 19:26:49.908385 ==CLK 0==
7220 19:26:49.911117 Final CLK duty delay cell = 0
7221 19:26:49.914505 [0] MAX Duty = 5156%(X100), DQS PI = 22
7222 19:26:49.917864 [0] MIN Duty = 4844%(X100), DQS PI = 48
7223 19:26:49.917941 [0] AVG Duty = 5000%(X100)
7224 19:26:49.921246
7225 19:26:49.924524 CH0 CLK Duty spec in!! Max-Min= 312%
7226 19:26:49.928122 [DutyScan_Calibration_Flow] ====Done====
7227 19:26:49.928196
7228 19:26:49.930923 [DutyScan_Calibration_Flow] k_type=1
7229 19:26:49.947377
7230 19:26:49.947488 ==DQS 0 ==
7231 19:26:49.950647 Final DQS duty delay cell = -4
7232 19:26:49.953925 [-4] MAX Duty = 5125%(X100), DQS PI = 24
7233 19:26:49.957350 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7234 19:26:49.960804 [-4] AVG Duty = 4891%(X100)
7235 19:26:49.960876
7236 19:26:49.960941 ==DQS 1 ==
7237 19:26:49.963525 Final DQS duty delay cell = 0
7238 19:26:49.966841 [0] MAX Duty = 5187%(X100), DQS PI = 4
7239 19:26:49.970540 [0] MIN Duty = 5031%(X100), DQS PI = 52
7240 19:26:49.973681 [0] AVG Duty = 5109%(X100)
7241 19:26:49.973754
7242 19:26:49.977261 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7243 19:26:49.977335
7244 19:26:49.980122 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7245 19:26:49.983518 [DutyScan_Calibration_Flow] ====Done====
7246 19:26:49.983592
7247 19:26:49.986749 [DutyScan_Calibration_Flow] k_type=3
7248 19:26:50.004414
7249 19:26:50.004524 ==DQM 0 ==
7250 19:26:50.007782 Final DQM duty delay cell = 0
7251 19:26:50.011167 [0] MAX Duty = 5218%(X100), DQS PI = 34
7252 19:26:50.014533 [0] MIN Duty = 4875%(X100), DQS PI = 60
7253 19:26:50.017881 [0] AVG Duty = 5046%(X100)
7254 19:26:50.017957
7255 19:26:50.018019 ==DQM 1 ==
7256 19:26:50.021294 Final DQM duty delay cell = 0
7257 19:26:50.024813 [0] MAX Duty = 5187%(X100), DQS PI = 4
7258 19:26:50.027598 [0] MIN Duty = 5062%(X100), DQS PI = 12
7259 19:26:50.030966 [0] AVG Duty = 5124%(X100)
7260 19:26:50.031056
7261 19:26:50.034478 CH0 DQM 0 Duty spec in!! Max-Min= 343%
7262 19:26:50.034588
7263 19:26:50.037829 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7264 19:26:50.040912 [DutyScan_Calibration_Flow] ====Done====
7265 19:26:50.041031
7266 19:26:50.044548 [DutyScan_Calibration_Flow] k_type=2
7267 19:26:50.061478
7268 19:26:50.061570 ==DQ 0 ==
7269 19:26:50.065024 Final DQ duty delay cell = 0
7270 19:26:50.068201 [0] MAX Duty = 5062%(X100), DQS PI = 26
7271 19:26:50.071517 [0] MIN Duty = 4907%(X100), DQS PI = 0
7272 19:26:50.071614 [0] AVG Duty = 4984%(X100)
7273 19:26:50.071708
7274 19:26:50.074966 ==DQ 1 ==
7275 19:26:50.078399 Final DQ duty delay cell = 0
7276 19:26:50.081742 [0] MAX Duty = 5125%(X100), DQS PI = 22
7277 19:26:50.085198 [0] MIN Duty = 4907%(X100), DQS PI = 34
7278 19:26:50.085295 [0] AVG Duty = 5016%(X100)
7279 19:26:50.085375
7280 19:26:50.088419 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7281 19:26:50.091620
7282 19:26:50.094671 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7283 19:26:50.098084 [DutyScan_Calibration_Flow] ====Done====
7284 19:26:50.098189 ==
7285 19:26:50.101942 Dram Type= 6, Freq= 0, CH_1, rank 0
7286 19:26:50.105083 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7287 19:26:50.105169 ==
7288 19:26:50.108045 [Duty_Offset_Calibration]
7289 19:26:50.108157 B0:1 B1:0 CA:0
7290 19:26:50.108248
7291 19:26:50.111597 [DutyScan_Calibration_Flow] k_type=0
7292 19:26:50.121154
7293 19:26:50.121284 ==CLK 0==
7294 19:26:50.124477 Final CLK duty delay cell = -4
7295 19:26:50.127958 [-4] MAX Duty = 4969%(X100), DQS PI = 24
7296 19:26:50.130682 [-4] MIN Duty = 4844%(X100), DQS PI = 2
7297 19:26:50.134727 [-4] AVG Duty = 4906%(X100)
7298 19:26:50.134840
7299 19:26:50.137426 CH1 CLK Duty spec in!! Max-Min= 125%
7300 19:26:50.141443 [DutyScan_Calibration_Flow] ====Done====
7301 19:26:50.141555
7302 19:26:50.144164 [DutyScan_Calibration_Flow] k_type=1
7303 19:26:50.160924
7304 19:26:50.161070 ==DQS 0 ==
7305 19:26:50.164683 Final DQS duty delay cell = 0
7306 19:26:50.167685 [0] MAX Duty = 5094%(X100), DQS PI = 30
7307 19:26:50.171294 [0] MIN Duty = 4844%(X100), DQS PI = 48
7308 19:26:50.174063 [0] AVG Duty = 4969%(X100)
7309 19:26:50.174189
7310 19:26:50.174279 ==DQS 1 ==
7311 19:26:50.177443 Final DQS duty delay cell = 0
7312 19:26:50.180799 [0] MAX Duty = 5249%(X100), DQS PI = 16
7313 19:26:50.184268 [0] MIN Duty = 4938%(X100), DQS PI = 8
7314 19:26:50.187245 [0] AVG Duty = 5093%(X100)
7315 19:26:50.187368
7316 19:26:50.190452 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7317 19:26:50.190538
7318 19:26:50.193816 CH1 DQS 1 Duty spec in!! Max-Min= 311%
7319 19:26:50.197272 [DutyScan_Calibration_Flow] ====Done====
7320 19:26:50.197371
7321 19:26:50.200428 [DutyScan_Calibration_Flow] k_type=3
7322 19:26:50.217749
7323 19:26:50.217865 ==DQM 0 ==
7324 19:26:50.221066 Final DQM duty delay cell = 0
7325 19:26:50.224324 [0] MAX Duty = 5187%(X100), DQS PI = 8
7326 19:26:50.227769 [0] MIN Duty = 4969%(X100), DQS PI = 48
7327 19:26:50.231110 [0] AVG Duty = 5078%(X100)
7328 19:26:50.231200
7329 19:26:50.231271 ==DQM 1 ==
7330 19:26:50.234887 Final DQM duty delay cell = 0
7331 19:26:50.237674 [0] MAX Duty = 5093%(X100), DQS PI = 18
7332 19:26:50.241040 [0] MIN Duty = 4907%(X100), DQS PI = 34
7333 19:26:50.241150 [0] AVG Duty = 5000%(X100)
7334 19:26:50.244646
7335 19:26:50.248173 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7336 19:26:50.248283
7337 19:26:50.251108 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7338 19:26:50.254450 [DutyScan_Calibration_Flow] ====Done====
7339 19:26:50.254555
7340 19:26:50.257653 [DutyScan_Calibration_Flow] k_type=2
7341 19:26:50.273927
7342 19:26:50.274043 ==DQ 0 ==
7343 19:26:50.277315 Final DQ duty delay cell = -4
7344 19:26:50.280624 [-4] MAX Duty = 5031%(X100), DQS PI = 10
7345 19:26:50.283979 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7346 19:26:50.287174 [-4] AVG Duty = 4953%(X100)
7347 19:26:50.287256
7348 19:26:50.287324 ==DQ 1 ==
7349 19:26:50.290682 Final DQ duty delay cell = 0
7350 19:26:50.294086 [0] MAX Duty = 5124%(X100), DQS PI = 18
7351 19:26:50.297470 [0] MIN Duty = 4938%(X100), DQS PI = 8
7352 19:26:50.300302 [0] AVG Duty = 5031%(X100)
7353 19:26:50.300415
7354 19:26:50.303896 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7355 19:26:50.303974
7356 19:26:50.307351 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7357 19:26:50.310526 [DutyScan_Calibration_Flow] ====Done====
7358 19:26:50.313706 nWR fixed to 30
7359 19:26:50.316793 [ModeRegInit_LP4] CH0 RK0
7360 19:26:50.316873 [ModeRegInit_LP4] CH0 RK1
7361 19:26:50.320170 [ModeRegInit_LP4] CH1 RK0
7362 19:26:50.323515 [ModeRegInit_LP4] CH1 RK1
7363 19:26:50.323597 match AC timing 5
7364 19:26:50.330147 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7365 19:26:50.333496 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7366 19:26:50.336881 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7367 19:26:50.343528 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7368 19:26:50.346863 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7369 19:26:50.346968 [MiockJmeterHQA]
7370 19:26:50.347065
7371 19:26:50.349928 [DramcMiockJmeter] u1RxGatingPI = 0
7372 19:26:50.353529 0 : 4363, 4137
7373 19:26:50.353641 4 : 4253, 4027
7374 19:26:50.356737 8 : 4364, 4137
7375 19:26:50.356813 12 : 4253, 4027
7376 19:26:50.360653 16 : 4363, 4138
7377 19:26:50.360730 20 : 4253, 4027
7378 19:26:50.360805 24 : 4252, 4027
7379 19:26:50.363441 28 : 4253, 4027
7380 19:26:50.363520 32 : 4255, 4029
7381 19:26:50.366673 36 : 4250, 4027
7382 19:26:50.366750 40 : 4363, 4137
7383 19:26:50.369838 44 : 4361, 4137
7384 19:26:50.369950 48 : 4250, 4027
7385 19:26:50.370027 52 : 4252, 4026
7386 19:26:50.373773 56 : 4250, 4027
7387 19:26:50.373845 60 : 4250, 4027
7388 19:26:50.377098 64 : 4252, 4029
7389 19:26:50.377170 68 : 4360, 4138
7390 19:26:50.379823 72 : 4252, 4026
7391 19:26:50.379922 76 : 4250, 4027
7392 19:26:50.383142 80 : 4250, 4027
7393 19:26:50.383217 84 : 4253, 4025
7394 19:26:50.383290 88 : 4250, 27
7395 19:26:50.386645 92 : 4250, 0
7396 19:26:50.386726 96 : 4252, 0
7397 19:26:50.390095 100 : 4361, 0
7398 19:26:50.390174 104 : 4250, 0
7399 19:26:50.390250 108 : 4250, 0
7400 19:26:50.393567 112 : 4250, 0
7401 19:26:50.393664 116 : 4250, 0
7402 19:26:50.393779 120 : 4250, 0
7403 19:26:50.396973 124 : 4250, 0
7404 19:26:50.397051 128 : 4250, 0
7405 19:26:50.399717 132 : 4250, 0
7406 19:26:50.399789 136 : 4253, 0
7407 19:26:50.399871 140 : 4250, 0
7408 19:26:50.403128 144 : 4250, 0
7409 19:26:50.403213 148 : 4252, 0
7410 19:26:50.406549 152 : 4250, 0
7411 19:26:50.406631 156 : 4360, 0
7412 19:26:50.406700 160 : 4361, 0
7413 19:26:50.409593 164 : 4361, 0
7414 19:26:50.409696 168 : 4361, 0
7415 19:26:50.413244 172 : 4250, 0
7416 19:26:50.413359 176 : 4250, 0
7417 19:26:50.413457 180 : 4250, 0
7418 19:26:50.416516 184 : 4250, 0
7419 19:26:50.416623 188 : 4253, 0
7420 19:26:50.416724 192 : 4250, 0
7421 19:26:50.419857 196 : 4250, 0
7422 19:26:50.419967 200 : 4252, 0
7423 19:26:50.422830 204 : 4363, 1295
7424 19:26:50.422940 208 : 4250, 3991
7425 19:26:50.426343 212 : 4361, 4137
7426 19:26:50.426463 216 : 4360, 4138
7427 19:26:50.429828 220 : 4250, 4027
7428 19:26:50.429933 224 : 4250, 4026
7429 19:26:50.433062 228 : 4363, 4139
7430 19:26:50.433164 232 : 4250, 4027
7431 19:26:50.433277 236 : 4250, 4027
7432 19:26:50.436454 240 : 4250, 4026
7433 19:26:50.436564 244 : 4253, 4029
7434 19:26:50.439863 248 : 4250, 4027
7435 19:26:50.439946 252 : 4250, 4027
7436 19:26:50.443257 256 : 4361, 4137
7437 19:26:50.443334 260 : 4250, 4026
7438 19:26:50.446472 264 : 4250, 4027
7439 19:26:50.446551 268 : 4360, 4138
7440 19:26:50.449775 272 : 4250, 4027
7441 19:26:50.449845 276 : 4250, 4026
7442 19:26:50.453186 280 : 4363, 4140
7443 19:26:50.453266 284 : 4250, 4027
7444 19:26:50.456360 288 : 4250, 4027
7445 19:26:50.456433 292 : 4250, 4026
7446 19:26:50.459625 296 : 4253, 4029
7447 19:26:50.459737 300 : 4250, 4027
7448 19:26:50.459836 304 : 4250, 4027
7449 19:26:50.463064 308 : 4361, 4005
7450 19:26:50.463140 312 : 4250, 1882
7451 19:26:50.463203
7452 19:26:50.465811 MIOCK jitter meter ch=0
7453 19:26:50.465878
7454 19:26:50.469762 1T = (312-88) = 224 dly cells
7455 19:26:50.476305 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7456 19:26:50.476411 ==
7457 19:26:50.479289 Dram Type= 6, Freq= 0, CH_0, rank 0
7458 19:26:50.482743 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7459 19:26:50.482826 ==
7460 19:26:50.489346 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7461 19:26:50.493065 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7462 19:26:50.495810 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7463 19:26:50.502580 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7464 19:26:50.511386 [CA 0] Center 43 (12~74) winsize 63
7465 19:26:50.514684 [CA 1] Center 43 (12~74) winsize 63
7466 19:26:50.518473 [CA 2] Center 38 (9~68) winsize 60
7467 19:26:50.521773 [CA 3] Center 38 (8~68) winsize 61
7468 19:26:50.524437 [CA 4] Center 37 (7~67) winsize 61
7469 19:26:50.527741 [CA 5] Center 35 (6~65) winsize 60
7470 19:26:50.527826
7471 19:26:50.531272 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7472 19:26:50.531347
7473 19:26:50.534686 [CATrainingPosCal] consider 1 rank data
7474 19:26:50.537990 u2DelayCellTimex100 = 290/100 ps
7475 19:26:50.541289 CA0 delay=43 (12~74),Diff = 8 PI (26 cell)
7476 19:26:50.547894 CA1 delay=43 (12~74),Diff = 8 PI (26 cell)
7477 19:26:50.551235 CA2 delay=38 (9~68),Diff = 3 PI (10 cell)
7478 19:26:50.554273 CA3 delay=38 (8~68),Diff = 3 PI (10 cell)
7479 19:26:50.557688 CA4 delay=37 (7~67),Diff = 2 PI (6 cell)
7480 19:26:50.561150 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7481 19:26:50.561225
7482 19:26:50.564511 CA PerBit enable=1, Macro0, CA PI delay=35
7483 19:26:50.564621
7484 19:26:50.567752 [CBTSetCACLKResult] CA Dly = 35
7485 19:26:50.570889 CS Dly: 9 (0~40)
7486 19:26:50.574634 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7487 19:26:50.577965 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7488 19:26:50.578069 ==
7489 19:26:50.581444 Dram Type= 6, Freq= 0, CH_0, rank 1
7490 19:26:50.584149 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7491 19:26:50.587506 ==
7492 19:26:50.591510 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7493 19:26:50.594313 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7494 19:26:50.601102 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7495 19:26:50.607501 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7496 19:26:50.615127 [CA 0] Center 42 (12~73) winsize 62
7497 19:26:50.618548 [CA 1] Center 42 (12~73) winsize 62
7498 19:26:50.621803 [CA 2] Center 37 (8~67) winsize 60
7499 19:26:50.625060 [CA 3] Center 37 (7~68) winsize 62
7500 19:26:50.628222 [CA 4] Center 35 (5~65) winsize 61
7501 19:26:50.631620 [CA 5] Center 35 (5~65) winsize 61
7502 19:26:50.631698
7503 19:26:50.635068 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7504 19:26:50.635140
7505 19:26:50.638482 [CATrainingPosCal] consider 2 rank data
7506 19:26:50.641260 u2DelayCellTimex100 = 290/100 ps
7507 19:26:50.645158 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7508 19:26:50.651739 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7509 19:26:50.655142 CA2 delay=38 (9~67),Diff = 3 PI (10 cell)
7510 19:26:50.658564 CA3 delay=38 (8~68),Diff = 3 PI (10 cell)
7511 19:26:50.661647 CA4 delay=36 (7~65),Diff = 1 PI (3 cell)
7512 19:26:50.665076 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7513 19:26:50.665155
7514 19:26:50.668310 CA PerBit enable=1, Macro0, CA PI delay=35
7515 19:26:50.668416
7516 19:26:50.671329 [CBTSetCACLKResult] CA Dly = 35
7517 19:26:50.675263 CS Dly: 10 (0~42)
7518 19:26:50.678178 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7519 19:26:50.681655 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7520 19:26:50.681757
7521 19:26:50.685032 ----->DramcWriteLeveling(PI) begin...
7522 19:26:50.685118 ==
7523 19:26:50.688068 Dram Type= 6, Freq= 0, CH_0, rank 0
7524 19:26:50.691661 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7525 19:26:50.695198 ==
7526 19:26:50.695276 Write leveling (Byte 0): 36 => 36
7527 19:26:50.698570 Write leveling (Byte 1): 28 => 28
7528 19:26:50.701809 DramcWriteLeveling(PI) end<-----
7529 19:26:50.701891
7530 19:26:50.701954 ==
7531 19:26:50.705268 Dram Type= 6, Freq= 0, CH_0, rank 0
7532 19:26:50.711565 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7533 19:26:50.711670 ==
7534 19:26:50.711772 [Gating] SW mode calibration
7535 19:26:50.721811 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7536 19:26:50.724890 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7537 19:26:50.731549 1 4 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7538 19:26:50.735072 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7539 19:26:50.738207 1 4 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7540 19:26:50.741428 1 4 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7541 19:26:50.748110 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7542 19:26:50.751559 1 4 20 | B1->B0 | 3434 3535 | 0 0 | (0 0) (0 0)
7543 19:26:50.754851 1 4 24 | B1->B0 | 3434 3635 | 1 1 | (1 1) (0 0)
7544 19:26:50.761473 1 4 28 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7545 19:26:50.764734 1 5 0 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7546 19:26:50.768087 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7547 19:26:50.774622 1 5 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
7548 19:26:50.777856 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7549 19:26:50.781267 1 5 16 | B1->B0 | 3434 2525 | 1 0 | (1 0) (0 0)
7550 19:26:50.787903 1 5 20 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
7551 19:26:50.791082 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7552 19:26:50.794152 1 5 28 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
7553 19:26:50.800895 1 6 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7554 19:26:50.804067 1 6 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7555 19:26:50.807631 1 6 8 | B1->B0 | 2323 3030 | 0 0 | (0 0) (1 1)
7556 19:26:50.814318 1 6 12 | B1->B0 | 2323 4545 | 0 0 | (0 0) (1 1)
7557 19:26:50.817686 1 6 16 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
7558 19:26:50.820521 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7559 19:26:50.827147 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7560 19:26:50.830438 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7561 19:26:50.834341 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7562 19:26:50.840731 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7563 19:26:50.844513 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7564 19:26:50.847532 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7565 19:26:50.854030 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7566 19:26:50.857492 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7567 19:26:50.860470 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7568 19:26:50.867393 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7569 19:26:50.870570 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7570 19:26:50.874168 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7571 19:26:50.880092 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7572 19:26:50.883432 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7573 19:26:50.886847 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7574 19:26:50.893776 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7575 19:26:50.897007 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7576 19:26:50.900295 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7577 19:26:50.906732 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7578 19:26:50.910003 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7579 19:26:50.913304 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7580 19:26:50.920121 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7581 19:26:50.923199 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7582 19:26:50.926835 Total UI for P1: 0, mck2ui 16
7583 19:26:50.930187 best dqsien dly found for B0: ( 1, 9, 10)
7584 19:26:50.933541 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7585 19:26:50.940305 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7586 19:26:50.940383 Total UI for P1: 0, mck2ui 16
7587 19:26:50.943014 best dqsien dly found for B1: ( 1, 9, 20)
7588 19:26:50.949825 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7589 19:26:50.953267 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7590 19:26:50.953349
7591 19:26:50.956659 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7592 19:26:50.959998 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7593 19:26:50.963619 [Gating] SW calibration Done
7594 19:26:50.963717 ==
7595 19:26:50.966459 Dram Type= 6, Freq= 0, CH_0, rank 0
7596 19:26:50.970096 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7597 19:26:50.970182 ==
7598 19:26:50.972968 RX Vref Scan: 0
7599 19:26:50.973045
7600 19:26:50.973109 RX Vref 0 -> 0, step: 1
7601 19:26:50.973173
7602 19:26:50.976392 RX Delay 0 -> 252, step: 8
7603 19:26:50.979875 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7604 19:26:50.986462 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7605 19:26:50.989814 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7606 19:26:50.992992 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7607 19:26:50.996652 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7608 19:26:50.999974 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7609 19:26:51.003360 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7610 19:26:51.009964 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7611 19:26:51.013035 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7612 19:26:51.016251 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7613 19:26:51.019552 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7614 19:26:51.023447 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7615 19:26:51.029441 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
7616 19:26:51.032757 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7617 19:26:51.036488 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7618 19:26:51.039436 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7619 19:26:51.039528 ==
7620 19:26:51.042720 Dram Type= 6, Freq= 0, CH_0, rank 0
7621 19:26:51.049454 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7622 19:26:51.049537 ==
7623 19:26:51.049602 DQS Delay:
7624 19:26:51.052894 DQS0 = 0, DQS1 = 0
7625 19:26:51.052976 DQM Delay:
7626 19:26:51.053042 DQM0 = 137, DQM1 = 130
7627 19:26:51.056411 DQ Delay:
7628 19:26:51.059718 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =131
7629 19:26:51.063118 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7630 19:26:51.066532 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
7631 19:26:51.069869 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =135
7632 19:26:51.069953
7633 19:26:51.070017
7634 19:26:51.070078 ==
7635 19:26:51.073324 Dram Type= 6, Freq= 0, CH_0, rank 0
7636 19:26:51.076607 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7637 19:26:51.079929 ==
7638 19:26:51.080040
7639 19:26:51.080138
7640 19:26:51.080207 TX Vref Scan disable
7641 19:26:51.083149 == TX Byte 0 ==
7642 19:26:51.086576 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7643 19:26:51.089296 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7644 19:26:51.092588 == TX Byte 1 ==
7645 19:26:51.096404 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7646 19:26:51.099365 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7647 19:26:51.102852 ==
7648 19:26:51.106258 Dram Type= 6, Freq= 0, CH_0, rank 0
7649 19:26:51.109491 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7650 19:26:51.109586 ==
7651 19:26:51.121314
7652 19:26:51.124456 TX Vref early break, caculate TX vref
7653 19:26:51.127764 TX Vref=16, minBit 0, minWin=23, winSum=380
7654 19:26:51.131072 TX Vref=18, minBit 4, minWin=23, winSum=388
7655 19:26:51.134491 TX Vref=20, minBit 1, minWin=23, winSum=396
7656 19:26:51.138005 TX Vref=22, minBit 2, minWin=24, winSum=409
7657 19:26:51.140736 TX Vref=24, minBit 0, minWin=25, winSum=421
7658 19:26:51.147836 TX Vref=26, minBit 0, minWin=25, winSum=423
7659 19:26:51.150830 TX Vref=28, minBit 6, minWin=25, winSum=428
7660 19:26:51.154207 TX Vref=30, minBit 2, minWin=24, winSum=408
7661 19:26:51.157427 TX Vref=32, minBit 1, minWin=24, winSum=402
7662 19:26:51.164170 [TxChooseVref] Worse bit 6, Min win 25, Win sum 428, Final Vref 28
7663 19:26:51.164253
7664 19:26:51.167551 Final TX Range 0 Vref 28
7665 19:26:51.167665
7666 19:26:51.167754 ==
7667 19:26:51.170877 Dram Type= 6, Freq= 0, CH_0, rank 0
7668 19:26:51.174265 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7669 19:26:51.174398 ==
7670 19:26:51.174495
7671 19:26:51.174577
7672 19:26:51.177645 TX Vref Scan disable
7673 19:26:51.180920 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7674 19:26:51.184299 == TX Byte 0 ==
7675 19:26:51.187742 u2DelayCellOfst[0]=10 cells (3 PI)
7676 19:26:51.191019 u2DelayCellOfst[1]=13 cells (4 PI)
7677 19:26:51.194264 u2DelayCellOfst[2]=10 cells (3 PI)
7678 19:26:51.197014 u2DelayCellOfst[3]=6 cells (2 PI)
7679 19:26:51.200391 u2DelayCellOfst[4]=6 cells (2 PI)
7680 19:26:51.203771 u2DelayCellOfst[5]=0 cells (0 PI)
7681 19:26:51.203879 u2DelayCellOfst[6]=16 cells (5 PI)
7682 19:26:51.207268 u2DelayCellOfst[7]=16 cells (5 PI)
7683 19:26:51.214054 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7684 19:26:51.217362 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7685 19:26:51.217459 == TX Byte 1 ==
7686 19:26:51.220171 u2DelayCellOfst[8]=0 cells (0 PI)
7687 19:26:51.224067 u2DelayCellOfst[9]=0 cells (0 PI)
7688 19:26:51.227337 u2DelayCellOfst[10]=10 cells (3 PI)
7689 19:26:51.230448 u2DelayCellOfst[11]=3 cells (1 PI)
7690 19:26:51.233477 u2DelayCellOfst[12]=10 cells (3 PI)
7691 19:26:51.237023 u2DelayCellOfst[13]=10 cells (3 PI)
7692 19:26:51.240472 u2DelayCellOfst[14]=13 cells (4 PI)
7693 19:26:51.243377 u2DelayCellOfst[15]=10 cells (3 PI)
7694 19:26:51.246925 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7695 19:26:51.253646 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7696 19:26:51.253756 DramC Write-DBI on
7697 19:26:51.253827 ==
7698 19:26:51.256722 Dram Type= 6, Freq= 0, CH_0, rank 0
7699 19:26:51.260266 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7700 19:26:51.260386 ==
7701 19:26:51.263420
7702 19:26:51.263505
7703 19:26:51.263571 TX Vref Scan disable
7704 19:26:51.267050 == TX Byte 0 ==
7705 19:26:51.270453 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7706 19:26:51.273372 == TX Byte 1 ==
7707 19:26:51.276954 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7708 19:26:51.280347 DramC Write-DBI off
7709 19:26:51.280451
7710 19:26:51.280536 [DATLAT]
7711 19:26:51.280632 Freq=1600, CH0 RK0
7712 19:26:51.280691
7713 19:26:51.283660 DATLAT Default: 0xf
7714 19:26:51.283732 0, 0xFFFF, sum = 0
7715 19:26:51.287103 1, 0xFFFF, sum = 0
7716 19:26:51.287176 2, 0xFFFF, sum = 0
7717 19:26:51.289917 3, 0xFFFF, sum = 0
7718 19:26:51.293333 4, 0xFFFF, sum = 0
7719 19:26:51.293447 5, 0xFFFF, sum = 0
7720 19:26:51.296592 6, 0xFFFF, sum = 0
7721 19:26:51.296673 7, 0xFFFF, sum = 0
7722 19:26:51.299961 8, 0xFFFF, sum = 0
7723 19:26:51.300040 9, 0xFFFF, sum = 0
7724 19:26:51.303342 10, 0xFFFF, sum = 0
7725 19:26:51.303443 11, 0xFFFF, sum = 0
7726 19:26:51.306706 12, 0xFFFF, sum = 0
7727 19:26:51.306787 13, 0xFFFF, sum = 0
7728 19:26:51.310206 14, 0x0, sum = 1
7729 19:26:51.310321 15, 0x0, sum = 2
7730 19:26:51.312918 16, 0x0, sum = 3
7731 19:26:51.313023 17, 0x0, sum = 4
7732 19:26:51.316393 best_step = 15
7733 19:26:51.316493
7734 19:26:51.316591 ==
7735 19:26:51.319632 Dram Type= 6, Freq= 0, CH_0, rank 0
7736 19:26:51.323079 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7737 19:26:51.323168 ==
7738 19:26:51.326493 RX Vref Scan: 1
7739 19:26:51.326569
7740 19:26:51.326636 Set Vref Range= 24 -> 127
7741 19:26:51.326705
7742 19:26:51.329935 RX Vref 24 -> 127, step: 1
7743 19:26:51.330042
7744 19:26:51.333126 RX Delay 19 -> 252, step: 4
7745 19:26:51.333228
7746 19:26:51.336601 Set Vref, RX VrefLevel [Byte0]: 24
7747 19:26:51.339771 [Byte1]: 24
7748 19:26:51.339846
7749 19:26:51.343167 Set Vref, RX VrefLevel [Byte0]: 25
7750 19:26:51.346534 [Byte1]: 25
7751 19:26:51.346648
7752 19:26:51.349900 Set Vref, RX VrefLevel [Byte0]: 26
7753 19:26:51.353304 [Byte1]: 26
7754 19:26:51.357157
7755 19:26:51.357267 Set Vref, RX VrefLevel [Byte0]: 27
7756 19:26:51.360519 [Byte1]: 27
7757 19:26:51.364526
7758 19:26:51.364604 Set Vref, RX VrefLevel [Byte0]: 28
7759 19:26:51.367613 [Byte1]: 28
7760 19:26:51.372561
7761 19:26:51.372646 Set Vref, RX VrefLevel [Byte0]: 29
7762 19:26:51.375494 [Byte1]: 29
7763 19:26:51.379574
7764 19:26:51.379654 Set Vref, RX VrefLevel [Byte0]: 30
7765 19:26:51.383185 [Byte1]: 30
7766 19:26:51.387262
7767 19:26:51.387343 Set Vref, RX VrefLevel [Byte0]: 31
7768 19:26:51.390853 [Byte1]: 31
7769 19:26:51.394884
7770 19:26:51.394957 Set Vref, RX VrefLevel [Byte0]: 32
7771 19:26:51.398246 [Byte1]: 32
7772 19:26:51.402162
7773 19:26:51.402273 Set Vref, RX VrefLevel [Byte0]: 33
7774 19:26:51.405572 [Byte1]: 33
7775 19:26:51.410329
7776 19:26:51.410420 Set Vref, RX VrefLevel [Byte0]: 34
7777 19:26:51.413030 [Byte1]: 34
7778 19:26:51.417764
7779 19:26:51.417897 Set Vref, RX VrefLevel [Byte0]: 35
7780 19:26:51.421143 [Byte1]: 35
7781 19:26:51.425086
7782 19:26:51.425192 Set Vref, RX VrefLevel [Byte0]: 36
7783 19:26:51.428487 [Byte1]: 36
7784 19:26:51.432620
7785 19:26:51.432720 Set Vref, RX VrefLevel [Byte0]: 37
7786 19:26:51.435818 [Byte1]: 37
7787 19:26:51.440451
7788 19:26:51.440550 Set Vref, RX VrefLevel [Byte0]: 38
7789 19:26:51.443682 [Byte1]: 38
7790 19:26:51.447663
7791 19:26:51.447738 Set Vref, RX VrefLevel [Byte0]: 39
7792 19:26:51.451105 [Byte1]: 39
7793 19:26:51.455610
7794 19:26:51.455695 Set Vref, RX VrefLevel [Byte0]: 40
7795 19:26:51.458928 [Byte1]: 40
7796 19:26:51.462880
7797 19:26:51.462961 Set Vref, RX VrefLevel [Byte0]: 41
7798 19:26:51.466173 [Byte1]: 41
7799 19:26:51.470902
7800 19:26:51.470983 Set Vref, RX VrefLevel [Byte0]: 42
7801 19:26:51.473713 [Byte1]: 42
7802 19:26:51.478494
7803 19:26:51.478576 Set Vref, RX VrefLevel [Byte0]: 43
7804 19:26:51.481766 [Byte1]: 43
7805 19:26:51.485739
7806 19:26:51.485822 Set Vref, RX VrefLevel [Byte0]: 44
7807 19:26:51.489090 [Byte1]: 44
7808 19:26:51.493547
7809 19:26:51.493628 Set Vref, RX VrefLevel [Byte0]: 45
7810 19:26:51.496476 [Byte1]: 45
7811 19:26:51.501084
7812 19:26:51.501162 Set Vref, RX VrefLevel [Byte0]: 46
7813 19:26:51.504347 [Byte1]: 46
7814 19:26:51.508448
7815 19:26:51.508523 Set Vref, RX VrefLevel [Byte0]: 47
7816 19:26:51.511751 [Byte1]: 47
7817 19:26:51.515857
7818 19:26:51.515934 Set Vref, RX VrefLevel [Byte0]: 48
7819 19:26:51.519473 [Byte1]: 48
7820 19:26:51.523500
7821 19:26:51.523581 Set Vref, RX VrefLevel [Byte0]: 49
7822 19:26:51.527081 [Byte1]: 49
7823 19:26:51.531142
7824 19:26:51.531272 Set Vref, RX VrefLevel [Byte0]: 50
7825 19:26:51.534230 [Byte1]: 50
7826 19:26:51.539002
7827 19:26:51.539079 Set Vref, RX VrefLevel [Byte0]: 51
7828 19:26:51.542404 [Byte1]: 51
7829 19:26:51.546412
7830 19:26:51.546493 Set Vref, RX VrefLevel [Byte0]: 52
7831 19:26:51.549700 [Byte1]: 52
7832 19:26:51.553811
7833 19:26:51.553892 Set Vref, RX VrefLevel [Byte0]: 53
7834 19:26:51.557104 [Byte1]: 53
7835 19:26:51.561770
7836 19:26:51.561867 Set Vref, RX VrefLevel [Byte0]: 54
7837 19:26:51.564891 [Byte1]: 54
7838 19:26:51.568962
7839 19:26:51.569042 Set Vref, RX VrefLevel [Byte0]: 55
7840 19:26:51.572437 [Byte1]: 55
7841 19:26:51.576530
7842 19:26:51.576610 Set Vref, RX VrefLevel [Byte0]: 56
7843 19:26:51.579849 [Byte1]: 56
7844 19:26:51.583894
7845 19:26:51.583972 Set Vref, RX VrefLevel [Byte0]: 57
7846 19:26:51.587325 [Byte1]: 57
7847 19:26:51.592085
7848 19:26:51.592162 Set Vref, RX VrefLevel [Byte0]: 58
7849 19:26:51.594858 [Byte1]: 58
7850 19:26:51.599721
7851 19:26:51.599798 Set Vref, RX VrefLevel [Byte0]: 59
7852 19:26:51.602370 [Byte1]: 59
7853 19:26:51.606883
7854 19:26:51.606960 Set Vref, RX VrefLevel [Byte0]: 60
7855 19:26:51.610124 [Byte1]: 60
7856 19:26:51.614735
7857 19:26:51.614814 Set Vref, RX VrefLevel [Byte0]: 61
7858 19:26:51.617838 [Byte1]: 61
7859 19:26:51.622126
7860 19:26:51.622239 Set Vref, RX VrefLevel [Byte0]: 62
7861 19:26:51.625370 [Byte1]: 62
7862 19:26:51.629969
7863 19:26:51.630071 Set Vref, RX VrefLevel [Byte0]: 63
7864 19:26:51.632671 [Byte1]: 63
7865 19:26:51.637254
7866 19:26:51.637354 Set Vref, RX VrefLevel [Byte0]: 64
7867 19:26:51.640534 [Byte1]: 64
7868 19:26:51.644649
7869 19:26:51.644751 Set Vref, RX VrefLevel [Byte0]: 65
7870 19:26:51.648032 [Byte1]: 65
7871 19:26:51.652080
7872 19:26:51.652155 Set Vref, RX VrefLevel [Byte0]: 66
7873 19:26:51.655503 [Byte1]: 66
7874 19:26:51.660037
7875 19:26:51.660111 Set Vref, RX VrefLevel [Byte0]: 67
7876 19:26:51.663457 [Byte1]: 67
7877 19:26:51.667327
7878 19:26:51.667403 Set Vref, RX VrefLevel [Byte0]: 68
7879 19:26:51.670561 [Byte1]: 68
7880 19:26:51.675240
7881 19:26:51.675317 Set Vref, RX VrefLevel [Byte0]: 69
7882 19:26:51.678654 [Byte1]: 69
7883 19:26:51.682775
7884 19:26:51.682876 Set Vref, RX VrefLevel [Byte0]: 70
7885 19:26:51.686251 [Byte1]: 70
7886 19:26:51.690257
7887 19:26:51.690365 Set Vref, RX VrefLevel [Byte0]: 71
7888 19:26:51.693700 [Byte1]: 71
7889 19:26:51.697777
7890 19:26:51.697874 Set Vref, RX VrefLevel [Byte0]: 72
7891 19:26:51.701177 [Byte1]: 72
7892 19:26:51.705244
7893 19:26:51.705315 Set Vref, RX VrefLevel [Byte0]: 73
7894 19:26:51.708637 [Byte1]: 73
7895 19:26:51.713186
7896 19:26:51.713285 Set Vref, RX VrefLevel [Byte0]: 74
7897 19:26:51.716437 [Byte1]: 74
7898 19:26:51.720464
7899 19:26:51.720564 Final RX Vref Byte 0 = 58 to rank0
7900 19:26:51.723733 Final RX Vref Byte 1 = 59 to rank0
7901 19:26:51.726892 Final RX Vref Byte 0 = 58 to rank1
7902 19:26:51.730569 Final RX Vref Byte 1 = 59 to rank1==
7903 19:26:51.733643 Dram Type= 6, Freq= 0, CH_0, rank 0
7904 19:26:51.740272 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7905 19:26:51.740374 ==
7906 19:26:51.740465 DQS Delay:
7907 19:26:51.743562 DQS0 = 0, DQS1 = 0
7908 19:26:51.743660 DQM Delay:
7909 19:26:51.743795 DQM0 = 134, DQM1 = 127
7910 19:26:51.746989 DQ Delay:
7911 19:26:51.750389 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =134
7912 19:26:51.753699 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =140
7913 19:26:51.757114 DQ8 =116, DQ9 =118, DQ10 =128, DQ11 =120
7914 19:26:51.760447 DQ12 =134, DQ13 =134, DQ14 =138, DQ15 =134
7915 19:26:51.760526
7916 19:26:51.760626
7917 19:26:51.760725
7918 19:26:51.763758 [DramC_TX_OE_Calibration] TA2
7919 19:26:51.767019 Original DQ_B0 (3 6) =30, OEN = 27
7920 19:26:51.770116 Original DQ_B1 (3 6) =30, OEN = 27
7921 19:26:51.773745 24, 0x0, End_B0=24 End_B1=24
7922 19:26:51.773823 25, 0x0, End_B0=25 End_B1=25
7923 19:26:51.776528 26, 0x0, End_B0=26 End_B1=26
7924 19:26:51.779961 27, 0x0, End_B0=27 End_B1=27
7925 19:26:51.783592 28, 0x0, End_B0=28 End_B1=28
7926 19:26:51.786803 29, 0x0, End_B0=29 End_B1=29
7927 19:26:51.786880 30, 0x0, End_B0=30 End_B1=30
7928 19:26:51.790161 31, 0x4141, End_B0=30 End_B1=30
7929 19:26:51.793213 Byte0 end_step=30 best_step=27
7930 19:26:51.797043 Byte1 end_step=30 best_step=27
7931 19:26:51.800183 Byte0 TX OE(2T, 0.5T) = (3, 3)
7932 19:26:51.803243 Byte1 TX OE(2T, 0.5T) = (3, 3)
7933 19:26:51.803348
7934 19:26:51.803441
7935 19:26:51.809994 [DQSOSCAuto] RK0, (LSB)MR18= 0x2722, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
7936 19:26:51.813521 CH0 RK0: MR19=303, MR18=2722
7937 19:26:51.820215 CH0_RK0: MR19=0x303, MR18=0x2722, DQSOSC=390, MR23=63, INC=24, DEC=16
7938 19:26:51.820318
7939 19:26:51.823295 ----->DramcWriteLeveling(PI) begin...
7940 19:26:51.823406 ==
7941 19:26:51.826263 Dram Type= 6, Freq= 0, CH_0, rank 1
7942 19:26:51.829577 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7943 19:26:51.829652 ==
7944 19:26:51.832906 Write leveling (Byte 0): 37 => 37
7945 19:26:51.836726 Write leveling (Byte 1): 27 => 27
7946 19:26:51.839718 DramcWriteLeveling(PI) end<-----
7947 19:26:51.839819
7948 19:26:51.839909 ==
7949 19:26:51.842831 Dram Type= 6, Freq= 0, CH_0, rank 1
7950 19:26:51.846566 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7951 19:26:51.846646 ==
7952 19:26:51.849822 [Gating] SW mode calibration
7953 19:26:51.856615 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7954 19:26:51.862608 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7955 19:26:51.865949 1 4 0 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
7956 19:26:51.873282 1 4 4 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7957 19:26:51.876084 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7958 19:26:51.879557 1 4 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 1)
7959 19:26:51.886115 1 4 16 | B1->B0 | 3030 3636 | 1 0 | (1 1) (1 1)
7960 19:26:51.889455 1 4 20 | B1->B0 | 3434 3534 | 1 1 | (1 1) (0 0)
7961 19:26:51.892753 1 4 24 | B1->B0 | 3434 3737 | 1 0 | (1 1) (1 1)
7962 19:26:51.899428 1 4 28 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7963 19:26:51.902664 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7964 19:26:51.905820 1 5 4 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7965 19:26:51.909580 1 5 8 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7966 19:26:51.916010 1 5 12 | B1->B0 | 3434 3131 | 1 0 | (1 0) (1 0)
7967 19:26:51.919349 1 5 16 | B1->B0 | 2f2f 2626 | 0 0 | (0 0) (0 0)
7968 19:26:51.922766 1 5 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7969 19:26:51.929343 1 5 24 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
7970 19:26:51.932465 1 5 28 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
7971 19:26:51.935692 1 6 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7972 19:26:51.942704 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7973 19:26:51.946053 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7974 19:26:51.949367 1 6 12 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
7975 19:26:51.956133 1 6 16 | B1->B0 | 3838 4545 | 1 0 | (0 0) (0 0)
7976 19:26:51.959374 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7977 19:26:51.962739 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7978 19:26:51.969492 1 6 28 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7979 19:26:51.972261 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7980 19:26:51.975610 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7981 19:26:51.982402 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7982 19:26:51.985817 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7983 19:26:51.989118 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7984 19:26:51.995797 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7985 19:26:51.999058 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7986 19:26:52.002404 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7987 19:26:52.009021 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7988 19:26:52.012611 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7989 19:26:52.015333 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7990 19:26:52.021978 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7991 19:26:52.025236 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7992 19:26:52.028709 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7993 19:26:52.035105 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7994 19:26:52.038439 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7995 19:26:52.042151 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7996 19:26:52.048410 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7997 19:26:52.051775 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7998 19:26:52.055189 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7999 19:26:52.061745 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8000 19:26:52.061818 Total UI for P1: 0, mck2ui 16
8001 19:26:52.068584 best dqsien dly found for B0: ( 1, 9, 12)
8002 19:26:52.071356 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8003 19:26:52.075123 Total UI for P1: 0, mck2ui 16
8004 19:26:52.078578 best dqsien dly found for B1: ( 1, 9, 14)
8005 19:26:52.081336 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8006 19:26:52.084804 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8007 19:26:52.084907
8008 19:26:52.088088 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8009 19:26:52.091485 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8010 19:26:52.094813 [Gating] SW calibration Done
8011 19:26:52.094892 ==
8012 19:26:52.098211 Dram Type= 6, Freq= 0, CH_0, rank 1
8013 19:26:52.101581 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8014 19:26:52.104831 ==
8015 19:26:52.104906 RX Vref Scan: 0
8016 19:26:52.104968
8017 19:26:52.108208 RX Vref 0 -> 0, step: 1
8018 19:26:52.108280
8019 19:26:52.108341 RX Delay 0 -> 252, step: 8
8020 19:26:52.114959 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8021 19:26:52.118464 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8022 19:26:52.121190 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8023 19:26:52.124483 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8024 19:26:52.127744 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8025 19:26:52.134532 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8026 19:26:52.137904 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8027 19:26:52.141281 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8028 19:26:52.144636 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8029 19:26:52.148065 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8030 19:26:52.154736 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8031 19:26:52.158104 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8032 19:26:52.161456 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8033 19:26:52.164869 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8034 19:26:52.168065 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8035 19:26:52.174646 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8036 19:26:52.174724 ==
8037 19:26:52.178325 Dram Type= 6, Freq= 0, CH_0, rank 1
8038 19:26:52.181403 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8039 19:26:52.181501 ==
8040 19:26:52.181590 DQS Delay:
8041 19:26:52.184903 DQS0 = 0, DQS1 = 0
8042 19:26:52.184984 DQM Delay:
8043 19:26:52.188253 DQM0 = 136, DQM1 = 128
8044 19:26:52.188333 DQ Delay:
8045 19:26:52.191585 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8046 19:26:52.194719 DQ4 =139, DQ5 =127, DQ6 =139, DQ7 =143
8047 19:26:52.197895 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8048 19:26:52.201272 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8049 19:26:52.204431
8050 19:26:52.204537
8051 19:26:52.204619 ==
8052 19:26:52.207771 Dram Type= 6, Freq= 0, CH_0, rank 1
8053 19:26:52.211493 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8054 19:26:52.211589 ==
8055 19:26:52.211667
8056 19:26:52.211726
8057 19:26:52.214283 TX Vref Scan disable
8058 19:26:52.214400 == TX Byte 0 ==
8059 19:26:52.221113 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
8060 19:26:52.224628 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8061 19:26:52.224739 == TX Byte 1 ==
8062 19:26:52.231099 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8063 19:26:52.234565 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8064 19:26:52.234670 ==
8065 19:26:52.237975 Dram Type= 6, Freq= 0, CH_0, rank 1
8066 19:26:52.241463 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8067 19:26:52.241560 ==
8068 19:26:52.255552
8069 19:26:52.259371 TX Vref early break, caculate TX vref
8070 19:26:52.262170 TX Vref=16, minBit 3, minWin=23, winSum=390
8071 19:26:52.265575 TX Vref=18, minBit 1, minWin=23, winSum=396
8072 19:26:52.269017 TX Vref=20, minBit 3, minWin=23, winSum=403
8073 19:26:52.272420 TX Vref=22, minBit 3, minWin=24, winSum=411
8074 19:26:52.275576 TX Vref=24, minBit 3, minWin=24, winSum=417
8075 19:26:52.282184 TX Vref=26, minBit 1, minWin=24, winSum=423
8076 19:26:52.285708 TX Vref=28, minBit 3, minWin=25, winSum=421
8077 19:26:52.288994 TX Vref=30, minBit 0, minWin=25, winSum=414
8078 19:26:52.292100 TX Vref=32, minBit 0, minWin=25, winSum=409
8079 19:26:52.295521 TX Vref=34, minBit 0, minWin=24, winSum=400
8080 19:26:52.302277 [TxChooseVref] Worse bit 3, Min win 25, Win sum 421, Final Vref 28
8081 19:26:52.302395
8082 19:26:52.305626 Final TX Range 0 Vref 28
8083 19:26:52.305696
8084 19:26:52.305756 ==
8085 19:26:52.308965 Dram Type= 6, Freq= 0, CH_0, rank 1
8086 19:26:52.312253 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8087 19:26:52.312335 ==
8088 19:26:52.312400
8089 19:26:52.312460
8090 19:26:52.315592 TX Vref Scan disable
8091 19:26:52.321935 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8092 19:26:52.322038 == TX Byte 0 ==
8093 19:26:52.325117 u2DelayCellOfst[0]=10 cells (3 PI)
8094 19:26:52.328544 u2DelayCellOfst[1]=13 cells (4 PI)
8095 19:26:52.331895 u2DelayCellOfst[2]=10 cells (3 PI)
8096 19:26:52.335682 u2DelayCellOfst[3]=10 cells (3 PI)
8097 19:26:52.338981 u2DelayCellOfst[4]=10 cells (3 PI)
8098 19:26:52.341915 u2DelayCellOfst[5]=0 cells (0 PI)
8099 19:26:52.345567 u2DelayCellOfst[6]=13 cells (4 PI)
8100 19:26:52.348563 u2DelayCellOfst[7]=16 cells (5 PI)
8101 19:26:52.351862 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8102 19:26:52.355332 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8103 19:26:52.358612 == TX Byte 1 ==
8104 19:26:52.361807 u2DelayCellOfst[8]=0 cells (0 PI)
8105 19:26:52.361888 u2DelayCellOfst[9]=0 cells (0 PI)
8106 19:26:52.365046 u2DelayCellOfst[10]=6 cells (2 PI)
8107 19:26:52.368318 u2DelayCellOfst[11]=3 cells (1 PI)
8108 19:26:52.371775 u2DelayCellOfst[12]=10 cells (3 PI)
8109 19:26:52.375371 u2DelayCellOfst[13]=10 cells (3 PI)
8110 19:26:52.378464 u2DelayCellOfst[14]=16 cells (5 PI)
8111 19:26:52.381591 u2DelayCellOfst[15]=10 cells (3 PI)
8112 19:26:52.384950 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8113 19:26:52.391791 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8114 19:26:52.391877 DramC Write-DBI on
8115 19:26:52.391940 ==
8116 19:26:52.395104 Dram Type= 6, Freq= 0, CH_0, rank 1
8117 19:26:52.398530 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8118 19:26:52.401774 ==
8119 19:26:52.401907
8120 19:26:52.402054
8121 19:26:52.402149 TX Vref Scan disable
8122 19:26:52.405282 == TX Byte 0 ==
8123 19:26:52.408696 Update DQM dly =738 (2 ,6, 34) DQM OEN =(3 ,3)
8124 19:26:52.412167 == TX Byte 1 ==
8125 19:26:52.415650 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8126 19:26:52.418391 DramC Write-DBI off
8127 19:26:52.418487
8128 19:26:52.418582 [DATLAT]
8129 19:26:52.418669 Freq=1600, CH0 RK1
8130 19:26:52.418754
8131 19:26:52.421761 DATLAT Default: 0xf
8132 19:26:52.425124 0, 0xFFFF, sum = 0
8133 19:26:52.425235 1, 0xFFFF, sum = 0
8134 19:26:52.428522 2, 0xFFFF, sum = 0
8135 19:26:52.428621 3, 0xFFFF, sum = 0
8136 19:26:52.431874 4, 0xFFFF, sum = 0
8137 19:26:52.431973 5, 0xFFFF, sum = 0
8138 19:26:52.435214 6, 0xFFFF, sum = 0
8139 19:26:52.435286 7, 0xFFFF, sum = 0
8140 19:26:52.438502 8, 0xFFFF, sum = 0
8141 19:26:52.438587 9, 0xFFFF, sum = 0
8142 19:26:52.441853 10, 0xFFFF, sum = 0
8143 19:26:52.441951 11, 0xFFFF, sum = 0
8144 19:26:52.445262 12, 0xFFFF, sum = 0
8145 19:26:52.445428 13, 0xFFFF, sum = 0
8146 19:26:52.448489 14, 0x0, sum = 1
8147 19:26:52.448593 15, 0x0, sum = 2
8148 19:26:52.451707 16, 0x0, sum = 3
8149 19:26:52.451803 17, 0x0, sum = 4
8150 19:26:52.454650 best_step = 15
8151 19:26:52.454730
8152 19:26:52.454791 ==
8153 19:26:52.458238 Dram Type= 6, Freq= 0, CH_0, rank 1
8154 19:26:52.461225 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8155 19:26:52.461299 ==
8156 19:26:52.464476 RX Vref Scan: 0
8157 19:26:52.464575
8158 19:26:52.464664 RX Vref 0 -> 0, step: 1
8159 19:26:52.464790
8160 19:26:52.467853 RX Delay 19 -> 252, step: 4
8161 19:26:52.474432 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8162 19:26:52.477691 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8163 19:26:52.480991 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8164 19:26:52.484604 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8165 19:26:52.488025 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8166 19:26:52.494760 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8167 19:26:52.497798 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8168 19:26:52.501349 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8169 19:26:52.504782 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8170 19:26:52.507877 iDelay=191, Bit 9, Center 118 (67 ~ 170) 104
8171 19:26:52.511018 iDelay=191, Bit 10, Center 130 (79 ~ 182) 104
8172 19:26:52.518188 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8173 19:26:52.521442 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8174 19:26:52.524816 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8175 19:26:52.527607 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8176 19:26:52.534279 iDelay=191, Bit 15, Center 134 (83 ~ 186) 104
8177 19:26:52.534391 ==
8178 19:26:52.537664 Dram Type= 6, Freq= 0, CH_0, rank 1
8179 19:26:52.541079 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8180 19:26:52.541159 ==
8181 19:26:52.541227 DQS Delay:
8182 19:26:52.544421 DQS0 = 0, DQS1 = 0
8183 19:26:52.544491 DQM Delay:
8184 19:26:52.547850 DQM0 = 134, DQM1 = 127
8185 19:26:52.547917 DQ Delay:
8186 19:26:52.550688 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =134
8187 19:26:52.554072 DQ4 =136, DQ5 =124, DQ6 =140, DQ7 =140
8188 19:26:52.557466 DQ8 =118, DQ9 =118, DQ10 =130, DQ11 =118
8189 19:26:52.560779 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =134
8190 19:26:52.560879
8191 19:26:52.564055
8192 19:26:52.564156
8193 19:26:52.564249 [DramC_TX_OE_Calibration] TA2
8194 19:26:52.567296 Original DQ_B0 (3 6) =30, OEN = 27
8195 19:26:52.570721 Original DQ_B1 (3 6) =30, OEN = 27
8196 19:26:52.574236 24, 0x0, End_B0=24 End_B1=24
8197 19:26:52.577526 25, 0x0, End_B0=25 End_B1=25
8198 19:26:52.580810 26, 0x0, End_B0=26 End_B1=26
8199 19:26:52.580914 27, 0x0, End_B0=27 End_B1=27
8200 19:26:52.583896 28, 0x0, End_B0=28 End_B1=28
8201 19:26:52.587553 29, 0x0, End_B0=29 End_B1=29
8202 19:26:52.591027 30, 0x0, End_B0=30 End_B1=30
8203 19:26:52.593921 31, 0x4545, End_B0=30 End_B1=30
8204 19:26:52.594030 Byte0 end_step=30 best_step=27
8205 19:26:52.597693 Byte1 end_step=30 best_step=27
8206 19:26:52.600888 Byte0 TX OE(2T, 0.5T) = (3, 3)
8207 19:26:52.603963 Byte1 TX OE(2T, 0.5T) = (3, 3)
8208 19:26:52.604040
8209 19:26:52.604117
8210 19:26:52.610605 [DQSOSCAuto] RK1, (LSB)MR18= 0x230a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
8211 19:26:52.613857 CH0 RK1: MR19=303, MR18=230A
8212 19:26:52.620406 CH0_RK1: MR19=0x303, MR18=0x230A, DQSOSC=392, MR23=63, INC=24, DEC=16
8213 19:26:52.624112 [RxdqsGatingPostProcess] freq 1600
8214 19:26:52.630574 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8215 19:26:52.633936 best DQS0 dly(2T, 0.5T) = (1, 1)
8216 19:26:52.634060 best DQS1 dly(2T, 0.5T) = (1, 1)
8217 19:26:52.637283 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8218 19:26:52.640677 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8219 19:26:52.643980 best DQS0 dly(2T, 0.5T) = (1, 1)
8220 19:26:52.647410 best DQS1 dly(2T, 0.5T) = (1, 1)
8221 19:26:52.650847 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8222 19:26:52.654174 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8223 19:26:52.657446 Pre-setting of DQS Precalculation
8224 19:26:52.660289 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8225 19:26:52.663787 ==
8226 19:26:52.667289 Dram Type= 6, Freq= 0, CH_1, rank 0
8227 19:26:52.670685 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8228 19:26:52.670764 ==
8229 19:26:52.673400 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8230 19:26:52.680220 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8231 19:26:52.683632 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8232 19:26:52.690433 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8233 19:26:52.698739 [CA 0] Center 41 (11~71) winsize 61
8234 19:26:52.701931 [CA 1] Center 42 (12~72) winsize 61
8235 19:26:52.704920 [CA 2] Center 38 (9~68) winsize 60
8236 19:26:52.708444 [CA 3] Center 37 (9~66) winsize 58
8237 19:26:52.711711 [CA 4] Center 37 (8~67) winsize 60
8238 19:26:52.715047 [CA 5] Center 36 (7~66) winsize 60
8239 19:26:52.715129
8240 19:26:52.718498 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8241 19:26:52.718582
8242 19:26:52.721923 [CATrainingPosCal] consider 1 rank data
8243 19:26:52.724727 u2DelayCellTimex100 = 290/100 ps
8244 19:26:52.728110 CA0 delay=41 (11~71),Diff = 5 PI (16 cell)
8245 19:26:52.734859 CA1 delay=42 (12~72),Diff = 6 PI (20 cell)
8246 19:26:52.738036 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
8247 19:26:52.741538 CA3 delay=37 (9~66),Diff = 1 PI (3 cell)
8248 19:26:52.744580 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8249 19:26:52.747839 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8250 19:26:52.747946
8251 19:26:52.751140 CA PerBit enable=1, Macro0, CA PI delay=36
8252 19:26:52.751259
8253 19:26:52.754670 [CBTSetCACLKResult] CA Dly = 36
8254 19:26:52.757786 CS Dly: 11 (0~42)
8255 19:26:52.761432 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8256 19:26:52.765216 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8257 19:26:52.765299 ==
8258 19:26:52.768147 Dram Type= 6, Freq= 0, CH_1, rank 1
8259 19:26:52.771342 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8260 19:26:52.774649 ==
8261 19:26:52.777899 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8262 19:26:52.781293 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8263 19:26:52.788092 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8264 19:26:52.794685 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8265 19:26:52.801391 [CA 0] Center 42 (12~72) winsize 61
8266 19:26:52.804797 [CA 1] Center 42 (13~72) winsize 60
8267 19:26:52.808061 [CA 2] Center 39 (10~69) winsize 60
8268 19:26:52.811258 [CA 3] Center 38 (9~68) winsize 60
8269 19:26:52.814960 [CA 4] Center 39 (10~69) winsize 60
8270 19:26:52.818161 [CA 5] Center 38 (9~68) winsize 60
8271 19:26:52.818266
8272 19:26:52.821438 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8273 19:26:52.821540
8274 19:26:52.824764 [CATrainingPosCal] consider 2 rank data
8275 19:26:52.828171 u2DelayCellTimex100 = 290/100 ps
8276 19:26:52.834836 CA0 delay=41 (12~71),Diff = 4 PI (13 cell)
8277 19:26:52.838295 CA1 delay=42 (13~72),Diff = 5 PI (16 cell)
8278 19:26:52.841717 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8279 19:26:52.845118 CA3 delay=37 (9~66),Diff = 0 PI (0 cell)
8280 19:26:52.847830 CA4 delay=38 (10~67),Diff = 1 PI (3 cell)
8281 19:26:52.851641 CA5 delay=37 (9~66),Diff = 0 PI (0 cell)
8282 19:26:52.851716
8283 19:26:52.855061 CA PerBit enable=1, Macro0, CA PI delay=37
8284 19:26:52.855139
8285 19:26:52.857756 [CBTSetCACLKResult] CA Dly = 37
8286 19:26:52.861026 CS Dly: 12 (0~44)
8287 19:26:52.865064 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8288 19:26:52.867710 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8289 19:26:52.867795
8290 19:26:52.871173 ----->DramcWriteLeveling(PI) begin...
8291 19:26:52.871293 ==
8292 19:26:52.874831 Dram Type= 6, Freq= 0, CH_1, rank 0
8293 19:26:52.881174 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8294 19:26:52.881258 ==
8295 19:26:52.884429 Write leveling (Byte 0): 26 => 26
8296 19:26:52.887779 Write leveling (Byte 1): 28 => 28
8297 19:26:52.887863 DramcWriteLeveling(PI) end<-----
8298 19:26:52.887938
8299 19:26:52.891184 ==
8300 19:26:52.894310 Dram Type= 6, Freq= 0, CH_1, rank 0
8301 19:26:52.897886 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8302 19:26:52.897973 ==
8303 19:26:52.901237 [Gating] SW mode calibration
8304 19:26:52.907871 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8305 19:26:52.911293 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8306 19:26:52.917805 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8307 19:26:52.921133 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8308 19:26:52.924365 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 0)
8309 19:26:52.931082 1 4 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
8310 19:26:52.934401 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8311 19:26:52.937773 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8312 19:26:52.944367 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8313 19:26:52.947808 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8314 19:26:52.951254 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8315 19:26:52.958049 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8316 19:26:52.960802 1 5 8 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 1)
8317 19:26:52.964243 1 5 12 | B1->B0 | 2525 2323 | 0 0 | (1 0) (1 0)
8318 19:26:52.970860 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8319 19:26:52.974279 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8320 19:26:52.977714 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8321 19:26:52.984379 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8322 19:26:52.987674 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8323 19:26:52.991044 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8324 19:26:52.994561 1 6 8 | B1->B0 | 2b2b 4242 | 1 0 | (0 0) (0 0)
8325 19:26:53.001065 1 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8326 19:26:53.004006 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8327 19:26:53.007308 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8328 19:26:53.014444 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8329 19:26:53.017356 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8330 19:26:53.020741 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8331 19:26:53.027220 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8332 19:26:53.030520 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8333 19:26:53.034294 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8334 19:26:53.040923 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8335 19:26:53.044029 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8336 19:26:53.047954 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8337 19:26:53.054393 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8338 19:26:53.057726 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8339 19:26:53.061088 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8340 19:26:53.067799 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8341 19:26:53.070563 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8342 19:26:53.073861 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8343 19:26:53.080674 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8344 19:26:53.084068 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8345 19:26:53.087463 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8346 19:26:53.094031 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8347 19:26:53.097455 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8348 19:26:53.100798 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8349 19:26:53.106776 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8350 19:26:53.110229 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8351 19:26:53.114034 Total UI for P1: 0, mck2ui 16
8352 19:26:53.116798 best dqsien dly found for B0: ( 1, 9, 10)
8353 19:26:53.120258 Total UI for P1: 0, mck2ui 16
8354 19:26:53.123683 best dqsien dly found for B1: ( 1, 9, 12)
8355 19:26:53.127026 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8356 19:26:53.130348 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8357 19:26:53.130453
8358 19:26:53.133504 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8359 19:26:53.136875 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8360 19:26:53.140240 [Gating] SW calibration Done
8361 19:26:53.140347 ==
8362 19:26:53.143494 Dram Type= 6, Freq= 0, CH_1, rank 0
8363 19:26:53.147490 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8364 19:26:53.147600 ==
8365 19:26:53.150634 RX Vref Scan: 0
8366 19:26:53.150720
8367 19:26:53.153705 RX Vref 0 -> 0, step: 1
8368 19:26:53.153805
8369 19:26:53.153903 RX Delay 0 -> 252, step: 8
8370 19:26:53.160199 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8371 19:26:53.163531 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8372 19:26:53.166945 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8373 19:26:53.170405 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8374 19:26:53.173490 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8375 19:26:53.180006 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8376 19:26:53.183370 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8377 19:26:53.186880 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8378 19:26:53.190276 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8379 19:26:53.194037 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8380 19:26:53.200690 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8381 19:26:53.203450 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8382 19:26:53.206883 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8383 19:26:53.210170 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8384 19:26:53.213456 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8385 19:26:53.220082 iDelay=200, Bit 15, Center 143 (96 ~ 191) 96
8386 19:26:53.220168 ==
8387 19:26:53.223489 Dram Type= 6, Freq= 0, CH_1, rank 0
8388 19:26:53.226871 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8389 19:26:53.226951 ==
8390 19:26:53.227018 DQS Delay:
8391 19:26:53.230195 DQS0 = 0, DQS1 = 0
8392 19:26:53.230265 DQM Delay:
8393 19:26:53.233641 DQM0 = 136, DQM1 = 133
8394 19:26:53.233710 DQ Delay:
8395 19:26:53.236776 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8396 19:26:53.240131 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8397 19:26:53.243435 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8398 19:26:53.246675 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =143
8399 19:26:53.246760
8400 19:26:53.246825
8401 19:26:53.250012 ==
8402 19:26:53.250093 Dram Type= 6, Freq= 0, CH_1, rank 0
8403 19:26:53.256768 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8404 19:26:53.256885 ==
8405 19:26:53.256979
8406 19:26:53.257069
8407 19:26:53.260134 TX Vref Scan disable
8408 19:26:53.260221 == TX Byte 0 ==
8409 19:26:53.263507 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8410 19:26:53.270107 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8411 19:26:53.270210 == TX Byte 1 ==
8412 19:26:53.273441 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8413 19:26:53.280258 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8414 19:26:53.280335 ==
8415 19:26:53.283624 Dram Type= 6, Freq= 0, CH_1, rank 0
8416 19:26:53.286789 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8417 19:26:53.286894 ==
8418 19:26:53.299602
8419 19:26:53.302609 TX Vref early break, caculate TX vref
8420 19:26:53.306103 TX Vref=16, minBit 1, minWin=22, winSum=374
8421 19:26:53.309123 TX Vref=18, minBit 1, minWin=23, winSum=384
8422 19:26:53.312585 TX Vref=20, minBit 0, minWin=24, winSum=401
8423 19:26:53.316097 TX Vref=22, minBit 0, minWin=24, winSum=406
8424 19:26:53.319275 TX Vref=24, minBit 0, minWin=25, winSum=416
8425 19:26:53.325876 TX Vref=26, minBit 0, minWin=25, winSum=424
8426 19:26:53.329232 TX Vref=28, minBit 0, minWin=25, winSum=421
8427 19:26:53.332738 TX Vref=30, minBit 0, minWin=25, winSum=417
8428 19:26:53.336233 TX Vref=32, minBit 6, minWin=24, winSum=413
8429 19:26:53.339027 TX Vref=34, minBit 1, minWin=24, winSum=401
8430 19:26:53.346186 [TxChooseVref] Worse bit 0, Min win 25, Win sum 424, Final Vref 26
8431 19:26:53.346289
8432 19:26:53.349456 Final TX Range 0 Vref 26
8433 19:26:53.349554
8434 19:26:53.349651 ==
8435 19:26:53.352764 Dram Type= 6, Freq= 0, CH_1, rank 0
8436 19:26:53.355549 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8437 19:26:53.355624 ==
8438 19:26:53.355686
8439 19:26:53.355779
8440 19:26:53.358891 TX Vref Scan disable
8441 19:26:53.365738 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8442 19:26:53.365847 == TX Byte 0 ==
8443 19:26:53.369104 u2DelayCellOfst[0]=16 cells (5 PI)
8444 19:26:53.372358 u2DelayCellOfst[1]=10 cells (3 PI)
8445 19:26:53.375821 u2DelayCellOfst[2]=0 cells (0 PI)
8446 19:26:53.379125 u2DelayCellOfst[3]=3 cells (1 PI)
8447 19:26:53.382592 u2DelayCellOfst[4]=6 cells (2 PI)
8448 19:26:53.385990 u2DelayCellOfst[5]=16 cells (5 PI)
8449 19:26:53.388672 u2DelayCellOfst[6]=16 cells (5 PI)
8450 19:26:53.388775 u2DelayCellOfst[7]=3 cells (1 PI)
8451 19:26:53.395888 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8452 19:26:53.399081 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8453 19:26:53.399184 == TX Byte 1 ==
8454 19:26:53.402309 u2DelayCellOfst[8]=0 cells (0 PI)
8455 19:26:53.405646 u2DelayCellOfst[9]=3 cells (1 PI)
8456 19:26:53.408930 u2DelayCellOfst[10]=13 cells (4 PI)
8457 19:26:53.412318 u2DelayCellOfst[11]=3 cells (1 PI)
8458 19:26:53.415664 u2DelayCellOfst[12]=13 cells (4 PI)
8459 19:26:53.418837 u2DelayCellOfst[13]=16 cells (5 PI)
8460 19:26:53.421916 u2DelayCellOfst[14]=16 cells (5 PI)
8461 19:26:53.425539 u2DelayCellOfst[15]=16 cells (5 PI)
8462 19:26:53.428525 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8463 19:26:53.435151 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8464 19:26:53.435262 DramC Write-DBI on
8465 19:26:53.435354 ==
8466 19:26:53.438666 Dram Type= 6, Freq= 0, CH_1, rank 0
8467 19:26:53.442009 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8468 19:26:53.442085 ==
8469 19:26:53.445242
8470 19:26:53.445341
8471 19:26:53.445430 TX Vref Scan disable
8472 19:26:53.448527 == TX Byte 0 ==
8473 19:26:53.451828 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8474 19:26:53.455476 == TX Byte 1 ==
8475 19:26:53.459092 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8476 19:26:53.459170 DramC Write-DBI off
8477 19:26:53.459246
8478 19:26:53.462289 [DATLAT]
8479 19:26:53.462402 Freq=1600, CH1 RK0
8480 19:26:53.462496
8481 19:26:53.465538 DATLAT Default: 0xf
8482 19:26:53.465626 0, 0xFFFF, sum = 0
8483 19:26:53.468930 1, 0xFFFF, sum = 0
8484 19:26:53.469007 2, 0xFFFF, sum = 0
8485 19:26:53.471966 3, 0xFFFF, sum = 0
8486 19:26:53.472047 4, 0xFFFF, sum = 0
8487 19:26:53.475285 5, 0xFFFF, sum = 0
8488 19:26:53.475393 6, 0xFFFF, sum = 0
8489 19:26:53.478537 7, 0xFFFF, sum = 0
8490 19:26:53.478615 8, 0xFFFF, sum = 0
8491 19:26:53.482032 9, 0xFFFF, sum = 0
8492 19:26:53.485345 10, 0xFFFF, sum = 0
8493 19:26:53.485449 11, 0xFFFF, sum = 0
8494 19:26:53.488872 12, 0xFFFF, sum = 0
8495 19:26:53.488949 13, 0xFFFF, sum = 0
8496 19:26:53.492251 14, 0x0, sum = 1
8497 19:26:53.492353 15, 0x0, sum = 2
8498 19:26:53.495702 16, 0x0, sum = 3
8499 19:26:53.495777 17, 0x0, sum = 4
8500 19:26:53.495856 best_step = 15
8501 19:26:53.498405
8502 19:26:53.498487 ==
8503 19:26:53.502317 Dram Type= 6, Freq= 0, CH_1, rank 0
8504 19:26:53.505707 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8505 19:26:53.505816 ==
8506 19:26:53.505908 RX Vref Scan: 1
8507 19:26:53.506004
8508 19:26:53.509132 Set Vref Range= 24 -> 127
8509 19:26:53.509206
8510 19:26:53.511697 RX Vref 24 -> 127, step: 1
8511 19:26:53.511797
8512 19:26:53.515182 RX Delay 27 -> 252, step: 4
8513 19:26:53.515264
8514 19:26:53.518524 Set Vref, RX VrefLevel [Byte0]: 24
8515 19:26:53.521904 [Byte1]: 24
8516 19:26:53.521986
8517 19:26:53.525277 Set Vref, RX VrefLevel [Byte0]: 25
8518 19:26:53.528606 [Byte1]: 25
8519 19:26:53.528689
8520 19:26:53.531839 Set Vref, RX VrefLevel [Byte0]: 26
8521 19:26:53.534940 [Byte1]: 26
8522 19:26:53.538733
8523 19:26:53.538817 Set Vref, RX VrefLevel [Byte0]: 27
8524 19:26:53.542065 [Byte1]: 27
8525 19:26:53.546131
8526 19:26:53.546208 Set Vref, RX VrefLevel [Byte0]: 28
8527 19:26:53.549413 [Byte1]: 28
8528 19:26:53.553892
8529 19:26:53.553995 Set Vref, RX VrefLevel [Byte0]: 29
8530 19:26:53.557305 [Byte1]: 29
8531 19:26:53.561327
8532 19:26:53.561426 Set Vref, RX VrefLevel [Byte0]: 30
8533 19:26:53.564516 [Byte1]: 30
8534 19:26:53.568749
8535 19:26:53.568858 Set Vref, RX VrefLevel [Byte0]: 31
8536 19:26:53.571873 [Byte1]: 31
8537 19:26:53.576187
8538 19:26:53.576287 Set Vref, RX VrefLevel [Byte0]: 32
8539 19:26:53.580290 [Byte1]: 32
8540 19:26:53.583639
8541 19:26:53.583737 Set Vref, RX VrefLevel [Byte0]: 33
8542 19:26:53.587387 [Byte1]: 33
8543 19:26:53.591204
8544 19:26:53.591311 Set Vref, RX VrefLevel [Byte0]: 34
8545 19:26:53.594703 [Byte1]: 34
8546 19:26:53.599062
8547 19:26:53.599141 Set Vref, RX VrefLevel [Byte0]: 35
8548 19:26:53.602154 [Byte1]: 35
8549 19:26:53.606476
8550 19:26:53.606562 Set Vref, RX VrefLevel [Byte0]: 36
8551 19:26:53.609764 [Byte1]: 36
8552 19:26:53.613839
8553 19:26:53.613948 Set Vref, RX VrefLevel [Byte0]: 37
8554 19:26:53.617262 [Byte1]: 37
8555 19:26:53.621400
8556 19:26:53.621500 Set Vref, RX VrefLevel [Byte0]: 38
8557 19:26:53.624718 [Byte1]: 38
8558 19:26:53.629562
8559 19:26:53.629649 Set Vref, RX VrefLevel [Byte0]: 39
8560 19:26:53.632214 [Byte1]: 39
8561 19:26:53.636786
8562 19:26:53.636863 Set Vref, RX VrefLevel [Byte0]: 40
8563 19:26:53.640189 [Byte1]: 40
8564 19:26:53.643979
8565 19:26:53.644061 Set Vref, RX VrefLevel [Byte0]: 41
8566 19:26:53.647783 [Byte1]: 41
8567 19:26:53.651944
8568 19:26:53.652028 Set Vref, RX VrefLevel [Byte0]: 42
8569 19:26:53.655114 [Byte1]: 42
8570 19:26:53.659563
8571 19:26:53.659646 Set Vref, RX VrefLevel [Byte0]: 43
8572 19:26:53.662280 [Byte1]: 43
8573 19:26:53.666439
8574 19:26:53.666522 Set Vref, RX VrefLevel [Byte0]: 44
8575 19:26:53.669822 [Byte1]: 44
8576 19:26:53.674384
8577 19:26:53.674467 Set Vref, RX VrefLevel [Byte0]: 45
8578 19:26:53.677637 [Byte1]: 45
8579 19:26:53.681763
8580 19:26:53.681846 Set Vref, RX VrefLevel [Byte0]: 46
8581 19:26:53.685234 [Byte1]: 46
8582 19:26:53.689136
8583 19:26:53.689218 Set Vref, RX VrefLevel [Byte0]: 47
8584 19:26:53.692477 [Byte1]: 47
8585 19:26:53.696582
8586 19:26:53.696664 Set Vref, RX VrefLevel [Byte0]: 48
8587 19:26:53.699950 [Byte1]: 48
8588 19:26:53.704492
8589 19:26:53.704574 Set Vref, RX VrefLevel [Byte0]: 49
8590 19:26:53.707547 [Byte1]: 49
8591 19:26:53.711676
8592 19:26:53.711759 Set Vref, RX VrefLevel [Byte0]: 50
8593 19:26:53.715623 [Byte1]: 50
8594 19:26:53.719343
8595 19:26:53.719454 Set Vref, RX VrefLevel [Byte0]: 51
8596 19:26:53.723073 [Byte1]: 51
8597 19:26:53.727059
8598 19:26:53.727143 Set Vref, RX VrefLevel [Byte0]: 52
8599 19:26:53.730255 [Byte1]: 52
8600 19:26:53.734683
8601 19:26:53.734765 Set Vref, RX VrefLevel [Byte0]: 53
8602 19:26:53.737865 [Byte1]: 53
8603 19:26:53.741893
8604 19:26:53.741977 Set Vref, RX VrefLevel [Byte0]: 54
8605 19:26:53.745278 [Byte1]: 54
8606 19:26:53.749760
8607 19:26:53.749844 Set Vref, RX VrefLevel [Byte0]: 55
8608 19:26:53.753121 [Byte1]: 55
8609 19:26:53.756997
8610 19:26:53.757080 Set Vref, RX VrefLevel [Byte0]: 56
8611 19:26:53.760295 [Byte1]: 56
8612 19:26:53.764737
8613 19:26:53.764824 Set Vref, RX VrefLevel [Byte0]: 57
8614 19:26:53.768205 [Byte1]: 57
8615 19:26:53.772095
8616 19:26:53.772178 Set Vref, RX VrefLevel [Byte0]: 58
8617 19:26:53.775514 [Byte1]: 58
8618 19:26:53.780099
8619 19:26:53.780181 Set Vref, RX VrefLevel [Byte0]: 59
8620 19:26:53.782804 [Byte1]: 59
8621 19:26:53.787544
8622 19:26:53.787627 Set Vref, RX VrefLevel [Byte0]: 60
8623 19:26:53.790854 [Byte1]: 60
8624 19:26:53.794882
8625 19:26:53.794965 Set Vref, RX VrefLevel [Byte0]: 61
8626 19:26:53.798111 [Byte1]: 61
8627 19:26:53.802211
8628 19:26:53.802294 Set Vref, RX VrefLevel [Byte0]: 62
8629 19:26:53.805680 [Byte1]: 62
8630 19:26:53.809820
8631 19:26:53.809902 Set Vref, RX VrefLevel [Byte0]: 63
8632 19:26:53.813214 [Byte1]: 63
8633 19:26:53.817270
8634 19:26:53.817352 Set Vref, RX VrefLevel [Byte0]: 64
8635 19:26:53.820592 [Byte1]: 64
8636 19:26:53.825255
8637 19:26:53.825339 Set Vref, RX VrefLevel [Byte0]: 65
8638 19:26:53.827927 [Byte1]: 65
8639 19:26:53.832383
8640 19:26:53.832499 Set Vref, RX VrefLevel [Byte0]: 66
8641 19:26:53.835866 [Byte1]: 66
8642 19:26:53.839848
8643 19:26:53.839949 Set Vref, RX VrefLevel [Byte0]: 67
8644 19:26:53.843188 [Byte1]: 67
8645 19:26:53.847463
8646 19:26:53.847541 Set Vref, RX VrefLevel [Byte0]: 68
8647 19:26:53.851082 [Byte1]: 68
8648 19:26:53.855096
8649 19:26:53.855166 Set Vref, RX VrefLevel [Byte0]: 69
8650 19:26:53.858364 [Byte1]: 69
8651 19:26:53.862401
8652 19:26:53.862503 Set Vref, RX VrefLevel [Byte0]: 70
8653 19:26:53.865808 [Byte1]: 70
8654 19:26:53.870006
8655 19:26:53.870104 Set Vref, RX VrefLevel [Byte0]: 71
8656 19:26:53.873191 [Byte1]: 71
8657 19:26:53.877639
8658 19:26:53.877743 Set Vref, RX VrefLevel [Byte0]: 72
8659 19:26:53.881203 [Byte1]: 72
8660 19:26:53.885296
8661 19:26:53.885396 Set Vref, RX VrefLevel [Byte0]: 73
8662 19:26:53.888653 [Byte1]: 73
8663 19:26:53.892526
8664 19:26:53.892626 Set Vref, RX VrefLevel [Byte0]: 74
8665 19:26:53.896063 [Byte1]: 74
8666 19:26:53.900220
8667 19:26:53.900295 Set Vref, RX VrefLevel [Byte0]: 75
8668 19:26:53.903666 [Byte1]: 75
8669 19:26:53.907564
8670 19:26:53.907638 Set Vref, RX VrefLevel [Byte0]: 76
8671 19:26:53.910875 [Byte1]: 76
8672 19:26:53.915652
8673 19:26:53.915735 Set Vref, RX VrefLevel [Byte0]: 77
8674 19:26:53.918437 [Byte1]: 77
8675 19:26:53.923337
8676 19:26:53.923423 Final RX Vref Byte 0 = 59 to rank0
8677 19:26:53.926431 Final RX Vref Byte 1 = 55 to rank0
8678 19:26:53.929244 Final RX Vref Byte 0 = 59 to rank1
8679 19:26:53.932744 Final RX Vref Byte 1 = 55 to rank1==
8680 19:26:53.936020 Dram Type= 6, Freq= 0, CH_1, rank 0
8681 19:26:53.942444 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8682 19:26:53.942528 ==
8683 19:26:53.942594 DQS Delay:
8684 19:26:53.942656 DQS0 = 0, DQS1 = 0
8685 19:26:53.945931 DQM Delay:
8686 19:26:53.946014 DQM0 = 134, DQM1 = 131
8687 19:26:53.949267 DQ Delay:
8688 19:26:53.952571 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
8689 19:26:53.955866 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =132
8690 19:26:53.959298 DQ8 =116, DQ9 =120, DQ10 =132, DQ11 =124
8691 19:26:53.962652 DQ12 =140, DQ13 =140, DQ14 =140, DQ15 =140
8692 19:26:53.962735
8693 19:26:53.962801
8694 19:26:53.962862
8695 19:26:53.966127 [DramC_TX_OE_Calibration] TA2
8696 19:26:53.969266 Original DQ_B0 (3 6) =30, OEN = 27
8697 19:26:53.972774 Original DQ_B1 (3 6) =30, OEN = 27
8698 19:26:53.976148 24, 0x0, End_B0=24 End_B1=24
8699 19:26:53.976233 25, 0x0, End_B0=25 End_B1=25
8700 19:26:53.979581 26, 0x0, End_B0=26 End_B1=26
8701 19:26:53.982737 27, 0x0, End_B0=27 End_B1=27
8702 19:26:53.985747 28, 0x0, End_B0=28 End_B1=28
8703 19:26:53.985832 29, 0x0, End_B0=29 End_B1=29
8704 19:26:53.989410 30, 0x0, End_B0=30 End_B1=30
8705 19:26:53.992434 31, 0x4141, End_B0=30 End_B1=30
8706 19:26:53.995598 Byte0 end_step=30 best_step=27
8707 19:26:53.998903 Byte1 end_step=30 best_step=27
8708 19:26:54.002097 Byte0 TX OE(2T, 0.5T) = (3, 3)
8709 19:26:54.005709 Byte1 TX OE(2T, 0.5T) = (3, 3)
8710 19:26:54.005792
8711 19:26:54.005856
8712 19:26:54.012364 [DQSOSCAuto] RK0, (LSB)MR18= 0x1927, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8713 19:26:54.015471 CH1 RK0: MR19=303, MR18=1927
8714 19:26:54.022203 CH1_RK0: MR19=0x303, MR18=0x1927, DQSOSC=390, MR23=63, INC=24, DEC=16
8715 19:26:54.022333
8716 19:26:54.025523 ----->DramcWriteLeveling(PI) begin...
8717 19:26:54.025665 ==
8718 19:26:54.029407 Dram Type= 6, Freq= 0, CH_1, rank 1
8719 19:26:54.032583 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8720 19:26:54.032666 ==
8721 19:26:54.035604 Write leveling (Byte 0): 25 => 25
8722 19:26:54.038957 Write leveling (Byte 1): 29 => 29
8723 19:26:54.042224 DramcWriteLeveling(PI) end<-----
8724 19:26:54.042329
8725 19:26:54.042410 ==
8726 19:26:54.045536 Dram Type= 6, Freq= 0, CH_1, rank 1
8727 19:26:54.048835 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8728 19:26:54.048917 ==
8729 19:26:54.052357 [Gating] SW mode calibration
8730 19:26:54.059079 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8731 19:26:54.065874 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8732 19:26:54.069399 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8733 19:26:54.072088 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8734 19:26:54.078761 1 4 8 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
8735 19:26:54.082135 1 4 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (0 0)
8736 19:26:54.085544 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8737 19:26:54.092369 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8738 19:26:54.095806 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8739 19:26:54.098579 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8740 19:26:54.105392 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8741 19:26:54.108809 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8742 19:26:54.112021 1 5 8 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 1)
8743 19:26:54.118878 1 5 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8744 19:26:54.122293 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8745 19:26:54.125336 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8746 19:26:54.132104 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8747 19:26:54.135447 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8748 19:26:54.138512 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8749 19:26:54.145323 1 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8750 19:26:54.148332 1 6 8 | B1->B0 | 4040 2424 | 0 0 | (0 0) (0 0)
8751 19:26:54.151660 1 6 12 | B1->B0 | 4646 4343 | 0 1 | (0 0) (0 0)
8752 19:26:54.158184 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8753 19:26:54.161777 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8754 19:26:54.165155 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8755 19:26:54.171522 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8756 19:26:54.175103 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8757 19:26:54.178614 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8758 19:26:54.185215 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8759 19:26:54.188543 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8760 19:26:54.191876 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8761 19:26:54.198557 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8762 19:26:54.201895 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8763 19:26:54.205184 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8764 19:26:54.211891 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8765 19:26:54.215304 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8766 19:26:54.218467 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8767 19:26:54.221902 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8768 19:26:54.228116 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8769 19:26:54.231564 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8770 19:26:54.234968 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8771 19:26:54.241714 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8772 19:26:54.244918 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8773 19:26:54.248322 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8774 19:26:54.254509 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8775 19:26:54.257861 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8776 19:26:54.261268 Total UI for P1: 0, mck2ui 16
8777 19:26:54.264491 best dqsien dly found for B1: ( 1, 9, 6)
8778 19:26:54.268328 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8779 19:26:54.271325 Total UI for P1: 0, mck2ui 16
8780 19:26:54.274780 best dqsien dly found for B0: ( 1, 9, 12)
8781 19:26:54.278062 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8782 19:26:54.281253 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8783 19:26:54.281337
8784 19:26:54.287865 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8785 19:26:54.291108 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8786 19:26:54.294397 [Gating] SW calibration Done
8787 19:26:54.294503 ==
8788 19:26:54.298096 Dram Type= 6, Freq= 0, CH_1, rank 1
8789 19:26:54.301300 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8790 19:26:54.301381 ==
8791 19:26:54.301464 RX Vref Scan: 0
8792 19:26:54.301565
8793 19:26:54.304850 RX Vref 0 -> 0, step: 1
8794 19:26:54.304931
8795 19:26:54.307691 RX Delay 0 -> 252, step: 8
8796 19:26:54.311102 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8797 19:26:54.314268 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8798 19:26:54.320775 iDelay=208, Bit 2, Center 119 (64 ~ 175) 112
8799 19:26:54.324667 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8800 19:26:54.327997 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8801 19:26:54.331438 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8802 19:26:54.334182 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8803 19:26:54.337599 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8804 19:26:54.344395 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8805 19:26:54.347877 iDelay=208, Bit 9, Center 123 (72 ~ 175) 104
8806 19:26:54.351264 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8807 19:26:54.354706 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8808 19:26:54.357515 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8809 19:26:54.364214 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8810 19:26:54.367613 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8811 19:26:54.371114 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8812 19:26:54.371194 ==
8813 19:26:54.374501 Dram Type= 6, Freq= 0, CH_1, rank 1
8814 19:26:54.377869 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8815 19:26:54.381290 ==
8816 19:26:54.381370 DQS Delay:
8817 19:26:54.381451 DQS0 = 0, DQS1 = 0
8818 19:26:54.384557 DQM Delay:
8819 19:26:54.384637 DQM0 = 135, DQM1 = 134
8820 19:26:54.387585 DQ Delay:
8821 19:26:54.390742 DQ0 =139, DQ1 =135, DQ2 =119, DQ3 =131
8822 19:26:54.394553 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8823 19:26:54.397606 DQ8 =119, DQ9 =123, DQ10 =135, DQ11 =127
8824 19:26:54.401320 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8825 19:26:54.401413
8826 19:26:54.401516
8827 19:26:54.401576 ==
8828 19:26:54.404430 Dram Type= 6, Freq= 0, CH_1, rank 1
8829 19:26:54.407869 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8830 19:26:54.407949 ==
8831 19:26:54.408013
8832 19:26:54.408071
8833 19:26:54.411164 TX Vref Scan disable
8834 19:26:54.414421 == TX Byte 0 ==
8835 19:26:54.417580 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8836 19:26:54.420772 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8837 19:26:54.423993 == TX Byte 1 ==
8838 19:26:54.427179 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8839 19:26:54.430935 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8840 19:26:54.431016 ==
8841 19:26:54.433835 Dram Type= 6, Freq= 0, CH_1, rank 1
8842 19:26:54.440661 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8843 19:26:54.440741 ==
8844 19:26:54.452504
8845 19:26:54.455763 TX Vref early break, caculate TX vref
8846 19:26:54.459180 TX Vref=16, minBit 0, minWin=23, winSum=381
8847 19:26:54.462591 TX Vref=18, minBit 0, minWin=24, winSum=395
8848 19:26:54.465858 TX Vref=20, minBit 1, minWin=24, winSum=401
8849 19:26:54.468653 TX Vref=22, minBit 0, minWin=24, winSum=411
8850 19:26:54.472167 TX Vref=24, minBit 0, minWin=24, winSum=416
8851 19:26:54.478882 TX Vref=26, minBit 0, minWin=25, winSum=427
8852 19:26:54.482361 TX Vref=28, minBit 6, minWin=24, winSum=423
8853 19:26:54.485662 TX Vref=30, minBit 0, minWin=25, winSum=419
8854 19:26:54.489015 TX Vref=32, minBit 6, minWin=24, winSum=411
8855 19:26:54.492293 TX Vref=34, minBit 0, minWin=24, winSum=403
8856 19:26:54.498881 [TxChooseVref] Worse bit 0, Min win 25, Win sum 427, Final Vref 26
8857 19:26:54.498963
8858 19:26:54.502100 Final TX Range 0 Vref 26
8859 19:26:54.502180
8860 19:26:54.502261 ==
8861 19:26:54.505181 Dram Type= 6, Freq= 0, CH_1, rank 1
8862 19:26:54.508770 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8863 19:26:54.508868 ==
8864 19:26:54.508946
8865 19:26:54.509042
8866 19:26:54.511760 TX Vref Scan disable
8867 19:26:54.518775 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8868 19:26:54.518856 == TX Byte 0 ==
8869 19:26:54.522055 u2DelayCellOfst[0]=16 cells (5 PI)
8870 19:26:54.525385 u2DelayCellOfst[1]=10 cells (3 PI)
8871 19:26:54.528601 u2DelayCellOfst[2]=0 cells (0 PI)
8872 19:26:54.531993 u2DelayCellOfst[3]=6 cells (2 PI)
8873 19:26:54.535446 u2DelayCellOfst[4]=6 cells (2 PI)
8874 19:26:54.538891 u2DelayCellOfst[5]=16 cells (5 PI)
8875 19:26:54.542431 u2DelayCellOfst[6]=16 cells (5 PI)
8876 19:26:54.542528 u2DelayCellOfst[7]=6 cells (2 PI)
8877 19:26:54.548593 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8878 19:26:54.551855 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8879 19:26:54.551936 == TX Byte 1 ==
8880 19:26:54.555191 u2DelayCellOfst[8]=0 cells (0 PI)
8881 19:26:54.558457 u2DelayCellOfst[9]=3 cells (1 PI)
8882 19:26:54.562199 u2DelayCellOfst[10]=10 cells (3 PI)
8883 19:26:54.565411 u2DelayCellOfst[11]=3 cells (1 PI)
8884 19:26:54.568820 u2DelayCellOfst[12]=13 cells (4 PI)
8885 19:26:54.571977 u2DelayCellOfst[13]=13 cells (4 PI)
8886 19:26:54.575561 u2DelayCellOfst[14]=16 cells (5 PI)
8887 19:26:54.578430 u2DelayCellOfst[15]=16 cells (5 PI)
8888 19:26:54.582019 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8889 19:26:54.588463 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8890 19:26:54.588543 DramC Write-DBI on
8891 19:26:54.588607 ==
8892 19:26:54.591852 Dram Type= 6, Freq= 0, CH_1, rank 1
8893 19:26:54.595241 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8894 19:26:54.598548 ==
8895 19:26:54.598628
8896 19:26:54.598691
8897 19:26:54.598751 TX Vref Scan disable
8898 19:26:54.601931 == TX Byte 0 ==
8899 19:26:54.604692 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8900 19:26:54.608113 == TX Byte 1 ==
8901 19:26:54.611501 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8902 19:26:54.614865 DramC Write-DBI off
8903 19:26:54.614946
8904 19:26:54.615010 [DATLAT]
8905 19:26:54.615070 Freq=1600, CH1 RK1
8906 19:26:54.615129
8907 19:26:54.618037 DATLAT Default: 0xf
8908 19:26:54.618164 0, 0xFFFF, sum = 0
8909 19:26:54.621688 1, 0xFFFF, sum = 0
8910 19:26:54.624585 2, 0xFFFF, sum = 0
8911 19:26:54.624668 3, 0xFFFF, sum = 0
8912 19:26:54.627764 4, 0xFFFF, sum = 0
8913 19:26:54.627848 5, 0xFFFF, sum = 0
8914 19:26:54.631425 6, 0xFFFF, sum = 0
8915 19:26:54.631507 7, 0xFFFF, sum = 0
8916 19:26:54.634775 8, 0xFFFF, sum = 0
8917 19:26:54.634858 9, 0xFFFF, sum = 0
8918 19:26:54.638262 10, 0xFFFF, sum = 0
8919 19:26:54.638395 11, 0xFFFF, sum = 0
8920 19:26:54.641384 12, 0xFFFF, sum = 0
8921 19:26:54.641466 13, 0xFFFF, sum = 0
8922 19:26:54.644587 14, 0x0, sum = 1
8923 19:26:54.644669 15, 0x0, sum = 2
8924 19:26:54.647920 16, 0x0, sum = 3
8925 19:26:54.648002 17, 0x0, sum = 4
8926 19:26:54.651302 best_step = 15
8927 19:26:54.651384
8928 19:26:54.651465 ==
8929 19:26:54.654646 Dram Type= 6, Freq= 0, CH_1, rank 1
8930 19:26:54.657921 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8931 19:26:54.658002 ==
8932 19:26:54.661415 RX Vref Scan: 0
8933 19:26:54.661496
8934 19:26:54.661560 RX Vref 0 -> 0, step: 1
8935 19:26:54.661620
8936 19:26:54.664865 RX Delay 19 -> 252, step: 4
8937 19:26:54.668126 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8938 19:26:54.674331 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8939 19:26:54.677730 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8940 19:26:54.681586 iDelay=195, Bit 3, Center 128 (83 ~ 174) 92
8941 19:26:54.684826 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8942 19:26:54.687730 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8943 19:26:54.691246 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8944 19:26:54.697625 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
8945 19:26:54.701282 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8946 19:26:54.704701 iDelay=195, Bit 9, Center 120 (67 ~ 174) 108
8947 19:26:54.707916 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8948 19:26:54.714328 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
8949 19:26:54.717718 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8950 19:26:54.721290 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8951 19:26:54.724693 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8952 19:26:54.727777 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
8953 19:26:54.730825 ==
8954 19:26:54.730900 Dram Type= 6, Freq= 0, CH_1, rank 1
8955 19:26:54.737846 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8956 19:26:54.737929 ==
8957 19:26:54.737993 DQS Delay:
8958 19:26:54.741190 DQS0 = 0, DQS1 = 0
8959 19:26:54.741301 DQM Delay:
8960 19:26:54.744301 DQM0 = 134, DQM1 = 131
8961 19:26:54.744382 DQ Delay:
8962 19:26:54.747445 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =128
8963 19:26:54.751083 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
8964 19:26:54.754050 DQ8 =116, DQ9 =120, DQ10 =132, DQ11 =126
8965 19:26:54.757526 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
8966 19:26:54.757608
8967 19:26:54.757672
8968 19:26:54.757769
8969 19:26:54.760716 [DramC_TX_OE_Calibration] TA2
8970 19:26:54.764408 Original DQ_B0 (3 6) =30, OEN = 27
8971 19:26:54.767791 Original DQ_B1 (3 6) =30, OEN = 27
8972 19:26:54.771253 24, 0x0, End_B0=24 End_B1=24
8973 19:26:54.773886 25, 0x0, End_B0=25 End_B1=25
8974 19:26:54.773967 26, 0x0, End_B0=26 End_B1=26
8975 19:26:54.777437 27, 0x0, End_B0=27 End_B1=27
8976 19:26:54.780792 28, 0x0, End_B0=28 End_B1=28
8977 19:26:54.784245 29, 0x0, End_B0=29 End_B1=29
8978 19:26:54.784327 30, 0x0, End_B0=30 End_B1=30
8979 19:26:54.787727 31, 0x4141, End_B0=30 End_B1=30
8980 19:26:54.791118 Byte0 end_step=30 best_step=27
8981 19:26:54.794438 Byte1 end_step=30 best_step=27
8982 19:26:54.797702 Byte0 TX OE(2T, 0.5T) = (3, 3)
8983 19:26:54.800600 Byte1 TX OE(2T, 0.5T) = (3, 3)
8984 19:26:54.800672
8985 19:26:54.800751
8986 19:26:54.807282 [DQSOSCAuto] RK1, (LSB)MR18= 0x2409, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
8987 19:26:54.810507 CH1 RK1: MR19=303, MR18=2409
8988 19:26:54.817578 CH1_RK1: MR19=0x303, MR18=0x2409, DQSOSC=391, MR23=63, INC=24, DEC=16
8989 19:26:54.820774 [RxdqsGatingPostProcess] freq 1600
8990 19:26:54.823925 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8991 19:26:54.827259 best DQS0 dly(2T, 0.5T) = (1, 1)
8992 19:26:54.830921 best DQS1 dly(2T, 0.5T) = (1, 1)
8993 19:26:54.834040 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8994 19:26:54.837666 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8995 19:26:54.840519 best DQS0 dly(2T, 0.5T) = (1, 1)
8996 19:26:54.844305 best DQS1 dly(2T, 0.5T) = (1, 1)
8997 19:26:54.847197 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8998 19:26:54.850780 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8999 19:26:54.854217 Pre-setting of DQS Precalculation
9000 19:26:54.857553 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9001 19:26:54.863955 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9002 19:26:54.874285 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9003 19:26:54.874401
9004 19:26:54.874466
9005 19:26:54.877624 [Calibration Summary] 3200 Mbps
9006 19:26:54.877722 CH 0, Rank 0
9007 19:26:54.880331 SW Impedance : PASS
9008 19:26:54.880430 DUTY Scan : NO K
9009 19:26:54.883799 ZQ Calibration : PASS
9010 19:26:54.883880 Jitter Meter : NO K
9011 19:26:54.887258 CBT Training : PASS
9012 19:26:54.890693 Write leveling : PASS
9013 19:26:54.890774 RX DQS gating : PASS
9014 19:26:54.893530 RX DQ/DQS(RDDQC) : PASS
9015 19:26:54.896949 TX DQ/DQS : PASS
9016 19:26:54.897031 RX DATLAT : PASS
9017 19:26:54.900410 RX DQ/DQS(Engine): PASS
9018 19:26:54.903832 TX OE : PASS
9019 19:26:54.903913 All Pass.
9020 19:26:54.904017
9021 19:26:54.904077 CH 0, Rank 1
9022 19:26:54.907264 SW Impedance : PASS
9023 19:26:54.910552 DUTY Scan : NO K
9024 19:26:54.910633 ZQ Calibration : PASS
9025 19:26:54.913871 Jitter Meter : NO K
9026 19:26:54.917394 CBT Training : PASS
9027 19:26:54.917476 Write leveling : PASS
9028 19:26:54.920831 RX DQS gating : PASS
9029 19:26:54.923614 RX DQ/DQS(RDDQC) : PASS
9030 19:26:54.923696 TX DQ/DQS : PASS
9031 19:26:54.926890 RX DATLAT : PASS
9032 19:26:54.930086 RX DQ/DQS(Engine): PASS
9033 19:26:54.930168 TX OE : PASS
9034 19:26:54.930232 All Pass.
9035 19:26:54.933416
9036 19:26:54.933496 CH 1, Rank 0
9037 19:26:54.936652 SW Impedance : PASS
9038 19:26:54.936733 DUTY Scan : NO K
9039 19:26:54.940544 ZQ Calibration : PASS
9040 19:26:54.940625 Jitter Meter : NO K
9041 19:26:54.943523 CBT Training : PASS
9042 19:26:54.946877 Write leveling : PASS
9043 19:26:54.946959 RX DQS gating : PASS
9044 19:26:54.949995 RX DQ/DQS(RDDQC) : PASS
9045 19:26:54.953416 TX DQ/DQS : PASS
9046 19:26:54.953507 RX DATLAT : PASS
9047 19:26:54.956671 RX DQ/DQS(Engine): PASS
9048 19:26:54.960224 TX OE : PASS
9049 19:26:54.960306 All Pass.
9050 19:26:54.960382
9051 19:26:54.960479 CH 1, Rank 1
9052 19:26:54.963553 SW Impedance : PASS
9053 19:26:54.966825 DUTY Scan : NO K
9054 19:26:54.966906 ZQ Calibration : PASS
9055 19:26:54.970076 Jitter Meter : NO K
9056 19:26:54.973528 CBT Training : PASS
9057 19:26:54.973655 Write leveling : PASS
9058 19:26:54.976581 RX DQS gating : PASS
9059 19:26:54.980192 RX DQ/DQS(RDDQC) : PASS
9060 19:26:54.980292 TX DQ/DQS : PASS
9061 19:26:54.983634 RX DATLAT : PASS
9062 19:26:54.986510 RX DQ/DQS(Engine): PASS
9063 19:26:54.986592 TX OE : PASS
9064 19:26:54.986657 All Pass.
9065 19:26:54.986716
9066 19:26:54.990102 DramC Write-DBI on
9067 19:26:54.993327 PER_BANK_REFRESH: Hybrid Mode
9068 19:26:54.993408 TX_TRACKING: ON
9069 19:26:55.003136 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9070 19:26:55.010055 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9071 19:26:55.020403 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9072 19:26:55.023982 [FAST_K] Save calibration result to emmc
9073 19:26:55.024064 sync common calibartion params.
9074 19:26:55.026538 sync cbt_mode0:1, 1:1
9075 19:26:55.030486 dram_init: ddr_geometry: 2
9076 19:26:55.030567 dram_init: ddr_geometry: 2
9077 19:26:55.033694 dram_init: ddr_geometry: 2
9078 19:26:55.036793 0:dram_rank_size:100000000
9079 19:26:55.040190 1:dram_rank_size:100000000
9080 19:26:55.043447 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9081 19:26:55.046823 DFS_SHUFFLE_HW_MODE: ON
9082 19:26:55.050145 dramc_set_vcore_voltage set vcore to 725000
9083 19:26:55.052895 Read voltage for 1600, 0
9084 19:26:55.052976 Vio18 = 0
9085 19:26:55.056203 Vcore = 725000
9086 19:26:55.056283 Vdram = 0
9087 19:26:55.056348 Vddq = 0
9088 19:26:55.056408 Vmddr = 0
9089 19:26:55.059483 switch to 3200 Mbps bootup
9090 19:26:55.062972 [DramcRunTimeConfig]
9091 19:26:55.063055 PHYPLL
9092 19:26:55.066283 DPM_CONTROL_AFTERK: ON
9093 19:26:55.066403 PER_BANK_REFRESH: ON
9094 19:26:55.069881 REFRESH_OVERHEAD_REDUCTION: ON
9095 19:26:55.072950 CMD_PICG_NEW_MODE: OFF
9096 19:26:55.073030 XRTWTW_NEW_MODE: ON
9097 19:26:55.076267 XRTRTR_NEW_MODE: ON
9098 19:26:55.076347 TX_TRACKING: ON
9099 19:26:55.079615 RDSEL_TRACKING: OFF
9100 19:26:55.082592 DQS Precalculation for DVFS: ON
9101 19:26:55.082690 RX_TRACKING: OFF
9102 19:26:55.086207 HW_GATING DBG: ON
9103 19:26:55.086290 ZQCS_ENABLE_LP4: ON
9104 19:26:55.089642 RX_PICG_NEW_MODE: ON
9105 19:26:55.089723 TX_PICG_NEW_MODE: ON
9106 19:26:55.092842 ENABLE_RX_DCM_DPHY: ON
9107 19:26:55.095996 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9108 19:26:55.099471 DUMMY_READ_FOR_TRACKING: OFF
9109 19:26:55.099552 !!! SPM_CONTROL_AFTERK: OFF
9110 19:26:55.102540 !!! SPM could not control APHY
9111 19:26:55.106102 IMPEDANCE_TRACKING: ON
9112 19:26:55.106183 TEMP_SENSOR: ON
9113 19:26:55.109866 HW_SAVE_FOR_SR: OFF
9114 19:26:55.112917 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9115 19:26:55.116147 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9116 19:26:55.116229 Read ODT Tracking: ON
9117 19:26:55.119440 Refresh Rate DeBounce: ON
9118 19:26:55.122573 DFS_NO_QUEUE_FLUSH: ON
9119 19:26:55.125960 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9120 19:26:55.126042 ENABLE_DFS_RUNTIME_MRW: OFF
9121 19:26:55.129345 DDR_RESERVE_NEW_MODE: ON
9122 19:26:55.132761 MR_CBT_SWITCH_FREQ: ON
9123 19:26:55.132842 =========================
9124 19:26:55.152805 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9125 19:26:55.156126 dram_init: ddr_geometry: 2
9126 19:26:55.174482 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9127 19:26:55.177682 dram_init: dram init end (result: 0)
9128 19:26:55.184372 DRAM-K: Full calibration passed in 24424 msecs
9129 19:26:55.187747 MRC: failed to locate region type 0.
9130 19:26:55.187837 DRAM rank0 size:0x100000000,
9131 19:26:55.191194 DRAM rank1 size=0x100000000
9132 19:26:55.200909 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9133 19:26:55.207592 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9134 19:26:55.214074 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9135 19:26:55.220953 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9136 19:26:55.224236 DRAM rank0 size:0x100000000,
9137 19:26:55.227482 DRAM rank1 size=0x100000000
9138 19:26:55.227563 CBMEM:
9139 19:26:55.230649 IMD: root @ 0xfffff000 254 entries.
9140 19:26:55.234197 IMD: root @ 0xffffec00 62 entries.
9141 19:26:55.237141 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9142 19:26:55.240586 WARNING: RO_VPD is uninitialized or empty.
9143 19:26:55.247091 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9144 19:26:55.254311 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9145 19:26:55.267522 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9146 19:26:55.278322 BS: romstage times (exec / console): total (unknown) / 23961 ms
9147 19:26:55.278419
9148 19:26:55.278483
9149 19:26:55.288636 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9150 19:26:55.291718 ARM64: Exception handlers installed.
9151 19:26:55.295285 ARM64: Testing exception
9152 19:26:55.298344 ARM64: Done test exception
9153 19:26:55.298444 Enumerating buses...
9154 19:26:55.301692 Show all devs... Before device enumeration.
9155 19:26:55.305127 Root Device: enabled 1
9156 19:26:55.308306 CPU_CLUSTER: 0: enabled 1
9157 19:26:55.308379 CPU: 00: enabled 1
9158 19:26:55.311629 Compare with tree...
9159 19:26:55.311699 Root Device: enabled 1
9160 19:26:55.315381 CPU_CLUSTER: 0: enabled 1
9161 19:26:55.318451 CPU: 00: enabled 1
9162 19:26:55.318535 Root Device scanning...
9163 19:26:55.321674 scan_static_bus for Root Device
9164 19:26:55.324870 CPU_CLUSTER: 0 enabled
9165 19:26:55.328401 scan_static_bus for Root Device done
9166 19:26:55.331646 scan_bus: bus Root Device finished in 8 msecs
9167 19:26:55.331744 done
9168 19:26:55.338498 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9169 19:26:55.341211 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9170 19:26:55.347899 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9171 19:26:55.351658 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9172 19:26:55.354666 Allocating resources...
9173 19:26:55.358246 Reading resources...
9174 19:26:55.361566 Root Device read_resources bus 0 link: 0
9175 19:26:55.361636 DRAM rank0 size:0x100000000,
9176 19:26:55.364573 DRAM rank1 size=0x100000000
9177 19:26:55.368188 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9178 19:26:55.371646 CPU: 00 missing read_resources
9179 19:26:55.374474 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9180 19:26:55.381307 Root Device read_resources bus 0 link: 0 done
9181 19:26:55.381389 Done reading resources.
9182 19:26:55.388224 Show resources in subtree (Root Device)...After reading.
9183 19:26:55.391476 Root Device child on link 0 CPU_CLUSTER: 0
9184 19:26:55.394892 CPU_CLUSTER: 0 child on link 0 CPU: 00
9185 19:26:55.404653 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9186 19:26:55.404735 CPU: 00
9187 19:26:55.407657 Root Device assign_resources, bus 0 link: 0
9188 19:26:55.411228 CPU_CLUSTER: 0 missing set_resources
9189 19:26:55.417886 Root Device assign_resources, bus 0 link: 0 done
9190 19:26:55.417968 Done setting resources.
9191 19:26:55.424380 Show resources in subtree (Root Device)...After assigning values.
9192 19:26:55.427667 Root Device child on link 0 CPU_CLUSTER: 0
9193 19:26:55.430876 CPU_CLUSTER: 0 child on link 0 CPU: 00
9194 19:26:55.441225 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9195 19:26:55.441339 CPU: 00
9196 19:26:55.444561 Done allocating resources.
9197 19:26:55.447894 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9198 19:26:55.451393 Enabling resources...
9199 19:26:55.451474 done.
9200 19:26:55.457498 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9201 19:26:55.457594 Initializing devices...
9202 19:26:55.460860 Root Device init
9203 19:26:55.460943 init hardware done!
9204 19:26:55.464145 0x00000018: ctrlr->caps
9205 19:26:55.468049 52.000 MHz: ctrlr->f_max
9206 19:26:55.468147 0.400 MHz: ctrlr->f_min
9207 19:26:55.471437 0x40ff8080: ctrlr->voltages
9208 19:26:55.471521 sclk: 390625
9209 19:26:55.474540 Bus Width = 1
9210 19:26:55.474622 sclk: 390625
9211 19:26:55.477185 Bus Width = 1
9212 19:26:55.477268 Early init status = 3
9213 19:26:55.484358 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9214 19:26:55.487684 in-header: 03 fc 00 00 01 00 00 00
9215 19:26:55.490768 in-data: 00
9216 19:26:55.493789 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9217 19:26:55.499054 in-header: 03 fd 00 00 00 00 00 00
9218 19:26:55.502137 in-data:
9219 19:26:55.505895 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9220 19:26:55.510503 in-header: 03 fc 00 00 01 00 00 00
9221 19:26:55.513783 in-data: 00
9222 19:26:55.516975 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9223 19:26:55.522262 in-header: 03 fd 00 00 00 00 00 00
9224 19:26:55.525428 in-data:
9225 19:26:55.528910 [SSUSB] Setting up USB HOST controller...
9226 19:26:55.532578 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9227 19:26:55.535459 [SSUSB] phy power-on done.
9228 19:26:55.539047 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9229 19:26:55.545452 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9230 19:26:55.548784 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9231 19:26:55.555675 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9232 19:26:55.562348 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9233 19:26:55.569184 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9234 19:26:55.575581 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9235 19:26:55.582348 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9236 19:26:55.585502 SPM: binary array size = 0x9dc
9237 19:26:55.588753 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9238 19:26:55.595569 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9239 19:26:55.602092 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9240 19:26:55.605603 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9241 19:26:55.612202 configure_display: Starting display init
9242 19:26:55.645552 anx7625_power_on_init: Init interface.
9243 19:26:55.648649 anx7625_disable_pd_protocol: Disabled PD feature.
9244 19:26:55.652334 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9245 19:26:55.679985 anx7625_start_dp_work: Secure OCM version=00
9246 19:26:55.683544 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9247 19:26:55.698192 sp_tx_get_edid_block: EDID Block = 1
9248 19:26:55.800513 Extracted contents:
9249 19:26:55.803847 header: 00 ff ff ff ff ff ff 00
9250 19:26:55.807243 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9251 19:26:55.810525 version: 01 04
9252 19:26:55.813902 basic params: 95 1f 11 78 0a
9253 19:26:55.817237 chroma info: 76 90 94 55 54 90 27 21 50 54
9254 19:26:55.820714 established: 00 00 00
9255 19:26:55.827487 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9256 19:26:55.830231 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9257 19:26:55.836914 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9258 19:26:55.844007 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9259 19:26:55.850651 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9260 19:26:55.853530 extensions: 00
9261 19:26:55.853613 checksum: fb
9262 19:26:55.853678
9263 19:26:55.856976 Manufacturer: IVO Model 57d Serial Number 0
9264 19:26:55.860453 Made week 0 of 2020
9265 19:26:55.860564 EDID version: 1.4
9266 19:26:55.863573 Digital display
9267 19:26:55.867125 6 bits per primary color channel
9268 19:26:55.867211 DisplayPort interface
9269 19:26:55.870098 Maximum image size: 31 cm x 17 cm
9270 19:26:55.873682 Gamma: 220%
9271 19:26:55.873764 Check DPMS levels
9272 19:26:55.876730 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9273 19:26:55.880232 First detailed timing is preferred timing
9274 19:26:55.883521 Established timings supported:
9275 19:26:55.887000 Standard timings supported:
9276 19:26:55.890320 Detailed timings
9277 19:26:55.893455 Hex of detail: 383680a07038204018303c0035ae10000019
9278 19:26:55.896670 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9279 19:26:55.903432 0780 0798 07c8 0820 hborder 0
9280 19:26:55.906636 0438 043b 0447 0458 vborder 0
9281 19:26:55.909910 -hsync -vsync
9282 19:26:55.909994 Did detailed timing
9283 19:26:55.916596 Hex of detail: 000000000000000000000000000000000000
9284 19:26:55.916680 Manufacturer-specified data, tag 0
9285 19:26:55.923373 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9286 19:26:55.926774 ASCII string: InfoVision
9287 19:26:55.930249 Hex of detail: 000000fe00523134304e574635205248200a
9288 19:26:55.933558 ASCII string: R140NWF5 RH
9289 19:26:55.933641 Checksum
9290 19:26:55.936852 Checksum: 0xfb (valid)
9291 19:26:55.940201 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9292 19:26:55.943617 DSI data_rate: 832800000 bps
9293 19:26:55.949735 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9294 19:26:55.953110 anx7625_parse_edid: pixelclock(138800).
9295 19:26:55.956431 hactive(1920), hsync(48), hfp(24), hbp(88)
9296 19:26:55.959783 vactive(1080), vsync(12), vfp(3), vbp(17)
9297 19:26:55.963531 anx7625_dsi_config: config dsi.
9298 19:26:55.969781 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9299 19:26:55.982709 anx7625_dsi_config: success to config DSI
9300 19:26:55.985775 anx7625_dp_start: MIPI phy setup OK.
9301 19:26:55.989472 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9302 19:26:55.992368 mtk_ddp_mode_set invalid vrefresh 60
9303 19:26:55.995975 main_disp_path_setup
9304 19:26:55.996061 ovl_layer_smi_id_en
9305 19:26:55.999459 ovl_layer_smi_id_en
9306 19:26:55.999560 ccorr_config
9307 19:26:55.999651 aal_config
9308 19:26:56.002545 gamma_config
9309 19:26:56.002653 postmask_config
9310 19:26:56.005795 dither_config
9311 19:26:56.009143 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9312 19:26:56.015773 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9313 19:26:56.018835 Root Device init finished in 555 msecs
9314 19:26:56.022607 CPU_CLUSTER: 0 init
9315 19:26:56.029363 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9316 19:26:56.032824 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9317 19:26:56.035553 APU_MBOX 0x190000b0 = 0x10001
9318 19:26:56.038770 APU_MBOX 0x190001b0 = 0x10001
9319 19:26:56.042189 APU_MBOX 0x190005b0 = 0x10001
9320 19:26:56.045458 APU_MBOX 0x190006b0 = 0x10001
9321 19:26:56.048823 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9322 19:26:56.061677 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9323 19:26:56.073780 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9324 19:26:56.080527 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9325 19:26:56.092450 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9326 19:26:56.101108 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9327 19:26:56.105079 CPU_CLUSTER: 0 init finished in 81 msecs
9328 19:26:56.108157 Devices initialized
9329 19:26:56.111103 Show all devs... After init.
9330 19:26:56.111177 Root Device: enabled 1
9331 19:26:56.114545 CPU_CLUSTER: 0: enabled 1
9332 19:26:56.117865 CPU: 00: enabled 1
9333 19:26:56.121565 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9334 19:26:56.124627 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9335 19:26:56.127884 ELOG: NV offset 0x57f000 size 0x1000
9336 19:26:56.134264 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9337 19:26:56.141506 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9338 19:26:56.144223 ELOG: Event(17) added with size 13 at 2024-04-18 19:22:45 UTC
9339 19:26:56.151251 out: cmd=0x121: 03 db 21 01 00 00 00 00
9340 19:26:56.154704 in-header: 03 0a 00 00 2c 00 00 00
9341 19:26:56.164284 in-data: 54 69 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9342 19:26:56.171154 ELOG: Event(A1) added with size 10 at 2024-04-18 19:22:45 UTC
9343 19:26:56.177886 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9344 19:26:56.184173 ELOG: Event(A0) added with size 9 at 2024-04-18 19:22:45 UTC
9345 19:26:56.187572 elog_add_boot_reason: Logged dev mode boot
9346 19:26:56.190796 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9347 19:26:56.193867 Finalize devices...
9348 19:26:56.197725 Devices finalized
9349 19:26:56.200900 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9350 19:26:56.204157 Writing coreboot table at 0xffe64000
9351 19:26:56.207429 0. 000000000010a000-0000000000113fff: RAMSTAGE
9352 19:26:56.211139 1. 0000000040000000-00000000400fffff: RAM
9353 19:26:56.217399 2. 0000000040100000-000000004032afff: RAMSTAGE
9354 19:26:56.220710 3. 000000004032b000-00000000545fffff: RAM
9355 19:26:56.224002 4. 0000000054600000-000000005465ffff: BL31
9356 19:26:56.227218 5. 0000000054660000-00000000ffe63fff: RAM
9357 19:26:56.234396 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9358 19:26:56.237230 7. 0000000100000000-000000023fffffff: RAM
9359 19:26:56.240570 Passing 5 GPIOs to payload:
9360 19:26:56.243964 NAME | PORT | POLARITY | VALUE
9361 19:26:56.247606 EC in RW | 0x000000aa | low | undefined
9362 19:26:56.254160 EC interrupt | 0x00000005 | low | undefined
9363 19:26:56.257623 TPM interrupt | 0x000000ab | high | undefined
9364 19:26:56.264233 SD card detect | 0x00000011 | high | undefined
9365 19:26:56.267694 speaker enable | 0x00000093 | high | undefined
9366 19:26:56.270460 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9367 19:26:56.273885 in-header: 03 f9 00 00 02 00 00 00
9368 19:26:56.277382 in-data: 02 00
9369 19:26:56.277479 ADC[4]: Raw value=904357 ID=7
9370 19:26:56.280728 ADC[3]: Raw value=213441 ID=1
9371 19:26:56.284622 RAM Code: 0x71
9372 19:26:56.284702 ADC[6]: Raw value=75332 ID=0
9373 19:26:56.287331 ADC[5]: Raw value=213072 ID=1
9374 19:26:56.290668 SKU Code: 0x1
9375 19:26:56.294084 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 9a37
9376 19:26:56.297389 coreboot table: 964 bytes.
9377 19:26:56.301087 IMD ROOT 0. 0xfffff000 0x00001000
9378 19:26:56.304205 IMD SMALL 1. 0xffffe000 0x00001000
9379 19:26:56.307530 RO MCACHE 2. 0xffffc000 0x00001104
9380 19:26:56.310797 CONSOLE 3. 0xfff7c000 0x00080000
9381 19:26:56.313941 FMAP 4. 0xfff7b000 0x00000452
9382 19:26:56.317179 TIME STAMP 5. 0xfff7a000 0x00000910
9383 19:26:56.320559 VBOOT WORK 6. 0xfff66000 0x00014000
9384 19:26:56.323853 RAMOOPS 7. 0xffe66000 0x00100000
9385 19:26:56.327253 COREBOOT 8. 0xffe64000 0x00002000
9386 19:26:56.327333 IMD small region:
9387 19:26:56.330744 IMD ROOT 0. 0xffffec00 0x00000400
9388 19:26:56.334171 VPD 1. 0xffffeb80 0x0000006c
9389 19:26:56.337572 MMC STATUS 2. 0xffffeb60 0x00000004
9390 19:26:56.344204 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9391 19:26:56.347408 Probing TPM: done!
9392 19:26:56.350694 Connected to device vid:did:rid of 1ae0:0028:00
9393 19:26:56.360717 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9394 19:26:56.364256 Initialized TPM device CR50 revision 0
9395 19:26:56.367542 Checking cr50 for pending updates
9396 19:26:56.371225 Reading cr50 TPM mode
9397 19:26:56.379830 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9398 19:26:56.386602 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9399 19:26:56.426653 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9400 19:26:56.429950 Checking segment from ROM address 0x40100000
9401 19:26:56.433359 Checking segment from ROM address 0x4010001c
9402 19:26:56.440152 Loading segment from ROM address 0x40100000
9403 19:26:56.440238 code (compression=0)
9404 19:26:56.446775 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9405 19:26:56.456845 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9406 19:26:56.456930 it's not compressed!
9407 19:26:56.463671 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9408 19:26:56.466439 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9409 19:26:56.487355 Loading segment from ROM address 0x4010001c
9410 19:26:56.487441 Entry Point 0x80000000
9411 19:26:56.490231 Loaded segments
9412 19:26:56.493610 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9413 19:26:56.500443 Jumping to boot code at 0x80000000(0xffe64000)
9414 19:26:56.506793 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9415 19:26:56.513419 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9416 19:26:56.521637 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9417 19:26:56.525169 Checking segment from ROM address 0x40100000
9418 19:26:56.528383 Checking segment from ROM address 0x4010001c
9419 19:26:56.534862 Loading segment from ROM address 0x40100000
9420 19:26:56.534948 code (compression=1)
9421 19:26:56.541525 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9422 19:26:56.551470 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9423 19:26:56.551556 using LZMA
9424 19:26:56.560175 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9425 19:26:56.566400 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9426 19:26:56.569897 Loading segment from ROM address 0x4010001c
9427 19:26:56.569981 Entry Point 0x54601000
9428 19:26:56.573285 Loaded segments
9429 19:26:56.576124 NOTICE: MT8192 bl31_setup
9430 19:26:56.583536 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9431 19:26:56.586991 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9432 19:26:56.590368 WARNING: region 0:
9433 19:26:56.593695 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9434 19:26:56.593775 WARNING: region 1:
9435 19:26:56.600376 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9436 19:26:56.600482 WARNING: region 2:
9437 19:26:56.606702 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9438 19:26:56.610440 WARNING: region 3:
9439 19:26:56.613660 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9440 19:26:56.617293 WARNING: region 4:
9441 19:26:56.620307 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9442 19:26:56.623876 WARNING: region 5:
9443 19:26:56.626871 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9444 19:26:56.630238 WARNING: region 6:
9445 19:26:56.633915 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9446 19:26:56.633996 WARNING: region 7:
9447 19:26:56.640797 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9448 19:26:56.647170 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9449 19:26:56.650655 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9450 19:26:56.653647 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9451 19:26:56.660184 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9452 19:26:56.663975 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9453 19:26:56.667103 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9454 19:26:56.673842 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9455 19:26:56.677386 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9456 19:26:56.680737 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9457 19:26:56.686826 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9458 19:26:56.690259 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9459 19:26:56.693639 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9460 19:26:56.700466 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9461 19:26:56.703864 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9462 19:26:56.710613 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9463 19:26:56.713908 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9464 19:26:56.717034 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9465 19:26:56.723744 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9466 19:26:56.726898 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9467 19:26:56.730185 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9468 19:26:56.736955 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9469 19:26:56.740197 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9470 19:26:56.747238 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9471 19:26:56.750260 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9472 19:26:56.753436 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9473 19:26:56.760497 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9474 19:26:56.763531 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9475 19:26:56.770022 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9476 19:26:56.773702 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9477 19:26:56.777080 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9478 19:26:56.783878 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9479 19:26:56.786757 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9480 19:26:56.790120 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9481 19:26:56.797314 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9482 19:26:56.800643 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9483 19:26:56.804078 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9484 19:26:56.807424 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9485 19:26:56.814004 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9486 19:26:56.817412 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9487 19:26:56.820747 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9488 19:26:56.823946 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9489 19:26:56.830634 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9490 19:26:56.833867 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9491 19:26:56.837176 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9492 19:26:56.840564 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9493 19:26:56.847397 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9494 19:26:56.850591 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9495 19:26:56.853719 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9496 19:26:56.860608 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9497 19:26:56.863937 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9498 19:26:56.867288 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9499 19:26:56.873920 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9500 19:26:56.877225 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9501 19:26:56.884024 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9502 19:26:56.887079 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9503 19:26:56.894037 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9504 19:26:56.897432 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9505 19:26:56.900521 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9506 19:26:56.907384 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9507 19:26:56.910906 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9508 19:26:56.917453 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9509 19:26:56.920849 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9510 19:26:56.927830 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9511 19:26:56.930961 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9512 19:26:56.934118 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9513 19:26:56.940742 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9514 19:26:56.944009 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9515 19:26:56.950850 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9516 19:26:56.954220 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9517 19:26:56.960655 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9518 19:26:56.964097 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9519 19:26:56.967412 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9520 19:26:56.973915 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9521 19:26:56.977246 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9522 19:26:56.984120 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9523 19:26:56.987462 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9524 19:26:56.994068 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9525 19:26:56.997477 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9526 19:26:57.000855 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9527 19:26:57.007674 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9528 19:26:57.010779 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9529 19:26:57.017846 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9530 19:26:57.021102 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9531 19:26:57.024699 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9532 19:26:57.030768 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9533 19:26:57.034382 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9534 19:26:57.040999 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9535 19:26:57.044703 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9536 19:26:57.051220 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9537 19:26:57.054643 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9538 19:26:57.058156 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9539 19:26:57.064743 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9540 19:26:57.067859 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9541 19:26:57.074557 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9542 19:26:57.077838 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9543 19:26:57.084564 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9544 19:26:57.087882 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9545 19:26:57.091358 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9546 19:26:57.094841 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9547 19:26:57.101497 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9548 19:26:57.104299 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9549 19:26:57.107783 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9550 19:26:57.114410 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9551 19:26:57.117718 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9552 19:26:57.124315 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9553 19:26:57.127669 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9554 19:26:57.131439 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9555 19:26:57.137845 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9556 19:26:57.141110 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9557 19:26:57.147903 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9558 19:26:57.151305 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9559 19:26:57.154644 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9560 19:26:57.160972 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9561 19:26:57.164338 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9562 19:26:57.167661 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9563 19:26:57.174699 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9564 19:26:57.177960 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9565 19:26:57.181325 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9566 19:26:57.187946 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9567 19:26:57.191318 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9568 19:26:57.194706 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9569 19:26:57.198131 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9570 19:26:57.204892 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9571 19:26:57.208333 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9572 19:26:57.211656 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9573 19:26:57.217960 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9574 19:26:57.221329 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9575 19:26:57.225340 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9576 19:26:57.231474 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9577 19:26:57.234889 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9578 19:26:57.238109 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9579 19:26:57.245175 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9580 19:26:57.248545 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9581 19:26:57.255345 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9582 19:26:57.258488 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9583 19:26:57.261612 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9584 19:26:57.268455 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9585 19:26:57.271444 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9586 19:26:57.278511 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9587 19:26:57.281564 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9588 19:26:57.285271 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9589 19:26:57.291891 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9590 19:26:57.295313 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9591 19:26:57.298830 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9592 19:26:57.305536 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9593 19:26:57.308271 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9594 19:26:57.315563 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9595 19:26:57.318392 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9596 19:26:57.321674 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9597 19:26:57.328304 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9598 19:26:57.332279 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9599 19:26:57.335640 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9600 19:26:57.341835 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9601 19:26:57.345319 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9602 19:26:57.352448 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9603 19:26:57.355722 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9604 19:26:57.358535 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9605 19:26:57.365247 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9606 19:26:57.369088 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9607 19:26:57.375254 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9608 19:26:57.378533 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9609 19:26:57.382250 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9610 19:26:57.388406 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9611 19:26:57.392436 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9612 19:26:57.398705 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9613 19:26:57.401727 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9614 19:26:57.405155 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9615 19:26:57.411775 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9616 19:26:57.415450 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9617 19:26:57.418587 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9618 19:26:57.425084 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9619 19:26:57.428413 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9620 19:26:57.435044 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9621 19:26:57.438483 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9622 19:26:57.441851 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9623 19:26:57.448565 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9624 19:26:57.451974 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9625 19:26:57.458746 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9626 19:26:57.461719 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9627 19:26:57.465152 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9628 19:26:57.471789 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9629 19:26:57.475544 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9630 19:26:57.478733 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9631 19:26:57.485485 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9632 19:26:57.488763 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9633 19:26:57.495359 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9634 19:26:57.498419 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9635 19:26:57.501734 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9636 19:26:57.508506 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9637 19:26:57.511713 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9638 19:26:57.518457 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9639 19:26:57.522005 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9640 19:26:57.525491 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9641 19:26:57.531813 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9642 19:26:57.535504 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9643 19:26:57.541866 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9644 19:26:57.545454 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9645 19:26:57.551722 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9646 19:26:57.555198 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9647 19:26:57.558565 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9648 19:26:57.565359 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9649 19:26:57.568558 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9650 19:26:57.575255 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9651 19:26:57.578621 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9652 19:26:57.581914 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9653 19:26:57.588515 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9654 19:26:57.592324 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9655 19:26:57.598216 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9656 19:26:57.601597 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9657 19:26:57.605259 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9658 19:26:57.611819 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9659 19:26:57.615108 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9660 19:26:57.621781 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9661 19:26:57.625668 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9662 19:26:57.628506 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9663 19:26:57.635355 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9664 19:26:57.638476 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9665 19:26:57.645342 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9666 19:26:57.648604 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9667 19:26:57.655382 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9668 19:26:57.658333 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9669 19:26:57.661815 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9670 19:26:57.668617 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9671 19:26:57.671861 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9672 19:26:57.678422 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9673 19:26:57.681852 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9674 19:26:57.685199 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9675 19:26:57.692316 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9676 19:26:57.695093 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9677 19:26:57.698336 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9678 19:26:57.705195 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9679 19:26:57.708443 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9680 19:26:57.711780 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9681 19:26:57.715416 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9682 19:26:57.721545 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9683 19:26:57.724877 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9684 19:26:57.728112 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9685 19:26:57.734861 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9686 19:26:57.738231 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9687 19:26:57.744809 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9688 19:26:57.748422 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9689 19:26:57.751580 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9690 19:26:57.758604 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9691 19:26:57.761979 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9692 19:26:57.765254 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9693 19:26:57.771518 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9694 19:26:57.775016 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9695 19:26:57.779161 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9696 19:26:57.785117 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9697 19:26:57.788522 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9698 19:26:57.791907 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9699 19:26:57.798252 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9700 19:26:57.802101 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9701 19:26:57.805365 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9702 19:26:57.811678 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9703 19:26:57.815026 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9704 19:26:57.822033 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9705 19:26:57.825345 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9706 19:26:57.828756 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9707 19:26:57.835266 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9708 19:26:57.838550 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9709 19:26:57.841917 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9710 19:26:57.848722 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9711 19:26:57.851482 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9712 19:26:57.858205 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9713 19:26:57.861827 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9714 19:26:57.864923 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9715 19:26:57.871561 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9716 19:26:57.874961 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9717 19:26:57.878156 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9718 19:26:57.881971 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9719 19:26:57.888047 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9720 19:26:57.891392 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9721 19:26:57.894907 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9722 19:26:57.898020 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9723 19:26:57.905117 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9724 19:26:57.908039 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9725 19:26:57.911275 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9726 19:26:57.914645 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9727 19:26:57.921179 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9728 19:26:57.924928 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9729 19:26:57.928303 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9730 19:26:57.934808 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9731 19:26:57.938064 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9732 19:26:57.941421 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9733 19:26:57.948179 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9734 19:26:57.951591 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9735 19:26:57.957782 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9736 19:26:57.961182 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9737 19:26:57.964595 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9738 19:26:57.971651 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9739 19:26:57.974856 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9740 19:26:57.981440 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9741 19:26:57.984805 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9742 19:26:57.987994 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9743 19:26:57.994705 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9744 19:26:57.998148 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9745 19:26:58.004940 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9746 19:26:58.008217 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9747 19:26:58.011562 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9748 19:26:58.018356 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9749 19:26:58.021557 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9750 19:26:58.027779 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9751 19:26:58.031125 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9752 19:26:58.037783 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9753 19:26:58.041058 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9754 19:26:58.044283 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9755 19:26:58.051182 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9756 19:26:58.054844 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9757 19:26:58.061534 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9758 19:26:58.064374 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9759 19:26:58.067719 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9760 19:26:58.074577 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9761 19:26:58.077701 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9762 19:26:58.081464 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9763 19:26:58.087682 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9764 19:26:58.091402 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9765 19:26:58.097934 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9766 19:26:58.101398 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9767 19:26:58.108193 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9768 19:26:58.111631 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9769 19:26:58.114358 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9770 19:26:58.121177 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9771 19:26:58.124569 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9772 19:26:58.131312 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9773 19:26:58.134519 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9774 19:26:58.137873 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9775 19:26:58.144475 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9776 19:26:58.148145 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9777 19:26:58.154216 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9778 19:26:58.157922 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9779 19:26:58.160986 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9780 19:26:58.167964 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9781 19:26:58.170870 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9782 19:26:58.177879 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9783 19:26:58.181274 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9784 19:26:58.184345 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9785 19:26:58.190911 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9786 19:26:58.194113 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9787 19:26:58.201122 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9788 19:26:58.204455 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9789 19:26:58.207758 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9790 19:26:58.214451 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9791 19:26:58.217834 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9792 19:26:58.224461 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9793 19:26:58.227811 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9794 19:26:58.231366 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9795 19:26:58.238060 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9796 19:26:58.240741 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9797 19:26:58.247598 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9798 19:26:58.250854 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9799 19:26:58.257380 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9800 19:26:58.260762 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9801 19:26:58.264170 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9802 19:26:58.270941 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9803 19:26:58.274334 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9804 19:26:58.281042 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9805 19:26:58.284262 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9806 19:26:58.291002 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9807 19:26:58.293815 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9808 19:26:58.297567 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9809 19:26:58.304206 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9810 19:26:58.307575 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9811 19:26:58.314324 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9812 19:26:58.317255 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9813 19:26:58.323898 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9814 19:26:58.327327 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9815 19:26:58.330339 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9816 19:26:58.337168 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9817 19:26:58.340468 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9818 19:26:58.347165 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9819 19:26:58.350556 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9820 19:26:58.357278 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9821 19:26:58.360466 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9822 19:26:58.363875 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9823 19:26:58.370592 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9824 19:26:58.373972 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9825 19:26:58.380681 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9826 19:26:58.383518 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9827 19:26:58.390274 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9828 19:26:58.393759 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9829 19:26:58.397141 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9830 19:26:58.403784 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9831 19:26:58.406956 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9832 19:26:58.413649 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9833 19:26:58.416999 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9834 19:26:58.423690 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9835 19:26:58.427047 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9836 19:26:58.430379 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9837 19:26:58.437179 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9838 19:26:58.440541 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9839 19:26:58.446970 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9840 19:26:58.450342 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9841 19:26:58.456780 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9842 19:26:58.460617 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9843 19:26:58.463972 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9844 19:26:58.470538 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9845 19:26:58.473818 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9846 19:26:58.480461 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9847 19:26:58.483862 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9848 19:26:58.490393 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9849 19:26:58.493828 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9850 19:26:58.497234 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9851 19:26:58.503335 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9852 19:26:58.506685 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9853 19:26:58.513547 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9854 19:26:58.516811 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9855 19:26:58.523651 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9856 19:26:58.526983 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9857 19:26:58.533168 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9858 19:26:58.536954 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9859 19:26:58.543500 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9860 19:26:58.546644 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9861 19:26:58.553215 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9862 19:26:58.556407 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9863 19:26:58.563543 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9864 19:26:58.566572 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9865 19:26:58.569872 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9866 19:26:58.576477 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9867 19:26:58.579581 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9868 19:26:58.586234 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9869 19:26:58.589802 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9870 19:26:58.596233 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9871 19:26:58.599787 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9872 19:26:58.606396 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9873 19:26:58.609810 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9874 19:26:58.616635 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9875 19:26:58.619347 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9876 19:26:58.626131 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9877 19:26:58.629595 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9878 19:26:58.636404 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9879 19:26:58.639662 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9880 19:26:58.646468 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9881 19:26:58.649463 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9882 19:26:58.656069 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9883 19:26:58.656150 INFO: [APUAPC] vio 0
9884 19:26:58.663652 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9885 19:26:58.666945 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9886 19:26:58.670278 INFO: [APUAPC] D0_APC_0: 0x400510
9887 19:26:58.673703 INFO: [APUAPC] D0_APC_1: 0x0
9888 19:26:58.676816 INFO: [APUAPC] D0_APC_2: 0x1540
9889 19:26:58.680010 INFO: [APUAPC] D0_APC_3: 0x0
9890 19:26:58.683262 INFO: [APUAPC] D1_APC_0: 0xffffffff
9891 19:26:58.686472 INFO: [APUAPC] D1_APC_1: 0xffffffff
9892 19:26:58.690141 INFO: [APUAPC] D1_APC_2: 0x3fffff
9893 19:26:58.693107 INFO: [APUAPC] D1_APC_3: 0x0
9894 19:26:58.696687 INFO: [APUAPC] D2_APC_0: 0xffffffff
9895 19:26:58.699781 INFO: [APUAPC] D2_APC_1: 0xffffffff
9896 19:26:58.703625 INFO: [APUAPC] D2_APC_2: 0x3fffff
9897 19:26:58.706685 INFO: [APUAPC] D2_APC_3: 0x0
9898 19:26:58.710170 INFO: [APUAPC] D3_APC_0: 0xffffffff
9899 19:26:58.712932 INFO: [APUAPC] D3_APC_1: 0xffffffff
9900 19:26:58.716395 INFO: [APUAPC] D3_APC_2: 0x3fffff
9901 19:26:58.716482 INFO: [APUAPC] D3_APC_3: 0x0
9902 19:26:58.720155 INFO: [APUAPC] D4_APC_0: 0xffffffff
9903 19:26:58.723119 INFO: [APUAPC] D4_APC_1: 0xffffffff
9904 19:26:58.726508 INFO: [APUAPC] D4_APC_2: 0x3fffff
9905 19:26:58.730322 INFO: [APUAPC] D4_APC_3: 0x0
9906 19:26:58.733194 INFO: [APUAPC] D5_APC_0: 0xffffffff
9907 19:26:58.736627 INFO: [APUAPC] D5_APC_1: 0xffffffff
9908 19:26:58.739968 INFO: [APUAPC] D5_APC_2: 0x3fffff
9909 19:26:58.743467 INFO: [APUAPC] D5_APC_3: 0x0
9910 19:26:58.746234 INFO: [APUAPC] D6_APC_0: 0xffffffff
9911 19:26:58.750138 INFO: [APUAPC] D6_APC_1: 0xffffffff
9912 19:26:58.753752 INFO: [APUAPC] D6_APC_2: 0x3fffff
9913 19:26:58.756252 INFO: [APUAPC] D6_APC_3: 0x0
9914 19:26:58.759914 INFO: [APUAPC] D7_APC_0: 0xffffffff
9915 19:26:58.763207 INFO: [APUAPC] D7_APC_1: 0xffffffff
9916 19:26:58.766739 INFO: [APUAPC] D7_APC_2: 0x3fffff
9917 19:26:58.769528 INFO: [APUAPC] D7_APC_3: 0x0
9918 19:26:58.772955 INFO: [APUAPC] D8_APC_0: 0xffffffff
9919 19:26:58.776347 INFO: [APUAPC] D8_APC_1: 0xffffffff
9920 19:26:58.779771 INFO: [APUAPC] D8_APC_2: 0x3fffff
9921 19:26:58.783076 INFO: [APUAPC] D8_APC_3: 0x0
9922 19:26:58.786550 INFO: [APUAPC] D9_APC_0: 0xffffffff
9923 19:26:58.789848 INFO: [APUAPC] D9_APC_1: 0xffffffff
9924 19:26:58.793286 INFO: [APUAPC] D9_APC_2: 0x3fffff
9925 19:26:58.796756 INFO: [APUAPC] D9_APC_3: 0x0
9926 19:26:58.799360 INFO: [APUAPC] D10_APC_0: 0xffffffff
9927 19:26:58.802736 INFO: [APUAPC] D10_APC_1: 0xffffffff
9928 19:26:58.806404 INFO: [APUAPC] D10_APC_2: 0x3fffff
9929 19:26:58.809634 INFO: [APUAPC] D10_APC_3: 0x0
9930 19:26:58.813153 INFO: [APUAPC] D11_APC_0: 0xffffffff
9931 19:26:58.816548 INFO: [APUAPC] D11_APC_1: 0xffffffff
9932 19:26:58.819697 INFO: [APUAPC] D11_APC_2: 0x3fffff
9933 19:26:58.823026 INFO: [APUAPC] D11_APC_3: 0x0
9934 19:26:58.826152 INFO: [APUAPC] D12_APC_0: 0xffffffff
9935 19:26:58.829278 INFO: [APUAPC] D12_APC_1: 0xffffffff
9936 19:26:58.832985 INFO: [APUAPC] D12_APC_2: 0x3fffff
9937 19:26:58.836001 INFO: [APUAPC] D12_APC_3: 0x0
9938 19:26:58.839377 INFO: [APUAPC] D13_APC_0: 0xffffffff
9939 19:26:58.842718 INFO: [APUAPC] D13_APC_1: 0xffffffff
9940 19:26:58.846288 INFO: [APUAPC] D13_APC_2: 0x3fffff
9941 19:26:58.849737 INFO: [APUAPC] D13_APC_3: 0x0
9942 19:26:58.852956 INFO: [APUAPC] D14_APC_0: 0xffffffff
9943 19:26:58.856402 INFO: [APUAPC] D14_APC_1: 0xffffffff
9944 19:26:58.859802 INFO: [APUAPC] D14_APC_2: 0x3fffff
9945 19:26:58.862995 INFO: [APUAPC] D14_APC_3: 0x0
9946 19:26:58.866297 INFO: [APUAPC] D15_APC_0: 0xffffffff
9947 19:26:58.869590 INFO: [APUAPC] D15_APC_1: 0xffffffff
9948 19:26:58.872436 INFO: [APUAPC] D15_APC_2: 0x3fffff
9949 19:26:58.875924 INFO: [APUAPC] D15_APC_3: 0x0
9950 19:26:58.879276 INFO: [APUAPC] APC_CON: 0x4
9951 19:26:58.882720 INFO: [NOCDAPC] D0_APC_0: 0x0
9952 19:26:58.886168 INFO: [NOCDAPC] D0_APC_1: 0x0
9953 19:26:58.889645 INFO: [NOCDAPC] D1_APC_0: 0x0
9954 19:26:58.889727 INFO: [NOCDAPC] D1_APC_1: 0xfff
9955 19:26:58.892604 INFO: [NOCDAPC] D2_APC_0: 0x0
9956 19:26:58.895947 INFO: [NOCDAPC] D2_APC_1: 0xfff
9957 19:26:58.899472 INFO: [NOCDAPC] D3_APC_0: 0x0
9958 19:26:58.902811 INFO: [NOCDAPC] D3_APC_1: 0xfff
9959 19:26:58.906209 INFO: [NOCDAPC] D4_APC_0: 0x0
9960 19:26:58.909652 INFO: [NOCDAPC] D4_APC_1: 0xfff
9961 19:26:58.912858 INFO: [NOCDAPC] D5_APC_0: 0x0
9962 19:26:58.916067 INFO: [NOCDAPC] D5_APC_1: 0xfff
9963 19:26:58.919353 INFO: [NOCDAPC] D6_APC_0: 0x0
9964 19:26:58.922884 INFO: [NOCDAPC] D6_APC_1: 0xfff
9965 19:26:58.922966 INFO: [NOCDAPC] D7_APC_0: 0x0
9966 19:26:58.926170 INFO: [NOCDAPC] D7_APC_1: 0xfff
9967 19:26:58.929560 INFO: [NOCDAPC] D8_APC_0: 0x0
9968 19:26:58.932458 INFO: [NOCDAPC] D8_APC_1: 0xfff
9969 19:26:58.935933 INFO: [NOCDAPC] D9_APC_0: 0x0
9970 19:26:58.939330 INFO: [NOCDAPC] D9_APC_1: 0xfff
9971 19:26:58.943016 INFO: [NOCDAPC] D10_APC_0: 0x0
9972 19:26:58.946326 INFO: [NOCDAPC] D10_APC_1: 0xfff
9973 19:26:58.949650 INFO: [NOCDAPC] D11_APC_0: 0x0
9974 19:26:58.952871 INFO: [NOCDAPC] D11_APC_1: 0xfff
9975 19:26:58.956029 INFO: [NOCDAPC] D12_APC_0: 0x0
9976 19:26:58.959333 INFO: [NOCDAPC] D12_APC_1: 0xfff
9977 19:26:58.959412 INFO: [NOCDAPC] D13_APC_0: 0x0
9978 19:26:58.962900 INFO: [NOCDAPC] D13_APC_1: 0xfff
9979 19:26:58.965936 INFO: [NOCDAPC] D14_APC_0: 0x0
9980 19:26:58.969141 INFO: [NOCDAPC] D14_APC_1: 0xfff
9981 19:26:58.972598 INFO: [NOCDAPC] D15_APC_0: 0x0
9982 19:26:58.975954 INFO: [NOCDAPC] D15_APC_1: 0xfff
9983 19:26:58.979094 INFO: [NOCDAPC] APC_CON: 0x4
9984 19:26:58.982669 INFO: [APUAPC] set_apusys_apc done
9985 19:26:58.986083 INFO: [DEVAPC] devapc_init done
9986 19:26:58.989360 INFO: GICv3 without legacy support detected.
9987 19:26:58.992205 INFO: ARM GICv3 driver initialized in EL3
9988 19:26:58.999109 INFO: Maximum SPI INTID supported: 639
9989 19:26:59.002506 INFO: BL31: Initializing runtime services
9990 19:26:59.005923 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9991 19:26:59.009586 INFO: SPM: enable CPC mode
9992 19:26:59.015777 INFO: mcdi ready for mcusys-off-idle and system suspend
9993 19:26:59.019317 INFO: BL31: Preparing for EL3 exit to normal world
9994 19:26:59.022296 INFO: Entry point address = 0x80000000
9995 19:26:59.025497 INFO: SPSR = 0x8
9996 19:26:59.031636
9997 19:26:59.031713
9998 19:26:59.031777
9999 19:26:59.034313 Starting depthcharge on Spherion...
10000 19:26:59.034393
10001 19:26:59.034463 Wipe memory regions:
10002 19:26:59.034526
10003 19:26:59.035390 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10004 19:26:59.035533 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10005 19:26:59.035650 Setting prompt string to ['asurada:']
10006 19:26:59.035770 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10007 19:26:59.037670 [0x00000040000000, 0x00000054600000)
10008 19:26:59.159996
10009 19:26:59.160137 [0x00000054660000, 0x00000080000000)
10010 19:26:59.420800
10011 19:26:59.420959 [0x000000821a7280, 0x000000ffe64000)
10012 19:27:00.165546
10013 19:27:00.165678 [0x00000100000000, 0x00000240000000)
10014 19:27:02.056165
10015 19:27:02.059319 Initializing XHCI USB controller at 0x11200000.
10016 19:27:03.097717
10017 19:27:03.100402 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10018 19:27:03.100480
10019 19:27:03.100544
10020 19:27:03.100609
10021 19:27:03.100914 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10023 19:27:03.201215 asurada: tftpboot 192.168.201.1 13420368/tftp-deploy-03xmkh_w/kernel/image.itb 13420368/tftp-deploy-03xmkh_w/kernel/cmdline
10024 19:27:03.201385 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10025 19:27:03.201499 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10026 19:27:03.205795 tftpboot 192.168.201.1 13420368/tftp-deploy-03xmkh_w/kernel/image.itp-deploy-03xmkh_w/kernel/cmdline
10027 19:27:03.205900
10028 19:27:03.206003 Waiting for link
10029 19:27:03.363874
10030 19:27:03.364144 R8152: Initializing
10031 19:27:03.364303
10032 19:27:03.367582 Version 9 (ocp_data = 6010)
10033 19:27:03.367784
10034 19:27:03.370579 R8152: Done initializing
10035 19:27:03.370795
10036 19:27:03.370953 Adding net device
10037 19:27:05.319830
10038 19:27:05.320325 done.
10039 19:27:05.320691
10040 19:27:05.320997 MAC: 00:e0:4c:78:7a:aa
10041 19:27:05.321323
10042 19:27:05.323198 Sending DHCP discover... done.
10043 19:27:05.323614
10044 19:27:08.799190 Waiting for reply... done.
10045 19:27:08.799326
10046 19:27:08.799400 Sending DHCP request... done.
10047 19:27:08.801930
10048 19:27:08.802081 Waiting for reply... done.
10049 19:27:08.802157
10050 19:27:08.805467 My ip is 192.168.201.12
10051 19:27:08.805573
10052 19:27:08.808807 The DHCP server ip is 192.168.201.1
10053 19:27:08.808904
10054 19:27:08.812386 TFTP server IP predefined by user: 192.168.201.1
10055 19:27:08.812467
10056 19:27:08.819205 Bootfile predefined by user: 13420368/tftp-deploy-03xmkh_w/kernel/image.itb
10057 19:27:08.819287
10058 19:27:08.822316 Sending tftp read request... done.
10059 19:27:08.822425
10060 19:27:08.825503 Waiting for the transfer...
10061 19:27:08.825601
10062 19:27:09.086504 00000000 ################################################################
10063 19:27:09.086642
10064 19:27:09.335735 00080000 ################################################################
10065 19:27:09.335870
10066 19:27:09.587827 00100000 ################################################################
10067 19:27:09.588000
10068 19:27:09.850529 00180000 ################################################################
10069 19:27:09.850668
10070 19:27:10.108223 00200000 ################################################################
10071 19:27:10.108384
10072 19:27:10.373765 00280000 ################################################################
10073 19:27:10.373901
10074 19:27:10.632708 00300000 ################################################################
10075 19:27:10.632879
10076 19:27:10.898473 00380000 ################################################################
10077 19:27:10.898609
10078 19:27:11.164669 00400000 ################################################################
10079 19:27:11.164799
10080 19:27:11.420654 00480000 ################################################################
10081 19:27:11.420787
10082 19:27:11.681121 00500000 ################################################################
10083 19:27:11.681280
10084 19:27:11.935996 00580000 ################################################################
10085 19:27:11.936162
10086 19:27:12.181765 00600000 ################################################################
10087 19:27:12.181933
10088 19:27:12.440008 00680000 ################################################################
10089 19:27:12.440169
10090 19:27:12.706645 00700000 ################################################################
10091 19:27:12.706817
10092 19:27:12.961540 00780000 ################################################################
10093 19:27:12.961680
10094 19:27:13.212145 00800000 ################################################################
10095 19:27:13.212303
10096 19:27:13.479801 00880000 ################################################################
10097 19:27:13.479938
10098 19:27:13.732306 00900000 ################################################################
10099 19:27:13.732456
10100 19:27:13.994109 00980000 ################################################################
10101 19:27:13.994240
10102 19:27:14.241225 00a00000 ################################################################
10103 19:27:14.241358
10104 19:27:14.492482 00a80000 ################################################################
10105 19:27:14.492614
10106 19:27:14.744113 00b00000 ################################################################
10107 19:27:14.744249
10108 19:27:14.997829 00b80000 ################################################################
10109 19:27:14.997964
10110 19:27:15.247852 00c00000 ################################################################
10111 19:27:15.247987
10112 19:27:15.504705 00c80000 ################################################################
10113 19:27:15.504842
10114 19:27:15.756821 00d00000 ################################################################
10115 19:27:15.756967
10116 19:27:16.021686 00d80000 ################################################################
10117 19:27:16.021818
10118 19:27:16.287890 00e00000 ################################################################
10119 19:27:16.288032
10120 19:27:16.547063 00e80000 ################################################################
10121 19:27:16.547246
10122 19:27:16.808797 00f00000 ################################################################
10123 19:27:16.808971
10124 19:27:17.063503 00f80000 ################################################################
10125 19:27:17.063643
10126 19:27:17.309907 01000000 ################################################################
10127 19:27:17.310107
10128 19:27:17.569127 01080000 ################################################################
10129 19:27:17.569287
10130 19:27:17.818953 01100000 ################################################################
10131 19:27:17.819118
10132 19:27:18.062682 01180000 ################################################################
10133 19:27:18.062822
10134 19:27:18.312723 01200000 ################################################################
10135 19:27:18.312882
10136 19:27:18.560921 01280000 ################################################################
10137 19:27:18.561063
10138 19:27:18.803577 01300000 ################################################################
10139 19:27:18.803722
10140 19:27:19.058766 01380000 ################################################################
10141 19:27:19.058924
10142 19:27:19.314741 01400000 ################################################################
10143 19:27:19.314912
10144 19:27:19.562239 01480000 ################################################################
10145 19:27:19.562394
10146 19:27:19.810275 01500000 ################################################################
10147 19:27:19.810418
10148 19:27:20.056866 01580000 ################################################################
10149 19:27:20.057007
10150 19:27:20.303697 01600000 ################################################################
10151 19:27:20.303869
10152 19:27:20.556623 01680000 ################################################################
10153 19:27:20.556768
10154 19:27:20.809445 01700000 ################################################################
10155 19:27:20.809591
10156 19:27:21.056614 01780000 ################################################################
10157 19:27:21.056807
10158 19:27:21.303018 01800000 ################################################################
10159 19:27:21.303187
10160 19:27:21.549775 01880000 ################################################################
10161 19:27:21.549935
10162 19:27:21.795543 01900000 ################################################################
10163 19:27:21.795701
10164 19:27:22.044179 01980000 ################################################################
10165 19:27:22.044314
10166 19:27:22.304009 01a00000 ################################################################
10167 19:27:22.304144
10168 19:27:22.561480 01a80000 ################################################################
10169 19:27:22.561618
10170 19:27:22.813056 01b00000 ################################################################
10171 19:27:22.813215
10172 19:27:23.060647 01b80000 ################################################################
10173 19:27:23.060814
10174 19:27:23.322939 01c00000 ################################################################
10175 19:27:23.323076
10176 19:27:23.581130 01c80000 ################################################################
10177 19:27:23.581295
10178 19:27:23.838888 01d00000 ################################################################
10179 19:27:23.839050
10180 19:27:24.085993 01d80000 ################################################################
10181 19:27:24.086126
10182 19:27:24.338232 01e00000 ################################################################
10183 19:27:24.338442
10184 19:27:24.585716 01e80000 ################################################################
10185 19:27:24.585848
10186 19:27:24.832024 01f00000 ################################################################
10187 19:27:24.832168
10188 19:27:25.087723 01f80000 ################################################################
10189 19:27:25.087854
10190 19:27:25.359912 02000000 ################################################################
10191 19:27:25.360046
10192 19:27:25.619539 02080000 ################################################################
10193 19:27:25.619680
10194 19:27:25.919408 02100000 ################################################################
10195 19:27:25.919548
10196 19:27:26.220121 02180000 ################################################################
10197 19:27:26.220266
10198 19:27:26.516585 02200000 ################################################################
10199 19:27:26.516723
10200 19:27:26.811650 02280000 ################################################################
10201 19:27:26.811788
10202 19:27:27.103073 02300000 ################################################################
10203 19:27:27.103213
10204 19:27:27.399406 02380000 ################################################################
10205 19:27:27.399552
10206 19:27:27.684739 02400000 ################################################################
10207 19:27:27.684875
10208 19:27:27.972822 02480000 ################################################################
10209 19:27:27.972956
10210 19:27:28.259922 02500000 ################################################################
10211 19:27:28.260057
10212 19:27:28.536496 02580000 ################################################################
10213 19:27:28.536629
10214 19:27:28.804310 02600000 ################################################################
10215 19:27:28.804447
10216 19:27:29.078340 02680000 ################################################################
10217 19:27:29.078471
10218 19:27:29.330691 02700000 ################################################################
10219 19:27:29.330825
10220 19:27:29.590967 02780000 ################################################################
10221 19:27:29.591116
10222 19:27:29.849787 02800000 ################################################################
10223 19:27:29.849934
10224 19:27:30.101179 02880000 ################################################################
10225 19:27:30.101337
10226 19:27:30.362708 02900000 ################################################################
10227 19:27:30.362844
10228 19:27:30.629240 02980000 ################################################################
10229 19:27:30.629412
10230 19:27:30.892111 02a00000 ################################################################
10231 19:27:30.892291
10232 19:27:31.154165 02a80000 ################################################################
10233 19:27:31.154361
10234 19:27:31.417521 02b00000 ################################################################
10235 19:27:31.417680
10236 19:27:31.675761 02b80000 ################################################################
10237 19:27:31.675896
10238 19:27:31.937938 02c00000 ################################################################
10239 19:27:31.938100
10240 19:27:32.190177 02c80000 ################################################################
10241 19:27:32.190320
10242 19:27:32.446442 02d00000 ################################################################
10243 19:27:32.446579
10244 19:27:32.709005 02d80000 ################################################################
10245 19:27:32.709143
10246 19:27:32.972638 02e00000 ################################################################
10247 19:27:32.972787
10248 19:27:33.244238 02e80000 ################################################################
10249 19:27:33.244375
10250 19:27:33.501567 02f00000 ################################################################
10251 19:27:33.501702
10252 19:27:33.787331 02f80000 ################################################################
10253 19:27:33.787467
10254 19:27:34.057989 03000000 ################################################################
10255 19:27:34.058122
10256 19:27:34.333553 03080000 ################################################################
10257 19:27:34.333693
10258 19:27:34.628309 03100000 ################################################################
10259 19:27:34.628439
10260 19:27:34.912620 03180000 ################################################################
10261 19:27:34.912797
10262 19:27:35.189651 03200000 ################################################################
10263 19:27:35.189790
10264 19:27:35.482420 03280000 ################################################################
10265 19:27:35.482554
10266 19:27:35.769950 03300000 ################################################################
10267 19:27:35.770091
10268 19:27:36.061177 03380000 ################################################################
10269 19:27:36.061326
10270 19:27:36.326209 03400000 ################################################################
10271 19:27:36.326381
10272 19:27:36.589877 03480000 ################################################################
10273 19:27:36.590012
10274 19:27:36.860846 03500000 ################################################################
10275 19:27:36.861009
10276 19:27:37.136593 03580000 ################################################################
10277 19:27:37.136731
10278 19:27:37.418081 03600000 ################################################################
10279 19:27:37.418278
10280 19:27:37.693449 03680000 ################################################################
10281 19:27:37.693600
10282 19:27:37.956931 03700000 ################################################################
10283 19:27:37.957081
10284 19:27:38.221562 03780000 ################################################################
10285 19:27:38.221710
10286 19:27:38.498252 03800000 ################################################################
10287 19:27:38.498419
10288 19:27:38.748249 03880000 ################################################################
10289 19:27:38.748395
10290 19:27:39.014794 03900000 ################################################################
10291 19:27:39.014944
10292 19:27:39.283050 03980000 ################################################################
10293 19:27:39.283208
10294 19:27:39.560666 03a00000 ################################################################
10295 19:27:39.560809
10296 19:27:39.816683 03a80000 ################################################################
10297 19:27:39.816819
10298 19:27:40.068547 03b00000 ################################################################
10299 19:27:40.068705
10300 19:27:40.334641 03b80000 ################################################################
10301 19:27:40.334804
10302 19:27:40.596577 03c00000 ################################################################
10303 19:27:40.596734
10304 19:27:40.875768 03c80000 ################################################################
10305 19:27:40.875922
10306 19:27:41.167212 03d00000 ################################################################
10307 19:27:41.167371
10308 19:27:41.441847 03d80000 ################################################################
10309 19:27:41.442003
10310 19:27:41.715840 03e00000 ################################################################
10311 19:27:41.715991
10312 19:27:41.977850 03e80000 ################################################################
10313 19:27:41.978002
10314 19:27:42.246037 03f00000 ################################################################
10315 19:27:42.246190
10316 19:27:42.509671 03f80000 ################################################################
10317 19:27:42.509809
10318 19:27:42.768239 04000000 ################################################################
10319 19:27:42.768380
10320 19:27:43.039463 04080000 ################################################################
10321 19:27:43.039606
10322 19:27:43.301244 04100000 ################################################################
10323 19:27:43.301420
10324 19:27:43.573684 04180000 ################################################################
10325 19:27:43.573846
10326 19:27:43.832582 04200000 ################################################################
10327 19:27:43.832717
10328 19:27:44.099291 04280000 ################################################################
10329 19:27:44.099429
10330 19:27:44.352880 04300000 ################################################################
10331 19:27:44.353016
10332 19:27:44.607475 04380000 ################################################################
10333 19:27:44.607624
10334 19:27:44.887424 04400000 ################################################################
10335 19:27:44.887559
10336 19:27:45.149231 04480000 ################################################################
10337 19:27:45.149375
10338 19:27:45.430151 04500000 ################################################################
10339 19:27:45.430332
10340 19:27:45.714547 04580000 ################################################################
10341 19:27:45.714684
10342 19:27:45.969056 04600000 ################################################################
10343 19:27:45.969188
10344 19:27:46.012587 04680000 ########### done.
10345 19:27:46.013056
10346 19:27:46.016161 The bootfile was 74014238 bytes long.
10347 19:27:46.016636
10348 19:27:46.019035 Sending tftp read request... done.
10349 19:27:46.019499
10350 19:27:46.022546 Waiting for the transfer...
10351 19:27:46.023010
10352 19:27:46.023338 00000000 # done.
10353 19:27:46.023692
10354 19:27:46.028906 Command line loaded dynamically from TFTP file: 13420368/tftp-deploy-03xmkh_w/kernel/cmdline
10355 19:27:46.029419
10356 19:27:46.042388 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10357 19:27:46.045709
10358 19:27:46.046143 Loading FIT.
10359 19:27:46.046541
10360 19:27:46.048931 Image ramdisk-1 has 61054618 bytes.
10361 19:27:46.049353
10362 19:27:46.052122 Image fdt-1 has 47230 bytes.
10363 19:27:46.052563
10364 19:27:46.055944 Image kernel-1 has 12910355 bytes.
10365 19:27:46.056368
10366 19:27:46.062369 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10367 19:27:46.062799
10368 19:27:46.081989 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10369 19:27:46.082335
10370 19:27:46.085163 Choosing best match conf-1 for compat google,spherion-rev2.
10371 19:27:46.090128
10372 19:27:46.095035 Connected to device vid:did:rid of 1ae0:0028:00
10373 19:27:46.102721
10374 19:27:46.106096 tpm_get_response: command 0x17b, return code 0x0
10375 19:27:46.106421
10376 19:27:46.109329 ec_init: CrosEC protocol v3 supported (256, 248)
10377 19:27:46.113710
10378 19:27:46.116939 tpm_cleanup: add release locality here.
10379 19:27:46.117241
10380 19:27:46.117483 Shutting down all USB controllers.
10381 19:27:46.120657
10382 19:27:46.120957 Removing current net device
10383 19:27:46.121199
10384 19:27:46.127220 Exiting depthcharge with code 4 at timestamp: 76361759
10385 19:27:46.127523
10386 19:27:46.130432 LZMA decompressing kernel-1 to 0x821a6718
10387 19:27:46.130733
10388 19:27:46.133966 LZMA decompressing kernel-1 to 0x40000000
10389 19:27:47.728588
10390 19:27:47.729110 jumping to kernel
10391 19:27:47.731261 end: 2.2.4 bootloader-commands (duration 00:00:49) [common]
10392 19:27:47.731615 start: 2.2.5 auto-login-action (timeout 00:03:36) [common]
10393 19:27:47.731891 Setting prompt string to ['Linux version [0-9]']
10394 19:27:47.732143 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10395 19:27:47.732393 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10396 19:27:47.810519
10397 19:27:47.813768 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10398 19:27:47.817657 start: 2.2.5.1 login-action (timeout 00:03:36) [common]
10399 19:27:47.818122 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10400 19:27:47.818524 Setting prompt string to []
10401 19:27:47.818926 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10402 19:27:47.819330 Using line separator: #'\n'#
10403 19:27:47.819865 No login prompt set.
10404 19:27:47.820209 Parsing kernel messages
10405 19:27:47.820508 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10406 19:27:47.821036 [login-action] Waiting for messages, (timeout 00:03:36)
10407 19:27:47.821382 Waiting using forced prompt support (timeout 00:01:48)
10408 19:27:47.836964 [ 0.000000] Linux version 6.1.86-cip19 (KernelCI@build-j170728-arm64-gcc-10-defconfig-arm64-chromebook-wrkxq) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Apr 18 19:05:54 UTC 2024
10409 19:27:47.840244 [ 0.000000] random: crng init done
10410 19:27:47.847546 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10411 19:27:47.848219 [ 0.000000] efi: UEFI not found.
10412 19:27:47.857495 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10413 19:27:47.863835 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10414 19:27:47.873741 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10415 19:27:47.883564 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10416 19:27:47.890111 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10417 19:27:47.893282 [ 0.000000] printk: bootconsole [mtk8250] enabled
10418 19:27:47.902192 [ 0.000000] NUMA: No NUMA configuration found
10419 19:27:47.908716 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10420 19:27:47.915190 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10421 19:27:47.915272 [ 0.000000] Zone ranges:
10422 19:27:47.922336 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10423 19:27:47.924974 [ 0.000000] DMA32 empty
10424 19:27:47.931996 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10425 19:27:47.935135 [ 0.000000] Movable zone start for each node
10426 19:27:47.938712 [ 0.000000] Early memory node ranges
10427 19:27:47.944991 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10428 19:27:47.951750 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10429 19:27:47.958205 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10430 19:27:47.964875 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10431 19:27:47.971353 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10432 19:27:47.978550 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10433 19:27:48.035043 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10434 19:27:48.041638 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10435 19:27:48.048220 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10436 19:27:48.051403 [ 0.000000] psci: probing for conduit method from DT.
10437 19:27:48.058000 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10438 19:27:48.061344 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10439 19:27:48.068191 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10440 19:27:48.071319 [ 0.000000] psci: SMC Calling Convention v1.2
10441 19:27:48.077987 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10442 19:27:48.081258 [ 0.000000] Detected VIPT I-cache on CPU0
10443 19:27:48.088253 [ 0.000000] CPU features: detected: GIC system register CPU interface
10444 19:27:48.094927 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10445 19:27:48.101488 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10446 19:27:48.108034 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10447 19:27:48.114702 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10448 19:27:48.121593 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10449 19:27:48.127900 [ 0.000000] alternatives: applying boot alternatives
10450 19:27:48.131211 [ 0.000000] Fallback order for Node 0: 0
10451 19:27:48.140955 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10452 19:27:48.141231 [ 0.000000] Policy zone: Normal
10453 19:27:48.157785 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10454 19:27:48.167498 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10455 19:27:48.179101 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10456 19:27:48.189331 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10457 19:27:48.196016 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10458 19:27:48.199458 <6>[ 0.000000] software IO TLB: area num 8.
10459 19:27:48.256021 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10460 19:27:48.405498 <6>[ 0.000000] Memory: 7904944K/8385536K available (18048K kernel code, 4118K rwdata, 22288K rodata, 8448K init, 616K bss, 447824K reserved, 32768K cma-reserved)
10461 19:27:48.412226 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10462 19:27:48.418808 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10463 19:27:48.422372 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10464 19:27:48.429049 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10465 19:27:48.435555 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10466 19:27:48.438649 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10467 19:27:48.448936 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10468 19:27:48.455323 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10469 19:27:48.458427 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10470 19:27:48.466138 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10471 19:27:48.469407 <6>[ 0.000000] GICv3: 608 SPIs implemented
10472 19:27:48.476740 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10473 19:27:48.480048 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10474 19:27:48.483147 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10475 19:27:48.492812 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10476 19:27:48.502733 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10477 19:27:48.516099 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10478 19:27:48.522523 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10479 19:27:48.532149 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10480 19:27:48.545216 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10481 19:27:48.551922 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10482 19:27:48.558566 <6>[ 0.009182] Console: colour dummy device 80x25
10483 19:27:48.568258 <6>[ 0.013930] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10484 19:27:48.571920 <6>[ 0.024372] pid_max: default: 32768 minimum: 301
10485 19:27:48.578021 <6>[ 0.029275] LSM: Security Framework initializing
10486 19:27:48.584938 <6>[ 0.034213] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10487 19:27:48.595075 <6>[ 0.042077] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10488 19:27:48.601261 <6>[ 0.051498] cblist_init_generic: Setting adjustable number of callback queues.
10489 19:27:48.608428 <6>[ 0.058941] cblist_init_generic: Setting shift to 3 and lim to 1.
10490 19:27:48.618070 <6>[ 0.065281] cblist_init_generic: Setting adjustable number of callback queues.
10491 19:27:48.624553 <6>[ 0.072753] cblist_init_generic: Setting shift to 3 and lim to 1.
10492 19:27:48.628234 <6>[ 0.079196] rcu: Hierarchical SRCU implementation.
10493 19:27:48.634501 <6>[ 0.084212] rcu: Max phase no-delay instances is 1000.
10494 19:27:48.641470 <6>[ 0.091235] EFI services will not be available.
10495 19:27:48.644504 <6>[ 0.096192] smp: Bringing up secondary CPUs ...
10496 19:27:48.652405 <6>[ 0.101236] Detected VIPT I-cache on CPU1
10497 19:27:48.659635 <6>[ 0.101305] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10498 19:27:48.666149 <6>[ 0.101338] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10499 19:27:48.669664 <6>[ 0.101669] Detected VIPT I-cache on CPU2
10500 19:27:48.676125 <6>[ 0.101722] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10501 19:27:48.686140 <6>[ 0.101741] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10502 19:27:48.689173 <6>[ 0.102002] Detected VIPT I-cache on CPU3
10503 19:27:48.695884 <6>[ 0.102051] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10504 19:27:48.702525 <6>[ 0.102066] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10505 19:27:48.705731 <6>[ 0.102370] CPU features: detected: Spectre-v4
10506 19:27:48.712459 <6>[ 0.102377] CPU features: detected: Spectre-BHB
10507 19:27:48.715651 <6>[ 0.102382] Detected PIPT I-cache on CPU4
10508 19:27:48.722028 <6>[ 0.102441] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10509 19:27:48.728853 <6>[ 0.102457] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10510 19:27:48.735877 <6>[ 0.102754] Detected PIPT I-cache on CPU5
10511 19:27:48.741778 <6>[ 0.102816] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10512 19:27:48.748683 <6>[ 0.102832] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10513 19:27:48.751996 <6>[ 0.103113] Detected PIPT I-cache on CPU6
10514 19:27:48.758866 <6>[ 0.103178] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10515 19:27:48.765500 <6>[ 0.103193] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10516 19:27:48.772177 <6>[ 0.103488] Detected PIPT I-cache on CPU7
10517 19:27:48.778495 <6>[ 0.103553] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10518 19:27:48.785392 <6>[ 0.103569] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10519 19:27:48.788323 <6>[ 0.103616] smp: Brought up 1 node, 8 CPUs
10520 19:27:48.795024 <6>[ 0.244974] SMP: Total of 8 processors activated.
10521 19:27:48.798150 <6>[ 0.249895] CPU features: detected: 32-bit EL0 Support
10522 19:27:48.808428 <6>[ 0.255258] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10523 19:27:48.814824 <6>[ 0.264058] CPU features: detected: Common not Private translations
10524 19:27:48.818573 <6>[ 0.270534] CPU features: detected: CRC32 instructions
10525 19:27:48.825127 <6>[ 0.275919] CPU features: detected: RCpc load-acquire (LDAPR)
10526 19:27:48.831682 <6>[ 0.281879] CPU features: detected: LSE atomic instructions
10527 19:27:48.838064 <6>[ 0.287660] CPU features: detected: Privileged Access Never
10528 19:27:48.841408 <6>[ 0.293440] CPU features: detected: RAS Extension Support
10529 19:27:48.851485 <6>[ 0.299049] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10530 19:27:48.854751 <6>[ 0.306269] CPU: All CPU(s) started at EL2
10531 19:27:48.861404 <6>[ 0.310585] alternatives: applying system-wide alternatives
10532 19:27:48.870428 <6>[ 0.321364] devtmpfs: initialized
10533 19:27:48.882858 <6>[ 0.330229] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10534 19:27:48.892711 <6>[ 0.340193] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10535 19:27:48.899668 <6>[ 0.348447] pinctrl core: initialized pinctrl subsystem
10536 19:27:48.902512 <6>[ 0.355087] DMI not present or invalid.
10537 19:27:48.909508 <6>[ 0.359497] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10538 19:27:48.919316 <6>[ 0.366378] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10539 19:27:48.925793 <6>[ 0.373968] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10540 19:27:48.935357 <6>[ 0.382199] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10541 19:27:48.939209 <6>[ 0.390437] audit: initializing netlink subsys (disabled)
10542 19:27:48.948876 <5>[ 0.396133] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10543 19:27:48.955415 <6>[ 0.396827] thermal_sys: Registered thermal governor 'step_wise'
10544 19:27:48.961805 <6>[ 0.404094] thermal_sys: Registered thermal governor 'power_allocator'
10545 19:27:48.965109 <6>[ 0.410350] cpuidle: using governor menu
10546 19:27:48.971761 <6>[ 0.421312] NET: Registered PF_QIPCRTR protocol family
10547 19:27:48.978708 <6>[ 0.426805] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10548 19:27:48.985079 <6>[ 0.433906] ASID allocator initialised with 32768 entries
10549 19:27:48.988471 <6>[ 0.440463] Serial: AMBA PL011 UART driver
10550 19:27:48.998126 <4>[ 0.449191] Trying to register duplicate clock ID: 134
10551 19:27:49.052232 <6>[ 0.506788] KASLR enabled
10552 19:27:49.066817 <6>[ 0.514480] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10553 19:27:49.074103 <6>[ 0.521494] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10554 19:27:49.080544 <6>[ 0.527985] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10555 19:27:49.087178 <6>[ 0.534986] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10556 19:27:49.093485 <6>[ 0.541473] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10557 19:27:49.099816 <6>[ 0.548479] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10558 19:27:49.106599 <6>[ 0.554967] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10559 19:27:49.113149 <6>[ 0.561969] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10560 19:27:49.116214 <6>[ 0.569407] ACPI: Interpreter disabled.
10561 19:27:49.124930 <6>[ 0.575811] iommu: Default domain type: Translated
10562 19:27:49.131039 <6>[ 0.580921] iommu: DMA domain TLB invalidation policy: strict mode
10563 19:27:49.134757 <5>[ 0.587581] SCSI subsystem initialized
10564 19:27:49.141206 <6>[ 0.591750] usbcore: registered new interface driver usbfs
10565 19:27:49.147719 <6>[ 0.597480] usbcore: registered new interface driver hub
10566 19:27:49.151084 <6>[ 0.603028] usbcore: registered new device driver usb
10567 19:27:49.158209 <6>[ 0.609121] pps_core: LinuxPPS API ver. 1 registered
10568 19:27:49.168216 <6>[ 0.614314] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10569 19:27:49.171710 <6>[ 0.623664] PTP clock support registered
10570 19:27:49.174733 <6>[ 0.627904] EDAC MC: Ver: 3.0.0
10571 19:27:49.181836 <6>[ 0.633048] FPGA manager framework
10572 19:27:49.185648 <6>[ 0.636729] Advanced Linux Sound Architecture Driver Initialized.
10573 19:27:49.189536 <6>[ 0.643503] vgaarb: loaded
10574 19:27:49.196042 <6>[ 0.646675] clocksource: Switched to clocksource arch_sys_counter
10575 19:27:49.202224 <5>[ 0.653091] VFS: Disk quotas dquot_6.6.0
10576 19:27:49.209241 <6>[ 0.657277] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10577 19:27:49.212440 <6>[ 0.664466] pnp: PnP ACPI: disabled
10578 19:27:49.220368 <6>[ 0.671087] NET: Registered PF_INET protocol family
10579 19:27:49.227422 <6>[ 0.676683] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10580 19:27:49.241363 <6>[ 0.689023] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10581 19:27:49.251241 <6>[ 0.697839] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10582 19:27:49.257725 <6>[ 0.705812] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10583 19:27:49.267557 <6>[ 0.714514] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10584 19:27:49.274169 <6>[ 0.724272] TCP: Hash tables configured (established 65536 bind 65536)
10585 19:27:49.280738 <6>[ 0.731137] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10586 19:27:49.290664 <6>[ 0.738335] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10587 19:27:49.297457 <6>[ 0.746036] NET: Registered PF_UNIX/PF_LOCAL protocol family
10588 19:27:49.300429 <6>[ 0.752179] RPC: Registered named UNIX socket transport module.
10589 19:27:49.307505 <6>[ 0.758331] RPC: Registered udp transport module.
10590 19:27:49.310484 <6>[ 0.763265] RPC: Registered tcp transport module.
10591 19:27:49.316849 <6>[ 0.768196] RPC: Registered tcp NFSv4.1 backchannel transport module.
10592 19:27:49.323680 <6>[ 0.774862] PCI: CLS 0 bytes, default 64
10593 19:27:49.326964 <6>[ 0.779185] Unpacking initramfs...
10594 19:27:49.333947 <6>[ 0.782969] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10595 19:27:49.344112 <6>[ 0.791586] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10596 19:27:49.350563 <6>[ 0.800384] kvm [1]: IPA Size Limit: 40 bits
10597 19:27:49.354211 <6>[ 0.804910] kvm [1]: GICv3: no GICV resource entry
10598 19:27:49.357233 <6>[ 0.809932] kvm [1]: disabling GICv2 emulation
10599 19:27:49.364140 <6>[ 0.814619] kvm [1]: GIC system register CPU interface enabled
10600 19:27:49.370509 <6>[ 0.820775] kvm [1]: vgic interrupt IRQ18
10601 19:27:49.376790 <6>[ 0.826740] kvm [1]: VHE mode initialized successfully
10602 19:27:49.379916 <5>[ 0.833130] Initialise system trusted keyrings
10603 19:27:49.387306 <6>[ 0.837929] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10604 19:27:49.396626 <6>[ 0.847911] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10605 19:27:49.403087 <5>[ 0.854254] NFS: Registering the id_resolver key type
10606 19:27:49.406861 <5>[ 0.859556] Key type id_resolver registered
10607 19:27:49.413252 <5>[ 0.863971] Key type id_legacy registered
10608 19:27:49.420163 <6>[ 0.868250] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10609 19:27:49.426473 <6>[ 0.875173] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10610 19:27:49.433247 <6>[ 0.882894] 9p: Installing v9fs 9p2000 file system support
10611 19:27:49.469717 <5>[ 0.920320] Key type asymmetric registered
10612 19:27:49.473097 <5>[ 0.924650] Asymmetric key parser 'x509' registered
10613 19:27:49.482717 <6>[ 0.929789] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10614 19:27:49.486602 <6>[ 0.937405] io scheduler mq-deadline registered
10615 19:27:49.489571 <6>[ 0.942164] io scheduler kyber registered
10616 19:27:49.508096 <6>[ 0.959235] EINJ: ACPI disabled.
10617 19:27:49.540181 <4>[ 0.984833] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10618 19:27:49.550054 <4>[ 0.995468] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10619 19:27:49.565214 <6>[ 1.015982] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10620 19:27:49.572687 <6>[ 1.024011] printk: console [ttyS0] disabled
10621 19:27:49.601010 <6>[ 1.048645] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10622 19:27:49.607504 <6>[ 1.058131] printk: console [ttyS0] enabled
10623 19:27:49.610745 <6>[ 1.058131] printk: console [ttyS0] enabled
10624 19:27:49.617140 <6>[ 1.067024] printk: bootconsole [mtk8250] disabled
10625 19:27:49.620997 <6>[ 1.067024] printk: bootconsole [mtk8250] disabled
10626 19:27:49.627569 <6>[ 1.078066] SuperH (H)SCI(F) driver initialized
10627 19:27:49.630733 <6>[ 1.083343] msm_serial: driver initialized
10628 19:27:49.644351 <6>[ 1.092254] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10629 19:27:49.654613 <6>[ 1.100803] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10630 19:27:49.661103 <6>[ 1.109347] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10631 19:27:49.670899 <6>[ 1.117973] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10632 19:27:49.681074 <6>[ 1.126680] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10633 19:27:49.687846 <6>[ 1.135393] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10634 19:27:49.697368 <6>[ 1.143932] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10635 19:27:49.704189 <6>[ 1.152731] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10636 19:27:49.714584 <6>[ 1.161273] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10637 19:27:49.725900 <6>[ 1.176886] loop: module loaded
10638 19:27:49.732275 <6>[ 1.183009] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10639 19:27:49.754711 <4>[ 1.206011] mtk-pmic-keys: Failed to locate of_node [id: -1]
10640 19:27:49.761873 <6>[ 1.212843] megasas: 07.719.03.00-rc1
10641 19:27:49.771583 <6>[ 1.222462] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10642 19:27:49.779371 <6>[ 1.230060] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10643 19:27:49.796058 <6>[ 1.246845] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10644 19:27:49.852851 <6>[ 1.297107] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10645 19:27:52.011000 <6>[ 3.462745] Freeing initrd memory: 59620K
10646 19:27:52.023222 <6>[ 3.474323] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10647 19:27:52.033777 <6>[ 3.485425] tun: Universal TUN/TAP device driver, 1.6
10648 19:27:52.037640 <6>[ 3.491501] thunder_xcv, ver 1.0
10649 19:27:52.040783 <6>[ 3.495010] thunder_bgx, ver 1.0
10650 19:27:52.044124 <6>[ 3.498503] nicpf, ver 1.0
10651 19:27:52.054273 <6>[ 3.502513] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10652 19:27:52.057998 <6>[ 3.509989] hns3: Copyright (c) 2017 Huawei Corporation.
10653 19:27:52.061027 <6>[ 3.515576] hclge is initializing
10654 19:27:52.067470 <6>[ 3.519157] e1000: Intel(R) PRO/1000 Network Driver
10655 19:27:52.074354 <6>[ 3.524286] e1000: Copyright (c) 1999-2006 Intel Corporation.
10656 19:27:52.077552 <6>[ 3.530305] e1000e: Intel(R) PRO/1000 Network Driver
10657 19:27:52.084136 <6>[ 3.535520] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10658 19:27:52.090993 <6>[ 3.541705] igb: Intel(R) Gigabit Ethernet Network Driver
10659 19:27:52.097862 <6>[ 3.547355] igb: Copyright (c) 2007-2014 Intel Corporation.
10660 19:27:52.104285 <6>[ 3.553191] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10661 19:27:52.111236 <6>[ 3.559709] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10662 19:27:52.114221 <6>[ 3.566174] sky2: driver version 1.30
10663 19:27:52.120825 <6>[ 3.571187] VFIO - User Level meta-driver version: 0.3
10664 19:27:52.128073 <6>[ 3.579426] usbcore: registered new interface driver usb-storage
10665 19:27:52.134574 <6>[ 3.585863] usbcore: registered new device driver onboard-usb-hub
10666 19:27:52.143057 <6>[ 3.595045] mt6397-rtc mt6359-rtc: registered as rtc0
10667 19:27:52.153195 <6>[ 3.600515] mt6397-rtc mt6359-rtc: setting system clock to 2024-04-18T19:23:41 UTC (1713468221)
10668 19:27:52.156468 <6>[ 3.610085] i2c_dev: i2c /dev entries driver
10669 19:27:52.174060 <6>[ 3.622010] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10670 19:27:52.180394 <4>[ 3.630748] cpu cpu0: supply cpu not found, using dummy regulator
10671 19:27:52.186593 <4>[ 3.637186] cpu cpu1: supply cpu not found, using dummy regulator
10672 19:27:52.193164 <4>[ 3.643592] cpu cpu2: supply cpu not found, using dummy regulator
10673 19:27:52.200008 <4>[ 3.649990] cpu cpu3: supply cpu not found, using dummy regulator
10674 19:27:52.206414 <4>[ 3.656389] cpu cpu4: supply cpu not found, using dummy regulator
10675 19:27:52.213379 <4>[ 3.662787] cpu cpu5: supply cpu not found, using dummy regulator
10676 19:27:52.220047 <4>[ 3.669183] cpu cpu6: supply cpu not found, using dummy regulator
10677 19:27:52.226190 <4>[ 3.675595] cpu cpu7: supply cpu not found, using dummy regulator
10678 19:27:52.244385 <6>[ 3.696232] cpu cpu0: EM: created perf domain
10679 19:27:52.247786 <6>[ 3.701163] cpu cpu4: EM: created perf domain
10680 19:27:52.255029 <6>[ 3.706813] sdhci: Secure Digital Host Controller Interface driver
10681 19:27:52.261987 <6>[ 3.713242] sdhci: Copyright(c) Pierre Ossman
10682 19:27:52.268717 <6>[ 3.718196] Synopsys Designware Multimedia Card Interface Driver
10683 19:27:52.275661 <6>[ 3.724828] sdhci-pltfm: SDHCI platform and OF driver helper
10684 19:27:52.278729 <6>[ 3.724848] mmc0: CQHCI version 5.10
10685 19:27:52.285646 <6>[ 3.734712] ledtrig-cpu: registered to indicate activity on CPUs
10686 19:27:52.291942 <6>[ 3.741723] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10687 19:27:52.298414 <6>[ 3.748776] usbcore: registered new interface driver usbhid
10688 19:27:52.301770 <6>[ 3.754601] usbhid: USB HID core driver
10689 19:27:52.308517 <6>[ 3.758801] spi_master spi0: will run message pump with realtime priority
10690 19:27:52.354011 <6>[ 3.798986] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10691 19:27:52.373360 <6>[ 3.814734] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10692 19:27:52.377100 <6>[ 3.829513] mmc0: Command Queue Engine enabled
10693 19:27:52.383702 <6>[ 3.829990] cros-ec-spi spi0.0: Chrome EC device registered
10694 19:27:52.390255 <6>[ 3.834286] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10695 19:27:52.397476 <6>[ 3.847546] mmcblk0: mmc0:0001 DA4128 116 GiB
10696 19:27:52.407285 <6>[ 3.853926] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10697 19:27:52.413627 <6>[ 3.863625] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10698 19:27:52.417070 <6>[ 3.864294] NET: Registered PF_PACKET protocol family
10699 19:27:52.423963 <6>[ 3.870419] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10700 19:27:52.426719 <6>[ 3.874960] 9pnet: Installing 9P2000 support
10701 19:27:52.433750 <6>[ 3.880728] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10702 19:27:52.436943 <5>[ 3.884659] Key type dns_resolver registered
10703 19:27:52.443577 <6>[ 3.890367] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10704 19:27:52.450205 <6>[ 3.895155] registered taskstats version 1
10705 19:27:52.453342 <5>[ 3.905288] Loading compiled-in X.509 certificates
10706 19:27:52.482524 <4>[ 3.926957] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10707 19:27:52.492366 <4>[ 3.937674] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10708 19:27:52.498798 <3>[ 3.948205] debugfs: File 'uA_load' in directory '/' already present!
10709 19:27:52.505501 <3>[ 3.954905] debugfs: File 'min_uV' in directory '/' already present!
10710 19:27:52.512118 <3>[ 3.961513] debugfs: File 'max_uV' in directory '/' already present!
10711 19:27:52.518825 <3>[ 3.968178] debugfs: File 'constraint_flags' in directory '/' already present!
10712 19:27:52.529902 <3>[ 3.977969] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10713 19:27:52.541840 <6>[ 3.993361] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10714 19:27:52.548838 <6>[ 4.000128] xhci-mtk 11200000.usb: xHCI Host Controller
10715 19:27:52.555314 <6>[ 4.005635] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10716 19:27:52.565811 <6>[ 4.013489] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10717 19:27:52.572228 <6>[ 4.022947] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10718 19:27:52.578727 <6>[ 4.029171] xhci-mtk 11200000.usb: xHCI Host Controller
10719 19:27:52.585284 <6>[ 4.034677] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10720 19:27:52.591917 <6>[ 4.042344] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10721 19:27:52.599114 <6>[ 4.050192] hub 1-0:1.0: USB hub found
10722 19:27:52.602284 <6>[ 4.054222] hub 1-0:1.0: 1 port detected
10723 19:27:52.611904 <6>[ 4.058517] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10724 19:27:52.615218 <6>[ 4.067284] hub 2-0:1.0: USB hub found
10725 19:27:52.618885 <6>[ 4.071310] hub 2-0:1.0: 1 port detected
10726 19:27:52.628602 <6>[ 4.079597] mtk-msdc 11f70000.mmc: Got CD GPIO
10727 19:27:52.638387 <6>[ 4.086655] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10728 19:27:52.645216 <6>[ 4.094712] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10729 19:27:52.655136 <4>[ 4.102662] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10730 19:27:52.664870 <6>[ 4.112203] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10731 19:27:52.671465 <6>[ 4.120280] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10732 19:27:52.678390 <6>[ 4.128311] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10733 19:27:52.688064 <6>[ 4.136228] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10734 19:27:52.694763 <6>[ 4.144051] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10735 19:27:52.704522 <6>[ 4.151870] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10736 19:27:52.714894 <6>[ 4.162254] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10737 19:27:52.721412 <6>[ 4.170611] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10738 19:27:52.731358 <6>[ 4.178959] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10739 19:27:52.738153 <6>[ 4.187298] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10740 19:27:52.747807 <6>[ 4.195636] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10741 19:27:52.754297 <6>[ 4.203974] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10742 19:27:52.764441 <6>[ 4.212311] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10743 19:27:52.770844 <6>[ 4.220649] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10744 19:27:52.780813 <6>[ 4.228986] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10745 19:27:52.787574 <6>[ 4.237326] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10746 19:27:52.797853 <6>[ 4.245664] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10747 19:27:52.804441 <6>[ 4.254001] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10748 19:27:52.814208 <6>[ 4.262339] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10749 19:27:52.824269 <6>[ 4.270677] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10750 19:27:52.830706 <6>[ 4.279015] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10751 19:27:52.837898 <6>[ 4.287752] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10752 19:27:52.844381 <6>[ 4.294923] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10753 19:27:52.850893 <6>[ 4.301691] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10754 19:27:52.857560 <6>[ 4.308453] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10755 19:27:52.863872 <6>[ 4.315378] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10756 19:27:52.874010 <6>[ 4.322225] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10757 19:27:52.884155 <6>[ 4.331357] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10758 19:27:52.894264 <6>[ 4.340476] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10759 19:27:52.903659 <6>[ 4.349769] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10760 19:27:52.913574 <6>[ 4.359236] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10761 19:27:52.920129 <6>[ 4.368702] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10762 19:27:52.929942 <6>[ 4.377822] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10763 19:27:52.939800 <6>[ 4.387288] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10764 19:27:52.950152 <6>[ 4.396407] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10765 19:27:52.960082 <6>[ 4.405701] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10766 19:27:52.970132 <6>[ 4.415861] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10767 19:27:52.979597 <6>[ 4.427792] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10768 19:27:53.026234 <6>[ 4.474938] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10769 19:27:53.181524 <6>[ 4.632934] hub 1-1:1.0: USB hub found
10770 19:27:53.184169 <6>[ 4.637430] hub 1-1:1.0: 4 ports detected
10771 19:27:53.194518 <6>[ 4.646290] hub 1-1:1.0: USB hub found
10772 19:27:53.197696 <6>[ 4.650818] hub 1-1:1.0: 4 ports detected
10773 19:27:53.303745 <6>[ 4.755342] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10774 19:27:53.333363 <6>[ 4.785048] hub 2-1:1.0: USB hub found
10775 19:27:53.336701 <6>[ 4.789594] hub 2-1:1.0: 3 ports detected
10776 19:27:53.346310 <6>[ 4.797962] hub 2-1:1.0: USB hub found
10777 19:27:53.349419 <6>[ 4.802425] hub 2-1:1.0: 3 ports detected
10778 19:27:53.522231 <6>[ 4.970923] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10779 19:27:53.655115 <6>[ 5.106338] hub 1-1.4:1.0: USB hub found
10780 19:27:53.658160 <6>[ 5.110925] hub 1-1.4:1.0: 2 ports detected
10781 19:27:53.667852 <6>[ 5.119436] hub 1-1.4:1.0: USB hub found
10782 19:27:53.670991 <6>[ 5.124069] hub 1-1.4:1.0: 2 ports detected
10783 19:27:53.738725 <6>[ 5.187217] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10784 19:27:53.970239 <6>[ 5.418989] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10785 19:27:54.162805 <6>[ 5.610963] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10786 19:28:05.264303 <6>[ 16.720074] ALSA device list:
10787 19:28:05.270695 <6>[ 16.723375] No soundcards found.
10788 19:28:05.278633 <6>[ 16.731513] Freeing unused kernel memory: 8448K
10789 19:28:05.281943 <6>[ 16.737113] Run /init as init process
10790 19:28:05.314332 <6>[ 16.766929] NET: Registered PF_INET6 protocol family
10791 19:28:05.320832 <6>[ 16.773398] Segment Routing with IPv6
10792 19:28:05.324030 <6>[ 16.777344] In-situ OAM (IOAM) with IPv6
10793 19:28:05.368231 <30>[ 16.795191] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10794 19:28:05.375188 <30>[ 16.828282] systemd[1]: Detected architecture arm64.
10795 19:28:05.375271
10796 19:28:05.381620 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10797 19:28:05.381702
10798 19:28:05.381765
10799 19:28:05.397995 <30>[ 16.851265] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10800 19:28:05.542031 <30>[ 16.992316] systemd[1]: Queued start job for default target graphical.target.
10801 19:28:05.578693 <30>[ 17.028885] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10802 19:28:05.585595 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10803 19:28:05.585717
10804 19:28:05.605418 <30>[ 17.055346] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10805 19:28:05.611966 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10806 19:28:05.615235
10807 19:28:05.633902 <30>[ 17.084203] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10808 19:28:05.644050 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10809 19:28:05.644130
10810 19:28:05.661340 <30>[ 17.111446] systemd[1]: Created slice user.slice - User and Session Slice.
10811 19:28:05.667964 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10812 19:28:05.668048
10813 19:28:05.688410 <30>[ 17.135072] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10814 19:28:05.695131 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10815 19:28:05.695212
10816 19:28:05.717731 <30>[ 17.163759] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10817 19:28:05.723417 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10818 19:28:05.723503
10819 19:28:05.751487 <30>[ 17.191053] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10820 19:28:05.761395 <30>[ 17.210906] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10821 19:28:05.767660 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10822 19:28:05.767794
10823 19:28:05.785857 <30>[ 17.235429] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10824 19:28:05.795426 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10825 19:28:05.795859
10826 19:28:05.813690 <30>[ 17.263472] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10827 19:28:05.823719 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10828 19:28:05.824211
10829 19:28:05.837837 <30>[ 17.291093] systemd[1]: Reached target paths.target - Path Units.
10830 19:28:05.845048 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10831 19:28:05.848217
10832 19:28:05.865725 <30>[ 17.315431] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10833 19:28:05.872291 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10834 19:28:05.872703
10835 19:28:05.886408 <30>[ 17.338983] systemd[1]: Reached target slices.target - Slice Units.
10836 19:28:05.896365 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10837 19:28:05.896784
10838 19:28:05.910599 <30>[ 17.363474] systemd[1]: Reached target swap.target - Swaps.
10839 19:28:05.916997 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10840 19:28:05.917411
10841 19:28:05.938350 <30>[ 17.387496] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10842 19:28:05.947929 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10843 19:28:05.948348
10844 19:28:05.966076 <30>[ 17.415500] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10845 19:28:05.975689 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10846 19:28:05.976115
10847 19:28:05.995556 <30>[ 17.445242] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10848 19:28:06.005429 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10849 19:28:06.005917
10850 19:28:06.021734 <30>[ 17.471717] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10851 19:28:06.031326 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10852 19:28:06.031485
10853 19:28:06.049476 <30>[ 17.499668] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10854 19:28:06.056549 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10855 19:28:06.056654
10856 19:28:06.073842 <30>[ 17.523714] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10857 19:28:06.083920 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10858 19:28:06.084049
10859 19:28:06.102468 <30>[ 17.552239] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10860 19:28:06.112269 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10861 19:28:06.112401
10862 19:28:06.169426 <30>[ 17.619135] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10863 19:28:06.175779 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10864 19:28:06.175893
10865 19:28:06.196309 <30>[ 17.646502] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10866 19:28:06.203205 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10867 19:28:06.203318
10868 19:28:06.226119 <30>[ 17.675638] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10869 19:28:06.232365 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10870 19:28:06.232486
10871 19:28:06.260007 <30>[ 17.703569] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10872 19:28:06.290192 <30>[ 17.739786] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10873 19:28:06.300016 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10874 19:28:06.300153
10875 19:28:06.323078 <30>[ 17.772769] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10876 19:28:06.329227 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10877 19:28:06.329361
10878 19:28:06.373824 <30>[ 17.823768] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10879 19:28:06.383871 Startin<6>[ 17.833168] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10880 19:28:06.390544 g [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10881 19:28:06.390966
10882 19:28:06.415428 <30>[ 17.864922] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10883 19:28:06.421810 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10884 19:28:06.422224
10885 19:28:06.447105 <30>[ 17.896644] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10886 19:28:06.456736 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10887 19:28:06.457171
10888 19:28:06.497750 <30>[ 17.947226] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10889 19:28:06.504215 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10890 19:28:06.504641
10891 19:28:06.530746 <30>[ 17.980505] systemd[1]: Starting systemd-journald.service - Journal Service...
10892 19:28:06.537016 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10893 19:28:06.537460
10894 19:28:06.574741 <30>[ 18.024256] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10895 19:28:06.581198 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10896 19:28:06.581622
10897 19:28:06.610591 <30>[ 18.056601] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10898 19:28:06.617166 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10899 19:28:06.617610
10900 19:28:06.643224 <30>[ 18.092599] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10901 19:28:06.652945 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10902 19:28:06.653469
10903 19:28:06.694454 <30>[ 18.144573] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10904 19:28:06.701457 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10905 19:28:06.701550
10906 19:28:06.730285 <30>[ 18.180205] systemd[1]: Started systemd-journald.service - Journal Service.
10907 19:28:06.736947 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10908 19:28:06.737368
10909 19:28:06.759329 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10910 19:28:06.759759
10911 19:28:06.778123 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10912 19:28:06.778654
10913 19:28:06.793400 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10914 19:28:06.793898
10915 19:28:06.811210 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10916 19:28:06.811676
10917 19:28:06.832884 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10918 19:28:06.833520
10919 19:28:06.852062 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10920 19:28:06.852485
10921 19:28:06.871708 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10922 19:28:06.872136
10923 19:28:06.891592 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10924 19:28:06.892032
10925 19:28:06.916163 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10926 19:28:06.916583
10927 19:28:06.940354 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10928 19:28:06.940777
10929 19:28:06.963231 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10930 19:28:06.963654
10931 19:28:06.988440 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10932 19:28:06.988958
10933 19:28:07.006759 See 'systemctl status systemd-remount-fs.service' for details.
10934 19:28:07.007175
10935 19:28:07.026768 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10936 19:28:07.027196
10937 19:28:07.048185 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10938 19:28:07.048608
10939 19:28:07.085962 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10940 19:28:07.086473
10941 19:28:07.103415 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10942 19:28:07.103837
10943 19:28:07.117738 <46>[ 18.567607] systemd-journald[181]: Received client request to flush runtime journal.
10944 19:28:07.132525 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10945 19:28:07.132944
10946 19:28:07.156816 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10947 19:28:07.157244
10948 19:28:07.180146 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10949 19:28:07.180566
10950 19:28:07.203955 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10951 19:28:07.204378
10952 19:28:07.222426 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10953 19:28:07.222893
10954 19:28:07.242874 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10955 19:28:07.243345
10956 19:28:07.262843 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10957 19:28:07.263282
10958 19:28:07.282880 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10959 19:28:07.283380
10960 19:28:07.325861 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10961 19:28:07.326392
10962 19:28:07.353480 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10963 19:28:07.353930
10964 19:28:07.370130 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10965 19:28:07.370603
10966 19:28:07.389549 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10967 19:28:07.389972
10968 19:28:07.442584 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10969 19:28:07.443069
10970 19:28:07.469178 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10971 19:28:07.469603
10972 19:28:07.489286 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10973 19:28:07.489711
10974 19:28:07.517566 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10975 19:28:07.518091
10976 19:28:07.543852 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10977 19:28:07.544391
10978 19:28:07.562998 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10979 19:28:07.563457
10980 19:28:07.616593 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10981 19:28:07.616750
10982 19:28:07.636306 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10983 19:28:07.636422
10984 19:28:07.671388 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10985 19:28:07.671515
10986 19:28:07.787224 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10987 19:28:07.787364
10988 19:28:07.805932 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10989 19:28:07.806087
10990 19:28:07.825679 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10991 19:28:07.825806
10992 19:28:07.836509 <6>[ 19.286418] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10993 19:28:07.842938 <6>[ 19.295160] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10994 19:28:07.852608 <4>[ 19.295544] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10995 19:28:07.859737 <6>[ 19.304433] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10996 19:28:07.866256 <6>[ 19.304830] remoteproc remoteproc0: scp is available
10997 19:28:07.869541 <6>[ 19.305136] remoteproc remoteproc0: powering up scp
10998 19:28:07.879433 <6>[ 19.305141] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10999 19:28:07.886136 <6>[ 19.305155] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
11000 19:28:07.892777 <4>[ 19.326868] elants_i2c 4-0010: supply vccio not found, using dummy regulator
11001 19:28:07.902250 <6>[ 19.329740] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
11002 19:28:07.905591 <6>[ 19.338591] mc: Linux media interface: v0.10
11003 19:28:07.912616 <3>[ 19.343225] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11004 19:28:07.922489 <3>[ 19.343242] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11005 19:28:07.929320 <3>[ 19.343246] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11006 19:28:07.935635 <6>[ 19.343482] usbcore: registered new device driver r8152-cfgselector
11007 19:28:07.945656 <3>[ 19.352489] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11008 19:28:07.949248 <6>[ 19.397537] videodev: Linux video capture interface: v2.00
11009 19:28:07.958676 <3>[ 19.403621] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11010 19:28:07.965236 <3>[ 19.416952] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11011 19:28:07.975482 <3>[ 19.425147] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11012 19:28:07.982000 <6>[ 19.431377] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
11013 19:28:07.988549 <6>[ 19.431386] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
11014 19:28:07.998389 <3>[ 19.433360] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11015 19:28:08.008931 [[0;32m OK [<6>[ 19.434124] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
11016 19:28:08.021760 0m] Started [0;<6>[ 19.434463] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
11017 19:28:08.028381 1;39mfstrim.time<6>[ 19.441768] remoteproc remoteproc0: remote processor scp is now up
11018 19:28:08.038221 r[0m - Discard <3>[ 19.448881] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11019 19:28:08.048279 unused blocks on<6>[ 19.449174] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
11020 19:28:08.048442 ce a week.
11021 19:28:08.048530
11022 19:28:08.058262 <6>[ 19.449196] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
11023 19:28:08.064899 <6>[ 19.469752] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
11024 19:28:08.071203 <6>[ 19.472606] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
11025 19:28:08.078139 <6>[ 19.472614] pci_bus 0000:00: root bus resource [bus 00-ff]
11026 19:28:08.084641 <6>[ 19.472623] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
11027 19:28:08.094819 <6>[ 19.472628] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
11028 19:28:08.101452 <6>[ 19.472686] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
11029 19:28:08.107649 <6>[ 19.472723] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
11030 19:28:08.114148 <6>[ 19.472870] pci 0000:00:00.0: supports D1 D2
11031 19:28:08.120976 <6>[ 19.472876] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11032 19:28:08.127708 <6>[ 19.474461] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
11033 19:28:08.134750 <6>[ 19.474593] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
11034 19:28:08.144277 <6>[ 19.474645] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
11035 19:28:08.150963 <6>[ 19.476986] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
11036 19:28:08.157748 <6>[ 19.477012] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11037 19:28:08.164577 <6>[ 19.477163] pci 0000:01:00.0: supports D1 D2
11038 19:28:08.170891 <6>[ 19.477169] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11039 19:28:08.177298 <3>[ 19.479102] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11040 19:28:08.183790 <6>[ 19.482780] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11041 19:28:08.194020 <6>[ 19.482815] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11042 19:28:08.200622 <6>[ 19.482822] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11043 19:28:08.207151 <6>[ 19.482835] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11044 19:28:08.217351 <6>[ 19.482852] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11045 19:28:08.224477 <6>[ 19.482868] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11046 19:28:08.231548 <6>[ 19.482885] pci 0000:00:00.0: PCI bridge to [bus 01]
11047 19:28:08.238667 <6>[ 19.482893] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11048 19:28:08.245834 <6>[ 19.483079] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11049 19:28:08.249104 <6>[ 19.484287] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
11050 19:28:08.256198 <6>[ 19.484593] pcieport 0000:00:00.0: AER: enabled with IRQ 282
11051 19:28:08.266257 <6>[ 19.493143] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
11052 19:28:08.272603 <3>[ 19.496119] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11053 19:28:08.275904 <6>[ 19.497042] Bluetooth: Core ver 2.22
11054 19:28:08.282466 <6>[ 19.497214] NET: Registered PF_BLUETOOTH protocol family
11055 19:28:08.288841 <6>[ 19.497228] Bluetooth: HCI device and connection manager initialized
11056 19:28:08.292329 <6>[ 19.497340] Bluetooth: HCI socket layer initialized
11057 19:28:08.298893 <6>[ 19.497399] Bluetooth: L2CAP socket layer initialized
11058 19:28:08.305597 <6>[ 19.497485] Bluetooth: SCO socket layer initialized
11059 19:28:08.311927 <5>[ 19.510197] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11060 19:28:08.318928 <3>[ 19.515629] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11061 19:28:08.328889 <3>[ 19.515758] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11062 19:28:08.335576 <3>[ 19.515763] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11063 19:28:08.344910 <3>[ 19.515768] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11064 19:28:08.351990 <3>[ 19.515783] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11065 19:28:08.362447 <3>[ 19.515788] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11066 19:28:08.368877 <3>[ 19.515856] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11067 19:28:08.375452 <6>[ 19.524310] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
11068 19:28:08.385486 <6>[ 19.531266] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11069 19:28:08.388818 <6>[ 19.532749] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11070 19:28:08.395311 <6>[ 19.538798] usbcore: registered new interface driver btusb
11071 19:28:08.406041 <4>[ 19.540188] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11072 19:28:08.412932 <3>[ 19.540199] Bluetooth: hci0: Failed to load firmware file (-2)
11073 19:28:08.419901 <3>[ 19.540203] Bluetooth: hci0: Failed to set up firmware (-2)
11074 19:28:08.429755 <4>[ 19.540208] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11075 19:28:08.442653 <6>[ 19.545826] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11076 19:28:08.450234 <5>[ 19.549408] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11077 19:28:08.457313 <5>[ 19.549684] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
11078 19:28:08.463946 <4>[ 19.549748] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11079 19:28:08.470418 <6>[ 19.549754] cfg80211: failed to load regulatory.db
11080 19:28:08.480579 <4>[ 19.564251] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
11081 19:28:08.487090 <6>[ 19.568087] usbcore: registered new interface driver uvcvideo
11082 19:28:08.494493 <4>[ 19.572446] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
11083 19:28:08.501619 <4>[ 19.602802] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
11084 19:28:08.508227 <4>[ 19.602802] Fallback method does not support PEC.
11085 19:28:08.514693 <6>[ 19.643844] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11086 19:28:08.524664 <3>[ 19.693968] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11087 19:28:08.531387 <6>[ 19.696668] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11088 19:28:08.537440 <3>[ 19.708065] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11089 19:28:08.548105 <3>[ 19.708809] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11090 19:28:08.551913 <6>[ 19.726850] mt7921e 0000:01:00.0: ASIC revision: 79610010
11091 19:28:08.558598 <6>[ 19.783025] r8152 2-1.3:1.0 eth0: v1.12.13
11092 19:28:08.564917 <3>[ 19.828837] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11093 19:28:08.575121 <3>[ 19.829690] power_supply sbs-5-000b: driver failed to report `capacity' property: -6
11094 19:28:08.581420 <6>[ 19.835539] usbcore: registered new interface driver r8152
11095 19:28:08.587973 <3>[ 19.869562] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11096 19:28:08.598249 <6>[ 19.886407] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
11097 19:28:08.598403 <6>[ 19.886407]
11098 19:28:08.604970 <6>[ 19.888058] usbcore: registered new interface driver cdc_ether
11099 19:28:08.614827 <3>[ 19.908076] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11100 19:28:08.621282 <6>[ 19.924365] usbcore: registered new interface driver r8153_ecm
11101 19:28:08.628320 <3>[ 19.954419] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11102 19:28:08.635001 <6>[ 19.986759] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
11103 19:28:08.644432 <3>[ 20.013440] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11104 19:28:08.651158 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11105 19:28:08.651258
11106 19:28:08.673664 [[0;32m OK [0m] Listening on [0;1;39mdbus.s<3>[ 20.123191] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11107 19:28:08.680187 ocket[…- D-Bus System Message Bus Socket.
11108 19:28:08.680298
11109 19:28:08.698602 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11110 19:28:08.698737
11111 19:28:08.709606 <6>[ 20.160115] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
11112 19:28:08.718590 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11113 19:28:08.718710
11114 19:28:08.758243 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11115 19:28:08.758434
11116 19:28:08.785695 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11117 19:28:08.785891
11118 19:28:08.826086 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11119 19:28:08.826230
11120 19:28:08.853869 [[0;32m OK [0m] Started [0;<46>[ 20.289890] systemd-journald[181]: Data hash table of /var/log/journal/c3f909ee3e324895ab90ff2613af9260/system.journal has a fill level at 75.1 (1537 of 2047 items, 524288 file size, 341 bytes per hash table item), suggesting rotation.
11121 19:28:08.869982 1;39mdbus.servic<46>[ 20.311462] systemd-journald[181]: /var/log/journal/c3f909ee3e324895ab90ff2613af9260/system.journal: Journal header limits reached or header out-of-date, rotating.
11122 19:28:08.873261 e[0m - D-Bus System Message Bus.
11123 19:28:08.873364
11124 19:28:08.906553 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11125 19:28:08.906702
11126 19:28:08.978863 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11127 19:28:08.979000
11128 19:28:09.001522 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11129 19:28:09.001654
11130 19:28:09.021440 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11131 19:28:09.021572
11132 19:28:09.041892 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11133 19:28:09.042030
11134 19:28:09.098156 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11135 19:28:09.098365
11136 19:28:09.118873 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11137 19:28:09.119025
11138 19:28:09.138572 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11139 19:28:09.138711
11140 19:28:09.154162 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11141 19:28:09.154282
11142 19:28:09.173596 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11143 19:28:09.173739
11144 19:28:09.226524 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11145 19:28:09.226669
11146 19:28:09.251938 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11147 19:28:09.252089
11148 19:28:09.277756 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11149 19:28:09.277905
11150 19:28:09.343752 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11151 19:28:09.343905
11152 19:28:09.363522 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11153 19:28:09.363666
11154 19:28:09.387558 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11155 19:28:09.387700
11156 19:28:09.430509
11157 19:28:09.430663
11158 19:28:09.433608 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11159 19:28:09.433694
11160 19:28:09.437001 debian-bookworm-arm64 login: root (automatic login)
11161 19:28:09.437085
11162 19:28:09.437169
11163 19:28:09.450457 Linux debian-bookworm-arm64 6.1.86-cip19 #1 SMP PREEMPT Thu Apr 18 19:05:54 UTC 2024 aarch64
11164 19:28:09.450553
11165 19:28:09.456954 The programs included with the Debian GNU/Linux system are free software;
11166 19:28:09.463192 the exact distribution terms for each program are described in the
11167 19:28:09.467024 individual files in /usr/share/doc/*/copyright.
11168 19:28:09.467109
11169 19:28:09.473119 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11170 19:28:09.476553 permitted by applicable law.
11171 19:28:09.476942 Matched prompt #10: / #
11173 19:28:09.477164 Setting prompt string to ['/ #']
11174 19:28:09.477275 end: 2.2.5.1 login-action (duration 00:00:22) [common]
11176 19:28:09.477496 end: 2.2.5 auto-login-action (duration 00:00:22) [common]
11177 19:28:09.477597 start: 2.2.6 expect-shell-connection (timeout 00:03:15) [common]
11178 19:28:09.477677 Setting prompt string to ['/ #']
11179 19:28:09.477773 Forcing a shell prompt, looking for ['/ #']
11181 19:28:09.528087 / #
11182 19:28:09.528274 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11183 19:28:09.528370 Waiting using forced prompt support (timeout 00:02:30)
11184 19:28:09.533700
11185 19:28:09.533988 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11186 19:28:09.534096 start: 2.2.7 export-device-env (timeout 00:03:15) [common]
11187 19:28:09.534205 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11188 19:28:09.534372 end: 2.2 depthcharge-retry (duration 00:01:45) [common]
11189 19:28:09.534473 end: 2 depthcharge-action (duration 00:01:45) [common]
11190 19:28:09.534576 start: 3 lava-test-retry (timeout 00:07:47) [common]
11191 19:28:09.534675 start: 3.1 lava-test-shell (timeout 00:07:47) [common]
11192 19:28:09.534758 Using namespace: common
11194 19:28:09.635190 / # #
11195 19:28:09.635367 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11196 19:28:09.635536 <6>[ 21.023054] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11197 19:28:09.640695 #
11198 19:28:09.640966 Using /lava-13420368
11200 19:28:09.741286 / # export SHELL=/bin/sh
11201 19:28:09.746519 export SHELL=/bin/sh
11203 19:28:09.847085 / # . /lava-13420368/environment
11204 19:28:09.852345 . /lava-13420368/environment
11206 19:28:09.952889 / # /lava-13420368/bin/lava-test-runner /lava-13420368/0
11207 19:28:09.953069 Test shell timeout: 10s (minimum of the action and connection timeout)
11208 19:28:09.958280 /lava-13420368/bin/lava-test-runner /lava-13420368/0
11209 19:28:09.987632 + export TESTRUN_ID=0_igt-kms-medi<8>[ 21.439980] <LAVA_SIGNAL_STARTRUN 0_igt-kms-mediatek 13420368_1.5.2.3.1>
11210 19:28:09.987961 Received signal: <STARTRUN> 0_igt-kms-mediatek 13420368_1.5.2.3.1
11211 19:28:09.988042 Starting test lava.0_igt-kms-mediatek (13420368_1.5.2.3.1)
11212 19:28:09.988128 Skipping test definition patterns.
11213 19:28:09.990868 atek
11214 19:28:09.994255 + cd /lava-13420368/0/tests/0_igt-kms-mediatek
11215 19:28:09.994396 + cat uuid
11216 19:28:09.997570 + UUID=13420368_1.5.2.3.1
11217 19:28:09.997654 + set +x
11218 19:28:10.013849 + IGT_FORCE_DRIVER=mediatek /usr/bin/igt-parser.sh core_auth core_getclient core_getstats core_getversion core_setmaster_<8>[ 21.465868] <LAVA_SIGNAL_TESTSET START core_auth>
11219 19:28:10.014156 Received signal: <TESTSET> START core_auth
11220 19:28:10.014238 Starting test_set core_auth
11221 19:28:10.023634 vs_auth drm_read kms_addfb_basic kms_atomic kms_flip_event_leak kms_prop_blob kms_setmode kms_vblank
11222 19:28:10.032384 <14>[ 21.486302] [IGT] core_auth: executing
11223 19:28:10.039383 IGT-Version: 1.2<14>[ 21.490697] [IGT] core_auth: starting subtest getclient-simple
11224 19:28:10.049198 8-ga44ebfe (aarc<14>[ 21.498261] [IGT] core_auth: finished subtest getclient-simple, SUCCESS
11225 19:28:10.052149 h64) (Linux: 6.1<14>[ 21.506783] [IGT] core_auth: exiting, ret=0
11226 19:28:10.055574 .86-cip19 aarch64)
11227 19:28:10.065743 Using IGT_SRANDOM=1713468239 for randomisati<8>[ 21.517018] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-simple RESULT=pass>
11228 19:28:10.065857 on
11229 19:28:10.066103 Received signal: <TESTCASE> TEST_CASE_ID=getclient-simple RESULT=pass
11231 19:28:10.069260 Starting subtest: getclient-simple
11232 19:28:10.072594 Opened device: /dev/dri/card0
11233 19:28:10.078819 [1mSubtest getclient-simple: SUCCESS (0.000s)[0m
11234 19:28:10.085295 <14>[ 21.538644] [IGT] core_auth: executing
11235 19:28:10.092393 IGT-Version: 1.2<14>[ 21.543086] [IGT] core_auth: starting subtest getclient-master-drop
11236 19:28:10.102025 8-ga44ebfe (aarc<14>[ 21.551092] [IGT] core_auth: finished subtest getclient-master-drop, SUCCESS
11237 19:28:10.105468 h64) (Linux: 6.1<14>[ 21.559780] [IGT] core_auth: exiting, ret=0
11238 19:28:10.108636 .86-cip19 aarch64)
11239 19:28:10.118871 Received signal: <TESTCASE> TEST_CASE_ID=getclient-master-drop RESULT=pass
11241 19:28:10.121962 Using IGT_SRANDOM=1713468239 for randomisati<8>[ 21.570160] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-master-drop RESULT=pass>
11242 19:28:10.122048 on
11243 19:28:10.125171 Starting subtest: getclient-master-drop
11244 19:28:10.128626 Opened device: /dev/dri/card0
11245 19:28:10.131836 [1mSubtest getclient-master-drop: SUCCESS (0.000s)[0m
11246 19:28:10.138810 <14>[ 21.592282] [IGT] core_auth: executing
11247 19:28:10.145154 IGT-Version: 1.2<14>[ 21.596699] [IGT] core_auth: starting subtest basic-auth
11248 19:28:10.151616 8-ga44ebfe (aarc<14>[ 21.603793] [IGT] core_auth: finished subtest basic-auth, SUCCESS
11249 19:28:10.158336 h64) (Linux: 6.1<14>[ 21.611484] [IGT] core_auth: exiting, ret=0
11250 19:28:10.162139 .86-cip19 aarch64)
11251 19:28:10.171677 Using IGT_SRANDOM=1713468239 for randomisati<8>[ 21.621696] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-auth RESULT=pass>
11252 19:28:10.171797 on
11253 19:28:10.172044 Received signal: <TESTCASE> TEST_CASE_ID=basic-auth RESULT=pass
11255 19:28:10.175358 Opened device: /dev/dri/card0
11256 19:28:10.178403 Starting subtest: basic-auth
11257 19:28:10.181710 [1mSubtest basic-auth: SUCCESS (0.000s)[0m
11258 19:28:10.189792 <14>[ 21.643608] [IGT] core_auth: executing
11259 19:28:10.196508 IGT-Version: 1.2<14>[ 21.648018] [IGT] core_auth: starting subtest many-magics
11260 19:28:10.200045 8-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11261 19:28:10.210045 Using IGT_SRANDOM=1713468239 for randomisati<14>[ 21.662001] [IGT] core_auth: finished subtest many-magics, SUCCESS
11262 19:28:10.212862 on
11263 19:28:10.216656 Opened devic<14>[ 21.669869] [IGT] core_auth: exiting, ret=0
11264 19:28:10.219843 e: /dev/dri/card0
11265 19:28:10.223058 Starting subtest: many-magics
11266 19:28:10.229493 Reopening devi<8>[ 21.680196] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=many-magics RESULT=pass>
11267 19:28:10.229770 Received signal: <TESTCASE> TEST_CASE_ID=many-magics RESULT=pass
11269 19:28:10.233405 ce failed after 1020 opens
11270 19:28:10.236606 [1m<8>[ 21.689750] <LAVA_SIGNAL_TESTSET STOP>
11271 19:28:10.236862 Received signal: <TESTSET> STOP
11272 19:28:10.236934 Closing test_set core_auth
11273 19:28:10.239874 Subtest many-magics: SUCCESS (0.007s)[0m
11274 19:28:10.269379 <14>[ 21.723399] [IGT] core_getclient: executing
11275 19:28:10.276394 IGT-Version: 1.2<14>[ 21.728318] [IGT] core_getclient: exiting, ret=0
11276 19:28:10.279625 8-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11277 19:28:10.289275 Using IGT_SR<8>[ 21.739332] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getclient RESULT=pass>
11278 19:28:10.289555 Received signal: <TESTCASE> TEST_CASE_ID=core_getclient RESULT=pass
11280 19:28:10.293152 ANDOM=1713468239 for randomisation
11281 19:28:10.293234 Opened device: /dev/dri/card0
11282 19:28:10.296282 SUCCESS (0.006s)
11283 19:28:10.320049 <14>[ 21.773947] [IGT] core_getstats: executing
11284 19:28:10.326660 IGT-Version: 1.2<14>[ 21.778823] [IGT] core_getstats: exiting, ret=0
11285 19:28:10.330024 8-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11286 19:28:10.340053 Using IGT_SR<8>[ 21.789308] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getstats RESULT=pass>
11287 19:28:10.340338 Received signal: <TESTCASE> TEST_CASE_ID=core_getstats RESULT=pass
11289 19:28:10.343418 ANDOM=1713468239 for randomisation
11290 19:28:10.343499 Opened device: /dev/dri/card0
11291 19:28:10.346628 SUCCESS (0.006s)
11292 19:28:10.384495 <14>[ 21.837973] [IGT] core_getversion: executing
11293 19:28:10.390920 IGT-Version: 1.2<14>[ 21.843147] [IGT] core_getversion: exiting, ret=0
11294 19:28:10.394110 8-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11295 19:28:10.404159 Using IGT_SR<8>[ 21.853891] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getversion RESULT=pass>
11296 19:28:10.404440 Received signal: <TESTCASE> TEST_CASE_ID=core_getversion RESULT=pass
11298 19:28:10.407473 ANDOM=1713468239 for randomisation
11299 19:28:10.410465 Opened device: /dev/dri/card0
11300 19:28:10.410547 SUCCESS (0.006s)
11301 19:28:10.436546 <14>[ 21.890344] [IGT] core_setmaster_vs_auth: executing
11302 19:28:10.443347 IGT-Version: 1.2<14>[ 21.896045] [IGT] core_setmaster_vs_auth: exiting, ret=0
11303 19:28:10.449808 8-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11304 19:28:10.456343 Using IGT_SR<8>[ 21.907583] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass>
11305 19:28:10.456620 Received signal: <TESTCASE> TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass
11307 19:28:10.460102 ANDOM=1713468239 for randomisation
11308 19:28:10.463124 Opened device: /dev/dri/card0
11309 19:28:10.466225 SUCCESS (0.007s)
11310 19:28:10.478510 <8>[ 21.932456] <LAVA_SIGNAL_TESTSET START drm_read>
11311 19:28:10.478796 Received signal: <TESTSET> START drm_read
11312 19:28:10.478880 Starting test_set drm_read
11313 19:28:10.496594 <14>[ 21.950172] [IGT] drm_read: executing
11314 19:28:10.503282 IGT-Version: 1.2<14>[ 21.954740] [IGT] drm_read: exiting, ret=77
11315 19:28:10.506451 8-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11316 19:28:10.512901 Using IGT_SR<8>[ 21.965138] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-buffer RESULT=skip>
11317 19:28:10.513195 Received signal: <TESTCASE> TEST_CASE_ID=invalid-buffer RESULT=skip
11319 19:28:10.516175 ANDOM=1713468239 for randomisation
11320 19:28:10.519514 Opened device: /dev/dri/card0
11321 19:28:10.526720 No KMS driver or no outputs, pipes: 16, outputs: 0
11322 19:28:10.529561 [1mSubtest invalid-buffer: SKIP (0.000s)[0m
11323 19:28:10.532901 <14>[ 21.987127] [IGT] drm_read: executing
11324 19:28:10.539496 IGT-Version: 1.2<14>[ 21.992091] [IGT] drm_read: exiting, ret=77
11325 19:28:10.542780 8-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11326 19:28:10.553070 Using IGT_SR<8>[ 22.002104] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=fault-buffer RESULT=skip>
11327 19:28:10.553347 Received signal: <TESTCASE> TEST_CASE_ID=fault-buffer RESULT=skip
11329 19:28:10.555893 ANDOM=1713468239 for randomisation
11330 19:28:10.555979 Opened device: /dev/dri/card0
11331 19:28:10.562692 No KMS driver or no outputs, pipes: 16, outputs: 0
11332 19:28:10.569875 [1mSubtest fault-buffer: SKIP (0.000s)[<14>[ 22.023703] [IGT] drm_read: executing
11333 19:28:10.569972 0m
11334 19:28:10.576222 IGT-Version: 1.2<14>[ 22.028695] [IGT] drm_read: exiting, ret=77
11335 19:28:10.579453 8-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11336 19:28:10.589493 Using IGT_SR<8>[ 22.039265] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-block RESULT=skip>
11337 19:28:10.589791 Received signal: <TESTCASE> TEST_CASE_ID=empty-block RESULT=skip
11339 19:28:10.592713 ANDOM=1713468239 for randomisation
11340 19:28:10.592798 Opened device: /dev/dri/card0
11341 19:28:10.599260 No KMS driver or no outputs, pipes: 16, outputs: 0
11342 19:28:10.606217 [1mSubtest empty-block: SKIP (0.000s)[0<14>[ 22.060264] [IGT] drm_read: executing
11343 19:28:10.606359 m
11344 19:28:10.613020 IGT-Version: 1.2<14>[ 22.065517] [IGT] drm_read: exiting, ret=77
11345 19:28:10.616033 8-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11346 19:28:10.625653 Using IGT_SR<8>[ 22.076241] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-nonblock RESULT=skip>
11347 19:28:10.625927 Received signal: <TESTCASE> TEST_CASE_ID=empty-nonblock RESULT=skip
11349 19:28:10.629507 ANDOM=1713468239 for randomisation
11350 19:28:10.632559 Opened device: /dev/dri/card0
11351 19:28:10.635906 No KMS driver or no outputs, pipes: 16, outputs: 0
11352 19:28:10.639085 [1mSubtest empty-nonblock: SKIP (0.000s)[0m
11353 19:28:10.642332 <14>[ 22.098111] [IGT] drm_read: executing
11354 19:28:10.648890 IGT-Version: 1.2<14>[ 22.103198] [IGT] drm_read: exiting, ret=77
11355 19:28:10.656123 8-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11356 19:28:10.665608 Using IGT_SRANDOM=1713468239<8>[ 22.114327] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-block RESULT=skip>
11357 19:28:10.665711 for randomisation
11358 19:28:10.665975 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-block RESULT=skip
11360 19:28:10.668836 Opened device: /dev/dri/card0
11361 19:28:10.672396 No KMS driver or no outputs, pipes: 16, outputs: 0
11362 19:28:10.679014 [1mSubtest short-buffer-block: SKIP (0.000s)[0m
11363 19:28:10.682173 <14>[ 22.137423] [IGT] drm_read: executing
11364 19:28:10.688723 IGT-Version: 1.2<14>[ 22.141898] [IGT] drm_read: exiting, ret=77
11365 19:28:10.693012 8-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11366 19:28:10.702432 Using IGT_SR<8>[ 22.152024] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-nonblock RESULT=skip>
11367 19:28:10.702711 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-nonblock RESULT=skip
11369 19:28:10.705318 ANDOM=1713468240 for randomisation
11370 19:28:10.708453 Opened device: /dev/dri/card0
11371 19:28:10.711876 No KMS driver or no outputs, pipes: 16, outputs: 0
11372 19:28:10.718477 [1mSubtest short-buffer-nonblock: SKIP (0.000s)[0m
11373 19:28:10.731622 <14>[ 22.185402] [IGT] drm_read: executing
11374 19:28:10.738563 IGT-Version: 1.2<14>[ 22.190216] [IGT] drm_read: exiting, ret=77
11375 19:28:10.741787 8-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11376 19:28:10.751730 Using IGT_SRANDOM=1713468240<8>[ 22.201662] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-wakeup RESULT=skip>
11377 19:28:10.751827 for randomisation
11378 19:28:10.752068 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-wakeup RESULT=skip
11380 19:28:10.757938 Opened devic<8>[ 22.211923] <LAVA_SIGNAL_TESTSET STOP>
11381 19:28:10.758197 Received signal: <TESTSET> STOP
11382 19:28:10.758266 Closing test_set drm_read
11383 19:28:10.761206 e: /dev/dri/card0
11384 19:28:10.764840 No KMS driver or no outputs, pipes: 16, outputs: 0
11385 19:28:10.768204 [1mSubtest short-buffer-wakeup: SKIP (0.000s)[0m
11386 19:28:10.779684 <8>[ 22.233730] <LAVA_SIGNAL_TESTSET START kms_addfb_basic>
11387 19:28:10.779954 Received signal: <TESTSET> START kms_addfb_basic
11388 19:28:10.780034 Starting test_set kms_addfb_basic
11389 19:28:10.799146 <14>[ 22.252922] [IGT] kms_addfb_basic: executing
11390 19:28:10.812720 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch6<14>[ 22.262122] [IGT] kms_addfb_basic: starting subtest unused-handle
11391 19:28:10.812861 4)
11392 19:28:10.818662 Using IGT_SR<14>[ 22.270079] [IGT] kms_addfb_basic: finished subtest unused-handle, SUCCESS
11393 19:28:10.822355 ANDOM=1713468240 for randomisation
11394 19:28:10.825577 Opened device: /dev/dri/card0
11395 19:28:10.832298 Starting subtest: unused-hand<14>[ 22.286870] [IGT] kms_addfb_basic: exiting, ret=0
11396 19:28:10.832383 le
11397 19:28:10.838495 [1mSubtest unused-handle: SUCCESS (0.000s)[0m
11398 19:28:10.849003 Test requirement not met in<8>[ 22.297962] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-handle RESULT=pass>
11399 19:28:10.849282 Received signal: <TESTCASE> TEST_CASE_ID=unused-handle RESULT=pass
11401 19:28:10.852081 function igt_require_intel, file ../lib/drmtest.c:880:
11402 19:28:10.855292 Test requirement: is_intel_device(fd)
11403 19:28:10.868159 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:88<14>[ 22.320422] [IGT] kms_addfb_basic: executing
11404 19:28:10.868273 0:
11405 19:28:10.872019 Test requirement: is_intel_device(fd)
11406 19:28:10.878568 No KMS driver or no o<14>[ 22.330454] [IGT] kms_addfb_basic: starting subtest unused-pitches
11407 19:28:10.888518 utputs, pipes: 1<14>[ 22.338372] [IGT] kms_addfb_basic: finished subtest unused-pitches, SUCCESS
11408 19:28:10.888644 6, outputs: 0
11409 19:28:10.894990 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11410 19:28:10.901484 Using IGT_SRA<14>[ 22.355152] [IGT] kms_addfb_basic: exiting, ret=0
11411 19:28:10.904787 NDOM=1713468240 for randomisation
11412 19:28:10.907983 Opened device: /dev/dri/card0
11413 19:28:10.914834 Starting subte<8>[ 22.366453] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-pitches RESULT=pass>
11414 19:28:10.915127 Received signal: <TESTCASE> TEST_CASE_ID=unused-pitches RESULT=pass
11416 19:28:10.917910 st: unused-pitches
11417 19:28:10.921389 [1mSubtest unused-pitches: SUCCESS (0.000s)[0m
11418 19:28:10.928319 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11419 19:28:10.934901 Test requirement: is_i<14>[ 22.388835] [IGT] kms_addfb_basic: executing
11420 19:28:10.937981 ntel_device(fd)
11421 19:28:10.947890 Test requirement not met in function igt_requir<14>[ 22.399135] [IGT] kms_addfb_basic: starting subtest unused-offsets
11422 19:28:10.957788 e_intel, file ..<14>[ 22.407015] [IGT] kms_addfb_basic: finished subtest unused-offsets, SUCCESS
11423 19:28:10.957907 /lib/drmtest.c:880:
11424 19:28:10.961360 Test requirement: is_intel_device(fd)
11425 19:28:10.971534 No KMS driver or no outputs, pipes: <14>[ 22.423659] [IGT] kms_addfb_basic: exiting, ret=0
11426 19:28:10.971676 16, outputs: 0
11427 19:28:10.981328 Received signal: <TESTCASE> TEST_CASE_ID=unused-offsets RESULT=pass
11429 19:28:10.984544 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1<8>[ 22.434472] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-offsets RESULT=pass>
11430 19:28:10.984645 .86-cip19 aarch64)
11431 19:28:10.987776 Using IGT_SRANDOM=1713468240 for randomisation
11432 19:28:10.991021 Opened device: /dev/dri/card0
11433 19:28:10.994457 Starting subtest: unused-offsets
11434 19:28:11.001408 [1mSubtest unused-offsets:<14>[ 22.455641] [IGT] kms_addfb_basic: executing
11435 19:28:11.004618 SUCCESS (0.000s)[0m
11436 19:28:11.014498 Test requirement not met in function igt_<14>[ 22.464803] [IGT] kms_addfb_basic: starting subtest unused-modifier
11437 19:28:11.021032 require_intel, f<14>[ 22.472789] [IGT] kms_addfb_basic: finished subtest unused-modifier, SUCCESS
11438 19:28:11.024334 ile ../lib/drmtest.c:880:
11439 19:28:11.027367 Test requirement: is_intel_device(fd)
11440 19:28:11.037606 Test requirement not met in fu<14>[ 22.489599] [IGT] kms_addfb_basic: exiting, ret=0
11441 19:28:11.040520 nction igt_require_intel, file ../lib/drmtest.c:880:
11442 19:28:11.048032 Test requi<8>[ 22.500472] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-modifier RESULT=pass>
11443 19:28:11.048314 Received signal: <TESTCASE> TEST_CASE_ID=unused-modifier RESULT=pass
11445 19:28:11.050361 rement: is_intel_device(fd)
11446 19:28:11.057491 No KMS driver or no outputs, pipes: 16, outputs: 0
11447 19:28:11.061034 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11448 19:28:11.067452 Using IGT_SRANDOM=171346824<14>[ 22.521784] [IGT] kms_addfb_basic: executing
11449 19:28:11.070658 0 for randomisation
11450 19:28:11.074176 Opened device: /dev/dri/card0
11451 19:28:11.080752 Starting sub<14>[ 22.532217] [IGT] kms_addfb_basic: starting subtest clobberred-modifier
11452 19:28:11.090531 test: unused-mod<14>[ 22.540429] [IGT] kms_addfb_basic: finished subtest clobberred-modifier, SKIP
11453 19:28:11.090706 ifier
11454 19:28:11.096893 [1mSubtest unused-modifier: SUCCESS (0.000s)[0m
11455 19:28:11.104069 Test requirement not met in function i<14>[ 22.557386] [IGT] kms_addfb_basic: exiting, ret=77
11456 19:28:11.107125 gt_require_intel, file ../lib/drmtest.c:880:
11457 19:28:11.116891 Test requirement: is_intel_device(<8>[ 22.568508] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clobberred-modifier RESULT=skip>
11458 19:28:11.117216 Received signal: <TESTCASE> TEST_CASE_ID=clobberred-modifier RESULT=skip
11460 19:28:11.120143 fd)
11461 19:28:11.127246 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11462 19:28:11.130473 Test requirement: is_intel_device(fd)
11463 19:28:11.136667 No KMS driver or no outputs, pipes: 16, outputs:<14>[ 22.591845] [IGT] kms_addfb_basic: executing
11464 19:28:11.140638 0
11465 19:28:11.150131 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aa<14>[ 22.601964] [IGT] kms_addfb_basic: starting subtest invalid-smem-bo-on-discrete
11466 19:28:11.153796 rch64)
11467 19:28:11.160296 Using IG<14>[ 22.610906] [IGT] kms_addfb_basic: finished subtest invalid-smem-bo-on-discrete, SKIP
11468 19:28:11.163532 T_SRANDOM=1713468240 for randomisation
11469 19:28:11.166750 Opened device: /dev/dri/card0
11470 19:28:11.173334 Starting subtest: clobber<14>[ 22.628401] [IGT] kms_addfb_basic: exiting, ret=77
11471 19:28:11.177059 red-modifier
11472 19:28:11.189961 Test requirement not met in function igt_require_i<8>[ 22.639460] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip>
11473 19:28:11.190294 Received signal: <TESTCASE> TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip
11475 19:28:11.193507 915, file ../lib/drmtest.c:885:
11476 19:28:11.196774 Test requirement: is_i915_device(fd)
11477 19:28:11.200143 [1mSubtest clobberred-modifier: SKIP (0.000s)[0m
11478 19:28:11.206665 Test requirement not met in function <14>[ 22.661444] [IGT] kms_addfb_basic: executing
11479 19:28:11.213221 igt_require_intel, file ../lib/drmtest.c:880:
11480 19:28:11.219650 Test requirement:<14>[ 22.671031] [IGT] kms_addfb_basic: starting subtest legacy-format
11481 19:28:11.223512 is_intel_device(fd)
11482 19:28:11.233232 Test requirement not met in function igt_require_intel, fi<14>[ 22.684755] [IGT] kms_addfb_basic: finished subtest legacy-format, SUCCESS
11483 19:28:11.236442 le ../lib/drmtest.c:880:
11484 19:28:11.240250 Test requirement: is_intel_device(fd)
11485 19:28:11.246548 No KMS driver or no outputs, pi<14>[ 22.700577] [IGT] kms_addfb_basic: exiting, ret=0
11486 19:28:11.249944 pes: 16, outputs: 0
11487 19:28:11.260095 Received signal: <TESTCASE> TEST_CASE_ID=legacy-format RESULT=pass
11489 19:28:11.262716 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 a<8>[ 22.711957] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=legacy-format RESULT=pass>
11490 19:28:11.262804 arch64)
11491 19:28:11.266355 Using IGT_SRANDOM=1713468240 for randomisation
11492 19:28:11.269683 Opened device: /dev/dri/card0
11493 19:28:11.273003 Starting subtest: invalid-smem-bo-on-discrete
11494 19:28:11.279457 Test requirement not met <14>[ 22.734101] [IGT] kms_addfb_basic: executing
11495 19:28:11.286198 in function igt_require_intel, file ../lib/drmtest.c:880:
11496 19:28:11.292808 Test requirement: is_<14>[ 22.745780] [IGT] kms_addfb_basic: starting subtest no-handle
11497 19:28:11.302532 intel_device(fd)<14>[ 22.752149] [IGT] kms_addfb_basic: finished subtest no-handle, SUCCESS
11498 19:28:11.302639
11499 19:28:11.306020 [1mSubtest invalid-smem-bo-on-discrete: SKIP (0.000s)[0m
11500 19:28:11.312785 Test requirement n<14>[ 22.766297] [IGT] kms_addfb_basic: exiting, ret=0
11501 19:28:11.319213 ot met in function igt_require_intel, file ../lib/drmtest.c:880:
11502 19:28:11.325550 Test requireme<8>[ 22.778109] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=no-handle RESULT=pass>
11503 19:28:11.325826 Received signal: <TESTCASE> TEST_CASE_ID=no-handle RESULT=pass
11505 19:28:11.328986 nt: is_intel_device(fd)
11506 19:28:11.335505 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11507 19:28:11.338822 Test requirement: is_intel_device(fd)
11508 19:28:11.345735 No KMS driver or no outputs,<14>[ 22.800384] [IGT] kms_addfb_basic: executing
11509 19:28:11.348919 pipes: 16, outputs: 0
11510 19:28:11.359155 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip1<14>[ 22.812681] [IGT] kms_addfb_basic: starting subtest basic
11511 19:28:11.362236 9 aarch64)
11512 19:28:11.369121 Usin<14>[ 22.819083] [IGT] kms_addfb_basic: finished subtest basic, SUCCESS
11513 19:28:11.372139 g IGT_SRANDOM=1713468240 for randomisation
11514 19:28:11.375865 Opened device: /dev/dri/card0
11515 19:28:11.378529 Start<14>[ 22.832825] [IGT] kms_addfb_basic: exiting, ret=0
11516 19:28:11.382510 ing subtest: legacy-format
11517 19:28:11.392298 Successfully fuzzed 10000 {bpp, dept<8>[ 22.844494] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
11518 19:28:11.392402 h} variations
11519 19:28:11.392665 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
11521 19:28:11.398590 [1mSubtest legacy-format: SUCCESS (0.006s)[0m
11522 19:28:11.405005 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11523 19:28:11.411971 Test requirement: is_intel_d<14>[ 22.865259] [IGT] kms_addfb_basic: executing
11524 19:28:11.412065 evice(fd)
11525 19:28:11.425205 Test requirement not met in function igt_require_intel, file ../lib/d<14>[ 22.877558] [IGT] kms_addfb_basic: starting subtest bad-pitch-0
11526 19:28:11.425322 rmtest.c:880:
11527 19:28:11.435148 T<14>[ 22.884387] [IGT] kms_addfb_basic: finished subtest bad-pitch-0, SUCCESS
11528 19:28:11.438453 est requirement: is_intel_device(fd)
11529 19:28:11.445136 No KMS driver or no outputs, pipes: 16, ou<14>[ 22.898640] [IGT] kms_addfb_basic: exiting, ret=0
11530 19:28:11.448162 tputs: 0
11531 19:28:11.451744 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11532 19:28:11.458541 Us<8>[ 22.910515] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-0 RESULT=pass>
11533 19:28:11.458814 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-0 RESULT=pass
11535 19:28:11.465127 ing IGT_SRANDOM=1713468240 for randomisation
11536 19:28:11.468441 Opened device: /dev/dri/card0
11537 19:28:11.468517 Starting subtest: no-handle
11538 19:28:11.474740 [1mSubtest no-handle: SUCCESS (0.000s)[0m
11539 19:28:11.478100 Test requ<14>[ 22.932551] [IGT] kms_addfb_basic: executing
11540 19:28:11.484437 irement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11541 19:28:11.490996 Test <14>[ 22.943964] [IGT] kms_addfb_basic: starting subtest bad-pitch-32
11542 19:28:11.501360 requirement: is_<14>[ 22.950833] [IGT] kms_addfb_basic: finished subtest bad-pitch-32, SUCCESS
11543 19:28:11.501475 intel_device(fd)
11544 19:28:11.511188 Test requirement not met in function igt_require_intel, file .<14>[ 22.965402] [IGT] kms_addfb_basic: exiting, ret=0
11545 19:28:11.514463 ./lib/drmtest.c:880:
11546 19:28:11.517679 Test requirement: is_intel_device(fd)
11547 19:28:11.527384 No KMS driver or no<8>[ 22.977212] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-32 RESULT=pass>
11548 19:28:11.527733 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-32 RESULT=pass
11550 19:28:11.530729 outputs, pipes: 16, outputs: 0
11551 19:28:11.533964 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11552 19:28:11.540944 Using IGT_SRANDOM=1713468240 for randomisation
11553 19:28:11.547235 Opened device: /dev/dri/car<14>[ 22.999538] [IGT] kms_addfb_basic: executing
11554 19:28:11.547362 d0
11555 19:28:11.550541 Starting subtest: basic
11556 19:28:11.554023 [1mSubtest basic: SUCCESS (0.000s)[0m
11557 19:28:11.560378 Test requi<14>[ 23.011957] [IGT] kms_addfb_basic: starting subtest bad-pitch-63
11558 19:28:11.567099 rement not met i<14>[ 23.019070] [IGT] kms_addfb_basic: finished subtest bad-pitch-63, SUCCESS
11559 19:28:11.574102 n function igt_require_intel, file ../lib/drmtest.c:880:
11560 19:28:11.580235 Test requirement: is_i<14>[ 23.033318] [IGT] kms_addfb_basic: exiting, ret=0
11561 19:28:11.583475 ntel_device(fd)
11562 19:28:11.593576 Test requirement not met in function igt_require_intel, file ..<8>[ 23.045070] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-63 RESULT=pass>
11563 19:28:11.593892 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-63 RESULT=pass
11565 19:28:11.596876 /lib/drmtest.c:880:
11566 19:28:11.600095 Test requirement: is_intel_device(fd)
11567 19:28:11.603979 No KMS driver or no outputs, pipes: 16, outputs: 0
11568 19:28:11.613646 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch6<14>[ 23.067337] [IGT] kms_addfb_basic: executing
11569 19:28:11.613780 4)
11570 19:28:11.620264 Using IGT_SRANDOM=1713468240 for randomisation
11571 19:28:11.626893 Opened device: /dev/dri/card<14>[ 23.080024] [IGT] kms_addfb_basic: starting subtest bad-pitch-128
11572 19:28:11.627012 0
11573 19:28:11.636915 Starting subt<14>[ 23.087076] [IGT] kms_addfb_basic: finished subtest bad-pitch-128, SUCCESS
11574 19:28:11.637000 est: bad-pitch-0
11575 19:28:11.643524 [1mSubtest bad-pitch-0: SUCCESS (0.000s)[0m
11576 19:28:11.650612 Test requiremen<14>[ 23.101416] [IGT] kms_addfb_basic: exiting, ret=0
11577 19:28:11.653704 t not met in function igt_require_intel, file ../lib/drmtest.c:880:
11578 19:28:11.663266 Test requir<8>[ 23.113635] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-128 RESULT=pass>
11579 19:28:11.663578 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-128 RESULT=pass
11581 19:28:11.667124 ement: is_intel_device(fd)
11582 19:28:11.673183 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11583 19:28:11.676861 Test requirement: is_intel_device(fd)
11584 19:28:11.680027 No KMS dr<14>[ 23.135640] [IGT] kms_addfb_basic: executing
11585 19:28:11.686948 iver or no outputs, pipes: 16, outputs: 0
11586 19:28:11.693599 IGT-Version: 1.28-ga44ebfe (aarch64) <14>[ 23.146880] [IGT] kms_addfb_basic: starting subtest bad-pitch-256
11587 19:28:11.703707 (Linux: 6.1.86-c<14>[ 23.153868] [IGT] kms_addfb_basic: finished subtest bad-pitch-256, SUCCESS
11588 19:28:11.703893 ip19 aarch64)
11589 19:28:11.710236 Using IGT_SRANDOM=1713468240 for randomisation
11590 19:28:11.716421 Opened device: /d<14>[ 23.168578] [IGT] kms_addfb_basic: exiting, ret=0
11591 19:28:11.716507 ev/dri/card0
11592 19:28:11.719790 Starting subtest: bad-pitch-32
11593 19:28:11.729524 [1mSubtest bad-pitch-32: SUCCESS <8>[ 23.180498] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-256 RESULT=pass>
11594 19:28:11.729625 (0.000s)[0m
11595 19:28:11.729866 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-256 RESULT=pass
11597 19:28:11.739531 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11598 19:28:11.742823 Test requirement: is_intel_device(fd)
11599 19:28:11.749897 Test requirement not me<14>[ 23.202446] [IGT] kms_addfb_basic: executing
11600 19:28:11.752665 t in function igt_require_intel, file ../lib/drmtest.c:880:
11601 19:28:11.762547 Test requirement: i<14>[ 23.213679] [IGT] kms_addfb_basic: starting subtest bad-pitch-1024
11602 19:28:11.769268 s_intel_device(f<14>[ 23.220859] [IGT] kms_addfb_basic: finished subtest bad-pitch-1024, SUCCESS
11603 19:28:11.772544 d)
11604 19:28:11.776192 No KMS driver or no outputs, pipes: 16, outputs: 0
11605 19:28:11.782606 IGT-Version: 1.28-ga44eb<14>[ 23.235597] [IGT] kms_addfb_basic: exiting, ret=0
11606 19:28:11.786044 fe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11607 19:28:11.795407 Using IGT_SRANDOM=1713468240 for ran<8>[ 23.247527] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-1024 RESULT=pass>
11608 19:28:11.795672 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-1024 RESULT=pass
11610 19:28:11.798768 domisation
11611 19:28:11.802161 Opened device: /dev/dri/card0
11612 19:28:11.802321 Starting subtest: bad-pitch-63
11613 19:28:11.808560 [1mSubtest bad-pitch-63: SUCCESS (0.000s)[0m
11614 19:28:11.815158 Test requirement not met in function igt_require_inte<14>[ 23.269996] [IGT] kms_addfb_basic: executing
11615 19:28:11.818447 l, file ../lib/drmtest.c:880:
11616 19:28:11.822267 Test requirement: is_intel_device(fd)
11617 19:28:11.831938 Test requi<14>[ 23.282278] [IGT] kms_addfb_basic: starting subtest bad-pitch-999
11618 19:28:11.838504 rement not met i<14>[ 23.289330] [IGT] kms_addfb_basic: finished subtest bad-pitch-999, SUCCESS
11619 19:28:11.845169 n function igt_require_intel, file ../lib/drmtest.c:880:
11620 19:28:11.851791 Test requirement: is_i<14>[ 23.303831] [IGT] kms_addfb_basic: exiting, ret=0
11621 19:28:11.851879 ntel_device(fd)
11622 19:28:11.858219 No KMS driver or no outputs, pipes: 16, outputs: 0
11623 19:28:11.864411 IGT-Version<8>[ 23.315670] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-999 RESULT=pass>
11624 19:28:11.864680 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-999 RESULT=pass
11626 19:28:11.871459 : 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11627 19:28:11.874987 Using IGT_SRANDOM=1713468240 for randomisation
11628 19:28:11.877901 Opened device: /dev/dri/card0
11629 19:28:11.881515 Starting subtest: bad-pitch-128
11630 19:28:11.884452 [1mSub<14>[ 23.338145] [IGT] kms_addfb_basic: executing
11631 19:28:11.888158 test bad-pitch-128: SUCCESS (0.000s)[0m
11632 19:28:11.897816 Test requirement not met in function i<14>[ 23.350529] [IGT] kms_addfb_basic: starting subtest bad-pitch-65536
11633 19:28:11.908193 gt_require_intel<14>[ 23.357804] [IGT] kms_addfb_basic: finished subtest bad-pitch-65536, SUCCESS
11634 19:28:11.911321 , file ../lib/drmtest.c:880:
11635 19:28:11.914277 Test requirement: is_intel_device(fd)
11636 19:28:11.921135 Test requir<14>[ 23.372552] [IGT] kms_addfb_basic: exiting, ret=0
11637 19:28:11.924678 ement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11638 19:28:11.934529 Test re<8>[ 23.384565] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-65536 RESULT=pass>
11639 19:28:11.934796 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-65536 RESULT=pass
11641 19:28:11.937853 quirement: is_intel_device(fd)
11642 19:28:11.941195 No KMS driver or no outputs, pipes: 16, outputs: 0
11643 19:28:11.947790 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11644 19:28:11.951041 Using IG<14>[ 23.406709] [IGT] kms_addfb_basic: executing
11645 19:28:11.957537 T_SRANDOM=1713468241 for randomisation
11646 19:28:11.957651 Opened device: /dev/dri/card0
11647 19:28:11.960842 Starting subtest: bad-pitch-256
11648 19:28:11.971005 [1mSubt<14>[ 23.420162] [IGT] kms_addfb_basic: starting subtest invalid-get-prop-any
11649 19:28:11.977126 est bad-pitch-25<14>[ 23.428404] [IGT] kms_addfb_basic: finished subtest invalid-get-prop-any, SUCCESS
11650 19:28:11.980362 6: SUCCESS (0.000s)[0m
11651 19:28:11.987273 Test requirement not me<14>[ 23.441581] [IGT] kms_addfb_basic: exiting, ret=0
11652 19:28:11.994022 t in function igt_require_intel, file ../lib/drmtest.c:880:
11653 19:28:12.004134 Test requirement: i<8>[ 23.452514] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
11654 19:28:12.004240 s_intel_device(fd)
11655 19:28:12.004483 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
11657 19:28:12.010704 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11658 19:28:12.013858 Test requirement: is_intel_device(fd)
11659 19:28:12.023734 No KMS driver or no outputs, pipe<14>[ 23.475484] [IGT] kms_addfb_basic: executing
11660 19:28:12.023864 s: 16, outputs: 0
11661 19:28:12.030609 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11662 19:28:12.040345 Using IGT_SRANDOM=1713468<14>[ 23.490044] [IGT] kms_addfb_basic: starting subtest invalid-get-prop
11663 19:28:12.047307 241 for randomis<14>[ 23.498145] [IGT] kms_addfb_basic: finished subtest invalid-get-prop, SUCCESS
11664 19:28:12.050183 ation
11665 19:28:12.050291 Opened device: /dev/dri/card0
11666 19:28:12.056648 Starting s<14>[ 23.510997] [IGT] kms_addfb_basic: exiting, ret=0
11667 19:28:12.060495 ubtest: bad-pitch-1024
11668 19:28:12.063900 [1mSubtest bad-pitch-1024: SUCCESS (0.000s)[0m
11669 19:28:12.070439 Test r<8>[ 23.521965] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
11670 19:28:12.070697 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
11672 19:28:12.076706 equirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11673 19:28:12.083057 Test requirement: is_intel_device(fd)
11674 19:28:12.089835 Test requirement not met in function igt_require_intel, fil<14>[ 23.544515] [IGT] kms_addfb_basic: executing
11675 19:28:12.093511 e ../lib/drmtest.c:880:
11676 19:28:12.096583 Test requirement: is_intel_device(fd)
11677 19:28:12.109780 No KMS driver or no outputs, pipes: 16, outputs:<14>[ 23.559063] [IGT] kms_addfb_basic: starting subtest invalid-set-prop-any
11678 19:28:12.109917 0
11679 19:28:12.116725 IGT-Version:<14>[ 23.567557] [IGT] kms_addfb_basic: finished subtest invalid-set-prop-any, SUCCESS
11680 19:28:12.126486 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aa<14>[ 23.580729] [IGT] kms_addfb_basic: exiting, ret=0
11681 19:28:12.126667 rch64)
11682 19:28:12.132971 Using IGT_SRANDOM=1713468241 for randomisation
11683 19:28:12.139961 Opened d<8>[ 23.590534] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
11684 19:28:12.140273 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
11686 19:28:12.142880 evice: /dev/dri/card0
11687 19:28:12.146540 Starting subtest: bad-pitch-999
11688 19:28:12.149950 [1mSubtest bad-pitch-999: SUCCESS (0.000s)[0m
11689 19:28:12.159702 Test requirement not met in function igt_require_intel,<14>[ 23.612781] [IGT] kms_addfb_basic: executing
11690 19:28:12.163010 file ../lib/drmtest.c:880:
11691 19:28:12.166345 Test requirement: is_intel_device(fd)
11692 19:28:12.176163 Test requirement not met in function igt_req<14>[ 23.626375] [IGT] kms_addfb_basic: starting subtest invalid-set-prop
11693 19:28:12.182714 uire_intel, file<14>[ 23.634492] [IGT] kms_addfb_basic: finished subtest invalid-set-prop, SUCCESS
11694 19:28:12.186063 ../lib/drmtest.c:880:
11695 19:28:12.192677 Test requirement: is_int<14>[ 23.647334] [IGT] kms_addfb_basic: exiting, ret=0
11696 19:28:12.195925 el_device(fd)
11697 19:28:12.199634 No KMS driver or no outputs, pipes: 16, outputs: 0
11698 19:28:12.206139 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
11700 19:28:12.209232 IGT-Version: <8>[ 23.658396] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
11701 19:28:12.212879 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11702 19:28:12.215809 Using IGT_SRANDOM=1713468241 for randomisation
11703 19:28:12.219193 Opened device: /dev/dri/card0
11704 19:28:12.222442 Starting subtest: bad-pitch-65536
11705 19:28:12.229545 [1mSub<14>[ 23.680855] [IGT] kms_addfb_basic: executing
11706 19:28:12.232952 test bad-pitch-65536: SUCCESS (0.000s)[0m
11707 19:28:12.239182 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11708 19:28:12.246269 <14>[ 23.697421] [IGT] kms_addfb_basic: starting subtest master-rmfb
11709 19:28:12.252828 Test requirement<14>[ 23.704519] [IGT] kms_addfb_basic: finished subtest master-rmfb, SUCCESS
11710 19:28:12.255945 : is_intel_device(fd)
11711 19:28:12.262687 Test requ<14>[ 23.715084] [IGT] kms_addfb_basic: exiting, ret=0
11712 19:28:12.275916 irement not met in function igt_require_intel, file ../lib/drmte<8>[ 23.725453] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=master-rmfb RESULT=pass>
11713 19:28:12.276039 st.c:880:
11714 19:28:12.276283 Received signal: <TESTCASE> TEST_CASE_ID=master-rmfb RESULT=pass
11716 19:28:12.278679 Test requirement: is_intel_device(fd)
11717 19:28:12.281922 No KMS driver or no outputs, pipes: 16, outputs: 0
11718 19:28:12.288674 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11719 19:28:12.295787 Using <14>[ 23.747314] [IGT] kms_addfb_basic: executing
11720 19:28:12.298934 IGT_SRANDOM=1713468241 for randomisation
11721 19:28:12.301946 Opened device: /dev/dri/card0
11722 19:28:12.305464 Starting subtest: invalid-get-prop-any
11723 19:28:12.315594 [1mSubtest invalid-get-prop-an<14>[ 23.765529] [IGT] kms_addfb_basic: starting subtest addfb25-modifier-no-flag
11724 19:28:12.325207 y: SUCCESS (0.00<14>[ 23.773395] [IGT] kms_addfb_basic: finished subtest addfb25-modifier-no-flag, SUCCESS
11725 19:28:12.325306 0s)[0m
11726 19:28:12.328514 Test re<14>[ 23.783109] [IGT] kms_addfb_basic: exiting, ret=0
11727 19:28:12.345134 quirement not met in function igt_require_intel, file ../lib/drm<8>[ 23.794041] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass>
11728 19:28:12.345261 test.c:880:
11729 19:28:12.345520 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass
11731 19:28:12.348526 Test requirement: is_intel_device(fd)
11732 19:28:12.354983 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11733 19:28:12.361956 Test requirement: is_int<14>[ 23.816344] [IGT] kms_addfb_basic: executing
11734 19:28:12.365684 el_device(fd)
11735 19:28:12.368537 No KMS driver or no outputs, pipes: 16, outputs: 0
11736 19:28:12.375185 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11737 19:28:12.381411 Using IGT<14>[ 23.833894] [IGT] kms_addfb_basic: starting subtest addfb25-bad-modifier
11738 19:28:12.384761 _SRANDOM=1713468241 for randomisation
11739 19:28:12.388182 Opened device: /dev/dri/card0
11740 19:28:12.391468 Starting subtest: invalid-get-prop
11741 19:28:12.395140 [1mSubtest invalid-get-prop: SUCCESS (0.000s)[0m
11742 19:28:12.404842 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11743 19:28:12.407930 Test requirement: is_intel_device(fd)
11744 19:28:12.414940 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11745 19:28:12.417905 Test requirement: is_intel_device(fd)
11746 19:28:12.421627 No KMS driver or no outputs, pipes: 16, outputs: 0
11747 19:28:12.427928 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11748 19:28:12.431627 Using IGT_SRANDOM=1713468241 for randomisation
11749 19:28:12.434564 Opened device: /dev/dri/card0
11750 19:28:12.437761 Starting subtest: invalid-set-prop-any
11751 19:28:12.441059 [1mSubtest invalid-set-prop-any: SUCCESS (0.000s)[0m
11752 19:28:12.451391 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11753 19:28:12.454579 Test requirement: is_intel_device(fd)
11754 19:28:12.461240 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11755 19:28:12.464347 Test requirement: is_intel_device(fd)
11756 19:28:12.467561 No KMS driver or no outputs, pipes: 16, outputs: 0
11757 19:28:12.474596 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11758 19:28:12.477836 Using IGT_SRANDOM=1713468241 for randomisation
11759 19:28:12.481262 Opened device: /dev/dri/card0
11760 19:28:12.484351 Starting subtest: invalid-set-prop
11761 19:28:12.487613 [1mSubtest invalid-set-prop: SUCCESS (0.000s)[0m
11762 19:28:12.497509 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11763 19:28:12.500612 Test requirement: is_intel_device(fd)
11764 19:28:12.507375 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11765 19:28:12.510591 Test requirement: is_intel_device(fd)
11766 19:28:12.514523 No KMS driver or no outputs, pipes: 16, outputs: 0
11767 19:28:12.521361 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11768 19:28:12.524081 Using IGT_SRANDOM=1713468241 for randomisation
11769 19:28:12.527691 Opened device: /dev/dri/card0
11770 19:28:12.530888 Starting subtest: master-rmfb
11771 19:28:12.534183 [1mSubtest master-rmfb: SUCCESS (0.000s)[0m
11772 19:28:12.541010 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11773 19:28:12.544052 Test requirement: is_intel_device(fd)
11774 19:28:12.553779 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11775 19:28:12.557609 Test requirement: is_intel_device(fd)
11776 19:28:12.560644 No KMS driver or no outputs, pipes: 16, outputs: 0
11777 19:28:12.567066 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11778 19:28:12.570290 Using IGT_SRANDOM=1713468241 for randomisation
11779 19:28:12.574093 Opened device: /dev/dri/card0
11780 19:28:12.577389 Starting subtest: addfb25-modifier-no-flag
11781 19:28:12.583541 [1mSubtest addfb25-modifier-no-flag: SUCCESS (0.000s)[0m
11782 19:28:12.590517 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11783 19:28:12.593504 Test requirement: is_intel_device(fd)
11784 19:28:12.600008 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11785 19:28:12.603376 Test requirement: is_intel_device(fd)
11786 19:28:12.606703 No KMS driver or no outputs, pipes: 16, outputs: 0
11787 19:28:12.613538 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11788 19:28:12.616478 Using IGT_SRANDOM=1713468241 for randomisation
11789 19:28:12.620256 Opened device: /dev/dri/card0
11790 19:28:12.623490 Starting subtest: addfb25-bad-modifier
11791 19:28:12.633186 (kms_addfb_basic:430) CRITICAL: Test assertion failure function addfb25_tests, file ../tests/kms_addfb_basic.c:714:
11792 19:28:12.653335 (kms_addfb_basic:430) CRITICAL: Failed assertion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1
11793 19:28:12.656700 (kms_addfb_basic:430) CRITICAL: error: 0 != -1
11794 19:28:12.656804 Stack trace:
11795 19:28:12.662979 #0 ../lib/igt_core.c:1989 __igt_fail_assert()
11796 19:28:12.663066 #1 [<unknown>+0xc8df4358]
11797 19:28:12.666471 #2 [<unknown>+0xc8df5fbc]
11798 19:28:12.669840 #3 [<unknown>+0xc8df156c]
11799 19:28:12.673054 #4 [__libc_init_first+0x80]
11800 19:28:12.676309 #5 [__libc_start_main+0x98]
11801 19:28:12.676393 #6 [<unknown>+0xc8df15b0]
11802 19:28:12.679559 Subtest addfb25-bad-modifier failed.
11803 19:28:12.682884 **** DEBUG ****
11804 19:28:12.689335 (kms_addfb_basic:430) ioctl_wrappers-DEBUG: Test requirement passed: igt_has_fb_modifiers(fd)
11805 19:28:12.699637 (kms_addfb_basic:430) CRITICAL: Test assertion failure function addfb25_tests, file ../tests/kms_addfb_basic.c:714:
11806 19:28:12.719273 (kms_addfb_basic:430) CRITICAL: Failed assertion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1
11807 19:28:12.729072 (kms_addfb_basic:430) CRITICAL: error: 0 != -1<14>[ 24.180456] [IGT] kms_addfb_basic: finished subtest addfb25-bad-modifier, FAIL
11808 19:28:12.729226
11809 19:28:12.736023 (kms_addfb_bas<14>[ 24.189458] [IGT] kms_addfb_basic: exiting, ret=98
11810 19:28:12.739276 ic:430) igt_core-INFO: Stack trace:
11811 19:28:12.752474 (kms_addfb_basic:430) igt_core-INFO: #0 .<8>[ 24.201737] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-bad-modifier RESULT=fail>
11812 19:28:12.752801 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-bad-modifier RESULT=fail
11814 19:28:12.756161 ./lib/igt_core.c:1989 __igt_fail_assert()
11815 19:28:12.762744 (kms_addfb_basic:430) igt_core-INFO: #1 [<unknown>+0xc8df4358]
11816 19:28:12.765831 (kms_addfb_basic:430) igt_core-INFO: #2 [<unknown>+0xc8df5fbc]
11817 19:28:12.772401 (<14>[ 24.224680] [IGT] kms_addfb_basic: executing
11818 19:28:12.775488 kms_addfb_basic:430) igt_core-INFO: #3 [<unknown>+0xc8df156c]
11819 19:28:12.782198 (kms_addfb_basic:430) igt_core-INFO: #4 [__libc_init_first+0x80]
11820 19:28:12.788727 (kms_addfb_basic:430) igt_c<14>[ 24.243203] [IGT] kms_addfb_basic: exiting, ret=77
11821 19:28:12.795298 ore-INFO: #5 [__libc_start_main+0x98]
11822 19:28:12.805612 (kms_addfb_basic:430) i<8>[ 24.253983] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip>
11823 19:28:12.805897 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip
11825 19:28:12.808538 gt_core-INFO: #6 [<unknown>+0xc8df15b0]
11826 19:28:12.808619 **** END ****
11827 19:28:12.815583 [1mSubtest addfb25-bad-modifier: FAIL (0.339s)[0m
11828 19:28:12.821909 Test requirement not met in function igt_requir<14>[ 24.276529] [IGT] kms_addfb_basic: executing
11829 19:28:12.825237 e_intel, file ../lib/drmtest.c:880:
11830 19:28:12.828885 Test requirement: is_intel_device(fd)
11831 19:28:12.838705 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11832 19:28:12.841975 <14>[ 24.295284] [IGT] kms_addfb_basic: exiting, ret=77
11833 19:28:12.845249 Test requirement: is_intel_device(fd)
11834 19:28:12.855637 No KMS driver or no outpu<8>[ 24.306317] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip>
11835 19:28:12.855898 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip
11837 19:28:12.858703 ts, pipes: 16, outputs: 0
11838 19:28:12.865582 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11839 19:28:12.868749 Using IGT_SRANDOM=1713468242 for randomisation
11840 19:28:12.875313 Opened device: /d<14>[ 24.328442] [IGT] kms_addfb_basic: executing
11841 19:28:12.875403 ev/dri/card0
11842 19:28:12.881691 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11843 19:28:12.885558 Test requirement: is_intel_device(fd)
11844 19:28:12.894849 [1mSubtest addfb25-x-t<14>[ 24.346422] [IGT] kms_addfb_basic: exiting, ret=77
11845 19:28:12.898780 iled-mismatch-legacy: SKIP (0.000s)[0m
11846 19:28:12.908628 Test requirement not me<8>[ 24.357199] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip>
11847 19:28:12.908942 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip
11849 19:28:12.914880 t in function igt_require_intel, file ../lib/drmtest.c:880:
11850 19:28:12.918134 Test requirement: is_intel_device(fd)
11851 19:28:12.921743 No KMS driver or no outputs, pipes: 16, outputs: 0
11852 19:28:12.928066 IGT-Vers<14>[ 24.380124] [IGT] kms_addfb_basic: executing
11853 19:28:12.931661 ion: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11854 19:28:12.934804 Using IGT_SRANDOM=1713468242 for randomisation
11855 19:28:12.938164 Opened device: /dev/dri/card0
11856 19:28:12.944871 Test requirement not <14>[ 24.398468] [IGT] kms_addfb_basic: exiting, ret=77
11857 19:28:12.951452 met in function igt_require_intel, file ../lib/drmtest.c:880:
11858 19:28:12.958269 T<8>[ 24.409443] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip>
11859 19:28:12.958596 Received signal: <TESTCASE> TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip
11861 19:28:12.961405 est requirement: is_intel_device(fd)
11862 19:28:12.967756 [1mSubtest addfb25-x-tiled-legacy: SKIP (0.000s)[0m
11863 19:28:12.978193 Test requirement not met in function igt_require_intel, file ../lib<14>[ 24.430624] [IGT] kms_addfb_basic: executing
11864 19:28:12.978329 /drmtest.c:880:
11865 19:28:12.981391 Test requirement: is_intel_device(fd)
11866 19:28:12.987846 No KMS driver or no outputs, pipes: 16, outputs: 0
11867 19:28:12.998058 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-<14>[ 24.449357] [IGT] kms_addfb_basic: exiting, ret=77
11868 19:28:12.998147 cip19 aarch64)
11869 19:28:13.001539 Using IGT_SRANDOM=1713468242 for randomisation
11870 19:28:13.004581 Opened device: /dev/dri/card0
11871 19:28:13.014169 T<8>[ 24.463766] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip>
11872 19:28:13.014459 Received signal: <TESTCASE> TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip
11874 19:28:13.020787 est requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11875 19:28:13.024522 Test requirement: is_intel_device(fd)
11876 19:28:13.033926 [1mSubtest addfb25-framebuffer-vs-set-tiling: SKIP (0<14>[ 24.486221] [IGT] kms_addfb_basic: executing
11877 19:28:13.034016 .000s)[0m
11878 19:28:13.040485 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11879 19:28:13.044127 Test requirement: is_intel_device(fd)
11880 19:28:13.050297 No KMS driver or no outpu<14>[ 24.505198] [IGT] kms_addfb_basic: exiting, ret=77
11881 19:28:13.054029 ts, pipes: 16, outputs: 0
11882 19:28:13.064014 IGT-Version: 1.28-ga44ebfe (aarch64) <8>[ 24.516112] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tile-pitch-mismatch RESULT=skip>
11883 19:28:13.064312 Received signal: <TESTCASE> TEST_CASE_ID=tile-pitch-mismatch RESULT=skip
11885 19:28:13.067169 (Linux: 6.1.86-cip19 aarch64)
11886 19:28:13.073688 Using IGT_SRANDOM=1713468242 for randomisation
11887 19:28:13.073790 Opened device: /dev/dri/card0
11888 19:28:13.083684 Test requirement not met in function igt_require_i<14>[ 24.537961] [IGT] kms_addfb_basic: executing
11889 19:28:13.087026 ntel, file ../lib/drmtest.c:880:
11890 19:28:13.090297 Test requirement: is_intel_device(fd)
11891 19:28:13.097259 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11892 19:28:13.103925 Tes<14>[ 24.555867] [IGT] kms_addfb_basic: exiting, ret=77
11893 19:28:13.107028 t requirement: is_intel_device(fd)
11894 19:28:13.116654 [1mSubtest basic-x-tiled-le<8>[ 24.567049] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip>
11895 19:28:13.116979 Received signal: <TESTCASE> TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip
11897 19:28:13.119973 gacy: SKIP (0.000s)[0m
11898 19:28:13.123754 No KMS driver or no outputs, pipes: 16, outputs: 0
11899 19:28:13.130505 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11900 19:28:13.133632 Using IGT_SRAND<14>[ 24.589208] [IGT] kms_addfb_basic: executing
11901 19:28:13.136839 OM=1713468242 for randomisation
11902 19:28:13.139952 Opened device: /dev/dri/card0
11903 19:28:13.146560 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11904 19:28:13.153402 Test require<14>[ 24.607015] [IGT] kms_addfb_basic: exiting, ret=77
11905 19:28:13.156584 ment: is_intel_device(fd)
11906 19:28:13.166661 Test requirement not met in function <8>[ 24.618042] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=size-max RESULT=skip>
11907 19:28:13.167053 Received signal: <TESTCASE> TEST_CASE_ID=size-max RESULT=skip
11909 19:28:13.169882 igt_require_intel, file ../lib/drmtest.c:880:
11910 19:28:13.173244 Test requirement: is_intel_device(fd)
11911 19:28:13.179983 [1mSubtest framebuffer-vs-set-tiling: SKIP (0.000s)[0m
11912 19:28:13.186434 No KMS driver or no outputs, pip<14>[ 24.639621] [IGT] kms_addfb_basic: executing
11913 19:28:13.186569 es: 16, outputs: 0
11914 19:28:13.193556 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11915 19:28:13.199947 Using IGT_SRANDOM=1713468242 for randomisation
11916 19:28:13.206843 Opened device: /dev/dri/<14>[ 24.658297] [IGT] kms_addfb_basic: exiting, ret=77
11917 19:28:13.206981 card0
11918 19:28:13.216532 Test requirement not met in function igt_require_intel, f<8>[ 24.669242] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-wide RESULT=skip>
11919 19:28:13.216848 Received signal: <TESTCASE> TEST_CASE_ID=too-wide RESULT=skip
11921 19:28:13.219851 ile ../lib/drmtest.c:880:
11922 19:28:13.223192 Test requirement: is_intel_device(fd)
11923 19:28:13.229535 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11924 19:28:13.236060 Test requi<14>[ 24.690842] [IGT] kms_addfb_basic: executing
11925 19:28:13.239499 rement: is_intel_device(fd)
11926 19:28:13.242705 [1mSubtest tile-pitch-mismatch: SKIP (0.000s)[0m
11927 19:28:13.250002 No KMS driver or no outputs, pipes: 16, outputs: 0
11928 19:28:13.255978 IGT-Version: 1.28-ga44ebfe <14>[ 24.708420] [IGT] kms_addfb_basic: exiting, ret=77
11929 19:28:13.259864 (aarch64) (Linux: 6.1.86-cip19 aarch64)
11930 19:28:13.266173 Received signal: <TESTCASE> TEST_CASE_ID=too-high RESULT=skip
11932 19:28:13.269217 Using IGT_SRANDOM=17134<8>[ 24.719484] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-high RESULT=skip>
11933 19:28:13.269336 68242 for randomisation
11934 19:28:13.272718 Opened device: /dev/dri/card0
11935 19:28:13.278971 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11936 19:28:13.285977 Test requirement: is<14>[ 24.739889] [IGT] kms_addfb_basic: executing
11937 19:28:13.289283 _intel_device(fd)
11938 19:28:13.295699 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11939 19:28:13.298898 Test requirement: is_intel_device(fd)
11940 19:28:13.305599 [1mSubtest basic-<14>[ 24.758101] [IGT] kms_addfb_basic: exiting, ret=77
11941 19:28:13.308841 y-tiled-legacy: SKIP (0.000s)[0m
11942 19:28:13.319006 No KMS driver or no outputs, <8>[ 24.769149] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small RESULT=skip>
11943 19:28:13.319194 pipes: 16, outputs: 0
11944 19:28:13.319515 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small RESULT=skip
11946 19:28:13.325407 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11947 19:28:13.329301 Using IGT_SRANDOM=1713468242 for randomisation
11948 19:28:13.335811 Opened device: /dev/d<14>[ 24.791000] [IGT] kms_addfb_basic: executing
11949 19:28:13.338957 ri/card0
11950 19:28:13.345664 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11951 19:28:13.349008 Test requirement: is_intel_device(fd)
11952 19:28:13.355588 Test requirement not met in<14>[ 24.808558] [IGT] kms_addfb_basic: exiting, ret=77
11953 19:28:13.362130 function igt_require_intel, file ../lib/drmtest.c:880:
11954 19:28:13.369063 Test re<8>[ 24.819758] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=small-bo RESULT=skip>
11955 19:28:13.369358 Received signal: <TESTCASE> TEST_CASE_ID=small-bo RESULT=skip
11957 19:28:13.372347 quirement: is_intel_device(fd)
11958 19:28:13.375462 No KMS driver or no outputs, pipes: 16, outputs: 0
11959 19:28:13.379633 [1mSubtest size-max: SKIP (0.000s)[0m
11960 19:28:13.385734 IGT-Version: 1.28-ga44ebfe (aarch64<14>[ 24.840082] [IGT] kms_addfb_basic: executing
11961 19:28:13.388630 ) (Linux: 6.1.86-cip19 aarch64)
11962 19:28:13.395550 Using IGT_SRANDOM=1713468242 for randomisation
11963 19:28:13.395653 Opened device: /dev/dri/card0
11964 19:28:13.405132 Test requirement not met in function igt_require<14>[ 24.858489] [IGT] kms_addfb_basic: exiting, ret=77
11965 19:28:13.408645 _intel, file ../lib/drmtest.c:880:
11966 19:28:13.418340 Test requirement: is_intel_d<8>[ 24.869754] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip>
11967 19:28:13.418690 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip
11969 19:28:13.422113 evice(fd)
11970 19:28:13.428084 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11971 19:28:13.431641 Test requirement: is_intel_device(fd)
11972 19:28:13.438592 No KMS driver or no output<14>[ 24.892274] [IGT] kms_addfb_basic: executing
11973 19:28:13.441780 s, pipes: 16, outputs: 0
11974 19:28:13.444851 [1mSubtest too-wide: SKIP (0.000s)[0m
11975 19:28:13.451361 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
11976 19:28:13.458567 Using IGT_SRANDOM=1713468<14>[ 24.909959] [IGT] kms_addfb_basic: exiting, ret=77
11977 19:28:13.458665 242 for randomisation
11978 19:28:13.461763 Opened device: /dev/dri/card0
11979 19:28:13.471595 Test requi<8>[ 24.921378] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip>
11980 19:28:13.471971 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip
11982 19:28:13.478028 rement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11983 19:28:13.481326 Test requirement: is_intel_device(fd)
11984 19:28:13.488045 Test requirement not met in function igt_requir<14>[ 24.943751] [IGT] kms_addfb_basic: executing
11985 19:28:13.491387 e_intel, file ../lib/drmtest.c:880:
11986 19:28:13.494478 Test requirement: is_intel_device(fd)
11987 19:28:13.501121 No KMS driver or no outputs, pipes: 16, outputs: 0
11988 19:28:13.508412 [1mSubtest too-<14>[ 24.961063] [IGT] kms_addfb_basic: exiting, ret=77
11989 19:28:13.508578 high: SKIP (0.000s)[0m
11990 19:28:13.521415 IGT-Version: 1.28-ga44ebfe (aarch64) (L<8>[ 24.971169] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip>
11991 19:28:13.521808 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip
11993 19:28:13.525026 inux: 6.1.86-cip19 aarch64)
11994 19:28:13.527845 Using IGT_SRANDOM=1713468242 for randomisation
11995 19:28:13.531496 Opened device: /dev/dri/card0
11996 19:28:13.537646 Test requirement not met in function igt_require_int<14>[ 24.993704] [IGT] kms_addfb_basic: executing
11997 19:28:13.541360 el, file ../lib/drmtest.c:880:
11998 19:28:13.544384 Test requirement: is_intel_device(fd)
11999 19:28:13.554327 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
12000 19:28:13.557832 Test <14>[ 25.011388] [IGT] kms_addfb_basic: exiting, ret=77
12001 19:28:13.561173 requirement: is_intel_device(fd)
12002 19:28:13.570857 No KMS driver or no outputs, p<8>[ 25.022107] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip>
12003 19:28:13.571226 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip
12005 19:28:13.574266 ipes: 16, outputs: 0
12006 19:28:13.577306 [1mSubtest bo-too-small: SKIP (0.000s)[0m
12007 19:28:13.583915 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12008 19:28:13.590508 Using IGT_SRANDOM=1713468<14>[ 25.044358] [IGT] kms_addfb_basic: executing
12009 19:28:13.593751 242 for randomisation
12010 19:28:13.597840 Opened device: /dev/dri/card0
12011 19:28:13.604113 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
12012 19:28:13.610732 Test requirement: is_i<14>[ 25.062909] [IGT] kms_addfb_basic: exiting, ret=77
12013 19:28:13.610902 ntel_device(fd)
12014 19:28:13.623735 Test requirement not met in function igt_requir<8>[ 25.073885] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-4-tiled RESULT=skip>
12015 19:28:13.624115 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-4-tiled RESULT=skip
12017 19:28:13.630385 e_intel, file ../lib/drmtest.c:8<8>[ 25.083734] <LAVA_SIGNAL_TESTSET STOP>
12018 19:28:13.630553 80:
12019 19:28:13.630890 Received signal: <TESTSET> STOP
12020 19:28:13.631041 Closing test_set kms_addfb_basic
12021 19:28:13.633911 Test requirement: is_intel_device(fd)
12022 19:28:13.637261 No KMS driver or no outputs, pipes: 16, outputs: 0
12023 19:28:13.640369 [1mSubtest small-bo: SKIP (0.000s)[0m
12024 19:28:13.646975 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12025 19:28:13.653788 Usi<8>[ 25.105713] <LAVA_SIGNAL_TESTSET START kms_atomic>
12026 19:28:13.654151 Received signal: <TESTSET> START kms_atomic
12027 19:28:13.654311 Starting test_set kms_atomic
12028 19:28:13.656749 ng IGT_SRANDOM=1713468242 for randomisation
12029 19:28:13.660004 Opened device: /dev/dri/card0
12030 19:28:13.666828 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
12031 19:28:13.670387 <14>[ 25.126092] [IGT] kms_atomic: executing
12032 19:28:13.676977 Test requirement<14>[ 25.130912] [IGT] kms_atomic: exiting, ret=77
12033 19:28:13.680192 : is_intel_device(fd)
12034 19:28:13.690490 Test requirement not met in function igt_<8>[ 25.141087] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-overlay-legacy RESULT=skip>
12035 19:28:13.690856 Received signal: <TESTCASE> TEST_CASE_ID=plane-overlay-legacy RESULT=skip
12037 19:28:13.693478 require_intel, file ../lib/drmtest.c:880:
12038 19:28:13.696575 Test requirement: is_intel_device(fd)
12039 19:28:13.703237 No KMS driver or no outputs, pipes: 16, outputs: 0
12040 19:28:13.709862 [1mSubtest bo-too-small-d<14>[ 25.163637] [IGT] kms_atomic: executing
12041 19:28:13.716734 ue-to-tiling: SK<14>[ 25.168351] [IGT] kms_atomic: exiting, ret=77
12042 19:28:13.716843 IP (0.000s)[0m
12043 19:28:13.726387 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-legacy RESULT=skip
12045 19:28:13.729983 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.<8>[ 25.178655] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-legacy RESULT=skip>
12046 19:28:13.730066 1.86-cip19 aarch64)
12047 19:28:13.733250 Using IGT_SRANDOM=1713468242 for randomisation
12048 19:28:13.736449 Opened device: /dev/dri/card0
12049 19:28:13.746174 Test requirement not met in function igt_require_intel, file ../lib/drmtest.<14>[ 25.201411] [IGT] kms_atomic: executing
12050 19:28:13.749832 c:880:
12051 19:28:13.753031 Test req<14>[ 25.207377] [IGT] kms_atomic: exiting, ret=77
12052 19:28:13.756012 uirement: is_intel_device(fd)
12053 19:28:13.769784 Test requirement not met in funct<8>[ 25.217964] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip>
12054 19:28:13.770083 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip
12056 19:28:13.773181 ion igt_require_intel, file ../lib/drmtest.c:880:
12057 19:28:13.776212 Test requirement: is_intel_device(fd)
12058 19:28:13.779212 No KMS driver or no outputs, pipes: 16, outputs: 0
12059 19:28:13.786179 [1mSubtest addfb2<14>[ 25.240831] [IGT] kms_atomic: executing
12060 19:28:13.792692 5-y-tiled-legacy<14>[ 25.246172] [IGT] kms_atomic: exiting, ret=77
12061 19:28:13.795901 : SKIP (0.000s)[0m
12062 19:28:13.806076 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux<8>[ 25.256551] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-immutable-zpos RESULT=skip>
12063 19:28:13.806345 Received signal: <TESTCASE> TEST_CASE_ID=plane-immutable-zpos RESULT=skip
12065 19:28:13.809378 : 6.1.86-cip19 aarch64)
12066 19:28:13.812636 Using IGT_SRANDOM=1713468242 for randomisation
12067 19:28:13.815953 Opened device: /dev/dri/card0
12068 19:28:13.826130 Test requirement not met in function igt_require_intel, file ../lib/drmt<14>[ 25.279759] [IGT] kms_atomic: executing
12069 19:28:13.826255 est.c:880:
12070 19:28:13.832513 Test<14>[ 25.285298] [IGT] kms_atomic: exiting, ret=77
12071 19:28:13.836342 requirement: is_intel_device(fd)
12072 19:28:13.842846 Test requirement not met in f<8>[ 25.295468] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test-only RESULT=skip>
12073 19:28:13.843103 Received signal: <TESTCASE> TEST_CASE_ID=test-only RESULT=skip
12075 19:28:13.848990 unction igt_require_intel, file ../lib/drmtest.c:880:
12076 19:28:13.852617 Test requirement: is_intel_device(fd)
12077 19:28:13.855699 No KMS driver or no outputs, pipes: 16, outputs: 0
12078 19:28:13.862647 [1mSubtest ad<14>[ 25.316583] [IGT] kms_atomic: executing
12079 19:28:13.869134 dfb25-yf-tiled-l<14>[ 25.321751] [IGT] kms_atomic: exiting, ret=77
12080 19:28:13.869244 egacy: SKIP (0.000s)[0m
12081 19:28:13.882694 IGT-Version: 1.28-ga44ebfe (aarch64) (<8>[ 25.331895] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-cursor-legacy RESULT=skip>
12082 19:28:13.882796 Linux: 6.1.86-cip19 aarch64)
12083 19:28:13.883038 Received signal: <TESTCASE> TEST_CASE_ID=plane-cursor-legacy RESULT=skip
12085 19:28:13.889207 Using IGT_SRANDOM=1713468242 for randomisation
12086 19:28:13.892222 Opened device: /dev/dri/card0
12087 19:28:13.899336 Test requirement not met in function igt_require_in<14>[ 25.354043] [IGT] kms_atomic: executing
12088 19:28:13.905887 tel, file ../lib<14>[ 25.359333] [IGT] kms_atomic: exiting, ret=77
12089 19:28:13.906010 /drmtest.c:880:
12090 19:28:13.912362 Test requirement: is_intel_device(fd)
12091 19:28:13.918841 Test req<8>[ 25.369869] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params RESULT=skip>
12092 19:28:13.919098 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params RESULT=skip
12094 19:28:13.925368 uirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
12095 19:28:13.928601 Test requirement: is_intel_device(fd)
12096 19:28:13.938555 No KMS driver or no outputs, pipes: 16, outpu<14>[ 25.391966] [IGT] kms_atomic: executing
12097 19:28:13.938642 ts: 0
12098 19:28:13.941892 [1mSubte<14>[ 25.396955] [IGT] kms_atomic: exiting, ret=77
12099 19:28:13.948538 st addfb25-y-tiled-small-legacy: SKIP (0.000s)[0m
12100 19:28:13.958446 IGT-Version:<8>[ 25.407355] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params-fence RESULT=skip>
12101 19:28:13.958706 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params-fence RESULT=skip
12103 19:28:13.962075 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12104 19:28:13.965030 Using IGT_SRANDOM=1713468242 for randomisation
12105 19:28:13.968610 Opened device: /dev/dri/card0
12106 19:28:13.975317 Test requirement not met <14>[ 25.429819] [IGT] kms_atomic: executing
12107 19:28:13.981772 in function igt_<14>[ 25.435117] [IGT] kms_atomic: exiting, ret=77
12108 19:28:13.985541 require_intel, file ../lib/drmtest.c:880:
12109 19:28:13.995046 Test requirement: is_<8>[ 25.445230] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params RESULT=skip>
12110 19:28:13.995128 intel_device(fd)
12111 19:28:13.995366 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params RESULT=skip
12113 19:28:14.005315 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
12114 19:28:14.008497 Test requirement: is_intel_device(fd)
12115 19:28:14.011535 No KMS driver or no<14>[ 25.467380] [IGT] kms_atomic: executing
12116 19:28:14.018226 outputs, pipes:<14>[ 25.472483] [IGT] kms_atomic: exiting, ret=77
12117 19:28:14.021727 16, outputs: 0
12118 19:28:14.025170 [1mSubtest addfb25-4-tiled: SKIP (0.000s)[0m
12119 19:28:14.031482 <8>[ 25.482923] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip>
12120 19:28:14.031566
12121 19:28:14.031806 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip
12123 19:28:14.038347 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12124 19:28:14.041906 Using IGT_SRANDOM=1713468243 for randomisation
12125 19:28:14.045056 Opened device: /dev/dri/card0
12126 19:28:14.051456 No KMS drive<14>[ 25.504881] [IGT] kms_atomic: executing
12127 19:28:14.057915 r or no outputs,<14>[ 25.510515] [IGT] kms_atomic: exiting, ret=77
12128 19:28:14.058016 pipes: 16, outputs: 0
12129 19:28:14.071439 [1mSubtest plane-overlay-legacy: SKIP (<8>[ 25.521053] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic-invalid-params RESULT=skip>
12130 19:28:14.071533 0.000s)[0m
12131 19:28:14.071776 Received signal: <TESTCASE> TEST_CASE_ID=atomic-invalid-params RESULT=skip
12133 19:28:14.077993 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12134 19:28:14.081165 Using IGT_SRANDOM=1713468243 for randomisation
12135 19:28:14.085182 Opened device: /dev/dri/card0
12136 19:28:14.088455 <14>[ 25.543070] [IGT] kms_atomic: executing
12137 19:28:14.094718 No KMS driver or<14>[ 25.548165] [IGT] kms_atomic: exiting, ret=77
12138 19:28:14.097766 no outputs, pipes: 16, outputs: 0
12139 19:28:14.107955 [1mSubtest plane-primary-le<8>[ 25.558580] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic-plane-damage RESULT=skip>
12140 19:28:14.108231 Received signal: <TESTCASE> TEST_CASE_ID=atomic-plane-damage RESULT=skip
12142 19:28:14.110915 gacy: SKIP (0.000s)[0m
12143 19:28:14.114599 IGT-Ver<8>[ 25.568514] <LAVA_SIGNAL_TESTSET STOP>
12144 19:28:14.114854 Received signal: <TESTSET> STOP
12145 19:28:14.114924 Closing test_set kms_atomic
12146 19:28:14.121515 sion: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12147 19:28:14.124640 Using IGT_SRANDOM=1713468243 for randomisation
12148 19:28:14.127765 Opened device: /dev/dri/card0
12149 19:28:14.130953 No KMS driver or no outputs, pipes: 16, outputs: 0
12150 19:28:14.137987 <8>[ 25.589907] <LAVA_SIGNAL_TESTSET START kms_flip_event_leak>
12151 19:28:14.138242 Received signal: <TESTSET> START kms_flip_event_leak
12152 19:28:14.138319 Starting test_set kms_flip_event_leak
12153 19:28:14.144282 [1mSubtest plane-primary-overlay-mutable-zpos: SKIP (0.000s)[0m
12154 19:28:14.147951 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12155 19:28:14.157884 Using IGT_SRANDOM=1713468<14>[ 25.609553] [IGT] kms_flip_event_leak: executing
12156 19:28:14.164230 243 for randomis<14>[ 25.615824] [IGT] kms_flip_event_leak: exiting, ret=77
12157 19:28:14.164366 ation
12158 19:28:14.167375 Opened device: /dev/dri/card0
12159 19:28:14.174501 No KMS driver or no output<8>[ 25.627230] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
12160 19:28:14.174763 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
12162 19:28:14.177613 s, pipes: 16, outputs: 0
12163 19:28:14.181185 [1mSu<8>[ 25.635889] <LAVA_SIGNAL_TESTSET STOP>
12164 19:28:14.181437 Received signal: <TESTSET> STOP
12165 19:28:14.181505 Closing test_set kms_flip_event_leak
12166 19:28:14.188017 btest plane-immutable-zpos: SKIP (0.000s)[0m
12167 19:28:14.191355 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12168 19:28:14.197798 Using IGT_SRANDOM=1713468243 for randomisation
12169 19:28:14.204182 Opened device: /dev/dri/card0<8>[ 25.657764] <LAVA_SIGNAL_TESTSET START kms_prop_blob>
12170 19:28:14.204269
12171 19:28:14.204508 Received signal: <TESTSET> START kms_prop_blob
12172 19:28:14.204578 Starting test_set kms_prop_blob
12173 19:28:14.207419 No KMS driver or no outputs, pipes: 16, outputs: 0
12174 19:28:14.211142 [1mSubtest test-only: SKIP (0.000s)[0m
12175 19:28:14.217234 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12176 19:28:14.224024 Using IGT_SR<14>[ 25.678162] [IGT] kms_prop_blob: executing
12177 19:28:14.230543 ANDOM=1713468243<14>[ 25.683428] [IGT] kms_prop_blob: starting subtest basic
12178 19:28:14.237463 for randomisati<14>[ 25.690155] [IGT] kms_prop_blob: finished subtest basic, SUCCESS
12179 19:28:14.240536 on
12180 19:28:14.243884 Opened devic<14>[ 25.697920] [IGT] kms_prop_blob: exiting, ret=0
12181 19:28:14.247044 e: /dev/dri/card0
12182 19:28:14.257197 No KMS driver or no outputs, pipes: 16, outpu<8>[ 25.708582] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
12183 19:28:14.257286 ts: 0
12184 19:28:14.257526 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
12186 19:28:14.263800 [1mSubtest plane-cursor-legacy: SKIP (0.000s)[0m
12187 19:28:14.266974 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12188 19:28:14.277222 Using IGT_SRANDOM=1713468243 for <14>[ 25.729608] [IGT] kms_prop_blob: executing
12189 19:28:14.277307 randomisation
12190 19:28:14.283872 O<14>[ 25.735072] [IGT] kms_prop_blob: starting subtest blob-prop-core
12191 19:28:14.290734 pened device: /d<14>[ 25.742479] [IGT] kms_prop_blob: finished subtest blob-prop-core, SUCCESS
12192 19:28:14.293503 ev/dri/card0
12193 19:28:14.296951 No<14>[ 25.751036] [IGT] kms_prop_blob: exiting, ret=0
12194 19:28:14.303400 KMS driver or no outputs, pipes: 16, outputs: 0
12195 19:28:14.310249 [1mSubtest pl<8>[ 25.761667] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-core RESULT=pass>
12196 19:28:14.310561 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-core RESULT=pass
12198 19:28:14.313557 ane-invalid-params: SKIP (0.000s)[0m
12199 19:28:14.320749 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12200 19:28:14.323815 Using IGT_SRANDOM=1713468243 for randomisation
12201 19:28:14.330729 Opene<14>[ 25.783471] [IGT] kms_prop_blob: executing
12202 19:28:14.337173 d device: /dev/d<14>[ 25.788712] [IGT] kms_prop_blob: starting subtest blob-prop-validate
12203 19:28:14.337257 ri/card0
12204 19:28:14.346955 No KMS<14>[ 25.796671] [IGT] kms_prop_blob: finished subtest blob-prop-validate, SUCCESS
12205 19:28:14.353561 driver or no ou<14>[ 25.805542] [IGT] kms_prop_blob: exiting, ret=0
12206 19:28:14.356462 tputs, pipes: 16, outputs: 0
12207 19:28:14.366701 [1mSubtest plane-invalid-params-f<8>[ 25.816140] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-validate RESULT=pass>
12208 19:28:14.366790 ence: SKIP (0.000s)[0m
12209 19:28:14.367031 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-validate RESULT=pass
12211 19:28:14.373424 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12212 19:28:14.376349 Using IGT_SRANDOM=1713468243 for randomisation
12213 19:28:14.383481 Opened device: /dev<14>[ 25.838186] [IGT] kms_prop_blob: executing
12214 19:28:14.386583 /dri/card0
12215 19:28:14.393160 No K<14>[ 25.843633] [IGT] kms_prop_blob: starting subtest blob-prop-lifetime
12216 19:28:14.399929 MS driver or no <14>[ 25.851575] [IGT] kms_prop_blob: finished subtest blob-prop-lifetime, SUCCESS
12217 19:28:14.406242 outputs, pipes: <14>[ 25.860408] [IGT] kms_prop_blob: exiting, ret=0
12218 19:28:14.409545 16, outputs: 0
12219 19:28:14.419377 [1mSubtest crtc-invalid-params: SKIP (0.000s)[<8>[ 25.871575] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-lifetime RESULT=pass>
12220 19:28:14.419474 0m
12221 19:28:14.419717 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-lifetime RESULT=pass
12223 19:28:14.425775 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12224 19:28:14.432917 Using IGT_SRANDOM=1713468243 for randomisation
12225 19:28:14.433009 Opened device: /dev/dri/card0
12226 19:28:14.439587 No KMS dr<14>[ 25.893053] [IGT] kms_prop_blob: executing
12227 19:28:14.445795 iver or no outpu<14>[ 25.898498] [IGT] kms_prop_blob: starting subtest blob-multiple
12228 19:28:14.455816 ts, pipes: 16, o<14>[ 25.906076] [IGT] kms_prop_blob: finished subtest blob-multiple, SUCCESS
12229 19:28:14.455940 utputs: 0
12230 19:28:14.462708 [1mS<14>[ 25.914436] [IGT] kms_prop_blob: exiting, ret=0
12231 19:28:14.466213 ubtest crtc-invalid-params-fence: SKIP (0.000s)[0m
12232 19:28:14.473011 IGT-Version<8>[ 25.925085] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-multiple RESULT=pass>
12233 19:28:14.473292 Received signal: <TESTCASE> TEST_CASE_ID=blob-multiple RESULT=pass
12235 19:28:14.479507 : 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12236 19:28:14.482405 Using IGT_SRANDOM=1713468243 for randomisation
12237 19:28:14.486128 Opened device: /dev/dri/card0
12238 19:28:14.492459 No KMS driver or no outp<14>[ 25.946651] [IGT] kms_prop_blob: executing
12239 19:28:14.502523 uts, pipes: 16, <14>[ 25.952077] [IGT] kms_prop_blob: starting subtest invalid-get-prop-any
12240 19:28:14.502638 outputs: 0
12241 19:28:14.508634 [1m<14>[ 25.960118] [IGT] kms_prop_blob: finished subtest invalid-get-prop-any, SUCCESS
12242 19:28:14.515807 Subtest atomic-i<14>[ 25.969337] [IGT] kms_prop_blob: exiting, ret=0
12243 19:28:14.519006 nvalid-params: SKIP (0.000s)[0m
12244 19:28:14.528510 IGT-Version: 1.28-ga44ebfe (aa<8>[ 25.979922] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
12245 19:28:14.528854 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
12247 19:28:14.531779 rch64) (Linux: 6.1.86-cip19 aarch64)
12248 19:28:14.535616 Using IGT_SRANDOM=1713468243 for randomisation
12249 19:28:14.538900 Opened device: /dev/dri/card0
12250 19:28:14.548878 No KMS driver or no outputs, pipes: 16, out<14>[ 26.002200] [IGT] kms_prop_blob: executing
12251 19:28:14.549035 puts: 0
12252 19:28:14.555250 [1mSub<14>[ 26.007551] [IGT] kms_prop_blob: starting subtest invalid-get-prop
12253 19:28:14.565320 test atomic-plan<14>[ 26.015369] [IGT] kms_prop_blob: finished subtest invalid-get-prop, SUCCESS
12254 19:28:14.571870 e-damage: SKIP (<14>[ 26.023960] [IGT] kms_prop_blob: exiting, ret=0
12255 19:28:14.571962 0.000s)[0m
12256 19:28:14.584985 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86<8>[ 26.035125] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
12257 19:28:14.585089 -cip19 aarch64)
12258 19:28:14.585332 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
12260 19:28:14.588483 Using IGT_SRANDOM=1713468243 for randomisation
12261 19:28:14.591893 Opened device: /dev/dri/card0
12262 19:28:14.598185 No KMS driver or no outputs, pipes: 16, outputs: 0
12263 19:28:14.605115 [1mSubtest basic: SKIP (0.0<14>[ 26.057063] [IGT] kms_prop_blob: executing
12264 19:28:14.605223 00s)[0m
12265 19:28:14.611578 IGT-Ve<14>[ 26.063257] [IGT] kms_prop_blob: starting subtest invalid-set-prop-any
12266 19:28:14.622195 rsion: 1.28-ga44<14>[ 26.071411] [IGT] kms_prop_blob: finished subtest invalid-set-prop-any, SUCCESS
12267 19:28:14.628065 ebfe (aarch64) (<14>[ 26.080440] [IGT] kms_prop_blob: exiting, ret=0
12268 19:28:14.631778 Linux: 6.1.86-cip19 aarch64)
12269 19:28:14.641292 Using IGT_SRANDOM=1713468243 for r<8>[ 26.091238] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
12270 19:28:14.641440 andomisation
12271 19:28:14.641748 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
12273 19:28:14.644579 Opened device: /dev/dri/card0
12274 19:28:14.648441 Starting subtest: basic
12275 19:28:14.651761 [1mSubtest basic: SUCCESS (0.000s)[0m
12276 19:28:14.658291 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.<14>[ 26.113005] [IGT] kms_prop_blob: executing
12277 19:28:14.668039 86-cip19 aarch64<14>[ 26.118637] [IGT] kms_prop_blob: starting subtest invalid-set-prop
12278 19:28:14.668208 )
12279 19:28:14.674396 Using IGT_SRA<14>[ 26.126410] [IGT] kms_prop_blob: finished subtest invalid-set-prop, SUCCESS
12280 19:28:14.681662 NDOM=1713468243 <14>[ 26.135127] [IGT] kms_prop_blob: exiting, ret=0
12281 19:28:14.684810 for randomisation
12282 19:28:14.688034 Opened device: /dev/dri/card0
12283 19:28:14.694465 Starting subte<8>[ 26.145839] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
12284 19:28:14.694811 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
12286 19:28:14.697892 st: blob-prop-core
12287 19:28:14.701434 [1mSubtest <8>[ 26.155920] <LAVA_SIGNAL_TESTSET STOP>
12288 19:28:14.701688 Received signal: <TESTSET> STOP
12289 19:28:14.701760 Closing test_set kms_prop_blob
12290 19:28:14.704601 blob-prop-core: SUCCESS (0.000s)[0m
12291 19:28:14.711047 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12292 19:28:14.714625 Using IGT_SRANDOM=1713468243 for randomisation
12293 19:28:14.717652 Opened device: /dev/dri/card0
12294 19:28:14.724261 Starting subtest: blob-<8>[ 26.178165] <LAVA_SIGNAL_TESTSET START kms_setmode>
12295 19:28:14.724529 Received signal: <TESTSET> START kms_setmode
12296 19:28:14.724604 Starting test_set kms_setmode
12297 19:28:14.727739 prop-validate
12298 19:28:14.730917 [1mSubtest blob-prop-validate: SUCCESS (0.000s)[0m
12299 19:28:14.737629 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12300 19:28:14.744455 Using IGT_SRANDOM=17134<14>[ 26.198138] [IGT] kms_setmode: executing
12301 19:28:14.744545 68243 for randomisation
12302 19:28:14.750818 Opened <14>[ 26.204271] [IGT] kms_setmode: starting subtest basic
12303 19:28:14.757291 device: /dev/dri<14>[ 26.212046] [IGT] kms_setmode: finished subtest basic, SKIP
12304 19:28:14.760900 /card0
12305 19:28:14.764035 Starting<14>[ 26.218288] [IGT] kms_setmode: exiting, ret=77
12306 19:28:14.767221 subtest: blob-prop-lifetime
12307 19:28:14.776971 [1mSubtest blob-prop-lifetime: SU<8>[ 26.229159] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
12308 19:28:14.777067 CCESS (0.000s)[0m
12309 19:28:14.777310 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
12311 19:28:14.784068 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12312 19:28:14.787341 Using IGT_SRANDOM=1713468243 for randomisation
12313 19:28:14.790718 Opened device: /dev/dri/card0
12314 19:28:14.797206 Starting <14>[ 26.250157] [IGT] kms_setmode: executing
12315 19:28:14.803608 subtest: blob-mu<14>[ 26.256262] [IGT] kms_setmode: starting subtest basic-clone-single-crtc
12316 19:28:14.807491 ltiple
12317 19:28:14.814125 [1mSubt<14>[ 26.264215] [IGT] kms_setmode: finished subtest basic-clone-single-crtc, SKIP
12318 19:28:14.820349 est blob-multipl<14>[ 26.273240] [IGT] kms_setmode: exiting, ret=77
12319 19:28:14.824054 e: SUCCESS (0.000s)[0m
12320 19:28:14.833439 IGT-Version: 1.28-ga44ebfe (aarch64) (L<8>[ 26.283643] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-clone-single-crtc RESULT=skip>
12321 19:28:14.833766 Received signal: <TESTCASE> TEST_CASE_ID=basic-clone-single-crtc RESULT=skip
12323 19:28:14.836895 inux: 6.1.86-cip19 aarch64)
12324 19:28:14.840337 Using IGT_SRANDOM=1713468243 for randomisation
12325 19:28:14.843980 Opened device: /dev/dri/card0
12326 19:28:14.846765 Starting subtest: invalid-get-prop-any
12327 19:28:14.850022 [1mSubtest <14>[ 26.305995] [IGT] kms_setmode: executing
12328 19:28:14.860376 invalid-get-prop<14>[ 26.311495] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc
12329 19:28:14.870158 -any: SUCCESS (0<14>[ 26.319715] [IGT] kms_setmode: finished subtest invalid-clone-single-crtc, SKIP
12330 19:28:14.870260 .000s)[0m
12331 19:28:14.876462 IGT-<14>[ 26.328755] [IGT] kms_setmode: exiting, ret=77
12332 19:28:14.880120 Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12333 19:28:14.889786 <8>[ 26.339529] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip>
12334 19:28:14.890051 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip
12336 19:28:14.892960 Using IGT_SRANDOM=1713468243 for randomisation
12337 19:28:14.896236 Opened device: /dev/dri/card0
12338 19:28:14.899489 Starting subtest: invalid-get-prop
12339 19:28:14.906029 [1mSubtest invalid-get-prop: SUCCESS (0.000s<14>[ 26.361835] [IGT] kms_setmode: executing
12340 19:28:14.909868 )[0m
12341 19:28:14.916276 IGT-Versi<14>[ 26.367267] [IGT] kms_setmode: starting subtest invalid-clone-exclusive-crtc
12342 19:28:14.926193 on: 1.28-ga44ebf<14>[ 26.375745] [IGT] kms_setmode: finished subtest invalid-clone-exclusive-crtc, SKIP
12343 19:28:14.932528 e (aarch64) (Lin<14>[ 26.385110] [IGT] kms_setmode: exiting, ret=77
12344 19:28:14.936354 ux: 6.1.86-cip19 aarch64)
12345 19:28:14.939296 Using IGT_SRANDOM=1713468243 for randomisation
12346 19:28:14.945774 Opene<8>[ 26.396974] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip>
12347 19:28:14.946035 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip
12349 19:28:14.949403 d device: /dev/dri/card0
12350 19:28:14.952611 Starting subtest: invalid-set-prop-any
12351 19:28:14.958958 [1mSubtest invalid-set-prop-any: SUCCESS (0.000s)[0m
12352 19:28:14.965609 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-ci<14>[ 26.421426] [IGT] kms_setmode: executing
12353 19:28:14.969079 p19 aarch64)
12354 19:28:14.975844 Us<14>[ 26.426592] [IGT] kms_setmode: starting subtest clone-exclusive-crtc
12355 19:28:14.982454 ing IGT_SRANDOM=<14>[ 26.434486] [IGT] kms_setmode: finished subtest clone-exclusive-crtc, SKIP
12356 19:28:14.989123 1713468244 for r<14>[ 26.443128] [IGT] kms_setmode: exiting, ret=77
12357 19:28:14.992062 andomisation
12358 19:28:14.992147 Opened device: /dev/dri/card0
12359 19:28:15.002002 Starting subtest: i<8>[ 26.454208] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clone-exclusive-crtc RESULT=skip>
12360 19:28:15.002268 Received signal: <TESTCASE> TEST_CASE_ID=clone-exclusive-crtc RESULT=skip
12362 19:28:15.005313 nvalid-set-prop
12363 19:28:15.009307 [1mSubtest invalid-set-prop: SUCCESS (0.000s)[0m
12364 19:28:15.015712 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12365 19:28:15.022152 Using IGT_SRANDOM=17134<14>[ 26.476008] [IGT] kms_setmode: executing
12366 19:28:15.032290 68244 for random<14>[ 26.481215] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc-stealing
12367 19:28:15.032386 isation
12368 19:28:15.042184 Opened <14>[ 26.490114] [IGT] kms_setmode: finished subtest invalid-clone-single-crtc-stealing, SKIP
12369 19:28:15.045169 device: /dev/dri<14>[ 26.499988] [IGT] kms_setmode: exiting, ret=77
12370 19:28:15.048808 /card0
12371 19:28:15.048888 Starting subtest: basic
12372 19:28:15.052012 No dynamic tests executed.
12373 19:28:15.061799 [1mSubtest basic: <8>[ 26.512285] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip>
12374 19:28:15.062056 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip
12376 19:28:15.065673 SKIP (0.000s)[0m
12377 19:28:15.068828 IGT-Version: <8>[ 26.523763] <LAVA_SIGNAL_TESTSET STOP>
12378 19:28:15.069079 Received signal: <TESTSET> STOP
12379 19:28:15.069147 Closing test_set kms_setmode
12380 19:28:15.075517 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12381 19:28:15.078599 Using IGT_SRANDOM=1713468244 for randomisation
12382 19:28:15.082015 Opened device: /dev/dri/card0
12383 19:28:15.084970 Starting subtest: basic-clone-single-crtc
12384 19:28:15.088728 No dynamic tests executed.
12385 19:28:15.092050 [1mSubtest basic-clone-single-crtc: SKIP (0.000s)[0m
12386 19:28:15.101611 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 a<8>[ 26.555706] <LAVA_SIGNAL_TESTSET START kms_vblank>
12387 19:28:15.101693 arch64)
12388 19:28:15.101927 Received signal: <TESTSET> START kms_vblank
12389 19:28:15.101992 Starting test_set kms_vblank
12390 19:28:15.108469 Using IGT_SRANDOM=1713468244 for randomisation
12391 19:28:15.108550 Opened device: /dev/dri/card0
12392 19:28:15.115207 Starting subtest: invalid-clone-single-crtc
12393 19:28:15.115287 No dynamic tests executed.
12394 19:28:15.121578 [1mSubtest invalid-clone-single-crtc: SKIP (0.000s)[0m
12395 19:28:15.131469 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-c<14>[ 26.584117] [IGT] kms_vblank: executing
12396 19:28:15.131551 ip19 aarch64)
12397 19:28:15.135287 U<14>[ 26.590254] [IGT] kms_vblank: exiting, ret=77
12398 19:28:15.141310 sing IGT_SRANDOM=1713468244 for randomisation
12399 19:28:15.141390 Opened device: /dev/dri/card0
12400 19:28:15.148108 Received signal: <TESTCASE> TEST_CASE_ID=invalid RESULT=skip
12402 19:28:15.151110 St<8>[ 26.601517] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid RESULT=skip>
12403 19:28:15.154755 arting subtest: invalid-clone-exclusive-crtc
12404 19:28:15.154836 No dynamic tests executed.
12405 19:28:15.161367 [1mSubtest invalid-clone-exclusive-crtc: SKIP (0.000s)[0m
12406 19:28:15.168298 IGT-Version: 1.28-ga44ebfe (aarch64) (Lin<14>[ 26.623750] [IGT] kms_vblank: executing
12407 19:28:15.174570 ux: 6.1.86-cip19<14>[ 26.629032] [IGT] kms_vblank: exiting, ret=77
12408 19:28:15.178088 aarch64)
12409 19:28:15.181107 Using IGT_SRANDOM=1713468244 for randomisation
12410 19:28:15.184375 Opened device: /dev/dri/card0
12411 19:28:15.191373 Starti<8>[ 26.642277] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-id RESULT=skip>
12412 19:28:15.191627 Received signal: <TESTCASE> TEST_CASE_ID=crtc-id RESULT=skip
12414 19:28:15.194475 ng subtest: clone-exclusive-crtc
12415 19:28:15.194557 No dynamic tests executed.
12416 19:28:15.200931 [1mSubtest clone-exclusive-crtc: SKIP (0.000s)[0m
12417 19:28:15.210931 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aar<14>[ 26.664055] [IGT] kms_vblank: executing
12418 19:28:15.211013 ch64)
12419 19:28:15.214492 Using IGT<14>[ 26.669580] [IGT] kms_vblank: exiting, ret=77
12420 19:28:15.220959 _SRANDOM=1713468244 for randomisation
12421 19:28:15.221040 Opened device: /dev/dri/card0
12422 19:28:15.231362 Starting s<8>[ 26.681599] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=accuracy-idle RESULT=skip>
12423 19:28:15.231618 Received signal: <TESTCASE> TEST_CASE_ID=accuracy-idle RESULT=skip
12425 19:28:15.234108 ubtest: invalid-clone-single-crtc-stealing
12426 19:28:15.237552 No dynamic tests executed.
12427 19:28:15.241419 [1mSubtest invalid-clone-single-crtc-stealing: SKIP (0.000s)[0m
12428 19:28:15.247631 IGT-Version: 1.28-ga4<14>[ 26.703216] [IGT] kms_vblank: executing
12429 19:28:15.254114 4ebfe (aarch64) <14>[ 26.707930] [IGT] kms_vblank: exiting, ret=77
12430 19:28:15.257897 (Linux: 6.1.86-cip19 aarch64)
12431 19:28:15.261062 Using IGT_SRANDOM=1713468244 for randomisation
12432 19:28:15.271452 Opened device: /d<8>[ 26.721728] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-idle RESULT=skip>
12433 19:28:15.271538 ev/dri/card0
12434 19:28:15.271781 Received signal: <TESTCASE> TEST_CASE_ID=query-idle RESULT=skip
12436 19:28:15.274271 No KMS driver or no outputs, pipes: 16, outputs: 0
12437 19:28:15.277812 [1mSubtest invalid: SKIP (0.000s)[0m
12438 19:28:15.287468 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-ci<14>[ 26.742318] [IGT] kms_vblank: executing
12439 19:28:15.287557 p19 aarch64)
12440 19:28:15.294265 Us<14>[ 26.747438] [IGT] kms_vblank: exiting, ret=77
12441 19:28:15.297353 ing IGT_SRANDOM=1713468244 for randomisation
12442 19:28:15.307053 Opened device: /de<8>[ 26.758282] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-idle-hang RESULT=skip>
12443 19:28:15.307137 v/dri/card0
12444 19:28:15.307375 Received signal: <TESTCASE> TEST_CASE_ID=query-idle-hang RESULT=skip
12446 19:28:15.311078 No KMS driver or no outputs, pipes: 16, outputs: 0
12447 19:28:15.317411 [1mSubtest crtc-id: SKIP (0.000s)[0m
12448 19:28:15.320637 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12449 19:28:15.327038 Using IGT_SRANDOM=1713468244 for randomisation
12450 19:28:15.327119 Opened device: /dev/dri/card0
12451 19:28:15.333698 No KMS driver or no <14>[ 26.789344] [IGT] kms_vblank: executing
12452 19:28:15.340643 outputs, pipes: <14>[ 26.794495] [IGT] kms_vblank: exiting, ret=77
12453 19:28:15.340726 16, outputs: 0
12454 19:28:15.347316 [1mSubtest accuracy-idle: SKIP (0.000s)[0m
12455 19:28:15.353357 IG<8>[ 26.805219] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked RESULT=skip>
12456 19:28:15.353612 Received signal: <TESTCASE> TEST_CASE_ID=query-forked RESULT=skip
12458 19:28:15.360424 T-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12459 19:28:15.363449 Using IGT_SRANDOM=1713468244 for randomisation
12460 19:28:15.366628 Opened device: /dev/dri/card0
12461 19:28:15.373789 No KMS driver or no outputs, pi<14>[ 26.827207] [IGT] kms_vblank: executing
12462 19:28:15.380273 pes: 16, outputs<14>[ 26.832321] [IGT] kms_vblank: exiting, ret=77
12463 19:28:15.380355 : 0
12464 19:28:15.383408 [1mSubtest query-idle: SKIP (0.000s)[0m
12465 19:28:15.393329 IGT-Version: 1.28-ga44ebfe (aarc<8>[ 26.844327] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked-hang RESULT=skip>
12466 19:28:15.393583 Received signal: <TESTCASE> TEST_CASE_ID=query-forked-hang RESULT=skip
12468 19:28:15.396427 h64) (Linux: 6.1.86-cip19 aarch64)
12469 19:28:15.400054 Using IGT_SRANDOM=1713468244 for randomisation
12470 19:28:15.403407 Opened device: /dev/dri/card0
12471 19:28:15.406736 No KMS driver or no outputs, pipes: 16, outputs: 0
12472 19:28:15.413235 [1mSubtest query-idle-hang: SKIP (0.000s)[0m
12473 19:28:15.419700 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19<14>[ 26.875654] [IGT] kms_vblank: executing
12474 19:28:15.423662 aarch64)
12475 19:28:15.426782 Using<14>[ 26.880947] [IGT] kms_vblank: exiting, ret=77
12476 19:28:15.430008 IGT_SRANDOM=1713468244 for randomisation
12477 19:28:15.433411 Opened device: /dev/dri/card0
12478 19:28:15.436567 No KMS driver or no outputs, pipes: 16, outputs: 0
12479 19:28:15.443524 Received signal: <TESTCASE> TEST_CASE_ID=query-busy RESULT=skip
12481 19:28:15.446379 [<8>[ 26.896727] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-busy RESULT=skip>
12482 19:28:15.449590 1mSubtest query-forked: SKIP (0.000s)[0m
12483 19:28:15.453213 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12484 19:28:15.459545 Using IGT_SRANDOM=1713468244 for randomisation
12485 19:28:15.463294 Opened device: /dev/dri/card0
12486 19:28:15.466390 No KMS driver or no outputs, pipes: 16, outputs: 0
12487 19:28:15.472716 [1mSubtest query-forked-hang: SKIP (0.000s)[<14>[ 26.928266] [IGT] kms_vblank: executing
12488 19:28:15.475865 0m
12489 19:28:15.479259 IGT-Version:<14>[ 26.934252] [IGT] kms_vblank: exiting, ret=77
12490 19:28:15.485998 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12491 19:28:15.492965 Using IG<8>[ 26.945164] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-busy-hang RESULT=skip>
12492 19:28:15.493228 Received signal: <TESTCASE> TEST_CASE_ID=query-busy-hang RESULT=skip
12494 19:28:15.496141 T_SRANDOM=1713468244 for randomisation
12495 19:28:15.499156 Opened device: /dev/dri/card0
12496 19:28:15.502908 No KMS driver or no outputs, pipes: 16, outputs: 0
12497 19:28:15.505946 [1mSubtest query-busy: SKIP (0.000s)[0m
12498 19:28:15.512718 IGT-Versio<14>[ 26.966419] [IGT] kms_vblank: executing
12499 19:28:15.519249 n: 1.28-ga44ebfe<14>[ 26.972461] [IGT] kms_vblank: exiting, ret=77
12500 19:28:15.522484 (aarch64) (Linux: 6.1.86-cip19 aarch64)
12501 19:28:15.532838 Using IGT_SRANDOM=1713468244 for rando<8>[ 26.983681] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked-busy RESULT=skip>
12502 19:28:15.532923 misation
12503 19:28:15.533164 Received signal: <TESTCASE> TEST_CASE_ID=query-forked-busy RESULT=skip
12505 19:28:15.536348 Opened device: /dev/dri/card0
12506 19:28:15.542510 No KMS driver or no outputs, pipes: 16, outputs: 0
12507 19:28:15.545668 [1mSubtest query-busy-hang: SKIP (0.000s)[0m
12508 19:28:15.552331 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12509 19:28:15.555575 Using IGT_SRANDOM=1713468244 for randomisation
12510 19:28:15.562505 Opened device: <14>[ 27.016057] [IGT] kms_vblank: executing
12511 19:28:15.562621 /dev/dri/card0
12512 19:28:15.565626 <14>[ 27.021062] [IGT] kms_vblank: exiting, ret=77
12513 19:28:15.572532 No KMS driver or no outputs, pipes: 16, outputs: 0
12514 19:28:15.575750 [1mSubtest query-forked-busy: SKIP (0.000s)[0m
12515 19:28:15.585700 IGT-Version: 1.28-ga44ebfe<8>[ 27.036673] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked-busy-hang RESULT=skip>
12516 19:28:15.586015 Received signal: <TESTCASE> TEST_CASE_ID=query-forked-busy-hang RESULT=skip
12518 19:28:15.588990 (aarch64) (Linux: 6.1.86-cip19 aarch64)
12519 19:28:15.592402 Using IGT_SRANDOM=1713468244 for randomisation
12520 19:28:15.595382 Opened device: /dev/dri/card0
12521 19:28:15.602387 No KMS driver or no outputs, pipes: 16, outputs: 0
12522 19:28:15.605472 [1<14>[ 27.060038] [IGT] kms_vblank: executing
12523 19:28:15.612340 mSubtest query-f<14>[ 27.065358] [IGT] kms_vblank: exiting, ret=77
12524 19:28:15.615539 orked-busy-hang: SKIP (0.000s)[0m
12525 19:28:15.625886 IGT-Version: 1.28-ga44ebfe (<8>[ 27.076484] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-idle RESULT=skip>
12526 19:28:15.626188 Received signal: <TESTCASE> TEST_CASE_ID=wait-idle RESULT=skip
12528 19:28:15.628528 aarch64) (Linux: 6.1.86-cip19 aarch64)
12529 19:28:15.632386 Using IGT_SRANDOM=1713468244 for randomisation
12530 19:28:15.635517 Opened device: /dev/dri/card0
12531 19:28:15.638841 No KMS driver or no outputs, pipes: 16, outputs: 0
12532 19:28:15.642043 [1mSubtest wait-idle: SKIP (0.000s)[0m
12533 19:28:15.652812 <14>[ 27.107006] [IGT] kms_vblank: executing
12534 19:28:15.659156 IGT-Version: 1.2<14>[ 27.111977] [IGT] kms_vblank: exiting, ret=77
12535 19:28:15.662755 8-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12536 19:28:15.666027 Using IGT_SRANDOM=1713468245 for randomisation
12537 19:28:15.675773 Opened device: /dev/dri/card<8>[ 27.127860] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-idle-hang RESULT=skip>
12538 19:28:15.675863 0
12539 19:28:15.676105 Received signal: <TESTCASE> TEST_CASE_ID=wait-idle-hang RESULT=skip
12541 19:28:15.682837 No KMS driver or no outputs, pipes: 16, outputs: 0
12542 19:28:15.685883 [1mSubtest wait-idle-hang: SKIP (0.000s)[0m
12543 19:28:15.696006 <14>[ 27.150372] [IGT] kms_vblank: executing
12544 19:28:15.702421 IGT-Version: 1.2<14>[ 27.155127] [IGT] kms_vblank: exiting, ret=77
12545 19:28:15.706166 8-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12546 19:28:15.715904 Using IGT_SRANDOM=1713468245<8>[ 27.167177] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked RESULT=skip>
12547 19:28:15.715998 for randomisation
12548 19:28:15.716238 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked RESULT=skip
12550 19:28:15.719305 Opened device: /dev/dri/card0
12551 19:28:15.726171 No KMS driver or no outputs, pipes: 16, outputs: 0
12552 19:28:15.728993 [1mSubtest wait-forked: SKIP (0.000s)[0m
12553 19:28:15.743661 <14>[ 27.197854] [IGT] kms_vblank: executing
12554 19:28:15.749861 IGT-Version: 1.2<14>[ 27.202889] [IGT] kms_vblank: exiting, ret=77
12555 19:28:15.753600 8-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12556 19:28:15.756820 Using IGT_SRANDOM=1713468245 for randomisation
12557 19:28:15.766729 Opened device: /dev/dri/card<8>[ 27.218558] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked-hang RESULT=skip>
12558 19:28:15.766826 0
12559 19:28:15.767067 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked-hang RESULT=skip
12561 19:28:15.772879 No KMS driver or no outputs, pipes: 16, outputs: 0
12562 19:28:15.776709 [1mSubtest wait-forked-hang: SKIP (0.000s)[0m
12563 19:28:15.796990 <14>[ 27.251376] [IGT] kms_vblank: executing
12564 19:28:15.803808 IGT-Version: 1.2<14>[ 27.256376] [IGT] kms_vblank: exiting, ret=77
12565 19:28:15.806993 8-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12566 19:28:15.810185 Using IGT_SRANDOM=1713468245 for randomisation
12567 19:28:15.820212 Opened device: /dev/dri/card<8>[ 27.272378] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-busy RESULT=skip>
12568 19:28:15.820316 0
12569 19:28:15.820545 Received signal: <TESTCASE> TEST_CASE_ID=wait-busy RESULT=skip
12571 19:28:15.824020 No KMS driver or no outputs, pipes: 16, outputs: 0
12572 19:28:15.830912 [1mSubtest wait-busy: SKIP (0.000s)[0m
12573 19:28:15.840351 <14>[ 27.294377] [IGT] kms_vblank: executing
12574 19:28:15.846576 IGT-Version: 1.2<14>[ 27.299131] [IGT] kms_vblank: exiting, ret=77
12575 19:28:15.849813 8-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12576 19:28:15.859958 Using IGT_SRANDOM=1713468245<8>[ 27.311255] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-busy-hang RESULT=skip>
12577 19:28:15.860081 for randomisation
12578 19:28:15.860323 Received signal: <TESTCASE> TEST_CASE_ID=wait-busy-hang RESULT=skip
12580 19:28:15.863602 Opened device: /dev/dri/card0
12581 19:28:15.870085 No KMS driver or no outputs, pipes: 16, outputs: 0
12582 19:28:15.873058 [1mSubtest wait-busy-hang: SKIP (0.000s)[0m
12583 19:28:15.876550 <14>[ 27.332333] [IGT] kms_vblank: executing
12584 19:28:15.883507 IGT-Version: 1.2<14>[ 27.336987] [IGT] kms_vblank: exiting, ret=77
12585 19:28:15.886611 8-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12586 19:28:15.896832 Using IGT_SRANDOM=1713468245<8>[ 27.349332] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked-busy RESULT=skip>
12587 19:28:15.897144 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked-busy RESULT=skip
12589 19:28:15.899869 for randomisation
12590 19:28:15.902903 Opened device: /dev/dri/card0
12591 19:28:15.906292 No KMS driver or no outputs, pipes: 16, outputs: 0
12592 19:28:15.909757 [1mSubtest wait-forked-busy: SKIP (0.000s)[0m
12593 19:28:15.926474 <14>[ 27.380692] [IGT] kms_vblank: executing
12594 19:28:15.933193 IGT-Version: 1.2<14>[ 27.385687] [IGT] kms_vblank: exiting, ret=77
12595 19:28:15.936432 8-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12596 19:28:15.946336 Using IGT_SRANDOM=1713468245<8>[ 27.397819] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked-busy-hang RESULT=skip>
12597 19:28:15.946639 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked-busy-hang RESULT=skip
12599 19:28:15.949486 for randomisation
12600 19:28:15.949570 Opened device: /dev/dri/card0
12601 19:28:15.956167 No KMS driver or no outputs, pipes: 16, outputs: 0
12602 19:28:15.960121 [1mSubtest wait-forked-busy-hang: SKIP (0.000s)[0m
12603 19:28:15.966513 <14>[ 27.420283] [IGT] kms_vblank: executing
12604 19:28:15.969947 IGT-Version: 1.2<14>[ 27.424916] [IGT] kms_vblank: exiting, ret=77
12605 19:28:15.976340 8-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12606 19:28:15.986080 Using IGT_SRANDOM=1713468245<8>[ 27.437205] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-idle RESULT=skip>
12607 19:28:15.986207 for randomisation
12608 19:28:15.986451 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-idle RESULT=skip
12610 19:28:15.989356 Opened device: /dev/dri/card0
12611 19:28:15.996369 No KMS driver or no outputs, pipes: 16, outputs: 0
12612 19:28:15.999388 [1mSubtest ts-continuation-idle: SKIP (0.000s)[0m
12613 19:28:16.013986 <14>[ 27.468309] [IGT] kms_vblank: executing
12614 19:28:16.020920 IGT-Version: 1.2<14>[ 27.473287] [IGT] kms_vblank: exiting, ret=77
12615 19:28:16.024616 8-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12616 19:28:16.033747 Using IGT_SRANDOM=1713468245<8>[ 27.485756] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-idle-hang RESULT=skip>
12617 19:28:16.034074 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-idle-hang RESULT=skip
12619 19:28:16.037363 for randomisation
12620 19:28:16.040525 Opened device: /dev/dri/card0
12621 19:28:16.043778 No KMS driver or no outputs, pipes: 16, outputs: 0
12622 19:28:16.046931 [1mSubtest ts-continuation-idle-hang: SKIP (0.000s)[0m
12623 19:28:16.053780 <14>[ 27.508252] [IGT] kms_vblank: executing
12624 19:28:16.060639 IGT-Version: 1.2<14>[ 27.512895] [IGT] kms_vblank: exiting, ret=77
12625 19:28:16.063649 8-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12626 19:28:16.073664 Using IGT_SRANDOM=1713468245<8>[ 27.525272] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-dpms-rpm RESULT=skip>
12627 19:28:16.073991 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-dpms-rpm RESULT=skip
12629 19:28:16.077321 for randomisation
12630 19:28:16.080112 Opened device: /dev/dri/card0
12631 19:28:16.083544 No KMS driver or no outputs, pipes: 16, outputs: 0
12632 19:28:16.086550 [1mSubtest ts-continuation-dpms-rpm: SKIP (0.000s)[0m
12633 19:28:16.103224 <14>[ 27.557069] [IGT] kms_vblank: executing
12634 19:28:16.109962 IGT-Version: 1.2<14>[ 27.562088] [IGT] kms_vblank: exiting, ret=77
12635 19:28:16.113061 8-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12636 19:28:16.116120 Using IGT_SRANDOM=1713468245 for randomisation
12637 19:28:16.125856 Opened devic<8>[ 27.577190] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-dpms-suspend RESULT=skip>
12638 19:28:16.126170 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-dpms-suspend RESULT=skip
12640 19:28:16.129529 e: /dev/dri/card0
12641 19:28:16.132731 No KMS driver or no outputs, pipes: 16, outputs: 0
12642 19:28:16.138980 [1mSubtest ts-continuation-dpms-suspend: SKIP (0.000s)[0m
12643 19:28:16.155703 <14>[ 27.610331] [IGT] kms_vblank: executing
12644 19:28:16.162359 IGT-Version: 1.2<14>[ 27.615362] [IGT] kms_vblank: exiting, ret=77
12645 19:28:16.166225 8-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12646 19:28:16.178916 Using IGT_SRANDOM=1713468245 for randomisati<8>[ 27.628191] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-suspend RESULT=skip>
12647 19:28:16.179074 on
12648 19:28:16.179324 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-suspend RESULT=skip
12650 19:28:16.182490 Opened device: /dev/dri/card0
12651 19:28:16.185912 No KMS driver or no outputs, pipes: 16, outputs: 0
12652 19:28:16.189070 [1mSubtest ts-continuation-suspend: SKIP (0.000s)[0m
12653 19:28:16.199788 <14>[ 27.654086] [IGT] kms_vblank: executing
12654 19:28:16.206167 IGT-Version: 1.2<14>[ 27.658857] [IGT] kms_vblank: exiting, ret=77
12655 19:28:16.209734 8-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12656 19:28:16.219995 Using IGT_SRANDOM=1713468245<8>[ 27.670950] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-modeset RESULT=skip>
12657 19:28:16.220334 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-modeset RESULT=skip
12659 19:28:16.222969 for randomisation
12660 19:28:16.226081 Opened device: /dev/dri/card0
12661 19:28:16.229606 No KMS driver or no outputs, pipes: 16, outputs: 0
12662 19:28:16.232918 [1mSubtest ts-continuation-modeset: SKIP (0.000s)[0m
12663 19:28:16.239669 <14>[ 27.692726] [IGT] kms_vblank: executing
12664 19:28:16.242854 IGT-Version: 1.2<14>[ 27.697962] [IGT] kms_vblank: exiting, ret=77
12665 19:28:16.249098 8-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12666 19:28:16.259347 Using IGT_SRANDOM=1713468245<8>[ 27.710217] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-modeset-hang RESULT=skip>
12667 19:28:16.259678 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-modeset-hang RESULT=skip
12669 19:28:16.262475 for randomisation
12670 19:28:16.262569 Opened device: /dev/dri/card0
12671 19:28:16.268980 No KMS driver or no outputs, pipes: 16, outputs: 0
12672 19:28:16.272214 [1mSubtest ts-continuation-modeset-hang: SKIP (0.000s)[0m
12673 19:28:16.279365 <14>[ 27.733921] [IGT] kms_vblank: executing
12674 19:28:16.286298 IGT-Version: 1.2<14>[ 27.738595] [IGT] kms_vblank: exiting, ret=77
12675 19:28:16.289502 8-ga44ebfe (aarch64) (Linux: 6.1.86-cip19 aarch64)
12676 19:28:16.299326 Using IGT_SRANDOM=1713468245<8>[ 27.750631] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-modeset-rpm RESULT=skip>
12677 19:28:16.299638 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-modeset-rpm RESULT=skip
12679 19:28:16.302908 for randomisation
12680 19:28:16.306166 Opened devic<8>[ 27.761422] <LAVA_SIGNAL_TESTSET STOP>
12681 19:28:16.306466 Received signal: <TESTSET> STOP
12682 19:28:16.306542 Closing test_set kms_vblank
12683 19:28:16.315884 e: /dev/dri/card<8>[ 27.767351] <LAVA_SIGNAL_ENDRUN 0_igt-kms-mediatek 13420368_1.5.2.3.1>
12684 19:28:16.316152 0
12685 19:28:16.316404 Received signal: <ENDRUN> 0_igt-kms-mediatek 13420368_1.5.2.3.1
12686 19:28:16.316488 Ending use of test pattern.
12687 19:28:16.316551 Ending test lava.0_igt-kms-mediatek (13420368_1.5.2.3.1), duration 6.33
12689 19:28:16.319432 No KMS driver or no outputs, pipes: 16, outputs: 0
12690 19:28:16.325946 [1mSubtest ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12691 19:28:16.326193 + set +x
12692 19:28:16.329167 <LAVA_TEST_RUNNER EXIT>
12693 19:28:16.329503 ok: lava_test_shell seems to have completed
12694 19:28:16.331250 accuracy-idle:
result: skip
set: kms_vblank
addfb25-4-tiled:
result: skip
set: kms_addfb_basic
addfb25-bad-modifier:
result: fail
set: kms_addfb_basic
addfb25-framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
addfb25-modifier-no-flag:
result: pass
set: kms_addfb_basic
addfb25-x-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-x-tiled-mismatch-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-small-legacy:
result: skip
set: kms_addfb_basic
addfb25-yf-tiled-legacy:
result: skip
set: kms_addfb_basic
atomic-invalid-params:
result: skip
set: kms_atomic
atomic-plane-damage:
result: skip
set: kms_atomic
bad-pitch-0:
result: pass
set: kms_addfb_basic
bad-pitch-1024:
result: pass
set: kms_addfb_basic
bad-pitch-128:
result: pass
set: kms_addfb_basic
bad-pitch-256:
result: pass
set: kms_addfb_basic
bad-pitch-32:
result: pass
set: kms_addfb_basic
bad-pitch-63:
result: pass
set: kms_addfb_basic
bad-pitch-65536:
result: pass
set: kms_addfb_basic
bad-pitch-999:
result: pass
set: kms_addfb_basic
basic:
result: skip
set: kms_setmode
basic-auth:
result: pass
set: core_auth
basic-clone-single-crtc:
result: skip
set: kms_setmode
basic-x-tiled-legacy:
result: skip
set: kms_addfb_basic
basic-y-tiled-legacy:
result: skip
set: kms_addfb_basic
blob-multiple:
result: pass
set: kms_prop_blob
blob-prop-core:
result: pass
set: kms_prop_blob
blob-prop-lifetime:
result: pass
set: kms_prop_blob
blob-prop-validate:
result: pass
set: kms_prop_blob
bo-too-small:
result: skip
set: kms_addfb_basic
bo-too-small-due-to-tiling:
result: skip
set: kms_addfb_basic
clobberred-modifier:
result: skip
set: kms_addfb_basic
clone-exclusive-crtc:
result: skip
set: kms_setmode
core_getclient: pass
core_getstats: pass
core_getversion: pass
core_setmaster_vs_auth: pass
crtc-id:
result: skip
set: kms_vblank
crtc-invalid-params:
result: skip
set: kms_atomic
crtc-invalid-params-fence:
result: skip
set: kms_atomic
empty-block:
result: skip
set: drm_read
empty-nonblock:
result: skip
set: drm_read
fault-buffer:
result: skip
set: drm_read
framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
getclient-master-drop:
result: pass
set: core_auth
getclient-simple:
result: pass
set: core_auth
invalid:
result: skip
set: kms_vblank
invalid-buffer:
result: skip
set: drm_read
invalid-clone-exclusive-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc-stealing:
result: skip
set: kms_setmode
invalid-get-prop:
result: pass
set: kms_prop_blob
invalid-get-prop-any:
result: pass
set: kms_prop_blob
invalid-set-prop:
result: pass
set: kms_prop_blob
invalid-set-prop-any:
result: pass
set: kms_prop_blob
invalid-smem-bo-on-discrete:
result: skip
set: kms_addfb_basic
legacy-format:
result: pass
set: kms_addfb_basic
many-magics:
result: pass
set: core_auth
master-rmfb:
result: pass
set: kms_addfb_basic
no-handle:
result: pass
set: kms_addfb_basic
plane-cursor-legacy:
result: skip
set: kms_atomic
plane-immutable-zpos:
result: skip
set: kms_atomic
plane-invalid-params:
result: skip
set: kms_atomic
plane-invalid-params-fence:
result: skip
set: kms_atomic
plane-overlay-legacy:
result: skip
set: kms_atomic
plane-primary-legacy:
result: skip
set: kms_atomic
plane-primary-overlay-mutable-zpos:
result: skip
set: kms_atomic
query-busy:
result: skip
set: kms_vblank
query-busy-hang:
result: skip
set: kms_vblank
query-forked:
result: skip
set: kms_vblank
query-forked-busy:
result: skip
set: kms_vblank
query-forked-busy-hang:
result: skip
set: kms_vblank
query-forked-hang:
result: skip
set: kms_vblank
query-idle:
result: skip
set: kms_vblank
query-idle-hang:
result: skip
set: kms_vblank
short-buffer-block:
result: skip
set: drm_read
short-buffer-nonblock:
result: skip
set: drm_read
short-buffer-wakeup:
result: skip
set: drm_read
size-max:
result: skip
set: kms_addfb_basic
small-bo:
result: skip
set: kms_addfb_basic
test-only:
result: skip
set: kms_atomic
tile-pitch-mismatch:
result: skip
set: kms_addfb_basic
too-high:
result: skip
set: kms_addfb_basic
too-wide:
result: skip
set: kms_addfb_basic
ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
ts-continuation-idle:
result: skip
set: kms_vblank
ts-continuation-idle-hang:
result: skip
set: kms_vblank
ts-continuation-modeset:
result: skip
set: kms_vblank
ts-continuation-modeset-hang:
result: skip
set: kms_vblank
ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
ts-continuation-suspend:
result: skip
set: kms_vblank
unused-handle:
result: pass
set: kms_addfb_basic
unused-modifier:
result: pass
set: kms_addfb_basic
unused-offsets:
result: pass
set: kms_addfb_basic
unused-pitches:
result: pass
set: kms_addfb_basic
wait-busy:
result: skip
set: kms_vblank
wait-busy-hang:
result: skip
set: kms_vblank
wait-forked:
result: skip
set: kms_vblank
wait-forked-busy:
result: skip
set: kms_vblank
wait-forked-busy-hang:
result: skip
set: kms_vblank
wait-forked-hang:
result: skip
set: kms_vblank
wait-idle:
result: skip
set: kms_vblank
wait-idle-hang:
result: skip
set: kms_vblank
12695 19:28:16.331418 end: 3.1 lava-test-shell (duration 00:00:07) [common]
12696 19:28:16.331507 end: 3 lava-test-retry (duration 00:00:07) [common]
12697 19:28:16.331598 start: 4 finalize (timeout 00:07:41) [common]
12698 19:28:16.331684 start: 4.1 power-off (timeout 00:00:30) [common]
12699 19:28:16.331835 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
12700 19:28:16.411830 >> Command sent successfully.
12701 19:28:16.415205 Returned 0 in 0 seconds
12702 19:28:16.515665 end: 4.1 power-off (duration 00:00:00) [common]
12704 19:28:16.516009 start: 4.2 read-feedback (timeout 00:07:40) [common]
12705 19:28:16.516293 Listened to connection for namespace 'common' for up to 1s
12706 19:28:17.517224 Finalising connection for namespace 'common'
12707 19:28:17.517416 Disconnecting from shell: Finalise
12708 19:28:17.517497 / #
12709 19:28:17.617841 end: 4.2 read-feedback (duration 00:00:01) [common]
12710 19:28:17.618026 end: 4 finalize (duration 00:00:01) [common]
12711 19:28:17.618146 Cleaning after the job
12712 19:28:17.618241 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13420368/tftp-deploy-03xmkh_w/ramdisk
12713 19:28:17.624926 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13420368/tftp-deploy-03xmkh_w/kernel
12714 19:28:17.632252 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13420368/tftp-deploy-03xmkh_w/dtb
12715 19:28:17.632469 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13420368/tftp-deploy-03xmkh_w/modules
12716 19:28:17.638194 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/13420368
12717 19:28:17.748728 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/13420368
12718 19:28:17.748912 Job finished correctly