Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 25
- Errors: 0
- Kernel Errors: 35
- Boot result: PASS
1 19:21:19.847924 lava-dispatcher, installed at version: 2024.01
2 19:21:19.848147 start: 0 validate
3 19:21:19.848280 Start time: 2024-04-18 19:21:19.848272+00:00 (UTC)
4 19:21:19.848415 Using caching service: 'http://localhost/cache/?uri=%s'
5 19:21:19.848549 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 19:21:20.116965 Using caching service: 'http://localhost/cache/?uri=%s'
7 19:21:20.117669 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 19:22:06.142611 Using caching service: 'http://localhost/cache/?uri=%s'
9 19:22:06.143248 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 19:22:06.405155 Using caching service: 'http://localhost/cache/?uri=%s'
11 19:22:06.405921 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 19:22:06.660414 Using caching service: 'http://localhost/cache/?uri=%s'
13 19:22:06.660583 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 19:22:09.669914 validate duration: 49.82
16 19:22:09.670172 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 19:22:09.670268 start: 1.1 download-retry (timeout 00:10:00) [common]
18 19:22:09.670354 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 19:22:09.670478 Not decompressing ramdisk as can be used compressed.
20 19:22:09.670564 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 19:22:09.670629 saving as /var/lib/lava/dispatcher/tmp/13420329/tftp-deploy-yatqcpq2/ramdisk/initrd.cpio.gz
22 19:22:09.670696 total size: 5628169 (5 MB)
23 19:22:09.671767 progress 0 % (0 MB)
24 19:22:09.673383 progress 5 % (0 MB)
25 19:22:09.674938 progress 10 % (0 MB)
26 19:22:09.676329 progress 15 % (0 MB)
27 19:22:09.677916 progress 20 % (1 MB)
28 19:22:09.679318 progress 25 % (1 MB)
29 19:22:09.680942 progress 30 % (1 MB)
30 19:22:09.682476 progress 35 % (1 MB)
31 19:22:09.683834 progress 40 % (2 MB)
32 19:22:09.685398 progress 45 % (2 MB)
33 19:22:09.686860 progress 50 % (2 MB)
34 19:22:09.688383 progress 55 % (2 MB)
35 19:22:09.689960 progress 60 % (3 MB)
36 19:22:09.691395 progress 65 % (3 MB)
37 19:22:09.692931 progress 70 % (3 MB)
38 19:22:09.694387 progress 75 % (4 MB)
39 19:22:09.695913 progress 80 % (4 MB)
40 19:22:09.697307 progress 85 % (4 MB)
41 19:22:09.699051 progress 90 % (4 MB)
42 19:22:09.700584 progress 95 % (5 MB)
43 19:22:09.702017 progress 100 % (5 MB)
44 19:22:09.702228 5 MB downloaded in 0.03 s (170.23 MB/s)
45 19:22:09.702387 end: 1.1.1 http-download (duration 00:00:00) [common]
47 19:22:09.702633 end: 1.1 download-retry (duration 00:00:00) [common]
48 19:22:09.702720 start: 1.2 download-retry (timeout 00:10:00) [common]
49 19:22:09.702806 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 19:22:09.702941 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 19:22:09.703012 saving as /var/lib/lava/dispatcher/tmp/13420329/tftp-deploy-yatqcpq2/kernel/Image
52 19:22:09.703078 total size: 54286848 (51 MB)
53 19:22:09.703141 No compression specified
54 19:22:09.704273 progress 0 % (0 MB)
55 19:22:09.718158 progress 5 % (2 MB)
56 19:22:09.731881 progress 10 % (5 MB)
57 19:22:09.745660 progress 15 % (7 MB)
58 19:22:09.759395 progress 20 % (10 MB)
59 19:22:09.773654 progress 25 % (12 MB)
60 19:22:09.787479 progress 30 % (15 MB)
61 19:22:09.801695 progress 35 % (18 MB)
62 19:22:09.815539 progress 40 % (20 MB)
63 19:22:09.829499 progress 45 % (23 MB)
64 19:22:09.843442 progress 50 % (25 MB)
65 19:22:09.857372 progress 55 % (28 MB)
66 19:22:09.871327 progress 60 % (31 MB)
67 19:22:09.884920 progress 65 % (33 MB)
68 19:22:09.899167 progress 70 % (36 MB)
69 19:22:09.912902 progress 75 % (38 MB)
70 19:22:09.926986 progress 80 % (41 MB)
71 19:22:09.941301 progress 85 % (44 MB)
72 19:22:09.955308 progress 90 % (46 MB)
73 19:22:09.969174 progress 95 % (49 MB)
74 19:22:09.982651 progress 100 % (51 MB)
75 19:22:09.982941 51 MB downloaded in 0.28 s (184.99 MB/s)
76 19:22:09.983097 end: 1.2.1 http-download (duration 00:00:00) [common]
78 19:22:09.983334 end: 1.2 download-retry (duration 00:00:00) [common]
79 19:22:09.983423 start: 1.3 download-retry (timeout 00:10:00) [common]
80 19:22:09.983511 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 19:22:09.983652 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 19:22:09.983721 saving as /var/lib/lava/dispatcher/tmp/13420329/tftp-deploy-yatqcpq2/dtb/mt8192-asurada-spherion-r0.dtb
83 19:22:09.983783 total size: 47230 (0 MB)
84 19:22:09.983844 No compression specified
85 19:22:09.984977 progress 69 % (0 MB)
86 19:22:09.985250 progress 100 % (0 MB)
87 19:22:09.985445 0 MB downloaded in 0.00 s (27.14 MB/s)
88 19:22:09.985571 end: 1.3.1 http-download (duration 00:00:00) [common]
90 19:22:09.985795 end: 1.3 download-retry (duration 00:00:00) [common]
91 19:22:09.985881 start: 1.4 download-retry (timeout 00:10:00) [common]
92 19:22:09.985963 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 19:22:09.986078 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 19:22:09.986146 saving as /var/lib/lava/dispatcher/tmp/13420329/tftp-deploy-yatqcpq2/nfsrootfs/full.rootfs.tar
95 19:22:09.986207 total size: 120894716 (115 MB)
96 19:22:09.986267 Using unxz to decompress xz
97 19:22:09.990357 progress 0 % (0 MB)
98 19:22:10.347110 progress 5 % (5 MB)
99 19:22:10.722719 progress 10 % (11 MB)
100 19:22:11.080650 progress 15 % (17 MB)
101 19:22:11.414397 progress 20 % (23 MB)
102 19:22:11.719852 progress 25 % (28 MB)
103 19:22:12.100757 progress 30 % (34 MB)
104 19:22:12.459249 progress 35 % (40 MB)
105 19:22:12.635092 progress 40 % (46 MB)
106 19:22:12.824301 progress 45 % (51 MB)
107 19:22:13.157132 progress 50 % (57 MB)
108 19:22:13.553854 progress 55 % (63 MB)
109 19:22:13.917363 progress 60 % (69 MB)
110 19:22:14.277855 progress 65 % (74 MB)
111 19:22:14.632614 progress 70 % (80 MB)
112 19:22:15.002773 progress 75 % (86 MB)
113 19:22:15.350307 progress 80 % (92 MB)
114 19:22:15.692855 progress 85 % (98 MB)
115 19:22:16.055710 progress 90 % (103 MB)
116 19:22:16.393959 progress 95 % (109 MB)
117 19:22:16.755722 progress 100 % (115 MB)
118 19:22:16.761042 115 MB downloaded in 6.77 s (17.02 MB/s)
119 19:22:16.761416 end: 1.4.1 http-download (duration 00:00:07) [common]
121 19:22:16.761825 end: 1.4 download-retry (duration 00:00:07) [common]
122 19:22:16.761954 start: 1.5 download-retry (timeout 00:09:53) [common]
123 19:22:16.762084 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 19:22:16.762285 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 19:22:16.762427 saving as /var/lib/lava/dispatcher/tmp/13420329/tftp-deploy-yatqcpq2/modules/modules.tar
126 19:22:16.762523 total size: 8631416 (8 MB)
127 19:22:16.762623 Using unxz to decompress xz
128 19:22:16.767423 progress 0 % (0 MB)
129 19:22:16.786770 progress 5 % (0 MB)
130 19:22:16.812161 progress 10 % (0 MB)
131 19:22:16.836651 progress 15 % (1 MB)
132 19:22:16.860111 progress 20 % (1 MB)
133 19:22:16.884854 progress 25 % (2 MB)
134 19:22:16.912206 progress 30 % (2 MB)
135 19:22:16.936574 progress 35 % (2 MB)
136 19:22:16.962454 progress 40 % (3 MB)
137 19:22:16.986397 progress 45 % (3 MB)
138 19:22:17.011546 progress 50 % (4 MB)
139 19:22:17.036426 progress 55 % (4 MB)
140 19:22:17.064717 progress 60 % (4 MB)
141 19:22:17.089842 progress 65 % (5 MB)
142 19:22:17.115091 progress 70 % (5 MB)
143 19:22:17.139538 progress 75 % (6 MB)
144 19:22:17.165589 progress 80 % (6 MB)
145 19:22:17.191781 progress 85 % (7 MB)
146 19:22:17.220297 progress 90 % (7 MB)
147 19:22:17.249283 progress 95 % (7 MB)
148 19:22:17.275888 progress 100 % (8 MB)
149 19:22:17.281292 8 MB downloaded in 0.52 s (15.87 MB/s)
150 19:22:17.281598 end: 1.5.1 http-download (duration 00:00:01) [common]
152 19:22:17.281866 end: 1.5 download-retry (duration 00:00:01) [common]
153 19:22:17.281960 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 19:22:17.282053 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 19:22:21.236143 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/13420329/extract-nfsrootfs-l3_d7ahj
156 19:22:21.236359 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 19:22:21.236461 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 19:22:21.236625 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/13420329/lava-overlay-a9r9nwg_
159 19:22:21.236756 makedir: /var/lib/lava/dispatcher/tmp/13420329/lava-overlay-a9r9nwg_/lava-13420329/bin
160 19:22:21.236857 makedir: /var/lib/lava/dispatcher/tmp/13420329/lava-overlay-a9r9nwg_/lava-13420329/tests
161 19:22:21.236992 makedir: /var/lib/lava/dispatcher/tmp/13420329/lava-overlay-a9r9nwg_/lava-13420329/results
162 19:22:21.237199 Creating /var/lib/lava/dispatcher/tmp/13420329/lava-overlay-a9r9nwg_/lava-13420329/bin/lava-add-keys
163 19:22:21.237409 Creating /var/lib/lava/dispatcher/tmp/13420329/lava-overlay-a9r9nwg_/lava-13420329/bin/lava-add-sources
164 19:22:21.237557 Creating /var/lib/lava/dispatcher/tmp/13420329/lava-overlay-a9r9nwg_/lava-13420329/bin/lava-background-process-start
165 19:22:21.237705 Creating /var/lib/lava/dispatcher/tmp/13420329/lava-overlay-a9r9nwg_/lava-13420329/bin/lava-background-process-stop
166 19:22:21.237914 Creating /var/lib/lava/dispatcher/tmp/13420329/lava-overlay-a9r9nwg_/lava-13420329/bin/lava-common-functions
167 19:22:21.238102 Creating /var/lib/lava/dispatcher/tmp/13420329/lava-overlay-a9r9nwg_/lava-13420329/bin/lava-echo-ipv4
168 19:22:21.238276 Creating /var/lib/lava/dispatcher/tmp/13420329/lava-overlay-a9r9nwg_/lava-13420329/bin/lava-install-packages
169 19:22:21.238417 Creating /var/lib/lava/dispatcher/tmp/13420329/lava-overlay-a9r9nwg_/lava-13420329/bin/lava-installed-packages
170 19:22:21.238563 Creating /var/lib/lava/dispatcher/tmp/13420329/lava-overlay-a9r9nwg_/lava-13420329/bin/lava-os-build
171 19:22:21.238734 Creating /var/lib/lava/dispatcher/tmp/13420329/lava-overlay-a9r9nwg_/lava-13420329/bin/lava-probe-channel
172 19:22:21.238903 Creating /var/lib/lava/dispatcher/tmp/13420329/lava-overlay-a9r9nwg_/lava-13420329/bin/lava-probe-ip
173 19:22:21.239068 Creating /var/lib/lava/dispatcher/tmp/13420329/lava-overlay-a9r9nwg_/lava-13420329/bin/lava-target-ip
174 19:22:21.239213 Creating /var/lib/lava/dispatcher/tmp/13420329/lava-overlay-a9r9nwg_/lava-13420329/bin/lava-target-mac
175 19:22:21.239354 Creating /var/lib/lava/dispatcher/tmp/13420329/lava-overlay-a9r9nwg_/lava-13420329/bin/lava-target-storage
176 19:22:21.239499 Creating /var/lib/lava/dispatcher/tmp/13420329/lava-overlay-a9r9nwg_/lava-13420329/bin/lava-test-case
177 19:22:21.239641 Creating /var/lib/lava/dispatcher/tmp/13420329/lava-overlay-a9r9nwg_/lava-13420329/bin/lava-test-event
178 19:22:21.239786 Creating /var/lib/lava/dispatcher/tmp/13420329/lava-overlay-a9r9nwg_/lava-13420329/bin/lava-test-feedback
179 19:22:21.239954 Creating /var/lib/lava/dispatcher/tmp/13420329/lava-overlay-a9r9nwg_/lava-13420329/bin/lava-test-raise
180 19:22:21.240123 Creating /var/lib/lava/dispatcher/tmp/13420329/lava-overlay-a9r9nwg_/lava-13420329/bin/lava-test-reference
181 19:22:21.240293 Creating /var/lib/lava/dispatcher/tmp/13420329/lava-overlay-a9r9nwg_/lava-13420329/bin/lava-test-runner
182 19:22:21.240459 Creating /var/lib/lava/dispatcher/tmp/13420329/lava-overlay-a9r9nwg_/lava-13420329/bin/lava-test-set
183 19:22:21.240600 Creating /var/lib/lava/dispatcher/tmp/13420329/lava-overlay-a9r9nwg_/lava-13420329/bin/lava-test-shell
184 19:22:21.240749 Updating /var/lib/lava/dispatcher/tmp/13420329/lava-overlay-a9r9nwg_/lava-13420329/bin/lava-add-keys (debian)
185 19:22:21.240924 Updating /var/lib/lava/dispatcher/tmp/13420329/lava-overlay-a9r9nwg_/lava-13420329/bin/lava-add-sources (debian)
186 19:22:21.241092 Updating /var/lib/lava/dispatcher/tmp/13420329/lava-overlay-a9r9nwg_/lava-13420329/bin/lava-install-packages (debian)
187 19:22:21.241279 Updating /var/lib/lava/dispatcher/tmp/13420329/lava-overlay-a9r9nwg_/lava-13420329/bin/lava-installed-packages (debian)
188 19:22:21.241641 Updating /var/lib/lava/dispatcher/tmp/13420329/lava-overlay-a9r9nwg_/lava-13420329/bin/lava-os-build (debian)
189 19:22:21.241805 Creating /var/lib/lava/dispatcher/tmp/13420329/lava-overlay-a9r9nwg_/lava-13420329/environment
190 19:22:21.241944 LAVA metadata
191 19:22:21.242024 - LAVA_JOB_ID=13420329
192 19:22:21.242104 - LAVA_DISPATCHER_IP=192.168.201.1
193 19:22:21.242242 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 19:22:21.242316 skipped lava-vland-overlay
195 19:22:21.242415 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 19:22:21.242514 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 19:22:21.242608 skipped lava-multinode-overlay
198 19:22:21.242725 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 19:22:21.242844 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 19:22:21.242958 Loading test definitions
201 19:22:21.243093 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 19:22:21.243201 Using /lava-13420329 at stage 0
203 19:22:21.254084 uuid=13420329_1.6.2.3.1 testdef=None
204 19:22:21.254188 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 19:22:21.254294 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 19:22:21.254837 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 19:22:21.255135 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 19:22:21.255808 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 19:22:21.256064 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 19:22:21.256843 runner path: /var/lib/lava/dispatcher/tmp/13420329/lava-overlay-a9r9nwg_/lava-13420329/0/tests/0_timesync-off test_uuid 13420329_1.6.2.3.1
213 19:22:21.259223 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 19:22:21.259681 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 19:22:21.259822 Using /lava-13420329 at stage 0
217 19:22:21.260009 Fetching tests from https://github.com/kernelci/test-definitions.git
218 19:22:21.260141 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/13420329/lava-overlay-a9r9nwg_/lava-13420329/0/tests/1_kselftest-alsa'
219 19:22:24.104888 Running '/usr/bin/git checkout kernelci.org
220 19:22:24.188167 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/13420329/lava-overlay-a9r9nwg_/lava-13420329/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
221 19:22:24.189347 uuid=13420329_1.6.2.3.5 testdef=None
222 19:22:24.189520 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 19:22:24.189769 start: 1.6.2.3.6 test-overlay (timeout 00:09:45) [common]
225 19:22:24.190899 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 19:22:24.191285 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:45) [common]
228 19:22:24.192886 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 19:22:24.193273 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:45) [common]
231 19:22:24.194841 runner path: /var/lib/lava/dispatcher/tmp/13420329/lava-overlay-a9r9nwg_/lava-13420329/0/tests/1_kselftest-alsa test_uuid 13420329_1.6.2.3.5
232 19:22:24.194975 BOARD='mt8192-asurada-spherion-r0'
233 19:22:24.195075 BRANCH='cip'
234 19:22:24.195165 SKIPFILE='/dev/null'
235 19:22:24.195253 SKIP_INSTALL='True'
236 19:22:24.195341 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 19:22:24.195432 TST_CASENAME=''
238 19:22:24.195518 TST_CMDFILES='alsa'
239 19:22:24.195706 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 19:22:24.196060 Creating lava-test-runner.conf files
242 19:22:24.196154 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/13420329/lava-overlay-a9r9nwg_/lava-13420329/0 for stage 0
243 19:22:24.196277 - 0_timesync-off
244 19:22:24.196377 - 1_kselftest-alsa
245 19:22:24.196503 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 19:22:24.196592 start: 1.6.2.4 compress-overlay (timeout 00:09:45) [common]
247 19:22:31.827466 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 19:22:31.827626 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:38) [common]
249 19:22:31.827722 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 19:22:31.827822 end: 1.6.2 lava-overlay (duration 00:00:11) [common]
251 19:22:31.827911 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:38) [common]
252 19:22:31.997207 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 19:22:31.997711 start: 1.6.4 extract-modules (timeout 00:09:38) [common]
254 19:22:31.997875 extracting modules file /var/lib/lava/dispatcher/tmp/13420329/tftp-deploy-yatqcpq2/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13420329/extract-nfsrootfs-l3_d7ahj
255 19:22:32.242621 extracting modules file /var/lib/lava/dispatcher/tmp/13420329/tftp-deploy-yatqcpq2/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13420329/extract-overlay-ramdisk-abcp399u/ramdisk
256 19:22:32.464597 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 19:22:32.464774 start: 1.6.5 apply-overlay-tftp (timeout 00:09:37) [common]
258 19:22:32.464878 [common] Applying overlay to NFS
259 19:22:32.464949 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13420329/compress-overlay-i42q7zq5/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/13420329/extract-nfsrootfs-l3_d7ahj
260 19:22:33.385083 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 19:22:33.385251 start: 1.6.6 configure-preseed-file (timeout 00:09:36) [common]
262 19:22:33.385375 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 19:22:33.385477 start: 1.6.7 compress-ramdisk (timeout 00:09:36) [common]
264 19:22:33.385563 Building ramdisk /var/lib/lava/dispatcher/tmp/13420329/extract-overlay-ramdisk-abcp399u/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/13420329/extract-overlay-ramdisk-abcp399u/ramdisk
265 19:22:33.725706 >> 130624 blocks
266 19:22:35.748389 rename /var/lib/lava/dispatcher/tmp/13420329/extract-overlay-ramdisk-abcp399u/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/13420329/tftp-deploy-yatqcpq2/ramdisk/ramdisk.cpio.gz
267 19:22:35.749017 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 19:22:35.749179 start: 1.6.8 prepare-kernel (timeout 00:09:34) [common]
269 19:22:35.749348 start: 1.6.8.1 prepare-fit (timeout 00:09:34) [common]
270 19:22:35.749514 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/13420329/tftp-deploy-yatqcpq2/kernel/Image'
271 19:22:50.233903 Returned 0 in 14 seconds
272 19:22:50.334541 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/13420329/tftp-deploy-yatqcpq2/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/13420329/tftp-deploy-yatqcpq2/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/13420329/tftp-deploy-yatqcpq2/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/13420329/tftp-deploy-yatqcpq2/kernel/image.itb
273 19:22:50.684002 output: FIT description: Kernel Image image with one or more FDT blobs
274 19:22:50.684401 output: Created: Thu Apr 18 20:22:50 2024
275 19:22:50.684487 output: Image 0 (kernel-1)
276 19:22:50.684573 output: Description:
277 19:22:50.684638 output: Created: Thu Apr 18 20:22:50 2024
278 19:22:50.684699 output: Type: Kernel Image
279 19:22:50.684760 output: Compression: lzma compressed
280 19:22:50.684820 output: Data Size: 12910355 Bytes = 12607.77 KiB = 12.31 MiB
281 19:22:50.684880 output: Architecture: AArch64
282 19:22:50.684937 output: OS: Linux
283 19:22:50.684991 output: Load Address: 0x00000000
284 19:22:50.685050 output: Entry Point: 0x00000000
285 19:22:50.685107 output: Hash algo: crc32
286 19:22:50.685163 output: Hash value: bbac8b0b
287 19:22:50.685220 output: Image 1 (fdt-1)
288 19:22:50.685276 output: Description: mt8192-asurada-spherion-r0
289 19:22:50.685370 output: Created: Thu Apr 18 20:22:50 2024
290 19:22:50.685447 output: Type: Flat Device Tree
291 19:22:50.685501 output: Compression: uncompressed
292 19:22:50.685554 output: Data Size: 47230 Bytes = 46.12 KiB = 0.05 MiB
293 19:22:50.685610 output: Architecture: AArch64
294 19:22:50.685663 output: Hash algo: crc32
295 19:22:50.685715 output: Hash value: 4bf0d1ac
296 19:22:50.685768 output: Image 2 (ramdisk-1)
297 19:22:50.685821 output: Description: unavailable
298 19:22:50.685874 output: Created: Thu Apr 18 20:22:50 2024
299 19:22:50.685928 output: Type: RAMDisk Image
300 19:22:50.685980 output: Compression: Unknown Compression
301 19:22:50.686034 output: Data Size: 18778291 Bytes = 18338.17 KiB = 17.91 MiB
302 19:22:50.686087 output: Architecture: AArch64
303 19:22:50.686140 output: OS: Linux
304 19:22:50.686192 output: Load Address: unavailable
305 19:22:50.686244 output: Entry Point: unavailable
306 19:22:50.686297 output: Hash algo: crc32
307 19:22:50.686350 output: Hash value: 2bc64f10
308 19:22:50.686402 output: Default Configuration: 'conf-1'
309 19:22:50.686455 output: Configuration 0 (conf-1)
310 19:22:50.686507 output: Description: mt8192-asurada-spherion-r0
311 19:22:50.686560 output: Kernel: kernel-1
312 19:22:50.686612 output: Init Ramdisk: ramdisk-1
313 19:22:50.686665 output: FDT: fdt-1
314 19:22:50.686717 output: Loadables: kernel-1
315 19:22:50.686770 output:
316 19:22:50.686974 end: 1.6.8.1 prepare-fit (duration 00:00:15) [common]
317 19:22:50.687097 end: 1.6.8 prepare-kernel (duration 00:00:15) [common]
318 19:22:50.687209 end: 1.6 prepare-tftp-overlay (duration 00:00:33) [common]
319 19:22:50.687322 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:19) [common]
320 19:22:50.687406 No LXC device requested
321 19:22:50.687487 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 19:22:50.687577 start: 1.8 deploy-device-env (timeout 00:09:19) [common]
323 19:22:50.687655 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 19:22:50.687724 Checking files for TFTP limit of 4294967296 bytes.
325 19:22:50.688226 end: 1 tftp-deploy (duration 00:00:41) [common]
326 19:22:50.688334 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 19:22:50.688429 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 19:22:50.688558 substitutions:
329 19:22:50.688628 - {DTB}: 13420329/tftp-deploy-yatqcpq2/dtb/mt8192-asurada-spherion-r0.dtb
330 19:22:50.688695 - {INITRD}: 13420329/tftp-deploy-yatqcpq2/ramdisk/ramdisk.cpio.gz
331 19:22:50.688756 - {KERNEL}: 13420329/tftp-deploy-yatqcpq2/kernel/Image
332 19:22:50.688815 - {LAVA_MAC}: None
333 19:22:50.688873 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/13420329/extract-nfsrootfs-l3_d7ahj
334 19:22:50.688931 - {NFS_SERVER_IP}: 192.168.201.1
335 19:22:50.688990 - {PRESEED_CONFIG}: None
336 19:22:50.689046 - {PRESEED_LOCAL}: None
337 19:22:50.689104 - {RAMDISK}: 13420329/tftp-deploy-yatqcpq2/ramdisk/ramdisk.cpio.gz
338 19:22:50.689160 - {ROOT_PART}: None
339 19:22:50.689216 - {ROOT}: None
340 19:22:50.689271 - {SERVER_IP}: 192.168.201.1
341 19:22:50.689326 - {TEE}: None
342 19:22:50.689425 Parsed boot commands:
343 19:22:50.689479 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 19:22:50.689662 Parsed boot commands: tftpboot 192.168.201.1 13420329/tftp-deploy-yatqcpq2/kernel/image.itb 13420329/tftp-deploy-yatqcpq2/kernel/cmdline
345 19:22:50.689754 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 19:22:50.689840 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 19:22:50.689934 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 19:22:50.690017 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 19:22:50.690093 Not connected, no need to disconnect.
350 19:22:50.690167 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 19:22:50.690248 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 19:22:50.690319 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
353 19:22:50.694129 Setting prompt string to ['lava-test: # ']
354 19:22:50.694517 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 19:22:50.694647 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 19:22:50.694806 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 19:22:50.694967 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 19:22:50.695218 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=reboot'
359 19:22:55.856037 >> Command sent successfully.
360 19:22:55.858545 Returned 0 in 5 seconds
361 19:22:55.959298 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 19:22:55.960686 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 19:22:55.961196 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 19:22:55.961748 Setting prompt string to 'Starting depthcharge on Spherion...'
366 19:22:55.962118 Changing prompt to 'Starting depthcharge on Spherion...'
367 19:22:55.962492 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 19:22:55.963489 [Enter `^Ec?' for help]
369 19:22:56.134174
370 19:22:56.134419
371 19:22:56.134539 F0: 102B 0000
372 19:22:56.134659
373 19:22:56.134761 F3: 1001 0000 [0200]
374 19:22:56.134880
375 19:22:56.137465 F3: 1001 0000
376 19:22:56.137585
377 19:22:56.137681 F7: 102D 0000
378 19:22:56.137774
379 19:22:56.137848 F1: 0000 0000
380 19:22:56.137904
381 19:22:56.141365 V0: 0000 0000 [0001]
382 19:22:56.141489
383 19:22:56.141571 00: 0007 8000
384 19:22:56.141638
385 19:22:56.145237 01: 0000 0000
386 19:22:56.145323
387 19:22:56.145428 BP: 0C00 0209 [0000]
388 19:22:56.145490
389 19:22:56.148523 G0: 1182 0000
390 19:22:56.148606
391 19:22:56.148672 EC: 0000 0021 [4000]
392 19:22:56.148734
393 19:22:56.151732 S7: 0000 0000 [0000]
394 19:22:56.151820
395 19:22:56.151887 CC: 0000 0000 [0001]
396 19:22:56.151949
397 19:22:56.155444 T0: 0000 0040 [010F]
398 19:22:56.155545
399 19:22:56.155611 Jump to BL
400 19:22:56.155673
401 19:22:56.180598
402 19:22:56.180761
403 19:22:56.180832
404 19:22:56.187712 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 19:22:56.191031 ARM64: Exception handlers installed.
406 19:22:56.194598 ARM64: Testing exception
407 19:22:56.198632 ARM64: Done test exception
408 19:22:56.205873 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 19:22:56.213394 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 19:22:56.221211 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 19:22:56.231184 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 19:22:56.238151 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 19:22:56.248463 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 19:22:56.258395 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 19:22:56.265563 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 19:22:56.283310 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 19:22:56.286642 WDT: Last reset was cold boot
418 19:22:56.290260 SPI1(PAD0) initialized at 2873684 Hz
419 19:22:56.293222 SPI5(PAD0) initialized at 992727 Hz
420 19:22:56.296619 VBOOT: Loading verstage.
421 19:22:56.303310 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 19:22:56.306712 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 19:22:56.309969 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 19:22:56.313198 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 19:22:56.321161 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 19:22:56.327774 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 19:22:56.338263 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 19:22:56.338623
429 19:22:56.338898
430 19:22:56.348799 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 19:22:56.352660 ARM64: Exception handlers installed.
432 19:22:56.352948 ARM64: Testing exception
433 19:22:56.355967 ARM64: Done test exception
434 19:22:56.359905 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 19:22:56.366233 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 19:22:56.379614 Probing TPM: . done!
437 19:22:56.379783 TPM ready after 0 ms
438 19:22:56.387332 Connected to device vid:did:rid of 1ae0:0028:00
439 19:22:56.393813 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
440 19:22:56.450219 Initialized TPM device CR50 revision 0
441 19:22:56.461563 tlcl_send_startup: Startup return code is 0
442 19:22:56.462019 TPM: setup succeeded
443 19:22:56.473220 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 19:22:56.481069 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 19:22:56.487827 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 19:22:56.503301 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 19:22:56.506715 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 19:22:56.514144 in-header: 03 07 00 00 08 00 00 00
449 19:22:56.517656 in-data: aa e4 47 04 13 02 00 00
450 19:22:56.521279 Chrome EC: UHEPI supported
451 19:22:56.528370 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 19:22:56.532464 in-header: 03 ad 00 00 08 00 00 00
453 19:22:56.535700 in-data: 00 20 20 08 00 00 00 00
454 19:22:56.536216 Phase 1
455 19:22:56.540610 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 19:22:56.546621 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 19:22:56.550251 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 19:22:56.554080 Recovery requested (1009000e)
459 19:22:56.562513 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 19:22:56.567532 tlcl_extend: response is 0
461 19:22:56.577872 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 19:22:56.583729 tlcl_extend: response is 0
463 19:22:56.590778 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 19:22:56.610961 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
465 19:22:56.617157 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 19:22:56.617754
467 19:22:56.618109
468 19:22:56.627983 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 19:22:56.631043 ARM64: Exception handlers installed.
470 19:22:56.631587 ARM64: Testing exception
471 19:22:56.634447 ARM64: Done test exception
472 19:22:56.655880 pmic_efuse_setting: Set efuses in 11 msecs
473 19:22:56.659311 pmwrap_interface_init: Select PMIF_VLD_RDY
474 19:22:56.665933 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 19:22:56.669449 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 19:22:56.676449 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 19:22:56.681720 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 19:22:56.683577 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 19:22:56.690764 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 19:22:56.694371 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 19:22:56.697654 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 19:22:56.701653 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 19:22:56.709212 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 19:22:56.713254 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 19:22:56.716993 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 19:22:56.723356 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 19:22:56.732311 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 19:22:56.734400 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 19:22:56.738254 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 19:22:56.747611 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 19:22:56.752097 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 19:22:56.756312 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 19:22:56.763174 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 19:22:56.766788 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 19:22:56.774083 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 19:22:56.777811 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 19:22:56.784913 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 19:22:56.788328 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 19:22:56.795852 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 19:22:56.799037 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 19:22:56.806575 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 19:22:56.810305 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 19:22:56.814074 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 19:22:56.821435 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 19:22:56.825286 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 19:22:56.828782 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 19:22:56.835621 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 19:22:56.839582 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 19:22:56.846485 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 19:22:56.850697 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 19:22:56.853553 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 19:22:56.861311 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 19:22:56.864413 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 19:22:56.868399 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 19:22:56.871710 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 19:22:56.875723 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 19:22:56.882662 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 19:22:56.886077 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 19:22:56.889787 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 19:22:56.893414 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 19:22:56.897212 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 19:22:56.904200 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 19:22:56.908383 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 19:22:56.911709 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 19:22:56.918783 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 19:22:56.925979 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 19:22:56.933363 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 19:22:56.940147 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 19:22:56.947826 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 19:22:56.951777 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 19:22:56.958758 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 19:22:56.962349 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 19:22:56.970272 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x12
534 19:22:56.973784 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 19:22:56.981070 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
536 19:22:56.984156 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 19:22:56.993771 [RTC]rtc_get_frequency_meter,154: input=15, output=835
538 19:22:57.002995 [RTC]rtc_get_frequency_meter,154: input=7, output=708
539 19:22:57.012177 [RTC]rtc_get_frequency_meter,154: input=11, output=772
540 19:22:57.021995 [RTC]rtc_get_frequency_meter,154: input=13, output=802
541 19:22:57.031213 [RTC]rtc_get_frequency_meter,154: input=12, output=787
542 19:22:57.041112 [RTC]rtc_get_frequency_meter,154: input=12, output=788
543 19:22:57.051094 [RTC]rtc_get_frequency_meter,154: input=13, output=803
544 19:22:57.054226 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
545 19:22:57.061607 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
546 19:22:57.065681 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 19:22:57.068866 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
548 19:22:57.072404 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 19:22:57.076373 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
550 19:22:57.079857 ADC[4]: Raw value=903400 ID=7
551 19:22:57.083873 ADC[3]: Raw value=213282 ID=1
552 19:22:57.084265 RAM Code: 0x71
553 19:22:57.087182 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 19:22:57.094685 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 19:22:57.101958 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 19:22:57.109173 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 19:22:57.112882 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 19:22:57.116184 in-header: 03 07 00 00 08 00 00 00
559 19:22:57.116273 in-data: aa e4 47 04 13 02 00 00
560 19:22:57.119941 Chrome EC: UHEPI supported
561 19:22:57.126638 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 19:22:57.130650 in-header: 03 ed 00 00 08 00 00 00
563 19:22:57.134703 in-data: 80 20 60 08 00 00 00 00
564 19:22:57.138952 MRC: failed to locate region type 0.
565 19:22:57.146237 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 19:22:57.146790 DRAM-K: Running full calibration
567 19:22:57.153992 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 19:22:57.157109 header.status = 0x0
569 19:22:57.160991 header.version = 0x6 (expected: 0x6)
570 19:22:57.164823 header.size = 0xd00 (expected: 0xd00)
571 19:22:57.165365 header.flags = 0x0
572 19:22:57.171449 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 19:22:57.188713 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
574 19:22:57.196387 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 19:22:57.199818 dram_init: ddr_geometry: 2
576 19:22:57.199902 [EMI] MDL number = 2
577 19:22:57.203719 [EMI] Get MDL freq = 0
578 19:22:57.203796 dram_init: ddr_type: 0
579 19:22:57.207519 is_discrete_lpddr4: 1
580 19:22:57.211163 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 19:22:57.211259
582 19:22:57.211325
583 19:22:57.211411 [Bian_co] ETT version 0.0.0.1
584 19:22:57.218272 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 19:22:57.218364
586 19:22:57.221872 dramc_set_vcore_voltage set vcore to 650000
587 19:22:57.221949 Read voltage for 800, 4
588 19:22:57.225708 Vio18 = 0
589 19:22:57.225784 Vcore = 650000
590 19:22:57.225876 Vdram = 0
591 19:22:57.225940 Vddq = 0
592 19:22:57.229538 Vmddr = 0
593 19:22:57.229614 dram_init: config_dvfs: 1
594 19:22:57.236179 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 19:22:57.240263 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 19:22:57.243800 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
597 19:22:57.247612 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
598 19:22:57.251573 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
599 19:22:57.254620 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
600 19:22:57.258585 MEM_TYPE=3, freq_sel=18
601 19:22:57.262583 sv_algorithm_assistance_LP4_1600
602 19:22:57.265773 ============ PULL DRAM RESETB DOWN ============
603 19:22:57.269131 ========== PULL DRAM RESETB DOWN end =========
604 19:22:57.272397 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 19:22:57.275818 ===================================
606 19:22:57.279129 LPDDR4 DRAM CONFIGURATION
607 19:22:57.282351 ===================================
608 19:22:57.285599 EX_ROW_EN[0] = 0x0
609 19:22:57.285700 EX_ROW_EN[1] = 0x0
610 19:22:57.289351 LP4Y_EN = 0x0
611 19:22:57.289466 WORK_FSP = 0x0
612 19:22:57.292622 WL = 0x2
613 19:22:57.292696 RL = 0x2
614 19:22:57.295833 BL = 0x2
615 19:22:57.295937 RPST = 0x0
616 19:22:57.299556 RD_PRE = 0x0
617 19:22:57.302314 WR_PRE = 0x1
618 19:22:57.302417 WR_PST = 0x0
619 19:22:57.305795 DBI_WR = 0x0
620 19:22:57.305907 DBI_RD = 0x0
621 19:22:57.309085 OTF = 0x1
622 19:22:57.312698 ===================================
623 19:22:57.315801 ===================================
624 19:22:57.315881 ANA top config
625 19:22:57.319132 ===================================
626 19:22:57.322229 DLL_ASYNC_EN = 0
627 19:22:57.325842 ALL_SLAVE_EN = 1
628 19:22:57.325933 NEW_RANK_MODE = 1
629 19:22:57.329255 DLL_IDLE_MODE = 1
630 19:22:57.332278 LP45_APHY_COMB_EN = 1
631 19:22:57.336029 TX_ODT_DIS = 1
632 19:22:57.336106 NEW_8X_MODE = 1
633 19:22:57.339076 ===================================
634 19:22:57.342423 ===================================
635 19:22:57.345722 data_rate = 1600
636 19:22:57.349017 CKR = 1
637 19:22:57.352171 DQ_P2S_RATIO = 8
638 19:22:57.355608 ===================================
639 19:22:57.358858 CA_P2S_RATIO = 8
640 19:22:57.362172 DQ_CA_OPEN = 0
641 19:22:57.362284 DQ_SEMI_OPEN = 0
642 19:22:57.365464 CA_SEMI_OPEN = 0
643 19:22:57.368768 CA_FULL_RATE = 0
644 19:22:57.372110 DQ_CKDIV4_EN = 1
645 19:22:57.375256 CA_CKDIV4_EN = 1
646 19:22:57.378531 CA_PREDIV_EN = 0
647 19:22:57.378668 PH8_DLY = 0
648 19:22:57.381795 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 19:22:57.385190 DQ_AAMCK_DIV = 4
650 19:22:57.388602 CA_AAMCK_DIV = 4
651 19:22:57.391724 CA_ADMCK_DIV = 4
652 19:22:57.395166 DQ_TRACK_CA_EN = 0
653 19:22:57.398358 CA_PICK = 800
654 19:22:57.398454 CA_MCKIO = 800
655 19:22:57.401756 MCKIO_SEMI = 0
656 19:22:57.405740 PLL_FREQ = 3068
657 19:22:57.409024 DQ_UI_PI_RATIO = 32
658 19:22:57.412862 CA_UI_PI_RATIO = 0
659 19:22:57.415810 ===================================
660 19:22:57.419664 ===================================
661 19:22:57.419780 memory_type:LPDDR4
662 19:22:57.423191 GP_NUM : 10
663 19:22:57.423278 SRAM_EN : 1
664 19:22:57.426707 MD32_EN : 0
665 19:22:57.430476 ===================================
666 19:22:57.430564 [ANA_INIT] >>>>>>>>>>>>>>
667 19:22:57.434434 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 19:22:57.437729 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 19:22:57.440870 ===================================
670 19:22:57.444599 data_rate = 1600,PCW = 0X7600
671 19:22:57.447725 ===================================
672 19:22:57.450985 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 19:22:57.457810 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 19:22:57.460978 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 19:22:57.467663 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 19:22:57.471148 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 19:22:57.474368 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 19:22:57.474449 [ANA_INIT] flow start
679 19:22:57.477786 [ANA_INIT] PLL >>>>>>>>
680 19:22:57.480959 [ANA_INIT] PLL <<<<<<<<
681 19:22:57.481062 [ANA_INIT] MIDPI >>>>>>>>
682 19:22:57.484377 [ANA_INIT] MIDPI <<<<<<<<
683 19:22:57.487698 [ANA_INIT] DLL >>>>>>>>
684 19:22:57.487811 [ANA_INIT] flow end
685 19:22:57.494338 ============ LP4 DIFF to SE enter ============
686 19:22:57.497510 ============ LP4 DIFF to SE exit ============
687 19:22:57.500794 [ANA_INIT] <<<<<<<<<<<<<
688 19:22:57.504128 [Flow] Enable top DCM control >>>>>
689 19:22:57.507556 [Flow] Enable top DCM control <<<<<
690 19:22:57.510777 Enable DLL master slave shuffle
691 19:22:57.514086 ==============================================================
692 19:22:57.517448 Gating Mode config
693 19:22:57.520760 ==============================================================
694 19:22:57.523883 Config description:
695 19:22:57.533646 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 19:22:57.540399 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 19:22:57.543779 SELPH_MODE 0: By rank 1: By Phase
698 19:22:57.550531 ==============================================================
699 19:22:57.553300 GAT_TRACK_EN = 1
700 19:22:57.556743 RX_GATING_MODE = 2
701 19:22:57.560276 RX_GATING_TRACK_MODE = 2
702 19:22:57.563332 SELPH_MODE = 1
703 19:22:57.566949 PICG_EARLY_EN = 1
704 19:22:57.567066 VALID_LAT_VALUE = 1
705 19:22:57.573899 ==============================================================
706 19:22:57.577259 Enter into Gating configuration >>>>
707 19:22:57.580426 Exit from Gating configuration <<<<
708 19:22:57.583807 Enter into DVFS_PRE_config >>>>>
709 19:22:57.593740 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 19:22:57.597130 Exit from DVFS_PRE_config <<<<<
711 19:22:57.600266 Enter into PICG configuration >>>>
712 19:22:57.603359 Exit from PICG configuration <<<<
713 19:22:57.606775 [RX_INPUT] configuration >>>>>
714 19:22:57.609999 [RX_INPUT] configuration <<<<<
715 19:22:57.616669 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 19:22:57.619975 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 19:22:57.627282 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 19:22:57.634668 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 19:22:57.637376 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 19:22:57.644156 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 19:22:57.647272 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 19:22:57.654229 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 19:22:57.657400 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 19:22:57.660323 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 19:22:57.663972 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 19:22:57.670674 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 19:22:57.673796 ===================================
728 19:22:57.677252 LPDDR4 DRAM CONFIGURATION
729 19:22:57.680287 ===================================
730 19:22:57.680377 EX_ROW_EN[0] = 0x0
731 19:22:57.683865 EX_ROW_EN[1] = 0x0
732 19:22:57.683980 LP4Y_EN = 0x0
733 19:22:57.687282 WORK_FSP = 0x0
734 19:22:57.687377 WL = 0x2
735 19:22:57.690537 RL = 0x2
736 19:22:57.690616 BL = 0x2
737 19:22:57.693842 RPST = 0x0
738 19:22:57.693931 RD_PRE = 0x0
739 19:22:57.697161 WR_PRE = 0x1
740 19:22:57.697293 WR_PST = 0x0
741 19:22:57.700426 DBI_WR = 0x0
742 19:22:57.700503 DBI_RD = 0x0
743 19:22:57.703652 OTF = 0x1
744 19:22:57.706960 ===================================
745 19:22:57.710249 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 19:22:57.713669 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 19:22:57.720479 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 19:22:57.723762 ===================================
749 19:22:57.723843 LPDDR4 DRAM CONFIGURATION
750 19:22:57.727167 ===================================
751 19:22:57.730558 EX_ROW_EN[0] = 0x10
752 19:22:57.733879 EX_ROW_EN[1] = 0x0
753 19:22:57.733988 LP4Y_EN = 0x0
754 19:22:57.737070 WORK_FSP = 0x0
755 19:22:57.737148 WL = 0x2
756 19:22:57.740494 RL = 0x2
757 19:22:57.740574 BL = 0x2
758 19:22:57.743720 RPST = 0x0
759 19:22:57.743825 RD_PRE = 0x0
760 19:22:57.747129 WR_PRE = 0x1
761 19:22:57.747209 WR_PST = 0x0
762 19:22:57.750313 DBI_WR = 0x0
763 19:22:57.750401 DBI_RD = 0x0
764 19:22:57.753479 OTF = 0x1
765 19:22:57.756892 ===================================
766 19:22:57.763697 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 19:22:57.766984 nWR fixed to 40
768 19:22:57.770202 [ModeRegInit_LP4] CH0 RK0
769 19:22:57.770288 [ModeRegInit_LP4] CH0 RK1
770 19:22:57.773314 [ModeRegInit_LP4] CH1 RK0
771 19:22:57.776760 [ModeRegInit_LP4] CH1 RK1
772 19:22:57.776851 match AC timing 13
773 19:22:57.783783 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 19:22:57.786933 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 19:22:57.789994 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 19:22:57.797023 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 19:22:57.800388 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 19:22:57.800535 [EMI DOE] emi_dcm 0
779 19:22:57.807139 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 19:22:57.807299 ==
781 19:22:57.810025 Dram Type= 6, Freq= 0, CH_0, rank 0
782 19:22:57.813688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 19:22:57.813914 ==
784 19:22:57.819733 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 19:22:57.826406 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 19:22:57.834408 [CA 0] Center 37 (7~68) winsize 62
787 19:22:57.836958 [CA 1] Center 37 (6~68) winsize 63
788 19:22:57.840333 [CA 2] Center 34 (4~65) winsize 62
789 19:22:57.844095 [CA 3] Center 34 (4~65) winsize 62
790 19:22:57.847394 [CA 4] Center 33 (3~64) winsize 62
791 19:22:57.850904 [CA 5] Center 33 (3~64) winsize 62
792 19:22:57.851060
793 19:22:57.854195 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 19:22:57.854354
795 19:22:57.857553 [CATrainingPosCal] consider 1 rank data
796 19:22:57.860729 u2DelayCellTimex100 = 270/100 ps
797 19:22:57.863879 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
798 19:22:57.870753 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
799 19:22:57.874200 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
800 19:22:57.877373 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
801 19:22:57.880608 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
802 19:22:57.883752 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 19:22:57.884193
804 19:22:57.887392 CA PerBit enable=1, Macro0, CA PI delay=33
805 19:22:57.887942
806 19:22:57.890517 [CBTSetCACLKResult] CA Dly = 33
807 19:22:57.893621 CS Dly: 6 (0~37)
808 19:22:57.894058 ==
809 19:22:57.897224 Dram Type= 6, Freq= 0, CH_0, rank 1
810 19:22:57.900230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 19:22:57.900795 ==
812 19:22:57.907370 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 19:22:57.910077 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 19:22:57.920633 [CA 0] Center 37 (6~68) winsize 63
815 19:22:57.924145 [CA 1] Center 37 (7~68) winsize 62
816 19:22:57.927330 [CA 2] Center 34 (4~65) winsize 62
817 19:22:57.930619 [CA 3] Center 34 (4~65) winsize 62
818 19:22:57.933910 [CA 4] Center 33 (3~64) winsize 62
819 19:22:57.937244 [CA 5] Center 33 (3~64) winsize 62
820 19:22:57.937706
821 19:22:57.940629 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 19:22:57.941049
823 19:22:57.943757 [CATrainingPosCal] consider 2 rank data
824 19:22:57.946856 u2DelayCellTimex100 = 270/100 ps
825 19:22:57.950252 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
826 19:22:57.956832 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
827 19:22:57.959885 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
828 19:22:57.963230 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
829 19:22:57.966893 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
830 19:22:57.969964 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 19:22:57.970466
832 19:22:57.973202 CA PerBit enable=1, Macro0, CA PI delay=33
833 19:22:57.973743
834 19:22:57.976761 [CBTSetCACLKResult] CA Dly = 33
835 19:22:57.979665 CS Dly: 6 (0~38)
836 19:22:57.980376
837 19:22:57.983321 ----->DramcWriteLeveling(PI) begin...
838 19:22:57.983765 ==
839 19:22:57.987111 Dram Type= 6, Freq= 0, CH_0, rank 0
840 19:22:57.990713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 19:22:57.991237 ==
842 19:22:57.994299 Write leveling (Byte 0): 34 => 34
843 19:22:57.997742 Write leveling (Byte 1): 28 => 28
844 19:22:57.998461 DramcWriteLeveling(PI) end<-----
845 19:22:57.999035
846 19:22:57.999538 ==
847 19:22:58.001629 Dram Type= 6, Freq= 0, CH_0, rank 0
848 19:22:58.008560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 19:22:58.009048 ==
850 19:22:58.009473 [Gating] SW mode calibration
851 19:22:58.018560 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 19:22:58.022302 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 19:22:58.025693 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 19:22:58.032489 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
855 19:22:58.035661 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
856 19:22:58.039084 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 19:22:58.045697 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 19:22:58.048972 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 19:22:58.052111 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 19:22:58.055325 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 19:22:58.062254 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 19:22:58.065481 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 19:22:58.068788 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 19:22:58.075631 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 19:22:58.078846 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 19:22:58.082195 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 19:22:58.088497 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 19:22:58.091629 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 19:22:58.095492 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 19:22:58.101558 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
871 19:22:58.105182 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
872 19:22:58.108416 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 19:22:58.115157 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 19:22:58.118166 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 19:22:58.121791 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 19:22:58.128303 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 19:22:58.131585 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 19:22:58.135040 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 19:22:58.140984 0 9 8 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)
880 19:22:58.144498 0 9 12 | B1->B0 | 2a2a 3434 | 1 1 | (0 0) (1 1)
881 19:22:58.147884 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 19:22:58.154792 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 19:22:58.157997 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 19:22:58.161278 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 19:22:58.167997 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 19:22:58.171515 0 10 4 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
887 19:22:58.174718 0 10 8 | B1->B0 | 3434 2525 | 0 0 | (1 1) (0 0)
888 19:22:58.181154 0 10 12 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
889 19:22:58.184371 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 19:22:58.187733 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 19:22:58.194646 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 19:22:58.197643 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 19:22:58.200973 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 19:22:58.207477 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
895 19:22:58.211157 0 11 8 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
896 19:22:58.214351 0 11 12 | B1->B0 | 3f3f 4646 | 0 0 | (1 1) (0 0)
897 19:22:58.220941 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 19:22:58.224050 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 19:22:58.227767 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 19:22:58.234131 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 19:22:58.237582 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 19:22:58.241146 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
903 19:22:58.247541 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
904 19:22:58.250399 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 19:22:58.253639 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 19:22:58.260342 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 19:22:58.263699 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 19:22:58.267049 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 19:22:58.273813 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 19:22:58.277159 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 19:22:58.280620 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 19:22:58.287186 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 19:22:58.290460 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 19:22:58.293632 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 19:22:58.300125 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 19:22:58.303805 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 19:22:58.307036 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 19:22:58.310136 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
919 19:22:58.317095 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
920 19:22:58.320073 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
921 19:22:58.323322 Total UI for P1: 0, mck2ui 16
922 19:22:58.326859 best dqsien dly found for B0: ( 0, 14, 10)
923 19:22:58.330304 Total UI for P1: 0, mck2ui 16
924 19:22:58.333380 best dqsien dly found for B1: ( 0, 14, 10)
925 19:22:58.336857 best DQS0 dly(MCK, UI, PI) = (0, 14, 10)
926 19:22:58.339753 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
927 19:22:58.340253
928 19:22:58.343498 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 10)
929 19:22:58.350199 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
930 19:22:58.350710 [Gating] SW calibration Done
931 19:22:58.351081 ==
932 19:22:58.353432 Dram Type= 6, Freq= 0, CH_0, rank 0
933 19:22:58.359459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 19:22:58.359923 ==
935 19:22:58.360306 RX Vref Scan: 0
936 19:22:58.360712
937 19:22:58.362878 RX Vref 0 -> 0, step: 1
938 19:22:58.363308
939 19:22:58.366611 RX Delay -130 -> 252, step: 16
940 19:22:58.369870 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
941 19:22:58.373223 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
942 19:22:58.376763 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
943 19:22:58.382994 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
944 19:22:58.386264 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
945 19:22:58.389560 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
946 19:22:58.392871 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
947 19:22:58.396508 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
948 19:22:58.403133 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
949 19:22:58.406580 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
950 19:22:58.409688 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
951 19:22:58.412641 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
952 19:22:58.419385 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
953 19:22:58.422442 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
954 19:22:58.425890 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
955 19:22:58.429165 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
956 19:22:58.429640 ==
957 19:22:58.432850 Dram Type= 6, Freq= 0, CH_0, rank 0
958 19:22:58.439032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 19:22:58.439464 ==
960 19:22:58.439803 DQS Delay:
961 19:22:58.440119 DQS0 = 0, DQS1 = 0
962 19:22:58.442563 DQM Delay:
963 19:22:58.442994 DQM0 = 86, DQM1 = 75
964 19:22:58.446012 DQ Delay:
965 19:22:58.449530 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
966 19:22:58.449961 DQ4 =85, DQ5 =77, DQ6 =93, DQ7 =93
967 19:22:58.452624 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =69
968 19:22:58.455989 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
969 19:22:58.459450
970 19:22:58.460066
971 19:22:58.460427 ==
972 19:22:58.462935 Dram Type= 6, Freq= 0, CH_0, rank 0
973 19:22:58.466040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 19:22:58.466469 ==
975 19:22:58.466809
976 19:22:58.467123
977 19:22:58.469270 TX Vref Scan disable
978 19:22:58.469728 == TX Byte 0 ==
979 19:22:58.475545 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
980 19:22:58.478956 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
981 19:22:58.479475 == TX Byte 1 ==
982 19:22:58.485410 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
983 19:22:58.488889 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
984 19:22:58.489460 ==
985 19:22:58.491968 Dram Type= 6, Freq= 0, CH_0, rank 0
986 19:22:58.495255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 19:22:58.495926 ==
988 19:22:58.509924 TX Vref=22, minBit 3, minWin=27, winSum=440
989 19:22:58.513203 TX Vref=24, minBit 4, minWin=27, winSum=441
990 19:22:58.516833 TX Vref=26, minBit 6, minWin=27, winSum=444
991 19:22:58.519884 TX Vref=28, minBit 8, minWin=27, winSum=446
992 19:22:58.523215 TX Vref=30, minBit 8, minWin=27, winSum=448
993 19:22:58.529807 TX Vref=32, minBit 11, minWin=26, winSum=440
994 19:22:58.533039 [TxChooseVref] Worse bit 8, Min win 27, Win sum 448, Final Vref 30
995 19:22:58.533548
996 19:22:58.536530 Final TX Range 1 Vref 30
997 19:22:58.536957
998 19:22:58.537295 ==
999 19:22:58.540276 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 19:22:58.543213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 19:22:58.546365 ==
1002 19:22:58.546796
1003 19:22:58.547138
1004 19:22:58.547614 TX Vref Scan disable
1005 19:22:58.550184 == TX Byte 0 ==
1006 19:22:58.553503 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1007 19:22:58.560273 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1008 19:22:58.560702 == TX Byte 1 ==
1009 19:22:58.563174 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1010 19:22:58.569795 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1011 19:22:58.570219
1012 19:22:58.570551 [DATLAT]
1013 19:22:58.570861 Freq=800, CH0 RK0
1014 19:22:58.571212
1015 19:22:58.573257 DATLAT Default: 0xa
1016 19:22:58.573739 0, 0xFFFF, sum = 0
1017 19:22:58.577024 1, 0xFFFF, sum = 0
1018 19:22:58.577539 2, 0xFFFF, sum = 0
1019 19:22:58.580011 3, 0xFFFF, sum = 0
1020 19:22:58.583413 4, 0xFFFF, sum = 0
1021 19:22:58.583838 5, 0xFFFF, sum = 0
1022 19:22:58.586616 6, 0xFFFF, sum = 0
1023 19:22:58.587055 7, 0xFFFF, sum = 0
1024 19:22:58.589789 8, 0xFFFF, sum = 0
1025 19:22:58.590245 9, 0x0, sum = 1
1026 19:22:58.593197 10, 0x0, sum = 2
1027 19:22:58.593639 11, 0x0, sum = 3
1028 19:22:58.593974 12, 0x0, sum = 4
1029 19:22:58.596418 best_step = 10
1030 19:22:58.596833
1031 19:22:58.597159 ==
1032 19:22:58.599586 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 19:22:58.602977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 19:22:58.603395 ==
1035 19:22:58.606232 RX Vref Scan: 1
1036 19:22:58.606648
1037 19:22:58.609963 Set Vref Range= 32 -> 127
1038 19:22:58.610377
1039 19:22:58.610705 RX Vref 32 -> 127, step: 1
1040 19:22:58.611013
1041 19:22:58.613193 RX Delay -111 -> 252, step: 8
1042 19:22:58.613655
1043 19:22:58.616385 Set Vref, RX VrefLevel [Byte0]: 32
1044 19:22:58.619591 [Byte1]: 32
1045 19:22:58.623257
1046 19:22:58.623674 Set Vref, RX VrefLevel [Byte0]: 33
1047 19:22:58.626310 [Byte1]: 33
1048 19:22:58.630331
1049 19:22:58.630747 Set Vref, RX VrefLevel [Byte0]: 34
1050 19:22:58.634134 [Byte1]: 34
1051 19:22:58.638009
1052 19:22:58.638423 Set Vref, RX VrefLevel [Byte0]: 35
1053 19:22:58.641317 [Byte1]: 35
1054 19:22:58.646181
1055 19:22:58.646607 Set Vref, RX VrefLevel [Byte0]: 36
1056 19:22:58.649550 [Byte1]: 36
1057 19:22:58.653963
1058 19:22:58.654378 Set Vref, RX VrefLevel [Byte0]: 37
1059 19:22:58.657003 [Byte1]: 37
1060 19:22:58.661565
1061 19:22:58.661989 Set Vref, RX VrefLevel [Byte0]: 38
1062 19:22:58.664770 [Byte1]: 38
1063 19:22:58.669483
1064 19:22:58.669910 Set Vref, RX VrefLevel [Byte0]: 39
1065 19:22:58.672251 [Byte1]: 39
1066 19:22:58.676530
1067 19:22:58.679544 Set Vref, RX VrefLevel [Byte0]: 40
1068 19:22:58.680058 [Byte1]: 40
1069 19:22:58.683648
1070 19:22:58.687297 Set Vref, RX VrefLevel [Byte0]: 41
1071 19:22:58.687717 [Byte1]: 41
1072 19:22:58.691693
1073 19:22:58.692171 Set Vref, RX VrefLevel [Byte0]: 42
1074 19:22:58.694995 [Byte1]: 42
1075 19:22:58.699502
1076 19:22:58.699919 Set Vref, RX VrefLevel [Byte0]: 43
1077 19:22:58.702765 [Byte1]: 43
1078 19:22:58.706934
1079 19:22:58.707369 Set Vref, RX VrefLevel [Byte0]: 44
1080 19:22:58.710455 [Byte1]: 44
1081 19:22:58.714943
1082 19:22:58.715386 Set Vref, RX VrefLevel [Byte0]: 45
1083 19:22:58.718408 [Byte1]: 45
1084 19:22:58.722300
1085 19:22:58.722717 Set Vref, RX VrefLevel [Byte0]: 46
1086 19:22:58.725612 [Byte1]: 46
1087 19:22:58.730014
1088 19:22:58.730436 Set Vref, RX VrefLevel [Byte0]: 47
1089 19:22:58.733423 [Byte1]: 47
1090 19:22:58.737441
1091 19:22:58.737884 Set Vref, RX VrefLevel [Byte0]: 48
1092 19:22:58.744072 [Byte1]: 48
1093 19:22:58.744502
1094 19:22:58.747375 Set Vref, RX VrefLevel [Byte0]: 49
1095 19:22:58.750763 [Byte1]: 49
1096 19:22:58.751235
1097 19:22:58.754001 Set Vref, RX VrefLevel [Byte0]: 50
1098 19:22:58.757170 [Byte1]: 50
1099 19:22:58.760287
1100 19:22:58.760390 Set Vref, RX VrefLevel [Byte0]: 51
1101 19:22:58.763461 [Byte1]: 51
1102 19:22:58.768093
1103 19:22:58.768195 Set Vref, RX VrefLevel [Byte0]: 52
1104 19:22:58.770792 [Byte1]: 52
1105 19:22:58.775483
1106 19:22:58.775561 Set Vref, RX VrefLevel [Byte0]: 53
1107 19:22:58.778596 [Byte1]: 53
1108 19:22:58.783206
1109 19:22:58.783307 Set Vref, RX VrefLevel [Byte0]: 54
1110 19:22:58.786333 [Byte1]: 54
1111 19:22:58.790569
1112 19:22:58.790673 Set Vref, RX VrefLevel [Byte0]: 55
1113 19:22:58.794208 [Byte1]: 55
1114 19:22:58.798642
1115 19:22:58.798720 Set Vref, RX VrefLevel [Byte0]: 56
1116 19:22:58.801891 [Byte1]: 56
1117 19:22:58.805790
1118 19:22:58.805872 Set Vref, RX VrefLevel [Byte0]: 57
1119 19:22:58.809650 [Byte1]: 57
1120 19:22:58.813628
1121 19:22:58.813729 Set Vref, RX VrefLevel [Byte0]: 58
1122 19:22:58.816896 [Byte1]: 58
1123 19:22:58.821537
1124 19:22:58.821626 Set Vref, RX VrefLevel [Byte0]: 59
1125 19:22:58.824807 [Byte1]: 59
1126 19:22:58.828739
1127 19:22:58.828816 Set Vref, RX VrefLevel [Byte0]: 60
1128 19:22:58.832040 [Byte1]: 60
1129 19:22:58.836604
1130 19:22:58.836686 Set Vref, RX VrefLevel [Byte0]: 61
1131 19:22:58.840177 [Byte1]: 61
1132 19:22:58.844248
1133 19:22:58.844349 Set Vref, RX VrefLevel [Byte0]: 62
1134 19:22:58.847603 [Byte1]: 62
1135 19:22:58.852059
1136 19:22:58.852159 Set Vref, RX VrefLevel [Byte0]: 63
1137 19:22:58.855320 [Byte1]: 63
1138 19:22:58.859543
1139 19:22:58.859646 Set Vref, RX VrefLevel [Byte0]: 64
1140 19:22:58.862806 [Byte1]: 64
1141 19:22:58.867456
1142 19:22:58.867538 Set Vref, RX VrefLevel [Byte0]: 65
1143 19:22:58.870747 [Byte1]: 65
1144 19:22:58.874742
1145 19:22:58.874823 Set Vref, RX VrefLevel [Byte0]: 66
1146 19:22:58.877942 [Byte1]: 66
1147 19:22:58.882554
1148 19:22:58.882635 Set Vref, RX VrefLevel [Byte0]: 67
1149 19:22:58.885723 [Byte1]: 67
1150 19:22:58.890033
1151 19:22:58.890114 Set Vref, RX VrefLevel [Byte0]: 68
1152 19:22:58.893302 [Byte1]: 68
1153 19:22:58.897613
1154 19:22:58.897694 Set Vref, RX VrefLevel [Byte0]: 69
1155 19:22:58.901232 [Byte1]: 69
1156 19:22:58.905639
1157 19:22:58.905722 Set Vref, RX VrefLevel [Byte0]: 70
1158 19:22:58.908676 [Byte1]: 70
1159 19:22:58.912937
1160 19:22:58.913045 Set Vref, RX VrefLevel [Byte0]: 71
1161 19:22:58.916488 [Byte1]: 71
1162 19:22:58.920834
1163 19:22:58.920911 Set Vref, RX VrefLevel [Byte0]: 72
1164 19:22:58.923990 [Byte1]: 72
1165 19:22:58.928345
1166 19:22:58.928441 Set Vref, RX VrefLevel [Byte0]: 73
1167 19:22:58.931696 [Byte1]: 73
1168 19:22:58.936214
1169 19:22:58.936287 Set Vref, RX VrefLevel [Byte0]: 74
1170 19:22:58.939659 [Byte1]: 74
1171 19:22:58.943971
1172 19:22:58.944069 Set Vref, RX VrefLevel [Byte0]: 75
1173 19:22:58.947111 [Byte1]: 75
1174 19:22:58.951068
1175 19:22:58.951148 Set Vref, RX VrefLevel [Byte0]: 76
1176 19:22:58.954902 [Byte1]: 76
1177 19:22:58.959015
1178 19:22:58.959095 Set Vref, RX VrefLevel [Byte0]: 77
1179 19:22:58.962332 [Byte1]: 77
1180 19:22:58.966280
1181 19:22:58.966361 Set Vref, RX VrefLevel [Byte0]: 78
1182 19:22:58.969624 [Byte1]: 78
1183 19:22:58.973915
1184 19:22:58.973996 Set Vref, RX VrefLevel [Byte0]: 79
1185 19:22:58.977289 [Byte1]: 79
1186 19:22:58.981985
1187 19:22:58.982067 Set Vref, RX VrefLevel [Byte0]: 80
1188 19:22:58.985190 [Byte1]: 80
1189 19:22:58.989163
1190 19:22:58.989275 Set Vref, RX VrefLevel [Byte0]: 81
1191 19:22:58.993133 [Byte1]: 81
1192 19:22:58.997484
1193 19:22:58.997563 Set Vref, RX VrefLevel [Byte0]: 82
1194 19:22:59.000662 [Byte1]: 82
1195 19:22:59.005049
1196 19:22:59.005131 Set Vref, RX VrefLevel [Byte0]: 83
1197 19:22:59.008350 [Byte1]: 83
1198 19:22:59.012714
1199 19:22:59.012788 Final RX Vref Byte 0 = 68 to rank0
1200 19:22:59.015843 Final RX Vref Byte 1 = 50 to rank0
1201 19:22:59.019088 Final RX Vref Byte 0 = 68 to rank1
1202 19:22:59.022322 Final RX Vref Byte 1 = 50 to rank1==
1203 19:22:59.025914 Dram Type= 6, Freq= 0, CH_0, rank 0
1204 19:22:59.032576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1205 19:22:59.032656 ==
1206 19:22:59.032720 DQS Delay:
1207 19:22:59.032780 DQS0 = 0, DQS1 = 0
1208 19:22:59.035612 DQM Delay:
1209 19:22:59.035686 DQM0 = 88, DQM1 = 76
1210 19:22:59.038876 DQ Delay:
1211 19:22:59.042184 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =84
1212 19:22:59.045958 DQ4 =88, DQ5 =76, DQ6 =100, DQ7 =100
1213 19:22:59.049159 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1214 19:22:59.052325 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1215 19:22:59.052406
1216 19:22:59.052470
1217 19:22:59.096042 [DQSOSCAuto] RK0, (LSB)MR18= 0x3f20, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 393 ps
1218 19:22:59.096710 CH0 RK0: MR19=606, MR18=3F20
1219 19:22:59.096796 CH0_RK0: MR19=0x606, MR18=0x3F20, DQSOSC=393, MR23=63, INC=95, DEC=63
1220 19:22:59.096862
1221 19:22:59.097119 ----->DramcWriteLeveling(PI) begin...
1222 19:22:59.097186 ==
1223 19:22:59.097247 Dram Type= 6, Freq= 0, CH_0, rank 1
1224 19:22:59.097316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1225 19:22:59.097416 ==
1226 19:22:59.097474 Write leveling (Byte 0): 31 => 31
1227 19:22:59.097531 Write leveling (Byte 1): 31 => 31
1228 19:22:59.098019 DramcWriteLeveling(PI) end<-----
1229 19:22:59.098101
1230 19:22:59.098165 ==
1231 19:22:59.098225 Dram Type= 6, Freq= 0, CH_0, rank 1
1232 19:22:59.098469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1233 19:22:59.098533 ==
1234 19:22:59.123861 [Gating] SW mode calibration
1235 19:22:59.124485 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1236 19:22:59.125076 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1237 19:22:59.125817 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1238 19:22:59.126085 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1239 19:22:59.126155 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1240 19:22:59.128515 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1241 19:22:59.131809 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 19:22:59.138690 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 19:22:59.141849 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 19:22:59.145073 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 19:22:59.151714 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 19:22:59.155019 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 19:22:59.158759 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 19:22:59.165238 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 19:22:59.168722 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 19:22:59.172015 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 19:22:59.178618 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 19:22:59.181788 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 19:22:59.185102 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 19:22:59.191778 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 19:22:59.194498 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1256 19:22:59.198447 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 19:22:59.204513 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 19:22:59.207945 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 19:22:59.211244 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 19:22:59.218115 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1261 19:22:59.221273 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1262 19:22:59.224981 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1263 19:22:59.231377 0 9 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
1264 19:22:59.234340 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1265 19:22:59.238103 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1266 19:22:59.241850 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1267 19:22:59.249457 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1268 19:22:59.253250 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1269 19:22:59.255977 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1270 19:22:59.259517 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1271 19:22:59.266362 0 10 8 | B1->B0 | 2f2f 2b2b | 0 0 | (0 1) (0 0)
1272 19:22:59.269658 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1273 19:22:59.273102 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1274 19:22:59.279704 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1275 19:22:59.282971 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1276 19:22:59.286796 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1277 19:22:59.292698 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1278 19:22:59.295967 0 11 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1279 19:22:59.299394 0 11 8 | B1->B0 | 3131 3d3d | 0 0 | (0 0) (0 0)
1280 19:22:59.305943 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1281 19:22:59.309115 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1282 19:22:59.312592 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1283 19:22:59.319692 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1284 19:22:59.322215 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1285 19:22:59.325931 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1286 19:22:59.332355 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1287 19:22:59.335603 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1288 19:22:59.338962 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1289 19:22:59.345660 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1290 19:22:59.348835 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1291 19:22:59.352172 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1292 19:22:59.358738 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1293 19:22:59.361888 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1294 19:22:59.365315 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1295 19:22:59.371736 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1296 19:22:59.374932 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1297 19:22:59.378234 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1298 19:22:59.385211 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1299 19:22:59.388556 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1300 19:22:59.391660 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1301 19:22:59.398431 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1302 19:22:59.401704 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1303 19:22:59.404563 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1304 19:22:59.411356 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1305 19:22:59.414499 Total UI for P1: 0, mck2ui 16
1306 19:22:59.418074 best dqsien dly found for B0: ( 0, 14, 8)
1307 19:22:59.421325 Total UI for P1: 0, mck2ui 16
1308 19:22:59.424831 best dqsien dly found for B1: ( 0, 14, 8)
1309 19:22:59.428073 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1310 19:22:59.431357 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1311 19:22:59.431867
1312 19:22:59.434274 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1313 19:22:59.437667 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1314 19:22:59.441079 [Gating] SW calibration Done
1315 19:22:59.441619 ==
1316 19:22:59.444503 Dram Type= 6, Freq= 0, CH_0, rank 1
1317 19:22:59.447767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1318 19:22:59.448192 ==
1319 19:22:59.451148 RX Vref Scan: 0
1320 19:22:59.451569
1321 19:22:59.454248 RX Vref 0 -> 0, step: 1
1322 19:22:59.454802
1323 19:22:59.455155 RX Delay -130 -> 252, step: 16
1324 19:22:59.460776 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1325 19:22:59.463981 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1326 19:22:59.467915 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1327 19:22:59.470498 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1328 19:22:59.474223 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1329 19:22:59.480633 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1330 19:22:59.484316 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1331 19:22:59.487490 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1332 19:22:59.490824 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1333 19:22:59.494149 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1334 19:22:59.500713 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1335 19:22:59.504031 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1336 19:22:59.507419 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1337 19:22:59.510676 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1338 19:22:59.517422 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1339 19:22:59.520692 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1340 19:22:59.521102 ==
1341 19:22:59.523836 Dram Type= 6, Freq= 0, CH_0, rank 1
1342 19:22:59.527191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1343 19:22:59.527607 ==
1344 19:22:59.530563 DQS Delay:
1345 19:22:59.531104 DQS0 = 0, DQS1 = 0
1346 19:22:59.531583 DQM Delay:
1347 19:22:59.534022 DQM0 = 84, DQM1 = 76
1348 19:22:59.534431 DQ Delay:
1349 19:22:59.537268 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
1350 19:22:59.540625 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1351 19:22:59.543416 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =69
1352 19:22:59.547148 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1353 19:22:59.547600
1354 19:22:59.547938
1355 19:22:59.548266 ==
1356 19:22:59.550289 Dram Type= 6, Freq= 0, CH_0, rank 1
1357 19:22:59.556962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1358 19:22:59.557543 ==
1359 19:22:59.557944
1360 19:22:59.558255
1361 19:22:59.558640 TX Vref Scan disable
1362 19:22:59.560308 == TX Byte 0 ==
1363 19:22:59.563394 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1364 19:22:59.570005 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1365 19:22:59.570449 == TX Byte 1 ==
1366 19:22:59.573013 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1367 19:22:59.579516 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1368 19:22:59.579931 ==
1369 19:22:59.583155 Dram Type= 6, Freq= 0, CH_0, rank 1
1370 19:22:59.586413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1371 19:22:59.586720 ==
1372 19:22:59.598567 TX Vref=22, minBit 9, minWin=27, winSum=443
1373 19:22:59.602354 TX Vref=24, minBit 8, minWin=27, winSum=444
1374 19:22:59.605746 TX Vref=26, minBit 9, minWin=27, winSum=448
1375 19:22:59.608431 TX Vref=28, minBit 8, minWin=27, winSum=450
1376 19:22:59.611804 TX Vref=30, minBit 8, minWin=27, winSum=445
1377 19:22:59.619283 TX Vref=32, minBit 9, minWin=27, winSum=444
1378 19:22:59.622606 [TxChooseVref] Worse bit 8, Min win 27, Win sum 450, Final Vref 28
1379 19:22:59.623107
1380 19:22:59.625836 Final TX Range 1 Vref 28
1381 19:22:59.626248
1382 19:22:59.626622 ==
1383 19:22:59.629247 Dram Type= 6, Freq= 0, CH_0, rank 1
1384 19:22:59.632356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1385 19:22:59.632779 ==
1386 19:22:59.635887
1387 19:22:59.636294
1388 19:22:59.636617 TX Vref Scan disable
1389 19:22:59.639156 == TX Byte 0 ==
1390 19:22:59.642565 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1391 19:22:59.648908 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1392 19:22:59.649524 == TX Byte 1 ==
1393 19:22:59.652145 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1394 19:22:59.658574 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1395 19:22:59.659008
1396 19:22:59.659339 [DATLAT]
1397 19:22:59.659728 Freq=800, CH0 RK1
1398 19:22:59.660080
1399 19:22:59.661843 DATLAT Default: 0xa
1400 19:22:59.662249 0, 0xFFFF, sum = 0
1401 19:22:59.665236 1, 0xFFFF, sum = 0
1402 19:22:59.668584 2, 0xFFFF, sum = 0
1403 19:22:59.669064 3, 0xFFFF, sum = 0
1404 19:22:59.671730 4, 0xFFFF, sum = 0
1405 19:22:59.672321 5, 0xFFFF, sum = 0
1406 19:22:59.675256 6, 0xFFFF, sum = 0
1407 19:22:59.675698 7, 0xFFFF, sum = 0
1408 19:22:59.678335 8, 0xFFFF, sum = 0
1409 19:22:59.678812 9, 0x0, sum = 1
1410 19:22:59.681992 10, 0x0, sum = 2
1411 19:22:59.682407 11, 0x0, sum = 3
1412 19:22:59.685318 12, 0x0, sum = 4
1413 19:22:59.685778 best_step = 10
1414 19:22:59.686150
1415 19:22:59.686498 ==
1416 19:22:59.688395 Dram Type= 6, Freq= 0, CH_0, rank 1
1417 19:22:59.691446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1418 19:22:59.691869 ==
1419 19:22:59.695164 RX Vref Scan: 0
1420 19:22:59.695570
1421 19:22:59.698267 RX Vref 0 -> 0, step: 1
1422 19:22:59.698824
1423 19:22:59.699299 RX Delay -111 -> 252, step: 8
1424 19:22:59.705887 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1425 19:22:59.708706 iDelay=217, Bit 1, Center 92 (-23 ~ 208) 232
1426 19:22:59.712600 iDelay=217, Bit 2, Center 80 (-31 ~ 192) 224
1427 19:22:59.715972 iDelay=217, Bit 3, Center 76 (-39 ~ 192) 232
1428 19:22:59.719117 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1429 19:22:59.725850 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1430 19:22:59.729295 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1431 19:22:59.732489 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1432 19:22:59.735895 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
1433 19:22:59.739095 iDelay=217, Bit 9, Center 64 (-47 ~ 176) 224
1434 19:22:59.745661 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1435 19:22:59.748984 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1436 19:22:59.752325 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1437 19:22:59.755548 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1438 19:22:59.762017 iDelay=217, Bit 14, Center 88 (-23 ~ 200) 224
1439 19:22:59.765129 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1440 19:22:59.765581 ==
1441 19:22:59.768886 Dram Type= 6, Freq= 0, CH_0, rank 1
1442 19:22:59.772082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1443 19:22:59.772655 ==
1444 19:22:59.775492 DQS Delay:
1445 19:22:59.775960 DQS0 = 0, DQS1 = 0
1446 19:22:59.776287 DQM Delay:
1447 19:22:59.778730 DQM0 = 85, DQM1 = 77
1448 19:22:59.779176 DQ Delay:
1449 19:22:59.781931 DQ0 =84, DQ1 =92, DQ2 =80, DQ3 =76
1450 19:22:59.784954 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =96
1451 19:22:59.788499 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1452 19:22:59.791476 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =84
1453 19:22:59.791885
1454 19:22:59.792230
1455 19:22:59.801396 [DQSOSCAuto] RK1, (LSB)MR18= 0x3d04, (MSB)MR19= 0x606, tDQSOscB0 = 409 ps tDQSOscB1 = 394 ps
1456 19:22:59.801839 CH0 RK1: MR19=606, MR18=3D04
1457 19:22:59.807888 CH0_RK1: MR19=0x606, MR18=0x3D04, DQSOSC=394, MR23=63, INC=95, DEC=63
1458 19:22:59.811835 [RxdqsGatingPostProcess] freq 800
1459 19:22:59.818232 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1460 19:22:59.821308 Pre-setting of DQS Precalculation
1461 19:22:59.824938 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1462 19:22:59.825400 ==
1463 19:22:59.828459 Dram Type= 6, Freq= 0, CH_1, rank 0
1464 19:22:59.834384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1465 19:22:59.834833 ==
1466 19:22:59.837919 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1467 19:22:59.844353 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1468 19:22:59.854229 [CA 0] Center 36 (6~67) winsize 62
1469 19:22:59.857326 [CA 1] Center 36 (6~67) winsize 62
1470 19:22:59.860398 [CA 2] Center 34 (4~65) winsize 62
1471 19:22:59.863719 [CA 3] Center 34 (3~65) winsize 63
1472 19:22:59.867139 [CA 4] Center 34 (4~65) winsize 62
1473 19:22:59.870975 [CA 5] Center 34 (3~65) winsize 63
1474 19:22:59.871507
1475 19:22:59.874167 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1476 19:22:59.874581
1477 19:22:59.877156 [CATrainingPosCal] consider 1 rank data
1478 19:22:59.880573 u2DelayCellTimex100 = 270/100 ps
1479 19:22:59.883881 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1480 19:22:59.890203 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1481 19:22:59.893919 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1482 19:22:59.897141 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1483 19:22:59.900142 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1484 19:22:59.903342 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1485 19:22:59.903754
1486 19:22:59.906924 CA PerBit enable=1, Macro0, CA PI delay=34
1487 19:22:59.907407
1488 19:22:59.910617 [CBTSetCACLKResult] CA Dly = 34
1489 19:22:59.911116 CS Dly: 5 (0~36)
1490 19:22:59.911455 ==
1491 19:22:59.914503 Dram Type= 6, Freq= 0, CH_1, rank 1
1492 19:22:59.917803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1493 19:22:59.921799 ==
1494 19:22:59.925093 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1495 19:22:59.931964 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1496 19:22:59.940501 [CA 0] Center 36 (6~67) winsize 62
1497 19:22:59.943806 [CA 1] Center 36 (6~67) winsize 62
1498 19:22:59.946828 [CA 2] Center 34 (4~65) winsize 62
1499 19:22:59.950129 [CA 3] Center 34 (3~65) winsize 63
1500 19:22:59.953430 [CA 4] Center 34 (4~65) winsize 62
1501 19:22:59.956863 [CA 5] Center 34 (4~65) winsize 62
1502 19:22:59.957285
1503 19:22:59.960290 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1504 19:22:59.960712
1505 19:22:59.963640 [CATrainingPosCal] consider 2 rank data
1506 19:22:59.966683 u2DelayCellTimex100 = 270/100 ps
1507 19:22:59.970040 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1508 19:22:59.976712 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1509 19:22:59.979961 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1510 19:22:59.982861 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1511 19:22:59.986453 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1512 19:22:59.989508 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1513 19:22:59.989928
1514 19:22:59.992937 CA PerBit enable=1, Macro0, CA PI delay=34
1515 19:22:59.993385
1516 19:22:59.996224 [CBTSetCACLKResult] CA Dly = 34
1517 19:23:00.000011 CS Dly: 6 (0~38)
1518 19:23:00.000431
1519 19:23:00.003006 ----->DramcWriteLeveling(PI) begin...
1520 19:23:00.003565 ==
1521 19:23:00.006068 Dram Type= 6, Freq= 0, CH_1, rank 0
1522 19:23:00.009945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1523 19:23:00.010369 ==
1524 19:23:00.013000 Write leveling (Byte 0): 24 => 24
1525 19:23:00.016045 Write leveling (Byte 1): 30 => 30
1526 19:23:00.019154 DramcWriteLeveling(PI) end<-----
1527 19:23:00.019577
1528 19:23:00.019911 ==
1529 19:23:00.023124 Dram Type= 6, Freq= 0, CH_1, rank 0
1530 19:23:00.026541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1531 19:23:00.026978 ==
1532 19:23:00.029880 [Gating] SW mode calibration
1533 19:23:00.036512 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1534 19:23:00.042833 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1535 19:23:00.046032 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1536 19:23:00.049676 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1537 19:23:00.055793 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1538 19:23:00.059175 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 19:23:00.062893 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 19:23:00.069256 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 19:23:00.072456 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 19:23:00.076284 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 19:23:00.082445 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 19:23:00.085775 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 19:23:00.089028 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 19:23:00.096292 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 19:23:00.099255 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 19:23:00.102405 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 19:23:00.108761 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 19:23:00.111987 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 19:23:00.115375 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 19:23:00.122407 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1553 19:23:00.125297 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1554 19:23:00.128876 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 19:23:00.135543 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 19:23:00.138866 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 19:23:00.142086 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 19:23:00.148730 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1559 19:23:00.151841 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1560 19:23:00.155183 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1561 19:23:00.161554 0 9 8 | B1->B0 | 2c2c 3131 | 0 0 | (0 0) (0 0)
1562 19:23:00.165432 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1563 19:23:00.168803 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1564 19:23:00.175371 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1565 19:23:00.178342 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1566 19:23:00.181408 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1567 19:23:00.185238 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1568 19:23:00.192271 0 10 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 0)
1569 19:23:00.195088 0 10 8 | B1->B0 | 2c2c 2323 | 0 0 | (1 1) (0 0)
1570 19:23:00.198367 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1571 19:23:00.204784 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1572 19:23:00.208145 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1573 19:23:00.211517 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1574 19:23:00.218705 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1575 19:23:00.221596 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1576 19:23:00.224968 0 11 4 | B1->B0 | 2424 2a2a | 0 0 | (0 0) (0 0)
1577 19:23:00.231254 0 11 8 | B1->B0 | 3838 3c3c | 1 0 | (1 1) (1 1)
1578 19:23:00.235341 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1579 19:23:00.238110 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1580 19:23:00.244741 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1581 19:23:00.247620 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1582 19:23:00.251088 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1583 19:23:00.257946 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1584 19:23:00.261394 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1585 19:23:00.264796 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1586 19:23:00.270919 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1587 19:23:00.274263 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1588 19:23:00.277982 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1589 19:23:00.284584 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1590 19:23:00.287791 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1591 19:23:00.290852 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1592 19:23:00.297892 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1593 19:23:00.301515 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1594 19:23:00.304488 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1595 19:23:00.310950 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1596 19:23:00.314167 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1597 19:23:00.317271 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1598 19:23:00.323843 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1599 19:23:00.327603 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1600 19:23:00.330910 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1601 19:23:00.337434 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1602 19:23:00.337956 Total UI for P1: 0, mck2ui 16
1603 19:23:00.343873 best dqsien dly found for B0: ( 0, 14, 4)
1604 19:23:00.347027 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1605 19:23:00.350797 Total UI for P1: 0, mck2ui 16
1606 19:23:00.354066 best dqsien dly found for B1: ( 0, 14, 8)
1607 19:23:00.357198 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1608 19:23:00.360422 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1609 19:23:00.360852
1610 19:23:00.363806 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1611 19:23:00.367003 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1612 19:23:00.370460 [Gating] SW calibration Done
1613 19:23:00.370884 ==
1614 19:23:00.373835 Dram Type= 6, Freq= 0, CH_1, rank 0
1615 19:23:00.377109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1616 19:23:00.377629 ==
1617 19:23:00.380468 RX Vref Scan: 0
1618 19:23:00.380891
1619 19:23:00.383698 RX Vref 0 -> 0, step: 1
1620 19:23:00.384152
1621 19:23:00.386984 RX Delay -130 -> 252, step: 16
1622 19:23:00.390084 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1623 19:23:00.393791 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1624 19:23:00.396969 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1625 19:23:00.400544 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1626 19:23:00.403690 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1627 19:23:00.410003 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1628 19:23:00.413386 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1629 19:23:00.416543 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1630 19:23:00.419813 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1631 19:23:00.426802 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1632 19:23:00.429896 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1633 19:23:00.433458 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1634 19:23:00.436417 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1635 19:23:00.440218 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1636 19:23:00.446714 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1637 19:23:00.449774 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1638 19:23:00.450191 ==
1639 19:23:00.453603 Dram Type= 6, Freq= 0, CH_1, rank 0
1640 19:23:00.456276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1641 19:23:00.456696 ==
1642 19:23:00.460303 DQS Delay:
1643 19:23:00.460719 DQS0 = 0, DQS1 = 0
1644 19:23:00.461118 DQM Delay:
1645 19:23:00.463377 DQM0 = 89, DQM1 = 78
1646 19:23:00.463875 DQ Delay:
1647 19:23:00.466563 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1648 19:23:00.469868 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1649 19:23:00.473065 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1650 19:23:00.476275 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1651 19:23:00.476687
1652 19:23:00.477010
1653 19:23:00.477311 ==
1654 19:23:00.479512 Dram Type= 6, Freq= 0, CH_1, rank 0
1655 19:23:00.486835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1656 19:23:00.487264 ==
1657 19:23:00.487591
1658 19:23:00.487892
1659 19:23:00.488180 TX Vref Scan disable
1660 19:23:00.490839 == TX Byte 0 ==
1661 19:23:00.494161 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1662 19:23:00.497429 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1663 19:23:00.500853 == TX Byte 1 ==
1664 19:23:00.504042 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1665 19:23:00.507174 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1666 19:23:00.510320 ==
1667 19:23:00.510736 Dram Type= 6, Freq= 0, CH_1, rank 0
1668 19:23:00.516731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1669 19:23:00.517147 ==
1670 19:23:00.529965 TX Vref=22, minBit 10, minWin=26, winSum=439
1671 19:23:00.533062 TX Vref=24, minBit 0, minWin=27, winSum=441
1672 19:23:00.536088 TX Vref=26, minBit 0, minWin=27, winSum=442
1673 19:23:00.539948 TX Vref=28, minBit 1, minWin=27, winSum=447
1674 19:23:00.543299 TX Vref=30, minBit 1, minWin=27, winSum=444
1675 19:23:00.549264 TX Vref=32, minBit 1, minWin=27, winSum=441
1676 19:23:00.553067 [TxChooseVref] Worse bit 1, Min win 27, Win sum 447, Final Vref 28
1677 19:23:00.553527
1678 19:23:00.556468 Final TX Range 1 Vref 28
1679 19:23:00.556884
1680 19:23:00.557215 ==
1681 19:23:00.559737 Dram Type= 6, Freq= 0, CH_1, rank 0
1682 19:23:00.562800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1683 19:23:00.563218 ==
1684 19:23:00.565981
1685 19:23:00.566391
1686 19:23:00.566721 TX Vref Scan disable
1687 19:23:00.570307 == TX Byte 0 ==
1688 19:23:00.573411 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1689 19:23:00.580066 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1690 19:23:00.580600 == TX Byte 1 ==
1691 19:23:00.583195 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1692 19:23:00.589865 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1693 19:23:00.590411
1694 19:23:00.590748 [DATLAT]
1695 19:23:00.591054 Freq=800, CH1 RK0
1696 19:23:00.591353
1697 19:23:00.593188 DATLAT Default: 0xa
1698 19:23:00.593623 0, 0xFFFF, sum = 0
1699 19:23:00.596482 1, 0xFFFF, sum = 0
1700 19:23:00.596907 2, 0xFFFF, sum = 0
1701 19:23:00.599659 3, 0xFFFF, sum = 0
1702 19:23:00.602975 4, 0xFFFF, sum = 0
1703 19:23:00.603557 5, 0xFFFF, sum = 0
1704 19:23:00.606185 6, 0xFFFF, sum = 0
1705 19:23:00.606610 7, 0xFFFF, sum = 0
1706 19:23:00.609632 8, 0xFFFF, sum = 0
1707 19:23:00.610138 9, 0x0, sum = 1
1708 19:23:00.612850 10, 0x0, sum = 2
1709 19:23:00.613450 11, 0x0, sum = 3
1710 19:23:00.613833 12, 0x0, sum = 4
1711 19:23:00.616049 best_step = 10
1712 19:23:00.616469
1713 19:23:00.616819 ==
1714 19:23:00.619148 Dram Type= 6, Freq= 0, CH_1, rank 0
1715 19:23:00.623139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1716 19:23:00.623563 ==
1717 19:23:00.626207 RX Vref Scan: 1
1718 19:23:00.626636
1719 19:23:00.629648 Set Vref Range= 32 -> 127
1720 19:23:00.630206
1721 19:23:00.630582 RX Vref 32 -> 127, step: 1
1722 19:23:00.630926
1723 19:23:00.632494 RX Delay -95 -> 252, step: 8
1724 19:23:00.632914
1725 19:23:00.636212 Set Vref, RX VrefLevel [Byte0]: 32
1726 19:23:00.639395 [Byte1]: 32
1727 19:23:00.642496
1728 19:23:00.642914 Set Vref, RX VrefLevel [Byte0]: 33
1729 19:23:00.645734 [Byte1]: 33
1730 19:23:00.650074
1731 19:23:00.650490 Set Vref, RX VrefLevel [Byte0]: 34
1732 19:23:00.653083 [Byte1]: 34
1733 19:23:00.657880
1734 19:23:00.658298 Set Vref, RX VrefLevel [Byte0]: 35
1735 19:23:00.661204 [Byte1]: 35
1736 19:23:00.665373
1737 19:23:00.665818 Set Vref, RX VrefLevel [Byte0]: 36
1738 19:23:00.668457 [Byte1]: 36
1739 19:23:00.672937
1740 19:23:00.673390 Set Vref, RX VrefLevel [Byte0]: 37
1741 19:23:00.679756 [Byte1]: 37
1742 19:23:00.680279
1743 19:23:00.682526 Set Vref, RX VrefLevel [Byte0]: 38
1744 19:23:00.685773 [Byte1]: 38
1745 19:23:00.686185
1746 19:23:00.689054 Set Vref, RX VrefLevel [Byte0]: 39
1747 19:23:00.692372 [Byte1]: 39
1748 19:23:00.692783
1749 19:23:00.695731 Set Vref, RX VrefLevel [Byte0]: 40
1750 19:23:00.699206 [Byte1]: 40
1751 19:23:00.703137
1752 19:23:00.703544 Set Vref, RX VrefLevel [Byte0]: 41
1753 19:23:00.706407 [Byte1]: 41
1754 19:23:00.711047
1755 19:23:00.711456 Set Vref, RX VrefLevel [Byte0]: 42
1756 19:23:00.714270 [Byte1]: 42
1757 19:23:00.718264
1758 19:23:00.718671 Set Vref, RX VrefLevel [Byte0]: 43
1759 19:23:00.721506 [Byte1]: 43
1760 19:23:00.726025
1761 19:23:00.726436 Set Vref, RX VrefLevel [Byte0]: 44
1762 19:23:00.729262 [Byte1]: 44
1763 19:23:00.733846
1764 19:23:00.734289 Set Vref, RX VrefLevel [Byte0]: 45
1765 19:23:00.736957 [Byte1]: 45
1766 19:23:00.741188
1767 19:23:00.741644 Set Vref, RX VrefLevel [Byte0]: 46
1768 19:23:00.744429 [Byte1]: 46
1769 19:23:00.749177
1770 19:23:00.749641 Set Vref, RX VrefLevel [Byte0]: 47
1771 19:23:00.752118 [Byte1]: 47
1772 19:23:00.756651
1773 19:23:00.757059 Set Vref, RX VrefLevel [Byte0]: 48
1774 19:23:00.759856 [Byte1]: 48
1775 19:23:00.764288
1776 19:23:00.764708 Set Vref, RX VrefLevel [Byte0]: 49
1777 19:23:00.767430 [Byte1]: 49
1778 19:23:00.771836
1779 19:23:00.772246 Set Vref, RX VrefLevel [Byte0]: 50
1780 19:23:00.778423 [Byte1]: 50
1781 19:23:00.778834
1782 19:23:00.781535 Set Vref, RX VrefLevel [Byte0]: 51
1783 19:23:00.784866 [Byte1]: 51
1784 19:23:00.785429
1785 19:23:00.788217 Set Vref, RX VrefLevel [Byte0]: 52
1786 19:23:00.791270 [Byte1]: 52
1787 19:23:00.791683
1788 19:23:00.794503 Set Vref, RX VrefLevel [Byte0]: 53
1789 19:23:00.797957 [Byte1]: 53
1790 19:23:00.801779
1791 19:23:00.802320 Set Vref, RX VrefLevel [Byte0]: 54
1792 19:23:00.805001 [Byte1]: 54
1793 19:23:00.809494
1794 19:23:00.810011 Set Vref, RX VrefLevel [Byte0]: 55
1795 19:23:00.812709 [Byte1]: 55
1796 19:23:00.817492
1797 19:23:00.817903 Set Vref, RX VrefLevel [Byte0]: 56
1798 19:23:00.820734 [Byte1]: 56
1799 19:23:00.824853
1800 19:23:00.825262 Set Vref, RX VrefLevel [Byte0]: 57
1801 19:23:00.827802 [Byte1]: 57
1802 19:23:00.832705
1803 19:23:00.833242 Set Vref, RX VrefLevel [Byte0]: 58
1804 19:23:00.835966 [Byte1]: 58
1805 19:23:00.839807
1806 19:23:00.840215 Set Vref, RX VrefLevel [Byte0]: 59
1807 19:23:00.843078 [Byte1]: 59
1808 19:23:00.847622
1809 19:23:00.848032 Set Vref, RX VrefLevel [Byte0]: 60
1810 19:23:00.850859 [Byte1]: 60
1811 19:23:00.855044
1812 19:23:00.855452 Set Vref, RX VrefLevel [Byte0]: 61
1813 19:23:00.858503 [Byte1]: 61
1814 19:23:00.862721
1815 19:23:00.863162 Set Vref, RX VrefLevel [Byte0]: 62
1816 19:23:00.865822 [Byte1]: 62
1817 19:23:00.870160
1818 19:23:00.870569 Set Vref, RX VrefLevel [Byte0]: 63
1819 19:23:00.873601 [Byte1]: 63
1820 19:23:00.877996
1821 19:23:00.878402 Set Vref, RX VrefLevel [Byte0]: 64
1822 19:23:00.881278 [Byte1]: 64
1823 19:23:00.885820
1824 19:23:00.886238 Set Vref, RX VrefLevel [Byte0]: 65
1825 19:23:00.889091 [Byte1]: 65
1826 19:23:00.892975
1827 19:23:00.893428 Set Vref, RX VrefLevel [Byte0]: 66
1828 19:23:00.896246 [Byte1]: 66
1829 19:23:00.900736
1830 19:23:00.901152 Set Vref, RX VrefLevel [Byte0]: 67
1831 19:23:00.904327 [Byte1]: 67
1832 19:23:00.908375
1833 19:23:00.908791 Set Vref, RX VrefLevel [Byte0]: 68
1834 19:23:00.911647 [Byte1]: 68
1835 19:23:00.916073
1836 19:23:00.916492 Set Vref, RX VrefLevel [Byte0]: 69
1837 19:23:00.919454 [Byte1]: 69
1838 19:23:00.923374
1839 19:23:00.923792 Set Vref, RX VrefLevel [Byte0]: 70
1840 19:23:00.926825 [Byte1]: 70
1841 19:23:00.931358
1842 19:23:00.931778 Set Vref, RX VrefLevel [Byte0]: 71
1843 19:23:00.934364 [Byte1]: 71
1844 19:23:00.938471
1845 19:23:00.938887 Set Vref, RX VrefLevel [Byte0]: 72
1846 19:23:00.941819 [Byte1]: 72
1847 19:23:00.946591
1848 19:23:00.947111 Set Vref, RX VrefLevel [Byte0]: 73
1849 19:23:00.949580 [Byte1]: 73
1850 19:23:00.954230
1851 19:23:00.954737 Set Vref, RX VrefLevel [Byte0]: 74
1852 19:23:00.957426 [Byte1]: 74
1853 19:23:00.961719
1854 19:23:00.962131 Set Vref, RX VrefLevel [Byte0]: 75
1855 19:23:00.964812 [Byte1]: 75
1856 19:23:00.969286
1857 19:23:00.969754 Set Vref, RX VrefLevel [Byte0]: 76
1858 19:23:00.975409 [Byte1]: 76
1859 19:23:00.975869
1860 19:23:00.979285 Final RX Vref Byte 0 = 63 to rank0
1861 19:23:00.982045 Final RX Vref Byte 1 = 65 to rank0
1862 19:23:00.985664 Final RX Vref Byte 0 = 63 to rank1
1863 19:23:00.988817 Final RX Vref Byte 1 = 65 to rank1==
1864 19:23:00.992201 Dram Type= 6, Freq= 0, CH_1, rank 0
1865 19:23:00.996056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1866 19:23:00.996480 ==
1867 19:23:00.996817 DQS Delay:
1868 19:23:00.999152 DQS0 = 0, DQS1 = 0
1869 19:23:00.999574 DQM Delay:
1870 19:23:01.002453 DQM0 = 86, DQM1 = 79
1871 19:23:01.002876 DQ Delay:
1872 19:23:01.005770 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =84
1873 19:23:01.009045 DQ4 =80, DQ5 =100, DQ6 =96, DQ7 =80
1874 19:23:01.012333 DQ8 =68, DQ9 =68, DQ10 =84, DQ11 =68
1875 19:23:01.015216 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =88
1876 19:23:01.015644
1877 19:23:01.015981
1878 19:23:01.022348 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c18, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 398 ps
1879 19:23:01.025576 CH1 RK0: MR19=606, MR18=2C18
1880 19:23:01.032321 CH1_RK0: MR19=0x606, MR18=0x2C18, DQSOSC=398, MR23=63, INC=93, DEC=62
1881 19:23:01.032823
1882 19:23:01.035303 ----->DramcWriteLeveling(PI) begin...
1883 19:23:01.035385 ==
1884 19:23:01.038443 Dram Type= 6, Freq= 0, CH_1, rank 1
1885 19:23:01.041731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1886 19:23:01.044476 ==
1887 19:23:01.047782 Write leveling (Byte 0): 25 => 25
1888 19:23:01.047863 Write leveling (Byte 1): 28 => 28
1889 19:23:01.051628 DramcWriteLeveling(PI) end<-----
1890 19:23:01.051704
1891 19:23:01.051766 ==
1892 19:23:01.054979 Dram Type= 6, Freq= 0, CH_1, rank 1
1893 19:23:01.061593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1894 19:23:01.061672 ==
1895 19:23:01.064822 [Gating] SW mode calibration
1896 19:23:01.071207 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1897 19:23:01.074297 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1898 19:23:01.081507 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1899 19:23:01.084433 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1900 19:23:01.087856 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 19:23:01.094505 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 19:23:01.097937 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 19:23:01.100707 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 19:23:01.107366 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 19:23:01.110670 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 19:23:01.114002 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 19:23:01.120636 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 19:23:01.123931 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 19:23:01.127705 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 19:23:01.134060 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 19:23:01.137373 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 19:23:01.140341 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1913 19:23:01.147423 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1914 19:23:01.150696 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1915 19:23:01.154040 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1916 19:23:01.160525 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1917 19:23:01.163803 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1918 19:23:01.167047 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1919 19:23:01.173366 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1920 19:23:01.176449 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1921 19:23:01.179922 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1922 19:23:01.186526 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1923 19:23:01.190368 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1924 19:23:01.193435 0 9 8 | B1->B0 | 3232 2a2a | 0 0 | (0 0) (0 0)
1925 19:23:01.199986 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1926 19:23:01.203139 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1927 19:23:01.206624 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1928 19:23:01.212994 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1929 19:23:01.216253 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1930 19:23:01.219294 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1931 19:23:01.225765 0 10 4 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 0)
1932 19:23:01.229772 0 10 8 | B1->B0 | 2626 2f2f | 0 1 | (0 0) (1 0)
1933 19:23:01.232589 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1934 19:23:01.238930 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1935 19:23:01.242664 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1936 19:23:01.246037 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1937 19:23:01.252747 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1938 19:23:01.255573 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1939 19:23:01.259313 0 11 4 | B1->B0 | 2929 2323 | 1 0 | (0 0) (0 0)
1940 19:23:01.265844 0 11 8 | B1->B0 | 4444 3434 | 0 0 | (0 0) (0 0)
1941 19:23:01.269210 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1942 19:23:01.272496 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1943 19:23:01.278781 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1944 19:23:01.282378 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1945 19:23:01.285839 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1946 19:23:01.288995 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1947 19:23:01.295612 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1948 19:23:01.298885 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1949 19:23:01.305220 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1950 19:23:01.308936 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1951 19:23:01.312091 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1952 19:23:01.318744 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1953 19:23:01.321832 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1954 19:23:01.325109 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1955 19:23:01.331640 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1956 19:23:01.334994 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1957 19:23:01.338322 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1958 19:23:01.344784 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1959 19:23:01.348228 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1960 19:23:01.351443 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1961 19:23:01.355287 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1962 19:23:01.362246 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1963 19:23:01.364965 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1964 19:23:01.368422 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1965 19:23:01.371638 Total UI for P1: 0, mck2ui 16
1966 19:23:01.374915 best dqsien dly found for B0: ( 0, 14, 4)
1967 19:23:01.378093 Total UI for P1: 0, mck2ui 16
1968 19:23:01.381394 best dqsien dly found for B1: ( 0, 14, 4)
1969 19:23:01.384766 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1970 19:23:01.388291 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1971 19:23:01.391365
1972 19:23:01.395156 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1973 19:23:01.398509 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1974 19:23:01.401092 [Gating] SW calibration Done
1975 19:23:01.401173 ==
1976 19:23:01.404409 Dram Type= 6, Freq= 0, CH_1, rank 1
1977 19:23:01.407862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1978 19:23:01.407944 ==
1979 19:23:01.408009 RX Vref Scan: 0
1980 19:23:01.408070
1981 19:23:01.411351 RX Vref 0 -> 0, step: 1
1982 19:23:01.411433
1983 19:23:01.414444 RX Delay -130 -> 252, step: 16
1984 19:23:01.417636 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1985 19:23:01.420938 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1986 19:23:01.427580 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1987 19:23:01.431435 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1988 19:23:01.434793 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1989 19:23:01.437969 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1990 19:23:01.444550 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1991 19:23:01.447936 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1992 19:23:01.451276 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1993 19:23:01.454386 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1994 19:23:01.457896 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1995 19:23:01.464277 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1996 19:23:01.467693 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1997 19:23:01.471059 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1998 19:23:01.474431 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1999 19:23:01.477286 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
2000 19:23:01.480834 ==
2001 19:23:01.480914 Dram Type= 6, Freq= 0, CH_1, rank 1
2002 19:23:01.487182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2003 19:23:01.487261 ==
2004 19:23:01.487324 DQS Delay:
2005 19:23:01.490676 DQS0 = 0, DQS1 = 0
2006 19:23:01.490749 DQM Delay:
2007 19:23:01.493797 DQM0 = 87, DQM1 = 76
2008 19:23:01.493869 DQ Delay:
2009 19:23:01.497322 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
2010 19:23:01.500564 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
2011 19:23:01.503623 DQ8 =61, DQ9 =69, DQ10 =77, DQ11 =61
2012 19:23:01.506929 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
2013 19:23:01.507009
2014 19:23:01.507074
2015 19:23:01.507136 ==
2016 19:23:01.510274 Dram Type= 6, Freq= 0, CH_1, rank 1
2017 19:23:01.514106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2018 19:23:01.514191 ==
2019 19:23:01.514255
2020 19:23:01.514315
2021 19:23:01.517265 TX Vref Scan disable
2022 19:23:01.520442 == TX Byte 0 ==
2023 19:23:01.523678 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2024 19:23:01.526997 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2025 19:23:01.530405 == TX Byte 1 ==
2026 19:23:01.533650 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2027 19:23:01.537296 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2028 19:23:01.537414 ==
2029 19:23:01.540359 Dram Type= 6, Freq= 0, CH_1, rank 1
2030 19:23:01.546706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2031 19:23:01.546787 ==
2032 19:23:01.558827 TX Vref=22, minBit 9, minWin=26, winSum=439
2033 19:23:01.562024 TX Vref=24, minBit 1, minWin=27, winSum=446
2034 19:23:01.565334 TX Vref=26, minBit 8, minWin=27, winSum=445
2035 19:23:01.568497 TX Vref=28, minBit 1, minWin=27, winSum=448
2036 19:23:01.571792 TX Vref=30, minBit 8, minWin=27, winSum=450
2037 19:23:01.578900 TX Vref=32, minBit 1, minWin=27, winSum=446
2038 19:23:01.582109 [TxChooseVref] Worse bit 8, Min win 27, Win sum 450, Final Vref 30
2039 19:23:01.582191
2040 19:23:01.585490 Final TX Range 1 Vref 30
2041 19:23:01.585572
2042 19:23:01.585637 ==
2043 19:23:01.588778 Dram Type= 6, Freq= 0, CH_1, rank 1
2044 19:23:01.591998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2045 19:23:01.592080 ==
2046 19:23:01.595016
2047 19:23:01.595098
2048 19:23:01.595162 TX Vref Scan disable
2049 19:23:01.598632 == TX Byte 0 ==
2050 19:23:01.601983 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2051 19:23:01.605118 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2052 19:23:01.608755 == TX Byte 1 ==
2053 19:23:01.611570 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2054 19:23:01.618257 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2055 19:23:01.618342
2056 19:23:01.618406 [DATLAT]
2057 19:23:01.618467 Freq=800, CH1 RK1
2058 19:23:01.618526
2059 19:23:01.621611 DATLAT Default: 0xa
2060 19:23:01.621694 0, 0xFFFF, sum = 0
2061 19:23:01.625353 1, 0xFFFF, sum = 0
2062 19:23:01.625451 2, 0xFFFF, sum = 0
2063 19:23:01.628438 3, 0xFFFF, sum = 0
2064 19:23:01.631770 4, 0xFFFF, sum = 0
2065 19:23:01.631873 5, 0xFFFF, sum = 0
2066 19:23:01.635086 6, 0xFFFF, sum = 0
2067 19:23:01.635169 7, 0xFFFF, sum = 0
2068 19:23:01.638483 8, 0xFFFF, sum = 0
2069 19:23:01.638566 9, 0x0, sum = 1
2070 19:23:01.641731 10, 0x0, sum = 2
2071 19:23:01.641814 11, 0x0, sum = 3
2072 19:23:01.641880 12, 0x0, sum = 4
2073 19:23:01.645001 best_step = 10
2074 19:23:01.645082
2075 19:23:01.645145 ==
2076 19:23:01.648109 Dram Type= 6, Freq= 0, CH_1, rank 1
2077 19:23:01.651800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2078 19:23:01.651882 ==
2079 19:23:01.654681 RX Vref Scan: 0
2080 19:23:01.654762
2081 19:23:01.658187 RX Vref 0 -> 0, step: 1
2082 19:23:01.658269
2083 19:23:01.658333 RX Delay -111 -> 252, step: 8
2084 19:23:01.665241 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2085 19:23:01.668564 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2086 19:23:01.671794 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
2087 19:23:01.675164 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
2088 19:23:01.678504 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2089 19:23:01.685005 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2090 19:23:01.688351 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2091 19:23:01.691542 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2092 19:23:01.695446 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2093 19:23:01.698655 iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232
2094 19:23:01.705284 iDelay=217, Bit 10, Center 80 (-39 ~ 200) 240
2095 19:23:01.708238 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
2096 19:23:01.711848 iDelay=217, Bit 12, Center 88 (-23 ~ 200) 224
2097 19:23:01.714715 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2098 19:23:01.721630 iDelay=217, Bit 14, Center 88 (-23 ~ 200) 224
2099 19:23:01.725067 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2100 19:23:01.725174 ==
2101 19:23:01.728278 Dram Type= 6, Freq= 0, CH_1, rank 1
2102 19:23:01.731227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2103 19:23:01.731310 ==
2104 19:23:01.734864 DQS Delay:
2105 19:23:01.734945 DQS0 = 0, DQS1 = 0
2106 19:23:01.735010 DQM Delay:
2107 19:23:01.737969 DQM0 = 87, DQM1 = 79
2108 19:23:01.738055 DQ Delay:
2109 19:23:01.741234 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
2110 19:23:01.744635 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2111 19:23:01.747741 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
2112 19:23:01.751148 DQ12 =88, DQ13 =84, DQ14 =88, DQ15 =88
2113 19:23:01.751254
2114 19:23:01.751350
2115 19:23:01.760855 [DQSOSCAuto] RK1, (LSB)MR18= 0x160e, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 404 ps
2116 19:23:01.764641 CH1 RK1: MR19=606, MR18=160E
2117 19:23:01.767997 CH1_RK1: MR19=0x606, MR18=0x160E, DQSOSC=404, MR23=63, INC=90, DEC=60
2118 19:23:01.771074 [RxdqsGatingPostProcess] freq 800
2119 19:23:01.777604 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2120 19:23:01.780868 Pre-setting of DQS Precalculation
2121 19:23:01.784204 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2122 19:23:01.794234 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2123 19:23:01.801242 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2124 19:23:01.801385
2125 19:23:01.801452
2126 19:23:01.804598 [Calibration Summary] 1600 Mbps
2127 19:23:01.804680 CH 0, Rank 0
2128 19:23:01.807276 SW Impedance : PASS
2129 19:23:01.807366 DUTY Scan : NO K
2130 19:23:01.810553 ZQ Calibration : PASS
2131 19:23:01.814633 Jitter Meter : NO K
2132 19:23:01.814716 CBT Training : PASS
2133 19:23:01.817875 Write leveling : PASS
2134 19:23:01.820572 RX DQS gating : PASS
2135 19:23:01.820653 RX DQ/DQS(RDDQC) : PASS
2136 19:23:01.823976 TX DQ/DQS : PASS
2137 19:23:01.827691 RX DATLAT : PASS
2138 19:23:01.827772 RX DQ/DQS(Engine): PASS
2139 19:23:01.830717 TX OE : NO K
2140 19:23:01.830799 All Pass.
2141 19:23:01.830863
2142 19:23:01.834366 CH 0, Rank 1
2143 19:23:01.834447 SW Impedance : PASS
2144 19:23:01.837506 DUTY Scan : NO K
2145 19:23:01.837588 ZQ Calibration : PASS
2146 19:23:01.840938 Jitter Meter : NO K
2147 19:23:01.844140 CBT Training : PASS
2148 19:23:01.844248 Write leveling : PASS
2149 19:23:01.847625 RX DQS gating : PASS
2150 19:23:01.850603 RX DQ/DQS(RDDQC) : PASS
2151 19:23:01.850685 TX DQ/DQS : PASS
2152 19:23:01.854488 RX DATLAT : PASS
2153 19:23:01.857848 RX DQ/DQS(Engine): PASS
2154 19:23:01.857930 TX OE : NO K
2155 19:23:01.861139 All Pass.
2156 19:23:01.861245
2157 19:23:01.861367 CH 1, Rank 0
2158 19:23:01.864265 SW Impedance : PASS
2159 19:23:01.864374 DUTY Scan : NO K
2160 19:23:01.867501 ZQ Calibration : PASS
2161 19:23:01.870772 Jitter Meter : NO K
2162 19:23:01.870854 CBT Training : PASS
2163 19:23:01.873787 Write leveling : PASS
2164 19:23:01.877508 RX DQS gating : PASS
2165 19:23:01.877590 RX DQ/DQS(RDDQC) : PASS
2166 19:23:01.880419 TX DQ/DQS : PASS
2167 19:23:01.883740 RX DATLAT : PASS
2168 19:23:01.883824 RX DQ/DQS(Engine): PASS
2169 19:23:01.886993 TX OE : NO K
2170 19:23:01.887069 All Pass.
2171 19:23:01.887130
2172 19:23:01.890408 CH 1, Rank 1
2173 19:23:01.890475 SW Impedance : PASS
2174 19:23:01.893583 DUTY Scan : NO K
2175 19:23:01.896918 ZQ Calibration : PASS
2176 19:23:01.896991 Jitter Meter : NO K
2177 19:23:01.900239 CBT Training : PASS
2178 19:23:01.900322 Write leveling : PASS
2179 19:23:01.903971 RX DQS gating : PASS
2180 19:23:01.906663 RX DQ/DQS(RDDQC) : PASS
2181 19:23:01.906740 TX DQ/DQS : PASS
2182 19:23:01.910025 RX DATLAT : PASS
2183 19:23:01.913316 RX DQ/DQS(Engine): PASS
2184 19:23:01.913430 TX OE : NO K
2185 19:23:01.916609 All Pass.
2186 19:23:01.916679
2187 19:23:01.916745 DramC Write-DBI off
2188 19:23:01.920502 PER_BANK_REFRESH: Hybrid Mode
2189 19:23:01.923774 TX_TRACKING: ON
2190 19:23:01.926467 [GetDramInforAfterCalByMRR] Vendor 6.
2191 19:23:01.930282 [GetDramInforAfterCalByMRR] Revision 606.
2192 19:23:01.933561 [GetDramInforAfterCalByMRR] Revision 2 0.
2193 19:23:01.933632 MR0 0x3b3b
2194 19:23:01.933693 MR8 0x5151
2195 19:23:01.940479 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2196 19:23:01.940550
2197 19:23:01.940611 MR0 0x3b3b
2198 19:23:01.940673 MR8 0x5151
2199 19:23:01.943027 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2200 19:23:01.943102
2201 19:23:01.953023 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2202 19:23:01.956554 [FAST_K] Save calibration result to emmc
2203 19:23:01.960095 [FAST_K] Save calibration result to emmc
2204 19:23:01.963128 dram_init: config_dvfs: 1
2205 19:23:01.966524 dramc_set_vcore_voltage set vcore to 662500
2206 19:23:01.969740 Read voltage for 1200, 2
2207 19:23:01.969821 Vio18 = 0
2208 19:23:01.973110 Vcore = 662500
2209 19:23:01.973217 Vdram = 0
2210 19:23:01.973310 Vddq = 0
2211 19:23:01.973436 Vmddr = 0
2212 19:23:01.979643 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2213 19:23:01.983028 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2214 19:23:01.986268 MEM_TYPE=3, freq_sel=15
2215 19:23:01.990077 sv_algorithm_assistance_LP4_1600
2216 19:23:01.992929 ============ PULL DRAM RESETB DOWN ============
2217 19:23:01.999640 ========== PULL DRAM RESETB DOWN end =========
2218 19:23:02.002587 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2219 19:23:02.006377 ===================================
2220 19:23:02.009685 LPDDR4 DRAM CONFIGURATION
2221 19:23:02.012947 ===================================
2222 19:23:02.013032 EX_ROW_EN[0] = 0x0
2223 19:23:02.016196 EX_ROW_EN[1] = 0x0
2224 19:23:02.016278 LP4Y_EN = 0x0
2225 19:23:02.019547 WORK_FSP = 0x0
2226 19:23:02.019628 WL = 0x4
2227 19:23:02.022892 RL = 0x4
2228 19:23:02.022973 BL = 0x2
2229 19:23:02.026014 RPST = 0x0
2230 19:23:02.029454 RD_PRE = 0x0
2231 19:23:02.029537 WR_PRE = 0x1
2232 19:23:02.032704 WR_PST = 0x0
2233 19:23:02.032774 DBI_WR = 0x0
2234 19:23:02.035965 DBI_RD = 0x0
2235 19:23:02.036046 OTF = 0x1
2236 19:23:02.039049 ===================================
2237 19:23:02.042692 ===================================
2238 19:23:02.045962 ANA top config
2239 19:23:02.049224 ===================================
2240 19:23:02.049306 DLL_ASYNC_EN = 0
2241 19:23:02.052683 ALL_SLAVE_EN = 0
2242 19:23:02.055782 NEW_RANK_MODE = 1
2243 19:23:02.059042 DLL_IDLE_MODE = 1
2244 19:23:02.059124 LP45_APHY_COMB_EN = 1
2245 19:23:02.062359 TX_ODT_DIS = 1
2246 19:23:02.065529 NEW_8X_MODE = 1
2247 19:23:02.068873 ===================================
2248 19:23:02.072115 ===================================
2249 19:23:02.075558 data_rate = 2400
2250 19:23:02.079061 CKR = 1
2251 19:23:02.082438 DQ_P2S_RATIO = 8
2252 19:23:02.085664 ===================================
2253 19:23:02.085737 CA_P2S_RATIO = 8
2254 19:23:02.088997 DQ_CA_OPEN = 0
2255 19:23:02.092356 DQ_SEMI_OPEN = 0
2256 19:23:02.095087 CA_SEMI_OPEN = 0
2257 19:23:02.098944 CA_FULL_RATE = 0
2258 19:23:02.102112 DQ_CKDIV4_EN = 0
2259 19:23:02.102191 CA_CKDIV4_EN = 0
2260 19:23:02.105217 CA_PREDIV_EN = 0
2261 19:23:02.108735 PH8_DLY = 17
2262 19:23:02.111745 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2263 19:23:02.115273 DQ_AAMCK_DIV = 4
2264 19:23:02.118492 CA_AAMCK_DIV = 4
2265 19:23:02.118573 CA_ADMCK_DIV = 4
2266 19:23:02.121689 DQ_TRACK_CA_EN = 0
2267 19:23:02.125537 CA_PICK = 1200
2268 19:23:02.128723 CA_MCKIO = 1200
2269 19:23:02.131888 MCKIO_SEMI = 0
2270 19:23:02.135140 PLL_FREQ = 2366
2271 19:23:02.138574 DQ_UI_PI_RATIO = 32
2272 19:23:02.141834 CA_UI_PI_RATIO = 0
2273 19:23:02.141906 ===================================
2274 19:23:02.145015 ===================================
2275 19:23:02.148054 memory_type:LPDDR4
2276 19:23:02.151925 GP_NUM : 10
2277 19:23:02.152007 SRAM_EN : 1
2278 19:23:02.155255 MD32_EN : 0
2279 19:23:02.158596 ===================================
2280 19:23:02.161761 [ANA_INIT] >>>>>>>>>>>>>>
2281 19:23:02.165055 <<<<<< [CONFIGURE PHASE]: ANA_TX
2282 19:23:02.168235 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2283 19:23:02.171502 ===================================
2284 19:23:02.171589 data_rate = 2400,PCW = 0X5b00
2285 19:23:02.174726 ===================================
2286 19:23:02.178055 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2287 19:23:02.185021 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2288 19:23:02.191510 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2289 19:23:02.194706 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2290 19:23:02.198025 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2291 19:23:02.201301 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2292 19:23:02.204604 [ANA_INIT] flow start
2293 19:23:02.207721 [ANA_INIT] PLL >>>>>>>>
2294 19:23:02.207803 [ANA_INIT] PLL <<<<<<<<
2295 19:23:02.210981 [ANA_INIT] MIDPI >>>>>>>>
2296 19:23:02.214321 [ANA_INIT] MIDPI <<<<<<<<
2297 19:23:02.214403 [ANA_INIT] DLL >>>>>>>>
2298 19:23:02.217707 [ANA_INIT] DLL <<<<<<<<
2299 19:23:02.220967 [ANA_INIT] flow end
2300 19:23:02.224850 ============ LP4 DIFF to SE enter ============
2301 19:23:02.227930 ============ LP4 DIFF to SE exit ============
2302 19:23:02.231573 [ANA_INIT] <<<<<<<<<<<<<
2303 19:23:02.234409 [Flow] Enable top DCM control >>>>>
2304 19:23:02.237527 [Flow] Enable top DCM control <<<<<
2305 19:23:02.241202 Enable DLL master slave shuffle
2306 19:23:02.244264 ==============================================================
2307 19:23:02.247542 Gating Mode config
2308 19:23:02.254341 ==============================================================
2309 19:23:02.254424 Config description:
2310 19:23:02.263927 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2311 19:23:02.270406 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2312 19:23:02.277118 SELPH_MODE 0: By rank 1: By Phase
2313 19:23:02.280501 ==============================================================
2314 19:23:02.283679 GAT_TRACK_EN = 1
2315 19:23:02.287664 RX_GATING_MODE = 2
2316 19:23:02.290846 RX_GATING_TRACK_MODE = 2
2317 19:23:02.294134 SELPH_MODE = 1
2318 19:23:02.297308 PICG_EARLY_EN = 1
2319 19:23:02.300271 VALID_LAT_VALUE = 1
2320 19:23:02.303613 ==============================================================
2321 19:23:02.306828 Enter into Gating configuration >>>>
2322 19:23:02.310242 Exit from Gating configuration <<<<
2323 19:23:02.314037 Enter into DVFS_PRE_config >>>>>
2324 19:23:02.326609 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2325 19:23:02.329983 Exit from DVFS_PRE_config <<<<<
2326 19:23:02.333280 Enter into PICG configuration >>>>
2327 19:23:02.336615 Exit from PICG configuration <<<<
2328 19:23:02.336698 [RX_INPUT] configuration >>>>>
2329 19:23:02.339897 [RX_INPUT] configuration <<<<<
2330 19:23:02.346811 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2331 19:23:02.350130 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2332 19:23:02.356416 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2333 19:23:02.362919 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2334 19:23:02.369678 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2335 19:23:02.376201 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2336 19:23:02.379542 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2337 19:23:02.383204 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2338 19:23:02.389869 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2339 19:23:02.392563 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2340 19:23:02.396561 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2341 19:23:02.399236 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2342 19:23:02.402653 ===================================
2343 19:23:02.406293 LPDDR4 DRAM CONFIGURATION
2344 19:23:02.409430 ===================================
2345 19:23:02.412877 EX_ROW_EN[0] = 0x0
2346 19:23:02.412977 EX_ROW_EN[1] = 0x0
2347 19:23:02.416261 LP4Y_EN = 0x0
2348 19:23:02.416367 WORK_FSP = 0x0
2349 19:23:02.419335 WL = 0x4
2350 19:23:02.419438 RL = 0x4
2351 19:23:02.422607 BL = 0x2
2352 19:23:02.422686 RPST = 0x0
2353 19:23:02.426020 RD_PRE = 0x0
2354 19:23:02.429056 WR_PRE = 0x1
2355 19:23:02.429146 WR_PST = 0x0
2356 19:23:02.432424 DBI_WR = 0x0
2357 19:23:02.432532 DBI_RD = 0x0
2358 19:23:02.435744 OTF = 0x1
2359 19:23:02.438975 ===================================
2360 19:23:02.442266 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2361 19:23:02.445969 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2362 19:23:02.449291 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2363 19:23:02.452644 ===================================
2364 19:23:02.455359 LPDDR4 DRAM CONFIGURATION
2365 19:23:02.459226 ===================================
2366 19:23:02.461952 EX_ROW_EN[0] = 0x10
2367 19:23:02.462031 EX_ROW_EN[1] = 0x0
2368 19:23:02.465092 LP4Y_EN = 0x0
2369 19:23:02.465165 WORK_FSP = 0x0
2370 19:23:02.468912 WL = 0x4
2371 19:23:02.472017 RL = 0x4
2372 19:23:02.472086 BL = 0x2
2373 19:23:02.475440 RPST = 0x0
2374 19:23:02.475516 RD_PRE = 0x0
2375 19:23:02.478438 WR_PRE = 0x1
2376 19:23:02.478516 WR_PST = 0x0
2377 19:23:02.481849 DBI_WR = 0x0
2378 19:23:02.481923 DBI_RD = 0x0
2379 19:23:02.485202 OTF = 0x1
2380 19:23:02.488656 ===================================
2381 19:23:02.494986 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2382 19:23:02.495071 ==
2383 19:23:02.498365 Dram Type= 6, Freq= 0, CH_0, rank 0
2384 19:23:02.502135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2385 19:23:02.502234 ==
2386 19:23:02.505517 [Duty_Offset_Calibration]
2387 19:23:02.505594 B0:1 B1:-1 CA:0
2388 19:23:02.505654
2389 19:23:02.508860 [DutyScan_Calibration_Flow] k_type=0
2390 19:23:02.517990
2391 19:23:02.518084 ==CLK 0==
2392 19:23:02.521814 Final CLK duty delay cell = 0
2393 19:23:02.524957 [0] MAX Duty = 5094%(X100), DQS PI = 16
2394 19:23:02.528299 [0] MIN Duty = 4875%(X100), DQS PI = 8
2395 19:23:02.528383 [0] AVG Duty = 4984%(X100)
2396 19:23:02.531612
2397 19:23:02.534593 CH0 CLK Duty spec in!! Max-Min= 219%
2398 19:23:02.538482 [DutyScan_Calibration_Flow] ====Done====
2399 19:23:02.538563
2400 19:23:02.541726 [DutyScan_Calibration_Flow] k_type=1
2401 19:23:02.556770
2402 19:23:02.556851 ==DQS 0 ==
2403 19:23:02.559996 Final DQS duty delay cell = -4
2404 19:23:02.563273 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2405 19:23:02.566704 [-4] MIN Duty = 4875%(X100), DQS PI = 6
2406 19:23:02.569972 [-4] AVG Duty = 4968%(X100)
2407 19:23:02.570054
2408 19:23:02.570117 ==DQS 1 ==
2409 19:23:02.573341 Final DQS duty delay cell = 0
2410 19:23:02.576578 [0] MAX Duty = 5124%(X100), DQS PI = 6
2411 19:23:02.579650 [0] MIN Duty = 5000%(X100), DQS PI = 20
2412 19:23:02.583629 [0] AVG Duty = 5062%(X100)
2413 19:23:02.583710
2414 19:23:02.586663 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2415 19:23:02.586744
2416 19:23:02.589797 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2417 19:23:02.592896 [DutyScan_Calibration_Flow] ====Done====
2418 19:23:02.592980
2419 19:23:02.596087 [DutyScan_Calibration_Flow] k_type=3
2420 19:23:02.614172
2421 19:23:02.614313 ==DQM 0 ==
2422 19:23:02.617786 Final DQM duty delay cell = 0
2423 19:23:02.620489 [0] MAX Duty = 5031%(X100), DQS PI = 18
2424 19:23:02.624348 [0] MIN Duty = 4875%(X100), DQS PI = 8
2425 19:23:02.627604 [0] AVG Duty = 4953%(X100)
2426 19:23:02.627699
2427 19:23:02.627766 ==DQM 1 ==
2428 19:23:02.630954 Final DQM duty delay cell = 4
2429 19:23:02.633622 [4] MAX Duty = 5187%(X100), DQS PI = 14
2430 19:23:02.637208 [4] MIN Duty = 4969%(X100), DQS PI = 26
2431 19:23:02.640677 [4] AVG Duty = 5078%(X100)
2432 19:23:02.640758
2433 19:23:02.643689 CH0 DQM 0 Duty spec in!! Max-Min= 156%
2434 19:23:02.643836
2435 19:23:02.647120 CH0 DQM 1 Duty spec in!! Max-Min= 218%
2436 19:23:02.650281 [DutyScan_Calibration_Flow] ====Done====
2437 19:23:02.650368
2438 19:23:02.653866 [DutyScan_Calibration_Flow] k_type=2
2439 19:23:02.668809
2440 19:23:02.668934 ==DQ 0 ==
2441 19:23:02.672180 Final DQ duty delay cell = -4
2442 19:23:02.676073 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2443 19:23:02.679426 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2444 19:23:02.682450 [-4] AVG Duty = 4969%(X100)
2445 19:23:02.682534
2446 19:23:02.682613 ==DQ 1 ==
2447 19:23:02.685584 Final DQ duty delay cell = -4
2448 19:23:02.689276 [-4] MAX Duty = 4969%(X100), DQS PI = 54
2449 19:23:02.692511 [-4] MIN Duty = 4876%(X100), DQS PI = 14
2450 19:23:02.695669 [-4] AVG Duty = 4922%(X100)
2451 19:23:02.695752
2452 19:23:02.698967 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2453 19:23:02.699045
2454 19:23:02.702250 CH0 DQ 1 Duty spec in!! Max-Min= 93%
2455 19:23:02.705476 [DutyScan_Calibration_Flow] ====Done====
2456 19:23:02.705561 ==
2457 19:23:02.708833 Dram Type= 6, Freq= 0, CH_1, rank 0
2458 19:23:02.712123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2459 19:23:02.712208 ==
2460 19:23:02.716007 [Duty_Offset_Calibration]
2461 19:23:02.716085 B0:-1 B1:1 CA:1
2462 19:23:02.716148
2463 19:23:02.719032 [DutyScan_Calibration_Flow] k_type=0
2464 19:23:02.729676
2465 19:23:02.729813 ==CLK 0==
2466 19:23:02.733020 Final CLK duty delay cell = 0
2467 19:23:02.736311 [0] MAX Duty = 5156%(X100), DQS PI = 22
2468 19:23:02.739653 [0] MIN Duty = 4969%(X100), DQS PI = 60
2469 19:23:02.742821 [0] AVG Duty = 5062%(X100)
2470 19:23:02.742899
2471 19:23:02.745918 CH1 CLK Duty spec in!! Max-Min= 187%
2472 19:23:02.749655 [DutyScan_Calibration_Flow] ====Done====
2473 19:23:02.749773
2474 19:23:02.752723 [DutyScan_Calibration_Flow] k_type=1
2475 19:23:02.768892
2476 19:23:02.768987 ==DQS 0 ==
2477 19:23:02.772265 Final DQS duty delay cell = 0
2478 19:23:02.775486 [0] MAX Duty = 5125%(X100), DQS PI = 48
2479 19:23:02.778768 [0] MIN Duty = 4907%(X100), DQS PI = 6
2480 19:23:02.778847 [0] AVG Duty = 5016%(X100)
2481 19:23:02.782130
2482 19:23:02.782206 ==DQS 1 ==
2483 19:23:02.785281 Final DQS duty delay cell = 0
2484 19:23:02.788371 [0] MAX Duty = 5062%(X100), DQS PI = 12
2485 19:23:02.792351 [0] MIN Duty = 4969%(X100), DQS PI = 56
2486 19:23:02.795431 [0] AVG Duty = 5015%(X100)
2487 19:23:02.795520
2488 19:23:02.798839 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2489 19:23:02.798926
2490 19:23:02.801601 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2491 19:23:02.804931 [DutyScan_Calibration_Flow] ====Done====
2492 19:23:02.805021
2493 19:23:02.808139 [DutyScan_Calibration_Flow] k_type=3
2494 19:23:02.824835
2495 19:23:02.824927 ==DQM 0 ==
2496 19:23:02.827766 Final DQM duty delay cell = -4
2497 19:23:02.831525 [-4] MAX Duty = 5062%(X100), DQS PI = 36
2498 19:23:02.834626 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2499 19:23:02.838135 [-4] AVG Duty = 4953%(X100)
2500 19:23:02.838238
2501 19:23:02.838305 ==DQM 1 ==
2502 19:23:02.841300 Final DQM duty delay cell = 0
2503 19:23:02.844682 [0] MAX Duty = 5156%(X100), DQS PI = 8
2504 19:23:02.847959 [0] MIN Duty = 4969%(X100), DQS PI = 28
2505 19:23:02.851014 [0] AVG Duty = 5062%(X100)
2506 19:23:02.851100
2507 19:23:02.854253 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2508 19:23:02.854345
2509 19:23:02.858094 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2510 19:23:02.860943 [DutyScan_Calibration_Flow] ====Done====
2511 19:23:02.861021
2512 19:23:02.864162 [DutyScan_Calibration_Flow] k_type=2
2513 19:23:02.881241
2514 19:23:02.881342 ==DQ 0 ==
2515 19:23:02.884544 Final DQ duty delay cell = 0
2516 19:23:02.887806 [0] MAX Duty = 5187%(X100), DQS PI = 30
2517 19:23:02.890957 [0] MIN Duty = 4876%(X100), DQS PI = 8
2518 19:23:02.891040 [0] AVG Duty = 5031%(X100)
2519 19:23:02.894300
2520 19:23:02.894373 ==DQ 1 ==
2521 19:23:02.897964 Final DQ duty delay cell = 0
2522 19:23:02.901133 [0] MAX Duty = 5124%(X100), DQS PI = 10
2523 19:23:02.904411 [0] MIN Duty = 4969%(X100), DQS PI = 0
2524 19:23:02.904488 [0] AVG Duty = 5046%(X100)
2525 19:23:02.904552
2526 19:23:02.910788 CH1 DQ 0 Duty spec in!! Max-Min= 311%
2527 19:23:02.910879
2528 19:23:02.913972 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2529 19:23:02.917773 [DutyScan_Calibration_Flow] ====Done====
2530 19:23:02.921180 nWR fixed to 30
2531 19:23:02.921258 [ModeRegInit_LP4] CH0 RK0
2532 19:23:02.924457 [ModeRegInit_LP4] CH0 RK1
2533 19:23:02.927760 [ModeRegInit_LP4] CH1 RK0
2534 19:23:02.930887 [ModeRegInit_LP4] CH1 RK1
2535 19:23:02.930965 match AC timing 7
2536 19:23:02.934144 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2537 19:23:02.940516 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2538 19:23:02.944063 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2539 19:23:02.950871 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2540 19:23:02.954032 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2541 19:23:02.954110 ==
2542 19:23:02.957167 Dram Type= 6, Freq= 0, CH_0, rank 0
2543 19:23:02.960362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2544 19:23:02.960453 ==
2545 19:23:02.966889 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2546 19:23:02.973564 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2547 19:23:02.981271 [CA 0] Center 39 (9~70) winsize 62
2548 19:23:02.984699 [CA 1] Center 39 (9~69) winsize 61
2549 19:23:02.987514 [CA 2] Center 35 (5~66) winsize 62
2550 19:23:02.991123 [CA 3] Center 35 (5~66) winsize 62
2551 19:23:02.994489 [CA 4] Center 33 (4~63) winsize 60
2552 19:23:02.997352 [CA 5] Center 33 (3~63) winsize 61
2553 19:23:02.997428
2554 19:23:03.000779 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2555 19:23:03.000874
2556 19:23:03.004667 [CATrainingPosCal] consider 1 rank data
2557 19:23:03.007830 u2DelayCellTimex100 = 270/100 ps
2558 19:23:03.010965 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2559 19:23:03.017354 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2560 19:23:03.020654 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2561 19:23:03.023988 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2562 19:23:03.027204 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2563 19:23:03.030527 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2564 19:23:03.030602
2565 19:23:03.033886 CA PerBit enable=1, Macro0, CA PI delay=33
2566 19:23:03.033965
2567 19:23:03.037183 [CBTSetCACLKResult] CA Dly = 33
2568 19:23:03.037259 CS Dly: 8 (0~39)
2569 19:23:03.040545 ==
2570 19:23:03.043706 Dram Type= 6, Freq= 0, CH_0, rank 1
2571 19:23:03.047510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2572 19:23:03.047626 ==
2573 19:23:03.050832 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2574 19:23:03.056961 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2575 19:23:03.067084 [CA 0] Center 39 (9~70) winsize 62
2576 19:23:03.070262 [CA 1] Center 39 (9~70) winsize 62
2577 19:23:03.073521 [CA 2] Center 35 (5~66) winsize 62
2578 19:23:03.076919 [CA 3] Center 34 (4~65) winsize 62
2579 19:23:03.080151 [CA 4] Center 33 (3~64) winsize 62
2580 19:23:03.083497 [CA 5] Center 33 (3~63) winsize 61
2581 19:23:03.083565
2582 19:23:03.086190 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2583 19:23:03.086268
2584 19:23:03.089572 [CATrainingPosCal] consider 2 rank data
2585 19:23:03.093469 u2DelayCellTimex100 = 270/100 ps
2586 19:23:03.096380 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2587 19:23:03.103107 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2588 19:23:03.106556 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2589 19:23:03.109505 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2590 19:23:03.112856 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2591 19:23:03.116176 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2592 19:23:03.116252
2593 19:23:03.119561 CA PerBit enable=1, Macro0, CA PI delay=33
2594 19:23:03.119642
2595 19:23:03.123015 [CBTSetCACLKResult] CA Dly = 33
2596 19:23:03.126672 CS Dly: 8 (0~40)
2597 19:23:03.126750
2598 19:23:03.129989 ----->DramcWriteLeveling(PI) begin...
2599 19:23:03.130066 ==
2600 19:23:03.133316 Dram Type= 6, Freq= 0, CH_0, rank 0
2601 19:23:03.136696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2602 19:23:03.136770 ==
2603 19:23:03.139687 Write leveling (Byte 0): 31 => 31
2604 19:23:03.143072 Write leveling (Byte 1): 29 => 29
2605 19:23:03.146318 DramcWriteLeveling(PI) end<-----
2606 19:23:03.146391
2607 19:23:03.146452 ==
2608 19:23:03.149488 Dram Type= 6, Freq= 0, CH_0, rank 0
2609 19:23:03.152688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2610 19:23:03.152765 ==
2611 19:23:03.156583 [Gating] SW mode calibration
2612 19:23:03.162702 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2613 19:23:03.169666 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2614 19:23:03.172983 0 15 0 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 1)
2615 19:23:03.176217 0 15 4 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
2616 19:23:03.182853 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2617 19:23:03.186188 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2618 19:23:03.189552 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2619 19:23:03.196091 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2620 19:23:03.199237 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2621 19:23:03.202552 0 15 28 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 1)
2622 19:23:03.209554 1 0 0 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
2623 19:23:03.212919 1 0 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
2624 19:23:03.216098 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2625 19:23:03.219162 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2626 19:23:03.226185 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2627 19:23:03.229129 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2628 19:23:03.232534 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2629 19:23:03.239451 1 0 28 | B1->B0 | 2323 3433 | 0 1 | (0 0) (0 0)
2630 19:23:03.242453 1 1 0 | B1->B0 | 2323 4444 | 1 0 | (0 0) (0 0)
2631 19:23:03.246028 1 1 4 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
2632 19:23:03.252545 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2633 19:23:03.255662 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2634 19:23:03.258991 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2635 19:23:03.266003 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2636 19:23:03.269058 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2637 19:23:03.272175 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2638 19:23:03.279330 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2639 19:23:03.282671 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2640 19:23:03.285944 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2641 19:23:03.291898 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2642 19:23:03.295855 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2643 19:23:03.298999 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2644 19:23:03.305489 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2645 19:23:03.308814 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2646 19:23:03.312069 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2647 19:23:03.318306 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2648 19:23:03.322228 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2649 19:23:03.324868 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2650 19:23:03.332076 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2651 19:23:03.335245 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2652 19:23:03.338499 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2653 19:23:03.345075 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2654 19:23:03.348484 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2655 19:23:03.351795 Total UI for P1: 0, mck2ui 16
2656 19:23:03.355216 best dqsien dly found for B0: ( 1, 3, 26)
2657 19:23:03.358696 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2658 19:23:03.361963 Total UI for P1: 0, mck2ui 16
2659 19:23:03.365106 best dqsien dly found for B1: ( 1, 4, 0)
2660 19:23:03.368353 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2661 19:23:03.371511 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2662 19:23:03.371584
2663 19:23:03.375322 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2664 19:23:03.381542 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2665 19:23:03.381622 [Gating] SW calibration Done
2666 19:23:03.381686 ==
2667 19:23:03.384856 Dram Type= 6, Freq= 0, CH_0, rank 0
2668 19:23:03.391635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2669 19:23:03.391711 ==
2670 19:23:03.391780 RX Vref Scan: 0
2671 19:23:03.391840
2672 19:23:03.394889 RX Vref 0 -> 0, step: 1
2673 19:23:03.394957
2674 19:23:03.398198 RX Delay -40 -> 252, step: 8
2675 19:23:03.401509 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2676 19:23:03.404776 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2677 19:23:03.408668 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2678 19:23:03.415297 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2679 19:23:03.418478 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2680 19:23:03.421603 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2681 19:23:03.424833 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2682 19:23:03.428138 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2683 19:23:03.431959 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2684 19:23:03.438519 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2685 19:23:03.441761 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2686 19:23:03.445103 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2687 19:23:03.448429 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2688 19:23:03.454731 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2689 19:23:03.458189 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2690 19:23:03.461229 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2691 19:23:03.461303 ==
2692 19:23:03.464608 Dram Type= 6, Freq= 0, CH_0, rank 0
2693 19:23:03.468003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2694 19:23:03.468089 ==
2695 19:23:03.471723 DQS Delay:
2696 19:23:03.471800 DQS0 = 0, DQS1 = 0
2697 19:23:03.474630 DQM Delay:
2698 19:23:03.474699 DQM0 = 119, DQM1 = 106
2699 19:23:03.474760 DQ Delay:
2700 19:23:03.478298 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2701 19:23:03.484481 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =123
2702 19:23:03.487804 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2703 19:23:03.491180 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2704 19:23:03.491263
2705 19:23:03.491328
2706 19:23:03.491388 ==
2707 19:23:03.494805 Dram Type= 6, Freq= 0, CH_0, rank 0
2708 19:23:03.498108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2709 19:23:03.498191 ==
2710 19:23:03.498256
2711 19:23:03.498317
2712 19:23:03.501299 TX Vref Scan disable
2713 19:23:03.504662 == TX Byte 0 ==
2714 19:23:03.508140 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2715 19:23:03.511278 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2716 19:23:03.514595 == TX Byte 1 ==
2717 19:23:03.518011 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2718 19:23:03.521145 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2719 19:23:03.521229 ==
2720 19:23:03.524366 Dram Type= 6, Freq= 0, CH_0, rank 0
2721 19:23:03.531096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2722 19:23:03.531181 ==
2723 19:23:03.541411 TX Vref=22, minBit 1, minWin=25, winSum=415
2724 19:23:03.544636 TX Vref=24, minBit 1, minWin=26, winSum=424
2725 19:23:03.547959 TX Vref=26, minBit 13, minWin=25, winSum=425
2726 19:23:03.551375 TX Vref=28, minBit 5, minWin=26, winSum=429
2727 19:23:03.554564 TX Vref=30, minBit 1, minWin=26, winSum=432
2728 19:23:03.561056 TX Vref=32, minBit 1, minWin=26, winSum=429
2729 19:23:03.564111 [TxChooseVref] Worse bit 1, Min win 26, Win sum 432, Final Vref 30
2730 19:23:03.564195
2731 19:23:03.567379 Final TX Range 1 Vref 30
2732 19:23:03.567461
2733 19:23:03.567554 ==
2734 19:23:03.570512 Dram Type= 6, Freq= 0, CH_0, rank 0
2735 19:23:03.574462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2736 19:23:03.577873 ==
2737 19:23:03.577955
2738 19:23:03.578018
2739 19:23:03.578077 TX Vref Scan disable
2740 19:23:03.581182 == TX Byte 0 ==
2741 19:23:03.584333 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2742 19:23:03.590645 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2743 19:23:03.590727 == TX Byte 1 ==
2744 19:23:03.594174 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2745 19:23:03.601005 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2746 19:23:03.601087
2747 19:23:03.601203 [DATLAT]
2748 19:23:03.601264 Freq=1200, CH0 RK0
2749 19:23:03.601324
2750 19:23:03.604461 DATLAT Default: 0xd
2751 19:23:03.604542 0, 0xFFFF, sum = 0
2752 19:23:03.607537 1, 0xFFFF, sum = 0
2753 19:23:03.610540 2, 0xFFFF, sum = 0
2754 19:23:03.610622 3, 0xFFFF, sum = 0
2755 19:23:03.613764 4, 0xFFFF, sum = 0
2756 19:23:03.613855 5, 0xFFFF, sum = 0
2757 19:23:03.617684 6, 0xFFFF, sum = 0
2758 19:23:03.617813 7, 0xFFFF, sum = 0
2759 19:23:03.620706 8, 0xFFFF, sum = 0
2760 19:23:03.620781 9, 0xFFFF, sum = 0
2761 19:23:03.623869 10, 0xFFFF, sum = 0
2762 19:23:03.623944 11, 0xFFFF, sum = 0
2763 19:23:03.627036 12, 0x0, sum = 1
2764 19:23:03.627110 13, 0x0, sum = 2
2765 19:23:03.630764 14, 0x0, sum = 3
2766 19:23:03.630839 15, 0x0, sum = 4
2767 19:23:03.634071 best_step = 13
2768 19:23:03.634141
2769 19:23:03.634200 ==
2770 19:23:03.637442 Dram Type= 6, Freq= 0, CH_0, rank 0
2771 19:23:03.640586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2772 19:23:03.640660 ==
2773 19:23:03.640726 RX Vref Scan: 1
2774 19:23:03.643861
2775 19:23:03.643929 Set Vref Range= 32 -> 127
2776 19:23:03.643988
2777 19:23:03.647345 RX Vref 32 -> 127, step: 1
2778 19:23:03.647413
2779 19:23:03.650580 RX Delay -21 -> 252, step: 4
2780 19:23:03.650657
2781 19:23:03.653939 Set Vref, RX VrefLevel [Byte0]: 32
2782 19:23:03.657178 [Byte1]: 32
2783 19:23:03.657270
2784 19:23:03.660539 Set Vref, RX VrefLevel [Byte0]: 33
2785 19:23:03.663688 [Byte1]: 33
2786 19:23:03.667587
2787 19:23:03.667658 Set Vref, RX VrefLevel [Byte0]: 34
2788 19:23:03.670589 [Byte1]: 34
2789 19:23:03.675734
2790 19:23:03.675810 Set Vref, RX VrefLevel [Byte0]: 35
2791 19:23:03.678313 [Byte1]: 35
2792 19:23:03.683060
2793 19:23:03.683133 Set Vref, RX VrefLevel [Byte0]: 36
2794 19:23:03.686409 [Byte1]: 36
2795 19:23:03.691037
2796 19:23:03.691112 Set Vref, RX VrefLevel [Byte0]: 37
2797 19:23:03.694258 [Byte1]: 37
2798 19:23:03.698957
2799 19:23:03.699060 Set Vref, RX VrefLevel [Byte0]: 38
2800 19:23:03.702150 [Byte1]: 38
2801 19:23:03.706829
2802 19:23:03.706930 Set Vref, RX VrefLevel [Byte0]: 39
2803 19:23:03.710759 [Byte1]: 39
2804 19:23:03.715248
2805 19:23:03.715343 Set Vref, RX VrefLevel [Byte0]: 40
2806 19:23:03.718238 [Byte1]: 40
2807 19:23:03.722783
2808 19:23:03.722865 Set Vref, RX VrefLevel [Byte0]: 41
2809 19:23:03.726015 [Byte1]: 41
2810 19:23:03.730837
2811 19:23:03.730950 Set Vref, RX VrefLevel [Byte0]: 42
2812 19:23:03.734265 [Byte1]: 42
2813 19:23:03.738560
2814 19:23:03.738654 Set Vref, RX VrefLevel [Byte0]: 43
2815 19:23:03.742299 [Byte1]: 43
2816 19:23:03.746329
2817 19:23:03.750074 Set Vref, RX VrefLevel [Byte0]: 44
2818 19:23:03.753444 [Byte1]: 44
2819 19:23:03.753519
2820 19:23:03.756644 Set Vref, RX VrefLevel [Byte0]: 45
2821 19:23:03.759902 [Byte1]: 45
2822 19:23:03.759985
2823 19:23:03.763113 Set Vref, RX VrefLevel [Byte0]: 46
2824 19:23:03.766359 [Byte1]: 46
2825 19:23:03.770374
2826 19:23:03.770479 Set Vref, RX VrefLevel [Byte0]: 47
2827 19:23:03.773596 [Byte1]: 47
2828 19:23:03.778592
2829 19:23:03.778671 Set Vref, RX VrefLevel [Byte0]: 48
2830 19:23:03.781685 [Byte1]: 48
2831 19:23:03.786170
2832 19:23:03.786273 Set Vref, RX VrefLevel [Byte0]: 49
2833 19:23:03.789522 [Byte1]: 49
2834 19:23:03.794164
2835 19:23:03.794239 Set Vref, RX VrefLevel [Byte0]: 50
2836 19:23:03.797470 [Byte1]: 50
2837 19:23:03.802203
2838 19:23:03.802389 Set Vref, RX VrefLevel [Byte0]: 51
2839 19:23:03.805230 [Byte1]: 51
2840 19:23:03.809765
2841 19:23:03.809846 Set Vref, RX VrefLevel [Byte0]: 52
2842 19:23:03.813013 [Byte1]: 52
2843 19:23:03.818182
2844 19:23:03.818265 Set Vref, RX VrefLevel [Byte0]: 53
2845 19:23:03.821541 [Byte1]: 53
2846 19:23:03.826147
2847 19:23:03.826227 Set Vref, RX VrefLevel [Byte0]: 54
2848 19:23:03.829355 [Byte1]: 54
2849 19:23:03.833883
2850 19:23:03.833965 Set Vref, RX VrefLevel [Byte0]: 55
2851 19:23:03.837014 [Byte1]: 55
2852 19:23:03.842159
2853 19:23:03.842234 Set Vref, RX VrefLevel [Byte0]: 56
2854 19:23:03.845198 [Byte1]: 56
2855 19:23:03.849757
2856 19:23:03.849832 Set Vref, RX VrefLevel [Byte0]: 57
2857 19:23:03.853026 [Byte1]: 57
2858 19:23:03.857651
2859 19:23:03.857726 Set Vref, RX VrefLevel [Byte0]: 58
2860 19:23:03.860999 [Byte1]: 58
2861 19:23:03.865266
2862 19:23:03.865403 Set Vref, RX VrefLevel [Byte0]: 59
2863 19:23:03.869005 [Byte1]: 59
2864 19:23:03.873581
2865 19:23:03.873652 Set Vref, RX VrefLevel [Byte0]: 60
2866 19:23:03.876897 [Byte1]: 60
2867 19:23:03.881341
2868 19:23:03.881414 Set Vref, RX VrefLevel [Byte0]: 61
2869 19:23:03.884432 [Byte1]: 61
2870 19:23:03.889024
2871 19:23:03.889104 Set Vref, RX VrefLevel [Byte0]: 62
2872 19:23:03.892423 [Byte1]: 62
2873 19:23:03.897067
2874 19:23:03.897144 Set Vref, RX VrefLevel [Byte0]: 63
2875 19:23:03.900316 [Byte1]: 63
2876 19:23:03.905505
2877 19:23:03.905580 Set Vref, RX VrefLevel [Byte0]: 64
2878 19:23:03.908759 [Byte1]: 64
2879 19:23:03.913305
2880 19:23:03.913407 Set Vref, RX VrefLevel [Byte0]: 65
2881 19:23:03.916734 [Byte1]: 65
2882 19:23:03.921288
2883 19:23:03.921409 Set Vref, RX VrefLevel [Byte0]: 66
2884 19:23:03.924637 [Byte1]: 66
2885 19:23:03.928655
2886 19:23:03.928729 Set Vref, RX VrefLevel [Byte0]: 67
2887 19:23:03.932091 [Byte1]: 67
2888 19:23:03.937046
2889 19:23:03.937166 Set Vref, RX VrefLevel [Byte0]: 68
2890 19:23:03.940282 [Byte1]: 68
2891 19:23:03.944753
2892 19:23:03.944854 Set Vref, RX VrefLevel [Byte0]: 69
2893 19:23:03.948062 [Byte1]: 69
2894 19:23:03.952592
2895 19:23:03.952755 Set Vref, RX VrefLevel [Byte0]: 70
2896 19:23:03.955918 [Byte1]: 70
2897 19:23:03.960929
2898 19:23:03.961027 Set Vref, RX VrefLevel [Byte0]: 71
2899 19:23:03.963818 [Byte1]: 71
2900 19:23:03.968765
2901 19:23:03.968842 Set Vref, RX VrefLevel [Byte0]: 72
2902 19:23:03.971655 [Byte1]: 72
2903 19:23:03.976591
2904 19:23:03.976701 Set Vref, RX VrefLevel [Byte0]: 73
2905 19:23:03.979669 [Byte1]: 73
2906 19:23:03.984140
2907 19:23:03.984239 Set Vref, RX VrefLevel [Byte0]: 74
2908 19:23:03.988121 [Byte1]: 74
2909 19:23:03.992618
2910 19:23:03.992720 Set Vref, RX VrefLevel [Byte0]: 75
2911 19:23:03.995601 [Byte1]: 75
2912 19:23:04.000098
2913 19:23:04.000194 Final RX Vref Byte 0 = 59 to rank0
2914 19:23:04.003357 Final RX Vref Byte 1 = 49 to rank0
2915 19:23:04.006661 Final RX Vref Byte 0 = 59 to rank1
2916 19:23:04.009890 Final RX Vref Byte 1 = 49 to rank1==
2917 19:23:04.013202 Dram Type= 6, Freq= 0, CH_0, rank 0
2918 19:23:04.020376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2919 19:23:04.020457 ==
2920 19:23:04.020530 DQS Delay:
2921 19:23:04.023033 DQS0 = 0, DQS1 = 0
2922 19:23:04.023139 DQM Delay:
2923 19:23:04.023227 DQM0 = 118, DQM1 = 106
2924 19:23:04.026786 DQ Delay:
2925 19:23:04.030076 DQ0 =116, DQ1 =120, DQ2 =114, DQ3 =114
2926 19:23:04.033307 DQ4 =120, DQ5 =112, DQ6 =126, DQ7 =126
2927 19:23:04.036768 DQ8 =96, DQ9 =92, DQ10 =110, DQ11 =100
2928 19:23:04.039818 DQ12 =110, DQ13 =108, DQ14 =118, DQ15 =116
2929 19:23:04.039897
2930 19:23:04.039966
2931 19:23:04.049811 [DQSOSCAuto] RK0, (LSB)MR18= 0xdf9, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 405 ps
2932 19:23:04.049891 CH0 RK0: MR19=403, MR18=DF9
2933 19:23:04.056243 CH0_RK0: MR19=0x403, MR18=0xDF9, DQSOSC=405, MR23=63, INC=39, DEC=26
2934 19:23:04.056339
2935 19:23:04.059577 ----->DramcWriteLeveling(PI) begin...
2936 19:23:04.059694 ==
2937 19:23:04.062765 Dram Type= 6, Freq= 0, CH_0, rank 1
2938 19:23:04.069705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2939 19:23:04.069786 ==
2940 19:23:04.073006 Write leveling (Byte 0): 32 => 32
2941 19:23:04.073090 Write leveling (Byte 1): 30 => 30
2942 19:23:04.076302 DramcWriteLeveling(PI) end<-----
2943 19:23:04.076410
2944 19:23:04.079501 ==
2945 19:23:04.082600 Dram Type= 6, Freq= 0, CH_0, rank 1
2946 19:23:04.086215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2947 19:23:04.086286 ==
2948 19:23:04.089222 [Gating] SW mode calibration
2949 19:23:04.095987 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2950 19:23:04.099156 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2951 19:23:04.105802 0 15 0 | B1->B0 | 2323 3131 | 0 1 | (0 0) (0 0)
2952 19:23:04.109156 0 15 4 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
2953 19:23:04.112611 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2954 19:23:04.119366 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2955 19:23:04.122567 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2956 19:23:04.125992 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2957 19:23:04.132296 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2958 19:23:04.135827 0 15 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2959 19:23:04.138998 1 0 0 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
2960 19:23:04.145440 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2961 19:23:04.148625 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2962 19:23:04.152030 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2963 19:23:04.158738 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2964 19:23:04.162259 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2965 19:23:04.165498 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2966 19:23:04.172012 1 0 28 | B1->B0 | 2423 3434 | 1 0 | (0 0) (1 1)
2967 19:23:04.174965 1 1 0 | B1->B0 | 3232 4545 | 0 0 | (0 0) (0 0)
2968 19:23:04.178313 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2969 19:23:04.184845 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2970 19:23:04.188867 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2971 19:23:04.191940 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2972 19:23:04.198347 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2973 19:23:04.201916 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2974 19:23:04.205105 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2975 19:23:04.211458 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2976 19:23:04.215064 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2977 19:23:04.217917 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2978 19:23:04.224957 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2979 19:23:04.228200 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2980 19:23:04.231610 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2981 19:23:04.237952 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2982 19:23:04.241228 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2983 19:23:04.244525 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2984 19:23:04.251105 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2985 19:23:04.254321 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2986 19:23:04.257793 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2987 19:23:04.261067 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2988 19:23:04.267839 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2989 19:23:04.271226 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2990 19:23:04.274771 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2991 19:23:04.281365 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2992 19:23:04.284683 Total UI for P1: 0, mck2ui 16
2993 19:23:04.287937 best dqsien dly found for B0: ( 1, 3, 28)
2994 19:23:04.291322 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2995 19:23:04.294589 Total UI for P1: 0, mck2ui 16
2996 19:23:04.297900 best dqsien dly found for B1: ( 1, 4, 0)
2997 19:23:04.301121 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2998 19:23:04.304382 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2999 19:23:04.304498
3000 19:23:04.307444 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3001 19:23:04.310951 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
3002 19:23:04.314583 [Gating] SW calibration Done
3003 19:23:04.314699 ==
3004 19:23:04.317744 Dram Type= 6, Freq= 0, CH_0, rank 1
3005 19:23:04.324159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3006 19:23:04.324286 ==
3007 19:23:04.324410 RX Vref Scan: 0
3008 19:23:04.324531
3009 19:23:04.327422 RX Vref 0 -> 0, step: 1
3010 19:23:04.327513
3011 19:23:04.330981 RX Delay -40 -> 252, step: 8
3012 19:23:04.334239 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
3013 19:23:04.337535 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
3014 19:23:04.340931 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
3015 19:23:04.346948 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3016 19:23:04.350229 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3017 19:23:04.353470 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
3018 19:23:04.356823 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3019 19:23:04.360147 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
3020 19:23:04.363579 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3021 19:23:04.370426 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3022 19:23:04.373741 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3023 19:23:04.376804 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3024 19:23:04.380592 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3025 19:23:04.387016 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3026 19:23:04.390001 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3027 19:23:04.393232 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3028 19:23:04.393345 ==
3029 19:23:04.397254 Dram Type= 6, Freq= 0, CH_0, rank 1
3030 19:23:04.400619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3031 19:23:04.400724 ==
3032 19:23:04.403880 DQS Delay:
3033 19:23:04.403982 DQS0 = 0, DQS1 = 0
3034 19:23:04.406527 DQM Delay:
3035 19:23:04.406611 DQM0 = 116, DQM1 = 108
3036 19:23:04.406674 DQ Delay:
3037 19:23:04.413644 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =115
3038 19:23:04.416891 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =123
3039 19:23:04.419862 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
3040 19:23:04.423556 DQ12 =111, DQ13 =119, DQ14 =119, DQ15 =111
3041 19:23:04.423658
3042 19:23:04.423756
3043 19:23:04.423848 ==
3044 19:23:04.426861 Dram Type= 6, Freq= 0, CH_0, rank 1
3045 19:23:04.430062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3046 19:23:04.430156 ==
3047 19:23:04.430246
3048 19:23:04.430308
3049 19:23:04.433189 TX Vref Scan disable
3050 19:23:04.436751 == TX Byte 0 ==
3051 19:23:04.439637 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3052 19:23:04.443441 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3053 19:23:04.446712 == TX Byte 1 ==
3054 19:23:04.449508 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3055 19:23:04.452798 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3056 19:23:04.452878 ==
3057 19:23:04.456438 Dram Type= 6, Freq= 0, CH_0, rank 1
3058 19:23:04.459627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3059 19:23:04.462884 ==
3060 19:23:04.473545 TX Vref=22, minBit 0, minWin=26, winSum=423
3061 19:23:04.476916 TX Vref=24, minBit 0, minWin=26, winSum=427
3062 19:23:04.479555 TX Vref=26, minBit 1, minWin=26, winSum=427
3063 19:23:04.482932 TX Vref=28, minBit 1, minWin=26, winSum=433
3064 19:23:04.486755 TX Vref=30, minBit 13, minWin=26, winSum=434
3065 19:23:04.493558 TX Vref=32, minBit 10, minWin=26, winSum=436
3066 19:23:04.496301 [TxChooseVref] Worse bit 10, Min win 26, Win sum 436, Final Vref 32
3067 19:23:04.496384
3068 19:23:04.499776 Final TX Range 1 Vref 32
3069 19:23:04.499857
3070 19:23:04.499921 ==
3071 19:23:04.503536 Dram Type= 6, Freq= 0, CH_0, rank 1
3072 19:23:04.509518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3073 19:23:04.509599 ==
3074 19:23:04.509662
3075 19:23:04.509721
3076 19:23:04.509777 TX Vref Scan disable
3077 19:23:04.513470 == TX Byte 0 ==
3078 19:23:04.516830 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3079 19:23:04.523311 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3080 19:23:04.523392 == TX Byte 1 ==
3081 19:23:04.526662 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3082 19:23:04.533625 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3083 19:23:04.533706
3084 19:23:04.533770 [DATLAT]
3085 19:23:04.533828 Freq=1200, CH0 RK1
3086 19:23:04.533907
3087 19:23:04.536199 DATLAT Default: 0xd
3088 19:23:04.539486 0, 0xFFFF, sum = 0
3089 19:23:04.539568 1, 0xFFFF, sum = 0
3090 19:23:04.543458 2, 0xFFFF, sum = 0
3091 19:23:04.543540 3, 0xFFFF, sum = 0
3092 19:23:04.546066 4, 0xFFFF, sum = 0
3093 19:23:04.546186 5, 0xFFFF, sum = 0
3094 19:23:04.550038 6, 0xFFFF, sum = 0
3095 19:23:04.550120 7, 0xFFFF, sum = 0
3096 19:23:04.553005 8, 0xFFFF, sum = 0
3097 19:23:04.553088 9, 0xFFFF, sum = 0
3098 19:23:04.556438 10, 0xFFFF, sum = 0
3099 19:23:04.556520 11, 0xFFFF, sum = 0
3100 19:23:04.559899 12, 0x0, sum = 1
3101 19:23:04.559980 13, 0x0, sum = 2
3102 19:23:04.563105 14, 0x0, sum = 3
3103 19:23:04.563203 15, 0x0, sum = 4
3104 19:23:04.566192 best_step = 13
3105 19:23:04.566271
3106 19:23:04.566366 ==
3107 19:23:04.569492 Dram Type= 6, Freq= 0, CH_0, rank 1
3108 19:23:04.572998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3109 19:23:04.573079 ==
3110 19:23:04.573158 RX Vref Scan: 0
3111 19:23:04.576419
3112 19:23:04.576499 RX Vref 0 -> 0, step: 1
3113 19:23:04.576562
3114 19:23:04.579337 RX Delay -21 -> 252, step: 4
3115 19:23:04.586136 iDelay=199, Bit 0, Center 112 (47 ~ 178) 132
3116 19:23:04.589348 iDelay=199, Bit 1, Center 118 (47 ~ 190) 144
3117 19:23:04.592748 iDelay=199, Bit 2, Center 110 (43 ~ 178) 136
3118 19:23:04.596062 iDelay=199, Bit 3, Center 114 (43 ~ 186) 144
3119 19:23:04.599189 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3120 19:23:04.606014 iDelay=199, Bit 5, Center 110 (43 ~ 178) 136
3121 19:23:04.609472 iDelay=199, Bit 6, Center 126 (55 ~ 198) 144
3122 19:23:04.612908 iDelay=199, Bit 7, Center 124 (55 ~ 194) 140
3123 19:23:04.616085 iDelay=199, Bit 8, Center 96 (27 ~ 166) 140
3124 19:23:04.619476 iDelay=199, Bit 9, Center 94 (27 ~ 162) 136
3125 19:23:04.622634 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3126 19:23:04.629161 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3127 19:23:04.632926 iDelay=199, Bit 12, Center 112 (47 ~ 178) 132
3128 19:23:04.636187 iDelay=199, Bit 13, Center 114 (47 ~ 182) 136
3129 19:23:04.639360 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
3130 19:23:04.645914 iDelay=199, Bit 15, Center 116 (51 ~ 182) 132
3131 19:23:04.646012 ==
3132 19:23:04.649099 Dram Type= 6, Freq= 0, CH_0, rank 1
3133 19:23:04.652386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3134 19:23:04.652480 ==
3135 19:23:04.652567 DQS Delay:
3136 19:23:04.655669 DQS0 = 0, DQS1 = 0
3137 19:23:04.655752 DQM Delay:
3138 19:23:04.658932 DQM0 = 116, DQM1 = 107
3139 19:23:04.659013 DQ Delay:
3140 19:23:04.662230 DQ0 =112, DQ1 =118, DQ2 =110, DQ3 =114
3141 19:23:04.665699 DQ4 =116, DQ5 =110, DQ6 =126, DQ7 =124
3142 19:23:04.668856 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =100
3143 19:23:04.672326 DQ12 =112, DQ13 =114, DQ14 =118, DQ15 =116
3144 19:23:04.672424
3145 19:23:04.672512
3146 19:23:04.681743 [DQSOSCAuto] RK1, (LSB)MR18= 0xae4, (MSB)MR19= 0x403, tDQSOscB0 = 421 ps tDQSOscB1 = 406 ps
3147 19:23:04.685079 CH0 RK1: MR19=403, MR18=AE4
3148 19:23:04.691778 CH0_RK1: MR19=0x403, MR18=0xAE4, DQSOSC=406, MR23=63, INC=39, DEC=26
3149 19:23:04.691896 [RxdqsGatingPostProcess] freq 1200
3150 19:23:04.698701 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3151 19:23:04.701948 best DQS0 dly(2T, 0.5T) = (0, 11)
3152 19:23:04.705232 best DQS1 dly(2T, 0.5T) = (0, 12)
3153 19:23:04.708740 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3154 19:23:04.711895 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3155 19:23:04.715128 best DQS0 dly(2T, 0.5T) = (0, 11)
3156 19:23:04.718142 best DQS1 dly(2T, 0.5T) = (0, 12)
3157 19:23:04.721531 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3158 19:23:04.725021 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3159 19:23:04.728114 Pre-setting of DQS Precalculation
3160 19:23:04.731845 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3161 19:23:04.731941 ==
3162 19:23:04.735172 Dram Type= 6, Freq= 0, CH_1, rank 0
3163 19:23:04.738364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3164 19:23:04.738446 ==
3165 19:23:04.744678 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3166 19:23:04.751232 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3167 19:23:04.759765 [CA 0] Center 37 (7~68) winsize 62
3168 19:23:04.763186 [CA 1] Center 38 (8~68) winsize 61
3169 19:23:04.766351 [CA 2] Center 34 (4~64) winsize 61
3170 19:23:04.769666 [CA 3] Center 33 (3~64) winsize 62
3171 19:23:04.772816 [CA 4] Center 34 (4~64) winsize 61
3172 19:23:04.776079 [CA 5] Center 33 (3~64) winsize 62
3173 19:23:04.776160
3174 19:23:04.779244 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3175 19:23:04.779325
3176 19:23:04.782427 [CATrainingPosCal] consider 1 rank data
3177 19:23:04.785559 u2DelayCellTimex100 = 270/100 ps
3178 19:23:04.788909 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3179 19:23:04.795840 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3180 19:23:04.798838 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3181 19:23:04.802416 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3182 19:23:04.805823 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3183 19:23:04.808903 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3184 19:23:04.809002
3185 19:23:04.812753 CA PerBit enable=1, Macro0, CA PI delay=33
3186 19:23:04.812860
3187 19:23:04.815899 [CBTSetCACLKResult] CA Dly = 33
3188 19:23:04.819132 CS Dly: 6 (0~37)
3189 19:23:04.819209 ==
3190 19:23:04.822364 Dram Type= 6, Freq= 0, CH_1, rank 1
3191 19:23:04.825546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3192 19:23:04.825651 ==
3193 19:23:04.832148 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3194 19:23:04.835498 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3195 19:23:04.844795 [CA 0] Center 37 (7~68) winsize 62
3196 19:23:04.848096 [CA 1] Center 38 (8~68) winsize 61
3197 19:23:04.851856 [CA 2] Center 34 (4~65) winsize 62
3198 19:23:04.855104 [CA 3] Center 33 (3~64) winsize 62
3199 19:23:04.858368 [CA 4] Center 34 (4~65) winsize 62
3200 19:23:04.861618 [CA 5] Center 33 (3~64) winsize 62
3201 19:23:04.861693
3202 19:23:04.864935 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3203 19:23:04.865035
3204 19:23:04.868299 [CATrainingPosCal] consider 2 rank data
3205 19:23:04.871610 u2DelayCellTimex100 = 270/100 ps
3206 19:23:04.874783 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3207 19:23:04.881510 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3208 19:23:04.884669 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3209 19:23:04.887742 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3210 19:23:04.891123 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3211 19:23:04.894400 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3212 19:23:04.894529
3213 19:23:04.898421 CA PerBit enable=1, Macro0, CA PI delay=33
3214 19:23:04.898497
3215 19:23:04.901048 [CBTSetCACLKResult] CA Dly = 33
3216 19:23:04.901148 CS Dly: 7 (0~40)
3217 19:23:04.904427
3218 19:23:04.908303 ----->DramcWriteLeveling(PI) begin...
3219 19:23:04.908376 ==
3220 19:23:04.911365 Dram Type= 6, Freq= 0, CH_1, rank 0
3221 19:23:04.914529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3222 19:23:04.914627 ==
3223 19:23:04.917950 Write leveling (Byte 0): 24 => 24
3224 19:23:04.920899 Write leveling (Byte 1): 27 => 27
3225 19:23:04.924519 DramcWriteLeveling(PI) end<-----
3226 19:23:04.924626
3227 19:23:04.924722 ==
3228 19:23:04.927802 Dram Type= 6, Freq= 0, CH_1, rank 0
3229 19:23:04.930958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3230 19:23:04.931049 ==
3231 19:23:04.934252 [Gating] SW mode calibration
3232 19:23:04.941295 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3233 19:23:04.947992 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3234 19:23:04.950681 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3235 19:23:04.954220 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3236 19:23:04.961080 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3237 19:23:04.964372 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3238 19:23:04.967535 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3239 19:23:04.974235 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3240 19:23:04.977524 0 15 24 | B1->B0 | 3434 2f2f | 1 1 | (0 0) (1 0)
3241 19:23:04.980798 0 15 28 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
3242 19:23:04.987483 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3243 19:23:04.990682 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3244 19:23:04.994115 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3245 19:23:05.000599 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3246 19:23:05.004025 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3247 19:23:05.007259 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3248 19:23:05.013848 1 0 24 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
3249 19:23:05.016907 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3250 19:23:05.020270 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3251 19:23:05.027194 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3252 19:23:05.030371 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3253 19:23:05.033726 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3254 19:23:05.040499 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3255 19:23:05.043690 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3256 19:23:05.046993 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3257 19:23:05.050161 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3258 19:23:05.056971 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3259 19:23:05.060164 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3260 19:23:05.063596 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3261 19:23:05.070347 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3262 19:23:05.073361 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3263 19:23:05.076589 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3264 19:23:05.083787 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3265 19:23:05.087097 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3266 19:23:05.090313 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3267 19:23:05.096581 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3268 19:23:05.100476 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3269 19:23:05.103594 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3270 19:23:05.110194 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3271 19:23:05.113538 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3272 19:23:05.116854 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3273 19:23:05.123258 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3274 19:23:05.126596 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3275 19:23:05.129910 Total UI for P1: 0, mck2ui 16
3276 19:23:05.133193 best dqsien dly found for B0: ( 1, 3, 28)
3277 19:23:05.136634 Total UI for P1: 0, mck2ui 16
3278 19:23:05.139642 best dqsien dly found for B1: ( 1, 3, 28)
3279 19:23:05.142833 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3280 19:23:05.146280 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3281 19:23:05.146360
3282 19:23:05.149144 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3283 19:23:05.156047 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3284 19:23:05.156126 [Gating] SW calibration Done
3285 19:23:05.156194 ==
3286 19:23:05.159301 Dram Type= 6, Freq= 0, CH_1, rank 0
3287 19:23:05.165913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3288 19:23:05.165990 ==
3289 19:23:05.166053 RX Vref Scan: 0
3290 19:23:05.166111
3291 19:23:05.169181 RX Vref 0 -> 0, step: 1
3292 19:23:05.169279
3293 19:23:05.172541 RX Delay -40 -> 252, step: 8
3294 19:23:05.175533 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3295 19:23:05.178944 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3296 19:23:05.182238 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3297 19:23:05.189073 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3298 19:23:05.192240 iDelay=208, Bit 4, Center 111 (40 ~ 183) 144
3299 19:23:05.195514 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3300 19:23:05.198928 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3301 19:23:05.202254 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3302 19:23:05.208514 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3303 19:23:05.211825 iDelay=208, Bit 9, Center 103 (32 ~ 175) 144
3304 19:23:05.214981 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3305 19:23:05.218429 iDelay=208, Bit 11, Center 95 (24 ~ 167) 144
3306 19:23:05.225375 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3307 19:23:05.228513 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3308 19:23:05.231769 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3309 19:23:05.235151 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3310 19:23:05.235220 ==
3311 19:23:05.238557 Dram Type= 6, Freq= 0, CH_1, rank 0
3312 19:23:05.241782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3313 19:23:05.245100 ==
3314 19:23:05.245170 DQS Delay:
3315 19:23:05.245229 DQS0 = 0, DQS1 = 0
3316 19:23:05.248300 DQM Delay:
3317 19:23:05.248369 DQM0 = 117, DQM1 = 109
3318 19:23:05.251574 DQ Delay:
3319 19:23:05.254621 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =115
3320 19:23:05.258324 DQ4 =111, DQ5 =131, DQ6 =123, DQ7 =115
3321 19:23:05.261832 DQ8 =95, DQ9 =103, DQ10 =111, DQ11 =95
3322 19:23:05.264861 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =119
3323 19:23:05.264934
3324 19:23:05.264994
3325 19:23:05.265056 ==
3326 19:23:05.267865 Dram Type= 6, Freq= 0, CH_1, rank 0
3327 19:23:05.271777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3328 19:23:05.271855 ==
3329 19:23:05.271916
3330 19:23:05.274532
3331 19:23:05.274596 TX Vref Scan disable
3332 19:23:05.277790 == TX Byte 0 ==
3333 19:23:05.281287 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3334 19:23:05.284449 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3335 19:23:05.288257 == TX Byte 1 ==
3336 19:23:05.291135 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3337 19:23:05.294568 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3338 19:23:05.294636 ==
3339 19:23:05.297559 Dram Type= 6, Freq= 0, CH_1, rank 0
3340 19:23:05.304133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3341 19:23:05.304208 ==
3342 19:23:05.314977 TX Vref=22, minBit 10, minWin=24, winSum=417
3343 19:23:05.318260 TX Vref=24, minBit 9, minWin=25, winSum=424
3344 19:23:05.321591 TX Vref=26, minBit 9, minWin=25, winSum=428
3345 19:23:05.324724 TX Vref=28, minBit 9, minWin=25, winSum=430
3346 19:23:05.328576 TX Vref=30, minBit 9, minWin=25, winSum=432
3347 19:23:05.334458 TX Vref=32, minBit 8, minWin=25, winSum=423
3348 19:23:05.337683 [TxChooseVref] Worse bit 9, Min win 25, Win sum 432, Final Vref 30
3349 19:23:05.337752
3350 19:23:05.341163 Final TX Range 1 Vref 30
3351 19:23:05.341235
3352 19:23:05.341302 ==
3353 19:23:05.344302 Dram Type= 6, Freq= 0, CH_1, rank 0
3354 19:23:05.348435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3355 19:23:05.351614 ==
3356 19:23:05.351690
3357 19:23:05.351752
3358 19:23:05.351809 TX Vref Scan disable
3359 19:23:05.354978 == TX Byte 0 ==
3360 19:23:05.358159 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3361 19:23:05.364543 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3362 19:23:05.364631 == TX Byte 1 ==
3363 19:23:05.367713 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3364 19:23:05.374521 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3365 19:23:05.374595
3366 19:23:05.374654 [DATLAT]
3367 19:23:05.374711 Freq=1200, CH1 RK0
3368 19:23:05.374766
3369 19:23:05.378063 DATLAT Default: 0xd
3370 19:23:05.381020 0, 0xFFFF, sum = 0
3371 19:23:05.381107 1, 0xFFFF, sum = 0
3372 19:23:05.384313 2, 0xFFFF, sum = 0
3373 19:23:05.384380 3, 0xFFFF, sum = 0
3374 19:23:05.387661 4, 0xFFFF, sum = 0
3375 19:23:05.387730 5, 0xFFFF, sum = 0
3376 19:23:05.391053 6, 0xFFFF, sum = 0
3377 19:23:05.391122 7, 0xFFFF, sum = 0
3378 19:23:05.394901 8, 0xFFFF, sum = 0
3379 19:23:05.394967 9, 0xFFFF, sum = 0
3380 19:23:05.397965 10, 0xFFFF, sum = 0
3381 19:23:05.398029 11, 0xFFFF, sum = 0
3382 19:23:05.400845 12, 0x0, sum = 1
3383 19:23:05.400921 13, 0x0, sum = 2
3384 19:23:05.404228 14, 0x0, sum = 3
3385 19:23:05.404299 15, 0x0, sum = 4
3386 19:23:05.407456 best_step = 13
3387 19:23:05.407521
3388 19:23:05.407576 ==
3389 19:23:05.410759 Dram Type= 6, Freq= 0, CH_1, rank 0
3390 19:23:05.414609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3391 19:23:05.414675 ==
3392 19:23:05.417239 RX Vref Scan: 1
3393 19:23:05.417345
3394 19:23:05.417427 Set Vref Range= 32 -> 127
3395 19:23:05.417484
3396 19:23:05.420658 RX Vref 32 -> 127, step: 1
3397 19:23:05.420726
3398 19:23:05.424208 RX Delay -21 -> 252, step: 4
3399 19:23:05.424276
3400 19:23:05.427352 Set Vref, RX VrefLevel [Byte0]: 32
3401 19:23:05.430559 [Byte1]: 32
3402 19:23:05.430629
3403 19:23:05.433829 Set Vref, RX VrefLevel [Byte0]: 33
3404 19:23:05.437092 [Byte1]: 33
3405 19:23:05.441087
3406 19:23:05.441156 Set Vref, RX VrefLevel [Byte0]: 34
3407 19:23:05.444376 [Byte1]: 34
3408 19:23:05.448997
3409 19:23:05.449061 Set Vref, RX VrefLevel [Byte0]: 35
3410 19:23:05.452327 [Byte1]: 35
3411 19:23:05.457595
3412 19:23:05.457672 Set Vref, RX VrefLevel [Byte0]: 36
3413 19:23:05.460966 [Byte1]: 36
3414 19:23:05.464900
3415 19:23:05.464967 Set Vref, RX VrefLevel [Byte0]: 37
3416 19:23:05.468738 [Byte1]: 37
3417 19:23:05.473169
3418 19:23:05.473237 Set Vref, RX VrefLevel [Byte0]: 38
3419 19:23:05.476631 [Byte1]: 38
3420 19:23:05.481274
3421 19:23:05.481399 Set Vref, RX VrefLevel [Byte0]: 39
3422 19:23:05.484109 [Byte1]: 39
3423 19:23:05.488888
3424 19:23:05.488961 Set Vref, RX VrefLevel [Byte0]: 40
3425 19:23:05.492290 [Byte1]: 40
3426 19:23:05.496831
3427 19:23:05.496903 Set Vref, RX VrefLevel [Byte0]: 41
3428 19:23:05.499898 [Byte1]: 41
3429 19:23:05.504551
3430 19:23:05.504618 Set Vref, RX VrefLevel [Byte0]: 42
3431 19:23:05.507925 [Byte1]: 42
3432 19:23:05.512552
3433 19:23:05.512624 Set Vref, RX VrefLevel [Byte0]: 43
3434 19:23:05.515735 [Byte1]: 43
3435 19:23:05.520739
3436 19:23:05.520818 Set Vref, RX VrefLevel [Byte0]: 44
3437 19:23:05.523962 [Byte1]: 44
3438 19:23:05.528244
3439 19:23:05.528316 Set Vref, RX VrefLevel [Byte0]: 45
3440 19:23:05.531943 [Byte1]: 45
3441 19:23:05.536557
3442 19:23:05.536633 Set Vref, RX VrefLevel [Byte0]: 46
3443 19:23:05.539730 [Byte1]: 46
3444 19:23:05.544396
3445 19:23:05.544465 Set Vref, RX VrefLevel [Byte0]: 47
3446 19:23:05.547670 [Byte1]: 47
3447 19:23:05.552265
3448 19:23:05.552341 Set Vref, RX VrefLevel [Byte0]: 48
3449 19:23:05.555543 [Byte1]: 48
3450 19:23:05.560259
3451 19:23:05.560328 Set Vref, RX VrefLevel [Byte0]: 49
3452 19:23:05.563447 [Byte1]: 49
3453 19:23:05.568167
3454 19:23:05.568256 Set Vref, RX VrefLevel [Byte0]: 50
3455 19:23:05.571197 [Byte1]: 50
3456 19:23:05.575769
3457 19:23:05.575842 Set Vref, RX VrefLevel [Byte0]: 51
3458 19:23:05.579198 [Byte1]: 51
3459 19:23:05.583759
3460 19:23:05.583825 Set Vref, RX VrefLevel [Byte0]: 52
3461 19:23:05.586999 [Byte1]: 52
3462 19:23:05.591698
3463 19:23:05.591774 Set Vref, RX VrefLevel [Byte0]: 53
3464 19:23:05.598566 [Byte1]: 53
3465 19:23:05.598638
3466 19:23:05.601593 Set Vref, RX VrefLevel [Byte0]: 54
3467 19:23:05.604871 [Byte1]: 54
3468 19:23:05.604947
3469 19:23:05.608370 Set Vref, RX VrefLevel [Byte0]: 55
3470 19:23:05.611270 [Byte1]: 55
3471 19:23:05.615519
3472 19:23:05.615590 Set Vref, RX VrefLevel [Byte0]: 56
3473 19:23:05.618707 [Byte1]: 56
3474 19:23:05.623753
3475 19:23:05.623823 Set Vref, RX VrefLevel [Byte0]: 57
3476 19:23:05.626941 [Byte1]: 57
3477 19:23:05.631611
3478 19:23:05.631688 Set Vref, RX VrefLevel [Byte0]: 58
3479 19:23:05.634750 [Byte1]: 58
3480 19:23:05.639013
3481 19:23:05.639084 Set Vref, RX VrefLevel [Byte0]: 59
3482 19:23:05.642515 [Byte1]: 59
3483 19:23:05.647264
3484 19:23:05.647332 Set Vref, RX VrefLevel [Byte0]: 60
3485 19:23:05.650542 [Byte1]: 60
3486 19:23:05.655243
3487 19:23:05.655314 Set Vref, RX VrefLevel [Byte0]: 61
3488 19:23:05.658648 [Byte1]: 61
3489 19:23:05.663140
3490 19:23:05.663215 Set Vref, RX VrefLevel [Byte0]: 62
3491 19:23:05.666512 [Byte1]: 62
3492 19:23:05.670978
3493 19:23:05.671057 Set Vref, RX VrefLevel [Byte0]: 63
3494 19:23:05.674215 [Byte1]: 63
3495 19:23:05.678939
3496 19:23:05.679013 Set Vref, RX VrefLevel [Byte0]: 64
3497 19:23:05.682246 [Byte1]: 64
3498 19:23:05.686916
3499 19:23:05.686986 Set Vref, RX VrefLevel [Byte0]: 65
3500 19:23:05.690252 [Byte1]: 65
3501 19:23:05.694816
3502 19:23:05.694882 Set Vref, RX VrefLevel [Byte0]: 66
3503 19:23:05.698072 [Byte1]: 66
3504 19:23:05.702735
3505 19:23:05.702802 Set Vref, RX VrefLevel [Byte0]: 67
3506 19:23:05.705954 [Byte1]: 67
3507 19:23:05.710578
3508 19:23:05.710653 Final RX Vref Byte 0 = 49 to rank0
3509 19:23:05.714145 Final RX Vref Byte 1 = 53 to rank0
3510 19:23:05.717193 Final RX Vref Byte 0 = 49 to rank1
3511 19:23:05.720697 Final RX Vref Byte 1 = 53 to rank1==
3512 19:23:05.723578 Dram Type= 6, Freq= 0, CH_1, rank 0
3513 19:23:05.730709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3514 19:23:05.730789 ==
3515 19:23:05.730860 DQS Delay:
3516 19:23:05.730920 DQS0 = 0, DQS1 = 0
3517 19:23:05.733872 DQM Delay:
3518 19:23:05.733942 DQM0 = 116, DQM1 = 110
3519 19:23:05.737010 DQ Delay:
3520 19:23:05.740211 DQ0 =120, DQ1 =110, DQ2 =108, DQ3 =112
3521 19:23:05.743485 DQ4 =114, DQ5 =126, DQ6 =126, DQ7 =112
3522 19:23:05.746863 DQ8 =96, DQ9 =104, DQ10 =112, DQ11 =98
3523 19:23:05.750441 DQ12 =118, DQ13 =118, DQ14 =118, DQ15 =118
3524 19:23:05.750515
3525 19:23:05.750574
3526 19:23:05.759916 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f4, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 409 ps
3527 19:23:05.759995 CH1 RK0: MR19=403, MR18=1F4
3528 19:23:05.766952 CH1_RK0: MR19=0x403, MR18=0x1F4, DQSOSC=409, MR23=63, INC=39, DEC=26
3529 19:23:05.767046
3530 19:23:05.770236 ----->DramcWriteLeveling(PI) begin...
3531 19:23:05.770308 ==
3532 19:23:05.773544 Dram Type= 6, Freq= 0, CH_1, rank 1
3533 19:23:05.780156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3534 19:23:05.780240 ==
3535 19:23:05.783575 Write leveling (Byte 0): 26 => 26
3536 19:23:05.783657 Write leveling (Byte 1): 28 => 28
3537 19:23:05.786288 DramcWriteLeveling(PI) end<-----
3538 19:23:05.786370
3539 19:23:05.789607 ==
3540 19:23:05.789688 Dram Type= 6, Freq= 0, CH_1, rank 1
3541 19:23:05.796126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3542 19:23:05.796208 ==
3543 19:23:05.799444 [Gating] SW mode calibration
3544 19:23:05.806600 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3545 19:23:05.809951 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3546 19:23:05.815818 0 15 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
3547 19:23:05.819566 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3548 19:23:05.822838 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3549 19:23:05.829243 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3550 19:23:05.832145 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3551 19:23:05.835273 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3552 19:23:05.842060 0 15 24 | B1->B0 | 3030 3434 | 1 1 | (1 0) (1 0)
3553 19:23:05.845235 0 15 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3554 19:23:05.848677 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3555 19:23:05.855177 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3556 19:23:05.858289 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3557 19:23:05.864971 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3558 19:23:05.868320 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3559 19:23:05.871896 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3560 19:23:05.878352 1 0 24 | B1->B0 | 3737 2525 | 0 0 | (0 0) (1 1)
3561 19:23:05.881591 1 0 28 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
3562 19:23:05.884913 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3563 19:23:05.891556 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3564 19:23:05.894733 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3565 19:23:05.898039 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3566 19:23:05.904552 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3567 19:23:05.907584 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3568 19:23:05.911257 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3569 19:23:05.918071 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3570 19:23:05.921290 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3571 19:23:05.924296 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3572 19:23:05.930784 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3573 19:23:05.933937 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3574 19:23:05.937808 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3575 19:23:05.944294 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3576 19:23:05.947420 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3577 19:23:05.950356 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3578 19:23:05.957038 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3579 19:23:05.960653 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3580 19:23:05.963472 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3581 19:23:05.970313 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3582 19:23:05.973483 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3583 19:23:05.977065 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3584 19:23:05.983680 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3585 19:23:05.986809 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3586 19:23:05.989986 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3587 19:23:05.993265 Total UI for P1: 0, mck2ui 16
3588 19:23:05.996736 best dqsien dly found for B0: ( 1, 3, 26)
3589 19:23:05.999950 Total UI for P1: 0, mck2ui 16
3590 19:23:06.003460 best dqsien dly found for B1: ( 1, 3, 26)
3591 19:23:06.006692 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3592 19:23:06.009838 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3593 19:23:06.009914
3594 19:23:06.016298 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3595 19:23:06.019585 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3596 19:23:06.019665 [Gating] SW calibration Done
3597 19:23:06.022913 ==
3598 19:23:06.026076 Dram Type= 6, Freq= 0, CH_1, rank 1
3599 19:23:06.029420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3600 19:23:06.029502 ==
3601 19:23:06.029566 RX Vref Scan: 0
3602 19:23:06.029653
3603 19:23:06.032663 RX Vref 0 -> 0, step: 1
3604 19:23:06.032730
3605 19:23:06.035882 RX Delay -40 -> 252, step: 8
3606 19:23:06.039181 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3607 19:23:06.042919 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3608 19:23:06.049444 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3609 19:23:06.052703 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3610 19:23:06.055802 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3611 19:23:06.058964 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3612 19:23:06.062173 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3613 19:23:06.068785 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3614 19:23:06.072638 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3615 19:23:06.075527 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3616 19:23:06.078843 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3617 19:23:06.082185 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3618 19:23:06.088777 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3619 19:23:06.092061 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3620 19:23:06.095646 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3621 19:23:06.098456 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3622 19:23:06.098529 ==
3623 19:23:06.101742 Dram Type= 6, Freq= 0, CH_1, rank 1
3624 19:23:06.108760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3625 19:23:06.108837 ==
3626 19:23:06.108899 DQS Delay:
3627 19:23:06.112172 DQS0 = 0, DQS1 = 0
3628 19:23:06.112258 DQM Delay:
3629 19:23:06.115375 DQM0 = 116, DQM1 = 109
3630 19:23:06.115443 DQ Delay:
3631 19:23:06.118643 DQ0 =123, DQ1 =111, DQ2 =103, DQ3 =111
3632 19:23:06.122044 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =115
3633 19:23:06.124719 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
3634 19:23:06.127966 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3635 19:23:06.128040
3636 19:23:06.128101
3637 19:23:06.128165 ==
3638 19:23:06.131832 Dram Type= 6, Freq= 0, CH_1, rank 1
3639 19:23:06.138305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3640 19:23:06.138384 ==
3641 19:23:06.138446
3642 19:23:06.138504
3643 19:23:06.138559 TX Vref Scan disable
3644 19:23:06.141782 == TX Byte 0 ==
3645 19:23:06.144851 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3646 19:23:06.151604 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3647 19:23:06.151692 == TX Byte 1 ==
3648 19:23:06.154973 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3649 19:23:06.161294 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3650 19:23:06.161412 ==
3651 19:23:06.164642 Dram Type= 6, Freq= 0, CH_1, rank 1
3652 19:23:06.168039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3653 19:23:06.168121 ==
3654 19:23:06.179320 TX Vref=22, minBit 9, minWin=25, winSum=424
3655 19:23:06.182671 TX Vref=24, minBit 9, minWin=25, winSum=428
3656 19:23:06.185804 TX Vref=26, minBit 9, minWin=26, winSum=431
3657 19:23:06.189008 TX Vref=28, minBit 8, minWin=26, winSum=433
3658 19:23:06.192324 TX Vref=30, minBit 9, minWin=26, winSum=435
3659 19:23:06.198749 TX Vref=32, minBit 7, minWin=26, winSum=430
3660 19:23:06.202588 [TxChooseVref] Worse bit 9, Min win 26, Win sum 435, Final Vref 30
3661 19:23:06.202670
3662 19:23:06.205872 Final TX Range 1 Vref 30
3663 19:23:06.205954
3664 19:23:06.206018 ==
3665 19:23:06.209034 Dram Type= 6, Freq= 0, CH_1, rank 1
3666 19:23:06.212556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3667 19:23:06.215383 ==
3668 19:23:06.215490
3669 19:23:06.215583
3670 19:23:06.215664 TX Vref Scan disable
3671 19:23:06.219081 == TX Byte 0 ==
3672 19:23:06.222357 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3673 19:23:06.226087 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3674 19:23:06.228723 == TX Byte 1 ==
3675 19:23:06.232569 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3676 19:23:06.235780 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3677 19:23:06.238944
3678 19:23:06.239014 [DATLAT]
3679 19:23:06.239076 Freq=1200, CH1 RK1
3680 19:23:06.239140
3681 19:23:06.242372 DATLAT Default: 0xd
3682 19:23:06.242443 0, 0xFFFF, sum = 0
3683 19:23:06.245672 1, 0xFFFF, sum = 0
3684 19:23:06.245749 2, 0xFFFF, sum = 0
3685 19:23:06.249088 3, 0xFFFF, sum = 0
3686 19:23:06.252201 4, 0xFFFF, sum = 0
3687 19:23:06.252300 5, 0xFFFF, sum = 0
3688 19:23:06.255620 6, 0xFFFF, sum = 0
3689 19:23:06.255695 7, 0xFFFF, sum = 0
3690 19:23:06.259013 8, 0xFFFF, sum = 0
3691 19:23:06.259082 9, 0xFFFF, sum = 0
3692 19:23:06.262203 10, 0xFFFF, sum = 0
3693 19:23:06.262275 11, 0xFFFF, sum = 0
3694 19:23:06.265452 12, 0x0, sum = 1
3695 19:23:06.265530 13, 0x0, sum = 2
3696 19:23:06.268778 14, 0x0, sum = 3
3697 19:23:06.268870 15, 0x0, sum = 4
3698 19:23:06.272216 best_step = 13
3699 19:23:06.272288
3700 19:23:06.272361 ==
3701 19:23:06.275336 Dram Type= 6, Freq= 0, CH_1, rank 1
3702 19:23:06.278724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3703 19:23:06.278791 ==
3704 19:23:06.278850 RX Vref Scan: 0
3705 19:23:06.281907
3706 19:23:06.281973 RX Vref 0 -> 0, step: 1
3707 19:23:06.282037
3708 19:23:06.285292 RX Delay -21 -> 252, step: 4
3709 19:23:06.291866 iDelay=199, Bit 0, Center 118 (51 ~ 186) 136
3710 19:23:06.295349 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3711 19:23:06.298636 iDelay=199, Bit 2, Center 106 (43 ~ 170) 128
3712 19:23:06.301703 iDelay=199, Bit 3, Center 112 (47 ~ 178) 132
3713 19:23:06.304932 iDelay=199, Bit 4, Center 114 (47 ~ 182) 136
3714 19:23:06.311476 iDelay=199, Bit 5, Center 128 (63 ~ 194) 132
3715 19:23:06.314696 iDelay=199, Bit 6, Center 130 (63 ~ 198) 136
3716 19:23:06.317686 iDelay=199, Bit 7, Center 114 (47 ~ 182) 136
3717 19:23:06.320936 iDelay=199, Bit 8, Center 98 (31 ~ 166) 136
3718 19:23:06.324586 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3719 19:23:06.331136 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3720 19:23:06.334553 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3721 19:23:06.337438 iDelay=199, Bit 12, Center 118 (51 ~ 186) 136
3722 19:23:06.341150 iDelay=199, Bit 13, Center 118 (51 ~ 186) 136
3723 19:23:06.347516 iDelay=199, Bit 14, Center 118 (51 ~ 186) 136
3724 19:23:06.350821 iDelay=199, Bit 15, Center 118 (51 ~ 186) 136
3725 19:23:06.350902 ==
3726 19:23:06.354032 Dram Type= 6, Freq= 0, CH_1, rank 1
3727 19:23:06.357268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3728 19:23:06.357381 ==
3729 19:23:06.360470 DQS Delay:
3730 19:23:06.360542 DQS0 = 0, DQS1 = 0
3731 19:23:06.360608 DQM Delay:
3732 19:23:06.363733 DQM0 = 116, DQM1 = 110
3733 19:23:06.363800 DQ Delay:
3734 19:23:06.367092 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =112
3735 19:23:06.370327 DQ4 =114, DQ5 =128, DQ6 =130, DQ7 =114
3736 19:23:06.376814 DQ8 =98, DQ9 =100, DQ10 =110, DQ11 =100
3737 19:23:06.380193 DQ12 =118, DQ13 =118, DQ14 =118, DQ15 =118
3738 19:23:06.380267
3739 19:23:06.380327
3740 19:23:06.386806 [DQSOSCAuto] RK1, (LSB)MR18= 0xf2ed, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 415 ps
3741 19:23:06.390002 CH1 RK1: MR19=303, MR18=F2ED
3742 19:23:06.396727 CH1_RK1: MR19=0x303, MR18=0xF2ED, DQSOSC=415, MR23=63, INC=38, DEC=25
3743 19:23:06.400010 [RxdqsGatingPostProcess] freq 1200
3744 19:23:06.406502 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3745 19:23:06.406575 best DQS0 dly(2T, 0.5T) = (0, 11)
3746 19:23:06.409735 best DQS1 dly(2T, 0.5T) = (0, 11)
3747 19:23:06.413190 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3748 19:23:06.416507 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3749 19:23:06.419506 best DQS0 dly(2T, 0.5T) = (0, 11)
3750 19:23:06.422540 best DQS1 dly(2T, 0.5T) = (0, 11)
3751 19:23:06.426188 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3752 19:23:06.429170 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3753 19:23:06.432743 Pre-setting of DQS Precalculation
3754 19:23:06.439507 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3755 19:23:06.446151 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3756 19:23:06.452575 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3757 19:23:06.452667
3758 19:23:06.452737
3759 19:23:06.455667 [Calibration Summary] 2400 Mbps
3760 19:23:06.455763 CH 0, Rank 0
3761 19:23:06.459146 SW Impedance : PASS
3762 19:23:06.462381 DUTY Scan : NO K
3763 19:23:06.462472 ZQ Calibration : PASS
3764 19:23:06.465607 Jitter Meter : NO K
3765 19:23:06.469102 CBT Training : PASS
3766 19:23:06.469197 Write leveling : PASS
3767 19:23:06.472635 RX DQS gating : PASS
3768 19:23:06.475628 RX DQ/DQS(RDDQC) : PASS
3769 19:23:06.475710 TX DQ/DQS : PASS
3770 19:23:06.478859 RX DATLAT : PASS
3771 19:23:06.482246 RX DQ/DQS(Engine): PASS
3772 19:23:06.482328 TX OE : NO K
3773 19:23:06.482393 All Pass.
3774 19:23:06.485583
3775 19:23:06.485664 CH 0, Rank 1
3776 19:23:06.489085 SW Impedance : PASS
3777 19:23:06.489167 DUTY Scan : NO K
3778 19:23:06.492299 ZQ Calibration : PASS
3779 19:23:06.495719 Jitter Meter : NO K
3780 19:23:06.495800 CBT Training : PASS
3781 19:23:06.499101 Write leveling : PASS
3782 19:23:06.499182 RX DQS gating : PASS
3783 19:23:06.501718 RX DQ/DQS(RDDQC) : PASS
3784 19:23:06.505092 TX DQ/DQS : PASS
3785 19:23:06.505173 RX DATLAT : PASS
3786 19:23:06.508390 RX DQ/DQS(Engine): PASS
3787 19:23:06.511683 TX OE : NO K
3788 19:23:06.511763 All Pass.
3789 19:23:06.511827
3790 19:23:06.511886 CH 1, Rank 0
3791 19:23:06.515014 SW Impedance : PASS
3792 19:23:06.518260 DUTY Scan : NO K
3793 19:23:06.518341 ZQ Calibration : PASS
3794 19:23:06.521607 Jitter Meter : NO K
3795 19:23:06.524807 CBT Training : PASS
3796 19:23:06.524888 Write leveling : PASS
3797 19:23:06.528045 RX DQS gating : PASS
3798 19:23:06.531832 RX DQ/DQS(RDDQC) : PASS
3799 19:23:06.531915 TX DQ/DQS : PASS
3800 19:23:06.534942 RX DATLAT : PASS
3801 19:23:06.538143 RX DQ/DQS(Engine): PASS
3802 19:23:06.538212 TX OE : NO K
3803 19:23:06.541037 All Pass.
3804 19:23:06.541106
3805 19:23:06.541170 CH 1, Rank 1
3806 19:23:06.544424 SW Impedance : PASS
3807 19:23:06.544493 DUTY Scan : NO K
3808 19:23:06.547964 ZQ Calibration : PASS
3809 19:23:06.551161 Jitter Meter : NO K
3810 19:23:06.551232 CBT Training : PASS
3811 19:23:06.554641 Write leveling : PASS
3812 19:23:06.557259 RX DQS gating : PASS
3813 19:23:06.557350 RX DQ/DQS(RDDQC) : PASS
3814 19:23:06.560459 TX DQ/DQS : PASS
3815 19:23:06.563798 RX DATLAT : PASS
3816 19:23:06.563868 RX DQ/DQS(Engine): PASS
3817 19:23:06.567766 TX OE : NO K
3818 19:23:06.567840 All Pass.
3819 19:23:06.567899
3820 19:23:06.570946 DramC Write-DBI off
3821 19:23:06.574136 PER_BANK_REFRESH: Hybrid Mode
3822 19:23:06.574206 TX_TRACKING: ON
3823 19:23:06.583796 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3824 19:23:06.587126 [FAST_K] Save calibration result to emmc
3825 19:23:06.590288 dramc_set_vcore_voltage set vcore to 650000
3826 19:23:06.593592 Read voltage for 600, 5
3827 19:23:06.593729 Vio18 = 0
3828 19:23:06.593812 Vcore = 650000
3829 19:23:06.596796 Vdram = 0
3830 19:23:06.596861 Vddq = 0
3831 19:23:06.596924 Vmddr = 0
3832 19:23:06.603963 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3833 19:23:06.607266 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3834 19:23:06.609938 MEM_TYPE=3, freq_sel=19
3835 19:23:06.613181 sv_algorithm_assistance_LP4_1600
3836 19:23:06.617028 ============ PULL DRAM RESETB DOWN ============
3837 19:23:06.623033 ========== PULL DRAM RESETB DOWN end =========
3838 19:23:06.626905 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3839 19:23:06.630249 ===================================
3840 19:23:06.633418 LPDDR4 DRAM CONFIGURATION
3841 19:23:06.636555 ===================================
3842 19:23:06.636624 EX_ROW_EN[0] = 0x0
3843 19:23:06.639954 EX_ROW_EN[1] = 0x0
3844 19:23:06.640021 LP4Y_EN = 0x0
3845 19:23:06.643264 WORK_FSP = 0x0
3846 19:23:06.643331 WL = 0x2
3847 19:23:06.646589 RL = 0x2
3848 19:23:06.646662 BL = 0x2
3849 19:23:06.649650 RPST = 0x0
3850 19:23:06.653270 RD_PRE = 0x0
3851 19:23:06.653350 WR_PRE = 0x1
3852 19:23:06.656224 WR_PST = 0x0
3853 19:23:06.656295 DBI_WR = 0x0
3854 19:23:06.660072 DBI_RD = 0x0
3855 19:23:06.660205 OTF = 0x1
3856 19:23:06.662695 ===================================
3857 19:23:06.666024 ===================================
3858 19:23:06.669336 ANA top config
3859 19:23:06.672610 ===================================
3860 19:23:06.672683 DLL_ASYNC_EN = 0
3861 19:23:06.675895 ALL_SLAVE_EN = 1
3862 19:23:06.679878 NEW_RANK_MODE = 1
3863 19:23:06.682510 DLL_IDLE_MODE = 1
3864 19:23:06.682583 LP45_APHY_COMB_EN = 1
3865 19:23:06.686380 TX_ODT_DIS = 1
3866 19:23:06.689473 NEW_8X_MODE = 1
3867 19:23:06.692704 ===================================
3868 19:23:06.695846 ===================================
3869 19:23:06.699672 data_rate = 1200
3870 19:23:06.702805 CKR = 1
3871 19:23:06.706129 DQ_P2S_RATIO = 8
3872 19:23:06.709237 ===================================
3873 19:23:06.709306 CA_P2S_RATIO = 8
3874 19:23:06.712345 DQ_CA_OPEN = 0
3875 19:23:06.715845 DQ_SEMI_OPEN = 0
3876 19:23:06.719186 CA_SEMI_OPEN = 0
3877 19:23:06.722463 CA_FULL_RATE = 0
3878 19:23:06.725728 DQ_CKDIV4_EN = 1
3879 19:23:06.725835 CA_CKDIV4_EN = 1
3880 19:23:06.729061 CA_PREDIV_EN = 0
3881 19:23:06.732319 PH8_DLY = 0
3882 19:23:06.735510 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3883 19:23:06.738710 DQ_AAMCK_DIV = 4
3884 19:23:06.741948 CA_AAMCK_DIV = 4
3885 19:23:06.742015 CA_ADMCK_DIV = 4
3886 19:23:06.745220 DQ_TRACK_CA_EN = 0
3887 19:23:06.748495 CA_PICK = 600
3888 19:23:06.751791 CA_MCKIO = 600
3889 19:23:06.755009 MCKIO_SEMI = 0
3890 19:23:06.758823 PLL_FREQ = 2288
3891 19:23:06.761757 DQ_UI_PI_RATIO = 32
3892 19:23:06.765345 CA_UI_PI_RATIO = 0
3893 19:23:06.768447 ===================================
3894 19:23:06.771549 ===================================
3895 19:23:06.771648 memory_type:LPDDR4
3896 19:23:06.774872 GP_NUM : 10
3897 19:23:06.774954 SRAM_EN : 1
3898 19:23:06.778127 MD32_EN : 0
3899 19:23:06.781566 ===================================
3900 19:23:06.784789 [ANA_INIT] >>>>>>>>>>>>>>
3901 19:23:06.788195 <<<<<< [CONFIGURE PHASE]: ANA_TX
3902 19:23:06.791468 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3903 19:23:06.794536 ===================================
3904 19:23:06.798361 data_rate = 1200,PCW = 0X5800
3905 19:23:06.801596 ===================================
3906 19:23:06.804945 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3907 19:23:06.808273 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3908 19:23:06.814629 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3909 19:23:06.817737 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3910 19:23:06.820932 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3911 19:23:06.824491 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3912 19:23:06.827869 [ANA_INIT] flow start
3913 19:23:06.830777 [ANA_INIT] PLL >>>>>>>>
3914 19:23:06.830858 [ANA_INIT] PLL <<<<<<<<
3915 19:23:06.834003 [ANA_INIT] MIDPI >>>>>>>>
3916 19:23:06.837164 [ANA_INIT] MIDPI <<<<<<<<
3917 19:23:06.840975 [ANA_INIT] DLL >>>>>>>>
3918 19:23:06.841056 [ANA_INIT] flow end
3919 19:23:06.843982 ============ LP4 DIFF to SE enter ============
3920 19:23:06.850675 ============ LP4 DIFF to SE exit ============
3921 19:23:06.850757 [ANA_INIT] <<<<<<<<<<<<<
3922 19:23:06.854026 [Flow] Enable top DCM control >>>>>
3923 19:23:06.857488 [Flow] Enable top DCM control <<<<<
3924 19:23:06.860685 Enable DLL master slave shuffle
3925 19:23:06.866987 ==============================================================
3926 19:23:06.870200 Gating Mode config
3927 19:23:06.873460 ==============================================================
3928 19:23:06.877019 Config description:
3929 19:23:06.887072 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3930 19:23:06.893597 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3931 19:23:06.896831 SELPH_MODE 0: By rank 1: By Phase
3932 19:23:06.903276 ==============================================================
3933 19:23:06.906351 GAT_TRACK_EN = 1
3934 19:23:06.909692 RX_GATING_MODE = 2
3935 19:23:06.913036 RX_GATING_TRACK_MODE = 2
3936 19:23:06.913120 SELPH_MODE = 1
3937 19:23:06.916357 PICG_EARLY_EN = 1
3938 19:23:06.920269 VALID_LAT_VALUE = 1
3939 19:23:06.926146 ==============================================================
3940 19:23:06.929581 Enter into Gating configuration >>>>
3941 19:23:06.932986 Exit from Gating configuration <<<<
3942 19:23:06.936217 Enter into DVFS_PRE_config >>>>>
3943 19:23:06.946451 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3944 19:23:06.949184 Exit from DVFS_PRE_config <<<<<
3945 19:23:06.952748 Enter into PICG configuration >>>>
3946 19:23:06.956104 Exit from PICG configuration <<<<
3947 19:23:06.959126 [RX_INPUT] configuration >>>>>
3948 19:23:06.962958 [RX_INPUT] configuration <<<<<
3949 19:23:06.966285 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3950 19:23:06.972616 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3951 19:23:06.979389 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3952 19:23:06.985853 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3953 19:23:06.992235 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3954 19:23:06.998628 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3955 19:23:07.002571 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3956 19:23:07.005788 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3957 19:23:07.008810 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3958 19:23:07.015321 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3959 19:23:07.018580 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3960 19:23:07.021852 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3961 19:23:07.025179 ===================================
3962 19:23:07.028599 LPDDR4 DRAM CONFIGURATION
3963 19:23:07.032019 ===================================
3964 19:23:07.032112 EX_ROW_EN[0] = 0x0
3965 19:23:07.035236 EX_ROW_EN[1] = 0x0
3966 19:23:07.038526 LP4Y_EN = 0x0
3967 19:23:07.038598 WORK_FSP = 0x0
3968 19:23:07.041839 WL = 0x2
3969 19:23:07.041912 RL = 0x2
3970 19:23:07.044983 BL = 0x2
3971 19:23:07.045085 RPST = 0x0
3972 19:23:07.048264 RD_PRE = 0x0
3973 19:23:07.048335 WR_PRE = 0x1
3974 19:23:07.051434 WR_PST = 0x0
3975 19:23:07.051503 DBI_WR = 0x0
3976 19:23:07.055044 DBI_RD = 0x0
3977 19:23:07.055119 OTF = 0x1
3978 19:23:07.058064 ===================================
3979 19:23:07.061626 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3980 19:23:07.068226 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3981 19:23:07.071241 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3982 19:23:07.074880 ===================================
3983 19:23:07.078171 LPDDR4 DRAM CONFIGURATION
3984 19:23:07.081455 ===================================
3985 19:23:07.081529 EX_ROW_EN[0] = 0x10
3986 19:23:07.084680 EX_ROW_EN[1] = 0x0
3987 19:23:07.087935 LP4Y_EN = 0x0
3988 19:23:07.088024 WORK_FSP = 0x0
3989 19:23:07.091377 WL = 0x2
3990 19:23:07.091465 RL = 0x2
3991 19:23:07.094601 BL = 0x2
3992 19:23:07.094681 RPST = 0x0
3993 19:23:07.097949 RD_PRE = 0x0
3994 19:23:07.098024 WR_PRE = 0x1
3995 19:23:07.101580 WR_PST = 0x0
3996 19:23:07.101660 DBI_WR = 0x0
3997 19:23:07.104734 DBI_RD = 0x0
3998 19:23:07.104816 OTF = 0x1
3999 19:23:07.107804 ===================================
4000 19:23:07.114074 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4001 19:23:07.119178 nWR fixed to 30
4002 19:23:07.122336 [ModeRegInit_LP4] CH0 RK0
4003 19:23:07.122417 [ModeRegInit_LP4] CH0 RK1
4004 19:23:07.125642 [ModeRegInit_LP4] CH1 RK0
4005 19:23:07.128988 [ModeRegInit_LP4] CH1 RK1
4006 19:23:07.129097 match AC timing 17
4007 19:23:07.135654 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
4008 19:23:07.138772 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4009 19:23:07.142061 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
4010 19:23:07.148075 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
4011 19:23:07.151346 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
4012 19:23:07.151426 ==
4013 19:23:07.154653 Dram Type= 6, Freq= 0, CH_0, rank 0
4014 19:23:07.158171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4015 19:23:07.161293 ==
4016 19:23:07.164461 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4017 19:23:07.171018 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4018 19:23:07.174219 [CA 0] Center 36 (6~66) winsize 61
4019 19:23:07.177948 [CA 1] Center 36 (6~66) winsize 61
4020 19:23:07.180855 [CA 2] Center 34 (4~65) winsize 62
4021 19:23:07.184192 [CA 3] Center 34 (4~65) winsize 62
4022 19:23:07.187738 [CA 4] Center 33 (3~64) winsize 62
4023 19:23:07.190898 [CA 5] Center 33 (3~64) winsize 62
4024 19:23:07.190977
4025 19:23:07.194149 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4026 19:23:07.194227
4027 19:23:07.197547 [CATrainingPosCal] consider 1 rank data
4028 19:23:07.200858 u2DelayCellTimex100 = 270/100 ps
4029 19:23:07.204045 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4030 19:23:07.207277 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4031 19:23:07.213773 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4032 19:23:07.217264 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4033 19:23:07.220920 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4034 19:23:07.223905 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4035 19:23:07.223990
4036 19:23:07.226968 CA PerBit enable=1, Macro0, CA PI delay=33
4037 19:23:07.227051
4038 19:23:07.230660 [CBTSetCACLKResult] CA Dly = 33
4039 19:23:07.233272 CS Dly: 5 (0~36)
4040 19:23:07.233397 ==
4041 19:23:07.236580 Dram Type= 6, Freq= 0, CH_0, rank 1
4042 19:23:07.239870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4043 19:23:07.239971 ==
4044 19:23:07.246454 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4045 19:23:07.249771 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4046 19:23:07.254399 [CA 0] Center 35 (5~66) winsize 62
4047 19:23:07.257578 [CA 1] Center 36 (6~66) winsize 61
4048 19:23:07.260903 [CA 2] Center 34 (4~65) winsize 62
4049 19:23:07.263907 [CA 3] Center 34 (4~64) winsize 61
4050 19:23:07.267171 [CA 4] Center 33 (2~64) winsize 63
4051 19:23:07.270889 [CA 5] Center 33 (2~64) winsize 63
4052 19:23:07.270991
4053 19:23:07.274253 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4054 19:23:07.274358
4055 19:23:07.277653 [CATrainingPosCal] consider 2 rank data
4056 19:23:07.280984 u2DelayCellTimex100 = 270/100 ps
4057 19:23:07.283622 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4058 19:23:07.290580 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4059 19:23:07.293653 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4060 19:23:07.297020 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4061 19:23:07.300416 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4062 19:23:07.303428 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4063 19:23:07.303530
4064 19:23:07.306683 CA PerBit enable=1, Macro0, CA PI delay=33
4065 19:23:07.306789
4066 19:23:07.310049 [CBTSetCACLKResult] CA Dly = 33
4067 19:23:07.313382 CS Dly: 5 (0~37)
4068 19:23:07.313466
4069 19:23:07.316610 ----->DramcWriteLeveling(PI) begin...
4070 19:23:07.316687 ==
4071 19:23:07.319921 Dram Type= 6, Freq= 0, CH_0, rank 0
4072 19:23:07.323573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4073 19:23:07.323680 ==
4074 19:23:07.326617 Write leveling (Byte 0): 32 => 32
4075 19:23:07.329997 Write leveling (Byte 1): 29 => 29
4076 19:23:07.333532 DramcWriteLeveling(PI) end<-----
4077 19:23:07.333611
4078 19:23:07.333675 ==
4079 19:23:07.336580 Dram Type= 6, Freq= 0, CH_0, rank 0
4080 19:23:07.339580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4081 19:23:07.339683 ==
4082 19:23:07.343132 [Gating] SW mode calibration
4083 19:23:07.349701 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4084 19:23:07.356304 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4085 19:23:07.359370 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4086 19:23:07.362575 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4087 19:23:07.369692 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4088 19:23:07.372851 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4089 19:23:07.379316 0 9 16 | B1->B0 | 2f2f 2727 | 0 0 | (0 0) (0 0)
4090 19:23:07.382577 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4091 19:23:07.385906 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4092 19:23:07.392344 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4093 19:23:07.395593 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4094 19:23:07.398910 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4095 19:23:07.405320 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4096 19:23:07.408868 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4097 19:23:07.411828 0 10 16 | B1->B0 | 3636 3d3d | 0 0 | (0 0) (0 0)
4098 19:23:07.418496 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4099 19:23:07.421735 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4100 19:23:07.425074 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4101 19:23:07.431736 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4102 19:23:07.435346 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4103 19:23:07.438448 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4104 19:23:07.442154 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4105 19:23:07.448371 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4106 19:23:07.451819 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4107 19:23:07.458613 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4108 19:23:07.461823 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4109 19:23:07.464979 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4110 19:23:07.468187 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4111 19:23:07.474705 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4112 19:23:07.477861 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4113 19:23:07.484962 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4114 19:23:07.488108 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4115 19:23:07.491591 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4116 19:23:07.498101 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4117 19:23:07.501345 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4118 19:23:07.504105 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4119 19:23:07.510693 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4120 19:23:07.513897 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4121 19:23:07.517448 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4122 19:23:07.520742 Total UI for P1: 0, mck2ui 16
4123 19:23:07.523826 best dqsien dly found for B0: ( 0, 13, 10)
4124 19:23:07.527253 Total UI for P1: 0, mck2ui 16
4125 19:23:07.530344 best dqsien dly found for B1: ( 0, 13, 12)
4126 19:23:07.533714 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4127 19:23:07.536933 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4128 19:23:07.537042
4129 19:23:07.543470 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4130 19:23:07.546550 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4131 19:23:07.550399 [Gating] SW calibration Done
4132 19:23:07.550509 ==
4133 19:23:07.553662 Dram Type= 6, Freq= 0, CH_0, rank 0
4134 19:23:07.556833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4135 19:23:07.556942 ==
4136 19:23:07.557034 RX Vref Scan: 0
4137 19:23:07.557122
4138 19:23:07.559913 RX Vref 0 -> 0, step: 1
4139 19:23:07.560034
4140 19:23:07.563632 RX Delay -230 -> 252, step: 16
4141 19:23:07.566525 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4142 19:23:07.572969 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4143 19:23:07.576225 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4144 19:23:07.579627 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4145 19:23:07.582789 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4146 19:23:07.586065 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4147 19:23:07.592567 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4148 19:23:07.596507 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4149 19:23:07.599148 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4150 19:23:07.603007 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4151 19:23:07.609539 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4152 19:23:07.612700 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4153 19:23:07.616053 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4154 19:23:07.619268 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4155 19:23:07.625873 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4156 19:23:07.628892 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4157 19:23:07.629017 ==
4158 19:23:07.632505 Dram Type= 6, Freq= 0, CH_0, rank 0
4159 19:23:07.635738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4160 19:23:07.635843 ==
4161 19:23:07.638978 DQS Delay:
4162 19:23:07.639095 DQS0 = 0, DQS1 = 0
4163 19:23:07.642137 DQM Delay:
4164 19:23:07.642248 DQM0 = 42, DQM1 = 28
4165 19:23:07.642339 DQ Delay:
4166 19:23:07.645849 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4167 19:23:07.649125 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4168 19:23:07.652172 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4169 19:23:07.655734 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4170 19:23:07.655831
4171 19:23:07.655902
4172 19:23:07.655962 ==
4173 19:23:07.658963 Dram Type= 6, Freq= 0, CH_0, rank 0
4174 19:23:07.665312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4175 19:23:07.665400 ==
4176 19:23:07.665463
4177 19:23:07.665528
4178 19:23:07.668592 TX Vref Scan disable
4179 19:23:07.668660 == TX Byte 0 ==
4180 19:23:07.672264 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4181 19:23:07.678960 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4182 19:23:07.679035 == TX Byte 1 ==
4183 19:23:07.685010 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4184 19:23:07.688595 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4185 19:23:07.688672 ==
4186 19:23:07.691678 Dram Type= 6, Freq= 0, CH_0, rank 0
4187 19:23:07.694906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4188 19:23:07.694976 ==
4189 19:23:07.695037
4190 19:23:07.695095
4191 19:23:07.698208 TX Vref Scan disable
4192 19:23:07.701427 == TX Byte 0 ==
4193 19:23:07.704877 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4194 19:23:07.708215 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4195 19:23:07.711622 == TX Byte 1 ==
4196 19:23:07.714944 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4197 19:23:07.718232 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4198 19:23:07.718301
4199 19:23:07.721521 [DATLAT]
4200 19:23:07.721675 Freq=600, CH0 RK0
4201 19:23:07.721809
4202 19:23:07.724923 DATLAT Default: 0x9
4203 19:23:07.725071 0, 0xFFFF, sum = 0
4204 19:23:07.728209 1, 0xFFFF, sum = 0
4205 19:23:07.728350 2, 0xFFFF, sum = 0
4206 19:23:07.731655 3, 0xFFFF, sum = 0
4207 19:23:07.731814 4, 0xFFFF, sum = 0
4208 19:23:07.734848 5, 0xFFFF, sum = 0
4209 19:23:07.735003 6, 0xFFFF, sum = 0
4210 19:23:07.738103 7, 0xFFFF, sum = 0
4211 19:23:07.738248 8, 0x0, sum = 1
4212 19:23:07.741278 9, 0x0, sum = 2
4213 19:23:07.741402 10, 0x0, sum = 3
4214 19:23:07.744261 11, 0x0, sum = 4
4215 19:23:07.744366 best_step = 9
4216 19:23:07.744464
4217 19:23:07.744552 ==
4218 19:23:07.747939 Dram Type= 6, Freq= 0, CH_0, rank 0
4219 19:23:07.754507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4220 19:23:07.754628 ==
4221 19:23:07.754737 RX Vref Scan: 1
4222 19:23:07.754834
4223 19:23:07.757706 RX Vref 0 -> 0, step: 1
4224 19:23:07.757805
4225 19:23:07.760534 RX Delay -195 -> 252, step: 8
4226 19:23:07.760634
4227 19:23:07.764110 Set Vref, RX VrefLevel [Byte0]: 59
4228 19:23:07.767475 [Byte1]: 49
4229 19:23:07.767555
4230 19:23:07.770491 Final RX Vref Byte 0 = 59 to rank0
4231 19:23:07.774054 Final RX Vref Byte 1 = 49 to rank0
4232 19:23:07.777456 Final RX Vref Byte 0 = 59 to rank1
4233 19:23:07.780780 Final RX Vref Byte 1 = 49 to rank1==
4234 19:23:07.783452 Dram Type= 6, Freq= 0, CH_0, rank 0
4235 19:23:07.787295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4236 19:23:07.790310 ==
4237 19:23:07.790394 DQS Delay:
4238 19:23:07.790459 DQS0 = 0, DQS1 = 0
4239 19:23:07.793978 DQM Delay:
4240 19:23:07.794061 DQM0 = 44, DQM1 = 32
4241 19:23:07.796756 DQ Delay:
4242 19:23:07.799953 DQ0 =44, DQ1 =44, DQ2 =44, DQ3 =40
4243 19:23:07.800035 DQ4 =44, DQ5 =36, DQ6 =52, DQ7 =48
4244 19:23:07.803625 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =24
4245 19:23:07.806570 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =40
4246 19:23:07.809844
4247 19:23:07.809927
4248 19:23:07.816434 [DQSOSCAuto] RK0, (LSB)MR18= 0x673f, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 390 ps
4249 19:23:07.819659 CH0 RK0: MR19=808, MR18=673F
4250 19:23:07.826312 CH0_RK0: MR19=0x808, MR18=0x673F, DQSOSC=390, MR23=63, INC=172, DEC=114
4251 19:23:07.826457
4252 19:23:07.829640 ----->DramcWriteLeveling(PI) begin...
4253 19:23:07.829725 ==
4254 19:23:07.832998 Dram Type= 6, Freq= 0, CH_0, rank 1
4255 19:23:07.836254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4256 19:23:07.836365 ==
4257 19:23:07.839628 Write leveling (Byte 0): 33 => 33
4258 19:23:07.842918 Write leveling (Byte 1): 31 => 31
4259 19:23:07.846151 DramcWriteLeveling(PI) end<-----
4260 19:23:07.846227
4261 19:23:07.846291 ==
4262 19:23:07.849281 Dram Type= 6, Freq= 0, CH_0, rank 1
4263 19:23:07.852922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4264 19:23:07.852992 ==
4265 19:23:07.856239 [Gating] SW mode calibration
4266 19:23:07.862562 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4267 19:23:07.869011 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4268 19:23:07.872349 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4269 19:23:07.879317 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4270 19:23:07.882642 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4271 19:23:07.885480 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4272 19:23:07.891934 0 9 16 | B1->B0 | 2e2e 2828 | 0 0 | (0 0) (0 0)
4273 19:23:07.895294 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4274 19:23:07.898530 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4275 19:23:07.926197 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4276 19:23:07.926349 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4277 19:23:07.926473 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4278 19:23:07.926569 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4279 19:23:07.926659 0 10 12 | B1->B0 | 2424 2626 | 0 0 | (0 0) (0 0)
4280 19:23:07.926771 0 10 16 | B1->B0 | 3c3c 4444 | 1 1 | (0 0) (0 0)
4281 19:23:07.931987 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4282 19:23:07.935172 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4283 19:23:07.938499 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4284 19:23:07.945213 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4285 19:23:07.947890 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4286 19:23:07.951104 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4287 19:23:07.958090 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4288 19:23:07.961324 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4289 19:23:07.964766 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4290 19:23:07.970850 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4291 19:23:07.974297 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4292 19:23:07.977660 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4293 19:23:07.984219 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4294 19:23:07.987357 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4295 19:23:07.991045 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4296 19:23:07.997345 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4297 19:23:08.000624 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4298 19:23:08.003997 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4299 19:23:08.010679 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4300 19:23:08.013867 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4301 19:23:08.017142 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4302 19:23:08.023601 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4303 19:23:08.027399 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4304 19:23:08.030657 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4305 19:23:08.033976 Total UI for P1: 0, mck2ui 16
4306 19:23:08.036712 best dqsien dly found for B0: ( 0, 13, 12)
4307 19:23:08.040587 Total UI for P1: 0, mck2ui 16
4308 19:23:08.043763 best dqsien dly found for B1: ( 0, 13, 12)
4309 19:23:08.047042 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4310 19:23:08.050306 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4311 19:23:08.053699
4312 19:23:08.057008 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4313 19:23:08.059922 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4314 19:23:08.063609 [Gating] SW calibration Done
4315 19:23:08.063711 ==
4316 19:23:08.066793 Dram Type= 6, Freq= 0, CH_0, rank 1
4317 19:23:08.070185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4318 19:23:08.070265 ==
4319 19:23:08.073316 RX Vref Scan: 0
4320 19:23:08.073401
4321 19:23:08.073467 RX Vref 0 -> 0, step: 1
4322 19:23:08.073535
4323 19:23:08.076978 RX Delay -230 -> 252, step: 16
4324 19:23:08.079952 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4325 19:23:08.086585 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4326 19:23:08.089865 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4327 19:23:08.092961 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4328 19:23:08.096296 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4329 19:23:08.103138 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4330 19:23:08.106678 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4331 19:23:08.109856 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4332 19:23:08.113165 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4333 19:23:08.116444 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4334 19:23:08.122976 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4335 19:23:08.126244 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4336 19:23:08.129538 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4337 19:23:08.132887 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4338 19:23:08.139520 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4339 19:23:08.142451 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4340 19:23:08.142555 ==
4341 19:23:08.146087 Dram Type= 6, Freq= 0, CH_0, rank 1
4342 19:23:08.149161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4343 19:23:08.149275 ==
4344 19:23:08.152579 DQS Delay:
4345 19:23:08.152687 DQS0 = 0, DQS1 = 0
4346 19:23:08.155882 DQM Delay:
4347 19:23:08.155989 DQM0 = 46, DQM1 = 37
4348 19:23:08.156082 DQ Delay:
4349 19:23:08.159139 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4350 19:23:08.162496 DQ4 =41, DQ5 =41, DQ6 =57, DQ7 =57
4351 19:23:08.165722 DQ8 =17, DQ9 =25, DQ10 =41, DQ11 =25
4352 19:23:08.168616 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4353 19:23:08.168718
4354 19:23:08.168826
4355 19:23:08.172433 ==
4356 19:23:08.175716 Dram Type= 6, Freq= 0, CH_0, rank 1
4357 19:23:08.178930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4358 19:23:08.179036 ==
4359 19:23:08.179132
4360 19:23:08.179221
4361 19:23:08.181946 TX Vref Scan disable
4362 19:23:08.182048 == TX Byte 0 ==
4363 19:23:08.188657 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4364 19:23:08.191863 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4365 19:23:08.191970 == TX Byte 1 ==
4366 19:23:08.198492 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4367 19:23:08.201653 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4368 19:23:08.201787 ==
4369 19:23:08.205091 Dram Type= 6, Freq= 0, CH_0, rank 1
4370 19:23:08.208442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4371 19:23:08.208577 ==
4372 19:23:08.208672
4373 19:23:08.208760
4374 19:23:08.211589 TX Vref Scan disable
4375 19:23:08.214633 == TX Byte 0 ==
4376 19:23:08.217820 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4377 19:23:08.224578 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4378 19:23:08.224762 == TX Byte 1 ==
4379 19:23:08.227750 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4380 19:23:08.234189 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4381 19:23:08.234369
4382 19:23:08.234469 [DATLAT]
4383 19:23:08.234564 Freq=600, CH0 RK1
4384 19:23:08.234659
4385 19:23:08.237605 DATLAT Default: 0x9
4386 19:23:08.240983 0, 0xFFFF, sum = 0
4387 19:23:08.241131 1, 0xFFFF, sum = 0
4388 19:23:08.244040 2, 0xFFFF, sum = 0
4389 19:23:08.244165 3, 0xFFFF, sum = 0
4390 19:23:08.247894 4, 0xFFFF, sum = 0
4391 19:23:08.248018 5, 0xFFFF, sum = 0
4392 19:23:08.251118 6, 0xFFFF, sum = 0
4393 19:23:08.251248 7, 0xFFFF, sum = 0
4394 19:23:08.254256 8, 0x0, sum = 1
4395 19:23:08.254407 9, 0x0, sum = 2
4396 19:23:08.257407 10, 0x0, sum = 3
4397 19:23:08.257560 11, 0x0, sum = 4
4398 19:23:08.257679 best_step = 9
4399 19:23:08.257772
4400 19:23:08.260567 ==
4401 19:23:08.264166 Dram Type= 6, Freq= 0, CH_0, rank 1
4402 19:23:08.267593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4403 19:23:08.267758 ==
4404 19:23:08.267862 RX Vref Scan: 0
4405 19:23:08.267956
4406 19:23:08.270833 RX Vref 0 -> 0, step: 1
4407 19:23:08.270942
4408 19:23:08.274011 RX Delay -195 -> 252, step: 8
4409 19:23:08.280132 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4410 19:23:08.283588 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4411 19:23:08.287518 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4412 19:23:08.290677 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4413 19:23:08.297178 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4414 19:23:08.300307 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4415 19:23:08.303600 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4416 19:23:08.306972 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4417 19:23:08.310328 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4418 19:23:08.316691 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4419 19:23:08.320148 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4420 19:23:08.323281 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4421 19:23:08.326903 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4422 19:23:08.333362 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4423 19:23:08.336564 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4424 19:23:08.339855 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4425 19:23:08.339938 ==
4426 19:23:08.343023 Dram Type= 6, Freq= 0, CH_0, rank 1
4427 19:23:08.349804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4428 19:23:08.349913 ==
4429 19:23:08.350008 DQS Delay:
4430 19:23:08.350103 DQS0 = 0, DQS1 = 0
4431 19:23:08.353098 DQM Delay:
4432 19:23:08.353206 DQM0 = 42, DQM1 = 36
4433 19:23:08.356418 DQ Delay:
4434 19:23:08.359677 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4435 19:23:08.362745 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4436 19:23:08.365975 DQ8 =28, DQ9 =20, DQ10 =40, DQ11 =28
4437 19:23:08.369132 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =44
4438 19:23:08.369240
4439 19:23:08.369337
4440 19:23:08.376041 [DQSOSCAuto] RK1, (LSB)MR18= 0x5d11, (MSB)MR19= 0x808, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
4441 19:23:08.379373 CH0 RK1: MR19=808, MR18=5D11
4442 19:23:08.385991 CH0_RK1: MR19=0x808, MR18=0x5D11, DQSOSC=392, MR23=63, INC=170, DEC=113
4443 19:23:08.389004 [RxdqsGatingPostProcess] freq 600
4444 19:23:08.392224 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4445 19:23:08.395656 Pre-setting of DQS Precalculation
4446 19:23:08.402501 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4447 19:23:08.402633 ==
4448 19:23:08.405303 Dram Type= 6, Freq= 0, CH_1, rank 0
4449 19:23:08.408983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4450 19:23:08.409091 ==
4451 19:23:08.415560 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4452 19:23:08.422361 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4453 19:23:08.425583 [CA 0] Center 35 (5~66) winsize 62
4454 19:23:08.428848 [CA 1] Center 35 (5~66) winsize 62
4455 19:23:08.431507 [CA 2] Center 34 (4~65) winsize 62
4456 19:23:08.435442 [CA 3] Center 33 (3~64) winsize 62
4457 19:23:08.438538 [CA 4] Center 34 (4~65) winsize 62
4458 19:23:08.441529 [CA 5] Center 33 (3~64) winsize 62
4459 19:23:08.441637
4460 19:23:08.444953 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4461 19:23:08.445062
4462 19:23:08.448109 [CATrainingPosCal] consider 1 rank data
4463 19:23:08.451509 u2DelayCellTimex100 = 270/100 ps
4464 19:23:08.454548 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4465 19:23:08.457923 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4466 19:23:08.461166 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4467 19:23:08.464459 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4468 19:23:08.467620 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4469 19:23:08.474300 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4470 19:23:08.474404
4471 19:23:08.477608 CA PerBit enable=1, Macro0, CA PI delay=33
4472 19:23:08.477686
4473 19:23:08.480869 [CBTSetCACLKResult] CA Dly = 33
4474 19:23:08.480967 CS Dly: 5 (0~36)
4475 19:23:08.481055 ==
4476 19:23:08.484584 Dram Type= 6, Freq= 0, CH_1, rank 1
4477 19:23:08.487567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4478 19:23:08.491014 ==
4479 19:23:08.494006 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4480 19:23:08.500582 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4481 19:23:08.503718 [CA 0] Center 35 (5~66) winsize 62
4482 19:23:08.507570 [CA 1] Center 36 (6~66) winsize 61
4483 19:23:08.510580 [CA 2] Center 34 (4~65) winsize 62
4484 19:23:08.513650 [CA 3] Center 34 (4~65) winsize 62
4485 19:23:08.517173 [CA 4] Center 34 (3~65) winsize 63
4486 19:23:08.520256 [CA 5] Center 34 (4~65) winsize 62
4487 19:23:08.520354
4488 19:23:08.523749 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4489 19:23:08.523829
4490 19:23:08.526979 [CATrainingPosCal] consider 2 rank data
4491 19:23:08.530275 u2DelayCellTimex100 = 270/100 ps
4492 19:23:08.533588 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4493 19:23:08.536943 CA1 delay=36 (6~66),Diff = 2 PI (19 cell)
4494 19:23:08.543538 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4495 19:23:08.546737 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
4496 19:23:08.549727 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4497 19:23:08.553356 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4498 19:23:08.553442
4499 19:23:08.556874 CA PerBit enable=1, Macro0, CA PI delay=34
4500 19:23:08.556973
4501 19:23:08.559997 [CBTSetCACLKResult] CA Dly = 34
4502 19:23:08.560098 CS Dly: 5 (0~37)
4503 19:23:08.563004
4504 19:23:08.566650 ----->DramcWriteLeveling(PI) begin...
4505 19:23:08.566749 ==
4506 19:23:08.569801 Dram Type= 6, Freq= 0, CH_1, rank 0
4507 19:23:08.573272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4508 19:23:08.573373 ==
4509 19:23:08.576648 Write leveling (Byte 0): 32 => 32
4510 19:23:08.579924 Write leveling (Byte 1): 29 => 29
4511 19:23:08.583134 DramcWriteLeveling(PI) end<-----
4512 19:23:08.583234
4513 19:23:08.583326 ==
4514 19:23:08.586458 Dram Type= 6, Freq= 0, CH_1, rank 0
4515 19:23:08.589713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4516 19:23:08.589784 ==
4517 19:23:08.592904 [Gating] SW mode calibration
4518 19:23:08.599712 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4519 19:23:08.606080 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4520 19:23:08.609683 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4521 19:23:08.612621 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4522 19:23:08.619200 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4523 19:23:08.622856 0 9 12 | B1->B0 | 3131 3030 | 0 0 | (1 0) (1 1)
4524 19:23:08.625750 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4525 19:23:08.632548 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4526 19:23:08.636023 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4527 19:23:08.639358 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4528 19:23:08.645813 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4529 19:23:08.649023 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4530 19:23:08.652335 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4531 19:23:08.658814 0 10 12 | B1->B0 | 3030 3636 | 0 0 | (0 0) (0 0)
4532 19:23:08.662581 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4533 19:23:08.665582 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4534 19:23:08.672504 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4535 19:23:08.675314 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4536 19:23:08.678876 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4537 19:23:08.684998 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4538 19:23:08.688383 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4539 19:23:08.691693 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4540 19:23:08.698312 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4541 19:23:08.702039 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4542 19:23:08.705011 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4543 19:23:08.711336 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4544 19:23:08.715087 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4545 19:23:08.718205 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4546 19:23:08.724530 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4547 19:23:08.727899 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4548 19:23:08.731493 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4549 19:23:08.738038 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4550 19:23:08.741213 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4551 19:23:08.744592 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4552 19:23:08.751164 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4553 19:23:08.754504 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4554 19:23:08.757745 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4555 19:23:08.764538 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4556 19:23:08.767677 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4557 19:23:08.771003 Total UI for P1: 0, mck2ui 16
4558 19:23:08.774148 best dqsien dly found for B0: ( 0, 13, 12)
4559 19:23:08.777941 Total UI for P1: 0, mck2ui 16
4560 19:23:08.781241 best dqsien dly found for B1: ( 0, 13, 12)
4561 19:23:08.784507 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4562 19:23:08.787350 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4563 19:23:08.787431
4564 19:23:08.790833 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4565 19:23:08.794012 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4566 19:23:08.797207 [Gating] SW calibration Done
4567 19:23:08.797312 ==
4568 19:23:08.800565 Dram Type= 6, Freq= 0, CH_1, rank 0
4569 19:23:08.807200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4570 19:23:08.807279 ==
4571 19:23:08.807346 RX Vref Scan: 0
4572 19:23:08.807435
4573 19:23:08.810274 RX Vref 0 -> 0, step: 1
4574 19:23:08.810375
4575 19:23:08.813960 RX Delay -230 -> 252, step: 16
4576 19:23:08.817139 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4577 19:23:08.820474 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4578 19:23:08.823771 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4579 19:23:08.830408 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4580 19:23:08.833661 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4581 19:23:08.836883 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4582 19:23:08.839837 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4583 19:23:08.846509 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4584 19:23:08.849731 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4585 19:23:08.852915 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4586 19:23:08.856154 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4587 19:23:08.862821 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4588 19:23:08.866071 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4589 19:23:08.869374 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4590 19:23:08.872496 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4591 19:23:08.879522 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4592 19:23:08.879602 ==
4593 19:23:08.882988 Dram Type= 6, Freq= 0, CH_1, rank 0
4594 19:23:08.886348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4595 19:23:08.886451 ==
4596 19:23:08.886542 DQS Delay:
4597 19:23:08.889027 DQS0 = 0, DQS1 = 0
4598 19:23:08.889128 DQM Delay:
4599 19:23:08.892284 DQM0 = 45, DQM1 = 37
4600 19:23:08.892386 DQ Delay:
4601 19:23:08.895630 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4602 19:23:08.898727 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4603 19:23:08.902253 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4604 19:23:08.905891 DQ12 =49, DQ13 =41, DQ14 =49, DQ15 =49
4605 19:23:08.905971
4606 19:23:08.906061
4607 19:23:08.906146 ==
4608 19:23:08.908758 Dram Type= 6, Freq= 0, CH_1, rank 0
4609 19:23:08.915163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4610 19:23:08.915242 ==
4611 19:23:08.915311
4612 19:23:08.915399
4613 19:23:08.915485 TX Vref Scan disable
4614 19:23:08.919020 == TX Byte 0 ==
4615 19:23:08.922151 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4616 19:23:08.928932 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4617 19:23:08.929041 == TX Byte 1 ==
4618 19:23:08.932198 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4619 19:23:08.939120 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4620 19:23:08.939227 ==
4621 19:23:08.941868 Dram Type= 6, Freq= 0, CH_1, rank 0
4622 19:23:08.945622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4623 19:23:08.945754 ==
4624 19:23:08.945902
4625 19:23:08.946023
4626 19:23:08.948920 TX Vref Scan disable
4627 19:23:08.952171 == TX Byte 0 ==
4628 19:23:08.955812 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4629 19:23:08.958345 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4630 19:23:08.962296 == TX Byte 1 ==
4631 19:23:08.965666 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4632 19:23:08.968330 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4633 19:23:08.968426
4634 19:23:08.968518 [DATLAT]
4635 19:23:08.971756 Freq=600, CH1 RK0
4636 19:23:08.971853
4637 19:23:08.974932 DATLAT Default: 0x9
4638 19:23:08.975030 0, 0xFFFF, sum = 0
4639 19:23:08.978272 1, 0xFFFF, sum = 0
4640 19:23:08.978379 2, 0xFFFF, sum = 0
4641 19:23:08.981513 3, 0xFFFF, sum = 0
4642 19:23:08.981617 4, 0xFFFF, sum = 0
4643 19:23:08.985212 5, 0xFFFF, sum = 0
4644 19:23:08.985312 6, 0xFFFF, sum = 0
4645 19:23:08.988556 7, 0xFFFF, sum = 0
4646 19:23:08.988668 8, 0x0, sum = 1
4647 19:23:08.991759 9, 0x0, sum = 2
4648 19:23:08.991865 10, 0x0, sum = 3
4649 19:23:08.995057 11, 0x0, sum = 4
4650 19:23:08.995202 best_step = 9
4651 19:23:08.995363
4652 19:23:08.995472 ==
4653 19:23:08.998380 Dram Type= 6, Freq= 0, CH_1, rank 0
4654 19:23:09.001614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4655 19:23:09.001715 ==
4656 19:23:09.004892 RX Vref Scan: 1
4657 19:23:09.004992
4658 19:23:09.007864 RX Vref 0 -> 0, step: 1
4659 19:23:09.007959
4660 19:23:09.011108 RX Delay -179 -> 252, step: 8
4661 19:23:09.011202
4662 19:23:09.011289 Set Vref, RX VrefLevel [Byte0]: 49
4663 19:23:09.014804 [Byte1]: 53
4664 19:23:09.019578
4665 19:23:09.019682 Final RX Vref Byte 0 = 49 to rank0
4666 19:23:09.022617 Final RX Vref Byte 1 = 53 to rank0
4667 19:23:09.025772 Final RX Vref Byte 0 = 49 to rank1
4668 19:23:09.029547 Final RX Vref Byte 1 = 53 to rank1==
4669 19:23:09.032671 Dram Type= 6, Freq= 0, CH_1, rank 0
4670 19:23:09.039255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4671 19:23:09.039360 ==
4672 19:23:09.039460 DQS Delay:
4673 19:23:09.042462 DQS0 = 0, DQS1 = 0
4674 19:23:09.042561 DQM Delay:
4675 19:23:09.042698 DQM0 = 48, DQM1 = 38
4676 19:23:09.045544 DQ Delay:
4677 19:23:09.049238 DQ0 =56, DQ1 =40, DQ2 =40, DQ3 =44
4678 19:23:09.052634 DQ4 =44, DQ5 =60, DQ6 =56, DQ7 =44
4679 19:23:09.055926 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4680 19:23:09.058937 DQ12 =48, DQ13 =44, DQ14 =48, DQ15 =48
4681 19:23:09.059042
4682 19:23:09.059133
4683 19:23:09.065825 [DQSOSCAuto] RK0, (LSB)MR18= 0x4e33, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 395 ps
4684 19:23:09.069125 CH1 RK0: MR19=808, MR18=4E33
4685 19:23:09.075890 CH1_RK0: MR19=0x808, MR18=0x4E33, DQSOSC=395, MR23=63, INC=168, DEC=112
4686 19:23:09.075999
4687 19:23:09.079018 ----->DramcWriteLeveling(PI) begin...
4688 19:23:09.079121 ==
4689 19:23:09.082259 Dram Type= 6, Freq= 0, CH_1, rank 1
4690 19:23:09.085462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4691 19:23:09.085542 ==
4692 19:23:09.088552 Write leveling (Byte 0): 28 => 28
4693 19:23:09.091848 Write leveling (Byte 1): 28 => 28
4694 19:23:09.095162 DramcWriteLeveling(PI) end<-----
4695 19:23:09.095258
4696 19:23:09.095347 ==
4697 19:23:09.098594 Dram Type= 6, Freq= 0, CH_1, rank 1
4698 19:23:09.101818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4699 19:23:09.105146 ==
4700 19:23:09.105251 [Gating] SW mode calibration
4701 19:23:09.114766 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4702 19:23:09.118175 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4703 19:23:09.121357 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4704 19:23:09.128245 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4705 19:23:09.131578 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4706 19:23:09.134618 0 9 12 | B1->B0 | 3030 3333 | 0 1 | (0 1) (1 0)
4707 19:23:09.141454 0 9 16 | B1->B0 | 2424 2626 | 0 0 | (0 0) (0 0)
4708 19:23:09.144510 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4709 19:23:09.147595 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4710 19:23:09.154312 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4711 19:23:09.157677 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4712 19:23:09.160858 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4713 19:23:09.167241 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4714 19:23:09.170830 0 10 12 | B1->B0 | 3535 2929 | 0 0 | (0 0) (0 0)
4715 19:23:09.173917 0 10 16 | B1->B0 | 4646 3f3f | 0 0 | (0 0) (0 0)
4716 19:23:09.180455 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4717 19:23:09.184160 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4718 19:23:09.187461 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4719 19:23:09.193847 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4720 19:23:09.197172 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4721 19:23:09.200503 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4722 19:23:09.207306 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4723 19:23:09.210678 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4724 19:23:09.213931 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4725 19:23:09.220524 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4726 19:23:09.223776 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4727 19:23:09.226913 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4728 19:23:09.233483 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4729 19:23:09.237304 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4730 19:23:09.240353 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4731 19:23:09.247132 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4732 19:23:09.250360 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4733 19:23:09.253736 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4734 19:23:09.260039 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4735 19:23:09.263649 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4736 19:23:09.266466 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4737 19:23:09.273733 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4738 19:23:09.276740 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4739 19:23:09.279801 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4740 19:23:09.282978 Total UI for P1: 0, mck2ui 16
4741 19:23:09.286397 best dqsien dly found for B0: ( 0, 13, 14)
4742 19:23:09.289646 Total UI for P1: 0, mck2ui 16
4743 19:23:09.292819 best dqsien dly found for B1: ( 0, 13, 12)
4744 19:23:09.296653 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4745 19:23:09.303142 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4746 19:23:09.303219
4747 19:23:09.306486 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4748 19:23:09.309781 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4749 19:23:09.312425 [Gating] SW calibration Done
4750 19:23:09.312512 ==
4751 19:23:09.316357 Dram Type= 6, Freq= 0, CH_1, rank 1
4752 19:23:09.319512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4753 19:23:09.319603 ==
4754 19:23:09.322960 RX Vref Scan: 0
4755 19:23:09.323050
4756 19:23:09.323140 RX Vref 0 -> 0, step: 1
4757 19:23:09.323227
4758 19:23:09.326150 RX Delay -230 -> 252, step: 16
4759 19:23:09.329534 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4760 19:23:09.336163 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4761 19:23:09.338820 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4762 19:23:09.342153 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4763 19:23:09.345471 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4764 19:23:09.352251 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4765 19:23:09.355324 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4766 19:23:09.358916 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4767 19:23:09.361896 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4768 19:23:09.368327 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4769 19:23:09.371959 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4770 19:23:09.375521 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4771 19:23:09.378346 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4772 19:23:09.385021 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4773 19:23:09.388599 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4774 19:23:09.391480 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4775 19:23:09.391553 ==
4776 19:23:09.395239 Dram Type= 6, Freq= 0, CH_1, rank 1
4777 19:23:09.398305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4778 19:23:09.401594 ==
4779 19:23:09.401668 DQS Delay:
4780 19:23:09.401740 DQS0 = 0, DQS1 = 0
4781 19:23:09.405023 DQM Delay:
4782 19:23:09.405106 DQM0 = 44, DQM1 = 36
4783 19:23:09.408291 DQ Delay:
4784 19:23:09.410944 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4785 19:23:09.411041 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4786 19:23:09.414240 DQ8 =17, DQ9 =17, DQ10 =41, DQ11 =25
4787 19:23:09.420791 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4788 19:23:09.420900
4789 19:23:09.420991
4790 19:23:09.421077 ==
4791 19:23:09.424129 Dram Type= 6, Freq= 0, CH_1, rank 1
4792 19:23:09.427541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4793 19:23:09.427646 ==
4794 19:23:09.427736
4795 19:23:09.427823
4796 19:23:09.430664 TX Vref Scan disable
4797 19:23:09.430759 == TX Byte 0 ==
4798 19:23:09.437281 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4799 19:23:09.440582 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4800 19:23:09.440652 == TX Byte 1 ==
4801 19:23:09.447366 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4802 19:23:09.450559 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4803 19:23:09.450662 ==
4804 19:23:09.453767 Dram Type= 6, Freq= 0, CH_1, rank 1
4805 19:23:09.457219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4806 19:23:09.457342 ==
4807 19:23:09.460370
4808 19:23:09.460466
4809 19:23:09.460538 TX Vref Scan disable
4810 19:23:09.464070 == TX Byte 0 ==
4811 19:23:09.467669 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4812 19:23:09.473831 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4813 19:23:09.473933 == TX Byte 1 ==
4814 19:23:09.477074 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4815 19:23:09.483823 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4816 19:23:09.483958
4817 19:23:09.484083 [DATLAT]
4818 19:23:09.484202 Freq=600, CH1 RK1
4819 19:23:09.484323
4820 19:23:09.486963 DATLAT Default: 0x9
4821 19:23:09.490481 0, 0xFFFF, sum = 0
4822 19:23:09.490554 1, 0xFFFF, sum = 0
4823 19:23:09.493922 2, 0xFFFF, sum = 0
4824 19:23:09.494029 3, 0xFFFF, sum = 0
4825 19:23:09.497106 4, 0xFFFF, sum = 0
4826 19:23:09.497273 5, 0xFFFF, sum = 0
4827 19:23:09.500681 6, 0xFFFF, sum = 0
4828 19:23:09.500783 7, 0xFFFF, sum = 0
4829 19:23:09.503470 8, 0x0, sum = 1
4830 19:23:09.503577 9, 0x0, sum = 2
4831 19:23:09.506910 10, 0x0, sum = 3
4832 19:23:09.507020 11, 0x0, sum = 4
4833 19:23:09.507161 best_step = 9
4834 19:23:09.507285
4835 19:23:09.510495 ==
4836 19:23:09.510607 Dram Type= 6, Freq= 0, CH_1, rank 1
4837 19:23:09.516997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4838 19:23:09.517155 ==
4839 19:23:09.517320 RX Vref Scan: 0
4840 19:23:09.517465
4841 19:23:09.520397 RX Vref 0 -> 0, step: 1
4842 19:23:09.520510
4843 19:23:09.523558 RX Delay -195 -> 252, step: 8
4844 19:23:09.530011 iDelay=213, Bit 0, Center 48 (-99 ~ 196) 296
4845 19:23:09.533364 iDelay=213, Bit 1, Center 40 (-107 ~ 188) 296
4846 19:23:09.536737 iDelay=213, Bit 2, Center 32 (-115 ~ 180) 296
4847 19:23:09.540059 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4848 19:23:09.543287 iDelay=213, Bit 4, Center 44 (-107 ~ 196) 304
4849 19:23:09.549834 iDelay=213, Bit 5, Center 56 (-91 ~ 204) 296
4850 19:23:09.553087 iDelay=213, Bit 6, Center 60 (-91 ~ 212) 304
4851 19:23:09.556413 iDelay=213, Bit 7, Center 44 (-107 ~ 196) 304
4852 19:23:09.559764 iDelay=213, Bit 8, Center 24 (-131 ~ 180) 312
4853 19:23:09.566320 iDelay=213, Bit 9, Center 24 (-131 ~ 180) 312
4854 19:23:09.569500 iDelay=213, Bit 10, Center 36 (-115 ~ 188) 304
4855 19:23:09.572656 iDelay=213, Bit 11, Center 28 (-123 ~ 180) 304
4856 19:23:09.576300 iDelay=213, Bit 12, Center 48 (-107 ~ 204) 312
4857 19:23:09.582612 iDelay=213, Bit 13, Center 44 (-107 ~ 196) 304
4858 19:23:09.585746 iDelay=213, Bit 14, Center 44 (-107 ~ 196) 304
4859 19:23:09.589317 iDelay=213, Bit 15, Center 44 (-107 ~ 196) 304
4860 19:23:09.589448 ==
4861 19:23:09.592749 Dram Type= 6, Freq= 0, CH_1, rank 1
4862 19:23:09.595889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4863 19:23:09.599054 ==
4864 19:23:09.599122 DQS Delay:
4865 19:23:09.599180 DQS0 = 0, DQS1 = 0
4866 19:23:09.602202 DQM Delay:
4867 19:23:09.602273 DQM0 = 45, DQM1 = 36
4868 19:23:09.605632 DQ Delay:
4869 19:23:09.608642 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4870 19:23:09.608709 DQ4 =44, DQ5 =56, DQ6 =60, DQ7 =44
4871 19:23:09.612472 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =28
4872 19:23:09.615454 DQ12 =48, DQ13 =44, DQ14 =44, DQ15 =44
4873 19:23:09.618947
4874 19:23:09.619013
4875 19:23:09.625645 [DQSOSCAuto] RK1, (LSB)MR18= 0x291e, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 402 ps
4876 19:23:09.629053 CH1 RK1: MR19=808, MR18=291E
4877 19:23:09.635483 CH1_RK1: MR19=0x808, MR18=0x291E, DQSOSC=402, MR23=63, INC=162, DEC=108
4878 19:23:09.638800 [RxdqsGatingPostProcess] freq 600
4879 19:23:09.641974 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4880 19:23:09.645448 Pre-setting of DQS Precalculation
4881 19:23:09.651979 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4882 19:23:09.658516 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4883 19:23:09.665079 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4884 19:23:09.665154
4885 19:23:09.665242
4886 19:23:09.668374 [Calibration Summary] 1200 Mbps
4887 19:23:09.668473 CH 0, Rank 0
4888 19:23:09.671811 SW Impedance : PASS
4889 19:23:09.675021 DUTY Scan : NO K
4890 19:23:09.675125 ZQ Calibration : PASS
4891 19:23:09.678111 Jitter Meter : NO K
4892 19:23:09.681170 CBT Training : PASS
4893 19:23:09.681270 Write leveling : PASS
4894 19:23:09.684817 RX DQS gating : PASS
4895 19:23:09.688047 RX DQ/DQS(RDDQC) : PASS
4896 19:23:09.688164 TX DQ/DQS : PASS
4897 19:23:09.691186 RX DATLAT : PASS
4898 19:23:09.694752 RX DQ/DQS(Engine): PASS
4899 19:23:09.694822 TX OE : NO K
4900 19:23:09.697894 All Pass.
4901 19:23:09.697964
4902 19:23:09.698024 CH 0, Rank 1
4903 19:23:09.701265 SW Impedance : PASS
4904 19:23:09.701394 DUTY Scan : NO K
4905 19:23:09.704290 ZQ Calibration : PASS
4906 19:23:09.707539 Jitter Meter : NO K
4907 19:23:09.707669 CBT Training : PASS
4908 19:23:09.710738 Write leveling : PASS
4909 19:23:09.714642 RX DQS gating : PASS
4910 19:23:09.714741 RX DQ/DQS(RDDQC) : PASS
4911 19:23:09.717321 TX DQ/DQS : PASS
4912 19:23:09.720569 RX DATLAT : PASS
4913 19:23:09.720663 RX DQ/DQS(Engine): PASS
4914 19:23:09.724466 TX OE : NO K
4915 19:23:09.724574 All Pass.
4916 19:23:09.724676
4917 19:23:09.727573 CH 1, Rank 0
4918 19:23:09.727673 SW Impedance : PASS
4919 19:23:09.730482 DUTY Scan : NO K
4920 19:23:09.733879 ZQ Calibration : PASS
4921 19:23:09.733992 Jitter Meter : NO K
4922 19:23:09.737556 CBT Training : PASS
4923 19:23:09.737700 Write leveling : PASS
4924 19:23:09.740490 RX DQS gating : PASS
4925 19:23:09.743840 RX DQ/DQS(RDDQC) : PASS
4926 19:23:09.743955 TX DQ/DQS : PASS
4927 19:23:09.747109 RX DATLAT : PASS
4928 19:23:09.750323 RX DQ/DQS(Engine): PASS
4929 19:23:09.750458 TX OE : NO K
4930 19:23:09.753712 All Pass.
4931 19:23:09.753791
4932 19:23:09.753853 CH 1, Rank 1
4933 19:23:09.757073 SW Impedance : PASS
4934 19:23:09.757184 DUTY Scan : NO K
4935 19:23:09.760186 ZQ Calibration : PASS
4936 19:23:09.763475 Jitter Meter : NO K
4937 19:23:09.763549 CBT Training : PASS
4938 19:23:09.766901 Write leveling : PASS
4939 19:23:09.770128 RX DQS gating : PASS
4940 19:23:09.770210 RX DQ/DQS(RDDQC) : PASS
4941 19:23:09.773318 TX DQ/DQS : PASS
4942 19:23:09.776663 RX DATLAT : PASS
4943 19:23:09.776745 RX DQ/DQS(Engine): PASS
4944 19:23:09.779895 TX OE : NO K
4945 19:23:09.779977 All Pass.
4946 19:23:09.780042
4947 19:23:09.783046 DramC Write-DBI off
4948 19:23:09.786377 PER_BANK_REFRESH: Hybrid Mode
4949 19:23:09.786460 TX_TRACKING: ON
4950 19:23:09.796555 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4951 19:23:09.799787 [FAST_K] Save calibration result to emmc
4952 19:23:09.802818 dramc_set_vcore_voltage set vcore to 662500
4953 19:23:09.806485 Read voltage for 933, 3
4954 19:23:09.806567 Vio18 = 0
4955 19:23:09.806631 Vcore = 662500
4956 19:23:09.809439 Vdram = 0
4957 19:23:09.809522 Vddq = 0
4958 19:23:09.809586 Vmddr = 0
4959 19:23:09.816535 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4960 19:23:09.819348 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4961 19:23:09.822627 MEM_TYPE=3, freq_sel=17
4962 19:23:09.826030 sv_algorithm_assistance_LP4_1600
4963 19:23:09.829210 ============ PULL DRAM RESETB DOWN ============
4964 19:23:09.835833 ========== PULL DRAM RESETB DOWN end =========
4965 19:23:09.839334 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4966 19:23:09.842815 ===================================
4967 19:23:09.845960 LPDDR4 DRAM CONFIGURATION
4968 19:23:09.849501 ===================================
4969 19:23:09.849587 EX_ROW_EN[0] = 0x0
4970 19:23:09.852746 EX_ROW_EN[1] = 0x0
4971 19:23:09.852849 LP4Y_EN = 0x0
4972 19:23:09.855922 WORK_FSP = 0x0
4973 19:23:09.856030 WL = 0x3
4974 19:23:09.859295 RL = 0x3
4975 19:23:09.859394 BL = 0x2
4976 19:23:09.862389 RPST = 0x0
4977 19:23:09.862461 RD_PRE = 0x0
4978 19:23:09.865885 WR_PRE = 0x1
4979 19:23:09.869073 WR_PST = 0x0
4980 19:23:09.869176 DBI_WR = 0x0
4981 19:23:09.872328 DBI_RD = 0x0
4982 19:23:09.872425 OTF = 0x1
4983 19:23:09.875447 ===================================
4984 19:23:09.878856 ===================================
4985 19:23:09.878939 ANA top config
4986 19:23:09.882724 ===================================
4987 19:23:09.885849 DLL_ASYNC_EN = 0
4988 19:23:09.889041 ALL_SLAVE_EN = 1
4989 19:23:09.892234 NEW_RANK_MODE = 1
4990 19:23:09.895483 DLL_IDLE_MODE = 1
4991 19:23:09.895563 LP45_APHY_COMB_EN = 1
4992 19:23:09.898612 TX_ODT_DIS = 1
4993 19:23:09.902304 NEW_8X_MODE = 1
4994 19:23:09.905523 ===================================
4995 19:23:09.908587 ===================================
4996 19:23:09.911774 data_rate = 1866
4997 19:23:09.915484 CKR = 1
4998 19:23:09.918616 DQ_P2S_RATIO = 8
4999 19:23:09.922128 ===================================
5000 19:23:09.922209 CA_P2S_RATIO = 8
5001 19:23:09.925472 DQ_CA_OPEN = 0
5002 19:23:09.928673 DQ_SEMI_OPEN = 0
5003 19:23:09.931900 CA_SEMI_OPEN = 0
5004 19:23:09.935327 CA_FULL_RATE = 0
5005 19:23:09.938708 DQ_CKDIV4_EN = 1
5006 19:23:09.938789 CA_CKDIV4_EN = 1
5007 19:23:09.942018 CA_PREDIV_EN = 0
5008 19:23:09.945257 PH8_DLY = 0
5009 19:23:09.948239 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
5010 19:23:09.951560 DQ_AAMCK_DIV = 4
5011 19:23:09.954657 CA_AAMCK_DIV = 4
5012 19:23:09.954738 CA_ADMCK_DIV = 4
5013 19:23:09.958307 DQ_TRACK_CA_EN = 0
5014 19:23:09.961513 CA_PICK = 933
5015 19:23:09.964941 CA_MCKIO = 933
5016 19:23:09.968105 MCKIO_SEMI = 0
5017 19:23:09.971335 PLL_FREQ = 3732
5018 19:23:09.974879 DQ_UI_PI_RATIO = 32
5019 19:23:09.974961 CA_UI_PI_RATIO = 0
5020 19:23:09.977904 ===================================
5021 19:23:09.981173 ===================================
5022 19:23:09.984649 memory_type:LPDDR4
5023 19:23:09.987953 GP_NUM : 10
5024 19:23:09.988062 SRAM_EN : 1
5025 19:23:09.991005 MD32_EN : 0
5026 19:23:09.994344 ===================================
5027 19:23:09.997644 [ANA_INIT] >>>>>>>>>>>>>>
5028 19:23:10.000935 <<<<<< [CONFIGURE PHASE]: ANA_TX
5029 19:23:10.004235 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5030 19:23:10.007367 ===================================
5031 19:23:10.007465 data_rate = 1866,PCW = 0X8f00
5032 19:23:10.011142 ===================================
5033 19:23:10.017566 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5034 19:23:10.020955 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5035 19:23:10.027674 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5036 19:23:10.030737 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5037 19:23:10.033967 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5038 19:23:10.037350 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5039 19:23:10.040571 [ANA_INIT] flow start
5040 19:23:10.043819 [ANA_INIT] PLL >>>>>>>>
5041 19:23:10.043917 [ANA_INIT] PLL <<<<<<<<
5042 19:23:10.047151 [ANA_INIT] MIDPI >>>>>>>>
5043 19:23:10.050350 [ANA_INIT] MIDPI <<<<<<<<
5044 19:23:10.050427 [ANA_INIT] DLL >>>>>>>>
5045 19:23:10.053598 [ANA_INIT] flow end
5046 19:23:10.057242 ============ LP4 DIFF to SE enter ============
5047 19:23:10.063895 ============ LP4 DIFF to SE exit ============
5048 19:23:10.063978 [ANA_INIT] <<<<<<<<<<<<<
5049 19:23:10.067331 [Flow] Enable top DCM control >>>>>
5050 19:23:10.070574 [Flow] Enable top DCM control <<<<<
5051 19:23:10.073554 Enable DLL master slave shuffle
5052 19:23:10.080219 ==============================================================
5053 19:23:10.080302 Gating Mode config
5054 19:23:10.086688 ==============================================================
5055 19:23:10.089964 Config description:
5056 19:23:10.100173 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5057 19:23:10.106892 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5058 19:23:10.110219 SELPH_MODE 0: By rank 1: By Phase
5059 19:23:10.116506 ==============================================================
5060 19:23:10.119541 GAT_TRACK_EN = 1
5061 19:23:10.119622 RX_GATING_MODE = 2
5062 19:23:10.123233 RX_GATING_TRACK_MODE = 2
5063 19:23:10.126492 SELPH_MODE = 1
5064 19:23:10.129828 PICG_EARLY_EN = 1
5065 19:23:10.132976 VALID_LAT_VALUE = 1
5066 19:23:10.139540 ==============================================================
5067 19:23:10.142760 Enter into Gating configuration >>>>
5068 19:23:10.146091 Exit from Gating configuration <<<<
5069 19:23:10.149277 Enter into DVFS_PRE_config >>>>>
5070 19:23:10.159641 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5071 19:23:10.162656 Exit from DVFS_PRE_config <<<<<
5072 19:23:10.166345 Enter into PICG configuration >>>>
5073 19:23:10.169636 Exit from PICG configuration <<<<
5074 19:23:10.172956 [RX_INPUT] configuration >>>>>
5075 19:23:10.176183 [RX_INPUT] configuration <<<<<
5076 19:23:10.179503 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5077 19:23:10.185836 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5078 19:23:10.192763 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5079 19:23:10.199188 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5080 19:23:10.202417 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5081 19:23:10.209136 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5082 19:23:10.215792 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5083 19:23:10.219046 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5084 19:23:10.222292 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5085 19:23:10.225300 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5086 19:23:10.232165 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5087 19:23:10.235529 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5088 19:23:10.238741 ===================================
5089 19:23:10.241799 LPDDR4 DRAM CONFIGURATION
5090 19:23:10.245058 ===================================
5091 19:23:10.245165 EX_ROW_EN[0] = 0x0
5092 19:23:10.248628 EX_ROW_EN[1] = 0x0
5093 19:23:10.248698 LP4Y_EN = 0x0
5094 19:23:10.251933 WORK_FSP = 0x0
5095 19:23:10.252030 WL = 0x3
5096 19:23:10.255277 RL = 0x3
5097 19:23:10.255350 BL = 0x2
5098 19:23:10.258604 RPST = 0x0
5099 19:23:10.261801 RD_PRE = 0x0
5100 19:23:10.261875 WR_PRE = 0x1
5101 19:23:10.264994 WR_PST = 0x0
5102 19:23:10.265072 DBI_WR = 0x0
5103 19:23:10.268212 DBI_RD = 0x0
5104 19:23:10.268305 OTF = 0x1
5105 19:23:10.271147 ===================================
5106 19:23:10.275031 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5107 19:23:10.280950 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5108 19:23:10.284310 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5109 19:23:10.287565 ===================================
5110 19:23:10.290894 LPDDR4 DRAM CONFIGURATION
5111 19:23:10.294124 ===================================
5112 19:23:10.294217 EX_ROW_EN[0] = 0x10
5113 19:23:10.297953 EX_ROW_EN[1] = 0x0
5114 19:23:10.298024 LP4Y_EN = 0x0
5115 19:23:10.300915 WORK_FSP = 0x0
5116 19:23:10.300985 WL = 0x3
5117 19:23:10.304522 RL = 0x3
5118 19:23:10.307438 BL = 0x2
5119 19:23:10.307506 RPST = 0x0
5120 19:23:10.310725 RD_PRE = 0x0
5121 19:23:10.310794 WR_PRE = 0x1
5122 19:23:10.314327 WR_PST = 0x0
5123 19:23:10.314403 DBI_WR = 0x0
5124 19:23:10.317759 DBI_RD = 0x0
5125 19:23:10.317853 OTF = 0x1
5126 19:23:10.321109 ===================================
5127 19:23:10.327620 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5128 19:23:10.331283 nWR fixed to 30
5129 19:23:10.334706 [ModeRegInit_LP4] CH0 RK0
5130 19:23:10.334780 [ModeRegInit_LP4] CH0 RK1
5131 19:23:10.337775 [ModeRegInit_LP4] CH1 RK0
5132 19:23:10.341532 [ModeRegInit_LP4] CH1 RK1
5133 19:23:10.341609 match AC timing 9
5134 19:23:10.348003 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5135 19:23:10.351208 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5136 19:23:10.354345 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5137 19:23:10.361410 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5138 19:23:10.364707 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5139 19:23:10.364816 ==
5140 19:23:10.367900 Dram Type= 6, Freq= 0, CH_0, rank 0
5141 19:23:10.371072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5142 19:23:10.371159 ==
5143 19:23:10.377276 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5144 19:23:10.383960 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5145 19:23:10.387300 [CA 0] Center 37 (7~68) winsize 62
5146 19:23:10.390660 [CA 1] Center 37 (7~68) winsize 62
5147 19:23:10.393865 [CA 2] Center 35 (4~66) winsize 63
5148 19:23:10.397108 [CA 3] Center 34 (4~65) winsize 62
5149 19:23:10.400334 [CA 4] Center 33 (3~64) winsize 62
5150 19:23:10.403589 [CA 5] Center 33 (3~64) winsize 62
5151 19:23:10.403670
5152 19:23:10.407454 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5153 19:23:10.407562
5154 19:23:10.410560 [CATrainingPosCal] consider 1 rank data
5155 19:23:10.413847 u2DelayCellTimex100 = 270/100 ps
5156 19:23:10.416997 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5157 19:23:10.420632 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5158 19:23:10.423545 CA2 delay=35 (4~66),Diff = 2 PI (12 cell)
5159 19:23:10.427140 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5160 19:23:10.433459 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5161 19:23:10.437168 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5162 19:23:10.437284
5163 19:23:10.440392 CA PerBit enable=1, Macro0, CA PI delay=33
5164 19:23:10.440490
5165 19:23:10.443546 [CBTSetCACLKResult] CA Dly = 33
5166 19:23:10.443642 CS Dly: 7 (0~38)
5167 19:23:10.443730 ==
5168 19:23:10.447107 Dram Type= 6, Freq= 0, CH_0, rank 1
5169 19:23:10.453500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5170 19:23:10.453576 ==
5171 19:23:10.456738 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5172 19:23:10.463751 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5173 19:23:10.466767 [CA 0] Center 37 (7~68) winsize 62
5174 19:23:10.470063 [CA 1] Center 37 (7~68) winsize 62
5175 19:23:10.473304 [CA 2] Center 34 (4~65) winsize 62
5176 19:23:10.476503 [CA 3] Center 34 (4~65) winsize 62
5177 19:23:10.480095 [CA 4] Center 33 (3~64) winsize 62
5178 19:23:10.483412 [CA 5] Center 33 (3~63) winsize 61
5179 19:23:10.483493
5180 19:23:10.486660 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5181 19:23:10.486741
5182 19:23:10.490026 [CATrainingPosCal] consider 2 rank data
5183 19:23:10.493351 u2DelayCellTimex100 = 270/100 ps
5184 19:23:10.496447 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5185 19:23:10.499766 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5186 19:23:10.506273 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5187 19:23:10.509490 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5188 19:23:10.512782 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5189 19:23:10.516568 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5190 19:23:10.516648
5191 19:23:10.519842 CA PerBit enable=1, Macro0, CA PI delay=33
5192 19:23:10.519923
5193 19:23:10.522566 [CBTSetCACLKResult] CA Dly = 33
5194 19:23:10.522672 CS Dly: 7 (0~39)
5195 19:23:10.526491
5196 19:23:10.529912 ----->DramcWriteLeveling(PI) begin...
5197 19:23:10.529994 ==
5198 19:23:10.532893 Dram Type= 6, Freq= 0, CH_0, rank 0
5199 19:23:10.535956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5200 19:23:10.536038 ==
5201 19:23:10.539476 Write leveling (Byte 0): 32 => 32
5202 19:23:10.542876 Write leveling (Byte 1): 28 => 28
5203 19:23:10.545927 DramcWriteLeveling(PI) end<-----
5204 19:23:10.546008
5205 19:23:10.546071 ==
5206 19:23:10.548918 Dram Type= 6, Freq= 0, CH_0, rank 0
5207 19:23:10.552634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5208 19:23:10.552717 ==
5209 19:23:10.555701 [Gating] SW mode calibration
5210 19:23:10.562641 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5211 19:23:10.569113 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5212 19:23:10.572109 0 14 0 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
5213 19:23:10.575296 0 14 4 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
5214 19:23:10.581937 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5215 19:23:10.585113 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5216 19:23:10.588955 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5217 19:23:10.595481 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5218 19:23:10.598797 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5219 19:23:10.601500 0 14 28 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
5220 19:23:10.608673 0 15 0 | B1->B0 | 3131 2727 | 0 0 | (0 1) (1 0)
5221 19:23:10.611931 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5222 19:23:10.614711 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5223 19:23:10.621287 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5224 19:23:10.624562 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5225 19:23:10.627853 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5226 19:23:10.634563 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5227 19:23:10.637882 0 15 28 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
5228 19:23:10.641227 1 0 0 | B1->B0 | 3030 4545 | 0 0 | (1 1) (0 0)
5229 19:23:10.647803 1 0 4 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
5230 19:23:10.651159 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5231 19:23:10.654188 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5232 19:23:10.660765 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5233 19:23:10.663997 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5234 19:23:10.667480 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5235 19:23:10.674232 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5236 19:23:10.677178 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5237 19:23:10.680642 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5238 19:23:10.687208 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5239 19:23:10.690560 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5240 19:23:10.693769 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5241 19:23:10.700242 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5242 19:23:10.703525 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5243 19:23:10.706838 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5244 19:23:10.713530 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5245 19:23:10.716825 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5246 19:23:10.720005 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5247 19:23:10.726551 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5248 19:23:10.729895 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5249 19:23:10.733140 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5250 19:23:10.739777 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5251 19:23:10.743064 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5252 19:23:10.746339 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5253 19:23:10.749748 Total UI for P1: 0, mck2ui 16
5254 19:23:10.752972 best dqsien dly found for B0: ( 1, 2, 30)
5255 19:23:10.759549 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5256 19:23:10.762912 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5257 19:23:10.766168 Total UI for P1: 0, mck2ui 16
5258 19:23:10.769431 best dqsien dly found for B1: ( 1, 3, 2)
5259 19:23:10.773314 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5260 19:23:10.776509 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5261 19:23:10.776591
5262 19:23:10.779492 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5263 19:23:10.783224 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5264 19:23:10.785975 [Gating] SW calibration Done
5265 19:23:10.786048 ==
5266 19:23:10.789617 Dram Type= 6, Freq= 0, CH_0, rank 0
5267 19:23:10.796030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5268 19:23:10.796110 ==
5269 19:23:10.796179 RX Vref Scan: 0
5270 19:23:10.796239
5271 19:23:10.799320 RX Vref 0 -> 0, step: 1
5272 19:23:10.799398
5273 19:23:10.802872 RX Delay -80 -> 252, step: 8
5274 19:23:10.805670 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5275 19:23:10.809164 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5276 19:23:10.812649 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5277 19:23:10.815733 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5278 19:23:10.822209 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5279 19:23:10.825564 iDelay=208, Bit 5, Center 87 (-16 ~ 191) 208
5280 19:23:10.828700 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5281 19:23:10.832021 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5282 19:23:10.835294 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5283 19:23:10.841948 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5284 19:23:10.845322 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5285 19:23:10.848550 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5286 19:23:10.851949 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5287 19:23:10.855200 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5288 19:23:10.861776 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5289 19:23:10.865093 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5290 19:23:10.865216 ==
5291 19:23:10.868222 Dram Type= 6, Freq= 0, CH_0, rank 0
5292 19:23:10.871497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5293 19:23:10.871643 ==
5294 19:23:10.875158 DQS Delay:
5295 19:23:10.875295 DQS0 = 0, DQS1 = 0
5296 19:23:10.875410 DQM Delay:
5297 19:23:10.878529 DQM0 = 97, DQM1 = 85
5298 19:23:10.878647 DQ Delay:
5299 19:23:10.881936 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5300 19:23:10.885177 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5301 19:23:10.887917 DQ8 =79, DQ9 =75, DQ10 =91, DQ11 =79
5302 19:23:10.891615 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =91
5303 19:23:10.891758
5304 19:23:10.891860
5305 19:23:10.891953 ==
5306 19:23:10.894866 Dram Type= 6, Freq= 0, CH_0, rank 0
5307 19:23:10.901483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5308 19:23:10.901634 ==
5309 19:23:10.901703
5310 19:23:10.901766
5311 19:23:10.901825 TX Vref Scan disable
5312 19:23:10.904913 == TX Byte 0 ==
5313 19:23:10.908265 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5314 19:23:10.915220 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5315 19:23:10.915377 == TX Byte 1 ==
5316 19:23:10.918471 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5317 19:23:10.924902 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5318 19:23:10.924987 ==
5319 19:23:10.928306 Dram Type= 6, Freq= 0, CH_0, rank 0
5320 19:23:10.931170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5321 19:23:10.931287 ==
5322 19:23:10.931381
5323 19:23:10.931462
5324 19:23:10.934859 TX Vref Scan disable
5325 19:23:10.938044 == TX Byte 0 ==
5326 19:23:10.941641 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5327 19:23:10.944574 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5328 19:23:10.947987 == TX Byte 1 ==
5329 19:23:10.951201 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5330 19:23:10.954551 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5331 19:23:10.954686
5332 19:23:10.954784 [DATLAT]
5333 19:23:10.957839 Freq=933, CH0 RK0
5334 19:23:10.957939
5335 19:23:10.958029 DATLAT Default: 0xd
5336 19:23:10.961103 0, 0xFFFF, sum = 0
5337 19:23:10.964312 1, 0xFFFF, sum = 0
5338 19:23:10.964390 2, 0xFFFF, sum = 0
5339 19:23:10.967671 3, 0xFFFF, sum = 0
5340 19:23:10.967748 4, 0xFFFF, sum = 0
5341 19:23:10.970976 5, 0xFFFF, sum = 0
5342 19:23:10.971045 6, 0xFFFF, sum = 0
5343 19:23:10.974333 7, 0xFFFF, sum = 0
5344 19:23:10.974435 8, 0xFFFF, sum = 0
5345 19:23:10.977559 9, 0xFFFF, sum = 0
5346 19:23:10.977631 10, 0x0, sum = 1
5347 19:23:10.980825 11, 0x0, sum = 2
5348 19:23:10.980901 12, 0x0, sum = 3
5349 19:23:10.984183 13, 0x0, sum = 4
5350 19:23:10.984260 best_step = 11
5351 19:23:10.984328
5352 19:23:10.984386 ==
5353 19:23:10.987323 Dram Type= 6, Freq= 0, CH_0, rank 0
5354 19:23:10.990551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5355 19:23:10.993825 ==
5356 19:23:10.993893 RX Vref Scan: 1
5357 19:23:10.993960
5358 19:23:10.997155 RX Vref 0 -> 0, step: 1
5359 19:23:10.997252
5360 19:23:10.997352 RX Delay -61 -> 252, step: 4
5361 19:23:11.001112
5362 19:23:11.001189 Set Vref, RX VrefLevel [Byte0]: 59
5363 19:23:11.004227 [Byte1]: 49
5364 19:23:11.009075
5365 19:23:11.009143 Final RX Vref Byte 0 = 59 to rank0
5366 19:23:11.012060 Final RX Vref Byte 1 = 49 to rank0
5367 19:23:11.015664 Final RX Vref Byte 0 = 59 to rank1
5368 19:23:11.018669 Final RX Vref Byte 1 = 49 to rank1==
5369 19:23:11.022125 Dram Type= 6, Freq= 0, CH_0, rank 0
5370 19:23:11.028789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5371 19:23:11.028871 ==
5372 19:23:11.028936 DQS Delay:
5373 19:23:11.032145 DQS0 = 0, DQS1 = 0
5374 19:23:11.032214 DQM Delay:
5375 19:23:11.032274 DQM0 = 97, DQM1 = 84
5376 19:23:11.035332 DQ Delay:
5377 19:23:11.038586 DQ0 =94, DQ1 =98, DQ2 =94, DQ3 =94
5378 19:23:11.041786 DQ4 =98, DQ5 =88, DQ6 =106, DQ7 =106
5379 19:23:11.045358 DQ8 =76, DQ9 =72, DQ10 =86, DQ11 =80
5380 19:23:11.048267 DQ12 =88, DQ13 =88, DQ14 =96, DQ15 =90
5381 19:23:11.048340
5382 19:23:11.048406
5383 19:23:11.054979 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a11, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 408 ps
5384 19:23:11.058601 CH0 RK0: MR19=505, MR18=2A11
5385 19:23:11.064941 CH0_RK0: MR19=0x505, MR18=0x2A11, DQSOSC=408, MR23=63, INC=65, DEC=43
5386 19:23:11.065061
5387 19:23:11.068644 ----->DramcWriteLeveling(PI) begin...
5388 19:23:11.068746 ==
5389 19:23:11.071915 Dram Type= 6, Freq= 0, CH_0, rank 1
5390 19:23:11.075184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5391 19:23:11.075269 ==
5392 19:23:11.078645 Write leveling (Byte 0): 33 => 33
5393 19:23:11.081740 Write leveling (Byte 1): 32 => 32
5394 19:23:11.085016 DramcWriteLeveling(PI) end<-----
5395 19:23:11.085099
5396 19:23:11.085164 ==
5397 19:23:11.088183 Dram Type= 6, Freq= 0, CH_0, rank 1
5398 19:23:11.091551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5399 19:23:11.094880 ==
5400 19:23:11.094966 [Gating] SW mode calibration
5401 19:23:11.104797 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5402 19:23:11.108031 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5403 19:23:11.111755 0 14 0 | B1->B0 | 2a2a 3131 | 0 1 | (1 0) (1 1)
5404 19:23:11.118136 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5405 19:23:11.121401 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5406 19:23:11.124697 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5407 19:23:11.131005 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5408 19:23:11.134511 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5409 19:23:11.137993 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5410 19:23:11.144463 0 14 28 | B1->B0 | 3333 2f2f | 1 0 | (1 1) (0 0)
5411 19:23:11.147666 0 15 0 | B1->B0 | 3030 2727 | 0 0 | (0 1) (0 0)
5412 19:23:11.151059 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5413 19:23:11.157538 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5414 19:23:11.161177 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5415 19:23:11.164293 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5416 19:23:11.170780 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5417 19:23:11.174032 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5418 19:23:11.177439 0 15 28 | B1->B0 | 2525 3838 | 0 0 | (0 0) (0 0)
5419 19:23:11.183966 1 0 0 | B1->B0 | 3f3f 4545 | 0 0 | (0 0) (0 0)
5420 19:23:11.187120 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5421 19:23:11.190577 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5422 19:23:11.196939 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5423 19:23:11.200309 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5424 19:23:11.203614 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5425 19:23:11.210147 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5426 19:23:11.213322 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5427 19:23:11.217107 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5428 19:23:11.223468 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5429 19:23:11.226780 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5430 19:23:11.230000 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5431 19:23:11.236482 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5432 19:23:11.239704 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5433 19:23:11.243294 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5434 19:23:11.249235 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5435 19:23:11.252845 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5436 19:23:11.256189 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5437 19:23:11.262937 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5438 19:23:11.266282 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5439 19:23:11.269623 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5440 19:23:11.276056 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5441 19:23:11.278818 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5442 19:23:11.282611 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5443 19:23:11.289295 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5444 19:23:11.292315 Total UI for P1: 0, mck2ui 16
5445 19:23:11.295310 best dqsien dly found for B0: ( 1, 2, 28)
5446 19:23:11.298931 Total UI for P1: 0, mck2ui 16
5447 19:23:11.302299 best dqsien dly found for B1: ( 1, 2, 28)
5448 19:23:11.305692 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5449 19:23:11.308927 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5450 19:23:11.309026
5451 19:23:11.312215 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5452 19:23:11.315736 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5453 19:23:11.318688 [Gating] SW calibration Done
5454 19:23:11.318785 ==
5455 19:23:11.321889 Dram Type= 6, Freq= 0, CH_0, rank 1
5456 19:23:11.325257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5457 19:23:11.325396 ==
5458 19:23:11.328433 RX Vref Scan: 0
5459 19:23:11.328508
5460 19:23:11.331763 RX Vref 0 -> 0, step: 1
5461 19:23:11.331864
5462 19:23:11.331953 RX Delay -80 -> 252, step: 8
5463 19:23:11.338554 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5464 19:23:11.341737 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5465 19:23:11.345139 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5466 19:23:11.348327 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5467 19:23:11.351906 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5468 19:23:11.355173 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5469 19:23:11.361718 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5470 19:23:11.365114 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5471 19:23:11.368408 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5472 19:23:11.371582 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5473 19:23:11.374921 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5474 19:23:11.381355 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5475 19:23:11.384684 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5476 19:23:11.387994 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5477 19:23:11.391240 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5478 19:23:11.394845 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5479 19:23:11.398091 ==
5480 19:23:11.401474 Dram Type= 6, Freq= 0, CH_0, rank 1
5481 19:23:11.404494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5482 19:23:11.404576 ==
5483 19:23:11.404669 DQS Delay:
5484 19:23:11.407809 DQS0 = 0, DQS1 = 0
5485 19:23:11.407890 DQM Delay:
5486 19:23:11.410704 DQM0 = 97, DQM1 = 86
5487 19:23:11.410786 DQ Delay:
5488 19:23:11.414293 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5489 19:23:11.417746 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5490 19:23:11.421134 DQ8 =79, DQ9 =75, DQ10 =91, DQ11 =79
5491 19:23:11.424122 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =91
5492 19:23:11.424204
5493 19:23:11.424267
5494 19:23:11.424326 ==
5495 19:23:11.427748 Dram Type= 6, Freq= 0, CH_0, rank 1
5496 19:23:11.430866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5497 19:23:11.430975 ==
5498 19:23:11.431067
5499 19:23:11.434129
5500 19:23:11.434210 TX Vref Scan disable
5501 19:23:11.437425 == TX Byte 0 ==
5502 19:23:11.440642 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5503 19:23:11.443975 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5504 19:23:11.447185 == TX Byte 1 ==
5505 19:23:11.450636 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5506 19:23:11.453803 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5507 19:23:11.453885 ==
5508 19:23:11.456945 Dram Type= 6, Freq= 0, CH_0, rank 1
5509 19:23:11.463651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5510 19:23:11.463757 ==
5511 19:23:11.463838
5512 19:23:11.463898
5513 19:23:11.466784 TX Vref Scan disable
5514 19:23:11.466866 == TX Byte 0 ==
5515 19:23:11.473734 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5516 19:23:11.476989 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5517 19:23:11.477071 == TX Byte 1 ==
5518 19:23:11.483598 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5519 19:23:11.486704 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5520 19:23:11.486785
5521 19:23:11.486850 [DATLAT]
5522 19:23:11.490183 Freq=933, CH0 RK1
5523 19:23:11.490264
5524 19:23:11.490333 DATLAT Default: 0xb
5525 19:23:11.493286 0, 0xFFFF, sum = 0
5526 19:23:11.493415 1, 0xFFFF, sum = 0
5527 19:23:11.496553 2, 0xFFFF, sum = 0
5528 19:23:11.496635 3, 0xFFFF, sum = 0
5529 19:23:11.499710 4, 0xFFFF, sum = 0
5530 19:23:11.499794 5, 0xFFFF, sum = 0
5531 19:23:11.502971 6, 0xFFFF, sum = 0
5532 19:23:11.503054 7, 0xFFFF, sum = 0
5533 19:23:11.506273 8, 0xFFFF, sum = 0
5534 19:23:11.509706 9, 0xFFFF, sum = 0
5535 19:23:11.509789 10, 0x0, sum = 1
5536 19:23:11.509855 11, 0x0, sum = 2
5537 19:23:11.512857 12, 0x0, sum = 3
5538 19:23:11.512944 13, 0x0, sum = 4
5539 19:23:11.516951 best_step = 11
5540 19:23:11.517032
5541 19:23:11.517097 ==
5542 19:23:11.520162 Dram Type= 6, Freq= 0, CH_0, rank 1
5543 19:23:11.523176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5544 19:23:11.523257 ==
5545 19:23:11.526212 RX Vref Scan: 0
5546 19:23:11.526293
5547 19:23:11.526358 RX Vref 0 -> 0, step: 1
5548 19:23:11.526418
5549 19:23:11.529753 RX Delay -69 -> 252, step: 4
5550 19:23:11.536839 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5551 19:23:11.540576 iDelay=203, Bit 1, Center 96 (-1 ~ 194) 196
5552 19:23:11.543560 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5553 19:23:11.547022 iDelay=203, Bit 3, Center 94 (-1 ~ 190) 192
5554 19:23:11.550075 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5555 19:23:11.553435 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5556 19:23:11.559991 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5557 19:23:11.563345 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5558 19:23:11.566743 iDelay=203, Bit 8, Center 76 (-17 ~ 170) 188
5559 19:23:11.570083 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5560 19:23:11.576528 iDelay=203, Bit 10, Center 86 (-9 ~ 182) 192
5561 19:23:11.579674 iDelay=203, Bit 11, Center 76 (-17 ~ 170) 188
5562 19:23:11.583434 iDelay=203, Bit 12, Center 92 (-1 ~ 186) 188
5563 19:23:11.586771 iDelay=203, Bit 13, Center 90 (-5 ~ 186) 192
5564 19:23:11.589769 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5565 19:23:11.592966 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5566 19:23:11.596875 ==
5567 19:23:11.599552 Dram Type= 6, Freq= 0, CH_0, rank 1
5568 19:23:11.603265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5569 19:23:11.603372 ==
5570 19:23:11.603467 DQS Delay:
5571 19:23:11.606412 DQS0 = 0, DQS1 = 0
5572 19:23:11.606494 DQM Delay:
5573 19:23:11.609694 DQM0 = 95, DQM1 = 85
5574 19:23:11.609775 DQ Delay:
5575 19:23:11.612907 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =94
5576 19:23:11.616190 DQ4 =96, DQ5 =86, DQ6 =104, DQ7 =104
5577 19:23:11.619479 DQ8 =76, DQ9 =74, DQ10 =86, DQ11 =76
5578 19:23:11.622692 DQ12 =92, DQ13 =90, DQ14 =96, DQ15 =92
5579 19:23:11.622773
5580 19:23:11.622837
5581 19:23:11.629469 [DQSOSCAuto] RK1, (LSB)MR18= 0x28f8, (MSB)MR19= 0x504, tDQSOscB0 = 424 ps tDQSOscB1 = 409 ps
5582 19:23:11.632705 CH0 RK1: MR19=504, MR18=28F8
5583 19:23:11.639654 CH0_RK1: MR19=0x504, MR18=0x28F8, DQSOSC=409, MR23=63, INC=64, DEC=43
5584 19:23:11.642661 [RxdqsGatingPostProcess] freq 933
5585 19:23:11.649117 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5586 19:23:11.652487 best DQS0 dly(2T, 0.5T) = (0, 10)
5587 19:23:11.655916 best DQS1 dly(2T, 0.5T) = (0, 11)
5588 19:23:11.659331 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5589 19:23:11.662375 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5590 19:23:11.662500 best DQS0 dly(2T, 0.5T) = (0, 10)
5591 19:23:11.665655 best DQS1 dly(2T, 0.5T) = (0, 10)
5592 19:23:11.669291 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5593 19:23:11.672500 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5594 19:23:11.675876 Pre-setting of DQS Precalculation
5595 19:23:11.682542 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5596 19:23:11.682639 ==
5597 19:23:11.685783 Dram Type= 6, Freq= 0, CH_1, rank 0
5598 19:23:11.688911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5599 19:23:11.688996 ==
5600 19:23:11.695793 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5601 19:23:11.702358 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5602 19:23:11.705717 [CA 0] Center 36 (6~67) winsize 62
5603 19:23:11.708921 [CA 1] Center 37 (7~68) winsize 62
5604 19:23:11.711946 [CA 2] Center 34 (4~65) winsize 62
5605 19:23:11.715077 [CA 3] Center 33 (3~64) winsize 62
5606 19:23:11.718423 [CA 4] Center 34 (4~64) winsize 61
5607 19:23:11.721638 [CA 5] Center 33 (3~64) winsize 62
5608 19:23:11.721731
5609 19:23:11.724971 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5610 19:23:11.725071
5611 19:23:11.728264 [CATrainingPosCal] consider 1 rank data
5612 19:23:11.731661 u2DelayCellTimex100 = 270/100 ps
5613 19:23:11.734928 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5614 19:23:11.738071 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5615 19:23:11.741301 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5616 19:23:11.745138 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5617 19:23:11.747784 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5618 19:23:11.751132 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5619 19:23:11.751216
5620 19:23:11.757696 CA PerBit enable=1, Macro0, CA PI delay=33
5621 19:23:11.757793
5622 19:23:11.760903 [CBTSetCACLKResult] CA Dly = 33
5623 19:23:11.760987 CS Dly: 6 (0~37)
5624 19:23:11.761053 ==
5625 19:23:11.764741 Dram Type= 6, Freq= 0, CH_1, rank 1
5626 19:23:11.767872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5627 19:23:11.767957 ==
5628 19:23:11.774554 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5629 19:23:11.780968 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5630 19:23:11.784583 [CA 0] Center 36 (6~67) winsize 62
5631 19:23:11.787307 [CA 1] Center 37 (7~67) winsize 61
5632 19:23:11.791028 [CA 2] Center 34 (4~65) winsize 62
5633 19:23:11.794413 [CA 3] Center 33 (3~64) winsize 62
5634 19:23:11.797855 [CA 4] Center 34 (3~65) winsize 63
5635 19:23:11.801119 [CA 5] Center 33 (3~64) winsize 62
5636 19:23:11.801206
5637 19:23:11.804313 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5638 19:23:11.804399
5639 19:23:11.807246 [CATrainingPosCal] consider 2 rank data
5640 19:23:11.810797 u2DelayCellTimex100 = 270/100 ps
5641 19:23:11.813796 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5642 19:23:11.817095 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5643 19:23:11.820821 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5644 19:23:11.823891 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5645 19:23:11.830486 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5646 19:23:11.833870 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5647 19:23:11.833954
5648 19:23:11.837126 CA PerBit enable=1, Macro0, CA PI delay=33
5649 19:23:11.837211
5650 19:23:11.840417 [CBTSetCACLKResult] CA Dly = 33
5651 19:23:11.840500 CS Dly: 7 (0~39)
5652 19:23:11.840566
5653 19:23:11.843650 ----->DramcWriteLeveling(PI) begin...
5654 19:23:11.843735 ==
5655 19:23:11.846906 Dram Type= 6, Freq= 0, CH_1, rank 0
5656 19:23:11.853591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5657 19:23:11.853675 ==
5658 19:23:11.856827 Write leveling (Byte 0): 27 => 27
5659 19:23:11.860098 Write leveling (Byte 1): 28 => 28
5660 19:23:11.860181 DramcWriteLeveling(PI) end<-----
5661 19:23:11.863459
5662 19:23:11.863540 ==
5663 19:23:11.866757 Dram Type= 6, Freq= 0, CH_1, rank 0
5664 19:23:11.870357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5665 19:23:11.870439 ==
5666 19:23:11.873701 [Gating] SW mode calibration
5667 19:23:11.880006 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5668 19:23:11.883231 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5669 19:23:11.889621 0 14 0 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
5670 19:23:11.893296 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5671 19:23:11.896905 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5672 19:23:11.903490 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5673 19:23:11.906833 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5674 19:23:11.909481 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5675 19:23:11.916019 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
5676 19:23:11.919740 0 14 28 | B1->B0 | 2f2f 2f2f | 0 0 | (0 0) (0 0)
5677 19:23:11.922628 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5678 19:23:11.929140 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5679 19:23:11.932847 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5680 19:23:11.936246 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5681 19:23:11.942855 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5682 19:23:11.946033 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5683 19:23:11.949206 0 15 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
5684 19:23:11.955811 0 15 28 | B1->B0 | 3232 3e3e | 0 0 | (0 0) (0 0)
5685 19:23:11.959103 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5686 19:23:11.962174 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5687 19:23:11.968778 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5688 19:23:11.971965 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5689 19:23:11.979015 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5690 19:23:11.982351 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5691 19:23:11.985576 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5692 19:23:11.992120 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5693 19:23:11.995219 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5694 19:23:11.998855 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5695 19:23:12.001727 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5696 19:23:12.008893 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5697 19:23:12.011665 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5698 19:23:12.014885 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5699 19:23:12.021590 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5700 19:23:12.024860 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5701 19:23:12.028241 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5702 19:23:12.034862 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5703 19:23:12.038254 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5704 19:23:12.041164 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5705 19:23:12.048184 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5706 19:23:12.051476 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5707 19:23:12.054741 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5708 19:23:12.061180 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5709 19:23:12.064597 Total UI for P1: 0, mck2ui 16
5710 19:23:12.067877 best dqsien dly found for B0: ( 1, 2, 22)
5711 19:23:12.071036 Total UI for P1: 0, mck2ui 16
5712 19:23:12.074289 best dqsien dly found for B1: ( 1, 2, 26)
5713 19:23:12.077463 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5714 19:23:12.080667 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5715 19:23:12.080774
5716 19:23:12.083842 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5717 19:23:12.087791 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5718 19:23:12.091124 [Gating] SW calibration Done
5719 19:23:12.091224 ==
5720 19:23:12.094345 Dram Type= 6, Freq= 0, CH_1, rank 0
5721 19:23:12.097149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5722 19:23:12.097249 ==
5723 19:23:12.100999 RX Vref Scan: 0
5724 19:23:12.101096
5725 19:23:12.104285 RX Vref 0 -> 0, step: 1
5726 19:23:12.104388
5727 19:23:12.104479 RX Delay -80 -> 252, step: 8
5728 19:23:12.110857 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5729 19:23:12.113870 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5730 19:23:12.117470 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5731 19:23:12.120556 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5732 19:23:12.123729 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5733 19:23:12.127591 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5734 19:23:12.134154 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5735 19:23:12.137477 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5736 19:23:12.140447 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5737 19:23:12.143666 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5738 19:23:12.147356 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5739 19:23:12.153632 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5740 19:23:12.156939 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5741 19:23:12.160461 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5742 19:23:12.163602 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5743 19:23:12.166830 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5744 19:23:12.166935 ==
5745 19:23:12.170183 Dram Type= 6, Freq= 0, CH_1, rank 0
5746 19:23:12.176845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5747 19:23:12.176953 ==
5748 19:23:12.177045 DQS Delay:
5749 19:23:12.179925 DQS0 = 0, DQS1 = 0
5750 19:23:12.180027 DQM Delay:
5751 19:23:12.183036 DQM0 = 101, DQM1 = 91
5752 19:23:12.183137 DQ Delay:
5753 19:23:12.186171 DQ0 =103, DQ1 =99, DQ2 =95, DQ3 =99
5754 19:23:12.190080 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5755 19:23:12.193268 DQ8 =79, DQ9 =83, DQ10 =91, DQ11 =79
5756 19:23:12.196601 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5757 19:23:12.196706
5758 19:23:12.196796
5759 19:23:12.196883 ==
5760 19:23:12.199857 Dram Type= 6, Freq= 0, CH_1, rank 0
5761 19:23:12.203098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5762 19:23:12.203196 ==
5763 19:23:12.203287
5764 19:23:12.203378
5765 19:23:12.206495 TX Vref Scan disable
5766 19:23:12.209749 == TX Byte 0 ==
5767 19:23:12.212943 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5768 19:23:12.215996 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5769 19:23:12.219287 == TX Byte 1 ==
5770 19:23:12.222540 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5771 19:23:12.226421 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5772 19:23:12.226496 ==
5773 19:23:12.229421 Dram Type= 6, Freq= 0, CH_1, rank 0
5774 19:23:12.235756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5775 19:23:12.235858 ==
5776 19:23:12.235951
5777 19:23:12.236038
5778 19:23:12.236129 TX Vref Scan disable
5779 19:23:12.240245 == TX Byte 0 ==
5780 19:23:12.243507 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5781 19:23:12.250092 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5782 19:23:12.250191 == TX Byte 1 ==
5783 19:23:12.253459 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5784 19:23:12.259619 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5785 19:23:12.259723
5786 19:23:12.259813 [DATLAT]
5787 19:23:12.259902 Freq=933, CH1 RK0
5788 19:23:12.259990
5789 19:23:12.263144 DATLAT Default: 0xd
5790 19:23:12.263227 0, 0xFFFF, sum = 0
5791 19:23:12.266242 1, 0xFFFF, sum = 0
5792 19:23:12.269690 2, 0xFFFF, sum = 0
5793 19:23:12.269767 3, 0xFFFF, sum = 0
5794 19:23:12.272958 4, 0xFFFF, sum = 0
5795 19:23:12.273031 5, 0xFFFF, sum = 0
5796 19:23:12.276135 6, 0xFFFF, sum = 0
5797 19:23:12.276207 7, 0xFFFF, sum = 0
5798 19:23:12.279769 8, 0xFFFF, sum = 0
5799 19:23:12.279853 9, 0xFFFF, sum = 0
5800 19:23:12.283057 10, 0x0, sum = 1
5801 19:23:12.283141 11, 0x0, sum = 2
5802 19:23:12.285923 12, 0x0, sum = 3
5803 19:23:12.286006 13, 0x0, sum = 4
5804 19:23:12.289194 best_step = 11
5805 19:23:12.289300
5806 19:23:12.289384 ==
5807 19:23:12.292921 Dram Type= 6, Freq= 0, CH_1, rank 0
5808 19:23:12.296209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5809 19:23:12.296292 ==
5810 19:23:12.296357 RX Vref Scan: 1
5811 19:23:12.299560
5812 19:23:12.299642 RX Vref 0 -> 0, step: 1
5813 19:23:12.299706
5814 19:23:12.302875 RX Delay -61 -> 252, step: 4
5815 19:23:12.302957
5816 19:23:12.305529 Set Vref, RX VrefLevel [Byte0]: 49
5817 19:23:12.308828 [Byte1]: 53
5818 19:23:12.312668
5819 19:23:12.312748 Final RX Vref Byte 0 = 49 to rank0
5820 19:23:12.316057 Final RX Vref Byte 1 = 53 to rank0
5821 19:23:12.319276 Final RX Vref Byte 0 = 49 to rank1
5822 19:23:12.322470 Final RX Vref Byte 1 = 53 to rank1==
5823 19:23:12.325810 Dram Type= 6, Freq= 0, CH_1, rank 0
5824 19:23:12.332320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5825 19:23:12.332420 ==
5826 19:23:12.332515 DQS Delay:
5827 19:23:12.335503 DQS0 = 0, DQS1 = 0
5828 19:23:12.335589 DQM Delay:
5829 19:23:12.335654 DQM0 = 100, DQM1 = 93
5830 19:23:12.339286 DQ Delay:
5831 19:23:12.342160 DQ0 =104, DQ1 =94, DQ2 =92, DQ3 =98
5832 19:23:12.345724 DQ4 =98, DQ5 =110, DQ6 =108, DQ7 =98
5833 19:23:12.349114 DQ8 =80, DQ9 =84, DQ10 =94, DQ11 =86
5834 19:23:12.352310 DQ12 =100, DQ13 =98, DQ14 =102, DQ15 =104
5835 19:23:12.352392
5836 19:23:12.352456
5837 19:23:12.358890 [DQSOSCAuto] RK0, (LSB)MR18= 0x1908, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 413 ps
5838 19:23:12.362123 CH1 RK0: MR19=505, MR18=1908
5839 19:23:12.368610 CH1_RK0: MR19=0x505, MR18=0x1908, DQSOSC=413, MR23=63, INC=63, DEC=42
5840 19:23:12.368692
5841 19:23:12.371794 ----->DramcWriteLeveling(PI) begin...
5842 19:23:12.371878 ==
5843 19:23:12.375588 Dram Type= 6, Freq= 0, CH_1, rank 1
5844 19:23:12.378650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5845 19:23:12.381631 ==
5846 19:23:12.381713 Write leveling (Byte 0): 25 => 25
5847 19:23:12.385206 Write leveling (Byte 1): 31 => 31
5848 19:23:12.388212 DramcWriteLeveling(PI) end<-----
5849 19:23:12.388294
5850 19:23:12.388358 ==
5851 19:23:12.391643 Dram Type= 6, Freq= 0, CH_1, rank 1
5852 19:23:12.398043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5853 19:23:12.398125 ==
5854 19:23:12.401861 [Gating] SW mode calibration
5855 19:23:12.407781 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5856 19:23:12.411127 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5857 19:23:12.417819 0 14 0 | B1->B0 | 3333 3333 | 1 1 | (1 1) (1 1)
5858 19:23:12.421075 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5859 19:23:12.424884 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5860 19:23:12.431229 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5861 19:23:12.434497 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5862 19:23:12.437797 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5863 19:23:12.444388 0 14 24 | B1->B0 | 3232 3434 | 1 1 | (1 0) (1 0)
5864 19:23:12.447556 0 14 28 | B1->B0 | 2c2c 2f2f | 1 1 | (1 0) (1 1)
5865 19:23:12.450753 0 15 0 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 0)
5866 19:23:12.457324 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5867 19:23:12.460718 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5868 19:23:12.464087 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5869 19:23:12.470459 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5870 19:23:12.473727 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5871 19:23:12.477557 0 15 24 | B1->B0 | 2524 2323 | 1 0 | (0 0) (0 0)
5872 19:23:12.483564 0 15 28 | B1->B0 | 3a3a 3131 | 0 1 | (1 1) (0 0)
5873 19:23:12.486772 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5874 19:23:12.490570 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5875 19:23:12.497002 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5876 19:23:12.500275 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5877 19:23:12.503985 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5878 19:23:12.510146 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5879 19:23:12.513737 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5880 19:23:12.516892 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5881 19:23:12.523653 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5882 19:23:12.526842 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5883 19:23:12.529896 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5884 19:23:12.536425 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5885 19:23:12.539805 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5886 19:23:12.543117 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5887 19:23:12.549586 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5888 19:23:12.552825 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5889 19:23:12.556050 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5890 19:23:12.563071 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5891 19:23:12.566346 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5892 19:23:12.569191 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5893 19:23:12.576165 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5894 19:23:12.579306 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5895 19:23:12.582885 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5896 19:23:12.589197 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5897 19:23:12.589305 Total UI for P1: 0, mck2ui 16
5898 19:23:12.595930 best dqsien dly found for B1: ( 1, 2, 24)
5899 19:23:12.599148 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5900 19:23:12.602403 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5901 19:23:12.605785 Total UI for P1: 0, mck2ui 16
5902 19:23:12.608989 best dqsien dly found for B0: ( 1, 2, 30)
5903 19:23:12.612172 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5904 19:23:12.615990 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5905 19:23:12.616087
5906 19:23:12.621869 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5907 19:23:12.625241 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5908 19:23:12.628864 [Gating] SW calibration Done
5909 19:23:12.628950 ==
5910 19:23:12.631709 Dram Type= 6, Freq= 0, CH_1, rank 1
5911 19:23:12.635500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5912 19:23:12.635583 ==
5913 19:23:12.635647 RX Vref Scan: 0
5914 19:23:12.635708
5915 19:23:12.638714 RX Vref 0 -> 0, step: 1
5916 19:23:12.638811
5917 19:23:12.642032 RX Delay -80 -> 252, step: 8
5918 19:23:12.645336 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5919 19:23:12.648419 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5920 19:23:12.655006 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5921 19:23:12.658437 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5922 19:23:12.661634 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5923 19:23:12.664836 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5924 19:23:12.668075 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5925 19:23:12.671474 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5926 19:23:12.677899 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5927 19:23:12.681583 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5928 19:23:12.684547 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5929 19:23:12.687631 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5930 19:23:12.690934 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5931 19:23:12.697639 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5932 19:23:12.701039 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5933 19:23:12.704004 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5934 19:23:12.704086 ==
5935 19:23:12.707828 Dram Type= 6, Freq= 0, CH_1, rank 1
5936 19:23:12.710557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5937 19:23:12.710654 ==
5938 19:23:12.714590 DQS Delay:
5939 19:23:12.714665 DQS0 = 0, DQS1 = 0
5940 19:23:12.717702 DQM Delay:
5941 19:23:12.717840 DQM0 = 99, DQM1 = 90
5942 19:23:12.717930 DQ Delay:
5943 19:23:12.720932 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =99
5944 19:23:12.724099 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5945 19:23:12.727355 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =83
5946 19:23:12.730690 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =99
5947 19:23:12.730834
5948 19:23:12.733666
5949 19:23:12.733788 ==
5950 19:23:12.737902 Dram Type= 6, Freq= 0, CH_1, rank 1
5951 19:23:12.740914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5952 19:23:12.741028 ==
5953 19:23:12.741093
5954 19:23:12.741152
5955 19:23:12.743753 TX Vref Scan disable
5956 19:23:12.743838 == TX Byte 0 ==
5957 19:23:12.750624 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5958 19:23:12.753809 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5959 19:23:12.753918 == TX Byte 1 ==
5960 19:23:12.759899 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5961 19:23:12.763862 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5962 19:23:12.763944 ==
5963 19:23:12.767071 Dram Type= 6, Freq= 0, CH_1, rank 1
5964 19:23:12.770531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5965 19:23:12.770613 ==
5966 19:23:12.770677
5967 19:23:12.770736
5968 19:23:12.773785 TX Vref Scan disable
5969 19:23:12.776969 == TX Byte 0 ==
5970 19:23:12.780382 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5971 19:23:12.783514 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5972 19:23:12.786572 == TX Byte 1 ==
5973 19:23:12.789931 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5974 19:23:12.793213 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5975 19:23:12.796452
5976 19:23:12.796532 [DATLAT]
5977 19:23:12.796596 Freq=933, CH1 RK1
5978 19:23:12.796657
5979 19:23:12.799440 DATLAT Default: 0xb
5980 19:23:12.799582 0, 0xFFFF, sum = 0
5981 19:23:12.803022 1, 0xFFFF, sum = 0
5982 19:23:12.803126 2, 0xFFFF, sum = 0
5983 19:23:12.806590 3, 0xFFFF, sum = 0
5984 19:23:12.806681 4, 0xFFFF, sum = 0
5985 19:23:12.809527 5, 0xFFFF, sum = 0
5986 19:23:12.812911 6, 0xFFFF, sum = 0
5987 19:23:12.813012 7, 0xFFFF, sum = 0
5988 19:23:12.816159 8, 0xFFFF, sum = 0
5989 19:23:12.816264 9, 0xFFFF, sum = 0
5990 19:23:12.819443 10, 0x0, sum = 1
5991 19:23:12.819594 11, 0x0, sum = 2
5992 19:23:12.822668 12, 0x0, sum = 3
5993 19:23:12.822746 13, 0x0, sum = 4
5994 19:23:12.822809 best_step = 11
5995 19:23:12.822867
5996 19:23:12.825928 ==
5997 19:23:12.829869 Dram Type= 6, Freq= 0, CH_1, rank 1
5998 19:23:12.833043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5999 19:23:12.833165 ==
6000 19:23:12.833231 RX Vref Scan: 0
6001 19:23:12.833292
6002 19:23:12.836269 RX Vref 0 -> 0, step: 1
6003 19:23:12.836371
6004 19:23:12.839414 RX Delay -69 -> 252, step: 4
6005 19:23:12.845983 iDelay=207, Bit 0, Center 106 (19 ~ 194) 176
6006 19:23:12.849042 iDelay=207, Bit 1, Center 94 (7 ~ 182) 176
6007 19:23:12.852267 iDelay=207, Bit 2, Center 90 (3 ~ 178) 176
6008 19:23:12.855778 iDelay=207, Bit 3, Center 98 (15 ~ 182) 168
6009 19:23:12.859203 iDelay=207, Bit 4, Center 100 (11 ~ 190) 180
6010 19:23:12.862517 iDelay=207, Bit 5, Center 110 (23 ~ 198) 176
6011 19:23:12.869070 iDelay=207, Bit 6, Center 114 (23 ~ 206) 184
6012 19:23:12.872268 iDelay=207, Bit 7, Center 98 (7 ~ 190) 184
6013 19:23:12.875658 iDelay=207, Bit 8, Center 82 (-9 ~ 174) 184
6014 19:23:12.878984 iDelay=207, Bit 9, Center 82 (-9 ~ 174) 184
6015 19:23:12.882242 iDelay=207, Bit 10, Center 94 (3 ~ 186) 184
6016 19:23:12.888636 iDelay=207, Bit 11, Center 86 (-1 ~ 174) 176
6017 19:23:12.891721 iDelay=207, Bit 12, Center 104 (15 ~ 194) 180
6018 19:23:12.895065 iDelay=207, Bit 13, Center 100 (11 ~ 190) 180
6019 19:23:12.898378 iDelay=207, Bit 14, Center 102 (15 ~ 190) 176
6020 19:23:12.901806 iDelay=207, Bit 15, Center 104 (15 ~ 194) 180
6021 19:23:12.904993 ==
6022 19:23:12.908328 Dram Type= 6, Freq= 0, CH_1, rank 1
6023 19:23:12.911546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6024 19:23:12.911627 ==
6025 19:23:12.911692 DQS Delay:
6026 19:23:12.914642 DQS0 = 0, DQS1 = 0
6027 19:23:12.914714 DQM Delay:
6028 19:23:12.918603 DQM0 = 101, DQM1 = 94
6029 19:23:12.918685 DQ Delay:
6030 19:23:12.921564 DQ0 =106, DQ1 =94, DQ2 =90, DQ3 =98
6031 19:23:12.925003 DQ4 =100, DQ5 =110, DQ6 =114, DQ7 =98
6032 19:23:12.927837 DQ8 =82, DQ9 =82, DQ10 =94, DQ11 =86
6033 19:23:12.931175 DQ12 =104, DQ13 =100, DQ14 =102, DQ15 =104
6034 19:23:12.931287
6035 19:23:12.931352
6036 19:23:12.941246 [DQSOSCAuto] RK1, (LSB)MR18= 0x902, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 419 ps
6037 19:23:12.941379 CH1 RK1: MR19=505, MR18=902
6038 19:23:12.948002 CH1_RK1: MR19=0x505, MR18=0x902, DQSOSC=419, MR23=63, INC=61, DEC=41
6039 19:23:12.951258 [RxdqsGatingPostProcess] freq 933
6040 19:23:12.957732 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6041 19:23:12.961078 best DQS0 dly(2T, 0.5T) = (0, 10)
6042 19:23:12.964587 best DQS1 dly(2T, 0.5T) = (0, 10)
6043 19:23:12.967856 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6044 19:23:12.970883 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6045 19:23:12.973908 best DQS0 dly(2T, 0.5T) = (0, 10)
6046 19:23:12.977258 best DQS1 dly(2T, 0.5T) = (0, 10)
6047 19:23:12.980818 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6048 19:23:12.980902 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6049 19:23:12.983975 Pre-setting of DQS Precalculation
6050 19:23:12.990574 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6051 19:23:12.997051 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6052 19:23:13.003627 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6053 19:23:13.003712
6054 19:23:13.003779
6055 19:23:13.007013 [Calibration Summary] 1866 Mbps
6056 19:23:13.010122 CH 0, Rank 0
6057 19:23:13.010206 SW Impedance : PASS
6058 19:23:13.013333 DUTY Scan : NO K
6059 19:23:13.017155 ZQ Calibration : PASS
6060 19:23:13.017238 Jitter Meter : NO K
6061 19:23:13.020381 CBT Training : PASS
6062 19:23:13.023588 Write leveling : PASS
6063 19:23:13.023673 RX DQS gating : PASS
6064 19:23:13.026766 RX DQ/DQS(RDDQC) : PASS
6065 19:23:13.029920 TX DQ/DQS : PASS
6066 19:23:13.030001 RX DATLAT : PASS
6067 19:23:13.033262 RX DQ/DQS(Engine): PASS
6068 19:23:13.036348 TX OE : NO K
6069 19:23:13.036447 All Pass.
6070 19:23:13.036536
6071 19:23:13.036618 CH 0, Rank 1
6072 19:23:13.039530 SW Impedance : PASS
6073 19:23:13.043073 DUTY Scan : NO K
6074 19:23:13.043148 ZQ Calibration : PASS
6075 19:23:13.046616 Jitter Meter : NO K
6076 19:23:13.046689 CBT Training : PASS
6077 19:23:13.049669 Write leveling : PASS
6078 19:23:13.053551 RX DQS gating : PASS
6079 19:23:13.053651 RX DQ/DQS(RDDQC) : PASS
6080 19:23:13.056096 TX DQ/DQS : PASS
6081 19:23:13.060052 RX DATLAT : PASS
6082 19:23:13.060154 RX DQ/DQS(Engine): PASS
6083 19:23:13.062677 TX OE : NO K
6084 19:23:13.062748 All Pass.
6085 19:23:13.062811
6086 19:23:13.066013 CH 1, Rank 0
6087 19:23:13.066085 SW Impedance : PASS
6088 19:23:13.069256 DUTY Scan : NO K
6089 19:23:13.072560 ZQ Calibration : PASS
6090 19:23:13.072632 Jitter Meter : NO K
6091 19:23:13.075814 CBT Training : PASS
6092 19:23:13.079176 Write leveling : PASS
6093 19:23:13.079277 RX DQS gating : PASS
6094 19:23:13.082409 RX DQ/DQS(RDDQC) : PASS
6095 19:23:13.086077 TX DQ/DQS : PASS
6096 19:23:13.086151 RX DATLAT : PASS
6097 19:23:13.089093 RX DQ/DQS(Engine): PASS
6098 19:23:13.092484 TX OE : NO K
6099 19:23:13.092573 All Pass.
6100 19:23:13.092634
6101 19:23:13.092691 CH 1, Rank 1
6102 19:23:13.095691 SW Impedance : PASS
6103 19:23:13.099465 DUTY Scan : NO K
6104 19:23:13.099572 ZQ Calibration : PASS
6105 19:23:13.102684 Jitter Meter : NO K
6106 19:23:13.106001 CBT Training : PASS
6107 19:23:13.106082 Write leveling : PASS
6108 19:23:13.109523 RX DQS gating : PASS
6109 19:23:13.112666 RX DQ/DQS(RDDQC) : PASS
6110 19:23:13.112742 TX DQ/DQS : PASS
6111 19:23:13.115828 RX DATLAT : PASS
6112 19:23:13.115901 RX DQ/DQS(Engine): PASS
6113 19:23:13.118993 TX OE : NO K
6114 19:23:13.119066 All Pass.
6115 19:23:13.119128
6116 19:23:13.122346 DramC Write-DBI off
6117 19:23:13.125748 PER_BANK_REFRESH: Hybrid Mode
6118 19:23:13.125831 TX_TRACKING: ON
6119 19:23:13.135466 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6120 19:23:13.138665 [FAST_K] Save calibration result to emmc
6121 19:23:13.142040 dramc_set_vcore_voltage set vcore to 650000
6122 19:23:13.145284 Read voltage for 400, 6
6123 19:23:13.145383 Vio18 = 0
6124 19:23:13.148430 Vcore = 650000
6125 19:23:13.148513 Vdram = 0
6126 19:23:13.148579 Vddq = 0
6127 19:23:13.148640 Vmddr = 0
6128 19:23:13.155482 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6129 19:23:13.161477 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6130 19:23:13.161561 MEM_TYPE=3, freq_sel=20
6131 19:23:13.164718 sv_algorithm_assistance_LP4_800
6132 19:23:13.168427 ============ PULL DRAM RESETB DOWN ============
6133 19:23:13.174938 ========== PULL DRAM RESETB DOWN end =========
6134 19:23:13.178203 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6135 19:23:13.181369 ===================================
6136 19:23:13.184690 LPDDR4 DRAM CONFIGURATION
6137 19:23:13.187935 ===================================
6138 19:23:13.188019 EX_ROW_EN[0] = 0x0
6139 19:23:13.191261 EX_ROW_EN[1] = 0x0
6140 19:23:13.194688 LP4Y_EN = 0x0
6141 19:23:13.194771 WORK_FSP = 0x0
6142 19:23:13.197971 WL = 0x2
6143 19:23:13.198059 RL = 0x2
6144 19:23:13.201058 BL = 0x2
6145 19:23:13.201141 RPST = 0x0
6146 19:23:13.204860 RD_PRE = 0x0
6147 19:23:13.204944 WR_PRE = 0x1
6148 19:23:13.207600 WR_PST = 0x0
6149 19:23:13.207684 DBI_WR = 0x0
6150 19:23:13.211030 DBI_RD = 0x0
6151 19:23:13.211114 OTF = 0x1
6152 19:23:13.214615 ===================================
6153 19:23:13.217506 ===================================
6154 19:23:13.220789 ANA top config
6155 19:23:13.224470 ===================================
6156 19:23:13.227649 DLL_ASYNC_EN = 0
6157 19:23:13.227757 ALL_SLAVE_EN = 1
6158 19:23:13.230910 NEW_RANK_MODE = 1
6159 19:23:13.234159 DLL_IDLE_MODE = 1
6160 19:23:13.237568 LP45_APHY_COMB_EN = 1
6161 19:23:13.237652 TX_ODT_DIS = 1
6162 19:23:13.240624 NEW_8X_MODE = 1
6163 19:23:13.244042 ===================================
6164 19:23:13.247362 ===================================
6165 19:23:13.250596 data_rate = 800
6166 19:23:13.253940 CKR = 1
6167 19:23:13.257040 DQ_P2S_RATIO = 4
6168 19:23:13.260828 ===================================
6169 19:23:13.263629 CA_P2S_RATIO = 4
6170 19:23:13.263735 DQ_CA_OPEN = 0
6171 19:23:13.267220 DQ_SEMI_OPEN = 1
6172 19:23:13.270836 CA_SEMI_OPEN = 1
6173 19:23:13.274062 CA_FULL_RATE = 0
6174 19:23:13.277084 DQ_CKDIV4_EN = 0
6175 19:23:13.280314 CA_CKDIV4_EN = 1
6176 19:23:13.280400 CA_PREDIV_EN = 0
6177 19:23:13.283529 PH8_DLY = 0
6178 19:23:13.286871 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6179 19:23:13.290142 DQ_AAMCK_DIV = 0
6180 19:23:13.294016 CA_AAMCK_DIV = 0
6181 19:23:13.297211 CA_ADMCK_DIV = 4
6182 19:23:13.297318 DQ_TRACK_CA_EN = 0
6183 19:23:13.299900 CA_PICK = 800
6184 19:23:13.303188 CA_MCKIO = 400
6185 19:23:13.306488 MCKIO_SEMI = 400
6186 19:23:13.310335 PLL_FREQ = 3016
6187 19:23:13.313686 DQ_UI_PI_RATIO = 32
6188 19:23:13.316985 CA_UI_PI_RATIO = 32
6189 19:23:13.319989 ===================================
6190 19:23:13.322976 ===================================
6191 19:23:13.326503 memory_type:LPDDR4
6192 19:23:13.326584 GP_NUM : 10
6193 19:23:13.329877 SRAM_EN : 1
6194 19:23:13.329974 MD32_EN : 0
6195 19:23:13.333203 ===================================
6196 19:23:13.336060 [ANA_INIT] >>>>>>>>>>>>>>
6197 19:23:13.339590 <<<<<< [CONFIGURE PHASE]: ANA_TX
6198 19:23:13.342958 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6199 19:23:13.345967 ===================================
6200 19:23:13.349136 data_rate = 800,PCW = 0X7400
6201 19:23:13.352605 ===================================
6202 19:23:13.355810 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6203 19:23:13.362337 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6204 19:23:13.372622 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6205 19:23:13.375543 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6206 19:23:13.379228 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6207 19:23:13.385965 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6208 19:23:13.386050 [ANA_INIT] flow start
6209 19:23:13.389182 [ANA_INIT] PLL >>>>>>>>
6210 19:23:13.389265 [ANA_INIT] PLL <<<<<<<<
6211 19:23:13.392525 [ANA_INIT] MIDPI >>>>>>>>
6212 19:23:13.395811 [ANA_INIT] MIDPI <<<<<<<<
6213 19:23:13.399164 [ANA_INIT] DLL >>>>>>>>
6214 19:23:13.399247 [ANA_INIT] flow end
6215 19:23:13.401931 ============ LP4 DIFF to SE enter ============
6216 19:23:13.408568 ============ LP4 DIFF to SE exit ============
6217 19:23:13.408652 [ANA_INIT] <<<<<<<<<<<<<
6218 19:23:13.411907 [Flow] Enable top DCM control >>>>>
6219 19:23:13.415091 [Flow] Enable top DCM control <<<<<
6220 19:23:13.418447 Enable DLL master slave shuffle
6221 19:23:13.425019 ==============================================================
6222 19:23:13.428289 Gating Mode config
6223 19:23:13.431666 ==============================================================
6224 19:23:13.434975 Config description:
6225 19:23:13.444910 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6226 19:23:13.451645 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6227 19:23:13.455036 SELPH_MODE 0: By rank 1: By Phase
6228 19:23:13.461619 ==============================================================
6229 19:23:13.464572 GAT_TRACK_EN = 0
6230 19:23:13.467999 RX_GATING_MODE = 2
6231 19:23:13.470976 RX_GATING_TRACK_MODE = 2
6232 19:23:13.474584 SELPH_MODE = 1
6233 19:23:13.474668 PICG_EARLY_EN = 1
6234 19:23:13.477856 VALID_LAT_VALUE = 1
6235 19:23:13.484541 ==============================================================
6236 19:23:13.487547 Enter into Gating configuration >>>>
6237 19:23:13.491181 Exit from Gating configuration <<<<
6238 19:23:13.494332 Enter into DVFS_PRE_config >>>>>
6239 19:23:13.504487 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6240 19:23:13.507258 Exit from DVFS_PRE_config <<<<<
6241 19:23:13.510516 Enter into PICG configuration >>>>
6242 19:23:13.513810 Exit from PICG configuration <<<<
6243 19:23:13.517147 [RX_INPUT] configuration >>>>>
6244 19:23:13.520251 [RX_INPUT] configuration <<<<<
6245 19:23:13.526919 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6246 19:23:13.530164 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6247 19:23:13.536885 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6248 19:23:13.543530 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6249 19:23:13.550184 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6250 19:23:13.556565 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6251 19:23:13.560365 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6252 19:23:13.563624 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6253 19:23:13.566753 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6254 19:23:13.573125 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6255 19:23:13.576294 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6256 19:23:13.579768 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6257 19:23:13.583022 ===================================
6258 19:23:13.586307 LPDDR4 DRAM CONFIGURATION
6259 19:23:13.589636 ===================================
6260 19:23:13.592896 EX_ROW_EN[0] = 0x0
6261 19:23:13.592978 EX_ROW_EN[1] = 0x0
6262 19:23:13.596338 LP4Y_EN = 0x0
6263 19:23:13.596420 WORK_FSP = 0x0
6264 19:23:13.599793 WL = 0x2
6265 19:23:13.599874 RL = 0x2
6266 19:23:13.602789 BL = 0x2
6267 19:23:13.602872 RPST = 0x0
6268 19:23:13.606192 RD_PRE = 0x0
6269 19:23:13.606274 WR_PRE = 0x1
6270 19:23:13.609402 WR_PST = 0x0
6271 19:23:13.609519 DBI_WR = 0x0
6272 19:23:13.612300 DBI_RD = 0x0
6273 19:23:13.615693 OTF = 0x1
6274 19:23:13.619013 ===================================
6275 19:23:13.622300 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6276 19:23:13.625635 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6277 19:23:13.629570 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6278 19:23:13.632157 ===================================
6279 19:23:13.635497 LPDDR4 DRAM CONFIGURATION
6280 19:23:13.638786 ===================================
6281 19:23:13.642725 EX_ROW_EN[0] = 0x10
6282 19:23:13.642806 EX_ROW_EN[1] = 0x0
6283 19:23:13.645474 LP4Y_EN = 0x0
6284 19:23:13.645555 WORK_FSP = 0x0
6285 19:23:13.648652 WL = 0x2
6286 19:23:13.648732 RL = 0x2
6287 19:23:13.651815 BL = 0x2
6288 19:23:13.651896 RPST = 0x0
6289 19:23:13.655718 RD_PRE = 0x0
6290 19:23:13.655798 WR_PRE = 0x1
6291 19:23:13.658913 WR_PST = 0x0
6292 19:23:13.661653 DBI_WR = 0x0
6293 19:23:13.661734 DBI_RD = 0x0
6294 19:23:13.665540 OTF = 0x1
6295 19:23:13.668729 ===================================
6296 19:23:13.671953 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6297 19:23:13.677233 nWR fixed to 30
6298 19:23:13.680565 [ModeRegInit_LP4] CH0 RK0
6299 19:23:13.680647 [ModeRegInit_LP4] CH0 RK1
6300 19:23:13.683925 [ModeRegInit_LP4] CH1 RK0
6301 19:23:13.687025 [ModeRegInit_LP4] CH1 RK1
6302 19:23:13.687106 match AC timing 19
6303 19:23:13.693561 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6304 19:23:13.696627 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6305 19:23:13.699955 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6306 19:23:13.706860 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6307 19:23:13.710237 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6308 19:23:13.710344 ==
6309 19:23:13.713152 Dram Type= 6, Freq= 0, CH_0, rank 0
6310 19:23:13.716489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6311 19:23:13.716572 ==
6312 19:23:13.722922 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6313 19:23:13.729424 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6314 19:23:13.733091 [CA 0] Center 36 (8~64) winsize 57
6315 19:23:13.736460 [CA 1] Center 36 (8~64) winsize 57
6316 19:23:13.739602 [CA 2] Center 36 (8~64) winsize 57
6317 19:23:13.742813 [CA 3] Center 36 (8~64) winsize 57
6318 19:23:13.746150 [CA 4] Center 36 (8~64) winsize 57
6319 19:23:13.749486 [CA 5] Center 36 (8~64) winsize 57
6320 19:23:13.749573
6321 19:23:13.752825 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6322 19:23:13.752908
6323 19:23:13.756108 [CATrainingPosCal] consider 1 rank data
6324 19:23:13.759262 u2DelayCellTimex100 = 270/100 ps
6325 19:23:13.762358 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6326 19:23:13.765657 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6327 19:23:13.768950 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6328 19:23:13.772751 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6329 19:23:13.775577 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6330 19:23:13.779354 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6331 19:23:13.779452
6332 19:23:13.786087 CA PerBit enable=1, Macro0, CA PI delay=36
6333 19:23:13.786169
6334 19:23:13.786234 [CBTSetCACLKResult] CA Dly = 36
6335 19:23:13.789263 CS Dly: 1 (0~32)
6336 19:23:13.789352 ==
6337 19:23:13.792476 Dram Type= 6, Freq= 0, CH_0, rank 1
6338 19:23:13.795474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6339 19:23:13.795592 ==
6340 19:23:13.801966 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6341 19:23:13.808542 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6342 19:23:13.812391 [CA 0] Center 36 (8~64) winsize 57
6343 19:23:13.815514 [CA 1] Center 36 (8~64) winsize 57
6344 19:23:13.818507 [CA 2] Center 36 (8~64) winsize 57
6345 19:23:13.822178 [CA 3] Center 36 (8~64) winsize 57
6346 19:23:13.822293 [CA 4] Center 36 (8~64) winsize 57
6347 19:23:13.825462 [CA 5] Center 36 (8~64) winsize 57
6348 19:23:13.825533
6349 19:23:13.831762 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6350 19:23:13.831864
6351 19:23:13.835403 [CATrainingPosCal] consider 2 rank data
6352 19:23:13.838336 u2DelayCellTimex100 = 270/100 ps
6353 19:23:13.841671 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6354 19:23:13.844752 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6355 19:23:13.848409 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6356 19:23:13.851614 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6357 19:23:13.854950 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6358 19:23:13.858221 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6359 19:23:13.858295
6360 19:23:13.861467 CA PerBit enable=1, Macro0, CA PI delay=36
6361 19:23:13.861536
6362 19:23:13.864657 [CBTSetCACLKResult] CA Dly = 36
6363 19:23:13.867816 CS Dly: 1 (0~32)
6364 19:23:13.867913
6365 19:23:13.871136 ----->DramcWriteLeveling(PI) begin...
6366 19:23:13.871211 ==
6367 19:23:13.874594 Dram Type= 6, Freq= 0, CH_0, rank 0
6368 19:23:13.877862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6369 19:23:13.877942 ==
6370 19:23:13.881169 Write leveling (Byte 0): 40 => 8
6371 19:23:13.884483 Write leveling (Byte 1): 32 => 0
6372 19:23:13.887812 DramcWriteLeveling(PI) end<-----
6373 19:23:13.887891
6374 19:23:13.887953 ==
6375 19:23:13.891134 Dram Type= 6, Freq= 0, CH_0, rank 0
6376 19:23:13.894393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6377 19:23:13.894468 ==
6378 19:23:13.897529 [Gating] SW mode calibration
6379 19:23:13.904133 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6380 19:23:13.910602 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6381 19:23:13.914459 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6382 19:23:13.920967 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6383 19:23:13.924165 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6384 19:23:13.927178 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6385 19:23:13.933837 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6386 19:23:13.937252 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6387 19:23:13.940514 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6388 19:23:13.946974 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6389 19:23:13.950390 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6390 19:23:13.953811 Total UI for P1: 0, mck2ui 16
6391 19:23:13.956851 best dqsien dly found for B0: ( 0, 14, 24)
6392 19:23:13.960543 Total UI for P1: 0, mck2ui 16
6393 19:23:13.963772 best dqsien dly found for B1: ( 0, 14, 24)
6394 19:23:13.967027 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6395 19:23:13.970216 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6396 19:23:13.970299
6397 19:23:13.973514 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6398 19:23:13.976975 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6399 19:23:13.980078 [Gating] SW calibration Done
6400 19:23:13.980161 ==
6401 19:23:13.983337 Dram Type= 6, Freq= 0, CH_0, rank 0
6402 19:23:13.989882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6403 19:23:13.989991 ==
6404 19:23:13.990087 RX Vref Scan: 0
6405 19:23:13.990177
6406 19:23:13.993088 RX Vref 0 -> 0, step: 1
6407 19:23:13.993183
6408 19:23:13.996447 RX Delay -410 -> 252, step: 16
6409 19:23:14.000250 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6410 19:23:14.003530 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6411 19:23:14.010010 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6412 19:23:14.013238 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6413 19:23:14.016538 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6414 19:23:14.019947 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6415 19:23:14.026446 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6416 19:23:14.029865 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6417 19:23:14.032940 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6418 19:23:14.036118 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6419 19:23:14.043111 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6420 19:23:14.046167 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6421 19:23:14.049447 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6422 19:23:14.052802 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6423 19:23:14.059512 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6424 19:23:14.062751 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6425 19:23:14.062854 ==
6426 19:23:14.065894 Dram Type= 6, Freq= 0, CH_0, rank 0
6427 19:23:14.069516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6428 19:23:14.069600 ==
6429 19:23:14.072342 DQS Delay:
6430 19:23:14.072448 DQS0 = 43, DQS1 = 59
6431 19:23:14.075538 DQM Delay:
6432 19:23:14.075635 DQM0 = 10, DQM1 = 11
6433 19:23:14.075727 DQ Delay:
6434 19:23:14.079383 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =0
6435 19:23:14.082595 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6436 19:23:14.085667 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6437 19:23:14.089042 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6438 19:23:14.089146
6439 19:23:14.089236
6440 19:23:14.089324 ==
6441 19:23:14.092191 Dram Type= 6, Freq= 0, CH_0, rank 0
6442 19:23:14.098756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6443 19:23:14.098861 ==
6444 19:23:14.098958
6445 19:23:14.099070
6446 19:23:14.099219 TX Vref Scan disable
6447 19:23:14.101971 == TX Byte 0 ==
6448 19:23:14.105280 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6449 19:23:14.108539 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6450 19:23:14.111751 == TX Byte 1 ==
6451 19:23:14.115202 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6452 19:23:14.121717 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6453 19:23:14.121793 ==
6454 19:23:14.124969 Dram Type= 6, Freq= 0, CH_0, rank 0
6455 19:23:14.128222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6456 19:23:14.128325 ==
6457 19:23:14.128415
6458 19:23:14.128495
6459 19:23:14.131537 TX Vref Scan disable
6460 19:23:14.131651 == TX Byte 0 ==
6461 19:23:14.134834 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6462 19:23:14.141454 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6463 19:23:14.141533 == TX Byte 1 ==
6464 19:23:14.144550 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6465 19:23:14.151336 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6466 19:23:14.151442
6467 19:23:14.151533 [DATLAT]
6468 19:23:14.154769 Freq=400, CH0 RK0
6469 19:23:14.154867
6470 19:23:14.154955 DATLAT Default: 0xf
6471 19:23:14.157956 0, 0xFFFF, sum = 0
6472 19:23:14.158033 1, 0xFFFF, sum = 0
6473 19:23:14.160989 2, 0xFFFF, sum = 0
6474 19:23:14.161108 3, 0xFFFF, sum = 0
6475 19:23:14.164237 4, 0xFFFF, sum = 0
6476 19:23:14.164367 5, 0xFFFF, sum = 0
6477 19:23:14.167999 6, 0xFFFF, sum = 0
6478 19:23:14.168145 7, 0xFFFF, sum = 0
6479 19:23:14.171092 8, 0xFFFF, sum = 0
6480 19:23:14.171197 9, 0xFFFF, sum = 0
6481 19:23:14.174373 10, 0xFFFF, sum = 0
6482 19:23:14.174447 11, 0xFFFF, sum = 0
6483 19:23:14.177525 12, 0xFFFF, sum = 0
6484 19:23:14.177632 13, 0x0, sum = 1
6485 19:23:14.181243 14, 0x0, sum = 2
6486 19:23:14.181422 15, 0x0, sum = 3
6487 19:23:14.184051 16, 0x0, sum = 4
6488 19:23:14.184154 best_step = 14
6489 19:23:14.184245
6490 19:23:14.184375 ==
6491 19:23:14.187554 Dram Type= 6, Freq= 0, CH_0, rank 0
6492 19:23:14.194131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6493 19:23:14.194275 ==
6494 19:23:14.194416 RX Vref Scan: 1
6495 19:23:14.194526
6496 19:23:14.197776 RX Vref 0 -> 0, step: 1
6497 19:23:14.197883
6498 19:23:14.200735 RX Delay -359 -> 252, step: 8
6499 19:23:14.200835
6500 19:23:14.203923 Set Vref, RX VrefLevel [Byte0]: 59
6501 19:23:14.207163 [Byte1]: 49
6502 19:23:14.210997
6503 19:23:14.211099 Final RX Vref Byte 0 = 59 to rank0
6504 19:23:14.214406 Final RX Vref Byte 1 = 49 to rank0
6505 19:23:14.217680 Final RX Vref Byte 0 = 59 to rank1
6506 19:23:14.220895 Final RX Vref Byte 1 = 49 to rank1==
6507 19:23:14.224271 Dram Type= 6, Freq= 0, CH_0, rank 0
6508 19:23:14.230613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6509 19:23:14.230717 ==
6510 19:23:14.230811 DQS Delay:
6511 19:23:14.233949 DQS0 = 48, DQS1 = 60
6512 19:23:14.234023 DQM Delay:
6513 19:23:14.234084 DQM0 = 11, DQM1 = 12
6514 19:23:14.237243 DQ Delay:
6515 19:23:14.240639 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6516 19:23:14.243952 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6517 19:23:14.244049 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6518 19:23:14.250486 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6519 19:23:14.250563
6520 19:23:14.250629
6521 19:23:14.256936 [DQSOSCAuto] RK0, (LSB)MR18= 0xb578, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 387 ps
6522 19:23:14.260647 CH0 RK0: MR19=C0C, MR18=B578
6523 19:23:14.267204 CH0_RK0: MR19=0xC0C, MR18=0xB578, DQSOSC=387, MR23=63, INC=394, DEC=262
6524 19:23:14.267313 ==
6525 19:23:14.270422 Dram Type= 6, Freq= 0, CH_0, rank 1
6526 19:23:14.273588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6527 19:23:14.273664 ==
6528 19:23:14.276612 [Gating] SW mode calibration
6529 19:23:14.283520 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6530 19:23:14.289989 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6531 19:23:14.293173 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6532 19:23:14.296835 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6533 19:23:14.302919 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6534 19:23:14.306552 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6535 19:23:14.309612 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6536 19:23:14.316201 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6537 19:23:14.319613 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6538 19:23:14.322828 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6539 19:23:14.329427 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6540 19:23:14.332749 Total UI for P1: 0, mck2ui 16
6541 19:23:14.335978 best dqsien dly found for B0: ( 0, 14, 24)
6542 19:23:14.339308 Total UI for P1: 0, mck2ui 16
6543 19:23:14.342630 best dqsien dly found for B1: ( 0, 14, 24)
6544 19:23:14.345898 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6545 19:23:14.349295 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6546 19:23:14.349386
6547 19:23:14.352636 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6548 19:23:14.355776 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6549 19:23:14.358955 [Gating] SW calibration Done
6550 19:23:14.359039 ==
6551 19:23:14.362288 Dram Type= 6, Freq= 0, CH_0, rank 1
6552 19:23:14.365517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6553 19:23:14.368710 ==
6554 19:23:14.368811 RX Vref Scan: 0
6555 19:23:14.368902
6556 19:23:14.372364 RX Vref 0 -> 0, step: 1
6557 19:23:14.372438
6558 19:23:14.375284 RX Delay -410 -> 252, step: 16
6559 19:23:14.378895 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6560 19:23:14.381658 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6561 19:23:14.385215 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6562 19:23:14.391507 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6563 19:23:14.395273 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6564 19:23:14.398507 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6565 19:23:14.401952 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6566 19:23:14.408238 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6567 19:23:14.411354 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6568 19:23:14.415050 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6569 19:23:14.421703 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6570 19:23:14.424676 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6571 19:23:14.427681 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6572 19:23:14.431125 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6573 19:23:14.438042 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6574 19:23:14.441452 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6575 19:23:14.441563 ==
6576 19:23:14.444124 Dram Type= 6, Freq= 0, CH_0, rank 1
6577 19:23:14.447943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6578 19:23:14.448042 ==
6579 19:23:14.450704 DQS Delay:
6580 19:23:14.450798 DQS0 = 43, DQS1 = 59
6581 19:23:14.454539 DQM Delay:
6582 19:23:14.454610 DQM0 = 11, DQM1 = 16
6583 19:23:14.454672 DQ Delay:
6584 19:23:14.457242 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6585 19:23:14.460965 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6586 19:23:14.464215 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6587 19:23:14.467629 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6588 19:23:14.467732
6589 19:23:14.467821
6590 19:23:14.467909 ==
6591 19:23:14.470919 Dram Type= 6, Freq= 0, CH_0, rank 1
6592 19:23:14.477503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6593 19:23:14.477614 ==
6594 19:23:14.477703
6595 19:23:14.477797
6596 19:23:14.477881 TX Vref Scan disable
6597 19:23:14.480533 == TX Byte 0 ==
6598 19:23:14.484096 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6599 19:23:14.487009 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6600 19:23:14.490770 == TX Byte 1 ==
6601 19:23:14.493736 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6602 19:23:14.497104 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6603 19:23:14.497203 ==
6604 19:23:14.500255 Dram Type= 6, Freq= 0, CH_0, rank 1
6605 19:23:14.506878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6606 19:23:14.506978 ==
6607 19:23:14.507076
6608 19:23:14.507163
6609 19:23:14.507251 TX Vref Scan disable
6610 19:23:14.510122 == TX Byte 0 ==
6611 19:23:14.513946 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6612 19:23:14.517043 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6613 19:23:14.520257 == TX Byte 1 ==
6614 19:23:14.523441 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6615 19:23:14.526642 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6616 19:23:14.526715
6617 19:23:14.529847 [DATLAT]
6618 19:23:14.529920 Freq=400, CH0 RK1
6619 19:23:14.529982
6620 19:23:14.533428 DATLAT Default: 0xe
6621 19:23:14.533503 0, 0xFFFF, sum = 0
6622 19:23:14.536824 1, 0xFFFF, sum = 0
6623 19:23:14.536896 2, 0xFFFF, sum = 0
6624 19:23:14.539690 3, 0xFFFF, sum = 0
6625 19:23:14.539791 4, 0xFFFF, sum = 0
6626 19:23:14.543461 5, 0xFFFF, sum = 0
6627 19:23:14.546851 6, 0xFFFF, sum = 0
6628 19:23:14.546933 7, 0xFFFF, sum = 0
6629 19:23:14.550064 8, 0xFFFF, sum = 0
6630 19:23:14.550175 9, 0xFFFF, sum = 0
6631 19:23:14.553466 10, 0xFFFF, sum = 0
6632 19:23:14.553576 11, 0xFFFF, sum = 0
6633 19:23:14.556742 12, 0xFFFF, sum = 0
6634 19:23:14.556824 13, 0x0, sum = 1
6635 19:23:14.559993 14, 0x0, sum = 2
6636 19:23:14.560075 15, 0x0, sum = 3
6637 19:23:14.563313 16, 0x0, sum = 4
6638 19:23:14.563397 best_step = 14
6639 19:23:14.563462
6640 19:23:14.563524 ==
6641 19:23:14.566607 Dram Type= 6, Freq= 0, CH_0, rank 1
6642 19:23:14.569869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6643 19:23:14.573082 ==
6644 19:23:14.573164 RX Vref Scan: 0
6645 19:23:14.573229
6646 19:23:14.576502 RX Vref 0 -> 0, step: 1
6647 19:23:14.576585
6648 19:23:14.579691 RX Delay -359 -> 252, step: 8
6649 19:23:14.586254 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6650 19:23:14.589359 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6651 19:23:14.592977 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6652 19:23:14.595750 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6653 19:23:14.602468 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6654 19:23:14.606234 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6655 19:23:14.609173 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6656 19:23:14.612804 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6657 19:23:14.619365 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6658 19:23:14.622599 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6659 19:23:14.625835 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6660 19:23:14.629197 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6661 19:23:14.635728 iDelay=217, Bit 12, Center -36 (-279 ~ 208) 488
6662 19:23:14.638944 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6663 19:23:14.642268 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6664 19:23:14.648960 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6665 19:23:14.649070 ==
6666 19:23:14.651893 Dram Type= 6, Freq= 0, CH_0, rank 1
6667 19:23:14.655455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6668 19:23:14.655539 ==
6669 19:23:14.655610 DQS Delay:
6670 19:23:14.658746 DQS0 = 44, DQS1 = 60
6671 19:23:14.658828 DQM Delay:
6672 19:23:14.661990 DQM0 = 8, DQM1 = 15
6673 19:23:14.662084 DQ Delay:
6674 19:23:14.665218 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =8
6675 19:23:14.668448 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6676 19:23:14.671896 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =8
6677 19:23:14.675177 DQ12 =24, DQ13 =20, DQ14 =24, DQ15 =20
6678 19:23:14.675277
6679 19:23:14.675368
6680 19:23:14.681904 [DQSOSCAuto] RK1, (LSB)MR18= 0xb23f, (MSB)MR19= 0xc0c, tDQSOscB0 = 401 ps tDQSOscB1 = 387 ps
6681 19:23:14.685176 CH0 RK1: MR19=C0C, MR18=B23F
6682 19:23:14.691867 CH0_RK1: MR19=0xC0C, MR18=0xB23F, DQSOSC=387, MR23=63, INC=394, DEC=262
6683 19:23:14.695039 [RxdqsGatingPostProcess] freq 400
6684 19:23:14.701861 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6685 19:23:14.701937 best DQS0 dly(2T, 0.5T) = (0, 10)
6686 19:23:14.704790 best DQS1 dly(2T, 0.5T) = (0, 10)
6687 19:23:14.708341 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6688 19:23:14.711735 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6689 19:23:14.714948 best DQS0 dly(2T, 0.5T) = (0, 10)
6690 19:23:14.717893 best DQS1 dly(2T, 0.5T) = (0, 10)
6691 19:23:14.721437 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6692 19:23:14.724321 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6693 19:23:14.727991 Pre-setting of DQS Precalculation
6694 19:23:14.734602 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6695 19:23:14.734716 ==
6696 19:23:14.737813 Dram Type= 6, Freq= 0, CH_1, rank 0
6697 19:23:14.741144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6698 19:23:14.741249 ==
6699 19:23:14.747632 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6700 19:23:14.750971 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6701 19:23:14.754284 [CA 0] Center 36 (8~64) winsize 57
6702 19:23:14.757467 [CA 1] Center 36 (8~64) winsize 57
6703 19:23:14.760460 [CA 2] Center 36 (8~64) winsize 57
6704 19:23:14.764004 [CA 3] Center 36 (8~64) winsize 57
6705 19:23:14.767463 [CA 4] Center 36 (8~64) winsize 57
6706 19:23:14.770414 [CA 5] Center 36 (8~64) winsize 57
6707 19:23:14.770492
6708 19:23:14.773765 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6709 19:23:14.773839
6710 19:23:14.777080 [CATrainingPosCal] consider 1 rank data
6711 19:23:14.780337 u2DelayCellTimex100 = 270/100 ps
6712 19:23:14.783640 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6713 19:23:14.790010 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6714 19:23:14.793260 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6715 19:23:14.796513 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6716 19:23:14.799825 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6717 19:23:14.803093 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6718 19:23:14.803164
6719 19:23:14.806948 CA PerBit enable=1, Macro0, CA PI delay=36
6720 19:23:14.807017
6721 19:23:14.810174 [CBTSetCACLKResult] CA Dly = 36
6722 19:23:14.813177 CS Dly: 1 (0~32)
6723 19:23:14.813279 ==
6724 19:23:14.816704 Dram Type= 6, Freq= 0, CH_1, rank 1
6725 19:23:14.819568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6726 19:23:14.819675 ==
6727 19:23:14.826621 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6728 19:23:14.829840 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6729 19:23:14.832932 [CA 0] Center 36 (8~64) winsize 57
6730 19:23:14.835950 [CA 1] Center 36 (8~64) winsize 57
6731 19:23:14.839326 [CA 2] Center 36 (8~64) winsize 57
6732 19:23:14.842850 [CA 3] Center 36 (8~64) winsize 57
6733 19:23:14.846287 [CA 4] Center 36 (8~64) winsize 57
6734 19:23:14.849270 [CA 5] Center 36 (8~64) winsize 57
6735 19:23:14.849381
6736 19:23:14.852559 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6737 19:23:14.852644
6738 19:23:14.855883 [CATrainingPosCal] consider 2 rank data
6739 19:23:14.859064 u2DelayCellTimex100 = 270/100 ps
6740 19:23:14.862471 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6741 19:23:14.868813 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6742 19:23:14.872609 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6743 19:23:14.875648 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6744 19:23:14.878695 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6745 19:23:14.882190 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6746 19:23:14.882269
6747 19:23:14.885515 CA PerBit enable=1, Macro0, CA PI delay=36
6748 19:23:14.885590
6749 19:23:14.888821 [CBTSetCACLKResult] CA Dly = 36
6750 19:23:14.888917 CS Dly: 1 (0~32)
6751 19:23:14.892175
6752 19:23:14.895380 ----->DramcWriteLeveling(PI) begin...
6753 19:23:14.895454 ==
6754 19:23:14.898652 Dram Type= 6, Freq= 0, CH_1, rank 0
6755 19:23:14.901928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6756 19:23:14.901999 ==
6757 19:23:14.905113 Write leveling (Byte 0): 40 => 8
6758 19:23:14.908312 Write leveling (Byte 1): 40 => 8
6759 19:23:14.911592 DramcWriteLeveling(PI) end<-----
6760 19:23:14.911687
6761 19:23:14.911775 ==
6762 19:23:14.915008 Dram Type= 6, Freq= 0, CH_1, rank 0
6763 19:23:14.918348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6764 19:23:14.918446 ==
6765 19:23:14.921646 [Gating] SW mode calibration
6766 19:23:14.928454 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6767 19:23:14.934687 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6768 19:23:14.938480 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6769 19:23:14.941713 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6770 19:23:14.947956 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6771 19:23:14.951562 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6772 19:23:14.954473 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6773 19:23:14.961064 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6774 19:23:14.964415 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6775 19:23:14.968365 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6776 19:23:14.974880 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6777 19:23:14.974983 Total UI for P1: 0, mck2ui 16
6778 19:23:14.981519 best dqsien dly found for B0: ( 0, 14, 24)
6779 19:23:14.981597 Total UI for P1: 0, mck2ui 16
6780 19:23:14.987840 best dqsien dly found for B1: ( 0, 14, 24)
6781 19:23:14.990863 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6782 19:23:14.994448 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6783 19:23:14.994553
6784 19:23:14.997767 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6785 19:23:15.000853 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6786 19:23:15.004146 [Gating] SW calibration Done
6787 19:23:15.004244 ==
6788 19:23:15.007601 Dram Type= 6, Freq= 0, CH_1, rank 0
6789 19:23:15.010862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6790 19:23:15.010958 ==
6791 19:23:15.014016 RX Vref Scan: 0
6792 19:23:15.014085
6793 19:23:15.014148 RX Vref 0 -> 0, step: 1
6794 19:23:15.017394
6795 19:23:15.017490 RX Delay -410 -> 252, step: 16
6796 19:23:15.024013 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6797 19:23:15.027277 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6798 19:23:15.030601 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6799 19:23:15.037050 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6800 19:23:15.040137 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6801 19:23:15.043705 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6802 19:23:15.047078 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6803 19:23:15.053644 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6804 19:23:15.056672 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6805 19:23:15.060155 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6806 19:23:15.063563 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6807 19:23:15.070156 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6808 19:23:15.073494 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6809 19:23:15.076522 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6810 19:23:15.079726 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6811 19:23:15.086311 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6812 19:23:15.086396 ==
6813 19:23:15.089631 Dram Type= 6, Freq= 0, CH_1, rank 0
6814 19:23:15.092914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6815 19:23:15.092998 ==
6816 19:23:15.096085 DQS Delay:
6817 19:23:15.096169 DQS0 = 43, DQS1 = 51
6818 19:23:15.096236 DQM Delay:
6819 19:23:15.099211 DQM0 = 12, DQM1 = 14
6820 19:23:15.099295 DQ Delay:
6821 19:23:15.102872 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6822 19:23:15.105825 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6823 19:23:15.108984 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6824 19:23:15.112285 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6825 19:23:15.112368
6826 19:23:15.112434
6827 19:23:15.112495 ==
6828 19:23:15.115686 Dram Type= 6, Freq= 0, CH_1, rank 0
6829 19:23:15.118943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6830 19:23:15.122238 ==
6831 19:23:15.122321
6832 19:23:15.122386
6833 19:23:15.122446 TX Vref Scan disable
6834 19:23:15.125702 == TX Byte 0 ==
6835 19:23:15.128837 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6836 19:23:15.132081 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6837 19:23:15.135348 == TX Byte 1 ==
6838 19:23:15.138660 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6839 19:23:15.141997 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6840 19:23:15.142080 ==
6841 19:23:15.145224 Dram Type= 6, Freq= 0, CH_1, rank 0
6842 19:23:15.152469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6843 19:23:15.152553 ==
6844 19:23:15.152619
6845 19:23:15.152681
6846 19:23:15.152740 TX Vref Scan disable
6847 19:23:15.155639 == TX Byte 0 ==
6848 19:23:15.158690 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6849 19:23:15.162056 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6850 19:23:15.165480 == TX Byte 1 ==
6851 19:23:15.168892 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6852 19:23:15.171973 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6853 19:23:15.172079
6854 19:23:15.175436 [DATLAT]
6855 19:23:15.175510 Freq=400, CH1 RK0
6856 19:23:15.175600
6857 19:23:15.178837 DATLAT Default: 0xf
6858 19:23:15.178918 0, 0xFFFF, sum = 0
6859 19:23:15.182227 1, 0xFFFF, sum = 0
6860 19:23:15.182315 2, 0xFFFF, sum = 0
6861 19:23:15.184988 3, 0xFFFF, sum = 0
6862 19:23:15.185090 4, 0xFFFF, sum = 0
6863 19:23:15.188431 5, 0xFFFF, sum = 0
6864 19:23:15.188535 6, 0xFFFF, sum = 0
6865 19:23:15.191685 7, 0xFFFF, sum = 0
6866 19:23:15.191787 8, 0xFFFF, sum = 0
6867 19:23:15.195214 9, 0xFFFF, sum = 0
6868 19:23:15.195305 10, 0xFFFF, sum = 0
6869 19:23:15.198709 11, 0xFFFF, sum = 0
6870 19:23:15.201917 12, 0xFFFF, sum = 0
6871 19:23:15.202018 13, 0x0, sum = 1
6872 19:23:15.205238 14, 0x0, sum = 2
6873 19:23:15.205352 15, 0x0, sum = 3
6874 19:23:15.205447 16, 0x0, sum = 4
6875 19:23:15.208343 best_step = 14
6876 19:23:15.208439
6877 19:23:15.208537 ==
6878 19:23:15.211536 Dram Type= 6, Freq= 0, CH_1, rank 0
6879 19:23:15.215156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6880 19:23:15.215254 ==
6881 19:23:15.218003 RX Vref Scan: 1
6882 19:23:15.218081
6883 19:23:15.221142 RX Vref 0 -> 0, step: 1
6884 19:23:15.221211
6885 19:23:15.221271 RX Delay -343 -> 252, step: 8
6886 19:23:15.221336
6887 19:23:15.225120 Set Vref, RX VrefLevel [Byte0]: 49
6888 19:23:15.227768 [Byte1]: 53
6889 19:23:15.233751
6890 19:23:15.233841 Final RX Vref Byte 0 = 49 to rank0
6891 19:23:15.236964 Final RX Vref Byte 1 = 53 to rank0
6892 19:23:15.240346 Final RX Vref Byte 0 = 49 to rank1
6893 19:23:15.243485 Final RX Vref Byte 1 = 53 to rank1==
6894 19:23:15.246173 Dram Type= 6, Freq= 0, CH_1, rank 0
6895 19:23:15.252799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6896 19:23:15.252905 ==
6897 19:23:15.253002 DQS Delay:
6898 19:23:15.256124 DQS0 = 44, DQS1 = 56
6899 19:23:15.256227 DQM Delay:
6900 19:23:15.256321 DQM0 = 7, DQM1 = 11
6901 19:23:15.259453 DQ Delay:
6902 19:23:15.262675 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6903 19:23:15.266640 DQ4 =4, DQ5 =16, DQ6 =16, DQ7 =4
6904 19:23:15.266725 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6905 19:23:15.269606 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =20
6906 19:23:15.272954
6907 19:23:15.273037
6908 19:23:15.279446 [DQSOSCAuto] RK0, (LSB)MR18= 0x8f65, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 391 ps
6909 19:23:15.282697 CH1 RK0: MR19=C0C, MR18=8F65
6910 19:23:15.289152 CH1_RK0: MR19=0xC0C, MR18=0x8F65, DQSOSC=391, MR23=63, INC=386, DEC=257
6911 19:23:15.289261 ==
6912 19:23:15.292363 Dram Type= 6, Freq= 0, CH_1, rank 1
6913 19:23:15.295928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6914 19:23:15.296012 ==
6915 19:23:15.298963 [Gating] SW mode calibration
6916 19:23:15.305806 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6917 19:23:15.312728 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6918 19:23:15.315964 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6919 19:23:15.319372 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6920 19:23:15.325510 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6921 19:23:15.329138 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6922 19:23:15.332161 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6923 19:23:15.338792 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6924 19:23:15.342036 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6925 19:23:15.345266 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6926 19:23:15.352094 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6927 19:23:15.352179 Total UI for P1: 0, mck2ui 16
6928 19:23:15.358733 best dqsien dly found for B0: ( 0, 14, 24)
6929 19:23:15.358818 Total UI for P1: 0, mck2ui 16
6930 19:23:15.365244 best dqsien dly found for B1: ( 0, 14, 24)
6931 19:23:15.368628 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6932 19:23:15.371787 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6933 19:23:15.371871
6934 19:23:15.374859 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6935 19:23:15.377935 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6936 19:23:15.381662 [Gating] SW calibration Done
6937 19:23:15.381746 ==
6938 19:23:15.384701 Dram Type= 6, Freq= 0, CH_1, rank 1
6939 19:23:15.388091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6940 19:23:15.388175 ==
6941 19:23:15.391122 RX Vref Scan: 0
6942 19:23:15.391206
6943 19:23:15.394840 RX Vref 0 -> 0, step: 1
6944 19:23:15.394924
6945 19:23:15.394990 RX Delay -410 -> 252, step: 16
6946 19:23:15.401265 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6947 19:23:15.404496 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6948 19:23:15.407634 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6949 19:23:15.414540 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6950 19:23:15.417617 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6951 19:23:15.421249 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6952 19:23:15.424535 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6953 19:23:15.431281 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6954 19:23:15.434378 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6955 19:23:15.437447 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6956 19:23:15.440842 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6957 19:23:15.447660 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6958 19:23:15.450903 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6959 19:23:15.454335 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6960 19:23:15.457783 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6961 19:23:15.463702 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6962 19:23:15.463788 ==
6963 19:23:15.466926 Dram Type= 6, Freq= 0, CH_1, rank 1
6964 19:23:15.470341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6965 19:23:15.470418 ==
6966 19:23:15.470480 DQS Delay:
6967 19:23:15.473558 DQS0 = 43, DQS1 = 51
6968 19:23:15.473655 DQM Delay:
6969 19:23:15.476918 DQM0 = 13, DQM1 = 14
6970 19:23:15.477013 DQ Delay:
6971 19:23:15.480279 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6972 19:23:15.484129 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6973 19:23:15.487162 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6974 19:23:15.490420 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6975 19:23:15.490494
6976 19:23:15.490571
6977 19:23:15.490631 ==
6978 19:23:15.493354 Dram Type= 6, Freq= 0, CH_1, rank 1
6979 19:23:15.497245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6980 19:23:15.497394 ==
6981 19:23:15.500280
6982 19:23:15.500378
6983 19:23:15.500474 TX Vref Scan disable
6984 19:23:15.503288 == TX Byte 0 ==
6985 19:23:15.506878 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6986 19:23:15.510056 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6987 19:23:15.513169 == TX Byte 1 ==
6988 19:23:15.516263 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6989 19:23:15.519691 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6990 19:23:15.519788 ==
6991 19:23:15.523096 Dram Type= 6, Freq= 0, CH_1, rank 1
6992 19:23:15.529823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6993 19:23:15.529990 ==
6994 19:23:15.530111
6995 19:23:15.530237
6996 19:23:15.530322 TX Vref Scan disable
6997 19:23:15.533159 == TX Byte 0 ==
6998 19:23:15.536558 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6999 19:23:15.539223 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
7000 19:23:15.542661 == TX Byte 1 ==
7001 19:23:15.546561 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
7002 19:23:15.549573 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
7003 19:23:15.549654
7004 19:23:15.552570 [DATLAT]
7005 19:23:15.552650 Freq=400, CH1 RK1
7006 19:23:15.552714
7007 19:23:15.556112 DATLAT Default: 0xe
7008 19:23:15.556217 0, 0xFFFF, sum = 0
7009 19:23:15.559405 1, 0xFFFF, sum = 0
7010 19:23:15.559499 2, 0xFFFF, sum = 0
7011 19:23:15.562657 3, 0xFFFF, sum = 0
7012 19:23:15.562740 4, 0xFFFF, sum = 0
7013 19:23:15.566085 5, 0xFFFF, sum = 0
7014 19:23:15.566167 6, 0xFFFF, sum = 0
7015 19:23:15.569354 7, 0xFFFF, sum = 0
7016 19:23:15.569451 8, 0xFFFF, sum = 0
7017 19:23:15.572811 9, 0xFFFF, sum = 0
7018 19:23:15.576092 10, 0xFFFF, sum = 0
7019 19:23:15.576166 11, 0xFFFF, sum = 0
7020 19:23:15.578655 12, 0xFFFF, sum = 0
7021 19:23:15.578759 13, 0x0, sum = 1
7022 19:23:15.582632 14, 0x0, sum = 2
7023 19:23:15.582704 15, 0x0, sum = 3
7024 19:23:15.582766 16, 0x0, sum = 4
7025 19:23:15.585443 best_step = 14
7026 19:23:15.585539
7027 19:23:15.585634 ==
7028 19:23:15.589191 Dram Type= 6, Freq= 0, CH_1, rank 1
7029 19:23:15.592414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7030 19:23:15.592485 ==
7031 19:23:15.595460 RX Vref Scan: 0
7032 19:23:15.595534
7033 19:23:15.598664 RX Vref 0 -> 0, step: 1
7034 19:23:15.598767
7035 19:23:15.598856 RX Delay -343 -> 252, step: 8
7036 19:23:15.607200 iDelay=225, Bit 0, Center -32 (-271 ~ 208) 480
7037 19:23:15.610793 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
7038 19:23:15.613783 iDelay=225, Bit 2, Center -44 (-287 ~ 200) 488
7039 19:23:15.620550 iDelay=225, Bit 3, Center -40 (-279 ~ 200) 480
7040 19:23:15.623729 iDelay=225, Bit 4, Center -40 (-287 ~ 208) 496
7041 19:23:15.627103 iDelay=225, Bit 5, Center -28 (-271 ~ 216) 488
7042 19:23:15.630289 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
7043 19:23:15.636872 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
7044 19:23:15.639985 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
7045 19:23:15.643534 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
7046 19:23:15.646702 iDelay=225, Bit 10, Center -48 (-295 ~ 200) 496
7047 19:23:15.653220 iDelay=225, Bit 11, Center -52 (-295 ~ 192) 488
7048 19:23:15.656352 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
7049 19:23:15.659506 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
7050 19:23:15.666702 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
7051 19:23:15.669932 iDelay=225, Bit 15, Center -36 (-287 ~ 216) 504
7052 19:23:15.670015 ==
7053 19:23:15.673337 Dram Type= 6, Freq= 0, CH_1, rank 1
7054 19:23:15.676599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7055 19:23:15.676681 ==
7056 19:23:15.679806 DQS Delay:
7057 19:23:15.679903 DQS0 = 44, DQS1 = 56
7058 19:23:15.679983 DQM Delay:
7059 19:23:15.683099 DQM0 = 7, DQM1 = 10
7060 19:23:15.683181 DQ Delay:
7061 19:23:15.686475 DQ0 =12, DQ1 =0, DQ2 =0, DQ3 =4
7062 19:23:15.689186 DQ4 =4, DQ5 =16, DQ6 =20, DQ7 =4
7063 19:23:15.692411 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
7064 19:23:15.695827 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
7065 19:23:15.695913
7066 19:23:15.695977
7067 19:23:15.705833 [DQSOSCAuto] RK1, (LSB)MR18= 0x6353, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 397 ps
7068 19:23:15.705931 CH1 RK1: MR19=C0C, MR18=6353
7069 19:23:15.712190 CH1_RK1: MR19=0xC0C, MR18=0x6353, DQSOSC=397, MR23=63, INC=374, DEC=249
7070 19:23:15.715808 [RxdqsGatingPostProcess] freq 400
7071 19:23:15.722258 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7072 19:23:15.725327 best DQS0 dly(2T, 0.5T) = (0, 10)
7073 19:23:15.729225 best DQS1 dly(2T, 0.5T) = (0, 10)
7074 19:23:15.732293 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7075 19:23:15.735602 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7076 19:23:15.738865 best DQS0 dly(2T, 0.5T) = (0, 10)
7077 19:23:15.742168 best DQS1 dly(2T, 0.5T) = (0, 10)
7078 19:23:15.745585 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7079 19:23:15.748671 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7080 19:23:15.748754 Pre-setting of DQS Precalculation
7081 19:23:15.755290 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7082 19:23:15.761753 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7083 19:23:15.768242 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7084 19:23:15.768327
7085 19:23:15.768392
7086 19:23:15.772093 [Calibration Summary] 800 Mbps
7087 19:23:15.774849 CH 0, Rank 0
7088 19:23:15.774931 SW Impedance : PASS
7089 19:23:15.778566 DUTY Scan : NO K
7090 19:23:15.781759 ZQ Calibration : PASS
7091 19:23:15.781834 Jitter Meter : NO K
7092 19:23:15.785053 CBT Training : PASS
7093 19:23:15.788405 Write leveling : PASS
7094 19:23:15.788486 RX DQS gating : PASS
7095 19:23:15.791648 RX DQ/DQS(RDDQC) : PASS
7096 19:23:15.791729 TX DQ/DQS : PASS
7097 19:23:15.794923 RX DATLAT : PASS
7098 19:23:15.798395 RX DQ/DQS(Engine): PASS
7099 19:23:15.798475 TX OE : NO K
7100 19:23:15.801694 All Pass.
7101 19:23:15.801776
7102 19:23:15.801840 CH 0, Rank 1
7103 19:23:15.804830 SW Impedance : PASS
7104 19:23:15.804911 DUTY Scan : NO K
7105 19:23:15.808084 ZQ Calibration : PASS
7106 19:23:15.811069 Jitter Meter : NO K
7107 19:23:15.811151 CBT Training : PASS
7108 19:23:15.814344 Write leveling : NO K
7109 19:23:15.818224 RX DQS gating : PASS
7110 19:23:15.818322 RX DQ/DQS(RDDQC) : PASS
7111 19:23:15.821216 TX DQ/DQS : PASS
7112 19:23:15.824788 RX DATLAT : PASS
7113 19:23:15.824869 RX DQ/DQS(Engine): PASS
7114 19:23:15.827976 TX OE : NO K
7115 19:23:15.828057 All Pass.
7116 19:23:15.828121
7117 19:23:15.831233 CH 1, Rank 0
7118 19:23:15.831330 SW Impedance : PASS
7119 19:23:15.834559 DUTY Scan : NO K
7120 19:23:15.837481 ZQ Calibration : PASS
7121 19:23:15.837564 Jitter Meter : NO K
7122 19:23:15.840802 CBT Training : PASS
7123 19:23:15.844047 Write leveling : PASS
7124 19:23:15.844131 RX DQS gating : PASS
7125 19:23:15.847215 RX DQ/DQS(RDDQC) : PASS
7126 19:23:15.850479 TX DQ/DQS : PASS
7127 19:23:15.850577 RX DATLAT : PASS
7128 19:23:15.854316 RX DQ/DQS(Engine): PASS
7129 19:23:15.857711 TX OE : NO K
7130 19:23:15.857795 All Pass.
7131 19:23:15.857860
7132 19:23:15.857922 CH 1, Rank 1
7133 19:23:15.860772 SW Impedance : PASS
7134 19:23:15.863969 DUTY Scan : NO K
7135 19:23:15.864053 ZQ Calibration : PASS
7136 19:23:15.867490 Jitter Meter : NO K
7137 19:23:15.870444 CBT Training : PASS
7138 19:23:15.870529 Write leveling : NO K
7139 19:23:15.873844 RX DQS gating : PASS
7140 19:23:15.873928 RX DQ/DQS(RDDQC) : PASS
7141 19:23:15.877094 TX DQ/DQS : PASS
7142 19:23:15.880300 RX DATLAT : PASS
7143 19:23:15.880397 RX DQ/DQS(Engine): PASS
7144 19:23:15.883501 TX OE : NO K
7145 19:23:15.883613 All Pass.
7146 19:23:15.883720
7147 19:23:15.887266 DramC Write-DBI off
7148 19:23:15.890437 PER_BANK_REFRESH: Hybrid Mode
7149 19:23:15.890522 TX_TRACKING: ON
7150 19:23:15.900295 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7151 19:23:15.903571 [FAST_K] Save calibration result to emmc
7152 19:23:15.906907 dramc_set_vcore_voltage set vcore to 725000
7153 19:23:15.910148 Read voltage for 1600, 0
7154 19:23:15.910229 Vio18 = 0
7155 19:23:15.913409 Vcore = 725000
7156 19:23:15.913503 Vdram = 0
7157 19:23:15.913596 Vddq = 0
7158 19:23:15.913674 Vmddr = 0
7159 19:23:15.919665 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7160 19:23:15.926284 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7161 19:23:15.926397 MEM_TYPE=3, freq_sel=13
7162 19:23:15.929832 sv_algorithm_assistance_LP4_3733
7163 19:23:15.936332 ============ PULL DRAM RESETB DOWN ============
7164 19:23:15.939639 ========== PULL DRAM RESETB DOWN end =========
7165 19:23:15.942868 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7166 19:23:15.946566 ===================================
7167 19:23:15.949818 LPDDR4 DRAM CONFIGURATION
7168 19:23:15.952406 ===================================
7169 19:23:15.955628 EX_ROW_EN[0] = 0x0
7170 19:23:15.955720 EX_ROW_EN[1] = 0x0
7171 19:23:15.959034 LP4Y_EN = 0x0
7172 19:23:15.959114 WORK_FSP = 0x1
7173 19:23:15.962351 WL = 0x5
7174 19:23:15.962431 RL = 0x5
7175 19:23:15.965651 BL = 0x2
7176 19:23:15.965740 RPST = 0x0
7177 19:23:15.969514 RD_PRE = 0x0
7178 19:23:15.969596 WR_PRE = 0x1
7179 19:23:15.972154 WR_PST = 0x1
7180 19:23:15.972245 DBI_WR = 0x0
7181 19:23:15.975878 DBI_RD = 0x0
7182 19:23:15.975965 OTF = 0x1
7183 19:23:15.978924 ===================================
7184 19:23:15.982258 ===================================
7185 19:23:15.985840 ANA top config
7186 19:23:15.988972 ===================================
7187 19:23:15.992050 DLL_ASYNC_EN = 0
7188 19:23:15.992131 ALL_SLAVE_EN = 0
7189 19:23:15.995669 NEW_RANK_MODE = 1
7190 19:23:15.998953 DLL_IDLE_MODE = 1
7191 19:23:16.002165 LP45_APHY_COMB_EN = 1
7192 19:23:16.005381 TX_ODT_DIS = 0
7193 19:23:16.005456 NEW_8X_MODE = 1
7194 19:23:16.008666 ===================================
7195 19:23:16.011920 ===================================
7196 19:23:16.015283 data_rate = 3200
7197 19:23:16.018527 CKR = 1
7198 19:23:16.021861 DQ_P2S_RATIO = 8
7199 19:23:16.025021 ===================================
7200 19:23:16.028089 CA_P2S_RATIO = 8
7201 19:23:16.031396 DQ_CA_OPEN = 0
7202 19:23:16.031489 DQ_SEMI_OPEN = 0
7203 19:23:16.034609 CA_SEMI_OPEN = 0
7204 19:23:16.038302 CA_FULL_RATE = 0
7205 19:23:16.041269 DQ_CKDIV4_EN = 0
7206 19:23:16.044882 CA_CKDIV4_EN = 0
7207 19:23:16.048150 CA_PREDIV_EN = 0
7208 19:23:16.048236 PH8_DLY = 12
7209 19:23:16.051232 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7210 19:23:16.054819 DQ_AAMCK_DIV = 4
7211 19:23:16.057972 CA_AAMCK_DIV = 4
7212 19:23:16.061210 CA_ADMCK_DIV = 4
7213 19:23:16.064528 DQ_TRACK_CA_EN = 0
7214 19:23:16.068013 CA_PICK = 1600
7215 19:23:16.068108 CA_MCKIO = 1600
7216 19:23:16.071253 MCKIO_SEMI = 0
7217 19:23:16.074606 PLL_FREQ = 3068
7218 19:23:16.077891 DQ_UI_PI_RATIO = 32
7219 19:23:16.081235 CA_UI_PI_RATIO = 0
7220 19:23:16.084539 ===================================
7221 19:23:16.087567 ===================================
7222 19:23:16.091143 memory_type:LPDDR4
7223 19:23:16.091237 GP_NUM : 10
7224 19:23:16.093962 SRAM_EN : 1
7225 19:23:16.094057 MD32_EN : 0
7226 19:23:16.097512 ===================================
7227 19:23:16.101134 [ANA_INIT] >>>>>>>>>>>>>>
7228 19:23:16.104196 <<<<<< [CONFIGURE PHASE]: ANA_TX
7229 19:23:16.107183 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7230 19:23:16.111021 ===================================
7231 19:23:16.114284 data_rate = 3200,PCW = 0X7600
7232 19:23:16.117635 ===================================
7233 19:23:16.120249 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7234 19:23:16.126873 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7235 19:23:16.130843 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7236 19:23:16.136939 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7237 19:23:16.140252 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7238 19:23:16.143577 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7239 19:23:16.143663 [ANA_INIT] flow start
7240 19:23:16.147352 [ANA_INIT] PLL >>>>>>>>
7241 19:23:16.150351 [ANA_INIT] PLL <<<<<<<<
7242 19:23:16.153806 [ANA_INIT] MIDPI >>>>>>>>
7243 19:23:16.153893 [ANA_INIT] MIDPI <<<<<<<<
7244 19:23:16.156653 [ANA_INIT] DLL >>>>>>>>
7245 19:23:16.160058 [ANA_INIT] DLL <<<<<<<<
7246 19:23:16.160144 [ANA_INIT] flow end
7247 19:23:16.163628 ============ LP4 DIFF to SE enter ============
7248 19:23:16.170223 ============ LP4 DIFF to SE exit ============
7249 19:23:16.170309 [ANA_INIT] <<<<<<<<<<<<<
7250 19:23:16.173320 [Flow] Enable top DCM control >>>>>
7251 19:23:16.176821 [Flow] Enable top DCM control <<<<<
7252 19:23:16.180049 Enable DLL master slave shuffle
7253 19:23:16.186702 ==============================================================
7254 19:23:16.189928 Gating Mode config
7255 19:23:16.193227 ==============================================================
7256 19:23:16.196553 Config description:
7257 19:23:16.206242 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7258 19:23:16.213085 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7259 19:23:16.216244 SELPH_MODE 0: By rank 1: By Phase
7260 19:23:16.223165 ==============================================================
7261 19:23:16.226353 GAT_TRACK_EN = 1
7262 19:23:16.229621 RX_GATING_MODE = 2
7263 19:23:16.233018 RX_GATING_TRACK_MODE = 2
7264 19:23:16.233143 SELPH_MODE = 1
7265 19:23:16.236122 PICG_EARLY_EN = 1
7266 19:23:16.239438 VALID_LAT_VALUE = 1
7267 19:23:16.246351 ==============================================================
7268 19:23:16.249538 Enter into Gating configuration >>>>
7269 19:23:16.252835 Exit from Gating configuration <<<<
7270 19:23:16.256165 Enter into DVFS_PRE_config >>>>>
7271 19:23:16.266233 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7272 19:23:16.269243 Exit from DVFS_PRE_config <<<<<
7273 19:23:16.272387 Enter into PICG configuration >>>>
7274 19:23:16.276102 Exit from PICG configuration <<<<
7275 19:23:16.279328 [RX_INPUT] configuration >>>>>
7276 19:23:16.282625 [RX_INPUT] configuration <<<<<
7277 19:23:16.286066 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7278 19:23:16.292662 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7279 19:23:16.299104 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7280 19:23:16.305324 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7281 19:23:16.312016 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7282 19:23:16.315604 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7283 19:23:16.322013 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7284 19:23:16.325119 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7285 19:23:16.328713 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7286 19:23:16.332076 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7287 19:23:16.338734 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7288 19:23:16.341846 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7289 19:23:16.345195 ===================================
7290 19:23:16.348306 LPDDR4 DRAM CONFIGURATION
7291 19:23:16.351499 ===================================
7292 19:23:16.351662 EX_ROW_EN[0] = 0x0
7293 19:23:16.354673 EX_ROW_EN[1] = 0x0
7294 19:23:16.354765 LP4Y_EN = 0x0
7295 19:23:16.358055 WORK_FSP = 0x1
7296 19:23:16.361468 WL = 0x5
7297 19:23:16.361558 RL = 0x5
7298 19:23:16.364486 BL = 0x2
7299 19:23:16.364570 RPST = 0x0
7300 19:23:16.368097 RD_PRE = 0x0
7301 19:23:16.368187 WR_PRE = 0x1
7302 19:23:16.371265 WR_PST = 0x1
7303 19:23:16.371365 DBI_WR = 0x0
7304 19:23:16.374535 DBI_RD = 0x0
7305 19:23:16.374634 OTF = 0x1
7306 19:23:16.378238 ===================================
7307 19:23:16.381275 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7308 19:23:16.388195 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7309 19:23:16.391576 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7310 19:23:16.394773 ===================================
7311 19:23:16.398306 LPDDR4 DRAM CONFIGURATION
7312 19:23:16.401294 ===================================
7313 19:23:16.401500 EX_ROW_EN[0] = 0x10
7314 19:23:16.404584 EX_ROW_EN[1] = 0x0
7315 19:23:16.407722 LP4Y_EN = 0x0
7316 19:23:16.407941 WORK_FSP = 0x1
7317 19:23:16.410942 WL = 0x5
7318 19:23:16.411277 RL = 0x5
7319 19:23:16.414796 BL = 0x2
7320 19:23:16.415060 RPST = 0x0
7321 19:23:16.418264 RD_PRE = 0x0
7322 19:23:16.418666 WR_PRE = 0x1
7323 19:23:16.421560 WR_PST = 0x1
7324 19:23:16.422011 DBI_WR = 0x0
7325 19:23:16.424575 DBI_RD = 0x0
7326 19:23:16.425075 OTF = 0x1
7327 19:23:16.427658 ===================================
7328 19:23:16.434476 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7329 19:23:16.434927 ==
7330 19:23:16.437669 Dram Type= 6, Freq= 0, CH_0, rank 0
7331 19:23:16.441105 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7332 19:23:16.444365 ==
7333 19:23:16.445074 [Duty_Offset_Calibration]
7334 19:23:16.447546 B0:1 B1:-1 CA:0
7335 19:23:16.448100
7336 19:23:16.450547 [DutyScan_Calibration_Flow] k_type=0
7337 19:23:16.459248
7338 19:23:16.459329 ==CLK 0==
7339 19:23:16.462673 Final CLK duty delay cell = 0
7340 19:23:16.466029 [0] MAX Duty = 5125%(X100), DQS PI = 20
7341 19:23:16.469067 [0] MIN Duty = 4907%(X100), DQS PI = 6
7342 19:23:16.469177 [0] AVG Duty = 5016%(X100)
7343 19:23:16.472877
7344 19:23:16.475918 CH0 CLK Duty spec in!! Max-Min= 218%
7345 19:23:16.478991 [DutyScan_Calibration_Flow] ====Done====
7346 19:23:16.479062
7347 19:23:16.482130 [DutyScan_Calibration_Flow] k_type=1
7348 19:23:16.498182
7349 19:23:16.498256 ==DQS 0 ==
7350 19:23:16.501482 Final DQS duty delay cell = -4
7351 19:23:16.504862 [-4] MAX Duty = 4969%(X100), DQS PI = 18
7352 19:23:16.508141 [-4] MIN Duty = 4844%(X100), DQS PI = 48
7353 19:23:16.511563 [-4] AVG Duty = 4906%(X100)
7354 19:23:16.511632
7355 19:23:16.511691 ==DQS 1 ==
7356 19:23:16.514729 Final DQS duty delay cell = 0
7357 19:23:16.518456 [0] MAX Duty = 5156%(X100), DQS PI = 2
7358 19:23:16.521766 [0] MIN Duty = 5031%(X100), DQS PI = 18
7359 19:23:16.524896 [0] AVG Duty = 5093%(X100)
7360 19:23:16.525052
7361 19:23:16.528028 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7362 19:23:16.528097
7363 19:23:16.531275 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7364 19:23:16.534598 [DutyScan_Calibration_Flow] ====Done====
7365 19:23:16.534675
7366 19:23:16.537817 [DutyScan_Calibration_Flow] k_type=3
7367 19:23:16.556347
7368 19:23:16.556435 ==DQM 0 ==
7369 19:23:16.560022 Final DQM duty delay cell = 0
7370 19:23:16.562603 [0] MAX Duty = 5124%(X100), DQS PI = 22
7371 19:23:16.565621 [0] MIN Duty = 4907%(X100), DQS PI = 10
7372 19:23:16.569302 [0] AVG Duty = 5015%(X100)
7373 19:23:16.569424
7374 19:23:16.569490 ==DQM 1 ==
7375 19:23:16.572763 Final DQM duty delay cell = 0
7376 19:23:16.575876 [0] MAX Duty = 5000%(X100), DQS PI = 8
7377 19:23:16.578931 [0] MIN Duty = 4782%(X100), DQS PI = 20
7378 19:23:16.582661 [0] AVG Duty = 4891%(X100)
7379 19:23:16.582737
7380 19:23:16.585575 CH0 DQM 0 Duty spec in!! Max-Min= 217%
7381 19:23:16.585664
7382 19:23:16.588701 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7383 19:23:16.591960 [DutyScan_Calibration_Flow] ====Done====
7384 19:23:16.592066
7385 19:23:16.595530 [DutyScan_Calibration_Flow] k_type=2
7386 19:23:16.612668
7387 19:23:16.612772 ==DQ 0 ==
7388 19:23:16.615750 Final DQ duty delay cell = -4
7389 19:23:16.618936 [-4] MAX Duty = 5031%(X100), DQS PI = 26
7390 19:23:16.621962 [-4] MIN Duty = 4876%(X100), DQS PI = 52
7391 19:23:16.625847 [-4] AVG Duty = 4953%(X100)
7392 19:23:16.625920
7393 19:23:16.625980 ==DQ 1 ==
7394 19:23:16.628497 Final DQ duty delay cell = 0
7395 19:23:16.631956 [0] MAX Duty = 5125%(X100), DQS PI = 2
7396 19:23:16.635617 [0] MIN Duty = 5000%(X100), DQS PI = 36
7397 19:23:16.638865 [0] AVG Duty = 5062%(X100)
7398 19:23:16.638965
7399 19:23:16.642117 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7400 19:23:16.642198
7401 19:23:16.645611 CH0 DQ 1 Duty spec in!! Max-Min= 125%
7402 19:23:16.648665 [DutyScan_Calibration_Flow] ====Done====
7403 19:23:16.648747 ==
7404 19:23:16.651800 Dram Type= 6, Freq= 0, CH_1, rank 0
7405 19:23:16.655438 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7406 19:23:16.655519 ==
7407 19:23:16.658783 [Duty_Offset_Calibration]
7408 19:23:16.658863 B0:-1 B1:1 CA:1
7409 19:23:16.658927
7410 19:23:16.661571 [DutyScan_Calibration_Flow] k_type=0
7411 19:23:16.673211
7412 19:23:16.673364 ==CLK 0==
7413 19:23:16.676125 Final CLK duty delay cell = 0
7414 19:23:16.679519 [0] MAX Duty = 5187%(X100), DQS PI = 24
7415 19:23:16.682544 [0] MIN Duty = 4969%(X100), DQS PI = 0
7416 19:23:16.686266 [0] AVG Duty = 5078%(X100)
7417 19:23:16.686356
7418 19:23:16.689565 CH1 CLK Duty spec in!! Max-Min= 218%
7419 19:23:16.692594 [DutyScan_Calibration_Flow] ====Done====
7420 19:23:16.692680
7421 19:23:16.696284 [DutyScan_Calibration_Flow] k_type=1
7422 19:23:16.712511
7423 19:23:16.712600 ==DQS 0 ==
7424 19:23:16.715926 Final DQS duty delay cell = 0
7425 19:23:16.719166 [0] MAX Duty = 5124%(X100), DQS PI = 18
7426 19:23:16.722449 [0] MIN Duty = 4907%(X100), DQS PI = 10
7427 19:23:16.725658 [0] AVG Duty = 5015%(X100)
7428 19:23:16.725730
7429 19:23:16.725790 ==DQS 1 ==
7430 19:23:16.729162 Final DQS duty delay cell = 0
7431 19:23:16.731871 [0] MAX Duty = 5093%(X100), DQS PI = 28
7432 19:23:16.735143 [0] MIN Duty = 4969%(X100), DQS PI = 54
7433 19:23:16.738941 [0] AVG Duty = 5031%(X100)
7434 19:23:16.739011
7435 19:23:16.742057 CH1 DQS 0 Duty spec in!! Max-Min= 217%
7436 19:23:16.742128
7437 19:23:16.745087 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7438 19:23:16.748509 [DutyScan_Calibration_Flow] ====Done====
7439 19:23:16.748592
7440 19:23:16.751788 [DutyScan_Calibration_Flow] k_type=3
7441 19:23:16.769656
7442 19:23:16.769746 ==DQM 0 ==
7443 19:23:16.772937 Final DQM duty delay cell = 0
7444 19:23:16.776317 [0] MAX Duty = 5187%(X100), DQS PI = 18
7445 19:23:16.779424 [0] MIN Duty = 5031%(X100), DQS PI = 6
7446 19:23:16.782392 [0] AVG Duty = 5109%(X100)
7447 19:23:16.782471
7448 19:23:16.782533 ==DQM 1 ==
7449 19:23:16.786148 Final DQM duty delay cell = 0
7450 19:23:16.789284 [0] MAX Duty = 5125%(X100), DQS PI = 0
7451 19:23:16.792655 [0] MIN Duty = 4969%(X100), DQS PI = 28
7452 19:23:16.795934 [0] AVG Duty = 5047%(X100)
7453 19:23:16.796031
7454 19:23:16.799175 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7455 19:23:16.799255
7456 19:23:16.802125 CH1 DQM 1 Duty spec in!! Max-Min= 156%
7457 19:23:16.805577 [DutyScan_Calibration_Flow] ====Done====
7458 19:23:16.805655
7459 19:23:16.808835 [DutyScan_Calibration_Flow] k_type=2
7460 19:23:16.826228
7461 19:23:16.826309 ==DQ 0 ==
7462 19:23:16.829706 Final DQ duty delay cell = 0
7463 19:23:16.832730 [0] MAX Duty = 5187%(X100), DQS PI = 32
7464 19:23:16.835915 [0] MIN Duty = 4906%(X100), DQS PI = 8
7465 19:23:16.835992 [0] AVG Duty = 5046%(X100)
7466 19:23:16.839165
7467 19:23:16.839273 ==DQ 1 ==
7468 19:23:16.842426 Final DQ duty delay cell = 0
7469 19:23:16.845768 [0] MAX Duty = 5156%(X100), DQS PI = 8
7470 19:23:16.849612 [0] MIN Duty = 4969%(X100), DQS PI = 56
7471 19:23:16.849694 [0] AVG Duty = 5062%(X100)
7472 19:23:16.852631
7473 19:23:16.855944 CH1 DQ 0 Duty spec in!! Max-Min= 281%
7474 19:23:16.856027
7475 19:23:16.859366 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7476 19:23:16.862775 [DutyScan_Calibration_Flow] ====Done====
7477 19:23:16.865970 nWR fixed to 30
7478 19:23:16.866053 [ModeRegInit_LP4] CH0 RK0
7479 19:23:16.869078 [ModeRegInit_LP4] CH0 RK1
7480 19:23:16.872566 [ModeRegInit_LP4] CH1 RK0
7481 19:23:16.875788 [ModeRegInit_LP4] CH1 RK1
7482 19:23:16.875870 match AC timing 5
7483 19:23:16.882354 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7484 19:23:16.885839 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7485 19:23:16.888882 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7486 19:23:16.895603 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7487 19:23:16.898841 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7488 19:23:16.898923 [MiockJmeterHQA]
7489 19:23:16.898988
7490 19:23:16.902120 [DramcMiockJmeter] u1RxGatingPI = 0
7491 19:23:16.905202 0 : 4252, 4027
7492 19:23:16.905278 4 : 4363, 4138
7493 19:23:16.909176 8 : 4253, 4027
7494 19:23:16.909259 12 : 4363, 4137
7495 19:23:16.911623 16 : 4253, 4027
7496 19:23:16.911714 20 : 4252, 4027
7497 19:23:16.911817 24 : 4252, 4027
7498 19:23:16.914935 28 : 4253, 4029
7499 19:23:16.915017 32 : 4361, 4138
7500 19:23:16.918214 36 : 4253, 4026
7501 19:23:16.918327 40 : 4250, 4027
7502 19:23:16.921932 44 : 4252, 4027
7503 19:23:16.922013 48 : 4253, 4029
7504 19:23:16.925001 52 : 4250, 4027
7505 19:23:16.925082 56 : 4363, 4137
7506 19:23:16.925146 60 : 4361, 4137
7507 19:23:16.928285 64 : 4249, 4027
7508 19:23:16.928370 68 : 4250, 4026
7509 19:23:16.931335 72 : 4250, 4026
7510 19:23:16.931416 76 : 4250, 4027
7511 19:23:16.934556 80 : 4253, 4029
7512 19:23:16.934637 84 : 4361, 4138
7513 19:23:16.938327 88 : 4250, 4025
7514 19:23:16.938410 92 : 4250, 428
7515 19:23:16.938476 96 : 4363, 0
7516 19:23:16.941298 100 : 4249, 0
7517 19:23:16.941422 104 : 4250, 0
7518 19:23:16.944632 108 : 4253, 0
7519 19:23:16.944715 112 : 4252, 0
7520 19:23:16.944790 116 : 4250, 0
7521 19:23:16.947871 120 : 4252, 0
7522 19:23:16.947964 124 : 4250, 0
7523 19:23:16.948031 128 : 4361, 0
7524 19:23:16.951189 132 : 4360, 0
7525 19:23:16.951271 136 : 4250, 0
7526 19:23:16.955018 140 : 4249, 0
7527 19:23:16.955101 144 : 4363, 0
7528 19:23:16.955166 148 : 4252, 0
7529 19:23:16.958156 152 : 4250, 0
7530 19:23:16.958239 156 : 4249, 0
7531 19:23:16.961270 160 : 4250, 0
7532 19:23:16.961411 164 : 4250, 0
7533 19:23:16.961522 168 : 4249, 0
7534 19:23:16.964620 172 : 4252, 0
7535 19:23:16.964715 176 : 4252, 0
7536 19:23:16.967725 180 : 4249, 0
7537 19:23:16.967808 184 : 4252, 0
7538 19:23:16.967873 188 : 4361, 0
7539 19:23:16.971051 192 : 4360, 0
7540 19:23:16.971133 196 : 4363, 0
7541 19:23:16.974375 200 : 4250, 0
7542 19:23:16.974462 204 : 4250, 0
7543 19:23:16.974528 208 : 4250, 0
7544 19:23:16.977513 212 : 4253, 0
7545 19:23:16.977595 216 : 4250, 0
7546 19:23:16.977661 220 : 4249, 0
7547 19:23:16.981127 224 : 4252, 276
7548 19:23:16.981209 228 : 4361, 3626
7549 19:23:16.984322 232 : 4360, 4138
7550 19:23:16.984405 236 : 4250, 4026
7551 19:23:16.987569 240 : 4361, 4137
7552 19:23:16.987652 244 : 4250, 4027
7553 19:23:16.990986 248 : 4249, 4027
7554 19:23:16.991069 252 : 4250, 4026
7555 19:23:16.994198 256 : 4253, 4029
7556 19:23:16.994280 260 : 4250, 4027
7557 19:23:16.997599 264 : 4249, 4027
7558 19:23:16.997681 268 : 4360, 4137
7559 19:23:17.001149 272 : 4250, 4026
7560 19:23:17.001231 276 : 4250, 4027
7561 19:23:17.004115 280 : 4360, 4138
7562 19:23:17.004198 284 : 4249, 4027
7563 19:23:17.004263 288 : 4250, 4026
7564 19:23:17.007270 292 : 4360, 4137
7565 19:23:17.007352 296 : 4250, 4027
7566 19:23:17.010486 300 : 4249, 4027
7567 19:23:17.010568 304 : 4250, 4026
7568 19:23:17.014199 308 : 4253, 4029
7569 19:23:17.014286 312 : 4250, 4027
7570 19:23:17.017243 316 : 4250, 4027
7571 19:23:17.017325 320 : 4361, 4137
7572 19:23:17.020603 324 : 4250, 4027
7573 19:23:17.020685 328 : 4250, 4027
7574 19:23:17.023878 332 : 4361, 4138
7575 19:23:17.023961 336 : 4250, 3789
7576 19:23:17.027254 340 : 4250, 1923
7577 19:23:17.027337
7578 19:23:17.027401 MIOCK jitter meter ch=0
7579 19:23:17.027495
7580 19:23:17.030306 1T = (340-92) = 248 dly cells
7581 19:23:17.037301 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps
7582 19:23:17.037424 ==
7583 19:23:17.040638 Dram Type= 6, Freq= 0, CH_0, rank 0
7584 19:23:17.043957 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7585 19:23:17.044038 ==
7586 19:23:17.050287 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7587 19:23:17.053501 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7588 19:23:17.056647 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7589 19:23:17.063123 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7590 19:23:17.073639 [CA 0] Center 43 (13~74) winsize 62
7591 19:23:17.076938 [CA 1] Center 42 (12~73) winsize 62
7592 19:23:17.080190 [CA 2] Center 38 (9~68) winsize 60
7593 19:23:17.083386 [CA 3] Center 38 (8~68) winsize 61
7594 19:23:17.086282 [CA 4] Center 36 (7~66) winsize 60
7595 19:23:17.089974 [CA 5] Center 35 (6~65) winsize 60
7596 19:23:17.090056
7597 19:23:17.093084 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7598 19:23:17.093166
7599 19:23:17.099769 [CATrainingPosCal] consider 1 rank data
7600 19:23:17.099851 u2DelayCellTimex100 = 262/100 ps
7601 19:23:17.106285 CA0 delay=43 (13~74),Diff = 8 PI (29 cell)
7602 19:23:17.109404 CA1 delay=42 (12~73),Diff = 7 PI (26 cell)
7603 19:23:17.112556 CA2 delay=38 (9~68),Diff = 3 PI (11 cell)
7604 19:23:17.116047 CA3 delay=38 (8~68),Diff = 3 PI (11 cell)
7605 19:23:17.119277 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7606 19:23:17.122913 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7607 19:23:17.122994
7608 19:23:17.125844 CA PerBit enable=1, Macro0, CA PI delay=35
7609 19:23:17.125924
7610 19:23:17.129349 [CBTSetCACLKResult] CA Dly = 35
7611 19:23:17.132520 CS Dly: 11 (0~42)
7612 19:23:17.135922 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7613 19:23:17.139017 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7614 19:23:17.139097 ==
7615 19:23:17.142659 Dram Type= 6, Freq= 0, CH_0, rank 1
7616 19:23:17.149050 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7617 19:23:17.149157 ==
7618 19:23:17.152155 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7619 19:23:17.159111 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7620 19:23:17.162379 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7621 19:23:17.168917 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7622 19:23:17.177206 [CA 0] Center 42 (12~73) winsize 62
7623 19:23:17.179922 [CA 1] Center 43 (13~73) winsize 61
7624 19:23:17.183244 [CA 2] Center 37 (8~67) winsize 60
7625 19:23:17.186504 [CA 3] Center 37 (7~67) winsize 61
7626 19:23:17.189766 [CA 4] Center 35 (6~65) winsize 60
7627 19:23:17.193014 [CA 5] Center 35 (5~65) winsize 61
7628 19:23:17.193094
7629 19:23:17.196681 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7630 19:23:17.196762
7631 19:23:17.203177 [CATrainingPosCal] consider 2 rank data
7632 19:23:17.203258 u2DelayCellTimex100 = 262/100 ps
7633 19:23:17.209641 CA0 delay=43 (13~73),Diff = 8 PI (29 cell)
7634 19:23:17.212987 CA1 delay=43 (13~73),Diff = 8 PI (29 cell)
7635 19:23:17.216319 CA2 delay=38 (9~67),Diff = 3 PI (11 cell)
7636 19:23:17.219508 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7637 19:23:17.223085 CA4 delay=36 (7~65),Diff = 1 PI (3 cell)
7638 19:23:17.226055 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7639 19:23:17.226135
7640 19:23:17.229642 CA PerBit enable=1, Macro0, CA PI delay=35
7641 19:23:17.229723
7642 19:23:17.232562 [CBTSetCACLKResult] CA Dly = 35
7643 19:23:17.236079 CS Dly: 12 (0~44)
7644 19:23:17.239175 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7645 19:23:17.242294 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7646 19:23:17.242375
7647 19:23:17.246164 ----->DramcWriteLeveling(PI) begin...
7648 19:23:17.249263 ==
7649 19:23:17.249369 Dram Type= 6, Freq= 0, CH_0, rank 0
7650 19:23:17.255759 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7651 19:23:17.255840 ==
7652 19:23:17.258943 Write leveling (Byte 0): 36 => 36
7653 19:23:17.262615 Write leveling (Byte 1): 26 => 26
7654 19:23:17.265706 DramcWriteLeveling(PI) end<-----
7655 19:23:17.265786
7656 19:23:17.265857 ==
7657 19:23:17.269121 Dram Type= 6, Freq= 0, CH_0, rank 0
7658 19:23:17.272340 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7659 19:23:17.272420 ==
7660 19:23:17.275543 [Gating] SW mode calibration
7661 19:23:17.282080 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7662 19:23:17.288979 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7663 19:23:17.292220 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7664 19:23:17.295671 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7665 19:23:17.302217 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7666 19:23:17.305238 1 4 12 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
7667 19:23:17.308358 1 4 16 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7668 19:23:17.314840 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7669 19:23:17.318326 1 4 24 | B1->B0 | 2c2c 3434 | 1 1 | (0 0) (1 1)
7670 19:23:17.321666 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7671 19:23:17.328238 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7672 19:23:17.331573 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7673 19:23:17.334640 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7674 19:23:17.341045 1 5 12 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (1 0)
7675 19:23:17.344441 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7676 19:23:17.347739 1 5 20 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
7677 19:23:17.354387 1 5 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
7678 19:23:17.357570 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7679 19:23:17.361201 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7680 19:23:17.367695 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7681 19:23:17.370732 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7682 19:23:17.374485 1 6 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7683 19:23:17.381042 1 6 16 | B1->B0 | 2323 4545 | 0 1 | (0 0) (0 0)
7684 19:23:17.384229 1 6 20 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
7685 19:23:17.387438 1 6 24 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
7686 19:23:17.394156 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7687 19:23:17.397425 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7688 19:23:17.400671 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7689 19:23:17.407220 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7690 19:23:17.410394 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7691 19:23:17.413628 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7692 19:23:17.420074 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7693 19:23:17.424079 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7694 19:23:17.427257 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7695 19:23:17.433788 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7696 19:23:17.437034 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7697 19:23:17.440211 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7698 19:23:17.446496 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7699 19:23:17.450303 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7700 19:23:17.453283 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7701 19:23:17.459569 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7702 19:23:17.463247 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7703 19:23:17.466268 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7704 19:23:17.472862 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7705 19:23:17.476609 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7706 19:23:17.479634 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7707 19:23:17.486054 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7708 19:23:17.486136 Total UI for P1: 0, mck2ui 16
7709 19:23:17.492550 best dqsien dly found for B0: ( 1, 9, 12)
7710 19:23:17.495922 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7711 19:23:17.499142 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7712 19:23:17.506125 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7713 19:23:17.506207 Total UI for P1: 0, mck2ui 16
7714 19:23:17.512552 best dqsien dly found for B1: ( 1, 9, 22)
7715 19:23:17.515943 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7716 19:23:17.519073 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7717 19:23:17.519149
7718 19:23:17.522709 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7719 19:23:17.525921 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7720 19:23:17.529177 [Gating] SW calibration Done
7721 19:23:17.529278 ==
7722 19:23:17.531870 Dram Type= 6, Freq= 0, CH_0, rank 0
7723 19:23:17.535110 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7724 19:23:17.535188 ==
7725 19:23:17.538631 RX Vref Scan: 0
7726 19:23:17.538709
7727 19:23:17.541881 RX Vref 0 -> 0, step: 1
7728 19:23:17.541968
7729 19:23:17.542033 RX Delay 0 -> 252, step: 8
7730 19:23:17.548817 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7731 19:23:17.551941 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7732 19:23:17.555149 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7733 19:23:17.558591 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7734 19:23:17.561788 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7735 19:23:17.568455 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7736 19:23:17.571912 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
7737 19:23:17.575034 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
7738 19:23:17.578008 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7739 19:23:17.581427 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7740 19:23:17.588249 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7741 19:23:17.591170 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7742 19:23:17.594455 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7743 19:23:17.597826 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7744 19:23:17.604372 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7745 19:23:17.608372 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7746 19:23:17.608456 ==
7747 19:23:17.611279 Dram Type= 6, Freq= 0, CH_0, rank 0
7748 19:23:17.614666 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7749 19:23:17.614752 ==
7750 19:23:17.618265 DQS Delay:
7751 19:23:17.618428 DQS0 = 0, DQS1 = 0
7752 19:23:17.618514 DQM Delay:
7753 19:23:17.621232 DQM0 = 133, DQM1 = 126
7754 19:23:17.621411 DQ Delay:
7755 19:23:17.624566 DQ0 =135, DQ1 =135, DQ2 =131, DQ3 =131
7756 19:23:17.627197 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =143
7757 19:23:17.634221 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =119
7758 19:23:17.637286 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =131
7759 19:23:17.637484
7760 19:23:17.637597
7761 19:23:17.637697 ==
7762 19:23:17.640592 Dram Type= 6, Freq= 0, CH_0, rank 0
7763 19:23:17.643938 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7764 19:23:17.644088 ==
7765 19:23:17.644213
7766 19:23:17.644322
7767 19:23:17.647242 TX Vref Scan disable
7768 19:23:17.650603 == TX Byte 0 ==
7769 19:23:17.653747 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7770 19:23:17.656870 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7771 19:23:17.659971 == TX Byte 1 ==
7772 19:23:17.663318 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7773 19:23:17.666614 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7774 19:23:17.667069 ==
7775 19:23:17.669934 Dram Type= 6, Freq= 0, CH_0, rank 0
7776 19:23:17.676907 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7777 19:23:17.677535 ==
7778 19:23:17.688824
7779 19:23:17.692680 TX Vref early break, caculate TX vref
7780 19:23:17.695880 TX Vref=16, minBit 1, minWin=22, winSum=369
7781 19:23:17.698935 TX Vref=18, minBit 0, minWin=23, winSum=380
7782 19:23:17.702441 TX Vref=20, minBit 1, minWin=23, winSum=387
7783 19:23:17.705796 TX Vref=22, minBit 1, minWin=24, winSum=401
7784 19:23:17.708933 TX Vref=24, minBit 3, minWin=24, winSum=405
7785 19:23:17.715606 TX Vref=26, minBit 0, minWin=24, winSum=411
7786 19:23:17.718650 TX Vref=28, minBit 4, minWin=25, winSum=416
7787 19:23:17.721661 TX Vref=30, minBit 0, minWin=24, winSum=409
7788 19:23:17.725565 TX Vref=32, minBit 0, minWin=24, winSum=398
7789 19:23:17.728864 TX Vref=34, minBit 4, minWin=22, winSum=388
7790 19:23:17.735467 [TxChooseVref] Worse bit 4, Min win 25, Win sum 416, Final Vref 28
7791 19:23:17.735944
7792 19:23:17.738480 Final TX Range 0 Vref 28
7793 19:23:17.738926
7794 19:23:17.739343 ==
7795 19:23:17.741494 Dram Type= 6, Freq= 0, CH_0, rank 0
7796 19:23:17.744880 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7797 19:23:17.745376 ==
7798 19:23:17.745772
7799 19:23:17.746123
7800 19:23:17.748110 TX Vref Scan disable
7801 19:23:17.755372 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
7802 19:23:17.755827 == TX Byte 0 ==
7803 19:23:17.758677 u2DelayCellOfst[0]=14 cells (4 PI)
7804 19:23:17.761878 u2DelayCellOfst[1]=18 cells (5 PI)
7805 19:23:17.764910 u2DelayCellOfst[2]=14 cells (4 PI)
7806 19:23:17.768263 u2DelayCellOfst[3]=18 cells (5 PI)
7807 19:23:17.771572 u2DelayCellOfst[4]=11 cells (3 PI)
7808 19:23:17.774795 u2DelayCellOfst[5]=0 cells (0 PI)
7809 19:23:17.778102 u2DelayCellOfst[6]=18 cells (5 PI)
7810 19:23:17.781682 u2DelayCellOfst[7]=22 cells (6 PI)
7811 19:23:17.784966 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7812 19:23:17.788086 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7813 19:23:17.790860 == TX Byte 1 ==
7814 19:23:17.794570 u2DelayCellOfst[8]=0 cells (0 PI)
7815 19:23:17.797672 u2DelayCellOfst[9]=0 cells (0 PI)
7816 19:23:17.801267 u2DelayCellOfst[10]=3 cells (1 PI)
7817 19:23:17.801412 u2DelayCellOfst[11]=0 cells (0 PI)
7818 19:23:17.804556 u2DelayCellOfst[12]=11 cells (3 PI)
7819 19:23:17.807809 u2DelayCellOfst[13]=11 cells (3 PI)
7820 19:23:17.810792 u2DelayCellOfst[14]=14 cells (4 PI)
7821 19:23:17.814295 u2DelayCellOfst[15]=11 cells (3 PI)
7822 19:23:17.820976 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7823 19:23:17.824161 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7824 19:23:17.824247 DramC Write-DBI on
7825 19:23:17.827080 ==
7826 19:23:17.827163 Dram Type= 6, Freq= 0, CH_0, rank 0
7827 19:23:17.833948 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7828 19:23:17.834029 ==
7829 19:23:17.834092
7830 19:23:17.834153
7831 19:23:17.837139 TX Vref Scan disable
7832 19:23:17.837252 == TX Byte 0 ==
7833 19:23:17.843912 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7834 19:23:17.843998 == TX Byte 1 ==
7835 19:23:17.847496 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7836 19:23:17.850733 DramC Write-DBI off
7837 19:23:17.850826
7838 19:23:17.850901 [DATLAT]
7839 19:23:17.853403 Freq=1600, CH0 RK0
7840 19:23:17.853495
7841 19:23:17.853571 DATLAT Default: 0xf
7842 19:23:17.857257 0, 0xFFFF, sum = 0
7843 19:23:17.857396 1, 0xFFFF, sum = 0
7844 19:23:17.860537 2, 0xFFFF, sum = 0
7845 19:23:17.860653 3, 0xFFFF, sum = 0
7846 19:23:17.863840 4, 0xFFFF, sum = 0
7847 19:23:17.867139 5, 0xFFFF, sum = 0
7848 19:23:17.867268 6, 0xFFFF, sum = 0
7849 19:23:17.870303 7, 0xFFFF, sum = 0
7850 19:23:17.870430 8, 0xFFFF, sum = 0
7851 19:23:17.873587 9, 0xFFFF, sum = 0
7852 19:23:17.873728 10, 0xFFFF, sum = 0
7853 19:23:17.877048 11, 0xFFFF, sum = 0
7854 19:23:17.877260 12, 0xFFFF, sum = 0
7855 19:23:17.879775 13, 0xFFFF, sum = 0
7856 19:23:17.879974 14, 0x0, sum = 1
7857 19:23:17.883026 15, 0x0, sum = 2
7858 19:23:17.883274 16, 0x0, sum = 3
7859 19:23:17.886918 17, 0x0, sum = 4
7860 19:23:17.887213 best_step = 15
7861 19:23:17.887468
7862 19:23:17.887718 ==
7863 19:23:17.890148 Dram Type= 6, Freq= 0, CH_0, rank 0
7864 19:23:17.893410 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7865 19:23:17.896721 ==
7866 19:23:17.897152 RX Vref Scan: 1
7867 19:23:17.897611
7868 19:23:17.899911 Set Vref Range= 24 -> 127
7869 19:23:17.900330
7870 19:23:17.903108 RX Vref 24 -> 127, step: 1
7871 19:23:17.903566
7872 19:23:17.903954 RX Delay 11 -> 252, step: 4
7873 19:23:17.904448
7874 19:23:17.906790 Set Vref, RX VrefLevel [Byte0]: 24
7875 19:23:17.909885 [Byte1]: 24
7876 19:23:17.913640
7877 19:23:17.914250 Set Vref, RX VrefLevel [Byte0]: 25
7878 19:23:17.917044 [Byte1]: 25
7879 19:23:17.921816
7880 19:23:17.922261 Set Vref, RX VrefLevel [Byte0]: 26
7881 19:23:17.927956 [Byte1]: 26
7882 19:23:17.928386
7883 19:23:17.931160 Set Vref, RX VrefLevel [Byte0]: 27
7884 19:23:17.934317 [Byte1]: 27
7885 19:23:17.934745
7886 19:23:17.938158 Set Vref, RX VrefLevel [Byte0]: 28
7887 19:23:17.940888 [Byte1]: 28
7888 19:23:17.944748
7889 19:23:17.945169 Set Vref, RX VrefLevel [Byte0]: 29
7890 19:23:17.948105 [Byte1]: 29
7891 19:23:17.952568
7892 19:23:17.953099 Set Vref, RX VrefLevel [Byte0]: 30
7893 19:23:17.955519 [Byte1]: 30
7894 19:23:17.959777
7895 19:23:17.960225 Set Vref, RX VrefLevel [Byte0]: 31
7896 19:23:17.963154 [Byte1]: 31
7897 19:23:17.967676
7898 19:23:17.968233 Set Vref, RX VrefLevel [Byte0]: 32
7899 19:23:17.970777 [Byte1]: 32
7900 19:23:17.974695
7901 19:23:17.975103 Set Vref, RX VrefLevel [Byte0]: 33
7902 19:23:17.977906 [Byte1]: 33
7903 19:23:17.982574
7904 19:23:17.983059 Set Vref, RX VrefLevel [Byte0]: 34
7905 19:23:17.985954 [Byte1]: 34
7906 19:23:17.989927
7907 19:23:17.990360 Set Vref, RX VrefLevel [Byte0]: 35
7908 19:23:17.993534 [Byte1]: 35
7909 19:23:17.997677
7910 19:23:17.998143 Set Vref, RX VrefLevel [Byte0]: 36
7911 19:23:18.001300 [Byte1]: 36
7912 19:23:18.005432
7913 19:23:18.005916 Set Vref, RX VrefLevel [Byte0]: 37
7914 19:23:18.008534 [Byte1]: 37
7915 19:23:18.013170
7916 19:23:18.013620 Set Vref, RX VrefLevel [Byte0]: 38
7917 19:23:18.016098 [Byte1]: 38
7918 19:23:18.020386
7919 19:23:18.020807 Set Vref, RX VrefLevel [Byte0]: 39
7920 19:23:18.023657 [Byte1]: 39
7921 19:23:18.028258
7922 19:23:18.028766 Set Vref, RX VrefLevel [Byte0]: 40
7923 19:23:18.031381 [Byte1]: 40
7924 19:23:18.036097
7925 19:23:18.036548 Set Vref, RX VrefLevel [Byte0]: 41
7926 19:23:18.038843 [Byte1]: 41
7927 19:23:18.043189
7928 19:23:18.043597 Set Vref, RX VrefLevel [Byte0]: 42
7929 19:23:18.046854 [Byte1]: 42
7930 19:23:18.051305
7931 19:23:18.051730 Set Vref, RX VrefLevel [Byte0]: 43
7932 19:23:18.054558 [Byte1]: 43
7933 19:23:18.058931
7934 19:23:18.059358 Set Vref, RX VrefLevel [Byte0]: 44
7935 19:23:18.062167 [Byte1]: 44
7936 19:23:18.066324
7937 19:23:18.066739 Set Vref, RX VrefLevel [Byte0]: 45
7938 19:23:18.069540 [Byte1]: 45
7939 19:23:18.074009
7940 19:23:18.074416 Set Vref, RX VrefLevel [Byte0]: 46
7941 19:23:18.077129 [Byte1]: 46
7942 19:23:18.081198
7943 19:23:18.081683 Set Vref, RX VrefLevel [Byte0]: 47
7944 19:23:18.084374 [Byte1]: 47
7945 19:23:18.089044
7946 19:23:18.089494 Set Vref, RX VrefLevel [Byte0]: 48
7947 19:23:18.092435 [Byte1]: 48
7948 19:23:18.096911
7949 19:23:18.097519 Set Vref, RX VrefLevel [Byte0]: 49
7950 19:23:18.100058 [Byte1]: 49
7951 19:23:18.104598
7952 19:23:18.105213 Set Vref, RX VrefLevel [Byte0]: 50
7953 19:23:18.107523 [Byte1]: 50
7954 19:23:18.112134
7955 19:23:18.112560 Set Vref, RX VrefLevel [Byte0]: 51
7956 19:23:18.115442 [Byte1]: 51
7957 19:23:18.119298
7958 19:23:18.119741 Set Vref, RX VrefLevel [Byte0]: 52
7959 19:23:18.125983 [Byte1]: 52
7960 19:23:18.126409
7961 19:23:18.129149 Set Vref, RX VrefLevel [Byte0]: 53
7962 19:23:18.132308 [Byte1]: 53
7963 19:23:18.132741
7964 19:23:18.135667 Set Vref, RX VrefLevel [Byte0]: 54
7965 19:23:18.138826 [Byte1]: 54
7966 19:23:18.142760
7967 19:23:18.143172 Set Vref, RX VrefLevel [Byte0]: 55
7968 19:23:18.145937 [Byte1]: 55
7969 19:23:18.149885
7970 19:23:18.150295 Set Vref, RX VrefLevel [Byte0]: 56
7971 19:23:18.152878 [Byte1]: 56
7972 19:23:18.157843
7973 19:23:18.158204 Set Vref, RX VrefLevel [Byte0]: 57
7974 19:23:18.160989 [Byte1]: 57
7975 19:23:18.165514
7976 19:23:18.165922 Set Vref, RX VrefLevel [Byte0]: 58
7977 19:23:18.168634 [Byte1]: 58
7978 19:23:18.172989
7979 19:23:18.173627 Set Vref, RX VrefLevel [Byte0]: 59
7980 19:23:18.176112 [Byte1]: 59
7981 19:23:18.180610
7982 19:23:18.181036 Set Vref, RX VrefLevel [Byte0]: 60
7983 19:23:18.183833 [Byte1]: 60
7984 19:23:18.187944
7985 19:23:18.188476 Set Vref, RX VrefLevel [Byte0]: 61
7986 19:23:18.191153 [Byte1]: 61
7987 19:23:18.195720
7988 19:23:18.196151 Set Vref, RX VrefLevel [Byte0]: 62
7989 19:23:18.198960 [Byte1]: 62
7990 19:23:18.203403
7991 19:23:18.204111 Set Vref, RX VrefLevel [Byte0]: 63
7992 19:23:18.206411 [Byte1]: 63
7993 19:23:18.211097
7994 19:23:18.211573 Set Vref, RX VrefLevel [Byte0]: 64
7995 19:23:18.214319 [Byte1]: 64
7996 19:23:18.218381
7997 19:23:18.218817 Set Vref, RX VrefLevel [Byte0]: 65
7998 19:23:18.224840 [Byte1]: 65
7999 19:23:18.225363
8000 19:23:18.228163 Set Vref, RX VrefLevel [Byte0]: 66
8001 19:23:18.231143 [Byte1]: 66
8002 19:23:18.231583
8003 19:23:18.234887 Set Vref, RX VrefLevel [Byte0]: 67
8004 19:23:18.237996 [Byte1]: 67
8005 19:23:18.241306
8006 19:23:18.241840 Set Vref, RX VrefLevel [Byte0]: 68
8007 19:23:18.244768 [Byte1]: 68
8008 19:23:18.248522
8009 19:23:18.248999 Set Vref, RX VrefLevel [Byte0]: 69
8010 19:23:18.251909 [Byte1]: 69
8011 19:23:18.256408
8012 19:23:18.256977 Set Vref, RX VrefLevel [Byte0]: 70
8013 19:23:18.259477 [Byte1]: 70
8014 19:23:18.264188
8015 19:23:18.264711 Set Vref, RX VrefLevel [Byte0]: 71
8016 19:23:18.267651 [Byte1]: 71
8017 19:23:18.271646
8018 19:23:18.272074 Set Vref, RX VrefLevel [Byte0]: 72
8019 19:23:18.274855 [Byte1]: 72
8020 19:23:18.279170
8021 19:23:18.279605 Set Vref, RX VrefLevel [Byte0]: 73
8022 19:23:18.282703 [Byte1]: 73
8023 19:23:18.287106
8024 19:23:18.287575 Set Vref, RX VrefLevel [Byte0]: 74
8025 19:23:18.290405 [Byte1]: 74
8026 19:23:18.294927
8027 19:23:18.295418 Set Vref, RX VrefLevel [Byte0]: 75
8028 19:23:18.298250 [Byte1]: 75
8029 19:23:18.302255
8030 19:23:18.302725 Set Vref, RX VrefLevel [Byte0]: 76
8031 19:23:18.305416 [Byte1]: 76
8032 19:23:18.309642
8033 19:23:18.310189 Set Vref, RX VrefLevel [Byte0]: 77
8034 19:23:18.313367 [Byte1]: 77
8035 19:23:18.317593
8036 19:23:18.318067 Set Vref, RX VrefLevel [Byte0]: 78
8037 19:23:18.324002 [Byte1]: 78
8038 19:23:18.324412
8039 19:23:18.327442 Set Vref, RX VrefLevel [Byte0]: 79
8040 19:23:18.330740 [Byte1]: 79
8041 19:23:18.331150
8042 19:23:18.333864 Final RX Vref Byte 0 = 66 to rank0
8043 19:23:18.337203 Final RX Vref Byte 1 = 59 to rank0
8044 19:23:18.340223 Final RX Vref Byte 0 = 66 to rank1
8045 19:23:18.344143 Final RX Vref Byte 1 = 59 to rank1==
8046 19:23:18.347082 Dram Type= 6, Freq= 0, CH_0, rank 0
8047 19:23:18.350449 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8048 19:23:18.350886 ==
8049 19:23:18.353705 DQS Delay:
8050 19:23:18.354135 DQS0 = 0, DQS1 = 0
8051 19:23:18.354460 DQM Delay:
8052 19:23:18.356989 DQM0 = 132, DQM1 = 123
8053 19:23:18.357476 DQ Delay:
8054 19:23:18.360283 DQ0 =130, DQ1 =136, DQ2 =130, DQ3 =132
8055 19:23:18.366932 DQ4 =132, DQ5 =122, DQ6 =140, DQ7 =140
8056 19:23:18.370053 DQ8 =116, DQ9 =112, DQ10 =124, DQ11 =118
8057 19:23:18.373096 DQ12 =130, DQ13 =128, DQ14 =134, DQ15 =128
8058 19:23:18.373555
8059 19:23:18.373944
8060 19:23:18.374296
8061 19:23:18.376457 [DramC_TX_OE_Calibration] TA2
8062 19:23:18.379690 Original DQ_B0 (3 6) =30, OEN = 27
8063 19:23:18.382919 Original DQ_B1 (3 6) =30, OEN = 27
8064 19:23:18.383348 24, 0x0, End_B0=24 End_B1=24
8065 19:23:18.386749 25, 0x0, End_B0=25 End_B1=25
8066 19:23:18.389637 26, 0x0, End_B0=26 End_B1=26
8067 19:23:18.393156 27, 0x0, End_B0=27 End_B1=27
8068 19:23:18.396258 28, 0x0, End_B0=28 End_B1=28
8069 19:23:18.396712 29, 0x0, End_B0=29 End_B1=29
8070 19:23:18.399528 30, 0x0, End_B0=30 End_B1=30
8071 19:23:18.402787 31, 0x4141, End_B0=30 End_B1=30
8072 19:23:18.406147 Byte0 end_step=30 best_step=27
8073 19:23:18.409397 Byte1 end_step=30 best_step=27
8074 19:23:18.412752 Byte0 TX OE(2T, 0.5T) = (3, 3)
8075 19:23:18.413209 Byte1 TX OE(2T, 0.5T) = (3, 3)
8076 19:23:18.413594
8077 19:23:18.415855
8078 19:23:18.422658 [DQSOSCAuto] RK0, (LSB)MR18= 0x2112, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 393 ps
8079 19:23:18.425912 CH0 RK0: MR19=303, MR18=2112
8080 19:23:18.432488 CH0_RK0: MR19=0x303, MR18=0x2112, DQSOSC=393, MR23=63, INC=23, DEC=15
8081 19:23:18.432977
8082 19:23:18.435561 ----->DramcWriteLeveling(PI) begin...
8083 19:23:18.436081 ==
8084 19:23:18.438742 Dram Type= 6, Freq= 0, CH_0, rank 1
8085 19:23:18.442140 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8086 19:23:18.442732 ==
8087 19:23:18.445405 Write leveling (Byte 0): 35 => 35
8088 19:23:18.448674 Write leveling (Byte 1): 29 => 29
8089 19:23:18.452145 DramcWriteLeveling(PI) end<-----
8090 19:23:18.452589
8091 19:23:18.452914 ==
8092 19:23:18.455272 Dram Type= 6, Freq= 0, CH_0, rank 1
8093 19:23:18.458552 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8094 19:23:18.458993 ==
8095 19:23:18.461897 [Gating] SW mode calibration
8096 19:23:18.468329 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8097 19:23:18.475219 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8098 19:23:18.478683 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8099 19:23:18.484914 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8100 19:23:18.488579 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8101 19:23:18.491314 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8102 19:23:18.497859 1 4 16 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
8103 19:23:18.501291 1 4 20 | B1->B0 | 3231 3434 | 1 1 | (0 0) (1 1)
8104 19:23:18.504883 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8105 19:23:18.511527 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8106 19:23:18.514942 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8107 19:23:18.518200 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8108 19:23:18.524401 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8109 19:23:18.527543 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8110 19:23:18.531124 1 5 16 | B1->B0 | 3434 2727 | 1 0 | (1 0) (0 0)
8111 19:23:18.537301 1 5 20 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
8112 19:23:18.540631 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8113 19:23:18.543889 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8114 19:23:18.550374 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8115 19:23:18.553733 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8116 19:23:18.556890 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8117 19:23:18.563740 1 6 12 | B1->B0 | 2323 3030 | 0 1 | (0 0) (0 0)
8118 19:23:18.567058 1 6 16 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
8119 19:23:18.570210 1 6 20 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
8120 19:23:18.576784 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8121 19:23:18.580102 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8122 19:23:18.583424 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8123 19:23:18.590051 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8124 19:23:18.593370 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8125 19:23:18.596532 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8126 19:23:18.603589 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8127 19:23:18.606436 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8128 19:23:18.609531 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8129 19:23:18.616075 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8130 19:23:18.619383 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8131 19:23:18.622603 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8132 19:23:18.629625 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8133 19:23:18.632811 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8134 19:23:18.636012 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8135 19:23:18.642430 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8136 19:23:18.645759 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8137 19:23:18.649084 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8138 19:23:18.655884 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8139 19:23:18.659016 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8140 19:23:18.662428 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8141 19:23:18.668815 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8142 19:23:18.672174 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8143 19:23:18.675437 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8144 19:23:18.678875 Total UI for P1: 0, mck2ui 16
8145 19:23:18.682106 best dqsien dly found for B0: ( 1, 9, 12)
8146 19:23:18.688705 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8147 19:23:18.689078 Total UI for P1: 0, mck2ui 16
8148 19:23:18.695515 best dqsien dly found for B1: ( 1, 9, 18)
8149 19:23:18.698738 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8150 19:23:18.701978 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8151 19:23:18.702445
8152 19:23:18.705647 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8153 19:23:18.708555 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8154 19:23:18.712479 [Gating] SW calibration Done
8155 19:23:18.712906 ==
8156 19:23:18.715560 Dram Type= 6, Freq= 0, CH_0, rank 1
8157 19:23:18.718879 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8158 19:23:18.719327 ==
8159 19:23:18.722134 RX Vref Scan: 0
8160 19:23:18.722548
8161 19:23:18.722910 RX Vref 0 -> 0, step: 1
8162 19:23:18.725314
8163 19:23:18.725748 RX Delay 0 -> 252, step: 8
8164 19:23:18.728946 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8165 19:23:18.735014 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8166 19:23:18.738560 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8167 19:23:18.741741 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8168 19:23:18.745392 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8169 19:23:18.751760 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8170 19:23:18.755132 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8171 19:23:18.758629 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8172 19:23:18.761898 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8173 19:23:18.765152 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8174 19:23:18.771629 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8175 19:23:18.774978 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8176 19:23:18.778211 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8177 19:23:18.781447 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8178 19:23:18.784765 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8179 19:23:18.791303 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8180 19:23:18.791800 ==
8181 19:23:18.794531 Dram Type= 6, Freq= 0, CH_0, rank 1
8182 19:23:18.797808 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8183 19:23:18.798218 ==
8184 19:23:18.798572 DQS Delay:
8185 19:23:18.801075 DQS0 = 0, DQS1 = 0
8186 19:23:18.801626 DQM Delay:
8187 19:23:18.804415 DQM0 = 133, DQM1 = 128
8188 19:23:18.804842 DQ Delay:
8189 19:23:18.807647 DQ0 =135, DQ1 =135, DQ2 =127, DQ3 =127
8190 19:23:18.811132 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8191 19:23:18.814545 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8192 19:23:18.817487 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
8193 19:23:18.821147
8194 19:23:18.821604
8195 19:23:18.821936 ==
8196 19:23:18.824261 Dram Type= 6, Freq= 0, CH_0, rank 1
8197 19:23:18.827435 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8198 19:23:18.827851 ==
8199 19:23:18.828178
8200 19:23:18.828480
8201 19:23:18.830828 TX Vref Scan disable
8202 19:23:18.831242 == TX Byte 0 ==
8203 19:23:18.837177 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8204 19:23:18.840683 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8205 19:23:18.841133 == TX Byte 1 ==
8206 19:23:18.847158 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8207 19:23:18.850771 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8208 19:23:18.851281 ==
8209 19:23:18.854052 Dram Type= 6, Freq= 0, CH_0, rank 1
8210 19:23:18.857323 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8211 19:23:18.857784 ==
8212 19:23:18.871505
8213 19:23:18.874926 TX Vref early break, caculate TX vref
8214 19:23:18.878075 TX Vref=16, minBit 1, minWin=22, winSum=374
8215 19:23:18.881288 TX Vref=18, minBit 0, minWin=23, winSum=388
8216 19:23:18.884726 TX Vref=20, minBit 0, minWin=23, winSum=397
8217 19:23:18.887756 TX Vref=22, minBit 1, minWin=23, winSum=405
8218 19:23:18.890985 TX Vref=24, minBit 0, minWin=25, winSum=414
8219 19:23:18.898270 TX Vref=26, minBit 0, minWin=25, winSum=417
8220 19:23:18.900896 TX Vref=28, minBit 0, minWin=24, winSum=411
8221 19:23:18.904270 TX Vref=30, minBit 1, minWin=24, winSum=406
8222 19:23:18.907561 TX Vref=32, minBit 0, minWin=24, winSum=401
8223 19:23:18.911320 TX Vref=34, minBit 2, minWin=23, winSum=390
8224 19:23:18.917952 [TxChooseVref] Worse bit 0, Min win 25, Win sum 417, Final Vref 26
8225 19:23:18.918370
8226 19:23:18.921265 Final TX Range 0 Vref 26
8227 19:23:18.921722
8228 19:23:18.922075 ==
8229 19:23:18.924420 Dram Type= 6, Freq= 0, CH_0, rank 1
8230 19:23:18.927465 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8231 19:23:18.927912 ==
8232 19:23:18.928239
8233 19:23:18.928581
8234 19:23:18.930804 TX Vref Scan disable
8235 19:23:18.937600 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8236 19:23:18.938030 == TX Byte 0 ==
8237 19:23:18.940984 u2DelayCellOfst[0]=11 cells (3 PI)
8238 19:23:18.944047 u2DelayCellOfst[1]=14 cells (4 PI)
8239 19:23:18.947489 u2DelayCellOfst[2]=11 cells (3 PI)
8240 19:23:18.950559 u2DelayCellOfst[3]=11 cells (3 PI)
8241 19:23:18.953877 u2DelayCellOfst[4]=7 cells (2 PI)
8242 19:23:18.957173 u2DelayCellOfst[5]=0 cells (0 PI)
8243 19:23:18.960358 u2DelayCellOfst[6]=14 cells (4 PI)
8244 19:23:18.964147 u2DelayCellOfst[7]=18 cells (5 PI)
8245 19:23:18.967065 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8246 19:23:18.970513 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8247 19:23:18.973846 == TX Byte 1 ==
8248 19:23:18.976736 u2DelayCellOfst[8]=0 cells (0 PI)
8249 19:23:18.980565 u2DelayCellOfst[9]=3 cells (1 PI)
8250 19:23:18.983848 u2DelayCellOfst[10]=7 cells (2 PI)
8251 19:23:18.984285 u2DelayCellOfst[11]=3 cells (1 PI)
8252 19:23:18.987127 u2DelayCellOfst[12]=14 cells (4 PI)
8253 19:23:18.990444 u2DelayCellOfst[13]=14 cells (4 PI)
8254 19:23:18.993665 u2DelayCellOfst[14]=18 cells (5 PI)
8255 19:23:18.996665 u2DelayCellOfst[15]=11 cells (3 PI)
8256 19:23:19.003776 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8257 19:23:19.006333 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8258 19:23:19.006748 DramC Write-DBI on
8259 19:23:19.009583 ==
8260 19:23:19.012887 Dram Type= 6, Freq= 0, CH_0, rank 1
8261 19:23:19.016187 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8262 19:23:19.016607 ==
8263 19:23:19.016925
8264 19:23:19.017238
8265 19:23:19.019645 TX Vref Scan disable
8266 19:23:19.020099 == TX Byte 0 ==
8267 19:23:19.026092 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8268 19:23:19.026522 == TX Byte 1 ==
8269 19:23:19.029299 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8270 19:23:19.032674 DramC Write-DBI off
8271 19:23:19.033070
8272 19:23:19.033540 [DATLAT]
8273 19:23:19.036243 Freq=1600, CH0 RK1
8274 19:23:19.036656
8275 19:23:19.037019 DATLAT Default: 0xf
8276 19:23:19.039473 0, 0xFFFF, sum = 0
8277 19:23:19.039918 1, 0xFFFF, sum = 0
8278 19:23:19.043082 2, 0xFFFF, sum = 0
8279 19:23:19.043511 3, 0xFFFF, sum = 0
8280 19:23:19.046111 4, 0xFFFF, sum = 0
8281 19:23:19.049138 5, 0xFFFF, sum = 0
8282 19:23:19.049679 6, 0xFFFF, sum = 0
8283 19:23:19.052435 7, 0xFFFF, sum = 0
8284 19:23:19.052855 8, 0xFFFF, sum = 0
8285 19:23:19.055680 9, 0xFFFF, sum = 0
8286 19:23:19.056122 10, 0xFFFF, sum = 0
8287 19:23:19.058881 11, 0xFFFF, sum = 0
8288 19:23:19.059297 12, 0xFFFF, sum = 0
8289 19:23:19.062115 13, 0xFFFF, sum = 0
8290 19:23:19.062590 14, 0x0, sum = 1
8291 19:23:19.065463 15, 0x0, sum = 2
8292 19:23:19.065902 16, 0x0, sum = 3
8293 19:23:19.068811 17, 0x0, sum = 4
8294 19:23:19.069227 best_step = 15
8295 19:23:19.069633
8296 19:23:19.069943 ==
8297 19:23:19.072006 Dram Type= 6, Freq= 0, CH_0, rank 1
8298 19:23:19.078421 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8299 19:23:19.078852 ==
8300 19:23:19.079277 RX Vref Scan: 0
8301 19:23:19.079605
8302 19:23:19.081995 RX Vref 0 -> 0, step: 1
8303 19:23:19.082470
8304 19:23:19.085293 RX Delay 11 -> 252, step: 4
8305 19:23:19.088131 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8306 19:23:19.091875 iDelay=195, Bit 1, Center 132 (79 ~ 186) 108
8307 19:23:19.095350 iDelay=195, Bit 2, Center 124 (71 ~ 178) 108
8308 19:23:19.101531 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8309 19:23:19.105111 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8310 19:23:19.107910 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8311 19:23:19.111573 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8312 19:23:19.114837 iDelay=195, Bit 7, Center 140 (87 ~ 194) 108
8313 19:23:19.121594 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8314 19:23:19.124205 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8315 19:23:19.127701 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8316 19:23:19.131047 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8317 19:23:19.137660 iDelay=195, Bit 12, Center 130 (75 ~ 186) 112
8318 19:23:19.140944 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8319 19:23:19.144283 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8320 19:23:19.147626 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8321 19:23:19.147708 ==
8322 19:23:19.150705 Dram Type= 6, Freq= 0, CH_0, rank 1
8323 19:23:19.157224 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8324 19:23:19.157342 ==
8325 19:23:19.157425 DQS Delay:
8326 19:23:19.160254 DQS0 = 0, DQS1 = 0
8327 19:23:19.160336 DQM Delay:
8328 19:23:19.164132 DQM0 = 130, DQM1 = 125
8329 19:23:19.164213 DQ Delay:
8330 19:23:19.167402 DQ0 =128, DQ1 =132, DQ2 =124, DQ3 =128
8331 19:23:19.170829 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =140
8332 19:23:19.174024 DQ8 =114, DQ9 =112, DQ10 =126, DQ11 =120
8333 19:23:19.176830 DQ12 =130, DQ13 =132, DQ14 =136, DQ15 =132
8334 19:23:19.176911
8335 19:23:19.176974
8336 19:23:19.177033
8337 19:23:19.180186 [DramC_TX_OE_Calibration] TA2
8338 19:23:19.183572 Original DQ_B0 (3 6) =30, OEN = 27
8339 19:23:19.186902 Original DQ_B1 (3 6) =30, OEN = 27
8340 19:23:19.189942 24, 0x0, End_B0=24 End_B1=24
8341 19:23:19.193697 25, 0x0, End_B0=25 End_B1=25
8342 19:23:19.193796 26, 0x0, End_B0=26 End_B1=26
8343 19:23:19.196624 27, 0x0, End_B0=27 End_B1=27
8344 19:23:19.200107 28, 0x0, End_B0=28 End_B1=28
8345 19:23:19.203037 29, 0x0, End_B0=29 End_B1=29
8346 19:23:19.203113 30, 0x0, End_B0=30 End_B1=30
8347 19:23:19.206897 31, 0x4141, End_B0=30 End_B1=30
8348 19:23:19.209773 Byte0 end_step=30 best_step=27
8349 19:23:19.212959 Byte1 end_step=30 best_step=27
8350 19:23:19.216269 Byte0 TX OE(2T, 0.5T) = (3, 3)
8351 19:23:19.220046 Byte1 TX OE(2T, 0.5T) = (3, 3)
8352 19:23:19.220127
8353 19:23:19.220190
8354 19:23:19.226644 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d01, (MSB)MR19= 0x303, tDQSOscB0 = 409 ps tDQSOscB1 = 395 ps
8355 19:23:19.230023 CH0 RK1: MR19=303, MR18=1D01
8356 19:23:19.236822 CH0_RK1: MR19=0x303, MR18=0x1D01, DQSOSC=395, MR23=63, INC=23, DEC=15
8357 19:23:19.239445 [RxdqsGatingPostProcess] freq 1600
8358 19:23:19.246581 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8359 19:23:19.246666 best DQS0 dly(2T, 0.5T) = (1, 1)
8360 19:23:19.249756 best DQS1 dly(2T, 0.5T) = (1, 1)
8361 19:23:19.252858 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8362 19:23:19.255995 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8363 19:23:19.259217 best DQS0 dly(2T, 0.5T) = (1, 1)
8364 19:23:19.263241 best DQS1 dly(2T, 0.5T) = (1, 1)
8365 19:23:19.265794 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8366 19:23:19.269285 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8367 19:23:19.272563 Pre-setting of DQS Precalculation
8368 19:23:19.275806 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8369 19:23:19.279184 ==
8370 19:23:19.279257 Dram Type= 6, Freq= 0, CH_1, rank 0
8371 19:23:19.285837 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8372 19:23:19.285914 ==
8373 19:23:19.289113 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8374 19:23:19.295756 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8375 19:23:19.298951 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8376 19:23:19.305262 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8377 19:23:19.313835 [CA 0] Center 41 (12~71) winsize 60
8378 19:23:19.316710 [CA 1] Center 41 (12~71) winsize 60
8379 19:23:19.320210 [CA 2] Center 37 (8~66) winsize 59
8380 19:23:19.323453 [CA 3] Center 35 (6~65) winsize 60
8381 19:23:19.326670 [CA 4] Center 36 (7~66) winsize 60
8382 19:23:19.329867 [CA 5] Center 36 (7~66) winsize 60
8383 19:23:19.329968
8384 19:23:19.333258 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8385 19:23:19.333378
8386 19:23:19.336480 [CATrainingPosCal] consider 1 rank data
8387 19:23:19.339939 u2DelayCellTimex100 = 262/100 ps
8388 19:23:19.346976 CA0 delay=41 (12~71),Diff = 6 PI (22 cell)
8389 19:23:19.349696 CA1 delay=41 (12~71),Diff = 6 PI (22 cell)
8390 19:23:19.353546 CA2 delay=37 (8~66),Diff = 2 PI (7 cell)
8391 19:23:19.356747 CA3 delay=35 (6~65),Diff = 0 PI (0 cell)
8392 19:23:19.360058 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
8393 19:23:19.363309 CA5 delay=36 (7~66),Diff = 1 PI (3 cell)
8394 19:23:19.363420
8395 19:23:19.366592 CA PerBit enable=1, Macro0, CA PI delay=35
8396 19:23:19.366669
8397 19:23:19.369845 [CBTSetCACLKResult] CA Dly = 35
8398 19:23:19.372940 CS Dly: 9 (0~40)
8399 19:23:19.376113 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8400 19:23:19.379635 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8401 19:23:19.379739 ==
8402 19:23:19.382833 Dram Type= 6, Freq= 0, CH_1, rank 1
8403 19:23:19.389480 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8404 19:23:19.389584 ==
8405 19:23:19.392850 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8406 19:23:19.399526 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8407 19:23:19.402874 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8408 19:23:19.409412 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8409 19:23:19.417168 [CA 0] Center 43 (14~72) winsize 59
8410 19:23:19.420703 [CA 1] Center 43 (13~73) winsize 61
8411 19:23:19.423709 [CA 2] Center 37 (8~67) winsize 60
8412 19:23:19.426724 [CA 3] Center 37 (7~67) winsize 61
8413 19:23:19.430217 [CA 4] Center 38 (9~67) winsize 59
8414 19:23:19.433858 [CA 5] Center 37 (8~67) winsize 60
8415 19:23:19.433955
8416 19:23:19.436808 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8417 19:23:19.436909
8418 19:23:19.439964 [CATrainingPosCal] consider 2 rank data
8419 19:23:19.443213 u2DelayCellTimex100 = 262/100 ps
8420 19:23:19.449627 CA0 delay=42 (14~71),Diff = 6 PI (22 cell)
8421 19:23:19.453111 CA1 delay=42 (13~71),Diff = 6 PI (22 cell)
8422 19:23:19.456372 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8423 19:23:19.460202 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8424 19:23:19.463464 CA4 delay=37 (9~66),Diff = 1 PI (3 cell)
8425 19:23:19.466795 CA5 delay=37 (8~66),Diff = 1 PI (3 cell)
8426 19:23:19.467032
8427 19:23:19.470168 CA PerBit enable=1, Macro0, CA PI delay=36
8428 19:23:19.470385
8429 19:23:19.473429 [CBTSetCACLKResult] CA Dly = 36
8430 19:23:19.476690 CS Dly: 11 (0~44)
8431 19:23:19.480331 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8432 19:23:19.482907 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8433 19:23:19.483338
8434 19:23:19.486535 ----->DramcWriteLeveling(PI) begin...
8435 19:23:19.486986 ==
8436 19:23:19.489534 Dram Type= 6, Freq= 0, CH_1, rank 0
8437 19:23:19.495930 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8438 19:23:19.496529 ==
8439 19:23:19.499754 Write leveling (Byte 0): 25 => 25
8440 19:23:19.503052 Write leveling (Byte 1): 27 => 27
8441 19:23:19.506340 DramcWriteLeveling(PI) end<-----
8442 19:23:19.506881
8443 19:23:19.507347 ==
8444 19:23:19.509651 Dram Type= 6, Freq= 0, CH_1, rank 0
8445 19:23:19.512899 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8446 19:23:19.513314 ==
8447 19:23:19.516056 [Gating] SW mode calibration
8448 19:23:19.522694 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8449 19:23:19.526022 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8450 19:23:19.532588 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8451 19:23:19.535874 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8452 19:23:19.538797 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8453 19:23:19.545640 1 4 12 | B1->B0 | 2c2c 3232 | 0 0 | (0 0) (0 0)
8454 19:23:19.548567 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8455 19:23:19.552124 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8456 19:23:19.558603 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8457 19:23:19.561941 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8458 19:23:19.565001 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8459 19:23:19.571521 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8460 19:23:19.574771 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8461 19:23:19.578074 1 5 12 | B1->B0 | 2b2b 2424 | 0 0 | (1 0) (1 0)
8462 19:23:19.584773 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8463 19:23:19.588017 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8464 19:23:19.594634 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8465 19:23:19.598516 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8466 19:23:19.601527 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8467 19:23:19.607655 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8468 19:23:19.611156 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8469 19:23:19.614524 1 6 12 | B1->B0 | 4242 4646 | 1 0 | (0 0) (0 0)
8470 19:23:19.621090 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8471 19:23:19.624311 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8472 19:23:19.627808 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8473 19:23:19.634422 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8474 19:23:19.637646 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8475 19:23:19.640970 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8476 19:23:19.647391 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8477 19:23:19.650744 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8478 19:23:19.653745 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8479 19:23:19.660647 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8480 19:23:19.663795 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8481 19:23:19.667132 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8482 19:23:19.673761 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8483 19:23:19.677143 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8484 19:23:19.679866 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8485 19:23:19.686651 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8486 19:23:19.689827 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8487 19:23:19.693127 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8488 19:23:19.699685 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8489 19:23:19.702970 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8490 19:23:19.706758 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8491 19:23:19.713401 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8492 19:23:19.716558 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8493 19:23:19.719636 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8494 19:23:19.726148 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8495 19:23:19.726235 Total UI for P1: 0, mck2ui 16
8496 19:23:19.733043 best dqsien dly found for B0: ( 1, 9, 10)
8497 19:23:19.733130 Total UI for P1: 0, mck2ui 16
8498 19:23:19.739707 best dqsien dly found for B1: ( 1, 9, 10)
8499 19:23:19.742490 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8500 19:23:19.745750 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8501 19:23:19.745835
8502 19:23:19.749502 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8503 19:23:19.752822 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8504 19:23:19.755892 [Gating] SW calibration Done
8505 19:23:19.755974 ==
8506 19:23:19.759131 Dram Type= 6, Freq= 0, CH_1, rank 0
8507 19:23:19.762523 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8508 19:23:19.762606 ==
8509 19:23:19.765916 RX Vref Scan: 0
8510 19:23:19.765998
8511 19:23:19.766064 RX Vref 0 -> 0, step: 1
8512 19:23:19.768725
8513 19:23:19.768798 RX Delay 0 -> 252, step: 8
8514 19:23:19.775549 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8515 19:23:19.779017 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8516 19:23:19.782005 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8517 19:23:19.785092 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8518 19:23:19.788984 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8519 19:23:19.795659 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8520 19:23:19.799036 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8521 19:23:19.801729 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8522 19:23:19.804957 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8523 19:23:19.808289 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8524 19:23:19.815028 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8525 19:23:19.818278 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8526 19:23:19.821681 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8527 19:23:19.824999 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8528 19:23:19.831285 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8529 19:23:19.834918 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8530 19:23:19.835001 ==
8531 19:23:19.837917 Dram Type= 6, Freq= 0, CH_1, rank 0
8532 19:23:19.841211 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8533 19:23:19.841301 ==
8534 19:23:19.844436 DQS Delay:
8535 19:23:19.844521 DQS0 = 0, DQS1 = 0
8536 19:23:19.844587 DQM Delay:
8537 19:23:19.848141 DQM0 = 137, DQM1 = 128
8538 19:23:19.848226 DQ Delay:
8539 19:23:19.851338 DQ0 =143, DQ1 =131, DQ2 =127, DQ3 =131
8540 19:23:19.854655 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8541 19:23:19.857873 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
8542 19:23:19.864312 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =135
8543 19:23:19.864395
8544 19:23:19.864460
8545 19:23:19.864519 ==
8546 19:23:19.867689 Dram Type= 6, Freq= 0, CH_1, rank 0
8547 19:23:19.871011 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8548 19:23:19.871093 ==
8549 19:23:19.871159
8550 19:23:19.871218
8551 19:23:19.874302 TX Vref Scan disable
8552 19:23:19.874384 == TX Byte 0 ==
8553 19:23:19.880721 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8554 19:23:19.884179 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8555 19:23:19.884261 == TX Byte 1 ==
8556 19:23:19.890606 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8557 19:23:19.894160 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8558 19:23:19.894269 ==
8559 19:23:19.897251 Dram Type= 6, Freq= 0, CH_1, rank 0
8560 19:23:19.900706 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8561 19:23:19.900795 ==
8562 19:23:19.914713
8563 19:23:19.917946 TX Vref early break, caculate TX vref
8564 19:23:19.921404 TX Vref=16, minBit 0, minWin=23, winSum=383
8565 19:23:19.924595 TX Vref=18, minBit 0, minWin=23, winSum=388
8566 19:23:19.927984 TX Vref=20, minBit 10, minWin=23, winSum=402
8567 19:23:19.930751 TX Vref=22, minBit 0, minWin=24, winSum=409
8568 19:23:19.934149 TX Vref=24, minBit 0, minWin=25, winSum=416
8569 19:23:19.940794 TX Vref=26, minBit 5, minWin=25, winSum=426
8570 19:23:19.944211 TX Vref=28, minBit 0, minWin=26, winSum=425
8571 19:23:19.947603 TX Vref=30, minBit 0, minWin=25, winSum=419
8572 19:23:19.950725 TX Vref=32, minBit 5, minWin=23, winSum=407
8573 19:23:19.953977 TX Vref=34, minBit 0, minWin=23, winSum=395
8574 19:23:19.960436 [TxChooseVref] Worse bit 0, Min win 26, Win sum 425, Final Vref 28
8575 19:23:19.960520
8576 19:23:19.963877 Final TX Range 0 Vref 28
8577 19:23:19.963959
8578 19:23:19.964042 ==
8579 19:23:19.967158 Dram Type= 6, Freq= 0, CH_1, rank 0
8580 19:23:19.970750 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8581 19:23:19.970859 ==
8582 19:23:19.970954
8583 19:23:19.971044
8584 19:23:19.974274 TX Vref Scan disable
8585 19:23:19.980134 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8586 19:23:19.980213 == TX Byte 0 ==
8587 19:23:19.983538 u2DelayCellOfst[0]=18 cells (5 PI)
8588 19:23:19.986775 u2DelayCellOfst[1]=14 cells (4 PI)
8589 19:23:19.990108 u2DelayCellOfst[2]=0 cells (0 PI)
8590 19:23:19.993355 u2DelayCellOfst[3]=7 cells (2 PI)
8591 19:23:19.996549 u2DelayCellOfst[4]=11 cells (3 PI)
8592 19:23:20.000344 u2DelayCellOfst[5]=22 cells (6 PI)
8593 19:23:20.003328 u2DelayCellOfst[6]=22 cells (6 PI)
8594 19:23:20.006432 u2DelayCellOfst[7]=7 cells (2 PI)
8595 19:23:20.009824 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8596 19:23:20.013117 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8597 19:23:20.016364 == TX Byte 1 ==
8598 19:23:20.019626 u2DelayCellOfst[8]=0 cells (0 PI)
8599 19:23:20.023582 u2DelayCellOfst[9]=3 cells (1 PI)
8600 19:23:20.026214 u2DelayCellOfst[10]=11 cells (3 PI)
8601 19:23:20.029565 u2DelayCellOfst[11]=7 cells (2 PI)
8602 19:23:20.029649 u2DelayCellOfst[12]=14 cells (4 PI)
8603 19:23:20.032901 u2DelayCellOfst[13]=18 cells (5 PI)
8604 19:23:20.036341 u2DelayCellOfst[14]=18 cells (5 PI)
8605 19:23:20.039738 u2DelayCellOfst[15]=18 cells (5 PI)
8606 19:23:20.046329 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8607 19:23:20.049618 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8608 19:23:20.049701 DramC Write-DBI on
8609 19:23:20.052966 ==
8610 19:23:20.056360 Dram Type= 6, Freq= 0, CH_1, rank 0
8611 19:23:20.059594 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8612 19:23:20.059677 ==
8613 19:23:20.059742
8614 19:23:20.059802
8615 19:23:20.062756 TX Vref Scan disable
8616 19:23:20.062838 == TX Byte 0 ==
8617 19:23:20.069277 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8618 19:23:20.069396 == TX Byte 1 ==
8619 19:23:20.072888 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8620 19:23:20.075809 DramC Write-DBI off
8621 19:23:20.075889
8622 19:23:20.075952 [DATLAT]
8623 19:23:20.079185 Freq=1600, CH1 RK0
8624 19:23:20.079264
8625 19:23:20.079327 DATLAT Default: 0xf
8626 19:23:20.082499 0, 0xFFFF, sum = 0
8627 19:23:20.082580 1, 0xFFFF, sum = 0
8628 19:23:20.085704 2, 0xFFFF, sum = 0
8629 19:23:20.085785 3, 0xFFFF, sum = 0
8630 19:23:20.089230 4, 0xFFFF, sum = 0
8631 19:23:20.092467 5, 0xFFFF, sum = 0
8632 19:23:20.092548 6, 0xFFFF, sum = 0
8633 19:23:20.095859 7, 0xFFFF, sum = 0
8634 19:23:20.095941 8, 0xFFFF, sum = 0
8635 19:23:20.099131 9, 0xFFFF, sum = 0
8636 19:23:20.099212 10, 0xFFFF, sum = 0
8637 19:23:20.102261 11, 0xFFFF, sum = 0
8638 19:23:20.102341 12, 0xFFFF, sum = 0
8639 19:23:20.105650 13, 0xFFFF, sum = 0
8640 19:23:20.105731 14, 0x0, sum = 1
8641 19:23:20.108967 15, 0x0, sum = 2
8642 19:23:20.109086 16, 0x0, sum = 3
8643 19:23:20.112135 17, 0x0, sum = 4
8644 19:23:20.112218 best_step = 15
8645 19:23:20.112301
8646 19:23:20.112378 ==
8647 19:23:20.115172 Dram Type= 6, Freq= 0, CH_1, rank 0
8648 19:23:20.118946 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8649 19:23:20.121692 ==
8650 19:23:20.121774 RX Vref Scan: 1
8651 19:23:20.121857
8652 19:23:20.125649 Set Vref Range= 24 -> 127
8653 19:23:20.125731
8654 19:23:20.128293 RX Vref 24 -> 127, step: 1
8655 19:23:20.128375
8656 19:23:20.128458 RX Delay 11 -> 252, step: 4
8657 19:23:20.128536
8658 19:23:20.131593 Set Vref, RX VrefLevel [Byte0]: 24
8659 19:23:20.134982 [Byte1]: 24
8660 19:23:20.139008
8661 19:23:20.139090 Set Vref, RX VrefLevel [Byte0]: 25
8662 19:23:20.142297 [Byte1]: 25
8663 19:23:20.146875
8664 19:23:20.146957 Set Vref, RX VrefLevel [Byte0]: 26
8665 19:23:20.150289 [Byte1]: 26
8666 19:23:20.154307
8667 19:23:20.154390 Set Vref, RX VrefLevel [Byte0]: 27
8668 19:23:20.157701 [Byte1]: 27
8669 19:23:20.161858
8670 19:23:20.161940 Set Vref, RX VrefLevel [Byte0]: 28
8671 19:23:20.165086 [Byte1]: 28
8672 19:23:20.169687
8673 19:23:20.169766 Set Vref, RX VrefLevel [Byte0]: 29
8674 19:23:20.172936 [Byte1]: 29
8675 19:23:20.177321
8676 19:23:20.177442 Set Vref, RX VrefLevel [Byte0]: 30
8677 19:23:20.180359 [Byte1]: 30
8678 19:23:20.184936
8679 19:23:20.185016 Set Vref, RX VrefLevel [Byte0]: 31
8680 19:23:20.188063 [Byte1]: 31
8681 19:23:20.192252
8682 19:23:20.192332 Set Vref, RX VrefLevel [Byte0]: 32
8683 19:23:20.195838 [Byte1]: 32
8684 19:23:20.199826
8685 19:23:20.199905 Set Vref, RX VrefLevel [Byte0]: 33
8686 19:23:20.203101 [Byte1]: 33
8687 19:23:20.207843
8688 19:23:20.207923 Set Vref, RX VrefLevel [Byte0]: 34
8689 19:23:20.210879 [Byte1]: 34
8690 19:23:20.215309
8691 19:23:20.215389 Set Vref, RX VrefLevel [Byte0]: 35
8692 19:23:20.218476 [Byte1]: 35
8693 19:23:20.223004
8694 19:23:20.223084 Set Vref, RX VrefLevel [Byte0]: 36
8695 19:23:20.226033 [Byte1]: 36
8696 19:23:20.230626
8697 19:23:20.230707 Set Vref, RX VrefLevel [Byte0]: 37
8698 19:23:20.234041 [Byte1]: 37
8699 19:23:20.237997
8700 19:23:20.238103 Set Vref, RX VrefLevel [Byte0]: 38
8701 19:23:20.241455 [Byte1]: 38
8702 19:23:20.246056
8703 19:23:20.246137 Set Vref, RX VrefLevel [Byte0]: 39
8704 19:23:20.248781 [Byte1]: 39
8705 19:23:20.253659
8706 19:23:20.253739 Set Vref, RX VrefLevel [Byte0]: 40
8707 19:23:20.256803 [Byte1]: 40
8708 19:23:20.260777
8709 19:23:20.260858 Set Vref, RX VrefLevel [Byte0]: 41
8710 19:23:20.264177 [Byte1]: 41
8711 19:23:20.268317
8712 19:23:20.268397 Set Vref, RX VrefLevel [Byte0]: 42
8713 19:23:20.271600 [Byte1]: 42
8714 19:23:20.276238
8715 19:23:20.276335 Set Vref, RX VrefLevel [Byte0]: 43
8716 19:23:20.279570 [Byte1]: 43
8717 19:23:20.283992
8718 19:23:20.284071 Set Vref, RX VrefLevel [Byte0]: 44
8719 19:23:20.287145 [Byte1]: 44
8720 19:23:20.291538
8721 19:23:20.291618 Set Vref, RX VrefLevel [Byte0]: 45
8722 19:23:20.294926 [Byte1]: 45
8723 19:23:20.298900
8724 19:23:20.298983 Set Vref, RX VrefLevel [Byte0]: 46
8725 19:23:20.302166 [Byte1]: 46
8726 19:23:20.306800
8727 19:23:20.306880 Set Vref, RX VrefLevel [Byte0]: 47
8728 19:23:20.309827 [Byte1]: 47
8729 19:23:20.314026
8730 19:23:20.314106 Set Vref, RX VrefLevel [Byte0]: 48
8731 19:23:20.317761 [Byte1]: 48
8732 19:23:20.321690
8733 19:23:20.321796 Set Vref, RX VrefLevel [Byte0]: 49
8734 19:23:20.324911 [Byte1]: 49
8735 19:23:20.329645
8736 19:23:20.329725 Set Vref, RX VrefLevel [Byte0]: 50
8737 19:23:20.332889 [Byte1]: 50
8738 19:23:20.337068
8739 19:23:20.337187 Set Vref, RX VrefLevel [Byte0]: 51
8740 19:23:20.340201 [Byte1]: 51
8741 19:23:20.344814
8742 19:23:20.344895 Set Vref, RX VrefLevel [Byte0]: 52
8743 19:23:20.348147 [Byte1]: 52
8744 19:23:20.352126
8745 19:23:20.352206 Set Vref, RX VrefLevel [Byte0]: 53
8746 19:23:20.355483 [Byte1]: 53
8747 19:23:20.360087
8748 19:23:20.360167 Set Vref, RX VrefLevel [Byte0]: 54
8749 19:23:20.363014 [Byte1]: 54
8750 19:23:20.367601
8751 19:23:20.367694 Set Vref, RX VrefLevel [Byte0]: 55
8752 19:23:20.370918 [Byte1]: 55
8753 19:23:20.374898
8754 19:23:20.374979 Set Vref, RX VrefLevel [Byte0]: 56
8755 19:23:20.378243 [Byte1]: 56
8756 19:23:20.383002
8757 19:23:20.383083 Set Vref, RX VrefLevel [Byte0]: 57
8758 19:23:20.386155 [Byte1]: 57
8759 19:23:20.390252
8760 19:23:20.390332 Set Vref, RX VrefLevel [Byte0]: 58
8761 19:23:20.393590 [Byte1]: 58
8762 19:23:20.398024
8763 19:23:20.398103 Set Vref, RX VrefLevel [Byte0]: 59
8764 19:23:20.401052 [Byte1]: 59
8765 19:23:20.405299
8766 19:23:20.405461 Set Vref, RX VrefLevel [Byte0]: 60
8767 19:23:20.408612 [Byte1]: 60
8768 19:23:20.413224
8769 19:23:20.413305 Set Vref, RX VrefLevel [Byte0]: 61
8770 19:23:20.416338 [Byte1]: 61
8771 19:23:20.421065
8772 19:23:20.421145 Set Vref, RX VrefLevel [Byte0]: 62
8773 19:23:20.423774 [Byte1]: 62
8774 19:23:20.428493
8775 19:23:20.428573 Set Vref, RX VrefLevel [Byte0]: 63
8776 19:23:20.431622 [Byte1]: 63
8777 19:23:20.435774
8778 19:23:20.435854 Set Vref, RX VrefLevel [Byte0]: 64
8779 19:23:20.439283 [Byte1]: 64
8780 19:23:20.443875
8781 19:23:20.443955 Set Vref, RX VrefLevel [Byte0]: 65
8782 19:23:20.446618 [Byte1]: 65
8783 19:23:20.451302
8784 19:23:20.451382 Set Vref, RX VrefLevel [Byte0]: 66
8785 19:23:20.454818 [Byte1]: 66
8786 19:23:20.458744
8787 19:23:20.458829 Set Vref, RX VrefLevel [Byte0]: 67
8788 19:23:20.462479 [Byte1]: 67
8789 19:23:20.466421
8790 19:23:20.466501 Set Vref, RX VrefLevel [Byte0]: 68
8791 19:23:20.469628 [Byte1]: 68
8792 19:23:20.474275
8793 19:23:20.474355 Set Vref, RX VrefLevel [Byte0]: 69
8794 19:23:20.477573 [Byte1]: 69
8795 19:23:20.481703
8796 19:23:20.481795 Set Vref, RX VrefLevel [Byte0]: 70
8797 19:23:20.485270 [Byte1]: 70
8798 19:23:20.489046
8799 19:23:20.489146 Set Vref, RX VrefLevel [Byte0]: 71
8800 19:23:20.492350 [Byte1]: 71
8801 19:23:20.496994
8802 19:23:20.497114 Set Vref, RX VrefLevel [Byte0]: 72
8803 19:23:20.500315 [Byte1]: 72
8804 19:23:20.504731
8805 19:23:20.504863 Final RX Vref Byte 0 = 55 to rank0
8806 19:23:20.507930 Final RX Vref Byte 1 = 61 to rank0
8807 19:23:20.510902 Final RX Vref Byte 0 = 55 to rank1
8808 19:23:20.514372 Final RX Vref Byte 1 = 61 to rank1==
8809 19:23:20.517972 Dram Type= 6, Freq= 0, CH_1, rank 0
8810 19:23:20.524372 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8811 19:23:20.524612 ==
8812 19:23:20.524801 DQS Delay:
8813 19:23:20.527704 DQS0 = 0, DQS1 = 0
8814 19:23:20.528097 DQM Delay:
8815 19:23:20.528362 DQM0 = 133, DQM1 = 128
8816 19:23:20.531013 DQ Delay:
8817 19:23:20.534448 DQ0 =142, DQ1 =128, DQ2 =122, DQ3 =130
8818 19:23:20.537620 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =128
8819 19:23:20.540985 DQ8 =114, DQ9 =116, DQ10 =130, DQ11 =118
8820 19:23:20.544112 DQ12 =136, DQ13 =136, DQ14 =136, DQ15 =138
8821 19:23:20.544409
8822 19:23:20.544641
8823 19:23:20.544857
8824 19:23:20.547766 [DramC_TX_OE_Calibration] TA2
8825 19:23:20.550807 Original DQ_B0 (3 6) =30, OEN = 27
8826 19:23:20.554194 Original DQ_B1 (3 6) =30, OEN = 27
8827 19:23:20.557442 24, 0x0, End_B0=24 End_B1=24
8828 19:23:20.557744 25, 0x0, End_B0=25 End_B1=25
8829 19:23:20.560886 26, 0x0, End_B0=26 End_B1=26
8830 19:23:20.563962 27, 0x0, End_B0=27 End_B1=27
8831 19:23:20.567454 28, 0x0, End_B0=28 End_B1=28
8832 19:23:20.570922 29, 0x0, End_B0=29 End_B1=29
8833 19:23:20.571224 30, 0x0, End_B0=30 End_B1=30
8834 19:23:20.574371 31, 0x4141, End_B0=30 End_B1=30
8835 19:23:20.577764 Byte0 end_step=30 best_step=27
8836 19:23:20.580924 Byte1 end_step=30 best_step=27
8837 19:23:20.583637 Byte0 TX OE(2T, 0.5T) = (3, 3)
8838 19:23:20.587044 Byte1 TX OE(2T, 0.5T) = (3, 3)
8839 19:23:20.587384
8840 19:23:20.587736
8841 19:23:20.593654 [DQSOSCAuto] RK0, (LSB)MR18= 0x170d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 398 ps
8842 19:23:20.596823 CH1 RK0: MR19=303, MR18=170D
8843 19:23:20.603565 CH1_RK0: MR19=0x303, MR18=0x170D, DQSOSC=398, MR23=63, INC=23, DEC=15
8844 19:23:20.603871
8845 19:23:20.606921 ----->DramcWriteLeveling(PI) begin...
8846 19:23:20.607218 ==
8847 19:23:20.610192 Dram Type= 6, Freq= 0, CH_1, rank 1
8848 19:23:20.613441 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8849 19:23:20.613753 ==
8850 19:23:20.616918 Write leveling (Byte 0): 23 => 23
8851 19:23:20.620119 Write leveling (Byte 1): 27 => 27
8852 19:23:20.623237 DramcWriteLeveling(PI) end<-----
8853 19:23:20.623531
8854 19:23:20.623837 ==
8855 19:23:20.626624 Dram Type= 6, Freq= 0, CH_1, rank 1
8856 19:23:20.630207 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8857 19:23:20.633175 ==
8858 19:23:20.633502 [Gating] SW mode calibration
8859 19:23:20.643518 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8860 19:23:20.646836 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8861 19:23:20.649535 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8862 19:23:20.656348 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8863 19:23:20.659813 1 4 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8864 19:23:20.662859 1 4 12 | B1->B0 | 3232 2323 | 1 1 | (1 1) (1 1)
8865 19:23:20.669619 1 4 16 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8866 19:23:20.672812 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8867 19:23:20.676151 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8868 19:23:20.683050 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8869 19:23:20.686156 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8870 19:23:20.689665 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8871 19:23:20.696070 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8872 19:23:20.699263 1 5 12 | B1->B0 | 2626 3434 | 0 1 | (1 0) (1 0)
8873 19:23:20.702866 1 5 16 | B1->B0 | 2323 2828 | 0 0 | (0 0) (1 0)
8874 19:23:20.709229 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8875 19:23:20.712457 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8876 19:23:20.715778 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8877 19:23:20.722087 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8878 19:23:20.725658 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8879 19:23:20.728822 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8880 19:23:20.735774 1 6 12 | B1->B0 | 4545 2524 | 0 1 | (0 0) (0 0)
8881 19:23:20.738765 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8882 19:23:20.741800 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8883 19:23:20.748810 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8884 19:23:20.751650 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8885 19:23:20.754938 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8886 19:23:20.761680 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8887 19:23:20.764757 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8888 19:23:20.768108 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8889 19:23:20.774905 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8890 19:23:20.778183 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8891 19:23:20.781449 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8892 19:23:20.788367 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8893 19:23:20.791220 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8894 19:23:20.794988 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8895 19:23:20.801293 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8896 19:23:20.804559 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8897 19:23:20.807933 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8898 19:23:20.814477 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8899 19:23:20.817522 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8900 19:23:20.820875 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8901 19:23:20.827578 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8902 19:23:20.830834 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8903 19:23:20.834171 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8904 19:23:20.840734 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8905 19:23:20.843886 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8906 19:23:20.847161 Total UI for P1: 0, mck2ui 16
8907 19:23:20.851167 best dqsien dly found for B0: ( 1, 9, 12)
8908 19:23:20.854476 Total UI for P1: 0, mck2ui 16
8909 19:23:20.857369 best dqsien dly found for B1: ( 1, 9, 10)
8910 19:23:20.860244 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8911 19:23:20.863787 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8912 19:23:20.863985
8913 19:23:20.867451 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8914 19:23:20.874134 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8915 19:23:20.874443 [Gating] SW calibration Done
8916 19:23:20.874746 ==
8917 19:23:20.877605 Dram Type= 6, Freq= 0, CH_1, rank 1
8918 19:23:20.883855 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8919 19:23:20.884659 ==
8920 19:23:20.885127 RX Vref Scan: 0
8921 19:23:20.885529
8922 19:23:20.887128 RX Vref 0 -> 0, step: 1
8923 19:23:20.887573
8924 19:23:20.890374 RX Delay 0 -> 252, step: 8
8925 19:23:20.893682 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8926 19:23:20.896985 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8927 19:23:20.900281 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8928 19:23:20.907124 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8929 19:23:20.910568 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8930 19:23:20.913364 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8931 19:23:20.917215 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8932 19:23:20.920353 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8933 19:23:20.926625 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8934 19:23:20.929971 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8935 19:23:20.933246 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8936 19:23:20.936693 iDelay=208, Bit 11, Center 123 (64 ~ 183) 120
8937 19:23:20.939911 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8938 19:23:20.946459 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8939 19:23:20.949698 iDelay=208, Bit 14, Center 135 (72 ~ 199) 128
8940 19:23:20.953401 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8941 19:23:20.953823 ==
8942 19:23:20.956584 Dram Type= 6, Freq= 0, CH_1, rank 1
8943 19:23:20.959945 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8944 19:23:20.963386 ==
8945 19:23:20.964119 DQS Delay:
8946 19:23:20.964742 DQS0 = 0, DQS1 = 0
8947 19:23:20.966697 DQM Delay:
8948 19:23:20.967151 DQM0 = 136, DQM1 = 129
8949 19:23:20.969869 DQ Delay:
8950 19:23:20.972939 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8951 19:23:20.976397 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8952 19:23:20.979343 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8953 19:23:20.983257 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8954 19:23:20.983801
8955 19:23:20.984179
8956 19:23:20.984723 ==
8957 19:23:20.986096 Dram Type= 6, Freq= 0, CH_1, rank 1
8958 19:23:20.989820 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8959 19:23:20.992629 ==
8960 19:23:20.993154
8961 19:23:20.993653
8962 19:23:20.994025 TX Vref Scan disable
8963 19:23:20.996207 == TX Byte 0 ==
8964 19:23:20.999416 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8965 19:23:21.002425 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8966 19:23:21.006304 == TX Byte 1 ==
8967 19:23:21.008892 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8968 19:23:21.012919 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8969 19:23:21.016154 ==
8970 19:23:21.016616 Dram Type= 6, Freq= 0, CH_1, rank 1
8971 19:23:21.022102 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8972 19:23:21.022560 ==
8973 19:23:21.034586
8974 19:23:21.038133 TX Vref early break, caculate TX vref
8975 19:23:21.041133 TX Vref=16, minBit 0, minWin=22, winSum=379
8976 19:23:21.044553 TX Vref=18, minBit 1, minWin=22, winSum=390
8977 19:23:21.047801 TX Vref=20, minBit 1, minWin=23, winSum=397
8978 19:23:21.050970 TX Vref=22, minBit 0, minWin=23, winSum=405
8979 19:23:21.053780 TX Vref=24, minBit 5, minWin=24, winSum=410
8980 19:23:21.060394 TX Vref=26, minBit 5, minWin=24, winSum=420
8981 19:23:21.063796 TX Vref=28, minBit 0, minWin=24, winSum=419
8982 19:23:21.067144 TX Vref=30, minBit 0, minWin=24, winSum=410
8983 19:23:21.070497 TX Vref=32, minBit 1, minWin=23, winSum=405
8984 19:23:21.073862 TX Vref=34, minBit 0, minWin=23, winSum=395
8985 19:23:21.080484 [TxChooseVref] Worse bit 5, Min win 24, Win sum 420, Final Vref 26
8986 19:23:21.080601
8987 19:23:21.083124 Final TX Range 0 Vref 26
8988 19:23:21.083238
8989 19:23:21.083327 ==
8990 19:23:21.086889 Dram Type= 6, Freq= 0, CH_1, rank 1
8991 19:23:21.090163 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8992 19:23:21.090246 ==
8993 19:23:21.090311
8994 19:23:21.093252
8995 19:23:21.093342 TX Vref Scan disable
8996 19:23:21.099965 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8997 19:23:21.100063 == TX Byte 0 ==
8998 19:23:21.102967 u2DelayCellOfst[0]=18 cells (5 PI)
8999 19:23:21.106214 u2DelayCellOfst[1]=11 cells (3 PI)
9000 19:23:21.109905 u2DelayCellOfst[2]=0 cells (0 PI)
9001 19:23:21.113100 u2DelayCellOfst[3]=3 cells (1 PI)
9002 19:23:21.116426 u2DelayCellOfst[4]=7 cells (2 PI)
9003 19:23:21.119837 u2DelayCellOfst[5]=22 cells (6 PI)
9004 19:23:21.122713 u2DelayCellOfst[6]=18 cells (5 PI)
9005 19:23:21.125917 u2DelayCellOfst[7]=3 cells (1 PI)
9006 19:23:21.129642 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
9007 19:23:21.132591 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
9008 19:23:21.136023 == TX Byte 1 ==
9009 19:23:21.139191 u2DelayCellOfst[8]=0 cells (0 PI)
9010 19:23:21.142705 u2DelayCellOfst[9]=7 cells (2 PI)
9011 19:23:21.145885 u2DelayCellOfst[10]=11 cells (3 PI)
9012 19:23:21.149150 u2DelayCellOfst[11]=7 cells (2 PI)
9013 19:23:21.152696 u2DelayCellOfst[12]=18 cells (5 PI)
9014 19:23:21.152779 u2DelayCellOfst[13]=18 cells (5 PI)
9015 19:23:21.155458 u2DelayCellOfst[14]=18 cells (5 PI)
9016 19:23:21.158745 u2DelayCellOfst[15]=18 cells (5 PI)
9017 19:23:21.165470 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
9018 19:23:21.168715 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
9019 19:23:21.168798 DramC Write-DBI on
9020 19:23:21.172167 ==
9021 19:23:21.175651 Dram Type= 6, Freq= 0, CH_1, rank 1
9022 19:23:21.178922 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9023 19:23:21.179004 ==
9024 19:23:21.179069
9025 19:23:21.179129
9026 19:23:21.182286 TX Vref Scan disable
9027 19:23:21.182388 == TX Byte 0 ==
9028 19:23:21.189028 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
9029 19:23:21.189154 == TX Byte 1 ==
9030 19:23:21.192206 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
9031 19:23:21.195666 DramC Write-DBI off
9032 19:23:21.195746
9033 19:23:21.195809 [DATLAT]
9034 19:23:21.199054 Freq=1600, CH1 RK1
9035 19:23:21.199134
9036 19:23:21.199197 DATLAT Default: 0xf
9037 19:23:21.202137 0, 0xFFFF, sum = 0
9038 19:23:21.202219 1, 0xFFFF, sum = 0
9039 19:23:21.205196 2, 0xFFFF, sum = 0
9040 19:23:21.208729 3, 0xFFFF, sum = 0
9041 19:23:21.208810 4, 0xFFFF, sum = 0
9042 19:23:21.211644 5, 0xFFFF, sum = 0
9043 19:23:21.211725 6, 0xFFFF, sum = 0
9044 19:23:21.215287 7, 0xFFFF, sum = 0
9045 19:23:21.215369 8, 0xFFFF, sum = 0
9046 19:23:21.218634 9, 0xFFFF, sum = 0
9047 19:23:21.218716 10, 0xFFFF, sum = 0
9048 19:23:21.221676 11, 0xFFFF, sum = 0
9049 19:23:21.221758 12, 0xFFFF, sum = 0
9050 19:23:21.224809 13, 0xFFFF, sum = 0
9051 19:23:21.224892 14, 0x0, sum = 1
9052 19:23:21.228383 15, 0x0, sum = 2
9053 19:23:21.228464 16, 0x0, sum = 3
9054 19:23:21.231305 17, 0x0, sum = 4
9055 19:23:21.231388 best_step = 15
9056 19:23:21.231448
9057 19:23:21.231506 ==
9058 19:23:21.235039 Dram Type= 6, Freq= 0, CH_1, rank 1
9059 19:23:21.241460 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9060 19:23:21.241536 ==
9061 19:23:21.241605 RX Vref Scan: 0
9062 19:23:21.241664
9063 19:23:21.244409 RX Vref 0 -> 0, step: 1
9064 19:23:21.244479
9065 19:23:21.247905 RX Delay 11 -> 252, step: 4
9066 19:23:21.251361 iDelay=199, Bit 0, Center 138 (83 ~ 194) 112
9067 19:23:21.254209 iDelay=199, Bit 1, Center 128 (75 ~ 182) 108
9068 19:23:21.260591 iDelay=199, Bit 2, Center 122 (67 ~ 178) 112
9069 19:23:21.263976 iDelay=199, Bit 3, Center 130 (79 ~ 182) 104
9070 19:23:21.267865 iDelay=199, Bit 4, Center 134 (79 ~ 190) 112
9071 19:23:21.270552 iDelay=199, Bit 5, Center 144 (91 ~ 198) 108
9072 19:23:21.273955 iDelay=199, Bit 6, Center 144 (91 ~ 198) 108
9073 19:23:21.280694 iDelay=199, Bit 7, Center 130 (79 ~ 182) 104
9074 19:23:21.284044 iDelay=199, Bit 8, Center 112 (55 ~ 170) 116
9075 19:23:21.287427 iDelay=199, Bit 9, Center 114 (59 ~ 170) 112
9076 19:23:21.290829 iDelay=199, Bit 10, Center 128 (75 ~ 182) 108
9077 19:23:21.294044 iDelay=199, Bit 11, Center 118 (67 ~ 170) 104
9078 19:23:21.300284 iDelay=199, Bit 12, Center 136 (83 ~ 190) 108
9079 19:23:21.303557 iDelay=199, Bit 13, Center 136 (83 ~ 190) 108
9080 19:23:21.307590 iDelay=199, Bit 14, Center 134 (79 ~ 190) 112
9081 19:23:21.310876 iDelay=199, Bit 15, Center 138 (83 ~ 194) 112
9082 19:23:21.310972 ==
9083 19:23:21.313516 Dram Type= 6, Freq= 0, CH_1, rank 1
9084 19:23:21.320358 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9085 19:23:21.320440 ==
9086 19:23:21.320505 DQS Delay:
9087 19:23:21.323624 DQS0 = 0, DQS1 = 0
9088 19:23:21.323708 DQM Delay:
9089 19:23:21.323772 DQM0 = 133, DQM1 = 127
9090 19:23:21.326997 DQ Delay:
9091 19:23:21.330026 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130
9092 19:23:21.333266 DQ4 =134, DQ5 =144, DQ6 =144, DQ7 =130
9093 19:23:21.337092 DQ8 =112, DQ9 =114, DQ10 =128, DQ11 =118
9094 19:23:21.340406 DQ12 =136, DQ13 =136, DQ14 =134, DQ15 =138
9095 19:23:21.340480
9096 19:23:21.340541
9097 19:23:21.340598
9098 19:23:21.343628 [DramC_TX_OE_Calibration] TA2
9099 19:23:21.346690 Original DQ_B0 (3 6) =30, OEN = 27
9100 19:23:21.349717 Original DQ_B1 (3 6) =30, OEN = 27
9101 19:23:21.353025 24, 0x0, End_B0=24 End_B1=24
9102 19:23:21.356823 25, 0x0, End_B0=25 End_B1=25
9103 19:23:21.356907 26, 0x0, End_B0=26 End_B1=26
9104 19:23:21.359950 27, 0x0, End_B0=27 End_B1=27
9105 19:23:21.362940 28, 0x0, End_B0=28 End_B1=28
9106 19:23:21.366601 29, 0x0, End_B0=29 End_B1=29
9107 19:23:21.366681 30, 0x0, End_B0=30 End_B1=30
9108 19:23:21.369878 31, 0x4141, End_B0=30 End_B1=30
9109 19:23:21.372777 Byte0 end_step=30 best_step=27
9110 19:23:21.376075 Byte1 end_step=30 best_step=27
9111 19:23:21.379468 Byte0 TX OE(2T, 0.5T) = (3, 3)
9112 19:23:21.382751 Byte1 TX OE(2T, 0.5T) = (3, 3)
9113 19:23:21.382829
9114 19:23:21.382891
9115 19:23:21.389279 [DQSOSCAuto] RK1, (LSB)MR18= 0x806, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 405 ps
9116 19:23:21.392792 CH1 RK1: MR19=303, MR18=806
9117 19:23:21.399290 CH1_RK1: MR19=0x303, MR18=0x806, DQSOSC=405, MR23=63, INC=22, DEC=15
9118 19:23:21.402709 [RxdqsGatingPostProcess] freq 1600
9119 19:23:21.409247 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9120 19:23:21.409339 best DQS0 dly(2T, 0.5T) = (1, 1)
9121 19:23:21.412640 best DQS1 dly(2T, 0.5T) = (1, 1)
9122 19:23:21.416061 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9123 19:23:21.419293 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9124 19:23:21.422732 best DQS0 dly(2T, 0.5T) = (1, 1)
9125 19:23:21.426045 best DQS1 dly(2T, 0.5T) = (1, 1)
9126 19:23:21.429237 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9127 19:23:21.432524 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9128 19:23:21.435713 Pre-setting of DQS Precalculation
9129 19:23:21.439235 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9130 19:23:21.449017 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9131 19:23:21.455261 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9132 19:23:21.455347
9133 19:23:21.455409
9134 19:23:21.458706 [Calibration Summary] 3200 Mbps
9135 19:23:21.458775 CH 0, Rank 0
9136 19:23:21.461751 SW Impedance : PASS
9137 19:23:21.461828 DUTY Scan : NO K
9138 19:23:21.464991 ZQ Calibration : PASS
9139 19:23:21.468265 Jitter Meter : NO K
9140 19:23:21.468338 CBT Training : PASS
9141 19:23:21.472192 Write leveling : PASS
9142 19:23:21.475213 RX DQS gating : PASS
9143 19:23:21.475292 RX DQ/DQS(RDDQC) : PASS
9144 19:23:21.478729 TX DQ/DQS : PASS
9145 19:23:21.481626 RX DATLAT : PASS
9146 19:23:21.481725 RX DQ/DQS(Engine): PASS
9147 19:23:21.484962 TX OE : PASS
9148 19:23:21.485041 All Pass.
9149 19:23:21.485103
9150 19:23:21.488203 CH 0, Rank 1
9151 19:23:21.488283 SW Impedance : PASS
9152 19:23:21.491917 DUTY Scan : NO K
9153 19:23:21.495295 ZQ Calibration : PASS
9154 19:23:21.495373 Jitter Meter : NO K
9155 19:23:21.498648 CBT Training : PASS
9156 19:23:21.501850 Write leveling : PASS
9157 19:23:21.501930 RX DQS gating : PASS
9158 19:23:21.505212 RX DQ/DQS(RDDQC) : PASS
9159 19:23:21.505292 TX DQ/DQS : PASS
9160 19:23:21.508524 RX DATLAT : PASS
9161 19:23:21.511784 RX DQ/DQS(Engine): PASS
9162 19:23:21.511879 TX OE : PASS
9163 19:23:21.515038 All Pass.
9164 19:23:21.515128
9165 19:23:21.515203 CH 1, Rank 0
9166 19:23:21.518316 SW Impedance : PASS
9167 19:23:21.518408 DUTY Scan : NO K
9168 19:23:21.521845 ZQ Calibration : PASS
9169 19:23:21.524534 Jitter Meter : NO K
9170 19:23:21.524644 CBT Training : PASS
9171 19:23:21.527815 Write leveling : PASS
9172 19:23:21.531171 RX DQS gating : PASS
9173 19:23:21.531308 RX DQ/DQS(RDDQC) : PASS
9174 19:23:21.534394 TX DQ/DQS : PASS
9175 19:23:21.537897 RX DATLAT : PASS
9176 19:23:21.538049 RX DQ/DQS(Engine): PASS
9177 19:23:21.541185 TX OE : PASS
9178 19:23:21.541377 All Pass.
9179 19:23:21.541543
9180 19:23:21.544403 CH 1, Rank 1
9181 19:23:21.544685 SW Impedance : PASS
9182 19:23:21.547541 DUTY Scan : NO K
9183 19:23:21.551133 ZQ Calibration : PASS
9184 19:23:21.551501 Jitter Meter : NO K
9185 19:23:21.554547 CBT Training : PASS
9186 19:23:21.557535 Write leveling : PASS
9187 19:23:21.557952 RX DQS gating : PASS
9188 19:23:21.561420 RX DQ/DQS(RDDQC) : PASS
9189 19:23:21.564467 TX DQ/DQS : PASS
9190 19:23:21.565044 RX DATLAT : PASS
9191 19:23:21.567972 RX DQ/DQS(Engine): PASS
9192 19:23:21.571138 TX OE : PASS
9193 19:23:21.571587 All Pass.
9194 19:23:21.571946
9195 19:23:21.572258 DramC Write-DBI on
9196 19:23:21.574685 PER_BANK_REFRESH: Hybrid Mode
9197 19:23:21.577739 TX_TRACKING: ON
9198 19:23:21.584312 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9199 19:23:21.594124 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9200 19:23:21.600788 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9201 19:23:21.604207 [FAST_K] Save calibration result to emmc
9202 19:23:21.607412 sync common calibartion params.
9203 19:23:21.610663 sync cbt_mode0:1, 1:1
9204 19:23:21.611077 dram_init: ddr_geometry: 2
9205 19:23:21.613976 dram_init: ddr_geometry: 2
9206 19:23:21.617313 dram_init: ddr_geometry: 2
9207 19:23:21.620666 0:dram_rank_size:100000000
9208 19:23:21.621084 1:dram_rank_size:100000000
9209 19:23:21.627234 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9210 19:23:21.630488 DFS_SHUFFLE_HW_MODE: ON
9211 19:23:21.633832 dramc_set_vcore_voltage set vcore to 725000
9212 19:23:21.636949 Read voltage for 1600, 0
9213 19:23:21.637480 Vio18 = 0
9214 19:23:21.637956 Vcore = 725000
9215 19:23:21.640139 Vdram = 0
9216 19:23:21.640692 Vddq = 0
9217 19:23:21.641202 Vmddr = 0
9218 19:23:21.643587 switch to 3200 Mbps bootup
9219 19:23:21.644032 [DramcRunTimeConfig]
9220 19:23:21.646887 PHYPLL
9221 19:23:21.647301 DPM_CONTROL_AFTERK: ON
9222 19:23:21.650090 PER_BANK_REFRESH: ON
9223 19:23:21.653259 REFRESH_OVERHEAD_REDUCTION: ON
9224 19:23:21.653799 CMD_PICG_NEW_MODE: OFF
9225 19:23:21.656794 XRTWTW_NEW_MODE: ON
9226 19:23:21.657220 XRTRTR_NEW_MODE: ON
9227 19:23:21.659862 TX_TRACKING: ON
9228 19:23:21.660464 RDSEL_TRACKING: OFF
9229 19:23:21.663070 DQS Precalculation for DVFS: ON
9230 19:23:21.666820 RX_TRACKING: OFF
9231 19:23:21.667256 HW_GATING DBG: ON
9232 19:23:21.669523 ZQCS_ENABLE_LP4: ON
9233 19:23:21.669949 RX_PICG_NEW_MODE: ON
9234 19:23:21.672914 TX_PICG_NEW_MODE: ON
9235 19:23:21.673467 ENABLE_RX_DCM_DPHY: ON
9236 19:23:21.676493 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9237 19:23:21.680201 DUMMY_READ_FOR_TRACKING: OFF
9238 19:23:21.683231 !!! SPM_CONTROL_AFTERK: OFF
9239 19:23:21.686638 !!! SPM could not control APHY
9240 19:23:21.687219 IMPEDANCE_TRACKING: ON
9241 19:23:21.689422 TEMP_SENSOR: ON
9242 19:23:21.689840 HW_SAVE_FOR_SR: OFF
9243 19:23:21.692810 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9244 19:23:21.695904 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9245 19:23:21.699346 Read ODT Tracking: ON
9246 19:23:21.702614 Refresh Rate DeBounce: ON
9247 19:23:21.703041 DFS_NO_QUEUE_FLUSH: ON
9248 19:23:21.706073 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9249 19:23:21.709237 ENABLE_DFS_RUNTIME_MRW: OFF
9250 19:23:21.712573 DDR_RESERVE_NEW_MODE: ON
9251 19:23:21.712673 MR_CBT_SWITCH_FREQ: ON
9252 19:23:21.715666 =========================
9253 19:23:21.734728 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9254 19:23:21.737900 dram_init: ddr_geometry: 2
9255 19:23:21.756263 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9256 19:23:21.759501 dram_init: dram init end (result: 0)
9257 19:23:21.766045 DRAM-K: Full calibration passed in 24606 msecs
9258 19:23:21.769305 MRC: failed to locate region type 0.
9259 19:23:21.769428 DRAM rank0 size:0x100000000,
9260 19:23:21.772670 DRAM rank1 size=0x100000000
9261 19:23:21.782832 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9262 19:23:21.789262 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9263 19:23:21.795898 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9264 19:23:21.805846 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9265 19:23:21.805928 DRAM rank0 size:0x100000000,
9266 19:23:21.809065 DRAM rank1 size=0x100000000
9267 19:23:21.809146 CBMEM:
9268 19:23:21.812502 IMD: root @ 0xfffff000 254 entries.
9269 19:23:21.815808 IMD: root @ 0xffffec00 62 entries.
9270 19:23:21.818899 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9271 19:23:21.825605 WARNING: RO_VPD is uninitialized or empty.
9272 19:23:21.828405 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9273 19:23:21.836905 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9274 19:23:21.849177 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9275 19:23:21.860454 BS: romstage times (exec / console): total (unknown) / 24099 ms
9276 19:23:21.860577
9277 19:23:21.860693
9278 19:23:21.870147 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9279 19:23:21.873293 ARM64: Exception handlers installed.
9280 19:23:21.877365 ARM64: Testing exception
9281 19:23:21.880522 ARM64: Done test exception
9282 19:23:21.880597 Enumerating buses...
9283 19:23:21.883699 Show all devs... Before device enumeration.
9284 19:23:21.886875 Root Device: enabled 1
9285 19:23:21.890037 CPU_CLUSTER: 0: enabled 1
9286 19:23:21.890155 CPU: 00: enabled 1
9287 19:23:21.893472 Compare with tree...
9288 19:23:21.893554 Root Device: enabled 1
9289 19:23:21.896937 CPU_CLUSTER: 0: enabled 1
9290 19:23:21.900196 CPU: 00: enabled 1
9291 19:23:21.900307 Root Device scanning...
9292 19:23:21.903016 scan_static_bus for Root Device
9293 19:23:21.906946 CPU_CLUSTER: 0 enabled
9294 19:23:21.909650 scan_static_bus for Root Device done
9295 19:23:21.912812 scan_bus: bus Root Device finished in 8 msecs
9296 19:23:21.912916 done
9297 19:23:21.919643 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9298 19:23:21.923134 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9299 19:23:21.929659 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9300 19:23:21.936074 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9301 19:23:21.936201 Allocating resources...
9302 19:23:21.939223 Reading resources...
9303 19:23:21.942803 Root Device read_resources bus 0 link: 0
9304 19:23:21.946075 DRAM rank0 size:0x100000000,
9305 19:23:21.946182 DRAM rank1 size=0x100000000
9306 19:23:21.953036 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9307 19:23:21.953149 CPU: 00 missing read_resources
9308 19:23:21.959511 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9309 19:23:21.962909 Root Device read_resources bus 0 link: 0 done
9310 19:23:21.966162 Done reading resources.
9311 19:23:21.969534 Show resources in subtree (Root Device)...After reading.
9312 19:23:21.972788 Root Device child on link 0 CPU_CLUSTER: 0
9313 19:23:21.975564 CPU_CLUSTER: 0 child on link 0 CPU: 00
9314 19:23:21.985588 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9315 19:23:21.985674 CPU: 00
9316 19:23:21.991886 Root Device assign_resources, bus 0 link: 0
9317 19:23:21.995662 CPU_CLUSTER: 0 missing set_resources
9318 19:23:21.998842 Root Device assign_resources, bus 0 link: 0 done
9319 19:23:21.998926 Done setting resources.
9320 19:23:22.005743 Show resources in subtree (Root Device)...After assigning values.
9321 19:23:22.008946 Root Device child on link 0 CPU_CLUSTER: 0
9322 19:23:22.012471 CPU_CLUSTER: 0 child on link 0 CPU: 00
9323 19:23:22.022309 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9324 19:23:22.022396 CPU: 00
9325 19:23:22.025546 Done allocating resources.
9326 19:23:22.032373 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9327 19:23:22.032482 Enabling resources...
9328 19:23:22.034980 done.
9329 19:23:22.038615 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9330 19:23:22.041691 Initializing devices...
9331 19:23:22.041776 Root Device init
9332 19:23:22.045126 init hardware done!
9333 19:23:22.045208 0x00000018: ctrlr->caps
9334 19:23:22.048590 52.000 MHz: ctrlr->f_max
9335 19:23:22.051407 0.400 MHz: ctrlr->f_min
9336 19:23:22.051496 0x40ff8080: ctrlr->voltages
9337 19:23:22.054970 sclk: 390625
9338 19:23:22.055053 Bus Width = 1
9339 19:23:22.057876 sclk: 390625
9340 19:23:22.057973 Bus Width = 1
9341 19:23:22.061737 Early init status = 3
9342 19:23:22.064966 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9343 19:23:22.068981 in-header: 03 fc 00 00 01 00 00 00
9344 19:23:22.072294 in-data: 00
9345 19:23:22.075717 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9346 19:23:22.080968 in-header: 03 fd 00 00 00 00 00 00
9347 19:23:22.084398 in-data:
9348 19:23:22.087602 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9349 19:23:22.092360 in-header: 03 fc 00 00 01 00 00 00
9350 19:23:22.095751 in-data: 00
9351 19:23:22.098952 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9352 19:23:22.104603 in-header: 03 fd 00 00 00 00 00 00
9353 19:23:22.107716 in-data:
9354 19:23:22.110794 [SSUSB] Setting up USB HOST controller...
9355 19:23:22.114577 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9356 19:23:22.117717 [SSUSB] phy power-on done.
9357 19:23:22.120992 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9358 19:23:22.127695 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9359 19:23:22.131061 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9360 19:23:22.137862 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9361 19:23:22.143717 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9362 19:23:22.150460 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9363 19:23:22.157113 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9364 19:23:22.164106 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9365 19:23:22.167040 SPM: binary array size = 0x9dc
9366 19:23:22.170538 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9367 19:23:22.177147 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9368 19:23:22.183655 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9369 19:23:22.190269 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9370 19:23:22.193523 configure_display: Starting display init
9371 19:23:22.227941 anx7625_power_on_init: Init interface.
9372 19:23:22.231163 anx7625_disable_pd_protocol: Disabled PD feature.
9373 19:23:22.234481 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9374 19:23:22.262325 anx7625_start_dp_work: Secure OCM version=00
9375 19:23:22.265316 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9376 19:23:22.280122 sp_tx_get_edid_block: EDID Block = 1
9377 19:23:22.382564 Extracted contents:
9378 19:23:22.386089 header: 00 ff ff ff ff ff ff 00
9379 19:23:22.389247 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9380 19:23:22.392551 version: 01 04
9381 19:23:22.396115 basic params: 95 1f 11 78 0a
9382 19:23:22.399242 chroma info: 76 90 94 55 54 90 27 21 50 54
9383 19:23:22.402738 established: 00 00 00
9384 19:23:22.409111 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9385 19:23:22.412603 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9386 19:23:22.419282 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9387 19:23:22.425496 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9388 19:23:22.432211 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9389 19:23:22.435485 extensions: 00
9390 19:23:22.435570 checksum: fb
9391 19:23:22.435683
9392 19:23:22.442247 Manufacturer: IVO Model 57d Serial Number 0
9393 19:23:22.442355 Made week 0 of 2020
9394 19:23:22.445466 EDID version: 1.4
9395 19:23:22.445573 Digital display
9396 19:23:22.448816 6 bits per primary color channel
9397 19:23:22.448923 DisplayPort interface
9398 19:23:22.452161 Maximum image size: 31 cm x 17 cm
9399 19:23:22.454897 Gamma: 220%
9400 19:23:22.454978 Check DPMS levels
9401 19:23:22.461703 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9402 19:23:22.465033 First detailed timing is preferred timing
9403 19:23:22.465141 Established timings supported:
9404 19:23:22.468250 Standard timings supported:
9405 19:23:22.471756 Detailed timings
9406 19:23:22.474903 Hex of detail: 383680a07038204018303c0035ae10000019
9407 19:23:22.481831 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9408 19:23:22.484793 0780 0798 07c8 0820 hborder 0
9409 19:23:22.487999 0438 043b 0447 0458 vborder 0
9410 19:23:22.491290 -hsync -vsync
9411 19:23:22.491374 Did detailed timing
9412 19:23:22.498440 Hex of detail: 000000000000000000000000000000000000
9413 19:23:22.501832 Manufacturer-specified data, tag 0
9414 19:23:22.505142 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9415 19:23:22.508137 ASCII string: InfoVision
9416 19:23:22.511262 Hex of detail: 000000fe00523134304e574635205248200a
9417 19:23:22.514761 ASCII string: R140NWF5 RH
9418 19:23:22.514842 Checksum
9419 19:23:22.518073 Checksum: 0xfb (valid)
9420 19:23:22.521856 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9421 19:23:22.525006 DSI data_rate: 832800000 bps
9422 19:23:22.531550 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9423 19:23:22.534623 anx7625_parse_edid: pixelclock(138800).
9424 19:23:22.538015 hactive(1920), hsync(48), hfp(24), hbp(88)
9425 19:23:22.541864 vactive(1080), vsync(12), vfp(3), vbp(17)
9426 19:23:22.545514 anx7625_dsi_config: config dsi.
9427 19:23:22.551435 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9428 19:23:22.564799 anx7625_dsi_config: success to config DSI
9429 19:23:22.568139 anx7625_dp_start: MIPI phy setup OK.
9430 19:23:22.571604 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9431 19:23:22.574828 mtk_ddp_mode_set invalid vrefresh 60
9432 19:23:22.578242 main_disp_path_setup
9433 19:23:22.578661 ovl_layer_smi_id_en
9434 19:23:22.581608 ovl_layer_smi_id_en
9435 19:23:22.582142 ccorr_config
9436 19:23:22.582647 aal_config
9437 19:23:22.585403 gamma_config
9438 19:23:22.585818 postmask_config
9439 19:23:22.588548 dither_config
9440 19:23:22.591511 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9441 19:23:22.598235 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9442 19:23:22.601223 Root Device init finished in 555 msecs
9443 19:23:22.604722 CPU_CLUSTER: 0 init
9444 19:23:22.611345 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9445 19:23:22.617802 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9446 19:23:22.618219 APU_MBOX 0x190000b0 = 0x10001
9447 19:23:22.621012 APU_MBOX 0x190001b0 = 0x10001
9448 19:23:22.624823 APU_MBOX 0x190005b0 = 0x10001
9449 19:23:22.627610 APU_MBOX 0x190006b0 = 0x10001
9450 19:23:22.634092 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9451 19:23:22.643861 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9452 19:23:22.656575 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9453 19:23:22.663294 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9454 19:23:22.674775 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9455 19:23:22.684097 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9456 19:23:22.687293 CPU_CLUSTER: 0 init finished in 81 msecs
9457 19:23:22.690206 Devices initialized
9458 19:23:22.693577 Show all devs... After init.
9459 19:23:22.693994 Root Device: enabled 1
9460 19:23:22.696765 CPU_CLUSTER: 0: enabled 1
9461 19:23:22.700242 CPU: 00: enabled 1
9462 19:23:22.703767 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9463 19:23:22.706886 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9464 19:23:22.710069 ELOG: NV offset 0x57f000 size 0x1000
9465 19:23:22.717384 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9466 19:23:22.723852 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9467 19:23:22.727136 ELOG: Event(17) added with size 13 at 2024-04-18 19:23:22 UTC
9468 19:23:22.733508 out: cmd=0x121: 03 db 21 01 00 00 00 00
9469 19:23:22.736705 in-header: 03 b2 00 00 2c 00 00 00
9470 19:23:22.749495 in-data: ad 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9471 19:23:22.753043 ELOG: Event(A1) added with size 10 at 2024-04-18 19:23:22 UTC
9472 19:23:22.759682 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9473 19:23:22.766144 ELOG: Event(A0) added with size 9 at 2024-04-18 19:23:22 UTC
9474 19:23:22.769175 elog_add_boot_reason: Logged dev mode boot
9475 19:23:22.775956 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9476 19:23:22.776039 Finalize devices...
9477 19:23:22.779185 Devices finalized
9478 19:23:22.782541 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9479 19:23:22.785750 Writing coreboot table at 0xffe64000
9480 19:23:22.792323 0. 000000000010a000-0000000000113fff: RAMSTAGE
9481 19:23:22.795325 1. 0000000040000000-00000000400fffff: RAM
9482 19:23:22.798632 2. 0000000040100000-000000004032afff: RAMSTAGE
9483 19:23:22.801992 3. 000000004032b000-00000000545fffff: RAM
9484 19:23:22.805167 4. 0000000054600000-000000005465ffff: BL31
9485 19:23:22.811763 5. 0000000054660000-00000000ffe63fff: RAM
9486 19:23:22.815276 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9487 19:23:22.818656 7. 0000000100000000-000000023fffffff: RAM
9488 19:23:22.822002 Passing 5 GPIOs to payload:
9489 19:23:22.827946 NAME | PORT | POLARITY | VALUE
9490 19:23:22.831322 EC in RW | 0x000000aa | low | undefined
9491 19:23:22.835195 EC interrupt | 0x00000005 | low | undefined
9492 19:23:22.841766 TPM interrupt | 0x000000ab | high | undefined
9493 19:23:22.844913 SD card detect | 0x00000011 | high | undefined
9494 19:23:22.851145 speaker enable | 0x00000093 | high | undefined
9495 19:23:22.855140 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9496 19:23:22.857869 in-header: 03 f9 00 00 02 00 00 00
9497 19:23:22.857965 in-data: 02 00
9498 19:23:22.861496 ADC[4]: Raw value=904509 ID=7
9499 19:23:22.864737 ADC[3]: Raw value=213282 ID=1
9500 19:23:22.864822 RAM Code: 0x71
9501 19:23:22.867859 ADC[6]: Raw value=75036 ID=0
9502 19:23:22.871064 ADC[5]: Raw value=213652 ID=1
9503 19:23:22.871144 SKU Code: 0x1
9504 19:23:22.877754 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 9e1
9505 19:23:22.881298 coreboot table: 964 bytes.
9506 19:23:22.884144 IMD ROOT 0. 0xfffff000 0x00001000
9507 19:23:22.887650 IMD SMALL 1. 0xffffe000 0x00001000
9508 19:23:22.890908 RO MCACHE 2. 0xffffc000 0x00001104
9509 19:23:22.894329 CONSOLE 3. 0xfff7c000 0x00080000
9510 19:23:22.897490 FMAP 4. 0xfff7b000 0x00000452
9511 19:23:22.900744 TIME STAMP 5. 0xfff7a000 0x00000910
9512 19:23:22.904348 VBOOT WORK 6. 0xfff66000 0x00014000
9513 19:23:22.907802 RAMOOPS 7. 0xffe66000 0x00100000
9514 19:23:22.910995 COREBOOT 8. 0xffe64000 0x00002000
9515 19:23:22.911076 IMD small region:
9516 19:23:22.914216 IMD ROOT 0. 0xffffec00 0x00000400
9517 19:23:22.917256 VPD 1. 0xffffeb80 0x0000006c
9518 19:23:22.920913 MMC STATUS 2. 0xffffeb60 0x00000004
9519 19:23:22.927592 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9520 19:23:22.927675 Probing TPM: done!
9521 19:23:22.934073 Connected to device vid:did:rid of 1ae0:0028:00
9522 19:23:22.943610 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9523 19:23:22.947636 Initialized TPM device CR50 revision 0
9524 19:23:22.947718 Checking cr50 for pending updates
9525 19:23:22.953959 Reading cr50 TPM mode
9526 19:23:22.962470 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9527 19:23:22.968902 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9528 19:23:23.008652 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9529 19:23:23.012063 Checking segment from ROM address 0x40100000
9530 19:23:23.019371 Checking segment from ROM address 0x4010001c
9531 19:23:23.022029 Loading segment from ROM address 0x40100000
9532 19:23:23.022112 code (compression=0)
9533 19:23:23.032227 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9534 19:23:23.038707 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9535 19:23:23.038797 it's not compressed!
9536 19:23:23.045843 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9537 19:23:23.052311 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9538 19:23:23.069247 Loading segment from ROM address 0x4010001c
9539 19:23:23.069378 Entry Point 0x80000000
9540 19:23:23.072607 Loaded segments
9541 19:23:23.075753 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9542 19:23:23.082704 Jumping to boot code at 0x80000000(0xffe64000)
9543 19:23:23.089222 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9544 19:23:23.095758 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9545 19:23:23.103892 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9546 19:23:23.107750 Checking segment from ROM address 0x40100000
9547 19:23:23.110606 Checking segment from ROM address 0x4010001c
9548 19:23:23.117088 Loading segment from ROM address 0x40100000
9549 19:23:23.117215 code (compression=1)
9550 19:23:23.123979 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9551 19:23:23.133599 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9552 19:23:23.133687 using LZMA
9553 19:23:23.142167 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9554 19:23:23.148613 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9555 19:23:23.151809 Loading segment from ROM address 0x4010001c
9556 19:23:23.151893 Entry Point 0x54601000
9557 19:23:23.155855 Loaded segments
9558 19:23:23.159053 NOTICE: MT8192 bl31_setup
9559 19:23:23.165704 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9560 19:23:23.169213 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9561 19:23:23.172646 WARNING: region 0:
9562 19:23:23.175319 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9563 19:23:23.175401 WARNING: region 1:
9564 19:23:23.182341 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9565 19:23:23.185592 WARNING: region 2:
9566 19:23:23.188946 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9567 19:23:23.192230 WARNING: region 3:
9568 19:23:23.195413 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9569 19:23:23.198743 WARNING: region 4:
9570 19:23:23.205169 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9571 19:23:23.205255 WARNING: region 5:
9572 19:23:23.208360 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9573 19:23:23.211762 WARNING: region 6:
9574 19:23:23.214963 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9575 19:23:23.218864 WARNING: region 7:
9576 19:23:23.221892 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9577 19:23:23.228618 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9578 19:23:23.231472 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9579 19:23:23.238881 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9580 19:23:23.241490 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9581 19:23:23.245061 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9582 19:23:23.251660 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9583 19:23:23.254904 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9584 19:23:23.258217 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9585 19:23:23.264809 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9586 19:23:23.267952 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9587 19:23:23.274848 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9588 19:23:23.278083 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9589 19:23:23.281273 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9590 19:23:23.288368 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9591 19:23:23.291625 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9592 19:23:23.294760 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9593 19:23:23.301187 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9594 19:23:23.304414 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9595 19:23:23.310857 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9596 19:23:23.314138 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9597 19:23:23.318004 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9598 19:23:23.324540 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9599 19:23:23.327786 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9600 19:23:23.334269 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9601 19:23:23.337241 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9602 19:23:23.340963 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9603 19:23:23.347288 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9604 19:23:23.350742 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9605 19:23:23.357513 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9606 19:23:23.361015 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9607 19:23:23.364318 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9608 19:23:23.370885 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9609 19:23:23.374244 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9610 19:23:23.377614 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9611 19:23:23.384261 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9612 19:23:23.386976 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9613 19:23:23.390291 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9614 19:23:23.394140 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9615 19:23:23.400534 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9616 19:23:23.403839 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9617 19:23:23.407298 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9618 19:23:23.410537 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9619 19:23:23.417039 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9620 19:23:23.420304 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9621 19:23:23.423741 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9622 19:23:23.427105 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9623 19:23:23.433491 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9624 19:23:23.437189 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9625 19:23:23.440311 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9626 19:23:23.447015 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9627 19:23:23.450071 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9628 19:23:23.457051 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9629 19:23:23.460278 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9630 19:23:23.466981 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9631 19:23:23.470050 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9632 19:23:23.473412 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9633 19:23:23.479876 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9634 19:23:23.483706 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9635 19:23:23.489866 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9636 19:23:23.493273 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9637 19:23:23.500286 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9638 19:23:23.503344 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9639 19:23:23.510602 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9640 19:23:23.513480 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9641 19:23:23.516601 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9642 19:23:23.523151 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9643 19:23:23.526358 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9644 19:23:23.532971 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9645 19:23:23.536919 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9646 19:23:23.543341 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9647 19:23:23.546687 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9648 19:23:23.552909 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9649 19:23:23.556218 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9650 19:23:23.559599 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9651 19:23:23.565867 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9652 19:23:23.569627 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9653 19:23:23.575876 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9654 19:23:23.579493 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9655 19:23:23.585930 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9656 19:23:23.589495 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9657 19:23:23.595966 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9658 19:23:23.599172 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9659 19:23:23.602544 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9660 19:23:23.609128 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9661 19:23:23.612882 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9662 19:23:23.619348 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9663 19:23:23.622563 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9664 19:23:23.629315 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9665 19:23:23.632404 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9666 19:23:23.635660 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9667 19:23:23.642325 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9668 19:23:23.645647 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9669 19:23:23.652249 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9670 19:23:23.655580 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9671 19:23:23.662173 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9672 19:23:23.665416 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9673 19:23:23.668625 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9674 19:23:23.675700 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9675 19:23:23.678802 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9676 19:23:23.681895 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9677 19:23:23.685590 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9678 19:23:23.692403 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9679 19:23:23.695163 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9680 19:23:23.701832 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9681 19:23:23.705364 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9682 19:23:23.708231 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9683 19:23:23.715650 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9684 19:23:23.718496 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9685 19:23:23.725109 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9686 19:23:23.728288 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9687 19:23:23.731613 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9688 19:23:23.737974 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9689 19:23:23.741457 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9690 19:23:23.748414 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9691 19:23:23.751664 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9692 19:23:23.754958 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9693 19:23:23.761802 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9694 19:23:23.765013 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9695 19:23:23.768301 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9696 19:23:23.775082 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9697 19:23:23.778234 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9698 19:23:23.781557 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9699 19:23:23.784936 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9700 19:23:23.791105 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9701 19:23:23.794387 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9702 19:23:23.797651 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9703 19:23:23.804131 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9704 19:23:23.807978 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9705 19:23:23.814448 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9706 19:23:23.818060 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9707 19:23:23.821054 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9708 19:23:23.827369 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9709 19:23:23.831062 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9710 19:23:23.837524 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9711 19:23:23.840880 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9712 19:23:23.844174 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9713 19:23:23.850702 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9714 19:23:23.854042 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9715 19:23:23.860843 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9716 19:23:23.864187 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9717 19:23:23.867615 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9718 19:23:23.874036 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9719 19:23:23.877090 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9720 19:23:23.884014 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9721 19:23:23.887225 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9722 19:23:23.890495 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9723 19:23:23.897044 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9724 19:23:23.900579 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9725 19:23:23.906932 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9726 19:23:23.910626 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9727 19:23:23.913945 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9728 19:23:23.920184 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9729 19:23:23.923720 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9730 19:23:23.929933 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9731 19:23:23.933432 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9732 19:23:23.936840 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9733 19:23:23.943533 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9734 19:23:23.946939 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9735 19:23:23.950182 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9736 19:23:23.956798 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9737 19:23:23.960225 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9738 19:23:23.966893 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9739 19:23:23.970087 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9740 19:23:23.973220 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9741 19:23:23.979928 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9742 19:23:23.983148 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9743 19:23:23.989795 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9744 19:23:23.992864 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9745 19:23:23.996240 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9746 19:23:24.003504 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9747 19:23:24.006593 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9748 19:23:24.013416 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9749 19:23:24.016648 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9750 19:23:24.019946 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9751 19:23:24.026518 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9752 19:23:24.029861 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9753 19:23:24.036430 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9754 19:23:24.039606 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9755 19:23:24.046280 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9756 19:23:24.049136 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9757 19:23:24.052545 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9758 19:23:24.059214 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9759 19:23:24.062674 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9760 19:23:24.065736 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9761 19:23:24.072246 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9762 19:23:24.076188 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9763 19:23:24.082476 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9764 19:23:24.085698 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9765 19:23:24.092286 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9766 19:23:24.095522 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9767 19:23:24.098673 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9768 19:23:24.105367 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9769 19:23:24.108464 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9770 19:23:24.115084 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9771 19:23:24.118972 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9772 19:23:24.121901 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9773 19:23:24.128508 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9774 19:23:24.131842 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9775 19:23:24.138277 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9776 19:23:24.141685 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9777 19:23:24.148726 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9778 19:23:24.151985 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9779 19:23:24.155361 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9780 19:23:24.161619 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9781 19:23:24.165016 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9782 19:23:24.171660 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9783 19:23:24.174979 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9784 19:23:24.181598 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9785 19:23:24.184493 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9786 19:23:24.188082 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9787 19:23:24.194324 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9788 19:23:24.197725 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9789 19:23:24.204660 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9790 19:23:24.207921 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9791 19:23:24.213927 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9792 19:23:24.217409 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9793 19:23:24.220622 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9794 19:23:24.227209 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9795 19:23:24.231196 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9796 19:23:24.237140 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9797 19:23:24.240735 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9798 19:23:24.247285 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9799 19:23:24.250368 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9800 19:23:24.253602 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9801 19:23:24.260144 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9802 19:23:24.263551 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9803 19:23:24.270540 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9804 19:23:24.273816 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9805 19:23:24.280408 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9806 19:23:24.283541 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9807 19:23:24.286653 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9808 19:23:24.289788 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9809 19:23:24.293483 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9810 19:23:24.299746 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9811 19:23:24.303115 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9812 19:23:24.309623 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9813 19:23:24.313039 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9814 19:23:24.316237 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9815 19:23:24.322934 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9816 19:23:24.326205 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9817 19:23:24.329440 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9818 19:23:24.336074 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9819 19:23:24.339266 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9820 19:23:24.346264 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9821 19:23:24.349267 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9822 19:23:24.352450 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9823 19:23:24.359445 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9824 19:23:24.362046 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9825 19:23:24.365370 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9826 19:23:24.372573 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9827 19:23:24.375416 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9828 19:23:24.381799 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9829 19:23:24.385135 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9830 19:23:24.388363 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9831 19:23:24.395409 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9832 19:23:24.398543 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9833 19:23:24.405293 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9834 19:23:24.408328 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9835 19:23:24.412111 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9836 19:23:24.418312 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9837 19:23:24.421858 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9838 19:23:24.425045 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9839 19:23:24.431721 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9840 19:23:24.434892 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9841 19:23:24.438028 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9842 19:23:24.444631 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9843 19:23:24.447909 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9844 19:23:24.454272 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9845 19:23:24.457644 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9846 19:23:24.461273 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9847 19:23:24.464166 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9848 19:23:24.471320 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9849 19:23:24.474793 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9850 19:23:24.477549 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9851 19:23:24.480688 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9852 19:23:24.487822 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9853 19:23:24.490883 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9854 19:23:24.494139 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9855 19:23:24.497192 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9856 19:23:24.503751 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9857 19:23:24.507183 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9858 19:23:24.510430 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9859 19:23:24.516880 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9860 19:23:24.520651 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9861 19:23:24.526779 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9862 19:23:24.530781 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9863 19:23:24.536815 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9864 19:23:24.540244 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9865 19:23:24.543085 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9866 19:23:24.549839 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9867 19:23:24.552965 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9868 19:23:24.560009 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9869 19:23:24.563448 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9870 19:23:24.566559 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9871 19:23:24.572984 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9872 19:23:24.575998 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9873 19:23:24.582562 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9874 19:23:24.585850 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9875 19:23:24.589470 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9876 19:23:24.595904 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9877 19:23:24.599611 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9878 19:23:24.606082 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9879 19:23:24.609322 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9880 19:23:24.616042 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9881 19:23:24.619193 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9882 19:23:24.622402 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9883 19:23:24.628980 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9884 19:23:24.632395 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9885 19:23:24.638576 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9886 19:23:24.641912 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9887 19:23:24.649088 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9888 19:23:24.652041 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9889 19:23:24.655091 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9890 19:23:24.662341 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9891 19:23:24.665711 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9892 19:23:24.671723 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9893 19:23:24.675007 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9894 19:23:24.678309 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9895 19:23:24.685355 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9896 19:23:24.688241 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9897 19:23:24.694834 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9898 19:23:24.698543 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9899 19:23:24.701835 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9900 19:23:24.708075 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9901 19:23:24.711615 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9902 19:23:24.718254 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9903 19:23:24.721634 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9904 19:23:24.728039 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9905 19:23:24.731256 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9906 19:23:24.734405 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9907 19:23:24.740932 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9908 19:23:24.744137 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9909 19:23:24.750659 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9910 19:23:24.753723 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9911 19:23:24.760695 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9912 19:23:24.763603 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9913 19:23:24.770791 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9914 19:23:24.774082 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9915 19:23:24.777446 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9916 19:23:24.784053 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9917 19:23:24.787154 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9918 19:23:24.793748 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9919 19:23:24.796947 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9920 19:23:24.800319 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9921 19:23:24.806997 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9922 19:23:24.809689 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9923 19:23:24.816359 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9924 19:23:24.819907 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9925 19:23:24.822838 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9926 19:23:24.829664 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9927 19:23:24.832847 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9928 19:23:24.839518 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9929 19:23:24.842705 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9930 19:23:24.849326 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9931 19:23:24.852750 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9932 19:23:24.855920 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9933 19:23:24.862652 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9934 19:23:24.865892 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9935 19:23:24.872294 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9936 19:23:24.875849 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9937 19:23:24.882556 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9938 19:23:24.885742 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9939 19:23:24.892301 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9940 19:23:24.895505 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9941 19:23:24.898643 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9942 19:23:24.905348 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9943 19:23:24.908706 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9944 19:23:24.915396 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9945 19:23:24.918563 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9946 19:23:24.925461 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9947 19:23:24.928495 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9948 19:23:24.934933 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9949 19:23:24.938416 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9950 19:23:24.945141 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9951 19:23:24.948511 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9952 19:23:24.951649 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9953 19:23:24.957993 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9954 19:23:24.961422 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9955 19:23:24.967728 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9956 19:23:24.971351 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9957 19:23:24.978144 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9958 19:23:24.981229 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9959 19:23:24.987482 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9960 19:23:24.990579 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9961 19:23:24.997680 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9962 19:23:25.001158 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9963 19:23:25.004227 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9964 19:23:25.010670 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9965 19:23:25.013996 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9966 19:23:25.020641 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9967 19:23:25.023806 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9968 19:23:25.030677 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9969 19:23:25.033937 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9970 19:23:25.037147 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9971 19:23:25.043441 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9972 19:23:25.046710 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9973 19:23:25.053495 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9974 19:23:25.056402 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9975 19:23:25.063639 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9976 19:23:25.066898 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9977 19:23:25.073317 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9978 19:23:25.076602 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9979 19:23:25.079850 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9980 19:23:25.086420 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9981 19:23:25.089549 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9982 19:23:25.095859 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9983 19:23:25.099590 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9984 19:23:25.106243 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9985 19:23:25.109018 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9986 19:23:25.115891 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9987 19:23:25.119096 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9988 19:23:25.126268 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9989 19:23:25.129456 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9990 19:23:25.136001 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9991 19:23:25.139207 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9992 19:23:25.145587 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9993 19:23:25.148918 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9994 19:23:25.155334 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9995 19:23:25.158611 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9996 19:23:25.165453 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9997 19:23:25.168824 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9998 19:23:25.172453 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9999 19:23:25.178756 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
10000 19:23:25.185401 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
10001 19:23:25.188601 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
10002 19:23:25.195281 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
10003 19:23:25.198862 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
10004 19:23:25.205478 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
10005 19:23:25.209033 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
10006 19:23:25.215420 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
10007 19:23:25.218538 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
10008 19:23:25.225132 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
10009 19:23:25.228531 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
10010 19:23:25.234592 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
10011 19:23:25.237900 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
10012 19:23:25.241052 INFO: [APUAPC] vio 0
10013 19:23:25.244469 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
10014 19:23:25.250800 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
10015 19:23:25.254596 INFO: [APUAPC] D0_APC_0: 0x400510
10016 19:23:25.254678 INFO: [APUAPC] D0_APC_1: 0x0
10017 19:23:25.257984 INFO: [APUAPC] D0_APC_2: 0x1540
10018 19:23:25.261206 INFO: [APUAPC] D0_APC_3: 0x0
10019 19:23:25.264555 INFO: [APUAPC] D1_APC_0: 0xffffffff
10020 19:23:25.267787 INFO: [APUAPC] D1_APC_1: 0xffffffff
10021 19:23:25.271069 INFO: [APUAPC] D1_APC_2: 0x3fffff
10022 19:23:25.274319 INFO: [APUAPC] D1_APC_3: 0x0
10023 19:23:25.277662 INFO: [APUAPC] D2_APC_0: 0xffffffff
10024 19:23:25.280787 INFO: [APUAPC] D2_APC_1: 0xffffffff
10025 19:23:25.283982 INFO: [APUAPC] D2_APC_2: 0x3fffff
10026 19:23:25.287239 INFO: [APUAPC] D2_APC_3: 0x0
10027 19:23:25.290576 INFO: [APUAPC] D3_APC_0: 0xffffffff
10028 19:23:25.293762 INFO: [APUAPC] D3_APC_1: 0xffffffff
10029 19:23:25.297311 INFO: [APUAPC] D3_APC_2: 0x3fffff
10030 19:23:25.300812 INFO: [APUAPC] D3_APC_3: 0x0
10031 19:23:25.303508 INFO: [APUAPC] D4_APC_0: 0xffffffff
10032 19:23:25.306899 INFO: [APUAPC] D4_APC_1: 0xffffffff
10033 19:23:25.310322 INFO: [APUAPC] D4_APC_2: 0x3fffff
10034 19:23:25.313310 INFO: [APUAPC] D4_APC_3: 0x0
10035 19:23:25.316895 INFO: [APUAPC] D5_APC_0: 0xffffffff
10036 19:23:25.320103 INFO: [APUAPC] D5_APC_1: 0xffffffff
10037 19:23:25.323505 INFO: [APUAPC] D5_APC_2: 0x3fffff
10038 19:23:25.326901 INFO: [APUAPC] D5_APC_3: 0x0
10039 19:23:25.330043 INFO: [APUAPC] D6_APC_0: 0xffffffff
10040 19:23:25.333524 INFO: [APUAPC] D6_APC_1: 0xffffffff
10041 19:23:25.336704 INFO: [APUAPC] D6_APC_2: 0x3fffff
10042 19:23:25.340027 INFO: [APUAPC] D6_APC_3: 0x0
10043 19:23:25.343002 INFO: [APUAPC] D7_APC_0: 0xffffffff
10044 19:23:25.346901 INFO: [APUAPC] D7_APC_1: 0xffffffff
10045 19:23:25.349650 INFO: [APUAPC] D7_APC_2: 0x3fffff
10046 19:23:25.352949 INFO: [APUAPC] D7_APC_3: 0x0
10047 19:23:25.356728 INFO: [APUAPC] D8_APC_0: 0xffffffff
10048 19:23:25.359910 INFO: [APUAPC] D8_APC_1: 0xffffffff
10049 19:23:25.363205 INFO: [APUAPC] D8_APC_2: 0x3fffff
10050 19:23:25.366538 INFO: [APUAPC] D8_APC_3: 0x0
10051 19:23:25.369835 INFO: [APUAPC] D9_APC_0: 0xffffffff
10052 19:23:25.373068 INFO: [APUAPC] D9_APC_1: 0xffffffff
10053 19:23:25.376303 INFO: [APUAPC] D9_APC_2: 0x3fffff
10054 19:23:25.379669 INFO: [APUAPC] D9_APC_3: 0x0
10055 19:23:25.382972 INFO: [APUAPC] D10_APC_0: 0xffffffff
10056 19:23:25.386162 INFO: [APUAPC] D10_APC_1: 0xffffffff
10057 19:23:25.389516 INFO: [APUAPC] D10_APC_2: 0x3fffff
10058 19:23:25.392899 INFO: [APUAPC] D10_APC_3: 0x0
10059 19:23:25.396112 INFO: [APUAPC] D11_APC_0: 0xffffffff
10060 19:23:25.399275 INFO: [APUAPC] D11_APC_1: 0xffffffff
10061 19:23:25.402628 INFO: [APUAPC] D11_APC_2: 0x3fffff
10062 19:23:25.405850 INFO: [APUAPC] D11_APC_3: 0x0
10063 19:23:25.408993 INFO: [APUAPC] D12_APC_0: 0xffffffff
10064 19:23:25.412607 INFO: [APUAPC] D12_APC_1: 0xffffffff
10065 19:23:25.415616 INFO: [APUAPC] D12_APC_2: 0x3fffff
10066 19:23:25.419444 INFO: [APUAPC] D12_APC_3: 0x0
10067 19:23:25.422551 INFO: [APUAPC] D13_APC_0: 0xffffffff
10068 19:23:25.425570 INFO: [APUAPC] D13_APC_1: 0xffffffff
10069 19:23:25.429221 INFO: [APUAPC] D13_APC_2: 0x3fffff
10070 19:23:25.432198 INFO: [APUAPC] D13_APC_3: 0x0
10071 19:23:25.435248 INFO: [APUAPC] D14_APC_0: 0xffffffff
10072 19:23:25.438732 INFO: [APUAPC] D14_APC_1: 0xffffffff
10073 19:23:25.442299 INFO: [APUAPC] D14_APC_2: 0x3fffff
10074 19:23:25.445312 INFO: [APUAPC] D14_APC_3: 0x0
10075 19:23:25.448667 INFO: [APUAPC] D15_APC_0: 0xffffffff
10076 19:23:25.451756 INFO: [APUAPC] D15_APC_1: 0xffffffff
10077 19:23:25.455135 INFO: [APUAPC] D15_APC_2: 0x3fffff
10078 19:23:25.458463 INFO: [APUAPC] D15_APC_3: 0x0
10079 19:23:25.462099 INFO: [APUAPC] APC_CON: 0x4
10080 19:23:25.465287 INFO: [NOCDAPC] D0_APC_0: 0x0
10081 19:23:25.468565 INFO: [NOCDAPC] D0_APC_1: 0x0
10082 19:23:25.471984 INFO: [NOCDAPC] D1_APC_0: 0x0
10083 19:23:25.472064 INFO: [NOCDAPC] D1_APC_1: 0xfff
10084 19:23:25.475216 INFO: [NOCDAPC] D2_APC_0: 0x0
10085 19:23:25.478587 INFO: [NOCDAPC] D2_APC_1: 0xfff
10086 19:23:25.481847 INFO: [NOCDAPC] D3_APC_0: 0x0
10087 19:23:25.485260 INFO: [NOCDAPC] D3_APC_1: 0xfff
10088 19:23:25.488308 INFO: [NOCDAPC] D4_APC_0: 0x0
10089 19:23:25.491580 INFO: [NOCDAPC] D4_APC_1: 0xfff
10090 19:23:25.494919 INFO: [NOCDAPC] D5_APC_0: 0x0
10091 19:23:25.498214 INFO: [NOCDAPC] D5_APC_1: 0xfff
10092 19:23:25.501633 INFO: [NOCDAPC] D6_APC_0: 0x0
10093 19:23:25.504998 INFO: [NOCDAPC] D6_APC_1: 0xfff
10094 19:23:25.508243 INFO: [NOCDAPC] D7_APC_0: 0x0
10095 19:23:25.508323 INFO: [NOCDAPC] D7_APC_1: 0xfff
10096 19:23:25.511304 INFO: [NOCDAPC] D8_APC_0: 0x0
10097 19:23:25.514615 INFO: [NOCDAPC] D8_APC_1: 0xfff
10098 19:23:25.517650 INFO: [NOCDAPC] D9_APC_0: 0x0
10099 19:23:25.521448 INFO: [NOCDAPC] D9_APC_1: 0xfff
10100 19:23:25.524740 INFO: [NOCDAPC] D10_APC_0: 0x0
10101 19:23:25.527700 INFO: [NOCDAPC] D10_APC_1: 0xfff
10102 19:23:25.531342 INFO: [NOCDAPC] D11_APC_0: 0x0
10103 19:23:25.534396 INFO: [NOCDAPC] D11_APC_1: 0xfff
10104 19:23:25.538189 INFO: [NOCDAPC] D12_APC_0: 0x0
10105 19:23:25.541386 INFO: [NOCDAPC] D12_APC_1: 0xfff
10106 19:23:25.544608 INFO: [NOCDAPC] D13_APC_0: 0x0
10107 19:23:25.547489 INFO: [NOCDAPC] D13_APC_1: 0xfff
10108 19:23:25.550978 INFO: [NOCDAPC] D14_APC_0: 0x0
10109 19:23:25.553891 INFO: [NOCDAPC] D14_APC_1: 0xfff
10110 19:23:25.553972 INFO: [NOCDAPC] D15_APC_0: 0x0
10111 19:23:25.557437 INFO: [NOCDAPC] D15_APC_1: 0xfff
10112 19:23:25.560581 INFO: [NOCDAPC] APC_CON: 0x4
10113 19:23:25.563960 INFO: [APUAPC] set_apusys_apc done
10114 19:23:25.567211 INFO: [DEVAPC] devapc_init done
10115 19:23:25.574110 INFO: GICv3 without legacy support detected.
10116 19:23:25.577397 INFO: ARM GICv3 driver initialized in EL3
10117 19:23:25.580678 INFO: Maximum SPI INTID supported: 639
10118 19:23:25.583996 INFO: BL31: Initializing runtime services
10119 19:23:25.590542 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10120 19:23:25.593780 INFO: SPM: enable CPC mode
10121 19:23:25.597032 INFO: mcdi ready for mcusys-off-idle and system suspend
10122 19:23:25.603764 INFO: BL31: Preparing for EL3 exit to normal world
10123 19:23:25.607131 INFO: Entry point address = 0x80000000
10124 19:23:25.607210 INFO: SPSR = 0x8
10125 19:23:25.613617
10126 19:23:25.613696
10127 19:23:25.613760
10128 19:23:25.616952 Starting depthcharge on Spherion...
10129 19:23:25.617031
10130 19:23:25.617094 Wipe memory regions:
10131 19:23:25.617152
10132 19:23:25.617798 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10133 19:23:25.617894 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10134 19:23:25.617974 Setting prompt string to ['asurada:']
10135 19:23:25.618054 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10136 19:23:25.620131 [0x00000040000000, 0x00000054600000)
10137 19:23:25.742521
10138 19:23:25.742648 [0x00000054660000, 0x00000080000000)
10139 19:23:26.003361
10140 19:23:26.003846 [0x000000821a7280, 0x000000ffe64000)
10141 19:23:26.748752
10142 19:23:26.749253 [0x00000100000000, 0x00000240000000)
10143 19:23:28.638955
10144 19:23:28.642644 Initializing XHCI USB controller at 0x11200000.
10145 19:23:29.680175
10146 19:23:29.683573 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10147 19:23:29.683656
10148 19:23:29.683719
10149 19:23:29.683778
10150 19:23:29.684056 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10152 19:23:29.784355 asurada: tftpboot 192.168.201.1 13420329/tftp-deploy-yatqcpq2/kernel/image.itb 13420329/tftp-deploy-yatqcpq2/kernel/cmdline
10153 19:23:29.784518 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10154 19:23:29.784632 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10155 19:23:29.789147 tftpboot 192.168.201.1 13420329/tftp-deploy-yatqcpq2/kernel/image.ittp-deploy-yatqcpq2/kernel/cmdline
10156 19:23:29.789261
10157 19:23:29.789382 Waiting for link
10158 19:23:29.947708
10159 19:23:29.948510 R8152: Initializing
10160 19:23:29.948906
10161 19:23:29.951035 Version 6 (ocp_data = 5c30)
10162 19:23:29.951451
10163 19:23:29.954041 R8152: Done initializing
10164 19:23:29.954472
10165 19:23:29.954799 Adding net device
10166 19:23:31.854385
10167 19:23:31.855047 done.
10168 19:23:31.855578
10169 19:23:31.856063 MAC: 00:e0:4c:68:02:81
10170 19:23:31.856588
10171 19:23:31.857454 Sending DHCP discover... done.
10172 19:23:31.857797
10173 19:23:35.195279 Waiting for reply... done.
10174 19:23:35.195798
10175 19:23:35.196211 Sending DHCP request... done.
10176 19:23:35.198541
10177 19:23:35.198970 Waiting for reply... done.
10178 19:23:35.201825
10179 19:23:35.202248 My ip is 192.168.201.14
10180 19:23:35.202628
10181 19:23:35.204972 The DHCP server ip is 192.168.201.1
10182 19:23:35.205472
10183 19:23:35.208350 TFTP server IP predefined by user: 192.168.201.1
10184 19:23:35.208766
10185 19:23:35.214894 Bootfile predefined by user: 13420329/tftp-deploy-yatqcpq2/kernel/image.itb
10186 19:23:35.215327
10187 19:23:35.218171 Sending tftp read request... done.
10188 19:23:35.218657
10189 19:23:35.226592 Waiting for the transfer...
10190 19:23:35.227214
10191 19:23:35.849180 00000000 ################################################################
10192 19:23:35.849892
10193 19:23:36.456415 00080000 ################################################################
10194 19:23:36.456574
10195 19:23:37.021589 00100000 ################################################################
10196 19:23:37.021753
10197 19:23:37.619155 00180000 ################################################################
10198 19:23:37.619307
10199 19:23:38.199395 00200000 ################################################################
10200 19:23:38.199551
10201 19:23:38.812274 00280000 ################################################################
10202 19:23:38.812469
10203 19:23:39.412018 00300000 ################################################################
10204 19:23:39.412154
10205 19:23:40.004728 00380000 ################################################################
10206 19:23:40.004876
10207 19:23:40.568184 00400000 ################################################################
10208 19:23:40.568336
10209 19:23:41.156398 00480000 ################################################################
10210 19:23:41.156547
10211 19:23:41.721172 00500000 ################################################################
10212 19:23:41.721362
10213 19:23:42.310157 00580000 ################################################################
10214 19:23:42.310319
10215 19:23:42.866068 00600000 ################################################################
10216 19:23:42.866272
10217 19:23:43.441217 00680000 ################################################################
10218 19:23:43.441399
10219 19:23:43.996827 00700000 ################################################################
10220 19:23:43.996965
10221 19:23:44.601816 00780000 ################################################################
10222 19:23:44.602308
10223 19:23:45.275387 00800000 ################################################################
10224 19:23:45.275901
10225 19:23:45.902993 00880000 ################################################################
10226 19:23:45.903135
10227 19:23:46.554542 00900000 ################################################################
10228 19:23:46.555197
10229 19:23:47.238884 00980000 ################################################################
10230 19:23:47.239406
10231 19:23:47.860291 00a00000 ################################################################
10232 19:23:47.860449
10233 19:23:48.438968 00a80000 ################################################################
10234 19:23:48.439152
10235 19:23:49.052637 00b00000 ################################################################
10236 19:23:49.052791
10237 19:23:49.702687 00b80000 ################################################################
10238 19:23:49.702860
10239 19:23:50.355583 00c00000 ################################################################
10240 19:23:50.355750
10241 19:23:50.936964 00c80000 ################################################################
10242 19:23:50.937122
10243 19:23:51.504107 00d00000 ################################################################
10244 19:23:51.504244
10245 19:23:52.068696 00d80000 ################################################################
10246 19:23:52.068840
10247 19:23:52.635127 00e00000 ################################################################
10248 19:23:52.635290
10249 19:23:53.182848 00e80000 ################################################################
10250 19:23:53.183001
10251 19:23:53.720763 00f00000 ################################################################
10252 19:23:53.720924
10253 19:23:54.264916 00f80000 ################################################################
10254 19:23:54.265089
10255 19:23:54.821502 01000000 ################################################################
10256 19:23:54.821653
10257 19:23:55.431689 01080000 ################################################################
10258 19:23:55.431825
10259 19:23:56.032675 01100000 ################################################################
10260 19:23:56.032813
10261 19:23:56.592759 01180000 ################################################################
10262 19:23:56.592900
10263 19:23:57.172469 01200000 ################################################################
10264 19:23:57.172614
10265 19:23:57.746153 01280000 ################################################################
10266 19:23:57.746304
10267 19:23:58.352291 01300000 ################################################################
10268 19:23:58.352466
10269 19:23:58.914514 01380000 ################################################################
10270 19:23:58.914680
10271 19:23:59.480340 01400000 ################################################################
10272 19:23:59.480512
10273 19:24:00.025685 01480000 ################################################################
10274 19:24:00.025849
10275 19:24:00.581733 01500000 ################################################################
10276 19:24:00.581868
10277 19:24:01.143126 01580000 ################################################################
10278 19:24:01.143283
10279 19:24:01.702879 01600000 ################################################################
10280 19:24:01.703052
10281 19:24:02.244469 01680000 ################################################################
10282 19:24:02.244615
10283 19:24:02.797989 01700000 ################################################################
10284 19:24:02.798146
10285 19:24:03.349586 01780000 ################################################################
10286 19:24:03.349841
10287 19:24:03.913517 01800000 ################################################################
10288 19:24:03.913686
10289 19:24:04.538057 01880000 ################################################################
10290 19:24:04.538622
10291 19:24:05.086402 01900000 ################################################################
10292 19:24:05.086534
10293 19:24:05.623268 01980000 ################################################################
10294 19:24:05.623400
10295 19:24:06.284651 01a00000 ################################################################
10296 19:24:06.284816
10297 19:24:06.942067 01a80000 ################################################################
10298 19:24:06.942204
10299 19:24:07.537603 01b00000 ################################################################
10300 19:24:07.537749
10301 19:24:08.098380 01b80000 ################################################################
10302 19:24:08.098514
10303 19:24:08.669447 01c00000 ################################################################
10304 19:24:08.669591
10305 19:24:09.332038 01c80000 ################################################################
10306 19:24:09.332213
10307 19:24:09.979999 01d00000 ################################################################
10308 19:24:09.980149
10309 19:24:10.546975 01d80000 ################################################################
10310 19:24:10.547112
10311 19:24:10.842332 01e00000 ################################### done.
10312 19:24:10.842493
10313 19:24:10.845608 The bootfile was 31737910 bytes long.
10314 19:24:10.845690
10315 19:24:10.848805 Sending tftp read request... done.
10316 19:24:10.848888
10317 19:24:10.852369 Waiting for the transfer...
10318 19:24:10.852451
10319 19:24:10.855507 00000000 # done.
10320 19:24:10.855592
10321 19:24:10.862309 Command line loaded dynamically from TFTP file: 13420329/tftp-deploy-yatqcpq2/kernel/cmdline
10322 19:24:10.862397
10323 19:24:10.885143 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/13420329/extract-nfsrootfs-l3_d7ahj,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10324 19:24:10.885296
10325 19:24:10.885390 Loading FIT.
10326 19:24:10.885451
10327 19:24:10.888573 Image ramdisk-1 has 18778291 bytes.
10328 19:24:10.888655
10329 19:24:10.891448 Image fdt-1 has 47230 bytes.
10330 19:24:10.891528
10331 19:24:10.894752 Image kernel-1 has 12910355 bytes.
10332 19:24:10.894833
10333 19:24:10.901734 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10334 19:24:10.905162
10335 19:24:10.921782 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10336 19:24:10.921928
10337 19:24:10.924746 Choosing best match conf-1 for compat google,spherion-rev2.
10338 19:24:10.929729
10339 19:24:10.934418 Connected to device vid:did:rid of 1ae0:0028:00
10340 19:24:10.941088
10341 19:24:10.944799 tpm_get_response: command 0x17b, return code 0x0
10342 19:24:10.944885
10343 19:24:10.948254 ec_init: CrosEC protocol v3 supported (256, 248)
10344 19:24:10.952262
10345 19:24:10.955305 tpm_cleanup: add release locality here.
10346 19:24:10.955387
10347 19:24:10.955451 Shutting down all USB controllers.
10348 19:24:10.958350
10349 19:24:10.958430 Removing current net device
10350 19:24:10.958493
10351 19:24:10.965504 Exiting depthcharge with code 4 at timestamp: 74781146
10352 19:24:10.965593
10353 19:24:10.968613 LZMA decompressing kernel-1 to 0x821a6718
10354 19:24:10.968694
10355 19:24:10.971910 LZMA decompressing kernel-1 to 0x40000000
10356 19:24:12.567228
10357 19:24:12.567737 jumping to kernel
10358 19:24:12.569454 end: 2.2.4 bootloader-commands (duration 00:00:47) [common]
10359 19:24:12.569948 start: 2.2.5 auto-login-action (timeout 00:03:38) [common]
10360 19:24:12.570361 Setting prompt string to ['Linux version [0-9]']
10361 19:24:12.570702 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10362 19:24:12.571042 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10363 19:24:12.649231
10364 19:24:12.652383 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10365 19:24:12.656216 start: 2.2.5.1 login-action (timeout 00:03:38) [common]
10366 19:24:12.656678 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10367 19:24:12.657031 Setting prompt string to []
10368 19:24:12.657442 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10369 19:24:12.657798 Using line separator: #'\n'#
10370 19:24:12.658123 No login prompt set.
10371 19:24:12.658433 Parsing kernel messages
10372 19:24:12.658713 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10373 19:24:12.659221 [login-action] Waiting for messages, (timeout 00:03:38)
10374 19:24:12.659541 Waiting using forced prompt support (timeout 00:01:49)
10375 19:24:12.675400 [ 0.000000] Linux version 6.1.86-cip19 (KernelCI@build-j170728-arm64-gcc-10-defconfig-arm64-chromebook-wrkxq) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Apr 18 19:05:54 UTC 2024
10376 19:24:12.678721 [ 0.000000] random: crng init done
10377 19:24:12.685217 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10378 19:24:12.688457 [ 0.000000] efi: UEFI not found.
10379 19:24:12.695382 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10380 19:24:12.705312 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10381 19:24:12.714989 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10382 19:24:12.721766 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10383 19:24:12.728197 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10384 19:24:12.734679 [ 0.000000] printk: bootconsole [mtk8250] enabled
10385 19:24:12.741301 [ 0.000000] NUMA: No NUMA configuration found
10386 19:24:12.748187 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10387 19:24:12.754723 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10388 19:24:12.755170 [ 0.000000] Zone ranges:
10389 19:24:12.760822 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10390 19:24:12.764062 [ 0.000000] DMA32 empty
10391 19:24:12.770618 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10392 19:24:12.774390 [ 0.000000] Movable zone start for each node
10393 19:24:12.777568 [ 0.000000] Early memory node ranges
10394 19:24:12.783996 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10395 19:24:12.791006 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10396 19:24:12.797472 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10397 19:24:12.803925 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10398 19:24:12.810119 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10399 19:24:12.816554 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10400 19:24:12.873848 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10401 19:24:12.880203 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10402 19:24:12.887608 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10403 19:24:12.890342 [ 0.000000] psci: probing for conduit method from DT.
10404 19:24:12.897245 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10405 19:24:12.900148 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10406 19:24:12.906534 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10407 19:24:12.910227 [ 0.000000] psci: SMC Calling Convention v1.2
10408 19:24:12.916732 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10409 19:24:12.919806 [ 0.000000] Detected VIPT I-cache on CPU0
10410 19:24:12.926158 [ 0.000000] CPU features: detected: GIC system register CPU interface
10411 19:24:12.933447 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10412 19:24:12.939839 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10413 19:24:12.946285 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10414 19:24:12.956288 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10415 19:24:12.963081 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10416 19:24:12.966167 [ 0.000000] alternatives: applying boot alternatives
10417 19:24:12.972582 [ 0.000000] Fallback order for Node 0: 0
10418 19:24:12.978923 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10419 19:24:12.982544 [ 0.000000] Policy zone: Normal
10420 19:24:13.005326 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/13420329/extract-nfsrootfs-l3_d7ahj,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10421 19:24:13.015104 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10422 19:24:13.026310 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10423 19:24:13.036177 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10424 19:24:13.043376 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10425 19:24:13.046471 <6>[ 0.000000] software IO TLB: area num 8.
10426 19:24:13.103136 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10427 19:24:13.251972 <6>[ 0.000000] Memory: 7946232K/8385536K available (18048K kernel code, 4118K rwdata, 22288K rodata, 8448K init, 616K bss, 406536K reserved, 32768K cma-reserved)
10428 19:24:13.258402 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10429 19:24:13.265451 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10430 19:24:13.268659 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10431 19:24:13.274726 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10432 19:24:13.281177 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10433 19:24:13.284457 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10434 19:24:13.294792 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10435 19:24:13.300871 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10436 19:24:13.307757 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10437 19:24:13.313943 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10438 19:24:13.317622 <6>[ 0.000000] GICv3: 608 SPIs implemented
10439 19:24:13.320525 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10440 19:24:13.327540 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10441 19:24:13.330372 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10442 19:24:13.337351 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10443 19:24:13.349971 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10444 19:24:13.363246 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10445 19:24:13.369624 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10446 19:24:13.378416 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10447 19:24:13.392079 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10448 19:24:13.398391 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10449 19:24:13.404917 <6>[ 0.009178] Console: colour dummy device 80x25
10450 19:24:13.414651 <6>[ 0.013935] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10451 19:24:13.421217 <6>[ 0.024377] pid_max: default: 32768 minimum: 301
10452 19:24:13.424348 <6>[ 0.029249] LSM: Security Framework initializing
10453 19:24:13.431146 <6>[ 0.034186] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10454 19:24:13.441607 <6>[ 0.041969] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10455 19:24:13.451260 <6>[ 0.051385] cblist_init_generic: Setting adjustable number of callback queues.
10456 19:24:13.458010 <6>[ 0.058824] cblist_init_generic: Setting shift to 3 and lim to 1.
10457 19:24:13.464494 <6>[ 0.065161] cblist_init_generic: Setting adjustable number of callback queues.
10458 19:24:13.470719 <6>[ 0.072588] cblist_init_generic: Setting shift to 3 and lim to 1.
10459 19:24:13.474066 <6>[ 0.078988] rcu: Hierarchical SRCU implementation.
10460 19:24:13.480836 <6>[ 0.084003] rcu: Max phase no-delay instances is 1000.
10461 19:24:13.487576 <6>[ 0.091030] EFI services will not be available.
10462 19:24:13.491542 <6>[ 0.095989] smp: Bringing up secondary CPUs ...
10463 19:24:13.499555 <6>[ 0.101034] Detected VIPT I-cache on CPU1
10464 19:24:13.506252 <6>[ 0.101102] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10465 19:24:13.512614 <6>[ 0.101135] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10466 19:24:13.516208 <6>[ 0.101472] Detected VIPT I-cache on CPU2
10467 19:24:13.525914 <6>[ 0.101525] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10468 19:24:13.532532 <6>[ 0.101543] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10469 19:24:13.535551 <6>[ 0.101803] Detected VIPT I-cache on CPU3
10470 19:24:13.541972 <6>[ 0.101852] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10471 19:24:13.548807 <6>[ 0.101866] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10472 19:24:13.554968 <6>[ 0.102170] CPU features: detected: Spectre-v4
10473 19:24:13.558294 <6>[ 0.102176] CPU features: detected: Spectre-BHB
10474 19:24:13.562125 <6>[ 0.102181] Detected PIPT I-cache on CPU4
10475 19:24:13.571554 <6>[ 0.102239] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10476 19:24:13.578234 <6>[ 0.102255] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10477 19:24:13.581305 <6>[ 0.102547] Detected PIPT I-cache on CPU5
10478 19:24:13.588480 <6>[ 0.102609] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10479 19:24:13.595258 <6>[ 0.102625] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10480 19:24:13.597939 <6>[ 0.102904] Detected PIPT I-cache on CPU6
10481 19:24:13.608019 <6>[ 0.102967] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10482 19:24:13.614503 <6>[ 0.102983] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10483 19:24:13.617495 <6>[ 0.103278] Detected PIPT I-cache on CPU7
10484 19:24:13.623999 <6>[ 0.103342] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10485 19:24:13.630441 <6>[ 0.103358] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10486 19:24:13.637178 <6>[ 0.103404] smp: Brought up 1 node, 8 CPUs
10487 19:24:13.640842 <6>[ 0.244739] SMP: Total of 8 processors activated.
10488 19:24:13.647079 <6>[ 0.249660] CPU features: detected: 32-bit EL0 Support
10489 19:24:13.653684 <6>[ 0.255024] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10490 19:24:13.660249 <6>[ 0.263824] CPU features: detected: Common not Private translations
10491 19:24:13.666773 <6>[ 0.270300] CPU features: detected: CRC32 instructions
10492 19:24:13.673307 <6>[ 0.275652] CPU features: detected: RCpc load-acquire (LDAPR)
10493 19:24:13.679903 <6>[ 0.281612] CPU features: detected: LSE atomic instructions
10494 19:24:13.683198 <6>[ 0.287394] CPU features: detected: Privileged Access Never
10495 19:24:13.689901 <6>[ 0.293173] CPU features: detected: RAS Extension Support
10496 19:24:13.696666 <6>[ 0.298782] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10497 19:24:13.700065 <6>[ 0.306004] CPU: All CPU(s) started at EL2
10498 19:24:13.706385 <6>[ 0.310320] alternatives: applying system-wide alternatives
10499 19:24:13.716889 <6>[ 0.321135] devtmpfs: initialized
10500 19:24:13.732711 <6>[ 0.330090] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10501 19:24:13.739232 <6>[ 0.340056] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10502 19:24:13.745792 <6>[ 0.348287] pinctrl core: initialized pinctrl subsystem
10503 19:24:13.749047 <6>[ 0.354929] DMI not present or invalid.
10504 19:24:13.755786 <6>[ 0.359341] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10505 19:24:13.765607 <6>[ 0.366239] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10506 19:24:13.772425 <6>[ 0.373830] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10507 19:24:13.782112 <6>[ 0.382065] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10508 19:24:13.785216 <6>[ 0.390302] audit: initializing netlink subsys (disabled)
10509 19:24:13.795640 <5>[ 0.395993] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10510 19:24:13.801713 <6>[ 0.396693] thermal_sys: Registered thermal governor 'step_wise'
10511 19:24:13.808351 <6>[ 0.403956] thermal_sys: Registered thermal governor 'power_allocator'
10512 19:24:13.812247 <6>[ 0.410211] cpuidle: using governor menu
10513 19:24:13.818127 <6>[ 0.421170] NET: Registered PF_QIPCRTR protocol family
10514 19:24:13.825025 <6>[ 0.426667] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10515 19:24:13.831522 <6>[ 0.433770] ASID allocator initialised with 32768 entries
10516 19:24:13.834769 <6>[ 0.440334] Serial: AMBA PL011 UART driver
10517 19:24:13.845120 <4>[ 0.449057] Trying to register duplicate clock ID: 134
10518 19:24:13.901433 <6>[ 0.508634] KASLR enabled
10519 19:24:13.915885 <6>[ 0.516370] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10520 19:24:13.922380 <6>[ 0.523381] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10521 19:24:13.928662 <6>[ 0.529867] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10522 19:24:13.935055 <6>[ 0.536874] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10523 19:24:13.941662 <6>[ 0.543363] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10524 19:24:13.948777 <6>[ 0.550364] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10525 19:24:13.955098 <6>[ 0.556847] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10526 19:24:13.961439 <6>[ 0.563848] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10527 19:24:13.965055 <6>[ 0.571370] ACPI: Interpreter disabled.
10528 19:24:13.973871 <6>[ 0.577776] iommu: Default domain type: Translated
10529 19:24:13.980212 <6>[ 0.582889] iommu: DMA domain TLB invalidation policy: strict mode
10530 19:24:13.983885 <5>[ 0.589551] SCSI subsystem initialized
10531 19:24:13.989878 <6>[ 0.593729] usbcore: registered new interface driver usbfs
10532 19:24:13.996998 <6>[ 0.599464] usbcore: registered new interface driver hub
10533 19:24:14.000197 <6>[ 0.605015] usbcore: registered new device driver usb
10534 19:24:14.007010 <6>[ 0.611110] pps_core: LinuxPPS API ver. 1 registered
10535 19:24:14.017262 <6>[ 0.616304] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10536 19:24:14.020535 <6>[ 0.625646] PTP clock support registered
10537 19:24:14.023555 <6>[ 0.629888] EDAC MC: Ver: 3.0.0
10538 19:24:14.030835 <6>[ 0.635024] FPGA manager framework
10539 19:24:14.037416 <6>[ 0.638707] Advanced Linux Sound Architecture Driver Initialized.
10540 19:24:14.040681 <6>[ 0.645454] vgaarb: loaded
10541 19:24:14.047754 <6>[ 0.648646] clocksource: Switched to clocksource arch_sys_counter
10542 19:24:14.051106 <5>[ 0.655094] VFS: Disk quotas dquot_6.6.0
10543 19:24:14.057558 <6>[ 0.659282] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10544 19:24:14.060926 <6>[ 0.666472] pnp: PnP ACPI: disabled
10545 19:24:14.069159 <6>[ 0.673157] NET: Registered PF_INET protocol family
10546 19:24:14.078607 <6>[ 0.678685] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10547 19:24:14.090279 <6>[ 0.691012] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10548 19:24:14.099932 <6>[ 0.699828] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10549 19:24:14.106874 <6>[ 0.707799] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10550 19:24:14.116347 <6>[ 0.716502] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10551 19:24:14.123052 <6>[ 0.726259] TCP: Hash tables configured (established 65536 bind 65536)
10552 19:24:14.129141 <6>[ 0.733118] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10553 19:24:14.139059 <6>[ 0.740317] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10554 19:24:14.145831 <6>[ 0.748021] NET: Registered PF_UNIX/PF_LOCAL protocol family
10555 19:24:14.152307 <6>[ 0.754175] RPC: Registered named UNIX socket transport module.
10556 19:24:14.155520 <6>[ 0.760331] RPC: Registered udp transport module.
10557 19:24:14.162568 <6>[ 0.765263] RPC: Registered tcp transport module.
10558 19:24:14.168946 <6>[ 0.770191] RPC: Registered tcp NFSv4.1 backchannel transport module.
10559 19:24:14.172221 <6>[ 0.776856] PCI: CLS 0 bytes, default 64
10560 19:24:14.175327 <6>[ 0.781199] Unpacking initramfs...
10561 19:24:14.199468 <6>[ 0.800769] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10562 19:24:14.209449 <6>[ 0.809445] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10563 19:24:14.212997 <6>[ 0.818292] kvm [1]: IPA Size Limit: 40 bits
10564 19:24:14.219498 <6>[ 0.822821] kvm [1]: GICv3: no GICV resource entry
10565 19:24:14.222692 <6>[ 0.827841] kvm [1]: disabling GICv2 emulation
10566 19:24:14.229455 <6>[ 0.832527] kvm [1]: GIC system register CPU interface enabled
10567 19:24:14.232615 <6>[ 0.838691] kvm [1]: vgic interrupt IRQ18
10568 19:24:14.239049 <6>[ 0.843053] kvm [1]: VHE mode initialized successfully
10569 19:24:14.246009 <5>[ 0.849487] Initialise system trusted keyrings
10570 19:24:14.252458 <6>[ 0.854325] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10571 19:24:14.259474 <6>[ 0.864292] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10572 19:24:14.266407 <5>[ 0.870693] NFS: Registering the id_resolver key type
10573 19:24:14.269617 <5>[ 0.875995] Key type id_resolver registered
10574 19:24:14.276124 <5>[ 0.880412] Key type id_legacy registered
10575 19:24:14.282450 <6>[ 0.884692] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10576 19:24:14.288892 <6>[ 0.891614] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10577 19:24:14.295488 <6>[ 0.899325] 9p: Installing v9fs 9p2000 file system support
10578 19:24:14.332152 <5>[ 0.936692] Key type asymmetric registered
10579 19:24:14.335670 <5>[ 0.941036] Asymmetric key parser 'x509' registered
10580 19:24:14.345752 <6>[ 0.946194] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10581 19:24:14.348973 <6>[ 0.953813] io scheduler mq-deadline registered
10582 19:24:14.352171 <6>[ 0.958573] io scheduler kyber registered
10583 19:24:14.370722 <6>[ 0.975417] EINJ: ACPI disabled.
10584 19:24:14.403166 <4>[ 1.000907] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10585 19:24:14.412953 <4>[ 1.011530] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10586 19:24:14.427507 <6>[ 1.032121] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10587 19:24:14.435315 <6>[ 1.040010] printk: console [ttyS0] disabled
10588 19:24:14.463369 <6>[ 1.064655] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10589 19:24:14.470405 <6>[ 1.074122] printk: console [ttyS0] enabled
10590 19:24:14.473659 <6>[ 1.074122] printk: console [ttyS0] enabled
10591 19:24:14.480419 <6>[ 1.083015] printk: bootconsole [mtk8250] disabled
10592 19:24:14.483452 <6>[ 1.083015] printk: bootconsole [mtk8250] disabled
10593 19:24:14.490044 <6>[ 1.094058] SuperH (H)SCI(F) driver initialized
10594 19:24:14.493263 <6>[ 1.099355] msm_serial: driver initialized
10595 19:24:14.507338 <6>[ 1.108289] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10596 19:24:14.516882 <6>[ 1.116839] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10597 19:24:14.523562 <6>[ 1.125383] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10598 19:24:14.533605 <6>[ 1.134010] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10599 19:24:14.543829 <6>[ 1.142716] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10600 19:24:14.549776 <6>[ 1.151435] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10601 19:24:14.559594 <6>[ 1.159975] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10602 19:24:14.566622 <6>[ 1.168773] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10603 19:24:14.576230 <6>[ 1.177314] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10604 19:24:14.588037 <6>[ 1.192885] loop: module loaded
10605 19:24:14.594881 <6>[ 1.198768] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10606 19:24:14.617748 <4>[ 1.222049] mtk-pmic-keys: Failed to locate of_node [id: -1]
10607 19:24:14.624566 <6>[ 1.228891] megasas: 07.719.03.00-rc1
10608 19:24:14.634000 <6>[ 1.238520] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10609 19:24:14.643429 <6>[ 1.248019] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10610 19:24:14.660214 <6>[ 1.264422] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10611 19:24:14.718972 <6>[ 1.317129] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10612 19:24:14.972081 <6>[ 1.575937] Freeing initrd memory: 18336K
10613 19:24:14.983804 <6>[ 1.587471] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10614 19:24:14.994257 <6>[ 1.598602] tun: Universal TUN/TAP device driver, 1.6
10615 19:24:14.997969 <6>[ 1.604680] thunder_xcv, ver 1.0
10616 19:24:15.001314 <6>[ 1.608177] thunder_bgx, ver 1.0
10617 19:24:15.004408 <6>[ 1.611682] nicpf, ver 1.0
10618 19:24:15.014862 <6>[ 1.615709] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10619 19:24:15.018821 <6>[ 1.623186] hns3: Copyright (c) 2017 Huawei Corporation.
10620 19:24:15.021938 <6>[ 1.628778] hclge is initializing
10621 19:24:15.028187 <6>[ 1.632356] e1000: Intel(R) PRO/1000 Network Driver
10622 19:24:15.035299 <6>[ 1.637486] e1000: Copyright (c) 1999-2006 Intel Corporation.
10623 19:24:15.038138 <6>[ 1.643499] e1000e: Intel(R) PRO/1000 Network Driver
10624 19:24:15.045182 <6>[ 1.648714] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10625 19:24:15.051470 <6>[ 1.654899] igb: Intel(R) Gigabit Ethernet Network Driver
10626 19:24:15.058286 <6>[ 1.660549] igb: Copyright (c) 2007-2014 Intel Corporation.
10627 19:24:15.064854 <6>[ 1.666386] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10628 19:24:15.071264 <6>[ 1.672903] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10629 19:24:15.074480 <6>[ 1.679367] sky2: driver version 1.30
10630 19:24:15.080672 <6>[ 1.684355] VFIO - User Level meta-driver version: 0.3
10631 19:24:15.088529 <6>[ 1.692566] usbcore: registered new interface driver usb-storage
10632 19:24:15.094848 <6>[ 1.699014] usbcore: registered new device driver onboard-usb-hub
10633 19:24:15.103819 <6>[ 1.708201] mt6397-rtc mt6359-rtc: registered as rtc0
10634 19:24:15.114232 <6>[ 1.713666] mt6397-rtc mt6359-rtc: setting system clock to 2024-04-18T19:24:15 UTC (1713468255)
10635 19:24:15.117401 <6>[ 1.723240] i2c_dev: i2c /dev entries driver
10636 19:24:15.134103 <6>[ 1.735069] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10637 19:24:15.140558 <4>[ 1.743798] cpu cpu0: supply cpu not found, using dummy regulator
10638 19:24:15.147566 <4>[ 1.750218] cpu cpu1: supply cpu not found, using dummy regulator
10639 19:24:15.153878 <4>[ 1.756628] cpu cpu2: supply cpu not found, using dummy regulator
10640 19:24:15.160561 <4>[ 1.763042] cpu cpu3: supply cpu not found, using dummy regulator
10641 19:24:15.167331 <4>[ 1.769439] cpu cpu4: supply cpu not found, using dummy regulator
10642 19:24:15.173729 <4>[ 1.775838] cpu cpu5: supply cpu not found, using dummy regulator
10643 19:24:15.180532 <4>[ 1.782237] cpu cpu6: supply cpu not found, using dummy regulator
10644 19:24:15.187060 <4>[ 1.788639] cpu cpu7: supply cpu not found, using dummy regulator
10645 19:24:15.205037 <6>[ 1.809283] cpu cpu0: EM: created perf domain
10646 19:24:15.208152 <6>[ 1.814200] cpu cpu4: EM: created perf domain
10647 19:24:15.215580 <6>[ 1.819835] sdhci: Secure Digital Host Controller Interface driver
10648 19:24:15.222166 <6>[ 1.826267] sdhci: Copyright(c) Pierre Ossman
10649 19:24:15.228952 <6>[ 1.831226] Synopsys Designware Multimedia Card Interface Driver
10650 19:24:15.235260 <6>[ 1.837862] sdhci-pltfm: SDHCI platform and OF driver helper
10651 19:24:15.238673 <6>[ 1.837927] mmc0: CQHCI version 5.10
10652 19:24:15.245153 <6>[ 1.847886] ledtrig-cpu: registered to indicate activity on CPUs
10653 19:24:15.252163 <6>[ 1.854833] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10654 19:24:15.258684 <6>[ 1.861881] usbcore: registered new interface driver usbhid
10655 19:24:15.261770 <6>[ 1.867706] usbhid: USB HID core driver
10656 19:24:15.268847 <6>[ 1.871930] spi_master spi0: will run message pump with realtime priority
10657 19:24:15.310578 <6>[ 1.908404] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10658 19:24:15.329183 <6>[ 1.923321] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10659 19:24:15.335924 <6>[ 1.939202] cros-ec-spi spi0.0: Chrome EC device registered
10660 19:24:15.339401 <6>[ 1.945257] mmc0: Command Queue Engine enabled
10661 19:24:15.346577 <6>[ 1.950009] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10662 19:24:15.353809 <6>[ 1.957716] mmcblk0: mmc0:0001 DA4128 116 GiB
10663 19:24:15.363310 <6>[ 1.967820] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10664 19:24:15.373224 <6>[ 1.972356] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10665 19:24:15.380017 <6>[ 1.975022] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10666 19:24:15.383634 <6>[ 1.984253] NET: Registered PF_PACKET protocol family
10667 19:24:15.389981 <6>[ 1.988935] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10668 19:24:15.393127 <6>[ 1.993667] 9pnet: Installing 9P2000 support
10669 19:24:15.400130 <6>[ 1.999468] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10670 19:24:15.406790 <5>[ 2.003336] Key type dns_resolver registered
10671 19:24:15.409772 <6>[ 2.014781] registered taskstats version 1
10672 19:24:15.416151 <5>[ 2.019161] Loading compiled-in X.509 certificates
10673 19:24:15.443603 <4>[ 2.041010] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10674 19:24:15.453590 <4>[ 2.051712] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10675 19:24:15.459946 <3>[ 2.062241] debugfs: File 'uA_load' in directory '/' already present!
10676 19:24:15.466323 <3>[ 2.068997] debugfs: File 'min_uV' in directory '/' already present!
10677 19:24:15.472825 <3>[ 2.075614] debugfs: File 'max_uV' in directory '/' already present!
10678 19:24:15.479535 <3>[ 2.082226] debugfs: File 'constraint_flags' in directory '/' already present!
10679 19:24:15.490429 <3>[ 2.091798] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10680 19:24:15.500086 <6>[ 2.104318] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10681 19:24:15.506682 <6>[ 2.111122] xhci-mtk 11200000.usb: xHCI Host Controller
10682 19:24:15.513453 <6>[ 2.116621] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10683 19:24:15.523229 <6>[ 2.124489] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10684 19:24:15.530199 <6>[ 2.133915] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10685 19:24:15.536447 <6>[ 2.140008] xhci-mtk 11200000.usb: xHCI Host Controller
10686 19:24:15.543601 <6>[ 2.145488] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10687 19:24:15.550142 <6>[ 2.153139] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10688 19:24:15.556905 <6>[ 2.160884] hub 1-0:1.0: USB hub found
10689 19:24:15.559693 <6>[ 2.164901] hub 1-0:1.0: 1 port detected
10690 19:24:15.569769 <6>[ 2.169178] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10691 19:24:15.572929 <6>[ 2.177938] hub 2-0:1.0: USB hub found
10692 19:24:15.576162 <6>[ 2.181960] hub 2-0:1.0: 1 port detected
10693 19:24:15.584776 <6>[ 2.188930] mtk-msdc 11f70000.mmc: Got CD GPIO
10694 19:24:15.596568 <6>[ 2.197817] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10695 19:24:15.603044 <6>[ 2.205848] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10696 19:24:15.613461 <4>[ 2.213752] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10697 19:24:15.623428 <6>[ 2.223287] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10698 19:24:15.630015 <6>[ 2.231363] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10699 19:24:15.636511 <6>[ 2.239389] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10700 19:24:15.646307 <6>[ 2.247312] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10701 19:24:15.652868 <6>[ 2.255129] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10702 19:24:15.662963 <6>[ 2.262946] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10703 19:24:15.672666 <6>[ 2.273362] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10704 19:24:15.679270 <6>[ 2.281746] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10705 19:24:15.689593 <6>[ 2.290089] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10706 19:24:15.696176 <6>[ 2.298427] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10707 19:24:15.705514 <6>[ 2.306764] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10708 19:24:15.712520 <6>[ 2.315102] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10709 19:24:15.722188 <6>[ 2.323440] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10710 19:24:15.728653 <6>[ 2.331777] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10711 19:24:15.738866 <6>[ 2.340115] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10712 19:24:15.748521 <6>[ 2.348453] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10713 19:24:15.755603 <6>[ 2.356791] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10714 19:24:15.765036 <6>[ 2.365130] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10715 19:24:15.771527 <6>[ 2.373468] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10716 19:24:15.781461 <6>[ 2.381806] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10717 19:24:15.788205 <6>[ 2.390143] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10718 19:24:15.794597 <6>[ 2.398874] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10719 19:24:15.801574 <6>[ 2.406016] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10720 19:24:15.808040 <6>[ 2.412790] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10721 19:24:15.818144 <6>[ 2.419557] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10722 19:24:15.825012 <6>[ 2.426491] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10723 19:24:15.831640 <6>[ 2.433352] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10724 19:24:15.840950 <6>[ 2.442491] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10725 19:24:15.851423 <6>[ 2.451610] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10726 19:24:15.860977 <6>[ 2.460903] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10727 19:24:15.871118 <6>[ 2.470371] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10728 19:24:15.880850 <6>[ 2.479837] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10729 19:24:15.887602 <6>[ 2.488957] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10730 19:24:15.897202 <6>[ 2.498424] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10731 19:24:15.907137 <6>[ 2.507544] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10732 19:24:15.917267 <6>[ 2.516839] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10733 19:24:15.926935 <6>[ 2.526999] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10734 19:24:15.937007 <6>[ 2.538686] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10735 19:24:15.944144 <6>[ 2.548388] Trying to probe devices needed for running init ...
10736 19:24:15.991302 <6>[ 2.592932] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10737 19:24:16.145954 <6>[ 2.750693] hub 1-1:1.0: USB hub found
10738 19:24:16.149522 <6>[ 2.755199] hub 1-1:1.0: 4 ports detected
10739 19:24:16.159778 <6>[ 2.764101] hub 1-1:1.0: USB hub found
10740 19:24:16.163013 <6>[ 2.768471] hub 1-1:1.0: 4 ports detected
10741 19:24:16.271948 <6>[ 2.873287] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10742 19:24:16.297976 <6>[ 2.902377] hub 2-1:1.0: USB hub found
10743 19:24:16.301075 <6>[ 2.906885] hub 2-1:1.0: 3 ports detected
10744 19:24:16.310103 <6>[ 2.915048] hub 2-1:1.0: USB hub found
10745 19:24:16.313411 <6>[ 2.919532] hub 2-1:1.0: 3 ports detected
10746 19:24:16.487690 <6>[ 3.088757] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10747 19:24:16.619971 <6>[ 3.224174] hub 1-1.4:1.0: USB hub found
10748 19:24:16.623093 <6>[ 3.228773] hub 1-1.4:1.0: 2 ports detected
10749 19:24:16.632607 <6>[ 3.236870] hub 1-1.4:1.0: USB hub found
10750 19:24:16.635628 <6>[ 3.241414] hub 1-1.4:1.0: 2 ports detected
10751 19:24:16.703696 <6>[ 3.305053] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10752 19:24:16.931813 <6>[ 3.532931] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10753 19:24:17.123737 <6>[ 3.724940] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10754 19:24:28.221396 <6>[ 14.829970] ALSA device list:
10755 19:24:28.227893 <6>[ 14.833267] No soundcards found.
10756 19:24:28.235687 <6>[ 14.841216] Freeing unused kernel memory: 8448K
10757 19:24:28.238891 <6>[ 14.846755] Run /init as init process
10758 19:24:28.248465 Loading, please wait...
10759 19:24:28.274054 Starting systemd-udevd version 252.22-1~deb12u1
10760 19:24:28.274496
10761 19:24:28.531592 <6>[ 15.133849] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10762 19:24:28.540107 <6>[ 15.145618] remoteproc remoteproc0: scp is available
10763 19:24:28.549801 <6>[ 15.151774] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10764 19:24:28.552962 <6>[ 15.154274] remoteproc remoteproc0: powering up scp
10765 19:24:28.563097 <6>[ 15.160127] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10766 19:24:28.569207 <6>[ 15.164801] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10767 19:24:28.579222 <6>[ 15.173512] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10768 19:24:28.585641 <6>[ 15.181824] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10769 19:24:28.592073 <6>[ 15.194665] usbcore: registered new device driver r8152-cfgselector
10770 19:24:28.602297 <3>[ 15.205363] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10771 19:24:28.609256 <4>[ 15.210127] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10772 19:24:28.619484 <3>[ 15.213668] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10773 19:24:28.625954 <4>[ 15.227460] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10774 19:24:28.632438 <3>[ 15.228971] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10775 19:24:28.641986 <3>[ 15.231505] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10776 19:24:28.645245 <6>[ 15.232934] mc: Linux media interface: v0.10
10777 19:24:28.655300 <6>[ 15.238640] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10778 19:24:28.662073 <3>[ 15.244546] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10779 19:24:28.668655 <6>[ 15.268188] videodev: Linux video capture interface: v2.00
10780 19:24:28.674920 <3>[ 15.272845] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10781 19:24:28.685026 <3>[ 15.272852] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10782 19:24:28.691665 <3>[ 15.272856] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10783 19:24:28.701929 <3>[ 15.272912] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10784 19:24:28.708446 <4>[ 15.287758] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10785 19:24:28.714978 <4>[ 15.287758] Fallback method does not support PEC.
10786 19:24:28.721902 <3>[ 15.294813] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10787 19:24:28.728301 <6>[ 15.316193] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10788 19:24:28.738345 <3>[ 15.319497] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10789 19:24:28.744547 <6>[ 15.321777] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10790 19:24:28.751325 <3>[ 15.324559] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10791 19:24:28.761547 <3>[ 15.324561] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10792 19:24:28.768359 <3>[ 15.324600] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10793 19:24:28.778212 <6>[ 15.324984] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10794 19:24:28.785167 <6>[ 15.332662] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10795 19:24:28.794599 <3>[ 15.339506] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10796 19:24:28.801636 <3>[ 15.339509] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10797 19:24:28.808118 <6>[ 15.340228] pci_bus 0000:00: root bus resource [bus 00-ff]
10798 19:24:28.814590 <6>[ 15.340235] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10799 19:24:28.824770 <6>[ 15.340238] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10800 19:24:28.831010 <6>[ 15.340273] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10801 19:24:28.837745 <6>[ 15.340286] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10802 19:24:28.844741 <6>[ 15.340355] pci 0000:00:00.0: supports D1 D2
10803 19:24:28.850878 <6>[ 15.340357] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10804 19:24:28.858147 <6>[ 15.341314] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10805 19:24:28.867862 <6>[ 15.341488] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10806 19:24:28.874142 <6>[ 15.341586] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10807 19:24:28.881236 <6>[ 15.341613] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10808 19:24:28.887516 <6>[ 15.341633] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10809 19:24:28.894255 <6>[ 15.341649] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10810 19:24:28.900699 <6>[ 15.341765] pci 0000:01:00.0: supports D1 D2
10811 19:24:28.907159 <6>[ 15.341767] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10812 19:24:28.914225 <6>[ 15.343428] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10813 19:24:28.923765 <6>[ 15.345105] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10814 19:24:28.933680 <6>[ 15.348130] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10815 19:24:28.940784 <6>[ 15.348283] remoteproc remoteproc0: remote processor scp is now up
10816 19:24:28.950339 <6>[ 15.348385] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10817 19:24:28.956953 <3>[ 15.355321] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10818 19:24:28.966902 <3>[ 15.355323] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10819 19:24:28.973321 <3>[ 15.355341] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10820 19:24:28.979712 <6>[ 15.356930] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10821 19:24:28.989984 <4>[ 15.378774] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10822 19:24:28.996427 <6>[ 15.379900] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10823 19:24:29.006476 <3>[ 15.380141] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10824 19:24:29.016152 <4>[ 15.388044] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10825 19:24:29.019551 <6>[ 15.388651] Bluetooth: Core ver 2.22
10826 19:24:29.022927 <6>[ 15.388750] NET: Registered PF_BLUETOOTH protocol family
10827 19:24:29.029313 <6>[ 15.388752] Bluetooth: HCI device and connection manager initialized
10828 19:24:29.035868 <6>[ 15.388769] Bluetooth: HCI socket layer initialized
10829 19:24:29.042580 <6>[ 15.388774] Bluetooth: L2CAP socket layer initialized
10830 19:24:29.045790 <6>[ 15.388779] Bluetooth: SCO socket layer initialized
10831 19:24:29.055898 <6>[ 15.396774] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10832 19:24:29.062480 <6>[ 15.426928] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10833 19:24:29.069061 <6>[ 15.435642] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10834 19:24:29.079292 <6>[ 15.435656] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10835 19:24:29.088979 <6>[ 15.443225] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10836 19:24:29.098698 <6>[ 15.449389] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10837 19:24:29.101867 <6>[ 15.449401] pci 0000:00:00.0: PCI bridge to [bus 01]
10838 19:24:29.108662 <6>[ 15.450276] usbcore: registered new interface driver btusb
10839 19:24:29.118789 <4>[ 15.451242] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10840 19:24:29.124873 <3>[ 15.451258] Bluetooth: hci0: Failed to load firmware file (-2)
10841 19:24:29.131671 <3>[ 15.451261] Bluetooth: hci0: Failed to set up firmware (-2)
10842 19:24:29.141808 <4>[ 15.451265] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10843 19:24:29.148303 <6>[ 15.454148] usbcore: registered new interface driver uvcvideo
10844 19:24:29.155179 <6>[ 15.460780] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10845 19:24:29.161602 <6>[ 15.461014] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10846 19:24:29.167974 <6>[ 15.461476] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10847 19:24:29.171711 <6>[ 15.464908] r8152 2-1.3:1.0 eth0: v1.12.13
10848 19:24:29.177953 <6>[ 15.464945] usbcore: registered new interface driver r8152
10849 19:24:29.184378 <6>[ 15.483863] usbcore: registered new interface driver cdc_ether
10850 19:24:29.191337 <6>[ 15.491545] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10851 19:24:29.197727 <6>[ 15.506205] usbcore: registered new interface driver r8153_ecm
10852 19:24:29.200978 <6>[ 15.511109] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10853 19:24:29.207538 <6>[ 15.536318] r8152 2-1.3:1.0 enx00e04c680281: renamed from eth0
10854 19:24:29.239949 <5>[ 15.842520] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10855 19:24:29.261937 <5>[ 15.864286] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10856 19:24:29.268438 <5>[ 15.871363] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10857 19:24:29.278553 <4>[ 15.879771] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10858 19:24:29.281661 <6>[ 15.888647] cfg80211: failed to load regulatory.db
10859 19:24:29.328889 <6>[ 15.931654] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10860 19:24:29.335671 <6>[ 15.939159] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10861 19:24:29.358846 <6>[ 15.964764] mt7921e 0000:01:00.0: ASIC revision: 79610010
10862 19:24:29.462229 <6>[ 16.064318] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10863 19:24:29.465230 <6>[ 16.064318]
10864 19:24:29.468234 Begin: Loading essential drivers ... done.
10865 19:24:29.472003 Begin: Running /scripts/init-premount ... done.
10866 19:24:29.478556 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10867 19:24:29.488381 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10868 19:24:29.491337 Device /sys/class/net/enx00e04c680281 found
10869 19:24:29.491768 done.
10870 19:24:29.501198 Begin: Waiting up to 180 secs for any network device to become available ... done.
10871 19:24:29.538766 IP-Config: enx00e04c680281 hardware address 00:e0:4c:68:02:81 mtu 1500 DHCP
10872 19:24:29.728792 <6>[ 16.330970] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10873 19:24:30.501859 <6>[ 17.107909] r8152 2-1.3:1.0 enx00e04c680281: carrier on
10874 19:24:30.578590 <6>[ 17.184861] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10875 19:24:30.607152 IP-Config: no response after 2 secs - giving up
10876 19:24:30.657992 IP-Config: enx00e04c680281 hardware address 00:e0:4c:68:02:81 mtu 1500 DHCP
10877 19:24:30.670395 IP-Config: wlp1s0 hardware address d8:f3:bc:78:0c:47 mtu 1500 DHCP
10878 19:24:31.359825 IP-Config: enx00e04c680281 complete (dhcp from 192.168.201.1):
10879 19:24:31.366757 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10880 19:24:31.373108 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10881 19:24:31.379694 host : mt8192-asurada-spherion-r0-cbg-9
10882 19:24:31.386811 domain : lava-rack
10883 19:24:31.392752 rootserver: 192.168.201.1 rootpath:
10884 19:24:31.392990 filename :
10885 19:24:31.508480 done.
10886 19:24:31.516268 Begin: Running /scripts/nfs-bottom ... done.
10887 19:24:31.528167 Begin: Running /scripts/init-bottom ... done.
10888 19:24:32.879044 <6>[ 19.485350] NET: Registered PF_INET6 protocol family
10889 19:24:32.886355 <6>[ 19.492686] Segment Routing with IPv6
10890 19:24:32.889395 <6>[ 19.496618] In-situ OAM (IOAM) with IPv6
10891 19:24:33.064948 <30>[ 19.645266] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10892 19:24:33.071785 <30>[ 19.678354] systemd[1]: Detected architecture arm64.
10893 19:24:33.081381
10894 19:24:33.084477 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10895 19:24:33.084604
10896 19:24:33.084708
10897 19:24:33.107753 <30>[ 19.714301] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10898 19:24:34.196342 <30>[ 20.799919] systemd[1]: Queued start job for default target graphical.target.
10899 19:24:34.246845 <30>[ 20.850202] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10900 19:24:34.253196 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10901 19:24:34.253322
10902 19:24:34.275570 <30>[ 20.878671] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10903 19:24:34.285077 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10904 19:24:34.285185
10905 19:24:34.303631 <30>[ 20.906678] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10906 19:24:34.313120 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10907 19:24:34.313217
10908 19:24:34.331115 <30>[ 20.934291] systemd[1]: Created slice user.slice - User and Session Slice.
10909 19:24:34.337289 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10910 19:24:34.337425
10911 19:24:34.361609 <30>[ 20.961797] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10912 19:24:34.371707 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10913 19:24:34.371812
10914 19:24:34.389274 <30>[ 20.989174] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10915 19:24:34.395522 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10916 19:24:34.395618
10917 19:24:34.424055 <30>[ 21.017578] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10918 19:24:34.434188 <30>[ 21.037496] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10919 19:24:34.441108 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10920 19:24:34.441205
10921 19:24:34.457892 <30>[ 21.061329] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10922 19:24:34.467999 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10923 19:24:34.468101
10924 19:24:34.485952 <30>[ 21.089039] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10925 19:24:34.495383 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10926 19:24:34.495487
10927 19:24:34.510174 <30>[ 21.117032] systemd[1]: Reached target paths.target - Path Units.
10928 19:24:34.517057 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10929 19:24:34.519886
10930 19:24:34.538279 <30>[ 21.141325] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10931 19:24:34.544612 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10932 19:24:34.544703
10933 19:24:34.561307 <30>[ 21.164941] systemd[1]: Reached target slices.target - Slice Units.
10934 19:24:34.567841 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10935 19:24:34.567987
10936 19:24:34.582645 <30>[ 21.189435] systemd[1]: Reached target swap.target - Swaps.
10937 19:24:34.589506 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10938 19:24:34.589647
10939 19:24:34.610322 <30>[ 21.213472] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10940 19:24:34.619547 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10941 19:24:34.619699
10942 19:24:34.638095 <30>[ 21.241428] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10943 19:24:34.647873 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10944 19:24:34.648012
10945 19:24:34.669029 <30>[ 21.272210] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10946 19:24:34.678600 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10947 19:24:34.678750
10948 19:24:34.694641 <30>[ 21.298270] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10949 19:24:34.704971 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10950 19:24:34.705088
10951 19:24:34.722350 <30>[ 21.325735] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10952 19:24:34.728902 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10953 19:24:34.729024
10954 19:24:34.747058 <30>[ 21.350466] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10955 19:24:34.756794 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10956 19:24:34.756907
10957 19:24:34.776282 <30>[ 21.379748] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10958 19:24:34.786628 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10959 19:24:34.786723
10960 19:24:34.802948 <30>[ 21.406143] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10961 19:24:34.812439 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10962 19:24:34.812529
10963 19:24:34.869861 <30>[ 21.473134] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10964 19:24:34.876487 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10965 19:24:34.876638
10966 19:24:34.898209 <30>[ 21.501657] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10967 19:24:34.904769 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10968 19:24:34.904860
10969 19:24:34.945880 <30>[ 21.549106] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10970 19:24:34.952324 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10971 19:24:34.952414
10972 19:24:34.976115 <30>[ 21.573318] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10973 19:24:34.990974 <30>[ 21.594568] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10974 19:24:35.001071 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10975 19:24:35.001205
10976 19:24:35.022494 <30>[ 21.625921] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10977 19:24:35.029052 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10978 19:24:35.029214
10979 19:24:35.055661 <30>[ 21.658663] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10980 19:24:35.062025 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10981 19:24:35.062423
10982 19:24:35.087227 <30>[ 21.690230] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10983 19:24:35.100195 Starting [0;1;39mmodprobe@drm.service[0m - Load Kerne<6>[ 21.703678] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10984 19:24:35.103795 l Module drm...
10985 19:24:35.104214
10986 19:24:35.162762 <30>[ 21.765542] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10987 19:24:35.172257 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10988 19:24:35.172688
10989 19:24:35.195131 <30>[ 21.798500] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10990 19:24:35.202305 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10991 19:24:35.202733
10992 19:24:35.225959 <30>[ 21.829174] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10993 19:24:35.236380 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop..<6>[ 21.843367] fuse: init (API version 7.37)
10994 19:24:35.237026 .
10995 19:24:35.239120
10996 19:24:35.267143 <30>[ 21.870479] systemd[1]: Starting systemd-journald.service - Journal Service...
10997 19:24:35.274200 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10998 19:24:35.274634
10999 19:24:35.298239 <30>[ 21.901252] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
11000 19:24:35.304553 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
11001 19:24:35.304977
11002 19:24:35.369987 <30>[ 21.969862] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
11003 19:24:35.376377 Starting [0;1;39msystemd-network-g… units from Kernel command line...
11004 19:24:35.376817
11005 19:24:35.396460 <30>[ 21.999877] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
11006 19:24:35.406254 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
11007 19:24:35.406342
11008 19:24:35.429246 <30>[ 22.031919] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
11009 19:24:35.442311 Starting [0;1;39msyste<3>[ 22.043260] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11010 19:24:35.445248 md-udev-trig…[0m - Coldplug All udev Devices...
11011 19:24:35.445364
11012 19:24:35.471934 <30>[ 22.075666] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
11013 19:24:35.478575 <3>[ 22.080081] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11014 19:24:35.488486 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
11015 19:24:35.488570
11016 19:24:35.506144 <30>[ 22.109418] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
11017 19:24:35.519854 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSI<3>[ 22.122514] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11018 19:24:35.523152 X Message Queue File System.
11019 19:24:35.523254
11020 19:24:35.542488 <30>[ 22.145176] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
11021 19:24:35.549103 <3>[ 22.151912] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11022 19:24:35.558465 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
11023 19:24:35.558574
11024 19:24:35.578536 <30>[ 22.181868] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
11025 19:24:35.588297 <3>[ 22.191233] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11026 19:24:35.595109 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
11027 19:24:35.595224
11028 19:24:35.617292 <3>[ 22.220519] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11029 19:24:35.627552 <30>[ 22.231279] systemd[1]: modprobe@configfs.service: Deactivated successfully.
11030 19:24:35.634532 <30>[ 22.239172] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
11031 19:24:35.647963 [[0;32m OK [0m] Finished [0;1;39mmodprobe@c<3>[ 22.251430] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11032 19:24:35.655071 onfigfs…[0m - Load Kernel Module configfs.
11033 19:24:35.655471
11034 19:24:35.671674 <30>[ 22.274063] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
11035 19:24:35.677957 <30>[ 22.281966] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
11036 19:24:35.687898 <3>[ 22.284254] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11037 19:24:35.694609 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
11038 19:24:35.695056
11039 19:24:35.719462 <3>[ 22.322469] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11040 19:24:35.726430 <30>[ 22.323001] systemd[1]: modprobe@drm.service: Deactivated successfully.
11041 19:24:35.736468 <30>[ 22.339204] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
11042 19:24:35.742796 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
11043 19:24:35.743229
11044 19:24:35.763522 <30>[ 22.366640] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
11045 19:24:35.770146 <3>[ 22.367347] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11046 19:24:35.779975 <30>[ 22.375033] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
11047 19:24:35.789851 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
11048 19:24:35.790278
11049 19:24:35.811661 <30>[ 22.414835] systemd[1]: modprobe@fuse.service: Deactivated successfully.
11050 19:24:35.818499 <30>[ 22.422656] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
11051 19:24:35.825852 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
11052 19:24:35.826291
11053 19:24:35.854489 <4>[ 22.450905] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
11054 19:24:35.864280 <3>[ 22.466572] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
11055 19:24:35.870535 <30>[ 22.467238] systemd[1]: Started systemd-journald.service - Journal Service.
11056 19:24:35.877050 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
11057 19:24:35.877670
11058 19:24:35.903568 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
11059 19:24:35.904137
11060 19:24:35.926844 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
11061 19:24:35.926970
11062 19:24:35.946415 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
11063 19:24:35.946538
11064 19:24:35.967043 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
11065 19:24:35.967162
11066 19:24:35.986723 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
11067 19:24:35.986840
11068 19:24:36.008492 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
11069 19:24:36.008609
11070 19:24:36.070436 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
11071 19:24:36.071035
11072 19:24:36.088861 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
11073 19:24:36.089477
11074 19:24:36.113840 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
11075 19:24:36.114308
11076 19:24:36.139421 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
11077 19:24:36.140065
11078 19:24:36.184029 <46>[ 22.787024] systemd-journald[299]: Received client request to flush runtime journal.
11079 19:24:36.194778 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
11080 19:24:36.195243
11081 19:24:36.225489 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
11082 19:24:36.225930
11083 19:24:36.510833 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
11084 19:24:36.511022
11085 19:24:36.530046 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
11086 19:24:36.530147
11087 19:24:36.550964 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
11088 19:24:36.551230
11089 19:24:36.968868 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
11090 19:24:36.969042
11091 19:24:37.623144 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11092 19:24:37.623277
11093 19:24:37.643492 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
11094 19:24:37.643609
11095 19:24:37.694859 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
11096 19:24:37.695343
11097 19:24:37.839139 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11098 19:24:37.839642
11099 19:24:37.858310 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11100 19:24:37.858768
11101 19:24:37.878120 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11102 19:24:37.878554
11103 19:24:37.926236 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11104 19:24:37.926687
11105 19:24:37.952362 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11106 19:24:37.952862
11107 19:24:38.224875 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11108 19:24:38.225031
11109 19:24:38.300086 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11110 19:24:38.300210
11111 19:24:38.341077 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11112 19:24:38.341193
11113 19:24:38.628794 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11114 19:24:38.628929
11115 19:24:38.679768 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11116 19:24:38.679899
11117 19:24:38.727565 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11118 19:24:38.727709
11119 19:24:38.841936 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11120 19:24:38.842077
11121 19:24:38.865027 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11122 19:24:38.865147
11123 19:24:38.887089 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11124 19:24:38.887202
11125 19:24:38.962059 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11126 19:24:38.962284
11127 19:24:38.993861 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11128 19:24:38.994337
11129 19:24:39.008811 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11130 19:24:39.009237
11131 19:24:39.032918 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11132 19:24:39.033468
11133 19:24:39.086844 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11134 19:24:39.087201
11135 19:24:39.106249 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11136 19:24:39.106390
11137 19:24:39.128790 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11138 19:24:39.129289
11139 19:24:39.146291 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11140 19:24:39.146833
11141 19:24:39.170072 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11142 19:24:39.170541
11143 19:24:39.189405 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11144 19:24:39.190022
11145 19:24:39.205366 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11146 19:24:39.206069
11147 19:24:39.227277 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11148 19:24:39.227524
11149 19:24:39.248627 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11150 19:24:39.249050
11151 19:24:39.265791 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11152 19:24:39.266214
11153 19:24:39.285188 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11154 19:24:39.285744
11155 19:24:39.305416 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11156 19:24:39.305906
11157 19:24:39.321317 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11158 19:24:39.321805
11159 19:24:39.338998 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11160 19:24:39.339580
11161 19:24:39.357437 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11162 19:24:39.357862
11163 19:24:39.364034 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11164 19:24:39.364450
11165 19:24:39.419191 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11166 19:24:39.419672
11167 19:24:39.451732 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11168 19:24:39.452204
11169 19:24:39.554167 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11170 19:24:39.554336
11171 19:24:39.569306 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11172 19:24:39.569467
11173 19:24:39.764383 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11174 19:24:39.764550
11175 19:24:39.824665 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11176 19:24:39.824942
11177 19:24:39.854347 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11178 19:24:39.854472
11179 19:24:39.878682 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11180 19:24:39.878774
11181 19:24:39.896421 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11182 19:24:39.896511
11183 19:24:39.932009 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11184 19:24:39.932179
11185 19:24:39.956884 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11186 19:24:39.957309
11187 19:24:40.000964 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11188 19:24:40.001552
11189 19:24:40.019597 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11190 19:24:40.020050
11191 19:24:40.075904 Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
11192 19:24:40.076513
11193 19:24:40.101832 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11194 19:24:40.102449
11195 19:24:40.182587 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11196 19:24:40.182714
11197 19:24:40.208071 [[0;32m OK [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
11198 19:24:40.208163
11199 19:24:40.307626
11200 19:24:40.307754
11201 19:24:40.310865 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11202 19:24:40.310971
11203 19:24:40.314311 debian-bookworm-arm64 login: root (automatic login)
11204 19:24:40.314391
11205 19:24:40.314455
11206 19:24:40.648356 Linux debian-bookworm-arm64 6.1.86-cip19 #1 SMP PREEMPT Thu Apr 18 19:05:54 UTC 2024 aarch64
11207 19:24:40.648517
11208 19:24:40.655143 The programs included with the Debian GNU/Linux system are free software;
11209 19:24:40.661551 the exact distribution terms for each program are described in the
11210 19:24:40.665060 individual files in /usr/share/doc/*/copyright.
11211 19:24:40.665160
11212 19:24:40.672028 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11213 19:24:40.674718 permitted by applicable law.
11214 19:24:41.797953 Matched prompt #10: / #
11216 19:24:41.798234 Setting prompt string to ['/ #']
11217 19:24:41.798327 end: 2.2.5.1 login-action (duration 00:00:29) [common]
11219 19:24:41.798520 end: 2.2.5 auto-login-action (duration 00:00:29) [common]
11220 19:24:41.798619 start: 2.2.6 expect-shell-connection (timeout 00:03:09) [common]
11221 19:24:41.798700 Setting prompt string to ['/ #']
11222 19:24:41.798774 Forcing a shell prompt, looking for ['/ #']
11224 19:24:41.849075 / #
11225 19:24:41.849255 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11226 19:24:41.849422 Waiting using forced prompt support (timeout 00:02:30)
11227 19:24:41.854220
11228 19:24:41.854514 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11229 19:24:41.854622 start: 2.2.7 export-device-env (timeout 00:03:09) [common]
11231 19:24:41.955012 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/13420329/extract-nfsrootfs-l3_d7ahj'
11232 19:24:41.960211 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/13420329/extract-nfsrootfs-l3_d7ahj'
11234 19:24:42.060761 / # export NFS_SERVER_IP='192.168.201.1'
11235 19:24:42.066185 export NFS_SERVER_IP='192.168.201.1'
11236 19:24:42.066481 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11237 19:24:42.066594 end: 2.2 depthcharge-retry (duration 00:01:51) [common]
11238 19:24:42.066722 end: 2 depthcharge-action (duration 00:01:51) [common]
11239 19:24:42.066828 start: 3 lava-test-retry (timeout 00:07:28) [common]
11240 19:24:42.066932 start: 3.1 lava-test-shell (timeout 00:07:28) [common]
11241 19:24:42.067046 Using namespace: common
11243 19:24:42.167485 / # #
11244 19:24:42.167703 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11245 19:24:42.172673 #
11246 19:24:42.172939 Using /lava-13420329
11248 19:24:42.273348 / # export SHELL=/bin/bash
11249 19:24:42.278656 export SHELL=/bin/bash
11251 19:24:42.379201 / # . /lava-13420329/environment
11252 19:24:42.384750 . /lava-13420329/environment
11254 19:24:42.491226 / # /lava-13420329/bin/lava-test-runner /lava-13420329/0
11255 19:24:42.491407 Test shell timeout: 10s (minimum of the action and connection timeout)
11256 19:24:42.496689 /lava-13420329/bin/lava-test-runner /lava-13420329/0
11257 19:24:42.782527 + export TESTRUN_ID=0_timesync-off
11258 19:24:42.786320 + TESTRUN_ID=0_timesync-off
11259 19:24:42.789489 + cd /lava-13420329/0/tests/0_timesync-off
11260 19:24:42.792532 ++ cat uuid
11261 19:24:42.799158 + UUID=13420329_1.6.2.3.1
11262 19:24:42.799282 + set +x
11263 19:24:42.805873 <LAVA_SIGNAL_STARTRUN 0_timesync-off 13420329_1.6.2.3.1>
11264 19:24:42.806233 Received signal: <STARTRUN> 0_timesync-off 13420329_1.6.2.3.1
11265 19:24:42.806347 Starting test lava.0_timesync-off (13420329_1.6.2.3.1)
11266 19:24:42.806470 Skipping test definition patterns.
11267 19:24:42.809249 + systemctl stop systemd-timesyncd
11268 19:24:42.870217 + set +x
11269 19:24:42.873421 <LAVA_SIGNAL_ENDRUN 0_timesync-off 13420329_1.6.2.3.1>
11270 19:24:42.873703 Received signal: <ENDRUN> 0_timesync-off 13420329_1.6.2.3.1
11271 19:24:42.873792 Ending use of test pattern.
11272 19:24:42.873856 Ending test lava.0_timesync-off (13420329_1.6.2.3.1), duration 0.07
11274 19:24:42.952740 + export TESTRUN_ID=1_kselftest-alsa
11275 19:24:42.955879 + TESTRUN_ID=1_kselftest-alsa
11276 19:24:42.962254 + cd /lava-13420329/0/tests/1_kselftest-alsa
11277 19:24:42.962338 ++ cat uuid
11278 19:24:42.966517 + UUID=13420329_1.6.2.3.5
11279 19:24:42.966595 + set +x
11280 19:24:42.972884 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 13420329_1.6.2.3.5>
11281 19:24:42.973139 Received signal: <STARTRUN> 1_kselftest-alsa 13420329_1.6.2.3.5
11282 19:24:42.973210 Starting test lava.1_kselftest-alsa (13420329_1.6.2.3.5)
11283 19:24:42.973290 Skipping test definition patterns.
11284 19:24:42.976165 + cd ./automated/linux/kselftest/
11285 19:24:43.002126 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11286 19:24:43.048314 INFO: install_deps skipped
11287 19:24:43.552159 --2024-04-18 19:24:43-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11288 19:24:43.564870 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11289 19:24:43.698513 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11290 19:24:43.831644 HTTP request sent, awaiting response... 200 OK
11291 19:24:43.834867 Length: 1651832 (1.6M) [application/octet-stream]
11292 19:24:43.838739 Saving to: 'kselftest_armhf.tar.gz'
11293 19:24:43.838814
11294 19:24:43.838875
11295 19:24:44.098288 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11296 19:24:44.365155 kselftest_armhf.tar 2%[ ] 46.39K 180KB/s
11297 19:24:44.677813 kselftest_armhf.tar 13%[=> ] 217.50K 421KB/s
11298 19:24:44.815435 kselftest_armhf.tar 50%[=========> ] 819.89K 999KB/s
11299 19:24:44.822328 kselftest_armhf.tar 100%[===================>] 1.58M 1.65MB/s in 1.0s
11300 19:24:44.822460
11301 19:24:44.967062 2024-04-18 19:24:45 (1.65 MB/s) - 'kselftest_armhf.tar.gz' saved [1651832/1651832]
11302 19:24:44.967210
11303 19:24:49.535687 skiplist:
11304 19:24:49.538758 ========================================
11305 19:24:49.541861 ========================================
11306 19:24:49.596924 alsa:mixer-test
11307 19:24:49.619627 ============== Tests to run ===============
11308 19:24:49.622795 alsa:mixer-test
11309 19:24:49.626292 ===========End Tests to run ===============
11310 19:24:49.629522 shardfile-alsa pass
11311 19:24:49.738152 <12>[ 36.346550] kselftest: Running tests in alsa
11312 19:24:49.747352 TAP version 13
11313 19:24:49.762627 1..1
11314 19:24:49.781434 # selftests: alsa: mixer-test
11315 19:24:50.305390 # TAP version 13
11316 19:24:50.305552 # 1..0
11317 19:24:50.311492 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:0 error:0
11318 19:24:50.315104 ok 1 selftests: alsa: mixer-test
11319 19:24:51.819208 alsa_mixer-test pass
11320 19:24:51.895816 + ../../utils/send-to-lava.sh ./output/result.txt
11321 19:24:51.978909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
11322 19:24:51.979309 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
11324 19:24:52.034688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
11325 19:24:52.034840 + set +x
11326 19:24:52.035085 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
11328 19:24:52.041494 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 13420329_1.6.2.3.5>
11329 19:24:52.041773 Received signal: <ENDRUN> 1_kselftest-alsa 13420329_1.6.2.3.5
11330 19:24:52.041852 Ending use of test pattern.
11331 19:24:52.041914 Ending test lava.1_kselftest-alsa (13420329_1.6.2.3.5), duration 9.07
11333 19:24:52.044518 <LAVA_TEST_RUNNER EXIT>
11334 19:24:52.044775 ok: lava_test_shell seems to have completed
11335 19:24:52.044878 alsa_mixer-test: pass
shardfile-alsa: pass
11336 19:24:52.044971 end: 3.1 lava-test-shell (duration 00:00:10) [common]
11337 19:24:52.045057 end: 3 lava-test-retry (duration 00:00:10) [common]
11338 19:24:52.045145 start: 4 finalize (timeout 00:07:18) [common]
11339 19:24:52.045236 start: 4.1 power-off (timeout 00:00:30) [common]
11340 19:24:52.045434 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=off'
11341 19:24:52.121940 >> Command sent successfully.
11342 19:24:52.124743 Returned 0 in 0 seconds
11343 19:24:52.225148 end: 4.1 power-off (duration 00:00:00) [common]
11345 19:24:52.225565 start: 4.2 read-feedback (timeout 00:07:17) [common]
11346 19:24:52.225829 Listened to connection for namespace 'common' for up to 1s
11347 19:24:53.226817 Finalising connection for namespace 'common'
11348 19:24:53.227049 Disconnecting from shell: Finalise
11349 19:24:53.227162 / #
11350 19:24:53.327496 end: 4.2 read-feedback (duration 00:00:01) [common]
11351 19:24:53.327713 end: 4 finalize (duration 00:00:01) [common]
11352 19:24:53.327833 Cleaning after the job
11353 19:24:53.328019 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13420329/tftp-deploy-yatqcpq2/ramdisk
11354 19:24:53.330124 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13420329/tftp-deploy-yatqcpq2/kernel
11355 19:24:53.340778 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13420329/tftp-deploy-yatqcpq2/dtb
11356 19:24:53.341057 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13420329/tftp-deploy-yatqcpq2/nfsrootfs
11357 19:24:53.405281 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13420329/tftp-deploy-yatqcpq2/modules
11358 19:24:53.410929 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/13420329
11359 19:24:53.976556 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/13420329
11360 19:24:53.976752 Job finished correctly