Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 25
- Errors: 0
- Kernel Errors: 37
- Boot result: PASS
1 19:26:19.560531 lava-dispatcher, installed at version: 2024.01
2 19:26:19.560788 start: 0 validate
3 19:26:19.560910 Start time: 2024-04-18 19:26:19.560902+00:00 (UTC)
4 19:26:19.561023 Using caching service: 'http://localhost/cache/?uri=%s'
5 19:26:19.561144 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 19:26:19.826077 Using caching service: 'http://localhost/cache/?uri=%s'
7 19:26:19.826767 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 19:26:20.096413 Using caching service: 'http://localhost/cache/?uri=%s'
9 19:26:20.097102 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 19:26:20.359991 Using caching service: 'http://localhost/cache/?uri=%s'
11 19:26:20.360741 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 19:26:20.632029 Using caching service: 'http://localhost/cache/?uri=%s'
13 19:26:20.632750 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 19:26:20.902535 validate duration: 1.34
16 19:26:20.903809 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 19:26:20.904323 start: 1.1 download-retry (timeout 00:10:00) [common]
18 19:26:20.904782 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 19:26:20.905403 Not decompressing ramdisk as can be used compressed.
20 19:26:20.905866 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 19:26:20.906246 saving as /var/lib/lava/dispatcher/tmp/13420409/tftp-deploy-jyww44e8/ramdisk/initrd.cpio.gz
22 19:26:20.906712 total size: 5628169 (5 MB)
23 19:26:20.912377 progress 0 % (0 MB)
24 19:26:20.921517 progress 5 % (0 MB)
25 19:26:20.928807 progress 10 % (0 MB)
26 19:26:20.933217 progress 15 % (0 MB)
27 19:26:20.937203 progress 20 % (1 MB)
28 19:26:20.940418 progress 25 % (1 MB)
29 19:26:20.943363 progress 30 % (1 MB)
30 19:26:20.946158 progress 35 % (1 MB)
31 19:26:20.948371 progress 40 % (2 MB)
32 19:26:20.950857 progress 45 % (2 MB)
33 19:26:20.952790 progress 50 % (2 MB)
34 19:26:20.954952 progress 55 % (2 MB)
35 19:26:20.956928 progress 60 % (3 MB)
36 19:26:20.958650 progress 65 % (3 MB)
37 19:26:20.960566 progress 70 % (3 MB)
38 19:26:20.962120 progress 75 % (4 MB)
39 19:26:20.963848 progress 80 % (4 MB)
40 19:26:20.965400 progress 85 % (4 MB)
41 19:26:20.966988 progress 90 % (4 MB)
42 19:26:20.968576 progress 95 % (5 MB)
43 19:26:20.970013 progress 100 % (5 MB)
44 19:26:20.970241 5 MB downloaded in 0.06 s (84.45 MB/s)
45 19:26:20.970403 end: 1.1.1 http-download (duration 00:00:00) [common]
47 19:26:20.970635 end: 1.1 download-retry (duration 00:00:00) [common]
48 19:26:20.970717 start: 1.2 download-retry (timeout 00:10:00) [common]
49 19:26:20.970797 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 19:26:20.970926 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 19:26:20.970992 saving as /var/lib/lava/dispatcher/tmp/13420409/tftp-deploy-jyww44e8/kernel/Image
52 19:26:20.971053 total size: 54286848 (51 MB)
53 19:26:20.971112 No compression specified
54 19:26:20.972172 progress 0 % (0 MB)
55 19:26:20.985745 progress 5 % (2 MB)
56 19:26:20.999325 progress 10 % (5 MB)
57 19:26:21.012914 progress 15 % (7 MB)
58 19:26:21.026453 progress 20 % (10 MB)
59 19:26:21.039756 progress 25 % (12 MB)
60 19:26:21.053017 progress 30 % (15 MB)
61 19:26:21.066121 progress 35 % (18 MB)
62 19:26:21.079765 progress 40 % (20 MB)
63 19:26:21.093278 progress 45 % (23 MB)
64 19:26:21.106746 progress 50 % (25 MB)
65 19:26:21.120667 progress 55 % (28 MB)
66 19:26:21.134497 progress 60 % (31 MB)
67 19:26:21.148608 progress 65 % (33 MB)
68 19:26:21.162500 progress 70 % (36 MB)
69 19:26:21.176815 progress 75 % (38 MB)
70 19:26:21.191556 progress 80 % (41 MB)
71 19:26:21.205820 progress 85 % (44 MB)
72 19:26:21.220143 progress 90 % (46 MB)
73 19:26:21.233836 progress 95 % (49 MB)
74 19:26:21.247630 progress 100 % (51 MB)
75 19:26:21.247850 51 MB downloaded in 0.28 s (187.04 MB/s)
76 19:26:21.247997 end: 1.2.1 http-download (duration 00:00:00) [common]
78 19:26:21.248228 end: 1.2 download-retry (duration 00:00:00) [common]
79 19:26:21.248311 start: 1.3 download-retry (timeout 00:10:00) [common]
80 19:26:21.248397 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 19:26:21.248533 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 19:26:21.248601 saving as /var/lib/lava/dispatcher/tmp/13420409/tftp-deploy-jyww44e8/dtb/mt8192-asurada-spherion-r0.dtb
83 19:26:21.248661 total size: 47230 (0 MB)
84 19:26:21.248721 No compression specified
85 19:26:21.249841 progress 69 % (0 MB)
86 19:26:21.250165 progress 100 % (0 MB)
87 19:26:21.250320 0 MB downloaded in 0.00 s (27.18 MB/s)
88 19:26:21.250440 end: 1.3.1 http-download (duration 00:00:00) [common]
90 19:26:21.250653 end: 1.3 download-retry (duration 00:00:00) [common]
91 19:26:21.250735 start: 1.4 download-retry (timeout 00:10:00) [common]
92 19:26:21.250813 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 19:26:21.250930 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 19:26:21.250996 saving as /var/lib/lava/dispatcher/tmp/13420409/tftp-deploy-jyww44e8/nfsrootfs/full.rootfs.tar
95 19:26:21.251055 total size: 120894716 (115 MB)
96 19:26:21.251115 Using unxz to decompress xz
97 19:26:21.255064 progress 0 % (0 MB)
98 19:26:21.593466 progress 5 % (5 MB)
99 19:26:21.940685 progress 10 % (11 MB)
100 19:26:22.283391 progress 15 % (17 MB)
101 19:26:22.603636 progress 20 % (23 MB)
102 19:26:22.890475 progress 25 % (28 MB)
103 19:26:23.237752 progress 30 % (34 MB)
104 19:26:23.568832 progress 35 % (40 MB)
105 19:26:23.730997 progress 40 % (46 MB)
106 19:26:23.905025 progress 45 % (51 MB)
107 19:26:24.204851 progress 50 % (57 MB)
108 19:26:24.575841 progress 55 % (63 MB)
109 19:26:24.911849 progress 60 % (69 MB)
110 19:26:25.241457 progress 65 % (74 MB)
111 19:26:25.575663 progress 70 % (80 MB)
112 19:26:25.927298 progress 75 % (86 MB)
113 19:26:26.257921 progress 80 % (92 MB)
114 19:26:26.588858 progress 85 % (98 MB)
115 19:26:26.941378 progress 90 % (103 MB)
116 19:26:27.261262 progress 95 % (109 MB)
117 19:26:27.609691 progress 100 % (115 MB)
118 19:26:27.614973 115 MB downloaded in 6.36 s (18.12 MB/s)
119 19:26:27.615238 end: 1.4.1 http-download (duration 00:00:06) [common]
121 19:26:27.615528 end: 1.4 download-retry (duration 00:00:06) [common]
122 19:26:27.615629 start: 1.5 download-retry (timeout 00:09:53) [common]
123 19:26:27.615733 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 19:26:27.615898 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 19:26:27.615998 saving as /var/lib/lava/dispatcher/tmp/13420409/tftp-deploy-jyww44e8/modules/modules.tar
126 19:26:27.616079 total size: 8631416 (8 MB)
127 19:26:27.616161 Using unxz to decompress xz
128 19:26:27.620298 progress 0 % (0 MB)
129 19:26:27.639004 progress 5 % (0 MB)
130 19:26:27.662927 progress 10 % (0 MB)
131 19:26:27.686345 progress 15 % (1 MB)
132 19:26:27.708761 progress 20 % (1 MB)
133 19:26:27.732705 progress 25 % (2 MB)
134 19:26:27.757703 progress 30 % (2 MB)
135 19:26:27.780727 progress 35 % (2 MB)
136 19:26:27.805224 progress 40 % (3 MB)
137 19:26:27.828233 progress 45 % (3 MB)
138 19:26:27.852091 progress 50 % (4 MB)
139 19:26:27.875908 progress 55 % (4 MB)
140 19:26:27.903402 progress 60 % (4 MB)
141 19:26:27.929621 progress 65 % (5 MB)
142 19:26:27.955196 progress 70 % (5 MB)
143 19:26:27.979611 progress 75 % (6 MB)
144 19:26:28.004590 progress 80 % (6 MB)
145 19:26:28.030380 progress 85 % (7 MB)
146 19:26:28.058251 progress 90 % (7 MB)
147 19:26:28.087172 progress 95 % (7 MB)
148 19:26:28.113303 progress 100 % (8 MB)
149 19:26:28.118693 8 MB downloaded in 0.50 s (16.38 MB/s)
150 19:26:28.118971 end: 1.5.1 http-download (duration 00:00:01) [common]
152 19:26:28.119232 end: 1.5 download-retry (duration 00:00:01) [common]
153 19:26:28.119325 start: 1.6 prepare-tftp-overlay (timeout 00:09:53) [common]
154 19:26:28.119417 start: 1.6.1 extract-nfsrootfs (timeout 00:09:53) [common]
155 19:26:31.463612 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/13420409/extract-nfsrootfs-jxo16__9
156 19:26:31.463823 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 19:26:31.463927 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 19:26:31.464101 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/13420409/lava-overlay-__48m8uv
159 19:26:31.464226 makedir: /var/lib/lava/dispatcher/tmp/13420409/lava-overlay-__48m8uv/lava-13420409/bin
160 19:26:31.464352 makedir: /var/lib/lava/dispatcher/tmp/13420409/lava-overlay-__48m8uv/lava-13420409/tests
161 19:26:31.464447 makedir: /var/lib/lava/dispatcher/tmp/13420409/lava-overlay-__48m8uv/lava-13420409/results
162 19:26:31.464546 Creating /var/lib/lava/dispatcher/tmp/13420409/lava-overlay-__48m8uv/lava-13420409/bin/lava-add-keys
163 19:26:31.464688 Creating /var/lib/lava/dispatcher/tmp/13420409/lava-overlay-__48m8uv/lava-13420409/bin/lava-add-sources
164 19:26:31.464856 Creating /var/lib/lava/dispatcher/tmp/13420409/lava-overlay-__48m8uv/lava-13420409/bin/lava-background-process-start
165 19:26:31.465007 Creating /var/lib/lava/dispatcher/tmp/13420409/lava-overlay-__48m8uv/lava-13420409/bin/lava-background-process-stop
166 19:26:31.465148 Creating /var/lib/lava/dispatcher/tmp/13420409/lava-overlay-__48m8uv/lava-13420409/bin/lava-common-functions
167 19:26:31.465318 Creating /var/lib/lava/dispatcher/tmp/13420409/lava-overlay-__48m8uv/lava-13420409/bin/lava-echo-ipv4
168 19:26:31.465439 Creating /var/lib/lava/dispatcher/tmp/13420409/lava-overlay-__48m8uv/lava-13420409/bin/lava-install-packages
169 19:26:31.465560 Creating /var/lib/lava/dispatcher/tmp/13420409/lava-overlay-__48m8uv/lava-13420409/bin/lava-installed-packages
170 19:26:31.465679 Creating /var/lib/lava/dispatcher/tmp/13420409/lava-overlay-__48m8uv/lava-13420409/bin/lava-os-build
171 19:26:31.465800 Creating /var/lib/lava/dispatcher/tmp/13420409/lava-overlay-__48m8uv/lava-13420409/bin/lava-probe-channel
172 19:26:31.465921 Creating /var/lib/lava/dispatcher/tmp/13420409/lava-overlay-__48m8uv/lava-13420409/bin/lava-probe-ip
173 19:26:31.466218 Creating /var/lib/lava/dispatcher/tmp/13420409/lava-overlay-__48m8uv/lava-13420409/bin/lava-target-ip
174 19:26:31.466345 Creating /var/lib/lava/dispatcher/tmp/13420409/lava-overlay-__48m8uv/lava-13420409/bin/lava-target-mac
175 19:26:31.466467 Creating /var/lib/lava/dispatcher/tmp/13420409/lava-overlay-__48m8uv/lava-13420409/bin/lava-target-storage
176 19:26:31.466590 Creating /var/lib/lava/dispatcher/tmp/13420409/lava-overlay-__48m8uv/lava-13420409/bin/lava-test-case
177 19:26:31.466712 Creating /var/lib/lava/dispatcher/tmp/13420409/lava-overlay-__48m8uv/lava-13420409/bin/lava-test-event
178 19:26:31.466832 Creating /var/lib/lava/dispatcher/tmp/13420409/lava-overlay-__48m8uv/lava-13420409/bin/lava-test-feedback
179 19:26:31.466953 Creating /var/lib/lava/dispatcher/tmp/13420409/lava-overlay-__48m8uv/lava-13420409/bin/lava-test-raise
180 19:26:31.467072 Creating /var/lib/lava/dispatcher/tmp/13420409/lava-overlay-__48m8uv/lava-13420409/bin/lava-test-reference
181 19:26:31.467192 Creating /var/lib/lava/dispatcher/tmp/13420409/lava-overlay-__48m8uv/lava-13420409/bin/lava-test-runner
182 19:26:31.467313 Creating /var/lib/lava/dispatcher/tmp/13420409/lava-overlay-__48m8uv/lava-13420409/bin/lava-test-set
183 19:26:31.467432 Creating /var/lib/lava/dispatcher/tmp/13420409/lava-overlay-__48m8uv/lava-13420409/bin/lava-test-shell
184 19:26:31.467557 Updating /var/lib/lava/dispatcher/tmp/13420409/lava-overlay-__48m8uv/lava-13420409/bin/lava-add-keys (debian)
185 19:26:31.467706 Updating /var/lib/lava/dispatcher/tmp/13420409/lava-overlay-__48m8uv/lava-13420409/bin/lava-add-sources (debian)
186 19:26:31.467845 Updating /var/lib/lava/dispatcher/tmp/13420409/lava-overlay-__48m8uv/lava-13420409/bin/lava-install-packages (debian)
187 19:26:31.467982 Updating /var/lib/lava/dispatcher/tmp/13420409/lava-overlay-__48m8uv/lava-13420409/bin/lava-installed-packages (debian)
188 19:26:31.468118 Updating /var/lib/lava/dispatcher/tmp/13420409/lava-overlay-__48m8uv/lava-13420409/bin/lava-os-build (debian)
189 19:26:31.468236 Creating /var/lib/lava/dispatcher/tmp/13420409/lava-overlay-__48m8uv/lava-13420409/environment
190 19:26:31.468329 LAVA metadata
191 19:26:31.468398 - LAVA_JOB_ID=13420409
192 19:26:31.468458 - LAVA_DISPATCHER_IP=192.168.201.1
193 19:26:31.468557 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
194 19:26:31.468620 skipped lava-vland-overlay
195 19:26:31.468691 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 19:26:31.468767 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
197 19:26:31.468825 skipped lava-multinode-overlay
198 19:26:31.468894 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 19:26:31.468968 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
200 19:26:31.469038 Loading test definitions
201 19:26:31.469170 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
202 19:26:31.469250 Using /lava-13420409 at stage 0
203 19:26:31.469517 uuid=13420409_1.6.2.3.1 testdef=None
204 19:26:31.469601 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 19:26:31.469681 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
206 19:26:31.470185 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 19:26:31.470399 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
209 19:26:31.470927 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 19:26:31.471180 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
212 19:26:31.471852 runner path: /var/lib/lava/dispatcher/tmp/13420409/lava-overlay-__48m8uv/lava-13420409/0/tests/0_timesync-off test_uuid 13420409_1.6.2.3.1
213 19:26:31.472005 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 19:26:31.472223 start: 1.6.2.3.5 git-repo-action (timeout 00:09:49) [common]
216 19:26:31.472291 Using /lava-13420409 at stage 0
217 19:26:31.472384 Fetching tests from https://github.com/kernelci/test-definitions.git
218 19:26:31.472467 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/13420409/lava-overlay-__48m8uv/lava-13420409/0/tests/1_kselftest-tpm2'
219 19:26:33.663860 Running '/usr/bin/git checkout kernelci.org
220 19:26:33.808642 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/13420409/lava-overlay-__48m8uv/lava-13420409/0/tests/1_kselftest-tpm2/automated/linux/kselftest/kselftest.yaml
221 19:26:33.809379 uuid=13420409_1.6.2.3.5 testdef=None
222 19:26:33.809540 end: 1.6.2.3.5 git-repo-action (duration 00:00:02) [common]
224 19:26:33.809791 start: 1.6.2.3.6 test-overlay (timeout 00:09:47) [common]
225 19:26:33.810619 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 19:26:33.810854 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:47) [common]
228 19:26:33.811811 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 19:26:33.812043 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:47) [common]
231 19:26:33.812953 runner path: /var/lib/lava/dispatcher/tmp/13420409/lava-overlay-__48m8uv/lava-13420409/0/tests/1_kselftest-tpm2 test_uuid 13420409_1.6.2.3.5
232 19:26:33.813046 BOARD='mt8192-asurada-spherion-r0'
233 19:26:33.813111 BRANCH='cip'
234 19:26:33.813171 SKIPFILE='/dev/null'
235 19:26:33.813228 SKIP_INSTALL='True'
236 19:26:33.813285 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 19:26:33.813344 TST_CASENAME=''
238 19:26:33.813399 TST_CMDFILES='tpm2'
239 19:26:33.813537 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 19:26:33.813741 Creating lava-test-runner.conf files
242 19:26:33.813804 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/13420409/lava-overlay-__48m8uv/lava-13420409/0 for stage 0
243 19:26:33.813897 - 0_timesync-off
244 19:26:33.813966 - 1_kselftest-tpm2
245 19:26:33.814066 end: 1.6.2.3 test-definition (duration 00:00:02) [common]
246 19:26:33.814152 start: 1.6.2.4 compress-overlay (timeout 00:09:47) [common]
247 19:26:41.210902 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 19:26:41.211067 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:40) [common]
249 19:26:41.211163 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 19:26:41.211262 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
251 19:26:41.211354 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:40) [common]
252 19:26:41.380388 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 19:26:41.380775 start: 1.6.4 extract-modules (timeout 00:09:40) [common]
254 19:26:41.380893 extracting modules file /var/lib/lava/dispatcher/tmp/13420409/tftp-deploy-jyww44e8/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13420409/extract-nfsrootfs-jxo16__9
255 19:26:41.595977 extracting modules file /var/lib/lava/dispatcher/tmp/13420409/tftp-deploy-jyww44e8/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13420409/extract-overlay-ramdisk-rxix6_iw/ramdisk
256 19:26:41.821529 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 19:26:41.821720 start: 1.6.5 apply-overlay-tftp (timeout 00:09:39) [common]
258 19:26:41.821839 [common] Applying overlay to NFS
259 19:26:41.821943 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13420409/compress-overlay-n1uczm3s/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/13420409/extract-nfsrootfs-jxo16__9
260 19:26:42.778507 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 19:26:42.778690 start: 1.6.6 configure-preseed-file (timeout 00:09:38) [common]
262 19:26:42.778798 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 19:26:42.778888 start: 1.6.7 compress-ramdisk (timeout 00:09:38) [common]
264 19:26:42.778971 Building ramdisk /var/lib/lava/dispatcher/tmp/13420409/extract-overlay-ramdisk-rxix6_iw/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/13420409/extract-overlay-ramdisk-rxix6_iw/ramdisk
265 19:26:43.134514 >> 130624 blocks
266 19:26:45.244675 rename /var/lib/lava/dispatcher/tmp/13420409/extract-overlay-ramdisk-rxix6_iw/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/13420409/tftp-deploy-jyww44e8/ramdisk/ramdisk.cpio.gz
267 19:26:45.245313 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 19:26:45.245472 start: 1.6.8 prepare-kernel (timeout 00:09:36) [common]
269 19:26:45.245574 start: 1.6.8.1 prepare-fit (timeout 00:09:36) [common]
270 19:26:45.245681 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/13420409/tftp-deploy-jyww44e8/kernel/Image'
271 19:26:59.126907 Returned 0 in 13 seconds
272 19:26:59.227917 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/13420409/tftp-deploy-jyww44e8/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/13420409/tftp-deploy-jyww44e8/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/13420409/tftp-deploy-jyww44e8/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/13420409/tftp-deploy-jyww44e8/kernel/image.itb
273 19:26:59.584175 output: FIT description: Kernel Image image with one or more FDT blobs
274 19:26:59.584547 output: Created: Thu Apr 18 20:26:59 2024
275 19:26:59.584624 output: Image 0 (kernel-1)
276 19:26:59.584690 output: Description:
277 19:26:59.584750 output: Created: Thu Apr 18 20:26:59 2024
278 19:26:59.584810 output: Type: Kernel Image
279 19:26:59.584870 output: Compression: lzma compressed
280 19:26:59.584931 output: Data Size: 12910355 Bytes = 12607.77 KiB = 12.31 MiB
281 19:26:59.584987 output: Architecture: AArch64
282 19:26:59.585046 output: OS: Linux
283 19:26:59.585101 output: Load Address: 0x00000000
284 19:26:59.585155 output: Entry Point: 0x00000000
285 19:26:59.585210 output: Hash algo: crc32
286 19:26:59.585264 output: Hash value: bbac8b0b
287 19:26:59.585316 output: Image 1 (fdt-1)
288 19:26:59.585370 output: Description: mt8192-asurada-spherion-r0
289 19:26:59.585421 output: Created: Thu Apr 18 20:26:59 2024
290 19:26:59.585473 output: Type: Flat Device Tree
291 19:26:59.585524 output: Compression: uncompressed
292 19:26:59.585575 output: Data Size: 47230 Bytes = 46.12 KiB = 0.05 MiB
293 19:26:59.585626 output: Architecture: AArch64
294 19:26:59.585677 output: Hash algo: crc32
295 19:26:59.585728 output: Hash value: 4bf0d1ac
296 19:26:59.585779 output: Image 2 (ramdisk-1)
297 19:26:59.585830 output: Description: unavailable
298 19:26:59.585881 output: Created: Thu Apr 18 20:26:59 2024
299 19:26:59.585932 output: Type: RAMDisk Image
300 19:26:59.585983 output: Compression: Unknown Compression
301 19:26:59.586058 output: Data Size: 18775594 Bytes = 18335.54 KiB = 17.91 MiB
302 19:26:59.586209 output: Architecture: AArch64
303 19:26:59.586292 output: OS: Linux
304 19:26:59.586344 output: Load Address: unavailable
305 19:26:59.586395 output: Entry Point: unavailable
306 19:26:59.586446 output: Hash algo: crc32
307 19:26:59.586496 output: Hash value: 1f1e57f8
308 19:26:59.586547 output: Default Configuration: 'conf-1'
309 19:26:59.586598 output: Configuration 0 (conf-1)
310 19:26:59.586649 output: Description: mt8192-asurada-spherion-r0
311 19:26:59.586701 output: Kernel: kernel-1
312 19:26:59.586751 output: Init Ramdisk: ramdisk-1
313 19:26:59.586802 output: FDT: fdt-1
314 19:26:59.586853 output: Loadables: kernel-1
315 19:26:59.586904 output:
316 19:26:59.587111 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 19:26:59.587213 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 19:26:59.587312 end: 1.6 prepare-tftp-overlay (duration 00:00:31) [common]
319 19:26:59.587403 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:21) [common]
320 19:26:59.587481 No LXC device requested
321 19:26:59.587558 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 19:26:59.587640 start: 1.8 deploy-device-env (timeout 00:09:21) [common]
323 19:26:59.587714 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 19:26:59.587781 Checking files for TFTP limit of 4294967296 bytes.
325 19:26:59.588285 end: 1 tftp-deploy (duration 00:00:39) [common]
326 19:26:59.588467 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 19:26:59.588598 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 19:26:59.588739 substitutions:
329 19:26:59.588807 - {DTB}: 13420409/tftp-deploy-jyww44e8/dtb/mt8192-asurada-spherion-r0.dtb
330 19:26:59.588869 - {INITRD}: 13420409/tftp-deploy-jyww44e8/ramdisk/ramdisk.cpio.gz
331 19:26:59.588927 - {KERNEL}: 13420409/tftp-deploy-jyww44e8/kernel/Image
332 19:26:59.589013 - {LAVA_MAC}: None
333 19:26:59.589068 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/13420409/extract-nfsrootfs-jxo16__9
334 19:26:59.589122 - {NFS_SERVER_IP}: 192.168.201.1
335 19:26:59.589175 - {PRESEED_CONFIG}: None
336 19:26:59.589256 - {PRESEED_LOCAL}: None
337 19:26:59.589308 - {RAMDISK}: 13420409/tftp-deploy-jyww44e8/ramdisk/ramdisk.cpio.gz
338 19:26:59.589360 - {ROOT_PART}: None
339 19:26:59.589412 - {ROOT}: None
340 19:26:59.589464 - {SERVER_IP}: 192.168.201.1
341 19:26:59.589516 - {TEE}: None
342 19:26:59.589568 Parsed boot commands:
343 19:26:59.589621 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 19:26:59.589806 Parsed boot commands: tftpboot 192.168.201.1 13420409/tftp-deploy-jyww44e8/kernel/image.itb 13420409/tftp-deploy-jyww44e8/kernel/cmdline
345 19:26:59.589892 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 19:26:59.589977 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 19:26:59.590115 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 19:26:59.590200 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 19:26:59.590272 Not connected, no need to disconnect.
350 19:26:59.590357 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 19:26:59.590480 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 19:26:59.590546 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
353 19:26:59.594762 Setting prompt string to ['lava-test: # ']
354 19:26:59.595117 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 19:26:59.595221 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 19:26:59.595336 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 19:26:59.595457 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 19:26:59.595693 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=reboot'
359 19:27:04.729083 >> Command sent successfully.
360 19:27:04.731593 Returned 0 in 5 seconds
361 19:27:04.832027 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 19:27:04.832373 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 19:27:04.832473 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 19:27:04.832563 Setting prompt string to 'Starting depthcharge on Spherion...'
366 19:27:04.832631 Changing prompt to 'Starting depthcharge on Spherion...'
367 19:27:04.832697 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 19:27:04.832967 [Enter `^Ec?' for help]
369 19:27:05.011363
370 19:27:05.011643
371 19:27:05.011800 F0: 102B 0000
372 19:27:05.011951
373 19:27:05.012094 F3: 1001 0000 [0200]
374 19:27:05.014183
375 19:27:05.014339 F3: 1001 0000
376 19:27:05.014462
377 19:27:05.014576 F7: 102D 0000
378 19:27:05.014687
379 19:27:05.017871 F1: 0000 0000
380 19:27:05.018040
381 19:27:05.018167 V0: 0000 0000 [0001]
382 19:27:05.018283
383 19:27:05.021088 00: 0007 8000
384 19:27:05.021297
385 19:27:05.021458 01: 0000 0000
386 19:27:05.021565
387 19:27:05.024291 BP: 0C00 0209 [0000]
388 19:27:05.024409
389 19:27:05.024506 G0: 1182 0000
390 19:27:05.024593
391 19:27:05.027566 EC: 0000 0021 [4000]
392 19:27:05.027684
393 19:27:05.027777 S7: 0000 0000 [0000]
394 19:27:05.027863
395 19:27:05.031514 CC: 0000 0000 [0001]
396 19:27:05.031620
397 19:27:05.031703 T0: 0000 0040 [010F]
398 19:27:05.031781
399 19:27:05.031855 Jump to BL
400 19:27:05.031926
401 19:27:05.058016
402 19:27:05.058195
403 19:27:05.058265
404 19:27:05.065130 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 19:27:05.068534 ARM64: Exception handlers installed.
406 19:27:05.072539 ARM64: Testing exception
407 19:27:05.076002 ARM64: Done test exception
408 19:27:05.082512 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 19:27:05.092605 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 19:27:05.099781 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 19:27:05.109883 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 19:27:05.116405 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 19:27:05.123202 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 19:27:05.134521 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 19:27:05.141625 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 19:27:05.160808 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 19:27:05.164085 WDT: Last reset was cold boot
418 19:27:05.167377 SPI1(PAD0) initialized at 2873684 Hz
419 19:27:05.170612 SPI5(PAD0) initialized at 992727 Hz
420 19:27:05.173797 VBOOT: Loading verstage.
421 19:27:05.180781 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 19:27:05.184112 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 19:27:05.187009 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 19:27:05.190409 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 19:27:05.198032 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 19:27:05.204613 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 19:27:05.215455 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 19:27:05.215541
429 19:27:05.215608
430 19:27:05.227087 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 19:27:05.230423 ARM64: Exception handlers installed.
432 19:27:05.230856 ARM64: Testing exception
433 19:27:05.233917 ARM64: Done test exception
434 19:27:05.237116 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 19:27:05.243874 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 19:27:05.257255 Probing TPM: . done!
437 19:27:05.257723 TPM ready after 0 ms
438 19:27:05.264288 Connected to device vid:did:rid of 1ae0:0028:00
439 19:27:05.271558 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
440 19:27:05.321697 Initialized TPM device CR50 revision 0
441 19:27:05.335930 tlcl_send_startup: Startup return code is 0
442 19:27:05.336070 TPM: setup succeeded
443 19:27:05.346489 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 19:27:05.356063 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 19:27:05.365493 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 19:27:05.374141 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 19:27:05.377752 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 19:27:05.381220 in-header: 03 07 00 00 08 00 00 00
449 19:27:05.384786 in-data: aa e4 47 04 13 02 00 00
450 19:27:05.388070 Chrome EC: UHEPI supported
451 19:27:05.394584 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 19:27:05.407957 in-header: 03 95 00 00 08 00 00 00
453 19:27:05.411487 in-data: 18 20 20 08 00 00 00 00
454 19:27:05.411935 Phase 1
455 19:27:05.418439 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 19:27:05.422075 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 19:27:05.429100 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 19:27:05.432658 Recovery requested (1009000e)
459 19:27:05.442764 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 19:27:05.446065 tlcl_extend: response is 0
461 19:27:05.454766 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 19:27:05.460426 tlcl_extend: response is 0
463 19:27:05.467654 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 19:27:05.487552 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
465 19:27:05.495187 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 19:27:05.495365
467 19:27:05.495500
468 19:27:05.502071 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 19:27:05.505794 ARM64: Exception handlers installed.
470 19:27:05.509488 ARM64: Testing exception
471 19:27:05.512593 ARM64: Done test exception
472 19:27:05.532787 pmic_efuse_setting: Set efuses in 11 msecs
473 19:27:05.536493 pmwrap_interface_init: Select PMIF_VLD_RDY
474 19:27:05.542853 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 19:27:05.546511 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 19:27:05.552564 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 19:27:05.556077 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 19:27:05.563108 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 19:27:05.565806 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 19:27:05.569637 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 19:27:05.576541 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 19:27:05.579291 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 19:27:05.586068 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 19:27:05.589556 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 19:27:05.592824 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 19:27:05.600117 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 19:27:05.603478 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 19:27:05.610466 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 19:27:05.618314 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 19:27:05.621762 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 19:27:05.628780 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 19:27:05.632458 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 19:27:05.640183 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 19:27:05.643253 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 19:27:05.651173 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 19:27:05.654381 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 19:27:05.661767 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 19:27:05.665702 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 19:27:05.673277 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 19:27:05.676566 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 19:27:05.684299 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 19:27:05.688078 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 19:27:05.691771 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 19:27:05.695679 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 19:27:05.703064 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 19:27:05.706505 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 19:27:05.713835 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 19:27:05.717919 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 19:27:05.721177 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 19:27:05.728529 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 19:27:05.732388 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 19:27:05.735928 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 19:27:05.739292 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 19:27:05.746272 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 19:27:05.750183 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 19:27:05.753907 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 19:27:05.757654 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 19:27:05.761356 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 19:27:05.768539 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 19:27:05.771993 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 19:27:05.776019 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 19:27:05.779789 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 19:27:05.783817 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 19:27:05.787378 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 19:27:05.797977 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 19:27:05.805154 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 19:27:05.808871 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 19:27:05.816009 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 19:27:05.826700 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 19:27:05.830516 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 19:27:05.834256 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 19:27:05.837423 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 19:27:05.846625 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x2c
534 19:27:05.849871 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 19:27:05.858095 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 19:27:05.861366 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 19:27:05.870546 [RTC]rtc_get_frequency_meter,154: input=15, output=764
538 19:27:05.879790 [RTC]rtc_get_frequency_meter,154: input=23, output=949
539 19:27:05.889484 [RTC]rtc_get_frequency_meter,154: input=19, output=856
540 19:27:05.899249 [RTC]rtc_get_frequency_meter,154: input=17, output=810
541 19:27:05.908556 [RTC]rtc_get_frequency_meter,154: input=16, output=787
542 19:27:05.917944 [RTC]rtc_get_frequency_meter,154: input=16, output=786
543 19:27:05.927822 [RTC]rtc_get_frequency_meter,154: input=17, output=811
544 19:27:05.930935 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
545 19:27:05.938364 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
546 19:27:05.942170 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 19:27:05.946459 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 19:27:05.949630 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 19:27:05.953513 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 19:27:05.957058 ADC[4]: Raw value=669695 ID=5
551 19:27:05.961106 ADC[3]: Raw value=212549 ID=1
552 19:27:05.961254 RAM Code: 0x51
553 19:27:05.964307 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 19:27:05.972130 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 19:27:05.978855 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
556 19:27:05.983131 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
557 19:27:05.986538 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 19:27:05.990758 in-header: 03 07 00 00 08 00 00 00
559 19:27:05.994704 in-data: aa e4 47 04 13 02 00 00
560 19:27:05.998400 Chrome EC: UHEPI supported
561 19:27:06.005730 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 19:27:06.009153 in-header: 03 95 00 00 08 00 00 00
563 19:27:06.012924 in-data: 18 20 20 08 00 00 00 00
564 19:27:06.013351 MRC: failed to locate region type 0.
565 19:27:06.020604 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 19:27:06.024284 DRAM-K: Running full calibration
567 19:27:06.031262 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
568 19:27:06.031582 header.status = 0x0
569 19:27:06.034931 header.version = 0x6 (expected: 0x6)
570 19:27:06.038468 header.size = 0xd00 (expected: 0xd00)
571 19:27:06.038768 header.flags = 0x0
572 19:27:06.045873 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 19:27:06.063782 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
574 19:27:06.071628 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 19:27:06.075096 dram_init: ddr_geometry: 0
576 19:27:06.075187 [EMI] MDL number = 0
577 19:27:06.078847 [EMI] Get MDL freq = 0
578 19:27:06.078936 dram_init: ddr_type: 0
579 19:27:06.082337 is_discrete_lpddr4: 1
580 19:27:06.086263 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 19:27:06.086353
582 19:27:06.086441
583 19:27:06.086525 [Bian_co] ETT version 0.0.0.1
584 19:27:06.093697 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
585 19:27:06.093787
586 19:27:06.097065 dramc_set_vcore_voltage set vcore to 650000
587 19:27:06.097161 Read voltage for 800, 4
588 19:27:06.101123 Vio18 = 0
589 19:27:06.101228 Vcore = 650000
590 19:27:06.101322 Vdram = 0
591 19:27:06.101411 Vddq = 0
592 19:27:06.104428 Vmddr = 0
593 19:27:06.104555 dram_init: config_dvfs: 1
594 19:27:06.113150 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 19:27:06.116397 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 19:27:06.119865 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
597 19:27:06.124044 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
598 19:27:06.127377 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
599 19:27:06.130954 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
600 19:27:06.134227 MEM_TYPE=3, freq_sel=18
601 19:27:06.138006 sv_algorithm_assistance_LP4_1600
602 19:27:06.142211 ============ PULL DRAM RESETB DOWN ============
603 19:27:06.145804 ========== PULL DRAM RESETB DOWN end =========
604 19:27:06.149650 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 19:27:06.153284 ===================================
606 19:27:06.156983 LPDDR4 DRAM CONFIGURATION
607 19:27:06.157425 ===================================
608 19:27:06.160883 EX_ROW_EN[0] = 0x0
609 19:27:06.164769 EX_ROW_EN[1] = 0x0
610 19:27:06.165370 LP4Y_EN = 0x0
611 19:27:06.165918 WORK_FSP = 0x0
612 19:27:06.168387 WL = 0x2
613 19:27:06.168891 RL = 0x2
614 19:27:06.172240 BL = 0x2
615 19:27:06.172680 RPST = 0x0
616 19:27:06.175226 RD_PRE = 0x0
617 19:27:06.175654 WR_PRE = 0x1
618 19:27:06.179374 WR_PST = 0x0
619 19:27:06.179897 DBI_WR = 0x0
620 19:27:06.182501 DBI_RD = 0x0
621 19:27:06.182939 OTF = 0x1
622 19:27:06.186571 ===================================
623 19:27:06.190170 ===================================
624 19:27:06.190493 ANA top config
625 19:27:06.193382 ===================================
626 19:27:06.197194 DLL_ASYNC_EN = 0
627 19:27:06.200761 ALL_SLAVE_EN = 1
628 19:27:06.200957 NEW_RANK_MODE = 1
629 19:27:06.203823 DLL_IDLE_MODE = 1
630 19:27:06.207421 LP45_APHY_COMB_EN = 1
631 19:27:06.210883 TX_ODT_DIS = 1
632 19:27:06.213635 NEW_8X_MODE = 1
633 19:27:06.217252 ===================================
634 19:27:06.220694 ===================================
635 19:27:06.220804 data_rate = 1600
636 19:27:06.224127 CKR = 1
637 19:27:06.228055 DQ_P2S_RATIO = 8
638 19:27:06.231200 ===================================
639 19:27:06.235302 CA_P2S_RATIO = 8
640 19:27:06.235836 DQ_CA_OPEN = 0
641 19:27:06.238420 DQ_SEMI_OPEN = 0
642 19:27:06.242434 CA_SEMI_OPEN = 0
643 19:27:06.245609 CA_FULL_RATE = 0
644 19:27:06.248734 DQ_CKDIV4_EN = 1
645 19:27:06.249170 CA_CKDIV4_EN = 1
646 19:27:06.252553 CA_PREDIV_EN = 0
647 19:27:06.255466 PH8_DLY = 0
648 19:27:06.259381 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 19:27:06.263015 DQ_AAMCK_DIV = 4
650 19:27:06.263444 CA_AAMCK_DIV = 4
651 19:27:06.266045 CA_ADMCK_DIV = 4
652 19:27:06.269446 DQ_TRACK_CA_EN = 0
653 19:27:06.272941 CA_PICK = 800
654 19:27:06.276104 CA_MCKIO = 800
655 19:27:06.279540 MCKIO_SEMI = 0
656 19:27:06.283312 PLL_FREQ = 3068
657 19:27:06.283743 DQ_UI_PI_RATIO = 32
658 19:27:06.286934 CA_UI_PI_RATIO = 0
659 19:27:06.290539 ===================================
660 19:27:06.293780 ===================================
661 19:27:06.297398 memory_type:LPDDR4
662 19:27:06.297885 GP_NUM : 10
663 19:27:06.301610 SRAM_EN : 1
664 19:27:06.302083 MD32_EN : 0
665 19:27:06.305134 ===================================
666 19:27:06.308867 [ANA_INIT] >>>>>>>>>>>>>>
667 19:27:06.309398 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 19:27:06.312648 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 19:27:06.316556 ===================================
670 19:27:06.319756 data_rate = 1600,PCW = 0X7600
671 19:27:06.322655 ===================================
672 19:27:06.326140 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 19:27:06.332674 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 19:27:06.336176 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 19:27:06.342662 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 19:27:06.346351 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 19:27:06.349505 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 19:27:06.352444 [ANA_INIT] flow start
679 19:27:06.352628 [ANA_INIT] PLL >>>>>>>>
680 19:27:06.355613 [ANA_INIT] PLL <<<<<<<<
681 19:27:06.358808 [ANA_INIT] MIDPI >>>>>>>>
682 19:27:06.358965 [ANA_INIT] MIDPI <<<<<<<<
683 19:27:06.362310 [ANA_INIT] DLL >>>>>>>>
684 19:27:06.365411 [ANA_INIT] flow end
685 19:27:06.369181 ============ LP4 DIFF to SE enter ============
686 19:27:06.372467 ============ LP4 DIFF to SE exit ============
687 19:27:06.375681 [ANA_INIT] <<<<<<<<<<<<<
688 19:27:06.379027 [Flow] Enable top DCM control >>>>>
689 19:27:06.382520 [Flow] Enable top DCM control <<<<<
690 19:27:06.385947 Enable DLL master slave shuffle
691 19:27:06.389036 ==============================================================
692 19:27:06.392670 Gating Mode config
693 19:27:06.399042 ==============================================================
694 19:27:06.399335 Config description:
695 19:27:06.409165 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 19:27:06.415524 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 19:27:06.419275 SELPH_MODE 0: By rank 1: By Phase
698 19:27:06.426497 ==============================================================
699 19:27:06.429685 GAT_TRACK_EN = 1
700 19:27:06.432512 RX_GATING_MODE = 2
701 19:27:06.435809 RX_GATING_TRACK_MODE = 2
702 19:27:06.439478 SELPH_MODE = 1
703 19:27:06.442416 PICG_EARLY_EN = 1
704 19:27:06.445795 VALID_LAT_VALUE = 1
705 19:27:06.449327 ==============================================================
706 19:27:06.452583 Enter into Gating configuration >>>>
707 19:27:06.455789 Exit from Gating configuration <<<<
708 19:27:06.459094 Enter into DVFS_PRE_config >>>>>
709 19:27:06.469408 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 19:27:06.472659 Exit from DVFS_PRE_config <<<<<
711 19:27:06.475888 Enter into PICG configuration >>>>
712 19:27:06.479196 Exit from PICG configuration <<<<
713 19:27:06.482506 [RX_INPUT] configuration >>>>>
714 19:27:06.485981 [RX_INPUT] configuration <<<<<
715 19:27:06.489642 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 19:27:06.495843 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 19:27:06.502298 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 19:27:06.509047 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 19:27:06.515741 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 19:27:06.522274 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 19:27:06.525504 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 19:27:06.528848 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 19:27:06.531880 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 19:27:06.535309 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 19:27:06.541985 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 19:27:06.545438 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 19:27:06.548723 ===================================
728 19:27:06.552184 LPDDR4 DRAM CONFIGURATION
729 19:27:06.555196 ===================================
730 19:27:06.555283 EX_ROW_EN[0] = 0x0
731 19:27:06.558836 EX_ROW_EN[1] = 0x0
732 19:27:06.558922 LP4Y_EN = 0x0
733 19:27:06.561979 WORK_FSP = 0x0
734 19:27:06.562074 WL = 0x2
735 19:27:06.565240 RL = 0x2
736 19:27:06.565326 BL = 0x2
737 19:27:06.568498 RPST = 0x0
738 19:27:06.572300 RD_PRE = 0x0
739 19:27:06.572413 WR_PRE = 0x1
740 19:27:06.575086 WR_PST = 0x0
741 19:27:06.575172 DBI_WR = 0x0
742 19:27:06.578405 DBI_RD = 0x0
743 19:27:06.578490 OTF = 0x1
744 19:27:06.581653 ===================================
745 19:27:06.585377 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 19:27:06.588741 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 19:27:06.595320 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 19:27:06.598873 ===================================
749 19:27:06.601954 LPDDR4 DRAM CONFIGURATION
750 19:27:06.605439 ===================================
751 19:27:06.605570 EX_ROW_EN[0] = 0x10
752 19:27:06.608759 EX_ROW_EN[1] = 0x0
753 19:27:06.608890 LP4Y_EN = 0x0
754 19:27:06.612100 WORK_FSP = 0x0
755 19:27:06.612246 WL = 0x2
756 19:27:06.615612 RL = 0x2
757 19:27:06.615778 BL = 0x2
758 19:27:06.618700 RPST = 0x0
759 19:27:06.618867 RD_PRE = 0x0
760 19:27:06.622124 WR_PRE = 0x1
761 19:27:06.622314 WR_PST = 0x0
762 19:27:06.625169 DBI_WR = 0x0
763 19:27:06.625527 DBI_RD = 0x0
764 19:27:06.628487 OTF = 0x1
765 19:27:06.632608 ===================================
766 19:27:06.638811 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 19:27:06.642386 nWR fixed to 40
768 19:27:06.645474 [ModeRegInit_LP4] CH0 RK0
769 19:27:06.645923 [ModeRegInit_LP4] CH0 RK1
770 19:27:06.648901 [ModeRegInit_LP4] CH1 RK0
771 19:27:06.652344 [ModeRegInit_LP4] CH1 RK1
772 19:27:06.652787 match AC timing 12
773 19:27:06.659034 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
774 19:27:06.662139 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 19:27:06.665212 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 19:27:06.671807 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 19:27:06.675031 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 19:27:06.675220 [EMI DOE] emi_dcm 0
779 19:27:06.682127 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 19:27:06.682293 ==
781 19:27:06.685336 Dram Type= 6, Freq= 0, CH_0, rank 0
782 19:27:06.688394 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
783 19:27:06.688530 ==
784 19:27:06.694968 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 19:27:06.701558 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 19:27:06.709558 [CA 0] Center 37 (7~68) winsize 62
787 19:27:06.712705 [CA 1] Center 37 (7~68) winsize 62
788 19:27:06.716027 [CA 2] Center 35 (5~66) winsize 62
789 19:27:06.719248 [CA 3] Center 35 (5~66) winsize 62
790 19:27:06.722863 [CA 4] Center 34 (4~65) winsize 62
791 19:27:06.726004 [CA 5] Center 34 (4~64) winsize 61
792 19:27:06.726711
793 19:27:06.729530 [CmdBusTrainingLP45] Vref(ca) range 1: 32
794 19:27:06.729961
795 19:27:06.732830 [CATrainingPosCal] consider 1 rank data
796 19:27:06.735851 u2DelayCellTimex100 = 270/100 ps
797 19:27:06.739258 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
798 19:27:06.742454 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
799 19:27:06.749511 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
800 19:27:06.753047 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
801 19:27:06.756375 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
802 19:27:06.759359 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
803 19:27:06.759849
804 19:27:06.762660 CA PerBit enable=1, Macro0, CA PI delay=34
805 19:27:06.763132
806 19:27:06.765796 [CBTSetCACLKResult] CA Dly = 34
807 19:27:06.766345 CS Dly: 5 (0~36)
808 19:27:06.766820 ==
809 19:27:06.769603 Dram Type= 6, Freq= 0, CH_0, rank 1
810 19:27:06.776078 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
811 19:27:06.776529 ==
812 19:27:06.779312 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 19:27:06.785999 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 19:27:06.795309 [CA 0] Center 37 (7~68) winsize 62
815 19:27:06.798818 [CA 1] Center 37 (6~68) winsize 63
816 19:27:06.801882 [CA 2] Center 35 (5~66) winsize 62
817 19:27:06.805033 [CA 3] Center 35 (4~66) winsize 63
818 19:27:06.808914 [CA 4] Center 33 (3~64) winsize 62
819 19:27:06.811962 [CA 5] Center 34 (3~65) winsize 63
820 19:27:06.812394
821 19:27:06.815141 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 19:27:06.815573
823 19:27:06.818433 [CATrainingPosCal] consider 2 rank data
824 19:27:06.822101 u2DelayCellTimex100 = 270/100 ps
825 19:27:06.824696 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
826 19:27:06.831917 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
827 19:27:06.835218 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
828 19:27:06.838075 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
829 19:27:06.841693 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
830 19:27:06.844769 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
831 19:27:06.844905
832 19:27:06.847979 CA PerBit enable=1, Macro0, CA PI delay=34
833 19:27:06.848113
834 19:27:06.851388 [CBTSetCACLKResult] CA Dly = 34
835 19:27:06.851507 CS Dly: 5 (0~37)
836 19:27:06.851601
837 19:27:06.854903 ----->DramcWriteLeveling(PI) begin...
838 19:27:06.858348 ==
839 19:27:06.861671 Dram Type= 6, Freq= 0, CH_0, rank 0
840 19:27:06.865335 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
841 19:27:06.865422 ==
842 19:27:06.868938 Write leveling (Byte 0): 30 => 30
843 19:27:06.869036 Write leveling (Byte 1): 30 => 30
844 19:27:06.873058 DramcWriteLeveling(PI) end<-----
845 19:27:06.873143
846 19:27:06.873208 ==
847 19:27:06.876589 Dram Type= 6, Freq= 0, CH_0, rank 0
848 19:27:06.879832 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
849 19:27:06.879946 ==
850 19:27:06.883185 [Gating] SW mode calibration
851 19:27:06.890051 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 19:27:06.897024 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 19:27:06.900271 0 6 0 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
854 19:27:06.903838 0 6 4 | B1->B0 | 2e2e 2525 | 0 0 | (1 1) (0 0)
855 19:27:06.910459 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 19:27:06.913922 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 19:27:06.917306 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 19:27:06.924205 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 19:27:06.927898 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 19:27:06.930530 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 19:27:06.937557 0 7 0 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
862 19:27:06.940789 0 7 4 | B1->B0 | 3939 3f3f | 0 0 | (0 0) (0 0)
863 19:27:06.944219 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
864 19:27:06.950660 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
865 19:27:06.954427 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
866 19:27:06.957908 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
867 19:27:06.960784 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 19:27:06.967481 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 19:27:06.970773 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
870 19:27:06.974173 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
871 19:27:06.980718 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
872 19:27:06.984300 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
873 19:27:06.987897 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
874 19:27:06.994001 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 19:27:06.997389 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 19:27:07.000854 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 19:27:07.007642 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 19:27:07.011189 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 19:27:07.014362 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 19:27:07.020972 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 19:27:07.024388 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 19:27:07.027440 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 19:27:07.034066 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 19:27:07.037948 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 19:27:07.040873 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
886 19:27:07.047320 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
887 19:27:07.047588 Total UI for P1: 0, mck2ui 16
888 19:27:07.050629 best dqsien dly found for B0: ( 0, 10, 0)
889 19:27:07.053880 Total UI for P1: 0, mck2ui 16
890 19:27:07.057657 best dqsien dly found for B1: ( 0, 10, 0)
891 19:27:07.060412 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
892 19:27:07.067415 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
893 19:27:07.067535
894 19:27:07.070851 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
895 19:27:07.073776 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
896 19:27:07.077190 [Gating] SW calibration Done
897 19:27:07.077275 ==
898 19:27:07.080489 Dram Type= 6, Freq= 0, CH_0, rank 0
899 19:27:07.083714 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
900 19:27:07.083800 ==
901 19:27:07.083867 RX Vref Scan: 0
902 19:27:07.087359
903 19:27:07.087445 RX Vref 0 -> 0, step: 1
904 19:27:07.087513
905 19:27:07.090690 RX Delay -130 -> 252, step: 16
906 19:27:07.093948 iDelay=222, Bit 0, Center 69 (-50 ~ 189) 240
907 19:27:07.097315 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
908 19:27:07.103968 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
909 19:27:07.107287 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
910 19:27:07.110503 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
911 19:27:07.113829 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
912 19:27:07.117069 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
913 19:27:07.123996 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
914 19:27:07.126938 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
915 19:27:07.130701 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
916 19:27:07.133852 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
917 19:27:07.137122 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
918 19:27:07.143804 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
919 19:27:07.147128 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
920 19:27:07.150639 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
921 19:27:07.154062 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
922 19:27:07.154406 ==
923 19:27:07.157298 Dram Type= 6, Freq= 0, CH_0, rank 0
924 19:27:07.164303 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
925 19:27:07.164855 ==
926 19:27:07.165331 DQS Delay:
927 19:27:07.167476 DQS0 = 0, DQS1 = 0
928 19:27:07.167930 DQM Delay:
929 19:27:07.168405 DQM0 = 81, DQM1 = 75
930 19:27:07.170508 DQ Delay:
931 19:27:07.173949 DQ0 =69, DQ1 =85, DQ2 =77, DQ3 =77
932 19:27:07.177872 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
933 19:27:07.180559 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
934 19:27:07.184061 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
935 19:27:07.184618
936 19:27:07.185091
937 19:27:07.185489 ==
938 19:27:07.187146 Dram Type= 6, Freq= 0, CH_0, rank 0
939 19:27:07.190300 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
940 19:27:07.190764 ==
941 19:27:07.191115
942 19:27:07.191448
943 19:27:07.193785 TX Vref Scan disable
944 19:27:07.194314 == TX Byte 0 ==
945 19:27:07.200308 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
946 19:27:07.203895 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
947 19:27:07.207272 == TX Byte 1 ==
948 19:27:07.210113 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
949 19:27:07.213261 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
950 19:27:07.213645 ==
951 19:27:07.216837 Dram Type= 6, Freq= 0, CH_0, rank 0
952 19:27:07.220394 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
953 19:27:07.223496 ==
954 19:27:07.233871 TX Vref=22, minBit 4, minWin=27, winSum=448
955 19:27:07.237468 TX Vref=24, minBit 0, minWin=27, winSum=445
956 19:27:07.240525 TX Vref=26, minBit 4, minWin=27, winSum=452
957 19:27:07.243949 TX Vref=28, minBit 0, minWin=27, winSum=455
958 19:27:07.247284 TX Vref=30, minBit 0, minWin=28, winSum=455
959 19:27:07.250892 TX Vref=32, minBit 0, minWin=28, winSum=456
960 19:27:07.258191 [TxChooseVref] Worse bit 0, Min win 28, Win sum 456, Final Vref 32
961 19:27:07.258552
962 19:27:07.261574 Final TX Range 1 Vref 32
963 19:27:07.261896
964 19:27:07.262263 ==
965 19:27:07.265088 Dram Type= 6, Freq= 0, CH_0, rank 0
966 19:27:07.268411 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
967 19:27:07.268748 ==
968 19:27:07.269005
969 19:27:07.269240
970 19:27:07.271535 TX Vref Scan disable
971 19:27:07.274939 == TX Byte 0 ==
972 19:27:07.278229 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
973 19:27:07.281754 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
974 19:27:07.284712 == TX Byte 1 ==
975 19:27:07.288360 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
976 19:27:07.291359 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
977 19:27:07.291685
978 19:27:07.294919 [DATLAT]
979 19:27:07.295242 Freq=800, CH0 RK0
980 19:27:07.295497
981 19:27:07.298052 DATLAT Default: 0xa
982 19:27:07.298383 0, 0xFFFF, sum = 0
983 19:27:07.301460 1, 0xFFFF, sum = 0
984 19:27:07.301807 2, 0xFFFF, sum = 0
985 19:27:07.305031 3, 0xFFFF, sum = 0
986 19:27:07.305357 4, 0xFFFF, sum = 0
987 19:27:07.308047 5, 0xFFFF, sum = 0
988 19:27:07.308441 6, 0xFFFF, sum = 0
989 19:27:07.311197 7, 0xFFFF, sum = 0
990 19:27:07.311527 8, 0x0, sum = 1
991 19:27:07.314768 9, 0x0, sum = 2
992 19:27:07.315099 10, 0x0, sum = 3
993 19:27:07.318329 11, 0x0, sum = 4
994 19:27:07.318656 best_step = 9
995 19:27:07.318975
996 19:27:07.319224 ==
997 19:27:07.321347 Dram Type= 6, Freq= 0, CH_0, rank 0
998 19:27:07.324559 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
999 19:27:07.328152 ==
1000 19:27:07.328482 RX Vref Scan: 1
1001 19:27:07.328926
1002 19:27:07.331345 Set Vref Range= 32 -> 127
1003 19:27:07.331667
1004 19:27:07.331921 RX Vref 32 -> 127, step: 1
1005 19:27:07.334787
1006 19:27:07.335105 RX Delay -95 -> 252, step: 8
1007 19:27:07.335360
1008 19:27:07.338255 Set Vref, RX VrefLevel [Byte0]: 32
1009 19:27:07.341795 [Byte1]: 32
1010 19:27:07.345087
1011 19:27:07.345424 Set Vref, RX VrefLevel [Byte0]: 33
1012 19:27:07.348133 [Byte1]: 33
1013 19:27:07.352472
1014 19:27:07.352793 Set Vref, RX VrefLevel [Byte0]: 34
1015 19:27:07.355891 [Byte1]: 34
1016 19:27:07.360351
1017 19:27:07.360778 Set Vref, RX VrefLevel [Byte0]: 35
1018 19:27:07.363462 [Byte1]: 35
1019 19:27:07.368184
1020 19:27:07.368511 Set Vref, RX VrefLevel [Byte0]: 36
1021 19:27:07.370933 [Byte1]: 36
1022 19:27:07.375358
1023 19:27:07.378819 Set Vref, RX VrefLevel [Byte0]: 37
1024 19:27:07.379185 [Byte1]: 37
1025 19:27:07.382796
1026 19:27:07.383229 Set Vref, RX VrefLevel [Byte0]: 38
1027 19:27:07.386100 [Byte1]: 38
1028 19:27:07.390416
1029 19:27:07.390784 Set Vref, RX VrefLevel [Byte0]: 39
1030 19:27:07.393922 [Byte1]: 39
1031 19:27:07.398450
1032 19:27:07.398865 Set Vref, RX VrefLevel [Byte0]: 40
1033 19:27:07.401944 [Byte1]: 40
1034 19:27:07.405559
1035 19:27:07.405999 Set Vref, RX VrefLevel [Byte0]: 41
1036 19:27:07.408986 [Byte1]: 41
1037 19:27:07.413108
1038 19:27:07.413349 Set Vref, RX VrefLevel [Byte0]: 42
1039 19:27:07.416351 [Byte1]: 42
1040 19:27:07.420818
1041 19:27:07.421032 Set Vref, RX VrefLevel [Byte0]: 43
1042 19:27:07.423870 [Byte1]: 43
1043 19:27:07.428208
1044 19:27:07.428370 Set Vref, RX VrefLevel [Byte0]: 44
1045 19:27:07.431937 [Byte1]: 44
1046 19:27:07.435864
1047 19:27:07.436020 Set Vref, RX VrefLevel [Byte0]: 45
1048 19:27:07.439074 [Byte1]: 45
1049 19:27:07.443978
1050 19:27:07.444073 Set Vref, RX VrefLevel [Byte0]: 46
1051 19:27:07.446725 [Byte1]: 46
1052 19:27:07.451314
1053 19:27:07.451408 Set Vref, RX VrefLevel [Byte0]: 47
1054 19:27:07.454329 [Byte1]: 47
1055 19:27:07.458409
1056 19:27:07.458531 Set Vref, RX VrefLevel [Byte0]: 48
1057 19:27:07.462124 [Byte1]: 48
1058 19:27:07.466188
1059 19:27:07.466289 Set Vref, RX VrefLevel [Byte0]: 49
1060 19:27:07.469794 [Byte1]: 49
1061 19:27:07.473823
1062 19:27:07.473933 Set Vref, RX VrefLevel [Byte0]: 50
1063 19:27:07.477257 [Byte1]: 50
1064 19:27:07.481587
1065 19:27:07.481767 Set Vref, RX VrefLevel [Byte0]: 51
1066 19:27:07.484639 [Byte1]: 51
1067 19:27:07.489480
1068 19:27:07.489567 Set Vref, RX VrefLevel [Byte0]: 52
1069 19:27:07.492354 [Byte1]: 52
1070 19:27:07.496907
1071 19:27:07.497003 Set Vref, RX VrefLevel [Byte0]: 53
1072 19:27:07.500155 [Byte1]: 53
1073 19:27:07.504377
1074 19:27:07.504468 Set Vref, RX VrefLevel [Byte0]: 54
1075 19:27:07.510796 [Byte1]: 54
1076 19:27:07.510884
1077 19:27:07.514497 Set Vref, RX VrefLevel [Byte0]: 55
1078 19:27:07.517655 [Byte1]: 55
1079 19:27:07.517743
1080 19:27:07.520460 Set Vref, RX VrefLevel [Byte0]: 56
1081 19:27:07.523798 [Byte1]: 56
1082 19:27:07.523893
1083 19:27:07.527965 Set Vref, RX VrefLevel [Byte0]: 57
1084 19:27:07.531268 [Byte1]: 57
1085 19:27:07.534895
1086 19:27:07.535056 Set Vref, RX VrefLevel [Byte0]: 58
1087 19:27:07.538226 [Byte1]: 58
1088 19:27:07.542537
1089 19:27:07.542672 Set Vref, RX VrefLevel [Byte0]: 59
1090 19:27:07.545843 [Byte1]: 59
1091 19:27:07.550306
1092 19:27:07.550480 Set Vref, RX VrefLevel [Byte0]: 60
1093 19:27:07.553618 [Byte1]: 60
1094 19:27:07.557889
1095 19:27:07.558146 Set Vref, RX VrefLevel [Byte0]: 61
1096 19:27:07.560885 [Byte1]: 61
1097 19:27:07.565549
1098 19:27:07.565917 Set Vref, RX VrefLevel [Byte0]: 62
1099 19:27:07.568264 [Byte1]: 62
1100 19:27:07.572840
1101 19:27:07.573226 Set Vref, RX VrefLevel [Byte0]: 63
1102 19:27:07.576317 [Byte1]: 63
1103 19:27:07.580470
1104 19:27:07.580996 Set Vref, RX VrefLevel [Byte0]: 64
1105 19:27:07.584038 [Byte1]: 64
1106 19:27:07.588190
1107 19:27:07.588622 Set Vref, RX VrefLevel [Byte0]: 65
1108 19:27:07.591179 [Byte1]: 65
1109 19:27:07.595713
1110 19:27:07.596135 Set Vref, RX VrefLevel [Byte0]: 66
1111 19:27:07.599426 [Byte1]: 66
1112 19:27:07.603480
1113 19:27:07.603942 Set Vref, RX VrefLevel [Byte0]: 67
1114 19:27:07.606464 [Byte1]: 67
1115 19:27:07.610874
1116 19:27:07.611145 Set Vref, RX VrefLevel [Byte0]: 68
1117 19:27:07.613868 [Byte1]: 68
1118 19:27:07.618194
1119 19:27:07.618374 Set Vref, RX VrefLevel [Byte0]: 69
1120 19:27:07.621835 [Byte1]: 69
1121 19:27:07.625968
1122 19:27:07.626156 Set Vref, RX VrefLevel [Byte0]: 70
1123 19:27:07.629089 [Byte1]: 70
1124 19:27:07.633659
1125 19:27:07.633850 Set Vref, RX VrefLevel [Byte0]: 71
1126 19:27:07.636600 [Byte1]: 71
1127 19:27:07.640924
1128 19:27:07.641054 Set Vref, RX VrefLevel [Byte0]: 72
1129 19:27:07.644144 [Byte1]: 72
1130 19:27:07.648466
1131 19:27:07.648549 Set Vref, RX VrefLevel [Byte0]: 73
1132 19:27:07.651690 [Byte1]: 73
1133 19:27:07.656060
1134 19:27:07.656141 Final RX Vref Byte 0 = 54 to rank0
1135 19:27:07.659665 Final RX Vref Byte 1 = 56 to rank0
1136 19:27:07.663194 Final RX Vref Byte 0 = 54 to rank1
1137 19:27:07.666249 Final RX Vref Byte 1 = 56 to rank1==
1138 19:27:07.669576 Dram Type= 6, Freq= 0, CH_0, rank 0
1139 19:27:07.676442 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1140 19:27:07.676549 ==
1141 19:27:07.676641 DQS Delay:
1142 19:27:07.676769 DQS0 = 0, DQS1 = 0
1143 19:27:07.679562 DQM Delay:
1144 19:27:07.679642 DQM0 = 83, DQM1 = 73
1145 19:27:07.682677 DQ Delay:
1146 19:27:07.686121 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1147 19:27:07.686202 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =92
1148 19:27:07.689690 DQ8 =64, DQ9 =56, DQ10 =76, DQ11 =64
1149 19:27:07.692872 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1150 19:27:07.696253
1151 19:27:07.696343
1152 19:27:07.702792 [DQSOSCAuto] RK0, (LSB)MR18= 0x3c3c, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
1153 19:27:07.705835 CH0 RK0: MR19=606, MR18=3C3C
1154 19:27:07.712638 CH0_RK0: MR19=0x606, MR18=0x3C3C, DQSOSC=394, MR23=63, INC=95, DEC=63
1155 19:27:07.712729
1156 19:27:07.716400 ----->DramcWriteLeveling(PI) begin...
1157 19:27:07.716877 ==
1158 19:27:07.719922 Dram Type= 6, Freq= 0, CH_0, rank 1
1159 19:27:07.723174 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1160 19:27:07.723754 ==
1161 19:27:07.726187 Write leveling (Byte 0): 29 => 29
1162 19:27:07.729817 Write leveling (Byte 1): 29 => 29
1163 19:27:07.732998 DramcWriteLeveling(PI) end<-----
1164 19:27:07.733444
1165 19:27:07.733870 ==
1166 19:27:07.736334 Dram Type= 6, Freq= 0, CH_0, rank 1
1167 19:27:07.739985 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1168 19:27:07.740418 ==
1169 19:27:07.742934 [Gating] SW mode calibration
1170 19:27:07.749956 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1171 19:27:07.756568 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1172 19:27:07.760182 0 6 0 | B1->B0 | 3030 2f2f | 0 1 | (0 1) (1 0)
1173 19:27:07.762834 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1174 19:27:07.769514 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 19:27:07.773213 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 19:27:07.776367 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 19:27:07.782877 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 19:27:07.786131 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 19:27:07.790154 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 19:27:07.796293 0 7 0 | B1->B0 | 2d2d 3131 | 0 0 | (0 0) (0 0)
1181 19:27:07.799850 0 7 4 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
1182 19:27:07.803008 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1183 19:27:07.809409 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1184 19:27:07.812831 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1185 19:27:07.816120 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1186 19:27:07.823077 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1187 19:27:07.826566 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1188 19:27:07.829454 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1189 19:27:07.833172 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1190 19:27:07.839543 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1191 19:27:07.843019 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1192 19:27:07.846403 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1193 19:27:07.852916 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1194 19:27:07.856459 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1195 19:27:07.859449 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1196 19:27:07.866073 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 19:27:07.869736 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 19:27:07.872860 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 19:27:07.880000 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 19:27:07.882650 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 19:27:07.885954 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 19:27:07.892657 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 19:27:07.896118 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 19:27:07.899459 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1205 19:27:07.906397 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1206 19:27:07.909242 0 10 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1207 19:27:07.912500 Total UI for P1: 0, mck2ui 16
1208 19:27:07.916123 best dqsien dly found for B0: ( 0, 10, 2)
1209 19:27:07.919064 Total UI for P1: 0, mck2ui 16
1210 19:27:07.922878 best dqsien dly found for B1: ( 0, 10, 4)
1211 19:27:07.926064 best DQS0 dly(MCK, UI, PI) = (0, 10, 2)
1212 19:27:07.929119 best DQS1 dly(MCK, UI, PI) = (0, 10, 4)
1213 19:27:07.929561
1214 19:27:07.932464 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 2)
1215 19:27:07.935969 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 4)
1216 19:27:07.980491 [Gating] SW calibration Done
1217 19:27:07.981059 ==
1218 19:27:07.981401 Dram Type= 6, Freq= 0, CH_0, rank 1
1219 19:27:07.982100 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1220 19:27:07.982472 ==
1221 19:27:07.982780 RX Vref Scan: 0
1222 19:27:07.983073
1223 19:27:07.983357 RX Vref 0 -> 0, step: 1
1224 19:27:07.983640
1225 19:27:07.983916 RX Delay -130 -> 252, step: 16
1226 19:27:07.984193 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1227 19:27:07.984469 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1228 19:27:07.984805 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1229 19:27:07.985094 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1230 19:27:07.985372 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1231 19:27:07.985647 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1232 19:27:07.990089 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1233 19:27:07.990571 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1234 19:27:07.993881 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1235 19:27:07.996936 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1236 19:27:07.997416 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1237 19:27:08.003616 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1238 19:27:08.006578 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1239 19:27:08.010241 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1240 19:27:08.013649 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1241 19:27:08.020278 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1242 19:27:08.020737 ==
1243 19:27:08.023737 Dram Type= 6, Freq= 0, CH_0, rank 1
1244 19:27:08.027174 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1245 19:27:08.027657 ==
1246 19:27:08.028136 DQS Delay:
1247 19:27:08.029962 DQS0 = 0, DQS1 = 0
1248 19:27:08.030689 DQM Delay:
1249 19:27:08.033519 DQM0 = 88, DQM1 = 75
1250 19:27:08.034006 DQ Delay:
1251 19:27:08.037015 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1252 19:27:08.040145 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =101
1253 19:27:08.043441 DQ8 =61, DQ9 =53, DQ10 =77, DQ11 =69
1254 19:27:08.047273 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1255 19:27:08.047814
1256 19:27:08.048297
1257 19:27:08.048796 ==
1258 19:27:08.050687 Dram Type= 6, Freq= 0, CH_0, rank 1
1259 19:27:08.053641 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1260 19:27:08.054280 ==
1261 19:27:08.054777
1262 19:27:08.055225
1263 19:27:08.056720 TX Vref Scan disable
1264 19:27:08.060328 == TX Byte 0 ==
1265 19:27:08.063688 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1266 19:27:08.067419 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1267 19:27:08.070197 == TX Byte 1 ==
1268 19:27:08.073520 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1269 19:27:08.077164 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1270 19:27:08.077730 ==
1271 19:27:08.080077 Dram Type= 6, Freq= 0, CH_0, rank 1
1272 19:27:08.086673 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1273 19:27:08.087248 ==
1274 19:27:08.098147 TX Vref=22, minBit 1, minWin=27, winSum=446
1275 19:27:08.101503 TX Vref=24, minBit 0, minWin=28, winSum=453
1276 19:27:08.104729 TX Vref=26, minBit 0, minWin=28, winSum=456
1277 19:27:08.108722 TX Vref=28, minBit 2, minWin=28, winSum=458
1278 19:27:08.112919 TX Vref=30, minBit 2, minWin=28, winSum=459
1279 19:27:08.115622 TX Vref=32, minBit 2, minWin=28, winSum=458
1280 19:27:08.122961 [TxChooseVref] Worse bit 2, Min win 28, Win sum 459, Final Vref 30
1281 19:27:08.123431
1282 19:27:08.126356 Final TX Range 1 Vref 30
1283 19:27:08.126822
1284 19:27:08.127182 ==
1285 19:27:08.129464 Dram Type= 6, Freq= 0, CH_0, rank 1
1286 19:27:08.133032 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1287 19:27:08.133520 ==
1288 19:27:08.133925
1289 19:27:08.134529
1290 19:27:08.136637 TX Vref Scan disable
1291 19:27:08.137116 == TX Byte 0 ==
1292 19:27:08.143299 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1293 19:27:08.146825 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1294 19:27:08.147407 == TX Byte 1 ==
1295 19:27:08.153524 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1296 19:27:08.156906 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1297 19:27:08.157342
1298 19:27:08.157775 [DATLAT]
1299 19:27:08.160145 Freq=800, CH0 RK1
1300 19:27:08.160693
1301 19:27:08.161135 DATLAT Default: 0x9
1302 19:27:08.163148 0, 0xFFFF, sum = 0
1303 19:27:08.163591 1, 0xFFFF, sum = 0
1304 19:27:08.166491 2, 0xFFFF, sum = 0
1305 19:27:08.166929 3, 0xFFFF, sum = 0
1306 19:27:08.170128 4, 0xFFFF, sum = 0
1307 19:27:08.170567 5, 0xFFFF, sum = 0
1308 19:27:08.173785 6, 0xFFFF, sum = 0
1309 19:27:08.174406 7, 0xFFFF, sum = 0
1310 19:27:08.177115 8, 0x0, sum = 1
1311 19:27:08.177629 9, 0x0, sum = 2
1312 19:27:08.180588 10, 0x0, sum = 3
1313 19:27:08.181025 11, 0x0, sum = 4
1314 19:27:08.183770 best_step = 9
1315 19:27:08.184288
1316 19:27:08.184729 ==
1317 19:27:08.186898 Dram Type= 6, Freq= 0, CH_0, rank 1
1318 19:27:08.190238 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1319 19:27:08.190763 ==
1320 19:27:08.191205 RX Vref Scan: 0
1321 19:27:08.193389
1322 19:27:08.193864 RX Vref 0 -> 0, step: 1
1323 19:27:08.194343
1324 19:27:08.196895 RX Delay -111 -> 252, step: 8
1325 19:27:08.203225 iDelay=217, Bit 0, Center 80 (-39 ~ 200) 240
1326 19:27:08.207010 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1327 19:27:08.210063 iDelay=217, Bit 2, Center 80 (-39 ~ 200) 240
1328 19:27:08.213370 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1329 19:27:08.216795 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1330 19:27:08.223355 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1331 19:27:08.226580 iDelay=217, Bit 6, Center 96 (-23 ~ 216) 240
1332 19:27:08.229882 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1333 19:27:08.232911 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1334 19:27:08.236791 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1335 19:27:08.242944 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1336 19:27:08.246171 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1337 19:27:08.249905 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1338 19:27:08.253206 iDelay=217, Bit 13, Center 80 (-39 ~ 200) 240
1339 19:27:08.256103 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1340 19:27:08.262890 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1341 19:27:08.263408 ==
1342 19:27:08.266453 Dram Type= 6, Freq= 0, CH_0, rank 1
1343 19:27:08.269863 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1344 19:27:08.270331 ==
1345 19:27:08.270773 DQS Delay:
1346 19:27:08.272846 DQS0 = 0, DQS1 = 0
1347 19:27:08.273340 DQM Delay:
1348 19:27:08.276431 DQM0 = 85, DQM1 = 74
1349 19:27:08.276851 DQ Delay:
1350 19:27:08.279899 DQ0 =80, DQ1 =88, DQ2 =80, DQ3 =80
1351 19:27:08.282869 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1352 19:27:08.286131 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1353 19:27:08.290179 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =84
1354 19:27:08.290806
1355 19:27:08.291154
1356 19:27:08.296428 [DQSOSCAuto] RK1, (LSB)MR18= 0x3f3f, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
1357 19:27:08.299373 CH0 RK1: MR19=606, MR18=3F3F
1358 19:27:08.306097 CH0_RK1: MR19=0x606, MR18=0x3F3F, DQSOSC=393, MR23=63, INC=95, DEC=63
1359 19:27:08.309446 [RxdqsGatingPostProcess] freq 800
1360 19:27:08.316041 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1361 19:27:08.319505 Pre-setting of DQS Precalculation
1362 19:27:08.323150 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1363 19:27:08.323570 ==
1364 19:27:08.326454 Dram Type= 6, Freq= 0, CH_1, rank 0
1365 19:27:08.329436 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1366 19:27:08.329858 ==
1367 19:27:08.336266 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1368 19:27:08.342780 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1369 19:27:08.351564 [CA 0] Center 37 (6~68) winsize 63
1370 19:27:08.354198 [CA 1] Center 37 (6~68) winsize 63
1371 19:27:08.357521 [CA 2] Center 34 (4~65) winsize 62
1372 19:27:08.360857 [CA 3] Center 34 (4~65) winsize 62
1373 19:27:08.364074 [CA 4] Center 33 (3~64) winsize 62
1374 19:27:08.367486 [CA 5] Center 33 (3~64) winsize 62
1375 19:27:08.367793
1376 19:27:08.370524 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1377 19:27:08.370821
1378 19:27:08.373878 [CATrainingPosCal] consider 1 rank data
1379 19:27:08.377455 u2DelayCellTimex100 = 270/100 ps
1380 19:27:08.380800 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1381 19:27:08.384297 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1382 19:27:08.390674 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1383 19:27:08.394391 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1384 19:27:08.398116 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1385 19:27:08.400806 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1386 19:27:08.401275
1387 19:27:08.404457 CA PerBit enable=1, Macro0, CA PI delay=33
1388 19:27:08.404918
1389 19:27:08.407451 [CBTSetCACLKResult] CA Dly = 33
1390 19:27:08.407911 CS Dly: 5 (0~36)
1391 19:27:08.408298 ==
1392 19:27:08.410646 Dram Type= 6, Freq= 0, CH_1, rank 1
1393 19:27:08.417245 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1394 19:27:08.417729 ==
1395 19:27:08.421406 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1396 19:27:08.427426 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1397 19:27:08.436444 [CA 0] Center 37 (6~68) winsize 63
1398 19:27:08.439726 [CA 1] Center 37 (6~68) winsize 63
1399 19:27:08.443129 [CA 2] Center 34 (4~65) winsize 62
1400 19:27:08.446535 [CA 3] Center 34 (4~65) winsize 62
1401 19:27:08.449803 [CA 4] Center 33 (3~64) winsize 62
1402 19:27:08.453322 [CA 5] Center 33 (3~64) winsize 62
1403 19:27:08.453736
1404 19:27:08.456664 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1405 19:27:08.457074
1406 19:27:08.460549 [CATrainingPosCal] consider 2 rank data
1407 19:27:08.463293 u2DelayCellTimex100 = 270/100 ps
1408 19:27:08.466783 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1409 19:27:08.469921 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1410 19:27:08.476568 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1411 19:27:08.479935 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1412 19:27:08.483475 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1413 19:27:08.486702 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1414 19:27:08.487119
1415 19:27:08.489933 CA PerBit enable=1, Macro0, CA PI delay=33
1416 19:27:08.490390
1417 19:27:08.493462 [CBTSetCACLKResult] CA Dly = 33
1418 19:27:08.493878 CS Dly: 5 (0~36)
1419 19:27:08.494329
1420 19:27:08.496798 ----->DramcWriteLeveling(PI) begin...
1421 19:27:08.497222 ==
1422 19:27:08.499894 Dram Type= 6, Freq= 0, CH_1, rank 0
1423 19:27:08.506470 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1424 19:27:08.506888 ==
1425 19:27:08.509989 Write leveling (Byte 0): 25 => 25
1426 19:27:08.513161 Write leveling (Byte 1): 26 => 26
1427 19:27:08.513767 DramcWriteLeveling(PI) end<-----
1428 19:27:08.516450
1429 19:27:08.516894 ==
1430 19:27:08.520304 Dram Type= 6, Freq= 0, CH_1, rank 0
1431 19:27:08.523107 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1432 19:27:08.523535 ==
1433 19:27:08.526739 [Gating] SW mode calibration
1434 19:27:08.533237 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1435 19:27:08.537082 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1436 19:27:08.543494 0 6 0 | B1->B0 | 2f2f 2525 | 1 0 | (1 0) (0 0)
1437 19:27:08.546356 0 6 4 | B1->B0 | 2525 2323 | 1 0 | (1 0) (0 0)
1438 19:27:08.549915 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1439 19:27:08.556757 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1440 19:27:08.560518 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1441 19:27:08.563107 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1442 19:27:08.569709 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1443 19:27:08.573056 0 6 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1444 19:27:08.577062 0 7 0 | B1->B0 | 2d2d 4242 | 0 0 | (0 0) (0 0)
1445 19:27:08.583047 0 7 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1446 19:27:08.586249 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1447 19:27:08.590200 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1448 19:27:08.596662 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1449 19:27:08.599880 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1450 19:27:08.603286 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1451 19:27:08.609967 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1452 19:27:08.612806 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1453 19:27:08.616646 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1454 19:27:08.622652 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1455 19:27:08.626233 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1456 19:27:08.629578 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1457 19:27:08.632865 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1458 19:27:08.639549 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1459 19:27:08.643101 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1460 19:27:08.646178 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1461 19:27:08.652795 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1462 19:27:08.656400 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1463 19:27:08.659399 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1464 19:27:08.666459 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1465 19:27:08.669875 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1466 19:27:08.672947 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1467 19:27:08.679648 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1468 19:27:08.683010 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1469 19:27:08.686165 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1470 19:27:08.689594 Total UI for P1: 0, mck2ui 16
1471 19:27:08.692700 best dqsien dly found for B0: ( 0, 9, 30)
1472 19:27:08.696616 Total UI for P1: 0, mck2ui 16
1473 19:27:08.699525 best dqsien dly found for B1: ( 0, 9, 30)
1474 19:27:08.702771 best DQS0 dly(MCK, UI, PI) = (0, 9, 30)
1475 19:27:08.706436 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1476 19:27:08.706997
1477 19:27:08.712965 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 30)
1478 19:27:08.715863 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1479 19:27:08.719402 [Gating] SW calibration Done
1480 19:27:08.720002 ==
1481 19:27:08.722633 Dram Type= 6, Freq= 0, CH_1, rank 0
1482 19:27:08.726432 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1483 19:27:08.727011 ==
1484 19:27:08.727371 RX Vref Scan: 0
1485 19:27:08.727704
1486 19:27:08.729079 RX Vref 0 -> 0, step: 1
1487 19:27:08.729721
1488 19:27:08.732805 RX Delay -130 -> 252, step: 16
1489 19:27:08.736147 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1490 19:27:08.739364 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1491 19:27:08.745706 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1492 19:27:08.749299 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1493 19:27:08.752531 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1494 19:27:08.755499 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1495 19:27:08.758980 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1496 19:27:08.766014 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1497 19:27:08.769594 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1498 19:27:08.773001 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1499 19:27:08.776267 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1500 19:27:08.780176 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1501 19:27:08.783722 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1502 19:27:08.787251 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1503 19:27:08.793813 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1504 19:27:08.797665 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1505 19:27:08.798155 ==
1506 19:27:08.801340 Dram Type= 6, Freq= 0, CH_1, rank 0
1507 19:27:08.805089 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1508 19:27:08.805615 ==
1509 19:27:08.806003 DQS Delay:
1510 19:27:08.808349 DQS0 = 0, DQS1 = 0
1511 19:27:08.808843 DQM Delay:
1512 19:27:08.811585 DQM0 = 81, DQM1 = 74
1513 19:27:08.812131 DQ Delay:
1514 19:27:08.815070 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1515 19:27:08.818599 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1516 19:27:08.821907 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =69
1517 19:27:08.825341 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =85
1518 19:27:08.825846
1519 19:27:08.826274
1520 19:27:08.826614 ==
1521 19:27:08.828107 Dram Type= 6, Freq= 0, CH_1, rank 0
1522 19:27:08.831466 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1523 19:27:08.831915 ==
1524 19:27:08.832239
1525 19:27:08.832565
1526 19:27:08.834975 TX Vref Scan disable
1527 19:27:08.838398 == TX Byte 0 ==
1528 19:27:08.842074 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1529 19:27:08.845241 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1530 19:27:08.847973 == TX Byte 1 ==
1531 19:27:08.851740 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1532 19:27:08.854708 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1533 19:27:08.855144 ==
1534 19:27:08.858120 Dram Type= 6, Freq= 0, CH_1, rank 0
1535 19:27:08.861595 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1536 19:27:08.864454 ==
1537 19:27:08.875875 TX Vref=22, minBit 3, minWin=27, winSum=445
1538 19:27:08.879402 TX Vref=24, minBit 3, minWin=27, winSum=448
1539 19:27:08.882494 TX Vref=26, minBit 0, minWin=28, winSum=452
1540 19:27:08.885810 TX Vref=28, minBit 3, minWin=27, winSum=452
1541 19:27:08.889525 TX Vref=30, minBit 0, minWin=28, winSum=459
1542 19:27:08.895781 TX Vref=32, minBit 9, minWin=27, winSum=454
1543 19:27:08.899119 [TxChooseVref] Worse bit 0, Min win 28, Win sum 459, Final Vref 30
1544 19:27:08.899539
1545 19:27:08.902481 Final TX Range 1 Vref 30
1546 19:27:08.902892
1547 19:27:08.903214 ==
1548 19:27:08.905669 Dram Type= 6, Freq= 0, CH_1, rank 0
1549 19:27:08.909096 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1550 19:27:08.909512 ==
1551 19:27:08.912409
1552 19:27:08.912819
1553 19:27:08.913139 TX Vref Scan disable
1554 19:27:08.915920 == TX Byte 0 ==
1555 19:27:08.919269 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1556 19:27:08.922468 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1557 19:27:08.926112 == TX Byte 1 ==
1558 19:27:08.929102 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1559 19:27:08.932456 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1560 19:27:08.935849
1561 19:27:08.936266 [DATLAT]
1562 19:27:08.936595 Freq=800, CH1 RK0
1563 19:27:08.936899
1564 19:27:08.939083 DATLAT Default: 0xa
1565 19:27:08.939495 0, 0xFFFF, sum = 0
1566 19:27:08.942473 1, 0xFFFF, sum = 0
1567 19:27:08.942890 2, 0xFFFF, sum = 0
1568 19:27:08.945872 3, 0xFFFF, sum = 0
1569 19:27:08.946342 4, 0xFFFF, sum = 0
1570 19:27:08.949602 5, 0xFFFF, sum = 0
1571 19:27:08.950128 6, 0xFFFF, sum = 0
1572 19:27:08.952437 7, 0xFFFF, sum = 0
1573 19:27:08.952991 8, 0x0, sum = 1
1574 19:27:08.955810 9, 0x0, sum = 2
1575 19:27:08.956238 10, 0x0, sum = 3
1576 19:27:08.959263 11, 0x0, sum = 4
1577 19:27:08.959676 best_step = 9
1578 19:27:08.959993
1579 19:27:08.960288 ==
1580 19:27:08.962326 Dram Type= 6, Freq= 0, CH_1, rank 0
1581 19:27:08.969178 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1582 19:27:08.969662 ==
1583 19:27:08.969989 RX Vref Scan: 1
1584 19:27:08.970346
1585 19:27:08.972574 Set Vref Range= 32 -> 127
1586 19:27:08.972983
1587 19:27:08.975633 RX Vref 32 -> 127, step: 1
1588 19:27:08.976047
1589 19:27:08.976366 RX Delay -111 -> 252, step: 8
1590 19:27:08.979072
1591 19:27:08.979502 Set Vref, RX VrefLevel [Byte0]: 32
1592 19:27:08.982502 [Byte1]: 32
1593 19:27:08.986682
1594 19:27:08.987122 Set Vref, RX VrefLevel [Byte0]: 33
1595 19:27:08.990482 [Byte1]: 33
1596 19:27:08.994364
1597 19:27:08.994805 Set Vref, RX VrefLevel [Byte0]: 34
1598 19:27:08.997929 [Byte1]: 34
1599 19:27:09.002211
1600 19:27:09.002692 Set Vref, RX VrefLevel [Byte0]: 35
1601 19:27:09.005615 [Byte1]: 35
1602 19:27:09.009832
1603 19:27:09.010290 Set Vref, RX VrefLevel [Byte0]: 36
1604 19:27:09.012877 [Byte1]: 36
1605 19:27:09.018054
1606 19:27:09.018477 Set Vref, RX VrefLevel [Byte0]: 37
1607 19:27:09.020637 [Byte1]: 37
1608 19:27:09.025279
1609 19:27:09.025718 Set Vref, RX VrefLevel [Byte0]: 38
1610 19:27:09.028336 [Byte1]: 38
1611 19:27:09.032944
1612 19:27:09.033352 Set Vref, RX VrefLevel [Byte0]: 39
1613 19:27:09.035649 [Byte1]: 39
1614 19:27:09.040504
1615 19:27:09.040936 Set Vref, RX VrefLevel [Byte0]: 40
1616 19:27:09.043870 [Byte1]: 40
1617 19:27:09.047770
1618 19:27:09.048179 Set Vref, RX VrefLevel [Byte0]: 41
1619 19:27:09.051115 [Byte1]: 41
1620 19:27:09.055524
1621 19:27:09.055931 Set Vref, RX VrefLevel [Byte0]: 42
1622 19:27:09.059117 [Byte1]: 42
1623 19:27:09.063491
1624 19:27:09.063900 Set Vref, RX VrefLevel [Byte0]: 43
1625 19:27:09.067205 [Byte1]: 43
1626 19:27:09.071026
1627 19:27:09.071459 Set Vref, RX VrefLevel [Byte0]: 44
1628 19:27:09.074425 [Byte1]: 44
1629 19:27:09.078620
1630 19:27:09.079103 Set Vref, RX VrefLevel [Byte0]: 45
1631 19:27:09.081923 [Byte1]: 45
1632 19:27:09.086651
1633 19:27:09.087060 Set Vref, RX VrefLevel [Byte0]: 46
1634 19:27:09.089779 [Byte1]: 46
1635 19:27:09.093666
1636 19:27:09.094220 Set Vref, RX VrefLevel [Byte0]: 47
1637 19:27:09.097070 [Byte1]: 47
1638 19:27:09.101749
1639 19:27:09.102313 Set Vref, RX VrefLevel [Byte0]: 48
1640 19:27:09.104805 [Byte1]: 48
1641 19:27:09.109271
1642 19:27:09.109683 Set Vref, RX VrefLevel [Byte0]: 49
1643 19:27:09.112682 [Byte1]: 49
1644 19:27:09.117229
1645 19:27:09.117906 Set Vref, RX VrefLevel [Byte0]: 50
1646 19:27:09.120103 [Byte1]: 50
1647 19:27:09.124662
1648 19:27:09.125114 Set Vref, RX VrefLevel [Byte0]: 51
1649 19:27:09.127785 [Byte1]: 51
1650 19:27:09.131854
1651 19:27:09.132304 Set Vref, RX VrefLevel [Byte0]: 52
1652 19:27:09.135316 [Byte1]: 52
1653 19:27:09.139996
1654 19:27:09.140453 Set Vref, RX VrefLevel [Byte0]: 53
1655 19:27:09.143206 [Byte1]: 53
1656 19:27:09.147366
1657 19:27:09.147930 Set Vref, RX VrefLevel [Byte0]: 54
1658 19:27:09.150691 [Byte1]: 54
1659 19:27:09.154848
1660 19:27:09.155299 Set Vref, RX VrefLevel [Byte0]: 55
1661 19:27:09.158261 [Byte1]: 55
1662 19:27:09.162733
1663 19:27:09.163155 Set Vref, RX VrefLevel [Byte0]: 56
1664 19:27:09.165971 [Byte1]: 56
1665 19:27:09.170669
1666 19:27:09.171159 Set Vref, RX VrefLevel [Byte0]: 57
1667 19:27:09.173463 [Byte1]: 57
1668 19:27:09.178162
1669 19:27:09.178641 Set Vref, RX VrefLevel [Byte0]: 58
1670 19:27:09.181375 [Byte1]: 58
1671 19:27:09.186140
1672 19:27:09.186662 Set Vref, RX VrefLevel [Byte0]: 59
1673 19:27:09.188999 [Byte1]: 59
1674 19:27:09.193477
1675 19:27:09.193985 Set Vref, RX VrefLevel [Byte0]: 60
1676 19:27:09.196515 [Byte1]: 60
1677 19:27:09.201062
1678 19:27:09.201551 Set Vref, RX VrefLevel [Byte0]: 61
1679 19:27:09.204319 [Byte1]: 61
1680 19:27:09.208569
1681 19:27:09.209075 Set Vref, RX VrefLevel [Byte0]: 62
1682 19:27:09.212008 [Byte1]: 62
1683 19:27:09.216310
1684 19:27:09.216925 Set Vref, RX VrefLevel [Byte0]: 63
1685 19:27:09.219650 [Byte1]: 63
1686 19:27:09.223644
1687 19:27:09.224056 Set Vref, RX VrefLevel [Byte0]: 64
1688 19:27:09.227045 [Byte1]: 64
1689 19:27:09.231341
1690 19:27:09.231752 Set Vref, RX VrefLevel [Byte0]: 65
1691 19:27:09.234850 [Byte1]: 65
1692 19:27:09.238972
1693 19:27:09.239403 Set Vref, RX VrefLevel [Byte0]: 66
1694 19:27:09.242493 [Byte1]: 66
1695 19:27:09.246831
1696 19:27:09.247287 Set Vref, RX VrefLevel [Byte0]: 67
1697 19:27:09.250315 [Byte1]: 67
1698 19:27:09.254693
1699 19:27:09.255182 Set Vref, RX VrefLevel [Byte0]: 68
1700 19:27:09.258082 [Byte1]: 68
1701 19:27:09.262074
1702 19:27:09.262600 Set Vref, RX VrefLevel [Byte0]: 69
1703 19:27:09.265438 [Byte1]: 69
1704 19:27:09.269656
1705 19:27:09.270313 Set Vref, RX VrefLevel [Byte0]: 70
1706 19:27:09.273011 [Byte1]: 70
1707 19:27:09.277426
1708 19:27:09.277926 Set Vref, RX VrefLevel [Byte0]: 71
1709 19:27:09.280820 [Byte1]: 71
1710 19:27:09.285339
1711 19:27:09.285861 Set Vref, RX VrefLevel [Byte0]: 72
1712 19:27:09.288755 [Byte1]: 72
1713 19:27:09.292882
1714 19:27:09.293343 Set Vref, RX VrefLevel [Byte0]: 73
1715 19:27:09.295807 [Byte1]: 73
1716 19:27:09.300593
1717 19:27:09.301077 Set Vref, RX VrefLevel [Byte0]: 74
1718 19:27:09.304131 [Byte1]: 74
1719 19:27:09.308309
1720 19:27:09.308731 Set Vref, RX VrefLevel [Byte0]: 75
1721 19:27:09.311480 [Byte1]: 75
1722 19:27:09.315935
1723 19:27:09.316469 Final RX Vref Byte 0 = 58 to rank0
1724 19:27:09.318914 Final RX Vref Byte 1 = 57 to rank0
1725 19:27:09.322515 Final RX Vref Byte 0 = 58 to rank1
1726 19:27:09.325363 Final RX Vref Byte 1 = 57 to rank1==
1727 19:27:09.328872 Dram Type= 6, Freq= 0, CH_1, rank 0
1728 19:27:09.335822 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1729 19:27:09.336252 ==
1730 19:27:09.336582 DQS Delay:
1731 19:27:09.336917 DQS0 = 0, DQS1 = 0
1732 19:27:09.338761 DQM Delay:
1733 19:27:09.339192 DQM0 = 81, DQM1 = 74
1734 19:27:09.342508 DQ Delay:
1735 19:27:09.345498 DQ0 =84, DQ1 =76, DQ2 =72, DQ3 =76
1736 19:27:09.345931 DQ4 =80, DQ5 =92, DQ6 =88, DQ7 =80
1737 19:27:09.349214 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =64
1738 19:27:09.352907 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =84
1739 19:27:09.353337
1740 19:27:09.353877
1741 19:27:09.363168 [DQSOSCAuto] RK0, (LSB)MR18= 0x4e4e, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
1742 19:27:09.366761 CH1 RK0: MR19=606, MR18=4E4E
1743 19:27:09.369959 CH1_RK0: MR19=0x606, MR18=0x4E4E, DQSOSC=390, MR23=63, INC=97, DEC=64
1744 19:27:09.370524
1745 19:27:09.373411 ----->DramcWriteLeveling(PI) begin...
1746 19:27:09.376488 ==
1747 19:27:09.380268 Dram Type= 6, Freq= 0, CH_1, rank 1
1748 19:27:09.383119 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1749 19:27:09.383584 ==
1750 19:27:09.386340 Write leveling (Byte 0): 27 => 27
1751 19:27:09.389755 Write leveling (Byte 1): 24 => 24
1752 19:27:09.393015 DramcWriteLeveling(PI) end<-----
1753 19:27:09.393540
1754 19:27:09.393905 ==
1755 19:27:09.396287 Dram Type= 6, Freq= 0, CH_1, rank 1
1756 19:27:09.399526 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1757 19:27:09.399988 ==
1758 19:27:09.403014 [Gating] SW mode calibration
1759 19:27:09.410161 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1760 19:27:09.413129 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1761 19:27:09.419751 0 6 0 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
1762 19:27:09.423162 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1763 19:27:09.426402 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1764 19:27:09.432939 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1765 19:27:09.436275 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1766 19:27:09.439643 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1767 19:27:09.446197 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1768 19:27:09.449886 0 6 28 | B1->B0 | 2323 3030 | 0 1 | (0 0) (0 0)
1769 19:27:09.453151 0 7 0 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
1770 19:27:09.459475 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1771 19:27:09.462979 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1772 19:27:09.466456 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1773 19:27:09.472694 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1774 19:27:09.476004 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1775 19:27:09.479356 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1776 19:27:09.485810 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1777 19:27:09.489762 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1778 19:27:09.493268 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1779 19:27:09.499388 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1780 19:27:09.502669 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1781 19:27:09.505957 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1782 19:27:09.512919 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1783 19:27:09.516300 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1784 19:27:09.519407 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1785 19:27:09.525978 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1786 19:27:09.529400 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1787 19:27:09.532617 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1788 19:27:09.536305 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1789 19:27:09.542592 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1790 19:27:09.546415 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1791 19:27:09.549281 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1792 19:27:09.555941 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1793 19:27:09.559240 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1794 19:27:09.563165 Total UI for P1: 0, mck2ui 16
1795 19:27:09.566092 best dqsien dly found for B0: ( 0, 9, 26)
1796 19:27:09.569490 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1797 19:27:09.573386 Total UI for P1: 0, mck2ui 16
1798 19:27:09.576238 best dqsien dly found for B1: ( 0, 10, 0)
1799 19:27:09.579288 best DQS0 dly(MCK, UI, PI) = (0, 9, 26)
1800 19:27:09.583289 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1801 19:27:09.583749
1802 19:27:09.589758 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 26)
1803 19:27:09.592840 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1804 19:27:09.593355 [Gating] SW calibration Done
1805 19:27:09.596009 ==
1806 19:27:09.599360 Dram Type= 6, Freq= 0, CH_1, rank 1
1807 19:27:09.603273 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1808 19:27:09.603759 ==
1809 19:27:09.604197 RX Vref Scan: 0
1810 19:27:09.604724
1811 19:27:09.606249 RX Vref 0 -> 0, step: 1
1812 19:27:09.606702
1813 19:27:09.609471 RX Delay -130 -> 252, step: 16
1814 19:27:09.612944 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1815 19:27:09.616249 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1816 19:27:09.622822 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1817 19:27:09.626147 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1818 19:27:09.629476 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1819 19:27:09.633027 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1820 19:27:09.635929 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1821 19:27:09.639047 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1822 19:27:09.645521 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1823 19:27:09.648976 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1824 19:27:09.652266 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1825 19:27:09.656364 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1826 19:27:09.662532 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1827 19:27:09.665911 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1828 19:27:09.669899 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1829 19:27:09.672924 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1830 19:27:09.673528 ==
1831 19:27:09.675886 Dram Type= 6, Freq= 0, CH_1, rank 1
1832 19:27:09.679760 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1833 19:27:09.682771 ==
1834 19:27:09.683302 DQS Delay:
1835 19:27:09.683751 DQS0 = 0, DQS1 = 0
1836 19:27:09.686127 DQM Delay:
1837 19:27:09.686579 DQM0 = 85, DQM1 = 72
1838 19:27:09.689330 DQ Delay:
1839 19:27:09.692620 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1840 19:27:09.693237 DQ4 =85, DQ5 =101, DQ6 =85, DQ7 =85
1841 19:27:09.696061 DQ8 =53, DQ9 =61, DQ10 =69, DQ11 =61
1842 19:27:09.699250 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =85
1843 19:27:09.702429
1844 19:27:09.702845
1845 19:27:09.703171 ==
1846 19:27:09.706050 Dram Type= 6, Freq= 0, CH_1, rank 1
1847 19:27:09.709397 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1848 19:27:09.709948 ==
1849 19:27:09.710471
1850 19:27:09.710920
1851 19:27:09.712795 TX Vref Scan disable
1852 19:27:09.713240 == TX Byte 0 ==
1853 19:27:09.719582 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1854 19:27:09.723189 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1855 19:27:09.723598 == TX Byte 1 ==
1856 19:27:09.729469 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1857 19:27:09.732720 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1858 19:27:09.733133 ==
1859 19:27:09.736380 Dram Type= 6, Freq= 0, CH_1, rank 1
1860 19:27:09.739531 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1861 19:27:09.740153 ==
1862 19:27:09.753071 TX Vref=22, minBit 0, minWin=27, winSum=448
1863 19:27:09.756602 TX Vref=24, minBit 0, minWin=28, winSum=452
1864 19:27:09.759609 TX Vref=26, minBit 0, minWin=28, winSum=457
1865 19:27:09.762973 TX Vref=28, minBit 9, minWin=27, winSum=454
1866 19:27:09.766457 TX Vref=30, minBit 9, minWin=27, winSum=454
1867 19:27:09.769624 TX Vref=32, minBit 0, minWin=28, winSum=455
1868 19:27:09.776426 [TxChooseVref] Worse bit 0, Min win 28, Win sum 457, Final Vref 26
1869 19:27:09.776907
1870 19:27:09.779771 Final TX Range 1 Vref 26
1871 19:27:09.780281
1872 19:27:09.780616 ==
1873 19:27:09.782799 Dram Type= 6, Freq= 0, CH_1, rank 1
1874 19:27:09.786610 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1875 19:27:09.787031 ==
1876 19:27:09.787355
1877 19:27:09.789509
1878 19:27:09.789924 TX Vref Scan disable
1879 19:27:09.792933 == TX Byte 0 ==
1880 19:27:09.796694 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1881 19:27:09.802965 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1882 19:27:09.803493 == TX Byte 1 ==
1883 19:27:09.806466 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1884 19:27:09.813275 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1885 19:27:09.813805
1886 19:27:09.814182 [DATLAT]
1887 19:27:09.814496 Freq=800, CH1 RK1
1888 19:27:09.814793
1889 19:27:09.816061 DATLAT Default: 0x9
1890 19:27:09.816494 0, 0xFFFF, sum = 0
1891 19:27:09.819514 1, 0xFFFF, sum = 0
1892 19:27:09.819940 2, 0xFFFF, sum = 0
1893 19:27:09.822667 3, 0xFFFF, sum = 0
1894 19:27:09.826626 4, 0xFFFF, sum = 0
1895 19:27:09.827049 5, 0xFFFF, sum = 0
1896 19:27:09.829734 6, 0xFFFF, sum = 0
1897 19:27:09.830181 7, 0xFFFF, sum = 0
1898 19:27:09.830517 8, 0x0, sum = 1
1899 19:27:09.833011 9, 0x0, sum = 2
1900 19:27:09.833433 10, 0x0, sum = 3
1901 19:27:09.836383 11, 0x0, sum = 4
1902 19:27:09.836901 best_step = 9
1903 19:27:09.837233
1904 19:27:09.837553 ==
1905 19:27:09.839462 Dram Type= 6, Freq= 0, CH_1, rank 1
1906 19:27:09.846373 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1907 19:27:09.846790 ==
1908 19:27:09.847116 RX Vref Scan: 0
1909 19:27:09.847449
1910 19:27:09.849670 RX Vref 0 -> 0, step: 1
1911 19:27:09.850104
1912 19:27:09.852836 RX Delay -111 -> 252, step: 8
1913 19:27:09.856709 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1914 19:27:09.859219 iDelay=217, Bit 1, Center 76 (-39 ~ 192) 232
1915 19:27:09.866407 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
1916 19:27:09.869403 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1917 19:27:09.872465 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1918 19:27:09.876137 iDelay=217, Bit 5, Center 96 (-23 ~ 216) 240
1919 19:27:09.879713 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1920 19:27:09.885843 iDelay=217, Bit 7, Center 80 (-39 ~ 200) 240
1921 19:27:09.889271 iDelay=217, Bit 8, Center 60 (-55 ~ 176) 232
1922 19:27:09.893019 iDelay=217, Bit 9, Center 64 (-55 ~ 184) 240
1923 19:27:09.896155 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1924 19:27:09.899589 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1925 19:27:09.905951 iDelay=217, Bit 12, Center 88 (-31 ~ 208) 240
1926 19:27:09.909074 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1927 19:27:09.913080 iDelay=217, Bit 14, Center 80 (-39 ~ 200) 240
1928 19:27:09.916264 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1929 19:27:09.916886 ==
1930 19:27:09.919446 Dram Type= 6, Freq= 0, CH_1, rank 1
1931 19:27:09.925867 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1932 19:27:09.926358 ==
1933 19:27:09.926712 DQS Delay:
1934 19:27:09.929120 DQS0 = 0, DQS1 = 0
1935 19:27:09.929571 DQM Delay:
1936 19:27:09.929925 DQM0 = 83, DQM1 = 75
1937 19:27:09.932770 DQ Delay:
1938 19:27:09.935822 DQ0 =84, DQ1 =76, DQ2 =76, DQ3 =80
1939 19:27:09.939597 DQ4 =84, DQ5 =96, DQ6 =92, DQ7 =80
1940 19:27:09.942715 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =68
1941 19:27:09.945771 DQ12 =88, DQ13 =84, DQ14 =80, DQ15 =84
1942 19:27:09.946305
1943 19:27:09.946671
1944 19:27:09.952540 [DQSOSCAuto] RK1, (LSB)MR18= 0x3838, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
1945 19:27:09.956197 CH1 RK1: MR19=606, MR18=3838
1946 19:27:09.962957 CH1_RK1: MR19=0x606, MR18=0x3838, DQSOSC=395, MR23=63, INC=94, DEC=63
1947 19:27:09.966509 [RxdqsGatingPostProcess] freq 800
1948 19:27:09.969396 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1949 19:27:09.973028 Pre-setting of DQS Precalculation
1950 19:27:09.979597 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1951 19:27:09.986136 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1952 19:27:09.992666 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1953 19:27:09.993087
1954 19:27:09.993418
1955 19:27:09.995793 [Calibration Summary] 1600 Mbps
1956 19:27:09.996226 CH 0, Rank 0
1957 19:27:09.999440 SW Impedance : PASS
1958 19:27:10.002684 DUTY Scan : NO K
1959 19:27:10.003116 ZQ Calibration : PASS
1960 19:27:10.005659 Jitter Meter : NO K
1961 19:27:10.006227 CBT Training : PASS
1962 19:27:10.009137 Write leveling : PASS
1963 19:27:10.012627 RX DQS gating : PASS
1964 19:27:10.013046 RX DQ/DQS(RDDQC) : PASS
1965 19:27:10.016232 TX DQ/DQS : PASS
1966 19:27:10.019393 RX DATLAT : PASS
1967 19:27:10.019813 RX DQ/DQS(Engine): PASS
1968 19:27:10.022620 TX OE : NO K
1969 19:27:10.023036 All Pass.
1970 19:27:10.023362
1971 19:27:10.025779 CH 0, Rank 1
1972 19:27:10.026234 SW Impedance : PASS
1973 19:27:10.028883 DUTY Scan : NO K
1974 19:27:10.032243 ZQ Calibration : PASS
1975 19:27:10.032716 Jitter Meter : NO K
1976 19:27:10.035975 CBT Training : PASS
1977 19:27:10.039519 Write leveling : PASS
1978 19:27:10.039994 RX DQS gating : PASS
1979 19:27:10.042589 RX DQ/DQS(RDDQC) : PASS
1980 19:27:10.043076 TX DQ/DQS : PASS
1981 19:27:10.045773 RX DATLAT : PASS
1982 19:27:10.049086 RX DQ/DQS(Engine): PASS
1983 19:27:10.049500 TX OE : NO K
1984 19:27:10.052556 All Pass.
1985 19:27:10.052967
1986 19:27:10.053290 CH 1, Rank 0
1987 19:27:10.056234 SW Impedance : PASS
1988 19:27:10.056696 DUTY Scan : NO K
1989 19:27:10.059391 ZQ Calibration : PASS
1990 19:27:10.062170 Jitter Meter : NO K
1991 19:27:10.062587 CBT Training : PASS
1992 19:27:10.066014 Write leveling : PASS
1993 19:27:10.069281 RX DQS gating : PASS
1994 19:27:10.069692 RX DQ/DQS(RDDQC) : PASS
1995 19:27:10.072733 TX DQ/DQS : PASS
1996 19:27:10.076301 RX DATLAT : PASS
1997 19:27:10.076842 RX DQ/DQS(Engine): PASS
1998 19:27:10.079335 TX OE : NO K
1999 19:27:10.079832 All Pass.
2000 19:27:10.080156
2001 19:27:10.082353 CH 1, Rank 1
2002 19:27:10.082766 SW Impedance : PASS
2003 19:27:10.085943 DUTY Scan : NO K
2004 19:27:10.089271 ZQ Calibration : PASS
2005 19:27:10.089684 Jitter Meter : NO K
2006 19:27:10.092142 CBT Training : PASS
2007 19:27:10.092558 Write leveling : PASS
2008 19:27:10.095923 RX DQS gating : PASS
2009 19:27:10.098960 RX DQ/DQS(RDDQC) : PASS
2010 19:27:10.099421 TX DQ/DQS : PASS
2011 19:27:10.102584 RX DATLAT : PASS
2012 19:27:10.105515 RX DQ/DQS(Engine): PASS
2013 19:27:10.105994 TX OE : NO K
2014 19:27:10.109014 All Pass.
2015 19:27:10.109475
2016 19:27:10.109832 DramC Write-DBI off
2017 19:27:10.112053 PER_BANK_REFRESH: Hybrid Mode
2018 19:27:10.115935 TX_TRACKING: ON
2019 19:27:10.118928 [GetDramInforAfterCalByMRR] Vendor 6.
2020 19:27:10.122414 [GetDramInforAfterCalByMRR] Revision 606.
2021 19:27:10.125562 [GetDramInforAfterCalByMRR] Revision 2 0.
2022 19:27:10.126137 MR0 0x3939
2023 19:27:10.126542 MR8 0x1111
2024 19:27:10.132352 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
2025 19:27:10.132800
2026 19:27:10.133161 MR0 0x3939
2027 19:27:10.133465 MR8 0x1111
2028 19:27:10.136093 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
2029 19:27:10.136720
2030 19:27:10.145573 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2031 19:27:10.149063 [FAST_K] Save calibration result to emmc
2032 19:27:10.152127 [FAST_K] Save calibration result to emmc
2033 19:27:10.155554 dram_init: config_dvfs: 1
2034 19:27:10.159145 dramc_set_vcore_voltage set vcore to 662500
2035 19:27:10.162413 Read voltage for 1200, 2
2036 19:27:10.162824 Vio18 = 0
2037 19:27:10.163141 Vcore = 662500
2038 19:27:10.165739 Vdram = 0
2039 19:27:10.166361 Vddq = 0
2040 19:27:10.166694 Vmddr = 0
2041 19:27:10.172311 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2042 19:27:10.175742 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2043 19:27:10.178889 MEM_TYPE=3, freq_sel=15
2044 19:27:10.182365 sv_algorithm_assistance_LP4_1600
2045 19:27:10.185461 ============ PULL DRAM RESETB DOWN ============
2046 19:27:10.188683 ========== PULL DRAM RESETB DOWN end =========
2047 19:27:10.195667 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2048 19:27:10.199046 ===================================
2049 19:27:10.202340 LPDDR4 DRAM CONFIGURATION
2050 19:27:10.202809 ===================================
2051 19:27:10.205539 EX_ROW_EN[0] = 0x0
2052 19:27:10.208867 EX_ROW_EN[1] = 0x0
2053 19:27:10.209434 LP4Y_EN = 0x0
2054 19:27:10.212205 WORK_FSP = 0x0
2055 19:27:10.212931 WL = 0x4
2056 19:27:10.215419 RL = 0x4
2057 19:27:10.216044 BL = 0x2
2058 19:27:10.218932 RPST = 0x0
2059 19:27:10.219541 RD_PRE = 0x0
2060 19:27:10.222443 WR_PRE = 0x1
2061 19:27:10.222956 WR_PST = 0x0
2062 19:27:10.226004 DBI_WR = 0x0
2063 19:27:10.226668 DBI_RD = 0x0
2064 19:27:10.229134 OTF = 0x1
2065 19:27:10.232026 ===================================
2066 19:27:10.235465 ===================================
2067 19:27:10.235955 ANA top config
2068 19:27:10.239098 ===================================
2069 19:27:10.242264 DLL_ASYNC_EN = 0
2070 19:27:10.245139 ALL_SLAVE_EN = 0
2071 19:27:10.248961 NEW_RANK_MODE = 1
2072 19:27:10.249419 DLL_IDLE_MODE = 1
2073 19:27:10.252114 LP45_APHY_COMB_EN = 1
2074 19:27:10.255366 TX_ODT_DIS = 1
2075 19:27:10.258614 NEW_8X_MODE = 1
2076 19:27:10.261754 ===================================
2077 19:27:10.265527 ===================================
2078 19:27:10.268888 data_rate = 2400
2079 19:27:10.269430 CKR = 1
2080 19:27:10.272090 DQ_P2S_RATIO = 8
2081 19:27:10.275476 ===================================
2082 19:27:10.278796 CA_P2S_RATIO = 8
2083 19:27:10.281954 DQ_CA_OPEN = 0
2084 19:27:10.285096 DQ_SEMI_OPEN = 0
2085 19:27:10.288897 CA_SEMI_OPEN = 0
2086 19:27:10.289441 CA_FULL_RATE = 0
2087 19:27:10.291607 DQ_CKDIV4_EN = 0
2088 19:27:10.295015 CA_CKDIV4_EN = 0
2089 19:27:10.298493 CA_PREDIV_EN = 0
2090 19:27:10.301901 PH8_DLY = 17
2091 19:27:10.305349 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2092 19:27:10.305911 DQ_AAMCK_DIV = 4
2093 19:27:10.308628 CA_AAMCK_DIV = 4
2094 19:27:10.311998 CA_ADMCK_DIV = 4
2095 19:27:10.315251 DQ_TRACK_CA_EN = 0
2096 19:27:10.318290 CA_PICK = 1200
2097 19:27:10.322014 CA_MCKIO = 1200
2098 19:27:10.325138 MCKIO_SEMI = 0
2099 19:27:10.325682 PLL_FREQ = 2366
2100 19:27:10.328320 DQ_UI_PI_RATIO = 32
2101 19:27:10.331513 CA_UI_PI_RATIO = 0
2102 19:27:10.335243 ===================================
2103 19:27:10.338753 ===================================
2104 19:27:10.341875 memory_type:LPDDR4
2105 19:27:10.342376 GP_NUM : 10
2106 19:27:10.344906 SRAM_EN : 1
2107 19:27:10.348174 MD32_EN : 0
2108 19:27:10.352065 ===================================
2109 19:27:10.352521 [ANA_INIT] >>>>>>>>>>>>>>
2110 19:27:10.355312 <<<<<< [CONFIGURE PHASE]: ANA_TX
2111 19:27:10.358129 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2112 19:27:10.361513 ===================================
2113 19:27:10.365062 data_rate = 2400,PCW = 0X5b00
2114 19:27:10.368427 ===================================
2115 19:27:10.372123 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2116 19:27:10.378009 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2117 19:27:10.381647 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2118 19:27:10.388398 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2119 19:27:10.391275 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2120 19:27:10.394649 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2121 19:27:10.398315 [ANA_INIT] flow start
2122 19:27:10.398727 [ANA_INIT] PLL >>>>>>>>
2123 19:27:10.401601 [ANA_INIT] PLL <<<<<<<<
2124 19:27:10.404547 [ANA_INIT] MIDPI >>>>>>>>
2125 19:27:10.405035 [ANA_INIT] MIDPI <<<<<<<<
2126 19:27:10.408593 [ANA_INIT] DLL >>>>>>>>
2127 19:27:10.411731 [ANA_INIT] DLL <<<<<<<<
2128 19:27:10.412144 [ANA_INIT] flow end
2129 19:27:10.414829 ============ LP4 DIFF to SE enter ============
2130 19:27:10.421404 ============ LP4 DIFF to SE exit ============
2131 19:27:10.421929 [ANA_INIT] <<<<<<<<<<<<<
2132 19:27:10.424729 [Flow] Enable top DCM control >>>>>
2133 19:27:10.428276 [Flow] Enable top DCM control <<<<<
2134 19:27:10.431453 Enable DLL master slave shuffle
2135 19:27:10.437791 ==============================================================
2136 19:27:10.438241 Gating Mode config
2137 19:27:10.444577 ==============================================================
2138 19:27:10.447993 Config description:
2139 19:27:10.457719 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2140 19:27:10.464313 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2141 19:27:10.467587 SELPH_MODE 0: By rank 1: By Phase
2142 19:27:10.474455 ==============================================================
2143 19:27:10.477661 GAT_TRACK_EN = 1
2144 19:27:10.481158 RX_GATING_MODE = 2
2145 19:27:10.481710 RX_GATING_TRACK_MODE = 2
2146 19:27:10.484779 SELPH_MODE = 1
2147 19:27:10.487857 PICG_EARLY_EN = 1
2148 19:27:10.491089 VALID_LAT_VALUE = 1
2149 19:27:10.497509 ==============================================================
2150 19:27:10.501087 Enter into Gating configuration >>>>
2151 19:27:10.504302 Exit from Gating configuration <<<<
2152 19:27:10.507671 Enter into DVFS_PRE_config >>>>>
2153 19:27:10.517932 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2154 19:27:10.521196 Exit from DVFS_PRE_config <<<<<
2155 19:27:10.523940 Enter into PICG configuration >>>>
2156 19:27:10.527451 Exit from PICG configuration <<<<
2157 19:27:10.531062 [RX_INPUT] configuration >>>>>
2158 19:27:10.534267 [RX_INPUT] configuration <<<<<
2159 19:27:10.537423 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2160 19:27:10.544716 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2161 19:27:10.551075 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2162 19:27:10.557293 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2163 19:27:10.560845 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2164 19:27:10.567322 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2165 19:27:10.570661 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2166 19:27:10.577590 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2167 19:27:10.580835 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2168 19:27:10.584109 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2169 19:27:10.587689 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2170 19:27:10.594256 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2171 19:27:10.597081 ===================================
2172 19:27:10.597496 LPDDR4 DRAM CONFIGURATION
2173 19:27:10.600763 ===================================
2174 19:27:10.603933 EX_ROW_EN[0] = 0x0
2175 19:27:10.607518 EX_ROW_EN[1] = 0x0
2176 19:27:10.607929 LP4Y_EN = 0x0
2177 19:27:10.610451 WORK_FSP = 0x0
2178 19:27:10.610864 WL = 0x4
2179 19:27:10.614390 RL = 0x4
2180 19:27:10.614801 BL = 0x2
2181 19:27:10.617306 RPST = 0x0
2182 19:27:10.617717 RD_PRE = 0x0
2183 19:27:10.620675 WR_PRE = 0x1
2184 19:27:10.621085 WR_PST = 0x0
2185 19:27:10.623870 DBI_WR = 0x0
2186 19:27:10.624300 DBI_RD = 0x0
2187 19:27:10.627196 OTF = 0x1
2188 19:27:10.630748 ===================================
2189 19:27:10.634300 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2190 19:27:10.637468 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2191 19:27:10.644031 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2192 19:27:10.647379 ===================================
2193 19:27:10.647797 LPDDR4 DRAM CONFIGURATION
2194 19:27:10.650527 ===================================
2195 19:27:10.653719 EX_ROW_EN[0] = 0x10
2196 19:27:10.657463 EX_ROW_EN[1] = 0x0
2197 19:27:10.657879 LP4Y_EN = 0x0
2198 19:27:10.660408 WORK_FSP = 0x0
2199 19:27:10.660871 WL = 0x4
2200 19:27:10.664059 RL = 0x4
2201 19:27:10.664469 BL = 0x2
2202 19:27:10.667295 RPST = 0x0
2203 19:27:10.667705 RD_PRE = 0x0
2204 19:27:10.670671 WR_PRE = 0x1
2205 19:27:10.671083 WR_PST = 0x0
2206 19:27:10.673727 DBI_WR = 0x0
2207 19:27:10.674166 DBI_RD = 0x0
2208 19:27:10.676945 OTF = 0x1
2209 19:27:10.680356 ===================================
2210 19:27:10.687104 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2211 19:27:10.687522 ==
2212 19:27:10.690324 Dram Type= 6, Freq= 0, CH_0, rank 0
2213 19:27:10.693674 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2214 19:27:10.694265 ==
2215 19:27:10.696910 [Duty_Offset_Calibration]
2216 19:27:10.697498 B0:0 B1:2 CA:1
2217 19:27:10.697884
2218 19:27:10.700364 [DutyScan_Calibration_Flow] k_type=0
2219 19:27:10.710511
2220 19:27:10.711078 ==CLK 0==
2221 19:27:10.713616 Final CLK duty delay cell = 0
2222 19:27:10.716856 [0] MAX Duty = 5093%(X100), DQS PI = 12
2223 19:27:10.720236 [0] MIN Duty = 4938%(X100), DQS PI = 54
2224 19:27:10.720802 [0] AVG Duty = 5015%(X100)
2225 19:27:10.723428
2226 19:27:10.726925 CH0 CLK Duty spec in!! Max-Min= 155%
2227 19:27:10.730310 [DutyScan_Calibration_Flow] ====Done====
2228 19:27:10.730924
2229 19:27:10.733660 [DutyScan_Calibration_Flow] k_type=1
2230 19:27:10.749589
2231 19:27:10.750141 ==DQS 0 ==
2232 19:27:10.753135 Final DQS duty delay cell = 0
2233 19:27:10.756402 [0] MAX Duty = 5125%(X100), DQS PI = 32
2234 19:27:10.759600 [0] MIN Duty = 5031%(X100), DQS PI = 4
2235 19:27:10.760013 [0] AVG Duty = 5078%(X100)
2236 19:27:10.762997
2237 19:27:10.763482 ==DQS 1 ==
2238 19:27:10.766557 Final DQS duty delay cell = 0
2239 19:27:10.769569 [0] MAX Duty = 5031%(X100), DQS PI = 48
2240 19:27:10.772815 [0] MIN Duty = 4906%(X100), DQS PI = 16
2241 19:27:10.773228 [0] AVG Duty = 4968%(X100)
2242 19:27:10.776570
2243 19:27:10.779634 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2244 19:27:10.780156
2245 19:27:10.782864 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2246 19:27:10.786406 [DutyScan_Calibration_Flow] ====Done====
2247 19:27:10.786911
2248 19:27:10.789479 [DutyScan_Calibration_Flow] k_type=3
2249 19:27:10.806686
2250 19:27:10.807167 ==DQM 0 ==
2251 19:27:10.810405 Final DQM duty delay cell = 0
2252 19:27:10.813529 [0] MAX Duty = 5124%(X100), DQS PI = 20
2253 19:27:10.816654 [0] MIN Duty = 4969%(X100), DQS PI = 40
2254 19:27:10.819993 [0] AVG Duty = 5046%(X100)
2255 19:27:10.820406
2256 19:27:10.820735 ==DQM 1 ==
2257 19:27:10.823390 Final DQM duty delay cell = 4
2258 19:27:10.827075 [4] MAX Duty = 5156%(X100), DQS PI = 48
2259 19:27:10.830204 [4] MIN Duty = 5000%(X100), DQS PI = 18
2260 19:27:10.833801 [4] AVG Duty = 5078%(X100)
2261 19:27:10.834235
2262 19:27:10.837470 CH0 DQM 0 Duty spec in!! Max-Min= 155%
2263 19:27:10.837967
2264 19:27:10.840346 CH0 DQM 1 Duty spec in!! Max-Min= 156%
2265 19:27:10.843706 [DutyScan_Calibration_Flow] ====Done====
2266 19:27:10.844134
2267 19:27:10.846715 [DutyScan_Calibration_Flow] k_type=2
2268 19:27:10.861809
2269 19:27:10.862332 ==DQ 0 ==
2270 19:27:10.865182 Final DQ duty delay cell = -4
2271 19:27:10.868633 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2272 19:27:10.871530 [-4] MIN Duty = 4813%(X100), DQS PI = 8
2273 19:27:10.875015 [-4] AVG Duty = 4937%(X100)
2274 19:27:10.875501
2275 19:27:10.875828 ==DQ 1 ==
2276 19:27:10.878596 Final DQ duty delay cell = -4
2277 19:27:10.881460 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2278 19:27:10.884678 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2279 19:27:10.888466 [-4] AVG Duty = 4984%(X100)
2280 19:27:10.888978
2281 19:27:10.891324 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2282 19:27:10.891750
2283 19:27:10.895148 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2284 19:27:10.898440 [DutyScan_Calibration_Flow] ====Done====
2285 19:27:10.898883 ==
2286 19:27:10.902007 Dram Type= 6, Freq= 0, CH_1, rank 0
2287 19:27:10.904910 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2288 19:27:10.905379 ==
2289 19:27:10.908578 [Duty_Offset_Calibration]
2290 19:27:10.909099 B0:0 B1:4 CA:-5
2291 19:27:10.909432
2292 19:27:10.911292 [DutyScan_Calibration_Flow] k_type=0
2293 19:27:10.922405
2294 19:27:10.922844 ==CLK 0==
2295 19:27:10.925652 Final CLK duty delay cell = 0
2296 19:27:10.928779 [0] MAX Duty = 5094%(X100), DQS PI = 24
2297 19:27:10.932208 [0] MIN Duty = 4907%(X100), DQS PI = 0
2298 19:27:10.932719 [0] AVG Duty = 5000%(X100)
2299 19:27:10.935331
2300 19:27:10.935860 CH1 CLK Duty spec in!! Max-Min= 187%
2301 19:27:10.942656 [DutyScan_Calibration_Flow] ====Done====
2302 19:27:10.943070
2303 19:27:10.945327 [DutyScan_Calibration_Flow] k_type=1
2304 19:27:10.961182
2305 19:27:10.961706 ==DQS 0 ==
2306 19:27:10.963823 Final DQS duty delay cell = 0
2307 19:27:10.967479 [0] MAX Duty = 5125%(X100), DQS PI = 16
2308 19:27:10.970425 [0] MIN Duty = 4875%(X100), DQS PI = 40
2309 19:27:10.973893 [0] AVG Duty = 5000%(X100)
2310 19:27:10.974556
2311 19:27:10.974996 ==DQS 1 ==
2312 19:27:10.977369 Final DQS duty delay cell = -4
2313 19:27:10.980608 [-4] MAX Duty = 5000%(X100), DQS PI = 4
2314 19:27:10.983784 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2315 19:27:10.987017 [-4] AVG Duty = 4953%(X100)
2316 19:27:10.987555
2317 19:27:10.990509 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2318 19:27:10.990979
2319 19:27:10.993479 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2320 19:27:10.997243 [DutyScan_Calibration_Flow] ====Done====
2321 19:27:10.997822
2322 19:27:11.000393 [DutyScan_Calibration_Flow] k_type=3
2323 19:27:11.015732
2324 19:27:11.016217 ==DQM 0 ==
2325 19:27:11.018910 Final DQM duty delay cell = -4
2326 19:27:11.022464 [-4] MAX Duty = 5094%(X100), DQS PI = 30
2327 19:27:11.025605 [-4] MIN Duty = 4844%(X100), DQS PI = 40
2328 19:27:11.029318 [-4] AVG Duty = 4969%(X100)
2329 19:27:11.029727
2330 19:27:11.030088 ==DQM 1 ==
2331 19:27:11.032835 Final DQM duty delay cell = -4
2332 19:27:11.035790 [-4] MAX Duty = 5062%(X100), DQS PI = 4
2333 19:27:11.039014 [-4] MIN Duty = 4907%(X100), DQS PI = 44
2334 19:27:11.042895 [-4] AVG Duty = 4984%(X100)
2335 19:27:11.043306
2336 19:27:11.045849 CH1 DQM 0 Duty spec in!! Max-Min= 250%
2337 19:27:11.046313
2338 19:27:11.049087 CH1 DQM 1 Duty spec in!! Max-Min= 155%
2339 19:27:11.052442 [DutyScan_Calibration_Flow] ====Done====
2340 19:27:11.052855
2341 19:27:11.055844 [DutyScan_Calibration_Flow] k_type=2
2342 19:27:11.073161
2343 19:27:11.073644 ==DQ 0 ==
2344 19:27:11.076760 Final DQ duty delay cell = 0
2345 19:27:11.079416 [0] MAX Duty = 5062%(X100), DQS PI = 0
2346 19:27:11.082823 [0] MIN Duty = 4938%(X100), DQS PI = 44
2347 19:27:11.083254 [0] AVG Duty = 5000%(X100)
2348 19:27:11.083595
2349 19:27:11.086186 ==DQ 1 ==
2350 19:27:11.089691 Final DQ duty delay cell = 0
2351 19:27:11.093261 [0] MAX Duty = 5000%(X100), DQS PI = 6
2352 19:27:11.096325 [0] MIN Duty = 4875%(X100), DQS PI = 0
2353 19:27:11.096740 [0] AVG Duty = 4937%(X100)
2354 19:27:11.097146
2355 19:27:11.099752 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2356 19:27:11.100167
2357 19:27:11.102853 CH1 DQ 1 Duty spec in!! Max-Min= 125%
2358 19:27:11.109651 [DutyScan_Calibration_Flow] ====Done====
2359 19:27:11.112717 nWR fixed to 30
2360 19:27:11.113127 [ModeRegInit_LP4] CH0 RK0
2361 19:27:11.115996 [ModeRegInit_LP4] CH0 RK1
2362 19:27:11.119260 [ModeRegInit_LP4] CH1 RK0
2363 19:27:11.119666 [ModeRegInit_LP4] CH1 RK1
2364 19:27:11.122590 match AC timing 6
2365 19:27:11.126525 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2366 19:27:11.129158 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2367 19:27:11.135912 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2368 19:27:11.139688 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2369 19:27:11.146471 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2370 19:27:11.147036 ==
2371 19:27:11.149460 Dram Type= 6, Freq= 0, CH_0, rank 0
2372 19:27:11.152618 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2373 19:27:11.153136 ==
2374 19:27:11.159516 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2375 19:27:11.162770 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2376 19:27:11.172474 [CA 0] Center 39 (9~70) winsize 62
2377 19:27:11.176206 [CA 1] Center 39 (9~70) winsize 62
2378 19:27:11.179278 [CA 2] Center 36 (5~67) winsize 63
2379 19:27:11.182602 [CA 3] Center 35 (5~66) winsize 62
2380 19:27:11.185918 [CA 4] Center 34 (3~65) winsize 63
2381 19:27:11.189406 [CA 5] Center 33 (3~64) winsize 62
2382 19:27:11.189813
2383 19:27:11.192950 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2384 19:27:11.193437
2385 19:27:11.195958 [CATrainingPosCal] consider 1 rank data
2386 19:27:11.199271 u2DelayCellTimex100 = 270/100 ps
2387 19:27:11.202325 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2388 19:27:11.205721 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2389 19:27:11.212742 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2390 19:27:11.216142 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2391 19:27:11.219410 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2392 19:27:11.222722 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2393 19:27:11.223204
2394 19:27:11.225731 CA PerBit enable=1, Macro0, CA PI delay=33
2395 19:27:11.226177
2396 19:27:11.229227 [CBTSetCACLKResult] CA Dly = 33
2397 19:27:11.229637 CS Dly: 7 (0~38)
2398 19:27:11.229954 ==
2399 19:27:11.232441 Dram Type= 6, Freq= 0, CH_0, rank 1
2400 19:27:11.239324 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2401 19:27:11.239748 ==
2402 19:27:11.242901 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2403 19:27:11.249312 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2404 19:27:11.258053 [CA 0] Center 39 (8~70) winsize 63
2405 19:27:11.261296 [CA 1] Center 39 (8~70) winsize 63
2406 19:27:11.264566 [CA 2] Center 36 (5~67) winsize 63
2407 19:27:11.268202 [CA 3] Center 35 (4~66) winsize 63
2408 19:27:11.271849 [CA 4] Center 33 (3~64) winsize 62
2409 19:27:11.274654 [CA 5] Center 34 (3~65) winsize 63
2410 19:27:11.275064
2411 19:27:11.278011 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2412 19:27:11.278593
2413 19:27:11.281596 [CATrainingPosCal] consider 2 rank data
2414 19:27:11.284651 u2DelayCellTimex100 = 270/100 ps
2415 19:27:11.287958 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2416 19:27:11.291387 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2417 19:27:11.297998 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2418 19:27:11.301283 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2419 19:27:11.304994 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2420 19:27:11.308092 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2421 19:27:11.308524
2422 19:27:11.311291 CA PerBit enable=1, Macro0, CA PI delay=33
2423 19:27:11.311718
2424 19:27:11.314882 [CBTSetCACLKResult] CA Dly = 33
2425 19:27:11.315308 CS Dly: 8 (0~40)
2426 19:27:11.315734
2427 19:27:11.318126 ----->DramcWriteLeveling(PI) begin...
2428 19:27:11.322114 ==
2429 19:27:11.322609 Dram Type= 6, Freq= 0, CH_0, rank 0
2430 19:27:11.328473 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2431 19:27:11.328986 ==
2432 19:27:11.331496 Write leveling (Byte 0): 28 => 28
2433 19:27:11.335060 Write leveling (Byte 1): 25 => 25
2434 19:27:11.335484 DramcWriteLeveling(PI) end<-----
2435 19:27:11.338279
2436 19:27:11.338700 ==
2437 19:27:11.341567 Dram Type= 6, Freq= 0, CH_0, rank 0
2438 19:27:11.344866 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2439 19:27:11.345294 ==
2440 19:27:11.348337 [Gating] SW mode calibration
2441 19:27:11.354644 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2442 19:27:11.358167 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2443 19:27:11.365256 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2444 19:27:11.368286 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2445 19:27:11.371403 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2446 19:27:11.378056 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2447 19:27:11.381357 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2448 19:27:11.384913 0 11 20 | B1->B0 | 2e2e 2d2d | 1 0 | (1 0) (1 0)
2449 19:27:11.391495 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2450 19:27:11.394536 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2451 19:27:11.398266 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2452 19:27:11.404743 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2453 19:27:11.408224 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2454 19:27:11.411167 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2455 19:27:11.418131 0 12 16 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
2456 19:27:11.421796 0 12 20 | B1->B0 | 3737 3d3d | 0 0 | (0 0) (1 1)
2457 19:27:11.424695 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2458 19:27:11.431917 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2459 19:27:11.434894 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2460 19:27:11.438069 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2461 19:27:11.441417 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2462 19:27:11.447935 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2463 19:27:11.451312 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2464 19:27:11.454917 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2465 19:27:11.461283 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2466 19:27:11.464579 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2467 19:27:11.468052 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2468 19:27:11.474950 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2469 19:27:11.477849 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2470 19:27:11.481540 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2471 19:27:11.488190 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2472 19:27:11.491133 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2473 19:27:11.494827 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2474 19:27:11.501258 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2475 19:27:11.504951 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2476 19:27:11.508152 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2477 19:27:11.514809 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2478 19:27:11.517888 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2479 19:27:11.521254 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2480 19:27:11.528079 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2481 19:27:11.531272 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2482 19:27:11.534394 Total UI for P1: 0, mck2ui 16
2483 19:27:11.537788 best dqsien dly found for B0: ( 0, 15, 20)
2484 19:27:11.541330 Total UI for P1: 0, mck2ui 16
2485 19:27:11.544632 best dqsien dly found for B1: ( 0, 15, 20)
2486 19:27:11.547980 best DQS0 dly(MCK, UI, PI) = (0, 15, 20)
2487 19:27:11.551328 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2488 19:27:11.551837
2489 19:27:11.554669 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 20)
2490 19:27:11.557889 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2491 19:27:11.561670 [Gating] SW calibration Done
2492 19:27:11.562232 ==
2493 19:27:11.564254 Dram Type= 6, Freq= 0, CH_0, rank 0
2494 19:27:11.567473 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2495 19:27:11.571093 ==
2496 19:27:11.571546 RX Vref Scan: 0
2497 19:27:11.572019
2498 19:27:11.574705 RX Vref 0 -> 0, step: 1
2499 19:27:11.575163
2500 19:27:11.575521 RX Delay -40 -> 252, step: 8
2501 19:27:11.581560 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2502 19:27:11.584434 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2503 19:27:11.587571 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2504 19:27:11.590975 iDelay=200, Bit 3, Center 111 (32 ~ 191) 160
2505 19:27:11.594360 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2506 19:27:11.601045 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2507 19:27:11.604335 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2508 19:27:11.607896 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2509 19:27:11.610798 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2510 19:27:11.614354 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2511 19:27:11.620879 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2512 19:27:11.624474 iDelay=200, Bit 11, Center 103 (40 ~ 167) 128
2513 19:27:11.627462 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2514 19:27:11.631405 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2515 19:27:11.634239 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2516 19:27:11.641043 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2517 19:27:11.641523 ==
2518 19:27:11.644668 Dram Type= 6, Freq= 0, CH_0, rank 0
2519 19:27:11.647536 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2520 19:27:11.648077 ==
2521 19:27:11.648563 DQS Delay:
2522 19:27:11.651013 DQS0 = 0, DQS1 = 0
2523 19:27:11.651432 DQM Delay:
2524 19:27:11.654398 DQM0 = 115, DQM1 = 106
2525 19:27:11.654807 DQ Delay:
2526 19:27:11.657433 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =111
2527 19:27:11.661322 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2528 19:27:11.664370 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =103
2529 19:27:11.667778 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =115
2530 19:27:11.668190
2531 19:27:11.668507
2532 19:27:11.670981 ==
2533 19:27:11.674639 Dram Type= 6, Freq= 0, CH_0, rank 0
2534 19:27:11.677955 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2535 19:27:11.678410 ==
2536 19:27:11.678738
2537 19:27:11.679037
2538 19:27:11.680918 TX Vref Scan disable
2539 19:27:11.681334 == TX Byte 0 ==
2540 19:27:11.684113 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2541 19:27:11.690767 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2542 19:27:11.691248 == TX Byte 1 ==
2543 19:27:11.694159 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2544 19:27:11.701484 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2545 19:27:11.702008 ==
2546 19:27:11.704808 Dram Type= 6, Freq= 0, CH_0, rank 0
2547 19:27:11.707890 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2548 19:27:11.708358 ==
2549 19:27:11.719402 TX Vref=22, minBit 8, minWin=24, winSum=409
2550 19:27:11.723056 TX Vref=24, minBit 8, minWin=25, winSum=418
2551 19:27:11.725840 TX Vref=26, minBit 8, minWin=25, winSum=427
2552 19:27:11.729519 TX Vref=28, minBit 8, minWin=26, winSum=434
2553 19:27:11.732688 TX Vref=30, minBit 12, minWin=26, winSum=435
2554 19:27:11.739052 TX Vref=32, minBit 9, minWin=26, winSum=433
2555 19:27:11.742537 [TxChooseVref] Worse bit 12, Min win 26, Win sum 435, Final Vref 30
2556 19:27:11.742954
2557 19:27:11.745892 Final TX Range 1 Vref 30
2558 19:27:11.746355
2559 19:27:11.746781 ==
2560 19:27:11.749743 Dram Type= 6, Freq= 0, CH_0, rank 0
2561 19:27:11.752618 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2562 19:27:11.756062 ==
2563 19:27:11.756569
2564 19:27:11.756898
2565 19:27:11.757199 TX Vref Scan disable
2566 19:27:11.759831 == TX Byte 0 ==
2567 19:27:11.762654 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2568 19:27:11.769373 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2569 19:27:11.769786 == TX Byte 1 ==
2570 19:27:11.772998 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2571 19:27:11.776073 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2572 19:27:11.779505
2573 19:27:11.779917 [DATLAT]
2574 19:27:11.780241 Freq=1200, CH0 RK0
2575 19:27:11.780544
2576 19:27:11.782990 DATLAT Default: 0xd
2577 19:27:11.783400 0, 0xFFFF, sum = 0
2578 19:27:11.786172 1, 0xFFFF, sum = 0
2579 19:27:11.789250 2, 0xFFFF, sum = 0
2580 19:27:11.789763 3, 0xFFFF, sum = 0
2581 19:27:11.792968 4, 0xFFFF, sum = 0
2582 19:27:11.793480 5, 0xFFFF, sum = 0
2583 19:27:11.796105 6, 0xFFFF, sum = 0
2584 19:27:11.796521 7, 0xFFFF, sum = 0
2585 19:27:11.799296 8, 0xFFFF, sum = 0
2586 19:27:11.799742 9, 0xFFFF, sum = 0
2587 19:27:11.802437 10, 0xFFFF, sum = 0
2588 19:27:11.802857 11, 0x0, sum = 1
2589 19:27:11.805866 12, 0x0, sum = 2
2590 19:27:11.806325 13, 0x0, sum = 3
2591 19:27:11.809501 14, 0x0, sum = 4
2592 19:27:11.809918 best_step = 12
2593 19:27:11.810306
2594 19:27:11.810615 ==
2595 19:27:11.812808 Dram Type= 6, Freq= 0, CH_0, rank 0
2596 19:27:11.816235 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2597 19:27:11.816667 ==
2598 19:27:11.819186 RX Vref Scan: 1
2599 19:27:11.819596
2600 19:27:11.822425 Set Vref Range= 32 -> 127
2601 19:27:11.822837
2602 19:27:11.823270 RX Vref 32 -> 127, step: 1
2603 19:27:11.823589
2604 19:27:11.825846 RX Delay -21 -> 252, step: 4
2605 19:27:11.826307
2606 19:27:11.829024 Set Vref, RX VrefLevel [Byte0]: 32
2607 19:27:11.832562 [Byte1]: 32
2608 19:27:11.836259
2609 19:27:11.836704 Set Vref, RX VrefLevel [Byte0]: 33
2610 19:27:11.839827 [Byte1]: 33
2611 19:27:11.844494
2612 19:27:11.844920 Set Vref, RX VrefLevel [Byte0]: 34
2613 19:27:11.847293 [Byte1]: 34
2614 19:27:11.851972
2615 19:27:11.852388 Set Vref, RX VrefLevel [Byte0]: 35
2616 19:27:11.855228 [Byte1]: 35
2617 19:27:11.860146
2618 19:27:11.860549 Set Vref, RX VrefLevel [Byte0]: 36
2619 19:27:11.863266 [Byte1]: 36
2620 19:27:11.868110
2621 19:27:11.868523 Set Vref, RX VrefLevel [Byte0]: 37
2622 19:27:11.870889 [Byte1]: 37
2623 19:27:11.875838
2624 19:27:11.876286 Set Vref, RX VrefLevel [Byte0]: 38
2625 19:27:11.879245 [Byte1]: 38
2626 19:27:11.883564
2627 19:27:11.883975 Set Vref, RX VrefLevel [Byte0]: 39
2628 19:27:11.886976 [Byte1]: 39
2629 19:27:11.891354
2630 19:27:11.891648 Set Vref, RX VrefLevel [Byte0]: 40
2631 19:27:11.895306 [Byte1]: 40
2632 19:27:11.899349
2633 19:27:11.899662 Set Vref, RX VrefLevel [Byte0]: 41
2634 19:27:11.902516 [Byte1]: 41
2635 19:27:11.907328
2636 19:27:11.907620 Set Vref, RX VrefLevel [Byte0]: 42
2637 19:27:11.911039 [Byte1]: 42
2638 19:27:11.915557
2639 19:27:11.915955 Set Vref, RX VrefLevel [Byte0]: 43
2640 19:27:11.918861 [Byte1]: 43
2641 19:27:11.923421
2642 19:27:11.923745 Set Vref, RX VrefLevel [Byte0]: 44
2643 19:27:11.926686 [Byte1]: 44
2644 19:27:11.931225
2645 19:27:11.931635 Set Vref, RX VrefLevel [Byte0]: 45
2646 19:27:11.934580 [Byte1]: 45
2647 19:27:11.939113
2648 19:27:11.939549 Set Vref, RX VrefLevel [Byte0]: 46
2649 19:27:11.942644 [Byte1]: 46
2650 19:27:11.947452
2651 19:27:11.947864 Set Vref, RX VrefLevel [Byte0]: 47
2652 19:27:11.951119 [Byte1]: 47
2653 19:27:11.955337
2654 19:27:11.955914 Set Vref, RX VrefLevel [Byte0]: 48
2655 19:27:11.958403 [Byte1]: 48
2656 19:27:11.963047
2657 19:27:11.963458 Set Vref, RX VrefLevel [Byte0]: 49
2658 19:27:11.966649 [Byte1]: 49
2659 19:27:11.971088
2660 19:27:11.971544 Set Vref, RX VrefLevel [Byte0]: 50
2661 19:27:11.974096 [Byte1]: 50
2662 19:27:11.978792
2663 19:27:11.979204 Set Vref, RX VrefLevel [Byte0]: 51
2664 19:27:11.982141 [Byte1]: 51
2665 19:27:11.986673
2666 19:27:11.987127 Set Vref, RX VrefLevel [Byte0]: 52
2667 19:27:11.989936 [Byte1]: 52
2668 19:27:11.994693
2669 19:27:11.995173 Set Vref, RX VrefLevel [Byte0]: 53
2670 19:27:11.997885 [Byte1]: 53
2671 19:27:12.002633
2672 19:27:12.003116 Set Vref, RX VrefLevel [Byte0]: 54
2673 19:27:12.005829 [Byte1]: 54
2674 19:27:12.010700
2675 19:27:12.011116 Set Vref, RX VrefLevel [Byte0]: 55
2676 19:27:12.013683 [Byte1]: 55
2677 19:27:12.018481
2678 19:27:12.018895 Set Vref, RX VrefLevel [Byte0]: 56
2679 19:27:12.021899 [Byte1]: 56
2680 19:27:12.026281
2681 19:27:12.026699 Set Vref, RX VrefLevel [Byte0]: 57
2682 19:27:12.029656 [Byte1]: 57
2683 19:27:12.034510
2684 19:27:12.034963 Set Vref, RX VrefLevel [Byte0]: 58
2685 19:27:12.037923 [Byte1]: 58
2686 19:27:12.042403
2687 19:27:12.042900 Set Vref, RX VrefLevel [Byte0]: 59
2688 19:27:12.045461 [Byte1]: 59
2689 19:27:12.049959
2690 19:27:12.050490 Set Vref, RX VrefLevel [Byte0]: 60
2691 19:27:12.053721 [Byte1]: 60
2692 19:27:12.058246
2693 19:27:12.058758 Set Vref, RX VrefLevel [Byte0]: 61
2694 19:27:12.061330 [Byte1]: 61
2695 19:27:12.065745
2696 19:27:12.066232 Set Vref, RX VrefLevel [Byte0]: 62
2697 19:27:12.068989 [Byte1]: 62
2698 19:27:12.073602
2699 19:27:12.073894 Set Vref, RX VrefLevel [Byte0]: 63
2700 19:27:12.076718 [Byte1]: 63
2701 19:27:12.081927
2702 19:27:12.082260 Set Vref, RX VrefLevel [Byte0]: 64
2703 19:27:12.085021 [Byte1]: 64
2704 19:27:12.089305
2705 19:27:12.089564 Set Vref, RX VrefLevel [Byte0]: 65
2706 19:27:12.092711 [Byte1]: 65
2707 19:27:12.097505
2708 19:27:12.097806 Set Vref, RX VrefLevel [Byte0]: 66
2709 19:27:12.100789 [Byte1]: 66
2710 19:27:12.105539
2711 19:27:12.106104 Final RX Vref Byte 0 = 51 to rank0
2712 19:27:12.109427 Final RX Vref Byte 1 = 49 to rank0
2713 19:27:12.112628 Final RX Vref Byte 0 = 51 to rank1
2714 19:27:12.115414 Final RX Vref Byte 1 = 49 to rank1==
2715 19:27:12.119276 Dram Type= 6, Freq= 0, CH_0, rank 0
2716 19:27:12.125669 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2717 19:27:12.126137 ==
2718 19:27:12.126473 DQS Delay:
2719 19:27:12.126775 DQS0 = 0, DQS1 = 0
2720 19:27:12.128898 DQM Delay:
2721 19:27:12.129309 DQM0 = 114, DQM1 = 105
2722 19:27:12.132684 DQ Delay:
2723 19:27:12.135519 DQ0 =110, DQ1 =114, DQ2 =114, DQ3 =110
2724 19:27:12.138812 DQ4 =118, DQ5 =106, DQ6 =124, DQ7 =122
2725 19:27:12.142112 DQ8 =94, DQ9 =86, DQ10 =106, DQ11 =96
2726 19:27:12.145641 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =118
2727 19:27:12.146090
2728 19:27:12.146425
2729 19:27:12.152177 [DQSOSCAuto] RK0, (LSB)MR18= 0x202, (MSB)MR19= 0x404, tDQSOscB0 = 409 ps tDQSOscB1 = 409 ps
2730 19:27:12.155162 CH0 RK0: MR19=404, MR18=202
2731 19:27:12.161633 CH0_RK0: MR19=0x404, MR18=0x202, DQSOSC=409, MR23=63, INC=39, DEC=26
2732 19:27:12.162081
2733 19:27:12.165188 ----->DramcWriteLeveling(PI) begin...
2734 19:27:12.165608 ==
2735 19:27:12.168634 Dram Type= 6, Freq= 0, CH_0, rank 1
2736 19:27:12.171937 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2737 19:27:12.175724 ==
2738 19:27:12.176218 Write leveling (Byte 0): 28 => 28
2739 19:27:12.179093 Write leveling (Byte 1): 25 => 25
2740 19:27:12.182249 DramcWriteLeveling(PI) end<-----
2741 19:27:12.182662
2742 19:27:12.182984 ==
2743 19:27:12.185467 Dram Type= 6, Freq= 0, CH_0, rank 1
2744 19:27:12.191873 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2745 19:27:12.192291 ==
2746 19:27:12.192616 [Gating] SW mode calibration
2747 19:27:12.202121 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2748 19:27:12.205466 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2749 19:27:12.208887 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2750 19:27:12.215700 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2751 19:27:12.219100 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2752 19:27:12.221783 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2753 19:27:12.228645 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2754 19:27:12.231681 0 11 20 | B1->B0 | 2c2c 2525 | 0 0 | (0 0) (0 0)
2755 19:27:12.235177 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2756 19:27:12.241627 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2757 19:27:12.245346 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2758 19:27:12.248677 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2759 19:27:12.255051 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2760 19:27:12.258499 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2761 19:27:12.262128 0 12 16 | B1->B0 | 2626 3333 | 0 1 | (0 0) (0 0)
2762 19:27:12.268287 0 12 20 | B1->B0 | 3d3d 4646 | 1 0 | (0 0) (0 0)
2763 19:27:12.271949 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2764 19:27:12.274933 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2765 19:27:12.282267 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2766 19:27:12.285429 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2767 19:27:12.288412 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2768 19:27:12.295128 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2769 19:27:12.298215 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2770 19:27:12.301783 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2771 19:27:12.308147 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2772 19:27:12.311410 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2773 19:27:12.314756 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2774 19:27:12.318355 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2775 19:27:12.324875 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2776 19:27:12.328123 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2777 19:27:12.331675 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2778 19:27:12.338203 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2779 19:27:12.341585 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2780 19:27:12.344900 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2781 19:27:12.351483 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2782 19:27:12.355106 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2783 19:27:12.358371 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2784 19:27:12.364646 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2785 19:27:12.368303 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2786 19:27:12.371580 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2787 19:27:12.374805 Total UI for P1: 0, mck2ui 16
2788 19:27:12.377926 best dqsien dly found for B0: ( 0, 15, 16)
2789 19:27:12.384520 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2790 19:27:12.385073 Total UI for P1: 0, mck2ui 16
2791 19:27:12.391558 best dqsien dly found for B1: ( 0, 15, 18)
2792 19:27:12.394570 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
2793 19:27:12.397909 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2794 19:27:12.398380
2795 19:27:12.401180 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
2796 19:27:12.404355 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2797 19:27:12.407809 [Gating] SW calibration Done
2798 19:27:12.408223 ==
2799 19:27:12.411544 Dram Type= 6, Freq= 0, CH_0, rank 1
2800 19:27:12.414595 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2801 19:27:12.415020 ==
2802 19:27:12.417746 RX Vref Scan: 0
2803 19:27:12.418194
2804 19:27:12.418527 RX Vref 0 -> 0, step: 1
2805 19:27:12.418830
2806 19:27:12.421309 RX Delay -40 -> 252, step: 8
2807 19:27:12.424652 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2808 19:27:12.431592 iDelay=200, Bit 1, Center 119 (40 ~ 199) 160
2809 19:27:12.434731 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2810 19:27:12.437891 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2811 19:27:12.441084 iDelay=200, Bit 4, Center 119 (40 ~ 199) 160
2812 19:27:12.444582 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2813 19:27:12.451361 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2814 19:27:12.454620 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2815 19:27:12.457994 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2816 19:27:12.461016 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2817 19:27:12.464285 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2818 19:27:12.471055 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2819 19:27:12.474330 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2820 19:27:12.477834 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2821 19:27:12.480792 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2822 19:27:12.484437 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2823 19:27:12.487600 ==
2824 19:27:12.490945 Dram Type= 6, Freq= 0, CH_0, rank 1
2825 19:27:12.494413 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2826 19:27:12.494830 ==
2827 19:27:12.495156 DQS Delay:
2828 19:27:12.498157 DQS0 = 0, DQS1 = 0
2829 19:27:12.498697 DQM Delay:
2830 19:27:12.500956 DQM0 = 116, DQM1 = 107
2831 19:27:12.501370 DQ Delay:
2832 19:27:12.504578 DQ0 =115, DQ1 =119, DQ2 =115, DQ3 =111
2833 19:27:12.507876 DQ4 =119, DQ5 =103, DQ6 =123, DQ7 =123
2834 19:27:12.511260 DQ8 =91, DQ9 =95, DQ10 =111, DQ11 =99
2835 19:27:12.514616 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2836 19:27:12.515131
2837 19:27:12.515457
2838 19:27:12.515766 ==
2839 19:27:12.517862 Dram Type= 6, Freq= 0, CH_0, rank 1
2840 19:27:12.524601 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2841 19:27:12.525098 ==
2842 19:27:12.525442
2843 19:27:12.525752
2844 19:27:12.526073 TX Vref Scan disable
2845 19:27:12.528005 == TX Byte 0 ==
2846 19:27:12.530821 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2847 19:27:12.534462 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2848 19:27:12.537892 == TX Byte 1 ==
2849 19:27:12.541224 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2850 19:27:12.547857 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2851 19:27:12.548276 ==
2852 19:27:12.551166 Dram Type= 6, Freq= 0, CH_0, rank 1
2853 19:27:12.554306 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2854 19:27:12.554737 ==
2855 19:27:12.565475 TX Vref=22, minBit 8, minWin=25, winSum=416
2856 19:27:12.568991 TX Vref=24, minBit 8, minWin=25, winSum=425
2857 19:27:12.572255 TX Vref=26, minBit 9, minWin=26, winSum=428
2858 19:27:12.575983 TX Vref=28, minBit 10, minWin=25, winSum=428
2859 19:27:12.578874 TX Vref=30, minBit 10, minWin=26, winSum=435
2860 19:27:12.585971 TX Vref=32, minBit 10, minWin=26, winSum=435
2861 19:27:12.589503 [TxChooseVref] Worse bit 10, Min win 26, Win sum 435, Final Vref 30
2862 19:27:12.590085
2863 19:27:12.592350 Final TX Range 1 Vref 30
2864 19:27:12.592814
2865 19:27:12.593173 ==
2866 19:27:12.595692 Dram Type= 6, Freq= 0, CH_0, rank 1
2867 19:27:12.598938 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2868 19:27:12.602495 ==
2869 19:27:12.602956
2870 19:27:12.603317
2871 19:27:12.603652 TX Vref Scan disable
2872 19:27:12.605749 == TX Byte 0 ==
2873 19:27:12.608941 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2874 19:27:12.615883 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2875 19:27:12.616348 == TX Byte 1 ==
2876 19:27:12.618877 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2877 19:27:12.625628 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2878 19:27:12.626192
2879 19:27:12.626560 [DATLAT]
2880 19:27:12.626899 Freq=1200, CH0 RK1
2881 19:27:12.627223
2882 19:27:12.629156 DATLAT Default: 0xc
2883 19:27:12.629615 0, 0xFFFF, sum = 0
2884 19:27:12.632458 1, 0xFFFF, sum = 0
2885 19:27:12.632937 2, 0xFFFF, sum = 0
2886 19:27:12.635507 3, 0xFFFF, sum = 0
2887 19:27:12.638851 4, 0xFFFF, sum = 0
2888 19:27:12.639308 5, 0xFFFF, sum = 0
2889 19:27:12.642247 6, 0xFFFF, sum = 0
2890 19:27:12.642734 7, 0xFFFF, sum = 0
2891 19:27:12.645652 8, 0xFFFF, sum = 0
2892 19:27:12.646145 9, 0xFFFF, sum = 0
2893 19:27:12.648741 10, 0xFFFF, sum = 0
2894 19:27:12.649225 11, 0x0, sum = 1
2895 19:27:12.652398 12, 0x0, sum = 2
2896 19:27:12.652816 13, 0x0, sum = 3
2897 19:27:12.655864 14, 0x0, sum = 4
2898 19:27:12.656283 best_step = 12
2899 19:27:12.656608
2900 19:27:12.656915 ==
2901 19:27:12.658742 Dram Type= 6, Freq= 0, CH_0, rank 1
2902 19:27:12.662311 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2903 19:27:12.662724 ==
2904 19:27:12.665658 RX Vref Scan: 0
2905 19:27:12.666119
2906 19:27:12.669208 RX Vref 0 -> 0, step: 1
2907 19:27:12.669672
2908 19:27:12.670014 RX Delay -21 -> 252, step: 4
2909 19:27:12.676434 iDelay=199, Bit 0, Center 110 (39 ~ 182) 144
2910 19:27:12.679476 iDelay=199, Bit 1, Center 116 (43 ~ 190) 148
2911 19:27:12.683012 iDelay=199, Bit 2, Center 114 (43 ~ 186) 144
2912 19:27:12.686415 iDelay=199, Bit 3, Center 108 (39 ~ 178) 140
2913 19:27:12.689767 iDelay=199, Bit 4, Center 116 (43 ~ 190) 148
2914 19:27:12.696371 iDelay=199, Bit 5, Center 108 (39 ~ 178) 140
2915 19:27:12.699870 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
2916 19:27:12.702890 iDelay=199, Bit 7, Center 124 (51 ~ 198) 148
2917 19:27:12.706288 iDelay=199, Bit 8, Center 94 (31 ~ 158) 128
2918 19:27:12.709535 iDelay=199, Bit 9, Center 90 (27 ~ 154) 128
2919 19:27:12.716809 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
2920 19:27:12.720011 iDelay=199, Bit 11, Center 96 (35 ~ 158) 124
2921 19:27:12.723001 iDelay=199, Bit 12, Center 114 (51 ~ 178) 128
2922 19:27:12.726081 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
2923 19:27:12.729764 iDelay=199, Bit 14, Center 116 (51 ~ 182) 132
2924 19:27:12.736493 iDelay=199, Bit 15, Center 114 (51 ~ 178) 128
2925 19:27:12.736973 ==
2926 19:27:12.739575 Dram Type= 6, Freq= 0, CH_0, rank 1
2927 19:27:12.743130 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2928 19:27:12.743547 ==
2929 19:27:12.743871 DQS Delay:
2930 19:27:12.746403 DQS0 = 0, DQS1 = 0
2931 19:27:12.746812 DQM Delay:
2932 19:27:12.749613 DQM0 = 114, DQM1 = 105
2933 19:27:12.750135 DQ Delay:
2934 19:27:12.753332 DQ0 =110, DQ1 =116, DQ2 =114, DQ3 =108
2935 19:27:12.756168 DQ4 =116, DQ5 =108, DQ6 =122, DQ7 =124
2936 19:27:12.759534 DQ8 =94, DQ9 =90, DQ10 =110, DQ11 =96
2937 19:27:12.763167 DQ12 =114, DQ13 =112, DQ14 =116, DQ15 =114
2938 19:27:12.763581
2939 19:27:12.763901
2940 19:27:12.773071 [DQSOSCAuto] RK1, (LSB)MR18= 0xe0e, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
2941 19:27:12.776547 CH0 RK1: MR19=404, MR18=E0E
2942 19:27:12.779842 CH0_RK1: MR19=0x404, MR18=0xE0E, DQSOSC=404, MR23=63, INC=40, DEC=26
2943 19:27:12.782595 [RxdqsGatingPostProcess] freq 1200
2944 19:27:12.789732 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2945 19:27:12.792605 Pre-setting of DQS Precalculation
2946 19:27:12.795829 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2947 19:27:12.796290 ==
2948 19:27:12.799202 Dram Type= 6, Freq= 0, CH_1, rank 0
2949 19:27:12.806142 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2950 19:27:12.806689 ==
2951 19:27:12.809799 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2952 19:27:12.816521 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2953 19:27:12.824813 [CA 0] Center 37 (7~68) winsize 62
2954 19:27:12.827777 [CA 1] Center 37 (7~68) winsize 62
2955 19:27:12.830888 [CA 2] Center 34 (4~65) winsize 62
2956 19:27:12.834676 [CA 3] Center 33 (3~64) winsize 62
2957 19:27:12.837917 [CA 4] Center 32 (1~63) winsize 63
2958 19:27:12.841014 [CA 5] Center 32 (2~63) winsize 62
2959 19:27:12.841590
2960 19:27:12.844407 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2961 19:27:12.844865
2962 19:27:12.848114 [CATrainingPosCal] consider 1 rank data
2963 19:27:12.851111 u2DelayCellTimex100 = 270/100 ps
2964 19:27:12.854695 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2965 19:27:12.861551 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2966 19:27:12.864628 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2967 19:27:12.867572 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2968 19:27:12.870963 CA4 delay=32 (1~63),Diff = 0 PI (0 cell)
2969 19:27:12.874697 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2970 19:27:12.875261
2971 19:27:12.877932 CA PerBit enable=1, Macro0, CA PI delay=32
2972 19:27:12.878422
2973 19:27:12.881140 [CBTSetCACLKResult] CA Dly = 32
2974 19:27:12.881598 CS Dly: 6 (0~37)
2975 19:27:12.884498 ==
2976 19:27:12.884953 Dram Type= 6, Freq= 0, CH_1, rank 1
2977 19:27:12.891073 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2978 19:27:12.891623 ==
2979 19:27:12.894718 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2980 19:27:12.901305 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2981 19:27:12.909822 [CA 0] Center 37 (7~68) winsize 62
2982 19:27:12.913047 [CA 1] Center 37 (6~68) winsize 63
2983 19:27:12.916470 [CA 2] Center 33 (3~64) winsize 62
2984 19:27:12.920372 [CA 3] Center 33 (3~64) winsize 62
2985 19:27:12.923087 [CA 4] Center 32 (2~63) winsize 62
2986 19:27:12.926780 [CA 5] Center 32 (1~63) winsize 63
2987 19:27:12.927444
2988 19:27:12.930144 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2989 19:27:12.930730
2990 19:27:12.933404 [CATrainingPosCal] consider 2 rank data
2991 19:27:12.936225 u2DelayCellTimex100 = 270/100 ps
2992 19:27:12.939969 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2993 19:27:12.946287 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2994 19:27:12.949647 CA2 delay=34 (4~64),Diff = 2 PI (9 cell)
2995 19:27:12.952822 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2996 19:27:12.956103 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2997 19:27:12.959644 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2998 19:27:12.960105
2999 19:27:12.962884 CA PerBit enable=1, Macro0, CA PI delay=32
3000 19:27:12.963342
3001 19:27:12.966301 [CBTSetCACLKResult] CA Dly = 32
3002 19:27:12.966902 CS Dly: 6 (0~38)
3003 19:27:12.967270
3004 19:27:12.969603 ----->DramcWriteLeveling(PI) begin...
3005 19:27:12.972789 ==
3006 19:27:12.976496 Dram Type= 6, Freq= 0, CH_1, rank 0
3007 19:27:12.979490 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3008 19:27:12.979958 ==
3009 19:27:12.982776 Write leveling (Byte 0): 22 => 22
3010 19:27:12.986143 Write leveling (Byte 1): 22 => 22
3011 19:27:12.989658 DramcWriteLeveling(PI) end<-----
3012 19:27:12.990257
3013 19:27:12.990625 ==
3014 19:27:12.992877 Dram Type= 6, Freq= 0, CH_1, rank 0
3015 19:27:12.996247 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3016 19:27:12.996803 ==
3017 19:27:12.999927 [Gating] SW mode calibration
3018 19:27:13.006359 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3019 19:27:13.013334 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3020 19:27:13.016889 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3021 19:27:13.019998 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3022 19:27:13.023057 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3023 19:27:13.029776 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3024 19:27:13.033028 0 11 16 | B1->B0 | 2e2e 2424 | 0 0 | (0 1) (0 0)
3025 19:27:13.036450 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3026 19:27:13.042809 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3027 19:27:13.046207 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3028 19:27:13.049725 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3029 19:27:13.056343 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3030 19:27:13.059669 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3031 19:27:13.062869 0 12 12 | B1->B0 | 2323 2929 | 0 0 | (0 0) (1 1)
3032 19:27:13.069670 0 12 16 | B1->B0 | 2e2e 4040 | 0 0 | (0 0) (0 0)
3033 19:27:13.073214 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3034 19:27:13.076120 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3035 19:27:13.082772 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3036 19:27:13.085881 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3037 19:27:13.089757 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3038 19:27:13.096597 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3039 19:27:13.099656 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3040 19:27:13.102703 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3041 19:27:13.109605 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3042 19:27:13.113235 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3043 19:27:13.116194 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3044 19:27:13.123121 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3045 19:27:13.126187 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3046 19:27:13.129587 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3047 19:27:13.133119 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3048 19:27:13.139722 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3049 19:27:13.142524 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3050 19:27:13.146191 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3051 19:27:13.152687 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3052 19:27:13.156095 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3053 19:27:13.159447 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3054 19:27:13.166421 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3055 19:27:13.169467 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3056 19:27:13.173015 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3057 19:27:13.180052 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3058 19:27:13.180608 Total UI for P1: 0, mck2ui 16
3059 19:27:13.186373 best dqsien dly found for B0: ( 0, 15, 16)
3060 19:27:13.189519 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3061 19:27:13.192585 Total UI for P1: 0, mck2ui 16
3062 19:27:13.196111 best dqsien dly found for B1: ( 0, 15, 18)
3063 19:27:13.199398 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
3064 19:27:13.202753 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
3065 19:27:13.203323
3066 19:27:13.205949 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
3067 19:27:13.209649 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
3068 19:27:13.212694 [Gating] SW calibration Done
3069 19:27:13.213151 ==
3070 19:27:13.216137 Dram Type= 6, Freq= 0, CH_1, rank 0
3071 19:27:13.219437 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3072 19:27:13.222524 ==
3073 19:27:13.222987 RX Vref Scan: 0
3074 19:27:13.223348
3075 19:27:13.226504 RX Vref 0 -> 0, step: 1
3076 19:27:13.227078
3077 19:27:13.229475 RX Delay -40 -> 252, step: 8
3078 19:27:13.232569 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3079 19:27:13.235852 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152
3080 19:27:13.239096 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3081 19:27:13.242693 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3082 19:27:13.249371 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3083 19:27:13.252663 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3084 19:27:13.255972 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3085 19:27:13.259711 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3086 19:27:13.262265 iDelay=208, Bit 8, Center 87 (16 ~ 159) 144
3087 19:27:13.269220 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3088 19:27:13.272947 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3089 19:27:13.275761 iDelay=208, Bit 11, Center 103 (32 ~ 175) 144
3090 19:27:13.279022 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3091 19:27:13.282629 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3092 19:27:13.289331 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3093 19:27:13.292389 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3094 19:27:13.292960 ==
3095 19:27:13.295769 Dram Type= 6, Freq= 0, CH_1, rank 0
3096 19:27:13.299565 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3097 19:27:13.300136 ==
3098 19:27:13.302177 DQS Delay:
3099 19:27:13.302634 DQS0 = 0, DQS1 = 0
3100 19:27:13.302991 DQM Delay:
3101 19:27:13.305831 DQM0 = 116, DQM1 = 109
3102 19:27:13.306447 DQ Delay:
3103 19:27:13.308883 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3104 19:27:13.312211 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3105 19:27:13.315875 DQ8 =87, DQ9 =99, DQ10 =111, DQ11 =103
3106 19:27:13.322282 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3107 19:27:13.322850
3108 19:27:13.323336
3109 19:27:13.323789 ==
3110 19:27:13.325901 Dram Type= 6, Freq= 0, CH_1, rank 0
3111 19:27:13.329047 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3112 19:27:13.329492 ==
3113 19:27:13.329956
3114 19:27:13.330439
3115 19:27:13.332325 TX Vref Scan disable
3116 19:27:13.332894 == TX Byte 0 ==
3117 19:27:13.338780 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3118 19:27:13.342291 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3119 19:27:13.342862 == TX Byte 1 ==
3120 19:27:13.349048 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3121 19:27:13.352526 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3122 19:27:13.353042 ==
3123 19:27:13.355619 Dram Type= 6, Freq= 0, CH_1, rank 0
3124 19:27:13.358662 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3125 19:27:13.359143 ==
3126 19:27:13.371807 TX Vref=22, minBit 11, minWin=24, winSum=412
3127 19:27:13.374527 TX Vref=24, minBit 15, minWin=25, winSum=425
3128 19:27:13.378205 TX Vref=26, minBit 8, minWin=26, winSum=430
3129 19:27:13.381564 TX Vref=28, minBit 1, minWin=26, winSum=430
3130 19:27:13.384545 TX Vref=30, minBit 8, minWin=26, winSum=431
3131 19:27:13.391656 TX Vref=32, minBit 0, minWin=26, winSum=427
3132 19:27:13.394521 [TxChooseVref] Worse bit 8, Min win 26, Win sum 431, Final Vref 30
3133 19:27:13.395006
3134 19:27:13.398345 Final TX Range 1 Vref 30
3135 19:27:13.398911
3136 19:27:13.399396 ==
3137 19:27:13.401377 Dram Type= 6, Freq= 0, CH_1, rank 0
3138 19:27:13.404549 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3139 19:27:13.405118 ==
3140 19:27:13.405601
3141 19:27:13.407782
3142 19:27:13.408373 TX Vref Scan disable
3143 19:27:13.411462 == TX Byte 0 ==
3144 19:27:13.414493 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3145 19:27:13.418202 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3146 19:27:13.421229 == TX Byte 1 ==
3147 19:27:13.425047 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3148 19:27:13.428392 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3149 19:27:13.428972
3150 19:27:13.431401 [DATLAT]
3151 19:27:13.431875 Freq=1200, CH1 RK0
3152 19:27:13.432357
3153 19:27:13.434911 DATLAT Default: 0xd
3154 19:27:13.435480 0, 0xFFFF, sum = 0
3155 19:27:13.437622 1, 0xFFFF, sum = 0
3156 19:27:13.438175 2, 0xFFFF, sum = 0
3157 19:27:13.441054 3, 0xFFFF, sum = 0
3158 19:27:13.441514 4, 0xFFFF, sum = 0
3159 19:27:13.444511 5, 0xFFFF, sum = 0
3160 19:27:13.444975 6, 0xFFFF, sum = 0
3161 19:27:13.448122 7, 0xFFFF, sum = 0
3162 19:27:13.448696 8, 0xFFFF, sum = 0
3163 19:27:13.451204 9, 0xFFFF, sum = 0
3164 19:27:13.454270 10, 0xFFFF, sum = 0
3165 19:27:13.454737 11, 0x0, sum = 1
3166 19:27:13.455097 12, 0x0, sum = 2
3167 19:27:13.457799 13, 0x0, sum = 3
3168 19:27:13.458509 14, 0x0, sum = 4
3169 19:27:13.460979 best_step = 12
3170 19:27:13.461724
3171 19:27:13.462296 ==
3172 19:27:13.464720 Dram Type= 6, Freq= 0, CH_1, rank 0
3173 19:27:13.467937 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3174 19:27:13.468402 ==
3175 19:27:13.471019 RX Vref Scan: 1
3176 19:27:13.471476
3177 19:27:13.471834 Set Vref Range= 32 -> 127
3178 19:27:13.474125
3179 19:27:13.474578 RX Vref 32 -> 127, step: 1
3180 19:27:13.474941
3181 19:27:13.477801 RX Delay -29 -> 252, step: 4
3182 19:27:13.478420
3183 19:27:13.481390 Set Vref, RX VrefLevel [Byte0]: 32
3184 19:27:13.484918 [Byte1]: 32
3185 19:27:13.487809
3186 19:27:13.488300 Set Vref, RX VrefLevel [Byte0]: 33
3187 19:27:13.490801 [Byte1]: 33
3188 19:27:13.495413
3189 19:27:13.495867 Set Vref, RX VrefLevel [Byte0]: 34
3190 19:27:13.499570 [Byte1]: 34
3191 19:27:13.503992
3192 19:27:13.504452 Set Vref, RX VrefLevel [Byte0]: 35
3193 19:27:13.506713 [Byte1]: 35
3194 19:27:13.511721
3195 19:27:13.512176 Set Vref, RX VrefLevel [Byte0]: 36
3196 19:27:13.514888 [Byte1]: 36
3197 19:27:13.519630
3198 19:27:13.520202 Set Vref, RX VrefLevel [Byte0]: 37
3199 19:27:13.522838 [Byte1]: 37
3200 19:27:13.527308
3201 19:27:13.527991 Set Vref, RX VrefLevel [Byte0]: 38
3202 19:27:13.530590 [Byte1]: 38
3203 19:27:13.535322
3204 19:27:13.535879 Set Vref, RX VrefLevel [Byte0]: 39
3205 19:27:13.538602 [Byte1]: 39
3206 19:27:13.543703
3207 19:27:13.544259 Set Vref, RX VrefLevel [Byte0]: 40
3208 19:27:13.546593 [Byte1]: 40
3209 19:27:13.551295
3210 19:27:13.551871 Set Vref, RX VrefLevel [Byte0]: 41
3211 19:27:13.554397 [Byte1]: 41
3212 19:27:13.559074
3213 19:27:13.559534 Set Vref, RX VrefLevel [Byte0]: 42
3214 19:27:13.562736 [Byte1]: 42
3215 19:27:13.567149
3216 19:27:13.567627 Set Vref, RX VrefLevel [Byte0]: 43
3217 19:27:13.570558 [Byte1]: 43
3218 19:27:13.575805
3219 19:27:13.576362 Set Vref, RX VrefLevel [Byte0]: 44
3220 19:27:13.578511 [Byte1]: 44
3221 19:27:13.583006
3222 19:27:13.583562 Set Vref, RX VrefLevel [Byte0]: 45
3223 19:27:13.586094 [Byte1]: 45
3224 19:27:13.591459
3225 19:27:13.592018 Set Vref, RX VrefLevel [Byte0]: 46
3226 19:27:13.594601 [Byte1]: 46
3227 19:27:13.599059
3228 19:27:13.599619 Set Vref, RX VrefLevel [Byte0]: 47
3229 19:27:13.602706 [Byte1]: 47
3230 19:27:13.606801
3231 19:27:13.607259 Set Vref, RX VrefLevel [Byte0]: 48
3232 19:27:13.610693 [Byte1]: 48
3233 19:27:13.615123
3234 19:27:13.615682 Set Vref, RX VrefLevel [Byte0]: 49
3235 19:27:13.618520 [Byte1]: 49
3236 19:27:13.622886
3237 19:27:13.623463 Set Vref, RX VrefLevel [Byte0]: 50
3238 19:27:13.626537 [Byte1]: 50
3239 19:27:13.631463
3240 19:27:13.632027 Set Vref, RX VrefLevel [Byte0]: 51
3241 19:27:13.634276 [Byte1]: 51
3242 19:27:13.639272
3243 19:27:13.639831 Set Vref, RX VrefLevel [Byte0]: 52
3244 19:27:13.642412 [Byte1]: 52
3245 19:27:13.647003
3246 19:27:13.647557 Set Vref, RX VrefLevel [Byte0]: 53
3247 19:27:13.650518 [Byte1]: 53
3248 19:27:13.654669
3249 19:27:13.655124 Set Vref, RX VrefLevel [Byte0]: 54
3250 19:27:13.657993 [Byte1]: 54
3251 19:27:13.662682
3252 19:27:13.663138 Set Vref, RX VrefLevel [Byte0]: 55
3253 19:27:13.665980 [Byte1]: 55
3254 19:27:13.670814
3255 19:27:13.671268 Set Vref, RX VrefLevel [Byte0]: 56
3256 19:27:13.673623 [Byte1]: 56
3257 19:27:13.678474
3258 19:27:13.679033 Set Vref, RX VrefLevel [Byte0]: 57
3259 19:27:13.681904 [Byte1]: 57
3260 19:27:13.686610
3261 19:27:13.687167 Set Vref, RX VrefLevel [Byte0]: 58
3262 19:27:13.690165 [Byte1]: 58
3263 19:27:13.694411
3264 19:27:13.694972 Set Vref, RX VrefLevel [Byte0]: 59
3265 19:27:13.697583 [Byte1]: 59
3266 19:27:13.702894
3267 19:27:13.703502 Set Vref, RX VrefLevel [Byte0]: 60
3268 19:27:13.706053 [Byte1]: 60
3269 19:27:13.710958
3270 19:27:13.711487 Set Vref, RX VrefLevel [Byte0]: 61
3271 19:27:13.713591 [Byte1]: 61
3272 19:27:13.718290
3273 19:27:13.718844 Set Vref, RX VrefLevel [Byte0]: 62
3274 19:27:13.722209 [Byte1]: 62
3275 19:27:13.726305
3276 19:27:13.726860 Set Vref, RX VrefLevel [Byte0]: 63
3277 19:27:13.729944 [Byte1]: 63
3278 19:27:13.734203
3279 19:27:13.734664 Set Vref, RX VrefLevel [Byte0]: 64
3280 19:27:13.737948 [Byte1]: 64
3281 19:27:13.742404
3282 19:27:13.742957 Set Vref, RX VrefLevel [Byte0]: 65
3283 19:27:13.745838 [Byte1]: 65
3284 19:27:13.750541
3285 19:27:13.751102 Set Vref, RX VrefLevel [Byte0]: 66
3286 19:27:13.753336 [Byte1]: 66
3287 19:27:13.758310
3288 19:27:13.758864 Set Vref, RX VrefLevel [Byte0]: 67
3289 19:27:13.761196 [Byte1]: 67
3290 19:27:13.765764
3291 19:27:13.769442 Final RX Vref Byte 0 = 53 to rank0
3292 19:27:13.769919 Final RX Vref Byte 1 = 52 to rank0
3293 19:27:13.772589 Final RX Vref Byte 0 = 53 to rank1
3294 19:27:13.776057 Final RX Vref Byte 1 = 52 to rank1==
3295 19:27:13.779470 Dram Type= 6, Freq= 0, CH_1, rank 0
3296 19:27:13.786532 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3297 19:27:13.787093 ==
3298 19:27:13.787454 DQS Delay:
3299 19:27:13.789784 DQS0 = 0, DQS1 = 0
3300 19:27:13.790390 DQM Delay:
3301 19:27:13.790755 DQM0 = 115, DQM1 = 106
3302 19:27:13.792786 DQ Delay:
3303 19:27:13.796170 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =114
3304 19:27:13.799448 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =112
3305 19:27:13.802341 DQ8 =86, DQ9 =94, DQ10 =110, DQ11 =98
3306 19:27:13.805813 DQ12 =114, DQ13 =116, DQ14 =114, DQ15 =116
3307 19:27:13.806416
3308 19:27:13.806779
3309 19:27:13.815883 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a1a, (MSB)MR19= 0x404, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
3310 19:27:13.816455 CH1 RK0: MR19=404, MR18=1A1A
3311 19:27:13.822596 CH1_RK0: MR19=0x404, MR18=0x1A1A, DQSOSC=400, MR23=63, INC=40, DEC=27
3312 19:27:13.823145
3313 19:27:13.826108 ----->DramcWriteLeveling(PI) begin...
3314 19:27:13.826671 ==
3315 19:27:13.829086 Dram Type= 6, Freq= 0, CH_1, rank 1
3316 19:27:13.835538 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3317 19:27:13.835995 ==
3318 19:27:13.839363 Write leveling (Byte 0): 23 => 23
3319 19:27:13.839924 Write leveling (Byte 1): 23 => 23
3320 19:27:13.842687 DramcWriteLeveling(PI) end<-----
3321 19:27:13.843246
3322 19:27:13.843606 ==
3323 19:27:13.845620 Dram Type= 6, Freq= 0, CH_1, rank 1
3324 19:27:13.852498 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3325 19:27:13.853048 ==
3326 19:27:13.855697 [Gating] SW mode calibration
3327 19:27:13.862408 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3328 19:27:13.865865 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3329 19:27:13.872299 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3330 19:27:13.875579 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3331 19:27:13.878791 0 11 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
3332 19:27:13.882230 0 11 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
3333 19:27:13.889122 0 11 16 | B1->B0 | 3030 2323 | 1 0 | (1 0) (1 0)
3334 19:27:13.892325 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3335 19:27:13.895937 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3336 19:27:13.902251 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3337 19:27:13.905657 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3338 19:27:13.909111 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3339 19:27:13.915871 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3340 19:27:13.919083 0 12 12 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (1 1)
3341 19:27:13.922413 0 12 16 | B1->B0 | 3636 4646 | 1 0 | (0 0) (0 0)
3342 19:27:13.928918 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3343 19:27:13.932261 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3344 19:27:13.935481 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3345 19:27:13.942148 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3346 19:27:13.945678 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3347 19:27:13.948962 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3348 19:27:13.955282 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3349 19:27:13.958732 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3350 19:27:13.962421 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3351 19:27:13.969177 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3352 19:27:13.972533 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3353 19:27:13.975637 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3354 19:27:13.982413 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3355 19:27:13.985820 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3356 19:27:13.989427 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3357 19:27:13.992243 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3358 19:27:13.999263 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3359 19:27:14.002235 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3360 19:27:14.005649 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3361 19:27:14.011932 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3362 19:27:14.015826 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3363 19:27:14.019121 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3364 19:27:14.025407 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3365 19:27:14.029306 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3366 19:27:14.032091 Total UI for P1: 0, mck2ui 16
3367 19:27:14.035559 best dqsien dly found for B0: ( 0, 15, 12)
3368 19:27:14.038926 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3369 19:27:14.045446 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3370 19:27:14.046014 Total UI for P1: 0, mck2ui 16
3371 19:27:14.052142 best dqsien dly found for B1: ( 0, 15, 18)
3372 19:27:14.055277 best DQS0 dly(MCK, UI, PI) = (0, 15, 12)
3373 19:27:14.058561 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
3374 19:27:14.059021
3375 19:27:14.061880 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 12)
3376 19:27:14.065486 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
3377 19:27:14.069025 [Gating] SW calibration Done
3378 19:27:14.069593 ==
3379 19:27:14.071819 Dram Type= 6, Freq= 0, CH_1, rank 1
3380 19:27:14.075194 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3381 19:27:14.075645 ==
3382 19:27:14.079131 RX Vref Scan: 0
3383 19:27:14.079680
3384 19:27:14.080036 RX Vref 0 -> 0, step: 1
3385 19:27:14.080366
3386 19:27:14.081949 RX Delay -40 -> 252, step: 8
3387 19:27:14.085728 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3388 19:27:14.091890 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3389 19:27:14.095419 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
3390 19:27:14.099106 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3391 19:27:14.101791 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3392 19:27:14.105378 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3393 19:27:14.111823 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3394 19:27:14.115491 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3395 19:27:14.118665 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
3396 19:27:14.121891 iDelay=200, Bit 9, Center 91 (16 ~ 167) 152
3397 19:27:14.125555 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
3398 19:27:14.132078 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
3399 19:27:14.135314 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3400 19:27:14.138818 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3401 19:27:14.141680 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3402 19:27:14.145541 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3403 19:27:14.148552 ==
3404 19:27:14.151774 Dram Type= 6, Freq= 0, CH_1, rank 1
3405 19:27:14.155120 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3406 19:27:14.155576 ==
3407 19:27:14.155928 DQS Delay:
3408 19:27:14.158491 DQS0 = 0, DQS1 = 0
3409 19:27:14.158936 DQM Delay:
3410 19:27:14.161672 DQM0 = 116, DQM1 = 105
3411 19:27:14.162317 DQ Delay:
3412 19:27:14.165109 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =115
3413 19:27:14.168782 DQ4 =115, DQ5 =123, DQ6 =123, DQ7 =115
3414 19:27:14.172115 DQ8 =91, DQ9 =91, DQ10 =107, DQ11 =99
3415 19:27:14.174899 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =111
3416 19:27:14.175352
3417 19:27:14.175695
3418 19:27:14.176019 ==
3419 19:27:14.178424 Dram Type= 6, Freq= 0, CH_1, rank 1
3420 19:27:14.185527 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3421 19:27:14.186128 ==
3422 19:27:14.186493
3423 19:27:14.186822
3424 19:27:14.187133 TX Vref Scan disable
3425 19:27:14.188631 == TX Byte 0 ==
3426 19:27:14.191729 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3427 19:27:14.195010 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3428 19:27:14.198476 == TX Byte 1 ==
3429 19:27:14.201662 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3430 19:27:14.205480 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3431 19:27:14.208820 ==
3432 19:27:14.212232 Dram Type= 6, Freq= 0, CH_1, rank 1
3433 19:27:14.215437 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3434 19:27:14.215994 ==
3435 19:27:14.226084 TX Vref=22, minBit 0, minWin=24, winSum=419
3436 19:27:14.229209 TX Vref=24, minBit 9, minWin=25, winSum=421
3437 19:27:14.232561 TX Vref=26, minBit 0, minWin=26, winSum=426
3438 19:27:14.235831 TX Vref=28, minBit 8, minWin=26, winSum=429
3439 19:27:14.239124 TX Vref=30, minBit 0, minWin=26, winSum=429
3440 19:27:14.242806 TX Vref=32, minBit 0, minWin=25, winSum=429
3441 19:27:14.249507 [TxChooseVref] Worse bit 8, Min win 26, Win sum 429, Final Vref 28
3442 19:27:14.250101
3443 19:27:14.252672 Final TX Range 1 Vref 28
3444 19:27:14.253229
3445 19:27:14.253582 ==
3446 19:27:14.255881 Dram Type= 6, Freq= 0, CH_1, rank 1
3447 19:27:14.259357 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3448 19:27:14.259816 ==
3449 19:27:14.260169
3450 19:27:14.262639
3451 19:27:14.263110 TX Vref Scan disable
3452 19:27:14.265975 == TX Byte 0 ==
3453 19:27:14.269142 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3454 19:27:14.272701 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3455 19:27:14.276209 == TX Byte 1 ==
3456 19:27:14.279358 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3457 19:27:14.282406 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3458 19:27:14.282873
3459 19:27:14.286396 [DATLAT]
3460 19:27:14.286957 Freq=1200, CH1 RK1
3461 19:27:14.287321
3462 19:27:14.289197 DATLAT Default: 0xc
3463 19:27:14.289947 0, 0xFFFF, sum = 0
3464 19:27:14.292577 1, 0xFFFF, sum = 0
3465 19:27:14.293120 2, 0xFFFF, sum = 0
3466 19:27:14.296072 3, 0xFFFF, sum = 0
3467 19:27:14.296540 4, 0xFFFF, sum = 0
3468 19:27:14.298947 5, 0xFFFF, sum = 0
3469 19:27:14.299425 6, 0xFFFF, sum = 0
3470 19:27:14.302407 7, 0xFFFF, sum = 0
3471 19:27:14.302872 8, 0xFFFF, sum = 0
3472 19:27:14.305772 9, 0xFFFF, sum = 0
3473 19:27:14.309391 10, 0xFFFF, sum = 0
3474 19:27:14.309960 11, 0x0, sum = 1
3475 19:27:14.310413 12, 0x0, sum = 2
3476 19:27:14.312814 13, 0x0, sum = 3
3477 19:27:14.313279 14, 0x0, sum = 4
3478 19:27:14.316141 best_step = 12
3479 19:27:14.316702
3480 19:27:14.317066 ==
3481 19:27:14.319151 Dram Type= 6, Freq= 0, CH_1, rank 1
3482 19:27:14.322780 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3483 19:27:14.323245 ==
3484 19:27:14.325912 RX Vref Scan: 0
3485 19:27:14.326404
3486 19:27:14.326764 RX Vref 0 -> 0, step: 1
3487 19:27:14.327097
3488 19:27:14.329208 RX Delay -29 -> 252, step: 4
3489 19:27:14.336648 iDelay=199, Bit 0, Center 114 (43 ~ 186) 144
3490 19:27:14.339380 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3491 19:27:14.342566 iDelay=199, Bit 2, Center 108 (39 ~ 178) 140
3492 19:27:14.345827 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3493 19:27:14.349392 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144
3494 19:27:14.355834 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3495 19:27:14.359691 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3496 19:27:14.363083 iDelay=199, Bit 7, Center 112 (39 ~ 186) 148
3497 19:27:14.365921 iDelay=199, Bit 8, Center 88 (19 ~ 158) 140
3498 19:27:14.369593 iDelay=199, Bit 9, Center 94 (27 ~ 162) 136
3499 19:27:14.376333 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3500 19:27:14.379620 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3501 19:27:14.382644 iDelay=199, Bit 12, Center 114 (43 ~ 186) 144
3502 19:27:14.386395 iDelay=199, Bit 13, Center 114 (47 ~ 182) 136
3503 19:27:14.389751 iDelay=199, Bit 14, Center 116 (47 ~ 186) 140
3504 19:27:14.396076 iDelay=199, Bit 15, Center 110 (43 ~ 178) 136
3505 19:27:14.396616 ==
3506 19:27:14.399430 Dram Type= 6, Freq= 0, CH_1, rank 1
3507 19:27:14.402861 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3508 19:27:14.403321 ==
3509 19:27:14.403677 DQS Delay:
3510 19:27:14.406390 DQS0 = 0, DQS1 = 0
3511 19:27:14.406946 DQM Delay:
3512 19:27:14.409712 DQM0 = 114, DQM1 = 105
3513 19:27:14.410318 DQ Delay:
3514 19:27:14.413053 DQ0 =114, DQ1 =110, DQ2 =108, DQ3 =112
3515 19:27:14.416130 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =112
3516 19:27:14.419985 DQ8 =88, DQ9 =94, DQ10 =110, DQ11 =98
3517 19:27:14.423341 DQ12 =114, DQ13 =114, DQ14 =116, DQ15 =110
3518 19:27:14.423893
3519 19:27:14.424251
3520 19:27:14.432686 [DQSOSCAuto] RK1, (LSB)MR18= 0xa0a, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
3521 19:27:14.436376 CH1 RK1: MR19=404, MR18=A0A
3522 19:27:14.438910 CH1_RK1: MR19=0x404, MR18=0xA0A, DQSOSC=406, MR23=63, INC=39, DEC=26
3523 19:27:14.442775 [RxdqsGatingPostProcess] freq 1200
3524 19:27:14.449376 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3525 19:27:14.452388 Pre-setting of DQS Precalculation
3526 19:27:14.455639 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3527 19:27:14.465580 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3528 19:27:14.472511 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3529 19:27:14.473055
3530 19:27:14.473408
3531 19:27:14.475615 [Calibration Summary] 2400 Mbps
3532 19:27:14.476174 CH 0, Rank 0
3533 19:27:14.479502 SW Impedance : PASS
3534 19:27:14.480057 DUTY Scan : NO K
3535 19:27:14.482320 ZQ Calibration : PASS
3536 19:27:14.485998 Jitter Meter : NO K
3537 19:27:14.486595 CBT Training : PASS
3538 19:27:14.489499 Write leveling : PASS
3539 19:27:14.492459 RX DQS gating : PASS
3540 19:27:14.493012 RX DQ/DQS(RDDQC) : PASS
3541 19:27:14.495487 TX DQ/DQS : PASS
3542 19:27:14.498501 RX DATLAT : PASS
3543 19:27:14.499005 RX DQ/DQS(Engine): PASS
3544 19:27:14.501957 TX OE : NO K
3545 19:27:14.502450 All Pass.
3546 19:27:14.502808
3547 19:27:14.505386 CH 0, Rank 1
3548 19:27:14.505882 SW Impedance : PASS
3549 19:27:14.508955 DUTY Scan : NO K
3550 19:27:14.512717 ZQ Calibration : PASS
3551 19:27:14.513172 Jitter Meter : NO K
3552 19:27:14.515224 CBT Training : PASS
3553 19:27:14.518512 Write leveling : PASS
3554 19:27:14.518962 RX DQS gating : PASS
3555 19:27:14.522142 RX DQ/DQS(RDDQC) : PASS
3556 19:27:14.522702 TX DQ/DQS : PASS
3557 19:27:14.525841 RX DATLAT : PASS
3558 19:27:14.528966 RX DQ/DQS(Engine): PASS
3559 19:27:14.529522 TX OE : NO K
3560 19:27:14.532434 All Pass.
3561 19:27:14.532988
3562 19:27:14.533434 CH 1, Rank 0
3563 19:27:14.535502 SW Impedance : PASS
3564 19:27:14.535954 DUTY Scan : NO K
3565 19:27:14.538970 ZQ Calibration : PASS
3566 19:27:14.542323 Jitter Meter : NO K
3567 19:27:14.542872 CBT Training : PASS
3568 19:27:14.545724 Write leveling : PASS
3569 19:27:14.548770 RX DQS gating : PASS
3570 19:27:14.549376 RX DQ/DQS(RDDQC) : PASS
3571 19:27:14.552196 TX DQ/DQS : PASS
3572 19:27:14.555497 RX DATLAT : PASS
3573 19:27:14.556020 RX DQ/DQS(Engine): PASS
3574 19:27:14.558472 TX OE : NO K
3575 19:27:14.558931 All Pass.
3576 19:27:14.559322
3577 19:27:14.562378 CH 1, Rank 1
3578 19:27:14.562865 SW Impedance : PASS
3579 19:27:14.565288 DUTY Scan : NO K
3580 19:27:14.565748 ZQ Calibration : PASS
3581 19:27:14.568557 Jitter Meter : NO K
3582 19:27:14.571984 CBT Training : PASS
3583 19:27:14.572437 Write leveling : PASS
3584 19:27:14.575213 RX DQS gating : PASS
3585 19:27:14.578485 RX DQ/DQS(RDDQC) : PASS
3586 19:27:14.578937 TX DQ/DQS : PASS
3587 19:27:14.582105 RX DATLAT : PASS
3588 19:27:14.585627 RX DQ/DQS(Engine): PASS
3589 19:27:14.586119 TX OE : NO K
3590 19:27:14.588621 All Pass.
3591 19:27:14.589075
3592 19:27:14.589395 DramC Write-DBI off
3593 19:27:14.591694 PER_BANK_REFRESH: Hybrid Mode
3594 19:27:14.592104 TX_TRACKING: ON
3595 19:27:14.601856 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3596 19:27:14.605218 [FAST_K] Save calibration result to emmc
3597 19:27:14.608141 dramc_set_vcore_voltage set vcore to 650000
3598 19:27:14.611925 Read voltage for 600, 5
3599 19:27:14.612371 Vio18 = 0
3600 19:27:14.615008 Vcore = 650000
3601 19:27:14.615494 Vdram = 0
3602 19:27:14.615821 Vddq = 0
3603 19:27:14.618458 Vmddr = 0
3604 19:27:14.621540 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3605 19:27:14.628324 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3606 19:27:14.628749 MEM_TYPE=3, freq_sel=19
3607 19:27:14.632115 sv_algorithm_assistance_LP4_1600
3608 19:27:14.638731 ============ PULL DRAM RESETB DOWN ============
3609 19:27:14.641605 ========== PULL DRAM RESETB DOWN end =========
3610 19:27:14.645195 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3611 19:27:14.648339 ===================================
3612 19:27:14.651792 LPDDR4 DRAM CONFIGURATION
3613 19:27:14.655141 ===================================
3614 19:27:14.655746 EX_ROW_EN[0] = 0x0
3615 19:27:14.658149 EX_ROW_EN[1] = 0x0
3616 19:27:14.661724 LP4Y_EN = 0x0
3617 19:27:14.662219 WORK_FSP = 0x0
3618 19:27:14.664946 WL = 0x2
3619 19:27:14.665603 RL = 0x2
3620 19:27:14.668152 BL = 0x2
3621 19:27:14.668579 RPST = 0x0
3622 19:27:14.671557 RD_PRE = 0x0
3623 19:27:14.672008 WR_PRE = 0x1
3624 19:27:14.674487 WR_PST = 0x0
3625 19:27:14.674924 DBI_WR = 0x0
3626 19:27:14.678060 DBI_RD = 0x0
3627 19:27:14.678516 OTF = 0x1
3628 19:27:14.681497 ===================================
3629 19:27:14.684666 ===================================
3630 19:27:14.687920 ANA top config
3631 19:27:14.691204 ===================================
3632 19:27:14.691697 DLL_ASYNC_EN = 0
3633 19:27:14.694531 ALL_SLAVE_EN = 1
3634 19:27:14.698072 NEW_RANK_MODE = 1
3635 19:27:14.701099 DLL_IDLE_MODE = 1
3636 19:27:14.704317 LP45_APHY_COMB_EN = 1
3637 19:27:14.705041 TX_ODT_DIS = 1
3638 19:27:14.707774 NEW_8X_MODE = 1
3639 19:27:14.711151 ===================================
3640 19:27:14.714123 ===================================
3641 19:27:14.717694 data_rate = 1200
3642 19:27:14.720641 CKR = 1
3643 19:27:14.724168 DQ_P2S_RATIO = 8
3644 19:27:14.727792 ===================================
3645 19:27:14.731067 CA_P2S_RATIO = 8
3646 19:27:14.731456 DQ_CA_OPEN = 0
3647 19:27:14.734078 DQ_SEMI_OPEN = 0
3648 19:27:14.737414 CA_SEMI_OPEN = 0
3649 19:27:14.740953 CA_FULL_RATE = 0
3650 19:27:14.744283 DQ_CKDIV4_EN = 1
3651 19:27:14.747543 CA_CKDIV4_EN = 1
3652 19:27:14.747919 CA_PREDIV_EN = 0
3653 19:27:14.750557 PH8_DLY = 0
3654 19:27:14.753772 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3655 19:27:14.757325 DQ_AAMCK_DIV = 4
3656 19:27:14.760972 CA_AAMCK_DIV = 4
3657 19:27:14.763716 CA_ADMCK_DIV = 4
3658 19:27:14.764089 DQ_TRACK_CA_EN = 0
3659 19:27:14.767316 CA_PICK = 600
3660 19:27:14.770733 CA_MCKIO = 600
3661 19:27:14.773870 MCKIO_SEMI = 0
3662 19:27:14.777211 PLL_FREQ = 2288
3663 19:27:14.780307 DQ_UI_PI_RATIO = 32
3664 19:27:14.785672 CA_UI_PI_RATIO = 0
3665 19:27:14.787283 ===================================
3666 19:27:14.790140 ===================================
3667 19:27:14.790555 memory_type:LPDDR4
3668 19:27:14.793478 GP_NUM : 10
3669 19:27:14.796948 SRAM_EN : 1
3670 19:27:14.797360 MD32_EN : 0
3671 19:27:14.800333 ===================================
3672 19:27:14.803385 [ANA_INIT] >>>>>>>>>>>>>>
3673 19:27:14.806791 <<<<<< [CONFIGURE PHASE]: ANA_TX
3674 19:27:14.810111 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3675 19:27:14.813402 ===================================
3676 19:27:14.817186 data_rate = 1200,PCW = 0X5800
3677 19:27:14.820322 ===================================
3678 19:27:14.823274 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3679 19:27:14.827029 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3680 19:27:14.833362 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3681 19:27:14.836821 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3682 19:27:14.840106 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3683 19:27:14.843424 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3684 19:27:14.846912 [ANA_INIT] flow start
3685 19:27:14.850122 [ANA_INIT] PLL >>>>>>>>
3686 19:27:14.850531 [ANA_INIT] PLL <<<<<<<<
3687 19:27:14.853289 [ANA_INIT] MIDPI >>>>>>>>
3688 19:27:14.856881 [ANA_INIT] MIDPI <<<<<<<<
3689 19:27:14.859831 [ANA_INIT] DLL >>>>>>>>
3690 19:27:14.860273 [ANA_INIT] flow end
3691 19:27:14.863447 ============ LP4 DIFF to SE enter ============
3692 19:27:14.870102 ============ LP4 DIFF to SE exit ============
3693 19:27:14.870546 [ANA_INIT] <<<<<<<<<<<<<
3694 19:27:14.873673 [Flow] Enable top DCM control >>>>>
3695 19:27:14.876776 [Flow] Enable top DCM control <<<<<
3696 19:27:14.879661 Enable DLL master slave shuffle
3697 19:27:14.886341 ==============================================================
3698 19:27:14.886780 Gating Mode config
3699 19:27:14.893223 ==============================================================
3700 19:27:14.896483 Config description:
3701 19:27:14.905853 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3702 19:27:14.912612 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3703 19:27:14.915818 SELPH_MODE 0: By rank 1: By Phase
3704 19:27:14.922520 ==============================================================
3705 19:27:14.925932 GAT_TRACK_EN = 1
3706 19:27:14.926006 RX_GATING_MODE = 2
3707 19:27:14.929279 RX_GATING_TRACK_MODE = 2
3708 19:27:14.932338 SELPH_MODE = 1
3709 19:27:14.935778 PICG_EARLY_EN = 1
3710 19:27:14.939318 VALID_LAT_VALUE = 1
3711 19:27:14.945906 ==============================================================
3712 19:27:14.949215 Enter into Gating configuration >>>>
3713 19:27:14.952638 Exit from Gating configuration <<<<
3714 19:27:14.955886 Enter into DVFS_PRE_config >>>>>
3715 19:27:14.965851 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3716 19:27:14.969256 Exit from DVFS_PRE_config <<<<<
3717 19:27:14.971986 Enter into PICG configuration >>>>
3718 19:27:14.975418 Exit from PICG configuration <<<<
3719 19:27:14.978764 [RX_INPUT] configuration >>>>>
3720 19:27:14.982075 [RX_INPUT] configuration <<<<<
3721 19:27:14.985694 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3722 19:27:14.991894 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3723 19:27:14.998780 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3724 19:27:15.005194 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3725 19:27:15.008623 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3726 19:27:15.015201 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3727 19:27:15.018278 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3728 19:27:15.025047 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3729 19:27:15.028459 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3730 19:27:15.031769 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3731 19:27:15.034971 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3732 19:27:15.041750 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3733 19:27:15.044718 ===================================
3734 19:27:15.048254 LPDDR4 DRAM CONFIGURATION
3735 19:27:15.051774 ===================================
3736 19:27:15.051852 EX_ROW_EN[0] = 0x0
3737 19:27:15.054537 EX_ROW_EN[1] = 0x0
3738 19:27:15.054603 LP4Y_EN = 0x0
3739 19:27:15.058286 WORK_FSP = 0x0
3740 19:27:15.058363 WL = 0x2
3741 19:27:15.061675 RL = 0x2
3742 19:27:15.061750 BL = 0x2
3743 19:27:15.065103 RPST = 0x0
3744 19:27:15.065173 RD_PRE = 0x0
3745 19:27:15.067968 WR_PRE = 0x1
3746 19:27:15.068042 WR_PST = 0x0
3747 19:27:15.071530 DBI_WR = 0x0
3748 19:27:15.071600 DBI_RD = 0x0
3749 19:27:15.074508 OTF = 0x1
3750 19:27:15.077901 ===================================
3751 19:27:15.081382 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3752 19:27:15.084674 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3753 19:27:15.091076 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3754 19:27:15.094310 ===================================
3755 19:27:15.094381 LPDDR4 DRAM CONFIGURATION
3756 19:27:15.097931 ===================================
3757 19:27:15.101490 EX_ROW_EN[0] = 0x10
3758 19:27:15.104673 EX_ROW_EN[1] = 0x0
3759 19:27:15.104743 LP4Y_EN = 0x0
3760 19:27:15.107721 WORK_FSP = 0x0
3761 19:27:15.107792 WL = 0x2
3762 19:27:15.111172 RL = 0x2
3763 19:27:15.111242 BL = 0x2
3764 19:27:15.114380 RPST = 0x0
3765 19:27:15.114455 RD_PRE = 0x0
3766 19:27:15.118152 WR_PRE = 0x1
3767 19:27:15.118227 WR_PST = 0x0
3768 19:27:15.121005 DBI_WR = 0x0
3769 19:27:15.121074 DBI_RD = 0x0
3770 19:27:15.124166 OTF = 0x1
3771 19:27:15.127834 ===================================
3772 19:27:15.134435 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3773 19:27:15.137369 nWR fixed to 30
3774 19:27:15.140789 [ModeRegInit_LP4] CH0 RK0
3775 19:27:15.140865 [ModeRegInit_LP4] CH0 RK1
3776 19:27:15.144445 [ModeRegInit_LP4] CH1 RK0
3777 19:27:15.147289 [ModeRegInit_LP4] CH1 RK1
3778 19:27:15.147366 match AC timing 16
3779 19:27:15.154248 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3780 19:27:15.157343 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3781 19:27:15.161245 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3782 19:27:15.167298 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3783 19:27:15.170920 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3784 19:27:15.171030 ==
3785 19:27:15.174202 Dram Type= 6, Freq= 0, CH_0, rank 0
3786 19:27:15.177314 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3787 19:27:15.177398 ==
3788 19:27:15.183818 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3789 19:27:15.190452 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3790 19:27:15.193703 [CA 0] Center 35 (5~66) winsize 62
3791 19:27:15.197016 [CA 1] Center 35 (5~66) winsize 62
3792 19:27:15.200342 [CA 2] Center 34 (4~65) winsize 62
3793 19:27:15.203957 [CA 3] Center 34 (4~65) winsize 62
3794 19:27:15.206901 [CA 4] Center 33 (3~64) winsize 62
3795 19:27:15.210062 [CA 5] Center 33 (3~64) winsize 62
3796 19:27:15.210148
3797 19:27:15.213760 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3798 19:27:15.213859
3799 19:27:15.216887 [CATrainingPosCal] consider 1 rank data
3800 19:27:15.220449 u2DelayCellTimex100 = 270/100 ps
3801 19:27:15.223387 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3802 19:27:15.227068 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3803 19:27:15.230318 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3804 19:27:15.233293 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3805 19:27:15.236863 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3806 19:27:15.243508 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3807 19:27:15.243582
3808 19:27:15.246530 CA PerBit enable=1, Macro0, CA PI delay=33
3809 19:27:15.246606
3810 19:27:15.250303 [CBTSetCACLKResult] CA Dly = 33
3811 19:27:15.250383 CS Dly: 6 (0~37)
3812 19:27:15.250446 ==
3813 19:27:15.253473 Dram Type= 6, Freq= 0, CH_0, rank 1
3814 19:27:15.256545 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3815 19:27:15.260018 ==
3816 19:27:15.263296 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3817 19:27:15.270001 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
3818 19:27:15.273386 [CA 0] Center 35 (5~66) winsize 62
3819 19:27:15.276702 [CA 1] Center 35 (5~66) winsize 62
3820 19:27:15.279884 [CA 2] Center 34 (4~65) winsize 62
3821 19:27:15.282994 [CA 3] Center 34 (4~65) winsize 62
3822 19:27:15.286313 [CA 4] Center 33 (3~64) winsize 62
3823 19:27:15.289750 [CA 5] Center 33 (3~64) winsize 62
3824 19:27:15.289846
3825 19:27:15.293021 [CmdBusTrainingLP45] Vref(ca) range 1: 39
3826 19:27:15.293119
3827 19:27:15.296390 [CATrainingPosCal] consider 2 rank data
3828 19:27:15.299753 u2DelayCellTimex100 = 270/100 ps
3829 19:27:15.302959 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3830 19:27:15.306206 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3831 19:27:15.309726 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3832 19:27:15.316159 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3833 19:27:15.319195 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3834 19:27:15.322575 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3835 19:27:15.322672
3836 19:27:15.326042 CA PerBit enable=1, Macro0, CA PI delay=33
3837 19:27:15.326153
3838 19:27:15.329644 [CBTSetCACLKResult] CA Dly = 33
3839 19:27:15.329766 CS Dly: 5 (0~35)
3840 19:27:15.329877
3841 19:27:15.332810 ----->DramcWriteLeveling(PI) begin...
3842 19:27:15.336280 ==
3843 19:27:15.339440 Dram Type= 6, Freq= 0, CH_0, rank 0
3844 19:27:15.342782 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3845 19:27:15.342880 ==
3846 19:27:15.345874 Write leveling (Byte 0): 32 => 32
3847 19:27:15.349579 Write leveling (Byte 1): 32 => 32
3848 19:27:15.352906 DramcWriteLeveling(PI) end<-----
3849 19:27:15.353009
3850 19:27:15.353096 ==
3851 19:27:15.356050 Dram Type= 6, Freq= 0, CH_0, rank 0
3852 19:27:15.358970 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3853 19:27:15.359040 ==
3854 19:27:15.362342 [Gating] SW mode calibration
3855 19:27:15.369252 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3856 19:27:15.372233 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3857 19:27:15.379223 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3858 19:27:15.382141 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3859 19:27:15.385492 0 5 8 | B1->B0 | 3434 3030 | 1 0 | (1 1) (1 1)
3860 19:27:15.392178 0 5 12 | B1->B0 | 2626 2323 | 0 0 | (1 1) (0 0)
3861 19:27:15.395856 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3862 19:27:15.398876 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3863 19:27:15.405483 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3864 19:27:15.408511 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3865 19:27:15.412190 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3866 19:27:15.419093 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3867 19:27:15.422216 0 6 8 | B1->B0 | 2828 2e2e | 0 0 | (0 0) (0 0)
3868 19:27:15.425271 0 6 12 | B1->B0 | 4444 4646 | 1 0 | (0 0) (0 0)
3869 19:27:15.431771 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3870 19:27:15.435340 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3871 19:27:15.438403 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3872 19:27:15.445173 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3873 19:27:15.448219 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3874 19:27:15.451810 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3875 19:27:15.458230 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3876 19:27:15.461648 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3877 19:27:15.465025 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3878 19:27:15.471759 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3879 19:27:15.474972 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3880 19:27:15.478207 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3881 19:27:15.484892 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3882 19:27:15.488495 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3883 19:27:15.491452 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3884 19:27:15.497820 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3885 19:27:15.501494 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3886 19:27:15.504363 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3887 19:27:15.511203 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3888 19:27:15.514376 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3889 19:27:15.517692 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3890 19:27:15.524402 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3891 19:27:15.527391 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3892 19:27:15.530801 Total UI for P1: 0, mck2ui 16
3893 19:27:15.534660 best dqsien dly found for B0: ( 0, 9, 6)
3894 19:27:15.537744 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3895 19:27:15.541012 Total UI for P1: 0, mck2ui 16
3896 19:27:15.544225 best dqsien dly found for B1: ( 0, 9, 8)
3897 19:27:15.547485 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
3898 19:27:15.550655 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
3899 19:27:15.550735
3900 19:27:15.557211 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
3901 19:27:15.560463 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
3902 19:27:15.563859 [Gating] SW calibration Done
3903 19:27:15.563939 ==
3904 19:27:15.567257 Dram Type= 6, Freq= 0, CH_0, rank 0
3905 19:27:15.570350 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3906 19:27:15.570433 ==
3907 19:27:15.570497 RX Vref Scan: 0
3908 19:27:15.570560
3909 19:27:15.573714 RX Vref 0 -> 0, step: 1
3910 19:27:15.573784
3911 19:27:15.577267 RX Delay -230 -> 252, step: 16
3912 19:27:15.580056 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3913 19:27:15.587321 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
3914 19:27:15.590300 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
3915 19:27:15.593659 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3916 19:27:15.597141 iDelay=218, Bit 4, Center 41 (-134 ~ 217) 352
3917 19:27:15.599930 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
3918 19:27:15.606705 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
3919 19:27:15.610294 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
3920 19:27:15.613629 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3921 19:27:15.616938 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3922 19:27:15.623607 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3923 19:27:15.626637 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3924 19:27:15.629857 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3925 19:27:15.633036 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3926 19:27:15.640094 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3927 19:27:15.643951 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3928 19:27:15.644031 ==
3929 19:27:15.646509 Dram Type= 6, Freq= 0, CH_0, rank 0
3930 19:27:15.650068 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3931 19:27:15.650162 ==
3932 19:27:15.652871 DQS Delay:
3933 19:27:15.652976 DQS0 = 0, DQS1 = 0
3934 19:27:15.653073 DQM Delay:
3935 19:27:15.656633 DQM0 = 39, DQM1 = 33
3936 19:27:15.656713 DQ Delay:
3937 19:27:15.659865 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
3938 19:27:15.663010 DQ4 =41, DQ5 =25, DQ6 =57, DQ7 =57
3939 19:27:15.666369 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3940 19:27:15.669577 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3941 19:27:15.669687
3942 19:27:15.669783
3943 19:27:15.669870 ==
3944 19:27:15.672980 Dram Type= 6, Freq= 0, CH_0, rank 0
3945 19:27:15.679538 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3946 19:27:15.679618 ==
3947 19:27:15.679681
3948 19:27:15.679739
3949 19:27:15.679813 TX Vref Scan disable
3950 19:27:15.683005 == TX Byte 0 ==
3951 19:27:15.686518 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
3952 19:27:15.689881 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
3953 19:27:15.693648 == TX Byte 1 ==
3954 19:27:15.696519 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
3955 19:27:15.702909 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
3956 19:27:15.703015 ==
3957 19:27:15.706715 Dram Type= 6, Freq= 0, CH_0, rank 0
3958 19:27:15.710053 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3959 19:27:15.710147 ==
3960 19:27:15.710209
3961 19:27:15.710267
3962 19:27:15.712799 TX Vref Scan disable
3963 19:27:15.712879 == TX Byte 0 ==
3964 19:27:15.719655 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
3965 19:27:15.723239 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
3966 19:27:15.723320 == TX Byte 1 ==
3967 19:27:15.730010 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
3968 19:27:15.733056 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
3969 19:27:15.733161
3970 19:27:15.733251 [DATLAT]
3971 19:27:15.735961 Freq=600, CH0 RK0
3972 19:27:15.736032
3973 19:27:15.736090 DATLAT Default: 0x9
3974 19:27:15.739313 0, 0xFFFF, sum = 0
3975 19:27:15.739430 1, 0xFFFF, sum = 0
3976 19:27:15.742659 2, 0xFFFF, sum = 0
3977 19:27:15.746198 3, 0xFFFF, sum = 0
3978 19:27:15.746301 4, 0xFFFF, sum = 0
3979 19:27:15.749572 5, 0xFFFF, sum = 0
3980 19:27:15.749659 6, 0xFFFF, sum = 0
3981 19:27:15.752684 7, 0x0, sum = 1
3982 19:27:15.752782 8, 0x0, sum = 2
3983 19:27:15.752878 9, 0x0, sum = 3
3984 19:27:15.756113 10, 0x0, sum = 4
3985 19:27:15.756213 best_step = 8
3986 19:27:15.756300
3987 19:27:15.756383 ==
3988 19:27:15.759468 Dram Type= 6, Freq= 0, CH_0, rank 0
3989 19:27:15.765906 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3990 19:27:15.766011 ==
3991 19:27:15.766133 RX Vref Scan: 1
3992 19:27:15.766221
3993 19:27:15.769409 RX Vref 0 -> 0, step: 1
3994 19:27:15.769491
3995 19:27:15.772822 RX Delay -195 -> 252, step: 8
3996 19:27:15.772898
3997 19:27:15.775654 Set Vref, RX VrefLevel [Byte0]: 51
3998 19:27:15.779017 [Byte1]: 49
3999 19:27:15.779087
4000 19:27:15.782550 Final RX Vref Byte 0 = 51 to rank0
4001 19:27:15.785924 Final RX Vref Byte 1 = 49 to rank0
4002 19:27:15.789316 Final RX Vref Byte 0 = 51 to rank1
4003 19:27:15.792415 Final RX Vref Byte 1 = 49 to rank1==
4004 19:27:15.795617 Dram Type= 6, Freq= 0, CH_0, rank 0
4005 19:27:15.798907 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4006 19:27:15.798982 ==
4007 19:27:15.802589 DQS Delay:
4008 19:27:15.802702 DQS0 = 0, DQS1 = 0
4009 19:27:15.805734 DQM Delay:
4010 19:27:15.805837 DQM0 = 40, DQM1 = 30
4011 19:27:15.805929 DQ Delay:
4012 19:27:15.808899 DQ0 =36, DQ1 =40, DQ2 =40, DQ3 =40
4013 19:27:15.812408 DQ4 =40, DQ5 =28, DQ6 =48, DQ7 =48
4014 19:27:15.815427 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4015 19:27:15.818929 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4016 19:27:15.819002
4017 19:27:15.819062
4018 19:27:15.828841 [DQSOSCAuto] RK0, (LSB)MR18= 0x5555, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
4019 19:27:15.832161 CH0 RK0: MR19=808, MR18=5555
4020 19:27:15.838924 CH0_RK0: MR19=0x808, MR18=0x5555, DQSOSC=393, MR23=63, INC=169, DEC=113
4021 19:27:15.839007
4022 19:27:15.842211 ----->DramcWriteLeveling(PI) begin...
4023 19:27:15.842285 ==
4024 19:27:15.845739 Dram Type= 6, Freq= 0, CH_0, rank 1
4025 19:27:15.849023 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4026 19:27:15.849093 ==
4027 19:27:15.852125 Write leveling (Byte 0): 31 => 31
4028 19:27:15.855484 Write leveling (Byte 1): 31 => 31
4029 19:27:15.858699 DramcWriteLeveling(PI) end<-----
4030 19:27:15.858774
4031 19:27:15.858833 ==
4032 19:27:15.862361 Dram Type= 6, Freq= 0, CH_0, rank 1
4033 19:27:15.865526 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4034 19:27:15.865600 ==
4035 19:27:15.868959 [Gating] SW mode calibration
4036 19:27:15.875127 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4037 19:27:15.882114 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4038 19:27:15.885383 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4039 19:27:15.888371 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4040 19:27:15.894923 0 5 8 | B1->B0 | 3232 3232 | 0 0 | (0 1) (0 0)
4041 19:27:15.898319 0 5 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
4042 19:27:15.901558 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4043 19:27:15.908422 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4044 19:27:15.911471 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4045 19:27:15.914814 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4046 19:27:15.921976 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4047 19:27:15.925056 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4048 19:27:15.928389 0 6 8 | B1->B0 | 2c2c 2e2e | 0 0 | (0 0) (0 0)
4049 19:27:15.935501 0 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4050 19:27:15.938113 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4051 19:27:15.941402 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4052 19:27:15.948391 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4053 19:27:15.951436 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4054 19:27:15.954733 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4055 19:27:15.961291 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4056 19:27:15.964729 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4057 19:27:15.968067 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4058 19:27:15.974774 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 19:27:15.977859 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 19:27:15.981384 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 19:27:15.987859 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 19:27:15.991330 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 19:27:15.994590 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 19:27:15.997882 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 19:27:16.004409 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 19:27:16.007997 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 19:27:16.011206 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 19:27:16.017915 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 19:27:16.021179 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 19:27:16.024380 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 19:27:16.031306 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 19:27:16.034333 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4073 19:27:16.037696 Total UI for P1: 0, mck2ui 16
4074 19:27:16.041075 best dqsien dly found for B0: ( 0, 9, 6)
4075 19:27:16.043937 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4076 19:27:16.047441 Total UI for P1: 0, mck2ui 16
4077 19:27:16.050463 best dqsien dly found for B1: ( 0, 9, 8)
4078 19:27:16.054317 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4079 19:27:16.057727 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4080 19:27:16.060894
4081 19:27:16.063740 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4082 19:27:16.067292 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4083 19:27:16.070706 [Gating] SW calibration Done
4084 19:27:16.070780 ==
4085 19:27:16.073803 Dram Type= 6, Freq= 0, CH_0, rank 1
4086 19:27:16.077281 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4087 19:27:16.077356 ==
4088 19:27:16.077416 RX Vref Scan: 0
4089 19:27:16.080224
4090 19:27:16.080289 RX Vref 0 -> 0, step: 1
4091 19:27:16.080349
4092 19:27:16.083603 RX Delay -230 -> 252, step: 16
4093 19:27:16.086752 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4094 19:27:16.093670 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4095 19:27:16.096957 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4096 19:27:16.100659 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4097 19:27:16.103434 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4098 19:27:16.106801 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4099 19:27:16.113427 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4100 19:27:16.117227 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4101 19:27:16.120106 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4102 19:27:16.123512 iDelay=218, Bit 9, Center 9 (-150 ~ 169) 320
4103 19:27:16.129971 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4104 19:27:16.133168 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4105 19:27:16.136794 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4106 19:27:16.139691 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4107 19:27:16.146630 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4108 19:27:16.149976 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4109 19:27:16.150080 ==
4110 19:27:16.153144 Dram Type= 6, Freq= 0, CH_0, rank 1
4111 19:27:16.156747 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4112 19:27:16.156827 ==
4113 19:27:16.160017 DQS Delay:
4114 19:27:16.160092 DQS0 = 0, DQS1 = 0
4115 19:27:16.160153 DQM Delay:
4116 19:27:16.163137 DQM0 = 45, DQM1 = 34
4117 19:27:16.163204 DQ Delay:
4118 19:27:16.165996 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4119 19:27:16.169927 DQ4 =49, DQ5 =41, DQ6 =49, DQ7 =49
4120 19:27:16.172876 DQ8 =25, DQ9 =9, DQ10 =41, DQ11 =33
4121 19:27:16.176419 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4122 19:27:16.176489
4123 19:27:16.176547
4124 19:27:16.176603 ==
4125 19:27:16.179394 Dram Type= 6, Freq= 0, CH_0, rank 1
4126 19:27:16.185970 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4127 19:27:16.186066 ==
4128 19:27:16.186141
4129 19:27:16.186199
4130 19:27:16.186254 TX Vref Scan disable
4131 19:27:16.189694 == TX Byte 0 ==
4132 19:27:16.193180 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4133 19:27:16.199527 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4134 19:27:16.199610 == TX Byte 1 ==
4135 19:27:16.203139 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4136 19:27:16.209552 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4137 19:27:16.209636 ==
4138 19:27:16.212909 Dram Type= 6, Freq= 0, CH_0, rank 1
4139 19:27:16.216544 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4140 19:27:16.216643 ==
4141 19:27:16.216739
4142 19:27:16.216826
4143 19:27:16.220080 TX Vref Scan disable
4144 19:27:16.222742 == TX Byte 0 ==
4145 19:27:16.226419 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4146 19:27:16.229572 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4147 19:27:16.232733 == TX Byte 1 ==
4148 19:27:16.236166 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4149 19:27:16.239261 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4150 19:27:16.239343
4151 19:27:16.239419 [DATLAT]
4152 19:27:16.243035 Freq=600, CH0 RK1
4153 19:27:16.243116
4154 19:27:16.246230 DATLAT Default: 0x8
4155 19:27:16.246311 0, 0xFFFF, sum = 0
4156 19:27:16.249106 1, 0xFFFF, sum = 0
4157 19:27:16.249188 2, 0xFFFF, sum = 0
4158 19:27:16.252765 3, 0xFFFF, sum = 0
4159 19:27:16.252847 4, 0xFFFF, sum = 0
4160 19:27:16.255752 5, 0xFFFF, sum = 0
4161 19:27:16.255835 6, 0xFFFF, sum = 0
4162 19:27:16.258926 7, 0x0, sum = 1
4163 19:27:16.259008 8, 0x0, sum = 2
4164 19:27:16.262430 9, 0x0, sum = 3
4165 19:27:16.262512 10, 0x0, sum = 4
4166 19:27:16.262576 best_step = 8
4167 19:27:16.262635
4168 19:27:16.266090 ==
4169 19:27:16.266171 Dram Type= 6, Freq= 0, CH_0, rank 1
4170 19:27:16.272680 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4171 19:27:16.272762 ==
4172 19:27:16.272826 RX Vref Scan: 0
4173 19:27:16.272886
4174 19:27:16.275387 RX Vref 0 -> 0, step: 1
4175 19:27:16.275468
4176 19:27:16.278851 RX Delay -195 -> 252, step: 8
4177 19:27:16.285763 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4178 19:27:16.288689 iDelay=205, Bit 1, Center 48 (-107 ~ 204) 312
4179 19:27:16.292411 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4180 19:27:16.295904 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4181 19:27:16.298911 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4182 19:27:16.305728 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4183 19:27:16.309011 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4184 19:27:16.312242 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4185 19:27:16.315205 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4186 19:27:16.321856 iDelay=205, Bit 9, Center 16 (-131 ~ 164) 296
4187 19:27:16.325437 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4188 19:27:16.328750 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4189 19:27:16.332233 iDelay=205, Bit 12, Center 40 (-107 ~ 188) 296
4190 19:27:16.338496 iDelay=205, Bit 13, Center 36 (-115 ~ 188) 304
4191 19:27:16.341891 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4192 19:27:16.345528 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4193 19:27:16.345610 ==
4194 19:27:16.348729 Dram Type= 6, Freq= 0, CH_0, rank 1
4195 19:27:16.351581 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4196 19:27:16.351663 ==
4197 19:27:16.355125 DQS Delay:
4198 19:27:16.355206 DQS0 = 0, DQS1 = 0
4199 19:27:16.358313 DQM Delay:
4200 19:27:16.358393 DQM0 = 42, DQM1 = 32
4201 19:27:16.358456 DQ Delay:
4202 19:27:16.361565 DQ0 =36, DQ1 =48, DQ2 =40, DQ3 =36
4203 19:27:16.364795 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4204 19:27:16.368183 DQ8 =20, DQ9 =16, DQ10 =32, DQ11 =24
4205 19:27:16.371578 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4206 19:27:16.371660
4207 19:27:16.375410
4208 19:27:16.381617 [DQSOSCAuto] RK1, (LSB)MR18= 0x6f6f, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
4209 19:27:16.384433 CH0 RK1: MR19=808, MR18=6F6F
4210 19:27:16.391333 CH0_RK1: MR19=0x808, MR18=0x6F6F, DQSOSC=389, MR23=63, INC=173, DEC=115
4211 19:27:16.394321 [RxdqsGatingPostProcess] freq 600
4212 19:27:16.398335 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4213 19:27:16.400925 Pre-setting of DQS Precalculation
4214 19:27:16.407732 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4215 19:27:16.407814 ==
4216 19:27:16.410930 Dram Type= 6, Freq= 0, CH_1, rank 0
4217 19:27:16.414849 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4218 19:27:16.414957 ==
4219 19:27:16.420733 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4220 19:27:16.424082 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4221 19:27:16.428346 [CA 0] Center 35 (5~66) winsize 62
4222 19:27:16.431558 [CA 1] Center 35 (5~66) winsize 62
4223 19:27:16.435334 [CA 2] Center 33 (3~64) winsize 62
4224 19:27:16.438050 [CA 3] Center 33 (3~64) winsize 62
4225 19:27:16.441502 [CA 4] Center 33 (2~64) winsize 63
4226 19:27:16.445110 [CA 5] Center 33 (2~64) winsize 63
4227 19:27:16.445191
4228 19:27:16.448314 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4229 19:27:16.448399
4230 19:27:16.451912 [CATrainingPosCal] consider 1 rank data
4231 19:27:16.454602 u2DelayCellTimex100 = 270/100 ps
4232 19:27:16.458144 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4233 19:27:16.464767 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4234 19:27:16.468101 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4235 19:27:16.471065 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4236 19:27:16.474272 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4237 19:27:16.477807 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4238 19:27:16.477888
4239 19:27:16.481081 CA PerBit enable=1, Macro0, CA PI delay=33
4240 19:27:16.481162
4241 19:27:16.484767 [CBTSetCACLKResult] CA Dly = 33
4242 19:27:16.487752 CS Dly: 4 (0~35)
4243 19:27:16.487832 ==
4244 19:27:16.491060 Dram Type= 6, Freq= 0, CH_1, rank 1
4245 19:27:16.494344 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4246 19:27:16.494426 ==
4247 19:27:16.500677 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4248 19:27:16.504000 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4249 19:27:16.508449 [CA 0] Center 35 (5~66) winsize 62
4250 19:27:16.511937 [CA 1] Center 34 (4~65) winsize 62
4251 19:27:16.515188 [CA 2] Center 33 (3~64) winsize 62
4252 19:27:16.518606 [CA 3] Center 33 (3~64) winsize 62
4253 19:27:16.522237 [CA 4] Center 32 (2~63) winsize 62
4254 19:27:16.525024 [CA 5] Center 32 (2~63) winsize 62
4255 19:27:16.525105
4256 19:27:16.528308 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4257 19:27:16.528418
4258 19:27:16.531600 [CATrainingPosCal] consider 2 rank data
4259 19:27:16.535072 u2DelayCellTimex100 = 270/100 ps
4260 19:27:16.538394 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4261 19:27:16.544969 CA1 delay=35 (5~65),Diff = 3 PI (28 cell)
4262 19:27:16.547958 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4263 19:27:16.551521 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4264 19:27:16.554496 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4265 19:27:16.557867 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4266 19:27:16.557962
4267 19:27:16.561712 CA PerBit enable=1, Macro0, CA PI delay=32
4268 19:27:16.561793
4269 19:27:16.564443 [CBTSetCACLKResult] CA Dly = 32
4270 19:27:16.568070 CS Dly: 4 (0~35)
4271 19:27:16.568165
4272 19:27:16.571503 ----->DramcWriteLeveling(PI) begin...
4273 19:27:16.571586 ==
4274 19:27:16.574467 Dram Type= 6, Freq= 0, CH_1, rank 0
4275 19:27:16.577727 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4276 19:27:16.577808 ==
4277 19:27:16.581087 Write leveling (Byte 0): 27 => 27
4278 19:27:16.584626 Write leveling (Byte 1): 26 => 26
4279 19:27:16.587768 DramcWriteLeveling(PI) end<-----
4280 19:27:16.587852
4281 19:27:16.587915 ==
4282 19:27:16.590960 Dram Type= 6, Freq= 0, CH_1, rank 0
4283 19:27:16.594084 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4284 19:27:16.594180 ==
4285 19:27:16.597572 [Gating] SW mode calibration
4286 19:27:16.604299 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4287 19:27:16.610823 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4288 19:27:16.613993 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4289 19:27:16.617387 0 5 4 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
4290 19:27:16.623913 0 5 8 | B1->B0 | 3030 2b2b | 0 0 | (1 1) (1 1)
4291 19:27:16.627438 0 5 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4292 19:27:16.630566 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4293 19:27:16.637258 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4294 19:27:16.640797 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4295 19:27:16.643840 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4296 19:27:16.650451 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4297 19:27:16.654103 0 6 4 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
4298 19:27:16.657310 0 6 8 | B1->B0 | 3333 3e3e | 0 0 | (0 0) (0 0)
4299 19:27:16.663760 0 6 12 | B1->B0 | 4545 4646 | 0 0 | (1 1) (0 0)
4300 19:27:16.667203 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4301 19:27:16.670368 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4302 19:27:16.677261 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4303 19:27:16.680461 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4304 19:27:16.683600 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4305 19:27:16.690598 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4306 19:27:16.693575 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4307 19:27:16.697052 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4308 19:27:16.703336 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4309 19:27:16.706783 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4310 19:27:16.710153 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4311 19:27:16.717019 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4312 19:27:16.720282 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4313 19:27:16.723270 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4314 19:27:16.729800 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4315 19:27:16.733088 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4316 19:27:16.736375 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4317 19:27:16.743131 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4318 19:27:16.746368 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4319 19:27:16.749725 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4320 19:27:16.756135 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4321 19:27:16.759650 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4322 19:27:16.763146 Total UI for P1: 0, mck2ui 16
4323 19:27:16.766222 best dqsien dly found for B0: ( 0, 9, 2)
4324 19:27:16.769771 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4325 19:27:16.776137 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4326 19:27:16.779606 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4327 19:27:16.782622 Total UI for P1: 0, mck2ui 16
4328 19:27:16.786059 best dqsien dly found for B1: ( 0, 9, 12)
4329 19:27:16.789535 best DQS0 dly(MCK, UI, PI) = (0, 9, 2)
4330 19:27:16.792929 best DQS1 dly(MCK, UI, PI) = (0, 9, 12)
4331 19:27:16.793010
4332 19:27:16.796148 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 2)
4333 19:27:16.799177 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 12)
4334 19:27:16.802383 [Gating] SW calibration Done
4335 19:27:16.802472 ==
4336 19:27:16.805999 Dram Type= 6, Freq= 0, CH_1, rank 0
4337 19:27:16.808839 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4338 19:27:16.812342 ==
4339 19:27:16.812442 RX Vref Scan: 0
4340 19:27:16.812532
4341 19:27:16.815644 RX Vref 0 -> 0, step: 1
4342 19:27:16.815716
4343 19:27:16.819044 RX Delay -230 -> 252, step: 16
4344 19:27:16.822466 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4345 19:27:16.825692 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4346 19:27:16.829119 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4347 19:27:16.835734 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4348 19:27:16.838637 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4349 19:27:16.842649 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4350 19:27:16.845602 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4351 19:27:16.848655 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4352 19:27:16.855779 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4353 19:27:16.859060 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4354 19:27:16.861773 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4355 19:27:16.865207 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4356 19:27:16.871786 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4357 19:27:16.875098 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4358 19:27:16.878535 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4359 19:27:16.882031 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4360 19:27:16.882153 ==
4361 19:27:16.885302 Dram Type= 6, Freq= 0, CH_1, rank 0
4362 19:27:16.892126 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4363 19:27:16.892203 ==
4364 19:27:16.892266 DQS Delay:
4365 19:27:16.895036 DQS0 = 0, DQS1 = 0
4366 19:27:16.895130 DQM Delay:
4367 19:27:16.898478 DQM0 = 37, DQM1 = 32
4368 19:27:16.898554 DQ Delay:
4369 19:27:16.901787 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4370 19:27:16.905118 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4371 19:27:16.908278 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4372 19:27:16.911472 DQ12 =41, DQ13 =49, DQ14 =33, DQ15 =49
4373 19:27:16.911543
4374 19:27:16.911625
4375 19:27:16.911683 ==
4376 19:27:16.914582 Dram Type= 6, Freq= 0, CH_1, rank 0
4377 19:27:16.918214 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4378 19:27:16.918289 ==
4379 19:27:16.918354
4380 19:27:16.918422
4381 19:27:16.921319 TX Vref Scan disable
4382 19:27:16.924757 == TX Byte 0 ==
4383 19:27:16.927975 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4384 19:27:16.931231 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4385 19:27:16.934569 == TX Byte 1 ==
4386 19:27:16.938138 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4387 19:27:16.941473 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4388 19:27:16.941578 ==
4389 19:27:16.944383 Dram Type= 6, Freq= 0, CH_1, rank 0
4390 19:27:16.950915 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4391 19:27:16.951015 ==
4392 19:27:16.951122
4393 19:27:16.951212
4394 19:27:16.951305 TX Vref Scan disable
4395 19:27:16.955183 == TX Byte 0 ==
4396 19:27:16.958614 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4397 19:27:16.965206 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4398 19:27:16.965335 == TX Byte 1 ==
4399 19:27:16.968422 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4400 19:27:16.974842 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4401 19:27:16.974925
4402 19:27:16.974988 [DATLAT]
4403 19:27:16.975048 Freq=600, CH1 RK0
4404 19:27:16.975105
4405 19:27:16.978194 DATLAT Default: 0x9
4406 19:27:16.981608 0, 0xFFFF, sum = 0
4407 19:27:16.981703 1, 0xFFFF, sum = 0
4408 19:27:16.984928 2, 0xFFFF, sum = 0
4409 19:27:16.985012 3, 0xFFFF, sum = 0
4410 19:27:16.988176 4, 0xFFFF, sum = 0
4411 19:27:16.988258 5, 0xFFFF, sum = 0
4412 19:27:16.991369 6, 0xFFFF, sum = 0
4413 19:27:16.991451 7, 0x0, sum = 1
4414 19:27:16.994451 8, 0x0, sum = 2
4415 19:27:16.994533 9, 0x0, sum = 3
4416 19:27:16.994597 10, 0x0, sum = 4
4417 19:27:16.998041 best_step = 8
4418 19:27:16.998136
4419 19:27:16.998199 ==
4420 19:27:17.001560 Dram Type= 6, Freq= 0, CH_1, rank 0
4421 19:27:17.004839 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4422 19:27:17.004920 ==
4423 19:27:17.007964 RX Vref Scan: 1
4424 19:27:17.008048
4425 19:27:17.008110 RX Vref 0 -> 0, step: 1
4426 19:27:17.011510
4427 19:27:17.011606 RX Delay -195 -> 252, step: 8
4428 19:27:17.011669
4429 19:27:17.014669 Set Vref, RX VrefLevel [Byte0]: 53
4430 19:27:17.017875 [Byte1]: 52
4431 19:27:17.021997
4432 19:27:17.022104 Final RX Vref Byte 0 = 53 to rank0
4433 19:27:17.025423 Final RX Vref Byte 1 = 52 to rank0
4434 19:27:17.028704 Final RX Vref Byte 0 = 53 to rank1
4435 19:27:17.032095 Final RX Vref Byte 1 = 52 to rank1==
4436 19:27:17.035175 Dram Type= 6, Freq= 0, CH_1, rank 0
4437 19:27:17.041689 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4438 19:27:17.041771 ==
4439 19:27:17.041835 DQS Delay:
4440 19:27:17.045418 DQS0 = 0, DQS1 = 0
4441 19:27:17.045506 DQM Delay:
4442 19:27:17.045569 DQM0 = 37, DQM1 = 29
4443 19:27:17.048443 DQ Delay:
4444 19:27:17.051789 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =36
4445 19:27:17.055070 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4446 19:27:17.058224 DQ8 =12, DQ9 =16, DQ10 =32, DQ11 =20
4447 19:27:17.061436 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4448 19:27:17.061517
4449 19:27:17.061580
4450 19:27:17.068099 [DQSOSCAuto] RK0, (LSB)MR18= 0x7474, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
4451 19:27:17.071417 CH1 RK0: MR19=808, MR18=7474
4452 19:27:17.078405 CH1_RK0: MR19=0x808, MR18=0x7474, DQSOSC=388, MR23=63, INC=174, DEC=116
4453 19:27:17.078488
4454 19:27:17.081541 ----->DramcWriteLeveling(PI) begin...
4455 19:27:17.081623 ==
4456 19:27:17.084674 Dram Type= 6, Freq= 0, CH_1, rank 1
4457 19:27:17.088129 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4458 19:27:17.088211 ==
4459 19:27:17.091697 Write leveling (Byte 0): 26 => 26
4460 19:27:17.094638 Write leveling (Byte 1): 26 => 26
4461 19:27:17.098361 DramcWriteLeveling(PI) end<-----
4462 19:27:17.098443
4463 19:27:17.098505 ==
4464 19:27:17.101667 Dram Type= 6, Freq= 0, CH_1, rank 1
4465 19:27:17.104595 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4466 19:27:17.108151 ==
4467 19:27:17.108232 [Gating] SW mode calibration
4468 19:27:17.117819 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4469 19:27:17.121132 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4470 19:27:17.124738 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4471 19:27:17.130937 0 5 4 | B1->B0 | 3434 3030 | 1 0 | (1 1) (1 0)
4472 19:27:17.134351 0 5 8 | B1->B0 | 2f2f 2424 | 0 0 | (1 1) (0 0)
4473 19:27:17.137595 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4474 19:27:17.144742 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4475 19:27:17.147722 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4476 19:27:17.151137 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4477 19:27:17.157533 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4478 19:27:17.160852 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4479 19:27:17.164119 0 6 4 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
4480 19:27:17.170904 0 6 8 | B1->B0 | 3535 4141 | 0 1 | (1 1) (0 0)
4481 19:27:17.174148 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4482 19:27:17.177227 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4483 19:27:17.183795 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4484 19:27:17.187185 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4485 19:27:17.190808 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4486 19:27:17.197052 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4487 19:27:17.200780 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4488 19:27:17.204007 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 19:27:17.210579 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 19:27:17.213728 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 19:27:17.217042 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 19:27:17.223555 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 19:27:17.226818 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 19:27:17.230426 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 19:27:17.236794 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 19:27:17.240260 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 19:27:17.243654 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 19:27:17.250231 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 19:27:17.253641 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 19:27:17.256646 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 19:27:17.263249 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 19:27:17.266640 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4503 19:27:17.269820 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 19:27:17.276414 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4505 19:27:17.276496 Total UI for P1: 0, mck2ui 16
4506 19:27:17.282878 best dqsien dly found for B0: ( 0, 9, 6)
4507 19:27:17.286069 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4508 19:27:17.289728 Total UI for P1: 0, mck2ui 16
4509 19:27:17.293042 best dqsien dly found for B1: ( 0, 9, 8)
4510 19:27:17.296293 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4511 19:27:17.299531 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4512 19:27:17.299628
4513 19:27:17.302956 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4514 19:27:17.305811 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4515 19:27:17.309170 [Gating] SW calibration Done
4516 19:27:17.309250 ==
4517 19:27:17.312552 Dram Type= 6, Freq= 0, CH_1, rank 1
4518 19:27:17.316126 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4519 19:27:17.319592 ==
4520 19:27:17.319672 RX Vref Scan: 0
4521 19:27:17.319734
4522 19:27:17.322557 RX Vref 0 -> 0, step: 1
4523 19:27:17.322636
4524 19:27:17.325939 RX Delay -230 -> 252, step: 16
4525 19:27:17.329423 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4526 19:27:17.332660 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4527 19:27:17.336092 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4528 19:27:17.342782 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4529 19:27:17.345689 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4530 19:27:17.348844 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4531 19:27:17.352126 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4532 19:27:17.355542 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4533 19:27:17.362287 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4534 19:27:17.365143 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4535 19:27:17.368485 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4536 19:27:17.372294 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4537 19:27:17.378655 iDelay=218, Bit 12, Center 41 (-134 ~ 217) 352
4538 19:27:17.381609 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4539 19:27:17.385241 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4540 19:27:17.388411 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4541 19:27:17.391731 ==
4542 19:27:17.391811 Dram Type= 6, Freq= 0, CH_1, rank 1
4543 19:27:17.398468 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4544 19:27:17.398550 ==
4545 19:27:17.398614 DQS Delay:
4546 19:27:17.401670 DQS0 = 0, DQS1 = 0
4547 19:27:17.401766 DQM Delay:
4548 19:27:17.405130 DQM0 = 41, DQM1 = 33
4549 19:27:17.405211 DQ Delay:
4550 19:27:17.408215 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =41
4551 19:27:17.411617 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =33
4552 19:27:17.415310 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4553 19:27:17.418535 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4554 19:27:17.418616
4555 19:27:17.418679
4556 19:27:17.418738 ==
4557 19:27:17.422015 Dram Type= 6, Freq= 0, CH_1, rank 1
4558 19:27:17.425020 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4559 19:27:17.425102 ==
4560 19:27:17.425165
4561 19:27:17.425224
4562 19:27:17.428213 TX Vref Scan disable
4563 19:27:17.431719 == TX Byte 0 ==
4564 19:27:17.435113 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4565 19:27:17.437899 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4566 19:27:17.441216 == TX Byte 1 ==
4567 19:27:17.444578 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4568 19:27:17.447894 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4569 19:27:17.447975 ==
4570 19:27:17.451202 Dram Type= 6, Freq= 0, CH_1, rank 1
4571 19:27:17.457979 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4572 19:27:17.458100 ==
4573 19:27:17.458163
4574 19:27:17.458222
4575 19:27:17.458279 TX Vref Scan disable
4576 19:27:17.462033 == TX Byte 0 ==
4577 19:27:17.465224 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4578 19:27:17.472318 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4579 19:27:17.472399 == TX Byte 1 ==
4580 19:27:17.475061 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4581 19:27:17.481877 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4582 19:27:17.481985
4583 19:27:17.482086 [DATLAT]
4584 19:27:17.482146 Freq=600, CH1 RK1
4585 19:27:17.482203
4586 19:27:17.485382 DATLAT Default: 0x8
4587 19:27:17.485461 0, 0xFFFF, sum = 0
4588 19:27:17.488820 1, 0xFFFF, sum = 0
4589 19:27:17.491994 2, 0xFFFF, sum = 0
4590 19:27:17.492076 3, 0xFFFF, sum = 0
4591 19:27:17.494872 4, 0xFFFF, sum = 0
4592 19:27:17.494954 5, 0xFFFF, sum = 0
4593 19:27:17.498707 6, 0xFFFF, sum = 0
4594 19:27:17.498789 7, 0x0, sum = 1
4595 19:27:17.501696 8, 0x0, sum = 2
4596 19:27:17.501778 9, 0x0, sum = 3
4597 19:27:17.501865 10, 0x0, sum = 4
4598 19:27:17.505327 best_step = 8
4599 19:27:17.505407
4600 19:27:17.505471 ==
4601 19:27:17.508441 Dram Type= 6, Freq= 0, CH_1, rank 1
4602 19:27:17.511471 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4603 19:27:17.511553 ==
4604 19:27:17.515058 RX Vref Scan: 0
4605 19:27:17.515138
4606 19:27:17.515201 RX Vref 0 -> 0, step: 1
4607 19:27:17.515290
4608 19:27:17.517889 RX Delay -195 -> 252, step: 8
4609 19:27:17.525653 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4610 19:27:17.528908 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4611 19:27:17.532345 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4612 19:27:17.535575 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4613 19:27:17.542275 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4614 19:27:17.545642 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4615 19:27:17.548858 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4616 19:27:17.552470 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4617 19:27:17.555359 iDelay=205, Bit 8, Center 12 (-147 ~ 172) 320
4618 19:27:17.562298 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4619 19:27:17.565423 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4620 19:27:17.568892 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4621 19:27:17.572408 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4622 19:27:17.578805 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4623 19:27:17.582137 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4624 19:27:17.585436 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4625 19:27:17.585547 ==
4626 19:27:17.588791 Dram Type= 6, Freq= 0, CH_1, rank 1
4627 19:27:17.594943 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4628 19:27:17.595040 ==
4629 19:27:17.595118 DQS Delay:
4630 19:27:17.595177 DQS0 = 0, DQS1 = 0
4631 19:27:17.598333 DQM Delay:
4632 19:27:17.598414 DQM0 = 36, DQM1 = 29
4633 19:27:17.601909 DQ Delay:
4634 19:27:17.605288 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4635 19:27:17.608489 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =32
4636 19:27:17.611859 DQ8 =12, DQ9 =20, DQ10 =28, DQ11 =20
4637 19:27:17.615053 DQ12 =36, DQ13 =40, DQ14 =36, DQ15 =40
4638 19:27:17.615134
4639 19:27:17.615197
4640 19:27:17.621783 [DQSOSCAuto] RK1, (LSB)MR18= 0x5454, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
4641 19:27:17.624714 CH1 RK1: MR19=808, MR18=5454
4642 19:27:17.631521 CH1_RK1: MR19=0x808, MR18=0x5454, DQSOSC=393, MR23=63, INC=169, DEC=113
4643 19:27:17.635051 [RxdqsGatingPostProcess] freq 600
4644 19:27:17.638422 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4645 19:27:17.641614 Pre-setting of DQS Precalculation
4646 19:27:17.648111 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4647 19:27:17.654355 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4648 19:27:17.661173 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4649 19:27:17.661258
4650 19:27:17.661321
4651 19:27:17.664510 [Calibration Summary] 1200 Mbps
4652 19:27:17.664592 CH 0, Rank 0
4653 19:27:17.667954 SW Impedance : PASS
4654 19:27:17.671298 DUTY Scan : NO K
4655 19:27:17.671370 ZQ Calibration : PASS
4656 19:27:17.674551 Jitter Meter : NO K
4657 19:27:17.677574 CBT Training : PASS
4658 19:27:17.677653 Write leveling : PASS
4659 19:27:17.681258 RX DQS gating : PASS
4660 19:27:17.684218 RX DQ/DQS(RDDQC) : PASS
4661 19:27:17.684297 TX DQ/DQS : PASS
4662 19:27:17.687535 RX DATLAT : PASS
4663 19:27:17.690552 RX DQ/DQS(Engine): PASS
4664 19:27:17.690633 TX OE : NO K
4665 19:27:17.694136 All Pass.
4666 19:27:17.694218
4667 19:27:17.694281 CH 0, Rank 1
4668 19:27:17.697498 SW Impedance : PASS
4669 19:27:17.697579 DUTY Scan : NO K
4670 19:27:17.701108 ZQ Calibration : PASS
4671 19:27:17.704347 Jitter Meter : NO K
4672 19:27:17.704428 CBT Training : PASS
4673 19:27:17.707614 Write leveling : PASS
4674 19:27:17.710603 RX DQS gating : PASS
4675 19:27:17.710684 RX DQ/DQS(RDDQC) : PASS
4676 19:27:17.714307 TX DQ/DQS : PASS
4677 19:27:17.717165 RX DATLAT : PASS
4678 19:27:17.717250 RX DQ/DQS(Engine): PASS
4679 19:27:17.720674 TX OE : NO K
4680 19:27:17.720763 All Pass.
4681 19:27:17.720826
4682 19:27:17.724030 CH 1, Rank 0
4683 19:27:17.724149 SW Impedance : PASS
4684 19:27:17.726980 DUTY Scan : NO K
4685 19:27:17.727061 ZQ Calibration : PASS
4686 19:27:17.730527 Jitter Meter : NO K
4687 19:27:17.733840 CBT Training : PASS
4688 19:27:17.733920 Write leveling : PASS
4689 19:27:17.737488 RX DQS gating : PASS
4690 19:27:17.740512 RX DQ/DQS(RDDQC) : PASS
4691 19:27:17.740593 TX DQ/DQS : PASS
4692 19:27:17.743537 RX DATLAT : PASS
4693 19:27:17.747190 RX DQ/DQS(Engine): PASS
4694 19:27:17.747270 TX OE : NO K
4695 19:27:17.750618 All Pass.
4696 19:27:17.750718
4697 19:27:17.750783 CH 1, Rank 1
4698 19:27:17.753532 SW Impedance : PASS
4699 19:27:17.753612 DUTY Scan : NO K
4700 19:27:17.756860 ZQ Calibration : PASS
4701 19:27:17.760424 Jitter Meter : NO K
4702 19:27:17.760506 CBT Training : PASS
4703 19:27:17.763505 Write leveling : PASS
4704 19:27:17.766732 RX DQS gating : PASS
4705 19:27:17.766813 RX DQ/DQS(RDDQC) : PASS
4706 19:27:17.770066 TX DQ/DQS : PASS
4707 19:27:17.773643 RX DATLAT : PASS
4708 19:27:17.773731 RX DQ/DQS(Engine): PASS
4709 19:27:17.776758 TX OE : NO K
4710 19:27:17.776859 All Pass.
4711 19:27:17.776924
4712 19:27:17.780019 DramC Write-DBI off
4713 19:27:17.783490 PER_BANK_REFRESH: Hybrid Mode
4714 19:27:17.783572 TX_TRACKING: ON
4715 19:27:17.793628 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4716 19:27:17.796739 [FAST_K] Save calibration result to emmc
4717 19:27:17.799787 dramc_set_vcore_voltage set vcore to 662500
4718 19:27:17.803367 Read voltage for 933, 3
4719 19:27:17.803460 Vio18 = 0
4720 19:27:17.803530 Vcore = 662500
4721 19:27:17.806433 Vdram = 0
4722 19:27:17.806514 Vddq = 0
4723 19:27:17.806577 Vmddr = 0
4724 19:27:17.813316 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4725 19:27:17.816187 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4726 19:27:17.819785 MEM_TYPE=3, freq_sel=17
4727 19:27:17.822958 sv_algorithm_assistance_LP4_1600
4728 19:27:17.826156 ============ PULL DRAM RESETB DOWN ============
4729 19:27:17.829553 ========== PULL DRAM RESETB DOWN end =========
4730 19:27:17.836148 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4731 19:27:17.840122 ===================================
4732 19:27:17.840203 LPDDR4 DRAM CONFIGURATION
4733 19:27:17.843057 ===================================
4734 19:27:17.846491 EX_ROW_EN[0] = 0x0
4735 19:27:17.849674 EX_ROW_EN[1] = 0x0
4736 19:27:17.849755 LP4Y_EN = 0x0
4737 19:27:17.852934 WORK_FSP = 0x0
4738 19:27:17.853016 WL = 0x3
4739 19:27:17.855931 RL = 0x3
4740 19:27:17.856015 BL = 0x2
4741 19:27:17.859412 RPST = 0x0
4742 19:27:17.859495 RD_PRE = 0x0
4743 19:27:17.862852 WR_PRE = 0x1
4744 19:27:17.862933 WR_PST = 0x0
4745 19:27:17.866036 DBI_WR = 0x0
4746 19:27:17.866156 DBI_RD = 0x0
4747 19:27:17.869589 OTF = 0x1
4748 19:27:17.872687 ===================================
4749 19:27:17.875808 ===================================
4750 19:27:17.875889 ANA top config
4751 19:27:17.879464 ===================================
4752 19:27:17.882806 DLL_ASYNC_EN = 0
4753 19:27:17.886013 ALL_SLAVE_EN = 1
4754 19:27:17.889164 NEW_RANK_MODE = 1
4755 19:27:17.889246 DLL_IDLE_MODE = 1
4756 19:27:17.892412 LP45_APHY_COMB_EN = 1
4757 19:27:17.896105 TX_ODT_DIS = 1
4758 19:27:17.899076 NEW_8X_MODE = 1
4759 19:27:17.902406 ===================================
4760 19:27:17.905550 ===================================
4761 19:27:17.908844 data_rate = 1866
4762 19:27:17.908925 CKR = 1
4763 19:27:17.912282 DQ_P2S_RATIO = 8
4764 19:27:17.915450 ===================================
4765 19:27:17.918906 CA_P2S_RATIO = 8
4766 19:27:17.922523 DQ_CA_OPEN = 0
4767 19:27:17.925598 DQ_SEMI_OPEN = 0
4768 19:27:17.928978 CA_SEMI_OPEN = 0
4769 19:27:17.929060 CA_FULL_RATE = 0
4770 19:27:17.932396 DQ_CKDIV4_EN = 1
4771 19:27:17.935980 CA_CKDIV4_EN = 1
4772 19:27:17.938871 CA_PREDIV_EN = 0
4773 19:27:17.942206 PH8_DLY = 0
4774 19:27:17.945431 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4775 19:27:17.945511 DQ_AAMCK_DIV = 4
4776 19:27:17.948916 CA_AAMCK_DIV = 4
4777 19:27:17.952013 CA_ADMCK_DIV = 4
4778 19:27:17.955505 DQ_TRACK_CA_EN = 0
4779 19:27:17.958761 CA_PICK = 933
4780 19:27:17.962409 CA_MCKIO = 933
4781 19:27:17.965755 MCKIO_SEMI = 0
4782 19:27:17.965836 PLL_FREQ = 3732
4783 19:27:17.968951 DQ_UI_PI_RATIO = 32
4784 19:27:17.972341 CA_UI_PI_RATIO = 0
4785 19:27:17.975170 ===================================
4786 19:27:17.978893 ===================================
4787 19:27:17.981718 memory_type:LPDDR4
4788 19:27:17.981799 GP_NUM : 10
4789 19:27:17.985503 SRAM_EN : 1
4790 19:27:17.988837 MD32_EN : 0
4791 19:27:17.992285 ===================================
4792 19:27:17.992420 [ANA_INIT] >>>>>>>>>>>>>>
4793 19:27:17.995311 <<<<<< [CONFIGURE PHASE]: ANA_TX
4794 19:27:17.998242 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4795 19:27:18.001782 ===================================
4796 19:27:18.004929 data_rate = 1866,PCW = 0X8f00
4797 19:27:18.008355 ===================================
4798 19:27:18.011734 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4799 19:27:18.018039 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4800 19:27:18.025287 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4801 19:27:18.027964 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4802 19:27:18.031432 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4803 19:27:18.035015 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4804 19:27:18.038162 [ANA_INIT] flow start
4805 19:27:18.038257 [ANA_INIT] PLL >>>>>>>>
4806 19:27:18.041548 [ANA_INIT] PLL <<<<<<<<
4807 19:27:18.044573 [ANA_INIT] MIDPI >>>>>>>>
4808 19:27:18.044670 [ANA_INIT] MIDPI <<<<<<<<
4809 19:27:18.048052 [ANA_INIT] DLL >>>>>>>>
4810 19:27:18.051157 [ANA_INIT] flow end
4811 19:27:18.055040 ============ LP4 DIFF to SE enter ============
4812 19:27:18.058297 ============ LP4 DIFF to SE exit ============
4813 19:27:18.061471 [ANA_INIT] <<<<<<<<<<<<<
4814 19:27:18.065086 [Flow] Enable top DCM control >>>>>
4815 19:27:18.067860 [Flow] Enable top DCM control <<<<<
4816 19:27:18.071230 Enable DLL master slave shuffle
4817 19:27:18.074495 ==============================================================
4818 19:27:18.078169 Gating Mode config
4819 19:27:18.084678 ==============================================================
4820 19:27:18.084759 Config description:
4821 19:27:18.094360 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4822 19:27:18.101145 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4823 19:27:18.107655 SELPH_MODE 0: By rank 1: By Phase
4824 19:27:18.111368 ==============================================================
4825 19:27:18.114259 GAT_TRACK_EN = 1
4826 19:27:18.117326 RX_GATING_MODE = 2
4827 19:27:18.120932 RX_GATING_TRACK_MODE = 2
4828 19:27:18.124279 SELPH_MODE = 1
4829 19:27:18.127316 PICG_EARLY_EN = 1
4830 19:27:18.130630 VALID_LAT_VALUE = 1
4831 19:27:18.134425 ==============================================================
4832 19:27:18.137259 Enter into Gating configuration >>>>
4833 19:27:18.140767 Exit from Gating configuration <<<<
4834 19:27:18.144229 Enter into DVFS_PRE_config >>>>>
4835 19:27:18.157180 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4836 19:27:18.160759 Exit from DVFS_PRE_config <<<<<
4837 19:27:18.163680 Enter into PICG configuration >>>>
4838 19:27:18.163762 Exit from PICG configuration <<<<
4839 19:27:18.167390 [RX_INPUT] configuration >>>>>
4840 19:27:18.170460 [RX_INPUT] configuration <<<<<
4841 19:27:18.177505 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4842 19:27:18.180452 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4843 19:27:18.186865 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4844 19:27:18.194088 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4845 19:27:18.200405 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4846 19:27:18.206632 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4847 19:27:18.210047 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4848 19:27:18.213478 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4849 19:27:18.220036 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4850 19:27:18.223144 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4851 19:27:18.226742 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4852 19:27:18.230363 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4853 19:27:18.233075 ===================================
4854 19:27:18.236491 LPDDR4 DRAM CONFIGURATION
4855 19:27:18.239664 ===================================
4856 19:27:18.243017 EX_ROW_EN[0] = 0x0
4857 19:27:18.243111 EX_ROW_EN[1] = 0x0
4858 19:27:18.246378 LP4Y_EN = 0x0
4859 19:27:18.246446 WORK_FSP = 0x0
4860 19:27:18.249431 WL = 0x3
4861 19:27:18.249498 RL = 0x3
4862 19:27:18.252733 BL = 0x2
4863 19:27:18.256143 RPST = 0x0
4864 19:27:18.256224 RD_PRE = 0x0
4865 19:27:18.259267 WR_PRE = 0x1
4866 19:27:18.259348 WR_PST = 0x0
4867 19:27:18.262524 DBI_WR = 0x0
4868 19:27:18.262604 DBI_RD = 0x0
4869 19:27:18.265912 OTF = 0x1
4870 19:27:18.269265 ===================================
4871 19:27:18.272642 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4872 19:27:18.276010 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4873 19:27:18.279082 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4874 19:27:18.282586 ===================================
4875 19:27:18.285750 LPDDR4 DRAM CONFIGURATION
4876 19:27:18.289353 ===================================
4877 19:27:18.292884 EX_ROW_EN[0] = 0x10
4878 19:27:18.292964 EX_ROW_EN[1] = 0x0
4879 19:27:18.295582 LP4Y_EN = 0x0
4880 19:27:18.295662 WORK_FSP = 0x0
4881 19:27:18.299394 WL = 0x3
4882 19:27:18.299475 RL = 0x3
4883 19:27:18.302185 BL = 0x2
4884 19:27:18.305755 RPST = 0x0
4885 19:27:18.305836 RD_PRE = 0x0
4886 19:27:18.308956 WR_PRE = 0x1
4887 19:27:18.309037 WR_PST = 0x0
4888 19:27:18.312211 DBI_WR = 0x0
4889 19:27:18.312291 DBI_RD = 0x0
4890 19:27:18.315589 OTF = 0x1
4891 19:27:18.318857 ===================================
4892 19:27:18.322437 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4893 19:27:18.327670 nWR fixed to 30
4894 19:27:18.331019 [ModeRegInit_LP4] CH0 RK0
4895 19:27:18.331099 [ModeRegInit_LP4] CH0 RK1
4896 19:27:18.334517 [ModeRegInit_LP4] CH1 RK0
4897 19:27:18.337878 [ModeRegInit_LP4] CH1 RK1
4898 19:27:18.337984 match AC timing 8
4899 19:27:18.344618 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4900 19:27:18.347540 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4901 19:27:18.350874 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4902 19:27:18.357439 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4903 19:27:18.360891 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4904 19:27:18.360973 ==
4905 19:27:18.364377 Dram Type= 6, Freq= 0, CH_0, rank 0
4906 19:27:18.367513 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4907 19:27:18.367595 ==
4908 19:27:18.373981 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4909 19:27:18.380970 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4910 19:27:18.384093 [CA 0] Center 38 (8~69) winsize 62
4911 19:27:18.387053 [CA 1] Center 38 (8~69) winsize 62
4912 19:27:18.390548 [CA 2] Center 36 (6~67) winsize 62
4913 19:27:18.393775 [CA 3] Center 36 (6~66) winsize 61
4914 19:27:18.397161 [CA 4] Center 34 (4~65) winsize 62
4915 19:27:18.400597 [CA 5] Center 34 (4~65) winsize 62
4916 19:27:18.400678
4917 19:27:18.403845 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4918 19:27:18.403926
4919 19:27:18.407364 [CATrainingPosCal] consider 1 rank data
4920 19:27:18.411004 u2DelayCellTimex100 = 270/100 ps
4921 19:27:18.414228 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4922 19:27:18.417504 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4923 19:27:18.420714 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4924 19:27:18.423770 CA3 delay=36 (6~66),Diff = 2 PI (12 cell)
4925 19:27:18.427266 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4926 19:27:18.434285 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4927 19:27:18.434366
4928 19:27:18.437076 CA PerBit enable=1, Macro0, CA PI delay=34
4929 19:27:18.437157
4930 19:27:18.440534 [CBTSetCACLKResult] CA Dly = 34
4931 19:27:18.440617 CS Dly: 7 (0~38)
4932 19:27:18.440681 ==
4933 19:27:18.443724 Dram Type= 6, Freq= 0, CH_0, rank 1
4934 19:27:18.447121 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4935 19:27:18.450556 ==
4936 19:27:18.453686 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4937 19:27:18.460411 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4938 19:27:18.463577 [CA 0] Center 38 (8~69) winsize 62
4939 19:27:18.467115 [CA 1] Center 38 (7~69) winsize 63
4940 19:27:18.470658 [CA 2] Center 36 (5~67) winsize 63
4941 19:27:18.473480 [CA 3] Center 35 (5~66) winsize 62
4942 19:27:18.477026 [CA 4] Center 34 (4~65) winsize 62
4943 19:27:18.480469 [CA 5] Center 34 (4~65) winsize 62
4944 19:27:18.480550
4945 19:27:18.484292 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4946 19:27:18.484373
4947 19:27:18.486937 [CATrainingPosCal] consider 2 rank data
4948 19:27:18.490358 u2DelayCellTimex100 = 270/100 ps
4949 19:27:18.493664 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4950 19:27:18.497010 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4951 19:27:18.500200 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4952 19:27:18.503434 CA3 delay=36 (6~66),Diff = 2 PI (12 cell)
4953 19:27:18.510080 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4954 19:27:18.513641 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4955 19:27:18.513748
4956 19:27:18.517009 CA PerBit enable=1, Macro0, CA PI delay=34
4957 19:27:18.517091
4958 19:27:18.520385 [CBTSetCACLKResult] CA Dly = 34
4959 19:27:18.520456 CS Dly: 7 (0~39)
4960 19:27:18.520516
4961 19:27:18.523547 ----->DramcWriteLeveling(PI) begin...
4962 19:27:18.523629 ==
4963 19:27:18.526780 Dram Type= 6, Freq= 0, CH_0, rank 0
4964 19:27:18.533770 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4965 19:27:18.533852 ==
4966 19:27:18.536966 Write leveling (Byte 0): 29 => 29
4967 19:27:18.540103 Write leveling (Byte 1): 27 => 27
4968 19:27:18.540184 DramcWriteLeveling(PI) end<-----
4969 19:27:18.540247
4970 19:27:18.543634 ==
4971 19:27:18.546893 Dram Type= 6, Freq= 0, CH_0, rank 0
4972 19:27:18.550098 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4973 19:27:18.550179 ==
4974 19:27:18.553663 [Gating] SW mode calibration
4975 19:27:18.559794 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4976 19:27:18.563204 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4977 19:27:18.569723 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4978 19:27:18.572887 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4979 19:27:18.576344 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4980 19:27:18.582758 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4981 19:27:18.586426 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4982 19:27:18.589877 0 10 20 | B1->B0 | 3434 3131 | 1 0 | (0 1) (0 0)
4983 19:27:18.596225 0 10 24 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (1 0)
4984 19:27:18.599251 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4985 19:27:18.602663 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4986 19:27:18.609322 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4987 19:27:18.612681 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4988 19:27:18.615754 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4989 19:27:18.622570 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4990 19:27:18.625851 0 11 20 | B1->B0 | 2a2a 3333 | 0 0 | (0 0) (0 0)
4991 19:27:18.629207 0 11 24 | B1->B0 | 3939 4242 | 1 0 | (0 0) (0 0)
4992 19:27:18.635598 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4993 19:27:18.639341 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4994 19:27:18.642477 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4995 19:27:18.648738 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4996 19:27:18.651933 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4997 19:27:18.655551 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4998 19:27:18.662465 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4999 19:27:18.665387 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5000 19:27:18.668652 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5001 19:27:18.675502 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5002 19:27:18.678926 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5003 19:27:18.681878 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5004 19:27:18.688800 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5005 19:27:18.691890 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5006 19:27:18.695050 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5007 19:27:18.701639 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5008 19:27:18.705481 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5009 19:27:18.708411 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5010 19:27:18.714833 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5011 19:27:18.718353 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5012 19:27:18.721801 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5013 19:27:18.728371 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5014 19:27:18.731332 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5015 19:27:18.734702 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5016 19:27:18.737853 Total UI for P1: 0, mck2ui 16
5017 19:27:18.741141 best dqsien dly found for B0: ( 0, 14, 20)
5018 19:27:18.748182 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5019 19:27:18.748265 Total UI for P1: 0, mck2ui 16
5020 19:27:18.754484 best dqsien dly found for B1: ( 0, 14, 22)
5021 19:27:18.757795 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
5022 19:27:18.761237 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
5023 19:27:18.761339
5024 19:27:18.764553 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
5025 19:27:18.767847 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
5026 19:27:18.771605 [Gating] SW calibration Done
5027 19:27:18.771679 ==
5028 19:27:18.774373 Dram Type= 6, Freq= 0, CH_0, rank 0
5029 19:27:18.777696 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5030 19:27:18.777797 ==
5031 19:27:18.780732 RX Vref Scan: 0
5032 19:27:18.780831
5033 19:27:18.780920 RX Vref 0 -> 0, step: 1
5034 19:27:18.784137
5035 19:27:18.784242 RX Delay -80 -> 252, step: 8
5036 19:27:18.790991 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5037 19:27:18.794258 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5038 19:27:18.797668 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5039 19:27:18.800721 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5040 19:27:18.804434 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5041 19:27:18.807829 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5042 19:27:18.813812 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5043 19:27:18.817500 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5044 19:27:18.820827 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5045 19:27:18.824127 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5046 19:27:18.827664 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5047 19:27:18.830407 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5048 19:27:18.837131 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5049 19:27:18.840620 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5050 19:27:18.843634 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5051 19:27:18.847410 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5052 19:27:18.847488 ==
5053 19:27:18.850678 Dram Type= 6, Freq= 0, CH_0, rank 0
5054 19:27:18.857279 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5055 19:27:18.857380 ==
5056 19:27:18.857481 DQS Delay:
5057 19:27:18.857569 DQS0 = 0, DQS1 = 0
5058 19:27:18.860328 DQM Delay:
5059 19:27:18.860423 DQM0 = 95, DQM1 = 87
5060 19:27:18.863902 DQ Delay:
5061 19:27:18.867126 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5062 19:27:18.870290 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =107
5063 19:27:18.873403 DQ8 =75, DQ9 =71, DQ10 =87, DQ11 =83
5064 19:27:18.877069 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5065 19:27:18.877174
5066 19:27:18.877246
5067 19:27:18.877305 ==
5068 19:27:18.880076 Dram Type= 6, Freq= 0, CH_0, rank 0
5069 19:27:18.883852 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5070 19:27:18.883949 ==
5071 19:27:18.884046
5072 19:27:18.884141
5073 19:27:18.887195 TX Vref Scan disable
5074 19:27:18.887294 == TX Byte 0 ==
5075 19:27:18.893183 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5076 19:27:18.896636 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5077 19:27:18.896722 == TX Byte 1 ==
5078 19:27:18.903131 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5079 19:27:18.906907 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5080 19:27:18.906997 ==
5081 19:27:18.909805 Dram Type= 6, Freq= 0, CH_0, rank 0
5082 19:27:18.913084 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5083 19:27:18.913180 ==
5084 19:27:18.913278
5085 19:27:18.916377
5086 19:27:18.916472 TX Vref Scan disable
5087 19:27:18.919700 == TX Byte 0 ==
5088 19:27:18.923142 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5089 19:27:18.926283 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5090 19:27:18.929526 == TX Byte 1 ==
5091 19:27:18.932989 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5092 19:27:18.939630 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5093 19:27:18.939729
5094 19:27:18.939817 [DATLAT]
5095 19:27:18.939914 Freq=933, CH0 RK0
5096 19:27:18.940001
5097 19:27:18.943040 DATLAT Default: 0xd
5098 19:27:18.943139 0, 0xFFFF, sum = 0
5099 19:27:18.946134 1, 0xFFFF, sum = 0
5100 19:27:18.949413 2, 0xFFFF, sum = 0
5101 19:27:18.949528 3, 0xFFFF, sum = 0
5102 19:27:18.952753 4, 0xFFFF, sum = 0
5103 19:27:18.952862 5, 0xFFFF, sum = 0
5104 19:27:18.956093 6, 0xFFFF, sum = 0
5105 19:27:18.956179 7, 0xFFFF, sum = 0
5106 19:27:18.959442 8, 0xFFFF, sum = 0
5107 19:27:18.959539 9, 0xFFFF, sum = 0
5108 19:27:18.962580 10, 0x0, sum = 1
5109 19:27:18.962688 11, 0x0, sum = 2
5110 19:27:18.965971 12, 0x0, sum = 3
5111 19:27:18.966107 13, 0x0, sum = 4
5112 19:27:18.966174 best_step = 11
5113 19:27:18.969170
5114 19:27:18.969250 ==
5115 19:27:18.972743 Dram Type= 6, Freq= 0, CH_0, rank 0
5116 19:27:18.976408 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5117 19:27:18.976490 ==
5118 19:27:18.976553 RX Vref Scan: 1
5119 19:27:18.976611
5120 19:27:18.979100 RX Vref 0 -> 0, step: 1
5121 19:27:18.979179
5122 19:27:18.982280 RX Delay -69 -> 252, step: 4
5123 19:27:18.982361
5124 19:27:18.986217 Set Vref, RX VrefLevel [Byte0]: 51
5125 19:27:18.988998 [Byte1]: 49
5126 19:27:18.992305
5127 19:27:18.992402 Final RX Vref Byte 0 = 51 to rank0
5128 19:27:18.996111 Final RX Vref Byte 1 = 49 to rank0
5129 19:27:18.998879 Final RX Vref Byte 0 = 51 to rank1
5130 19:27:19.002273 Final RX Vref Byte 1 = 49 to rank1==
5131 19:27:19.005460 Dram Type= 6, Freq= 0, CH_0, rank 0
5132 19:27:19.012567 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5133 19:27:19.012648 ==
5134 19:27:19.012709 DQS Delay:
5135 19:27:19.015415 DQS0 = 0, DQS1 = 0
5136 19:27:19.015483 DQM Delay:
5137 19:27:19.015566 DQM0 = 97, DQM1 = 87
5138 19:27:19.018708 DQ Delay:
5139 19:27:19.022162 DQ0 =92, DQ1 =98, DQ2 =96, DQ3 =94
5140 19:27:19.025613 DQ4 =102, DQ5 =88, DQ6 =106, DQ7 =102
5141 19:27:19.028882 DQ8 =78, DQ9 =72, DQ10 =86, DQ11 =78
5142 19:27:19.032083 DQ12 =94, DQ13 =94, DQ14 =98, DQ15 =96
5143 19:27:19.032151
5144 19:27:19.032210
5145 19:27:19.038551 [DQSOSCAuto] RK0, (LSB)MR18= 0x2323, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
5146 19:27:19.041907 CH0 RK0: MR19=505, MR18=2323
5147 19:27:19.048824 CH0_RK0: MR19=0x505, MR18=0x2323, DQSOSC=410, MR23=63, INC=64, DEC=42
5148 19:27:19.048930
5149 19:27:19.051954 ----->DramcWriteLeveling(PI) begin...
5150 19:27:19.052056 ==
5151 19:27:19.055577 Dram Type= 6, Freq= 0, CH_0, rank 1
5152 19:27:19.058395 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5153 19:27:19.058476 ==
5154 19:27:19.061796 Write leveling (Byte 0): 27 => 27
5155 19:27:19.065094 Write leveling (Byte 1): 26 => 26
5156 19:27:19.068664 DramcWriteLeveling(PI) end<-----
5157 19:27:19.068759
5158 19:27:19.068845 ==
5159 19:27:19.071914 Dram Type= 6, Freq= 0, CH_0, rank 1
5160 19:27:19.075149 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5161 19:27:19.078365 ==
5162 19:27:19.078439 [Gating] SW mode calibration
5163 19:27:19.084959 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5164 19:27:19.091805 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5165 19:27:19.095223 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5166 19:27:19.101306 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5167 19:27:19.104860 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5168 19:27:19.108356 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5169 19:27:19.114528 0 10 16 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5170 19:27:19.118167 0 10 20 | B1->B0 | 2f2f 2828 | 1 0 | (1 1) (0 0)
5171 19:27:19.121053 0 10 24 | B1->B0 | 2525 2323 | 0 0 | (1 1) (0 0)
5172 19:27:19.128075 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5173 19:27:19.131180 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5174 19:27:19.134639 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5175 19:27:19.141283 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5176 19:27:19.144484 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5177 19:27:19.147837 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5178 19:27:19.154368 0 11 20 | B1->B0 | 2828 3333 | 0 0 | (0 0) (1 1)
5179 19:27:19.157844 0 11 24 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
5180 19:27:19.161054 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5181 19:27:19.167853 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5182 19:27:19.170937 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5183 19:27:19.174816 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5184 19:27:19.180760 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5185 19:27:19.183960 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5186 19:27:19.187672 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5187 19:27:19.193922 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 19:27:19.197342 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 19:27:19.200452 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 19:27:19.207171 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 19:27:19.210754 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 19:27:19.213754 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 19:27:19.220251 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 19:27:19.223545 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 19:27:19.226720 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 19:27:19.233642 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 19:27:19.236855 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 19:27:19.240296 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 19:27:19.246802 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 19:27:19.250199 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 19:27:19.253038 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5202 19:27:19.259923 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5203 19:27:19.263344 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5204 19:27:19.266344 Total UI for P1: 0, mck2ui 16
5205 19:27:19.269579 best dqsien dly found for B0: ( 0, 14, 20)
5206 19:27:19.273301 Total UI for P1: 0, mck2ui 16
5207 19:27:19.276411 best dqsien dly found for B1: ( 0, 14, 18)
5208 19:27:19.279933 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
5209 19:27:19.282805 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5210 19:27:19.282909
5211 19:27:19.286470 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
5212 19:27:19.289448 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5213 19:27:19.293119 [Gating] SW calibration Done
5214 19:27:19.293193 ==
5215 19:27:19.296254 Dram Type= 6, Freq= 0, CH_0, rank 1
5216 19:27:19.299780 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5217 19:27:19.302923 ==
5218 19:27:19.302995 RX Vref Scan: 0
5219 19:27:19.303055
5220 19:27:19.306426 RX Vref 0 -> 0, step: 1
5221 19:27:19.306494
5222 19:27:19.309785 RX Delay -80 -> 252, step: 8
5223 19:27:19.312966 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5224 19:27:19.315912 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5225 19:27:19.319398 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5226 19:27:19.322558 iDelay=208, Bit 3, Center 91 (0 ~ 183) 184
5227 19:27:19.326047 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5228 19:27:19.332687 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5229 19:27:19.335997 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5230 19:27:19.339518 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5231 19:27:19.342559 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5232 19:27:19.346344 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5233 19:27:19.352746 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5234 19:27:19.355786 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5235 19:27:19.359350 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5236 19:27:19.362434 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5237 19:27:19.365995 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5238 19:27:19.369652 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5239 19:27:19.372211 ==
5240 19:27:19.375554 Dram Type= 6, Freq= 0, CH_0, rank 1
5241 19:27:19.379406 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5242 19:27:19.379502 ==
5243 19:27:19.379593 DQS Delay:
5244 19:27:19.381937 DQS0 = 0, DQS1 = 0
5245 19:27:19.382053 DQM Delay:
5246 19:27:19.385700 DQM0 = 96, DQM1 = 85
5247 19:27:19.385800 DQ Delay:
5248 19:27:19.388534 DQ0 =91, DQ1 =99, DQ2 =95, DQ3 =91
5249 19:27:19.391767 DQ4 =99, DQ5 =83, DQ6 =103, DQ7 =107
5250 19:27:19.395401 DQ8 =71, DQ9 =71, DQ10 =87, DQ11 =75
5251 19:27:19.398834 DQ12 =95, DQ13 =91, DQ14 =95, DQ15 =95
5252 19:27:19.398933
5253 19:27:19.399024
5254 19:27:19.399111 ==
5255 19:27:19.402192 Dram Type= 6, Freq= 0, CH_0, rank 1
5256 19:27:19.405159 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5257 19:27:19.405258 ==
5258 19:27:19.405346
5259 19:27:19.408337
5260 19:27:19.408415 TX Vref Scan disable
5261 19:27:19.411809 == TX Byte 0 ==
5262 19:27:19.414823 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5263 19:27:19.418273 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5264 19:27:19.421503 == TX Byte 1 ==
5265 19:27:19.424849 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5266 19:27:19.428486 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5267 19:27:19.431458 ==
5268 19:27:19.431529 Dram Type= 6, Freq= 0, CH_0, rank 1
5269 19:27:19.437999 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5270 19:27:19.438132 ==
5271 19:27:19.438220
5272 19:27:19.438313
5273 19:27:19.441203 TX Vref Scan disable
5274 19:27:19.441303 == TX Byte 0 ==
5275 19:27:19.448084 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5276 19:27:19.451451 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5277 19:27:19.451530 == TX Byte 1 ==
5278 19:27:19.458056 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5279 19:27:19.461443 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5280 19:27:19.461550
5281 19:27:19.461637 [DATLAT]
5282 19:27:19.464525 Freq=933, CH0 RK1
5283 19:27:19.464616
5284 19:27:19.464709 DATLAT Default: 0xb
5285 19:27:19.468207 0, 0xFFFF, sum = 0
5286 19:27:19.468308 1, 0xFFFF, sum = 0
5287 19:27:19.471441 2, 0xFFFF, sum = 0
5288 19:27:19.471545 3, 0xFFFF, sum = 0
5289 19:27:19.474314 4, 0xFFFF, sum = 0
5290 19:27:19.474419 5, 0xFFFF, sum = 0
5291 19:27:19.477749 6, 0xFFFF, sum = 0
5292 19:27:19.477850 7, 0xFFFF, sum = 0
5293 19:27:19.481112 8, 0xFFFF, sum = 0
5294 19:27:19.484385 9, 0xFFFF, sum = 0
5295 19:27:19.484488 10, 0x0, sum = 1
5296 19:27:19.484581 11, 0x0, sum = 2
5297 19:27:19.487961 12, 0x0, sum = 3
5298 19:27:19.488064 13, 0x0, sum = 4
5299 19:27:19.491175 best_step = 11
5300 19:27:19.491270
5301 19:27:19.491358 ==
5302 19:27:19.494414 Dram Type= 6, Freq= 0, CH_0, rank 1
5303 19:27:19.497992 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5304 19:27:19.498131 ==
5305 19:27:19.500933 RX Vref Scan: 0
5306 19:27:19.501031
5307 19:27:19.501121 RX Vref 0 -> 0, step: 1
5308 19:27:19.501207
5309 19:27:19.504111 RX Delay -69 -> 252, step: 4
5310 19:27:19.511538 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5311 19:27:19.514945 iDelay=203, Bit 1, Center 96 (-1 ~ 194) 196
5312 19:27:19.518094 iDelay=203, Bit 2, Center 96 (3 ~ 190) 188
5313 19:27:19.521485 iDelay=203, Bit 3, Center 92 (3 ~ 182) 180
5314 19:27:19.524622 iDelay=203, Bit 4, Center 102 (11 ~ 194) 184
5315 19:27:19.531646 iDelay=203, Bit 5, Center 90 (-1 ~ 182) 184
5316 19:27:19.534882 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5317 19:27:19.538235 iDelay=203, Bit 7, Center 108 (15 ~ 202) 188
5318 19:27:19.541156 iDelay=203, Bit 8, Center 74 (-13 ~ 162) 176
5319 19:27:19.544552 iDelay=203, Bit 9, Center 72 (-17 ~ 162) 180
5320 19:27:19.551278 iDelay=203, Bit 10, Center 86 (-9 ~ 182) 192
5321 19:27:19.554998 iDelay=203, Bit 11, Center 78 (-9 ~ 166) 176
5322 19:27:19.557913 iDelay=203, Bit 12, Center 92 (3 ~ 182) 180
5323 19:27:19.560838 iDelay=203, Bit 13, Center 90 (-1 ~ 182) 184
5324 19:27:19.564373 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5325 19:27:19.567748 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5326 19:27:19.571362 ==
5327 19:27:19.574171 Dram Type= 6, Freq= 0, CH_0, rank 1
5328 19:27:19.577767 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5329 19:27:19.577868 ==
5330 19:27:19.577974 DQS Delay:
5331 19:27:19.580753 DQS0 = 0, DQS1 = 0
5332 19:27:19.580868 DQM Delay:
5333 19:27:19.583894 DQM0 = 97, DQM1 = 85
5334 19:27:19.583992 DQ Delay:
5335 19:27:19.587864 DQ0 =92, DQ1 =96, DQ2 =96, DQ3 =92
5336 19:27:19.590925 DQ4 =102, DQ5 =90, DQ6 =104, DQ7 =108
5337 19:27:19.594374 DQ8 =74, DQ9 =72, DQ10 =86, DQ11 =78
5338 19:27:19.597687 DQ12 =92, DQ13 =90, DQ14 =98, DQ15 =96
5339 19:27:19.597797
5340 19:27:19.597886
5341 19:27:19.603751 [DQSOSCAuto] RK1, (LSB)MR18= 0x2a2a, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 408 ps
5342 19:27:19.607447 CH0 RK1: MR19=505, MR18=2A2A
5343 19:27:19.613815 CH0_RK1: MR19=0x505, MR18=0x2A2A, DQSOSC=408, MR23=63, INC=65, DEC=43
5344 19:27:19.617451 [RxdqsGatingPostProcess] freq 933
5345 19:27:19.623460 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5346 19:27:19.626988 Pre-setting of DQS Precalculation
5347 19:27:19.630244 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5348 19:27:19.630323 ==
5349 19:27:19.633622 Dram Type= 6, Freq= 0, CH_1, rank 0
5350 19:27:19.636672 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5351 19:27:19.640118 ==
5352 19:27:19.643796 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5353 19:27:19.650245 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5354 19:27:19.653333 [CA 0] Center 37 (7~68) winsize 62
5355 19:27:19.656926 [CA 1] Center 37 (6~68) winsize 63
5356 19:27:19.660051 [CA 2] Center 34 (4~65) winsize 62
5357 19:27:19.663328 [CA 3] Center 34 (4~65) winsize 62
5358 19:27:19.666618 [CA 4] Center 33 (2~64) winsize 63
5359 19:27:19.670189 [CA 5] Center 33 (2~64) winsize 63
5360 19:27:19.670303
5361 19:27:19.673180 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5362 19:27:19.673290
5363 19:27:19.676789 [CATrainingPosCal] consider 1 rank data
5364 19:27:19.680150 u2DelayCellTimex100 = 270/100 ps
5365 19:27:19.683350 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5366 19:27:19.686415 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5367 19:27:19.690002 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5368 19:27:19.693314 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5369 19:27:19.700058 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5370 19:27:19.702871 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
5371 19:27:19.702951
5372 19:27:19.706263 CA PerBit enable=1, Macro0, CA PI delay=33
5373 19:27:19.706342
5374 19:27:19.709539 [CBTSetCACLKResult] CA Dly = 33
5375 19:27:19.709627 CS Dly: 5 (0~36)
5376 19:27:19.709689 ==
5377 19:27:19.713059 Dram Type= 6, Freq= 0, CH_1, rank 1
5378 19:27:19.719588 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5379 19:27:19.719668 ==
5380 19:27:19.722882 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5381 19:27:19.729295 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5382 19:27:19.732954 [CA 0] Center 37 (6~68) winsize 63
5383 19:27:19.736053 [CA 1] Center 37 (6~68) winsize 63
5384 19:27:19.739491 [CA 2] Center 34 (4~65) winsize 62
5385 19:27:19.742801 [CA 3] Center 34 (4~65) winsize 62
5386 19:27:19.746286 [CA 4] Center 33 (3~64) winsize 62
5387 19:27:19.749422 [CA 5] Center 33 (3~63) winsize 61
5388 19:27:19.749501
5389 19:27:19.752477 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5390 19:27:19.752557
5391 19:27:19.755772 [CATrainingPosCal] consider 2 rank data
5392 19:27:19.759156 u2DelayCellTimex100 = 270/100 ps
5393 19:27:19.762458 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5394 19:27:19.766077 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5395 19:27:19.772835 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5396 19:27:19.775977 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5397 19:27:19.780779 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5398 19:27:19.782472 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5399 19:27:19.782577
5400 19:27:19.785882 CA PerBit enable=1, Macro0, CA PI delay=33
5401 19:27:19.785982
5402 19:27:19.788976 [CBTSetCACLKResult] CA Dly = 33
5403 19:27:19.789071 CS Dly: 5 (0~37)
5404 19:27:19.789139
5405 19:27:19.792423 ----->DramcWriteLeveling(PI) begin...
5406 19:27:19.795455 ==
5407 19:27:19.798834 Dram Type= 6, Freq= 0, CH_1, rank 0
5408 19:27:19.802178 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5409 19:27:19.802279 ==
5410 19:27:19.805637 Write leveling (Byte 0): 23 => 23
5411 19:27:19.809024 Write leveling (Byte 1): 27 => 27
5412 19:27:19.812118 DramcWriteLeveling(PI) end<-----
5413 19:27:19.812214
5414 19:27:19.812301 ==
5415 19:27:19.815498 Dram Type= 6, Freq= 0, CH_1, rank 0
5416 19:27:19.819172 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5417 19:27:19.819270 ==
5418 19:27:19.822101 [Gating] SW mode calibration
5419 19:27:19.828963 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5420 19:27:19.835345 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5421 19:27:19.838711 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5422 19:27:19.841936 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5423 19:27:19.848671 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5424 19:27:19.851992 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5425 19:27:19.855430 0 10 16 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 1)
5426 19:27:19.861800 0 10 20 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
5427 19:27:19.865250 0 10 24 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
5428 19:27:19.868569 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5429 19:27:19.874862 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5430 19:27:19.878338 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5431 19:27:19.882053 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5432 19:27:19.888454 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5433 19:27:19.891597 0 11 16 | B1->B0 | 2323 3131 | 0 0 | (0 0) (1 1)
5434 19:27:19.895079 0 11 20 | B1->B0 | 2c2c 4545 | 0 0 | (0 0) (0 0)
5435 19:27:19.901811 0 11 24 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
5436 19:27:19.904823 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5437 19:27:19.907872 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5438 19:27:19.914411 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5439 19:27:19.917920 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5440 19:27:19.921128 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5441 19:27:19.927740 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5442 19:27:19.931245 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5443 19:27:19.934561 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5444 19:27:19.937687 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5445 19:27:19.944277 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5446 19:27:19.947561 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5447 19:27:19.954324 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5448 19:27:19.957405 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5449 19:27:19.960867 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5450 19:27:19.967702 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5451 19:27:19.971067 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5452 19:27:19.973780 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5453 19:27:19.980407 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5454 19:27:19.984197 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5455 19:27:19.987134 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5456 19:27:19.990794 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5457 19:27:19.997361 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5458 19:27:20.000628 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5459 19:27:20.003985 Total UI for P1: 0, mck2ui 16
5460 19:27:20.007046 best dqsien dly found for B0: ( 0, 14, 18)
5461 19:27:20.010504 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5462 19:27:20.013738 Total UI for P1: 0, mck2ui 16
5463 19:27:20.016935 best dqsien dly found for B1: ( 0, 14, 20)
5464 19:27:20.020181 best DQS0 dly(MCK, UI, PI) = (0, 14, 18)
5465 19:27:20.026859 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5466 19:27:20.026967
5467 19:27:20.030096 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 18)
5468 19:27:20.033642 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5469 19:27:20.037109 [Gating] SW calibration Done
5470 19:27:20.037210 ==
5471 19:27:20.040350 Dram Type= 6, Freq= 0, CH_1, rank 0
5472 19:27:20.043608 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5473 19:27:20.043707 ==
5474 19:27:20.046879 RX Vref Scan: 0
5475 19:27:20.046975
5476 19:27:20.047073 RX Vref 0 -> 0, step: 1
5477 19:27:20.047159
5478 19:27:20.050333 RX Delay -80 -> 252, step: 8
5479 19:27:20.053579 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5480 19:27:20.056900 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5481 19:27:20.063702 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5482 19:27:20.066501 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5483 19:27:20.070120 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5484 19:27:20.073366 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5485 19:27:20.076367 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5486 19:27:20.079890 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5487 19:27:20.086372 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5488 19:27:20.089941 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5489 19:27:20.093269 iDelay=208, Bit 10, Center 87 (-16 ~ 191) 208
5490 19:27:20.096378 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5491 19:27:20.103119 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5492 19:27:20.106186 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5493 19:27:20.109262 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5494 19:27:20.112594 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5495 19:27:20.112696 ==
5496 19:27:20.115955 Dram Type= 6, Freq= 0, CH_1, rank 0
5497 19:27:20.119474 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5498 19:27:20.123165 ==
5499 19:27:20.123238 DQS Delay:
5500 19:27:20.123299 DQS0 = 0, DQS1 = 0
5501 19:27:20.126282 DQM Delay:
5502 19:27:20.126364 DQM0 = 94, DQM1 = 85
5503 19:27:20.129378 DQ Delay:
5504 19:27:20.129479 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5505 19:27:20.132575 DQ4 =95, DQ5 =103, DQ6 =99, DQ7 =91
5506 19:27:20.135996 DQ8 =71, DQ9 =75, DQ10 =87, DQ11 =75
5507 19:27:20.139338 DQ12 =95, DQ13 =99, DQ14 =91, DQ15 =91
5508 19:27:20.139417
5509 19:27:20.142485
5510 19:27:20.142589 ==
5511 19:27:20.145933 Dram Type= 6, Freq= 0, CH_1, rank 0
5512 19:27:20.149155 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5513 19:27:20.149251 ==
5514 19:27:20.149348
5515 19:27:20.149436
5516 19:27:20.152527 TX Vref Scan disable
5517 19:27:20.152611 == TX Byte 0 ==
5518 19:27:20.159266 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5519 19:27:20.162540 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5520 19:27:20.162614 == TX Byte 1 ==
5521 19:27:20.169554 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5522 19:27:20.172658 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5523 19:27:20.172727 ==
5524 19:27:20.175886 Dram Type= 6, Freq= 0, CH_1, rank 0
5525 19:27:20.179465 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5526 19:27:20.179536 ==
5527 19:27:20.179596
5528 19:27:20.179652
5529 19:27:20.182416 TX Vref Scan disable
5530 19:27:20.185842 == TX Byte 0 ==
5531 19:27:20.189316 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5532 19:27:20.192604 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5533 19:27:20.195903 == TX Byte 1 ==
5534 19:27:20.199227 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5535 19:27:20.202336 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5536 19:27:20.202416
5537 19:27:20.205783 [DATLAT]
5538 19:27:20.205862 Freq=933, CH1 RK0
5539 19:27:20.205924
5540 19:27:20.209399 DATLAT Default: 0xd
5541 19:27:20.209478 0, 0xFFFF, sum = 0
5542 19:27:20.212649 1, 0xFFFF, sum = 0
5543 19:27:20.212737 2, 0xFFFF, sum = 0
5544 19:27:20.215502 3, 0xFFFF, sum = 0
5545 19:27:20.215582 4, 0xFFFF, sum = 0
5546 19:27:20.219287 5, 0xFFFF, sum = 0
5547 19:27:20.219368 6, 0xFFFF, sum = 0
5548 19:27:20.222533 7, 0xFFFF, sum = 0
5549 19:27:20.222630 8, 0xFFFF, sum = 0
5550 19:27:20.225959 9, 0xFFFF, sum = 0
5551 19:27:20.226063 10, 0x0, sum = 1
5552 19:27:20.228852 11, 0x0, sum = 2
5553 19:27:20.228932 12, 0x0, sum = 3
5554 19:27:20.232149 13, 0x0, sum = 4
5555 19:27:20.232231 best_step = 11
5556 19:27:20.232293
5557 19:27:20.232351 ==
5558 19:27:20.235873 Dram Type= 6, Freq= 0, CH_1, rank 0
5559 19:27:20.242570 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5560 19:27:20.242651 ==
5561 19:27:20.242713 RX Vref Scan: 1
5562 19:27:20.242771
5563 19:27:20.246066 RX Vref 0 -> 0, step: 1
5564 19:27:20.246173
5565 19:27:20.249128 RX Delay -69 -> 252, step: 4
5566 19:27:20.249208
5567 19:27:20.252588 Set Vref, RX VrefLevel [Byte0]: 53
5568 19:27:20.255704 [Byte1]: 52
5569 19:27:20.255783
5570 19:27:20.259043 Final RX Vref Byte 0 = 53 to rank0
5571 19:27:20.261988 Final RX Vref Byte 1 = 52 to rank0
5572 19:27:20.265372 Final RX Vref Byte 0 = 53 to rank1
5573 19:27:20.268811 Final RX Vref Byte 1 = 52 to rank1==
5574 19:27:20.272275 Dram Type= 6, Freq= 0, CH_1, rank 0
5575 19:27:20.275749 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5576 19:27:20.275850 ==
5577 19:27:20.278545 DQS Delay:
5578 19:27:20.278625 DQS0 = 0, DQS1 = 0
5579 19:27:20.278688 DQM Delay:
5580 19:27:20.282144 DQM0 = 93, DQM1 = 88
5581 19:27:20.282224 DQ Delay:
5582 19:27:20.285451 DQ0 =96, DQ1 =90, DQ2 =86, DQ3 =90
5583 19:27:20.288780 DQ4 =92, DQ5 =104, DQ6 =100, DQ7 =92
5584 19:27:20.292266 DQ8 =72, DQ9 =80, DQ10 =90, DQ11 =80
5585 19:27:20.295490 DQ12 =94, DQ13 =98, DQ14 =96, DQ15 =96
5586 19:27:20.295570
5587 19:27:20.295633
5588 19:27:20.305267 [DQSOSCAuto] RK0, (LSB)MR18= 0x3939, (MSB)MR19= 0x505, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
5589 19:27:20.308373 CH1 RK0: MR19=505, MR18=3939
5590 19:27:20.312049 CH1_RK0: MR19=0x505, MR18=0x3939, DQSOSC=404, MR23=63, INC=66, DEC=44
5591 19:27:20.314998
5592 19:27:20.318390 ----->DramcWriteLeveling(PI) begin...
5593 19:27:20.318468 ==
5594 19:27:20.321828 Dram Type= 6, Freq= 0, CH_1, rank 1
5595 19:27:20.324830 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5596 19:27:20.324902 ==
5597 19:27:20.328126 Write leveling (Byte 0): 22 => 22
5598 19:27:20.331539 Write leveling (Byte 1): 24 => 24
5599 19:27:20.334735 DramcWriteLeveling(PI) end<-----
5600 19:27:20.334806
5601 19:27:20.334870 ==
5602 19:27:20.338010 Dram Type= 6, Freq= 0, CH_1, rank 1
5603 19:27:20.341459 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5604 19:27:20.341542 ==
5605 19:27:20.344988 [Gating] SW mode calibration
5606 19:27:20.351366 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5607 19:27:20.357961 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5608 19:27:20.361557 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5609 19:27:20.364778 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5610 19:27:20.371412 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5611 19:27:20.374488 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5612 19:27:20.377814 0 10 16 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
5613 19:27:20.384327 0 10 20 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
5614 19:27:20.387708 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5615 19:27:20.391023 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5616 19:27:20.397763 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5617 19:27:20.401006 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5618 19:27:20.404088 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5619 19:27:20.410663 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5620 19:27:20.414110 0 11 16 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (0 0)
5621 19:27:20.417461 0 11 20 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
5622 19:27:20.423924 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5623 19:27:20.427342 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5624 19:27:20.431020 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5625 19:27:20.437330 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5626 19:27:20.440577 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5627 19:27:20.443911 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5628 19:27:20.450697 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5629 19:27:20.454228 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5630 19:27:20.457159 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5631 19:27:20.463863 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 19:27:20.467348 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 19:27:20.470381 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 19:27:20.476856 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 19:27:20.480254 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 19:27:20.483418 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 19:27:20.490019 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 19:27:20.493452 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 19:27:20.496982 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 19:27:20.503680 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 19:27:20.507078 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 19:27:20.510183 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 19:27:20.516612 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 19:27:20.520044 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5645 19:27:20.523119 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5646 19:27:20.529822 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5647 19:27:20.529907 Total UI for P1: 0, mck2ui 16
5648 19:27:20.533588 best dqsien dly found for B0: ( 0, 14, 18)
5649 19:27:20.536789 Total UI for P1: 0, mck2ui 16
5650 19:27:20.539633 best dqsien dly found for B1: ( 0, 14, 18)
5651 19:27:20.546700 best DQS0 dly(MCK, UI, PI) = (0, 14, 18)
5652 19:27:20.549842 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5653 19:27:20.549923
5654 19:27:20.552873 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 18)
5655 19:27:20.556361 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5656 19:27:20.559571 [Gating] SW calibration Done
5657 19:27:20.559653 ==
5658 19:27:20.563296 Dram Type= 6, Freq= 0, CH_1, rank 1
5659 19:27:20.566097 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5660 19:27:20.566193 ==
5661 19:27:20.569504 RX Vref Scan: 0
5662 19:27:20.569585
5663 19:27:20.569649 RX Vref 0 -> 0, step: 1
5664 19:27:20.569708
5665 19:27:20.572919 RX Delay -80 -> 252, step: 8
5666 19:27:20.576406 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5667 19:27:20.582611 iDelay=208, Bit 1, Center 87 (-8 ~ 183) 192
5668 19:27:20.586083 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5669 19:27:20.589352 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5670 19:27:20.593083 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5671 19:27:20.596142 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5672 19:27:20.599089 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5673 19:27:20.605999 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5674 19:27:20.609105 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5675 19:27:20.612394 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5676 19:27:20.616431 iDelay=208, Bit 10, Center 87 (-16 ~ 191) 208
5677 19:27:20.618929 iDelay=208, Bit 11, Center 79 (-24 ~ 183) 208
5678 19:27:20.625530 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5679 19:27:20.629118 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5680 19:27:20.632578 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5681 19:27:20.635644 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5682 19:27:20.635726 ==
5683 19:27:20.639448 Dram Type= 6, Freq= 0, CH_1, rank 1
5684 19:27:20.642055 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5685 19:27:20.645342 ==
5686 19:27:20.645423 DQS Delay:
5687 19:27:20.645486 DQS0 = 0, DQS1 = 0
5688 19:27:20.648826 DQM Delay:
5689 19:27:20.648907 DQM0 = 96, DQM1 = 88
5690 19:27:20.652504 DQ Delay:
5691 19:27:20.656052 DQ0 =99, DQ1 =87, DQ2 =83, DQ3 =95
5692 19:27:20.658879 DQ4 =99, DQ5 =107, DQ6 =107, DQ7 =95
5693 19:27:20.662518 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =79
5694 19:27:20.665678 DQ12 =99, DQ13 =103, DQ14 =95, DQ15 =95
5695 19:27:20.666152
5696 19:27:20.666489
5697 19:27:20.666794 ==
5698 19:27:20.669049 Dram Type= 6, Freq= 0, CH_1, rank 1
5699 19:27:20.672497 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5700 19:27:20.673137 ==
5701 19:27:20.673600
5702 19:27:20.673921
5703 19:27:20.676064 TX Vref Scan disable
5704 19:27:20.676492 == TX Byte 0 ==
5705 19:27:20.682576 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5706 19:27:20.685574 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5707 19:27:20.685984 == TX Byte 1 ==
5708 19:27:20.692634 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5709 19:27:20.695631 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5710 19:27:20.696091 ==
5711 19:27:20.699106 Dram Type= 6, Freq= 0, CH_1, rank 1
5712 19:27:20.702543 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5713 19:27:20.703001 ==
5714 19:27:20.703370
5715 19:27:20.703783
5716 19:27:20.705673 TX Vref Scan disable
5717 19:27:20.708740 == TX Byte 0 ==
5718 19:27:20.712163 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5719 19:27:20.715320 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5720 19:27:20.718638 == TX Byte 1 ==
5721 19:27:20.722222 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5722 19:27:20.725843 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5723 19:27:20.728735
5724 19:27:20.729245 [DATLAT]
5725 19:27:20.729572 Freq=933, CH1 RK1
5726 19:27:20.729875
5727 19:27:20.732720 DATLAT Default: 0xb
5728 19:27:20.733232 0, 0xFFFF, sum = 0
5729 19:27:20.735413 1, 0xFFFF, sum = 0
5730 19:27:20.735933 2, 0xFFFF, sum = 0
5731 19:27:20.738990 3, 0xFFFF, sum = 0
5732 19:27:20.739510 4, 0xFFFF, sum = 0
5733 19:27:20.742128 5, 0xFFFF, sum = 0
5734 19:27:20.745745 6, 0xFFFF, sum = 0
5735 19:27:20.746399 7, 0xFFFF, sum = 0
5736 19:27:20.748783 8, 0xFFFF, sum = 0
5737 19:27:20.749201 9, 0xFFFF, sum = 0
5738 19:27:20.752232 10, 0x0, sum = 1
5739 19:27:20.752648 11, 0x0, sum = 2
5740 19:27:20.752976 12, 0x0, sum = 3
5741 19:27:20.755244 13, 0x0, sum = 4
5742 19:27:20.755661 best_step = 11
5743 19:27:20.756000
5744 19:27:20.758251 ==
5745 19:27:20.758662 Dram Type= 6, Freq= 0, CH_1, rank 1
5746 19:27:20.764999 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5747 19:27:20.765514 ==
5748 19:27:20.765841 RX Vref Scan: 0
5749 19:27:20.766299
5750 19:27:20.768593 RX Vref 0 -> 0, step: 1
5751 19:27:20.769112
5752 19:27:20.771857 RX Delay -69 -> 252, step: 4
5753 19:27:20.774701 iDelay=203, Bit 0, Center 98 (7 ~ 190) 184
5754 19:27:20.781432 iDelay=203, Bit 1, Center 90 (-1 ~ 182) 184
5755 19:27:20.785163 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5756 19:27:20.788608 iDelay=203, Bit 3, Center 92 (-1 ~ 186) 188
5757 19:27:20.791599 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5758 19:27:20.795180 iDelay=203, Bit 5, Center 108 (15 ~ 202) 188
5759 19:27:20.801703 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5760 19:27:20.805101 iDelay=203, Bit 7, Center 94 (3 ~ 186) 184
5761 19:27:20.808287 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5762 19:27:20.811241 iDelay=203, Bit 9, Center 76 (-17 ~ 170) 188
5763 19:27:20.814474 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5764 19:27:20.818467 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5765 19:27:20.824440 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5766 19:27:20.827826 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180
5767 19:27:20.831550 iDelay=203, Bit 14, Center 94 (-1 ~ 190) 192
5768 19:27:20.834909 iDelay=203, Bit 15, Center 94 (3 ~ 186) 184
5769 19:27:20.835466 ==
5770 19:27:20.837864 Dram Type= 6, Freq= 0, CH_1, rank 1
5771 19:27:20.841525 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5772 19:27:20.845027 ==
5773 19:27:20.845578 DQS Delay:
5774 19:27:20.845936 DQS0 = 0, DQS1 = 0
5775 19:27:20.847885 DQM Delay:
5776 19:27:20.848336 DQM0 = 96, DQM1 = 87
5777 19:27:20.851446 DQ Delay:
5778 19:27:20.854631 DQ0 =98, DQ1 =90, DQ2 =88, DQ3 =92
5779 19:27:20.858253 DQ4 =96, DQ5 =108, DQ6 =104, DQ7 =94
5780 19:27:20.861189 DQ8 =74, DQ9 =76, DQ10 =88, DQ11 =80
5781 19:27:20.864619 DQ12 =96, DQ13 =96, DQ14 =94, DQ15 =94
5782 19:27:20.865077
5783 19:27:20.865432
5784 19:27:20.871386 [DQSOSCAuto] RK1, (LSB)MR18= 0x2222, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
5785 19:27:20.874434 CH1 RK1: MR19=505, MR18=2222
5786 19:27:20.881141 CH1_RK1: MR19=0x505, MR18=0x2222, DQSOSC=411, MR23=63, INC=64, DEC=42
5787 19:27:20.884169 [RxdqsGatingPostProcess] freq 933
5788 19:27:20.887653 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5789 19:27:20.890798 Pre-setting of DQS Precalculation
5790 19:27:20.898126 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5791 19:27:20.904390 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5792 19:27:20.911428 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5793 19:27:20.912051
5794 19:27:20.912416
5795 19:27:20.914150 [Calibration Summary] 1866 Mbps
5796 19:27:20.914605 CH 0, Rank 0
5797 19:27:20.917765 SW Impedance : PASS
5798 19:27:20.921292 DUTY Scan : NO K
5799 19:27:20.921841 ZQ Calibration : PASS
5800 19:27:20.924284 Jitter Meter : NO K
5801 19:27:20.927471 CBT Training : PASS
5802 19:27:20.928072 Write leveling : PASS
5803 19:27:20.930693 RX DQS gating : PASS
5804 19:27:20.934093 RX DQ/DQS(RDDQC) : PASS
5805 19:27:20.934789 TX DQ/DQS : PASS
5806 19:27:20.937457 RX DATLAT : PASS
5807 19:27:20.940599 RX DQ/DQS(Engine): PASS
5808 19:27:20.941141 TX OE : NO K
5809 19:27:20.941508 All Pass.
5810 19:27:20.943660
5811 19:27:20.944110 CH 0, Rank 1
5812 19:27:20.947378 SW Impedance : PASS
5813 19:27:20.947829 DUTY Scan : NO K
5814 19:27:20.950710 ZQ Calibration : PASS
5815 19:27:20.953892 Jitter Meter : NO K
5816 19:27:20.954494 CBT Training : PASS
5817 19:27:20.957313 Write leveling : PASS
5818 19:27:20.957888 RX DQS gating : PASS
5819 19:27:20.960731 RX DQ/DQS(RDDQC) : PASS
5820 19:27:20.963480 TX DQ/DQS : PASS
5821 19:27:20.963939 RX DATLAT : PASS
5822 19:27:20.967163 RX DQ/DQS(Engine): PASS
5823 19:27:20.970657 TX OE : NO K
5824 19:27:20.971215 All Pass.
5825 19:27:20.971573
5826 19:27:20.971903 CH 1, Rank 0
5827 19:27:20.974191 SW Impedance : PASS
5828 19:27:20.977023 DUTY Scan : NO K
5829 19:27:20.977676 ZQ Calibration : PASS
5830 19:27:20.980206 Jitter Meter : NO K
5831 19:27:20.983394 CBT Training : PASS
5832 19:27:20.983850 Write leveling : PASS
5833 19:27:20.986633 RX DQS gating : PASS
5834 19:27:20.990189 RX DQ/DQS(RDDQC) : PASS
5835 19:27:20.990744 TX DQ/DQS : PASS
5836 19:27:20.993692 RX DATLAT : PASS
5837 19:27:20.996983 RX DQ/DQS(Engine): PASS
5838 19:27:20.997529 TX OE : NO K
5839 19:27:21.000024 All Pass.
5840 19:27:21.000694
5841 19:27:21.001066 CH 1, Rank 1
5842 19:27:21.003749 SW Impedance : PASS
5843 19:27:21.004325 DUTY Scan : NO K
5844 19:27:21.006439 ZQ Calibration : PASS
5845 19:27:21.010474 Jitter Meter : NO K
5846 19:27:21.011038 CBT Training : PASS
5847 19:27:21.013641 Write leveling : PASS
5848 19:27:21.017278 RX DQS gating : PASS
5849 19:27:21.017868 RX DQ/DQS(RDDQC) : PASS
5850 19:27:21.019637 TX DQ/DQS : PASS
5851 19:27:21.020102 RX DATLAT : PASS
5852 19:27:21.022900 RX DQ/DQS(Engine): PASS
5853 19:27:21.026719 TX OE : NO K
5854 19:27:21.027287 All Pass.
5855 19:27:21.027648
5856 19:27:21.029931 DramC Write-DBI off
5857 19:27:21.030536 PER_BANK_REFRESH: Hybrid Mode
5858 19:27:21.033471 TX_TRACKING: ON
5859 19:27:21.043245 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5860 19:27:21.046414 [FAST_K] Save calibration result to emmc
5861 19:27:21.050071 dramc_set_vcore_voltage set vcore to 650000
5862 19:27:21.052957 Read voltage for 400, 6
5863 19:27:21.053525 Vio18 = 0
5864 19:27:21.053901 Vcore = 650000
5865 19:27:21.054288 Vdram = 0
5866 19:27:21.056202 Vddq = 0
5867 19:27:21.056657 Vmddr = 0
5868 19:27:21.062559 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5869 19:27:21.065794 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5870 19:27:21.069396 MEM_TYPE=3, freq_sel=20
5871 19:27:21.072907 sv_algorithm_assistance_LP4_800
5872 19:27:21.076111 ============ PULL DRAM RESETB DOWN ============
5873 19:27:21.079411 ========== PULL DRAM RESETB DOWN end =========
5874 19:27:21.086245 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5875 19:27:21.089791 ===================================
5876 19:27:21.090424 LPDDR4 DRAM CONFIGURATION
5877 19:27:21.092574 ===================================
5878 19:27:21.096268 EX_ROW_EN[0] = 0x0
5879 19:27:21.099102 EX_ROW_EN[1] = 0x0
5880 19:27:21.099567 LP4Y_EN = 0x0
5881 19:27:21.102833 WORK_FSP = 0x0
5882 19:27:21.103396 WL = 0x2
5883 19:27:21.106105 RL = 0x2
5884 19:27:21.106568 BL = 0x2
5885 19:27:21.109100 RPST = 0x0
5886 19:27:21.109665 RD_PRE = 0x0
5887 19:27:21.112192 WR_PRE = 0x1
5888 19:27:21.112655 WR_PST = 0x0
5889 19:27:21.115579 DBI_WR = 0x0
5890 19:27:21.116039 DBI_RD = 0x0
5891 19:27:21.118951 OTF = 0x1
5892 19:27:21.122652 ===================================
5893 19:27:21.125918 ===================================
5894 19:27:21.126526 ANA top config
5895 19:27:21.129221 ===================================
5896 19:27:21.131972 DLL_ASYNC_EN = 0
5897 19:27:21.135632 ALL_SLAVE_EN = 1
5898 19:27:21.138968 NEW_RANK_MODE = 1
5899 19:27:21.139434 DLL_IDLE_MODE = 1
5900 19:27:21.142197 LP45_APHY_COMB_EN = 1
5901 19:27:21.145553 TX_ODT_DIS = 1
5902 19:27:21.148485 NEW_8X_MODE = 1
5903 19:27:21.152470 ===================================
5904 19:27:21.155514 ===================================
5905 19:27:21.158974 data_rate = 800
5906 19:27:21.159526 CKR = 1
5907 19:27:21.162117 DQ_P2S_RATIO = 4
5908 19:27:21.164988 ===================================
5909 19:27:21.168729 CA_P2S_RATIO = 4
5910 19:27:21.172251 DQ_CA_OPEN = 0
5911 19:27:21.175066 DQ_SEMI_OPEN = 1
5912 19:27:21.178333 CA_SEMI_OPEN = 1
5913 19:27:21.178849 CA_FULL_RATE = 0
5914 19:27:21.181532 DQ_CKDIV4_EN = 0
5915 19:27:21.185138 CA_CKDIV4_EN = 1
5916 19:27:21.188695 CA_PREDIV_EN = 0
5917 19:27:21.192148 PH8_DLY = 0
5918 19:27:21.195149 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5919 19:27:21.195705 DQ_AAMCK_DIV = 0
5920 19:27:21.198529 CA_AAMCK_DIV = 0
5921 19:27:21.201643 CA_ADMCK_DIV = 4
5922 19:27:21.205122 DQ_TRACK_CA_EN = 0
5923 19:27:21.208238 CA_PICK = 800
5924 19:27:21.211267 CA_MCKIO = 400
5925 19:27:21.214755 MCKIO_SEMI = 400
5926 19:27:21.218220 PLL_FREQ = 3016
5927 19:27:21.218683 DQ_UI_PI_RATIO = 32
5928 19:27:21.221491 CA_UI_PI_RATIO = 32
5929 19:27:21.224484 ===================================
5930 19:27:21.227681 ===================================
5931 19:27:21.230993 memory_type:LPDDR4
5932 19:27:21.234594 GP_NUM : 10
5933 19:27:21.235148 SRAM_EN : 1
5934 19:27:21.237780 MD32_EN : 0
5935 19:27:21.241083 ===================================
5936 19:27:21.244442 [ANA_INIT] >>>>>>>>>>>>>>
5937 19:27:21.244994 <<<<<< [CONFIGURE PHASE]: ANA_TX
5938 19:27:21.251448 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5939 19:27:21.254285 ===================================
5940 19:27:21.254843 data_rate = 800,PCW = 0X7400
5941 19:27:21.257694 ===================================
5942 19:27:21.261184 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5943 19:27:21.267623 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5944 19:27:21.277504 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5945 19:27:21.283935 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5946 19:27:21.287325 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5947 19:27:21.290470 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5948 19:27:21.294083 [ANA_INIT] flow start
5949 19:27:21.294640 [ANA_INIT] PLL >>>>>>>>
5950 19:27:21.297411 [ANA_INIT] PLL <<<<<<<<
5951 19:27:21.300966 [ANA_INIT] MIDPI >>>>>>>>
5952 19:27:21.301519 [ANA_INIT] MIDPI <<<<<<<<
5953 19:27:21.303807 [ANA_INIT] DLL >>>>>>>>
5954 19:27:21.307047 [ANA_INIT] flow end
5955 19:27:21.310435 ============ LP4 DIFF to SE enter ============
5956 19:27:21.313811 ============ LP4 DIFF to SE exit ============
5957 19:27:21.317209 [ANA_INIT] <<<<<<<<<<<<<
5958 19:27:21.320569 [Flow] Enable top DCM control >>>>>
5959 19:27:21.323717 [Flow] Enable top DCM control <<<<<
5960 19:27:21.327142 Enable DLL master slave shuffle
5961 19:27:21.330469 ==============================================================
5962 19:27:21.333547 Gating Mode config
5963 19:27:21.340471 ==============================================================
5964 19:27:21.341031 Config description:
5965 19:27:21.350489 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5966 19:27:21.356435 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5967 19:27:21.363294 SELPH_MODE 0: By rank 1: By Phase
5968 19:27:21.366928 ==============================================================
5969 19:27:21.369827 GAT_TRACK_EN = 0
5970 19:27:21.373171 RX_GATING_MODE = 2
5971 19:27:21.376954 RX_GATING_TRACK_MODE = 2
5972 19:27:21.379818 SELPH_MODE = 1
5973 19:27:21.382839 PICG_EARLY_EN = 1
5974 19:27:21.386497 VALID_LAT_VALUE = 1
5975 19:27:21.389656 ==============================================================
5976 19:27:21.393157 Enter into Gating configuration >>>>
5977 19:27:21.396668 Exit from Gating configuration <<<<
5978 19:27:21.399849 Enter into DVFS_PRE_config >>>>>
5979 19:27:21.413147 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5980 19:27:21.416331 Exit from DVFS_PRE_config <<<<<
5981 19:27:21.419593 Enter into PICG configuration >>>>
5982 19:27:21.420052 Exit from PICG configuration <<<<
5983 19:27:21.422710 [RX_INPUT] configuration >>>>>
5984 19:27:21.425836 [RX_INPUT] configuration <<<<<
5985 19:27:21.432412 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5986 19:27:21.435749 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5987 19:27:21.442327 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5988 19:27:21.449037 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5989 19:27:21.455470 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5990 19:27:21.462263 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5991 19:27:21.465639 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5992 19:27:21.469383 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5993 19:27:21.475418 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5994 19:27:21.478948 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5995 19:27:21.482335 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5996 19:27:21.485398 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5997 19:27:21.488707 ===================================
5998 19:27:21.491720 LPDDR4 DRAM CONFIGURATION
5999 19:27:21.494859 ===================================
6000 19:27:21.498453 EX_ROW_EN[0] = 0x0
6001 19:27:21.498862 EX_ROW_EN[1] = 0x0
6002 19:27:21.501960 LP4Y_EN = 0x0
6003 19:27:21.502408 WORK_FSP = 0x0
6004 19:27:21.505141 WL = 0x2
6005 19:27:21.505699 RL = 0x2
6006 19:27:21.508671 BL = 0x2
6007 19:27:21.509094 RPST = 0x0
6008 19:27:21.511883 RD_PRE = 0x0
6009 19:27:21.515150 WR_PRE = 0x1
6010 19:27:21.515560 WR_PST = 0x0
6011 19:27:21.518629 DBI_WR = 0x0
6012 19:27:21.519041 DBI_RD = 0x0
6013 19:27:21.521474 OTF = 0x1
6014 19:27:21.525202 ===================================
6015 19:27:21.528503 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6016 19:27:21.531601 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6017 19:27:21.534737 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6018 19:27:21.538131 ===================================
6019 19:27:21.541644 LPDDR4 DRAM CONFIGURATION
6020 19:27:21.545030 ===================================
6021 19:27:21.548213 EX_ROW_EN[0] = 0x10
6022 19:27:21.548708 EX_ROW_EN[1] = 0x0
6023 19:27:21.551375 LP4Y_EN = 0x0
6024 19:27:21.551940 WORK_FSP = 0x0
6025 19:27:21.555084 WL = 0x2
6026 19:27:21.555541 RL = 0x2
6027 19:27:21.557952 BL = 0x2
6028 19:27:21.558640 RPST = 0x0
6029 19:27:21.561311 RD_PRE = 0x0
6030 19:27:21.564556 WR_PRE = 0x1
6031 19:27:21.565179 WR_PST = 0x0
6032 19:27:21.568013 DBI_WR = 0x0
6033 19:27:21.568472 DBI_RD = 0x0
6034 19:27:21.571475 OTF = 0x1
6035 19:27:21.574665 ===================================
6036 19:27:21.577635 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6037 19:27:21.583281 nWR fixed to 30
6038 19:27:21.586833 [ModeRegInit_LP4] CH0 RK0
6039 19:27:21.587435 [ModeRegInit_LP4] CH0 RK1
6040 19:27:21.589637 [ModeRegInit_LP4] CH1 RK0
6041 19:27:21.593633 [ModeRegInit_LP4] CH1 RK1
6042 19:27:21.594241 match AC timing 18
6043 19:27:21.599869 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
6044 19:27:21.603351 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6045 19:27:21.606596 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6046 19:27:21.613134 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6047 19:27:21.616222 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6048 19:27:21.616723 ==
6049 19:27:21.619697 Dram Type= 6, Freq= 0, CH_0, rank 0
6050 19:27:21.623072 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6051 19:27:21.623647 ==
6052 19:27:21.629522 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6053 19:27:21.636409 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6054 19:27:21.639684 [CA 0] Center 36 (8~64) winsize 57
6055 19:27:21.642847 [CA 1] Center 36 (8~64) winsize 57
6056 19:27:21.645726 [CA 2] Center 36 (8~64) winsize 57
6057 19:27:21.649791 [CA 3] Center 36 (8~64) winsize 57
6058 19:27:21.652410 [CA 4] Center 36 (8~64) winsize 57
6059 19:27:21.652877 [CA 5] Center 36 (8~64) winsize 57
6060 19:27:21.655674
6061 19:27:21.659079 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6062 19:27:21.659579
6063 19:27:21.662651 [CATrainingPosCal] consider 1 rank data
6064 19:27:21.665732 u2DelayCellTimex100 = 270/100 ps
6065 19:27:21.669154 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6066 19:27:21.672586 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6067 19:27:21.675912 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6068 19:27:21.679056 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6069 19:27:21.682386 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6070 19:27:21.685696 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6071 19:27:21.686285
6072 19:27:21.689297 CA PerBit enable=1, Macro0, CA PI delay=36
6073 19:27:21.690013
6074 19:27:21.692328 [CBTSetCACLKResult] CA Dly = 36
6075 19:27:21.695540 CS Dly: 1 (0~32)
6076 19:27:21.695953 ==
6077 19:27:21.699465 Dram Type= 6, Freq= 0, CH_0, rank 1
6078 19:27:21.701992 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6079 19:27:21.702467 ==
6080 19:27:21.709398 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6081 19:27:21.715402 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6082 19:27:21.718933 [CA 0] Center 36 (8~64) winsize 57
6083 19:27:21.719614 [CA 1] Center 36 (8~64) winsize 57
6084 19:27:21.722226 [CA 2] Center 36 (8~64) winsize 57
6085 19:27:21.725861 [CA 3] Center 36 (8~64) winsize 57
6086 19:27:21.729094 [CA 4] Center 36 (8~64) winsize 57
6087 19:27:21.731829 [CA 5] Center 36 (8~64) winsize 57
6088 19:27:21.732241
6089 19:27:21.735442 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6090 19:27:21.735976
6091 19:27:21.742579 [CATrainingPosCal] consider 2 rank data
6092 19:27:21.743227 u2DelayCellTimex100 = 270/100 ps
6093 19:27:21.748625 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6094 19:27:21.751976 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6095 19:27:21.755247 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6096 19:27:21.758580 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6097 19:27:21.761948 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6098 19:27:21.764892 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6099 19:27:21.765305
6100 19:27:21.768419 CA PerBit enable=1, Macro0, CA PI delay=36
6101 19:27:21.768973
6102 19:27:21.771628 [CBTSetCACLKResult] CA Dly = 36
6103 19:27:21.774745 CS Dly: 1 (0~32)
6104 19:27:21.775155
6105 19:27:21.778555 ----->DramcWriteLeveling(PI) begin...
6106 19:27:21.779123 ==
6107 19:27:21.781246 Dram Type= 6, Freq= 0, CH_0, rank 0
6108 19:27:21.784581 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6109 19:27:21.785000 ==
6110 19:27:21.788124 Write leveling (Byte 0): 32 => 0
6111 19:27:21.791684 Write leveling (Byte 1): 32 => 0
6112 19:27:21.795071 DramcWriteLeveling(PI) end<-----
6113 19:27:21.795761
6114 19:27:21.796290 ==
6115 19:27:21.798451 Dram Type= 6, Freq= 0, CH_0, rank 0
6116 19:27:21.801492 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6117 19:27:21.801951 ==
6118 19:27:21.804707 [Gating] SW mode calibration
6119 19:27:21.811316 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6120 19:27:21.817977 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6121 19:27:21.821486 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6122 19:27:21.824981 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6123 19:27:21.831383 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6124 19:27:21.834318 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6125 19:27:21.837687 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6126 19:27:21.844651 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6127 19:27:21.847376 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6128 19:27:21.851037 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6129 19:27:21.857627 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6130 19:27:21.858078 Total UI for P1: 0, mck2ui 16
6131 19:27:21.863996 best dqsien dly found for B0: ( 0, 10, 16)
6132 19:27:21.864470 Total UI for P1: 0, mck2ui 16
6133 19:27:21.870706 best dqsien dly found for B1: ( 0, 10, 16)
6134 19:27:21.874462 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6135 19:27:21.877508 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6136 19:27:21.878189
6137 19:27:21.880285 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6138 19:27:21.883841 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6139 19:27:21.887230 [Gating] SW calibration Done
6140 19:27:21.887815 ==
6141 19:27:21.890485 Dram Type= 6, Freq= 0, CH_0, rank 0
6142 19:27:21.893829 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6143 19:27:21.894423 ==
6144 19:27:21.897199 RX Vref Scan: 0
6145 19:27:21.897780
6146 19:27:21.900644 RX Vref 0 -> 0, step: 1
6147 19:27:21.901088
6148 19:27:21.901479 RX Delay -410 -> 252, step: 16
6149 19:27:21.907247 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6150 19:27:21.910435 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6151 19:27:21.913789 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6152 19:27:21.917316 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6153 19:27:21.923696 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6154 19:27:21.927174 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496
6155 19:27:21.930144 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6156 19:27:21.933603 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6157 19:27:21.940065 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6158 19:27:21.943747 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6159 19:27:21.947179 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6160 19:27:21.953161 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6161 19:27:21.956711 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6162 19:27:21.959935 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6163 19:27:21.963129 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6164 19:27:21.969897 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6165 19:27:21.970454 ==
6166 19:27:21.973023 Dram Type= 6, Freq= 0, CH_0, rank 0
6167 19:27:21.976643 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6168 19:27:21.977256 ==
6169 19:27:21.977596 DQS Delay:
6170 19:27:21.980135 DQS0 = 51, DQS1 = 59
6171 19:27:21.980611 DQM Delay:
6172 19:27:21.983132 DQM0 = 12, DQM1 = 16
6173 19:27:21.983542 DQ Delay:
6174 19:27:21.986828 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6175 19:27:21.989804 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6176 19:27:21.993156 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6177 19:27:21.996077 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6178 19:27:21.996506
6179 19:27:21.996832
6180 19:27:21.997195 ==
6181 19:27:21.999919 Dram Type= 6, Freq= 0, CH_0, rank 0
6182 19:27:22.002684 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6183 19:27:22.003100 ==
6184 19:27:22.003478
6185 19:27:22.006251
6186 19:27:22.006662 TX Vref Scan disable
6187 19:27:22.009583 == TX Byte 0 ==
6188 19:27:22.012668 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6189 19:27:22.016335 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6190 19:27:22.019444 == TX Byte 1 ==
6191 19:27:22.022542 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6192 19:27:22.025833 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6193 19:27:22.026299 ==
6194 19:27:22.029293 Dram Type= 6, Freq= 0, CH_0, rank 0
6195 19:27:22.035970 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6196 19:27:22.036491 ==
6197 19:27:22.036824
6198 19:27:22.037232
6199 19:27:22.037539 TX Vref Scan disable
6200 19:27:22.039032 == TX Byte 0 ==
6201 19:27:22.042791 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6202 19:27:22.045785 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6203 19:27:22.049478 == TX Byte 1 ==
6204 19:27:22.052282 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6205 19:27:22.055544 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6206 19:27:22.055957
6207 19:27:22.059179 [DATLAT]
6208 19:27:22.059592 Freq=400, CH0 RK0
6209 19:27:22.059919
6210 19:27:22.062334 DATLAT Default: 0xf
6211 19:27:22.062743 0, 0xFFFF, sum = 0
6212 19:27:22.065993 1, 0xFFFF, sum = 0
6213 19:27:22.066484 2, 0xFFFF, sum = 0
6214 19:27:22.069151 3, 0xFFFF, sum = 0
6215 19:27:22.069689 4, 0xFFFF, sum = 0
6216 19:27:22.072109 5, 0xFFFF, sum = 0
6217 19:27:22.072532 6, 0xFFFF, sum = 0
6218 19:27:22.076229 7, 0xFFFF, sum = 0
6219 19:27:22.076727 8, 0xFFFF, sum = 0
6220 19:27:22.078924 9, 0xFFFF, sum = 0
6221 19:27:22.082255 10, 0xFFFF, sum = 0
6222 19:27:22.082883 11, 0xFFFF, sum = 0
6223 19:27:22.085703 12, 0x0, sum = 1
6224 19:27:22.086168 13, 0x0, sum = 2
6225 19:27:22.088952 14, 0x0, sum = 3
6226 19:27:22.089471 15, 0x0, sum = 4
6227 19:27:22.089811 best_step = 13
6228 19:27:22.090162
6229 19:27:22.092477 ==
6230 19:27:22.095568 Dram Type= 6, Freq= 0, CH_0, rank 0
6231 19:27:22.098728 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6232 19:27:22.099155 ==
6233 19:27:22.099481 RX Vref Scan: 1
6234 19:27:22.099786
6235 19:27:22.101810 RX Vref 0 -> 0, step: 1
6236 19:27:22.102271
6237 19:27:22.105689 RX Delay -359 -> 252, step: 8
6238 19:27:22.106147
6239 19:27:22.108925 Set Vref, RX VrefLevel [Byte0]: 51
6240 19:27:22.111967 [Byte1]: 49
6241 19:27:22.115874
6242 19:27:22.116290 Final RX Vref Byte 0 = 51 to rank0
6243 19:27:22.119377 Final RX Vref Byte 1 = 49 to rank0
6244 19:27:22.122372 Final RX Vref Byte 0 = 51 to rank1
6245 19:27:22.125706 Final RX Vref Byte 1 = 49 to rank1==
6246 19:27:22.128687 Dram Type= 6, Freq= 0, CH_0, rank 0
6247 19:27:22.135269 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6248 19:27:22.135688 ==
6249 19:27:22.136015 DQS Delay:
6250 19:27:22.138616 DQS0 = 52, DQS1 = 68
6251 19:27:22.139027 DQM Delay:
6252 19:27:22.139352 DQM0 = 9, DQM1 = 17
6253 19:27:22.141972 DQ Delay:
6254 19:27:22.145187 DQ0 =4, DQ1 =8, DQ2 =8, DQ3 =4
6255 19:27:22.145618 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6256 19:27:22.148546 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6257 19:27:22.151642 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =28
6258 19:27:22.152070
6259 19:27:22.155040
6260 19:27:22.161835 [DQSOSCAuto] RK0, (LSB)MR18= 0xa2a2, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
6261 19:27:22.165358 CH0 RK0: MR19=C0C, MR18=A2A2
6262 19:27:22.171897 CH0_RK0: MR19=0xC0C, MR18=0xA2A2, DQSOSC=389, MR23=63, INC=390, DEC=260
6263 19:27:22.172316 ==
6264 19:27:22.175191 Dram Type= 6, Freq= 0, CH_0, rank 1
6265 19:27:22.178765 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6266 19:27:22.179260 ==
6267 19:27:22.181666 [Gating] SW mode calibration
6268 19:27:22.188557 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6269 19:27:22.194926 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6270 19:27:22.198220 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6271 19:27:22.201343 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6272 19:27:22.208248 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6273 19:27:22.211356 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6274 19:27:22.214550 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6275 19:27:22.221381 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6276 19:27:22.224655 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6277 19:27:22.227756 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6278 19:27:22.234396 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6279 19:27:22.234812 Total UI for P1: 0, mck2ui 16
6280 19:27:22.241118 best dqsien dly found for B0: ( 0, 10, 16)
6281 19:27:22.241531 Total UI for P1: 0, mck2ui 16
6282 19:27:22.244206 best dqsien dly found for B1: ( 0, 10, 16)
6283 19:27:22.250874 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6284 19:27:22.254312 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6285 19:27:22.254809
6286 19:27:22.257275 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6287 19:27:22.260634 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6288 19:27:22.263860 [Gating] SW calibration Done
6289 19:27:22.264276 ==
6290 19:27:22.267445 Dram Type= 6, Freq= 0, CH_0, rank 1
6291 19:27:22.270704 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6292 19:27:22.271122 ==
6293 19:27:22.273800 RX Vref Scan: 0
6294 19:27:22.274253
6295 19:27:22.274584 RX Vref 0 -> 0, step: 1
6296 19:27:22.274887
6297 19:27:22.277333 RX Delay -410 -> 252, step: 16
6298 19:27:22.283717 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6299 19:27:22.287574 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6300 19:27:22.290407 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6301 19:27:22.293991 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6302 19:27:22.300707 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6303 19:27:22.304199 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6304 19:27:22.307141 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6305 19:27:22.310319 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6306 19:27:22.316947 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6307 19:27:22.320294 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6308 19:27:22.323458 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6309 19:27:22.326886 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6310 19:27:22.333415 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6311 19:27:22.336738 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6312 19:27:22.340165 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6313 19:27:22.346562 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6314 19:27:22.347124 ==
6315 19:27:22.350151 Dram Type= 6, Freq= 0, CH_0, rank 1
6316 19:27:22.353227 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6317 19:27:22.353663 ==
6318 19:27:22.353991 DQS Delay:
6319 19:27:22.356896 DQS0 = 43, DQS1 = 59
6320 19:27:22.357498 DQM Delay:
6321 19:27:22.359861 DQM0 = 6, DQM1 = 15
6322 19:27:22.360279 DQ Delay:
6323 19:27:22.363293 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6324 19:27:22.366458 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6325 19:27:22.370080 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6326 19:27:22.373350 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6327 19:27:22.373799
6328 19:27:22.374169
6329 19:27:22.374481 ==
6330 19:27:22.376475 Dram Type= 6, Freq= 0, CH_0, rank 1
6331 19:27:22.380292 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6332 19:27:22.380781 ==
6333 19:27:22.381111
6334 19:27:22.381411
6335 19:27:22.383304 TX Vref Scan disable
6336 19:27:22.383794 == TX Byte 0 ==
6337 19:27:22.389483 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6338 19:27:22.393061 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6339 19:27:22.393532 == TX Byte 1 ==
6340 19:27:22.399652 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6341 19:27:22.402767 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6342 19:27:22.403272 ==
6343 19:27:22.406194 Dram Type= 6, Freq= 0, CH_0, rank 1
6344 19:27:22.409441 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6345 19:27:22.410009 ==
6346 19:27:22.410399
6347 19:27:22.410708
6348 19:27:22.413022 TX Vref Scan disable
6349 19:27:22.416343 == TX Byte 0 ==
6350 19:27:22.419590 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6351 19:27:22.422710 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6352 19:27:22.425765 == TX Byte 1 ==
6353 19:27:22.429012 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6354 19:27:22.432585 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6355 19:27:22.433038
6356 19:27:22.433365 [DATLAT]
6357 19:27:22.436018 Freq=400, CH0 RK1
6358 19:27:22.436537
6359 19:27:22.436867 DATLAT Default: 0xd
6360 19:27:22.438931 0, 0xFFFF, sum = 0
6361 19:27:22.439374 1, 0xFFFF, sum = 0
6362 19:27:22.442379 2, 0xFFFF, sum = 0
6363 19:27:22.445774 3, 0xFFFF, sum = 0
6364 19:27:22.446312 4, 0xFFFF, sum = 0
6365 19:27:22.449056 5, 0xFFFF, sum = 0
6366 19:27:22.449473 6, 0xFFFF, sum = 0
6367 19:27:22.452349 7, 0xFFFF, sum = 0
6368 19:27:22.452847 8, 0xFFFF, sum = 0
6369 19:27:22.455673 9, 0xFFFF, sum = 0
6370 19:27:22.456156 10, 0xFFFF, sum = 0
6371 19:27:22.458770 11, 0xFFFF, sum = 0
6372 19:27:22.459239 12, 0x0, sum = 1
6373 19:27:22.462408 13, 0x0, sum = 2
6374 19:27:22.462703 14, 0x0, sum = 3
6375 19:27:22.465736 15, 0x0, sum = 4
6376 19:27:22.466055 best_step = 13
6377 19:27:22.466292
6378 19:27:22.466504 ==
6379 19:27:22.468716 Dram Type= 6, Freq= 0, CH_0, rank 1
6380 19:27:22.472005 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6381 19:27:22.472306 ==
6382 19:27:22.475707 RX Vref Scan: 0
6383 19:27:22.476002
6384 19:27:22.478849 RX Vref 0 -> 0, step: 1
6385 19:27:22.479143
6386 19:27:22.481788 RX Delay -359 -> 252, step: 8
6387 19:27:22.488919 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6388 19:27:22.492160 iDelay=217, Bit 1, Center -40 (-295 ~ 216) 512
6389 19:27:22.495193 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6390 19:27:22.498765 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6391 19:27:22.501952 iDelay=217, Bit 4, Center -36 (-287 ~ 216) 504
6392 19:27:22.508569 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6393 19:27:22.512047 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6394 19:27:22.514962 iDelay=217, Bit 7, Center -32 (-279 ~ 216) 496
6395 19:27:22.521902 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6396 19:27:22.525027 iDelay=217, Bit 9, Center -64 (-311 ~ 184) 496
6397 19:27:22.528011 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6398 19:27:22.531546 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6399 19:27:22.538408 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6400 19:27:22.541527 iDelay=217, Bit 13, Center -44 (-295 ~ 208) 504
6401 19:27:22.544788 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6402 19:27:22.548202 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6403 19:27:22.551483 ==
6404 19:27:22.551935 Dram Type= 6, Freq= 0, CH_0, rank 1
6405 19:27:22.558279 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6406 19:27:22.558695 ==
6407 19:27:22.559015 DQS Delay:
6408 19:27:22.561705 DQS0 = 52, DQS1 = 64
6409 19:27:22.562215 DQM Delay:
6410 19:27:22.564833 DQM0 = 10, DQM1 = 14
6411 19:27:22.565239 DQ Delay:
6412 19:27:22.567721 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =4
6413 19:27:22.571378 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =20
6414 19:27:22.574371 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6415 19:27:22.578435 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =24
6416 19:27:22.578874
6417 19:27:22.579197
6418 19:27:22.584284 [DQSOSCAuto] RK1, (LSB)MR18= 0xbcbc, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 386 ps
6419 19:27:22.587953 CH0 RK1: MR19=C0C, MR18=BCBC
6420 19:27:22.594293 CH0_RK1: MR19=0xC0C, MR18=0xBCBC, DQSOSC=386, MR23=63, INC=396, DEC=264
6421 19:27:22.597592 [RxdqsGatingPostProcess] freq 400
6422 19:27:22.604552 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6423 19:27:22.604972 Pre-setting of DQS Precalculation
6424 19:27:22.610566 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6425 19:27:22.610985 ==
6426 19:27:22.614157 Dram Type= 6, Freq= 0, CH_1, rank 0
6427 19:27:22.617352 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6428 19:27:22.617772 ==
6429 19:27:22.623707 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6430 19:27:22.630356 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6431 19:27:22.634287 [CA 0] Center 36 (8~64) winsize 57
6432 19:27:22.637246 [CA 1] Center 36 (8~64) winsize 57
6433 19:27:22.640745 [CA 2] Center 36 (8~64) winsize 57
6434 19:27:22.644086 [CA 3] Center 36 (8~64) winsize 57
6435 19:27:22.644502 [CA 4] Center 36 (8~64) winsize 57
6436 19:27:22.646948 [CA 5] Center 36 (8~64) winsize 57
6437 19:27:22.647362
6438 19:27:22.653559 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6439 19:27:22.653975
6440 19:27:22.657201 [CATrainingPosCal] consider 1 rank data
6441 19:27:22.660138 u2DelayCellTimex100 = 270/100 ps
6442 19:27:22.663628 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6443 19:27:22.667079 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6444 19:27:22.670118 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6445 19:27:22.673709 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6446 19:27:22.676916 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6447 19:27:22.680214 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6448 19:27:22.680630
6449 19:27:22.683487 CA PerBit enable=1, Macro0, CA PI delay=36
6450 19:27:22.683906
6451 19:27:22.687547 [CBTSetCACLKResult] CA Dly = 36
6452 19:27:22.690301 CS Dly: 1 (0~32)
6453 19:27:22.690715 ==
6454 19:27:22.693596 Dram Type= 6, Freq= 0, CH_1, rank 1
6455 19:27:22.696501 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6456 19:27:22.696929 ==
6457 19:27:22.703262 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6458 19:27:22.710107 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6459 19:27:22.713285 [CA 0] Center 36 (8~64) winsize 57
6460 19:27:22.713766 [CA 1] Center 36 (8~64) winsize 57
6461 19:27:22.716520 [CA 2] Center 36 (8~64) winsize 57
6462 19:27:22.719615 [CA 3] Center 36 (8~64) winsize 57
6463 19:27:22.722966 [CA 4] Center 36 (8~64) winsize 57
6464 19:27:22.726228 [CA 5] Center 36 (8~64) winsize 57
6465 19:27:22.726794
6466 19:27:22.729778 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6467 19:27:22.730369
6468 19:27:22.732861 [CATrainingPosCal] consider 2 rank data
6469 19:27:22.736434 u2DelayCellTimex100 = 270/100 ps
6470 19:27:22.739527 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6471 19:27:22.746492 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6472 19:27:22.749549 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6473 19:27:22.752788 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6474 19:27:22.756150 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6475 19:27:22.759574 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6476 19:27:22.759985
6477 19:27:22.763222 CA PerBit enable=1, Macro0, CA PI delay=36
6478 19:27:22.763751
6479 19:27:22.766140 [CBTSetCACLKResult] CA Dly = 36
6480 19:27:22.769461 CS Dly: 1 (0~32)
6481 19:27:22.769868
6482 19:27:22.772658 ----->DramcWriteLeveling(PI) begin...
6483 19:27:22.773118 ==
6484 19:27:22.776015 Dram Type= 6, Freq= 0, CH_1, rank 0
6485 19:27:22.779668 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6486 19:27:22.780154 ==
6487 19:27:22.782532 Write leveling (Byte 0): 32 => 0
6488 19:27:22.785989 Write leveling (Byte 1): 32 => 0
6489 19:27:22.789542 DramcWriteLeveling(PI) end<-----
6490 19:27:22.789972
6491 19:27:22.790435 ==
6492 19:27:22.792921 Dram Type= 6, Freq= 0, CH_1, rank 0
6493 19:27:22.795679 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6494 19:27:22.796104 ==
6495 19:27:22.799092 [Gating] SW mode calibration
6496 19:27:22.805500 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6497 19:27:22.812176 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6498 19:27:22.816041 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6499 19:27:22.819536 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6500 19:27:22.825804 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6501 19:27:22.829194 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6502 19:27:22.832763 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6503 19:27:22.838950 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6504 19:27:22.842487 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6505 19:27:22.845876 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6506 19:27:22.852146 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6507 19:27:22.852603 Total UI for P1: 0, mck2ui 16
6508 19:27:22.855325 best dqsien dly found for B0: ( 0, 10, 16)
6509 19:27:22.859162 Total UI for P1: 0, mck2ui 16
6510 19:27:22.862339 best dqsien dly found for B1: ( 0, 10, 16)
6511 19:27:22.868935 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6512 19:27:22.872304 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6513 19:27:22.872714
6514 19:27:22.875283 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6515 19:27:22.878799 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6516 19:27:22.882004 [Gating] SW calibration Done
6517 19:27:22.882439 ==
6518 19:27:22.885556 Dram Type= 6, Freq= 0, CH_1, rank 0
6519 19:27:22.888678 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6520 19:27:22.889096 ==
6521 19:27:22.892278 RX Vref Scan: 0
6522 19:27:22.892688
6523 19:27:22.893004 RX Vref 0 -> 0, step: 1
6524 19:27:22.893307
6525 19:27:22.895788 RX Delay -410 -> 252, step: 16
6526 19:27:22.902514 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6527 19:27:22.905163 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6528 19:27:22.908863 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6529 19:27:22.911675 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6530 19:27:22.918119 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6531 19:27:22.921834 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6532 19:27:22.925408 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6533 19:27:22.928731 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6534 19:27:22.934836 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6535 19:27:22.938138 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6536 19:27:22.941523 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6537 19:27:22.944648 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6538 19:27:22.951245 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6539 19:27:22.954771 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6540 19:27:22.957970 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6541 19:27:22.964612 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6542 19:27:22.965024 ==
6543 19:27:22.968191 Dram Type= 6, Freq= 0, CH_1, rank 0
6544 19:27:22.971404 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6545 19:27:22.971808 ==
6546 19:27:22.972124 DQS Delay:
6547 19:27:22.975168 DQS0 = 43, DQS1 = 59
6548 19:27:22.975678 DQM Delay:
6549 19:27:22.978204 DQM0 = 6, DQM1 = 16
6550 19:27:22.978712 DQ Delay:
6551 19:27:22.981327 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6552 19:27:22.984519 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6553 19:27:22.987692 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6554 19:27:22.991014 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =32
6555 19:27:22.991425
6556 19:27:22.991744
6557 19:27:22.992042 ==
6558 19:27:22.994505 Dram Type= 6, Freq= 0, CH_1, rank 0
6559 19:27:22.997747 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6560 19:27:22.998247 ==
6561 19:27:22.998716
6562 19:27:22.999076
6563 19:27:23.000937 TX Vref Scan disable
6564 19:27:23.001477 == TX Byte 0 ==
6565 19:27:23.007274 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6566 19:27:23.010763 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6567 19:27:23.011176 == TX Byte 1 ==
6568 19:27:23.017221 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6569 19:27:23.020847 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6570 19:27:23.021391 ==
6571 19:27:23.023890 Dram Type= 6, Freq= 0, CH_1, rank 0
6572 19:27:23.027648 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6573 19:27:23.028063 ==
6574 19:27:23.028432
6575 19:27:23.030762
6576 19:27:23.031169 TX Vref Scan disable
6577 19:27:23.034180 == TX Byte 0 ==
6578 19:27:23.037316 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6579 19:27:23.040640 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6580 19:27:23.043917 == TX Byte 1 ==
6581 19:27:23.047067 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6582 19:27:23.050411 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6583 19:27:23.050838
6584 19:27:23.053764 [DATLAT]
6585 19:27:23.054206 Freq=400, CH1 RK0
6586 19:27:23.054534
6587 19:27:23.056945 DATLAT Default: 0xf
6588 19:27:23.057351 0, 0xFFFF, sum = 0
6589 19:27:23.060390 1, 0xFFFF, sum = 0
6590 19:27:23.060803 2, 0xFFFF, sum = 0
6591 19:27:23.063946 3, 0xFFFF, sum = 0
6592 19:27:23.064496 4, 0xFFFF, sum = 0
6593 19:27:23.067013 5, 0xFFFF, sum = 0
6594 19:27:23.067444 6, 0xFFFF, sum = 0
6595 19:27:23.070291 7, 0xFFFF, sum = 0
6596 19:27:23.070708 8, 0xFFFF, sum = 0
6597 19:27:23.073640 9, 0xFFFF, sum = 0
6598 19:27:23.074085 10, 0xFFFF, sum = 0
6599 19:27:23.077443 11, 0xFFFF, sum = 0
6600 19:27:23.077872 12, 0x0, sum = 1
6601 19:27:23.080272 13, 0x0, sum = 2
6602 19:27:23.080687 14, 0x0, sum = 3
6603 19:27:23.083700 15, 0x0, sum = 4
6604 19:27:23.084114 best_step = 13
6605 19:27:23.084430
6606 19:27:23.084727 ==
6607 19:27:23.086996 Dram Type= 6, Freq= 0, CH_1, rank 0
6608 19:27:23.093655 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6609 19:27:23.094183 ==
6610 19:27:23.094520 RX Vref Scan: 1
6611 19:27:23.094881
6612 19:27:23.097241 RX Vref 0 -> 0, step: 1
6613 19:27:23.097650
6614 19:27:23.100291 RX Delay -359 -> 252, step: 8
6615 19:27:23.100716
6616 19:27:23.103676 Set Vref, RX VrefLevel [Byte0]: 53
6617 19:27:23.107106 [Byte1]: 52
6618 19:27:23.107517
6619 19:27:23.110393 Final RX Vref Byte 0 = 53 to rank0
6620 19:27:23.113393 Final RX Vref Byte 1 = 52 to rank0
6621 19:27:23.116797 Final RX Vref Byte 0 = 53 to rank1
6622 19:27:23.120336 Final RX Vref Byte 1 = 52 to rank1==
6623 19:27:23.123321 Dram Type= 6, Freq= 0, CH_1, rank 0
6624 19:27:23.126665 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6625 19:27:23.129894 ==
6626 19:27:23.130348 DQS Delay:
6627 19:27:23.130676 DQS0 = 48, DQS1 = 64
6628 19:27:23.133552 DQM Delay:
6629 19:27:23.133958 DQM0 = 8, DQM1 = 16
6630 19:27:23.136852 DQ Delay:
6631 19:27:23.137259 DQ0 =12, DQ1 =0, DQ2 =0, DQ3 =4
6632 19:27:23.140115 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =4
6633 19:27:23.143270 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6634 19:27:23.146819 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6635 19:27:23.147229
6636 19:27:23.147580
6637 19:27:23.156597 [DQSOSCAuto] RK0, (LSB)MR18= 0xd7d7, (MSB)MR19= 0xc0c, tDQSOscB0 = 383 ps tDQSOscB1 = 383 ps
6638 19:27:23.159863 CH1 RK0: MR19=C0C, MR18=D7D7
6639 19:27:23.166345 CH1_RK0: MR19=0xC0C, MR18=0xD7D7, DQSOSC=383, MR23=63, INC=402, DEC=268
6640 19:27:23.166847 ==
6641 19:27:23.169536 Dram Type= 6, Freq= 0, CH_1, rank 1
6642 19:27:23.172994 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6643 19:27:23.173477 ==
6644 19:27:23.176469 [Gating] SW mode calibration
6645 19:27:23.183035 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6646 19:27:23.186443 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6647 19:27:23.192804 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6648 19:27:23.195875 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6649 19:27:23.199442 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6650 19:27:23.206130 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
6651 19:27:23.209350 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6652 19:27:23.212781 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6653 19:27:23.219486 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6654 19:27:23.222427 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6655 19:27:23.225834 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6656 19:27:23.229319 Total UI for P1: 0, mck2ui 16
6657 19:27:23.232606 best dqsien dly found for B0: ( 0, 10, 16)
6658 19:27:23.235564 Total UI for P1: 0, mck2ui 16
6659 19:27:23.239101 best dqsien dly found for B1: ( 0, 10, 16)
6660 19:27:23.242298 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6661 19:27:23.249294 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6662 19:27:23.249706
6663 19:27:23.251997 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6664 19:27:23.255808 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6665 19:27:23.259108 [Gating] SW calibration Done
6666 19:27:23.259516 ==
6667 19:27:23.261934 Dram Type= 6, Freq= 0, CH_1, rank 1
6668 19:27:23.265428 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6669 19:27:23.265947 ==
6670 19:27:23.268857 RX Vref Scan: 0
6671 19:27:23.269266
6672 19:27:23.269588 RX Vref 0 -> 0, step: 1
6673 19:27:23.269883
6674 19:27:23.272500 RX Delay -410 -> 252, step: 16
6675 19:27:23.278949 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6676 19:27:23.281700 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6677 19:27:23.285655 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6678 19:27:23.288500 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6679 19:27:23.295001 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6680 19:27:23.298303 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6681 19:27:23.301843 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6682 19:27:23.305233 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6683 19:27:23.312169 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6684 19:27:23.315369 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6685 19:27:23.318562 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6686 19:27:23.321498 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6687 19:27:23.328262 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6688 19:27:23.331771 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6689 19:27:23.334941 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6690 19:27:23.337983 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6691 19:27:23.341354 ==
6692 19:27:23.344596 Dram Type= 6, Freq= 0, CH_1, rank 1
6693 19:27:23.348457 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6694 19:27:23.348873 ==
6695 19:27:23.349197 DQS Delay:
6696 19:27:23.351179 DQS0 = 35, DQS1 = 59
6697 19:27:23.351588 DQM Delay:
6698 19:27:23.354661 DQM0 = 3, DQM1 = 18
6699 19:27:23.355069 DQ Delay:
6700 19:27:23.357837 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6701 19:27:23.361434 DQ4 =0, DQ5 =16, DQ6 =8, DQ7 =0
6702 19:27:23.361844 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6703 19:27:23.367867 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =24
6704 19:27:23.368293
6705 19:27:23.368637
6706 19:27:23.368936 ==
6707 19:27:23.371320 Dram Type= 6, Freq= 0, CH_1, rank 1
6708 19:27:23.374750 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6709 19:27:23.375161 ==
6710 19:27:23.375481
6711 19:27:23.375775
6712 19:27:23.378095 TX Vref Scan disable
6713 19:27:23.378526 == TX Byte 0 ==
6714 19:27:23.381904 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6715 19:27:23.388200 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6716 19:27:23.388622 == TX Byte 1 ==
6717 19:27:23.391376 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6718 19:27:23.398093 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6719 19:27:23.398679 ==
6720 19:27:23.401555 Dram Type= 6, Freq= 0, CH_1, rank 1
6721 19:27:23.404555 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6722 19:27:23.404980 ==
6723 19:27:23.405310
6724 19:27:23.405617
6725 19:27:23.408349 TX Vref Scan disable
6726 19:27:23.408866 == TX Byte 0 ==
6727 19:27:23.414402 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6728 19:27:23.417717 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6729 19:27:23.418166 == TX Byte 1 ==
6730 19:27:23.424130 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6731 19:27:23.427601 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6732 19:27:23.428024
6733 19:27:23.428412 [DATLAT]
6734 19:27:23.431424 Freq=400, CH1 RK1
6735 19:27:23.431948
6736 19:27:23.432283 DATLAT Default: 0xd
6737 19:27:23.434190 0, 0xFFFF, sum = 0
6738 19:27:23.434617 1, 0xFFFF, sum = 0
6739 19:27:23.437838 2, 0xFFFF, sum = 0
6740 19:27:23.438418 3, 0xFFFF, sum = 0
6741 19:27:23.440921 4, 0xFFFF, sum = 0
6742 19:27:23.441348 5, 0xFFFF, sum = 0
6743 19:27:23.444193 6, 0xFFFF, sum = 0
6744 19:27:23.444617 7, 0xFFFF, sum = 0
6745 19:27:23.447484 8, 0xFFFF, sum = 0
6746 19:27:23.447909 9, 0xFFFF, sum = 0
6747 19:27:23.450736 10, 0xFFFF, sum = 0
6748 19:27:23.451163 11, 0xFFFF, sum = 0
6749 19:27:23.453840 12, 0x0, sum = 1
6750 19:27:23.454289 13, 0x0, sum = 2
6751 19:27:23.457207 14, 0x0, sum = 3
6752 19:27:23.457632 15, 0x0, sum = 4
6753 19:27:23.461036 best_step = 13
6754 19:27:23.461456
6755 19:27:23.461783 ==
6756 19:27:23.464126 Dram Type= 6, Freq= 0, CH_1, rank 1
6757 19:27:23.467214 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6758 19:27:23.467639 ==
6759 19:27:23.470486 RX Vref Scan: 0
6760 19:27:23.470921
6761 19:27:23.471250 RX Vref 0 -> 0, step: 1
6762 19:27:23.471578
6763 19:27:23.473882 RX Delay -359 -> 252, step: 8
6764 19:27:23.482254 iDelay=225, Bit 0, Center -36 (-279 ~ 208) 488
6765 19:27:23.485217 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
6766 19:27:23.488991 iDelay=225, Bit 2, Center -48 (-295 ~ 200) 496
6767 19:27:23.494920 iDelay=225, Bit 3, Center -44 (-287 ~ 200) 488
6768 19:27:23.498397 iDelay=225, Bit 4, Center -40 (-287 ~ 208) 496
6769 19:27:23.501678 iDelay=225, Bit 5, Center -24 (-271 ~ 224) 496
6770 19:27:23.505161 iDelay=225, Bit 6, Center -32 (-279 ~ 216) 496
6771 19:27:23.511713 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
6772 19:27:23.514909 iDelay=225, Bit 8, Center -64 (-311 ~ 184) 496
6773 19:27:23.518426 iDelay=225, Bit 9, Center -60 (-311 ~ 192) 504
6774 19:27:23.521682 iDelay=225, Bit 10, Center -48 (-295 ~ 200) 496
6775 19:27:23.528300 iDelay=225, Bit 11, Center -56 (-303 ~ 192) 496
6776 19:27:23.531474 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
6777 19:27:23.534548 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
6778 19:27:23.537879 iDelay=225, Bit 14, Center -36 (-287 ~ 216) 504
6779 19:27:23.544717 iDelay=225, Bit 15, Center -40 (-287 ~ 208) 496
6780 19:27:23.545277 ==
6781 19:27:23.548119 Dram Type= 6, Freq= 0, CH_1, rank 1
6782 19:27:23.551876 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6783 19:27:23.552305 ==
6784 19:27:23.552628 DQS Delay:
6785 19:27:23.554788 DQS0 = 48, DQS1 = 64
6786 19:27:23.555351 DQM Delay:
6787 19:27:23.558090 DQM0 = 9, DQM1 = 16
6788 19:27:23.558646 DQ Delay:
6789 19:27:23.561011 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6790 19:27:23.564445 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6791 19:27:23.567955 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6792 19:27:23.571115 DQ12 =28, DQ13 =24, DQ14 =28, DQ15 =24
6793 19:27:23.571674
6794 19:27:23.572090
6795 19:27:23.577810 [DQSOSCAuto] RK1, (LSB)MR18= 0xb5b5, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
6796 19:27:23.581197 CH1 RK1: MR19=C0C, MR18=B5B5
6797 19:27:23.587507 CH1_RK1: MR19=0xC0C, MR18=0xB5B5, DQSOSC=387, MR23=63, INC=394, DEC=262
6798 19:27:23.590886 [RxdqsGatingPostProcess] freq 400
6799 19:27:23.597654 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6800 19:27:23.600936 Pre-setting of DQS Precalculation
6801 19:27:23.604140 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6802 19:27:23.610828 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6803 19:27:23.617741 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6804 19:27:23.618295
6805 19:27:23.620716
6806 19:27:23.621158 [Calibration Summary] 800 Mbps
6807 19:27:23.624026 CH 0, Rank 0
6808 19:27:23.624448 SW Impedance : PASS
6809 19:27:23.627408 DUTY Scan : NO K
6810 19:27:23.630756 ZQ Calibration : PASS
6811 19:27:23.631173 Jitter Meter : NO K
6812 19:27:23.634056 CBT Training : PASS
6813 19:27:23.637438 Write leveling : PASS
6814 19:27:23.637856 RX DQS gating : PASS
6815 19:27:23.640439 RX DQ/DQS(RDDQC) : PASS
6816 19:27:23.643984 TX DQ/DQS : PASS
6817 19:27:23.644404 RX DATLAT : PASS
6818 19:27:23.647433 RX DQ/DQS(Engine): PASS
6819 19:27:23.650567 TX OE : NO K
6820 19:27:23.650990 All Pass.
6821 19:27:23.651319
6822 19:27:23.651626 CH 0, Rank 1
6823 19:27:23.653910 SW Impedance : PASS
6824 19:27:23.657010 DUTY Scan : NO K
6825 19:27:23.657423 ZQ Calibration : PASS
6826 19:27:23.660506 Jitter Meter : NO K
6827 19:27:23.663960 CBT Training : PASS
6828 19:27:23.664379 Write leveling : NO K
6829 19:27:23.666912 RX DQS gating : PASS
6830 19:27:23.670084 RX DQ/DQS(RDDQC) : PASS
6831 19:27:23.670506 TX DQ/DQS : PASS
6832 19:27:23.673704 RX DATLAT : PASS
6833 19:27:23.674257 RX DQ/DQS(Engine): PASS
6834 19:27:23.676605 TX OE : NO K
6835 19:27:23.677178 All Pass.
6836 19:27:23.677519
6837 19:27:23.680111 CH 1, Rank 0
6838 19:27:23.683398 SW Impedance : PASS
6839 19:27:23.683817 DUTY Scan : NO K
6840 19:27:23.686666 ZQ Calibration : PASS
6841 19:27:23.687083 Jitter Meter : NO K
6842 19:27:23.689888 CBT Training : PASS
6843 19:27:23.693532 Write leveling : PASS
6844 19:27:23.694146 RX DQS gating : PASS
6845 19:27:23.696999 RX DQ/DQS(RDDQC) : PASS
6846 19:27:23.700091 TX DQ/DQS : PASS
6847 19:27:23.700509 RX DATLAT : PASS
6848 19:27:23.703244 RX DQ/DQS(Engine): PASS
6849 19:27:23.706482 TX OE : NO K
6850 19:27:23.706896 All Pass.
6851 19:27:23.707215
6852 19:27:23.707600 CH 1, Rank 1
6853 19:27:23.709643 SW Impedance : PASS
6854 19:27:23.713337 DUTY Scan : NO K
6855 19:27:23.713746 ZQ Calibration : PASS
6856 19:27:23.716597 Jitter Meter : NO K
6857 19:27:23.719782 CBT Training : PASS
6858 19:27:23.720196 Write leveling : NO K
6859 19:27:23.723241 RX DQS gating : PASS
6860 19:27:23.726434 RX DQ/DQS(RDDQC) : PASS
6861 19:27:23.726848 TX DQ/DQS : PASS
6862 19:27:23.729838 RX DATLAT : PASS
6863 19:27:23.732788 RX DQ/DQS(Engine): PASS
6864 19:27:23.733201 TX OE : NO K
6865 19:27:23.733525 All Pass.
6866 19:27:23.736440
6867 19:27:23.736848 DramC Write-DBI off
6868 19:27:23.739740 PER_BANK_REFRESH: Hybrid Mode
6869 19:27:23.740151 TX_TRACKING: ON
6870 19:27:23.749574 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6871 19:27:23.753145 [FAST_K] Save calibration result to emmc
6872 19:27:23.756336 dramc_set_vcore_voltage set vcore to 725000
6873 19:27:23.759239 Read voltage for 1600, 0
6874 19:27:23.759652 Vio18 = 0
6875 19:27:23.762977 Vcore = 725000
6876 19:27:23.763388 Vdram = 0
6877 19:27:23.763711 Vddq = 0
6878 19:27:23.764013 Vmddr = 0
6879 19:27:23.769259 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6880 19:27:23.775971 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6881 19:27:23.776453 MEM_TYPE=3, freq_sel=13
6882 19:27:23.779285 sv_algorithm_assistance_LP4_3733
6883 19:27:23.785809 ============ PULL DRAM RESETB DOWN ============
6884 19:27:23.789107 ========== PULL DRAM RESETB DOWN end =========
6885 19:27:23.792958 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6886 19:27:23.795971 ===================================
6887 19:27:23.798904 LPDDR4 DRAM CONFIGURATION
6888 19:27:23.802505 ===================================
6889 19:27:23.802917 EX_ROW_EN[0] = 0x0
6890 19:27:23.805719 EX_ROW_EN[1] = 0x0
6891 19:27:23.809148 LP4Y_EN = 0x0
6892 19:27:23.809560 WORK_FSP = 0x1
6893 19:27:23.812509 WL = 0x5
6894 19:27:23.812924 RL = 0x5
6895 19:27:23.815507 BL = 0x2
6896 19:27:23.815919 RPST = 0x0
6897 19:27:23.819089 RD_PRE = 0x0
6898 19:27:23.819501 WR_PRE = 0x1
6899 19:27:23.822480 WR_PST = 0x1
6900 19:27:23.822910 DBI_WR = 0x0
6901 19:27:23.825845 DBI_RD = 0x0
6902 19:27:23.826442 OTF = 0x1
6903 19:27:23.828847 ===================================
6904 19:27:23.832259 ===================================
6905 19:27:23.835619 ANA top config
6906 19:27:23.838634 ===================================
6907 19:27:23.839102 DLL_ASYNC_EN = 0
6908 19:27:23.842170 ALL_SLAVE_EN = 0
6909 19:27:23.845578 NEW_RANK_MODE = 1
6910 19:27:23.848720 DLL_IDLE_MODE = 1
6911 19:27:23.852308 LP45_APHY_COMB_EN = 1
6912 19:27:23.852718 TX_ODT_DIS = 0
6913 19:27:23.855336 NEW_8X_MODE = 1
6914 19:27:23.858537 ===================================
6915 19:27:23.861782 ===================================
6916 19:27:23.864976 data_rate = 3200
6917 19:27:23.868560 CKR = 1
6918 19:27:23.871961 DQ_P2S_RATIO = 8
6919 19:27:23.875116 ===================================
6920 19:27:23.878640 CA_P2S_RATIO = 8
6921 19:27:23.879141 DQ_CA_OPEN = 0
6922 19:27:23.881928 DQ_SEMI_OPEN = 0
6923 19:27:23.885318 CA_SEMI_OPEN = 0
6924 19:27:23.888148 CA_FULL_RATE = 0
6925 19:27:23.891746 DQ_CKDIV4_EN = 0
6926 19:27:23.895153 CA_CKDIV4_EN = 0
6927 19:27:23.895578 CA_PREDIV_EN = 0
6928 19:27:23.897942 PH8_DLY = 12
6929 19:27:23.901540 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6930 19:27:23.904629 DQ_AAMCK_DIV = 4
6931 19:27:23.908038 CA_AAMCK_DIV = 4
6932 19:27:23.911296 CA_ADMCK_DIV = 4
6933 19:27:23.911708 DQ_TRACK_CA_EN = 0
6934 19:27:23.915051 CA_PICK = 1600
6935 19:27:23.918104 CA_MCKIO = 1600
6936 19:27:23.921343 MCKIO_SEMI = 0
6937 19:27:23.924715 PLL_FREQ = 3068
6938 19:27:23.927699 DQ_UI_PI_RATIO = 32
6939 19:27:23.931154 CA_UI_PI_RATIO = 0
6940 19:27:23.934583 ===================================
6941 19:27:23.938104 ===================================
6942 19:27:23.938664 memory_type:LPDDR4
6943 19:27:23.941273 GP_NUM : 10
6944 19:27:23.944666 SRAM_EN : 1
6945 19:27:23.945075 MD32_EN : 0
6946 19:27:23.947545 ===================================
6947 19:27:23.951113 [ANA_INIT] >>>>>>>>>>>>>>
6948 19:27:23.954121 <<<<<< [CONFIGURE PHASE]: ANA_TX
6949 19:27:23.957669 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6950 19:27:23.960829 ===================================
6951 19:27:23.964044 data_rate = 3200,PCW = 0X7600
6952 19:27:23.967468 ===================================
6953 19:27:23.970744 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6954 19:27:23.974481 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6955 19:27:23.980613 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6956 19:27:23.983971 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6957 19:27:23.990439 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6958 19:27:23.993869 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6959 19:27:23.994324 [ANA_INIT] flow start
6960 19:27:23.997352 [ANA_INIT] PLL >>>>>>>>
6961 19:27:24.000565 [ANA_INIT] PLL <<<<<<<<
6962 19:27:24.000981 [ANA_INIT] MIDPI >>>>>>>>
6963 19:27:24.004172 [ANA_INIT] MIDPI <<<<<<<<
6964 19:27:24.006801 [ANA_INIT] DLL >>>>>>>>
6965 19:27:24.007213 [ANA_INIT] DLL <<<<<<<<
6966 19:27:24.010182 [ANA_INIT] flow end
6967 19:27:24.013579 ============ LP4 DIFF to SE enter ============
6968 19:27:24.016792 ============ LP4 DIFF to SE exit ============
6969 19:27:24.020264 [ANA_INIT] <<<<<<<<<<<<<
6970 19:27:24.023749 [Flow] Enable top DCM control >>>>>
6971 19:27:24.027146 [Flow] Enable top DCM control <<<<<
6972 19:27:24.030210 Enable DLL master slave shuffle
6973 19:27:24.036657 ==============================================================
6974 19:27:24.037163 Gating Mode config
6975 19:27:24.043339 ==============================================================
6976 19:27:24.046452 Config description:
6977 19:27:24.053340 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6978 19:27:24.059923 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6979 19:27:24.066367 SELPH_MODE 0: By rank 1: By Phase
6980 19:27:24.073475 ==============================================================
6981 19:27:24.076406 GAT_TRACK_EN = 1
6982 19:27:24.076841 RX_GATING_MODE = 2
6983 19:27:24.079836 RX_GATING_TRACK_MODE = 2
6984 19:27:24.083281 SELPH_MODE = 1
6985 19:27:24.086007 PICG_EARLY_EN = 1
6986 19:27:24.089764 VALID_LAT_VALUE = 1
6987 19:27:24.096009 ==============================================================
6988 19:27:24.099213 Enter into Gating configuration >>>>
6989 19:27:24.102658 Exit from Gating configuration <<<<
6990 19:27:24.105782 Enter into DVFS_PRE_config >>>>>
6991 19:27:24.115967 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6992 19:27:24.119221 Exit from DVFS_PRE_config <<<<<
6993 19:27:24.122679 Enter into PICG configuration >>>>
6994 19:27:24.125756 Exit from PICG configuration <<<<
6995 19:27:24.128905 [RX_INPUT] configuration >>>>>
6996 19:27:24.132256 [RX_INPUT] configuration <<<<<
6997 19:27:24.135561 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6998 19:27:24.142344 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6999 19:27:24.149097 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7000 19:27:24.155659 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7001 19:27:24.159038 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7002 19:27:24.165508 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7003 19:27:24.168839 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7004 19:27:24.175372 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7005 19:27:24.178561 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7006 19:27:24.182200 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7007 19:27:24.185536 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7008 19:27:24.192039 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7009 19:27:24.195375 ===================================
7010 19:27:24.198459 LPDDR4 DRAM CONFIGURATION
7011 19:27:24.201833 ===================================
7012 19:27:24.202418 EX_ROW_EN[0] = 0x0
7013 19:27:24.205115 EX_ROW_EN[1] = 0x0
7014 19:27:24.205647 LP4Y_EN = 0x0
7015 19:27:24.208180 WORK_FSP = 0x1
7016 19:27:24.208752 WL = 0x5
7017 19:27:24.211558 RL = 0x5
7018 19:27:24.212120 BL = 0x2
7019 19:27:24.214766 RPST = 0x0
7020 19:27:24.215327 RD_PRE = 0x0
7021 19:27:24.218324 WR_PRE = 0x1
7022 19:27:24.218883 WR_PST = 0x1
7023 19:27:24.221994 DBI_WR = 0x0
7024 19:27:24.222497 DBI_RD = 0x0
7025 19:27:24.225299 OTF = 0x1
7026 19:27:24.228304 ===================================
7027 19:27:24.231478 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7028 19:27:24.234552 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7029 19:27:24.241555 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7030 19:27:24.244823 ===================================
7031 19:27:24.245444 LPDDR4 DRAM CONFIGURATION
7032 19:27:24.248180 ===================================
7033 19:27:24.251405 EX_ROW_EN[0] = 0x10
7034 19:27:24.254814 EX_ROW_EN[1] = 0x0
7035 19:27:24.255226 LP4Y_EN = 0x0
7036 19:27:24.257974 WORK_FSP = 0x1
7037 19:27:24.258417 WL = 0x5
7038 19:27:24.261284 RL = 0x5
7039 19:27:24.261699 BL = 0x2
7040 19:27:24.264461 RPST = 0x0
7041 19:27:24.264945 RD_PRE = 0x0
7042 19:27:24.268038 WR_PRE = 0x1
7043 19:27:24.268465 WR_PST = 0x1
7044 19:27:24.271299 DBI_WR = 0x0
7045 19:27:24.271857 DBI_RD = 0x0
7046 19:27:24.274641 OTF = 0x1
7047 19:27:24.277838 ===================================
7048 19:27:24.284524 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7049 19:27:24.285097 ==
7050 19:27:24.288120 Dram Type= 6, Freq= 0, CH_0, rank 0
7051 19:27:24.291223 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7052 19:27:24.291726 ==
7053 19:27:24.294201 [Duty_Offset_Calibration]
7054 19:27:24.294741 B0:0 B1:2 CA:1
7055 19:27:24.295151
7056 19:27:24.297866 [DutyScan_Calibration_Flow] k_type=0
7057 19:27:24.308876
7058 19:27:24.309507 ==CLK 0==
7059 19:27:24.312069 Final CLK duty delay cell = 0
7060 19:27:24.315661 [0] MAX Duty = 5156%(X100), DQS PI = 22
7061 19:27:24.318489 [0] MIN Duty = 4938%(X100), DQS PI = 52
7062 19:27:24.319062 [0] AVG Duty = 5047%(X100)
7063 19:27:24.321900
7064 19:27:24.325292 CH0 CLK Duty spec in!! Max-Min= 218%
7065 19:27:24.328463 [DutyScan_Calibration_Flow] ====Done====
7066 19:27:24.329109
7067 19:27:24.332070 [DutyScan_Calibration_Flow] k_type=1
7068 19:27:24.349033
7069 19:27:24.349446 ==DQS 0 ==
7070 19:27:24.352106 Final DQS duty delay cell = 0
7071 19:27:24.355236 [0] MAX Duty = 5125%(X100), DQS PI = 30
7072 19:27:24.358467 [0] MIN Duty = 5031%(X100), DQS PI = 8
7073 19:27:24.359003 [0] AVG Duty = 5078%(X100)
7074 19:27:24.361929
7075 19:27:24.362395 ==DQS 1 ==
7076 19:27:24.365400 Final DQS duty delay cell = 0
7077 19:27:24.368699 [0] MAX Duty = 5031%(X100), DQS PI = 4
7078 19:27:24.371926 [0] MIN Duty = 4876%(X100), DQS PI = 16
7079 19:27:24.375432 [0] AVG Duty = 4953%(X100)
7080 19:27:24.375954
7081 19:27:24.378556 CH0 DQS 0 Duty spec in!! Max-Min= 94%
7082 19:27:24.379064
7083 19:27:24.382117 CH0 DQS 1 Duty spec in!! Max-Min= 155%
7084 19:27:24.385427 [DutyScan_Calibration_Flow] ====Done====
7085 19:27:24.386002
7086 19:27:24.388390 [DutyScan_Calibration_Flow] k_type=3
7087 19:27:24.405495
7088 19:27:24.405919 ==DQM 0 ==
7089 19:27:24.409048 Final DQM duty delay cell = 0
7090 19:27:24.412196 [0] MAX Duty = 5187%(X100), DQS PI = 22
7091 19:27:24.415740 [0] MIN Duty = 4907%(X100), DQS PI = 42
7092 19:27:24.418710 [0] AVG Duty = 5047%(X100)
7093 19:27:24.419133
7094 19:27:24.419455 ==DQM 1 ==
7095 19:27:24.422139 Final DQM duty delay cell = 0
7096 19:27:24.425756 [0] MAX Duty = 5000%(X100), DQS PI = 4
7097 19:27:24.428742 [0] MIN Duty = 4782%(X100), DQS PI = 14
7098 19:27:24.432309 [0] AVG Duty = 4891%(X100)
7099 19:27:24.432720
7100 19:27:24.435232 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7101 19:27:24.435643
7102 19:27:24.438693 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7103 19:27:24.442101 [DutyScan_Calibration_Flow] ====Done====
7104 19:27:24.442513
7105 19:27:24.445093 [DutyScan_Calibration_Flow] k_type=2
7106 19:27:24.462261
7107 19:27:24.462778 ==DQ 0 ==
7108 19:27:24.465269 Final DQ duty delay cell = 0
7109 19:27:24.468959 [0] MAX Duty = 5218%(X100), DQS PI = 18
7110 19:27:24.472001 [0] MIN Duty = 4938%(X100), DQS PI = 56
7111 19:27:24.472412 [0] AVG Duty = 5078%(X100)
7112 19:27:24.475658
7113 19:27:24.476065 ==DQ 1 ==
7114 19:27:24.478799 Final DQ duty delay cell = -4
7115 19:27:24.482245 [-4] MAX Duty = 5094%(X100), DQS PI = 4
7116 19:27:24.485523 [-4] MIN Duty = 4844%(X100), DQS PI = 26
7117 19:27:24.488541 [-4] AVG Duty = 4969%(X100)
7118 19:27:24.488950
7119 19:27:24.492073 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7120 19:27:24.492527
7121 19:27:24.495385 CH0 DQ 1 Duty spec in!! Max-Min= 250%
7122 19:27:24.498675 [DutyScan_Calibration_Flow] ====Done====
7123 19:27:24.499131 ==
7124 19:27:24.501596 Dram Type= 6, Freq= 0, CH_1, rank 0
7125 19:27:24.505220 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7126 19:27:24.505646 ==
7127 19:27:24.508265 [Duty_Offset_Calibration]
7128 19:27:24.508672 B0:0 B1:5 CA:-5
7129 19:27:24.508989
7130 19:27:24.511351 [DutyScan_Calibration_Flow] k_type=0
7131 19:27:24.522778
7132 19:27:24.523231 ==CLK 0==
7133 19:27:24.525946 Final CLK duty delay cell = 0
7134 19:27:24.529239 [0] MAX Duty = 5156%(X100), DQS PI = 22
7135 19:27:24.533039 [0] MIN Duty = 4875%(X100), DQS PI = 52
7136 19:27:24.533549 [0] AVG Duty = 5015%(X100)
7137 19:27:24.536212
7138 19:27:24.539771 CH1 CLK Duty spec in!! Max-Min= 281%
7139 19:27:24.542774 [DutyScan_Calibration_Flow] ====Done====
7140 19:27:24.543262
7141 19:27:24.546146 [DutyScan_Calibration_Flow] k_type=1
7142 19:27:24.561570
7143 19:27:24.562021 ==DQS 0 ==
7144 19:27:24.565067 Final DQS duty delay cell = 0
7145 19:27:24.568221 [0] MAX Duty = 5187%(X100), DQS PI = 18
7146 19:27:24.571748 [0] MIN Duty = 4876%(X100), DQS PI = 42
7147 19:27:24.575181 [0] AVG Duty = 5031%(X100)
7148 19:27:24.575660
7149 19:27:24.576062 ==DQS 1 ==
7150 19:27:24.578440 Final DQS duty delay cell = -4
7151 19:27:24.581557 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7152 19:27:24.585315 [-4] MIN Duty = 4844%(X100), DQS PI = 40
7153 19:27:24.588434 [-4] AVG Duty = 4922%(X100)
7154 19:27:24.588916
7155 19:27:24.591330 CH1 DQS 0 Duty spec in!! Max-Min= 311%
7156 19:27:24.591783
7157 19:27:24.594846 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7158 19:27:24.598194 [DutyScan_Calibration_Flow] ====Done====
7159 19:27:24.598608
7160 19:27:24.601678 [DutyScan_Calibration_Flow] k_type=3
7161 19:27:24.617435
7162 19:27:24.617919 ==DQM 0 ==
7163 19:27:24.620871 Final DQM duty delay cell = -4
7164 19:27:24.623760 [-4] MAX Duty = 5093%(X100), DQS PI = 34
7165 19:27:24.626986 [-4] MIN Duty = 4782%(X100), DQS PI = 42
7166 19:27:24.630472 [-4] AVG Duty = 4937%(X100)
7167 19:27:24.630887
7168 19:27:24.631212 ==DQM 1 ==
7169 19:27:24.633909 Final DQM duty delay cell = -4
7170 19:27:24.637101 [-4] MAX Duty = 5031%(X100), DQS PI = 0
7171 19:27:24.640300 [-4] MIN Duty = 4907%(X100), DQS PI = 36
7172 19:27:24.643845 [-4] AVG Duty = 4969%(X100)
7173 19:27:24.644275
7174 19:27:24.646939 CH1 DQM 0 Duty spec in!! Max-Min= 311%
7175 19:27:24.647469
7176 19:27:24.650206 CH1 DQM 1 Duty spec in!! Max-Min= 124%
7177 19:27:24.653743 [DutyScan_Calibration_Flow] ====Done====
7178 19:27:24.654317
7179 19:27:24.657090 [DutyScan_Calibration_Flow] k_type=2
7180 19:27:24.675255
7181 19:27:24.675816 ==DQ 0 ==
7182 19:27:24.678111 Final DQ duty delay cell = 0
7183 19:27:24.681737 [0] MAX Duty = 5062%(X100), DQS PI = 0
7184 19:27:24.684625 [0] MIN Duty = 4938%(X100), DQS PI = 46
7185 19:27:24.685219 [0] AVG Duty = 5000%(X100)
7186 19:27:24.685639
7187 19:27:24.688072 ==DQ 1 ==
7188 19:27:24.691207 Final DQ duty delay cell = 0
7189 19:27:24.694746 [0] MAX Duty = 5031%(X100), DQS PI = 4
7190 19:27:24.697967 [0] MIN Duty = 4875%(X100), DQS PI = 28
7191 19:27:24.698474 [0] AVG Duty = 4953%(X100)
7192 19:27:24.698835
7193 19:27:24.701803 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7194 19:27:24.704453
7195 19:27:24.708392 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7196 19:27:24.711476 [DutyScan_Calibration_Flow] ====Done====
7197 19:27:24.714584 nWR fixed to 30
7198 19:27:24.715054 [ModeRegInit_LP4] CH0 RK0
7199 19:27:24.718019 [ModeRegInit_LP4] CH0 RK1
7200 19:27:24.721482 [ModeRegInit_LP4] CH1 RK0
7201 19:27:24.724437 [ModeRegInit_LP4] CH1 RK1
7202 19:27:24.724922 match AC timing 4
7203 19:27:24.727765 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7204 19:27:24.734581 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7205 19:27:24.737574 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7206 19:27:24.744397 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7207 19:27:24.747527 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7208 19:27:24.748131 [MiockJmeterHQA]
7209 19:27:24.748493
7210 19:27:24.750889 [DramcMiockJmeter] u1RxGatingPI = 0
7211 19:27:24.754308 0 : 4255, 4030
7212 19:27:24.754738 4 : 4252, 4027
7213 19:27:24.757676 8 : 4252, 4027
7214 19:27:24.758140 12 : 4252, 4027
7215 19:27:24.758485 16 : 4363, 4137
7216 19:27:24.761221 20 : 4253, 4026
7217 19:27:24.761643 24 : 4252, 4027
7218 19:27:24.764233 28 : 4252, 4027
7219 19:27:24.764655 32 : 4253, 4026
7220 19:27:24.767770 36 : 4363, 4138
7221 19:27:24.768192 40 : 4253, 4026
7222 19:27:24.768524 44 : 4365, 4140
7223 19:27:24.771393 48 : 4252, 4027
7224 19:27:24.771840 52 : 4253, 4027
7225 19:27:24.774396 56 : 4250, 4027
7226 19:27:24.774818 60 : 4360, 4137
7227 19:27:24.777607 64 : 4250, 4027
7228 19:27:24.778067 68 : 4361, 4138
7229 19:27:24.781095 72 : 4250, 4027
7230 19:27:24.781658 76 : 4250, 4027
7231 19:27:24.782017 80 : 4250, 4027
7232 19:27:24.784511 84 : 4250, 4026
7233 19:27:24.784933 88 : 4361, 4137
7234 19:27:24.787778 92 : 4250, 4027
7235 19:27:24.788218 96 : 4361, 4137
7236 19:27:24.790533 100 : 4250, 1721
7237 19:27:24.791186 104 : 4361, 0
7238 19:27:24.791650 108 : 4361, 0
7239 19:27:24.794136 112 : 4363, 0
7240 19:27:24.794568 116 : 4250, 0
7241 19:27:24.797818 120 : 4250, 0
7242 19:27:24.798282 124 : 4250, 0
7243 19:27:24.798619 128 : 4250, 0
7244 19:27:24.801010 132 : 4250, 0
7245 19:27:24.801434 136 : 4250, 0
7246 19:27:24.804093 140 : 4250, 0
7247 19:27:24.804518 144 : 4250, 0
7248 19:27:24.804852 148 : 4361, 0
7249 19:27:24.807494 152 : 4250, 0
7250 19:27:24.807918 156 : 4361, 0
7251 19:27:24.811224 160 : 4361, 0
7252 19:27:24.811752 164 : 4361, 0
7253 19:27:24.812092 168 : 4250, 0
7254 19:27:24.813680 172 : 4250, 0
7255 19:27:24.814251 176 : 4250, 0
7256 19:27:24.817162 180 : 4250, 0
7257 19:27:24.817585 184 : 4250, 0
7258 19:27:24.817918 188 : 4250, 0
7259 19:27:24.820510 192 : 4250, 0
7260 19:27:24.820932 196 : 4360, 0
7261 19:27:24.821263 200 : 4361, 0
7262 19:27:24.823784 204 : 4248, 0
7263 19:27:24.824193 208 : 4250, 0
7264 19:27:24.827389 212 : 4361, 0
7265 19:27:24.827811 216 : 4361, 0
7266 19:27:24.828142 220 : 4250, 693
7267 19:27:24.830803 224 : 4250, 4006
7268 19:27:24.831230 228 : 4361, 4137
7269 19:27:24.833909 232 : 4361, 4138
7270 19:27:24.834398 236 : 4250, 4027
7271 19:27:24.837540 240 : 4361, 4137
7272 19:27:24.838213 244 : 4361, 4138
7273 19:27:24.840276 248 : 4250, 4027
7274 19:27:24.840700 252 : 4250, 4027
7275 19:27:24.843441 256 : 4250, 4027
7276 19:27:24.843751 260 : 4250, 4027
7277 19:27:24.846998 264 : 4249, 4027
7278 19:27:24.847305 268 : 4250, 4027
7279 19:27:24.850293 272 : 4250, 4027
7280 19:27:24.850640 276 : 4250, 4027
7281 19:27:24.851026 280 : 4361, 4138
7282 19:27:24.853510 284 : 4360, 4137
7283 19:27:24.853819 288 : 4248, 4024
7284 19:27:24.856909 292 : 4361, 4137
7285 19:27:24.857214 296 : 4361, 4138
7286 19:27:24.860035 300 : 4250, 4027
7287 19:27:24.860342 304 : 4250, 4026
7288 19:27:24.864123 308 : 4250, 4026
7289 19:27:24.864430 312 : 4250, 4027
7290 19:27:24.866811 316 : 4250, 4027
7291 19:27:24.867120 320 : 4250, 4026
7292 19:27:24.870809 324 : 4250, 4027
7293 19:27:24.871127 328 : 4250, 4027
7294 19:27:24.873604 332 : 4361, 4138
7295 19:27:24.873912 336 : 4360, 3804
7296 19:27:24.874254 340 : 4248, 1885
7297 19:27:24.877073
7298 19:27:24.877375 MIOCK jitter meter ch=0
7299 19:27:24.877680
7300 19:27:24.880626 1T = (340-100) = 240 dly cells
7301 19:27:24.886723 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7302 19:27:24.887038 ==
7303 19:27:24.890302 Dram Type= 6, Freq= 0, CH_0, rank 0
7304 19:27:24.893472 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7305 19:27:24.893803 ==
7306 19:27:24.900115 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7307 19:27:24.903383 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7308 19:27:24.906427 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7309 19:27:24.913190 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7310 19:27:24.921940 [CA 0] Center 42 (12~72) winsize 61
7311 19:27:24.925234 [CA 1] Center 41 (11~72) winsize 62
7312 19:27:24.928716 [CA 2] Center 37 (7~68) winsize 62
7313 19:27:24.931545 [CA 3] Center 37 (7~67) winsize 61
7314 19:27:24.935142 [CA 4] Center 35 (5~66) winsize 62
7315 19:27:24.938290 [CA 5] Center 35 (5~65) winsize 61
7316 19:27:24.938720
7317 19:27:24.941572 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7318 19:27:24.942121
7319 19:27:24.945222 [CATrainingPosCal] consider 1 rank data
7320 19:27:24.948508 u2DelayCellTimex100 = 271/100 ps
7321 19:27:24.954921 CA0 delay=42 (12~72),Diff = 7 PI (25 cell)
7322 19:27:24.958308 CA1 delay=41 (11~72),Diff = 6 PI (21 cell)
7323 19:27:24.961166 CA2 delay=37 (7~68),Diff = 2 PI (7 cell)
7324 19:27:24.965274 CA3 delay=37 (7~67),Diff = 2 PI (7 cell)
7325 19:27:24.968410 CA4 delay=35 (5~66),Diff = 0 PI (0 cell)
7326 19:27:24.971752 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7327 19:27:24.972233
7328 19:27:24.974680 CA PerBit enable=1, Macro0, CA PI delay=35
7329 19:27:24.975066
7330 19:27:24.978124 [CBTSetCACLKResult] CA Dly = 35
7331 19:27:24.981599 CS Dly: 11 (0~42)
7332 19:27:24.985158 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7333 19:27:24.987939 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7334 19:27:24.988371 ==
7335 19:27:24.991543 Dram Type= 6, Freq= 0, CH_0, rank 1
7336 19:27:24.994665 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7337 19:27:24.998149 ==
7338 19:27:25.001008 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7339 19:27:25.004730 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7340 19:27:25.011067 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7341 19:27:25.017650 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7342 19:27:25.025147 [CA 0] Center 42 (12~73) winsize 62
7343 19:27:25.027698 [CA 1] Center 42 (12~73) winsize 62
7344 19:27:25.031233 [CA 2] Center 38 (9~68) winsize 60
7345 19:27:25.034414 [CA 3] Center 38 (8~68) winsize 61
7346 19:27:25.037973 [CA 4] Center 36 (6~66) winsize 61
7347 19:27:25.041453 [CA 5] Center 36 (6~66) winsize 61
7348 19:27:25.041888
7349 19:27:25.044522 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7350 19:27:25.044908
7351 19:27:25.047498 [CATrainingPosCal] consider 2 rank data
7352 19:27:25.050816 u2DelayCellTimex100 = 271/100 ps
7353 19:27:25.054463 CA0 delay=42 (12~72),Diff = 7 PI (25 cell)
7354 19:27:25.060675 CA1 delay=42 (12~72),Diff = 7 PI (25 cell)
7355 19:27:25.064154 CA2 delay=38 (9~68),Diff = 3 PI (10 cell)
7356 19:27:25.067285 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7357 19:27:25.070905 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7358 19:27:25.074336 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7359 19:27:25.074723
7360 19:27:25.077280 CA PerBit enable=1, Macro0, CA PI delay=35
7361 19:27:25.077739
7362 19:27:25.080424 [CBTSetCACLKResult] CA Dly = 35
7363 19:27:25.083852 CS Dly: 11 (0~42)
7364 19:27:25.087151 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7365 19:27:25.090537 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7366 19:27:25.090914
7367 19:27:25.093816 ----->DramcWriteLeveling(PI) begin...
7368 19:27:25.094258 ==
7369 19:27:25.097274 Dram Type= 6, Freq= 0, CH_0, rank 0
7370 19:27:25.103923 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7371 19:27:25.104563 ==
7372 19:27:25.107541 Write leveling (Byte 0): 30 => 30
7373 19:27:25.110815 Write leveling (Byte 1): 25 => 25
7374 19:27:25.111203 DramcWriteLeveling(PI) end<-----
7375 19:27:25.113714
7376 19:27:25.114117 ==
7377 19:27:25.117229 Dram Type= 6, Freq= 0, CH_0, rank 0
7378 19:27:25.120422 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7379 19:27:25.120807 ==
7380 19:27:25.123635 [Gating] SW mode calibration
7381 19:27:25.130839 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7382 19:27:25.133510 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7383 19:27:25.140232 0 12 0 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 1)
7384 19:27:25.143348 0 12 4 | B1->B0 | 2323 3433 | 0 1 | (0 0) (1 1)
7385 19:27:25.146981 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7386 19:27:25.153547 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7387 19:27:25.156817 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7388 19:27:25.160049 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7389 19:27:25.166328 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7390 19:27:25.169704 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7391 19:27:25.173209 0 13 0 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
7392 19:27:25.179860 0 13 4 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (1 0)
7393 19:27:25.183109 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7394 19:27:25.186214 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7395 19:27:25.193041 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7396 19:27:25.196109 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7397 19:27:25.200043 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7398 19:27:25.206069 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7399 19:27:25.209431 0 14 0 | B1->B0 | 2323 3636 | 0 1 | (0 0) (0 0)
7400 19:27:25.212999 0 14 4 | B1->B0 | 3030 4646 | 0 0 | (1 1) (0 0)
7401 19:27:25.219463 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7402 19:27:25.222505 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7403 19:27:25.225924 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7404 19:27:25.232731 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7405 19:27:25.236444 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7406 19:27:25.239234 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7407 19:27:25.245757 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7408 19:27:25.248968 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7409 19:27:25.252677 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7410 19:27:25.259344 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7411 19:27:25.262509 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7412 19:27:25.266139 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7413 19:27:25.272324 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7414 19:27:25.275754 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7415 19:27:25.279175 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7416 19:27:25.285668 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7417 19:27:25.288812 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7418 19:27:25.292249 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7419 19:27:25.298451 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7420 19:27:25.302133 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7421 19:27:25.305459 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7422 19:27:25.312709 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7423 19:27:25.315182 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7424 19:27:25.318675 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7425 19:27:25.325024 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7426 19:27:25.325595 Total UI for P1: 0, mck2ui 16
7427 19:27:25.331932 best dqsien dly found for B0: ( 1, 1, 0)
7428 19:27:25.332487 Total UI for P1: 0, mck2ui 16
7429 19:27:25.338422 best dqsien dly found for B1: ( 1, 1, 2)
7430 19:27:25.342116 best DQS0 dly(MCK, UI, PI) = (1, 1, 0)
7431 19:27:25.345332 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
7432 19:27:25.345925
7433 19:27:25.348462 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 0)
7434 19:27:25.351563 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
7435 19:27:25.354973 [Gating] SW calibration Done
7436 19:27:25.355434 ==
7437 19:27:25.358353 Dram Type= 6, Freq= 0, CH_0, rank 0
7438 19:27:25.361600 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7439 19:27:25.362102 ==
7440 19:27:25.365164 RX Vref Scan: 0
7441 19:27:25.365716
7442 19:27:25.366229 RX Vref 0 -> 0, step: 1
7443 19:27:25.366739
7444 19:27:25.368414 RX Delay 0 -> 252, step: 8
7445 19:27:25.371416 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7446 19:27:25.378115 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7447 19:27:25.381486 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7448 19:27:25.384397 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7449 19:27:25.388181 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7450 19:27:25.391189 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7451 19:27:25.394603 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
7452 19:27:25.401404 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
7453 19:27:25.404399 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
7454 19:27:25.408286 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7455 19:27:25.411296 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7456 19:27:25.417812 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7457 19:27:25.421555 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7458 19:27:25.424293 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7459 19:27:25.427878 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
7460 19:27:25.431167 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7461 19:27:25.434219 ==
7462 19:27:25.434685 Dram Type= 6, Freq= 0, CH_0, rank 0
7463 19:27:25.440756 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7464 19:27:25.441306 ==
7465 19:27:25.441670 DQS Delay:
7466 19:27:25.444311 DQS0 = 0, DQS1 = 0
7467 19:27:25.444861 DQM Delay:
7468 19:27:25.447895 DQM0 = 129, DQM1 = 124
7469 19:27:25.448452 DQ Delay:
7470 19:27:25.450985 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =127
7471 19:27:25.454146 DQ4 =135, DQ5 =119, DQ6 =135, DQ7 =135
7472 19:27:25.457775 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
7473 19:27:25.461212 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7474 19:27:25.461766
7475 19:27:25.462181
7476 19:27:25.462526 ==
7477 19:27:25.464444 Dram Type= 6, Freq= 0, CH_0, rank 0
7478 19:27:25.470818 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7479 19:27:25.471375 ==
7480 19:27:25.471737
7481 19:27:25.472068
7482 19:27:25.472386 TX Vref Scan disable
7483 19:27:25.474869 == TX Byte 0 ==
7484 19:27:25.477993 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7485 19:27:25.484636 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7486 19:27:25.485187 == TX Byte 1 ==
7487 19:27:25.487515 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7488 19:27:25.494382 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7489 19:27:25.494952 ==
7490 19:27:25.497286 Dram Type= 6, Freq= 0, CH_0, rank 0
7491 19:27:25.500743 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7492 19:27:25.501210 ==
7493 19:27:25.513861
7494 19:27:25.516966 TX Vref early break, caculate TX vref
7495 19:27:25.520595 TX Vref=16, minBit 8, minWin=21, winSum=368
7496 19:27:25.523696 TX Vref=18, minBit 10, minWin=21, winSum=378
7497 19:27:25.527001 TX Vref=20, minBit 8, minWin=23, winSum=390
7498 19:27:25.530513 TX Vref=22, minBit 8, minWin=22, winSum=395
7499 19:27:25.533709 TX Vref=24, minBit 8, minWin=22, winSum=405
7500 19:27:25.539906 TX Vref=26, minBit 7, minWin=25, winSum=413
7501 19:27:25.543552 TX Vref=28, minBit 1, minWin=25, winSum=414
7502 19:27:25.546580 TX Vref=30, minBit 6, minWin=24, winSum=409
7503 19:27:25.550117 TX Vref=32, minBit 1, minWin=24, winSum=398
7504 19:27:25.553259 TX Vref=34, minBit 3, minWin=23, winSum=389
7505 19:27:25.560521 [TxChooseVref] Worse bit 1, Min win 25, Win sum 414, Final Vref 28
7506 19:27:25.561093
7507 19:27:25.563651 Final TX Range 0 Vref 28
7508 19:27:25.564110
7509 19:27:25.564465 ==
7510 19:27:25.566990 Dram Type= 6, Freq= 0, CH_0, rank 0
7511 19:27:25.569953 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7512 19:27:25.570433 ==
7513 19:27:25.570787
7514 19:27:25.571124
7515 19:27:25.573375 TX Vref Scan disable
7516 19:27:25.580025 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7517 19:27:25.580581 == TX Byte 0 ==
7518 19:27:25.583552 u2DelayCellOfst[0]=14 cells (4 PI)
7519 19:27:25.586436 u2DelayCellOfst[1]=18 cells (5 PI)
7520 19:27:25.589641 u2DelayCellOfst[2]=14 cells (4 PI)
7521 19:27:25.593469 u2DelayCellOfst[3]=14 cells (4 PI)
7522 19:27:25.596522 u2DelayCellOfst[4]=10 cells (3 PI)
7523 19:27:25.599635 u2DelayCellOfst[5]=0 cells (0 PI)
7524 19:27:25.603473 u2DelayCellOfst[6]=18 cells (5 PI)
7525 19:27:25.606212 u2DelayCellOfst[7]=18 cells (5 PI)
7526 19:27:25.609886 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7527 19:27:25.612946 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7528 19:27:25.616420 == TX Byte 1 ==
7529 19:27:25.619549 u2DelayCellOfst[8]=3 cells (1 PI)
7530 19:27:25.620005 u2DelayCellOfst[9]=0 cells (0 PI)
7531 19:27:25.622970 u2DelayCellOfst[10]=10 cells (3 PI)
7532 19:27:25.626286 u2DelayCellOfst[11]=7 cells (2 PI)
7533 19:27:25.629381 u2DelayCellOfst[12]=18 cells (5 PI)
7534 19:27:25.632997 u2DelayCellOfst[13]=14 cells (4 PI)
7535 19:27:25.636439 u2DelayCellOfst[14]=18 cells (5 PI)
7536 19:27:25.639372 u2DelayCellOfst[15]=14 cells (4 PI)
7537 19:27:25.642942 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
7538 19:27:25.649252 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
7539 19:27:25.649793 DramC Write-DBI on
7540 19:27:25.650183 ==
7541 19:27:25.652633 Dram Type= 6, Freq= 0, CH_0, rank 0
7542 19:27:25.659113 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7543 19:27:25.659667 ==
7544 19:27:25.660028
7545 19:27:25.660357
7546 19:27:25.660671 TX Vref Scan disable
7547 19:27:25.663144 == TX Byte 0 ==
7548 19:27:25.666789 Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3)
7549 19:27:25.670003 == TX Byte 1 ==
7550 19:27:25.673306 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
7551 19:27:25.676845 DramC Write-DBI off
7552 19:27:25.677398
7553 19:27:25.677756 [DATLAT]
7554 19:27:25.678119 Freq=1600, CH0 RK0
7555 19:27:25.678442
7556 19:27:25.679586 DATLAT Default: 0xf
7557 19:27:25.680038 0, 0xFFFF, sum = 0
7558 19:27:25.683269 1, 0xFFFF, sum = 0
7559 19:27:25.686690 2, 0xFFFF, sum = 0
7560 19:27:25.687251 3, 0xFFFF, sum = 0
7561 19:27:25.689834 4, 0xFFFF, sum = 0
7562 19:27:25.690331 5, 0xFFFF, sum = 0
7563 19:27:25.692736 6, 0xFFFF, sum = 0
7564 19:27:25.693199 7, 0xFFFF, sum = 0
7565 19:27:25.696091 8, 0xFFFF, sum = 0
7566 19:27:25.696551 9, 0xFFFF, sum = 0
7567 19:27:25.699361 10, 0xFFFF, sum = 0
7568 19:27:25.699858 11, 0xFFFF, sum = 0
7569 19:27:25.702768 12, 0x8FFF, sum = 0
7570 19:27:25.703247 13, 0x0, sum = 1
7571 19:27:25.706071 14, 0x0, sum = 2
7572 19:27:25.706534 15, 0x0, sum = 3
7573 19:27:25.709428 16, 0x0, sum = 4
7574 19:27:25.709891 best_step = 14
7575 19:27:25.710343
7576 19:27:25.710681 ==
7577 19:27:25.713005 Dram Type= 6, Freq= 0, CH_0, rank 0
7578 19:27:25.716179 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7579 19:27:25.719800 ==
7580 19:27:25.720398 RX Vref Scan: 1
7581 19:27:25.720935
7582 19:27:25.722730 Set Vref Range= 24 -> 127
7583 19:27:25.723184
7584 19:27:25.726081 RX Vref 24 -> 127, step: 1
7585 19:27:25.726542
7586 19:27:25.726897 RX Delay 11 -> 252, step: 4
7587 19:27:25.727227
7588 19:27:25.729326 Set Vref, RX VrefLevel [Byte0]: 24
7589 19:27:25.732898 [Byte1]: 24
7590 19:27:25.736647
7591 19:27:25.737202 Set Vref, RX VrefLevel [Byte0]: 25
7592 19:27:25.739716 [Byte1]: 25
7593 19:27:25.744327
7594 19:27:25.744882 Set Vref, RX VrefLevel [Byte0]: 26
7595 19:27:25.747426 [Byte1]: 26
7596 19:27:25.751925
7597 19:27:25.752476 Set Vref, RX VrefLevel [Byte0]: 27
7598 19:27:25.755148 [Byte1]: 27
7599 19:27:25.759387
7600 19:27:25.759942 Set Vref, RX VrefLevel [Byte0]: 28
7601 19:27:25.763165 [Byte1]: 28
7602 19:27:25.767159
7603 19:27:25.767612 Set Vref, RX VrefLevel [Byte0]: 29
7604 19:27:25.770378 [Byte1]: 29
7605 19:27:25.774523
7606 19:27:25.774977 Set Vref, RX VrefLevel [Byte0]: 30
7607 19:27:25.778344 [Byte1]: 30
7608 19:27:25.782391
7609 19:27:25.782947 Set Vref, RX VrefLevel [Byte0]: 31
7610 19:27:25.785839 [Byte1]: 31
7611 19:27:25.789951
7612 19:27:25.790554 Set Vref, RX VrefLevel [Byte0]: 32
7613 19:27:25.793351 [Byte1]: 32
7614 19:27:25.797942
7615 19:27:25.798539 Set Vref, RX VrefLevel [Byte0]: 33
7616 19:27:25.800648 [Byte1]: 33
7617 19:27:25.805221
7618 19:27:25.805774 Set Vref, RX VrefLevel [Byte0]: 34
7619 19:27:25.808540 [Byte1]: 34
7620 19:27:25.813250
7621 19:27:25.813801 Set Vref, RX VrefLevel [Byte0]: 35
7622 19:27:25.816520 [Byte1]: 35
7623 19:27:25.820576
7624 19:27:25.821128 Set Vref, RX VrefLevel [Byte0]: 36
7625 19:27:25.824169 [Byte1]: 36
7626 19:27:25.827926
7627 19:27:25.828417 Set Vref, RX VrefLevel [Byte0]: 37
7628 19:27:25.831100 [Byte1]: 37
7629 19:27:25.835839
7630 19:27:25.836390 Set Vref, RX VrefLevel [Byte0]: 38
7631 19:27:25.838752 [Byte1]: 38
7632 19:27:25.843371
7633 19:27:25.843925 Set Vref, RX VrefLevel [Byte0]: 39
7634 19:27:25.846233 [Byte1]: 39
7635 19:27:25.850945
7636 19:27:25.851633 Set Vref, RX VrefLevel [Byte0]: 40
7637 19:27:25.854435 [Byte1]: 40
7638 19:27:25.858260
7639 19:27:25.858759 Set Vref, RX VrefLevel [Byte0]: 41
7640 19:27:25.861749 [Byte1]: 41
7641 19:27:25.866136
7642 19:27:25.866698 Set Vref, RX VrefLevel [Byte0]: 42
7643 19:27:25.869199 [Byte1]: 42
7644 19:27:25.873835
7645 19:27:25.874360 Set Vref, RX VrefLevel [Byte0]: 43
7646 19:27:25.880338 [Byte1]: 43
7647 19:27:25.880806
7648 19:27:25.883588 Set Vref, RX VrefLevel [Byte0]: 44
7649 19:27:25.886937 [Byte1]: 44
7650 19:27:25.887388
7651 19:27:25.889727 Set Vref, RX VrefLevel [Byte0]: 45
7652 19:27:25.893234 [Byte1]: 45
7653 19:27:25.896815
7654 19:27:25.897470 Set Vref, RX VrefLevel [Byte0]: 46
7655 19:27:25.899823 [Byte1]: 46
7656 19:27:25.904646
7657 19:27:25.905197 Set Vref, RX VrefLevel [Byte0]: 47
7658 19:27:25.907892 [Byte1]: 47
7659 19:27:25.911426
7660 19:27:25.911879 Set Vref, RX VrefLevel [Byte0]: 48
7661 19:27:25.914844 [Byte1]: 48
7662 19:27:25.919164
7663 19:27:25.919717 Set Vref, RX VrefLevel [Byte0]: 49
7664 19:27:25.922655 [Byte1]: 49
7665 19:27:25.926958
7666 19:27:25.927427 Set Vref, RX VrefLevel [Byte0]: 50
7667 19:27:25.930484 [Byte1]: 50
7668 19:27:25.934326
7669 19:27:25.934808 Set Vref, RX VrefLevel [Byte0]: 51
7670 19:27:25.937842 [Byte1]: 51
7671 19:27:25.941895
7672 19:27:25.942417 Set Vref, RX VrefLevel [Byte0]: 52
7673 19:27:25.945553 [Byte1]: 52
7674 19:27:25.949830
7675 19:27:25.950349 Set Vref, RX VrefLevel [Byte0]: 53
7676 19:27:25.953113 [Byte1]: 53
7677 19:27:25.957397
7678 19:27:25.957822 Set Vref, RX VrefLevel [Byte0]: 54
7679 19:27:25.960570 [Byte1]: 54
7680 19:27:25.965041
7681 19:27:25.965510 Set Vref, RX VrefLevel [Byte0]: 55
7682 19:27:25.968067 [Byte1]: 55
7683 19:27:25.972517
7684 19:27:25.972985 Set Vref, RX VrefLevel [Byte0]: 56
7685 19:27:25.979292 [Byte1]: 56
7686 19:27:25.979765
7687 19:27:25.982332 Set Vref, RX VrefLevel [Byte0]: 57
7688 19:27:25.985886 [Byte1]: 57
7689 19:27:25.986509
7690 19:27:25.989385 Set Vref, RX VrefLevel [Byte0]: 58
7691 19:27:25.992414 [Byte1]: 58
7692 19:27:25.993001
7693 19:27:25.995430 Set Vref, RX VrefLevel [Byte0]: 59
7694 19:27:25.999233 [Byte1]: 59
7695 19:27:26.002882
7696 19:27:26.003336 Set Vref, RX VrefLevel [Byte0]: 60
7697 19:27:26.006489 [Byte1]: 60
7698 19:27:26.010428
7699 19:27:26.010953 Set Vref, RX VrefLevel [Byte0]: 61
7700 19:27:26.014226 [Byte1]: 61
7701 19:27:26.018610
7702 19:27:26.019185 Set Vref, RX VrefLevel [Byte0]: 62
7703 19:27:26.021593 [Byte1]: 62
7704 19:27:26.026012
7705 19:27:26.026749 Set Vref, RX VrefLevel [Byte0]: 63
7706 19:27:26.029313 [Byte1]: 63
7707 19:27:26.033252
7708 19:27:26.033780 Set Vref, RX VrefLevel [Byte0]: 64
7709 19:27:26.037361 [Byte1]: 64
7710 19:27:26.041053
7711 19:27:26.041605 Set Vref, RX VrefLevel [Byte0]: 65
7712 19:27:26.044746 [Byte1]: 65
7713 19:27:26.049212
7714 19:27:26.049769 Set Vref, RX VrefLevel [Byte0]: 66
7715 19:27:26.052334 [Byte1]: 66
7716 19:27:26.056091
7717 19:27:26.056558 Set Vref, RX VrefLevel [Byte0]: 67
7718 19:27:26.059647 [Byte1]: 67
7719 19:27:26.063974
7720 19:27:26.064622 Set Vref, RX VrefLevel [Byte0]: 68
7721 19:27:26.067087 [Byte1]: 68
7722 19:27:26.071563
7723 19:27:26.072073 Set Vref, RX VrefLevel [Byte0]: 69
7724 19:27:26.078163 [Byte1]: 69
7725 19:27:26.078626
7726 19:27:26.081219 Set Vref, RX VrefLevel [Byte0]: 70
7727 19:27:26.084856 [Byte1]: 70
7728 19:27:26.085422
7729 19:27:26.088227 Set Vref, RX VrefLevel [Byte0]: 71
7730 19:27:26.091136 [Byte1]: 71
7731 19:27:26.094484
7732 19:27:26.094954 Set Vref, RX VrefLevel [Byte0]: 72
7733 19:27:26.097896 [Byte1]: 72
7734 19:27:26.102187
7735 19:27:26.102911 Set Vref, RX VrefLevel [Byte0]: 73
7736 19:27:26.105054 [Byte1]: 73
7737 19:27:26.110098
7738 19:27:26.110835 Final RX Vref Byte 0 = 53 to rank0
7739 19:27:26.112692 Final RX Vref Byte 1 = 56 to rank0
7740 19:27:26.116174 Final RX Vref Byte 0 = 53 to rank1
7741 19:27:26.119541 Final RX Vref Byte 1 = 56 to rank1==
7742 19:27:26.123057 Dram Type= 6, Freq= 0, CH_0, rank 0
7743 19:27:26.129518 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7744 19:27:26.130123 ==
7745 19:27:26.130499 DQS Delay:
7746 19:27:26.133348 DQS0 = 0, DQS1 = 0
7747 19:27:26.133906 DQM Delay:
7748 19:27:26.134341 DQM0 = 127, DQM1 = 121
7749 19:27:26.135810 DQ Delay:
7750 19:27:26.139817 DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =124
7751 19:27:26.142746 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7752 19:27:26.146492 DQ8 =112, DQ9 =104, DQ10 =120, DQ11 =112
7753 19:27:26.149530 DQ12 =126, DQ13 =126, DQ14 =136, DQ15 =134
7754 19:27:26.150134
7755 19:27:26.150497
7756 19:27:26.150832
7757 19:27:26.152512 [DramC_TX_OE_Calibration] TA2
7758 19:27:26.155916 Original DQ_B0 (3 6) =30, OEN = 27
7759 19:27:26.159262 Original DQ_B1 (3 6) =30, OEN = 27
7760 19:27:26.162684 24, 0x0, End_B0=24 End_B1=24
7761 19:27:26.163264 25, 0x0, End_B0=25 End_B1=25
7762 19:27:26.165863 26, 0x0, End_B0=26 End_B1=26
7763 19:27:26.169427 27, 0x0, End_B0=27 End_B1=27
7764 19:27:26.172491 28, 0x0, End_B0=28 End_B1=28
7765 19:27:26.175808 29, 0x0, End_B0=29 End_B1=29
7766 19:27:26.176276 30, 0x0, End_B0=30 End_B1=30
7767 19:27:26.179267 31, 0x4141, End_B0=30 End_B1=30
7768 19:27:26.182998 Byte0 end_step=30 best_step=27
7769 19:27:26.185811 Byte1 end_step=30 best_step=27
7770 19:27:26.189556 Byte0 TX OE(2T, 0.5T) = (3, 3)
7771 19:27:26.192144 Byte1 TX OE(2T, 0.5T) = (3, 3)
7772 19:27:26.192665
7773 19:27:26.193035
7774 19:27:26.198747 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e1e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
7775 19:27:26.202458 CH0 RK0: MR19=303, MR18=1E1E
7776 19:27:26.208844 CH0_RK0: MR19=0x303, MR18=0x1E1E, DQSOSC=394, MR23=63, INC=23, DEC=15
7777 19:27:26.209413
7778 19:27:26.212262 ----->DramcWriteLeveling(PI) begin...
7779 19:27:26.212748 ==
7780 19:27:26.215386 Dram Type= 6, Freq= 0, CH_0, rank 1
7781 19:27:26.218945 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7782 19:27:26.219410 ==
7783 19:27:26.222557 Write leveling (Byte 0): 30 => 30
7784 19:27:26.225531 Write leveling (Byte 1): 28 => 28
7785 19:27:26.229035 DramcWriteLeveling(PI) end<-----
7786 19:27:26.229616
7787 19:27:26.229977 ==
7788 19:27:26.232301 Dram Type= 6, Freq= 0, CH_0, rank 1
7789 19:27:26.235612 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7790 19:27:26.236073 ==
7791 19:27:26.238993 [Gating] SW mode calibration
7792 19:27:26.245823 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7793 19:27:26.251903 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7794 19:27:26.255606 0 12 0 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
7795 19:27:26.262326 0 12 4 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
7796 19:27:26.265094 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7797 19:27:26.268379 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7798 19:27:26.275247 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7799 19:27:26.278345 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7800 19:27:26.282109 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7801 19:27:26.288668 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7802 19:27:26.291695 0 13 0 | B1->B0 | 3434 2e2e | 1 0 | (1 0) (0 1)
7803 19:27:26.295144 0 13 4 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (0 0)
7804 19:27:26.302311 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7805 19:27:26.305147 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7806 19:27:26.308411 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7807 19:27:26.315281 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7808 19:27:26.318239 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7809 19:27:26.321507 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7810 19:27:26.328138 0 14 0 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
7811 19:27:26.331524 0 14 4 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
7812 19:27:26.334682 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7813 19:27:26.341422 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7814 19:27:26.344443 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7815 19:27:26.347911 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7816 19:27:26.354620 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7817 19:27:26.357375 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7818 19:27:26.361084 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7819 19:27:26.367563 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7820 19:27:26.370755 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7821 19:27:26.374011 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7822 19:27:26.380823 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7823 19:27:26.384244 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7824 19:27:26.387119 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7825 19:27:26.394259 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7826 19:27:26.397564 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7827 19:27:26.400667 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7828 19:27:26.406899 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7829 19:27:26.410633 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7830 19:27:26.413617 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7831 19:27:26.420258 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7832 19:27:26.424218 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7833 19:27:26.427116 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7834 19:27:26.430772 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7835 19:27:26.433949 Total UI for P1: 0, mck2ui 16
7836 19:27:26.436733 best dqsien dly found for B0: ( 1, 0, 26)
7837 19:27:26.443763 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7838 19:27:26.446931 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7839 19:27:26.450296 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7840 19:27:26.453419 Total UI for P1: 0, mck2ui 16
7841 19:27:26.457173 best dqsien dly found for B1: ( 1, 1, 4)
7842 19:27:26.459832 best DQS0 dly(MCK, UI, PI) = (1, 0, 26)
7843 19:27:26.463579 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
7844 19:27:26.466732
7845 19:27:26.470503 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 26)
7846 19:27:26.473361 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
7847 19:27:26.477064 [Gating] SW calibration Done
7848 19:27:26.477627 ==
7849 19:27:26.479818 Dram Type= 6, Freq= 0, CH_0, rank 1
7850 19:27:26.483952 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7851 19:27:26.484543 ==
7852 19:27:26.484939 RX Vref Scan: 0
7853 19:27:26.485276
7854 19:27:26.486549 RX Vref 0 -> 0, step: 1
7855 19:27:26.487008
7856 19:27:26.490097 RX Delay 0 -> 252, step: 8
7857 19:27:26.493673 iDelay=200, Bit 0, Center 127 (64 ~ 191) 128
7858 19:27:26.496533 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7859 19:27:26.502984 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7860 19:27:26.506224 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7861 19:27:26.509906 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7862 19:27:26.513137 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7863 19:27:26.516721 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7864 19:27:26.523060 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7865 19:27:26.526288 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7866 19:27:26.529681 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7867 19:27:26.533211 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7868 19:27:26.535983 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7869 19:27:26.543298 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7870 19:27:26.546644 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7871 19:27:26.549332 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7872 19:27:26.553029 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7873 19:27:26.553589 ==
7874 19:27:26.556124 Dram Type= 6, Freq= 0, CH_0, rank 1
7875 19:27:26.562403 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7876 19:27:26.562899 ==
7877 19:27:26.563448 DQS Delay:
7878 19:27:26.565757 DQS0 = 0, DQS1 = 0
7879 19:27:26.566247 DQM Delay:
7880 19:27:26.566606 DQM0 = 130, DQM1 = 124
7881 19:27:26.569502 DQ Delay:
7882 19:27:26.572927 DQ0 =127, DQ1 =131, DQ2 =131, DQ3 =127
7883 19:27:26.576252 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
7884 19:27:26.579528 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =119
7885 19:27:26.582995 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
7886 19:27:26.583560
7887 19:27:26.583917
7888 19:27:26.584246 ==
7889 19:27:26.586453 Dram Type= 6, Freq= 0, CH_0, rank 1
7890 19:27:26.589489 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7891 19:27:26.593001 ==
7892 19:27:26.593563
7893 19:27:26.593925
7894 19:27:26.594301 TX Vref Scan disable
7895 19:27:26.596168 == TX Byte 0 ==
7896 19:27:26.599290 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7897 19:27:26.602697 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7898 19:27:26.605609 == TX Byte 1 ==
7899 19:27:26.608984 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7900 19:27:26.612601 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7901 19:27:26.616092 ==
7902 19:27:26.619022 Dram Type= 6, Freq= 0, CH_0, rank 1
7903 19:27:26.622575 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7904 19:27:26.623037 ==
7905 19:27:26.635865
7906 19:27:26.639004 TX Vref early break, caculate TX vref
7907 19:27:26.642190 TX Vref=16, minBit 1, minWin=22, winSum=376
7908 19:27:26.645602 TX Vref=18, minBit 1, minWin=22, winSum=388
7909 19:27:26.648530 TX Vref=20, minBit 1, minWin=24, winSum=398
7910 19:27:26.652103 TX Vref=22, minBit 9, minWin=24, winSum=403
7911 19:27:26.655702 TX Vref=24, minBit 8, minWin=24, winSum=409
7912 19:27:26.662257 TX Vref=26, minBit 1, minWin=25, winSum=419
7913 19:27:26.665214 TX Vref=28, minBit 1, minWin=25, winSum=417
7914 19:27:26.668179 TX Vref=30, minBit 0, minWin=25, winSum=414
7915 19:27:26.672033 TX Vref=32, minBit 8, minWin=24, winSum=408
7916 19:27:26.675034 TX Vref=34, minBit 0, minWin=24, winSum=398
7917 19:27:26.678622 TX Vref=36, minBit 1, minWin=23, winSum=388
7918 19:27:26.685074 [TxChooseVref] Worse bit 1, Min win 25, Win sum 419, Final Vref 26
7919 19:27:26.685639
7920 19:27:26.688388 Final TX Range 0 Vref 26
7921 19:27:26.688950
7922 19:27:26.689314 ==
7923 19:27:26.691672 Dram Type= 6, Freq= 0, CH_0, rank 1
7924 19:27:26.695191 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7925 19:27:26.695758 ==
7926 19:27:26.698318
7927 19:27:26.698774
7928 19:27:26.699137 TX Vref Scan disable
7929 19:27:26.705203 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7930 19:27:26.705845 == TX Byte 0 ==
7931 19:27:26.708139 u2DelayCellOfst[0]=10 cells (3 PI)
7932 19:27:26.711644 u2DelayCellOfst[1]=14 cells (4 PI)
7933 19:27:26.715128 u2DelayCellOfst[2]=10 cells (3 PI)
7934 19:27:26.718131 u2DelayCellOfst[3]=10 cells (3 PI)
7935 19:27:26.721527 u2DelayCellOfst[4]=3 cells (1 PI)
7936 19:27:26.724638 u2DelayCellOfst[5]=0 cells (0 PI)
7937 19:27:26.728218 u2DelayCellOfst[6]=14 cells (4 PI)
7938 19:27:26.731272 u2DelayCellOfst[7]=14 cells (4 PI)
7939 19:27:26.734606 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7940 19:27:26.738495 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7941 19:27:26.741620 == TX Byte 1 ==
7942 19:27:26.744572 u2DelayCellOfst[8]=3 cells (1 PI)
7943 19:27:26.747740 u2DelayCellOfst[9]=0 cells (0 PI)
7944 19:27:26.751040 u2DelayCellOfst[10]=10 cells (3 PI)
7945 19:27:26.754500 u2DelayCellOfst[11]=7 cells (2 PI)
7946 19:27:26.757734 u2DelayCellOfst[12]=14 cells (4 PI)
7947 19:27:26.761065 u2DelayCellOfst[13]=14 cells (4 PI)
7948 19:27:26.761527 u2DelayCellOfst[14]=18 cells (5 PI)
7949 19:27:26.763914 u2DelayCellOfst[15]=18 cells (5 PI)
7950 19:27:26.770660 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7951 19:27:26.773999 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7952 19:27:26.777395 DramC Write-DBI on
7953 19:27:26.777958 ==
7954 19:27:26.780383 Dram Type= 6, Freq= 0, CH_0, rank 1
7955 19:27:26.783913 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7956 19:27:26.784483 ==
7957 19:27:26.784851
7958 19:27:26.785187
7959 19:27:26.787890 TX Vref Scan disable
7960 19:27:26.788453 == TX Byte 0 ==
7961 19:27:26.794073 Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3)
7962 19:27:26.794641 == TX Byte 1 ==
7963 19:27:26.796926 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7964 19:27:26.800964 DramC Write-DBI off
7965 19:27:26.801527
7966 19:27:26.801892 [DATLAT]
7967 19:27:26.804109 Freq=1600, CH0 RK1
7968 19:27:26.804703
7969 19:27:26.805116 DATLAT Default: 0xe
7970 19:27:26.806790 0, 0xFFFF, sum = 0
7971 19:27:26.807259 1, 0xFFFF, sum = 0
7972 19:27:26.810627 2, 0xFFFF, sum = 0
7973 19:27:26.813839 3, 0xFFFF, sum = 0
7974 19:27:26.814357 4, 0xFFFF, sum = 0
7975 19:27:26.817087 5, 0xFFFF, sum = 0
7976 19:27:26.817564 6, 0xFFFF, sum = 0
7977 19:27:26.820163 7, 0xFFFF, sum = 0
7978 19:27:26.820629 8, 0xFFFF, sum = 0
7979 19:27:26.823875 9, 0xFFFF, sum = 0
7980 19:27:26.824443 10, 0xFFFF, sum = 0
7981 19:27:26.827030 11, 0xFFFF, sum = 0
7982 19:27:26.827499 12, 0x8FFF, sum = 0
7983 19:27:26.829985 13, 0x0, sum = 1
7984 19:27:26.830488 14, 0x0, sum = 2
7985 19:27:26.833524 15, 0x0, sum = 3
7986 19:27:26.834144 16, 0x0, sum = 4
7987 19:27:26.837097 best_step = 14
7988 19:27:26.837709
7989 19:27:26.838126 ==
7990 19:27:26.840670 Dram Type= 6, Freq= 0, CH_0, rank 1
7991 19:27:26.843456 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7992 19:27:26.843925 ==
7993 19:27:26.844288 RX Vref Scan: 0
7994 19:27:26.847213
7995 19:27:26.847777 RX Vref 0 -> 0, step: 1
7996 19:27:26.848143
7997 19:27:26.850490 RX Delay 11 -> 252, step: 4
7998 19:27:26.853475 iDelay=195, Bit 0, Center 124 (71 ~ 178) 108
7999 19:27:26.860431 iDelay=195, Bit 1, Center 132 (79 ~ 186) 108
8000 19:27:26.863539 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
8001 19:27:26.866611 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8002 19:27:26.870241 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
8003 19:27:26.873529 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8004 19:27:26.880011 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8005 19:27:26.883278 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
8006 19:27:26.886524 iDelay=195, Bit 8, Center 108 (55 ~ 162) 108
8007 19:27:26.889862 iDelay=195, Bit 9, Center 108 (55 ~ 162) 108
8008 19:27:26.892857 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
8009 19:27:26.899415 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
8010 19:27:26.902907 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
8011 19:27:26.906335 iDelay=195, Bit 13, Center 128 (75 ~ 182) 108
8012 19:27:26.909721 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
8013 19:27:26.916123 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
8014 19:27:26.916693 ==
8015 19:27:26.919092 Dram Type= 6, Freq= 0, CH_0, rank 1
8016 19:27:26.922331 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8017 19:27:26.922812 ==
8018 19:27:26.923300 DQS Delay:
8019 19:27:26.926055 DQS0 = 0, DQS1 = 0
8020 19:27:26.926630 DQM Delay:
8021 19:27:26.929197 DQM0 = 129, DQM1 = 120
8022 19:27:26.929671 DQ Delay:
8023 19:27:26.933038 DQ0 =124, DQ1 =132, DQ2 =126, DQ3 =124
8024 19:27:26.936530 DQ4 =132, DQ5 =120, DQ6 =136, DQ7 =138
8025 19:27:26.939850 DQ8 =108, DQ9 =108, DQ10 =122, DQ11 =112
8026 19:27:26.942362 DQ12 =126, DQ13 =128, DQ14 =130, DQ15 =130
8027 19:27:26.942837
8028 19:27:26.946185
8029 19:27:26.946755
8030 19:27:26.947236 [DramC_TX_OE_Calibration] TA2
8031 19:27:26.949159 Original DQ_B0 (3 6) =30, OEN = 27
8032 19:27:26.952836 Original DQ_B1 (3 6) =30, OEN = 27
8033 19:27:26.955873 24, 0x0, End_B0=24 End_B1=24
8034 19:27:26.959169 25, 0x0, End_B0=25 End_B1=25
8035 19:27:26.962575 26, 0x0, End_B0=26 End_B1=26
8036 19:27:26.963065 27, 0x0, End_B0=27 End_B1=27
8037 19:27:26.966087 28, 0x0, End_B0=28 End_B1=28
8038 19:27:26.968898 29, 0x0, End_B0=29 End_B1=29
8039 19:27:26.972324 30, 0x0, End_B0=30 End_B1=30
8040 19:27:26.975447 31, 0x4141, End_B0=30 End_B1=30
8041 19:27:26.975952 Byte0 end_step=30 best_step=27
8042 19:27:26.978738 Byte1 end_step=30 best_step=27
8043 19:27:26.982244 Byte0 TX OE(2T, 0.5T) = (3, 3)
8044 19:27:26.985745 Byte1 TX OE(2T, 0.5T) = (3, 3)
8045 19:27:26.986356
8046 19:27:26.986725
8047 19:27:26.995340 [DQSOSCAuto] RK1, (LSB)MR18= 0x2121, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
8048 19:27:26.995901 CH0 RK1: MR19=303, MR18=2121
8049 19:27:27.001940 CH0_RK1: MR19=0x303, MR18=0x2121, DQSOSC=393, MR23=63, INC=23, DEC=15
8050 19:27:27.005096 [RxdqsGatingPostProcess] freq 1600
8051 19:27:27.012056 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8052 19:27:27.014860 Pre-setting of DQS Precalculation
8053 19:27:27.018161 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8054 19:27:27.018724 ==
8055 19:27:27.021945 Dram Type= 6, Freq= 0, CH_1, rank 0
8056 19:27:27.028259 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8057 19:27:27.028818 ==
8058 19:27:27.031345 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8059 19:27:27.038361 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8060 19:27:27.041293 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8061 19:27:27.047830 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8062 19:27:27.054995 [CA 0] Center 41 (11~71) winsize 61
8063 19:27:27.058293 [CA 1] Center 40 (10~71) winsize 62
8064 19:27:27.061129 [CA 2] Center 36 (7~66) winsize 60
8065 19:27:27.064544 [CA 3] Center 35 (6~65) winsize 60
8066 19:27:27.068025 [CA 4] Center 33 (4~63) winsize 60
8067 19:27:27.071402 [CA 5] Center 33 (4~63) winsize 60
8068 19:27:27.071863
8069 19:27:27.074579 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8070 19:27:27.075041
8071 19:27:27.081143 [CATrainingPosCal] consider 1 rank data
8072 19:27:27.081609 u2DelayCellTimex100 = 271/100 ps
8073 19:27:27.087728 CA0 delay=41 (11~71),Diff = 8 PI (28 cell)
8074 19:27:27.090744 CA1 delay=40 (10~71),Diff = 7 PI (25 cell)
8075 19:27:27.093948 CA2 delay=36 (7~66),Diff = 3 PI (10 cell)
8076 19:27:27.097473 CA3 delay=35 (6~65),Diff = 2 PI (7 cell)
8077 19:27:27.100713 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
8078 19:27:27.103955 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8079 19:27:27.104524
8080 19:27:27.107689 CA PerBit enable=1, Macro0, CA PI delay=33
8081 19:27:27.108314
8082 19:27:27.111093 [CBTSetCACLKResult] CA Dly = 33
8083 19:27:27.113796 CS Dly: 9 (0~40)
8084 19:27:27.117507 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8085 19:27:27.120930 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8086 19:27:27.121406 ==
8087 19:27:27.124435 Dram Type= 6, Freq= 0, CH_1, rank 1
8088 19:27:27.130138 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8089 19:27:27.130814 ==
8090 19:27:27.133409 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8091 19:27:27.140831 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8092 19:27:27.144017 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8093 19:27:27.150316 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8094 19:27:27.157145 [CA 0] Center 40 (10~70) winsize 61
8095 19:27:27.160420 [CA 1] Center 40 (10~70) winsize 61
8096 19:27:27.163480 [CA 2] Center 35 (6~65) winsize 60
8097 19:27:27.166919 [CA 3] Center 35 (6~65) winsize 60
8098 19:27:27.170138 [CA 4] Center 33 (4~62) winsize 59
8099 19:27:27.173546 [CA 5] Center 33 (4~63) winsize 60
8100 19:27:27.173968
8101 19:27:27.176931 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8102 19:27:27.177350
8103 19:27:27.183532 [CATrainingPosCal] consider 2 rank data
8104 19:27:27.184252 u2DelayCellTimex100 = 271/100 ps
8105 19:27:27.189830 CA0 delay=40 (11~70),Diff = 7 PI (25 cell)
8106 19:27:27.193259 CA1 delay=40 (10~70),Diff = 7 PI (25 cell)
8107 19:27:27.196999 CA2 delay=36 (7~65),Diff = 3 PI (10 cell)
8108 19:27:27.200224 CA3 delay=35 (6~65),Diff = 2 PI (7 cell)
8109 19:27:27.203206 CA4 delay=33 (4~62),Diff = 0 PI (0 cell)
8110 19:27:27.206445 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8111 19:27:27.206865
8112 19:27:27.209513 CA PerBit enable=1, Macro0, CA PI delay=33
8113 19:27:27.209933
8114 19:27:27.213027 [CBTSetCACLKResult] CA Dly = 33
8115 19:27:27.216540 CS Dly: 9 (0~41)
8116 19:27:27.219889 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8117 19:27:27.223170 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8118 19:27:27.223590
8119 19:27:27.226599 ----->DramcWriteLeveling(PI) begin...
8120 19:27:27.227023 ==
8121 19:27:27.229625 Dram Type= 6, Freq= 0, CH_1, rank 0
8122 19:27:27.236478 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8123 19:27:27.237003 ==
8124 19:27:27.239895 Write leveling (Byte 0): 22 => 22
8125 19:27:27.243126 Write leveling (Byte 1): 21 => 21
8126 19:27:27.243546 DramcWriteLeveling(PI) end<-----
8127 19:27:27.246464
8128 19:27:27.246984 ==
8129 19:27:27.249419 Dram Type= 6, Freq= 0, CH_1, rank 0
8130 19:27:27.253025 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8131 19:27:27.253448 ==
8132 19:27:27.255973 [Gating] SW mode calibration
8133 19:27:27.262776 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8134 19:27:27.266195 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8135 19:27:27.272613 0 12 0 | B1->B0 | 2727 3434 | 0 1 | (1 1) (1 1)
8136 19:27:27.276051 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8137 19:27:27.279441 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8138 19:27:27.286181 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8139 19:27:27.289079 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8140 19:27:27.292844 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8141 19:27:27.299266 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8142 19:27:27.303011 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
8143 19:27:27.305817 0 13 0 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
8144 19:27:27.312335 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8145 19:27:27.315611 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8146 19:27:27.319433 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8147 19:27:27.325851 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8148 19:27:27.328725 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8149 19:27:27.331928 0 13 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8150 19:27:27.338719 0 13 28 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
8151 19:27:27.341806 0 14 0 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
8152 19:27:27.345385 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8153 19:27:27.351495 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8154 19:27:27.354637 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8155 19:27:27.358097 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8156 19:27:27.365294 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8157 19:27:27.368253 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8158 19:27:27.371505 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8159 19:27:27.377970 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8160 19:27:27.381564 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8161 19:27:27.385025 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8162 19:27:27.391704 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8163 19:27:27.394761 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8164 19:27:27.398125 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8165 19:27:27.404950 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8166 19:27:27.407722 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8167 19:27:27.411036 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8168 19:27:27.418179 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8169 19:27:27.421410 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8170 19:27:27.424814 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8171 19:27:27.431285 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8172 19:27:27.434091 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8173 19:27:27.437378 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8174 19:27:27.444236 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8175 19:27:27.447300 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8176 19:27:27.450877 Total UI for P1: 0, mck2ui 16
8177 19:27:27.454142 best dqsien dly found for B0: ( 1, 0, 26)
8178 19:27:27.457772 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8179 19:27:27.464025 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8180 19:27:27.464573 Total UI for P1: 0, mck2ui 16
8181 19:27:27.470330 best dqsien dly found for B1: ( 1, 1, 4)
8182 19:27:27.473543 best DQS0 dly(MCK, UI, PI) = (1, 0, 26)
8183 19:27:27.476941 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
8184 19:27:27.477401
8185 19:27:27.480246 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 26)
8186 19:27:27.483852 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
8187 19:27:27.487233 [Gating] SW calibration Done
8188 19:27:27.487797 ==
8189 19:27:27.490382 Dram Type= 6, Freq= 0, CH_1, rank 0
8190 19:27:27.494097 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8191 19:27:27.494652 ==
8192 19:27:27.497050 RX Vref Scan: 0
8193 19:27:27.497511
8194 19:27:27.497870 RX Vref 0 -> 0, step: 1
8195 19:27:27.498244
8196 19:27:27.500193 RX Delay 0 -> 252, step: 8
8197 19:27:27.503972 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8198 19:27:27.510365 iDelay=200, Bit 1, Center 123 (72 ~ 175) 104
8199 19:27:27.513660 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8200 19:27:27.517074 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8201 19:27:27.519970 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8202 19:27:27.523470 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8203 19:27:27.530175 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8204 19:27:27.533503 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8205 19:27:27.536995 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8206 19:27:27.540171 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8207 19:27:27.543463 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8208 19:27:27.549840 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8209 19:27:27.553597 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8210 19:27:27.556501 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8211 19:27:27.559689 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8212 19:27:27.566283 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8213 19:27:27.566907 ==
8214 19:27:27.569586 Dram Type= 6, Freq= 0, CH_1, rank 0
8215 19:27:27.572615 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8216 19:27:27.573174 ==
8217 19:27:27.573539 DQS Delay:
8218 19:27:27.576287 DQS0 = 0, DQS1 = 0
8219 19:27:27.576750 DQM Delay:
8220 19:27:27.579231 DQM0 = 130, DQM1 = 125
8221 19:27:27.579689 DQ Delay:
8222 19:27:27.582516 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =127
8223 19:27:27.586481 DQ4 =131, DQ5 =143, DQ6 =135, DQ7 =127
8224 19:27:27.589524 DQ8 =107, DQ9 =115, DQ10 =123, DQ11 =115
8225 19:27:27.592987 DQ12 =131, DQ13 =139, DQ14 =135, DQ15 =135
8226 19:27:27.593556
8227 19:27:27.596471
8228 19:27:27.597041 ==
8229 19:27:27.599445 Dram Type= 6, Freq= 0, CH_1, rank 0
8230 19:27:27.602383 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8231 19:27:27.602863 ==
8232 19:27:27.603258
8233 19:27:27.603599
8234 19:27:27.605981 TX Vref Scan disable
8235 19:27:27.606626 == TX Byte 0 ==
8236 19:27:27.612259 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8237 19:27:27.615564 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8238 19:27:27.616046 == TX Byte 1 ==
8239 19:27:27.622673 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8240 19:27:27.625780 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8241 19:27:27.626409 ==
8242 19:27:27.629254 Dram Type= 6, Freq= 0, CH_1, rank 0
8243 19:27:27.632401 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8244 19:27:27.632868 ==
8245 19:27:27.645712
8246 19:27:27.648652 TX Vref early break, caculate TX vref
8247 19:27:27.651534 TX Vref=16, minBit 3, minWin=21, winSum=369
8248 19:27:27.655156 TX Vref=18, minBit 3, minWin=22, winSum=376
8249 19:27:27.658247 TX Vref=20, minBit 3, minWin=22, winSum=381
8250 19:27:27.662020 TX Vref=22, minBit 3, minWin=22, winSum=392
8251 19:27:27.664812 TX Vref=24, minBit 3, minWin=23, winSum=399
8252 19:27:27.671637 TX Vref=26, minBit 3, minWin=24, winSum=414
8253 19:27:27.674802 TX Vref=28, minBit 3, minWin=24, winSum=416
8254 19:27:27.678156 TX Vref=30, minBit 3, minWin=24, winSum=407
8255 19:27:27.681801 TX Vref=32, minBit 1, minWin=24, winSum=400
8256 19:27:27.685241 TX Vref=34, minBit 1, minWin=23, winSum=392
8257 19:27:27.692051 [TxChooseVref] Worse bit 3, Min win 24, Win sum 416, Final Vref 28
8258 19:27:27.692622
8259 19:27:27.694956 Final TX Range 0 Vref 28
8260 19:27:27.695418
8261 19:27:27.695773 ==
8262 19:27:27.698393 Dram Type= 6, Freq= 0, CH_1, rank 0
8263 19:27:27.701558 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8264 19:27:27.702196 ==
8265 19:27:27.702578
8266 19:27:27.702913
8267 19:27:27.705003 TX Vref Scan disable
8268 19:27:27.711220 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8269 19:27:27.711684 == TX Byte 0 ==
8270 19:27:27.714942 u2DelayCellOfst[0]=18 cells (5 PI)
8271 19:27:27.717860 u2DelayCellOfst[1]=14 cells (4 PI)
8272 19:27:27.721303 u2DelayCellOfst[2]=0 cells (0 PI)
8273 19:27:27.724604 u2DelayCellOfst[3]=10 cells (3 PI)
8274 19:27:27.727537 u2DelayCellOfst[4]=10 cells (3 PI)
8275 19:27:27.731273 u2DelayCellOfst[5]=18 cells (5 PI)
8276 19:27:27.734591 u2DelayCellOfst[6]=18 cells (5 PI)
8277 19:27:27.738258 u2DelayCellOfst[7]=7 cells (2 PI)
8278 19:27:27.740791 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8279 19:27:27.744100 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8280 19:27:27.747582 == TX Byte 1 ==
8281 19:27:27.751020 u2DelayCellOfst[8]=0 cells (0 PI)
8282 19:27:27.751620 u2DelayCellOfst[9]=7 cells (2 PI)
8283 19:27:27.754007 u2DelayCellOfst[10]=10 cells (3 PI)
8284 19:27:27.757526 u2DelayCellOfst[11]=3 cells (1 PI)
8285 19:27:27.761015 u2DelayCellOfst[12]=18 cells (5 PI)
8286 19:27:27.764718 u2DelayCellOfst[13]=21 cells (6 PI)
8287 19:27:27.767233 u2DelayCellOfst[14]=18 cells (5 PI)
8288 19:27:27.770743 u2DelayCellOfst[15]=18 cells (5 PI)
8289 19:27:27.777227 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8290 19:27:27.780986 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8291 19:27:27.781554 DramC Write-DBI on
8292 19:27:27.781922 ==
8293 19:27:27.783992 Dram Type= 6, Freq= 0, CH_1, rank 0
8294 19:27:27.790806 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8295 19:27:27.791373 ==
8296 19:27:27.791739
8297 19:27:27.792074
8298 19:27:27.792452 TX Vref Scan disable
8299 19:27:27.794493 == TX Byte 0 ==
8300 19:27:27.797870 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
8301 19:27:27.800955 == TX Byte 1 ==
8302 19:27:27.805005 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8303 19:27:27.807819 DramC Write-DBI off
8304 19:27:27.808383
8305 19:27:27.808745 [DATLAT]
8306 19:27:27.809114 Freq=1600, CH1 RK0
8307 19:27:27.809645
8308 19:27:27.810951 DATLAT Default: 0xf
8309 19:27:27.813960 0, 0xFFFF, sum = 0
8310 19:27:27.814484 1, 0xFFFF, sum = 0
8311 19:27:27.817360 2, 0xFFFF, sum = 0
8312 19:27:27.817825 3, 0xFFFF, sum = 0
8313 19:27:27.820951 4, 0xFFFF, sum = 0
8314 19:27:27.821709 5, 0xFFFF, sum = 0
8315 19:27:27.824206 6, 0xFFFF, sum = 0
8316 19:27:27.824803 7, 0xFFFF, sum = 0
8317 19:27:27.827359 8, 0xFFFF, sum = 0
8318 19:27:27.827825 9, 0xFFFF, sum = 0
8319 19:27:27.830950 10, 0xFFFF, sum = 0
8320 19:27:27.831420 11, 0xFFFF, sum = 0
8321 19:27:27.834426 12, 0xFFF, sum = 0
8322 19:27:27.834892 13, 0x0, sum = 1
8323 19:27:27.837389 14, 0x0, sum = 2
8324 19:27:27.837861 15, 0x0, sum = 3
8325 19:27:27.840995 16, 0x0, sum = 4
8326 19:27:27.841566 best_step = 14
8327 19:27:27.841931
8328 19:27:27.842356 ==
8329 19:27:27.844121 Dram Type= 6, Freq= 0, CH_1, rank 0
8330 19:27:27.847790 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8331 19:27:27.851148 ==
8332 19:27:27.851609 RX Vref Scan: 1
8333 19:27:27.851968
8334 19:27:27.853803 Set Vref Range= 24 -> 127
8335 19:27:27.854292
8336 19:27:27.857246 RX Vref 24 -> 127, step: 1
8337 19:27:27.857704
8338 19:27:27.858093 RX Delay 3 -> 252, step: 4
8339 19:27:27.858435
8340 19:27:27.860716 Set Vref, RX VrefLevel [Byte0]: 24
8341 19:27:27.863891 [Byte1]: 24
8342 19:27:27.867750
8343 19:27:27.868211 Set Vref, RX VrefLevel [Byte0]: 25
8344 19:27:27.870864 [Byte1]: 25
8345 19:27:27.875348
8346 19:27:27.875806 Set Vref, RX VrefLevel [Byte0]: 26
8347 19:27:27.878805 [Byte1]: 26
8348 19:27:27.883266
8349 19:27:27.883724 Set Vref, RX VrefLevel [Byte0]: 27
8350 19:27:27.886589 [Byte1]: 27
8351 19:27:27.890484
8352 19:27:27.890947 Set Vref, RX VrefLevel [Byte0]: 28
8353 19:27:27.893904 [Byte1]: 28
8354 19:27:27.898102
8355 19:27:27.898565 Set Vref, RX VrefLevel [Byte0]: 29
8356 19:27:27.901394 [Byte1]: 29
8357 19:27:27.905645
8358 19:27:27.905952 Set Vref, RX VrefLevel [Byte0]: 30
8359 19:27:27.908743 [Byte1]: 30
8360 19:27:27.913268
8361 19:27:27.913462 Set Vref, RX VrefLevel [Byte0]: 31
8362 19:27:27.916442 [Byte1]: 31
8363 19:27:27.920970
8364 19:27:27.921113 Set Vref, RX VrefLevel [Byte0]: 32
8365 19:27:27.924425 [Byte1]: 32
8366 19:27:27.928433
8367 19:27:27.928549 Set Vref, RX VrefLevel [Byte0]: 33
8368 19:27:27.932196 [Byte1]: 33
8369 19:27:27.936298
8370 19:27:27.936469 Set Vref, RX VrefLevel [Byte0]: 34
8371 19:27:27.939983 [Byte1]: 34
8372 19:27:27.944130
8373 19:27:27.944222 Set Vref, RX VrefLevel [Byte0]: 35
8374 19:27:27.947324 [Byte1]: 35
8375 19:27:27.951561
8376 19:27:27.951732 Set Vref, RX VrefLevel [Byte0]: 36
8377 19:27:27.955584 [Byte1]: 36
8378 19:27:27.959315
8379 19:27:27.959488 Set Vref, RX VrefLevel [Byte0]: 37
8380 19:27:27.962663 [Byte1]: 37
8381 19:27:27.967033
8382 19:27:27.967214 Set Vref, RX VrefLevel [Byte0]: 38
8383 19:27:27.970171 [Byte1]: 38
8384 19:27:27.974543
8385 19:27:27.974731 Set Vref, RX VrefLevel [Byte0]: 39
8386 19:27:27.977961 [Byte1]: 39
8387 19:27:27.982801
8388 19:27:27.983253 Set Vref, RX VrefLevel [Byte0]: 40
8389 19:27:27.985690 [Byte1]: 40
8390 19:27:27.990401
8391 19:27:27.990864 Set Vref, RX VrefLevel [Byte0]: 41
8392 19:27:27.993373 [Byte1]: 41
8393 19:27:27.997675
8394 19:27:27.998169 Set Vref, RX VrefLevel [Byte0]: 42
8395 19:27:28.001001 [Byte1]: 42
8396 19:27:28.005554
8397 19:27:28.006158 Set Vref, RX VrefLevel [Byte0]: 43
8398 19:27:28.009362 [Byte1]: 43
8399 19:27:28.013372
8400 19:27:28.014054 Set Vref, RX VrefLevel [Byte0]: 44
8401 19:27:28.016459 [Byte1]: 44
8402 19:27:28.020597
8403 19:27:28.021052 Set Vref, RX VrefLevel [Byte0]: 45
8404 19:27:28.024391 [Byte1]: 45
8405 19:27:28.028917
8406 19:27:28.029479 Set Vref, RX VrefLevel [Byte0]: 46
8407 19:27:28.031403 [Byte1]: 46
8408 19:27:28.036120
8409 19:27:28.036675 Set Vref, RX VrefLevel [Byte0]: 47
8410 19:27:28.039609 [Byte1]: 47
8411 19:27:28.044086
8412 19:27:28.044689 Set Vref, RX VrefLevel [Byte0]: 48
8413 19:27:28.046788 [Byte1]: 48
8414 19:27:28.051828
8415 19:27:28.052388 Set Vref, RX VrefLevel [Byte0]: 49
8416 19:27:28.054833 [Byte1]: 49
8417 19:27:28.058983
8418 19:27:28.059542 Set Vref, RX VrefLevel [Byte0]: 50
8419 19:27:28.062294 [Byte1]: 50
8420 19:27:28.066970
8421 19:27:28.067529 Set Vref, RX VrefLevel [Byte0]: 51
8422 19:27:28.069787 [Byte1]: 51
8423 19:27:28.074289
8424 19:27:28.074747 Set Vref, RX VrefLevel [Byte0]: 52
8425 19:27:28.077770 [Byte1]: 52
8426 19:27:28.082130
8427 19:27:28.082692 Set Vref, RX VrefLevel [Byte0]: 53
8428 19:27:28.085484 [Byte1]: 53
8429 19:27:28.089580
8430 19:27:28.090321 Set Vref, RX VrefLevel [Byte0]: 54
8431 19:27:28.092963 [Byte1]: 54
8432 19:27:28.097203
8433 19:27:28.097745 Set Vref, RX VrefLevel [Byte0]: 55
8434 19:27:28.100770 [Byte1]: 55
8435 19:27:28.104914
8436 19:27:28.105379 Set Vref, RX VrefLevel [Byte0]: 56
8437 19:27:28.108279 [Byte1]: 56
8438 19:27:28.112408
8439 19:27:28.113066 Set Vref, RX VrefLevel [Byte0]: 57
8440 19:27:28.115646 [Byte1]: 57
8441 19:27:28.120336
8442 19:27:28.120796 Set Vref, RX VrefLevel [Byte0]: 58
8443 19:27:28.123538 [Byte1]: 58
8444 19:27:28.128045
8445 19:27:28.128551 Set Vref, RX VrefLevel [Byte0]: 59
8446 19:27:28.130921 [Byte1]: 59
8447 19:27:28.135207
8448 19:27:28.135531 Set Vref, RX VrefLevel [Byte0]: 60
8449 19:27:28.138819 [Byte1]: 60
8450 19:27:28.143066
8451 19:27:28.143323 Set Vref, RX VrefLevel [Byte0]: 61
8452 19:27:28.146182 [Byte1]: 61
8453 19:27:28.150422
8454 19:27:28.150661 Set Vref, RX VrefLevel [Byte0]: 62
8455 19:27:28.154019 [Byte1]: 62
8456 19:27:28.158033
8457 19:27:28.158270 Set Vref, RX VrefLevel [Byte0]: 63
8458 19:27:28.161622 [Byte1]: 63
8459 19:27:28.166011
8460 19:27:28.166245 Set Vref, RX VrefLevel [Byte0]: 64
8461 19:27:28.169460 [Byte1]: 64
8462 19:27:28.173605
8463 19:27:28.173836 Set Vref, RX VrefLevel [Byte0]: 65
8464 19:27:28.176763 [Byte1]: 65
8465 19:27:28.181138
8466 19:27:28.181365 Set Vref, RX VrefLevel [Byte0]: 66
8467 19:27:28.184402 [Byte1]: 66
8468 19:27:28.188725
8469 19:27:28.189010 Set Vref, RX VrefLevel [Byte0]: 67
8470 19:27:28.192178 [Byte1]: 67
8471 19:27:28.196479
8472 19:27:28.196787 Set Vref, RX VrefLevel [Byte0]: 68
8473 19:27:28.199634 [Byte1]: 68
8474 19:27:28.203952
8475 19:27:28.204230 Set Vref, RX VrefLevel [Byte0]: 69
8476 19:27:28.207489 [Byte1]: 69
8477 19:27:28.211651
8478 19:27:28.211922 Set Vref, RX VrefLevel [Byte0]: 70
8479 19:27:28.215122 [Byte1]: 70
8480 19:27:28.219072
8481 19:27:28.219383 Set Vref, RX VrefLevel [Byte0]: 71
8482 19:27:28.222685 [Byte1]: 71
8483 19:27:28.227344
8484 19:27:28.227535 Set Vref, RX VrefLevel [Byte0]: 72
8485 19:27:28.230407 [Byte1]: 72
8486 19:27:28.234447
8487 19:27:28.234635 Set Vref, RX VrefLevel [Byte0]: 73
8488 19:27:28.237994 [Byte1]: 73
8489 19:27:28.242713
8490 19:27:28.243129 Set Vref, RX VrefLevel [Byte0]: 74
8491 19:27:28.245782 [Byte1]: 74
8492 19:27:28.250489
8493 19:27:28.250907 Set Vref, RX VrefLevel [Byte0]: 75
8494 19:27:28.253383 [Byte1]: 75
8495 19:27:28.258071
8496 19:27:28.258542 Set Vref, RX VrefLevel [Byte0]: 76
8497 19:27:28.261518 [Byte1]: 76
8498 19:27:28.265424
8499 19:27:28.265837 Final RX Vref Byte 0 = 62 to rank0
8500 19:27:28.268726 Final RX Vref Byte 1 = 55 to rank0
8501 19:27:28.272350 Final RX Vref Byte 0 = 62 to rank1
8502 19:27:28.275719 Final RX Vref Byte 1 = 55 to rank1==
8503 19:27:28.278792 Dram Type= 6, Freq= 0, CH_1, rank 0
8504 19:27:28.285614 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8505 19:27:28.286069 ==
8506 19:27:28.286408 DQS Delay:
8507 19:27:28.288687 DQS0 = 0, DQS1 = 0
8508 19:27:28.289104 DQM Delay:
8509 19:27:28.289429 DQM0 = 129, DQM1 = 122
8510 19:27:28.292212 DQ Delay:
8511 19:27:28.295337 DQ0 =132, DQ1 =122, DQ2 =116, DQ3 =128
8512 19:27:28.298769 DQ4 =130, DQ5 =140, DQ6 =138, DQ7 =126
8513 19:27:28.301689 DQ8 =104, DQ9 =114, DQ10 =124, DQ11 =112
8514 19:27:28.305006 DQ12 =130, DQ13 =134, DQ14 =132, DQ15 =132
8515 19:27:28.305420
8516 19:27:28.305741
8517 19:27:28.306064
8518 19:27:28.308388 [DramC_TX_OE_Calibration] TA2
8519 19:27:28.311746 Original DQ_B0 (3 6) =30, OEN = 27
8520 19:27:28.315011 Original DQ_B1 (3 6) =30, OEN = 27
8521 19:27:28.318430 24, 0x0, End_B0=24 End_B1=24
8522 19:27:28.318853 25, 0x0, End_B0=25 End_B1=25
8523 19:27:28.321974 26, 0x0, End_B0=26 End_B1=26
8524 19:27:28.325110 27, 0x0, End_B0=27 End_B1=27
8525 19:27:28.328258 28, 0x0, End_B0=28 End_B1=28
8526 19:27:28.331437 29, 0x0, End_B0=29 End_B1=29
8527 19:27:28.331862 30, 0x0, End_B0=30 End_B1=30
8528 19:27:28.334959 31, 0x4141, End_B0=30 End_B1=30
8529 19:27:28.338475 Byte0 end_step=30 best_step=27
8530 19:27:28.341401 Byte1 end_step=30 best_step=27
8531 19:27:28.344946 Byte0 TX OE(2T, 0.5T) = (3, 3)
8532 19:27:28.347979 Byte1 TX OE(2T, 0.5T) = (3, 3)
8533 19:27:28.348276
8534 19:27:28.348536
8535 19:27:28.354524 [DQSOSCAuto] RK0, (LSB)MR18= 0x2424, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
8536 19:27:28.358194 CH1 RK0: MR19=303, MR18=2424
8537 19:27:28.364465 CH1_RK0: MR19=0x303, MR18=0x2424, DQSOSC=391, MR23=63, INC=24, DEC=16
8538 19:27:28.364888
8539 19:27:28.368096 ----->DramcWriteLeveling(PI) begin...
8540 19:27:28.368788 ==
8541 19:27:28.371015 Dram Type= 6, Freq= 0, CH_1, rank 1
8542 19:27:28.374224 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8543 19:27:28.374643 ==
8544 19:27:28.377507 Write leveling (Byte 0): 21 => 21
8545 19:27:28.381488 Write leveling (Byte 1): 19 => 19
8546 19:27:28.384170 DramcWriteLeveling(PI) end<-----
8547 19:27:28.384601
8548 19:27:28.385200 ==
8549 19:27:28.387118 Dram Type= 6, Freq= 0, CH_1, rank 1
8550 19:27:28.394155 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8551 19:27:28.394573 ==
8552 19:27:28.394901 [Gating] SW mode calibration
8553 19:27:28.404218 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8554 19:27:28.407333 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8555 19:27:28.410806 0 12 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8556 19:27:28.417318 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8557 19:27:28.420568 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8558 19:27:28.423698 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8559 19:27:28.430370 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8560 19:27:28.433860 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
8561 19:27:28.436940 0 12 24 | B1->B0 | 3434 2929 | 1 0 | (1 1) (0 1)
8562 19:27:28.443664 0 12 28 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
8563 19:27:28.446986 0 13 0 | B1->B0 | 2a2a 2323 | 0 0 | (0 1) (0 0)
8564 19:27:28.449878 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8565 19:27:28.456593 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8566 19:27:28.460012 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8567 19:27:28.463459 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8568 19:27:28.469721 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8569 19:27:28.472959 0 13 24 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (0 0)
8570 19:27:28.476462 0 13 28 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
8571 19:27:28.482986 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8572 19:27:28.486011 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8573 19:27:28.489912 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8574 19:27:28.496489 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8575 19:27:28.499686 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8576 19:27:28.502885 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8577 19:27:28.509836 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8578 19:27:28.512809 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8579 19:27:28.516114 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8580 19:27:28.522543 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8581 19:27:28.525875 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8582 19:27:28.529506 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8583 19:27:28.535767 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8584 19:27:28.539173 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8585 19:27:28.542173 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8586 19:27:28.548732 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8587 19:27:28.552063 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8588 19:27:28.555758 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8589 19:27:28.561815 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8590 19:27:28.565391 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8591 19:27:28.568985 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8592 19:27:28.575208 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8593 19:27:28.578897 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8594 19:27:28.582178 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8595 19:27:28.585834 Total UI for P1: 0, mck2ui 16
8596 19:27:28.589085 best dqsien dly found for B0: ( 1, 0, 24)
8597 19:27:28.595664 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8598 19:27:28.598918 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8599 19:27:28.602084 Total UI for P1: 0, mck2ui 16
8600 19:27:28.605483 best dqsien dly found for B1: ( 1, 0, 30)
8601 19:27:28.609201 best DQS0 dly(MCK, UI, PI) = (1, 0, 24)
8602 19:27:28.611812 best DQS1 dly(MCK, UI, PI) = (1, 0, 30)
8603 19:27:28.612105
8604 19:27:28.615332 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 24)
8605 19:27:28.618452 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 30)
8606 19:27:28.621970 [Gating] SW calibration Done
8607 19:27:28.622223 ==
8608 19:27:28.624821 Dram Type= 6, Freq= 0, CH_1, rank 1
8609 19:27:28.631524 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8610 19:27:28.631654 ==
8611 19:27:28.631755 RX Vref Scan: 0
8612 19:27:28.631849
8613 19:27:28.635052 RX Vref 0 -> 0, step: 1
8614 19:27:28.635181
8615 19:27:28.638623 RX Delay 0 -> 252, step: 8
8616 19:27:28.641993 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8617 19:27:28.644828 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8618 19:27:28.648128 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8619 19:27:28.651292 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8620 19:27:28.658098 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8621 19:27:28.661367 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8622 19:27:28.664828 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8623 19:27:28.668007 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8624 19:27:28.671451 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8625 19:27:28.678098 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8626 19:27:28.681148 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8627 19:27:28.684775 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8628 19:27:28.688088 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8629 19:27:28.691658 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8630 19:27:28.697967 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8631 19:27:28.701274 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8632 19:27:28.701750 ==
8633 19:27:28.704632 Dram Type= 6, Freq= 0, CH_1, rank 1
8634 19:27:28.707858 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8635 19:27:28.708333 ==
8636 19:27:28.711445 DQS Delay:
8637 19:27:28.711916 DQS0 = 0, DQS1 = 0
8638 19:27:28.714477 DQM Delay:
8639 19:27:28.714947 DQM0 = 130, DQM1 = 124
8640 19:27:28.715610 DQ Delay:
8641 19:27:28.717800 DQ0 =131, DQ1 =127, DQ2 =119, DQ3 =127
8642 19:27:28.721352 DQ4 =127, DQ5 =143, DQ6 =139, DQ7 =127
8643 19:27:28.727584 DQ8 =107, DQ9 =115, DQ10 =123, DQ11 =115
8644 19:27:28.730888 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =131
8645 19:27:28.731359
8646 19:27:28.731823
8647 19:27:28.732402 ==
8648 19:27:28.734129 Dram Type= 6, Freq= 0, CH_1, rank 1
8649 19:27:28.737450 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8650 19:27:28.737881 ==
8651 19:27:28.738334
8652 19:27:28.738740
8653 19:27:28.741043 TX Vref Scan disable
8654 19:27:28.744497 == TX Byte 0 ==
8655 19:27:28.747543 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8656 19:27:28.750967 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8657 19:27:28.753918 == TX Byte 1 ==
8658 19:27:28.757539 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8659 19:27:28.760409 Update DQM dly =973 (3 ,6, 13) DQM OEN =(3 ,3)
8660 19:27:28.760595 ==
8661 19:27:28.763855 Dram Type= 6, Freq= 0, CH_1, rank 1
8662 19:27:28.767267 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8663 19:27:28.770208 ==
8664 19:27:28.783572
8665 19:27:28.787092 TX Vref early break, caculate TX vref
8666 19:27:28.789981 TX Vref=16, minBit 3, minWin=22, winSum=382
8667 19:27:28.793435 TX Vref=18, minBit 7, minWin=22, winSum=387
8668 19:27:28.796515 TX Vref=20, minBit 2, minWin=23, winSum=396
8669 19:27:28.799944 TX Vref=22, minBit 3, minWin=24, winSum=409
8670 19:27:28.803597 TX Vref=24, minBit 3, minWin=24, winSum=412
8671 19:27:28.809872 TX Vref=26, minBit 0, minWin=25, winSum=421
8672 19:27:28.813330 TX Vref=28, minBit 0, minWin=25, winSum=417
8673 19:27:28.816311 TX Vref=30, minBit 0, minWin=25, winSum=418
8674 19:27:28.819540 TX Vref=32, minBit 0, minWin=25, winSum=417
8675 19:27:28.823322 TX Vref=34, minBit 0, minWin=24, winSum=399
8676 19:27:28.829532 TX Vref=36, minBit 0, minWin=23, winSum=399
8677 19:27:28.833097 TX Vref=38, minBit 0, minWin=22, winSum=383
8678 19:27:28.836357 [TxChooseVref] Worse bit 0, Min win 25, Win sum 421, Final Vref 26
8679 19:27:28.839821
8680 19:27:28.840274 Final TX Range 0 Vref 26
8681 19:27:28.840631
8682 19:27:28.840964 ==
8683 19:27:28.843267 Dram Type= 6, Freq= 0, CH_1, rank 1
8684 19:27:28.849650 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8685 19:27:28.850138 ==
8686 19:27:28.850471
8687 19:27:28.850775
8688 19:27:28.851066 TX Vref Scan disable
8689 19:27:28.856992 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8690 19:27:28.857451 == TX Byte 0 ==
8691 19:27:28.860235 u2DelayCellOfst[0]=18 cells (5 PI)
8692 19:27:28.863207 u2DelayCellOfst[1]=10 cells (3 PI)
8693 19:27:28.866452 u2DelayCellOfst[2]=0 cells (0 PI)
8694 19:27:28.869736 u2DelayCellOfst[3]=10 cells (3 PI)
8695 19:27:28.873018 u2DelayCellOfst[4]=10 cells (3 PI)
8696 19:27:28.876340 u2DelayCellOfst[5]=18 cells (5 PI)
8697 19:27:28.879545 u2DelayCellOfst[6]=18 cells (5 PI)
8698 19:27:28.883054 u2DelayCellOfst[7]=7 cells (2 PI)
8699 19:27:28.886167 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8700 19:27:28.889940 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8701 19:27:28.892929 == TX Byte 1 ==
8702 19:27:28.896286 u2DelayCellOfst[8]=0 cells (0 PI)
8703 19:27:28.899696 u2DelayCellOfst[9]=7 cells (2 PI)
8704 19:27:28.902909 u2DelayCellOfst[10]=7 cells (2 PI)
8705 19:27:28.906467 u2DelayCellOfst[11]=3 cells (1 PI)
8706 19:27:28.909227 u2DelayCellOfst[12]=14 cells (4 PI)
8707 19:27:28.909448 u2DelayCellOfst[13]=18 cells (5 PI)
8708 19:27:28.912818 u2DelayCellOfst[14]=14 cells (4 PI)
8709 19:27:28.915920 u2DelayCellOfst[15]=18 cells (5 PI)
8710 19:27:28.922666 Update DQ dly =971 (3 ,6, 11) DQ OEN =(3 ,3)
8711 19:27:28.925905 Update DQM dly =973 (3 ,6, 13) DQM OEN =(3 ,3)
8712 19:27:28.926033 DramC Write-DBI on
8713 19:27:28.929155 ==
8714 19:27:28.932456 Dram Type= 6, Freq= 0, CH_1, rank 1
8715 19:27:28.935875 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8716 19:27:28.935969 ==
8717 19:27:28.936041
8718 19:27:28.936107
8719 19:27:28.938753 TX Vref Scan disable
8720 19:27:28.938843 == TX Byte 0 ==
8721 19:27:28.945884 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8722 19:27:28.946252 == TX Byte 1 ==
8723 19:27:28.949320 Update DQM dly =715 (2 ,6, 11) DQM OEN =(3 ,3)
8724 19:27:28.952282 DramC Write-DBI off
8725 19:27:28.952598
8726 19:27:28.952846 [DATLAT]
8727 19:27:28.955672 Freq=1600, CH1 RK1
8728 19:27:28.956004
8729 19:27:28.956252 DATLAT Default: 0xe
8730 19:27:28.959049 0, 0xFFFF, sum = 0
8731 19:27:28.959373 1, 0xFFFF, sum = 0
8732 19:27:28.962271 2, 0xFFFF, sum = 0
8733 19:27:28.962592 3, 0xFFFF, sum = 0
8734 19:27:28.965697 4, 0xFFFF, sum = 0
8735 19:27:28.966046 5, 0xFFFF, sum = 0
8736 19:27:28.969080 6, 0xFFFF, sum = 0
8737 19:27:28.972747 7, 0xFFFF, sum = 0
8738 19:27:28.973071 8, 0xFFFF, sum = 0
8739 19:27:28.975784 9, 0xFFFF, sum = 0
8740 19:27:28.976199 10, 0xFFFF, sum = 0
8741 19:27:28.979126 11, 0xFFFF, sum = 0
8742 19:27:28.979545 12, 0x8FFF, sum = 0
8743 19:27:28.982886 13, 0x0, sum = 1
8744 19:27:28.983453 14, 0x0, sum = 2
8745 19:27:28.985876 15, 0x0, sum = 3
8746 19:27:28.986358 16, 0x0, sum = 4
8747 19:27:28.986719 best_step = 14
8748 19:27:28.988959
8749 19:27:28.989415 ==
8750 19:27:28.992164 Dram Type= 6, Freq= 0, CH_1, rank 1
8751 19:27:28.995503 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8752 19:27:28.995962 ==
8753 19:27:28.996323 RX Vref Scan: 0
8754 19:27:28.996660
8755 19:27:28.999209 RX Vref 0 -> 0, step: 1
8756 19:27:28.999666
8757 19:27:29.002451 RX Delay 3 -> 252, step: 4
8758 19:27:29.005953 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8759 19:27:29.012489 iDelay=195, Bit 1, Center 122 (67 ~ 178) 112
8760 19:27:29.015292 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8761 19:27:29.018956 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8762 19:27:29.021966 iDelay=195, Bit 4, Center 128 (75 ~ 182) 108
8763 19:27:29.025355 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8764 19:27:29.032298 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8765 19:27:29.035701 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8766 19:27:29.038700 iDelay=195, Bit 8, Center 104 (47 ~ 162) 116
8767 19:27:29.042118 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8768 19:27:29.045126 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8769 19:27:29.051781 iDelay=195, Bit 11, Center 112 (55 ~ 170) 116
8770 19:27:29.055068 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116
8771 19:27:29.058437 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8772 19:27:29.061758 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
8773 19:27:29.064626 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8774 19:27:29.068211 ==
8775 19:27:29.071461 Dram Type= 6, Freq= 0, CH_1, rank 1
8776 19:27:29.074913 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8777 19:27:29.075036 ==
8778 19:27:29.075130 DQS Delay:
8779 19:27:29.077821 DQS0 = 0, DQS1 = 0
8780 19:27:29.077960 DQM Delay:
8781 19:27:29.081226 DQM0 = 127, DQM1 = 122
8782 19:27:29.081323 DQ Delay:
8783 19:27:29.084478 DQ0 =128, DQ1 =122, DQ2 =118, DQ3 =124
8784 19:27:29.087785 DQ4 =128, DQ5 =138, DQ6 =136, DQ7 =126
8785 19:27:29.090969 DQ8 =104, DQ9 =110, DQ10 =124, DQ11 =112
8786 19:27:29.094182 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8787 19:27:29.094263
8788 19:27:29.094326
8789 19:27:29.094384
8790 19:27:29.098112 [DramC_TX_OE_Calibration] TA2
8791 19:27:29.101367 Original DQ_B0 (3 6) =30, OEN = 27
8792 19:27:29.104586 Original DQ_B1 (3 6) =30, OEN = 27
8793 19:27:29.115770 24, 0x0, End_B0=24 End_B1=24
8794 19:27:29.116100 25, 0x0, End_B0=25 End_B1=25
8795 19:27:29.116362 26, 0x0, End_B0=26 End_B1=26
8796 19:27:29.116602 27, 0x0, End_B0=27 End_B1=27
8797 19:27:29.117735 28, 0x0, End_B0=28 End_B1=28
8798 19:27:29.120779 29, 0x0, End_B0=29 End_B1=29
8799 19:27:29.124336 30, 0x0, End_B0=30 End_B1=30
8800 19:27:29.124662 31, 0x4141, End_B0=30 End_B1=30
8801 19:27:29.127790 Byte0 end_step=30 best_step=27
8802 19:27:29.131017 Byte1 end_step=30 best_step=27
8803 19:27:29.134221 Byte0 TX OE(2T, 0.5T) = (3, 3)
8804 19:27:29.137628 Byte1 TX OE(2T, 0.5T) = (3, 3)
8805 19:27:29.138094
8806 19:27:29.138370
8807 19:27:29.144084 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
8808 19:27:29.147503 CH1 RK1: MR19=303, MR18=1C1C
8809 19:27:29.154139 CH1_RK1: MR19=0x303, MR18=0x1C1C, DQSOSC=395, MR23=63, INC=23, DEC=15
8810 19:27:29.157714 [RxdqsGatingPostProcess] freq 1600
8811 19:27:29.164337 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8812 19:27:29.167663 Pre-setting of DQS Precalculation
8813 19:27:29.171028 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8814 19:27:29.177442 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8815 19:27:29.183922 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8816 19:27:29.184338
8817 19:27:29.187330
8818 19:27:29.187552 [Calibration Summary] 3200 Mbps
8819 19:27:29.190369 CH 0, Rank 0
8820 19:27:29.190591 SW Impedance : PASS
8821 19:27:29.193683 DUTY Scan : NO K
8822 19:27:29.197279 ZQ Calibration : PASS
8823 19:27:29.197431 Jitter Meter : NO K
8824 19:27:29.200720 CBT Training : PASS
8825 19:27:29.203906 Write leveling : PASS
8826 19:27:29.204037 RX DQS gating : PASS
8827 19:27:29.206864 RX DQ/DQS(RDDQC) : PASS
8828 19:27:29.209954 TX DQ/DQS : PASS
8829 19:27:29.210114 RX DATLAT : PASS
8830 19:27:29.213341 RX DQ/DQS(Engine): PASS
8831 19:27:29.216939 TX OE : PASS
8832 19:27:29.217099 All Pass.
8833 19:27:29.217206
8834 19:27:29.217277 CH 0, Rank 1
8835 19:27:29.220013 SW Impedance : PASS
8836 19:27:29.223293 DUTY Scan : NO K
8837 19:27:29.223389 ZQ Calibration : PASS
8838 19:27:29.226407 Jitter Meter : NO K
8839 19:27:29.230109 CBT Training : PASS
8840 19:27:29.230195 Write leveling : PASS
8841 19:27:29.232941 RX DQS gating : PASS
8842 19:27:29.236353 RX DQ/DQS(RDDQC) : PASS
8843 19:27:29.236435 TX DQ/DQS : PASS
8844 19:27:29.239856 RX DATLAT : PASS
8845 19:27:29.239951 RX DQ/DQS(Engine): PASS
8846 19:27:29.243426 TX OE : PASS
8847 19:27:29.243511 All Pass.
8848 19:27:29.243604
8849 19:27:29.246402 CH 1, Rank 0
8850 19:27:29.249730 SW Impedance : PASS
8851 19:27:29.250162 DUTY Scan : NO K
8852 19:27:29.252911 ZQ Calibration : PASS
8853 19:27:29.253235 Jitter Meter : NO K
8854 19:27:29.256288 CBT Training : PASS
8855 19:27:29.259658 Write leveling : PASS
8856 19:27:29.260015 RX DQS gating : PASS
8857 19:27:29.262900 RX DQ/DQS(RDDQC) : PASS
8858 19:27:29.266218 TX DQ/DQS : PASS
8859 19:27:29.266745 RX DATLAT : PASS
8860 19:27:29.269664 RX DQ/DQS(Engine): PASS
8861 19:27:29.272869 TX OE : PASS
8862 19:27:29.273213 All Pass.
8863 19:27:29.273468
8864 19:27:29.273705 CH 1, Rank 1
8865 19:27:29.275884 SW Impedance : PASS
8866 19:27:29.279454 DUTY Scan : NO K
8867 19:27:29.279779 ZQ Calibration : PASS
8868 19:27:29.282518 Jitter Meter : NO K
8869 19:27:29.285945 CBT Training : PASS
8870 19:27:29.286313 Write leveling : PASS
8871 19:27:29.289139 RX DQS gating : PASS
8872 19:27:29.292616 RX DQ/DQS(RDDQC) : PASS
8873 19:27:29.292938 TX DQ/DQS : PASS
8874 19:27:29.295999 RX DATLAT : PASS
8875 19:27:29.299079 RX DQ/DQS(Engine): PASS
8876 19:27:29.299405 TX OE : PASS
8877 19:27:29.302777 All Pass.
8878 19:27:29.303098
8879 19:27:29.303360 DramC Write-DBI on
8880 19:27:29.305851 PER_BANK_REFRESH: Hybrid Mode
8881 19:27:29.306245 TX_TRACKING: ON
8882 19:27:29.316015 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8883 19:27:29.325678 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8884 19:27:29.332427 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8885 19:27:29.335644 [FAST_K] Save calibration result to emmc
8886 19:27:29.338768 sync common calibartion params.
8887 19:27:29.339093 sync cbt_mode0:0, 1:0
8888 19:27:29.341990 dram_init: ddr_geometry: 0
8889 19:27:29.345302 dram_init: ddr_geometry: 0
8890 19:27:29.345543 dram_init: ddr_geometry: 0
8891 19:27:29.348738 0:dram_rank_size:80000000
8892 19:27:29.351859 1:dram_rank_size:80000000
8893 19:27:29.358561 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8894 19:27:29.358697 DFS_SHUFFLE_HW_MODE: ON
8895 19:27:29.361937 dramc_set_vcore_voltage set vcore to 725000
8896 19:27:29.364922 Read voltage for 1600, 0
8897 19:27:29.365042 Vio18 = 0
8898 19:27:29.368076 Vcore = 725000
8899 19:27:29.368180 Vdram = 0
8900 19:27:29.368261 Vddq = 0
8901 19:27:29.371658 Vmddr = 0
8902 19:27:29.371752 switch to 3200 Mbps bootup
8903 19:27:29.375047 [DramcRunTimeConfig]
8904 19:27:29.375141 PHYPLL
8905 19:27:29.378298 DPM_CONTROL_AFTERK: ON
8906 19:27:29.378385 PER_BANK_REFRESH: ON
8907 19:27:29.381811 REFRESH_OVERHEAD_REDUCTION: ON
8908 19:27:29.384909 CMD_PICG_NEW_MODE: OFF
8909 19:27:29.384991 XRTWTW_NEW_MODE: ON
8910 19:27:29.388010 XRTRTR_NEW_MODE: ON
8911 19:27:29.388091 TX_TRACKING: ON
8912 19:27:29.391297 RDSEL_TRACKING: OFF
8913 19:27:29.394900 DQS Precalculation for DVFS: ON
8914 19:27:29.394983 RX_TRACKING: OFF
8915 19:27:29.398140 HW_GATING DBG: ON
8916 19:27:29.398222 ZQCS_ENABLE_LP4: ON
8917 19:27:29.401318 RX_PICG_NEW_MODE: ON
8918 19:27:29.401399 TX_PICG_NEW_MODE: ON
8919 19:27:29.404566 ENABLE_RX_DCM_DPHY: ON
8920 19:27:29.408248 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8921 19:27:29.411451 DUMMY_READ_FOR_TRACKING: OFF
8922 19:27:29.411533 !!! SPM_CONTROL_AFTERK: OFF
8923 19:27:29.414778 !!! SPM could not control APHY
8924 19:27:29.417912 IMPEDANCE_TRACKING: ON
8925 19:27:29.417993 TEMP_SENSOR: ON
8926 19:27:29.421159 HW_SAVE_FOR_SR: OFF
8927 19:27:29.424678 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8928 19:27:29.427641 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8929 19:27:29.431129 Read ODT Tracking: ON
8930 19:27:29.431211 Refresh Rate DeBounce: ON
8931 19:27:29.434351 DFS_NO_QUEUE_FLUSH: ON
8932 19:27:29.437696 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8933 19:27:29.440853 ENABLE_DFS_RUNTIME_MRW: OFF
8934 19:27:29.440935 DDR_RESERVE_NEW_MODE: ON
8935 19:27:29.444539 MR_CBT_SWITCH_FREQ: ON
8936 19:27:29.447450 =========================
8937 19:27:29.465337 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8938 19:27:29.468405 dram_init: ddr_geometry: 0
8939 19:27:29.486554 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8940 19:27:29.489766 dram_init: dram init end (result: 0)
8941 19:27:29.496775 DRAM-K: Full calibration passed in 23461 msecs
8942 19:27:29.499978 MRC: failed to locate region type 0.
8943 19:27:29.500140 DRAM rank0 size:0x80000000,
8944 19:27:29.503109 DRAM rank1 size=0x80000000
8945 19:27:29.512727 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8946 19:27:29.518984 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8947 19:27:29.525953 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8948 19:27:29.532287 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8949 19:27:29.535597 DRAM rank0 size:0x80000000,
8950 19:27:29.538973 DRAM rank1 size=0x80000000
8951 19:27:29.539165 CBMEM:
8952 19:27:29.542494 IMD: root @ 0xfffff000 254 entries.
8953 19:27:29.545898 IMD: root @ 0xffffec00 62 entries.
8954 19:27:29.549084 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8955 19:27:29.552211 WARNING: RO_VPD is uninitialized or empty.
8956 19:27:29.558896 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8957 19:27:29.566327 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8958 19:27:29.578694 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
8959 19:27:29.590052 BS: romstage times (exec / console): total (unknown) / 22996 ms
8960 19:27:29.590232
8961 19:27:29.590322
8962 19:27:29.600103 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8963 19:27:29.603282 ARM64: Exception handlers installed.
8964 19:27:29.606692 ARM64: Testing exception
8965 19:27:29.610152 ARM64: Done test exception
8966 19:27:29.610353 Enumerating buses...
8967 19:27:29.613533 Show all devs... Before device enumeration.
8968 19:27:29.616858 Root Device: enabled 1
8969 19:27:29.620279 CPU_CLUSTER: 0: enabled 1
8970 19:27:29.620517 CPU: 00: enabled 1
8971 19:27:29.623537 Compare with tree...
8972 19:27:29.623765 Root Device: enabled 1
8973 19:27:29.626974 CPU_CLUSTER: 0: enabled 1
8974 19:27:29.630110 CPU: 00: enabled 1
8975 19:27:29.630364 Root Device scanning...
8976 19:27:29.633503 scan_static_bus for Root Device
8977 19:27:29.636610 CPU_CLUSTER: 0 enabled
8978 19:27:29.640457 scan_static_bus for Root Device done
8979 19:27:29.643569 scan_bus: bus Root Device finished in 8 msecs
8980 19:27:29.644011 done
8981 19:27:29.650247 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8982 19:27:29.654348 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8983 19:27:29.659621 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8984 19:27:29.662983 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8985 19:27:29.666451 Allocating resources...
8986 19:27:29.670013 Reading resources...
8987 19:27:29.673255 Root Device read_resources bus 0 link: 0
8988 19:27:29.673719 DRAM rank0 size:0x80000000,
8989 19:27:29.676401 DRAM rank1 size=0x80000000
8990 19:27:29.679857 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8991 19:27:29.683294 CPU: 00 missing read_resources
8992 19:27:29.689845 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8993 19:27:29.693352 Root Device read_resources bus 0 link: 0 done
8994 19:27:29.694141 Done reading resources.
8995 19:27:29.699531 Show resources in subtree (Root Device)...After reading.
8996 19:27:29.703010 Root Device child on link 0 CPU_CLUSTER: 0
8997 19:27:29.706304 CPU_CLUSTER: 0 child on link 0 CPU: 00
8998 19:27:29.716267 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8999 19:27:29.716838 CPU: 00
9000 19:27:29.719768 Root Device assign_resources, bus 0 link: 0
9001 19:27:29.722980 CPU_CLUSTER: 0 missing set_resources
9002 19:27:29.729395 Root Device assign_resources, bus 0 link: 0 done
9003 19:27:29.729874 Done setting resources.
9004 19:27:29.736309 Show resources in subtree (Root Device)...After assigning values.
9005 19:27:29.739454 Root Device child on link 0 CPU_CLUSTER: 0
9006 19:27:29.742695 CPU_CLUSTER: 0 child on link 0 CPU: 00
9007 19:27:29.752734 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
9008 19:27:29.753297 CPU: 00
9009 19:27:29.755777 Done allocating resources.
9010 19:27:29.762479 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9011 19:27:29.762943 Enabling resources...
9012 19:27:29.763424 done.
9013 19:27:29.769237 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9014 19:27:29.769806 Initializing devices...
9015 19:27:29.772141 Root Device init
9016 19:27:29.772614 init hardware done!
9017 19:27:29.775517 0x00000018: ctrlr->caps
9018 19:27:29.778722 52.000 MHz: ctrlr->f_max
9019 19:27:29.779209 0.400 MHz: ctrlr->f_min
9020 19:27:29.782139 0x40ff8080: ctrlr->voltages
9021 19:27:29.785607 sclk: 390625
9022 19:27:29.786122 Bus Width = 1
9023 19:27:29.786718 sclk: 390625
9024 19:27:29.788978 Bus Width = 1
9025 19:27:29.789436 Early init status = 3
9026 19:27:29.795157 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9027 19:27:29.798825 in-header: 03 fc 00 00 01 00 00 00
9028 19:27:29.802356 in-data: 00
9029 19:27:29.805010 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9030 19:27:29.810889 in-header: 03 fd 00 00 00 00 00 00
9031 19:27:29.814303 in-data:
9032 19:27:29.817355 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9033 19:27:29.822238 in-header: 03 fc 00 00 01 00 00 00
9034 19:27:29.824750 in-data: 00
9035 19:27:29.828431 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9036 19:27:29.834035 in-header: 03 fd 00 00 00 00 00 00
9037 19:27:29.837769 in-data:
9038 19:27:29.840631 [SSUSB] Setting up USB HOST controller...
9039 19:27:29.844205 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9040 19:27:29.847576 [SSUSB] phy power-on done.
9041 19:27:29.850640 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9042 19:27:29.857400 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9043 19:27:29.860787 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9044 19:27:29.867385 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9045 19:27:29.874146 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9046 19:27:29.880425 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9047 19:27:29.887292 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9048 19:27:29.894121 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9049 19:27:29.897048 SPM: binary array size = 0x9dc
9050 19:27:29.900980 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9051 19:27:29.906906 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9052 19:27:29.914172 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9053 19:27:29.920351 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9054 19:27:29.923885 configure_display: Starting display init
9055 19:27:29.958078 anx7625_power_on_init: Init interface.
9056 19:27:29.961080 anx7625_disable_pd_protocol: Disabled PD feature.
9057 19:27:29.964162 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9058 19:27:29.992227 anx7625_start_dp_work: Secure OCM version=00
9059 19:27:29.995514 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9060 19:27:30.010134 sp_tx_get_edid_block: EDID Block = 1
9061 19:27:30.112688 Extracted contents:
9062 19:27:30.115863 header: 00 ff ff ff ff ff ff 00
9063 19:27:30.119440 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9064 19:27:30.122891 version: 01 04
9065 19:27:30.125763 basic params: 95 1f 11 78 0a
9066 19:27:30.129444 chroma info: 76 90 94 55 54 90 27 21 50 54
9067 19:27:30.132561 established: 00 00 00
9068 19:27:30.139316 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9069 19:27:30.142534 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9070 19:27:30.149588 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9071 19:27:30.155876 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9072 19:27:30.162216 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9073 19:27:30.165555 extensions: 00
9074 19:27:30.166012 checksum: fb
9075 19:27:30.166429
9076 19:27:30.168874 Manufacturer: IVO Model 57d Serial Number 0
9077 19:27:30.172425 Made week 0 of 2020
9078 19:27:30.175734 EDID version: 1.4
9079 19:27:30.176206 Digital display
9080 19:27:30.178755 6 bits per primary color channel
9081 19:27:30.179313 DisplayPort interface
9082 19:27:30.182197 Maximum image size: 31 cm x 17 cm
9083 19:27:30.185202 Gamma: 220%
9084 19:27:30.185836 Check DPMS levels
9085 19:27:30.188640 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9086 19:27:30.195460 First detailed timing is preferred timing
9087 19:27:30.196019 Established timings supported:
9088 19:27:30.198580 Standard timings supported:
9089 19:27:30.201917 Detailed timings
9090 19:27:30.204930 Hex of detail: 383680a07038204018303c0035ae10000019
9091 19:27:30.211659 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9092 19:27:30.215518 0780 0798 07c8 0820 hborder 0
9093 19:27:30.218225 0438 043b 0447 0458 vborder 0
9094 19:27:30.221676 -hsync -vsync
9095 19:27:30.222333 Did detailed timing
9096 19:27:30.228188 Hex of detail: 000000000000000000000000000000000000
9097 19:27:30.231894 Manufacturer-specified data, tag 0
9098 19:27:30.235107 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9099 19:27:30.238412 ASCII string: InfoVision
9100 19:27:30.241479 Hex of detail: 000000fe00523134304e574635205248200a
9101 19:27:30.244879 ASCII string: R140NWF5 RH
9102 19:27:30.245294 Checksum
9103 19:27:30.247922 Checksum: 0xfb (valid)
9104 19:27:30.251393 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9105 19:27:30.254800 DSI data_rate: 832800000 bps
9106 19:27:30.261682 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9107 19:27:30.264657 anx7625_parse_edid: pixelclock(138800).
9108 19:27:30.267991 hactive(1920), hsync(48), hfp(24), hbp(88)
9109 19:27:30.271665 vactive(1080), vsync(12), vfp(3), vbp(17)
9110 19:27:30.274673 anx7625_dsi_config: config dsi.
9111 19:27:30.281202 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9112 19:27:30.294954 anx7625_dsi_config: success to config DSI
9113 19:27:30.297791 anx7625_dp_start: MIPI phy setup OK.
9114 19:27:30.301200 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9115 19:27:30.304637 mtk_ddp_mode_set invalid vrefresh 60
9116 19:27:30.307542 main_disp_path_setup
9117 19:27:30.307959 ovl_layer_smi_id_en
9118 19:27:30.310847 ovl_layer_smi_id_en
9119 19:27:30.311143 ccorr_config
9120 19:27:30.311379 aal_config
9121 19:27:30.314138 gamma_config
9122 19:27:30.314439 postmask_config
9123 19:27:30.317408 dither_config
9124 19:27:30.320563 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9125 19:27:30.327550 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9126 19:27:30.330937 Root Device init finished in 555 msecs
9127 19:27:30.334215 CPU_CLUSTER: 0 init
9128 19:27:30.340523 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9129 19:27:30.347235 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9130 19:27:30.347325 APU_MBOX 0x190000b0 = 0x10001
9131 19:27:30.350487 APU_MBOX 0x190001b0 = 0x10001
9132 19:27:30.353849 APU_MBOX 0x190005b0 = 0x10001
9133 19:27:30.357222 APU_MBOX 0x190006b0 = 0x10001
9134 19:27:30.363607 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9135 19:27:30.373608 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9136 19:27:30.385873 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9137 19:27:30.392219 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9138 19:27:30.404301 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9139 19:27:30.412974 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9140 19:27:30.416287 CPU_CLUSTER: 0 init finished in 81 msecs
9141 19:27:30.419963 Devices initialized
9142 19:27:30.423051 Show all devs... After init.
9143 19:27:30.423165 Root Device: enabled 1
9144 19:27:30.426477 CPU_CLUSTER: 0: enabled 1
9145 19:27:30.429804 CPU: 00: enabled 1
9146 19:27:30.432821 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9147 19:27:30.436468 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9148 19:27:30.439942 ELOG: NV offset 0x57f000 size 0x1000
9149 19:27:30.446281 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9150 19:27:30.452732 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9151 19:27:30.456282 ELOG: Event(17) added with size 13 at 2024-04-18 19:27:30 UTC
9152 19:27:30.463161 out: cmd=0x121: 03 db 21 01 00 00 00 00
9153 19:27:30.466483 in-header: 03 bc 00 00 2c 00 00 00
9154 19:27:30.476537 in-data: a7 64 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9155 19:27:30.482788 ELOG: Event(A1) added with size 10 at 2024-04-18 19:27:30 UTC
9156 19:27:30.489489 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9157 19:27:30.496266 ELOG: Event(A0) added with size 9 at 2024-04-18 19:27:30 UTC
9158 19:27:30.499571 elog_add_boot_reason: Logged dev mode boot
9159 19:27:30.506355 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9160 19:27:30.506769 Finalize devices...
9161 19:27:30.509618 Devices finalized
9162 19:27:30.512801 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9163 19:27:30.516754 Writing coreboot table at 0xffe64000
9164 19:27:30.519726 0. 000000000010a000-0000000000113fff: RAMSTAGE
9165 19:27:30.522906 1. 0000000040000000-00000000400fffff: RAM
9166 19:27:30.529557 2. 0000000040100000-000000004032afff: RAMSTAGE
9167 19:27:30.532683 3. 000000004032b000-00000000545fffff: RAM
9168 19:27:30.536105 4. 0000000054600000-000000005465ffff: BL31
9169 19:27:30.539502 5. 0000000054660000-00000000ffe63fff: RAM
9170 19:27:30.545995 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9171 19:27:30.549262 7. 0000000100000000-000000013fffffff: RAM
9172 19:27:30.552675 Passing 5 GPIOs to payload:
9173 19:27:30.555820 NAME | PORT | POLARITY | VALUE
9174 19:27:30.559156 EC in RW | 0x000000aa | low | undefined
9175 19:27:30.565945 EC interrupt | 0x00000005 | low | undefined
9176 19:27:30.569048 TPM interrupt | 0x000000ab | high | undefined
9177 19:27:30.575731 SD card detect | 0x00000011 | high | undefined
9178 19:27:30.579150 speaker enable | 0x00000093 | high | undefined
9179 19:27:30.582466 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9180 19:27:30.585580 in-header: 03 f8 00 00 02 00 00 00
9181 19:27:30.589114 in-data: 03 00
9182 19:27:30.589619 ADC[4]: Raw value=668958 ID=5
9183 19:27:30.592359 ADC[3]: Raw value=212549 ID=1
9184 19:27:30.595884 RAM Code: 0x51
9185 19:27:30.598615 ADC[6]: Raw value=74410 ID=0
9186 19:27:30.599190 ADC[5]: Raw value=211444 ID=1
9187 19:27:30.601971 SKU Code: 0x1
9188 19:27:30.605929 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 336d
9189 19:27:30.608552 coreboot table: 964 bytes.
9190 19:27:30.612022 IMD ROOT 0. 0xfffff000 0x00001000
9191 19:27:30.615403 IMD SMALL 1. 0xffffe000 0x00001000
9192 19:27:30.618423 RO MCACHE 2. 0xffffc000 0x00001104
9193 19:27:30.621805 CONSOLE 3. 0xfff7c000 0x00080000
9194 19:27:30.625062 FMAP 4. 0xfff7b000 0x00000452
9195 19:27:30.628704 TIME STAMP 5. 0xfff7a000 0x00000910
9196 19:27:30.632066 VBOOT WORK 6. 0xfff66000 0x00014000
9197 19:27:30.635169 RAMOOPS 7. 0xffe66000 0x00100000
9198 19:27:30.638790 COREBOOT 8. 0xffe64000 0x00002000
9199 19:27:30.642117 IMD small region:
9200 19:27:30.644949 IMD ROOT 0. 0xffffec00 0x00000400
9201 19:27:30.648232 VPD 1. 0xffffeb80 0x0000006c
9202 19:27:30.651581 MMC STATUS 2. 0xffffeb60 0x00000004
9203 19:27:30.654910 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9204 19:27:30.658069 Probing TPM: done!
9205 19:27:30.661726 Connected to device vid:did:rid of 1ae0:0028:00
9206 19:27:30.672476 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
9207 19:27:30.675660 Initialized TPM device CR50 revision 0
9208 19:27:30.679570 Checking cr50 for pending updates
9209 19:27:30.683087 Reading cr50 TPM mode
9210 19:27:30.692163 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9211 19:27:30.698402 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9212 19:27:30.738827 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9213 19:27:30.742117 Checking segment from ROM address 0x40100000
9214 19:27:30.745343 Checking segment from ROM address 0x4010001c
9215 19:27:30.752099 Loading segment from ROM address 0x40100000
9216 19:27:30.752659 code (compression=0)
9217 19:27:30.762185 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9218 19:27:30.768641 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9219 19:27:30.769202 it's not compressed!
9220 19:27:30.774958 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9221 19:27:30.778790 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9222 19:27:30.798786 Loading segment from ROM address 0x4010001c
9223 19:27:30.799280 Entry Point 0x80000000
9224 19:27:30.802128 Loaded segments
9225 19:27:30.805266 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9226 19:27:30.812135 Jumping to boot code at 0x80000000(0xffe64000)
9227 19:27:30.818735 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9228 19:27:30.825405 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9229 19:27:30.833378 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9230 19:27:30.837186 Checking segment from ROM address 0x40100000
9231 19:27:30.840292 Checking segment from ROM address 0x4010001c
9232 19:27:30.846918 Loading segment from ROM address 0x40100000
9233 19:27:30.847334 code (compression=1)
9234 19:27:30.853632 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9235 19:27:30.863149 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9236 19:27:30.863568 using LZMA
9237 19:27:30.871713 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9238 19:27:30.878909 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9239 19:27:30.881936 Loading segment from ROM address 0x4010001c
9240 19:27:30.882431 Entry Point 0x54601000
9241 19:27:30.885221 Loaded segments
9242 19:27:30.888453 NOTICE: MT8192 bl31_setup
9243 19:27:30.895204 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9244 19:27:30.898532 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9245 19:27:30.901720 WARNING: region 0:
9246 19:27:30.905256 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9247 19:27:30.905669 WARNING: region 1:
9248 19:27:30.911939 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9249 19:27:30.915266 WARNING: region 2:
9250 19:27:30.918523 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9251 19:27:30.921823 WARNING: region 3:
9252 19:27:30.925149 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9253 19:27:30.928942 WARNING: region 4:
9254 19:27:30.935122 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9255 19:27:30.935577 WARNING: region 5:
9256 19:27:30.938363 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9257 19:27:30.941886 WARNING: region 6:
9258 19:27:30.945217 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9259 19:27:30.948467 WARNING: region 7:
9260 19:27:30.951675 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9261 19:27:30.958494 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9262 19:27:30.961894 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9263 19:27:30.964920 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9264 19:27:30.972174 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9265 19:27:30.974875 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9266 19:27:30.979014 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9267 19:27:30.985084 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9268 19:27:30.989092 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9269 19:27:30.995570 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9270 19:27:30.998489 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9271 19:27:31.001998 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9272 19:27:31.008707 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9273 19:27:31.012283 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9274 19:27:31.015212 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9275 19:27:31.022015 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9276 19:27:31.025366 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9277 19:27:31.031807 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9278 19:27:31.035062 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9279 19:27:31.038698 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9280 19:27:31.045495 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9281 19:27:31.048381 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9282 19:27:31.051791 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9283 19:27:31.058433 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9284 19:27:31.061777 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9285 19:27:31.068523 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9286 19:27:31.071769 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9287 19:27:31.074857 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9288 19:27:31.081461 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9289 19:27:31.084886 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9290 19:27:31.091838 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9291 19:27:31.094714 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9292 19:27:31.098136 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9293 19:27:31.104774 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9294 19:27:31.108286 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9295 19:27:31.111633 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9296 19:27:31.115344 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9297 19:27:31.122120 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9298 19:27:31.124912 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9299 19:27:31.128385 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9300 19:27:31.131631 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9301 19:27:31.138192 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9302 19:27:31.141944 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9303 19:27:31.145326 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9304 19:27:31.148579 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9305 19:27:31.154710 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9306 19:27:31.158103 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9307 19:27:31.161276 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9308 19:27:31.165102 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9309 19:27:31.171638 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9310 19:27:31.174873 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9311 19:27:31.181342 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9312 19:27:31.184776 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9313 19:27:31.191431 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9314 19:27:31.194822 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9315 19:27:31.198222 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9316 19:27:31.205095 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9317 19:27:31.207988 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9318 19:27:31.214874 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9319 19:27:31.218210 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9320 19:27:31.225246 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9321 19:27:31.228421 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9322 19:27:31.235059 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9323 19:27:31.237976 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9324 19:27:31.241544 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9325 19:27:31.248099 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9326 19:27:31.251565 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9327 19:27:31.258299 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9328 19:27:31.261638 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9329 19:27:31.268071 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9330 19:27:31.271155 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9331 19:27:31.274773 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9332 19:27:31.281222 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9333 19:27:31.284476 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9334 19:27:31.292183 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9335 19:27:31.294704 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9336 19:27:31.301257 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9337 19:27:31.304219 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9338 19:27:31.307706 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9339 19:27:31.314161 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9340 19:27:31.317466 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9341 19:27:31.324438 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9342 19:27:31.327433 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9343 19:27:31.334318 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9344 19:27:31.337488 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9345 19:27:31.341108 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9346 19:27:31.347964 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9347 19:27:31.350851 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9348 19:27:31.357460 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9349 19:27:31.360784 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9350 19:27:31.367667 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9351 19:27:31.370861 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9352 19:27:31.374517 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9353 19:27:31.381343 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9354 19:27:31.384392 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9355 19:27:31.390845 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9356 19:27:31.394383 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9357 19:27:31.400703 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9358 19:27:31.404679 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9359 19:27:31.407191 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9360 19:27:31.411115 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9361 19:27:31.414125 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9362 19:27:31.420794 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9363 19:27:31.423975 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9364 19:27:31.430964 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9365 19:27:31.434638 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9366 19:27:31.437516 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9367 19:27:31.444339 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9368 19:27:31.447318 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9369 19:27:31.454408 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9370 19:27:31.457449 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9371 19:27:31.460638 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9372 19:27:31.467617 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9373 19:27:31.471050 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9374 19:27:31.477528 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9375 19:27:31.480545 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9376 19:27:31.487247 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9377 19:27:31.490456 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9378 19:27:31.494113 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9379 19:27:31.497110 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9380 19:27:31.504016 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9381 19:27:31.507596 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9382 19:27:31.510524 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9383 19:27:31.513808 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9384 19:27:31.520358 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9385 19:27:31.523991 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9386 19:27:31.527172 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9387 19:27:31.533648 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9388 19:27:31.537203 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9389 19:27:31.543696 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9390 19:27:31.547057 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9391 19:27:31.550519 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9392 19:27:31.557017 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9393 19:27:31.560722 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9394 19:27:31.567109 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9395 19:27:31.570513 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9396 19:27:31.573892 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9397 19:27:31.580400 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9398 19:27:31.583978 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9399 19:27:31.587187 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9400 19:27:31.593914 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9401 19:27:31.597288 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9402 19:27:31.603631 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9403 19:27:31.607107 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9404 19:27:31.611050 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9405 19:27:31.616982 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9406 19:27:31.620418 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9407 19:27:31.627346 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9408 19:27:31.630671 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9409 19:27:31.633643 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9410 19:27:31.640678 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9411 19:27:31.643627 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9412 19:27:31.647039 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9413 19:27:31.654021 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9414 19:27:31.657004 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9415 19:27:31.663894 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9416 19:27:31.667389 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9417 19:27:31.670629 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9418 19:27:31.677076 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9419 19:27:31.680299 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9420 19:27:31.687032 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9421 19:27:31.690401 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9422 19:27:31.693532 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9423 19:27:31.700453 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9424 19:27:31.703551 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9425 19:27:31.710336 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9426 19:27:31.713510 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9427 19:27:31.716730 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9428 19:27:31.723406 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9429 19:27:31.726797 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9430 19:27:31.733871 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9431 19:27:31.736515 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9432 19:27:31.740193 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9433 19:27:31.746481 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9434 19:27:31.749805 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9435 19:27:31.756038 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9436 19:27:31.759626 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9437 19:27:31.762949 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9438 19:27:31.769434 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9439 19:27:31.772834 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9440 19:27:31.779304 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9441 19:27:31.782255 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9442 19:27:31.785320 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9443 19:27:31.792273 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9444 19:27:31.795794 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9445 19:27:31.802545 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9446 19:27:31.805746 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9447 19:27:31.808984 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9448 19:27:31.815550 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9449 19:27:31.819246 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9450 19:27:31.825593 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9451 19:27:31.828605 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9452 19:27:31.835557 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9453 19:27:31.838825 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9454 19:27:31.841989 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9455 19:27:31.848704 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9456 19:27:31.852028 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9457 19:27:31.858839 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9458 19:27:31.861807 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9459 19:27:31.864991 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9460 19:27:31.871811 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9461 19:27:31.874892 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9462 19:27:31.881275 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9463 19:27:31.884689 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9464 19:27:31.891536 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9465 19:27:31.894722 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9466 19:27:31.898161 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9467 19:27:31.904731 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9468 19:27:31.908304 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9469 19:27:31.914419 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9470 19:27:31.917866 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9471 19:27:31.924411 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9472 19:27:31.927711 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9473 19:27:31.930560 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9474 19:27:31.937356 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9475 19:27:31.940722 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9476 19:27:31.947107 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9477 19:27:31.950444 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9478 19:27:31.957116 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9479 19:27:31.960979 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9480 19:27:31.964044 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9481 19:27:31.970402 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9482 19:27:31.974203 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9483 19:27:31.980821 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9484 19:27:31.983883 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9485 19:27:31.987352 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9486 19:27:31.993701 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9487 19:27:31.997469 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9488 19:27:32.004358 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9489 19:27:32.006871 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9490 19:27:32.010606 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9491 19:27:32.016922 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9492 19:27:32.020238 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9493 19:27:32.023569 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9494 19:27:32.026926 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9495 19:27:32.033451 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9496 19:27:32.036771 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9497 19:27:32.040258 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9498 19:27:32.046722 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9499 19:27:32.050097 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9500 19:27:32.056631 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9501 19:27:32.060119 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9502 19:27:32.063758 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9503 19:27:32.069611 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9504 19:27:32.073297 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9505 19:27:32.076232 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9506 19:27:32.082898 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9507 19:27:32.086311 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9508 19:27:32.092876 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9509 19:27:32.096600 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9510 19:27:32.099251 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9511 19:27:32.106122 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9512 19:27:32.109221 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9513 19:27:32.116087 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9514 19:27:32.119266 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9515 19:27:32.122766 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9516 19:27:32.129524 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9517 19:27:32.133057 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9518 19:27:32.136047 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9519 19:27:32.142866 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9520 19:27:32.145791 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9521 19:27:32.148933 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9522 19:27:32.155728 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9523 19:27:32.159312 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9524 19:27:32.162349 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9525 19:27:32.168806 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9526 19:27:32.172288 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9527 19:27:32.179126 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9528 19:27:32.182121 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9529 19:27:32.185517 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9530 19:27:32.192398 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9531 19:27:32.195541 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9532 19:27:32.199100 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9533 19:27:32.202004 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9534 19:27:32.205271 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9535 19:27:32.211794 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9536 19:27:32.215115 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9537 19:27:32.218637 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9538 19:27:32.222008 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9539 19:27:32.228557 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9540 19:27:32.231557 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9541 19:27:32.235027 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9542 19:27:32.241847 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9543 19:27:32.245038 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9544 19:27:32.248032 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9545 19:27:32.254973 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9546 19:27:32.258334 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9547 19:27:32.264883 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9548 19:27:32.268222 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9549 19:27:32.274622 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9550 19:27:32.277785 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9551 19:27:32.281114 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9552 19:27:32.287717 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9553 19:27:32.291410 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9554 19:27:32.297721 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9555 19:27:32.300748 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9556 19:27:32.307541 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9557 19:27:32.310852 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9558 19:27:32.314085 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9559 19:27:32.320597 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9560 19:27:32.323823 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9561 19:27:32.330601 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9562 19:27:32.333976 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9563 19:27:32.337320 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9564 19:27:32.343911 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9565 19:27:32.347227 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9566 19:27:32.353500 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9567 19:27:32.357005 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9568 19:27:32.360316 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9569 19:27:32.367004 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9570 19:27:32.370011 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9571 19:27:32.376819 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9572 19:27:32.380307 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9573 19:27:32.386929 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9574 19:27:32.390311 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9575 19:27:32.393578 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9576 19:27:32.400272 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9577 19:27:32.403386 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9578 19:27:32.410348 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9579 19:27:32.413229 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9580 19:27:32.416720 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9581 19:27:32.423288 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9582 19:27:32.426274 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9583 19:27:32.433160 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9584 19:27:32.437086 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9585 19:27:32.443275 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9586 19:27:32.446352 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9587 19:27:32.449482 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9588 19:27:32.456429 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9589 19:27:32.459575 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9590 19:27:32.466175 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9591 19:27:32.469459 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9592 19:27:32.472563 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9593 19:27:32.479580 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9594 19:27:32.482570 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9595 19:27:32.489356 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9596 19:27:32.492810 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9597 19:27:32.499075 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9598 19:27:32.502702 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9599 19:27:32.505761 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9600 19:27:32.512156 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9601 19:27:32.515633 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9602 19:27:32.522162 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9603 19:27:32.525372 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9604 19:27:32.528905 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9605 19:27:32.535549 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9606 19:27:32.538964 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9607 19:27:32.545684 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9608 19:27:32.548759 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9609 19:27:32.552194 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9610 19:27:32.558888 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9611 19:27:32.562216 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9612 19:27:32.568531 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9613 19:27:32.571983 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9614 19:27:32.578540 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9615 19:27:32.581642 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9616 19:27:32.584783 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9617 19:27:32.591321 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9618 19:27:32.594888 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9619 19:27:32.601424 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9620 19:27:32.604685 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9621 19:27:32.611291 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9622 19:27:32.614527 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9623 19:27:32.621003 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9624 19:27:32.624542 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9625 19:27:32.627872 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9626 19:27:32.634327 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9627 19:27:32.637769 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9628 19:27:32.644254 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9629 19:27:32.647577 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9630 19:27:32.654736 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9631 19:27:32.657632 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9632 19:27:32.664239 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9633 19:27:32.667479 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9634 19:27:32.670900 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9635 19:27:32.677422 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9636 19:27:32.680574 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9637 19:27:32.687293 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9638 19:27:32.690701 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9639 19:27:32.697407 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9640 19:27:32.700578 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9641 19:27:32.703919 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9642 19:27:32.710465 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9643 19:27:32.713920 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9644 19:27:32.720563 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9645 19:27:32.723616 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9646 19:27:32.730706 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9647 19:27:32.733591 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9648 19:27:32.740372 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9649 19:27:32.743644 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9650 19:27:32.746706 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9651 19:27:32.753744 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9652 19:27:32.757088 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9653 19:27:32.763302 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9654 19:27:32.766947 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9655 19:27:32.773165 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9656 19:27:32.776423 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9657 19:27:32.783188 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9658 19:27:32.786722 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9659 19:27:32.789485 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9660 19:27:32.796303 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9661 19:27:32.799893 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9662 19:27:32.806329 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9663 19:27:32.809577 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9664 19:27:32.813168 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9665 19:27:32.819469 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9666 19:27:32.822859 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9667 19:27:32.829734 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9668 19:27:32.832822 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9669 19:27:32.839362 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9670 19:27:32.842391 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9671 19:27:32.849029 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9672 19:27:32.852355 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9673 19:27:32.858883 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9674 19:27:32.862279 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9675 19:27:32.868944 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9676 19:27:32.872224 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9677 19:27:32.878883 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9678 19:27:32.882301 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9679 19:27:32.889095 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9680 19:27:32.892375 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9681 19:27:32.898605 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9682 19:27:32.901822 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9683 19:27:32.908568 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9684 19:27:32.912018 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9685 19:27:32.918805 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9686 19:27:32.921531 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9687 19:27:32.928512 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9688 19:27:32.932002 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9689 19:27:32.938541 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9690 19:27:32.941658 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9691 19:27:32.948262 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9692 19:27:32.951927 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9693 19:27:32.958459 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9694 19:27:32.961473 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9695 19:27:32.968024 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9696 19:27:32.968631 INFO: [APUAPC] vio 0
9697 19:27:32.975204 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9698 19:27:32.978230 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9699 19:27:32.981265 INFO: [APUAPC] D0_APC_0: 0x400510
9700 19:27:32.985067 INFO: [APUAPC] D0_APC_1: 0x0
9701 19:27:32.988110 INFO: [APUAPC] D0_APC_2: 0x1540
9702 19:27:32.991810 INFO: [APUAPC] D0_APC_3: 0x0
9703 19:27:32.995041 INFO: [APUAPC] D1_APC_0: 0xffffffff
9704 19:27:32.997894 INFO: [APUAPC] D1_APC_1: 0xffffffff
9705 19:27:33.001179 INFO: [APUAPC] D1_APC_2: 0x3fffff
9706 19:27:33.004461 INFO: [APUAPC] D1_APC_3: 0x0
9707 19:27:33.007766 INFO: [APUAPC] D2_APC_0: 0xffffffff
9708 19:27:33.011284 INFO: [APUAPC] D2_APC_1: 0xffffffff
9709 19:27:33.014418 INFO: [APUAPC] D2_APC_2: 0x3fffff
9710 19:27:33.017809 INFO: [APUAPC] D2_APC_3: 0x0
9711 19:27:33.021477 INFO: [APUAPC] D3_APC_0: 0xffffffff
9712 19:27:33.024713 INFO: [APUAPC] D3_APC_1: 0xffffffff
9713 19:27:33.028182 INFO: [APUAPC] D3_APC_2: 0x3fffff
9714 19:27:33.031153 INFO: [APUAPC] D3_APC_3: 0x0
9715 19:27:33.034476 INFO: [APUAPC] D4_APC_0: 0xffffffff
9716 19:27:33.037812 INFO: [APUAPC] D4_APC_1: 0xffffffff
9717 19:27:33.041389 INFO: [APUAPC] D4_APC_2: 0x3fffff
9718 19:27:33.041803 INFO: [APUAPC] D4_APC_3: 0x0
9719 19:27:33.047780 INFO: [APUAPC] D5_APC_0: 0xffffffff
9720 19:27:33.051372 INFO: [APUAPC] D5_APC_1: 0xffffffff
9721 19:27:33.054731 INFO: [APUAPC] D5_APC_2: 0x3fffff
9722 19:27:33.055163 INFO: [APUAPC] D5_APC_3: 0x0
9723 19:27:33.057727 INFO: [APUAPC] D6_APC_0: 0xffffffff
9724 19:27:33.061408 INFO: [APUAPC] D6_APC_1: 0xffffffff
9725 19:27:33.064348 INFO: [APUAPC] D6_APC_2: 0x3fffff
9726 19:27:33.067768 INFO: [APUAPC] D6_APC_3: 0x0
9727 19:27:33.071214 INFO: [APUAPC] D7_APC_0: 0xffffffff
9728 19:27:33.074330 INFO: [APUAPC] D7_APC_1: 0xffffffff
9729 19:27:33.077691 INFO: [APUAPC] D7_APC_2: 0x3fffff
9730 19:27:33.081041 INFO: [APUAPC] D7_APC_3: 0x0
9731 19:27:33.084401 INFO: [APUAPC] D8_APC_0: 0xffffffff
9732 19:27:33.087440 INFO: [APUAPC] D8_APC_1: 0xffffffff
9733 19:27:33.090705 INFO: [APUAPC] D8_APC_2: 0x3fffff
9734 19:27:33.093906 INFO: [APUAPC] D8_APC_3: 0x0
9735 19:27:33.097331 INFO: [APUAPC] D9_APC_0: 0xffffffff
9736 19:27:33.100983 INFO: [APUAPC] D9_APC_1: 0xffffffff
9737 19:27:33.103995 INFO: [APUAPC] D9_APC_2: 0x3fffff
9738 19:27:33.107683 INFO: [APUAPC] D9_APC_3: 0x0
9739 19:27:33.110664 INFO: [APUAPC] D10_APC_0: 0xffffffff
9740 19:27:33.114164 INFO: [APUAPC] D10_APC_1: 0xffffffff
9741 19:27:33.117156 INFO: [APUAPC] D10_APC_2: 0x3fffff
9742 19:27:33.121045 INFO: [APUAPC] D10_APC_3: 0x0
9743 19:27:33.124076 INFO: [APUAPC] D11_APC_0: 0xffffffff
9744 19:27:33.127372 INFO: [APUAPC] D11_APC_1: 0xffffffff
9745 19:27:33.130382 INFO: [APUAPC] D11_APC_2: 0x3fffff
9746 19:27:33.133661 INFO: [APUAPC] D11_APC_3: 0x0
9747 19:27:33.137630 INFO: [APUAPC] D12_APC_0: 0xffffffff
9748 19:27:33.140700 INFO: [APUAPC] D12_APC_1: 0xffffffff
9749 19:27:33.143892 INFO: [APUAPC] D12_APC_2: 0x3fffff
9750 19:27:33.146739 INFO: [APUAPC] D12_APC_3: 0x0
9751 19:27:33.150112 INFO: [APUAPC] D13_APC_0: 0xffffffff
9752 19:27:33.153266 INFO: [APUAPC] D13_APC_1: 0xffffffff
9753 19:27:33.156700 INFO: [APUAPC] D13_APC_2: 0x3fffff
9754 19:27:33.160138 INFO: [APUAPC] D13_APC_3: 0x0
9755 19:27:33.163441 INFO: [APUAPC] D14_APC_0: 0xffffffff
9756 19:27:33.166730 INFO: [APUAPC] D14_APC_1: 0xffffffff
9757 19:27:33.169902 INFO: [APUAPC] D14_APC_2: 0x3fffff
9758 19:27:33.173487 INFO: [APUAPC] D14_APC_3: 0x0
9759 19:27:33.176592 INFO: [APUAPC] D15_APC_0: 0xffffffff
9760 19:27:33.179860 INFO: [APUAPC] D15_APC_1: 0xffffffff
9761 19:27:33.183335 INFO: [APUAPC] D15_APC_2: 0x3fffff
9762 19:27:33.186249 INFO: [APUAPC] D15_APC_3: 0x0
9763 19:27:33.189957 INFO: [APUAPC] APC_CON: 0x4
9764 19:27:33.193035 INFO: [NOCDAPC] D0_APC_0: 0x0
9765 19:27:33.196670 INFO: [NOCDAPC] D0_APC_1: 0x0
9766 19:27:33.199460 INFO: [NOCDAPC] D1_APC_0: 0x0
9767 19:27:33.203043 INFO: [NOCDAPC] D1_APC_1: 0xfff
9768 19:27:33.206310 INFO: [NOCDAPC] D2_APC_0: 0x0
9769 19:27:33.209959 INFO: [NOCDAPC] D2_APC_1: 0xfff
9770 19:27:33.213045 INFO: [NOCDAPC] D3_APC_0: 0x0
9771 19:27:33.213155 INFO: [NOCDAPC] D3_APC_1: 0xfff
9772 19:27:33.216408 INFO: [NOCDAPC] D4_APC_0: 0x0
9773 19:27:33.219338 INFO: [NOCDAPC] D4_APC_1: 0xfff
9774 19:27:33.222637 INFO: [NOCDAPC] D5_APC_0: 0x0
9775 19:27:33.226409 INFO: [NOCDAPC] D5_APC_1: 0xfff
9776 19:27:33.229410 INFO: [NOCDAPC] D6_APC_0: 0x0
9777 19:27:33.232915 INFO: [NOCDAPC] D6_APC_1: 0xfff
9778 19:27:33.236222 INFO: [NOCDAPC] D7_APC_0: 0x0
9779 19:27:33.239248 INFO: [NOCDAPC] D7_APC_1: 0xfff
9780 19:27:33.242471 INFO: [NOCDAPC] D8_APC_0: 0x0
9781 19:27:33.246138 INFO: [NOCDAPC] D8_APC_1: 0xfff
9782 19:27:33.246223 INFO: [NOCDAPC] D9_APC_0: 0x0
9783 19:27:33.249079 INFO: [NOCDAPC] D9_APC_1: 0xfff
9784 19:27:33.252738 INFO: [NOCDAPC] D10_APC_0: 0x0
9785 19:27:33.255712 INFO: [NOCDAPC] D10_APC_1: 0xfff
9786 19:27:33.258975 INFO: [NOCDAPC] D11_APC_0: 0x0
9787 19:27:33.262440 INFO: [NOCDAPC] D11_APC_1: 0xfff
9788 19:27:33.265946 INFO: [NOCDAPC] D12_APC_0: 0x0
9789 19:27:33.268886 INFO: [NOCDAPC] D12_APC_1: 0xfff
9790 19:27:33.272139 INFO: [NOCDAPC] D13_APC_0: 0x0
9791 19:27:33.275517 INFO: [NOCDAPC] D13_APC_1: 0xfff
9792 19:27:33.279170 INFO: [NOCDAPC] D14_APC_0: 0x0
9793 19:27:33.282454 INFO: [NOCDAPC] D14_APC_1: 0xfff
9794 19:27:33.285548 INFO: [NOCDAPC] D15_APC_0: 0x0
9795 19:27:33.288775 INFO: [NOCDAPC] D15_APC_1: 0xfff
9796 19:27:33.292206 INFO: [NOCDAPC] APC_CON: 0x4
9797 19:27:33.295356 INFO: [APUAPC] set_apusys_apc done
9798 19:27:33.298682 INFO: [DEVAPC] devapc_init done
9799 19:27:33.302251 INFO: GICv3 without legacy support detected.
9800 19:27:33.305314 INFO: ARM GICv3 driver initialized in EL3
9801 19:27:33.308552 INFO: Maximum SPI INTID supported: 639
9802 19:27:33.311808 INFO: BL31: Initializing runtime services
9803 19:27:33.318440 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9804 19:27:33.322019 INFO: SPM: enable CPC mode
9805 19:27:33.325096 INFO: mcdi ready for mcusys-off-idle and system suspend
9806 19:27:33.332070 INFO: BL31: Preparing for EL3 exit to normal world
9807 19:27:33.335146 INFO: Entry point address = 0x80000000
9808 19:27:33.338312 INFO: SPSR = 0x8
9809 19:27:33.342775
9810 19:27:33.342856
9811 19:27:33.342918
9812 19:27:33.346202 Starting depthcharge on Spherion...
9813 19:27:33.346309
9814 19:27:33.346400 Wipe memory regions:
9815 19:27:33.346486
9816 19:27:33.347290 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
9817 19:27:33.347419 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
9818 19:27:33.347526 Setting prompt string to ['asurada:']
9819 19:27:33.347633 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
9820 19:27:33.349056 [0x00000040000000, 0x00000054600000)
9821 19:27:33.472255
9822 19:27:33.472762 [0x00000054660000, 0x00000080000000)
9823 19:27:33.732317
9824 19:27:33.732498 [0x000000821a7280, 0x000000ffe64000)
9825 19:27:34.477801
9826 19:27:34.478385 [0x00000100000000, 0x00000140000000)
9827 19:27:34.858939
9828 19:27:34.862236 Initializing XHCI USB controller at 0x11200000.
9829 19:27:35.900261
9830 19:27:35.902845 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9831 19:27:35.903362
9832 19:27:35.903722
9833 19:27:35.904054
9834 19:27:35.904868 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9836 19:27:36.005865 asurada: tftpboot 192.168.201.1 13420409/tftp-deploy-jyww44e8/kernel/image.itb 13420409/tftp-deploy-jyww44e8/kernel/cmdline
9837 19:27:36.006076 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9838 19:27:36.006191 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:24)
9839 19:27:36.010625 tftpboot 192.168.201.1 13420409/tftp-deploy-jyww44e8/kernel/image.itp-deploy-jyww44e8/kernel/cmdline
9840 19:27:36.011085
9841 19:27:36.011435 Waiting for link
9842 19:27:36.171052
9843 19:27:36.171601 R8152: Initializing
9844 19:27:36.171972
9845 19:27:36.174257 Version 9 (ocp_data = 6010)
9846 19:27:36.174720
9847 19:27:36.177906 R8152: Done initializing
9848 19:27:36.178420
9849 19:27:36.178792 Adding net device
9850 19:27:38.187460
9851 19:27:38.188023 done.
9852 19:27:38.188387
9853 19:27:38.188724 MAC: 00:e0:4c:68:03:bd
9854 19:27:38.189048
9855 19:27:38.190521 Sending DHCP discover... done.
9856 19:27:38.191149
9857 19:27:38.193739 Waiting for reply... done.
9858 19:27:38.194391
9859 19:27:38.197083 Sending DHCP request... done.
9860 19:27:38.197538
9861 19:27:38.200717 Waiting for reply... done.
9862 19:27:38.201172
9863 19:27:38.201527 My ip is 192.168.201.16
9864 19:27:38.201857
9865 19:27:38.203942 The DHCP server ip is 192.168.201.1
9866 19:27:38.204402
9867 19:27:38.207722 TFTP server IP predefined by user: 192.168.201.1
9868 19:27:38.208283
9869 19:27:38.214223 Bootfile predefined by user: 13420409/tftp-deploy-jyww44e8/kernel/image.itb
9870 19:27:38.214960
9871 19:27:38.217074 Sending tftp read request... done.
9872 19:27:38.217532
9873 19:27:38.226315 Waiting for the transfer...
9874 19:27:38.226897
9875 19:27:38.519379 00000000 ################################################################
9876 19:27:38.519513
9877 19:27:38.788844 00080000 ################################################################
9878 19:27:38.788986
9879 19:27:39.064134 00100000 ################################################################
9880 19:27:39.064270
9881 19:27:39.343032 00180000 ################################################################
9882 19:27:39.343174
9883 19:27:39.636282 00200000 ################################################################
9884 19:27:39.636422
9885 19:27:39.925669 00280000 ################################################################
9886 19:27:39.925810
9887 19:27:40.207091 00300000 ################################################################
9888 19:27:40.207222
9889 19:27:40.466687 00380000 ################################################################
9890 19:27:40.466835
9891 19:27:40.759264 00400000 ################################################################
9892 19:27:40.759408
9893 19:27:41.030002 00480000 ################################################################
9894 19:27:41.030145
9895 19:27:41.313765 00500000 ################################################################
9896 19:27:41.313934
9897 19:27:41.608902 00580000 ################################################################
9898 19:27:41.609036
9899 19:27:41.887402 00600000 ################################################################
9900 19:27:41.887548
9901 19:27:42.164409 00680000 ################################################################
9902 19:27:42.164557
9903 19:27:42.432102 00700000 ################################################################
9904 19:27:42.432244
9905 19:27:42.705934 00780000 ################################################################
9906 19:27:42.706118
9907 19:27:42.972011 00800000 ################################################################
9908 19:27:42.972162
9909 19:27:43.251446 00880000 ################################################################
9910 19:27:43.251685
9911 19:27:43.539569 00900000 ################################################################
9912 19:27:43.539716
9913 19:27:43.812880 00980000 ################################################################
9914 19:27:43.813023
9915 19:27:44.080975 00a00000 ################################################################
9916 19:27:44.081121
9917 19:27:44.353583 00a80000 ################################################################
9918 19:27:44.353732
9919 19:27:44.617677 00b00000 ################################################################
9920 19:27:44.617830
9921 19:27:44.883773 00b80000 ################################################################
9922 19:27:44.883923
9923 19:27:45.149018 00c00000 ################################################################
9924 19:27:45.149157
9925 19:27:45.449566 00c80000 ################################################################
9926 19:27:45.449721
9927 19:27:45.786414 00d00000 ################################################################
9928 19:27:45.786570
9929 19:27:46.132266 00d80000 ################################################################
9930 19:27:46.132420
9931 19:27:46.481410 00e00000 ################################################################
9932 19:27:46.481558
9933 19:27:46.788665 00e80000 ################################################################
9934 19:27:46.788814
9935 19:27:47.067916 00f00000 ################################################################
9936 19:27:47.068050
9937 19:27:47.347851 00f80000 ################################################################
9938 19:27:47.347993
9939 19:27:47.637083 01000000 ################################################################
9940 19:27:47.637225
9941 19:27:47.897320 01080000 ################################################################
9942 19:27:47.897467
9943 19:27:48.167259 01100000 ################################################################
9944 19:27:48.167407
9945 19:27:48.440472 01180000 ################################################################
9946 19:27:48.440617
9947 19:27:48.733341 01200000 ################################################################
9948 19:27:48.733485
9949 19:27:49.007264 01280000 ################################################################
9950 19:27:49.007391
9951 19:27:49.295280 01300000 ################################################################
9952 19:27:49.295425
9953 19:27:49.588378 01380000 ################################################################
9954 19:27:49.588523
9955 19:27:49.882177 01400000 ################################################################
9956 19:27:49.882320
9957 19:27:50.175731 01480000 ################################################################
9958 19:27:50.175881
9959 19:27:50.441350 01500000 ################################################################
9960 19:27:50.441492
9961 19:27:50.698133 01580000 ################################################################
9962 19:27:50.698277
9963 19:27:50.959804 01600000 ################################################################
9964 19:27:50.959952
9965 19:27:51.211124 01680000 ################################################################
9966 19:27:51.211271
9967 19:27:51.461700 01700000 ################################################################
9968 19:27:51.461851
9969 19:27:51.736835 01780000 ################################################################
9970 19:27:51.736971
9971 19:27:52.015740 01800000 ################################################################
9972 19:27:52.015888
9973 19:27:52.274172 01880000 ################################################################
9974 19:27:52.274314
9975 19:27:52.539758 01900000 ################################################################
9976 19:27:52.539904
9977 19:27:52.797589 01980000 ################################################################
9978 19:27:52.797727
9979 19:27:53.046763 01a00000 ################################################################
9980 19:27:53.046895
9981 19:27:53.342231 01a80000 ################################################################
9982 19:27:53.342380
9983 19:27:53.687293 01b00000 ################################################################
9984 19:27:53.687440
9985 19:27:54.023930 01b80000 ################################################################
9986 19:27:54.024074
9987 19:27:54.366162 01c00000 ################################################################
9988 19:27:54.366325
9989 19:27:54.713106 01c80000 ################################################################
9990 19:27:54.713257
9991 19:27:55.060040 01d00000 ################################################################
9992 19:27:55.060173
9993 19:27:55.409286 01d80000 ################################################################
9994 19:27:55.409447
9995 19:27:55.592153 01e00000 ################################## done.
9996 19:27:55.592307
9997 19:27:55.595338 The bootfile was 31735214 bytes long.
9998 19:27:55.595417
9999 19:27:55.598684 Sending tftp read request... done.
10000 19:27:55.598757
10001 19:27:55.598818 Waiting for the transfer...
10002 19:27:55.598886
10003 19:27:55.601834 00000000 # done.
10004 19:27:55.601932
10005 19:27:55.608787 Command line loaded dynamically from TFTP file: 13420409/tftp-deploy-jyww44e8/kernel/cmdline
10006 19:27:55.608864
10007 19:27:55.631506 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/13420409/extract-nfsrootfs-jxo16__9,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10008 19:27:55.631598
10009 19:27:55.631670 Loading FIT.
10010 19:27:55.631732
10011 19:27:55.634837 Image ramdisk-1 has 18775594 bytes.
10012 19:27:55.634919
10013 19:27:55.638307 Image fdt-1 has 47230 bytes.
10014 19:27:55.638408
10015 19:27:55.641749 Image kernel-1 has 12910355 bytes.
10016 19:27:55.641827
10017 19:27:55.651317 Compat preference: google,spherion-rev3-sku1 google,spherion-rev3 google,spherion-sku1 google,spherion
10018 19:27:55.651393
10019 19:27:55.668198 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 (match) google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10020 19:27:55.668319
10021 19:27:55.674621 Choosing best match conf-1 for compat google,spherion-rev3.
10022 19:27:55.674700
10023 19:27:55.682259 Connected to device vid:did:rid of 1ae0:0028:00
10024 19:27:55.688995
10025 19:27:55.692264 tpm_get_response: command 0x17b, return code 0x0
10026 19:27:55.692376
10027 19:27:55.699267 ec_init: CrosEC protocol v3 supported (256, 248)
10028 19:27:55.699351
10029 19:27:55.702265 tpm_cleanup: add release locality here.
10030 19:27:55.702337
10031 19:27:55.705955 Shutting down all USB controllers.
10032 19:27:55.706089
10033 19:27:55.709259 Removing current net device
10034 19:27:55.709331
10035 19:27:55.712662 Exiting depthcharge with code 4 at timestamp: 50653654
10036 19:27:55.712736
10037 19:27:55.719245 LZMA decompressing kernel-1 to 0x821a6718
10038 19:27:55.719326
10039 19:27:55.722401 LZMA decompressing kernel-1 to 0x40000000
10040 19:27:57.315001
10041 19:27:57.315165 jumping to kernel
10042 19:27:57.315627 end: 2.2.4 bootloader-commands (duration 00:00:24) [common]
10043 19:27:57.315734 start: 2.2.5 auto-login-action (timeout 00:04:02) [common]
10044 19:27:57.315817 Setting prompt string to ['Linux version [0-9]']
10045 19:27:57.315887 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10046 19:27:57.315954 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10047 19:27:57.366283
10048 19:27:57.369513 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10049 19:27:57.372954 start: 2.2.5.1 login-action (timeout 00:04:02) [common]
10050 19:27:57.373043 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10051 19:27:57.373112 Setting prompt string to []
10052 19:27:57.373188 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10053 19:27:57.373261 Using line separator: #'\n'#
10054 19:27:57.373318 No login prompt set.
10055 19:27:57.373377 Parsing kernel messages
10056 19:27:57.373434 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10057 19:27:57.373537 [login-action] Waiting for messages, (timeout 00:04:02)
10058 19:27:57.373601 Waiting using forced prompt support (timeout 00:02:01)
10059 19:27:57.392594 [ 0.000000] Linux version 6.1.86-cip19 (KernelCI@build-j170728-arm64-gcc-10-defconfig-arm64-chromebook-wrkxq) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Apr 18 19:05:54 UTC 2024
10060 19:27:57.396195 [ 0.000000] random: crng init done
10061 19:27:57.402613 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10062 19:27:57.405777 [ 0.000000] efi: UEFI not found.
10063 19:27:57.412386 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10064 19:27:57.419205 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10065 19:27:57.429136 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10066 19:27:57.439207 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10067 19:27:57.445697 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10068 19:27:57.452318 [ 0.000000] printk: bootconsole [mtk8250] enabled
10069 19:27:57.458798 [ 0.000000] NUMA: No NUMA configuration found
10070 19:27:57.465110 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10071 19:27:57.468254 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d4a00-0x13f7d6fff]
10072 19:27:57.472069 [ 0.000000] Zone ranges:
10073 19:27:57.478635 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10074 19:27:57.481844 [ 0.000000] DMA32 empty
10075 19:27:57.488133 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10076 19:27:57.491707 [ 0.000000] Movable zone start for each node
10077 19:27:57.494933 [ 0.000000] Early memory node ranges
10078 19:27:57.501425 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10079 19:27:57.507987 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10080 19:27:57.514488 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10081 19:27:57.521304 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10082 19:27:57.527899 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10083 19:27:57.534267 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10084 19:27:57.564239 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10085 19:27:57.570791 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10086 19:27:57.577795 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10087 19:27:57.580745 [ 0.000000] psci: probing for conduit method from DT.
10088 19:27:57.587166 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10089 19:27:57.590743 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10090 19:27:57.597341 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10091 19:27:57.600627 [ 0.000000] psci: SMC Calling Convention v1.2
10092 19:27:57.606942 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10093 19:27:57.610253 [ 0.000000] Detected VIPT I-cache on CPU0
10094 19:27:57.616970 [ 0.000000] CPU features: detected: GIC system register CPU interface
10095 19:27:57.623439 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10096 19:27:57.630347 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10097 19:27:57.637219 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10098 19:27:57.646570 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10099 19:27:57.653190 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10100 19:27:57.656560 [ 0.000000] alternatives: applying boot alternatives
10101 19:27:57.663061 [ 0.000000] Fallback order for Node 0: 0
10102 19:27:57.669946 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10103 19:27:57.673118 [ 0.000000] Policy zone: Normal
10104 19:27:57.695934 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/13420409/extract-nfsrootfs-jxo16__9,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10105 19:27:57.705882 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10106 19:27:57.715677 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10107 19:27:57.722713 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10108 19:27:57.729269 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10109 19:27:57.735694 <6>[ 0.000000] software IO TLB: area num 8.
10110 19:27:57.790866 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10111 19:27:57.871053 <6>[ 0.000000] Memory: 3831820K/4191232K available (18048K kernel code, 4118K rwdata, 22288K rodata, 8448K init, 616K bss, 326644K reserved, 32768K cma-reserved)
10112 19:27:57.877884 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10113 19:27:57.884477 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10114 19:27:57.887696 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10115 19:27:57.894332 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10116 19:27:57.900821 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10117 19:27:57.904201 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10118 19:27:57.914115 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10119 19:27:57.920884 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10120 19:27:57.927146 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10121 19:27:57.933911 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10122 19:27:57.937223 <6>[ 0.000000] GICv3: 608 SPIs implemented
10123 19:27:57.940589 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10124 19:27:57.947360 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10125 19:27:57.950898 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10126 19:27:57.957418 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10127 19:27:57.970213 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10128 19:27:57.983271 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10129 19:27:57.990062 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10130 19:27:57.997769 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10131 19:27:58.010515 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10132 19:27:58.017160 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10133 19:27:58.024295 <6>[ 0.009180] Console: colour dummy device 80x25
10134 19:27:58.033747 <6>[ 0.013907] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10135 19:27:58.040681 <6>[ 0.024349] pid_max: default: 32768 minimum: 301
10136 19:27:58.043833 <6>[ 0.029250] LSM: Security Framework initializing
10137 19:27:58.050421 <6>[ 0.034165] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10138 19:27:58.060333 <6>[ 0.041772] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10139 19:27:58.066868 <6>[ 0.050999] cblist_init_generic: Setting adjustable number of callback queues.
10140 19:27:58.073519 <6>[ 0.058440] cblist_init_generic: Setting shift to 3 and lim to 1.
10141 19:27:58.083475 <6>[ 0.064818] cblist_init_generic: Setting adjustable number of callback queues.
10142 19:27:58.090229 <6>[ 0.072246] cblist_init_generic: Setting shift to 3 and lim to 1.
10143 19:27:58.093724 <6>[ 0.078646] rcu: Hierarchical SRCU implementation.
10144 19:27:58.099903 <6>[ 0.083661] rcu: Max phase no-delay instances is 1000.
10145 19:27:58.106451 <6>[ 0.090678] EFI services will not be available.
10146 19:27:58.109839 <6>[ 0.095632] smp: Bringing up secondary CPUs ...
10147 19:27:58.118181 <6>[ 0.100676] Detected VIPT I-cache on CPU1
10148 19:27:58.124472 <6>[ 0.100745] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10149 19:27:58.130968 <6>[ 0.100777] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10150 19:27:58.134329 <6>[ 0.101107] Detected VIPT I-cache on CPU2
10151 19:27:58.140961 <6>[ 0.101158] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10152 19:27:58.150979 <6>[ 0.101174] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10153 19:27:58.154133 <6>[ 0.101428] Detected VIPT I-cache on CPU3
10154 19:27:58.160971 <6>[ 0.101475] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10155 19:27:58.167319 <6>[ 0.101489] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10156 19:27:58.170489 <6>[ 0.101787] CPU features: detected: Spectre-v4
10157 19:27:58.177300 <6>[ 0.101792] CPU features: detected: Spectre-BHB
10158 19:27:58.180397 <6>[ 0.101797] Detected PIPT I-cache on CPU4
10159 19:27:58.187187 <6>[ 0.101858] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10160 19:27:58.193892 <6>[ 0.101874] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10161 19:27:58.200131 <6>[ 0.102165] Detected PIPT I-cache on CPU5
10162 19:27:58.206819 <6>[ 0.102228] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10163 19:27:58.213749 <6>[ 0.102244] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10164 19:27:58.217290 <6>[ 0.102523] Detected PIPT I-cache on CPU6
10165 19:27:58.223557 <6>[ 0.102586] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10166 19:27:58.230196 <6>[ 0.102602] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10167 19:27:58.236704 <6>[ 0.102901] Detected PIPT I-cache on CPU7
10168 19:27:58.243305 <6>[ 0.102967] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10169 19:27:58.249664 <6>[ 0.102983] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10170 19:27:58.253013 <6>[ 0.103030] smp: Brought up 1 node, 8 CPUs
10171 19:27:58.259725 <6>[ 0.244322] SMP: Total of 8 processors activated.
10172 19:27:58.263039 <6>[ 0.249244] CPU features: detected: 32-bit EL0 Support
10173 19:27:58.272850 <6>[ 0.254607] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10174 19:27:58.279359 <6>[ 0.263462] CPU features: detected: Common not Private translations
10175 19:27:58.286294 <6>[ 0.269978] CPU features: detected: CRC32 instructions
10176 19:27:58.292648 <6>[ 0.275330] CPU features: detected: RCpc load-acquire (LDAPR)
10177 19:27:58.296127 <6>[ 0.281290] CPU features: detected: LSE atomic instructions
10178 19:27:58.302367 <6>[ 0.287071] CPU features: detected: Privileged Access Never
10179 19:27:58.309159 <6>[ 0.292851] CPU features: detected: RAS Extension Support
10180 19:27:58.315597 <6>[ 0.298459] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10181 19:27:58.318981 <6>[ 0.305697] CPU: All CPU(s) started at EL2
10182 19:27:58.325459 <6>[ 0.310013] alternatives: applying system-wide alternatives
10183 19:27:58.334571 <6>[ 0.320009] devtmpfs: initialized
10184 19:27:58.346720 <6>[ 0.328311] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10185 19:27:58.356141 <6>[ 0.338274] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10186 19:27:58.363004 <6>[ 0.346273] pinctrl core: initialized pinctrl subsystem
10187 19:27:58.366221 <6>[ 0.353073] DMI not present or invalid.
10188 19:27:58.372795 <6>[ 0.357490] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10189 19:27:58.382744 <6>[ 0.364367] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10190 19:27:58.389280 <6>[ 0.371813] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10191 19:27:58.399497 <6>[ 0.379899] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10192 19:27:58.402619 <6>[ 0.388060] audit: initializing netlink subsys (disabled)
10193 19:27:58.412490 <5>[ 0.393762] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10194 19:27:58.418822 <6>[ 0.394515] thermal_sys: Registered thermal governor 'step_wise'
10195 19:27:58.425909 <6>[ 0.401731] thermal_sys: Registered thermal governor 'power_allocator'
10196 19:27:58.428725 <6>[ 0.407988] cpuidle: using governor menu
10197 19:27:58.435327 <6>[ 0.418948] NET: Registered PF_QIPCRTR protocol family
10198 19:27:58.441987 <6>[ 0.424482] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10199 19:27:58.445164 <6>[ 0.431581] ASID allocator initialised with 32768 entries
10200 19:27:58.453105 <6>[ 0.438186] Serial: AMBA PL011 UART driver
10201 19:27:58.462026 <4>[ 0.447334] Trying to register duplicate clock ID: 134
10202 19:27:58.519089 <6>[ 0.507526] KASLR enabled
10203 19:27:58.533572 <6>[ 0.515255] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10204 19:27:58.540032 <6>[ 0.522269] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10205 19:27:58.546797 <6>[ 0.528757] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10206 19:27:58.553118 <6>[ 0.535761] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10207 19:27:58.559731 <6>[ 0.542248] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10208 19:27:58.566184 <6>[ 0.549253] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10209 19:27:58.573020 <6>[ 0.555740] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10210 19:27:58.579368 <6>[ 0.562748] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10211 19:27:58.582877 <6>[ 0.570279] ACPI: Interpreter disabled.
10212 19:27:58.591573 <6>[ 0.576763] iommu: Default domain type: Translated
10213 19:27:58.598076 <6>[ 0.581877] iommu: DMA domain TLB invalidation policy: strict mode
10214 19:27:58.601518 <5>[ 0.588535] SCSI subsystem initialized
10215 19:27:58.608444 <6>[ 0.592697] usbcore: registered new interface driver usbfs
10216 19:27:58.614536 <6>[ 0.598429] usbcore: registered new interface driver hub
10217 19:27:58.618304 <6>[ 0.603983] usbcore: registered new device driver usb
10218 19:27:58.624781 <6>[ 0.610113] pps_core: LinuxPPS API ver. 1 registered
10219 19:27:58.634827 <6>[ 0.615309] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10220 19:27:58.637917 <6>[ 0.624652] PTP clock support registered
10221 19:27:58.641265 <6>[ 0.628895] EDAC MC: Ver: 3.0.0
10222 19:27:58.649250 <6>[ 0.634073] FPGA manager framework
10223 19:27:58.655518 <6>[ 0.637753] Advanced Linux Sound Architecture Driver Initialized.
10224 19:27:58.658593 <6>[ 0.644533] vgaarb: loaded
10225 19:27:58.665211 <6>[ 0.647705] clocksource: Switched to clocksource arch_sys_counter
10226 19:27:58.668659 <5>[ 0.654147] VFS: Disk quotas dquot_6.6.0
10227 19:27:58.675008 <6>[ 0.658329] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10228 19:27:58.678581 <6>[ 0.665517] pnp: PnP ACPI: disabled
10229 19:27:58.687077 <6>[ 0.672188] NET: Registered PF_INET protocol family
10230 19:27:58.693497 <6>[ 0.677566] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10231 19:27:58.705607 <6>[ 0.687577] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10232 19:27:58.715661 <6>[ 0.696362] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10233 19:27:58.722122 <6>[ 0.704329] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10234 19:27:58.728740 <6>[ 0.712736] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10235 19:27:58.739686 <6>[ 0.721389] TCP: Hash tables configured (established 32768 bind 32768)
10236 19:27:58.746050 <6>[ 0.728244] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10237 19:27:58.752899 <6>[ 0.735263] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10238 19:27:58.759261 <6>[ 0.742778] NET: Registered PF_UNIX/PF_LOCAL protocol family
10239 19:27:58.765735 <6>[ 0.748903] RPC: Registered named UNIX socket transport module.
10240 19:27:58.769222 <6>[ 0.755057] RPC: Registered udp transport module.
10241 19:27:58.775898 <6>[ 0.759990] RPC: Registered tcp transport module.
10242 19:27:58.782241 <6>[ 0.764923] RPC: Registered tcp NFSv4.1 backchannel transport module.
10243 19:27:58.785488 <6>[ 0.771589] PCI: CLS 0 bytes, default 64
10244 19:27:58.788710 <6>[ 0.775881] Unpacking initramfs...
10245 19:27:58.798650 <6>[ 0.779933] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10246 19:27:58.805167 <6>[ 0.788553] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10247 19:27:58.812303 <6>[ 0.797386] kvm [1]: IPA Size Limit: 40 bits
10248 19:27:58.815572 <6>[ 0.801912] kvm [1]: GICv3: no GICV resource entry
10249 19:27:58.821935 <6>[ 0.806933] kvm [1]: disabling GICv2 emulation
10250 19:27:58.828461 <6>[ 0.811618] kvm [1]: GIC system register CPU interface enabled
10251 19:27:58.831789 <6>[ 0.817769] kvm [1]: vgic interrupt IRQ18
10252 19:27:58.838304 <6>[ 0.822128] kvm [1]: VHE mode initialized successfully
10253 19:27:58.841632 <5>[ 0.828654] Initialise system trusted keyrings
10254 19:27:58.848322 <6>[ 0.833443] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10255 19:27:58.858355 <6>[ 0.843410] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10256 19:27:58.864732 <5>[ 0.849765] NFS: Registering the id_resolver key type
10257 19:27:58.867807 <5>[ 0.855059] Key type id_resolver registered
10258 19:27:58.874653 <5>[ 0.859471] Key type id_legacy registered
10259 19:27:58.881285 <6>[ 0.863746] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10260 19:27:58.887695 <6>[ 0.870670] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10261 19:27:58.894291 <6>[ 0.878365] 9p: Installing v9fs 9p2000 file system support
10262 19:27:58.930421 <5>[ 0.915768] Key type asymmetric registered
10263 19:27:58.933721 <5>[ 0.920098] Asymmetric key parser 'x509' registered
10264 19:27:58.943913 <6>[ 0.925230] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10265 19:27:58.946889 <6>[ 0.932838] io scheduler mq-deadline registered
10266 19:27:58.950463 <6>[ 0.937596] io scheduler kyber registered
10267 19:27:58.969368 <6>[ 0.954756] EINJ: ACPI disabled.
10268 19:27:59.001957 <4>[ 0.980642] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10269 19:27:59.011691 <4>[ 0.991266] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10270 19:27:59.026735 <6>[ 1.012110] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10271 19:27:59.034741 <6>[ 1.020028] printk: console [ttyS0] disabled
10272 19:27:59.062715 <6>[ 1.044666] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10273 19:27:59.069219 <6>[ 1.054139] printk: console [ttyS0] enabled
10274 19:27:59.072716 <6>[ 1.054139] printk: console [ttyS0] enabled
10275 19:27:59.079317 <6>[ 1.063037] printk: bootconsole [mtk8250] disabled
10276 19:27:59.082779 <6>[ 1.063037] printk: bootconsole [mtk8250] disabled
10277 19:27:59.089007 <6>[ 1.074116] SuperH (H)SCI(F) driver initialized
10278 19:27:59.092459 <6>[ 1.079407] msm_serial: driver initialized
10279 19:27:59.106639 <6>[ 1.088426] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10280 19:27:59.116156 <6>[ 1.096970] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10281 19:27:59.122864 <6>[ 1.105517] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10282 19:27:59.133145 <6>[ 1.114144] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10283 19:27:59.142733 <6>[ 1.122850] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10284 19:27:59.149508 <6>[ 1.131563] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10285 19:27:59.159470 <6>[ 1.140104] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10286 19:27:59.165980 <6>[ 1.148902] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10287 19:27:59.175784 <6>[ 1.157445] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10288 19:27:59.187981 <6>[ 1.173175] loop: module loaded
10289 19:27:59.194778 <6>[ 1.179073] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10290 19:27:59.217146 <4>[ 1.202171] mtk-pmic-keys: Failed to locate of_node [id: -1]
10291 19:27:59.223588 <6>[ 1.208964] megasas: 07.719.03.00-rc1
10292 19:27:59.233153 <6>[ 1.218592] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10293 19:27:59.241888 <6>[ 1.227086] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10294 19:27:59.258661 <6>[ 1.243762] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10295 19:27:59.315059 <6>[ 1.293733] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10296 19:27:59.623837 <6>[ 1.609010] Freeing initrd memory: 18332K
10297 19:27:59.635107 <6>[ 1.620524] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10298 19:27:59.646216 <6>[ 1.631673] tun: Universal TUN/TAP device driver, 1.6
10299 19:27:59.649899 <6>[ 1.637774] thunder_xcv, ver 1.0
10300 19:27:59.652789 <6>[ 1.641285] thunder_bgx, ver 1.0
10301 19:27:59.656442 <6>[ 1.644779] nicpf, ver 1.0
10302 19:27:59.667128 <6>[ 1.648845] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10303 19:27:59.669919 <6>[ 1.656321] hns3: Copyright (c) 2017 Huawei Corporation.
10304 19:27:59.676832 <6>[ 1.661914] hclge is initializing
10305 19:27:59.680191 <6>[ 1.665495] e1000: Intel(R) PRO/1000 Network Driver
10306 19:27:59.686938 <6>[ 1.670623] e1000: Copyright (c) 1999-2006 Intel Corporation.
10307 19:27:59.690322 <6>[ 1.676636] e1000e: Intel(R) PRO/1000 Network Driver
10308 19:27:59.696828 <6>[ 1.681851] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10309 19:27:59.703412 <6>[ 1.688036] igb: Intel(R) Gigabit Ethernet Network Driver
10310 19:27:59.710033 <6>[ 1.693685] igb: Copyright (c) 2007-2014 Intel Corporation.
10311 19:27:59.716663 <6>[ 1.699526] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10312 19:27:59.723032 <6>[ 1.706044] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10313 19:27:59.726419 <6>[ 1.712509] sky2: driver version 1.30
10314 19:27:59.733422 <6>[ 1.717545] VFIO - User Level meta-driver version: 0.3
10315 19:27:59.740644 <6>[ 1.725874] usbcore: registered new interface driver usb-storage
10316 19:27:59.747021 <6>[ 1.732324] usbcore: registered new device driver onboard-usb-hub
10317 19:27:59.756404 <6>[ 1.741553] mt6397-rtc mt6359-rtc: registered as rtc0
10318 19:27:59.766245 <6>[ 1.747018] mt6397-rtc mt6359-rtc: setting system clock to 2024-04-18T19:27:59 UTC (1713468479)
10319 19:27:59.769542 <6>[ 1.756605] i2c_dev: i2c /dev entries driver
10320 19:27:59.786771 <6>[ 1.768560] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10321 19:27:59.792944 <4>[ 1.777306] cpu cpu0: supply cpu not found, using dummy regulator
10322 19:27:59.799849 <4>[ 1.783753] cpu cpu1: supply cpu not found, using dummy regulator
10323 19:27:59.806217 <4>[ 1.790154] cpu cpu2: supply cpu not found, using dummy regulator
10324 19:27:59.812993 <4>[ 1.796558] cpu cpu3: supply cpu not found, using dummy regulator
10325 19:27:59.820084 <4>[ 1.802975] cpu cpu4: supply cpu not found, using dummy regulator
10326 19:27:59.826208 <4>[ 1.809375] cpu cpu5: supply cpu not found, using dummy regulator
10327 19:27:59.833189 <4>[ 1.815775] cpu cpu6: supply cpu not found, using dummy regulator
10328 19:27:59.839453 <4>[ 1.822186] cpu cpu7: supply cpu not found, using dummy regulator
10329 19:27:59.858513 <6>[ 1.843820] cpu cpu0: EM: created perf domain
10330 19:27:59.861758 <6>[ 1.848735] cpu cpu4: EM: created perf domain
10331 19:27:59.868830 <6>[ 1.854287] sdhci: Secure Digital Host Controller Interface driver
10332 19:27:59.875642 <6>[ 1.860719] sdhci: Copyright(c) Pierre Ossman
10333 19:27:59.882290 <6>[ 1.865644] Synopsys Designware Multimedia Card Interface Driver
10334 19:27:59.889112 <6>[ 1.872248] sdhci-pltfm: SDHCI platform and OF driver helper
10335 19:27:59.892401 <6>[ 1.872378] mmc0: CQHCI version 5.10
10336 19:27:59.898952 <6>[ 1.882291] ledtrig-cpu: registered to indicate activity on CPUs
10337 19:27:59.905395 <6>[ 1.889356] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10338 19:27:59.912015 <6>[ 1.896381] usbcore: registered new interface driver usbhid
10339 19:27:59.915719 <6>[ 1.902207] usbhid: USB HID core driver
10340 19:27:59.922105 <6>[ 1.906417] spi_master spi0: will run message pump with realtime priority
10341 19:27:59.965648 <6>[ 1.944431] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10342 19:27:59.984863 <6>[ 1.960405] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10343 19:27:59.988561 <6>[ 1.973960] mmc0: Command Queue Engine enabled
10344 19:27:59.995107 <6>[ 1.978776] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10345 19:28:00.001863 <6>[ 1.986242] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10346 19:28:00.004930 <6>[ 1.986278] cros-ec-spi spi0.0: Chrome EC device registered
10347 19:28:00.011362 <6>[ 1.995074] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10348 19:28:00.019310 <6>[ 2.004601] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10349 19:28:00.025939 <6>[ 2.010571] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10350 19:28:00.032808 <6>[ 2.016770] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10351 19:28:00.050925 <6>[ 2.033040] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10352 19:28:00.058359 <6>[ 2.043743] NET: Registered PF_PACKET protocol family
10353 19:28:00.061667 <6>[ 2.049138] 9pnet: Installing 9P2000 support
10354 19:28:00.068623 <5>[ 2.053702] Key type dns_resolver registered
10355 19:28:00.071892 <6>[ 2.058704] registered taskstats version 1
10356 19:28:00.078593 <5>[ 2.063085] Loading compiled-in X.509 certificates
10357 19:28:00.108427 <4>[ 2.086705] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10358 19:28:00.117803 <4>[ 2.097515] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10359 19:28:00.124757 <3>[ 2.108135] debugfs: File 'uA_load' in directory '/' already present!
10360 19:28:00.131087 <3>[ 2.114860] debugfs: File 'min_uV' in directory '/' already present!
10361 19:28:00.137690 <3>[ 2.121472] debugfs: File 'max_uV' in directory '/' already present!
10362 19:28:00.144304 <3>[ 2.128080] debugfs: File 'constraint_flags' in directory '/' already present!
10363 19:28:00.155913 <3>[ 2.137923] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10364 19:28:00.168662 <6>[ 2.154038] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10365 19:28:00.175378 <6>[ 2.160901] xhci-mtk 11200000.usb: xHCI Host Controller
10366 19:28:00.182590 <6>[ 2.166459] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10367 19:28:00.192264 <6>[ 2.174379] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10368 19:28:00.199048 <6>[ 2.183806] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10369 19:28:00.205701 <6>[ 2.189862] xhci-mtk 11200000.usb: xHCI Host Controller
10370 19:28:00.212536 <6>[ 2.195340] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10371 19:28:00.219057 <6>[ 2.202990] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10372 19:28:00.225549 <6>[ 2.210757] hub 1-0:1.0: USB hub found
10373 19:28:00.229255 <6>[ 2.214798] hub 1-0:1.0: 1 port detected
10374 19:28:00.235642 <6>[ 2.219078] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10375 19:28:00.242342 <6>[ 2.227844] hub 2-0:1.0: USB hub found
10376 19:28:00.245666 <6>[ 2.231864] hub 2-0:1.0: 1 port detected
10377 19:28:00.253237 <6>[ 2.238692] mtk-msdc 11f70000.mmc: Got CD GPIO
10378 19:28:00.265276 <6>[ 2.247505] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10379 19:28:00.272158 <6>[ 2.255540] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10380 19:28:00.281780 <4>[ 2.263429] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10381 19:28:00.291743 <6>[ 2.272958] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10382 19:28:00.298337 <6>[ 2.281034] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10383 19:28:00.305142 <6>[ 2.289058] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10384 19:28:00.314921 <6>[ 2.296977] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10385 19:28:00.321541 <6>[ 2.304795] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10386 19:28:00.331467 <6>[ 2.312612] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10387 19:28:00.341397 <6>[ 2.322972] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10388 19:28:00.348030 <6>[ 2.331357] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10389 19:28:00.357978 <6>[ 2.339710] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10390 19:28:00.364610 <6>[ 2.348047] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10391 19:28:00.374536 <6>[ 2.356385] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10392 19:28:00.381053 <6>[ 2.364723] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10393 19:28:00.391301 <6>[ 2.373061] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10394 19:28:00.400922 <6>[ 2.381397] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10395 19:28:00.407612 <6>[ 2.389735] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10396 19:28:00.417870 <6>[ 2.398071] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10397 19:28:00.423839 <6>[ 2.406409] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10398 19:28:00.433899 <6>[ 2.414746] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10399 19:28:00.440418 <6>[ 2.423083] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10400 19:28:00.450242 <6>[ 2.431419] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10401 19:28:00.457183 <6>[ 2.439758] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10402 19:28:00.463733 <6>[ 2.448486] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10403 19:28:00.470162 <6>[ 2.455607] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10404 19:28:00.477375 <6>[ 2.462351] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10405 19:28:00.487246 <6>[ 2.469111] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10406 19:28:00.493548 <6>[ 2.476014] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10407 19:28:00.500361 <6>[ 2.482853] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10408 19:28:00.510193 <6>[ 2.491991] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10409 19:28:00.520326 <6>[ 2.501110] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10410 19:28:00.530913 <6>[ 2.510405] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10411 19:28:00.540108 <6>[ 2.519871] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10412 19:28:00.546769 <6>[ 2.529337] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10413 19:28:00.556707 <6>[ 2.538456] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10414 19:28:00.566713 <6>[ 2.547924] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10415 19:28:00.576447 <6>[ 2.557042] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10416 19:28:00.585976 <6>[ 2.566337] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10417 19:28:00.596294 <6>[ 2.576498] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10418 19:28:00.605739 <6>[ 2.588008] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10419 19:28:00.612801 <6>[ 2.597676] Trying to probe devices needed for running init ...
10420 19:28:00.653989 <6>[ 2.635973] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10421 19:28:00.808195 <6>[ 2.793692] hub 1-1:1.0: USB hub found
10422 19:28:00.811530 <6>[ 2.798189] hub 1-1:1.0: 4 ports detected
10423 19:28:00.820829 <6>[ 2.806101] hub 1-1:1.0: USB hub found
10424 19:28:00.823946 <6>[ 2.810445] hub 1-1:1.0: 4 ports detected
10425 19:28:00.933958 <6>[ 2.916281] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10426 19:28:00.959470 <6>[ 2.944707] hub 2-1:1.0: USB hub found
10427 19:28:00.962789 <6>[ 2.949124] hub 2-1:1.0: 3 ports detected
10428 19:28:00.971891 <6>[ 2.957176] hub 2-1:1.0: USB hub found
10429 19:28:00.974950 <6>[ 2.961689] hub 2-1:1.0: 3 ports detected
10430 19:28:01.149811 <6>[ 3.131993] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10431 19:28:01.281843 <6>[ 3.267329] hub 1-1.4:1.0: USB hub found
10432 19:28:01.285062 <6>[ 3.271919] hub 1-1.4:1.0: 2 ports detected
10433 19:28:01.293471 <6>[ 3.278904] hub 1-1.4:1.0: USB hub found
10434 19:28:01.296673 <6>[ 3.283448] hub 1-1.4:1.0: 2 ports detected
10435 19:28:01.362230 <6>[ 3.344121] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10436 19:28:01.593629 <6>[ 3.576014] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10437 19:28:01.785866 <6>[ 3.767988] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10438 19:28:12.910754 <6>[ 14.901014] ALSA device list:
10439 19:28:12.917611 <6>[ 14.904306] No soundcards found.
10440 19:28:12.925089 <6>[ 14.912085] Freeing unused kernel memory: 8448K
10441 19:28:12.928240 <6>[ 14.917735] Run /init as init process
10442 19:28:12.938905 Loading, please wait...
10443 19:28:12.966421 Starting systemd-udevd version 252.22-1~deb12u1
10444 19:28:12.966513
10445 19:28:13.252655 <6>[ 15.236394] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10446 19:28:13.265709 <6>[ 15.249191] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10447 19:28:13.268782 <6>[ 15.253973] remoteproc remoteproc0: scp is available
10448 19:28:13.278840 <6>[ 15.256916] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10449 19:28:13.285690 <6>[ 15.262175] remoteproc remoteproc0: powering up scp
10450 19:28:13.292088 <3>[ 15.264427] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10451 19:28:13.298642 <3>[ 15.264441] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10452 19:28:13.308765 <3>[ 15.264451] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10453 19:28:13.318645 <6>[ 15.270766] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10454 19:28:13.325112 <6>[ 15.275888] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10455 19:28:13.331810 <6>[ 15.275925] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10456 19:28:13.338287 <6>[ 15.276034] usbcore: registered new device driver r8152-cfgselector
10457 19:28:13.345185 <3>[ 15.276260] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10458 19:28:13.355048 <3>[ 15.276275] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10459 19:28:13.361761 <3>[ 15.276278] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10460 19:28:13.371403 <3>[ 15.276284] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10461 19:28:13.377946 <3>[ 15.276289] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10462 19:28:13.385219 <3>[ 15.284246] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10463 19:28:13.395331 <4>[ 15.290347] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10464 19:28:13.401723 <4>[ 15.294342] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10465 19:28:13.408745 <6>[ 15.303539] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10466 19:28:13.415424 <3>[ 15.312801] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10467 19:28:13.422128 <6>[ 15.329204] mc: Linux media interface: v0.10
10468 19:28:13.429092 <3>[ 15.329586] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10469 19:28:13.438511 <4>[ 15.347553] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10470 19:28:13.441959 <4>[ 15.347553] Fallback method does not support PEC.
10471 19:28:13.452267 <3>[ 15.353882] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10472 19:28:13.458649 <3>[ 15.377388] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10473 19:28:13.468397 <3>[ 15.378328] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10474 19:28:13.478667 <6>[ 15.404952] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10475 19:28:13.488105 <3>[ 15.406180] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10476 19:28:13.494738 <3>[ 15.408914] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10477 19:28:13.501660 <6>[ 15.409282] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10478 19:28:13.508049 <6>[ 15.409291] pci_bus 0000:00: root bus resource [bus 00-ff]
10479 19:28:13.514788 <6>[ 15.409298] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10480 19:28:13.524416 <6>[ 15.409302] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10481 19:28:13.531094 <6>[ 15.409343] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10482 19:28:13.537506 <6>[ 15.409363] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10483 19:28:13.544418 <6>[ 15.409441] pci 0000:00:00.0: supports D1 D2
10484 19:28:13.551447 <6>[ 15.409444] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10485 19:28:13.557454 <6>[ 15.410997] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10486 19:28:13.564386 <6>[ 15.411117] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10487 19:28:13.570653 <6>[ 15.411151] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10488 19:28:13.577731 <6>[ 15.411171] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10489 19:28:13.587813 <6>[ 15.411189] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10490 19:28:13.590532 <6>[ 15.411306] pci 0000:01:00.0: supports D1 D2
10491 19:28:13.597267 <6>[ 15.411309] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10492 19:28:13.607251 <6>[ 15.413701] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10493 19:28:13.613887 <6>[ 15.417765] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10494 19:28:13.620771 <6>[ 15.417772] remoteproc remoteproc0: remote processor scp is now up
10495 19:28:13.630682 <6>[ 15.417794] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10496 19:28:13.637171 <6>[ 15.419775] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10497 19:28:13.643731 <6>[ 15.419808] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10498 19:28:13.650183 <6>[ 15.419816] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10499 19:28:13.660215 <6>[ 15.419831] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10500 19:28:13.666993 <6>[ 15.419848] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10501 19:28:13.676966 <6>[ 15.419865] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10502 19:28:13.679916 <6>[ 15.419883] pci 0000:00:00.0: PCI bridge to [bus 01]
10503 19:28:13.689975 <6>[ 15.419892] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10504 19:28:13.696528 <6>[ 15.420071] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10505 19:28:13.703163 <6>[ 15.420826] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10506 19:28:13.712941 <3>[ 15.421191] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10507 19:28:13.719709 <3>[ 15.421202] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10508 19:28:13.726177 <6>[ 15.421262] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10509 19:28:13.733170 <6>[ 15.421826] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10510 19:28:13.742812 <6>[ 15.421847] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10511 19:28:13.749278 <4>[ 15.444536] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10512 19:28:13.759090 <3>[ 15.451685] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10513 19:28:13.765886 <3>[ 15.451771] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10514 19:28:13.772219 <6>[ 15.453050] videodev: Linux video capture interface: v2.00
10515 19:28:13.779114 <4>[ 15.459840] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10516 19:28:13.788790 <5>[ 15.471218] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10517 19:28:13.795573 <6>[ 15.471535] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10518 19:28:13.805204 <6>[ 15.473821] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10519 19:28:13.808699 <6>[ 15.494270] Bluetooth: Core ver 2.22
10520 19:28:13.815411 <5>[ 15.513772] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10521 19:28:13.821770 <6>[ 15.516533] NET: Registered PF_BLUETOOTH protocol family
10522 19:28:13.828621 <5>[ 15.522930] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10523 19:28:13.834940 <6>[ 15.523290] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10524 19:28:13.848290 <6>[ 15.524426] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10525 19:28:13.854700 <6>[ 15.524521] usbcore: registered new interface driver uvcvideo
10526 19:28:13.861400 <6>[ 15.530166] Bluetooth: HCI device and connection manager initialized
10527 19:28:13.871303 <4>[ 15.534767] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10528 19:28:13.874741 <6>[ 15.535854] r8152 2-1.3:1.0 eth0: v1.12.13
10529 19:28:13.881159 <6>[ 15.535891] usbcore: registered new interface driver r8152
10530 19:28:13.884665 <6>[ 15.541568] Bluetooth: HCI socket layer initialized
10531 19:28:13.891486 <6>[ 15.549811] cfg80211: failed to load regulatory.db
10532 19:28:13.894592 <6>[ 15.556066] Bluetooth: L2CAP socket layer initialized
10533 19:28:13.901220 <6>[ 15.557622] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10534 19:28:13.907540 <6>[ 15.563665] usbcore: registered new interface driver cdc_ether
10535 19:28:13.914400 <6>[ 15.571016] Bluetooth: SCO socket layer initialized
10536 19:28:13.920828 <6>[ 15.589961] usbcore: registered new interface driver r8153_ecm
10537 19:28:13.927903 <6>[ 15.634428] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10538 19:28:13.933956 <6>[ 15.657728] r8152 2-1.3:1.0 enx00e04c6803bd: renamed from eth0
10539 19:28:13.940678 <6>[ 15.659999] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10540 19:28:13.944233 <6>[ 15.660459] usbcore: registered new interface driver btusb
10541 19:28:13.953785 <4>[ 15.661638] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10542 19:28:13.960478 <3>[ 15.661654] Bluetooth: hci0: Failed to load firmware file (-2)
10543 19:28:13.967002 <3>[ 15.661662] Bluetooth: hci0: Failed to set up firmware (-2)
10544 19:28:13.976853 <4>[ 15.661669] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10545 19:28:14.000981 <6>[ 15.988120] mt7921e 0000:01:00.0: ASIC revision: 79610010
10546 19:28:14.102976 <6>[ 16.086751] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10547 19:28:14.106107 <6>[ 16.086751]
10548 19:28:14.121525 Begin: Loading essential drivers ... done.
10549 19:28:14.125124 Begin: Running /scripts/init-premount ... done.
10550 19:28:14.131618 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10551 19:28:14.141572 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10552 19:28:14.144650 Device /sys/class/net/enx00e04c6803bd found
10553 19:28:14.144749 done.
10554 19:28:14.164995 Begin: Waiting up to 180 secs for any network device to become available ... done.
10555 19:28:14.204172 IP-Config: enx00e04c6803bd hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10556 19:28:14.372831 <6>[ 16.356736] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10557 19:28:15.124962 <6>[ 17.111938] r8152 2-1.3:1.0 enx00e04c6803bd: carrier on
10558 19:28:15.236663 <6>[ 17.223905] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10559 19:28:15.260239 IP-Config: no response after 2 secs - giving up
10560 19:28:15.288862 IP-Config: enx00e04c6803bd hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10561 19:28:15.308970 IP-Config: wlp1s0 hardware address 74:4c:a1:92:35:3b mtu 1500 DHCP
10562 19:28:15.985384 IP-Config: enx00e04c6803bd complete (dhcp from 192.168.201.1):
10563 19:28:15.991618 address: 192.168.201.16 broadcast: 192.168.201.255 netmask: 255.255.255.0
10564 19:28:15.998443 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10565 19:28:16.005114 host : mt8192-asurada-spherion-r0-cbg-4
10566 19:28:16.011739 domain : lava-rack
10567 19:28:16.017920 rootserver: 192.168.201.1 rootpath:
10568 19:28:16.018002 filename :
10569 19:28:16.108559 done.
10570 19:28:16.111743 Begin: Running /scripts/nfs-bottom ... done.
10571 19:28:16.128682 Begin: Running /scripts/init-bottom ... done.
10572 19:28:17.441769 <6>[ 19.429239] NET: Registered PF_INET6 protocol family
10573 19:28:17.449112 <6>[ 19.436436] Segment Routing with IPv6
10574 19:28:17.452163 <6>[ 19.440417] In-situ OAM (IOAM) with IPv6
10575 19:28:17.637907 <30>[ 19.599052] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10576 19:28:17.645377 <30>[ 19.632664] systemd[1]: Detected architecture arm64.
10577 19:28:17.651270
10578 19:28:17.655000 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10579 19:28:17.655082
10580 19:28:17.655147
10581 19:28:17.680837 <30>[ 19.668343] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10582 19:28:18.635748 <30>[ 20.619805] systemd[1]: Queued start job for default target graphical.target.
10583 19:28:18.676874 <30>[ 20.661245] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10584 19:28:18.683336 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10585 19:28:18.683418
10586 19:28:18.705864 <30>[ 20.689886] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10587 19:28:18.715424 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10588 19:28:18.715507
10589 19:28:18.733377 <30>[ 20.717805] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10590 19:28:18.743791 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10591 19:28:18.743876
10592 19:28:18.761953 <30>[ 20.746198] systemd[1]: Created slice user.slice - User and Session Slice.
10593 19:28:18.768553 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10594 19:28:18.768635
10595 19:28:18.792254 <30>[ 20.772884] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10596 19:28:18.798742 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10597 19:28:18.798825
10598 19:28:18.819391 <30>[ 20.800308] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10599 19:28:18.825701 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10600 19:28:18.825783
10601 19:28:18.854081 <30>[ 20.828639] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10602 19:28:18.864533 <30>[ 20.848562] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10603 19:28:18.870737 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10604 19:28:18.870818
10605 19:28:18.888071 <30>[ 20.872376] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10606 19:28:18.894774 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10607 19:28:18.898277
10608 19:28:18.916101 <30>[ 20.900464] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10609 19:28:18.926317 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10610 19:28:18.926400
10611 19:28:18.941129 <30>[ 20.928555] systemd[1]: Reached target paths.target - Path Units.
10612 19:28:18.947879 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10613 19:28:18.951111
10614 19:28:18.968049 <30>[ 20.952334] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10615 19:28:18.974702 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10616 19:28:18.974785
10617 19:28:18.988559 <30>[ 20.975990] systemd[1]: Reached target slices.target - Slice Units.
10618 19:28:18.998600 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10619 19:28:18.998682
10620 19:28:19.013024 <30>[ 21.000480] systemd[1]: Reached target swap.target - Swaps.
10621 19:28:19.019658 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10622 19:28:19.019743
10623 19:28:19.040666 <30>[ 21.024501] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10624 19:28:19.050116 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10625 19:28:19.050201
10626 19:28:19.068208 <30>[ 21.052455] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10627 19:28:19.077935 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10628 19:28:19.078019
10629 19:28:19.098363 <30>[ 21.082527] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10630 19:28:19.108367 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10631 19:28:19.108452
10632 19:28:19.125231 <30>[ 21.109186] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10633 19:28:19.134654 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10634 19:28:19.134739
10635 19:28:19.153057 <30>[ 21.137162] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10636 19:28:19.159658 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10637 19:28:19.159744
10638 19:28:19.182048 <30>[ 21.166253] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10639 19:28:19.191783 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10640 19:28:19.191868
10641 19:28:19.211113 <30>[ 21.195173] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10642 19:28:19.220964 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10643 19:28:19.221055
10644 19:28:19.236239 <30>[ 21.220505] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10645 19:28:19.245968 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10646 19:28:19.246079
10647 19:28:19.304159 <30>[ 21.288210] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10648 19:28:19.310345 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10649 19:28:19.310442
10650 19:28:19.332692 <30>[ 21.317050] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10651 19:28:19.339189 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10652 19:28:19.339286
10653 19:28:19.367864 <30>[ 21.352053] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10654 19:28:19.374484 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10655 19:28:19.374570
10656 19:28:19.402623 <30>[ 21.380282] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10657 19:28:19.416307 <30>[ 21.400494] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10658 19:28:19.425837 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10659 19:28:19.425921
10660 19:28:19.480284 <30>[ 21.464714] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10661 19:28:19.487348 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10662 19:28:19.487434
10663 19:28:19.517428 <30>[ 21.501530] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10664 19:28:19.523878 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10665 19:28:19.523962
10666 19:28:19.549579 <30>[ 21.533936] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10667 19:28:19.559555 Startin<6>[ 21.543095] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10668 19:28:19.566284 g [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10669 19:28:19.566366
10670 19:28:19.593292 <30>[ 21.577712] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10671 19:28:19.603027 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10672 19:28:19.603111
10673 19:28:19.625206 <30>[ 21.609667] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10674 19:28:19.632091 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10675 19:28:19.632178
10676 19:28:19.657253 <30>[ 21.641629] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10677 19:28:19.663755 Startin<6>[ 21.650473] fuse: init (API version 7.37)
10678 19:28:19.670380 g [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10679 19:28:19.670463
10680 19:28:19.701617 <30>[ 21.685855] systemd[1]: Starting systemd-journald.service - Journal Service...
10681 19:28:19.708230 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10682 19:28:19.708314
10683 19:28:19.760955 <30>[ 21.745130] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10684 19:28:19.767608 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10685 19:28:19.767718
10686 19:28:19.797260 <30>[ 21.778129] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10687 19:28:19.803505 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10688 19:28:19.803588
10689 19:28:19.827702 <3>[ 21.811940] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10690 19:28:19.837702 <30>[ 21.812185] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10691 19:28:19.844334 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10692 19:28:19.844413
10693 19:28:19.859224 <3>[ 21.843774] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10694 19:28:19.870935 <30>[ 21.855435] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10695 19:28:19.878136 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10696 19:28:19.878224
10697 19:28:19.904309 <3>[ 21.888373] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10698 19:28:19.910548 <30>[ 21.888650] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10699 19:28:19.920660 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10700 19:28:19.920764
10701 19:28:19.940395 <30>[ 21.924688] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10702 19:28:19.950434 <3>[ 21.925593] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10703 19:28:19.956840 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10704 19:28:19.956930
10705 19:28:19.976994 <30>[ 21.960811] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10706 19:28:19.983380 <3>[ 21.961857] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10707 19:28:19.993460 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10708 19:28:19.993545
10709 19:28:20.012464 <30>[ 21.996763] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10710 19:28:20.022732 <3>[ 21.999421] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10711 19:28:20.029094 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10712 19:28:20.029173
10713 19:28:20.049219 <30>[ 22.033218] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10714 19:28:20.055840 <3>[ 22.036644] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10715 19:28:20.065666 <30>[ 22.041171] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10716 19:28:20.072624 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10717 19:28:20.072710
10718 19:28:20.091512 <3>[ 22.075878] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10719 19:28:20.098153 <30>[ 22.077354] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10720 19:28:20.107921 <30>[ 22.092526] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10721 19:28:20.115140 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10722 19:28:20.115219
10723 19:28:20.128692 <3>[ 22.113424] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10724 19:28:20.140337 <30>[ 22.124834] systemd[1]: modprobe@drm.service: Deactivated successfully.
10725 19:28:20.147455 <30>[ 22.132287] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10726 19:28:20.163929 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Mod<3>[ 22.147136] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10727 19:28:20.164017 ule drm.
10728 19:28:20.164081
10729 19:28:20.184767 <30>[ 22.168809] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10730 19:28:20.191936 <30>[ 22.176798] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10731 19:28:20.201943 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10732 19:28:20.202033
10733 19:28:20.220464 <30>[ 22.204899] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10734 19:28:20.226869 <30>[ 22.212288] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10735 19:28:20.236792 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10736 19:28:20.236875
10737 19:28:20.252159 <30>[ 22.236621] systemd[1]: Started systemd-journald.service - Journal Service.
10738 19:28:20.258706 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10739 19:28:20.258790
10740 19:28:20.276444 <4>[ 22.254281] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10741 19:28:20.286403 <3>[ 22.269935] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10742 19:28:20.293336 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10743 19:28:20.293444
10744 19:28:20.313258 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10745 19:28:20.313346
10746 19:28:20.332796 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10747 19:28:20.332884
10748 19:28:20.352374 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10749 19:28:20.352461
10750 19:28:20.372737 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10751 19:28:20.372820
10752 19:28:20.392567 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10753 19:28:20.392647
10754 19:28:20.460097 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10755 19:28:20.460214
10756 19:28:20.485036 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10757 19:28:20.485123
10758 19:28:20.552911 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10759 19:28:20.553054
10760 19:28:20.578571 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10761 19:28:20.578659
10762 19:28:20.604229 <46>[ 22.588464] systemd-journald[306]: Received client request to flush runtime journal.
10763 19:28:20.610577 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10764 19:28:20.610661
10765 19:28:20.681748 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10766 19:28:20.681875
10767 19:28:20.927407 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10768 19:28:20.927554
10769 19:28:20.948650 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10770 19:28:20.948749
10771 19:28:20.969269 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10772 19:28:20.969363
10773 19:28:20.989904 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10774 19:28:20.989995
10775 19:28:21.756995 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10776 19:28:21.757184
10777 19:28:21.808880 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10778 19:28:21.808995
10779 19:28:22.063447 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10780 19:28:22.063650
10781 19:28:22.149394 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10782 19:28:22.149539
10783 19:28:22.168296 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10784 19:28:22.168385
10785 19:28:22.187550 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10786 19:28:22.187662
10787 19:28:22.232298 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10788 19:28:22.232398
10789 19:28:22.258688 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10790 19:28:22.258789
10791 19:28:22.451164 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10792 19:28:22.451321
10793 19:28:22.497559 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10794 19:28:22.497679
10795 19:28:22.562894 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10796 19:28:22.563035
10797 19:28:22.795736 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10798 19:28:22.795893
10799 19:28:22.870698 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10800 19:28:22.870832
10801 19:28:22.901089 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10802 19:28:22.901184
10803 19:28:23.010913 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10804 19:28:23.011059
10805 19:28:23.032147 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10806 19:28:23.032261
10807 19:28:23.072205 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10808 19:28:23.072349
10809 19:28:23.098441 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10810 19:28:23.098556
10811 19:28:23.115618 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10812 19:28:23.115756
10813 19:28:23.145187 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10814 19:28:23.145316
10815 19:28:23.167220 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10816 19:28:23.167323
10817 19:28:23.188150 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10818 19:28:23.188298
10819 19:28:23.212325 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10820 19:28:23.212420
10821 19:28:23.235927 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10822 19:28:23.236024
10823 19:28:23.255803 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10824 19:28:23.255894
10825 19:28:23.277835 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
10826 19:28:23.277948
10827 19:28:23.297057 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
10828 19:28:23.297144
10829 19:28:23.314592 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
10830 19:28:23.314677
10831 19:28:23.336218 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
10832 19:28:23.336343
10833 19:28:23.358193 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10834 19:28:23.358314
10835 19:28:23.375769 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10836 19:28:23.375859
10837 19:28:23.412701 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10838 19:28:23.412800
10839 19:28:23.434521 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10840 19:28:23.434634
10841 19:28:23.458362 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10842 19:28:23.458454
10843 19:28:23.477841 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10844 19:28:23.477951
10845 19:28:23.529165 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10846 19:28:23.529279
10847 19:28:23.562367 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
10848 19:28:23.562481
10849 19:28:23.674969 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10850 19:28:23.675107
10851 19:28:23.703968 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10852 19:28:23.704064
10853 19:28:23.729361 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10854 19:28:23.729445
10855 19:28:23.852930 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10856 19:28:23.853104
10857 19:28:23.868574 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10858 19:28:23.868661
10859 19:28:23.888822 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
10860 19:28:23.888907
10861 19:28:23.920101 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10862 19:28:23.920190
10863 19:28:23.934179 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10864 19:28:23.934299
10865 19:28:23.949714 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10866 19:28:23.949802
10867 19:28:23.977001 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10868 19:28:23.977096
10869 19:28:24.017456 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
10870 19:28:24.017544
10871 19:28:24.047391 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
10872 19:28:24.047488
10873 19:28:24.067802 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
10874 19:28:24.067889
10875 19:28:24.127408 Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
10876 19:28:24.127515
10877 19:28:24.151732 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
10878 19:28:24.151831
10879 19:28:24.203919 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
10880 19:28:24.204027
10881 19:28:24.225871 [[0;32m OK [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
10882 19:28:24.225988
10883 19:28:24.311335
10884 19:28:24.311495
10885 19:28:24.314478 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
10886 19:28:24.314561
10887 19:28:24.317676 debian-bookworm-arm64 login: root (automatic login)
10888 19:28:24.317759
10889 19:28:24.317823
10890 19:28:24.564752 Linux debian-bookworm-arm64 6.1.86-cip19 #1 SMP PREEMPT Thu Apr 18 19:05:54 UTC 2024 aarch64
10891 19:28:24.564933
10892 19:28:24.570938 The programs included with the Debian GNU/Linux system are free software;
10893 19:28:24.578141 the exact distribution terms for each program are described in the
10894 19:28:24.581303 individual files in /usr/share/doc/*/copyright.
10895 19:28:24.581386
10896 19:28:24.587394 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10897 19:28:24.590865 permitted by applicable law.
10898 19:28:25.593159 Matched prompt #10: / #
10900 19:28:25.593446 Setting prompt string to ['/ #']
10901 19:28:25.593539 end: 2.2.5.1 login-action (duration 00:00:28) [common]
10903 19:28:25.593732 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
10904 19:28:25.593817 start: 2.2.6 expect-shell-connection (timeout 00:03:34) [common]
10905 19:28:25.593885 Setting prompt string to ['/ #']
10906 19:28:25.593945 Forcing a shell prompt, looking for ['/ #']
10908 19:28:25.644197 / #
10909 19:28:25.644302 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10910 19:28:25.644374 Waiting using forced prompt support (timeout 00:02:30)
10911 19:28:25.649350
10912 19:28:25.649623 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10913 19:28:25.649718 start: 2.2.7 export-device-env (timeout 00:03:34) [common]
10915 19:28:25.750063 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/13420409/extract-nfsrootfs-jxo16__9'
10916 19:28:25.755572 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/13420409/extract-nfsrootfs-jxo16__9'
10918 19:28:25.856036 / # export NFS_SERVER_IP='192.168.201.1'
10919 19:28:25.861278 export NFS_SERVER_IP='192.168.201.1'
10920 19:28:25.861559 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10921 19:28:25.861661 end: 2.2 depthcharge-retry (duration 00:01:26) [common]
10922 19:28:25.861752 end: 2 depthcharge-action (duration 00:01:26) [common]
10923 19:28:25.861843 start: 3 lava-test-retry (timeout 00:07:55) [common]
10924 19:28:25.861968 start: 3.1 lava-test-shell (timeout 00:07:55) [common]
10925 19:28:25.862073 Using namespace: common
10927 19:28:25.962360 / # #
10928 19:28:25.962535 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10929 19:28:25.967490 #
10930 19:28:25.967755 Using /lava-13420409
10932 19:28:26.068033 / # export SHELL=/bin/bash
10933 19:28:26.073001 export SHELL=/bin/bash
10935 19:28:26.173529 / # . /lava-13420409/environment
10936 19:28:26.178953 . /lava-13420409/environment
10938 19:28:26.283676 / # /lava-13420409/bin/lava-test-runner /lava-13420409/0
10939 19:28:26.283861 Test shell timeout: 10s (minimum of the action and connection timeout)
10940 19:28:26.288905 /lava-13420409/bin/lava-test-runner /lava-13420409/0
10941 19:28:26.506841 + export TESTRUN_ID=0_timesync-off
10942 19:28:26.509756 + TESTRUN_ID=0_timesync-off
10943 19:28:26.513064 + cd /lava-13420409/0/tests/0_timesync-off
10944 19:28:26.516280 ++ cat uuid
10945 19:28:26.516388 + UUID=13420409_1.6.2.3.1
10946 19:28:26.519546 + set +x
10947 19:28:26.523109 <LAVA_SIGNAL_STARTRUN 0_timesync-off 13420409_1.6.2.3.1>
10948 19:28:26.523397 Received signal: <STARTRUN> 0_timesync-off 13420409_1.6.2.3.1
10949 19:28:26.523496 Starting test lava.0_timesync-off (13420409_1.6.2.3.1)
10950 19:28:26.523617 Skipping test definition patterns.
10951 19:28:26.526032 + systemctl stop systemd-timesyncd
10952 19:28:26.594865 + set +x
10953 19:28:26.598498 <LAVA_SIGNAL_ENDRUN 0_timesync-off 13420409_1.6.2.3.1>
10954 19:28:26.598788 Received signal: <ENDRUN> 0_timesync-off 13420409_1.6.2.3.1
10955 19:28:26.598904 Ending use of test pattern.
10956 19:28:26.598997 Ending test lava.0_timesync-off (13420409_1.6.2.3.1), duration 0.08
10958 19:28:26.651482 + export TESTRUN_ID=1_kselftest-tpm2
10959 19:28:26.654814 + TESTRUN_ID=1_kselftest-tpm2
10960 19:28:26.661631 + cd /lava-13420409/0/tests/1_kselftest-tpm2
10961 19:28:26.661742 ++ cat uuid
10962 19:28:26.664602 + UUID=13420409_1.6.2.3.5
10963 19:28:26.664705 + set +x
10964 19:28:26.667921 <LAVA_SIGNAL_STARTRUN 1_kselftest-tpm2 13420409_1.6.2.3.5>
10965 19:28:26.668199 Received signal: <STARTRUN> 1_kselftest-tpm2 13420409_1.6.2.3.5
10966 19:28:26.668300 Starting test lava.1_kselftest-tpm2 (13420409_1.6.2.3.5)
10967 19:28:26.668415 Skipping test definition patterns.
10968 19:28:26.671329 + cd ./automated/linux/kselftest/
10969 19:28:26.697623 + ./kselftest.sh -c tpm2 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
10970 19:28:26.718983 INFO: install_deps skipped
10971 19:28:27.199347 --2024-04-18 19:28:27-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
10972 19:28:27.205666 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
10973 19:28:27.334300 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
10974 19:28:27.467464 HTTP request sent, awaiting response... 200 OK
10975 19:28:27.470923 Length: 1651832 (1.6M) [application/octet-stream]
10976 19:28:27.474082 Saving to: 'kselftest_armhf.tar.gz'
10977 19:28:27.474165
10978 19:28:27.474231
10979 19:28:27.733601 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
10980 19:28:27.999831 kselftest_armhf.tar 3%[ ] 49.22K 182KB/s
10981 19:28:28.313602 kselftest_armhf.tar 13%[=> ] 217.50K 401KB/s
10982 19:28:28.532242 kselftest_armhf.tar 50%[=========> ] 814.23K 946KB/s
10983 19:28:28.538633 kselftest_armhf.tar 51%[=========> ] 834.03K 770KB/s
10984 19:28:28.545264 kselftest_armhf.tar 100%[===================>] 1.58M 1.44MB/s in 1.1s
10985 19:28:28.545350
10986 19:28:28.691492 2024-04-18 19:28:28 (1.44 MB/s) - 'kselftest_armhf.tar.gz' saved [1651832/1651832]
10987 19:28:28.691642
10988 19:28:32.157369 skiplist:
10989 19:28:32.160714 ========================================
10990 19:28:32.163675 ========================================
10991 19:28:32.198756 tpm2:test_smoke.sh
10992 19:28:32.202074 tpm2:test_space.sh
10993 19:28:32.216529 ============== Tests to run ===============
10994 19:28:32.216707 tpm2:test_smoke.sh
10995 19:28:32.219711 tpm2:test_space.sh
10996 19:28:32.223276 ===========End Tests to run ===============
10997 19:28:32.223372 shardfile-tpm2 pass
10998 19:28:32.314531 <12>[ 34.303751] kselftest: Running tests in tpm2
10999 19:28:32.323823 TAP version 13
11000 19:28:32.336318 1..2
11001 19:28:32.361936 # selftests: tpm2: test_smoke.sh
11002 19:28:34.134529 # test_read_partial_overwrite (tpm2_tests.SmokeTest.test_read_partial_overwrite) ... ERROR
11003 19:28:34.140817 # test_read_partial_resp (tpm2_tests.SmokeTest.test_read_partial_resp) ... ERROR
11004 19:28:34.147707 # Exception ignored in: <function Client.__del__ at 0xffff8b98ccc0>
11005 19:28:34.150808 # Traceback (most recent call last):
11006 19:28:34.161109 # File "/lava-13420409/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11007 19:28:34.161203 # if self.tpm:
11008 19:28:34.164064 # ^^^^^^^^
11009 19:28:34.167525 # AttributeError: 'Client' object has no attribute 'tpm'
11010 19:28:34.173955 # test_seal_with_auth (tpm2_tests.SmokeTest.test_seal_with_auth) ... ERROR
11011 19:28:34.180719 # Exception ignored in: <function Client.__del__ at 0xffff8b98ccc0>
11012 19:28:34.184047 # Traceback (most recent call last):
11013 19:28:34.193980 # File "/lava-13420409/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11014 19:28:34.194102 # if self.tpm:
11015 19:28:34.197301 # ^^^^^^^^
11016 19:28:34.200678 # AttributeError: 'Client' object has no attribute 'tpm'
11017 19:28:34.207683 # test_seal_with_policy (tpm2_tests.SmokeTest.test_seal_with_policy) ... ERROR
11018 19:28:34.214200 # Exception ignored in: <function Client.__del__ at 0xffff8b98ccc0>
11019 19:28:34.217528 # Traceback (most recent call last):
11020 19:28:34.227496 # File "/lava-13420409/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11021 19:28:34.230441 # if self.tpm:
11022 19:28:34.230515 # ^^^^^^^^
11023 19:28:34.237291 # AttributeError: 'Client' object has no attribute 'tpm'
11024 19:28:34.243821 # test_seal_with_too_long_auth (tpm2_tests.SmokeTest.test_seal_with_too_long_auth) ... ERROR
11025 19:28:34.250603 # Exception ignored in: <function Client.__del__ at 0xffff8b98ccc0>
11026 19:28:34.253927 # Traceback (most recent call last):
11027 19:28:34.263608 # File "/lava-13420409/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11028 19:28:34.267170 # if self.tpm:
11029 19:28:34.267244 # ^^^^^^^^
11030 19:28:34.273573 # AttributeError: 'Client' object has no attribute 'tpm'
11031 19:28:34.280215 # test_send_two_cmds (tpm2_tests.SmokeTest.test_send_two_cmds) ... ERROR
11032 19:28:34.283464 # Exception ignored in: <function Client.__del__ at 0xffff8b98ccc0>
11033 19:28:34.286917 # Traceback (most recent call last):
11034 19:28:34.297044 # File "/lava-13420409/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11035 19:28:34.300604 # if self.tpm:
11036 19:28:34.300677 # ^^^^^^^^
11037 19:28:34.306956 # AttributeError: 'Client' object has no attribute 'tpm'
11038 19:28:34.313712 # test_too_short_cmd (tpm2_tests.SmokeTest.test_too_short_cmd) ... ERROR
11039 19:28:34.320484 # Exception ignored in: <function Client.__del__ at 0xffff8b98ccc0>
11040 19:28:34.323503 # Traceback (most recent call last):
11041 19:28:34.333446 # File "/lava-13420409/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11042 19:28:34.333531 # if self.tpm:
11043 19:28:34.336738 # ^^^^^^^^
11044 19:28:34.340024 # AttributeError: 'Client' object has no attribute 'tpm'
11045 19:28:34.350155 # test_unseal_with_wrong_auth (tpm2_tests.SmokeTest.test_unseal_with_wrong_auth) ... ERROR
11046 19:28:34.353324 # Exception ignored in: <function Client.__del__ at 0xffff8b98ccc0>
11047 19:28:34.356757 # Traceback (most recent call last):
11048 19:28:34.366527 # File "/lava-13420409/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11049 19:28:34.369746 # if self.tpm:
11050 19:28:34.369829 # ^^^^^^^^
11051 19:28:34.376191 # AttributeError: 'Client' object has no attribute 'tpm'
11052 19:28:34.386403 # test_unseal_with_wrong_policy (tpm2_tests.SmokeTest.test_unseal_with_wrong_policy) ... ERROR
11053 19:28:34.390362 # Exception ignored in: <function Client.__del__ at 0xffff8b98ccc0>
11054 19:28:34.394601 # Traceback (most recent call last):
11055 19:28:34.404463 # File "/lava-13420409/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11056 19:28:34.404549 # if self.tpm:
11057 19:28:34.408089 # ^^^^^^^^
11058 19:28:34.411049 # AttributeError: 'Client' object has no attribute 'tpm'
11059 19:28:34.411131 #
11060 19:28:34.417806 # ======================================================================
11061 19:28:34.427919 # ERROR: test_read_partial_overwrite (tpm2_tests.SmokeTest.test_read_partial_overwrite)
11062 19:28:34.434302 # ----------------------------------------------------------------------
11063 19:28:34.437548 # Traceback (most recent call last):
11064 19:28:34.447871 # File "/lava-13420409/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 16, in setUp
11065 19:28:34.451022 # self.root_key = self.client.create_root_key()
11066 19:28:34.454397 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11067 19:28:34.467684 # File "/lava-13420409/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11068 19:28:34.471118 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11069 19:28:34.477534 # ^^^^^^^^^^^^^^^^^^
11070 19:28:34.487554 # File "/lava-13420409/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11071 19:28:34.487636 # raise ProtocolError(cc, rc)
11072 19:28:34.494298 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11073 19:28:34.494372 #
11074 19:28:34.501036 # ======================================================================
11075 19:28:34.507734 # ERROR: test_read_partial_resp (tpm2_tests.SmokeTest.test_read_partial_resp)
11076 19:28:34.514256 # ----------------------------------------------------------------------
11077 19:28:34.517555 # Traceback (most recent call last):
11078 19:28:34.527405 # File "/lava-13420409/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11079 19:28:34.530902 # self.client = tpm2.Client()
11080 19:28:34.534305 # ^^^^^^^^^^^^^
11081 19:28:34.544030 # File "/lava-13420409/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11082 19:28:34.550566 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11083 19:28:34.554019 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11084 19:28:34.560315 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11085 19:28:34.560392 #
11086 19:28:34.567122 # ======================================================================
11087 19:28:34.573623 # ERROR: test_seal_with_auth (tpm2_tests.SmokeTest.test_seal_with_auth)
11088 19:28:34.580588 # ----------------------------------------------------------------------
11089 19:28:34.583456 # Traceback (most recent call last):
11090 19:28:34.593596 # File "/lava-13420409/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11091 19:28:34.596827 # self.client = tpm2.Client()
11092 19:28:34.600011 # ^^^^^^^^^^^^^
11093 19:28:34.610271 # File "/lava-13420409/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11094 19:28:34.613338 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11095 19:28:34.620055 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11096 19:28:34.623030 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11097 19:28:34.623117 #
11098 19:28:34.629769 # ======================================================================
11099 19:28:34.636455 # ERROR: test_seal_with_policy (tpm2_tests.SmokeTest.test_seal_with_policy)
11100 19:28:34.643503 # ----------------------------------------------------------------------
11101 19:28:34.646814 # Traceback (most recent call last):
11102 19:28:34.656528 # File "/lava-13420409/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11103 19:28:34.659926 # self.client = tpm2.Client()
11104 19:28:34.663578 # ^^^^^^^^^^^^^
11105 19:28:34.673032 # File "/lava-13420409/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11106 19:28:34.676209 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11107 19:28:34.683483 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11108 19:28:34.686779 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11109 19:28:34.686853 #
11110 19:28:34.693735 # ======================================================================
11111 19:28:34.701150 # ERROR: test_seal_with_too_long_auth (tpm2_tests.SmokeTest.test_seal_with_too_long_auth)
11112 19:28:34.708087 # ----------------------------------------------------------------------
11113 19:28:34.711744 # Traceback (most recent call last):
11114 19:28:34.722329 # File "/lava-13420409/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11115 19:28:34.725920 # self.client = tpm2.Client()
11116 19:28:34.732401 # ^^^^^^^^^^^^^
11117 19:28:34.739378 # File "/lava-13420409/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11118 19:28:34.742836 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11119 19:28:34.749866 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11120 19:28:34.753132 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11121 19:28:34.753217 #
11122 19:28:34.759973 # ======================================================================
11123 19:28:34.766765 # ERROR: test_send_two_cmds (tpm2_tests.SmokeTest.test_send_two_cmds)
11124 19:28:34.773005 # ----------------------------------------------------------------------
11125 19:28:34.776546 # Traceback (most recent call last):
11126 19:28:34.786638 # File "/lava-13420409/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11127 19:28:34.789712 # self.client = tpm2.Client()
11128 19:28:34.793179 # ^^^^^^^^^^^^^
11129 19:28:34.803094 # File "/lava-13420409/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11130 19:28:34.806294 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11131 19:28:34.812723 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11132 19:28:34.816329 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11133 19:28:34.816401 #
11134 19:28:34.822748 # ======================================================================
11135 19:28:34.829488 # ERROR: test_too_short_cmd (tpm2_tests.SmokeTest.test_too_short_cmd)
11136 19:28:34.835799 # ----------------------------------------------------------------------
11137 19:28:34.839086 # Traceback (most recent call last):
11138 19:28:34.849166 # File "/lava-13420409/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11139 19:28:34.852331 # self.client = tpm2.Client()
11140 19:28:34.855780 # ^^^^^^^^^^^^^
11141 19:28:34.865735 # File "/lava-13420409/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11142 19:28:34.868940 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11143 19:28:34.875625 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11144 19:28:34.878878 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11145 19:28:34.882312 #
11146 19:28:34.885541 # ======================================================================
11147 19:28:34.895502 # ERROR: test_unseal_with_wrong_auth (tpm2_tests.SmokeTest.test_unseal_with_wrong_auth)
11148 19:28:34.902420 # ----------------------------------------------------------------------
11149 19:28:34.905507 # Traceback (most recent call last):
11150 19:28:34.915630 # File "/lava-13420409/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11151 19:28:34.919090 # self.client = tpm2.Client()
11152 19:28:34.922139 # ^^^^^^^^^^^^^
11153 19:28:34.932637 # File "/lava-13420409/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11154 19:28:34.935520 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11155 19:28:34.939052 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11156 19:28:34.945675 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11157 19:28:34.945758 #
11158 19:28:34.951903 # ======================================================================
11159 19:28:34.961787 # ERROR: test_unseal_with_wrong_policy (tpm2_tests.SmokeTest.test_unseal_with_wrong_policy)
11160 19:28:34.965406 # ----------------------------------------------------------------------
11161 19:28:34.968471 # Traceback (most recent call last):
11162 19:28:34.978650 # File "/lava-13420409/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11163 19:28:34.981617 # self.client = tpm2.Client()
11164 19:28:34.985088 # ^^^^^^^^^^^^^
11165 19:28:34.994900 # File "/lava-13420409/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11166 19:28:35.001564 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11167 19:28:35.005052 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11168 19:28:35.011622 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11169 19:28:35.011714 #
11170 19:28:35.018497 # ----------------------------------------------------------------------
11171 19:28:35.018573 # Ran 9 tests in 0.052s
11172 19:28:35.021650 #
11173 19:28:35.021721 # FAILED (errors=9)
11174 19:28:35.028306 # test_async (tpm2_tests.AsyncTest.test_async) ... ok
11175 19:28:35.035086 # test_flush_invalid_context (tpm2_tests.AsyncTest.test_flush_invalid_context) ... ok
11176 19:28:35.035174 #
11177 19:28:35.041518 # ----------------------------------------------------------------------
11178 19:28:35.045028 # Ran 2 tests in 0.024s
11179 19:28:35.045101 #
11180 19:28:35.045175 # OK
11181 19:28:35.048151 ok 1 selftests: tpm2: test_smoke.sh
11182 19:28:35.051590 # selftests: tpm2: test_space.sh
11183 19:28:35.057913 # test_flush_context (tpm2_tests.SpaceTest.test_flush_context) ... ERROR
11184 19:28:35.061473 # test_get_handles (tpm2_tests.SpaceTest.test_get_handles) ... ERROR
11185 19:28:35.067818 # test_invalid_cc (tpm2_tests.SpaceTest.test_invalid_cc) ... ERROR
11186 19:28:35.074543 # test_make_two_spaces (tpm2_tests.SpaceTest.test_make_two_spaces) ... ERROR
11187 19:28:35.074624 #
11188 19:28:35.081381 # ======================================================================
11189 19:28:35.087848 # ERROR: test_flush_context (tpm2_tests.SpaceTest.test_flush_context)
11190 19:28:35.094695 # ----------------------------------------------------------------------
11191 19:28:35.097754 # Traceback (most recent call last):
11192 19:28:35.110952 # File "/lava-13420409/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 261, in test_flush_context
11193 19:28:35.114180 # root1 = space1.create_root_key()
11194 19:28:35.117721 # ^^^^^^^^^^^^^^^^^^^^^^^^
11195 19:28:35.127551 # File "/lava-13420409/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11196 19:28:35.133971 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11197 19:28:35.137270 # ^^^^^^^^^^^^^^^^^^
11198 19:28:35.147342 # File "/lava-13420409/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11199 19:28:35.150702 # raise ProtocolError(cc, rc)
11200 19:28:35.157401 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11201 19:28:35.157478 #
11202 19:28:35.163975 # ======================================================================
11203 19:28:35.167218 # ERROR: test_get_handles (tpm2_tests.SpaceTest.test_get_handles)
11204 19:28:35.173852 # ----------------------------------------------------------------------
11205 19:28:35.177083 # Traceback (most recent call last):
11206 19:28:35.190352 # File "/lava-13420409/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 271, in test_get_handles
11207 19:28:35.193683 # space1.create_root_key()
11208 19:28:35.203412 # File "/lava-13420409/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11209 19:28:35.207036 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11210 19:28:35.213566 # ^^^^^^^^^^^^^^^^^^
11211 19:28:35.223591 # File "/lava-13420409/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11212 19:28:35.226795 # raise ProtocolError(cc, rc)
11213 19:28:35.230223 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11214 19:28:35.233461 #
11215 19:28:35.239957 # ======================================================================
11216 19:28:35.243259 # ERROR: test_invalid_cc (tpm2_tests.SpaceTest.test_invalid_cc)
11217 19:28:35.250248 # ----------------------------------------------------------------------
11218 19:28:35.253633 # Traceback (most recent call last):
11219 19:28:35.266413 # File "/lava-13420409/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 290, in test_invalid_cc
11220 19:28:35.269876 # root1 = space1.create_root_key()
11221 19:28:35.273048 # ^^^^^^^^^^^^^^^^^^^^^^^^
11222 19:28:35.282847 # File "/lava-13420409/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11223 19:28:35.286500 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11224 19:28:35.292921 # ^^^^^^^^^^^^^^^^^^
11225 19:28:35.303149 # File "/lava-13420409/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11226 19:28:35.306450 # raise ProtocolError(cc, rc)
11227 19:28:35.313247 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11228 19:28:35.313332 #
11229 19:28:35.319677 # ======================================================================
11230 19:28:35.326276 # ERROR: test_make_two_spaces (tpm2_tests.SpaceTest.test_make_two_spaces)
11231 19:28:35.329511 # ----------------------------------------------------------------------
11232 19:28:35.332743 # Traceback (most recent call last):
11233 19:28:35.346221 # File "/lava-13420409/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 247, in test_make_two_spaces
11234 19:28:35.349891 # root1 = space1.create_root_key()
11235 19:28:35.352593 # ^^^^^^^^^^^^^^^^^^^^^^^^
11236 19:28:35.363118 # File "/lava-13420409/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11237 19:28:35.369075 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11238 19:28:35.372583 # ^^^^^^^^^^^^^^^^^^
11239 19:28:35.382622 # File "/lava-13420409/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11240 19:28:35.385715 # raise ProtocolError(cc, rc)
11241 19:28:35.392575 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11242 19:28:35.392653 #
11243 19:28:35.398959 # ----------------------------------------------------------------------
11244 19:28:35.402250 # Ran 4 tests in 0.085s
11245 19:28:35.402327 #
11246 19:28:35.402396 # FAILED (errors=4)
11247 19:28:35.408917 not ok 2 selftests: tpm2: test_space.sh # exit=1
11248 19:28:35.660047 tpm2_test_smoke_sh pass
11249 19:28:35.663445 tpm2_test_space_sh fail
11250 19:28:35.729053 + ../../utils/send-to-lava.sh ./output/result.txt
11251 19:28:35.778403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-tpm2 RESULT=pass>
11252 19:28:35.778735 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-tpm2 RESULT=pass
11254 19:28:35.812175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass>
11255 19:28:35.812429 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass
11257 19:28:35.848196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_space_sh RESULT=fail>
11258 19:28:35.848460 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_space_sh RESULT=fail
11260 19:28:35.851524 + set +x
11261 19:28:35.855338 <LAVA_SIGNAL_ENDRUN 1_kselftest-tpm2 13420409_1.6.2.3.5>
11262 19:28:35.855585 Received signal: <ENDRUN> 1_kselftest-tpm2 13420409_1.6.2.3.5
11263 19:28:35.855669 Ending use of test pattern.
11264 19:28:35.855731 Ending test lava.1_kselftest-tpm2 (13420409_1.6.2.3.5), duration 9.19
11266 19:28:35.858302 <LAVA_TEST_RUNNER EXIT>
11267 19:28:35.858553 ok: lava_test_shell seems to have completed
11268 19:28:35.858654 shardfile-tpm2: pass
tpm2_test_smoke_sh: pass
tpm2_test_space_sh: fail
11269 19:28:35.858749 end: 3.1 lava-test-shell (duration 00:00:10) [common]
11270 19:28:35.858831 end: 3 lava-test-retry (duration 00:00:10) [common]
11271 19:28:35.858921 start: 4 finalize (timeout 00:07:45) [common]
11272 19:28:35.859011 start: 4.1 power-off (timeout 00:00:30) [common]
11273 19:28:35.859171 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=off'
11274 19:28:35.935603 >> Command sent successfully.
11275 19:28:35.937852 Returned 0 in 0 seconds
11276 19:28:36.038142 end: 4.1 power-off (duration 00:00:00) [common]
11278 19:28:36.038516 start: 4.2 read-feedback (timeout 00:07:45) [common]
11279 19:28:36.038777 Listened to connection for namespace 'common' for up to 1s
11280 19:28:37.039713 Finalising connection for namespace 'common'
11281 19:28:37.039902 Disconnecting from shell: Finalise
11282 19:28:37.039978 / #
11283 19:28:37.140295 end: 4.2 read-feedback (duration 00:00:01) [common]
11284 19:28:37.140502 end: 4 finalize (duration 00:00:01) [common]
11285 19:28:37.140651 Cleaning after the job
11286 19:28:37.140794 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13420409/tftp-deploy-jyww44e8/ramdisk
11287 19:28:37.143019 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13420409/tftp-deploy-jyww44e8/kernel
11288 19:28:37.153901 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13420409/tftp-deploy-jyww44e8/dtb
11289 19:28:37.154139 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13420409/tftp-deploy-jyww44e8/nfsrootfs
11290 19:28:37.219909 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13420409/tftp-deploy-jyww44e8/modules
11291 19:28:37.225895 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/13420409
11292 19:28:37.795382 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/13420409
11293 19:28:37.795576 Job finished correctly