Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 25
- Errors: 0
- Kernel Errors: 34
- Boot result: PASS
1 19:25:48.845751 lava-dispatcher, installed at version: 2024.01
2 19:25:48.845956 start: 0 validate
3 19:25:48.846083 Start time: 2024-04-18 19:25:48.846075+00:00 (UTC)
4 19:25:48.846203 Using caching service: 'http://localhost/cache/?uri=%s'
5 19:25:48.846332 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-libcamera%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 19:25:49.114136 Using caching service: 'http://localhost/cache/?uri=%s'
7 19:25:49.114302 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 19:25:49.380317 Using caching service: 'http://localhost/cache/?uri=%s'
9 19:25:49.380489 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 19:25:49.638908 Using caching service: 'http://localhost/cache/?uri=%s'
11 19:25:49.639090 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-libcamera%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 19:25:49.905845 Using caching service: 'http://localhost/cache/?uri=%s'
13 19:25:49.906026 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 19:25:50.165059 validate duration: 1.32
16 19:25:50.165324 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 19:25:50.165421 start: 1.1 download-retry (timeout 00:10:00) [common]
18 19:25:50.165518 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 19:25:50.165679 Not decompressing ramdisk as can be used compressed.
20 19:25:50.165765 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-libcamera/20240313.0/arm64/initrd.cpio.gz
21 19:25:50.165830 saving as /var/lib/lava/dispatcher/tmp/13420400/tftp-deploy-flapplqt/ramdisk/initrd.cpio.gz
22 19:25:50.165895 total size: 5628151 (5 MB)
23 19:25:50.167039 progress 0 % (0 MB)
24 19:25:50.168679 progress 5 % (0 MB)
25 19:25:50.170290 progress 10 % (0 MB)
26 19:25:50.171689 progress 15 % (0 MB)
27 19:25:50.173246 progress 20 % (1 MB)
28 19:25:50.174730 progress 25 % (1 MB)
29 19:25:50.176282 progress 30 % (1 MB)
30 19:25:50.177848 progress 35 % (1 MB)
31 19:25:50.179219 progress 40 % (2 MB)
32 19:25:50.180865 progress 45 % (2 MB)
33 19:25:50.182270 progress 50 % (2 MB)
34 19:25:50.183882 progress 55 % (2 MB)
35 19:25:50.185410 progress 60 % (3 MB)
36 19:25:50.186820 progress 65 % (3 MB)
37 19:25:50.188400 progress 70 % (3 MB)
38 19:25:50.189806 progress 75 % (4 MB)
39 19:25:50.191330 progress 80 % (4 MB)
40 19:25:50.192697 progress 85 % (4 MB)
41 19:25:50.194286 progress 90 % (4 MB)
42 19:25:50.195808 progress 95 % (5 MB)
43 19:25:50.197186 progress 100 % (5 MB)
44 19:25:50.197393 5 MB downloaded in 0.03 s (170.41 MB/s)
45 19:25:50.197589 end: 1.1.1 http-download (duration 00:00:00) [common]
47 19:25:50.197830 end: 1.1 download-retry (duration 00:00:00) [common]
48 19:25:50.197926 start: 1.2 download-retry (timeout 00:10:00) [common]
49 19:25:50.198011 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 19:25:50.198147 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 19:25:50.198218 saving as /var/lib/lava/dispatcher/tmp/13420400/tftp-deploy-flapplqt/kernel/Image
52 19:25:50.198280 total size: 54286848 (51 MB)
53 19:25:50.198343 No compression specified
54 19:25:50.199462 progress 0 % (0 MB)
55 19:25:50.213243 progress 5 % (2 MB)
56 19:25:50.227325 progress 10 % (5 MB)
57 19:25:50.241152 progress 15 % (7 MB)
58 19:25:50.255096 progress 20 % (10 MB)
59 19:25:50.268901 progress 25 % (12 MB)
60 19:25:50.282834 progress 30 % (15 MB)
61 19:25:50.296443 progress 35 % (18 MB)
62 19:25:50.310333 progress 40 % (20 MB)
63 19:25:50.324152 progress 45 % (23 MB)
64 19:25:50.338072 progress 50 % (25 MB)
65 19:25:50.351793 progress 55 % (28 MB)
66 19:25:50.365491 progress 60 % (31 MB)
67 19:25:50.379058 progress 65 % (33 MB)
68 19:25:50.392957 progress 70 % (36 MB)
69 19:25:50.406761 progress 75 % (38 MB)
70 19:25:50.420820 progress 80 % (41 MB)
71 19:25:50.434616 progress 85 % (44 MB)
72 19:25:50.448524 progress 90 % (46 MB)
73 19:25:50.462064 progress 95 % (49 MB)
74 19:25:50.475519 progress 100 % (51 MB)
75 19:25:50.475739 51 MB downloaded in 0.28 s (186.60 MB/s)
76 19:25:50.475889 end: 1.2.1 http-download (duration 00:00:00) [common]
78 19:25:50.476160 end: 1.2 download-retry (duration 00:00:00) [common]
79 19:25:50.476263 start: 1.3 download-retry (timeout 00:10:00) [common]
80 19:25:50.476352 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 19:25:50.476489 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 19:25:50.476561 saving as /var/lib/lava/dispatcher/tmp/13420400/tftp-deploy-flapplqt/dtb/mt8192-asurada-spherion-r0.dtb
83 19:25:50.476624 total size: 47230 (0 MB)
84 19:25:50.476687 No compression specified
85 19:25:50.477849 progress 69 % (0 MB)
86 19:25:50.478123 progress 100 % (0 MB)
87 19:25:50.478299 0 MB downloaded in 0.00 s (26.93 MB/s)
88 19:25:50.478437 end: 1.3.1 http-download (duration 00:00:00) [common]
90 19:25:50.478658 end: 1.3 download-retry (duration 00:00:00) [common]
91 19:25:50.478747 start: 1.4 download-retry (timeout 00:10:00) [common]
92 19:25:50.478830 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 19:25:50.478945 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-libcamera/20240313.0/arm64/full.rootfs.tar.xz
94 19:25:50.479015 saving as /var/lib/lava/dispatcher/tmp/13420400/tftp-deploy-flapplqt/nfsrootfs/full.rootfs.tar
95 19:25:50.479076 total size: 69067788 (65 MB)
96 19:25:50.479138 Using unxz to decompress xz
97 19:25:50.483286 progress 0 % (0 MB)
98 19:25:50.674736 progress 5 % (3 MB)
99 19:25:50.876127 progress 10 % (6 MB)
100 19:25:51.078265 progress 15 % (9 MB)
101 19:25:51.241222 progress 20 % (13 MB)
102 19:25:51.421242 progress 25 % (16 MB)
103 19:25:51.623546 progress 30 % (19 MB)
104 19:25:51.742278 progress 35 % (23 MB)
105 19:25:51.838528 progress 40 % (26 MB)
106 19:25:52.039338 progress 45 % (29 MB)
107 19:25:52.248513 progress 50 % (32 MB)
108 19:25:52.454380 progress 55 % (36 MB)
109 19:25:52.676918 progress 60 % (39 MB)
110 19:25:52.865229 progress 65 % (42 MB)
111 19:25:53.059934 progress 70 % (46 MB)
112 19:25:53.251556 progress 75 % (49 MB)
113 19:25:53.465706 progress 80 % (52 MB)
114 19:25:53.649306 progress 85 % (56 MB)
115 19:25:53.852276 progress 90 % (59 MB)
116 19:25:54.062663 progress 95 % (62 MB)
117 19:25:54.269930 progress 100 % (65 MB)
118 19:25:54.275837 65 MB downloaded in 3.80 s (17.35 MB/s)
119 19:25:54.276089 end: 1.4.1 http-download (duration 00:00:04) [common]
121 19:25:54.276371 end: 1.4 download-retry (duration 00:00:04) [common]
122 19:25:54.276467 start: 1.5 download-retry (timeout 00:09:56) [common]
123 19:25:54.276558 start: 1.5.1 http-download (timeout 00:09:56) [common]
124 19:25:54.276710 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 19:25:54.276781 saving as /var/lib/lava/dispatcher/tmp/13420400/tftp-deploy-flapplqt/modules/modules.tar
126 19:25:54.276844 total size: 8631416 (8 MB)
127 19:25:54.276908 Using unxz to decompress xz
128 19:25:54.281104 progress 0 % (0 MB)
129 19:25:54.299945 progress 5 % (0 MB)
130 19:25:54.324342 progress 10 % (0 MB)
131 19:25:54.347979 progress 15 % (1 MB)
132 19:25:54.371059 progress 20 % (1 MB)
133 19:25:54.395177 progress 25 % (2 MB)
134 19:25:54.420763 progress 30 % (2 MB)
135 19:25:54.444156 progress 35 % (2 MB)
136 19:25:54.468972 progress 40 % (3 MB)
137 19:25:54.492686 progress 45 % (3 MB)
138 19:25:54.517158 progress 50 % (4 MB)
139 19:25:54.541781 progress 55 % (4 MB)
140 19:25:54.569090 progress 60 % (4 MB)
141 19:25:54.593845 progress 65 % (5 MB)
142 19:25:54.618528 progress 70 % (5 MB)
143 19:25:54.642473 progress 75 % (6 MB)
144 19:25:54.667645 progress 80 % (6 MB)
145 19:25:54.692999 progress 85 % (7 MB)
146 19:25:54.721601 progress 90 % (7 MB)
147 19:25:54.750405 progress 95 % (7 MB)
148 19:25:54.776261 progress 100 % (8 MB)
149 19:25:54.781694 8 MB downloaded in 0.50 s (16.31 MB/s)
150 19:25:54.781944 end: 1.5.1 http-download (duration 00:00:01) [common]
152 19:25:54.782211 end: 1.5 download-retry (duration 00:00:01) [common]
153 19:25:54.782303 start: 1.6 prepare-tftp-overlay (timeout 00:09:55) [common]
154 19:25:54.782399 start: 1.6.1 extract-nfsrootfs (timeout 00:09:55) [common]
155 19:25:56.326677 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/13420400/extract-nfsrootfs-co75676u
156 19:25:56.326914 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 19:25:56.327015 start: 1.6.2 lava-overlay (timeout 00:09:54) [common]
158 19:25:56.327179 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/13420400/lava-overlay-cl2r0me4
159 19:25:56.327307 makedir: /var/lib/lava/dispatcher/tmp/13420400/lava-overlay-cl2r0me4/lava-13420400/bin
160 19:25:56.327406 makedir: /var/lib/lava/dispatcher/tmp/13420400/lava-overlay-cl2r0me4/lava-13420400/tests
161 19:25:56.327504 makedir: /var/lib/lava/dispatcher/tmp/13420400/lava-overlay-cl2r0me4/lava-13420400/results
162 19:25:56.327603 Creating /var/lib/lava/dispatcher/tmp/13420400/lava-overlay-cl2r0me4/lava-13420400/bin/lava-add-keys
163 19:25:56.327740 Creating /var/lib/lava/dispatcher/tmp/13420400/lava-overlay-cl2r0me4/lava-13420400/bin/lava-add-sources
164 19:25:56.327886 Creating /var/lib/lava/dispatcher/tmp/13420400/lava-overlay-cl2r0me4/lava-13420400/bin/lava-background-process-start
165 19:25:56.328028 Creating /var/lib/lava/dispatcher/tmp/13420400/lava-overlay-cl2r0me4/lava-13420400/bin/lava-background-process-stop
166 19:25:56.328154 Creating /var/lib/lava/dispatcher/tmp/13420400/lava-overlay-cl2r0me4/lava-13420400/bin/lava-common-functions
167 19:25:56.328277 Creating /var/lib/lava/dispatcher/tmp/13420400/lava-overlay-cl2r0me4/lava-13420400/bin/lava-echo-ipv4
168 19:25:56.328400 Creating /var/lib/lava/dispatcher/tmp/13420400/lava-overlay-cl2r0me4/lava-13420400/bin/lava-install-packages
169 19:25:56.328523 Creating /var/lib/lava/dispatcher/tmp/13420400/lava-overlay-cl2r0me4/lava-13420400/bin/lava-installed-packages
170 19:25:56.328645 Creating /var/lib/lava/dispatcher/tmp/13420400/lava-overlay-cl2r0me4/lava-13420400/bin/lava-os-build
171 19:25:56.328767 Creating /var/lib/lava/dispatcher/tmp/13420400/lava-overlay-cl2r0me4/lava-13420400/bin/lava-probe-channel
172 19:25:56.328889 Creating /var/lib/lava/dispatcher/tmp/13420400/lava-overlay-cl2r0me4/lava-13420400/bin/lava-probe-ip
173 19:25:56.329011 Creating /var/lib/lava/dispatcher/tmp/13420400/lava-overlay-cl2r0me4/lava-13420400/bin/lava-target-ip
174 19:25:56.329133 Creating /var/lib/lava/dispatcher/tmp/13420400/lava-overlay-cl2r0me4/lava-13420400/bin/lava-target-mac
175 19:25:56.329256 Creating /var/lib/lava/dispatcher/tmp/13420400/lava-overlay-cl2r0me4/lava-13420400/bin/lava-target-storage
176 19:25:56.329380 Creating /var/lib/lava/dispatcher/tmp/13420400/lava-overlay-cl2r0me4/lava-13420400/bin/lava-test-case
177 19:25:56.329504 Creating /var/lib/lava/dispatcher/tmp/13420400/lava-overlay-cl2r0me4/lava-13420400/bin/lava-test-event
178 19:25:56.329663 Creating /var/lib/lava/dispatcher/tmp/13420400/lava-overlay-cl2r0me4/lava-13420400/bin/lava-test-feedback
179 19:25:56.329785 Creating /var/lib/lava/dispatcher/tmp/13420400/lava-overlay-cl2r0me4/lava-13420400/bin/lava-test-raise
180 19:25:56.329909 Creating /var/lib/lava/dispatcher/tmp/13420400/lava-overlay-cl2r0me4/lava-13420400/bin/lava-test-reference
181 19:25:56.330031 Creating /var/lib/lava/dispatcher/tmp/13420400/lava-overlay-cl2r0me4/lava-13420400/bin/lava-test-runner
182 19:25:56.330154 Creating /var/lib/lava/dispatcher/tmp/13420400/lava-overlay-cl2r0me4/lava-13420400/bin/lava-test-set
183 19:25:56.330276 Creating /var/lib/lava/dispatcher/tmp/13420400/lava-overlay-cl2r0me4/lava-13420400/bin/lava-test-shell
184 19:25:56.330404 Updating /var/lib/lava/dispatcher/tmp/13420400/lava-overlay-cl2r0me4/lava-13420400/bin/lava-install-packages (oe)
185 19:25:56.330553 Updating /var/lib/lava/dispatcher/tmp/13420400/lava-overlay-cl2r0me4/lava-13420400/bin/lava-installed-packages (oe)
186 19:25:56.330673 Creating /var/lib/lava/dispatcher/tmp/13420400/lava-overlay-cl2r0me4/lava-13420400/environment
187 19:25:56.330769 LAVA metadata
188 19:25:56.330838 - LAVA_JOB_ID=13420400
189 19:25:56.330900 - LAVA_DISPATCHER_IP=192.168.201.1
190 19:25:56.330997 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:54) [common]
191 19:25:56.331062 skipped lava-vland-overlay
192 19:25:56.331136 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 19:25:56.331213 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:54) [common]
194 19:25:56.331273 skipped lava-multinode-overlay
195 19:25:56.331344 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 19:25:56.331419 start: 1.6.2.3 test-definition (timeout 00:09:54) [common]
197 19:25:56.331491 Loading test definitions
198 19:25:56.331576 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:54) [common]
199 19:25:56.331645 Using /lava-13420400 at stage 0
200 19:25:56.331940 uuid=13420400_1.6.2.3.1 testdef=None
201 19:25:56.332028 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 19:25:56.332114 start: 1.6.2.3.2 test-overlay (timeout 00:09:54) [common]
203 19:25:56.332594 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 19:25:56.332812 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:54) [common]
206 19:25:56.333405 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 19:25:56.333679 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:54) [common]
209 19:25:56.334258 runner path: /var/lib/lava/dispatcher/tmp/13420400/lava-overlay-cl2r0me4/lava-13420400/0/tests/0_lc-compliance test_uuid 13420400_1.6.2.3.1
210 19:25:56.334413 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 19:25:56.334617 Creating lava-test-runner.conf files
213 19:25:56.334679 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/13420400/lava-overlay-cl2r0me4/lava-13420400/0 for stage 0
214 19:25:56.334768 - 0_lc-compliance
215 19:25:56.334863 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
216 19:25:56.334947 start: 1.6.2.4 compress-overlay (timeout 00:09:54) [common]
217 19:25:56.340886 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
218 19:25:56.340987 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:54) [common]
219 19:25:56.341071 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
220 19:25:56.341154 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
221 19:25:56.341237 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:54) [common]
222 19:25:56.507927 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
223 19:25:56.508305 start: 1.6.4 extract-modules (timeout 00:09:54) [common]
224 19:25:56.508420 extracting modules file /var/lib/lava/dispatcher/tmp/13420400/tftp-deploy-flapplqt/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13420400/extract-nfsrootfs-co75676u
225 19:25:56.722364 extracting modules file /var/lib/lava/dispatcher/tmp/13420400/tftp-deploy-flapplqt/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13420400/extract-overlay-ramdisk-m8mr5lhn/ramdisk
226 19:25:56.945001 end: 1.6.4 extract-modules (duration 00:00:00) [common]
227 19:25:56.945175 start: 1.6.5 apply-overlay-tftp (timeout 00:09:53) [common]
228 19:25:56.945276 [common] Applying overlay to NFS
229 19:25:56.945345 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13420400/compress-overlay-r6dz_gfs/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/13420400/extract-nfsrootfs-co75676u
230 19:25:56.951888 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
231 19:25:56.952000 start: 1.6.6 configure-preseed-file (timeout 00:09:53) [common]
232 19:25:56.952093 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
233 19:25:56.952180 start: 1.6.7 compress-ramdisk (timeout 00:09:53) [common]
234 19:25:56.952257 Building ramdisk /var/lib/lava/dispatcher/tmp/13420400/extract-overlay-ramdisk-m8mr5lhn/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/13420400/extract-overlay-ramdisk-m8mr5lhn/ramdisk
235 19:25:57.301156 >> 130624 blocks
236 19:25:59.463875 rename /var/lib/lava/dispatcher/tmp/13420400/extract-overlay-ramdisk-m8mr5lhn/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/13420400/tftp-deploy-flapplqt/ramdisk/ramdisk.cpio.gz
237 19:25:59.464390 end: 1.6.7 compress-ramdisk (duration 00:00:03) [common]
238 19:25:59.464525 start: 1.6.8 prepare-kernel (timeout 00:09:51) [common]
239 19:25:59.464667 start: 1.6.8.1 prepare-fit (timeout 00:09:51) [common]
240 19:25:59.464823 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/13420400/tftp-deploy-flapplqt/kernel/Image'
241 19:26:13.229680 Returned 0 in 13 seconds
242 19:26:13.330318 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/13420400/tftp-deploy-flapplqt/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/13420400/tftp-deploy-flapplqt/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/13420400/tftp-deploy-flapplqt/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/13420400/tftp-deploy-flapplqt/kernel/image.itb
243 19:26:13.712054 output: FIT description: Kernel Image image with one or more FDT blobs
244 19:26:13.712425 output: Created: Thu Apr 18 20:26:13 2024
245 19:26:13.712531 output: Image 0 (kernel-1)
246 19:26:13.712620 output: Description:
247 19:26:13.712704 output: Created: Thu Apr 18 20:26:13 2024
248 19:26:13.712791 output: Type: Kernel Image
249 19:26:13.712873 output: Compression: lzma compressed
250 19:26:13.712973 output: Data Size: 12910355 Bytes = 12607.77 KiB = 12.31 MiB
251 19:26:13.713075 output: Architecture: AArch64
252 19:26:13.713177 output: OS: Linux
253 19:26:13.713277 output: Load Address: 0x00000000
254 19:26:13.713377 output: Entry Point: 0x00000000
255 19:26:13.713474 output: Hash algo: crc32
256 19:26:13.713581 output: Hash value: bbac8b0b
257 19:26:13.713680 output: Image 1 (fdt-1)
258 19:26:13.713776 output: Description: mt8192-asurada-spherion-r0
259 19:26:13.713873 output: Created: Thu Apr 18 20:26:13 2024
260 19:26:13.713969 output: Type: Flat Device Tree
261 19:26:13.714065 output: Compression: uncompressed
262 19:26:13.714160 output: Data Size: 47230 Bytes = 46.12 KiB = 0.05 MiB
263 19:26:13.714256 output: Architecture: AArch64
264 19:26:13.714350 output: Hash algo: crc32
265 19:26:13.714444 output: Hash value: 4bf0d1ac
266 19:26:13.714538 output: Image 2 (ramdisk-1)
267 19:26:13.714631 output: Description: unavailable
268 19:26:13.714725 output: Created: Thu Apr 18 20:26:13 2024
269 19:26:13.714818 output: Type: RAMDisk Image
270 19:26:13.714912 output: Compression: Unknown Compression
271 19:26:13.715005 output: Data Size: 18778539 Bytes = 18338.42 KiB = 17.91 MiB
272 19:26:13.715099 output: Architecture: AArch64
273 19:26:13.715193 output: OS: Linux
274 19:26:13.715286 output: Load Address: unavailable
275 19:26:13.715378 output: Entry Point: unavailable
276 19:26:13.715471 output: Hash algo: crc32
277 19:26:13.715563 output: Hash value: d3fd68a6
278 19:26:13.715656 output: Default Configuration: 'conf-1'
279 19:26:13.715749 output: Configuration 0 (conf-1)
280 19:26:13.715841 output: Description: mt8192-asurada-spherion-r0
281 19:26:13.715933 output: Kernel: kernel-1
282 19:26:13.716026 output: Init Ramdisk: ramdisk-1
283 19:26:13.716121 output: FDT: fdt-1
284 19:26:13.716214 output: Loadables: kernel-1
285 19:26:13.716307 output:
286 19:26:13.716568 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
287 19:26:13.716719 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
288 19:26:13.716873 end: 1.6 prepare-tftp-overlay (duration 00:00:19) [common]
289 19:26:13.717010 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:36) [common]
290 19:26:13.717130 No LXC device requested
291 19:26:13.717256 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
292 19:26:13.717387 start: 1.8 deploy-device-env (timeout 00:09:36) [common]
293 19:26:13.717516 end: 1.8 deploy-device-env (duration 00:00:00) [common]
294 19:26:13.717625 Checking files for TFTP limit of 4294967296 bytes.
295 19:26:13.718313 end: 1 tftp-deploy (duration 00:00:24) [common]
296 19:26:13.718461 start: 2 depthcharge-action (timeout 00:05:00) [common]
297 19:26:13.718570 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
298 19:26:13.718761 substitutions:
299 19:26:13.718862 - {DTB}: 13420400/tftp-deploy-flapplqt/dtb/mt8192-asurada-spherion-r0.dtb
300 19:26:13.718969 - {INITRD}: 13420400/tftp-deploy-flapplqt/ramdisk/ramdisk.cpio.gz
301 19:26:13.719070 - {KERNEL}: 13420400/tftp-deploy-flapplqt/kernel/Image
302 19:26:13.719171 - {LAVA_MAC}: None
303 19:26:13.719270 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/13420400/extract-nfsrootfs-co75676u
304 19:26:13.719371 - {NFS_SERVER_IP}: 192.168.201.1
305 19:26:13.719470 - {PRESEED_CONFIG}: None
306 19:26:13.719567 - {PRESEED_LOCAL}: None
307 19:26:13.719665 - {RAMDISK}: 13420400/tftp-deploy-flapplqt/ramdisk/ramdisk.cpio.gz
308 19:26:13.719762 - {ROOT_PART}: None
309 19:26:13.719859 - {ROOT}: None
310 19:26:13.719956 - {SERVER_IP}: 192.168.201.1
311 19:26:13.720052 - {TEE}: None
312 19:26:13.720148 Parsed boot commands:
313 19:26:13.720243 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
314 19:26:13.720495 Parsed boot commands: tftpboot 192.168.201.1 13420400/tftp-deploy-flapplqt/kernel/image.itb 13420400/tftp-deploy-flapplqt/kernel/cmdline
315 19:26:13.720624 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
316 19:26:13.720755 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
317 19:26:13.720893 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
318 19:26:13.721024 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
319 19:26:13.721138 Not connected, no need to disconnect.
320 19:26:13.721259 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
321 19:26:13.721391 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
322 19:26:13.721501 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
323 19:26:13.725818 Setting prompt string to ['lava-test: # ']
324 19:26:13.726339 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
325 19:26:13.726521 end: 2.2.1 reset-connection (duration 00:00:00) [common]
326 19:26:13.726668 start: 2.2.2 reset-device (timeout 00:05:00) [common]
327 19:26:13.726819 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
328 19:26:13.727172 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
329 19:26:18.862686 >> Command sent successfully.
330 19:26:18.865107 Returned 0 in 5 seconds
331 19:26:18.965517 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
333 19:26:18.965930 end: 2.2.2 reset-device (duration 00:00:05) [common]
334 19:26:18.966046 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
335 19:26:18.966145 Setting prompt string to 'Starting depthcharge on Spherion...'
336 19:26:18.966224 Changing prompt to 'Starting depthcharge on Spherion...'
337 19:26:18.966310 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
338 19:26:18.966690 [Enter `^Ec?' for help]
339 19:26:19.137099
340 19:26:19.137250
341 19:26:19.137355 F0: 102B 0000
342 19:26:19.137463
343 19:26:19.137597 F3: 1001 0000 [0200]
344 19:26:19.140795
345 19:26:19.140901 F3: 1001 0000
346 19:26:19.141004
347 19:26:19.141103 F7: 102D 0000
348 19:26:19.141202
349 19:26:19.143977 F1: 0000 0000
350 19:26:19.144089
351 19:26:19.144184 V0: 0000 0000 [0001]
352 19:26:19.144279
353 19:26:19.147129 00: 0007 8000
354 19:26:19.147234
355 19:26:19.147330 01: 0000 0000
356 19:26:19.147425
357 19:26:19.150904 BP: 0C00 0209 [0000]
358 19:26:19.151008
359 19:26:19.151100 G0: 1182 0000
360 19:26:19.151190
361 19:26:19.154460 EC: 0000 0021 [4000]
362 19:26:19.154559
363 19:26:19.154649 S7: 0000 0000 [0000]
364 19:26:19.154739
365 19:26:19.157911 CC: 0000 0000 [0001]
366 19:26:19.157989
367 19:26:19.158055 T0: 0000 0040 [010F]
368 19:26:19.158118
369 19:26:19.158176 Jump to BL
370 19:26:19.158232
371 19:26:19.184580
372 19:26:19.184706
373 19:26:19.184802
374 19:26:19.191632 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
375 19:26:19.195559 ARM64: Exception handlers installed.
376 19:26:19.199051 ARM64: Testing exception
377 19:26:19.202569 ARM64: Done test exception
378 19:26:19.208892 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
379 19:26:19.219116 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
380 19:26:19.226067 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
381 19:26:19.235430 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
382 19:26:19.242174 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
383 19:26:19.248797 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
384 19:26:19.261246 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
385 19:26:19.267672 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
386 19:26:19.287299 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
387 19:26:19.290288 WDT: Last reset was cold boot
388 19:26:19.293546 SPI1(PAD0) initialized at 2873684 Hz
389 19:26:19.296917 SPI5(PAD0) initialized at 992727 Hz
390 19:26:19.300292 VBOOT: Loading verstage.
391 19:26:19.307140 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
392 19:26:19.310198 FMAP: Found "FLASH" version 1.1 at 0x20000.
393 19:26:19.313652 FMAP: base = 0x0 size = 0x800000 #areas = 25
394 19:26:19.317005 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
395 19:26:19.324536 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
396 19:26:19.330999 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
397 19:26:19.342034 read SPI 0x96554 0xa1eb: 4594 us, 9022 KB/s, 72.176 Mbps
398 19:26:19.342122
399 19:26:19.342208
400 19:26:19.352187 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
401 19:26:19.355527 ARM64: Exception handlers installed.
402 19:26:19.358945 ARM64: Testing exception
403 19:26:19.359031 ARM64: Done test exception
404 19:26:19.365246 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
405 19:26:19.368696 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
406 19:26:19.383372 Probing TPM: . done!
407 19:26:19.383493 TPM ready after 0 ms
408 19:26:19.389780 Connected to device vid:did:rid of 1ae0:0028:00
409 19:26:19.396803 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
410 19:26:19.437420 Initialized TPM device CR50 revision 0
411 19:26:19.448560 tlcl_send_startup: Startup return code is 0
412 19:26:19.448648 TPM: setup succeeded
413 19:26:19.460199 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
414 19:26:19.468734 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
415 19:26:19.481249 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
416 19:26:19.489500 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
417 19:26:19.492965 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
418 19:26:19.497540 in-header: 03 07 00 00 08 00 00 00
419 19:26:19.501191 in-data: aa e4 47 04 13 02 00 00
420 19:26:19.505167 Chrome EC: UHEPI supported
421 19:26:19.512476 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
422 19:26:19.515976 in-header: 03 9d 00 00 08 00 00 00
423 19:26:19.519429 in-data: 10 20 20 08 00 00 00 00
424 19:26:19.519504 Phase 1
425 19:26:19.522794 FMAP: area GBB found @ 3f5000 (12032 bytes)
426 19:26:19.530704 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
427 19:26:19.533907 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
428 19:26:19.537743 Recovery requested (1009000e)
429 19:26:19.542485 TPM: Extending digest for VBOOT: boot mode into PCR 0
430 19:26:19.551066 tlcl_extend: response is 0
431 19:26:19.559137 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
432 19:26:19.564578 tlcl_extend: response is 0
433 19:26:19.571326 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
434 19:26:19.592265 read SPI 0x210d4 0x2173b: 15147 us, 9045 KB/s, 72.360 Mbps
435 19:26:19.599257 BS: bootblock times (exec / console): total (unknown) / 148 ms
436 19:26:19.599347
437 19:26:19.599415
438 19:26:19.609884 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
439 19:26:19.609984 ARM64: Exception handlers installed.
440 19:26:19.613663 ARM64: Testing exception
441 19:26:19.616887 ARM64: Done test exception
442 19:26:19.637540 pmic_efuse_setting: Set efuses in 11 msecs
443 19:26:19.641253 pmwrap_interface_init: Select PMIF_VLD_RDY
444 19:26:19.648483 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
445 19:26:19.651676 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
446 19:26:19.656013 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
447 19:26:19.662462 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
448 19:26:19.666528 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
449 19:26:19.670390 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
450 19:26:19.674257 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
451 19:26:19.681237 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
452 19:26:19.684605 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
453 19:26:19.688180 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
454 19:26:19.695015 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
455 19:26:19.697756 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
456 19:26:19.704847 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
457 19:26:19.708361 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
458 19:26:19.714810 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
459 19:26:19.721043 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
460 19:26:19.727645 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
461 19:26:19.731149 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
462 19:26:19.738501 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
463 19:26:19.741941 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
464 19:26:19.750159 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
465 19:26:19.753589 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
466 19:26:19.760365 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
467 19:26:19.767536 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
468 19:26:19.771358 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
469 19:26:19.777867 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
470 19:26:19.781499 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
471 19:26:19.784974 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
472 19:26:19.792278 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
473 19:26:19.795535 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
474 19:26:19.803504 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
475 19:26:19.806454 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
476 19:26:19.810366 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
477 19:26:19.818064 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
478 19:26:19.821597 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
479 19:26:19.825003 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
480 19:26:19.832137 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
481 19:26:19.835456 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
482 19:26:19.841669 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
483 19:26:19.845199 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
484 19:26:19.848755 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
485 19:26:19.855448 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
486 19:26:19.858334 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
487 19:26:19.861905 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
488 19:26:19.865286 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
489 19:26:19.872255 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
490 19:26:19.875655 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
491 19:26:19.878834 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
492 19:26:19.885789 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
493 19:26:19.888699 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
494 19:26:19.892371 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
495 19:26:19.899193 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
496 19:26:19.908558 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
497 19:26:19.911830 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
498 19:26:19.921944 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
499 19:26:19.928508 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
500 19:26:19.934556 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
501 19:26:19.938541 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
502 19:26:19.941649 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
503 19:26:19.950021 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x2e
504 19:26:19.956237 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
505 19:26:19.959779 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
506 19:26:19.963149 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
507 19:26:19.974720 [RTC]rtc_get_frequency_meter,154: input=15, output=794
508 19:26:19.977685 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
509 19:26:19.984520 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
510 19:26:19.987575 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
511 19:26:19.990962 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
512 19:26:19.994597 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
513 19:26:19.997980 ADC[4]: Raw value=895561 ID=7
514 19:26:20.000997 ADC[3]: Raw value=213070 ID=1
515 19:26:20.003903 RAM Code: 0x71
516 19:26:20.007662 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
517 19:26:20.014062 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
518 19:26:20.021000 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
519 19:26:20.028531 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
520 19:26:20.032013 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
521 19:26:20.034870 in-header: 03 07 00 00 08 00 00 00
522 19:26:20.038159 in-data: aa e4 47 04 13 02 00 00
523 19:26:20.041521 Chrome EC: UHEPI supported
524 19:26:20.045220 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
525 19:26:20.049469 in-header: 03 d5 00 00 08 00 00 00
526 19:26:20.053106 in-data: 98 20 60 08 00 00 00 00
527 19:26:20.056471 MRC: failed to locate region type 0.
528 19:26:20.063724 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
529 19:26:20.067130 DRAM-K: Running full calibration
530 19:26:20.074105 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
531 19:26:20.074248 header.status = 0x0
532 19:26:20.077600 header.version = 0x6 (expected: 0x6)
533 19:26:20.081089 header.size = 0xd00 (expected: 0xd00)
534 19:26:20.084513 header.flags = 0x0
535 19:26:20.087871 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
536 19:26:20.106845 read SPI 0x72590 0x1c583: 12502 us, 9286 KB/s, 74.288 Mbps
537 19:26:20.113330 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
538 19:26:20.116832 dram_init: ddr_geometry: 2
539 19:26:20.119747 [EMI] MDL number = 2
540 19:26:20.119877 [EMI] Get MDL freq = 0
541 19:26:20.123204 dram_init: ddr_type: 0
542 19:26:20.123300 is_discrete_lpddr4: 1
543 19:26:20.126204 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
544 19:26:20.126294
545 19:26:20.126391
546 19:26:20.129759 [Bian_co] ETT version 0.0.0.1
547 19:26:20.136269 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
548 19:26:20.136507
549 19:26:20.140126 dramc_set_vcore_voltage set vcore to 650000
550 19:26:20.140245 Read voltage for 800, 4
551 19:26:20.143088 Vio18 = 0
552 19:26:20.143171 Vcore = 650000
553 19:26:20.143252 Vdram = 0
554 19:26:20.146654 Vddq = 0
555 19:26:20.146761 Vmddr = 0
556 19:26:20.149819 dram_init: config_dvfs: 1
557 19:26:20.153300 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
558 19:26:20.159775 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
559 19:26:20.163358 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
560 19:26:20.166215 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
561 19:26:20.169803 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
562 19:26:20.173098 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
563 19:26:20.176348 MEM_TYPE=3, freq_sel=18
564 19:26:20.179647 sv_algorithm_assistance_LP4_1600
565 19:26:20.183180 ============ PULL DRAM RESETB DOWN ============
566 19:26:20.186653 ========== PULL DRAM RESETB DOWN end =========
567 19:26:20.193471 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
568 19:26:20.197053 ===================================
569 19:26:20.197167 LPDDR4 DRAM CONFIGURATION
570 19:26:20.201096 ===================================
571 19:26:20.204656 EX_ROW_EN[0] = 0x0
572 19:26:20.204764 EX_ROW_EN[1] = 0x0
573 19:26:20.208152 LP4Y_EN = 0x0
574 19:26:20.208250 WORK_FSP = 0x0
575 19:26:20.211620 WL = 0x2
576 19:26:20.211718 RL = 0x2
577 19:26:20.215697 BL = 0x2
578 19:26:20.215800 RPST = 0x0
579 19:26:20.219300 RD_PRE = 0x0
580 19:26:20.219398 WR_PRE = 0x1
581 19:26:20.222790 WR_PST = 0x0
582 19:26:20.222889 DBI_WR = 0x0
583 19:26:20.222956 DBI_RD = 0x0
584 19:26:20.226917 OTF = 0x1
585 19:26:20.230307 ===================================
586 19:26:20.233904 ===================================
587 19:26:20.234021 ANA top config
588 19:26:20.237383 ===================================
589 19:26:20.241137 DLL_ASYNC_EN = 0
590 19:26:20.241246 ALL_SLAVE_EN = 1
591 19:26:20.244641 NEW_RANK_MODE = 1
592 19:26:20.248443 DLL_IDLE_MODE = 1
593 19:26:20.251751 LP45_APHY_COMB_EN = 1
594 19:26:20.251857 TX_ODT_DIS = 1
595 19:26:20.255834 NEW_8X_MODE = 1
596 19:26:20.259620 ===================================
597 19:26:20.263179 ===================================
598 19:26:20.266661 data_rate = 1600
599 19:26:20.266776 CKR = 1
600 19:26:20.270221 DQ_P2S_RATIO = 8
601 19:26:20.273735 ===================================
602 19:26:20.276989 CA_P2S_RATIO = 8
603 19:26:20.280568 DQ_CA_OPEN = 0
604 19:26:20.280673 DQ_SEMI_OPEN = 0
605 19:26:20.283610 CA_SEMI_OPEN = 0
606 19:26:20.286953 CA_FULL_RATE = 0
607 19:26:20.290599 DQ_CKDIV4_EN = 1
608 19:26:20.293704 CA_CKDIV4_EN = 1
609 19:26:20.297173 CA_PREDIV_EN = 0
610 19:26:20.297271 PH8_DLY = 0
611 19:26:20.300368 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
612 19:26:20.303908 DQ_AAMCK_DIV = 4
613 19:26:20.307061 CA_AAMCK_DIV = 4
614 19:26:20.310498 CA_ADMCK_DIV = 4
615 19:26:20.313356 DQ_TRACK_CA_EN = 0
616 19:26:20.313473 CA_PICK = 800
617 19:26:20.316922 CA_MCKIO = 800
618 19:26:20.320527 MCKIO_SEMI = 0
619 19:26:20.323515 PLL_FREQ = 3068
620 19:26:20.326989 DQ_UI_PI_RATIO = 32
621 19:26:20.330456 CA_UI_PI_RATIO = 0
622 19:26:20.333946 ===================================
623 19:26:20.336923 ===================================
624 19:26:20.337021 memory_type:LPDDR4
625 19:26:20.340398 GP_NUM : 10
626 19:26:20.343742 SRAM_EN : 1
627 19:26:20.343835 MD32_EN : 0
628 19:26:20.347238 ===================================
629 19:26:20.350165 [ANA_INIT] >>>>>>>>>>>>>>
630 19:26:20.353913 <<<<<< [CONFIGURE PHASE]: ANA_TX
631 19:26:20.357117 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
632 19:26:20.360555 ===================================
633 19:26:20.363867 data_rate = 1600,PCW = 0X7600
634 19:26:20.367052 ===================================
635 19:26:20.370516 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
636 19:26:20.373470 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
637 19:26:20.380576 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
638 19:26:20.383513 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
639 19:26:20.386959 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
640 19:26:20.390796 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
641 19:26:20.394199 [ANA_INIT] flow start
642 19:26:20.398259 [ANA_INIT] PLL >>>>>>>>
643 19:26:20.398344 [ANA_INIT] PLL <<<<<<<<
644 19:26:20.401473 [ANA_INIT] MIDPI >>>>>>>>
645 19:26:20.401598 [ANA_INIT] MIDPI <<<<<<<<
646 19:26:20.405015 [ANA_INIT] DLL >>>>>>>>
647 19:26:20.408997 [ANA_INIT] flow end
648 19:26:20.412848 ============ LP4 DIFF to SE enter ============
649 19:26:20.416156 ============ LP4 DIFF to SE exit ============
650 19:26:20.416242 [ANA_INIT] <<<<<<<<<<<<<
651 19:26:20.419856 [Flow] Enable top DCM control >>>>>
652 19:26:20.423944 [Flow] Enable top DCM control <<<<<
653 19:26:20.427958 Enable DLL master slave shuffle
654 19:26:20.431618 ==============================================================
655 19:26:20.435027 Gating Mode config
656 19:26:20.442221 ==============================================================
657 19:26:20.442307 Config description:
658 19:26:20.451853 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
659 19:26:20.458233 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
660 19:26:20.461901 SELPH_MODE 0: By rank 1: By Phase
661 19:26:20.468533 ==============================================================
662 19:26:20.472263 GAT_TRACK_EN = 1
663 19:26:20.475860 RX_GATING_MODE = 2
664 19:26:20.479463 RX_GATING_TRACK_MODE = 2
665 19:26:20.479555 SELPH_MODE = 1
666 19:26:20.482998 PICG_EARLY_EN = 1
667 19:26:20.486506 VALID_LAT_VALUE = 1
668 19:26:20.494003 ==============================================================
669 19:26:20.497888 Enter into Gating configuration >>>>
670 19:26:20.497976 Exit from Gating configuration <<<<
671 19:26:20.501326 Enter into DVFS_PRE_config >>>>>
672 19:26:20.511797 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
673 19:26:20.515867 Exit from DVFS_PRE_config <<<<<
674 19:26:20.519432 Enter into PICG configuration >>>>
675 19:26:20.522729 Exit from PICG configuration <<<<
676 19:26:20.526459 [RX_INPUT] configuration >>>>>
677 19:26:20.526545 [RX_INPUT] configuration <<<<<
678 19:26:20.533961 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
679 19:26:20.537489 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
680 19:26:20.544826 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
681 19:26:20.552453 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
682 19:26:20.555854 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
683 19:26:20.563557 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
684 19:26:20.566984 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
685 19:26:20.570715 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
686 19:26:20.574106 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
687 19:26:20.581720 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
688 19:26:20.585325 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
689 19:26:20.588892 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
690 19:26:20.592828 ===================================
691 19:26:20.592913 LPDDR4 DRAM CONFIGURATION
692 19:26:20.596279 ===================================
693 19:26:20.600197 EX_ROW_EN[0] = 0x0
694 19:26:20.600280 EX_ROW_EN[1] = 0x0
695 19:26:20.603687 LP4Y_EN = 0x0
696 19:26:20.603771 WORK_FSP = 0x0
697 19:26:20.607200 WL = 0x2
698 19:26:20.607284 RL = 0x2
699 19:26:20.611213 BL = 0x2
700 19:26:20.611297 RPST = 0x0
701 19:26:20.614636 RD_PRE = 0x0
702 19:26:20.614720 WR_PRE = 0x1
703 19:26:20.618540 WR_PST = 0x0
704 19:26:20.618624 DBI_WR = 0x0
705 19:26:20.618690 DBI_RD = 0x0
706 19:26:20.622185 OTF = 0x1
707 19:26:20.625685 ===================================
708 19:26:20.629868 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
709 19:26:20.633296 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
710 19:26:20.636606 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
711 19:26:20.640239 ===================================
712 19:26:20.644041 LPDDR4 DRAM CONFIGURATION
713 19:26:20.647857 ===================================
714 19:26:20.647942 EX_ROW_EN[0] = 0x10
715 19:26:20.651157 EX_ROW_EN[1] = 0x0
716 19:26:20.651240 LP4Y_EN = 0x0
717 19:26:20.655135 WORK_FSP = 0x0
718 19:26:20.655219 WL = 0x2
719 19:26:20.658375 RL = 0x2
720 19:26:20.658485 BL = 0x2
721 19:26:20.662410 RPST = 0x0
722 19:26:20.662494 RD_PRE = 0x0
723 19:26:20.666041 WR_PRE = 0x1
724 19:26:20.666131 WR_PST = 0x0
725 19:26:20.670113 DBI_WR = 0x0
726 19:26:20.670197 DBI_RD = 0x0
727 19:26:20.673694 OTF = 0x1
728 19:26:20.673778 ===================================
729 19:26:20.680641 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
730 19:26:20.685404 nWR fixed to 40
731 19:26:20.688609 [ModeRegInit_LP4] CH0 RK0
732 19:26:20.688700 [ModeRegInit_LP4] CH0 RK1
733 19:26:20.692229 [ModeRegInit_LP4] CH1 RK0
734 19:26:20.692314 [ModeRegInit_LP4] CH1 RK1
735 19:26:20.696209 match AC timing 13
736 19:26:20.699715 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
737 19:26:20.703793 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
738 19:26:20.707105 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
739 19:26:20.714536 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
740 19:26:20.718496 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
741 19:26:20.718581 [EMI DOE] emi_dcm 0
742 19:26:20.725581 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
743 19:26:20.725662 ==
744 19:26:20.729655 Dram Type= 6, Freq= 0, CH_0, rank 0
745 19:26:20.733068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
746 19:26:20.733153 ==
747 19:26:20.737149 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
748 19:26:20.744384 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
749 19:26:20.752888 [CA 0] Center 38 (7~69) winsize 63
750 19:26:20.756404 [CA 1] Center 38 (7~69) winsize 63
751 19:26:20.759928 [CA 2] Center 35 (5~66) winsize 62
752 19:26:20.763936 [CA 3] Center 35 (5~66) winsize 62
753 19:26:20.767484 [CA 4] Center 34 (4~65) winsize 62
754 19:26:20.771041 [CA 5] Center 34 (4~65) winsize 62
755 19:26:20.771187
756 19:26:20.775578 [CmdBusTrainingLP45] Vref(ca) range 1: 34
757 19:26:20.775663
758 19:26:20.778420 [CATrainingPosCal] consider 1 rank data
759 19:26:20.778506 u2DelayCellTimex100 = 270/100 ps
760 19:26:20.785043 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
761 19:26:20.788506 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
762 19:26:20.791560 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
763 19:26:20.795267 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
764 19:26:20.798443 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
765 19:26:20.801431 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
766 19:26:20.801558
767 19:26:20.804951 CA PerBit enable=1, Macro0, CA PI delay=34
768 19:26:20.805036
769 19:26:20.808567 [CBTSetCACLKResult] CA Dly = 34
770 19:26:20.811936 CS Dly: 5 (0~36)
771 19:26:20.812028 ==
772 19:26:20.815218 Dram Type= 6, Freq= 0, CH_0, rank 1
773 19:26:20.818623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 19:26:20.818723 ==
775 19:26:20.824774 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
776 19:26:20.828293 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
777 19:26:20.838727 [CA 0] Center 38 (7~69) winsize 63
778 19:26:20.842108 [CA 1] Center 38 (7~69) winsize 63
779 19:26:20.845500 [CA 2] Center 35 (5~66) winsize 62
780 19:26:20.848422 [CA 3] Center 35 (5~66) winsize 62
781 19:26:20.852191 [CA 4] Center 34 (4~65) winsize 62
782 19:26:20.855181 [CA 5] Center 34 (4~65) winsize 62
783 19:26:20.855255
784 19:26:20.858855 [CmdBusTrainingLP45] Vref(ca) range 1: 32
785 19:26:20.858950
786 19:26:20.862163 [CATrainingPosCal] consider 2 rank data
787 19:26:20.865409 u2DelayCellTimex100 = 270/100 ps
788 19:26:20.868947 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
789 19:26:20.871985 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
790 19:26:20.878515 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
791 19:26:20.881842 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
792 19:26:20.885599 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
793 19:26:20.888696 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
794 19:26:20.888773
795 19:26:20.892154 CA PerBit enable=1, Macro0, CA PI delay=34
796 19:26:20.892253
797 19:26:20.895410 [CBTSetCACLKResult] CA Dly = 34
798 19:26:20.895510 CS Dly: 5 (0~37)
799 19:26:20.895603
800 19:26:20.901809 ----->DramcWriteLeveling(PI) begin...
801 19:26:20.901892 ==
802 19:26:20.904970 Dram Type= 6, Freq= 0, CH_0, rank 0
803 19:26:20.908574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
804 19:26:20.908648 ==
805 19:26:20.911859 Write leveling (Byte 0): 33 => 33
806 19:26:20.914792 Write leveling (Byte 1): 31 => 31
807 19:26:20.918166 DramcWriteLeveling(PI) end<-----
808 19:26:20.918242
809 19:26:20.918305 ==
810 19:26:20.922059 Dram Type= 6, Freq= 0, CH_0, rank 0
811 19:26:20.924931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
812 19:26:20.925028 ==
813 19:26:20.928212 [Gating] SW mode calibration
814 19:26:20.935437 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
815 19:26:20.938305 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
816 19:26:20.945434 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
817 19:26:20.948556 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
818 19:26:20.951454 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
819 19:26:20.958583 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
820 19:26:20.961798 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 19:26:20.965013 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 19:26:20.971756 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 19:26:20.975560 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 19:26:20.978987 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 19:26:20.982594 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 19:26:20.989949 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 19:26:20.993580 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 19:26:20.997215 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 19:26:21.000515 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 19:26:21.008270 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 19:26:21.011230 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 19:26:21.014726 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 19:26:21.017443 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 19:26:21.024505 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
835 19:26:21.027944 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
836 19:26:21.031106 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 19:26:21.037657 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 19:26:21.041009 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 19:26:21.044626 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 19:26:21.051067 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
841 19:26:21.054571 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 19:26:21.058055 0 9 8 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 1)
843 19:26:21.064504 0 9 12 | B1->B0 | 2424 3030 | 0 0 | (0 0) (1 1)
844 19:26:21.067492 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
845 19:26:21.071015 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
846 19:26:21.077408 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
847 19:26:21.081060 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
848 19:26:21.084245 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
849 19:26:21.091065 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
850 19:26:21.094647 0 10 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
851 19:26:21.097442 0 10 12 | B1->B0 | 2e2e 2424 | 0 0 | (0 0) (0 0)
852 19:26:21.100947 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 19:26:21.107678 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 19:26:21.111101 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 19:26:21.114656 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 19:26:21.121029 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 19:26:21.123991 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 19:26:21.127735 0 11 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
859 19:26:21.134343 0 11 12 | B1->B0 | 3535 4444 | 1 0 | (0 0) (0 0)
860 19:26:21.137540 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
861 19:26:21.141156 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
862 19:26:21.147900 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
863 19:26:21.150765 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
864 19:26:21.154255 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
865 19:26:21.160707 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
866 19:26:21.164197 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
867 19:26:21.169457 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
868 19:26:21.174248 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
869 19:26:21.177827 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
870 19:26:21.180529 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
871 19:26:21.187757 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
872 19:26:21.190826 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
873 19:26:21.193954 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
874 19:26:21.200749 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 19:26:21.204201 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 19:26:21.207649 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 19:26:21.210919 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 19:26:21.217639 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 19:26:21.221201 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 19:26:21.224033 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 19:26:21.231135 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 19:26:21.234045 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 19:26:21.237416 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
884 19:26:21.243889 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
885 19:26:21.247783 Total UI for P1: 0, mck2ui 16
886 19:26:21.250567 best dqsien dly found for B0: ( 0, 14, 12)
887 19:26:21.250656 Total UI for P1: 0, mck2ui 16
888 19:26:21.257464 best dqsien dly found for B1: ( 0, 14, 12)
889 19:26:21.260886 best DQS0 dly(MCK, UI, PI) = (0, 14, 12)
890 19:26:21.263916 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
891 19:26:21.264026
892 19:26:21.267440 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 12)
893 19:26:21.270560 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
894 19:26:21.274053 [Gating] SW calibration Done
895 19:26:21.274133 ==
896 19:26:21.277688 Dram Type= 6, Freq= 0, CH_0, rank 0
897 19:26:21.280593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
898 19:26:21.280685 ==
899 19:26:21.284030 RX Vref Scan: 0
900 19:26:21.284115
901 19:26:21.284204 RX Vref 0 -> 0, step: 1
902 19:26:21.284268
903 19:26:21.287684 RX Delay -130 -> 252, step: 16
904 19:26:21.294041 iDelay=206, Bit 0, Center 77 (-50 ~ 205) 256
905 19:26:21.297986 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
906 19:26:21.300836 iDelay=206, Bit 2, Center 77 (-50 ~ 205) 256
907 19:26:21.304002 iDelay=206, Bit 3, Center 77 (-50 ~ 205) 256
908 19:26:21.307532 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
909 19:26:21.310700 iDelay=206, Bit 5, Center 69 (-50 ~ 189) 240
910 19:26:21.317682 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
911 19:26:21.321013 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
912 19:26:21.324475 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
913 19:26:21.327314 iDelay=206, Bit 9, Center 61 (-66 ~ 189) 256
914 19:26:21.330944 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
915 19:26:21.337311 iDelay=206, Bit 11, Center 61 (-66 ~ 189) 256
916 19:26:21.340880 iDelay=206, Bit 12, Center 77 (-50 ~ 205) 256
917 19:26:21.344170 iDelay=206, Bit 13, Center 77 (-50 ~ 205) 256
918 19:26:21.347207 iDelay=206, Bit 14, Center 77 (-50 ~ 205) 256
919 19:26:21.353899 iDelay=206, Bit 15, Center 77 (-50 ~ 205) 256
920 19:26:21.354003 ==
921 19:26:21.357301 Dram Type= 6, Freq= 0, CH_0, rank 0
922 19:26:21.360716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
923 19:26:21.360813 ==
924 19:26:21.360908 DQS Delay:
925 19:26:21.363957 DQS0 = 0, DQS1 = 0
926 19:26:21.364056 DQM Delay:
927 19:26:21.367147 DQM0 = 80, DQM1 = 70
928 19:26:21.367255 DQ Delay:
929 19:26:21.370487 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
930 19:26:21.374344 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =85
931 19:26:21.377356 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
932 19:26:21.380985 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
933 19:26:21.381096
934 19:26:21.381191
935 19:26:21.381281 ==
936 19:26:21.384111 Dram Type= 6, Freq= 0, CH_0, rank 0
937 19:26:21.388365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
938 19:26:21.388476 ==
939 19:26:21.388575
940 19:26:21.388665
941 19:26:21.391636 TX Vref Scan disable
942 19:26:21.391782 == TX Byte 0 ==
943 19:26:21.398011 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
944 19:26:21.401404 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
945 19:26:21.401487 == TX Byte 1 ==
946 19:26:21.407839 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
947 19:26:21.411659 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
948 19:26:21.411769 ==
949 19:26:21.414937 Dram Type= 6, Freq= 0, CH_0, rank 0
950 19:26:21.418057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
951 19:26:21.418142 ==
952 19:26:21.432329 TX Vref=22, minBit 12, minWin=26, winSum=434
953 19:26:21.435736 TX Vref=24, minBit 8, minWin=26, winSum=434
954 19:26:21.438806 TX Vref=26, minBit 14, minWin=26, winSum=437
955 19:26:21.442201 TX Vref=28, minBit 4, minWin=27, winSum=441
956 19:26:21.445789 TX Vref=30, minBit 4, minWin=27, winSum=440
957 19:26:21.449245 TX Vref=32, minBit 10, minWin=26, winSum=439
958 19:26:21.455687 [TxChooseVref] Worse bit 4, Min win 27, Win sum 441, Final Vref 28
959 19:26:21.455779
960 19:26:21.459259 Final TX Range 1 Vref 28
961 19:26:21.459346
962 19:26:21.459448 ==
963 19:26:21.462452 Dram Type= 6, Freq= 0, CH_0, rank 0
964 19:26:21.466036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
965 19:26:21.466155 ==
966 19:26:21.466259
967 19:26:21.468751
968 19:26:21.468835 TX Vref Scan disable
969 19:26:21.472550 == TX Byte 0 ==
970 19:26:21.475832 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
971 19:26:21.479307 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
972 19:26:21.482232 == TX Byte 1 ==
973 19:26:21.485516 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
974 19:26:21.488919 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
975 19:26:21.492194
976 19:26:21.492297 [DATLAT]
977 19:26:21.492390 Freq=800, CH0 RK0
978 19:26:21.492481
979 19:26:21.495393 DATLAT Default: 0xa
980 19:26:21.495504 0, 0xFFFF, sum = 0
981 19:26:21.499028 1, 0xFFFF, sum = 0
982 19:26:21.499117 2, 0xFFFF, sum = 0
983 19:26:21.502552 3, 0xFFFF, sum = 0
984 19:26:21.502637 4, 0xFFFF, sum = 0
985 19:26:21.505611 5, 0xFFFF, sum = 0
986 19:26:21.509001 6, 0xFFFF, sum = 0
987 19:26:21.509078 7, 0xFFFF, sum = 0
988 19:26:21.512375 8, 0xFFFF, sum = 0
989 19:26:21.512477 9, 0x0, sum = 1
990 19:26:21.512569 10, 0x0, sum = 2
991 19:26:21.515345 11, 0x0, sum = 3
992 19:26:21.515425 12, 0x0, sum = 4
993 19:26:21.518738 best_step = 10
994 19:26:21.518866
995 19:26:21.518983 ==
996 19:26:21.522057 Dram Type= 6, Freq= 0, CH_0, rank 0
997 19:26:21.525771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
998 19:26:21.525884 ==
999 19:26:21.529143 RX Vref Scan: 1
1000 19:26:21.529249
1001 19:26:21.529356 Set Vref Range= 32 -> 127
1002 19:26:21.532594
1003 19:26:21.532756 RX Vref 32 -> 127, step: 1
1004 19:26:21.532874
1005 19:26:21.535889 RX Delay -111 -> 252, step: 8
1006 19:26:21.536001
1007 19:26:21.538974 Set Vref, RX VrefLevel [Byte0]: 32
1008 19:26:21.542564 [Byte1]: 32
1009 19:26:21.542665
1010 19:26:21.545465 Set Vref, RX VrefLevel [Byte0]: 33
1011 19:26:21.549049 [Byte1]: 33
1012 19:26:21.552979
1013 19:26:21.553082 Set Vref, RX VrefLevel [Byte0]: 34
1014 19:26:21.555834 [Byte1]: 34
1015 19:26:21.560513
1016 19:26:21.560622 Set Vref, RX VrefLevel [Byte0]: 35
1017 19:26:21.563877 [Byte1]: 35
1018 19:26:21.568368
1019 19:26:21.568476 Set Vref, RX VrefLevel [Byte0]: 36
1020 19:26:21.571317 [Byte1]: 36
1021 19:26:21.575898
1022 19:26:21.576013 Set Vref, RX VrefLevel [Byte0]: 37
1023 19:26:21.579195 [Byte1]: 37
1024 19:26:21.583361
1025 19:26:21.583478 Set Vref, RX VrefLevel [Byte0]: 38
1026 19:26:21.586416 [Byte1]: 38
1027 19:26:21.590943
1028 19:26:21.591076 Set Vref, RX VrefLevel [Byte0]: 39
1029 19:26:21.594548 [Byte1]: 39
1030 19:26:21.598829
1031 19:26:21.598971 Set Vref, RX VrefLevel [Byte0]: 40
1032 19:26:21.602202 [Byte1]: 40
1033 19:26:21.606449
1034 19:26:21.606552 Set Vref, RX VrefLevel [Byte0]: 41
1035 19:26:21.609684 [Byte1]: 41
1036 19:26:21.613953
1037 19:26:21.614056 Set Vref, RX VrefLevel [Byte0]: 42
1038 19:26:21.617087 [Byte1]: 42
1039 19:26:21.622035
1040 19:26:21.622166 Set Vref, RX VrefLevel [Byte0]: 43
1041 19:26:21.624728 [Byte1]: 43
1042 19:26:21.629321
1043 19:26:21.629433 Set Vref, RX VrefLevel [Byte0]: 44
1044 19:26:21.632630 [Byte1]: 44
1045 19:26:21.637386
1046 19:26:21.637498 Set Vref, RX VrefLevel [Byte0]: 45
1047 19:26:21.640727 [Byte1]: 45
1048 19:26:21.645089
1049 19:26:21.645191 Set Vref, RX VrefLevel [Byte0]: 46
1050 19:26:21.648102 [Byte1]: 46
1051 19:26:21.652660
1052 19:26:21.652760 Set Vref, RX VrefLevel [Byte0]: 47
1053 19:26:21.656115 [Byte1]: 47
1054 19:26:21.660171
1055 19:26:21.660306 Set Vref, RX VrefLevel [Byte0]: 48
1056 19:26:21.663716 [Byte1]: 48
1057 19:26:21.667682
1058 19:26:21.667798 Set Vref, RX VrefLevel [Byte0]: 49
1059 19:26:21.671079 [Byte1]: 49
1060 19:26:21.675086
1061 19:26:21.675196 Set Vref, RX VrefLevel [Byte0]: 50
1062 19:26:21.678627 [Byte1]: 50
1063 19:26:21.682797
1064 19:26:21.682958 Set Vref, RX VrefLevel [Byte0]: 51
1065 19:26:21.686089 [Byte1]: 51
1066 19:26:21.690272
1067 19:26:21.690380 Set Vref, RX VrefLevel [Byte0]: 52
1068 19:26:21.693823 [Byte1]: 52
1069 19:26:21.697942
1070 19:26:21.698051 Set Vref, RX VrefLevel [Byte0]: 53
1071 19:26:21.701485 [Byte1]: 53
1072 19:26:21.705785
1073 19:26:21.705867 Set Vref, RX VrefLevel [Byte0]: 54
1074 19:26:21.708974 [Byte1]: 54
1075 19:26:21.713627
1076 19:26:21.713736 Set Vref, RX VrefLevel [Byte0]: 55
1077 19:26:21.716616 [Byte1]: 55
1078 19:26:21.720931
1079 19:26:21.721093 Set Vref, RX VrefLevel [Byte0]: 56
1080 19:26:21.724039 [Byte1]: 56
1081 19:26:21.728866
1082 19:26:21.729004 Set Vref, RX VrefLevel [Byte0]: 57
1083 19:26:21.731744 [Byte1]: 57
1084 19:26:21.736338
1085 19:26:21.736452 Set Vref, RX VrefLevel [Byte0]: 58
1086 19:26:21.739552 [Byte1]: 58
1087 19:26:21.744297
1088 19:26:21.744403 Set Vref, RX VrefLevel [Byte0]: 59
1089 19:26:21.747308 [Byte1]: 59
1090 19:26:21.751394
1091 19:26:21.751501 Set Vref, RX VrefLevel [Byte0]: 60
1092 19:26:21.754899 [Byte1]: 60
1093 19:26:21.759146
1094 19:26:21.759252 Set Vref, RX VrefLevel [Byte0]: 61
1095 19:26:21.762527 [Byte1]: 61
1096 19:26:21.766669
1097 19:26:21.766795 Set Vref, RX VrefLevel [Byte0]: 62
1098 19:26:21.770339 [Byte1]: 62
1099 19:26:21.774469
1100 19:26:21.774579 Set Vref, RX VrefLevel [Byte0]: 63
1101 19:26:21.778039 [Byte1]: 63
1102 19:26:21.782147
1103 19:26:21.782232 Set Vref, RX VrefLevel [Byte0]: 64
1104 19:26:21.785601 [Byte1]: 64
1105 19:26:21.789744
1106 19:26:21.789819 Set Vref, RX VrefLevel [Byte0]: 65
1107 19:26:21.793098 [Byte1]: 65
1108 19:26:21.797270
1109 19:26:21.797353 Set Vref, RX VrefLevel [Byte0]: 66
1110 19:26:21.800594 [Byte1]: 66
1111 19:26:21.805321
1112 19:26:21.805404 Set Vref, RX VrefLevel [Byte0]: 67
1113 19:26:21.808193 [Byte1]: 67
1114 19:26:21.812570
1115 19:26:21.812654 Set Vref, RX VrefLevel [Byte0]: 68
1116 19:26:21.816234 [Byte1]: 68
1117 19:26:21.820351
1118 19:26:21.820460 Set Vref, RX VrefLevel [Byte0]: 69
1119 19:26:21.823846 [Byte1]: 69
1120 19:26:21.827936
1121 19:26:21.828017 Set Vref, RX VrefLevel [Byte0]: 70
1122 19:26:21.831412 [Byte1]: 70
1123 19:26:21.835907
1124 19:26:21.835991 Set Vref, RX VrefLevel [Byte0]: 71
1125 19:26:21.838851 [Byte1]: 71
1126 19:26:21.843148
1127 19:26:21.843271 Set Vref, RX VrefLevel [Byte0]: 72
1128 19:26:21.846559 [Byte1]: 72
1129 19:26:21.850842
1130 19:26:21.850923 Set Vref, RX VrefLevel [Byte0]: 73
1131 19:26:21.854103 [Byte1]: 73
1132 19:26:21.858421
1133 19:26:21.858503 Set Vref, RX VrefLevel [Byte0]: 74
1134 19:26:21.861974 [Byte1]: 74
1135 19:26:21.866412
1136 19:26:21.866498 Set Vref, RX VrefLevel [Byte0]: 75
1137 19:26:21.869497 [Byte1]: 75
1138 19:26:21.874018
1139 19:26:21.874101 Set Vref, RX VrefLevel [Byte0]: 76
1140 19:26:21.877548 [Byte1]: 76
1141 19:26:21.881891
1142 19:26:21.881998 Final RX Vref Byte 0 = 56 to rank0
1143 19:26:21.884800 Final RX Vref Byte 1 = 53 to rank0
1144 19:26:21.888198 Final RX Vref Byte 0 = 56 to rank1
1145 19:26:21.891682 Final RX Vref Byte 1 = 53 to rank1==
1146 19:26:21.895168 Dram Type= 6, Freq= 0, CH_0, rank 0
1147 19:26:21.898612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1148 19:26:21.901481 ==
1149 19:26:21.901607 DQS Delay:
1150 19:26:21.901672 DQS0 = 0, DQS1 = 0
1151 19:26:21.904784 DQM Delay:
1152 19:26:21.904891 DQM0 = 81, DQM1 = 68
1153 19:26:21.908279 DQ Delay:
1154 19:26:21.911797 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1155 19:26:21.911879 DQ4 =80, DQ5 =68, DQ6 =88, DQ7 =92
1156 19:26:21.914803 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1157 19:26:21.918203 DQ12 =72, DQ13 =72, DQ14 =80, DQ15 =76
1158 19:26:21.921499
1159 19:26:21.921621
1160 19:26:21.928140 [DQSOSCAuto] RK0, (LSB)MR18= 0x2423, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 400 ps
1161 19:26:21.931492 CH0 RK0: MR19=606, MR18=2423
1162 19:26:21.938497 CH0_RK0: MR19=0x606, MR18=0x2423, DQSOSC=400, MR23=63, INC=92, DEC=61
1163 19:26:21.938583
1164 19:26:21.941567 ----->DramcWriteLeveling(PI) begin...
1165 19:26:21.941650 ==
1166 19:26:21.944501 Dram Type= 6, Freq= 0, CH_0, rank 1
1167 19:26:21.947999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1168 19:26:21.948097 ==
1169 19:26:21.951467 Write leveling (Byte 0): 34 => 34
1170 19:26:21.954686 Write leveling (Byte 1): 30 => 30
1171 19:26:21.958006 DramcWriteLeveling(PI) end<-----
1172 19:26:21.958088
1173 19:26:21.958152 ==
1174 19:26:21.961223 Dram Type= 6, Freq= 0, CH_0, rank 1
1175 19:26:21.964699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1176 19:26:21.964782 ==
1177 19:26:21.968575 [Gating] SW mode calibration
1178 19:26:21.974983 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1179 19:26:21.981784 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1180 19:26:21.984885 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1181 19:26:21.988294 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1182 19:26:21.995175 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1183 19:26:21.998506 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 19:26:22.001465 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 19:26:22.008495 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 19:26:22.011592 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 19:26:22.015236 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 19:26:22.018783 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 19:26:22.025193 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 19:26:22.028478 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 19:26:22.031503 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 19:26:22.038554 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 19:26:22.042128 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 19:26:22.045127 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 19:26:22.051591 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 19:26:22.055057 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 19:26:22.058459 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1198 19:26:22.106215 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1199 19:26:22.106358 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1200 19:26:22.106616 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 19:26:22.106684 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 19:26:22.106746 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 19:26:22.107293 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 19:26:22.107376 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 19:26:22.107631 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1206 19:26:22.107698 0 9 8 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
1207 19:26:22.108057 0 9 12 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
1208 19:26:22.141995 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1209 19:26:22.142148 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1210 19:26:22.142639 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1211 19:26:22.143323 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1212 19:26:22.143607 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1213 19:26:22.143886 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
1214 19:26:22.143953 0 10 8 | B1->B0 | 3131 2929 | 0 1 | (0 0) (1 0)
1215 19:26:22.144529 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 19:26:22.146813 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 19:26:22.150313 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 19:26:22.153850 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 19:26:22.157268 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 19:26:22.160735 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 19:26:22.163512 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1222 19:26:22.170322 0 11 8 | B1->B0 | 3131 4141 | 0 0 | (1 1) (0 0)
1223 19:26:22.173552 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
1224 19:26:22.177015 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1225 19:26:22.183637 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1226 19:26:22.187113 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1227 19:26:22.190598 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1228 19:26:22.197053 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1229 19:26:22.200672 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1230 19:26:22.203534 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1231 19:26:22.210555 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1232 19:26:22.213833 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1233 19:26:22.217350 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1234 19:26:22.221361 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1235 19:26:22.225082 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1236 19:26:22.232138 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1237 19:26:22.235575 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1238 19:26:22.238848 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1239 19:26:22.246035 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1240 19:26:22.249443 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1241 19:26:22.252368 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1242 19:26:22.255888 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1243 19:26:22.262984 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1244 19:26:22.265721 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1245 19:26:22.269394 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1246 19:26:22.275722 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1247 19:26:22.279258 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1248 19:26:22.282643 Total UI for P1: 0, mck2ui 16
1249 19:26:22.286052 best dqsien dly found for B0: ( 0, 14, 6)
1250 19:26:22.289780 Total UI for P1: 0, mck2ui 16
1251 19:26:22.292552 best dqsien dly found for B1: ( 0, 14, 10)
1252 19:26:22.296028 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1253 19:26:22.299435 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1254 19:26:22.299518
1255 19:26:22.302949 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1256 19:26:22.305859 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1257 19:26:22.309344 [Gating] SW calibration Done
1258 19:26:22.309426 ==
1259 19:26:22.312873 Dram Type= 6, Freq= 0, CH_0, rank 1
1260 19:26:22.316410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1261 19:26:22.316492 ==
1262 19:26:22.319234 RX Vref Scan: 0
1263 19:26:22.319316
1264 19:26:22.322700 RX Vref 0 -> 0, step: 1
1265 19:26:22.322782
1266 19:26:22.326073 RX Delay -130 -> 252, step: 16
1267 19:26:22.329670 iDelay=206, Bit 0, Center 77 (-50 ~ 205) 256
1268 19:26:22.332474 iDelay=206, Bit 1, Center 77 (-50 ~ 205) 256
1269 19:26:22.335995 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1270 19:26:22.339216 iDelay=206, Bit 3, Center 69 (-50 ~ 189) 240
1271 19:26:22.345940 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
1272 19:26:22.348881 iDelay=206, Bit 5, Center 69 (-50 ~ 189) 240
1273 19:26:22.352257 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1274 19:26:22.355476 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1275 19:26:22.359279 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1276 19:26:22.365603 iDelay=206, Bit 9, Center 53 (-66 ~ 173) 240
1277 19:26:22.369157 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1278 19:26:22.372294 iDelay=206, Bit 11, Center 61 (-66 ~ 189) 256
1279 19:26:22.375718 iDelay=206, Bit 12, Center 77 (-50 ~ 205) 256
1280 19:26:22.378671 iDelay=206, Bit 13, Center 77 (-50 ~ 205) 256
1281 19:26:22.385400 iDelay=206, Bit 14, Center 77 (-50 ~ 205) 256
1282 19:26:22.388546 iDelay=206, Bit 15, Center 77 (-50 ~ 205) 256
1283 19:26:22.388630 ==
1284 19:26:22.391995 Dram Type= 6, Freq= 0, CH_0, rank 1
1285 19:26:22.395446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1286 19:26:22.395529 ==
1287 19:26:22.398993 DQS Delay:
1288 19:26:22.399075 DQS0 = 0, DQS1 = 0
1289 19:26:22.399139 DQM Delay:
1290 19:26:22.401893 DQM0 = 76, DQM1 = 70
1291 19:26:22.401975 DQ Delay:
1292 19:26:22.405255 DQ0 =77, DQ1 =77, DQ2 =69, DQ3 =69
1293 19:26:22.408946 DQ4 =77, DQ5 =69, DQ6 =85, DQ7 =85
1294 19:26:22.411872 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =61
1295 19:26:22.415278 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1296 19:26:22.415360
1297 19:26:22.415424
1298 19:26:22.415482 ==
1299 19:26:22.418717 Dram Type= 6, Freq= 0, CH_0, rank 1
1300 19:26:22.425456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1301 19:26:22.425575 ==
1302 19:26:22.425640
1303 19:26:22.425700
1304 19:26:22.425758 TX Vref Scan disable
1305 19:26:22.428656 == TX Byte 0 ==
1306 19:26:22.432212 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1307 19:26:22.439045 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1308 19:26:22.439128 == TX Byte 1 ==
1309 19:26:22.442313 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1310 19:26:22.448947 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1311 19:26:22.449030 ==
1312 19:26:22.452522 Dram Type= 6, Freq= 0, CH_0, rank 1
1313 19:26:22.455425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1314 19:26:22.455507 ==
1315 19:26:22.468628 TX Vref=22, minBit 1, minWin=27, winSum=435
1316 19:26:22.471233 TX Vref=24, minBit 1, minWin=27, winSum=438
1317 19:26:22.474850 TX Vref=26, minBit 1, minWin=27, winSum=439
1318 19:26:22.478194 TX Vref=28, minBit 1, minWin=27, winSum=442
1319 19:26:22.481412 TX Vref=30, minBit 2, minWin=27, winSum=444
1320 19:26:22.488692 TX Vref=32, minBit 2, minWin=27, winSum=440
1321 19:26:22.491824 [TxChooseVref] Worse bit 2, Min win 27, Win sum 444, Final Vref 30
1322 19:26:22.491908
1323 19:26:22.494879 Final TX Range 1 Vref 30
1324 19:26:22.494962
1325 19:26:22.495025 ==
1326 19:26:22.498161 Dram Type= 6, Freq= 0, CH_0, rank 1
1327 19:26:22.501449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1328 19:26:22.501555 ==
1329 19:26:22.504525
1330 19:26:22.504607
1331 19:26:22.504669 TX Vref Scan disable
1332 19:26:22.508272 == TX Byte 0 ==
1333 19:26:22.511698 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1334 19:26:22.518201 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1335 19:26:22.518312 == TX Byte 1 ==
1336 19:26:22.521685 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1337 19:26:22.525243 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1338 19:26:22.528519
1339 19:26:22.528622 [DATLAT]
1340 19:26:22.528711 Freq=800, CH0 RK1
1341 19:26:22.528798
1342 19:26:22.531943 DATLAT Default: 0xa
1343 19:26:22.532040 0, 0xFFFF, sum = 0
1344 19:26:22.535274 1, 0xFFFF, sum = 0
1345 19:26:22.535383 2, 0xFFFF, sum = 0
1346 19:26:22.538315 3, 0xFFFF, sum = 0
1347 19:26:22.538414 4, 0xFFFF, sum = 0
1348 19:26:22.541743 5, 0xFFFF, sum = 0
1349 19:26:22.544675 6, 0xFFFF, sum = 0
1350 19:26:22.544774 7, 0xFFFF, sum = 0
1351 19:26:22.548003 8, 0xFFFF, sum = 0
1352 19:26:22.548098 9, 0x0, sum = 1
1353 19:26:22.548186 10, 0x0, sum = 2
1354 19:26:22.551745 11, 0x0, sum = 3
1355 19:26:22.551815 12, 0x0, sum = 4
1356 19:26:22.555155 best_step = 10
1357 19:26:22.555222
1358 19:26:22.555279 ==
1359 19:26:22.558115 Dram Type= 6, Freq= 0, CH_0, rank 1
1360 19:26:22.561553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1361 19:26:22.561635 ==
1362 19:26:22.565021 RX Vref Scan: 0
1363 19:26:22.565101
1364 19:26:22.565164 RX Vref 0 -> 0, step: 1
1365 19:26:22.565223
1366 19:26:22.568051 RX Delay -111 -> 252, step: 8
1367 19:26:22.574927 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
1368 19:26:22.578191 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1369 19:26:22.581880 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1370 19:26:22.585000 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1371 19:26:22.588612 iDelay=209, Bit 4, Center 76 (-39 ~ 192) 232
1372 19:26:22.594951 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1373 19:26:22.598211 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1374 19:26:22.601535 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1375 19:26:22.605214 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1376 19:26:22.608341 iDelay=209, Bit 9, Center 56 (-55 ~ 168) 224
1377 19:26:22.615225 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1378 19:26:22.618525 iDelay=209, Bit 11, Center 60 (-55 ~ 176) 232
1379 19:26:22.622184 iDelay=209, Bit 12, Center 76 (-39 ~ 192) 232
1380 19:26:22.625200 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
1381 19:26:22.628603 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1382 19:26:22.635148 iDelay=209, Bit 15, Center 76 (-39 ~ 192) 232
1383 19:26:22.635231 ==
1384 19:26:22.638380 Dram Type= 6, Freq= 0, CH_0, rank 1
1385 19:26:22.641840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1386 19:26:22.641921 ==
1387 19:26:22.641984 DQS Delay:
1388 19:26:22.645317 DQS0 = 0, DQS1 = 0
1389 19:26:22.645397 DQM Delay:
1390 19:26:22.648766 DQM0 = 79, DQM1 = 70
1391 19:26:22.648846 DQ Delay:
1392 19:26:22.651790 DQ0 =80, DQ1 =84, DQ2 =76, DQ3 =72
1393 19:26:22.655185 DQ4 =76, DQ5 =64, DQ6 =88, DQ7 =92
1394 19:26:22.658614 DQ8 =60, DQ9 =56, DQ10 =72, DQ11 =60
1395 19:26:22.662166 DQ12 =76, DQ13 =80, DQ14 =80, DQ15 =76
1396 19:26:22.662246
1397 19:26:22.662308
1398 19:26:22.668488 [DQSOSCAuto] RK1, (LSB)MR18= 0x4924, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
1399 19:26:22.671974 CH0 RK1: MR19=606, MR18=4924
1400 19:26:22.678525 CH0_RK1: MR19=0x606, MR18=0x4924, DQSOSC=391, MR23=63, INC=96, DEC=64
1401 19:26:22.682022 [RxdqsGatingPostProcess] freq 800
1402 19:26:22.688625 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1403 19:26:22.688706 Pre-setting of DQS Precalculation
1404 19:26:22.695469 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1405 19:26:22.695551 ==
1406 19:26:22.698932 Dram Type= 6, Freq= 0, CH_1, rank 0
1407 19:26:22.702137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1408 19:26:22.702219 ==
1409 19:26:22.708554 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1410 19:26:22.715253 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1411 19:26:22.723265 [CA 0] Center 36 (6~67) winsize 62
1412 19:26:22.726790 [CA 1] Center 36 (6~67) winsize 62
1413 19:26:22.730118 [CA 2] Center 35 (5~65) winsize 61
1414 19:26:22.733268 [CA 3] Center 34 (4~64) winsize 61
1415 19:26:22.736880 [CA 4] Center 34 (5~64) winsize 60
1416 19:26:22.740271 [CA 5] Center 34 (4~64) winsize 61
1417 19:26:22.740350
1418 19:26:22.743473 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1419 19:26:22.743554
1420 19:26:22.746706 [CATrainingPosCal] consider 1 rank data
1421 19:26:22.750020 u2DelayCellTimex100 = 270/100 ps
1422 19:26:22.753461 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1423 19:26:22.757169 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1424 19:26:22.763676 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1425 19:26:22.767059 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1426 19:26:22.770627 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
1427 19:26:22.773494 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1428 19:26:22.773631
1429 19:26:22.776991 CA PerBit enable=1, Macro0, CA PI delay=34
1430 19:26:22.777071
1431 19:26:22.779968 [CBTSetCACLKResult] CA Dly = 34
1432 19:26:22.780048 CS Dly: 5 (0~36)
1433 19:26:22.780111 ==
1434 19:26:22.783499 Dram Type= 6, Freq= 0, CH_1, rank 1
1435 19:26:22.789927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1436 19:26:22.790015 ==
1437 19:26:22.793311 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1438 19:26:22.800130 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1439 19:26:22.809365 [CA 0] Center 36 (6~67) winsize 62
1440 19:26:22.812811 [CA 1] Center 36 (6~67) winsize 62
1441 19:26:22.816172 [CA 2] Center 35 (5~65) winsize 61
1442 19:26:22.819648 [CA 3] Center 34 (4~64) winsize 61
1443 19:26:22.823088 [CA 4] Center 34 (4~65) winsize 62
1444 19:26:22.826032 [CA 5] Center 33 (3~64) winsize 62
1445 19:26:22.826117
1446 19:26:22.829424 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1447 19:26:22.829521
1448 19:26:22.833001 [CATrainingPosCal] consider 2 rank data
1449 19:26:22.836358 u2DelayCellTimex100 = 270/100 ps
1450 19:26:22.839263 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1451 19:26:22.842729 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1452 19:26:22.849462 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1453 19:26:22.852631 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1454 19:26:22.856539 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
1455 19:26:22.859799 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1456 19:26:22.859887
1457 19:26:22.863031 CA PerBit enable=1, Macro0, CA PI delay=34
1458 19:26:22.863114
1459 19:26:22.866156 [CBTSetCACLKResult] CA Dly = 34
1460 19:26:22.866238 CS Dly: 6 (0~38)
1461 19:26:22.866302
1462 19:26:22.869542 ----->DramcWriteLeveling(PI) begin...
1463 19:26:22.872877 ==
1464 19:26:22.872960 Dram Type= 6, Freq= 0, CH_1, rank 0
1465 19:26:22.880061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1466 19:26:22.880147 ==
1467 19:26:22.883987 Write leveling (Byte 0): 29 => 29
1468 19:26:22.884075 Write leveling (Byte 1): 29 => 29
1469 19:26:22.887657 DramcWriteLeveling(PI) end<-----
1470 19:26:22.887741
1471 19:26:22.887805 ==
1472 19:26:22.891167 Dram Type= 6, Freq= 0, CH_1, rank 0
1473 19:26:22.894750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1474 19:26:22.894835 ==
1475 19:26:22.898687 [Gating] SW mode calibration
1476 19:26:22.906066 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1477 19:26:22.909487 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1478 19:26:22.916812 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1479 19:26:22.920012 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1480 19:26:22.923539 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1481 19:26:22.930098 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 19:26:22.933636 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 19:26:22.937162 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 19:26:22.940063 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 19:26:22.946991 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 19:26:22.950423 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 19:26:22.953926 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 19:26:22.960086 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 19:26:22.963781 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 19:26:22.966598 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 19:26:22.973447 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 19:26:22.977008 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 19:26:22.980285 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 19:26:22.986764 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 19:26:22.990398 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 19:26:22.993403 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 19:26:22.999979 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 19:26:23.003269 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 19:26:23.006782 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 19:26:23.013730 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 19:26:23.016918 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 19:26:23.019835 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 19:26:23.026786 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 19:26:23.030114 0 9 8 | B1->B0 | 2424 2525 | 1 1 | (1 1) (1 1)
1505 19:26:23.033705 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1506 19:26:23.037089 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1507 19:26:23.043580 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1508 19:26:23.047010 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1509 19:26:23.050427 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1510 19:26:23.056708 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1511 19:26:23.060184 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (1 0) (1 0)
1512 19:26:23.063606 0 10 8 | B1->B0 | 2e2e 2e2e | 1 1 | (1 0) (1 0)
1513 19:26:23.070015 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 19:26:23.073229 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 19:26:23.076601 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 19:26:23.083559 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 19:26:23.086501 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 19:26:23.090042 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 19:26:23.096938 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1520 19:26:23.100123 0 11 8 | B1->B0 | 3a3a 3b3b | 0 1 | (0 0) (0 0)
1521 19:26:23.103609 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1522 19:26:23.110058 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1523 19:26:23.113536 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1524 19:26:23.116815 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1525 19:26:23.123231 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1526 19:26:23.126511 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1527 19:26:23.130138 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1528 19:26:23.133654 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1529 19:26:23.140248 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1530 19:26:23.143848 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1531 19:26:23.146751 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1532 19:26:23.153212 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1533 19:26:23.156616 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1534 19:26:23.160111 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1535 19:26:23.166614 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1536 19:26:23.170139 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1537 19:26:23.173490 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1538 19:26:23.180081 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1539 19:26:23.183069 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1540 19:26:23.187050 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1541 19:26:23.193314 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1542 19:26:23.196820 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1543 19:26:23.200425 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1544 19:26:23.206799 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1545 19:26:23.210131 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1546 19:26:23.213660 Total UI for P1: 0, mck2ui 16
1547 19:26:23.217016 best dqsien dly found for B0: ( 0, 14, 8)
1548 19:26:23.219879 Total UI for P1: 0, mck2ui 16
1549 19:26:23.223622 best dqsien dly found for B1: ( 0, 14, 10)
1550 19:26:23.226672 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1551 19:26:23.230002 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1552 19:26:23.230093
1553 19:26:23.233217 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1554 19:26:23.236666 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1555 19:26:23.240403 [Gating] SW calibration Done
1556 19:26:23.240492 ==
1557 19:26:23.243578 Dram Type= 6, Freq= 0, CH_1, rank 0
1558 19:26:23.246845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1559 19:26:23.246927 ==
1560 19:26:23.250198 RX Vref Scan: 0
1561 19:26:23.250279
1562 19:26:23.253418 RX Vref 0 -> 0, step: 1
1563 19:26:23.253500
1564 19:26:23.253575 RX Delay -130 -> 252, step: 16
1565 19:26:23.260267 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1566 19:26:23.263833 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1567 19:26:23.266737 iDelay=222, Bit 2, Center 61 (-66 ~ 189) 256
1568 19:26:23.270338 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1569 19:26:23.273312 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1570 19:26:23.280207 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1571 19:26:23.283037 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1572 19:26:23.286574 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1573 19:26:23.290290 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1574 19:26:23.293279 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1575 19:26:23.300130 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1576 19:26:23.303086 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1577 19:26:23.306574 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1578 19:26:23.310079 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1579 19:26:23.312965 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1580 19:26:23.319661 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1581 19:26:23.319765 ==
1582 19:26:23.323115 Dram Type= 6, Freq= 0, CH_1, rank 0
1583 19:26:23.326706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1584 19:26:23.326791 ==
1585 19:26:23.326855 DQS Delay:
1586 19:26:23.329651 DQS0 = 0, DQS1 = 0
1587 19:26:23.329733 DQM Delay:
1588 19:26:23.332974 DQM0 = 80, DQM1 = 70
1589 19:26:23.333055 DQ Delay:
1590 19:26:23.336745 DQ0 =85, DQ1 =77, DQ2 =61, DQ3 =77
1591 19:26:23.339673 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1592 19:26:23.343085 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
1593 19:26:23.346319 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1594 19:26:23.346400
1595 19:26:23.346464
1596 19:26:23.346523 ==
1597 19:26:23.350267 Dram Type= 6, Freq= 0, CH_1, rank 0
1598 19:26:23.353344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1599 19:26:23.353453 ==
1600 19:26:23.356643
1601 19:26:23.356725
1602 19:26:23.356788 TX Vref Scan disable
1603 19:26:23.360092 == TX Byte 0 ==
1604 19:26:23.363034 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1605 19:26:23.366314 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1606 19:26:23.369856 == TX Byte 1 ==
1607 19:26:23.373102 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1608 19:26:23.376180 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1609 19:26:23.376264 ==
1610 19:26:23.379681 Dram Type= 6, Freq= 0, CH_1, rank 0
1611 19:26:23.385959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1612 19:26:23.386046 ==
1613 19:26:23.398437 TX Vref=22, minBit 0, minWin=27, winSum=438
1614 19:26:23.401422 TX Vref=24, minBit 1, minWin=26, winSum=440
1615 19:26:23.404976 TX Vref=26, minBit 5, minWin=27, winSum=445
1616 19:26:23.408378 TX Vref=28, minBit 4, minWin=27, winSum=444
1617 19:26:23.411846 TX Vref=30, minBit 5, minWin=27, winSum=448
1618 19:26:23.415308 TX Vref=32, minBit 0, minWin=27, winSum=444
1619 19:26:23.421750 [TxChooseVref] Worse bit 5, Min win 27, Win sum 448, Final Vref 30
1620 19:26:23.421834
1621 19:26:23.425338 Final TX Range 1 Vref 30
1622 19:26:23.425421
1623 19:26:23.425484 ==
1624 19:26:23.428072 Dram Type= 6, Freq= 0, CH_1, rank 0
1625 19:26:23.431590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1626 19:26:23.431673 ==
1627 19:26:23.431744
1628 19:26:23.431833
1629 19:26:23.434988 TX Vref Scan disable
1630 19:26:23.438550 == TX Byte 0 ==
1631 19:26:23.441755 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1632 19:26:23.444704 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1633 19:26:23.448150 == TX Byte 1 ==
1634 19:26:23.451588 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1635 19:26:23.455549 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1636 19:26:23.455652
1637 19:26:23.458899 [DATLAT]
1638 19:26:23.458982 Freq=800, CH1 RK0
1639 19:26:23.459046
1640 19:26:23.462328 DATLAT Default: 0xa
1641 19:26:23.462410 0, 0xFFFF, sum = 0
1642 19:26:23.465805 1, 0xFFFF, sum = 0
1643 19:26:23.465889 2, 0xFFFF, sum = 0
1644 19:26:23.469357 3, 0xFFFF, sum = 0
1645 19:26:23.469466 4, 0xFFFF, sum = 0
1646 19:26:23.472226 5, 0xFFFF, sum = 0
1647 19:26:23.472313 6, 0xFFFF, sum = 0
1648 19:26:23.475489 7, 0xFFFF, sum = 0
1649 19:26:23.475575 8, 0xFFFF, sum = 0
1650 19:26:23.479112 9, 0x0, sum = 1
1651 19:26:23.479198 10, 0x0, sum = 2
1652 19:26:23.482419 11, 0x0, sum = 3
1653 19:26:23.482505 12, 0x0, sum = 4
1654 19:26:23.482593 best_step = 10
1655 19:26:23.485656
1656 19:26:23.485741 ==
1657 19:26:23.489164 Dram Type= 6, Freq= 0, CH_1, rank 0
1658 19:26:23.492537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1659 19:26:23.492635 ==
1660 19:26:23.492722 RX Vref Scan: 1
1661 19:26:23.492821
1662 19:26:23.495660 Set Vref Range= 32 -> 127
1663 19:26:23.495763
1664 19:26:23.499040 RX Vref 32 -> 127, step: 1
1665 19:26:23.499129
1666 19:26:23.502673 RX Delay -111 -> 252, step: 8
1667 19:26:23.502765
1668 19:26:23.505477 Set Vref, RX VrefLevel [Byte0]: 32
1669 19:26:23.508854 [Byte1]: 32
1670 19:26:23.508946
1671 19:26:23.512355 Set Vref, RX VrefLevel [Byte0]: 33
1672 19:26:23.515835 [Byte1]: 33
1673 19:26:23.515925
1674 19:26:23.519488 Set Vref, RX VrefLevel [Byte0]: 34
1675 19:26:23.522380 [Byte1]: 34
1676 19:26:23.525954
1677 19:26:23.526037 Set Vref, RX VrefLevel [Byte0]: 35
1678 19:26:23.529731 [Byte1]: 35
1679 19:26:23.533964
1680 19:26:23.534049 Set Vref, RX VrefLevel [Byte0]: 36
1681 19:26:23.537277 [Byte1]: 36
1682 19:26:23.541227
1683 19:26:23.541310 Set Vref, RX VrefLevel [Byte0]: 37
1684 19:26:23.544588 [Byte1]: 37
1685 19:26:23.549294
1686 19:26:23.549378 Set Vref, RX VrefLevel [Byte0]: 38
1687 19:26:23.552737 [Byte1]: 38
1688 19:26:23.556694
1689 19:26:23.556777 Set Vref, RX VrefLevel [Byte0]: 39
1690 19:26:23.560106 [Byte1]: 39
1691 19:26:23.564667
1692 19:26:23.564751 Set Vref, RX VrefLevel [Byte0]: 40
1693 19:26:23.567981 [Byte1]: 40
1694 19:26:23.572013
1695 19:26:23.572101 Set Vref, RX VrefLevel [Byte0]: 41
1696 19:26:23.575691 [Byte1]: 41
1697 19:26:23.579638
1698 19:26:23.579721 Set Vref, RX VrefLevel [Byte0]: 42
1699 19:26:23.583149 [Byte1]: 42
1700 19:26:23.587282
1701 19:26:23.587366 Set Vref, RX VrefLevel [Byte0]: 43
1702 19:26:23.590763 [Byte1]: 43
1703 19:26:23.595031
1704 19:26:23.595116 Set Vref, RX VrefLevel [Byte0]: 44
1705 19:26:23.598535 [Byte1]: 44
1706 19:26:23.602539
1707 19:26:23.602621 Set Vref, RX VrefLevel [Byte0]: 45
1708 19:26:23.606188 [Byte1]: 45
1709 19:26:23.610124
1710 19:26:23.610215 Set Vref, RX VrefLevel [Byte0]: 46
1711 19:26:23.613775 [Byte1]: 46
1712 19:26:23.617954
1713 19:26:23.618037 Set Vref, RX VrefLevel [Byte0]: 47
1714 19:26:23.621216 [Byte1]: 47
1715 19:26:23.625559
1716 19:26:23.625645 Set Vref, RX VrefLevel [Byte0]: 48
1717 19:26:23.628813 [Byte1]: 48
1718 19:26:23.633497
1719 19:26:23.633617 Set Vref, RX VrefLevel [Byte0]: 49
1720 19:26:23.636443 [Byte1]: 49
1721 19:26:23.640824
1722 19:26:23.640907 Set Vref, RX VrefLevel [Byte0]: 50
1723 19:26:23.644043 [Byte1]: 50
1724 19:26:23.648390
1725 19:26:23.648474 Set Vref, RX VrefLevel [Byte0]: 51
1726 19:26:23.652030 [Byte1]: 51
1727 19:26:23.656091
1728 19:26:23.656174 Set Vref, RX VrefLevel [Byte0]: 52
1729 19:26:23.659541 [Byte1]: 52
1730 19:26:23.663620
1731 19:26:23.663702 Set Vref, RX VrefLevel [Byte0]: 53
1732 19:26:23.667245 [Byte1]: 53
1733 19:26:23.671703
1734 19:26:23.671787 Set Vref, RX VrefLevel [Byte0]: 54
1735 19:26:23.674558 [Byte1]: 54
1736 19:26:23.679221
1737 19:26:23.679314 Set Vref, RX VrefLevel [Byte0]: 55
1738 19:26:23.682728 [Byte1]: 55
1739 19:26:23.686838
1740 19:26:23.686926 Set Vref, RX VrefLevel [Byte0]: 56
1741 19:26:23.690446 [Byte1]: 56
1742 19:26:23.694590
1743 19:26:23.694674 Set Vref, RX VrefLevel [Byte0]: 57
1744 19:26:23.697611 [Byte1]: 57
1745 19:26:23.702043
1746 19:26:23.702126 Set Vref, RX VrefLevel [Byte0]: 58
1747 19:26:23.705492 [Byte1]: 58
1748 19:26:23.709956
1749 19:26:23.710039 Set Vref, RX VrefLevel [Byte0]: 59
1750 19:26:23.712764 [Byte1]: 59
1751 19:26:23.717663
1752 19:26:23.717747 Set Vref, RX VrefLevel [Byte0]: 60
1753 19:26:23.720831 [Byte1]: 60
1754 19:26:23.724829
1755 19:26:23.724914 Set Vref, RX VrefLevel [Byte0]: 61
1756 19:26:23.728624 [Byte1]: 61
1757 19:26:23.732684
1758 19:26:23.732767 Set Vref, RX VrefLevel [Byte0]: 62
1759 19:26:23.736065 [Byte1]: 62
1760 19:26:23.740436
1761 19:26:23.740519 Set Vref, RX VrefLevel [Byte0]: 63
1762 19:26:23.743813 [Byte1]: 63
1763 19:26:23.748105
1764 19:26:23.748190 Set Vref, RX VrefLevel [Byte0]: 64
1765 19:26:23.751035 [Byte1]: 64
1766 19:26:23.755631
1767 19:26:23.755712 Set Vref, RX VrefLevel [Byte0]: 65
1768 19:26:23.759051 [Byte1]: 65
1769 19:26:23.763115
1770 19:26:23.763197 Set Vref, RX VrefLevel [Byte0]: 66
1771 19:26:23.766792 [Byte1]: 66
1772 19:26:23.770661
1773 19:26:23.770745 Set Vref, RX VrefLevel [Byte0]: 67
1774 19:26:23.774531 [Byte1]: 67
1775 19:26:23.778753
1776 19:26:23.778836 Set Vref, RX VrefLevel [Byte0]: 68
1777 19:26:23.781550 [Byte1]: 68
1778 19:26:23.786237
1779 19:26:23.786319 Set Vref, RX VrefLevel [Byte0]: 69
1780 19:26:23.789694 [Byte1]: 69
1781 19:26:23.793680
1782 19:26:23.793767 Set Vref, RX VrefLevel [Byte0]: 70
1783 19:26:23.797157 [Byte1]: 70
1784 19:26:23.801211
1785 19:26:23.801305 Set Vref, RX VrefLevel [Byte0]: 71
1786 19:26:23.804630 [Byte1]: 71
1787 19:26:23.809367
1788 19:26:23.809478 Set Vref, RX VrefLevel [Byte0]: 72
1789 19:26:23.812727 [Byte1]: 72
1790 19:26:23.816688
1791 19:26:23.816778 Set Vref, RX VrefLevel [Byte0]: 73
1792 19:26:23.820079 [Byte1]: 73
1793 19:26:23.824270
1794 19:26:23.824364 Set Vref, RX VrefLevel [Byte0]: 74
1795 19:26:23.827894 [Byte1]: 74
1796 19:26:23.831960
1797 19:26:23.832059 Final RX Vref Byte 0 = 55 to rank0
1798 19:26:23.835600 Final RX Vref Byte 1 = 52 to rank0
1799 19:26:23.838903 Final RX Vref Byte 0 = 55 to rank1
1800 19:26:23.842341 Final RX Vref Byte 1 = 52 to rank1==
1801 19:26:23.845134 Dram Type= 6, Freq= 0, CH_1, rank 0
1802 19:26:23.851972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1803 19:26:23.852063 ==
1804 19:26:23.852150 DQS Delay:
1805 19:26:23.852231 DQS0 = 0, DQS1 = 0
1806 19:26:23.855720 DQM Delay:
1807 19:26:23.855809 DQM0 = 81, DQM1 = 72
1808 19:26:23.858445 DQ Delay:
1809 19:26:23.861703 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =76
1810 19:26:23.865293 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
1811 19:26:23.865389 DQ8 =60, DQ9 =64, DQ10 =72, DQ11 =68
1812 19:26:23.872046 DQ12 =80, DQ13 =80, DQ14 =76, DQ15 =80
1813 19:26:23.872178
1814 19:26:23.872271
1815 19:26:23.878834 [DQSOSCAuto] RK0, (LSB)MR18= 0x111c, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 405 ps
1816 19:26:23.882022 CH1 RK0: MR19=606, MR18=111C
1817 19:26:23.889021 CH1_RK0: MR19=0x606, MR18=0x111C, DQSOSC=402, MR23=63, INC=91, DEC=60
1818 19:26:23.889150
1819 19:26:23.892049 ----->DramcWriteLeveling(PI) begin...
1820 19:26:23.892141 ==
1821 19:26:23.895563 Dram Type= 6, Freq= 0, CH_1, rank 1
1822 19:26:23.899022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1823 19:26:23.899114 ==
1824 19:26:23.902427 Write leveling (Byte 0): 28 => 28
1825 19:26:23.905379 Write leveling (Byte 1): 29 => 29
1826 19:26:23.908807 DramcWriteLeveling(PI) end<-----
1827 19:26:23.908898
1828 19:26:23.908984 ==
1829 19:26:23.912151 Dram Type= 6, Freq= 0, CH_1, rank 1
1830 19:26:23.915531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1831 19:26:23.915628 ==
1832 19:26:23.918769 [Gating] SW mode calibration
1833 19:26:23.925806 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1834 19:26:23.931963 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1835 19:26:23.935849 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1836 19:26:23.939116 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1837 19:26:23.945915 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 19:26:23.948663 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 19:26:23.951955 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 19:26:23.958846 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 19:26:23.962329 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 19:26:23.965487 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 19:26:23.969082 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 19:26:23.975528 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 19:26:23.978910 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 19:26:23.981845 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 19:26:23.988516 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 19:26:23.991804 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 19:26:23.995158 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 19:26:24.001984 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 19:26:24.005439 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 19:26:24.008983 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1853 19:26:24.015268 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 19:26:24.018821 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 19:26:24.021732 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 19:26:24.028606 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 19:26:24.032176 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 19:26:24.035062 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 19:26:24.041808 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 19:26:24.045137 0 9 4 | B1->B0 | 2323 2828 | 0 1 | (0 0) (1 1)
1861 19:26:24.048704 0 9 8 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
1862 19:26:24.055312 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1863 19:26:24.058598 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1864 19:26:24.062034 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1865 19:26:24.068599 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1866 19:26:24.072029 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1867 19:26:24.075552 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1868 19:26:24.082118 0 10 4 | B1->B0 | 3131 2d2d | 1 1 | (1 1) (1 0)
1869 19:26:24.085478 0 10 8 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
1870 19:26:24.088813 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 19:26:24.092357 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 19:26:24.098827 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 19:26:24.102288 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 19:26:24.105177 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 19:26:24.112044 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 19:26:24.115532 0 11 4 | B1->B0 | 2929 3737 | 0 0 | (0 0) (0 0)
1877 19:26:24.118836 0 11 8 | B1->B0 | 3c3c 4646 | 1 0 | (0 0) (0 0)
1878 19:26:24.125689 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1879 19:26:24.129015 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1880 19:26:24.131956 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1881 19:26:24.138397 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1882 19:26:24.141948 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1883 19:26:24.145398 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1884 19:26:24.152255 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1885 19:26:24.155477 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1886 19:26:24.158685 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1887 19:26:24.165070 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1888 19:26:24.168546 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1889 19:26:24.172146 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1890 19:26:24.178489 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1891 19:26:24.182075 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1892 19:26:24.185445 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1893 19:26:24.188929 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1894 19:26:24.195018 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1895 19:26:24.198774 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1896 19:26:24.202166 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1897 19:26:24.208280 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1898 19:26:24.211716 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1899 19:26:24.215059 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1900 19:26:24.221773 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1901 19:26:24.225160 Total UI for P1: 0, mck2ui 16
1902 19:26:24.228401 best dqsien dly found for B0: ( 0, 14, 2)
1903 19:26:24.231761 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1904 19:26:24.235112 Total UI for P1: 0, mck2ui 16
1905 19:26:24.238619 best dqsien dly found for B1: ( 0, 14, 4)
1906 19:26:24.241551 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1907 19:26:24.245058 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1908 19:26:24.245157
1909 19:26:24.248497 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1910 19:26:24.251984 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1911 19:26:24.254862 [Gating] SW calibration Done
1912 19:26:24.254961 ==
1913 19:26:24.258281 Dram Type= 6, Freq= 0, CH_1, rank 1
1914 19:26:24.261576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1915 19:26:24.265105 ==
1916 19:26:24.265206 RX Vref Scan: 0
1917 19:26:24.265274
1918 19:26:24.268237 RX Vref 0 -> 0, step: 1
1919 19:26:24.268327
1920 19:26:24.271638 RX Delay -130 -> 252, step: 16
1921 19:26:24.275161 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1922 19:26:24.278506 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1923 19:26:24.281903 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1924 19:26:24.284723 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1925 19:26:24.291825 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1926 19:26:24.295256 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1927 19:26:24.298134 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1928 19:26:24.301550 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1929 19:26:24.305129 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1930 19:26:24.308676 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1931 19:26:24.315091 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1932 19:26:24.318367 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1933 19:26:24.321697 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1934 19:26:24.325031 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1935 19:26:24.331921 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1936 19:26:24.335122 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1937 19:26:24.335247 ==
1938 19:26:24.338312 Dram Type= 6, Freq= 0, CH_1, rank 1
1939 19:26:24.341657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1940 19:26:24.341775 ==
1941 19:26:24.341851 DQS Delay:
1942 19:26:24.344976 DQS0 = 0, DQS1 = 0
1943 19:26:24.345067 DQM Delay:
1944 19:26:24.348566 DQM0 = 79, DQM1 = 73
1945 19:26:24.348657 DQ Delay:
1946 19:26:24.352023 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =77
1947 19:26:24.354944 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =77
1948 19:26:24.358310 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =69
1949 19:26:24.361849 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =85
1950 19:26:24.361948
1951 19:26:24.362015
1952 19:26:24.362075 ==
1953 19:26:24.365291 Dram Type= 6, Freq= 0, CH_1, rank 1
1954 19:26:24.368584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1955 19:26:24.371797 ==
1956 19:26:24.371904
1957 19:26:24.371971
1958 19:26:24.372033 TX Vref Scan disable
1959 19:26:24.375029 == TX Byte 0 ==
1960 19:26:24.378196 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1961 19:26:24.381569 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1962 19:26:24.385010 == TX Byte 1 ==
1963 19:26:24.388513 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1964 19:26:24.392024 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1965 19:26:24.392124 ==
1966 19:26:24.394959 Dram Type= 6, Freq= 0, CH_1, rank 1
1967 19:26:24.401734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1968 19:26:24.401853 ==
1969 19:26:24.414066 TX Vref=22, minBit 6, minWin=27, winSum=450
1970 19:26:24.416961 TX Vref=24, minBit 1, minWin=28, winSum=454
1971 19:26:24.420567 TX Vref=26, minBit 1, minWin=28, winSum=456
1972 19:26:24.423971 TX Vref=28, minBit 0, minWin=28, winSum=458
1973 19:26:24.426867 TX Vref=30, minBit 5, minWin=27, winSum=458
1974 19:26:24.430533 TX Vref=32, minBit 5, minWin=27, winSum=459
1975 19:26:24.437326 [TxChooseVref] Worse bit 0, Min win 28, Win sum 458, Final Vref 28
1976 19:26:24.437453
1977 19:26:24.440575 Final TX Range 1 Vref 28
1978 19:26:24.440663
1979 19:26:24.440727 ==
1980 19:26:24.443533 Dram Type= 6, Freq= 0, CH_1, rank 1
1981 19:26:24.446857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1982 19:26:24.446953 ==
1983 19:26:24.447020
1984 19:26:24.450392
1985 19:26:24.450479 TX Vref Scan disable
1986 19:26:24.453692 == TX Byte 0 ==
1987 19:26:24.457133 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1988 19:26:24.460199 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1989 19:26:24.463756 == TX Byte 1 ==
1990 19:26:24.467105 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1991 19:26:24.470520 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1992 19:26:24.473472
1993 19:26:24.473635 [DATLAT]
1994 19:26:24.473709 Freq=800, CH1 RK1
1995 19:26:24.473771
1996 19:26:24.476791 DATLAT Default: 0xa
1997 19:26:24.476904 0, 0xFFFF, sum = 0
1998 19:26:24.480054 1, 0xFFFF, sum = 0
1999 19:26:24.480171 2, 0xFFFF, sum = 0
2000 19:26:24.483833 3, 0xFFFF, sum = 0
2001 19:26:24.483923 4, 0xFFFF, sum = 0
2002 19:26:24.486893 5, 0xFFFF, sum = 0
2003 19:26:24.490223 6, 0xFFFF, sum = 0
2004 19:26:24.490318 7, 0xFFFF, sum = 0
2005 19:26:24.490385 8, 0x0, sum = 1
2006 19:26:24.493445 9, 0x0, sum = 2
2007 19:26:24.493593 10, 0x0, sum = 3
2008 19:26:24.497134 11, 0x0, sum = 4
2009 19:26:24.497225 best_step = 9
2010 19:26:24.497291
2011 19:26:24.497351 ==
2012 19:26:24.500004 Dram Type= 6, Freq= 0, CH_1, rank 1
2013 19:26:24.507235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2014 19:26:24.507378 ==
2015 19:26:24.507446 RX Vref Scan: 0
2016 19:26:24.507506
2017 19:26:24.510078 RX Vref 0 -> 0, step: 1
2018 19:26:24.510168
2019 19:26:24.513654 RX Delay -111 -> 252, step: 8
2020 19:26:24.516664 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
2021 19:26:24.520119 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2022 19:26:24.526576 iDelay=209, Bit 2, Center 64 (-55 ~ 184) 240
2023 19:26:24.530203 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2024 19:26:24.533718 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2025 19:26:24.536552 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2026 19:26:24.539962 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2027 19:26:24.546981 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2028 19:26:24.550013 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2029 19:26:24.553479 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2030 19:26:24.556903 iDelay=209, Bit 10, Center 80 (-39 ~ 200) 240
2031 19:26:24.560283 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2032 19:26:24.566764 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2033 19:26:24.569964 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2034 19:26:24.573741 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2035 19:26:24.576577 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2036 19:26:24.576683 ==
2037 19:26:24.580034 Dram Type= 6, Freq= 0, CH_1, rank 1
2038 19:26:24.583512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2039 19:26:24.586690 ==
2040 19:26:24.586790 DQS Delay:
2041 19:26:24.586858 DQS0 = 0, DQS1 = 0
2042 19:26:24.590441 DQM Delay:
2043 19:26:24.590539 DQM0 = 77, DQM1 = 74
2044 19:26:24.593821 DQ Delay:
2045 19:26:24.593915 DQ0 =80, DQ1 =72, DQ2 =64, DQ3 =72
2046 19:26:24.597009 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2047 19:26:24.600121 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =68
2048 19:26:24.603642 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
2049 19:26:24.603750
2050 19:26:24.603818
2051 19:26:24.613711 [DQSOSCAuto] RK1, (LSB)MR18= 0x273f, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
2052 19:26:24.616938 CH1 RK1: MR19=606, MR18=273F
2053 19:26:24.623419 CH1_RK1: MR19=0x606, MR18=0x273F, DQSOSC=393, MR23=63, INC=95, DEC=63
2054 19:26:24.626912 [RxdqsGatingPostProcess] freq 800
2055 19:26:24.630523 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2056 19:26:24.633434 Pre-setting of DQS Precalculation
2057 19:26:24.636930 [DualRankRxdatlatCal] RK0: 10, RK1: 9, Final_Datlat 10
2058 19:26:24.646666 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2059 19:26:24.653578 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2060 19:26:24.653719
2061 19:26:24.653789
2062 19:26:24.656607 [Calibration Summary] 1600 Mbps
2063 19:26:24.656696 CH 0, Rank 0
2064 19:26:24.659985 SW Impedance : PASS
2065 19:26:24.660077 DUTY Scan : NO K
2066 19:26:24.663576 ZQ Calibration : PASS
2067 19:26:24.666598 Jitter Meter : NO K
2068 19:26:24.666692 CBT Training : PASS
2069 19:26:24.669869 Write leveling : PASS
2070 19:26:24.673869 RX DQS gating : PASS
2071 19:26:24.673979 RX DQ/DQS(RDDQC) : PASS
2072 19:26:24.676658 TX DQ/DQS : PASS
2073 19:26:24.680226 RX DATLAT : PASS
2074 19:26:24.680322 RX DQ/DQS(Engine): PASS
2075 19:26:24.683513 TX OE : NO K
2076 19:26:24.683598 All Pass.
2077 19:26:24.683663
2078 19:26:24.686601 CH 0, Rank 1
2079 19:26:24.686684 SW Impedance : PASS
2080 19:26:24.690440 DUTY Scan : NO K
2081 19:26:24.693282 ZQ Calibration : PASS
2082 19:26:24.693373 Jitter Meter : NO K
2083 19:26:24.696734 CBT Training : PASS
2084 19:26:24.700133 Write leveling : PASS
2085 19:26:24.700219 RX DQS gating : PASS
2086 19:26:24.703206 RX DQ/DQS(RDDQC) : PASS
2087 19:26:24.703289 TX DQ/DQS : PASS
2088 19:26:24.707076 RX DATLAT : PASS
2089 19:26:24.710208 RX DQ/DQS(Engine): PASS
2090 19:26:24.710292 TX OE : NO K
2091 19:26:24.713398 All Pass.
2092 19:26:24.713482
2093 19:26:24.713585 CH 1, Rank 0
2094 19:26:24.716933 SW Impedance : PASS
2095 19:26:24.717018 DUTY Scan : NO K
2096 19:26:24.720100 ZQ Calibration : PASS
2097 19:26:24.723653 Jitter Meter : NO K
2098 19:26:24.723738 CBT Training : PASS
2099 19:26:24.726687 Write leveling : PASS
2100 19:26:24.730253 RX DQS gating : PASS
2101 19:26:24.730344 RX DQ/DQS(RDDQC) : PASS
2102 19:26:24.733517 TX DQ/DQS : PASS
2103 19:26:24.737071 RX DATLAT : PASS
2104 19:26:24.737173 RX DQ/DQS(Engine): PASS
2105 19:26:24.740429 TX OE : NO K
2106 19:26:24.740523 All Pass.
2107 19:26:24.740589
2108 19:26:24.743409 CH 1, Rank 1
2109 19:26:24.743495 SW Impedance : PASS
2110 19:26:24.746773 DUTY Scan : NO K
2111 19:26:24.746861 ZQ Calibration : PASS
2112 19:26:24.750140 Jitter Meter : NO K
2113 19:26:24.753713 CBT Training : PASS
2114 19:26:24.753810 Write leveling : PASS
2115 19:26:24.756646 RX DQS gating : PASS
2116 19:26:24.760005 RX DQ/DQS(RDDQC) : PASS
2117 19:26:24.760098 TX DQ/DQS : PASS
2118 19:26:24.763546 RX DATLAT : PASS
2119 19:26:24.767090 RX DQ/DQS(Engine): PASS
2120 19:26:24.767186 TX OE : NO K
2121 19:26:24.770550 All Pass.
2122 19:26:24.770665
2123 19:26:24.770757 DramC Write-DBI off
2124 19:26:24.773299 PER_BANK_REFRESH: Hybrid Mode
2125 19:26:24.773389 TX_TRACKING: ON
2126 19:26:24.776572 [GetDramInforAfterCalByMRR] Vendor 6.
2127 19:26:24.783543 [GetDramInforAfterCalByMRR] Revision 606.
2128 19:26:24.787214 [GetDramInforAfterCalByMRR] Revision 2 0.
2129 19:26:24.787315 MR0 0x3b3b
2130 19:26:24.787380 MR8 0x5151
2131 19:26:24.790200 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2132 19:26:24.790286
2133 19:26:24.793657 MR0 0x3b3b
2134 19:26:24.793742 MR8 0x5151
2135 19:26:24.797038 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2136 19:26:24.797122
2137 19:26:24.807023 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2138 19:26:24.810433 [FAST_K] Save calibration result to emmc
2139 19:26:24.813500 [FAST_K] Save calibration result to emmc
2140 19:26:24.817060 dram_init: config_dvfs: 1
2141 19:26:24.820362 dramc_set_vcore_voltage set vcore to 662500
2142 19:26:24.823838 Read voltage for 1200, 2
2143 19:26:24.823952 Vio18 = 0
2144 19:26:24.824018 Vcore = 662500
2145 19:26:24.824079 Vdram = 0
2146 19:26:24.826762 Vddq = 0
2147 19:26:24.826850 Vmddr = 0
2148 19:26:24.833790 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2149 19:26:24.837183 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2150 19:26:24.840243 MEM_TYPE=3, freq_sel=15
2151 19:26:24.843493 sv_algorithm_assistance_LP4_1600
2152 19:26:24.847069 ============ PULL DRAM RESETB DOWN ============
2153 19:26:24.850533 ========== PULL DRAM RESETB DOWN end =========
2154 19:26:24.856938 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2155 19:26:24.860136 ===================================
2156 19:26:24.860224 LPDDR4 DRAM CONFIGURATION
2157 19:26:24.863664 ===================================
2158 19:26:24.866712 EX_ROW_EN[0] = 0x0
2159 19:26:24.866798 EX_ROW_EN[1] = 0x0
2160 19:26:24.870175 LP4Y_EN = 0x0
2161 19:26:24.873751 WORK_FSP = 0x0
2162 19:26:24.873838 WL = 0x4
2163 19:26:24.877058 RL = 0x4
2164 19:26:24.877141 BL = 0x2
2165 19:26:24.880006 RPST = 0x0
2166 19:26:24.880089 RD_PRE = 0x0
2167 19:26:24.883488 WR_PRE = 0x1
2168 19:26:24.883576 WR_PST = 0x0
2169 19:26:24.886823 DBI_WR = 0x0
2170 19:26:24.886906 DBI_RD = 0x0
2171 19:26:24.890122 OTF = 0x1
2172 19:26:24.893727 ===================================
2173 19:26:24.896599 ===================================
2174 19:26:24.896681 ANA top config
2175 19:26:24.900530 ===================================
2176 19:26:24.903290 DLL_ASYNC_EN = 0
2177 19:26:24.906991 ALL_SLAVE_EN = 0
2178 19:26:24.907074 NEW_RANK_MODE = 1
2179 19:26:24.910365 DLL_IDLE_MODE = 1
2180 19:26:24.913700 LP45_APHY_COMB_EN = 1
2181 19:26:24.916578 TX_ODT_DIS = 1
2182 19:26:24.916665 NEW_8X_MODE = 1
2183 19:26:24.920028 ===================================
2184 19:26:24.923819 ===================================
2185 19:26:24.926576 data_rate = 2400
2186 19:26:24.930314 CKR = 1
2187 19:26:24.933265 DQ_P2S_RATIO = 8
2188 19:26:24.936789 ===================================
2189 19:26:24.940287 CA_P2S_RATIO = 8
2190 19:26:24.943314 DQ_CA_OPEN = 0
2191 19:26:24.946814 DQ_SEMI_OPEN = 0
2192 19:26:24.946902 CA_SEMI_OPEN = 0
2193 19:26:24.950294 CA_FULL_RATE = 0
2194 19:26:24.953219 DQ_CKDIV4_EN = 0
2195 19:26:24.956737 CA_CKDIV4_EN = 0
2196 19:26:24.960272 CA_PREDIV_EN = 0
2197 19:26:24.963571 PH8_DLY = 17
2198 19:26:24.963660 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2199 19:26:24.966861 DQ_AAMCK_DIV = 4
2200 19:26:24.969870 CA_AAMCK_DIV = 4
2201 19:26:24.973486 CA_ADMCK_DIV = 4
2202 19:26:24.976685 DQ_TRACK_CA_EN = 0
2203 19:26:24.980366 CA_PICK = 1200
2204 19:26:24.980457 CA_MCKIO = 1200
2205 19:26:24.983663 MCKIO_SEMI = 0
2206 19:26:24.986476 PLL_FREQ = 2366
2207 19:26:24.990196 DQ_UI_PI_RATIO = 32
2208 19:26:24.993275 CA_UI_PI_RATIO = 0
2209 19:26:24.996727 ===================================
2210 19:26:24.999844 ===================================
2211 19:26:25.003595 memory_type:LPDDR4
2212 19:26:25.003688 GP_NUM : 10
2213 19:26:25.006689 SRAM_EN : 1
2214 19:26:25.006774 MD32_EN : 0
2215 19:26:25.009907 ===================================
2216 19:26:25.013936 [ANA_INIT] >>>>>>>>>>>>>>
2217 19:26:25.016591 <<<<<< [CONFIGURE PHASE]: ANA_TX
2218 19:26:25.020041 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2219 19:26:25.023518 ===================================
2220 19:26:25.026722 data_rate = 2400,PCW = 0X5b00
2221 19:26:25.030023 ===================================
2222 19:26:25.033389 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2223 19:26:25.036924 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2224 19:26:25.043345 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2225 19:26:25.046828 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2226 19:26:25.050386 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2227 19:26:25.056874 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2228 19:26:25.056960 [ANA_INIT] flow start
2229 19:26:25.060410 [ANA_INIT] PLL >>>>>>>>
2230 19:26:25.060492 [ANA_INIT] PLL <<<<<<<<
2231 19:26:25.063460 [ANA_INIT] MIDPI >>>>>>>>
2232 19:26:25.067004 [ANA_INIT] MIDPI <<<<<<<<
2233 19:26:25.070010 [ANA_INIT] DLL >>>>>>>>
2234 19:26:25.070094 [ANA_INIT] DLL <<<<<<<<
2235 19:26:25.073491 [ANA_INIT] flow end
2236 19:26:25.077028 ============ LP4 DIFF to SE enter ============
2237 19:26:25.080035 ============ LP4 DIFF to SE exit ============
2238 19:26:25.083509 [ANA_INIT] <<<<<<<<<<<<<
2239 19:26:25.086950 [Flow] Enable top DCM control >>>>>
2240 19:26:25.090358 [Flow] Enable top DCM control <<<<<
2241 19:26:25.093630 Enable DLL master slave shuffle
2242 19:26:25.100042 ==============================================================
2243 19:26:25.100128 Gating Mode config
2244 19:26:25.106708 ==============================================================
2245 19:26:25.106793 Config description:
2246 19:26:25.116514 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2247 19:26:25.123583 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2248 19:26:25.130018 SELPH_MODE 0: By rank 1: By Phase
2249 19:26:25.133256 ==============================================================
2250 19:26:25.136975 GAT_TRACK_EN = 1
2251 19:26:25.140064 RX_GATING_MODE = 2
2252 19:26:25.143591 RX_GATING_TRACK_MODE = 2
2253 19:26:25.146830 SELPH_MODE = 1
2254 19:26:25.150035 PICG_EARLY_EN = 1
2255 19:26:25.153476 VALID_LAT_VALUE = 1
2256 19:26:25.156530 ==============================================================
2257 19:26:25.159936 Enter into Gating configuration >>>>
2258 19:26:25.163480 Exit from Gating configuration <<<<
2259 19:26:25.166811 Enter into DVFS_PRE_config >>>>>
2260 19:26:25.179796 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2261 19:26:25.183420 Exit from DVFS_PRE_config <<<<<
2262 19:26:25.186340 Enter into PICG configuration >>>>
2263 19:26:25.186423 Exit from PICG configuration <<<<
2264 19:26:25.189767 [RX_INPUT] configuration >>>>>
2265 19:26:25.193267 [RX_INPUT] configuration <<<<<
2266 19:26:25.199908 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2267 19:26:25.203296 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2268 19:26:25.209728 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2269 19:26:25.217068 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2270 19:26:25.223379 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2271 19:26:25.229759 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2272 19:26:25.233063 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2273 19:26:25.236289 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2274 19:26:25.239696 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2275 19:26:25.246749 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2276 19:26:25.249826 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2277 19:26:25.253365 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2278 19:26:25.256605 ===================================
2279 19:26:25.260367 LPDDR4 DRAM CONFIGURATION
2280 19:26:25.263362 ===================================
2281 19:26:25.266618 EX_ROW_EN[0] = 0x0
2282 19:26:25.266711 EX_ROW_EN[1] = 0x0
2283 19:26:25.269982 LP4Y_EN = 0x0
2284 19:26:25.270074 WORK_FSP = 0x0
2285 19:26:25.273156 WL = 0x4
2286 19:26:25.273317 RL = 0x4
2287 19:26:25.276652 BL = 0x2
2288 19:26:25.276752 RPST = 0x0
2289 19:26:25.280177 RD_PRE = 0x0
2290 19:26:25.280268 WR_PRE = 0x1
2291 19:26:25.283222 WR_PST = 0x0
2292 19:26:25.283313 DBI_WR = 0x0
2293 19:26:25.286701 DBI_RD = 0x0
2294 19:26:25.286792 OTF = 0x1
2295 19:26:25.290235 ===================================
2296 19:26:25.293090 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2297 19:26:25.300299 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2298 19:26:25.303177 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2299 19:26:25.306895 ===================================
2300 19:26:25.309726 LPDDR4 DRAM CONFIGURATION
2301 19:26:25.313154 ===================================
2302 19:26:25.313256 EX_ROW_EN[0] = 0x10
2303 19:26:25.316746 EX_ROW_EN[1] = 0x0
2304 19:26:25.316839 LP4Y_EN = 0x0
2305 19:26:25.319863 WORK_FSP = 0x0
2306 19:26:25.323229 WL = 0x4
2307 19:26:25.323329 RL = 0x4
2308 19:26:25.326715 BL = 0x2
2309 19:26:25.326809 RPST = 0x0
2310 19:26:25.330083 RD_PRE = 0x0
2311 19:26:25.330187 WR_PRE = 0x1
2312 19:26:25.332951 WR_PST = 0x0
2313 19:26:25.333039 DBI_WR = 0x0
2314 19:26:25.336772 DBI_RD = 0x0
2315 19:26:25.336866 OTF = 0x1
2316 19:26:25.339876 ===================================
2317 19:26:25.346540 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2318 19:26:25.346671 ==
2319 19:26:25.349783 Dram Type= 6, Freq= 0, CH_0, rank 0
2320 19:26:25.353284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2321 19:26:25.353386 ==
2322 19:26:25.356712 [Duty_Offset_Calibration]
2323 19:26:25.359759 B0:2 B1:0 CA:3
2324 19:26:25.359856
2325 19:26:25.363094 [DutyScan_Calibration_Flow] k_type=0
2326 19:26:25.371107
2327 19:26:25.371246 ==CLK 0==
2328 19:26:25.374566 Final CLK duty delay cell = 0
2329 19:26:25.377936 [0] MAX Duty = 5031%(X100), DQS PI = 12
2330 19:26:25.381045 [0] MIN Duty = 4906%(X100), DQS PI = 54
2331 19:26:25.381158 [0] AVG Duty = 4968%(X100)
2332 19:26:25.384447
2333 19:26:25.388020 CH0 CLK Duty spec in!! Max-Min= 125%
2334 19:26:25.390927 [DutyScan_Calibration_Flow] ====Done====
2335 19:26:25.391025
2336 19:26:25.394401 [DutyScan_Calibration_Flow] k_type=1
2337 19:26:25.409696
2338 19:26:25.409848 ==DQS 0 ==
2339 19:26:25.413029 Final DQS duty delay cell = 0
2340 19:26:25.416570 [0] MAX Duty = 5062%(X100), DQS PI = 18
2341 19:26:25.419315 [0] MIN Duty = 4907%(X100), DQS PI = 2
2342 19:26:25.419414 [0] AVG Duty = 4984%(X100)
2343 19:26:25.423105
2344 19:26:25.423234 ==DQS 1 ==
2345 19:26:25.426019 Final DQS duty delay cell = -4
2346 19:26:25.429385 [-4] MAX Duty = 4969%(X100), DQS PI = 24
2347 19:26:25.432807 [-4] MIN Duty = 4875%(X100), DQS PI = 14
2348 19:26:25.436148 [-4] AVG Duty = 4922%(X100)
2349 19:26:25.436246
2350 19:26:25.439659 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2351 19:26:25.439747
2352 19:26:25.443063 CH0 DQS 1 Duty spec in!! Max-Min= 94%
2353 19:26:25.446404 [DutyScan_Calibration_Flow] ====Done====
2354 19:26:25.446500
2355 19:26:25.449427 [DutyScan_Calibration_Flow] k_type=3
2356 19:26:25.467246
2357 19:26:25.467398 ==DQM 0 ==
2358 19:26:25.470668 Final DQM duty delay cell = 0
2359 19:26:25.473897 [0] MAX Duty = 5124%(X100), DQS PI = 28
2360 19:26:25.477392 [0] MIN Duty = 4876%(X100), DQS PI = 0
2361 19:26:25.477568 [0] AVG Duty = 5000%(X100)
2362 19:26:25.480480
2363 19:26:25.480578 ==DQM 1 ==
2364 19:26:25.483805 Final DQM duty delay cell = 4
2365 19:26:25.486954 [4] MAX Duty = 5124%(X100), DQS PI = 52
2366 19:26:25.490561 [4] MIN Duty = 5031%(X100), DQS PI = 10
2367 19:26:25.490705 [4] AVG Duty = 5077%(X100)
2368 19:26:25.494064
2369 19:26:25.497096 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2370 19:26:25.497232
2371 19:26:25.500143 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2372 19:26:25.503791 [DutyScan_Calibration_Flow] ====Done====
2373 19:26:25.503903
2374 19:26:25.507352 [DutyScan_Calibration_Flow] k_type=2
2375 19:26:25.521762
2376 19:26:25.521916 ==DQ 0 ==
2377 19:26:25.525114 Final DQ duty delay cell = -4
2378 19:26:25.528539 [-4] MAX Duty = 5000%(X100), DQS PI = 12
2379 19:26:25.531923 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2380 19:26:25.535363 [-4] AVG Duty = 4953%(X100)
2381 19:26:25.535467
2382 19:26:25.535532 ==DQ 1 ==
2383 19:26:25.538813 Final DQ duty delay cell = -4
2384 19:26:25.541717 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2385 19:26:25.545193 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2386 19:26:25.548710 [-4] AVG Duty = 4938%(X100)
2387 19:26:25.548843
2388 19:26:25.552156 CH0 DQ 0 Duty spec in!! Max-Min= 93%
2389 19:26:25.552259
2390 19:26:25.555499 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2391 19:26:25.558356 [DutyScan_Calibration_Flow] ====Done====
2392 19:26:25.558459 ==
2393 19:26:25.561852 Dram Type= 6, Freq= 0, CH_1, rank 0
2394 19:26:25.565266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2395 19:26:25.565394 ==
2396 19:26:25.568258 [Duty_Offset_Calibration]
2397 19:26:25.568365 B0:1 B1:-2 CA:0
2398 19:26:25.568432
2399 19:26:25.571920 [DutyScan_Calibration_Flow] k_type=0
2400 19:26:25.582593
2401 19:26:25.582757 ==CLK 0==
2402 19:26:25.585463 Final CLK duty delay cell = 0
2403 19:26:25.588987 [0] MAX Duty = 5031%(X100), DQS PI = 18
2404 19:26:25.592597 [0] MIN Duty = 4876%(X100), DQS PI = 2
2405 19:26:25.592694 [0] AVG Duty = 4953%(X100)
2406 19:26:25.596082
2407 19:26:25.596169 CH1 CLK Duty spec in!! Max-Min= 155%
2408 19:26:25.602579 [DutyScan_Calibration_Flow] ====Done====
2409 19:26:25.602688
2410 19:26:25.606045 [DutyScan_Calibration_Flow] k_type=1
2411 19:26:25.620825
2412 19:26:25.620981 ==DQS 0 ==
2413 19:26:25.624250 Final DQS duty delay cell = -4
2414 19:26:25.627587 [-4] MAX Duty = 5000%(X100), DQS PI = 24
2415 19:26:25.630756 [-4] MIN Duty = 4876%(X100), DQS PI = 50
2416 19:26:25.634125 [-4] AVG Duty = 4938%(X100)
2417 19:26:25.634238
2418 19:26:25.634304 ==DQS 1 ==
2419 19:26:25.637402 Final DQS duty delay cell = 0
2420 19:26:25.641299 [0] MAX Duty = 5062%(X100), DQS PI = 0
2421 19:26:25.644235 [0] MIN Duty = 4875%(X100), DQS PI = 26
2422 19:26:25.647274 [0] AVG Duty = 4968%(X100)
2423 19:26:25.647383
2424 19:26:25.650681 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2425 19:26:25.650896
2426 19:26:25.654147 CH1 DQS 1 Duty spec in!! Max-Min= 187%
2427 19:26:25.657446 [DutyScan_Calibration_Flow] ====Done====
2428 19:26:25.657592
2429 19:26:25.660972 [DutyScan_Calibration_Flow] k_type=3
2430 19:26:25.677704
2431 19:26:25.677861 ==DQM 0 ==
2432 19:26:25.680685 Final DQM duty delay cell = 0
2433 19:26:25.684557 [0] MAX Duty = 5000%(X100), DQS PI = 22
2434 19:26:25.687737 [0] MIN Duty = 4844%(X100), DQS PI = 54
2435 19:26:25.687869 [0] AVG Duty = 4922%(X100)
2436 19:26:25.690649
2437 19:26:25.690799 ==DQM 1 ==
2438 19:26:25.694080 Final DQM duty delay cell = 0
2439 19:26:25.697566 [0] MAX Duty = 5031%(X100), DQS PI = 36
2440 19:26:25.700565 [0] MIN Duty = 4907%(X100), DQS PI = 0
2441 19:26:25.700675 [0] AVG Duty = 4969%(X100)
2442 19:26:25.704208
2443 19:26:25.707635 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2444 19:26:25.707747
2445 19:26:25.710624 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2446 19:26:25.714112 [DutyScan_Calibration_Flow] ====Done====
2447 19:26:25.714240
2448 19:26:25.717088 [DutyScan_Calibration_Flow] k_type=2
2449 19:26:25.734105
2450 19:26:25.734266 ==DQ 0 ==
2451 19:26:25.737221 Final DQ duty delay cell = 0
2452 19:26:25.740584 [0] MAX Duty = 5062%(X100), DQS PI = 12
2453 19:26:25.744151 [0] MIN Duty = 4938%(X100), DQS PI = 54
2454 19:26:25.744288 [0] AVG Duty = 5000%(X100)
2455 19:26:25.744360
2456 19:26:25.747508 ==DQ 1 ==
2457 19:26:25.750696 Final DQ duty delay cell = 0
2458 19:26:25.754123 [0] MAX Duty = 5125%(X100), DQS PI = 36
2459 19:26:25.757244 [0] MIN Duty = 4938%(X100), DQS PI = 26
2460 19:26:25.757351 [0] AVG Duty = 5031%(X100)
2461 19:26:25.757416
2462 19:26:25.760572 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2463 19:26:25.763912
2464 19:26:25.767246 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2465 19:26:25.770593 [DutyScan_Calibration_Flow] ====Done====
2466 19:26:25.773715 nWR fixed to 30
2467 19:26:25.773813 [ModeRegInit_LP4] CH0 RK0
2468 19:26:25.777119 [ModeRegInit_LP4] CH0 RK1
2469 19:26:25.780611 [ModeRegInit_LP4] CH1 RK0
2470 19:26:25.783905 [ModeRegInit_LP4] CH1 RK1
2471 19:26:25.784035 match AC timing 7
2472 19:26:25.787055 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2473 19:26:25.793934 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2474 19:26:25.797036 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2475 19:26:25.800325 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2476 19:26:25.806924 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2477 19:26:25.807013 ==
2478 19:26:25.810283 Dram Type= 6, Freq= 0, CH_0, rank 0
2479 19:26:25.813863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2480 19:26:25.813945 ==
2481 19:26:25.820286 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2482 19:26:25.827253 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2483 19:26:25.834252 [CA 0] Center 40 (10~71) winsize 62
2484 19:26:25.837733 [CA 1] Center 39 (9~70) winsize 62
2485 19:26:25.841162 [CA 2] Center 36 (6~66) winsize 61
2486 19:26:25.844237 [CA 3] Center 35 (5~66) winsize 62
2487 19:26:25.847368 [CA 4] Center 34 (4~65) winsize 62
2488 19:26:25.850834 [CA 5] Center 33 (3~63) winsize 61
2489 19:26:25.850922
2490 19:26:25.854362 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2491 19:26:25.854443
2492 19:26:25.857623 [CATrainingPosCal] consider 1 rank data
2493 19:26:25.860586 u2DelayCellTimex100 = 270/100 ps
2494 19:26:25.864039 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2495 19:26:25.867542 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2496 19:26:25.874145 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2497 19:26:25.877218 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2498 19:26:25.880954 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2499 19:26:25.884419 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2500 19:26:25.884503
2501 19:26:25.887083 CA PerBit enable=1, Macro0, CA PI delay=33
2502 19:26:25.887166
2503 19:26:25.890641 [CBTSetCACLKResult] CA Dly = 33
2504 19:26:25.890723 CS Dly: 7 (0~38)
2505 19:26:25.893930 ==
2506 19:26:25.897344 Dram Type= 6, Freq= 0, CH_0, rank 1
2507 19:26:25.900551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2508 19:26:25.900634 ==
2509 19:26:25.906855 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2510 19:26:25.910500 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2511 19:26:25.920013 [CA 0] Center 40 (10~70) winsize 61
2512 19:26:25.923589 [CA 1] Center 40 (10~70) winsize 61
2513 19:26:25.926569 [CA 2] Center 35 (5~66) winsize 62
2514 19:26:25.930127 [CA 3] Center 35 (5~66) winsize 62
2515 19:26:25.933659 [CA 4] Center 34 (4~65) winsize 62
2516 19:26:25.936538 [CA 5] Center 33 (3~64) winsize 62
2517 19:26:25.936622
2518 19:26:25.940056 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2519 19:26:25.940140
2520 19:26:25.943027 [CATrainingPosCal] consider 2 rank data
2521 19:26:25.946623 u2DelayCellTimex100 = 270/100 ps
2522 19:26:25.949961 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2523 19:26:25.956365 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2524 19:26:25.960256 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2525 19:26:25.963021 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2526 19:26:25.966672 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2527 19:26:25.969638 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2528 19:26:25.969731
2529 19:26:25.973159 CA PerBit enable=1, Macro0, CA PI delay=33
2530 19:26:25.973251
2531 19:26:25.976057 [CBTSetCACLKResult] CA Dly = 33
2532 19:26:25.979655 CS Dly: 8 (0~40)
2533 19:26:25.979759
2534 19:26:25.982879 ----->DramcWriteLeveling(PI) begin...
2535 19:26:25.982972 ==
2536 19:26:25.986522 Dram Type= 6, Freq= 0, CH_0, rank 0
2537 19:26:25.989710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2538 19:26:25.989798 ==
2539 19:26:25.992724 Write leveling (Byte 0): 32 => 32
2540 19:26:25.996079 Write leveling (Byte 1): 27 => 27
2541 19:26:25.999372 DramcWriteLeveling(PI) end<-----
2542 19:26:25.999464
2543 19:26:25.999549 ==
2544 19:26:26.002936 Dram Type= 6, Freq= 0, CH_0, rank 0
2545 19:26:26.006115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2546 19:26:26.006202 ==
2547 19:26:26.009545 [Gating] SW mode calibration
2548 19:26:26.016476 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2549 19:26:26.022835 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2550 19:26:26.026330 0 15 0 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
2551 19:26:26.029477 0 15 4 | B1->B0 | 2a2a 3333 | 0 0 | (0 0) (0 0)
2552 19:26:26.036221 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2553 19:26:26.039863 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2554 19:26:26.042630 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2555 19:26:26.049546 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2556 19:26:26.052603 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2557 19:26:26.056026 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2558 19:26:26.062548 1 0 0 | B1->B0 | 3232 2c2c | 0 1 | (0 0) (1 0)
2559 19:26:26.066255 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2560 19:26:26.069473 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2561 19:26:26.076095 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2562 19:26:26.079589 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2563 19:26:26.082543 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2564 19:26:26.089466 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2565 19:26:26.092572 1 0 28 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
2566 19:26:26.096301 1 1 0 | B1->B0 | 2626 3535 | 1 0 | (0 0) (0 0)
2567 19:26:26.099615 1 1 4 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
2568 19:26:26.106051 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2569 19:26:26.109427 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2570 19:26:26.112575 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2571 19:26:26.119653 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2572 19:26:26.123524 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2573 19:26:26.126332 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2574 19:26:26.133208 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2575 19:26:26.136581 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2576 19:26:26.139853 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2577 19:26:26.146473 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2578 19:26:26.149789 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2579 19:26:26.153054 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2580 19:26:26.159998 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2581 19:26:26.162849 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2582 19:26:26.166149 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2583 19:26:26.172942 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2584 19:26:26.176572 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2585 19:26:26.179747 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2586 19:26:26.186301 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2587 19:26:26.189693 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2588 19:26:26.192648 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2589 19:26:26.196243 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2590 19:26:26.202862 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2591 19:26:26.206316 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2592 19:26:26.209457 Total UI for P1: 0, mck2ui 16
2593 19:26:26.213052 best dqsien dly found for B0: ( 1, 3, 30)
2594 19:26:26.216436 Total UI for P1: 0, mck2ui 16
2595 19:26:26.219695 best dqsien dly found for B1: ( 1, 4, 0)
2596 19:26:26.222753 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2597 19:26:26.227066 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2598 19:26:26.227550
2599 19:26:26.229590 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2600 19:26:26.233281 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2601 19:26:26.236352 [Gating] SW calibration Done
2602 19:26:26.236728 ==
2603 19:26:26.239840 Dram Type= 6, Freq= 0, CH_0, rank 0
2604 19:26:26.246337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2605 19:26:26.246737 ==
2606 19:26:26.247140 RX Vref Scan: 0
2607 19:26:26.247517
2608 19:26:26.249857 RX Vref 0 -> 0, step: 1
2609 19:26:26.250257
2610 19:26:26.252701 RX Delay -40 -> 252, step: 8
2611 19:26:26.256133 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2612 19:26:26.259507 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2613 19:26:26.262703 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2614 19:26:26.266184 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2615 19:26:26.273232 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2616 19:26:26.276375 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2617 19:26:26.279764 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2618 19:26:26.283236 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2619 19:26:26.286126 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2620 19:26:26.289463 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2621 19:26:26.296402 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2622 19:26:26.299447 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
2623 19:26:26.303192 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2624 19:26:26.306350 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2625 19:26:26.309558 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2626 19:26:26.316395 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2627 19:26:26.316821 ==
2628 19:26:26.319820 Dram Type= 6, Freq= 0, CH_0, rank 0
2629 19:26:26.323072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2630 19:26:26.323494 ==
2631 19:26:26.323835 DQS Delay:
2632 19:26:26.326360 DQS0 = 0, DQS1 = 0
2633 19:26:26.326939 DQM Delay:
2634 19:26:26.329400 DQM0 = 113, DQM1 = 103
2635 19:26:26.329861 DQ Delay:
2636 19:26:26.332860 DQ0 =115, DQ1 =111, DQ2 =115, DQ3 =107
2637 19:26:26.336504 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2638 19:26:26.339425 DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =99
2639 19:26:26.342897 DQ12 =107, DQ13 =111, DQ14 =115, DQ15 =111
2640 19:26:26.343325
2641 19:26:26.343656
2642 19:26:26.346376 ==
2643 19:26:26.346800 Dram Type= 6, Freq= 0, CH_0, rank 0
2644 19:26:26.352814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2645 19:26:26.353048 ==
2646 19:26:26.353227
2647 19:26:26.353394
2648 19:26:26.356119 TX Vref Scan disable
2649 19:26:26.356347 == TX Byte 0 ==
2650 19:26:26.359548 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2651 19:26:26.365899 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2652 19:26:26.366061 == TX Byte 1 ==
2653 19:26:26.369415 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2654 19:26:26.375711 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2655 19:26:26.375831 ==
2656 19:26:26.379584 Dram Type= 6, Freq= 0, CH_0, rank 0
2657 19:26:26.382385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2658 19:26:26.382488 ==
2659 19:26:26.394625 TX Vref=22, minBit 10, minWin=24, winSum=414
2660 19:26:26.398426 TX Vref=24, minBit 8, minWin=25, winSum=419
2661 19:26:26.401458 TX Vref=26, minBit 8, minWin=25, winSum=428
2662 19:26:26.404748 TX Vref=28, minBit 4, minWin=26, winSum=429
2663 19:26:26.408177 TX Vref=30, minBit 8, minWin=26, winSum=432
2664 19:26:26.414538 TX Vref=32, minBit 8, minWin=25, winSum=426
2665 19:26:26.418051 [TxChooseVref] Worse bit 8, Min win 26, Win sum 432, Final Vref 30
2666 19:26:26.418196
2667 19:26:26.421431 Final TX Range 1 Vref 30
2668 19:26:26.421574
2669 19:26:26.421693 ==
2670 19:26:26.424629 Dram Type= 6, Freq= 0, CH_0, rank 0
2671 19:26:26.428336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2672 19:26:26.428443 ==
2673 19:26:26.428518
2674 19:26:26.431647
2675 19:26:26.431740 TX Vref Scan disable
2676 19:26:26.435450 == TX Byte 0 ==
2677 19:26:26.438218 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2678 19:26:26.441847 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2679 19:26:26.445322 == TX Byte 1 ==
2680 19:26:26.448178 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2681 19:26:26.451929 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2682 19:26:26.452111
2683 19:26:26.454849 [DATLAT]
2684 19:26:26.455003 Freq=1200, CH0 RK0
2685 19:26:26.455112
2686 19:26:26.458280 DATLAT Default: 0xd
2687 19:26:26.458400 0, 0xFFFF, sum = 0
2688 19:26:26.461786 1, 0xFFFF, sum = 0
2689 19:26:26.461907 2, 0xFFFF, sum = 0
2690 19:26:26.464775 3, 0xFFFF, sum = 0
2691 19:26:26.464915 4, 0xFFFF, sum = 0
2692 19:26:26.468353 5, 0xFFFF, sum = 0
2693 19:26:26.468502 6, 0xFFFF, sum = 0
2694 19:26:26.471230 7, 0xFFFF, sum = 0
2695 19:26:26.474926 8, 0xFFFF, sum = 0
2696 19:26:26.475103 9, 0xFFFF, sum = 0
2697 19:26:26.478552 10, 0xFFFF, sum = 0
2698 19:26:26.478749 11, 0xFFFF, sum = 0
2699 19:26:26.481564 12, 0x0, sum = 1
2700 19:26:26.481760 13, 0x0, sum = 2
2701 19:26:26.484847 14, 0x0, sum = 3
2702 19:26:26.485077 15, 0x0, sum = 4
2703 19:26:26.485261 best_step = 13
2704 19:26:26.485428
2705 19:26:26.488240 ==
2706 19:26:26.491834 Dram Type= 6, Freq= 0, CH_0, rank 0
2707 19:26:26.494989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2708 19:26:26.495350 ==
2709 19:26:26.495635 RX Vref Scan: 1
2710 19:26:26.495901
2711 19:26:26.498540 Set Vref Range= 32 -> 127
2712 19:26:26.498950
2713 19:26:26.501418 RX Vref 32 -> 127, step: 1
2714 19:26:26.501835
2715 19:26:26.505110 RX Delay -37 -> 252, step: 4
2716 19:26:26.505499
2717 19:26:26.508403 Set Vref, RX VrefLevel [Byte0]: 32
2718 19:26:26.511767 [Byte1]: 32
2719 19:26:26.512157
2720 19:26:26.515071 Set Vref, RX VrefLevel [Byte0]: 33
2721 19:26:26.518162 [Byte1]: 33
2722 19:26:26.521628
2723 19:26:26.522132 Set Vref, RX VrefLevel [Byte0]: 34
2724 19:26:26.525329 [Byte1]: 34
2725 19:26:26.529648
2726 19:26:26.530177 Set Vref, RX VrefLevel [Byte0]: 35
2727 19:26:26.532829 [Byte1]: 35
2728 19:26:26.538019
2729 19:26:26.538442 Set Vref, RX VrefLevel [Byte0]: 36
2730 19:26:26.541373 [Byte1]: 36
2731 19:26:26.545586
2732 19:26:26.546008 Set Vref, RX VrefLevel [Byte0]: 37
2733 19:26:26.549158 [Byte1]: 37
2734 19:26:26.554185
2735 19:26:26.554705 Set Vref, RX VrefLevel [Byte0]: 38
2736 19:26:26.557142 [Byte1]: 38
2737 19:26:26.561886
2738 19:26:26.562401 Set Vref, RX VrefLevel [Byte0]: 39
2739 19:26:26.565244 [Byte1]: 39
2740 19:26:26.570093
2741 19:26:26.570611 Set Vref, RX VrefLevel [Byte0]: 40
2742 19:26:26.573415 [Byte1]: 40
2743 19:26:26.578058
2744 19:26:26.578483 Set Vref, RX VrefLevel [Byte0]: 41
2745 19:26:26.581021 [Byte1]: 41
2746 19:26:26.585908
2747 19:26:26.586423 Set Vref, RX VrefLevel [Byte0]: 42
2748 19:26:26.589563 [Byte1]: 42
2749 19:26:26.594339
2750 19:26:26.594862 Set Vref, RX VrefLevel [Byte0]: 43
2751 19:26:26.597118 [Byte1]: 43
2752 19:26:26.602117
2753 19:26:26.602634 Set Vref, RX VrefLevel [Byte0]: 44
2754 19:26:26.605741 [Byte1]: 44
2755 19:26:26.609993
2756 19:26:26.610513 Set Vref, RX VrefLevel [Byte0]: 45
2757 19:26:26.613372 [Byte1]: 45
2758 19:26:26.617775
2759 19:26:26.618312 Set Vref, RX VrefLevel [Byte0]: 46
2760 19:26:26.621484 [Byte1]: 46
2761 19:26:26.626003
2762 19:26:26.626427 Set Vref, RX VrefLevel [Byte0]: 47
2763 19:26:26.629288 [Byte1]: 47
2764 19:26:26.633706
2765 19:26:26.634178 Set Vref, RX VrefLevel [Byte0]: 48
2766 19:26:26.636767 [Byte1]: 48
2767 19:26:26.641421
2768 19:26:26.641930 Set Vref, RX VrefLevel [Byte0]: 49
2769 19:26:26.645215 [Byte1]: 49
2770 19:26:26.649345
2771 19:26:26.649893 Set Vref, RX VrefLevel [Byte0]: 50
2772 19:26:26.653248 [Byte1]: 50
2773 19:26:26.657805
2774 19:26:26.658241 Set Vref, RX VrefLevel [Byte0]: 51
2775 19:26:26.660828 [Byte1]: 51
2776 19:26:26.665605
2777 19:26:26.666028 Set Vref, RX VrefLevel [Byte0]: 52
2778 19:26:26.668954 [Byte1]: 52
2779 19:26:26.673736
2780 19:26:26.674159 Set Vref, RX VrefLevel [Byte0]: 53
2781 19:26:26.676877 [Byte1]: 53
2782 19:26:26.681683
2783 19:26:26.682104 Set Vref, RX VrefLevel [Byte0]: 54
2784 19:26:26.685212 [Byte1]: 54
2785 19:26:26.690200
2786 19:26:26.690717 Set Vref, RX VrefLevel [Byte0]: 55
2787 19:26:26.692971 [Byte1]: 55
2788 19:26:26.697882
2789 19:26:26.698400 Set Vref, RX VrefLevel [Byte0]: 56
2790 19:26:26.701504 [Byte1]: 56
2791 19:26:26.705905
2792 19:26:26.706567 Set Vref, RX VrefLevel [Byte0]: 57
2793 19:26:26.709313 [Byte1]: 57
2794 19:26:26.713948
2795 19:26:26.714468 Set Vref, RX VrefLevel [Byte0]: 58
2796 19:26:26.717252 [Byte1]: 58
2797 19:26:26.721644
2798 19:26:26.722155 Set Vref, RX VrefLevel [Byte0]: 59
2799 19:26:26.724802 [Byte1]: 59
2800 19:26:26.729685
2801 19:26:26.730201 Set Vref, RX VrefLevel [Byte0]: 60
2802 19:26:26.733393 [Byte1]: 60
2803 19:26:26.738070
2804 19:26:26.738591 Set Vref, RX VrefLevel [Byte0]: 61
2805 19:26:26.741010 [Byte1]: 61
2806 19:26:26.745759
2807 19:26:26.746284 Set Vref, RX VrefLevel [Byte0]: 62
2808 19:26:26.749204 [Byte1]: 62
2809 19:26:26.753907
2810 19:26:26.754426 Set Vref, RX VrefLevel [Byte0]: 63
2811 19:26:26.757269 [Byte1]: 63
2812 19:26:26.761768
2813 19:26:26.762287 Set Vref, RX VrefLevel [Byte0]: 64
2814 19:26:26.765055 [Byte1]: 64
2815 19:26:26.769813
2816 19:26:26.770305 Set Vref, RX VrefLevel [Byte0]: 65
2817 19:26:26.773144 [Byte1]: 65
2818 19:26:26.777641
2819 19:26:26.778206 Set Vref, RX VrefLevel [Byte0]: 66
2820 19:26:26.780574 [Byte1]: 66
2821 19:26:26.785708
2822 19:26:26.786130 Set Vref, RX VrefLevel [Byte0]: 67
2823 19:26:26.788916 [Byte1]: 67
2824 19:26:26.793623
2825 19:26:26.794046 Set Vref, RX VrefLevel [Byte0]: 68
2826 19:26:26.797256 [Byte1]: 68
2827 19:26:26.801315
2828 19:26:26.801782 Set Vref, RX VrefLevel [Byte0]: 69
2829 19:26:26.804938 [Byte1]: 69
2830 19:26:26.809729
2831 19:26:26.810400 Set Vref, RX VrefLevel [Byte0]: 70
2832 19:26:26.812935 [Byte1]: 70
2833 19:26:26.817904
2834 19:26:26.818327 Set Vref, RX VrefLevel [Byte0]: 71
2835 19:26:26.820734 [Byte1]: 71
2836 19:26:26.825364
2837 19:26:26.825835 Set Vref, RX VrefLevel [Byte0]: 72
2838 19:26:26.828642 [Byte1]: 72
2839 19:26:26.833559
2840 19:26:26.834018 Set Vref, RX VrefLevel [Byte0]: 73
2841 19:26:26.837099 [Byte1]: 73
2842 19:26:26.841807
2843 19:26:26.842231 Set Vref, RX VrefLevel [Byte0]: 74
2844 19:26:26.844880 [Byte1]: 74
2845 19:26:26.849790
2846 19:26:26.850214 Final RX Vref Byte 0 = 60 to rank0
2847 19:26:26.853125 Final RX Vref Byte 1 = 54 to rank0
2848 19:26:26.856158 Final RX Vref Byte 0 = 60 to rank1
2849 19:26:26.860060 Final RX Vref Byte 1 = 54 to rank1==
2850 19:26:26.862844 Dram Type= 6, Freq= 0, CH_0, rank 0
2851 19:26:26.869732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2852 19:26:26.870180 ==
2853 19:26:26.870567 DQS Delay:
2854 19:26:26.870885 DQS0 = 0, DQS1 = 0
2855 19:26:26.872951 DQM Delay:
2856 19:26:26.873374 DQM0 = 112, DQM1 = 102
2857 19:26:26.876441 DQ Delay:
2858 19:26:26.879973 DQ0 =112, DQ1 =112, DQ2 =112, DQ3 =108
2859 19:26:26.883306 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2860 19:26:26.886795 DQ8 =92, DQ9 =84, DQ10 =104, DQ11 =94
2861 19:26:26.889905 DQ12 =108, DQ13 =108, DQ14 =116, DQ15 =110
2862 19:26:26.890336
2863 19:26:26.890665
2864 19:26:26.896201 [DQSOSCAuto] RK0, (LSB)MR18= 0xfdfc, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
2865 19:26:26.899971 CH0 RK0: MR19=303, MR18=FDFC
2866 19:26:26.906187 CH0_RK0: MR19=0x303, MR18=0xFDFC, DQSOSC=411, MR23=63, INC=38, DEC=25
2867 19:26:26.906697
2868 19:26:26.909810 ----->DramcWriteLeveling(PI) begin...
2869 19:26:26.910243 ==
2870 19:26:26.913372 Dram Type= 6, Freq= 0, CH_0, rank 1
2871 19:26:26.916669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2872 19:26:26.917218 ==
2873 19:26:26.920019 Write leveling (Byte 0): 31 => 31
2874 19:26:26.923040 Write leveling (Byte 1): 30 => 30
2875 19:26:26.926389 DramcWriteLeveling(PI) end<-----
2876 19:26:26.926814
2877 19:26:26.927228 ==
2878 19:26:26.929602 Dram Type= 6, Freq= 0, CH_0, rank 1
2879 19:26:26.933065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2880 19:26:26.936427 ==
2881 19:26:26.936968 [Gating] SW mode calibration
2882 19:26:26.946593 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2883 19:26:26.949697 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2884 19:26:26.953183 0 15 0 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
2885 19:26:26.960145 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2886 19:26:26.963669 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2887 19:26:26.967150 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2888 19:26:26.973598 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2889 19:26:26.976504 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2890 19:26:26.979923 0 15 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
2891 19:26:26.986831 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
2892 19:26:26.990325 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2893 19:26:26.992946 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2894 19:26:26.999960 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2895 19:26:27.003318 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2896 19:26:27.006958 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2897 19:26:27.013088 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2898 19:26:27.016513 1 0 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
2899 19:26:27.020019 1 0 28 | B1->B0 | 2323 4141 | 0 1 | (0 0) (0 0)
2900 19:26:27.023157 1 1 0 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
2901 19:26:27.029653 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2902 19:26:27.033273 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2903 19:26:27.036643 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2904 19:26:27.043041 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2905 19:26:27.046002 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2906 19:26:27.049686 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2907 19:26:27.056237 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2908 19:26:27.059844 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2909 19:26:27.062681 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2910 19:26:27.069130 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2911 19:26:27.072779 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2912 19:26:27.076431 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2913 19:26:27.082974 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2914 19:26:27.085986 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2915 19:26:27.089950 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2916 19:26:27.096101 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2917 19:26:27.099456 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2918 19:26:27.102980 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2919 19:26:27.109683 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 19:26:27.113130 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 19:26:27.116058 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 19:26:27.122915 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2923 19:26:27.126337 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2924 19:26:27.129467 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2925 19:26:27.132788 Total UI for P1: 0, mck2ui 16
2926 19:26:27.136183 best dqsien dly found for B0: ( 1, 3, 26)
2927 19:26:27.139214 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2928 19:26:27.142522 Total UI for P1: 0, mck2ui 16
2929 19:26:27.146031 best dqsien dly found for B1: ( 1, 4, 0)
2930 19:26:27.149744 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2931 19:26:27.156172 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2932 19:26:27.156670
2933 19:26:27.159686 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2934 19:26:27.162583 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2935 19:26:27.166155 [Gating] SW calibration Done
2936 19:26:27.166583 ==
2937 19:26:27.169480 Dram Type= 6, Freq= 0, CH_0, rank 1
2938 19:26:27.172506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2939 19:26:27.172986 ==
2940 19:26:27.173474 RX Vref Scan: 0
2941 19:26:27.173921
2942 19:26:27.176051 RX Vref 0 -> 0, step: 1
2943 19:26:27.176630
2944 19:26:27.179566 RX Delay -40 -> 252, step: 8
2945 19:26:27.182595 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2946 19:26:27.186110 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2947 19:26:27.192507 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2948 19:26:27.195972 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2949 19:26:27.199073 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2950 19:26:27.202438 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2951 19:26:27.206047 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2952 19:26:27.212554 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2953 19:26:27.216145 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2954 19:26:27.219102 iDelay=200, Bit 9, Center 87 (16 ~ 159) 144
2955 19:26:27.222691 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2956 19:26:27.226291 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2957 19:26:27.232725 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2958 19:26:27.236115 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2959 19:26:27.239114 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2960 19:26:27.242705 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2961 19:26:27.243132 ==
2962 19:26:27.246297 Dram Type= 6, Freq= 0, CH_0, rank 1
2963 19:26:27.249388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2964 19:26:27.253228 ==
2965 19:26:27.253821 DQS Delay:
2966 19:26:27.254167 DQS0 = 0, DQS1 = 0
2967 19:26:27.256219 DQM Delay:
2968 19:26:27.256735 DQM0 = 112, DQM1 = 102
2969 19:26:27.259506 DQ Delay:
2970 19:26:27.262914 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2971 19:26:27.266321 DQ4 =115, DQ5 =103, DQ6 =119, DQ7 =123
2972 19:26:27.269477 DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =95
2973 19:26:27.272516 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =111
2974 19:26:27.272947
2975 19:26:27.273338
2976 19:26:27.273709 ==
2977 19:26:27.275924 Dram Type= 6, Freq= 0, CH_0, rank 1
2978 19:26:27.279147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2979 19:26:27.279760 ==
2980 19:26:27.280175
2981 19:26:27.280648
2982 19:26:27.282896 TX Vref Scan disable
2983 19:26:27.285994 == TX Byte 0 ==
2984 19:26:27.289615 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2985 19:26:27.292549 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2986 19:26:27.295857 == TX Byte 1 ==
2987 19:26:27.299498 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2988 19:26:27.302786 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2989 19:26:27.303273 ==
2990 19:26:27.306286 Dram Type= 6, Freq= 0, CH_0, rank 1
2991 19:26:27.309174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2992 19:26:27.312994 ==
2993 19:26:27.322593 TX Vref=22, minBit 0, minWin=26, winSum=426
2994 19:26:27.326202 TX Vref=24, minBit 1, minWin=26, winSum=426
2995 19:26:27.329931 TX Vref=26, minBit 1, minWin=26, winSum=433
2996 19:26:27.332831 TX Vref=28, minBit 14, minWin=26, winSum=441
2997 19:26:27.336263 TX Vref=30, minBit 8, minWin=26, winSum=443
2998 19:26:27.342620 TX Vref=32, minBit 10, minWin=26, winSum=439
2999 19:26:27.346386 [TxChooseVref] Worse bit 8, Min win 26, Win sum 443, Final Vref 30
3000 19:26:27.346908
3001 19:26:27.349592 Final TX Range 1 Vref 30
3002 19:26:27.350122
3003 19:26:27.350460 ==
3004 19:26:27.352875 Dram Type= 6, Freq= 0, CH_0, rank 1
3005 19:26:27.356849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3006 19:26:27.357373 ==
3007 19:26:27.357762
3008 19:26:27.359653
3009 19:26:27.360170 TX Vref Scan disable
3010 19:26:27.362596 == TX Byte 0 ==
3011 19:26:27.366232 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3012 19:26:27.369482 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3013 19:26:27.372921 == TX Byte 1 ==
3014 19:26:27.376241 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3015 19:26:27.379888 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3016 19:26:27.380411
3017 19:26:27.382802 [DATLAT]
3018 19:26:27.383321 Freq=1200, CH0 RK1
3019 19:26:27.383662
3020 19:26:27.386071 DATLAT Default: 0xd
3021 19:26:27.386492 0, 0xFFFF, sum = 0
3022 19:26:27.389292 1, 0xFFFF, sum = 0
3023 19:26:27.389855 2, 0xFFFF, sum = 0
3024 19:26:27.392416 3, 0xFFFF, sum = 0
3025 19:26:27.396237 4, 0xFFFF, sum = 0
3026 19:26:27.396783 5, 0xFFFF, sum = 0
3027 19:26:27.399244 6, 0xFFFF, sum = 0
3028 19:26:27.399676 7, 0xFFFF, sum = 0
3029 19:26:27.402454 8, 0xFFFF, sum = 0
3030 19:26:27.402885 9, 0xFFFF, sum = 0
3031 19:26:27.406049 10, 0xFFFF, sum = 0
3032 19:26:27.406480 11, 0xFFFF, sum = 0
3033 19:26:27.409268 12, 0x0, sum = 1
3034 19:26:27.409861 13, 0x0, sum = 2
3035 19:26:27.412259 14, 0x0, sum = 3
3036 19:26:27.412780 15, 0x0, sum = 4
3037 19:26:27.413251 best_step = 13
3038 19:26:27.416027
3039 19:26:27.416577 ==
3040 19:26:27.419163 Dram Type= 6, Freq= 0, CH_0, rank 1
3041 19:26:27.422529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3042 19:26:27.422963 ==
3043 19:26:27.423395 RX Vref Scan: 0
3044 19:26:27.423802
3045 19:26:27.426109 RX Vref 0 -> 0, step: 1
3046 19:26:27.426604
3047 19:26:27.429332 RX Delay -29 -> 252, step: 4
3048 19:26:27.432730 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3049 19:26:27.439114 iDelay=195, Bit 1, Center 110 (39 ~ 182) 144
3050 19:26:27.442683 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3051 19:26:27.445983 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3052 19:26:27.449759 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3053 19:26:27.452522 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3054 19:26:27.459315 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3055 19:26:27.462813 iDelay=195, Bit 7, Center 120 (47 ~ 194) 148
3056 19:26:27.466023 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3057 19:26:27.469175 iDelay=195, Bit 9, Center 84 (15 ~ 154) 140
3058 19:26:27.472727 iDelay=195, Bit 10, Center 104 (35 ~ 174) 140
3059 19:26:27.475712 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3060 19:26:27.482707 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3061 19:26:27.485846 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3062 19:26:27.489246 iDelay=195, Bit 14, Center 114 (47 ~ 182) 136
3063 19:26:27.492305 iDelay=195, Bit 15, Center 110 (43 ~ 178) 136
3064 19:26:27.492723 ==
3065 19:26:27.495894 Dram Type= 6, Freq= 0, CH_0, rank 1
3066 19:26:27.502422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3067 19:26:27.502505 ==
3068 19:26:27.502569 DQS Delay:
3069 19:26:27.505398 DQS0 = 0, DQS1 = 0
3070 19:26:27.505486 DQM Delay:
3071 19:26:27.505565 DQM0 = 110, DQM1 = 101
3072 19:26:27.509146 DQ Delay:
3073 19:26:27.512899 DQ0 =108, DQ1 =110, DQ2 =108, DQ3 =108
3074 19:26:27.515809 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =120
3075 19:26:27.519260 DQ8 =90, DQ9 =84, DQ10 =104, DQ11 =94
3076 19:26:27.522380 DQ12 =108, DQ13 =108, DQ14 =114, DQ15 =110
3077 19:26:27.522574
3078 19:26:27.522709
3079 19:26:27.529451 [DQSOSCAuto] RK1, (LSB)MR18= 0xff8, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 404 ps
3080 19:26:27.532339 CH0 RK1: MR19=403, MR18=FF8
3081 19:26:27.539175 CH0_RK1: MR19=0x403, MR18=0xFF8, DQSOSC=404, MR23=63, INC=40, DEC=26
3082 19:26:27.542427 [RxdqsGatingPostProcess] freq 1200
3083 19:26:27.549338 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3084 19:26:27.552551 best DQS0 dly(2T, 0.5T) = (0, 11)
3085 19:26:27.552999 best DQS1 dly(2T, 0.5T) = (0, 12)
3086 19:26:27.556079 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3087 19:26:27.559067 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3088 19:26:27.562327 best DQS0 dly(2T, 0.5T) = (0, 11)
3089 19:26:27.565908 best DQS1 dly(2T, 0.5T) = (0, 12)
3090 19:26:27.568981 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3091 19:26:27.572523 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3092 19:26:27.575551 Pre-setting of DQS Precalculation
3093 19:26:27.582797 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3094 19:26:27.583335 ==
3095 19:26:27.585579 Dram Type= 6, Freq= 0, CH_1, rank 0
3096 19:26:27.589404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3097 19:26:27.589980 ==
3098 19:26:27.595892 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3099 19:26:27.599393 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3100 19:26:27.608606 [CA 0] Center 37 (7~67) winsize 61
3101 19:26:27.611966 [CA 1] Center 37 (7~68) winsize 62
3102 19:26:27.614928 [CA 2] Center 34 (4~64) winsize 61
3103 19:26:27.618614 [CA 3] Center 34 (4~64) winsize 61
3104 19:26:27.621991 [CA 4] Center 34 (4~64) winsize 61
3105 19:26:27.624819 [CA 5] Center 33 (3~63) winsize 61
3106 19:26:27.625255
3107 19:26:27.628392 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3108 19:26:27.628942
3109 19:26:27.631677 [CATrainingPosCal] consider 1 rank data
3110 19:26:27.634981 u2DelayCellTimex100 = 270/100 ps
3111 19:26:27.638248 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3112 19:26:27.641632 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3113 19:26:27.648472 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3114 19:26:27.652103 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3115 19:26:27.654838 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3116 19:26:27.658456 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3117 19:26:27.658976
3118 19:26:27.662069 CA PerBit enable=1, Macro0, CA PI delay=33
3119 19:26:27.662593
3120 19:26:27.664607 [CBTSetCACLKResult] CA Dly = 33
3121 19:26:27.665021 CS Dly: 6 (0~37)
3122 19:26:27.667981 ==
3123 19:26:27.668396 Dram Type= 6, Freq= 0, CH_1, rank 1
3124 19:26:27.674571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3125 19:26:27.675079 ==
3126 19:26:27.678107 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3127 19:26:27.684693 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3128 19:26:27.693973 [CA 0] Center 37 (8~67) winsize 60
3129 19:26:27.697299 [CA 1] Center 37 (7~68) winsize 62
3130 19:26:27.700852 [CA 2] Center 34 (4~65) winsize 62
3131 19:26:27.704025 [CA 3] Center 33 (3~64) winsize 62
3132 19:26:27.707656 [CA 4] Center 34 (4~65) winsize 62
3133 19:26:27.710414 [CA 5] Center 32 (2~63) winsize 62
3134 19:26:27.710831
3135 19:26:27.714028 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3136 19:26:27.714554
3137 19:26:27.717389 [CATrainingPosCal] consider 2 rank data
3138 19:26:27.721014 u2DelayCellTimex100 = 270/100 ps
3139 19:26:27.723883 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3140 19:26:27.727385 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3141 19:26:27.734114 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3142 19:26:27.737597 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3143 19:26:27.740416 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3144 19:26:27.744012 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3145 19:26:27.744561
3146 19:26:27.747713 CA PerBit enable=1, Macro0, CA PI delay=33
3147 19:26:27.748239
3148 19:26:27.750388 [CBTSetCACLKResult] CA Dly = 33
3149 19:26:27.750834 CS Dly: 7 (0~40)
3150 19:26:27.751178
3151 19:26:27.754141 ----->DramcWriteLeveling(PI) begin...
3152 19:26:27.757056 ==
3153 19:26:27.757501 Dram Type= 6, Freq= 0, CH_1, rank 0
3154 19:26:27.764307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3155 19:26:27.764876 ==
3156 19:26:27.767941 Write leveling (Byte 0): 28 => 28
3157 19:26:27.771071 Write leveling (Byte 1): 29 => 29
3158 19:26:27.771489 DramcWriteLeveling(PI) end<-----
3159 19:26:27.773942
3160 19:26:27.774358 ==
3161 19:26:27.777666 Dram Type= 6, Freq= 0, CH_1, rank 0
3162 19:26:27.781008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3163 19:26:27.781460 ==
3164 19:26:27.783982 [Gating] SW mode calibration
3165 19:26:27.790873 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3166 19:26:27.793675 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3167 19:26:27.800335 0 15 0 | B1->B0 | 2c2c 2323 | 1 0 | (0 0) (0 0)
3168 19:26:27.803707 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3169 19:26:27.807496 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3170 19:26:27.813559 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3171 19:26:27.817233 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3172 19:26:27.820561 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3173 19:26:27.827140 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3174 19:26:27.830183 0 15 28 | B1->B0 | 3131 3232 | 0 0 | (0 0) (0 0)
3175 19:26:27.833707 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3176 19:26:27.840386 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3177 19:26:27.844157 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3178 19:26:27.847397 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3179 19:26:27.854311 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3180 19:26:27.857313 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3181 19:26:27.860490 1 0 24 | B1->B0 | 2424 2323 | 1 0 | (0 0) (0 0)
3182 19:26:27.867955 1 0 28 | B1->B0 | 3736 3131 | 1 1 | (0 0) (1 1)
3183 19:26:27.870527 1 1 0 | B1->B0 | 4545 4343 | 0 0 | (0 0) (0 0)
3184 19:26:27.874130 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3185 19:26:27.877447 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3186 19:26:27.884002 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3187 19:26:27.887648 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3188 19:26:27.890639 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3189 19:26:27.897354 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3190 19:26:27.900952 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3191 19:26:27.904328 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3192 19:26:27.910699 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3193 19:26:27.914380 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3194 19:26:27.917443 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3195 19:26:27.923958 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3196 19:26:27.927480 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3197 19:26:27.930993 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3198 19:26:27.937198 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3199 19:26:27.940584 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3200 19:26:27.943759 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3201 19:26:27.950836 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3202 19:26:27.953894 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 19:26:27.957369 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 19:26:27.964130 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 19:26:27.967464 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 19:26:27.970610 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3207 19:26:27.977270 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3208 19:26:27.977825 Total UI for P1: 0, mck2ui 16
3209 19:26:27.980673 best dqsien dly found for B0: ( 1, 3, 28)
3210 19:26:27.984094 Total UI for P1: 0, mck2ui 16
3211 19:26:27.987358 best dqsien dly found for B1: ( 1, 3, 28)
3212 19:26:27.990956 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3213 19:26:27.997249 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3214 19:26:27.997696
3215 19:26:28.001000 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3216 19:26:28.004082 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3217 19:26:28.007325 [Gating] SW calibration Done
3218 19:26:28.007744 ==
3219 19:26:28.010894 Dram Type= 6, Freq= 0, CH_1, rank 0
3220 19:26:28.013898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3221 19:26:28.014318 ==
3222 19:26:28.014643 RX Vref Scan: 0
3223 19:26:28.017494
3224 19:26:28.017929 RX Vref 0 -> 0, step: 1
3225 19:26:28.018251
3226 19:26:28.020437 RX Delay -40 -> 252, step: 8
3227 19:26:28.024223 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3228 19:26:28.027743 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3229 19:26:28.034122 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3230 19:26:28.037044 iDelay=200, Bit 3, Center 111 (32 ~ 191) 160
3231 19:26:28.040663 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3232 19:26:28.043746 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3233 19:26:28.047388 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3234 19:26:28.054181 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3235 19:26:28.057270 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3236 19:26:28.060463 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3237 19:26:28.064045 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3238 19:26:28.067162 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3239 19:26:28.070943 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3240 19:26:28.077286 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3241 19:26:28.080772 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3242 19:26:28.083881 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3243 19:26:28.084294 ==
3244 19:26:28.087329 Dram Type= 6, Freq= 0, CH_1, rank 0
3245 19:26:28.090974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3246 19:26:28.094107 ==
3247 19:26:28.094530 DQS Delay:
3248 19:26:28.094861 DQS0 = 0, DQS1 = 0
3249 19:26:28.097412 DQM Delay:
3250 19:26:28.097872 DQM0 = 114, DQM1 = 105
3251 19:26:28.100905 DQ Delay:
3252 19:26:28.103824 DQ0 =123, DQ1 =107, DQ2 =99, DQ3 =111
3253 19:26:28.107393 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =115
3254 19:26:28.110379 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =103
3255 19:26:28.113844 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =111
3256 19:26:28.114276
3257 19:26:28.114647
3258 19:26:28.114962 ==
3259 19:26:28.117329 Dram Type= 6, Freq= 0, CH_1, rank 0
3260 19:26:28.120941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3261 19:26:28.121387 ==
3262 19:26:28.121798
3263 19:26:28.122118
3264 19:26:28.123982 TX Vref Scan disable
3265 19:26:28.127597 == TX Byte 0 ==
3266 19:26:28.130490 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3267 19:26:28.134022 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3268 19:26:28.137500 == TX Byte 1 ==
3269 19:26:28.140798 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3270 19:26:28.144095 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3271 19:26:28.144663 ==
3272 19:26:28.147701 Dram Type= 6, Freq= 0, CH_1, rank 0
3273 19:26:28.150560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3274 19:26:28.151019 ==
3275 19:26:28.163882 TX Vref=22, minBit 8, minWin=24, winSum=409
3276 19:26:28.167134 TX Vref=24, minBit 8, minWin=25, winSum=418
3277 19:26:28.170276 TX Vref=26, minBit 11, minWin=25, winSum=423
3278 19:26:28.173500 TX Vref=28, minBit 9, minWin=25, winSum=426
3279 19:26:28.177407 TX Vref=30, minBit 9, minWin=25, winSum=425
3280 19:26:28.184127 TX Vref=32, minBit 8, minWin=25, winSum=426
3281 19:26:28.187358 [TxChooseVref] Worse bit 9, Min win 25, Win sum 426, Final Vref 28
3282 19:26:28.187945
3283 19:26:28.190307 Final TX Range 1 Vref 28
3284 19:26:28.190731
3285 19:26:28.191061 ==
3286 19:26:28.193776 Dram Type= 6, Freq= 0, CH_1, rank 0
3287 19:26:28.196842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3288 19:26:28.197271 ==
3289 19:26:28.200583
3290 19:26:28.201001
3291 19:26:28.201396 TX Vref Scan disable
3292 19:26:28.203490 == TX Byte 0 ==
3293 19:26:28.206948 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3294 19:26:28.210087 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3295 19:26:28.213780 == TX Byte 1 ==
3296 19:26:28.217274 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3297 19:26:28.220162 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3298 19:26:28.223601
3299 19:26:28.224018 [DATLAT]
3300 19:26:28.224347 Freq=1200, CH1 RK0
3301 19:26:28.224656
3302 19:26:28.227231 DATLAT Default: 0xd
3303 19:26:28.227654 0, 0xFFFF, sum = 0
3304 19:26:28.230365 1, 0xFFFF, sum = 0
3305 19:26:28.230795 2, 0xFFFF, sum = 0
3306 19:26:28.234006 3, 0xFFFF, sum = 0
3307 19:26:28.236906 4, 0xFFFF, sum = 0
3308 19:26:28.237332 5, 0xFFFF, sum = 0
3309 19:26:28.240915 6, 0xFFFF, sum = 0
3310 19:26:28.241444 7, 0xFFFF, sum = 0
3311 19:26:28.243525 8, 0xFFFF, sum = 0
3312 19:26:28.243955 9, 0xFFFF, sum = 0
3313 19:26:28.247154 10, 0xFFFF, sum = 0
3314 19:26:28.247681 11, 0xFFFF, sum = 0
3315 19:26:28.250215 12, 0x0, sum = 1
3316 19:26:28.250646 13, 0x0, sum = 2
3317 19:26:28.253925 14, 0x0, sum = 3
3318 19:26:28.254492 15, 0x0, sum = 4
3319 19:26:28.254835 best_step = 13
3320 19:26:28.257394
3321 19:26:28.257956 ==
3322 19:26:28.260230 Dram Type= 6, Freq= 0, CH_1, rank 0
3323 19:26:28.263672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3324 19:26:28.264101 ==
3325 19:26:28.264438 RX Vref Scan: 1
3326 19:26:28.264750
3327 19:26:28.267453 Set Vref Range= 32 -> 127
3328 19:26:28.267975
3329 19:26:28.270196 RX Vref 32 -> 127, step: 1
3330 19:26:28.270617
3331 19:26:28.273612 RX Delay -21 -> 252, step: 4
3332 19:26:28.274034
3333 19:26:28.276959 Set Vref, RX VrefLevel [Byte0]: 32
3334 19:26:28.280270 [Byte1]: 32
3335 19:26:28.280693
3336 19:26:28.283365 Set Vref, RX VrefLevel [Byte0]: 33
3337 19:26:28.287097 [Byte1]: 33
3338 19:26:28.287521
3339 19:26:28.290350 Set Vref, RX VrefLevel [Byte0]: 34
3340 19:26:28.293842 [Byte1]: 34
3341 19:26:28.298081
3342 19:26:28.298500 Set Vref, RX VrefLevel [Byte0]: 35
3343 19:26:28.301629 [Byte1]: 35
3344 19:26:28.305744
3345 19:26:28.306271 Set Vref, RX VrefLevel [Byte0]: 36
3346 19:26:28.309128 [Byte1]: 36
3347 19:26:28.314124
3348 19:26:28.314637 Set Vref, RX VrefLevel [Byte0]: 37
3349 19:26:28.317501 [Byte1]: 37
3350 19:26:28.321662
3351 19:26:28.322305 Set Vref, RX VrefLevel [Byte0]: 38
3352 19:26:28.324802 [Byte1]: 38
3353 19:26:28.329736
3354 19:26:28.330155 Set Vref, RX VrefLevel [Byte0]: 39
3355 19:26:28.332992 [Byte1]: 39
3356 19:26:28.337772
3357 19:26:28.338183 Set Vref, RX VrefLevel [Byte0]: 40
3358 19:26:28.340979 [Byte1]: 40
3359 19:26:28.345873
3360 19:26:28.346379 Set Vref, RX VrefLevel [Byte0]: 41
3361 19:26:28.349243 [Byte1]: 41
3362 19:26:28.353312
3363 19:26:28.353897 Set Vref, RX VrefLevel [Byte0]: 42
3364 19:26:28.356583 [Byte1]: 42
3365 19:26:28.361554
3366 19:26:28.361967 Set Vref, RX VrefLevel [Byte0]: 43
3367 19:26:28.364553 [Byte1]: 43
3368 19:26:28.369309
3369 19:26:28.369798 Set Vref, RX VrefLevel [Byte0]: 44
3370 19:26:28.372313 [Byte1]: 44
3371 19:26:28.377584
3372 19:26:28.377998 Set Vref, RX VrefLevel [Byte0]: 45
3373 19:26:28.380343 [Byte1]: 45
3374 19:26:28.385440
3375 19:26:28.385887 Set Vref, RX VrefLevel [Byte0]: 46
3376 19:26:28.388362 [Byte1]: 46
3377 19:26:28.393152
3378 19:26:28.393690 Set Vref, RX VrefLevel [Byte0]: 47
3379 19:26:28.396414 [Byte1]: 47
3380 19:26:28.401054
3381 19:26:28.401569 Set Vref, RX VrefLevel [Byte0]: 48
3382 19:26:28.404502 [Byte1]: 48
3383 19:26:28.408680
3384 19:26:28.409100 Set Vref, RX VrefLevel [Byte0]: 49
3385 19:26:28.412325 [Byte1]: 49
3386 19:26:28.416929
3387 19:26:28.417396 Set Vref, RX VrefLevel [Byte0]: 50
3388 19:26:28.420321 [Byte1]: 50
3389 19:26:28.425049
3390 19:26:28.425726 Set Vref, RX VrefLevel [Byte0]: 51
3391 19:26:28.427870 [Byte1]: 51
3392 19:26:28.432617
3393 19:26:28.433060 Set Vref, RX VrefLevel [Byte0]: 52
3394 19:26:28.436055 [Byte1]: 52
3395 19:26:28.440421
3396 19:26:28.440864 Set Vref, RX VrefLevel [Byte0]: 53
3397 19:26:28.444053 [Byte1]: 53
3398 19:26:28.448388
3399 19:26:28.448806 Set Vref, RX VrefLevel [Byte0]: 54
3400 19:26:28.452196 [Byte1]: 54
3401 19:26:28.456995
3402 19:26:28.457615 Set Vref, RX VrefLevel [Byte0]: 55
3403 19:26:28.460004 [Byte1]: 55
3404 19:26:28.464777
3405 19:26:28.465293 Set Vref, RX VrefLevel [Byte0]: 56
3406 19:26:28.468207 [Byte1]: 56
3407 19:26:28.473045
3408 19:26:28.473605 Set Vref, RX VrefLevel [Byte0]: 57
3409 19:26:28.475963 [Byte1]: 57
3410 19:26:28.480667
3411 19:26:28.481180 Set Vref, RX VrefLevel [Byte0]: 58
3412 19:26:28.483679 [Byte1]: 58
3413 19:26:28.488072
3414 19:26:28.488492 Set Vref, RX VrefLevel [Byte0]: 59
3415 19:26:28.491662 [Byte1]: 59
3416 19:26:28.496409
3417 19:26:28.496926 Set Vref, RX VrefLevel [Byte0]: 60
3418 19:26:28.499810 [Byte1]: 60
3419 19:26:28.504278
3420 19:26:28.504792 Set Vref, RX VrefLevel [Byte0]: 61
3421 19:26:28.507697 [Byte1]: 61
3422 19:26:28.512180
3423 19:26:28.512693 Set Vref, RX VrefLevel [Byte0]: 62
3424 19:26:28.515755 [Byte1]: 62
3425 19:26:28.519939
3426 19:26:28.520458 Set Vref, RX VrefLevel [Byte0]: 63
3427 19:26:28.522995 [Byte1]: 63
3428 19:26:28.527868
3429 19:26:28.528435 Set Vref, RX VrefLevel [Byte0]: 64
3430 19:26:28.531550 [Byte1]: 64
3431 19:26:28.535569
3432 19:26:28.536175 Set Vref, RX VrefLevel [Byte0]: 65
3433 19:26:28.539232 [Byte1]: 65
3434 19:26:28.543335
3435 19:26:28.543792 Set Vref, RX VrefLevel [Byte0]: 66
3436 19:26:28.546732 [Byte1]: 66
3437 19:26:28.551292
3438 19:26:28.551744 Set Vref, RX VrefLevel [Byte0]: 67
3439 19:26:28.554703 [Byte1]: 67
3440 19:26:28.559408
3441 19:26:28.559828 Set Vref, RX VrefLevel [Byte0]: 68
3442 19:26:28.562750 [Byte1]: 68
3443 19:26:28.567306
3444 19:26:28.567724 Final RX Vref Byte 0 = 55 to rank0
3445 19:26:28.570732 Final RX Vref Byte 1 = 54 to rank0
3446 19:26:28.574089 Final RX Vref Byte 0 = 55 to rank1
3447 19:26:28.577501 Final RX Vref Byte 1 = 54 to rank1==
3448 19:26:28.581141 Dram Type= 6, Freq= 0, CH_1, rank 0
3449 19:26:28.587650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3450 19:26:28.588452 ==
3451 19:26:28.588816 DQS Delay:
3452 19:26:28.589127 DQS0 = 0, DQS1 = 0
3453 19:26:28.590479 DQM Delay:
3454 19:26:28.590906 DQM0 = 114, DQM1 = 107
3455 19:26:28.593824 DQ Delay:
3456 19:26:28.597017 DQ0 =118, DQ1 =108, DQ2 =104, DQ3 =112
3457 19:26:28.600934 DQ4 =112, DQ5 =122, DQ6 =124, DQ7 =112
3458 19:26:28.604516 DQ8 =94, DQ9 =98, DQ10 =106, DQ11 =102
3459 19:26:28.607705 DQ12 =114, DQ13 =114, DQ14 =114, DQ15 =114
3460 19:26:28.608230
3461 19:26:28.608569
3462 19:26:28.614349 [DQSOSCAuto] RK0, (LSB)MR18= 0xedf4, (MSB)MR19= 0x303, tDQSOscB0 = 415 ps tDQSOscB1 = 417 ps
3463 19:26:28.617638 CH1 RK0: MR19=303, MR18=EDF4
3464 19:26:28.624403 CH1_RK0: MR19=0x303, MR18=0xEDF4, DQSOSC=415, MR23=63, INC=38, DEC=25
3465 19:26:28.624935
3466 19:26:28.627985 ----->DramcWriteLeveling(PI) begin...
3467 19:26:28.628513 ==
3468 19:26:28.630500 Dram Type= 6, Freq= 0, CH_1, rank 1
3469 19:26:28.634038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3470 19:26:28.637141 ==
3471 19:26:28.637719 Write leveling (Byte 0): 23 => 23
3472 19:26:28.640949 Write leveling (Byte 1): 28 => 28
3473 19:26:28.643661 DramcWriteLeveling(PI) end<-----
3474 19:26:28.644086
3475 19:26:28.644418 ==
3476 19:26:28.647579 Dram Type= 6, Freq= 0, CH_1, rank 1
3477 19:26:28.654015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3478 19:26:28.654540 ==
3479 19:26:28.654932 [Gating] SW mode calibration
3480 19:26:28.663951 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3481 19:26:28.667207 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3482 19:26:28.673998 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3483 19:26:28.677024 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3484 19:26:28.680515 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3485 19:26:28.687243 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3486 19:26:28.690188 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3487 19:26:28.693637 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3488 19:26:28.697273 0 15 24 | B1->B0 | 3434 2626 | 1 0 | (1 0) (1 0)
3489 19:26:28.703487 0 15 28 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
3490 19:26:28.707290 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3491 19:26:28.710406 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3492 19:26:28.716932 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3493 19:26:28.720645 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3494 19:26:28.723933 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3495 19:26:28.730776 1 0 20 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
3496 19:26:28.733417 1 0 24 | B1->B0 | 2c2c 4646 | 1 0 | (0 0) (0 0)
3497 19:26:28.736835 1 0 28 | B1->B0 | 403f 4646 | 1 0 | (1 1) (0 0)
3498 19:26:28.743345 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3499 19:26:28.747040 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3500 19:26:28.750571 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3501 19:26:28.757346 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3502 19:26:28.760437 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3503 19:26:28.763578 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3504 19:26:28.770015 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3505 19:26:28.773615 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3506 19:26:28.776652 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3507 19:26:28.784021 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3508 19:26:28.786763 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3509 19:26:28.789971 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3510 19:26:28.796727 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3511 19:26:28.800392 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3512 19:26:28.803136 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3513 19:26:28.806831 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3514 19:26:28.813328 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3515 19:26:28.816561 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3516 19:26:28.819989 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 19:26:28.827052 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 19:26:28.829959 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3519 19:26:28.833460 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3520 19:26:28.839939 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3521 19:26:28.843368 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3522 19:26:28.846831 Total UI for P1: 0, mck2ui 16
3523 19:26:28.850224 best dqsien dly found for B0: ( 1, 3, 22)
3524 19:26:28.853388 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3525 19:26:28.857000 Total UI for P1: 0, mck2ui 16
3526 19:26:28.860054 best dqsien dly found for B1: ( 1, 3, 28)
3527 19:26:28.863320 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3528 19:26:28.866070 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3529 19:26:28.869856
3530 19:26:28.873428 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3531 19:26:28.876899 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3532 19:26:28.879804 [Gating] SW calibration Done
3533 19:26:28.880231 ==
3534 19:26:28.882967 Dram Type= 6, Freq= 0, CH_1, rank 1
3535 19:26:28.886308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3536 19:26:28.886738 ==
3537 19:26:28.887075 RX Vref Scan: 0
3538 19:26:28.887387
3539 19:26:28.889725 RX Vref 0 -> 0, step: 1
3540 19:26:28.890357
3541 19:26:28.892673 RX Delay -40 -> 252, step: 8
3542 19:26:28.896249 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3543 19:26:28.899557 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3544 19:26:28.906541 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3545 19:26:28.909351 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3546 19:26:28.912966 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3547 19:26:28.916288 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3548 19:26:28.919593 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3549 19:26:28.926134 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3550 19:26:28.929684 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3551 19:26:28.933167 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3552 19:26:28.936014 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3553 19:26:28.939761 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3554 19:26:28.946112 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3555 19:26:28.949845 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3556 19:26:28.952409 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3557 19:26:28.955850 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
3558 19:26:28.956276 ==
3559 19:26:28.959103 Dram Type= 6, Freq= 0, CH_1, rank 1
3560 19:26:28.966084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3561 19:26:28.966598 ==
3562 19:26:28.966934 DQS Delay:
3563 19:26:28.969016 DQS0 = 0, DQS1 = 0
3564 19:26:28.969590 DQM Delay:
3565 19:26:28.969942 DQM0 = 110, DQM1 = 109
3566 19:26:28.972411 DQ Delay:
3567 19:26:28.975478 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =107
3568 19:26:28.978952 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =111
3569 19:26:28.982390 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3570 19:26:28.985861 DQ12 =119, DQ13 =119, DQ14 =111, DQ15 =115
3571 19:26:28.986374
3572 19:26:28.986710
3573 19:26:28.987022 ==
3574 19:26:28.988963 Dram Type= 6, Freq= 0, CH_1, rank 1
3575 19:26:28.991945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3576 19:26:28.995638 ==
3577 19:26:28.996147
3578 19:26:28.996481
3579 19:26:28.996792 TX Vref Scan disable
3580 19:26:28.999273 == TX Byte 0 ==
3581 19:26:29.002044 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3582 19:26:29.005654 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3583 19:26:29.008666 == TX Byte 1 ==
3584 19:26:29.011994 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3585 19:26:29.015443 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3586 19:26:29.018632 ==
3587 19:26:29.019145 Dram Type= 6, Freq= 0, CH_1, rank 1
3588 19:26:29.025315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3589 19:26:29.025874 ==
3590 19:26:29.036604 TX Vref=22, minBit 11, minWin=25, winSum=421
3591 19:26:29.039911 TX Vref=24, minBit 0, minWin=25, winSum=425
3592 19:26:29.042861 TX Vref=26, minBit 0, minWin=26, winSum=427
3593 19:26:29.046467 TX Vref=28, minBit 1, minWin=26, winSum=433
3594 19:26:29.049816 TX Vref=30, minBit 8, minWin=25, winSum=434
3595 19:26:29.056724 TX Vref=32, minBit 8, minWin=25, winSum=432
3596 19:26:29.059746 [TxChooseVref] Worse bit 1, Min win 26, Win sum 433, Final Vref 28
3597 19:26:29.060314
3598 19:26:29.062823 Final TX Range 1 Vref 28
3599 19:26:29.063249
3600 19:26:29.063585 ==
3601 19:26:29.066037 Dram Type= 6, Freq= 0, CH_1, rank 1
3602 19:26:29.069447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3603 19:26:29.072711 ==
3604 19:26:29.073222
3605 19:26:29.073599
3606 19:26:29.073920 TX Vref Scan disable
3607 19:26:29.076345 == TX Byte 0 ==
3608 19:26:29.079472 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3609 19:26:29.086308 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3610 19:26:29.086817 == TX Byte 1 ==
3611 19:26:29.089950 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3612 19:26:29.096301 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3613 19:26:29.096876
3614 19:26:29.097372 [DATLAT]
3615 19:26:29.097838 Freq=1200, CH1 RK1
3616 19:26:29.098183
3617 19:26:29.099217 DATLAT Default: 0xd
3618 19:26:29.102851 0, 0xFFFF, sum = 0
3619 19:26:29.103467 1, 0xFFFF, sum = 0
3620 19:26:29.105983 2, 0xFFFF, sum = 0
3621 19:26:29.106487 3, 0xFFFF, sum = 0
3622 19:26:29.108936 4, 0xFFFF, sum = 0
3623 19:26:29.109438 5, 0xFFFF, sum = 0
3624 19:26:29.112363 6, 0xFFFF, sum = 0
3625 19:26:29.112842 7, 0xFFFF, sum = 0
3626 19:26:29.116003 8, 0xFFFF, sum = 0
3627 19:26:29.116500 9, 0xFFFF, sum = 0
3628 19:26:29.118966 10, 0xFFFF, sum = 0
3629 19:26:29.119418 11, 0xFFFF, sum = 0
3630 19:26:29.122331 12, 0x0, sum = 1
3631 19:26:29.122779 13, 0x0, sum = 2
3632 19:26:29.126145 14, 0x0, sum = 3
3633 19:26:29.126573 15, 0x0, sum = 4
3634 19:26:29.129394 best_step = 13
3635 19:26:29.130026
3636 19:26:29.130423 ==
3637 19:26:29.132212 Dram Type= 6, Freq= 0, CH_1, rank 1
3638 19:26:29.135746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3639 19:26:29.136310 ==
3640 19:26:29.139068 RX Vref Scan: 0
3641 19:26:29.139555
3642 19:26:29.139980 RX Vref 0 -> 0, step: 1
3643 19:26:29.140312
3644 19:26:29.142255 RX Delay -21 -> 252, step: 4
3645 19:26:29.149009 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3646 19:26:29.151803 iDelay=195, Bit 1, Center 108 (39 ~ 178) 140
3647 19:26:29.155464 iDelay=195, Bit 2, Center 100 (31 ~ 170) 140
3648 19:26:29.158787 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3649 19:26:29.162115 iDelay=195, Bit 4, Center 108 (39 ~ 178) 140
3650 19:26:29.168603 iDelay=195, Bit 5, Center 122 (51 ~ 194) 144
3651 19:26:29.171927 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3652 19:26:29.175119 iDelay=195, Bit 7, Center 108 (39 ~ 178) 140
3653 19:26:29.178118 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3654 19:26:29.181931 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3655 19:26:29.188173 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3656 19:26:29.191548 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3657 19:26:29.194958 iDelay=195, Bit 12, Center 120 (59 ~ 182) 124
3658 19:26:29.198462 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3659 19:26:29.204502 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3660 19:26:29.208435 iDelay=195, Bit 15, Center 118 (51 ~ 186) 136
3661 19:26:29.208861 ==
3662 19:26:29.211766 Dram Type= 6, Freq= 0, CH_1, rank 1
3663 19:26:29.214909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3664 19:26:29.215351 ==
3665 19:26:29.218020 DQS Delay:
3666 19:26:29.218443 DQS0 = 0, DQS1 = 0
3667 19:26:29.218774 DQM Delay:
3668 19:26:29.221303 DQM0 = 111, DQM1 = 110
3669 19:26:29.221824 DQ Delay:
3670 19:26:29.224697 DQ0 =114, DQ1 =108, DQ2 =100, DQ3 =108
3671 19:26:29.227917 DQ4 =108, DQ5 =122, DQ6 =122, DQ7 =108
3672 19:26:29.230834 DQ8 =98, DQ9 =102, DQ10 =112, DQ11 =104
3673 19:26:29.238287 DQ12 =120, DQ13 =116, DQ14 =116, DQ15 =118
3674 19:26:29.238812
3675 19:26:29.239144
3676 19:26:29.244919 [DQSOSCAuto] RK1, (LSB)MR18= 0xfb0b, (MSB)MR19= 0x304, tDQSOscB0 = 405 ps tDQSOscB1 = 412 ps
3677 19:26:29.248142 CH1 RK1: MR19=304, MR18=FB0B
3678 19:26:29.254476 CH1_RK1: MR19=0x304, MR18=0xFB0B, DQSOSC=405, MR23=63, INC=39, DEC=26
3679 19:26:29.258136 [RxdqsGatingPostProcess] freq 1200
3680 19:26:29.260910 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3681 19:26:29.264250 best DQS0 dly(2T, 0.5T) = (0, 11)
3682 19:26:29.267336 best DQS1 dly(2T, 0.5T) = (0, 11)
3683 19:26:29.270899 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3684 19:26:29.274183 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3685 19:26:29.277554 best DQS0 dly(2T, 0.5T) = (0, 11)
3686 19:26:29.280740 best DQS1 dly(2T, 0.5T) = (0, 11)
3687 19:26:29.283986 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3688 19:26:29.287287 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3689 19:26:29.290486 Pre-setting of DQS Precalculation
3690 19:26:29.293908 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3691 19:26:29.304027 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3692 19:26:29.310493 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3693 19:26:29.311071
3694 19:26:29.311570
3695 19:26:29.314050 [Calibration Summary] 2400 Mbps
3696 19:26:29.314473 CH 0, Rank 0
3697 19:26:29.317060 SW Impedance : PASS
3698 19:26:29.317799 DUTY Scan : NO K
3699 19:26:29.320692 ZQ Calibration : PASS
3700 19:26:29.323924 Jitter Meter : NO K
3701 19:26:29.324345 CBT Training : PASS
3702 19:26:29.326874 Write leveling : PASS
3703 19:26:29.330258 RX DQS gating : PASS
3704 19:26:29.330742 RX DQ/DQS(RDDQC) : PASS
3705 19:26:29.333580 TX DQ/DQS : PASS
3706 19:26:29.337189 RX DATLAT : PASS
3707 19:26:29.337744 RX DQ/DQS(Engine): PASS
3708 19:26:29.340938 TX OE : NO K
3709 19:26:29.341455 All Pass.
3710 19:26:29.341845
3711 19:26:29.343706 CH 0, Rank 1
3712 19:26:29.344129 SW Impedance : PASS
3713 19:26:29.347253 DUTY Scan : NO K
3714 19:26:29.350245 ZQ Calibration : PASS
3715 19:26:29.350672 Jitter Meter : NO K
3716 19:26:29.353571 CBT Training : PASS
3717 19:26:29.357036 Write leveling : PASS
3718 19:26:29.357592 RX DQS gating : PASS
3719 19:26:29.360300 RX DQ/DQS(RDDQC) : PASS
3720 19:26:29.363886 TX DQ/DQS : PASS
3721 19:26:29.364340 RX DATLAT : PASS
3722 19:26:29.366866 RX DQ/DQS(Engine): PASS
3723 19:26:29.367287 TX OE : NO K
3724 19:26:29.370396 All Pass.
3725 19:26:29.370856
3726 19:26:29.371197 CH 1, Rank 0
3727 19:26:29.373389 SW Impedance : PASS
3728 19:26:29.373845 DUTY Scan : NO K
3729 19:26:29.376915 ZQ Calibration : PASS
3730 19:26:29.379896 Jitter Meter : NO K
3731 19:26:29.380332 CBT Training : PASS
3732 19:26:29.383487 Write leveling : PASS
3733 19:26:29.386410 RX DQS gating : PASS
3734 19:26:29.386864 RX DQ/DQS(RDDQC) : PASS
3735 19:26:29.390099 TX DQ/DQS : PASS
3736 19:26:29.393397 RX DATLAT : PASS
3737 19:26:29.393868 RX DQ/DQS(Engine): PASS
3738 19:26:29.396421 TX OE : NO K
3739 19:26:29.396846 All Pass.
3740 19:26:29.397176
3741 19:26:29.400083 CH 1, Rank 1
3742 19:26:29.400595 SW Impedance : PASS
3743 19:26:29.402874 DUTY Scan : NO K
3744 19:26:29.406361 ZQ Calibration : PASS
3745 19:26:29.406787 Jitter Meter : NO K
3746 19:26:29.409628 CBT Training : PASS
3747 19:26:29.412966 Write leveling : PASS
3748 19:26:29.413389 RX DQS gating : PASS
3749 19:26:29.416812 RX DQ/DQS(RDDQC) : PASS
3750 19:26:29.420096 TX DQ/DQS : PASS
3751 19:26:29.420620 RX DATLAT : PASS
3752 19:26:29.423481 RX DQ/DQS(Engine): PASS
3753 19:26:29.423997 TX OE : NO K
3754 19:26:29.426397 All Pass.
3755 19:26:29.426914
3756 19:26:29.427254 DramC Write-DBI off
3757 19:26:29.429908 PER_BANK_REFRESH: Hybrid Mode
3758 19:26:29.433568 TX_TRACKING: ON
3759 19:26:29.439895 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3760 19:26:29.443205 [FAST_K] Save calibration result to emmc
3761 19:26:29.449587 dramc_set_vcore_voltage set vcore to 650000
3762 19:26:29.450057 Read voltage for 600, 5
3763 19:26:29.453113 Vio18 = 0
3764 19:26:29.453571 Vcore = 650000
3765 19:26:29.453915 Vdram = 0
3766 19:26:29.454230 Vddq = 0
3767 19:26:29.456404 Vmddr = 0
3768 19:26:29.460162 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3769 19:26:29.466075 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3770 19:26:29.469706 MEM_TYPE=3, freq_sel=19
3771 19:26:29.470239 sv_algorithm_assistance_LP4_1600
3772 19:26:29.475994 ============ PULL DRAM RESETB DOWN ============
3773 19:26:29.479978 ========== PULL DRAM RESETB DOWN end =========
3774 19:26:29.482976 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3775 19:26:29.486327 ===================================
3776 19:26:29.489306 LPDDR4 DRAM CONFIGURATION
3777 19:26:29.492841 ===================================
3778 19:26:29.495990 EX_ROW_EN[0] = 0x0
3779 19:26:29.496436 EX_ROW_EN[1] = 0x0
3780 19:26:29.499497 LP4Y_EN = 0x0
3781 19:26:29.499943 WORK_FSP = 0x0
3782 19:26:29.502507 WL = 0x2
3783 19:26:29.502948 RL = 0x2
3784 19:26:29.505988 BL = 0x2
3785 19:26:29.506433 RPST = 0x0
3786 19:26:29.509106 RD_PRE = 0x0
3787 19:26:29.509586 WR_PRE = 0x1
3788 19:26:29.512624 WR_PST = 0x0
3789 19:26:29.513073 DBI_WR = 0x0
3790 19:26:29.516101 DBI_RD = 0x0
3791 19:26:29.516692 OTF = 0x1
3792 19:26:29.519542 ===================================
3793 19:26:29.522888 ===================================
3794 19:26:29.526173 ANA top config
3795 19:26:29.529498 ===================================
3796 19:26:29.532849 DLL_ASYNC_EN = 0
3797 19:26:29.533368 ALL_SLAVE_EN = 1
3798 19:26:29.536259 NEW_RANK_MODE = 1
3799 19:26:29.539185 DLL_IDLE_MODE = 1
3800 19:26:29.542544 LP45_APHY_COMB_EN = 1
3801 19:26:29.545591 TX_ODT_DIS = 1
3802 19:26:29.546021 NEW_8X_MODE = 1
3803 19:26:29.549315 ===================================
3804 19:26:29.552582 ===================================
3805 19:26:29.555634 data_rate = 1200
3806 19:26:29.559353 CKR = 1
3807 19:26:29.562622 DQ_P2S_RATIO = 8
3808 19:26:29.565500 ===================================
3809 19:26:29.569356 CA_P2S_RATIO = 8
3810 19:26:29.569944 DQ_CA_OPEN = 0
3811 19:26:29.572552 DQ_SEMI_OPEN = 0
3812 19:26:29.575871 CA_SEMI_OPEN = 0
3813 19:26:29.579185 CA_FULL_RATE = 0
3814 19:26:29.582163 DQ_CKDIV4_EN = 1
3815 19:26:29.586201 CA_CKDIV4_EN = 1
3816 19:26:29.586722 CA_PREDIV_EN = 0
3817 19:26:29.588996 PH8_DLY = 0
3818 19:26:29.592869 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3819 19:26:29.595433 DQ_AAMCK_DIV = 4
3820 19:26:29.598936 CA_AAMCK_DIV = 4
3821 19:26:29.602609 CA_ADMCK_DIV = 4
3822 19:26:29.603136 DQ_TRACK_CA_EN = 0
3823 19:26:29.605658 CA_PICK = 600
3824 19:26:29.608627 CA_MCKIO = 600
3825 19:26:29.612341 MCKIO_SEMI = 0
3826 19:26:29.615827 PLL_FREQ = 2288
3827 19:26:29.618877 DQ_UI_PI_RATIO = 32
3828 19:26:29.622071 CA_UI_PI_RATIO = 0
3829 19:26:29.625364 ===================================
3830 19:26:29.628540 ===================================
3831 19:26:29.628991 memory_type:LPDDR4
3832 19:26:29.631916 GP_NUM : 10
3833 19:26:29.635210 SRAM_EN : 1
3834 19:26:29.635632 MD32_EN : 0
3835 19:26:29.638736 ===================================
3836 19:26:29.641985 [ANA_INIT] >>>>>>>>>>>>>>
3837 19:26:29.645285 <<<<<< [CONFIGURE PHASE]: ANA_TX
3838 19:26:29.648554 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3839 19:26:29.652047 ===================================
3840 19:26:29.655340 data_rate = 1200,PCW = 0X5800
3841 19:26:29.658791 ===================================
3842 19:26:29.661621 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3843 19:26:29.665044 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3844 19:26:29.671790 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3845 19:26:29.675119 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3846 19:26:29.678331 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3847 19:26:29.685052 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3848 19:26:29.685544 [ANA_INIT] flow start
3849 19:26:29.688420 [ANA_INIT] PLL >>>>>>>>
3850 19:26:29.691813 [ANA_INIT] PLL <<<<<<<<
3851 19:26:29.692329 [ANA_INIT] MIDPI >>>>>>>>
3852 19:26:29.694590 [ANA_INIT] MIDPI <<<<<<<<
3853 19:26:29.698049 [ANA_INIT] DLL >>>>>>>>
3854 19:26:29.698467 [ANA_INIT] flow end
3855 19:26:29.701712 ============ LP4 DIFF to SE enter ============
3856 19:26:29.708568 ============ LP4 DIFF to SE exit ============
3857 19:26:29.709089 [ANA_INIT] <<<<<<<<<<<<<
3858 19:26:29.711439 [Flow] Enable top DCM control >>>>>
3859 19:26:29.714920 [Flow] Enable top DCM control <<<<<
3860 19:26:29.718208 Enable DLL master slave shuffle
3861 19:26:29.724796 ==============================================================
3862 19:26:29.725220 Gating Mode config
3863 19:26:29.731089 ==============================================================
3864 19:26:29.734438 Config description:
3865 19:26:29.744406 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3866 19:26:29.751471 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3867 19:26:29.754244 SELPH_MODE 0: By rank 1: By Phase
3868 19:26:29.761063 ==============================================================
3869 19:26:29.764484 GAT_TRACK_EN = 1
3870 19:26:29.768058 RX_GATING_MODE = 2
3871 19:26:29.768579 RX_GATING_TRACK_MODE = 2
3872 19:26:29.771026 SELPH_MODE = 1
3873 19:26:29.774518 PICG_EARLY_EN = 1
3874 19:26:29.777702 VALID_LAT_VALUE = 1
3875 19:26:29.784784 ==============================================================
3876 19:26:29.787889 Enter into Gating configuration >>>>
3877 19:26:29.791015 Exit from Gating configuration <<<<
3878 19:26:29.794042 Enter into DVFS_PRE_config >>>>>
3879 19:26:29.803881 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3880 19:26:29.807691 Exit from DVFS_PRE_config <<<<<
3881 19:26:29.810409 Enter into PICG configuration >>>>
3882 19:26:29.814045 Exit from PICG configuration <<<<
3883 19:26:29.817172 [RX_INPUT] configuration >>>>>
3884 19:26:29.820630 [RX_INPUT] configuration <<<<<
3885 19:26:29.824497 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3886 19:26:29.830764 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3887 19:26:29.837130 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3888 19:26:29.844242 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3889 19:26:29.847168 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3890 19:26:29.853838 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3891 19:26:29.857206 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3892 19:26:29.863652 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3893 19:26:29.866969 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3894 19:26:29.870452 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3895 19:26:29.873443 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3896 19:26:29.880330 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3897 19:26:29.883368 ===================================
3898 19:26:29.887309 LPDDR4 DRAM CONFIGURATION
3899 19:26:29.890087 ===================================
3900 19:26:29.890516 EX_ROW_EN[0] = 0x0
3901 19:26:29.893962 EX_ROW_EN[1] = 0x0
3902 19:26:29.894480 LP4Y_EN = 0x0
3903 19:26:29.896517 WORK_FSP = 0x0
3904 19:26:29.896937 WL = 0x2
3905 19:26:29.900059 RL = 0x2
3906 19:26:29.900482 BL = 0x2
3907 19:26:29.903839 RPST = 0x0
3908 19:26:29.904351 RD_PRE = 0x0
3909 19:26:29.906624 WR_PRE = 0x1
3910 19:26:29.907144 WR_PST = 0x0
3911 19:26:29.909862 DBI_WR = 0x0
3912 19:26:29.913391 DBI_RD = 0x0
3913 19:26:29.913990 OTF = 0x1
3914 19:26:29.917092 ===================================
3915 19:26:29.920395 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3916 19:26:29.923529 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3917 19:26:29.929927 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3918 19:26:29.933311 ===================================
3919 19:26:29.936644 LPDDR4 DRAM CONFIGURATION
3920 19:26:29.939575 ===================================
3921 19:26:29.940023 EX_ROW_EN[0] = 0x10
3922 19:26:29.943004 EX_ROW_EN[1] = 0x0
3923 19:26:29.943467 LP4Y_EN = 0x0
3924 19:26:29.946539 WORK_FSP = 0x0
3925 19:26:29.947006 WL = 0x2
3926 19:26:29.949614 RL = 0x2
3927 19:26:29.950038 BL = 0x2
3928 19:26:29.953216 RPST = 0x0
3929 19:26:29.953677 RD_PRE = 0x0
3930 19:26:29.956122 WR_PRE = 0x1
3931 19:26:29.956544 WR_PST = 0x0
3932 19:26:29.959690 DBI_WR = 0x0
3933 19:26:29.960112 DBI_RD = 0x0
3934 19:26:29.963143 OTF = 0x1
3935 19:26:29.966699 ===================================
3936 19:26:29.972976 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3937 19:26:29.976874 nWR fixed to 30
3938 19:26:29.979429 [ModeRegInit_LP4] CH0 RK0
3939 19:26:29.979951 [ModeRegInit_LP4] CH0 RK1
3940 19:26:29.982882 [ModeRegInit_LP4] CH1 RK0
3941 19:26:29.986627 [ModeRegInit_LP4] CH1 RK1
3942 19:26:29.987216 match AC timing 17
3943 19:26:29.993079 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3944 19:26:29.996267 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3945 19:26:29.999759 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3946 19:26:30.006017 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3947 19:26:30.009672 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3948 19:26:30.010230 ==
3949 19:26:30.012740 Dram Type= 6, Freq= 0, CH_0, rank 0
3950 19:26:30.016236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3951 19:26:30.016730 ==
3952 19:26:30.022637 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3953 19:26:30.029471 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3954 19:26:30.032451 [CA 0] Center 37 (7~67) winsize 61
3955 19:26:30.036235 [CA 1] Center 36 (6~67) winsize 62
3956 19:26:30.039027 [CA 2] Center 35 (5~65) winsize 61
3957 19:26:30.042300 [CA 3] Center 35 (5~65) winsize 61
3958 19:26:30.045970 [CA 4] Center 34 (4~65) winsize 62
3959 19:26:30.049124 [CA 5] Center 34 (3~65) winsize 63
3960 19:26:30.049694
3961 19:26:30.052376 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3962 19:26:30.053006
3963 19:26:30.055721 [CATrainingPosCal] consider 1 rank data
3964 19:26:30.059067 u2DelayCellTimex100 = 270/100 ps
3965 19:26:30.062004 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3966 19:26:30.065335 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
3967 19:26:30.068709 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3968 19:26:30.072355 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3969 19:26:30.079043 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3970 19:26:30.081844 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
3971 19:26:30.082366
3972 19:26:30.085614 CA PerBit enable=1, Macro0, CA PI delay=34
3973 19:26:30.086041
3974 19:26:30.088759 [CBTSetCACLKResult] CA Dly = 34
3975 19:26:30.089370 CS Dly: 6 (0~37)
3976 19:26:30.089848 ==
3977 19:26:30.092135 Dram Type= 6, Freq= 0, CH_0, rank 1
3978 19:26:30.095761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3979 19:26:30.098946 ==
3980 19:26:30.102319 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3981 19:26:30.109342 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3982 19:26:30.112354 [CA 0] Center 37 (7~67) winsize 61
3983 19:26:30.115707 [CA 1] Center 37 (7~67) winsize 61
3984 19:26:30.119170 [CA 2] Center 35 (5~65) winsize 61
3985 19:26:30.122239 [CA 3] Center 35 (5~65) winsize 61
3986 19:26:30.125295 [CA 4] Center 34 (3~65) winsize 63
3987 19:26:30.128887 [CA 5] Center 33 (3~64) winsize 62
3988 19:26:30.129408
3989 19:26:30.131941 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3990 19:26:30.132414
3991 19:26:30.135179 [CATrainingPosCal] consider 2 rank data
3992 19:26:30.138482 u2DelayCellTimex100 = 270/100 ps
3993 19:26:30.141913 CA0 delay=37 (7~67),Diff = 4 PI (38 cell)
3994 19:26:30.145344 CA1 delay=37 (7~67),Diff = 4 PI (38 cell)
3995 19:26:30.148580 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
3996 19:26:30.155462 CA3 delay=35 (5~65),Diff = 2 PI (19 cell)
3997 19:26:30.158405 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
3998 19:26:30.161973 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3999 19:26:30.162397
4000 19:26:30.165019 CA PerBit enable=1, Macro0, CA PI delay=33
4001 19:26:30.165445
4002 19:26:30.168592 [CBTSetCACLKResult] CA Dly = 33
4003 19:26:30.169038 CS Dly: 6 (0~37)
4004 19:26:30.169379
4005 19:26:30.171456 ----->DramcWriteLeveling(PI) begin...
4006 19:26:30.174756 ==
4007 19:26:30.178296 Dram Type= 6, Freq= 0, CH_0, rank 0
4008 19:26:30.181446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4009 19:26:30.181912 ==
4010 19:26:30.185283 Write leveling (Byte 0): 30 => 30
4011 19:26:30.188290 Write leveling (Byte 1): 30 => 30
4012 19:26:30.191952 DramcWriteLeveling(PI) end<-----
4013 19:26:30.192474
4014 19:26:30.192812 ==
4015 19:26:30.195461 Dram Type= 6, Freq= 0, CH_0, rank 0
4016 19:26:30.197847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4017 19:26:30.198282 ==
4018 19:26:30.201559 [Gating] SW mode calibration
4019 19:26:30.208280 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4020 19:26:30.214459 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4021 19:26:30.218080 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4022 19:26:30.221494 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4023 19:26:30.228464 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4024 19:26:30.231326 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4025 19:26:30.234685 0 9 16 | B1->B0 | 3030 2a2a | 1 0 | (0 0) (0 0)
4026 19:26:30.241394 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4027 19:26:30.244571 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4028 19:26:30.248040 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4029 19:26:30.251548 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4030 19:26:30.257719 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4031 19:26:30.261670 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4032 19:26:30.265122 0 10 12 | B1->B0 | 2525 2c2c | 0 0 | (0 0) (1 1)
4033 19:26:30.271787 0 10 16 | B1->B0 | 2b2b 4141 | 0 0 | (0 0) (0 0)
4034 19:26:30.274532 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4035 19:26:30.278261 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4036 19:26:30.284193 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4037 19:26:30.288236 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4038 19:26:30.290951 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4039 19:26:30.297388 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4040 19:26:30.301090 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4041 19:26:30.304620 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4042 19:26:30.310788 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4043 19:26:30.314069 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 19:26:30.317720 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 19:26:30.324248 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 19:26:30.327762 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 19:26:30.330932 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 19:26:30.337541 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 19:26:30.340548 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 19:26:30.344246 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 19:26:30.350578 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 19:26:30.353876 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 19:26:30.357077 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 19:26:30.363509 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 19:26:30.366655 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 19:26:30.370035 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 19:26:30.376686 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4058 19:26:30.377140 Total UI for P1: 0, mck2ui 16
4059 19:26:30.383663 best dqsien dly found for B0: ( 0, 13, 14)
4060 19:26:30.384089 Total UI for P1: 0, mck2ui 16
4061 19:26:30.389849 best dqsien dly found for B1: ( 0, 13, 14)
4062 19:26:30.393370 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4063 19:26:30.396945 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4064 19:26:30.397368
4065 19:26:30.399957 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4066 19:26:30.403780 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4067 19:26:30.406592 [Gating] SW calibration Done
4068 19:26:30.407019 ==
4069 19:26:30.410093 Dram Type= 6, Freq= 0, CH_0, rank 0
4070 19:26:30.412984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4071 19:26:30.413411 ==
4072 19:26:30.416879 RX Vref Scan: 0
4073 19:26:30.417395
4074 19:26:30.417788 RX Vref 0 -> 0, step: 1
4075 19:26:30.420019
4076 19:26:30.420441 RX Delay -230 -> 252, step: 16
4077 19:26:30.426670 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4078 19:26:30.429323 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4079 19:26:30.432932 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4080 19:26:30.436308 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4081 19:26:30.442993 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4082 19:26:30.446528 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4083 19:26:30.449434 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4084 19:26:30.452941 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4085 19:26:30.456004 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4086 19:26:30.462841 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4087 19:26:30.465839 iDelay=218, Bit 10, Center 25 (-150 ~ 201) 352
4088 19:26:30.469271 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4089 19:26:30.472562 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4090 19:26:30.480006 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4091 19:26:30.482956 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4092 19:26:30.486040 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4093 19:26:30.486464 ==
4094 19:26:30.489461 Dram Type= 6, Freq= 0, CH_0, rank 0
4095 19:26:30.492601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4096 19:26:30.496357 ==
4097 19:26:30.496879 DQS Delay:
4098 19:26:30.497214 DQS0 = 0, DQS1 = 0
4099 19:26:30.499118 DQM Delay:
4100 19:26:30.499573 DQM0 = 36, DQM1 = 27
4101 19:26:30.502232 DQ Delay:
4102 19:26:30.505956 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4103 19:26:30.508944 DQ4 =33, DQ5 =17, DQ6 =49, DQ7 =49
4104 19:26:30.512910 DQ8 =17, DQ9 =17, DQ10 =25, DQ11 =17
4105 19:26:30.515802 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4106 19:26:30.516321
4107 19:26:30.516653
4108 19:26:30.516961 ==
4109 19:26:30.519491 Dram Type= 6, Freq= 0, CH_0, rank 0
4110 19:26:30.522105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4111 19:26:30.522528 ==
4112 19:26:30.522858
4113 19:26:30.523164
4114 19:26:30.525554 TX Vref Scan disable
4115 19:26:30.525976 == TX Byte 0 ==
4116 19:26:30.532267 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4117 19:26:30.535868 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4118 19:26:30.536422 == TX Byte 1 ==
4119 19:26:30.542087 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4120 19:26:30.546012 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4121 19:26:30.546534 ==
4122 19:26:30.548579 Dram Type= 6, Freq= 0, CH_0, rank 0
4123 19:26:30.552276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4124 19:26:30.552698 ==
4125 19:26:30.553025
4126 19:26:30.553328
4127 19:26:30.555238 TX Vref Scan disable
4128 19:26:30.558920 == TX Byte 0 ==
4129 19:26:30.562175 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4130 19:26:30.569143 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4131 19:26:30.569706 == TX Byte 1 ==
4132 19:26:30.571995 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4133 19:26:30.578517 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4134 19:26:30.579033
4135 19:26:30.579363 [DATLAT]
4136 19:26:30.579670 Freq=600, CH0 RK0
4137 19:26:30.579964
4138 19:26:30.582049 DATLAT Default: 0x9
4139 19:26:30.582468 0, 0xFFFF, sum = 0
4140 19:26:30.585055 1, 0xFFFF, sum = 0
4141 19:26:30.585593 2, 0xFFFF, sum = 0
4142 19:26:30.588783 3, 0xFFFF, sum = 0
4143 19:26:30.592233 4, 0xFFFF, sum = 0
4144 19:26:30.592803 5, 0xFFFF, sum = 0
4145 19:26:30.595215 6, 0xFFFF, sum = 0
4146 19:26:30.595644 7, 0xFFFF, sum = 0
4147 19:26:30.598252 8, 0x0, sum = 1
4148 19:26:30.598677 9, 0x0, sum = 2
4149 19:26:30.599012 10, 0x0, sum = 3
4150 19:26:30.601317 11, 0x0, sum = 4
4151 19:26:30.601839 best_step = 9
4152 19:26:30.602176
4153 19:26:30.602486 ==
4154 19:26:30.605220 Dram Type= 6, Freq= 0, CH_0, rank 0
4155 19:26:30.611475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4156 19:26:30.611996 ==
4157 19:26:30.612329 RX Vref Scan: 1
4158 19:26:30.612637
4159 19:26:30.614784 RX Vref 0 -> 0, step: 1
4160 19:26:30.615204
4161 19:26:30.618030 RX Delay -195 -> 252, step: 8
4162 19:26:30.618448
4163 19:26:30.621053 Set Vref, RX VrefLevel [Byte0]: 60
4164 19:26:30.624598 [Byte1]: 54
4165 19:26:30.625129
4166 19:26:30.628319 Final RX Vref Byte 0 = 60 to rank0
4167 19:26:30.631243 Final RX Vref Byte 1 = 54 to rank0
4168 19:26:30.634729 Final RX Vref Byte 0 = 60 to rank1
4169 19:26:30.638331 Final RX Vref Byte 1 = 54 to rank1==
4170 19:26:30.641248 Dram Type= 6, Freq= 0, CH_0, rank 0
4171 19:26:30.645181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4172 19:26:30.645756 ==
4173 19:26:30.647898 DQS Delay:
4174 19:26:30.648315 DQS0 = 0, DQS1 = 0
4175 19:26:30.651255 DQM Delay:
4176 19:26:30.651676 DQM0 = 34, DQM1 = 29
4177 19:26:30.652007 DQ Delay:
4178 19:26:30.654589 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =32
4179 19:26:30.657760 DQ4 =32, DQ5 =24, DQ6 =40, DQ7 =48
4180 19:26:30.660707 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4181 19:26:30.664751 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =36
4182 19:26:30.665326
4183 19:26:30.667709
4184 19:26:30.674224 [DQSOSCAuto] RK0, (LSB)MR18= 0x4241, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
4185 19:26:30.677614 CH0 RK0: MR19=808, MR18=4241
4186 19:26:30.684480 CH0_RK0: MR19=0x808, MR18=0x4241, DQSOSC=397, MR23=63, INC=166, DEC=110
4187 19:26:30.685003
4188 19:26:30.688159 ----->DramcWriteLeveling(PI) begin...
4189 19:26:30.688684 ==
4190 19:26:30.690679 Dram Type= 6, Freq= 0, CH_0, rank 1
4191 19:26:30.694442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4192 19:26:30.694968 ==
4193 19:26:30.697662 Write leveling (Byte 0): 30 => 30
4194 19:26:30.700911 Write leveling (Byte 1): 30 => 30
4195 19:26:30.704196 DramcWriteLeveling(PI) end<-----
4196 19:26:30.704714
4197 19:26:30.705048 ==
4198 19:26:30.707620 Dram Type= 6, Freq= 0, CH_0, rank 1
4199 19:26:30.710804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4200 19:26:30.711354 ==
4201 19:26:30.714161 [Gating] SW mode calibration
4202 19:26:30.721188 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4203 19:26:30.727324 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4204 19:26:30.730550 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4205 19:26:30.733675 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4206 19:26:30.740736 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4207 19:26:30.743725 0 9 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
4208 19:26:30.747084 0 9 16 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
4209 19:26:30.753781 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4210 19:26:30.757225 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4211 19:26:30.760294 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4212 19:26:30.767379 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4213 19:26:30.770399 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4214 19:26:30.773990 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4215 19:26:30.780280 0 10 12 | B1->B0 | 2424 3636 | 0 0 | (0 0) (0 0)
4216 19:26:30.783842 0 10 16 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
4217 19:26:30.787254 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4218 19:26:30.793570 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4219 19:26:30.796986 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4220 19:26:30.799898 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4221 19:26:30.806609 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4222 19:26:30.809963 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4223 19:26:30.813493 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4224 19:26:30.820460 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4225 19:26:30.823436 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4226 19:26:30.826501 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4227 19:26:30.833303 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4228 19:26:30.836829 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4229 19:26:30.840222 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4230 19:26:30.846592 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 19:26:30.849684 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4232 19:26:30.853374 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4233 19:26:30.860153 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4234 19:26:30.863125 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 19:26:30.866437 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 19:26:30.873216 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 19:26:30.876523 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 19:26:30.879995 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 19:26:30.882993 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4240 19:26:30.889885 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4241 19:26:30.892768 Total UI for P1: 0, mck2ui 16
4242 19:26:30.896326 best dqsien dly found for B0: ( 0, 13, 12)
4243 19:26:30.900021 Total UI for P1: 0, mck2ui 16
4244 19:26:30.903128 best dqsien dly found for B1: ( 0, 13, 14)
4245 19:26:30.906433 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4246 19:26:30.909891 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4247 19:26:30.910314
4248 19:26:30.912885 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4249 19:26:30.916316 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4250 19:26:30.919854 [Gating] SW calibration Done
4251 19:26:30.920278 ==
4252 19:26:30.922881 Dram Type= 6, Freq= 0, CH_0, rank 1
4253 19:26:30.926574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4254 19:26:30.926993 ==
4255 19:26:30.929501 RX Vref Scan: 0
4256 19:26:30.929943
4257 19:26:30.932945 RX Vref 0 -> 0, step: 1
4258 19:26:30.933319
4259 19:26:30.933674 RX Delay -230 -> 252, step: 16
4260 19:26:30.939447 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4261 19:26:30.943101 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4262 19:26:30.946151 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4263 19:26:30.949550 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4264 19:26:30.956060 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4265 19:26:30.959526 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4266 19:26:30.962416 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4267 19:26:30.965981 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4268 19:26:30.972449 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4269 19:26:30.975723 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4270 19:26:30.979452 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4271 19:26:30.982589 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4272 19:26:30.985572 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4273 19:26:30.992515 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4274 19:26:30.995743 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4275 19:26:30.999138 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4276 19:26:30.999557 ==
4277 19:26:31.002471 Dram Type= 6, Freq= 0, CH_0, rank 1
4278 19:26:31.008803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4279 19:26:31.009223 ==
4280 19:26:31.009589 DQS Delay:
4281 19:26:31.012205 DQS0 = 0, DQS1 = 0
4282 19:26:31.012709 DQM Delay:
4283 19:26:31.013201 DQM0 = 40, DQM1 = 31
4284 19:26:31.015392 DQ Delay:
4285 19:26:31.018932 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =33
4286 19:26:31.022293 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4287 19:26:31.025383 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4288 19:26:31.028994 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =41
4289 19:26:31.029408
4290 19:26:31.029782
4291 19:26:31.030090 ==
4292 19:26:31.032456 Dram Type= 6, Freq= 0, CH_0, rank 1
4293 19:26:31.035583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4294 19:26:31.036105 ==
4295 19:26:31.036442
4296 19:26:31.036746
4297 19:26:31.038796 TX Vref Scan disable
4298 19:26:31.039212 == TX Byte 0 ==
4299 19:26:31.045998 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4300 19:26:31.049029 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4301 19:26:31.049445 == TX Byte 1 ==
4302 19:26:31.055687 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4303 19:26:31.059105 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4304 19:26:31.059678 ==
4305 19:26:31.061970 Dram Type= 6, Freq= 0, CH_0, rank 1
4306 19:26:31.065440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4307 19:26:31.066109 ==
4308 19:26:31.066530
4309 19:26:31.066941
4310 19:26:31.069134 TX Vref Scan disable
4311 19:26:31.072156 == TX Byte 0 ==
4312 19:26:31.076098 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4313 19:26:31.078828 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4314 19:26:31.082293 == TX Byte 1 ==
4315 19:26:31.085239 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4316 19:26:31.088793 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4317 19:26:31.092148
4318 19:26:31.092706 [DATLAT]
4319 19:26:31.093143 Freq=600, CH0 RK1
4320 19:26:31.093698
4321 19:26:31.095443 DATLAT Default: 0x9
4322 19:26:31.095913 0, 0xFFFF, sum = 0
4323 19:26:31.098636 1, 0xFFFF, sum = 0
4324 19:26:31.099243 2, 0xFFFF, sum = 0
4325 19:26:31.101806 3, 0xFFFF, sum = 0
4326 19:26:31.102365 4, 0xFFFF, sum = 0
4327 19:26:31.105438 5, 0xFFFF, sum = 0
4328 19:26:31.108246 6, 0xFFFF, sum = 0
4329 19:26:31.108667 7, 0xFFFF, sum = 0
4330 19:26:31.109009 8, 0x0, sum = 1
4331 19:26:31.111752 9, 0x0, sum = 2
4332 19:26:31.111973 10, 0x0, sum = 3
4333 19:26:31.114841 11, 0x0, sum = 4
4334 19:26:31.115138 best_step = 9
4335 19:26:31.115399
4336 19:26:31.115637 ==
4337 19:26:31.118256 Dram Type= 6, Freq= 0, CH_0, rank 1
4338 19:26:31.125032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4339 19:26:31.125182 ==
4340 19:26:31.125298 RX Vref Scan: 0
4341 19:26:31.125408
4342 19:26:31.128049 RX Vref 0 -> 0, step: 1
4343 19:26:31.128198
4344 19:26:31.131669 RX Delay -195 -> 252, step: 8
4345 19:26:31.135031 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4346 19:26:31.141503 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4347 19:26:31.145158 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4348 19:26:31.148069 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4349 19:26:31.151683 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4350 19:26:31.158438 iDelay=205, Bit 5, Center 20 (-139 ~ 180) 320
4351 19:26:31.161811 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4352 19:26:31.165061 iDelay=205, Bit 7, Center 40 (-115 ~ 196) 312
4353 19:26:31.168582 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4354 19:26:31.171791 iDelay=205, Bit 9, Center 12 (-147 ~ 172) 320
4355 19:26:31.178182 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4356 19:26:31.181873 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4357 19:26:31.184904 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4358 19:26:31.188365 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4359 19:26:31.194931 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4360 19:26:31.198115 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4361 19:26:31.198529 ==
4362 19:26:31.201657 Dram Type= 6, Freq= 0, CH_0, rank 1
4363 19:26:31.204355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4364 19:26:31.204776 ==
4365 19:26:31.208041 DQS Delay:
4366 19:26:31.208453 DQS0 = 0, DQS1 = 0
4367 19:26:31.211543 DQM Delay:
4368 19:26:31.211979 DQM0 = 33, DQM1 = 28
4369 19:26:31.212303 DQ Delay:
4370 19:26:31.214742 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4371 19:26:31.218080 DQ4 =32, DQ5 =20, DQ6 =44, DQ7 =40
4372 19:26:31.220979 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4373 19:26:31.224459 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4374 19:26:31.224870
4375 19:26:31.225193
4376 19:26:31.234512 [DQSOSCAuto] RK1, (LSB)MR18= 0x6d3c, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 389 ps
4377 19:26:31.237900 CH0 RK1: MR19=808, MR18=6D3C
4378 19:26:31.241229 CH0_RK1: MR19=0x808, MR18=0x6D3C, DQSOSC=389, MR23=63, INC=173, DEC=115
4379 19:26:31.244444 [RxdqsGatingPostProcess] freq 600
4380 19:26:31.251166 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4381 19:26:31.254499 Pre-setting of DQS Precalculation
4382 19:26:31.257586 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4383 19:26:31.257999 ==
4384 19:26:31.261422 Dram Type= 6, Freq= 0, CH_1, rank 0
4385 19:26:31.268203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4386 19:26:31.268749 ==
4387 19:26:31.270771 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4388 19:26:31.277915 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4389 19:26:31.281561 [CA 0] Center 35 (5~66) winsize 62
4390 19:26:31.284409 [CA 1] Center 35 (5~66) winsize 62
4391 19:26:31.287977 [CA 2] Center 34 (4~65) winsize 62
4392 19:26:31.290793 [CA 3] Center 34 (4~65) winsize 62
4393 19:26:31.294264 [CA 4] Center 34 (4~65) winsize 62
4394 19:26:31.297614 [CA 5] Center 33 (3~64) winsize 62
4395 19:26:31.298150
4396 19:26:31.301077 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4397 19:26:31.301494
4398 19:26:31.303953 [CATrainingPosCal] consider 1 rank data
4399 19:26:31.307532 u2DelayCellTimex100 = 270/100 ps
4400 19:26:31.310948 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4401 19:26:31.316963 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4402 19:26:31.320493 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4403 19:26:31.323671 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4404 19:26:31.327398 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4405 19:26:31.330465 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4406 19:26:31.330837
4407 19:26:31.333780 CA PerBit enable=1, Macro0, CA PI delay=33
4408 19:26:31.334212
4409 19:26:31.337363 [CBTSetCACLKResult] CA Dly = 33
4410 19:26:31.340314 CS Dly: 5 (0~36)
4411 19:26:31.340682 ==
4412 19:26:31.343831 Dram Type= 6, Freq= 0, CH_1, rank 1
4413 19:26:31.346845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4414 19:26:31.347264 ==
4415 19:26:31.353338 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4416 19:26:31.356885 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4417 19:26:31.361068 [CA 0] Center 36 (6~66) winsize 61
4418 19:26:31.364770 [CA 1] Center 36 (5~67) winsize 63
4419 19:26:31.367593 [CA 2] Center 34 (3~65) winsize 63
4420 19:26:31.370876 [CA 3] Center 34 (3~65) winsize 63
4421 19:26:31.374434 [CA 4] Center 34 (4~65) winsize 62
4422 19:26:31.377619 [CA 5] Center 33 (3~64) winsize 62
4423 19:26:31.378064
4424 19:26:31.381183 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4425 19:26:31.381707
4426 19:26:31.384420 [CATrainingPosCal] consider 2 rank data
4427 19:26:31.387976 u2DelayCellTimex100 = 270/100 ps
4428 19:26:31.391041 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4429 19:26:31.394692 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4430 19:26:31.401286 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4431 19:26:31.404100 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4432 19:26:31.407997 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4433 19:26:31.410895 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4434 19:26:31.411389
4435 19:26:31.414409 CA PerBit enable=1, Macro0, CA PI delay=33
4436 19:26:31.414829
4437 19:26:31.417924 [CBTSetCACLKResult] CA Dly = 33
4438 19:26:31.418377 CS Dly: 5 (0~37)
4439 19:26:31.418829
4440 19:26:31.420945 ----->DramcWriteLeveling(PI) begin...
4441 19:26:31.424490 ==
4442 19:26:31.427530 Dram Type= 6, Freq= 0, CH_1, rank 0
4443 19:26:31.431176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4444 19:26:31.431596 ==
4445 19:26:31.434114 Write leveling (Byte 0): 29 => 29
4446 19:26:31.437612 Write leveling (Byte 1): 29 => 29
4447 19:26:31.441182 DramcWriteLeveling(PI) end<-----
4448 19:26:31.441747
4449 19:26:31.442149 ==
4450 19:26:31.444386 Dram Type= 6, Freq= 0, CH_1, rank 0
4451 19:26:31.447375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4452 19:26:31.447910 ==
4453 19:26:31.451006 [Gating] SW mode calibration
4454 19:26:31.457445 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4455 19:26:31.463925 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4456 19:26:31.467619 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4457 19:26:31.470631 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4458 19:26:31.477104 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4459 19:26:31.480746 0 9 12 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 1)
4460 19:26:31.483832 0 9 16 | B1->B0 | 2727 2525 | 0 0 | (0 0) (1 1)
4461 19:26:31.487287 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4462 19:26:31.493618 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4463 19:26:31.497354 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4464 19:26:31.500114 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4465 19:26:31.506865 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4466 19:26:31.510469 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4467 19:26:31.514022 0 10 12 | B1->B0 | 3030 3131 | 0 0 | (0 0) (0 0)
4468 19:26:31.520095 0 10 16 | B1->B0 | 4141 4444 | 0 0 | (0 0) (0 0)
4469 19:26:31.523681 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4470 19:26:31.526945 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4471 19:26:31.533536 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4472 19:26:31.536600 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4473 19:26:31.540341 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4474 19:26:31.547073 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4475 19:26:31.549992 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4476 19:26:31.553766 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4477 19:26:31.560033 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 19:26:31.563773 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 19:26:31.566660 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 19:26:31.573267 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 19:26:31.576231 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 19:26:31.579888 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 19:26:31.586461 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 19:26:31.590015 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 19:26:31.592934 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 19:26:31.599809 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 19:26:31.602632 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 19:26:31.606419 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 19:26:31.612723 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 19:26:31.616162 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 19:26:31.619593 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4492 19:26:31.626499 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4493 19:26:31.626707 Total UI for P1: 0, mck2ui 16
4494 19:26:31.632742 best dqsien dly found for B0: ( 0, 13, 12)
4495 19:26:31.633325 Total UI for P1: 0, mck2ui 16
4496 19:26:31.639387 best dqsien dly found for B1: ( 0, 13, 14)
4497 19:26:31.643045 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4498 19:26:31.646126 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4499 19:26:31.646670
4500 19:26:31.649796 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4501 19:26:31.652664 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4502 19:26:31.656172 [Gating] SW calibration Done
4503 19:26:31.656720 ==
4504 19:26:31.659814 Dram Type= 6, Freq= 0, CH_1, rank 0
4505 19:26:31.662615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4506 19:26:31.663086 ==
4507 19:26:31.665831 RX Vref Scan: 0
4508 19:26:31.666393
4509 19:26:31.666800 RX Vref 0 -> 0, step: 1
4510 19:26:31.667364
4511 19:26:31.669503 RX Delay -230 -> 252, step: 16
4512 19:26:31.675839 iDelay=218, Bit 0, Center 41 (-134 ~ 217) 352
4513 19:26:31.679337 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4514 19:26:31.682426 iDelay=218, Bit 2, Center 25 (-150 ~ 201) 352
4515 19:26:31.685986 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4516 19:26:31.689114 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4517 19:26:31.695701 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4518 19:26:31.699264 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4519 19:26:31.702256 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4520 19:26:31.705731 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4521 19:26:31.712188 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4522 19:26:31.715720 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4523 19:26:31.718760 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4524 19:26:31.721921 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4525 19:26:31.728513 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4526 19:26:31.731935 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4527 19:26:31.734950 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4528 19:26:31.735248 ==
4529 19:26:31.738408 Dram Type= 6, Freq= 0, CH_1, rank 0
4530 19:26:31.741910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4531 19:26:31.745102 ==
4532 19:26:31.745446 DQS Delay:
4533 19:26:31.745728 DQS0 = 0, DQS1 = 0
4534 19:26:31.748792 DQM Delay:
4535 19:26:31.749135 DQM0 = 37, DQM1 = 28
4536 19:26:31.751740 DQ Delay:
4537 19:26:31.752043 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =33
4538 19:26:31.755337 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4539 19:26:31.758263 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4540 19:26:31.761855 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4541 19:26:31.764973
4542 19:26:31.765431
4543 19:26:31.765882 ==
4544 19:26:31.768508 Dram Type= 6, Freq= 0, CH_1, rank 0
4545 19:26:31.771825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4546 19:26:31.772217 ==
4547 19:26:31.772463
4548 19:26:31.772681
4549 19:26:31.774783 TX Vref Scan disable
4550 19:26:31.775103 == TX Byte 0 ==
4551 19:26:31.781784 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4552 19:26:31.785056 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4553 19:26:31.785362 == TX Byte 1 ==
4554 19:26:31.791447 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4555 19:26:31.794890 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4556 19:26:31.795192 ==
4557 19:26:31.797998 Dram Type= 6, Freq= 0, CH_1, rank 0
4558 19:26:31.801500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4559 19:26:31.801832 ==
4560 19:26:31.802067
4561 19:26:31.802286
4562 19:26:31.805132 TX Vref Scan disable
4563 19:26:31.808046 == TX Byte 0 ==
4564 19:26:31.811373 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4565 19:26:31.814858 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4566 19:26:31.817909 == TX Byte 1 ==
4567 19:26:31.821506 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4568 19:26:31.824709 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4569 19:26:31.825004
4570 19:26:31.827920 [DATLAT]
4571 19:26:31.828365 Freq=600, CH1 RK0
4572 19:26:31.828612
4573 19:26:31.831744 DATLAT Default: 0x9
4574 19:26:31.832043 0, 0xFFFF, sum = 0
4575 19:26:31.834916 1, 0xFFFF, sum = 0
4576 19:26:31.835268 2, 0xFFFF, sum = 0
4577 19:26:31.837895 3, 0xFFFF, sum = 0
4578 19:26:31.838197 4, 0xFFFF, sum = 0
4579 19:26:31.841308 5, 0xFFFF, sum = 0
4580 19:26:31.841551 6, 0xFFFF, sum = 0
4581 19:26:31.844697 7, 0xFFFF, sum = 0
4582 19:26:31.844931 8, 0x0, sum = 1
4583 19:26:31.847856 9, 0x0, sum = 2
4584 19:26:31.848191 10, 0x0, sum = 3
4585 19:26:31.851452 11, 0x0, sum = 4
4586 19:26:31.851752 best_step = 9
4587 19:26:31.852042
4588 19:26:31.852293 ==
4589 19:26:31.854867 Dram Type= 6, Freq= 0, CH_1, rank 0
4590 19:26:31.861024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4591 19:26:31.861176 ==
4592 19:26:31.861294 RX Vref Scan: 1
4593 19:26:31.861403
4594 19:26:31.864600 RX Vref 0 -> 0, step: 1
4595 19:26:31.864751
4596 19:26:31.867708 RX Delay -195 -> 252, step: 8
4597 19:26:31.867875
4598 19:26:31.871314 Set Vref, RX VrefLevel [Byte0]: 55
4599 19:26:31.874506 [Byte1]: 54
4600 19:26:31.874635
4601 19:26:31.877980 Final RX Vref Byte 0 = 55 to rank0
4602 19:26:31.881695 Final RX Vref Byte 1 = 54 to rank0
4603 19:26:31.884568 Final RX Vref Byte 0 = 55 to rank1
4604 19:26:31.888178 Final RX Vref Byte 1 = 54 to rank1==
4605 19:26:31.891552 Dram Type= 6, Freq= 0, CH_1, rank 0
4606 19:26:31.894977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4607 19:26:31.895394 ==
4608 19:26:31.898069 DQS Delay:
4609 19:26:31.898365 DQS0 = 0, DQS1 = 0
4610 19:26:31.898599 DQM Delay:
4611 19:26:31.901033 DQM0 = 38, DQM1 = 28
4612 19:26:31.901338 DQ Delay:
4613 19:26:31.904447 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4614 19:26:31.907876 DQ4 =36, DQ5 =44, DQ6 =48, DQ7 =36
4615 19:26:31.911095 DQ8 =12, DQ9 =16, DQ10 =28, DQ11 =20
4616 19:26:31.914594 DQ12 =40, DQ13 =36, DQ14 =36, DQ15 =36
4617 19:26:31.914913
4618 19:26:31.915161
4619 19:26:31.924697 [DQSOSCAuto] RK0, (LSB)MR18= 0x212f, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 403 ps
4620 19:26:31.925024 CH1 RK0: MR19=808, MR18=212F
4621 19:26:31.931216 CH1_RK0: MR19=0x808, MR18=0x212F, DQSOSC=400, MR23=63, INC=163, DEC=109
4622 19:26:31.931557
4623 19:26:31.934137 ----->DramcWriteLeveling(PI) begin...
4624 19:26:31.937223 ==
4625 19:26:31.940792 Dram Type= 6, Freq= 0, CH_1, rank 1
4626 19:26:31.944266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4627 19:26:31.944572 ==
4628 19:26:31.947381 Write leveling (Byte 0): 29 => 29
4629 19:26:31.950884 Write leveling (Byte 1): 31 => 31
4630 19:26:31.953846 DramcWriteLeveling(PI) end<-----
4631 19:26:31.954257
4632 19:26:31.954513 ==
4633 19:26:31.956978 Dram Type= 6, Freq= 0, CH_1, rank 1
4634 19:26:31.960355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4635 19:26:31.960676 ==
4636 19:26:31.964097 [Gating] SW mode calibration
4637 19:26:31.970277 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4638 19:26:31.977327 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4639 19:26:31.980213 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4640 19:26:31.983902 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4641 19:26:31.990437 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4642 19:26:31.993493 0 9 12 | B1->B0 | 3232 2c2c | 1 0 | (1 0) (0 0)
4643 19:26:31.997112 0 9 16 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
4644 19:26:32.003606 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4645 19:26:32.006684 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4646 19:26:32.010013 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4647 19:26:32.016603 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4648 19:26:32.020215 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4649 19:26:32.023624 0 10 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
4650 19:26:32.029563 0 10 12 | B1->B0 | 3131 3a3a | 0 1 | (0 0) (0 0)
4651 19:26:32.033249 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4652 19:26:32.036215 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4653 19:26:32.042734 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4654 19:26:32.046311 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4655 19:26:32.049413 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4656 19:26:32.056085 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4657 19:26:32.059551 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4658 19:26:32.063213 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4659 19:26:32.069331 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4660 19:26:32.073082 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4661 19:26:32.076119 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4662 19:26:32.082827 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4663 19:26:32.086588 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4664 19:26:32.089284 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 19:26:32.096311 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4666 19:26:32.099476 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4667 19:26:32.102450 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4668 19:26:32.109283 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4669 19:26:32.112464 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4670 19:26:32.116004 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 19:26:32.118919 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 19:26:32.126033 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 19:26:32.128710 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 19:26:32.132165 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4675 19:26:32.135509 Total UI for P1: 0, mck2ui 16
4676 19:26:32.138753 best dqsien dly found for B1: ( 0, 13, 10)
4677 19:26:32.145956 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4678 19:26:32.148855 Total UI for P1: 0, mck2ui 16
4679 19:26:32.152333 best dqsien dly found for B0: ( 0, 13, 12)
4680 19:26:32.156105 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4681 19:26:32.159016 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4682 19:26:32.159439
4683 19:26:32.162495 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4684 19:26:32.165387 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4685 19:26:32.169021 [Gating] SW calibration Done
4686 19:26:32.169440 ==
4687 19:26:32.172510 Dram Type= 6, Freq= 0, CH_1, rank 1
4688 19:26:32.175805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4689 19:26:32.176352 ==
4690 19:26:32.179032 RX Vref Scan: 0
4691 19:26:32.179554
4692 19:26:32.182343 RX Vref 0 -> 0, step: 1
4693 19:26:32.182863
4694 19:26:32.183237 RX Delay -230 -> 252, step: 16
4695 19:26:32.189380 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4696 19:26:32.192406 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4697 19:26:32.195528 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4698 19:26:32.198858 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4699 19:26:32.205541 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4700 19:26:32.208974 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4701 19:26:32.212589 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4702 19:26:32.215562 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4703 19:26:32.219105 iDelay=218, Bit 8, Center 9 (-166 ~ 185) 352
4704 19:26:32.225647 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4705 19:26:32.229098 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4706 19:26:32.232088 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4707 19:26:32.235761 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4708 19:26:32.241933 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4709 19:26:32.245248 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4710 19:26:32.248338 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4711 19:26:32.248528 ==
4712 19:26:32.251927 Dram Type= 6, Freq= 0, CH_1, rank 1
4713 19:26:32.255282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4714 19:26:32.258537 ==
4715 19:26:32.258673 DQS Delay:
4716 19:26:32.258799 DQS0 = 0, DQS1 = 0
4717 19:26:32.261790 DQM Delay:
4718 19:26:32.261935 DQM0 = 35, DQM1 = 28
4719 19:26:32.264859 DQ Delay:
4720 19:26:32.265007 DQ0 =33, DQ1 =33, DQ2 =17, DQ3 =33
4721 19:26:32.268475 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4722 19:26:32.271478 DQ8 =9, DQ9 =17, DQ10 =33, DQ11 =25
4723 19:26:32.274922 DQ12 =33, DQ13 =41, DQ14 =33, DQ15 =33
4724 19:26:32.275014
4725 19:26:32.278586
4726 19:26:32.278677 ==
4727 19:26:32.281525 Dram Type= 6, Freq= 0, CH_1, rank 1
4728 19:26:32.284761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4729 19:26:32.284883 ==
4730 19:26:32.284987
4731 19:26:32.285084
4732 19:26:32.288178 TX Vref Scan disable
4733 19:26:32.288309 == TX Byte 0 ==
4734 19:26:32.294772 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4735 19:26:32.298326 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4736 19:26:32.298421 == TX Byte 1 ==
4737 19:26:32.304499 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4738 19:26:32.308079 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4739 19:26:32.308218 ==
4740 19:26:32.311640 Dram Type= 6, Freq= 0, CH_1, rank 1
4741 19:26:32.315072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4742 19:26:32.315191 ==
4743 19:26:32.315283
4744 19:26:32.315369
4745 19:26:32.318615 TX Vref Scan disable
4746 19:26:32.321467 == TX Byte 0 ==
4747 19:26:32.325155 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4748 19:26:32.328145 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4749 19:26:32.331739 == TX Byte 1 ==
4750 19:26:32.334741 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4751 19:26:32.338397 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4752 19:26:32.338623
4753 19:26:32.341355 [DATLAT]
4754 19:26:32.341709 Freq=600, CH1 RK1
4755 19:26:32.342026
4756 19:26:32.345102 DATLAT Default: 0x9
4757 19:26:32.345456 0, 0xFFFF, sum = 0
4758 19:26:32.348105 1, 0xFFFF, sum = 0
4759 19:26:32.348574 2, 0xFFFF, sum = 0
4760 19:26:32.351915 3, 0xFFFF, sum = 0
4761 19:26:32.352282 4, 0xFFFF, sum = 0
4762 19:26:32.355037 5, 0xFFFF, sum = 0
4763 19:26:32.355440 6, 0xFFFF, sum = 0
4764 19:26:32.358515 7, 0xFFFF, sum = 0
4765 19:26:32.358874 8, 0x0, sum = 1
4766 19:26:32.361450 9, 0x0, sum = 2
4767 19:26:32.361948 10, 0x0, sum = 3
4768 19:26:32.364898 11, 0x0, sum = 4
4769 19:26:32.365258 best_step = 9
4770 19:26:32.365575
4771 19:26:32.365848 ==
4772 19:26:32.368149 Dram Type= 6, Freq= 0, CH_1, rank 1
4773 19:26:32.371874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4774 19:26:32.374819 ==
4775 19:26:32.375190 RX Vref Scan: 0
4776 19:26:32.375477
4777 19:26:32.378329 RX Vref 0 -> 0, step: 1
4778 19:26:32.378682
4779 19:26:32.381402 RX Delay -211 -> 252, step: 8
4780 19:26:32.385046 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4781 19:26:32.391552 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4782 19:26:32.394781 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4783 19:26:32.397997 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4784 19:26:32.401439 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4785 19:26:32.404553 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4786 19:26:32.411170 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4787 19:26:32.414540 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4788 19:26:32.418045 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4789 19:26:32.421457 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4790 19:26:32.427617 iDelay=205, Bit 10, Center 32 (-131 ~ 196) 328
4791 19:26:32.431202 iDelay=205, Bit 11, Center 24 (-139 ~ 188) 328
4792 19:26:32.434846 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4793 19:26:32.437790 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4794 19:26:32.444673 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4795 19:26:32.447654 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4796 19:26:32.448088 ==
4797 19:26:32.451192 Dram Type= 6, Freq= 0, CH_1, rank 1
4798 19:26:32.454189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4799 19:26:32.454619 ==
4800 19:26:32.457780 DQS Delay:
4801 19:26:32.458201 DQS0 = 0, DQS1 = 0
4802 19:26:32.458534 DQM Delay:
4803 19:26:32.461468 DQM0 = 36, DQM1 = 30
4804 19:26:32.461925 DQ Delay:
4805 19:26:32.464371 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4806 19:26:32.467553 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =32
4807 19:26:32.471388 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4808 19:26:32.474203 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4809 19:26:32.474625
4810 19:26:32.474958
4811 19:26:32.484344 [DQSOSCAuto] RK1, (LSB)MR18= 0x3454, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
4812 19:26:32.484774 CH1 RK1: MR19=808, MR18=3454
4813 19:26:32.490853 CH1_RK1: MR19=0x808, MR18=0x3454, DQSOSC=393, MR23=63, INC=169, DEC=113
4814 19:26:32.493977 [RxdqsGatingPostProcess] freq 600
4815 19:26:32.500517 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4816 19:26:32.503855 Pre-setting of DQS Precalculation
4817 19:26:32.507170 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4818 19:26:32.517173 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4819 19:26:32.523790 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4820 19:26:32.524343
4821 19:26:32.524830
4822 19:26:32.526892 [Calibration Summary] 1200 Mbps
4823 19:26:32.527400 CH 0, Rank 0
4824 19:26:32.530233 SW Impedance : PASS
4825 19:26:32.530766 DUTY Scan : NO K
4826 19:26:32.533342 ZQ Calibration : PASS
4827 19:26:32.536661 Jitter Meter : NO K
4828 19:26:32.537211 CBT Training : PASS
4829 19:26:32.540347 Write leveling : PASS
4830 19:26:32.543649 RX DQS gating : PASS
4831 19:26:32.544185 RX DQ/DQS(RDDQC) : PASS
4832 19:26:32.546603 TX DQ/DQS : PASS
4833 19:26:32.547057 RX DATLAT : PASS
4834 19:26:32.550416 RX DQ/DQS(Engine): PASS
4835 19:26:32.553438 TX OE : NO K
4836 19:26:32.553974 All Pass.
4837 19:26:32.554361
4838 19:26:32.554683 CH 0, Rank 1
4839 19:26:32.556976 SW Impedance : PASS
4840 19:26:32.559946 DUTY Scan : NO K
4841 19:26:32.560527 ZQ Calibration : PASS
4842 19:26:32.563580 Jitter Meter : NO K
4843 19:26:32.566618 CBT Training : PASS
4844 19:26:32.567165 Write leveling : PASS
4845 19:26:32.570256 RX DQS gating : PASS
4846 19:26:32.573747 RX DQ/DQS(RDDQC) : PASS
4847 19:26:32.574272 TX DQ/DQS : PASS
4848 19:26:32.576785 RX DATLAT : PASS
4849 19:26:32.579895 RX DQ/DQS(Engine): PASS
4850 19:26:32.580398 TX OE : NO K
4851 19:26:32.583684 All Pass.
4852 19:26:32.584100
4853 19:26:32.584426 CH 1, Rank 0
4854 19:26:32.586692 SW Impedance : PASS
4855 19:26:32.587108 DUTY Scan : NO K
4856 19:26:32.590204 ZQ Calibration : PASS
4857 19:26:32.593668 Jitter Meter : NO K
4858 19:26:32.594222 CBT Training : PASS
4859 19:26:32.596801 Write leveling : PASS
4860 19:26:32.599959 RX DQS gating : PASS
4861 19:26:32.600532 RX DQ/DQS(RDDQC) : PASS
4862 19:26:32.603692 TX DQ/DQS : PASS
4863 19:26:32.604110 RX DATLAT : PASS
4864 19:26:32.607063 RX DQ/DQS(Engine): PASS
4865 19:26:32.609940 TX OE : NO K
4866 19:26:32.610487 All Pass.
4867 19:26:32.610830
4868 19:26:32.611139 CH 1, Rank 1
4869 19:26:32.613443 SW Impedance : PASS
4870 19:26:32.616914 DUTY Scan : NO K
4871 19:26:32.617489 ZQ Calibration : PASS
4872 19:26:32.620458 Jitter Meter : NO K
4873 19:26:32.623485 CBT Training : PASS
4874 19:26:32.624067 Write leveling : PASS
4875 19:26:32.626588 RX DQS gating : PASS
4876 19:26:32.629937 RX DQ/DQS(RDDQC) : PASS
4877 19:26:32.630356 TX DQ/DQS : PASS
4878 19:26:32.633254 RX DATLAT : PASS
4879 19:26:32.636720 RX DQ/DQS(Engine): PASS
4880 19:26:32.637393 TX OE : NO K
4881 19:26:32.639880 All Pass.
4882 19:26:32.640387
4883 19:26:32.640841 DramC Write-DBI off
4884 19:26:32.642937 PER_BANK_REFRESH: Hybrid Mode
4885 19:26:32.643424 TX_TRACKING: ON
4886 19:26:32.653086 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4887 19:26:32.656206 [FAST_K] Save calibration result to emmc
4888 19:26:32.659546 dramc_set_vcore_voltage set vcore to 662500
4889 19:26:32.663262 Read voltage for 933, 3
4890 19:26:32.663747 Vio18 = 0
4891 19:26:32.666579 Vcore = 662500
4892 19:26:32.667124 Vdram = 0
4893 19:26:32.667709 Vddq = 0
4894 19:26:32.669294 Vmddr = 0
4895 19:26:32.673482 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4896 19:26:32.679373 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4897 19:26:32.680027 MEM_TYPE=3, freq_sel=17
4898 19:26:32.682944 sv_algorithm_assistance_LP4_1600
4899 19:26:32.689566 ============ PULL DRAM RESETB DOWN ============
4900 19:26:32.692476 ========== PULL DRAM RESETB DOWN end =========
4901 19:26:32.696206 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4902 19:26:32.699549 ===================================
4903 19:26:32.702853 LPDDR4 DRAM CONFIGURATION
4904 19:26:32.705793 ===================================
4905 19:26:32.706212 EX_ROW_EN[0] = 0x0
4906 19:26:32.709480 EX_ROW_EN[1] = 0x0
4907 19:26:32.712608 LP4Y_EN = 0x0
4908 19:26:32.713022 WORK_FSP = 0x0
4909 19:26:32.716130 WL = 0x3
4910 19:26:32.716833 RL = 0x3
4911 19:26:32.719048 BL = 0x2
4912 19:26:32.719559 RPST = 0x0
4913 19:26:32.722787 RD_PRE = 0x0
4914 19:26:32.723325 WR_PRE = 0x1
4915 19:26:32.725691 WR_PST = 0x0
4916 19:26:32.726107 DBI_WR = 0x0
4917 19:26:32.728837 DBI_RD = 0x0
4918 19:26:32.729282 OTF = 0x1
4919 19:26:32.732256 ===================================
4920 19:26:32.735902 ===================================
4921 19:26:32.739430 ANA top config
4922 19:26:32.742689 ===================================
4923 19:26:32.743104 DLL_ASYNC_EN = 0
4924 19:26:32.745795 ALL_SLAVE_EN = 1
4925 19:26:32.748822 NEW_RANK_MODE = 1
4926 19:26:32.752479 DLL_IDLE_MODE = 1
4927 19:26:32.755756 LP45_APHY_COMB_EN = 1
4928 19:26:32.756266 TX_ODT_DIS = 1
4929 19:26:32.759037 NEW_8X_MODE = 1
4930 19:26:32.762410 ===================================
4931 19:26:32.765484 ===================================
4932 19:26:32.769079 data_rate = 1866
4933 19:26:32.772343 CKR = 1
4934 19:26:32.775653 DQ_P2S_RATIO = 8
4935 19:26:32.779050 ===================================
4936 19:26:32.782149 CA_P2S_RATIO = 8
4937 19:26:32.782657 DQ_CA_OPEN = 0
4938 19:26:32.785597 DQ_SEMI_OPEN = 0
4939 19:26:32.788739 CA_SEMI_OPEN = 0
4940 19:26:32.792165 CA_FULL_RATE = 0
4941 19:26:32.795162 DQ_CKDIV4_EN = 1
4942 19:26:32.798865 CA_CKDIV4_EN = 1
4943 19:26:32.799286 CA_PREDIV_EN = 0
4944 19:26:32.801890 PH8_DLY = 0
4945 19:26:32.805416 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4946 19:26:32.808658 DQ_AAMCK_DIV = 4
4947 19:26:32.811677 CA_AAMCK_DIV = 4
4948 19:26:32.815332 CA_ADMCK_DIV = 4
4949 19:26:32.815754 DQ_TRACK_CA_EN = 0
4950 19:26:32.818901 CA_PICK = 933
4951 19:26:32.821948 CA_MCKIO = 933
4952 19:26:32.825482 MCKIO_SEMI = 0
4953 19:26:32.828402 PLL_FREQ = 3732
4954 19:26:32.832069 DQ_UI_PI_RATIO = 32
4955 19:26:32.835111 CA_UI_PI_RATIO = 0
4956 19:26:32.838580 ===================================
4957 19:26:32.841595 ===================================
4958 19:26:32.842017 memory_type:LPDDR4
4959 19:26:32.845169 GP_NUM : 10
4960 19:26:32.845624 SRAM_EN : 1
4961 19:26:32.848766 MD32_EN : 0
4962 19:26:32.851616 ===================================
4963 19:26:32.854860 [ANA_INIT] >>>>>>>>>>>>>>
4964 19:26:32.858074 <<<<<< [CONFIGURE PHASE]: ANA_TX
4965 19:26:32.861891 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4966 19:26:32.865098 ===================================
4967 19:26:32.868225 data_rate = 1866,PCW = 0X8f00
4968 19:26:32.868762 ===================================
4969 19:26:32.872047 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4970 19:26:32.878407 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4971 19:26:32.884982 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4972 19:26:32.888421 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4973 19:26:32.891802 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4974 19:26:32.894479 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4975 19:26:32.898465 [ANA_INIT] flow start
4976 19:26:32.901620 [ANA_INIT] PLL >>>>>>>>
4977 19:26:32.902225 [ANA_INIT] PLL <<<<<<<<
4978 19:26:32.904961 [ANA_INIT] MIDPI >>>>>>>>
4979 19:26:32.908412 [ANA_INIT] MIDPI <<<<<<<<
4980 19:26:32.908826 [ANA_INIT] DLL >>>>>>>>
4981 19:26:32.911451 [ANA_INIT] flow end
4982 19:26:32.914449 ============ LP4 DIFF to SE enter ============
4983 19:26:32.918122 ============ LP4 DIFF to SE exit ============
4984 19:26:32.921347 [ANA_INIT] <<<<<<<<<<<<<
4985 19:26:32.924755 [Flow] Enable top DCM control >>>>>
4986 19:26:32.928322 [Flow] Enable top DCM control <<<<<
4987 19:26:32.931374 Enable DLL master slave shuffle
4988 19:26:32.937900 ==============================================================
4989 19:26:32.938325 Gating Mode config
4990 19:26:32.944485 ==============================================================
4991 19:26:32.948032 Config description:
4992 19:26:32.954579 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4993 19:26:32.960926 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4994 19:26:32.967395 SELPH_MODE 0: By rank 1: By Phase
4995 19:26:32.974340 ==============================================================
4996 19:26:32.977470 GAT_TRACK_EN = 1
4997 19:26:32.977959 RX_GATING_MODE = 2
4998 19:26:32.980844 RX_GATING_TRACK_MODE = 2
4999 19:26:32.984019 SELPH_MODE = 1
5000 19:26:32.987093 PICG_EARLY_EN = 1
5001 19:26:32.990554 VALID_LAT_VALUE = 1
5002 19:26:32.997027 ==============================================================
5003 19:26:33.000556 Enter into Gating configuration >>>>
5004 19:26:33.004036 Exit from Gating configuration <<<<
5005 19:26:33.006949 Enter into DVFS_PRE_config >>>>>
5006 19:26:33.017140 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5007 19:26:33.020702 Exit from DVFS_PRE_config <<<<<
5008 19:26:33.023807 Enter into PICG configuration >>>>
5009 19:26:33.027124 Exit from PICG configuration <<<<
5010 19:26:33.029942 [RX_INPUT] configuration >>>>>
5011 19:26:33.033305 [RX_INPUT] configuration <<<<<
5012 19:26:33.036876 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5013 19:26:33.043445 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5014 19:26:33.049772 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5015 19:26:33.056417 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5016 19:26:33.060002 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5017 19:26:33.066607 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5018 19:26:33.069577 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5019 19:26:33.076276 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5020 19:26:33.079860 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5021 19:26:33.082663 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5022 19:26:33.086408 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5023 19:26:33.092739 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5024 19:26:33.096238 ===================================
5025 19:26:33.096393 LPDDR4 DRAM CONFIGURATION
5026 19:26:33.099345 ===================================
5027 19:26:33.103291 EX_ROW_EN[0] = 0x0
5028 19:26:33.106162 EX_ROW_EN[1] = 0x0
5029 19:26:33.106733 LP4Y_EN = 0x0
5030 19:26:33.109370 WORK_FSP = 0x0
5031 19:26:33.110026 WL = 0x3
5032 19:26:33.112631 RL = 0x3
5033 19:26:33.113218 BL = 0x2
5034 19:26:33.116305 RPST = 0x0
5035 19:26:33.116871 RD_PRE = 0x0
5036 19:26:33.119810 WR_PRE = 0x1
5037 19:26:33.120363 WR_PST = 0x0
5038 19:26:33.122776 DBI_WR = 0x0
5039 19:26:33.123204 DBI_RD = 0x0
5040 19:26:33.126300 OTF = 0x1
5041 19:26:33.129730 ===================================
5042 19:26:33.133071 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5043 19:26:33.136278 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5044 19:26:33.143184 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5045 19:26:33.146161 ===================================
5046 19:26:33.146584 LPDDR4 DRAM CONFIGURATION
5047 19:26:33.149653 ===================================
5048 19:26:33.153126 EX_ROW_EN[0] = 0x10
5049 19:26:33.155819 EX_ROW_EN[1] = 0x0
5050 19:26:33.156335 LP4Y_EN = 0x0
5051 19:26:33.159520 WORK_FSP = 0x0
5052 19:26:33.159972 WL = 0x3
5053 19:26:33.162505 RL = 0x3
5054 19:26:33.162959 BL = 0x2
5055 19:26:33.166104 RPST = 0x0
5056 19:26:33.166552 RD_PRE = 0x0
5057 19:26:33.169630 WR_PRE = 0x1
5058 19:26:33.170173 WR_PST = 0x0
5059 19:26:33.172693 DBI_WR = 0x0
5060 19:26:33.173126 DBI_RD = 0x0
5061 19:26:33.176139 OTF = 0x1
5062 19:26:33.179522 ===================================
5063 19:26:33.186156 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5064 19:26:33.189363 nWR fixed to 30
5065 19:26:33.192376 [ModeRegInit_LP4] CH0 RK0
5066 19:26:33.192942 [ModeRegInit_LP4] CH0 RK1
5067 19:26:33.195915 [ModeRegInit_LP4] CH1 RK0
5068 19:26:33.199199 [ModeRegInit_LP4] CH1 RK1
5069 19:26:33.199761 match AC timing 9
5070 19:26:33.205613 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5071 19:26:33.209219 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5072 19:26:33.212342 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5073 19:26:33.219179 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5074 19:26:33.222500 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5075 19:26:33.222919 ==
5076 19:26:33.225578 Dram Type= 6, Freq= 0, CH_0, rank 0
5077 19:26:33.229006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5078 19:26:33.229425 ==
5079 19:26:33.235850 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5080 19:26:33.242460 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5081 19:26:33.245267 [CA 0] Center 38 (8~69) winsize 62
5082 19:26:33.249043 [CA 1] Center 38 (8~69) winsize 62
5083 19:26:33.252084 [CA 2] Center 35 (5~66) winsize 62
5084 19:26:33.255695 [CA 3] Center 35 (5~66) winsize 62
5085 19:26:33.258532 [CA 4] Center 34 (4~65) winsize 62
5086 19:26:33.262140 [CA 5] Center 34 (4~64) winsize 61
5087 19:26:33.262629
5088 19:26:33.265768 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5089 19:26:33.266185
5090 19:26:33.268937 [CATrainingPosCal] consider 1 rank data
5091 19:26:33.272539 u2DelayCellTimex100 = 270/100 ps
5092 19:26:33.275460 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5093 19:26:33.278783 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5094 19:26:33.281943 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5095 19:26:33.285405 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5096 19:26:33.288415 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5097 19:26:33.292142 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5098 19:26:33.292564
5099 19:26:33.298991 CA PerBit enable=1, Macro0, CA PI delay=34
5100 19:26:33.299518
5101 19:26:33.302392 [CBTSetCACLKResult] CA Dly = 34
5102 19:26:33.302913 CS Dly: 6 (0~37)
5103 19:26:33.303244 ==
5104 19:26:33.305132 Dram Type= 6, Freq= 0, CH_0, rank 1
5105 19:26:33.308881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5106 19:26:33.309421 ==
5107 19:26:33.315504 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5108 19:26:33.322100 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5109 19:26:33.325393 [CA 0] Center 38 (8~69) winsize 62
5110 19:26:33.328557 [CA 1] Center 38 (8~69) winsize 62
5111 19:26:33.331923 [CA 2] Center 35 (5~66) winsize 62
5112 19:26:33.335139 [CA 3] Center 35 (5~66) winsize 62
5113 19:26:33.338179 [CA 4] Center 34 (4~65) winsize 62
5114 19:26:33.341596 [CA 5] Center 33 (3~64) winsize 62
5115 19:26:33.342210
5116 19:26:33.344902 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5117 19:26:33.345440
5118 19:26:33.348305 [CATrainingPosCal] consider 2 rank data
5119 19:26:33.351958 u2DelayCellTimex100 = 270/100 ps
5120 19:26:33.354931 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5121 19:26:33.358436 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5122 19:26:33.361732 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5123 19:26:33.364648 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5124 19:26:33.368056 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5125 19:26:33.374989 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5126 19:26:33.375553
5127 19:26:33.378368 CA PerBit enable=1, Macro0, CA PI delay=34
5128 19:26:33.378897
5129 19:26:33.381361 [CBTSetCACLKResult] CA Dly = 34
5130 19:26:33.381901 CS Dly: 7 (0~39)
5131 19:26:33.382298
5132 19:26:33.384835 ----->DramcWriteLeveling(PI) begin...
5133 19:26:33.385480 ==
5134 19:26:33.387863 Dram Type= 6, Freq= 0, CH_0, rank 0
5135 19:26:33.391563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5136 19:26:33.394456 ==
5137 19:26:33.397983 Write leveling (Byte 0): 33 => 33
5138 19:26:33.398445 Write leveling (Byte 1): 32 => 32
5139 19:26:33.401459 DramcWriteLeveling(PI) end<-----
5140 19:26:33.401968
5141 19:26:33.402421 ==
5142 19:26:33.404264 Dram Type= 6, Freq= 0, CH_0, rank 0
5143 19:26:33.411463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5144 19:26:33.411984 ==
5145 19:26:33.414357 [Gating] SW mode calibration
5146 19:26:33.420940 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5147 19:26:33.424569 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5148 19:26:33.430922 0 14 0 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
5149 19:26:33.434339 0 14 4 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
5150 19:26:33.437743 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5151 19:26:33.444304 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5152 19:26:33.447724 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5153 19:26:33.451081 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5154 19:26:33.457400 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5155 19:26:33.460739 0 14 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
5156 19:26:33.464086 0 15 0 | B1->B0 | 3333 2e2e | 0 0 | (0 1) (1 1)
5157 19:26:33.471128 0 15 4 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
5158 19:26:33.473897 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5159 19:26:33.477179 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5160 19:26:33.484379 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5161 19:26:33.487479 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5162 19:26:33.490665 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5163 19:26:33.497243 0 15 28 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
5164 19:26:33.500188 1 0 0 | B1->B0 | 2d2d 3f3f | 0 0 | (0 0) (0 0)
5165 19:26:33.503841 1 0 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5166 19:26:33.510743 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5167 19:26:33.513966 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5168 19:26:33.517116 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5169 19:26:33.520420 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5170 19:26:33.527137 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5171 19:26:33.530145 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5172 19:26:33.533789 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5173 19:26:33.540554 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5174 19:26:33.543423 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 19:26:33.547110 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 19:26:33.553737 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 19:26:33.557066 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 19:26:33.560342 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 19:26:33.566695 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 19:26:33.570387 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 19:26:33.573298 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 19:26:33.580042 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 19:26:33.583723 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 19:26:33.586650 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 19:26:33.593368 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 19:26:33.596584 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 19:26:33.600307 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5188 19:26:33.606914 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5189 19:26:33.607343 Total UI for P1: 0, mck2ui 16
5190 19:26:33.613615 best dqsien dly found for B0: ( 1, 2, 28)
5191 19:26:33.616384 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5192 19:26:33.619767 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5193 19:26:33.622818 Total UI for P1: 0, mck2ui 16
5194 19:26:33.626581 best dqsien dly found for B1: ( 1, 3, 4)
5195 19:26:33.629398 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5196 19:26:33.633080 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5197 19:26:33.633629
5198 19:26:33.639786 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5199 19:26:33.642715 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5200 19:26:33.643286 [Gating] SW calibration Done
5201 19:26:33.646100 ==
5202 19:26:33.649464 Dram Type= 6, Freq= 0, CH_0, rank 0
5203 19:26:33.653177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5204 19:26:33.653652 ==
5205 19:26:33.653996 RX Vref Scan: 0
5206 19:26:33.654311
5207 19:26:33.656205 RX Vref 0 -> 0, step: 1
5208 19:26:33.656620
5209 19:26:33.659882 RX Delay -80 -> 252, step: 8
5210 19:26:33.662773 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5211 19:26:33.666228 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5212 19:26:33.669434 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5213 19:26:33.675871 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5214 19:26:33.679251 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5215 19:26:33.682561 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5216 19:26:33.686234 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5217 19:26:33.689447 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5218 19:26:33.692440 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5219 19:26:33.698933 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5220 19:26:33.702437 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5221 19:26:33.705906 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5222 19:26:33.709293 iDelay=208, Bit 12, Center 87 (-16 ~ 191) 208
5223 19:26:33.715793 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5224 19:26:33.718672 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5225 19:26:33.721838 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5226 19:26:33.721993 ==
5227 19:26:33.725529 Dram Type= 6, Freq= 0, CH_0, rank 0
5228 19:26:33.728518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5229 19:26:33.728624 ==
5230 19:26:33.731822 DQS Delay:
5231 19:26:33.731915 DQS0 = 0, DQS1 = 0
5232 19:26:33.735084 DQM Delay:
5233 19:26:33.735208 DQM0 = 94, DQM1 = 83
5234 19:26:33.735312 DQ Delay:
5235 19:26:33.738416 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5236 19:26:33.742316 DQ4 =99, DQ5 =79, DQ6 =103, DQ7 =107
5237 19:26:33.745187 DQ8 =79, DQ9 =71, DQ10 =83, DQ11 =75
5238 19:26:33.748410 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =91
5239 19:26:33.748492
5240 19:26:33.748557
5241 19:26:33.751797 ==
5242 19:26:33.751879 Dram Type= 6, Freq= 0, CH_0, rank 0
5243 19:26:33.758615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5244 19:26:33.758781 ==
5245 19:26:33.758865
5246 19:26:33.758936
5247 19:26:33.761632 TX Vref Scan disable
5248 19:26:33.761732 == TX Byte 0 ==
5249 19:26:33.765118 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5250 19:26:33.771713 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5251 19:26:33.771797 == TX Byte 1 ==
5252 19:26:33.775238 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5253 19:26:33.781870 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5254 19:26:33.781965 ==
5255 19:26:33.784835 Dram Type= 6, Freq= 0, CH_0, rank 0
5256 19:26:33.788676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5257 19:26:33.789118 ==
5258 19:26:33.789445
5259 19:26:33.789784
5260 19:26:33.792036 TX Vref Scan disable
5261 19:26:33.795138 == TX Byte 0 ==
5262 19:26:33.798546 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5263 19:26:33.801832 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5264 19:26:33.805382 == TX Byte 1 ==
5265 19:26:33.808369 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5266 19:26:33.811967 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5267 19:26:33.812404
5268 19:26:33.815017 [DATLAT]
5269 19:26:33.815457 Freq=933, CH0 RK0
5270 19:26:33.815898
5271 19:26:33.818379 DATLAT Default: 0xd
5272 19:26:33.818819 0, 0xFFFF, sum = 0
5273 19:26:33.822151 1, 0xFFFF, sum = 0
5274 19:26:33.822598 2, 0xFFFF, sum = 0
5275 19:26:33.824918 3, 0xFFFF, sum = 0
5276 19:26:33.825361 4, 0xFFFF, sum = 0
5277 19:26:33.828144 5, 0xFFFF, sum = 0
5278 19:26:33.828589 6, 0xFFFF, sum = 0
5279 19:26:33.831742 7, 0xFFFF, sum = 0
5280 19:26:33.832186 8, 0xFFFF, sum = 0
5281 19:26:33.834847 9, 0xFFFF, sum = 0
5282 19:26:33.835291 10, 0x0, sum = 1
5283 19:26:33.837994 11, 0x0, sum = 2
5284 19:26:33.838488 12, 0x0, sum = 3
5285 19:26:33.841305 13, 0x0, sum = 4
5286 19:26:33.841803 best_step = 11
5287 19:26:33.842242
5288 19:26:33.842656 ==
5289 19:26:33.844843 Dram Type= 6, Freq= 0, CH_0, rank 0
5290 19:26:33.847840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5291 19:26:33.851520 ==
5292 19:26:33.851958 RX Vref Scan: 1
5293 19:26:33.852394
5294 19:26:33.854742 RX Vref 0 -> 0, step: 1
5295 19:26:33.855180
5296 19:26:33.858443 RX Delay -69 -> 252, step: 4
5297 19:26:33.858881
5298 19:26:33.861276 Set Vref, RX VrefLevel [Byte0]: 60
5299 19:26:33.864610 [Byte1]: 54
5300 19:26:33.865049
5301 19:26:33.868183 Final RX Vref Byte 0 = 60 to rank0
5302 19:26:33.871397 Final RX Vref Byte 1 = 54 to rank0
5303 19:26:33.874961 Final RX Vref Byte 0 = 60 to rank1
5304 19:26:33.878034 Final RX Vref Byte 1 = 54 to rank1==
5305 19:26:33.881490 Dram Type= 6, Freq= 0, CH_0, rank 0
5306 19:26:33.884455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5307 19:26:33.885041 ==
5308 19:26:33.888234 DQS Delay:
5309 19:26:33.888891 DQS0 = 0, DQS1 = 0
5310 19:26:33.889366 DQM Delay:
5311 19:26:33.891185 DQM0 = 95, DQM1 = 83
5312 19:26:33.891755 DQ Delay:
5313 19:26:33.894583 DQ0 =94, DQ1 =94, DQ2 =92, DQ3 =94
5314 19:26:33.898060 DQ4 =96, DQ5 =84, DQ6 =102, DQ7 =104
5315 19:26:33.901264 DQ8 =76, DQ9 =70, DQ10 =84, DQ11 =78
5316 19:26:33.904250 DQ12 =88, DQ13 =90, DQ14 =92, DQ15 =90
5317 19:26:33.904821
5318 19:26:33.905290
5319 19:26:33.914527 [DQSOSCAuto] RK0, (LSB)MR18= 0x100f, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 416 ps
5320 19:26:33.917975 CH0 RK0: MR19=505, MR18=100F
5321 19:26:33.921089 CH0_RK0: MR19=0x505, MR18=0x100F, DQSOSC=416, MR23=63, INC=62, DEC=41
5322 19:26:33.921694
5323 19:26:33.927707 ----->DramcWriteLeveling(PI) begin...
5324 19:26:33.928413 ==
5325 19:26:33.930920 Dram Type= 6, Freq= 0, CH_0, rank 1
5326 19:26:33.934417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5327 19:26:33.934899 ==
5328 19:26:33.937624 Write leveling (Byte 0): 32 => 32
5329 19:26:33.940951 Write leveling (Byte 1): 28 => 28
5330 19:26:33.943922 DramcWriteLeveling(PI) end<-----
5331 19:26:33.944341
5332 19:26:33.944664 ==
5333 19:26:33.947431 Dram Type= 6, Freq= 0, CH_0, rank 1
5334 19:26:33.950992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5335 19:26:33.951490 ==
5336 19:26:33.954182 [Gating] SW mode calibration
5337 19:26:33.960230 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5338 19:26:33.966867 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5339 19:26:33.970224 0 14 0 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
5340 19:26:33.973357 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5341 19:26:33.980539 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5342 19:26:33.984011 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5343 19:26:33.987111 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5344 19:26:33.993593 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5345 19:26:33.996623 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5346 19:26:34.000268 0 14 28 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (1 0)
5347 19:26:34.006621 0 15 0 | B1->B0 | 3030 2323 | 0 0 | (1 1) (0 0)
5348 19:26:34.009972 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5349 19:26:34.013347 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5350 19:26:34.019764 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5351 19:26:34.023255 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5352 19:26:34.026193 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5353 19:26:34.033190 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5354 19:26:34.036775 0 15 28 | B1->B0 | 2828 3333 | 0 0 | (0 0) (0 0)
5355 19:26:34.039684 1 0 0 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
5356 19:26:34.046553 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5357 19:26:34.049805 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5358 19:26:34.052827 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5359 19:26:34.059423 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5360 19:26:34.062897 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5361 19:26:34.066434 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5362 19:26:34.072923 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5363 19:26:34.076258 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5364 19:26:34.079742 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5365 19:26:34.086028 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 19:26:34.089643 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 19:26:34.092632 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 19:26:34.099530 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 19:26:34.102472 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 19:26:34.106133 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 19:26:34.109196 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 19:26:34.115758 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 19:26:34.119296 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 19:26:34.125730 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 19:26:34.129243 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 19:26:34.132655 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 19:26:34.135828 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 19:26:34.142610 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5379 19:26:34.145833 Total UI for P1: 0, mck2ui 16
5380 19:26:34.149301 best dqsien dly found for B0: ( 1, 2, 26)
5381 19:26:34.152420 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5382 19:26:34.156128 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5383 19:26:34.158705 Total UI for P1: 0, mck2ui 16
5384 19:26:34.162343 best dqsien dly found for B1: ( 1, 2, 30)
5385 19:26:34.165393 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5386 19:26:34.172232 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5387 19:26:34.172749
5388 19:26:34.175826 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5389 19:26:34.178597 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5390 19:26:34.182013 [Gating] SW calibration Done
5391 19:26:34.182490 ==
5392 19:26:34.185476 Dram Type= 6, Freq= 0, CH_0, rank 1
5393 19:26:34.188361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5394 19:26:34.188783 ==
5395 19:26:34.191693 RX Vref Scan: 0
5396 19:26:34.192114
5397 19:26:34.192440 RX Vref 0 -> 0, step: 1
5398 19:26:34.192746
5399 19:26:34.195045 RX Delay -80 -> 252, step: 8
5400 19:26:34.198482 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5401 19:26:34.201647 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5402 19:26:34.208444 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5403 19:26:34.211873 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5404 19:26:34.215135 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5405 19:26:34.218531 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5406 19:26:34.221385 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5407 19:26:34.228389 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5408 19:26:34.231688 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5409 19:26:34.235004 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5410 19:26:34.237921 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5411 19:26:34.241936 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5412 19:26:34.248143 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5413 19:26:34.251223 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5414 19:26:34.254813 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5415 19:26:34.257708 iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192
5416 19:26:34.257894 ==
5417 19:26:34.261300 Dram Type= 6, Freq= 0, CH_0, rank 1
5418 19:26:34.264767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5419 19:26:34.267670 ==
5420 19:26:34.267802 DQS Delay:
5421 19:26:34.267906 DQS0 = 0, DQS1 = 0
5422 19:26:34.270799 DQM Delay:
5423 19:26:34.270930 DQM0 = 92, DQM1 = 83
5424 19:26:34.274433 DQ Delay:
5425 19:26:34.277971 DQ0 =91, DQ1 =91, DQ2 =87, DQ3 =91
5426 19:26:34.281028 DQ4 =91, DQ5 =79, DQ6 =103, DQ7 =103
5427 19:26:34.284166 DQ8 =75, DQ9 =67, DQ10 =83, DQ11 =79
5428 19:26:34.287631 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =87
5429 19:26:34.287716
5430 19:26:34.287782
5431 19:26:34.287844 ==
5432 19:26:34.291010 Dram Type= 6, Freq= 0, CH_0, rank 1
5433 19:26:34.294040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5434 19:26:34.294124 ==
5435 19:26:34.294189
5436 19:26:34.294248
5437 19:26:34.298055 TX Vref Scan disable
5438 19:26:34.298384 == TX Byte 0 ==
5439 19:26:34.304466 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5440 19:26:34.307446 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5441 19:26:34.307740 == TX Byte 1 ==
5442 19:26:34.313921 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5443 19:26:34.317429 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5444 19:26:34.317732 ==
5445 19:26:34.320673 Dram Type= 6, Freq= 0, CH_0, rank 1
5446 19:26:34.323954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5447 19:26:34.324194 ==
5448 19:26:34.324383
5449 19:26:34.327234
5450 19:26:34.327509 TX Vref Scan disable
5451 19:26:34.330718 == TX Byte 0 ==
5452 19:26:34.334048 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5453 19:26:34.337370 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5454 19:26:34.340761 == TX Byte 1 ==
5455 19:26:34.344183 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5456 19:26:34.347596 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5457 19:26:34.347839
5458 19:26:34.350560 [DATLAT]
5459 19:26:34.350802 Freq=933, CH0 RK1
5460 19:26:34.350994
5461 19:26:34.353846 DATLAT Default: 0xb
5462 19:26:34.354100 0, 0xFFFF, sum = 0
5463 19:26:34.357080 1, 0xFFFF, sum = 0
5464 19:26:34.357325 2, 0xFFFF, sum = 0
5465 19:26:34.360441 3, 0xFFFF, sum = 0
5466 19:26:34.360688 4, 0xFFFF, sum = 0
5467 19:26:34.364102 5, 0xFFFF, sum = 0
5468 19:26:34.364349 6, 0xFFFF, sum = 0
5469 19:26:34.367133 7, 0xFFFF, sum = 0
5470 19:26:34.370452 8, 0xFFFF, sum = 0
5471 19:26:34.370701 9, 0xFFFF, sum = 0
5472 19:26:34.374180 10, 0x0, sum = 1
5473 19:26:34.374426 11, 0x0, sum = 2
5474 19:26:34.374620 12, 0x0, sum = 3
5475 19:26:34.377229 13, 0x0, sum = 4
5476 19:26:34.377475 best_step = 11
5477 19:26:34.377728
5478 19:26:34.377912 ==
5479 19:26:34.380231 Dram Type= 6, Freq= 0, CH_0, rank 1
5480 19:26:34.386898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5481 19:26:34.387143 ==
5482 19:26:34.387389 RX Vref Scan: 0
5483 19:26:34.387576
5484 19:26:34.390481 RX Vref 0 -> 0, step: 1
5485 19:26:34.390563
5486 19:26:34.393349 RX Delay -77 -> 252, step: 4
5487 19:26:34.396734 iDelay=199, Bit 0, Center 88 (-5 ~ 182) 188
5488 19:26:34.403569 iDelay=199, Bit 1, Center 92 (-1 ~ 186) 188
5489 19:26:34.407017 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5490 19:26:34.409951 iDelay=199, Bit 3, Center 90 (-5 ~ 186) 192
5491 19:26:34.413489 iDelay=199, Bit 4, Center 92 (-1 ~ 186) 188
5492 19:26:34.416507 iDelay=199, Bit 5, Center 80 (-13 ~ 174) 188
5493 19:26:34.423682 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5494 19:26:34.427115 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5495 19:26:34.430605 iDelay=199, Bit 8, Center 78 (-13 ~ 170) 184
5496 19:26:34.433828 iDelay=199, Bit 9, Center 70 (-17 ~ 158) 176
5497 19:26:34.437042 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5498 19:26:34.443276 iDelay=199, Bit 11, Center 78 (-13 ~ 170) 184
5499 19:26:34.447109 iDelay=199, Bit 12, Center 92 (-1 ~ 186) 188
5500 19:26:34.450113 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5501 19:26:34.453084 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5502 19:26:34.456398 iDelay=199, Bit 15, Center 92 (-1 ~ 186) 188
5503 19:26:34.456973 ==
5504 19:26:34.459851 Dram Type= 6, Freq= 0, CH_0, rank 1
5505 19:26:34.466879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5506 19:26:34.467391 ==
5507 19:26:34.467830 DQS Delay:
5508 19:26:34.470207 DQS0 = 0, DQS1 = 0
5509 19:26:34.470629 DQM Delay:
5510 19:26:34.470964 DQM0 = 92, DQM1 = 85
5511 19:26:34.473218 DQ Delay:
5512 19:26:34.476687 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =90
5513 19:26:34.480140 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
5514 19:26:34.483122 DQ8 =78, DQ9 =70, DQ10 =86, DQ11 =78
5515 19:26:34.486240 DQ12 =92, DQ13 =90, DQ14 =96, DQ15 =92
5516 19:26:34.486656
5517 19:26:34.486979
5518 19:26:34.493348 [DQSOSCAuto] RK1, (LSB)MR18= 0x2b0c, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 408 ps
5519 19:26:34.496281 CH0 RK1: MR19=505, MR18=2B0C
5520 19:26:34.502824 CH0_RK1: MR19=0x505, MR18=0x2B0C, DQSOSC=408, MR23=63, INC=65, DEC=43
5521 19:26:34.506357 [RxdqsGatingPostProcess] freq 933
5522 19:26:34.512845 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5523 19:26:34.513268 best DQS0 dly(2T, 0.5T) = (0, 10)
5524 19:26:34.516534 best DQS1 dly(2T, 0.5T) = (0, 11)
5525 19:26:34.519340 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5526 19:26:34.523106 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5527 19:26:34.525964 best DQS0 dly(2T, 0.5T) = (0, 10)
5528 19:26:34.529694 best DQS1 dly(2T, 0.5T) = (0, 10)
5529 19:26:34.532500 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5530 19:26:34.535965 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5531 19:26:34.539579 Pre-setting of DQS Precalculation
5532 19:26:34.545490 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5533 19:26:34.545958 ==
5534 19:26:34.548966 Dram Type= 6, Freq= 0, CH_1, rank 0
5535 19:26:34.552412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5536 19:26:34.552879 ==
5537 19:26:34.558884 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5538 19:26:34.562228 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5539 19:26:34.566376 [CA 0] Center 37 (8~67) winsize 60
5540 19:26:34.569366 [CA 1] Center 38 (8~68) winsize 61
5541 19:26:34.573197 [CA 2] Center 34 (5~64) winsize 60
5542 19:26:34.576130 [CA 3] Center 34 (5~64) winsize 60
5543 19:26:34.579544 [CA 4] Center 35 (5~65) winsize 61
5544 19:26:34.582913 [CA 5] Center 33 (4~63) winsize 60
5545 19:26:34.583333
5546 19:26:34.586547 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5547 19:26:34.587029
5548 19:26:34.589583 [CATrainingPosCal] consider 1 rank data
5549 19:26:34.593048 u2DelayCellTimex100 = 270/100 ps
5550 19:26:34.596207 CA0 delay=37 (8~67),Diff = 4 PI (24 cell)
5551 19:26:34.602553 CA1 delay=38 (8~68),Diff = 5 PI (31 cell)
5552 19:26:34.606078 CA2 delay=34 (5~64),Diff = 1 PI (6 cell)
5553 19:26:34.609096 CA3 delay=34 (5~64),Diff = 1 PI (6 cell)
5554 19:26:34.612750 CA4 delay=35 (5~65),Diff = 2 PI (12 cell)
5555 19:26:34.616185 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5556 19:26:34.616485
5557 19:26:34.619314 CA PerBit enable=1, Macro0, CA PI delay=33
5558 19:26:34.619740
5559 19:26:34.622727 [CBTSetCACLKResult] CA Dly = 33
5560 19:26:34.623005 CS Dly: 6 (0~37)
5561 19:26:34.625747 ==
5562 19:26:34.629218 Dram Type= 6, Freq= 0, CH_1, rank 1
5563 19:26:34.632368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5564 19:26:34.632776 ==
5565 19:26:34.639415 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5566 19:26:34.642418 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5567 19:26:34.646085 [CA 0] Center 37 (7~68) winsize 62
5568 19:26:34.649804 [CA 1] Center 37 (7~68) winsize 62
5569 19:26:34.652664 [CA 2] Center 35 (5~65) winsize 61
5570 19:26:34.656303 [CA 3] Center 34 (4~65) winsize 62
5571 19:26:34.659668 [CA 4] Center 35 (5~65) winsize 61
5572 19:26:34.662635 [CA 5] Center 33 (3~64) winsize 62
5573 19:26:34.663046
5574 19:26:34.666155 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5575 19:26:34.666579
5576 19:26:34.669533 [CATrainingPosCal] consider 2 rank data
5577 19:26:34.672592 u2DelayCellTimex100 = 270/100 ps
5578 19:26:34.675735 CA0 delay=37 (8~67),Diff = 4 PI (24 cell)
5579 19:26:34.682826 CA1 delay=38 (8~68),Diff = 5 PI (31 cell)
5580 19:26:34.686326 CA2 delay=34 (5~64),Diff = 1 PI (6 cell)
5581 19:26:34.689506 CA3 delay=34 (5~64),Diff = 1 PI (6 cell)
5582 19:26:34.692746 CA4 delay=35 (5~65),Diff = 2 PI (12 cell)
5583 19:26:34.696036 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5584 19:26:34.696217
5585 19:26:34.699155 CA PerBit enable=1, Macro0, CA PI delay=33
5586 19:26:34.699337
5587 19:26:34.703022 [CBTSetCACLKResult] CA Dly = 33
5588 19:26:34.703202 CS Dly: 7 (0~39)
5589 19:26:34.706084
5590 19:26:34.709389 ----->DramcWriteLeveling(PI) begin...
5591 19:26:34.709625 ==
5592 19:26:34.712463 Dram Type= 6, Freq= 0, CH_1, rank 0
5593 19:26:34.716016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5594 19:26:34.716196 ==
5595 19:26:34.718882 Write leveling (Byte 0): 28 => 28
5596 19:26:34.722466 Write leveling (Byte 1): 30 => 30
5597 19:26:34.726093 DramcWriteLeveling(PI) end<-----
5598 19:26:34.726299
5599 19:26:34.726462 ==
5600 19:26:34.728760 Dram Type= 6, Freq= 0, CH_1, rank 0
5601 19:26:34.732599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5602 19:26:34.732780 ==
5603 19:26:34.735437 [Gating] SW mode calibration
5604 19:26:34.742792 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5605 19:26:34.749211 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5606 19:26:34.752199 0 14 0 | B1->B0 | 3131 3232 | 0 0 | (0 0) (0 0)
5607 19:26:34.755834 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5608 19:26:34.762216 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5609 19:26:34.765110 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5610 19:26:34.768614 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5611 19:26:34.775262 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5612 19:26:34.778904 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5613 19:26:34.781772 0 14 28 | B1->B0 | 3030 2e2e | 0 1 | (0 0) (1 1)
5614 19:26:34.788521 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
5615 19:26:34.791860 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5616 19:26:34.795763 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5617 19:26:34.801770 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5618 19:26:34.805111 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5619 19:26:34.808641 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5620 19:26:34.815032 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5621 19:26:34.818189 0 15 28 | B1->B0 | 3636 3333 | 0 1 | (0 0) (1 1)
5622 19:26:34.821747 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5623 19:26:34.828195 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5624 19:26:34.831236 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5625 19:26:34.834706 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5626 19:26:34.841429 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5627 19:26:34.844978 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5628 19:26:34.847858 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5629 19:26:34.854522 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5630 19:26:34.857966 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 19:26:34.860945 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 19:26:34.867539 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 19:26:34.871067 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 19:26:34.874764 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 19:26:34.881362 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 19:26:34.884427 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 19:26:34.887990 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 19:26:34.894333 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 19:26:34.897319 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 19:26:34.900952 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 19:26:34.904395 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 19:26:34.910660 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 19:26:34.914213 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 19:26:34.917493 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 19:26:34.924144 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5646 19:26:34.927133 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5647 19:26:34.930925 Total UI for P1: 0, mck2ui 16
5648 19:26:34.933931 best dqsien dly found for B0: ( 1, 2, 28)
5649 19:26:34.936992 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5650 19:26:34.940685 Total UI for P1: 0, mck2ui 16
5651 19:26:34.943969 best dqsien dly found for B1: ( 1, 2, 30)
5652 19:26:34.947288 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5653 19:26:34.950392 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5654 19:26:34.953730
5655 19:26:34.957158 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5656 19:26:34.960145 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5657 19:26:34.963657 [Gating] SW calibration Done
5658 19:26:34.963741 ==
5659 19:26:34.967040 Dram Type= 6, Freq= 0, CH_1, rank 0
5660 19:26:34.970097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5661 19:26:34.970194 ==
5662 19:26:34.970259 RX Vref Scan: 0
5663 19:26:34.973620
5664 19:26:34.973726 RX Vref 0 -> 0, step: 1
5665 19:26:34.973818
5666 19:26:34.977168 RX Delay -80 -> 252, step: 8
5667 19:26:34.980222 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5668 19:26:34.983743 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5669 19:26:34.990312 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5670 19:26:34.993613 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5671 19:26:34.996931 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5672 19:26:35.000745 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5673 19:26:35.003888 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5674 19:26:35.006893 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5675 19:26:35.013633 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5676 19:26:35.016702 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5677 19:26:35.020437 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5678 19:26:35.023626 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5679 19:26:35.027093 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5680 19:26:35.033633 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5681 19:26:35.036997 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5682 19:26:35.040146 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5683 19:26:35.040562 ==
5684 19:26:35.043471 Dram Type= 6, Freq= 0, CH_1, rank 0
5685 19:26:35.046919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5686 19:26:35.050177 ==
5687 19:26:35.050580 DQS Delay:
5688 19:26:35.050922 DQS0 = 0, DQS1 = 0
5689 19:26:35.053543 DQM Delay:
5690 19:26:35.054000 DQM0 = 95, DQM1 = 87
5691 19:26:35.054331 DQ Delay:
5692 19:26:35.056460 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5693 19:26:35.059998 DQ4 =91, DQ5 =107, DQ6 =107, DQ7 =91
5694 19:26:35.063518 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5695 19:26:35.066347 DQ12 =95, DQ13 =91, DQ14 =91, DQ15 =91
5696 19:26:35.070174
5697 19:26:35.070400
5698 19:26:35.070576 ==
5699 19:26:35.072892 Dram Type= 6, Freq= 0, CH_1, rank 0
5700 19:26:35.076607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5701 19:26:35.076760 ==
5702 19:26:35.076879
5703 19:26:35.076989
5704 19:26:35.079397 TX Vref Scan disable
5705 19:26:35.079583 == TX Byte 0 ==
5706 19:26:35.086550 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5707 19:26:35.089523 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5708 19:26:35.089639 == TX Byte 1 ==
5709 19:26:35.096061 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5710 19:26:35.099644 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5711 19:26:35.099737 ==
5712 19:26:35.102508 Dram Type= 6, Freq= 0, CH_1, rank 0
5713 19:26:35.106051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5714 19:26:35.106137 ==
5715 19:26:35.106203
5716 19:26:35.106265
5717 19:26:35.109354 TX Vref Scan disable
5718 19:26:35.112725 == TX Byte 0 ==
5719 19:26:35.115708 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5720 19:26:35.119370 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5721 19:26:35.122706 == TX Byte 1 ==
5722 19:26:35.125962 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5723 19:26:35.129142 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5724 19:26:35.129224
5725 19:26:35.132170 [DATLAT]
5726 19:26:35.132252 Freq=933, CH1 RK0
5727 19:26:35.132317
5728 19:26:35.135903 DATLAT Default: 0xd
5729 19:26:35.135984 0, 0xFFFF, sum = 0
5730 19:26:35.139262 1, 0xFFFF, sum = 0
5731 19:26:35.139346 2, 0xFFFF, sum = 0
5732 19:26:35.142645 3, 0xFFFF, sum = 0
5733 19:26:35.142728 4, 0xFFFF, sum = 0
5734 19:26:35.146001 5, 0xFFFF, sum = 0
5735 19:26:35.146085 6, 0xFFFF, sum = 0
5736 19:26:35.149286 7, 0xFFFF, sum = 0
5737 19:26:35.149368 8, 0xFFFF, sum = 0
5738 19:26:35.152524 9, 0xFFFF, sum = 0
5739 19:26:35.152605 10, 0x0, sum = 1
5740 19:26:35.155666 11, 0x0, sum = 2
5741 19:26:35.155749 12, 0x0, sum = 3
5742 19:26:35.159141 13, 0x0, sum = 4
5743 19:26:35.159566 best_step = 11
5744 19:26:35.159891
5745 19:26:35.160195 ==
5746 19:26:35.162733 Dram Type= 6, Freq= 0, CH_1, rank 0
5747 19:26:35.169675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5748 19:26:35.170100 ==
5749 19:26:35.170430 RX Vref Scan: 1
5750 19:26:35.170738
5751 19:26:35.172625 RX Vref 0 -> 0, step: 1
5752 19:26:35.173044
5753 19:26:35.176117 RX Delay -61 -> 252, step: 4
5754 19:26:35.176547
5755 19:26:35.179131 Set Vref, RX VrefLevel [Byte0]: 55
5756 19:26:35.182671 [Byte1]: 54
5757 19:26:35.183093
5758 19:26:35.185910 Final RX Vref Byte 0 = 55 to rank0
5759 19:26:35.188903 Final RX Vref Byte 1 = 54 to rank0
5760 19:26:35.192512 Final RX Vref Byte 0 = 55 to rank1
5761 19:26:35.195656 Final RX Vref Byte 1 = 54 to rank1==
5762 19:26:35.199333 Dram Type= 6, Freq= 0, CH_1, rank 0
5763 19:26:35.202259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5764 19:26:35.202678 ==
5765 19:26:35.205765 DQS Delay:
5766 19:26:35.206218 DQS0 = 0, DQS1 = 0
5767 19:26:35.209310 DQM Delay:
5768 19:26:35.209807 DQM0 = 96, DQM1 = 89
5769 19:26:35.210218 DQ Delay:
5770 19:26:35.212203 DQ0 =100, DQ1 =92, DQ2 =84, DQ3 =94
5771 19:26:35.215654 DQ4 =92, DQ5 =106, DQ6 =110, DQ7 =94
5772 19:26:35.219202 DQ8 =78, DQ9 =82, DQ10 =88, DQ11 =82
5773 19:26:35.222016 DQ12 =98, DQ13 =94, DQ14 =96, DQ15 =94
5774 19:26:35.222637
5775 19:26:35.223169
5776 19:26:35.232092 [DQSOSCAuto] RK0, (LSB)MR18= 0xff08, (MSB)MR19= 0x405, tDQSOscB0 = 419 ps tDQSOscB1 = 422 ps
5777 19:26:35.235068 CH1 RK0: MR19=405, MR18=FF08
5778 19:26:35.241781 CH1_RK0: MR19=0x405, MR18=0xFF08, DQSOSC=419, MR23=63, INC=61, DEC=41
5779 19:26:35.241980
5780 19:26:35.245168 ----->DramcWriteLeveling(PI) begin...
5781 19:26:35.245320 ==
5782 19:26:35.248826 Dram Type= 6, Freq= 0, CH_1, rank 1
5783 19:26:35.252472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5784 19:26:35.252893 ==
5785 19:26:35.255436 Write leveling (Byte 0): 26 => 26
5786 19:26:35.258841 Write leveling (Byte 1): 26 => 26
5787 19:26:35.262231 DramcWriteLeveling(PI) end<-----
5788 19:26:35.262647
5789 19:26:35.263004 ==
5790 19:26:35.265658 Dram Type= 6, Freq= 0, CH_1, rank 1
5791 19:26:35.268878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5792 19:26:35.269299 ==
5793 19:26:35.272040 [Gating] SW mode calibration
5794 19:26:35.278503 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5795 19:26:35.284977 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5796 19:26:35.288480 0 14 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
5797 19:26:35.291889 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5798 19:26:35.298404 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5799 19:26:35.302013 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5800 19:26:35.304850 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5801 19:26:35.311316 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5802 19:26:35.314942 0 14 24 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
5803 19:26:35.318306 0 14 28 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5804 19:26:35.324649 0 15 0 | B1->B0 | 2525 2323 | 0 0 | (1 1) (0 0)
5805 19:26:35.327850 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5806 19:26:35.331680 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5807 19:26:35.337833 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5808 19:26:35.341027 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5809 19:26:35.344674 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5810 19:26:35.351056 0 15 24 | B1->B0 | 2727 3232 | 0 0 | (0 0) (0 0)
5811 19:26:35.354457 0 15 28 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
5812 19:26:35.357666 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5813 19:26:35.364529 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5814 19:26:35.368091 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5815 19:26:35.371107 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5816 19:26:35.377483 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5817 19:26:35.380812 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5818 19:26:35.384093 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5819 19:26:35.390652 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5820 19:26:35.394189 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5821 19:26:35.397422 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5822 19:26:35.404320 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5823 19:26:35.407463 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5824 19:26:35.410995 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5825 19:26:35.417663 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5826 19:26:35.421301 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5827 19:26:35.423933 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5828 19:26:35.427549 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 19:26:35.434119 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 19:26:35.437354 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 19:26:35.440811 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 19:26:35.447341 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 19:26:35.450981 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5834 19:26:35.454012 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5835 19:26:35.457368 Total UI for P1: 0, mck2ui 16
5836 19:26:35.460819 best dqsien dly found for B0: ( 1, 2, 20)
5837 19:26:35.467450 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5838 19:26:35.470811 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5839 19:26:35.474216 Total UI for P1: 0, mck2ui 16
5840 19:26:35.477325 best dqsien dly found for B1: ( 1, 2, 28)
5841 19:26:35.480908 best DQS0 dly(MCK, UI, PI) = (1, 2, 20)
5842 19:26:35.483839 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5843 19:26:35.484528
5844 19:26:35.487466 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 20)
5845 19:26:35.490924 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5846 19:26:35.493840 [Gating] SW calibration Done
5847 19:26:35.494537 ==
5848 19:26:35.496900 Dram Type= 6, Freq= 0, CH_1, rank 1
5849 19:26:35.503972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5850 19:26:35.504648 ==
5851 19:26:35.505022 RX Vref Scan: 0
5852 19:26:35.505394
5853 19:26:35.507256 RX Vref 0 -> 0, step: 1
5854 19:26:35.507951
5855 19:26:35.510207 RX Delay -80 -> 252, step: 8
5856 19:26:35.513811 iDelay=208, Bit 0, Center 95 (-8 ~ 199) 208
5857 19:26:35.517488 iDelay=208, Bit 1, Center 87 (-16 ~ 191) 208
5858 19:26:35.520286 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5859 19:26:35.523878 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5860 19:26:35.530257 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5861 19:26:35.533696 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5862 19:26:35.536690 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5863 19:26:35.540324 iDelay=208, Bit 7, Center 87 (-16 ~ 191) 208
5864 19:26:35.543135 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5865 19:26:35.549987 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5866 19:26:35.553386 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5867 19:26:35.556612 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5868 19:26:35.559662 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5869 19:26:35.563468 iDelay=208, Bit 13, Center 95 (-8 ~ 199) 208
5870 19:26:35.569781 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5871 19:26:35.572807 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5872 19:26:35.572907 ==
5873 19:26:35.576172 Dram Type= 6, Freq= 0, CH_1, rank 1
5874 19:26:35.579503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5875 19:26:35.579590 ==
5876 19:26:35.579657 DQS Delay:
5877 19:26:35.583101 DQS0 = 0, DQS1 = 0
5878 19:26:35.583185 DQM Delay:
5879 19:26:35.586153 DQM0 = 92, DQM1 = 90
5880 19:26:35.586235 DQ Delay:
5881 19:26:35.589263 DQ0 =95, DQ1 =87, DQ2 =83, DQ3 =87
5882 19:26:35.592860 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =87
5883 19:26:35.596433 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =83
5884 19:26:35.599424 DQ12 =99, DQ13 =95, DQ14 =99, DQ15 =99
5885 19:26:35.599507
5886 19:26:35.599573
5887 19:26:35.599632 ==
5888 19:26:35.602741 Dram Type= 6, Freq= 0, CH_1, rank 1
5889 19:26:35.606235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5890 19:26:35.609879 ==
5891 19:26:35.609961
5892 19:26:35.610025
5893 19:26:35.610085 TX Vref Scan disable
5894 19:26:35.612784 == TX Byte 0 ==
5895 19:26:35.616173 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5896 19:26:35.619568 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5897 19:26:35.623049 == TX Byte 1 ==
5898 19:26:35.626000 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5899 19:26:35.629275 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5900 19:26:35.632837 ==
5901 19:26:35.636274 Dram Type= 6, Freq= 0, CH_1, rank 1
5902 19:26:35.639130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5903 19:26:35.639234 ==
5904 19:26:35.639315
5905 19:26:35.639389
5906 19:26:35.642638 TX Vref Scan disable
5907 19:26:35.642750 == TX Byte 0 ==
5908 19:26:35.649274 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5909 19:26:35.652668 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5910 19:26:35.652807 == TX Byte 1 ==
5911 19:26:35.659110 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5912 19:26:35.662549 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5913 19:26:35.662726
5914 19:26:35.662864 [DATLAT]
5915 19:26:35.665717 Freq=933, CH1 RK1
5916 19:26:35.665891
5917 19:26:35.666030 DATLAT Default: 0xb
5918 19:26:35.669042 0, 0xFFFF, sum = 0
5919 19:26:35.669342 1, 0xFFFF, sum = 0
5920 19:26:35.672763 2, 0xFFFF, sum = 0
5921 19:26:35.673032 3, 0xFFFF, sum = 0
5922 19:26:35.675830 4, 0xFFFF, sum = 0
5923 19:26:35.679237 5, 0xFFFF, sum = 0
5924 19:26:35.679545 6, 0xFFFF, sum = 0
5925 19:26:35.682746 7, 0xFFFF, sum = 0
5926 19:26:35.683154 8, 0xFFFF, sum = 0
5927 19:26:35.685649 9, 0xFFFF, sum = 0
5928 19:26:35.686055 10, 0x0, sum = 1
5929 19:26:35.689167 11, 0x0, sum = 2
5930 19:26:35.689637 12, 0x0, sum = 3
5931 19:26:35.689985 13, 0x0, sum = 4
5932 19:26:35.692723 best_step = 11
5933 19:26:35.693146
5934 19:26:35.693475 ==
5935 19:26:35.695632 Dram Type= 6, Freq= 0, CH_1, rank 1
5936 19:26:35.699194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5937 19:26:35.699726 ==
5938 19:26:35.702120 RX Vref Scan: 0
5939 19:26:35.702570
5940 19:26:35.705428 RX Vref 0 -> 0, step: 1
5941 19:26:35.706074
5942 19:26:35.706604 RX Delay -69 -> 252, step: 4
5943 19:26:35.713498 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
5944 19:26:35.716501 iDelay=203, Bit 1, Center 86 (-9 ~ 182) 192
5945 19:26:35.719912 iDelay=203, Bit 2, Center 82 (-13 ~ 178) 192
5946 19:26:35.723609 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5947 19:26:35.726787 iDelay=203, Bit 4, Center 90 (-5 ~ 186) 192
5948 19:26:35.733456 iDelay=203, Bit 5, Center 102 (7 ~ 198) 192
5949 19:26:35.736558 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5950 19:26:35.739849 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
5951 19:26:35.742961 iDelay=203, Bit 8, Center 80 (-13 ~ 174) 188
5952 19:26:35.746374 iDelay=203, Bit 9, Center 82 (-9 ~ 174) 184
5953 19:26:35.750005 iDelay=203, Bit 10, Center 92 (-5 ~ 190) 196
5954 19:26:35.756444 iDelay=203, Bit 11, Center 86 (-5 ~ 178) 184
5955 19:26:35.759376 iDelay=203, Bit 12, Center 98 (7 ~ 190) 184
5956 19:26:35.763093 iDelay=203, Bit 13, Center 100 (7 ~ 194) 188
5957 19:26:35.766074 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5958 19:26:35.769556 iDelay=203, Bit 15, Center 98 (3 ~ 194) 192
5959 19:26:35.769988 ==
5960 19:26:35.772573 Dram Type= 6, Freq= 0, CH_1, rank 1
5961 19:26:35.779569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5962 19:26:35.780131 ==
5963 19:26:35.780633 DQS Delay:
5964 19:26:35.782643 DQS0 = 0, DQS1 = 0
5965 19:26:35.782946 DQM Delay:
5966 19:26:35.783185 DQM0 = 92, DQM1 = 91
5967 19:26:35.786363 DQ Delay:
5968 19:26:35.789419 DQ0 =96, DQ1 =86, DQ2 =82, DQ3 =88
5969 19:26:35.792676 DQ4 =90, DQ5 =102, DQ6 =104, DQ7 =88
5970 19:26:35.796046 DQ8 =80, DQ9 =82, DQ10 =92, DQ11 =86
5971 19:26:35.799541 DQ12 =98, DQ13 =100, DQ14 =98, DQ15 =98
5972 19:26:35.799697
5973 19:26:35.799816
5974 19:26:35.806125 [DQSOSCAuto] RK1, (LSB)MR18= 0xc20, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 418 ps
5975 19:26:35.809503 CH1 RK1: MR19=505, MR18=C20
5976 19:26:35.815775 CH1_RK1: MR19=0x505, MR18=0xC20, DQSOSC=411, MR23=63, INC=64, DEC=42
5977 19:26:35.819396 [RxdqsGatingPostProcess] freq 933
5978 19:26:35.822708 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5979 19:26:35.825782 best DQS0 dly(2T, 0.5T) = (0, 10)
5980 19:26:35.829356 best DQS1 dly(2T, 0.5T) = (0, 10)
5981 19:26:35.832352 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5982 19:26:35.836021 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5983 19:26:35.839053 best DQS0 dly(2T, 0.5T) = (0, 10)
5984 19:26:35.842324 best DQS1 dly(2T, 0.5T) = (0, 10)
5985 19:26:35.845628 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5986 19:26:35.849316 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5987 19:26:35.852501 Pre-setting of DQS Precalculation
5988 19:26:35.855835 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5989 19:26:35.865745 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5990 19:26:35.872296 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5991 19:26:35.872390
5992 19:26:35.872455
5993 19:26:35.875359 [Calibration Summary] 1866 Mbps
5994 19:26:35.875443 CH 0, Rank 0
5995 19:26:35.878901 SW Impedance : PASS
5996 19:26:35.878991 DUTY Scan : NO K
5997 19:26:35.882368 ZQ Calibration : PASS
5998 19:26:35.885233 Jitter Meter : NO K
5999 19:26:35.885315 CBT Training : PASS
6000 19:26:35.888769 Write leveling : PASS
6001 19:26:35.892040 RX DQS gating : PASS
6002 19:26:35.892126 RX DQ/DQS(RDDQC) : PASS
6003 19:26:35.895217 TX DQ/DQS : PASS
6004 19:26:35.898534 RX DATLAT : PASS
6005 19:26:35.898618 RX DQ/DQS(Engine): PASS
6006 19:26:35.902196 TX OE : NO K
6007 19:26:35.902278 All Pass.
6008 19:26:35.902343
6009 19:26:35.905750 CH 0, Rank 1
6010 19:26:35.905833 SW Impedance : PASS
6011 19:26:35.908698 DUTY Scan : NO K
6012 19:26:35.912225 ZQ Calibration : PASS
6013 19:26:35.912320 Jitter Meter : NO K
6014 19:26:35.915130 CBT Training : PASS
6015 19:26:35.918481 Write leveling : PASS
6016 19:26:35.918663 RX DQS gating : PASS
6017 19:26:35.921768 RX DQ/DQS(RDDQC) : PASS
6018 19:26:35.921944 TX DQ/DQS : PASS
6019 19:26:35.925189 RX DATLAT : PASS
6020 19:26:35.928768 RX DQ/DQS(Engine): PASS
6021 19:26:35.928928 TX OE : NO K
6022 19:26:35.932261 All Pass.
6023 19:26:35.932478
6024 19:26:35.932610 CH 1, Rank 0
6025 19:26:35.935313 SW Impedance : PASS
6026 19:26:35.935530 DUTY Scan : NO K
6027 19:26:35.938299 ZQ Calibration : PASS
6028 19:26:35.941717 Jitter Meter : NO K
6029 19:26:35.941891 CBT Training : PASS
6030 19:26:35.945409 Write leveling : PASS
6031 19:26:35.948303 RX DQS gating : PASS
6032 19:26:35.948504 RX DQ/DQS(RDDQC) : PASS
6033 19:26:35.951675 TX DQ/DQS : PASS
6034 19:26:35.954948 RX DATLAT : PASS
6035 19:26:35.955192 RX DQ/DQS(Engine): PASS
6036 19:26:35.958350 TX OE : NO K
6037 19:26:35.958658 All Pass.
6038 19:26:35.958895
6039 19:26:35.961997 CH 1, Rank 1
6040 19:26:35.962391 SW Impedance : PASS
6041 19:26:35.965224 DUTY Scan : NO K
6042 19:26:35.968485 ZQ Calibration : PASS
6043 19:26:35.969069 Jitter Meter : NO K
6044 19:26:35.972230 CBT Training : PASS
6045 19:26:35.975090 Write leveling : PASS
6046 19:26:35.975562 RX DQS gating : PASS
6047 19:26:35.978376 RX DQ/DQS(RDDQC) : PASS
6048 19:26:35.981599 TX DQ/DQS : PASS
6049 19:26:35.982073 RX DATLAT : PASS
6050 19:26:35.985182 RX DQ/DQS(Engine): PASS
6051 19:26:35.985804 TX OE : NO K
6052 19:26:35.988279 All Pass.
6053 19:26:35.988747
6054 19:26:35.989110 DramC Write-DBI off
6055 19:26:35.991561 PER_BANK_REFRESH: Hybrid Mode
6056 19:26:35.995107 TX_TRACKING: ON
6057 19:26:36.001576 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6058 19:26:36.004886 [FAST_K] Save calibration result to emmc
6059 19:26:36.011508 dramc_set_vcore_voltage set vcore to 650000
6060 19:26:36.012164 Read voltage for 400, 6
6061 19:26:36.012770 Vio18 = 0
6062 19:26:36.014799 Vcore = 650000
6063 19:26:36.015458 Vdram = 0
6064 19:26:36.015933 Vddq = 0
6065 19:26:36.018031 Vmddr = 0
6066 19:26:36.021045 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6067 19:26:36.027601 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6068 19:26:36.031013 MEM_TYPE=3, freq_sel=20
6069 19:26:36.031429 sv_algorithm_assistance_LP4_800
6070 19:26:36.037458 ============ PULL DRAM RESETB DOWN ============
6071 19:26:36.041056 ========== PULL DRAM RESETB DOWN end =========
6072 19:26:36.044099 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6073 19:26:36.047486 ===================================
6074 19:26:36.051095 LPDDR4 DRAM CONFIGURATION
6075 19:26:36.054094 ===================================
6076 19:26:36.057441 EX_ROW_EN[0] = 0x0
6077 19:26:36.057573 EX_ROW_EN[1] = 0x0
6078 19:26:36.060609 LP4Y_EN = 0x0
6079 19:26:36.060734 WORK_FSP = 0x0
6080 19:26:36.063856 WL = 0x2
6081 19:26:36.063955 RL = 0x2
6082 19:26:36.067355 BL = 0x2
6083 19:26:36.067442 RPST = 0x0
6084 19:26:36.070825 RD_PRE = 0x0
6085 19:26:36.070912 WR_PRE = 0x1
6086 19:26:36.074248 WR_PST = 0x0
6087 19:26:36.074334 DBI_WR = 0x0
6088 19:26:36.077464 DBI_RD = 0x0
6089 19:26:36.077584 OTF = 0x1
6090 19:26:36.080598 ===================================
6091 19:26:36.084021 ===================================
6092 19:26:36.087060 ANA top config
6093 19:26:36.090556 ===================================
6094 19:26:36.094092 DLL_ASYNC_EN = 0
6095 19:26:36.094175 ALL_SLAVE_EN = 1
6096 19:26:36.096980 NEW_RANK_MODE = 1
6097 19:26:36.100567 DLL_IDLE_MODE = 1
6098 19:26:36.104278 LP45_APHY_COMB_EN = 1
6099 19:26:36.107870 TX_ODT_DIS = 1
6100 19:26:36.108647 NEW_8X_MODE = 1
6101 19:26:36.110711 ===================================
6102 19:26:36.114325 ===================================
6103 19:26:36.117303 data_rate = 800
6104 19:26:36.120593 CKR = 1
6105 19:26:36.124039 DQ_P2S_RATIO = 4
6106 19:26:36.127291 ===================================
6107 19:26:36.130596 CA_P2S_RATIO = 4
6108 19:26:36.133970 DQ_CA_OPEN = 0
6109 19:26:36.134409 DQ_SEMI_OPEN = 1
6110 19:26:36.137188 CA_SEMI_OPEN = 1
6111 19:26:36.140730 CA_FULL_RATE = 0
6112 19:26:36.143822 DQ_CKDIV4_EN = 0
6113 19:26:36.147342 CA_CKDIV4_EN = 1
6114 19:26:36.147801 CA_PREDIV_EN = 0
6115 19:26:36.150443 PH8_DLY = 0
6116 19:26:36.153897 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6117 19:26:36.156959 DQ_AAMCK_DIV = 0
6118 19:26:36.160723 CA_AAMCK_DIV = 0
6119 19:26:36.163429 CA_ADMCK_DIV = 4
6120 19:26:36.166820 DQ_TRACK_CA_EN = 0
6121 19:26:36.167251 CA_PICK = 800
6122 19:26:36.170608 CA_MCKIO = 400
6123 19:26:36.246107 MCKIO_SEMI = 400
6124 19:26:36.246969 PLL_FREQ = 3016
6125 19:26:36.247332 DQ_UI_PI_RATIO = 32
6126 19:26:36.247651 CA_UI_PI_RATIO = 32
6127 19:26:36.247952 ===================================
6128 19:26:36.248243 ===================================
6129 19:26:36.248527 memory_type:LPDDR4
6130 19:26:36.248811 GP_NUM : 10
6131 19:26:36.249088 SRAM_EN : 1
6132 19:26:36.249426 MD32_EN : 0
6133 19:26:36.249845 ===================================
6134 19:26:36.250133 [ANA_INIT] >>>>>>>>>>>>>>
6135 19:26:36.250415 <<<<<< [CONFIGURE PHASE]: ANA_TX
6136 19:26:36.250700 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6137 19:26:36.250978 ===================================
6138 19:26:36.251253 data_rate = 800,PCW = 0X7400
6139 19:26:36.251529 ===================================
6140 19:26:36.251803 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6141 19:26:36.252075 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6142 19:26:36.252451 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6143 19:26:36.252803 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6144 19:26:36.253082 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6145 19:26:36.253417 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6146 19:26:36.253759 [ANA_INIT] flow start
6147 19:26:36.256407 [ANA_INIT] PLL >>>>>>>>
6148 19:26:36.256825 [ANA_INIT] PLL <<<<<<<<
6149 19:26:36.259930 [ANA_INIT] MIDPI >>>>>>>>
6150 19:26:36.262921 [ANA_INIT] MIDPI <<<<<<<<
6151 19:26:36.266504 [ANA_INIT] DLL >>>>>>>>
6152 19:26:36.266919 [ANA_INIT] flow end
6153 19:26:36.269552 ============ LP4 DIFF to SE enter ============
6154 19:26:36.276153 ============ LP4 DIFF to SE exit ============
6155 19:26:36.276453 [ANA_INIT] <<<<<<<<<<<<<
6156 19:26:36.279350 [Flow] Enable top DCM control >>>>>
6157 19:26:36.282580 [Flow] Enable top DCM control <<<<<
6158 19:26:36.285960 Enable DLL master slave shuffle
6159 19:26:36.292839 ==============================================================
6160 19:26:36.292925 Gating Mode config
6161 19:26:36.298937 ==============================================================
6162 19:26:36.302546 Config description:
6163 19:26:36.309079 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6164 19:26:36.315842 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6165 19:26:36.322255 SELPH_MODE 0: By rank 1: By Phase
6166 19:26:36.328857 ==============================================================
6167 19:26:36.332299 GAT_TRACK_EN = 0
6168 19:26:36.332421 RX_GATING_MODE = 2
6169 19:26:36.335817 RX_GATING_TRACK_MODE = 2
6170 19:26:36.339285 SELPH_MODE = 1
6171 19:26:36.341938 PICG_EARLY_EN = 1
6172 19:26:36.345738 VALID_LAT_VALUE = 1
6173 19:26:36.352176 ==============================================================
6174 19:26:36.355401 Enter into Gating configuration >>>>
6175 19:26:36.359029 Exit from Gating configuration <<<<
6176 19:26:36.362280 Enter into DVFS_PRE_config >>>>>
6177 19:26:36.372739 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6178 19:26:36.375611 Exit from DVFS_PRE_config <<<<<
6179 19:26:36.378940 Enter into PICG configuration >>>>
6180 19:26:36.382625 Exit from PICG configuration <<<<
6181 19:26:36.385478 [RX_INPUT] configuration >>>>>
6182 19:26:36.388937 [RX_INPUT] configuration <<<<<
6183 19:26:36.392335 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6184 19:26:36.398425 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6185 19:26:36.405562 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6186 19:26:36.411946 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6187 19:26:36.415637 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6188 19:26:36.421723 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6189 19:26:36.425304 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6190 19:26:36.431618 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6191 19:26:36.435057 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6192 19:26:36.438445 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6193 19:26:36.441358 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6194 19:26:36.448249 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6195 19:26:36.451510 ===================================
6196 19:26:36.451742 LPDDR4 DRAM CONFIGURATION
6197 19:26:36.454637 ===================================
6198 19:26:36.458124 EX_ROW_EN[0] = 0x0
6199 19:26:36.461291 EX_ROW_EN[1] = 0x0
6200 19:26:36.461556 LP4Y_EN = 0x0
6201 19:26:36.464705 WORK_FSP = 0x0
6202 19:26:36.465001 WL = 0x2
6203 19:26:36.468214 RL = 0x2
6204 19:26:36.468438 BL = 0x2
6205 19:26:36.471146 RPST = 0x0
6206 19:26:36.471368 RD_PRE = 0x0
6207 19:26:36.474670 WR_PRE = 0x1
6208 19:26:36.474893 WR_PST = 0x0
6209 19:26:36.478346 DBI_WR = 0x0
6210 19:26:36.478569 DBI_RD = 0x0
6211 19:26:36.481306 OTF = 0x1
6212 19:26:36.484664 ===================================
6213 19:26:36.487928 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6214 19:26:36.491453 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6215 19:26:36.497884 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6216 19:26:36.501122 ===================================
6217 19:26:36.501660 LPDDR4 DRAM CONFIGURATION
6218 19:26:36.504820 ===================================
6219 19:26:36.508002 EX_ROW_EN[0] = 0x10
6220 19:26:36.511268 EX_ROW_EN[1] = 0x0
6221 19:26:36.511717 LP4Y_EN = 0x0
6222 19:26:36.514554 WORK_FSP = 0x0
6223 19:26:36.514980 WL = 0x2
6224 19:26:36.517583 RL = 0x2
6225 19:26:36.518011 BL = 0x2
6226 19:26:36.521174 RPST = 0x0
6227 19:26:36.521668 RD_PRE = 0x0
6228 19:26:36.524160 WR_PRE = 0x1
6229 19:26:36.524585 WR_PST = 0x0
6230 19:26:36.527675 DBI_WR = 0x0
6231 19:26:36.528099 DBI_RD = 0x0
6232 19:26:36.531100 OTF = 0x1
6233 19:26:36.534114 ===================================
6234 19:26:36.540974 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6235 19:26:36.543909 nWR fixed to 30
6236 19:26:36.547542 [ModeRegInit_LP4] CH0 RK0
6237 19:26:36.547965 [ModeRegInit_LP4] CH0 RK1
6238 19:26:36.550595 [ModeRegInit_LP4] CH1 RK0
6239 19:26:36.554028 [ModeRegInit_LP4] CH1 RK1
6240 19:26:36.554529 match AC timing 19
6241 19:26:36.560422 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6242 19:26:36.563823 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6243 19:26:36.567434 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6244 19:26:36.573729 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6245 19:26:36.577222 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6246 19:26:36.577757 ==
6247 19:26:36.580749 Dram Type= 6, Freq= 0, CH_0, rank 0
6248 19:26:36.583890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6249 19:26:36.584462 ==
6250 19:26:36.590337 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6251 19:26:36.597572 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6252 19:26:36.600524 [CA 0] Center 36 (8~64) winsize 57
6253 19:26:36.603505 [CA 1] Center 36 (8~64) winsize 57
6254 19:26:36.606968 [CA 2] Center 36 (8~64) winsize 57
6255 19:26:36.610223 [CA 3] Center 36 (8~64) winsize 57
6256 19:26:36.610650 [CA 4] Center 36 (8~64) winsize 57
6257 19:26:36.613743 [CA 5] Center 36 (8~64) winsize 57
6258 19:26:36.614172
6259 19:26:36.620486 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6260 19:26:36.620913
6261 19:26:36.623497 [CATrainingPosCal] consider 1 rank data
6262 19:26:36.627131 u2DelayCellTimex100 = 270/100 ps
6263 19:26:36.630732 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6264 19:26:36.633574 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6265 19:26:36.636978 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6266 19:26:36.639890 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6267 19:26:36.643537 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6268 19:26:36.646934 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6269 19:26:36.647402
6270 19:26:36.650105 CA PerBit enable=1, Macro0, CA PI delay=36
6271 19:26:36.650599
6272 19:26:36.653370 [CBTSetCACLKResult] CA Dly = 36
6273 19:26:36.656452 CS Dly: 1 (0~32)
6274 19:26:36.656933 ==
6275 19:26:36.660051 Dram Type= 6, Freq= 0, CH_0, rank 1
6276 19:26:36.663572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6277 19:26:36.663998 ==
6278 19:26:36.669891 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6279 19:26:36.676546 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6280 19:26:36.677035 [CA 0] Center 36 (8~64) winsize 57
6281 19:26:36.679833 [CA 1] Center 36 (8~64) winsize 57
6282 19:26:36.683381 [CA 2] Center 36 (8~64) winsize 57
6283 19:26:36.686857 [CA 3] Center 36 (8~64) winsize 57
6284 19:26:36.689655 [CA 4] Center 36 (8~64) winsize 57
6285 19:26:36.693154 [CA 5] Center 36 (8~64) winsize 57
6286 19:26:36.693606
6287 19:26:36.696938 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6288 19:26:36.697448
6289 19:26:36.700143 [CATrainingPosCal] consider 2 rank data
6290 19:26:36.702943 u2DelayCellTimex100 = 270/100 ps
6291 19:26:36.706475 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6292 19:26:36.712843 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6293 19:26:36.716222 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6294 19:26:36.719614 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6295 19:26:36.722894 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6296 19:26:36.726111 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6297 19:26:36.726757
6298 19:26:36.729359 CA PerBit enable=1, Macro0, CA PI delay=36
6299 19:26:36.729946
6300 19:26:36.732856 [CBTSetCACLKResult] CA Dly = 36
6301 19:26:36.736151 CS Dly: 1 (0~32)
6302 19:26:36.736576
6303 19:26:36.739118 ----->DramcWriteLeveling(PI) begin...
6304 19:26:36.739552 ==
6305 19:26:36.742591 Dram Type= 6, Freq= 0, CH_0, rank 0
6306 19:26:36.746285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6307 19:26:36.746713 ==
6308 19:26:36.749552 Write leveling (Byte 0): 40 => 8
6309 19:26:36.752867 Write leveling (Byte 1): 40 => 8
6310 19:26:36.756108 DramcWriteLeveling(PI) end<-----
6311 19:26:36.756531
6312 19:26:36.756861 ==
6313 19:26:36.759648 Dram Type= 6, Freq= 0, CH_0, rank 0
6314 19:26:36.762413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6315 19:26:36.762841 ==
6316 19:26:36.765844 [Gating] SW mode calibration
6317 19:26:36.772480 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6318 19:26:36.779215 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6319 19:26:36.782699 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6320 19:26:36.785532 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6321 19:26:36.792452 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6322 19:26:36.795590 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6323 19:26:36.799008 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6324 19:26:36.805703 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6325 19:26:36.808979 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6326 19:26:36.812439 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6327 19:26:36.818998 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6328 19:26:36.819425 Total UI for P1: 0, mck2ui 16
6329 19:26:36.825501 best dqsien dly found for B0: ( 0, 14, 24)
6330 19:26:36.825972 Total UI for P1: 0, mck2ui 16
6331 19:26:36.828966 best dqsien dly found for B1: ( 0, 14, 24)
6332 19:26:36.835785 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6333 19:26:36.838557 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6334 19:26:36.838979
6335 19:26:36.841784 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6336 19:26:36.845428 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6337 19:26:36.848815 [Gating] SW calibration Done
6338 19:26:36.849149 ==
6339 19:26:36.851784 Dram Type= 6, Freq= 0, CH_0, rank 0
6340 19:26:36.855260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6341 19:26:36.855488 ==
6342 19:26:36.858867 RX Vref Scan: 0
6343 19:26:36.859154
6344 19:26:36.859332 RX Vref 0 -> 0, step: 1
6345 19:26:36.859499
6346 19:26:36.861883 RX Delay -410 -> 252, step: 16
6347 19:26:36.868646 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6348 19:26:36.872385 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6349 19:26:36.875147 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6350 19:26:36.878676 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6351 19:26:36.885292 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6352 19:26:36.888348 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6353 19:26:36.892057 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6354 19:26:36.895074 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6355 19:26:36.902083 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6356 19:26:36.905305 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6357 19:26:36.908373 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6358 19:26:36.911580 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6359 19:26:36.918286 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6360 19:26:36.921592 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6361 19:26:36.924604 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6362 19:26:36.928194 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6363 19:26:36.931372 ==
6364 19:26:36.935005 Dram Type= 6, Freq= 0, CH_0, rank 0
6365 19:26:36.937902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6366 19:26:36.938379 ==
6367 19:26:36.938794 DQS Delay:
6368 19:26:36.941234 DQS0 = 59, DQS1 = 59
6369 19:26:36.941893 DQM Delay:
6370 19:26:36.945046 DQM0 = 18, DQM1 = 9
6371 19:26:36.945541 DQ Delay:
6372 19:26:36.947861 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6373 19:26:36.951370 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6374 19:26:36.954528 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6375 19:26:36.957734 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6376 19:26:36.958402
6377 19:26:36.958861
6378 19:26:36.959303 ==
6379 19:26:36.961423 Dram Type= 6, Freq= 0, CH_0, rank 0
6380 19:26:36.964567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6381 19:26:36.964984 ==
6382 19:26:36.965310
6383 19:26:36.965659
6384 19:26:36.968178 TX Vref Scan disable
6385 19:26:36.968595 == TX Byte 0 ==
6386 19:26:36.974424 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6387 19:26:36.977697 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6388 19:26:36.978115 == TX Byte 1 ==
6389 19:26:36.984315 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6390 19:26:36.987869 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6391 19:26:36.988300 ==
6392 19:26:36.991413 Dram Type= 6, Freq= 0, CH_0, rank 0
6393 19:26:36.994481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6394 19:26:36.994965 ==
6395 19:26:36.995293
6396 19:26:36.995596
6397 19:26:36.997959 TX Vref Scan disable
6398 19:26:36.998376 == TX Byte 0 ==
6399 19:26:37.004343 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6400 19:26:37.008282 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6401 19:26:37.008797 == TX Byte 1 ==
6402 19:26:37.014789 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6403 19:26:37.017738 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6404 19:26:37.018156
6405 19:26:37.018483 [DATLAT]
6406 19:26:37.021301 Freq=400, CH0 RK0
6407 19:26:37.021763
6408 19:26:37.022092 DATLAT Default: 0xf
6409 19:26:37.024646 0, 0xFFFF, sum = 0
6410 19:26:37.025070 1, 0xFFFF, sum = 0
6411 19:26:37.027837 2, 0xFFFF, sum = 0
6412 19:26:37.028448 3, 0xFFFF, sum = 0
6413 19:26:37.031203 4, 0xFFFF, sum = 0
6414 19:26:37.031724 5, 0xFFFF, sum = 0
6415 19:26:37.034186 6, 0xFFFF, sum = 0
6416 19:26:37.034610 7, 0xFFFF, sum = 0
6417 19:26:37.037677 8, 0xFFFF, sum = 0
6418 19:26:37.040994 9, 0xFFFF, sum = 0
6419 19:26:37.041418 10, 0xFFFF, sum = 0
6420 19:26:37.044054 11, 0xFFFF, sum = 0
6421 19:26:37.044480 12, 0xFFFF, sum = 0
6422 19:26:37.047871 13, 0x0, sum = 1
6423 19:26:37.048416 14, 0x0, sum = 2
6424 19:26:37.050874 15, 0x0, sum = 3
6425 19:26:37.051301 16, 0x0, sum = 4
6426 19:26:37.051639 best_step = 14
6427 19:26:37.052032
6428 19:26:37.054163 ==
6429 19:26:37.057206 Dram Type= 6, Freq= 0, CH_0, rank 0
6430 19:26:37.060909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6431 19:26:37.061333 ==
6432 19:26:37.061724 RX Vref Scan: 1
6433 19:26:37.062064
6434 19:26:37.064402 RX Vref 0 -> 0, step: 1
6435 19:26:37.064821
6436 19:26:37.067654 RX Delay -359 -> 252, step: 8
6437 19:26:37.068075
6438 19:26:37.070721 Set Vref, RX VrefLevel [Byte0]: 60
6439 19:26:37.073934 [Byte1]: 54
6440 19:26:37.077844
6441 19:26:37.078262 Final RX Vref Byte 0 = 60 to rank0
6442 19:26:37.081318 Final RX Vref Byte 1 = 54 to rank0
6443 19:26:37.084737 Final RX Vref Byte 0 = 60 to rank1
6444 19:26:37.087729 Final RX Vref Byte 1 = 54 to rank1==
6445 19:26:37.091249 Dram Type= 6, Freq= 0, CH_0, rank 0
6446 19:26:37.098088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6447 19:26:37.098675 ==
6448 19:26:37.099013 DQS Delay:
6449 19:26:37.101000 DQS0 = 60, DQS1 = 68
6450 19:26:37.101605 DQM Delay:
6451 19:26:37.101996 DQM0 = 14, DQM1 = 14
6452 19:26:37.104409 DQ Delay:
6453 19:26:37.107929 DQ0 =12, DQ1 =16, DQ2 =12, DQ3 =12
6454 19:26:37.110923 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6455 19:26:37.111512 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6456 19:26:37.117349 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6457 19:26:37.117961
6458 19:26:37.118314
6459 19:26:37.124249 [DQSOSCAuto] RK0, (LSB)MR18= 0x8381, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6460 19:26:37.127691 CH0 RK0: MR19=C0C, MR18=8381
6461 19:26:37.134330 CH0_RK0: MR19=0xC0C, MR18=0x8381, DQSOSC=393, MR23=63, INC=382, DEC=254
6462 19:26:37.134761 ==
6463 19:26:37.137423 Dram Type= 6, Freq= 0, CH_0, rank 1
6464 19:26:37.141162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6465 19:26:37.141631 ==
6466 19:26:37.144274 [Gating] SW mode calibration
6467 19:26:37.150879 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6468 19:26:37.157673 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6469 19:26:37.160604 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6470 19:26:37.164165 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6471 19:26:37.170416 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6472 19:26:37.173975 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6473 19:26:37.177282 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6474 19:26:37.183806 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6475 19:26:37.187119 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6476 19:26:37.190390 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6477 19:26:37.197000 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6478 19:26:37.197614 Total UI for P1: 0, mck2ui 16
6479 19:26:37.204162 best dqsien dly found for B0: ( 0, 14, 24)
6480 19:26:37.204709 Total UI for P1: 0, mck2ui 16
6481 19:26:37.207104 best dqsien dly found for B1: ( 0, 14, 24)
6482 19:26:37.213682 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6483 19:26:37.217336 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6484 19:26:37.217927
6485 19:26:37.220322 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6486 19:26:37.223321 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6487 19:26:37.226944 [Gating] SW calibration Done
6488 19:26:37.227414 ==
6489 19:26:37.229950 Dram Type= 6, Freq= 0, CH_0, rank 1
6490 19:26:37.233582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6491 19:26:37.234126 ==
6492 19:26:37.236603 RX Vref Scan: 0
6493 19:26:37.237132
6494 19:26:37.237497 RX Vref 0 -> 0, step: 1
6495 19:26:37.237957
6496 19:26:37.240228 RX Delay -410 -> 252, step: 16
6497 19:26:37.246508 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6498 19:26:37.250024 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6499 19:26:37.253595 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6500 19:26:37.256395 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6501 19:26:37.263262 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6502 19:26:37.266630 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6503 19:26:37.269908 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6504 19:26:37.273052 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6505 19:26:37.280066 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6506 19:26:37.283046 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6507 19:26:37.286178 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6508 19:26:37.289570 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6509 19:26:37.296144 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6510 19:26:37.299415 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6511 19:26:37.302856 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6512 19:26:37.306191 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6513 19:26:37.309482 ==
6514 19:26:37.313033 Dram Type= 6, Freq= 0, CH_0, rank 1
6515 19:26:37.315828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6516 19:26:37.316266 ==
6517 19:26:37.316600 DQS Delay:
6518 19:26:37.319476 DQS0 = 59, DQS1 = 59
6519 19:26:37.319902 DQM Delay:
6520 19:26:37.322617 DQM0 = 17, DQM1 = 10
6521 19:26:37.323037 DQ Delay:
6522 19:26:37.326166 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6523 19:26:37.329251 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =32
6524 19:26:37.333011 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6525 19:26:37.335996 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6526 19:26:37.336508
6527 19:26:37.336842
6528 19:26:37.337151 ==
6529 19:26:37.339552 Dram Type= 6, Freq= 0, CH_0, rank 1
6530 19:26:37.342562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6531 19:26:37.342986 ==
6532 19:26:37.343319
6533 19:26:37.343628
6534 19:26:37.345552 TX Vref Scan disable
6535 19:26:37.349129 == TX Byte 0 ==
6536 19:26:37.352459 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6537 19:26:37.355980 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6538 19:26:37.358724 == TX Byte 1 ==
6539 19:26:37.362167 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6540 19:26:37.365502 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6541 19:26:37.366019 ==
6542 19:26:37.368980 Dram Type= 6, Freq= 0, CH_0, rank 1
6543 19:26:37.372595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6544 19:26:37.373029 ==
6545 19:26:37.373407
6546 19:26:37.375448
6547 19:26:37.375870 TX Vref Scan disable
6548 19:26:37.378867 == TX Byte 0 ==
6549 19:26:37.382350 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6550 19:26:37.385320 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6551 19:26:37.388622 == TX Byte 1 ==
6552 19:26:37.391846 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6553 19:26:37.395142 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6554 19:26:37.395611
6555 19:26:37.395954 [DATLAT]
6556 19:26:37.398438 Freq=400, CH0 RK1
6557 19:26:37.398865
6558 19:26:37.399248 DATLAT Default: 0xe
6559 19:26:37.402055 0, 0xFFFF, sum = 0
6560 19:26:37.404841 1, 0xFFFF, sum = 0
6561 19:26:37.405269 2, 0xFFFF, sum = 0
6562 19:26:37.408655 3, 0xFFFF, sum = 0
6563 19:26:37.409085 4, 0xFFFF, sum = 0
6564 19:26:37.411999 5, 0xFFFF, sum = 0
6565 19:26:37.412468 6, 0xFFFF, sum = 0
6566 19:26:37.415543 7, 0xFFFF, sum = 0
6567 19:26:37.415973 8, 0xFFFF, sum = 0
6568 19:26:37.418558 9, 0xFFFF, sum = 0
6569 19:26:37.418989 10, 0xFFFF, sum = 0
6570 19:26:37.421471 11, 0xFFFF, sum = 0
6571 19:26:37.421957 12, 0xFFFF, sum = 0
6572 19:26:37.424987 13, 0x0, sum = 1
6573 19:26:37.425411 14, 0x0, sum = 2
6574 19:26:37.428607 15, 0x0, sum = 3
6575 19:26:37.429125 16, 0x0, sum = 4
6576 19:26:37.431599 best_step = 14
6577 19:26:37.432017
6578 19:26:37.432345 ==
6579 19:26:37.435168 Dram Type= 6, Freq= 0, CH_0, rank 1
6580 19:26:37.438293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6581 19:26:37.438716 ==
6582 19:26:37.441256 RX Vref Scan: 0
6583 19:26:37.441739
6584 19:26:37.442141 RX Vref 0 -> 0, step: 1
6585 19:26:37.442466
6586 19:26:37.444849 RX Delay -359 -> 252, step: 8
6587 19:26:37.452513 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6588 19:26:37.455941 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6589 19:26:37.459193 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6590 19:26:37.462852 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6591 19:26:37.469069 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6592 19:26:37.472385 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6593 19:26:37.475938 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6594 19:26:37.478968 iDelay=217, Bit 7, Center -40 (-295 ~ 216) 512
6595 19:26:37.485991 iDelay=217, Bit 8, Center -60 (-311 ~ 192) 504
6596 19:26:37.489014 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6597 19:26:37.492562 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6598 19:26:37.499143 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6599 19:26:37.502887 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6600 19:26:37.505595 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6601 19:26:37.509342 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6602 19:26:37.515751 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6603 19:26:37.516213 ==
6604 19:26:37.519053 Dram Type= 6, Freq= 0, CH_0, rank 1
6605 19:26:37.522038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6606 19:26:37.522465 ==
6607 19:26:37.522797 DQS Delay:
6608 19:26:37.525405 DQS0 = 60, DQS1 = 72
6609 19:26:37.525858 DQM Delay:
6610 19:26:37.528697 DQM0 = 11, DQM1 = 18
6611 19:26:37.529116 DQ Delay:
6612 19:26:37.531975 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6613 19:26:37.535268 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =20
6614 19:26:37.538675 DQ8 =12, DQ9 =0, DQ10 =20, DQ11 =12
6615 19:26:37.542387 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =24
6616 19:26:37.542810
6617 19:26:37.543138
6618 19:26:37.548897 [DQSOSCAuto] RK1, (LSB)MR18= 0xcc82, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 384 ps
6619 19:26:37.551847 CH0 RK1: MR19=C0C, MR18=CC82
6620 19:26:37.558958 CH0_RK1: MR19=0xC0C, MR18=0xCC82, DQSOSC=384, MR23=63, INC=400, DEC=267
6621 19:26:37.561776 [RxdqsGatingPostProcess] freq 400
6622 19:26:37.568467 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6623 19:26:37.571963 best DQS0 dly(2T, 0.5T) = (0, 10)
6624 19:26:37.575187 best DQS1 dly(2T, 0.5T) = (0, 10)
6625 19:26:37.578273 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6626 19:26:37.578703 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6627 19:26:37.581457 best DQS0 dly(2T, 0.5T) = (0, 10)
6628 19:26:37.584901 best DQS1 dly(2T, 0.5T) = (0, 10)
6629 19:26:37.588481 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6630 19:26:37.592134 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6631 19:26:37.594974 Pre-setting of DQS Precalculation
6632 19:26:37.601604 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6633 19:26:37.602034 ==
6634 19:26:37.604939 Dram Type= 6, Freq= 0, CH_1, rank 0
6635 19:26:37.608174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6636 19:26:37.608652 ==
6637 19:26:37.614788 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6638 19:26:37.621861 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6639 19:26:37.622392 [CA 0] Center 36 (8~64) winsize 57
6640 19:26:37.624927 [CA 1] Center 36 (8~64) winsize 57
6641 19:26:37.628175 [CA 2] Center 36 (8~64) winsize 57
6642 19:26:37.631536 [CA 3] Center 36 (8~64) winsize 57
6643 19:26:37.634664 [CA 4] Center 36 (8~64) winsize 57
6644 19:26:37.637923 [CA 5] Center 36 (8~64) winsize 57
6645 19:26:37.638343
6646 19:26:37.641137 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6647 19:26:37.641794
6648 19:26:37.644383 [CATrainingPosCal] consider 1 rank data
6649 19:26:37.647772 u2DelayCellTimex100 = 270/100 ps
6650 19:26:37.651625 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6651 19:26:37.658122 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6652 19:26:37.660944 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6653 19:26:37.664545 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6654 19:26:37.668165 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6655 19:26:37.670939 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6656 19:26:37.671369
6657 19:26:37.674441 CA PerBit enable=1, Macro0, CA PI delay=36
6658 19:26:37.674865
6659 19:26:37.677432 [CBTSetCACLKResult] CA Dly = 36
6660 19:26:37.681019 CS Dly: 1 (0~32)
6661 19:26:37.681441 ==
6662 19:26:37.684605 Dram Type= 6, Freq= 0, CH_1, rank 1
6663 19:26:37.687828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6664 19:26:37.688372 ==
6665 19:26:37.694327 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6666 19:26:37.698100 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6667 19:26:37.701157 [CA 0] Center 36 (8~64) winsize 57
6668 19:26:37.703969 [CA 1] Center 36 (8~64) winsize 57
6669 19:26:37.707699 [CA 2] Center 36 (8~64) winsize 57
6670 19:26:37.710406 [CA 3] Center 36 (8~64) winsize 57
6671 19:26:37.714006 [CA 4] Center 36 (8~64) winsize 57
6672 19:26:37.717529 [CA 5] Center 36 (8~64) winsize 57
6673 19:26:37.718307
6674 19:26:37.720781 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6675 19:26:37.721380
6676 19:26:37.724545 [CATrainingPosCal] consider 2 rank data
6677 19:26:37.727168 u2DelayCellTimex100 = 270/100 ps
6678 19:26:37.730750 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6679 19:26:37.733836 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6680 19:26:37.737240 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6681 19:26:37.743527 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6682 19:26:37.747407 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6683 19:26:37.750909 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6684 19:26:37.751505
6685 19:26:37.754002 CA PerBit enable=1, Macro0, CA PI delay=36
6686 19:26:37.754659
6687 19:26:37.757248 [CBTSetCACLKResult] CA Dly = 36
6688 19:26:37.757774 CS Dly: 1 (0~32)
6689 19:26:37.758258
6690 19:26:37.760702 ----->DramcWriteLeveling(PI) begin...
6691 19:26:37.761235 ==
6692 19:26:37.764091 Dram Type= 6, Freq= 0, CH_1, rank 0
6693 19:26:37.770445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6694 19:26:37.771174 ==
6695 19:26:37.774126 Write leveling (Byte 0): 40 => 8
6696 19:26:37.777076 Write leveling (Byte 1): 40 => 8
6697 19:26:37.777754 DramcWriteLeveling(PI) end<-----
6698 19:26:37.780388
6699 19:26:37.780968 ==
6700 19:26:37.783425 Dram Type= 6, Freq= 0, CH_1, rank 0
6701 19:26:37.786750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6702 19:26:37.787345 ==
6703 19:26:37.790547 [Gating] SW mode calibration
6704 19:26:37.796936 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6705 19:26:37.800196 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6706 19:26:37.806664 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6707 19:26:37.810043 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6708 19:26:37.813444 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6709 19:26:37.819655 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6710 19:26:37.823145 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6711 19:26:37.826574 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6712 19:26:37.832802 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6713 19:26:37.836444 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6714 19:26:37.839401 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6715 19:26:37.843036 Total UI for P1: 0, mck2ui 16
6716 19:26:37.846503 best dqsien dly found for B0: ( 0, 14, 24)
6717 19:26:37.849866 Total UI for P1: 0, mck2ui 16
6718 19:26:37.853197 best dqsien dly found for B1: ( 0, 14, 24)
6719 19:26:37.856359 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6720 19:26:37.863027 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6721 19:26:37.863605
6722 19:26:37.866303 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6723 19:26:37.869873 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6724 19:26:37.872599 [Gating] SW calibration Done
6725 19:26:37.873020 ==
6726 19:26:37.876299 Dram Type= 6, Freq= 0, CH_1, rank 0
6727 19:26:37.879448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6728 19:26:37.879876 ==
6729 19:26:37.880207 RX Vref Scan: 0
6730 19:26:37.882813
6731 19:26:37.883233 RX Vref 0 -> 0, step: 1
6732 19:26:37.883568
6733 19:26:37.886087 RX Delay -410 -> 252, step: 16
6734 19:26:37.889162 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6735 19:26:37.896245 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6736 19:26:37.899108 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6737 19:26:37.902849 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6738 19:26:37.905899 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6739 19:26:37.912288 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6740 19:26:37.915829 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6741 19:26:37.919526 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6742 19:26:37.922507 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6743 19:26:37.929162 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6744 19:26:37.932545 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6745 19:26:37.935856 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6746 19:26:37.939787 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6747 19:26:37.945479 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6748 19:26:37.949159 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6749 19:26:37.952740 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6750 19:26:37.953207 ==
6751 19:26:37.955998 Dram Type= 6, Freq= 0, CH_1, rank 0
6752 19:26:37.962393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6753 19:26:37.962817 ==
6754 19:26:37.963229 DQS Delay:
6755 19:26:37.965480 DQS0 = 51, DQS1 = 59
6756 19:26:37.965950 DQM Delay:
6757 19:26:37.966282 DQM0 = 13, DQM1 = 10
6758 19:26:37.968957 DQ Delay:
6759 19:26:37.972387 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6760 19:26:37.972809 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6761 19:26:37.975711 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6762 19:26:37.979333 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6763 19:26:37.979759
6764 19:26:37.980085
6765 19:26:37.982200 ==
6766 19:26:37.985621 Dram Type= 6, Freq= 0, CH_1, rank 0
6767 19:26:37.988792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6768 19:26:37.988901 ==
6769 19:26:37.988965
6770 19:26:37.989023
6771 19:26:37.991707 TX Vref Scan disable
6772 19:26:37.991788 == TX Byte 0 ==
6773 19:26:37.995288 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6774 19:26:38.001798 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6775 19:26:38.001966 == TX Byte 1 ==
6776 19:26:38.005011 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6777 19:26:38.011724 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6778 19:26:38.011934 ==
6779 19:26:38.015106 Dram Type= 6, Freq= 0, CH_1, rank 0
6780 19:26:38.018061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6781 19:26:38.018174 ==
6782 19:26:38.018262
6783 19:26:38.018344
6784 19:26:38.021661 TX Vref Scan disable
6785 19:26:38.021746 == TX Byte 0 ==
6786 19:26:38.025055 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6787 19:26:38.031573 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6788 19:26:38.031664 == TX Byte 1 ==
6789 19:26:38.034807 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6790 19:26:38.041350 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6791 19:26:38.041454
6792 19:26:38.041570 [DATLAT]
6793 19:26:38.041671 Freq=400, CH1 RK0
6794 19:26:38.044682
6795 19:26:38.044828 DATLAT Default: 0xf
6796 19:26:38.048320 0, 0xFFFF, sum = 0
6797 19:26:38.048437 1, 0xFFFF, sum = 0
6798 19:26:38.051667 2, 0xFFFF, sum = 0
6799 19:26:38.051880 3, 0xFFFF, sum = 0
6800 19:26:38.055282 4, 0xFFFF, sum = 0
6801 19:26:38.055503 5, 0xFFFF, sum = 0
6802 19:26:38.057964 6, 0xFFFF, sum = 0
6803 19:26:38.058160 7, 0xFFFF, sum = 0
6804 19:26:38.061367 8, 0xFFFF, sum = 0
6805 19:26:38.061584 9, 0xFFFF, sum = 0
6806 19:26:38.064424 10, 0xFFFF, sum = 0
6807 19:26:38.064637 11, 0xFFFF, sum = 0
6808 19:26:38.068048 12, 0xFFFF, sum = 0
6809 19:26:38.068306 13, 0x0, sum = 1
6810 19:26:38.071262 14, 0x0, sum = 2
6811 19:26:38.071486 15, 0x0, sum = 3
6812 19:26:38.074875 16, 0x0, sum = 4
6813 19:26:38.075127 best_step = 14
6814 19:26:38.075379
6815 19:26:38.075614 ==
6816 19:26:38.078219 Dram Type= 6, Freq= 0, CH_1, rank 0
6817 19:26:38.085577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6818 19:26:38.086067 ==
6819 19:26:38.086478 RX Vref Scan: 1
6820 19:26:38.086856
6821 19:26:38.088217 RX Vref 0 -> 0, step: 1
6822 19:26:38.088614
6823 19:26:38.091340 RX Delay -359 -> 252, step: 8
6824 19:26:38.091818
6825 19:26:38.095297 Set Vref, RX VrefLevel [Byte0]: 55
6826 19:26:38.098412 [Byte1]: 54
6827 19:26:38.098892
6828 19:26:38.101427 Final RX Vref Byte 0 = 55 to rank0
6829 19:26:38.104939 Final RX Vref Byte 1 = 54 to rank0
6830 19:26:38.108597 Final RX Vref Byte 0 = 55 to rank1
6831 19:26:38.111633 Final RX Vref Byte 1 = 54 to rank1==
6832 19:26:38.114753 Dram Type= 6, Freq= 0, CH_1, rank 0
6833 19:26:38.117738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6834 19:26:38.121506 ==
6835 19:26:38.121999 DQS Delay:
6836 19:26:38.122361 DQS0 = 52, DQS1 = 64
6837 19:26:38.124704 DQM Delay:
6838 19:26:38.125163 DQM0 = 9, DQM1 = 10
6839 19:26:38.127660 DQ Delay:
6840 19:26:38.128080 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6841 19:26:38.131094 DQ4 =8, DQ5 =16, DQ6 =20, DQ7 =8
6842 19:26:38.134736 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6843 19:26:38.137661 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6844 19:26:38.138118
6845 19:26:38.138450
6846 19:26:38.147831 [DQSOSCAuto] RK0, (LSB)MR18= 0x5468, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 399 ps
6847 19:26:38.151139 CH1 RK0: MR19=C0C, MR18=5468
6848 19:26:38.157605 CH1_RK0: MR19=0xC0C, MR18=0x5468, DQSOSC=396, MR23=63, INC=376, DEC=251
6849 19:26:38.158071 ==
6850 19:26:38.161145 Dram Type= 6, Freq= 0, CH_1, rank 1
6851 19:26:38.164027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6852 19:26:38.164661 ==
6853 19:26:38.167563 [Gating] SW mode calibration
6854 19:26:38.174180 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6855 19:26:38.177633 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6856 19:26:38.184156 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6857 19:26:38.187385 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6858 19:26:38.190663 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6859 19:26:38.197618 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6860 19:26:38.200570 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6861 19:26:38.203982 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6862 19:26:38.210707 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6863 19:26:38.213716 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6864 19:26:38.217359 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6865 19:26:38.220236 Total UI for P1: 0, mck2ui 16
6866 19:26:38.223741 best dqsien dly found for B0: ( 0, 14, 24)
6867 19:26:38.227183 Total UI for P1: 0, mck2ui 16
6868 19:26:38.230176 best dqsien dly found for B1: ( 0, 14, 24)
6869 19:26:38.233483 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6870 19:26:38.240253 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6871 19:26:38.240670
6872 19:26:38.243879 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6873 19:26:38.246840 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6874 19:26:38.250165 [Gating] SW calibration Done
6875 19:26:38.250584 ==
6876 19:26:38.253835 Dram Type= 6, Freq= 0, CH_1, rank 1
6877 19:26:38.256696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6878 19:26:38.257149 ==
6879 19:26:38.260126 RX Vref Scan: 0
6880 19:26:38.260550
6881 19:26:38.260879 RX Vref 0 -> 0, step: 1
6882 19:26:38.261187
6883 19:26:38.263487 RX Delay -410 -> 252, step: 16
6884 19:26:38.266519 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6885 19:26:38.273476 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6886 19:26:38.276487 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6887 19:26:38.280042 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6888 19:26:38.283101 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6889 19:26:38.289699 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6890 19:26:38.293403 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6891 19:26:38.296576 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6892 19:26:38.299987 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6893 19:26:38.306282 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6894 19:26:38.309449 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6895 19:26:38.313162 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6896 19:26:38.320194 iDelay=230, Bit 12, Center -35 (-298 ~ 229) 528
6897 19:26:38.322852 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6898 19:26:38.326416 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6899 19:26:38.329712 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6900 19:26:38.330136 ==
6901 19:26:38.332903 Dram Type= 6, Freq= 0, CH_1, rank 1
6902 19:26:38.339280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6903 19:26:38.339972 ==
6904 19:26:38.340599 DQS Delay:
6905 19:26:38.342598 DQS0 = 59, DQS1 = 59
6906 19:26:38.343022 DQM Delay:
6907 19:26:38.346379 DQM0 = 19, DQM1 = 15
6908 19:26:38.346875 DQ Delay:
6909 19:26:38.349652 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6910 19:26:38.352961 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6911 19:26:38.356346 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =8
6912 19:26:38.359231 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6913 19:26:38.359683
6914 19:26:38.360326
6915 19:26:38.360770 ==
6916 19:26:38.362554 Dram Type= 6, Freq= 0, CH_1, rank 1
6917 19:26:38.366203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6918 19:26:38.366700 ==
6919 19:26:38.367329
6920 19:26:38.367731
6921 19:26:38.369102 TX Vref Scan disable
6922 19:26:38.369788 == TX Byte 0 ==
6923 19:26:38.375879 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6924 19:26:38.379143 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6925 19:26:38.379579 == TX Byte 1 ==
6926 19:26:38.385794 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6927 19:26:38.389337 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6928 19:26:38.389844 ==
6929 19:26:38.392286 Dram Type= 6, Freq= 0, CH_1, rank 1
6930 19:26:38.395953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6931 19:26:38.396391 ==
6932 19:26:38.396795
6933 19:26:38.397133
6934 19:26:38.398988 TX Vref Scan disable
6935 19:26:38.399429 == TX Byte 0 ==
6936 19:26:38.405970 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6937 19:26:38.408871 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6938 19:26:38.409307 == TX Byte 1 ==
6939 19:26:38.415597 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6940 19:26:38.418795 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6941 19:26:38.419215
6942 19:26:38.419571 [DATLAT]
6943 19:26:38.422042 Freq=400, CH1 RK1
6944 19:26:38.422460
6945 19:26:38.422787 DATLAT Default: 0xe
6946 19:26:38.425657 0, 0xFFFF, sum = 0
6947 19:26:38.426084 1, 0xFFFF, sum = 0
6948 19:26:38.429494 2, 0xFFFF, sum = 0
6949 19:26:38.430374 3, 0xFFFF, sum = 0
6950 19:26:38.432216 4, 0xFFFF, sum = 0
6951 19:26:38.432638 5, 0xFFFF, sum = 0
6952 19:26:38.435678 6, 0xFFFF, sum = 0
6953 19:26:38.436105 7, 0xFFFF, sum = 0
6954 19:26:38.439118 8, 0xFFFF, sum = 0
6955 19:26:38.439544 9, 0xFFFF, sum = 0
6956 19:26:38.442229 10, 0xFFFF, sum = 0
6957 19:26:38.445872 11, 0xFFFF, sum = 0
6958 19:26:38.446514 12, 0xFFFF, sum = 0
6959 19:26:38.448699 13, 0x0, sum = 1
6960 19:26:38.449157 14, 0x0, sum = 2
6961 19:26:38.452284 15, 0x0, sum = 3
6962 19:26:38.452709 16, 0x0, sum = 4
6963 19:26:38.453054 best_step = 14
6964 19:26:38.453360
6965 19:26:38.455301 ==
6966 19:26:38.458686 Dram Type= 6, Freq= 0, CH_1, rank 1
6967 19:26:38.461664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6968 19:26:38.462089 ==
6969 19:26:38.462416 RX Vref Scan: 0
6970 19:26:38.462728
6971 19:26:38.465008 RX Vref 0 -> 0, step: 1
6972 19:26:38.465427
6973 19:26:38.468742 RX Delay -359 -> 252, step: 8
6974 19:26:38.475373 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6975 19:26:38.478698 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
6976 19:26:38.482019 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
6977 19:26:38.488796 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6978 19:26:38.491838 iDelay=217, Bit 4, Center -44 (-295 ~ 208) 504
6979 19:26:38.495595 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
6980 19:26:38.498915 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6981 19:26:38.501933 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
6982 19:26:38.508696 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
6983 19:26:38.511769 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
6984 19:26:38.515400 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
6985 19:26:38.522004 iDelay=217, Bit 11, Center -56 (-311 ~ 200) 512
6986 19:26:38.525073 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6987 19:26:38.528327 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6988 19:26:38.532198 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
6989 19:26:38.538677 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6990 19:26:38.539250 ==
6991 19:26:38.542002 Dram Type= 6, Freq= 0, CH_1, rank 1
6992 19:26:38.544975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6993 19:26:38.545477 ==
6994 19:26:38.546114 DQS Delay:
6995 19:26:38.548884 DQS0 = 60, DQS1 = 64
6996 19:26:38.549491 DQM Delay:
6997 19:26:38.551665 DQM0 = 13, DQM1 = 11
6998 19:26:38.552147 DQ Delay:
6999 19:26:38.555463 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7000 19:26:38.558332 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
7001 19:26:38.561775 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
7002 19:26:38.565463 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
7003 19:26:38.566032
7004 19:26:38.566480
7005 19:26:38.571454 [DQSOSCAuto] RK1, (LSB)MR18= 0x74a5, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 395 ps
7006 19:26:38.575211 CH1 RK1: MR19=C0C, MR18=74A5
7007 19:26:38.581452 CH1_RK1: MR19=0xC0C, MR18=0x74A5, DQSOSC=389, MR23=63, INC=390, DEC=260
7008 19:26:38.584935 [RxdqsGatingPostProcess] freq 400
7009 19:26:38.591671 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7010 19:26:38.594981 best DQS0 dly(2T, 0.5T) = (0, 10)
7011 19:26:38.595423 best DQS1 dly(2T, 0.5T) = (0, 10)
7012 19:26:38.598214 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7013 19:26:38.601663 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7014 19:26:38.605193 best DQS0 dly(2T, 0.5T) = (0, 10)
7015 19:26:38.608277 best DQS1 dly(2T, 0.5T) = (0, 10)
7016 19:26:38.611586 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7017 19:26:38.614712 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7018 19:26:38.618236 Pre-setting of DQS Precalculation
7019 19:26:38.624682 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7020 19:26:38.631272 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7021 19:26:38.637821 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7022 19:26:38.638247
7023 19:26:38.638570
7024 19:26:38.641255 [Calibration Summary] 800 Mbps
7025 19:26:38.641705 CH 0, Rank 0
7026 19:26:38.644595 SW Impedance : PASS
7027 19:26:38.647986 DUTY Scan : NO K
7028 19:26:38.648407 ZQ Calibration : PASS
7029 19:26:38.651044 Jitter Meter : NO K
7030 19:26:38.654623 CBT Training : PASS
7031 19:26:38.655042 Write leveling : PASS
7032 19:26:38.657422 RX DQS gating : PASS
7033 19:26:38.658010 RX DQ/DQS(RDDQC) : PASS
7034 19:26:38.661171 TX DQ/DQS : PASS
7035 19:26:38.664894 RX DATLAT : PASS
7036 19:26:38.665313 RX DQ/DQS(Engine): PASS
7037 19:26:38.667543 TX OE : NO K
7038 19:26:38.667981 All Pass.
7039 19:26:38.668312
7040 19:26:38.671018 CH 0, Rank 1
7041 19:26:38.671437 SW Impedance : PASS
7042 19:26:38.674308 DUTY Scan : NO K
7043 19:26:38.677342 ZQ Calibration : PASS
7044 19:26:38.677868 Jitter Meter : NO K
7045 19:26:38.681026 CBT Training : PASS
7046 19:26:38.684438 Write leveling : NO K
7047 19:26:38.684875 RX DQS gating : PASS
7048 19:26:38.687356 RX DQ/DQS(RDDQC) : PASS
7049 19:26:38.690590 TX DQ/DQS : PASS
7050 19:26:38.691031 RX DATLAT : PASS
7051 19:26:38.694144 RX DQ/DQS(Engine): PASS
7052 19:26:38.697563 TX OE : NO K
7053 19:26:38.697988 All Pass.
7054 19:26:38.698317
7055 19:26:38.698625 CH 1, Rank 0
7056 19:26:38.701226 SW Impedance : PASS
7057 19:26:38.704202 DUTY Scan : NO K
7058 19:26:38.704646 ZQ Calibration : PASS
7059 19:26:38.707599 Jitter Meter : NO K
7060 19:26:38.710845 CBT Training : PASS
7061 19:26:38.711264 Write leveling : PASS
7062 19:26:38.713959 RX DQS gating : PASS
7063 19:26:38.714381 RX DQ/DQS(RDDQC) : PASS
7064 19:26:38.717462 TX DQ/DQS : PASS
7065 19:26:38.720670 RX DATLAT : PASS
7066 19:26:38.721093 RX DQ/DQS(Engine): PASS
7067 19:26:38.724115 TX OE : NO K
7068 19:26:38.724537 All Pass.
7069 19:26:38.724864
7070 19:26:38.727143 CH 1, Rank 1
7071 19:26:38.727559 SW Impedance : PASS
7072 19:26:38.730552 DUTY Scan : NO K
7073 19:26:38.733956 ZQ Calibration : PASS
7074 19:26:38.734373 Jitter Meter : NO K
7075 19:26:38.737184 CBT Training : PASS
7076 19:26:38.740740 Write leveling : NO K
7077 19:26:38.741160 RX DQS gating : PASS
7078 19:26:38.743963 RX DQ/DQS(RDDQC) : PASS
7079 19:26:38.747276 TX DQ/DQS : PASS
7080 19:26:38.747695 RX DATLAT : PASS
7081 19:26:38.750595 RX DQ/DQS(Engine): PASS
7082 19:26:38.754045 TX OE : NO K
7083 19:26:38.754464 All Pass.
7084 19:26:38.754789
7085 19:26:38.755098 DramC Write-DBI off
7086 19:26:38.757329 PER_BANK_REFRESH: Hybrid Mode
7087 19:26:38.760276 TX_TRACKING: ON
7088 19:26:38.766881 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7089 19:26:38.773871 [FAST_K] Save calibration result to emmc
7090 19:26:38.776865 dramc_set_vcore_voltage set vcore to 725000
7091 19:26:38.777284 Read voltage for 1600, 0
7092 19:26:38.780242 Vio18 = 0
7093 19:26:38.780660 Vcore = 725000
7094 19:26:38.781030 Vdram = 0
7095 19:26:38.783774 Vddq = 0
7096 19:26:38.784269 Vmddr = 0
7097 19:26:38.786787 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7098 19:26:38.793978 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7099 19:26:38.796925 MEM_TYPE=3, freq_sel=13
7100 19:26:38.800256 sv_algorithm_assistance_LP4_3733
7101 19:26:38.803323 ============ PULL DRAM RESETB DOWN ============
7102 19:26:38.806750 ========== PULL DRAM RESETB DOWN end =========
7103 19:26:38.813384 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7104 19:26:38.813839 ===================================
7105 19:26:38.816907 LPDDR4 DRAM CONFIGURATION
7106 19:26:38.820281 ===================================
7107 19:26:38.823534 EX_ROW_EN[0] = 0x0
7108 19:26:38.823954 EX_ROW_EN[1] = 0x0
7109 19:26:38.826480 LP4Y_EN = 0x0
7110 19:26:38.826902 WORK_FSP = 0x1
7111 19:26:38.830019 WL = 0x5
7112 19:26:38.830442 RL = 0x5
7113 19:26:38.833124 BL = 0x2
7114 19:26:38.836686 RPST = 0x0
7115 19:26:38.837289 RD_PRE = 0x0
7116 19:26:38.839606 WR_PRE = 0x1
7117 19:26:38.840024 WR_PST = 0x1
7118 19:26:38.843008 DBI_WR = 0x0
7119 19:26:38.843428 DBI_RD = 0x0
7120 19:26:38.846524 OTF = 0x1
7121 19:26:38.849628 ===================================
7122 19:26:38.853194 ===================================
7123 19:26:38.853661 ANA top config
7124 19:26:38.856400 ===================================
7125 19:26:38.859523 DLL_ASYNC_EN = 0
7126 19:26:38.862821 ALL_SLAVE_EN = 0
7127 19:26:38.863253 NEW_RANK_MODE = 1
7128 19:26:38.866099 DLL_IDLE_MODE = 1
7129 19:26:38.869607 LP45_APHY_COMB_EN = 1
7130 19:26:38.872548 TX_ODT_DIS = 0
7131 19:26:38.876073 NEW_8X_MODE = 1
7132 19:26:38.879218 ===================================
7133 19:26:38.882648 ===================================
7134 19:26:38.883071 data_rate = 3200
7135 19:26:38.886211 CKR = 1
7136 19:26:38.889252 DQ_P2S_RATIO = 8
7137 19:26:38.892882 ===================================
7138 19:26:38.895902 CA_P2S_RATIO = 8
7139 19:26:38.899061 DQ_CA_OPEN = 0
7140 19:26:38.902645 DQ_SEMI_OPEN = 0
7141 19:26:38.903082 CA_SEMI_OPEN = 0
7142 19:26:38.905497 CA_FULL_RATE = 0
7143 19:26:38.909031 DQ_CKDIV4_EN = 0
7144 19:26:38.912598 CA_CKDIV4_EN = 0
7145 19:26:38.915488 CA_PREDIV_EN = 0
7146 19:26:38.919059 PH8_DLY = 12
7147 19:26:38.922130 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7148 19:26:38.922555 DQ_AAMCK_DIV = 4
7149 19:26:38.925813 CA_AAMCK_DIV = 4
7150 19:26:38.928760 CA_ADMCK_DIV = 4
7151 19:26:38.932185 DQ_TRACK_CA_EN = 0
7152 19:26:38.935308 CA_PICK = 1600
7153 19:26:38.938870 CA_MCKIO = 1600
7154 19:26:38.942376 MCKIO_SEMI = 0
7155 19:26:38.942796 PLL_FREQ = 3068
7156 19:26:38.945250 DQ_UI_PI_RATIO = 32
7157 19:26:38.948627 CA_UI_PI_RATIO = 0
7158 19:26:38.952163 ===================================
7159 19:26:38.955634 ===================================
7160 19:26:38.958473 memory_type:LPDDR4
7161 19:26:38.958892 GP_NUM : 10
7162 19:26:38.961660 SRAM_EN : 1
7163 19:26:38.965370 MD32_EN : 0
7164 19:26:38.968562 ===================================
7165 19:26:38.968983 [ANA_INIT] >>>>>>>>>>>>>>
7166 19:26:38.971740 <<<<<< [CONFIGURE PHASE]: ANA_TX
7167 19:26:38.975472 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7168 19:26:38.978165 ===================================
7169 19:26:38.981546 data_rate = 3200,PCW = 0X7600
7170 19:26:38.984980 ===================================
7171 19:26:38.988323 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7172 19:26:38.995355 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7173 19:26:38.998412 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7174 19:26:39.004906 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7175 19:26:39.008737 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7176 19:26:39.011855 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7177 19:26:39.015115 [ANA_INIT] flow start
7178 19:26:39.015537 [ANA_INIT] PLL >>>>>>>>
7179 19:26:39.018005 [ANA_INIT] PLL <<<<<<<<
7180 19:26:39.021556 [ANA_INIT] MIDPI >>>>>>>>
7181 19:26:39.022109 [ANA_INIT] MIDPI <<<<<<<<
7182 19:26:39.024924 [ANA_INIT] DLL >>>>>>>>
7183 19:26:39.028149 [ANA_INIT] DLL <<<<<<<<
7184 19:26:39.028695 [ANA_INIT] flow end
7185 19:26:39.034989 ============ LP4 DIFF to SE enter ============
7186 19:26:39.038390 ============ LP4 DIFF to SE exit ============
7187 19:26:39.041247 [ANA_INIT] <<<<<<<<<<<<<
7188 19:26:39.044556 [Flow] Enable top DCM control >>>>>
7189 19:26:39.047862 [Flow] Enable top DCM control <<<<<
7190 19:26:39.048323 Enable DLL master slave shuffle
7191 19:26:39.054279 ==============================================================
7192 19:26:39.057858 Gating Mode config
7193 19:26:39.060708 ==============================================================
7194 19:26:39.064328 Config description:
7195 19:26:39.073932 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7196 19:26:39.080732 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7197 19:26:39.083927 SELPH_MODE 0: By rank 1: By Phase
7198 19:26:39.090502 ==============================================================
7199 19:26:39.094096 GAT_TRACK_EN = 1
7200 19:26:39.097257 RX_GATING_MODE = 2
7201 19:26:39.100631 RX_GATING_TRACK_MODE = 2
7202 19:26:39.103757 SELPH_MODE = 1
7203 19:26:39.107397 PICG_EARLY_EN = 1
7204 19:26:39.107837 VALID_LAT_VALUE = 1
7205 19:26:39.113954 ==============================================================
7206 19:26:39.116814 Enter into Gating configuration >>>>
7207 19:26:39.120236 Exit from Gating configuration <<<<
7208 19:26:39.123834 Enter into DVFS_PRE_config >>>>>
7209 19:26:39.133827 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7210 19:26:39.137109 Exit from DVFS_PRE_config <<<<<
7211 19:26:39.140355 Enter into PICG configuration >>>>
7212 19:26:39.143667 Exit from PICG configuration <<<<
7213 19:26:39.146731 [RX_INPUT] configuration >>>>>
7214 19:26:39.149939 [RX_INPUT] configuration <<<<<
7215 19:26:39.156527 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7216 19:26:39.159885 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7217 19:26:39.166530 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7218 19:26:39.173444 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7219 19:26:39.179888 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7220 19:26:39.186378 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7221 19:26:39.190119 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7222 19:26:39.193326 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7223 19:26:39.196386 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7224 19:26:39.203221 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7225 19:26:39.206450 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7226 19:26:39.209555 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7227 19:26:39.212717 ===================================
7228 19:26:39.216277 LPDDR4 DRAM CONFIGURATION
7229 19:26:39.219373 ===================================
7230 19:26:39.219794 EX_ROW_EN[0] = 0x0
7231 19:26:39.222971 EX_ROW_EN[1] = 0x0
7232 19:26:39.226702 LP4Y_EN = 0x0
7233 19:26:39.227238 WORK_FSP = 0x1
7234 19:26:39.229466 WL = 0x5
7235 19:26:39.229918 RL = 0x5
7236 19:26:39.232623 BL = 0x2
7237 19:26:39.233041 RPST = 0x0
7238 19:26:39.236420 RD_PRE = 0x0
7239 19:26:39.236945 WR_PRE = 0x1
7240 19:26:39.239776 WR_PST = 0x1
7241 19:26:39.240195 DBI_WR = 0x0
7242 19:26:39.242876 DBI_RD = 0x0
7243 19:26:39.243294 OTF = 0x1
7244 19:26:39.246159 ===================================
7245 19:26:39.249555 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7246 19:26:39.256209 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7247 19:26:39.259342 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7248 19:26:39.262890 ===================================
7249 19:26:39.265882 LPDDR4 DRAM CONFIGURATION
7250 19:26:39.268983 ===================================
7251 19:26:39.269403 EX_ROW_EN[0] = 0x10
7252 19:26:39.272352 EX_ROW_EN[1] = 0x0
7253 19:26:39.275746 LP4Y_EN = 0x0
7254 19:26:39.276167 WORK_FSP = 0x1
7255 19:26:39.278926 WL = 0x5
7256 19:26:39.279348 RL = 0x5
7257 19:26:39.281931 BL = 0x2
7258 19:26:39.282394 RPST = 0x0
7259 19:26:39.285393 RD_PRE = 0x0
7260 19:26:39.285873 WR_PRE = 0x1
7261 19:26:39.288640 WR_PST = 0x1
7262 19:26:39.289124 DBI_WR = 0x0
7263 19:26:39.292106 DBI_RD = 0x0
7264 19:26:39.292658 OTF = 0x1
7265 19:26:39.295182 ===================================
7266 19:26:39.302080 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7267 19:26:39.302562 ==
7268 19:26:39.304812 Dram Type= 6, Freq= 0, CH_0, rank 0
7269 19:26:39.311854 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7270 19:26:39.311939 ==
7271 19:26:39.312023 [Duty_Offset_Calibration]
7272 19:26:39.315098 B0:2 B1:0 CA:3
7273 19:26:39.315180
7274 19:26:39.318333 [DutyScan_Calibration_Flow] k_type=0
7275 19:26:39.326993
7276 19:26:39.327100 ==CLK 0==
7277 19:26:39.330506 Final CLK duty delay cell = 0
7278 19:26:39.334110 [0] MAX Duty = 5031%(X100), DQS PI = 12
7279 19:26:39.337121 [0] MIN Duty = 4907%(X100), DQS PI = 6
7280 19:26:39.337224 [0] AVG Duty = 4969%(X100)
7281 19:26:39.340604
7282 19:26:39.343619 CH0 CLK Duty spec in!! Max-Min= 124%
7283 19:26:39.347233 [DutyScan_Calibration_Flow] ====Done====
7284 19:26:39.347334
7285 19:26:39.350173 [DutyScan_Calibration_Flow] k_type=1
7286 19:26:39.366985
7287 19:26:39.367095 ==DQS 0 ==
7288 19:26:39.370809 Final DQS duty delay cell = 0
7289 19:26:39.374338 [0] MAX Duty = 5094%(X100), DQS PI = 28
7290 19:26:39.377325 [0] MIN Duty = 4875%(X100), DQS PI = 48
7291 19:26:39.377799 [0] AVG Duty = 4984%(X100)
7292 19:26:39.380821
7293 19:26:39.381248 ==DQS 1 ==
7294 19:26:39.383804 Final DQS duty delay cell = 0
7295 19:26:39.387365 [0] MAX Duty = 5156%(X100), DQS PI = 32
7296 19:26:39.390810 [0] MIN Duty = 5031%(X100), DQS PI = 14
7297 19:26:39.391329 [0] AVG Duty = 5093%(X100)
7298 19:26:39.394190
7299 19:26:39.397411 CH0 DQS 0 Duty spec in!! Max-Min= 219%
7300 19:26:39.398038
7301 19:26:39.400498 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7302 19:26:39.403836 [DutyScan_Calibration_Flow] ====Done====
7303 19:26:39.404264
7304 19:26:39.406894 [DutyScan_Calibration_Flow] k_type=3
7305 19:26:39.425112
7306 19:26:39.425762 ==DQM 0 ==
7307 19:26:39.428666 Final DQM duty delay cell = 0
7308 19:26:39.432017 [0] MAX Duty = 5125%(X100), DQS PI = 30
7309 19:26:39.435018 [0] MIN Duty = 4844%(X100), DQS PI = 50
7310 19:26:39.438834 [0] AVG Duty = 4984%(X100)
7311 19:26:39.439396
7312 19:26:39.439959 ==DQM 1 ==
7313 19:26:39.441828 Final DQM duty delay cell = 4
7314 19:26:39.445498 [4] MAX Duty = 5156%(X100), DQS PI = 52
7315 19:26:39.448418 [4] MIN Duty = 5031%(X100), DQS PI = 12
7316 19:26:39.451420 [4] AVG Duty = 5093%(X100)
7317 19:26:39.451846
7318 19:26:39.454944 CH0 DQM 0 Duty spec in!! Max-Min= 281%
7319 19:26:39.455617
7320 19:26:39.458455 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7321 19:26:39.461442 [DutyScan_Calibration_Flow] ====Done====
7322 19:26:39.462021
7323 19:26:39.464992 [DutyScan_Calibration_Flow] k_type=2
7324 19:26:39.481710
7325 19:26:39.482123 ==DQ 0 ==
7326 19:26:39.484707 Final DQ duty delay cell = -4
7327 19:26:39.487993 [-4] MAX Duty = 5000%(X100), DQS PI = 14
7328 19:26:39.491160 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7329 19:26:39.494386 [-4] AVG Duty = 4938%(X100)
7330 19:26:39.494470
7331 19:26:39.494562 ==DQ 1 ==
7332 19:26:39.497385 Final DQ duty delay cell = 0
7333 19:26:39.501025 [0] MAX Duty = 5156%(X100), DQS PI = 58
7334 19:26:39.504512 [0] MIN Duty = 5000%(X100), DQS PI = 16
7335 19:26:39.507863 [0] AVG Duty = 5078%(X100)
7336 19:26:39.507943
7337 19:26:39.511029 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7338 19:26:39.511142
7339 19:26:39.514460 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7340 19:26:39.517406 [DutyScan_Calibration_Flow] ====Done====
7341 19:26:39.517536 ==
7342 19:26:39.521005 Dram Type= 6, Freq= 0, CH_1, rank 0
7343 19:26:39.523958 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7344 19:26:39.524090 ==
7345 19:26:39.527563 [Duty_Offset_Calibration]
7346 19:26:39.527699 B0:1 B1:-2 CA:1
7347 19:26:39.527822
7348 19:26:39.530644 [DutyScan_Calibration_Flow] k_type=0
7349 19:26:39.541535
7350 19:26:39.541738 ==CLK 0==
7351 19:26:39.545070 Final CLK duty delay cell = 0
7352 19:26:39.548168 [0] MAX Duty = 5062%(X100), DQS PI = 20
7353 19:26:39.551669 [0] MIN Duty = 4813%(X100), DQS PI = 60
7354 19:26:39.554621 [0] AVG Duty = 4937%(X100)
7355 19:26:39.554886
7356 19:26:39.558244 CH1 CLK Duty spec in!! Max-Min= 249%
7357 19:26:39.561688 [DutyScan_Calibration_Flow] ====Done====
7358 19:26:39.561768
7359 19:26:39.564626 [DutyScan_Calibration_Flow] k_type=1
7360 19:26:39.581060
7361 19:26:39.581165 ==DQS 0 ==
7362 19:26:39.584926 Final DQS duty delay cell = 0
7363 19:26:39.587717 [0] MAX Duty = 5187%(X100), DQS PI = 24
7364 19:26:39.591137 [0] MIN Duty = 5031%(X100), DQS PI = 54
7365 19:26:39.594794 [0] AVG Duty = 5109%(X100)
7366 19:26:39.594899
7367 19:26:39.594989 ==DQS 1 ==
7368 19:26:39.597758 Final DQS duty delay cell = 0
7369 19:26:39.601244 [0] MAX Duty = 5093%(X100), DQS PI = 0
7370 19:26:39.604210 [0] MIN Duty = 4844%(X100), DQS PI = 24
7371 19:26:39.607715 [0] AVG Duty = 4968%(X100)
7372 19:26:39.607821
7373 19:26:39.611032 CH1 DQS 0 Duty spec in!! Max-Min= 156%
7374 19:26:39.611112
7375 19:26:39.614663 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7376 19:26:39.617475 [DutyScan_Calibration_Flow] ====Done====
7377 19:26:39.617599
7378 19:26:39.621290 [DutyScan_Calibration_Flow] k_type=3
7379 19:26:39.637951
7380 19:26:39.638070 ==DQM 0 ==
7381 19:26:39.641280 Final DQM duty delay cell = 0
7382 19:26:39.644762 [0] MAX Duty = 5031%(X100), DQS PI = 24
7383 19:26:39.647879 [0] MIN Duty = 4813%(X100), DQS PI = 54
7384 19:26:39.651681 [0] AVG Duty = 4922%(X100)
7385 19:26:39.652142
7386 19:26:39.652487 ==DQM 1 ==
7387 19:26:39.654961 Final DQM duty delay cell = 0
7388 19:26:39.658366 [0] MAX Duty = 5062%(X100), DQS PI = 34
7389 19:26:39.661421 [0] MIN Duty = 4875%(X100), DQS PI = 24
7390 19:26:39.664772 [0] AVG Duty = 4968%(X100)
7391 19:26:39.665183
7392 19:26:39.668263 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7393 19:26:39.668726
7394 19:26:39.671114 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7395 19:26:39.674940 [DutyScan_Calibration_Flow] ====Done====
7396 19:26:39.675354
7397 19:26:39.677994 [DutyScan_Calibration_Flow] k_type=2
7398 19:26:39.695106
7399 19:26:39.695609 ==DQ 0 ==
7400 19:26:39.698239 Final DQ duty delay cell = 0
7401 19:26:39.701730 [0] MAX Duty = 5093%(X100), DQS PI = 22
7402 19:26:39.704796 [0] MIN Duty = 4907%(X100), DQS PI = 0
7403 19:26:39.705310 [0] AVG Duty = 5000%(X100)
7404 19:26:39.708376
7405 19:26:39.708915 ==DQ 1 ==
7406 19:26:39.711353 Final DQ duty delay cell = 0
7407 19:26:39.714830 [0] MAX Duty = 5125%(X100), DQS PI = 34
7408 19:26:39.718144 [0] MIN Duty = 4969%(X100), DQS PI = 24
7409 19:26:39.718706 [0] AVG Duty = 5047%(X100)
7410 19:26:39.719126
7411 19:26:39.725169 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7412 19:26:39.725661
7413 19:26:39.728713 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7414 19:26:39.731936 [DutyScan_Calibration_Flow] ====Done====
7415 19:26:39.734944 nWR fixed to 30
7416 19:26:39.735432 [ModeRegInit_LP4] CH0 RK0
7417 19:26:39.738360 [ModeRegInit_LP4] CH0 RK1
7418 19:26:39.741937 [ModeRegInit_LP4] CH1 RK0
7419 19:26:39.744868 [ModeRegInit_LP4] CH1 RK1
7420 19:26:39.745330 match AC timing 5
7421 19:26:39.748179 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7422 19:26:39.754787 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7423 19:26:39.758254 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7424 19:26:39.764813 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7425 19:26:39.768074 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7426 19:26:39.768671 [MiockJmeterHQA]
7427 19:26:39.769204
7428 19:26:39.771365 [DramcMiockJmeter] u1RxGatingPI = 0
7429 19:26:39.774613 0 : 4253, 4027
7430 19:26:39.775078 4 : 4253, 4026
7431 19:26:39.775536 8 : 4255, 4029
7432 19:26:39.777966 12 : 4367, 4142
7433 19:26:39.778522 16 : 4255, 4029
7434 19:26:39.781661 20 : 4257, 4032
7435 19:26:39.782150 24 : 4257, 4029
7436 19:26:39.784489 28 : 4255, 4029
7437 19:26:39.784911 32 : 4370, 4143
7438 19:26:39.788124 36 : 4257, 4029
7439 19:26:39.788546 40 : 4367, 4140
7440 19:26:39.788879 44 : 4365, 4140
7441 19:26:39.791123 48 : 4254, 4029
7442 19:26:39.791550 52 : 4257, 4030
7443 19:26:39.794670 56 : 4254, 4029
7444 19:26:39.795093 60 : 4257, 4032
7445 19:26:39.797660 64 : 4368, 4142
7446 19:26:39.798089 68 : 4252, 4029
7447 19:26:39.801180 72 : 4252, 4029
7448 19:26:39.801644 76 : 4255, 4029
7449 19:26:39.801984 80 : 4255, 4030
7450 19:26:39.804841 84 : 4368, 4143
7451 19:26:39.805265 88 : 4365, 4140
7452 19:26:39.807877 92 : 4252, 4029
7453 19:26:39.808301 96 : 4255, 4029
7454 19:26:39.811263 100 : 4366, 4140
7455 19:26:39.811690 104 : 4252, 3951
7456 19:26:39.814701 108 : 4365, 26
7457 19:26:39.815125 112 : 4255, 0
7458 19:26:39.815459 116 : 4255, 0
7459 19:26:39.817834 120 : 4257, 0
7460 19:26:39.818258 124 : 4252, 0
7461 19:26:39.820813 128 : 4255, 0
7462 19:26:39.821240 132 : 4368, 0
7463 19:26:39.821618 136 : 4363, 0
7464 19:26:39.824706 140 : 4252, 0
7465 19:26:39.825132 144 : 4366, 0
7466 19:26:39.825668 148 : 4252, 0
7467 19:26:39.827899 152 : 4363, 0
7468 19:26:39.828323 156 : 4253, 0
7469 19:26:39.830865 160 : 4252, 0
7470 19:26:39.831291 164 : 4252, 0
7471 19:26:39.831657 168 : 4255, 0
7472 19:26:39.834356 172 : 4257, 0
7473 19:26:39.834780 176 : 4252, 0
7474 19:26:39.837853 180 : 4255, 0
7475 19:26:39.838278 184 : 4255, 0
7476 19:26:39.838613 188 : 4252, 0
7477 19:26:39.841038 192 : 4363, 0
7478 19:26:39.841581 196 : 4366, 0
7479 19:26:39.844422 200 : 4253, 0
7480 19:26:39.844845 204 : 4252, 0
7481 19:26:39.845177 208 : 4255, 0
7482 19:26:39.847367 212 : 4257, 0
7483 19:26:39.847792 216 : 4252, 0
7484 19:26:39.848124 220 : 4255, 0
7485 19:26:39.850965 224 : 4253, 0
7486 19:26:39.851407 228 : 4252, 0
7487 19:26:39.854413 232 : 4253, 0
7488 19:26:39.854837 236 : 4257, 552
7489 19:26:39.857334 240 : 4362, 4137
7490 19:26:39.857804 244 : 4252, 4029
7491 19:26:39.860936 248 : 4255, 4029
7492 19:26:39.861381 252 : 4252, 4029
7493 19:26:39.861827 256 : 4366, 4140
7494 19:26:39.864370 260 : 4365, 4140
7495 19:26:39.864795 264 : 4252, 4029
7496 19:26:39.867616 268 : 4255, 4029
7497 19:26:39.868041 272 : 4253, 4029
7498 19:26:39.870980 276 : 4250, 4027
7499 19:26:39.871403 280 : 4252, 4030
7500 19:26:39.873988 284 : 4257, 4032
7501 19:26:39.874410 288 : 4255, 4029
7502 19:26:39.877279 292 : 4363, 4140
7503 19:26:39.877765 296 : 4252, 4030
7504 19:26:39.880552 300 : 4255, 4029
7505 19:26:39.880973 304 : 4255, 4029
7506 19:26:39.884254 308 : 4255, 4029
7507 19:26:39.884708 312 : 4253, 4029
7508 19:26:39.885046 316 : 4250, 4026
7509 19:26:39.887563 320 : 4367, 4143
7510 19:26:39.887989 324 : 4253, 4029
7511 19:26:39.890642 328 : 4252, 4029
7512 19:26:39.891066 332 : 4252, 4030
7513 19:26:39.894295 336 : 4257, 4032
7514 19:26:39.894795 340 : 4255, 4029
7515 19:26:39.897292 344 : 4255, 4029
7516 19:26:39.897754 348 : 4363, 4139
7517 19:26:39.901088 352 : 4252, 4012
7518 19:26:39.901539 356 : 4366, 2795
7519 19:26:39.903926 360 : 4366, 0
7520 19:26:39.904350
7521 19:26:39.904677 MIOCK jitter meter ch=0
7522 19:26:39.904986
7523 19:26:39.907588 1T = (360-108) = 252 dly cells
7524 19:26:39.914313 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7525 19:26:39.914831 ==
7526 19:26:39.917194 Dram Type= 6, Freq= 0, CH_0, rank 0
7527 19:26:39.920720 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7528 19:26:39.921152 ==
7529 19:26:39.926961 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7530 19:26:39.930505 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7531 19:26:39.933939 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7532 19:26:39.940231 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7533 19:26:39.950215 [CA 0] Center 44 (14~75) winsize 62
7534 19:26:39.953204 [CA 1] Center 43 (13~74) winsize 62
7535 19:26:39.956354 [CA 2] Center 40 (11~69) winsize 59
7536 19:26:39.959756 [CA 3] Center 39 (10~68) winsize 59
7537 19:26:39.963252 [CA 4] Center 37 (8~67) winsize 60
7538 19:26:39.966795 [CA 5] Center 37 (7~67) winsize 61
7539 19:26:39.967320
7540 19:26:39.969766 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7541 19:26:39.970343
7542 19:26:39.973154 [CATrainingPosCal] consider 1 rank data
7543 19:26:39.976355 u2DelayCellTimex100 = 258/100 ps
7544 19:26:39.979924 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7545 19:26:39.986976 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7546 19:26:39.990114 CA2 delay=40 (11~69),Diff = 3 PI (11 cell)
7547 19:26:39.993316 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7548 19:26:39.996573 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7549 19:26:40.000014 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7550 19:26:40.000559
7551 19:26:40.002940 CA PerBit enable=1, Macro0, CA PI delay=37
7552 19:26:40.003570
7553 19:26:40.006392 [CBTSetCACLKResult] CA Dly = 37
7554 19:26:40.009386 CS Dly: 11 (0~42)
7555 19:26:40.012860 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7556 19:26:40.016558 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7557 19:26:40.017115 ==
7558 19:26:40.019567 Dram Type= 6, Freq= 0, CH_0, rank 1
7559 19:26:40.026298 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7560 19:26:40.026731 ==
7561 19:26:40.029984 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7562 19:26:40.036541 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7563 19:26:40.039317 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7564 19:26:40.045910 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7565 19:26:40.053980 [CA 0] Center 43 (13~74) winsize 62
7566 19:26:40.057409 [CA 1] Center 43 (13~74) winsize 62
7567 19:26:40.060309 [CA 2] Center 39 (10~68) winsize 59
7568 19:26:40.063784 [CA 3] Center 39 (10~68) winsize 59
7569 19:26:40.066966 [CA 4] Center 36 (6~66) winsize 61
7570 19:26:40.070416 [CA 5] Center 36 (6~66) winsize 61
7571 19:26:40.070836
7572 19:26:40.073759 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7573 19:26:40.074296
7574 19:26:40.079982 [CATrainingPosCal] consider 2 rank data
7575 19:26:40.080404 u2DelayCellTimex100 = 258/100 ps
7576 19:26:40.087015 CA0 delay=44 (14~74),Diff = 8 PI (30 cell)
7577 19:26:40.090051 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7578 19:26:40.093599 CA2 delay=39 (11~68),Diff = 3 PI (11 cell)
7579 19:26:40.097031 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7580 19:26:40.100230 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7581 19:26:40.103510 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7582 19:26:40.103935
7583 19:26:40.106785 CA PerBit enable=1, Macro0, CA PI delay=36
7584 19:26:40.107206
7585 19:26:40.110020 [CBTSetCACLKResult] CA Dly = 36
7586 19:26:40.113451 CS Dly: 11 (0~43)
7587 19:26:40.116335 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7588 19:26:40.120034 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7589 19:26:40.120453
7590 19:26:40.122940 ----->DramcWriteLeveling(PI) begin...
7591 19:26:40.126448 ==
7592 19:26:40.129588 Dram Type= 6, Freq= 0, CH_0, rank 0
7593 19:26:40.133327 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7594 19:26:40.133778 ==
7595 19:26:40.135972 Write leveling (Byte 0): 37 => 37
7596 19:26:40.139639 Write leveling (Byte 1): 28 => 28
7597 19:26:40.142964 DramcWriteLeveling(PI) end<-----
7598 19:26:40.143541
7599 19:26:40.143875 ==
7600 19:26:40.146580 Dram Type= 6, Freq= 0, CH_0, rank 0
7601 19:26:40.149659 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7602 19:26:40.150085 ==
7603 19:26:40.153199 [Gating] SW mode calibration
7604 19:26:40.159530 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7605 19:26:40.166242 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7606 19:26:40.169643 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7607 19:26:40.172996 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7608 19:26:40.179312 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7609 19:26:40.182844 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7610 19:26:40.185951 1 4 16 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (0 0)
7611 19:26:40.192259 1 4 20 | B1->B0 | 2323 3434 | 1 1 | (0 0) (1 1)
7612 19:26:40.195936 1 4 24 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
7613 19:26:40.199369 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7614 19:26:40.205581 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7615 19:26:40.209033 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7616 19:26:40.212193 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7617 19:26:40.218841 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7618 19:26:40.222131 1 5 16 | B1->B0 | 3434 2424 | 1 1 | (1 1) (1 0)
7619 19:26:40.225752 1 5 20 | B1->B0 | 3232 2323 | 0 0 | (0 0) (0 0)
7620 19:26:40.232474 1 5 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
7621 19:26:40.235198 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7622 19:26:40.238726 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7623 19:26:40.245227 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7624 19:26:40.248837 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7625 19:26:40.251721 1 6 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7626 19:26:40.258893 1 6 16 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
7627 19:26:40.261769 1 6 20 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
7628 19:26:40.265433 1 6 24 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
7629 19:26:40.268852 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7630 19:26:40.275173 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7631 19:26:40.278737 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7632 19:26:40.281842 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7633 19:26:40.288179 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7634 19:26:40.292072 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7635 19:26:40.294825 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7636 19:26:40.301732 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7637 19:26:40.305000 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7638 19:26:40.308418 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7639 19:26:40.314995 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 19:26:40.318038 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7641 19:26:40.321320 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7642 19:26:40.327912 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 19:26:40.331290 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7644 19:26:40.334427 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7645 19:26:40.341269 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7646 19:26:40.344870 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7647 19:26:40.348150 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7648 19:26:40.354524 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7649 19:26:40.358180 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7650 19:26:40.361146 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7651 19:26:40.367860 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7652 19:26:40.371027 Total UI for P1: 0, mck2ui 16
7653 19:26:40.374400 best dqsien dly found for B0: ( 1, 9, 14)
7654 19:26:40.377451 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7655 19:26:40.380764 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7656 19:26:40.384636 Total UI for P1: 0, mck2ui 16
7657 19:26:40.387478 best dqsien dly found for B1: ( 1, 9, 22)
7658 19:26:40.391094 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7659 19:26:40.394119 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7660 19:26:40.394536
7661 19:26:40.400962 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7662 19:26:40.404315 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7663 19:26:40.407884 [Gating] SW calibration Done
7664 19:26:40.408317 ==
7665 19:26:40.410735 Dram Type= 6, Freq= 0, CH_0, rank 0
7666 19:26:40.414306 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7667 19:26:40.414743 ==
7668 19:26:40.415072 RX Vref Scan: 0
7669 19:26:40.415376
7670 19:26:40.417866 RX Vref 0 -> 0, step: 1
7671 19:26:40.418280
7672 19:26:40.420796 RX Delay 0 -> 252, step: 8
7673 19:26:40.424081 iDelay=192, Bit 0, Center 127 (72 ~ 183) 112
7674 19:26:40.427247 iDelay=192, Bit 1, Center 131 (80 ~ 183) 104
7675 19:26:40.433882 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7676 19:26:40.437449 iDelay=192, Bit 3, Center 119 (64 ~ 175) 112
7677 19:26:40.440550 iDelay=192, Bit 4, Center 127 (72 ~ 183) 112
7678 19:26:40.443646 iDelay=192, Bit 5, Center 115 (64 ~ 167) 104
7679 19:26:40.447186 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7680 19:26:40.453944 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7681 19:26:40.456743 iDelay=192, Bit 8, Center 115 (56 ~ 175) 120
7682 19:26:40.460420 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7683 19:26:40.463912 iDelay=192, Bit 10, Center 123 (64 ~ 183) 120
7684 19:26:40.467544 iDelay=192, Bit 11, Center 119 (64 ~ 175) 112
7685 19:26:40.474159 iDelay=192, Bit 12, Center 127 (72 ~ 183) 112
7686 19:26:40.477071 iDelay=192, Bit 13, Center 131 (72 ~ 191) 120
7687 19:26:40.480694 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7688 19:26:40.483600 iDelay=192, Bit 15, Center 131 (72 ~ 191) 120
7689 19:26:40.484108 ==
7690 19:26:40.487068 Dram Type= 6, Freq= 0, CH_0, rank 0
7691 19:26:40.493177 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7692 19:26:40.493772 ==
7693 19:26:40.494283 DQS Delay:
7694 19:26:40.496755 DQS0 = 0, DQS1 = 0
7695 19:26:40.497289 DQM Delay:
7696 19:26:40.497738 DQM0 = 128, DQM1 = 124
7697 19:26:40.500285 DQ Delay:
7698 19:26:40.503732 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =119
7699 19:26:40.506563 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
7700 19:26:40.510153 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
7701 19:26:40.513144 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
7702 19:26:40.513781
7703 19:26:40.514263
7704 19:26:40.514779 ==
7705 19:26:40.516600 Dram Type= 6, Freq= 0, CH_0, rank 0
7706 19:26:40.520230 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7707 19:26:40.523162 ==
7708 19:26:40.523742
7709 19:26:40.524255
7710 19:26:40.524728 TX Vref Scan disable
7711 19:26:40.526799 == TX Byte 0 ==
7712 19:26:40.530493 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
7713 19:26:40.533330 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
7714 19:26:40.536530 == TX Byte 1 ==
7715 19:26:40.539931 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7716 19:26:40.543394 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7717 19:26:40.546381 ==
7718 19:26:40.549895 Dram Type= 6, Freq= 0, CH_0, rank 0
7719 19:26:40.552690 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7720 19:26:40.553292 ==
7721 19:26:40.566144
7722 19:26:40.569714 TX Vref early break, caculate TX vref
7723 19:26:40.573265 TX Vref=16, minBit 8, minWin=21, winSum=365
7724 19:26:40.576515 TX Vref=18, minBit 8, minWin=21, winSum=373
7725 19:26:40.579568 TX Vref=20, minBit 8, minWin=22, winSum=384
7726 19:26:40.583178 TX Vref=22, minBit 8, minWin=23, winSum=391
7727 19:26:40.586025 TX Vref=24, minBit 8, minWin=24, winSum=405
7728 19:26:40.592739 TX Vref=26, minBit 12, minWin=24, winSum=412
7729 19:26:40.595850 TX Vref=28, minBit 4, minWin=25, winSum=413
7730 19:26:40.599301 TX Vref=30, minBit 8, minWin=24, winSum=407
7731 19:26:40.602548 TX Vref=32, minBit 8, minWin=23, winSum=392
7732 19:26:40.605996 TX Vref=34, minBit 8, minWin=23, winSum=388
7733 19:26:40.612531 [TxChooseVref] Worse bit 4, Min win 25, Win sum 413, Final Vref 28
7734 19:26:40.613078
7735 19:26:40.616053 Final TX Range 0 Vref 28
7736 19:26:40.616469
7737 19:26:40.616792 ==
7738 19:26:40.619707 Dram Type= 6, Freq= 0, CH_0, rank 0
7739 19:26:40.622559 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7740 19:26:40.623088 ==
7741 19:26:40.623555
7742 19:26:40.624104
7743 19:26:40.626191 TX Vref Scan disable
7744 19:26:40.632566 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7745 19:26:40.633121 == TX Byte 0 ==
7746 19:26:40.636141 u2DelayCellOfst[0]=15 cells (4 PI)
7747 19:26:40.639112 u2DelayCellOfst[1]=15 cells (4 PI)
7748 19:26:40.642518 u2DelayCellOfst[2]=15 cells (4 PI)
7749 19:26:40.645852 u2DelayCellOfst[3]=15 cells (4 PI)
7750 19:26:40.649334 u2DelayCellOfst[4]=11 cells (3 PI)
7751 19:26:40.652173 u2DelayCellOfst[5]=0 cells (0 PI)
7752 19:26:40.655592 u2DelayCellOfst[6]=18 cells (5 PI)
7753 19:26:40.659325 u2DelayCellOfst[7]=15 cells (4 PI)
7754 19:26:40.662285 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7755 19:26:40.665858 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7756 19:26:40.669429 == TX Byte 1 ==
7757 19:26:40.672361 u2DelayCellOfst[8]=0 cells (0 PI)
7758 19:26:40.672779 u2DelayCellOfst[9]=0 cells (0 PI)
7759 19:26:40.675494 u2DelayCellOfst[10]=3 cells (1 PI)
7760 19:26:40.678875 u2DelayCellOfst[11]=0 cells (0 PI)
7761 19:26:40.682301 u2DelayCellOfst[12]=11 cells (3 PI)
7762 19:26:40.685703 u2DelayCellOfst[13]=7 cells (2 PI)
7763 19:26:40.688938 u2DelayCellOfst[14]=11 cells (3 PI)
7764 19:26:40.692373 u2DelayCellOfst[15]=7 cells (2 PI)
7765 19:26:40.695613 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7766 19:26:40.702198 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7767 19:26:40.702627 DramC Write-DBI on
7768 19:26:40.702953 ==
7769 19:26:40.705676 Dram Type= 6, Freq= 0, CH_0, rank 0
7770 19:26:40.711758 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7771 19:26:40.712237 ==
7772 19:26:40.712735
7773 19:26:40.713059
7774 19:26:40.713359 TX Vref Scan disable
7775 19:26:40.716242 == TX Byte 0 ==
7776 19:26:40.719237 Update DQM dly =738 (2 ,6, 34) DQM OEN =(3 ,3)
7777 19:26:40.722596 == TX Byte 1 ==
7778 19:26:40.725648 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7779 19:26:40.729101 DramC Write-DBI off
7780 19:26:40.729558
7781 19:26:40.729957 [DATLAT]
7782 19:26:40.730325 Freq=1600, CH0 RK0
7783 19:26:40.730636
7784 19:26:40.732802 DATLAT Default: 0xf
7785 19:26:40.733265 0, 0xFFFF, sum = 0
7786 19:26:40.735704 1, 0xFFFF, sum = 0
7787 19:26:40.739304 2, 0xFFFF, sum = 0
7788 19:26:40.739801 3, 0xFFFF, sum = 0
7789 19:26:40.742444 4, 0xFFFF, sum = 0
7790 19:26:40.742908 5, 0xFFFF, sum = 0
7791 19:26:40.745891 6, 0xFFFF, sum = 0
7792 19:26:40.746334 7, 0xFFFF, sum = 0
7793 19:26:40.748878 8, 0xFFFF, sum = 0
7794 19:26:40.749483 9, 0xFFFF, sum = 0
7795 19:26:40.752331 10, 0xFFFF, sum = 0
7796 19:26:40.752769 11, 0xFFFF, sum = 0
7797 19:26:40.755523 12, 0xFFFF, sum = 0
7798 19:26:40.756066 13, 0xFFFF, sum = 0
7799 19:26:40.758728 14, 0x0, sum = 1
7800 19:26:40.759163 15, 0x0, sum = 2
7801 19:26:40.762078 16, 0x0, sum = 3
7802 19:26:40.762514 17, 0x0, sum = 4
7803 19:26:40.765622 best_step = 15
7804 19:26:40.766049
7805 19:26:40.766476 ==
7806 19:26:40.768704 Dram Type= 6, Freq= 0, CH_0, rank 0
7807 19:26:40.772278 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7808 19:26:40.772780 ==
7809 19:26:40.775936 RX Vref Scan: 1
7810 19:26:40.776363
7811 19:26:40.776789 Set Vref Range= 24 -> 127
7812 19:26:40.777204
7813 19:26:40.778694 RX Vref 24 -> 127, step: 1
7814 19:26:40.779121
7815 19:26:40.782367 RX Delay 11 -> 252, step: 4
7816 19:26:40.782795
7817 19:26:40.785244 Set Vref, RX VrefLevel [Byte0]: 24
7818 19:26:40.788908 [Byte1]: 24
7819 19:26:40.789397
7820 19:26:40.792313 Set Vref, RX VrefLevel [Byte0]: 25
7821 19:26:40.795223 [Byte1]: 25
7822 19:26:40.798864
7823 19:26:40.799322 Set Vref, RX VrefLevel [Byte0]: 26
7824 19:26:40.801951 [Byte1]: 26
7825 19:26:40.805830
7826 19:26:40.805917 Set Vref, RX VrefLevel [Byte0]: 27
7827 19:26:40.809419 [Byte1]: 27
7828 19:26:40.813383
7829 19:26:40.813469 Set Vref, RX VrefLevel [Byte0]: 28
7830 19:26:40.816947 [Byte1]: 28
7831 19:26:40.821119
7832 19:26:40.821191 Set Vref, RX VrefLevel [Byte0]: 29
7833 19:26:40.824434 [Byte1]: 29
7834 19:26:40.828781
7835 19:26:40.828870 Set Vref, RX VrefLevel [Byte0]: 30
7836 19:26:40.832142 [Byte1]: 30
7837 19:26:40.836866
7838 19:26:40.836970 Set Vref, RX VrefLevel [Byte0]: 31
7839 19:26:40.839823 [Byte1]: 31
7840 19:26:40.844115
7841 19:26:40.844227 Set Vref, RX VrefLevel [Byte0]: 32
7842 19:26:40.847613 [Byte1]: 32
7843 19:26:40.851760
7844 19:26:40.851897 Set Vref, RX VrefLevel [Byte0]: 33
7845 19:26:40.855317 [Byte1]: 33
7846 19:26:40.859271
7847 19:26:40.859425 Set Vref, RX VrefLevel [Byte0]: 34
7848 19:26:40.862622 [Byte1]: 34
7849 19:26:40.866978
7850 19:26:40.867183 Set Vref, RX VrefLevel [Byte0]: 35
7851 19:26:40.870347 [Byte1]: 35
7852 19:26:40.874767
7853 19:26:40.875097 Set Vref, RX VrefLevel [Byte0]: 36
7854 19:26:40.878362 [Byte1]: 36
7855 19:26:40.882576
7856 19:26:40.882968 Set Vref, RX VrefLevel [Byte0]: 37
7857 19:26:40.885596 [Byte1]: 37
7858 19:26:40.890326
7859 19:26:40.890752 Set Vref, RX VrefLevel [Byte0]: 38
7860 19:26:40.893266 [Byte1]: 38
7861 19:26:40.897539
7862 19:26:40.897978 Set Vref, RX VrefLevel [Byte0]: 39
7863 19:26:40.901043 [Byte1]: 39
7864 19:26:40.905042
7865 19:26:40.905125 Set Vref, RX VrefLevel [Byte0]: 40
7866 19:26:40.908099 [Byte1]: 40
7867 19:26:40.912768
7868 19:26:40.912850 Set Vref, RX VrefLevel [Byte0]: 41
7869 19:26:40.916167 [Byte1]: 41
7870 19:26:40.920568
7871 19:26:40.920686 Set Vref, RX VrefLevel [Byte0]: 42
7872 19:26:40.923610 [Byte1]: 42
7873 19:26:40.927933
7874 19:26:40.928036 Set Vref, RX VrefLevel [Byte0]: 43
7875 19:26:40.930926 [Byte1]: 43
7876 19:26:40.935458
7877 19:26:40.935588 Set Vref, RX VrefLevel [Byte0]: 44
7878 19:26:40.939174 [Byte1]: 44
7879 19:26:40.943271
7880 19:26:40.943506 Set Vref, RX VrefLevel [Byte0]: 45
7881 19:26:40.946702 [Byte1]: 45
7882 19:26:40.950652
7883 19:26:40.950842 Set Vref, RX VrefLevel [Byte0]: 46
7884 19:26:40.954257 [Byte1]: 46
7885 19:26:40.958542
7886 19:26:40.958749 Set Vref, RX VrefLevel [Byte0]: 47
7887 19:26:40.961599 [Byte1]: 47
7888 19:26:40.966344
7889 19:26:40.966650 Set Vref, RX VrefLevel [Byte0]: 48
7890 19:26:40.969726 [Byte1]: 48
7891 19:26:40.974049
7892 19:26:40.974432 Set Vref, RX VrefLevel [Byte0]: 49
7893 19:26:40.977355 [Byte1]: 49
7894 19:26:40.981493
7895 19:26:40.981943 Set Vref, RX VrefLevel [Byte0]: 50
7896 19:26:40.984450 [Byte1]: 50
7897 19:26:40.989240
7898 19:26:40.989755 Set Vref, RX VrefLevel [Byte0]: 51
7899 19:26:40.992121 [Byte1]: 51
7900 19:26:40.997174
7901 19:26:40.997758 Set Vref, RX VrefLevel [Byte0]: 52
7902 19:26:40.999975 [Byte1]: 52
7903 19:26:41.004384
7904 19:26:41.004938 Set Vref, RX VrefLevel [Byte0]: 53
7905 19:26:41.007994 [Byte1]: 53
7906 19:26:41.012225
7907 19:26:41.012781 Set Vref, RX VrefLevel [Byte0]: 54
7908 19:26:41.015030 [Byte1]: 54
7909 19:26:41.019721
7910 19:26:41.020182 Set Vref, RX VrefLevel [Byte0]: 55
7911 19:26:41.022662 [Byte1]: 55
7912 19:26:41.027783
7913 19:26:41.028342 Set Vref, RX VrefLevel [Byte0]: 56
7914 19:26:41.030524 [Byte1]: 56
7915 19:26:41.035446
7916 19:26:41.036002 Set Vref, RX VrefLevel [Byte0]: 57
7917 19:26:41.038117 [Byte1]: 57
7918 19:26:41.042786
7919 19:26:41.043336 Set Vref, RX VrefLevel [Byte0]: 58
7920 19:26:41.045503 [Byte1]: 58
7921 19:26:41.050106
7922 19:26:41.050621 Set Vref, RX VrefLevel [Byte0]: 59
7923 19:26:41.053156 [Byte1]: 59
7924 19:26:41.057596
7925 19:26:41.058100 Set Vref, RX VrefLevel [Byte0]: 60
7926 19:26:41.061008 [Byte1]: 60
7927 19:26:41.065055
7928 19:26:41.065619 Set Vref, RX VrefLevel [Byte0]: 61
7929 19:26:41.068823 [Byte1]: 61
7930 19:26:41.072609
7931 19:26:41.073072 Set Vref, RX VrefLevel [Byte0]: 62
7932 19:26:41.075889 [Byte1]: 62
7933 19:26:41.080429
7934 19:26:41.080970 Set Vref, RX VrefLevel [Byte0]: 63
7935 19:26:41.083942 [Byte1]: 63
7936 19:26:41.088051
7937 19:26:41.088465 Set Vref, RX VrefLevel [Byte0]: 64
7938 19:26:41.091270 [Byte1]: 64
7939 19:26:41.096253
7940 19:26:41.096766 Set Vref, RX VrefLevel [Byte0]: 65
7941 19:26:41.099007 [Byte1]: 65
7942 19:26:41.103725
7943 19:26:41.104229 Set Vref, RX VrefLevel [Byte0]: 66
7944 19:26:41.106421 [Byte1]: 66
7945 19:26:41.110651
7946 19:26:41.111064 Set Vref, RX VrefLevel [Byte0]: 67
7947 19:26:41.114447 [Byte1]: 67
7948 19:26:41.118513
7949 19:26:41.119065 Set Vref, RX VrefLevel [Byte0]: 68
7950 19:26:41.121964 [Byte1]: 68
7951 19:26:41.126240
7952 19:26:41.126817 Set Vref, RX VrefLevel [Byte0]: 69
7953 19:26:41.129390 [Byte1]: 69
7954 19:26:41.133654
7955 19:26:41.134098 Set Vref, RX VrefLevel [Byte0]: 70
7956 19:26:41.137199 [Byte1]: 70
7957 19:26:41.141335
7958 19:26:41.141802 Set Vref, RX VrefLevel [Byte0]: 71
7959 19:26:41.144907 [Byte1]: 71
7960 19:26:41.148979
7961 19:26:41.149391 Set Vref, RX VrefLevel [Byte0]: 72
7962 19:26:41.152275 [Byte1]: 72
7963 19:26:41.156552
7964 19:26:41.156958 Set Vref, RX VrefLevel [Byte0]: 73
7965 19:26:41.159542 [Byte1]: 73
7966 19:26:41.164036
7967 19:26:41.164505 Set Vref, RX VrefLevel [Byte0]: 74
7968 19:26:41.167186 [Byte1]: 74
7969 19:26:41.171985
7970 19:26:41.172455 Set Vref, RX VrefLevel [Byte0]: 75
7971 19:26:41.174931 [Byte1]: 75
7972 19:26:41.179211
7973 19:26:41.179702 Set Vref, RX VrefLevel [Byte0]: 76
7974 19:26:41.182532 [Byte1]: 76
7975 19:26:41.186869
7976 19:26:41.187253 Final RX Vref Byte 0 = 63 to rank0
7977 19:26:41.189816 Final RX Vref Byte 1 = 60 to rank0
7978 19:26:41.193121 Final RX Vref Byte 0 = 63 to rank1
7979 19:26:41.196355 Final RX Vref Byte 1 = 60 to rank1==
7980 19:26:41.199912 Dram Type= 6, Freq= 0, CH_0, rank 0
7981 19:26:41.206487 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7982 19:26:41.206582 ==
7983 19:26:41.206650 DQS Delay:
7984 19:26:41.209892 DQS0 = 0, DQS1 = 0
7985 19:26:41.209976 DQM Delay:
7986 19:26:41.210041 DQM0 = 126, DQM1 = 119
7987 19:26:41.212796 DQ Delay:
7988 19:26:41.216208 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
7989 19:26:41.220008 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =138
7990 19:26:41.223117 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
7991 19:26:41.226256 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =128
7992 19:26:41.226343
7993 19:26:41.226410
7994 19:26:41.226472
7995 19:26:41.229778 [DramC_TX_OE_Calibration] TA2
7996 19:26:41.233342 Original DQ_B0 (3 6) =30, OEN = 27
7997 19:26:41.236261 Original DQ_B1 (3 6) =30, OEN = 27
7998 19:26:41.239700 24, 0x0, End_B0=24 End_B1=24
7999 19:26:41.239811 25, 0x0, End_B0=25 End_B1=25
8000 19:26:41.242714 26, 0x0, End_B0=26 End_B1=26
8001 19:26:41.246224 27, 0x0, End_B0=27 End_B1=27
8002 19:26:41.249781 28, 0x0, End_B0=28 End_B1=28
8003 19:26:41.252719 29, 0x0, End_B0=29 End_B1=29
8004 19:26:41.252871 30, 0x0, End_B0=30 End_B1=30
8005 19:26:41.256428 31, 0x4545, End_B0=30 End_B1=30
8006 19:26:41.259859 Byte0 end_step=30 best_step=27
8007 19:26:41.262816 Byte1 end_step=30 best_step=27
8008 19:26:41.266207 Byte0 TX OE(2T, 0.5T) = (3, 3)
8009 19:26:41.269339 Byte1 TX OE(2T, 0.5T) = (3, 3)
8010 19:26:41.269661
8011 19:26:41.269852
8012 19:26:41.276175 [DQSOSCAuto] RK0, (LSB)MR18= 0x1514, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
8013 19:26:41.280001 CH0 RK0: MR19=303, MR18=1514
8014 19:26:41.286261 CH0_RK0: MR19=0x303, MR18=0x1514, DQSOSC=399, MR23=63, INC=23, DEC=15
8015 19:26:41.286654
8016 19:26:41.289468 ----->DramcWriteLeveling(PI) begin...
8017 19:26:41.289884 ==
8018 19:26:41.293193 Dram Type= 6, Freq= 0, CH_0, rank 1
8019 19:26:41.296489 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8020 19:26:41.296932 ==
8021 19:26:41.299437 Write leveling (Byte 0): 34 => 34
8022 19:26:41.303275 Write leveling (Byte 1): 29 => 29
8023 19:26:41.306088 DramcWriteLeveling(PI) end<-----
8024 19:26:41.306510
8025 19:26:41.306834 ==
8026 19:26:41.309558 Dram Type= 6, Freq= 0, CH_0, rank 1
8027 19:26:41.312933 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8028 19:26:41.313354 ==
8029 19:26:41.316146 [Gating] SW mode calibration
8030 19:26:41.322851 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8031 19:26:41.329136 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8032 19:26:41.332559 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8033 19:26:41.339217 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8034 19:26:41.342266 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8035 19:26:41.345931 1 4 12 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 1)
8036 19:26:41.352359 1 4 16 | B1->B0 | 2828 3434 | 1 1 | (0 0) (1 1)
8037 19:26:41.355949 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8038 19:26:41.358887 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8039 19:26:41.365948 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8040 19:26:41.368793 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8041 19:26:41.372394 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8042 19:26:41.379133 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8043 19:26:41.382473 1 5 12 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (1 0)
8044 19:26:41.385595 1 5 16 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
8045 19:26:41.392257 1 5 20 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
8046 19:26:41.395401 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8047 19:26:41.398989 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8048 19:26:41.405906 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8049 19:26:41.408782 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8050 19:26:41.412380 1 6 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8051 19:26:41.415242 1 6 12 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
8052 19:26:41.421871 1 6 16 | B1->B0 | 2d2d 4646 | 1 0 | (0 0) (0 0)
8053 19:26:41.425419 1 6 20 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
8054 19:26:41.428829 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8055 19:26:41.435340 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8056 19:26:41.438619 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8057 19:26:41.441406 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8058 19:26:41.447838 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8059 19:26:41.451459 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8060 19:26:41.454986 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8061 19:26:41.461374 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8062 19:26:41.464464 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8063 19:26:41.467915 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8064 19:26:41.474426 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8065 19:26:41.478019 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8066 19:26:41.481063 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8067 19:26:41.487712 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8068 19:26:41.490703 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8069 19:26:41.494260 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8070 19:26:41.501164 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8071 19:26:41.504400 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8072 19:26:41.507353 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8073 19:26:41.514194 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8074 19:26:41.517602 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8075 19:26:41.521276 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8076 19:26:41.527888 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8077 19:26:41.528001 Total UI for P1: 0, mck2ui 16
8078 19:26:41.534387 best dqsien dly found for B0: ( 1, 9, 10)
8079 19:26:41.537318 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8080 19:26:41.540907 Total UI for P1: 0, mck2ui 16
8081 19:26:41.544454 best dqsien dly found for B1: ( 1, 9, 16)
8082 19:26:41.547528 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8083 19:26:41.551111 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8084 19:26:41.551294
8085 19:26:41.554068 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8086 19:26:41.557629 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8087 19:26:41.560764 [Gating] SW calibration Done
8088 19:26:41.561030 ==
8089 19:26:41.564385 Dram Type= 6, Freq= 0, CH_0, rank 1
8090 19:26:41.570893 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8091 19:26:41.571293 ==
8092 19:26:41.571663 RX Vref Scan: 0
8093 19:26:41.571980
8094 19:26:41.574211 RX Vref 0 -> 0, step: 1
8095 19:26:41.574564
8096 19:26:41.577465 RX Delay 0 -> 252, step: 8
8097 19:26:41.581107 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8098 19:26:41.583903 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8099 19:26:41.587431 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8100 19:26:41.590823 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8101 19:26:41.597099 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8102 19:26:41.600679 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8103 19:26:41.603773 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8104 19:26:41.607354 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8105 19:26:41.610561 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8106 19:26:41.616956 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8107 19:26:41.620478 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8108 19:26:41.623679 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8109 19:26:41.627005 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8110 19:26:41.633608 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
8111 19:26:41.637111 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8112 19:26:41.640563 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8113 19:26:41.640920 ==
8114 19:26:41.643684 Dram Type= 6, Freq= 0, CH_0, rank 1
8115 19:26:41.646717 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8116 19:26:41.647154 ==
8117 19:26:41.650282 DQS Delay:
8118 19:26:41.650698 DQS0 = 0, DQS1 = 0
8119 19:26:41.653191 DQM Delay:
8120 19:26:41.653695 DQM0 = 128, DQM1 = 121
8121 19:26:41.654032 DQ Delay:
8122 19:26:41.660250 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
8123 19:26:41.663123 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
8124 19:26:41.666534 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
8125 19:26:41.670003 DQ12 =127, DQ13 =127, DQ14 =131, DQ15 =127
8126 19:26:41.670458
8127 19:26:41.671225
8128 19:26:41.671854 ==
8129 19:26:41.673596 Dram Type= 6, Freq= 0, CH_0, rank 1
8130 19:26:41.676451 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8131 19:26:41.677183 ==
8132 19:26:41.677989
8133 19:26:41.678656
8134 19:26:41.679973 TX Vref Scan disable
8135 19:26:41.683162 == TX Byte 0 ==
8136 19:26:41.686607 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8137 19:26:41.689506 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8138 19:26:41.693175 == TX Byte 1 ==
8139 19:26:41.696262 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8140 19:26:41.700165 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8141 19:26:41.700605 ==
8142 19:26:41.702909 Dram Type= 6, Freq= 0, CH_0, rank 1
8143 19:26:41.709451 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8144 19:26:41.709929 ==
8145 19:26:41.722756
8146 19:26:41.726112 TX Vref early break, caculate TX vref
8147 19:26:41.728878 TX Vref=16, minBit 0, minWin=22, winSum=371
8148 19:26:41.732646 TX Vref=18, minBit 0, minWin=22, winSum=375
8149 19:26:41.735634 TX Vref=20, minBit 1, minWin=23, winSum=385
8150 19:26:41.738969 TX Vref=22, minBit 0, minWin=24, winSum=397
8151 19:26:41.742325 TX Vref=24, minBit 0, minWin=24, winSum=402
8152 19:26:41.748728 TX Vref=26, minBit 0, minWin=24, winSum=402
8153 19:26:41.752450 TX Vref=28, minBit 2, minWin=25, winSum=415
8154 19:26:41.755318 TX Vref=30, minBit 11, minWin=24, winSum=409
8155 19:26:41.758924 TX Vref=32, minBit 13, minWin=23, winSum=398
8156 19:26:41.761894 TX Vref=34, minBit 4, minWin=24, winSum=397
8157 19:26:41.768399 TX Vref=36, minBit 8, minWin=22, winSum=385
8158 19:26:41.771835 [TxChooseVref] Worse bit 2, Min win 25, Win sum 415, Final Vref 28
8159 19:26:41.772242
8160 19:26:41.775183 Final TX Range 0 Vref 28
8161 19:26:41.775601
8162 19:26:41.775971 ==
8163 19:26:41.778609 Dram Type= 6, Freq= 0, CH_0, rank 1
8164 19:26:41.782170 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8165 19:26:41.785054 ==
8166 19:26:41.785451
8167 19:26:41.785821
8168 19:26:41.786156 TX Vref Scan disable
8169 19:26:41.791739 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8170 19:26:41.792224 == TX Byte 0 ==
8171 19:26:41.795352 u2DelayCellOfst[0]=15 cells (4 PI)
8172 19:26:41.798937 u2DelayCellOfst[1]=18 cells (5 PI)
8173 19:26:41.802031 u2DelayCellOfst[2]=11 cells (3 PI)
8174 19:26:41.805622 u2DelayCellOfst[3]=11 cells (3 PI)
8175 19:26:41.808878 u2DelayCellOfst[4]=7 cells (2 PI)
8176 19:26:41.812115 u2DelayCellOfst[5]=0 cells (0 PI)
8177 19:26:41.815461 u2DelayCellOfst[6]=18 cells (5 PI)
8178 19:26:41.818517 u2DelayCellOfst[7]=18 cells (5 PI)
8179 19:26:41.821691 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8180 19:26:41.825580 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8181 19:26:41.828430 == TX Byte 1 ==
8182 19:26:41.831567 u2DelayCellOfst[8]=0 cells (0 PI)
8183 19:26:41.834945 u2DelayCellOfst[9]=0 cells (0 PI)
8184 19:26:41.838534 u2DelayCellOfst[10]=7 cells (2 PI)
8185 19:26:41.841841 u2DelayCellOfst[11]=3 cells (1 PI)
8186 19:26:41.844959 u2DelayCellOfst[12]=11 cells (3 PI)
8187 19:26:41.845350 u2DelayCellOfst[13]=7 cells (2 PI)
8188 19:26:41.847933 u2DelayCellOfst[14]=15 cells (4 PI)
8189 19:26:41.851363 u2DelayCellOfst[15]=7 cells (2 PI)
8190 19:26:41.858256 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8191 19:26:41.861231 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8192 19:26:41.861778 DramC Write-DBI on
8193 19:26:41.864954 ==
8194 19:26:41.867986 Dram Type= 6, Freq= 0, CH_0, rank 1
8195 19:26:41.871587 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8196 19:26:41.872008 ==
8197 19:26:41.872340
8198 19:26:41.872644
8199 19:26:41.874533 TX Vref Scan disable
8200 19:26:41.874951 == TX Byte 0 ==
8201 19:26:41.881312 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8202 19:26:41.881826 == TX Byte 1 ==
8203 19:26:41.884736 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8204 19:26:41.887546 DramC Write-DBI off
8205 19:26:41.887964
8206 19:26:41.888290 [DATLAT]
8207 19:26:41.891247 Freq=1600, CH0 RK1
8208 19:26:41.891768
8209 19:26:41.892197 DATLAT Default: 0xf
8210 19:26:41.894398 0, 0xFFFF, sum = 0
8211 19:26:41.894973 1, 0xFFFF, sum = 0
8212 19:26:41.897825 2, 0xFFFF, sum = 0
8213 19:26:41.898387 3, 0xFFFF, sum = 0
8214 19:26:41.900899 4, 0xFFFF, sum = 0
8215 19:26:41.901412 5, 0xFFFF, sum = 0
8216 19:26:41.904696 6, 0xFFFF, sum = 0
8217 19:26:41.907679 7, 0xFFFF, sum = 0
8218 19:26:41.908143 8, 0xFFFF, sum = 0
8219 19:26:41.910700 9, 0xFFFF, sum = 0
8220 19:26:41.911163 10, 0xFFFF, sum = 0
8221 19:26:41.914391 11, 0xFFFF, sum = 0
8222 19:26:41.914840 12, 0xFFFF, sum = 0
8223 19:26:41.917402 13, 0xCFFF, sum = 0
8224 19:26:41.917898 14, 0x0, sum = 1
8225 19:26:41.920714 15, 0x0, sum = 2
8226 19:26:41.921149 16, 0x0, sum = 3
8227 19:26:41.924105 17, 0x0, sum = 4
8228 19:26:41.924565 best_step = 15
8229 19:26:41.924896
8230 19:26:41.925201 ==
8231 19:26:41.927143 Dram Type= 6, Freq= 0, CH_0, rank 1
8232 19:26:41.930479 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8233 19:26:41.933929 ==
8234 19:26:41.934348 RX Vref Scan: 0
8235 19:26:41.934677
8236 19:26:41.937493 RX Vref 0 -> 0, step: 1
8237 19:26:41.937951
8238 19:26:41.938279 RX Delay 3 -> 252, step: 4
8239 19:26:41.944567 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8240 19:26:41.947972 iDelay=191, Bit 1, Center 126 (71 ~ 182) 112
8241 19:26:41.951289 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8242 19:26:41.954838 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8243 19:26:41.958007 iDelay=191, Bit 4, Center 122 (67 ~ 178) 112
8244 19:26:41.964465 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8245 19:26:41.968115 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8246 19:26:41.971155 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8247 19:26:41.974289 iDelay=191, Bit 8, Center 110 (55 ~ 166) 112
8248 19:26:41.977796 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8249 19:26:41.984692 iDelay=191, Bit 10, Center 120 (63 ~ 178) 116
8250 19:26:41.987909 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8251 19:26:41.990748 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8252 19:26:41.994395 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8253 19:26:42.001120 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8254 19:26:42.004521 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8255 19:26:42.004940 ==
8256 19:26:42.007544 Dram Type= 6, Freq= 0, CH_0, rank 1
8257 19:26:42.010980 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8258 19:26:42.011427 ==
8259 19:26:42.014489 DQS Delay:
8260 19:26:42.014962 DQS0 = 0, DQS1 = 0
8261 19:26:42.015363 DQM Delay:
8262 19:26:42.017365 DQM0 = 124, DQM1 = 118
8263 19:26:42.017859 DQ Delay:
8264 19:26:42.021039 DQ0 =124, DQ1 =126, DQ2 =122, DQ3 =122
8265 19:26:42.024069 DQ4 =122, DQ5 =112, DQ6 =134, DQ7 =134
8266 19:26:42.027519 DQ8 =110, DQ9 =104, DQ10 =120, DQ11 =112
8267 19:26:42.033716 DQ12 =124, DQ13 =122, DQ14 =128, DQ15 =124
8268 19:26:42.034149
8269 19:26:42.034479
8270 19:26:42.034782
8271 19:26:42.037196 [DramC_TX_OE_Calibration] TA2
8272 19:26:42.037739 Original DQ_B0 (3 6) =30, OEN = 27
8273 19:26:42.040678 Original DQ_B1 (3 6) =30, OEN = 27
8274 19:26:42.044150 24, 0x0, End_B0=24 End_B1=24
8275 19:26:42.047157 25, 0x0, End_B0=25 End_B1=25
8276 19:26:42.050599 26, 0x0, End_B0=26 End_B1=26
8277 19:26:42.053984 27, 0x0, End_B0=27 End_B1=27
8278 19:26:42.054433 28, 0x0, End_B0=28 End_B1=28
8279 19:26:42.057582 29, 0x0, End_B0=29 End_B1=29
8280 19:26:42.060550 30, 0x0, End_B0=30 End_B1=30
8281 19:26:42.064292 31, 0x4141, End_B0=30 End_B1=30
8282 19:26:42.067296 Byte0 end_step=30 best_step=27
8283 19:26:42.067737 Byte1 end_step=30 best_step=27
8284 19:26:42.070528 Byte0 TX OE(2T, 0.5T) = (3, 3)
8285 19:26:42.073695 Byte1 TX OE(2T, 0.5T) = (3, 3)
8286 19:26:42.074147
8287 19:26:42.074485
8288 19:26:42.083848 [DQSOSCAuto] RK1, (LSB)MR18= 0x2412, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
8289 19:26:42.084279 CH0 RK1: MR19=303, MR18=2412
8290 19:26:42.090468 CH0_RK1: MR19=0x303, MR18=0x2412, DQSOSC=391, MR23=63, INC=24, DEC=16
8291 19:26:42.093637 [RxdqsGatingPostProcess] freq 1600
8292 19:26:42.100668 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8293 19:26:42.103478 best DQS0 dly(2T, 0.5T) = (1, 1)
8294 19:26:42.106903 best DQS1 dly(2T, 0.5T) = (1, 1)
8295 19:26:42.110538 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8296 19:26:42.113916 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8297 19:26:42.114320 best DQS0 dly(2T, 0.5T) = (1, 1)
8298 19:26:42.116800 best DQS1 dly(2T, 0.5T) = (1, 1)
8299 19:26:42.120541 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8300 19:26:42.123488 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8301 19:26:42.127265 Pre-setting of DQS Precalculation
8302 19:26:42.133673 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8303 19:26:42.134089 ==
8304 19:26:42.137070 Dram Type= 6, Freq= 0, CH_1, rank 0
8305 19:26:42.139873 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8306 19:26:42.140311 ==
8307 19:26:42.146970 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8308 19:26:42.150323 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8309 19:26:42.153325 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8310 19:26:42.159920 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8311 19:26:42.168798 [CA 0] Center 41 (13~70) winsize 58
8312 19:26:42.172289 [CA 1] Center 42 (12~72) winsize 61
8313 19:26:42.175868 [CA 2] Center 37 (8~66) winsize 59
8314 19:26:42.179010 [CA 3] Center 36 (7~66) winsize 60
8315 19:26:42.182265 [CA 4] Center 37 (8~67) winsize 60
8316 19:26:42.185794 [CA 5] Center 36 (7~66) winsize 60
8317 19:26:42.186213
8318 19:26:42.189032 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8319 19:26:42.189451
8320 19:26:42.192077 [CATrainingPosCal] consider 1 rank data
8321 19:26:42.195516 u2DelayCellTimex100 = 258/100 ps
8322 19:26:42.198830 CA0 delay=41 (13~70),Diff = 5 PI (18 cell)
8323 19:26:42.205366 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8324 19:26:42.208861 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8325 19:26:42.212196 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8326 19:26:42.215489 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8327 19:26:42.218773 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8328 19:26:42.219198
8329 19:26:42.222280 CA PerBit enable=1, Macro0, CA PI delay=36
8330 19:26:42.222776
8331 19:26:42.225295 [CBTSetCACLKResult] CA Dly = 36
8332 19:26:42.228931 CS Dly: 9 (0~40)
8333 19:26:42.231838 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8334 19:26:42.235364 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8335 19:26:42.235790 ==
8336 19:26:42.238972 Dram Type= 6, Freq= 0, CH_1, rank 1
8337 19:26:42.241805 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8338 19:26:42.242279 ==
8339 19:26:42.248822 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8340 19:26:42.252065 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8341 19:26:42.258755 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8342 19:26:42.261561 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8343 19:26:42.272285 [CA 0] Center 42 (12~72) winsize 61
8344 19:26:42.275121 [CA 1] Center 42 (12~72) winsize 61
8345 19:26:42.278900 [CA 2] Center 38 (9~67) winsize 59
8346 19:26:42.281832 [CA 3] Center 36 (7~66) winsize 60
8347 19:26:42.285613 [CA 4] Center 38 (8~68) winsize 61
8348 19:26:42.288674 [CA 5] Center 36 (6~66) winsize 61
8349 19:26:42.289091
8350 19:26:42.292057 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8351 19:26:42.292473
8352 19:26:42.294957 [CATrainingPosCal] consider 2 rank data
8353 19:26:42.298805 u2DelayCellTimex100 = 258/100 ps
8354 19:26:42.302006 CA0 delay=41 (13~70),Diff = 5 PI (18 cell)
8355 19:26:42.308633 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8356 19:26:42.311947 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8357 19:26:42.315151 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8358 19:26:42.318448 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8359 19:26:42.321575 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8360 19:26:42.321999
8361 19:26:42.325757 CA PerBit enable=1, Macro0, CA PI delay=36
8362 19:26:42.326224
8363 19:26:42.328791 [CBTSetCACLKResult] CA Dly = 36
8364 19:26:42.331880 CS Dly: 11 (0~44)
8365 19:26:42.335009 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8366 19:26:42.338489 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8367 19:26:42.338571
8368 19:26:42.341379 ----->DramcWriteLeveling(PI) begin...
8369 19:26:42.341490 ==
8370 19:26:42.345035 Dram Type= 6, Freq= 0, CH_1, rank 0
8371 19:26:42.348072 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8372 19:26:42.351415 ==
8373 19:26:42.355064 Write leveling (Byte 0): 24 => 24
8374 19:26:42.355158 Write leveling (Byte 1): 30 => 30
8375 19:26:42.358254 DramcWriteLeveling(PI) end<-----
8376 19:26:42.358355
8377 19:26:42.358435 ==
8378 19:26:42.361412 Dram Type= 6, Freq= 0, CH_1, rank 0
8379 19:26:42.367879 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8380 19:26:42.368002 ==
8381 19:26:42.371422 [Gating] SW mode calibration
8382 19:26:42.377952 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8383 19:26:42.381452 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8384 19:26:42.388223 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8385 19:26:42.391108 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8386 19:26:42.394456 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8387 19:26:42.401201 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8388 19:26:42.404132 1 4 16 | B1->B0 | 3333 3231 | 1 1 | (0 0) (1 1)
8389 19:26:42.407640 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8390 19:26:42.414164 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8391 19:26:42.417637 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8392 19:26:42.421189 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8393 19:26:42.427460 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8394 19:26:42.430894 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8395 19:26:42.434105 1 5 12 | B1->B0 | 3434 3333 | 0 1 | (0 0) (1 0)
8396 19:26:42.441052 1 5 16 | B1->B0 | 2525 2323 | 0 0 | (0 1) (1 0)
8397 19:26:42.444000 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8398 19:26:42.447560 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8399 19:26:42.450545 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8400 19:26:42.457207 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8401 19:26:42.460730 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8402 19:26:42.463708 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8403 19:26:42.470586 1 6 12 | B1->B0 | 2d2d 2525 | 0 0 | (0 0) (0 0)
8404 19:26:42.474146 1 6 16 | B1->B0 | 4545 4444 | 0 0 | (0 0) (0 0)
8405 19:26:42.477027 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8406 19:26:42.484094 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8407 19:26:42.487069 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8408 19:26:42.490693 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8409 19:26:42.497356 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8410 19:26:42.500289 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8411 19:26:42.503826 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8412 19:26:42.510482 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8413 19:26:42.513771 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8414 19:26:42.516770 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8415 19:26:42.523479 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8416 19:26:42.526749 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8417 19:26:42.530314 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8418 19:26:42.536680 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8419 19:26:42.540177 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8420 19:26:42.543656 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8421 19:26:42.549942 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8422 19:26:42.553368 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8423 19:26:42.556851 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8424 19:26:42.563460 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8425 19:26:42.566390 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8426 19:26:42.569931 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8427 19:26:42.576545 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8428 19:26:42.579826 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8429 19:26:42.583526 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8430 19:26:42.586405 Total UI for P1: 0, mck2ui 16
8431 19:26:42.590109 best dqsien dly found for B0: ( 1, 9, 14)
8432 19:26:42.593211 Total UI for P1: 0, mck2ui 16
8433 19:26:42.597008 best dqsien dly found for B1: ( 1, 9, 16)
8434 19:26:42.599818 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8435 19:26:42.603429 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8436 19:26:42.603511
8437 19:26:42.610035 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8438 19:26:42.613406 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8439 19:26:42.613488 [Gating] SW calibration Done
8440 19:26:42.616720 ==
8441 19:26:42.619791 Dram Type= 6, Freq= 0, CH_1, rank 0
8442 19:26:42.623505 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8443 19:26:42.623588 ==
8444 19:26:42.623652 RX Vref Scan: 0
8445 19:26:42.623712
8446 19:26:42.626161 RX Vref 0 -> 0, step: 1
8447 19:26:42.626243
8448 19:26:42.629703 RX Delay 0 -> 252, step: 8
8449 19:26:42.633176 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8450 19:26:42.636353 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8451 19:26:42.639719 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8452 19:26:42.646428 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8453 19:26:42.649881 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8454 19:26:42.653081 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8455 19:26:42.656560 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8456 19:26:42.659755 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8457 19:26:42.666386 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8458 19:26:42.669788 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8459 19:26:42.672622 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8460 19:26:42.676005 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8461 19:26:42.679621 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8462 19:26:42.685932 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8463 19:26:42.689245 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8464 19:26:42.692466 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8465 19:26:42.692574 ==
8466 19:26:42.695967 Dram Type= 6, Freq= 0, CH_1, rank 0
8467 19:26:42.699441 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8468 19:26:42.702745 ==
8469 19:26:42.702827 DQS Delay:
8470 19:26:42.702892 DQS0 = 0, DQS1 = 0
8471 19:26:42.705894 DQM Delay:
8472 19:26:42.705996 DQM0 = 132, DQM1 = 125
8473 19:26:42.709008 DQ Delay:
8474 19:26:42.712633 DQ0 =135, DQ1 =131, DQ2 =119, DQ3 =131
8475 19:26:42.715659 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8476 19:26:42.719156 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8477 19:26:42.722709 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =135
8478 19:26:42.722786
8479 19:26:42.722849
8480 19:26:42.722908 ==
8481 19:26:42.725668 Dram Type= 6, Freq= 0, CH_1, rank 0
8482 19:26:42.729060 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8483 19:26:42.729136 ==
8484 19:26:42.732484
8485 19:26:42.732577
8486 19:26:42.732640 TX Vref Scan disable
8487 19:26:42.735956 == TX Byte 0 ==
8488 19:26:42.738991 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8489 19:26:42.742595 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8490 19:26:42.745768 == TX Byte 1 ==
8491 19:26:42.748917 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8492 19:26:42.752338 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8493 19:26:42.752421 ==
8494 19:26:42.755928 Dram Type= 6, Freq= 0, CH_1, rank 0
8495 19:26:42.762316 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8496 19:26:42.762399 ==
8497 19:26:42.774306
8498 19:26:42.777897 TX Vref early break, caculate TX vref
8499 19:26:42.780803 TX Vref=16, minBit 8, minWin=21, winSum=360
8500 19:26:42.784420 TX Vref=18, minBit 8, minWin=21, winSum=371
8501 19:26:42.787295 TX Vref=20, minBit 8, minWin=22, winSum=379
8502 19:26:42.790934 TX Vref=22, minBit 8, minWin=23, winSum=391
8503 19:26:42.794262 TX Vref=24, minBit 8, minWin=24, winSum=402
8504 19:26:42.800752 TX Vref=26, minBit 11, minWin=23, winSum=408
8505 19:26:42.804110 TX Vref=28, minBit 9, minWin=24, winSum=414
8506 19:26:42.807391 TX Vref=30, minBit 8, minWin=24, winSum=410
8507 19:26:42.811146 TX Vref=32, minBit 9, minWin=23, winSum=398
8508 19:26:42.814612 TX Vref=34, minBit 8, minWin=22, winSum=388
8509 19:26:42.820604 [TxChooseVref] Worse bit 9, Min win 24, Win sum 414, Final Vref 28
8510 19:26:42.820759
8511 19:26:42.824576 Final TX Range 0 Vref 28
8512 19:26:42.824728
8513 19:26:42.824846 ==
8514 19:26:42.827503 Dram Type= 6, Freq= 0, CH_1, rank 0
8515 19:26:42.830423 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8516 19:26:42.830594 ==
8517 19:26:42.830729
8518 19:26:42.830855
8519 19:26:42.833834 TX Vref Scan disable
8520 19:26:42.840625 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8521 19:26:42.840864 == TX Byte 0 ==
8522 19:26:42.844402 u2DelayCellOfst[0]=18 cells (5 PI)
8523 19:26:42.847451 u2DelayCellOfst[1]=11 cells (3 PI)
8524 19:26:42.850936 u2DelayCellOfst[2]=0 cells (0 PI)
8525 19:26:42.854324 u2DelayCellOfst[3]=7 cells (2 PI)
8526 19:26:42.857271 u2DelayCellOfst[4]=7 cells (2 PI)
8527 19:26:42.860967 u2DelayCellOfst[5]=22 cells (6 PI)
8528 19:26:42.863829 u2DelayCellOfst[6]=18 cells (5 PI)
8529 19:26:42.867413 u2DelayCellOfst[7]=7 cells (2 PI)
8530 19:26:42.870804 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8531 19:26:42.874038 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8532 19:26:42.876879 == TX Byte 1 ==
8533 19:26:42.880547 u2DelayCellOfst[8]=0 cells (0 PI)
8534 19:26:42.881223 u2DelayCellOfst[9]=7 cells (2 PI)
8535 19:26:42.883577 u2DelayCellOfst[10]=11 cells (3 PI)
8536 19:26:42.887096 u2DelayCellOfst[11]=7 cells (2 PI)
8537 19:26:42.890789 u2DelayCellOfst[12]=15 cells (4 PI)
8538 19:26:42.893550 u2DelayCellOfst[13]=18 cells (5 PI)
8539 19:26:42.897171 u2DelayCellOfst[14]=18 cells (5 PI)
8540 19:26:42.900052 u2DelayCellOfst[15]=18 cells (5 PI)
8541 19:26:42.903512 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8542 19:26:42.910375 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8543 19:26:42.910904 DramC Write-DBI on
8544 19:26:42.911386 ==
8545 19:26:42.913622 Dram Type= 6, Freq= 0, CH_1, rank 0
8546 19:26:42.919848 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8547 19:26:42.920268 ==
8548 19:26:42.920597
8549 19:26:42.920965
8550 19:26:42.921263 TX Vref Scan disable
8551 19:26:42.924181 == TX Byte 0 ==
8552 19:26:42.927232 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8553 19:26:42.930612 == TX Byte 1 ==
8554 19:26:42.933969 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8555 19:26:42.937186 DramC Write-DBI off
8556 19:26:42.937768
8557 19:26:42.938145 [DATLAT]
8558 19:26:42.938462 Freq=1600, CH1 RK0
8559 19:26:42.938784
8560 19:26:42.940409 DATLAT Default: 0xf
8561 19:26:42.943649 0, 0xFFFF, sum = 0
8562 19:26:42.944124 1, 0xFFFF, sum = 0
8563 19:26:42.947137 2, 0xFFFF, sum = 0
8564 19:26:42.947566 3, 0xFFFF, sum = 0
8565 19:26:42.950655 4, 0xFFFF, sum = 0
8566 19:26:42.951082 5, 0xFFFF, sum = 0
8567 19:26:42.953647 6, 0xFFFF, sum = 0
8568 19:26:42.954166 7, 0xFFFF, sum = 0
8569 19:26:42.956910 8, 0xFFFF, sum = 0
8570 19:26:42.957336 9, 0xFFFF, sum = 0
8571 19:26:42.960275 10, 0xFFFF, sum = 0
8572 19:26:42.960728 11, 0xFFFF, sum = 0
8573 19:26:42.963887 12, 0xFFFF, sum = 0
8574 19:26:42.964328 13, 0x8FFF, sum = 0
8575 19:26:42.966824 14, 0x0, sum = 1
8576 19:26:42.967249 15, 0x0, sum = 2
8577 19:26:42.970435 16, 0x0, sum = 3
8578 19:26:42.970879 17, 0x0, sum = 4
8579 19:26:42.973889 best_step = 15
8580 19:26:42.974328
8581 19:26:42.974764 ==
8582 19:26:42.976773 Dram Type= 6, Freq= 0, CH_1, rank 0
8583 19:26:42.980011 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8584 19:26:42.980449 ==
8585 19:26:42.983503 RX Vref Scan: 1
8586 19:26:42.984001
8587 19:26:42.984438 Set Vref Range= 24 -> 127
8588 19:26:42.984856
8589 19:26:42.986930 RX Vref 24 -> 127, step: 1
8590 19:26:42.987395
8591 19:26:42.990036 RX Delay 11 -> 252, step: 4
8592 19:26:42.990474
8593 19:26:42.993556 Set Vref, RX VrefLevel [Byte0]: 24
8594 19:26:42.996742 [Byte1]: 24
8595 19:26:42.997180
8596 19:26:43.000213 Set Vref, RX VrefLevel [Byte0]: 25
8597 19:26:43.003172 [Byte1]: 25
8598 19:26:43.006802
8599 19:26:43.007237 Set Vref, RX VrefLevel [Byte0]: 26
8600 19:26:43.010359 [Byte1]: 26
8601 19:26:43.014410
8602 19:26:43.014846 Set Vref, RX VrefLevel [Byte0]: 27
8603 19:26:43.017758 [Byte1]: 27
8604 19:26:43.021857
8605 19:26:43.022291 Set Vref, RX VrefLevel [Byte0]: 28
8606 19:26:43.025492 [Byte1]: 28
8607 19:26:43.029753
8608 19:26:43.030184 Set Vref, RX VrefLevel [Byte0]: 29
8609 19:26:43.032639 [Byte1]: 29
8610 19:26:43.036846
8611 19:26:43.036930 Set Vref, RX VrefLevel [Byte0]: 30
8612 19:26:43.039896 [Byte1]: 30
8613 19:26:43.044403
8614 19:26:43.044487 Set Vref, RX VrefLevel [Byte0]: 31
8615 19:26:43.047870 [Byte1]: 31
8616 19:26:43.052239
8617 19:26:43.052336 Set Vref, RX VrefLevel [Byte0]: 32
8618 19:26:43.055323 [Byte1]: 32
8619 19:26:43.060089
8620 19:26:43.060195 Set Vref, RX VrefLevel [Byte0]: 33
8621 19:26:43.063211 [Byte1]: 33
8622 19:26:43.067380
8623 19:26:43.067507 Set Vref, RX VrefLevel [Byte0]: 34
8624 19:26:43.071108 [Byte1]: 34
8625 19:26:43.074989
8626 19:26:43.075129 Set Vref, RX VrefLevel [Byte0]: 35
8627 19:26:43.078548 [Byte1]: 35
8628 19:26:43.082565
8629 19:26:43.082745 Set Vref, RX VrefLevel [Byte0]: 36
8630 19:26:43.086037 [Byte1]: 36
8631 19:26:43.090185
8632 19:26:43.090394 Set Vref, RX VrefLevel [Byte0]: 37
8633 19:26:43.093797 [Byte1]: 37
8634 19:26:43.097909
8635 19:26:43.098219 Set Vref, RX VrefLevel [Byte0]: 38
8636 19:26:43.101595 [Byte1]: 38
8637 19:26:43.105923
8638 19:26:43.106323 Set Vref, RX VrefLevel [Byte0]: 39
8639 19:26:43.109020 [Byte1]: 39
8640 19:26:43.113301
8641 19:26:43.113782 Set Vref, RX VrefLevel [Byte0]: 40
8642 19:26:43.116820 [Byte1]: 40
8643 19:26:43.121097
8644 19:26:43.121568 Set Vref, RX VrefLevel [Byte0]: 41
8645 19:26:43.124102 [Byte1]: 41
8646 19:26:43.128670
8647 19:26:43.129221 Set Vref, RX VrefLevel [Byte0]: 42
8648 19:26:43.132021 [Byte1]: 42
8649 19:26:43.135979
8650 19:26:43.136568 Set Vref, RX VrefLevel [Byte0]: 43
8651 19:26:43.139744 [Byte1]: 43
8652 19:26:43.143645
8653 19:26:43.144064 Set Vref, RX VrefLevel [Byte0]: 44
8654 19:26:43.147089 [Byte1]: 44
8655 19:26:43.151184
8656 19:26:43.151624 Set Vref, RX VrefLevel [Byte0]: 45
8657 19:26:43.154962 [Byte1]: 45
8658 19:26:43.158793
8659 19:26:43.159243 Set Vref, RX VrefLevel [Byte0]: 46
8660 19:26:43.162420 [Byte1]: 46
8661 19:26:43.166452
8662 19:26:43.166890 Set Vref, RX VrefLevel [Byte0]: 47
8663 19:26:43.170116 [Byte1]: 47
8664 19:26:43.174480
8665 19:26:43.174904 Set Vref, RX VrefLevel [Byte0]: 48
8666 19:26:43.177373 [Byte1]: 48
8667 19:26:43.181940
8668 19:26:43.182363 Set Vref, RX VrefLevel [Byte0]: 49
8669 19:26:43.185416 [Byte1]: 49
8670 19:26:43.189598
8671 19:26:43.190163 Set Vref, RX VrefLevel [Byte0]: 50
8672 19:26:43.192645 [Byte1]: 50
8673 19:26:43.197382
8674 19:26:43.197886 Set Vref, RX VrefLevel [Byte0]: 51
8675 19:26:43.200232 [Byte1]: 51
8676 19:26:43.204701
8677 19:26:43.205123 Set Vref, RX VrefLevel [Byte0]: 52
8678 19:26:43.207860 [Byte1]: 52
8679 19:26:43.212548
8680 19:26:43.212971 Set Vref, RX VrefLevel [Byte0]: 53
8681 19:26:43.215589 [Byte1]: 53
8682 19:26:43.219725
8683 19:26:43.220147 Set Vref, RX VrefLevel [Byte0]: 54
8684 19:26:43.223360 [Byte1]: 54
8685 19:26:43.227511
8686 19:26:43.227962 Set Vref, RX VrefLevel [Byte0]: 55
8687 19:26:43.230534 [Byte1]: 55
8688 19:26:43.234988
8689 19:26:43.235411 Set Vref, RX VrefLevel [Byte0]: 56
8690 19:26:43.238597 [Byte1]: 56
8691 19:26:43.243103
8692 19:26:43.243602 Set Vref, RX VrefLevel [Byte0]: 57
8693 19:26:43.246133 [Byte1]: 57
8694 19:26:43.250419
8695 19:26:43.250932 Set Vref, RX VrefLevel [Byte0]: 58
8696 19:26:43.253477 [Byte1]: 58
8697 19:26:43.257901
8698 19:26:43.258353 Set Vref, RX VrefLevel [Byte0]: 59
8699 19:26:43.261242 [Byte1]: 59
8700 19:26:43.265372
8701 19:26:43.266007 Set Vref, RX VrefLevel [Byte0]: 60
8702 19:26:43.269179 [Byte1]: 60
8703 19:26:43.273261
8704 19:26:43.273864 Set Vref, RX VrefLevel [Byte0]: 61
8705 19:26:43.276268 [Byte1]: 61
8706 19:26:43.280849
8707 19:26:43.281441 Set Vref, RX VrefLevel [Byte0]: 62
8708 19:26:43.283777 [Byte1]: 62
8709 19:26:43.288007
8710 19:26:43.288161 Set Vref, RX VrefLevel [Byte0]: 63
8711 19:26:43.291312 [Byte1]: 63
8712 19:26:43.295588
8713 19:26:43.295688 Set Vref, RX VrefLevel [Byte0]: 64
8714 19:26:43.298844 [Byte1]: 64
8715 19:26:43.303178
8716 19:26:43.303285 Set Vref, RX VrefLevel [Byte0]: 65
8717 19:26:43.306795 [Byte1]: 65
8718 19:26:43.310836
8719 19:26:43.310930 Set Vref, RX VrefLevel [Byte0]: 66
8720 19:26:43.314675 [Byte1]: 66
8721 19:26:43.318282
8722 19:26:43.318384 Set Vref, RX VrefLevel [Byte0]: 67
8723 19:26:43.322004 [Byte1]: 67
8724 19:26:43.326246
8725 19:26:43.326354 Set Vref, RX VrefLevel [Byte0]: 68
8726 19:26:43.329787 [Byte1]: 68
8727 19:26:43.334030
8728 19:26:43.334173 Set Vref, RX VrefLevel [Byte0]: 69
8729 19:26:43.336993 [Byte1]: 69
8730 19:26:43.341689
8731 19:26:43.341854 Set Vref, RX VrefLevel [Byte0]: 70
8732 19:26:43.344560 [Byte1]: 70
8733 19:26:43.348907
8734 19:26:43.349083 Set Vref, RX VrefLevel [Byte0]: 71
8735 19:26:43.352341 [Byte1]: 71
8736 19:26:43.356752
8737 19:26:43.356971 Set Vref, RX VrefLevel [Byte0]: 72
8738 19:26:43.360177 [Byte1]: 72
8739 19:26:43.364063
8740 19:26:43.364324 Set Vref, RX VrefLevel [Byte0]: 73
8741 19:26:43.367863 [Byte1]: 73
8742 19:26:43.372399
8743 19:26:43.372709 Final RX Vref Byte 0 = 59 to rank0
8744 19:26:43.375338 Final RX Vref Byte 1 = 53 to rank0
8745 19:26:43.378429 Final RX Vref Byte 0 = 59 to rank1
8746 19:26:43.382147 Final RX Vref Byte 1 = 53 to rank1==
8747 19:26:43.384960 Dram Type= 6, Freq= 0, CH_1, rank 0
8748 19:26:43.392036 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8749 19:26:43.392476 ==
8750 19:26:43.392914 DQS Delay:
8751 19:26:43.394836 DQS0 = 0, DQS1 = 0
8752 19:26:43.395390 DQM Delay:
8753 19:26:43.395869 DQM0 = 130, DQM1 = 123
8754 19:26:43.398333 DQ Delay:
8755 19:26:43.401749 DQ0 =138, DQ1 =126, DQ2 =120, DQ3 =126
8756 19:26:43.404762 DQ4 =126, DQ5 =142, DQ6 =140, DQ7 =126
8757 19:26:43.408280 DQ8 =108, DQ9 =114, DQ10 =122, DQ11 =116
8758 19:26:43.411462 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8759 19:26:43.411894
8760 19:26:43.412221
8761 19:26:43.412652
8762 19:26:43.414809 [DramC_TX_OE_Calibration] TA2
8763 19:26:43.418552 Original DQ_B0 (3 6) =30, OEN = 27
8764 19:26:43.421415 Original DQ_B1 (3 6) =30, OEN = 27
8765 19:26:43.425128 24, 0x0, End_B0=24 End_B1=24
8766 19:26:43.427920 25, 0x0, End_B0=25 End_B1=25
8767 19:26:43.428483 26, 0x0, End_B0=26 End_B1=26
8768 19:26:43.431486 27, 0x0, End_B0=27 End_B1=27
8769 19:26:43.434599 28, 0x0, End_B0=28 End_B1=28
8770 19:26:43.438174 29, 0x0, End_B0=29 End_B1=29
8771 19:26:43.438623 30, 0x0, End_B0=30 End_B1=30
8772 19:26:43.441181 31, 0x5151, End_B0=30 End_B1=30
8773 19:26:43.444854 Byte0 end_step=30 best_step=27
8774 19:26:43.447812 Byte1 end_step=30 best_step=27
8775 19:26:43.451580 Byte0 TX OE(2T, 0.5T) = (3, 3)
8776 19:26:43.455027 Byte1 TX OE(2T, 0.5T) = (3, 3)
8777 19:26:43.455604
8778 19:26:43.456185
8779 19:26:43.460788 [DQSOSCAuto] RK0, (LSB)MR18= 0x70b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 406 ps
8780 19:26:43.464447 CH1 RK0: MR19=303, MR18=70B
8781 19:26:43.470913 CH1_RK0: MR19=0x303, MR18=0x70B, DQSOSC=404, MR23=63, INC=22, DEC=15
8782 19:26:43.471380
8783 19:26:43.474596 ----->DramcWriteLeveling(PI) begin...
8784 19:26:43.475034 ==
8785 19:26:43.477615 Dram Type= 6, Freq= 0, CH_1, rank 1
8786 19:26:43.480849 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8787 19:26:43.481314 ==
8788 19:26:43.484250 Write leveling (Byte 0): 26 => 26
8789 19:26:43.487834 Write leveling (Byte 1): 28 => 28
8790 19:26:43.490856 DramcWriteLeveling(PI) end<-----
8791 19:26:43.491307
8792 19:26:43.491631 ==
8793 19:26:43.494503 Dram Type= 6, Freq= 0, CH_1, rank 1
8794 19:26:43.497445 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8795 19:26:43.498031 ==
8796 19:26:43.500879 [Gating] SW mode calibration
8797 19:26:43.507575 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8798 19:26:43.513850 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8799 19:26:43.517503 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8800 19:26:43.524248 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8801 19:26:43.526921 1 4 8 | B1->B0 | 2323 3434 | 1 1 | (1 1) (1 1)
8802 19:26:43.530450 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8803 19:26:43.536768 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8804 19:26:43.540194 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8805 19:26:43.543733 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8806 19:26:43.550486 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8807 19:26:43.553407 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8808 19:26:43.557087 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8809 19:26:43.563819 1 5 8 | B1->B0 | 3434 2c2c | 1 0 | (1 0) (0 0)
8810 19:26:43.566982 1 5 12 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
8811 19:26:43.570022 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8812 19:26:43.576618 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8813 19:26:43.580066 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8814 19:26:43.583259 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8815 19:26:43.589853 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8816 19:26:43.593083 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8817 19:26:43.596285 1 6 8 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
8818 19:26:43.603253 1 6 12 | B1->B0 | 4444 4646 | 1 0 | (0 0) (0 0)
8819 19:26:43.606060 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8820 19:26:43.609437 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8821 19:26:43.616172 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8822 19:26:43.619315 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8823 19:26:43.622286 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8824 19:26:43.628779 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8825 19:26:43.632209 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8826 19:26:43.635825 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8827 19:26:43.642413 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8828 19:26:43.645347 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8829 19:26:43.648859 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8830 19:26:43.655591 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8831 19:26:43.658945 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8832 19:26:43.662006 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8833 19:26:43.668484 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8834 19:26:43.672083 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8835 19:26:43.675695 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8836 19:26:43.681658 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8837 19:26:43.685222 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8838 19:26:43.688951 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8839 19:26:43.695203 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8840 19:26:43.698771 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8841 19:26:43.701921 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8842 19:26:43.708423 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8843 19:26:43.711635 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8844 19:26:43.714957 Total UI for P1: 0, mck2ui 16
8845 19:26:43.718630 best dqsien dly found for B0: ( 1, 9, 10)
8846 19:26:43.721715 Total UI for P1: 0, mck2ui 16
8847 19:26:43.725001 best dqsien dly found for B1: ( 1, 9, 10)
8848 19:26:43.728240 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8849 19:26:43.731770 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8850 19:26:43.732073
8851 19:26:43.735403 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8852 19:26:43.738605 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8853 19:26:43.742133 [Gating] SW calibration Done
8854 19:26:43.742559 ==
8855 19:26:43.744918 Dram Type= 6, Freq= 0, CH_1, rank 1
8856 19:26:43.748595 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8857 19:26:43.751672 ==
8858 19:26:43.752093 RX Vref Scan: 0
8859 19:26:43.752427
8860 19:26:43.755013 RX Vref 0 -> 0, step: 1
8861 19:26:43.755528
8862 19:26:43.755907 RX Delay 0 -> 252, step: 8
8863 19:26:43.761652 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8864 19:26:43.764910 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8865 19:26:43.768224 iDelay=200, Bit 2, Center 115 (56 ~ 175) 120
8866 19:26:43.771829 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8867 19:26:43.775052 iDelay=200, Bit 4, Center 123 (64 ~ 183) 120
8868 19:26:43.781768 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8869 19:26:43.784776 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8870 19:26:43.788401 iDelay=200, Bit 7, Center 127 (64 ~ 191) 128
8871 19:26:43.791324 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8872 19:26:43.794962 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8873 19:26:43.801372 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8874 19:26:43.804622 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8875 19:26:43.807763 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8876 19:26:43.811159 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8877 19:26:43.817963 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8878 19:26:43.821187 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8879 19:26:43.821640 ==
8880 19:26:43.824247 Dram Type= 6, Freq= 0, CH_1, rank 1
8881 19:26:43.828073 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8882 19:26:43.828529 ==
8883 19:26:43.831249 DQS Delay:
8884 19:26:43.831670 DQS0 = 0, DQS1 = 0
8885 19:26:43.832005 DQM Delay:
8886 19:26:43.834596 DQM0 = 128, DQM1 = 127
8887 19:26:43.835018 DQ Delay:
8888 19:26:43.837743 DQ0 =131, DQ1 =127, DQ2 =115, DQ3 =123
8889 19:26:43.840867 DQ4 =123, DQ5 =139, DQ6 =139, DQ7 =127
8890 19:26:43.847430 DQ8 =111, DQ9 =115, DQ10 =131, DQ11 =123
8891 19:26:43.850998 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =139
8892 19:26:43.851518
8893 19:26:43.851867
8894 19:26:43.852271 ==
8895 19:26:43.853975 Dram Type= 6, Freq= 0, CH_1, rank 1
8896 19:26:43.857695 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8897 19:26:43.858140 ==
8898 19:26:43.858503
8899 19:26:43.858813
8900 19:26:43.860720 TX Vref Scan disable
8901 19:26:43.861098 == TX Byte 0 ==
8902 19:26:43.867864 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8903 19:26:43.870815 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8904 19:26:43.871223 == TX Byte 1 ==
8905 19:26:43.877571 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8906 19:26:43.880596 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8907 19:26:43.881150 ==
8908 19:26:43.884109 Dram Type= 6, Freq= 0, CH_1, rank 1
8909 19:26:43.887060 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8910 19:26:43.887605 ==
8911 19:26:43.902630
8912 19:26:43.906031 TX Vref early break, caculate TX vref
8913 19:26:43.908885 TX Vref=16, minBit 0, minWin=22, winSum=381
8914 19:26:43.912500 TX Vref=18, minBit 0, minWin=23, winSum=391
8915 19:26:43.915742 TX Vref=20, minBit 0, minWin=24, winSum=400
8916 19:26:43.919221 TX Vref=22, minBit 0, minWin=23, winSum=408
8917 19:26:43.922644 TX Vref=24, minBit 9, minWin=24, winSum=415
8918 19:26:43.928826 TX Vref=26, minBit 1, minWin=25, winSum=422
8919 19:26:43.932310 TX Vref=28, minBit 1, minWin=25, winSum=423
8920 19:26:43.935756 TX Vref=30, minBit 0, minWin=25, winSum=421
8921 19:26:43.939400 TX Vref=32, minBit 5, minWin=23, winSum=414
8922 19:26:43.942238 TX Vref=34, minBit 5, minWin=23, winSum=404
8923 19:26:43.945377 TX Vref=36, minBit 0, minWin=24, winSum=397
8924 19:26:43.952606 [TxChooseVref] Worse bit 1, Min win 25, Win sum 423, Final Vref 28
8925 19:26:43.953036
8926 19:26:43.955671 Final TX Range 0 Vref 28
8927 19:26:43.956088
8928 19:26:43.956445 ==
8929 19:26:43.958903 Dram Type= 6, Freq= 0, CH_1, rank 1
8930 19:26:43.962267 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8931 19:26:43.962708 ==
8932 19:26:43.963090
8933 19:26:43.963459
8934 19:26:43.965912 TX Vref Scan disable
8935 19:26:43.972121 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8936 19:26:43.972548 == TX Byte 0 ==
8937 19:26:43.975704 u2DelayCellOfst[0]=18 cells (5 PI)
8938 19:26:43.978761 u2DelayCellOfst[1]=15 cells (4 PI)
8939 19:26:43.982224 u2DelayCellOfst[2]=0 cells (0 PI)
8940 19:26:43.985200 u2DelayCellOfst[3]=7 cells (2 PI)
8941 19:26:43.988540 u2DelayCellOfst[4]=11 cells (3 PI)
8942 19:26:43.991847 u2DelayCellOfst[5]=18 cells (5 PI)
8943 19:26:43.995329 u2DelayCellOfst[6]=18 cells (5 PI)
8944 19:26:43.998446 u2DelayCellOfst[7]=3 cells (1 PI)
8945 19:26:44.002002 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8946 19:26:44.005459 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8947 19:26:44.008307 == TX Byte 1 ==
8948 19:26:44.011822 u2DelayCellOfst[8]=0 cells (0 PI)
8949 19:26:44.015378 u2DelayCellOfst[9]=7 cells (2 PI)
8950 19:26:44.018305 u2DelayCellOfst[10]=15 cells (4 PI)
8951 19:26:44.018729 u2DelayCellOfst[11]=7 cells (2 PI)
8952 19:26:44.021917 u2DelayCellOfst[12]=18 cells (5 PI)
8953 19:26:44.025011 u2DelayCellOfst[13]=18 cells (5 PI)
8954 19:26:44.028495 u2DelayCellOfst[14]=22 cells (6 PI)
8955 19:26:44.031478 u2DelayCellOfst[15]=18 cells (5 PI)
8956 19:26:44.037977 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8957 19:26:44.041649 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8958 19:26:44.042093 DramC Write-DBI on
8959 19:26:44.042419 ==
8960 19:26:44.044918 Dram Type= 6, Freq= 0, CH_1, rank 1
8961 19:26:44.051278 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8962 19:26:44.051736 ==
8963 19:26:44.052077
8964 19:26:44.052409
8965 19:26:44.052724 TX Vref Scan disable
8966 19:26:44.055773 == TX Byte 0 ==
8967 19:26:44.059124 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8968 19:26:44.062562 == TX Byte 1 ==
8969 19:26:44.065907 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8970 19:26:44.068726 DramC Write-DBI off
8971 19:26:44.069388
8972 19:26:44.070064 [DATLAT]
8973 19:26:44.070436 Freq=1600, CH1 RK1
8974 19:26:44.070794
8975 19:26:44.072368 DATLAT Default: 0xf
8976 19:26:44.072718 0, 0xFFFF, sum = 0
8977 19:26:44.075551 1, 0xFFFF, sum = 0
8978 19:26:44.078977 2, 0xFFFF, sum = 0
8979 19:26:44.079412 3, 0xFFFF, sum = 0
8980 19:26:44.082168 4, 0xFFFF, sum = 0
8981 19:26:44.082607 5, 0xFFFF, sum = 0
8982 19:26:44.085826 6, 0xFFFF, sum = 0
8983 19:26:44.086364 7, 0xFFFF, sum = 0
8984 19:26:44.088810 8, 0xFFFF, sum = 0
8985 19:26:44.089211 9, 0xFFFF, sum = 0
8986 19:26:44.091851 10, 0xFFFF, sum = 0
8987 19:26:44.092320 11, 0xFFFF, sum = 0
8988 19:26:44.095478 12, 0xFFFF, sum = 0
8989 19:26:44.096064 13, 0x8FFF, sum = 0
8990 19:26:44.098450 14, 0x0, sum = 1
8991 19:26:44.098883 15, 0x0, sum = 2
8992 19:26:44.101983 16, 0x0, sum = 3
8993 19:26:44.102707 17, 0x0, sum = 4
8994 19:26:44.105238 best_step = 15
8995 19:26:44.105767
8996 19:26:44.106100 ==
8997 19:26:44.108947 Dram Type= 6, Freq= 0, CH_1, rank 1
8998 19:26:44.112235 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8999 19:26:44.112662 ==
9000 19:26:44.115049 RX Vref Scan: 0
9001 19:26:44.115491
9002 19:26:44.115880 RX Vref 0 -> 0, step: 1
9003 19:26:44.116210
9004 19:26:44.118487 RX Delay 3 -> 252, step: 4
9005 19:26:44.125008 iDelay=195, Bit 0, Center 134 (79 ~ 190) 112
9006 19:26:44.128729 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
9007 19:26:44.131757 iDelay=195, Bit 2, Center 114 (59 ~ 170) 112
9008 19:26:44.135312 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
9009 19:26:44.138339 iDelay=195, Bit 4, Center 122 (67 ~ 178) 112
9010 19:26:44.145174 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
9011 19:26:44.148437 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
9012 19:26:44.151681 iDelay=195, Bit 7, Center 124 (67 ~ 182) 116
9013 19:26:44.154951 iDelay=195, Bit 8, Center 110 (51 ~ 170) 120
9014 19:26:44.158253 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
9015 19:26:44.164632 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9016 19:26:44.168319 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9017 19:26:44.171373 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
9018 19:26:44.174757 iDelay=195, Bit 13, Center 134 (79 ~ 190) 112
9019 19:26:44.178371 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
9020 19:26:44.185082 iDelay=195, Bit 15, Center 134 (79 ~ 190) 112
9021 19:26:44.185504 ==
9022 19:26:44.187975 Dram Type= 6, Freq= 0, CH_1, rank 1
9023 19:26:44.191625 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9024 19:26:44.192078 ==
9025 19:26:44.192407 DQS Delay:
9026 19:26:44.194539 DQS0 = 0, DQS1 = 0
9027 19:26:44.194975 DQM Delay:
9028 19:26:44.198227 DQM0 = 127, DQM1 = 125
9029 19:26:44.198687 DQ Delay:
9030 19:26:44.201144 DQ0 =134, DQ1 =126, DQ2 =114, DQ3 =124
9031 19:26:44.204557 DQ4 =122, DQ5 =138, DQ6 =138, DQ7 =124
9032 19:26:44.207682 DQ8 =110, DQ9 =112, DQ10 =128, DQ11 =120
9033 19:26:44.211394 DQ12 =132, DQ13 =134, DQ14 =130, DQ15 =134
9034 19:26:44.214747
9035 19:26:44.215396
9036 19:26:44.215960
9037 19:26:44.216510 [DramC_TX_OE_Calibration] TA2
9038 19:26:44.217810 Original DQ_B0 (3 6) =30, OEN = 27
9039 19:26:44.221081 Original DQ_B1 (3 6) =30, OEN = 27
9040 19:26:44.224430 24, 0x0, End_B0=24 End_B1=24
9041 19:26:44.227799 25, 0x0, End_B0=25 End_B1=25
9042 19:26:44.231079 26, 0x0, End_B0=26 End_B1=26
9043 19:26:44.231506 27, 0x0, End_B0=27 End_B1=27
9044 19:26:44.234453 28, 0x0, End_B0=28 End_B1=28
9045 19:26:44.237618 29, 0x0, End_B0=29 End_B1=29
9046 19:26:44.241161 30, 0x0, End_B0=30 End_B1=30
9047 19:26:44.244117 31, 0x4141, End_B0=30 End_B1=30
9048 19:26:44.244593 Byte0 end_step=30 best_step=27
9049 19:26:44.247714 Byte1 end_step=30 best_step=27
9050 19:26:44.250927 Byte0 TX OE(2T, 0.5T) = (3, 3)
9051 19:26:44.254267 Byte1 TX OE(2T, 0.5T) = (3, 3)
9052 19:26:44.254685
9053 19:26:44.255089
9054 19:26:44.261036 [DQSOSCAuto] RK1, (LSB)MR18= 0xe1a, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 402 ps
9055 19:26:44.264357 CH1 RK1: MR19=303, MR18=E1A
9056 19:26:44.270796 CH1_RK1: MR19=0x303, MR18=0xE1A, DQSOSC=396, MR23=63, INC=23, DEC=15
9057 19:26:44.274188 [RxdqsGatingPostProcess] freq 1600
9058 19:26:44.280807 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9059 19:26:44.283792 best DQS0 dly(2T, 0.5T) = (1, 1)
9060 19:26:44.284289 best DQS1 dly(2T, 0.5T) = (1, 1)
9061 19:26:44.287231 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9062 19:26:44.290862 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9063 19:26:44.293831 best DQS0 dly(2T, 0.5T) = (1, 1)
9064 19:26:44.297554 best DQS1 dly(2T, 0.5T) = (1, 1)
9065 19:26:44.300399 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9066 19:26:44.304028 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9067 19:26:44.307412 Pre-setting of DQS Precalculation
9068 19:26:44.310415 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9069 19:26:44.320400 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9070 19:26:44.326763 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9071 19:26:44.327234
9072 19:26:44.327579
9073 19:26:44.330493 [Calibration Summary] 3200 Mbps
9074 19:26:44.330960 CH 0, Rank 0
9075 19:26:44.333848 SW Impedance : PASS
9076 19:26:44.336886 DUTY Scan : NO K
9077 19:26:44.337360 ZQ Calibration : PASS
9078 19:26:44.340285 Jitter Meter : NO K
9079 19:26:44.340766 CBT Training : PASS
9080 19:26:44.343744 Write leveling : PASS
9081 19:26:44.347342 RX DQS gating : PASS
9082 19:26:44.347757 RX DQ/DQS(RDDQC) : PASS
9083 19:26:44.350019 TX DQ/DQS : PASS
9084 19:26:44.353615 RX DATLAT : PASS
9085 19:26:44.354035 RX DQ/DQS(Engine): PASS
9086 19:26:44.357078 TX OE : PASS
9087 19:26:44.357564 All Pass.
9088 19:26:44.357955
9089 19:26:44.360087 CH 0, Rank 1
9090 19:26:44.360738 SW Impedance : PASS
9091 19:26:44.363709 DUTY Scan : NO K
9092 19:26:44.366772 ZQ Calibration : PASS
9093 19:26:44.367399 Jitter Meter : NO K
9094 19:26:44.370135 CBT Training : PASS
9095 19:26:44.373223 Write leveling : PASS
9096 19:26:44.373855 RX DQS gating : PASS
9097 19:26:44.376451 RX DQ/DQS(RDDQC) : PASS
9098 19:26:44.379892 TX DQ/DQS : PASS
9099 19:26:44.380367 RX DATLAT : PASS
9100 19:26:44.383461 RX DQ/DQS(Engine): PASS
9101 19:26:44.386346 TX OE : PASS
9102 19:26:44.386968 All Pass.
9103 19:26:44.387456
9104 19:26:44.387912 CH 1, Rank 0
9105 19:26:44.389942 SW Impedance : PASS
9106 19:26:44.393427 DUTY Scan : NO K
9107 19:26:44.393974 ZQ Calibration : PASS
9108 19:26:44.396418 Jitter Meter : NO K
9109 19:26:44.397068 CBT Training : PASS
9110 19:26:44.399874 Write leveling : PASS
9111 19:26:44.403089 RX DQS gating : PASS
9112 19:26:44.403564 RX DQ/DQS(RDDQC) : PASS
9113 19:26:44.406592 TX DQ/DQS : PASS
9114 19:26:44.409805 RX DATLAT : PASS
9115 19:26:44.410422 RX DQ/DQS(Engine): PASS
9116 19:26:44.413327 TX OE : PASS
9117 19:26:44.413863 All Pass.
9118 19:26:44.414364
9119 19:26:44.416230 CH 1, Rank 1
9120 19:26:44.416765 SW Impedance : PASS
9121 19:26:44.419860 DUTY Scan : NO K
9122 19:26:44.422824 ZQ Calibration : PASS
9123 19:26:44.423435 Jitter Meter : NO K
9124 19:26:44.426365 CBT Training : PASS
9125 19:26:44.429315 Write leveling : PASS
9126 19:26:44.429812 RX DQS gating : PASS
9127 19:26:44.433146 RX DQ/DQS(RDDQC) : PASS
9128 19:26:44.436061 TX DQ/DQS : PASS
9129 19:26:44.436512 RX DATLAT : PASS
9130 19:26:44.439775 RX DQ/DQS(Engine): PASS
9131 19:26:44.442803 TX OE : PASS
9132 19:26:44.443227 All Pass.
9133 19:26:44.443560
9134 19:26:44.443870 DramC Write-DBI on
9135 19:26:44.445962 PER_BANK_REFRESH: Hybrid Mode
9136 19:26:44.449343 TX_TRACKING: ON
9137 19:26:44.456327 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9138 19:26:44.465915 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9139 19:26:44.472964 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9140 19:26:44.475884 [FAST_K] Save calibration result to emmc
9141 19:26:44.479446 sync common calibartion params.
9142 19:26:44.482768 sync cbt_mode0:1, 1:1
9143 19:26:44.483246 dram_init: ddr_geometry: 2
9144 19:26:44.485840 dram_init: ddr_geometry: 2
9145 19:26:44.489038 dram_init: ddr_geometry: 2
9146 19:26:44.489464 0:dram_rank_size:100000000
9147 19:26:44.492275 1:dram_rank_size:100000000
9148 19:26:44.499206 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9149 19:26:44.502189 DFS_SHUFFLE_HW_MODE: ON
9150 19:26:44.505815 dramc_set_vcore_voltage set vcore to 725000
9151 19:26:44.506238 Read voltage for 1600, 0
9152 19:26:44.508778 Vio18 = 0
9153 19:26:44.509327 Vcore = 725000
9154 19:26:44.509890 Vdram = 0
9155 19:26:44.512233 Vddq = 0
9156 19:26:44.512833 Vmddr = 0
9157 19:26:44.515307 switch to 3200 Mbps bootup
9158 19:26:44.515934 [DramcRunTimeConfig]
9159 19:26:44.516484 PHYPLL
9160 19:26:44.518787 DPM_CONTROL_AFTERK: ON
9161 19:26:44.522180 PER_BANK_REFRESH: ON
9162 19:26:44.525462 REFRESH_OVERHEAD_REDUCTION: ON
9163 19:26:44.525927 CMD_PICG_NEW_MODE: OFF
9164 19:26:44.529041 XRTWTW_NEW_MODE: ON
9165 19:26:44.529463 XRTRTR_NEW_MODE: ON
9166 19:26:44.532033 TX_TRACKING: ON
9167 19:26:44.532516 RDSEL_TRACKING: OFF
9168 19:26:44.535574 DQS Precalculation for DVFS: ON
9169 19:26:44.538613 RX_TRACKING: OFF
9170 19:26:44.539135 HW_GATING DBG: ON
9171 19:26:44.542184 ZQCS_ENABLE_LP4: ON
9172 19:26:44.542644 RX_PICG_NEW_MODE: ON
9173 19:26:44.545235 TX_PICG_NEW_MODE: ON
9174 19:26:44.545782 ENABLE_RX_DCM_DPHY: ON
9175 19:26:44.548839 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9176 19:26:44.551897 DUMMY_READ_FOR_TRACKING: OFF
9177 19:26:44.555798 !!! SPM_CONTROL_AFTERK: OFF
9178 19:26:44.558740 !!! SPM could not control APHY
9179 19:26:44.559220 IMPEDANCE_TRACKING: ON
9180 19:26:44.561614 TEMP_SENSOR: ON
9181 19:26:44.562078 HW_SAVE_FOR_SR: OFF
9182 19:26:44.565116 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9183 19:26:44.568609 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9184 19:26:44.571682 Read ODT Tracking: ON
9185 19:26:44.574905 Refresh Rate DeBounce: ON
9186 19:26:44.575410 DFS_NO_QUEUE_FLUSH: ON
9187 19:26:44.578470 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9188 19:26:44.581619 ENABLE_DFS_RUNTIME_MRW: OFF
9189 19:26:44.585120 DDR_RESERVE_NEW_MODE: ON
9190 19:26:44.585600 MR_CBT_SWITCH_FREQ: ON
9191 19:26:44.588318 =========================
9192 19:26:44.606984 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9193 19:26:44.610414 dram_init: ddr_geometry: 2
9194 19:26:44.628351 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9195 19:26:44.631443 dram_init: dram init end (result: 0)
9196 19:26:44.638120 DRAM-K: Full calibration passed in 24559 msecs
9197 19:26:44.641552 MRC: failed to locate region type 0.
9198 19:26:44.641650 DRAM rank0 size:0x100000000,
9199 19:26:44.644649 DRAM rank1 size=0x100000000
9200 19:26:44.654664 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9201 19:26:44.661221 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9202 19:26:44.667782 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9203 19:26:44.674791 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9204 19:26:44.677906 DRAM rank0 size:0x100000000,
9205 19:26:44.681395 DRAM rank1 size=0x100000000
9206 19:26:44.681498 CBMEM:
9207 19:26:44.684956 IMD: root @ 0xfffff000 254 entries.
9208 19:26:44.688252 IMD: root @ 0xffffec00 62 entries.
9209 19:26:44.691710 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9210 19:26:44.694539 WARNING: RO_VPD is uninitialized or empty.
9211 19:26:44.701176 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9212 19:26:44.708125 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9213 19:26:44.721290 read SPI 0x42894 0xe01e: 6227 us, 9213 KB/s, 73.704 Mbps
9214 19:26:44.732097 BS: romstage times (exec / console): total (unknown) / 24024 ms
9215 19:26:44.732180
9216 19:26:44.732244
9217 19:26:44.742159 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9218 19:26:44.745497 ARM64: Exception handlers installed.
9219 19:26:44.748820 ARM64: Testing exception
9220 19:26:44.752032 ARM64: Done test exception
9221 19:26:44.752115 Enumerating buses...
9222 19:26:44.755363 Show all devs... Before device enumeration.
9223 19:26:44.758874 Root Device: enabled 1
9224 19:26:44.761763 CPU_CLUSTER: 0: enabled 1
9225 19:26:44.761846 CPU: 00: enabled 1
9226 19:26:44.765327 Compare with tree...
9227 19:26:44.765409 Root Device: enabled 1
9228 19:26:44.768987 CPU_CLUSTER: 0: enabled 1
9229 19:26:44.771944 CPU: 00: enabled 1
9230 19:26:44.772026 Root Device scanning...
9231 19:26:44.775438 scan_static_bus for Root Device
9232 19:26:44.778524 CPU_CLUSTER: 0 enabled
9233 19:26:44.782127 scan_static_bus for Root Device done
9234 19:26:44.785066 scan_bus: bus Root Device finished in 8 msecs
9235 19:26:44.785148 done
9236 19:26:44.791577 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9237 19:26:44.795088 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9238 19:26:44.802608 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9239 19:26:44.805315 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9240 19:26:44.808501 Allocating resources...
9241 19:26:44.812313 Reading resources...
9242 19:26:44.815386 Root Device read_resources bus 0 link: 0
9243 19:26:44.818697 DRAM rank0 size:0x100000000,
9244 19:26:44.819121 DRAM rank1 size=0x100000000
9245 19:26:44.821827 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9246 19:26:44.825454 CPU: 00 missing read_resources
9247 19:26:44.831777 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9248 19:26:44.834855 Root Device read_resources bus 0 link: 0 done
9249 19:26:44.835280 Done reading resources.
9250 19:26:44.842055 Show resources in subtree (Root Device)...After reading.
9251 19:26:44.845408 Root Device child on link 0 CPU_CLUSTER: 0
9252 19:26:44.848592 CPU_CLUSTER: 0 child on link 0 CPU: 00
9253 19:26:44.858545 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9254 19:26:44.859206 CPU: 00
9255 19:26:44.861650 Root Device assign_resources, bus 0 link: 0
9256 19:26:44.864594 CPU_CLUSTER: 0 missing set_resources
9257 19:26:44.871810 Root Device assign_resources, bus 0 link: 0 done
9258 19:26:44.872270 Done setting resources.
9259 19:26:44.878092 Show resources in subtree (Root Device)...After assigning values.
9260 19:26:44.881201 Root Device child on link 0 CPU_CLUSTER: 0
9261 19:26:44.884740 CPU_CLUSTER: 0 child on link 0 CPU: 00
9262 19:26:44.894967 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9263 19:26:44.895524 CPU: 00
9264 19:26:44.898002 Done allocating resources.
9265 19:26:44.904497 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9266 19:26:44.904921 Enabling resources...
9267 19:26:44.905372 done.
9268 19:26:44.911050 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9269 19:26:44.911626 Initializing devices...
9270 19:26:44.914561 Root Device init
9271 19:26:44.917995 init hardware done!
9272 19:26:44.918691 0x00000018: ctrlr->caps
9273 19:26:44.921268 52.000 MHz: ctrlr->f_max
9274 19:26:44.921850 0.400 MHz: ctrlr->f_min
9275 19:26:44.924468 0x40ff8080: ctrlr->voltages
9276 19:26:44.927817 sclk: 390625
9277 19:26:44.928295 Bus Width = 1
9278 19:26:44.928716 sclk: 390625
9279 19:26:44.931208 Bus Width = 1
9280 19:26:44.931771 Early init status = 3
9281 19:26:44.937834 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9282 19:26:44.941181 in-header: 03 fc 00 00 01 00 00 00
9283 19:26:44.944335 in-data: 00
9284 19:26:44.947791 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9285 19:26:44.951273 in-header: 03 fd 00 00 00 00 00 00
9286 19:26:44.954594 in-data:
9287 19:26:44.957846 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9288 19:26:44.961424 in-header: 03 fc 00 00 01 00 00 00
9289 19:26:44.965163 in-data: 00
9290 19:26:44.967953 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9291 19:26:44.972366 in-header: 03 fd 00 00 00 00 00 00
9292 19:26:44.976061 in-data:
9293 19:26:44.979145 [SSUSB] Setting up USB HOST controller...
9294 19:26:44.982495 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9295 19:26:44.986027 [SSUSB] phy power-on done.
9296 19:26:44.989557 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9297 19:26:44.995674 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9298 19:26:44.999111 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9299 19:26:45.005804 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9300 19:26:45.012376 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9301 19:26:45.019047 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9302 19:26:45.026069 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9303 19:26:45.032520 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9304 19:26:45.035967 SPM: binary array size = 0x9dc
9305 19:26:45.038678 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9306 19:26:45.045408 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9307 19:26:45.052440 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9308 19:26:45.055295 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9309 19:26:45.061902 configure_display: Starting display init
9310 19:26:45.095736 anx7625_power_on_init: Init interface.
9311 19:26:45.099252 anx7625_disable_pd_protocol: Disabled PD feature.
9312 19:26:45.102104 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9313 19:26:45.129836 anx7625_start_dp_work: Secure OCM version=00
9314 19:26:45.133245 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9315 19:26:45.147790 sp_tx_get_edid_block: EDID Block = 1
9316 19:26:45.250754 Extracted contents:
9317 19:26:45.254008 header: 00 ff ff ff ff ff ff 00
9318 19:26:45.257136 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9319 19:26:45.260363 version: 01 04
9320 19:26:45.263461 basic params: 95 1f 11 78 0a
9321 19:26:45.266780 chroma info: 76 90 94 55 54 90 27 21 50 54
9322 19:26:45.270518 established: 00 00 00
9323 19:26:45.276970 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9324 19:26:45.280171 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9325 19:26:45.286592 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9326 19:26:45.293203 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9327 19:26:45.300434 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9328 19:26:45.303403 extensions: 00
9329 19:26:45.303484 checksum: fb
9330 19:26:45.303548
9331 19:26:45.306710 Manufacturer: IVO Model 57d Serial Number 0
9332 19:26:45.310118 Made week 0 of 2020
9333 19:26:45.313460 EDID version: 1.4
9334 19:26:45.313582 Digital display
9335 19:26:45.316712 6 bits per primary color channel
9336 19:26:45.316808 DisplayPort interface
9337 19:26:45.319943 Maximum image size: 31 cm x 17 cm
9338 19:26:45.323547 Gamma: 220%
9339 19:26:45.323649 Check DPMS levels
9340 19:26:45.326581 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9341 19:26:45.333476 First detailed timing is preferred timing
9342 19:26:45.333931 Established timings supported:
9343 19:26:45.337105 Standard timings supported:
9344 19:26:45.340117 Detailed timings
9345 19:26:45.343555 Hex of detail: 383680a07038204018303c0035ae10000019
9346 19:26:45.347245 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9347 19:26:45.353216 0780 0798 07c8 0820 hborder 0
9348 19:26:45.356815 0438 043b 0447 0458 vborder 0
9349 19:26:45.359874 -hsync -vsync
9350 19:26:45.360312 Did detailed timing
9351 19:26:45.366652 Hex of detail: 000000000000000000000000000000000000
9352 19:26:45.370140 Manufacturer-specified data, tag 0
9353 19:26:45.373873 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9354 19:26:45.377475 ASCII string: InfoVision
9355 19:26:45.380134 Hex of detail: 000000fe00523134304e574635205248200a
9356 19:26:45.383286 ASCII string: R140NWF5 RH
9357 19:26:45.383714 Checksum
9358 19:26:45.386918 Checksum: 0xfb (valid)
9359 19:26:45.390298 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9360 19:26:45.393241 DSI data_rate: 832800000 bps
9361 19:26:45.399836 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9362 19:26:45.403616 anx7625_parse_edid: pixelclock(138800).
9363 19:26:45.406636 hactive(1920), hsync(48), hfp(24), hbp(88)
9364 19:26:45.410035 vactive(1080), vsync(12), vfp(3), vbp(17)
9365 19:26:45.413478 anx7625_dsi_config: config dsi.
9366 19:26:45.419813 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9367 19:26:45.432824 anx7625_dsi_config: success to config DSI
9368 19:26:45.436446 anx7625_dp_start: MIPI phy setup OK.
9369 19:26:45.439344 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9370 19:26:45.442953 mtk_ddp_mode_set invalid vrefresh 60
9371 19:26:45.446006 main_disp_path_setup
9372 19:26:45.446424 ovl_layer_smi_id_en
9373 19:26:45.449668 ovl_layer_smi_id_en
9374 19:26:45.450086 ccorr_config
9375 19:26:45.450417 aal_config
9376 19:26:45.452751 gamma_config
9377 19:26:45.453168 postmask_config
9378 19:26:45.456327 dither_config
9379 19:26:45.459271 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9380 19:26:45.465737 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9381 19:26:45.469306 Root Device init finished in 551 msecs
9382 19:26:45.472785 CPU_CLUSTER: 0 init
9383 19:26:45.479307 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9384 19:26:45.485812 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9385 19:26:45.486233 APU_MBOX 0x190000b0 = 0x10001
9386 19:26:45.488951 APU_MBOX 0x190001b0 = 0x10001
9387 19:26:45.492005 APU_MBOX 0x190005b0 = 0x10001
9388 19:26:45.495686 APU_MBOX 0x190006b0 = 0x10001
9389 19:26:45.502152 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9390 19:26:45.511733 read SPI 0x539f4 0xe237: 6251 us, 9264 KB/s, 74.112 Mbps
9391 19:26:45.524104 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9392 19:26:45.530743 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9393 19:26:45.542624 read SPI 0x61c74 0xe8ef: 6412 us, 9299 KB/s, 74.392 Mbps
9394 19:26:45.551792 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9395 19:26:45.555480 CPU_CLUSTER: 0 init finished in 81 msecs
9396 19:26:45.558516 Devices initialized
9397 19:26:45.562064 Show all devs... After init.
9398 19:26:45.562552 Root Device: enabled 1
9399 19:26:45.565202 CPU_CLUSTER: 0: enabled 1
9400 19:26:45.568133 CPU: 00: enabled 1
9401 19:26:45.571691 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9402 19:26:45.574781 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9403 19:26:45.578281 ELOG: NV offset 0x57f000 size 0x1000
9404 19:26:45.584692 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9405 19:26:45.591496 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9406 19:26:45.594440 ELOG: Event(17) added with size 13 at 2024-04-18 19:26:45 UTC
9407 19:26:45.601411 out: cmd=0x121: 03 db 21 01 00 00 00 00
9408 19:26:45.604289 in-header: 03 6f 00 00 2c 00 00 00
9409 19:26:45.614311 in-data: f0 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9410 19:26:45.621087 ELOG: Event(A1) added with size 10 at 2024-04-18 19:26:45 UTC
9411 19:26:45.627991 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9412 19:26:45.634202 ELOG: Event(A0) added with size 9 at 2024-04-18 19:26:45 UTC
9413 19:26:45.637723 elog_add_boot_reason: Logged dev mode boot
9414 19:26:45.644225 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9415 19:26:45.644658 Finalize devices...
9416 19:26:45.647367 Devices finalized
9417 19:26:45.650829 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9418 19:26:45.654095 Writing coreboot table at 0xffe64000
9419 19:26:45.657188 0. 000000000010a000-0000000000113fff: RAMSTAGE
9420 19:26:45.663714 1. 0000000040000000-00000000400fffff: RAM
9421 19:26:45.667270 2. 0000000040100000-000000004032afff: RAMSTAGE
9422 19:26:45.670257 3. 000000004032b000-00000000545fffff: RAM
9423 19:26:45.673850 4. 0000000054600000-000000005465ffff: BL31
9424 19:26:45.676809 5. 0000000054660000-00000000ffe63fff: RAM
9425 19:26:45.683444 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9426 19:26:45.687086 7. 0000000100000000-000000023fffffff: RAM
9427 19:26:45.690547 Passing 5 GPIOs to payload:
9428 19:26:45.693433 NAME | PORT | POLARITY | VALUE
9429 19:26:45.700083 EC in RW | 0x000000aa | low | undefined
9430 19:26:45.703785 EC interrupt | 0x00000005 | low | undefined
9431 19:26:45.706806 TPM interrupt | 0x000000ab | high | undefined
9432 19:26:45.713175 SD card detect | 0x00000011 | high | undefined
9433 19:26:45.716865 speaker enable | 0x00000093 | high | undefined
9434 19:26:45.720205 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9435 19:26:45.723512 in-header: 03 f9 00 00 02 00 00 00
9436 19:26:45.726889 in-data: 02 00
9437 19:26:45.730419 ADC[4]: Raw value=895191 ID=7
9438 19:26:45.730854 ADC[3]: Raw value=213440 ID=1
9439 19:26:45.733226 RAM Code: 0x71
9440 19:26:45.736712 ADC[6]: Raw value=74722 ID=0
9441 19:26:45.739881 ADC[5]: Raw value=212700 ID=1
9442 19:26:45.740316 SKU Code: 0x1
9443 19:26:45.746406 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum aab5
9444 19:26:45.746840 coreboot table: 964 bytes.
9445 19:26:45.749860 IMD ROOT 0. 0xfffff000 0x00001000
9446 19:26:45.753186 IMD SMALL 1. 0xffffe000 0x00001000
9447 19:26:45.756201 RO MCACHE 2. 0xffffc000 0x00001104
9448 19:26:45.759343 CONSOLE 3. 0xfff7c000 0x00080000
9449 19:26:45.762899 FMAP 4. 0xfff7b000 0x00000452
9450 19:26:45.766287 TIME STAMP 5. 0xfff7a000 0x00000910
9451 19:26:45.769624 VBOOT WORK 6. 0xfff66000 0x00014000
9452 19:26:45.772528 RAMOOPS 7. 0xffe66000 0x00100000
9453 19:26:45.776029 COREBOOT 8. 0xffe64000 0x00002000
9454 19:26:45.779673 IMD small region:
9455 19:26:45.782729 IMD ROOT 0. 0xffffec00 0x00000400
9456 19:26:45.786222 VPD 1. 0xffffeb80 0x0000006c
9457 19:26:45.789109 MMC STATUS 2. 0xffffeb60 0x00000004
9458 19:26:45.792680 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9459 19:26:45.795655 Probing TPM: done!
9460 19:26:45.799796 Connected to device vid:did:rid of 1ae0:0028:00
9461 19:26:45.810460 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9462 19:26:45.814055 Initialized TPM device CR50 revision 0
9463 19:26:45.817119 Checking cr50 for pending updates
9464 19:26:45.821293 Reading cr50 TPM mode
9465 19:26:45.829776 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9466 19:26:45.836170 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9467 19:26:45.876939 read SPI 0x3990ec 0x4f1b0: 34860 us, 9294 KB/s, 74.352 Mbps
9468 19:26:45.880290 Checking segment from ROM address 0x40100000
9469 19:26:45.883255 Checking segment from ROM address 0x4010001c
9470 19:26:45.889865 Loading segment from ROM address 0x40100000
9471 19:26:45.890327 code (compression=0)
9472 19:26:45.900141 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9473 19:26:45.906845 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9474 19:26:45.907388 it's not compressed!
9475 19:26:45.913284 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9476 19:26:45.916725 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9477 19:26:45.936824 Loading segment from ROM address 0x4010001c
9478 19:26:45.937309 Entry Point 0x80000000
9479 19:26:45.940384 Loaded segments
9480 19:26:45.943775 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9481 19:26:45.950402 Jumping to boot code at 0x80000000(0xffe64000)
9482 19:26:45.956973 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9483 19:26:45.963689 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9484 19:26:45.971294 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9485 19:26:45.974638 Checking segment from ROM address 0x40100000
9486 19:26:45.977962 Checking segment from ROM address 0x4010001c
9487 19:26:45.984803 Loading segment from ROM address 0x40100000
9488 19:26:45.985409 code (compression=1)
9489 19:26:45.991154 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9490 19:26:46.001260 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9491 19:26:46.001781 using LZMA
9492 19:26:46.009920 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9493 19:26:46.016576 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9494 19:26:46.019864 Loading segment from ROM address 0x4010001c
9495 19:26:46.019938 Entry Point 0x54601000
9496 19:26:46.022852 Loaded segments
9497 19:26:46.026483 NOTICE: MT8192 bl31_setup
9498 19:26:46.032995 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9499 19:26:46.036401 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9500 19:26:46.039934 WARNING: region 0:
9501 19:26:46.043497 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9502 19:26:46.043582 WARNING: region 1:
9503 19:26:46.049728 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9504 19:26:46.052819 WARNING: region 2:
9505 19:26:46.056434 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9506 19:26:46.059813 WARNING: region 3:
9507 19:26:46.063359 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9508 19:26:46.066206 WARNING: region 4:
9509 19:26:46.073522 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9510 19:26:46.073622 WARNING: region 5:
9511 19:26:46.076187 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9512 19:26:46.079992 WARNING: region 6:
9513 19:26:46.083322 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9514 19:26:46.086692 WARNING: region 7:
9515 19:26:46.089734 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9516 19:26:46.096657 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9517 19:26:46.099582 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9518 19:26:46.103239 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9519 19:26:46.109392 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9520 19:26:46.113232 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9521 19:26:46.116190 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9522 19:26:46.122938 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9523 19:26:46.126654 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9524 19:26:46.133320 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9525 19:26:46.136363 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9526 19:26:46.140039 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9527 19:26:46.146481 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9528 19:26:46.149929 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9529 19:26:46.152967 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9530 19:26:46.159552 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9531 19:26:46.163207 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9532 19:26:46.169974 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9533 19:26:46.172861 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9534 19:26:46.176280 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9535 19:26:46.182911 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9536 19:26:46.186245 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9537 19:26:46.189283 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9538 19:26:46.196149 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9539 19:26:46.199548 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9540 19:26:46.205946 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9541 19:26:46.209406 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9542 19:26:46.213196 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9543 19:26:46.219756 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9544 19:26:46.222656 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9545 19:26:46.229984 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9546 19:26:46.233031 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9547 19:26:46.236123 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9548 19:26:46.243084 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9549 19:26:46.246530 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9550 19:26:46.249615 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9551 19:26:46.252555 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9552 19:26:46.259646 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9553 19:26:46.262994 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9554 19:26:46.266000 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9555 19:26:46.269540 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9556 19:26:46.275874 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9557 19:26:46.279416 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9558 19:26:46.282469 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9559 19:26:46.285888 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9560 19:26:46.292652 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9561 19:26:46.296017 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9562 19:26:46.299559 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9563 19:26:46.302449 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9564 19:26:46.309066 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9565 19:26:46.312381 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9566 19:26:46.319111 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9567 19:26:46.322718 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9568 19:26:46.329351 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9569 19:26:46.332297 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9570 19:26:46.335864 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9571 19:26:46.342550 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9572 19:26:46.345671 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9573 19:26:46.352605 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9574 19:26:46.356167 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9575 19:26:46.362970 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9576 19:26:46.366302 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9577 19:26:46.372758 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9578 19:26:46.376231 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9579 19:26:46.379238 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9580 19:26:46.385714 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9581 19:26:46.389341 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9582 19:26:46.395740 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9583 19:26:46.399130 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9584 19:26:46.406047 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9585 19:26:46.409737 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9586 19:26:46.412571 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9587 19:26:46.419316 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9588 19:26:46.423031 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9589 19:26:46.429317 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9590 19:26:46.432852 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9591 19:26:46.439774 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9592 19:26:46.442837 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9593 19:26:46.446443 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9594 19:26:46.453107 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9595 19:26:46.456481 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9596 19:26:46.462805 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9597 19:26:46.466239 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9598 19:26:46.472643 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9599 19:26:46.476169 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9600 19:26:46.479443 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9601 19:26:46.485833 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9602 19:26:46.489292 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9603 19:26:46.495936 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9604 19:26:46.498961 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9605 19:26:46.505925 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9606 19:26:46.509381 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9607 19:26:46.512862 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9608 19:26:46.519632 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9609 19:26:46.522469 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9610 19:26:46.529063 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9611 19:26:46.532744 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9612 19:26:46.535613 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9613 19:26:46.542613 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9614 19:26:46.545550 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9615 19:26:46.549236 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9616 19:26:46.552156 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9617 19:26:46.558782 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9618 19:26:46.562378 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9619 19:26:46.568939 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9620 19:26:46.572189 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9621 19:26:46.575460 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9622 19:26:46.582387 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9623 19:26:46.585912 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9624 19:26:46.592564 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9625 19:26:46.595620 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9626 19:26:46.599204 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9627 19:26:46.605963 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9628 19:26:46.608712 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9629 19:26:46.615920 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9630 19:26:46.619463 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9631 19:26:46.622572 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9632 19:26:46.629234 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9633 19:26:46.632915 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9634 19:26:46.635771 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9635 19:26:46.642284 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9636 19:26:46.645986 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9637 19:26:46.649258 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9638 19:26:46.652419 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9639 19:26:46.658956 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9640 19:26:46.662348 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9641 19:26:46.665917 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9642 19:26:46.671957 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9643 19:26:46.675664 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9644 19:26:46.682092 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9645 19:26:46.685376 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9646 19:26:46.688833 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9647 19:26:46.695535 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9648 19:26:46.698943 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9649 19:26:46.701992 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9650 19:26:46.708751 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9651 19:26:46.711822 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9652 19:26:46.718771 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9653 19:26:46.721779 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9654 19:26:46.725616 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9655 19:26:46.732277 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9656 19:26:46.735704 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9657 19:26:46.742393 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9658 19:26:46.745278 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9659 19:26:46.748734 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9660 19:26:46.755727 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9661 19:26:46.758774 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9662 19:26:46.761981 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9663 19:26:46.768799 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9664 19:26:46.771919 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9665 19:26:46.778989 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9666 19:26:46.781916 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9667 19:26:46.785428 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9668 19:26:46.791873 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9669 19:26:46.795410 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9670 19:26:46.802448 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9671 19:26:46.805553 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9672 19:26:46.808896 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9673 19:26:46.815557 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9674 19:26:46.818840 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9675 19:26:46.821941 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9676 19:26:46.828696 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9677 19:26:46.832133 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9678 19:26:46.838980 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9679 19:26:46.842138 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9680 19:26:46.845642 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9681 19:26:46.852180 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9682 19:26:46.855733 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9683 19:26:46.862085 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9684 19:26:46.865409 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9685 19:26:46.868572 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9686 19:26:46.875293 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9687 19:26:46.878778 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9688 19:26:46.885366 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9689 19:26:46.888318 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9690 19:26:46.891869 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9691 19:26:46.898332 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9692 19:26:46.902031 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9693 19:26:46.908476 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9694 19:26:46.911481 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9695 19:26:46.915398 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9696 19:26:46.921795 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9697 19:26:46.924809 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9698 19:26:46.931906 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9699 19:26:46.934549 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9700 19:26:46.938126 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9701 19:26:46.944914 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9702 19:26:46.947828 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9703 19:26:46.954398 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9704 19:26:46.957965 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9705 19:26:46.960851 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9706 19:26:46.967832 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9707 19:26:46.970831 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9708 19:26:46.977702 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9709 19:26:46.981073 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9710 19:26:46.988015 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9711 19:26:46.991004 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9712 19:26:46.993998 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9713 19:26:47.000624 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9714 19:26:47.004386 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9715 19:26:47.010947 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9716 19:26:47.014009 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9717 19:26:47.020611 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9718 19:26:47.024004 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9719 19:26:47.027315 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9720 19:26:47.033618 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9721 19:26:47.037418 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9722 19:26:47.043859 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9723 19:26:47.047316 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9724 19:26:47.050260 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9725 19:26:47.056750 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9726 19:26:47.060439 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9727 19:26:47.067084 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9728 19:26:47.070011 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9729 19:26:47.077075 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9730 19:26:47.080508 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9731 19:26:47.083378 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9732 19:26:47.090086 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9733 19:26:47.092911 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9734 19:26:47.099648 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9735 19:26:47.103215 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9736 19:26:47.109834 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9737 19:26:47.113348 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9738 19:26:47.116286 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9739 19:26:47.122775 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9740 19:26:47.126431 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9741 19:26:47.133560 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9742 19:26:47.136341 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9743 19:26:47.142630 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9744 19:26:47.146346 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9745 19:26:47.149788 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9746 19:26:47.152585 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9747 19:26:47.159288 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9748 19:26:47.162331 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9749 19:26:47.165771 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9750 19:26:47.172189 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9751 19:26:47.175723 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9752 19:26:47.178951 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9753 19:26:47.185466 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9754 19:26:47.188487 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9755 19:26:47.191854 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9756 19:26:47.198925 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9757 19:26:47.201872 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9758 19:26:47.208306 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9759 19:26:47.211757 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9760 19:26:47.214840 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9761 19:26:47.221349 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9762 19:26:47.224914 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9763 19:26:47.228436 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9764 19:26:47.234984 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9765 19:26:47.237918 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9766 19:26:47.244774 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9767 19:26:47.248125 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9768 19:26:47.251687 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9769 19:26:47.258069 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9770 19:26:47.261390 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9771 19:26:47.264482 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9772 19:26:47.271703 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9773 19:26:47.274557 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9774 19:26:47.278443 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9775 19:26:47.284604 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9776 19:26:47.288089 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9777 19:26:47.294553 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9778 19:26:47.298008 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9779 19:26:47.301461 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9780 19:26:47.307709 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9781 19:26:47.311027 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9782 19:26:47.317962 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9783 19:26:47.320831 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9784 19:26:47.324298 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9785 19:26:47.327895 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9786 19:26:47.334497 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9787 19:26:47.337417 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9788 19:26:47.341007 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9789 19:26:47.344561 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9790 19:26:47.350980 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9791 19:26:47.354390 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9792 19:26:47.357440 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9793 19:26:47.360738 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9794 19:26:47.367582 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9795 19:26:47.370553 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9796 19:26:47.374139 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9797 19:26:47.377585 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9798 19:26:47.384168 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9799 19:26:47.387217 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9800 19:26:47.393898 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9801 19:26:47.397470 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9802 19:26:47.403794 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9803 19:26:47.407335 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9804 19:26:47.410679 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9805 19:26:47.416986 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9806 19:26:47.420178 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9807 19:26:47.427614 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9808 19:26:47.430687 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9809 19:26:47.433623 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9810 19:26:47.440125 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9811 19:26:47.443543 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9812 19:26:47.450046 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9813 19:26:47.453348 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9814 19:26:47.456808 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9815 19:26:47.463066 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9816 19:26:47.466761 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9817 19:26:47.473195 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9818 19:26:47.476498 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9819 19:26:47.482934 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9820 19:26:47.486279 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9821 19:26:47.489987 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9822 19:26:47.496679 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9823 19:26:47.499738 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9824 19:26:47.506344 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9825 19:26:47.509710 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9826 19:26:47.516378 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9827 19:26:47.519285 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9828 19:26:47.522830 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9829 19:26:47.529813 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9830 19:26:47.532613 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9831 19:26:47.539636 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9832 19:26:47.542642 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9833 19:26:47.545806 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9834 19:26:47.552532 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9835 19:26:47.555685 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9836 19:26:47.562318 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9837 19:26:47.565773 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9838 19:26:47.569125 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9839 19:26:47.575878 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9840 19:26:47.578974 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9841 19:26:47.585411 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9842 19:26:47.588622 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9843 19:26:47.595326 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9844 19:26:47.598869 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9845 19:26:47.601994 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9846 19:26:47.608460 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9847 19:26:47.611870 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9848 19:26:47.618424 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9849 19:26:47.622108 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9850 19:26:47.625102 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9851 19:26:47.631788 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9852 19:26:47.635331 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9853 19:26:47.641776 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9854 19:26:47.645343 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9855 19:26:47.651892 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9856 19:26:47.654884 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9857 19:26:47.658331 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9858 19:26:47.664792 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9859 19:26:47.668153 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9860 19:26:47.674993 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9861 19:26:47.678187 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9862 19:26:47.681429 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9863 19:26:47.687957 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9864 19:26:47.691835 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9865 19:26:47.697943 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9866 19:26:47.701191 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9867 19:26:47.707910 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9868 19:26:47.711324 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9869 19:26:47.714135 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9870 19:26:47.721201 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9871 19:26:47.724144 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9872 19:26:47.731356 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9873 19:26:47.734244 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9874 19:26:47.740916 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9875 19:26:47.744048 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9876 19:26:47.747722 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9877 19:26:47.754050 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9878 19:26:47.757091 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9879 19:26:47.764122 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9880 19:26:47.767173 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9881 19:26:47.773784 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9882 19:26:47.777301 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9883 19:26:47.783783 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9884 19:26:47.787276 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9885 19:26:47.790339 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9886 19:26:47.797045 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9887 19:26:47.800252 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9888 19:26:47.806643 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9889 19:26:47.810184 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9890 19:26:47.816674 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9891 19:26:47.820109 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9892 19:26:47.823488 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9893 19:26:47.830313 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9894 19:26:47.833347 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9895 19:26:47.839787 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9896 19:26:47.843359 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9897 19:26:47.849777 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9898 19:26:47.853497 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9899 19:26:47.859924 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9900 19:26:47.862879 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9901 19:26:47.866335 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9902 19:26:47.873066 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9903 19:26:47.876173 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9904 19:26:47.882816 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9905 19:26:47.886356 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9906 19:26:47.892690 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9907 19:26:47.896251 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9908 19:26:47.899675 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9909 19:26:47.906093 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9910 19:26:47.909638 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9911 19:26:47.915943 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9912 19:26:47.919356 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9913 19:26:47.926397 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9914 19:26:47.929379 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9915 19:26:47.932850 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9916 19:26:47.939915 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9917 19:26:47.942951 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9918 19:26:47.949156 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9919 19:26:47.952292 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9920 19:26:47.959369 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9921 19:26:47.962765 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9922 19:26:47.965697 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9923 19:26:47.972645 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9924 19:26:47.975582 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9925 19:26:47.982726 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9926 19:26:47.985626 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9927 19:26:47.992274 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9928 19:26:47.995315 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9929 19:26:48.002332 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9930 19:26:48.005673 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9931 19:26:48.012218 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9932 19:26:48.015750 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9933 19:26:48.022042 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9934 19:26:48.025426 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9935 19:26:48.031838 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9936 19:26:48.035364 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9937 19:26:48.042005 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9938 19:26:48.045553 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9939 19:26:48.051948 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9940 19:26:48.055144 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9941 19:26:48.062032 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9942 19:26:48.065461 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9943 19:26:48.072069 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9944 19:26:48.075280 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9945 19:26:48.081993 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9946 19:26:48.085571 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9947 19:26:48.092081 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9948 19:26:48.095155 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9949 19:26:48.101656 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9950 19:26:48.105279 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9951 19:26:48.108185 INFO: [APUAPC] vio 0
9952 19:26:48.111710 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9953 19:26:48.118385 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9954 19:26:48.121607 INFO: [APUAPC] D0_APC_0: 0x400510
9955 19:26:48.125043 INFO: [APUAPC] D0_APC_1: 0x0
9956 19:26:48.125655 INFO: [APUAPC] D0_APC_2: 0x1540
9957 19:26:48.128419 INFO: [APUAPC] D0_APC_3: 0x0
9958 19:26:48.131483 INFO: [APUAPC] D1_APC_0: 0xffffffff
9959 19:26:48.135079 INFO: [APUAPC] D1_APC_1: 0xffffffff
9960 19:26:48.138248 INFO: [APUAPC] D1_APC_2: 0x3fffff
9961 19:26:48.142011 INFO: [APUAPC] D1_APC_3: 0x0
9962 19:26:48.144895 INFO: [APUAPC] D2_APC_0: 0xffffffff
9963 19:26:48.148523 INFO: [APUAPC] D2_APC_1: 0xffffffff
9964 19:26:48.151566 INFO: [APUAPC] D2_APC_2: 0x3fffff
9965 19:26:48.154640 INFO: [APUAPC] D2_APC_3: 0x0
9966 19:26:48.158140 INFO: [APUAPC] D3_APC_0: 0xffffffff
9967 19:26:48.161816 INFO: [APUAPC] D3_APC_1: 0xffffffff
9968 19:26:48.164675 INFO: [APUAPC] D3_APC_2: 0x3fffff
9969 19:26:48.168007 INFO: [APUAPC] D3_APC_3: 0x0
9970 19:26:48.171632 INFO: [APUAPC] D4_APC_0: 0xffffffff
9971 19:26:48.174426 INFO: [APUAPC] D4_APC_1: 0xffffffff
9972 19:26:48.177814 INFO: [APUAPC] D4_APC_2: 0x3fffff
9973 19:26:48.181471 INFO: [APUAPC] D4_APC_3: 0x0
9974 19:26:48.184919 INFO: [APUAPC] D5_APC_0: 0xffffffff
9975 19:26:48.187960 INFO: [APUAPC] D5_APC_1: 0xffffffff
9976 19:26:48.191519 INFO: [APUAPC] D5_APC_2: 0x3fffff
9977 19:26:48.194462 INFO: [APUAPC] D5_APC_3: 0x0
9978 19:26:48.197883 INFO: [APUAPC] D6_APC_0: 0xffffffff
9979 19:26:48.201475 INFO: [APUAPC] D6_APC_1: 0xffffffff
9980 19:26:48.204397 INFO: [APUAPC] D6_APC_2: 0x3fffff
9981 19:26:48.208110 INFO: [APUAPC] D6_APC_3: 0x0
9982 19:26:48.211024 INFO: [APUAPC] D7_APC_0: 0xffffffff
9983 19:26:48.214735 INFO: [APUAPC] D7_APC_1: 0xffffffff
9984 19:26:48.217696 INFO: [APUAPC] D7_APC_2: 0x3fffff
9985 19:26:48.221196 INFO: [APUAPC] D7_APC_3: 0x0
9986 19:26:48.224581 INFO: [APUAPC] D8_APC_0: 0xffffffff
9987 19:26:48.228005 INFO: [APUAPC] D8_APC_1: 0xffffffff
9988 19:26:48.230931 INFO: [APUAPC] D8_APC_2: 0x3fffff
9989 19:26:48.234076 INFO: [APUAPC] D8_APC_3: 0x0
9990 19:26:48.237618 INFO: [APUAPC] D9_APC_0: 0xffffffff
9991 19:26:48.241035 INFO: [APUAPC] D9_APC_1: 0xffffffff
9992 19:26:48.244511 INFO: [APUAPC] D9_APC_2: 0x3fffff
9993 19:26:48.247487 INFO: [APUAPC] D9_APC_3: 0x0
9994 19:26:48.251071 INFO: [APUAPC] D10_APC_0: 0xffffffff
9995 19:26:48.254121 INFO: [APUAPC] D10_APC_1: 0xffffffff
9996 19:26:48.257669 INFO: [APUAPC] D10_APC_2: 0x3fffff
9997 19:26:48.260693 INFO: [APUAPC] D10_APC_3: 0x0
9998 19:26:48.264509 INFO: [APUAPC] D11_APC_0: 0xffffffff
9999 19:26:48.267440 INFO: [APUAPC] D11_APC_1: 0xffffffff
10000 19:26:48.270986 INFO: [APUAPC] D11_APC_2: 0x3fffff
10001 19:26:48.273753 INFO: [APUAPC] D11_APC_3: 0x0
10002 19:26:48.277153 INFO: [APUAPC] D12_APC_0: 0xffffffff
10003 19:26:48.280054 INFO: [APUAPC] D12_APC_1: 0xffffffff
10004 19:26:48.283607 INFO: [APUAPC] D12_APC_2: 0x3fffff
10005 19:26:48.286761 INFO: [APUAPC] D12_APC_3: 0x0
10006 19:26:48.290313 INFO: [APUAPC] D13_APC_0: 0xffffffff
10007 19:26:48.293887 INFO: [APUAPC] D13_APC_1: 0xffffffff
10008 19:26:48.296713 INFO: [APUAPC] D13_APC_2: 0x3fffff
10009 19:26:48.300170 INFO: [APUAPC] D13_APC_3: 0x0
10010 19:26:48.303592 INFO: [APUAPC] D14_APC_0: 0xffffffff
10011 19:26:48.306743 INFO: [APUAPC] D14_APC_1: 0xffffffff
10012 19:26:48.310198 INFO: [APUAPC] D14_APC_2: 0x3fffff
10013 19:26:48.313650 INFO: [APUAPC] D14_APC_3: 0x0
10014 19:26:48.316527 INFO: [APUAPC] D15_APC_0: 0xffffffff
10015 19:26:48.320141 INFO: [APUAPC] D15_APC_1: 0xffffffff
10016 19:26:48.323166 INFO: [APUAPC] D15_APC_2: 0x3fffff
10017 19:26:48.326596 INFO: [APUAPC] D15_APC_3: 0x0
10018 19:26:48.330081 INFO: [APUAPC] APC_CON: 0x4
10019 19:26:48.333527 INFO: [NOCDAPC] D0_APC_0: 0x0
10020 19:26:48.336366 INFO: [NOCDAPC] D0_APC_1: 0x0
10021 19:26:48.336488 INFO: [NOCDAPC] D1_APC_0: 0x0
10022 19:26:48.339617 INFO: [NOCDAPC] D1_APC_1: 0xfff
10023 19:26:48.343226 INFO: [NOCDAPC] D2_APC_0: 0x0
10024 19:26:48.346330 INFO: [NOCDAPC] D2_APC_1: 0xfff
10025 19:26:48.350065 INFO: [NOCDAPC] D3_APC_0: 0x0
10026 19:26:48.353377 INFO: [NOCDAPC] D3_APC_1: 0xfff
10027 19:26:48.356762 INFO: [NOCDAPC] D4_APC_0: 0x0
10028 19:26:48.359666 INFO: [NOCDAPC] D4_APC_1: 0xfff
10029 19:26:48.363237 INFO: [NOCDAPC] D5_APC_0: 0x0
10030 19:26:48.366881 INFO: [NOCDAPC] D5_APC_1: 0xfff
10031 19:26:48.367303 INFO: [NOCDAPC] D6_APC_0: 0x0
10032 19:26:48.369808 INFO: [NOCDAPC] D6_APC_1: 0xfff
10033 19:26:48.373435 INFO: [NOCDAPC] D7_APC_0: 0x0
10034 19:26:48.376753 INFO: [NOCDAPC] D7_APC_1: 0xfff
10035 19:26:48.380299 INFO: [NOCDAPC] D8_APC_0: 0x0
10036 19:26:48.383622 INFO: [NOCDAPC] D8_APC_1: 0xfff
10037 19:26:48.386559 INFO: [NOCDAPC] D9_APC_0: 0x0
10038 19:26:48.389917 INFO: [NOCDAPC] D9_APC_1: 0xfff
10039 19:26:48.393616 INFO: [NOCDAPC] D10_APC_0: 0x0
10040 19:26:48.396423 INFO: [NOCDAPC] D10_APC_1: 0xfff
10041 19:26:48.399750 INFO: [NOCDAPC] D11_APC_0: 0x0
10042 19:26:48.403027 INFO: [NOCDAPC] D11_APC_1: 0xfff
10043 19:26:48.403112 INFO: [NOCDAPC] D12_APC_0: 0x0
10044 19:26:48.406039 INFO: [NOCDAPC] D12_APC_1: 0xfff
10045 19:26:48.409843 INFO: [NOCDAPC] D13_APC_0: 0x0
10046 19:26:48.413093 INFO: [NOCDAPC] D13_APC_1: 0xfff
10047 19:26:48.416384 INFO: [NOCDAPC] D14_APC_0: 0x0
10048 19:26:48.419784 INFO: [NOCDAPC] D14_APC_1: 0xfff
10049 19:26:48.422983 INFO: [NOCDAPC] D15_APC_0: 0x0
10050 19:26:48.426240 INFO: [NOCDAPC] D15_APC_1: 0xfff
10051 19:26:48.429381 INFO: [NOCDAPC] APC_CON: 0x4
10052 19:26:48.432972 INFO: [APUAPC] set_apusys_apc done
10053 19:26:48.435897 INFO: [DEVAPC] devapc_init done
10054 19:26:48.439436 INFO: GICv3 without legacy support detected.
10055 19:26:48.442863 INFO: ARM GICv3 driver initialized in EL3
10056 19:26:48.446275 INFO: Maximum SPI INTID supported: 639
10057 19:26:48.452688 INFO: BL31: Initializing runtime services
10058 19:26:48.455913 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10059 19:26:48.459234 INFO: SPM: enable CPC mode
10060 19:26:48.466012 INFO: mcdi ready for mcusys-off-idle and system suspend
10061 19:26:48.469543 INFO: BL31: Preparing for EL3 exit to normal world
10062 19:26:48.472676 INFO: Entry point address = 0x80000000
10063 19:26:48.475576 INFO: SPSR = 0x8
10064 19:26:48.481221
10065 19:26:48.481310
10066 19:26:48.481377
10067 19:26:48.484700 Starting depthcharge on Spherion...
10068 19:26:48.484784
10069 19:26:48.484848 Wipe memory regions:
10070 19:26:48.484910
10071 19:26:48.485571 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10072 19:26:48.485689 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10073 19:26:48.485773 Setting prompt string to ['asurada:']
10074 19:26:48.485855 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10075 19:26:48.487640 [0x00000040000000, 0x00000054600000)
10076 19:26:48.610090
10077 19:26:48.610233 [0x00000054660000, 0x00000080000000)
10078 19:26:48.870551
10079 19:26:48.870700 [0x000000821a7280, 0x000000ffe64000)
10080 19:26:49.615541
10081 19:26:49.615704 [0x00000100000000, 0x00000240000000)
10082 19:26:51.505954
10083 19:26:51.509136 Initializing XHCI USB controller at 0x11200000.
10084 19:26:52.546839
10085 19:26:52.549773 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10086 19:26:52.549898
10087 19:26:52.549991
10088 19:26:52.550088
10089 19:26:52.550445 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10091 19:26:52.650833 asurada: tftpboot 192.168.201.1 13420400/tftp-deploy-flapplqt/kernel/image.itb 13420400/tftp-deploy-flapplqt/kernel/cmdline
10092 19:26:52.651034 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10093 19:26:52.651180 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10094 19:26:52.655346 tftpboot 192.168.201.1 13420400/tftp-deploy-flapplqt/kernel/image.itp-deploy-flapplqt/kernel/cmdline
10095 19:26:52.655464
10096 19:26:52.655557 Waiting for link
10097 19:26:52.815739
10098 19:26:52.815914 R8152: Initializing
10099 19:26:52.816016
10100 19:26:52.819345 Version 6 (ocp_data = 5c30)
10101 19:26:52.819448
10102 19:26:52.822108 R8152: Done initializing
10103 19:26:52.822199
10104 19:26:52.822279 Adding net device
10105 19:26:54.883090
10106 19:26:54.883261 done.
10107 19:26:54.883356
10108 19:26:54.883450 MAC: 00:24:32:30:78:ff
10109 19:26:54.883538
10110 19:26:54.886699 Sending DHCP discover... done.
10111 19:26:54.886784
10112 19:26:54.889899 Waiting for reply... done.
10113 19:26:54.889990
10114 19:26:54.893305 Sending DHCP request... done.
10115 19:26:54.893403
10116 19:26:54.898977 Waiting for reply... done.
10117 19:26:54.899058
10118 19:26:54.899121 My ip is 192.168.201.21
10119 19:26:54.899180
10120 19:26:54.902363 The DHCP server ip is 192.168.201.1
10121 19:26:54.902460
10122 19:26:54.908976 TFTP server IP predefined by user: 192.168.201.1
10123 19:26:54.909084
10124 19:26:54.915801 Bootfile predefined by user: 13420400/tftp-deploy-flapplqt/kernel/image.itb
10125 19:26:54.915945
10126 19:26:54.916036 Sending tftp read request... done.
10127 19:26:54.918790
10128 19:26:54.922177 Waiting for the transfer...
10129 19:26:54.922256
10130 19:26:55.493796 00000000 ################################################################
10131 19:26:55.493947
10132 19:26:56.085985 00080000 ################################################################
10133 19:26:56.086161
10134 19:26:56.660314 00100000 ################################################################
10135 19:26:56.660475
10136 19:26:57.231732 00180000 ################################################################
10137 19:26:57.231870
10138 19:26:57.804360 00200000 ################################################################
10139 19:26:57.804497
10140 19:26:58.371851 00280000 ################################################################
10141 19:26:58.372011
10142 19:26:58.923132 00300000 ################################################################
10143 19:26:58.923264
10144 19:26:59.480840 00380000 ################################################################
10145 19:26:59.480979
10146 19:27:00.048915 00400000 ################################################################
10147 19:27:00.049068
10148 19:27:00.603485 00480000 ################################################################
10149 19:27:00.603665
10150 19:27:01.162245 00500000 ################################################################
10151 19:27:01.162446
10152 19:27:01.746672 00580000 ################################################################
10153 19:27:01.746824
10154 19:27:02.325477 00600000 ################################################################
10155 19:27:02.325764
10156 19:27:02.895192 00680000 ################################################################
10157 19:27:02.895385
10158 19:27:03.460156 00700000 ################################################################
10159 19:27:03.460342
10160 19:27:04.043705 00780000 ################################################################
10161 19:27:04.043871
10162 19:27:04.597919 00800000 ################################################################
10163 19:27:04.598070
10164 19:27:05.157674 00880000 ################################################################
10165 19:27:05.157863
10166 19:27:05.698267 00900000 ################################################################
10167 19:27:05.698427
10168 19:27:06.303604 00980000 ################################################################
10169 19:27:06.304216
10170 19:27:06.963914 00a00000 ################################################################
10171 19:27:06.964569
10172 19:27:07.629607 00a80000 ################################################################
10173 19:27:07.629775
10174 19:27:08.265617 00b00000 ################################################################
10175 19:27:08.265778
10176 19:27:08.901195 00b80000 ################################################################
10177 19:27:08.901882
10178 19:27:09.580587 00c00000 ################################################################
10179 19:27:09.581149
10180 19:27:10.162190 00c80000 ################################################################
10181 19:27:10.162410
10182 19:27:10.770873 00d00000 ################################################################
10183 19:27:10.771095
10184 19:27:11.361418 00d80000 ################################################################
10185 19:27:11.361967
10186 19:27:11.979381 00e00000 ################################################################
10187 19:27:11.979947
10188 19:27:12.613133 00e80000 ################################################################
10189 19:27:12.613289
10190 19:27:13.211543 00f00000 ################################################################
10191 19:27:13.212076
10192 19:27:13.866164 00f80000 ################################################################
10193 19:27:13.866701
10194 19:27:14.539474 01000000 ################################################################
10195 19:27:14.539739
10196 19:27:15.182632 01080000 ################################################################
10197 19:27:15.182788
10198 19:27:15.806545 01100000 ################################################################
10199 19:27:15.807072
10200 19:27:16.496305 01180000 ################################################################
10201 19:27:16.496459
10202 19:27:17.062387 01200000 ################################################################
10203 19:27:17.063111
10204 19:27:17.979006 01280000 ################################################################
10205 19:27:17.979543
10206 19:27:18.296407 01300000 ################################################################
10207 19:27:18.296706
10208 19:27:18.966420 01380000 ################################################################
10209 19:27:18.967145
10210 19:27:19.620205 01400000 ################################################################
10211 19:27:19.620807
10212 19:27:20.248554 01480000 ################################################################
10213 19:27:20.248688
10214 19:27:20.922779 01500000 ################################################################
10215 19:27:20.923352
10216 19:27:21.572169 01580000 ################################################################
10217 19:27:21.572308
10218 19:27:22.166151 01600000 ################################################################
10219 19:27:22.166295
10220 19:27:22.772799 01680000 ################################################################
10221 19:27:22.772940
10222 19:27:23.395425 01700000 ################################################################
10223 19:27:23.395933
10224 19:27:24.059396 01780000 ################################################################
10225 19:27:24.059526
10226 19:27:24.686166 01800000 ################################################################
10227 19:27:24.686727
10228 19:27:25.344451 01880000 ################################################################
10229 19:27:25.344995
10230 19:27:26.019244 01900000 ################################################################
10231 19:27:26.019766
10232 19:27:26.669970 01980000 ################################################################
10233 19:27:26.670467
10234 19:27:27.271043 01a00000 ################################################################
10235 19:27:27.271194
10236 19:27:27.796136 01a80000 ################################################################
10237 19:27:27.796288
10238 19:27:28.325435 01b00000 ################################################################
10239 19:27:28.325597
10240 19:27:28.878367 01b80000 ################################################################
10241 19:27:28.878516
10242 19:27:29.425032 01c00000 ################################################################
10243 19:27:29.425167
10244 19:27:29.980587 01c80000 ################################################################
10245 19:27:29.980774
10246 19:27:30.523945 01d00000 ################################################################
10247 19:27:30.524087
10248 19:27:31.066842 01d80000 ################################################################
10249 19:27:31.067022
10250 19:27:31.355064 01e00000 ################################### done.
10251 19:27:31.355216
10252 19:27:31.358453 The bootfile was 31738158 bytes long.
10253 19:27:31.358545
10254 19:27:31.361879 Sending tftp read request... done.
10255 19:27:31.362017
10256 19:27:31.364727 Waiting for the transfer...
10257 19:27:31.364831
10258 19:27:31.368263 00000000 # done.
10259 19:27:31.368365
10260 19:27:31.374633 Command line loaded dynamically from TFTP file: 13420400/tftp-deploy-flapplqt/kernel/cmdline
10261 19:27:31.374715
10262 19:27:31.397808 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/13420400/extract-nfsrootfs-co75676u,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10263 19:27:31.397972
10264 19:27:31.398086 Loading FIT.
10265 19:27:31.398184
10266 19:27:31.401155 Image ramdisk-1 has 18778539 bytes.
10267 19:27:31.401264
10268 19:27:31.404233 Image fdt-1 has 47230 bytes.
10269 19:27:31.404341
10270 19:27:31.408049 Image kernel-1 has 12910355 bytes.
10271 19:27:31.408157
10272 19:27:31.414174 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10273 19:27:31.414264
10274 19:27:31.434202 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10275 19:27:31.434326
10276 19:27:31.437467 Choosing best match conf-1 for compat google,spherion-rev2.
10277 19:27:31.442920
10278 19:27:31.447484 Connected to device vid:did:rid of 1ae0:0028:00
10279 19:27:31.455245
10280 19:27:31.458685 tpm_get_response: command 0x17b, return code 0x0
10281 19:27:31.458791
10282 19:27:31.462248 ec_init: CrosEC protocol v3 supported (256, 248)
10283 19:27:31.467547
10284 19:27:31.470448 tpm_cleanup: add release locality here.
10285 19:27:31.470549
10286 19:27:31.470639 Shutting down all USB controllers.
10287 19:27:31.474012
10288 19:27:31.474112 Removing current net device
10289 19:27:31.474205
10290 19:27:31.480498 Exiting depthcharge with code 4 at timestamp: 72292587
10291 19:27:31.480585
10292 19:27:31.484066 LZMA decompressing kernel-1 to 0x821a6718
10293 19:27:31.484171
10294 19:27:31.487007 LZMA decompressing kernel-1 to 0x40000000
10295 19:27:33.081298
10296 19:27:33.081458 jumping to kernel
10297 19:27:33.081932 end: 2.2.4 bootloader-commands (duration 00:00:45) [common]
10298 19:27:33.082032 start: 2.2.5 auto-login-action (timeout 00:03:41) [common]
10299 19:27:33.082152 Setting prompt string to ['Linux version [0-9]']
10300 19:27:33.082223 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10301 19:27:33.082291 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10302 19:27:33.163979
10303 19:27:33.167468 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10304 19:27:33.171135 start: 2.2.5.1 login-action (timeout 00:03:41) [common]
10305 19:27:33.171250 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10306 19:27:33.171358 Setting prompt string to []
10307 19:27:33.171435 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10308 19:27:33.171509 Using line separator: #'\n'#
10309 19:27:33.171568 No login prompt set.
10310 19:27:33.171629 Parsing kernel messages
10311 19:27:33.171723 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10312 19:27:33.171829 [login-action] Waiting for messages, (timeout 00:03:41)
10313 19:27:33.171894 Waiting using forced prompt support (timeout 00:01:50)
10314 19:27:33.190733 [ 0.000000] Linux version 6.1.86-cip19 (KernelCI@build-j170728-arm64-gcc-10-defconfig-arm64-chromebook-wrkxq) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Apr 18 19:05:54 UTC 2024
10315 19:27:33.194147 [ 0.000000] random: crng init done
10316 19:27:33.200612 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10317 19:27:33.203602 [ 0.000000] efi: UEFI not found.
10318 19:27:33.210272 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10319 19:27:33.216748 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10320 19:27:33.227072 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10321 19:27:33.236795 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10322 19:27:33.243097 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10323 19:27:33.250180 [ 0.000000] printk: bootconsole [mtk8250] enabled
10324 19:27:33.256548 [ 0.000000] NUMA: No NUMA configuration found
10325 19:27:33.263151 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10326 19:27:33.266806 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10327 19:27:33.269755 [ 0.000000] Zone ranges:
10328 19:27:33.276238 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10329 19:27:33.279626 [ 0.000000] DMA32 empty
10330 19:27:33.286233 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10331 19:27:33.289520 [ 0.000000] Movable zone start for each node
10332 19:27:33.292965 [ 0.000000] Early memory node ranges
10333 19:27:33.299247 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10334 19:27:33.305855 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10335 19:27:33.312588 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10336 19:27:33.319587 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10337 19:27:33.322709 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10338 19:27:33.332684 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10339 19:27:33.388464 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10340 19:27:33.395389 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10341 19:27:33.401844 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10342 19:27:33.405381 [ 0.000000] psci: probing for conduit method from DT.
10343 19:27:33.412064 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10344 19:27:33.415073 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10345 19:27:33.422037 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10346 19:27:33.425033 [ 0.000000] psci: SMC Calling Convention v1.2
10347 19:27:33.431404 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10348 19:27:33.434960 [ 0.000000] Detected VIPT I-cache on CPU0
10349 19:27:33.441542 [ 0.000000] CPU features: detected: GIC system register CPU interface
10350 19:27:33.448384 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10351 19:27:33.454775 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10352 19:27:33.461304 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10353 19:27:33.467826 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10354 19:27:33.477519 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10355 19:27:33.481257 [ 0.000000] alternatives: applying boot alternatives
10356 19:27:33.487920 [ 0.000000] Fallback order for Node 0: 0
10357 19:27:33.494210 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10358 19:27:33.497470 [ 0.000000] Policy zone: Normal
10359 19:27:33.520631 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/13420400/extract-nfsrootfs-co75676u,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10360 19:27:33.530555 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10361 19:27:33.541728 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10362 19:27:33.551285 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10363 19:27:33.558222 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10364 19:27:33.561168 <6>[ 0.000000] software IO TLB: area num 8.
10365 19:27:33.618712 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10366 19:27:33.768372 <6>[ 0.000000] Memory: 7946232K/8385536K available (18048K kernel code, 4118K rwdata, 22288K rodata, 8448K init, 616K bss, 406536K reserved, 32768K cma-reserved)
10367 19:27:33.774996 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10368 19:27:33.781219 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10369 19:27:33.784708 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10370 19:27:33.791115 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10371 19:27:33.798245 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10372 19:27:33.801250 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10373 19:27:33.811201 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10374 19:27:33.817933 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10375 19:27:33.824269 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10376 19:27:33.831154 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10377 19:27:33.834485 <6>[ 0.000000] GICv3: 608 SPIs implemented
10378 19:27:33.837545 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10379 19:27:33.844229 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10380 19:27:33.847268 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10381 19:27:33.854203 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10382 19:27:33.867670 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10383 19:27:33.880744 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10384 19:27:33.886940 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10385 19:27:33.894910 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10386 19:27:33.908233 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10387 19:27:33.914579 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10388 19:27:33.921391 <6>[ 0.009235] Console: colour dummy device 80x25
10389 19:27:33.931048 <6>[ 0.013953] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10390 19:27:33.937658 <6>[ 0.024461] pid_max: default: 32768 minimum: 301
10391 19:27:33.941162 <6>[ 0.029332] LSM: Security Framework initializing
10392 19:27:33.947858 <6>[ 0.034303] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10393 19:27:33.957747 <6>[ 0.042117] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10394 19:27:33.967476 <6>[ 0.051590] cblist_init_generic: Setting adjustable number of callback queues.
10395 19:27:33.971032 <6>[ 0.059033] cblist_init_generic: Setting shift to 3 and lim to 1.
10396 19:27:33.981075 <6>[ 0.065372] cblist_init_generic: Setting adjustable number of callback queues.
10397 19:27:33.987663 <6>[ 0.072799] cblist_init_generic: Setting shift to 3 and lim to 1.
10398 19:27:33.990720 <6>[ 0.079200] rcu: Hierarchical SRCU implementation.
10399 19:27:33.997388 <6>[ 0.084215] rcu: Max phase no-delay instances is 1000.
10400 19:27:34.003997 <6>[ 0.091241] EFI services will not be available.
10401 19:27:34.007638 <6>[ 0.096198] smp: Bringing up secondary CPUs ...
10402 19:27:34.015538 <6>[ 0.101245] Detected VIPT I-cache on CPU1
10403 19:27:34.022442 <6>[ 0.101315] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10404 19:27:34.028634 <6>[ 0.101349] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10405 19:27:34.032339 <6>[ 0.101682] Detected VIPT I-cache on CPU2
10406 19:27:34.041709 <6>[ 0.101734] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10407 19:27:34.048577 <6>[ 0.101753] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10408 19:27:34.052107 <6>[ 0.102013] Detected VIPT I-cache on CPU3
10409 19:27:34.058393 <6>[ 0.102060] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10410 19:27:34.065341 <6>[ 0.102075] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10411 19:27:34.068551 <6>[ 0.102378] CPU features: detected: Spectre-v4
10412 19:27:34.075155 <6>[ 0.102383] CPU features: detected: Spectre-BHB
10413 19:27:34.078530 <6>[ 0.102388] Detected PIPT I-cache on CPU4
10414 19:27:34.084828 <6>[ 0.102444] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10415 19:27:34.091630 <6>[ 0.102461] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10416 19:27:34.098229 <6>[ 0.102755] Detected PIPT I-cache on CPU5
10417 19:27:34.104516 <6>[ 0.102816] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10418 19:27:34.111257 <6>[ 0.102832] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10419 19:27:34.114590 <6>[ 0.103112] Detected PIPT I-cache on CPU6
10420 19:27:34.121210 <6>[ 0.103176] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10421 19:27:34.127647 <6>[ 0.103192] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10422 19:27:34.134573 <6>[ 0.103487] Detected PIPT I-cache on CPU7
10423 19:27:34.140877 <6>[ 0.103552] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10424 19:27:34.147624 <6>[ 0.103568] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10425 19:27:34.151291 <6>[ 0.103616] smp: Brought up 1 node, 8 CPUs
10426 19:27:34.157852 <6>[ 0.244989] SMP: Total of 8 processors activated.
10427 19:27:34.160830 <6>[ 0.249941] CPU features: detected: 32-bit EL0 Support
10428 19:27:34.170983 <6>[ 0.255337] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10429 19:27:34.177653 <6>[ 0.264138] CPU features: detected: Common not Private translations
10430 19:27:34.184032 <6>[ 0.270615] CPU features: detected: CRC32 instructions
10431 19:27:34.187417 <6>[ 0.275999] CPU features: detected: RCpc load-acquire (LDAPR)
10432 19:27:34.193979 <6>[ 0.281959] CPU features: detected: LSE atomic instructions
10433 19:27:34.200564 <6>[ 0.287741] CPU features: detected: Privileged Access Never
10434 19:27:34.207199 <6>[ 0.293556] CPU features: detected: RAS Extension Support
10435 19:27:34.213702 <6>[ 0.299199] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10436 19:27:34.216985 <6>[ 0.306422] CPU: All CPU(s) started at EL2
10437 19:27:34.223838 <6>[ 0.310739] alternatives: applying system-wide alternatives
10438 19:27:34.233439 <6>[ 0.321551] devtmpfs: initialized
10439 19:27:34.245588 <6>[ 0.330471] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10440 19:27:34.255679 <6>[ 0.340435] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10441 19:27:34.262550 <6>[ 0.348683] pinctrl core: initialized pinctrl subsystem
10442 19:27:34.265693 <6>[ 0.355360] DMI not present or invalid.
10443 19:27:34.272357 <6>[ 0.359772] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10444 19:27:34.282047 <6>[ 0.366605] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10445 19:27:34.288787 <6>[ 0.374195] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10446 19:27:34.298885 <6>[ 0.382424] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10447 19:27:34.301861 <6>[ 0.390667] audit: initializing netlink subsys (disabled)
10448 19:27:34.312207 <5>[ 0.396360] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10449 19:27:34.318716 <6>[ 0.397065] thermal_sys: Registered thermal governor 'step_wise'
10450 19:27:34.325232 <6>[ 0.404323] thermal_sys: Registered thermal governor 'power_allocator'
10451 19:27:34.328409 <6>[ 0.410577] cpuidle: using governor menu
10452 19:27:34.335357 <6>[ 0.421540] NET: Registered PF_QIPCRTR protocol family
10453 19:27:34.341807 <6>[ 0.427035] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10454 19:27:34.348254 <6>[ 0.434135] ASID allocator initialised with 32768 entries
10455 19:27:34.351567 <6>[ 0.440714] Serial: AMBA PL011 UART driver
10456 19:27:34.361561 <4>[ 0.449472] Trying to register duplicate clock ID: 134
10457 19:27:34.416325 <6>[ 0.507278] KASLR enabled
10458 19:27:34.430718 <6>[ 0.514986] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10459 19:27:34.437052 <6>[ 0.521999] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10460 19:27:34.443225 <6>[ 0.528490] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10461 19:27:34.449792 <6>[ 0.535492] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10462 19:27:34.456532 <6>[ 0.541976] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10463 19:27:34.462970 <6>[ 0.548976] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10464 19:27:34.469807 <6>[ 0.555465] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10465 19:27:34.476412 <6>[ 0.562467] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10466 19:27:34.479974 <6>[ 0.569988] ACPI: Interpreter disabled.
10467 19:27:34.488272 <6>[ 0.576399] iommu: Default domain type: Translated
10468 19:27:34.495316 <6>[ 0.581511] iommu: DMA domain TLB invalidation policy: strict mode
10469 19:27:34.498310 <5>[ 0.588171] SCSI subsystem initialized
10470 19:27:34.505009 <6>[ 0.592333] usbcore: registered new interface driver usbfs
10471 19:27:34.511799 <6>[ 0.598066] usbcore: registered new interface driver hub
10472 19:27:34.514832 <6>[ 0.603615] usbcore: registered new device driver usb
10473 19:27:34.521470 <6>[ 0.609706] pps_core: LinuxPPS API ver. 1 registered
10474 19:27:34.531814 <6>[ 0.614901] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10475 19:27:34.534816 <6>[ 0.624244] PTP clock support registered
10476 19:27:34.538188 <6>[ 0.628486] EDAC MC: Ver: 3.0.0
10477 19:27:34.545988 <6>[ 0.633637] FPGA manager framework
10478 19:27:34.552172 <6>[ 0.637316] Advanced Linux Sound Architecture Driver Initialized.
10479 19:27:34.555681 <6>[ 0.644093] vgaarb: loaded
10480 19:27:34.562438 <6>[ 0.647264] clocksource: Switched to clocksource arch_sys_counter
10481 19:27:34.565706 <5>[ 0.653701] VFS: Disk quotas dquot_6.6.0
10482 19:27:34.572406 <6>[ 0.657888] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10483 19:27:34.575327 <6>[ 0.665075] pnp: PnP ACPI: disabled
10484 19:27:34.583751 <6>[ 0.671734] NET: Registered PF_INET protocol family
10485 19:27:34.593432 <6>[ 0.677323] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10486 19:27:34.605322 <6>[ 0.689651] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10487 19:27:34.615047 <6>[ 0.698464] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10488 19:27:34.621854 <6>[ 0.706434] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10489 19:27:34.628274 <6>[ 0.715140] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10490 19:27:34.640017 <6>[ 0.724896] TCP: Hash tables configured (established 65536 bind 65536)
10491 19:27:34.647141 <6>[ 0.731756] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10492 19:27:34.653879 <6>[ 0.738954] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10493 19:27:34.659954 <6>[ 0.746660] NET: Registered PF_UNIX/PF_LOCAL protocol family
10494 19:27:34.666519 <6>[ 0.752808] RPC: Registered named UNIX socket transport module.
10495 19:27:34.669920 <6>[ 0.758960] RPC: Registered udp transport module.
10496 19:27:34.676784 <6>[ 0.763894] RPC: Registered tcp transport module.
10497 19:27:34.683363 <6>[ 0.768824] RPC: Registered tcp NFSv4.1 backchannel transport module.
10498 19:27:34.686600 <6>[ 0.775490] PCI: CLS 0 bytes, default 64
10499 19:27:34.689466 <6>[ 0.779826] Unpacking initramfs...
10500 19:27:34.714530 <6>[ 0.799371] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10501 19:27:34.724530 <6>[ 0.808041] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10502 19:27:34.727910 <6>[ 0.816878] kvm [1]: IPA Size Limit: 40 bits
10503 19:27:34.734380 <6>[ 0.821405] kvm [1]: GICv3: no GICV resource entry
10504 19:27:34.738023 <6>[ 0.826423] kvm [1]: disabling GICv2 emulation
10505 19:27:34.744565 <6>[ 0.831112] kvm [1]: GIC system register CPU interface enabled
10506 19:27:34.747474 <6>[ 0.837273] kvm [1]: vgic interrupt IRQ18
10507 19:27:34.754085 <6>[ 0.841644] kvm [1]: VHE mode initialized successfully
10508 19:27:34.761119 <5>[ 0.847997] Initialise system trusted keyrings
10509 19:27:34.767338 <6>[ 0.852809] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10510 19:27:34.775130 <6>[ 0.862801] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10511 19:27:34.781397 <5>[ 0.869177] NFS: Registering the id_resolver key type
10512 19:27:34.784900 <5>[ 0.874472] Key type id_resolver registered
10513 19:27:34.791691 <5>[ 0.878889] Key type id_legacy registered
10514 19:27:34.798070 <6>[ 0.883169] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10515 19:27:34.804634 <6>[ 0.890090] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10516 19:27:34.811142 <6>[ 0.897811] 9p: Installing v9fs 9p2000 file system support
10517 19:27:34.846995 <5>[ 0.935017] Key type asymmetric registered
10518 19:27:34.850437 <5>[ 0.939346] Asymmetric key parser 'x509' registered
10519 19:27:34.860475 <6>[ 0.944495] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10520 19:27:34.863432 <6>[ 0.952116] io scheduler mq-deadline registered
10521 19:27:34.866912 <6>[ 0.956890] io scheduler kyber registered
10522 19:27:34.885775 <6>[ 0.973694] EINJ: ACPI disabled.
10523 19:27:34.917401 <4>[ 0.998814] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10524 19:27:34.927523 <4>[ 1.009437] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10525 19:27:34.941951 <6>[ 1.029895] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10526 19:27:34.949572 <6>[ 1.037853] printk: console [ttyS0] disabled
10527 19:27:34.977782 <6>[ 1.062487] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10528 19:27:34.984316 <6>[ 1.071954] printk: console [ttyS0] enabled
10529 19:27:34.987799 <6>[ 1.071954] printk: console [ttyS0] enabled
10530 19:27:34.994310 <6>[ 1.080853] printk: bootconsole [mtk8250] disabled
10531 19:27:34.997988 <6>[ 1.080853] printk: bootconsole [mtk8250] disabled
10532 19:27:35.004301 <6>[ 1.091909] SuperH (H)SCI(F) driver initialized
10533 19:27:35.007738 <6>[ 1.097176] msm_serial: driver initialized
10534 19:27:35.021585 <6>[ 1.106065] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10535 19:27:35.031330 <6>[ 1.114616] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10536 19:27:35.037725 <6>[ 1.123157] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10537 19:27:35.047894 <6>[ 1.131784] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10538 19:27:35.057675 <6>[ 1.140489] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10539 19:27:35.064667 <6>[ 1.149206] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10540 19:27:35.074386 <6>[ 1.157747] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10541 19:27:35.080833 <6>[ 1.166537] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10542 19:27:35.090999 <6>[ 1.175078] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10543 19:27:35.102698 <6>[ 1.190472] loop: module loaded
10544 19:27:35.109025 <6>[ 1.196312] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10545 19:27:35.131840 <4>[ 1.219533] mtk-pmic-keys: Failed to locate of_node [id: -1]
10546 19:27:35.138324 <6>[ 1.226354] megasas: 07.719.03.00-rc1
10547 19:27:35.148341 <6>[ 1.235939] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10548 19:27:35.154919 <6>[ 1.242637] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10549 19:27:35.171224 <6>[ 1.259118] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10550 19:27:35.227401 <6>[ 1.308849] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10551 19:27:35.478380 <6>[ 1.566658] Freeing initrd memory: 18336K
10552 19:27:35.490195 <6>[ 1.578031] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10553 19:27:35.500892 <6>[ 1.588802] tun: Universal TUN/TAP device driver, 1.6
10554 19:27:35.504027 <6>[ 1.594844] thunder_xcv, ver 1.0
10555 19:27:35.507375 <6>[ 1.598352] thunder_bgx, ver 1.0
10556 19:27:35.510825 <6>[ 1.601863] nicpf, ver 1.0
10557 19:27:35.521299 <6>[ 1.605876] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10558 19:27:35.524744 <6>[ 1.613352] hns3: Copyright (c) 2017 Huawei Corporation.
10559 19:27:35.530918 <6>[ 1.618945] hclge is initializing
10560 19:27:35.534248 <6>[ 1.622519] e1000: Intel(R) PRO/1000 Network Driver
10561 19:27:35.540933 <6>[ 1.627647] e1000: Copyright (c) 1999-2006 Intel Corporation.
10562 19:27:35.544534 <6>[ 1.633661] e1000e: Intel(R) PRO/1000 Network Driver
10563 19:27:35.550775 <6>[ 1.638877] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10564 19:27:35.557898 <6>[ 1.645062] igb: Intel(R) Gigabit Ethernet Network Driver
10565 19:27:35.564242 <6>[ 1.650713] igb: Copyright (c) 2007-2014 Intel Corporation.
10566 19:27:35.570879 <6>[ 1.656549] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10567 19:27:35.577826 <6>[ 1.663067] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10568 19:27:35.581075 <6>[ 1.669528] sky2: driver version 1.30
10569 19:27:35.587416 <6>[ 1.674511] VFIO - User Level meta-driver version: 0.3
10570 19:27:35.594458 <6>[ 1.682711] usbcore: registered new interface driver usb-storage
10571 19:27:35.601457 <6>[ 1.689160] usbcore: registered new device driver onboard-usb-hub
10572 19:27:35.610303 <6>[ 1.698298] mt6397-rtc mt6359-rtc: registered as rtc0
10573 19:27:35.620251 <6>[ 1.703762] mt6397-rtc mt6359-rtc: setting system clock to 2024-04-18T19:27:35 UTC (1713468455)
10574 19:27:35.623634 <6>[ 1.713320] i2c_dev: i2c /dev entries driver
10575 19:27:35.640584 <6>[ 1.724992] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10576 19:27:35.646989 <4>[ 1.733716] cpu cpu0: supply cpu not found, using dummy regulator
10577 19:27:35.653932 <4>[ 1.740132] cpu cpu1: supply cpu not found, using dummy regulator
10578 19:27:35.660351 <4>[ 1.746543] cpu cpu2: supply cpu not found, using dummy regulator
10579 19:27:35.666957 <4>[ 1.752941] cpu cpu3: supply cpu not found, using dummy regulator
10580 19:27:35.673621 <4>[ 1.759361] cpu cpu4: supply cpu not found, using dummy regulator
10581 19:27:35.680202 <4>[ 1.765762] cpu cpu5: supply cpu not found, using dummy regulator
10582 19:27:35.686779 <4>[ 1.772158] cpu cpu6: supply cpu not found, using dummy regulator
10583 19:27:35.690176 <4>[ 1.778567] cpu cpu7: supply cpu not found, using dummy regulator
10584 19:27:35.712415 <6>[ 1.800219] cpu cpu0: EM: created perf domain
10585 19:27:35.715922 <6>[ 1.805157] cpu cpu4: EM: created perf domain
10586 19:27:35.723029 <6>[ 1.810724] sdhci: Secure Digital Host Controller Interface driver
10587 19:27:35.729366 <6>[ 1.817157] sdhci: Copyright(c) Pierre Ossman
10588 19:27:35.735788 <6>[ 1.822119] Synopsys Designware Multimedia Card Interface Driver
10589 19:27:35.742436 <6>[ 1.828763] sdhci-pltfm: SDHCI platform and OF driver helper
10590 19:27:35.746066 <6>[ 1.828909] mmc0: CQHCI version 5.10
10591 19:27:35.752762 <6>[ 1.838740] ledtrig-cpu: registered to indicate activity on CPUs
10592 19:27:35.758952 <6>[ 1.845700] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10593 19:27:35.765663 <6>[ 1.852756] usbcore: registered new interface driver usbhid
10594 19:27:35.769258 <6>[ 1.858581] usbhid: USB HID core driver
10595 19:27:35.775780 <6>[ 1.862775] spi_master spi0: will run message pump with realtime priority
10596 19:27:35.817681 <6>[ 1.899089] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10597 19:27:35.836355 <6>[ 1.914112] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10598 19:27:35.843422 <6>[ 1.928954] cros-ec-spi spi0.0: Chrome EC device registered
10599 19:27:35.846448 <6>[ 1.935011] mmc0: Command Queue Engine enabled
10600 19:27:35.853362 <6>[ 1.939750] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10601 19:27:35.859759 <6>[ 1.947417] mmcblk0: mmc0:0001 DA4128 116 GiB
10602 19:27:35.867691 <6>[ 1.955817] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10603 19:27:35.874972 <6>[ 1.962900] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10604 19:27:35.881498 <6>[ 1.968935] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10605 19:27:35.891848 <6>[ 1.974110] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10606 19:27:35.898282 <6>[ 1.974784] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10607 19:27:35.901568 <6>[ 1.984816] NET: Registered PF_PACKET protocol family
10608 19:27:35.908145 <6>[ 1.995382] 9pnet: Installing 9P2000 support
10609 19:27:35.911128 <5>[ 1.999947] Key type dns_resolver registered
10610 19:27:35.914687 <6>[ 2.004908] registered taskstats version 1
10611 19:27:35.920979 <5>[ 2.009300] Loading compiled-in X.509 certificates
10612 19:27:35.951746 <4>[ 2.033196] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10613 19:27:35.961411 <4>[ 2.043944] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10614 19:27:35.968095 <3>[ 2.054561] debugfs: File 'uA_load' in directory '/' already present!
10615 19:27:35.975110 <3>[ 2.061279] debugfs: File 'min_uV' in directory '/' already present!
10616 19:27:35.981430 <3>[ 2.067893] debugfs: File 'max_uV' in directory '/' already present!
10617 19:27:35.987971 <3>[ 2.074503] debugfs: File 'constraint_flags' in directory '/' already present!
10618 19:27:35.999511 <3>[ 2.084451] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10619 19:27:36.013219 <6>[ 2.101297] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10620 19:27:36.020265 <6>[ 2.108086] xhci-mtk 11200000.usb: xHCI Host Controller
10621 19:27:36.026563 <6>[ 2.113588] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10622 19:27:36.036655 <6>[ 2.121509] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10623 19:27:36.043474 <6>[ 2.130943] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10624 19:27:36.049894 <6>[ 2.137141] xhci-mtk 11200000.usb: xHCI Host Controller
10625 19:27:36.056501 <6>[ 2.142649] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10626 19:27:36.062961 <6>[ 2.150305] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10627 19:27:36.070072 <6>[ 2.158247] hub 1-0:1.0: USB hub found
10628 19:27:36.073639 <6>[ 2.162276] hub 1-0:1.0: 1 port detected
10629 19:27:36.083172 <6>[ 2.166570] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10630 19:27:36.086832 <6>[ 2.175388] hub 2-0:1.0: USB hub found
10631 19:27:36.090219 <6>[ 2.179407] hub 2-0:1.0: 1 port detected
10632 19:27:36.099214 <6>[ 2.187158] mtk-msdc 11f70000.mmc: Got CD GPIO
10633 19:27:36.112251 <6>[ 2.197153] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10634 19:27:36.119030 <6>[ 2.205426] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10635 19:27:36.129080 <4>[ 2.213365] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10636 19:27:36.138781 <6>[ 2.222914] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10637 19:27:36.145412 <6>[ 2.230997] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10638 19:27:36.155308 <6>[ 2.239038] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10639 19:27:36.161842 <6>[ 2.246952] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10640 19:27:36.168824 <6>[ 2.254786] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10641 19:27:36.178982 <6>[ 2.262604] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10642 19:27:36.188743 <6>[ 2.273080] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10643 19:27:36.195339 <6>[ 2.281438] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10644 19:27:36.204979 <6>[ 2.289808] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10645 19:27:36.215233 <6>[ 2.298148] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10646 19:27:36.221378 <6>[ 2.306498] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10647 19:27:36.231446 <6>[ 2.314836] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10648 19:27:36.237940 <6>[ 2.323185] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10649 19:27:36.247772 <6>[ 2.331523] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10650 19:27:36.254836 <6>[ 2.339870] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10651 19:27:36.264538 <6>[ 2.348208] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10652 19:27:36.270973 <6>[ 2.356546] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10653 19:27:36.281254 <6>[ 2.364884] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10654 19:27:36.287665 <6>[ 2.373221] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10655 19:27:36.297344 <6>[ 2.381559] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10656 19:27:36.304048 <6>[ 2.389897] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10657 19:27:36.310534 <6>[ 2.398671] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10658 19:27:36.317436 <6>[ 2.405844] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10659 19:27:36.324532 <6>[ 2.412618] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10660 19:27:36.334504 <6>[ 2.419386] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10661 19:27:36.340850 <6>[ 2.426318] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10662 19:27:36.347852 <6>[ 2.433187] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10663 19:27:36.357750 <6>[ 2.442324] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10664 19:27:36.367499 <6>[ 2.451477] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10665 19:27:36.377836 <6>[ 2.460821] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10666 19:27:36.387635 <6>[ 2.470290] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10667 19:27:36.397283 <6>[ 2.479757] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10668 19:27:36.403900 <6>[ 2.488876] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10669 19:27:36.413994 <6>[ 2.498342] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10670 19:27:36.423980 <6>[ 2.507462] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10671 19:27:36.434028 <6>[ 2.516757] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10672 19:27:36.443576 <6>[ 2.526917] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10673 19:27:36.453646 <6>[ 2.538378] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10674 19:27:36.460259 <6>[ 2.547973] Trying to probe devices needed for running init ...
10675 19:27:36.510699 <6>[ 2.595545] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10676 19:27:36.665184 <6>[ 2.753550] hub 1-1:1.0: USB hub found
10677 19:27:36.668565 <6>[ 2.758056] hub 1-1:1.0: 4 ports detected
10678 19:27:36.678861 <6>[ 2.766812] hub 1-1:1.0: USB hub found
10679 19:27:36.681800 <6>[ 2.771183] hub 1-1:1.0: 4 ports detected
10680 19:27:36.790881 <6>[ 2.875619] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10681 19:27:36.817027 <6>[ 2.905191] hub 2-1:1.0: USB hub found
10682 19:27:36.820520 <6>[ 2.909706] hub 2-1:1.0: 3 ports detected
10683 19:27:36.829233 <6>[ 2.917349] hub 2-1:1.0: USB hub found
10684 19:27:36.832632 <6>[ 2.921740] hub 2-1:1.0: 3 ports detected
10685 19:27:37.002561 <6>[ 3.087611] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10686 19:27:37.134549 <6>[ 3.222829] hub 1-1.4:1.0: USB hub found
10687 19:27:37.138161 <6>[ 3.227440] hub 1-1.4:1.0: 2 ports detected
10688 19:27:37.146583 <6>[ 3.234662] hub 1-1.4:1.0: USB hub found
10689 19:27:37.149455 <6>[ 3.239214] hub 1-1.4:1.0: 2 ports detected
10690 19:27:37.214648 <6>[ 3.299647] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10691 19:27:37.446496 <6>[ 3.531579] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10692 19:27:37.638363 <6>[ 3.723590] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10693 19:27:48.740592 <6>[ 14.833069] ALSA device list:
10694 19:27:48.746869 <6>[ 14.836388] No soundcards found.
10695 19:27:48.754247 <6>[ 14.843818] Freeing unused kernel memory: 8448K
10696 19:27:48.757435 <6>[ 14.848812] Run /init as init process
10697 19:27:48.766788 Loading, please wait...
10698 19:27:48.793460 Starting systemd-udevd version 252.22-1~deb12u1
10699 19:27:48.793641
10700 19:27:49.028507 <6>[ 15.115037] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10701 19:27:49.039938 <6>[ 15.129551] remoteproc remoteproc0: scp is available
10702 19:27:49.047016 <6>[ 15.135842] remoteproc remoteproc0: powering up scp
10703 19:27:49.053225 <6>[ 15.141022] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10704 19:27:49.060005 <6>[ 15.149467] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10705 19:27:49.073209 <6>[ 15.159772] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10706 19:27:49.079886 <6>[ 15.167403] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10707 19:27:49.090046 <6>[ 15.168640] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10708 19:27:49.096700 <6>[ 15.176108] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10709 19:27:49.103358 <6>[ 15.193174] usbcore: registered new device driver r8152-cfgselector
10710 19:27:49.113811 <4>[ 15.193588] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10711 19:27:49.124880 <4>[ 15.211061] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10712 19:27:49.128267 <6>[ 15.211146] mc: Linux media interface: v0.10
10713 19:27:49.134630 <3>[ 15.214278] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10714 19:27:49.144825 <3>[ 15.214300] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10715 19:27:49.151073 <3>[ 15.214304] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10716 19:27:49.160974 <4>[ 15.222651] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10717 19:27:49.167818 <4>[ 15.222651] Fallback method does not support PEC.
10718 19:27:49.174512 <3>[ 15.224659] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10719 19:27:49.181087 <6>[ 15.240738] videodev: Linux video capture interface: v2.00
10720 19:27:49.187734 <3>[ 15.247679] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10721 19:27:49.194348 <6>[ 15.280389] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10722 19:27:49.204070 <6>[ 15.280428] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10723 19:27:49.210592 <6>[ 15.280436] remoteproc remoteproc0: remote processor scp is now up
10724 19:27:49.217183 <3>[ 15.282937] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10725 19:27:49.227302 <6>[ 15.293425] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10726 19:27:49.237195 <3>[ 15.298607] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10727 19:27:49.243752 <6>[ 15.300411] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10728 19:27:49.250191 <6>[ 15.300862] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10729 19:27:49.256821 <6>[ 15.300870] pci_bus 0000:00: root bus resource [bus 00-ff]
10730 19:27:49.263670 <6>[ 15.300877] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10731 19:27:49.273731 <6>[ 15.300883] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10732 19:27:49.280266 <6>[ 15.300918] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10733 19:27:49.287011 <6>[ 15.300946] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10734 19:27:49.293324 <6>[ 15.301045] pci 0000:00:00.0: supports D1 D2
10735 19:27:49.299838 <6>[ 15.301049] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10736 19:27:49.306588 <6>[ 15.302850] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10737 19:27:49.313132 <6>[ 15.302965] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10738 19:27:49.323456 <6>[ 15.302998] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10739 19:27:49.330038 <6>[ 15.303022] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10740 19:27:49.336676 <6>[ 15.303041] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10741 19:27:49.340262 <6>[ 15.303169] pci 0000:01:00.0: supports D1 D2
10742 19:27:49.346933 <6>[ 15.303173] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10743 19:27:49.356254 <6>[ 15.305539] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10744 19:27:49.366497 <6>[ 15.306112] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10745 19:27:49.373171 <3>[ 15.313194] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10746 19:27:49.382709 <6>[ 15.315787] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10747 19:27:49.389729 <6>[ 15.319372] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10748 19:27:49.396626 <6>[ 15.319407] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10749 19:27:49.403231 <6>[ 15.319413] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10750 19:27:49.413305 <6>[ 15.319427] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10751 19:27:49.419867 <6>[ 15.319443] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10752 19:27:49.429692 <6>[ 15.319460] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10753 19:27:49.433192 <6>[ 15.319477] pci 0000:00:00.0: PCI bridge to [bus 01]
10754 19:27:49.442917 <6>[ 15.319485] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10755 19:27:49.449666 <6>[ 15.319613] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10756 19:27:49.452740 <6>[ 15.320524] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10757 19:27:49.459697 <6>[ 15.320920] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10758 19:27:49.469234 <6>[ 15.330428] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10759 19:27:49.479260 <3>[ 15.331205] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10760 19:27:49.485830 <4>[ 15.347454] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10761 19:27:49.496106 <3>[ 15.352163] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10762 19:27:49.502707 <4>[ 15.359185] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10763 19:27:49.512715 <5>[ 15.361541] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10764 19:27:49.519145 <3>[ 15.369195] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10765 19:27:49.525918 <5>[ 15.378836] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10766 19:27:49.532218 <3>[ 15.382898] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10767 19:27:49.542183 <3>[ 15.383027] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10768 19:27:49.545288 <6>[ 15.384288] Bluetooth: Core ver 2.22
10769 19:27:49.551869 <6>[ 15.384350] NET: Registered PF_BLUETOOTH protocol family
10770 19:27:49.558781 <6>[ 15.384351] Bluetooth: HCI device and connection manager initialized
10771 19:27:49.561818 <6>[ 15.384377] Bluetooth: HCI socket layer initialized
10772 19:27:49.568701 <6>[ 15.384385] Bluetooth: L2CAP socket layer initialized
10773 19:27:49.572191 <6>[ 15.384398] Bluetooth: SCO socket layer initialized
10774 19:27:49.581914 <5>[ 15.388574] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10775 19:27:49.588612 <3>[ 15.394401] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10776 19:27:49.598152 <4>[ 15.402792] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10777 19:27:49.608187 <3>[ 15.409155] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10778 19:27:49.614681 <6>[ 15.410020] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10779 19:27:49.624880 <6>[ 15.411250] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10780 19:27:49.631465 <6>[ 15.411512] usbcore: registered new interface driver uvcvideo
10781 19:27:49.638057 <6>[ 15.416725] cfg80211: failed to load regulatory.db
10782 19:27:49.644277 <6>[ 15.419721] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10783 19:27:49.651264 <3>[ 15.423974] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10784 19:27:49.661105 <3>[ 15.423980] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10785 19:27:49.668664 <3>[ 15.427786] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10786 19:27:49.674572 <6>[ 15.431576] r8152 2-1.3:1.0 eth0: v1.12.13
10787 19:27:49.680599 <3>[ 15.436039] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10788 19:27:49.687422 <6>[ 15.436544] usbcore: registered new interface driver btusb
10789 19:27:49.693854 <6>[ 15.442915] usbcore: registered new interface driver r8152
10790 19:27:49.703934 <4>[ 15.443579] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10791 19:27:49.710706 <3>[ 15.443589] Bluetooth: hci0: Failed to load firmware file (-2)
10792 19:27:49.714094 <3>[ 15.443593] Bluetooth: hci0: Failed to set up firmware (-2)
10793 19:27:49.727123 <4>[ 15.443596] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10794 19:27:49.733431 <3>[ 15.490875] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10795 19:27:49.740165 <6>[ 15.516104] usbcore: registered new interface driver cdc_ether
10796 19:27:49.746841 <6>[ 15.526956] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10797 19:27:49.753451 <6>[ 15.537038] usbcore: registered new interface driver r8153_ecm
10798 19:27:49.759879 <6>[ 15.543228] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10799 19:27:49.766598 <6>[ 15.571650] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
10800 19:27:49.773249 <6>[ 15.592889] mt7921e 0000:01:00.0: ASIC revision: 79610010
10801 19:27:49.872501 <6>[ 15.958789] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10802 19:27:49.875382 <6>[ 15.958789]
10803 19:27:49.890622 Begin: Loading essential drivers ... done.
10804 19:27:49.894227 Begin: Running /scripts/init-premount ... done.
10805 19:27:49.900683 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10806 19:27:49.910281 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10807 19:27:49.914104 Device /sys/class/net/enx0024323078ff found
10808 19:27:49.914196 done.
10809 19:27:49.945786 Begin: Waiting up to 180 secs for any network device to become available ... done.
10810 19:27:49.976974 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10811 19:27:50.140519 <6>[ 16.227281] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10812 19:27:50.997488 <6>[ 17.087472] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10813 19:27:51.031351 <6>[ 17.120920] r8152 2-1.3:1.0 enx0024323078ff: carrier on
10814 19:27:51.113918 IP-Config: no response after 2 secs - giving up
10815 19:27:51.172873 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10816 19:27:51.194004 IP-Config: wlp1s0 hardware address d8:f3:bc:78:28:07 mtu 1500 DHCP
10817 19:27:51.883651 IP-Config: enx0024323078ff complete (dhcp from 192.168.201.1):
10818 19:27:51.890652 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10819 19:27:51.897121 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10820 19:27:51.903786 host : mt8192-asurada-spherion-r0-cbg-8
10821 19:27:51.910410 domain : lava-rack
10822 19:27:51.913411 rootserver: 192.168.201.1 rootpath:
10823 19:27:51.916358 filename :
10824 19:27:52.053652 done.
10825 19:27:52.061380 Begin: Running /scripts/nfs-bottom ... done.
10826 19:27:52.075840 Begin: Running /scripts/init-bottom ... done.
10827 19:27:53.440295 <6>[ 19.530135] NET: Registered PF_INET6 protocol family
10828 19:27:53.449541 <6>[ 19.539746] Segment Routing with IPv6
10829 19:27:53.452798 <6>[ 19.543730] In-situ OAM (IOAM) with IPv6
10830 19:27:53.659124 <30>[ 19.722960] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10831 19:27:53.665860 <30>[ 19.756058] systemd[1]: Detected architecture arm64.
10832 19:27:53.674319
10833 19:27:53.677719 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10834 19:27:53.677813
10835 19:27:53.677877
10836 19:27:53.707570 <30>[ 19.797414] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10837 19:27:54.760061 <30>[ 20.846703] systemd[1]: Queued start job for default target graphical.target.
10838 19:27:54.801922 <30>[ 20.888795] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10839 19:27:54.808243 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10840 19:27:54.808332
10841 19:27:54.830543 <30>[ 20.917354] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10842 19:27:54.840190 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10843 19:27:54.840280
10844 19:27:54.858225 <30>[ 20.945307] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10845 19:27:54.868470 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10846 19:27:54.868560
10847 19:27:54.885795 <30>[ 20.972901] systemd[1]: Created slice user.slice - User and Session Slice.
10848 19:27:54.892588 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10849 19:27:54.892695
10850 19:27:54.916071 <30>[ 20.999848] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10851 19:27:54.922651 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10852 19:27:54.922752
10853 19:27:54.944331 <30>[ 21.027780] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10854 19:27:54.950591 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10855 19:27:54.950678
10856 19:27:54.979045 <30>[ 21.056239] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10857 19:27:54.989164 <30>[ 21.076146] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10858 19:27:54.995819 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10859 19:27:54.995924
10860 19:27:55.012756 <30>[ 21.099565] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10861 19:27:55.019093 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10862 19:27:55.019174
10863 19:27:55.036730 <30>[ 21.123625] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10864 19:27:55.046798 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10865 19:27:55.046889
10866 19:27:55.061244 <30>[ 21.151649] systemd[1]: Reached target paths.target - Path Units.
10867 19:27:55.067845 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10868 19:27:55.071454
10869 19:27:55.089217 <30>[ 21.175998] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10870 19:27:55.095406 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10871 19:27:55.095523
10872 19:27:55.109225 <30>[ 21.199557] systemd[1]: Reached target slices.target - Slice Units.
10873 19:27:55.119551 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10874 19:27:55.119655
10875 19:27:55.133830 <30>[ 21.224063] systemd[1]: Reached target swap.target - Swaps.
10876 19:27:55.140206 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10877 19:27:55.140291
10878 19:27:55.161260 <30>[ 21.248107] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10879 19:27:55.171178 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10880 19:27:55.171263
10881 19:27:55.189709 <30>[ 21.276501] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10882 19:27:55.199588 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10883 19:27:55.199675
10884 19:27:55.220209 <30>[ 21.306966] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10885 19:27:55.229611 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10886 19:27:55.229702
10887 19:27:55.246111 <30>[ 21.333076] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10888 19:27:55.256015 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10889 19:27:55.256101
10890 19:27:55.272932 <30>[ 21.360208] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10891 19:27:55.279569 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10892 19:27:55.279692
10893 19:27:55.298096 <30>[ 21.385050] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10894 19:27:55.308142 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10895 19:27:55.308256
10896 19:27:55.327688 <30>[ 21.414554] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10897 19:27:55.337342 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10898 19:27:55.337480
10899 19:27:55.353243 <30>[ 21.440037] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10900 19:27:55.362900 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10901 19:27:55.362987
10902 19:27:55.413352 <30>[ 21.500047] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10903 19:27:55.419916 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10904 19:27:55.420015
10905 19:27:55.439090 <30>[ 21.526162] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10906 19:27:55.445421 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10907 19:27:55.445554
10908 19:27:55.468487 <30>[ 21.555422] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10909 19:27:55.475151 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10910 19:27:55.475232
10911 19:27:55.499435 <30>[ 21.580116] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10912 19:27:55.515713 <30>[ 21.602707] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10913 19:27:55.525788 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10914 19:27:55.525907
10915 19:27:55.550181 <30>[ 21.637200] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10916 19:27:55.556963 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10917 19:27:55.557048
10918 19:27:55.582269 <30>[ 21.669190] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10919 19:27:55.588858 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10920 19:27:55.588943
10921 19:27:55.614147 <30>[ 21.701118] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10922 19:27:55.627414 Starting [0;1;39mmodprobe@drm.service<6>[ 21.712664] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10923 19:27:55.630791 [0m - Load Kernel Module drm...
10924 19:27:55.630875
10925 19:27:55.654305 <30>[ 21.741273] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10926 19:27:55.664121 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10927 19:27:55.664206
10928 19:27:55.685949 <30>[ 21.773090] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10929 19:27:55.692360 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10930 19:27:55.692447
10931 19:27:55.724330 <6>[ 21.814407] fuse: init (API version 7.37)
10932 19:27:55.757366 <30>[ 21.844341] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10933 19:27:55.763739 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10934 19:27:55.763832
10935 19:27:55.790208 <30>[ 21.877316] systemd[1]: Starting systemd-journald.service - Journal Service...
10936 19:27:55.796770 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10937 19:27:55.796854
10938 19:27:55.829499 <30>[ 21.916373] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10939 19:27:55.836148 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10940 19:27:55.836249
10941 19:27:55.920693 <30>[ 22.004528] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10942 19:27:55.927324 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10943 19:27:55.927425
10944 19:27:55.948316 <30>[ 22.035028] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10945 19:27:55.957720 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10946 19:27:55.957806
10947 19:27:55.983618 <30>[ 22.070737] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10948 19:27:55.990302 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10949 19:27:55.993250
10950 19:27:56.018419 <30>[ 22.105413] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10951 19:27:56.027939 [[0;32m OK [<3>[ 22.114339] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10952 19:27:56.035009 0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10953 19:27:56.035096
10954 19:27:56.058224 <30>[ 22.144502] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10955 19:27:56.068161 [[0;32m OK [<3>[ 22.153411] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10956 19:27:56.074409 0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10957 19:27:56.074494
10958 19:27:56.093732 <30>[ 22.180711] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10959 19:27:56.100358 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10960 19:27:56.100443
10961 19:27:56.111103 <3>[ 22.198483] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10962 19:27:56.125765 <30>[ 22.212819] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10963 19:27:56.133670 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10964 19:27:56.136590
10965 19:27:56.142953 <3>[ 22.229876] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10966 19:27:56.154332 <30>[ 22.241350] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10967 19:27:56.161063 <30>[ 22.249182] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10968 19:27:56.174510 [[0;32m OK [0m] Finished [0<3>[ 22.259968] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10969 19:27:56.177743 ;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10970 19:27:56.177854
10971 19:27:56.194347 <30>[ 22.284186] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10972 19:27:56.204053 <3>[ 22.289729] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10973 19:27:56.214100 <30>[ 22.291859] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10974 19:27:56.221121 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10975 19:27:56.221208
10976 19:27:56.234790 <3>[ 22.321834] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10977 19:27:56.244730 <30>[ 22.332065] systemd[1]: modprobe@drm.service: Deactivated successfully.
10978 19:27:56.251754 <30>[ 22.339976] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10979 19:27:56.265846 [[0;32m OK [0m] Finished [0;1;39mmodprobe@d<3>[ 22.351170] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10980 19:27:56.269327 rm.service[0m - Load Kernel Module drm.
10981 19:27:56.269412
10982 19:27:56.290613 <30>[ 22.377373] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10983 19:27:56.297453 <3>[ 22.381454] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10984 19:27:56.307255 <30>[ 22.385814] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10985 19:27:56.317580 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10986 19:27:56.317668
10987 19:27:56.328171 <3>[ 22.415092] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10988 19:27:56.338772 <30>[ 22.425991] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10989 19:27:56.346186 <30>[ 22.433654] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10990 19:27:56.352531 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10991 19:27:56.352619
10992 19:27:56.371187 <30>[ 22.460710] systemd[1]: modprobe@loop.service: Deactivated successfully.
10993 19:27:56.381388 <30>[ 22.468647] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
10994 19:27:56.387903 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10995 19:27:56.387992
10996 19:27:56.413460 <30>[ 22.500077] systemd[1]: Started systemd-journald.service - Journal Service.
10997 19:27:56.420136 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10998 19:27:56.420224
10999 19:27:56.436450 <4>[ 22.515225] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
11000 19:27:56.443130 <3>[ 22.530874] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
11001 19:27:56.449975 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
11002 19:27:56.453115
11003 19:27:56.471823 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
11004 19:27:56.471919
11005 19:27:56.490336 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
11006 19:27:56.490428
11007 19:27:56.510174 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
11008 19:27:56.510263
11009 19:27:56.531461 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
11010 19:27:56.531553
11011 19:27:56.589083 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
11012 19:27:56.589222
11013 19:27:56.607286 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
11014 19:27:56.607375
11015 19:27:56.632409 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
11016 19:27:56.632504
11017 19:27:56.653809 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
11018 19:27:56.653897
11019 19:27:56.695468 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Ke<46>[ 22.781585] systemd-journald[300]: Received client request to flush runtime journal.
11020 19:27:56.695562 rnel Variables...
11021 19:27:56.695629
11022 19:27:56.720439 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
11023 19:27:56.720528
11024 19:27:56.752227 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
11025 19:27:56.752337
11026 19:27:56.769149 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
11027 19:27:56.769252
11028 19:27:56.786411 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
11029 19:27:56.786501
11030 19:27:57.466769 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
11031 19:27:57.466918
11032 19:27:57.883861 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
11033 19:27:57.884006
11034 19:27:57.934179 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
11035 19:27:57.934352
11036 19:27:58.095701 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11037 19:27:58.095850
11038 19:27:58.209826 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11039 19:27:58.209975
11040 19:27:58.233116 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11041 19:27:58.233266
11042 19:27:58.256517 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11043 19:27:58.256676
11044 19:27:58.301055 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11045 19:27:58.301171
11046 19:27:58.322371 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11047 19:27:58.322463
11048 19:27:58.597903 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11049 19:27:58.598057
11050 19:27:58.667006 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11051 19:27:58.667145
11052 19:27:58.711014 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11053 19:27:58.711118
11054 19:27:59.018630 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11055 19:27:59.018768
11056 19:27:59.078525 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11057 19:27:59.078653
11058 19:27:59.098012 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11059 19:27:59.098130
11060 19:27:59.137772 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11061 19:27:59.137876
11062 19:27:59.213363 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11063 19:27:59.213543
11064 19:27:59.236435 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11065 19:27:59.236531
11066 19:27:59.257735 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11067 19:27:59.257821
11068 19:27:59.283442 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11069 19:27:59.283538
11070 19:27:59.335494 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11071 19:27:59.335618
11072 19:27:59.360407 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11073 19:27:59.360505
11074 19:27:59.409860 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11075 19:27:59.410000
11076 19:27:59.429774 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11077 19:27:59.429862
11078 19:27:59.457530 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11079 19:27:59.457639
11080 19:27:59.481430 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11081 19:27:59.481559
11082 19:27:59.502060 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11083 19:27:59.502171
11084 19:27:59.525694 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11085 19:27:59.525789
11086 19:27:59.552505 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11087 19:27:59.552604
11088 19:27:59.571526 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11089 19:27:59.571659
11090 19:27:59.588569 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11091 19:27:59.588707
11092 19:27:59.627761 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11093 19:27:59.627874
11094 19:27:59.647564 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11095 19:27:59.647668
11096 19:27:59.664318 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11097 19:27:59.664417
11098 19:27:59.679936 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11099 19:27:59.680039
11100 19:27:59.698239 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11101 19:27:59.698339
11102 19:27:59.716214 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11103 19:27:59.716305
11104 19:27:59.722570 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11105 19:27:59.722684
11106 19:27:59.780664 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11107 19:27:59.780787
11108 19:27:59.810373 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11109 19:27:59.810472
11110 19:27:59.854927 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11111 19:27:59.855051
11112 19:27:59.902887 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11113 19:27:59.903038
11114 19:28:00.105024 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11115 19:28:00.105183
11116 19:28:00.169894 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11117 19:28:00.170054
11118 19:28:00.197765 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11119 19:28:00.197907
11120 19:28:00.215734 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11121 19:28:00.215870
11122 19:28:00.232216 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11123 19:28:00.232355
11124 19:28:00.266762 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11125 19:28:00.266907
11126 19:28:00.286092 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11127 19:28:00.286213
11128 19:28:00.318810 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11129 19:28:00.318903
11130 19:28:00.338015 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11131 19:28:00.338156
11132 19:28:00.410789 Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
11133 19:28:00.410939
11134 19:28:00.435154 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11135 19:28:00.435283
11136 19:28:00.483402 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11137 19:28:00.483545
11138 19:28:00.551484 [[0;32m OK [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
11139 19:28:00.551632
11140 19:28:00.653001
11141 19:28:00.653169
11142 19:28:00.656369 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11143 19:28:00.656469
11144 19:28:00.660130 debian-bookworm-arm64 login: root (automatic login)
11145 19:28:00.660202
11146 19:28:00.660264
11147 19:28:00.918534 Linux debian-bookworm-arm64 6.1.86-cip19 #1 SMP PREEMPT Thu Apr 18 19:05:54 UTC 2024 aarch64
11148 19:28:00.918683
11149 19:28:00.925109 The programs included with the Debian GNU/Linux system are free software;
11150 19:28:00.932120 the exact distribution terms for each program are described in the
11151 19:28:00.935450 individual files in /usr/share/doc/*/copyright.
11152 19:28:00.935562
11153 19:28:00.941529 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11154 19:28:00.945248 permitted by applicable law.
11155 19:28:01.036614 Matched prompt #10: / #
11157 19:28:01.036996 Setting prompt string to ['/ #']
11158 19:28:01.037135 end: 2.2.5.1 login-action (duration 00:00:28) [common]
11160 19:28:01.037450 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
11161 19:28:01.037629 start: 2.2.6 expect-shell-connection (timeout 00:03:13) [common]
11162 19:28:01.037737 Setting prompt string to ['/ #']
11163 19:28:01.037829 Forcing a shell prompt, looking for ['/ #']
11165 19:28:01.088095 / #
11166 19:28:01.088237 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11167 19:28:01.088346 Waiting using forced prompt support (timeout 00:02:30)
11168 19:28:01.092972
11169 19:28:01.093267 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11170 19:28:01.093390 start: 2.2.7 export-device-env (timeout 00:03:13) [common]
11172 19:28:01.193740 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/13420400/extract-nfsrootfs-co75676u'
11173 19:28:01.199230 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/13420400/extract-nfsrootfs-co75676u'
11175 19:28:01.299741 / # export NFS_SERVER_IP='192.168.201.1'
11176 19:28:01.305467 export NFS_SERVER_IP='192.168.201.1'
11177 19:28:01.305795 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11178 19:28:01.305894 end: 2.2 depthcharge-retry (duration 00:01:48) [common]
11179 19:28:01.305987 end: 2 depthcharge-action (duration 00:01:48) [common]
11180 19:28:01.306106 start: 3 lava-test-retry (timeout 00:30:00) [common]
11181 19:28:01.306240 start: 3.1 lava-test-shell (timeout 00:30:00) [common]
11182 19:28:01.306346 Using namespace: common
11184 19:28:01.406706 / # #
11185 19:28:01.406906 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:30:00)
11186 19:28:01.412621 #
11187 19:28:01.412925 Using /lava-13420400
11189 19:28:01.513260 / # export SHELL=/bin/sh
11190 19:28:01.519348 export SHELL=/bin/sh
11192 19:28:01.619823 / # . /lava-13420400/environment
11193 19:28:01.625144 . /lava-13420400/environment
11195 19:28:01.731195 / # /lava-13420400/bin/lava-test-runner /lava-13420400/0
11196 19:28:01.731377 Test shell timeout: 10s (minimum of the action and connection timeout)
11197 19:28:01.736952 /lava-13420400/bin/lava-test-runner /lava-13420400/0
11198 19:28:01.985867 + export TESTRUN_ID=0_lc-compliance
11199 19:28:01.992521 + cd /lava-13420400/0/tests/0_lc-compliance
11200 19:28:01.992636 + cat uuid
11201 19:28:02.001455 + UUID=13420400_1.6.2.3.1
11202 19:28:02.001588 + set +x
11203 19:28:02.008449 <LAVA_SIGNAL_STARTRUN 0_lc-compliance 13420400_1.6.2.3.1>
11204 19:28:02.008732 Received signal: <STARTRUN> 0_lc-compliance 13420400_1.6.2.3.1
11205 19:28:02.008806 Starting test lava.0_lc-compliance (13420400_1.6.2.3.1)
11206 19:28:02.008960 Skipping test definition patterns.
11207 19:28:02.011920 + /usr/bin/lc-compliance-parser.sh
11208 19:28:03.633195 [0:00:29.640821353] [410] [1;32m INFO [1;37mCamera [1;34mcamera_manager.cpp:284 [0mlibcamera v0.0.0+1-01935edb
11209 19:28:03.636286 Using camera /base/soc/usb@11200000-1.4.1:1.0-04f2:b741
11210 19:28:03.651388 [0:00:29.659577704] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11211 19:28:03.708263 [0:00:29.716375830] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11212 19:28:03.711288 [==========] Running 120 tests from 1 test suite.
11213 19:28:03.761625 [0:00:29.770420901] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11214 19:28:03.781462 [----------] Global test environment set-up.
11215 19:28:03.815336 [0:00:29.824445024] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11216 19:28:03.855590 [----------] 120 tests from CaptureTests/SingleStream
11217 19:28:03.927363 [ RUN ] CaptureTests/SingleStream.Capture/Raw_1
11218 19:28:03.986187 <LAVA_SIGNAL_TESTSET START CaptureTests/SingleStream>
11219 19:28:03.986509 Received signal: <TESTSET> START CaptureTests/SingleStream
11220 19:28:03.986600 Starting test_set CaptureTests/SingleStream
11221 19:28:03.989252 Camera needs 4 requests, can't test only 1
11222 19:28:04.059780 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11223 19:28:04.126347
11224 19:28:04.202440 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_1 (57 ms)
11225 19:28:04.242558 [0:00:30.255390481] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11226 19:28:04.290949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_1 RESULT=skip>
11227 19:28:04.291331 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_1 RESULT=skip
11229 19:28:04.305669 [ RUN ] CaptureTests/SingleStream.Capture/Raw_2
11230 19:28:04.351767 Camera needs 4 requests, can't test only 2
11231 19:28:04.432067 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11232 19:28:04.497754
11233 19:28:04.572175 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_2 (52 ms)
11234 19:28:04.652288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_2 RESULT=skip>
11235 19:28:04.652634 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_2 RESULT=skip
11237 19:28:04.667344 [ RUN ] CaptureTests/SingleStream.Capture/Raw_3
11238 19:28:04.726626 Camera needs 4 requests, can't test only 3
11239 19:28:04.799607 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11240 19:28:04.867692
11241 19:28:04.933231 [0:00:30.951283590] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11242 19:28:04.943436 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_3 (55 ms)
11243 19:28:05.030374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_3 RESULT=skip>
11244 19:28:05.030721 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_3 RESULT=skip
11246 19:28:05.044442 [ RUN ] CaptureTests/SingleStream.Capture/Raw_5
11247 19:28:05.092454 [ OK ] CaptureTests/SingleStream.Capture/Raw_5 (430 ms)
11248 19:28:05.175726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_5 RESULT=pass>
11249 19:28:05.176071 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_5 RESULT=pass
11251 19:28:05.190145 [ RUN ] CaptureTests/SingleStream.Capture/Raw_8
11252 19:28:05.238298 [ OK ] CaptureTests/SingleStream.Capture/Raw_8 (695 ms)
11253 19:28:05.323003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_8 RESULT=pass>
11254 19:28:05.323365 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_8 RESULT=pass
11256 19:28:05.337399 [ RUN ] CaptureTests/SingleStream.Capture/Raw_13
11257 19:28:06.180204 [ OK ] CaptureTests/SingleStream.Capture/Raw_13 (1262 ms)
11258 19:28:06.190116 [0:00:32.215030416] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11259 19:28:06.265210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_13 RESULT=pass>
11260 19:28:06.265551 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_13 RESULT=pass
11262 19:28:06.278703 [ RUN ] CaptureTests/SingleStream.Capture/Raw_21
11263 19:28:07.994855 [ OK ] CaptureTests/SingleStream.Capture/Raw_21 (1824 ms)
11264 19:28:08.004622 [0:00:34.039661062] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11265 19:28:08.082843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_21 RESULT=pass>
11266 19:28:08.083224 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_21 RESULT=pass
11268 19:28:08.097995 [ RUN ] CaptureTests/SingleStream.Capture/Raw_34
11269 19:28:10.719772 [ OK ] CaptureTests/SingleStream.Capture/Raw_34 (2736 ms)
11270 19:28:10.729485 [0:00:36.775786787] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11271 19:28:10.810935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_34 RESULT=pass>
11272 19:28:10.811296 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_34 RESULT=pass
11274 19:28:10.827794 [ RUN ] CaptureTests/SingleStream.Capture/Raw_55
11275 19:28:14.915461 [ OK ] CaptureTests/SingleStream.Capture/Raw_55 (4206 ms)
11276 19:28:14.925342 [0:00:40.982558141] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11277 19:28:15.007007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_55 RESULT=pass>
11278 19:28:15.007365 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_55 RESULT=pass
11280 19:28:15.022095 [ RUN ] CaptureTests/SingleStream.Capture/Raw_89
11281 19:28:19.967505 <6>[ 46.064175] vpu: disabling
11282 19:28:19.971122 <6>[ 46.067269] vproc2: disabling
11283 19:28:19.974150 <6>[ 46.070583] vproc1: disabling
11284 19:28:19.977795 <6>[ 46.073922] vaud18: disabling
11285 19:28:19.984252 <6>[ 46.077429] vsram_others: disabling
11286 19:28:19.987551 <6>[ 46.081386] va09: disabling
11287 19:28:19.990510 <6>[ 46.084545] vsram_md: disabling
11288 19:28:19.993820 <6>[ 46.088113] Vgpu: disabling
11289 19:28:21.491365 [ OK ] CaptureTests/SingleStream.Capture/Raw_89 (6584 ms)
11290 19:28:21.501098 [0:00:47.567187855] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11291 19:28:21.551777 [0:00:47.619662208] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11292 19:28:21.631835 [0:00:47.674406488] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11293 19:28:21.646274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_89 RESULT=pass>
11294 19:28:21.646616 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_89 RESULT=pass
11296 19:28:21.659695 [0:00:47.727697941] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11297 19:28:21.662818 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_1
11298 19:28:21.712272 Camera needs 4 requests, can't test only 1
11299 19:28:21.780988 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11300 19:28:21.846428
11301 19:28:21.928030 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_1 (53 ms)
11302 19:28:22.009664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip>
11303 19:28:22.010007 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip
11305 19:28:22.024593 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_2
11306 19:28:22.074828 Camera needs 4 requests, can't test only 2
11307 19:28:22.145160 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11308 19:28:22.214561
11309 19:28:22.287212 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_2 (53 ms)
11310 19:28:22.354088 [0:00:48.422924390] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11311 19:28:22.376730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip>
11312 19:28:22.377038 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip
11314 19:28:22.393848 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_3
11315 19:28:22.441941 Camera needs 4 requests, can't test only 3
11316 19:28:22.512902 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11317 19:28:22.583407
11318 19:28:22.660766 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_3 (54 ms)
11319 19:28:22.746374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip>
11320 19:28:22.746696 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip
11322 19:28:22.761989 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_5
11323 19:28:22.813330 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_5 (694 ms)
11324 19:28:22.912068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass>
11325 19:28:22.912404 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass
11327 19:28:22.928759 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_8
11328 19:28:23.252449 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_8 (906 ms)
11329 19:28:23.265646 [0:00:49.330271514] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11330 19:28:23.349819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass>
11331 19:28:23.350148 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass
11333 19:28:23.367547 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_13
11334 19:28:24.507162 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_13 (1255 ms)
11335 19:28:24.520297 [0:00:50.585174923] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11336 19:28:24.601953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass>
11337 19:28:24.602305 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass
11339 19:28:24.619434 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_21
11340 19:28:26.322069 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_21 (1816 ms)
11341 19:28:26.335276 [0:00:52.401708674] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11342 19:28:26.420071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass>
11343 19:28:26.420419 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass
11345 19:28:26.435750 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_34
11346 19:28:29.048475 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_34 (2727 ms)
11347 19:28:29.061976 [0:00:55.128990555] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11348 19:28:29.146925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass>
11349 19:28:29.147261 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass
11351 19:28:29.164475 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_55
11352 19:28:33.243657 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_55 (4195 ms)
11353 19:28:33.256343 [0:00:59.324562153] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11354 19:28:33.352732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass>
11355 19:28:33.353058 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass
11357 19:28:33.370647 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_89
11358 19:28:39.817462 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_89 (6574 ms)
11359 19:28:39.830374 [0:01:05.899509583] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11360 19:28:39.878900 [0:01:05.952984007] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11361 19:28:39.923199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass>
11362 19:28:39.923499 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass
11364 19:28:39.936548 [0:01:06.008150099] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11365 19:28:39.945914 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_1
11366 19:28:39.988323 [0:01:06.062338481] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11367 19:28:40.002433 Camera needs 4 requests, can't test only 1
11368 19:28:40.087446 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11369 19:28:40.164350
11370 19:28:40.247575 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_1 (53 ms)
11371 19:28:40.345636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip>
11372 19:28:40.345947 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip
11374 19:28:40.362976 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_2
11375 19:28:40.420942 Camera needs 4 requests, can't test only 2
11376 19:28:40.505003 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11377 19:28:40.584204
11378 19:28:40.667221 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_2 (55 ms)
11379 19:28:40.683030 [0:01:06.757234699] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11380 19:28:40.764396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip>
11381 19:28:40.764703 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip
11383 19:28:40.781830 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_3
11384 19:28:40.834729 Camera needs 4 requests, can't test only 3
11385 19:28:40.916409 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11386 19:28:40.993776
11387 19:28:41.076739 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_3 (54 ms)
11388 19:28:41.171546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip>
11389 19:28:41.171880 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip
11391 19:28:41.188917 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_5
11392 19:28:41.244288 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_5 (694 ms)
11393 19:28:41.341918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass>
11394 19:28:41.342232 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass
11396 19:28:41.361268 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_8
11397 19:28:41.581667 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_8 (906 ms)
11398 19:28:41.594667 [0:01:07.663958009] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11399 19:28:41.677529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass>
11400 19:28:41.677849 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass
11402 19:28:41.695142 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_13
11403 19:28:42.836292 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_13 (1254 ms)
11404 19:28:42.849560 [0:01:08.918778507] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11405 19:28:42.934873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass>
11406 19:28:42.935201 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass
11408 19:28:42.951703 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_21
11409 19:28:44.651325 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_21 (1814 ms)
11410 19:28:44.664044 [0:01:10.733143774] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11411 19:28:44.750956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass>
11412 19:28:44.751278 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass
11414 19:28:44.769709 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_34
11415 19:28:47.376696 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_34 (2725 ms)
11416 19:28:47.390138 [0:01:13.459303555] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11417 19:28:47.473962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass>
11418 19:28:47.474270 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass
11420 19:28:47.490187 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_55
11421 19:28:51.571384 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_55 (4194 ms)
11422 19:28:51.584556 [0:01:17.654597181] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11423 19:28:51.675630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass>
11424 19:28:51.675930 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass
11426 19:28:51.695338 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_89
11427 19:28:58.146935 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_89 (6575 ms)
11428 19:28:58.159932 [0:01:24.230557695] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11429 19:28:58.207156 [0:01:24.282430121] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11430 19:28:58.237125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass>
11431 19:28:58.237448 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass
11433 19:28:58.259355 [0:01:24.334498233] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11434 19:28:58.262319 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_1
11435 19:28:58.312160 [0:01:24.387301405] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11436 19:28:58.314912 Camera needs 4 requests, can't test only 1
11437 19:28:58.398926 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11438 19:28:58.475437
11439 19:28:58.562636 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_1 (52 ms)
11440 19:28:58.659395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip>
11441 19:28:58.659707 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip
11443 19:28:58.676320 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_2
11444 19:28:58.734460 Camera needs 4 requests, can't test only 2
11445 19:28:58.820362 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11446 19:28:58.901942
11447 19:28:58.984991 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_2 (51 ms)
11448 19:28:59.004043 [0:01:25.079590568] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11449 19:28:59.083254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip>
11450 19:28:59.083623 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip
11452 19:28:59.101091 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_3
11453 19:28:59.157232 Camera needs 4 requests, can't test only 3
11454 19:28:59.244535 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11455 19:28:59.326174
11456 19:28:59.413694 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_3 (52 ms)
11457 19:28:59.512011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip>
11458 19:28:59.512321 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip
11460 19:28:59.529615 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_5
11461 19:28:59.587452 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_5 (692 ms)
11462 19:28:59.685502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass>
11463 19:28:59.685812 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass
11465 19:28:59.701742 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_8
11466 19:28:59.900656 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_8 (903 ms)
11467 19:28:59.913914 [0:01:25.984218357] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11468 19:29:00.001199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass>
11469 19:29:00.001535 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass
11471 19:29:00.018994 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_13
11472 19:29:01.155687 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_13 (1254 ms)
11473 19:29:01.168428 [0:01:27.239327477] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11474 19:29:01.256554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass>
11475 19:29:01.256848 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass
11477 19:29:01.273496 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_21
11478 19:29:02.969883 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_21 (1814 ms)
11479 19:29:02.983287 [0:01:29.053903389] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11480 19:29:03.067832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass>
11481 19:29:03.068122 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass
11483 19:29:03.082321 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_34
11484 19:29:05.694090 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_34 (2724 ms)
11485 19:29:05.707589 [0:01:31.778632636] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11486 19:29:05.797770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass>
11487 19:29:05.798081 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass
11489 19:29:05.817039 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_55
11490 19:29:09.889868 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_55 (4194 ms)
11491 19:29:09.902540 [0:01:35.973367533] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11492 19:29:10.004381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass>
11493 19:29:10.005133 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass
11495 19:29:10.023925 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_89
11496 19:29:16.464214 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_89 (6575 ms)
11497 19:29:16.477386 [0:01:42.548531292] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11498 19:29:16.524186 [0:01:42.601159382] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11499 19:29:16.577246 [0:01:42.653711703] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11500 19:29:16.580721 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass
11502 19:29:16.583442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass>
11503 19:29:16.597818 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_1
11504 19:29:16.631256 [0:01:42.707570314] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11505 19:29:16.666844 Camera needs 4 requests, can't test only 1
11506 19:29:16.759782 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11507 19:29:16.849652
11508 19:29:16.949845 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_1 (52 ms)
11509 19:29:17.063802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip>
11510 19:29:17.064962 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip
11512 19:29:17.083215 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_2
11513 19:29:17.145990 Camera needs 4 requests, can't test only 2
11514 19:29:17.244153 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11515 19:29:17.339478
11516 19:29:17.441250 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_2 (52 ms)
11517 19:29:17.559002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip>
11518 19:29:17.559999 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip
11520 19:29:17.580152 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_3
11521 19:29:17.645816 Camera needs 4 requests, can't test only 3
11522 19:29:17.742332 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11523 19:29:17.841899
11524 19:29:17.947453 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_3 (53 ms)
11525 19:29:18.059726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip>
11526 19:29:18.060068 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip
11528 19:29:18.076562 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_5
11529 19:29:18.703837 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_5 (2080 ms)
11530 19:29:18.717199 [0:01:44.788508379] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11531 19:29:18.823238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass>
11532 19:29:18.824050 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass
11534 19:29:18.844368 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_8
11535 19:29:21.415817 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_8 (2712 ms)
11536 19:29:21.428480 [0:01:47.503189657] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11537 19:29:21.519932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass>
11538 19:29:21.520869 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass
11540 19:29:21.541106 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_13
11541 19:29:25.174443 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_13 (3758 ms)
11542 19:29:25.187625 [0:01:51.262075458] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11543 19:29:25.271315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass>
11544 19:29:25.271645 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass
11546 19:29:25.287491 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_21
11547 19:29:30.612529 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_21 (5438 ms)
11548 19:29:30.625687 [0:01:56.701217330] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11549 19:29:30.736738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass>
11550 19:29:30.737600 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass
11552 19:29:30.757428 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_34
11553 19:29:38.784058 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_34 (8169 ms)
11554 19:29:38.796910 [0:02:04.872358211] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11555 19:29:38.911206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass>
11556 19:29:38.912047 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass
11558 19:29:38.931452 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_55
11559 19:29:51.362295 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_55 (12575 ms)
11560 19:29:51.375502 [0:02:17.450611389] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11561 19:29:51.464793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass>
11562 19:29:51.465116 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass
11564 19:29:51.482034 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_89
11565 19:30:11.082234 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_89 (19717 ms)
11566 19:30:11.095482 [0:02:37.169823610] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11567 19:30:11.146721 [0:02:37.223848644] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11568 19:30:11.184479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass>
11569 19:30:11.184789 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass
11571 19:30:11.200618 [0:02:37.278046199] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11572 19:30:11.207356 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1
11573 19:30:11.254034 [0:02:37.331197403] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11574 19:30:11.257380 Camera needs 4 requests, can't test only 1
11575 19:30:11.335909 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11576 19:30:11.413575
11577 19:30:11.502994 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1 (54 ms)
11578 19:30:11.597213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip>
11579 19:30:11.597567 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip
11581 19:30:11.610363 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2
11582 19:30:11.664364 Camera needs 4 requests, can't test only 2
11583 19:30:11.749372 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11584 19:30:11.828357
11585 19:30:11.916870 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2 (54 ms)
11586 19:30:12.010189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip>
11587 19:30:12.010505 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip
11589 19:30:12.022388 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3
11590 19:30:12.078617 Camera needs 4 requests, can't test only 3
11591 19:30:12.157758 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11592 19:30:12.239807
11593 19:30:12.329705 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3 (53 ms)
11594 19:30:12.426692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip>
11595 19:30:12.426993 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip
11597 19:30:12.441398 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5
11598 19:30:13.324994 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5 (2075 ms)
11599 19:30:13.334483 [0:02:39.406883448] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11600 19:30:13.422308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass>
11601 19:30:13.422604 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass
11603 19:30:13.435581 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8
11604 19:30:16.033105 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8 (2708 ms)
11605 19:30:16.042715 [0:02:42.116453582] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11606 19:30:16.132388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass>
11607 19:30:16.132723 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass
11609 19:30:16.146405 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13
11610 19:30:19.791100 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13 (3758 ms)
11611 19:30:19.800848 [0:02:45.875079207] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11612 19:30:19.884288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass>
11613 19:30:19.884614 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass
11615 19:30:19.896622 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21
11616 19:30:25.229137 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21 (5438 ms)
11617 19:30:25.239247 [0:02:51.313106731] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11618 19:30:25.319820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass>
11619 19:30:25.320143 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass
11621 19:30:25.331442 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34
11622 19:30:33.400721 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34 (8171 ms)
11623 19:30:33.410295 [0:02:59.484404551] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11624 19:30:33.502234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass>
11625 19:30:33.502526 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass
11627 19:30:33.515363 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55
11628 19:30:45.978940 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55 (12579 ms)
11629 19:30:45.988708 [0:03:12.063848324] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11630 19:30:46.081829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass>
11631 19:30:46.082130 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass
11633 19:30:46.095223 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89
11634 19:31:05.698045 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89 (19718 ms)
11635 19:31:05.708029 [0:03:31.784564986] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11636 19:31:05.758059 [0:03:31.837920147] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11637 19:31:05.789474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass>
11638 19:31:05.789800 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass
11640 19:31:05.802575 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1
11641 19:31:05.815876 [0:03:31.893488891] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11642 19:31:05.867045 [0:03:31.946862744] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11643 19:31:05.870618 Camera needs 4 requests, can't test only 1
11644 19:31:05.947944 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11645 19:31:06.023428
11646 19:31:06.109825 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1 (53 ms)
11647 19:31:06.219993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip>
11648 19:31:06.220817 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip
11650 19:31:06.237963 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2
11651 19:31:06.309905 Camera needs 4 requests, can't test only 2
11652 19:31:06.408930 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11653 19:31:06.504592
11654 19:31:06.612708 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2 (55 ms)
11655 19:31:06.736177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip>
11656 19:31:06.736979 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip
11658 19:31:06.754788 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3
11659 19:31:06.826948 Camera needs 4 requests, can't test only 3
11660 19:31:06.930058 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11661 19:31:07.032413
11662 19:31:07.133241 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3 (53 ms)
11663 19:31:07.241486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip>
11664 19:31:07.242240 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip
11666 19:31:07.259390 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5
11667 19:31:07.942450 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5 (2079 ms)
11668 19:31:07.952186 [0:03:34.026613336] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11669 19:31:08.060867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass>
11670 19:31:08.061653 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass
11672 19:31:08.078554 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8
11673 19:31:10.650352 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8 (2708 ms)
11674 19:31:10.660285 [0:03:36.736331434] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11675 19:31:10.770167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass>
11676 19:31:10.770468 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass
11678 19:31:10.786550 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13
11679 19:31:14.408397 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13 (3758 ms)
11680 19:31:14.418017 [0:03:40.494856643] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11681 19:31:14.528307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass>
11682 19:31:14.529067 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass
11684 19:31:14.545842 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21
11685 19:31:19.846573 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21 (5439 ms)
11686 19:31:19.856663 [0:03:45.933949374] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11687 19:31:19.961916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass>
11688 19:31:19.962688 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass
11690 19:31:19.979384 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34
11691 19:31:28.018668 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34 (8172 ms)
11692 19:31:28.028484 [0:03:54.106525937] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11693 19:31:28.115714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass>
11694 19:31:28.116016 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass
11696 19:31:28.128958 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55
11697 19:31:40.596614 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55 (12577 ms)
11698 19:31:40.606764 [0:04:06.685773646] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11699 19:31:40.717971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass>
11700 19:31:40.718806 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass
11702 19:31:40.734827 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89
11703 19:32:00.316866 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89 (19716 ms)
11704 19:32:00.326536 [0:04:26.402818312] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11705 19:32:00.375087 [0:04:26.455499814] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11706 19:32:00.427775 [0:04:26.508700763] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11707 19:32:00.444704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass>
11708 19:32:00.445414 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass
11710 19:32:00.464223 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1
11711 19:32:00.481314 [0:04:26.561711592] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11712 19:32:00.535273 Camera needs 4 requests, can't test only 1
11713 19:32:00.636883 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11714 19:32:00.733717
11715 19:32:00.836306 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1 (53 ms)
11716 19:32:00.956784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip>
11717 19:32:00.957568 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip
11719 19:32:00.975842 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2
11720 19:32:01.044763 Camera needs 4 requests, can't test only 2
11721 19:32:01.145476 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11722 19:32:01.246165
11723 19:32:01.348714 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2 (53 ms)
11724 19:32:01.464440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip>
11725 19:32:01.465271 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip
11727 19:32:01.483376 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3
11728 19:32:01.554686 Camera needs 4 requests, can't test only 3
11729 19:32:01.659477 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11730 19:32:01.758997
11731 19:32:01.871782 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3 (52 ms)
11732 19:32:01.996317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip>
11733 19:32:01.997073 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip
11735 19:32:02.013479 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5
11736 19:32:02.553649 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5 (2077 ms)
11737 19:32:02.563519 [0:04:28.639470473] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11738 19:32:02.672179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass>
11739 19:32:02.672994 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass
11741 19:32:02.692252 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8
11742 19:32:05.262372 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8 (2708 ms)
11743 19:32:05.272487 [0:04:31.348099754] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11744 19:32:05.381082 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass
11746 19:32:05.384366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass>
11747 19:32:05.402489 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13
11748 19:32:09.020775 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13 (3758 ms)
11749 19:32:09.030399 [0:04:35.106712727] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11750 19:32:09.133476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass>
11751 19:32:09.134285 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass
11753 19:32:09.153205 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21
11754 19:32:14.459443 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21 (5438 ms)
11755 19:32:14.469029 [0:04:40.544253945] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11756 19:32:14.585660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass>
11757 19:32:14.586480 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass
11759 19:32:14.605672 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34
11760 19:32:22.629836 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34 (8169 ms)
11761 19:32:22.639519 [0:04:48.714857562] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11762 19:32:22.746190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass>
11763 19:32:22.746929 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass
11765 19:32:22.764760 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55
11766 19:32:35.208344 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55 (12578 ms)
11767 19:32:35.218605 [0:05:01.292669877] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11768 19:32:35.332087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass>
11769 19:32:35.332857 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass
11771 19:32:35.350783 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89
11772 19:32:54.927142 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89 (19718 ms)
11773 19:32:54.936503 [0:05:21.011712995] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11774 19:32:55.047629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass>
11775 19:32:55.048390 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass
11777 19:32:55.065872 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_1
11778 19:32:55.338782 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_1 (415 ms)
11779 19:32:55.352155 [0:05:21.426941746] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11780 19:32:55.465443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass>
11781 19:32:55.466303 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass
11783 19:32:55.487986 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_2
11784 19:32:55.826064 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_2 (486 ms)
11785 19:32:55.839135 [0:05:21.914379506] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11786 19:32:55.950025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass>
11787 19:32:55.950822 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass
11789 19:32:55.971798 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_3
11790 19:32:56.381071 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_3 (555 ms)
11791 19:32:56.393990 [0:05:22.468522632] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11792 19:32:56.501555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass>
11793 19:32:56.502338 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass
11795 19:32:56.521611 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_5
11796 19:32:57.074526 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_5 (693 ms)
11797 19:32:57.087655 [0:05:23.162587817] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11798 19:32:57.195977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass>
11799 19:32:57.196785 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass
11801 19:32:57.217241 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_8
11802 19:32:57.979248 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_8 (904 ms)
11803 19:32:57.992182 [0:05:24.067065927] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11804 19:32:58.097038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass>
11805 19:32:58.097816 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass
11807 19:32:58.118355 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_13
11808 19:32:59.235376 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_13 (1255 ms)
11809 19:32:59.248415 [0:05:25.322636794] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11810 19:32:59.353203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass>
11811 19:32:59.353497 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass
11813 19:32:59.372779 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_21
11814 19:33:01.049374 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_21 (1814 ms)
11815 19:33:01.062285 [0:05:27.136902637] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11816 19:33:01.180807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass>
11817 19:33:01.181645 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass
11819 19:33:01.200213 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_34
11820 19:33:03.773864 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_34 (2724 ms)
11821 19:33:03.786551 [0:05:29.861518765] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11822 19:33:03.893175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass>
11823 19:33:03.894042 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass
11825 19:33:03.915598 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_55
11826 19:33:07.968266 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_55 (4194 ms)
11827 19:33:07.981750 [0:05:34.056175984] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11828 19:33:08.082815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass>
11829 19:33:08.083567 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass
11831 19:33:08.103184 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_89
11832 19:33:14.543245 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_89 (6575 ms)
11833 19:33:14.556818 [0:05:40.631438674] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11834 19:33:14.664054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass>
11835 19:33:14.664860 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass
11837 19:33:14.684534 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1
11838 19:33:14.960967 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1 (413 ms)
11839 19:33:14.970793 [0:05:41.045467647] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11840 19:33:15.080250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass>
11841 19:33:15.080992 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass
11843 19:33:15.097555 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2
11844 19:33:15.445656 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2 (485 ms)
11845 19:33:15.455369 [0:05:41.530462651] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11846 19:33:15.538496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass>
11847 19:33:15.538800 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass
11849 19:33:15.552859 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3
11850 19:33:16.000092 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3 (553 ms)
11851 19:33:16.009647 [0:05:42.084475680] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11852 19:33:16.121332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass>
11853 19:33:16.122304 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass
11855 19:33:16.140366 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5
11856 19:33:16.694638 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5 (694 ms)
11857 19:33:16.703958 [0:05:42.778858265] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11858 19:33:16.817046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass>
11859 19:33:16.818031 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass
11861 19:33:16.835771 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8
11862 19:33:17.601277 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8 (906 ms)
11863 19:33:17.611338 [0:05:43.686097920] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11864 19:33:17.723295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass>
11865 19:33:17.724266 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass
11867 19:33:17.741917 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13
11868 19:33:18.855995 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13 (1254 ms)
11869 19:33:18.865905 [0:05:44.940577869] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11870 19:33:18.975940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass>
11871 19:33:18.976719 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass
11873 19:33:18.994813 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21
11874 19:33:20.669406 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21 (1813 ms)
11875 19:33:20.679380 [0:05:46.754777385] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11876 19:33:20.766049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass>
11877 19:33:20.766353 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass
11879 19:33:20.779870 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34
11880 19:33:23.396381 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34 (2726 ms)
11881 19:33:23.406010 [0:05:49.480994637] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11882 19:33:23.514264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass>
11883 19:33:23.515024 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass
11885 19:33:23.529887 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55
11886 19:33:27.591164 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55 (4194 ms)
11887 19:33:27.601380 [0:05:53.675850097] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11888 19:33:27.712335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass>
11889 19:33:27.713174 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass
11891 19:33:27.731983 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89
11892 19:33:34.166190 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89 (6574 ms)
11893 19:33:34.175788 [0:06:00.251074476] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11894 19:33:34.281000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass>
11895 19:33:34.281866 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass
11897 19:33:34.298780 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1
11898 19:33:34.580776 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1 (414 ms)
11899 19:33:34.590467 [0:06:00.666015337] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11900 19:33:34.696458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass>
11901 19:33:34.697294 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass
11903 19:33:34.716283 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2
11904 19:33:35.065908 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2 (485 ms)
11905 19:33:35.075980 [0:06:01.151034637] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11906 19:33:35.184268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass>
11907 19:33:35.185073 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass
11909 19:33:35.201710 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3
11910 19:33:35.620913 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3 (554 ms)
11911 19:33:35.630858 [0:06:01.706049723] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11912 19:33:35.741333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass>
11913 19:33:35.742228 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass
11915 19:33:35.760991 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5
11916 19:33:36.315353 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5 (694 ms)
11917 19:33:36.324921 [0:06:02.400172680] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11918 19:33:36.434604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass>
11919 19:33:36.435362 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass
11921 19:33:36.452049 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8
11922 19:33:37.221276 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8 (906 ms)
11923 19:33:37.231199 [0:06:03.306438150] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11924 19:33:37.339990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass>
11925 19:33:37.340800 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass
11927 19:33:37.358781 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13
11928 19:33:38.475406 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13 (1253 ms)
11929 19:33:38.484890 [0:06:04.560372060] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11930 19:33:38.587633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass>
11931 19:33:38.588471 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass
11933 19:33:38.606099 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21
11934 19:33:40.289589 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21 (1814 ms)
11935 19:33:40.299811 [0:06:06.374848397] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11936 19:33:40.408162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass>
11937 19:33:40.408942 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass
11939 19:33:40.428289 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34
11940 19:33:43.014450 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34 (2724 ms)
11941 19:33:43.024133 [0:06:09.099583939] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11942 19:33:43.131453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass>
11943 19:33:43.132212 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass
11945 19:33:43.149679 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55
11946 19:33:47.208704 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55 (4194 ms)
11947 19:33:47.218509 [0:06:13.294570669] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11948 19:33:47.318774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass>
11949 19:33:47.319798 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass
11951 19:33:47.335097 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89
11952 19:33:53.784041 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89 (6575 ms)
11953 19:33:53.793608 [0:06:19.869829890] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11954 19:33:53.900152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass>
11955 19:33:53.900473 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass
11957 19:33:53.916811 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1
11958 19:33:54.198214 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1 (414 ms)
11959 19:33:54.207871 [0:06:20.283711675] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11960 19:33:54.313025 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass
11962 19:33:54.316018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass>
11963 19:33:54.333298 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2
11964 19:33:54.682822 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2 (484 ms)
11965 19:33:54.692919 [0:06:20.768638696] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11966 19:33:54.794914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass>
11967 19:33:54.795706 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass
11969 19:33:54.815941 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3
11970 19:33:55.237158 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3 (554 ms)
11971 19:33:55.247081 [0:06:21.322827551] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11972 19:33:55.351931 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass
11974 19:33:55.354468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass>
11975 19:33:55.373777 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5
11976 19:33:55.931388 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5 (693 ms)
11977 19:33:55.941173 [0:06:22.017015041] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11978 19:33:56.050373 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass
11980 19:33:56.052830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass>
11981 19:33:56.071881 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8
11982 19:33:56.836381 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8 (904 ms)
11983 19:33:56.846111 [0:06:22.922181127] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11984 19:33:56.953443 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass
11986 19:33:56.956519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass>
11987 19:33:56.976338 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13
11988 19:33:58.090637 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13 (1254 ms)
11989 19:33:58.100717 [0:06:24.177295725] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11990 19:33:58.205338 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass
11992 19:33:58.208526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass>
11993 19:33:58.225700 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21
11994 19:33:59.905277 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21 (1814 ms)
11995 19:33:59.914852 [0:06:25.992093962] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
11996 19:34:00.023122 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass
11998 19:34:00.026006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass>
11999 19:34:00.045909 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34
12000 19:34:02.631223 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34 (2725 ms)
12001 19:34:02.640991 [0:06:28.717934728] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
12002 19:34:02.760619 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass
12004 19:34:02.763281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass>
12005 19:34:02.782183 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55
12006 19:34:06.826038 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55 (4195 ms)
12007 19:34:06.835851 [0:06:32.913140911] [410] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
12008 19:34:06.943029 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass
12010 19:34:06.946302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass>
12011 19:34:06.965224 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89
12012 19:34:13.400671 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89 (6575 ms)
12013 19:34:13.504335 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass
12015 19:34:13.507335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass>
12016 19:34:13.523246 [----------] 120 tests from CaptureTests/SingleStream (369828 ms total)
12017 19:34:13.596255
12018 19:34:13.679552 [----------] Global test environment tear-down
12019 19:34:13.765830 [==========] 120 tests from 1 test suite ran. (369828 ms total)
12020 19:34:13.858359 <LAVA_SIGNAL_TESTSET STOP>
12021 19:34:13.858665 Received signal: <TESTSET> STOP
12022 19:34:13.858751 Closing test_set CaptureTests/SingleStream
12023 19:34:13.861825 + set +x
12024 19:34:13.865068 <LAVA_SIGNAL_ENDRUN 0_lc-compliance 13420400_1.6.2.3.1>
12025 19:34:13.865327 Received signal: <ENDRUN> 0_lc-compliance 13420400_1.6.2.3.1
12026 19:34:13.865411 Ending use of test pattern.
12027 19:34:13.865477 Ending test lava.0_lc-compliance (13420400_1.6.2.3.1), duration 371.86
12029 19:34:13.868517 <LAVA_TEST_RUNNER EXIT>
12030 19:34:13.869304 ok: lava_test_shell seems to have completed
12031 19:34:13.875544 Capture/Raw_1:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_13:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_2:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_21:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_3:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_34:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_5:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_55:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_8:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_89:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
12032 19:34:13.875719 end: 3.1 lava-test-shell (duration 00:06:13) [common]
12033 19:34:13.875804 end: 3 lava-test-retry (duration 00:06:13) [common]
12034 19:34:13.875887 start: 4 finalize (timeout 00:10:00) [common]
12035 19:34:13.875971 start: 4.1 power-off (timeout 00:00:30) [common]
12036 19:34:13.876116 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
12037 19:34:13.952140 >> Command sent successfully.
12038 19:34:13.957381 Returned 0 in 0 seconds
12039 19:34:14.058630 end: 4.1 power-off (duration 00:00:00) [common]
12041 19:34:14.060174 start: 4.2 read-feedback (timeout 00:10:00) [common]
12042 19:34:14.061768 Listened to connection for namespace 'common' for up to 1s
12043 19:34:15.061621 Finalising connection for namespace 'common'
12044 19:34:15.061816 Disconnecting from shell: Finalise
12045 19:34:15.061904 / #
12046 19:34:15.162589 end: 4.2 read-feedback (duration 00:00:01) [common]
12047 19:34:15.163344 end: 4 finalize (duration 00:00:01) [common]
12048 19:34:15.163991 Cleaning after the job
12049 19:34:15.164529 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13420400/tftp-deploy-flapplqt/ramdisk
12050 19:34:15.174669 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13420400/tftp-deploy-flapplqt/kernel
12051 19:34:15.208656 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13420400/tftp-deploy-flapplqt/dtb
12052 19:34:15.208983 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13420400/tftp-deploy-flapplqt/nfsrootfs
12053 19:34:15.254466 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13420400/tftp-deploy-flapplqt/modules
12054 19:34:15.259975 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/13420400
12055 19:34:15.513196 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/13420400
12056 19:34:15.513383 Job finished correctly