Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 26
- Errors: 1
- Kernel Errors: 33
- Boot result: PASS
1 19:25:51.021823 lava-dispatcher, installed at version: 2024.01
2 19:25:51.022082 start: 0 validate
3 19:25:51.022251 Start time: 2024-04-18 19:25:51.022243+00:00 (UTC)
4 19:25:51.022424 Using caching service: 'http://localhost/cache/?uri=%s'
5 19:25:51.022592 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-v4l2%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 19:25:51.282973 Using caching service: 'http://localhost/cache/?uri=%s'
7 19:25:51.283205 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 19:25:51.540432 Using caching service: 'http://localhost/cache/?uri=%s'
9 19:25:51.540656 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 19:25:51.798261 Using caching service: 'http://localhost/cache/?uri=%s'
11 19:25:51.798497 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 19:25:52.058147 validate duration: 1.04
14 19:25:52.058536 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 19:25:52.058674 start: 1.1 download-retry (timeout 00:10:00) [common]
16 19:25:52.058797 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 19:25:52.058955 Not decompressing ramdisk as can be used compressed.
18 19:25:52.059079 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-v4l2/20240313.0/arm64/rootfs.cpio.gz
19 19:25:52.059173 saving as /var/lib/lava/dispatcher/tmp/13420397/tftp-deploy-49036zue/ramdisk/rootfs.cpio.gz
20 19:25:52.059268 total size: 28105535 (26 MB)
21 19:25:52.060837 progress 0 % (0 MB)
22 19:25:52.068672 progress 5 % (1 MB)
23 19:25:52.076536 progress 10 % (2 MB)
24 19:25:52.084406 progress 15 % (4 MB)
25 19:25:52.092407 progress 20 % (5 MB)
26 19:25:52.100343 progress 25 % (6 MB)
27 19:25:52.108467 progress 30 % (8 MB)
28 19:25:52.116369 progress 35 % (9 MB)
29 19:25:52.124262 progress 40 % (10 MB)
30 19:25:52.131938 progress 45 % (12 MB)
31 19:25:52.139808 progress 50 % (13 MB)
32 19:25:52.147939 progress 55 % (14 MB)
33 19:25:52.156118 progress 60 % (16 MB)
34 19:25:52.164256 progress 65 % (17 MB)
35 19:25:52.172190 progress 70 % (18 MB)
36 19:25:52.180061 progress 75 % (20 MB)
37 19:25:52.188107 progress 80 % (21 MB)
38 19:25:52.196050 progress 85 % (22 MB)
39 19:25:52.203887 progress 90 % (24 MB)
40 19:25:52.211890 progress 95 % (25 MB)
41 19:25:52.219918 progress 100 % (26 MB)
42 19:25:52.220242 26 MB downloaded in 0.16 s (166.51 MB/s)
43 19:25:52.220480 end: 1.1.1 http-download (duration 00:00:00) [common]
45 19:25:52.220880 end: 1.1 download-retry (duration 00:00:00) [common]
46 19:25:52.221011 start: 1.2 download-retry (timeout 00:10:00) [common]
47 19:25:52.221132 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 19:25:52.221375 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 19:25:52.221474 saving as /var/lib/lava/dispatcher/tmp/13420397/tftp-deploy-49036zue/kernel/Image
50 19:25:52.221542 total size: 54286848 (51 MB)
51 19:25:52.221605 No compression specified
52 19:25:52.222742 progress 0 % (0 MB)
53 19:25:52.236974 progress 5 % (2 MB)
54 19:25:52.251248 progress 10 % (5 MB)
55 19:25:52.265513 progress 15 % (7 MB)
56 19:25:52.279734 progress 20 % (10 MB)
57 19:25:52.294214 progress 25 % (12 MB)
58 19:25:52.309776 progress 30 % (15 MB)
59 19:25:52.325226 progress 35 % (18 MB)
60 19:25:52.340784 progress 40 % (20 MB)
61 19:25:52.356192 progress 45 % (23 MB)
62 19:25:52.371722 progress 50 % (25 MB)
63 19:25:52.387062 progress 55 % (28 MB)
64 19:25:52.401217 progress 60 % (31 MB)
65 19:25:52.415204 progress 65 % (33 MB)
66 19:25:52.429247 progress 70 % (36 MB)
67 19:25:52.443292 progress 75 % (38 MB)
68 19:25:52.457672 progress 80 % (41 MB)
69 19:25:52.472087 progress 85 % (44 MB)
70 19:25:52.486382 progress 90 % (46 MB)
71 19:25:52.500077 progress 95 % (49 MB)
72 19:25:52.514034 progress 100 % (51 MB)
73 19:25:52.514307 51 MB downloaded in 0.29 s (176.84 MB/s)
74 19:25:52.514467 end: 1.2.1 http-download (duration 00:00:00) [common]
76 19:25:52.514697 end: 1.2 download-retry (duration 00:00:00) [common]
77 19:25:52.514783 start: 1.3 download-retry (timeout 00:10:00) [common]
78 19:25:52.514869 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 19:25:52.515015 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 19:25:52.515085 saving as /var/lib/lava/dispatcher/tmp/13420397/tftp-deploy-49036zue/dtb/mt8192-asurada-spherion-r0.dtb
81 19:25:52.515148 total size: 47230 (0 MB)
82 19:25:52.515211 No compression specified
83 19:25:52.516539 progress 69 % (0 MB)
84 19:25:52.516816 progress 100 % (0 MB)
85 19:25:52.516972 0 MB downloaded in 0.00 s (24.73 MB/s)
86 19:25:52.517098 end: 1.3.1 http-download (duration 00:00:00) [common]
88 19:25:52.517336 end: 1.3 download-retry (duration 00:00:00) [common]
89 19:25:52.517420 start: 1.4 download-retry (timeout 00:10:00) [common]
90 19:25:52.517504 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 19:25:52.517618 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 19:25:52.517685 saving as /var/lib/lava/dispatcher/tmp/13420397/tftp-deploy-49036zue/modules/modules.tar
93 19:25:52.517745 total size: 8631416 (8 MB)
94 19:25:52.517806 Using unxz to decompress xz
95 19:25:52.521995 progress 0 % (0 MB)
96 19:25:52.542117 progress 5 % (0 MB)
97 19:25:52.567205 progress 10 % (0 MB)
98 19:25:52.591830 progress 15 % (1 MB)
99 19:25:52.615888 progress 20 % (1 MB)
100 19:25:52.641538 progress 25 % (2 MB)
101 19:25:52.667888 progress 30 % (2 MB)
102 19:25:52.692421 progress 35 % (2 MB)
103 19:25:52.718184 progress 40 % (3 MB)
104 19:25:52.742752 progress 45 % (3 MB)
105 19:25:52.768576 progress 50 % (4 MB)
106 19:25:52.794548 progress 55 % (4 MB)
107 19:25:52.823171 progress 60 % (4 MB)
108 19:25:52.849438 progress 65 % (5 MB)
109 19:25:52.875792 progress 70 % (5 MB)
110 19:25:52.901032 progress 75 % (6 MB)
111 19:25:52.927140 progress 80 % (6 MB)
112 19:25:52.953555 progress 85 % (7 MB)
113 19:25:52.983046 progress 90 % (7 MB)
114 19:25:53.012355 progress 95 % (7 MB)
115 19:25:53.039159 progress 100 % (8 MB)
116 19:25:53.044878 8 MB downloaded in 0.53 s (15.62 MB/s)
117 19:25:53.045276 end: 1.4.1 http-download (duration 00:00:01) [common]
119 19:25:53.045572 end: 1.4 download-retry (duration 00:00:01) [common]
120 19:25:53.045684 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 19:25:53.045781 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 19:25:53.045877 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 19:25:53.045972 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 19:25:53.046213 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/13420397/lava-overlay-jeylrbne
125 19:25:53.046368 makedir: /var/lib/lava/dispatcher/tmp/13420397/lava-overlay-jeylrbne/lava-13420397/bin
126 19:25:53.046475 makedir: /var/lib/lava/dispatcher/tmp/13420397/lava-overlay-jeylrbne/lava-13420397/tests
127 19:25:53.046580 makedir: /var/lib/lava/dispatcher/tmp/13420397/lava-overlay-jeylrbne/lava-13420397/results
128 19:25:53.046703 Creating /var/lib/lava/dispatcher/tmp/13420397/lava-overlay-jeylrbne/lava-13420397/bin/lava-add-keys
129 19:25:53.046864 Creating /var/lib/lava/dispatcher/tmp/13420397/lava-overlay-jeylrbne/lava-13420397/bin/lava-add-sources
130 19:25:53.046995 Creating /var/lib/lava/dispatcher/tmp/13420397/lava-overlay-jeylrbne/lava-13420397/bin/lava-background-process-start
131 19:25:53.047141 Creating /var/lib/lava/dispatcher/tmp/13420397/lava-overlay-jeylrbne/lava-13420397/bin/lava-background-process-stop
132 19:25:53.047266 Creating /var/lib/lava/dispatcher/tmp/13420397/lava-overlay-jeylrbne/lava-13420397/bin/lava-common-functions
133 19:25:53.047433 Creating /var/lib/lava/dispatcher/tmp/13420397/lava-overlay-jeylrbne/lava-13420397/bin/lava-echo-ipv4
134 19:25:53.047602 Creating /var/lib/lava/dispatcher/tmp/13420397/lava-overlay-jeylrbne/lava-13420397/bin/lava-install-packages
135 19:25:53.047758 Creating /var/lib/lava/dispatcher/tmp/13420397/lava-overlay-jeylrbne/lava-13420397/bin/lava-installed-packages
136 19:25:53.047940 Creating /var/lib/lava/dispatcher/tmp/13420397/lava-overlay-jeylrbne/lava-13420397/bin/lava-os-build
137 19:25:53.048110 Creating /var/lib/lava/dispatcher/tmp/13420397/lava-overlay-jeylrbne/lava-13420397/bin/lava-probe-channel
138 19:25:53.048266 Creating /var/lib/lava/dispatcher/tmp/13420397/lava-overlay-jeylrbne/lava-13420397/bin/lava-probe-ip
139 19:25:53.048436 Creating /var/lib/lava/dispatcher/tmp/13420397/lava-overlay-jeylrbne/lava-13420397/bin/lava-target-ip
140 19:25:53.048613 Creating /var/lib/lava/dispatcher/tmp/13420397/lava-overlay-jeylrbne/lava-13420397/bin/lava-target-mac
141 19:25:53.048770 Creating /var/lib/lava/dispatcher/tmp/13420397/lava-overlay-jeylrbne/lava-13420397/bin/lava-target-storage
142 19:25:53.048943 Creating /var/lib/lava/dispatcher/tmp/13420397/lava-overlay-jeylrbne/lava-13420397/bin/lava-test-case
143 19:25:53.049119 Creating /var/lib/lava/dispatcher/tmp/13420397/lava-overlay-jeylrbne/lava-13420397/bin/lava-test-event
144 19:25:53.049322 Creating /var/lib/lava/dispatcher/tmp/13420397/lava-overlay-jeylrbne/lava-13420397/bin/lava-test-feedback
145 19:25:53.049447 Creating /var/lib/lava/dispatcher/tmp/13420397/lava-overlay-jeylrbne/lava-13420397/bin/lava-test-raise
146 19:25:53.049591 Creating /var/lib/lava/dispatcher/tmp/13420397/lava-overlay-jeylrbne/lava-13420397/bin/lava-test-reference
147 19:25:53.049746 Creating /var/lib/lava/dispatcher/tmp/13420397/lava-overlay-jeylrbne/lava-13420397/bin/lava-test-runner
148 19:25:53.049917 Creating /var/lib/lava/dispatcher/tmp/13420397/lava-overlay-jeylrbne/lava-13420397/bin/lava-test-set
149 19:25:53.050062 Creating /var/lib/lava/dispatcher/tmp/13420397/lava-overlay-jeylrbne/lava-13420397/bin/lava-test-shell
150 19:25:53.050190 Updating /var/lib/lava/dispatcher/tmp/13420397/lava-overlay-jeylrbne/lava-13420397/bin/lava-install-packages (oe)
151 19:25:53.050353 Updating /var/lib/lava/dispatcher/tmp/13420397/lava-overlay-jeylrbne/lava-13420397/bin/lava-installed-packages (oe)
152 19:25:53.050482 Creating /var/lib/lava/dispatcher/tmp/13420397/lava-overlay-jeylrbne/lava-13420397/environment
153 19:25:53.050607 LAVA metadata
154 19:25:53.050683 - LAVA_JOB_ID=13420397
155 19:25:53.050746 - LAVA_DISPATCHER_IP=192.168.201.1
156 19:25:53.050881 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 19:25:53.050949 skipped lava-vland-overlay
158 19:25:53.051033 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 19:25:53.051121 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 19:25:53.051183 skipped lava-multinode-overlay
161 19:25:53.051257 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 19:25:53.051387 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 19:25:53.051469 Loading test definitions
164 19:25:53.051579 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 19:25:53.051655 Using /lava-13420397 at stage 0
166 19:25:53.051984 uuid=13420397_1.5.2.3.1 testdef=None
167 19:25:53.052096 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 19:25:53.052180 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 19:25:53.052883 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 19:25:53.053336 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 19:25:53.054325 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 19:25:53.054744 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 19:25:53.055763 runner path: /var/lib/lava/dispatcher/tmp/13420397/lava-overlay-jeylrbne/lava-13420397/0/tests/0_v4l2-compliance-mtk-vcodec-enc test_uuid 13420397_1.5.2.3.1
176 19:25:53.055993 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 19:25:53.056362 Creating lava-test-runner.conf files
179 19:25:53.056461 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/13420397/lava-overlay-jeylrbne/lava-13420397/0 for stage 0
180 19:25:53.056621 - 0_v4l2-compliance-mtk-vcodec-enc
181 19:25:53.056775 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 19:25:53.056907 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 19:25:53.067909 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 19:25:53.068133 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 19:25:53.068264 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 19:25:53.068424 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 19:25:53.068589 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 19:25:53.977525 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 19:25:53.978021 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 19:25:53.978219 extracting modules file /var/lib/lava/dispatcher/tmp/13420397/tftp-deploy-49036zue/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13420397/extract-overlay-ramdisk-xqw343x0/ramdisk
191 19:25:54.214413 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 19:25:54.214601 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 19:25:54.214714 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13420397/compress-overlay-r38vyo6n/overlay-1.5.2.4.tar.gz to ramdisk
194 19:25:54.214798 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13420397/compress-overlay-r38vyo6n/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/13420397/extract-overlay-ramdisk-xqw343x0/ramdisk
195 19:25:54.221542 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 19:25:54.221700 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 19:25:54.221811 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 19:25:54.221921 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 19:25:54.222015 Building ramdisk /var/lib/lava/dispatcher/tmp/13420397/extract-overlay-ramdisk-xqw343x0/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/13420397/extract-overlay-ramdisk-xqw343x0/ramdisk
200 19:25:54.927264 >> 276171 blocks
201 19:25:59.138709 rename /var/lib/lava/dispatcher/tmp/13420397/extract-overlay-ramdisk-xqw343x0/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/13420397/tftp-deploy-49036zue/ramdisk/ramdisk.cpio.gz
202 19:25:59.139189 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 19:25:59.139360 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 19:25:59.139494 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 19:25:59.139641 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/13420397/tftp-deploy-49036zue/kernel/Image'
206 19:26:13.013925 Returned 0 in 13 seconds
207 19:26:13.114520 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/13420397/tftp-deploy-49036zue/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/13420397/tftp-deploy-49036zue/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/13420397/tftp-deploy-49036zue/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/13420397/tftp-deploy-49036zue/kernel/image.itb
208 19:26:13.756294 output: FIT description: Kernel Image image with one or more FDT blobs
209 19:26:13.756712 output: Created: Thu Apr 18 20:26:13 2024
210 19:26:13.756820 output: Image 0 (kernel-1)
211 19:26:13.756921 output: Description:
212 19:26:13.757013 output: Created: Thu Apr 18 20:26:13 2024
213 19:26:13.757101 output: Type: Kernel Image
214 19:26:13.757192 output: Compression: lzma compressed
215 19:26:13.757268 output: Data Size: 12910355 Bytes = 12607.77 KiB = 12.31 MiB
216 19:26:13.757334 output: Architecture: AArch64
217 19:26:13.757399 output: OS: Linux
218 19:26:13.757457 output: Load Address: 0x00000000
219 19:26:13.757516 output: Entry Point: 0x00000000
220 19:26:13.757606 output: Hash algo: crc32
221 19:26:13.757695 output: Hash value: bbac8b0b
222 19:26:13.757782 output: Image 1 (fdt-1)
223 19:26:13.757872 output: Description: mt8192-asurada-spherion-r0
224 19:26:13.757959 output: Created: Thu Apr 18 20:26:13 2024
225 19:26:13.758041 output: Type: Flat Device Tree
226 19:26:13.758130 output: Compression: uncompressed
227 19:26:13.758213 output: Data Size: 47230 Bytes = 46.12 KiB = 0.05 MiB
228 19:26:13.758297 output: Architecture: AArch64
229 19:26:13.758384 output: Hash algo: crc32
230 19:26:13.758466 output: Hash value: 4bf0d1ac
231 19:26:13.758550 output: Image 2 (ramdisk-1)
232 19:26:13.758635 output: Description: unavailable
233 19:26:13.758720 output: Created: Thu Apr 18 20:26:13 2024
234 19:26:13.758806 output: Type: RAMDisk Image
235 19:26:13.758889 output: Compression: Unknown Compression
236 19:26:13.758977 output: Data Size: 41252845 Bytes = 40285.98 KiB = 39.34 MiB
237 19:26:13.759062 output: Architecture: AArch64
238 19:26:13.759148 output: OS: Linux
239 19:26:13.759231 output: Load Address: unavailable
240 19:26:13.759316 output: Entry Point: unavailable
241 19:26:13.759398 output: Hash algo: crc32
242 19:26:13.759487 output: Hash value: 9fc19d3b
243 19:26:13.759576 output: Default Configuration: 'conf-1'
244 19:26:13.759658 output: Configuration 0 (conf-1)
245 19:26:13.759745 output: Description: mt8192-asurada-spherion-r0
246 19:26:13.759828 output: Kernel: kernel-1
247 19:26:13.759912 output: Init Ramdisk: ramdisk-1
248 19:26:13.759996 output: FDT: fdt-1
249 19:26:13.760080 output: Loadables: kernel-1
250 19:26:13.760175 output:
251 19:26:13.760409 end: 1.5.8.1 prepare-fit (duration 00:00:15) [common]
252 19:26:13.760545 end: 1.5.8 prepare-kernel (duration 00:00:15) [common]
253 19:26:13.760680 end: 1.5 prepare-tftp-overlay (duration 00:00:21) [common]
254 19:26:13.760828 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:38) [common]
255 19:26:13.760939 No LXC device requested
256 19:26:13.761055 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 19:26:13.761176 start: 1.7 deploy-device-env (timeout 00:09:38) [common]
258 19:26:13.761300 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 19:26:13.761398 Checking files for TFTP limit of 4294967296 bytes.
260 19:26:13.762073 end: 1 tftp-deploy (duration 00:00:22) [common]
261 19:26:13.762209 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 19:26:13.762345 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 19:26:13.762522 substitutions:
264 19:26:13.762620 - {DTB}: 13420397/tftp-deploy-49036zue/dtb/mt8192-asurada-spherion-r0.dtb
265 19:26:13.762719 - {INITRD}: 13420397/tftp-deploy-49036zue/ramdisk/ramdisk.cpio.gz
266 19:26:13.762809 - {KERNEL}: 13420397/tftp-deploy-49036zue/kernel/Image
267 19:26:13.762897 - {LAVA_MAC}: None
268 19:26:13.762986 - {PRESEED_CONFIG}: None
269 19:26:13.763071 - {PRESEED_LOCAL}: None
270 19:26:13.763162 - {RAMDISK}: 13420397/tftp-deploy-49036zue/ramdisk/ramdisk.cpio.gz
271 19:26:13.763247 - {ROOT_PART}: None
272 19:26:13.763334 - {ROOT}: None
273 19:26:13.763435 - {SERVER_IP}: 192.168.201.1
274 19:26:13.763520 - {TEE}: None
275 19:26:13.763611 Parsed boot commands:
276 19:26:13.763696 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 19:26:13.763923 Parsed boot commands: tftpboot 192.168.201.1 13420397/tftp-deploy-49036zue/kernel/image.itb 13420397/tftp-deploy-49036zue/kernel/cmdline
278 19:26:13.764043 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 19:26:13.764166 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 19:26:13.764294 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 19:26:13.764417 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 19:26:13.764525 Not connected, no need to disconnect.
283 19:26:13.764638 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 19:26:13.764758 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 19:26:13.764858 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
286 19:26:13.768796 Setting prompt string to ['lava-test: # ']
287 19:26:13.769191 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 19:26:13.769342 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 19:26:13.769479 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 19:26:13.769601 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 19:26:13.769944 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=reboot'
292 19:26:18.918717 >> Command sent successfully.
293 19:26:18.932030 Returned 0 in 5 seconds
294 19:26:19.033279 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 19:26:19.035187 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 19:26:19.035747 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 19:26:19.036164 Setting prompt string to 'Starting depthcharge on Spherion...'
299 19:26:19.036499 Changing prompt to 'Starting depthcharge on Spherion...'
300 19:26:19.036843 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 19:26:19.038094 [Enter `^Ec?' for help]
302 19:26:19.200079
303 19:26:19.200613
304 19:26:19.200963 F0: 102B 0000
305 19:26:19.201343
306 19:26:19.201668 F3: 1001 0000 [0200]
307 19:26:19.201966
308 19:26:19.203463 F3: 1001 0000
309 19:26:19.203885
310 19:26:19.204214 F7: 102D 0000
311 19:26:19.204522
312 19:26:19.207000 F1: 0000 0000
313 19:26:19.207421
314 19:26:19.207761 V0: 0000 0000 [0001]
315 19:26:19.208078
316 19:26:19.210153 00: 0007 8000
317 19:26:19.210591
318 19:26:19.210924 01: 0000 0000
319 19:26:19.211243
320 19:26:19.211544 BP: 0C00 0209 [0000]
321 19:26:19.213279
322 19:26:19.213704 G0: 1182 0000
323 19:26:19.214039
324 19:26:19.214431 EC: 0000 0021 [4000]
325 19:26:19.217791
326 19:26:19.218210 S7: 0000 0000 [0000]
327 19:26:19.218545
328 19:26:19.218852 CC: 0000 0000 [0001]
329 19:26:19.220653
330 19:26:19.221070 T0: 0000 0040 [010F]
331 19:26:19.221472
332 19:26:19.221787 Jump to BL
333 19:26:19.222085
334 19:26:19.246893
335 19:26:19.247438
336 19:26:19.247979
337 19:26:19.254191 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 19:26:19.257705 ARM64: Exception handlers installed.
339 19:26:19.261913 ARM64: Testing exception
340 19:26:19.264908 ARM64: Done test exception
341 19:26:19.271817 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 19:26:19.282243 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 19:26:19.288424 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 19:26:19.299108 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 19:26:19.305240 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 19:26:19.312161 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 19:26:19.323632 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 19:26:19.330058 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 19:26:19.349710 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 19:26:19.352677 WDT: Last reset was cold boot
351 19:26:19.356256 SPI1(PAD0) initialized at 2873684 Hz
352 19:26:19.359316 SPI5(PAD0) initialized at 992727 Hz
353 19:26:19.363051 VBOOT: Loading verstage.
354 19:26:19.369464 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 19:26:19.372811 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 19:26:19.376335 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 19:26:19.379979 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 19:26:19.386669 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 19:26:19.393201 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 19:26:19.404429 read SPI 0x96554 0xa1eb: 4595 us, 9020 KB/s, 72.160 Mbps
361 19:26:19.404540
362 19:26:19.404635
363 19:26:19.414441 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 19:26:19.417682 ARM64: Exception handlers installed.
365 19:26:19.421204 ARM64: Testing exception
366 19:26:19.421287 ARM64: Done test exception
367 19:26:19.427966 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 19:26:19.431224 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 19:26:19.446743 Probing TPM: . done!
370 19:26:19.446855 TPM ready after 0 ms
371 19:26:19.454263 Connected to device vid:did:rid of 1ae0:0028:00
372 19:26:19.460853 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 19:26:19.517688 Initialized TPM device CR50 revision 0
374 19:26:19.529653 tlcl_send_startup: Startup return code is 0
375 19:26:19.529818 TPM: setup succeeded
376 19:26:19.541405 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 19:26:19.550106 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 19:26:19.562581 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 19:26:19.571949 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 19:26:19.574989 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 19:26:19.580445 in-header: 03 07 00 00 08 00 00 00
382 19:26:19.585071 in-data: aa e4 47 04 13 02 00 00
383 19:26:19.588338 Chrome EC: UHEPI supported
384 19:26:19.595689 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 19:26:19.599084 in-header: 03 ad 00 00 08 00 00 00
386 19:26:19.603106 in-data: 00 20 20 08 00 00 00 00
387 19:26:19.603189 Phase 1
388 19:26:19.606473 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 19:26:19.610518 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 19:26:19.617735 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 19:26:19.622129 Recovery requested (1009000e)
392 19:26:19.628943 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 19:26:19.634957 tlcl_extend: response is 0
394 19:26:19.644208 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 19:26:19.649797 tlcl_extend: response is 0
396 19:26:19.656648 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 19:26:19.676343 read SPI 0x210d4 0x2173b: 15149 us, 9044 KB/s, 72.352 Mbps
398 19:26:19.683161 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 19:26:19.683296
400 19:26:19.683396
401 19:26:19.693921 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 19:26:19.696918 ARM64: Exception handlers installed.
403 19:26:19.697040 ARM64: Testing exception
404 19:26:19.700672 ARM64: Done test exception
405 19:26:19.721799 pmic_efuse_setting: Set efuses in 11 msecs
406 19:26:19.724811 pmwrap_interface_init: Select PMIF_VLD_RDY
407 19:26:19.732339 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 19:26:19.736074 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 19:26:19.739661 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 19:26:19.746464 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 19:26:19.749822 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 19:26:19.753679 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 19:26:19.761161 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 19:26:19.765049 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 19:26:19.768311 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 19:26:19.775587 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 19:26:19.779302 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 19:26:19.783018 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 19:26:19.786869 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 19:26:19.794015 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 19:26:19.798473 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 19:26:19.806050 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 19:26:19.809979 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 19:26:19.816853 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 19:26:19.824055 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 19:26:19.827953 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 19:26:19.832070 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 19:26:19.839184 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 19:26:19.846315 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 19:26:19.850104 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 19:26:19.854535 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 19:26:19.861638 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 19:26:19.865318 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 19:26:19.872860 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 19:26:19.876550 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 19:26:19.880038 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 19:26:19.887926 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 19:26:19.890852 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 19:26:19.894464 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 19:26:19.902063 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 19:26:19.905713 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 19:26:19.909609 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 19:26:19.917064 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 19:26:19.920767 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 19:26:19.924266 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 19:26:19.927935 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 19:26:19.935026 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 19:26:19.938765 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 19:26:19.942426 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 19:26:19.946448 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 19:26:19.949869 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 19:26:19.957745 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 19:26:19.961396 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 19:26:19.964929 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 19:26:19.968661 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 19:26:19.972879 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 19:26:19.975868 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 19:26:19.983265 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 19:26:19.995109 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 19:26:19.998826 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 19:26:20.005575 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 19:26:20.012863 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 19:26:20.020729 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 19:26:20.023835 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 19:26:20.027420 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 19:26:20.034675 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x8
467 19:26:20.038555 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 19:26:20.046359 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
469 19:26:20.049976 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 19:26:20.059928 [RTC]rtc_get_frequency_meter,154: input=15, output=791
471 19:26:20.068844 [RTC]rtc_get_frequency_meter,154: input=23, output=978
472 19:26:20.078089 [RTC]rtc_get_frequency_meter,154: input=19, output=884
473 19:26:20.088111 [RTC]rtc_get_frequency_meter,154: input=17, output=836
474 19:26:20.097665 [RTC]rtc_get_frequency_meter,154: input=16, output=814
475 19:26:20.106923 [RTC]rtc_get_frequency_meter,154: input=15, output=791
476 19:26:20.116524 [RTC]rtc_get_frequency_meter,154: input=16, output=813
477 19:26:20.120057 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
478 19:26:20.127067 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
479 19:26:20.130437 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 19:26:20.134586 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
481 19:26:20.137699 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 19:26:20.141444 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
483 19:26:20.145842 ADC[4]: Raw value=902066 ID=7
484 19:26:20.149040 ADC[3]: Raw value=212967 ID=1
485 19:26:20.149125 RAM Code: 0x71
486 19:26:20.153021 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 19:26:20.160384 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 19:26:20.168697 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 19:26:20.175881 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 19:26:20.175965 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 19:26:20.180043 in-header: 03 07 00 00 08 00 00 00
492 19:26:20.183250 in-data: aa e4 47 04 13 02 00 00
493 19:26:20.186803 Chrome EC: UHEPI supported
494 19:26:20.194530 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 19:26:20.197956 in-header: 03 ed 00 00 08 00 00 00
496 19:26:20.201702 in-data: 80 20 60 08 00 00 00 00
497 19:26:20.201777 MRC: failed to locate region type 0.
498 19:26:20.209391 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 19:26:20.212261 DRAM-K: Running full calibration
500 19:26:20.220408 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 19:26:20.220485 header.status = 0x0
502 19:26:20.224035 header.version = 0x6 (expected: 0x6)
503 19:26:20.227648 header.size = 0xd00 (expected: 0xd00)
504 19:26:20.227720 header.flags = 0x0
505 19:26:20.234875 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 19:26:20.253251 read SPI 0x72590 0x1c583: 12504 us, 9284 KB/s, 74.272 Mbps
507 19:26:20.261231 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 19:26:20.261330 dram_init: ddr_geometry: 2
509 19:26:20.264812 [EMI] MDL number = 2
510 19:26:20.269189 [EMI] Get MDL freq = 0
511 19:26:20.269284 dram_init: ddr_type: 0
512 19:26:20.272915 is_discrete_lpddr4: 1
513 19:26:20.272991 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 19:26:20.273054
515 19:26:20.276661
516 19:26:20.276731 [Bian_co] ETT version 0.0.0.1
517 19:26:20.280471 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 19:26:20.280548
519 19:26:20.283982 dramc_set_vcore_voltage set vcore to 650000
520 19:26:20.287782 Read voltage for 800, 4
521 19:26:20.287855 Vio18 = 0
522 19:26:20.291459 Vcore = 650000
523 19:26:20.291531 Vdram = 0
524 19:26:20.291595 Vddq = 0
525 19:26:20.291654 Vmddr = 0
526 19:26:20.295208 dram_init: config_dvfs: 1
527 19:26:20.299513 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 19:26:20.306821 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 19:26:20.310321 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
530 19:26:20.313717 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
531 19:26:20.317423 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
532 19:26:20.320598 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
533 19:26:20.324203 MEM_TYPE=3, freq_sel=18
534 19:26:20.327186 sv_algorithm_assistance_LP4_1600
535 19:26:20.330817 ============ PULL DRAM RESETB DOWN ============
536 19:26:20.334204 ========== PULL DRAM RESETB DOWN end =========
537 19:26:20.340658 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 19:26:20.344214 ===================================
539 19:26:20.344294 LPDDR4 DRAM CONFIGURATION
540 19:26:20.347145 ===================================
541 19:26:20.350838 EX_ROW_EN[0] = 0x0
542 19:26:20.350924 EX_ROW_EN[1] = 0x0
543 19:26:20.354023 LP4Y_EN = 0x0
544 19:26:20.354095 WORK_FSP = 0x0
545 19:26:20.357640 WL = 0x2
546 19:26:20.357715 RL = 0x2
547 19:26:20.360773 BL = 0x2
548 19:26:20.360847 RPST = 0x0
549 19:26:20.364357 RD_PRE = 0x0
550 19:26:20.367486 WR_PRE = 0x1
551 19:26:20.367558 WR_PST = 0x0
552 19:26:20.370576 DBI_WR = 0x0
553 19:26:20.370646 DBI_RD = 0x0
554 19:26:20.373987 OTF = 0x1
555 19:26:20.377966 ===================================
556 19:26:20.380663 ===================================
557 19:26:20.380734 ANA top config
558 19:26:20.384018 ===================================
559 19:26:20.387481 DLL_ASYNC_EN = 0
560 19:26:20.387553 ALL_SLAVE_EN = 1
561 19:26:20.390745 NEW_RANK_MODE = 1
562 19:26:20.394100 DLL_IDLE_MODE = 1
563 19:26:20.397643 LP45_APHY_COMB_EN = 1
564 19:26:20.401223 TX_ODT_DIS = 1
565 19:26:20.401309 NEW_8X_MODE = 1
566 19:26:20.404355 ===================================
567 19:26:20.408012 ===================================
568 19:26:20.411217 data_rate = 1600
569 19:26:20.414535 CKR = 1
570 19:26:20.417911 DQ_P2S_RATIO = 8
571 19:26:20.421177 ===================================
572 19:26:20.424491 CA_P2S_RATIO = 8
573 19:26:20.424560 DQ_CA_OPEN = 0
574 19:26:20.428006 DQ_SEMI_OPEN = 0
575 19:26:20.431068 CA_SEMI_OPEN = 0
576 19:26:20.434742 CA_FULL_RATE = 0
577 19:26:20.438030 DQ_CKDIV4_EN = 1
578 19:26:20.441605 CA_CKDIV4_EN = 1
579 19:26:20.441678 CA_PREDIV_EN = 0
580 19:26:20.444662 PH8_DLY = 0
581 19:26:20.448009 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 19:26:20.451656 DQ_AAMCK_DIV = 4
583 19:26:20.454832 CA_AAMCK_DIV = 4
584 19:26:20.454912 CA_ADMCK_DIV = 4
585 19:26:20.458201 DQ_TRACK_CA_EN = 0
586 19:26:20.461315 CA_PICK = 800
587 19:26:20.465028 CA_MCKIO = 800
588 19:26:20.467953 MCKIO_SEMI = 0
589 19:26:20.472270 PLL_FREQ = 3068
590 19:26:20.472344 DQ_UI_PI_RATIO = 32
591 19:26:20.475471 CA_UI_PI_RATIO = 0
592 19:26:20.479552 ===================================
593 19:26:20.483050 ===================================
594 19:26:20.486493 memory_type:LPDDR4
595 19:26:20.486572 GP_NUM : 10
596 19:26:20.490294 SRAM_EN : 1
597 19:26:20.490370 MD32_EN : 0
598 19:26:20.493457 ===================================
599 19:26:20.497564 [ANA_INIT] >>>>>>>>>>>>>>
600 19:26:20.501302 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 19:26:20.504931 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 19:26:20.508710 ===================================
603 19:26:20.508798 data_rate = 1600,PCW = 0X7600
604 19:26:20.511721 ===================================
605 19:26:20.515006 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 19:26:20.521759 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 19:26:20.528393 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 19:26:20.532090 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 19:26:20.535234 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 19:26:20.538847 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 19:26:20.541886 [ANA_INIT] flow start
612 19:26:20.541960 [ANA_INIT] PLL >>>>>>>>
613 19:26:20.545507 [ANA_INIT] PLL <<<<<<<<
614 19:26:20.548628 [ANA_INIT] MIDPI >>>>>>>>
615 19:26:20.548699 [ANA_INIT] MIDPI <<<<<<<<
616 19:26:20.552169 [ANA_INIT] DLL >>>>>>>>
617 19:26:20.555313 [ANA_INIT] flow end
618 19:26:20.559059 ============ LP4 DIFF to SE enter ============
619 19:26:20.562454 ============ LP4 DIFF to SE exit ============
620 19:26:20.565475 [ANA_INIT] <<<<<<<<<<<<<
621 19:26:20.568425 [Flow] Enable top DCM control >>>>>
622 19:26:20.572255 [Flow] Enable top DCM control <<<<<
623 19:26:20.575275 Enable DLL master slave shuffle
624 19:26:20.578980 ==============================================================
625 19:26:20.582056 Gating Mode config
626 19:26:20.585732 ==============================================================
627 19:26:20.589122 Config description:
628 19:26:20.598737 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 19:26:20.605921 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 19:26:20.608674 SELPH_MODE 0: By rank 1: By Phase
631 19:26:20.615830 ==============================================================
632 19:26:20.618859 GAT_TRACK_EN = 1
633 19:26:20.622659 RX_GATING_MODE = 2
634 19:26:20.625572 RX_GATING_TRACK_MODE = 2
635 19:26:20.629343 SELPH_MODE = 1
636 19:26:20.629425 PICG_EARLY_EN = 1
637 19:26:20.632162 VALID_LAT_VALUE = 1
638 19:26:20.638851 ==============================================================
639 19:26:20.642672 Enter into Gating configuration >>>>
640 19:26:20.645751 Exit from Gating configuration <<<<
641 19:26:20.649440 Enter into DVFS_PRE_config >>>>>
642 19:26:20.659140 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 19:26:20.662845 Exit from DVFS_PRE_config <<<<<
644 19:26:20.665701 Enter into PICG configuration >>>>
645 19:26:20.669179 Exit from PICG configuration <<<<
646 19:26:20.672581 [RX_INPUT] configuration >>>>>
647 19:26:20.675879 [RX_INPUT] configuration <<<<<
648 19:26:20.679447 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 19:26:20.685795 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 19:26:20.693294 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 19:26:20.696816 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 19:26:20.703643 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 19:26:20.710332 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 19:26:20.713417 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 19:26:20.716834 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 19:26:20.723475 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 19:26:20.727119 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 19:26:20.730263 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 19:26:20.733999 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 19:26:20.736901 ===================================
661 19:26:20.740558 LPDDR4 DRAM CONFIGURATION
662 19:26:20.743821 ===================================
663 19:26:20.746903 EX_ROW_EN[0] = 0x0
664 19:26:20.746988 EX_ROW_EN[1] = 0x0
665 19:26:20.750287 LP4Y_EN = 0x0
666 19:26:20.750361 WORK_FSP = 0x0
667 19:26:20.754034 WL = 0x2
668 19:26:20.754109 RL = 0x2
669 19:26:20.757194 BL = 0x2
670 19:26:20.757304 RPST = 0x0
671 19:26:20.760959 RD_PRE = 0x0
672 19:26:20.761036 WR_PRE = 0x1
673 19:26:20.763938 WR_PST = 0x0
674 19:26:20.764050 DBI_WR = 0x0
675 19:26:20.767189 DBI_RD = 0x0
676 19:26:20.767263 OTF = 0x1
677 19:26:20.770478 ===================================
678 19:26:20.777478 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 19:26:20.780684 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 19:26:20.783630 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 19:26:20.787476 ===================================
682 19:26:20.790587 LPDDR4 DRAM CONFIGURATION
683 19:26:20.794076 ===================================
684 19:26:20.794146 EX_ROW_EN[0] = 0x10
685 19:26:20.797181 EX_ROW_EN[1] = 0x0
686 19:26:20.800927 LP4Y_EN = 0x0
687 19:26:20.801000 WORK_FSP = 0x0
688 19:26:20.803865 WL = 0x2
689 19:26:20.803938 RL = 0x2
690 19:26:20.807290 BL = 0x2
691 19:26:20.807362 RPST = 0x0
692 19:26:20.810961 RD_PRE = 0x0
693 19:26:20.811040 WR_PRE = 0x1
694 19:26:20.814132 WR_PST = 0x0
695 19:26:20.814204 DBI_WR = 0x0
696 19:26:20.817174 DBI_RD = 0x0
697 19:26:20.817275 OTF = 0x1
698 19:26:20.820708 ===================================
699 19:26:20.827197 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 19:26:20.831436 nWR fixed to 40
701 19:26:20.834575 [ModeRegInit_LP4] CH0 RK0
702 19:26:20.834672 [ModeRegInit_LP4] CH0 RK1
703 19:26:20.838455 [ModeRegInit_LP4] CH1 RK0
704 19:26:20.841613 [ModeRegInit_LP4] CH1 RK1
705 19:26:20.841685 match AC timing 13
706 19:26:20.848289 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 19:26:20.851601 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 19:26:20.855059 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 19:26:20.862061 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 19:26:20.865018 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 19:26:20.865091 [EMI DOE] emi_dcm 0
712 19:26:20.871758 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 19:26:20.871837 ==
714 19:26:20.874837 Dram Type= 6, Freq= 0, CH_0, rank 0
715 19:26:20.878390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 19:26:20.878469 ==
717 19:26:20.885403 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 19:26:20.888369 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 19:26:20.898765 [CA 0] Center 37 (6~68) winsize 63
720 19:26:20.902319 [CA 1] Center 37 (6~68) winsize 63
721 19:26:20.905788 [CA 2] Center 35 (5~66) winsize 62
722 19:26:20.909155 [CA 3] Center 34 (4~65) winsize 62
723 19:26:20.912549 [CA 4] Center 34 (3~65) winsize 63
724 19:26:20.915896 [CA 5] Center 33 (3~64) winsize 62
725 19:26:20.915997
726 19:26:20.919371 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 19:26:20.919441
728 19:26:20.922473 [CATrainingPosCal] consider 1 rank data
729 19:26:20.925561 u2DelayCellTimex100 = 270/100 ps
730 19:26:20.928945 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
731 19:26:20.932478 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
732 19:26:20.936165 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
733 19:26:20.942702 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
734 19:26:20.945907 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
735 19:26:20.949518 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 19:26:20.949590
737 19:26:20.952560 CA PerBit enable=1, Macro0, CA PI delay=33
738 19:26:20.952631
739 19:26:20.956204 [CBTSetCACLKResult] CA Dly = 33
740 19:26:20.956273 CS Dly: 5 (0~36)
741 19:26:20.956332 ==
742 19:26:20.959315 Dram Type= 6, Freq= 0, CH_0, rank 1
743 19:26:20.965738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 19:26:20.965812 ==
745 19:26:20.969414 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 19:26:20.976293 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 19:26:20.985457 [CA 0] Center 37 (6~68) winsize 63
748 19:26:20.988434 [CA 1] Center 37 (7~68) winsize 62
749 19:26:20.991973 [CA 2] Center 35 (5~66) winsize 62
750 19:26:20.995228 [CA 3] Center 35 (4~66) winsize 63
751 19:26:20.998709 [CA 4] Center 34 (3~65) winsize 63
752 19:26:21.001847 [CA 5] Center 33 (3~64) winsize 62
753 19:26:21.001920
754 19:26:21.005353 [CmdBusTrainingLP45] Vref(ca) range 1: 32
755 19:26:21.005421
756 19:26:21.008528 [CATrainingPosCal] consider 2 rank data
757 19:26:21.011948 u2DelayCellTimex100 = 270/100 ps
758 19:26:21.015445 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
759 19:26:21.018870 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
760 19:26:21.025527 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
761 19:26:21.029154 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
762 19:26:21.032352 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
763 19:26:21.035372 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 19:26:21.035452
765 19:26:21.038627 CA PerBit enable=1, Macro0, CA PI delay=33
766 19:26:21.038702
767 19:26:21.041866 [CBTSetCACLKResult] CA Dly = 33
768 19:26:21.041941 CS Dly: 6 (0~38)
769 19:26:21.042003
770 19:26:21.045079 ----->DramcWriteLeveling(PI) begin...
771 19:26:21.045152 ==
772 19:26:21.048604 Dram Type= 6, Freq= 0, CH_0, rank 0
773 19:26:21.055421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 19:26:21.055509 ==
775 19:26:21.059386 Write leveling (Byte 0): 30 => 30
776 19:26:21.059461 Write leveling (Byte 1): 30 => 30
777 19:26:21.063038 DramcWriteLeveling(PI) end<-----
778 19:26:21.063111
779 19:26:21.063172 ==
780 19:26:21.066910 Dram Type= 6, Freq= 0, CH_0, rank 0
781 19:26:21.070457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 19:26:21.070529 ==
783 19:26:21.074007 [Gating] SW mode calibration
784 19:26:21.080635 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 19:26:21.087950 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 19:26:21.091135 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 19:26:21.094587 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
788 19:26:21.101105 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
789 19:26:21.104801 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
790 19:26:21.108158 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 19:26:21.111173 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 19:26:21.118366 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 19:26:21.121297 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 19:26:21.124492 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 19:26:21.131393 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 19:26:21.134733 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 19:26:21.138321 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 19:26:21.144896 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 19:26:21.148046 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 19:26:21.151592 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 19:26:21.158376 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 19:26:21.161407 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 19:26:21.164838 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 19:26:21.171573 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
805 19:26:21.174984 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 19:26:21.178622 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 19:26:21.181763 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 19:26:21.188289 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 19:26:21.191929 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 19:26:21.195028 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 19:26:21.201676 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 19:26:21.205077 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 19:26:21.208780 0 9 12 | B1->B0 | 2625 3333 | 1 1 | (0 0) (1 1)
814 19:26:21.215011 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 19:26:21.218745 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 19:26:21.221657 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 19:26:21.228361 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 19:26:21.232185 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 19:26:21.235546 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
820 19:26:21.242157 0 10 8 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
821 19:26:21.245250 0 10 12 | B1->B0 | 2f2f 2424 | 0 0 | (1 1) (0 0)
822 19:26:21.248670 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 19:26:21.252254 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 19:26:21.258965 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 19:26:21.262069 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 19:26:21.265668 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 19:26:21.272268 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 19:26:21.275587 0 11 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
829 19:26:21.278996 0 11 12 | B1->B0 | 3838 3f3f | 1 0 | (0 0) (0 0)
830 19:26:21.285991 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 19:26:21.289047 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 19:26:21.292463 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 19:26:21.299416 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 19:26:21.302381 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 19:26:21.306119 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 19:26:21.309600 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
837 19:26:21.316141 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
838 19:26:21.319475 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 19:26:21.322537 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 19:26:21.329101 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 19:26:21.332974 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 19:26:21.335989 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 19:26:21.342688 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 19:26:21.346150 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 19:26:21.349811 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 19:26:21.353401 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 19:26:21.359701 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 19:26:21.363464 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 19:26:21.366590 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 19:26:21.372983 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 19:26:21.376717 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 19:26:21.379679 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
853 19:26:21.386517 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
854 19:26:21.386599 Total UI for P1: 0, mck2ui 16
855 19:26:21.393033 best dqsien dly found for B0: ( 0, 14, 8)
856 19:26:21.393115 Total UI for P1: 0, mck2ui 16
857 19:26:21.399839 best dqsien dly found for B1: ( 0, 14, 8)
858 19:26:21.403348 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
859 19:26:21.406599 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
860 19:26:21.406681
861 19:26:21.410322 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
862 19:26:21.413281 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
863 19:26:21.416741 [Gating] SW calibration Done
864 19:26:21.416822 ==
865 19:26:21.420485 Dram Type= 6, Freq= 0, CH_0, rank 0
866 19:26:21.423445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 19:26:21.423527 ==
868 19:26:21.423592 RX Vref Scan: 0
869 19:26:21.427269
870 19:26:21.427350 RX Vref 0 -> 0, step: 1
871 19:26:21.427414
872 19:26:21.430248 RX Delay -130 -> 252, step: 16
873 19:26:21.433462 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
874 19:26:21.436998 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
875 19:26:21.443987 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
876 19:26:21.446687 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
877 19:26:21.450090 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
878 19:26:21.453615 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
879 19:26:21.457293 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
880 19:26:21.463815 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
881 19:26:21.466892 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
882 19:26:21.470544 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
883 19:26:21.473563 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
884 19:26:21.476873 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
885 19:26:21.483845 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
886 19:26:21.487208 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
887 19:26:21.490628 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
888 19:26:21.494048 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
889 19:26:21.494145 ==
890 19:26:21.496861 Dram Type= 6, Freq= 0, CH_0, rank 0
891 19:26:21.500657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 19:26:21.503475 ==
893 19:26:21.503589 DQS Delay:
894 19:26:21.503697 DQS0 = 0, DQS1 = 0
895 19:26:21.507194 DQM Delay:
896 19:26:21.507306 DQM0 = 82, DQM1 = 76
897 19:26:21.510594 DQ Delay:
898 19:26:21.510694 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
899 19:26:21.513791 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =85
900 19:26:21.516905 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
901 19:26:21.520497 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
902 19:26:21.520577
903 19:26:21.523658
904 19:26:21.523758 ==
905 19:26:21.527259 Dram Type= 6, Freq= 0, CH_0, rank 0
906 19:26:21.530407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 19:26:21.530515 ==
908 19:26:21.530614
909 19:26:21.530718
910 19:26:21.533942 TX Vref Scan disable
911 19:26:21.534051 == TX Byte 0 ==
912 19:26:21.537042 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
913 19:26:21.543747 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
914 19:26:21.543827 == TX Byte 1 ==
915 19:26:21.547441 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
916 19:26:21.554135 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
917 19:26:21.554214 ==
918 19:26:21.557481 Dram Type= 6, Freq= 0, CH_0, rank 0
919 19:26:21.560719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 19:26:21.560819 ==
921 19:26:21.574051 TX Vref=22, minBit 0, minWin=27, winSum=438
922 19:26:21.577098 TX Vref=24, minBit 3, minWin=27, winSum=444
923 19:26:21.580671 TX Vref=26, minBit 5, minWin=27, winSum=446
924 19:26:21.583646 TX Vref=28, minBit 5, minWin=27, winSum=452
925 19:26:21.587373 TX Vref=30, minBit 2, minWin=28, winSum=453
926 19:26:21.590399 TX Vref=32, minBit 2, minWin=28, winSum=454
927 19:26:21.597512 [TxChooseVref] Worse bit 2, Min win 28, Win sum 454, Final Vref 32
928 19:26:21.597622
929 19:26:21.600858 Final TX Range 1 Vref 32
930 19:26:21.600944
931 19:26:21.601024 ==
932 19:26:21.604467 Dram Type= 6, Freq= 0, CH_0, rank 0
933 19:26:21.607487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 19:26:21.607565 ==
935 19:26:21.607651
936 19:26:21.607727
937 19:26:21.610692 TX Vref Scan disable
938 19:26:21.614194 == TX Byte 0 ==
939 19:26:21.617845 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
940 19:26:21.621154 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
941 19:26:21.624555 == TX Byte 1 ==
942 19:26:21.627938 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
943 19:26:21.631344 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
944 19:26:21.631450
945 19:26:21.634845 [DATLAT]
946 19:26:21.634925 Freq=800, CH0 RK0
947 19:26:21.635015
948 19:26:21.637738 DATLAT Default: 0xa
949 19:26:21.637849 0, 0xFFFF, sum = 0
950 19:26:21.640975 1, 0xFFFF, sum = 0
951 19:26:21.641086 2, 0xFFFF, sum = 0
952 19:26:21.644555 3, 0xFFFF, sum = 0
953 19:26:21.644639 4, 0xFFFF, sum = 0
954 19:26:21.647796 5, 0xFFFF, sum = 0
955 19:26:21.647872 6, 0xFFFF, sum = 0
956 19:26:21.651410 7, 0xFFFF, sum = 0
957 19:26:21.651494 8, 0xFFFF, sum = 0
958 19:26:21.654615 9, 0x0, sum = 1
959 19:26:21.654698 10, 0x0, sum = 2
960 19:26:21.658431 11, 0x0, sum = 3
961 19:26:21.658514 12, 0x0, sum = 4
962 19:26:21.661629 best_step = 10
963 19:26:21.661710
964 19:26:21.661774 ==
965 19:26:21.664525 Dram Type= 6, Freq= 0, CH_0, rank 0
966 19:26:21.668024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 19:26:21.668106 ==
968 19:26:21.668170 RX Vref Scan: 1
969 19:26:21.668230
970 19:26:21.671560 Set Vref Range= 32 -> 127
971 19:26:21.671698
972 19:26:21.674669 RX Vref 32 -> 127, step: 1
973 19:26:21.674750
974 19:26:21.678197 RX Delay -95 -> 252, step: 8
975 19:26:21.678277
976 19:26:21.681639 Set Vref, RX VrefLevel [Byte0]: 32
977 19:26:21.684841 [Byte1]: 32
978 19:26:21.684922
979 19:26:21.688077 Set Vref, RX VrefLevel [Byte0]: 33
980 19:26:21.691671 [Byte1]: 33
981 19:26:21.691752
982 19:26:21.695891 Set Vref, RX VrefLevel [Byte0]: 34
983 19:26:21.699028 [Byte1]: 34
984 19:26:21.699109
985 19:26:21.702797 Set Vref, RX VrefLevel [Byte0]: 35
986 19:26:21.705645 [Byte1]: 35
987 19:26:21.709410
988 19:26:21.709490 Set Vref, RX VrefLevel [Byte0]: 36
989 19:26:21.712881 [Byte1]: 36
990 19:26:21.716814
991 19:26:21.716894 Set Vref, RX VrefLevel [Byte0]: 37
992 19:26:21.719936 [Byte1]: 37
993 19:26:21.724734
994 19:26:21.724840 Set Vref, RX VrefLevel [Byte0]: 38
995 19:26:21.728242 [Byte1]: 38
996 19:26:21.732911
997 19:26:21.732992 Set Vref, RX VrefLevel [Byte0]: 39
998 19:26:21.736045 [Byte1]: 39
999 19:26:21.739860
1000 19:26:21.739942 Set Vref, RX VrefLevel [Byte0]: 40
1001 19:26:21.743208 [Byte1]: 40
1002 19:26:21.747890
1003 19:26:21.747972 Set Vref, RX VrefLevel [Byte0]: 41
1004 19:26:21.751035 [Byte1]: 41
1005 19:26:21.755380
1006 19:26:21.755490 Set Vref, RX VrefLevel [Byte0]: 42
1007 19:26:21.759088 [Byte1]: 42
1008 19:26:21.762655
1009 19:26:21.762736 Set Vref, RX VrefLevel [Byte0]: 43
1010 19:26:21.765818 [Byte1]: 43
1011 19:26:21.770095
1012 19:26:21.770176 Set Vref, RX VrefLevel [Byte0]: 44
1013 19:26:21.773385 [Byte1]: 44
1014 19:26:21.777895
1015 19:26:21.777976 Set Vref, RX VrefLevel [Byte0]: 45
1016 19:26:21.780930 [Byte1]: 45
1017 19:26:21.785190
1018 19:26:21.785291 Set Vref, RX VrefLevel [Byte0]: 46
1019 19:26:21.788392 [Byte1]: 46
1020 19:26:21.792802
1021 19:26:21.792883 Set Vref, RX VrefLevel [Byte0]: 47
1022 19:26:21.796279 [Byte1]: 47
1023 19:26:21.800158
1024 19:26:21.800240 Set Vref, RX VrefLevel [Byte0]: 48
1025 19:26:21.803796 [Byte1]: 48
1026 19:26:21.808046
1027 19:26:21.808125 Set Vref, RX VrefLevel [Byte0]: 49
1028 19:26:21.811073 [Byte1]: 49
1029 19:26:21.815652
1030 19:26:21.815731 Set Vref, RX VrefLevel [Byte0]: 50
1031 19:26:21.818981 [Byte1]: 50
1032 19:26:21.823342
1033 19:26:21.823422 Set Vref, RX VrefLevel [Byte0]: 51
1034 19:26:21.826399 [Byte1]: 51
1035 19:26:21.831202
1036 19:26:21.831282 Set Vref, RX VrefLevel [Byte0]: 52
1037 19:26:21.833984 [Byte1]: 52
1038 19:26:21.838440
1039 19:26:21.838515 Set Vref, RX VrefLevel [Byte0]: 53
1040 19:26:21.841403 [Byte1]: 53
1041 19:26:21.845735
1042 19:26:21.845846 Set Vref, RX VrefLevel [Byte0]: 54
1043 19:26:21.849440 [Byte1]: 54
1044 19:26:21.853407
1045 19:26:21.853516 Set Vref, RX VrefLevel [Byte0]: 55
1046 19:26:21.856701 [Byte1]: 55
1047 19:26:21.861024
1048 19:26:21.861125 Set Vref, RX VrefLevel [Byte0]: 56
1049 19:26:21.864790 [Byte1]: 56
1050 19:26:21.869126
1051 19:26:21.869257 Set Vref, RX VrefLevel [Byte0]: 57
1052 19:26:21.872145 [Byte1]: 57
1053 19:26:21.875878
1054 19:26:21.879394 Set Vref, RX VrefLevel [Byte0]: 58
1055 19:26:21.883058 [Byte1]: 58
1056 19:26:21.883152
1057 19:26:21.885905 Set Vref, RX VrefLevel [Byte0]: 59
1058 19:26:21.889630 [Byte1]: 59
1059 19:26:21.889731
1060 19:26:21.892625 Set Vref, RX VrefLevel [Byte0]: 60
1061 19:26:21.896026 [Byte1]: 60
1062 19:26:21.896127
1063 19:26:21.899289 Set Vref, RX VrefLevel [Byte0]: 61
1064 19:26:21.902876 [Byte1]: 61
1065 19:26:21.906638
1066 19:26:21.906744 Set Vref, RX VrefLevel [Byte0]: 62
1067 19:26:21.910170 [Byte1]: 62
1068 19:26:21.914681
1069 19:26:21.914750 Set Vref, RX VrefLevel [Byte0]: 63
1070 19:26:21.917809 [Byte1]: 63
1071 19:26:21.921717
1072 19:26:21.921822 Set Vref, RX VrefLevel [Byte0]: 64
1073 19:26:21.925185 [Byte1]: 64
1074 19:26:21.929523
1075 19:26:21.929603 Set Vref, RX VrefLevel [Byte0]: 65
1076 19:26:21.932546 [Byte1]: 65
1077 19:26:21.937184
1078 19:26:21.937315 Set Vref, RX VrefLevel [Byte0]: 66
1079 19:26:21.940723 [Byte1]: 66
1080 19:26:21.944741
1081 19:26:21.944821 Set Vref, RX VrefLevel [Byte0]: 67
1082 19:26:21.947926 [Byte1]: 67
1083 19:26:21.952243
1084 19:26:21.952323 Set Vref, RX VrefLevel [Byte0]: 68
1085 19:26:21.955720 [Byte1]: 68
1086 19:26:21.959680
1087 19:26:21.959760 Set Vref, RX VrefLevel [Byte0]: 69
1088 19:26:21.962999 [Byte1]: 69
1089 19:26:21.967334
1090 19:26:21.967414 Set Vref, RX VrefLevel [Byte0]: 70
1091 19:26:21.971132 [Byte1]: 70
1092 19:26:21.975466
1093 19:26:21.975545 Set Vref, RX VrefLevel [Byte0]: 71
1094 19:26:21.978691 [Byte1]: 71
1095 19:26:21.983090
1096 19:26:21.983169 Set Vref, RX VrefLevel [Byte0]: 72
1097 19:26:21.986002 [Byte1]: 72
1098 19:26:21.990784
1099 19:26:21.990880 Set Vref, RX VrefLevel [Byte0]: 73
1100 19:26:21.993540 [Byte1]: 73
1101 19:26:21.997905
1102 19:26:21.998000 Set Vref, RX VrefLevel [Byte0]: 74
1103 19:26:22.001176 [Byte1]: 74
1104 19:26:22.005459
1105 19:26:22.005539 Set Vref, RX VrefLevel [Byte0]: 75
1106 19:26:22.008748 [Byte1]: 75
1107 19:26:22.012916
1108 19:26:22.012998 Set Vref, RX VrefLevel [Byte0]: 76
1109 19:26:22.016274 [Byte1]: 76
1110 19:26:22.020683
1111 19:26:22.020763 Final RX Vref Byte 0 = 62 to rank0
1112 19:26:22.024231 Final RX Vref Byte 1 = 57 to rank0
1113 19:26:22.027283 Final RX Vref Byte 0 = 62 to rank1
1114 19:26:22.030923 Final RX Vref Byte 1 = 57 to rank1==
1115 19:26:22.034328 Dram Type= 6, Freq= 0, CH_0, rank 0
1116 19:26:22.037614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1117 19:26:22.040753 ==
1118 19:26:22.040834 DQS Delay:
1119 19:26:22.040897 DQS0 = 0, DQS1 = 0
1120 19:26:22.044543 DQM Delay:
1121 19:26:22.044623 DQM0 = 87, DQM1 = 79
1122 19:26:22.047353 DQ Delay:
1123 19:26:22.050598 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1124 19:26:22.050678 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =92
1125 19:26:22.054154 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =76
1126 19:26:22.057180 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =88
1127 19:26:22.060961
1128 19:26:22.061040
1129 19:26:22.067165 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a11, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps
1130 19:26:22.070668 CH0 RK0: MR19=606, MR18=2A11
1131 19:26:22.077682 CH0_RK0: MR19=0x606, MR18=0x2A11, DQSOSC=399, MR23=63, INC=92, DEC=61
1132 19:26:22.077762
1133 19:26:22.081093 ----->DramcWriteLeveling(PI) begin...
1134 19:26:22.081190 ==
1135 19:26:22.084162 Dram Type= 6, Freq= 0, CH_0, rank 1
1136 19:26:22.087741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1137 19:26:22.087822 ==
1138 19:26:22.090701 Write leveling (Byte 0): 32 => 32
1139 19:26:22.094503 Write leveling (Byte 1): 29 => 29
1140 19:26:22.097610 DramcWriteLeveling(PI) end<-----
1141 19:26:22.097690
1142 19:26:22.097753 ==
1143 19:26:22.101211 Dram Type= 6, Freq= 0, CH_0, rank 1
1144 19:26:22.104126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1145 19:26:22.104207 ==
1146 19:26:22.108144 [Gating] SW mode calibration
1147 19:26:22.114306 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1148 19:26:22.121758 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1149 19:26:22.124291 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1150 19:26:22.127978 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1151 19:26:22.131467 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1152 19:26:22.175442 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 19:26:22.175770 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 19:26:22.175873 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 19:26:22.175967 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 19:26:22.176057 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 19:26:22.176174 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 19:26:22.176263 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 19:26:22.176357 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 19:26:22.176430 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 19:26:22.176483 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 19:26:22.219399 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 19:26:22.219741 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 19:26:22.219820 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 19:26:22.219894 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1166 19:26:22.219956 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1167 19:26:22.220026 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1168 19:26:22.220085 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 19:26:22.220152 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 19:26:22.220231 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 19:26:22.220321 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 19:26:22.223769 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 19:26:22.230275 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 19:26:22.234088 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 19:26:22.237154 0 9 8 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
1176 19:26:22.243824 0 9 12 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
1177 19:26:22.247706 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 19:26:22.250528 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 19:26:22.257355 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 19:26:22.260435 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 19:26:22.263679 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 19:26:22.270631 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
1183 19:26:22.273710 0 10 8 | B1->B0 | 2f2f 2424 | 0 0 | (0 0) (0 0)
1184 19:26:22.277308 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 19:26:22.281064 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 19:26:22.287149 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 19:26:22.290761 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 19:26:22.294058 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 19:26:22.300580 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 19:26:22.304843 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1191 19:26:22.308625 0 11 8 | B1->B0 | 2828 4040 | 1 0 | (0 0) (1 1)
1192 19:26:22.312457 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
1193 19:26:22.316079 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 19:26:22.323301 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 19:26:22.326925 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 19:26:22.330139 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 19:26:22.333949 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1198 19:26:22.340621 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 19:26:22.344228 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1200 19:26:22.347429 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1201 19:26:22.351189 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 19:26:22.357734 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 19:26:22.360872 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 19:26:22.364758 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 19:26:22.370979 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 19:26:22.374428 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 19:26:22.377971 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 19:26:22.384711 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 19:26:22.387735 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 19:26:22.391310 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 19:26:22.398074 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 19:26:22.401095 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 19:26:22.404601 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 19:26:22.408003 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1215 19:26:22.414668 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1216 19:26:22.418119 Total UI for P1: 0, mck2ui 16
1217 19:26:22.421309 best dqsien dly found for B0: ( 0, 14, 4)
1218 19:26:22.425035 Total UI for P1: 0, mck2ui 16
1219 19:26:22.427942 best dqsien dly found for B1: ( 0, 14, 6)
1220 19:26:22.431811 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1221 19:26:22.434671 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1222 19:26:22.434760
1223 19:26:22.438525 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1224 19:26:22.441492 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1225 19:26:22.444643 [Gating] SW calibration Done
1226 19:26:22.444724 ==
1227 19:26:22.448192 Dram Type= 6, Freq= 0, CH_0, rank 1
1228 19:26:22.451724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1229 19:26:22.451806 ==
1230 19:26:22.454684 RX Vref Scan: 0
1231 19:26:22.454773
1232 19:26:22.454838 RX Vref 0 -> 0, step: 1
1233 19:26:22.454897
1234 19:26:22.458479 RX Delay -130 -> 252, step: 16
1235 19:26:22.461503 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1236 19:26:22.468544 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1237 19:26:22.471906 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1238 19:26:22.475097 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1239 19:26:22.478081 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1240 19:26:22.481832 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1241 19:26:22.488658 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1242 19:26:22.491645 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1243 19:26:22.495142 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1244 19:26:22.498229 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1245 19:26:22.501682 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1246 19:26:22.508442 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1247 19:26:22.511556 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1248 19:26:22.515023 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1249 19:26:22.518220 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1250 19:26:22.521581 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1251 19:26:22.521662 ==
1252 19:26:22.525234 Dram Type= 6, Freq= 0, CH_0, rank 1
1253 19:26:22.531595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1254 19:26:22.531681 ==
1255 19:26:22.531745 DQS Delay:
1256 19:26:22.535280 DQS0 = 0, DQS1 = 0
1257 19:26:22.535360 DQM Delay:
1258 19:26:22.535424 DQM0 = 86, DQM1 = 77
1259 19:26:22.538277 DQ Delay:
1260 19:26:22.541575 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1261 19:26:22.545149 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =93
1262 19:26:22.548496 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1263 19:26:22.552112 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1264 19:26:22.552192
1265 19:26:22.552295
1266 19:26:22.552354 ==
1267 19:26:22.555225 Dram Type= 6, Freq= 0, CH_0, rank 1
1268 19:26:22.558793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1269 19:26:22.558888 ==
1270 19:26:22.558968
1271 19:26:22.559042
1272 19:26:22.562022 TX Vref Scan disable
1273 19:26:22.562101 == TX Byte 0 ==
1274 19:26:22.568411 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1275 19:26:22.571585 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1276 19:26:22.571665 == TX Byte 1 ==
1277 19:26:22.578429 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1278 19:26:22.582135 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1279 19:26:22.582216 ==
1280 19:26:22.585099 Dram Type= 6, Freq= 0, CH_0, rank 1
1281 19:26:22.588461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1282 19:26:22.588542 ==
1283 19:26:22.603084 TX Vref=22, minBit 5, minWin=27, winSum=445
1284 19:26:22.606744 TX Vref=24, minBit 5, minWin=27, winSum=447
1285 19:26:22.609986 TX Vref=26, minBit 9, minWin=27, winSum=450
1286 19:26:22.612950 TX Vref=28, minBit 12, minWin=27, winSum=452
1287 19:26:22.616403 TX Vref=30, minBit 2, minWin=28, winSum=456
1288 19:26:22.619666 TX Vref=32, minBit 2, minWin=28, winSum=456
1289 19:26:22.626805 [TxChooseVref] Worse bit 2, Min win 28, Win sum 456, Final Vref 30
1290 19:26:22.626901
1291 19:26:22.629975 Final TX Range 1 Vref 30
1292 19:26:22.630070
1293 19:26:22.630147 ==
1294 19:26:22.633567 Dram Type= 6, Freq= 0, CH_0, rank 1
1295 19:26:22.636277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1296 19:26:22.636408 ==
1297 19:26:22.636499
1298 19:26:22.636585
1299 19:26:22.639779 TX Vref Scan disable
1300 19:26:22.642999 == TX Byte 0 ==
1301 19:26:22.646695 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1302 19:26:22.649799 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1303 19:26:22.653390 == TX Byte 1 ==
1304 19:26:22.656411 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1305 19:26:22.660078 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1306 19:26:22.660158
1307 19:26:22.663095 [DATLAT]
1308 19:26:22.663173 Freq=800, CH0 RK1
1309 19:26:22.663236
1310 19:26:22.666373 DATLAT Default: 0xa
1311 19:26:22.666452 0, 0xFFFF, sum = 0
1312 19:26:22.670021 1, 0xFFFF, sum = 0
1313 19:26:22.670120 2, 0xFFFF, sum = 0
1314 19:26:22.673344 3, 0xFFFF, sum = 0
1315 19:26:22.673425 4, 0xFFFF, sum = 0
1316 19:26:22.676630 5, 0xFFFF, sum = 0
1317 19:26:22.676710 6, 0xFFFF, sum = 0
1318 19:26:22.679817 7, 0xFFFF, sum = 0
1319 19:26:22.679889 8, 0xFFFF, sum = 0
1320 19:26:22.683246 9, 0x0, sum = 1
1321 19:26:22.683325 10, 0x0, sum = 2
1322 19:26:22.686656 11, 0x0, sum = 3
1323 19:26:22.686767 12, 0x0, sum = 4
1324 19:26:22.690101 best_step = 10
1325 19:26:22.690182
1326 19:26:22.690244 ==
1327 19:26:22.693136 Dram Type= 6, Freq= 0, CH_0, rank 1
1328 19:26:22.697074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1329 19:26:22.697158 ==
1330 19:26:22.700345 RX Vref Scan: 0
1331 19:26:22.700435
1332 19:26:22.700505 RX Vref 0 -> 0, step: 1
1333 19:26:22.700572
1334 19:26:22.703244 RX Delay -95 -> 252, step: 8
1335 19:26:22.710268 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1336 19:26:22.713716 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1337 19:26:22.717170 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1338 19:26:22.720261 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1339 19:26:22.724293 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1340 19:26:22.727307 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1341 19:26:22.734166 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1342 19:26:22.737190 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1343 19:26:22.740369 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1344 19:26:22.743900 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1345 19:26:22.747158 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1346 19:26:22.753618 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1347 19:26:22.757108 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1348 19:26:22.760604 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1349 19:26:22.763890 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1350 19:26:22.767050 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1351 19:26:22.767129 ==
1352 19:26:22.770359 Dram Type= 6, Freq= 0, CH_0, rank 1
1353 19:26:22.777599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1354 19:26:22.777674 ==
1355 19:26:22.777736 DQS Delay:
1356 19:26:22.780642 DQS0 = 0, DQS1 = 0
1357 19:26:22.780723 DQM Delay:
1358 19:26:22.780787 DQM0 = 87, DQM1 = 78
1359 19:26:22.783695 DQ Delay:
1360 19:26:22.787309 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1361 19:26:22.790618 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1362 19:26:22.794034 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1363 19:26:22.797019 DQ12 =80, DQ13 =84, DQ14 =88, DQ15 =88
1364 19:26:22.797098
1365 19:26:22.797159
1366 19:26:22.804006 [DQSOSCAuto] RK1, (LSB)MR18= 0x2c16, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps
1367 19:26:22.807502 CH0 RK1: MR19=606, MR18=2C16
1368 19:26:22.814147 CH0_RK1: MR19=0x606, MR18=0x2C16, DQSOSC=398, MR23=63, INC=93, DEC=62
1369 19:26:22.817819 [RxdqsGatingPostProcess] freq 800
1370 19:26:22.821068 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1371 19:26:22.824040 Pre-setting of DQS Precalculation
1372 19:26:22.830744 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1373 19:26:22.830829 ==
1374 19:26:22.834466 Dram Type= 6, Freq= 0, CH_1, rank 0
1375 19:26:22.837307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1376 19:26:22.837396 ==
1377 19:26:22.844040 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1378 19:26:22.847749 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1379 19:26:22.858477 [CA 0] Center 36 (7~66) winsize 60
1380 19:26:22.861256 [CA 1] Center 36 (6~67) winsize 62
1381 19:26:22.864650 [CA 2] Center 34 (4~65) winsize 62
1382 19:26:22.868118 [CA 3] Center 34 (3~65) winsize 63
1383 19:26:22.871352 [CA 4] Center 34 (4~65) winsize 62
1384 19:26:22.874745 [CA 5] Center 33 (3~64) winsize 62
1385 19:26:22.874826
1386 19:26:22.878167 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1387 19:26:22.878248
1388 19:26:22.881384 [CATrainingPosCal] consider 1 rank data
1389 19:26:22.884800 u2DelayCellTimex100 = 270/100 ps
1390 19:26:22.888096 CA0 delay=36 (7~66),Diff = 3 PI (21 cell)
1391 19:26:22.891356 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1392 19:26:22.894895 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1393 19:26:22.898379 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1394 19:26:22.905381 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1395 19:26:22.908388 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1396 19:26:22.908469
1397 19:26:22.911966 CA PerBit enable=1, Macro0, CA PI delay=33
1398 19:26:22.912047
1399 19:26:22.915372 [CBTSetCACLKResult] CA Dly = 33
1400 19:26:22.915453 CS Dly: 4 (0~35)
1401 19:26:22.915517 ==
1402 19:26:22.918737 Dram Type= 6, Freq= 0, CH_1, rank 1
1403 19:26:22.921773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1404 19:26:22.925530 ==
1405 19:26:22.928538 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1406 19:26:22.935340 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1407 19:26:22.943883 [CA 0] Center 36 (6~66) winsize 61
1408 19:26:22.947530 [CA 1] Center 36 (6~66) winsize 61
1409 19:26:22.950723 [CA 2] Center 34 (4~65) winsize 62
1410 19:26:22.953725 [CA 3] Center 33 (3~64) winsize 62
1411 19:26:22.957170 [CA 4] Center 34 (4~65) winsize 62
1412 19:26:22.960468 [CA 5] Center 33 (3~64) winsize 62
1413 19:26:22.960537
1414 19:26:22.963968 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1415 19:26:22.964048
1416 19:26:22.967140 [CATrainingPosCal] consider 2 rank data
1417 19:26:22.971051 u2DelayCellTimex100 = 270/100 ps
1418 19:26:22.974690 CA0 delay=36 (7~66),Diff = 3 PI (21 cell)
1419 19:26:22.978397 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1420 19:26:22.981731 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1421 19:26:22.985391 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1422 19:26:22.989094 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1423 19:26:22.993125 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1424 19:26:22.993217
1425 19:26:22.997192 CA PerBit enable=1, Macro0, CA PI delay=33
1426 19:26:22.997301
1427 19:26:23.000754 [CBTSetCACLKResult] CA Dly = 33
1428 19:26:23.000834 CS Dly: 5 (0~37)
1429 19:26:23.000898
1430 19:26:23.004410 ----->DramcWriteLeveling(PI) begin...
1431 19:26:23.004492 ==
1432 19:26:23.007760 Dram Type= 6, Freq= 0, CH_1, rank 0
1433 19:26:23.011493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1434 19:26:23.015076 ==
1435 19:26:23.015157 Write leveling (Byte 0): 25 => 25
1436 19:26:23.018141 Write leveling (Byte 1): 29 => 29
1437 19:26:23.021605 DramcWriteLeveling(PI) end<-----
1438 19:26:23.021685
1439 19:26:23.021749 ==
1440 19:26:23.024761 Dram Type= 6, Freq= 0, CH_1, rank 0
1441 19:26:23.031704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1442 19:26:23.031793 ==
1443 19:26:23.031859 [Gating] SW mode calibration
1444 19:26:23.041630 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1445 19:26:23.045073 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1446 19:26:23.048547 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1447 19:26:23.055192 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1448 19:26:23.058445 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1449 19:26:23.061581 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 19:26:23.068270 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 19:26:23.071431 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 19:26:23.075291 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 19:26:23.081554 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 19:26:23.084902 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 19:26:23.088832 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 19:26:23.095324 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 19:26:23.098440 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 19:26:23.102107 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 19:26:23.105151 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 19:26:23.111936 0 7 24 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1461 19:26:23.115121 0 7 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1462 19:26:23.118625 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 19:26:23.125453 0 8 4 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1464 19:26:23.128789 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1465 19:26:23.131651 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 19:26:23.138513 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 19:26:23.141984 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 19:26:23.145261 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 19:26:23.152428 0 8 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1470 19:26:23.155537 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 19:26:23.158530 0 9 4 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
1472 19:26:23.165800 0 9 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1473 19:26:23.168884 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1474 19:26:23.172145 0 9 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1475 19:26:23.175624 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 19:26:23.182470 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 19:26:23.185462 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 19:26:23.189017 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 19:26:23.195963 0 10 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1480 19:26:23.198971 0 10 8 | B1->B0 | 2c2c 2c2c | 0 0 | (1 0) (0 0)
1481 19:26:23.202454 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 19:26:23.209256 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 19:26:23.212372 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 19:26:23.216138 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 19:26:23.222965 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 19:26:23.225979 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 19:26:23.229336 0 11 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1488 19:26:23.232818 0 11 8 | B1->B0 | 2f2f 2929 | 0 0 | (1 1) (0 0)
1489 19:26:23.239690 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1490 19:26:23.242723 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1491 19:26:23.245940 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 19:26:23.253063 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 19:26:23.256224 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 19:26:23.259358 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 19:26:23.266309 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 19:26:23.269321 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1497 19:26:23.272909 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 19:26:23.279823 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 19:26:23.282726 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 19:26:23.286586 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 19:26:23.293063 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 19:26:23.296214 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 19:26:23.299800 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 19:26:23.302746 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 19:26:23.309717 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 19:26:23.312841 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 19:26:23.316440 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 19:26:23.323153 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 19:26:23.326360 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 19:26:23.329822 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 19:26:23.336774 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 19:26:23.339834 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1513 19:26:23.343418 Total UI for P1: 0, mck2ui 16
1514 19:26:23.346411 best dqsien dly found for B0: ( 0, 14, 6)
1515 19:26:23.350189 Total UI for P1: 0, mck2ui 16
1516 19:26:23.353484 best dqsien dly found for B1: ( 0, 14, 6)
1517 19:26:23.356927 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1518 19:26:23.359965 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1519 19:26:23.360047
1520 19:26:23.363278 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1521 19:26:23.366839 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1522 19:26:23.369722 [Gating] SW calibration Done
1523 19:26:23.369803 ==
1524 19:26:23.373265 Dram Type= 6, Freq= 0, CH_1, rank 0
1525 19:26:23.376677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1526 19:26:23.376759 ==
1527 19:26:23.380417 RX Vref Scan: 0
1528 19:26:23.380497
1529 19:26:23.380560 RX Vref 0 -> 0, step: 1
1530 19:26:23.380619
1531 19:26:23.383301 RX Delay -130 -> 252, step: 16
1532 19:26:23.390127 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1533 19:26:23.393453 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1534 19:26:23.396898 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1535 19:26:23.400136 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1536 19:26:23.403654 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1537 19:26:23.407408 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1538 19:26:23.413615 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1539 19:26:23.417191 iDelay=206, Bit 7, Center 77 (-50 ~ 205) 256
1540 19:26:23.420337 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1541 19:26:23.423925 iDelay=206, Bit 9, Center 53 (-66 ~ 173) 240
1542 19:26:23.427154 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1543 19:26:23.433739 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1544 19:26:23.437667 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1545 19:26:23.440713 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1546 19:26:23.444360 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1547 19:26:23.447366 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1548 19:26:23.447445 ==
1549 19:26:23.450587 Dram Type= 6, Freq= 0, CH_1, rank 0
1550 19:26:23.457648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1551 19:26:23.457730 ==
1552 19:26:23.457794 DQS Delay:
1553 19:26:23.460587 DQS0 = 0, DQS1 = 0
1554 19:26:23.460667 DQM Delay:
1555 19:26:23.460757 DQM0 = 82, DQM1 = 74
1556 19:26:23.464200 DQ Delay:
1557 19:26:23.467357 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1558 19:26:23.470921 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1559 19:26:23.474107 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
1560 19:26:23.477583 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1561 19:26:23.477655
1562 19:26:23.477715
1563 19:26:23.477771 ==
1564 19:26:23.480812 Dram Type= 6, Freq= 0, CH_1, rank 0
1565 19:26:23.483818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1566 19:26:23.483906 ==
1567 19:26:23.483983
1568 19:26:23.484041
1569 19:26:23.487575 TX Vref Scan disable
1570 19:26:23.487642 == TX Byte 0 ==
1571 19:26:23.494586 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1572 19:26:23.497429 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1573 19:26:23.497509 == TX Byte 1 ==
1574 19:26:23.504500 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1575 19:26:23.507412 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1576 19:26:23.507494 ==
1577 19:26:23.510758 Dram Type= 6, Freq= 0, CH_1, rank 0
1578 19:26:23.514080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1579 19:26:23.514161 ==
1580 19:26:23.528323 TX Vref=22, minBit 10, minWin=26, winSum=437
1581 19:26:23.531802 TX Vref=24, minBit 4, minWin=27, winSum=440
1582 19:26:23.535353 TX Vref=26, minBit 0, minWin=27, winSum=444
1583 19:26:23.538492 TX Vref=28, minBit 4, minWin=27, winSum=449
1584 19:26:23.542038 TX Vref=30, minBit 5, minWin=27, winSum=451
1585 19:26:23.545060 TX Vref=32, minBit 11, minWin=27, winSum=451
1586 19:26:23.551827 [TxChooseVref] Worse bit 5, Min win 27, Win sum 451, Final Vref 30
1587 19:26:23.551908
1588 19:26:23.555765 Final TX Range 1 Vref 30
1589 19:26:23.555871
1590 19:26:23.555936 ==
1591 19:26:23.559218 Dram Type= 6, Freq= 0, CH_1, rank 0
1592 19:26:23.562893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1593 19:26:23.562995 ==
1594 19:26:23.563059
1595 19:26:23.563119
1596 19:26:23.566554 TX Vref Scan disable
1597 19:26:23.569425 == TX Byte 0 ==
1598 19:26:23.572832 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1599 19:26:23.576235 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1600 19:26:23.580261 == TX Byte 1 ==
1601 19:26:23.583188 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1602 19:26:23.586290 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1603 19:26:23.586374
1604 19:26:23.586438 [DATLAT]
1605 19:26:23.589868 Freq=800, CH1 RK0
1606 19:26:23.589950
1607 19:26:23.593001 DATLAT Default: 0xa
1608 19:26:23.593081 0, 0xFFFF, sum = 0
1609 19:26:23.596400 1, 0xFFFF, sum = 0
1610 19:26:23.596487 2, 0xFFFF, sum = 0
1611 19:26:23.599630 3, 0xFFFF, sum = 0
1612 19:26:23.599728 4, 0xFFFF, sum = 0
1613 19:26:23.603055 5, 0xFFFF, sum = 0
1614 19:26:23.603139 6, 0xFFFF, sum = 0
1615 19:26:23.606759 7, 0xFFFF, sum = 0
1616 19:26:23.606841 8, 0xFFFF, sum = 0
1617 19:26:23.609647 9, 0x0, sum = 1
1618 19:26:23.609728 10, 0x0, sum = 2
1619 19:26:23.613085 11, 0x0, sum = 3
1620 19:26:23.613169 12, 0x0, sum = 4
1621 19:26:23.613258 best_step = 10
1622 19:26:23.613319
1623 19:26:23.616410 ==
1624 19:26:23.616491 Dram Type= 6, Freq= 0, CH_1, rank 0
1625 19:26:23.622993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1626 19:26:23.623075 ==
1627 19:26:23.623138 RX Vref Scan: 1
1628 19:26:23.623196
1629 19:26:23.626905 Set Vref Range= 32 -> 127
1630 19:26:23.626985
1631 19:26:23.629835 RX Vref 32 -> 127, step: 1
1632 19:26:23.629915
1633 19:26:23.633617 RX Delay -111 -> 252, step: 8
1634 19:26:23.633698
1635 19:26:23.636634 Set Vref, RX VrefLevel [Byte0]: 32
1636 19:26:23.639737 [Byte1]: 32
1637 19:26:23.639818
1638 19:26:23.643336 Set Vref, RX VrefLevel [Byte0]: 33
1639 19:26:23.646533 [Byte1]: 33
1640 19:26:23.646613
1641 19:26:23.650241 Set Vref, RX VrefLevel [Byte0]: 34
1642 19:26:23.653068 [Byte1]: 34
1643 19:26:23.656847
1644 19:26:23.656944 Set Vref, RX VrefLevel [Byte0]: 35
1645 19:26:23.659985 [Byte1]: 35
1646 19:26:23.664128
1647 19:26:23.664226 Set Vref, RX VrefLevel [Byte0]: 36
1648 19:26:23.667819 [Byte1]: 36
1649 19:26:23.671934
1650 19:26:23.672021 Set Vref, RX VrefLevel [Byte0]: 37
1651 19:26:23.675350 [Byte1]: 37
1652 19:26:23.679827
1653 19:26:23.679908 Set Vref, RX VrefLevel [Byte0]: 38
1654 19:26:23.683258 [Byte1]: 38
1655 19:26:23.687335
1656 19:26:23.687415 Set Vref, RX VrefLevel [Byte0]: 39
1657 19:26:23.690363 [Byte1]: 39
1658 19:26:23.694775
1659 19:26:23.694856 Set Vref, RX VrefLevel [Byte0]: 40
1660 19:26:23.698403 [Byte1]: 40
1661 19:26:23.702613
1662 19:26:23.702694 Set Vref, RX VrefLevel [Byte0]: 41
1663 19:26:23.709199 [Byte1]: 41
1664 19:26:23.709301
1665 19:26:23.712248 Set Vref, RX VrefLevel [Byte0]: 42
1666 19:26:23.715906 [Byte1]: 42
1667 19:26:23.715990
1668 19:26:23.719306 Set Vref, RX VrefLevel [Byte0]: 43
1669 19:26:23.722608 [Byte1]: 43
1670 19:26:23.722689
1671 19:26:23.726027 Set Vref, RX VrefLevel [Byte0]: 44
1672 19:26:23.728957 [Byte1]: 44
1673 19:26:23.733267
1674 19:26:23.733350 Set Vref, RX VrefLevel [Byte0]: 45
1675 19:26:23.736154 [Byte1]: 45
1676 19:26:23.740607
1677 19:26:23.740706 Set Vref, RX VrefLevel [Byte0]: 46
1678 19:26:23.744362 [Byte1]: 46
1679 19:26:23.748534
1680 19:26:23.748633 Set Vref, RX VrefLevel [Byte0]: 47
1681 19:26:23.751496 [Byte1]: 47
1682 19:26:23.755928
1683 19:26:23.756008 Set Vref, RX VrefLevel [Byte0]: 48
1684 19:26:23.759580 [Byte1]: 48
1685 19:26:23.763795
1686 19:26:23.763894 Set Vref, RX VrefLevel [Byte0]: 49
1687 19:26:23.766990 [Byte1]: 49
1688 19:26:23.771610
1689 19:26:23.771691 Set Vref, RX VrefLevel [Byte0]: 50
1690 19:26:23.774545 [Byte1]: 50
1691 19:26:23.779115
1692 19:26:23.779195 Set Vref, RX VrefLevel [Byte0]: 51
1693 19:26:23.782393 [Byte1]: 51
1694 19:26:23.786406
1695 19:26:23.786487 Set Vref, RX VrefLevel [Byte0]: 52
1696 19:26:23.790227 [Byte1]: 52
1697 19:26:23.794605
1698 19:26:23.794703 Set Vref, RX VrefLevel [Byte0]: 53
1699 19:26:23.797534 [Byte1]: 53
1700 19:26:23.801857
1701 19:26:23.801946 Set Vref, RX VrefLevel [Byte0]: 54
1702 19:26:23.805087 [Byte1]: 54
1703 19:26:23.809765
1704 19:26:23.809845 Set Vref, RX VrefLevel [Byte0]: 55
1705 19:26:23.813457 [Byte1]: 55
1706 19:26:23.817369
1707 19:26:23.817450 Set Vref, RX VrefLevel [Byte0]: 56
1708 19:26:23.820841 [Byte1]: 56
1709 19:26:23.824621
1710 19:26:23.824702 Set Vref, RX VrefLevel [Byte0]: 57
1711 19:26:23.828246 [Byte1]: 57
1712 19:26:23.832621
1713 19:26:23.832701 Set Vref, RX VrefLevel [Byte0]: 58
1714 19:26:23.835751 [Byte1]: 58
1715 19:26:23.840516
1716 19:26:23.840647 Set Vref, RX VrefLevel [Byte0]: 59
1717 19:26:23.843569 [Byte1]: 59
1718 19:26:23.847827
1719 19:26:23.847909 Set Vref, RX VrefLevel [Byte0]: 60
1720 19:26:23.851546 [Byte1]: 60
1721 19:26:23.855924
1722 19:26:23.856004 Set Vref, RX VrefLevel [Byte0]: 61
1723 19:26:23.859031 [Byte1]: 61
1724 19:26:23.863170
1725 19:26:23.863267 Set Vref, RX VrefLevel [Byte0]: 62
1726 19:26:23.866252 [Byte1]: 62
1727 19:26:23.870622
1728 19:26:23.870702 Set Vref, RX VrefLevel [Byte0]: 63
1729 19:26:23.874752 [Byte1]: 63
1730 19:26:23.878441
1731 19:26:23.878522 Set Vref, RX VrefLevel [Byte0]: 64
1732 19:26:23.881516 [Byte1]: 64
1733 19:26:23.886373
1734 19:26:23.886502 Set Vref, RX VrefLevel [Byte0]: 65
1735 19:26:23.889282 [Byte1]: 65
1736 19:26:23.893482
1737 19:26:23.893567 Set Vref, RX VrefLevel [Byte0]: 66
1738 19:26:23.896970 [Byte1]: 66
1739 19:26:23.901258
1740 19:26:23.901338 Set Vref, RX VrefLevel [Byte0]: 67
1741 19:26:23.904807 [Byte1]: 67
1742 19:26:23.909019
1743 19:26:23.909100 Set Vref, RX VrefLevel [Byte0]: 68
1744 19:26:23.912452 [Byte1]: 68
1745 19:26:23.916778
1746 19:26:23.916859 Set Vref, RX VrefLevel [Byte0]: 69
1747 19:26:23.919947 [Byte1]: 69
1748 19:26:23.924475
1749 19:26:23.924556 Set Vref, RX VrefLevel [Byte0]: 70
1750 19:26:23.927447 [Byte1]: 70
1751 19:26:23.931862
1752 19:26:23.931943 Set Vref, RX VrefLevel [Byte0]: 71
1753 19:26:23.935214 [Byte1]: 71
1754 19:26:23.940009
1755 19:26:23.940091 Set Vref, RX VrefLevel [Byte0]: 72
1756 19:26:23.943030 [Byte1]: 72
1757 19:26:23.947211
1758 19:26:23.947292 Set Vref, RX VrefLevel [Byte0]: 73
1759 19:26:23.950896 [Byte1]: 73
1760 19:26:23.955362
1761 19:26:23.955478 Set Vref, RX VrefLevel [Byte0]: 74
1762 19:26:23.958499 [Byte1]: 74
1763 19:26:23.962333
1764 19:26:23.962413 Set Vref, RX VrefLevel [Byte0]: 75
1765 19:26:23.966021 [Byte1]: 75
1766 19:26:23.970189
1767 19:26:23.970269 Set Vref, RX VrefLevel [Byte0]: 76
1768 19:26:23.973775 [Byte1]: 76
1769 19:26:23.978014
1770 19:26:23.978095 Set Vref, RX VrefLevel [Byte0]: 77
1771 19:26:23.981168 [Byte1]: 77
1772 19:26:23.985509
1773 19:26:23.985589 Set Vref, RX VrefLevel [Byte0]: 78
1774 19:26:23.988635 [Byte1]: 78
1775 19:26:23.993419
1776 19:26:23.993500 Set Vref, RX VrefLevel [Byte0]: 79
1777 19:26:23.996495 [Byte1]: 79
1778 19:26:24.000826
1779 19:26:24.000907 Set Vref, RX VrefLevel [Byte0]: 80
1780 19:26:24.003828 [Byte1]: 80
1781 19:26:24.008278
1782 19:26:24.008360 Final RX Vref Byte 0 = 57 to rank0
1783 19:26:24.011424 Final RX Vref Byte 1 = 58 to rank0
1784 19:26:24.015117 Final RX Vref Byte 0 = 57 to rank1
1785 19:26:24.018201 Final RX Vref Byte 1 = 58 to rank1==
1786 19:26:24.021728 Dram Type= 6, Freq= 0, CH_1, rank 0
1787 19:26:24.025374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1788 19:26:24.028759 ==
1789 19:26:24.028839 DQS Delay:
1790 19:26:24.028902 DQS0 = 0, DQS1 = 0
1791 19:26:24.031713 DQM Delay:
1792 19:26:24.031793 DQM0 = 84, DQM1 = 74
1793 19:26:24.035499 DQ Delay:
1794 19:26:24.038753 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =84
1795 19:26:24.038867 DQ4 =84, DQ5 =92, DQ6 =96, DQ7 =80
1796 19:26:24.042385 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =72
1797 19:26:24.045091 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =76
1798 19:26:24.045213
1799 19:26:24.048833
1800 19:26:24.055539 [DQSOSCAuto] RK0, (LSB)MR18= 0x28fd, (MSB)MR19= 0x605, tDQSOscB0 = 410 ps tDQSOscB1 = 399 ps
1801 19:26:24.058518 CH1 RK0: MR19=605, MR18=28FD
1802 19:26:24.065229 CH1_RK0: MR19=0x605, MR18=0x28FD, DQSOSC=399, MR23=63, INC=92, DEC=61
1803 19:26:24.065328
1804 19:26:24.068499 ----->DramcWriteLeveling(PI) begin...
1805 19:26:24.068581 ==
1806 19:26:24.072189 Dram Type= 6, Freq= 0, CH_1, rank 1
1807 19:26:24.075175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1808 19:26:24.075257 ==
1809 19:26:24.078908 Write leveling (Byte 0): 29 => 29
1810 19:26:24.081938 Write leveling (Byte 1): 29 => 29
1811 19:26:24.085158 DramcWriteLeveling(PI) end<-----
1812 19:26:24.085262
1813 19:26:24.085325 ==
1814 19:26:24.088763 Dram Type= 6, Freq= 0, CH_1, rank 1
1815 19:26:24.092041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1816 19:26:24.092125 ==
1817 19:26:24.095580 [Gating] SW mode calibration
1818 19:26:24.102030 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1819 19:26:24.108687 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1820 19:26:24.111994 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1821 19:26:24.115306 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1822 19:26:24.119125 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 19:26:24.125764 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 19:26:24.128792 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 19:26:24.132613 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 19:26:24.139486 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 19:26:24.142228 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 19:26:24.145671 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 19:26:24.152944 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 19:26:24.156101 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 19:26:24.159082 0 7 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1832 19:26:24.166063 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 19:26:24.169404 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 19:26:24.172388 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 19:26:24.176198 0 7 28 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1836 19:26:24.183028 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1837 19:26:24.186119 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1838 19:26:24.189420 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1839 19:26:24.196307 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 19:26:24.199741 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 19:26:24.202786 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 19:26:24.209626 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 19:26:24.212939 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 19:26:24.216066 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 19:26:24.223092 0 9 4 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 1)
1846 19:26:24.226368 0 9 8 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
1847 19:26:24.229808 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1848 19:26:24.236141 0 9 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1849 19:26:24.239877 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1850 19:26:24.243008 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1851 19:26:24.246574 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1852 19:26:24.253347 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1853 19:26:24.256488 0 10 4 | B1->B0 | 3030 2d2d | 0 0 | (0 0) (0 1)
1854 19:26:24.259482 0 10 8 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (0 0)
1855 19:26:24.266890 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 19:26:24.269873 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 19:26:24.273432 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 19:26:24.280041 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 19:26:24.283303 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 19:26:24.286715 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 19:26:24.293432 0 11 4 | B1->B0 | 2828 3a3a | 0 1 | (0 0) (0 0)
1862 19:26:24.296806 0 11 8 | B1->B0 | 3737 4646 | 0 0 | (1 1) (0 0)
1863 19:26:24.300317 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1864 19:26:24.303569 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1865 19:26:24.310366 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1866 19:26:24.313971 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1867 19:26:24.317568 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1868 19:26:24.323754 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1869 19:26:24.327040 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1870 19:26:24.330530 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1871 19:26:24.337270 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 19:26:24.340300 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 19:26:24.343913 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 19:26:24.350466 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 19:26:24.354000 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 19:26:24.356984 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 19:26:24.364366 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 19:26:24.367142 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 19:26:24.370576 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 19:26:24.374273 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 19:26:24.381010 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 19:26:24.383891 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 19:26:24.387456 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 19:26:24.393985 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 19:26:24.397698 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1886 19:26:24.401303 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1887 19:26:24.404438 Total UI for P1: 0, mck2ui 16
1888 19:26:24.408022 best dqsien dly found for B0: ( 0, 14, 4)
1889 19:26:24.411165 Total UI for P1: 0, mck2ui 16
1890 19:26:24.414312 best dqsien dly found for B1: ( 0, 14, 6)
1891 19:26:24.417767 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1892 19:26:24.420692 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1893 19:26:24.421102
1894 19:26:24.424443 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1895 19:26:24.430967 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1896 19:26:24.431667 [Gating] SW calibration Done
1897 19:26:24.432045 ==
1898 19:26:24.434536 Dram Type= 6, Freq= 0, CH_1, rank 1
1899 19:26:24.441109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1900 19:26:24.441759 ==
1901 19:26:24.442298 RX Vref Scan: 0
1902 19:26:24.442872
1903 19:26:24.444216 RX Vref 0 -> 0, step: 1
1904 19:26:24.444794
1905 19:26:24.447423 RX Delay -130 -> 252, step: 16
1906 19:26:24.451092 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1907 19:26:24.454593 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1908 19:26:24.458015 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1909 19:26:24.464531 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1910 19:26:24.468337 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1911 19:26:24.471432 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1912 19:26:24.474546 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1913 19:26:24.478309 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1914 19:26:24.481744 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1915 19:26:24.488001 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1916 19:26:24.491511 iDelay=206, Bit 10, Center 77 (-50 ~ 205) 256
1917 19:26:24.494847 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1918 19:26:24.497845 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1919 19:26:24.501301 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1920 19:26:24.508551 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1921 19:26:24.511488 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1922 19:26:24.512075 ==
1923 19:26:24.514670 Dram Type= 6, Freq= 0, CH_1, rank 1
1924 19:26:24.518281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1925 19:26:24.518918 ==
1926 19:26:24.521685 DQS Delay:
1927 19:26:24.522294 DQS0 = 0, DQS1 = 0
1928 19:26:24.522856 DQM Delay:
1929 19:26:24.524896 DQM0 = 81, DQM1 = 77
1930 19:26:24.525529 DQ Delay:
1931 19:26:24.528429 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1932 19:26:24.531369 DQ4 =85, DQ5 =93, DQ6 =85, DQ7 =77
1933 19:26:24.535197 DQ8 =61, DQ9 =69, DQ10 =77, DQ11 =69
1934 19:26:24.538109 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1935 19:26:24.538602
1936 19:26:24.539128
1937 19:26:24.539707 ==
1938 19:26:24.541643 Dram Type= 6, Freq= 0, CH_1, rank 1
1939 19:26:24.544916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1940 19:26:24.548395 ==
1941 19:26:24.548806
1942 19:26:24.549129
1943 19:26:24.549490 TX Vref Scan disable
1944 19:26:24.552070 == TX Byte 0 ==
1945 19:26:24.554872 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1946 19:26:24.558517 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1947 19:26:24.561650 == TX Byte 1 ==
1948 19:26:24.565073 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1949 19:26:24.568535 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1950 19:26:24.569368 ==
1951 19:26:24.572019 Dram Type= 6, Freq= 0, CH_1, rank 1
1952 19:26:24.578841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1953 19:26:24.579477 ==
1954 19:26:24.590138 TX Vref=22, minBit 1, minWin=27, winSum=443
1955 19:26:24.593565 TX Vref=24, minBit 9, minWin=27, winSum=445
1956 19:26:24.596958 TX Vref=26, minBit 0, minWin=28, winSum=450
1957 19:26:24.600118 TX Vref=28, minBit 3, minWin=27, winSum=449
1958 19:26:24.603425 TX Vref=30, minBit 0, minWin=28, winSum=452
1959 19:26:24.610490 TX Vref=32, minBit 0, minWin=28, winSum=452
1960 19:26:24.613937 [TxChooseVref] Worse bit 0, Min win 28, Win sum 452, Final Vref 30
1961 19:26:24.614490
1962 19:26:24.616680 Final TX Range 1 Vref 30
1963 19:26:24.617191
1964 19:26:24.617727 ==
1965 19:26:24.620485 Dram Type= 6, Freq= 0, CH_1, rank 1
1966 19:26:24.623453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1967 19:26:24.623955 ==
1968 19:26:24.624455
1969 19:26:24.627254
1970 19:26:24.627747 TX Vref Scan disable
1971 19:26:24.630340 == TX Byte 0 ==
1972 19:26:24.633738 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1973 19:26:24.637417 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1974 19:26:24.640506 == TX Byte 1 ==
1975 19:26:24.643970 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1976 19:26:24.646877 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1977 19:26:24.647389
1978 19:26:24.650735 [DATLAT]
1979 19:26:24.651237 Freq=800, CH1 RK1
1980 19:26:24.651733
1981 19:26:24.653714 DATLAT Default: 0xa
1982 19:26:24.654211 0, 0xFFFF, sum = 0
1983 19:26:24.657308 1, 0xFFFF, sum = 0
1984 19:26:24.657870 2, 0xFFFF, sum = 0
1985 19:26:24.660179 3, 0xFFFF, sum = 0
1986 19:26:24.660718 4, 0xFFFF, sum = 0
1987 19:26:24.663841 5, 0xFFFF, sum = 0
1988 19:26:24.664388 6, 0xFFFF, sum = 0
1989 19:26:24.667368 7, 0xFFFF, sum = 0
1990 19:26:24.667941 8, 0xFFFF, sum = 0
1991 19:26:24.670645 9, 0x0, sum = 1
1992 19:26:24.671146 10, 0x0, sum = 2
1993 19:26:24.674135 11, 0x0, sum = 3
1994 19:26:24.674696 12, 0x0, sum = 4
1995 19:26:24.677578 best_step = 10
1996 19:26:24.678067
1997 19:26:24.678510 ==
1998 19:26:24.680724 Dram Type= 6, Freq= 0, CH_1, rank 1
1999 19:26:24.684061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2000 19:26:24.684584 ==
2001 19:26:24.685079 RX Vref Scan: 0
2002 19:26:24.687222
2003 19:26:24.687706 RX Vref 0 -> 0, step: 1
2004 19:26:24.688198
2005 19:26:24.690816 RX Delay -111 -> 252, step: 8
2006 19:26:24.694477 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
2007 19:26:24.700703 iDelay=209, Bit 1, Center 76 (-39 ~ 192) 232
2008 19:26:24.703960 iDelay=209, Bit 2, Center 68 (-47 ~ 184) 232
2009 19:26:24.707702 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
2010 19:26:24.710725 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
2011 19:26:24.714340 iDelay=209, Bit 5, Center 92 (-23 ~ 208) 232
2012 19:26:24.720931 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2013 19:26:24.724614 iDelay=209, Bit 7, Center 76 (-39 ~ 192) 232
2014 19:26:24.727767 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2015 19:26:24.731020 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
2016 19:26:24.734396 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
2017 19:26:24.740685 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2018 19:26:24.744543 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
2019 19:26:24.747472 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
2020 19:26:24.750936 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2021 19:26:24.754582 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
2022 19:26:24.757670 ==
2023 19:26:24.758186 Dram Type= 6, Freq= 0, CH_1, rank 1
2024 19:26:24.764887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2025 19:26:24.765621 ==
2026 19:26:24.766224 DQS Delay:
2027 19:26:24.767681 DQS0 = 0, DQS1 = 0
2028 19:26:24.768306 DQM Delay:
2029 19:26:24.771404 DQM0 = 80, DQM1 = 75
2030 19:26:24.772038 DQ Delay:
2031 19:26:24.774611 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
2032 19:26:24.778071 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
2033 19:26:24.781020 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
2034 19:26:24.784454 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
2035 19:26:24.784789
2036 19:26:24.785094
2037 19:26:24.791199 [DQSOSCAuto] RK1, (LSB)MR18= 0x252f, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 400 ps
2038 19:26:24.794691 CH1 RK1: MR19=606, MR18=252F
2039 19:26:24.801298 CH1_RK1: MR19=0x606, MR18=0x252F, DQSOSC=397, MR23=63, INC=93, DEC=62
2040 19:26:24.804151 [RxdqsGatingPostProcess] freq 800
2041 19:26:24.807611 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2042 19:26:24.811089 Pre-setting of DQS Precalculation
2043 19:26:24.817684 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2044 19:26:24.824803 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2045 19:26:24.831266 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2046 19:26:24.831354
2047 19:26:24.831441
2048 19:26:24.834377 [Calibration Summary] 1600 Mbps
2049 19:26:24.834464 CH 0, Rank 0
2050 19:26:24.838102 SW Impedance : PASS
2051 19:26:24.840970 DUTY Scan : NO K
2052 19:26:24.841056 ZQ Calibration : PASS
2053 19:26:24.844709 Jitter Meter : NO K
2054 19:26:24.848414 CBT Training : PASS
2055 19:26:24.848496 Write leveling : PASS
2056 19:26:24.851406 RX DQS gating : PASS
2057 19:26:24.854318 RX DQ/DQS(RDDQC) : PASS
2058 19:26:24.854400 TX DQ/DQS : PASS
2059 19:26:24.857933 RX DATLAT : PASS
2060 19:26:24.858040 RX DQ/DQS(Engine): PASS
2061 19:26:24.861198 TX OE : NO K
2062 19:26:24.861292 All Pass.
2063 19:26:24.861357
2064 19:26:24.864762 CH 0, Rank 1
2065 19:26:24.864843 SW Impedance : PASS
2066 19:26:24.868230 DUTY Scan : NO K
2067 19:26:24.871350 ZQ Calibration : PASS
2068 19:26:24.871432 Jitter Meter : NO K
2069 19:26:24.874438 CBT Training : PASS
2070 19:26:24.878290 Write leveling : PASS
2071 19:26:24.878371 RX DQS gating : PASS
2072 19:26:24.881758 RX DQ/DQS(RDDQC) : PASS
2073 19:26:24.884521 TX DQ/DQS : PASS
2074 19:26:24.884603 RX DATLAT : PASS
2075 19:26:24.888367 RX DQ/DQS(Engine): PASS
2076 19:26:24.888474 TX OE : NO K
2077 19:26:24.891412 All Pass.
2078 19:26:24.891512
2079 19:26:24.891601 CH 1, Rank 0
2080 19:26:24.894838 SW Impedance : PASS
2081 19:26:24.894920 DUTY Scan : NO K
2082 19:26:24.898255 ZQ Calibration : PASS
2083 19:26:24.901314 Jitter Meter : NO K
2084 19:26:24.901396 CBT Training : PASS
2085 19:26:24.904753 Write leveling : PASS
2086 19:26:24.908715 RX DQS gating : PASS
2087 19:26:24.908819 RX DQ/DQS(RDDQC) : PASS
2088 19:26:24.911465 TX DQ/DQS : PASS
2089 19:26:24.915162 RX DATLAT : PASS
2090 19:26:24.915273 RX DQ/DQS(Engine): PASS
2091 19:26:24.918015 TX OE : NO K
2092 19:26:24.918096 All Pass.
2093 19:26:24.918158
2094 19:26:24.921460 CH 1, Rank 1
2095 19:26:24.921562 SW Impedance : PASS
2096 19:26:24.924919 DUTY Scan : NO K
2097 19:26:24.928448 ZQ Calibration : PASS
2098 19:26:24.928555 Jitter Meter : NO K
2099 19:26:24.931570 CBT Training : PASS
2100 19:26:24.931650 Write leveling : PASS
2101 19:26:24.934868 RX DQS gating : PASS
2102 19:26:24.938346 RX DQ/DQS(RDDQC) : PASS
2103 19:26:24.938451 TX DQ/DQS : PASS
2104 19:26:24.941402 RX DATLAT : PASS
2105 19:26:24.945080 RX DQ/DQS(Engine): PASS
2106 19:26:24.945162 TX OE : NO K
2107 19:26:24.948722 All Pass.
2108 19:26:24.948819
2109 19:26:24.948914 DramC Write-DBI off
2110 19:26:24.951715 PER_BANK_REFRESH: Hybrid Mode
2111 19:26:24.951795 TX_TRACKING: ON
2112 19:26:24.954767 [GetDramInforAfterCalByMRR] Vendor 6.
2113 19:26:24.962085 [GetDramInforAfterCalByMRR] Revision 606.
2114 19:26:24.965166 [GetDramInforAfterCalByMRR] Revision 2 0.
2115 19:26:24.965284 MR0 0x3b3b
2116 19:26:24.965381 MR8 0x5151
2117 19:26:24.968186 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2118 19:26:24.968292
2119 19:26:24.971473 MR0 0x3b3b
2120 19:26:24.971594 MR8 0x5151
2121 19:26:24.975126 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2122 19:26:24.975234
2123 19:26:24.984992 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2124 19:26:24.988457 [FAST_K] Save calibration result to emmc
2125 19:26:24.991560 [FAST_K] Save calibration result to emmc
2126 19:26:24.995287 dram_init: config_dvfs: 1
2127 19:26:24.998449 dramc_set_vcore_voltage set vcore to 662500
2128 19:26:25.001983 Read voltage for 1200, 2
2129 19:26:25.002062 Vio18 = 0
2130 19:26:25.002125 Vcore = 662500
2131 19:26:25.002183 Vdram = 0
2132 19:26:25.005648 Vddq = 0
2133 19:26:25.005728 Vmddr = 0
2134 19:26:25.012083 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2135 19:26:25.015230 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2136 19:26:25.018713 MEM_TYPE=3, freq_sel=15
2137 19:26:25.021895 sv_algorithm_assistance_LP4_1600
2138 19:26:25.025244 ============ PULL DRAM RESETB DOWN ============
2139 19:26:25.028824 ========== PULL DRAM RESETB DOWN end =========
2140 19:26:25.035324 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2141 19:26:25.038842 ===================================
2142 19:26:25.038923 LPDDR4 DRAM CONFIGURATION
2143 19:26:25.041971 ===================================
2144 19:26:25.045197 EX_ROW_EN[0] = 0x0
2145 19:26:25.045300 EX_ROW_EN[1] = 0x0
2146 19:26:25.048765 LP4Y_EN = 0x0
2147 19:26:25.048845 WORK_FSP = 0x0
2148 19:26:25.051924 WL = 0x4
2149 19:26:25.052004 RL = 0x4
2150 19:26:25.055185 BL = 0x2
2151 19:26:25.058686 RPST = 0x0
2152 19:26:25.058766 RD_PRE = 0x0
2153 19:26:25.062195 WR_PRE = 0x1
2154 19:26:25.062274 WR_PST = 0x0
2155 19:26:25.065375 DBI_WR = 0x0
2156 19:26:25.065454 DBI_RD = 0x0
2157 19:26:25.068963 OTF = 0x1
2158 19:26:25.072041 ===================================
2159 19:26:25.075515 ===================================
2160 19:26:25.075597 ANA top config
2161 19:26:25.078646 ===================================
2162 19:26:25.082103 DLL_ASYNC_EN = 0
2163 19:26:25.082208 ALL_SLAVE_EN = 0
2164 19:26:25.085822 NEW_RANK_MODE = 1
2165 19:26:25.088904 DLL_IDLE_MODE = 1
2166 19:26:25.092248 LP45_APHY_COMB_EN = 1
2167 19:26:25.095507 TX_ODT_DIS = 1
2168 19:26:25.095588 NEW_8X_MODE = 1
2169 19:26:25.099288 ===================================
2170 19:26:25.102109 ===================================
2171 19:26:25.105728 data_rate = 2400
2172 19:26:25.108831 CKR = 1
2173 19:26:25.112221 DQ_P2S_RATIO = 8
2174 19:26:25.115724 ===================================
2175 19:26:25.118850 CA_P2S_RATIO = 8
2176 19:26:25.118945 DQ_CA_OPEN = 0
2177 19:26:25.122293 DQ_SEMI_OPEN = 0
2178 19:26:25.126232 CA_SEMI_OPEN = 0
2179 19:26:25.129408 CA_FULL_RATE = 0
2180 19:26:25.132291 DQ_CKDIV4_EN = 0
2181 19:26:25.136046 CA_CKDIV4_EN = 0
2182 19:26:25.136143 CA_PREDIV_EN = 0
2183 19:26:25.139371 PH8_DLY = 17
2184 19:26:25.142598 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2185 19:26:25.146161 DQ_AAMCK_DIV = 4
2186 19:26:25.149598 CA_AAMCK_DIV = 4
2187 19:26:25.149705 CA_ADMCK_DIV = 4
2188 19:26:25.153047 DQ_TRACK_CA_EN = 0
2189 19:26:25.156096 CA_PICK = 1200
2190 19:26:25.159731 CA_MCKIO = 1200
2191 19:26:25.162873 MCKIO_SEMI = 0
2192 19:26:25.166262 PLL_FREQ = 2366
2193 19:26:25.169861 DQ_UI_PI_RATIO = 32
2194 19:26:25.169944 CA_UI_PI_RATIO = 0
2195 19:26:25.172950 ===================================
2196 19:26:25.176010 ===================================
2197 19:26:25.179800 memory_type:LPDDR4
2198 19:26:25.183040 GP_NUM : 10
2199 19:26:25.183141 SRAM_EN : 1
2200 19:26:25.186040 MD32_EN : 0
2201 19:26:25.189321 ===================================
2202 19:26:25.193017 [ANA_INIT] >>>>>>>>>>>>>>
2203 19:26:25.196405 <<<<<< [CONFIGURE PHASE]: ANA_TX
2204 19:26:25.199755 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2205 19:26:25.203210 ===================================
2206 19:26:25.203287 data_rate = 2400,PCW = 0X5b00
2207 19:26:25.206262 ===================================
2208 19:26:25.209689 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2209 19:26:25.216263 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2210 19:26:25.223246 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2211 19:26:25.226878 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2212 19:26:25.229975 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2213 19:26:25.232962 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2214 19:26:25.236782 [ANA_INIT] flow start
2215 19:26:25.236877 [ANA_INIT] PLL >>>>>>>>
2216 19:26:25.239713 [ANA_INIT] PLL <<<<<<<<
2217 19:26:25.243408 [ANA_INIT] MIDPI >>>>>>>>
2218 19:26:25.243504 [ANA_INIT] MIDPI <<<<<<<<
2219 19:26:25.247060 [ANA_INIT] DLL >>>>>>>>
2220 19:26:25.249941 [ANA_INIT] DLL <<<<<<<<
2221 19:26:25.250038 [ANA_INIT] flow end
2222 19:26:25.256873 ============ LP4 DIFF to SE enter ============
2223 19:26:25.260559 ============ LP4 DIFF to SE exit ============
2224 19:26:25.263816 [ANA_INIT] <<<<<<<<<<<<<
2225 19:26:25.263941 [Flow] Enable top DCM control >>>>>
2226 19:26:25.266799 [Flow] Enable top DCM control <<<<<
2227 19:26:25.270554 Enable DLL master slave shuffle
2228 19:26:25.276824 ==============================================================
2229 19:26:25.280533 Gating Mode config
2230 19:26:25.283977 ==============================================================
2231 19:26:25.286922 Config description:
2232 19:26:25.297180 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2233 19:26:25.303615 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2234 19:26:25.307276 SELPH_MODE 0: By rank 1: By Phase
2235 19:26:25.314007 ==============================================================
2236 19:26:25.317367 GAT_TRACK_EN = 1
2237 19:26:25.317911 RX_GATING_MODE = 2
2238 19:26:25.320486 RX_GATING_TRACK_MODE = 2
2239 19:26:25.324225 SELPH_MODE = 1
2240 19:26:25.327369 PICG_EARLY_EN = 1
2241 19:26:25.330655 VALID_LAT_VALUE = 1
2242 19:26:25.337571 ==============================================================
2243 19:26:25.340699 Enter into Gating configuration >>>>
2244 19:26:25.344276 Exit from Gating configuration <<<<
2245 19:26:25.347502 Enter into DVFS_PRE_config >>>>>
2246 19:26:25.357925 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2247 19:26:25.361103 Exit from DVFS_PRE_config <<<<<
2248 19:26:25.364259 Enter into PICG configuration >>>>
2249 19:26:25.367844 Exit from PICG configuration <<<<
2250 19:26:25.371109 [RX_INPUT] configuration >>>>>
2251 19:26:25.371210 [RX_INPUT] configuration <<<<<
2252 19:26:25.377870 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2253 19:26:25.384046 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2254 19:26:25.387812 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2255 19:26:25.394296 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2256 19:26:25.401059 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2257 19:26:25.407595 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2258 19:26:25.411355 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2259 19:26:25.414431 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2260 19:26:25.418052 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2261 19:26:25.424627 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2262 19:26:25.427667 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2263 19:26:25.431500 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2264 19:26:25.434639 ===================================
2265 19:26:25.438282 LPDDR4 DRAM CONFIGURATION
2266 19:26:25.441558 ===================================
2267 19:26:25.444751 EX_ROW_EN[0] = 0x0
2268 19:26:25.444855 EX_ROW_EN[1] = 0x0
2269 19:26:25.447730 LP4Y_EN = 0x0
2270 19:26:25.447833 WORK_FSP = 0x0
2271 19:26:25.451312 WL = 0x4
2272 19:26:25.451422 RL = 0x4
2273 19:26:25.454761 BL = 0x2
2274 19:26:25.454870 RPST = 0x0
2275 19:26:25.458021 RD_PRE = 0x0
2276 19:26:25.458119 WR_PRE = 0x1
2277 19:26:25.461659 WR_PST = 0x0
2278 19:26:25.461755 DBI_WR = 0x0
2279 19:26:25.464921 DBI_RD = 0x0
2280 19:26:25.465018 OTF = 0x1
2281 19:26:25.468466 ===================================
2282 19:26:25.471796 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2283 19:26:25.478325 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2284 19:26:25.481288 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2285 19:26:25.484854 ===================================
2286 19:26:25.488070 LPDDR4 DRAM CONFIGURATION
2287 19:26:25.491922 ===================================
2288 19:26:25.492033 EX_ROW_EN[0] = 0x10
2289 19:26:25.495197 EX_ROW_EN[1] = 0x0
2290 19:26:25.495306 LP4Y_EN = 0x0
2291 19:26:25.498175 WORK_FSP = 0x0
2292 19:26:25.498269 WL = 0x4
2293 19:26:25.501575 RL = 0x4
2294 19:26:25.501685 BL = 0x2
2295 19:26:25.505398 RPST = 0x0
2296 19:26:25.508478 RD_PRE = 0x0
2297 19:26:25.508586 WR_PRE = 0x1
2298 19:26:25.511365 WR_PST = 0x0
2299 19:26:25.511465 DBI_WR = 0x0
2300 19:26:25.514910 DBI_RD = 0x0
2301 19:26:25.515006 OTF = 0x1
2302 19:26:25.518726 ===================================
2303 19:26:25.525357 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2304 19:26:25.525427 ==
2305 19:26:25.528377 Dram Type= 6, Freq= 0, CH_0, rank 0
2306 19:26:25.531915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2307 19:26:25.532011 ==
2308 19:26:25.535094 [Duty_Offset_Calibration]
2309 19:26:25.535188 B0:2 B1:-1 CA:1
2310 19:26:25.538950
2311 19:26:25.541885 [DutyScan_Calibration_Flow] k_type=0
2312 19:26:25.549114
2313 19:26:25.549217 ==CLK 0==
2314 19:26:25.551760 Final CLK duty delay cell = -4
2315 19:26:25.555222 [-4] MAX Duty = 5000%(X100), DQS PI = 4
2316 19:26:25.558818 [-4] MIN Duty = 4875%(X100), DQS PI = 30
2317 19:26:25.561839 [-4] AVG Duty = 4937%(X100)
2318 19:26:25.561941
2319 19:26:25.565623 CH0 CLK Duty spec in!! Max-Min= 125%
2320 19:26:25.568821 [DutyScan_Calibration_Flow] ====Done====
2321 19:26:25.568922
2322 19:26:25.572155 [DutyScan_Calibration_Flow] k_type=1
2323 19:26:25.586862
2324 19:26:25.586966 ==DQS 0 ==
2325 19:26:25.590128 Final DQS duty delay cell = -4
2326 19:26:25.593081 [-4] MAX Duty = 5000%(X100), DQS PI = 54
2327 19:26:25.596782 [-4] MIN Duty = 4876%(X100), DQS PI = 12
2328 19:26:25.600164 [-4] AVG Duty = 4938%(X100)
2329 19:26:25.600266
2330 19:26:25.600356 ==DQS 1 ==
2331 19:26:25.603757 Final DQS duty delay cell = -4
2332 19:26:25.606613 [-4] MAX Duty = 5124%(X100), DQS PI = 18
2333 19:26:25.610375 [-4] MIN Duty = 5000%(X100), DQS PI = 50
2334 19:26:25.613611 [-4] AVG Duty = 5062%(X100)
2335 19:26:25.613687
2336 19:26:25.617084 CH0 DQS 0 Duty spec in!! Max-Min= 124%
2337 19:26:25.617182
2338 19:26:25.620114 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2339 19:26:25.623326 [DutyScan_Calibration_Flow] ====Done====
2340 19:26:25.623426
2341 19:26:25.626960 [DutyScan_Calibration_Flow] k_type=3
2342 19:26:25.644137
2343 19:26:25.644241 ==DQM 0 ==
2344 19:26:25.647406 Final DQM duty delay cell = 0
2345 19:26:25.650367 [0] MAX Duty = 5000%(X100), DQS PI = 54
2346 19:26:25.653741 [0] MIN Duty = 4907%(X100), DQS PI = 2
2347 19:26:25.653840 [0] AVG Duty = 4953%(X100)
2348 19:26:25.653927
2349 19:26:25.657271 ==DQM 1 ==
2350 19:26:25.660928 Final DQM duty delay cell = 0
2351 19:26:25.664397 [0] MAX Duty = 5156%(X100), DQS PI = 62
2352 19:26:25.667344 [0] MIN Duty = 4969%(X100), DQS PI = 10
2353 19:26:25.667443 [0] AVG Duty = 5062%(X100)
2354 19:26:25.667531
2355 19:26:25.671294 CH0 DQM 0 Duty spec in!! Max-Min= 93%
2356 19:26:25.674221
2357 19:26:25.677574 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2358 19:26:25.681123 [DutyScan_Calibration_Flow] ====Done====
2359 19:26:25.681305
2360 19:26:25.684082 [DutyScan_Calibration_Flow] k_type=2
2361 19:26:25.699584
2362 19:26:25.699697 ==DQ 0 ==
2363 19:26:25.702983 Final DQ duty delay cell = -4
2364 19:26:25.706104 [-4] MAX Duty = 5062%(X100), DQS PI = 54
2365 19:26:25.709679 [-4] MIN Duty = 4875%(X100), DQS PI = 18
2366 19:26:25.713266 [-4] AVG Duty = 4968%(X100)
2367 19:26:25.713368
2368 19:26:25.713457 ==DQ 1 ==
2369 19:26:25.716198 Final DQ duty delay cell = 0
2370 19:26:25.719454 [0] MAX Duty = 5031%(X100), DQS PI = 18
2371 19:26:25.723137 [0] MIN Duty = 4907%(X100), DQS PI = 46
2372 19:26:25.723251 [0] AVG Duty = 4969%(X100)
2373 19:26:25.726440
2374 19:26:25.729738 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2375 19:26:25.729845
2376 19:26:25.732963 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2377 19:26:25.736187 [DutyScan_Calibration_Flow] ====Done====
2378 19:26:25.736292 ==
2379 19:26:25.739855 Dram Type= 6, Freq= 0, CH_1, rank 0
2380 19:26:25.742907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2381 19:26:25.743014 ==
2382 19:26:25.746879 [Duty_Offset_Calibration]
2383 19:26:25.746977 B0:1 B1:1 CA:2
2384 19:26:25.747069
2385 19:26:25.749730 [DutyScan_Calibration_Flow] k_type=0
2386 19:26:25.759995
2387 19:26:25.760107 ==CLK 0==
2388 19:26:25.763646 Final CLK duty delay cell = 0
2389 19:26:25.766610 [0] MAX Duty = 5156%(X100), DQS PI = 24
2390 19:26:25.770282 [0] MIN Duty = 4938%(X100), DQS PI = 40
2391 19:26:25.770382 [0] AVG Duty = 5047%(X100)
2392 19:26:25.770475
2393 19:26:25.773089 CH1 CLK Duty spec in!! Max-Min= 218%
2394 19:26:25.779745 [DutyScan_Calibration_Flow] ====Done====
2395 19:26:25.779847
2396 19:26:25.783154 [DutyScan_Calibration_Flow] k_type=1
2397 19:26:25.799040
2398 19:26:25.799146 ==DQS 0 ==
2399 19:26:25.802908 Final DQS duty delay cell = 0
2400 19:26:25.805574 [0] MAX Duty = 5031%(X100), DQS PI = 18
2401 19:26:25.809043 [0] MIN Duty = 4844%(X100), DQS PI = 48
2402 19:26:25.809147 [0] AVG Duty = 4937%(X100)
2403 19:26:25.812346
2404 19:26:25.812446 ==DQS 1 ==
2405 19:26:25.815991 Final DQS duty delay cell = 0
2406 19:26:25.819317 [0] MAX Duty = 5062%(X100), DQS PI = 36
2407 19:26:25.822397 [0] MIN Duty = 4907%(X100), DQS PI = 8
2408 19:26:25.822496 [0] AVG Duty = 4984%(X100)
2409 19:26:25.825812
2410 19:26:25.829117 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2411 19:26:25.829221
2412 19:26:25.832653 CH1 DQS 1 Duty spec in!! Max-Min= 155%
2413 19:26:25.835767 [DutyScan_Calibration_Flow] ====Done====
2414 19:26:25.835865
2415 19:26:25.839093 [DutyScan_Calibration_Flow] k_type=3
2416 19:26:25.855415
2417 19:26:25.855520 ==DQM 0 ==
2418 19:26:25.859198 Final DQM duty delay cell = 0
2419 19:26:25.862187 [0] MAX Duty = 5093%(X100), DQS PI = 16
2420 19:26:25.865896 [0] MIN Duty = 4875%(X100), DQS PI = 50
2421 19:26:25.865994 [0] AVG Duty = 4984%(X100)
2422 19:26:25.868811
2423 19:26:25.868906 ==DQM 1 ==
2424 19:26:25.872587 Final DQM duty delay cell = 0
2425 19:26:25.875627 [0] MAX Duty = 5125%(X100), DQS PI = 0
2426 19:26:25.879117 [0] MIN Duty = 4938%(X100), DQS PI = 22
2427 19:26:25.879213 [0] AVG Duty = 5031%(X100)
2428 19:26:25.879299
2429 19:26:28.784199 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2430 19:26:28.784872
2431 19:26:28.785462 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2432 19:26:28.785894 [DutyScan_Calibration_Flow] ====Done====
2433 19:26:28.786377
2434 19:26:28.786981 [DutyScan_Calibration_Flow] k_type=2
2435 19:26:28.787545
2436 19:26:28.788035 ==DQ 0 ==
2437 19:26:28.788618 Final DQ duty delay cell = 0
2438 19:26:28.789164 [0] MAX Duty = 5124%(X100), DQS PI = 18
2439 19:26:28.789668 [0] MIN Duty = 4938%(X100), DQS PI = 50
2440 19:26:28.789895 [0] AVG Duty = 5031%(X100)
2441 19:26:28.789979
2442 19:26:28.790065 ==DQ 1 ==
2443 19:26:28.790152 Final DQ duty delay cell = 0
2444 19:26:28.790239 [0] MAX Duty = 5093%(X100), DQS PI = 8
2445 19:26:28.790340 [0] MIN Duty = 5000%(X100), DQS PI = 4
2446 19:26:28.790430 [0] AVG Duty = 5046%(X100)
2447 19:26:28.790528
2448 19:26:28.790613 CH1 DQ 0 Duty spec in!! Max-Min= 186%
2449 19:26:28.790717
2450 19:26:28.790808 CH1 DQ 1 Duty spec in!! Max-Min= 93%
2451 19:26:28.790901 [DutyScan_Calibration_Flow] ====Done====
2452 19:26:28.790993 nWR fixed to 30
2453 19:26:28.791089 [ModeRegInit_LP4] CH0 RK0
2454 19:26:28.791171 [ModeRegInit_LP4] CH0 RK1
2455 19:26:28.791259 [ModeRegInit_LP4] CH1 RK0
2456 19:26:28.791342 [ModeRegInit_LP4] CH1 RK1
2457 19:26:28.791431 match AC timing 7
2458 19:26:28.791516 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2459 19:26:28.791604 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2460 19:26:28.791700 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2461 19:26:28.791785 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2462 19:26:28.791897 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2463 19:26:28.792009 ==
2464 19:26:28.792107 Dram Type= 6, Freq= 0, CH_0, rank 0
2465 19:26:28.792217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2466 19:26:28.792314 ==
2467 19:26:28.792414 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2468 19:26:28.792534 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2469 19:26:28.792640 [CA 0] Center 40 (10~71) winsize 62
2470 19:26:28.792737 [CA 1] Center 39 (9~70) winsize 62
2471 19:26:28.792832 [CA 2] Center 36 (6~67) winsize 62
2472 19:26:28.792945 [CA 3] Center 36 (5~67) winsize 63
2473 19:26:28.793041 [CA 4] Center 35 (5~65) winsize 61
2474 19:26:28.793134 [CA 5] Center 34 (4~64) winsize 61
2475 19:26:28.793225
2476 19:26:28.793321 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2477 19:26:28.793410
2478 19:26:28.793493 [CATrainingPosCal] consider 1 rank data
2479 19:26:28.793580 u2DelayCellTimex100 = 270/100 ps
2480 19:26:28.793663 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2481 19:26:28.793751 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2482 19:26:28.793834 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2483 19:26:28.793921 CA3 delay=36 (5~67),Diff = 2 PI (9 cell)
2484 19:26:28.794003 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2485 19:26:28.794090 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2486 19:26:28.794191
2487 19:26:28.794277 CA PerBit enable=1, Macro0, CA PI delay=34
2488 19:26:28.794359
2489 19:26:28.794441 [CBTSetCACLKResult] CA Dly = 34
2490 19:26:28.794532 CS Dly: 7 (0~38)
2491 19:26:28.794615 ==
2492 19:26:28.794697 Dram Type= 6, Freq= 0, CH_0, rank 1
2493 19:26:28.794784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2494 19:26:28.794867 ==
2495 19:26:28.794955 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2496 19:26:28.795039 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2497 19:26:28.795125 [CA 0] Center 39 (9~70) winsize 62
2498 19:26:28.795208 [CA 1] Center 40 (10~70) winsize 61
2499 19:26:28.795291 [CA 2] Center 36 (6~67) winsize 62
2500 19:26:28.795373 [CA 3] Center 36 (5~67) winsize 63
2501 19:26:28.795457 [CA 4] Center 34 (4~65) winsize 62
2502 19:26:28.795548 [CA 5] Center 34 (4~64) winsize 61
2503 19:26:28.795641
2504 19:26:28.795728 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2505 19:26:28.795809
2506 19:26:28.795894 [CATrainingPosCal] consider 2 rank data
2507 19:26:28.795980 u2DelayCellTimex100 = 270/100 ps
2508 19:26:28.796063 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2509 19:26:28.796147 CA1 delay=40 (10~70),Diff = 6 PI (28 cell)
2510 19:26:28.796234 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2511 19:26:28.796316 CA3 delay=36 (5~67),Diff = 2 PI (9 cell)
2512 19:26:28.796401 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2513 19:26:28.796483 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2514 19:26:28.796568
2515 19:26:28.796651 CA PerBit enable=1, Macro0, CA PI delay=34
2516 19:26:28.796736
2517 19:26:28.796820 [CBTSetCACLKResult] CA Dly = 34
2518 19:26:28.796904 CS Dly: 8 (0~41)
2519 19:26:28.796994
2520 19:26:28.797076 ----->DramcWriteLeveling(PI) begin...
2521 19:26:28.797167 ==
2522 19:26:28.797258 Dram Type= 6, Freq= 0, CH_0, rank 0
2523 19:26:28.797347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2524 19:26:28.797440 ==
2525 19:26:28.797522 Write leveling (Byte 0): 31 => 31
2526 19:26:28.797612 Write leveling (Byte 1): 29 => 29
2527 19:26:28.797695 DramcWriteLeveling(PI) end<-----
2528 19:26:28.797778
2529 19:26:28.797859 ==
2530 19:26:28.797940 Dram Type= 6, Freq= 0, CH_0, rank 0
2531 19:26:28.798028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2532 19:26:28.798110 ==
2533 19:26:28.798195 [Gating] SW mode calibration
2534 19:26:28.798279 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2535 19:26:28.798368 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2536 19:26:28.798452 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2537 19:26:28.798553 0 15 4 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
2538 19:26:28.798639 0 15 8 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
2539 19:26:28.798721 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2540 19:26:28.798806 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2541 19:26:28.798893 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2542 19:26:28.798983 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2543 19:26:28.799066 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2544 19:26:28.799151 1 0 0 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 1)
2545 19:26:28.799233 1 0 4 | B1->B0 | 2929 2323 | 0 0 | (0 0) (1 0)
2546 19:26:28.799321 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2547 19:26:28.799406 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2548 19:26:28.799488 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2549 19:26:28.799575 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2550 19:26:28.799657 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2551 19:26:28.799970 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2552 19:26:28.800071 1 1 0 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
2553 19:26:28.800161 1 1 4 | B1->B0 | 3d3d 4545 | 0 0 | (0 0) (0 0)
2554 19:26:28.800248 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2555 19:26:28.800331 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2556 19:26:28.800414 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2557 19:26:28.800504 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2558 19:26:28.800586 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2559 19:26:28.800689 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2560 19:26:28.800772 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2561 19:26:28.800862 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2562 19:26:28.800945 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 19:26:28.801035 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 19:26:28.801118 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 19:26:28.801203 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 19:26:28.801298 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 19:26:28.801380 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 19:26:28.801470 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 19:26:28.801553 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 19:26:28.801635 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 19:26:28.801722 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 19:26:28.801804 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 19:26:28.801889 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 19:26:28.801971 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 19:26:28.802057 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2576 19:26:28.802140 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2577 19:26:28.802235 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2578 19:26:28.802323 Total UI for P1: 0, mck2ui 16
2579 19:26:28.802406 best dqsien dly found for B0: ( 1, 4, 0)
2580 19:26:28.802494 Total UI for P1: 0, mck2ui 16
2581 19:26:28.802577 best dqsien dly found for B1: ( 1, 4, 2)
2582 19:26:28.802676 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2583 19:26:28.802760 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2584 19:26:28.802843
2585 19:26:28.802932 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2586 19:26:28.803015 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2587 19:26:28.803102 [Gating] SW calibration Done
2588 19:26:28.803184 ==
2589 19:26:28.803271 Dram Type= 6, Freq= 0, CH_0, rank 0
2590 19:26:28.803355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2591 19:26:28.803437 ==
2592 19:26:28.803524 RX Vref Scan: 0
2593 19:26:28.803605
2594 19:26:28.803694 RX Vref 0 -> 0, step: 1
2595 19:26:28.803776
2596 19:26:28.803866 RX Delay -40 -> 252, step: 8
2597 19:26:28.803948 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2598 19:26:28.804034 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2599 19:26:28.804121 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2600 19:26:28.804203 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2601 19:26:28.804293 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2602 19:26:28.804376 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2603 19:26:28.804460 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2604 19:26:28.804543 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2605 19:26:28.804625 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2606 19:26:28.804733 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2607 19:26:28.804816 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2608 19:26:28.804902 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2609 19:26:28.804985 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2610 19:26:28.805070 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2611 19:26:28.805159 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2612 19:26:28.805257 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2613 19:26:28.805340 ==
2614 19:26:28.805438 Dram Type= 6, Freq= 0, CH_0, rank 0
2615 19:26:28.805521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2616 19:26:28.805605 ==
2617 19:26:28.805691 DQS Delay:
2618 19:26:28.805773 DQS0 = 0, DQS1 = 0
2619 19:26:28.805859 DQM Delay:
2620 19:26:28.805945 DQM0 = 116, DQM1 = 107
2621 19:26:28.806029 DQ Delay:
2622 19:26:28.806119 DQ0 =115, DQ1 =115, DQ2 =115, DQ3 =111
2623 19:26:28.806206 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2624 19:26:28.806292 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2625 19:26:28.806375 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2626 19:26:28.806456
2627 19:26:28.806541
2628 19:26:28.806622 ==
2629 19:26:28.806720 Dram Type= 6, Freq= 0, CH_0, rank 0
2630 19:26:28.806803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2631 19:26:28.806891 ==
2632 19:26:28.806974
2633 19:26:28.807062
2634 19:26:28.807149 TX Vref Scan disable
2635 19:26:28.807231 == TX Byte 0 ==
2636 19:26:28.807316 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2637 19:26:28.807399 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2638 19:26:28.807482 == TX Byte 1 ==
2639 19:26:28.807568 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2640 19:26:28.807650 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2641 19:26:28.807735 ==
2642 19:26:28.807817 Dram Type= 6, Freq= 0, CH_0, rank 0
2643 19:26:28.807906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2644 19:26:28.807988 ==
2645 19:26:28.808073 TX Vref=22, minBit 1, minWin=25, winSum=418
2646 19:26:28.808156 TX Vref=24, minBit 7, minWin=24, winSum=421
2647 19:26:28.808239 TX Vref=26, minBit 3, minWin=25, winSum=424
2648 19:26:28.808326 TX Vref=28, minBit 5, minWin=25, winSum=429
2649 19:26:28.808412 TX Vref=30, minBit 1, minWin=26, winSum=433
2650 19:26:28.808495 TX Vref=32, minBit 0, minWin=26, winSum=431
2651 19:26:28.808585 [TxChooseVref] Worse bit 1, Min win 26, Win sum 433, Final Vref 30
2652 19:26:28.808679
2653 19:26:28.808766 Final TX Range 1 Vref 30
2654 19:26:28.808848
2655 19:26:28.808933 ==
2656 19:26:28.809023 Dram Type= 6, Freq= 0, CH_0, rank 0
2657 19:26:28.809106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2658 19:26:28.809215 ==
2659 19:26:28.809302
2660 19:26:28.809387
2661 19:26:28.809473 TX Vref Scan disable
2662 19:26:28.809562 == TX Byte 0 ==
2663 19:26:28.809647 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2664 19:26:28.809729 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2665 19:26:28.809815 == TX Byte 1 ==
2666 19:26:28.809898 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2667 19:26:28.810200 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2668 19:26:28.810294
2669 19:26:28.810383 [DATLAT]
2670 19:26:28.810466 Freq=1200, CH0 RK0
2671 19:26:28.810550
2672 19:26:28.810636 DATLAT Default: 0xd
2673 19:26:28.810743 0, 0xFFFF, sum = 0
2674 19:26:28.810830 1, 0xFFFF, sum = 0
2675 19:26:28.810914 2, 0xFFFF, sum = 0
2676 19:26:28.811003 3, 0xFFFF, sum = 0
2677 19:26:28.811094 4, 0xFFFF, sum = 0
2678 19:26:28.811182 5, 0xFFFF, sum = 0
2679 19:26:28.811267 6, 0xFFFF, sum = 0
2680 19:26:28.811350 7, 0xFFFF, sum = 0
2681 19:26:28.811438 8, 0xFFFF, sum = 0
2682 19:26:28.811522 9, 0xFFFF, sum = 0
2683 19:26:28.811609 10, 0xFFFF, sum = 0
2684 19:26:28.811693 11, 0xFFFF, sum = 0
2685 19:26:28.811782 12, 0x0, sum = 1
2686 19:26:28.811866 13, 0x0, sum = 2
2687 19:26:28.811953 14, 0x0, sum = 3
2688 19:26:28.812036 15, 0x0, sum = 4
2689 19:26:28.812137 best_step = 13
2690 19:26:28.812225
2691 19:26:28.812307 ==
2692 19:26:28.812388 Dram Type= 6, Freq= 0, CH_0, rank 0
2693 19:26:28.812475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2694 19:26:28.812557 ==
2695 19:26:28.812646 RX Vref Scan: 1
2696 19:26:28.812735
2697 19:26:28.812820 Set Vref Range= 32 -> 127
2698 19:26:28.812902
2699 19:26:28.812986 RX Vref 32 -> 127, step: 1
2700 19:26:28.813068
2701 19:26:28.813149 RX Delay -21 -> 252, step: 4
2702 19:26:28.813251
2703 19:26:28.813334 Set Vref, RX VrefLevel [Byte0]: 32
2704 19:26:28.813423 [Byte1]: 32
2705 19:26:28.813505
2706 19:26:28.813597 Set Vref, RX VrefLevel [Byte0]: 33
2707 19:26:28.813681 [Byte1]: 33
2708 19:26:28.813766
2709 19:26:28.813849 Set Vref, RX VrefLevel [Byte0]: 34
2710 19:26:28.813931 [Byte1]: 34
2711 19:26:28.814021
2712 19:26:28.814103 Set Vref, RX VrefLevel [Byte0]: 35
2713 19:26:28.814188 [Byte1]: 35
2714 19:26:28.814269
2715 19:26:28.814354 Set Vref, RX VrefLevel [Byte0]: 36
2716 19:26:28.814437 [Byte1]: 36
2717 19:26:28.814524
2718 19:26:28.814607 Set Vref, RX VrefLevel [Byte0]: 37
2719 19:26:28.814709 [Byte1]: 37
2720 19:26:28.814793
2721 19:26:28.814889 Set Vref, RX VrefLevel [Byte0]: 38
2722 19:26:28.814980 [Byte1]: 38
2723 19:26:28.815060
2724 19:26:28.815140 Set Vref, RX VrefLevel [Byte0]: 39
2725 19:26:28.815225 [Byte1]: 39
2726 19:26:28.815350
2727 19:26:28.815431 Set Vref, RX VrefLevel [Byte0]: 40
2728 19:26:28.815510 [Byte1]: 40
2729 19:26:28.815593
2730 19:26:28.815673 Set Vref, RX VrefLevel [Byte0]: 41
2731 19:26:28.815756 [Byte1]: 41
2732 19:26:28.815840
2733 19:26:28.815923 Set Vref, RX VrefLevel [Byte0]: 42
2734 19:26:28.816005 [Byte1]: 42
2735 19:26:28.816084
2736 19:26:28.816167 Set Vref, RX VrefLevel [Byte0]: 43
2737 19:26:28.816247 [Byte1]: 43
2738 19:26:28.816329
2739 19:26:28.816414 Set Vref, RX VrefLevel [Byte0]: 44
2740 19:26:28.816494 [Byte1]: 44
2741 19:26:28.816575
2742 19:26:28.816667 Set Vref, RX VrefLevel [Byte0]: 45
2743 19:26:28.816818 [Byte1]: 45
2744 19:26:28.816927
2745 19:26:28.817014 Set Vref, RX VrefLevel [Byte0]: 46
2746 19:26:28.817096 [Byte1]: 46
2747 19:26:28.817182
2748 19:26:28.817284 Set Vref, RX VrefLevel [Byte0]: 47
2749 19:26:28.817369 [Byte1]: 47
2750 19:26:28.817449
2751 19:26:28.817532 Set Vref, RX VrefLevel [Byte0]: 48
2752 19:26:28.817631 [Byte1]: 48
2753 19:26:28.817726
2754 19:26:28.817809 Set Vref, RX VrefLevel [Byte0]: 49
2755 19:26:28.817890 [Byte1]: 49
2756 19:26:28.817969
2757 19:26:28.818126 Set Vref, RX VrefLevel [Byte0]: 50
2758 19:26:28.818224 [Byte1]: 50
2759 19:26:28.818304
2760 19:26:28.818401 Set Vref, RX VrefLevel [Byte0]: 51
2761 19:26:28.818497 [Byte1]: 51
2762 19:26:28.818579
2763 19:26:28.818663 Set Vref, RX VrefLevel [Byte0]: 52
2764 19:26:28.818751 [Byte1]: 52
2765 19:26:28.818893
2766 19:26:28.818991 Set Vref, RX VrefLevel [Byte0]: 53
2767 19:26:28.819072 [Byte1]: 53
2768 19:26:28.819174
2769 19:26:28.819272 Set Vref, RX VrefLevel [Byte0]: 54
2770 19:26:28.819352 [Byte1]: 54
2771 19:26:28.819435
2772 19:26:28.819516 Set Vref, RX VrefLevel [Byte0]: 55
2773 19:26:28.819595 [Byte1]: 55
2774 19:26:28.819712
2775 19:26:28.819792 Set Vref, RX VrefLevel [Byte0]: 56
2776 19:26:28.819876 [Byte1]: 56
2777 19:26:28.819955
2778 19:26:28.820039 Set Vref, RX VrefLevel [Byte0]: 57
2779 19:26:28.820119 [Byte1]: 57
2780 19:26:28.820201
2781 19:26:28.820282 Set Vref, RX VrefLevel [Byte0]: 58
2782 19:26:28.820362 [Byte1]: 58
2783 19:26:28.820448
2784 19:26:28.820528 Set Vref, RX VrefLevel [Byte0]: 59
2785 19:26:28.820610 [Byte1]: 59
2786 19:26:28.820703
2787 19:26:28.820823 Set Vref, RX VrefLevel [Byte0]: 60
2788 19:26:28.820919 [Byte1]: 60
2789 19:26:28.821002
2790 19:26:28.821082 Set Vref, RX VrefLevel [Byte0]: 61
2791 19:26:28.821162 [Byte1]: 61
2792 19:26:28.821277
2793 19:26:28.821373 Set Vref, RX VrefLevel [Byte0]: 62
2794 19:26:28.821486 [Byte1]: 62
2795 19:26:28.821566
2796 19:26:28.821681 Set Vref, RX VrefLevel [Byte0]: 63
2797 19:26:28.821764 [Byte1]: 63
2798 19:26:28.821889
2799 19:26:28.821970 Set Vref, RX VrefLevel [Byte0]: 64
2800 19:26:28.822073 [Byte1]: 64
2801 19:26:28.822202
2802 19:26:28.822299 Set Vref, RX VrefLevel [Byte0]: 65
2803 19:26:28.822397 [Byte1]: 65
2804 19:26:28.822494
2805 19:26:28.822622 Set Vref, RX VrefLevel [Byte0]: 66
2806 19:26:28.822718 [Byte1]: 66
2807 19:26:28.822833
2808 19:26:28.822915 Set Vref, RX VrefLevel [Byte0]: 67
2809 19:26:28.823017 [Byte1]: 67
2810 19:26:28.823097
2811 19:26:28.823182 Set Vref, RX VrefLevel [Byte0]: 68
2812 19:26:28.823263 [Byte1]: 68
2813 19:26:28.823343
2814 19:26:28.823427 Set Vref, RX VrefLevel [Byte0]: 69
2815 19:26:28.823507 [Byte1]: 69
2816 19:26:28.823590
2817 19:26:28.823670 Final RX Vref Byte 0 = 52 to rank0
2818 19:26:28.823783 Final RX Vref Byte 1 = 52 to rank0
2819 19:26:28.823864 Final RX Vref Byte 0 = 52 to rank1
2820 19:26:28.823947 Final RX Vref Byte 1 = 52 to rank1==
2821 19:26:28.824032 Dram Type= 6, Freq= 0, CH_0, rank 0
2822 19:26:28.824145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2823 19:26:28.824240 ==
2824 19:26:28.824366 DQS Delay:
2825 19:26:28.824534 DQS0 = 0, DQS1 = 0
2826 19:26:28.824628 DQM Delay:
2827 19:26:28.824711 DQM0 = 115, DQM1 = 104
2828 19:26:28.824794 DQ Delay:
2829 19:26:28.824894 DQ0 =116, DQ1 =114, DQ2 =112, DQ3 =114
2830 19:26:28.824980 DQ4 =116, DQ5 =108, DQ6 =122, DQ7 =122
2831 19:26:28.825062 DQ8 =92, DQ9 =90, DQ10 =104, DQ11 =96
2832 19:26:28.825143 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2833 19:26:28.825283
2834 19:26:28.825410
2835 19:26:28.825492 [DQSOSCAuto] RK0, (LSB)MR18= 0xffef, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 410 ps
2836 19:26:28.825809 CH0 RK0: MR19=303, MR18=FFEF
2837 19:26:28.825918 CH0_RK0: MR19=0x303, MR18=0xFFEF, DQSOSC=410, MR23=63, INC=39, DEC=26
2838 19:26:28.826004
2839 19:26:28.826068 ----->DramcWriteLeveling(PI) begin...
2840 19:26:28.826122 ==
2841 19:26:28.826183 Dram Type= 6, Freq= 0, CH_0, rank 1
2842 19:26:28.826265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2843 19:26:28.826345 ==
2844 19:26:28.826467 Write leveling (Byte 0): 33 => 33
2845 19:26:28.826547 Write leveling (Byte 1): 30 => 30
2846 19:26:28.826630 DramcWriteLeveling(PI) end<-----
2847 19:26:28.826709
2848 19:26:28.826818 ==
2849 19:26:28.826913 Dram Type= 6, Freq= 0, CH_0, rank 1
2850 19:26:28.826997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2851 19:26:28.827110 ==
2852 19:26:28.827231 [Gating] SW mode calibration
2853 19:26:28.827313 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2854 19:26:28.827394 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2855 19:26:28.827507 0 15 0 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
2856 19:26:28.827588 0 15 4 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
2857 19:26:28.827703 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2858 19:26:28.827784 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2859 19:26:28.827867 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2860 19:26:28.827948 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2861 19:26:28.828036 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 1)
2862 19:26:28.828123 0 15 28 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 0)
2863 19:26:28.828208 1 0 0 | B1->B0 | 2f2f 2a2a | 1 0 | (1 0) (1 1)
2864 19:26:28.828289 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2865 19:26:28.828369 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2866 19:26:28.828454 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2867 19:26:28.828535 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2868 19:26:28.828630 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2869 19:26:28.828725 1 0 24 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (1 1)
2870 19:26:28.828814 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2871 19:26:28.828895 1 1 0 | B1->B0 | 2a2a 3b3b | 0 0 | (0 0) (0 0)
2872 19:26:28.829016 1 1 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
2873 19:26:28.829119 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2874 19:26:28.829218 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2875 19:26:28.829315 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2876 19:26:28.829410 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2877 19:26:28.829492 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2878 19:26:28.829579 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2879 19:26:28.829663 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2880 19:26:28.829798 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2881 19:26:28.829881 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 19:26:28.829967 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 19:26:28.830134 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 19:26:28.830294 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 19:26:28.830382 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 19:26:28.830468 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 19:26:28.830552 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 19:26:28.830642 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 19:26:28.830723 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 19:26:28.830809 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 19:26:28.830931 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 19:26:28.831025 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 19:26:28.831107 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 19:26:28.831193 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2895 19:26:28.831274 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2896 19:26:28.831367 Total UI for P1: 0, mck2ui 16
2897 19:26:28.831451 best dqsien dly found for B0: ( 1, 3, 28)
2898 19:26:28.831531 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2899 19:26:28.831618 Total UI for P1: 0, mck2ui 16
2900 19:26:28.831700 best dqsien dly found for B1: ( 1, 4, 0)
2901 19:26:28.831819 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2902 19:26:28.831901 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2903 19:26:28.831986
2904 19:26:28.832078 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2905 19:26:28.832217 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2906 19:26:28.832357 [Gating] SW calibration Done
2907 19:26:28.832445 ==
2908 19:26:28.832596 Dram Type= 6, Freq= 0, CH_0, rank 1
2909 19:26:28.832678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2910 19:26:28.832783 ==
2911 19:26:28.832894 RX Vref Scan: 0
2912 19:26:28.832988
2913 19:26:28.833072 RX Vref 0 -> 0, step: 1
2914 19:26:28.833164
2915 19:26:28.833268 RX Delay -40 -> 252, step: 8
2916 19:26:28.833363 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2917 19:26:28.833445 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2918 19:26:28.833530 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2919 19:26:28.833611 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2920 19:26:28.833700 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2921 19:26:28.833788 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2922 19:26:28.833870 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2923 19:26:28.833953 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2924 19:26:28.834038 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2925 19:26:28.834221 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2926 19:26:28.834345 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2927 19:26:28.834438 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2928 19:26:28.834521 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2929 19:26:28.834606 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2930 19:26:28.834687 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2931 19:26:28.834774 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2932 19:26:28.834854 ==
2933 19:26:28.834939 Dram Type= 6, Freq= 0, CH_0, rank 1
2934 19:26:28.835021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2935 19:26:28.835101 ==
2936 19:26:28.835184 DQS Delay:
2937 19:26:28.835482 DQS0 = 0, DQS1 = 0
2938 19:26:28.835570 DQM Delay:
2939 19:26:28.835654 DQM0 = 115, DQM1 = 106
2940 19:26:28.835734 DQ Delay:
2941 19:26:28.835820 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2942 19:26:28.835901 DQ4 =115, DQ5 =103, DQ6 =123, DQ7 =123
2943 19:26:28.835984 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
2944 19:26:28.836065 DQ12 =115, DQ13 =111, DQ14 =119, DQ15 =111
2945 19:26:28.836144
2946 19:26:28.836228
2947 19:26:28.836307 ==
2948 19:26:28.836393 Dram Type= 6, Freq= 0, CH_0, rank 1
2949 19:26:28.836474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2950 19:26:28.836557 ==
2951 19:26:28.836638
2952 19:26:28.836716
2953 19:26:28.836801 TX Vref Scan disable
2954 19:26:28.836884 == TX Byte 0 ==
2955 19:26:28.836964 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2956 19:26:28.837048 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2957 19:26:28.837128 == TX Byte 1 ==
2958 19:26:28.837232 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2959 19:26:28.837332 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2960 19:26:28.837416 ==
2961 19:26:28.837497 Dram Type= 6, Freq= 0, CH_0, rank 1
2962 19:26:28.837577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2963 19:26:28.837660 ==
2964 19:26:28.837740 TX Vref=22, minBit 1, minWin=25, winSum=417
2965 19:26:28.837828 TX Vref=24, minBit 1, minWin=25, winSum=427
2966 19:26:28.837909 TX Vref=26, minBit 3, minWin=25, winSum=427
2967 19:26:28.837992 TX Vref=28, minBit 12, minWin=26, winSum=435
2968 19:26:28.838073 TX Vref=30, minBit 12, minWin=26, winSum=436
2969 19:26:28.838154 TX Vref=32, minBit 4, minWin=26, winSum=435
2970 19:26:28.838242 [TxChooseVref] Worse bit 12, Min win 26, Win sum 436, Final Vref 30
2971 19:26:28.838323
2972 19:26:28.838402 Final TX Range 1 Vref 30
2973 19:26:28.838485
2974 19:26:28.838574 ==
2975 19:26:28.838660 Dram Type= 6, Freq= 0, CH_0, rank 1
2976 19:26:28.838740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2977 19:26:28.838822 ==
2978 19:26:28.838902
2979 19:26:28.838981
2980 19:26:28.839066 TX Vref Scan disable
2981 19:26:28.839146 == TX Byte 0 ==
2982 19:26:28.839230 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2983 19:26:28.839311 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2984 19:26:28.839393 == TX Byte 1 ==
2985 19:26:28.839487 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2986 19:26:28.839570 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2987 19:26:28.839649
2988 19:26:28.839733 [DATLAT]
2989 19:26:28.839813 Freq=1200, CH0 RK1
2990 19:26:28.839897
2991 19:26:28.839977 DATLAT Default: 0xd
2992 19:26:28.840059 0, 0xFFFF, sum = 0
2993 19:26:28.840141 1, 0xFFFF, sum = 0
2994 19:26:28.840223 2, 0xFFFF, sum = 0
2995 19:26:28.840309 3, 0xFFFF, sum = 0
2996 19:26:28.840391 4, 0xFFFF, sum = 0
2997 19:26:28.840481 5, 0xFFFF, sum = 0
2998 19:26:28.840563 6, 0xFFFF, sum = 0
2999 19:26:28.840651 7, 0xFFFF, sum = 0
3000 19:26:28.840733 8, 0xFFFF, sum = 0
3001 19:26:28.840817 9, 0xFFFF, sum = 0
3002 19:26:28.840905 10, 0xFFFF, sum = 0
3003 19:26:28.841009 11, 0xFFFF, sum = 0
3004 19:26:28.841092 12, 0x0, sum = 1
3005 19:26:28.841177 13, 0x0, sum = 2
3006 19:26:28.841270 14, 0x0, sum = 3
3007 19:26:28.841354 15, 0x0, sum = 4
3008 19:26:28.841436 best_step = 13
3009 19:26:28.841515
3010 19:26:28.841602 ==
3011 19:26:28.841683 Dram Type= 6, Freq= 0, CH_0, rank 1
3012 19:26:28.841768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3013 19:26:28.841849 ==
3014 19:26:28.841932 RX Vref Scan: 0
3015 19:26:28.842012
3016 19:26:28.842092 RX Vref 0 -> 0, step: 1
3017 19:26:28.842186
3018 19:26:28.842265 RX Delay -21 -> 252, step: 4
3019 19:26:28.842353 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3020 19:26:28.842435 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3021 19:26:28.842516 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3022 19:26:28.842601 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3023 19:26:28.842681 iDelay=195, Bit 4, Center 114 (47 ~ 182) 136
3024 19:26:28.842761 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3025 19:26:28.842844 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3026 19:26:28.842935 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3027 19:26:28.843072 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3028 19:26:28.843159 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3029 19:26:28.843251 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3030 19:26:28.843335 iDelay=195, Bit 11, Center 96 (31 ~ 162) 132
3031 19:26:28.843423 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3032 19:26:28.843503 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
3033 19:26:28.843587 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3034 19:26:28.843667 iDelay=195, Bit 15, Center 114 (47 ~ 182) 136
3035 19:26:28.843751 ==
3036 19:26:28.843833 Dram Type= 6, Freq= 0, CH_0, rank 1
3037 19:26:28.843914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3038 19:26:28.843997 ==
3039 19:26:28.844078 DQS Delay:
3040 19:26:28.844157 DQS0 = 0, DQS1 = 0
3041 19:26:28.844239 DQM Delay:
3042 19:26:28.844319 DQM0 = 114, DQM1 = 105
3043 19:26:28.844404 DQ Delay:
3044 19:26:28.844484 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3045 19:26:28.844569 DQ4 =114, DQ5 =104, DQ6 =122, DQ7 =122
3046 19:26:28.844658 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =96
3047 19:26:28.844739 DQ12 =110, DQ13 =112, DQ14 =116, DQ15 =114
3048 19:26:28.844867
3049 19:26:28.844951
3050 19:26:28.845046 [DQSOSCAuto] RK1, (LSB)MR18= 0xf0, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 410 ps
3051 19:26:28.845129 CH0 RK1: MR19=403, MR18=F0
3052 19:26:28.845231 CH0_RK1: MR19=0x403, MR18=0xF0, DQSOSC=410, MR23=63, INC=39, DEC=26
3053 19:26:28.845354 [RxdqsGatingPostProcess] freq 1200
3054 19:26:28.845453 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3055 19:26:28.845534 best DQS0 dly(2T, 0.5T) = (0, 12)
3056 19:26:28.845617 best DQS1 dly(2T, 0.5T) = (0, 12)
3057 19:26:28.845735 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3058 19:26:28.845819 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3059 19:26:28.845900 best DQS0 dly(2T, 0.5T) = (0, 11)
3060 19:26:28.846017 best DQS1 dly(2T, 0.5T) = (0, 12)
3061 19:26:28.846098 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3062 19:26:28.846179 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3063 19:26:28.846302 Pre-setting of DQS Precalculation
3064 19:26:28.846382 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3065 19:26:28.846467 ==
3066 19:26:28.846547 Dram Type= 6, Freq= 0, CH_1, rank 0
3067 19:26:28.846629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3068 19:26:28.846741 ==
3069 19:26:28.846823 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3070 19:26:28.846906 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3071 19:26:28.846989 [CA 0] Center 38 (9~68) winsize 60
3072 19:26:28.847073 [CA 1] Center 38 (8~68) winsize 61
3073 19:26:28.847170 [CA 2] Center 35 (5~65) winsize 61
3074 19:26:28.847270 [CA 3] Center 34 (4~65) winsize 62
3075 19:26:28.847548 [CA 4] Center 34 (4~65) winsize 62
3076 19:26:28.847641 [CA 5] Center 34 (4~64) winsize 61
3077 19:26:28.847757
3078 19:26:28.847837 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3079 19:26:28.847920
3080 19:26:28.848031 [CATrainingPosCal] consider 1 rank data
3081 19:26:28.848116 u2DelayCellTimex100 = 270/100 ps
3082 19:26:28.848196 CA0 delay=38 (9~68),Diff = 4 PI (19 cell)
3083 19:26:28.848280 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3084 19:26:28.848360 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3085 19:26:28.848444 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3086 19:26:28.848562 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3087 19:26:28.848648 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3088 19:26:28.848727
3089 19:26:28.848820 CA PerBit enable=1, Macro0, CA PI delay=34
3090 19:26:28.848901
3091 19:26:28.848981 [CBTSetCACLKResult] CA Dly = 34
3092 19:26:28.849067 CS Dly: 6 (0~37)
3093 19:26:28.849150 ==
3094 19:26:28.849281 Dram Type= 6, Freq= 0, CH_1, rank 1
3095 19:26:28.849402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3096 19:26:28.849487 ==
3097 19:26:28.849568 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3098 19:26:28.849652 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3099 19:26:28.849733 [CA 0] Center 38 (8~68) winsize 61
3100 19:26:28.849813 [CA 1] Center 38 (8~68) winsize 61
3101 19:26:28.849896 [CA 2] Center 34 (4~65) winsize 62
3102 19:26:28.849976 [CA 3] Center 34 (4~65) winsize 62
3103 19:26:28.850101 [CA 4] Center 34 (4~65) winsize 62
3104 19:26:28.850251 [CA 5] Center 33 (3~63) winsize 61
3105 19:26:28.850331
3106 19:26:28.850414 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3107 19:26:28.850496
3108 19:26:28.850578 [CATrainingPosCal] consider 2 rank data
3109 19:26:28.850658 u2DelayCellTimex100 = 270/100 ps
3110 19:26:28.850743 CA0 delay=38 (9~68),Diff = 5 PI (24 cell)
3111 19:26:28.850824 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3112 19:26:28.850907 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3113 19:26:28.850988 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3114 19:26:28.851101 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3115 19:26:28.851218 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3116 19:26:28.851319
3117 19:26:28.851399 CA PerBit enable=1, Macro0, CA PI delay=33
3118 19:26:28.851487
3119 19:26:28.851568 [CBTSetCACLKResult] CA Dly = 33
3120 19:26:28.851650 CS Dly: 7 (0~40)
3121 19:26:28.851739
3122 19:26:28.851819 ----->DramcWriteLeveling(PI) begin...
3123 19:26:28.851938 ==
3124 19:26:28.852019 Dram Type= 6, Freq= 0, CH_1, rank 0
3125 19:26:28.852103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3126 19:26:28.852184 ==
3127 19:26:28.852264 Write leveling (Byte 0): 25 => 25
3128 19:26:28.852349 Write leveling (Byte 1): 29 => 29
3129 19:26:28.852429 DramcWriteLeveling(PI) end<-----
3130 19:26:28.852511
3131 19:26:28.852594 ==
3132 19:26:28.852680 Dram Type= 6, Freq= 0, CH_1, rank 0
3133 19:26:28.852800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3134 19:26:28.852907 ==
3135 19:26:28.853001 [Gating] SW mode calibration
3136 19:26:28.853086 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3137 19:26:28.853180 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3138 19:26:28.853297 0 15 0 | B1->B0 | 2929 2525 | 1 0 | (0 0) (0 0)
3139 19:26:28.853420 0 15 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3140 19:26:28.853509 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3141 19:26:28.853591 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3142 19:26:28.853672 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3143 19:26:28.853794 0 15 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3144 19:26:28.853877 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3145 19:26:28.854019 0 15 28 | B1->B0 | 3333 3434 | 0 0 | (0 0) (0 1)
3146 19:26:28.854117 1 0 0 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (1 1)
3147 19:26:28.854198 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3148 19:26:28.854283 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3149 19:26:28.854365 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3150 19:26:28.854447 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3151 19:26:28.854564 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3152 19:26:28.854645 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3153 19:26:28.854730 1 0 28 | B1->B0 | 2827 2323 | 1 0 | (0 0) (0 0)
3154 19:26:28.854811 1 1 0 | B1->B0 | 4444 3737 | 0 0 | (0 0) (0 0)
3155 19:26:28.854891 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3156 19:26:28.854975 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3157 19:26:28.855056 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 19:26:28.855144 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3159 19:26:28.855274 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 19:26:28.855358 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3161 19:26:28.855438 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3162 19:26:28.855542 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3163 19:26:28.855637 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 19:26:28.855720 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 19:26:28.855801 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 19:26:28.855900 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 19:26:28.855985 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 19:26:28.856067 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 19:26:28.856152 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 19:26:28.856235 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 19:26:28.856317 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 19:26:28.856402 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 19:26:28.856484 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 19:26:28.856586 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 19:26:28.856667 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 19:26:28.856750 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 19:26:28.856831 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3178 19:26:28.856927 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3179 19:26:28.857024 Total UI for P1: 0, mck2ui 16
3180 19:26:28.857321 best dqsien dly found for B1: ( 1, 3, 30)
3181 19:26:28.857412 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3182 19:26:28.857493 Total UI for P1: 0, mck2ui 16
3183 19:26:28.857578 best dqsien dly found for B0: ( 1, 3, 30)
3184 19:26:28.857661 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3185 19:26:28.857741 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3186 19:26:28.857862
3187 19:26:28.857956 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3188 19:26:28.858043 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3189 19:26:28.858123 [Gating] SW calibration Done
3190 19:26:28.858206 ==
3191 19:26:28.858287 Dram Type= 6, Freq= 0, CH_1, rank 0
3192 19:26:28.858376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3193 19:26:28.858458 ==
3194 19:26:28.858539 RX Vref Scan: 0
3195 19:26:28.858620
3196 19:26:28.858710 RX Vref 0 -> 0, step: 1
3197 19:26:28.858794
3198 19:26:28.858877 RX Delay -40 -> 252, step: 8
3199 19:26:28.858958 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3200 19:26:28.859041 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3201 19:26:28.859122 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3202 19:26:28.859220 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3203 19:26:28.859302 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3204 19:26:28.859382 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3205 19:26:28.859466 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3206 19:26:28.859546 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3207 19:26:28.859631 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3208 19:26:28.859712 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3209 19:26:28.859794 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3210 19:26:28.859875 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3211 19:26:28.859955 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3212 19:26:28.860039 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3213 19:26:28.860119 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3214 19:26:28.860203 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3215 19:26:28.860283 ==
3216 19:26:28.860363 Dram Type= 6, Freq= 0, CH_1, rank 0
3217 19:26:28.860447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3218 19:26:28.860527 ==
3219 19:26:28.860610 DQS Delay:
3220 19:26:28.860690 DQS0 = 0, DQS1 = 0
3221 19:26:28.860774 DQM Delay:
3222 19:26:28.860854 DQM0 = 116, DQM1 = 108
3223 19:26:28.860935 DQ Delay:
3224 19:26:28.861016 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =119
3225 19:26:28.861096 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =115
3226 19:26:28.861195 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
3227 19:26:28.861406 DQ12 =119, DQ13 =115, DQ14 =111, DQ15 =115
3228 19:26:28.861503
3229 19:26:28.861592
3230 19:26:28.861703 ==
3231 19:26:28.861786 Dram Type= 6, Freq= 0, CH_1, rank 0
3232 19:26:28.861868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3233 19:26:28.861948 ==
3234 19:26:28.862072
3235 19:26:28.862153
3236 19:26:28.862235 TX Vref Scan disable
3237 19:26:28.862314 == TX Byte 0 ==
3238 19:26:28.862402 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3239 19:26:28.862483 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3240 19:26:28.862567 == TX Byte 1 ==
3241 19:26:28.862675 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3242 19:26:28.862758 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3243 19:26:28.862842 ==
3244 19:26:28.862922 Dram Type= 6, Freq= 0, CH_1, rank 0
3245 19:26:28.863004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3246 19:26:28.863085 ==
3247 19:26:28.863165 TX Vref=22, minBit 0, minWin=25, winSum=413
3248 19:26:28.863250 TX Vref=24, minBit 1, minWin=25, winSum=415
3249 19:26:28.863331 TX Vref=26, minBit 3, minWin=25, winSum=422
3250 19:26:28.863415 TX Vref=28, minBit 0, minWin=26, winSum=424
3251 19:26:28.863496 TX Vref=30, minBit 1, minWin=26, winSum=429
3252 19:26:28.863581 TX Vref=32, minBit 0, minWin=26, winSum=429
3253 19:26:28.863663 [TxChooseVref] Worse bit 1, Min win 26, Win sum 429, Final Vref 30
3254 19:26:28.863742
3255 19:26:28.863825 Final TX Range 1 Vref 30
3256 19:26:28.863910
3257 19:26:28.863999 ==
3258 19:26:28.864081 Dram Type= 6, Freq= 0, CH_1, rank 0
3259 19:26:28.864161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3260 19:26:28.864245 ==
3261 19:26:28.864325
3262 19:26:28.864405
3263 19:26:28.864486 TX Vref Scan disable
3264 19:26:28.864565 == TX Byte 0 ==
3265 19:26:28.864650 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3266 19:26:28.864731 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3267 19:26:28.864816 == TX Byte 1 ==
3268 19:26:28.864896 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3269 19:26:28.864977 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3270 19:26:28.865071
3271 19:26:28.865150 [DATLAT]
3272 19:26:28.865272 Freq=1200, CH1 RK0
3273 19:26:28.865352
3274 19:26:28.865438 DATLAT Default: 0xd
3275 19:26:28.865519 0, 0xFFFF, sum = 0
3276 19:26:28.865603 1, 0xFFFF, sum = 0
3277 19:26:28.865684 2, 0xFFFF, sum = 0
3278 19:26:28.865768 3, 0xFFFF, sum = 0
3279 19:26:28.865850 4, 0xFFFF, sum = 0
3280 19:26:28.865941 5, 0xFFFF, sum = 0
3281 19:26:28.866023 6, 0xFFFF, sum = 0
3282 19:26:28.866108 7, 0xFFFF, sum = 0
3283 19:26:28.866192 8, 0xFFFF, sum = 0
3284 19:26:28.866273 9, 0xFFFF, sum = 0
3285 19:26:28.866359 10, 0xFFFF, sum = 0
3286 19:26:28.866441 11, 0xFFFF, sum = 0
3287 19:26:28.866527 12, 0x0, sum = 1
3288 19:26:28.866609 13, 0x0, sum = 2
3289 19:26:28.866695 14, 0x0, sum = 3
3290 19:26:28.866777 15, 0x0, sum = 4
3291 19:26:28.866860 best_step = 13
3292 19:26:28.866943
3293 19:26:28.867023 ==
3294 19:26:28.867102 Dram Type= 6, Freq= 0, CH_1, rank 0
3295 19:26:28.867185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3296 19:26:28.867264 ==
3297 19:26:28.867347 RX Vref Scan: 1
3298 19:26:28.867425
3299 19:26:28.867505 Set Vref Range= 32 -> 127
3300 19:26:28.867586
3301 19:26:28.867665 RX Vref 32 -> 127, step: 1
3302 19:26:28.867748
3303 19:26:28.867827 RX Delay -21 -> 252, step: 4
3304 19:26:28.867911
3305 19:26:28.867990 Set Vref, RX VrefLevel [Byte0]: 32
3306 19:26:28.868069 [Byte1]: 32
3307 19:26:28.868153
3308 19:26:28.868233 Set Vref, RX VrefLevel [Byte0]: 33
3309 19:26:28.868312 [Byte1]: 33
3310 19:26:28.868395
3311 19:26:28.868474 Set Vref, RX VrefLevel [Byte0]: 34
3312 19:26:28.868556 [Byte1]: 34
3313 19:26:28.868635
3314 19:26:28.868714 Set Vref, RX VrefLevel [Byte0]: 35
3315 19:26:28.868797 [Byte1]: 35
3316 19:26:28.868876
3317 19:26:28.868981 Set Vref, RX VrefLevel [Byte0]: 36
3318 19:26:28.869061 [Byte1]: 36
3319 19:26:28.869145
3320 19:26:28.869246 Set Vref, RX VrefLevel [Byte0]: 37
3321 19:26:28.869344 [Byte1]: 37
3322 19:26:28.869423
3323 19:26:28.869506 Set Vref, RX VrefLevel [Byte0]: 38
3324 19:26:28.869589 [Byte1]: 38
3325 19:26:28.869668
3326 19:26:28.869749 Set Vref, RX VrefLevel [Byte0]: 39
3327 19:26:28.869829 [Byte1]: 39
3328 19:26:28.869907
3329 19:26:28.869991 Set Vref, RX VrefLevel [Byte0]: 40
3330 19:26:28.870070 [Byte1]: 40
3331 19:26:28.870153
3332 19:26:28.870232 Set Vref, RX VrefLevel [Byte0]: 41
3333 19:26:28.870513 [Byte1]: 41
3334 19:26:28.870599
3335 19:26:28.870678 Set Vref, RX VrefLevel [Byte0]: 42
3336 19:26:28.870765 [Byte1]: 42
3337 19:26:28.870847
3338 19:26:28.870932 Set Vref, RX VrefLevel [Byte0]: 43
3339 19:26:28.871014 [Byte1]: 43
3340 19:26:28.871092
3341 19:26:28.871176 Set Vref, RX VrefLevel [Byte0]: 44
3342 19:26:28.871257 [Byte1]: 44
3343 19:26:28.871338
3344 19:26:28.871418 Set Vref, RX VrefLevel [Byte0]: 45
3345 19:26:28.871498 [Byte1]: 45
3346 19:26:28.871602
3347 19:26:28.871695 Set Vref, RX VrefLevel [Byte0]: 46
3348 19:26:28.871780 [Byte1]: 46
3349 19:26:28.871859
3350 19:26:28.871942 Set Vref, RX VrefLevel [Byte0]: 47
3351 19:26:28.872022 [Byte1]: 47
3352 19:26:28.872115
3353 19:26:28.872196 Set Vref, RX VrefLevel [Byte0]: 48
3354 19:26:28.872275 [Byte1]: 48
3355 19:26:28.872358
3356 19:26:28.872437 Set Vref, RX VrefLevel [Byte0]: 49
3357 19:26:28.872521 [Byte1]: 49
3358 19:26:28.872600
3359 19:26:28.872681 Set Vref, RX VrefLevel [Byte0]: 50
3360 19:26:28.872761 [Byte1]: 50
3361 19:26:28.872840
3362 19:26:28.872924 Set Vref, RX VrefLevel [Byte0]: 51
3363 19:26:28.873003 [Byte1]: 51
3364 19:26:28.873086
3365 19:26:28.873166 Set Vref, RX VrefLevel [Byte0]: 52
3366 19:26:28.873286 [Byte1]: 52
3367 19:26:28.873366
3368 19:26:28.873447 Set Vref, RX VrefLevel [Byte0]: 53
3369 19:26:28.873528 [Byte1]: 53
3370 19:26:28.873606
3371 19:26:28.873691 Set Vref, RX VrefLevel [Byte0]: 54
3372 19:26:28.873772 [Byte1]: 54
3373 19:26:28.873850
3374 19:26:28.873933 Set Vref, RX VrefLevel [Byte0]: 55
3375 19:26:28.874013 [Byte1]: 55
3376 19:26:28.874094
3377 19:26:28.874173 Set Vref, RX VrefLevel [Byte0]: 56
3378 19:26:28.874252 [Byte1]: 56
3379 19:26:28.874336
3380 19:26:28.874416 Set Vref, RX VrefLevel [Byte0]: 57
3381 19:26:28.874500 [Byte1]: 57
3382 19:26:28.874579
3383 19:26:28.874658 Set Vref, RX VrefLevel [Byte0]: 58
3384 19:26:28.874741 [Byte1]: 58
3385 19:26:28.874820
3386 19:26:28.874902 Set Vref, RX VrefLevel [Byte0]: 59
3387 19:26:28.874981 [Byte1]: 59
3388 19:26:28.875062
3389 19:26:28.875147 Set Vref, RX VrefLevel [Byte0]: 60
3390 19:26:28.875227 [Byte1]: 60
3391 19:26:28.875307
3392 19:26:28.875389 Set Vref, RX VrefLevel [Byte0]: 61
3393 19:26:28.875478 [Byte1]: 61
3394 19:26:28.875561
3395 19:26:28.875640 Set Vref, RX VrefLevel [Byte0]: 62
3396 19:26:28.875722 [Byte1]: 62
3397 19:26:28.875801
3398 19:26:28.875880 Set Vref, RX VrefLevel [Byte0]: 63
3399 19:26:28.875964 [Byte1]: 63
3400 19:26:28.876042
3401 19:26:28.876124 Set Vref, RX VrefLevel [Byte0]: 64
3402 19:26:28.876204 [Byte1]: 64
3403 19:26:28.876286
3404 19:26:28.876367 Set Vref, RX VrefLevel [Byte0]: 65
3405 19:26:28.876446 [Byte1]: 65
3406 19:26:28.876528
3407 19:26:28.876608 Set Vref, RX VrefLevel [Byte0]: 66
3408 19:26:28.876687 [Byte1]: 66
3409 19:26:28.876768
3410 19:26:28.876847 Set Vref, RX VrefLevel [Byte0]: 67
3411 19:26:28.876931 [Byte1]: 67
3412 19:26:28.877038
3413 19:26:28.877119 Set Vref, RX VrefLevel [Byte0]: 68
3414 19:26:28.877253 [Byte1]: 68
3415 19:26:28.877340
3416 19:26:28.877420 Set Vref, RX VrefLevel [Byte0]: 69
3417 19:26:28.877505 [Byte1]: 69
3418 19:26:28.877584
3419 19:26:28.877664 Set Vref, RX VrefLevel [Byte0]: 70
3420 19:26:28.877748 [Byte1]: 70
3421 19:26:28.877828
3422 19:26:28.877907 Final RX Vref Byte 0 = 59 to rank0
3423 19:26:28.877991 Final RX Vref Byte 1 = 53 to rank0
3424 19:26:28.878071 Final RX Vref Byte 0 = 59 to rank1
3425 19:26:28.878154 Final RX Vref Byte 1 = 53 to rank1==
3426 19:26:28.878234 Dram Type= 6, Freq= 0, CH_1, rank 0
3427 19:26:28.878316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3428 19:26:28.878407 ==
3429 19:26:28.878488 DQS Delay:
3430 19:26:28.878568 DQS0 = 0, DQS1 = 0
3431 19:26:28.878646 DQM Delay:
3432 19:26:28.878729 DQM0 = 116, DQM1 = 109
3433 19:26:28.878808 DQ Delay:
3434 19:26:28.878891 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3435 19:26:28.878971 DQ4 =116, DQ5 =124, DQ6 =126, DQ7 =114
3436 19:26:28.879050 DQ8 =98, DQ9 =98, DQ10 =112, DQ11 =106
3437 19:26:28.879133 DQ12 =118, DQ13 =116, DQ14 =116, DQ15 =114
3438 19:26:28.879213
3439 19:26:28.879294
3440 19:26:28.879391 [DQSOSCAuto] RK0, (LSB)MR18= 0xe5, (MSB)MR19= 0x403, tDQSOscB0 = 421 ps tDQSOscB1 = 410 ps
3441 19:26:28.879472 CH1 RK0: MR19=403, MR18=E5
3442 19:26:28.879556 CH1_RK0: MR19=0x403, MR18=0xE5, DQSOSC=410, MR23=63, INC=39, DEC=26
3443 19:26:28.879635
3444 19:26:28.879717 ----->DramcWriteLeveling(PI) begin...
3445 19:26:28.879799 ==
3446 19:26:28.879878 Dram Type= 6, Freq= 0, CH_1, rank 1
3447 19:26:28.879961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3448 19:26:28.880041 ==
3449 19:26:28.880163 Write leveling (Byte 0): 25 => 25
3450 19:26:28.880242 Write leveling (Byte 1): 29 => 29
3451 19:26:28.880325 DramcWriteLeveling(PI) end<-----
3452 19:26:28.880404
3453 19:26:28.880486 ==
3454 19:26:28.880575 Dram Type= 6, Freq= 0, CH_1, rank 1
3455 19:26:28.880655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3456 19:26:28.880734 ==
3457 19:26:28.880827 [Gating] SW mode calibration
3458 19:26:28.880911 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3459 19:26:28.880992 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3460 19:26:28.881079 0 15 0 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
3461 19:26:28.881161 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3462 19:26:28.881283 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3463 19:26:28.881364 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3464 19:26:28.881451 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3465 19:26:28.881531 0 15 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3466 19:26:28.881615 0 15 24 | B1->B0 | 3434 2d2d | 0 0 | (0 0) (0 0)
3467 19:26:28.881696 0 15 28 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3468 19:26:28.881776 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3469 19:26:28.881859 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3470 19:26:28.881939 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3471 19:26:28.882038 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3472 19:26:28.882131 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3473 19:26:28.882417 1 0 20 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
3474 19:26:28.889152 1 0 24 | B1->B0 | 2525 3c3c | 0 0 | (0 0) (0 0)
3475 19:26:28.891914 1 0 28 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3476 19:26:28.895649 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3477 19:26:28.901827 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3478 19:26:28.905351 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3479 19:26:28.909107 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3480 19:26:28.915178 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3481 19:26:28.918769 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3482 19:26:28.921945 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3483 19:26:28.929186 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3484 19:26:28.932448 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 19:26:28.935764 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 19:26:28.938712 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 19:26:28.945345 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 19:26:28.948997 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 19:26:28.952274 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 19:26:28.958989 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 19:26:28.962160 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 19:26:28.965516 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 19:26:28.972010 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 19:26:28.975978 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 19:26:28.978867 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 19:26:28.985729 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3497 19:26:28.989294 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3498 19:26:28.992203 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3499 19:26:28.998949 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3500 19:26:28.999478 Total UI for P1: 0, mck2ui 16
3501 19:26:29.005919 best dqsien dly found for B0: ( 1, 3, 22)
3502 19:26:29.009800 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3503 19:26:29.012439 Total UI for P1: 0, mck2ui 16
3504 19:26:29.016125 best dqsien dly found for B1: ( 1, 3, 28)
3505 19:26:29.019369 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3506 19:26:29.022303 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3507 19:26:29.022817
3508 19:26:29.026244 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3509 19:26:29.029051 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3510 19:26:29.032643 [Gating] SW calibration Done
3511 19:26:29.032741 ==
3512 19:26:29.035588 Dram Type= 6, Freq= 0, CH_1, rank 1
3513 19:26:29.038802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3514 19:26:29.038907 ==
3515 19:26:29.042288 RX Vref Scan: 0
3516 19:26:29.042390
3517 19:26:29.045341 RX Vref 0 -> 0, step: 1
3518 19:26:29.045442
3519 19:26:29.045533 RX Delay -40 -> 252, step: 8
3520 19:26:29.052201 iDelay=192, Bit 0, Center 111 (40 ~ 183) 144
3521 19:26:29.055358 iDelay=192, Bit 1, Center 111 (40 ~ 183) 144
3522 19:26:29.058565 iDelay=192, Bit 2, Center 103 (32 ~ 175) 144
3523 19:26:29.062145 iDelay=192, Bit 3, Center 115 (48 ~ 183) 136
3524 19:26:29.065566 iDelay=192, Bit 4, Center 111 (40 ~ 183) 144
3525 19:26:29.071891 iDelay=192, Bit 5, Center 123 (56 ~ 191) 136
3526 19:26:29.075535 iDelay=192, Bit 6, Center 119 (48 ~ 191) 144
3527 19:26:29.078575 iDelay=192, Bit 7, Center 111 (48 ~ 175) 128
3528 19:26:29.082006 iDelay=192, Bit 8, Center 103 (32 ~ 175) 144
3529 19:26:29.085113 iDelay=192, Bit 9, Center 95 (24 ~ 167) 144
3530 19:26:29.092009 iDelay=192, Bit 10, Center 111 (40 ~ 183) 144
3531 19:26:29.095143 iDelay=192, Bit 11, Center 103 (32 ~ 175) 144
3532 19:26:29.099031 iDelay=192, Bit 12, Center 115 (48 ~ 183) 136
3533 19:26:29.102147 iDelay=192, Bit 13, Center 123 (56 ~ 191) 136
3534 19:26:29.105040 iDelay=192, Bit 14, Center 119 (48 ~ 191) 144
3535 19:26:29.112024 iDelay=192, Bit 15, Center 119 (48 ~ 191) 144
3536 19:26:29.112121 ==
3537 19:26:29.115640 Dram Type= 6, Freq= 0, CH_1, rank 1
3538 19:26:29.118881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3539 19:26:29.118985 ==
3540 19:26:29.119080 DQS Delay:
3541 19:26:29.121880 DQS0 = 0, DQS1 = 0
3542 19:26:29.121975 DQM Delay:
3543 19:26:29.125706 DQM0 = 113, DQM1 = 111
3544 19:26:29.125813 DQ Delay:
3545 19:26:29.128675 DQ0 =111, DQ1 =111, DQ2 =103, DQ3 =115
3546 19:26:29.131842 DQ4 =111, DQ5 =123, DQ6 =119, DQ7 =111
3547 19:26:29.135559 DQ8 =103, DQ9 =95, DQ10 =111, DQ11 =103
3548 19:26:29.138665 DQ12 =115, DQ13 =123, DQ14 =119, DQ15 =119
3549 19:26:29.138768
3550 19:26:29.138860
3551 19:26:29.142263 ==
3552 19:26:29.142369 Dram Type= 6, Freq= 0, CH_1, rank 1
3553 19:26:29.148534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3554 19:26:29.148639 ==
3555 19:26:29.148728
3556 19:26:29.148816
3557 19:26:29.152378 TX Vref Scan disable
3558 19:26:29.152478 == TX Byte 0 ==
3559 19:26:29.155516 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3560 19:26:29.162402 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3561 19:26:29.162505 == TX Byte 1 ==
3562 19:26:29.165443 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3563 19:26:29.171908 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3564 19:26:29.172007 ==
3565 19:26:29.175143 Dram Type= 6, Freq= 0, CH_1, rank 1
3566 19:26:29.178768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3567 19:26:29.178863 ==
3568 19:26:29.190723 TX Vref=22, minBit 3, minWin=25, winSum=416
3569 19:26:29.193880 TX Vref=24, minBit 0, minWin=26, winSum=422
3570 19:26:29.197501 TX Vref=26, minBit 3, minWin=25, winSum=424
3571 19:26:29.200863 TX Vref=28, minBit 1, minWin=26, winSum=430
3572 19:26:29.203950 TX Vref=30, minBit 5, minWin=26, winSum=432
3573 19:26:29.207649 TX Vref=32, minBit 1, minWin=26, winSum=435
3574 19:26:29.214149 [TxChooseVref] Worse bit 1, Min win 26, Win sum 435, Final Vref 32
3575 19:26:29.214264
3576 19:26:29.217646 Final TX Range 1 Vref 32
3577 19:26:29.217744
3578 19:26:29.217834 ==
3579 19:26:29.220751 Dram Type= 6, Freq= 0, CH_1, rank 1
3580 19:26:29.224551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3581 19:26:29.224650 ==
3582 19:26:29.224740
3583 19:26:29.224828
3584 19:26:29.227481 TX Vref Scan disable
3585 19:26:29.231168 == TX Byte 0 ==
3586 19:26:29.234124 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3587 19:26:29.237420 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3588 19:26:29.240956 == TX Byte 1 ==
3589 19:26:29.244230 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3590 19:26:29.247144 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3591 19:26:29.247246
3592 19:26:29.250773 [DATLAT]
3593 19:26:29.250870 Freq=1200, CH1 RK1
3594 19:26:29.250960
3595 19:26:29.254000 DATLAT Default: 0xd
3596 19:26:29.254095 0, 0xFFFF, sum = 0
3597 19:26:29.257750 1, 0xFFFF, sum = 0
3598 19:26:29.257855 2, 0xFFFF, sum = 0
3599 19:26:31.289355 3, 0xFFFF, sum = 0
3600 19:26:31.290491 4, 0xFFFF, sum = 0
3601 19:26:31.364995 5, 0xFFFF, sum = 0
3602 19:26:31.365807 6, 0xFFFF, sum = 0
3603 19:26:31.366327 7, 0xFFFF, sum = 0
3604 19:26:31.366747 8, 0xFFFF, sum = 0
3605 19:26:31.367152 9, 0xFFFF, sum = 0
3606 19:26:31.367845 10, 0xFFFF, sum = 0
3607 19:26:31.368371 11, 0xFFFF, sum = 0
3608 19:26:31.368871 12, 0x0, sum = 1
3609 19:26:31.369394 13, 0x0, sum = 2
3610 19:26:31.369935 14, 0x0, sum = 3
3611 19:26:31.370475 15, 0x0, sum = 4
3612 19:26:31.370965 best_step = 13
3613 19:26:31.371482
3614 19:26:31.371956 ==
3615 19:26:31.372474 Dram Type= 6, Freq= 0, CH_1, rank 1
3616 19:26:31.372997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3617 19:26:31.373548 ==
3618 19:26:31.374031 RX Vref Scan: 0
3619 19:26:31.374481
3620 19:26:31.374863 RX Vref 0 -> 0, step: 1
3621 19:26:31.375244
3622 19:26:31.375618 RX Delay -21 -> 252, step: 4
3623 19:26:31.375998 iDelay=191, Bit 0, Center 114 (47 ~ 182) 136
3624 19:26:31.376512 iDelay=191, Bit 1, Center 108 (43 ~ 174) 132
3625 19:26:31.377026 iDelay=191, Bit 2, Center 104 (39 ~ 170) 132
3626 19:26:31.377462 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3627 19:26:31.377889 iDelay=191, Bit 4, Center 112 (47 ~ 178) 132
3628 19:26:31.378269 iDelay=191, Bit 5, Center 120 (55 ~ 186) 132
3629 19:26:31.378737 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3630 19:26:31.379244 iDelay=191, Bit 7, Center 110 (47 ~ 174) 128
3631 19:26:31.379713 iDelay=191, Bit 8, Center 100 (35 ~ 166) 132
3632 19:26:31.380226 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3633 19:26:31.380692 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3634 19:26:31.381156 iDelay=191, Bit 11, Center 102 (35 ~ 170) 136
3635 19:26:31.381644 iDelay=191, Bit 12, Center 114 (51 ~ 178) 128
3636 19:26:31.382147 iDelay=191, Bit 13, Center 118 (55 ~ 182) 128
3637 19:26:31.382616 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3638 19:26:31.383117 iDelay=191, Bit 15, Center 118 (51 ~ 186) 136
3639 19:26:31.383620 ==
3640 19:26:31.384086 Dram Type= 6, Freq= 0, CH_1, rank 1
3641 19:26:31.384591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3642 19:26:31.385180 ==
3643 19:26:31.385689 DQS Delay:
3644 19:26:31.386168 DQS0 = 0, DQS1 = 0
3645 19:26:31.386623 DQM Delay:
3646 19:26:31.387049 DQM0 = 112, DQM1 = 109
3647 19:26:31.387502 DQ Delay:
3648 19:26:31.387950 DQ0 =114, DQ1 =108, DQ2 =104, DQ3 =112
3649 19:26:31.388377 DQ4 =112, DQ5 =120, DQ6 =122, DQ7 =110
3650 19:26:31.388828 DQ8 =100, DQ9 =98, DQ10 =110, DQ11 =102
3651 19:26:31.389312 DQ12 =114, DQ13 =118, DQ14 =118, DQ15 =118
3652 19:26:31.389696
3653 19:26:31.390196
3654 19:26:31.390729 [DQSOSCAuto] RK1, (LSB)MR18= 0xf6fc, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 414 ps
3655 19:26:31.391213 CH1 RK1: MR19=303, MR18=F6FC
3656 19:26:31.391739 CH1_RK1: MR19=0x303, MR18=0xF6FC, DQSOSC=411, MR23=63, INC=38, DEC=25
3657 19:26:31.392096 [RxdqsGatingPostProcess] freq 1200
3658 19:26:31.392442 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3659 19:26:31.392824 best DQS0 dly(2T, 0.5T) = (0, 11)
3660 19:26:31.393133 best DQS1 dly(2T, 0.5T) = (0, 11)
3661 19:26:31.393492 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3662 19:26:31.393792 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3663 19:26:31.394117 best DQS0 dly(2T, 0.5T) = (0, 11)
3664 19:26:31.394412 best DQS1 dly(2T, 0.5T) = (0, 11)
3665 19:26:31.394733 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3666 19:26:31.395028 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3667 19:26:31.395349 Pre-setting of DQS Precalculation
3668 19:26:31.395646 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3669 19:26:31.395972 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3670 19:26:31.396273 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3671 19:26:31.396590
3672 19:26:31.396849
3673 19:26:31.397069 [Calibration Summary] 2400 Mbps
3674 19:26:31.397327 CH 0, Rank 0
3675 19:26:31.397552 SW Impedance : PASS
3676 19:26:31.397797 DUTY Scan : NO K
3677 19:26:31.398019 ZQ Calibration : PASS
3678 19:26:31.398239 Jitter Meter : NO K
3679 19:26:31.398482 CBT Training : PASS
3680 19:26:31.398703 Write leveling : PASS
3681 19:26:31.398923 RX DQS gating : PASS
3682 19:26:31.399180 RX DQ/DQS(RDDQC) : PASS
3683 19:26:31.399404 TX DQ/DQS : PASS
3684 19:26:31.399647 RX DATLAT : PASS
3685 19:26:31.399869 RX DQ/DQS(Engine): PASS
3686 19:26:31.400096 TX OE : NO K
3687 19:26:31.400340 All Pass.
3688 19:26:31.400560
3689 19:26:31.400780 CH 0, Rank 1
3690 19:26:31.401021 SW Impedance : PASS
3691 19:26:31.401255 DUTY Scan : NO K
3692 19:26:31.401409 ZQ Calibration : PASS
3693 19:26:31.401582 Jitter Meter : NO K
3694 19:26:31.401736 CBT Training : PASS
3695 19:26:31.401852 Write leveling : PASS
3696 19:26:31.401966 RX DQS gating : PASS
3697 19:26:31.402108 RX DQ/DQS(RDDQC) : PASS
3698 19:26:31.402227 TX DQ/DQS : PASS
3699 19:26:31.402344 RX DATLAT : PASS
3700 19:26:31.402486 RX DQ/DQS(Engine): PASS
3701 19:26:31.402615 TX OE : NO K
3702 19:26:31.402732 All Pass.
3703 19:26:31.402861
3704 19:26:31.402978 CH 1, Rank 0
3705 19:26:31.403158 SW Impedance : PASS
3706 19:26:31.403337 DUTY Scan : NO K
3707 19:26:31.403519 ZQ Calibration : PASS
3708 19:26:31.403713 Jitter Meter : NO K
3709 19:26:31.403892 CBT Training : PASS
3710 19:26:31.404084 Write leveling : PASS
3711 19:26:31.404264 RX DQS gating : PASS
3712 19:26:31.404442 RX DQ/DQS(RDDQC) : PASS
3713 19:26:31.404619 TX DQ/DQS : PASS
3714 19:26:31.404815 RX DATLAT : PASS
3715 19:26:31.405007 RX DQ/DQS(Engine): PASS
3716 19:26:31.405226 TX OE : NO K
3717 19:26:31.405390 All Pass.
3718 19:26:31.405510
3719 19:26:31.405647 CH 1, Rank 1
3720 19:26:31.405765 SW Impedance : PASS
3721 19:26:31.405881 DUTY Scan : NO K
3722 19:26:31.405996 ZQ Calibration : PASS
3723 19:26:31.406129 Jitter Meter : NO K
3724 19:26:31.406246 CBT Training : PASS
3725 19:26:31.406361 Write leveling : PASS
3726 19:26:31.406476 RX DQS gating : PASS
3727 19:26:31.406589 RX DQ/DQS(RDDQC) : PASS
3728 19:26:31.406717 TX DQ/DQS : PASS
3729 19:26:31.406812 RX DATLAT : PASS
3730 19:26:31.406907 RX DQ/DQS(Engine): PASS
3731 19:26:31.407002 TX OE : NO K
3732 19:26:31.407098 All Pass.
3733 19:26:31.407194
3734 19:26:31.407288 DramC Write-DBI off
3735 19:26:31.407383 PER_BANK_REFRESH: Hybrid Mode
3736 19:26:31.407478 TX_TRACKING: ON
3737 19:26:31.407574 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3738 19:26:31.407672 [FAST_K] Save calibration result to emmc
3739 19:26:31.407769 dramc_set_vcore_voltage set vcore to 650000
3740 19:26:31.407864 Read voltage for 600, 5
3741 19:26:31.407959 Vio18 = 0
3742 19:26:31.408054 Vcore = 650000
3743 19:26:31.408149 Vdram = 0
3744 19:26:31.408243 Vddq = 0
3745 19:26:31.408337 Vmddr = 0
3746 19:26:31.408433 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3747 19:26:31.408795 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3748 19:26:31.408906 MEM_TYPE=3, freq_sel=19
3749 19:26:31.409006 sv_algorithm_assistance_LP4_1600
3750 19:26:31.409102 ============ PULL DRAM RESETB DOWN ============
3751 19:26:31.409200 ========== PULL DRAM RESETB DOWN end =========
3752 19:26:31.409315 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3753 19:26:31.409412 ===================================
3754 19:26:31.409509 LPDDR4 DRAM CONFIGURATION
3755 19:26:31.409605 ===================================
3756 19:26:31.409702 EX_ROW_EN[0] = 0x0
3757 19:26:31.409801 EX_ROW_EN[1] = 0x0
3758 19:26:31.409897 LP4Y_EN = 0x0
3759 19:26:31.409993 WORK_FSP = 0x0
3760 19:26:31.410105 WL = 0x2
3761 19:26:31.410200 RL = 0x2
3762 19:26:31.410295 BL = 0x2
3763 19:26:31.410391 RPST = 0x0
3764 19:26:31.410486 RD_PRE = 0x0
3765 19:26:31.410581 WR_PRE = 0x1
3766 19:26:31.410675 WR_PST = 0x0
3767 19:26:31.410770 DBI_WR = 0x0
3768 19:26:31.410865 DBI_RD = 0x0
3769 19:26:31.410959 OTF = 0x1
3770 19:26:31.411054 ===================================
3771 19:26:31.411151 ===================================
3772 19:26:31.411246 ANA top config
3773 19:26:31.411357 ===================================
3774 19:26:31.411454 DLL_ASYNC_EN = 0
3775 19:26:31.411549 ALL_SLAVE_EN = 1
3776 19:26:31.411645 NEW_RANK_MODE = 1
3777 19:26:31.411750 DLL_IDLE_MODE = 1
3778 19:26:31.411832 LP45_APHY_COMB_EN = 1
3779 19:26:31.411914 TX_ODT_DIS = 1
3780 19:26:31.411996 NEW_8X_MODE = 1
3781 19:26:31.412079 ===================================
3782 19:26:31.412162 ===================================
3783 19:26:31.412243 data_rate = 1200
3784 19:26:31.412325 CKR = 1
3785 19:26:31.412407 DQ_P2S_RATIO = 8
3786 19:26:31.412489 ===================================
3787 19:26:31.412572 CA_P2S_RATIO = 8
3788 19:26:31.412654 DQ_CA_OPEN = 0
3789 19:26:31.412737 DQ_SEMI_OPEN = 0
3790 19:26:31.412819 CA_SEMI_OPEN = 0
3791 19:26:31.412913 CA_FULL_RATE = 0
3792 19:26:31.412997 DQ_CKDIV4_EN = 1
3793 19:26:31.413093 CA_CKDIV4_EN = 1
3794 19:26:31.413234 CA_PREDIV_EN = 0
3795 19:26:31.413364 PH8_DLY = 0
3796 19:26:31.413492 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3797 19:26:31.413619 DQ_AAMCK_DIV = 4
3798 19:26:31.413747 CA_AAMCK_DIV = 4
3799 19:26:31.413874 CA_ADMCK_DIV = 4
3800 19:26:31.414001 DQ_TRACK_CA_EN = 0
3801 19:26:31.414129 CA_PICK = 600
3802 19:26:31.414256 CA_MCKIO = 600
3803 19:26:31.414384 MCKIO_SEMI = 0
3804 19:26:31.414511 PLL_FREQ = 2288
3805 19:26:31.414641 DQ_UI_PI_RATIO = 32
3806 19:26:31.414743 CA_UI_PI_RATIO = 0
3807 19:26:31.414827 ===================================
3808 19:26:31.414911 ===================================
3809 19:26:31.414994 memory_type:LPDDR4
3810 19:26:31.415076 GP_NUM : 10
3811 19:26:31.415158 SRAM_EN : 1
3812 19:26:31.415241 MD32_EN : 0
3813 19:26:31.415323 ===================================
3814 19:26:31.415405 [ANA_INIT] >>>>>>>>>>>>>>
3815 19:26:31.415487 <<<<<< [CONFIGURE PHASE]: ANA_TX
3816 19:26:31.415571 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3817 19:26:31.415654 ===================================
3818 19:26:31.415737 data_rate = 1200,PCW = 0X5800
3819 19:26:31.415820 ===================================
3820 19:26:31.415902 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3821 19:26:31.415986 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3822 19:26:31.416069 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3823 19:26:31.416152 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3824 19:26:31.416235 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3825 19:26:31.416317 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3826 19:26:31.416400 [ANA_INIT] flow start
3827 19:26:31.416483 [ANA_INIT] PLL >>>>>>>>
3828 19:26:31.416580 [ANA_INIT] PLL <<<<<<<<
3829 19:26:31.416663 [ANA_INIT] MIDPI >>>>>>>>
3830 19:26:31.416759 [ANA_INIT] MIDPI <<<<<<<<
3831 19:26:31.416831 [ANA_INIT] DLL >>>>>>>>
3832 19:26:31.416902 [ANA_INIT] flow end
3833 19:26:31.416974 ============ LP4 DIFF to SE enter ============
3834 19:26:31.417056 ============ LP4 DIFF to SE exit ============
3835 19:26:31.417179 [ANA_INIT] <<<<<<<<<<<<<
3836 19:26:31.417312 [Flow] Enable top DCM control >>>>>
3837 19:26:31.417423 [Flow] Enable top DCM control <<<<<
3838 19:26:31.417525 Enable DLL master slave shuffle
3839 19:26:31.417658 ==============================================================
3840 19:26:31.417783 Gating Mode config
3841 19:26:31.417884 ==============================================================
3842 19:26:31.417991 Config description:
3843 19:26:31.418092 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3844 19:26:31.418219 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3845 19:26:31.418356 SELPH_MODE 0: By rank 1: By Phase
3846 19:26:31.418491 ==============================================================
3847 19:26:31.418618 GAT_TRACK_EN = 1
3848 19:26:31.418743 RX_GATING_MODE = 2
3849 19:26:31.418867 RX_GATING_TRACK_MODE = 2
3850 19:26:31.418991 SELPH_MODE = 1
3851 19:26:31.419116 PICG_EARLY_EN = 1
3852 19:26:31.419260 VALID_LAT_VALUE = 1
3853 19:26:31.419394 ==============================================================
3854 19:26:31.419520 Enter into Gating configuration >>>>
3855 19:26:31.419645 Exit from Gating configuration <<<<
3856 19:26:31.419768 Enter into DVFS_PRE_config >>>>>
3857 19:26:31.419893 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3858 19:26:31.420019 Exit from DVFS_PRE_config <<<<<
3859 19:26:31.420143 Enter into PICG configuration >>>>
3860 19:26:31.420267 Exit from PICG configuration <<<<
3861 19:26:31.420620 [RX_INPUT] configuration >>>>>
3862 19:26:31.420749 [RX_INPUT] configuration <<<<<
3863 19:26:31.420877 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3864 19:26:31.421004 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3865 19:26:31.421130 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3866 19:26:31.421270 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3867 19:26:31.421405 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3868 19:26:31.421533 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3869 19:26:31.421662 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3870 19:26:31.421794 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3871 19:26:31.421906 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3872 19:26:31.422018 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3873 19:26:31.422130 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3874 19:26:31.422241 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3875 19:26:31.422352 ===================================
3876 19:26:31.422464 LPDDR4 DRAM CONFIGURATION
3877 19:26:31.422574 ===================================
3878 19:26:31.422685 EX_ROW_EN[0] = 0x0
3879 19:26:31.422796 EX_ROW_EN[1] = 0x0
3880 19:26:31.422906 LP4Y_EN = 0x0
3881 19:26:31.423017 WORK_FSP = 0x0
3882 19:26:31.423127 WL = 0x2
3883 19:26:31.423237 RL = 0x2
3884 19:26:31.423347 BL = 0x2
3885 19:26:31.423457 RPST = 0x0
3886 19:26:31.423566 RD_PRE = 0x0
3887 19:26:31.423676 WR_PRE = 0x1
3888 19:26:31.423785 WR_PST = 0x0
3889 19:26:31.423895 DBI_WR = 0x0
3890 19:26:31.424017 DBI_RD = 0x0
3891 19:26:31.424127 OTF = 0x1
3892 19:26:31.424237 ===================================
3893 19:26:31.424348 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3894 19:26:31.424458 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3895 19:26:31.424569 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3896 19:26:31.424679 ===================================
3897 19:26:31.424790 LPDDR4 DRAM CONFIGURATION
3898 19:26:31.424900 ===================================
3899 19:26:31.425010 EX_ROW_EN[0] = 0x10
3900 19:26:31.425131 EX_ROW_EN[1] = 0x0
3901 19:26:31.425249 LP4Y_EN = 0x0
3902 19:26:31.425362 WORK_FSP = 0x0
3903 19:26:31.425472 WL = 0x2
3904 19:26:31.425592 RL = 0x2
3905 19:26:31.425703 BL = 0x2
3906 19:26:31.425813 RPST = 0x0
3907 19:26:31.425922 RD_PRE = 0x0
3908 19:26:31.426032 WR_PRE = 0x1
3909 19:26:31.426142 WR_PST = 0x0
3910 19:26:31.426252 DBI_WR = 0x0
3911 19:26:31.426361 DBI_RD = 0x0
3912 19:26:31.426471 OTF = 0x1
3913 19:26:31.426582 ===================================
3914 19:26:31.426693 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3915 19:26:31.426805 nWR fixed to 30
3916 19:26:31.426905 [ModeRegInit_LP4] CH0 RK0
3917 19:26:31.427004 [ModeRegInit_LP4] CH0 RK1
3918 19:26:31.427103 [ModeRegInit_LP4] CH1 RK0
3919 19:26:31.427203 [ModeRegInit_LP4] CH1 RK1
3920 19:26:31.427302 match AC timing 17
3921 19:26:31.427400 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3922 19:26:31.427500 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3923 19:26:31.427599 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3924 19:26:31.427698 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3925 19:26:31.427798 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3926 19:26:31.427897 ==
3927 19:26:31.427997 Dram Type= 6, Freq= 0, CH_0, rank 0
3928 19:26:31.428106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3929 19:26:31.428208 ==
3930 19:26:31.428308 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3931 19:26:31.428408 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3932 19:26:31.428508 [CA 0] Center 36 (6~66) winsize 61
3933 19:26:31.428607 [CA 1] Center 36 (6~66) winsize 61
3934 19:26:31.428706 [CA 2] Center 34 (4~65) winsize 62
3935 19:26:31.428805 [CA 3] Center 34 (4~65) winsize 62
3936 19:26:31.428914 [CA 4] Center 33 (3~64) winsize 62
3937 19:26:31.429014 [CA 5] Center 33 (3~64) winsize 62
3938 19:26:31.429129
3939 19:26:31.429237 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3940 19:26:31.429327
3941 19:26:31.429417 [CATrainingPosCal] consider 1 rank data
3942 19:26:31.429519 u2DelayCellTimex100 = 270/100 ps
3943 19:26:31.429620 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3944 19:26:31.429721 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3945 19:26:31.429821 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3946 19:26:31.429908 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3947 19:26:31.430009 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3948 19:26:31.430109 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3949 19:26:31.430209
3950 19:26:31.430309 CA PerBit enable=1, Macro0, CA PI delay=33
3951 19:26:31.430409
3952 19:26:31.430508 [CBTSetCACLKResult] CA Dly = 33
3953 19:26:31.430608 CS Dly: 4 (0~35)
3954 19:26:31.430708 ==
3955 19:26:31.430807 Dram Type= 6, Freq= 0, CH_0, rank 1
3956 19:26:31.430906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3957 19:26:31.431006 ==
3958 19:26:31.431106 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3959 19:26:31.431206 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3960 19:26:31.431306 [CA 0] Center 36 (6~66) winsize 61
3961 19:26:31.431406 [CA 1] Center 36 (6~66) winsize 61
3962 19:26:31.431506 [CA 2] Center 34 (4~65) winsize 62
3963 19:26:31.431605 [CA 3] Center 34 (4~65) winsize 62
3964 19:26:31.431704 [CA 4] Center 33 (3~64) winsize 62
3965 19:26:31.431807 [CA 5] Center 33 (3~64) winsize 62
3966 19:26:31.431897
3967 19:26:31.431996 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3968 19:26:31.432086
3969 19:26:31.432177 [CATrainingPosCal] consider 2 rank data
3970 19:26:31.432267 u2DelayCellTimex100 = 270/100 ps
3971 19:26:31.432358 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3972 19:26:31.432456 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3973 19:26:31.432548 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3974 19:26:31.432638 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3975 19:26:31.432728 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3976 19:26:31.432818 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3977 19:26:31.432908
3978 19:26:31.432998 CA PerBit enable=1, Macro0, CA PI delay=33
3979 19:26:31.433090
3980 19:26:31.433181 [CBTSetCACLKResult] CA Dly = 33
3981 19:26:31.433265 CS Dly: 4 (0~36)
3982 19:26:31.433339
3983 19:26:31.433627 ----->DramcWriteLeveling(PI) begin...
3984 19:26:31.433722 ==
3985 19:26:31.433817 Dram Type= 6, Freq= 0, CH_0, rank 0
3986 19:26:31.433909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3987 19:26:31.434012 ==
3988 19:26:31.434104 Write leveling (Byte 0): 32 => 32
3989 19:26:31.434196 Write leveling (Byte 1): 31 => 31
3990 19:26:31.434287 DramcWriteLeveling(PI) end<-----
3991 19:26:31.434379
3992 19:26:31.434470 ==
3993 19:26:31.434561 Dram Type= 6, Freq= 0, CH_0, rank 0
3994 19:26:31.434652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3995 19:26:31.434744 ==
3996 19:26:31.434834 [Gating] SW mode calibration
3997 19:26:31.434933 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3998 19:26:31.435026 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3999 19:26:31.435117 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4000 19:26:31.435209 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4001 19:26:31.435300 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4002 19:26:31.435391 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4003 19:26:31.435490 0 9 16 | B1->B0 | 3131 2b2b | 0 0 | (0 1) (1 1)
4004 19:26:31.435589 0 9 20 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4005 19:26:31.435680 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4006 19:26:31.435771 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4007 19:26:31.435861 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4008 19:26:31.435952 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4009 19:26:31.436051 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4010 19:26:31.436141 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4011 19:26:31.436232 0 10 16 | B1->B0 | 3030 3b3b | 0 0 | (1 1) (0 0)
4012 19:26:31.436323 0 10 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4013 19:26:31.436413 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4014 19:26:31.436504 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4015 19:26:31.436594 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4016 19:26:31.436697 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4017 19:26:31.436786 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4018 19:26:31.436874 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4019 19:26:31.436963 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4020 19:26:31.437051 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 19:26:31.437139 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 19:26:31.437237 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 19:26:31.437328 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 19:26:31.437417 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 19:26:31.437505 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 19:26:31.437594 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 19:26:31.437683 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 19:26:31.437771 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 19:26:31.437870 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 19:26:31.437959 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 19:26:31.438054 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 19:26:31.438143 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 19:26:31.438232 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 19:26:31.438320 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 19:26:31.438417 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4036 19:26:31.438506 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4037 19:26:31.438594 Total UI for P1: 0, mck2ui 16
4038 19:26:31.438684 best dqsien dly found for B0: ( 0, 13, 16)
4039 19:26:31.438772 Total UI for P1: 0, mck2ui 16
4040 19:26:31.438869 best dqsien dly found for B1: ( 0, 13, 16)
4041 19:26:31.438958 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4042 19:26:31.439054 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4043 19:26:31.439181
4044 19:26:31.439269 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4045 19:26:31.439364 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4046 19:26:31.439453 [Gating] SW calibration Done
4047 19:26:31.439542 ==
4048 19:26:31.439631 Dram Type= 6, Freq= 0, CH_0, rank 0
4049 19:26:31.439720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4050 19:26:31.439809 ==
4051 19:26:31.439945 RX Vref Scan: 0
4052 19:26:31.440033
4053 19:26:31.440121 RX Vref 0 -> 0, step: 1
4054 19:26:31.440210
4055 19:26:31.440306 RX Delay -230 -> 252, step: 16
4056 19:26:31.440395 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4057 19:26:31.440484 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4058 19:26:31.440573 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4059 19:26:31.440661 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4060 19:26:31.440749 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4061 19:26:31.440837 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4062 19:26:31.440926 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4063 19:26:31.441014 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4064 19:26:31.441111 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4065 19:26:31.441199 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4066 19:26:31.441324 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4067 19:26:31.441413 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4068 19:26:31.441502 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4069 19:26:31.441591 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4070 19:26:31.441679 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4071 19:26:31.441768 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4072 19:26:31.441856 ==
4073 19:26:31.441945 Dram Type= 6, Freq= 0, CH_0, rank 0
4074 19:26:31.442041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4075 19:26:31.442131 ==
4076 19:26:31.442219 DQS Delay:
4077 19:26:31.442308 DQS0 = 0, DQS1 = 0
4078 19:26:31.442396 DQM Delay:
4079 19:26:31.442485 DQM0 = 42, DQM1 = 32
4080 19:26:31.442573 DQ Delay:
4081 19:26:31.442701 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4082 19:26:31.442790 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =57
4083 19:26:31.442879 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4084 19:26:31.442968 DQ12 =33, DQ13 =41, DQ14 =49, DQ15 =41
4085 19:26:31.443057
4086 19:26:31.443174
4087 19:26:31.443262 ==
4088 19:26:31.443350 Dram Type= 6, Freq= 0, CH_0, rank 0
4089 19:26:31.443639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4090 19:26:31.443730 ==
4091 19:26:31.443821
4092 19:26:31.443911
4093 19:26:31.444000 TX Vref Scan disable
4094 19:26:31.444098 == TX Byte 0 ==
4095 19:26:31.444187 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4096 19:26:31.444276 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4097 19:26:31.444366 == TX Byte 1 ==
4098 19:26:31.444454 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4099 19:26:31.444544 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4100 19:26:31.444641 ==
4101 19:26:31.444729 Dram Type= 6, Freq= 0, CH_0, rank 0
4102 19:26:31.444819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4103 19:26:31.444908 ==
4104 19:26:31.445001
4105 19:26:31.445111
4106 19:26:31.445215 TX Vref Scan disable
4107 19:26:31.445319 == TX Byte 0 ==
4108 19:26:31.445409 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4109 19:26:31.445498 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4110 19:26:31.445587 == TX Byte 1 ==
4111 19:26:31.445676 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4112 19:26:31.445774 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4113 19:26:31.445864
4114 19:26:31.445952 [DATLAT]
4115 19:26:31.446041 Freq=600, CH0 RK0
4116 19:26:31.446130
4117 19:26:31.446217 DATLAT Default: 0x9
4118 19:26:31.446305 0, 0xFFFF, sum = 0
4119 19:26:31.446396 1, 0xFFFF, sum = 0
4120 19:26:31.446487 2, 0xFFFF, sum = 0
4121 19:26:31.446577 3, 0xFFFF, sum = 0
4122 19:26:31.446667 4, 0xFFFF, sum = 0
4123 19:26:31.446757 5, 0xFFFF, sum = 0
4124 19:26:31.446847 6, 0xFFFF, sum = 0
4125 19:26:31.446937 7, 0xFFFF, sum = 0
4126 19:26:31.447027 8, 0x0, sum = 1
4127 19:26:31.447117 9, 0x0, sum = 2
4128 19:26:31.447207 10, 0x0, sum = 3
4129 19:26:31.447297 11, 0x0, sum = 4
4130 19:26:31.447387 best_step = 9
4131 19:26:31.447475
4132 19:26:31.447564 ==
4133 19:26:31.447652 Dram Type= 6, Freq= 0, CH_0, rank 0
4134 19:26:31.447740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4135 19:26:31.447829 ==
4136 19:26:31.447918 RX Vref Scan: 1
4137 19:26:31.448006
4138 19:26:31.448094 RX Vref 0 -> 0, step: 1
4139 19:26:31.448182
4140 19:26:31.448270 RX Delay -195 -> 252, step: 8
4141 19:26:31.448359
4142 19:26:31.448448 Set Vref, RX VrefLevel [Byte0]: 52
4143 19:26:31.448536 [Byte1]: 52
4144 19:26:31.448625
4145 19:26:31.448713 Final RX Vref Byte 0 = 52 to rank0
4146 19:26:31.448802 Final RX Vref Byte 1 = 52 to rank0
4147 19:26:31.448890 Final RX Vref Byte 0 = 52 to rank1
4148 19:26:31.448979 Final RX Vref Byte 1 = 52 to rank1==
4149 19:26:31.449088 Dram Type= 6, Freq= 0, CH_0, rank 0
4150 19:26:31.449179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4151 19:26:31.449290 ==
4152 19:26:31.449380 DQS Delay:
4153 19:26:31.449469 DQS0 = 0, DQS1 = 0
4154 19:26:31.449557 DQM Delay:
4155 19:26:31.449645 DQM0 = 42, DQM1 = 33
4156 19:26:31.449734 DQ Delay:
4157 19:26:31.449822 DQ0 =44, DQ1 =44, DQ2 =36, DQ3 =40
4158 19:26:31.449910 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4159 19:26:31.449999 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4160 19:26:31.450087 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4161 19:26:31.450175
4162 19:26:31.450264
4163 19:26:31.450352 [DQSOSCAuto] RK0, (LSB)MR18= 0x4221, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
4164 19:26:31.450441 CH0 RK0: MR19=808, MR18=4221
4165 19:26:31.450529 CH0_RK0: MR19=0x808, MR18=0x4221, DQSOSC=397, MR23=63, INC=166, DEC=110
4166 19:26:31.450620
4167 19:26:31.450709 ----->DramcWriteLeveling(PI) begin...
4168 19:26:31.450799 ==
4169 19:26:31.450888 Dram Type= 6, Freq= 0, CH_0, rank 1
4170 19:26:31.450976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4171 19:26:31.451065 ==
4172 19:26:31.451192 Write leveling (Byte 0): 32 => 32
4173 19:26:31.451281 Write leveling (Byte 1): 32 => 32
4174 19:26:31.451369 DramcWriteLeveling(PI) end<-----
4175 19:26:31.451458
4176 19:26:31.451546 ==
4177 19:26:31.451634 Dram Type= 6, Freq= 0, CH_0, rank 1
4178 19:26:31.451722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4179 19:26:31.451811 ==
4180 19:26:31.451899 [Gating] SW mode calibration
4181 19:26:31.451988 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4182 19:26:31.452077 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4183 19:26:31.452166 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4184 19:26:31.452254 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4185 19:26:31.452343 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4186 19:26:31.452431 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
4187 19:26:31.452520 0 9 16 | B1->B0 | 3131 2323 | 0 0 | (0 0) (0 0)
4188 19:26:31.452609 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4189 19:26:31.452697 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4190 19:26:31.452785 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4191 19:26:31.452873 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4192 19:26:31.452962 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4193 19:26:31.453050 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4194 19:26:31.453141 0 10 12 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
4195 19:26:31.453256 0 10 16 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
4196 19:26:31.453360 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4197 19:26:31.453449 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4198 19:26:31.453538 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4199 19:26:31.453631 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4200 19:26:31.453720 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4201 19:26:31.453809 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4202 19:26:31.453898 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4203 19:26:31.453987 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4204 19:26:31.454076 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 19:26:31.454164 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 19:26:31.454252 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 19:26:31.454341 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 19:26:31.454429 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 19:26:31.454518 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 19:26:31.454606 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 19:26:31.454695 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 19:26:31.454783 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 19:26:31.454871 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 19:26:31.454959 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 19:26:31.455047 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 19:26:31.455136 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 19:26:31.455419 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 19:26:31.455510 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4219 19:26:31.455602 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4220 19:26:31.455692 Total UI for P1: 0, mck2ui 16
4221 19:26:31.455782 best dqsien dly found for B0: ( 0, 13, 12)
4222 19:26:31.455872 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4223 19:26:31.455961 Total UI for P1: 0, mck2ui 16
4224 19:26:31.456051 best dqsien dly found for B1: ( 0, 13, 16)
4225 19:26:31.456140 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4226 19:26:31.456229 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4227 19:26:31.456317
4228 19:26:31.456405 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4229 19:26:31.456494 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4230 19:26:31.456583 [Gating] SW calibration Done
4231 19:26:31.456671 ==
4232 19:26:31.456760 Dram Type= 6, Freq= 0, CH_0, rank 1
4233 19:26:31.456849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4234 19:26:31.456938 ==
4235 19:26:31.457026 RX Vref Scan: 0
4236 19:26:31.457114
4237 19:26:31.457202 RX Vref 0 -> 0, step: 1
4238 19:26:31.457331
4239 19:26:31.457423 RX Delay -230 -> 252, step: 16
4240 19:26:31.457513 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4241 19:26:31.457602 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4242 19:26:31.457691 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4243 19:26:31.457780 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4244 19:26:31.457868 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4245 19:26:31.457959 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4246 19:26:31.458047 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4247 19:26:31.458136 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4248 19:26:31.458224 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4249 19:26:31.458312 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4250 19:26:31.458400 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4251 19:26:31.458488 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4252 19:26:31.458576 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4253 19:26:31.458664 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4254 19:26:31.458752 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4255 19:26:31.458841 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4256 19:26:31.458929 ==
4257 19:26:31.459018 Dram Type= 6, Freq= 0, CH_0, rank 1
4258 19:26:31.459106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4259 19:26:31.459194 ==
4260 19:26:31.459283 DQS Delay:
4261 19:26:31.459371 DQS0 = 0, DQS1 = 0
4262 19:26:31.459459 DQM Delay:
4263 19:26:31.459548 DQM0 = 40, DQM1 = 32
4264 19:26:31.459646 DQ Delay:
4265 19:26:31.459735 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =33
4266 19:26:31.459824 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4267 19:26:31.459912 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4268 19:26:31.460000 DQ12 =33, DQ13 =41, DQ14 =49, DQ15 =41
4269 19:26:31.460089
4270 19:26:31.460177
4271 19:26:31.460265 ==
4272 19:26:31.460354 Dram Type= 6, Freq= 0, CH_0, rank 1
4273 19:26:31.460442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4274 19:26:31.460531 ==
4275 19:26:31.460619
4276 19:26:31.460707
4277 19:26:31.460795 TX Vref Scan disable
4278 19:26:31.460883 == TX Byte 0 ==
4279 19:26:31.460971 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4280 19:26:31.461060 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4281 19:26:31.461149 == TX Byte 1 ==
4282 19:26:31.461275 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4283 19:26:31.461365 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4284 19:26:31.461454 ==
4285 19:26:31.461543 Dram Type= 6, Freq= 0, CH_0, rank 1
4286 19:26:31.461632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4287 19:26:31.461721 ==
4288 19:26:31.461809
4289 19:26:31.461898
4290 19:26:31.461986 TX Vref Scan disable
4291 19:26:31.462074 == TX Byte 0 ==
4292 19:26:31.462162 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4293 19:26:31.462262 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4294 19:26:31.462348 == TX Byte 1 ==
4295 19:26:31.462436 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4296 19:26:31.462525 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4297 19:26:31.462617
4298 19:26:31.462701 [DATLAT]
4299 19:26:31.462782 Freq=600, CH0 RK1
4300 19:26:31.462869
4301 19:26:31.462951 DATLAT Default: 0x9
4302 19:26:31.463033 0, 0xFFFF, sum = 0
4303 19:26:31.463117 1, 0xFFFF, sum = 0
4304 19:26:31.463200 2, 0xFFFF, sum = 0
4305 19:26:31.463282 3, 0xFFFF, sum = 0
4306 19:26:31.463366 4, 0xFFFF, sum = 0
4307 19:26:31.463448 5, 0xFFFF, sum = 0
4308 19:26:31.463534 6, 0xFFFF, sum = 0
4309 19:26:31.463617 7, 0xFFFF, sum = 0
4310 19:26:31.463697 8, 0x0, sum = 1
4311 19:26:31.463780 9, 0x0, sum = 2
4312 19:26:31.463861 10, 0x0, sum = 3
4313 19:26:31.463943 11, 0x0, sum = 4
4314 19:26:31.464025 best_step = 9
4315 19:26:31.464105
4316 19:26:31.464185 ==
4317 19:26:31.464269 Dram Type= 6, Freq= 0, CH_0, rank 1
4318 19:26:31.464350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4319 19:26:31.464431 ==
4320 19:26:31.464510 RX Vref Scan: 0
4321 19:26:31.464590
4322 19:26:31.464670 RX Vref 0 -> 0, step: 1
4323 19:26:31.464750
4324 19:26:31.464830 RX Delay -195 -> 252, step: 8
4325 19:26:31.464910 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4326 19:26:31.464990 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4327 19:26:31.465071 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4328 19:26:31.465152 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4329 19:26:31.465273 iDelay=205, Bit 4, Center 40 (-107 ~ 188) 296
4330 19:26:31.465357 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4331 19:26:31.465438 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4332 19:26:31.465518 iDelay=205, Bit 7, Center 44 (-107 ~ 196) 304
4333 19:26:31.465599 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4334 19:26:31.465679 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4335 19:26:31.465760 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4336 19:26:31.465841 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4337 19:26:31.465921 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4338 19:26:31.466002 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4339 19:26:31.466083 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4340 19:26:31.466164 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4341 19:26:31.466244 ==
4342 19:26:31.466324 Dram Type= 6, Freq= 0, CH_0, rank 1
4343 19:26:31.466404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4344 19:26:31.466485 ==
4345 19:26:31.466564 DQS Delay:
4346 19:26:31.466644 DQS0 = 0, DQS1 = 0
4347 19:26:31.466723 DQM Delay:
4348 19:26:31.466802 DQM0 = 39, DQM1 = 32
4349 19:26:31.466882 DQ Delay:
4350 19:26:31.466961 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =40
4351 19:26:31.467041 DQ4 =40, DQ5 =28, DQ6 =48, DQ7 =44
4352 19:26:31.467121 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =28
4353 19:26:31.467201 DQ12 =36, DQ13 =36, DQ14 =40, DQ15 =40
4354 19:26:31.467280
4355 19:26:31.467360
4356 19:26:31.467640 [DQSOSCAuto] RK1, (LSB)MR18= 0x4f31, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 394 ps
4357 19:26:31.467734 CH0 RK1: MR19=808, MR18=4F31
4358 19:26:31.467819 CH0_RK1: MR19=0x808, MR18=0x4F31, DQSOSC=394, MR23=63, INC=168, DEC=112
4359 19:26:31.467903 [RxdqsGatingPostProcess] freq 600
4360 19:26:31.467985 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4361 19:26:31.468067 Pre-setting of DQS Precalculation
4362 19:26:31.468147 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4363 19:26:31.468227 ==
4364 19:26:31.468308 Dram Type= 6, Freq= 0, CH_1, rank 0
4365 19:26:31.468389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4366 19:26:31.468469 ==
4367 19:26:31.468549 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4368 19:26:31.468633 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4369 19:26:31.468712 [CA 0] Center 35 (5~66) winsize 62
4370 19:26:31.468787 [CA 1] Center 35 (5~66) winsize 62
4371 19:26:31.468863 [CA 2] Center 33 (3~64) winsize 62
4372 19:26:31.468938 [CA 3] Center 33 (3~64) winsize 62
4373 19:26:31.469015 [CA 4] Center 33 (3~64) winsize 62
4374 19:26:31.469095 [CA 5] Center 33 (3~64) winsize 62
4375 19:26:31.469176
4376 19:26:31.469301 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4377 19:26:31.469383
4378 19:26:31.469480 [CATrainingPosCal] consider 1 rank data
4379 19:26:31.471880 u2DelayCellTimex100 = 270/100 ps
4380 19:26:31.474860 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4381 19:26:31.478745 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4382 19:26:31.481760 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4383 19:26:31.484934 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4384 19:26:31.488452 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4385 19:26:31.491496 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4386 19:26:31.491602
4387 19:26:31.498655 CA PerBit enable=1, Macro0, CA PI delay=33
4388 19:26:31.498762
4389 19:26:31.501954 [CBTSetCACLKResult] CA Dly = 33
4390 19:26:31.502055 CS Dly: 6 (0~37)
4391 19:26:31.502145 ==
4392 19:26:31.505064 Dram Type= 6, Freq= 0, CH_1, rank 1
4393 19:26:31.508421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4394 19:26:31.508536 ==
4395 19:26:31.515170 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4396 19:26:31.522324 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4397 19:26:31.525027 [CA 0] Center 35 (5~66) winsize 62
4398 19:26:31.528424 [CA 1] Center 36 (6~66) winsize 61
4399 19:26:31.532017 [CA 2] Center 34 (3~65) winsize 63
4400 19:26:31.535049 [CA 3] Center 34 (3~65) winsize 63
4401 19:26:31.538329 [CA 4] Center 34 (4~65) winsize 62
4402 19:26:31.541908 [CA 5] Center 33 (3~64) winsize 62
4403 19:26:31.542140
4404 19:26:31.545221 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4405 19:26:31.545411
4406 19:26:31.548812 [CATrainingPosCal] consider 2 rank data
4407 19:26:31.551700 u2DelayCellTimex100 = 270/100 ps
4408 19:26:31.555306 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4409 19:26:31.559022 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4410 19:26:31.562134 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4411 19:26:31.565825 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4412 19:26:31.568588 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4413 19:26:31.571924 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4414 19:26:31.572034
4415 19:26:31.578834 CA PerBit enable=1, Macro0, CA PI delay=33
4416 19:26:31.578965
4417 19:26:31.579065 [CBTSetCACLKResult] CA Dly = 33
4418 19:26:31.581896 CS Dly: 5 (0~36)
4419 19:26:31.582002
4420 19:26:31.585005 ----->DramcWriteLeveling(PI) begin...
4421 19:26:31.585120 ==
4422 19:26:31.588598 Dram Type= 6, Freq= 0, CH_1, rank 0
4423 19:26:31.591616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4424 19:26:31.591736 ==
4425 19:26:31.595434 Write leveling (Byte 0): 32 => 32
4426 19:26:31.598270 Write leveling (Byte 1): 32 => 32
4427 19:26:31.601572 DramcWriteLeveling(PI) end<-----
4428 19:26:31.601665
4429 19:26:31.601731 ==
4430 19:26:31.605204 Dram Type= 6, Freq= 0, CH_1, rank 0
4431 19:26:31.608386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4432 19:26:31.612274 ==
4433 19:26:31.612368 [Gating] SW mode calibration
4434 19:26:31.621980 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4435 19:26:31.625365 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4436 19:26:31.628490 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4437 19:26:31.635167 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4438 19:26:31.638229 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4439 19:26:31.641789 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
4440 19:26:31.648559 0 9 16 | B1->B0 | 2a2a 2828 | 0 1 | (0 0) (1 0)
4441 19:26:31.651642 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4442 19:26:31.655316 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4443 19:26:31.661880 0 9 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4444 19:26:31.665262 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4445 19:26:31.668799 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4446 19:26:31.675312 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4447 19:26:31.678819 0 10 12 | B1->B0 | 2525 2b2b | 0 0 | (0 0) (0 0)
4448 19:26:31.681880 0 10 16 | B1->B0 | 3c3c 4242 | 0 0 | (0 0) (0 0)
4449 19:26:31.685393 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4450 19:26:31.691665 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4451 19:26:31.695348 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4452 19:26:31.699063 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4453 19:26:31.705218 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4454 19:26:31.709019 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4455 19:26:31.711791 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4456 19:26:31.718995 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 19:26:31.721832 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 19:26:31.725422 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 19:26:31.731725 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 19:26:31.735553 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 19:26:31.738932 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 19:26:31.745684 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 19:26:31.749126 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 19:26:31.751939 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 19:26:31.755105 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 19:26:31.761906 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 19:26:31.765542 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 19:26:31.768629 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 19:26:31.775663 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 19:26:31.778657 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 19:26:31.782272 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4472 19:26:31.785228 Total UI for P1: 0, mck2ui 16
4473 19:26:31.788721 best dqsien dly found for B1: ( 0, 13, 10)
4474 19:26:31.795596 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4475 19:26:31.795687 Total UI for P1: 0, mck2ui 16
4476 19:26:31.802392 best dqsien dly found for B0: ( 0, 13, 12)
4477 19:26:31.805184 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4478 19:26:31.808542 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4479 19:26:31.808628
4480 19:26:31.812375 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4481 19:26:31.815060 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4482 19:26:31.818906 [Gating] SW calibration Done
4483 19:26:31.819010 ==
4484 19:26:31.822342 Dram Type= 6, Freq= 0, CH_1, rank 0
4485 19:26:31.825181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4486 19:26:31.825291 ==
4487 19:26:31.828923 RX Vref Scan: 0
4488 19:26:31.829032
4489 19:26:31.829131 RX Vref 0 -> 0, step: 1
4490 19:26:31.829262
4491 19:26:31.831889 RX Delay -230 -> 252, step: 16
4492 19:26:31.838714 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4493 19:26:31.842311 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4494 19:26:31.845423 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4495 19:26:31.848695 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4496 19:26:31.851897 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4497 19:26:31.858905 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4498 19:26:31.862225 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4499 19:26:31.865353 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4500 19:26:31.869141 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4501 19:26:31.872695 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4502 19:26:31.879152 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4503 19:26:31.882278 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4504 19:26:31.885776 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4505 19:26:31.888784 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4506 19:26:31.895314 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4507 19:26:31.899030 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4508 19:26:31.899134 ==
4509 19:26:31.902167 Dram Type= 6, Freq= 0, CH_1, rank 0
4510 19:26:31.905504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4511 19:26:31.905596 ==
4512 19:26:31.909106 DQS Delay:
4513 19:26:31.909223 DQS0 = 0, DQS1 = 0
4514 19:26:31.909311 DQM Delay:
4515 19:26:31.912117 DQM0 = 46, DQM1 = 36
4516 19:26:31.912249 DQ Delay:
4517 19:26:31.915718 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4518 19:26:31.918952 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =41
4519 19:26:31.922536 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =33
4520 19:26:31.925532 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4521 19:26:31.925618
4522 19:26:31.925700
4523 19:26:31.925778 ==
4524 19:26:31.929116 Dram Type= 6, Freq= 0, CH_1, rank 0
4525 19:26:31.935415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4526 19:26:31.935564 ==
4527 19:26:31.935673
4528 19:26:31.935763
4529 19:26:31.935848 TX Vref Scan disable
4530 19:26:31.939220 == TX Byte 0 ==
4531 19:26:31.942361 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4532 19:26:31.948947 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4533 19:26:31.949093 == TX Byte 1 ==
4534 19:26:31.952319 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4535 19:26:31.958726 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4536 19:26:31.958888 ==
4537 19:26:31.962144 Dram Type= 6, Freq= 0, CH_1, rank 0
4538 19:26:31.965640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4539 19:26:31.965770 ==
4540 19:26:31.965864
4541 19:26:31.965963
4542 19:26:31.969007 TX Vref Scan disable
4543 19:26:31.969138 == TX Byte 0 ==
4544 19:26:31.976055 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4545 19:26:31.978884 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4546 19:26:31.979051 == TX Byte 1 ==
4547 19:26:31.985711 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4548 19:26:31.989477 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4549 19:26:31.989611
4550 19:26:31.989712 [DATLAT]
4551 19:26:31.992379 Freq=600, CH1 RK0
4552 19:26:31.992486
4553 19:26:31.992584 DATLAT Default: 0x9
4554 19:26:31.996283 0, 0xFFFF, sum = 0
4555 19:26:31.996398 1, 0xFFFF, sum = 0
4556 19:26:31.999136 2, 0xFFFF, sum = 0
4557 19:26:31.999245 3, 0xFFFF, sum = 0
4558 19:26:32.002800 4, 0xFFFF, sum = 0
4559 19:26:32.002914 5, 0xFFFF, sum = 0
4560 19:26:32.005909 6, 0xFFFF, sum = 0
4561 19:26:32.006028 7, 0xFFFF, sum = 0
4562 19:26:32.009422 8, 0x0, sum = 1
4563 19:26:32.009543 9, 0x0, sum = 2
4564 19:26:32.013000 10, 0x0, sum = 3
4565 19:26:32.013112 11, 0x0, sum = 4
4566 19:26:32.016187 best_step = 9
4567 19:26:32.016296
4568 19:26:32.016386 ==
4569 19:26:32.019636 Dram Type= 6, Freq= 0, CH_1, rank 0
4570 19:26:32.022819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4571 19:26:32.022944 ==
4572 19:26:32.026277 RX Vref Scan: 1
4573 19:26:32.026395
4574 19:26:32.026485 RX Vref 0 -> 0, step: 1
4575 19:26:32.026582
4576 19:26:32.029349 RX Delay -195 -> 252, step: 8
4577 19:26:32.029460
4578 19:26:32.033042 Set Vref, RX VrefLevel [Byte0]: 59
4579 19:26:32.036092 [Byte1]: 53
4580 19:26:32.039530
4581 19:26:32.039650 Final RX Vref Byte 0 = 59 to rank0
4582 19:26:32.042980 Final RX Vref Byte 1 = 53 to rank0
4583 19:26:32.046103 Final RX Vref Byte 0 = 59 to rank1
4584 19:26:32.049698 Final RX Vref Byte 1 = 53 to rank1==
4585 19:26:32.052782 Dram Type= 6, Freq= 0, CH_1, rank 0
4586 19:26:32.059494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4587 19:26:32.059639 ==
4588 19:26:32.059753 DQS Delay:
4589 19:26:32.059841 DQS0 = 0, DQS1 = 0
4590 19:26:32.063010 DQM Delay:
4591 19:26:32.063129 DQM0 = 40, DQM1 = 34
4592 19:26:32.066261 DQ Delay:
4593 19:26:32.069725 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4594 19:26:32.069859 DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =36
4595 19:26:32.072695 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =32
4596 19:26:32.076033 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =40
4597 19:26:32.079986
4598 19:26:32.080119
4599 19:26:32.086221 [DQSOSCAuto] RK0, (LSB)MR18= 0x4006, (MSB)MR19= 0x808, tDQSOscB0 = 408 ps tDQSOscB1 = 397 ps
4600 19:26:32.090191 CH1 RK0: MR19=808, MR18=4006
4601 19:26:32.096144 CH1_RK0: MR19=0x808, MR18=0x4006, DQSOSC=397, MR23=63, INC=166, DEC=110
4602 19:26:32.096292
4603 19:26:32.099856 ----->DramcWriteLeveling(PI) begin...
4604 19:26:32.099973 ==
4605 19:26:32.103522 Dram Type= 6, Freq= 0, CH_1, rank 1
4606 19:26:32.106573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4607 19:26:32.106701 ==
4608 19:26:32.109592 Write leveling (Byte 0): 30 => 30
4609 19:26:32.113187 Write leveling (Byte 1): 31 => 31
4610 19:26:32.116217 DramcWriteLeveling(PI) end<-----
4611 19:26:32.116333
4612 19:26:32.116437 ==
4613 19:26:32.119904 Dram Type= 6, Freq= 0, CH_1, rank 1
4614 19:26:32.122780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4615 19:26:32.122903 ==
4616 19:26:32.126208 [Gating] SW mode calibration
4617 19:26:32.133263 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4618 19:26:32.139480 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4619 19:26:32.143261 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4620 19:26:32.146658 0 9 4 | B1->B0 | 3534 3434 | 1 1 | (0 0) (1 1)
4621 19:26:32.153004 0 9 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
4622 19:26:32.156218 0 9 12 | B1->B0 | 3030 2929 | 0 1 | (0 0) (1 0)
4623 19:26:32.159634 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4624 19:26:32.166382 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4625 19:26:32.169681 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4626 19:26:32.172888 0 9 28 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
4627 19:26:32.179622 0 10 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4628 19:26:32.183032 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4629 19:26:32.186392 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4630 19:26:32.189717 0 10 12 | B1->B0 | 3130 3d3d | 1 0 | (0 0) (0 0)
4631 19:26:32.196680 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4632 19:26:32.199834 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4633 19:26:32.203401 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4634 19:26:32.209613 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4635 19:26:32.213234 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4636 19:26:32.216154 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4637 19:26:32.223185 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4638 19:26:32.226198 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4639 19:26:32.229938 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4640 19:26:32.236336 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 19:26:32.239907 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 19:26:32.243459 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 19:26:32.249622 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 19:26:32.252968 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 19:26:32.256513 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 19:26:32.263606 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 19:26:32.266746 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 19:26:32.270604 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 19:26:32.273076 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 19:26:32.300441 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 19:26:32.300661 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 19:26:32.300777 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 19:26:32.300896 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4654 19:26:32.300989 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4655 19:26:32.301087 Total UI for P1: 0, mck2ui 16
4656 19:26:32.303426 best dqsien dly found for B0: ( 0, 13, 8)
4657 19:26:32.307174 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4658 19:26:32.310084 Total UI for P1: 0, mck2ui 16
4659 19:26:32.313168 best dqsien dly found for B1: ( 0, 13, 12)
4660 19:26:32.316831 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4661 19:26:32.319759 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4662 19:26:32.319913
4663 19:26:32.326455 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4664 19:26:32.330155 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4665 19:26:32.330315 [Gating] SW calibration Done
4666 19:26:32.333204 ==
4667 19:26:32.336553 Dram Type= 6, Freq= 0, CH_1, rank 1
4668 19:26:32.339969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4669 19:26:32.340120 ==
4670 19:26:32.340249 RX Vref Scan: 0
4671 19:26:32.340350
4672 19:26:32.343554 RX Vref 0 -> 0, step: 1
4673 19:26:32.343681
4674 19:26:32.346320 RX Delay -230 -> 252, step: 16
4675 19:26:32.349727 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4676 19:26:32.353241 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4677 19:26:32.359995 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4678 19:26:32.363257 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4679 19:26:32.366592 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4680 19:26:32.369761 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4681 19:26:32.376538 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4682 19:26:32.379977 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4683 19:26:32.383126 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4684 19:26:32.386449 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4685 19:26:32.389622 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4686 19:26:32.396807 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4687 19:26:32.399833 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4688 19:26:32.403401 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4689 19:26:32.406581 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4690 19:26:32.413825 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4691 19:26:32.414023 ==
4692 19:26:32.416583 Dram Type= 6, Freq= 0, CH_1, rank 1
4693 19:26:32.420311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4694 19:26:32.420477 ==
4695 19:26:32.420575 DQS Delay:
4696 19:26:32.423276 DQS0 = 0, DQS1 = 0
4697 19:26:32.423394 DQM Delay:
4698 19:26:32.426428 DQM0 = 38, DQM1 = 35
4699 19:26:32.426559 DQ Delay:
4700 19:26:32.429962 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =33
4701 19:26:32.433180 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4702 19:26:32.436901 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4703 19:26:32.440079 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =49
4704 19:26:32.440204
4705 19:26:32.440309
4706 19:26:32.440418 ==
4707 19:26:32.443010 Dram Type= 6, Freq= 0, CH_1, rank 1
4708 19:26:32.446803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4709 19:26:32.446933 ==
4710 19:26:32.447045
4711 19:26:32.447153
4712 19:26:32.449854 TX Vref Scan disable
4713 19:26:32.453140 == TX Byte 0 ==
4714 19:26:32.456756 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4715 19:26:32.459993 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4716 19:26:32.463489 == TX Byte 1 ==
4717 19:26:32.466644 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4718 19:26:32.469690 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4719 19:26:32.469825 ==
4720 19:26:32.473222 Dram Type= 6, Freq= 0, CH_1, rank 1
4721 19:26:32.479763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4722 19:26:32.479944 ==
4723 19:26:32.480045
4724 19:26:32.480142
4725 19:26:32.480262 TX Vref Scan disable
4726 19:26:32.484121 == TX Byte 0 ==
4727 19:26:32.487679 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4728 19:26:32.490821 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4729 19:26:32.494251 == TX Byte 1 ==
4730 19:26:32.496981 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4731 19:26:32.500541 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4732 19:26:32.504395
4733 19:26:32.504550 [DATLAT]
4734 19:26:32.504648 Freq=600, CH1 RK1
4735 19:26:32.504737
4736 19:26:32.507478 DATLAT Default: 0x9
4737 19:26:32.507594 0, 0xFFFF, sum = 0
4738 19:26:32.510553 1, 0xFFFF, sum = 0
4739 19:26:32.510675 2, 0xFFFF, sum = 0
4740 19:26:32.514212 3, 0xFFFF, sum = 0
4741 19:26:32.514351 4, 0xFFFF, sum = 0
4742 19:26:32.517477 5, 0xFFFF, sum = 0
4743 19:26:32.520964 6, 0xFFFF, sum = 0
4744 19:26:32.521127 7, 0xFFFF, sum = 0
4745 19:26:32.521241 8, 0x0, sum = 1
4746 19:26:32.523733 9, 0x0, sum = 2
4747 19:26:32.523868 10, 0x0, sum = 3
4748 19:26:32.527073 11, 0x0, sum = 4
4749 19:26:32.527207 best_step = 9
4750 19:26:32.527316
4751 19:26:32.527415 ==
4752 19:26:32.530648 Dram Type= 6, Freq= 0, CH_1, rank 1
4753 19:26:32.537391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4754 19:26:32.537556 ==
4755 19:26:32.537663 RX Vref Scan: 0
4756 19:26:32.537762
4757 19:26:32.540545 RX Vref 0 -> 0, step: 1
4758 19:26:32.540676
4759 19:26:32.543613 RX Delay -195 -> 252, step: 8
4760 19:26:32.547318 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4761 19:26:32.553568 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4762 19:26:32.557254 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4763 19:26:32.560202 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4764 19:26:32.563740 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4765 19:26:32.567019 iDelay=205, Bit 5, Center 52 (-99 ~ 204) 304
4766 19:26:32.573819 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4767 19:26:32.576899 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4768 19:26:32.584489 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4769 19:26:32.584675 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4770 19:26:32.610801 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4771 19:26:32.611006 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4772 19:26:32.611147 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4773 19:26:32.611240 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4774 19:26:32.611329 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4775 19:26:32.611636 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4776 19:26:32.611772 ==
4777 19:26:32.613863 Dram Type= 6, Freq= 0, CH_1, rank 1
4778 19:26:32.617536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4779 19:26:32.617736 ==
4780 19:26:32.617838 DQS Delay:
4781 19:26:32.620257 DQS0 = 0, DQS1 = 0
4782 19:26:32.620415 DQM Delay:
4783 19:26:32.624212 DQM0 = 38, DQM1 = 33
4784 19:26:32.624378 DQ Delay:
4785 19:26:32.626935 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =36
4786 19:26:32.630327 DQ4 =40, DQ5 =52, DQ6 =48, DQ7 =32
4787 19:26:32.634129 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =24
4788 19:26:32.637123 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4789 19:26:32.637329
4790 19:26:32.637461
4791 19:26:32.647026 [DQSOSCAuto] RK1, (LSB)MR18= 0x3341, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 400 ps
4792 19:26:32.647221 CH1 RK1: MR19=808, MR18=3341
4793 19:26:32.653781 CH1_RK1: MR19=0x808, MR18=0x3341, DQSOSC=397, MR23=63, INC=166, DEC=110
4794 19:26:32.656998 [RxdqsGatingPostProcess] freq 600
4795 19:26:32.663745 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4796 19:26:32.667447 Pre-setting of DQS Precalculation
4797 19:26:32.670577 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4798 19:26:32.676977 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4799 19:26:32.684099 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4800 19:26:32.684300
4801 19:26:32.687235
4802 19:26:32.687386 [Calibration Summary] 1200 Mbps
4803 19:26:32.690407 CH 0, Rank 0
4804 19:26:32.690565 SW Impedance : PASS
4805 19:26:32.693801 DUTY Scan : NO K
4806 19:26:32.697102 ZQ Calibration : PASS
4807 19:26:32.697276 Jitter Meter : NO K
4808 19:26:32.700489 CBT Training : PASS
4809 19:26:32.703868 Write leveling : PASS
4810 19:26:32.704055 RX DQS gating : PASS
4811 19:26:32.706956 RX DQ/DQS(RDDQC) : PASS
4812 19:26:32.710008 TX DQ/DQS : PASS
4813 19:26:32.710148 RX DATLAT : PASS
4814 19:26:32.713732 RX DQ/DQS(Engine): PASS
4815 19:26:32.717026 TX OE : NO K
4816 19:26:32.717183 All Pass.
4817 19:26:32.717286
4818 19:26:32.717348 CH 0, Rank 1
4819 19:26:32.720360 SW Impedance : PASS
4820 19:26:32.723488 DUTY Scan : NO K
4821 19:26:32.723632 ZQ Calibration : PASS
4822 19:26:32.727056 Jitter Meter : NO K
4823 19:26:32.727197 CBT Training : PASS
4824 19:26:32.730220 Write leveling : PASS
4825 19:26:32.733815 RX DQS gating : PASS
4826 19:26:32.733980 RX DQ/DQS(RDDQC) : PASS
4827 19:26:32.737148 TX DQ/DQS : PASS
4828 19:26:32.740634 RX DATLAT : PASS
4829 19:26:32.740839 RX DQ/DQS(Engine): PASS
4830 19:26:32.743496 TX OE : NO K
4831 19:26:32.743609 All Pass.
4832 19:26:32.743710
4833 19:26:32.747246 CH 1, Rank 0
4834 19:26:32.747366 SW Impedance : PASS
4835 19:26:32.750175 DUTY Scan : NO K
4836 19:26:32.753822 ZQ Calibration : PASS
4837 19:26:32.753956 Jitter Meter : NO K
4838 19:26:32.756966 CBT Training : PASS
4839 19:26:32.760674 Write leveling : PASS
4840 19:26:32.760770 RX DQS gating : PASS
4841 19:26:32.763774 RX DQ/DQS(RDDQC) : PASS
4842 19:26:32.763882 TX DQ/DQS : PASS
4843 19:26:32.767137 RX DATLAT : PASS
4844 19:26:32.770216 RX DQ/DQS(Engine): PASS
4845 19:26:32.770305 TX OE : NO K
4846 19:26:32.774017 All Pass.
4847 19:26:32.774103
4848 19:26:32.774166 CH 1, Rank 1
4849 19:26:32.776959 SW Impedance : PASS
4850 19:26:32.777090 DUTY Scan : NO K
4851 19:26:32.780672 ZQ Calibration : PASS
4852 19:26:32.783657 Jitter Meter : NO K
4853 19:26:32.783764 CBT Training : PASS
4854 19:26:32.787019 Write leveling : PASS
4855 19:26:32.790342 RX DQS gating : PASS
4856 19:26:32.790441 RX DQ/DQS(RDDQC) : PASS
4857 19:26:32.793911 TX DQ/DQS : PASS
4858 19:26:32.796986 RX DATLAT : PASS
4859 19:26:32.797116 RX DQ/DQS(Engine): PASS
4860 19:26:32.800665 TX OE : NO K
4861 19:26:32.800805 All Pass.
4862 19:26:32.800908
4863 19:26:32.803665 DramC Write-DBI off
4864 19:26:32.806892 PER_BANK_REFRESH: Hybrid Mode
4865 19:26:32.806992 TX_TRACKING: ON
4866 19:26:32.817084 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4867 19:26:32.820197 [FAST_K] Save calibration result to emmc
4868 19:26:32.823494 dramc_set_vcore_voltage set vcore to 662500
4869 19:26:32.826784 Read voltage for 933, 3
4870 19:26:32.826887 Vio18 = 0
4871 19:26:32.826951 Vcore = 662500
4872 19:26:32.830144 Vdram = 0
4873 19:26:32.830226 Vddq = 0
4874 19:26:32.830287 Vmddr = 0
4875 19:26:32.837293 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4876 19:26:32.840261 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4877 19:26:32.843929 MEM_TYPE=3, freq_sel=17
4878 19:26:32.847141 sv_algorithm_assistance_LP4_1600
4879 19:26:32.850336 ============ PULL DRAM RESETB DOWN ============
4880 19:26:32.853695 ========== PULL DRAM RESETB DOWN end =========
4881 19:26:32.860681 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4882 19:26:32.863871 ===================================
4883 19:26:32.864013 LPDDR4 DRAM CONFIGURATION
4884 19:26:32.866834 ===================================
4885 19:26:32.870412 EX_ROW_EN[0] = 0x0
4886 19:26:32.870541 EX_ROW_EN[1] = 0x0
4887 19:26:32.873564 LP4Y_EN = 0x0
4888 19:26:32.877245 WORK_FSP = 0x0
4889 19:26:32.877388 WL = 0x3
4890 19:26:32.880396 RL = 0x3
4891 19:26:32.880486 BL = 0x2
4892 19:26:32.883403 RPST = 0x0
4893 19:26:32.883499 RD_PRE = 0x0
4894 19:26:32.886982 WR_PRE = 0x1
4895 19:26:32.887078 WR_PST = 0x0
4896 19:26:32.890048 DBI_WR = 0x0
4897 19:26:32.890174 DBI_RD = 0x0
4898 19:26:32.893786 OTF = 0x1
4899 19:26:32.897140 ===================================
4900 19:26:32.900398 ===================================
4901 19:26:32.900584 ANA top config
4902 19:26:32.903812 ===================================
4903 19:26:32.906944 DLL_ASYNC_EN = 0
4904 19:26:32.910391 ALL_SLAVE_EN = 1
4905 19:26:32.910585 NEW_RANK_MODE = 1
4906 19:26:32.913722 DLL_IDLE_MODE = 1
4907 19:26:32.917151 LP45_APHY_COMB_EN = 1
4908 19:26:32.920472 TX_ODT_DIS = 1
4909 19:26:32.923650 NEW_8X_MODE = 1
4910 19:26:32.923831 ===================================
4911 19:26:32.927115 ===================================
4912 19:26:32.930101 data_rate = 1866
4913 19:26:32.933275 CKR = 1
4914 19:26:32.936639 DQ_P2S_RATIO = 8
4915 19:26:32.940085 ===================================
4916 19:26:32.943819 CA_P2S_RATIO = 8
4917 19:26:32.946739 DQ_CA_OPEN = 0
4918 19:26:32.946909 DQ_SEMI_OPEN = 0
4919 19:26:32.950233 CA_SEMI_OPEN = 0
4920 19:26:32.953996 CA_FULL_RATE = 0
4921 19:26:32.957328 DQ_CKDIV4_EN = 1
4922 19:26:32.959997 CA_CKDIV4_EN = 1
4923 19:26:32.963739 CA_PREDIV_EN = 0
4924 19:26:32.963865 PH8_DLY = 0
4925 19:26:32.967015 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4926 19:26:32.970076 DQ_AAMCK_DIV = 4
4927 19:26:32.974000 CA_AAMCK_DIV = 4
4928 19:26:32.976859 CA_ADMCK_DIV = 4
4929 19:26:32.980083 DQ_TRACK_CA_EN = 0
4930 19:26:32.980207 CA_PICK = 933
4931 19:26:32.983523 CA_MCKIO = 933
4932 19:26:32.987196 MCKIO_SEMI = 0
4933 19:26:32.990319 PLL_FREQ = 3732
4934 19:26:32.993556 DQ_UI_PI_RATIO = 32
4935 19:26:32.996983 CA_UI_PI_RATIO = 0
4936 19:26:33.000212 ===================================
4937 19:26:33.003375 ===================================
4938 19:26:33.003510 memory_type:LPDDR4
4939 19:26:33.006743 GP_NUM : 10
4940 19:26:33.010393 SRAM_EN : 1
4941 19:26:33.010555 MD32_EN : 0
4942 19:26:33.013565 ===================================
4943 19:26:33.017419 [ANA_INIT] >>>>>>>>>>>>>>
4944 19:26:33.020210 <<<<<< [CONFIGURE PHASE]: ANA_TX
4945 19:26:33.023373 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4946 19:26:33.027008 ===================================
4947 19:26:33.030601 data_rate = 1866,PCW = 0X8f00
4948 19:26:33.033446 ===================================
4949 19:26:33.036826 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4950 19:26:33.040372 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4951 19:26:33.046894 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4952 19:26:33.050767 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4953 19:26:33.053862 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4954 19:26:33.057493 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4955 19:26:33.060165 [ANA_INIT] flow start
4956 19:26:33.063743 [ANA_INIT] PLL >>>>>>>>
4957 19:26:33.063913 [ANA_INIT] PLL <<<<<<<<
4958 19:26:33.067412 [ANA_INIT] MIDPI >>>>>>>>
4959 19:26:33.070422 [ANA_INIT] MIDPI <<<<<<<<
4960 19:26:33.070585 [ANA_INIT] DLL >>>>>>>>
4961 19:26:33.074241 [ANA_INIT] flow end
4962 19:26:33.076987 ============ LP4 DIFF to SE enter ============
4963 19:26:33.083883 ============ LP4 DIFF to SE exit ============
4964 19:26:33.084088 [ANA_INIT] <<<<<<<<<<<<<
4965 19:26:33.087542 [Flow] Enable top DCM control >>>>>
4966 19:26:33.090642 [Flow] Enable top DCM control <<<<<
4967 19:26:33.093550 Enable DLL master slave shuffle
4968 19:26:33.100291 ==============================================================
4969 19:26:33.100479 Gating Mode config
4970 19:26:33.107252 ==============================================================
4971 19:26:33.110369 Config description:
4972 19:26:33.117105 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4973 19:26:33.123979 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4974 19:26:33.130842 SELPH_MODE 0: By rank 1: By Phase
4975 19:26:33.133810 ==============================================================
4976 19:26:33.137125 GAT_TRACK_EN = 1
4977 19:26:33.140207 RX_GATING_MODE = 2
4978 19:26:33.143506 RX_GATING_TRACK_MODE = 2
4979 19:26:33.147195 SELPH_MODE = 1
4980 19:26:33.150385 PICG_EARLY_EN = 1
4981 19:26:33.153738 VALID_LAT_VALUE = 1
4982 19:26:33.160510 ==============================================================
4983 19:26:33.163810 Enter into Gating configuration >>>>
4984 19:26:33.166783 Exit from Gating configuration <<<<
4985 19:26:33.170367 Enter into DVFS_PRE_config >>>>>
4986 19:26:33.180329 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4987 19:26:33.183896 Exit from DVFS_PRE_config <<<<<
4988 19:26:33.187320 Enter into PICG configuration >>>>
4989 19:26:33.190732 Exit from PICG configuration <<<<
4990 19:26:33.190910 [RX_INPUT] configuration >>>>>
4991 19:26:33.194330 [RX_INPUT] configuration <<<<<
4992 19:26:33.200615 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4993 19:26:33.203655 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4994 19:26:33.210374 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4995 19:26:33.217028 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4996 19:26:33.224317 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4997 19:26:33.230762 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4998 19:26:33.233899 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4999 19:26:33.237951 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5000 19:26:33.240727 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5001 19:26:33.247586 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5002 19:26:33.250716 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5003 19:26:33.254236 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5004 19:26:33.257101 ===================================
5005 19:26:33.260610 LPDDR4 DRAM CONFIGURATION
5006 19:26:33.263810 ===================================
5007 19:26:33.267594 EX_ROW_EN[0] = 0x0
5008 19:26:33.267792 EX_ROW_EN[1] = 0x0
5009 19:26:33.270760 LP4Y_EN = 0x0
5010 19:26:33.270932 WORK_FSP = 0x0
5011 19:26:33.273873 WL = 0x3
5012 19:26:33.274020 RL = 0x3
5013 19:26:33.277462 BL = 0x2
5014 19:26:33.277653 RPST = 0x0
5015 19:26:33.280716 RD_PRE = 0x0
5016 19:26:33.280908 WR_PRE = 0x1
5017 19:26:33.284007 WR_PST = 0x0
5018 19:26:33.284198 DBI_WR = 0x0
5019 19:26:33.287306 DBI_RD = 0x0
5020 19:26:33.287491 OTF = 0x1
5021 19:26:33.290845 ===================================
5022 19:26:33.294172 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5023 19:26:33.300441 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5024 19:26:33.304088 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5025 19:26:33.307235 ===================================
5026 19:26:33.310982 LPDDR4 DRAM CONFIGURATION
5027 19:26:33.313899 ===================================
5028 19:26:33.314084 EX_ROW_EN[0] = 0x10
5029 19:26:33.317607 EX_ROW_EN[1] = 0x0
5030 19:26:33.320526 LP4Y_EN = 0x0
5031 19:26:33.320689 WORK_FSP = 0x0
5032 19:26:33.324299 WL = 0x3
5033 19:26:33.324486 RL = 0x3
5034 19:26:33.327566 BL = 0x2
5035 19:26:33.327737 RPST = 0x0
5036 19:26:33.330548 RD_PRE = 0x0
5037 19:26:33.330693 WR_PRE = 0x1
5038 19:26:33.334254 WR_PST = 0x0
5039 19:26:33.334418 DBI_WR = 0x0
5040 19:26:33.337160 DBI_RD = 0x0
5041 19:26:33.337339 OTF = 0x1
5042 19:26:33.340835 ===================================
5043 19:26:33.347036 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5044 19:26:33.351163 nWR fixed to 30
5045 19:26:33.354477 [ModeRegInit_LP4] CH0 RK0
5046 19:26:33.354612 [ModeRegInit_LP4] CH0 RK1
5047 19:26:33.358029 [ModeRegInit_LP4] CH1 RK0
5048 19:26:33.361891 [ModeRegInit_LP4] CH1 RK1
5049 19:26:33.362026 match AC timing 9
5050 19:26:33.368387 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5051 19:26:33.371586 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5052 19:26:33.374895 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5053 19:26:33.381682 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5054 19:26:33.385045 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5055 19:26:33.385228 ==
5056 19:26:33.388257 Dram Type= 6, Freq= 0, CH_0, rank 0
5057 19:26:33.391506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5058 19:26:33.391641 ==
5059 19:26:33.398613 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5060 19:26:33.404737 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5061 19:26:33.407885 [CA 0] Center 38 (8~69) winsize 62
5062 19:26:33.411535 [CA 1] Center 38 (8~69) winsize 62
5063 19:26:33.414530 [CA 2] Center 35 (5~66) winsize 62
5064 19:26:33.418184 [CA 3] Center 35 (4~66) winsize 63
5065 19:26:33.421381 [CA 4] Center 34 (4~65) winsize 62
5066 19:26:33.424746 [CA 5] Center 34 (4~64) winsize 61
5067 19:26:33.424908
5068 19:26:33.428106 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5069 19:26:33.428253
5070 19:26:33.431728 [CATrainingPosCal] consider 1 rank data
5071 19:26:33.434430 u2DelayCellTimex100 = 270/100 ps
5072 19:26:33.437878 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5073 19:26:33.441093 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5074 19:26:33.444693 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5075 19:26:33.447779 CA3 delay=35 (4~66),Diff = 1 PI (6 cell)
5076 19:26:33.451468 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5077 19:26:33.454468 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5078 19:26:33.454624
5079 19:26:33.461257 CA PerBit enable=1, Macro0, CA PI delay=34
5080 19:26:33.461409
5081 19:26:33.461486 [CBTSetCACLKResult] CA Dly = 34
5082 19:26:33.464717 CS Dly: 6 (0~37)
5083 19:26:33.464880 ==
5084 19:26:33.467613 Dram Type= 6, Freq= 0, CH_0, rank 1
5085 19:26:33.471320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5086 19:26:33.471504 ==
5087 19:26:33.477848 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5088 19:26:33.484966 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5089 19:26:33.487912 [CA 0] Center 38 (7~69) winsize 63
5090 19:26:33.491368 [CA 1] Center 38 (8~69) winsize 62
5091 19:26:33.494364 [CA 2] Center 35 (5~66) winsize 62
5092 19:26:33.497700 [CA 3] Center 35 (5~66) winsize 62
5093 19:26:33.501127 [CA 4] Center 34 (4~64) winsize 61
5094 19:26:33.504349 [CA 5] Center 33 (3~64) winsize 62
5095 19:26:33.504512
5096 19:26:33.507808 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5097 19:26:33.507949
5098 19:26:33.511067 [CATrainingPosCal] consider 2 rank data
5099 19:26:33.514259 u2DelayCellTimex100 = 270/100 ps
5100 19:26:33.517785 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5101 19:26:33.520880 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5102 19:26:33.524413 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5103 19:26:33.527573 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5104 19:26:33.531098 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5105 19:26:33.534644 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5106 19:26:33.534795
5107 19:26:33.541086 CA PerBit enable=1, Macro0, CA PI delay=34
5108 19:26:33.541269
5109 19:26:33.544255 [CBTSetCACLKResult] CA Dly = 34
5110 19:26:33.544375 CS Dly: 7 (0~39)
5111 19:26:33.544469
5112 19:26:33.547890 ----->DramcWriteLeveling(PI) begin...
5113 19:26:33.548020 ==
5114 19:26:33.550826 Dram Type= 6, Freq= 0, CH_0, rank 0
5115 19:26:33.554121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5116 19:26:33.554261 ==
5117 19:26:33.557811 Write leveling (Byte 0): 31 => 31
5118 19:26:33.561133 Write leveling (Byte 1): 30 => 30
5119 19:26:33.564049 DramcWriteLeveling(PI) end<-----
5120 19:26:33.564182
5121 19:26:33.564273 ==
5122 19:26:33.567347 Dram Type= 6, Freq= 0, CH_0, rank 0
5123 19:26:33.574071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5124 19:26:33.574219 ==
5125 19:26:33.574290 [Gating] SW mode calibration
5126 19:26:33.584468 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5127 19:26:33.587674 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5128 19:26:33.590971 0 14 0 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
5129 19:26:33.597529 0 14 4 | B1->B0 | 2c2c 3434 | 1 1 | (0 0) (1 1)
5130 19:26:33.601048 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5131 19:26:33.604233 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5132 19:26:33.610648 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5133 19:26:33.614077 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5134 19:26:33.617725 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5135 19:26:33.624229 0 14 28 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 0)
5136 19:26:33.627338 0 15 0 | B1->B0 | 3333 3030 | 1 0 | (0 1) (0 1)
5137 19:26:33.631048 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (1 0) (1 0)
5138 19:26:33.637423 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5139 19:26:33.641015 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5140 19:26:33.643957 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5141 19:26:33.650738 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5142 19:26:33.654180 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5143 19:26:33.657249 0 15 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5144 19:26:33.664184 1 0 0 | B1->B0 | 3333 4040 | 0 0 | (0 0) (0 0)
5145 19:26:33.667751 1 0 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5146 19:26:33.671301 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5147 19:26:33.674089 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5148 19:26:33.681197 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5149 19:26:33.684290 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5150 19:26:33.687374 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5151 19:26:33.694388 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5152 19:26:33.697878 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5153 19:26:33.700998 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 19:26:33.707528 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 19:26:33.710924 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 19:26:33.714156 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 19:26:33.720931 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 19:26:33.724630 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 19:26:33.727898 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 19:26:33.734571 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 19:26:33.737687 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 19:26:33.741318 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 19:26:33.744452 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 19:26:33.751194 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 19:26:33.754627 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 19:26:33.757869 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 19:26:33.764204 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5168 19:26:33.767700 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5169 19:26:33.770957 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5170 19:26:33.774609 Total UI for P1: 0, mck2ui 16
5171 19:26:33.778068 best dqsien dly found for B0: ( 1, 2, 30)
5172 19:26:33.780888 Total UI for P1: 0, mck2ui 16
5173 19:26:33.784383 best dqsien dly found for B1: ( 1, 2, 30)
5174 19:26:33.788153 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5175 19:26:33.791018 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5176 19:26:33.791148
5177 19:26:33.798077 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5178 19:26:33.800861 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5179 19:26:33.801041 [Gating] SW calibration Done
5180 19:26:33.804357 ==
5181 19:26:33.807689 Dram Type= 6, Freq= 0, CH_0, rank 0
5182 19:26:33.811318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5183 19:26:33.811485 ==
5184 19:26:33.811570 RX Vref Scan: 0
5185 19:26:33.811631
5186 19:26:33.814818 RX Vref 0 -> 0, step: 1
5187 19:26:33.814962
5188 19:26:33.817582 RX Delay -80 -> 252, step: 8
5189 19:26:33.821064 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5190 19:26:33.824432 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5191 19:26:33.828047 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5192 19:26:33.834834 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5193 19:26:33.837709 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5194 19:26:33.841525 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5195 19:26:33.844323 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5196 19:26:33.848055 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5197 19:26:33.851149 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5198 19:26:33.857866 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5199 19:26:33.861414 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5200 19:26:33.865230 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5201 19:26:33.868048 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5202 19:26:33.871506 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5203 19:26:33.874830 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5204 19:26:33.881643 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5205 19:26:33.881785 ==
5206 19:26:33.884673 Dram Type= 6, Freq= 0, CH_0, rank 0
5207 19:26:33.887984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5208 19:26:33.888145 ==
5209 19:26:33.888235 DQS Delay:
5210 19:26:33.891766 DQS0 = 0, DQS1 = 0
5211 19:26:33.891883 DQM Delay:
5212 19:26:33.894624 DQM0 = 97, DQM1 = 87
5213 19:26:33.894725 DQ Delay:
5214 19:26:33.898398 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5215 19:26:33.901327 DQ4 =99, DQ5 =87, DQ6 =111, DQ7 =103
5216 19:26:33.905118 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5217 19:26:33.908044 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =95
5218 19:26:33.908160
5219 19:26:33.908247
5220 19:26:33.908316 ==
5221 19:26:33.911189 Dram Type= 6, Freq= 0, CH_0, rank 0
5222 19:26:33.914551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5223 19:26:33.914676 ==
5224 19:26:33.914752
5225 19:26:33.914813
5226 19:26:33.917995 TX Vref Scan disable
5227 19:26:33.921725 == TX Byte 0 ==
5228 19:26:33.924609 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5229 19:26:33.928555 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5230 19:26:33.931388 == TX Byte 1 ==
5231 19:26:33.934907 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5232 19:26:33.938556 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5233 19:26:33.938697 ==
5234 19:26:33.941826 Dram Type= 6, Freq= 0, CH_0, rank 0
5235 19:26:33.947919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5236 19:26:33.948088 ==
5237 19:26:33.948197
5238 19:26:33.948287
5239 19:26:33.948381 TX Vref Scan disable
5240 19:26:33.952181 == TX Byte 0 ==
5241 19:26:33.955415 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5242 19:26:33.962039 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5243 19:26:33.962182 == TX Byte 1 ==
5244 19:26:33.965050 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5245 19:26:33.968784 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5246 19:26:33.971932
5247 19:26:33.972081 [DATLAT]
5248 19:26:33.972202 Freq=933, CH0 RK0
5249 19:26:33.972276
5250 19:26:33.975051 DATLAT Default: 0xd
5251 19:26:33.975146 0, 0xFFFF, sum = 0
5252 19:26:33.978559 1, 0xFFFF, sum = 0
5253 19:26:33.978669 2, 0xFFFF, sum = 0
5254 19:26:33.982109 3, 0xFFFF, sum = 0
5255 19:26:33.982216 4, 0xFFFF, sum = 0
5256 19:26:33.984987 5, 0xFFFF, sum = 0
5257 19:26:33.988879 6, 0xFFFF, sum = 0
5258 19:26:33.989040 7, 0xFFFF, sum = 0
5259 19:26:33.992199 8, 0xFFFF, sum = 0
5260 19:26:33.992329 9, 0xFFFF, sum = 0
5261 19:26:33.995458 10, 0x0, sum = 1
5262 19:26:33.995609 11, 0x0, sum = 2
5263 19:26:33.995710 12, 0x0, sum = 3
5264 19:26:33.998374 13, 0x0, sum = 4
5265 19:26:33.998480 best_step = 11
5266 19:26:33.998549
5267 19:26:34.001954 ==
5268 19:26:34.002071 Dram Type= 6, Freq= 0, CH_0, rank 0
5269 19:26:34.008733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5270 19:26:34.008874 ==
5271 19:26:34.008949 RX Vref Scan: 1
5272 19:26:34.009010
5273 19:26:34.011999 RX Vref 0 -> 0, step: 1
5274 19:26:34.012144
5275 19:26:34.014971 RX Delay -61 -> 252, step: 4
5276 19:26:34.015115
5277 19:26:34.018306 Set Vref, RX VrefLevel [Byte0]: 52
5278 19:26:34.021906 [Byte1]: 52
5279 19:26:34.022074
5280 19:26:34.025368 Final RX Vref Byte 0 = 52 to rank0
5281 19:26:34.029151 Final RX Vref Byte 1 = 52 to rank0
5282 19:26:34.031724 Final RX Vref Byte 0 = 52 to rank1
5283 19:26:34.035231 Final RX Vref Byte 1 = 52 to rank1==
5284 19:26:34.038556 Dram Type= 6, Freq= 0, CH_0, rank 0
5285 19:26:34.041923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5286 19:26:34.042053 ==
5287 19:26:34.045443 DQS Delay:
5288 19:26:34.045611 DQS0 = 0, DQS1 = 0
5289 19:26:34.048771 DQM Delay:
5290 19:26:34.048917 DQM0 = 97, DQM1 = 88
5291 19:26:34.049031 DQ Delay:
5292 19:26:34.051754 DQ0 =98, DQ1 =98, DQ2 =94, DQ3 =94
5293 19:26:34.055547 DQ4 =100, DQ5 =86, DQ6 =104, DQ7 =102
5294 19:26:34.058492 DQ8 =78, DQ9 =76, DQ10 =90, DQ11 =80
5295 19:26:34.062345 DQ12 =96, DQ13 =92, DQ14 =100, DQ15 =96
5296 19:26:34.062507
5297 19:26:34.062625
5298 19:26:34.071995 [DQSOSCAuto] RK0, (LSB)MR18= 0x1601, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 414 ps
5299 19:26:34.075269 CH0 RK0: MR19=505, MR18=1601
5300 19:26:34.081858 CH0_RK0: MR19=0x505, MR18=0x1601, DQSOSC=414, MR23=63, INC=63, DEC=42
5301 19:26:34.082006
5302 19:26:34.085000 ----->DramcWriteLeveling(PI) begin...
5303 19:26:34.085110 ==
5304 19:26:34.088487 Dram Type= 6, Freq= 0, CH_0, rank 1
5305 19:26:34.092175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5306 19:26:34.092335 ==
5307 19:26:34.094853 Write leveling (Byte 0): 29 => 29
5308 19:26:34.098357 Write leveling (Byte 1): 26 => 26
5309 19:26:34.101594 DramcWriteLeveling(PI) end<-----
5310 19:26:34.101726
5311 19:26:34.101821 ==
5312 19:26:34.104969 Dram Type= 6, Freq= 0, CH_0, rank 1
5313 19:26:34.108630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5314 19:26:34.108771 ==
5315 19:26:34.111768 [Gating] SW mode calibration
5316 19:26:34.118337 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5317 19:26:34.124949 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5318 19:26:34.128510 0 14 0 | B1->B0 | 2423 3434 | 1 1 | (0 0) (1 1)
5319 19:26:34.131985 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5320 19:26:34.138343 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5321 19:26:34.142091 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5322 19:26:34.145106 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5323 19:26:34.152171 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5324 19:26:34.155001 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
5325 19:26:34.158425 0 14 28 | B1->B0 | 3333 3030 | 0 0 | (0 0) (1 1)
5326 19:26:34.165003 0 15 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 1) (1 0)
5327 19:26:34.168133 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5328 19:26:34.171685 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5329 19:26:34.174847 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5330 19:26:34.181535 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5331 19:26:34.185170 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5332 19:26:34.188349 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5333 19:26:34.195005 0 15 28 | B1->B0 | 2424 3434 | 0 0 | (0 0) (0 0)
5334 19:26:34.198392 1 0 0 | B1->B0 | 3838 4646 | 0 0 | (1 1) (0 0)
5335 19:26:34.202139 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5336 19:26:34.208732 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5337 19:26:34.212103 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5338 19:26:34.214838 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5339 19:26:34.221538 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5340 19:26:34.225127 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5341 19:26:34.228623 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5342 19:26:34.235196 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5343 19:26:34.238633 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5344 19:26:34.241806 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 19:26:34.248587 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 19:26:34.251583 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 19:26:34.254833 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 19:26:34.261547 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 19:26:34.265598 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 19:26:34.268332 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 19:26:34.272138 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 19:26:34.278146 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 19:26:34.281616 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 19:26:34.285284 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 19:26:34.291839 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5356 19:26:34.295031 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5357 19:26:34.298119 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5358 19:26:34.301877 Total UI for P1: 0, mck2ui 16
5359 19:26:34.304745 best dqsien dly found for B0: ( 1, 2, 22)
5360 19:26:34.311421 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5361 19:26:34.311565 Total UI for P1: 0, mck2ui 16
5362 19:26:34.318333 best dqsien dly found for B1: ( 1, 2, 30)
5363 19:26:34.321494 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5364 19:26:34.324689 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5365 19:26:34.324848
5366 19:26:34.328266 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5367 19:26:34.331798 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5368 19:26:34.334711 [Gating] SW calibration Done
5369 19:26:34.334861 ==
5370 19:26:34.338554 Dram Type= 6, Freq= 0, CH_0, rank 1
5371 19:26:34.341467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5372 19:26:34.341626 ==
5373 19:26:34.344847 RX Vref Scan: 0
5374 19:26:34.344998
5375 19:26:34.345094 RX Vref 0 -> 0, step: 1
5376 19:26:34.345181
5377 19:26:34.348229 RX Delay -80 -> 252, step: 8
5378 19:26:34.351468 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5379 19:26:34.358032 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5380 19:26:34.361436 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5381 19:26:34.364561 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5382 19:26:34.367999 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5383 19:26:34.371423 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5384 19:26:34.374648 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5385 19:26:34.381625 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5386 19:26:34.384908 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5387 19:26:34.388227 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5388 19:26:34.391346 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5389 19:26:34.395022 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5390 19:26:34.401075 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5391 19:26:34.404839 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5392 19:26:34.408376 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5393 19:26:34.411513 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5394 19:26:34.411657 ==
5395 19:26:34.414562 Dram Type= 6, Freq= 0, CH_0, rank 1
5396 19:26:34.418187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5397 19:26:34.418333 ==
5398 19:26:34.421154 DQS Delay:
5399 19:26:34.421303 DQS0 = 0, DQS1 = 0
5400 19:26:34.424550 DQM Delay:
5401 19:26:34.424677 DQM0 = 96, DQM1 = 86
5402 19:26:34.424780 DQ Delay:
5403 19:26:34.427927 DQ0 =99, DQ1 =95, DQ2 =95, DQ3 =91
5404 19:26:34.431628 DQ4 =95, DQ5 =87, DQ6 =107, DQ7 =103
5405 19:26:34.434649 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5406 19:26:34.437889 DQ12 =87, DQ13 =91, DQ14 =95, DQ15 =95
5407 19:26:34.438059
5408 19:26:34.438169
5409 19:26:34.441577 ==
5410 19:26:34.441695 Dram Type= 6, Freq= 0, CH_0, rank 1
5411 19:26:34.448104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5412 19:26:34.448291 ==
5413 19:26:34.448399
5414 19:26:34.448491
5415 19:26:34.451209 TX Vref Scan disable
5416 19:26:34.451340 == TX Byte 0 ==
5417 19:26:34.454952 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5418 19:26:34.461509 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5419 19:26:34.461689 == TX Byte 1 ==
5420 19:26:34.465167 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5421 19:26:34.471580 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5422 19:26:34.471763 ==
5423 19:26:34.474980 Dram Type= 6, Freq= 0, CH_0, rank 1
5424 19:26:34.478610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5425 19:26:34.478795 ==
5426 19:26:34.478908
5427 19:26:34.478999
5428 19:26:34.481599 TX Vref Scan disable
5429 19:26:34.484954 == TX Byte 0 ==
5430 19:26:34.488214 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5431 19:26:34.491961 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5432 19:26:34.494933 == TX Byte 1 ==
5433 19:26:34.498012 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5434 19:26:34.501422 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5435 19:26:34.501565
5436 19:26:34.501640 [DATLAT]
5437 19:26:34.504838 Freq=933, CH0 RK1
5438 19:26:34.504988
5439 19:26:34.505100 DATLAT Default: 0xb
5440 19:26:34.507948 0, 0xFFFF, sum = 0
5441 19:26:34.511646 1, 0xFFFF, sum = 0
5442 19:26:34.511785 2, 0xFFFF, sum = 0
5443 19:26:34.514718 3, 0xFFFF, sum = 0
5444 19:26:34.514848 4, 0xFFFF, sum = 0
5445 19:26:34.518229 5, 0xFFFF, sum = 0
5446 19:26:34.518353 6, 0xFFFF, sum = 0
5447 19:26:34.521703 7, 0xFFFF, sum = 0
5448 19:26:34.521848 8, 0xFFFF, sum = 0
5449 19:26:34.524723 9, 0xFFFF, sum = 0
5450 19:26:34.524849 10, 0x0, sum = 1
5451 19:26:34.528520 11, 0x0, sum = 2
5452 19:26:34.528664 12, 0x0, sum = 3
5453 19:26:34.531571 13, 0x0, sum = 4
5454 19:26:34.531737 best_step = 11
5455 19:26:34.531838
5456 19:26:34.531942 ==
5457 19:26:34.534619 Dram Type= 6, Freq= 0, CH_0, rank 1
5458 19:26:34.538153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5459 19:26:34.538342 ==
5460 19:26:34.541220 RX Vref Scan: 0
5461 19:26:34.541377
5462 19:26:34.544778 RX Vref 0 -> 0, step: 1
5463 19:26:34.544940
5464 19:26:34.545049 RX Delay -61 -> 252, step: 4
5465 19:26:34.552718 iDelay=199, Bit 0, Center 96 (3 ~ 190) 188
5466 19:26:34.555693 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5467 19:26:34.559059 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5468 19:26:34.562696 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5469 19:26:34.566045 iDelay=199, Bit 4, Center 96 (7 ~ 186) 180
5470 19:26:34.569040 iDelay=199, Bit 5, Center 84 (-9 ~ 178) 188
5471 19:26:34.575747 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5472 19:26:34.579200 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5473 19:26:34.582405 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5474 19:26:34.585833 iDelay=199, Bit 9, Center 78 (-9 ~ 166) 176
5475 19:26:34.589314 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5476 19:26:34.592822 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5477 19:26:34.599540 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5478 19:26:34.602548 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5479 19:26:34.606205 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5480 19:26:34.609148 iDelay=199, Bit 15, Center 92 (3 ~ 182) 180
5481 19:26:34.609322 ==
5482 19:26:34.612765 Dram Type= 6, Freq= 0, CH_0, rank 1
5483 19:26:34.616372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5484 19:26:34.619517 ==
5485 19:26:34.619664 DQS Delay:
5486 19:26:34.619774 DQS0 = 0, DQS1 = 0
5487 19:26:34.622787 DQM Delay:
5488 19:26:34.622912 DQM0 = 95, DQM1 = 86
5489 19:26:34.623002 DQ Delay:
5490 19:26:34.626147 DQ0 =96, DQ1 =96, DQ2 =92, DQ3 =94
5491 19:26:34.629764 DQ4 =96, DQ5 =84, DQ6 =104, DQ7 =102
5492 19:26:34.632910 DQ8 =80, DQ9 =78, DQ10 =88, DQ11 =78
5493 19:26:34.636006 DQ12 =90, DQ13 =90, DQ14 =98, DQ15 =92
5494 19:26:34.639142
5495 19:26:34.639289
5496 19:26:34.646291 [DQSOSCAuto] RK1, (LSB)MR18= 0x1604, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 414 ps
5497 19:26:34.649088 CH0 RK1: MR19=505, MR18=1604
5498 19:26:34.655722 CH0_RK1: MR19=0x505, MR18=0x1604, DQSOSC=414, MR23=63, INC=63, DEC=42
5499 19:26:34.658869 [RxdqsGatingPostProcess] freq 933
5500 19:26:34.662601 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5501 19:26:34.665537 best DQS0 dly(2T, 0.5T) = (0, 10)
5502 19:26:34.669178 best DQS1 dly(2T, 0.5T) = (0, 10)
5503 19:26:34.672779 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5504 19:26:34.675662 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5505 19:26:34.679305 best DQS0 dly(2T, 0.5T) = (0, 10)
5506 19:26:34.682328 best DQS1 dly(2T, 0.5T) = (0, 10)
5507 19:26:34.685724 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5508 19:26:34.688946 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5509 19:26:34.692549 Pre-setting of DQS Precalculation
5510 19:26:34.696130 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5511 19:26:34.696291 ==
5512 19:26:34.698917 Dram Type= 6, Freq= 0, CH_1, rank 0
5513 19:26:34.702666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5514 19:26:34.706111 ==
5515 19:26:34.708981 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5516 19:26:34.715656 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5517 19:26:34.719288 [CA 0] Center 36 (6~67) winsize 62
5518 19:26:34.722259 [CA 1] Center 36 (6~67) winsize 62
5519 19:26:34.725492 [CA 2] Center 34 (4~64) winsize 61
5520 19:26:34.729129 [CA 3] Center 33 (3~64) winsize 62
5521 19:26:34.732547 [CA 4] Center 34 (4~64) winsize 61
5522 19:26:34.735659 [CA 5] Center 33 (3~64) winsize 62
5523 19:26:34.735825
5524 19:26:34.738769 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5525 19:26:34.738911
5526 19:26:34.742281 [CATrainingPosCal] consider 1 rank data
5527 19:26:34.745963 u2DelayCellTimex100 = 270/100 ps
5528 19:26:34.748985 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5529 19:26:34.752081 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5530 19:26:34.755543 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5531 19:26:34.762265 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5532 19:26:34.765507 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5533 19:26:34.768591 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5534 19:26:34.768712
5535 19:26:34.772269 CA PerBit enable=1, Macro0, CA PI delay=33
5536 19:26:34.772376
5537 19:26:34.775135 [CBTSetCACLKResult] CA Dly = 33
5538 19:26:34.775263 CS Dly: 4 (0~35)
5539 19:26:34.775358 ==
5540 19:26:34.778864 Dram Type= 6, Freq= 0, CH_1, rank 1
5541 19:26:34.785570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5542 19:26:34.785704 ==
5543 19:26:34.788961 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5544 19:26:34.795559 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5545 19:26:34.799287 [CA 0] Center 36 (6~67) winsize 62
5546 19:26:34.802155 [CA 1] Center 37 (7~67) winsize 61
5547 19:26:34.805463 [CA 2] Center 33 (3~64) winsize 62
5548 19:26:34.808834 [CA 3] Center 33 (3~64) winsize 62
5549 19:26:34.812188 [CA 4] Center 34 (4~65) winsize 62
5550 19:26:34.815800 [CA 5] Center 32 (2~63) winsize 62
5551 19:26:34.815939
5552 19:26:34.819114 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5553 19:26:34.819252
5554 19:26:34.822230 [CATrainingPosCal] consider 2 rank data
5555 19:26:34.825587 u2DelayCellTimex100 = 270/100 ps
5556 19:26:34.828719 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5557 19:26:34.832611 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5558 19:26:34.835384 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5559 19:26:34.838819 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5560 19:26:34.845790 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5561 19:26:34.849094 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5562 19:26:34.849244
5563 19:26:34.852742 CA PerBit enable=1, Macro0, CA PI delay=33
5564 19:26:34.852860
5565 19:26:34.855912 [CBTSetCACLKResult] CA Dly = 33
5566 19:26:34.856024 CS Dly: 5 (0~37)
5567 19:26:34.856096
5568 19:26:34.858925 ----->DramcWriteLeveling(PI) begin...
5569 19:26:34.859024 ==
5570 19:26:34.862347 Dram Type= 6, Freq= 0, CH_1, rank 0
5571 19:26:34.868802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5572 19:26:34.868946 ==
5573 19:26:34.872221 Write leveling (Byte 0): 29 => 29
5574 19:26:34.872400 Write leveling (Byte 1): 31 => 31
5575 19:26:34.875634 DramcWriteLeveling(PI) end<-----
5576 19:26:34.875798
5577 19:26:34.879194 ==
5578 19:26:34.879338 Dram Type= 6, Freq= 0, CH_1, rank 0
5579 19:26:34.885923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5580 19:26:34.886118 ==
5581 19:26:34.888969 [Gating] SW mode calibration
5582 19:26:34.895880 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5583 19:26:34.898958 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5584 19:26:34.905900 0 14 0 | B1->B0 | 3030 3333 | 0 1 | (0 0) (1 1)
5585 19:26:34.909134 0 14 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5586 19:26:34.912301 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5587 19:26:34.919075 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5588 19:26:34.922429 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5589 19:26:34.925660 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5590 19:26:34.928978 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
5591 19:26:34.935513 0 14 28 | B1->B0 | 3030 3030 | 1 1 | (1 0) (1 0)
5592 19:26:34.939046 0 15 0 | B1->B0 | 2b2b 2828 | 0 0 | (0 0) (0 0)
5593 19:26:34.942639 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5594 19:26:34.948928 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5595 19:26:34.952513 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5596 19:26:34.955385 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5597 19:26:34.962460 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5598 19:26:34.965901 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5599 19:26:34.968882 0 15 28 | B1->B0 | 3030 2b2b | 0 0 | (0 0) (0 0)
5600 19:26:34.975449 1 0 0 | B1->B0 | 4141 4141 | 0 0 | (0 0) (0 0)
5601 19:26:34.978736 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5602 19:26:34.982578 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5603 19:26:34.988906 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5604 19:26:34.992438 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5605 19:26:34.995698 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5606 19:26:35.002464 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5607 19:26:35.005945 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5608 19:26:35.008841 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 19:26:35.015692 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 19:26:35.018623 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 19:26:35.021999 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 19:26:35.028695 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 19:26:35.032156 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 19:26:35.035365 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 19:26:35.038988 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 19:26:35.045554 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 19:26:35.048686 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 19:26:35.052541 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 19:26:35.059061 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 19:26:35.062302 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 19:26:35.065560 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 19:26:35.071955 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 19:26:35.075768 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5624 19:26:35.078766 Total UI for P1: 0, mck2ui 16
5625 19:26:35.082384 best dqsien dly found for B0: ( 1, 2, 26)
5626 19:26:35.085452 Total UI for P1: 0, mck2ui 16
5627 19:26:35.089018 best dqsien dly found for B1: ( 1, 2, 26)
5628 19:26:35.092181 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5629 19:26:35.095263 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5630 19:26:35.095395
5631 19:26:35.098919 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5632 19:26:35.101922 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5633 19:26:35.105252 [Gating] SW calibration Done
5634 19:26:35.105385 ==
5635 19:26:35.108793 Dram Type= 6, Freq= 0, CH_1, rank 0
5636 19:26:35.112400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5637 19:26:35.115536 ==
5638 19:26:35.115664 RX Vref Scan: 0
5639 19:26:35.115738
5640 19:26:35.119252 RX Vref 0 -> 0, step: 1
5641 19:26:35.119367
5642 19:26:35.119436 RX Delay -80 -> 252, step: 8
5643 19:26:35.125853 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5644 19:26:35.129278 iDelay=200, Bit 1, Center 95 (0 ~ 191) 192
5645 19:26:35.132413 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5646 19:26:35.136126 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5647 19:26:35.139139 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5648 19:26:35.143032 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5649 19:26:35.148968 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5650 19:26:35.152386 iDelay=200, Bit 7, Center 91 (-8 ~ 191) 200
5651 19:26:35.155680 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5652 19:26:35.159253 iDelay=200, Bit 9, Center 75 (-24 ~ 175) 200
5653 19:26:35.162571 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5654 19:26:35.168997 iDelay=200, Bit 11, Center 83 (-16 ~ 183) 200
5655 19:26:35.172217 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5656 19:26:35.175698 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5657 19:26:35.178891 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5658 19:26:35.182296 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5659 19:26:35.182461 ==
5660 19:26:35.185581 Dram Type= 6, Freq= 0, CH_1, rank 0
5661 19:26:35.189125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5662 19:26:35.192373 ==
5663 19:26:35.192519 DQS Delay:
5664 19:26:35.192619 DQS0 = 0, DQS1 = 0
5665 19:26:35.195854 DQM Delay:
5666 19:26:35.195983 DQM0 = 96, DQM1 = 88
5667 19:26:35.199348 DQ Delay:
5668 19:26:35.199484 DQ0 =95, DQ1 =95, DQ2 =87, DQ3 =95
5669 19:26:35.202469 DQ4 =95, DQ5 =103, DQ6 =107, DQ7 =91
5670 19:26:35.205683 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =83
5671 19:26:35.209007 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5672 19:26:35.212830
5673 19:26:35.212987
5674 19:26:35.213087 ==
5675 19:26:35.215669 Dram Type= 6, Freq= 0, CH_1, rank 0
5676 19:26:35.219456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5677 19:26:35.219599 ==
5678 19:26:35.219701
5679 19:26:35.219788
5680 19:26:35.222383 TX Vref Scan disable
5681 19:26:35.222508 == TX Byte 0 ==
5682 19:26:35.229082 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5683 19:26:35.232444 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5684 19:26:35.232617 == TX Byte 1 ==
5685 19:26:35.239380 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5686 19:26:35.242367 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5687 19:26:35.242520 ==
5688 19:26:35.246063 Dram Type= 6, Freq= 0, CH_1, rank 0
5689 19:26:35.248995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5690 19:26:35.249150 ==
5691 19:26:35.249265
5692 19:26:35.249368
5693 19:26:35.252134 TX Vref Scan disable
5694 19:26:35.255748 == TX Byte 0 ==
5695 19:26:35.258769 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5696 19:26:35.262546 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5697 19:26:35.265583 == TX Byte 1 ==
5698 19:26:35.269030 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5699 19:26:35.272279 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5700 19:26:35.272413
5701 19:26:35.275721 [DATLAT]
5702 19:26:35.275910 Freq=933, CH1 RK0
5703 19:26:35.275983
5704 19:26:35.278888 DATLAT Default: 0xd
5705 19:26:35.279030 0, 0xFFFF, sum = 0
5706 19:26:35.282584 1, 0xFFFF, sum = 0
5707 19:26:35.282703 2, 0xFFFF, sum = 0
5708 19:26:35.285736 3, 0xFFFF, sum = 0
5709 19:26:35.285839 4, 0xFFFF, sum = 0
5710 19:26:35.288810 5, 0xFFFF, sum = 0
5711 19:26:35.288958 6, 0xFFFF, sum = 0
5712 19:26:35.292141 7, 0xFFFF, sum = 0
5713 19:26:35.292294 8, 0xFFFF, sum = 0
5714 19:26:35.295814 9, 0xFFFF, sum = 0
5715 19:26:35.295961 10, 0x0, sum = 1
5716 19:26:35.299136 11, 0x0, sum = 2
5717 19:26:35.299244 12, 0x0, sum = 3
5718 19:26:35.302380 13, 0x0, sum = 4
5719 19:26:35.302500 best_step = 11
5720 19:26:35.302570
5721 19:26:35.302631 ==
5722 19:26:35.305610 Dram Type= 6, Freq= 0, CH_1, rank 0
5723 19:26:35.308918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5724 19:26:35.312213 ==
5725 19:26:35.312340 RX Vref Scan: 1
5726 19:26:35.312411
5727 19:26:35.315695 RX Vref 0 -> 0, step: 1
5728 19:26:35.315877
5729 19:26:35.319215 RX Delay -69 -> 252, step: 4
5730 19:26:35.319393
5731 19:26:35.322100 Set Vref, RX VrefLevel [Byte0]: 59
5732 19:26:35.322240 [Byte1]: 53
5733 19:26:35.327640
5734 19:26:35.327825 Final RX Vref Byte 0 = 59 to rank0
5735 19:26:35.330557 Final RX Vref Byte 1 = 53 to rank0
5736 19:26:35.334398 Final RX Vref Byte 0 = 59 to rank1
5737 19:26:35.337685 Final RX Vref Byte 1 = 53 to rank1==
5738 19:26:35.340871 Dram Type= 6, Freq= 0, CH_1, rank 0
5739 19:26:35.347156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5740 19:26:35.347311 ==
5741 19:26:35.347386 DQS Delay:
5742 19:26:35.347449 DQS0 = 0, DQS1 = 0
5743 19:26:35.350600 DQM Delay:
5744 19:26:35.350712 DQM0 = 98, DQM1 = 89
5745 19:26:35.354434 DQ Delay:
5746 19:26:35.357493 DQ0 =100, DQ1 =92, DQ2 =88, DQ3 =96
5747 19:26:35.360883 DQ4 =96, DQ5 =106, DQ6 =110, DQ7 =96
5748 19:26:35.363919 DQ8 =80, DQ9 =78, DQ10 =90, DQ11 =86
5749 19:26:35.367224 DQ12 =98, DQ13 =96, DQ14 =96, DQ15 =94
5750 19:26:35.367355
5751 19:26:35.367428
5752 19:26:35.374531 [DQSOSCAuto] RK0, (LSB)MR18= 0x14f0, (MSB)MR19= 0x504, tDQSOscB0 = 427 ps tDQSOscB1 = 415 ps
5753 19:26:35.377330 CH1 RK0: MR19=504, MR18=14F0
5754 19:26:35.384189 CH1_RK0: MR19=0x504, MR18=0x14F0, DQSOSC=415, MR23=63, INC=62, DEC=41
5755 19:26:35.384396
5756 19:26:35.387237 ----->DramcWriteLeveling(PI) begin...
5757 19:26:35.387416 ==
5758 19:26:35.390969 Dram Type= 6, Freq= 0, CH_1, rank 1
5759 19:26:35.394156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5760 19:26:35.394341 ==
5761 19:26:35.397097 Write leveling (Byte 0): 28 => 28
5762 19:26:35.400638 Write leveling (Byte 1): 26 => 26
5763 19:26:35.404248 DramcWriteLeveling(PI) end<-----
5764 19:26:35.404424
5765 19:26:35.404566 ==
5766 19:26:35.407431 Dram Type= 6, Freq= 0, CH_1, rank 1
5767 19:26:35.410655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5768 19:26:35.410848 ==
5769 19:26:35.413863 [Gating] SW mode calibration
5770 19:26:35.420593 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5771 19:26:35.427214 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5772 19:26:35.430544 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5773 19:26:35.437551 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5774 19:26:35.440858 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5775 19:26:35.444244 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5776 19:26:35.447226 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5777 19:26:35.453559 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5778 19:26:35.457161 0 14 24 | B1->B0 | 3232 2f2f | 0 0 | (0 0) (0 0)
5779 19:26:35.460250 0 14 28 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
5780 19:26:35.467062 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5781 19:26:35.470652 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5782 19:26:35.473704 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5783 19:26:35.480377 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5784 19:26:35.483938 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5785 19:26:35.487065 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5786 19:26:35.493794 0 15 24 | B1->B0 | 2525 3737 | 0 0 | (0 0) (1 1)
5787 19:26:35.497353 0 15 28 | B1->B0 | 3b3b 4646 | 0 0 | (1 1) (0 0)
5788 19:26:35.500360 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5789 19:26:35.507050 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5790 19:26:35.510223 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5791 19:26:35.514274 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5792 19:26:35.520734 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5793 19:26:35.523670 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5794 19:26:35.527387 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5795 19:26:35.534054 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 19:26:35.537325 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 19:26:35.540607 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 19:26:35.543784 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 19:26:35.550712 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 19:26:35.553875 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 19:26:35.557138 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 19:26:35.563927 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 19:26:35.567489 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 19:26:35.570486 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 19:26:35.577263 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 19:26:35.580339 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 19:26:35.583988 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 19:26:35.590656 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 19:26:35.593621 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 19:26:35.597353 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5811 19:26:35.603528 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5812 19:26:35.603713 Total UI for P1: 0, mck2ui 16
5813 19:26:35.610915 best dqsien dly found for B0: ( 1, 2, 24)
5814 19:26:35.614099 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5815 19:26:35.616875 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5816 19:26:35.620591 Total UI for P1: 0, mck2ui 16
5817 19:26:35.623677 best dqsien dly found for B1: ( 1, 2, 30)
5818 19:26:35.627198 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5819 19:26:35.630585 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5820 19:26:35.630761
5821 19:26:35.633569 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5822 19:26:35.640701 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5823 19:26:35.640875 [Gating] SW calibration Done
5824 19:26:35.640983 ==
5825 19:26:35.643664 Dram Type= 6, Freq= 0, CH_1, rank 1
5826 19:26:35.650449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5827 19:26:35.650587 ==
5828 19:26:35.650664 RX Vref Scan: 0
5829 19:26:35.650727
5830 19:26:35.654148 RX Vref 0 -> 0, step: 1
5831 19:26:35.654252
5832 19:26:35.657405 RX Delay -80 -> 252, step: 8
5833 19:26:35.660546 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5834 19:26:35.663881 iDelay=200, Bit 1, Center 87 (-8 ~ 183) 192
5835 19:26:35.667284 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5836 19:26:35.670530 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5837 19:26:35.677153 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5838 19:26:35.680242 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5839 19:26:35.684136 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5840 19:26:35.687792 iDelay=200, Bit 7, Center 87 (-8 ~ 183) 192
5841 19:26:35.690743 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5842 19:26:35.694366 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5843 19:26:35.700443 iDelay=200, Bit 10, Center 91 (-8 ~ 191) 200
5844 19:26:35.704099 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5845 19:26:35.707020 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5846 19:26:35.710776 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5847 19:26:35.714193 iDelay=200, Bit 14, Center 99 (0 ~ 199) 200
5848 19:26:35.717377 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5849 19:26:35.720897 ==
5850 19:26:35.721065 Dram Type= 6, Freq= 0, CH_1, rank 1
5851 19:26:35.727399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5852 19:26:35.727580 ==
5853 19:26:35.727681 DQS Delay:
5854 19:26:35.730597 DQS0 = 0, DQS1 = 0
5855 19:26:35.730738 DQM Delay:
5856 19:26:35.733968 DQM0 = 94, DQM1 = 89
5857 19:26:35.734121 DQ Delay:
5858 19:26:35.737527 DQ0 =95, DQ1 =87, DQ2 =87, DQ3 =95
5859 19:26:35.740878 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =87
5860 19:26:35.743937 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5861 19:26:35.747810 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =95
5862 19:26:35.747932
5863 19:26:35.747998
5864 19:26:35.748057 ==
5865 19:26:35.750610 Dram Type= 6, Freq= 0, CH_1, rank 1
5866 19:26:35.754509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5867 19:26:35.754645 ==
5868 19:26:35.754748
5869 19:26:35.754837
5870 19:26:35.757563 TX Vref Scan disable
5871 19:26:35.760744 == TX Byte 0 ==
5872 19:26:35.763990 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5873 19:26:35.767145 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5874 19:26:35.770451 == TX Byte 1 ==
5875 19:26:35.774245 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5876 19:26:35.777387 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5877 19:26:35.777513 ==
5878 19:26:35.780728 Dram Type= 6, Freq= 0, CH_1, rank 1
5879 19:26:35.783992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5880 19:26:35.784105 ==
5881 19:26:35.784193
5882 19:26:35.787241
5883 19:26:35.787343 TX Vref Scan disable
5884 19:26:35.790558 == TX Byte 0 ==
5885 19:26:35.793858 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5886 19:26:35.797220 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5887 19:26:35.800580 == TX Byte 1 ==
5888 19:26:35.803787 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5889 19:26:35.807381 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5890 19:26:35.811065
5891 19:26:35.811191 [DATLAT]
5892 19:26:35.811262 Freq=933, CH1 RK1
5893 19:26:35.811325
5894 19:26:35.813897 DATLAT Default: 0xb
5895 19:26:35.813989 0, 0xFFFF, sum = 0
5896 19:26:35.817199 1, 0xFFFF, sum = 0
5897 19:26:35.817316 2, 0xFFFF, sum = 0
5898 19:26:35.820505 3, 0xFFFF, sum = 0
5899 19:26:35.820614 4, 0xFFFF, sum = 0
5900 19:26:35.824442 5, 0xFFFF, sum = 0
5901 19:26:35.824550 6, 0xFFFF, sum = 0
5902 19:26:35.827855 7, 0xFFFF, sum = 0
5903 19:26:35.827966 8, 0xFFFF, sum = 0
5904 19:26:35.830933 9, 0xFFFF, sum = 0
5905 19:26:35.831035 10, 0x0, sum = 1
5906 19:26:35.834264 11, 0x0, sum = 2
5907 19:26:35.834367 12, 0x0, sum = 3
5908 19:26:35.837903 13, 0x0, sum = 4
5909 19:26:35.838009 best_step = 11
5910 19:26:35.838078
5911 19:26:35.838139 ==
5912 19:26:35.840589 Dram Type= 6, Freq= 0, CH_1, rank 1
5913 19:26:35.847326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5914 19:26:35.847466 ==
5915 19:26:35.847541 RX Vref Scan: 0
5916 19:26:35.847602
5917 19:26:35.850595 RX Vref 0 -> 0, step: 1
5918 19:26:35.850708
5919 19:26:35.854037 RX Delay -61 -> 252, step: 4
5920 19:26:35.857247 iDelay=199, Bit 0, Center 96 (3 ~ 190) 188
5921 19:26:35.860755 iDelay=199, Bit 1, Center 90 (-1 ~ 182) 184
5922 19:26:35.867396 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5923 19:26:35.870905 iDelay=199, Bit 3, Center 94 (3 ~ 186) 184
5924 19:26:35.873732 iDelay=199, Bit 4, Center 94 (3 ~ 186) 184
5925 19:26:35.877393 iDelay=199, Bit 5, Center 104 (15 ~ 194) 180
5926 19:26:35.880997 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5927 19:26:35.883911 iDelay=199, Bit 7, Center 92 (3 ~ 182) 180
5928 19:26:35.890804 iDelay=199, Bit 8, Center 80 (-13 ~ 174) 188
5929 19:26:35.893932 iDelay=199, Bit 9, Center 78 (-13 ~ 170) 184
5930 19:26:35.896940 iDelay=199, Bit 10, Center 88 (-5 ~ 182) 188
5931 19:26:35.900538 iDelay=199, Bit 11, Center 82 (-9 ~ 174) 184
5932 19:26:35.903535 iDelay=199, Bit 12, Center 96 (7 ~ 186) 180
5933 19:26:35.910479 iDelay=199, Bit 13, Center 98 (7 ~ 190) 184
5934 19:26:35.913704 iDelay=199, Bit 14, Center 100 (11 ~ 190) 180
5935 19:26:35.916796 iDelay=199, Bit 15, Center 98 (7 ~ 190) 184
5936 19:26:35.916921 ==
5937 19:26:35.920428 Dram Type= 6, Freq= 0, CH_1, rank 1
5938 19:26:35.924000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5939 19:26:35.924122 ==
5940 19:26:35.926755 DQS Delay:
5941 19:26:35.926899 DQS0 = 0, DQS1 = 0
5942 19:26:35.930144 DQM Delay:
5943 19:26:35.930319 DQM0 = 95, DQM1 = 90
5944 19:26:35.930422 DQ Delay:
5945 19:26:35.933399 DQ0 =96, DQ1 =90, DQ2 =86, DQ3 =94
5946 19:26:35.936996 DQ4 =94, DQ5 =104, DQ6 =106, DQ7 =92
5947 19:26:35.939980 DQ8 =80, DQ9 =78, DQ10 =88, DQ11 =82
5948 19:26:35.943889 DQ12 =96, DQ13 =98, DQ14 =100, DQ15 =98
5949 19:26:35.944026
5950 19:26:35.944096
5951 19:26:35.953440 [DQSOSCAuto] RK1, (LSB)MR18= 0x111a, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 416 ps
5952 19:26:35.956442 CH1 RK1: MR19=505, MR18=111A
5953 19:26:35.963219 CH1_RK1: MR19=0x505, MR18=0x111A, DQSOSC=413, MR23=63, INC=63, DEC=42
5954 19:26:35.963401 [RxdqsGatingPostProcess] freq 933
5955 19:26:35.969915 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5956 19:26:35.973342 best DQS0 dly(2T, 0.5T) = (0, 10)
5957 19:26:35.976387 best DQS1 dly(2T, 0.5T) = (0, 10)
5958 19:26:35.980083 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5959 19:26:35.983184 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5960 19:26:35.986701 best DQS0 dly(2T, 0.5T) = (0, 10)
5961 19:26:35.989749 best DQS1 dly(2T, 0.5T) = (0, 10)
5962 19:26:35.993101 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5963 19:26:35.997004 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5964 19:26:36.000130 Pre-setting of DQS Precalculation
5965 19:26:36.003230 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5966 19:26:36.009830 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5967 19:26:36.016839 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5968 19:26:36.017021
5969 19:26:36.019791
5970 19:26:36.019922 [Calibration Summary] 1866 Mbps
5971 19:26:36.023467 CH 0, Rank 0
5972 19:26:36.023613 SW Impedance : PASS
5973 19:26:36.026964 DUTY Scan : NO K
5974 19:26:36.030318 ZQ Calibration : PASS
5975 19:26:36.030470 Jitter Meter : NO K
5976 19:26:36.033819 CBT Training : PASS
5977 19:26:36.036780 Write leveling : PASS
5978 19:26:36.036927 RX DQS gating : PASS
5979 19:26:36.040135 RX DQ/DQS(RDDQC) : PASS
5980 19:26:36.043337 TX DQ/DQS : PASS
5981 19:26:36.043471 RX DATLAT : PASS
5982 19:26:36.046951 RX DQ/DQS(Engine): PASS
5983 19:26:36.047164 TX OE : NO K
5984 19:26:36.050027 All Pass.
5985 19:26:36.050237
5986 19:26:36.050363 CH 0, Rank 1
5987 19:26:36.053423 SW Impedance : PASS
5988 19:26:36.053595 DUTY Scan : NO K
5989 19:26:36.056669 ZQ Calibration : PASS
5990 19:26:36.059755 Jitter Meter : NO K
5991 19:26:36.059909 CBT Training : PASS
5992 19:26:36.063566 Write leveling : PASS
5993 19:26:36.066440 RX DQS gating : PASS
5994 19:26:36.066563 RX DQ/DQS(RDDQC) : PASS
5995 19:26:36.070066 TX DQ/DQS : PASS
5996 19:26:36.073730 RX DATLAT : PASS
5997 19:26:36.073884 RX DQ/DQS(Engine): PASS
5998 19:26:36.076575 TX OE : NO K
5999 19:26:36.076687 All Pass.
6000 19:26:36.076756
6001 19:26:36.080338 CH 1, Rank 0
6002 19:26:36.080493 SW Impedance : PASS
6003 19:26:36.083188 DUTY Scan : NO K
6004 19:26:36.086809 ZQ Calibration : PASS
6005 19:26:36.086935 Jitter Meter : NO K
6006 19:26:36.089998 CBT Training : PASS
6007 19:26:36.093241 Write leveling : PASS
6008 19:26:36.093359 RX DQS gating : PASS
6009 19:26:36.096733 RX DQ/DQS(RDDQC) : PASS
6010 19:26:36.096855 TX DQ/DQS : PASS
6011 19:26:36.099826 RX DATLAT : PASS
6012 19:26:36.103518 RX DQ/DQS(Engine): PASS
6013 19:26:36.103682 TX OE : NO K
6014 19:26:36.106718 All Pass.
6015 19:26:36.106857
6016 19:26:36.106965 CH 1, Rank 1
6017 19:26:36.110116 SW Impedance : PASS
6018 19:26:36.110254 DUTY Scan : NO K
6019 19:26:36.113751 ZQ Calibration : PASS
6020 19:26:36.116723 Jitter Meter : NO K
6021 19:26:36.116861 CBT Training : PASS
6022 19:26:36.120217 Write leveling : PASS
6023 19:26:36.123202 RX DQS gating : PASS
6024 19:26:36.123361 RX DQ/DQS(RDDQC) : PASS
6025 19:26:36.126852 TX DQ/DQS : PASS
6026 19:26:36.130085 RX DATLAT : PASS
6027 19:26:36.130241 RX DQ/DQS(Engine): PASS
6028 19:26:36.133601 TX OE : NO K
6029 19:26:36.133729 All Pass.
6030 19:26:36.133802
6031 19:26:36.136571 DramC Write-DBI off
6032 19:26:36.140021 PER_BANK_REFRESH: Hybrid Mode
6033 19:26:36.140180 TX_TRACKING: ON
6034 19:26:36.150166 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6035 19:26:36.153681 [FAST_K] Save calibration result to emmc
6036 19:26:36.157120 dramc_set_vcore_voltage set vcore to 650000
6037 19:26:36.157292 Read voltage for 400, 6
6038 19:26:36.160519 Vio18 = 0
6039 19:26:36.160682 Vcore = 650000
6040 19:26:36.160822 Vdram = 0
6041 19:26:36.163336 Vddq = 0
6042 19:26:36.163449 Vmddr = 0
6043 19:26:36.166850 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6044 19:26:36.173968 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6045 19:26:36.176939 MEM_TYPE=3, freq_sel=20
6046 19:26:36.180026 sv_algorithm_assistance_LP4_800
6047 19:26:36.183803 ============ PULL DRAM RESETB DOWN ============
6048 19:26:36.186922 ========== PULL DRAM RESETB DOWN end =========
6049 19:26:36.193863 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6050 19:26:36.194101 ===================================
6051 19:26:36.196870 LPDDR4 DRAM CONFIGURATION
6052 19:26:36.200543 ===================================
6053 19:26:36.203676 EX_ROW_EN[0] = 0x0
6054 19:26:36.203808 EX_ROW_EN[1] = 0x0
6055 19:26:36.207231 LP4Y_EN = 0x0
6056 19:26:36.207354 WORK_FSP = 0x0
6057 19:26:36.210306 WL = 0x2
6058 19:26:36.210427 RL = 0x2
6059 19:26:36.213877 BL = 0x2
6060 19:26:36.213993 RPST = 0x0
6061 19:26:36.217467 RD_PRE = 0x0
6062 19:26:36.217616 WR_PRE = 0x1
6063 19:26:36.220447 WR_PST = 0x0
6064 19:26:36.220562 DBI_WR = 0x0
6065 19:26:36.223952 DBI_RD = 0x0
6066 19:26:36.227757 OTF = 0x1
6067 19:26:36.227890 ===================================
6068 19:26:36.230559 ===================================
6069 19:26:36.234255 ANA top config
6070 19:26:36.237334 ===================================
6071 19:26:36.240589 DLL_ASYNC_EN = 0
6072 19:26:36.240708 ALL_SLAVE_EN = 1
6073 19:26:36.244054 NEW_RANK_MODE = 1
6074 19:26:36.247220 DLL_IDLE_MODE = 1
6075 19:26:36.250534 LP45_APHY_COMB_EN = 1
6076 19:26:36.250659 TX_ODT_DIS = 1
6077 19:26:36.254170 NEW_8X_MODE = 1
6078 19:26:36.257344 ===================================
6079 19:26:36.260690 ===================================
6080 19:26:36.263840 data_rate = 800
6081 19:26:36.267437 CKR = 1
6082 19:26:36.270509 DQ_P2S_RATIO = 4
6083 19:26:36.273784 ===================================
6084 19:26:36.277251 CA_P2S_RATIO = 4
6085 19:26:36.277391 DQ_CA_OPEN = 0
6086 19:26:36.280531 DQ_SEMI_OPEN = 1
6087 19:26:36.284091 CA_SEMI_OPEN = 1
6088 19:26:36.287394 CA_FULL_RATE = 0
6089 19:26:36.290505 DQ_CKDIV4_EN = 0
6090 19:26:36.294134 CA_CKDIV4_EN = 1
6091 19:26:36.294288 CA_PREDIV_EN = 0
6092 19:26:36.297295 PH8_DLY = 0
6093 19:26:36.300788 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6094 19:26:36.303922 DQ_AAMCK_DIV = 0
6095 19:26:36.307435 CA_AAMCK_DIV = 0
6096 19:26:36.310633 CA_ADMCK_DIV = 4
6097 19:26:36.310764 DQ_TRACK_CA_EN = 0
6098 19:26:36.314331 CA_PICK = 800
6099 19:26:36.317345 CA_MCKIO = 400
6100 19:26:36.320500 MCKIO_SEMI = 400
6101 19:26:36.323825 PLL_FREQ = 3016
6102 19:26:36.327033 DQ_UI_PI_RATIO = 32
6103 19:26:36.330388 CA_UI_PI_RATIO = 32
6104 19:26:36.333889 ===================================
6105 19:26:36.337607 ===================================
6106 19:26:36.337757 memory_type:LPDDR4
6107 19:26:36.340673 GP_NUM : 10
6108 19:26:36.344300 SRAM_EN : 1
6109 19:26:36.344427 MD32_EN : 0
6110 19:26:36.347281 ===================================
6111 19:26:36.350362 [ANA_INIT] >>>>>>>>>>>>>>
6112 19:26:36.353910 <<<<<< [CONFIGURE PHASE]: ANA_TX
6113 19:26:36.357060 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6114 19:26:36.360671 ===================================
6115 19:26:36.364376 data_rate = 800,PCW = 0X7400
6116 19:26:36.364507 ===================================
6117 19:26:36.370693 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6118 19:26:36.373919 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6119 19:26:36.387269 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6120 19:26:36.390442 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6121 19:26:36.393706 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6122 19:26:36.397584 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6123 19:26:36.400608 [ANA_INIT] flow start
6124 19:26:36.400736 [ANA_INIT] PLL >>>>>>>>
6125 19:26:36.403793 [ANA_INIT] PLL <<<<<<<<
6126 19:26:36.407644 [ANA_INIT] MIDPI >>>>>>>>
6127 19:26:36.407813 [ANA_INIT] MIDPI <<<<<<<<
6128 19:26:36.410430 [ANA_INIT] DLL >>>>>>>>
6129 19:26:36.414235 [ANA_INIT] flow end
6130 19:26:36.417347 ============ LP4 DIFF to SE enter ============
6131 19:26:36.421098 ============ LP4 DIFF to SE exit ============
6132 19:26:36.424049 [ANA_INIT] <<<<<<<<<<<<<
6133 19:26:36.427668 [Flow] Enable top DCM control >>>>>
6134 19:26:36.430513 [Flow] Enable top DCM control <<<<<
6135 19:26:36.434022 Enable DLL master slave shuffle
6136 19:26:36.437553 ==============================================================
6137 19:26:36.440504 Gating Mode config
6138 19:26:36.447664 ==============================================================
6139 19:26:36.447837 Config description:
6140 19:26:36.457195 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6141 19:26:36.463987 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6142 19:26:36.467107 SELPH_MODE 0: By rank 1: By Phase
6143 19:26:36.474214 ==============================================================
6144 19:26:36.477148 GAT_TRACK_EN = 0
6145 19:26:36.480829 RX_GATING_MODE = 2
6146 19:26:36.484087 RX_GATING_TRACK_MODE = 2
6147 19:26:36.487688 SELPH_MODE = 1
6148 19:26:36.490728 PICG_EARLY_EN = 1
6149 19:26:36.493887 VALID_LAT_VALUE = 1
6150 19:26:36.497412 ==============================================================
6151 19:26:36.500692 Enter into Gating configuration >>>>
6152 19:26:36.504542 Exit from Gating configuration <<<<
6153 19:26:36.507427 Enter into DVFS_PRE_config >>>>>
6154 19:26:36.517274 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6155 19:26:36.520678 Exit from DVFS_PRE_config <<<<<
6156 19:26:36.524163 Enter into PICG configuration >>>>
6157 19:26:36.527261 Exit from PICG configuration <<<<
6158 19:26:36.531026 [RX_INPUT] configuration >>>>>
6159 19:26:36.534094 [RX_INPUT] configuration <<<<<
6160 19:26:36.537681 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6161 19:26:36.544281 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6162 19:26:36.551024 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6163 19:26:36.558182 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6164 19:26:36.564214 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6165 19:26:36.567290 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6166 19:26:36.574108 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6167 19:26:36.577378 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6168 19:26:36.580919 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6169 19:26:36.583950 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6170 19:26:36.590744 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6171 19:26:36.594088 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6172 19:26:36.597526 ===================================
6173 19:26:36.600694 LPDDR4 DRAM CONFIGURATION
6174 19:26:36.604233 ===================================
6175 19:26:36.604369 EX_ROW_EN[0] = 0x0
6176 19:26:36.607518 EX_ROW_EN[1] = 0x0
6177 19:26:36.607636 LP4Y_EN = 0x0
6178 19:26:36.611106 WORK_FSP = 0x0
6179 19:26:36.611223 WL = 0x2
6180 19:26:36.614175 RL = 0x2
6181 19:26:36.614318 BL = 0x2
6182 19:26:36.617644 RPST = 0x0
6183 19:26:36.617759 RD_PRE = 0x0
6184 19:26:36.620546 WR_PRE = 0x1
6185 19:26:36.620636 WR_PST = 0x0
6186 19:26:36.624271 DBI_WR = 0x0
6187 19:26:36.627339 DBI_RD = 0x0
6188 19:26:36.627484 OTF = 0x1
6189 19:26:36.630718 ===================================
6190 19:26:36.633787 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6191 19:26:36.637520 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6192 19:26:36.643934 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6193 19:26:36.647373 ===================================
6194 19:26:36.650799 LPDDR4 DRAM CONFIGURATION
6195 19:26:36.654198 ===================================
6196 19:26:36.654359 EX_ROW_EN[0] = 0x10
6197 19:26:36.657416 EX_ROW_EN[1] = 0x0
6198 19:26:36.657516 LP4Y_EN = 0x0
6199 19:26:36.660477 WORK_FSP = 0x0
6200 19:26:36.660594 WL = 0x2
6201 19:26:36.663671 RL = 0x2
6202 19:26:36.663793 BL = 0x2
6203 19:26:36.667063 RPST = 0x0
6204 19:26:36.667186 RD_PRE = 0x0
6205 19:26:36.670554 WR_PRE = 0x1
6206 19:26:36.670665 WR_PST = 0x0
6207 19:26:36.673594 DBI_WR = 0x0
6208 19:26:36.673718 DBI_RD = 0x0
6209 19:26:36.677174 OTF = 0x1
6210 19:26:36.680460 ===================================
6211 19:26:36.686942 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6212 19:26:36.690722 nWR fixed to 30
6213 19:26:36.693642 [ModeRegInit_LP4] CH0 RK0
6214 19:26:36.693766 [ModeRegInit_LP4] CH0 RK1
6215 19:26:36.697367 [ModeRegInit_LP4] CH1 RK0
6216 19:26:36.700260 [ModeRegInit_LP4] CH1 RK1
6217 19:26:36.700377 match AC timing 19
6218 19:26:36.707029 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6219 19:26:36.710128 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6220 19:26:36.714001 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6221 19:26:36.720533 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6222 19:26:36.723731 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6223 19:26:36.723878 ==
6224 19:26:36.727425 Dram Type= 6, Freq= 0, CH_0, rank 0
6225 19:26:36.730465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6226 19:26:36.730593 ==
6227 19:26:36.736970 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6228 19:26:36.743877 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6229 19:26:36.747432 [CA 0] Center 36 (8~64) winsize 57
6230 19:26:36.747583 [CA 1] Center 36 (8~64) winsize 57
6231 19:26:36.750342 [CA 2] Center 36 (8~64) winsize 57
6232 19:26:36.753770 [CA 3] Center 36 (8~64) winsize 57
6233 19:26:36.757649 [CA 4] Center 36 (8~64) winsize 57
6234 19:26:36.760663 [CA 5] Center 36 (8~64) winsize 57
6235 19:26:36.760817
6236 19:26:36.763706 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6237 19:26:36.763836
6238 19:26:36.767639 [CATrainingPosCal] consider 1 rank data
6239 19:26:36.770715 u2DelayCellTimex100 = 270/100 ps
6240 19:26:36.774116 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6241 19:26:36.780803 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 19:26:36.783860 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 19:26:36.787230 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 19:26:36.790426 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 19:26:36.793640 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 19:26:36.793772
6247 19:26:36.797385 CA PerBit enable=1, Macro0, CA PI delay=36
6248 19:26:36.797564
6249 19:26:36.800505 [CBTSetCACLKResult] CA Dly = 36
6250 19:26:36.800679 CS Dly: 1 (0~32)
6251 19:26:36.804024 ==
6252 19:26:36.807138 Dram Type= 6, Freq= 0, CH_0, rank 1
6253 19:26:36.810340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6254 19:26:36.810544 ==
6255 19:26:36.813468 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6256 19:26:36.820251 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6257 19:26:36.823709 [CA 0] Center 36 (8~64) winsize 57
6258 19:26:36.827108 [CA 1] Center 36 (8~64) winsize 57
6259 19:26:36.830454 [CA 2] Center 36 (8~64) winsize 57
6260 19:26:36.833562 [CA 3] Center 36 (8~64) winsize 57
6261 19:26:36.837100 [CA 4] Center 36 (8~64) winsize 57
6262 19:26:36.840625 [CA 5] Center 36 (8~64) winsize 57
6263 19:26:36.840798
6264 19:26:36.843835 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6265 19:26:36.843973
6266 19:26:36.846770 [CATrainingPosCal] consider 2 rank data
6267 19:26:36.850764 u2DelayCellTimex100 = 270/100 ps
6268 19:26:36.853689 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6269 19:26:36.857543 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6270 19:26:36.860575 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6271 19:26:36.864168 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6272 19:26:36.866949 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6273 19:26:36.873611 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6274 19:26:36.873821
6275 19:26:36.877183 CA PerBit enable=1, Macro0, CA PI delay=36
6276 19:26:36.877365
6277 19:26:36.880616 [CBTSetCACLKResult] CA Dly = 36
6278 19:26:36.880735 CS Dly: 1 (0~32)
6279 19:26:36.880805
6280 19:26:36.883598 ----->DramcWriteLeveling(PI) begin...
6281 19:26:36.883752 ==
6282 19:26:36.887394 Dram Type= 6, Freq= 0, CH_0, rank 0
6283 19:26:36.890973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6284 19:26:36.894014 ==
6285 19:26:36.894138 Write leveling (Byte 0): 40 => 8
6286 19:26:36.897093 Write leveling (Byte 1): 32 => 0
6287 19:26:36.900580 DramcWriteLeveling(PI) end<-----
6288 19:26:36.900714
6289 19:26:36.900819 ==
6290 19:26:36.903830 Dram Type= 6, Freq= 0, CH_0, rank 0
6291 19:26:36.910537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6292 19:26:36.910676 ==
6293 19:26:36.910754 [Gating] SW mode calibration
6294 19:26:36.921313 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6295 19:26:36.924240 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6296 19:26:36.927114 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6297 19:26:36.934072 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6298 19:26:36.937085 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6299 19:26:36.940494 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6300 19:26:36.947447 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6301 19:26:36.950547 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6302 19:26:36.954029 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6303 19:26:36.961011 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6304 19:26:36.964082 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6305 19:26:36.967001 Total UI for P1: 0, mck2ui 16
6306 19:26:36.970452 best dqsien dly found for B0: ( 0, 14, 24)
6307 19:26:36.973975 Total UI for P1: 0, mck2ui 16
6308 19:26:36.977052 best dqsien dly found for B1: ( 0, 14, 24)
6309 19:26:36.980668 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6310 19:26:36.984205 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6311 19:26:36.984332
6312 19:26:36.987223 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6313 19:26:36.990946 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6314 19:26:36.993910 [Gating] SW calibration Done
6315 19:26:36.994030 ==
6316 19:26:36.997557 Dram Type= 6, Freq= 0, CH_0, rank 0
6317 19:26:37.000677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6318 19:26:37.003641 ==
6319 19:26:37.003772 RX Vref Scan: 0
6320 19:26:37.003866
6321 19:26:37.007423 RX Vref 0 -> 0, step: 1
6322 19:26:37.007551
6323 19:26:37.010615 RX Delay -410 -> 252, step: 16
6324 19:26:37.014026 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6325 19:26:37.016916 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6326 19:26:37.020738 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6327 19:26:37.027425 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6328 19:26:37.030392 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6329 19:26:37.033922 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6330 19:26:37.037598 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6331 19:26:37.044241 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6332 19:26:37.047115 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6333 19:26:37.050976 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6334 19:26:37.053985 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6335 19:26:37.060525 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6336 19:26:37.063887 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6337 19:26:37.067037 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6338 19:26:37.070687 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6339 19:26:37.077439 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6340 19:26:37.077634 ==
6341 19:26:37.080602 Dram Type= 6, Freq= 0, CH_0, rank 0
6342 19:26:37.083939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6343 19:26:37.084101 ==
6344 19:26:37.084208 DQS Delay:
6345 19:26:37.086966 DQS0 = 35, DQS1 = 51
6346 19:26:37.087098 DQM Delay:
6347 19:26:37.090864 DQM0 = 6, DQM1 = 10
6348 19:26:37.091011 DQ Delay:
6349 19:26:37.094340 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6350 19:26:37.097099 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6351 19:26:37.100227 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6352 19:26:37.104165 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6353 19:26:37.104355
6354 19:26:37.104472
6355 19:26:37.104581 ==
6356 19:26:37.106862 Dram Type= 6, Freq= 0, CH_0, rank 0
6357 19:26:37.110577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6358 19:26:37.110733 ==
6359 19:26:37.110842
6360 19:26:37.110932
6361 19:26:37.113741 TX Vref Scan disable
6362 19:26:37.113884 == TX Byte 0 ==
6363 19:26:37.120371 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6364 19:26:37.123642 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6365 19:26:37.123803 == TX Byte 1 ==
6366 19:26:37.130399 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6367 19:26:37.133787 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6368 19:26:37.133951 ==
6369 19:26:37.136846 Dram Type= 6, Freq= 0, CH_0, rank 0
6370 19:26:37.140438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6371 19:26:37.140593 ==
6372 19:26:37.140695
6373 19:26:37.140798
6374 19:26:37.143628 TX Vref Scan disable
6375 19:26:37.143761 == TX Byte 0 ==
6376 19:26:37.150756 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6377 19:26:37.153634 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6378 19:26:37.153773 == TX Byte 1 ==
6379 19:26:37.160362 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6380 19:26:37.163611 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6381 19:26:37.163727
6382 19:26:37.163799 [DATLAT]
6383 19:26:37.167129 Freq=400, CH0 RK0
6384 19:26:37.167258
6385 19:26:37.167355 DATLAT Default: 0xf
6386 19:26:37.170208 0, 0xFFFF, sum = 0
6387 19:26:37.170332 1, 0xFFFF, sum = 0
6388 19:26:37.173800 2, 0xFFFF, sum = 0
6389 19:26:37.173926 3, 0xFFFF, sum = 0
6390 19:26:37.176750 4, 0xFFFF, sum = 0
6391 19:26:37.180475 5, 0xFFFF, sum = 0
6392 19:26:37.180630 6, 0xFFFF, sum = 0
6393 19:26:37.183754 7, 0xFFFF, sum = 0
6394 19:26:37.183905 8, 0xFFFF, sum = 0
6395 19:26:37.186916 9, 0xFFFF, sum = 0
6396 19:26:37.187061 10, 0xFFFF, sum = 0
6397 19:26:37.190516 11, 0xFFFF, sum = 0
6398 19:26:37.190668 12, 0xFFFF, sum = 0
6399 19:26:37.193670 13, 0x0, sum = 1
6400 19:26:37.193812 14, 0x0, sum = 2
6401 19:26:37.197306 15, 0x0, sum = 3
6402 19:26:37.197440 16, 0x0, sum = 4
6403 19:26:37.197513 best_step = 14
6404 19:26:37.200738
6405 19:26:37.200870 ==
6406 19:26:37.203773 Dram Type= 6, Freq= 0, CH_0, rank 0
6407 19:26:37.207331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6408 19:26:37.207484 ==
6409 19:26:37.207584 RX Vref Scan: 1
6410 19:26:37.207672
6411 19:26:37.210424 RX Vref 0 -> 0, step: 1
6412 19:26:37.210528
6413 19:26:37.214016 RX Delay -343 -> 252, step: 8
6414 19:26:37.214167
6415 19:26:37.217413 Set Vref, RX VrefLevel [Byte0]: 52
6416 19:26:37.220513 [Byte1]: 52
6417 19:26:37.224037
6418 19:26:37.224193 Final RX Vref Byte 0 = 52 to rank0
6419 19:26:37.227532 Final RX Vref Byte 1 = 52 to rank0
6420 19:26:37.230806 Final RX Vref Byte 0 = 52 to rank1
6421 19:26:37.233875 Final RX Vref Byte 1 = 52 to rank1==
6422 19:26:37.237359 Dram Type= 6, Freq= 0, CH_0, rank 0
6423 19:26:37.243913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6424 19:26:37.244090 ==
6425 19:26:37.244201 DQS Delay:
6426 19:26:37.247451 DQS0 = 44, DQS1 = 60
6427 19:26:37.247579 DQM Delay:
6428 19:26:37.247679 DQM0 = 12, DQM1 = 15
6429 19:26:37.250386 DQ Delay:
6430 19:26:37.253820 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =12
6431 19:26:37.257383 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6432 19:26:37.257540 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =12
6433 19:26:37.260768 DQ12 =24, DQ13 =20, DQ14 =24, DQ15 =28
6434 19:26:37.264214
6435 19:26:37.264339
6436 19:26:37.270746 [DQSOSCAuto] RK0, (LSB)MR18= 0x8d5a, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 392 ps
6437 19:26:37.273824 CH0 RK0: MR19=C0C, MR18=8D5A
6438 19:26:37.281056 CH0_RK0: MR19=0xC0C, MR18=0x8D5A, DQSOSC=392, MR23=63, INC=384, DEC=256
6439 19:26:37.281242 ==
6440 19:26:37.283964 Dram Type= 6, Freq= 0, CH_0, rank 1
6441 19:26:37.287498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6442 19:26:37.287667 ==
6443 19:26:37.290656 [Gating] SW mode calibration
6444 19:26:37.297347 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6445 19:26:37.304058 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6446 19:26:37.307645 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6447 19:26:37.310534 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6448 19:26:37.314299 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6449 19:26:37.320951 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6450 19:26:37.324166 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6451 19:26:37.327435 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6452 19:26:37.334288 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6453 19:26:37.337485 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6454 19:26:37.340975 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6455 19:26:37.343887 Total UI for P1: 0, mck2ui 16
6456 19:26:37.347536 best dqsien dly found for B0: ( 0, 14, 24)
6457 19:26:37.350786 Total UI for P1: 0, mck2ui 16
6458 19:26:37.354337 best dqsien dly found for B1: ( 0, 14, 24)
6459 19:26:37.357333 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6460 19:26:37.360791 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6461 19:26:37.360946
6462 19:26:37.367369 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6463 19:26:37.370687 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6464 19:26:37.374280 [Gating] SW calibration Done
6465 19:26:37.374442 ==
6466 19:26:37.377241 Dram Type= 6, Freq= 0, CH_0, rank 1
6467 19:26:37.380645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6468 19:26:37.380800 ==
6469 19:26:37.380901 RX Vref Scan: 0
6470 19:26:37.380993
6471 19:26:37.384154 RX Vref 0 -> 0, step: 1
6472 19:26:37.384286
6473 19:26:37.387414 RX Delay -410 -> 252, step: 16
6474 19:26:37.390889 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6475 19:26:37.397734 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6476 19:26:37.400713 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6477 19:26:37.403723 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6478 19:26:37.407457 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6479 19:26:37.410813 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6480 19:26:37.417437 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6481 19:26:37.421178 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6482 19:26:37.424257 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6483 19:26:37.427225 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6484 19:26:37.434191 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6485 19:26:37.437741 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6486 19:26:37.440568 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6487 19:26:37.447355 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6488 19:26:37.451047 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6489 19:26:37.454408 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6490 19:26:37.454523 ==
6491 19:26:37.457574 Dram Type= 6, Freq= 0, CH_0, rank 1
6492 19:26:37.460817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6493 19:26:37.460969 ==
6494 19:26:37.463953 DQS Delay:
6495 19:26:37.464117 DQS0 = 43, DQS1 = 51
6496 19:26:37.467378 DQM Delay:
6497 19:26:37.467492 DQM0 = 11, DQM1 = 10
6498 19:26:37.467566 DQ Delay:
6499 19:26:37.470766 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6500 19:26:37.474141 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6501 19:26:37.477109 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6502 19:26:37.480513 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6503 19:26:37.480684
6504 19:26:37.480802
6505 19:26:37.480892 ==
6506 19:26:37.484151 Dram Type= 6, Freq= 0, CH_0, rank 1
6507 19:26:37.490646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6508 19:26:37.490813 ==
6509 19:26:37.490913
6510 19:26:37.491002
6511 19:26:37.491088 TX Vref Scan disable
6512 19:26:37.494071 == TX Byte 0 ==
6513 19:26:37.497551 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6514 19:26:37.500833 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6515 19:26:37.503763 == TX Byte 1 ==
6516 19:26:37.507274 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6517 19:26:37.510518 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6518 19:26:37.510674 ==
6519 19:26:37.513977 Dram Type= 6, Freq= 0, CH_0, rank 1
6520 19:26:37.520954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6521 19:26:37.521157 ==
6522 19:26:37.521289
6523 19:26:37.521410
6524 19:26:37.521500 TX Vref Scan disable
6525 19:26:37.524221 == TX Byte 0 ==
6526 19:26:37.527520 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6527 19:26:37.530494 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6528 19:26:37.534251 == TX Byte 1 ==
6529 19:26:37.537797 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6530 19:26:37.540862 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6531 19:26:37.541049
6532 19:26:37.544007 [DATLAT]
6533 19:26:37.544158 Freq=400, CH0 RK1
6534 19:26:37.544262
6535 19:26:37.547594 DATLAT Default: 0xe
6536 19:26:37.547734 0, 0xFFFF, sum = 0
6537 19:26:37.550599 1, 0xFFFF, sum = 0
6538 19:26:37.550747 2, 0xFFFF, sum = 0
6539 19:26:37.554029 3, 0xFFFF, sum = 0
6540 19:26:37.554163 4, 0xFFFF, sum = 0
6541 19:26:37.557541 5, 0xFFFF, sum = 0
6542 19:26:37.557710 6, 0xFFFF, sum = 0
6543 19:26:37.560961 7, 0xFFFF, sum = 0
6544 19:26:37.561117 8, 0xFFFF, sum = 0
6545 19:26:37.563876 9, 0xFFFF, sum = 0
6546 19:26:37.564016 10, 0xFFFF, sum = 0
6547 19:26:37.567511 11, 0xFFFF, sum = 0
6548 19:26:37.567659 12, 0xFFFF, sum = 0
6549 19:26:37.570716 13, 0x0, sum = 1
6550 19:26:37.570834 14, 0x0, sum = 2
6551 19:26:37.574223 15, 0x0, sum = 3
6552 19:26:37.574354 16, 0x0, sum = 4
6553 19:26:37.577578 best_step = 14
6554 19:26:37.577711
6555 19:26:37.577785 ==
6556 19:26:37.581032 Dram Type= 6, Freq= 0, CH_0, rank 1
6557 19:26:37.583991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6558 19:26:37.584114 ==
6559 19:26:37.876954 RX Vref Scan: 0
6560 19:26:37.877119
6561 19:26:37.877232 RX Vref 0 -> 0, step: 1
6562 19:26:37.877334
6563 19:26:37.877639 RX Delay -343 -> 252, step: 8
6564 19:26:37.877732 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6565 19:26:37.877794 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6566 19:26:37.877852 iDelay=217, Bit 2, Center -36 (-271 ~ 200) 472
6567 19:26:37.877909 iDelay=217, Bit 3, Center -32 (-271 ~ 208) 480
6568 19:26:37.877964 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6569 19:26:37.878019 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6570 19:26:37.878072 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6571 19:26:37.878126 iDelay=217, Bit 7, Center -28 (-263 ~ 208) 472
6572 19:26:37.878181 iDelay=217, Bit 8, Center -56 (-295 ~ 184) 480
6573 19:26:37.878234 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6574 19:26:37.878288 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6575 19:26:37.878341 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6576 19:26:37.878393 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6577 19:26:37.878446 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6578 19:26:37.878499 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6579 19:26:37.878552 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6580 19:26:37.878604 ==
6581 19:26:37.878658 Dram Type= 6, Freq= 0, CH_0, rank 1
6582 19:26:37.878712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6583 19:26:37.878765 ==
6584 19:26:37.878821 DQS Delay:
6585 19:26:37.878880 DQS0 = 48, DQS1 = 56
6586 19:26:37.878963 DQM Delay:
6587 19:26:37.879044 DQM0 = 14, DQM1 = 10
6588 19:26:37.879126 DQ Delay:
6589 19:26:37.879216 DQ0 =16, DQ1 =16, DQ2 =12, DQ3 =16
6590 19:26:37.879327 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6591 19:26:37.879417 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6592 19:26:37.879500 DQ12 =12, DQ13 =16, DQ14 =20, DQ15 =20
6593 19:26:37.879582
6594 19:26:37.879665
6595 19:26:37.879722 [DQSOSCAuto] RK1, (LSB)MR18= 0x9064, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 391 ps
6596 19:26:37.879776 CH0 RK1: MR19=C0C, MR18=9064
6597 19:26:37.879860 CH0_RK1: MR19=0xC0C, MR18=0x9064, DQSOSC=391, MR23=63, INC=386, DEC=257
6598 19:26:37.879946 [RxdqsGatingPostProcess] freq 400
6599 19:26:37.880039 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6600 19:26:37.880134 best DQS0 dly(2T, 0.5T) = (0, 10)
6601 19:26:37.880218 best DQS1 dly(2T, 0.5T) = (0, 10)
6602 19:26:37.880300 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6603 19:26:37.880382 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6604 19:26:37.880479 best DQS0 dly(2T, 0.5T) = (0, 10)
6605 19:26:37.880588 best DQS1 dly(2T, 0.5T) = (0, 10)
6606 19:26:37.880671 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6607 19:26:37.880753 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6608 19:26:37.880835 Pre-setting of DQS Precalculation
6609 19:26:37.880917 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6610 19:26:37.880999 ==
6611 19:26:37.881085 Dram Type= 6, Freq= 0, CH_1, rank 0
6612 19:26:37.881167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6613 19:26:37.881255 ==
6614 19:26:37.881311 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6615 19:26:37.881365 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6616 19:26:37.881418 [CA 0] Center 36 (8~64) winsize 57
6617 19:26:37.881471 [CA 1] Center 36 (8~64) winsize 57
6618 19:26:37.881522 [CA 2] Center 36 (8~64) winsize 57
6619 19:26:37.881575 [CA 3] Center 36 (8~64) winsize 57
6620 19:26:37.881627 [CA 4] Center 36 (8~64) winsize 57
6621 19:26:37.881680 [CA 5] Center 36 (8~64) winsize 57
6622 19:26:37.881732
6623 19:26:37.881785 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6624 19:26:37.881837
6625 19:26:37.881889 [CATrainingPosCal] consider 1 rank data
6626 19:26:37.881942 u2DelayCellTimex100 = 270/100 ps
6627 19:26:37.881994 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6628 19:26:37.882047 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 19:26:37.882100 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 19:26:37.882152 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 19:26:37.882204 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 19:26:37.882256 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 19:26:37.882308
6634 19:26:37.882360 CA PerBit enable=1, Macro0, CA PI delay=36
6635 19:26:37.882413
6636 19:26:37.882464 [CBTSetCACLKResult] CA Dly = 36
6637 19:26:37.882517 CS Dly: 1 (0~32)
6638 19:26:37.882569 ==
6639 19:26:37.882621 Dram Type= 6, Freq= 0, CH_1, rank 1
6640 19:26:37.882674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6641 19:26:37.882726 ==
6642 19:26:37.882779 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6643 19:26:37.882832 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6644 19:26:37.882885 [CA 0] Center 36 (8~64) winsize 57
6645 19:26:37.882936 [CA 1] Center 36 (8~64) winsize 57
6646 19:26:37.882988 [CA 2] Center 36 (8~64) winsize 57
6647 19:26:37.883040 [CA 3] Center 36 (8~64) winsize 57
6648 19:26:37.883092 [CA 4] Center 36 (8~64) winsize 57
6649 19:26:37.883144 [CA 5] Center 36 (8~64) winsize 57
6650 19:26:37.883196
6651 19:26:37.883248 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6652 19:26:37.883300
6653 19:26:37.883353 [CATrainingPosCal] consider 2 rank data
6654 19:26:37.883404 u2DelayCellTimex100 = 270/100 ps
6655 19:26:37.883477 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6656 19:26:37.883534 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6657 19:26:37.885175 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6658 19:26:37.888909 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6659 19:26:37.891810 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6660 19:26:37.895154 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6661 19:26:37.895284
6662 19:26:37.898684 CA PerBit enable=1, Macro0, CA PI delay=36
6663 19:26:37.898808
6664 19:26:37.902078 [CBTSetCACLKResult] CA Dly = 36
6665 19:26:37.905280 CS Dly: 1 (0~32)
6666 19:26:37.905410
6667 19:26:37.908725 ----->DramcWriteLeveling(PI) begin...
6668 19:26:37.908859 ==
6669 19:26:37.911780 Dram Type= 6, Freq= 0, CH_1, rank 0
6670 19:26:37.915576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6671 19:26:37.915695 ==
6672 19:26:37.918365 Write leveling (Byte 0): 40 => 8
6673 19:26:37.922061 Write leveling (Byte 1): 40 => 8
6674 19:26:37.924991 DramcWriteLeveling(PI) end<-----
6675 19:26:37.925106
6676 19:26:37.925212 ==
6677 19:26:37.928507 Dram Type= 6, Freq= 0, CH_1, rank 0
6678 19:26:37.932222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6679 19:26:37.932345 ==
6680 19:26:37.935451 [Gating] SW mode calibration
6681 19:26:37.941926 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6682 19:26:37.948555 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6683 19:26:37.952135 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6684 19:26:37.955160 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6685 19:26:37.962176 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6686 19:26:37.965776 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6687 19:26:37.968658 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6688 19:26:37.975659 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6689 19:26:37.978760 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6690 19:26:37.982041 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6691 19:26:37.988376 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6692 19:26:37.988592 Total UI for P1: 0, mck2ui 16
6693 19:26:37.991792 best dqsien dly found for B0: ( 0, 14, 24)
6694 19:26:37.995406 Total UI for P1: 0, mck2ui 16
6695 19:26:37.998542 best dqsien dly found for B1: ( 0, 14, 24)
6696 19:26:38.004947 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6697 19:26:38.008233 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6698 19:26:38.008361
6699 19:26:38.011666 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6700 19:26:38.015113 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6701 19:26:38.018540 [Gating] SW calibration Done
6702 19:26:38.018674 ==
6703 19:26:38.021742 Dram Type= 6, Freq= 0, CH_1, rank 0
6704 19:26:38.025072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6705 19:26:38.025240 ==
6706 19:26:38.028237 RX Vref Scan: 0
6707 19:26:38.028350
6708 19:26:38.028444 RX Vref 0 -> 0, step: 1
6709 19:26:38.028526
6710 19:26:38.031767 RX Delay -410 -> 252, step: 16
6711 19:26:38.035031 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6712 19:26:38.041693 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6713 19:26:38.044784 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6714 19:26:38.048225 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6715 19:26:38.051726 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6716 19:26:38.058608 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6717 19:26:38.061651 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6718 19:26:38.065204 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6719 19:26:38.068221 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6720 19:26:38.075320 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6721 19:26:38.078078 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6722 19:26:38.081670 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6723 19:26:38.085340 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6724 19:26:38.091409 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6725 19:26:38.094993 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6726 19:26:38.098092 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6727 19:26:38.098265 ==
6728 19:26:38.101933 Dram Type= 6, Freq= 0, CH_1, rank 0
6729 19:26:38.108255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6730 19:26:38.108403 ==
6731 19:26:38.108480 DQS Delay:
6732 19:26:38.111472 DQS0 = 51, DQS1 = 59
6733 19:26:38.111610 DQM Delay:
6734 19:26:38.111704 DQM0 = 19, DQM1 = 16
6735 19:26:38.114850 DQ Delay:
6736 19:26:38.118104 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6737 19:26:38.121730 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6738 19:26:38.121870 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6739 19:26:38.128310 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6740 19:26:38.128499
6741 19:26:38.128600
6742 19:26:38.128689 ==
6743 19:26:38.131509 Dram Type= 6, Freq= 0, CH_1, rank 0
6744 19:26:38.135304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6745 19:26:38.135447 ==
6746 19:26:38.135569
6747 19:26:38.135656
6748 19:26:38.138437 TX Vref Scan disable
6749 19:26:38.138535 == TX Byte 0 ==
6750 19:26:38.141529 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6751 19:26:38.148193 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6752 19:26:38.148332 == TX Byte 1 ==
6753 19:26:38.151681 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6754 19:26:38.158183 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6755 19:26:38.158332 ==
6756 19:26:38.161393 Dram Type= 6, Freq= 0, CH_1, rank 0
6757 19:26:38.164805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6758 19:26:38.164973 ==
6759 19:26:38.165088
6760 19:26:38.165180
6761 19:26:38.168017 TX Vref Scan disable
6762 19:26:38.168158 == TX Byte 0 ==
6763 19:26:38.171671 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6764 19:26:38.178429 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6765 19:26:38.178614 == TX Byte 1 ==
6766 19:26:38.181467 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6767 19:26:38.188539 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6768 19:26:38.188737
6769 19:26:38.188858 [DATLAT]
6770 19:26:38.191578 Freq=400, CH1 RK0
6771 19:26:38.191716
6772 19:26:38.191812 DATLAT Default: 0xf
6773 19:26:38.194609 0, 0xFFFF, sum = 0
6774 19:26:38.194729 1, 0xFFFF, sum = 0
6775 19:26:38.198371 2, 0xFFFF, sum = 0
6776 19:26:38.198508 3, 0xFFFF, sum = 0
6777 19:26:38.201608 4, 0xFFFF, sum = 0
6778 19:26:38.201732 5, 0xFFFF, sum = 0
6779 19:26:38.205230 6, 0xFFFF, sum = 0
6780 19:26:38.205360 7, 0xFFFF, sum = 0
6781 19:26:38.208170 8, 0xFFFF, sum = 0
6782 19:26:38.208307 9, 0xFFFF, sum = 0
6783 19:26:38.211960 10, 0xFFFF, sum = 0
6784 19:26:38.212116 11, 0xFFFF, sum = 0
6785 19:26:38.215064 12, 0xFFFF, sum = 0
6786 19:26:38.215217 13, 0x0, sum = 1
6787 19:26:38.218456 14, 0x0, sum = 2
6788 19:26:38.218616 15, 0x0, sum = 3
6789 19:26:38.221904 16, 0x0, sum = 4
6790 19:26:38.222064 best_step = 14
6791 19:26:38.222172
6792 19:26:38.222273 ==
6793 19:26:38.224828 Dram Type= 6, Freq= 0, CH_1, rank 0
6794 19:26:38.228330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6795 19:26:38.231992 ==
6796 19:26:38.232146 RX Vref Scan: 1
6797 19:26:38.232250
6798 19:26:38.234890 RX Vref 0 -> 0, step: 1
6799 19:26:38.235020
6800 19:26:38.238202 RX Delay -359 -> 252, step: 8
6801 19:26:38.238309
6802 19:26:38.241389 Set Vref, RX VrefLevel [Byte0]: 59
6803 19:26:38.244949 [Byte1]: 53
6804 19:26:38.245092
6805 19:26:38.248888 Final RX Vref Byte 0 = 59 to rank0
6806 19:26:38.251580 Final RX Vref Byte 1 = 53 to rank0
6807 19:26:38.255368 Final RX Vref Byte 0 = 59 to rank1
6808 19:26:38.258628 Final RX Vref Byte 1 = 53 to rank1==
6809 19:26:38.261672 Dram Type= 6, Freq= 0, CH_1, rank 0
6810 19:26:38.265067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6811 19:26:38.265278 ==
6812 19:26:38.268559 DQS Delay:
6813 19:26:38.268752 DQS0 = 48, DQS1 = 60
6814 19:26:38.271365 DQM Delay:
6815 19:26:38.271535 DQM0 = 12, DQM1 = 13
6816 19:26:38.271665 DQ Delay:
6817 19:26:38.274975 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6818 19:26:38.278148 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =12
6819 19:26:38.281849 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =12
6820 19:26:38.284706 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6821 19:26:38.284858
6822 19:26:38.284955
6823 19:26:38.295182 [DQSOSCAuto] RK0, (LSB)MR18= 0x8930, (MSB)MR19= 0xc0c, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
6824 19:26:38.298283 CH1 RK0: MR19=C0C, MR18=8930
6825 19:26:38.301475 CH1_RK0: MR19=0xC0C, MR18=0x8930, DQSOSC=392, MR23=63, INC=384, DEC=256
6826 19:26:38.304828 ==
6827 19:26:38.307957 Dram Type= 6, Freq= 0, CH_1, rank 1
6828 19:26:38.311549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6829 19:26:38.311696 ==
6830 19:26:38.314798 [Gating] SW mode calibration
6831 19:26:38.321341 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6832 19:26:38.324423 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6833 19:26:38.331597 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6834 19:26:38.334627 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6835 19:26:38.338093 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6836 19:26:38.344564 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6837 19:26:38.348084 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6838 19:26:38.351593 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6839 19:26:38.357913 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6840 19:26:38.361446 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6841 19:26:38.364832 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6842 19:26:38.368086 Total UI for P1: 0, mck2ui 16
6843 19:26:38.371477 best dqsien dly found for B0: ( 0, 14, 24)
6844 19:26:38.374654 Total UI for P1: 0, mck2ui 16
6845 19:26:38.377813 best dqsien dly found for B1: ( 0, 14, 24)
6846 19:26:38.381567 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6847 19:26:38.384499 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6848 19:26:38.384599
6849 19:26:38.388325 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6850 19:26:38.394805 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6851 19:26:38.394972 [Gating] SW calibration Done
6852 19:26:38.395085 ==
6853 19:26:38.397869 Dram Type= 6, Freq= 0, CH_1, rank 1
6854 19:26:38.404609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6855 19:26:38.404777 ==
6856 19:26:38.404888 RX Vref Scan: 0
6857 19:26:38.404987
6858 19:26:38.408059 RX Vref 0 -> 0, step: 1
6859 19:26:38.408187
6860 19:26:38.411434 RX Delay -410 -> 252, step: 16
6861 19:26:38.415040 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6862 19:26:38.418210 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6863 19:26:38.424808 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6864 19:26:38.428343 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6865 19:26:38.431843 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6866 19:26:38.435093 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6867 19:26:38.441107 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6868 19:26:38.444567 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6869 19:26:38.447946 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6870 19:26:38.451291 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6871 19:26:38.458095 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6872 19:26:38.461536 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6873 19:26:38.464541 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6874 19:26:38.468217 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6875 19:26:38.474716 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6876 19:26:38.478073 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6877 19:26:38.478213 ==
6878 19:26:38.481523 Dram Type= 6, Freq= 0, CH_1, rank 1
6879 19:26:38.484671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6880 19:26:38.484798 ==
6881 19:26:38.488143 DQS Delay:
6882 19:26:38.488262 DQS0 = 43, DQS1 = 59
6883 19:26:38.488349 DQM Delay:
6884 19:26:38.491936 DQM0 = 10, DQM1 = 20
6885 19:26:38.492051 DQ Delay:
6886 19:26:38.494940 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6887 19:26:38.498415 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6888 19:26:38.501571 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6889 19:26:38.504637 DQ12 =24, DQ13 =32, DQ14 =32, DQ15 =32
6890 19:26:38.504734
6891 19:26:38.504820
6892 19:26:38.504918 ==
6893 19:26:38.508179 Dram Type= 6, Freq= 0, CH_1, rank 1
6894 19:26:38.511428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6895 19:26:38.514552 ==
6896 19:26:38.514651
6897 19:26:38.514737
6898 19:26:38.514817 TX Vref Scan disable
6899 19:26:38.518063 == TX Byte 0 ==
6900 19:26:38.521157 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6901 19:26:38.524522 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6902 19:26:38.528243 == TX Byte 1 ==
6903 19:26:38.531596 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6904 19:26:38.534571 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6905 19:26:38.534680 ==
6906 19:26:38.537949 Dram Type= 6, Freq= 0, CH_1, rank 1
6907 19:26:38.541298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6908 19:26:38.544578 ==
6909 19:26:38.544679
6910 19:26:38.544746
6911 19:26:38.544806 TX Vref Scan disable
6912 19:26:38.547767 == TX Byte 0 ==
6913 19:26:38.551354 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6914 19:26:38.554384 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6915 19:26:38.557884 == TX Byte 1 ==
6916 19:26:38.561030 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6917 19:26:38.564655 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6918 19:26:38.564776
6919 19:26:38.564879 [DATLAT]
6920 19:26:38.568023 Freq=400, CH1 RK1
6921 19:26:38.568120
6922 19:26:38.571681 DATLAT Default: 0xe
6923 19:26:38.571818 0, 0xFFFF, sum = 0
6924 19:26:38.574392 1, 0xFFFF, sum = 0
6925 19:26:38.574487 2, 0xFFFF, sum = 0
6926 19:26:38.577960 3, 0xFFFF, sum = 0
6927 19:26:38.578063 4, 0xFFFF, sum = 0
6928 19:26:38.581522 5, 0xFFFF, sum = 0
6929 19:26:38.581625 6, 0xFFFF, sum = 0
6930 19:26:38.584538 7, 0xFFFF, sum = 0
6931 19:26:38.584629 8, 0xFFFF, sum = 0
6932 19:26:38.588034 9, 0xFFFF, sum = 0
6933 19:26:38.588155 10, 0xFFFF, sum = 0
6934 19:26:38.591401 11, 0xFFFF, sum = 0
6935 19:26:38.591524 12, 0xFFFF, sum = 0
6936 19:26:38.594413 13, 0x0, sum = 1
6937 19:26:38.594538 14, 0x0, sum = 2
6938 19:26:38.598018 15, 0x0, sum = 3
6939 19:26:38.598136 16, 0x0, sum = 4
6940 19:26:38.601354 best_step = 14
6941 19:26:38.601484
6942 19:26:38.601575 ==
6943 19:26:38.604387 Dram Type= 6, Freq= 0, CH_1, rank 1
6944 19:26:38.608009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6945 19:26:38.608140 ==
6946 19:26:38.608242 RX Vref Scan: 0
6947 19:26:38.611557
6948 19:26:38.611680 RX Vref 0 -> 0, step: 1
6949 19:26:38.611784
6950 19:26:38.614683 RX Delay -359 -> 252, step: 8
6951 19:26:38.622200 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6952 19:26:38.625917 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6953 19:26:38.628791 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
6954 19:26:38.632691 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6955 19:26:38.639046 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6956 19:26:38.642038 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6957 19:26:38.645762 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6958 19:26:38.648701 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
6959 19:26:38.655467 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6960 19:26:38.658914 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6961 19:26:38.662183 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6962 19:26:38.665201 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6963 19:26:38.672247 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6964 19:26:38.675363 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6965 19:26:38.678808 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6966 19:26:38.682095 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6967 19:26:38.685571 ==
6968 19:26:38.689028 Dram Type= 6, Freq= 0, CH_1, rank 1
6969 19:26:38.692040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6970 19:26:38.692135 ==
6971 19:26:38.692200 DQS Delay:
6972 19:26:38.695351 DQS0 = 52, DQS1 = 56
6973 19:26:38.695442 DQM Delay:
6974 19:26:38.698728 DQM0 = 13, DQM1 = 9
6975 19:26:38.698820 DQ Delay:
6976 19:26:38.702000 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6977 19:26:38.705431 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
6978 19:26:38.708605 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6979 19:26:38.712427 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6980 19:26:38.712533
6981 19:26:38.712614
6982 19:26:38.719133 [DQSOSCAuto] RK1, (LSB)MR18= 0x7d92, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 394 ps
6983 19:26:38.722299 CH1 RK1: MR19=C0C, MR18=7D92
6984 19:26:38.728925 CH1_RK1: MR19=0xC0C, MR18=0x7D92, DQSOSC=391, MR23=63, INC=386, DEC=257
6985 19:26:38.732255 [RxdqsGatingPostProcess] freq 400
6986 19:26:38.735852 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6987 19:26:38.739026 best DQS0 dly(2T, 0.5T) = (0, 10)
6988 19:26:38.742656 best DQS1 dly(2T, 0.5T) = (0, 10)
6989 19:26:38.745520 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6990 19:26:38.749137 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6991 19:26:38.752167 best DQS0 dly(2T, 0.5T) = (0, 10)
6992 19:26:38.755835 best DQS1 dly(2T, 0.5T) = (0, 10)
6993 19:26:38.758993 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6994 19:26:38.762148 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6995 19:26:38.765661 Pre-setting of DQS Precalculation
6996 19:26:38.769046 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6997 19:26:38.775505 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6998 19:26:38.785530 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6999 19:26:38.785691
7000 19:26:38.785788
7001 19:26:38.789200 [Calibration Summary] 800 Mbps
7002 19:26:38.789324 CH 0, Rank 0
7003 19:26:38.792302 SW Impedance : PASS
7004 19:26:38.792411 DUTY Scan : NO K
7005 19:26:38.795355 ZQ Calibration : PASS
7006 19:26:38.798536 Jitter Meter : NO K
7007 19:26:38.798653 CBT Training : PASS
7008 19:26:38.802030 Write leveling : PASS
7009 19:26:38.802153 RX DQS gating : PASS
7010 19:26:38.805630 RX DQ/DQS(RDDQC) : PASS
7011 19:26:38.808636 TX DQ/DQS : PASS
7012 19:26:38.808772 RX DATLAT : PASS
7013 19:26:38.812280 RX DQ/DQS(Engine): PASS
7014 19:26:38.815522 TX OE : NO K
7015 19:26:38.815649 All Pass.
7016 19:26:38.815758
7017 19:26:38.815872 CH 0, Rank 1
7018 19:26:38.818662 SW Impedance : PASS
7019 19:26:38.822150 DUTY Scan : NO K
7020 19:26:38.822233 ZQ Calibration : PASS
7021 19:26:38.825677 Jitter Meter : NO K
7022 19:26:38.828773 CBT Training : PASS
7023 19:26:38.828887 Write leveling : NO K
7024 19:26:38.831864 RX DQS gating : PASS
7025 19:26:38.835551 RX DQ/DQS(RDDQC) : PASS
7026 19:26:38.835660 TX DQ/DQS : PASS
7027 19:26:38.838576 RX DATLAT : PASS
7028 19:26:38.838659 RX DQ/DQS(Engine): PASS
7029 19:26:38.842088 TX OE : NO K
7030 19:26:38.842176 All Pass.
7031 19:26:38.842242
7032 19:26:38.845468 CH 1, Rank 0
7033 19:26:38.845567 SW Impedance : PASS
7034 19:26:38.848961 DUTY Scan : NO K
7035 19:26:38.852287 ZQ Calibration : PASS
7036 19:26:38.852385 Jitter Meter : NO K
7037 19:26:38.855146 CBT Training : PASS
7038 19:26:38.859053 Write leveling : PASS
7039 19:26:38.859143 RX DQS gating : PASS
7040 19:26:38.862062 RX DQ/DQS(RDDQC) : PASS
7041 19:26:38.865715 TX DQ/DQS : PASS
7042 19:26:38.865815 RX DATLAT : PASS
7043 19:26:38.868613 RX DQ/DQS(Engine): PASS
7044 19:26:38.872228 TX OE : NO K
7045 19:26:38.872319 All Pass.
7046 19:26:38.872385
7047 19:26:38.872445 CH 1, Rank 1
7048 19:26:38.875663 SW Impedance : PASS
7049 19:26:38.878607 DUTY Scan : NO K
7050 19:26:38.878702 ZQ Calibration : PASS
7051 19:26:38.882104 Jitter Meter : NO K
7052 19:26:38.885626 CBT Training : PASS
7053 19:26:38.885735 Write leveling : NO K
7054 19:26:38.888587 RX DQS gating : PASS
7055 19:26:38.888680 RX DQ/DQS(RDDQC) : PASS
7056 19:26:38.892058 TX DQ/DQS : PASS
7057 19:26:38.895191 RX DATLAT : PASS
7058 19:26:38.895295 RX DQ/DQS(Engine): PASS
7059 19:26:38.898979 TX OE : NO K
7060 19:26:38.899085 All Pass.
7061 19:26:38.899157
7062 19:26:38.901928 DramC Write-DBI off
7063 19:26:38.905243 PER_BANK_REFRESH: Hybrid Mode
7064 19:26:38.905344 TX_TRACKING: ON
7065 19:26:38.915951 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7066 19:26:38.918959 [FAST_K] Save calibration result to emmc
7067 19:26:38.922540 dramc_set_vcore_voltage set vcore to 725000
7068 19:26:38.925494 Read voltage for 1600, 0
7069 19:26:38.925603 Vio18 = 0
7070 19:26:38.925670 Vcore = 725000
7071 19:26:38.928629 Vdram = 0
7072 19:26:38.928722 Vddq = 0
7073 19:26:38.928788 Vmddr = 0
7074 19:26:38.935675 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7075 19:26:38.938791 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7076 19:26:38.942315 MEM_TYPE=3, freq_sel=13
7077 19:26:38.945789 sv_algorithm_assistance_LP4_3733
7078 19:26:38.948983 ============ PULL DRAM RESETB DOWN ============
7079 19:26:38.952016 ========== PULL DRAM RESETB DOWN end =========
7080 19:26:38.958879 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7081 19:26:38.962251 ===================================
7082 19:26:38.962401 LPDDR4 DRAM CONFIGURATION
7083 19:26:38.965515 ===================================
7084 19:26:38.968879 EX_ROW_EN[0] = 0x0
7085 19:26:38.972085 EX_ROW_EN[1] = 0x0
7086 19:26:38.972219 LP4Y_EN = 0x0
7087 19:26:38.975710 WORK_FSP = 0x1
7088 19:26:38.975842 WL = 0x5
7089 19:26:38.978822 RL = 0x5
7090 19:26:38.978926 BL = 0x2
7091 19:26:38.982053 RPST = 0x0
7092 19:26:38.982193 RD_PRE = 0x0
7093 19:26:38.985568 WR_PRE = 0x1
7094 19:26:38.985675 WR_PST = 0x1
7095 19:26:38.988936 DBI_WR = 0x0
7096 19:26:38.989065 DBI_RD = 0x0
7097 19:26:38.992638 OTF = 0x1
7098 19:26:38.995675 ===================================
7099 19:26:38.998743 ===================================
7100 19:26:38.998875 ANA top config
7101 19:26:39.002493 ===================================
7102 19:26:39.005416 DLL_ASYNC_EN = 0
7103 19:26:39.008787 ALL_SLAVE_EN = 0
7104 19:26:39.012319 NEW_RANK_MODE = 1
7105 19:26:39.012489 DLL_IDLE_MODE = 1
7106 19:26:39.015455 LP45_APHY_COMB_EN = 1
7107 19:26:39.019236 TX_ODT_DIS = 0
7108 19:26:39.022156 NEW_8X_MODE = 1
7109 19:26:39.025416 ===================================
7110 19:26:39.029126 ===================================
7111 19:26:39.032228 data_rate = 3200
7112 19:26:39.032389 CKR = 1
7113 19:26:39.035640 DQ_P2S_RATIO = 8
7114 19:26:39.038801 ===================================
7115 19:26:39.042214 CA_P2S_RATIO = 8
7116 19:26:39.045666 DQ_CA_OPEN = 0
7117 19:26:39.049115 DQ_SEMI_OPEN = 0
7118 19:26:39.049297 CA_SEMI_OPEN = 0
7119 19:26:39.051979 CA_FULL_RATE = 0
7120 19:26:39.055842 DQ_CKDIV4_EN = 0
7121 19:26:39.059271 CA_CKDIV4_EN = 0
7122 19:26:39.062330 CA_PREDIV_EN = 0
7123 19:26:39.065766 PH8_DLY = 12
7124 19:26:39.065921 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7125 19:26:39.069105 DQ_AAMCK_DIV = 4
7126 19:26:39.072321 CA_AAMCK_DIV = 4
7127 19:26:39.075385 CA_ADMCK_DIV = 4
7128 19:26:39.078758 DQ_TRACK_CA_EN = 0
7129 19:26:39.082540 CA_PICK = 1600
7130 19:26:39.085365 CA_MCKIO = 1600
7131 19:26:39.085531 MCKIO_SEMI = 0
7132 19:26:39.088862 PLL_FREQ = 3068
7133 19:26:39.092679 DQ_UI_PI_RATIO = 32
7134 19:26:39.095757 CA_UI_PI_RATIO = 0
7135 19:26:39.098729 ===================================
7136 19:26:39.102333 ===================================
7137 19:26:39.105468 memory_type:LPDDR4
7138 19:26:39.105637 GP_NUM : 10
7139 19:26:39.108930 SRAM_EN : 1
7140 19:26:39.109091 MD32_EN : 0
7141 19:26:39.112536 ===================================
7142 19:26:39.115611 [ANA_INIT] >>>>>>>>>>>>>>
7143 19:26:39.119272 <<<<<< [CONFIGURE PHASE]: ANA_TX
7144 19:26:39.122069 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7145 19:26:39.125363 ===================================
7146 19:26:39.129009 data_rate = 3200,PCW = 0X7600
7147 19:26:39.132247 ===================================
7148 19:26:39.135925 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7149 19:26:39.142605 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7150 19:26:39.145711 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7151 19:26:39.152225 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7152 19:26:39.155505 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7153 19:26:39.158962 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7154 19:26:39.159086 [ANA_INIT] flow start
7155 19:26:39.162637 [ANA_INIT] PLL >>>>>>>>
7156 19:26:39.165494 [ANA_INIT] PLL <<<<<<<<
7157 19:26:39.165677 [ANA_INIT] MIDPI >>>>>>>>
7158 19:26:39.168939 [ANA_INIT] MIDPI <<<<<<<<
7159 19:26:39.172592 [ANA_INIT] DLL >>>>>>>>
7160 19:26:39.172753 [ANA_INIT] DLL <<<<<<<<
7161 19:26:39.175844 [ANA_INIT] flow end
7162 19:26:39.179047 ============ LP4 DIFF to SE enter ============
7163 19:26:39.182241 ============ LP4 DIFF to SE exit ============
7164 19:26:39.185910 [ANA_INIT] <<<<<<<<<<<<<
7165 19:26:39.189499 [Flow] Enable top DCM control >>>>>
7166 19:26:39.192507 [Flow] Enable top DCM control <<<<<
7167 19:26:39.195800 Enable DLL master slave shuffle
7168 19:26:39.202543 ==============================================================
7169 19:26:39.202715 Gating Mode config
7170 19:26:39.209521 ==============================================================
7171 19:26:39.209687 Config description:
7172 19:26:39.219406 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7173 19:26:39.226049 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7174 19:26:39.232328 SELPH_MODE 0: By rank 1: By Phase
7175 19:26:39.235725 ==============================================================
7176 19:26:39.239439 GAT_TRACK_EN = 1
7177 19:26:39.242527 RX_GATING_MODE = 2
7178 19:26:39.246064 RX_GATING_TRACK_MODE = 2
7179 19:26:39.248958 SELPH_MODE = 1
7180 19:26:39.252708 PICG_EARLY_EN = 1
7181 19:26:39.255810 VALID_LAT_VALUE = 1
7182 19:26:39.259082 ==============================================================
7183 19:26:39.262733 Enter into Gating configuration >>>>
7184 19:26:39.265724 Exit from Gating configuration <<<<
7185 19:26:39.269567 Enter into DVFS_PRE_config >>>>>
7186 19:26:39.282994 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7187 19:26:39.283160 Exit from DVFS_PRE_config <<<<<
7188 19:26:39.286043 Enter into PICG configuration >>>>
7189 19:26:39.289484 Exit from PICG configuration <<<<
7190 19:26:39.292869 [RX_INPUT] configuration >>>>>
7191 19:26:39.296501 [RX_INPUT] configuration <<<<<
7192 19:26:39.302679 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7193 19:26:39.306272 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7194 19:26:39.312983 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7195 19:26:39.319522 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7196 19:26:39.326261 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7197 19:26:39.333102 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7198 19:26:39.336149 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7199 19:26:39.339721 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7200 19:26:39.342696 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7201 19:26:39.349315 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7202 19:26:39.352991 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7203 19:26:39.356597 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7204 19:26:39.359801 ===================================
7205 19:26:39.362717 LPDDR4 DRAM CONFIGURATION
7206 19:26:39.366562 ===================================
7207 19:26:39.366704 EX_ROW_EN[0] = 0x0
7208 19:26:39.369461 EX_ROW_EN[1] = 0x0
7209 19:26:39.369588 LP4Y_EN = 0x0
7210 19:26:39.373179 WORK_FSP = 0x1
7211 19:26:39.376298 WL = 0x5
7212 19:26:39.376438 RL = 0x5
7213 19:26:39.379761 BL = 0x2
7214 19:26:39.379860 RPST = 0x0
7215 19:26:39.382906 RD_PRE = 0x0
7216 19:26:39.383062 WR_PRE = 0x1
7217 19:26:39.386535 WR_PST = 0x1
7218 19:26:39.386680 DBI_WR = 0x0
7219 19:26:39.389775 DBI_RD = 0x0
7220 19:26:39.389914 OTF = 0x1
7221 19:26:39.392728 ===================================
7222 19:26:39.396552 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7223 19:26:39.403103 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7224 19:26:39.406074 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7225 19:26:39.409254 ===================================
7226 19:26:39.413154 LPDDR4 DRAM CONFIGURATION
7227 19:26:39.416253 ===================================
7228 19:26:39.416401 EX_ROW_EN[0] = 0x10
7229 19:26:39.419544 EX_ROW_EN[1] = 0x0
7230 19:26:39.419664 LP4Y_EN = 0x0
7231 19:26:39.422990 WORK_FSP = 0x1
7232 19:26:39.423112 WL = 0x5
7233 19:26:39.426301 RL = 0x5
7234 19:26:39.426413 BL = 0x2
7235 19:26:39.429541 RPST = 0x0
7236 19:26:39.429672 RD_PRE = 0x0
7237 19:26:39.432755 WR_PRE = 0x1
7238 19:26:39.436724 WR_PST = 0x1
7239 19:26:39.436858 DBI_WR = 0x0
7240 19:26:39.439600 DBI_RD = 0x0
7241 19:26:39.439715 OTF = 0x1
7242 19:26:39.442901 ===================================
7243 19:26:39.449486 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7244 19:26:39.449636 ==
7245 19:26:39.452721 Dram Type= 6, Freq= 0, CH_0, rank 0
7246 19:26:39.455857 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7247 19:26:39.455970 ==
7248 19:26:39.459275 [Duty_Offset_Calibration]
7249 19:26:39.459378 B0:2 B1:-1 CA:1
7250 19:26:39.462828
7251 19:26:39.462941 [DutyScan_Calibration_Flow] k_type=0
7252 19:26:39.473275
7253 19:26:39.473435 ==CLK 0==
7254 19:26:39.477059 Final CLK duty delay cell = -4
7255 19:26:39.480052 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7256 19:26:39.483137 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7257 19:26:39.486801 [-4] AVG Duty = 4937%(X100)
7258 19:26:39.486942
7259 19:26:39.489955 CH0 CLK Duty spec in!! Max-Min= 187%
7260 19:26:39.493646 [DutyScan_Calibration_Flow] ====Done====
7261 19:26:39.493838
7262 19:26:39.496666 [DutyScan_Calibration_Flow] k_type=1
7263 19:26:39.512860
7264 19:26:39.513025 ==DQS 0 ==
7265 19:26:39.515910 Final DQS duty delay cell = 0
7266 19:26:39.519598 [0] MAX Duty = 5156%(X100), DQS PI = 20
7267 19:26:39.522930 [0] MIN Duty = 5000%(X100), DQS PI = 32
7268 19:26:39.523098 [0] AVG Duty = 5078%(X100)
7269 19:26:39.526367
7270 19:26:39.526501 ==DQS 1 ==
7271 19:26:39.529217 Final DQS duty delay cell = -4
7272 19:26:39.532907 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7273 19:26:39.536459 [-4] MIN Duty = 5000%(X100), DQS PI = 40
7274 19:26:39.539409 [-4] AVG Duty = 5046%(X100)
7275 19:26:39.539548
7276 19:26:39.543107 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7277 19:26:39.543236
7278 19:26:39.546330 CH0 DQS 1 Duty spec in!! Max-Min= 93%
7279 19:26:39.549611 [DutyScan_Calibration_Flow] ====Done====
7280 19:26:39.549744
7281 19:26:39.552481 [DutyScan_Calibration_Flow] k_type=3
7282 19:26:39.570153
7283 19:26:39.570318 ==DQM 0 ==
7284 19:26:39.573227 Final DQM duty delay cell = 0
7285 19:26:39.576583 [0] MAX Duty = 5000%(X100), DQS PI = 20
7286 19:26:39.579766 [0] MIN Duty = 4875%(X100), DQS PI = 4
7287 19:26:39.579867 [0] AVG Duty = 4937%(X100)
7288 19:26:39.583987
7289 19:26:39.584106 ==DQM 1 ==
7290 19:26:39.586938 Final DQM duty delay cell = 0
7291 19:26:39.589921 [0] MAX Duty = 5218%(X100), DQS PI = 58
7292 19:26:39.593578 [0] MIN Duty = 4969%(X100), DQS PI = 20
7293 19:26:39.593710 [0] AVG Duty = 5093%(X100)
7294 19:26:39.596616
7295 19:26:39.600328 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7296 19:26:39.600432
7297 19:26:39.603494 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7298 19:26:39.606918 [DutyScan_Calibration_Flow] ====Done====
7299 19:26:39.607071
7300 19:26:39.609757 [DutyScan_Calibration_Flow] k_type=2
7301 19:26:39.627548
7302 19:26:39.627735 ==DQ 0 ==
7303 19:26:39.630316 Final DQ duty delay cell = 0
7304 19:26:39.633950 [0] MAX Duty = 5156%(X100), DQS PI = 0
7305 19:26:39.637029 [0] MIN Duty = 5031%(X100), DQS PI = 10
7306 19:26:39.637126 [0] AVG Duty = 5093%(X100)
7307 19:26:39.637240
7308 19:26:39.640196 ==DQ 1 ==
7309 19:26:39.643964 Final DQ duty delay cell = 0
7310 19:26:39.647548 [0] MAX Duty = 5031%(X100), DQS PI = 30
7311 19:26:39.650476 [0] MIN Duty = 4907%(X100), DQS PI = 18
7312 19:26:39.650584 [0] AVG Duty = 4969%(X100)
7313 19:26:39.650657
7314 19:26:39.654159 CH0 DQ 0 Duty spec in!! Max-Min= 125%
7315 19:26:39.654277
7316 19:26:39.657046 CH0 DQ 1 Duty spec in!! Max-Min= 124%
7317 19:26:39.664025 [DutyScan_Calibration_Flow] ====Done====
7318 19:26:39.664180 ==
7319 19:26:39.667018 Dram Type= 6, Freq= 0, CH_1, rank 0
7320 19:26:39.670727 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7321 19:26:39.670813 ==
7322 19:26:39.673865 [Duty_Offset_Calibration]
7323 19:26:39.673947 B0:1 B1:1 CA:2
7324 19:26:39.674010
7325 19:26:39.677424 [DutyScan_Calibration_Flow] k_type=0
7326 19:26:39.687315
7327 19:26:39.687412 ==CLK 0==
7328 19:26:39.690676 Final CLK duty delay cell = 0
7329 19:26:39.693984 [0] MAX Duty = 5093%(X100), DQS PI = 36
7330 19:26:39.697377 [0] MIN Duty = 4969%(X100), DQS PI = 4
7331 19:26:39.697480 [0] AVG Duty = 5031%(X100)
7332 19:26:39.700275
7333 19:26:39.703810 CH1 CLK Duty spec in!! Max-Min= 124%
7334 19:26:39.707273 [DutyScan_Calibration_Flow] ====Done====
7335 19:26:39.707400
7336 19:26:39.710419 [DutyScan_Calibration_Flow] k_type=1
7337 19:26:39.727063
7338 19:26:39.727176 ==DQS 0 ==
7339 19:26:39.730036 Final DQS duty delay cell = 0
7340 19:26:39.733654 [0] MAX Duty = 5031%(X100), DQS PI = 52
7341 19:26:39.736650 [0] MIN Duty = 4844%(X100), DQS PI = 12
7342 19:26:39.740339 [0] AVG Duty = 4937%(X100)
7343 19:26:39.740437
7344 19:26:39.740539 ==DQS 1 ==
7345 19:26:39.743305 Final DQS duty delay cell = 0
7346 19:26:39.747406 [0] MAX Duty = 5062%(X100), DQS PI = 18
7347 19:26:39.749938 [0] MIN Duty = 4907%(X100), DQS PI = 46
7348 19:26:39.753676 [0] AVG Duty = 4984%(X100)
7349 19:26:39.753768
7350 19:26:39.756850 CH1 DQS 0 Duty spec in!! Max-Min= 187%
7351 19:26:39.756949
7352 19:26:39.760001 CH1 DQS 1 Duty spec in!! Max-Min= 155%
7353 19:26:39.763441 [DutyScan_Calibration_Flow] ====Done====
7354 19:26:39.763547
7355 19:26:39.766742 [DutyScan_Calibration_Flow] k_type=3
7356 19:26:39.783629
7357 19:26:39.783767 ==DQM 0 ==
7358 19:26:39.787283 Final DQM duty delay cell = 0
7359 19:26:39.790431 [0] MAX Duty = 5124%(X100), DQS PI = 52
7360 19:26:39.793529 [0] MIN Duty = 4876%(X100), DQS PI = 16
7361 19:26:39.793641 [0] AVG Duty = 5000%(X100)
7362 19:26:39.797296
7363 19:26:39.797396 ==DQM 1 ==
7364 19:26:39.800292 Final DQM duty delay cell = 0
7365 19:26:39.803784 [0] MAX Duty = 5187%(X100), DQS PI = 28
7366 19:26:39.807246 [0] MIN Duty = 4875%(X100), DQS PI = 50
7367 19:26:39.810197 [0] AVG Duty = 5031%(X100)
7368 19:26:39.810274
7369 19:26:39.813588 CH1 DQM 0 Duty spec in!! Max-Min= 248%
7370 19:26:39.813662
7371 19:26:39.816944 CH1 DQM 1 Duty spec in!! Max-Min= 312%
7372 19:26:39.820388 [DutyScan_Calibration_Flow] ====Done====
7373 19:26:39.820470
7374 19:26:39.823801 [DutyScan_Calibration_Flow] k_type=2
7375 19:26:39.840879
7376 19:26:39.841024 ==DQ 0 ==
7377 19:26:39.844569 Final DQ duty delay cell = 0
7378 19:26:39.847484 [0] MAX Duty = 5093%(X100), DQS PI = 52
7379 19:26:39.850576 [0] MIN Duty = 4938%(X100), DQS PI = 20
7380 19:26:39.850730 [0] AVG Duty = 5015%(X100)
7381 19:26:39.850835
7382 19:26:39.854363 ==DQ 1 ==
7383 19:26:39.857120 Final DQ duty delay cell = 0
7384 19:26:39.860992 [0] MAX Duty = 5125%(X100), DQS PI = 22
7385 19:26:39.864085 [0] MIN Duty = 5031%(X100), DQS PI = 0
7386 19:26:39.864276 [0] AVG Duty = 5078%(X100)
7387 19:26:39.864380
7388 19:26:39.867179 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7389 19:26:39.867294
7390 19:26:39.870785 CH1 DQ 1 Duty spec in!! Max-Min= 94%
7391 19:26:39.877474 [DutyScan_Calibration_Flow] ====Done====
7392 19:26:39.880981 nWR fixed to 30
7393 19:26:39.881101 [ModeRegInit_LP4] CH0 RK0
7394 19:26:39.883993 [ModeRegInit_LP4] CH0 RK1
7395 19:26:39.887371 [ModeRegInit_LP4] CH1 RK0
7396 19:26:39.887483 [ModeRegInit_LP4] CH1 RK1
7397 19:26:39.890668 match AC timing 5
7398 19:26:39.893730 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7399 19:26:39.897400 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7400 19:26:39.904034 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7401 19:26:39.907564 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7402 19:26:39.913940 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7403 19:26:39.914035 [MiockJmeterHQA]
7404 19:26:39.914101
7405 19:26:39.917077 [DramcMiockJmeter] u1RxGatingPI = 0
7406 19:26:39.920665 0 : 4257, 4029
7407 19:26:39.920750 4 : 4363, 4137
7408 19:26:39.920816 8 : 4255, 4029
7409 19:26:39.924130 12 : 4368, 4140
7410 19:26:39.924247 16 : 4257, 4029
7411 19:26:39.927269 20 : 4363, 4137
7412 19:26:39.927370 24 : 4252, 4027
7413 19:26:39.930794 28 : 4255, 4030
7414 19:26:39.930902 32 : 4252, 4027
7415 19:26:39.931006 36 : 4252, 4027
7416 19:26:39.934149 40 : 4252, 4027
7417 19:26:39.934261 44 : 4363, 4138
7418 19:26:39.937336 48 : 4257, 4029
7419 19:26:39.937421 52 : 4253, 4027
7420 19:26:39.940486 56 : 4255, 4029
7421 19:26:39.940589 60 : 4368, 4140
7422 19:26:39.943761 64 : 4253, 4026
7423 19:26:39.943915 68 : 4255, 4029
7424 19:26:39.944013 72 : 4250, 4026
7425 19:26:39.947384 76 : 4250, 4027
7426 19:26:39.947495 80 : 4252, 4029
7427 19:26:39.950753 84 : 4250, 4027
7428 19:26:39.950871 88 : 4361, 4137
7429 19:26:39.953820 92 : 4254, 4029
7430 19:26:39.953939 96 : 4363, 3275
7431 19:26:39.954042 100 : 4253, 0
7432 19:26:39.956946 104 : 4254, 0
7433 19:26:39.957085 108 : 4250, 0
7434 19:26:39.960511 112 : 4250, 0
7435 19:26:39.960651 116 : 4257, 0
7436 19:26:39.960761 120 : 4363, 0
7437 19:26:39.963632 124 : 4365, 0
7438 19:26:39.963753 128 : 4360, 0
7439 19:26:39.967192 132 : 4250, 0
7440 19:26:39.967269 136 : 4253, 0
7441 19:26:39.967333 140 : 4363, 0
7442 19:26:39.970794 144 : 4253, 0
7443 19:26:39.970875 148 : 4252, 0
7444 19:26:39.970937 152 : 4255, 0
7445 19:26:39.973886 156 : 4250, 0
7446 19:26:39.973962 160 : 4252, 0
7447 19:26:39.976974 164 : 4255, 0
7448 19:26:39.977077 168 : 4255, 0
7449 19:26:39.977176 172 : 4252, 0
7450 19:26:39.980418 176 : 4250, 0
7451 19:26:39.980492 180 : 4255, 0
7452 19:26:39.983703 184 : 4255, 0
7453 19:26:39.983817 188 : 4250, 0
7454 19:26:39.983910 192 : 4257, 0
7455 19:26:39.987017 196 : 4365, 0
7456 19:26:39.987150 200 : 4250, 0
7457 19:26:39.990502 204 : 4249, 0
7458 19:26:39.990615 208 : 4255, 0
7459 19:26:39.990684 212 : 4250, 49
7460 19:26:39.993669 216 : 4249, 3686
7461 19:26:39.993766 220 : 4252, 4029
7462 19:26:39.997242 224 : 4361, 4138
7463 19:26:39.997326 228 : 4363, 4140
7464 19:26:40.000614 232 : 4247, 4024
7465 19:26:40.000733 236 : 4253, 4029
7466 19:26:40.003713 240 : 4253, 4029
7467 19:26:40.003825 244 : 4250, 4027
7468 19:26:40.007336 248 : 4255, 4029
7469 19:26:40.007466 252 : 4250, 4026
7470 19:26:40.007563 256 : 4360, 4137
7471 19:26:40.010262 260 : 4250, 4027
7472 19:26:40.010364 264 : 4250, 4027
7473 19:26:40.013960 268 : 4251, 4027
7474 19:26:40.014032 272 : 4366, 4140
7475 19:26:40.016958 276 : 4253, 4029
7476 19:26:40.017054 280 : 4363, 4140
7477 19:26:40.020373 284 : 4363, 4140
7478 19:26:40.020460 288 : 4253, 4029
7479 19:26:40.023706 292 : 4250, 4026
7480 19:26:40.023785 296 : 4250, 4027
7481 19:26:40.027408 300 : 4255, 4032
7482 19:26:40.027482 304 : 4255, 4029
7483 19:26:40.027543 308 : 4250, 4027
7484 19:26:40.030443 312 : 4252, 4029
7485 19:26:40.030520 316 : 4254, 4030
7486 19:26:40.033715 320 : 4255, 4029
7487 19:26:40.033822 324 : 4252, 4029
7488 19:26:40.037086 328 : 4360, 4137
7489 19:26:40.037191 332 : 4360, 3082
7490 19:26:40.040828 336 : 4250, 82
7491 19:26:40.040904
7492 19:26:40.040966 MIOCK jitter meter ch=0
7493 19:26:40.041032
7494 19:26:40.043773 1T = (336-100) = 236 dly cells
7495 19:26:40.050765 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7496 19:26:40.050846 ==
7497 19:26:40.054011 Dram Type= 6, Freq= 0, CH_0, rank 0
7498 19:26:40.057220 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7499 19:26:40.057296 ==
7500 19:26:40.064167 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7501 19:26:40.067278 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7502 19:26:40.070798 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7503 19:26:40.077002 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7504 19:26:40.086865 [CA 0] Center 44 (14~75) winsize 62
7505 19:26:40.090221 [CA 1] Center 43 (13~74) winsize 62
7506 19:26:40.093939 [CA 2] Center 39 (10~68) winsize 59
7507 19:26:40.097187 [CA 3] Center 39 (10~68) winsize 59
7508 19:26:40.100182 [CA 4] Center 37 (8~67) winsize 60
7509 19:26:40.103853 [CA 5] Center 37 (7~67) winsize 61
7510 19:26:40.103960
7511 19:26:40.106967 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7512 19:26:40.107048
7513 19:26:40.110672 [CATrainingPosCal] consider 1 rank data
7514 19:26:40.113509 u2DelayCellTimex100 = 275/100 ps
7515 19:26:40.117154 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7516 19:26:40.123569 CA1 delay=43 (13~74),Diff = 6 PI (21 cell)
7517 19:26:40.127220 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7518 19:26:40.130307 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7519 19:26:40.134098 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7520 19:26:40.137003 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7521 19:26:40.137106
7522 19:26:40.140454 CA PerBit enable=1, Macro0, CA PI delay=37
7523 19:26:40.140537
7524 19:26:40.143794 [CBTSetCACLKResult] CA Dly = 37
7525 19:26:40.147325 CS Dly: 10 (0~41)
7526 19:26:40.150399 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7527 19:26:40.154024 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7528 19:26:40.154099 ==
7529 19:26:40.156991 Dram Type= 6, Freq= 0, CH_0, rank 1
7530 19:26:40.160658 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7531 19:26:40.163554 ==
7532 19:26:40.167164 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7533 19:26:40.170649 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7534 19:26:40.177518 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7535 19:26:40.180472 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7536 19:26:40.191104 [CA 0] Center 44 (14~75) winsize 62
7537 19:26:40.194016 [CA 1] Center 44 (14~75) winsize 62
7538 19:26:40.197732 [CA 2] Center 40 (10~70) winsize 61
7539 19:26:40.201198 [CA 3] Center 39 (10~69) winsize 60
7540 19:26:40.204495 [CA 4] Center 37 (8~67) winsize 60
7541 19:26:40.207778 [CA 5] Center 37 (7~67) winsize 61
7542 19:26:40.207880
7543 19:26:40.210701 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7544 19:26:40.210785
7545 19:26:40.214005 [CATrainingPosCal] consider 2 rank data
7546 19:26:40.217418 u2DelayCellTimex100 = 275/100 ps
7547 19:26:40.221079 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7548 19:26:40.227872 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7549 19:26:40.230887 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7550 19:26:40.234008 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7551 19:26:40.237868 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7552 19:26:40.241483 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7553 19:26:40.241562
7554 19:26:40.244537 CA PerBit enable=1, Macro0, CA PI delay=37
7555 19:26:40.244618
7556 19:26:40.247948 [CBTSetCACLKResult] CA Dly = 37
7557 19:26:40.251169 CS Dly: 11 (0~44)
7558 19:26:40.254640 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7559 19:26:40.257658 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7560 19:26:40.257740
7561 19:26:40.261082 ----->DramcWriteLeveling(PI) begin...
7562 19:26:40.261188 ==
7563 19:26:40.264202 Dram Type= 6, Freq= 0, CH_0, rank 0
7564 19:26:40.268061 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7565 19:26:40.271442 ==
7566 19:26:40.271520 Write leveling (Byte 0): 31 => 31
7567 19:26:40.274588 Write leveling (Byte 1): 27 => 27
7568 19:26:40.277913 DramcWriteLeveling(PI) end<-----
7569 19:26:40.278000
7570 19:26:40.278064 ==
7571 19:26:40.280797 Dram Type= 6, Freq= 0, CH_0, rank 0
7572 19:26:40.287610 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7573 19:26:40.287706 ==
7574 19:26:40.287774 [Gating] SW mode calibration
7575 19:26:40.297604 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7576 19:26:40.300885 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7577 19:26:40.304570 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7578 19:26:40.311214 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7579 19:26:40.314601 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7580 19:26:40.317529 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7581 19:26:40.324544 1 4 16 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (1 1)
7582 19:26:40.327529 1 4 20 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
7583 19:26:40.330708 1 4 24 | B1->B0 | 2b2b 3434 | 0 1 | (1 1) (1 1)
7584 19:26:40.337428 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7585 19:26:40.341283 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7586 19:26:40.344306 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7587 19:26:40.351024 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7588 19:26:40.354567 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7589 19:26:40.357569 1 5 16 | B1->B0 | 3434 2c2c | 1 1 | (1 1) (1 0)
7590 19:26:40.364353 1 5 20 | B1->B0 | 3434 2626 | 1 0 | (1 0) (0 0)
7591 19:26:40.367741 1 5 24 | B1->B0 | 2828 2323 | 0 0 | (0 1) (0 0)
7592 19:26:40.371118 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7593 19:26:40.377854 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7594 19:26:40.380885 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7595 19:26:40.384331 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7596 19:26:40.391230 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7597 19:26:40.394171 1 6 16 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
7598 19:26:40.397846 1 6 20 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
7599 19:26:40.400710 1 6 24 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
7600 19:26:40.407466 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7601 19:26:40.411011 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7602 19:26:40.414214 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7603 19:26:40.421225 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7604 19:26:40.424630 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7605 19:26:40.427926 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7606 19:26:40.434739 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7607 19:26:40.437762 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7608 19:26:40.441361 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7609 19:26:40.447574 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7610 19:26:40.451176 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7611 19:26:40.455149 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7612 19:26:40.461155 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7613 19:26:40.464836 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7614 19:26:40.467690 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7615 19:26:40.474514 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 19:26:40.478055 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 19:26:40.481048 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 19:26:40.484544 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 19:26:40.491207 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 19:26:40.494764 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 19:26:40.497916 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7622 19:26:40.504368 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7623 19:26:40.507610 Total UI for P1: 0, mck2ui 16
7624 19:26:40.511165 best dqsien dly found for B0: ( 1, 9, 16)
7625 19:26:40.514327 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7626 19:26:40.518117 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7627 19:26:40.521140 Total UI for P1: 0, mck2ui 16
7628 19:26:40.524623 best dqsien dly found for B1: ( 1, 9, 22)
7629 19:26:40.527837 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7630 19:26:40.531189 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7631 19:26:40.531273
7632 19:26:40.538010 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7633 19:26:40.541483 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7634 19:26:40.541568 [Gating] SW calibration Done
7635 19:26:40.544556 ==
7636 19:26:40.547745 Dram Type= 6, Freq= 0, CH_0, rank 0
7637 19:26:40.551239 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7638 19:26:40.551325 ==
7639 19:26:40.551389 RX Vref Scan: 0
7640 19:26:40.551448
7641 19:26:40.555136 RX Vref 0 -> 0, step: 1
7642 19:26:40.555211
7643 19:26:40.558199 RX Delay 0 -> 252, step: 8
7644 19:26:40.561674 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7645 19:26:40.564654 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7646 19:26:40.568182 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7647 19:26:40.575038 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7648 19:26:40.578158 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7649 19:26:40.581696 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7650 19:26:40.584473 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7651 19:26:40.587823 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7652 19:26:40.594694 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7653 19:26:40.598329 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7654 19:26:40.601639 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7655 19:26:40.604587 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7656 19:26:40.608237 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7657 19:26:40.614525 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7658 19:26:40.618070 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7659 19:26:40.621813 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7660 19:26:40.621892 ==
7661 19:26:40.624772 Dram Type= 6, Freq= 0, CH_0, rank 0
7662 19:26:40.627717 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7663 19:26:40.627825 ==
7664 19:26:40.631529 DQS Delay:
7665 19:26:40.631637 DQS0 = 0, DQS1 = 0
7666 19:26:40.634644 DQM Delay:
7667 19:26:40.634751 DQM0 = 132, DQM1 = 125
7668 19:26:40.634843 DQ Delay:
7669 19:26:40.641427 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7670 19:26:40.644856 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7671 19:26:40.647834 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =123
7672 19:26:40.651643 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7673 19:26:40.651738
7674 19:26:40.651811
7675 19:26:40.651871 ==
7676 19:26:40.654497 Dram Type= 6, Freq= 0, CH_0, rank 0
7677 19:26:40.658305 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7678 19:26:40.658391 ==
7679 19:26:40.658494
7680 19:26:40.658584
7681 19:26:40.661512 TX Vref Scan disable
7682 19:26:40.664424 == TX Byte 0 ==
7683 19:26:40.667719 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7684 19:26:40.671210 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7685 19:26:40.674398 == TX Byte 1 ==
7686 19:26:40.678073 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7687 19:26:40.681553 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7688 19:26:40.681638 ==
7689 19:26:40.684330 Dram Type= 6, Freq= 0, CH_0, rank 0
7690 19:26:40.688142 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7691 19:26:40.691336 ==
7692 19:26:40.703929
7693 19:26:40.707430 TX Vref early break, caculate TX vref
7694 19:26:40.710600 TX Vref=16, minBit 4, minWin=21, winSum=353
7695 19:26:40.713869 TX Vref=18, minBit 0, minWin=22, winSum=369
7696 19:26:40.717026 TX Vref=20, minBit 0, minWin=23, winSum=378
7697 19:26:40.720695 TX Vref=22, minBit 7, minWin=23, winSum=391
7698 19:26:40.724116 TX Vref=24, minBit 1, minWin=24, winSum=403
7699 19:26:40.730848 TX Vref=26, minBit 2, minWin=25, winSum=412
7700 19:26:40.733864 TX Vref=28, minBit 0, minWin=25, winSum=415
7701 19:26:40.737051 TX Vref=30, minBit 2, minWin=25, winSum=416
7702 19:26:40.740691 TX Vref=32, minBit 0, minWin=25, winSum=410
7703 19:26:40.743736 TX Vref=34, minBit 0, minWin=24, winSum=397
7704 19:26:40.746774 TX Vref=36, minBit 0, minWin=23, winSum=386
7705 19:26:40.753559 [TxChooseVref] Worse bit 2, Min win 25, Win sum 416, Final Vref 30
7706 19:26:40.753673
7707 19:26:40.757162 Final TX Range 0 Vref 30
7708 19:26:40.757267
7709 19:26:40.757354 ==
7710 19:26:40.760184 Dram Type= 6, Freq= 0, CH_0, rank 0
7711 19:26:40.764009 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7712 19:26:40.764091 ==
7713 19:26:40.764158
7714 19:26:40.764217
7715 19:26:40.766982 TX Vref Scan disable
7716 19:26:40.773707 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7717 19:26:40.773791 == TX Byte 0 ==
7718 19:26:40.777184 u2DelayCellOfst[0]=14 cells (4 PI)
7719 19:26:40.780248 u2DelayCellOfst[1]=21 cells (6 PI)
7720 19:26:40.783296 u2DelayCellOfst[2]=10 cells (3 PI)
7721 19:26:40.786841 u2DelayCellOfst[3]=14 cells (4 PI)
7722 19:26:40.789860 u2DelayCellOfst[4]=10 cells (3 PI)
7723 19:26:40.793621 u2DelayCellOfst[5]=0 cells (0 PI)
7724 19:26:40.796658 u2DelayCellOfst[6]=21 cells (6 PI)
7725 19:26:40.800226 u2DelayCellOfst[7]=21 cells (6 PI)
7726 19:26:40.803299 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7727 19:26:40.807062 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7728 19:26:40.810096 == TX Byte 1 ==
7729 19:26:40.813796 u2DelayCellOfst[8]=0 cells (0 PI)
7730 19:26:40.816767 u2DelayCellOfst[9]=0 cells (0 PI)
7731 19:26:40.819987 u2DelayCellOfst[10]=7 cells (2 PI)
7732 19:26:40.820069 u2DelayCellOfst[11]=0 cells (0 PI)
7733 19:26:40.823290 u2DelayCellOfst[12]=14 cells (4 PI)
7734 19:26:40.826632 u2DelayCellOfst[13]=10 cells (3 PI)
7735 19:26:40.829811 u2DelayCellOfst[14]=17 cells (5 PI)
7736 19:26:40.833230 u2DelayCellOfst[15]=10 cells (3 PI)
7737 19:26:40.840238 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7738 19:26:40.843789 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7739 19:26:40.843886 DramC Write-DBI on
7740 19:26:40.843953 ==
7741 19:26:40.846667 Dram Type= 6, Freq= 0, CH_0, rank 0
7742 19:26:40.853464 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7743 19:26:40.853565 ==
7744 19:26:40.853637
7745 19:26:40.853698
7746 19:26:40.853756 TX Vref Scan disable
7747 19:26:40.857581 == TX Byte 0 ==
7748 19:26:40.860901 Update DQM dly =732 (2 ,6, 28) DQM OEN =(3 ,3)
7749 19:26:40.864074 == TX Byte 1 ==
7750 19:26:40.867157 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7751 19:26:40.871000 DramC Write-DBI off
7752 19:26:40.871085
7753 19:26:40.871150 [DATLAT]
7754 19:26:40.871209 Freq=1600, CH0 RK0
7755 19:26:40.871274
7756 19:26:40.874092 DATLAT Default: 0xf
7757 19:26:40.874168 0, 0xFFFF, sum = 0
7758 19:26:40.877596 1, 0xFFFF, sum = 0
7759 19:26:40.880318 2, 0xFFFF, sum = 0
7760 19:26:40.880396 3, 0xFFFF, sum = 0
7761 19:26:40.883975 4, 0xFFFF, sum = 0
7762 19:26:40.884064 5, 0xFFFF, sum = 0
7763 19:26:40.887499 6, 0xFFFF, sum = 0
7764 19:26:40.887576 7, 0xFFFF, sum = 0
7765 19:26:40.890982 8, 0xFFFF, sum = 0
7766 19:26:40.891058 9, 0xFFFF, sum = 0
7767 19:26:40.893920 10, 0xFFFF, sum = 0
7768 19:26:40.894005 11, 0xFFFF, sum = 0
7769 19:26:40.897161 12, 0xFFFF, sum = 0
7770 19:26:40.897266 13, 0xFFFF, sum = 0
7771 19:26:40.900707 14, 0x0, sum = 1
7772 19:26:40.900779 15, 0x0, sum = 2
7773 19:26:40.903553 16, 0x0, sum = 3
7774 19:26:40.903654 17, 0x0, sum = 4
7775 19:26:40.907271 best_step = 15
7776 19:26:40.907345
7777 19:26:40.907406 ==
7778 19:26:40.910853 Dram Type= 6, Freq= 0, CH_0, rank 0
7779 19:26:40.913803 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7780 19:26:40.913884 ==
7781 19:26:40.917220 RX Vref Scan: 1
7782 19:26:40.917314
7783 19:26:40.917379 Set Vref Range= 24 -> 127
7784 19:26:40.917438
7785 19:26:40.920749 RX Vref 24 -> 127, step: 1
7786 19:26:40.920831
7787 19:26:40.923880 RX Delay 11 -> 252, step: 4
7788 19:26:40.923962
7789 19:26:40.927441 Set Vref, RX VrefLevel [Byte0]: 24
7790 19:26:40.930666 [Byte1]: 24
7791 19:26:40.930749
7792 19:26:40.933829 Set Vref, RX VrefLevel [Byte0]: 25
7793 19:26:40.937025 [Byte1]: 25
7794 19:26:40.937133
7795 19:26:40.940457 Set Vref, RX VrefLevel [Byte0]: 26
7796 19:26:40.944094 [Byte1]: 26
7797 19:26:40.947553
7798 19:26:40.947635 Set Vref, RX VrefLevel [Byte0]: 27
7799 19:26:40.951148 [Byte1]: 27
7800 19:26:40.955356
7801 19:26:40.955441 Set Vref, RX VrefLevel [Byte0]: 28
7802 19:26:40.958842 [Byte1]: 28
7803 19:26:40.963280
7804 19:26:40.963366 Set Vref, RX VrefLevel [Byte0]: 29
7805 19:26:40.966535 [Byte1]: 29
7806 19:26:40.970860
7807 19:26:40.970952 Set Vref, RX VrefLevel [Byte0]: 30
7808 19:26:40.973996 [Byte1]: 30
7809 19:26:40.978161
7810 19:26:40.978253 Set Vref, RX VrefLevel [Byte0]: 31
7811 19:26:40.981380 [Byte1]: 31
7812 19:26:40.985673
7813 19:26:40.985758 Set Vref, RX VrefLevel [Byte0]: 32
7814 19:26:40.989350 [Byte1]: 32
7815 19:26:40.993715
7816 19:26:40.993797 Set Vref, RX VrefLevel [Byte0]: 33
7817 19:26:40.997136 [Byte1]: 33
7818 19:26:41.001379
7819 19:26:41.001460 Set Vref, RX VrefLevel [Byte0]: 34
7820 19:26:41.004509 [Byte1]: 34
7821 19:26:41.008792
7822 19:26:41.008874 Set Vref, RX VrefLevel [Byte0]: 35
7823 19:26:41.014839 [Byte1]: 35
7824 19:26:41.014922
7825 19:26:41.018567 Set Vref, RX VrefLevel [Byte0]: 36
7826 19:26:41.021938 [Byte1]: 36
7827 19:26:41.022035
7828 19:26:41.025575 Set Vref, RX VrefLevel [Byte0]: 37
7829 19:26:41.028417 [Byte1]: 37
7830 19:26:41.028499
7831 19:26:41.031555 Set Vref, RX VrefLevel [Byte0]: 38
7832 19:26:41.035076 [Byte1]: 38
7833 19:26:41.039068
7834 19:26:41.039150 Set Vref, RX VrefLevel [Byte0]: 39
7835 19:26:41.042731 [Byte1]: 39
7836 19:26:41.046869
7837 19:26:41.046954 Set Vref, RX VrefLevel [Byte0]: 40
7838 19:26:41.050496 [Byte1]: 40
7839 19:26:41.054129
7840 19:26:41.054215 Set Vref, RX VrefLevel [Byte0]: 41
7841 19:26:41.057549 [Byte1]: 41
7842 19:26:41.061948
7843 19:26:41.062053 Set Vref, RX VrefLevel [Byte0]: 42
7844 19:26:41.065126 [Byte1]: 42
7845 19:26:41.069429
7846 19:26:41.069512 Set Vref, RX VrefLevel [Byte0]: 43
7847 19:26:41.072844 [Byte1]: 43
7848 19:26:41.077000
7849 19:26:41.077085 Set Vref, RX VrefLevel [Byte0]: 44
7850 19:26:41.080746 [Byte1]: 44
7851 19:26:41.084842
7852 19:26:41.084950 Set Vref, RX VrefLevel [Byte0]: 45
7853 19:26:41.088513 [Byte1]: 45
7854 19:26:41.092815
7855 19:26:41.092921 Set Vref, RX VrefLevel [Byte0]: 46
7856 19:26:41.095760 [Byte1]: 46
7857 19:26:41.100060
7858 19:26:41.100160 Set Vref, RX VrefLevel [Byte0]: 47
7859 19:26:41.103511 [Byte1]: 47
7860 19:26:41.107908
7861 19:26:41.108010 Set Vref, RX VrefLevel [Byte0]: 48
7862 19:26:41.110808 [Byte1]: 48
7863 19:26:41.115457
7864 19:26:41.115558 Set Vref, RX VrefLevel [Byte0]: 49
7865 19:26:41.118418 [Byte1]: 49
7866 19:26:41.123301
7867 19:26:41.123421 Set Vref, RX VrefLevel [Byte0]: 50
7868 19:26:41.126241 [Byte1]: 50
7869 19:26:41.130139
7870 19:26:41.130243 Set Vref, RX VrefLevel [Byte0]: 51
7871 19:26:41.133875 [Byte1]: 51
7872 19:26:41.138066
7873 19:26:41.138170 Set Vref, RX VrefLevel [Byte0]: 52
7874 19:26:41.141781 [Byte1]: 52
7875 19:26:41.145522
7876 19:26:41.145627 Set Vref, RX VrefLevel [Byte0]: 53
7877 19:26:41.149329 [Byte1]: 53
7878 19:26:41.153367
7879 19:26:41.153474 Set Vref, RX VrefLevel [Byte0]: 54
7880 19:26:41.156514 [Byte1]: 54
7881 19:26:41.160872
7882 19:26:41.160978 Set Vref, RX VrefLevel [Byte0]: 55
7883 19:26:41.164021 [Byte1]: 55
7884 19:26:41.168978
7885 19:26:41.169085 Set Vref, RX VrefLevel [Byte0]: 56
7886 19:26:41.172036 [Byte1]: 56
7887 19:26:41.176030
7888 19:26:41.176149 Set Vref, RX VrefLevel [Byte0]: 57
7889 19:26:41.179234 [Byte1]: 57
7890 19:26:41.183899
7891 19:26:41.184014 Set Vref, RX VrefLevel [Byte0]: 58
7892 19:26:41.186894 [Byte1]: 58
7893 19:26:41.191551
7894 19:26:41.191662 Set Vref, RX VrefLevel [Byte0]: 59
7895 19:26:41.194839 [Byte1]: 59
7896 19:26:41.199166
7897 19:26:41.199277 Set Vref, RX VrefLevel [Byte0]: 60
7898 19:26:41.202274 [Byte1]: 60
7899 19:26:41.206898
7900 19:26:41.207009 Set Vref, RX VrefLevel [Byte0]: 61
7901 19:26:41.209975 [Byte1]: 61
7902 19:26:41.214440
7903 19:26:41.214530 Set Vref, RX VrefLevel [Byte0]: 62
7904 19:26:41.217297 [Byte1]: 62
7905 19:26:41.221614
7906 19:26:41.221699 Set Vref, RX VrefLevel [Byte0]: 63
7907 19:26:41.224911 [Byte1]: 63
7908 19:26:41.229152
7909 19:26:41.229268 Set Vref, RX VrefLevel [Byte0]: 64
7910 19:26:41.232774 [Byte1]: 64
7911 19:26:41.237122
7912 19:26:41.237234 Set Vref, RX VrefLevel [Byte0]: 65
7913 19:26:41.240576 [Byte1]: 65
7914 19:26:41.244824
7915 19:26:41.244942 Set Vref, RX VrefLevel [Byte0]: 66
7916 19:26:41.248054 [Byte1]: 66
7917 19:26:41.252224
7918 19:26:41.252332 Set Vref, RX VrefLevel [Byte0]: 67
7919 19:26:41.255373 [Byte1]: 67
7920 19:26:41.259771
7921 19:26:41.259856 Set Vref, RX VrefLevel [Byte0]: 68
7922 19:26:41.263550 [Byte1]: 68
7923 19:26:41.267337
7924 19:26:41.267420 Set Vref, RX VrefLevel [Byte0]: 69
7925 19:26:41.270923 [Byte1]: 69
7926 19:26:41.275656
7927 19:26:41.275765 Set Vref, RX VrefLevel [Byte0]: 70
7928 19:26:41.278426 [Byte1]: 70
7929 19:26:41.282537
7930 19:26:41.282646 Set Vref, RX VrefLevel [Byte0]: 71
7931 19:26:41.286140 [Byte1]: 71
7932 19:26:41.290098
7933 19:26:41.290203 Set Vref, RX VrefLevel [Byte0]: 72
7934 19:26:41.293871 [Byte1]: 72
7935 19:26:41.297711
7936 19:26:41.297831 Set Vref, RX VrefLevel [Byte0]: 73
7937 19:26:41.301341 [Byte1]: 73
7938 19:26:41.306181
7939 19:26:41.306291 Set Vref, RX VrefLevel [Byte0]: 74
7940 19:26:41.308919 [Byte1]: 74
7941 19:26:41.313217
7942 19:26:41.313304 Set Vref, RX VrefLevel [Byte0]: 75
7943 19:26:41.316209 [Byte1]: 75
7944 19:26:41.320552
7945 19:26:41.320663 Set Vref, RX VrefLevel [Byte0]: 76
7946 19:26:41.324075 [Byte1]: 76
7947 19:26:41.328366
7948 19:26:41.328480 Final RX Vref Byte 0 = 62 to rank0
7949 19:26:41.331875 Final RX Vref Byte 1 = 62 to rank0
7950 19:26:41.334977 Final RX Vref Byte 0 = 62 to rank1
7951 19:26:41.338497 Final RX Vref Byte 1 = 62 to rank1==
7952 19:26:41.341988 Dram Type= 6, Freq= 0, CH_0, rank 0
7953 19:26:41.348401 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7954 19:26:41.348519 ==
7955 19:26:41.348620 DQS Delay:
7956 19:26:41.348722 DQS0 = 0, DQS1 = 0
7957 19:26:41.351477 DQM Delay:
7958 19:26:41.351583 DQM0 = 130, DQM1 = 122
7959 19:26:41.354717 DQ Delay:
7960 19:26:41.358248 DQ0 =130, DQ1 =134, DQ2 =126, DQ3 =126
7961 19:26:41.361960 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =138
7962 19:26:41.365215 DQ8 =110, DQ9 =110, DQ10 =122, DQ11 =116
7963 19:26:41.368092 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =134
7964 19:26:41.368202
7965 19:26:41.368297
7966 19:26:41.368386
7967 19:26:41.371378 [DramC_TX_OE_Calibration] TA2
7968 19:26:41.374795 Original DQ_B0 (3 6) =30, OEN = 27
7969 19:26:41.378251 Original DQ_B1 (3 6) =30, OEN = 27
7970 19:26:41.381858 24, 0x0, End_B0=24 End_B1=24
7971 19:26:41.381969 25, 0x0, End_B0=25 End_B1=25
7972 19:26:41.384951 26, 0x0, End_B0=26 End_B1=26
7973 19:26:41.388619 27, 0x0, End_B0=27 End_B1=27
7974 19:26:41.391747 28, 0x0, End_B0=28 End_B1=28
7975 19:26:41.391853 29, 0x0, End_B0=29 End_B1=29
7976 19:26:41.394895 30, 0x0, End_B0=30 End_B1=30
7977 19:26:41.398535 31, 0x5151, End_B0=30 End_B1=30
7978 19:26:41.401466 Byte0 end_step=30 best_step=27
7979 19:26:41.405103 Byte1 end_step=30 best_step=27
7980 19:26:41.408348 Byte0 TX OE(2T, 0.5T) = (3, 3)
7981 19:26:41.408459 Byte1 TX OE(2T, 0.5T) = (3, 3)
7982 19:26:41.408561
7983 19:26:41.411788
7984 19:26:41.418499 [DQSOSCAuto] RK0, (LSB)MR18= 0x1307, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 400 ps
7985 19:26:41.421692 CH0 RK0: MR19=303, MR18=1307
7986 19:26:41.428875 CH0_RK0: MR19=0x303, MR18=0x1307, DQSOSC=400, MR23=63, INC=23, DEC=15
7987 19:26:41.428989
7988 19:26:41.431975 ----->DramcWriteLeveling(PI) begin...
7989 19:26:41.432101 ==
7990 19:26:41.435090 Dram Type= 6, Freq= 0, CH_0, rank 1
7991 19:26:41.438862 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7992 19:26:41.438963 ==
7993 19:26:41.441925 Write leveling (Byte 0): 33 => 33
7994 19:26:41.445387 Write leveling (Byte 1): 25 => 25
7995 19:26:41.448790 DramcWriteLeveling(PI) end<-----
7996 19:26:41.448937
7997 19:26:41.449032 ==
7998 19:26:41.451893 Dram Type= 6, Freq= 0, CH_0, rank 1
7999 19:26:41.455526 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8000 19:26:41.455639 ==
8001 19:26:41.458420 [Gating] SW mode calibration
8002 19:26:41.465885 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8003 19:26:41.472410 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8004 19:26:41.475621 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8005 19:26:41.478746 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8006 19:26:41.485266 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8007 19:26:41.488815 1 4 12 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
8008 19:26:41.492107 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8009 19:26:41.495244 1 4 20 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
8010 19:26:41.501905 1 4 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8011 19:26:41.505195 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8012 19:26:41.508539 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8013 19:26:41.515242 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8014 19:26:41.518664 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8015 19:26:41.522092 1 5 12 | B1->B0 | 3434 2727 | 1 0 | (1 1) (1 0)
8016 19:26:41.528423 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8017 19:26:41.531931 1 5 20 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
8018 19:26:41.535707 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8019 19:26:41.542296 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8020 19:26:41.545529 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8021 19:26:41.549311 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8022 19:26:41.555480 1 6 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
8023 19:26:41.559139 1 6 12 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
8024 19:26:41.562198 1 6 16 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
8025 19:26:41.569102 1 6 20 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
8026 19:26:41.572023 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8027 19:26:41.575702 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8028 19:26:41.578680 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8029 19:26:41.585457 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8030 19:26:41.588468 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8031 19:26:41.592131 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8032 19:26:41.598868 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8033 19:26:41.602126 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8034 19:26:41.605550 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8035 19:26:41.611868 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8036 19:26:41.615333 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8037 19:26:41.618845 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8038 19:26:41.625176 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8039 19:26:41.628846 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8040 19:26:41.632060 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8041 19:26:41.638391 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 19:26:41.642267 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 19:26:41.645176 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 19:26:41.651835 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 19:26:41.655659 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8046 19:26:41.658975 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8047 19:26:41.665631 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8048 19:26:41.665718 Total UI for P1: 0, mck2ui 16
8049 19:26:41.668612 best dqsien dly found for B0: ( 1, 9, 6)
8050 19:26:41.675532 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8051 19:26:41.678576 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8052 19:26:41.682191 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8053 19:26:41.688637 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8054 19:26:41.692386 Total UI for P1: 0, mck2ui 16
8055 19:26:41.695389 best dqsien dly found for B1: ( 1, 9, 22)
8056 19:26:41.698836 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8057 19:26:41.702412 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
8058 19:26:41.702496
8059 19:26:41.705295 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8060 19:26:41.708601 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
8061 19:26:41.711988 [Gating] SW calibration Done
8062 19:26:41.712072 ==
8063 19:26:41.715333 Dram Type= 6, Freq= 0, CH_0, rank 1
8064 19:26:41.718992 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8065 19:26:41.719075 ==
8066 19:26:41.721980 RX Vref Scan: 0
8067 19:26:41.722063
8068 19:26:41.722128 RX Vref 0 -> 0, step: 1
8069 19:26:41.722188
8070 19:26:41.725184 RX Delay 0 -> 252, step: 8
8071 19:26:41.728634 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8072 19:26:41.735709 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8073 19:26:41.738701 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8074 19:26:41.742222 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8075 19:26:41.745718 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8076 19:26:41.748540 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8077 19:26:41.755392 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8078 19:26:41.758471 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8079 19:26:41.762161 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8080 19:26:41.765508 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8081 19:26:41.768459 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8082 19:26:41.775572 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8083 19:26:41.778696 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
8084 19:26:41.782093 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8085 19:26:41.785384 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8086 19:26:41.788858 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8087 19:26:41.788963 ==
8088 19:26:41.792253 Dram Type= 6, Freq= 0, CH_0, rank 1
8089 19:26:41.798953 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8090 19:26:41.799054 ==
8091 19:26:41.799145 DQS Delay:
8092 19:26:41.802112 DQS0 = 0, DQS1 = 0
8093 19:26:41.802212 DQM Delay:
8094 19:26:41.805439 DQM0 = 130, DQM1 = 125
8095 19:26:41.805550 DQ Delay:
8096 19:26:41.808825 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =127
8097 19:26:41.812627 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
8098 19:26:41.815710 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8099 19:26:41.818905 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =131
8100 19:26:41.819014
8101 19:26:41.819108
8102 19:26:41.819206 ==
8103 19:26:41.822234 Dram Type= 6, Freq= 0, CH_0, rank 1
8104 19:26:41.828675 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8105 19:26:41.828769 ==
8106 19:26:41.828870
8107 19:26:41.828988
8108 19:26:41.829084 TX Vref Scan disable
8109 19:26:41.832174 == TX Byte 0 ==
8110 19:26:41.835797 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8111 19:26:41.838912 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8112 19:26:41.842411 == TX Byte 1 ==
8113 19:26:41.845416 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8114 19:26:41.848856 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8115 19:26:41.852341 ==
8116 19:26:41.855768 Dram Type= 6, Freq= 0, CH_0, rank 1
8117 19:26:41.858606 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8118 19:26:41.858696 ==
8119 19:26:41.873496
8120 19:26:41.876563 TX Vref early break, caculate TX vref
8121 19:26:41.880253 TX Vref=16, minBit 8, minWin=22, winSum=373
8122 19:26:41.883417 TX Vref=18, minBit 9, minWin=22, winSum=378
8123 19:26:41.886477 TX Vref=20, minBit 3, minWin=23, winSum=393
8124 19:26:41.889783 TX Vref=22, minBit 9, minWin=23, winSum=399
8125 19:26:41.893511 TX Vref=24, minBit 9, minWin=24, winSum=405
8126 19:26:41.900125 TX Vref=26, minBit 8, minWin=25, winSum=414
8127 19:26:41.903081 TX Vref=28, minBit 1, minWin=25, winSum=414
8128 19:26:41.906965 TX Vref=30, minBit 10, minWin=25, winSum=421
8129 19:26:41.909898 TX Vref=32, minBit 2, minWin=25, winSum=413
8130 19:26:41.913430 TX Vref=34, minBit 8, minWin=24, winSum=406
8131 19:26:41.916751 TX Vref=36, minBit 0, minWin=24, winSum=395
8132 19:26:41.923490 [TxChooseVref] Worse bit 10, Min win 25, Win sum 421, Final Vref 30
8133 19:26:41.923574
8134 19:26:41.926731 Final TX Range 0 Vref 30
8135 19:26:41.926813
8136 19:26:41.926876 ==
8137 19:26:41.929866 Dram Type= 6, Freq= 0, CH_0, rank 1
8138 19:26:41.933152 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8139 19:26:41.933261 ==
8140 19:26:41.933327
8141 19:26:41.933386
8142 19:26:41.936498 TX Vref Scan disable
8143 19:26:41.943614 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8144 19:26:41.943696 == TX Byte 0 ==
8145 19:26:41.946420 u2DelayCellOfst[0]=10 cells (3 PI)
8146 19:26:41.949738 u2DelayCellOfst[1]=17 cells (5 PI)
8147 19:26:41.953521 u2DelayCellOfst[2]=10 cells (3 PI)
8148 19:26:41.956341 u2DelayCellOfst[3]=10 cells (3 PI)
8149 19:26:41.959625 u2DelayCellOfst[4]=7 cells (2 PI)
8150 19:26:41.963128 u2DelayCellOfst[5]=0 cells (0 PI)
8151 19:26:41.966425 u2DelayCellOfst[6]=17 cells (5 PI)
8152 19:26:41.969821 u2DelayCellOfst[7]=17 cells (5 PI)
8153 19:26:41.973504 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8154 19:26:41.976505 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8155 19:26:41.979679 == TX Byte 1 ==
8156 19:26:41.983248 u2DelayCellOfst[8]=0 cells (0 PI)
8157 19:26:41.983332 u2DelayCellOfst[9]=0 cells (0 PI)
8158 19:26:41.986484 u2DelayCellOfst[10]=7 cells (2 PI)
8159 19:26:41.990099 u2DelayCellOfst[11]=0 cells (0 PI)
8160 19:26:41.993054 u2DelayCellOfst[12]=10 cells (3 PI)
8161 19:26:41.996794 u2DelayCellOfst[13]=10 cells (3 PI)
8162 19:26:42.000194 u2DelayCellOfst[14]=14 cells (4 PI)
8163 19:26:42.003776 u2DelayCellOfst[15]=10 cells (3 PI)
8164 19:26:42.006768 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8165 19:26:42.013619 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8166 19:26:42.013722 DramC Write-DBI on
8167 19:26:42.013808 ==
8168 19:26:42.016804 Dram Type= 6, Freq= 0, CH_0, rank 1
8169 19:26:42.020222 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8170 19:26:42.023500 ==
8171 19:26:42.023582
8172 19:26:42.023665
8173 19:26:42.023744 TX Vref Scan disable
8174 19:26:42.027017 == TX Byte 0 ==
8175 19:26:42.030344 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8176 19:26:42.033753 == TX Byte 1 ==
8177 19:26:42.036960 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8178 19:26:42.040252 DramC Write-DBI off
8179 19:26:42.040337
8180 19:26:42.040421 [DATLAT]
8181 19:26:42.040501 Freq=1600, CH0 RK1
8182 19:26:42.040579
8183 19:26:42.043322 DATLAT Default: 0xf
8184 19:26:42.043406 0, 0xFFFF, sum = 0
8185 19:26:42.047034 1, 0xFFFF, sum = 0
8186 19:26:42.047119 2, 0xFFFF, sum = 0
8187 19:26:42.050296 3, 0xFFFF, sum = 0
8188 19:26:42.050376 4, 0xFFFF, sum = 0
8189 19:26:42.053405 5, 0xFFFF, sum = 0
8190 19:26:42.057241 6, 0xFFFF, sum = 0
8191 19:26:42.057323 7, 0xFFFF, sum = 0
8192 19:26:42.060276 8, 0xFFFF, sum = 0
8193 19:26:42.060357 9, 0xFFFF, sum = 0
8194 19:26:42.063534 10, 0xFFFF, sum = 0
8195 19:26:42.063615 11, 0xFFFF, sum = 0
8196 19:26:42.066935 12, 0xFFFF, sum = 0
8197 19:26:42.067014 13, 0xFFFF, sum = 0
8198 19:26:42.070517 14, 0x0, sum = 1
8199 19:26:42.070594 15, 0x0, sum = 2
8200 19:26:42.073920 16, 0x0, sum = 3
8201 19:26:42.073999 17, 0x0, sum = 4
8202 19:26:42.077290 best_step = 15
8203 19:26:42.077381
8204 19:26:42.077447 ==
8205 19:26:42.080447 Dram Type= 6, Freq= 0, CH_0, rank 1
8206 19:26:42.083997 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8207 19:26:42.084089 ==
8208 19:26:42.084153 RX Vref Scan: 0
8209 19:26:42.084223
8210 19:26:42.086881 RX Vref 0 -> 0, step: 1
8211 19:26:42.086959
8212 19:26:42.090301 RX Delay 11 -> 252, step: 4
8213 19:26:42.094055 iDelay=195, Bit 0, Center 126 (71 ~ 182) 112
8214 19:26:42.100802 iDelay=195, Bit 1, Center 130 (75 ~ 186) 112
8215 19:26:42.103527 iDelay=195, Bit 2, Center 124 (67 ~ 182) 116
8216 19:26:42.106948 iDelay=195, Bit 3, Center 126 (71 ~ 182) 112
8217 19:26:42.110598 iDelay=195, Bit 4, Center 128 (75 ~ 182) 108
8218 19:26:42.113713 iDelay=195, Bit 5, Center 116 (63 ~ 170) 108
8219 19:26:42.116808 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8220 19:26:42.123634 iDelay=195, Bit 7, Center 134 (79 ~ 190) 112
8221 19:26:42.127142 iDelay=195, Bit 8, Center 112 (59 ~ 166) 108
8222 19:26:42.130288 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8223 19:26:42.133695 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
8224 19:26:42.137025 iDelay=195, Bit 11, Center 116 (63 ~ 170) 108
8225 19:26:42.143721 iDelay=195, Bit 12, Center 126 (75 ~ 178) 104
8226 19:26:42.146910 iDelay=195, Bit 13, Center 128 (75 ~ 182) 108
8227 19:26:42.150334 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
8228 19:26:42.153520 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
8229 19:26:42.153603 ==
8230 19:26:42.157410 Dram Type= 6, Freq= 0, CH_0, rank 1
8231 19:26:42.163644 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8232 19:26:42.163725 ==
8233 19:26:42.163812 DQS Delay:
8234 19:26:42.166950 DQS0 = 0, DQS1 = 0
8235 19:26:42.167026 DQM Delay:
8236 19:26:42.167105 DQM0 = 127, DQM1 = 122
8237 19:26:42.170153 DQ Delay:
8238 19:26:42.173510 DQ0 =126, DQ1 =130, DQ2 =124, DQ3 =126
8239 19:26:42.177203 DQ4 =128, DQ5 =116, DQ6 =138, DQ7 =134
8240 19:26:42.179984 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
8241 19:26:42.183890 DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =130
8242 19:26:42.183976
8243 19:26:42.184060
8244 19:26:42.184139
8245 19:26:42.187240 [DramC_TX_OE_Calibration] TA2
8246 19:26:42.190190 Original DQ_B0 (3 6) =30, OEN = 27
8247 19:26:42.193485 Original DQ_B1 (3 6) =30, OEN = 27
8248 19:26:42.196820 24, 0x0, End_B0=24 End_B1=24
8249 19:26:42.196906 25, 0x0, End_B0=25 End_B1=25
8250 19:26:42.200459 26, 0x0, End_B0=26 End_B1=26
8251 19:26:42.203551 27, 0x0, End_B0=27 End_B1=27
8252 19:26:42.207214 28, 0x0, End_B0=28 End_B1=28
8253 19:26:42.210166 29, 0x0, End_B0=29 End_B1=29
8254 19:26:42.210251 30, 0x0, End_B0=30 End_B1=30
8255 19:26:42.213423 31, 0x4141, End_B0=30 End_B1=30
8256 19:26:42.216515 Byte0 end_step=30 best_step=27
8257 19:26:42.220248 Byte1 end_step=30 best_step=27
8258 19:26:42.223316 Byte0 TX OE(2T, 0.5T) = (3, 3)
8259 19:26:42.226823 Byte1 TX OE(2T, 0.5T) = (3, 3)
8260 19:26:42.226919
8261 19:26:42.227004
8262 19:26:42.233600 [DQSOSCAuto] RK1, (LSB)MR18= 0x180d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
8263 19:26:42.236507 CH0 RK1: MR19=303, MR18=180D
8264 19:26:42.243275 CH0_RK1: MR19=0x303, MR18=0x180D, DQSOSC=397, MR23=63, INC=23, DEC=15
8265 19:26:42.247026 [RxdqsGatingPostProcess] freq 1600
8266 19:26:42.250026 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8267 19:26:42.253523 best DQS0 dly(2T, 0.5T) = (1, 1)
8268 19:26:42.256707 best DQS1 dly(2T, 0.5T) = (1, 1)
8269 19:26:42.259762 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8270 19:26:42.263372 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8271 19:26:42.266694 best DQS0 dly(2T, 0.5T) = (1, 1)
8272 19:26:42.270218 best DQS1 dly(2T, 0.5T) = (1, 1)
8273 19:26:42.273396 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8274 19:26:42.276769 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8275 19:26:42.279848 Pre-setting of DQS Precalculation
8276 19:26:42.283318 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8277 19:26:42.283402 ==
8278 19:26:42.286652 Dram Type= 6, Freq= 0, CH_1, rank 0
8279 19:26:42.289855 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8280 19:26:42.289941 ==
8281 19:26:42.296621 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8282 19:26:42.300160 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8283 19:26:42.306518 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8284 19:26:42.309643 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8285 19:26:42.320141 [CA 0] Center 42 (13~71) winsize 59
8286 19:26:42.323326 [CA 1] Center 43 (14~72) winsize 59
8287 19:26:42.326524 [CA 2] Center 37 (8~66) winsize 59
8288 19:26:42.330134 [CA 3] Center 36 (7~65) winsize 59
8289 19:26:42.333340 [CA 4] Center 37 (7~67) winsize 61
8290 19:26:42.336820 [CA 5] Center 36 (7~66) winsize 60
8291 19:26:42.336905
8292 19:26:42.339968 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8293 19:26:42.340075
8294 19:26:42.343638 [CATrainingPosCal] consider 1 rank data
8295 19:26:42.346792 u2DelayCellTimex100 = 275/100 ps
8296 19:26:42.350307 CA0 delay=42 (13~71),Diff = 6 PI (21 cell)
8297 19:26:42.356999 CA1 delay=43 (14~72),Diff = 7 PI (24 cell)
8298 19:26:42.360079 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8299 19:26:42.363326 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8300 19:26:42.366873 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
8301 19:26:42.369791 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8302 19:26:42.369865
8303 19:26:42.373396 CA PerBit enable=1, Macro0, CA PI delay=36
8304 19:26:42.373473
8305 19:26:42.376992 [CBTSetCACLKResult] CA Dly = 36
8306 19:26:42.377074 CS Dly: 9 (0~40)
8307 19:26:42.383162 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8308 19:26:42.386874 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8309 19:26:42.386958 ==
8310 19:26:42.389804 Dram Type= 6, Freq= 0, CH_1, rank 1
8311 19:26:42.393190 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8312 19:26:42.393285 ==
8313 19:26:42.399743 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8314 19:26:42.403380 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8315 19:26:42.409944 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8316 19:26:42.413457 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8317 19:26:42.422895 [CA 0] Center 43 (14~72) winsize 59
8318 19:26:42.426893 [CA 1] Center 42 (14~71) winsize 58
8319 19:26:42.429834 [CA 2] Center 37 (9~66) winsize 58
8320 19:26:42.432892 [CA 3] Center 36 (7~66) winsize 60
8321 19:26:42.436528 [CA 4] Center 37 (8~67) winsize 60
8322 19:26:42.439554 [CA 5] Center 36 (7~66) winsize 60
8323 19:26:42.439629
8324 19:26:42.443307 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8325 19:26:42.443380
8326 19:26:42.446633 [CATrainingPosCal] consider 2 rank data
8327 19:26:42.449986 u2DelayCellTimex100 = 275/100 ps
8328 19:26:42.452942 CA0 delay=42 (14~71),Diff = 6 PI (21 cell)
8329 19:26:42.459737 CA1 delay=42 (14~71),Diff = 6 PI (21 cell)
8330 19:26:42.463307 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8331 19:26:42.466549 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8332 19:26:42.470120 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8333 19:26:42.473477 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8334 19:26:42.473558
8335 19:26:42.476524 CA PerBit enable=1, Macro0, CA PI delay=36
8336 19:26:42.476607
8337 19:26:42.479662 [CBTSetCACLKResult] CA Dly = 36
8338 19:26:42.479742 CS Dly: 11 (0~44)
8339 19:26:42.486350 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8340 19:26:42.489704 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8341 19:26:42.489785
8342 19:26:42.493305 ----->DramcWriteLeveling(PI) begin...
8343 19:26:42.493387 ==
8344 19:26:42.496289 Dram Type= 6, Freq= 0, CH_1, rank 0
8345 19:26:42.499712 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8346 19:26:42.503153 ==
8347 19:26:42.503238 Write leveling (Byte 0): 24 => 24
8348 19:26:42.506713 Write leveling (Byte 1): 27 => 27
8349 19:26:42.509424 DramcWriteLeveling(PI) end<-----
8350 19:26:42.509513
8351 19:26:42.509608 ==
8352 19:26:42.513022 Dram Type= 6, Freq= 0, CH_1, rank 0
8353 19:26:42.519730 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8354 19:26:42.519812 ==
8355 19:26:42.519899 [Gating] SW mode calibration
8356 19:26:42.529575 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8357 19:26:42.533072 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8358 19:26:42.536083 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8359 19:26:42.542818 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8360 19:26:42.546664 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8361 19:26:42.549654 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8362 19:26:42.555962 1 4 16 | B1->B0 | 2c2c 2525 | 1 1 | (0 0) (0 0)
8363 19:26:42.559547 1 4 20 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
8364 19:26:42.563152 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8365 19:26:42.569367 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8366 19:26:42.572909 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8367 19:26:42.576210 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8368 19:26:42.582778 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8369 19:26:42.586581 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8370 19:26:42.589507 1 5 16 | B1->B0 | 2e2e 3434 | 0 1 | (1 0) (1 0)
8371 19:26:42.596421 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8372 19:26:42.599276 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8373 19:26:42.602695 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8374 19:26:42.609146 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8375 19:26:42.612655 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8376 19:26:42.616154 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8377 19:26:42.623059 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8378 19:26:42.626409 1 6 16 | B1->B0 | 4343 3a3a | 0 0 | (0 0) (1 1)
8379 19:26:42.629369 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8380 19:26:42.636235 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8381 19:26:42.639366 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8382 19:26:42.642489 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8383 19:26:42.649100 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8384 19:26:42.652642 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8385 19:26:42.655772 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8386 19:26:42.659381 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8387 19:26:42.666090 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8388 19:26:42.669361 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8389 19:26:42.672820 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8390 19:26:42.679266 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8391 19:26:42.682391 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8392 19:26:42.686140 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 19:26:42.692895 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 19:26:42.696107 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 19:26:42.699017 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 19:26:42.705823 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 19:26:42.709327 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 19:26:42.712941 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 19:26:42.719527 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 19:26:42.722745 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 19:26:42.726130 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 19:26:42.732750 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8403 19:26:42.735948 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8404 19:26:42.739046 Total UI for P1: 0, mck2ui 16
8405 19:26:42.742773 best dqsien dly found for B0: ( 1, 9, 16)
8406 19:26:42.745715 Total UI for P1: 0, mck2ui 16
8407 19:26:42.749548 best dqsien dly found for B1: ( 1, 9, 16)
8408 19:26:42.752539 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8409 19:26:42.756139 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8410 19:26:42.756224
8411 19:26:42.759427 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8412 19:26:42.762623 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8413 19:26:42.766327 [Gating] SW calibration Done
8414 19:26:42.766443 ==
8415 19:26:42.769445 Dram Type= 6, Freq= 0, CH_1, rank 0
8416 19:26:42.772814 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8417 19:26:42.772892 ==
8418 19:26:42.776146 RX Vref Scan: 0
8419 19:26:42.776241
8420 19:26:42.779225 RX Vref 0 -> 0, step: 1
8421 19:26:42.779333
8422 19:26:42.779434 RX Delay 0 -> 252, step: 8
8423 19:26:42.785913 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8424 19:26:42.789306 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8425 19:26:42.792527 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8426 19:26:42.796203 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8427 19:26:42.799068 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8428 19:26:42.806063 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8429 19:26:42.809574 iDelay=208, Bit 6, Center 143 (96 ~ 191) 96
8430 19:26:42.812703 iDelay=208, Bit 7, Center 127 (72 ~ 183) 112
8431 19:26:42.816207 iDelay=208, Bit 8, Center 115 (64 ~ 167) 104
8432 19:26:42.819382 iDelay=208, Bit 9, Center 115 (64 ~ 167) 104
8433 19:26:42.822810 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8434 19:26:42.829091 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8435 19:26:42.832330 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8436 19:26:42.835879 iDelay=208, Bit 13, Center 135 (80 ~ 191) 112
8437 19:26:42.838977 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8438 19:26:42.845636 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8439 19:26:42.845764 ==
8440 19:26:42.849148 Dram Type= 6, Freq= 0, CH_1, rank 0
8441 19:26:42.852814 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8442 19:26:42.852930 ==
8443 19:26:42.853025 DQS Delay:
8444 19:26:42.855809 DQS0 = 0, DQS1 = 0
8445 19:26:42.855894 DQM Delay:
8446 19:26:42.859334 DQM0 = 135, DQM1 = 127
8447 19:26:42.859418 DQ Delay:
8448 19:26:42.862431 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8449 19:26:42.865898 DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =127
8450 19:26:42.869171 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
8451 19:26:42.872462 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8452 19:26:42.872544
8453 19:26:42.872609
8454 19:26:42.872668 ==
8455 19:26:42.875916 Dram Type= 6, Freq= 0, CH_1, rank 0
8456 19:26:42.882408 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8457 19:26:42.882490 ==
8458 19:26:42.882555
8459 19:26:42.882615
8460 19:26:42.882672 TX Vref Scan disable
8461 19:26:42.886153 == TX Byte 0 ==
8462 19:26:42.889903 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8463 19:26:42.896365 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8464 19:26:42.896474 == TX Byte 1 ==
8465 19:26:42.899774 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8466 19:26:42.902931 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8467 19:26:42.906272 ==
8468 19:26:42.909707 Dram Type= 6, Freq= 0, CH_1, rank 0
8469 19:26:42.913484 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8470 19:26:42.913567 ==
8471 19:26:42.925225
8472 19:26:42.928712 TX Vref early break, caculate TX vref
8473 19:26:42.932088 TX Vref=16, minBit 8, minWin=21, winSum=368
8474 19:26:42.935743 TX Vref=18, minBit 8, minWin=21, winSum=376
8475 19:26:42.938687 TX Vref=20, minBit 8, minWin=21, winSum=384
8476 19:26:42.941995 TX Vref=22, minBit 5, minWin=23, winSum=394
8477 19:26:42.945229 TX Vref=24, minBit 5, minWin=24, winSum=405
8478 19:26:42.951983 TX Vref=26, minBit 5, minWin=24, winSum=413
8479 19:26:42.955408 TX Vref=28, minBit 5, minWin=25, winSum=424
8480 19:26:42.958739 TX Vref=30, minBit 0, minWin=25, winSum=420
8481 19:26:42.962232 TX Vref=32, minBit 8, minWin=24, winSum=412
8482 19:26:42.965466 TX Vref=34, minBit 9, minWin=23, winSum=400
8483 19:26:42.972176 [TxChooseVref] Worse bit 5, Min win 25, Win sum 424, Final Vref 28
8484 19:26:42.972286
8485 19:26:42.975185 Final TX Range 0 Vref 28
8486 19:26:42.975268
8487 19:26:42.975333 ==
8488 19:26:42.978585 Dram Type= 6, Freq= 0, CH_1, rank 0
8489 19:26:42.982114 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8490 19:26:42.982196 ==
8491 19:26:42.982261
8492 19:26:42.982320
8493 19:26:42.985225 TX Vref Scan disable
8494 19:26:42.991987 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8495 19:26:42.992098 == TX Byte 0 ==
8496 19:26:42.995775 u2DelayCellOfst[0]=17 cells (5 PI)
8497 19:26:42.998622 u2DelayCellOfst[1]=10 cells (3 PI)
8498 19:26:43.002336 u2DelayCellOfst[2]=0 cells (0 PI)
8499 19:26:43.005371 u2DelayCellOfst[3]=3 cells (1 PI)
8500 19:26:43.009072 u2DelayCellOfst[4]=7 cells (2 PI)
8501 19:26:43.009181 u2DelayCellOfst[5]=21 cells (6 PI)
8502 19:26:43.012053 u2DelayCellOfst[6]=17 cells (5 PI)
8503 19:26:43.015775 u2DelayCellOfst[7]=3 cells (1 PI)
8504 19:26:43.022035 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8505 19:26:43.025664 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8506 19:26:43.025776 == TX Byte 1 ==
8507 19:26:43.028920 u2DelayCellOfst[8]=0 cells (0 PI)
8508 19:26:43.032459 u2DelayCellOfst[9]=3 cells (1 PI)
8509 19:26:43.035658 u2DelayCellOfst[10]=10 cells (3 PI)
8510 19:26:43.039285 u2DelayCellOfst[11]=7 cells (2 PI)
8511 19:26:43.042161 u2DelayCellOfst[12]=14 cells (4 PI)
8512 19:26:43.045821 u2DelayCellOfst[13]=17 cells (5 PI)
8513 19:26:43.049131 u2DelayCellOfst[14]=17 cells (5 PI)
8514 19:26:43.052441 u2DelayCellOfst[15]=17 cells (5 PI)
8515 19:26:43.055550 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8516 19:26:43.059037 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8517 19:26:43.062854 DramC Write-DBI on
8518 19:26:43.062956 ==
8519 19:26:43.065859 Dram Type= 6, Freq= 0, CH_1, rank 0
8520 19:26:43.069156 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8521 19:26:43.069236 ==
8522 19:26:43.069298
8523 19:26:43.069356
8524 19:26:43.072270 TX Vref Scan disable
8525 19:26:43.076099 == TX Byte 0 ==
8526 19:26:43.079156 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8527 19:26:43.079239 == TX Byte 1 ==
8528 19:26:43.085805 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8529 19:26:43.085893 DramC Write-DBI off
8530 19:26:43.085957
8531 19:26:43.086020 [DATLAT]
8532 19:26:43.088990 Freq=1600, CH1 RK0
8533 19:26:43.089072
8534 19:26:43.092349 DATLAT Default: 0xf
8535 19:26:43.092457 0, 0xFFFF, sum = 0
8536 19:26:43.095700 1, 0xFFFF, sum = 0
8537 19:26:43.095783 2, 0xFFFF, sum = 0
8538 19:26:43.098972 3, 0xFFFF, sum = 0
8539 19:26:43.099082 4, 0xFFFF, sum = 0
8540 19:26:43.102308 5, 0xFFFF, sum = 0
8541 19:26:43.102387 6, 0xFFFF, sum = 0
8542 19:26:43.105578 7, 0xFFFF, sum = 0
8543 19:26:43.105650 8, 0xFFFF, sum = 0
8544 19:26:43.109145 9, 0xFFFF, sum = 0
8545 19:26:43.109247 10, 0xFFFF, sum = 0
8546 19:26:43.112131 11, 0xFFFF, sum = 0
8547 19:26:43.112237 12, 0xFFFF, sum = 0
8548 19:26:43.115762 13, 0xFFFF, sum = 0
8549 19:26:43.115865 14, 0x0, sum = 1
8550 19:26:43.119098 15, 0x0, sum = 2
8551 19:26:43.119168 16, 0x0, sum = 3
8552 19:26:43.122082 17, 0x0, sum = 4
8553 19:26:43.122165 best_step = 15
8554 19:26:43.122237
8555 19:26:43.122299 ==
8556 19:26:43.125498 Dram Type= 6, Freq= 0, CH_1, rank 0
8557 19:26:43.132227 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8558 19:26:43.132310 ==
8559 19:26:43.132374 RX Vref Scan: 1
8560 19:26:43.132434
8561 19:26:43.135143 Set Vref Range= 24 -> 127
8562 19:26:43.135249
8563 19:26:43.138864 RX Vref 24 -> 127, step: 1
8564 19:26:43.138945
8565 19:26:43.142280 RX Delay 19 -> 252, step: 4
8566 19:26:43.142361
8567 19:26:43.142425 Set Vref, RX VrefLevel [Byte0]: 24
8568 19:26:43.145315 [Byte1]: 24
8569 19:26:43.149395
8570 19:26:43.149476 Set Vref, RX VrefLevel [Byte0]: 25
8571 19:26:43.153065 [Byte1]: 25
8572 19:26:43.157580
8573 19:26:43.157661 Set Vref, RX VrefLevel [Byte0]: 26
8574 19:26:43.160698 [Byte1]: 26
8575 19:26:43.164561
8576 19:26:43.164669 Set Vref, RX VrefLevel [Byte0]: 27
8577 19:26:43.168160 [Byte1]: 27
8578 19:26:43.172247
8579 19:26:43.172353 Set Vref, RX VrefLevel [Byte0]: 28
8580 19:26:43.175410 [Byte1]: 28
8581 19:26:43.180362
8582 19:26:43.180470 Set Vref, RX VrefLevel [Byte0]: 29
8583 19:26:43.183218 [Byte1]: 29
8584 19:26:43.187451
8585 19:26:43.187559 Set Vref, RX VrefLevel [Byte0]: 30
8586 19:26:43.190629 [Byte1]: 30
8587 19:26:43.195633
8588 19:26:43.195740 Set Vref, RX VrefLevel [Byte0]: 31
8589 19:26:43.198651 [Byte1]: 31
8590 19:26:43.202679
8591 19:26:43.202783 Set Vref, RX VrefLevel [Byte0]: 32
8592 19:26:43.206187 [Byte1]: 32
8593 19:26:43.210337
8594 19:26:43.210445 Set Vref, RX VrefLevel [Byte0]: 33
8595 19:26:43.213750 [Byte1]: 33
8596 19:26:43.218293
8597 19:26:43.218374 Set Vref, RX VrefLevel [Byte0]: 34
8598 19:26:43.221037 [Byte1]: 34
8599 19:26:43.225312
8600 19:26:43.225393 Set Vref, RX VrefLevel [Byte0]: 35
8601 19:26:43.228673 [Byte1]: 35
8602 19:26:43.233068
8603 19:26:43.233150 Set Vref, RX VrefLevel [Byte0]: 36
8604 19:26:43.236444 [Byte1]: 36
8605 19:26:43.241027
8606 19:26:43.241109 Set Vref, RX VrefLevel [Byte0]: 37
8607 19:26:43.243823 [Byte1]: 37
8608 19:26:43.248159
8609 19:26:43.248267 Set Vref, RX VrefLevel [Byte0]: 38
8610 19:26:43.251817 [Byte1]: 38
8611 19:26:43.256043
8612 19:26:43.256127 Set Vref, RX VrefLevel [Byte0]: 39
8613 19:26:43.259169 [Byte1]: 39
8614 19:26:43.263685
8615 19:26:43.263767 Set Vref, RX VrefLevel [Byte0]: 40
8616 19:26:43.266885 [Byte1]: 40
8617 19:26:43.270969
8618 19:26:43.271054 Set Vref, RX VrefLevel [Byte0]: 41
8619 19:26:43.274060 [Byte1]: 41
8620 19:26:43.278666
8621 19:26:43.278775 Set Vref, RX VrefLevel [Byte0]: 42
8622 19:26:43.281800 [Byte1]: 42
8623 19:26:43.286192
8624 19:26:43.286310 Set Vref, RX VrefLevel [Byte0]: 43
8625 19:26:43.289142 [Byte1]: 43
8626 19:26:43.293956
8627 19:26:43.294038 Set Vref, RX VrefLevel [Byte0]: 44
8628 19:26:43.296879 [Byte1]: 44
8629 19:26:43.301175
8630 19:26:43.301274 Set Vref, RX VrefLevel [Byte0]: 45
8631 19:26:43.304199 [Byte1]: 45
8632 19:26:43.309050
8633 19:26:43.309132 Set Vref, RX VrefLevel [Byte0]: 46
8634 19:26:43.312309 [Byte1]: 46
8635 19:26:43.316112
8636 19:26:43.316194 Set Vref, RX VrefLevel [Byte0]: 47
8637 19:26:43.319822 [Byte1]: 47
8638 19:26:43.324040
8639 19:26:43.324126 Set Vref, RX VrefLevel [Byte0]: 48
8640 19:26:43.327159 [Byte1]: 48
8641 19:26:43.331368
8642 19:26:43.331454 Set Vref, RX VrefLevel [Byte0]: 49
8643 19:26:43.334489 [Byte1]: 49
8644 19:26:43.338850
8645 19:26:43.338936 Set Vref, RX VrefLevel [Byte0]: 50
8646 19:26:43.342230 [Byte1]: 50
8647 19:26:43.346557
8648 19:26:43.346641 Set Vref, RX VrefLevel [Byte0]: 51
8649 19:26:43.349760 [Byte1]: 51
8650 19:26:43.354150
8651 19:26:43.354261 Set Vref, RX VrefLevel [Byte0]: 52
8652 19:26:43.357584 [Byte1]: 52
8653 19:26:43.361734
8654 19:26:43.361819 Set Vref, RX VrefLevel [Byte0]: 53
8655 19:26:43.365092 [Byte1]: 53
8656 19:26:43.369426
8657 19:26:43.369534 Set Vref, RX VrefLevel [Byte0]: 54
8658 19:26:43.372735 [Byte1]: 54
8659 19:26:43.376597
8660 19:26:43.376679 Set Vref, RX VrefLevel [Byte0]: 55
8661 19:26:43.380580 [Byte1]: 55
8662 19:26:43.384844
8663 19:26:43.384925 Set Vref, RX VrefLevel [Byte0]: 56
8664 19:26:43.387657 [Byte1]: 56
8665 19:26:43.392083
8666 19:26:43.392164 Set Vref, RX VrefLevel [Byte0]: 57
8667 19:26:43.395134 [Byte1]: 57
8668 19:26:43.400003
8669 19:26:43.400085 Set Vref, RX VrefLevel [Byte0]: 58
8670 19:26:43.403190 [Byte1]: 58
8671 19:26:43.406961
8672 19:26:43.407043 Set Vref, RX VrefLevel [Byte0]: 59
8673 19:26:43.410766 [Byte1]: 59
8674 19:26:43.414895
8675 19:26:43.414981 Set Vref, RX VrefLevel [Byte0]: 60
8676 19:26:43.417932 [Byte1]: 60
8677 19:26:43.422176
8678 19:26:43.422257 Set Vref, RX VrefLevel [Byte0]: 61
8679 19:26:43.425427 [Byte1]: 61
8680 19:26:43.430179
8681 19:26:43.430261 Set Vref, RX VrefLevel [Byte0]: 62
8682 19:26:43.432927 [Byte1]: 62
8683 19:26:43.437580
8684 19:26:43.437662 Set Vref, RX VrefLevel [Byte0]: 63
8685 19:26:43.440725 [Byte1]: 63
8686 19:26:43.444851
8687 19:26:43.444933 Set Vref, RX VrefLevel [Byte0]: 64
8688 19:26:43.448400 [Byte1]: 64
8689 19:26:43.452886
8690 19:26:43.452967 Set Vref, RX VrefLevel [Byte0]: 65
8691 19:26:43.455817 [Byte1]: 65
8692 19:26:43.459881
8693 19:26:43.459963 Set Vref, RX VrefLevel [Byte0]: 66
8694 19:26:43.463636 [Byte1]: 66
8695 19:26:43.467890
8696 19:26:43.467972 Set Vref, RX VrefLevel [Byte0]: 67
8697 19:26:43.471070 [Byte1]: 67
8698 19:26:43.475481
8699 19:26:43.475563 Set Vref, RX VrefLevel [Byte0]: 68
8700 19:26:43.478848 [Byte1]: 68
8701 19:26:43.482968
8702 19:26:43.483050 Set Vref, RX VrefLevel [Byte0]: 69
8703 19:26:43.486479 [Byte1]: 69
8704 19:26:43.490392
8705 19:26:43.490477 Set Vref, RX VrefLevel [Byte0]: 70
8706 19:26:43.493882 [Byte1]: 70
8707 19:26:43.497863
8708 19:26:43.497947 Set Vref, RX VrefLevel [Byte0]: 71
8709 19:26:43.501546 [Byte1]: 71
8710 19:26:43.505810
8711 19:26:43.505887 Set Vref, RX VrefLevel [Byte0]: 72
8712 19:26:43.509334 [Byte1]: 72
8713 19:26:43.513352
8714 19:26:43.513461 Final RX Vref Byte 0 = 61 to rank0
8715 19:26:43.516358 Final RX Vref Byte 1 = 54 to rank0
8716 19:26:43.520136 Final RX Vref Byte 0 = 61 to rank1
8717 19:26:43.523119 Final RX Vref Byte 1 = 54 to rank1==
8718 19:26:43.526868 Dram Type= 6, Freq= 0, CH_1, rank 0
8719 19:26:43.533020 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8720 19:26:43.533101 ==
8721 19:26:43.533201 DQS Delay:
8722 19:26:43.533288 DQS0 = 0, DQS1 = 0
8723 19:26:43.536554 DQM Delay:
8724 19:26:43.536650 DQM0 = 131, DQM1 = 124
8725 19:26:43.539593 DQ Delay:
8726 19:26:43.543347 DQ0 =134, DQ1 =126, DQ2 =120, DQ3 =128
8727 19:26:43.546633 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =126
8728 19:26:43.549980 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =120
8729 19:26:43.552897 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =132
8730 19:26:43.552981
8731 19:26:43.553080
8732 19:26:43.553178
8733 19:26:43.556486 [DramC_TX_OE_Calibration] TA2
8734 19:26:43.559873 Original DQ_B0 (3 6) =30, OEN = 27
8735 19:26:43.563469 Original DQ_B1 (3 6) =30, OEN = 27
8736 19:26:43.566484 24, 0x0, End_B0=24 End_B1=24
8737 19:26:43.566569 25, 0x0, End_B0=25 End_B1=25
8738 19:26:43.570152 26, 0x0, End_B0=26 End_B1=26
8739 19:26:43.573331 27, 0x0, End_B0=27 End_B1=27
8740 19:26:43.576730 28, 0x0, End_B0=28 End_B1=28
8741 19:26:43.576825 29, 0x0, End_B0=29 End_B1=29
8742 19:26:43.579834 30, 0x0, End_B0=30 End_B1=30
8743 19:26:43.583292 31, 0x4141, End_B0=30 End_B1=30
8744 19:26:43.586777 Byte0 end_step=30 best_step=27
8745 19:26:43.589921 Byte1 end_step=30 best_step=27
8746 19:26:43.593148 Byte0 TX OE(2T, 0.5T) = (3, 3)
8747 19:26:43.593243 Byte1 TX OE(2T, 0.5T) = (3, 3)
8748 19:26:43.593309
8749 19:26:43.596239
8750 19:26:43.603111 [DQSOSCAuto] RK0, (LSB)MR18= 0x14fe, (MSB)MR19= 0x302, tDQSOscB0 = 411 ps tDQSOscB1 = 399 ps
8751 19:26:43.606365 CH1 RK0: MR19=302, MR18=14FE
8752 19:26:43.612960 CH1_RK0: MR19=0x302, MR18=0x14FE, DQSOSC=399, MR23=63, INC=23, DEC=15
8753 19:26:43.613045
8754 19:26:43.616416 ----->DramcWriteLeveling(PI) begin...
8755 19:26:43.616523 ==
8756 19:26:43.619809 Dram Type= 6, Freq= 0, CH_1, rank 1
8757 19:26:43.622958 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8758 19:26:43.623043 ==
8759 19:26:43.626371 Write leveling (Byte 0): 27 => 27
8760 19:26:43.630210 Write leveling (Byte 1): 27 => 27
8761 19:26:43.633300 DramcWriteLeveling(PI) end<-----
8762 19:26:43.633382
8763 19:26:43.633445 ==
8764 19:26:43.636312 Dram Type= 6, Freq= 0, CH_1, rank 1
8765 19:26:43.639976 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8766 19:26:43.640060 ==
8767 19:26:43.643027 [Gating] SW mode calibration
8768 19:26:43.649570 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8769 19:26:43.656145 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8770 19:26:43.659665 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8771 19:26:43.662814 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8772 19:26:43.669436 1 4 8 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
8773 19:26:43.673035 1 4 12 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
8774 19:26:43.676385 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8775 19:26:43.683065 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8776 19:26:43.686227 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8777 19:26:43.689524 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8778 19:26:43.696724 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8779 19:26:43.699918 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8780 19:26:43.703024 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8781 19:26:43.710065 1 5 12 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
8782 19:26:43.712968 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8783 19:26:43.716650 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8784 19:26:43.719613 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8785 19:26:43.726239 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8786 19:26:43.729737 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8787 19:26:43.733174 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8788 19:26:43.739879 1 6 8 | B1->B0 | 2525 3b3b | 0 1 | (0 0) (0 0)
8789 19:26:43.743035 1 6 12 | B1->B0 | 3f3f 4545 | 0 0 | (0 0) (0 0)
8790 19:26:43.746166 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8791 19:26:43.752968 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8792 19:26:43.756595 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8793 19:26:43.759766 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8794 19:26:43.766237 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8795 19:26:43.770001 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8796 19:26:43.773070 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8797 19:26:43.779505 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8798 19:26:43.782682 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8799 19:26:43.786343 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 19:26:43.793180 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 19:26:43.796552 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 19:26:43.799587 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 19:26:43.806033 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 19:26:43.809386 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 19:26:43.812932 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 19:26:43.819836 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 19:26:43.822975 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 19:26:43.826198 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 19:26:43.829395 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 19:26:43.836520 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 19:26:43.839442 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8812 19:26:43.843068 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8813 19:26:43.850122 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8814 19:26:43.850263 Total UI for P1: 0, mck2ui 16
8815 19:26:43.856311 best dqsien dly found for B0: ( 1, 9, 6)
8816 19:26:43.860116 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8817 19:26:43.863053 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8818 19:26:43.866046 Total UI for P1: 0, mck2ui 16
8819 19:26:43.869916 best dqsien dly found for B1: ( 1, 9, 14)
8820 19:26:43.873083 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8821 19:26:43.876247 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8822 19:26:43.876356
8823 19:26:43.879837 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8824 19:26:43.886069 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8825 19:26:43.886198 [Gating] SW calibration Done
8826 19:26:43.889889 ==
8827 19:26:43.892736 Dram Type= 6, Freq= 0, CH_1, rank 1
8828 19:26:43.896516 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8829 19:26:43.896623 ==
8830 19:26:43.896691 RX Vref Scan: 0
8831 19:26:43.896753
8832 19:26:43.899679 RX Vref 0 -> 0, step: 1
8833 19:26:43.899770
8834 19:26:43.902692 RX Delay 0 -> 252, step: 8
8835 19:26:43.906530 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8836 19:26:43.909979 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8837 19:26:43.913417 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8838 19:26:43.920014 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8839 19:26:43.922872 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8840 19:26:43.926769 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8841 19:26:43.929888 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8842 19:26:43.933033 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8843 19:26:43.936268 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8844 19:26:43.942824 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8845 19:26:43.946559 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8846 19:26:43.949408 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8847 19:26:43.952702 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8848 19:26:43.959755 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8849 19:26:43.962868 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8850 19:26:43.966528 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8851 19:26:43.966651 ==
8852 19:26:43.969562 Dram Type= 6, Freq= 0, CH_1, rank 1
8853 19:26:43.973233 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8854 19:26:43.973359 ==
8855 19:26:43.976323 DQS Delay:
8856 19:26:43.976418 DQS0 = 0, DQS1 = 0
8857 19:26:43.979365 DQM Delay:
8858 19:26:43.979465 DQM0 = 132, DQM1 = 128
8859 19:26:43.979553 DQ Delay:
8860 19:26:43.982951 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8861 19:26:43.989718 DQ4 =131, DQ5 =147, DQ6 =143, DQ7 =127
8862 19:26:43.992822 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8863 19:26:43.996492 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =135
8864 19:26:43.996602
8865 19:26:43.996672
8866 19:26:43.996732 ==
8867 19:26:43.999446 Dram Type= 6, Freq= 0, CH_1, rank 1
8868 19:26:44.003161 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8869 19:26:44.003263 ==
8870 19:26:44.003331
8871 19:26:44.003392
8872 19:26:44.006444 TX Vref Scan disable
8873 19:26:44.009998 == TX Byte 0 ==
8874 19:26:44.013057 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8875 19:26:44.016532 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8876 19:26:44.019565 == TX Byte 1 ==
8877 19:26:44.023226 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8878 19:26:44.026631 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8879 19:26:44.026766 ==
8880 19:26:44.029485 Dram Type= 6, Freq= 0, CH_1, rank 1
8881 19:26:44.033134 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8882 19:26:44.033268 ==
8883 19:26:44.047838
8884 19:26:44.051404 TX Vref early break, caculate TX vref
8885 19:26:44.054412 TX Vref=16, minBit 6, minWin=22, winSum=376
8886 19:26:44.058034 TX Vref=18, minBit 0, minWin=23, winSum=388
8887 19:26:44.061073 TX Vref=20, minBit 5, minWin=24, winSum=394
8888 19:26:44.064557 TX Vref=22, minBit 0, minWin=24, winSum=398
8889 19:26:44.067972 TX Vref=24, minBit 0, minWin=25, winSum=414
8890 19:26:44.075045 TX Vref=26, minBit 9, minWin=25, winSum=417
8891 19:26:44.078054 TX Vref=28, minBit 15, minWin=25, winSum=423
8892 19:26:44.081159 TX Vref=30, minBit 0, minWin=25, winSum=421
8893 19:26:44.084851 TX Vref=32, minBit 0, minWin=25, winSum=416
8894 19:26:44.088005 TX Vref=34, minBit 0, minWin=23, winSum=403
8895 19:26:44.091106 TX Vref=36, minBit 0, minWin=23, winSum=393
8896 19:26:44.097792 [TxChooseVref] Worse bit 15, Min win 25, Win sum 423, Final Vref 28
8897 19:26:44.097927
8898 19:26:44.101157 Final TX Range 0 Vref 28
8899 19:26:44.101299
8900 19:26:44.101370 ==
8901 19:26:44.104315 Dram Type= 6, Freq= 0, CH_1, rank 1
8902 19:26:44.107979 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8903 19:26:44.108099 ==
8904 19:26:44.108195
8905 19:26:44.108291
8906 19:26:44.111421 TX Vref Scan disable
8907 19:26:44.118072 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8908 19:26:44.118230 == TX Byte 0 ==
8909 19:26:44.121547 u2DelayCellOfst[0]=17 cells (5 PI)
8910 19:26:44.124492 u2DelayCellOfst[1]=10 cells (3 PI)
8911 19:26:44.127666 u2DelayCellOfst[2]=0 cells (0 PI)
8912 19:26:44.131326 u2DelayCellOfst[3]=7 cells (2 PI)
8913 19:26:44.134449 u2DelayCellOfst[4]=10 cells (3 PI)
8914 19:26:44.137829 u2DelayCellOfst[5]=17 cells (5 PI)
8915 19:26:44.141548 u2DelayCellOfst[6]=17 cells (5 PI)
8916 19:26:44.144658 u2DelayCellOfst[7]=7 cells (2 PI)
8917 19:26:44.148401 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8918 19:26:44.151340 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8919 19:26:44.154908 == TX Byte 1 ==
8920 19:26:44.155043 u2DelayCellOfst[8]=0 cells (0 PI)
8921 19:26:44.158277 u2DelayCellOfst[9]=3 cells (1 PI)
8922 19:26:44.161146 u2DelayCellOfst[10]=10 cells (3 PI)
8923 19:26:44.164717 u2DelayCellOfst[11]=7 cells (2 PI)
8924 19:26:44.168510 u2DelayCellOfst[12]=14 cells (4 PI)
8925 19:26:44.171478 u2DelayCellOfst[13]=14 cells (4 PI)
8926 19:26:44.175094 u2DelayCellOfst[14]=17 cells (5 PI)
8927 19:26:44.177878 u2DelayCellOfst[15]=14 cells (4 PI)
8928 19:26:44.181687 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8929 19:26:44.188142 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8930 19:26:44.188299 DramC Write-DBI on
8931 19:26:44.188397 ==
8932 19:26:44.191302 Dram Type= 6, Freq= 0, CH_1, rank 1
8933 19:26:44.194840 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8934 19:26:44.197999 ==
8935 19:26:44.198099
8936 19:26:44.198165
8937 19:26:44.198225 TX Vref Scan disable
8938 19:26:44.201569 == TX Byte 0 ==
8939 19:26:44.204992 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8940 19:26:44.208203 == TX Byte 1 ==
8941 19:26:44.211251 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8942 19:26:44.211355 DramC Write-DBI off
8943 19:26:44.214776
8944 19:26:44.214891 [DATLAT]
8945 19:26:44.214985 Freq=1600, CH1 RK1
8946 19:26:44.215075
8947 19:26:44.217883 DATLAT Default: 0xf
8948 19:26:44.217973 0, 0xFFFF, sum = 0
8949 19:26:44.221576 1, 0xFFFF, sum = 0
8950 19:26:44.221670 2, 0xFFFF, sum = 0
8951 19:26:44.224868 3, 0xFFFF, sum = 0
8952 19:26:44.225003 4, 0xFFFF, sum = 0
8953 19:26:44.228009 5, 0xFFFF, sum = 0
8954 19:26:44.231480 6, 0xFFFF, sum = 0
8955 19:26:44.231586 7, 0xFFFF, sum = 0
8956 19:26:44.234673 8, 0xFFFF, sum = 0
8957 19:26:44.234769 9, 0xFFFF, sum = 0
8958 19:26:44.238008 10, 0xFFFF, sum = 0
8959 19:26:44.238101 11, 0xFFFF, sum = 0
8960 19:26:44.241528 12, 0xFFFF, sum = 0
8961 19:26:44.241628 13, 0xFFFF, sum = 0
8962 19:26:44.244729 14, 0x0, sum = 1
8963 19:26:44.244820 15, 0x0, sum = 2
8964 19:26:44.248254 16, 0x0, sum = 3
8965 19:26:44.248352 17, 0x0, sum = 4
8966 19:26:44.248420 best_step = 15
8967 19:26:44.251437
8968 19:26:44.251524 ==
8969 19:26:44.255240 Dram Type= 6, Freq= 0, CH_1, rank 1
8970 19:26:44.258334 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8971 19:26:44.258435 ==
8972 19:26:44.258504 RX Vref Scan: 0
8973 19:26:44.258566
8974 19:26:44.261335 RX Vref 0 -> 0, step: 1
8975 19:26:44.261424
8976 19:26:44.264932 RX Delay 11 -> 252, step: 4
8977 19:26:44.268228 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8978 19:26:44.271532 iDelay=191, Bit 1, Center 124 (71 ~ 178) 108
8979 19:26:44.278192 iDelay=191, Bit 2, Center 118 (67 ~ 170) 104
8980 19:26:44.281827 iDelay=191, Bit 3, Center 128 (79 ~ 178) 100
8981 19:26:44.284678 iDelay=191, Bit 4, Center 130 (79 ~ 182) 104
8982 19:26:44.287981 iDelay=191, Bit 5, Center 142 (95 ~ 190) 96
8983 19:26:44.291852 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8984 19:26:44.298280 iDelay=191, Bit 7, Center 124 (75 ~ 174) 100
8985 19:26:44.301493 iDelay=191, Bit 8, Center 114 (59 ~ 170) 112
8986 19:26:44.305060 iDelay=191, Bit 9, Center 114 (59 ~ 170) 112
8987 19:26:44.308217 iDelay=191, Bit 10, Center 126 (71 ~ 182) 112
8988 19:26:44.311618 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8989 19:26:44.318413 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8990 19:26:44.321593 iDelay=191, Bit 13, Center 136 (83 ~ 190) 108
8991 19:26:44.324898 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8992 19:26:44.328336 iDelay=191, Bit 15, Center 134 (83 ~ 186) 104
8993 19:26:44.328440 ==
8994 19:26:44.331801 Dram Type= 6, Freq= 0, CH_1, rank 1
8995 19:26:44.338191 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8996 19:26:44.338280 ==
8997 19:26:44.338348 DQS Delay:
8998 19:26:44.338409 DQS0 = 0, DQS1 = 0
8999 19:26:44.341554 DQM Delay:
9000 19:26:44.341637 DQM0 = 129, DQM1 = 126
9001 19:26:44.344860 DQ Delay:
9002 19:26:44.347952 DQ0 =134, DQ1 =124, DQ2 =118, DQ3 =128
9003 19:26:44.351430 DQ4 =130, DQ5 =142, DQ6 =138, DQ7 =124
9004 19:26:44.354801 DQ8 =114, DQ9 =114, DQ10 =126, DQ11 =118
9005 19:26:44.358401 DQ12 =134, DQ13 =136, DQ14 =134, DQ15 =134
9006 19:26:44.358486
9007 19:26:44.358550
9008 19:26:44.358610
9009 19:26:44.361859 [DramC_TX_OE_Calibration] TA2
9010 19:26:44.365264 Original DQ_B0 (3 6) =30, OEN = 27
9011 19:26:44.368577 Original DQ_B1 (3 6) =30, OEN = 27
9012 19:26:44.371889 24, 0x0, End_B0=24 End_B1=24
9013 19:26:44.372010 25, 0x0, End_B0=25 End_B1=25
9014 19:26:44.375090 26, 0x0, End_B0=26 End_B1=26
9015 19:26:44.378081 27, 0x0, End_B0=27 End_B1=27
9016 19:26:44.381844 28, 0x0, End_B0=28 End_B1=28
9017 19:26:44.381931 29, 0x0, End_B0=29 End_B1=29
9018 19:26:44.384728 30, 0x0, End_B0=30 End_B1=30
9019 19:26:44.387968 31, 0x4141, End_B0=30 End_B1=30
9020 19:26:44.391603 Byte0 end_step=30 best_step=27
9021 19:26:44.395242 Byte1 end_step=30 best_step=27
9022 19:26:44.398346 Byte0 TX OE(2T, 0.5T) = (3, 3)
9023 19:26:44.398440 Byte1 TX OE(2T, 0.5T) = (3, 3)
9024 19:26:44.398508
9025 19:26:44.398569
9026 19:26:44.408426 [DQSOSCAuto] RK1, (LSB)MR18= 0xf14, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 402 ps
9027 19:26:44.412006 CH1 RK1: MR19=303, MR18=F14
9028 19:26:44.415422 CH1_RK1: MR19=0x303, MR18=0xF14, DQSOSC=399, MR23=63, INC=23, DEC=15
9029 19:26:44.419087 [RxdqsGatingPostProcess] freq 1600
9030 19:26:44.425183 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9031 19:26:44.429080 best DQS0 dly(2T, 0.5T) = (1, 1)
9032 19:26:44.432162 best DQS1 dly(2T, 0.5T) = (1, 1)
9033 19:26:44.435660 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9034 19:26:44.438515 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9035 19:26:44.441772 best DQS0 dly(2T, 0.5T) = (1, 1)
9036 19:26:44.441868 best DQS1 dly(2T, 0.5T) = (1, 1)
9037 19:26:44.445230 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9038 19:26:44.448473 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9039 19:26:44.452049 Pre-setting of DQS Precalculation
9040 19:26:44.458636 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9041 19:26:44.464979 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9042 19:26:44.471977 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9043 19:26:44.472063
9044 19:26:44.472126
9045 19:26:44.475262 [Calibration Summary] 3200 Mbps
9046 19:26:44.475343 CH 0, Rank 0
9047 19:26:44.478320 SW Impedance : PASS
9048 19:26:44.481984 DUTY Scan : NO K
9049 19:26:44.482079 ZQ Calibration : PASS
9050 19:26:44.484949 Jitter Meter : NO K
9051 19:26:44.488198 CBT Training : PASS
9052 19:26:44.488348 Write leveling : PASS
9053 19:26:44.491868 RX DQS gating : PASS
9054 19:26:44.494984 RX DQ/DQS(RDDQC) : PASS
9055 19:26:44.495089 TX DQ/DQS : PASS
9056 19:26:44.498109 RX DATLAT : PASS
9057 19:26:44.501702 RX DQ/DQS(Engine): PASS
9058 19:26:44.501778 TX OE : PASS
9059 19:26:44.505046 All Pass.
9060 19:26:44.505166
9061 19:26:44.505278 CH 0, Rank 1
9062 19:26:44.508105 SW Impedance : PASS
9063 19:26:44.508239 DUTY Scan : NO K
9064 19:26:44.511591 ZQ Calibration : PASS
9065 19:26:44.514746 Jitter Meter : NO K
9066 19:26:44.514902 CBT Training : PASS
9067 19:26:44.518374 Write leveling : PASS
9068 19:26:44.521142 RX DQS gating : PASS
9069 19:26:44.521247 RX DQ/DQS(RDDQC) : PASS
9070 19:26:44.524953 TX DQ/DQS : PASS
9071 19:26:44.525036 RX DATLAT : PASS
9072 19:26:44.528102 RX DQ/DQS(Engine): PASS
9073 19:26:44.531548 TX OE : PASS
9074 19:26:44.531631 All Pass.
9075 19:26:44.531696
9076 19:26:44.531756 CH 1, Rank 0
9077 19:26:44.534914 SW Impedance : PASS
9078 19:26:44.538172 DUTY Scan : NO K
9079 19:26:44.538275 ZQ Calibration : PASS
9080 19:26:44.541666 Jitter Meter : NO K
9081 19:26:44.544954 CBT Training : PASS
9082 19:26:44.545034 Write leveling : PASS
9083 19:26:44.548277 RX DQS gating : PASS
9084 19:26:44.551839 RX DQ/DQS(RDDQC) : PASS
9085 19:26:44.551921 TX DQ/DQS : PASS
9086 19:26:44.555011 RX DATLAT : PASS
9087 19:26:44.558402 RX DQ/DQS(Engine): PASS
9088 19:26:44.558501 TX OE : PASS
9089 19:26:44.558596 All Pass.
9090 19:26:44.561559
9091 19:26:44.561655 CH 1, Rank 1
9092 19:26:44.564612 SW Impedance : PASS
9093 19:26:44.564692 DUTY Scan : NO K
9094 19:26:44.567932 ZQ Calibration : PASS
9095 19:26:44.568012 Jitter Meter : NO K
9096 19:26:44.571241 CBT Training : PASS
9097 19:26:44.575373 Write leveling : PASS
9098 19:26:44.575516 RX DQS gating : PASS
9099 19:26:44.578300 RX DQ/DQS(RDDQC) : PASS
9100 19:26:44.581674 TX DQ/DQS : PASS
9101 19:26:44.581771 RX DATLAT : PASS
9102 19:26:44.584663 RX DQ/DQS(Engine): PASS
9103 19:26:44.588342 TX OE : PASS
9104 19:26:44.588469 All Pass.
9105 19:26:44.588579
9106 19:26:44.588684 DramC Write-DBI on
9107 19:26:44.591627 PER_BANK_REFRESH: Hybrid Mode
9108 19:26:44.594675 TX_TRACKING: ON
9109 19:26:44.601323 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9110 19:26:44.611935 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9111 19:26:44.618344 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9112 19:26:44.621489 [FAST_K] Save calibration result to emmc
9113 19:26:44.625229 sync common calibartion params.
9114 19:26:44.625315 sync cbt_mode0:1, 1:1
9115 19:26:44.628194 dram_init: ddr_geometry: 2
9116 19:26:44.631858 dram_init: ddr_geometry: 2
9117 19:26:44.635074 dram_init: ddr_geometry: 2
9118 19:26:44.635157 0:dram_rank_size:100000000
9119 19:26:44.638192 1:dram_rank_size:100000000
9120 19:26:44.645034 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9121 19:26:44.645145 DFS_SHUFFLE_HW_MODE: ON
9122 19:26:44.651545 dramc_set_vcore_voltage set vcore to 725000
9123 19:26:44.651656 Read voltage for 1600, 0
9124 19:26:44.655005 Vio18 = 0
9125 19:26:44.655113 Vcore = 725000
9126 19:26:44.655204 Vdram = 0
9127 19:26:44.655296 Vddq = 0
9128 19:26:44.658422 Vmddr = 0
9129 19:26:44.658535 switch to 3200 Mbps bootup
9130 19:26:44.661903 [DramcRunTimeConfig]
9131 19:26:44.662006 PHYPLL
9132 19:26:44.665017 DPM_CONTROL_AFTERK: ON
9133 19:26:44.665131 PER_BANK_REFRESH: ON
9134 19:26:44.668424 REFRESH_OVERHEAD_REDUCTION: ON
9135 19:26:44.671563 CMD_PICG_NEW_MODE: OFF
9136 19:26:44.671674 XRTWTW_NEW_MODE: ON
9137 19:26:44.674807 XRTRTR_NEW_MODE: ON
9138 19:26:44.674912 TX_TRACKING: ON
9139 19:26:44.678311 RDSEL_TRACKING: OFF
9140 19:26:44.681543 DQS Precalculation for DVFS: ON
9141 19:26:44.681639 RX_TRACKING: OFF
9142 19:26:44.684894 HW_GATING DBG: ON
9143 19:26:44.685000 ZQCS_ENABLE_LP4: ON
9144 19:26:44.688429 RX_PICG_NEW_MODE: ON
9145 19:26:44.688534 TX_PICG_NEW_MODE: ON
9146 19:26:44.691517 ENABLE_RX_DCM_DPHY: ON
9147 19:26:44.695182 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9148 19:26:44.698320 DUMMY_READ_FOR_TRACKING: OFF
9149 19:26:44.701808 !!! SPM_CONTROL_AFTERK: OFF
9150 19:26:44.701901 !!! SPM could not control APHY
9151 19:26:44.704906 IMPEDANCE_TRACKING: ON
9152 19:26:44.705006 TEMP_SENSOR: ON
9153 19:26:44.708679 HW_SAVE_FOR_SR: OFF
9154 19:26:44.711717 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9155 19:26:44.714920 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9156 19:26:44.718609 Read ODT Tracking: ON
9157 19:26:44.718691 Refresh Rate DeBounce: ON
9158 19:26:44.721672 DFS_NO_QUEUE_FLUSH: ON
9159 19:26:44.725319 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9160 19:26:44.728601 ENABLE_DFS_RUNTIME_MRW: OFF
9161 19:26:44.728685 DDR_RESERVE_NEW_MODE: ON
9162 19:26:44.731767 MR_CBT_SWITCH_FREQ: ON
9163 19:26:44.735171 =========================
9164 19:26:44.752907 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9165 19:26:44.756080 dram_init: ddr_geometry: 2
9166 19:26:44.774232 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9167 19:26:44.777518 dram_init: dram init end (result: 0)
9168 19:26:44.783942 DRAM-K: Full calibration passed in 24559 msecs
9169 19:26:44.787403 MRC: failed to locate region type 0.
9170 19:26:44.787507 DRAM rank0 size:0x100000000,
9171 19:26:44.790560 DRAM rank1 size=0x100000000
9172 19:26:44.800856 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9173 19:26:44.807598 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9174 19:26:44.813703 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9175 19:26:44.820641 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9176 19:26:44.823841 DRAM rank0 size:0x100000000,
9177 19:26:44.827666 DRAM rank1 size=0x100000000
9178 19:26:44.827767 CBMEM:
9179 19:26:44.830740 IMD: root @ 0xfffff000 254 entries.
9180 19:26:44.834200 IMD: root @ 0xffffec00 62 entries.
9181 19:26:44.837159 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9182 19:26:44.841038 WARNING: RO_VPD is uninitialized or empty.
9183 19:26:44.847111 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9184 19:26:44.853906 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9185 19:26:44.866969 read SPI 0x42894 0xe01e: 6227 us, 9213 KB/s, 73.704 Mbps
9186 19:26:44.878305 BS: romstage times (exec / console): total (unknown) / 24064 ms
9187 19:26:44.878416
9188 19:26:44.878513
9189 19:26:44.888403 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9190 19:26:44.891645 ARM64: Exception handlers installed.
9191 19:26:44.895015 ARM64: Testing exception
9192 19:26:44.898439 ARM64: Done test exception
9193 19:26:44.898515 Enumerating buses...
9194 19:26:44.901726 Show all devs... Before device enumeration.
9195 19:26:44.905159 Root Device: enabled 1
9196 19:26:44.908293 CPU_CLUSTER: 0: enabled 1
9197 19:26:44.908363 CPU: 00: enabled 1
9198 19:26:44.912024 Compare with tree...
9199 19:26:44.912093 Root Device: enabled 1
9200 19:26:44.914987 CPU_CLUSTER: 0: enabled 1
9201 19:26:44.918672 CPU: 00: enabled 1
9202 19:26:44.918767 Root Device scanning...
9203 19:26:44.921924 scan_static_bus for Root Device
9204 19:26:44.925612 CPU_CLUSTER: 0 enabled
9205 19:26:44.928278 scan_static_bus for Root Device done
9206 19:26:44.931751 scan_bus: bus Root Device finished in 8 msecs
9207 19:26:44.931845 done
9208 19:26:44.938544 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9209 19:26:44.942232 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9210 19:26:44.945118 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9211 19:26:44.952295 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9212 19:26:44.955391 Allocating resources...
9213 19:26:44.955479 Reading resources...
9214 19:26:44.958591 Root Device read_resources bus 0 link: 0
9215 19:26:44.962209 DRAM rank0 size:0x100000000,
9216 19:26:44.965143 DRAM rank1 size=0x100000000
9217 19:26:44.969069 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9218 19:26:44.972091 CPU: 00 missing read_resources
9219 19:26:44.975318 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9220 19:26:44.978823 Root Device read_resources bus 0 link: 0 done
9221 19:26:44.982236 Done reading resources.
9222 19:26:44.988941 Show resources in subtree (Root Device)...After reading.
9223 19:26:44.992260 Root Device child on link 0 CPU_CLUSTER: 0
9224 19:26:44.995721 CPU_CLUSTER: 0 child on link 0 CPU: 00
9225 19:26:45.002091 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9226 19:26:45.005127 CPU: 00
9227 19:26:45.009111 Root Device assign_resources, bus 0 link: 0
9228 19:26:45.012066 CPU_CLUSTER: 0 missing set_resources
9229 19:26:45.015702 Root Device assign_resources, bus 0 link: 0 done
9230 19:26:45.018995 Done setting resources.
9231 19:26:45.025797 Show resources in subtree (Root Device)...After assigning values.
9232 19:26:45.028901 Root Device child on link 0 CPU_CLUSTER: 0
9233 19:26:45.031977 CPU_CLUSTER: 0 child on link 0 CPU: 00
9234 19:26:45.039275 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9235 19:26:45.042416 CPU: 00
9236 19:26:45.042512 Done allocating resources.
9237 19:26:45.049034 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9238 19:26:45.052265 Enabling resources...
9239 19:26:45.052371 done.
9240 19:26:45.055684 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9241 19:26:45.058841 Initializing devices...
9242 19:26:45.058938 Root Device init
9243 19:26:45.062069 init hardware done!
9244 19:26:45.065400 0x00000018: ctrlr->caps
9245 19:26:45.065499 52.000 MHz: ctrlr->f_max
9246 19:26:45.068857 0.400 MHz: ctrlr->f_min
9247 19:26:45.071865 0x40ff8080: ctrlr->voltages
9248 19:26:45.071962 sclk: 390625
9249 19:26:45.072048 Bus Width = 1
9250 19:26:45.075527 sclk: 390625
9251 19:26:45.075632 Bus Width = 1
9252 19:26:45.078572 Early init status = 3
9253 19:26:45.081992 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9254 19:26:45.085841 in-header: 03 fc 00 00 01 00 00 00
9255 19:26:45.089089 in-data: 00
9256 19:26:45.092882 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9257 19:26:45.097086 in-header: 03 fd 00 00 00 00 00 00
9258 19:26:45.100539 in-data:
9259 19:26:45.103478 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9260 19:26:45.106785 in-header: 03 fc 00 00 01 00 00 00
9261 19:26:45.110718 in-data: 00
9262 19:26:45.113357 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9263 19:26:45.118592 in-header: 03 fd 00 00 00 00 00 00
9264 19:26:45.121472 in-data:
9265 19:26:45.125162 [SSUSB] Setting up USB HOST controller...
9266 19:26:45.128235 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9267 19:26:45.131822 [SSUSB] phy power-on done.
9268 19:26:45.134973 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9269 19:26:45.141724 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9270 19:26:45.144817 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9271 19:26:45.151372 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9272 19:26:45.157931 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9273 19:26:45.164785 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9274 19:26:45.171517 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9275 19:26:45.178244 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9276 19:26:45.178408 SPM: binary array size = 0x9dc
9277 19:26:45.184815 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9278 19:26:45.191516 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9279 19:26:45.197976 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9280 19:26:45.201669 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9281 19:26:45.204986 configure_display: Starting display init
9282 19:26:45.241289 anx7625_power_on_init: Init interface.
9283 19:26:45.244991 anx7625_disable_pd_protocol: Disabled PD feature.
9284 19:26:45.248270 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9285 19:26:45.276001 anx7625_start_dp_work: Secure OCM version=00
9286 19:26:45.279166 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9287 19:26:45.294176 sp_tx_get_edid_block: EDID Block = 1
9288 19:26:45.396784 Extracted contents:
9289 19:26:45.399665 header: 00 ff ff ff ff ff ff 00
9290 19:26:45.403384 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9291 19:26:45.406531 version: 01 04
9292 19:26:45.410280 basic params: 95 1f 11 78 0a
9293 19:26:45.413492 chroma info: 76 90 94 55 54 90 27 21 50 54
9294 19:26:45.416408 established: 00 00 00
9295 19:26:45.419838 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9296 19:26:45.426463 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9297 19:26:45.432784 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9298 19:26:45.439868 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9299 19:26:45.446311 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9300 19:26:45.449516 extensions: 00
9301 19:26:45.449631 checksum: fb
9302 19:26:45.449749
9303 19:26:45.453312 Manufacturer: IVO Model 57d Serial Number 0
9304 19:26:45.456395 Made week 0 of 2020
9305 19:26:45.456493 EDID version: 1.4
9306 19:26:45.459589 Digital display
9307 19:26:45.463366 6 bits per primary color channel
9308 19:26:45.463473 DisplayPort interface
9309 19:26:45.466313 Maximum image size: 31 cm x 17 cm
9310 19:26:45.470110 Gamma: 220%
9311 19:26:45.470218 Check DPMS levels
9312 19:26:45.473186 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9313 19:26:45.476309 First detailed timing is preferred timing
9314 19:26:45.479516 Established timings supported:
9315 19:26:45.483097 Standard timings supported:
9316 19:26:45.483204 Detailed timings
9317 19:26:45.489561 Hex of detail: 383680a07038204018303c0035ae10000019
9318 19:26:45.493090 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9319 19:26:45.499680 0780 0798 07c8 0820 hborder 0
9320 19:26:45.503162 0438 043b 0447 0458 vborder 0
9321 19:26:45.503329 -hsync -vsync
9322 19:26:45.506305 Did detailed timing
9323 19:26:45.509519 Hex of detail: 000000000000000000000000000000000000
9324 19:26:45.512778 Manufacturer-specified data, tag 0
9325 19:26:45.519483 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9326 19:26:45.519598 ASCII string: InfoVision
9327 19:26:45.526016 Hex of detail: 000000fe00523134304e574635205248200a
9328 19:26:45.529518 ASCII string: R140NWF5 RH
9329 19:26:45.529602 Checksum
9330 19:26:45.529665 Checksum: 0xfb (valid)
9331 19:26:45.536545 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9332 19:26:45.539335 DSI data_rate: 832800000 bps
9333 19:26:45.542559 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9334 19:26:45.545824 anx7625_parse_edid: pixelclock(138800).
9335 19:26:45.552831 hactive(1920), hsync(48), hfp(24), hbp(88)
9336 19:26:45.556007 vactive(1080), vsync(12), vfp(3), vbp(17)
9337 19:26:45.559490 anx7625_dsi_config: config dsi.
9338 19:26:45.566023 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9339 19:26:45.578649 anx7625_dsi_config: success to config DSI
9340 19:26:45.581795 anx7625_dp_start: MIPI phy setup OK.
9341 19:26:45.584938 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9342 19:26:45.588527 mtk_ddp_mode_set invalid vrefresh 60
9343 19:26:45.592011 main_disp_path_setup
9344 19:26:45.592136 ovl_layer_smi_id_en
9345 19:26:45.595123 ovl_layer_smi_id_en
9346 19:26:45.595211 ccorr_config
9347 19:26:45.595280 aal_config
9348 19:26:45.598684 gamma_config
9349 19:26:45.598777 postmask_config
9350 19:26:45.601577 dither_config
9351 19:26:45.605142 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9352 19:26:45.611629 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9353 19:26:45.615347 Root Device init finished in 551 msecs
9354 19:26:45.615485 CPU_CLUSTER: 0 init
9355 19:26:45.624817 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9356 19:26:45.628907 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9357 19:26:45.631715 APU_MBOX 0x190000b0 = 0x10001
9358 19:26:45.635568 APU_MBOX 0x190001b0 = 0x10001
9359 19:26:45.638194 APU_MBOX 0x190005b0 = 0x10001
9360 19:26:45.641733 APU_MBOX 0x190006b0 = 0x10001
9361 19:26:45.644909 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9362 19:26:45.657627 read SPI 0x539f4 0xe237: 6249 us, 9267 KB/s, 74.136 Mbps
9363 19:26:45.670166 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9364 19:26:45.676996 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9365 19:26:45.688097 read SPI 0x61c74 0xe8ef: 6412 us, 9299 KB/s, 74.392 Mbps
9366 19:26:45.697249 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9367 19:26:45.700799 CPU_CLUSTER: 0 init finished in 81 msecs
9368 19:26:45.704112 Devices initialized
9369 19:26:45.707664 Show all devs... After init.
9370 19:26:45.707755 Root Device: enabled 1
9371 19:26:45.710789 CPU_CLUSTER: 0: enabled 1
9372 19:26:45.714302 CPU: 00: enabled 1
9373 19:26:45.717526 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9374 19:26:45.720615 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9375 19:26:45.724202 ELOG: NV offset 0x57f000 size 0x1000
9376 19:26:45.730529 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9377 19:26:45.737812 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9378 19:26:45.740801 ELOG: Event(17) added with size 13 at 2024-04-18 19:26:45 UTC
9379 19:26:45.744088 out: cmd=0x121: 03 db 21 01 00 00 00 00
9380 19:26:45.747639 in-header: 03 ee 00 00 2c 00 00 00
9381 19:26:45.761137 in-data: 71 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9382 19:26:45.767850 ELOG: Event(A1) added with size 10 at 2024-04-18 19:26:45 UTC
9383 19:26:45.774166 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9384 19:26:45.780742 ELOG: Event(A0) added with size 9 at 2024-04-18 19:26:45 UTC
9385 19:26:45.784669 elog_add_boot_reason: Logged dev mode boot
9386 19:26:45.787468 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9387 19:26:45.791435 Finalize devices...
9388 19:26:45.791623 Devices finalized
9389 19:26:45.797932 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9390 19:26:45.800903 Writing coreboot table at 0xffe64000
9391 19:26:45.804422 0. 000000000010a000-0000000000113fff: RAMSTAGE
9392 19:26:45.807548 1. 0000000040000000-00000000400fffff: RAM
9393 19:26:45.810830 2. 0000000040100000-000000004032afff: RAMSTAGE
9394 19:26:45.818207 3. 000000004032b000-00000000545fffff: RAM
9395 19:26:45.821153 4. 0000000054600000-000000005465ffff: BL31
9396 19:26:45.824280 5. 0000000054660000-00000000ffe63fff: RAM
9397 19:26:45.827427 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9398 19:26:45.834080 7. 0000000100000000-000000023fffffff: RAM
9399 19:26:45.834219 Passing 5 GPIOs to payload:
9400 19:26:45.841183 NAME | PORT | POLARITY | VALUE
9401 19:26:45.844327 EC in RW | 0x000000aa | low | undefined
9402 19:26:45.851339 EC interrupt | 0x00000005 | low | undefined
9403 19:26:45.854956 TPM interrupt | 0x000000ab | high | undefined
9404 19:26:45.857967 SD card detect | 0x00000011 | high | undefined
9405 19:26:45.864458 speaker enable | 0x00000093 | high | undefined
9406 19:26:45.868036 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9407 19:26:45.871072 in-header: 03 f9 00 00 02 00 00 00
9408 19:26:45.871158 in-data: 02 00
9409 19:26:45.874297 ADC[4]: Raw value=900590 ID=7
9410 19:26:45.877873 ADC[3]: Raw value=213336 ID=1
9411 19:26:45.877958 RAM Code: 0x71
9412 19:26:45.880896 ADC[6]: Raw value=74926 ID=0
9413 19:26:45.884306 ADC[5]: Raw value=212229 ID=1
9414 19:26:45.884405 SKU Code: 0x1
9415 19:26:45.890838 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 9485
9416 19:26:45.894561 coreboot table: 964 bytes.
9417 19:26:45.897409 IMD ROOT 0. 0xfffff000 0x00001000
9418 19:26:45.900678 IMD SMALL 1. 0xffffe000 0x00001000
9419 19:26:45.904374 RO MCACHE 2. 0xffffc000 0x00001104
9420 19:26:45.907470 CONSOLE 3. 0xfff7c000 0x00080000
9421 19:26:45.910517 FMAP 4. 0xfff7b000 0x00000452
9422 19:26:45.913909 TIME STAMP 5. 0xfff7a000 0x00000910
9423 19:26:45.917377 VBOOT WORK 6. 0xfff66000 0x00014000
9424 19:26:45.920561 RAMOOPS 7. 0xffe66000 0x00100000
9425 19:26:45.924176 COREBOOT 8. 0xffe64000 0x00002000
9426 19:26:45.924277 IMD small region:
9427 19:26:45.927325 IMD ROOT 0. 0xffffec00 0x00000400
9428 19:26:45.930439 VPD 1. 0xffffeb80 0x0000006c
9429 19:26:45.934117 MMC STATUS 2. 0xffffeb60 0x00000004
9430 19:26:45.940724 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9431 19:26:45.940850 Probing TPM: done!
9432 19:26:45.947472 Connected to device vid:did:rid of 1ae0:0028:00
9433 19:26:45.954079 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9434 19:26:45.957750 Initialized TPM device CR50 revision 0
9435 19:26:45.961741 Checking cr50 for pending updates
9436 19:26:45.967465 Reading cr50 TPM mode
9437 19:26:45.975616 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9438 19:26:45.982507 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9439 19:26:46.022520 read SPI 0x3990ec 0x4f1b0: 34859 us, 9295 KB/s, 74.360 Mbps
9440 19:26:46.025793 Checking segment from ROM address 0x40100000
9441 19:26:46.029143 Checking segment from ROM address 0x4010001c
9442 19:26:46.036127 Loading segment from ROM address 0x40100000
9443 19:26:46.036240 code (compression=0)
9444 19:26:46.043051 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9445 19:26:46.052748 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9446 19:26:46.052889 it's not compressed!
9447 19:26:46.060140 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9448 19:26:46.063131 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9449 19:26:46.083073 Loading segment from ROM address 0x4010001c
9450 19:26:46.083200 Entry Point 0x80000000
9451 19:26:46.086102 Loaded segments
9452 19:26:46.089798 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9453 19:26:46.096737 Jumping to boot code at 0x80000000(0xffe64000)
9454 19:26:46.103016 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9455 19:26:46.109588 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9456 19:26:46.117630 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9457 19:26:46.121004 Checking segment from ROM address 0x40100000
9458 19:26:46.124277 Checking segment from ROM address 0x4010001c
9459 19:26:46.130924 Loading segment from ROM address 0x40100000
9460 19:26:46.131010 code (compression=1)
9461 19:26:46.137663 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9462 19:26:46.147894 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9463 19:26:46.147986 using LZMA
9464 19:26:46.155619 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9465 19:26:46.162531 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9466 19:26:46.165890 Loading segment from ROM address 0x4010001c
9467 19:26:46.165977 Entry Point 0x54601000
9468 19:26:46.169416 Loaded segments
9469 19:26:46.172273 NOTICE: MT8192 bl31_setup
9470 19:26:46.179246 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9471 19:26:46.182624 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9472 19:26:46.186055 WARNING: region 0:
9473 19:26:46.189448 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9474 19:26:46.189538 WARNING: region 1:
9475 19:26:46.196174 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9476 19:26:46.199924 WARNING: region 2:
9477 19:26:46.203078 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9478 19:26:46.205936 WARNING: region 3:
9479 19:26:46.209540 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9480 19:26:46.213103 WARNING: region 4:
9481 19:26:46.216065 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9482 19:26:46.219589 WARNING: region 5:
9483 19:26:46.223271 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9484 19:26:46.226394 WARNING: region 6:
9485 19:26:46.229879 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9486 19:26:46.229966 WARNING: region 7:
9487 19:26:46.236525 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9488 19:26:46.243233 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9489 19:26:46.246522 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9490 19:26:46.249985 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9491 19:26:46.252990 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9492 19:26:46.259748 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9493 19:26:46.263280 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9494 19:26:46.269832 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9495 19:26:46.273653 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9496 19:26:46.276777 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9497 19:26:46.283363 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9498 19:26:46.287014 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9499 19:26:46.290401 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9500 19:26:46.297022 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9501 19:26:46.300038 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9502 19:26:46.303752 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9503 19:26:46.310490 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9504 19:26:46.313528 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9505 19:26:46.320418 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9506 19:26:46.323816 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9507 19:26:46.326736 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9508 19:26:46.334154 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9509 19:26:46.337166 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9510 19:26:46.340703 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9511 19:26:46.346941 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9512 19:26:46.350302 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9513 19:26:46.357137 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9514 19:26:46.360617 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9515 19:26:46.363954 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9516 19:26:46.370693 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9517 19:26:46.373697 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9518 19:26:46.380450 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9519 19:26:46.383799 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9520 19:26:46.387646 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9521 19:26:46.390593 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9522 19:26:46.397525 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9523 19:26:46.400834 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9524 19:26:46.403979 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9525 19:26:46.407436 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9526 19:26:46.414118 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9527 19:26:46.417170 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9528 19:26:46.420991 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9529 19:26:46.423909 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9530 19:26:46.430968 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9531 19:26:46.434116 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9532 19:26:46.437106 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9533 19:26:46.441004 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9534 19:26:46.447327 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9535 19:26:46.450578 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9536 19:26:46.454315 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9537 19:26:46.466928 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9538 19:26:46.467109 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9539 19:26:46.471236 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9540 19:26:46.474358 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9541 19:26:46.477695 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9542 19:26:46.484464 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9543 19:26:46.487499 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9544 19:26:46.494525 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9545 19:26:46.497730 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9546 19:26:46.501416 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9547 19:26:46.508106 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9548 19:26:46.510913 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9549 19:26:46.517918 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9550 19:26:46.520901 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9551 19:26:46.527819 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9552 19:26:46.531216 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9553 19:26:46.537553 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9554 19:26:46.541012 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9555 19:26:46.544608 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9556 19:26:46.550922 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9557 19:26:46.554393 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9558 19:26:46.561541 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9559 19:26:46.564739 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9560 19:26:46.567828 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9561 19:26:46.574651 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9562 19:26:46.578272 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9563 19:26:46.585107 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9564 19:26:46.588100 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9565 19:26:46.594485 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9566 19:26:46.598064 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9567 19:26:46.604849 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9568 19:26:46.608551 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9569 19:26:46.611390 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9570 19:26:46.618377 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9571 19:26:46.621957 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9572 19:26:46.628617 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9573 19:26:46.631634 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9574 19:26:46.635237 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9575 19:26:46.641817 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9576 19:26:46.645146 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9577 19:26:46.651707 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9578 19:26:46.654870 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9579 19:26:46.662051 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9580 19:26:46.664942 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9581 19:26:46.668594 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9582 19:26:46.675524 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9583 19:26:46.678664 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9584 19:26:46.681778 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9585 19:26:46.689066 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9586 19:26:46.692445 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9587 19:26:46.695292 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9588 19:26:46.699178 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9589 19:26:46.705522 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9590 19:26:46.708698 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9591 19:26:46.715574 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9592 19:26:46.718530 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9593 19:26:46.722216 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9594 19:26:46.728849 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9595 19:26:46.731887 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9596 19:26:46.738886 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9597 19:26:46.741957 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9598 19:26:46.745552 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9599 19:26:46.752040 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9600 19:26:46.755648 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9601 19:26:46.762446 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9602 19:26:46.765078 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9603 19:26:46.768895 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9604 19:26:46.775513 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9605 19:26:46.778880 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9606 19:26:46.782329 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9607 19:26:46.785359 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9608 19:26:46.792007 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9609 19:26:46.795613 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9610 19:26:46.798716 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9611 19:26:46.802072 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9612 19:26:46.809170 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9613 19:26:46.812240 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9614 19:26:46.818703 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9615 19:26:46.822650 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9616 19:26:46.825528 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9617 19:26:46.832293 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9618 19:26:46.835950 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9619 19:26:46.839273 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9620 19:26:46.845977 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9621 19:26:46.849763 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9622 19:26:46.856228 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9623 19:26:46.859524 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9624 19:26:46.862374 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9625 19:26:46.868974 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9626 19:26:46.872697 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9627 19:26:46.875852 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9628 19:26:46.882731 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9629 19:26:46.886257 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9630 19:26:46.892527 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9631 19:26:46.896223 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9632 19:26:46.899159 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9633 19:26:46.906536 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9634 19:26:46.909343 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9635 19:26:46.916055 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9636 19:26:46.919344 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9637 19:26:46.922674 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9638 19:26:46.929181 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9639 19:26:46.932526 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9640 19:26:46.936317 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9641 19:26:46.942888 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9642 19:26:46.946244 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9643 19:26:46.952616 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9644 19:26:46.956335 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9645 19:26:46.959911 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9646 19:26:46.966162 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9647 19:26:46.969661 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9648 19:26:46.976389 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9649 19:26:46.979394 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9650 19:26:46.982515 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9651 19:26:46.989574 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9652 19:26:46.992791 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9653 19:26:46.996154 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9654 19:26:47.002948 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9655 19:26:47.006881 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9656 19:26:47.013713 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9657 19:26:47.016268 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9658 19:26:47.019853 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9659 19:26:47.026642 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9660 19:26:47.029817 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9661 19:26:47.033533 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9662 19:26:47.040162 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9663 19:26:47.043369 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9664 19:26:47.049739 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9665 19:26:47.053495 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9666 19:26:47.056236 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9667 19:26:47.062853 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9668 19:26:47.066327 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9669 19:26:47.072934 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9670 19:26:47.076138 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9671 19:26:47.079780 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9672 19:26:47.086661 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9673 19:26:47.089630 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9674 19:26:47.096161 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9675 19:26:47.099070 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9676 19:26:47.102230 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9677 19:26:47.109079 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9678 19:26:47.112314 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9679 19:26:47.119493 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9680 19:26:47.122376 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9681 19:26:47.128953 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9682 19:26:47.131939 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9683 19:26:47.135321 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9684 19:26:47.141937 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9685 19:26:47.145719 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9686 19:26:47.151959 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9687 19:26:47.155503 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9688 19:26:47.159085 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9689 19:26:47.165573 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9690 19:26:47.168923 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9691 19:26:47.175317 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9692 19:26:47.178891 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9693 19:26:47.185342 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9694 19:26:47.188704 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9695 19:26:47.191799 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9696 19:26:47.198961 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9697 19:26:47.202011 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9698 19:26:47.208642 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9699 19:26:47.212408 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9700 19:26:47.215560 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9701 19:26:47.222277 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9702 19:26:47.225181 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9703 19:26:47.232204 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9704 19:26:47.235353 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9705 19:26:47.238918 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9706 19:26:47.245186 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9707 19:26:47.248855 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9708 19:26:47.255218 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9709 19:26:47.258697 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9710 19:26:47.262228 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9711 19:26:47.268915 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9712 19:26:47.272335 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9713 19:26:47.278908 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9714 19:26:47.282051 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9715 19:26:47.288801 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9716 19:26:47.292226 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9717 19:26:47.295561 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9718 19:26:47.298747 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9719 19:26:47.305176 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9720 19:26:47.308790 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9721 19:26:47.311917 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9722 19:26:47.315481 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9723 19:26:47.322011 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9724 19:26:47.325111 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9725 19:26:47.331730 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9726 19:26:47.335344 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9727 19:26:47.338802 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9728 19:26:47.345467 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9729 19:26:47.348932 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9730 19:26:47.351769 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9731 19:26:47.358614 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9732 19:26:47.362272 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9733 19:26:47.365381 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9734 19:26:47.372361 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9735 19:26:47.375438 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9736 19:26:47.378922 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9737 19:26:47.385157 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9738 19:26:47.388529 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9739 19:26:47.395865 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9740 19:26:47.398793 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9741 19:26:47.402232 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9742 19:26:47.408519 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9743 19:26:47.411964 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9744 19:26:47.415976 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9745 19:26:47.422517 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9746 19:26:47.425472 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9747 19:26:47.428845 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9748 19:26:47.435905 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9749 19:26:47.438833 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9750 19:26:47.445239 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9751 19:26:47.448827 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9752 19:26:47.452658 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9753 19:26:47.459150 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9754 19:26:47.462337 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9755 19:26:47.465314 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9756 19:26:47.472317 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9757 19:26:47.475608 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9758 19:26:47.478933 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9759 19:26:47.482077 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9760 19:26:47.485562 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9761 19:26:47.491950 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9762 19:26:47.495585 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9763 19:26:47.498732 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9764 19:26:47.502464 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9765 19:26:47.508713 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9766 19:26:47.512007 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9767 19:26:47.515271 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9768 19:26:47.519131 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9769 19:26:47.525499 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9770 19:26:47.528697 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9771 19:26:47.535692 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9772 19:26:47.538866 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9773 19:26:47.542112 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9774 19:26:47.548672 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9775 19:26:47.552491 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9776 19:26:47.558813 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9777 19:26:47.562356 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9778 19:26:47.565430 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9779 19:26:47.572234 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9780 19:26:47.576030 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9781 19:26:47.582581 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9782 19:26:47.585905 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9783 19:26:47.589060 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9784 19:26:47.595634 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9785 19:26:47.599028 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9786 19:26:47.605636 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9787 19:26:47.608783 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9788 19:26:47.612341 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9789 19:26:47.618975 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9790 19:26:47.622534 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9791 19:26:47.628866 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9792 19:26:47.632258 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9793 19:26:47.635409 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9794 19:26:47.642545 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9795 19:26:47.645173 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9796 19:26:47.651919 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9797 19:26:47.655286 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9798 19:26:47.662140 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9799 19:26:47.665785 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9800 19:26:47.668559 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9801 19:26:47.675201 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9802 19:26:47.678927 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9803 19:26:47.681948 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9804 19:26:47.688861 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9805 19:26:47.691939 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9806 19:26:47.698505 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9807 19:26:47.701985 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9808 19:26:47.708720 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9809 19:26:47.711973 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9810 19:26:47.715560 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9811 19:26:47.721790 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9812 19:26:47.725532 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9813 19:26:47.732148 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9814 19:26:47.735662 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9815 19:26:47.738455 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9816 19:26:47.745510 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9817 19:26:47.748569 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9818 19:26:47.755396 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9819 19:26:47.758849 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9820 19:26:47.762199 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9821 19:26:47.769246 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9822 19:26:47.772158 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9823 19:26:47.779009 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9824 19:26:47.781984 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9825 19:26:47.785766 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9826 19:26:47.792529 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9827 19:26:47.795494 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9828 19:26:47.799153 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9829 19:26:47.805806 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9830 19:26:47.809109 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9831 19:26:47.815683 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9832 19:26:47.819147 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9833 19:26:47.822404 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9834 19:26:47.829124 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9835 19:26:47.832128 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9836 19:26:47.839290 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9837 19:26:47.842196 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9838 19:26:47.849132 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9839 19:26:47.852106 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9840 19:26:47.855843 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9841 19:26:47.862586 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9842 19:26:47.865574 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9843 19:26:47.872384 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9844 19:26:47.875787 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9845 19:26:47.879284 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9846 19:26:47.885624 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9847 19:26:47.889174 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9848 19:26:47.895866 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9849 19:26:47.898935 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9850 19:26:47.905788 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9851 19:26:47.909224 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9852 19:26:47.912329 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9853 19:26:47.919197 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9854 19:26:47.922876 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9855 19:26:47.929327 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9856 19:26:47.932509 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9857 19:26:47.936271 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9858 19:26:47.942697 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9859 19:26:47.945824 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9860 19:26:47.952530 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9861 19:26:47.956188 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9862 19:26:47.962651 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9863 19:26:47.966368 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9864 19:26:47.972893 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9865 19:26:47.976207 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9866 19:26:47.979435 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9867 19:26:47.986229 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9868 19:26:47.989393 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9869 19:26:47.996008 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9870 19:26:47.999560 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9871 19:26:48.005724 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9872 19:26:48.009324 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9873 19:26:48.013049 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9874 19:26:48.019084 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9875 19:26:48.023004 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9876 19:26:48.029300 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9877 19:26:48.032929 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9878 19:26:48.035943 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9879 19:26:48.042544 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9880 19:26:48.045801 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9881 19:26:48.052610 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9882 19:26:48.056398 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9883 19:26:48.062886 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9884 19:26:48.066025 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9885 19:26:48.069620 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9886 19:26:48.076244 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9887 19:26:48.079244 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9888 19:26:48.086564 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9889 19:26:48.089441 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9890 19:26:48.092467 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9891 19:26:48.099501 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9892 19:26:48.102957 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9893 19:26:48.109644 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9894 19:26:48.112596 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9895 19:26:48.119326 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9896 19:26:48.122911 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9897 19:26:48.129606 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9898 19:26:48.133183 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9899 19:26:48.139606 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9900 19:26:48.142614 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9901 19:26:48.149247 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9902 19:26:48.152810 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9903 19:26:48.159664 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9904 19:26:48.163039 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9905 19:26:48.165985 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9906 19:26:48.172988 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9907 19:26:48.176465 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9908 19:26:48.182821 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9909 19:26:48.186371 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9910 19:26:48.193649 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9911 19:26:48.196529 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9912 19:26:48.203499 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9913 19:26:48.206725 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9914 19:26:48.213662 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9915 19:26:48.216661 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9916 19:26:48.223527 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9917 19:26:48.227040 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9918 19:26:48.233631 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9919 19:26:48.236768 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9920 19:26:48.243508 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9921 19:26:48.246447 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9922 19:26:48.249996 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9923 19:26:48.253508 INFO: [APUAPC] vio 0
9924 19:26:48.260274 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9925 19:26:48.263044 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9926 19:26:48.266685 INFO: [APUAPC] D0_APC_0: 0x400510
9927 19:26:48.269675 INFO: [APUAPC] D0_APC_1: 0x0
9928 19:26:48.273101 INFO: [APUAPC] D0_APC_2: 0x1540
9929 19:26:48.276139 INFO: [APUAPC] D0_APC_3: 0x0
9930 19:26:48.280085 INFO: [APUAPC] D1_APC_0: 0xffffffff
9931 19:26:48.283087 INFO: [APUAPC] D1_APC_1: 0xffffffff
9932 19:26:48.286861 INFO: [APUAPC] D1_APC_2: 0x3fffff
9933 19:26:48.289687 INFO: [APUAPC] D1_APC_3: 0x0
9934 19:26:48.292791 INFO: [APUAPC] D2_APC_0: 0xffffffff
9935 19:26:48.296154 INFO: [APUAPC] D2_APC_1: 0xffffffff
9936 19:26:48.299881 INFO: [APUAPC] D2_APC_2: 0x3fffff
9937 19:26:48.299986 INFO: [APUAPC] D2_APC_3: 0x0
9938 19:26:48.303336 INFO: [APUAPC] D3_APC_0: 0xffffffff
9939 19:26:48.309478 INFO: [APUAPC] D3_APC_1: 0xffffffff
9940 19:26:48.309604 INFO: [APUAPC] D3_APC_2: 0x3fffff
9941 19:26:48.313011 INFO: [APUAPC] D3_APC_3: 0x0
9942 19:26:48.316618 INFO: [APUAPC] D4_APC_0: 0xffffffff
9943 19:26:48.319761 INFO: [APUAPC] D4_APC_1: 0xffffffff
9944 19:26:48.323278 INFO: [APUAPC] D4_APC_2: 0x3fffff
9945 19:26:48.326348 INFO: [APUAPC] D4_APC_3: 0x0
9946 19:26:48.329959 INFO: [APUAPC] D5_APC_0: 0xffffffff
9947 19:26:48.333086 INFO: [APUAPC] D5_APC_1: 0xffffffff
9948 19:26:48.336655 INFO: [APUAPC] D5_APC_2: 0x3fffff
9949 19:26:48.339632 INFO: [APUAPC] D5_APC_3: 0x0
9950 19:26:48.343215 INFO: [APUAPC] D6_APC_0: 0xffffffff
9951 19:26:48.346372 INFO: [APUAPC] D6_APC_1: 0xffffffff
9952 19:26:48.349884 INFO: [APUAPC] D6_APC_2: 0x3fffff
9953 19:26:48.353446 INFO: [APUAPC] D6_APC_3: 0x0
9954 19:26:48.356493 INFO: [APUAPC] D7_APC_0: 0xffffffff
9955 19:26:48.359607 INFO: [APUAPC] D7_APC_1: 0xffffffff
9956 19:26:48.362839 INFO: [APUAPC] D7_APC_2: 0x3fffff
9957 19:26:48.366607 INFO: [APUAPC] D7_APC_3: 0x0
9958 19:26:48.369966 INFO: [APUAPC] D8_APC_0: 0xffffffff
9959 19:26:48.373042 INFO: [APUAPC] D8_APC_1: 0xffffffff
9960 19:26:48.376454 INFO: [APUAPC] D8_APC_2: 0x3fffff
9961 19:26:48.379689 INFO: [APUAPC] D8_APC_3: 0x0
9962 19:26:48.383343 INFO: [APUAPC] D9_APC_0: 0xffffffff
9963 19:26:48.386183 INFO: [APUAPC] D9_APC_1: 0xffffffff
9964 19:26:48.389542 INFO: [APUAPC] D9_APC_2: 0x3fffff
9965 19:26:48.393223 INFO: [APUAPC] D9_APC_3: 0x0
9966 19:26:48.396045 INFO: [APUAPC] D10_APC_0: 0xffffffff
9967 19:26:48.399245 INFO: [APUAPC] D10_APC_1: 0xffffffff
9968 19:26:48.402740 INFO: [APUAPC] D10_APC_2: 0x3fffff
9969 19:26:48.406152 INFO: [APUAPC] D10_APC_3: 0x0
9970 19:26:48.409512 INFO: [APUAPC] D11_APC_0: 0xffffffff
9971 19:26:48.412850 INFO: [APUAPC] D11_APC_1: 0xffffffff
9972 19:26:48.416262 INFO: [APUAPC] D11_APC_2: 0x3fffff
9973 19:26:48.419563 INFO: [APUAPC] D11_APC_3: 0x0
9974 19:26:48.422573 INFO: [APUAPC] D12_APC_0: 0xffffffff
9975 19:26:48.426062 INFO: [APUAPC] D12_APC_1: 0xffffffff
9976 19:26:48.429700 INFO: [APUAPC] D12_APC_2: 0x3fffff
9977 19:26:48.432494 INFO: [APUAPC] D12_APC_3: 0x0
9978 19:26:48.436063 INFO: [APUAPC] D13_APC_0: 0xffffffff
9979 19:26:48.439485 INFO: [APUAPC] D13_APC_1: 0xffffffff
9980 19:26:48.443406 INFO: [APUAPC] D13_APC_2: 0x3fffff
9981 19:26:48.446278 INFO: [APUAPC] D13_APC_3: 0x0
9982 19:26:48.449624 INFO: [APUAPC] D14_APC_0: 0xffffffff
9983 19:26:48.453333 INFO: [APUAPC] D14_APC_1: 0xffffffff
9984 19:26:48.456269 INFO: [APUAPC] D14_APC_2: 0x3fffff
9985 19:26:48.459889 INFO: [APUAPC] D14_APC_3: 0x0
9986 19:26:48.462924 INFO: [APUAPC] D15_APC_0: 0xffffffff
9987 19:26:48.466217 INFO: [APUAPC] D15_APC_1: 0xffffffff
9988 19:26:48.469674 INFO: [APUAPC] D15_APC_2: 0x3fffff
9989 19:26:48.472914 INFO: [APUAPC] D15_APC_3: 0x0
9990 19:26:48.476222 INFO: [APUAPC] APC_CON: 0x4
9991 19:26:48.479854 INFO: [NOCDAPC] D0_APC_0: 0x0
9992 19:26:48.482684 INFO: [NOCDAPC] D0_APC_1: 0x0
9993 19:26:48.482878 INFO: [NOCDAPC] D1_APC_0: 0x0
9994 19:26:48.486413 INFO: [NOCDAPC] D1_APC_1: 0xfff
9995 19:26:48.489684 INFO: [NOCDAPC] D2_APC_0: 0x0
9996 19:26:48.492759 INFO: [NOCDAPC] D2_APC_1: 0xfff
9997 19:26:48.495938 INFO: [NOCDAPC] D3_APC_0: 0x0
9998 19:26:48.499436 INFO: [NOCDAPC] D3_APC_1: 0xfff
9999 19:26:48.502872 INFO: [NOCDAPC] D4_APC_0: 0x0
10000 19:26:48.505883 INFO: [NOCDAPC] D4_APC_1: 0xfff
10001 19:26:48.509427 INFO: [NOCDAPC] D5_APC_0: 0x0
10002 19:26:48.512845 INFO: [NOCDAPC] D5_APC_1: 0xfff
10003 19:26:48.512959 INFO: [NOCDAPC] D6_APC_0: 0x0
10004 19:26:48.516221 INFO: [NOCDAPC] D6_APC_1: 0xfff
10005 19:26:48.519229 INFO: [NOCDAPC] D7_APC_0: 0x0
10006 19:26:48.522406 INFO: [NOCDAPC] D7_APC_1: 0xfff
10007 19:26:48.525749 INFO: [NOCDAPC] D8_APC_0: 0x0
10008 19:26:48.528987 INFO: [NOCDAPC] D8_APC_1: 0xfff
10009 19:26:48.532411 INFO: [NOCDAPC] D9_APC_0: 0x0
10010 19:26:48.535675 INFO: [NOCDAPC] D9_APC_1: 0xfff
10011 19:26:48.539292 INFO: [NOCDAPC] D10_APC_0: 0x0
10012 19:26:48.542784 INFO: [NOCDAPC] D10_APC_1: 0xfff
10013 19:26:48.545827 INFO: [NOCDAPC] D11_APC_0: 0x0
10014 19:26:48.549563 INFO: [NOCDAPC] D11_APC_1: 0xfff
10015 19:26:48.549675 INFO: [NOCDAPC] D12_APC_0: 0x0
10016 19:26:48.552707 INFO: [NOCDAPC] D12_APC_1: 0xfff
10017 19:26:48.555874 INFO: [NOCDAPC] D13_APC_0: 0x0
10018 19:26:48.559476 INFO: [NOCDAPC] D13_APC_1: 0xfff
10019 19:26:48.562581 INFO: [NOCDAPC] D14_APC_0: 0x0
10020 19:26:48.565652 INFO: [NOCDAPC] D14_APC_1: 0xfff
10021 19:26:48.569175 INFO: [NOCDAPC] D15_APC_0: 0x0
10022 19:26:48.572735 INFO: [NOCDAPC] D15_APC_1: 0xfff
10023 19:26:48.575983 INFO: [NOCDAPC] APC_CON: 0x4
10024 19:26:48.579526 INFO: [APUAPC] set_apusys_apc done
10025 19:26:48.582484 INFO: [DEVAPC] devapc_init done
10026 19:26:48.585958 INFO: GICv3 without legacy support detected.
10027 19:26:48.588796 INFO: ARM GICv3 driver initialized in EL3
10028 19:26:48.592813 INFO: Maximum SPI INTID supported: 639
10029 19:26:48.598812 INFO: BL31: Initializing runtime services
10030 19:26:48.602205 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10031 19:26:48.605641 INFO: SPM: enable CPC mode
10032 19:26:48.612332 INFO: mcdi ready for mcusys-off-idle and system suspend
10033 19:26:48.615938 INFO: BL31: Preparing for EL3 exit to normal world
10034 19:26:48.618892 INFO: Entry point address = 0x80000000
10035 19:26:48.622384 INFO: SPSR = 0x8
10036 19:26:48.627658
10037 19:26:48.627756
10038 19:26:48.627843
10039 19:26:48.631014 Starting depthcharge on Spherion...
10040 19:26:48.631121
10041 19:26:48.631212 Wipe memory regions:
10042 19:26:48.631290
10043 19:26:48.632093 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10044 19:26:48.632243 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10045 19:26:48.632335 Setting prompt string to ['asurada:']
10046 19:26:48.632452 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10047 19:26:48.633750 [0x00000040000000, 0x00000054600000)
10048 19:26:48.756813
10049 19:26:48.756959 [0x00000054660000, 0x00000080000000)
10050 19:26:49.017062
10051 19:26:49.017255 [0x000000821a7280, 0x000000ffe64000)
10052 19:26:49.762124
10053 19:26:49.762304 [0x00000100000000, 0x00000240000000)
10054 19:26:51.652693
10055 19:26:51.655658 Initializing XHCI USB controller at 0x11200000.
10056 19:26:52.693348
10057 19:26:52.696576 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10058 19:26:52.696680
10059 19:26:52.696760
10060 19:26:52.696854
10061 19:26:52.697180 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10063 19:26:52.797720 asurada: tftpboot 192.168.201.1 13420397/tftp-deploy-49036zue/kernel/image.itb 13420397/tftp-deploy-49036zue/kernel/cmdline
10064 19:26:52.797960 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10065 19:26:52.798167 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10066 19:26:52.802172 tftpboot 192.168.201.1 13420397/tftp-deploy-49036zue/kernel/image.ittp-deploy-49036zue/kernel/cmdline
10067 19:26:52.802292
10068 19:26:52.802383 Waiting for link
10069 19:26:52.962672
10070 19:26:52.962893 R8152: Initializing
10071 19:26:52.963016
10072 19:26:52.965895 Version 6 (ocp_data = 5c30)
10073 19:26:52.966041
10074 19:26:52.969636 R8152: Done initializing
10075 19:26:52.969781
10076 19:26:52.969895 Adding net device
10077 19:26:54.883281
10078 19:26:54.883897 done.
10079 19:26:54.884310
10080 19:26:54.884684 MAC: 00:24:32:30:78:52
10081 19:26:54.885051
10082 19:26:54.886150 Sending DHCP discover... done.
10083 19:26:54.886526
10084 19:26:54.889505 Waiting for reply... done.
10085 19:26:54.889921
10086 19:26:54.892577 Sending DHCP request... done.
10087 19:26:54.892968
10088 19:26:59.043498 Waiting for reply... done.
10089 19:26:59.043668
10090 19:26:59.043779 My ip is 192.168.201.14
10091 19:26:59.043875
10092 19:26:59.047068 The DHCP server ip is 192.168.201.1
10093 19:26:59.047184
10094 19:26:59.054070 TFTP server IP predefined by user: 192.168.201.1
10095 19:26:59.054178
10096 19:26:59.060353 Bootfile predefined by user: 13420397/tftp-deploy-49036zue/kernel/image.itb
10097 19:26:59.060440
10098 19:26:59.060511 Sending tftp read request... done.
10099 19:26:59.063578
10100 19:26:59.067475 Waiting for the transfer...
10101 19:26:59.067597
10102 19:26:59.616666 00000000 ################################################################
10103 19:26:59.616838
10104 19:27:00.175870 00080000 ################################################################
10105 19:27:00.176050
10106 19:27:00.753184 00100000 ################################################################
10107 19:27:00.753370
10108 19:27:01.321901 00180000 ################################################################
10109 19:27:01.322180
10110 19:27:01.876270 00200000 ################################################################
10111 19:27:01.876422
10112 19:27:02.434277 00280000 ################################################################
10113 19:27:02.434431
10114 19:27:03.009616 00300000 ################################################################
10115 19:27:03.010222
10116 19:27:03.619810 00380000 ################################################################
10117 19:27:03.620695
10118 19:27:04.201540 00400000 ################################################################
10119 19:27:04.201679
10120 19:27:04.818634 00480000 ################################################################
10121 19:27:04.818789
10122 19:27:05.347753 00500000 ################################################################
10123 19:27:05.347905
10124 19:27:05.880523 00580000 ################################################################
10125 19:27:05.880693
10126 19:27:06.414217 00600000 ################################################################
10127 19:27:06.414353
10128 19:27:06.948563 00680000 ################################################################
10129 19:27:06.948701
10130 19:27:07.511389 00700000 ################################################################
10131 19:27:07.512061
10132 19:27:08.127852 00780000 ################################################################
10133 19:27:08.128434
10134 19:27:08.714506 00800000 ################################################################
10135 19:27:08.714695
10136 19:27:09.332840 00880000 ################################################################
10137 19:27:09.333588
10138 19:27:09.931047 00900000 ################################################################
10139 19:27:09.931183
10140 19:27:10.486788 00980000 ################################################################
10141 19:27:10.486949
10142 19:27:11.036321 00a00000 ################################################################
10143 19:27:11.036453
10144 19:27:11.565847 00a80000 ################################################################
10145 19:27:11.565979
10146 19:27:12.110938 00b00000 ################################################################
10147 19:27:12.111071
10148 19:27:12.663775 00b80000 ################################################################
10149 19:27:12.663911
10150 19:27:13.260519 00c00000 ################################################################
10151 19:27:13.261021
10152 19:27:13.898893 00c80000 ################################################################
10153 19:27:13.899397
10154 19:27:14.521696 00d00000 ################################################################
10155 19:27:14.521829
10156 19:27:15.128297 00d80000 ################################################################
10157 19:27:15.128427
10158 19:27:15.659653 00e00000 ################################################################
10159 19:27:15.659784
10160 19:27:16.197065 00e80000 ################################################################
10161 19:27:16.197199
10162 19:27:16.744305 00f00000 ################################################################
10163 19:27:16.744463
10164 19:27:17.298123 00f80000 ################################################################
10165 19:27:17.298255
10166 19:27:17.838376 01000000 ################################################################
10167 19:27:17.838548
10168 19:27:18.375220 01080000 ################################################################
10169 19:27:18.375357
10170 19:27:18.896743 01100000 ################################################################
10171 19:27:18.896917
10172 19:27:19.416283 01180000 ################################################################
10173 19:27:19.416486
10174 19:27:19.944597 01200000 ################################################################
10175 19:27:19.944826
10176 19:27:20.470426 01280000 ################################################################
10177 19:27:20.470588
10178 19:27:20.990081 01300000 ################################################################
10179 19:27:20.990248
10180 19:27:21.514094 01380000 ################################################################
10181 19:27:21.514266
10182 19:27:22.036943 01400000 ################################################################
10183 19:27:22.037119
10184 19:27:22.562077 01480000 ################################################################
10185 19:27:22.562233
10186 19:27:23.103960 01500000 ################################################################
10187 19:27:23.104095
10188 19:27:23.641033 01580000 ################################################################
10189 19:27:23.641199
10190 19:27:24.189785 01600000 ################################################################
10191 19:27:24.189937
10192 19:27:24.728660 01680000 ################################################################
10193 19:27:24.728801
10194 19:27:25.276014 01700000 ################################################################
10195 19:27:25.276185
10196 19:27:25.839335 01780000 ################################################################
10197 19:27:25.839483
10198 19:27:26.359756 01800000 ################################################################
10199 19:27:26.359924
10200 19:27:26.891411 01880000 ################################################################
10201 19:27:26.891577
10202 19:27:27.432250 01900000 ################################################################
10203 19:27:27.432385
10204 19:27:27.997418 01980000 ################################################################
10205 19:27:27.997593
10206 19:27:28.555426 01a00000 ################################################################
10207 19:27:28.555578
10208 19:27:29.112489 01a80000 ################################################################
10209 19:27:29.112635
10210 19:27:29.674376 01b00000 ################################################################
10211 19:27:29.674521
10212 19:27:30.239152 01b80000 ################################################################
10213 19:27:30.239298
10214 19:27:30.802587 01c00000 ################################################################
10215 19:27:30.802733
10216 19:27:31.366206 01c80000 ################################################################
10217 19:27:31.366721
10218 19:27:31.929395 01d00000 ################################################################
10219 19:27:31.929525
10220 19:27:32.463402 01d80000 ################################################################
10221 19:27:32.463562
10222 19:27:33.042578 01e00000 ################################################################
10223 19:27:33.043144
10224 19:27:33.681271 01e80000 ################################################################
10225 19:27:33.681910
10226 19:27:34.245933 01f00000 ################################################################
10227 19:27:34.246068
10228 19:27:34.794760 01f80000 ################################################################
10229 19:27:34.794966
10230 19:27:35.414473 02000000 ################################################################
10231 19:27:35.415140
10232 19:27:36.036201 02080000 ################################################################
10233 19:27:36.036725
10234 19:27:36.955090 02100000 ################################################################
10235 19:27:36.955711
10236 19:27:37.251572 02180000 ################################################################
10237 19:27:37.252250
10238 19:27:37.888674 02200000 ################################################################
10239 19:27:37.889447
10240 19:27:38.598021 02280000 ################################################################
10241 19:27:38.598547
10242 19:27:39.117578 02300000 ################################################################
10243 19:27:39.117715
10244 19:27:39.711205 02380000 ################################################################
10245 19:27:39.711336
10246 19:27:40.299139 02400000 ################################################################
10247 19:27:40.299646
10248 19:27:40.929943 02480000 ################################################################
10249 19:27:40.930580
10250 19:27:41.534947 02500000 ################################################################
10251 19:27:41.535489
10252 19:27:42.093973 02580000 ################################################################
10253 19:27:42.094111
10254 19:27:42.648139 02600000 ################################################################
10255 19:27:42.648282
10256 19:27:43.228510 02680000 ################################################################
10257 19:27:43.229064
10258 19:27:43.831260 02700000 ################################################################
10259 19:27:43.831405
10260 19:27:44.382321 02780000 ################################################################
10261 19:27:44.382464
10262 19:27:44.932995 02800000 ################################################################
10263 19:27:44.933132
10264 19:27:45.534715 02880000 ################################################################
10265 19:27:45.534913
10266 19:27:46.162378 02900000 ################################################################
10267 19:27:46.162542
10268 19:27:46.707494 02980000 ################################################################
10269 19:27:46.707644
10270 19:27:47.300505 02a00000 ################################################################
10271 19:27:47.300660
10272 19:27:47.917305 02a80000 ################################################################
10273 19:27:47.917875
10274 19:27:48.531956 02b00000 ################################################################
10275 19:27:48.532652
10276 19:27:49.135865 02b80000 ################################################################
10277 19:27:49.136039
10278 19:27:49.700074 02c00000 ################################################################
10279 19:27:49.700241
10280 19:27:50.293464 02c80000 ################################################################
10281 19:27:50.293626
10282 19:27:50.886611 02d00000 ################################################################
10283 19:27:50.886760
10284 19:27:51.600696 02d80000 ################################################################
10285 19:27:51.601237
10286 19:27:52.143340 02e00000 ################################################################
10287 19:27:52.143524
10288 19:27:52.773500 02e80000 ################################################################
10289 19:27:52.774167
10290 19:27:53.372180 02f00000 ################################################################
10291 19:27:53.372913
10292 19:27:54.014706 02f80000 ################################################################
10293 19:27:54.015255
10294 19:27:54.609036 03000000 ################################################################
10295 19:27:54.609259
10296 19:27:55.163165 03080000 ################################################################
10297 19:27:55.163423
10298 19:27:55.722238 03100000 ################################################################
10299 19:27:55.722396
10300 19:27:56.338752 03180000 ################################################################
10301 19:27:56.338986
10302 19:27:56.939041 03200000 ################################################################
10303 19:27:56.939291
10304 19:27:57.502686 03280000 ################################################################
10305 19:27:57.502829
10306 19:27:58.056955 03300000 ################################################################
10307 19:27:58.057104
10308 19:27:58.276455 03380000 ########################## done.
10309 19:27:58.276607
10310 19:27:58.279370 The bootfile was 54212466 bytes long.
10311 19:27:58.279452
10312 19:27:58.283284 Sending tftp read request... done.
10313 19:27:58.283363
10314 19:27:58.283441 Waiting for the transfer...
10315 19:27:58.283516
10316 19:27:58.286316 00000000 # done.
10317 19:27:58.286392
10318 19:27:58.293092 Command line loaded dynamically from TFTP file: 13420397/tftp-deploy-49036zue/kernel/cmdline
10319 19:27:58.293225
10320 19:27:58.306461 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10321 19:27:58.306564
10322 19:27:58.309879 Loading FIT.
10323 19:27:58.309962
10324 19:27:58.313423 Image ramdisk-1 has 41252845 bytes.
10325 19:27:58.313508
10326 19:27:58.313573 Image fdt-1 has 47230 bytes.
10327 19:27:58.313634
10328 19:27:58.316461 Image kernel-1 has 12910355 bytes.
10329 19:27:58.316534
10330 19:27:58.326423 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10331 19:27:58.326531
10332 19:27:58.343162 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10333 19:27:58.343281
10334 19:27:58.349851 Choosing best match conf-1 for compat google,spherion-rev2.
10335 19:27:58.353418
10336 19:27:58.357897 Connected to device vid:did:rid of 1ae0:0028:00
10337 19:27:58.366221
10338 19:27:58.369769 tpm_get_response: command 0x17b, return code 0x0
10339 19:27:58.369855
10340 19:27:58.372833 ec_init: CrosEC protocol v3 supported (256, 248)
10341 19:27:58.378225
10342 19:27:58.381186 tpm_cleanup: add release locality here.
10343 19:27:58.381353
10344 19:27:58.381419 Shutting down all USB controllers.
10345 19:27:58.384917
10346 19:27:58.384998 Removing current net device
10347 19:27:58.385062
10348 19:27:58.391762 Exiting depthcharge with code 4 at timestamp: 99141453
10349 19:27:58.391845
10350 19:27:58.394941 LZMA decompressing kernel-1 to 0x821a6718
10351 19:27:58.395060
10352 19:27:58.397934 LZMA decompressing kernel-1 to 0x40000000
10353 19:27:59.992458
10354 19:27:59.992942 jumping to kernel
10355 19:27:59.994919 end: 2.2.4 bootloader-commands (duration 00:01:11) [common]
10356 19:27:59.995607 start: 2.2.5 auto-login-action (timeout 00:03:14) [common]
10357 19:27:59.996115 Setting prompt string to ['Linux version [0-9]']
10358 19:27:59.996590 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10359 19:27:59.997061 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10360 19:28:00.074848
10361 19:28:00.077905 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10362 19:28:00.082012 start: 2.2.5.1 login-action (timeout 00:03:14) [common]
10363 19:28:00.082515 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10364 19:28:00.082940 Setting prompt string to []
10365 19:28:00.083384 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10366 19:28:00.083969 Using line separator: #'\n'#
10367 19:28:00.084369 No login prompt set.
10368 19:28:00.084880 Parsing kernel messages
10369 19:28:00.085688 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10370 19:28:00.086355 [login-action] Waiting for messages, (timeout 00:03:14)
10371 19:28:00.086724 Waiting using forced prompt support (timeout 00:01:37)
10372 19:28:00.101270 [ 0.000000] Linux version 6.1.86-cip19 (KernelCI@build-j170728-arm64-gcc-10-defconfig-arm64-chromebook-wrkxq) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Apr 18 19:05:54 UTC 2024
10373 19:28:00.104629 [ 0.000000] random: crng init done
10374 19:28:00.111020 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10375 19:28:00.111500 [ 0.000000] efi: UEFI not found.
10376 19:28:00.121381 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10377 19:28:00.128160 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10378 19:28:00.138001 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10379 19:28:00.148130 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10380 19:28:00.154874 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10381 19:28:00.157880 [ 0.000000] printk: bootconsole [mtk8250] enabled
10382 19:28:00.166669 [ 0.000000] NUMA: No NUMA configuration found
10383 19:28:00.173508 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10384 19:28:00.180245 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10385 19:28:00.180826 [ 0.000000] Zone ranges:
10386 19:28:00.186600 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10387 19:28:00.190113 [ 0.000000] DMA32 empty
10388 19:28:00.196421 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10389 19:28:00.200113 [ 0.000000] Movable zone start for each node
10390 19:28:00.203150 [ 0.000000] Early memory node ranges
10391 19:28:00.209940 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10392 19:28:00.216628 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10393 19:28:00.222708 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10394 19:28:00.230273 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10395 19:28:00.236589 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10396 19:28:00.243350 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10397 19:28:00.299553 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10398 19:28:00.305627 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10399 19:28:00.312560 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10400 19:28:00.315699 [ 0.000000] psci: probing for conduit method from DT.
10401 19:28:00.322282 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10402 19:28:00.325527 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10403 19:28:00.332103 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10404 19:28:00.335727 [ 0.000000] psci: SMC Calling Convention v1.2
10405 19:28:00.343242 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10406 19:28:00.345499 [ 0.000000] Detected VIPT I-cache on CPU0
10407 19:28:00.352147 [ 0.000000] CPU features: detected: GIC system register CPU interface
10408 19:28:00.358693 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10409 19:28:00.365150 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10410 19:28:00.372135 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10411 19:28:00.378426 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10412 19:28:00.384900 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10413 19:28:00.391880 [ 0.000000] alternatives: applying boot alternatives
10414 19:28:00.395406 [ 0.000000] Fallback order for Node 0: 0
10415 19:28:00.405077 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10416 19:28:00.405192 [ 0.000000] Policy zone: Normal
10417 19:28:00.422209 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10418 19:28:00.431916 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10419 19:28:00.443516 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10420 19:28:00.453273 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10421 19:28:00.460026 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10422 19:28:00.463573 <6>[ 0.000000] software IO TLB: area num 8.
10423 19:28:00.519981 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10424 19:28:00.669504 <6>[ 0.000000] Memory: 7924284K/8385536K available (18048K kernel code, 4118K rwdata, 22288K rodata, 8448K init, 616K bss, 428484K reserved, 32768K cma-reserved)
10425 19:28:00.676367 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10426 19:28:00.683008 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10427 19:28:00.685967 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10428 19:28:00.692702 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10429 19:28:00.699475 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10430 19:28:00.702931 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10431 19:28:00.712915 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10432 19:28:00.719445 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10433 19:28:00.722541 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10434 19:28:00.730236 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10435 19:28:00.733707 <6>[ 0.000000] GICv3: 608 SPIs implemented
10436 19:28:00.740652 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10437 19:28:00.743722 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10438 19:28:00.747101 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10439 19:28:00.757027 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10440 19:28:00.767227 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10441 19:28:00.780535 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10442 19:28:00.787114 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10443 19:28:00.796104 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10444 19:28:00.809163 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10445 19:28:00.815881 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10446 19:28:00.822473 <6>[ 0.009240] Console: colour dummy device 80x25
10447 19:28:00.832191 <6>[ 0.013967] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10448 19:28:00.836151 <6>[ 0.024409] pid_max: default: 32768 minimum: 301
10449 19:28:00.842176 <6>[ 0.029280] LSM: Security Framework initializing
10450 19:28:00.849061 <6>[ 0.034219] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10451 19:28:00.858836 <6>[ 0.042033] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10452 19:28:00.865425 <6>[ 0.051455] cblist_init_generic: Setting adjustable number of callback queues.
10453 19:28:00.871984 <6>[ 0.058896] cblist_init_generic: Setting shift to 3 and lim to 1.
10454 19:28:00.882072 <6>[ 0.065235] cblist_init_generic: Setting adjustable number of callback queues.
10455 19:28:00.885615 <6>[ 0.072662] cblist_init_generic: Setting shift to 3 and lim to 1.
10456 19:28:00.892403 <6>[ 0.079062] rcu: Hierarchical SRCU implementation.
10457 19:28:00.899048 <6>[ 0.084077] rcu: Max phase no-delay instances is 1000.
10458 19:28:00.905880 <6>[ 0.091099] EFI services will not be available.
10459 19:28:00.908732 <6>[ 0.096056] smp: Bringing up secondary CPUs ...
10460 19:28:00.916280 <6>[ 0.101101] Detected VIPT I-cache on CPU1
10461 19:28:00.923373 <6>[ 0.101170] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10462 19:28:00.929620 <6>[ 0.101202] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10463 19:28:00.933327 <6>[ 0.101540] Detected VIPT I-cache on CPU2
10464 19:28:00.939953 <6>[ 0.101593] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10465 19:28:00.946219 <6>[ 0.101613] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10466 19:28:00.953089 <6>[ 0.101870] Detected VIPT I-cache on CPU3
10467 19:28:00.960140 <6>[ 0.101919] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10468 19:28:00.966609 <6>[ 0.101934] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10469 19:28:00.969842 <6>[ 0.102236] CPU features: detected: Spectre-v4
10470 19:28:00.976598 <6>[ 0.102242] CPU features: detected: Spectre-BHB
10471 19:28:00.979675 <6>[ 0.102247] Detected PIPT I-cache on CPU4
10472 19:28:00.986881 <6>[ 0.102304] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10473 19:28:00.993446 <6>[ 0.102322] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10474 19:28:00.996631 <6>[ 0.102617] Detected PIPT I-cache on CPU5
10475 19:28:01.006767 <6>[ 0.102679] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10476 19:28:01.012959 <6>[ 0.102695] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10477 19:28:01.016380 <6>[ 0.102961] Detected PIPT I-cache on CPU6
10478 19:28:01.022918 <6>[ 0.103020] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10479 19:28:01.029867 <6>[ 0.103035] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10480 19:28:01.033261 <6>[ 0.103323] Detected PIPT I-cache on CPU7
10481 19:28:01.043266 <6>[ 0.103387] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10482 19:28:01.049449 <6>[ 0.103403] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10483 19:28:01.053115 <6>[ 0.103451] smp: Brought up 1 node, 8 CPUs
10484 19:28:01.056047 <6>[ 0.244748] SMP: Total of 8 processors activated.
10485 19:28:01.062878 <6>[ 0.249669] CPU features: detected: 32-bit EL0 Support
10486 19:28:01.072808 <6>[ 0.255066] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10487 19:28:01.079495 <6>[ 0.263921] CPU features: detected: Common not Private translations
10488 19:28:01.083032 <6>[ 0.270437] CPU features: detected: CRC32 instructions
10489 19:28:01.089531 <6>[ 0.275822] CPU features: detected: RCpc load-acquire (LDAPR)
10490 19:28:01.096657 <6>[ 0.281818] CPU features: detected: LSE atomic instructions
10491 19:28:01.102919 <6>[ 0.287600] CPU features: detected: Privileged Access Never
10492 19:28:01.106065 <6>[ 0.293416] CPU features: detected: RAS Extension Support
10493 19:28:01.112642 <6>[ 0.299024] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10494 19:28:01.119712 <6>[ 0.306243] CPU: All CPU(s) started at EL2
10495 19:28:01.122755 <6>[ 0.310560] alternatives: applying system-wide alternatives
10496 19:28:01.134116 <6>[ 0.321371] devtmpfs: initialized
10497 19:28:01.146939 <6>[ 0.330356] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10498 19:28:01.156920 <6>[ 0.340316] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10499 19:28:01.163195 <6>[ 0.348572] pinctrl core: initialized pinctrl subsystem
10500 19:28:01.166686 <6>[ 0.355207] DMI not present or invalid.
10501 19:28:01.173614 <6>[ 0.359619] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10502 19:28:01.183547 <6>[ 0.366509] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10503 19:28:01.190119 <6>[ 0.374093] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10504 19:28:01.199578 <6>[ 0.382323] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10505 19:28:01.203120 <6>[ 0.390564] audit: initializing netlink subsys (disabled)
10506 19:28:01.212985 <5>[ 0.396260] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10507 19:28:01.219670 <6>[ 0.396960] thermal_sys: Registered thermal governor 'step_wise'
10508 19:28:01.226194 <6>[ 0.404223] thermal_sys: Registered thermal governor 'power_allocator'
10509 19:28:01.229908 <6>[ 0.410477] cpuidle: using governor menu
10510 19:28:01.236039 <6>[ 0.421431] NET: Registered PF_QIPCRTR protocol family
10511 19:28:01.242965 <6>[ 0.426920] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10512 19:28:01.246359 <6>[ 0.434022] ASID allocator initialised with 32768 entries
10513 19:28:01.253452 <6>[ 0.440585] Serial: AMBA PL011 UART driver
10514 19:28:01.262446 <4>[ 0.449309] Trying to register duplicate clock ID: 134
10515 19:28:01.318524 <6>[ 0.508846] KASLR enabled
10516 19:28:01.333078 <6>[ 0.516601] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10517 19:28:01.339921 <6>[ 0.523615] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10518 19:28:01.346550 <6>[ 0.530100] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10519 19:28:01.353114 <6>[ 0.537105] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10520 19:28:01.359361 <6>[ 0.543590] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10521 19:28:01.366061 <6>[ 0.550594] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10522 19:28:01.372910 <6>[ 0.557077] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10523 19:28:01.379442 <6>[ 0.564084] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10524 19:28:01.382654 <6>[ 0.571606] ACPI: Interpreter disabled.
10525 19:28:01.391268 <6>[ 0.578027] iommu: Default domain type: Translated
10526 19:28:01.397736 <6>[ 0.583138] iommu: DMA domain TLB invalidation policy: strict mode
10527 19:28:01.400854 <5>[ 0.589800] SCSI subsystem initialized
10528 19:28:01.407795 <6>[ 0.593975] usbcore: registered new interface driver usbfs
10529 19:28:01.414215 <6>[ 0.599709] usbcore: registered new interface driver hub
10530 19:28:01.417663 <6>[ 0.605262] usbcore: registered new device driver usb
10531 19:28:01.424209 <6>[ 0.611362] pps_core: LinuxPPS API ver. 1 registered
10532 19:28:01.434400 <6>[ 0.616554] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10533 19:28:01.437668 <6>[ 0.625901] PTP clock support registered
10534 19:28:01.440713 <6>[ 0.630144] EDAC MC: Ver: 3.0.0
10535 19:28:01.448043 <6>[ 0.635288] FPGA manager framework
10536 19:28:01.455025 <6>[ 0.638967] Advanced Linux Sound Architecture Driver Initialized.
10537 19:28:01.458086 <6>[ 0.645753] vgaarb: loaded
10538 19:28:01.464652 <6>[ 0.648926] clocksource: Switched to clocksource arch_sys_counter
10539 19:28:01.468143 <5>[ 0.655373] VFS: Disk quotas dquot_6.6.0
10540 19:28:01.475170 <6>[ 0.659560] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10541 19:28:01.478320 <6>[ 0.666748] pnp: PnP ACPI: disabled
10542 19:28:01.486591 <6>[ 0.673411] NET: Registered PF_INET protocol family
10543 19:28:01.496377 <6>[ 0.679012] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10544 19:28:01.507736 <6>[ 0.691329] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10545 19:28:01.517537 <6>[ 0.700143] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10546 19:28:01.523940 <6>[ 0.708116] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10547 19:28:01.530957 <6>[ 0.716817] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10548 19:28:01.543037 <6>[ 0.726576] TCP: Hash tables configured (established 65536 bind 65536)
10549 19:28:01.549325 <6>[ 0.733442] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10550 19:28:01.556006 <6>[ 0.740642] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10551 19:28:01.563065 <6>[ 0.748348] NET: Registered PF_UNIX/PF_LOCAL protocol family
10552 19:28:01.569606 <6>[ 0.754499] RPC: Registered named UNIX socket transport module.
10553 19:28:01.572887 <6>[ 0.760652] RPC: Registered udp transport module.
10554 19:28:01.579466 <6>[ 0.765584] RPC: Registered tcp transport module.
10555 19:28:01.586068 <6>[ 0.770518] RPC: Registered tcp NFSv4.1 backchannel transport module.
10556 19:28:01.589704 <6>[ 0.777186] PCI: CLS 0 bytes, default 64
10557 19:28:01.592819 <6>[ 0.781523] Unpacking initramfs...
10558 19:28:01.617609 <6>[ 0.801050] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10559 19:28:01.627575 <6>[ 0.809701] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10560 19:28:01.630608 <6>[ 0.818540] kvm [1]: IPA Size Limit: 40 bits
10561 19:28:01.637073 <6>[ 0.823068] kvm [1]: GICv3: no GICV resource entry
10562 19:28:01.640793 <6>[ 0.828087] kvm [1]: disabling GICv2 emulation
10563 19:28:01.647580 <6>[ 0.832774] kvm [1]: GIC system register CPU interface enabled
10564 19:28:01.650633 <6>[ 0.838930] kvm [1]: vgic interrupt IRQ18
10565 19:28:01.657363 <6>[ 0.843287] kvm [1]: VHE mode initialized successfully
10566 19:28:01.663952 <5>[ 0.849713] Initialise system trusted keyrings
10567 19:28:01.670843 <6>[ 0.854565] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10568 19:28:01.677696 <6>[ 0.864617] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10569 19:28:01.684542 <5>[ 0.871005] NFS: Registering the id_resolver key type
10570 19:28:01.688063 <5>[ 0.876302] Key type id_resolver registered
10571 19:28:01.694519 <5>[ 0.880715] Key type id_legacy registered
10572 19:28:01.701171 <6>[ 0.885001] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10573 19:28:01.708181 <6>[ 0.891923] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10574 19:28:01.714844 <6>[ 0.899637] 9p: Installing v9fs 9p2000 file system support
10575 19:28:01.751405 <5>[ 0.937894] Key type asymmetric registered
10576 19:28:01.754699 <5>[ 0.942223] Asymmetric key parser 'x509' registered
10577 19:28:01.764711 <6>[ 0.947362] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10578 19:28:01.767557 <6>[ 0.954979] io scheduler mq-deadline registered
10579 19:28:01.770546 <6>[ 0.959757] io scheduler kyber registered
10580 19:28:01.789599 <6>[ 0.976568] EINJ: ACPI disabled.
10581 19:28:01.822286 <4>[ 1.001921] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10582 19:28:01.831350 <4>[ 1.012556] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10583 19:28:01.845757 <6>[ 1.033108] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10584 19:28:01.854107 <6>[ 1.041072] printk: console [ttyS0] disabled
10585 19:28:01.882542 <6>[ 1.065697] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10586 19:28:01.888620 <6>[ 1.075161] printk: console [ttyS0] enabled
10587 19:28:01.892032 <6>[ 1.075161] printk: console [ttyS0] enabled
10588 19:28:01.898994 <6>[ 1.084054] printk: bootconsole [mtk8250] disabled
10589 19:28:01.902260 <6>[ 1.084054] printk: bootconsole [mtk8250] disabled
10590 19:28:01.908710 <6>[ 1.095087] SuperH (H)SCI(F) driver initialized
10591 19:28:01.912124 <6>[ 1.100355] msm_serial: driver initialized
10592 19:28:01.925988 <6>[ 1.109248] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10593 19:28:01.936059 <6>[ 1.117793] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10594 19:28:01.942788 <6>[ 1.126336] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10595 19:28:01.952415 <6>[ 1.134963] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10596 19:28:01.958756 <6>[ 1.143674] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10597 19:28:01.969128 <6>[ 1.152393] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10598 19:28:01.979086 <6>[ 1.160935] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10599 19:28:01.985355 <6>[ 1.169733] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10600 19:28:01.995393 <6>[ 1.178276] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10601 19:28:02.006990 <6>[ 1.193797] loop: module loaded
10602 19:28:02.013692 <6>[ 1.199754] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10603 19:28:02.035716 <4>[ 1.223139] mtk-pmic-keys: Failed to locate of_node [id: -1]
10604 19:28:02.042842 <6>[ 1.230015] megasas: 07.719.03.00-rc1
10605 19:28:02.052920 <6>[ 1.239651] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10606 19:28:02.061890 <6>[ 1.248324] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10607 19:28:02.078395 <6>[ 1.265145] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10608 19:28:02.134667 <6>[ 1.315363] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10609 19:28:03.325408 <6>[ 2.512326] Freeing initrd memory: 40284K
10610 19:28:03.336884 <6>[ 2.523910] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10611 19:28:03.347942 <6>[ 2.535085] tun: Universal TUN/TAP device driver, 1.6
10612 19:28:03.351530 <6>[ 2.541178] thunder_xcv, ver 1.0
10613 19:28:03.354626 <6>[ 2.544674] thunder_bgx, ver 1.0
10614 19:28:03.357664 <6>[ 2.548175] nicpf, ver 1.0
10615 19:28:03.368169 <6>[ 2.552213] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10616 19:28:03.371447 <6>[ 2.559689] hns3: Copyright (c) 2017 Huawei Corporation.
10617 19:28:03.378457 <6>[ 2.565277] hclge is initializing
10618 19:28:03.381319 <6>[ 2.568853] e1000: Intel(R) PRO/1000 Network Driver
10619 19:28:03.387795 <6>[ 2.573983] e1000: Copyright (c) 1999-2006 Intel Corporation.
10620 19:28:03.391235 <6>[ 2.580001] e1000e: Intel(R) PRO/1000 Network Driver
10621 19:28:03.398043 <6>[ 2.585216] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10622 19:28:03.404584 <6>[ 2.591402] igb: Intel(R) Gigabit Ethernet Network Driver
10623 19:28:03.411280 <6>[ 2.597052] igb: Copyright (c) 2007-2014 Intel Corporation.
10624 19:28:03.418077 <6>[ 2.602889] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10625 19:28:03.424299 <6>[ 2.609408] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10626 19:28:03.427810 <6>[ 2.615873] sky2: driver version 1.30
10627 19:28:03.434105 <6>[ 2.620867] VFIO - User Level meta-driver version: 0.3
10628 19:28:03.442082 <6>[ 2.629171] usbcore: registered new interface driver usb-storage
10629 19:28:03.448824 <6>[ 2.635612] usbcore: registered new device driver onboard-usb-hub
10630 19:28:03.457593 <6>[ 2.644814] mt6397-rtc mt6359-rtc: registered as rtc0
10631 19:28:03.467499 <6>[ 2.650277] mt6397-rtc mt6359-rtc: setting system clock to 2024-04-18T19:28:03 UTC (1713468483)
10632 19:28:03.470583 <6>[ 2.659846] i2c_dev: i2c /dev entries driver
10633 19:28:03.487848 <6>[ 2.671721] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10634 19:28:03.494402 <4>[ 2.680452] cpu cpu0: supply cpu not found, using dummy regulator
10635 19:28:03.501141 <4>[ 2.686871] cpu cpu1: supply cpu not found, using dummy regulator
10636 19:28:03.507878 <4>[ 2.693277] cpu cpu2: supply cpu not found, using dummy regulator
10637 19:28:03.514375 <4>[ 2.699694] cpu cpu3: supply cpu not found, using dummy regulator
10638 19:28:03.520993 <4>[ 2.706089] cpu cpu4: supply cpu not found, using dummy regulator
10639 19:28:03.527721 <4>[ 2.712489] cpu cpu5: supply cpu not found, using dummy regulator
10640 19:28:03.534276 <4>[ 2.718884] cpu cpu6: supply cpu not found, using dummy regulator
10641 19:28:03.540484 <4>[ 2.725285] cpu cpu7: supply cpu not found, using dummy regulator
10642 19:28:03.560039 <6>[ 2.746946] cpu cpu0: EM: created perf domain
10643 19:28:03.563048 <6>[ 2.751858] cpu cpu4: EM: created perf domain
10644 19:28:03.570537 <6>[ 2.757499] sdhci: Secure Digital Host Controller Interface driver
10645 19:28:03.576730 <6>[ 2.763930] sdhci: Copyright(c) Pierre Ossman
10646 19:28:03.583598 <6>[ 2.768889] Synopsys Designware Multimedia Card Interface Driver
10647 19:28:03.590007 <6>[ 2.775533] sdhci-pltfm: SDHCI platform and OF driver helper
10648 19:28:03.593336 <6>[ 2.775581] mmc0: CQHCI version 5.10
10649 19:28:03.600046 <6>[ 2.785904] ledtrig-cpu: registered to indicate activity on CPUs
10650 19:28:03.607329 <6>[ 2.792923] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10651 19:28:03.613422 <6>[ 2.799972] usbcore: registered new interface driver usbhid
10652 19:28:03.617018 <6>[ 2.805798] usbhid: USB HID core driver
10653 19:28:03.623435 <6>[ 2.810015] spi_master spi0: will run message pump with realtime priority
10654 19:28:03.668078 <6>[ 2.848525] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10655 19:28:03.686644 <6>[ 2.863418] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10656 19:28:03.689657 <6>[ 2.877286] mmc0: Command Queue Engine enabled
10657 19:28:03.696563 <6>[ 2.882034] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10658 19:28:03.703176 <6>[ 2.888747] cros-ec-spi spi0.0: Chrome EC device registered
10659 19:28:03.706076 <6>[ 2.889293] mmcblk0: mmc0:0001 DA4128 116 GiB
10660 19:28:03.717712 <6>[ 2.904844] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10661 19:28:03.724362 <6>[ 2.911783] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10662 19:28:03.731273 <6>[ 2.917958] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10663 19:28:03.737793 <6>[ 2.924241] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10664 19:28:03.747561 <6>[ 2.929559] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10665 19:28:03.754916 <6>[ 2.941448] NET: Registered PF_PACKET protocol family
10666 19:28:03.758104 <6>[ 2.946849] 9pnet: Installing 9P2000 support
10667 19:28:03.764534 <5>[ 2.951408] Key type dns_resolver registered
10668 19:28:03.767756 <6>[ 2.956402] registered taskstats version 1
10669 19:28:03.774119 <5>[ 2.960787] Loading compiled-in X.509 certificates
10670 19:28:03.806648 <4>[ 2.987057] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10671 19:28:03.816485 <4>[ 2.997849] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10672 19:28:03.823157 <3>[ 3.008405] debugfs: File 'uA_load' in directory '/' already present!
10673 19:28:03.829728 <3>[ 3.015108] debugfs: File 'min_uV' in directory '/' already present!
10674 19:28:03.836405 <3>[ 3.021715] debugfs: File 'max_uV' in directory '/' already present!
10675 19:28:03.843113 <3>[ 3.028322] debugfs: File 'constraint_flags' in directory '/' already present!
10676 19:28:03.853746 <3>[ 3.037938] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10677 19:28:03.863520 <6>[ 3.050882] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10678 19:28:03.870186 <6>[ 3.057705] xhci-mtk 11200000.usb: xHCI Host Controller
10679 19:28:03.876983 <6>[ 3.063214] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10680 19:28:03.887512 <6>[ 3.071074] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10681 19:28:03.893837 <6>[ 3.080510] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10682 19:28:03.900386 <6>[ 3.086565] xhci-mtk 11200000.usb: xHCI Host Controller
10683 19:28:03.907093 <6>[ 3.092040] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10684 19:28:03.913865 <6>[ 3.099686] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10685 19:28:03.920607 <6>[ 3.107347] hub 1-0:1.0: USB hub found
10686 19:28:03.923608 <6>[ 3.111355] hub 1-0:1.0: 1 port detected
10687 19:28:03.930173 <6>[ 3.115631] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10688 19:28:03.937349 <6>[ 3.124163] hub 2-0:1.0: USB hub found
10689 19:28:03.940374 <6>[ 3.128167] hub 2-0:1.0: 1 port detected
10690 19:28:03.948765 <6>[ 3.136260] mtk-msdc 11f70000.mmc: Got CD GPIO
10691 19:28:03.960607 <6>[ 3.144756] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10692 19:28:03.967404 <6>[ 3.152789] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10693 19:28:03.977399 <4>[ 3.160767] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10694 19:28:03.987162 <6>[ 3.170292] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10695 19:28:03.993842 <6>[ 3.178402] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10696 19:28:04.000436 <6>[ 3.186384] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10697 19:28:04.010260 <6>[ 3.194318] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10698 19:28:04.017357 <6>[ 3.202137] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10699 19:28:04.027011 <6>[ 3.209966] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10700 19:28:04.037478 <6>[ 3.220076] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10701 19:28:04.043744 <6>[ 3.228460] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10702 19:28:04.054202 <6>[ 3.236800] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10703 19:28:04.060284 <6>[ 3.245150] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10704 19:28:04.070369 <6>[ 3.253488] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10705 19:28:04.077080 <6>[ 3.261837] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10706 19:28:04.086667 <6>[ 3.270174] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10707 19:28:04.093391 <6>[ 3.278523] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10708 19:28:04.103628 <6>[ 3.286862] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10709 19:28:04.110429 <6>[ 3.295209] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10710 19:28:04.120019 <6>[ 3.303549] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10711 19:28:04.126641 <6>[ 3.311886] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10712 19:28:04.136635 <6>[ 3.320223] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10713 19:28:04.143073 <6>[ 3.328560] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10714 19:28:04.153099 <6>[ 3.336897] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10715 19:28:04.160472 <6>[ 3.345691] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10716 19:28:04.167074 <6>[ 3.352931] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10717 19:28:04.173476 <6>[ 3.359822] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10718 19:28:04.180114 <6>[ 3.366714] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10719 19:28:04.186191 <6>[ 3.373746] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10720 19:28:04.196417 <6>[ 3.380624] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10721 19:28:04.206674 <6>[ 3.389754] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10722 19:28:04.216415 <6>[ 3.398873] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10723 19:28:04.226548 <6>[ 3.408192] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10724 19:28:04.236298 <6>[ 3.417663] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10725 19:28:04.243402 <6>[ 3.427130] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10726 19:28:04.252837 <6>[ 3.436249] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10727 19:28:04.262660 <6>[ 3.445720] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10728 19:28:04.272807 <6>[ 3.454839] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10729 19:28:04.282626 <6>[ 3.464133] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10730 19:28:04.292843 <6>[ 3.474293] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10731 19:28:04.302572 <6>[ 3.485663] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10732 19:28:04.329088 <6>[ 3.513452] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10733 19:28:04.357531 <6>[ 3.544863] hub 2-1:1.0: USB hub found
10734 19:28:04.360628 <6>[ 3.549343] hub 2-1:1.0: 3 ports detected
10735 19:28:04.369576 <6>[ 3.556672] hub 2-1:1.0: USB hub found
10736 19:28:04.372403 <6>[ 3.561108] hub 2-1:1.0: 3 ports detected
10737 19:28:04.481081 <6>[ 3.665221] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10738 19:28:04.636106 <6>[ 3.823223] hub 1-1:1.0: USB hub found
10739 19:28:04.639387 <6>[ 3.827708] hub 1-1:1.0: 4 ports detected
10740 19:28:04.649734 <6>[ 3.836752] hub 1-1:1.0: USB hub found
10741 19:28:04.652823 <6>[ 3.841261] hub 1-1:1.0: 4 ports detected
10742 19:28:04.721539 <6>[ 3.905408] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10743 19:28:04.973052 <6>[ 4.157243] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10744 19:28:05.106125 <6>[ 4.293184] hub 1-1.4:1.0: USB hub found
10745 19:28:05.109192 <6>[ 4.297865] hub 1-1.4:1.0: 2 ports detected
10746 19:28:05.118634 <6>[ 4.306271] hub 1-1.4:1.0: USB hub found
10747 19:28:05.122263 <6>[ 4.310862] hub 1-1.4:1.0: 2 ports detected
10748 19:28:05.421097 <6>[ 4.605246] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10749 19:28:05.613608 <6>[ 4.797250] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10750 19:28:16.598003 <6>[ 15.790240] ALSA device list:
10751 19:28:16.604450 <6>[ 15.793534] No soundcards found.
10752 19:28:16.613388 <6>[ 15.802005] Freeing unused kernel memory: 8448K
10753 19:28:16.616812 <6>[ 15.806993] Run /init as init process
10754 19:28:16.664348 <6>[ 15.853059] NET: Registered PF_INET6 protocol family
10755 19:28:16.670738 <6>[ 15.859430] Segment Routing with IPv6
10756 19:28:16.674404 <6>[ 15.863374] In-situ OAM (IOAM) with IPv6
10757 19:28:16.717053 <30>[ 15.879358] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10758 19:28:16.723679 <30>[ 15.912448] systemd[1]: Detected architecture arm64.
10759 19:28:16.723791
10760 19:28:16.729942 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10761 19:28:16.730023
10762 19:28:16.730086
10763 19:28:16.744668 <30>[ 15.933534] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10764 19:28:16.885581 <30>[ 16.070831] systemd[1]: Queued start job for default target graphical.target.
10765 19:28:16.933792 <30>[ 16.119289] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10766 19:28:16.940465 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10767 19:28:16.940562
10768 19:28:16.960724 <30>[ 16.146125] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10769 19:28:16.967271 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10770 19:28:16.967354
10771 19:28:16.992916 <30>[ 16.178597] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10772 19:28:17.003146 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10773 19:28:17.003284
10774 19:28:17.021175 <30>[ 16.206478] systemd[1]: Created slice user.slice - User and Session Slice.
10775 19:28:17.027909 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10776 19:28:17.028019
10777 19:28:17.047370 <30>[ 16.229454] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10778 19:28:17.053858 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10779 19:28:17.054000
10780 19:28:17.075456 <30>[ 16.257430] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10781 19:28:17.081925 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10782 19:28:17.082022
10783 19:28:17.110170 <30>[ 16.285787] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10784 19:28:17.120295 <30>[ 16.305678] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10785 19:28:17.126778 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10786 19:28:17.126863
10787 19:28:17.144044 <30>[ 16.329237] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10788 19:28:17.150565 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10789 19:28:17.150648
10790 19:28:17.167891 <30>[ 16.353269] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10791 19:28:17.177802 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10792 19:28:17.177886
10793 19:28:17.192471 <30>[ 16.381354] systemd[1]: Reached target paths.target - Path Units.
10794 19:28:17.199167 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10795 19:28:17.202542
10796 19:28:17.220371 <30>[ 16.405650] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10797 19:28:17.226947 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10798 19:28:17.227043
10799 19:28:17.240259 <30>[ 16.429251] systemd[1]: Reached target slices.target - Slice Units.
10800 19:28:17.250286 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10801 19:28:17.250373
10802 19:28:17.265179 <30>[ 16.453702] systemd[1]: Reached target swap.target - Swaps.
10803 19:28:17.271560 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10804 19:28:17.271658
10805 19:28:17.291885 <30>[ 16.477738] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10806 19:28:17.301840 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10807 19:28:17.301923
10808 19:28:17.320174 <30>[ 16.505684] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10809 19:28:17.329796 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10810 19:28:17.329880
10811 19:28:17.349576 <30>[ 16.535233] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10812 19:28:17.359680 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10813 19:28:17.359773
10814 19:28:17.376341 <30>[ 16.561825] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10815 19:28:17.386892 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10816 19:28:17.386983
10817 19:28:17.404745 <30>[ 16.589867] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10818 19:28:17.411478 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10819 19:28:17.411612
10820 19:28:17.428741 <30>[ 16.613892] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10821 19:28:17.438323 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10822 19:28:17.438408
10823 19:28:17.457417 <30>[ 16.642641] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10824 19:28:17.467016 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10825 19:28:17.467099
10826 19:28:17.485073 <30>[ 16.670364] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10827 19:28:17.494529 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10828 19:28:17.494612
10829 19:28:17.543750 <30>[ 16.729393] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10830 19:28:17.550233 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10831 19:28:17.550323
10832 19:28:17.570013 <30>[ 16.755284] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10833 19:28:17.576097 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10834 19:28:17.576184
10835 19:28:17.598397 <30>[ 16.784249] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10836 19:28:17.605135 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10837 19:28:17.605258
10838 19:28:17.630777 <30>[ 16.809537] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10839 19:28:17.668511 <30>[ 16.853969] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10840 19:28:17.678037 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10841 19:28:17.678123
10842 19:28:17.700744 <30>[ 16.886503] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10843 19:28:17.707793 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10844 19:28:17.707878
10845 19:28:17.764408 <30>[ 16.949996] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10846 19:28:17.774723 Startin<6>[ 16.959403] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10847 19:28:17.781058 g [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10848 19:28:17.781141
10849 19:28:17.804644 <30>[ 16.990327] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10850 19:28:17.811163 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10851 19:28:17.811247
10852 19:28:17.836980 <30>[ 17.022510] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10853 19:28:17.843557 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10854 19:28:17.843643
10855 19:28:17.868405 <30>[ 17.054108] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10856 19:28:17.875003 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10857 19:28:17.875086
10858 19:28:17.928011 <30>[ 17.113600] systemd[1]: Starting systemd-journald.service - Journal Service...
10859 19:28:17.934287 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10860 19:28:17.934380
10861 19:28:17.955048 <30>[ 17.140449] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10862 19:28:17.961720 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10863 19:28:17.961805
10864 19:28:17.988584 <30>[ 17.170523] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10865 19:28:17.994980 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10866 19:28:17.995065
10867 19:28:18.016469 <30>[ 17.202099] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10868 19:28:18.026251 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10869 19:28:18.026338
10870 19:28:18.047228 <30>[ 17.232468] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10871 19:28:18.053219 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10872 19:28:18.053337
10873 19:28:18.079378 <30>[ 17.265043] systemd[1]: Started systemd-journald.service - Journal Service.
10874 19:28:18.086071 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10875 19:28:18.086157
10876 19:28:18.108105 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10877 19:28:18.108190
10878 19:28:18.124781 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10879 19:28:18.124867
10880 19:28:18.144092 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10881 19:28:18.144177
10882 19:28:18.164538 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10883 19:28:18.164627
10884 19:28:18.184672 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10885 19:28:18.184775
10886 19:28:18.204524 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10887 19:28:18.204612
10888 19:28:18.225990 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10889 19:28:18.226104
10890 19:28:18.245374 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10891 19:28:18.245457
10892 19:28:18.266994 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10893 19:28:18.267099
10894 19:28:18.285863 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10895 19:28:18.285966
10896 19:28:18.309760 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10897 19:28:18.309855
10898 19:28:18.334451 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10899 19:28:18.334595
10900 19:28:18.340880 See 'systemctl status systemd-remount-fs.service' for details.
10901 19:28:18.340965
10902 19:28:18.350925 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10903 19:28:18.351009
10904 19:28:18.374487 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10905 19:28:18.374646
10906 19:28:18.420186 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10907 19:28:18.420384
10908 19:28:18.443753 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10909 19:28:18.443925
10910 19:28:18.462368 <46>[ 17.648402] systemd-journald[187]: Received client request to flush runtime journal.
10911 19:28:18.475095 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10912 19:28:18.475205
10913 19:28:18.496085 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10914 19:28:18.496215
10915 19:28:18.525059 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10916 19:28:18.525234
10917 19:28:18.558176 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10918 19:28:18.558327
10919 19:28:18.581326 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10920 19:28:18.581454
10921 19:28:18.604956 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10922 19:28:18.605071
10923 19:28:18.628749 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10924 19:28:18.628905
10925 19:28:18.652797 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10926 19:28:18.652927
10927 19:28:18.699834 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10928 19:28:18.699982
10929 19:28:18.722201 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10930 19:28:18.722336
10931 19:28:18.739913 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10932 19:28:18.740025
10933 19:28:18.755358 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10934 19:28:18.755485
10935 19:28:18.808523 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10936 19:28:18.808673
10937 19:28:18.831862 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10938 19:28:18.831988
10939 19:28:18.855056 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10940 19:28:18.855182
10941 19:28:18.874731 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10942 19:28:18.874850
10943 19:28:18.909113 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10944 19:28:18.909285
10945 19:28:18.946739 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10946 19:28:18.946873
10947 19:28:18.986582 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10948 19:28:18.986721
10949 19:28:19.035822 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10950 19:28:19.035967
10951 19:28:19.049604 <5>[ 18.235260] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10952 19:28:19.074978 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10953 19:28:19.075099
10954 19:28:19.081182 <5>[ 18.268667] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10955 19:28:19.091203 <5>[ 18.276167] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10956 19:28:19.098281 <4>[ 18.284761] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10957 19:28:19.104896 <6>[ 18.293919] cfg80211: failed to load regulatory.db
10958 19:28:19.114525 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10959 19:28:19.114614
10960 19:28:19.135227 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10961 19:28:19.135336
10962 19:28:19.255893 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10963 19:28:19.256068
10964 19:28:19.262042 <6>[ 18.449058] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10965 19:28:19.273094 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10966 19:28:19.273183
10967 19:28:19.281402 <6>[ 18.470694] remoteproc remoteproc0: scp is available
10968 19:28:19.288461 <6>[ 18.475368] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10969 19:28:19.294785 <6>[ 18.476162] remoteproc remoteproc0: powering up scp
10970 19:28:19.304702 <6>[ 18.483848] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10971 19:28:19.311742 <6>[ 18.488709] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10972 19:28:19.321782 <3>[ 18.494649] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10973 19:28:19.328213 <3>[ 18.494657] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10974 19:28:19.334695 <3>[ 18.494661] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10975 19:28:19.344863 <6>[ 18.497336] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10976 19:28:19.351629 <3>[ 18.497470] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10977 19:28:19.360969 <3>[ 18.497482] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10978 19:28:19.367976 <3>[ 18.497486] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10979 19:28:19.377720 <3>[ 18.497495] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10980 19:28:19.384627 <3>[ 18.497499] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10981 19:28:19.394709 <3>[ 18.497536] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10982 19:28:19.401258 <3>[ 18.497570] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10983 19:28:19.407705 <3>[ 18.497573] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10984 19:28:19.417928 <3>[ 18.497575] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10985 19:28:19.424781 <3>[ 18.497603] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10986 19:28:19.434659 <3>[ 18.497606] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10987 19:28:19.441351 <3>[ 18.497608] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10988 19:28:19.451271 <3>[ 18.497611] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10989 19:28:19.457678 <3>[ 18.497614] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10990 19:28:19.464271 <3>[ 18.497635] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10991 19:28:19.471405 <6>[ 18.505777] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10992 19:28:19.477952 <6>[ 18.566923] mc: Linux media interface: v0.10
10993 19:28:19.484653 <4>[ 18.583333] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10994 19:28:19.490984 <6>[ 18.589588] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10995 19:28:19.497677 <4>[ 18.604689] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10996 19:28:19.503934 <6>[ 18.634304] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10997 19:28:19.514115 <6>[ 18.691890] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10998 19:28:19.520664 <6>[ 18.691898] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10999 19:28:19.527485 <6>[ 18.692781] pci_bus 0000:00: root bus resource [bus 00-ff]
11000 19:28:19.533979 <6>[ 18.699529] remoteproc remoteproc0: remote processor scp is now up
11001 19:28:19.540297 <6>[ 18.708083] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
11002 19:28:19.548203 <4>[ 18.718885] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
11003 19:28:19.554691 <4>[ 18.718885] Fallback method does not support PEC.
11004 19:28:19.564138 <6>[ 18.720873] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
11005 19:28:19.574441 <3>[ 18.744224] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11006 19:28:19.578012 <6>[ 18.748161] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
11007 19:28:19.584516 <6>[ 18.750616] usbcore: registered new device driver r8152-cfgselector
11008 19:28:19.594125 <6>[ 18.779761] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
11009 19:28:19.597791 <6>[ 18.779848] pci 0000:00:00.0: supports D1 D2
11010 19:28:19.604357 <6>[ 18.780187] videodev: Linux video capture interface: v2.00
11011 19:28:19.611760 <6>[ 18.781384] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
11012 19:28:19.618594 <6>[ 18.783661] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
11013 19:28:19.632210 [[0;32m OK [<6>[ 18.783898] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
11014 19:28:19.639166 0m] Reached targ<3>[ 18.807032] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11015 19:28:19.648840 et [0;1;39mtime<3>[ 18.809551] power_supply sbs-5-000b: driver failed to report `temp' property: -6
11016 19:28:19.655684 <6>[ 18.814037] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11017 19:28:19.666121 -set.target[0m <6>[ 18.815101] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
11018 19:28:19.675733 <6>[ 18.823091] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
11019 19:28:19.685949 - System Time Se<6>[ 18.823440] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
11020 19:28:19.686054 t.
11021 19:28:19.686121
11022 19:28:19.695856 <3>[ 18.832071] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11023 19:28:19.703073 <6>[ 18.835210] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
11024 19:28:19.706235 <6>[ 18.844865] Bluetooth: Core ver 2.22
11025 19:28:19.713373 <6>[ 18.850862] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
11026 19:28:19.720540 <6>[ 18.853231] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
11027 19:28:19.727410 <6>[ 18.860550] NET: Registered PF_BLUETOOTH protocol family
11028 19:28:19.734512 <6>[ 18.870565] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
11029 19:28:19.743939 <4>[ 18.873983] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
11030 19:28:19.751191 <4>[ 18.873993] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
11031 19:28:19.757440 <6>[ 18.880974] Bluetooth: HCI device and connection manager initialized
11032 19:28:19.767621 <6>[ 18.890194] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11033 19:28:19.771118 <6>[ 18.896464] Bluetooth: HCI socket layer initialized
11034 19:28:19.778928 <6>[ 18.896469] Bluetooth: L2CAP socket layer initialized
11035 19:28:19.785505 <6>[ 18.898384] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11036 19:28:19.795139 <6>[ 18.900308] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11037 19:28:19.801990 <6>[ 18.900436] pci 0000:01:00.0: supports D1 D2
11038 19:28:19.808808 <6>[ 18.900454] usbcore: registered new interface driver uvcvideo
11039 19:28:19.815360 <3>[ 18.904345] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11040 19:28:19.822315 <6>[ 18.907857] Bluetooth: SCO socket layer initialized
11041 19:28:19.829129 <6>[ 18.916147] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11042 19:28:19.832826 <6>[ 18.917088] r8152 2-1.3:1.0 eth0: v1.12.13
11043 19:28:19.843077 <3>[ 18.918635] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11044 19:28:19.846381 <6>[ 18.923217] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11045 19:28:19.853317 <6>[ 18.929363] usbcore: registered new interface driver r8152
11046 19:28:19.859428 <6>[ 18.929469] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11047 19:28:19.866065 <6>[ 18.947235] usbcore: registered new interface driver cdc_ether
11048 19:28:19.872993 <6>[ 18.953721] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11049 19:28:19.879996 <6>[ 18.961791] usbcore: registered new interface driver btusb
11050 19:28:19.890243 <4>[ 18.962537] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11051 19:28:19.896788 <3>[ 18.962547] Bluetooth: hci0: Failed to load firmware file (-2)
11052 19:28:19.903486 <3>[ 18.962550] Bluetooth: hci0: Failed to set up firmware (-2)
11053 19:28:19.914143 <4>[ 18.962553] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11054 19:28:19.920855 <6>[ 18.966005] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11055 19:28:19.927843 <6>[ 18.966016] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11056 19:28:19.934676 <6>[ 18.966163] usbcore: registered new interface driver r8153_ecm
11057 19:28:19.944906 <3>[ 18.976231] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11058 19:28:19.948165 <6>[ 18.977239] r8152 2-1.3:1.0 enx002432307852: renamed from eth0
11059 19:28:19.958892 <6>[ 18.978353] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11060 19:28:19.965864 <3>[ 18.991745] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11061 19:28:19.976265 <6>[ 18.995297] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11062 19:28:19.983230 <3>[ 19.042296] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11063 19:28:19.989807 <6>[ 19.047414] pci 0000:00:00.0: PCI bridge to [bus 01]
11064 19:28:19.996288 <6>[ 19.047420] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11065 19:28:20.003270 <6>[ 19.047574] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11066 19:28:20.010477 <3>[ 19.070970] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11067 19:28:20.017118 <6>[ 19.074742] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
11068 19:28:20.023611 Startin<6>[ 19.212289] pcieport 0000:00:00.0: AER: enabled with IRQ 283
11069 19:28:20.030536 g [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11070 19:28:20.030618
11071 19:28:20.052528 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11072 19:28:20.052611
11073 19:28:20.111579 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m<6>[ 19.299141] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11074 19:28:20.120987 - Bluetooth Sup<6>[ 19.307106] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11075 19:28:20.121073 port.
11076 19:28:20.121137
11077 19:28:20.146970 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initiali<6>[ 19.335187] mt7921e 0000:01:00.0: ASIC revision: 79610010
11078 19:28:20.149836 zation.
11079 19:28:20.149911
11080 19:28:20.168821 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11081 19:28:20.168909
11082 19:28:20.191676 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11083 19:28:20.191760
11084 19:28:20.207672 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11085 19:28:20.207782
11086 19:28:20.223265 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11087 19:28:20.223372
11088 19:28:20.239906 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11089 19:28:20.240011
11090 19:28:20.251947 <6>[ 19.438026] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
11091 19:28:20.255107 <6>[ 19.438026]
11092 19:28:20.261990 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11093 19:28:20.262104
11094 19:28:20.279611 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11095 19:28:20.279716
11096 19:28:20.337114 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11097 19:28:20.337289
11098 19:28:20.365501 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11099 19:28:20.365623
11100 19:28:20.385884 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11101 19:28:20.385977
11102 19:28:20.404230 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11103 19:28:20.404337
11104 19:28:20.439785 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11105 19:28:20.439910
11106 19:28:20.480371 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11107 19:28:20.480466
11108 19:28:20.501414 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11109 19:28:20.501501
11110 19:28:20.522953 [[0;32m OK [0m] Reached targ<6>[ 19.707294] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
11111 19:28:20.526410 et [0;1;39mgetty.target[0m - Login Prompts.
11112 19:28:20.526525
11113 19:28:20.547385 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11114 19:28:20.547500
11115 19:28:20.564862 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11116 19:28:20.564956
11117 19:28:20.584628 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11118 19:28:20.584709
11119 19:28:20.605314 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11120 19:28:20.605394
11121 19:28:20.624011 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11122 19:28:20.624096
11123 19:28:20.680798 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11124 19:28:20.680924
11125 19:28:20.720101 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11126 19:28:20.720202
11127 19:28:20.761152
11128 19:28:20.761326
11129 19:28:20.764635 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11130 19:28:20.764715
11131 19:28:20.768212 debian-bookworm-arm64 login: root (automatic login)
11132 19:28:20.768310
11133 19:28:20.768393
11134 19:28:20.778184 Linux debian-bookworm-arm64 6.1.86-cip19 #1 SMP PREEMPT Thu Apr 18 19:05:54 UTC 2024 aarch64
11135 19:28:20.778301
11136 19:28:20.784717 The programs included with the Debian GNU/Linux system are free software;
11137 19:28:20.791822 the exact distribution terms for each program are described in the
11138 19:28:20.795082 individual files in /usr/share/doc/*/copyright.
11139 19:28:20.795163
11140 19:28:20.801921 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11141 19:28:20.805102 permitted by applicable law.
11142 19:28:20.805528 Matched prompt #10: / #
11144 19:28:20.805754 Setting prompt string to ['/ #']
11145 19:28:20.805845 end: 2.2.5.1 login-action (duration 00:00:21) [common]
11147 19:28:20.806044 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
11148 19:28:20.806147 start: 2.2.6 expect-shell-connection (timeout 00:02:53) [common]
11149 19:28:20.806217 Setting prompt string to ['/ #']
11150 19:28:20.806276 Forcing a shell prompt, looking for ['/ #']
11152 19:28:20.856485 / #
11153 19:28:20.856620 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11154 19:28:20.856700 Waiting using forced prompt support (timeout 00:02:30)
11155 19:28:20.861488
11156 19:28:20.861782 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11157 19:28:20.861873 start: 2.2.7 export-device-env (timeout 00:02:53) [common]
11158 19:28:20.861973 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11159 19:28:20.862053 end: 2.2 depthcharge-retry (duration 00:02:07) [common]
11160 19:28:20.862144 end: 2 depthcharge-action (duration 00:02:07) [common]
11161 19:28:20.862262 start: 3 lava-test-retry (timeout 00:07:31) [common]
11162 19:28:20.862386 start: 3.1 lava-test-shell (timeout 00:07:31) [common]
11163 19:28:20.862489 Using namespace: common
11165 19:28:20.962899 / # #
11166 19:28:20.963058 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11167 19:28:20.968528 #
11168 19:28:20.968807 Using /lava-13420397
11170 19:28:21.069120 / # export SHELL=/bin/sh
11171 19:28:21.074422 export SHELL=/bin/sh
11173 19:28:21.174914 / # . /lava-13420397/environment
11174 19:28:21.179914 . /lava-13420397/environment
11176 19:28:21.280401 / # /lava-13420397/bin/lava-test-runner /lava-13420397/0
11177 19:28:21.280554 Test shell timeout: 10s (minimum of the action and connection timeout)
11178 19:28:21.285240 /lava-13420397/bin/lava-test-runner /lava-13420397/0
11179 19:28:21.307763 + export TESTRUN_ID=0_v4l2-compliance-mtk-vcodec-enc
11180 19:28:21.314700 + cd /lava-1<6>[ 20.502574] IPv6: ADDRCONF(NETDEV_CHANGE): enx002432307852: link becomes ready
11181 19:28:21.324892 3420397/0/tests/<6>[ 20.511254] r8152 2-1.3:1.0 enx002432307852: carrier on
11182 19:28:21.324982 0_v4l2-compliance-mtk-vcodec-enc
11183 19:28:21.327887 + cat uuid
11184 19:28:21.327958 + UUID=13420397_1.5.2.3.1
11185 19:28:21.331512 + set +x
11186 19:28:21.338028 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-mtk-vcodec-enc 13420397_1.5.2.3.1>
11187 19:28:21.338283 Received signal: <STARTRUN> 0_v4l2-compliance-mtk-vcodec-enc 13420397_1.5.2.3.1
11188 19:28:21.338354 Starting test lava.0_v4l2-compliance-mtk-vcodec-enc (13420397_1.5.2.3.1)
11189 19:28:21.338441 Skipping test definition patterns.
11190 19:28:21.340860 + /usr/bin/v4l2-parser.sh -d mtk-vcodec-enc
11191 19:28:21.348070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11192 19:28:21.348154 device: /dev/video2
11193 19:28:21.348397 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11195 19:28:21.358520 <4>[ 20.544493] use of bytesused == 0 is deprecated and will be removed in the future,
11196 19:28:21.365355 <4>[ 20.553731] use the actual size instead.
11197 19:28:21.380206 v4l2-compliance 1.27.0-1, 64 bits, 64-bit time_t
11198 19:28:21.392729 v4l2-compliance SHA: a18611d8960<6>[ 20.581410] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11199 19:28:21.396159 f 2024-03-08 13:09:54
11200 19:28:21.396231
11201 19:28:21.408831 Compliance test for mtk-vcodec-enc device /dev/video2:
11202 19:28:21.417319
11203 19:28:21.428876 Driver Info:
11204 19:28:21.444421 Driver name : mtk-vcodec-enc
11205 19:28:21.459047 Card type : MT8192 video encoder
11206 19:28:21.468905 Bus info : platform:17020000.vcodec
11207 19:28:21.475189 Driver version : 6.1.86
11208 19:28:21.485582 Capabilities : 0x84204000
11209 19:28:21.495860 Video Memory-to-Memory Multiplanar
11210 19:28:21.506506 Streaming
11211 19:28:21.522523 Extended Pix Format
11212 19:28:21.532386 Device Capabilities
11213 19:28:21.545377 Device Caps : 0x04204000
11214 19:28:21.555480 Video Memory-to-Memory Multiplanar
11215 19:28:21.566516 Streaming
11216 19:28:21.576539 Extended Pix Format
11217 19:28:21.587073 Detected Stateful Encoder
11218 19:28:21.597425
11219 19:28:21.608806 Required ioctls:
11220 19:28:21.627475 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11221 19:28:21.627566 test VIDIOC_QUERYCAP: OK
11222 19:28:21.627806 Received signal: <TESTSET> START Required-ioctls
11223 19:28:21.627889 Starting test_set Required-ioctls
11224 19:28:21.651190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11225 19:28:21.651443 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11227 19:28:21.654729 test invalid ioctls: OK
11228 19:28:21.674897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11229 19:28:21.674978
11230 19:28:21.675209 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11232 19:28:21.688973 Allow for multiple opens:
11233 19:28:21.695058 <LAVA_SIGNAL_TESTSET STOP>
11234 19:28:21.695319 Received signal: <TESTSET> STOP
11235 19:28:21.695388 Closing test_set Required-ioctls
11236 19:28:21.704844 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11237 19:28:21.705096 Received signal: <TESTSET> START Allow-for-multiple-opens
11238 19:28:21.705171 Starting test_set Allow-for-multiple-opens
11239 19:28:21.707834 test second /dev/video2 open: OK
11240 19:28:21.729010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video2-open RESULT=pass>
11241 19:28:21.729244 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video2-open RESULT=pass
11243 19:28:21.731928 test VIDIOC_QUERYCAP: OK
11244 19:28:21.753675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11245 19:28:21.753933 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11247 19:28:21.756902 test VIDIOC_G/S_PRIORITY: OK
11248 19:28:21.777114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11249 19:28:21.777370 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11251 19:28:21.780376 test for unlimited opens: OK
11252 19:28:21.802468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11253 19:28:21.802557
11254 19:28:21.802797 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11256 19:28:21.817403 Debug ioctls:
11257 19:28:21.825662 <LAVA_SIGNAL_TESTSET STOP>
11258 19:28:21.825918 Received signal: <TESTSET> STOP
11259 19:28:21.825988 Closing test_set Allow-for-multiple-opens
11260 19:28:21.834825 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11261 19:28:21.835070 Received signal: <TESTSET> START Debug-ioctls
11262 19:28:21.835135 Starting test_set Debug-ioctls
11263 19:28:21.837585 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11264 19:28:21.860615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11265 19:28:21.860963 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11267 19:28:21.866470 test VIDIOC_LOG_STATUS: OK (Not Supported)
11268 19:28:21.885708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11269 19:28:21.885901
11270 19:28:21.886190 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11272 19:28:21.895194 Input ioctls:
11273 19:28:21.904364 <LAVA_SIGNAL_TESTSET STOP>
11274 19:28:21.904715 Received signal: <TESTSET> STOP
11275 19:28:21.904807 Closing test_set Debug-ioctls
11276 19:28:21.915836 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11277 19:28:21.916179 Received signal: <TESTSET> START Input-ioctls
11278 19:28:21.916269 Starting test_set Input-ioctls
11279 19:28:21.918811 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11280 19:28:21.945014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11281 19:28:21.945353 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11283 19:28:21.948399 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11284 19:28:21.966137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11285 19:28:21.966486 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11287 19:28:21.973008 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11288 19:28:21.990450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11289 19:28:21.990805 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11291 19:28:21.997062 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11292 19:28:22.015181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11293 19:28:22.015533 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11295 19:28:22.018328 test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
11296 19:28:22.039566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11297 19:28:22.040075 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11299 19:28:22.042912 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11300 19:28:22.064604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11301 19:28:22.065011 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11303 19:28:22.068065 Inputs: 0 Audio Inputs: 0 Tuners: 0
11304 19:28:22.079409
11305 19:28:22.096357 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11306 19:28:22.118318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11307 19:28:22.118674 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11309 19:28:22.124999 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11310 19:28:22.142917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11311 19:28:22.143275 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11313 19:28:22.149296 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11314 19:28:22.171435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11315 19:28:22.171785 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11317 19:28:22.177976 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11318 19:28:22.197094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11319 19:28:22.197504 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11321 19:28:22.203082 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11322 19:28:22.220546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11323 19:28:22.220709
11324 19:28:22.220963 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11326 19:28:22.238483 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11327 19:28:22.259052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11328 19:28:22.259402 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11330 19:28:22.265547 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11331 19:28:22.285702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11332 19:28:22.286046 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11334 19:28:22.288707 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11335 19:28:22.306810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11336 19:28:22.307155 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11338 19:28:22.309628 test VIDIOC_G/S_EDID: OK (Not Supported)
11339 19:28:22.332225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11340 19:28:22.332390
11341 19:28:22.332652 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11343 19:28:22.343877 Control ioctls:
11344 19:28:22.350917 <LAVA_SIGNAL_TESTSET STOP>
11345 19:28:22.351263 Received signal: <TESTSET> STOP
11346 19:28:22.351350 Closing test_set Input-ioctls
11347 19:28:22.360509 <LAVA_SIGNAL_TESTSET START Control-ioctls>
11348 19:28:22.360854 Received signal: <TESTSET> START Control-ioctls
11349 19:28:22.360944 Starting test_set Control-ioctls
11350 19:28:22.363363 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11351 19:28:22.388071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11352 19:28:22.388263 test VIDIOC_QUERYCTRL: OK
11353 19:28:22.388537 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11355 19:28:22.419445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11356 19:28:22.419797 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11358 19:28:22.422212 test VIDIOC_G/S_CTRL: OK
11359 19:28:22.442921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11360 19:28:22.443363 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11362 19:28:22.445964 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11363 19:28:22.470211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11364 19:28:22.470674 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11366 19:28:22.476651 fail: v4l2-test-controls.cpp(1167): node->codec_mask & STATEFUL_ENCODER
11367 19:28:22.484014 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: FAIL
11368 19:28:22.511942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail>
11369 19:28:22.512299 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail
11371 19:28:22.515307 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11372 19:28:22.534329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11373 19:28:22.534682 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11375 19:28:22.537434 Standard Controls: 16 Private Controls: 0
11376 19:28:22.543731
11377 19:28:22.554896 Format ioctls:
11378 19:28:22.565677 <LAVA_SIGNAL_TESTSET STOP>
11379 19:28:22.566030 Received signal: <TESTSET> STOP
11380 19:28:22.566117 Closing test_set Control-ioctls
11381 19:28:22.576541 <LAVA_SIGNAL_TESTSET START Format-ioctls>
11382 19:28:22.576894 Received signal: <TESTSET> START Format-ioctls
11383 19:28:22.576990 Starting test_set Format-ioctls
11384 19:28:22.579667 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11385 19:28:22.609447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11386 19:28:22.609731 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11388 19:28:22.612273 test VIDIOC_G/S_PARM: OK
11389 19:28:22.630412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11390 19:28:22.630670 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11392 19:28:22.633965 test VIDIOC_G_FBUF: OK (Not Supported)
11393 19:28:22.654296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11394 19:28:22.654547 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11396 19:28:22.657735 test VIDIOC_G_FMT: OK
11397 19:28:22.678162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11398 19:28:22.678415 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11400 19:28:22.681130 test VIDIOC_TRY_FMT: OK
11401 19:28:22.701627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11402 19:28:22.701881 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11404 19:28:22.708358 fail: v4l2-test-formats.cpp(924): sel.r.width != fmt.g_width()
11405 19:28:22.711808 test VIDIOC_S_FMT: FAIL
11406 19:28:22.736493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail>
11407 19:28:22.736752 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail
11409 19:28:22.739443 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11410 19:28:22.761302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11411 19:28:22.761592 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11413 19:28:22.764514 test Cropping: OK
11414 19:28:22.786771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11415 19:28:22.787026 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11417 19:28:22.789701 test Composing: OK (Not Supported)
11418 19:28:22.812104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11419 19:28:22.812356 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11421 19:28:22.815350 test Scaling: OK (Not Supported)
11422 19:28:22.837539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11423 19:28:22.837623
11424 19:28:22.837857 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11426 19:28:22.847450 Codec ioctls:
11427 19:28:22.856933 <LAVA_SIGNAL_TESTSET STOP>
11428 19:28:22.857184 Received signal: <TESTSET> STOP
11429 19:28:22.857259 Closing test_set Format-ioctls
11430 19:28:22.868095 <LAVA_SIGNAL_TESTSET START Codec-ioctls>
11431 19:28:22.868346 Received signal: <TESTSET> START Codec-ioctls
11432 19:28:22.868413 Starting test_set Codec-ioctls
11433 19:28:22.871673 test VIDIOC_(TRY_)ENCODER_CMD: OK
11434 19:28:22.893070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11435 19:28:22.893349 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11437 19:28:22.900147 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11438 19:28:22.917602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11439 19:28:22.917854 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11441 19:28:22.923950 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11442 19:28:22.942156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11443 19:28:22.942238
11444 19:28:22.942472 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11446 19:28:22.952578 Buffer ioctls:
11447 19:28:22.963541 <LAVA_SIGNAL_TESTSET STOP>
11448 19:28:22.963791 Received signal: <TESTSET> STOP
11449 19:28:22.963860 Closing test_set Codec-ioctls
11450 19:28:22.972778 <LAVA_SIGNAL_TESTSET START Buffer-ioctls>
11451 19:28:22.973040 Received signal: <TESTSET> START Buffer-ioctls
11452 19:28:22.973110 Starting test_set Buffer-ioctls
11453 19:28:22.976315 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11454 19:28:23.003468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11455 19:28:23.003734 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11457 19:28:23.006518 test CREATE_BUFS maximum buffers: OK
11458 19:28:23.024783 Received signal: <TESTCASE> TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass
11460 19:28:23.028033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass>
11461 19:28:23.028135 test VIDIOC_EXPBUF: OK
11462 19:28:23.048092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11463 19:28:23.048360 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11465 19:28:23.051182 test Requests: OK (Not Supported)
11466 19:28:23.072249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11467 19:28:23.072337
11468 19:28:23.072575 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11470 19:28:23.082271 Test input 0:
11471 19:28:23.095090
11472 19:28:23.108133 Streaming ioctls:
11473 19:28:23.115634 <LAVA_SIGNAL_TESTSET STOP>
11474 19:28:23.115916 Received signal: <TESTSET> STOP
11475 19:28:23.116000 Closing test_set Buffer-ioctls
11476 19:28:23.125087 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11477 19:28:23.125395 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11478 19:28:23.125481 Starting test_set Streaming-ioctls_Test-input-0
11479 19:28:23.129047 test read/write: OK (Not Supported)
11480 19:28:23.150195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11481 19:28:23.150455 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11483 19:28:23.156694 fail: v4l2-test-buffers.cpp(2829): node->streamon(q.g_type())
11484 19:28:23.166650 fail: v4l2-test-buffers.cpp(2876): testBlockingDQBuf(node, q)
11485 19:28:23.175609 test blocking wait: FAIL
11486 19:28:23.199131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=fail>
11487 19:28:23.199433 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=fail
11489 19:28:23.206328 fail: v4l2-test-buffers.cpp(1461): node->streamon(q.g_type())
11490 19:28:23.209202 test MMAP (select): FAIL
11491 19:28:23.237361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11492 19:28:23.237629 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11494 19:28:23.244106 fail: v4l2-test-buffers.cpp(1461): node->streamon(q.g_type())
11495 19:28:23.247755 test MMAP (epoll): FAIL
11496 19:28:23.274344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11497 19:28:23.274608 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11499 19:28:23.280714 fail: v4l2-test-buffers.cpp(1633): ret && ret != ENOTTY (got 22)
11500 19:28:23.290003 fail: v4l2-test-buffers.cpp(1764): setupUserPtr(node, q)
11501 19:28:23.300456 test USERPTR (select): FAIL
11502 19:28:23.325421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=fail>
11503 19:28:23.325696 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=fail
11505 19:28:23.331742 test DMABUF: Cannot test, specify --expbuf-device
11506 19:28:23.335213
11507 19:28:23.353062 Total for mtk-vcodec-enc device /dev/video2: 51, Succeeded: 45, Failed: 6, Warnings: 0
11508 19:28:23.359533 <LAVA_TEST_RUNNER EXIT>
11509 19:28:23.359798 ok: lava_test_shell seems to have completed
11510 19:28:23.359873 Marking unfinished test run as failed
11512 19:28:23.360797 CREATE_BUFS-maximum-buffers:
result: pass
set: Buffer-ioctls
Composing:
result: pass
set: Format-ioctls
Cropping:
result: pass
set: Format-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls
Scaling:
result: pass
set: Format-ioctls
USERPTR-select:
result: fail
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls
VIDIOC_G_FMT:
result: pass
set: Format-ioctls
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls
VIDIOC_S_FMT:
result: fail
set: Format-ioctls
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: fail
set: Control-ioctls
blocking-wait:
result: fail
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video2-open:
result: pass
set: Allow-for-multiple-opens
11513 19:28:23.360919 end: 3.1 lava-test-shell (duration 00:00:02) [common]
11514 19:28:23.361005 end: 3 lava-test-retry (duration 00:00:02) [common]
11515 19:28:23.361094 start: 4 finalize (timeout 00:07:29) [common]
11516 19:28:23.361183 start: 4.1 power-off (timeout 00:00:30) [common]
11517 19:28:23.361343 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=off'
11518 19:28:23.436607 >> Command sent successfully.
11519 19:28:23.439110 Returned 0 in 0 seconds
11520 19:28:23.539487 end: 4.1 power-off (duration 00:00:00) [common]
11522 19:28:23.539929 start: 4.2 read-feedback (timeout 00:07:29) [common]
11523 19:28:23.540228 Listened to connection for namespace 'common' for up to 1s
11524 19:28:24.541161 Finalising connection for namespace 'common'
11525 19:28:24.541414 Disconnecting from shell: Finalise
11526 19:28:24.541499 / #
11527 19:28:24.641796 end: 4.2 read-feedback (duration 00:00:01) [common]
11528 19:28:24.641950 end: 4 finalize (duration 00:00:01) [common]
11529 19:28:24.642060 Cleaning after the job
11530 19:28:24.642164 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13420397/tftp-deploy-49036zue/ramdisk
11531 19:28:24.646680 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13420397/tftp-deploy-49036zue/kernel
11532 19:28:24.653749 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13420397/tftp-deploy-49036zue/dtb
11533 19:28:24.653911 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13420397/tftp-deploy-49036zue/modules
11534 19:28:24.659253 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/13420397
11535 19:28:24.722569 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/13420397
11536 19:28:24.722746 Job finished correctly