Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 23
- Errors: 1
- Kernel Errors: 33
- Boot result: PASS
1 19:22:34.313615 lava-dispatcher, installed at version: 2024.01
2 19:22:34.313800 start: 0 validate
3 19:22:34.313923 Start time: 2024-04-18 19:22:34.313916+00:00 (UTC)
4 19:22:34.314037 Using caching service: 'http://localhost/cache/?uri=%s'
5 19:22:34.314164 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-v4l2%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 19:22:34.575336 Using caching service: 'http://localhost/cache/?uri=%s'
7 19:22:34.576222 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 19:22:59.336348 Using caching service: 'http://localhost/cache/?uri=%s'
9 19:22:59.337134 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 19:22:59.599385 Using caching service: 'http://localhost/cache/?uri=%s'
11 19:22:59.600119 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 19:23:05.857998 validate duration: 31.54
14 19:23:05.858333 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 19:23:05.858509 start: 1.1 download-retry (timeout 00:10:00) [common]
16 19:23:05.858602 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 19:23:05.858719 Not decompressing ramdisk as can be used compressed.
18 19:23:05.858801 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-v4l2/20240313.0/arm64/rootfs.cpio.gz
19 19:23:05.858903 saving as /var/lib/lava/dispatcher/tmp/13420357/tftp-deploy-lhsbc3e1/ramdisk/rootfs.cpio.gz
20 19:23:05.858966 total size: 28105535 (26 MB)
21 19:23:06.126268 progress 0 % (0 MB)
22 19:23:06.133834 progress 5 % (1 MB)
23 19:23:06.141310 progress 10 % (2 MB)
24 19:23:06.148812 progress 15 % (4 MB)
25 19:23:06.156280 progress 20 % (5 MB)
26 19:23:06.163627 progress 25 % (6 MB)
27 19:23:06.170991 progress 30 % (8 MB)
28 19:23:06.178062 progress 35 % (9 MB)
29 19:23:06.185212 progress 40 % (10 MB)
30 19:23:06.192212 progress 45 % (12 MB)
31 19:23:06.199363 progress 50 % (13 MB)
32 19:23:06.206762 progress 55 % (14 MB)
33 19:23:06.214058 progress 60 % (16 MB)
34 19:23:06.221329 progress 65 % (17 MB)
35 19:23:06.228645 progress 70 % (18 MB)
36 19:23:06.235882 progress 75 % (20 MB)
37 19:23:06.243078 progress 80 % (21 MB)
38 19:23:06.250277 progress 85 % (22 MB)
39 19:23:06.257103 progress 90 % (24 MB)
40 19:23:06.264043 progress 95 % (25 MB)
41 19:23:06.270995 progress 100 % (26 MB)
42 19:23:06.271200 26 MB downloaded in 0.41 s (65.02 MB/s)
43 19:23:06.271360 end: 1.1.1 http-download (duration 00:00:00) [common]
45 19:23:06.271600 end: 1.1 download-retry (duration 00:00:00) [common]
46 19:23:06.271688 start: 1.2 download-retry (timeout 00:10:00) [common]
47 19:23:06.271772 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 19:23:06.271906 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 19:23:06.271975 saving as /var/lib/lava/dispatcher/tmp/13420357/tftp-deploy-lhsbc3e1/kernel/Image
50 19:23:06.272037 total size: 54286848 (51 MB)
51 19:23:06.272097 No compression specified
52 19:23:06.273210 progress 0 % (0 MB)
53 19:23:06.286652 progress 5 % (2 MB)
54 19:23:06.300138 progress 10 % (5 MB)
55 19:23:06.313830 progress 15 % (7 MB)
56 19:23:06.327791 progress 20 % (10 MB)
57 19:23:06.341632 progress 25 % (12 MB)
58 19:23:06.355364 progress 30 % (15 MB)
59 19:23:06.368732 progress 35 % (18 MB)
60 19:23:06.382405 progress 40 % (20 MB)
61 19:23:06.395898 progress 45 % (23 MB)
62 19:23:06.409396 progress 50 % (25 MB)
63 19:23:06.423206 progress 55 % (28 MB)
64 19:23:06.437163 progress 60 % (31 MB)
65 19:23:06.450839 progress 65 % (33 MB)
66 19:23:06.464466 progress 70 % (36 MB)
67 19:23:06.477985 progress 75 % (38 MB)
68 19:23:06.491554 progress 80 % (41 MB)
69 19:23:06.505113 progress 85 % (44 MB)
70 19:23:06.518694 progress 90 % (46 MB)
71 19:23:06.532362 progress 95 % (49 MB)
72 19:23:06.546000 progress 100 % (51 MB)
73 19:23:06.546273 51 MB downloaded in 0.27 s (188.79 MB/s)
74 19:23:06.546430 end: 1.2.1 http-download (duration 00:00:00) [common]
76 19:23:06.546656 end: 1.2 download-retry (duration 00:00:00) [common]
77 19:23:06.546743 start: 1.3 download-retry (timeout 00:09:59) [common]
78 19:23:06.546836 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 19:23:06.546981 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 19:23:06.547054 saving as /var/lib/lava/dispatcher/tmp/13420357/tftp-deploy-lhsbc3e1/dtb/mt8192-asurada-spherion-r0.dtb
81 19:23:06.547116 total size: 47230 (0 MB)
82 19:23:06.547177 No compression specified
83 19:23:06.548279 progress 69 % (0 MB)
84 19:23:06.548552 progress 100 % (0 MB)
85 19:23:06.548707 0 MB downloaded in 0.00 s (28.36 MB/s)
86 19:23:06.548829 end: 1.3.1 http-download (duration 00:00:00) [common]
88 19:23:06.549049 end: 1.3 download-retry (duration 00:00:00) [common]
89 19:23:06.549133 start: 1.4 download-retry (timeout 00:09:59) [common]
90 19:23:06.549215 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 19:23:06.549350 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 19:23:06.549433 saving as /var/lib/lava/dispatcher/tmp/13420357/tftp-deploy-lhsbc3e1/modules/modules.tar
93 19:23:06.549493 total size: 8631416 (8 MB)
94 19:23:06.549554 Using unxz to decompress xz
95 19:23:06.553091 progress 0 % (0 MB)
96 19:23:06.571984 progress 5 % (0 MB)
97 19:23:06.596370 progress 10 % (0 MB)
98 19:23:06.620345 progress 15 % (1 MB)
99 19:23:06.643921 progress 20 % (1 MB)
100 19:23:06.668625 progress 25 % (2 MB)
101 19:23:06.694102 progress 30 % (2 MB)
102 19:23:06.717833 progress 35 % (2 MB)
103 19:23:06.743105 progress 40 % (3 MB)
104 19:23:06.766830 progress 45 % (3 MB)
105 19:23:06.791404 progress 50 % (4 MB)
106 19:23:06.815883 progress 55 % (4 MB)
107 19:23:06.843841 progress 60 % (4 MB)
108 19:23:06.868900 progress 65 % (5 MB)
109 19:23:06.893646 progress 70 % (5 MB)
110 19:23:06.917700 progress 75 % (6 MB)
111 19:23:06.943037 progress 80 % (6 MB)
112 19:23:06.968991 progress 85 % (7 MB)
113 19:23:06.997132 progress 90 % (7 MB)
114 19:23:07.025730 progress 95 % (7 MB)
115 19:23:07.051862 progress 100 % (8 MB)
116 19:23:07.057422 8 MB downloaded in 0.51 s (16.21 MB/s)
117 19:23:07.057670 end: 1.4.1 http-download (duration 00:00:01) [common]
119 19:23:07.057928 end: 1.4 download-retry (duration 00:00:01) [common]
120 19:23:07.058024 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 19:23:07.058120 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 19:23:07.058204 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 19:23:07.058293 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 19:23:07.058506 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/13420357/lava-overlay-gnxoc6ji
125 19:23:07.058637 makedir: /var/lib/lava/dispatcher/tmp/13420357/lava-overlay-gnxoc6ji/lava-13420357/bin
126 19:23:07.058756 makedir: /var/lib/lava/dispatcher/tmp/13420357/lava-overlay-gnxoc6ji/lava-13420357/tests
127 19:23:07.058887 makedir: /var/lib/lava/dispatcher/tmp/13420357/lava-overlay-gnxoc6ji/lava-13420357/results
128 19:23:07.059006 Creating /var/lib/lava/dispatcher/tmp/13420357/lava-overlay-gnxoc6ji/lava-13420357/bin/lava-add-keys
129 19:23:07.059149 Creating /var/lib/lava/dispatcher/tmp/13420357/lava-overlay-gnxoc6ji/lava-13420357/bin/lava-add-sources
130 19:23:07.059278 Creating /var/lib/lava/dispatcher/tmp/13420357/lava-overlay-gnxoc6ji/lava-13420357/bin/lava-background-process-start
131 19:23:07.059406 Creating /var/lib/lava/dispatcher/tmp/13420357/lava-overlay-gnxoc6ji/lava-13420357/bin/lava-background-process-stop
132 19:23:07.059527 Creating /var/lib/lava/dispatcher/tmp/13420357/lava-overlay-gnxoc6ji/lava-13420357/bin/lava-common-functions
133 19:23:07.059649 Creating /var/lib/lava/dispatcher/tmp/13420357/lava-overlay-gnxoc6ji/lava-13420357/bin/lava-echo-ipv4
134 19:23:07.059774 Creating /var/lib/lava/dispatcher/tmp/13420357/lava-overlay-gnxoc6ji/lava-13420357/bin/lava-install-packages
135 19:23:07.059896 Creating /var/lib/lava/dispatcher/tmp/13420357/lava-overlay-gnxoc6ji/lava-13420357/bin/lava-installed-packages
136 19:23:07.060016 Creating /var/lib/lava/dispatcher/tmp/13420357/lava-overlay-gnxoc6ji/lava-13420357/bin/lava-os-build
137 19:23:07.060136 Creating /var/lib/lava/dispatcher/tmp/13420357/lava-overlay-gnxoc6ji/lava-13420357/bin/lava-probe-channel
138 19:23:07.060255 Creating /var/lib/lava/dispatcher/tmp/13420357/lava-overlay-gnxoc6ji/lava-13420357/bin/lava-probe-ip
139 19:23:07.060376 Creating /var/lib/lava/dispatcher/tmp/13420357/lava-overlay-gnxoc6ji/lava-13420357/bin/lava-target-ip
140 19:23:07.060497 Creating /var/lib/lava/dispatcher/tmp/13420357/lava-overlay-gnxoc6ji/lava-13420357/bin/lava-target-mac
141 19:23:07.060617 Creating /var/lib/lava/dispatcher/tmp/13420357/lava-overlay-gnxoc6ji/lava-13420357/bin/lava-target-storage
142 19:23:07.060741 Creating /var/lib/lava/dispatcher/tmp/13420357/lava-overlay-gnxoc6ji/lava-13420357/bin/lava-test-case
143 19:23:07.060861 Creating /var/lib/lava/dispatcher/tmp/13420357/lava-overlay-gnxoc6ji/lava-13420357/bin/lava-test-event
144 19:23:07.060980 Creating /var/lib/lava/dispatcher/tmp/13420357/lava-overlay-gnxoc6ji/lava-13420357/bin/lava-test-feedback
145 19:23:07.061100 Creating /var/lib/lava/dispatcher/tmp/13420357/lava-overlay-gnxoc6ji/lava-13420357/bin/lava-test-raise
146 19:23:07.061221 Creating /var/lib/lava/dispatcher/tmp/13420357/lava-overlay-gnxoc6ji/lava-13420357/bin/lava-test-reference
147 19:23:07.061383 Creating /var/lib/lava/dispatcher/tmp/13420357/lava-overlay-gnxoc6ji/lava-13420357/bin/lava-test-runner
148 19:23:07.061504 Creating /var/lib/lava/dispatcher/tmp/13420357/lava-overlay-gnxoc6ji/lava-13420357/bin/lava-test-set
149 19:23:07.061626 Creating /var/lib/lava/dispatcher/tmp/13420357/lava-overlay-gnxoc6ji/lava-13420357/bin/lava-test-shell
150 19:23:07.061750 Updating /var/lib/lava/dispatcher/tmp/13420357/lava-overlay-gnxoc6ji/lava-13420357/bin/lava-install-packages (oe)
151 19:23:07.061898 Updating /var/lib/lava/dispatcher/tmp/13420357/lava-overlay-gnxoc6ji/lava-13420357/bin/lava-installed-packages (oe)
152 19:23:07.062018 Creating /var/lib/lava/dispatcher/tmp/13420357/lava-overlay-gnxoc6ji/lava-13420357/environment
153 19:23:07.062116 LAVA metadata
154 19:23:07.062192 - LAVA_JOB_ID=13420357
155 19:23:07.062257 - LAVA_DISPATCHER_IP=192.168.201.1
156 19:23:07.062360 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 19:23:07.062428 skipped lava-vland-overlay
158 19:23:07.062503 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 19:23:07.062585 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 19:23:07.062650 skipped lava-multinode-overlay
161 19:23:07.062726 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 19:23:07.062825 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 19:23:07.062903 Loading test definitions
164 19:23:07.062996 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 19:23:07.063072 Using /lava-13420357 at stage 0
166 19:23:07.063366 uuid=13420357_1.5.2.3.1 testdef=None
167 19:23:07.063455 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 19:23:07.063544 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 19:23:07.064046 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 19:23:07.064268 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 19:23:07.064868 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 19:23:07.065101 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 19:23:07.065721 runner path: /var/lib/lava/dispatcher/tmp/13420357/lava-overlay-gnxoc6ji/lava-13420357/0/tests/0_v4l2-compliance-uvc test_uuid 13420357_1.5.2.3.1
176 19:23:07.065879 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 19:23:07.066088 Creating lava-test-runner.conf files
179 19:23:07.066152 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/13420357/lava-overlay-gnxoc6ji/lava-13420357/0 for stage 0
180 19:23:07.066241 - 0_v4l2-compliance-uvc
181 19:23:07.066337 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 19:23:07.066423 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 19:23:07.073629 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 19:23:07.073740 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 19:23:07.073830 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 19:23:07.073919 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 19:23:07.074006 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 19:23:07.935234 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 19:23:07.935603 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 19:23:07.935712 extracting modules file /var/lib/lava/dispatcher/tmp/13420357/tftp-deploy-lhsbc3e1/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13420357/extract-overlay-ramdisk-mcmi20fe/ramdisk
191 19:23:08.144516 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 19:23:08.144685 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 19:23:08.144785 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13420357/compress-overlay-8vvd5q6y/overlay-1.5.2.4.tar.gz to ramdisk
194 19:23:08.144858 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13420357/compress-overlay-8vvd5q6y/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/13420357/extract-overlay-ramdisk-mcmi20fe/ramdisk
195 19:23:08.151300 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 19:23:08.151424 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 19:23:08.151520 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 19:23:08.151613 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 19:23:08.151694 Building ramdisk /var/lib/lava/dispatcher/tmp/13420357/extract-overlay-ramdisk-mcmi20fe/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/13420357/extract-overlay-ramdisk-mcmi20fe/ramdisk
200 19:23:08.851884 >> 276170 blocks
201 19:23:12.892577 rename /var/lib/lava/dispatcher/tmp/13420357/extract-overlay-ramdisk-mcmi20fe/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/13420357/tftp-deploy-lhsbc3e1/ramdisk/ramdisk.cpio.gz
202 19:23:12.892995 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 19:23:12.893122 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 19:23:12.893226 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 19:23:12.893370 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/13420357/tftp-deploy-lhsbc3e1/kernel/Image'
206 19:23:25.861600 Returned 0 in 12 seconds
207 19:23:25.962204 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/13420357/tftp-deploy-lhsbc3e1/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/13420357/tftp-deploy-lhsbc3e1/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/13420357/tftp-deploy-lhsbc3e1/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/13420357/tftp-deploy-lhsbc3e1/kernel/image.itb
208 19:23:26.556250 output: FIT description: Kernel Image image with one or more FDT blobs
209 19:23:26.556598 output: Created: Thu Apr 18 20:23:26 2024
210 19:23:26.556701 output: Image 0 (kernel-1)
211 19:23:26.556787 output: Description:
212 19:23:26.556872 output: Created: Thu Apr 18 20:23:26 2024
213 19:23:26.556955 output: Type: Kernel Image
214 19:23:26.557036 output: Compression: lzma compressed
215 19:23:26.557118 output: Data Size: 12910355 Bytes = 12607.77 KiB = 12.31 MiB
216 19:23:26.557219 output: Architecture: AArch64
217 19:23:26.557324 output: OS: Linux
218 19:23:26.557426 output: Load Address: 0x00000000
219 19:23:26.557524 output: Entry Point: 0x00000000
220 19:23:26.557623 output: Hash algo: crc32
221 19:23:26.557721 output: Hash value: bbac8b0b
222 19:23:26.557816 output: Image 1 (fdt-1)
223 19:23:26.557912 output: Description: mt8192-asurada-spherion-r0
224 19:23:26.558008 output: Created: Thu Apr 18 20:23:26 2024
225 19:23:26.558102 output: Type: Flat Device Tree
226 19:23:26.558195 output: Compression: uncompressed
227 19:23:26.558289 output: Data Size: 47230 Bytes = 46.12 KiB = 0.05 MiB
228 19:23:26.558383 output: Architecture: AArch64
229 19:23:26.558476 output: Hash algo: crc32
230 19:23:26.558570 output: Hash value: 4bf0d1ac
231 19:23:26.558663 output: Image 2 (ramdisk-1)
232 19:23:26.558756 output: Description: unavailable
233 19:23:26.558850 output: Created: Thu Apr 18 20:23:26 2024
234 19:23:26.558943 output: Type: RAMDisk Image
235 19:23:26.559036 output: Compression: Unknown Compression
236 19:23:26.559130 output: Data Size: 41256090 Bytes = 40289.15 KiB = 39.34 MiB
237 19:23:26.559224 output: Architecture: AArch64
238 19:23:26.559317 output: OS: Linux
239 19:23:26.559416 output: Load Address: unavailable
240 19:23:26.559510 output: Entry Point: unavailable
241 19:23:26.559603 output: Hash algo: crc32
242 19:23:26.559695 output: Hash value: 2a4b7073
243 19:23:26.559788 output: Default Configuration: 'conf-1'
244 19:23:26.559881 output: Configuration 0 (conf-1)
245 19:23:26.559974 output: Description: mt8192-asurada-spherion-r0
246 19:23:26.560067 output: Kernel: kernel-1
247 19:23:26.560159 output: Init Ramdisk: ramdisk-1
248 19:23:26.560251 output: FDT: fdt-1
249 19:23:26.560344 output: Loadables: kernel-1
250 19:23:26.560436 output:
251 19:23:26.560675 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 19:23:26.560816 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 19:23:26.560965 end: 1.5 prepare-tftp-overlay (duration 00:00:20) [common]
254 19:23:26.561106 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:39) [common]
255 19:23:26.561223 No LXC device requested
256 19:23:26.561385 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 19:23:26.561495 start: 1.7 deploy-device-env (timeout 00:09:39) [common]
258 19:23:26.561590 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 19:23:26.561673 Checking files for TFTP limit of 4294967296 bytes.
260 19:23:26.562180 end: 1 tftp-deploy (duration 00:00:21) [common]
261 19:23:26.562294 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 19:23:26.562404 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 19:23:26.562582 substitutions:
264 19:23:26.562684 - {DTB}: 13420357/tftp-deploy-lhsbc3e1/dtb/mt8192-asurada-spherion-r0.dtb
265 19:23:26.562765 - {INITRD}: 13420357/tftp-deploy-lhsbc3e1/ramdisk/ramdisk.cpio.gz
266 19:23:26.562846 - {KERNEL}: 13420357/tftp-deploy-lhsbc3e1/kernel/Image
267 19:23:26.562924 - {LAVA_MAC}: None
268 19:23:26.563002 - {PRESEED_CONFIG}: None
269 19:23:26.563079 - {PRESEED_LOCAL}: None
270 19:23:26.563176 - {RAMDISK}: 13420357/tftp-deploy-lhsbc3e1/ramdisk/ramdisk.cpio.gz
271 19:23:26.563272 - {ROOT_PART}: None
272 19:23:26.563368 - {ROOT}: None
273 19:23:26.563465 - {SERVER_IP}: 192.168.201.1
274 19:23:26.563560 - {TEE}: None
275 19:23:26.563656 Parsed boot commands:
276 19:23:26.563750 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 19:23:26.563980 Parsed boot commands: tftpboot 192.168.201.1 13420357/tftp-deploy-lhsbc3e1/kernel/image.itb 13420357/tftp-deploy-lhsbc3e1/kernel/cmdline
278 19:23:26.564109 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 19:23:26.564241 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 19:23:26.564382 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 19:23:26.564513 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 19:23:26.564623 Not connected, no need to disconnect.
283 19:23:26.564743 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 19:23:26.564872 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 19:23:26.564977 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
286 19:23:26.568596 Setting prompt string to ['lava-test: # ']
287 19:23:26.568940 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 19:23:26.569062 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 19:23:26.569192 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 19:23:26.569335 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 19:23:26.569565 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
292 19:23:31.701656 >> Command sent successfully.
293 19:23:31.704006 Returned 0 in 5 seconds
294 19:23:31.804430 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 19:23:31.804793 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 19:23:31.804905 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 19:23:31.805001 Setting prompt string to 'Starting depthcharge on Spherion...'
299 19:23:31.805078 Changing prompt to 'Starting depthcharge on Spherion...'
300 19:23:31.805187 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 19:23:31.805566 [Enter `^Ec?' for help]
302 19:23:31.977632
303 19:23:31.977798
304 19:23:31.977898 F0: 102B 0000
305 19:23:31.977980
306 19:23:31.978060 F3: 1001 0000 [0200]
307 19:23:31.978138
308 19:23:31.981052 F3: 1001 0000
309 19:23:31.981139
310 19:23:31.981241 F7: 102D 0000
311 19:23:31.981374
312 19:23:31.983833 F1: 0000 0000
313 19:23:31.983968
314 19:23:31.984069 V0: 0000 0000 [0001]
315 19:23:31.984149
316 19:23:31.987418 00: 0007 8000
317 19:23:31.987521
318 19:23:31.987600 01: 0000 0000
319 19:23:31.987678
320 19:23:31.990641 BP: 0C00 0209 [0000]
321 19:23:31.990727
322 19:23:31.990812 G0: 1182 0000
323 19:23:31.990893
324 19:23:31.990971 EC: 0000 0021 [4000]
325 19:23:31.994187
326 19:23:31.994272 S7: 0000 0000 [0000]
327 19:23:31.994357
328 19:23:31.997738 CC: 0000 0000 [0001]
329 19:23:31.997826
330 19:23:31.997911 T0: 0000 0040 [010F]
331 19:23:31.997991
332 19:23:31.998070 Jump to BL
333 19:23:31.998148
334 19:23:32.024772
335 19:23:32.024934
336 19:23:32.025026
337 19:23:32.031527 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 19:23:32.034811 ARM64: Exception handlers installed.
339 19:23:32.038977 ARM64: Testing exception
340 19:23:32.041949 ARM64: Done test exception
341 19:23:32.048733 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 19:23:32.058982 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 19:23:32.066144 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 19:23:32.076179 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 19:23:32.082868 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 19:23:32.089550 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 19:23:32.100909 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 19:23:32.107971 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 19:23:32.126981 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 19:23:32.130775 WDT: Last reset was cold boot
351 19:23:32.134023 SPI1(PAD0) initialized at 2873684 Hz
352 19:23:32.137310 SPI5(PAD0) initialized at 992727 Hz
353 19:23:32.140487 VBOOT: Loading verstage.
354 19:23:32.147146 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 19:23:32.150584 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 19:23:32.153708 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 19:23:32.157106 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 19:23:32.164551 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 19:23:32.171296 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 19:23:32.181884 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
361 19:23:32.182027
362 19:23:32.182098
363 19:23:32.192048 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 19:23:32.195695 ARM64: Exception handlers installed.
365 19:23:32.198808 ARM64: Testing exception
366 19:23:32.198901 ARM64: Done test exception
367 19:23:32.205410 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 19:23:32.209170 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 19:23:32.223166 Probing TPM: . done!
370 19:23:32.223305 TPM ready after 0 ms
371 19:23:32.229872 Connected to device vid:did:rid of 1ae0:0028:00
372 19:23:32.236945 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 19:23:32.294635 Initialized TPM device CR50 revision 0
374 19:23:32.305275 tlcl_send_startup: Startup return code is 0
375 19:23:32.305459 TPM: setup succeeded
376 19:23:32.316424 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 19:23:32.325110 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 19:23:32.335664 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 19:23:32.344846 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 19:23:32.348082 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 19:23:32.356142 in-header: 03 07 00 00 08 00 00 00
382 19:23:32.360190 in-data: aa e4 47 04 13 02 00 00
383 19:23:32.363794 Chrome EC: UHEPI supported
384 19:23:32.370898 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 19:23:32.374728 in-header: 03 ad 00 00 08 00 00 00
386 19:23:32.378569 in-data: 00 20 20 08 00 00 00 00
387 19:23:32.378672 Phase 1
388 19:23:32.382657 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 19:23:32.389608 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 19:23:32.393717 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 19:23:32.398033 Recovery requested (1009000e)
392 19:23:32.406430 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 19:23:32.411788 tlcl_extend: response is 0
394 19:23:32.421203 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 19:23:32.426916 tlcl_extend: response is 0
396 19:23:32.434026 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 19:23:32.454367 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 19:23:32.461447 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 19:23:32.461576
400 19:23:32.461645
401 19:23:32.471513 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 19:23:32.474798 ARM64: Exception handlers installed.
403 19:23:32.474899 ARM64: Testing exception
404 19:23:32.478030 ARM64: Done test exception
405 19:23:32.499624 pmic_efuse_setting: Set efuses in 11 msecs
406 19:23:32.503024 pmwrap_interface_init: Select PMIF_VLD_RDY
407 19:23:32.509747 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 19:23:32.513262 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 19:23:32.517079 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 19:23:32.523792 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 19:23:32.527404 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 19:23:32.534471 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 19:23:32.537934 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 19:23:32.541841 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 19:23:32.549023 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 19:23:32.552772 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 19:23:32.556308 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 19:23:32.559599 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 19:23:32.566207 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 19:23:32.573089 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 19:23:32.576355 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 19:23:32.583453 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 19:23:32.590489 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 19:23:32.594145 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 19:23:32.601555 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 19:23:32.604580 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 19:23:32.612012 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 19:23:32.615425 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 19:23:32.622000 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 19:23:32.628885 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 19:23:32.632511 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 19:23:32.638779 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 19:23:32.642023 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 19:23:32.648818 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 19:23:32.652553 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 19:23:32.658820 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 19:23:32.662078 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 19:23:32.668761 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 19:23:32.672498 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 19:23:32.678866 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 19:23:32.682637 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 19:23:32.688925 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 19:23:32.692131 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 19:23:32.699260 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 19:23:32.702628 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 19:23:32.706398 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 19:23:32.710215 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 19:23:32.716932 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 19:23:32.719874 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 19:23:32.723426 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 19:23:32.730150 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 19:23:32.733451 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 19:23:32.737007 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 19:23:32.740116 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 19:23:32.746721 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 19:23:32.750012 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 19:23:32.753438 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 19:23:32.763339 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 19:23:32.770104 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 19:23:32.773422 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 19:23:32.783526 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 19:23:32.790704 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 19:23:32.797241 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 19:23:32.800368 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 19:23:32.803632 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 19:23:32.811876 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
467 19:23:32.818650 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 19:23:32.821704 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 19:23:32.825222 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 19:23:32.836650 [RTC]rtc_get_frequency_meter,154: input=15, output=772
471 19:23:32.845803 [RTC]rtc_get_frequency_meter,154: input=23, output=958
472 19:23:32.855363 [RTC]rtc_get_frequency_meter,154: input=19, output=865
473 19:23:32.864990 [RTC]rtc_get_frequency_meter,154: input=17, output=818
474 19:23:32.874297 [RTC]rtc_get_frequency_meter,154: input=16, output=796
475 19:23:32.877754 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
476 19:23:32.884886 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
477 19:23:32.887688 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
478 19:23:32.891178 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
479 19:23:32.894599 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
480 19:23:32.897986 ADC[4]: Raw value=902876 ID=7
481 19:23:32.901251 ADC[3]: Raw value=213179 ID=1
482 19:23:32.901347 RAM Code: 0x71
483 19:23:32.907676 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
484 19:23:32.910965 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
485 19:23:32.921108 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
486 19:23:32.927985 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
487 19:23:32.931028 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
488 19:23:32.934812 in-header: 03 07 00 00 08 00 00 00
489 19:23:32.937559 in-data: aa e4 47 04 13 02 00 00
490 19:23:32.940944 Chrome EC: UHEPI supported
491 19:23:32.947629 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
492 19:23:32.950763 in-header: 03 ed 00 00 08 00 00 00
493 19:23:32.954452 in-data: 80 20 60 08 00 00 00 00
494 19:23:32.957687 MRC: failed to locate region type 0.
495 19:23:32.964209 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
496 19:23:32.967601 DRAM-K: Running full calibration
497 19:23:32.971309 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
498 19:23:32.974458 header.status = 0x0
499 19:23:32.977840 header.version = 0x6 (expected: 0x6)
500 19:23:32.981098 header.size = 0xd00 (expected: 0xd00)
501 19:23:32.984247 header.flags = 0x0
502 19:23:32.987485 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
503 19:23:33.006499 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
504 19:23:33.013340 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
505 19:23:33.016761 dram_init: ddr_geometry: 2
506 19:23:33.019808 [EMI] MDL number = 2
507 19:23:33.019898 [EMI] Get MDL freq = 0
508 19:23:33.023512 dram_init: ddr_type: 0
509 19:23:33.023600 is_discrete_lpddr4: 1
510 19:23:33.026750 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
511 19:23:33.026837
512 19:23:33.026904
513 19:23:33.029987 [Bian_co] ETT version 0.0.0.1
514 19:23:33.036796 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
515 19:23:33.036903
516 19:23:33.039739 dramc_set_vcore_voltage set vcore to 650000
517 19:23:33.039827 Read voltage for 800, 4
518 19:23:33.043412 Vio18 = 0
519 19:23:33.043501 Vcore = 650000
520 19:23:33.043569 Vdram = 0
521 19:23:33.046580 Vddq = 0
522 19:23:33.046668 Vmddr = 0
523 19:23:33.049841 dram_init: config_dvfs: 1
524 19:23:33.053745 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
525 19:23:33.060816 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
526 19:23:33.064864 [SwImpedanceCal] DRVP=9, DRVN=15, ODTN=9
527 19:23:33.068648 freq_region=0, Reg: DRVP=9, DRVN=15, ODTN=9
528 19:23:33.072247 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
529 19:23:33.075679 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
530 19:23:33.075782 MEM_TYPE=3, freq_sel=18
531 19:23:33.079380 sv_algorithm_assistance_LP4_1600
532 19:23:33.083312 ============ PULL DRAM RESETB DOWN ============
533 19:23:33.086726 ========== PULL DRAM RESETB DOWN end =========
534 19:23:33.094489 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
535 19:23:33.098239 ===================================
536 19:23:33.098352 LPDDR4 DRAM CONFIGURATION
537 19:23:33.101804 ===================================
538 19:23:33.106200 EX_ROW_EN[0] = 0x0
539 19:23:33.106299 EX_ROW_EN[1] = 0x0
540 19:23:33.106367 LP4Y_EN = 0x0
541 19:23:33.109705 WORK_FSP = 0x0
542 19:23:33.109794 WL = 0x2
543 19:23:33.113341 RL = 0x2
544 19:23:33.113430 BL = 0x2
545 19:23:33.116634 RPST = 0x0
546 19:23:33.116722 RD_PRE = 0x0
547 19:23:33.120032 WR_PRE = 0x1
548 19:23:33.120120 WR_PST = 0x0
549 19:23:33.123347 DBI_WR = 0x0
550 19:23:33.123432 DBI_RD = 0x0
551 19:23:33.126618 OTF = 0x1
552 19:23:33.129995 ===================================
553 19:23:33.133460 ===================================
554 19:23:33.133550 ANA top config
555 19:23:33.136782 ===================================
556 19:23:33.140120 DLL_ASYNC_EN = 0
557 19:23:33.143459 ALL_SLAVE_EN = 1
558 19:23:33.146603 NEW_RANK_MODE = 1
559 19:23:33.146701 DLL_IDLE_MODE = 1
560 19:23:33.149911 LP45_APHY_COMB_EN = 1
561 19:23:33.153365 TX_ODT_DIS = 1
562 19:23:33.156736 NEW_8X_MODE = 1
563 19:23:33.160176 ===================================
564 19:23:33.163268 ===================================
565 19:23:33.166759 data_rate = 1600
566 19:23:33.166852 CKR = 1
567 19:23:33.170242 DQ_P2S_RATIO = 8
568 19:23:33.174171 ===================================
569 19:23:33.178115 CA_P2S_RATIO = 8
570 19:23:33.178214 DQ_CA_OPEN = 0
571 19:23:33.181750 DQ_SEMI_OPEN = 0
572 19:23:33.185208 CA_SEMI_OPEN = 0
573 19:23:33.188510 CA_FULL_RATE = 0
574 19:23:33.192347 DQ_CKDIV4_EN = 1
575 19:23:33.192443 CA_CKDIV4_EN = 1
576 19:23:33.196005 CA_PREDIV_EN = 0
577 19:23:33.199586 PH8_DLY = 0
578 19:23:33.202914 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
579 19:23:33.203004 DQ_AAMCK_DIV = 4
580 19:23:33.206274 CA_AAMCK_DIV = 4
581 19:23:33.209796 CA_ADMCK_DIV = 4
582 19:23:33.212619 DQ_TRACK_CA_EN = 0
583 19:23:33.216247 CA_PICK = 800
584 19:23:33.219321 CA_MCKIO = 800
585 19:23:33.219411 MCKIO_SEMI = 0
586 19:23:33.223117 PLL_FREQ = 3068
587 19:23:33.226390 DQ_UI_PI_RATIO = 32
588 19:23:33.229669 CA_UI_PI_RATIO = 0
589 19:23:33.232994 ===================================
590 19:23:33.236174 ===================================
591 19:23:33.239566 memory_type:LPDDR4
592 19:23:33.239658 GP_NUM : 10
593 19:23:33.242865 SRAM_EN : 1
594 19:23:33.246300 MD32_EN : 0
595 19:23:33.249968 ===================================
596 19:23:33.250063 [ANA_INIT] >>>>>>>>>>>>>>
597 19:23:33.253652 <<<<<< [CONFIGURE PHASE]: ANA_TX
598 19:23:33.257651 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
599 19:23:33.261043 ===================================
600 19:23:33.264962 data_rate = 1600,PCW = 0X7600
601 19:23:33.265058 ===================================
602 19:23:33.268627 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
603 19:23:33.275773 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
604 19:23:33.279378 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
605 19:23:33.287016 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
606 19:23:33.290274 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
607 19:23:33.293498 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
608 19:23:33.293590 [ANA_INIT] flow start
609 19:23:33.296903 [ANA_INIT] PLL >>>>>>>>
610 19:23:33.296990 [ANA_INIT] PLL <<<<<<<<
611 19:23:33.300314 [ANA_INIT] MIDPI >>>>>>>>
612 19:23:33.303770 [ANA_INIT] MIDPI <<<<<<<<
613 19:23:33.307160 [ANA_INIT] DLL >>>>>>>>
614 19:23:33.307248 [ANA_INIT] flow end
615 19:23:33.310579 ============ LP4 DIFF to SE enter ============
616 19:23:33.316839 ============ LP4 DIFF to SE exit ============
617 19:23:33.316935 [ANA_INIT] <<<<<<<<<<<<<
618 19:23:33.320110 [Flow] Enable top DCM control >>>>>
619 19:23:33.323848 [Flow] Enable top DCM control <<<<<
620 19:23:33.327340 Enable DLL master slave shuffle
621 19:23:33.333476 ==============================================================
622 19:23:33.333579 Gating Mode config
623 19:23:33.340593 ==============================================================
624 19:23:33.343474 Config description:
625 19:23:33.353466 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
626 19:23:33.360153 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
627 19:23:33.363687 SELPH_MODE 0: By rank 1: By Phase
628 19:23:33.370214 ==============================================================
629 19:23:33.373471 GAT_TRACK_EN = 1
630 19:23:33.373584 RX_GATING_MODE = 2
631 19:23:33.377139 RX_GATING_TRACK_MODE = 2
632 19:23:33.380299 SELPH_MODE = 1
633 19:23:33.383610 PICG_EARLY_EN = 1
634 19:23:33.386811 VALID_LAT_VALUE = 1
635 19:23:33.393581 ==============================================================
636 19:23:33.396997 Enter into Gating configuration >>>>
637 19:23:33.400388 Exit from Gating configuration <<<<
638 19:23:33.403431 Enter into DVFS_PRE_config >>>>>
639 19:23:33.413739 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
640 19:23:33.417063 Exit from DVFS_PRE_config <<<<<
641 19:23:33.420360 Enter into PICG configuration >>>>
642 19:23:33.423604 Exit from PICG configuration <<<<
643 19:23:33.426838 [RX_INPUT] configuration >>>>>
644 19:23:33.426928 [RX_INPUT] configuration <<<<<
645 19:23:33.433730 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
646 19:23:33.440414 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
647 19:23:33.443647 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
648 19:23:33.450451 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
649 19:23:33.457231 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
650 19:23:33.463595 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
651 19:23:33.467349 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
652 19:23:33.470179 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
653 19:23:33.477624 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
654 19:23:33.481017 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
655 19:23:33.484432 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
656 19:23:33.487962 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
657 19:23:33.491162 ===================================
658 19:23:33.494447 LPDDR4 DRAM CONFIGURATION
659 19:23:33.497688 ===================================
660 19:23:33.501079 EX_ROW_EN[0] = 0x0
661 19:23:33.501172 EX_ROW_EN[1] = 0x0
662 19:23:33.504451 LP4Y_EN = 0x0
663 19:23:33.504537 WORK_FSP = 0x0
664 19:23:33.507485 WL = 0x2
665 19:23:33.507570 RL = 0x2
666 19:23:33.511160 BL = 0x2
667 19:23:33.511249 RPST = 0x0
668 19:23:33.514525 RD_PRE = 0x0
669 19:23:33.514611 WR_PRE = 0x1
670 19:23:33.517524 WR_PST = 0x0
671 19:23:33.517623 DBI_WR = 0x0
672 19:23:33.521325 DBI_RD = 0x0
673 19:23:33.521425 OTF = 0x1
674 19:23:33.524665 ===================================
675 19:23:33.528017 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
676 19:23:33.534474 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
677 19:23:33.537730 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
678 19:23:33.541007 ===================================
679 19:23:33.544293 LPDDR4 DRAM CONFIGURATION
680 19:23:33.547711 ===================================
681 19:23:33.547805 EX_ROW_EN[0] = 0x10
682 19:23:33.551223 EX_ROW_EN[1] = 0x0
683 19:23:33.551313 LP4Y_EN = 0x0
684 19:23:33.554609 WORK_FSP = 0x0
685 19:23:33.554697 WL = 0x2
686 19:23:33.557805 RL = 0x2
687 19:23:33.557892 BL = 0x2
688 19:23:33.561180 RPST = 0x0
689 19:23:33.565014 RD_PRE = 0x0
690 19:23:33.565106 WR_PRE = 0x1
691 19:23:33.568310 WR_PST = 0x0
692 19:23:33.568396 DBI_WR = 0x0
693 19:23:33.571649 DBI_RD = 0x0
694 19:23:33.571737 OTF = 0x1
695 19:23:33.574621 ===================================
696 19:23:33.581159 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
697 19:23:33.585056 nWR fixed to 40
698 19:23:33.588554 [ModeRegInit_LP4] CH0 RK0
699 19:23:33.588646 [ModeRegInit_LP4] CH0 RK1
700 19:23:33.591744 [ModeRegInit_LP4] CH1 RK0
701 19:23:33.595205 [ModeRegInit_LP4] CH1 RK1
702 19:23:33.595293 match AC timing 13
703 19:23:33.601702 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
704 19:23:33.605117 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
705 19:23:33.608449 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
706 19:23:33.615336 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
707 19:23:33.618224 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
708 19:23:33.618320 [EMI DOE] emi_dcm 0
709 19:23:33.625062 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
710 19:23:33.625163 ==
711 19:23:33.628347 Dram Type= 6, Freq= 0, CH_0, rank 0
712 19:23:33.631729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
713 19:23:33.631819 ==
714 19:23:33.638411 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
715 19:23:33.641827 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
716 19:23:33.652429 [CA 0] Center 37 (7~68) winsize 62
717 19:23:33.656102 [CA 1] Center 38 (7~69) winsize 63
718 19:23:33.659500 [CA 2] Center 35 (5~66) winsize 62
719 19:23:33.662840 [CA 3] Center 35 (4~66) winsize 63
720 19:23:33.666284 [CA 4] Center 34 (4~65) winsize 62
721 19:23:33.669172 [CA 5] Center 33 (3~64) winsize 62
722 19:23:33.669262
723 19:23:33.672850 [CmdBusTrainingLP45] Vref(ca) range 1: 34
724 19:23:33.672953
725 19:23:33.676675 [CATrainingPosCal] consider 1 rank data
726 19:23:33.680740 u2DelayCellTimex100 = 270/100 ps
727 19:23:33.684161 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
728 19:23:33.687727 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
729 19:23:33.691593 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
730 19:23:33.694984 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
731 19:23:33.698800 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
732 19:23:33.702339 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
733 19:23:33.702434
734 19:23:33.706251 CA PerBit enable=1, Macro0, CA PI delay=33
735 19:23:33.706340
736 19:23:33.709653 [CBTSetCACLKResult] CA Dly = 33
737 19:23:33.709741 CS Dly: 6 (0~37)
738 19:23:33.709808 ==
739 19:23:33.713052 Dram Type= 6, Freq= 0, CH_0, rank 1
740 19:23:33.716555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
741 19:23:33.720333 ==
742 19:23:33.723590 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
743 19:23:33.730703 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
744 19:23:33.739291 [CA 0] Center 38 (7~69) winsize 63
745 19:23:33.743214 [CA 1] Center 38 (7~69) winsize 63
746 19:23:33.746838 [CA 2] Center 36 (6~67) winsize 62
747 19:23:33.750956 [CA 3] Center 35 (5~66) winsize 62
748 19:23:33.754794 [CA 4] Center 35 (4~66) winsize 63
749 19:23:33.754894 [CA 5] Center 34 (4~65) winsize 62
750 19:23:33.754962
751 19:23:33.758310 [CmdBusTrainingLP45] Vref(ca) range 1: 32
752 19:23:33.758398
753 19:23:33.762168 [CATrainingPosCal] consider 2 rank data
754 19:23:33.765838 u2DelayCellTimex100 = 270/100 ps
755 19:23:33.769655 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
756 19:23:33.773584 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
757 19:23:33.777192 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
758 19:23:33.780752 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
759 19:23:33.784748 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
760 19:23:33.788106 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
761 19:23:33.788204
762 19:23:33.792035 CA PerBit enable=1, Macro0, CA PI delay=34
763 19:23:33.792127
764 19:23:33.795562 [CBTSetCACLKResult] CA Dly = 34
765 19:23:33.795651 CS Dly: 6 (0~38)
766 19:23:33.795719
767 19:23:33.799656 ----->DramcWriteLeveling(PI) begin...
768 19:23:33.799747 ==
769 19:23:33.803309 Dram Type= 6, Freq= 0, CH_0, rank 0
770 19:23:33.807240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
771 19:23:33.807338 ==
772 19:23:33.810932 Write leveling (Byte 0): 32 => 32
773 19:23:33.814346 Write leveling (Byte 1): 29 => 29
774 19:23:33.818305 DramcWriteLeveling(PI) end<-----
775 19:23:33.818404
776 19:23:33.818472 ==
777 19:23:33.822033 Dram Type= 6, Freq= 0, CH_0, rank 0
778 19:23:33.825921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
779 19:23:33.826015 ==
780 19:23:33.829218 [Gating] SW mode calibration
781 19:23:33.836647 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
782 19:23:33.840340 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
783 19:23:33.844464 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
784 19:23:33.847613 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
785 19:23:33.855597 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
786 19:23:33.859000 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 19:23:33.863143 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 19:23:33.866432 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 19:23:33.870361 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 19:23:33.874080 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 19:23:33.881459 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 19:23:33.885322 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 19:23:33.889090 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 19:23:33.892434 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 19:23:33.896570 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 19:23:33.903773 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 19:23:33.907369 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 19:23:33.911118 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 19:23:33.914560 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
800 19:23:33.918482 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
801 19:23:33.925946 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
802 19:23:33.929177 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 19:23:33.933099 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 19:23:33.936738 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 19:23:33.940600 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 19:23:33.944542 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 19:23:33.951921 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 19:23:33.955880 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 19:23:33.959767 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
810 19:23:33.963211 0 9 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
811 19:23:33.967027 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 19:23:33.970743 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 19:23:33.978037 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 19:23:33.981887 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 19:23:33.985589 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
816 19:23:33.988876 0 10 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (0 1)
817 19:23:33.996346 0 10 8 | B1->B0 | 3131 2323 | 0 0 | (0 1) (0 0)
818 19:23:34.000009 0 10 12 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
819 19:23:34.003185 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 19:23:34.006404 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 19:23:34.013125 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 19:23:34.016594 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 19:23:34.020000 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 19:23:34.026593 0 11 4 | B1->B0 | 2323 3938 | 0 1 | (0 0) (0 0)
825 19:23:34.029755 0 11 8 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
826 19:23:34.033113 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
827 19:23:34.039853 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 19:23:34.043081 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 19:23:34.046456 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 19:23:34.049719 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 19:23:34.056772 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 19:23:34.060094 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
833 19:23:34.062982 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
834 19:23:34.069946 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
835 19:23:34.073173 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 19:23:34.076575 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 19:23:34.083157 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 19:23:34.086470 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 19:23:34.089722 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 19:23:34.096941 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 19:23:34.100195 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 19:23:34.103437 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 19:23:34.110179 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 19:23:34.113209 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 19:23:34.116642 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 19:23:34.120271 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 19:23:34.127017 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 19:23:34.130033 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
849 19:23:34.133456 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
850 19:23:34.136838 Total UI for P1: 0, mck2ui 16
851 19:23:34.140226 best dqsien dly found for B0: ( 0, 14, 4)
852 19:23:34.143479 Total UI for P1: 0, mck2ui 16
853 19:23:34.147033 best dqsien dly found for B1: ( 0, 14, 6)
854 19:23:34.149967 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
855 19:23:34.153518 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
856 19:23:34.153630
857 19:23:34.160131 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
858 19:23:34.163103 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
859 19:23:34.163186 [Gating] SW calibration Done
860 19:23:34.166847 ==
861 19:23:34.170300 Dram Type= 6, Freq= 0, CH_0, rank 0
862 19:23:34.173373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
863 19:23:34.173488 ==
864 19:23:34.173660 RX Vref Scan: 0
865 19:23:34.173827
866 19:23:34.177001 RX Vref 0 -> 0, step: 1
867 19:23:34.177151
868 19:23:34.180323 RX Delay -130 -> 252, step: 16
869 19:23:34.183790 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
870 19:23:34.186597 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
871 19:23:34.190413 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
872 19:23:34.197059 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
873 19:23:34.200267 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
874 19:23:34.203567 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
875 19:23:34.206931 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
876 19:23:34.210113 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
877 19:23:34.216943 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
878 19:23:34.220001 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
879 19:23:34.223572 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
880 19:23:34.226715 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
881 19:23:34.230194 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
882 19:23:34.236775 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
883 19:23:34.240257 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
884 19:23:34.243803 iDelay=222, Bit 15, Center 77 (-34 ~ 189) 224
885 19:23:34.243934 ==
886 19:23:34.247151 Dram Type= 6, Freq= 0, CH_0, rank 0
887 19:23:34.250402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
888 19:23:34.250491 ==
889 19:23:34.253821 DQS Delay:
890 19:23:34.253927 DQS0 = 0, DQS1 = 0
891 19:23:34.257090 DQM Delay:
892 19:23:34.257241 DQM0 = 89, DQM1 = 78
893 19:23:34.257369 DQ Delay:
894 19:23:34.260380 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
895 19:23:34.263570 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =101
896 19:23:34.266924 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
897 19:23:34.270154 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =77
898 19:23:34.270242
899 19:23:34.270309
900 19:23:34.273559 ==
901 19:23:34.277178 Dram Type= 6, Freq= 0, CH_0, rank 0
902 19:23:34.280380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
903 19:23:34.280471 ==
904 19:23:34.280560
905 19:23:34.280623
906 19:23:34.284152 TX Vref Scan disable
907 19:23:34.284263 == TX Byte 0 ==
908 19:23:34.287539 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
909 19:23:34.294047 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
910 19:23:34.294159 == TX Byte 1 ==
911 19:23:34.297439 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
912 19:23:34.303723 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
913 19:23:34.303826 ==
914 19:23:34.307369 Dram Type= 6, Freq= 0, CH_0, rank 0
915 19:23:34.310675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
916 19:23:34.310778 ==
917 19:23:34.323806 TX Vref=22, minBit 8, minWin=26, winSum=435
918 19:23:34.326881 TX Vref=24, minBit 11, minWin=26, winSum=439
919 19:23:34.330258 TX Vref=26, minBit 8, minWin=27, winSum=449
920 19:23:34.333849 TX Vref=28, minBit 9, minWin=27, winSum=453
921 19:23:34.336873 TX Vref=30, minBit 1, minWin=28, winSum=456
922 19:23:34.343957 TX Vref=32, minBit 13, minWin=27, winSum=454
923 19:23:34.346928 [TxChooseVref] Worse bit 1, Min win 28, Win sum 456, Final Vref 30
924 19:23:34.347055
925 19:23:34.350135 Final TX Range 1 Vref 30
926 19:23:34.350272
927 19:23:34.350380 ==
928 19:23:34.353537 Dram Type= 6, Freq= 0, CH_0, rank 0
929 19:23:34.357354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
930 19:23:34.357480 ==
931 19:23:34.360560
932 19:23:34.360638
933 19:23:34.360702 TX Vref Scan disable
934 19:23:34.363967 == TX Byte 0 ==
935 19:23:34.367163 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
936 19:23:34.370431 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
937 19:23:34.374331 == TX Byte 1 ==
938 19:23:34.377194 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
939 19:23:34.380841 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
940 19:23:34.384198
941 19:23:34.384303 [DATLAT]
942 19:23:34.384373 Freq=800, CH0 RK0
943 19:23:34.384443
944 19:23:34.387408 DATLAT Default: 0xa
945 19:23:34.387496 0, 0xFFFF, sum = 0
946 19:23:34.390736 1, 0xFFFF, sum = 0
947 19:23:34.390826 2, 0xFFFF, sum = 0
948 19:23:34.394163 3, 0xFFFF, sum = 0
949 19:23:34.394263 4, 0xFFFF, sum = 0
950 19:23:34.397577 5, 0xFFFF, sum = 0
951 19:23:34.397695 6, 0xFFFF, sum = 0
952 19:23:34.400809 7, 0xFFFF, sum = 0
953 19:23:34.400900 8, 0xFFFF, sum = 0
954 19:23:34.403963 9, 0x0, sum = 1
955 19:23:34.404053 10, 0x0, sum = 2
956 19:23:34.407726 11, 0x0, sum = 3
957 19:23:34.407816 12, 0x0, sum = 4
958 19:23:34.411144 best_step = 10
959 19:23:34.411232
960 19:23:34.411300 ==
961 19:23:34.414349 Dram Type= 6, Freq= 0, CH_0, rank 0
962 19:23:34.417629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
963 19:23:34.417718 ==
964 19:23:34.420644 RX Vref Scan: 1
965 19:23:34.420732
966 19:23:34.420800 Set Vref Range= 32 -> 127
967 19:23:34.420866
968 19:23:34.424065 RX Vref 32 -> 127, step: 1
969 19:23:34.424153
970 19:23:34.427528 RX Delay -95 -> 252, step: 8
971 19:23:34.427617
972 19:23:34.430991 Set Vref, RX VrefLevel [Byte0]: 32
973 19:23:34.434050 [Byte1]: 32
974 19:23:34.434141
975 19:23:34.437275 Set Vref, RX VrefLevel [Byte0]: 33
976 19:23:34.440786 [Byte1]: 33
977 19:23:34.444309
978 19:23:34.444402 Set Vref, RX VrefLevel [Byte0]: 34
979 19:23:34.447321 [Byte1]: 34
980 19:23:34.451700
981 19:23:34.451800 Set Vref, RX VrefLevel [Byte0]: 35
982 19:23:34.455585 [Byte1]: 35
983 19:23:34.459345
984 19:23:34.459439 Set Vref, RX VrefLevel [Byte0]: 36
985 19:23:34.462822 [Byte1]: 36
986 19:23:34.466932
987 19:23:34.467025 Set Vref, RX VrefLevel [Byte0]: 37
988 19:23:34.470316 [Byte1]: 37
989 19:23:34.474504
990 19:23:34.474603 Set Vref, RX VrefLevel [Byte0]: 38
991 19:23:34.478459 [Byte1]: 38
992 19:23:34.482718
993 19:23:34.482813 Set Vref, RX VrefLevel [Byte0]: 39
994 19:23:34.486008 [Byte1]: 39
995 19:23:34.490088
996 19:23:34.490183 Set Vref, RX VrefLevel [Byte0]: 40
997 19:23:34.493161 [Byte1]: 40
998 19:23:34.497508
999 19:23:34.497599 Set Vref, RX VrefLevel [Byte0]: 41
1000 19:23:34.500761 [Byte1]: 41
1001 19:23:34.505583
1002 19:23:34.505683 Set Vref, RX VrefLevel [Byte0]: 42
1003 19:23:34.508938 [Byte1]: 42
1004 19:23:34.513093
1005 19:23:34.513189 Set Vref, RX VrefLevel [Byte0]: 43
1006 19:23:34.516552 [Byte1]: 43
1007 19:23:34.520723
1008 19:23:34.520818 Set Vref, RX VrefLevel [Byte0]: 44
1009 19:23:34.523658 [Byte1]: 44
1010 19:23:34.528573
1011 19:23:34.528673 Set Vref, RX VrefLevel [Byte0]: 45
1012 19:23:34.531454 [Byte1]: 45
1013 19:23:34.535777
1014 19:23:34.535873 Set Vref, RX VrefLevel [Byte0]: 46
1015 19:23:34.538686 [Byte1]: 46
1016 19:23:34.543012
1017 19:23:34.543110 Set Vref, RX VrefLevel [Byte0]: 47
1018 19:23:34.546269 [Byte1]: 47
1019 19:23:34.550706
1020 19:23:34.550802 Set Vref, RX VrefLevel [Byte0]: 48
1021 19:23:34.554020 [Byte1]: 48
1022 19:23:34.558099
1023 19:23:34.558190 Set Vref, RX VrefLevel [Byte0]: 49
1024 19:23:34.561643 [Byte1]: 49
1025 19:23:34.566173
1026 19:23:34.566266 Set Vref, RX VrefLevel [Byte0]: 50
1027 19:23:34.569025 [Byte1]: 50
1028 19:23:34.573520
1029 19:23:34.573614 Set Vref, RX VrefLevel [Byte0]: 51
1030 19:23:34.576638 [Byte1]: 51
1031 19:23:34.580916
1032 19:23:34.581009 Set Vref, RX VrefLevel [Byte0]: 52
1033 19:23:34.584327 [Byte1]: 52
1034 19:23:34.588573
1035 19:23:34.588663 Set Vref, RX VrefLevel [Byte0]: 53
1036 19:23:34.592013 [Byte1]: 53
1037 19:23:34.596308
1038 19:23:34.596399 Set Vref, RX VrefLevel [Byte0]: 54
1039 19:23:34.599643 [Byte1]: 54
1040 19:23:34.603885
1041 19:23:34.603975 Set Vref, RX VrefLevel [Byte0]: 55
1042 19:23:34.607050 [Byte1]: 55
1043 19:23:34.611297
1044 19:23:34.611384 Set Vref, RX VrefLevel [Byte0]: 56
1045 19:23:34.614808 [Byte1]: 56
1046 19:23:34.619016
1047 19:23:34.619106 Set Vref, RX VrefLevel [Byte0]: 57
1048 19:23:34.622131 [Byte1]: 57
1049 19:23:34.626432
1050 19:23:34.626521 Set Vref, RX VrefLevel [Byte0]: 58
1051 19:23:34.629892 [Byte1]: 58
1052 19:23:34.634207
1053 19:23:34.634295 Set Vref, RX VrefLevel [Byte0]: 59
1054 19:23:34.637673 [Byte1]: 59
1055 19:23:34.641722
1056 19:23:34.641810 Set Vref, RX VrefLevel [Byte0]: 60
1057 19:23:34.645261 [Byte1]: 60
1058 19:23:34.649184
1059 19:23:34.649275 Set Vref, RX VrefLevel [Byte0]: 61
1060 19:23:34.652919 [Byte1]: 61
1061 19:23:34.657458
1062 19:23:34.657551 Set Vref, RX VrefLevel [Byte0]: 62
1063 19:23:34.660262 [Byte1]: 62
1064 19:23:34.664565
1065 19:23:34.664659 Set Vref, RX VrefLevel [Byte0]: 63
1066 19:23:34.667891 [Byte1]: 63
1067 19:23:34.672115
1068 19:23:34.672224 Set Vref, RX VrefLevel [Byte0]: 64
1069 19:23:34.675694 [Byte1]: 64
1070 19:23:34.679868
1071 19:23:34.679964 Set Vref, RX VrefLevel [Byte0]: 65
1072 19:23:34.683331 [Byte1]: 65
1073 19:23:34.687246
1074 19:23:34.687336 Set Vref, RX VrefLevel [Byte0]: 66
1075 19:23:34.690636 [Byte1]: 66
1076 19:23:34.694799
1077 19:23:34.694890 Set Vref, RX VrefLevel [Byte0]: 67
1078 19:23:34.698461 [Byte1]: 67
1079 19:23:34.702833
1080 19:23:34.702925 Set Vref, RX VrefLevel [Byte0]: 68
1081 19:23:34.706207 [Byte1]: 68
1082 19:23:34.710651
1083 19:23:34.710743 Set Vref, RX VrefLevel [Byte0]: 69
1084 19:23:34.713254 [Byte1]: 69
1085 19:23:34.717813
1086 19:23:34.717902 Set Vref, RX VrefLevel [Byte0]: 70
1087 19:23:34.721023 [Byte1]: 70
1088 19:23:34.725321
1089 19:23:34.725433 Set Vref, RX VrefLevel [Byte0]: 71
1090 19:23:34.728679 [Byte1]: 71
1091 19:23:34.733364
1092 19:23:34.733455 Set Vref, RX VrefLevel [Byte0]: 72
1093 19:23:34.736299 [Byte1]: 72
1094 19:23:34.740481
1095 19:23:34.740569 Set Vref, RX VrefLevel [Byte0]: 73
1096 19:23:34.743778 [Byte1]: 73
1097 19:23:34.748128
1098 19:23:34.748220 Set Vref, RX VrefLevel [Byte0]: 74
1099 19:23:34.751562 [Byte1]: 74
1100 19:23:34.755998
1101 19:23:34.756095 Set Vref, RX VrefLevel [Byte0]: 75
1102 19:23:34.759235 [Byte1]: 75
1103 19:23:34.763508
1104 19:23:34.763603 Set Vref, RX VrefLevel [Byte0]: 76
1105 19:23:34.766971 [Byte1]: 76
1106 19:23:34.771269
1107 19:23:34.771364 Set Vref, RX VrefLevel [Byte0]: 77
1108 19:23:34.774438 [Byte1]: 77
1109 19:23:34.778550
1110 19:23:34.778647 Set Vref, RX VrefLevel [Byte0]: 78
1111 19:23:34.782226 [Byte1]: 78
1112 19:23:34.786283
1113 19:23:34.786374 Set Vref, RX VrefLevel [Byte0]: 79
1114 19:23:34.789524 [Byte1]: 79
1115 19:23:34.793870
1116 19:23:34.793959 Final RX Vref Byte 0 = 61 to rank0
1117 19:23:34.797107 Final RX Vref Byte 1 = 63 to rank0
1118 19:23:34.800819 Final RX Vref Byte 0 = 61 to rank1
1119 19:23:34.803607 Final RX Vref Byte 1 = 63 to rank1==
1120 19:23:34.807302 Dram Type= 6, Freq= 0, CH_0, rank 0
1121 19:23:34.813933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1122 19:23:34.814034 ==
1123 19:23:34.814102 DQS Delay:
1124 19:23:34.814165 DQS0 = 0, DQS1 = 0
1125 19:23:34.817196 DQM Delay:
1126 19:23:34.817282 DQM0 = 93, DQM1 = 83
1127 19:23:34.820436 DQ Delay:
1128 19:23:34.823852 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1129 19:23:34.827567 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1130 19:23:34.827659 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =80
1131 19:23:34.833714 DQ12 =88, DQ13 =88, DQ14 =92, DQ15 =92
1132 19:23:34.833808
1133 19:23:34.833876
1134 19:23:34.840508 [DQSOSCAuto] RK0, (LSB)MR18= 0x3b36, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 394 ps
1135 19:23:34.843929 CH0 RK0: MR19=606, MR18=3B36
1136 19:23:34.850353 CH0_RK0: MR19=0x606, MR18=0x3B36, DQSOSC=394, MR23=63, INC=95, DEC=63
1137 19:23:34.850463
1138 19:23:34.853799 ----->DramcWriteLeveling(PI) begin...
1139 19:23:34.853890 ==
1140 19:23:34.857181 Dram Type= 6, Freq= 0, CH_0, rank 1
1141 19:23:34.860637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1142 19:23:34.860728 ==
1143 19:23:34.863729 Write leveling (Byte 0): 31 => 31
1144 19:23:34.867470 Write leveling (Byte 1): 29 => 29
1145 19:23:34.870493 DramcWriteLeveling(PI) end<-----
1146 19:23:34.870582
1147 19:23:34.870650 ==
1148 19:23:34.873984 Dram Type= 6, Freq= 0, CH_0, rank 1
1149 19:23:34.877012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1150 19:23:34.877105 ==
1151 19:23:34.880527 [Gating] SW mode calibration
1152 19:23:34.887348 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1153 19:23:34.893925 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1154 19:23:34.897229 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1155 19:23:34.900335 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1156 19:23:34.947994 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1157 19:23:34.948171 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 19:23:34.948275 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 19:23:34.948573 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 19:23:34.948642 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 19:23:34.948703 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 19:23:34.948762 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 19:23:34.948832 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 19:23:34.949186 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 19:23:34.949454 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 19:23:34.965262 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 19:23:34.965454 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 19:23:34.965755 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 19:23:34.965840 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 19:23:34.968962 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 19:23:34.972281 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1172 19:23:34.975192 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1173 19:23:34.981955 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 19:23:34.985291 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 19:23:34.988821 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 19:23:34.995510 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 19:23:34.998853 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 19:23:35.001999 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 19:23:35.008821 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1180 19:23:35.012156 0 9 8 | B1->B0 | 2929 3434 | 1 0 | (1 1) (0 0)
1181 19:23:35.015309 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 19:23:35.018596 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 19:23:35.025277 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 19:23:35.028892 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 19:23:35.032214 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 19:23:35.038952 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1187 19:23:35.042253 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 0)
1188 19:23:35.045649 0 10 8 | B1->B0 | 2d2d 2424 | 1 0 | (0 0) (0 0)
1189 19:23:35.052223 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 19:23:35.055507 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 19:23:35.058835 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 19:23:35.065663 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 19:23:35.069150 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 19:23:35.072162 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 19:23:35.078792 0 11 4 | B1->B0 | 2828 3030 | 0 1 | (0 0) (0 0)
1196 19:23:35.082459 0 11 8 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
1197 19:23:35.086184 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 19:23:35.089931 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 19:23:35.093689 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 19:23:35.100446 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 19:23:35.103990 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 19:23:35.107392 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 19:23:35.111058 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 19:23:35.117800 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1205 19:23:35.121455 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 19:23:35.124754 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 19:23:35.131526 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 19:23:35.134616 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 19:23:35.137992 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 19:23:35.144559 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 19:23:35.148021 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 19:23:35.151259 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 19:23:35.158078 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 19:23:35.161178 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 19:23:35.164669 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 19:23:35.168386 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 19:23:35.175042 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 19:23:35.178316 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 19:23:35.181210 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1220 19:23:35.184979 Total UI for P1: 0, mck2ui 16
1221 19:23:35.188317 best dqsien dly found for B0: ( 0, 14, 2)
1222 19:23:35.194970 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1223 19:23:35.197978 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1224 19:23:35.201429 Total UI for P1: 0, mck2ui 16
1225 19:23:35.205159 best dqsien dly found for B1: ( 0, 14, 6)
1226 19:23:35.208074 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1227 19:23:35.211756 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1228 19:23:35.211848
1229 19:23:35.215140 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1230 19:23:35.218190 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1231 19:23:35.221878 [Gating] SW calibration Done
1232 19:23:35.221970 ==
1233 19:23:35.224813 Dram Type= 6, Freq= 0, CH_0, rank 1
1234 19:23:35.228149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1235 19:23:35.231480 ==
1236 19:23:35.231569 RX Vref Scan: 0
1237 19:23:35.231635
1238 19:23:35.234715 RX Vref 0 -> 0, step: 1
1239 19:23:35.234826
1240 19:23:35.238398 RX Delay -130 -> 252, step: 16
1241 19:23:35.241432 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1242 19:23:35.244858 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1243 19:23:35.248019 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1244 19:23:35.251308 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1245 19:23:35.258117 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1246 19:23:35.261380 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1247 19:23:35.264733 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1248 19:23:35.268038 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1249 19:23:35.271521 iDelay=222, Bit 8, Center 69 (-34 ~ 173) 208
1250 19:23:35.274684 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
1251 19:23:35.281806 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1252 19:23:35.284868 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1253 19:23:35.288136 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1254 19:23:35.291578 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1255 19:23:35.298133 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1256 19:23:35.301546 iDelay=222, Bit 15, Center 77 (-34 ~ 189) 224
1257 19:23:35.301672 ==
1258 19:23:35.304979 Dram Type= 6, Freq= 0, CH_0, rank 1
1259 19:23:35.307873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1260 19:23:35.307965 ==
1261 19:23:35.308032 DQS Delay:
1262 19:23:35.311322 DQS0 = 0, DQS1 = 0
1263 19:23:35.311409 DQM Delay:
1264 19:23:35.314824 DQM0 = 89, DQM1 = 77
1265 19:23:35.314912 DQ Delay:
1266 19:23:35.318105 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =77
1267 19:23:35.321284 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
1268 19:23:35.324961 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77
1269 19:23:35.328253 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =77
1270 19:23:35.328347
1271 19:23:35.328414
1272 19:23:35.328476 ==
1273 19:23:35.331708 Dram Type= 6, Freq= 0, CH_0, rank 1
1274 19:23:35.334657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1275 19:23:35.337934 ==
1276 19:23:35.338024
1277 19:23:35.338093
1278 19:23:35.338154 TX Vref Scan disable
1279 19:23:35.341460 == TX Byte 0 ==
1280 19:23:35.344602 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1281 19:23:35.347913 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1282 19:23:35.351295 == TX Byte 1 ==
1283 19:23:35.354944 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1284 19:23:35.358398 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1285 19:23:35.361750 ==
1286 19:23:35.361844 Dram Type= 6, Freq= 0, CH_0, rank 1
1287 19:23:35.367864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1288 19:23:35.367964 ==
1289 19:23:35.380774 TX Vref=22, minBit 3, minWin=27, winSum=447
1290 19:23:35.384238 TX Vref=24, minBit 8, minWin=27, winSum=448
1291 19:23:35.387608 TX Vref=26, minBit 8, minWin=27, winSum=450
1292 19:23:35.390644 TX Vref=28, minBit 8, minWin=27, winSum=454
1293 19:23:35.393905 TX Vref=30, minBit 8, minWin=27, winSum=456
1294 19:23:35.397833 TX Vref=32, minBit 8, minWin=27, winSum=456
1295 19:23:35.404123 [TxChooseVref] Worse bit 8, Min win 27, Win sum 456, Final Vref 30
1296 19:23:35.404233
1297 19:23:35.407305 Final TX Range 1 Vref 30
1298 19:23:35.407414
1299 19:23:35.407508 ==
1300 19:23:35.410664 Dram Type= 6, Freq= 0, CH_0, rank 1
1301 19:23:35.413983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1302 19:23:35.414072 ==
1303 19:23:35.414136
1304 19:23:35.417383
1305 19:23:35.417498 TX Vref Scan disable
1306 19:23:35.420539 == TX Byte 0 ==
1307 19:23:35.423959 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1308 19:23:35.427220 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1309 19:23:35.430616 == TX Byte 1 ==
1310 19:23:35.434278 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1311 19:23:35.437471 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1312 19:23:35.440867
1313 19:23:35.440952 [DATLAT]
1314 19:23:35.441016 Freq=800, CH0 RK1
1315 19:23:35.441076
1316 19:23:35.444246 DATLAT Default: 0xa
1317 19:23:35.444331 0, 0xFFFF, sum = 0
1318 19:23:35.447403 1, 0xFFFF, sum = 0
1319 19:23:35.447490 2, 0xFFFF, sum = 0
1320 19:23:35.450581 3, 0xFFFF, sum = 0
1321 19:23:35.450666 4, 0xFFFF, sum = 0
1322 19:23:35.453812 5, 0xFFFF, sum = 0
1323 19:23:35.457117 6, 0xFFFF, sum = 0
1324 19:23:35.457205 7, 0xFFFF, sum = 0
1325 19:23:35.460934 8, 0xFFFF, sum = 0
1326 19:23:35.461018 9, 0x0, sum = 1
1327 19:23:35.461083 10, 0x0, sum = 2
1328 19:23:35.464353 11, 0x0, sum = 3
1329 19:23:35.464436 12, 0x0, sum = 4
1330 19:23:35.467160 best_step = 10
1331 19:23:35.467242
1332 19:23:35.467306 ==
1333 19:23:35.470591 Dram Type= 6, Freq= 0, CH_0, rank 1
1334 19:23:35.473953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1335 19:23:35.474038 ==
1336 19:23:35.477355 RX Vref Scan: 0
1337 19:23:35.477448
1338 19:23:35.477513 RX Vref 0 -> 0, step: 1
1339 19:23:35.477572
1340 19:23:35.480822 RX Delay -79 -> 252, step: 8
1341 19:23:35.487159 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1342 19:23:35.490451 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1343 19:23:35.494089 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1344 19:23:35.497178 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1345 19:23:35.500625 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1346 19:23:35.507128 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1347 19:23:35.510605 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1348 19:23:35.513750 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1349 19:23:35.517178 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1350 19:23:35.520429 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1351 19:23:35.527241 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1352 19:23:35.530413 iDelay=209, Bit 11, Center 76 (-23 ~ 176) 200
1353 19:23:35.533889 iDelay=209, Bit 12, Center 88 (-15 ~ 192) 208
1354 19:23:35.537254 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1355 19:23:35.540524 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1356 19:23:35.547452 iDelay=209, Bit 15, Center 88 (-15 ~ 192) 208
1357 19:23:35.547557 ==
1358 19:23:35.550510 Dram Type= 6, Freq= 0, CH_0, rank 1
1359 19:23:35.553900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1360 19:23:35.553990 ==
1361 19:23:35.554055 DQS Delay:
1362 19:23:35.557338 DQS0 = 0, DQS1 = 0
1363 19:23:35.557421 DQM Delay:
1364 19:23:35.560821 DQM0 = 90, DQM1 = 81
1365 19:23:35.560903 DQ Delay:
1366 19:23:35.564166 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =84
1367 19:23:35.567513 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1368 19:23:35.570880 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =76
1369 19:23:35.573715 DQ12 =88, DQ13 =84, DQ14 =92, DQ15 =88
1370 19:23:35.573800
1371 19:23:35.573862
1372 19:23:35.584043 [DQSOSCAuto] RK1, (LSB)MR18= 0x411b, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 393 ps
1373 19:23:35.584166 CH0 RK1: MR19=606, MR18=411B
1374 19:23:35.590593 CH0_RK1: MR19=0x606, MR18=0x411B, DQSOSC=393, MR23=63, INC=95, DEC=63
1375 19:23:35.593972 [RxdqsGatingPostProcess] freq 800
1376 19:23:35.600656 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1377 19:23:35.604223 Pre-setting of DQS Precalculation
1378 19:23:35.607129 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1379 19:23:35.607215 ==
1380 19:23:35.610513 Dram Type= 6, Freq= 0, CH_1, rank 0
1381 19:23:35.613806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1382 19:23:35.613925 ==
1383 19:23:35.620393 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1384 19:23:35.627138 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1385 19:23:35.636012 [CA 0] Center 36 (6~67) winsize 62
1386 19:23:35.639061 [CA 1] Center 36 (6~67) winsize 62
1387 19:23:35.642733 [CA 2] Center 34 (4~65) winsize 62
1388 19:23:35.645526 [CA 3] Center 34 (3~65) winsize 63
1389 19:23:35.648872 [CA 4] Center 34 (4~65) winsize 62
1390 19:23:35.652271 [CA 5] Center 33 (3~64) winsize 62
1391 19:23:35.652359
1392 19:23:35.655907 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1393 19:23:35.655989
1394 19:23:35.659303 [CATrainingPosCal] consider 1 rank data
1395 19:23:35.662494 u2DelayCellTimex100 = 270/100 ps
1396 19:23:35.665794 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1397 19:23:35.669182 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1398 19:23:35.675983 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1399 19:23:35.679122 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1400 19:23:35.682345 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1401 19:23:35.685846 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1402 19:23:35.685939
1403 19:23:35.689140 CA PerBit enable=1, Macro0, CA PI delay=33
1404 19:23:35.689224
1405 19:23:35.692472 [CBTSetCACLKResult] CA Dly = 33
1406 19:23:35.692554 CS Dly: 5 (0~36)
1407 19:23:35.692619 ==
1408 19:23:35.695820 Dram Type= 6, Freq= 0, CH_1, rank 1
1409 19:23:35.702448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1410 19:23:35.702548 ==
1411 19:23:35.705700 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1412 19:23:35.712591 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1413 19:23:35.721972 [CA 0] Center 36 (6~67) winsize 62
1414 19:23:35.725261 [CA 1] Center 37 (6~68) winsize 63
1415 19:23:35.728694 [CA 2] Center 35 (4~66) winsize 63
1416 19:23:35.731952 [CA 3] Center 34 (4~65) winsize 62
1417 19:23:35.735538 [CA 4] Center 34 (4~65) winsize 62
1418 19:23:35.739006 [CA 5] Center 34 (4~64) winsize 61
1419 19:23:35.739097
1420 19:23:35.741805 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1421 19:23:35.741887
1422 19:23:35.745319 [CATrainingPosCal] consider 2 rank data
1423 19:23:35.749252 u2DelayCellTimex100 = 270/100 ps
1424 19:23:35.753021 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1425 19:23:35.756866 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1426 19:23:35.760652 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1427 19:23:35.763996 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1428 19:23:35.767721 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1429 19:23:35.771657 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1430 19:23:35.771752
1431 19:23:35.775460 CA PerBit enable=1, Macro0, CA PI delay=34
1432 19:23:35.775563
1433 19:23:35.779108 [CBTSetCACLKResult] CA Dly = 34
1434 19:23:35.779229 CS Dly: 5 (0~37)
1435 19:23:35.779294
1436 19:23:35.782614 ----->DramcWriteLeveling(PI) begin...
1437 19:23:35.782699 ==
1438 19:23:35.786227 Dram Type= 6, Freq= 0, CH_1, rank 0
1439 19:23:35.789863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1440 19:23:35.789954 ==
1441 19:23:35.793157 Write leveling (Byte 0): 28 => 28
1442 19:23:35.796415 Write leveling (Byte 1): 29 => 29
1443 19:23:35.799842 DramcWriteLeveling(PI) end<-----
1444 19:23:35.799955
1445 19:23:35.800032 ==
1446 19:23:35.803195 Dram Type= 6, Freq= 0, CH_1, rank 0
1447 19:23:35.806551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1448 19:23:35.809747 ==
1449 19:23:35.809833 [Gating] SW mode calibration
1450 19:23:35.820054 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1451 19:23:35.823235 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1452 19:23:35.826573 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1453 19:23:35.833128 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1454 19:23:35.836529 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 19:23:35.839735 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 19:23:35.846595 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 19:23:35.849842 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 19:23:35.853135 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 19:23:35.859808 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 19:23:35.863124 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 19:23:35.866464 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 19:23:35.873576 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 19:23:35.876380 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 19:23:35.879893 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 19:23:35.883194 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 19:23:35.889944 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 19:23:35.893290 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1468 19:23:35.896762 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1469 19:23:35.903293 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1470 19:23:35.906710 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1471 19:23:35.910066 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 19:23:35.916384 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 19:23:35.920196 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 19:23:35.923145 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 19:23:35.929838 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 19:23:35.933287 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 19:23:35.936325 0 9 4 | B1->B0 | 2525 2d2d | 1 0 | (1 1) (0 0)
1478 19:23:35.943345 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 19:23:35.946795 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 19:23:35.949976 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 19:23:35.956603 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 19:23:35.960324 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 19:23:35.963228 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 19:23:35.966496 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
1485 19:23:35.973284 0 10 4 | B1->B0 | 2f2f 2929 | 1 1 | (1 0) (1 0)
1486 19:23:35.976670 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1487 19:23:35.980025 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 19:23:35.986656 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 19:23:35.989996 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 19:23:35.993212 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 19:23:35.999743 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 19:23:36.003284 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 19:23:36.006496 0 11 4 | B1->B0 | 3232 3939 | 1 0 | (0 0) (0 0)
1494 19:23:36.013210 0 11 8 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1495 19:23:36.016637 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 19:23:36.019953 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 19:23:36.026949 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 19:23:36.029826 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 19:23:36.033284 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 19:23:36.040256 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 19:23:36.043572 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1502 19:23:36.046897 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 19:23:36.050299 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 19:23:36.056743 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 19:23:36.060433 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 19:23:36.063752 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 19:23:36.070603 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 19:23:36.073700 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 19:23:36.077203 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 19:23:36.083808 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 19:23:36.087191 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 19:23:36.090169 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 19:23:36.096742 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 19:23:36.100363 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 19:23:36.103732 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 19:23:36.110354 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 19:23:36.113633 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1518 19:23:36.116945 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1519 19:23:36.120268 Total UI for P1: 0, mck2ui 16
1520 19:23:36.123490 best dqsien dly found for B0: ( 0, 14, 4)
1521 19:23:36.127075 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1522 19:23:36.130239 Total UI for P1: 0, mck2ui 16
1523 19:23:36.133941 best dqsien dly found for B1: ( 0, 14, 6)
1524 19:23:36.136912 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1525 19:23:36.143556 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1526 19:23:36.143684
1527 19:23:36.147189 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1528 19:23:36.150167 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1529 19:23:36.153532 [Gating] SW calibration Done
1530 19:23:36.153621 ==
1531 19:23:36.157225 Dram Type= 6, Freq= 0, CH_1, rank 0
1532 19:23:36.160283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1533 19:23:36.160371 ==
1534 19:23:36.160436 RX Vref Scan: 0
1535 19:23:36.160495
1536 19:23:36.163495 RX Vref 0 -> 0, step: 1
1537 19:23:36.163577
1538 19:23:36.166865 RX Delay -130 -> 252, step: 16
1539 19:23:36.170170 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1540 19:23:36.173507 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1541 19:23:36.180043 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1542 19:23:36.183779 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1543 19:23:36.186762 iDelay=206, Bit 4, Center 77 (-34 ~ 189) 224
1544 19:23:36.190097 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1545 19:23:36.193633 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1546 19:23:36.200278 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1547 19:23:36.203529 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1548 19:23:36.206783 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1549 19:23:36.210109 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1550 19:23:36.213429 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1551 19:23:36.220167 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1552 19:23:36.224004 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1553 19:23:36.226826 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1554 19:23:36.230655 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1555 19:23:36.230748 ==
1556 19:23:36.233896 Dram Type= 6, Freq= 0, CH_1, rank 0
1557 19:23:36.237250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1558 19:23:36.240673 ==
1559 19:23:36.240762 DQS Delay:
1560 19:23:36.240829 DQS0 = 0, DQS1 = 0
1561 19:23:36.243529 DQM Delay:
1562 19:23:36.243612 DQM0 = 85, DQM1 = 80
1563 19:23:36.247308 DQ Delay:
1564 19:23:36.247395 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =85
1565 19:23:36.250483 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =85
1566 19:23:36.254015 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1567 19:23:36.257143 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1568 19:23:36.257231
1569 19:23:36.260580
1570 19:23:36.260665 ==
1571 19:23:36.263903 Dram Type= 6, Freq= 0, CH_1, rank 0
1572 19:23:36.267108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1573 19:23:36.267197 ==
1574 19:23:36.267263
1575 19:23:36.267324
1576 19:23:36.270600 TX Vref Scan disable
1577 19:23:36.270689 == TX Byte 0 ==
1578 19:23:36.274142 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1579 19:23:36.280915 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1580 19:23:36.281034 == TX Byte 1 ==
1581 19:23:36.284117 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1582 19:23:36.290678 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1583 19:23:36.290777 ==
1584 19:23:36.293977 Dram Type= 6, Freq= 0, CH_1, rank 0
1585 19:23:36.297254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1586 19:23:36.297392 ==
1587 19:23:36.310529 TX Vref=22, minBit 8, minWin=27, winSum=448
1588 19:23:36.313899 TX Vref=24, minBit 15, minWin=27, winSum=453
1589 19:23:36.316870 TX Vref=26, minBit 15, minWin=27, winSum=452
1590 19:23:36.320234 TX Vref=28, minBit 15, minWin=27, winSum=456
1591 19:23:36.324049 TX Vref=30, minBit 15, minWin=27, winSum=457
1592 19:23:36.330701 TX Vref=32, minBit 12, minWin=27, winSum=456
1593 19:23:36.334005 [TxChooseVref] Worse bit 15, Min win 27, Win sum 457, Final Vref 30
1594 19:23:36.334089
1595 19:23:36.337957 Final TX Range 1 Vref 30
1596 19:23:36.338041
1597 19:23:36.338107 ==
1598 19:23:36.340916 Dram Type= 6, Freq= 0, CH_1, rank 0
1599 19:23:36.344144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1600 19:23:36.344230 ==
1601 19:23:36.344295
1602 19:23:36.347700
1603 19:23:36.347785 TX Vref Scan disable
1604 19:23:36.351052 == TX Byte 0 ==
1605 19:23:36.354385 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1606 19:23:36.357781 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1607 19:23:36.361266 == TX Byte 1 ==
1608 19:23:36.364419 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1609 19:23:36.367751 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1610 19:23:36.367835
1611 19:23:36.371294 [DATLAT]
1612 19:23:36.371413 Freq=800, CH1 RK0
1613 19:23:36.371510
1614 19:23:36.374314 DATLAT Default: 0xa
1615 19:23:36.374423 0, 0xFFFF, sum = 0
1616 19:23:36.377804 1, 0xFFFF, sum = 0
1617 19:23:36.377894 2, 0xFFFF, sum = 0
1618 19:23:36.381513 3, 0xFFFF, sum = 0
1619 19:23:36.381593 4, 0xFFFF, sum = 0
1620 19:23:36.384336 5, 0xFFFF, sum = 0
1621 19:23:36.384408 6, 0xFFFF, sum = 0
1622 19:23:36.387953 7, 0xFFFF, sum = 0
1623 19:23:36.388026 8, 0xFFFF, sum = 0
1624 19:23:36.391370 9, 0x0, sum = 1
1625 19:23:36.391441 10, 0x0, sum = 2
1626 19:23:36.394202 11, 0x0, sum = 3
1627 19:23:36.394271 12, 0x0, sum = 4
1628 19:23:36.397491 best_step = 10
1629 19:23:36.397559
1630 19:23:36.397619 ==
1631 19:23:36.401202 Dram Type= 6, Freq= 0, CH_1, rank 0
1632 19:23:36.404588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1633 19:23:36.404658 ==
1634 19:23:36.407788 RX Vref Scan: 1
1635 19:23:36.407856
1636 19:23:36.407916 Set Vref Range= 32 -> 127
1637 19:23:36.407980
1638 19:23:36.411091 RX Vref 32 -> 127, step: 1
1639 19:23:36.411159
1640 19:23:36.414328 RX Delay -95 -> 252, step: 8
1641 19:23:36.414396
1642 19:23:36.417640 Set Vref, RX VrefLevel [Byte0]: 32
1643 19:23:36.420901 [Byte1]: 32
1644 19:23:36.420971
1645 19:23:36.424370 Set Vref, RX VrefLevel [Byte0]: 33
1646 19:23:36.427387 [Byte1]: 33
1647 19:23:36.431111
1648 19:23:36.431179 Set Vref, RX VrefLevel [Byte0]: 34
1649 19:23:36.434552 [Byte1]: 34
1650 19:23:36.438928
1651 19:23:36.438997 Set Vref, RX VrefLevel [Byte0]: 35
1652 19:23:36.441933 [Byte1]: 35
1653 19:23:36.446064
1654 19:23:36.446133 Set Vref, RX VrefLevel [Byte0]: 36
1655 19:23:36.449476 [Byte1]: 36
1656 19:23:36.453621
1657 19:23:36.453693 Set Vref, RX VrefLevel [Byte0]: 37
1658 19:23:36.456862 [Byte1]: 37
1659 19:23:36.461566
1660 19:23:36.461642 Set Vref, RX VrefLevel [Byte0]: 38
1661 19:23:36.464774 [Byte1]: 38
1662 19:23:36.468974
1663 19:23:36.469076 Set Vref, RX VrefLevel [Byte0]: 39
1664 19:23:36.472301 [Byte1]: 39
1665 19:23:36.476374
1666 19:23:36.476461 Set Vref, RX VrefLevel [Byte0]: 40
1667 19:23:36.479755 [Byte1]: 40
1668 19:23:36.484135
1669 19:23:36.484221 Set Vref, RX VrefLevel [Byte0]: 41
1670 19:23:36.487529 [Byte1]: 41
1671 19:23:36.491910
1672 19:23:36.491993 Set Vref, RX VrefLevel [Byte0]: 42
1673 19:23:36.495089 [Byte1]: 42
1674 19:23:36.499236
1675 19:23:36.499319 Set Vref, RX VrefLevel [Byte0]: 43
1676 19:23:36.502717 [Byte1]: 43
1677 19:23:36.506909
1678 19:23:36.506992 Set Vref, RX VrefLevel [Byte0]: 44
1679 19:23:36.510104 [Byte1]: 44
1680 19:23:36.514332
1681 19:23:36.514417 Set Vref, RX VrefLevel [Byte0]: 45
1682 19:23:36.518080 [Byte1]: 45
1683 19:23:36.522215
1684 19:23:36.522299 Set Vref, RX VrefLevel [Byte0]: 46
1685 19:23:36.525616 [Byte1]: 46
1686 19:23:36.529620
1687 19:23:36.529709 Set Vref, RX VrefLevel [Byte0]: 47
1688 19:23:36.533157 [Byte1]: 47
1689 19:23:36.537583
1690 19:23:36.537757 Set Vref, RX VrefLevel [Byte0]: 48
1691 19:23:36.541003 [Byte1]: 48
1692 19:23:36.545100
1693 19:23:36.545187 Set Vref, RX VrefLevel [Byte0]: 49
1694 19:23:36.548536 [Byte1]: 49
1695 19:23:36.552419
1696 19:23:36.552530 Set Vref, RX VrefLevel [Byte0]: 50
1697 19:23:36.556036 [Byte1]: 50
1698 19:23:36.560303
1699 19:23:36.560387 Set Vref, RX VrefLevel [Byte0]: 51
1700 19:23:36.563306 [Byte1]: 51
1701 19:23:36.568141
1702 19:23:36.568226 Set Vref, RX VrefLevel [Byte0]: 52
1703 19:23:36.570951 [Byte1]: 52
1704 19:23:36.575419
1705 19:23:36.575509 Set Vref, RX VrefLevel [Byte0]: 53
1706 19:23:36.578373 [Byte1]: 53
1707 19:23:36.582956
1708 19:23:36.583046 Set Vref, RX VrefLevel [Byte0]: 54
1709 19:23:36.586335 [Byte1]: 54
1710 19:23:36.590760
1711 19:23:36.590843 Set Vref, RX VrefLevel [Byte0]: 55
1712 19:23:36.593655 [Byte1]: 55
1713 19:23:36.598244
1714 19:23:36.598326 Set Vref, RX VrefLevel [Byte0]: 56
1715 19:23:36.601571 [Byte1]: 56
1716 19:23:36.605521
1717 19:23:36.605604 Set Vref, RX VrefLevel [Byte0]: 57
1718 19:23:36.608823 [Byte1]: 57
1719 19:23:36.613442
1720 19:23:36.613526 Set Vref, RX VrefLevel [Byte0]: 58
1721 19:23:36.616448 [Byte1]: 58
1722 19:23:36.620822
1723 19:23:36.620905 Set Vref, RX VrefLevel [Byte0]: 59
1724 19:23:36.624675 [Byte1]: 59
1725 19:23:36.628362
1726 19:23:36.628445 Set Vref, RX VrefLevel [Byte0]: 60
1727 19:23:36.631892 [Byte1]: 60
1728 19:23:36.636133
1729 19:23:36.636226 Set Vref, RX VrefLevel [Byte0]: 61
1730 19:23:36.639372 [Byte1]: 61
1731 19:23:36.643588
1732 19:23:36.643673 Set Vref, RX VrefLevel [Byte0]: 62
1733 19:23:36.646843 [Byte1]: 62
1734 19:23:36.651156
1735 19:23:36.651239 Set Vref, RX VrefLevel [Byte0]: 63
1736 19:23:36.654916 [Byte1]: 63
1737 19:23:36.659191
1738 19:23:36.659273 Set Vref, RX VrefLevel [Byte0]: 64
1739 19:23:36.662279 [Byte1]: 64
1740 19:23:36.666498
1741 19:23:36.666580 Set Vref, RX VrefLevel [Byte0]: 65
1742 19:23:36.669698 [Byte1]: 65
1743 19:23:36.673901
1744 19:23:36.673984 Set Vref, RX VrefLevel [Byte0]: 66
1745 19:23:36.677548 [Byte1]: 66
1746 19:23:36.681670
1747 19:23:36.681754 Set Vref, RX VrefLevel [Byte0]: 67
1748 19:23:36.685058 [Byte1]: 67
1749 19:23:36.689328
1750 19:23:36.689424 Set Vref, RX VrefLevel [Byte0]: 68
1751 19:23:36.692372 [Byte1]: 68
1752 19:23:36.696820
1753 19:23:36.696903 Set Vref, RX VrefLevel [Byte0]: 69
1754 19:23:36.700138 [Byte1]: 69
1755 19:23:36.704518
1756 19:23:36.704601 Set Vref, RX VrefLevel [Byte0]: 70
1757 19:23:36.707810 [Byte1]: 70
1758 19:23:36.712194
1759 19:23:36.712277 Set Vref, RX VrefLevel [Byte0]: 71
1760 19:23:36.715355 [Byte1]: 71
1761 19:23:36.719630
1762 19:23:36.719720 Set Vref, RX VrefLevel [Byte0]: 72
1763 19:23:36.722843 [Byte1]: 72
1764 19:23:36.727117
1765 19:23:36.727236 Set Vref, RX VrefLevel [Byte0]: 73
1766 19:23:36.730617 [Byte1]: 73
1767 19:23:36.734815
1768 19:23:36.734899 Set Vref, RX VrefLevel [Byte0]: 74
1769 19:23:36.738053 [Byte1]: 74
1770 19:23:36.742541
1771 19:23:36.742627 Set Vref, RX VrefLevel [Byte0]: 75
1772 19:23:36.745931 [Byte1]: 75
1773 19:23:36.750357
1774 19:23:36.750440 Set Vref, RX VrefLevel [Byte0]: 76
1775 19:23:36.753173 [Byte1]: 76
1776 19:23:36.757807
1777 19:23:36.757890 Final RX Vref Byte 0 = 54 to rank0
1778 19:23:36.760810 Final RX Vref Byte 1 = 59 to rank0
1779 19:23:36.764336 Final RX Vref Byte 0 = 54 to rank1
1780 19:23:36.767578 Final RX Vref Byte 1 = 59 to rank1==
1781 19:23:36.770998 Dram Type= 6, Freq= 0, CH_1, rank 0
1782 19:23:36.777820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1783 19:23:36.777934 ==
1784 19:23:36.778003 DQS Delay:
1785 19:23:36.778080 DQS0 = 0, DQS1 = 0
1786 19:23:36.781035 DQM Delay:
1787 19:23:36.781143 DQM0 = 92, DQM1 = 81
1788 19:23:36.784610 DQ Delay:
1789 19:23:36.787664 DQ0 =96, DQ1 =84, DQ2 =84, DQ3 =92
1790 19:23:36.791038 DQ4 =88, DQ5 =104, DQ6 =100, DQ7 =88
1791 19:23:36.791121 DQ8 =72, DQ9 =68, DQ10 =84, DQ11 =76
1792 19:23:36.797685 DQ12 =92, DQ13 =88, DQ14 =84, DQ15 =88
1793 19:23:36.797769
1794 19:23:36.797835
1795 19:23:36.804328 [DQSOSCAuto] RK0, (LSB)MR18= 0x3451, (MSB)MR19= 0x606, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
1796 19:23:36.807859 CH1 RK0: MR19=606, MR18=3451
1797 19:23:36.814377 CH1_RK0: MR19=0x606, MR18=0x3451, DQSOSC=389, MR23=63, INC=97, DEC=65
1798 19:23:36.814469
1799 19:23:36.817925 ----->DramcWriteLeveling(PI) begin...
1800 19:23:36.818009 ==
1801 19:23:36.820965 Dram Type= 6, Freq= 0, CH_1, rank 1
1802 19:23:36.824490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1803 19:23:36.824575 ==
1804 19:23:36.827613 Write leveling (Byte 0): 26 => 26
1805 19:23:36.831117 Write leveling (Byte 1): 31 => 31
1806 19:23:36.834309 DramcWriteLeveling(PI) end<-----
1807 19:23:36.834394
1808 19:23:36.834460 ==
1809 19:23:36.837750 Dram Type= 6, Freq= 0, CH_1, rank 1
1810 19:23:36.840968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1811 19:23:36.841078 ==
1812 19:23:36.844400 [Gating] SW mode calibration
1813 19:23:36.851055 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1814 19:23:36.857985 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1815 19:23:36.861271 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1816 19:23:36.864594 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1817 19:23:36.871066 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 19:23:36.874689 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 19:23:36.878098 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 19:23:36.884594 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 19:23:36.888065 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 19:23:36.891585 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 19:23:36.894730 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 19:23:36.901264 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 19:23:36.904719 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 19:23:36.908047 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 19:23:36.914879 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 19:23:36.918027 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 19:23:36.921215 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 19:23:36.928305 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 19:23:36.931172 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1832 19:23:36.934838 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1833 19:23:36.941602 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1834 19:23:36.944894 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 19:23:36.948119 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 19:23:36.954685 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 19:23:36.958180 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 19:23:36.961380 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 19:23:36.967993 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 19:23:36.971327 0 9 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1841 19:23:36.974668 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1842 19:23:36.981407 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1843 19:23:36.984746 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1844 19:23:36.987954 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1845 19:23:36.991593 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1846 19:23:36.998436 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1847 19:23:37.001477 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1848 19:23:37.004648 0 10 4 | B1->B0 | 2b2b 3131 | 0 1 | (0 0) (1 0)
1849 19:23:37.011864 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 19:23:37.014937 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 19:23:37.018700 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 19:23:37.025210 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 19:23:37.028181 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 19:23:37.031992 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 19:23:37.038268 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 19:23:37.041650 0 11 4 | B1->B0 | 2e2e 2d2d | 1 0 | (0 0) (0 0)
1857 19:23:37.045108 0 11 8 | B1->B0 | 4545 4545 | 0 0 | (0 0) (0 0)
1858 19:23:37.051650 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1859 19:23:37.055260 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 19:23:37.058635 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 19:23:37.061869 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 19:23:37.068424 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1863 19:23:37.071761 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1864 19:23:37.075111 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1865 19:23:37.081950 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 19:23:37.085253 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 19:23:37.088332 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 19:23:37.095401 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 19:23:37.098733 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 19:23:37.102136 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 19:23:37.108678 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 19:23:37.111980 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 19:23:37.115276 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 19:23:37.122016 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 19:23:37.125238 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 19:23:37.128344 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 19:23:37.135185 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 19:23:37.138573 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 19:23:37.141824 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 19:23:37.145090 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1881 19:23:37.151935 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1882 19:23:37.155092 Total UI for P1: 0, mck2ui 16
1883 19:23:37.158440 best dqsien dly found for B0: ( 0, 14, 6)
1884 19:23:37.161794 Total UI for P1: 0, mck2ui 16
1885 19:23:37.165217 best dqsien dly found for B1: ( 0, 14, 4)
1886 19:23:37.168419 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1887 19:23:37.171722 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1888 19:23:37.171804
1889 19:23:37.175184 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1890 19:23:37.178428 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1891 19:23:37.181860 [Gating] SW calibration Done
1892 19:23:37.181958 ==
1893 19:23:37.185167 Dram Type= 6, Freq= 0, CH_1, rank 1
1894 19:23:37.188692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1895 19:23:37.188787 ==
1896 19:23:37.191712 RX Vref Scan: 0
1897 19:23:37.191802
1898 19:23:37.191866 RX Vref 0 -> 0, step: 1
1899 19:23:37.191925
1900 19:23:37.195480 RX Delay -130 -> 252, step: 16
1901 19:23:37.198743 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1902 19:23:37.205150 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1903 19:23:37.208838 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1904 19:23:37.212135 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1905 19:23:37.215432 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1906 19:23:37.218430 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1907 19:23:37.225269 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1908 19:23:37.228493 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1909 19:23:37.231774 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1910 19:23:37.235327 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1911 19:23:37.238674 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1912 19:23:37.245217 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1913 19:23:37.248914 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1914 19:23:37.252275 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1915 19:23:37.255740 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1916 19:23:37.258837 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1917 19:23:37.262133 ==
1918 19:23:37.262232 Dram Type= 6, Freq= 0, CH_1, rank 1
1919 19:23:37.268817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1920 19:23:37.268921 ==
1921 19:23:37.268987 DQS Delay:
1922 19:23:37.272085 DQS0 = 0, DQS1 = 0
1923 19:23:37.272168 DQM Delay:
1924 19:23:37.275294 DQM0 = 87, DQM1 = 81
1925 19:23:37.275377 DQ Delay:
1926 19:23:37.278609 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =85
1927 19:23:37.282257 DQ4 =93, DQ5 =101, DQ6 =93, DQ7 =77
1928 19:23:37.285437 DQ8 =69, DQ9 =77, DQ10 =85, DQ11 =77
1929 19:23:37.288792 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1930 19:23:37.288873
1931 19:23:37.288937
1932 19:23:37.288996 ==
1933 19:23:37.292078 Dram Type= 6, Freq= 0, CH_1, rank 1
1934 19:23:37.295674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1935 19:23:37.295758 ==
1936 19:23:37.295822
1937 19:23:37.295884
1938 19:23:37.298945 TX Vref Scan disable
1939 19:23:37.302381 == TX Byte 0 ==
1940 19:23:37.305503 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1941 19:23:37.308909 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1942 19:23:37.308989 == TX Byte 1 ==
1943 19:23:37.315810 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1944 19:23:37.319184 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1945 19:23:37.319267 ==
1946 19:23:37.322614 Dram Type= 6, Freq= 0, CH_1, rank 1
1947 19:23:37.325473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1948 19:23:37.325557 ==
1949 19:23:37.340146 TX Vref=22, minBit 8, minWin=27, winSum=449
1950 19:23:37.343460 TX Vref=24, minBit 8, minWin=27, winSum=448
1951 19:23:37.347040 TX Vref=26, minBit 9, minWin=27, winSum=455
1952 19:23:37.350011 TX Vref=28, minBit 13, minWin=27, winSum=457
1953 19:23:37.353808 TX Vref=30, minBit 8, minWin=28, winSum=460
1954 19:23:37.357096 TX Vref=32, minBit 9, minWin=27, winSum=457
1955 19:23:37.363585 [TxChooseVref] Worse bit 8, Min win 28, Win sum 460, Final Vref 30
1956 19:23:37.363670
1957 19:23:37.366963 Final TX Range 1 Vref 30
1958 19:23:37.367047
1959 19:23:37.367111 ==
1960 19:23:37.370285 Dram Type= 6, Freq= 0, CH_1, rank 1
1961 19:23:37.373642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1962 19:23:37.373725 ==
1963 19:23:37.373789
1964 19:23:37.376897
1965 19:23:37.376978 TX Vref Scan disable
1966 19:23:37.380337 == TX Byte 0 ==
1967 19:23:37.383551 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1968 19:23:37.386927 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1969 19:23:37.390340 == TX Byte 1 ==
1970 19:23:37.393524 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1971 19:23:37.396848 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1972 19:23:37.400108
1973 19:23:37.400190 [DATLAT]
1974 19:23:37.400255 Freq=800, CH1 RK1
1975 19:23:37.400315
1976 19:23:37.403763 DATLAT Default: 0xa
1977 19:23:37.403845 0, 0xFFFF, sum = 0
1978 19:23:37.407218 1, 0xFFFF, sum = 0
1979 19:23:37.407303 2, 0xFFFF, sum = 0
1980 19:23:37.410549 3, 0xFFFF, sum = 0
1981 19:23:37.410633 4, 0xFFFF, sum = 0
1982 19:23:37.413617 5, 0xFFFF, sum = 0
1983 19:23:37.413702 6, 0xFFFF, sum = 0
1984 19:23:37.417491 7, 0xFFFF, sum = 0
1985 19:23:37.417577 8, 0xFFFF, sum = 0
1986 19:23:37.420646 9, 0x0, sum = 1
1987 19:23:37.420729 10, 0x0, sum = 2
1988 19:23:37.423563 11, 0x0, sum = 3
1989 19:23:37.423648 12, 0x0, sum = 4
1990 19:23:37.427275 best_step = 10
1991 19:23:37.427360
1992 19:23:37.427425 ==
1993 19:23:37.430394 Dram Type= 6, Freq= 0, CH_1, rank 1
1994 19:23:37.433681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1995 19:23:37.433766 ==
1996 19:23:37.436888 RX Vref Scan: 0
1997 19:23:37.436970
1998 19:23:37.437036 RX Vref 0 -> 0, step: 1
1999 19:23:37.437097
2000 19:23:37.440241 RX Delay -95 -> 252, step: 8
2001 19:23:37.447334 iDelay=209, Bit 0, Center 96 (-7 ~ 200) 208
2002 19:23:37.450398 iDelay=209, Bit 1, Center 88 (-15 ~ 192) 208
2003 19:23:37.453884 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2004 19:23:37.457205 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2005 19:23:37.460802 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
2006 19:23:37.464020 iDelay=209, Bit 5, Center 104 (1 ~ 208) 208
2007 19:23:37.470771 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2008 19:23:37.474126 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2009 19:23:37.477573 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2010 19:23:37.480872 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
2011 19:23:37.484090 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
2012 19:23:37.490706 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2013 19:23:37.494071 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
2014 19:23:37.497314 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2015 19:23:37.500635 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2016 19:23:37.503903 iDelay=209, Bit 15, Center 96 (-15 ~ 208) 224
2017 19:23:37.507659 ==
2018 19:23:37.507743 Dram Type= 6, Freq= 0, CH_1, rank 1
2019 19:23:37.514361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2020 19:23:37.514446 ==
2021 19:23:37.514511 DQS Delay:
2022 19:23:37.517522 DQS0 = 0, DQS1 = 0
2023 19:23:37.517605 DQM Delay:
2024 19:23:37.520824 DQM0 = 91, DQM1 = 83
2025 19:23:37.520907 DQ Delay:
2026 19:23:37.524167 DQ0 =96, DQ1 =88, DQ2 =80, DQ3 =88
2027 19:23:37.527296 DQ4 =92, DQ5 =104, DQ6 =96, DQ7 =88
2028 19:23:37.530976 DQ8 =68, DQ9 =76, DQ10 =84, DQ11 =80
2029 19:23:37.534123 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =96
2030 19:23:37.534207
2031 19:23:37.534272
2032 19:23:37.540820 [DQSOSCAuto] RK1, (LSB)MR18= 0x390d, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 395 ps
2033 19:23:37.544081 CH1 RK1: MR19=606, MR18=390D
2034 19:23:37.550738 CH1_RK1: MR19=0x606, MR18=0x390D, DQSOSC=395, MR23=63, INC=94, DEC=63
2035 19:23:37.554191 [RxdqsGatingPostProcess] freq 800
2036 19:23:37.557783 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2037 19:23:37.560646 Pre-setting of DQS Precalculation
2038 19:23:37.567405 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2039 19:23:37.574205 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2040 19:23:37.580981 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2041 19:23:37.581078
2042 19:23:37.581144
2043 19:23:37.584370 [Calibration Summary] 1600 Mbps
2044 19:23:37.584454 CH 0, Rank 0
2045 19:23:37.587716 SW Impedance : PASS
2046 19:23:37.591259 DUTY Scan : NO K
2047 19:23:37.591344 ZQ Calibration : PASS
2048 19:23:37.594477 Jitter Meter : NO K
2049 19:23:37.597932 CBT Training : PASS
2050 19:23:37.598016 Write leveling : PASS
2051 19:23:37.601281 RX DQS gating : PASS
2052 19:23:37.604783 RX DQ/DQS(RDDQC) : PASS
2053 19:23:37.604866 TX DQ/DQS : PASS
2054 19:23:37.607797 RX DATLAT : PASS
2055 19:23:37.607880 RX DQ/DQS(Engine): PASS
2056 19:23:37.611384 TX OE : NO K
2057 19:23:37.611466 All Pass.
2058 19:23:37.611532
2059 19:23:37.614710 CH 0, Rank 1
2060 19:23:37.614793 SW Impedance : PASS
2061 19:23:37.617724 DUTY Scan : NO K
2062 19:23:37.621242 ZQ Calibration : PASS
2063 19:23:37.621330 Jitter Meter : NO K
2064 19:23:37.624525 CBT Training : PASS
2065 19:23:37.628297 Write leveling : PASS
2066 19:23:37.628380 RX DQS gating : PASS
2067 19:23:37.631136 RX DQ/DQS(RDDQC) : PASS
2068 19:23:37.634547 TX DQ/DQS : PASS
2069 19:23:37.634631 RX DATLAT : PASS
2070 19:23:37.638012 RX DQ/DQS(Engine): PASS
2071 19:23:37.641114 TX OE : NO K
2072 19:23:37.641197 All Pass.
2073 19:23:37.641263
2074 19:23:37.641331 CH 1, Rank 0
2075 19:23:37.644531 SW Impedance : PASS
2076 19:23:37.644614 DUTY Scan : NO K
2077 19:23:37.648101 ZQ Calibration : PASS
2078 19:23:37.651209 Jitter Meter : NO K
2079 19:23:37.651293 CBT Training : PASS
2080 19:23:37.654752 Write leveling : PASS
2081 19:23:37.658016 RX DQS gating : PASS
2082 19:23:37.658100 RX DQ/DQS(RDDQC) : PASS
2083 19:23:37.661350 TX DQ/DQS : PASS
2084 19:23:37.664892 RX DATLAT : PASS
2085 19:23:37.664976 RX DQ/DQS(Engine): PASS
2086 19:23:37.667854 TX OE : NO K
2087 19:23:37.667937 All Pass.
2088 19:23:37.668003
2089 19:23:37.671087 CH 1, Rank 1
2090 19:23:37.671171 SW Impedance : PASS
2091 19:23:37.674632 DUTY Scan : NO K
2092 19:23:37.677855 ZQ Calibration : PASS
2093 19:23:37.677938 Jitter Meter : NO K
2094 19:23:37.681136 CBT Training : PASS
2095 19:23:37.684564 Write leveling : PASS
2096 19:23:37.684649 RX DQS gating : PASS
2097 19:23:37.687859 RX DQ/DQS(RDDQC) : PASS
2098 19:23:37.687942 TX DQ/DQS : PASS
2099 19:23:37.691189 RX DATLAT : PASS
2100 19:23:37.694819 RX DQ/DQS(Engine): PASS
2101 19:23:37.694902 TX OE : NO K
2102 19:23:37.698173 All Pass.
2103 19:23:37.698256
2104 19:23:37.698322 DramC Write-DBI off
2105 19:23:37.701562 PER_BANK_REFRESH: Hybrid Mode
2106 19:23:37.704462 TX_TRACKING: ON
2107 19:23:37.708220 [GetDramInforAfterCalByMRR] Vendor 6.
2108 19:23:37.711202 [GetDramInforAfterCalByMRR] Revision 606.
2109 19:23:37.714412 [GetDramInforAfterCalByMRR] Revision 2 0.
2110 19:23:37.714495 MR0 0x3b3b
2111 19:23:37.714561 MR8 0x5151
2112 19:23:37.721149 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2113 19:23:37.721232
2114 19:23:37.721302 MR0 0x3b3b
2115 19:23:37.721364 MR8 0x5151
2116 19:23:37.724412 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2117 19:23:37.724495
2118 19:23:37.734612 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2119 19:23:37.738468 [FAST_K] Save calibration result to emmc
2120 19:23:37.741331 [FAST_K] Save calibration result to emmc
2121 19:23:37.744784 dram_init: config_dvfs: 1
2122 19:23:37.748325 dramc_set_vcore_voltage set vcore to 662500
2123 19:23:37.751851 Read voltage for 1200, 2
2124 19:23:37.751929 Vio18 = 0
2125 19:23:37.751992 Vcore = 662500
2126 19:23:37.754581 Vdram = 0
2127 19:23:37.754664 Vddq = 0
2128 19:23:37.754759 Vmddr = 0
2129 19:23:37.761842 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2130 19:23:37.764650 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2131 19:23:37.767935 MEM_TYPE=3, freq_sel=15
2132 19:23:37.771346 sv_algorithm_assistance_LP4_1600
2133 19:23:37.774892 ============ PULL DRAM RESETB DOWN ============
2134 19:23:37.778099 ========== PULL DRAM RESETB DOWN end =========
2135 19:23:37.784744 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2136 19:23:37.788418 ===================================
2137 19:23:37.788502 LPDDR4 DRAM CONFIGURATION
2138 19:23:37.791376 ===================================
2139 19:23:37.794845 EX_ROW_EN[0] = 0x0
2140 19:23:37.798253 EX_ROW_EN[1] = 0x0
2141 19:23:37.798367 LP4Y_EN = 0x0
2142 19:23:37.801462 WORK_FSP = 0x0
2143 19:23:37.801578 WL = 0x4
2144 19:23:37.804621 RL = 0x4
2145 19:23:37.804724 BL = 0x2
2146 19:23:37.808006 RPST = 0x0
2147 19:23:37.808110 RD_PRE = 0x0
2148 19:23:37.811418 WR_PRE = 0x1
2149 19:23:37.811519 WR_PST = 0x0
2150 19:23:37.814723 DBI_WR = 0x0
2151 19:23:37.814827 DBI_RD = 0x0
2152 19:23:37.818207 OTF = 0x1
2153 19:23:37.821718 ===================================
2154 19:23:37.824686 ===================================
2155 19:23:37.824786 ANA top config
2156 19:23:37.828467 ===================================
2157 19:23:37.831509 DLL_ASYNC_EN = 0
2158 19:23:37.834678 ALL_SLAVE_EN = 0
2159 19:23:37.834779 NEW_RANK_MODE = 1
2160 19:23:37.838228 DLL_IDLE_MODE = 1
2161 19:23:37.841580 LP45_APHY_COMB_EN = 1
2162 19:23:37.844718 TX_ODT_DIS = 1
2163 19:23:37.848373 NEW_8X_MODE = 1
2164 19:23:37.851552 ===================================
2165 19:23:37.854939 ===================================
2166 19:23:37.855071 data_rate = 2400
2167 19:23:37.858194 CKR = 1
2168 19:23:37.861401 DQ_P2S_RATIO = 8
2169 19:23:37.864626 ===================================
2170 19:23:37.868038 CA_P2S_RATIO = 8
2171 19:23:37.871326 DQ_CA_OPEN = 0
2172 19:23:37.874614 DQ_SEMI_OPEN = 0
2173 19:23:37.874699 CA_SEMI_OPEN = 0
2174 19:23:37.878041 CA_FULL_RATE = 0
2175 19:23:37.881649 DQ_CKDIV4_EN = 0
2176 19:23:37.884942 CA_CKDIV4_EN = 0
2177 19:23:37.888352 CA_PREDIV_EN = 0
2178 19:23:37.891623 PH8_DLY = 17
2179 19:23:37.891708 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2180 19:23:37.894811 DQ_AAMCK_DIV = 4
2181 19:23:37.898257 CA_AAMCK_DIV = 4
2182 19:23:37.901650 CA_ADMCK_DIV = 4
2183 19:23:37.905020 DQ_TRACK_CA_EN = 0
2184 19:23:37.908321 CA_PICK = 1200
2185 19:23:37.908405 CA_MCKIO = 1200
2186 19:23:37.911743 MCKIO_SEMI = 0
2187 19:23:37.915006 PLL_FREQ = 2366
2188 19:23:37.918349 DQ_UI_PI_RATIO = 32
2189 19:23:37.921456 CA_UI_PI_RATIO = 0
2190 19:23:37.925017 ===================================
2191 19:23:37.928424 ===================================
2192 19:23:37.931706 memory_type:LPDDR4
2193 19:23:37.931789 GP_NUM : 10
2194 19:23:37.935003 SRAM_EN : 1
2195 19:23:37.935086 MD32_EN : 0
2196 19:23:37.938290 ===================================
2197 19:23:37.941662 [ANA_INIT] >>>>>>>>>>>>>>
2198 19:23:37.944915 <<<<<< [CONFIGURE PHASE]: ANA_TX
2199 19:23:37.948200 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2200 19:23:37.951455 ===================================
2201 19:23:37.955275 data_rate = 2400,PCW = 0X5b00
2202 19:23:37.958217 ===================================
2203 19:23:37.961550 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2204 19:23:37.964799 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2205 19:23:37.971758 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2206 19:23:37.974759 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2207 19:23:37.981748 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2208 19:23:37.984947 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2209 19:23:37.985038 [ANA_INIT] flow start
2210 19:23:37.988352 [ANA_INIT] PLL >>>>>>>>
2211 19:23:37.991473 [ANA_INIT] PLL <<<<<<<<
2212 19:23:37.991560 [ANA_INIT] MIDPI >>>>>>>>
2213 19:23:37.994915 [ANA_INIT] MIDPI <<<<<<<<
2214 19:23:37.998289 [ANA_INIT] DLL >>>>>>>>
2215 19:23:37.998375 [ANA_INIT] DLL <<<<<<<<
2216 19:23:38.001673 [ANA_INIT] flow end
2217 19:23:38.005022 ============ LP4 DIFF to SE enter ============
2218 19:23:38.008348 ============ LP4 DIFF to SE exit ============
2219 19:23:38.011605 [ANA_INIT] <<<<<<<<<<<<<
2220 19:23:38.014875 [Flow] Enable top DCM control >>>>>
2221 19:23:38.018209 [Flow] Enable top DCM control <<<<<
2222 19:23:38.021293 Enable DLL master slave shuffle
2223 19:23:38.028365 ==============================================================
2224 19:23:38.028459 Gating Mode config
2225 19:23:38.034967 ==============================================================
2226 19:23:38.035063 Config description:
2227 19:23:38.044916 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2228 19:23:38.051536 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2229 19:23:38.058130 SELPH_MODE 0: By rank 1: By Phase
2230 19:23:38.061558 ==============================================================
2231 19:23:38.064779 GAT_TRACK_EN = 1
2232 19:23:38.068637 RX_GATING_MODE = 2
2233 19:23:38.071847 RX_GATING_TRACK_MODE = 2
2234 19:23:38.075236 SELPH_MODE = 1
2235 19:23:38.078202 PICG_EARLY_EN = 1
2236 19:23:38.081509 VALID_LAT_VALUE = 1
2237 19:23:38.085112 ==============================================================
2238 19:23:38.088304 Enter into Gating configuration >>>>
2239 19:23:38.091830 Exit from Gating configuration <<<<
2240 19:23:38.094915 Enter into DVFS_PRE_config >>>>>
2241 19:23:38.108498 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2242 19:23:38.111816 Exit from DVFS_PRE_config <<<<<
2243 19:23:38.111904 Enter into PICG configuration >>>>
2244 19:23:38.115231 Exit from PICG configuration <<<<
2245 19:23:38.118582 [RX_INPUT] configuration >>>>>
2246 19:23:38.121876 [RX_INPUT] configuration <<<<<
2247 19:23:38.128451 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2248 19:23:38.132044 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2249 19:23:38.138165 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2250 19:23:38.145002 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2251 19:23:38.151456 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2252 19:23:38.158305 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2253 19:23:38.161774 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2254 19:23:38.164802 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2255 19:23:38.168078 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2256 19:23:38.174764 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2257 19:23:38.178089 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2258 19:23:38.181594 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2259 19:23:38.184714 ===================================
2260 19:23:38.188084 LPDDR4 DRAM CONFIGURATION
2261 19:23:38.191484 ===================================
2262 19:23:38.191570 EX_ROW_EN[0] = 0x0
2263 19:23:38.194881 EX_ROW_EN[1] = 0x0
2264 19:23:38.198344 LP4Y_EN = 0x0
2265 19:23:38.198429 WORK_FSP = 0x0
2266 19:23:38.201574 WL = 0x4
2267 19:23:38.201659 RL = 0x4
2268 19:23:38.205244 BL = 0x2
2269 19:23:38.205357 RPST = 0x0
2270 19:23:38.208126 RD_PRE = 0x0
2271 19:23:38.208209 WR_PRE = 0x1
2272 19:23:38.211565 WR_PST = 0x0
2273 19:23:38.211649 DBI_WR = 0x0
2274 19:23:38.214866 DBI_RD = 0x0
2275 19:23:38.214950 OTF = 0x1
2276 19:23:38.218287 ===================================
2277 19:23:38.221437 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2278 19:23:38.228220 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2279 19:23:38.231447 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2280 19:23:38.235121 ===================================
2281 19:23:38.238425 LPDDR4 DRAM CONFIGURATION
2282 19:23:38.241655 ===================================
2283 19:23:38.241740 EX_ROW_EN[0] = 0x10
2284 19:23:38.245018 EX_ROW_EN[1] = 0x0
2285 19:23:38.245102 LP4Y_EN = 0x0
2286 19:23:38.248169 WORK_FSP = 0x0
2287 19:23:38.248253 WL = 0x4
2288 19:23:38.251503 RL = 0x4
2289 19:23:38.251587 BL = 0x2
2290 19:23:38.254969 RPST = 0x0
2291 19:23:38.258433 RD_PRE = 0x0
2292 19:23:38.258517 WR_PRE = 0x1
2293 19:23:38.261787 WR_PST = 0x0
2294 19:23:38.261893 DBI_WR = 0x0
2295 19:23:38.265220 DBI_RD = 0x0
2296 19:23:38.265309 OTF = 0x1
2297 19:23:38.268228 ===================================
2298 19:23:38.274806 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2299 19:23:38.274886 ==
2300 19:23:38.278269 Dram Type= 6, Freq= 0, CH_0, rank 0
2301 19:23:38.281903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2302 19:23:38.282022 ==
2303 19:23:38.285083 [Duty_Offset_Calibration]
2304 19:23:38.285162 B0:2 B1:0 CA:1
2305 19:23:38.285224
2306 19:23:38.288335 [DutyScan_Calibration_Flow] k_type=0
2307 19:23:38.298334
2308 19:23:38.298415 ==CLK 0==
2309 19:23:38.302189 Final CLK duty delay cell = -4
2310 19:23:38.305521 [-4] MAX Duty = 5031%(X100), DQS PI = 26
2311 19:23:38.309102 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2312 19:23:38.311894 [-4] AVG Duty = 4953%(X100)
2313 19:23:38.311973
2314 19:23:38.315280 CH0 CLK Duty spec in!! Max-Min= 156%
2315 19:23:38.318525 [DutyScan_Calibration_Flow] ====Done====
2316 19:23:38.318604
2317 19:23:38.322333 [DutyScan_Calibration_Flow] k_type=1
2318 19:23:38.337407
2319 19:23:38.337486 ==DQS 0 ==
2320 19:23:38.340747 Final DQS duty delay cell = 0
2321 19:23:38.344068 [0] MAX Duty = 5187%(X100), DQS PI = 30
2322 19:23:38.347401 [0] MIN Duty = 4938%(X100), DQS PI = 0
2323 19:23:38.347480 [0] AVG Duty = 5062%(X100)
2324 19:23:38.350992
2325 19:23:38.351071 ==DQS 1 ==
2326 19:23:38.354031 Final DQS duty delay cell = -4
2327 19:23:38.357354 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2328 19:23:38.360616 [-4] MIN Duty = 4907%(X100), DQS PI = 8
2329 19:23:38.363946 [-4] AVG Duty = 5015%(X100)
2330 19:23:38.364025
2331 19:23:38.367404 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2332 19:23:38.367483
2333 19:23:38.370771 CH0 DQS 1 Duty spec in!! Max-Min= 217%
2334 19:23:38.374147 [DutyScan_Calibration_Flow] ====Done====
2335 19:23:38.374230
2336 19:23:38.377763 [DutyScan_Calibration_Flow] k_type=3
2337 19:23:38.394284
2338 19:23:38.394420 ==DQM 0 ==
2339 19:23:38.397684 Final DQM duty delay cell = 0
2340 19:23:38.401043 [0] MAX Duty = 5062%(X100), DQS PI = 24
2341 19:23:38.404414 [0] MIN Duty = 4813%(X100), DQS PI = 0
2342 19:23:38.404496 [0] AVG Duty = 4937%(X100)
2343 19:23:38.407678
2344 19:23:38.407759 ==DQM 1 ==
2345 19:23:38.410841 Final DQM duty delay cell = 0
2346 19:23:38.414244 [0] MAX Duty = 5187%(X100), DQS PI = 46
2347 19:23:38.417588 [0] MIN Duty = 5000%(X100), DQS PI = 22
2348 19:23:38.417675 [0] AVG Duty = 5093%(X100)
2349 19:23:38.420833
2350 19:23:38.424500 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2351 19:23:38.424585
2352 19:23:38.427427 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2353 19:23:38.430814 [DutyScan_Calibration_Flow] ====Done====
2354 19:23:38.430899
2355 19:23:38.434069 [DutyScan_Calibration_Flow] k_type=2
2356 19:23:38.450777
2357 19:23:38.450893 ==DQ 0 ==
2358 19:23:38.454375 Final DQ duty delay cell = -4
2359 19:23:38.457538 [-4] MAX Duty = 5062%(X100), DQS PI = 34
2360 19:23:38.460848 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2361 19:23:38.464229 [-4] AVG Duty = 4968%(X100)
2362 19:23:38.464314
2363 19:23:38.464398 ==DQ 1 ==
2364 19:23:38.467615 Final DQ duty delay cell = 4
2365 19:23:38.470990 [4] MAX Duty = 5093%(X100), DQS PI = 4
2366 19:23:38.474371 [4] MIN Duty = 5031%(X100), DQS PI = 0
2367 19:23:38.474455 [4] AVG Duty = 5062%(X100)
2368 19:23:38.474539
2369 19:23:38.477720 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2370 19:23:38.480593
2371 19:23:38.480714 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2372 19:23:38.487238 [DutyScan_Calibration_Flow] ====Done====
2373 19:23:38.487326 ==
2374 19:23:38.490641 Dram Type= 6, Freq= 0, CH_1, rank 0
2375 19:23:38.494049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2376 19:23:38.494137 ==
2377 19:23:38.497422 [Duty_Offset_Calibration]
2378 19:23:38.497507 B0:0 B1:-1 CA:2
2379 19:23:38.497591
2380 19:23:38.500784 [DutyScan_Calibration_Flow] k_type=0
2381 19:23:38.511044
2382 19:23:38.511136 ==CLK 0==
2383 19:23:38.514031 Final CLK duty delay cell = 0
2384 19:23:38.517509 [0] MAX Duty = 5156%(X100), DQS PI = 16
2385 19:23:38.520683 [0] MIN Duty = 4938%(X100), DQS PI = 44
2386 19:23:38.520769 [0] AVG Duty = 5047%(X100)
2387 19:23:38.524091
2388 19:23:38.527328 CH1 CLK Duty spec in!! Max-Min= 218%
2389 19:23:38.530662 [DutyScan_Calibration_Flow] ====Done====
2390 19:23:38.530747
2391 19:23:38.533927 [DutyScan_Calibration_Flow] k_type=1
2392 19:23:38.550217
2393 19:23:38.550323 ==DQS 0 ==
2394 19:23:38.553429 Final DQS duty delay cell = 0
2395 19:23:38.556750 [0] MAX Duty = 5093%(X100), DQS PI = 24
2396 19:23:38.560160 [0] MIN Duty = 4969%(X100), DQS PI = 0
2397 19:23:38.560288 [0] AVG Duty = 5031%(X100)
2398 19:23:38.563326
2399 19:23:38.563411 ==DQS 1 ==
2400 19:23:38.566856 Final DQS duty delay cell = 0
2401 19:23:38.570131 [0] MAX Duty = 5156%(X100), DQS PI = 0
2402 19:23:38.573505 [0] MIN Duty = 4844%(X100), DQS PI = 36
2403 19:23:38.573590 [0] AVG Duty = 5000%(X100)
2404 19:23:38.577134
2405 19:23:38.580064 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2406 19:23:38.580149
2407 19:23:38.583675 CH1 DQS 1 Duty spec in!! Max-Min= 312%
2408 19:23:38.587121 [DutyScan_Calibration_Flow] ====Done====
2409 19:23:38.587212
2410 19:23:38.590349 [DutyScan_Calibration_Flow] k_type=3
2411 19:23:38.606873
2412 19:23:38.606988 ==DQM 0 ==
2413 19:23:38.609820 Final DQM duty delay cell = 4
2414 19:23:38.613476 [4] MAX Duty = 5093%(X100), DQS PI = 6
2415 19:23:38.616625 [4] MIN Duty = 4969%(X100), DQS PI = 28
2416 19:23:38.616726 [4] AVG Duty = 5031%(X100)
2417 19:23:38.616869
2418 19:23:38.620114 ==DQM 1 ==
2419 19:23:38.623642 Final DQM duty delay cell = -4
2420 19:23:38.626613 [-4] MAX Duty = 5000%(X100), DQS PI = 62
2421 19:23:38.630167 [-4] MIN Duty = 4751%(X100), DQS PI = 36
2422 19:23:38.633481 [-4] AVG Duty = 4875%(X100)
2423 19:23:38.633566
2424 19:23:38.636734 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2425 19:23:38.636819
2426 19:23:38.640114 CH1 DQM 1 Duty spec in!! Max-Min= 249%
2427 19:23:38.643456 [DutyScan_Calibration_Flow] ====Done====
2428 19:23:38.643540
2429 19:23:38.646686 [DutyScan_Calibration_Flow] k_type=2
2430 19:23:38.663600
2431 19:23:38.663722 ==DQ 0 ==
2432 19:23:38.666667 Final DQ duty delay cell = 0
2433 19:23:38.669884 [0] MAX Duty = 5031%(X100), DQS PI = 20
2434 19:23:38.673275 [0] MIN Duty = 4938%(X100), DQS PI = 0
2435 19:23:38.673381 [0] AVG Duty = 4984%(X100)
2436 19:23:38.676720
2437 19:23:38.676803 ==DQ 1 ==
2438 19:23:38.680209 Final DQ duty delay cell = 0
2439 19:23:38.683495 [0] MAX Duty = 5031%(X100), DQS PI = 2
2440 19:23:38.686851 [0] MIN Duty = 4813%(X100), DQS PI = 34
2441 19:23:38.686938 [0] AVG Duty = 4922%(X100)
2442 19:23:38.687022
2443 19:23:38.690040 CH1 DQ 0 Duty spec in!! Max-Min= 93%
2444 19:23:38.690125
2445 19:23:38.693716 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2446 19:23:38.700198 [DutyScan_Calibration_Flow] ====Done====
2447 19:23:38.703367 nWR fixed to 30
2448 19:23:38.703456 [ModeRegInit_LP4] CH0 RK0
2449 19:23:38.707087 [ModeRegInit_LP4] CH0 RK1
2450 19:23:38.710376 [ModeRegInit_LP4] CH1 RK0
2451 19:23:38.710461 [ModeRegInit_LP4] CH1 RK1
2452 19:23:38.713427 match AC timing 7
2453 19:23:38.716804 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2454 19:23:38.720289 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2455 19:23:38.726939 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2456 19:23:38.730199 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2457 19:23:38.736961 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2458 19:23:38.737050 ==
2459 19:23:38.740133 Dram Type= 6, Freq= 0, CH_0, rank 0
2460 19:23:38.743523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2461 19:23:38.743607 ==
2462 19:23:38.750181 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2463 19:23:38.753305 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2464 19:23:38.763145 [CA 0] Center 38 (7~69) winsize 63
2465 19:23:38.766510 [CA 1] Center 38 (7~69) winsize 63
2466 19:23:38.769565 [CA 2] Center 34 (4~65) winsize 62
2467 19:23:38.773356 [CA 3] Center 34 (4~65) winsize 62
2468 19:23:38.776268 [CA 4] Center 34 (4~64) winsize 61
2469 19:23:38.779633 [CA 5] Center 32 (2~63) winsize 62
2470 19:23:38.779719
2471 19:23:38.782844 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2472 19:23:38.782932
2473 19:23:38.786715 [CATrainingPosCal] consider 1 rank data
2474 19:23:38.790064 u2DelayCellTimex100 = 270/100 ps
2475 19:23:38.793332 CA0 delay=38 (7~69),Diff = 6 PI (28 cell)
2476 19:23:38.796747 CA1 delay=38 (7~69),Diff = 6 PI (28 cell)
2477 19:23:38.803169 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2478 19:23:38.806820 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2479 19:23:38.809591 CA4 delay=34 (4~64),Diff = 2 PI (9 cell)
2480 19:23:38.812894 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2481 19:23:38.812998
2482 19:23:38.816256 CA PerBit enable=1, Macro0, CA PI delay=32
2483 19:23:38.816341
2484 19:23:38.819780 [CBTSetCACLKResult] CA Dly = 32
2485 19:23:38.819865 CS Dly: 6 (0~37)
2486 19:23:38.822959 ==
2487 19:23:38.823101 Dram Type= 6, Freq= 0, CH_0, rank 1
2488 19:23:38.829558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2489 19:23:38.829645 ==
2490 19:23:38.833198 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2491 19:23:38.839692 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2492 19:23:38.848749 [CA 0] Center 38 (8~69) winsize 62
2493 19:23:38.852027 [CA 1] Center 38 (7~69) winsize 63
2494 19:23:38.855288 [CA 2] Center 35 (5~66) winsize 62
2495 19:23:38.858653 [CA 3] Center 35 (5~66) winsize 62
2496 19:23:38.861971 [CA 4] Center 34 (4~65) winsize 62
2497 19:23:38.865427 [CA 5] Center 33 (3~63) winsize 61
2498 19:23:38.865511
2499 19:23:38.868837 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2500 19:23:38.868921
2501 19:23:38.872246 [CATrainingPosCal] consider 2 rank data
2502 19:23:38.875541 u2DelayCellTimex100 = 270/100 ps
2503 19:23:38.878927 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2504 19:23:38.882222 CA1 delay=38 (7~69),Diff = 5 PI (24 cell)
2505 19:23:38.888682 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
2506 19:23:38.892072 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2507 19:23:38.895427 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2508 19:23:38.898800 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2509 19:23:38.898885
2510 19:23:38.902152 CA PerBit enable=1, Macro0, CA PI delay=33
2511 19:23:38.902236
2512 19:23:38.905504 [CBTSetCACLKResult] CA Dly = 33
2513 19:23:38.905589 CS Dly: 7 (0~39)
2514 19:23:38.905672
2515 19:23:38.908870 ----->DramcWriteLeveling(PI) begin...
2516 19:23:38.908955 ==
2517 19:23:38.912235 Dram Type= 6, Freq= 0, CH_0, rank 0
2518 19:23:38.919017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2519 19:23:38.919106 ==
2520 19:23:38.922343 Write leveling (Byte 0): 34 => 34
2521 19:23:38.925828 Write leveling (Byte 1): 30 => 30
2522 19:23:38.925914 DramcWriteLeveling(PI) end<-----
2523 19:23:38.928904
2524 19:23:38.928988 ==
2525 19:23:38.932426 Dram Type= 6, Freq= 0, CH_0, rank 0
2526 19:23:38.935969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2527 19:23:38.936054 ==
2528 19:23:38.938979 [Gating] SW mode calibration
2529 19:23:38.945483 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2530 19:23:38.949044 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2531 19:23:38.955848 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2532 19:23:38.959177 0 15 4 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
2533 19:23:38.962194 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2534 19:23:38.969354 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2535 19:23:38.972596 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2536 19:23:38.975730 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2537 19:23:38.982338 0 15 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
2538 19:23:38.985666 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
2539 19:23:38.988967 1 0 0 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
2540 19:23:38.995929 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2541 19:23:38.999325 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2542 19:23:39.002258 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2543 19:23:39.005631 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2544 19:23:39.012425 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2545 19:23:39.015747 1 0 24 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
2546 19:23:39.019440 1 0 28 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
2547 19:23:39.025728 1 1 0 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
2548 19:23:39.029282 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2549 19:23:39.032686 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2550 19:23:39.039399 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2551 19:23:39.042842 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2552 19:23:39.046007 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2553 19:23:39.052502 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2554 19:23:39.055819 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2555 19:23:39.059592 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2556 19:23:39.066202 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 19:23:39.069428 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 19:23:39.072661 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 19:23:39.076034 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 19:23:39.082961 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 19:23:39.086270 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 19:23:39.089520 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 19:23:39.095813 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 19:23:39.099383 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 19:23:39.102676 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 19:23:39.109306 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 19:23:39.112791 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 19:23:39.115678 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 19:23:39.122462 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2570 19:23:39.125654 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2571 19:23:39.129402 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2572 19:23:39.132295 Total UI for P1: 0, mck2ui 16
2573 19:23:39.135685 best dqsien dly found for B0: ( 1, 3, 26)
2574 19:23:39.142061 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2575 19:23:39.142154 Total UI for P1: 0, mck2ui 16
2576 19:23:39.148782 best dqsien dly found for B1: ( 1, 3, 30)
2577 19:23:39.152065 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2578 19:23:39.155596 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2579 19:23:39.155732
2580 19:23:39.158918 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2581 19:23:39.162515 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2582 19:23:39.165512 [Gating] SW calibration Done
2583 19:23:39.165596 ==
2584 19:23:39.168814 Dram Type= 6, Freq= 0, CH_0, rank 0
2585 19:23:39.172591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2586 19:23:39.172674 ==
2587 19:23:39.175926 RX Vref Scan: 0
2588 19:23:39.176008
2589 19:23:39.176073 RX Vref 0 -> 0, step: 1
2590 19:23:39.176132
2591 19:23:39.178801 RX Delay -40 -> 252, step: 8
2592 19:23:39.182515 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
2593 19:23:39.188946 iDelay=208, Bit 1, Center 123 (56 ~ 191) 136
2594 19:23:39.192476 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2595 19:23:39.195638 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2596 19:23:39.199093 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2597 19:23:39.202135 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2598 19:23:39.208918 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2599 19:23:39.212136 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2600 19:23:39.215873 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
2601 19:23:39.218982 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2602 19:23:39.222285 iDelay=208, Bit 10, Center 111 (48 ~ 175) 128
2603 19:23:39.228960 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2604 19:23:39.232381 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2605 19:23:39.235543 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2606 19:23:39.239047 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2607 19:23:39.242432 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2608 19:23:39.245445 ==
2609 19:23:39.245529 Dram Type= 6, Freq= 0, CH_0, rank 0
2610 19:23:39.252050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2611 19:23:39.252144 ==
2612 19:23:39.252246 DQS Delay:
2613 19:23:39.255497 DQS0 = 0, DQS1 = 0
2614 19:23:39.255581 DQM Delay:
2615 19:23:39.259039 DQM0 = 123, DQM1 = 110
2616 19:23:39.259124 DQ Delay:
2617 19:23:39.262219 DQ0 =123, DQ1 =123, DQ2 =119, DQ3 =119
2618 19:23:39.265581 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2619 19:23:39.268839 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =107
2620 19:23:39.272132 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2621 19:23:39.272218
2622 19:23:39.272319
2623 19:23:39.272407 ==
2624 19:23:39.275480 Dram Type= 6, Freq= 0, CH_0, rank 0
2625 19:23:39.278826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2626 19:23:39.282302 ==
2627 19:23:39.282428
2628 19:23:39.282557
2629 19:23:39.282616 TX Vref Scan disable
2630 19:23:39.285591 == TX Byte 0 ==
2631 19:23:39.289118 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2632 19:23:39.292342 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2633 19:23:39.295637 == TX Byte 1 ==
2634 19:23:39.299028 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2635 19:23:39.302174 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2636 19:23:39.305550 ==
2637 19:23:39.305628 Dram Type= 6, Freq= 0, CH_0, rank 0
2638 19:23:39.312281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2639 19:23:39.312364 ==
2640 19:23:39.323494 TX Vref=22, minBit 5, minWin=23, winSum=401
2641 19:23:39.326838 TX Vref=24, minBit 7, minWin=23, winSum=404
2642 19:23:39.330066 TX Vref=26, minBit 0, minWin=24, winSum=413
2643 19:23:39.333488 TX Vref=28, minBit 1, minWin=24, winSum=415
2644 19:23:39.336948 TX Vref=30, minBit 4, minWin=24, winSum=418
2645 19:23:39.339844 TX Vref=32, minBit 0, minWin=25, winSum=416
2646 19:23:39.346657 [TxChooseVref] Worse bit 0, Min win 25, Win sum 416, Final Vref 32
2647 19:23:39.346761
2648 19:23:39.349909 Final TX Range 1 Vref 32
2649 19:23:39.350008
2650 19:23:39.350072 ==
2651 19:23:39.353527 Dram Type= 6, Freq= 0, CH_0, rank 0
2652 19:23:39.356911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2653 19:23:39.356999 ==
2654 19:23:39.357067
2655 19:23:39.359965
2656 19:23:39.360051 TX Vref Scan disable
2657 19:23:39.363173 == TX Byte 0 ==
2658 19:23:39.366889 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2659 19:23:39.370305 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2660 19:23:39.373205 == TX Byte 1 ==
2661 19:23:39.376881 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2662 19:23:39.380270 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2663 19:23:39.380364
2664 19:23:39.383458 [DATLAT]
2665 19:23:39.383549 Freq=1200, CH0 RK0
2666 19:23:39.383636
2667 19:23:39.387146 DATLAT Default: 0xd
2668 19:23:39.387232 0, 0xFFFF, sum = 0
2669 19:23:39.390059 1, 0xFFFF, sum = 0
2670 19:23:39.390145 2, 0xFFFF, sum = 0
2671 19:23:39.393559 3, 0xFFFF, sum = 0
2672 19:23:39.393648 4, 0xFFFF, sum = 0
2673 19:23:39.396725 5, 0xFFFF, sum = 0
2674 19:23:39.396813 6, 0xFFFF, sum = 0
2675 19:23:39.400261 7, 0xFFFF, sum = 0
2676 19:23:39.400348 8, 0xFFFF, sum = 0
2677 19:23:39.403546 9, 0xFFFF, sum = 0
2678 19:23:39.406476 10, 0xFFFF, sum = 0
2679 19:23:39.406565 11, 0xFFFF, sum = 0
2680 19:23:39.409886 12, 0x0, sum = 1
2681 19:23:39.409972 13, 0x0, sum = 2
2682 19:23:39.410057 14, 0x0, sum = 3
2683 19:23:39.413219 15, 0x0, sum = 4
2684 19:23:39.413328 best_step = 13
2685 19:23:39.413425
2686 19:23:39.416582 ==
2687 19:23:39.416682 Dram Type= 6, Freq= 0, CH_0, rank 0
2688 19:23:39.423692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2689 19:23:39.423793 ==
2690 19:23:39.423884 RX Vref Scan: 1
2691 19:23:39.423964
2692 19:23:39.427158 Set Vref Range= 32 -> 127
2693 19:23:39.427244
2694 19:23:39.430283 RX Vref 32 -> 127, step: 1
2695 19:23:39.430369
2696 19:23:39.433644 RX Delay -13 -> 252, step: 4
2697 19:23:39.433728
2698 19:23:39.436601 Set Vref, RX VrefLevel [Byte0]: 32
2699 19:23:39.439931 [Byte1]: 32
2700 19:23:39.440016
2701 19:23:39.443286 Set Vref, RX VrefLevel [Byte0]: 33
2702 19:23:39.446522 [Byte1]: 33
2703 19:23:39.446611
2704 19:23:39.450155 Set Vref, RX VrefLevel [Byte0]: 34
2705 19:23:39.453502 [Byte1]: 34
2706 19:23:39.457554
2707 19:23:39.457643 Set Vref, RX VrefLevel [Byte0]: 35
2708 19:23:39.460798 [Byte1]: 35
2709 19:23:39.465163
2710 19:23:39.465253 Set Vref, RX VrefLevel [Byte0]: 36
2711 19:23:39.468587 [Byte1]: 36
2712 19:23:39.473289
2713 19:23:39.473419 Set Vref, RX VrefLevel [Byte0]: 37
2714 19:23:39.476355 [Byte1]: 37
2715 19:23:39.480928
2716 19:23:39.481019 Set Vref, RX VrefLevel [Byte0]: 38
2717 19:23:39.484227 [Byte1]: 38
2718 19:23:39.488778
2719 19:23:39.492403 Set Vref, RX VrefLevel [Byte0]: 39
2720 19:23:39.495745 [Byte1]: 39
2721 19:23:39.495832
2722 19:23:39.498581 Set Vref, RX VrefLevel [Byte0]: 40
2723 19:23:39.502028 [Byte1]: 40
2724 19:23:39.502114
2725 19:23:39.505251 Set Vref, RX VrefLevel [Byte0]: 41
2726 19:23:39.508651 [Byte1]: 41
2727 19:23:39.512793
2728 19:23:39.512882 Set Vref, RX VrefLevel [Byte0]: 42
2729 19:23:39.515744 [Byte1]: 42
2730 19:23:39.520460
2731 19:23:39.520548 Set Vref, RX VrefLevel [Byte0]: 43
2732 19:23:39.524055 [Byte1]: 43
2733 19:23:39.528306
2734 19:23:39.528392 Set Vref, RX VrefLevel [Byte0]: 44
2735 19:23:39.531789 [Byte1]: 44
2736 19:23:39.536575
2737 19:23:39.536660 Set Vref, RX VrefLevel [Byte0]: 45
2738 19:23:39.539432 [Byte1]: 45
2739 19:23:39.544157
2740 19:23:39.544243 Set Vref, RX VrefLevel [Byte0]: 46
2741 19:23:39.547454 [Byte1]: 46
2742 19:23:39.552307
2743 19:23:39.552393 Set Vref, RX VrefLevel [Byte0]: 47
2744 19:23:39.555269 [Byte1]: 47
2745 19:23:39.559750
2746 19:23:39.559835 Set Vref, RX VrefLevel [Byte0]: 48
2747 19:23:39.563166 [Byte1]: 48
2748 19:23:39.567700
2749 19:23:39.567787 Set Vref, RX VrefLevel [Byte0]: 49
2750 19:23:39.571164 [Byte1]: 49
2751 19:23:39.575723
2752 19:23:39.575809 Set Vref, RX VrefLevel [Byte0]: 50
2753 19:23:39.578910 [Byte1]: 50
2754 19:23:39.583845
2755 19:23:39.583936 Set Vref, RX VrefLevel [Byte0]: 51
2756 19:23:39.587125 [Byte1]: 51
2757 19:23:39.591599
2758 19:23:39.591685 Set Vref, RX VrefLevel [Byte0]: 52
2759 19:23:39.594739 [Byte1]: 52
2760 19:23:39.599750
2761 19:23:39.599836 Set Vref, RX VrefLevel [Byte0]: 53
2762 19:23:39.602807 [Byte1]: 53
2763 19:23:39.607449
2764 19:23:39.607538 Set Vref, RX VrefLevel [Byte0]: 54
2765 19:23:39.610806 [Byte1]: 54
2766 19:23:39.615063
2767 19:23:39.615148 Set Vref, RX VrefLevel [Byte0]: 55
2768 19:23:39.618311 [Byte1]: 55
2769 19:23:39.622987
2770 19:23:39.623071 Set Vref, RX VrefLevel [Byte0]: 56
2771 19:23:39.626241 [Byte1]: 56
2772 19:23:39.631055
2773 19:23:39.631139 Set Vref, RX VrefLevel [Byte0]: 57
2774 19:23:39.634338 [Byte1]: 57
2775 19:23:39.639010
2776 19:23:39.639094 Set Vref, RX VrefLevel [Byte0]: 58
2777 19:23:39.642297 [Byte1]: 58
2778 19:23:39.646683
2779 19:23:39.646773 Set Vref, RX VrefLevel [Byte0]: 59
2780 19:23:39.650092 [Byte1]: 59
2781 19:23:39.654651
2782 19:23:39.654736 Set Vref, RX VrefLevel [Byte0]: 60
2783 19:23:39.657975 [Byte1]: 60
2784 19:23:39.662742
2785 19:23:39.662827 Set Vref, RX VrefLevel [Byte0]: 61
2786 19:23:39.665813 [Byte1]: 61
2787 19:23:39.670724
2788 19:23:39.670809 Set Vref, RX VrefLevel [Byte0]: 62
2789 19:23:39.673929 [Byte1]: 62
2790 19:23:39.678140
2791 19:23:39.678224 Set Vref, RX VrefLevel [Byte0]: 63
2792 19:23:39.681599 [Byte1]: 63
2793 19:23:39.686054
2794 19:23:39.686144 Set Vref, RX VrefLevel [Byte0]: 64
2795 19:23:39.689521 [Byte1]: 64
2796 19:23:39.694182
2797 19:23:39.694268 Set Vref, RX VrefLevel [Byte0]: 65
2798 19:23:39.697574 [Byte1]: 65
2799 19:23:39.701827
2800 19:23:39.701911 Set Vref, RX VrefLevel [Byte0]: 66
2801 19:23:39.705436 [Byte1]: 66
2802 19:23:39.710070
2803 19:23:39.710157 Set Vref, RX VrefLevel [Byte0]: 67
2804 19:23:39.713440 [Byte1]: 67
2805 19:23:39.717911
2806 19:23:39.717996 Set Vref, RX VrefLevel [Byte0]: 68
2807 19:23:39.720993 [Byte1]: 68
2808 19:23:39.725755
2809 19:23:39.725838 Set Vref, RX VrefLevel [Byte0]: 69
2810 19:23:39.729010 [Byte1]: 69
2811 19:23:39.733315
2812 19:23:39.733413 Final RX Vref Byte 0 = 60 to rank0
2813 19:23:39.736676 Final RX Vref Byte 1 = 48 to rank0
2814 19:23:39.740167 Final RX Vref Byte 0 = 60 to rank1
2815 19:23:39.743487 Final RX Vref Byte 1 = 48 to rank1==
2816 19:23:39.746803 Dram Type= 6, Freq= 0, CH_0, rank 0
2817 19:23:39.753998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2818 19:23:39.754089 ==
2819 19:23:39.754174 DQS Delay:
2820 19:23:39.754251 DQS0 = 0, DQS1 = 0
2821 19:23:39.757006 DQM Delay:
2822 19:23:39.757089 DQM0 = 123, DQM1 = 108
2823 19:23:39.760162 DQ Delay:
2824 19:23:39.763590 DQ0 =122, DQ1 =124, DQ2 =120, DQ3 =120
2825 19:23:39.766810 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2826 19:23:39.770164 DQ8 =100, DQ9 =94, DQ10 =110, DQ11 =104
2827 19:23:39.773568 DQ12 =114, DQ13 =110, DQ14 =122, DQ15 =116
2828 19:23:39.773652
2829 19:23:39.773734
2830 19:23:39.780398 [DQSOSCAuto] RK0, (LSB)MR18= 0x906, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 406 ps
2831 19:23:39.783775 CH0 RK0: MR19=404, MR18=906
2832 19:23:39.790586 CH0_RK0: MR19=0x404, MR18=0x906, DQSOSC=406, MR23=63, INC=39, DEC=26
2833 19:23:39.790688
2834 19:23:39.793778 ----->DramcWriteLeveling(PI) begin...
2835 19:23:39.793863 ==
2836 19:23:39.797081 Dram Type= 6, Freq= 0, CH_0, rank 1
2837 19:23:39.800130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2838 19:23:39.800214 ==
2839 19:23:39.803735 Write leveling (Byte 0): 33 => 33
2840 19:23:39.807036 Write leveling (Byte 1): 30 => 30
2841 19:23:39.810364 DramcWriteLeveling(PI) end<-----
2842 19:23:39.810463
2843 19:23:39.810575 ==
2844 19:23:39.813645 Dram Type= 6, Freq= 0, CH_0, rank 1
2845 19:23:39.817103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2846 19:23:39.820416 ==
2847 19:23:39.820500 [Gating] SW mode calibration
2848 19:23:39.830173 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2849 19:23:39.833855 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2850 19:23:39.837251 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2851 19:23:39.843980 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2852 19:23:39.847211 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2853 19:23:39.850324 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2854 19:23:39.857003 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2855 19:23:39.860327 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2856 19:23:39.863360 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2857 19:23:39.870096 0 15 28 | B1->B0 | 2f2f 2b2b | 0 0 | (1 0) (1 0)
2858 19:23:39.873611 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
2859 19:23:39.876929 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2860 19:23:39.880570 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2861 19:23:39.887471 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2862 19:23:39.890332 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2863 19:23:39.893840 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2864 19:23:39.900454 1 0 24 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)
2865 19:23:39.903697 1 0 28 | B1->B0 | 3e3e 4545 | 0 0 | (0 0) (0 0)
2866 19:23:39.907262 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2867 19:23:39.913869 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2868 19:23:39.917125 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2869 19:23:39.920679 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2870 19:23:39.927156 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2871 19:23:39.930437 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2872 19:23:39.933715 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2873 19:23:39.940518 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2874 19:23:39.943867 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 19:23:39.947112 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 19:23:39.953793 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 19:23:39.957247 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 19:23:39.960592 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 19:23:39.964113 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 19:23:39.970620 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 19:23:39.974046 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 19:23:39.977263 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 19:23:39.984096 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 19:23:39.987452 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 19:23:39.991225 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 19:23:39.997383 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 19:23:40.000804 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 19:23:40.004183 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 19:23:40.010664 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2890 19:23:40.014012 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2891 19:23:40.017609 Total UI for P1: 0, mck2ui 16
2892 19:23:40.020957 best dqsien dly found for B0: ( 1, 3, 28)
2893 19:23:40.024492 Total UI for P1: 0, mck2ui 16
2894 19:23:40.027401 best dqsien dly found for B1: ( 1, 3, 28)
2895 19:23:40.031186 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2896 19:23:40.034534 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2897 19:23:40.034616
2898 19:23:40.037678 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2899 19:23:40.040772 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2900 19:23:40.044182 [Gating] SW calibration Done
2901 19:23:40.044263 ==
2902 19:23:40.047534 Dram Type= 6, Freq= 0, CH_0, rank 1
2903 19:23:40.050987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2904 19:23:40.051069 ==
2905 19:23:40.054248 RX Vref Scan: 0
2906 19:23:40.054329
2907 19:23:40.054392 RX Vref 0 -> 0, step: 1
2908 19:23:40.057632
2909 19:23:40.057713 RX Delay -40 -> 252, step: 8
2910 19:23:40.064274 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2911 19:23:40.067724 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2912 19:23:40.071152 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2913 19:23:40.074427 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2914 19:23:40.077784 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2915 19:23:40.084559 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2916 19:23:40.087490 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2917 19:23:40.091280 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2918 19:23:40.094151 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2919 19:23:40.097818 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2920 19:23:40.101568 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2921 19:23:40.107698 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2922 19:23:40.111230 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2923 19:23:40.114398 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2924 19:23:40.117833 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2925 19:23:40.124504 iDelay=200, Bit 15, Center 111 (48 ~ 175) 128
2926 19:23:40.124584 ==
2927 19:23:40.127879 Dram Type= 6, Freq= 0, CH_0, rank 1
2928 19:23:40.130986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2929 19:23:40.131109 ==
2930 19:23:40.131172 DQS Delay:
2931 19:23:40.134425 DQS0 = 0, DQS1 = 0
2932 19:23:40.134505 DQM Delay:
2933 19:23:40.137735 DQM0 = 120, DQM1 = 108
2934 19:23:40.137815 DQ Delay:
2935 19:23:40.141096 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2936 19:23:40.144329 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2937 19:23:40.147640 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2938 19:23:40.151020 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2939 19:23:40.151099
2940 19:23:40.151163
2941 19:23:40.151221 ==
2942 19:23:40.154271 Dram Type= 6, Freq= 0, CH_0, rank 1
2943 19:23:40.161246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2944 19:23:40.161370 ==
2945 19:23:40.161435
2946 19:23:40.161492
2947 19:23:40.161549 TX Vref Scan disable
2948 19:23:40.164584 == TX Byte 0 ==
2949 19:23:40.167915 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2950 19:23:40.171457 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2951 19:23:40.174485 == TX Byte 1 ==
2952 19:23:40.177833 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2953 19:23:40.181571 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2954 19:23:40.184832 ==
2955 19:23:40.188030 Dram Type= 6, Freq= 0, CH_0, rank 1
2956 19:23:40.191174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2957 19:23:40.191255 ==
2958 19:23:40.202504 TX Vref=22, minBit 2, minWin=24, winSum=408
2959 19:23:40.205791 TX Vref=24, minBit 4, minWin=24, winSum=411
2960 19:23:40.208961 TX Vref=26, minBit 7, minWin=24, winSum=417
2961 19:23:40.212438 TX Vref=28, minBit 0, minWin=25, winSum=423
2962 19:23:40.216072 TX Vref=30, minBit 1, minWin=25, winSum=418
2963 19:23:40.219287 TX Vref=32, minBit 0, minWin=25, winSum=417
2964 19:23:40.226349 [TxChooseVref] Worse bit 0, Min win 25, Win sum 423, Final Vref 28
2965 19:23:40.226431
2966 19:23:40.229257 Final TX Range 1 Vref 28
2967 19:23:40.229371
2968 19:23:40.229436 ==
2969 19:23:40.232683 Dram Type= 6, Freq= 0, CH_0, rank 1
2970 19:23:40.235823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2971 19:23:40.235904 ==
2972 19:23:40.235967
2973 19:23:40.236023
2974 19:23:40.239431 TX Vref Scan disable
2975 19:23:40.242639 == TX Byte 0 ==
2976 19:23:40.246329 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2977 19:23:40.249192 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2978 19:23:40.252570 == TX Byte 1 ==
2979 19:23:40.256318 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2980 19:23:40.259741 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2981 19:23:40.259821
2982 19:23:40.262978 [DATLAT]
2983 19:23:40.263058 Freq=1200, CH0 RK1
2984 19:23:40.263121
2985 19:23:40.266333 DATLAT Default: 0xd
2986 19:23:40.266413 0, 0xFFFF, sum = 0
2987 19:23:40.269574 1, 0xFFFF, sum = 0
2988 19:23:40.269655 2, 0xFFFF, sum = 0
2989 19:23:40.272909 3, 0xFFFF, sum = 0
2990 19:23:40.272990 4, 0xFFFF, sum = 0
2991 19:23:40.275975 5, 0xFFFF, sum = 0
2992 19:23:40.276056 6, 0xFFFF, sum = 0
2993 19:23:40.279370 7, 0xFFFF, sum = 0
2994 19:23:40.279478 8, 0xFFFF, sum = 0
2995 19:23:40.282841 9, 0xFFFF, sum = 0
2996 19:23:40.282923 10, 0xFFFF, sum = 0
2997 19:23:40.286268 11, 0xFFFF, sum = 0
2998 19:23:40.286350 12, 0x0, sum = 1
2999 19:23:40.289241 13, 0x0, sum = 2
3000 19:23:40.289427 14, 0x0, sum = 3
3001 19:23:40.292855 15, 0x0, sum = 4
3002 19:23:40.292962 best_step = 13
3003 19:23:40.293052
3004 19:23:40.293138 ==
3005 19:23:40.296299 Dram Type= 6, Freq= 0, CH_0, rank 1
3006 19:23:40.302854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3007 19:23:40.302934 ==
3008 19:23:40.302997 RX Vref Scan: 0
3009 19:23:40.303054
3010 19:23:40.306258 RX Vref 0 -> 0, step: 1
3011 19:23:40.306339
3012 19:23:40.309575 RX Delay -21 -> 252, step: 4
3013 19:23:40.312885 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3014 19:23:40.316430 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3015 19:23:40.322702 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3016 19:23:40.326175 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3017 19:23:40.329469 iDelay=195, Bit 4, Center 118 (51 ~ 186) 136
3018 19:23:40.333005 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3019 19:23:40.336636 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3020 19:23:40.343229 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3021 19:23:40.346216 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3022 19:23:40.349619 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3023 19:23:40.352917 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3024 19:23:40.356245 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3025 19:23:40.359648 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3026 19:23:40.366523 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3027 19:23:40.369713 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3028 19:23:40.373248 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3029 19:23:40.373338 ==
3030 19:23:40.376376 Dram Type= 6, Freq= 0, CH_0, rank 1
3031 19:23:40.379480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3032 19:23:40.382752 ==
3033 19:23:40.382834 DQS Delay:
3034 19:23:40.382898 DQS0 = 0, DQS1 = 0
3035 19:23:40.386212 DQM Delay:
3036 19:23:40.386294 DQM0 = 119, DQM1 = 107
3037 19:23:40.389461 DQ Delay:
3038 19:23:40.392699 DQ0 =118, DQ1 =122, DQ2 =116, DQ3 =114
3039 19:23:40.395981 DQ4 =118, DQ5 =114, DQ6 =126, DQ7 =126
3040 19:23:40.399607 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =106
3041 19:23:40.403014 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =114
3042 19:23:40.403095
3043 19:23:40.403158
3044 19:23:40.409603 [DQSOSCAuto] RK1, (LSB)MR18= 0x11f8, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 403 ps
3045 19:23:40.412793 CH0 RK1: MR19=403, MR18=11F8
3046 19:23:40.419714 CH0_RK1: MR19=0x403, MR18=0x11F8, DQSOSC=403, MR23=63, INC=40, DEC=26
3047 19:23:40.422830 [RxdqsGatingPostProcess] freq 1200
3048 19:23:40.429788 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3049 19:23:40.429870 best DQS0 dly(2T, 0.5T) = (0, 11)
3050 19:23:40.432932 best DQS1 dly(2T, 0.5T) = (0, 11)
3051 19:23:40.436306 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3052 19:23:40.439648 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3053 19:23:40.442810 best DQS0 dly(2T, 0.5T) = (0, 11)
3054 19:23:40.446240 best DQS1 dly(2T, 0.5T) = (0, 11)
3055 19:23:40.449823 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3056 19:23:40.452899 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3057 19:23:40.456499 Pre-setting of DQS Precalculation
3058 19:23:40.459720 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3059 19:23:40.463063 ==
3060 19:23:40.466341 Dram Type= 6, Freq= 0, CH_1, rank 0
3061 19:23:40.469510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3062 19:23:40.469591 ==
3063 19:23:40.472731 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3064 19:23:40.479560 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3065 19:23:40.488882 [CA 0] Center 37 (7~67) winsize 61
3066 19:23:40.492287 [CA 1] Center 37 (7~68) winsize 62
3067 19:23:40.495144 [CA 2] Center 35 (5~65) winsize 61
3068 19:23:40.498866 [CA 3] Center 33 (3~64) winsize 62
3069 19:23:40.501727 [CA 4] Center 33 (3~64) winsize 62
3070 19:23:40.505398 [CA 5] Center 32 (2~63) winsize 62
3071 19:23:40.505477
3072 19:23:40.508810 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3073 19:23:40.508890
3074 19:23:40.512054 [CATrainingPosCal] consider 1 rank data
3075 19:23:40.515371 u2DelayCellTimex100 = 270/100 ps
3076 19:23:40.518623 CA0 delay=37 (7~67),Diff = 5 PI (24 cell)
3077 19:23:40.521939 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
3078 19:23:40.528690 CA2 delay=35 (5~65),Diff = 3 PI (14 cell)
3079 19:23:40.532315 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
3080 19:23:40.535516 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
3081 19:23:40.538943 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3082 19:23:40.539024
3083 19:23:40.542662 CA PerBit enable=1, Macro0, CA PI delay=32
3084 19:23:40.542742
3085 19:23:40.545801 [CBTSetCACLKResult] CA Dly = 32
3086 19:23:40.545881 CS Dly: 5 (0~36)
3087 19:23:40.545943 ==
3088 19:23:40.549024 Dram Type= 6, Freq= 0, CH_1, rank 1
3089 19:23:40.555941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3090 19:23:40.556022 ==
3091 19:23:40.559280 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3092 19:23:40.565889 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3093 19:23:40.574450 [CA 0] Center 38 (8~68) winsize 61
3094 19:23:40.577658 [CA 1] Center 37 (7~68) winsize 62
3095 19:23:40.581039 [CA 2] Center 35 (5~66) winsize 62
3096 19:23:40.584279 [CA 3] Center 34 (4~65) winsize 62
3097 19:23:40.587778 [CA 4] Center 34 (4~64) winsize 61
3098 19:23:40.590820 [CA 5] Center 33 (3~64) winsize 62
3099 19:23:40.590901
3100 19:23:40.594223 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3101 19:23:40.594304
3102 19:23:40.597629 [CATrainingPosCal] consider 2 rank data
3103 19:23:40.600867 u2DelayCellTimex100 = 270/100 ps
3104 19:23:40.604550 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3105 19:23:40.607783 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3106 19:23:40.614338 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3107 19:23:40.618037 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3108 19:23:40.621319 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3109 19:23:40.624422 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3110 19:23:40.624503
3111 19:23:40.627719 CA PerBit enable=1, Macro0, CA PI delay=33
3112 19:23:40.627800
3113 19:23:40.631013 [CBTSetCACLKResult] CA Dly = 33
3114 19:23:40.631094 CS Dly: 6 (0~38)
3115 19:23:40.631158
3116 19:23:40.634448 ----->DramcWriteLeveling(PI) begin...
3117 19:23:40.634531 ==
3118 19:23:40.637874 Dram Type= 6, Freq= 0, CH_1, rank 0
3119 19:23:40.644818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3120 19:23:40.644902 ==
3121 19:23:40.648063 Write leveling (Byte 0): 24 => 24
3122 19:23:40.651264 Write leveling (Byte 1): 28 => 28
3123 19:23:40.651346 DramcWriteLeveling(PI) end<-----
3124 19:23:40.651411
3125 19:23:40.654708 ==
3126 19:23:40.657762 Dram Type= 6, Freq= 0, CH_1, rank 0
3127 19:23:40.661185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3128 19:23:40.661330 ==
3129 19:23:40.664500 [Gating] SW mode calibration
3130 19:23:40.671337 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3131 19:23:40.674915 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3132 19:23:40.681325 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3133 19:23:40.684758 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3134 19:23:40.688101 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3135 19:23:40.694617 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3136 19:23:40.697926 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3137 19:23:40.701260 0 15 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
3138 19:23:40.707915 0 15 24 | B1->B0 | 2626 2525 | 0 0 | (0 0) (1 0)
3139 19:23:40.711342 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3140 19:23:40.714697 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3141 19:23:40.721282 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3142 19:23:40.724631 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3143 19:23:40.728040 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3144 19:23:40.731365 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3145 19:23:40.738444 1 0 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3146 19:23:40.741759 1 0 24 | B1->B0 | 3a3a 4545 | 0 0 | (0 0) (0 0)
3147 19:23:40.744906 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3148 19:23:40.751411 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3149 19:23:40.754706 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3150 19:23:40.758337 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3151 19:23:40.764979 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3152 19:23:40.768497 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3153 19:23:40.771919 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3154 19:23:40.778146 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3155 19:23:40.781646 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3156 19:23:40.784906 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 19:23:40.791449 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 19:23:40.794921 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 19:23:40.798503 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 19:23:40.804882 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 19:23:40.808416 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 19:23:40.811573 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 19:23:40.814965 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 19:23:40.821681 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 19:23:40.824834 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 19:23:40.828237 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 19:23:40.835366 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 19:23:40.838676 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 19:23:40.841846 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 19:23:40.848417 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3171 19:23:40.851917 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3172 19:23:40.855149 Total UI for P1: 0, mck2ui 16
3173 19:23:40.858748 best dqsien dly found for B0: ( 1, 3, 24)
3174 19:23:40.861671 Total UI for P1: 0, mck2ui 16
3175 19:23:40.865240 best dqsien dly found for B1: ( 1, 3, 24)
3176 19:23:40.868634 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3177 19:23:40.872042 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3178 19:23:40.872126
3179 19:23:40.875449 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3180 19:23:40.878581 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3181 19:23:40.882136 [Gating] SW calibration Done
3182 19:23:40.882220 ==
3183 19:23:40.885307 Dram Type= 6, Freq= 0, CH_1, rank 0
3184 19:23:40.888566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3185 19:23:40.888651 ==
3186 19:23:40.892311 RX Vref Scan: 0
3187 19:23:40.892395
3188 19:23:40.892460 RX Vref 0 -> 0, step: 1
3189 19:23:40.895257
3190 19:23:40.895339 RX Delay -40 -> 252, step: 8
3191 19:23:40.902313 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3192 19:23:40.905705 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3193 19:23:40.908492 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3194 19:23:40.911767 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3195 19:23:40.915402 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3196 19:23:40.922049 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3197 19:23:40.925352 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3198 19:23:40.928690 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3199 19:23:40.932008 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3200 19:23:40.935341 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3201 19:23:40.938603 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3202 19:23:40.945210 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3203 19:23:40.948454 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3204 19:23:40.951732 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3205 19:23:40.955195 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3206 19:23:40.961725 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3207 19:23:40.961811 ==
3208 19:23:40.965279 Dram Type= 6, Freq= 0, CH_1, rank 0
3209 19:23:40.968406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3210 19:23:40.968490 ==
3211 19:23:40.968554 DQS Delay:
3212 19:23:40.971782 DQS0 = 0, DQS1 = 0
3213 19:23:40.971865 DQM Delay:
3214 19:23:40.975168 DQM0 = 120, DQM1 = 112
3215 19:23:40.975250 DQ Delay:
3216 19:23:40.978670 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =119
3217 19:23:40.982263 DQ4 =115, DQ5 =127, DQ6 =131, DQ7 =123
3218 19:23:40.985017 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3219 19:23:40.988603 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3220 19:23:40.988689
3221 19:23:40.988754
3222 19:23:40.988814 ==
3223 19:23:40.991986 Dram Type= 6, Freq= 0, CH_1, rank 0
3224 19:23:40.998625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3225 19:23:40.998709 ==
3226 19:23:40.998775
3227 19:23:40.998835
3228 19:23:40.998894 TX Vref Scan disable
3229 19:23:41.002538 == TX Byte 0 ==
3230 19:23:41.005264 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3231 19:23:41.012181 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3232 19:23:41.012266 == TX Byte 1 ==
3233 19:23:41.015294 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3234 19:23:41.018856 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3235 19:23:41.022226 ==
3236 19:23:41.025504 Dram Type= 6, Freq= 0, CH_1, rank 0
3237 19:23:41.028753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3238 19:23:41.028836 ==
3239 19:23:41.039918 TX Vref=22, minBit 7, minWin=24, winSum=398
3240 19:23:41.043625 TX Vref=24, minBit 8, minWin=23, winSum=401
3241 19:23:41.046704 TX Vref=26, minBit 10, minWin=24, winSum=408
3242 19:23:41.049975 TX Vref=28, minBit 8, minWin=25, winSum=417
3243 19:23:41.053206 TX Vref=30, minBit 9, minWin=24, winSum=418
3244 19:23:41.059832 TX Vref=32, minBit 9, minWin=25, winSum=419
3245 19:23:41.063192 [TxChooseVref] Worse bit 9, Min win 25, Win sum 419, Final Vref 32
3246 19:23:41.063301
3247 19:23:41.066579 Final TX Range 1 Vref 32
3248 19:23:41.066662
3249 19:23:41.066730 ==
3250 19:23:41.070138 Dram Type= 6, Freq= 0, CH_1, rank 0
3251 19:23:41.073505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3252 19:23:41.073587 ==
3253 19:23:41.073652
3254 19:23:41.076882
3255 19:23:41.076964 TX Vref Scan disable
3256 19:23:41.080066 == TX Byte 0 ==
3257 19:23:41.083401 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3258 19:23:41.086851 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3259 19:23:41.090149 == TX Byte 1 ==
3260 19:23:41.093284 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3261 19:23:41.097144 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3262 19:23:41.097251
3263 19:23:41.100168 [DATLAT]
3264 19:23:41.100250 Freq=1200, CH1 RK0
3265 19:23:41.100314
3266 19:23:41.103582 DATLAT Default: 0xd
3267 19:23:41.103663 0, 0xFFFF, sum = 0
3268 19:23:41.106904 1, 0xFFFF, sum = 0
3269 19:23:41.106987 2, 0xFFFF, sum = 0
3270 19:23:41.110540 3, 0xFFFF, sum = 0
3271 19:23:41.110623 4, 0xFFFF, sum = 0
3272 19:23:41.113737 5, 0xFFFF, sum = 0
3273 19:23:41.113820 6, 0xFFFF, sum = 0
3274 19:23:41.117099 7, 0xFFFF, sum = 0
3275 19:23:41.117182 8, 0xFFFF, sum = 0
3276 19:23:41.120394 9, 0xFFFF, sum = 0
3277 19:23:41.120478 10, 0xFFFF, sum = 0
3278 19:23:41.123523 11, 0xFFFF, sum = 0
3279 19:23:41.123606 12, 0x0, sum = 1
3280 19:23:41.126768 13, 0x0, sum = 2
3281 19:23:41.126851 14, 0x0, sum = 3
3282 19:23:41.130579 15, 0x0, sum = 4
3283 19:23:41.130666 best_step = 13
3284 19:23:41.130732
3285 19:23:41.130793 ==
3286 19:23:41.133861 Dram Type= 6, Freq= 0, CH_1, rank 0
3287 19:23:41.140041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3288 19:23:41.140124 ==
3289 19:23:41.140189 RX Vref Scan: 1
3290 19:23:41.140249
3291 19:23:41.143422 Set Vref Range= 32 -> 127
3292 19:23:41.143504
3293 19:23:41.146707 RX Vref 32 -> 127, step: 1
3294 19:23:41.146787
3295 19:23:41.150023 RX Delay -13 -> 252, step: 4
3296 19:23:41.150104
3297 19:23:41.153700 Set Vref, RX VrefLevel [Byte0]: 32
3298 19:23:41.157038 [Byte1]: 32
3299 19:23:41.157119
3300 19:23:41.160187 Set Vref, RX VrefLevel [Byte0]: 33
3301 19:23:41.163603 [Byte1]: 33
3302 19:23:41.163684
3303 19:23:41.166890 Set Vref, RX VrefLevel [Byte0]: 34
3304 19:23:41.170214 [Byte1]: 34
3305 19:23:41.174207
3306 19:23:41.174288 Set Vref, RX VrefLevel [Byte0]: 35
3307 19:23:41.177538 [Byte1]: 35
3308 19:23:41.182015
3309 19:23:41.182097 Set Vref, RX VrefLevel [Byte0]: 36
3310 19:23:41.185492 [Byte1]: 36
3311 19:23:41.189916
3312 19:23:41.190000 Set Vref, RX VrefLevel [Byte0]: 37
3313 19:23:41.193088 [Byte1]: 37
3314 19:23:41.197957
3315 19:23:41.198038 Set Vref, RX VrefLevel [Byte0]: 38
3316 19:23:41.201270 [Byte1]: 38
3317 19:23:41.205592
3318 19:23:41.205673 Set Vref, RX VrefLevel [Byte0]: 39
3319 19:23:41.208880 [Byte1]: 39
3320 19:23:41.213734
3321 19:23:41.213823 Set Vref, RX VrefLevel [Byte0]: 40
3322 19:23:41.216715 [Byte1]: 40
3323 19:23:41.221462
3324 19:23:41.221542 Set Vref, RX VrefLevel [Byte0]: 41
3325 19:23:41.224691 [Byte1]: 41
3326 19:23:41.229137
3327 19:23:41.229217 Set Vref, RX VrefLevel [Byte0]: 42
3328 19:23:41.232647 [Byte1]: 42
3329 19:23:41.237414
3330 19:23:41.237494 Set Vref, RX VrefLevel [Byte0]: 43
3331 19:23:41.240752 [Byte1]: 43
3332 19:23:41.245069
3333 19:23:41.245149 Set Vref, RX VrefLevel [Byte0]: 44
3334 19:23:41.248427 [Byte1]: 44
3335 19:23:41.253054
3336 19:23:41.253136 Set Vref, RX VrefLevel [Byte0]: 45
3337 19:23:41.256412 [Byte1]: 45
3338 19:23:41.260915
3339 19:23:41.260995 Set Vref, RX VrefLevel [Byte0]: 46
3340 19:23:41.264177 [Byte1]: 46
3341 19:23:41.268833
3342 19:23:41.268913 Set Vref, RX VrefLevel [Byte0]: 47
3343 19:23:41.275374 [Byte1]: 47
3344 19:23:41.275455
3345 19:23:41.278440 Set Vref, RX VrefLevel [Byte0]: 48
3346 19:23:41.282279 [Byte1]: 48
3347 19:23:41.282359
3348 19:23:41.285008 Set Vref, RX VrefLevel [Byte0]: 49
3349 19:23:41.288531 [Byte1]: 49
3350 19:23:41.292385
3351 19:23:41.292465 Set Vref, RX VrefLevel [Byte0]: 50
3352 19:23:41.295563 [Byte1]: 50
3353 19:23:41.300357
3354 19:23:41.300437 Set Vref, RX VrefLevel [Byte0]: 51
3355 19:23:41.303544 [Byte1]: 51
3356 19:23:41.308309
3357 19:23:41.308390 Set Vref, RX VrefLevel [Byte0]: 52
3358 19:23:41.311254 [Byte1]: 52
3359 19:23:41.316083
3360 19:23:41.316164 Set Vref, RX VrefLevel [Byte0]: 53
3361 19:23:41.319345 [Byte1]: 53
3362 19:23:41.324080
3363 19:23:41.324161 Set Vref, RX VrefLevel [Byte0]: 54
3364 19:23:41.327515 [Byte1]: 54
3365 19:23:41.331866
3366 19:23:41.331974 Set Vref, RX VrefLevel [Byte0]: 55
3367 19:23:41.335356 [Byte1]: 55
3368 19:23:41.339761
3369 19:23:41.339831 Set Vref, RX VrefLevel [Byte0]: 56
3370 19:23:41.342998 [Byte1]: 56
3371 19:23:41.347354
3372 19:23:41.347435 Set Vref, RX VrefLevel [Byte0]: 57
3373 19:23:41.350644 [Byte1]: 57
3374 19:23:41.355492
3375 19:23:41.355572 Set Vref, RX VrefLevel [Byte0]: 58
3376 19:23:41.358836 [Byte1]: 58
3377 19:23:41.363318
3378 19:23:41.363401 Set Vref, RX VrefLevel [Byte0]: 59
3379 19:23:41.366838 [Byte1]: 59
3380 19:23:41.371605
3381 19:23:41.371685 Set Vref, RX VrefLevel [Byte0]: 60
3382 19:23:41.374695 [Byte1]: 60
3383 19:23:41.379114
3384 19:23:41.379195 Set Vref, RX VrefLevel [Byte0]: 61
3385 19:23:41.382308 [Byte1]: 61
3386 19:23:41.387029
3387 19:23:41.387111 Set Vref, RX VrefLevel [Byte0]: 62
3388 19:23:41.390465 [Byte1]: 62
3389 19:23:41.394895
3390 19:23:41.394976 Set Vref, RX VrefLevel [Byte0]: 63
3391 19:23:41.398078 [Byte1]: 63
3392 19:23:41.402772
3393 19:23:41.402853 Set Vref, RX VrefLevel [Byte0]: 64
3394 19:23:41.406261 [Byte1]: 64
3395 19:23:41.410521
3396 19:23:41.410602 Set Vref, RX VrefLevel [Byte0]: 65
3397 19:23:41.413941 [Byte1]: 65
3398 19:23:41.418646
3399 19:23:41.418726 Set Vref, RX VrefLevel [Byte0]: 66
3400 19:23:41.422265 [Byte1]: 66
3401 19:23:41.426647
3402 19:23:41.426730 Set Vref, RX VrefLevel [Byte0]: 67
3403 19:23:41.429573 [Byte1]: 67
3404 19:23:41.434572
3405 19:23:41.434653 Final RX Vref Byte 0 = 51 to rank0
3406 19:23:41.437743 Final RX Vref Byte 1 = 52 to rank0
3407 19:23:41.441163 Final RX Vref Byte 0 = 51 to rank1
3408 19:23:41.444478 Final RX Vref Byte 1 = 52 to rank1==
3409 19:23:41.447811 Dram Type= 6, Freq= 0, CH_1, rank 0
3410 19:23:41.454240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3411 19:23:41.454322 ==
3412 19:23:41.454385 DQS Delay:
3413 19:23:41.454445 DQS0 = 0, DQS1 = 0
3414 19:23:41.457674 DQM Delay:
3415 19:23:41.457755 DQM0 = 119, DQM1 = 112
3416 19:23:41.461069 DQ Delay:
3417 19:23:41.464376 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =118
3418 19:23:41.467901 DQ4 =118, DQ5 =128, DQ6 =128, DQ7 =118
3419 19:23:41.470871 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =106
3420 19:23:41.474524 DQ12 =122, DQ13 =116, DQ14 =122, DQ15 =118
3421 19:23:41.474607
3422 19:23:41.474671
3423 19:23:41.480788 [DQSOSCAuto] RK0, (LSB)MR18= 0x13, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 410 ps
3424 19:23:41.484108 CH1 RK0: MR19=404, MR18=13
3425 19:23:41.491170 CH1_RK0: MR19=0x404, MR18=0x13, DQSOSC=402, MR23=63, INC=40, DEC=27
3426 19:23:41.491256
3427 19:23:41.494096 ----->DramcWriteLeveling(PI) begin...
3428 19:23:41.494178 ==
3429 19:23:41.497658 Dram Type= 6, Freq= 0, CH_1, rank 1
3430 19:23:41.501065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3431 19:23:41.501148 ==
3432 19:23:41.504269 Write leveling (Byte 0): 24 => 24
3433 19:23:41.507613 Write leveling (Byte 1): 31 => 31
3434 19:23:41.510800 DramcWriteLeveling(PI) end<-----
3435 19:23:41.510882
3436 19:23:41.510945 ==
3437 19:23:41.514146 Dram Type= 6, Freq= 0, CH_1, rank 1
3438 19:23:41.517801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3439 19:23:41.521208 ==
3440 19:23:41.521294 [Gating] SW mode calibration
3441 19:23:41.531050 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3442 19:23:41.534047 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3443 19:23:41.537760 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3444 19:23:41.544140 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3445 19:23:41.547807 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3446 19:23:41.550887 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3447 19:23:41.557612 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3448 19:23:41.560909 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3449 19:23:41.564249 0 15 24 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 0)
3450 19:23:41.571259 0 15 28 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
3451 19:23:41.574600 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3452 19:23:41.577730 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3453 19:23:41.580951 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3454 19:23:41.587729 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3455 19:23:41.591132 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3456 19:23:41.594378 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3457 19:23:41.601043 1 0 24 | B1->B0 | 3b3b 2e2e | 0 0 | (0 0) (0 0)
3458 19:23:41.604563 1 0 28 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
3459 19:23:41.607891 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3460 19:23:41.614597 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3461 19:23:41.617634 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3462 19:23:41.621121 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3463 19:23:41.627667 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3464 19:23:41.631154 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3465 19:23:41.634428 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3466 19:23:41.640957 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 19:23:41.644148 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 19:23:41.647489 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 19:23:41.654378 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 19:23:41.657653 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 19:23:41.661000 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 19:23:41.667536 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 19:23:41.670929 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 19:23:41.674043 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 19:23:41.680978 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 19:23:41.683955 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 19:23:41.687454 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 19:23:41.694310 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 19:23:41.697573 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 19:23:41.700988 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3481 19:23:41.707667 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3482 19:23:41.711054 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3483 19:23:41.714151 Total UI for P1: 0, mck2ui 16
3484 19:23:41.717636 best dqsien dly found for B0: ( 1, 3, 24)
3485 19:23:41.720916 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3486 19:23:41.724114 Total UI for P1: 0, mck2ui 16
3487 19:23:41.727711 best dqsien dly found for B1: ( 1, 3, 24)
3488 19:23:41.730753 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3489 19:23:41.734032 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3490 19:23:41.734113
3491 19:23:41.737629 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3492 19:23:41.740684 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3493 19:23:41.744140 [Gating] SW calibration Done
3494 19:23:41.744221 ==
3495 19:23:41.747636 Dram Type= 6, Freq= 0, CH_1, rank 1
3496 19:23:41.754419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3497 19:23:41.754501 ==
3498 19:23:41.754566 RX Vref Scan: 0
3499 19:23:41.754625
3500 19:23:41.757246 RX Vref 0 -> 0, step: 1
3501 19:23:41.757375
3502 19:23:41.760678 RX Delay -40 -> 252, step: 8
3503 19:23:41.764010 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3504 19:23:41.767190 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3505 19:23:41.770622 iDelay=200, Bit 2, Center 107 (48 ~ 167) 120
3506 19:23:41.773767 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3507 19:23:41.780766 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3508 19:23:41.784226 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3509 19:23:41.787607 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3510 19:23:41.790415 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3511 19:23:41.793921 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3512 19:23:41.800261 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3513 19:23:41.803486 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3514 19:23:41.806906 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3515 19:23:41.810210 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3516 19:23:41.817023 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3517 19:23:41.820062 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3518 19:23:41.823586 iDelay=200, Bit 15, Center 127 (56 ~ 199) 144
3519 19:23:41.823723 ==
3520 19:23:41.826822 Dram Type= 6, Freq= 0, CH_1, rank 1
3521 19:23:41.830190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3522 19:23:41.830277 ==
3523 19:23:41.833271 DQS Delay:
3524 19:23:41.833397 DQS0 = 0, DQS1 = 0
3525 19:23:41.836532 DQM Delay:
3526 19:23:41.836628 DQM0 = 119, DQM1 = 114
3527 19:23:41.836721 DQ Delay:
3528 19:23:41.843480 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =119
3529 19:23:41.846912 DQ4 =123, DQ5 =131, DQ6 =123, DQ7 =115
3530 19:23:41.850097 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107
3531 19:23:41.853441 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =127
3532 19:23:41.853523
3533 19:23:41.853586
3534 19:23:41.853644 ==
3535 19:23:41.856785 Dram Type= 6, Freq= 0, CH_1, rank 1
3536 19:23:41.860096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3537 19:23:41.860178 ==
3538 19:23:41.860241
3539 19:23:41.860299
3540 19:23:41.863163 TX Vref Scan disable
3541 19:23:41.866449 == TX Byte 0 ==
3542 19:23:41.869701 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3543 19:23:41.873091 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3544 19:23:41.876418 == TX Byte 1 ==
3545 19:23:41.879782 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3546 19:23:41.883108 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3547 19:23:41.883188 ==
3548 19:23:41.886663 Dram Type= 6, Freq= 0, CH_1, rank 1
3549 19:23:41.889879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3550 19:23:41.893241 ==
3551 19:23:41.903724 TX Vref=22, minBit 1, minWin=25, winSum=413
3552 19:23:41.906989 TX Vref=24, minBit 1, minWin=25, winSum=415
3553 19:23:41.910312 TX Vref=26, minBit 3, minWin=25, winSum=418
3554 19:23:41.913679 TX Vref=28, minBit 1, minWin=26, winSum=425
3555 19:23:41.916990 TX Vref=30, minBit 1, minWin=26, winSum=428
3556 19:23:41.920236 TX Vref=32, minBit 1, minWin=26, winSum=426
3557 19:23:41.926907 [TxChooseVref] Worse bit 1, Min win 26, Win sum 428, Final Vref 30
3558 19:23:41.926991
3559 19:23:41.930399 Final TX Range 1 Vref 30
3560 19:23:41.930482
3561 19:23:41.930545 ==
3562 19:23:41.933773 Dram Type= 6, Freq= 0, CH_1, rank 1
3563 19:23:41.937093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3564 19:23:41.937176 ==
3565 19:23:41.937240
3566 19:23:41.940296
3567 19:23:41.940377 TX Vref Scan disable
3568 19:23:41.943809 == TX Byte 0 ==
3569 19:23:41.946768 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3570 19:23:41.950242 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3571 19:23:41.953564 == TX Byte 1 ==
3572 19:23:41.956730 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3573 19:23:41.960144 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3574 19:23:41.960227
3575 19:23:41.963426 [DATLAT]
3576 19:23:41.963508 Freq=1200, CH1 RK1
3577 19:23:41.963572
3578 19:23:41.966843 DATLAT Default: 0xd
3579 19:23:41.966924 0, 0xFFFF, sum = 0
3580 19:23:41.970273 1, 0xFFFF, sum = 0
3581 19:23:41.970356 2, 0xFFFF, sum = 0
3582 19:23:41.973698 3, 0xFFFF, sum = 0
3583 19:23:41.973781 4, 0xFFFF, sum = 0
3584 19:23:41.976927 5, 0xFFFF, sum = 0
3585 19:23:41.977009 6, 0xFFFF, sum = 0
3586 19:23:41.980493 7, 0xFFFF, sum = 0
3587 19:23:41.983336 8, 0xFFFF, sum = 0
3588 19:23:41.983419 9, 0xFFFF, sum = 0
3589 19:23:41.986577 10, 0xFFFF, sum = 0
3590 19:23:41.986661 11, 0xFFFF, sum = 0
3591 19:23:41.990131 12, 0x0, sum = 1
3592 19:23:41.990216 13, 0x0, sum = 2
3593 19:23:41.993603 14, 0x0, sum = 3
3594 19:23:41.993686 15, 0x0, sum = 4
3595 19:23:41.993753 best_step = 13
3596 19:23:41.993813
3597 19:23:41.996761 ==
3598 19:23:41.999973 Dram Type= 6, Freq= 0, CH_1, rank 1
3599 19:23:42.003114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3600 19:23:42.003197 ==
3601 19:23:42.003261 RX Vref Scan: 0
3602 19:23:42.003320
3603 19:23:42.006967 RX Vref 0 -> 0, step: 1
3604 19:23:42.007048
3605 19:23:42.010142 RX Delay -13 -> 252, step: 4
3606 19:23:42.013055 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3607 19:23:42.019770 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3608 19:23:42.023136 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3609 19:23:42.026717 iDelay=195, Bit 3, Center 116 (55 ~ 178) 124
3610 19:23:42.030030 iDelay=195, Bit 4, Center 120 (59 ~ 182) 124
3611 19:23:42.033703 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3612 19:23:42.039994 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3613 19:23:42.043348 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3614 19:23:42.046527 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3615 19:23:42.049919 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3616 19:23:42.053458 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3617 19:23:42.060211 iDelay=195, Bit 11, Center 108 (43 ~ 174) 132
3618 19:23:42.063038 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3619 19:23:42.066868 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3620 19:23:42.070129 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3621 19:23:42.073480 iDelay=195, Bit 15, Center 124 (59 ~ 190) 132
3622 19:23:42.076304 ==
3623 19:23:42.076385 Dram Type= 6, Freq= 0, CH_1, rank 1
3624 19:23:42.083130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3625 19:23:42.083241 ==
3626 19:23:42.083318 DQS Delay:
3627 19:23:42.086390 DQS0 = 0, DQS1 = 0
3628 19:23:42.086471 DQM Delay:
3629 19:23:42.089588 DQM0 = 119, DQM1 = 113
3630 19:23:42.089724 DQ Delay:
3631 19:23:42.093017 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =116
3632 19:23:42.096290 DQ4 =120, DQ5 =130, DQ6 =126, DQ7 =116
3633 19:23:42.099764 DQ8 =98, DQ9 =102, DQ10 =112, DQ11 =108
3634 19:23:42.102764 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =124
3635 19:23:42.102873
3636 19:23:42.102941
3637 19:23:42.112903 [DQSOSCAuto] RK1, (LSB)MR18= 0x7ec, (MSB)MR19= 0x403, tDQSOscB0 = 418 ps tDQSOscB1 = 407 ps
3638 19:23:42.113039 CH1 RK1: MR19=403, MR18=7EC
3639 19:23:42.119680 CH1_RK1: MR19=0x403, MR18=0x7EC, DQSOSC=407, MR23=63, INC=39, DEC=26
3640 19:23:42.122952 [RxdqsGatingPostProcess] freq 1200
3641 19:23:42.129500 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3642 19:23:42.133031 best DQS0 dly(2T, 0.5T) = (0, 11)
3643 19:23:42.136030 best DQS1 dly(2T, 0.5T) = (0, 11)
3644 19:23:42.139698 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3645 19:23:42.142935 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3646 19:23:42.146079 best DQS0 dly(2T, 0.5T) = (0, 11)
3647 19:23:42.146162 best DQS1 dly(2T, 0.5T) = (0, 11)
3648 19:23:42.149205 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3649 19:23:42.152642 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3650 19:23:42.155844 Pre-setting of DQS Precalculation
3651 19:23:42.162566 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3652 19:23:42.169215 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3653 19:23:42.175995 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3654 19:23:42.176079
3655 19:23:42.176143
3656 19:23:42.179375 [Calibration Summary] 2400 Mbps
3657 19:23:42.182470 CH 0, Rank 0
3658 19:23:42.182610 SW Impedance : PASS
3659 19:23:42.185782 DUTY Scan : NO K
3660 19:23:42.188890 ZQ Calibration : PASS
3661 19:23:42.189031 Jitter Meter : NO K
3662 19:23:42.192478 CBT Training : PASS
3663 19:23:42.192611 Write leveling : PASS
3664 19:23:42.195803 RX DQS gating : PASS
3665 19:23:42.199169 RX DQ/DQS(RDDQC) : PASS
3666 19:23:42.199252 TX DQ/DQS : PASS
3667 19:23:42.202330 RX DATLAT : PASS
3668 19:23:42.205730 RX DQ/DQS(Engine): PASS
3669 19:23:42.205804 TX OE : NO K
3670 19:23:42.208879 All Pass.
3671 19:23:42.208952
3672 19:23:42.209013 CH 0, Rank 1
3673 19:23:42.212108 SW Impedance : PASS
3674 19:23:42.212205 DUTY Scan : NO K
3675 19:23:42.215488 ZQ Calibration : PASS
3676 19:23:42.218990 Jitter Meter : NO K
3677 19:23:42.219059 CBT Training : PASS
3678 19:23:42.222108 Write leveling : PASS
3679 19:23:42.225439 RX DQS gating : PASS
3680 19:23:42.225570 RX DQ/DQS(RDDQC) : PASS
3681 19:23:42.228889 TX DQ/DQS : PASS
3682 19:23:42.232146 RX DATLAT : PASS
3683 19:23:42.232233 RX DQ/DQS(Engine): PASS
3684 19:23:42.235491 TX OE : NO K
3685 19:23:42.235574 All Pass.
3686 19:23:42.235640
3687 19:23:42.239104 CH 1, Rank 0
3688 19:23:42.239187 SW Impedance : PASS
3689 19:23:42.242595 DUTY Scan : NO K
3690 19:23:42.242678 ZQ Calibration : PASS
3691 19:23:42.245971 Jitter Meter : NO K
3692 19:23:42.249005 CBT Training : PASS
3693 19:23:42.249087 Write leveling : PASS
3694 19:23:42.252278 RX DQS gating : PASS
3695 19:23:42.255966 RX DQ/DQS(RDDQC) : PASS
3696 19:23:42.256048 TX DQ/DQS : PASS
3697 19:23:42.259039 RX DATLAT : PASS
3698 19:23:42.262242 RX DQ/DQS(Engine): PASS
3699 19:23:42.262349 TX OE : NO K
3700 19:23:42.265570 All Pass.
3701 19:23:42.265653
3702 19:23:42.265718 CH 1, Rank 1
3703 19:23:42.269170 SW Impedance : PASS
3704 19:23:42.269253 DUTY Scan : NO K
3705 19:23:42.272497 ZQ Calibration : PASS
3706 19:23:42.275689 Jitter Meter : NO K
3707 19:23:42.275771 CBT Training : PASS
3708 19:23:42.279115 Write leveling : PASS
3709 19:23:42.282309 RX DQS gating : PASS
3710 19:23:42.282391 RX DQ/DQS(RDDQC) : PASS
3711 19:23:42.285487 TX DQ/DQS : PASS
3712 19:23:42.285596 RX DATLAT : PASS
3713 19:23:42.288622 RX DQ/DQS(Engine): PASS
3714 19:23:42.292599 TX OE : NO K
3715 19:23:42.292683 All Pass.
3716 19:23:42.292747
3717 19:23:42.295486 DramC Write-DBI off
3718 19:23:42.295569 PER_BANK_REFRESH: Hybrid Mode
3719 19:23:42.299039 TX_TRACKING: ON
3720 19:23:42.308496 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3721 19:23:42.312124 [FAST_K] Save calibration result to emmc
3722 19:23:42.315431 dramc_set_vcore_voltage set vcore to 650000
3723 19:23:42.318666 Read voltage for 600, 5
3724 19:23:42.318749 Vio18 = 0
3725 19:23:42.318814 Vcore = 650000
3726 19:23:42.322041 Vdram = 0
3727 19:23:42.322124 Vddq = 0
3728 19:23:42.322188 Vmddr = 0
3729 19:23:42.328552 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3730 19:23:42.331825 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3731 19:23:42.335128 MEM_TYPE=3, freq_sel=19
3732 19:23:42.338399 sv_algorithm_assistance_LP4_1600
3733 19:23:42.341707 ============ PULL DRAM RESETB DOWN ============
3734 19:23:42.344872 ========== PULL DRAM RESETB DOWN end =========
3735 19:23:42.351711 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3736 19:23:42.355130 ===================================
3737 19:23:42.355213 LPDDR4 DRAM CONFIGURATION
3738 19:23:42.358569 ===================================
3739 19:23:42.361888 EX_ROW_EN[0] = 0x0
3740 19:23:42.364917 EX_ROW_EN[1] = 0x0
3741 19:23:42.365000 LP4Y_EN = 0x0
3742 19:23:42.368395 WORK_FSP = 0x0
3743 19:23:42.368503 WL = 0x2
3744 19:23:42.371577 RL = 0x2
3745 19:23:42.371659 BL = 0x2
3746 19:23:42.375130 RPST = 0x0
3747 19:23:42.375212 RD_PRE = 0x0
3748 19:23:42.378157 WR_PRE = 0x1
3749 19:23:42.378240 WR_PST = 0x0
3750 19:23:42.381831 DBI_WR = 0x0
3751 19:23:42.381913 DBI_RD = 0x0
3752 19:23:42.385055 OTF = 0x1
3753 19:23:42.388342 ===================================
3754 19:23:42.391675 ===================================
3755 19:23:42.391758 ANA top config
3756 19:23:42.394540 ===================================
3757 19:23:42.398246 DLL_ASYNC_EN = 0
3758 19:23:42.401453 ALL_SLAVE_EN = 1
3759 19:23:42.404774 NEW_RANK_MODE = 1
3760 19:23:42.404857 DLL_IDLE_MODE = 1
3761 19:23:42.407950 LP45_APHY_COMB_EN = 1
3762 19:23:42.411392 TX_ODT_DIS = 1
3763 19:23:42.414812 NEW_8X_MODE = 1
3764 19:23:42.417879 ===================================
3765 19:23:42.421204 ===================================
3766 19:23:42.424467 data_rate = 1200
3767 19:23:42.424550 CKR = 1
3768 19:23:42.427863 DQ_P2S_RATIO = 8
3769 19:23:42.431185 ===================================
3770 19:23:42.434528 CA_P2S_RATIO = 8
3771 19:23:42.437688 DQ_CA_OPEN = 0
3772 19:23:42.441093 DQ_SEMI_OPEN = 0
3773 19:23:42.444426 CA_SEMI_OPEN = 0
3774 19:23:42.444509 CA_FULL_RATE = 0
3775 19:23:42.447788 DQ_CKDIV4_EN = 1
3776 19:23:42.451088 CA_CKDIV4_EN = 1
3777 19:23:42.454550 CA_PREDIV_EN = 0
3778 19:23:42.457797 PH8_DLY = 0
3779 19:23:42.460719 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3780 19:23:42.460802 DQ_AAMCK_DIV = 4
3781 19:23:42.464173 CA_AAMCK_DIV = 4
3782 19:23:42.467545 CA_ADMCK_DIV = 4
3783 19:23:42.470837 DQ_TRACK_CA_EN = 0
3784 19:23:42.473974 CA_PICK = 600
3785 19:23:42.477419 CA_MCKIO = 600
3786 19:23:42.477501 MCKIO_SEMI = 0
3787 19:23:42.480892 PLL_FREQ = 2288
3788 19:23:42.484338 DQ_UI_PI_RATIO = 32
3789 19:23:42.487461 CA_UI_PI_RATIO = 0
3790 19:23:42.490845 ===================================
3791 19:23:42.494175 ===================================
3792 19:23:42.497495 memory_type:LPDDR4
3793 19:23:42.497577 GP_NUM : 10
3794 19:23:42.501254 SRAM_EN : 1
3795 19:23:42.504323 MD32_EN : 0
3796 19:23:42.507769 ===================================
3797 19:23:42.507851 [ANA_INIT] >>>>>>>>>>>>>>
3798 19:23:42.511016 <<<<<< [CONFIGURE PHASE]: ANA_TX
3799 19:23:42.514416 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3800 19:23:42.517483 ===================================
3801 19:23:42.521047 data_rate = 1200,PCW = 0X5800
3802 19:23:42.524318 ===================================
3803 19:23:42.527665 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3804 19:23:42.534137 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3805 19:23:42.537437 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3806 19:23:42.544390 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3807 19:23:42.547505 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3808 19:23:42.551082 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3809 19:23:42.551244 [ANA_INIT] flow start
3810 19:23:42.554281 [ANA_INIT] PLL >>>>>>>>
3811 19:23:42.558151 [ANA_INIT] PLL <<<<<<<<
3812 19:23:42.558310 [ANA_INIT] MIDPI >>>>>>>>
3813 19:23:42.560907 [ANA_INIT] MIDPI <<<<<<<<
3814 19:23:42.564121 [ANA_INIT] DLL >>>>>>>>
3815 19:23:42.564265 [ANA_INIT] flow end
3816 19:23:42.570744 ============ LP4 DIFF to SE enter ============
3817 19:23:42.574120 ============ LP4 DIFF to SE exit ============
3818 19:23:42.577343 [ANA_INIT] <<<<<<<<<<<<<
3819 19:23:42.581073 [Flow] Enable top DCM control >>>>>
3820 19:23:42.583971 [Flow] Enable top DCM control <<<<<
3821 19:23:42.584130 Enable DLL master slave shuffle
3822 19:23:42.590956 ==============================================================
3823 19:23:42.594329 Gating Mode config
3824 19:23:42.597448 ==============================================================
3825 19:23:42.601125 Config description:
3826 19:23:42.610825 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3827 19:23:42.617429 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3828 19:23:42.621059 SELPH_MODE 0: By rank 1: By Phase
3829 19:23:42.627596 ==============================================================
3830 19:23:42.630625 GAT_TRACK_EN = 1
3831 19:23:42.633893 RX_GATING_MODE = 2
3832 19:23:42.637635 RX_GATING_TRACK_MODE = 2
3833 19:23:42.640656 SELPH_MODE = 1
3834 19:23:42.644093 PICG_EARLY_EN = 1
3835 19:23:42.644484 VALID_LAT_VALUE = 1
3836 19:23:42.650453 ==============================================================
3837 19:23:42.653795 Enter into Gating configuration >>>>
3838 19:23:42.657277 Exit from Gating configuration <<<<
3839 19:23:42.660433 Enter into DVFS_PRE_config >>>>>
3840 19:23:42.670126 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3841 19:23:42.673592 Exit from DVFS_PRE_config <<<<<
3842 19:23:42.676754 Enter into PICG configuration >>>>
3843 19:23:42.680070 Exit from PICG configuration <<<<
3844 19:23:42.683581 [RX_INPUT] configuration >>>>>
3845 19:23:42.686825 [RX_INPUT] configuration <<<<<
3846 19:23:42.690179 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3847 19:23:42.696728 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3848 19:23:42.703551 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3849 19:23:42.709894 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3850 19:23:42.716510 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3851 19:23:42.723532 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3852 19:23:42.726854 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3853 19:23:42.729991 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3854 19:23:42.733168 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3855 19:23:42.736489 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3856 19:23:42.743068 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3857 19:23:42.746559 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3858 19:23:42.749759 ===================================
3859 19:23:42.753084 LPDDR4 DRAM CONFIGURATION
3860 19:23:42.756430 ===================================
3861 19:23:42.756514 EX_ROW_EN[0] = 0x0
3862 19:23:42.759625 EX_ROW_EN[1] = 0x0
3863 19:23:42.759709 LP4Y_EN = 0x0
3864 19:23:42.762949 WORK_FSP = 0x0
3865 19:23:42.763031 WL = 0x2
3866 19:23:42.766297 RL = 0x2
3867 19:23:42.769566 BL = 0x2
3868 19:23:42.769649 RPST = 0x0
3869 19:23:42.773260 RD_PRE = 0x0
3870 19:23:42.773387 WR_PRE = 0x1
3871 19:23:42.776363 WR_PST = 0x0
3872 19:23:42.776445 DBI_WR = 0x0
3873 19:23:42.779920 DBI_RD = 0x0
3874 19:23:42.780003 OTF = 0x1
3875 19:23:42.783160 ===================================
3876 19:23:42.786336 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3877 19:23:42.792791 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3878 19:23:42.796210 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3879 19:23:42.799543 ===================================
3880 19:23:42.802728 LPDDR4 DRAM CONFIGURATION
3881 19:23:42.806284 ===================================
3882 19:23:42.806368 EX_ROW_EN[0] = 0x10
3883 19:23:42.809598 EX_ROW_EN[1] = 0x0
3884 19:23:42.809682 LP4Y_EN = 0x0
3885 19:23:42.812779 WORK_FSP = 0x0
3886 19:23:42.812861 WL = 0x2
3887 19:23:42.816037 RL = 0x2
3888 19:23:42.816119 BL = 0x2
3889 19:23:42.819436 RPST = 0x0
3890 19:23:42.819519 RD_PRE = 0x0
3891 19:23:42.822671 WR_PRE = 0x1
3892 19:23:42.822754 WR_PST = 0x0
3893 19:23:42.826492 DBI_WR = 0x0
3894 19:23:42.829800 DBI_RD = 0x0
3895 19:23:42.829883 OTF = 0x1
3896 19:23:42.833105 ===================================
3897 19:23:42.839420 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3898 19:23:42.843188 nWR fixed to 30
3899 19:23:42.846143 [ModeRegInit_LP4] CH0 RK0
3900 19:23:42.846225 [ModeRegInit_LP4] CH0 RK1
3901 19:23:42.849616 [ModeRegInit_LP4] CH1 RK0
3902 19:23:42.852946 [ModeRegInit_LP4] CH1 RK1
3903 19:23:42.853029 match AC timing 17
3904 19:23:42.859707 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3905 19:23:42.862857 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3906 19:23:42.866215 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3907 19:23:42.873285 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3908 19:23:42.876209 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3909 19:23:42.876292 ==
3910 19:23:42.879920 Dram Type= 6, Freq= 0, CH_0, rank 0
3911 19:23:42.882904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3912 19:23:42.882988 ==
3913 19:23:42.889760 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3914 19:23:42.896387 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3915 19:23:42.899571 [CA 0] Center 36 (6~67) winsize 62
3916 19:23:42.903414 [CA 1] Center 36 (6~67) winsize 62
3917 19:23:42.906161 [CA 2] Center 34 (4~65) winsize 62
3918 19:23:42.909876 [CA 3] Center 34 (3~65) winsize 63
3919 19:23:42.913213 [CA 4] Center 33 (3~64) winsize 62
3920 19:23:42.916224 [CA 5] Center 33 (2~64) winsize 63
3921 19:23:42.916306
3922 19:23:42.919743 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3923 19:23:42.919825
3924 19:23:42.923092 [CATrainingPosCal] consider 1 rank data
3925 19:23:42.926314 u2DelayCellTimex100 = 270/100 ps
3926 19:23:42.929652 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3927 19:23:42.932925 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3928 19:23:42.936258 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3929 19:23:42.939350 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3930 19:23:42.942631 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3931 19:23:42.945989 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
3932 19:23:42.946071
3933 19:23:42.952750 CA PerBit enable=1, Macro0, CA PI delay=33
3934 19:23:42.952834
3935 19:23:42.955995 [CBTSetCACLKResult] CA Dly = 33
3936 19:23:42.956078 CS Dly: 4 (0~35)
3937 19:23:42.956142 ==
3938 19:23:42.959311 Dram Type= 6, Freq= 0, CH_0, rank 1
3939 19:23:42.962595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3940 19:23:42.962677 ==
3941 19:23:42.969286 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3942 19:23:42.976141 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3943 19:23:42.979415 [CA 0] Center 36 (6~67) winsize 62
3944 19:23:42.982624 [CA 1] Center 36 (6~67) winsize 62
3945 19:23:42.985859 [CA 2] Center 35 (5~66) winsize 62
3946 19:23:42.989231 [CA 3] Center 34 (4~65) winsize 62
3947 19:23:42.992427 [CA 4] Center 34 (3~65) winsize 63
3948 19:23:42.995799 [CA 5] Center 33 (3~64) winsize 62
3949 19:23:42.995898
3950 19:23:42.999244 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3951 19:23:42.999381
3952 19:23:43.002436 [CATrainingPosCal] consider 2 rank data
3953 19:23:43.005616 u2DelayCellTimex100 = 270/100 ps
3954 19:23:43.009414 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3955 19:23:43.012460 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3956 19:23:43.015893 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
3957 19:23:43.018892 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3958 19:23:43.025719 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3959 19:23:43.029062 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3960 19:23:43.029178
3961 19:23:43.032403 CA PerBit enable=1, Macro0, CA PI delay=33
3962 19:23:43.032486
3963 19:23:43.035395 [CBTSetCACLKResult] CA Dly = 33
3964 19:23:43.035478 CS Dly: 5 (0~37)
3965 19:23:43.035544
3966 19:23:43.039010 ----->DramcWriteLeveling(PI) begin...
3967 19:23:43.039093 ==
3968 19:23:43.042696 Dram Type= 6, Freq= 0, CH_0, rank 0
3969 19:23:43.049364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3970 19:23:43.049760 ==
3971 19:23:43.052901 Write leveling (Byte 0): 34 => 34
3972 19:23:43.053262 Write leveling (Byte 1): 29 => 29
3973 19:23:43.056318 DramcWriteLeveling(PI) end<-----
3974 19:23:43.056812
3975 19:23:43.059165 ==
3976 19:23:43.059553 Dram Type= 6, Freq= 0, CH_0, rank 0
3977 19:23:43.066330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3978 19:23:43.066824 ==
3979 19:23:43.069669 [Gating] SW mode calibration
3980 19:23:43.076507 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3981 19:23:43.079416 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3982 19:23:43.086107 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3983 19:23:43.089588 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3984 19:23:43.092744 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3985 19:23:43.099174 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
3986 19:23:43.102365 0 9 16 | B1->B0 | 2e2e 2323 | 0 0 | (1 1) (0 0)
3987 19:23:43.106094 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3988 19:23:43.112566 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3989 19:23:43.115737 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3990 19:23:43.119386 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3991 19:23:43.125682 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3992 19:23:43.129038 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3993 19:23:43.132440 0 10 12 | B1->B0 | 2727 3838 | 1 0 | (0 0) (1 1)
3994 19:23:43.136310 0 10 16 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
3995 19:23:43.142553 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3996 19:23:43.145863 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3997 19:23:43.149076 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3998 19:23:43.155772 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3999 19:23:43.159336 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4000 19:23:43.162726 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4001 19:23:43.169031 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4002 19:23:43.172497 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 19:23:43.175941 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 19:23:43.182288 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 19:23:43.185819 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 19:23:43.189186 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 19:23:43.195879 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 19:23:43.199529 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 19:23:43.202661 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 19:23:43.209078 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 19:23:43.212308 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 19:23:43.215426 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 19:23:43.222280 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 19:23:43.225633 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 19:23:43.228710 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 19:23:43.235768 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 19:23:43.238886 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4018 19:23:43.242084 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4019 19:23:43.245430 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4020 19:23:43.248947 Total UI for P1: 0, mck2ui 16
4021 19:23:43.252321 best dqsien dly found for B0: ( 0, 13, 14)
4022 19:23:43.255439 Total UI for P1: 0, mck2ui 16
4023 19:23:43.258624 best dqsien dly found for B1: ( 0, 13, 16)
4024 19:23:43.261881 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4025 19:23:43.268726 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4026 19:23:43.269144
4027 19:23:43.272099 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4028 19:23:43.275452 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4029 19:23:43.278498 [Gating] SW calibration Done
4030 19:23:43.278913 ==
4031 19:23:43.282410 Dram Type= 6, Freq= 0, CH_0, rank 0
4032 19:23:43.285406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4033 19:23:43.285825 ==
4034 19:23:43.286171 RX Vref Scan: 0
4035 19:23:43.288505
4036 19:23:43.288977 RX Vref 0 -> 0, step: 1
4037 19:23:43.289347
4038 19:23:43.291956 RX Delay -230 -> 252, step: 16
4039 19:23:43.295415 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4040 19:23:43.301848 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4041 19:23:43.305390 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4042 19:23:43.308584 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4043 19:23:43.311945 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4044 19:23:43.315063 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4045 19:23:43.321876 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4046 19:23:43.325243 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4047 19:23:43.328346 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4048 19:23:43.331821 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4049 19:23:43.338491 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4050 19:23:43.341848 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4051 19:23:43.345470 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4052 19:23:43.348642 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4053 19:23:43.355075 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4054 19:23:43.358708 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4055 19:23:43.359124 ==
4056 19:23:43.361946 Dram Type= 6, Freq= 0, CH_0, rank 0
4057 19:23:43.365084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4058 19:23:43.365539 ==
4059 19:23:43.368326 DQS Delay:
4060 19:23:43.368741 DQS0 = 0, DQS1 = 0
4061 19:23:43.369067 DQM Delay:
4062 19:23:43.372065 DQM0 = 51, DQM1 = 38
4063 19:23:43.372577 DQ Delay:
4064 19:23:43.375522 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =49
4065 19:23:43.378976 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4066 19:23:43.381926 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =25
4067 19:23:43.385505 DQ12 =41, DQ13 =41, DQ14 =57, DQ15 =49
4068 19:23:43.386054
4069 19:23:43.386390
4070 19:23:43.386696 ==
4071 19:23:43.388507 Dram Type= 6, Freq= 0, CH_0, rank 0
4072 19:23:43.391672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4073 19:23:43.395490 ==
4074 19:23:43.396009
4075 19:23:43.396344
4076 19:23:43.396654 TX Vref Scan disable
4077 19:23:43.398864 == TX Byte 0 ==
4078 19:23:43.402028 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4079 19:23:43.405653 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4080 19:23:43.409182 == TX Byte 1 ==
4081 19:23:43.412449 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4082 19:23:43.415447 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4083 19:23:43.418797 ==
4084 19:23:43.421880 Dram Type= 6, Freq= 0, CH_0, rank 0
4085 19:23:43.425575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4086 19:23:43.426097 ==
4087 19:23:43.426433
4088 19:23:43.426746
4089 19:23:43.428540 TX Vref Scan disable
4090 19:23:43.431553 == TX Byte 0 ==
4091 19:23:43.435207 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4092 19:23:43.438186 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4093 19:23:43.441808 == TX Byte 1 ==
4094 19:23:43.445011 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4095 19:23:43.448204 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4096 19:23:43.448645
4097 19:23:43.449000 [DATLAT]
4098 19:23:43.451791 Freq=600, CH0 RK0
4099 19:23:43.452354
4100 19:23:43.452837 DATLAT Default: 0x9
4101 19:23:43.455091 0, 0xFFFF, sum = 0
4102 19:23:43.455660 1, 0xFFFF, sum = 0
4103 19:23:43.458566 2, 0xFFFF, sum = 0
4104 19:23:43.459029 3, 0xFFFF, sum = 0
4105 19:23:43.461673 4, 0xFFFF, sum = 0
4106 19:23:43.464983 5, 0xFFFF, sum = 0
4107 19:23:43.465478 6, 0xFFFF, sum = 0
4108 19:23:43.468225 7, 0xFFFF, sum = 0
4109 19:23:43.468648 8, 0x0, sum = 1
4110 19:23:43.468980 9, 0x0, sum = 2
4111 19:23:43.471764 10, 0x0, sum = 3
4112 19:23:43.472184 11, 0x0, sum = 4
4113 19:23:43.475202 best_step = 9
4114 19:23:43.475621
4115 19:23:43.475951 ==
4116 19:23:43.478147 Dram Type= 6, Freq= 0, CH_0, rank 0
4117 19:23:43.481655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4118 19:23:43.482100 ==
4119 19:23:43.484885 RX Vref Scan: 1
4120 19:23:43.485349
4121 19:23:43.485845 RX Vref 0 -> 0, step: 1
4122 19:23:43.486173
4123 19:23:43.488241 RX Delay -179 -> 252, step: 8
4124 19:23:43.488657
4125 19:23:43.491682 Set Vref, RX VrefLevel [Byte0]: 60
4126 19:23:43.494973 [Byte1]: 48
4127 19:23:43.498929
4128 19:23:43.499343 Final RX Vref Byte 0 = 60 to rank0
4129 19:23:43.502218 Final RX Vref Byte 1 = 48 to rank0
4130 19:23:43.505785 Final RX Vref Byte 0 = 60 to rank1
4131 19:23:43.508780 Final RX Vref Byte 1 = 48 to rank1==
4132 19:23:43.512212 Dram Type= 6, Freq= 0, CH_0, rank 0
4133 19:23:43.518477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4134 19:23:43.518559 ==
4135 19:23:43.518624 DQS Delay:
4136 19:23:43.518684 DQS0 = 0, DQS1 = 0
4137 19:23:43.521948 DQM Delay:
4138 19:23:43.522029 DQM0 = 49, DQM1 = 37
4139 19:23:43.525440 DQ Delay:
4140 19:23:43.528569 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4141 19:23:43.528650 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56
4142 19:23:43.532074 DQ8 =32, DQ9 =20, DQ10 =36, DQ11 =32
4143 19:23:43.538291 DQ12 =44, DQ13 =40, DQ14 =48, DQ15 =44
4144 19:23:43.538373
4145 19:23:43.538437
4146 19:23:43.545230 [DQSOSCAuto] RK0, (LSB)MR18= 0x5651, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
4147 19:23:43.548518 CH0 RK0: MR19=808, MR18=5651
4148 19:23:43.555362 CH0_RK0: MR19=0x808, MR18=0x5651, DQSOSC=393, MR23=63, INC=169, DEC=113
4149 19:23:43.555444
4150 19:23:43.558486 ----->DramcWriteLeveling(PI) begin...
4151 19:23:43.558568 ==
4152 19:23:43.561784 Dram Type= 6, Freq= 0, CH_0, rank 1
4153 19:23:43.565010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4154 19:23:43.565092 ==
4155 19:23:43.568254 Write leveling (Byte 0): 34 => 34
4156 19:23:43.571670 Write leveling (Byte 1): 30 => 30
4157 19:23:43.575078 DramcWriteLeveling(PI) end<-----
4158 19:23:43.575159
4159 19:23:43.575223 ==
4160 19:23:43.578068 Dram Type= 6, Freq= 0, CH_0, rank 1
4161 19:23:43.581413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4162 19:23:43.581522 ==
4163 19:23:43.585004 [Gating] SW mode calibration
4164 19:23:43.592041 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4165 19:23:43.598664 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4166 19:23:43.601699 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4167 19:23:43.605517 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4168 19:23:43.611780 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4169 19:23:43.615521 0 9 12 | B1->B0 | 3434 3232 | 1 1 | (0 0) (1 0)
4170 19:23:43.618512 0 9 16 | B1->B0 | 2828 2323 | 0 0 | (0 0) (1 0)
4171 19:23:43.625111 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4172 19:23:43.628348 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4173 19:23:43.631775 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4174 19:23:43.638754 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4175 19:23:43.641835 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4176 19:23:43.645421 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4177 19:23:43.652049 0 10 12 | B1->B0 | 3030 3a3a | 1 1 | (0 0) (0 0)
4178 19:23:43.654888 0 10 16 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
4179 19:23:43.658703 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4180 19:23:43.665096 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4181 19:23:43.668198 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4182 19:23:43.671695 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4183 19:23:43.678106 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4184 19:23:43.681671 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4185 19:23:43.684952 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4186 19:23:43.691352 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 19:23:43.694696 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 19:23:43.698081 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 19:23:43.705004 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 19:23:43.708499 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 19:23:43.711570 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 19:23:43.718721 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 19:23:43.721604 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 19:23:43.725019 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 19:23:43.731989 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 19:23:43.735287 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 19:23:43.738756 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 19:23:43.742160 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 19:23:43.748452 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 19:23:43.751615 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 19:23:43.754755 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4202 19:23:43.758347 Total UI for P1: 0, mck2ui 16
4203 19:23:43.761640 best dqsien dly found for B0: ( 0, 13, 10)
4204 19:23:43.768029 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4205 19:23:43.771584 Total UI for P1: 0, mck2ui 16
4206 19:23:43.775075 best dqsien dly found for B1: ( 0, 13, 12)
4207 19:23:43.778240 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4208 19:23:43.781554 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4209 19:23:43.782069
4210 19:23:43.784992 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4211 19:23:43.788221 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4212 19:23:43.791475 [Gating] SW calibration Done
4213 19:23:43.791889 ==
4214 19:23:43.795457 Dram Type= 6, Freq= 0, CH_0, rank 1
4215 19:23:43.798877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4216 19:23:43.799393 ==
4217 19:23:43.801562 RX Vref Scan: 0
4218 19:23:43.801977
4219 19:23:43.802305 RX Vref 0 -> 0, step: 1
4220 19:23:43.802609
4221 19:23:43.805028 RX Delay -230 -> 252, step: 16
4222 19:23:43.811664 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4223 19:23:43.815519 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4224 19:23:43.818080 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4225 19:23:43.822038 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4226 19:23:43.825463 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4227 19:23:43.831827 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4228 19:23:43.835354 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4229 19:23:43.838296 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4230 19:23:43.841185 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4231 19:23:43.847904 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4232 19:23:43.851202 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4233 19:23:43.854484 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4234 19:23:43.857952 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4235 19:23:43.864629 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4236 19:23:43.867691 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4237 19:23:43.871261 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4238 19:23:43.871678 ==
4239 19:23:43.874854 Dram Type= 6, Freq= 0, CH_0, rank 1
4240 19:23:43.877891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4241 19:23:43.878307 ==
4242 19:23:43.881236 DQS Delay:
4243 19:23:43.881676 DQS0 = 0, DQS1 = 0
4244 19:23:43.884850 DQM Delay:
4245 19:23:43.885325 DQM0 = 49, DQM1 = 41
4246 19:23:43.885671 DQ Delay:
4247 19:23:43.887906 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4248 19:23:43.891435 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4249 19:23:43.894470 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4250 19:23:43.897819 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =49
4251 19:23:43.898232
4252 19:23:43.898557
4253 19:23:43.901248 ==
4254 19:23:43.901697 Dram Type= 6, Freq= 0, CH_0, rank 1
4255 19:23:43.908063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4256 19:23:43.908582 ==
4257 19:23:43.908912
4258 19:23:43.909216
4259 19:23:43.911272 TX Vref Scan disable
4260 19:23:43.911792 == TX Byte 0 ==
4261 19:23:43.914761 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4262 19:23:43.921532 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4263 19:23:43.922072 == TX Byte 1 ==
4264 19:23:43.927939 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4265 19:23:43.931199 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4266 19:23:43.931617 ==
4267 19:23:43.934563 Dram Type= 6, Freq= 0, CH_0, rank 1
4268 19:23:43.938285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4269 19:23:43.938803 ==
4270 19:23:43.939130
4271 19:23:43.939434
4272 19:23:43.941117 TX Vref Scan disable
4273 19:23:43.944989 == TX Byte 0 ==
4274 19:23:43.947915 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4275 19:23:43.951414 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4276 19:23:43.954841 == TX Byte 1 ==
4277 19:23:43.957912 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4278 19:23:43.960972 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4279 19:23:43.961426
4280 19:23:43.964466 [DATLAT]
4281 19:23:43.964976 Freq=600, CH0 RK1
4282 19:23:43.965335
4283 19:23:43.967561 DATLAT Default: 0x9
4284 19:23:43.968010 0, 0xFFFF, sum = 0
4285 19:23:43.971074 1, 0xFFFF, sum = 0
4286 19:23:43.971492 2, 0xFFFF, sum = 0
4287 19:23:43.974348 3, 0xFFFF, sum = 0
4288 19:23:43.974767 4, 0xFFFF, sum = 0
4289 19:23:43.977475 5, 0xFFFF, sum = 0
4290 19:23:43.977896 6, 0xFFFF, sum = 0
4291 19:23:43.981162 7, 0xFFFF, sum = 0
4292 19:23:43.981620 8, 0x0, sum = 1
4293 19:23:43.984574 9, 0x0, sum = 2
4294 19:23:43.984983 10, 0x0, sum = 3
4295 19:23:43.987443 11, 0x0, sum = 4
4296 19:23:43.987917 best_step = 9
4297 19:23:43.988235
4298 19:23:43.988526 ==
4299 19:23:43.991004 Dram Type= 6, Freq= 0, CH_0, rank 1
4300 19:23:43.994362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4301 19:23:43.997437 ==
4302 19:23:43.997892 RX Vref Scan: 0
4303 19:23:43.998364
4304 19:23:44.000935 RX Vref 0 -> 0, step: 1
4305 19:23:44.001367
4306 19:23:44.004367 RX Delay -179 -> 252, step: 8
4307 19:23:44.007518 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4308 19:23:44.010912 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4309 19:23:44.017913 iDelay=205, Bit 2, Center 48 (-99 ~ 196) 296
4310 19:23:44.020455 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4311 19:23:44.024305 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4312 19:23:44.027695 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4313 19:23:44.030445 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4314 19:23:44.037644 iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296
4315 19:23:44.040932 iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288
4316 19:23:44.044185 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4317 19:23:44.047391 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4318 19:23:44.053916 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4319 19:23:44.057566 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4320 19:23:44.060509 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4321 19:23:44.063903 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4322 19:23:44.067256 iDelay=205, Bit 15, Center 48 (-91 ~ 188) 280
4323 19:23:44.067801 ==
4324 19:23:44.070544 Dram Type= 6, Freq= 0, CH_0, rank 1
4325 19:23:44.077235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4326 19:23:44.077861 ==
4327 19:23:44.078205 DQS Delay:
4328 19:23:44.080373 DQS0 = 0, DQS1 = 0
4329 19:23:44.080778 DQM Delay:
4330 19:23:44.083595 DQM0 = 49, DQM1 = 41
4331 19:23:44.083675 DQ Delay:
4332 19:23:44.086748 DQ0 =48, DQ1 =48, DQ2 =48, DQ3 =44
4333 19:23:44.090342 DQ4 =48, DQ5 =40, DQ6 =60, DQ7 =56
4334 19:23:44.093306 DQ8 =36, DQ9 =28, DQ10 =40, DQ11 =36
4335 19:23:44.096961 DQ12 =48, DQ13 =44, DQ14 =52, DQ15 =48
4336 19:23:44.097040
4337 19:23:44.097103
4338 19:23:44.103346 [DQSOSCAuto] RK1, (LSB)MR18= 0x6532, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 390 ps
4339 19:23:44.106776 CH0 RK1: MR19=808, MR18=6532
4340 19:23:44.113566 CH0_RK1: MR19=0x808, MR18=0x6532, DQSOSC=390, MR23=63, INC=172, DEC=114
4341 19:23:44.116528 [RxdqsGatingPostProcess] freq 600
4342 19:23:44.120140 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4343 19:23:44.123437 Pre-setting of DQS Precalculation
4344 19:23:44.129758 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4345 19:23:44.129844 ==
4346 19:23:44.133236 Dram Type= 6, Freq= 0, CH_1, rank 0
4347 19:23:44.136572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4348 19:23:44.136652 ==
4349 19:23:44.143343 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4350 19:23:44.149840 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4351 19:23:44.153087 [CA 0] Center 35 (5~66) winsize 62
4352 19:23:44.156466 [CA 1] Center 35 (5~66) winsize 62
4353 19:23:44.159824 [CA 2] Center 34 (4~65) winsize 62
4354 19:23:44.163071 [CA 3] Center 33 (3~64) winsize 62
4355 19:23:44.166506 [CA 4] Center 34 (3~65) winsize 63
4356 19:23:44.169939 [CA 5] Center 33 (3~64) winsize 62
4357 19:23:44.170018
4358 19:23:44.172907 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4359 19:23:44.173012
4360 19:23:44.176202 [CATrainingPosCal] consider 1 rank data
4361 19:23:44.180080 u2DelayCellTimex100 = 270/100 ps
4362 19:23:44.183427 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4363 19:23:44.186550 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4364 19:23:44.189769 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4365 19:23:44.193306 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4366 19:23:44.196810 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4367 19:23:44.200016 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4368 19:23:44.200210
4369 19:23:44.203569 CA PerBit enable=1, Macro0, CA PI delay=33
4370 19:23:44.206452
4371 19:23:44.206613 [CBTSetCACLKResult] CA Dly = 33
4372 19:23:44.210162 CS Dly: 3 (0~34)
4373 19:23:44.210374 ==
4374 19:23:44.213478 Dram Type= 6, Freq= 0, CH_1, rank 1
4375 19:23:44.216707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4376 19:23:44.216947 ==
4377 19:23:44.223337 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4378 19:23:44.230122 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4379 19:23:44.233413 [CA 0] Center 36 (6~66) winsize 61
4380 19:23:44.236620 [CA 1] Center 35 (5~66) winsize 62
4381 19:23:44.240022 [CA 2] Center 34 (4~65) winsize 62
4382 19:23:44.243523 [CA 3] Center 34 (4~65) winsize 62
4383 19:23:44.246839 [CA 4] Center 34 (4~65) winsize 62
4384 19:23:44.250208 [CA 5] Center 33 (3~64) winsize 62
4385 19:23:44.250718
4386 19:23:44.253365 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4387 19:23:44.253881
4388 19:23:44.256333 [CATrainingPosCal] consider 2 rank data
4389 19:23:44.259456 u2DelayCellTimex100 = 270/100 ps
4390 19:23:44.262912 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4391 19:23:44.266220 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4392 19:23:44.269692 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4393 19:23:44.272868 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4394 19:23:44.276209 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4395 19:23:44.279724 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4396 19:23:44.279837
4397 19:23:44.286173 CA PerBit enable=1, Macro0, CA PI delay=33
4398 19:23:44.286389
4399 19:23:44.289659 [CBTSetCACLKResult] CA Dly = 33
4400 19:23:44.289809 CS Dly: 4 (0~37)
4401 19:23:44.289918
4402 19:23:44.292569 ----->DramcWriteLeveling(PI) begin...
4403 19:23:44.292723 ==
4404 19:23:44.296038 Dram Type= 6, Freq= 0, CH_1, rank 0
4405 19:23:44.299375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4406 19:23:44.299549 ==
4407 19:23:44.303189 Write leveling (Byte 0): 29 => 29
4408 19:23:44.306109 Write leveling (Byte 1): 31 => 31
4409 19:23:44.309530 DramcWriteLeveling(PI) end<-----
4410 19:23:44.309858
4411 19:23:44.310059 ==
4412 19:23:44.313128 Dram Type= 6, Freq= 0, CH_1, rank 0
4413 19:23:44.319719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4414 19:23:44.320237 ==
4415 19:23:44.320579 [Gating] SW mode calibration
4416 19:23:44.329820 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4417 19:23:44.332967 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4418 19:23:44.336508 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4419 19:23:44.342862 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4420 19:23:44.346529 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4421 19:23:44.349708 0 9 12 | B1->B0 | 2b2b 2e2e | 0 0 | (0 1) (1 1)
4422 19:23:44.356371 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4423 19:23:44.359571 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4424 19:23:44.363263 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4425 19:23:44.369723 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4426 19:23:44.372813 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4427 19:23:44.376406 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4428 19:23:44.383322 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4429 19:23:44.386041 0 10 12 | B1->B0 | 3c3c 4242 | 1 1 | (0 0) (0 0)
4430 19:23:44.389290 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4431 19:23:44.395803 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4432 19:23:44.399393 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4433 19:23:44.403039 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4434 19:23:44.409275 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4435 19:23:44.412881 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4436 19:23:44.416064 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4437 19:23:44.422841 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4438 19:23:44.426075 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 19:23:44.429455 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 19:23:44.435838 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 19:23:44.439697 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 19:23:44.442885 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 19:23:44.446160 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 19:23:44.452835 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 19:23:44.456211 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 19:23:44.459308 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 19:23:44.466160 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 19:23:44.469285 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 19:23:44.472824 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 19:23:44.479157 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 19:23:44.482624 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 19:23:44.486133 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4453 19:23:44.492176 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4454 19:23:44.496329 Total UI for P1: 0, mck2ui 16
4455 19:23:44.499082 best dqsien dly found for B0: ( 0, 13, 8)
4456 19:23:44.499600 Total UI for P1: 0, mck2ui 16
4457 19:23:44.505960 best dqsien dly found for B1: ( 0, 13, 10)
4458 19:23:44.509077 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4459 19:23:44.512645 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4460 19:23:44.513203
4461 19:23:44.515712 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4462 19:23:44.519100 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4463 19:23:44.521975 [Gating] SW calibration Done
4464 19:23:44.522398 ==
4465 19:23:44.525427 Dram Type= 6, Freq= 0, CH_1, rank 0
4466 19:23:44.528910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4467 19:23:44.529450 ==
4468 19:23:44.532151 RX Vref Scan: 0
4469 19:23:44.532573
4470 19:23:44.532906 RX Vref 0 -> 0, step: 1
4471 19:23:44.535640
4472 19:23:44.536153 RX Delay -230 -> 252, step: 16
4473 19:23:44.542249 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4474 19:23:44.545368 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4475 19:23:44.548631 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4476 19:23:44.551910 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4477 19:23:44.558939 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4478 19:23:44.561931 iDelay=218, Bit 5, Center 57 (-86 ~ 201) 288
4479 19:23:44.565239 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4480 19:23:44.568697 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4481 19:23:44.571835 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4482 19:23:44.578540 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4483 19:23:44.581714 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4484 19:23:44.585215 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4485 19:23:44.588607 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4486 19:23:44.595249 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4487 19:23:44.598823 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4488 19:23:44.601970 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4489 19:23:44.602397 ==
4490 19:23:44.605194 Dram Type= 6, Freq= 0, CH_1, rank 0
4491 19:23:44.608384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4492 19:23:44.608906 ==
4493 19:23:44.611736 DQS Delay:
4494 19:23:44.612250 DQS0 = 0, DQS1 = 0
4495 19:23:44.615138 DQM Delay:
4496 19:23:44.615659 DQM0 = 52, DQM1 = 45
4497 19:23:44.615998 DQ Delay:
4498 19:23:44.618169 DQ0 =57, DQ1 =49, DQ2 =41, DQ3 =49
4499 19:23:44.621757 DQ4 =49, DQ5 =57, DQ6 =65, DQ7 =49
4500 19:23:44.624796 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =33
4501 19:23:44.628459 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4502 19:23:44.628972
4503 19:23:44.629348
4504 19:23:44.631379 ==
4505 19:23:44.634743 Dram Type= 6, Freq= 0, CH_1, rank 0
4506 19:23:44.638325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4507 19:23:44.638843 ==
4508 19:23:44.639180
4509 19:23:44.639490
4510 19:23:44.641181 TX Vref Scan disable
4511 19:23:44.641629 == TX Byte 0 ==
4512 19:23:44.648210 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4513 19:23:44.651371 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4514 19:23:44.651790 == TX Byte 1 ==
4515 19:23:44.658381 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4516 19:23:44.661826 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4517 19:23:44.662356 ==
4518 19:23:44.664820 Dram Type= 6, Freq= 0, CH_1, rank 0
4519 19:23:44.668333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4520 19:23:44.668855 ==
4521 19:23:44.669183
4522 19:23:44.669520
4523 19:23:44.671628 TX Vref Scan disable
4524 19:23:44.674703 == TX Byte 0 ==
4525 19:23:44.678242 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4526 19:23:44.681246 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4527 19:23:44.684794 == TX Byte 1 ==
4528 19:23:44.688488 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4529 19:23:44.691229 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4530 19:23:44.691761
4531 19:23:44.694407 [DATLAT]
4532 19:23:44.694819 Freq=600, CH1 RK0
4533 19:23:44.695150
4534 19:23:44.697913 DATLAT Default: 0x9
4535 19:23:44.698323 0, 0xFFFF, sum = 0
4536 19:23:44.701590 1, 0xFFFF, sum = 0
4537 19:23:44.702113 2, 0xFFFF, sum = 0
4538 19:23:44.704754 3, 0xFFFF, sum = 0
4539 19:23:44.705337 4, 0xFFFF, sum = 0
4540 19:23:44.708166 5, 0xFFFF, sum = 0
4541 19:23:44.708687 6, 0xFFFF, sum = 0
4542 19:23:44.710904 7, 0xFFFF, sum = 0
4543 19:23:44.711323 8, 0x0, sum = 1
4544 19:23:44.714256 9, 0x0, sum = 2
4545 19:23:44.714676 10, 0x0, sum = 3
4546 19:23:44.718239 11, 0x0, sum = 4
4547 19:23:44.718763 best_step = 9
4548 19:23:44.719093
4549 19:23:44.719397 ==
4550 19:23:44.720904 Dram Type= 6, Freq= 0, CH_1, rank 0
4551 19:23:44.724255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4552 19:23:44.727526 ==
4553 19:23:44.728042 RX Vref Scan: 1
4554 19:23:44.728377
4555 19:23:44.730832 RX Vref 0 -> 0, step: 1
4556 19:23:44.731246
4557 19:23:44.734220 RX Delay -163 -> 252, step: 8
4558 19:23:44.734643
4559 19:23:44.737727 Set Vref, RX VrefLevel [Byte0]: 51
4560 19:23:44.741467 [Byte1]: 52
4561 19:23:44.742015
4562 19:23:44.744529 Final RX Vref Byte 0 = 51 to rank0
4563 19:23:44.747925 Final RX Vref Byte 1 = 52 to rank0
4564 19:23:44.750826 Final RX Vref Byte 0 = 51 to rank1
4565 19:23:44.754311 Final RX Vref Byte 1 = 52 to rank1==
4566 19:23:44.757880 Dram Type= 6, Freq= 0, CH_1, rank 0
4567 19:23:44.761612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4568 19:23:44.762190 ==
4569 19:23:44.762526 DQS Delay:
4570 19:23:44.764240 DQS0 = 0, DQS1 = 0
4571 19:23:44.764758 DQM Delay:
4572 19:23:44.767913 DQM0 = 48, DQM1 = 41
4573 19:23:44.768437 DQ Delay:
4574 19:23:44.770844 DQ0 =56, DQ1 =40, DQ2 =36, DQ3 =44
4575 19:23:44.773932 DQ4 =52, DQ5 =60, DQ6 =56, DQ7 =44
4576 19:23:44.777696 DQ8 =28, DQ9 =28, DQ10 =48, DQ11 =32
4577 19:23:44.780809 DQ12 =52, DQ13 =48, DQ14 =48, DQ15 =48
4578 19:23:44.781351
4579 19:23:44.781695
4580 19:23:44.790742 [DQSOSCAuto] RK0, (LSB)MR18= 0x4c73, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4581 19:23:44.791247 CH1 RK0: MR19=808, MR18=4C73
4582 19:23:44.797846 CH1_RK0: MR19=0x808, MR18=0x4C73, DQSOSC=388, MR23=63, INC=174, DEC=116
4583 19:23:44.798401
4584 19:23:44.801388 ----->DramcWriteLeveling(PI) begin...
4585 19:23:44.801907 ==
4586 19:23:44.804127 Dram Type= 6, Freq= 0, CH_1, rank 1
4587 19:23:44.810624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4588 19:23:44.811145 ==
4589 19:23:44.813852 Write leveling (Byte 0): 29 => 29
4590 19:23:44.817535 Write leveling (Byte 1): 30 => 30
4591 19:23:44.817947 DramcWriteLeveling(PI) end<-----
4592 19:23:44.818269
4593 19:23:44.821181 ==
4594 19:23:44.824553 Dram Type= 6, Freq= 0, CH_1, rank 1
4595 19:23:44.827494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4596 19:23:44.828027 ==
4597 19:23:44.830555 [Gating] SW mode calibration
4598 19:23:44.837436 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4599 19:23:44.840724 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4600 19:23:44.847329 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4601 19:23:44.850650 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4602 19:23:44.853652 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4603 19:23:44.860553 0 9 12 | B1->B0 | 2828 2f2f | 1 1 | (1 0) (0 0)
4604 19:23:44.863575 0 9 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4605 19:23:44.867128 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4606 19:23:44.873670 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4607 19:23:44.877356 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4608 19:23:44.880519 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4609 19:23:44.887135 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4610 19:23:44.890570 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4611 19:23:44.893508 0 10 12 | B1->B0 | 4141 2e2e | 0 0 | (0 0) (0 0)
4612 19:23:44.900330 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4613 19:23:44.903974 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4614 19:23:44.907029 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4615 19:23:44.913487 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4616 19:23:44.916785 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4617 19:23:44.920365 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4618 19:23:44.927186 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4619 19:23:44.930458 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4620 19:23:44.933210 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 19:23:44.940266 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 19:23:44.943645 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 19:23:44.947013 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 19:23:44.953569 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 19:23:44.956743 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 19:23:44.960000 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 19:23:44.966764 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 19:23:44.970047 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 19:23:44.973261 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 19:23:44.976514 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 19:23:44.983170 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 19:23:44.986588 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 19:23:44.989876 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 19:23:44.996415 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 19:23:44.999512 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4636 19:23:45.007363 Total UI for P1: 0, mck2ui 16
4637 19:23:45.007778 best dqsien dly found for B0: ( 0, 13, 10)
4638 19:23:45.009476 Total UI for P1: 0, mck2ui 16
4639 19:23:45.012853 best dqsien dly found for B1: ( 0, 13, 10)
4640 19:23:45.016175 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4641 19:23:45.019566 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4642 19:23:45.020004
4643 19:23:45.022560 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4644 19:23:45.029274 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4645 19:23:45.029724 [Gating] SW calibration Done
4646 19:23:45.030060 ==
4647 19:23:45.032910 Dram Type= 6, Freq= 0, CH_1, rank 1
4648 19:23:45.039627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4649 19:23:45.040145 ==
4650 19:23:45.040481 RX Vref Scan: 0
4651 19:23:45.040791
4652 19:23:45.042943 RX Vref 0 -> 0, step: 1
4653 19:23:45.043461
4654 19:23:45.046136 RX Delay -230 -> 252, step: 16
4655 19:23:45.049910 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4656 19:23:45.052859 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4657 19:23:45.056323 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4658 19:23:45.062607 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4659 19:23:45.066136 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4660 19:23:45.069355 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4661 19:23:45.072869 iDelay=218, Bit 6, Center 57 (-86 ~ 201) 288
4662 19:23:45.076006 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4663 19:23:45.082528 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4664 19:23:45.086128 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4665 19:23:45.088967 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4666 19:23:45.092746 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4667 19:23:45.099145 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4668 19:23:45.102875 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4669 19:23:45.105537 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4670 19:23:45.109445 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4671 19:23:45.112819 ==
4672 19:23:45.113375 Dram Type= 6, Freq= 0, CH_1, rank 1
4673 19:23:45.119229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4674 19:23:45.119749 ==
4675 19:23:45.120090 DQS Delay:
4676 19:23:45.122245 DQS0 = 0, DQS1 = 0
4677 19:23:45.122662 DQM Delay:
4678 19:23:45.125744 DQM0 = 51, DQM1 = 46
4679 19:23:45.126261 DQ Delay:
4680 19:23:45.129316 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4681 19:23:45.132461 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4682 19:23:45.136183 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4683 19:23:45.139076 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4684 19:23:45.139603
4685 19:23:45.139937
4686 19:23:45.140244 ==
4687 19:23:45.142227 Dram Type= 6, Freq= 0, CH_1, rank 1
4688 19:23:45.145905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4689 19:23:45.146429 ==
4690 19:23:45.146762
4691 19:23:45.147075
4692 19:23:45.149377 TX Vref Scan disable
4693 19:23:45.152137 == TX Byte 0 ==
4694 19:23:45.155607 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4695 19:23:45.159011 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4696 19:23:45.162524 == TX Byte 1 ==
4697 19:23:45.165525 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4698 19:23:45.169212 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4699 19:23:45.169793 ==
4700 19:23:45.172539 Dram Type= 6, Freq= 0, CH_1, rank 1
4701 19:23:45.175585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4702 19:23:45.176010 ==
4703 19:23:45.179031
4704 19:23:45.179451
4705 19:23:45.179786 TX Vref Scan disable
4706 19:23:45.182671 == TX Byte 0 ==
4707 19:23:45.186186 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4708 19:23:45.189242 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4709 19:23:45.192755 == TX Byte 1 ==
4710 19:23:45.195751 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4711 19:23:45.202944 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4712 19:23:45.203480
4713 19:23:45.203819 [DATLAT]
4714 19:23:45.204128 Freq=600, CH1 RK1
4715 19:23:45.204425
4716 19:23:45.206177 DATLAT Default: 0x9
4717 19:23:45.206596 0, 0xFFFF, sum = 0
4718 19:23:45.209725 1, 0xFFFF, sum = 0
4719 19:23:45.210249 2, 0xFFFF, sum = 0
4720 19:23:45.212743 3, 0xFFFF, sum = 0
4721 19:23:45.216214 4, 0xFFFF, sum = 0
4722 19:23:45.216737 5, 0xFFFF, sum = 0
4723 19:23:45.219528 6, 0xFFFF, sum = 0
4724 19:23:45.220050 7, 0xFFFF, sum = 0
4725 19:23:45.220389 8, 0x0, sum = 1
4726 19:23:45.222872 9, 0x0, sum = 2
4727 19:23:45.223390 10, 0x0, sum = 3
4728 19:23:45.226219 11, 0x0, sum = 4
4729 19:23:45.226745 best_step = 9
4730 19:23:45.227078
4731 19:23:45.227382 ==
4732 19:23:45.229468 Dram Type= 6, Freq= 0, CH_1, rank 1
4733 19:23:45.236035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4734 19:23:45.236550 ==
4735 19:23:45.236887 RX Vref Scan: 0
4736 19:23:45.237220
4737 19:23:45.239381 RX Vref 0 -> 0, step: 1
4738 19:23:45.239895
4739 19:23:45.242776 RX Delay -163 -> 252, step: 8
4740 19:23:45.245482 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4741 19:23:45.252603 iDelay=205, Bit 1, Center 44 (-91 ~ 180) 272
4742 19:23:45.256003 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4743 19:23:45.259401 iDelay=205, Bit 3, Center 48 (-91 ~ 188) 280
4744 19:23:45.262771 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4745 19:23:45.265871 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4746 19:23:45.272435 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4747 19:23:45.275665 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4748 19:23:45.278686 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4749 19:23:45.282216 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4750 19:23:45.285469 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4751 19:23:45.292209 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4752 19:23:45.295874 iDelay=205, Bit 12, Center 52 (-91 ~ 196) 288
4753 19:23:45.299100 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4754 19:23:45.301838 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4755 19:23:45.305609 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4756 19:23:45.309073 ==
4757 19:23:45.312397 Dram Type= 6, Freq= 0, CH_1, rank 1
4758 19:23:45.315263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4759 19:23:45.315682 ==
4760 19:23:45.316009 DQS Delay:
4761 19:23:45.318936 DQS0 = 0, DQS1 = 0
4762 19:23:45.319451 DQM Delay:
4763 19:23:45.322496 DQM0 = 49, DQM1 = 45
4764 19:23:45.323014 DQ Delay:
4765 19:23:45.325666 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =48
4766 19:23:45.329390 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4767 19:23:45.331935 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =40
4768 19:23:45.335492 DQ12 =52, DQ13 =52, DQ14 =48, DQ15 =56
4769 19:23:45.336009
4770 19:23:45.336338
4771 19:23:45.342218 [DQSOSCAuto] RK1, (LSB)MR18= 0x571e, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
4772 19:23:45.345731 CH1 RK1: MR19=808, MR18=571E
4773 19:23:45.352332 CH1_RK1: MR19=0x808, MR18=0x571E, DQSOSC=393, MR23=63, INC=169, DEC=113
4774 19:23:45.355963 [RxdqsGatingPostProcess] freq 600
4775 19:23:45.362778 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4776 19:23:45.363338 Pre-setting of DQS Precalculation
4777 19:23:45.369129 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4778 19:23:45.375461 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4779 19:23:45.382167 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4780 19:23:45.382762
4781 19:23:45.383124
4782 19:23:45.385736 [Calibration Summary] 1200 Mbps
4783 19:23:45.388690 CH 0, Rank 0
4784 19:23:45.389149 SW Impedance : PASS
4785 19:23:45.391879 DUTY Scan : NO K
4786 19:23:45.395397 ZQ Calibration : PASS
4787 19:23:45.395861 Jitter Meter : NO K
4788 19:23:45.398432 CBT Training : PASS
4789 19:23:45.398850 Write leveling : PASS
4790 19:23:45.401834 RX DQS gating : PASS
4791 19:23:45.405182 RX DQ/DQS(RDDQC) : PASS
4792 19:23:45.405636 TX DQ/DQS : PASS
4793 19:23:45.408415 RX DATLAT : PASS
4794 19:23:45.412067 RX DQ/DQS(Engine): PASS
4795 19:23:45.412574 TX OE : NO K
4796 19:23:45.415168 All Pass.
4797 19:23:45.415577
4798 19:23:45.415900 CH 0, Rank 1
4799 19:23:45.418749 SW Impedance : PASS
4800 19:23:45.419295 DUTY Scan : NO K
4801 19:23:45.421415 ZQ Calibration : PASS
4802 19:23:45.425406 Jitter Meter : NO K
4803 19:23:45.425990 CBT Training : PASS
4804 19:23:45.428503 Write leveling : PASS
4805 19:23:45.431804 RX DQS gating : PASS
4806 19:23:45.432373 RX DQ/DQS(RDDQC) : PASS
4807 19:23:45.435239 TX DQ/DQS : PASS
4808 19:23:45.438109 RX DATLAT : PASS
4809 19:23:45.438532 RX DQ/DQS(Engine): PASS
4810 19:23:45.441861 TX OE : NO K
4811 19:23:45.442376 All Pass.
4812 19:23:45.442707
4813 19:23:45.445281 CH 1, Rank 0
4814 19:23:45.445838 SW Impedance : PASS
4815 19:23:45.448732 DUTY Scan : NO K
4816 19:23:45.449249 ZQ Calibration : PASS
4817 19:23:45.452134 Jitter Meter : NO K
4818 19:23:45.455237 CBT Training : PASS
4819 19:23:45.455757 Write leveling : PASS
4820 19:23:45.458253 RX DQS gating : PASS
4821 19:23:45.462016 RX DQ/DQS(RDDQC) : PASS
4822 19:23:45.462534 TX DQ/DQS : PASS
4823 19:23:45.465439 RX DATLAT : PASS
4824 19:23:45.468505 RX DQ/DQS(Engine): PASS
4825 19:23:45.469020 TX OE : NO K
4826 19:23:45.471981 All Pass.
4827 19:23:45.472498
4828 19:23:45.472827 CH 1, Rank 1
4829 19:23:45.475375 SW Impedance : PASS
4830 19:23:45.475895 DUTY Scan : NO K
4831 19:23:45.477983 ZQ Calibration : PASS
4832 19:23:45.481635 Jitter Meter : NO K
4833 19:23:45.482050 CBT Training : PASS
4834 19:23:45.484978 Write leveling : PASS
4835 19:23:45.488480 RX DQS gating : PASS
4836 19:23:45.489023 RX DQ/DQS(RDDQC) : PASS
4837 19:23:45.491652 TX DQ/DQS : PASS
4838 19:23:45.494655 RX DATLAT : PASS
4839 19:23:45.495150 RX DQ/DQS(Engine): PASS
4840 19:23:45.498267 TX OE : NO K
4841 19:23:45.498682 All Pass.
4842 19:23:45.499085
4843 19:23:45.501490 DramC Write-DBI off
4844 19:23:45.501981 PER_BANK_REFRESH: Hybrid Mode
4845 19:23:45.504895 TX_TRACKING: ON
4846 19:23:45.515074 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4847 19:23:45.518323 [FAST_K] Save calibration result to emmc
4848 19:23:45.521260 dramc_set_vcore_voltage set vcore to 662500
4849 19:23:45.525056 Read voltage for 933, 3
4850 19:23:45.525686 Vio18 = 0
4851 19:23:45.526019 Vcore = 662500
4852 19:23:45.526325 Vdram = 0
4853 19:23:45.527944 Vddq = 0
4854 19:23:45.528355 Vmddr = 0
4855 19:23:45.534635 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4856 19:23:45.538266 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4857 19:23:45.541474 MEM_TYPE=3, freq_sel=17
4858 19:23:45.544883 sv_algorithm_assistance_LP4_1600
4859 19:23:45.548442 ============ PULL DRAM RESETB DOWN ============
4860 19:23:45.551869 ========== PULL DRAM RESETB DOWN end =========
4861 19:23:45.558254 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4862 19:23:45.561376 ===================================
4863 19:23:45.561893 LPDDR4 DRAM CONFIGURATION
4864 19:23:45.564935 ===================================
4865 19:23:45.568356 EX_ROW_EN[0] = 0x0
4866 19:23:45.571765 EX_ROW_EN[1] = 0x0
4867 19:23:45.572281 LP4Y_EN = 0x0
4868 19:23:45.574739 WORK_FSP = 0x0
4869 19:23:45.575256 WL = 0x3
4870 19:23:45.577968 RL = 0x3
4871 19:23:45.578485 BL = 0x2
4872 19:23:45.581171 RPST = 0x0
4873 19:23:45.581732 RD_PRE = 0x0
4874 19:23:45.584679 WR_PRE = 0x1
4875 19:23:45.585201 WR_PST = 0x0
4876 19:23:45.588257 DBI_WR = 0x0
4877 19:23:45.588779 DBI_RD = 0x0
4878 19:23:45.591216 OTF = 0x1
4879 19:23:45.594058 ===================================
4880 19:23:45.597984 ===================================
4881 19:23:45.598502 ANA top config
4882 19:23:45.600937 ===================================
4883 19:23:45.604624 DLL_ASYNC_EN = 0
4884 19:23:45.607959 ALL_SLAVE_EN = 1
4885 19:23:45.608511 NEW_RANK_MODE = 1
4886 19:23:45.611576 DLL_IDLE_MODE = 1
4887 19:23:45.614384 LP45_APHY_COMB_EN = 1
4888 19:23:45.617751 TX_ODT_DIS = 1
4889 19:23:45.621275 NEW_8X_MODE = 1
4890 19:23:45.624400 ===================================
4891 19:23:45.624916 ===================================
4892 19:23:45.627850 data_rate = 1866
4893 19:23:45.631482 CKR = 1
4894 19:23:45.634758 DQ_P2S_RATIO = 8
4895 19:23:45.638501 ===================================
4896 19:23:45.641904 CA_P2S_RATIO = 8
4897 19:23:45.644687 DQ_CA_OPEN = 0
4898 19:23:45.645204 DQ_SEMI_OPEN = 0
4899 19:23:45.647970 CA_SEMI_OPEN = 0
4900 19:23:45.651798 CA_FULL_RATE = 0
4901 19:23:45.654690 DQ_CKDIV4_EN = 1
4902 19:23:45.658258 CA_CKDIV4_EN = 1
4903 19:23:45.661882 CA_PREDIV_EN = 0
4904 19:23:45.662399 PH8_DLY = 0
4905 19:23:45.664571 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4906 19:23:45.668212 DQ_AAMCK_DIV = 4
4907 19:23:45.671570 CA_AAMCK_DIV = 4
4908 19:23:45.674562 CA_ADMCK_DIV = 4
4909 19:23:45.677893 DQ_TRACK_CA_EN = 0
4910 19:23:45.678414 CA_PICK = 933
4911 19:23:45.681282 CA_MCKIO = 933
4912 19:23:45.684641 MCKIO_SEMI = 0
4913 19:23:45.688280 PLL_FREQ = 3732
4914 19:23:45.691243 DQ_UI_PI_RATIO = 32
4915 19:23:45.694192 CA_UI_PI_RATIO = 0
4916 19:23:45.697664 ===================================
4917 19:23:45.701076 ===================================
4918 19:23:45.704373 memory_type:LPDDR4
4919 19:23:45.704885 GP_NUM : 10
4920 19:23:45.707591 SRAM_EN : 1
4921 19:23:45.708133 MD32_EN : 0
4922 19:23:45.711111 ===================================
4923 19:23:45.714212 [ANA_INIT] >>>>>>>>>>>>>>
4924 19:23:45.717675 <<<<<< [CONFIGURE PHASE]: ANA_TX
4925 19:23:45.721169 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4926 19:23:45.724331 ===================================
4927 19:23:45.727662 data_rate = 1866,PCW = 0X8f00
4928 19:23:45.731145 ===================================
4929 19:23:45.734375 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4930 19:23:45.737785 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4931 19:23:45.744618 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4932 19:23:45.747723 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4933 19:23:45.751071 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4934 19:23:45.757730 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4935 19:23:45.758261 [ANA_INIT] flow start
4936 19:23:45.761370 [ANA_INIT] PLL >>>>>>>>
4937 19:23:45.764688 [ANA_INIT] PLL <<<<<<<<
4938 19:23:45.765213 [ANA_INIT] MIDPI >>>>>>>>
4939 19:23:45.767617 [ANA_INIT] MIDPI <<<<<<<<
4940 19:23:45.770737 [ANA_INIT] DLL >>>>>>>>
4941 19:23:45.771215 [ANA_INIT] flow end
4942 19:23:45.774298 ============ LP4 DIFF to SE enter ============
4943 19:23:45.781128 ============ LP4 DIFF to SE exit ============
4944 19:23:45.781738 [ANA_INIT] <<<<<<<<<<<<<
4945 19:23:45.784601 [Flow] Enable top DCM control >>>>>
4946 19:23:45.787261 [Flow] Enable top DCM control <<<<<
4947 19:23:45.790702 Enable DLL master slave shuffle
4948 19:23:45.797725 ==============================================================
4949 19:23:45.798253 Gating Mode config
4950 19:23:45.803933 ==============================================================
4951 19:23:45.807588 Config description:
4952 19:23:45.817274 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4953 19:23:45.824044 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4954 19:23:45.827414 SELPH_MODE 0: By rank 1: By Phase
4955 19:23:45.833591 ==============================================================
4956 19:23:45.837746 GAT_TRACK_EN = 1
4957 19:23:45.840618 RX_GATING_MODE = 2
4958 19:23:45.841138 RX_GATING_TRACK_MODE = 2
4959 19:23:45.844023 SELPH_MODE = 1
4960 19:23:45.846970 PICG_EARLY_EN = 1
4961 19:23:45.850507 VALID_LAT_VALUE = 1
4962 19:23:45.857322 ==============================================================
4963 19:23:45.860511 Enter into Gating configuration >>>>
4964 19:23:45.864174 Exit from Gating configuration <<<<
4965 19:23:45.866965 Enter into DVFS_PRE_config >>>>>
4966 19:23:45.877176 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4967 19:23:45.880724 Exit from DVFS_PRE_config <<<<<
4968 19:23:45.883496 Enter into PICG configuration >>>>
4969 19:23:45.887219 Exit from PICG configuration <<<<
4970 19:23:45.890148 [RX_INPUT] configuration >>>>>
4971 19:23:45.893973 [RX_INPUT] configuration <<<<<
4972 19:23:45.897138 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4973 19:23:45.903786 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4974 19:23:45.910325 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4975 19:23:45.916784 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4976 19:23:45.920229 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4977 19:23:45.927068 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4978 19:23:45.929958 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4979 19:23:45.936582 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4980 19:23:45.940450 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4981 19:23:45.943599 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4982 19:23:45.946859 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4983 19:23:45.953345 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4984 19:23:45.956582 ===================================
4985 19:23:45.957049 LPDDR4 DRAM CONFIGURATION
4986 19:23:45.959619 ===================================
4987 19:23:45.963088 EX_ROW_EN[0] = 0x0
4988 19:23:45.966594 EX_ROW_EN[1] = 0x0
4989 19:23:45.967104 LP4Y_EN = 0x0
4990 19:23:45.969933 WORK_FSP = 0x0
4991 19:23:45.970446 WL = 0x3
4992 19:23:45.973124 RL = 0x3
4993 19:23:45.973583 BL = 0x2
4994 19:23:45.976811 RPST = 0x0
4995 19:23:45.977367 RD_PRE = 0x0
4996 19:23:45.980275 WR_PRE = 0x1
4997 19:23:45.980782 WR_PST = 0x0
4998 19:23:45.982895 DBI_WR = 0x0
4999 19:23:45.983347 DBI_RD = 0x0
5000 19:23:45.986621 OTF = 0x1
5001 19:23:45.990192 ===================================
5002 19:23:45.992981 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5003 19:23:45.996343 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5004 19:23:46.003564 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5005 19:23:46.006791 ===================================
5006 19:23:46.007301 LPDDR4 DRAM CONFIGURATION
5007 19:23:46.009962 ===================================
5008 19:23:46.013779 EX_ROW_EN[0] = 0x10
5009 19:23:46.016487 EX_ROW_EN[1] = 0x0
5010 19:23:46.016996 LP4Y_EN = 0x0
5011 19:23:46.019802 WORK_FSP = 0x0
5012 19:23:46.020309 WL = 0x3
5013 19:23:46.023581 RL = 0x3
5014 19:23:46.024090 BL = 0x2
5015 19:23:46.026175 RPST = 0x0
5016 19:23:46.026600 RD_PRE = 0x0
5017 19:23:46.029631 WR_PRE = 0x1
5018 19:23:46.030053 WR_PST = 0x0
5019 19:23:46.033104 DBI_WR = 0x0
5020 19:23:46.033601 DBI_RD = 0x0
5021 19:23:46.036112 OTF = 0x1
5022 19:23:46.039376 ===================================
5023 19:23:46.046496 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5024 19:23:46.049576 nWR fixed to 30
5025 19:23:46.050099 [ModeRegInit_LP4] CH0 RK0
5026 19:23:46.052863 [ModeRegInit_LP4] CH0 RK1
5027 19:23:46.056366 [ModeRegInit_LP4] CH1 RK0
5028 19:23:46.059601 [ModeRegInit_LP4] CH1 RK1
5029 19:23:46.060025 match AC timing 9
5030 19:23:46.062578 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5031 19:23:46.069355 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5032 19:23:46.073287 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5033 19:23:46.079364 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5034 19:23:46.083079 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5035 19:23:46.083633 ==
5036 19:23:46.086545 Dram Type= 6, Freq= 0, CH_0, rank 0
5037 19:23:46.089540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5038 19:23:46.090060 ==
5039 19:23:46.096300 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5040 19:23:46.102831 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5041 19:23:46.105854 [CA 0] Center 37 (7~68) winsize 62
5042 19:23:46.109665 [CA 1] Center 38 (7~69) winsize 63
5043 19:23:46.113396 [CA 2] Center 35 (5~66) winsize 62
5044 19:23:46.116040 [CA 3] Center 34 (4~65) winsize 62
5045 19:23:46.119257 [CA 4] Center 34 (4~64) winsize 61
5046 19:23:46.122679 [CA 5] Center 33 (3~64) winsize 62
5047 19:23:46.123242
5048 19:23:46.125797 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5049 19:23:46.126324
5050 19:23:46.129251 [CATrainingPosCal] consider 1 rank data
5051 19:23:46.132766 u2DelayCellTimex100 = 270/100 ps
5052 19:23:46.136311 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5053 19:23:46.139222 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5054 19:23:46.142559 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5055 19:23:46.145902 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5056 19:23:46.149090 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5057 19:23:46.152230 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5058 19:23:46.152720
5059 19:23:46.159105 CA PerBit enable=1, Macro0, CA PI delay=33
5060 19:23:46.159641
5061 19:23:46.159984 [CBTSetCACLKResult] CA Dly = 33
5062 19:23:46.162432 CS Dly: 6 (0~37)
5063 19:23:46.162858 ==
5064 19:23:46.165408 Dram Type= 6, Freq= 0, CH_0, rank 1
5065 19:23:46.169251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5066 19:23:46.169836 ==
5067 19:23:46.175558 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5068 19:23:46.182562 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5069 19:23:46.185767 [CA 0] Center 38 (8~69) winsize 62
5070 19:23:46.189421 [CA 1] Center 38 (8~69) winsize 62
5071 19:23:46.192469 [CA 2] Center 36 (6~66) winsize 61
5072 19:23:46.195979 [CA 3] Center 35 (5~66) winsize 62
5073 19:23:46.199129 [CA 4] Center 34 (4~65) winsize 62
5074 19:23:46.202507 [CA 5] Center 34 (4~64) winsize 61
5075 19:23:46.203066
5076 19:23:46.205830 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5077 19:23:46.206295
5078 19:23:46.209466 [CATrainingPosCal] consider 2 rank data
5079 19:23:46.212846 u2DelayCellTimex100 = 270/100 ps
5080 19:23:46.215999 CA0 delay=38 (8~68),Diff = 4 PI (24 cell)
5081 19:23:46.219092 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5082 19:23:46.222777 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5083 19:23:46.225866 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5084 19:23:46.229410 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5085 19:23:46.232611 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5086 19:23:46.233174
5087 19:23:46.239369 CA PerBit enable=1, Macro0, CA PI delay=34
5088 19:23:46.239791
5089 19:23:46.240122 [CBTSetCACLKResult] CA Dly = 34
5090 19:23:46.242504 CS Dly: 7 (0~39)
5091 19:23:46.243016
5092 19:23:46.245688 ----->DramcWriteLeveling(PI) begin...
5093 19:23:46.246113 ==
5094 19:23:46.249436 Dram Type= 6, Freq= 0, CH_0, rank 0
5095 19:23:46.252479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5096 19:23:46.253043 ==
5097 19:23:46.255616 Write leveling (Byte 0): 32 => 32
5098 19:23:46.258965 Write leveling (Byte 1): 29 => 29
5099 19:23:46.261959 DramcWriteLeveling(PI) end<-----
5100 19:23:46.262381
5101 19:23:46.262706 ==
5102 19:23:46.265264 Dram Type= 6, Freq= 0, CH_0, rank 0
5103 19:23:46.268848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5104 19:23:46.272304 ==
5105 19:23:46.272722 [Gating] SW mode calibration
5106 19:23:46.282613 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5107 19:23:46.285431 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5108 19:23:46.288834 0 14 0 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
5109 19:23:46.295249 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5110 19:23:46.298739 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5111 19:23:46.302273 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5112 19:23:46.308812 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5113 19:23:46.312253 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5114 19:23:46.315639 0 14 24 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
5115 19:23:46.321991 0 14 28 | B1->B0 | 3333 2424 | 1 0 | (1 0) (0 0)
5116 19:23:46.325484 0 15 0 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
5117 19:23:46.328885 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5118 19:23:46.335494 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5119 19:23:46.338718 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5120 19:23:46.341837 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5121 19:23:46.348594 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5122 19:23:46.352108 0 15 24 | B1->B0 | 2323 3232 | 0 0 | (0 0) (1 1)
5123 19:23:46.355401 0 15 28 | B1->B0 | 2424 4646 | 1 0 | (0 0) (0 0)
5124 19:23:46.361646 1 0 0 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5125 19:23:46.365334 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5126 19:23:46.368378 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5127 19:23:46.374930 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5128 19:23:46.378097 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5129 19:23:46.381757 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5130 19:23:46.388683 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5131 19:23:46.391408 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5132 19:23:46.394517 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5133 19:23:46.401692 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 19:23:46.404806 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 19:23:46.408393 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 19:23:46.414736 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 19:23:46.418143 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 19:23:46.421268 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 19:23:46.428167 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 19:23:46.430982 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 19:23:46.434363 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 19:23:46.441352 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 19:23:46.444223 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 19:23:46.447732 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 19:23:46.454183 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 19:23:46.457755 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5147 19:23:46.460816 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5148 19:23:46.464162 Total UI for P1: 0, mck2ui 16
5149 19:23:46.467656 best dqsien dly found for B0: ( 1, 2, 24)
5150 19:23:46.474213 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5151 19:23:46.474864 Total UI for P1: 0, mck2ui 16
5152 19:23:46.477342 best dqsien dly found for B1: ( 1, 2, 28)
5153 19:23:46.483862 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5154 19:23:46.486901 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5155 19:23:46.487357
5156 19:23:46.490547 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5157 19:23:46.493587 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5158 19:23:46.497021 [Gating] SW calibration Done
5159 19:23:46.497613 ==
5160 19:23:46.500353 Dram Type= 6, Freq= 0, CH_0, rank 0
5161 19:23:46.504091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5162 19:23:46.504649 ==
5163 19:23:46.506916 RX Vref Scan: 0
5164 19:23:46.507506
5165 19:23:46.507914 RX Vref 0 -> 0, step: 1
5166 19:23:46.508256
5167 19:23:46.510351 RX Delay -80 -> 252, step: 8
5168 19:23:46.513372 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5169 19:23:46.520227 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5170 19:23:46.523834 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5171 19:23:46.526912 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5172 19:23:46.530155 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5173 19:23:46.533709 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5174 19:23:46.536655 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5175 19:23:46.543680 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5176 19:23:46.546818 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5177 19:23:46.550260 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5178 19:23:46.553629 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5179 19:23:46.556400 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5180 19:23:46.563276 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5181 19:23:46.566281 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5182 19:23:46.569918 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5183 19:23:46.573411 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5184 19:23:46.573931 ==
5185 19:23:46.576393 Dram Type= 6, Freq= 0, CH_0, rank 0
5186 19:23:46.579815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5187 19:23:46.580236 ==
5188 19:23:46.583202 DQS Delay:
5189 19:23:46.583708 DQS0 = 0, DQS1 = 0
5190 19:23:46.586257 DQM Delay:
5191 19:23:46.586673 DQM0 = 105, DQM1 = 90
5192 19:23:46.587001 DQ Delay:
5193 19:23:46.592559 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5194 19:23:46.596127 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5195 19:23:46.599160 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5196 19:23:46.602839 DQ12 =91, DQ13 =91, DQ14 =99, DQ15 =99
5197 19:23:46.603254
5198 19:23:46.603580
5199 19:23:46.603882 ==
5200 19:23:46.606096 Dram Type= 6, Freq= 0, CH_0, rank 0
5201 19:23:46.609155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5202 19:23:46.609600 ==
5203 19:23:46.609930
5204 19:23:46.610238
5205 19:23:46.612656 TX Vref Scan disable
5206 19:23:46.613069 == TX Byte 0 ==
5207 19:23:46.619728 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5208 19:23:46.622956 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5209 19:23:46.623477 == TX Byte 1 ==
5210 19:23:46.629447 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5211 19:23:46.632873 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5212 19:23:46.633467 ==
5213 19:23:46.636017 Dram Type= 6, Freq= 0, CH_0, rank 0
5214 19:23:46.639493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5215 19:23:46.640059 ==
5216 19:23:46.640426
5217 19:23:46.640758
5218 19:23:46.642791 TX Vref Scan disable
5219 19:23:46.646215 == TX Byte 0 ==
5220 19:23:46.649548 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5221 19:23:46.652829 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5222 19:23:46.656248 == TX Byte 1 ==
5223 19:23:46.659821 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5224 19:23:46.663006 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5225 19:23:46.663582
5226 19:23:46.666083 [DATLAT]
5227 19:23:46.666639 Freq=933, CH0 RK0
5228 19:23:46.667003
5229 19:23:46.669330 DATLAT Default: 0xd
5230 19:23:46.669894 0, 0xFFFF, sum = 0
5231 19:23:46.672884 1, 0xFFFF, sum = 0
5232 19:23:46.673480 2, 0xFFFF, sum = 0
5233 19:23:46.676460 3, 0xFFFF, sum = 0
5234 19:23:46.677071 4, 0xFFFF, sum = 0
5235 19:23:46.679194 5, 0xFFFF, sum = 0
5236 19:23:46.679758 6, 0xFFFF, sum = 0
5237 19:23:46.682513 7, 0xFFFF, sum = 0
5238 19:23:46.682980 8, 0xFFFF, sum = 0
5239 19:23:46.686593 9, 0xFFFF, sum = 0
5240 19:23:46.687159 10, 0x0, sum = 1
5241 19:23:46.689483 11, 0x0, sum = 2
5242 19:23:46.690043 12, 0x0, sum = 3
5243 19:23:46.692634 13, 0x0, sum = 4
5244 19:23:46.693198 best_step = 11
5245 19:23:46.693603
5246 19:23:46.693941 ==
5247 19:23:46.696033 Dram Type= 6, Freq= 0, CH_0, rank 0
5248 19:23:46.699577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5249 19:23:46.702561 ==
5250 19:23:46.703020 RX Vref Scan: 1
5251 19:23:46.703469
5252 19:23:46.706110 RX Vref 0 -> 0, step: 1
5253 19:23:46.706566
5254 19:23:46.709477 RX Delay -53 -> 252, step: 4
5255 19:23:46.709936
5256 19:23:46.712660 Set Vref, RX VrefLevel [Byte0]: 60
5257 19:23:46.716360 [Byte1]: 48
5258 19:23:46.716916
5259 19:23:46.719163 Final RX Vref Byte 0 = 60 to rank0
5260 19:23:46.722424 Final RX Vref Byte 1 = 48 to rank0
5261 19:23:46.725973 Final RX Vref Byte 0 = 60 to rank1
5262 19:23:46.729358 Final RX Vref Byte 1 = 48 to rank1==
5263 19:23:46.732649 Dram Type= 6, Freq= 0, CH_0, rank 0
5264 19:23:46.735960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5265 19:23:46.736580 ==
5266 19:23:46.739113 DQS Delay:
5267 19:23:46.739568 DQS0 = 0, DQS1 = 0
5268 19:23:46.739929 DQM Delay:
5269 19:23:46.742701 DQM0 = 107, DQM1 = 92
5270 19:23:46.743257 DQ Delay:
5271 19:23:46.746194 DQ0 =106, DQ1 =106, DQ2 =102, DQ3 =106
5272 19:23:46.749464 DQ4 =106, DQ5 =98, DQ6 =120, DQ7 =114
5273 19:23:46.752488 DQ8 =86, DQ9 =76, DQ10 =92, DQ11 =92
5274 19:23:46.755794 DQ12 =96, DQ13 =94, DQ14 =104, DQ15 =100
5275 19:23:46.756356
5276 19:23:46.756721
5277 19:23:46.766086 [DQSOSCAuto] RK0, (LSB)MR18= 0x211d, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 411 ps
5278 19:23:46.769518 CH0 RK0: MR19=505, MR18=211D
5279 19:23:46.776177 CH0_RK0: MR19=0x505, MR18=0x211D, DQSOSC=411, MR23=63, INC=64, DEC=42
5280 19:23:46.776739
5281 19:23:46.779356 ----->DramcWriteLeveling(PI) begin...
5282 19:23:46.779820 ==
5283 19:23:46.782564 Dram Type= 6, Freq= 0, CH_0, rank 1
5284 19:23:46.786038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5285 19:23:46.786601 ==
5286 19:23:46.789630 Write leveling (Byte 0): 32 => 32
5287 19:23:46.792733 Write leveling (Byte 1): 29 => 29
5288 19:23:46.795751 DramcWriteLeveling(PI) end<-----
5289 19:23:46.796213
5290 19:23:46.796576 ==
5291 19:23:46.799179 Dram Type= 6, Freq= 0, CH_0, rank 1
5292 19:23:46.802440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5293 19:23:46.802891 ==
5294 19:23:46.806009 [Gating] SW mode calibration
5295 19:23:46.812482 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5296 19:23:46.818914 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5297 19:23:46.822370 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5298 19:23:46.825833 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5299 19:23:46.832154 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5300 19:23:46.835657 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5301 19:23:46.838827 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5302 19:23:46.845868 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5303 19:23:46.849362 0 14 24 | B1->B0 | 3434 2f2f | 1 1 | (0 0) (1 1)
5304 19:23:46.852185 0 14 28 | B1->B0 | 2f2f 2626 | 0 0 | (0 1) (0 1)
5305 19:23:46.859356 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5306 19:23:46.862384 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5307 19:23:46.865940 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5308 19:23:46.872515 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5309 19:23:46.875796 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5310 19:23:46.878837 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5311 19:23:46.885659 0 15 24 | B1->B0 | 2928 2a2a | 1 0 | (0 0) (0 0)
5312 19:23:46.888986 0 15 28 | B1->B0 | 3c3c 4343 | 0 0 | (0 0) (1 1)
5313 19:23:46.892356 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5314 19:23:46.895477 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5315 19:23:46.902169 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5316 19:23:46.905341 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5317 19:23:46.909037 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5318 19:23:46.915397 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5319 19:23:46.918921 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5320 19:23:46.922062 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5321 19:23:46.928796 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 19:23:46.932172 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 19:23:46.935361 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 19:23:46.941564 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 19:23:46.945413 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 19:23:46.948696 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 19:23:46.955540 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 19:23:46.958316 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 19:23:46.962000 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 19:23:46.968379 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 19:23:46.971845 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 19:23:46.975237 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 19:23:46.981716 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 19:23:46.985332 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 19:23:46.988851 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 19:23:46.995677 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5337 19:23:46.998331 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5338 19:23:47.002122 Total UI for P1: 0, mck2ui 16
5339 19:23:47.005600 best dqsien dly found for B0: ( 1, 2, 28)
5340 19:23:47.008471 Total UI for P1: 0, mck2ui 16
5341 19:23:47.011914 best dqsien dly found for B1: ( 1, 2, 28)
5342 19:23:47.015215 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5343 19:23:47.018194 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5344 19:23:47.018663
5345 19:23:47.021818 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5346 19:23:47.025010 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5347 19:23:47.028423 [Gating] SW calibration Done
5348 19:23:47.028889 ==
5349 19:23:47.031250 Dram Type= 6, Freq= 0, CH_0, rank 1
5350 19:23:47.034898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5351 19:23:47.035366 ==
5352 19:23:47.038145 RX Vref Scan: 0
5353 19:23:47.038610
5354 19:23:47.041379 RX Vref 0 -> 0, step: 1
5355 19:23:47.041863
5356 19:23:47.042229 RX Delay -80 -> 252, step: 8
5357 19:23:47.048171 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5358 19:23:47.051505 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5359 19:23:47.054784 iDelay=208, Bit 2, Center 103 (16 ~ 191) 176
5360 19:23:47.058451 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5361 19:23:47.061764 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5362 19:23:47.067914 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5363 19:23:47.071823 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5364 19:23:47.074539 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5365 19:23:47.078230 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5366 19:23:47.081225 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5367 19:23:47.084915 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5368 19:23:47.091947 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5369 19:23:47.094724 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5370 19:23:47.098240 iDelay=208, Bit 13, Center 95 (8 ~ 183) 176
5371 19:23:47.101703 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5372 19:23:47.104832 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5373 19:23:47.105454 ==
5374 19:23:47.108419 Dram Type= 6, Freq= 0, CH_0, rank 1
5375 19:23:47.115318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5376 19:23:47.115891 ==
5377 19:23:47.116261 DQS Delay:
5378 19:23:47.117998 DQS0 = 0, DQS1 = 0
5379 19:23:47.118477 DQM Delay:
5380 19:23:47.118846 DQM0 = 106, DQM1 = 91
5381 19:23:47.121363 DQ Delay:
5382 19:23:47.124575 DQ0 =107, DQ1 =107, DQ2 =103, DQ3 =99
5383 19:23:47.128209 DQ4 =107, DQ5 =99, DQ6 =115, DQ7 =111
5384 19:23:47.131348 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =91
5385 19:23:47.134736 DQ12 =95, DQ13 =95, DQ14 =103, DQ15 =95
5386 19:23:47.135307
5387 19:23:47.135676
5388 19:23:47.136017 ==
5389 19:23:47.137897 Dram Type= 6, Freq= 0, CH_0, rank 1
5390 19:23:47.141461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5391 19:23:47.141932 ==
5392 19:23:47.142383
5393 19:23:47.142735
5394 19:23:47.144735 TX Vref Scan disable
5395 19:23:47.148392 == TX Byte 0 ==
5396 19:23:47.151486 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5397 19:23:47.154661 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5398 19:23:47.157798 == TX Byte 1 ==
5399 19:23:47.161461 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5400 19:23:47.164837 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5401 19:23:47.165406 ==
5402 19:23:47.168042 Dram Type= 6, Freq= 0, CH_0, rank 1
5403 19:23:47.171728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5404 19:23:47.174665 ==
5405 19:23:47.175093
5406 19:23:47.175428
5407 19:23:47.175735 TX Vref Scan disable
5408 19:23:47.178251 == TX Byte 0 ==
5409 19:23:47.181732 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5410 19:23:47.188355 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5411 19:23:47.188884 == TX Byte 1 ==
5412 19:23:47.191573 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5413 19:23:47.198170 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5414 19:23:47.198699
5415 19:23:47.199037 [DATLAT]
5416 19:23:47.199348 Freq=933, CH0 RK1
5417 19:23:47.199649
5418 19:23:47.201887 DATLAT Default: 0xb
5419 19:23:47.202416 0, 0xFFFF, sum = 0
5420 19:23:47.204665 1, 0xFFFF, sum = 0
5421 19:23:47.205092 2, 0xFFFF, sum = 0
5422 19:23:47.208320 3, 0xFFFF, sum = 0
5423 19:23:47.211395 4, 0xFFFF, sum = 0
5424 19:23:47.211826 5, 0xFFFF, sum = 0
5425 19:23:47.215318 6, 0xFFFF, sum = 0
5426 19:23:47.215856 7, 0xFFFF, sum = 0
5427 19:23:47.218189 8, 0xFFFF, sum = 0
5428 19:23:47.218624 9, 0xFFFF, sum = 0
5429 19:23:47.221103 10, 0x0, sum = 1
5430 19:23:47.221579 11, 0x0, sum = 2
5431 19:23:47.224458 12, 0x0, sum = 3
5432 19:23:47.224887 13, 0x0, sum = 4
5433 19:23:47.225227 best_step = 11
5434 19:23:47.225591
5435 19:23:47.227846 ==
5436 19:23:47.228265 Dram Type= 6, Freq= 0, CH_0, rank 1
5437 19:23:47.234731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5438 19:23:47.235162 ==
5439 19:23:47.235498 RX Vref Scan: 0
5440 19:23:47.235825
5441 19:23:47.237884 RX Vref 0 -> 0, step: 1
5442 19:23:47.238309
5443 19:23:47.241407 RX Delay -53 -> 252, step: 4
5444 19:23:47.244470 iDelay=203, Bit 0, Center 104 (19 ~ 190) 172
5445 19:23:47.250840 iDelay=203, Bit 1, Center 106 (19 ~ 194) 176
5446 19:23:47.254278 iDelay=203, Bit 2, Center 102 (15 ~ 190) 176
5447 19:23:47.257358 iDelay=203, Bit 3, Center 98 (15 ~ 182) 168
5448 19:23:47.260941 iDelay=203, Bit 4, Center 106 (23 ~ 190) 168
5449 19:23:47.264296 iDelay=203, Bit 5, Center 96 (11 ~ 182) 172
5450 19:23:47.270919 iDelay=203, Bit 6, Center 114 (27 ~ 202) 176
5451 19:23:47.274024 iDelay=203, Bit 7, Center 112 (27 ~ 198) 172
5452 19:23:47.277187 iDelay=203, Bit 8, Center 84 (-1 ~ 170) 172
5453 19:23:47.280657 iDelay=203, Bit 9, Center 80 (-1 ~ 162) 164
5454 19:23:47.283851 iDelay=203, Bit 10, Center 92 (7 ~ 178) 172
5455 19:23:47.287443 iDelay=203, Bit 11, Center 92 (11 ~ 174) 164
5456 19:23:47.294226 iDelay=203, Bit 12, Center 96 (11 ~ 182) 172
5457 19:23:47.297116 iDelay=203, Bit 13, Center 94 (11 ~ 178) 168
5458 19:23:47.300510 iDelay=203, Bit 14, Center 102 (19 ~ 186) 168
5459 19:23:47.304130 iDelay=203, Bit 15, Center 100 (19 ~ 182) 164
5460 19:23:47.304290 ==
5461 19:23:47.307400 Dram Type= 6, Freq= 0, CH_0, rank 1
5462 19:23:47.314165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5463 19:23:47.314258 ==
5464 19:23:47.314331 DQS Delay:
5465 19:23:47.317146 DQS0 = 0, DQS1 = 0
5466 19:23:47.317237 DQM Delay:
5467 19:23:47.317315 DQM0 = 104, DQM1 = 92
5468 19:23:47.320549 DQ Delay:
5469 19:23:47.324064 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =98
5470 19:23:47.327006 DQ4 =106, DQ5 =96, DQ6 =114, DQ7 =112
5471 19:23:47.330375 DQ8 =84, DQ9 =80, DQ10 =92, DQ11 =92
5472 19:23:47.333772 DQ12 =96, DQ13 =94, DQ14 =102, DQ15 =100
5473 19:23:47.333882
5474 19:23:47.333967
5475 19:23:47.340757 [DQSOSCAuto] RK1, (LSB)MR18= 0x2909, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 408 ps
5476 19:23:47.343789 CH0 RK1: MR19=505, MR18=2909
5477 19:23:47.350592 CH0_RK1: MR19=0x505, MR18=0x2909, DQSOSC=408, MR23=63, INC=65, DEC=43
5478 19:23:47.353840 [RxdqsGatingPostProcess] freq 933
5479 19:23:47.360224 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5480 19:23:47.360356 best DQS0 dly(2T, 0.5T) = (0, 10)
5481 19:23:47.363798 best DQS1 dly(2T, 0.5T) = (0, 10)
5482 19:23:47.367305 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5483 19:23:47.370227 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5484 19:23:47.373591 best DQS0 dly(2T, 0.5T) = (0, 10)
5485 19:23:47.377013 best DQS1 dly(2T, 0.5T) = (0, 10)
5486 19:23:47.380513 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5487 19:23:47.383921 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5488 19:23:47.387224 Pre-setting of DQS Precalculation
5489 19:23:47.393562 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5490 19:23:47.393700 ==
5491 19:23:47.397140 Dram Type= 6, Freq= 0, CH_1, rank 0
5492 19:23:47.400676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5493 19:23:47.400773 ==
5494 19:23:47.407068 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5495 19:23:47.410147 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5496 19:23:47.413906 [CA 0] Center 37 (7~67) winsize 61
5497 19:23:47.417334 [CA 1] Center 37 (6~68) winsize 63
5498 19:23:47.421120 [CA 2] Center 35 (5~65) winsize 61
5499 19:23:47.424384 [CA 3] Center 34 (4~65) winsize 62
5500 19:23:47.427496 [CA 4] Center 34 (4~65) winsize 62
5501 19:23:47.430959 [CA 5] Center 34 (4~64) winsize 61
5502 19:23:47.431291
5503 19:23:47.434322 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5504 19:23:47.434652
5505 19:23:47.437906 [CATrainingPosCal] consider 1 rank data
5506 19:23:47.440632 u2DelayCellTimex100 = 270/100 ps
5507 19:23:47.444476 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5508 19:23:47.450689 CA1 delay=37 (6~68),Diff = 3 PI (18 cell)
5509 19:23:47.454130 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5510 19:23:47.457358 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5511 19:23:47.460779 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5512 19:23:47.463828 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5513 19:23:47.464379
5514 19:23:47.467308 CA PerBit enable=1, Macro0, CA PI delay=34
5515 19:23:47.467840
5516 19:23:47.470756 [CBTSetCACLKResult] CA Dly = 34
5517 19:23:47.471306 CS Dly: 5 (0~36)
5518 19:23:47.474081 ==
5519 19:23:47.477211 Dram Type= 6, Freq= 0, CH_1, rank 1
5520 19:23:47.480527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5521 19:23:47.481071 ==
5522 19:23:47.484125 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5523 19:23:47.490606 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5524 19:23:47.493995 [CA 0] Center 37 (7~68) winsize 62
5525 19:23:47.497285 [CA 1] Center 37 (7~68) winsize 62
5526 19:23:47.500727 [CA 2] Center 35 (5~66) winsize 62
5527 19:23:47.504156 [CA 3] Center 35 (5~65) winsize 61
5528 19:23:47.507521 [CA 4] Center 35 (5~65) winsize 61
5529 19:23:47.510616 [CA 5] Center 34 (4~64) winsize 61
5530 19:23:47.510781
5531 19:23:47.514057 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5532 19:23:47.514244
5533 19:23:47.517543 [CATrainingPosCal] consider 2 rank data
5534 19:23:47.520993 u2DelayCellTimex100 = 270/100 ps
5535 19:23:47.523864 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5536 19:23:47.527402 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5537 19:23:47.534322 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5538 19:23:47.537599 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5539 19:23:47.540636 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5540 19:23:47.543969 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5541 19:23:47.544053
5542 19:23:47.547368 CA PerBit enable=1, Macro0, CA PI delay=34
5543 19:23:47.547477
5544 19:23:47.551029 [CBTSetCACLKResult] CA Dly = 34
5545 19:23:47.551132 CS Dly: 6 (0~38)
5546 19:23:47.551223
5547 19:23:47.553814 ----->DramcWriteLeveling(PI) begin...
5548 19:23:47.557382 ==
5549 19:23:47.561142 Dram Type= 6, Freq= 0, CH_1, rank 0
5550 19:23:47.564246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5551 19:23:47.564831 ==
5552 19:23:47.567574 Write leveling (Byte 0): 26 => 26
5553 19:23:47.570643 Write leveling (Byte 1): 28 => 28
5554 19:23:47.574495 DramcWriteLeveling(PI) end<-----
5555 19:23:47.575031
5556 19:23:47.575521 ==
5557 19:23:47.577672 Dram Type= 6, Freq= 0, CH_1, rank 0
5558 19:23:47.581008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5559 19:23:47.581555 ==
5560 19:23:47.584309 [Gating] SW mode calibration
5561 19:23:47.591358 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5562 19:23:47.594363 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5563 19:23:47.601157 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5564 19:23:47.604594 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5565 19:23:47.607998 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5566 19:23:47.613943 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5567 19:23:47.617355 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5568 19:23:47.621068 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5569 19:23:47.627366 0 14 24 | B1->B0 | 3131 3333 | 1 1 | (1 0) (1 0)
5570 19:23:47.630869 0 14 28 | B1->B0 | 2727 2323 | 1 0 | (1 0) (0 0)
5571 19:23:47.634223 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5572 19:23:47.640853 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5573 19:23:47.643739 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5574 19:23:47.647074 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5575 19:23:47.653904 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5576 19:23:47.657101 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5577 19:23:47.660177 0 15 24 | B1->B0 | 2b2b 2f2e | 0 1 | (0 0) (0 0)
5578 19:23:47.666835 0 15 28 | B1->B0 | 3939 3f3f | 0 0 | (0 0) (0 0)
5579 19:23:47.670092 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5580 19:23:47.673591 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5581 19:23:47.680362 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5582 19:23:47.683500 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5583 19:23:47.686993 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5584 19:23:47.693527 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5585 19:23:47.696883 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5586 19:23:47.700201 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 19:23:47.707172 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 19:23:47.710283 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 19:23:47.713305 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 19:23:47.720145 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 19:23:47.723431 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 19:23:47.726897 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 19:23:47.733210 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 19:23:47.736682 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 19:23:47.740057 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 19:23:47.743562 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 19:23:47.750471 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 19:23:47.754126 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 19:23:47.756903 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 19:23:47.764055 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5601 19:23:47.767043 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5602 19:23:47.770395 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5603 19:23:47.773805 Total UI for P1: 0, mck2ui 16
5604 19:23:47.776957 best dqsien dly found for B0: ( 1, 2, 22)
5605 19:23:47.783627 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5606 19:23:47.784016 Total UI for P1: 0, mck2ui 16
5607 19:23:47.790631 best dqsien dly found for B1: ( 1, 2, 26)
5608 19:23:47.793550 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5609 19:23:47.796645 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5610 19:23:47.797133
5611 19:23:47.800005 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5612 19:23:47.803595 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5613 19:23:47.806573 [Gating] SW calibration Done
5614 19:23:47.807038 ==
5615 19:23:47.810466 Dram Type= 6, Freq= 0, CH_1, rank 0
5616 19:23:47.813686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5617 19:23:47.814149 ==
5618 19:23:47.817101 RX Vref Scan: 0
5619 19:23:47.817605
5620 19:23:47.817976 RX Vref 0 -> 0, step: 1
5621 19:23:47.818318
5622 19:23:47.820097 RX Delay -80 -> 252, step: 8
5623 19:23:47.827158 iDelay=208, Bit 0, Center 107 (24 ~ 191) 168
5624 19:23:47.830026 iDelay=208, Bit 1, Center 99 (16 ~ 183) 168
5625 19:23:47.833746 iDelay=208, Bit 2, Center 99 (16 ~ 183) 168
5626 19:23:47.837181 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5627 19:23:47.840030 iDelay=208, Bit 4, Center 103 (16 ~ 191) 176
5628 19:23:47.843531 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5629 19:23:47.850294 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5630 19:23:47.853823 iDelay=208, Bit 7, Center 103 (16 ~ 191) 176
5631 19:23:47.857186 iDelay=208, Bit 8, Center 91 (0 ~ 183) 184
5632 19:23:47.860768 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5633 19:23:47.863385 iDelay=208, Bit 10, Center 103 (16 ~ 191) 176
5634 19:23:47.867215 iDelay=208, Bit 11, Center 95 (8 ~ 183) 176
5635 19:23:47.873633 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5636 19:23:47.876896 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5637 19:23:47.880272 iDelay=208, Bit 14, Center 107 (16 ~ 199) 184
5638 19:23:47.883706 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5639 19:23:47.884219 ==
5640 19:23:47.886799 Dram Type= 6, Freq= 0, CH_1, rank 0
5641 19:23:47.893423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5642 19:23:47.893997 ==
5643 19:23:47.894364 DQS Delay:
5644 19:23:47.896567 DQS0 = 0, DQS1 = 0
5645 19:23:47.897026 DQM Delay:
5646 19:23:47.899996 DQM0 = 105, DQM1 = 100
5647 19:23:47.900595 DQ Delay:
5648 19:23:47.903440 DQ0 =107, DQ1 =99, DQ2 =99, DQ3 =103
5649 19:23:47.906826 DQ4 =103, DQ5 =111, DQ6 =115, DQ7 =103
5650 19:23:47.910140 DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =95
5651 19:23:47.913253 DQ12 =107, DQ13 =107, DQ14 =107, DQ15 =103
5652 19:23:47.913787
5653 19:23:47.914158
5654 19:23:47.914498 ==
5655 19:23:47.916648 Dram Type= 6, Freq= 0, CH_1, rank 0
5656 19:23:47.920267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5657 19:23:47.923685 ==
5658 19:23:47.924252
5659 19:23:47.924620
5660 19:23:47.924960 TX Vref Scan disable
5661 19:23:47.926307 == TX Byte 0 ==
5662 19:23:47.930046 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5663 19:23:47.933280 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5664 19:23:47.936733 == TX Byte 1 ==
5665 19:23:47.939967 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5666 19:23:47.943580 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5667 19:23:47.944148 ==
5668 19:23:47.946593 Dram Type= 6, Freq= 0, CH_1, rank 0
5669 19:23:47.953462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5670 19:23:47.954037 ==
5671 19:23:47.954406
5672 19:23:47.954743
5673 19:23:47.955066 TX Vref Scan disable
5674 19:23:47.957796 == TX Byte 0 ==
5675 19:23:47.960799 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5676 19:23:47.967730 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5677 19:23:47.968294 == TX Byte 1 ==
5678 19:23:47.971138 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5679 19:23:47.977335 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5680 19:23:47.977909
5681 19:23:47.978273 [DATLAT]
5682 19:23:47.978612 Freq=933, CH1 RK0
5683 19:23:47.978943
5684 19:23:47.981053 DATLAT Default: 0xd
5685 19:23:47.981665 0, 0xFFFF, sum = 0
5686 19:23:47.983832 1, 0xFFFF, sum = 0
5687 19:23:47.984299 2, 0xFFFF, sum = 0
5688 19:23:47.986990 3, 0xFFFF, sum = 0
5689 19:23:47.990632 4, 0xFFFF, sum = 0
5690 19:23:47.991104 5, 0xFFFF, sum = 0
5691 19:23:47.994057 6, 0xFFFF, sum = 0
5692 19:23:47.994688 7, 0xFFFF, sum = 0
5693 19:23:47.996925 8, 0xFFFF, sum = 0
5694 19:23:47.997428 9, 0xFFFF, sum = 0
5695 19:23:48.000488 10, 0x0, sum = 1
5696 19:23:48.000961 11, 0x0, sum = 2
5697 19:23:48.003885 12, 0x0, sum = 3
5698 19:23:48.004460 13, 0x0, sum = 4
5699 19:23:48.004836 best_step = 11
5700 19:23:48.005178
5701 19:23:48.007364 ==
5702 19:23:48.010405 Dram Type= 6, Freq= 0, CH_1, rank 0
5703 19:23:48.013888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5704 19:23:48.014426 ==
5705 19:23:48.014802 RX Vref Scan: 1
5706 19:23:48.015146
5707 19:23:48.016944 RX Vref 0 -> 0, step: 1
5708 19:23:48.017457
5709 19:23:48.020382 RX Delay -45 -> 252, step: 4
5710 19:23:48.020846
5711 19:23:48.023792 Set Vref, RX VrefLevel [Byte0]: 51
5712 19:23:48.027201 [Byte1]: 52
5713 19:23:48.027775
5714 19:23:48.030747 Final RX Vref Byte 0 = 51 to rank0
5715 19:23:48.033748 Final RX Vref Byte 1 = 52 to rank0
5716 19:23:48.037213 Final RX Vref Byte 0 = 51 to rank1
5717 19:23:48.040269 Final RX Vref Byte 1 = 52 to rank1==
5718 19:23:48.043621 Dram Type= 6, Freq= 0, CH_1, rank 0
5719 19:23:48.047064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5720 19:23:48.047530 ==
5721 19:23:48.050291 DQS Delay:
5722 19:23:48.050782 DQS0 = 0, DQS1 = 0
5723 19:23:48.053454 DQM Delay:
5724 19:23:48.053937 DQM0 = 108, DQM1 = 101
5725 19:23:48.056881 DQ Delay:
5726 19:23:48.060361 DQ0 =112, DQ1 =102, DQ2 =100, DQ3 =108
5727 19:23:48.063796 DQ4 =108, DQ5 =116, DQ6 =118, DQ7 =104
5728 19:23:48.066661 DQ8 =94, DQ9 =90, DQ10 =104, DQ11 =94
5729 19:23:48.069988 DQ12 =110, DQ13 =104, DQ14 =108, DQ15 =106
5730 19:23:48.070421
5731 19:23:48.070787
5732 19:23:48.076899 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b34, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 413 ps
5733 19:23:48.080658 CH1 RK0: MR19=505, MR18=1B34
5734 19:23:48.086768 CH1_RK0: MR19=0x505, MR18=0x1B34, DQSOSC=405, MR23=63, INC=66, DEC=44
5735 19:23:48.087186
5736 19:23:48.089979 ----->DramcWriteLeveling(PI) begin...
5737 19:23:48.090418 ==
5738 19:23:48.093746 Dram Type= 6, Freq= 0, CH_1, rank 1
5739 19:23:48.096769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5740 19:23:48.097208 ==
5741 19:23:48.099891 Write leveling (Byte 0): 29 => 29
5742 19:23:48.103659 Write leveling (Byte 1): 28 => 28
5743 19:23:48.106493 DramcWriteLeveling(PI) end<-----
5744 19:23:48.106959
5745 19:23:48.107296 ==
5746 19:23:48.110357 Dram Type= 6, Freq= 0, CH_1, rank 1
5747 19:23:48.113343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5748 19:23:48.116844 ==
5749 19:23:48.117270 [Gating] SW mode calibration
5750 19:23:48.123285 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5751 19:23:48.130047 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5752 19:23:48.133553 0 14 0 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
5753 19:23:48.139811 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5754 19:23:48.143319 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5755 19:23:48.146725 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5756 19:23:48.153507 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5757 19:23:48.156533 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5758 19:23:48.159640 0 14 24 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 0)
5759 19:23:48.166174 0 14 28 | B1->B0 | 2626 2d2d | 0 0 | (0 0) (1 0)
5760 19:23:48.169548 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5761 19:23:48.173080 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5762 19:23:48.179630 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5763 19:23:48.182520 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5764 19:23:48.186162 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5765 19:23:48.192551 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5766 19:23:48.196200 0 15 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5767 19:23:48.199648 0 15 28 | B1->B0 | 4141 3333 | 0 0 | (0 0) (0 0)
5768 19:23:48.206259 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5769 19:23:48.209242 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5770 19:23:48.212652 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5771 19:23:48.219327 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5772 19:23:48.222721 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5773 19:23:48.226169 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5774 19:23:48.229325 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5775 19:23:48.235952 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5776 19:23:48.239302 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 19:23:48.242705 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 19:23:48.249500 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 19:23:48.253009 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 19:23:48.256180 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 19:23:48.263059 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 19:23:48.266252 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 19:23:48.269754 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 19:23:48.275907 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 19:23:48.279359 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 19:23:48.282567 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 19:23:48.289534 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 19:23:48.292331 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 19:23:48.296081 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 19:23:48.302637 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5791 19:23:48.303107 Total UI for P1: 0, mck2ui 16
5792 19:23:48.309259 best dqsien dly found for B1: ( 1, 2, 22)
5793 19:23:48.312360 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5794 19:23:48.315953 Total UI for P1: 0, mck2ui 16
5795 19:23:48.318921 best dqsien dly found for B0: ( 1, 2, 24)
5796 19:23:48.322423 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5797 19:23:48.325951 best DQS1 dly(MCK, UI, PI) = (1, 2, 22)
5798 19:23:48.326587
5799 19:23:48.328765 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5800 19:23:48.332397 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 22)
5801 19:23:48.336082 [Gating] SW calibration Done
5802 19:23:48.336647 ==
5803 19:23:48.338926 Dram Type= 6, Freq= 0, CH_1, rank 1
5804 19:23:48.342469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5805 19:23:48.345701 ==
5806 19:23:48.346168 RX Vref Scan: 0
5807 19:23:48.346536
5808 19:23:48.348837 RX Vref 0 -> 0, step: 1
5809 19:23:48.349243
5810 19:23:48.352511 RX Delay -80 -> 252, step: 8
5811 19:23:48.356095 iDelay=200, Bit 0, Center 107 (24 ~ 191) 168
5812 19:23:48.358720 iDelay=200, Bit 1, Center 99 (16 ~ 183) 168
5813 19:23:48.362638 iDelay=200, Bit 2, Center 91 (8 ~ 175) 168
5814 19:23:48.365575 iDelay=200, Bit 3, Center 103 (16 ~ 191) 176
5815 19:23:48.371880 iDelay=200, Bit 4, Center 107 (24 ~ 191) 168
5816 19:23:48.375701 iDelay=200, Bit 5, Center 111 (24 ~ 199) 176
5817 19:23:48.378874 iDelay=200, Bit 6, Center 107 (24 ~ 191) 168
5818 19:23:48.382029 iDelay=200, Bit 7, Center 107 (24 ~ 191) 168
5819 19:23:48.385415 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5820 19:23:48.388733 iDelay=200, Bit 9, Center 87 (0 ~ 175) 176
5821 19:23:48.395199 iDelay=200, Bit 10, Center 99 (8 ~ 191) 184
5822 19:23:48.399238 iDelay=200, Bit 11, Center 91 (0 ~ 183) 184
5823 19:23:48.402128 iDelay=200, Bit 12, Center 107 (16 ~ 199) 184
5824 19:23:48.405357 iDelay=200, Bit 13, Center 103 (16 ~ 191) 176
5825 19:23:48.408882 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5826 19:23:48.415510 iDelay=200, Bit 15, Center 107 (16 ~ 199) 184
5827 19:23:48.415929 ==
5828 19:23:48.418937 Dram Type= 6, Freq= 0, CH_1, rank 1
5829 19:23:48.421945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5830 19:23:48.422365 ==
5831 19:23:48.422695 DQS Delay:
5832 19:23:48.425718 DQS0 = 0, DQS1 = 0
5833 19:23:48.426247 DQM Delay:
5834 19:23:48.428683 DQM0 = 104, DQM1 = 97
5835 19:23:48.429095 DQ Delay:
5836 19:23:48.432235 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =103
5837 19:23:48.435734 DQ4 =107, DQ5 =111, DQ6 =107, DQ7 =107
5838 19:23:48.438620 DQ8 =83, DQ9 =87, DQ10 =99, DQ11 =91
5839 19:23:48.441906 DQ12 =107, DQ13 =103, DQ14 =99, DQ15 =107
5840 19:23:48.442355
5841 19:23:48.442837
5842 19:23:48.443166 ==
5843 19:23:48.445420 Dram Type= 6, Freq= 0, CH_1, rank 1
5844 19:23:48.452208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5845 19:23:48.452729 ==
5846 19:23:48.453060
5847 19:23:48.453414
5848 19:23:48.453720 TX Vref Scan disable
5849 19:23:48.454957 == TX Byte 0 ==
5850 19:23:48.458779 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5851 19:23:48.465685 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5852 19:23:48.466206 == TX Byte 1 ==
5853 19:23:48.469226 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5854 19:23:48.475736 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5855 19:23:48.476257 ==
5856 19:23:48.479053 Dram Type= 6, Freq= 0, CH_1, rank 1
5857 19:23:48.481840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5858 19:23:48.482388 ==
5859 19:23:48.482761
5860 19:23:48.483072
5861 19:23:48.485507 TX Vref Scan disable
5862 19:23:48.486021 == TX Byte 0 ==
5863 19:23:48.491847 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5864 19:23:48.494987 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5865 19:23:48.495425 == TX Byte 1 ==
5866 19:23:48.501799 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5867 19:23:48.505251 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5868 19:23:48.505821
5869 19:23:48.506186 [DATLAT]
5870 19:23:48.508545 Freq=933, CH1 RK1
5871 19:23:48.509061
5872 19:23:48.509450 DATLAT Default: 0xb
5873 19:23:48.511734 0, 0xFFFF, sum = 0
5874 19:23:48.512153 1, 0xFFFF, sum = 0
5875 19:23:48.514897 2, 0xFFFF, sum = 0
5876 19:23:48.515319 3, 0xFFFF, sum = 0
5877 19:23:48.518234 4, 0xFFFF, sum = 0
5878 19:23:48.518656 5, 0xFFFF, sum = 0
5879 19:23:48.521506 6, 0xFFFF, sum = 0
5880 19:23:48.524993 7, 0xFFFF, sum = 0
5881 19:23:48.525462 8, 0xFFFF, sum = 0
5882 19:23:48.528431 9, 0xFFFF, sum = 0
5883 19:23:48.528951 10, 0x0, sum = 1
5884 19:23:48.529288 11, 0x0, sum = 2
5885 19:23:48.531810 12, 0x0, sum = 3
5886 19:23:48.532343 13, 0x0, sum = 4
5887 19:23:48.534801 best_step = 11
5888 19:23:48.535281
5889 19:23:48.535662 ==
5890 19:23:48.538096 Dram Type= 6, Freq= 0, CH_1, rank 1
5891 19:23:48.541211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5892 19:23:48.541712 ==
5893 19:23:48.544932 RX Vref Scan: 0
5894 19:23:48.545382
5895 19:23:48.545721 RX Vref 0 -> 0, step: 1
5896 19:23:48.547974
5897 19:23:48.548387 RX Delay -53 -> 252, step: 4
5898 19:23:48.555435 iDelay=199, Bit 0, Center 114 (43 ~ 186) 144
5899 19:23:48.558908 iDelay=199, Bit 1, Center 104 (31 ~ 178) 148
5900 19:23:48.562260 iDelay=199, Bit 2, Center 96 (23 ~ 170) 148
5901 19:23:48.565827 iDelay=199, Bit 3, Center 106 (27 ~ 186) 160
5902 19:23:48.569324 iDelay=199, Bit 4, Center 108 (31 ~ 186) 156
5903 19:23:48.575640 iDelay=199, Bit 5, Center 118 (39 ~ 198) 160
5904 19:23:48.578794 iDelay=199, Bit 6, Center 116 (39 ~ 194) 156
5905 19:23:48.582309 iDelay=199, Bit 7, Center 106 (31 ~ 182) 152
5906 19:23:48.585403 iDelay=199, Bit 8, Center 88 (7 ~ 170) 164
5907 19:23:48.589355 iDelay=199, Bit 9, Center 90 (11 ~ 170) 160
5908 19:23:48.595342 iDelay=199, Bit 10, Center 102 (23 ~ 182) 160
5909 19:23:48.598929 iDelay=199, Bit 11, Center 96 (15 ~ 178) 164
5910 19:23:48.601858 iDelay=199, Bit 12, Center 108 (27 ~ 190) 164
5911 19:23:48.605462 iDelay=199, Bit 13, Center 108 (27 ~ 190) 164
5912 19:23:48.608587 iDelay=199, Bit 14, Center 106 (23 ~ 190) 168
5913 19:23:48.615191 iDelay=199, Bit 15, Center 110 (27 ~ 194) 168
5914 19:23:48.615652 ==
5915 19:23:48.618515 Dram Type= 6, Freq= 0, CH_1, rank 1
5916 19:23:48.621696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5917 19:23:48.622344 ==
5918 19:23:48.622756 DQS Delay:
5919 19:23:48.625055 DQS0 = 0, DQS1 = 0
5920 19:23:48.625764 DQM Delay:
5921 19:23:48.628478 DQM0 = 108, DQM1 = 101
5922 19:23:48.629106 DQ Delay:
5923 19:23:48.631915 DQ0 =114, DQ1 =104, DQ2 =96, DQ3 =106
5924 19:23:48.635350 DQ4 =108, DQ5 =118, DQ6 =116, DQ7 =106
5925 19:23:48.638403 DQ8 =88, DQ9 =90, DQ10 =102, DQ11 =96
5926 19:23:48.642106 DQ12 =108, DQ13 =108, DQ14 =106, DQ15 =110
5927 19:23:48.642561
5928 19:23:48.642898
5929 19:23:48.651612 [DQSOSCAuto] RK1, (LSB)MR18= 0x21fd, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 411 ps
5930 19:23:48.655085 CH1 RK1: MR19=504, MR18=21FD
5931 19:23:48.658701 CH1_RK1: MR19=0x504, MR18=0x21FD, DQSOSC=411, MR23=63, INC=64, DEC=42
5932 19:23:48.661749 [RxdqsGatingPostProcess] freq 933
5933 19:23:48.668382 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5934 19:23:48.671849 best DQS0 dly(2T, 0.5T) = (0, 10)
5935 19:23:48.674732 best DQS1 dly(2T, 0.5T) = (0, 10)
5936 19:23:48.678327 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5937 19:23:48.681798 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5938 19:23:48.684739 best DQS0 dly(2T, 0.5T) = (0, 10)
5939 19:23:48.688309 best DQS1 dly(2T, 0.5T) = (0, 10)
5940 19:23:48.691774 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5941 19:23:48.695317 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5942 19:23:48.695917 Pre-setting of DQS Precalculation
5943 19:23:48.701686 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5944 19:23:48.708055 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5945 19:23:48.714951 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5946 19:23:48.715526
5947 19:23:48.716032
5948 19:23:48.718215 [Calibration Summary] 1866 Mbps
5949 19:23:48.721285 CH 0, Rank 0
5950 19:23:48.721744 SW Impedance : PASS
5951 19:23:48.724872 DUTY Scan : NO K
5952 19:23:48.728107 ZQ Calibration : PASS
5953 19:23:48.728529 Jitter Meter : NO K
5954 19:23:48.731453 CBT Training : PASS
5955 19:23:48.734970 Write leveling : PASS
5956 19:23:48.735587 RX DQS gating : PASS
5957 19:23:48.738275 RX DQ/DQS(RDDQC) : PASS
5958 19:23:48.741724 TX DQ/DQS : PASS
5959 19:23:48.742170 RX DATLAT : PASS
5960 19:23:48.744792 RX DQ/DQS(Engine): PASS
5961 19:23:48.745214 TX OE : NO K
5962 19:23:48.748018 All Pass.
5963 19:23:48.748464
5964 19:23:48.748797 CH 0, Rank 1
5965 19:23:48.751657 SW Impedance : PASS
5966 19:23:48.752106 DUTY Scan : NO K
5967 19:23:48.754545 ZQ Calibration : PASS
5968 19:23:48.758329 Jitter Meter : NO K
5969 19:23:48.758757 CBT Training : PASS
5970 19:23:48.761114 Write leveling : PASS
5971 19:23:48.764686 RX DQS gating : PASS
5972 19:23:48.765111 RX DQ/DQS(RDDQC) : PASS
5973 19:23:48.767918 TX DQ/DQS : PASS
5974 19:23:48.771486 RX DATLAT : PASS
5975 19:23:48.771960 RX DQ/DQS(Engine): PASS
5976 19:23:48.774663 TX OE : NO K
5977 19:23:48.775089 All Pass.
5978 19:23:48.775513
5979 19:23:48.777796 CH 1, Rank 0
5980 19:23:48.778221 SW Impedance : PASS
5981 19:23:48.781499 DUTY Scan : NO K
5982 19:23:48.784332 ZQ Calibration : PASS
5983 19:23:48.784761 Jitter Meter : NO K
5984 19:23:48.787911 CBT Training : PASS
5985 19:23:48.791322 Write leveling : PASS
5986 19:23:48.792001 RX DQS gating : PASS
5987 19:23:48.794342 RX DQ/DQS(RDDQC) : PASS
5988 19:23:48.794845 TX DQ/DQS : PASS
5989 19:23:48.797923 RX DATLAT : PASS
5990 19:23:48.801239 RX DQ/DQS(Engine): PASS
5991 19:23:48.801694 TX OE : NO K
5992 19:23:48.804605 All Pass.
5993 19:23:48.805015
5994 19:23:48.805379 CH 1, Rank 1
5995 19:23:48.808334 SW Impedance : PASS
5996 19:23:48.808848 DUTY Scan : NO K
5997 19:23:48.811068 ZQ Calibration : PASS
5998 19:23:48.814343 Jitter Meter : NO K
5999 19:23:48.814828 CBT Training : PASS
6000 19:23:48.817897 Write leveling : PASS
6001 19:23:48.821378 RX DQS gating : PASS
6002 19:23:48.821799 RX DQ/DQS(RDDQC) : PASS
6003 19:23:48.824624 TX DQ/DQS : PASS
6004 19:23:48.827834 RX DATLAT : PASS
6005 19:23:48.828417 RX DQ/DQS(Engine): PASS
6006 19:23:48.831659 TX OE : NO K
6007 19:23:48.832071 All Pass.
6008 19:23:48.832418
6009 19:23:48.834420 DramC Write-DBI off
6010 19:23:48.837824 PER_BANK_REFRESH: Hybrid Mode
6011 19:23:48.838235 TX_TRACKING: ON
6012 19:23:48.847632 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6013 19:23:48.850928 [FAST_K] Save calibration result to emmc
6014 19:23:48.854638 dramc_set_vcore_voltage set vcore to 650000
6015 19:23:48.857835 Read voltage for 400, 6
6016 19:23:48.858251 Vio18 = 0
6017 19:23:48.858578 Vcore = 650000
6018 19:23:48.861182 Vdram = 0
6019 19:23:48.861629 Vddq = 0
6020 19:23:48.861960 Vmddr = 0
6021 19:23:48.867691 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6022 19:23:48.871093 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6023 19:23:48.874801 MEM_TYPE=3, freq_sel=20
6024 19:23:48.877769 sv_algorithm_assistance_LP4_800
6025 19:23:48.880943 ============ PULL DRAM RESETB DOWN ============
6026 19:23:48.884861 ========== PULL DRAM RESETB DOWN end =========
6027 19:23:48.891066 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6028 19:23:48.894514 ===================================
6029 19:23:48.895080 LPDDR4 DRAM CONFIGURATION
6030 19:23:48.897700 ===================================
6031 19:23:48.901096 EX_ROW_EN[0] = 0x0
6032 19:23:48.904319 EX_ROW_EN[1] = 0x0
6033 19:23:48.904882 LP4Y_EN = 0x0
6034 19:23:48.907711 WORK_FSP = 0x0
6035 19:23:48.908278 WL = 0x2
6036 19:23:48.911251 RL = 0x2
6037 19:23:48.911815 BL = 0x2
6038 19:23:48.914663 RPST = 0x0
6039 19:23:48.915227 RD_PRE = 0x0
6040 19:23:48.917810 WR_PRE = 0x1
6041 19:23:48.918441 WR_PST = 0x0
6042 19:23:48.920821 DBI_WR = 0x0
6043 19:23:48.921282 DBI_RD = 0x0
6044 19:23:48.924508 OTF = 0x1
6045 19:23:48.928084 ===================================
6046 19:23:48.931047 ===================================
6047 19:23:48.931561 ANA top config
6048 19:23:48.934142 ===================================
6049 19:23:48.937832 DLL_ASYNC_EN = 0
6050 19:23:48.940675 ALL_SLAVE_EN = 1
6051 19:23:48.941189 NEW_RANK_MODE = 1
6052 19:23:48.944175 DLL_IDLE_MODE = 1
6053 19:23:48.947672 LP45_APHY_COMB_EN = 1
6054 19:23:48.950847 TX_ODT_DIS = 1
6055 19:23:48.954083 NEW_8X_MODE = 1
6056 19:23:48.957394 ===================================
6057 19:23:48.960463 ===================================
6058 19:23:48.960991 data_rate = 800
6059 19:23:48.964070 CKR = 1
6060 19:23:48.967477 DQ_P2S_RATIO = 4
6061 19:23:48.970783 ===================================
6062 19:23:48.973977 CA_P2S_RATIO = 4
6063 19:23:48.977633 DQ_CA_OPEN = 0
6064 19:23:48.980724 DQ_SEMI_OPEN = 1
6065 19:23:48.981192 CA_SEMI_OPEN = 1
6066 19:23:48.984131 CA_FULL_RATE = 0
6067 19:23:48.987600 DQ_CKDIV4_EN = 0
6068 19:23:48.990768 CA_CKDIV4_EN = 1
6069 19:23:48.994293 CA_PREDIV_EN = 0
6070 19:23:48.997736 PH8_DLY = 0
6071 19:23:48.998158 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6072 19:23:49.000552 DQ_AAMCK_DIV = 0
6073 19:23:49.003986 CA_AAMCK_DIV = 0
6074 19:23:49.007424 CA_ADMCK_DIV = 4
6075 19:23:49.011054 DQ_TRACK_CA_EN = 0
6076 19:23:49.013774 CA_PICK = 800
6077 19:23:49.014199 CA_MCKIO = 400
6078 19:23:49.017533 MCKIO_SEMI = 400
6079 19:23:49.020450 PLL_FREQ = 3016
6080 19:23:49.023908 DQ_UI_PI_RATIO = 32
6081 19:23:49.027276 CA_UI_PI_RATIO = 32
6082 19:23:49.030384 ===================================
6083 19:23:49.034029 ===================================
6084 19:23:49.037341 memory_type:LPDDR4
6085 19:23:49.037830 GP_NUM : 10
6086 19:23:49.040649 SRAM_EN : 1
6087 19:23:49.043992 MD32_EN : 0
6088 19:23:49.047496 ===================================
6089 19:23:49.048013 [ANA_INIT] >>>>>>>>>>>>>>
6090 19:23:49.050644 <<<<<< [CONFIGURE PHASE]: ANA_TX
6091 19:23:49.054445 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6092 19:23:49.057363 ===================================
6093 19:23:49.060648 data_rate = 800,PCW = 0X7400
6094 19:23:49.063954 ===================================
6095 19:23:49.067871 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6096 19:23:49.073846 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6097 19:23:49.083933 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6098 19:23:49.087039 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6099 19:23:49.090203 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6100 19:23:49.096936 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6101 19:23:49.097441 [ANA_INIT] flow start
6102 19:23:49.100476 [ANA_INIT] PLL >>>>>>>>
6103 19:23:49.100944 [ANA_INIT] PLL <<<<<<<<
6104 19:23:49.104081 [ANA_INIT] MIDPI >>>>>>>>
6105 19:23:49.107092 [ANA_INIT] MIDPI <<<<<<<<
6106 19:23:49.110430 [ANA_INIT] DLL >>>>>>>>
6107 19:23:49.110989 [ANA_INIT] flow end
6108 19:23:49.113911 ============ LP4 DIFF to SE enter ============
6109 19:23:49.120176 ============ LP4 DIFF to SE exit ============
6110 19:23:49.120761 [ANA_INIT] <<<<<<<<<<<<<
6111 19:23:49.123521 [Flow] Enable top DCM control >>>>>
6112 19:23:49.127302 [Flow] Enable top DCM control <<<<<
6113 19:23:49.130687 Enable DLL master slave shuffle
6114 19:23:49.137146 ==============================================================
6115 19:23:49.137747 Gating Mode config
6116 19:23:49.143816 ==============================================================
6117 19:23:49.147476 Config description:
6118 19:23:49.157260 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6119 19:23:49.163335 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6120 19:23:49.166933 SELPH_MODE 0: By rank 1: By Phase
6121 19:23:49.173395 ==============================================================
6122 19:23:49.177092 GAT_TRACK_EN = 0
6123 19:23:49.177828 RX_GATING_MODE = 2
6124 19:23:49.180241 RX_GATING_TRACK_MODE = 2
6125 19:23:49.183558 SELPH_MODE = 1
6126 19:23:49.187071 PICG_EARLY_EN = 1
6127 19:23:49.190220 VALID_LAT_VALUE = 1
6128 19:23:49.196832 ==============================================================
6129 19:23:49.200057 Enter into Gating configuration >>>>
6130 19:23:49.203558 Exit from Gating configuration <<<<
6131 19:23:49.206748 Enter into DVFS_PRE_config >>>>>
6132 19:23:49.216664 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6133 19:23:49.219986 Exit from DVFS_PRE_config <<<<<
6134 19:23:49.223365 Enter into PICG configuration >>>>
6135 19:23:49.226712 Exit from PICG configuration <<<<
6136 19:23:49.230207 [RX_INPUT] configuration >>>>>
6137 19:23:49.233150 [RX_INPUT] configuration <<<<<
6138 19:23:49.236759 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6139 19:23:49.243332 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6140 19:23:49.249921 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6141 19:23:49.253194 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6142 19:23:49.259968 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6143 19:23:49.266505 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6144 19:23:49.269693 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6145 19:23:49.273373 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6146 19:23:49.279762 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6147 19:23:49.283017 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6148 19:23:49.286340 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6149 19:23:49.293037 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6150 19:23:49.296499 ===================================
6151 19:23:49.296945 LPDDR4 DRAM CONFIGURATION
6152 19:23:49.299626 ===================================
6153 19:23:49.303154 EX_ROW_EN[0] = 0x0
6154 19:23:49.303723 EX_ROW_EN[1] = 0x0
6155 19:23:49.306745 LP4Y_EN = 0x0
6156 19:23:49.309811 WORK_FSP = 0x0
6157 19:23:49.310268 WL = 0x2
6158 19:23:49.313255 RL = 0x2
6159 19:23:49.313729 BL = 0x2
6160 19:23:49.316351 RPST = 0x0
6161 19:23:49.316869 RD_PRE = 0x0
6162 19:23:49.319670 WR_PRE = 0x1
6163 19:23:49.320221 WR_PST = 0x0
6164 19:23:49.323148 DBI_WR = 0x0
6165 19:23:49.323567 DBI_RD = 0x0
6166 19:23:49.326202 OTF = 0x1
6167 19:23:49.329857 ===================================
6168 19:23:49.332823 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6169 19:23:49.336109 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6170 19:23:49.343069 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6171 19:23:49.346226 ===================================
6172 19:23:49.346656 LPDDR4 DRAM CONFIGURATION
6173 19:23:49.349366 ===================================
6174 19:23:49.352929 EX_ROW_EN[0] = 0x10
6175 19:23:49.353337 EX_ROW_EN[1] = 0x0
6176 19:23:49.356349 LP4Y_EN = 0x0
6177 19:23:49.356735 WORK_FSP = 0x0
6178 19:23:49.359753 WL = 0x2
6179 19:23:49.360050 RL = 0x2
6180 19:23:49.363183 BL = 0x2
6181 19:23:49.366602 RPST = 0x0
6182 19:23:49.367006 RD_PRE = 0x0
6183 19:23:49.369402 WR_PRE = 0x1
6184 19:23:49.369701 WR_PST = 0x0
6185 19:23:49.373178 DBI_WR = 0x0
6186 19:23:49.373618 DBI_RD = 0x0
6187 19:23:49.376331 OTF = 0x1
6188 19:23:49.379393 ===================================
6189 19:23:49.382690 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6190 19:23:49.388397 nWR fixed to 30
6191 19:23:49.391807 [ModeRegInit_LP4] CH0 RK0
6192 19:23:49.392171 [ModeRegInit_LP4] CH0 RK1
6193 19:23:49.395016 [ModeRegInit_LP4] CH1 RK0
6194 19:23:49.398228 [ModeRegInit_LP4] CH1 RK1
6195 19:23:49.398598 match AC timing 19
6196 19:23:49.404758 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6197 19:23:49.408012 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6198 19:23:49.411381 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6199 19:23:49.418127 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6200 19:23:49.421262 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6201 19:23:49.421755 ==
6202 19:23:49.424894 Dram Type= 6, Freq= 0, CH_0, rank 0
6203 19:23:49.427834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6204 19:23:49.428264 ==
6205 19:23:49.434758 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6206 19:23:49.441323 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6207 19:23:49.444757 [CA 0] Center 36 (8~64) winsize 57
6208 19:23:49.448257 [CA 1] Center 36 (8~64) winsize 57
6209 19:23:49.451305 [CA 2] Center 36 (8~64) winsize 57
6210 19:23:49.451608 [CA 3] Center 36 (8~64) winsize 57
6211 19:23:49.454695 [CA 4] Center 36 (8~64) winsize 57
6212 19:23:49.458080 [CA 5] Center 36 (8~64) winsize 57
6213 19:23:49.458383
6214 19:23:49.464443 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6215 19:23:49.464744
6216 19:23:49.467799 [CATrainingPosCal] consider 1 rank data
6217 19:23:49.471275 u2DelayCellTimex100 = 270/100 ps
6218 19:23:49.474524 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6219 19:23:49.477721 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6220 19:23:49.481248 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6221 19:23:49.484204 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6222 19:23:49.487578 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6223 19:23:49.491006 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6224 19:23:49.491112
6225 19:23:49.494389 CA PerBit enable=1, Macro0, CA PI delay=36
6226 19:23:49.494473
6227 19:23:49.497463 [CBTSetCACLKResult] CA Dly = 36
6228 19:23:49.501106 CS Dly: 1 (0~32)
6229 19:23:49.501189 ==
6230 19:23:49.504043 Dram Type= 6, Freq= 0, CH_0, rank 1
6231 19:23:49.507242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6232 19:23:49.507325 ==
6233 19:23:49.513971 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6234 19:23:49.517155 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6235 19:23:49.520515 [CA 0] Center 36 (8~64) winsize 57
6236 19:23:49.524032 [CA 1] Center 36 (8~64) winsize 57
6237 19:23:49.527582 [CA 2] Center 36 (8~64) winsize 57
6238 19:23:49.530649 [CA 3] Center 36 (8~64) winsize 57
6239 19:23:49.534052 [CA 4] Center 36 (8~64) winsize 57
6240 19:23:49.537528 [CA 5] Center 36 (8~64) winsize 57
6241 19:23:49.537612
6242 19:23:49.540412 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6243 19:23:49.540502
6244 19:23:49.543852 [CATrainingPosCal] consider 2 rank data
6245 19:23:49.547463 u2DelayCellTimex100 = 270/100 ps
6246 19:23:49.550763 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 19:23:49.554094 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 19:23:49.560611 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 19:23:49.564025 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 19:23:49.567444 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 19:23:49.570825 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 19:23:49.571248
6253 19:23:49.574333 CA PerBit enable=1, Macro0, CA PI delay=36
6254 19:23:49.574757
6255 19:23:49.577465 [CBTSetCACLKResult] CA Dly = 36
6256 19:23:49.578004 CS Dly: 1 (0~32)
6257 19:23:49.578499
6258 19:23:49.580696 ----->DramcWriteLeveling(PI) begin...
6259 19:23:49.583878 ==
6260 19:23:49.587588 Dram Type= 6, Freq= 0, CH_0, rank 0
6261 19:23:49.590880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6262 19:23:49.591442 ==
6263 19:23:49.594056 Write leveling (Byte 0): 40 => 8
6264 19:23:49.597254 Write leveling (Byte 1): 32 => 0
6265 19:23:49.601033 DramcWriteLeveling(PI) end<-----
6266 19:23:49.601585
6267 19:23:49.601919 ==
6268 19:23:49.603921 Dram Type= 6, Freq= 0, CH_0, rank 0
6269 19:23:49.607578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6270 19:23:49.608094 ==
6271 19:23:49.610416 [Gating] SW mode calibration
6272 19:23:49.617402 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6273 19:23:49.620512 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6274 19:23:49.627334 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6275 19:23:49.630760 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6276 19:23:49.634032 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6277 19:23:49.640600 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6278 19:23:49.644086 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6279 19:23:49.647657 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6280 19:23:49.653768 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6281 19:23:49.657008 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6282 19:23:49.660586 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6283 19:23:49.663829 Total UI for P1: 0, mck2ui 16
6284 19:23:49.667480 best dqsien dly found for B0: ( 0, 14, 24)
6285 19:23:49.670411 Total UI for P1: 0, mck2ui 16
6286 19:23:49.673634 best dqsien dly found for B1: ( 0, 14, 24)
6287 19:23:49.676937 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6288 19:23:49.680439 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6289 19:23:49.683941
6290 19:23:49.687080 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6291 19:23:49.690431 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6292 19:23:49.693637 [Gating] SW calibration Done
6293 19:23:49.694131 ==
6294 19:23:49.697004 Dram Type= 6, Freq= 0, CH_0, rank 0
6295 19:23:49.700185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6296 19:23:49.700636 ==
6297 19:23:49.701013 RX Vref Scan: 0
6298 19:23:49.701383
6299 19:23:49.703730 RX Vref 0 -> 0, step: 1
6300 19:23:49.704263
6301 19:23:49.707115 RX Delay -410 -> 252, step: 16
6302 19:23:49.710227 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6303 19:23:49.717126 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6304 19:23:49.720457 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6305 19:23:49.723454 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6306 19:23:49.726989 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6307 19:23:49.734082 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6308 19:23:49.736812 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6309 19:23:49.740469 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6310 19:23:49.743360 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6311 19:23:49.747104 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6312 19:23:49.753529 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6313 19:23:49.757245 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6314 19:23:49.760365 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6315 19:23:49.767092 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6316 19:23:49.770061 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6317 19:23:49.773631 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6318 19:23:49.774086 ==
6319 19:23:49.776874 Dram Type= 6, Freq= 0, CH_0, rank 0
6320 19:23:49.780573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6321 19:23:49.783840 ==
6322 19:23:49.784397 DQS Delay:
6323 19:23:49.784759 DQS0 = 19, DQS1 = 43
6324 19:23:49.787158 DQM Delay:
6325 19:23:49.787714 DQM0 = 5, DQM1 = 15
6326 19:23:49.790198 DQ Delay:
6327 19:23:49.790741 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6328 19:23:49.793742 DQ4 =8, DQ5 =0, DQ6 =8, DQ7 =16
6329 19:23:49.796914 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6330 19:23:49.800020 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6331 19:23:49.800473
6332 19:23:49.800825
6333 19:23:49.801160 ==
6334 19:23:49.803493 Dram Type= 6, Freq= 0, CH_0, rank 0
6335 19:23:49.810090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6336 19:23:49.810638 ==
6337 19:23:49.810996
6338 19:23:49.811324
6339 19:23:49.811637 TX Vref Scan disable
6340 19:23:49.813186 == TX Byte 0 ==
6341 19:23:49.816321 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6342 19:23:49.819870 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6343 19:23:49.823284 == TX Byte 1 ==
6344 19:23:49.826485 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6345 19:23:49.830069 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6346 19:23:49.833370 ==
6347 19:23:49.833822 Dram Type= 6, Freq= 0, CH_0, rank 0
6348 19:23:49.840534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6349 19:23:49.841081 ==
6350 19:23:49.841469
6351 19:23:49.841838
6352 19:23:49.843097 TX Vref Scan disable
6353 19:23:49.843543 == TX Byte 0 ==
6354 19:23:49.846869 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6355 19:23:49.853728 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6356 19:23:49.854276 == TX Byte 1 ==
6357 19:23:49.856582 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6358 19:23:49.863191 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6359 19:23:49.863726
6360 19:23:49.864078 [DATLAT]
6361 19:23:49.864402 Freq=400, CH0 RK0
6362 19:23:49.864713
6363 19:23:49.866531 DATLAT Default: 0xf
6364 19:23:49.866976 0, 0xFFFF, sum = 0
6365 19:23:49.870252 1, 0xFFFF, sum = 0
6366 19:23:49.870804 2, 0xFFFF, sum = 0
6367 19:23:49.873003 3, 0xFFFF, sum = 0
6368 19:23:49.876887 4, 0xFFFF, sum = 0
6369 19:23:49.877483 5, 0xFFFF, sum = 0
6370 19:23:49.879667 6, 0xFFFF, sum = 0
6371 19:23:49.880118 7, 0xFFFF, sum = 0
6372 19:23:49.883181 8, 0xFFFF, sum = 0
6373 19:23:49.883733 9, 0xFFFF, sum = 0
6374 19:23:49.886567 10, 0xFFFF, sum = 0
6375 19:23:49.887122 11, 0xFFFF, sum = 0
6376 19:23:49.890016 12, 0xFFFF, sum = 0
6377 19:23:49.890579 13, 0x0, sum = 1
6378 19:23:49.892954 14, 0x0, sum = 2
6379 19:23:49.893436 15, 0x0, sum = 3
6380 19:23:49.896618 16, 0x0, sum = 4
6381 19:23:49.897172 best_step = 14
6382 19:23:49.897583
6383 19:23:49.897915 ==
6384 19:23:49.899474 Dram Type= 6, Freq= 0, CH_0, rank 0
6385 19:23:49.902916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6386 19:23:49.906494 ==
6387 19:23:49.906939 RX Vref Scan: 1
6388 19:23:49.907290
6389 19:23:49.909904 RX Vref 0 -> 0, step: 1
6390 19:23:49.910448
6391 19:23:49.912907 RX Delay -327 -> 252, step: 8
6392 19:23:49.913469
6393 19:23:49.913918 Set Vref, RX VrefLevel [Byte0]: 60
6394 19:23:49.916051 [Byte1]: 48
6395 19:23:49.921789
6396 19:23:49.922233 Final RX Vref Byte 0 = 60 to rank0
6397 19:23:49.925022 Final RX Vref Byte 1 = 48 to rank0
6398 19:23:49.928165 Final RX Vref Byte 0 = 60 to rank1
6399 19:23:49.931553 Final RX Vref Byte 1 = 48 to rank1==
6400 19:23:49.935156 Dram Type= 6, Freq= 0, CH_0, rank 0
6401 19:23:49.941495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6402 19:23:49.942018 ==
6403 19:23:49.942377 DQS Delay:
6404 19:23:49.944831 DQS0 = 28, DQS1 = 48
6405 19:23:49.945281 DQM Delay:
6406 19:23:49.945688 DQM0 = 12, DQM1 = 16
6407 19:23:49.948321 DQ Delay:
6408 19:23:49.952043 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6409 19:23:49.952475 DQ4 =12, DQ5 =0, DQ6 =24, DQ7 =20
6410 19:23:49.954864 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =12
6411 19:23:49.958382 DQ12 =24, DQ13 =20, DQ14 =28, DQ15 =24
6412 19:23:49.961791
6413 19:23:49.962196
6414 19:23:49.968366 [DQSOSCAuto] RK0, (LSB)MR18= 0xaaa2, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 388 ps
6415 19:23:49.971408 CH0 RK0: MR19=C0C, MR18=AAA2
6416 19:23:49.978226 CH0_RK0: MR19=0xC0C, MR18=0xAAA2, DQSOSC=388, MR23=63, INC=392, DEC=261
6417 19:23:49.978635 ==
6418 19:23:49.981808 Dram Type= 6, Freq= 0, CH_0, rank 1
6419 19:23:49.985050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6420 19:23:49.985493 ==
6421 19:23:49.988408 [Gating] SW mode calibration
6422 19:23:49.994901 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6423 19:23:50.001745 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6424 19:23:50.004716 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6425 19:23:50.008000 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6426 19:23:50.014840 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6427 19:23:50.018059 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6428 19:23:50.021390 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6429 19:23:50.024687 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6430 19:23:50.031280 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6431 19:23:50.034492 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6432 19:23:50.037576 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6433 19:23:50.041248 Total UI for P1: 0, mck2ui 16
6434 19:23:50.044853 best dqsien dly found for B0: ( 0, 14, 24)
6435 19:23:50.048258 Total UI for P1: 0, mck2ui 16
6436 19:23:50.051256 best dqsien dly found for B1: ( 0, 14, 24)
6437 19:23:50.054652 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6438 19:23:50.057626 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6439 19:23:50.061103
6440 19:23:50.064590 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6441 19:23:50.068353 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6442 19:23:50.071157 [Gating] SW calibration Done
6443 19:23:50.071239 ==
6444 19:23:50.074556 Dram Type= 6, Freq= 0, CH_0, rank 1
6445 19:23:50.078084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6446 19:23:50.078172 ==
6447 19:23:50.078241 RX Vref Scan: 0
6448 19:23:50.078305
6449 19:23:50.081260 RX Vref 0 -> 0, step: 1
6450 19:23:50.081362
6451 19:23:50.084573 RX Delay -410 -> 252, step: 16
6452 19:23:50.087738 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6453 19:23:50.094680 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6454 19:23:50.097767 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6455 19:23:50.101355 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6456 19:23:50.104448 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6457 19:23:50.111175 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6458 19:23:50.114514 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6459 19:23:50.117880 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6460 19:23:50.121006 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6461 19:23:50.127817 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6462 19:23:50.130948 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6463 19:23:50.134564 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6464 19:23:50.137973 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6465 19:23:50.144393 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6466 19:23:50.147656 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6467 19:23:50.151115 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6468 19:23:50.151623 ==
6469 19:23:50.154622 Dram Type= 6, Freq= 0, CH_0, rank 1
6470 19:23:50.157607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6471 19:23:50.161084 ==
6472 19:23:50.161586 DQS Delay:
6473 19:23:50.161902 DQS0 = 27, DQS1 = 35
6474 19:23:50.164602 DQM Delay:
6475 19:23:50.165167 DQM0 = 9, DQM1 = 9
6476 19:23:50.167949 DQ Delay:
6477 19:23:50.168375 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6478 19:23:50.170904 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6479 19:23:50.174357 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6480 19:23:50.177778 DQ12 =8, DQ13 =16, DQ14 =16, DQ15 =16
6481 19:23:50.178228
6482 19:23:50.178626
6483 19:23:50.178962 ==
6484 19:23:50.181270 Dram Type= 6, Freq= 0, CH_0, rank 1
6485 19:23:50.187624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6486 19:23:50.188212 ==
6487 19:23:50.188722
6488 19:23:50.189204
6489 19:23:50.189673 TX Vref Scan disable
6490 19:23:50.191081 == TX Byte 0 ==
6491 19:23:50.194277 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6492 19:23:50.197865 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6493 19:23:50.200897 == TX Byte 1 ==
6494 19:23:50.204149 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6495 19:23:50.207656 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6496 19:23:50.208255 ==
6497 19:23:50.210879 Dram Type= 6, Freq= 0, CH_0, rank 1
6498 19:23:50.217396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6499 19:23:50.217947 ==
6500 19:23:50.218290
6501 19:23:50.218791
6502 19:23:50.219146 TX Vref Scan disable
6503 19:23:50.220733 == TX Byte 0 ==
6504 19:23:50.223995 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6505 19:23:50.227612 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6506 19:23:50.230906 == TX Byte 1 ==
6507 19:23:50.234563 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6508 19:23:50.237824 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6509 19:23:50.238298
6510 19:23:50.240890 [DATLAT]
6511 19:23:50.241474 Freq=400, CH0 RK1
6512 19:23:50.241986
6513 19:23:50.244170 DATLAT Default: 0xe
6514 19:23:50.244707 0, 0xFFFF, sum = 0
6515 19:23:50.247626 1, 0xFFFF, sum = 0
6516 19:23:50.248201 2, 0xFFFF, sum = 0
6517 19:23:50.250689 3, 0xFFFF, sum = 0
6518 19:23:50.251236 4, 0xFFFF, sum = 0
6519 19:23:50.254406 5, 0xFFFF, sum = 0
6520 19:23:50.254875 6, 0xFFFF, sum = 0
6521 19:23:50.257237 7, 0xFFFF, sum = 0
6522 19:23:50.257708 8, 0xFFFF, sum = 0
6523 19:23:50.260913 9, 0xFFFF, sum = 0
6524 19:23:50.261366 10, 0xFFFF, sum = 0
6525 19:23:50.264372 11, 0xFFFF, sum = 0
6526 19:23:50.267408 12, 0xFFFF, sum = 0
6527 19:23:50.267965 13, 0x0, sum = 1
6528 19:23:50.268444 14, 0x0, sum = 2
6529 19:23:50.271001 15, 0x0, sum = 3
6530 19:23:50.271420 16, 0x0, sum = 4
6531 19:23:50.274301 best_step = 14
6532 19:23:50.274715
6533 19:23:50.275043 ==
6534 19:23:50.278171 Dram Type= 6, Freq= 0, CH_0, rank 1
6535 19:23:50.281118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6536 19:23:50.281680 ==
6537 19:23:50.284143 RX Vref Scan: 0
6538 19:23:50.284558
6539 19:23:50.284884 RX Vref 0 -> 0, step: 1
6540 19:23:50.287885
6541 19:23:50.288297 RX Delay -311 -> 252, step: 8
6542 19:23:50.295672 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6543 19:23:50.298906 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6544 19:23:50.302438 iDelay=217, Bit 2, Center -24 (-247 ~ 200) 448
6545 19:23:50.305605 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6546 19:23:50.312307 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6547 19:23:50.315847 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6548 19:23:50.318959 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6549 19:23:50.322348 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6550 19:23:50.328983 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6551 19:23:50.332141 iDelay=217, Bit 9, Center -40 (-263 ~ 184) 448
6552 19:23:50.335497 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6553 19:23:50.338891 iDelay=217, Bit 11, Center -36 (-263 ~ 192) 456
6554 19:23:50.345552 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6555 19:23:50.348850 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6556 19:23:50.352174 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6557 19:23:50.355396 iDelay=217, Bit 15, Center -20 (-239 ~ 200) 440
6558 19:23:50.359461 ==
6559 19:23:50.362211 Dram Type= 6, Freq= 0, CH_0, rank 1
6560 19:23:50.365870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6561 19:23:50.366390 ==
6562 19:23:50.366771 DQS Delay:
6563 19:23:50.368849 DQS0 = 28, DQS1 = 40
6564 19:23:50.369269 DQM Delay:
6565 19:23:50.371918 DQM0 = 10, DQM1 = 12
6566 19:23:50.372337 DQ Delay:
6567 19:23:50.375911 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6568 19:23:50.378871 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6569 19:23:50.382319 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6570 19:23:50.385396 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6571 19:23:50.385816
6572 19:23:50.386148
6573 19:23:50.392049 [DQSOSCAuto] RK1, (LSB)MR18= 0xb467, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 387 ps
6574 19:23:50.395499 CH0 RK1: MR19=C0C, MR18=B467
6575 19:23:50.401987 CH0_RK1: MR19=0xC0C, MR18=0xB467, DQSOSC=387, MR23=63, INC=394, DEC=262
6576 19:23:50.405157 [RxdqsGatingPostProcess] freq 400
6577 19:23:50.408591 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6578 19:23:50.411935 best DQS0 dly(2T, 0.5T) = (0, 10)
6579 19:23:50.415195 best DQS1 dly(2T, 0.5T) = (0, 10)
6580 19:23:50.418607 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6581 19:23:50.421926 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6582 19:23:50.425420 best DQS0 dly(2T, 0.5T) = (0, 10)
6583 19:23:50.429009 best DQS1 dly(2T, 0.5T) = (0, 10)
6584 19:23:50.432014 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6585 19:23:50.435154 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6586 19:23:50.438302 Pre-setting of DQS Precalculation
6587 19:23:50.441772 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6588 19:23:50.445197 ==
6589 19:23:50.448502 Dram Type= 6, Freq= 0, CH_1, rank 0
6590 19:23:50.451892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6591 19:23:50.452320 ==
6592 19:23:50.458430 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6593 19:23:50.461436 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6594 19:23:50.464896 [CA 0] Center 36 (8~64) winsize 57
6595 19:23:50.468396 [CA 1] Center 36 (8~64) winsize 57
6596 19:23:50.471995 [CA 2] Center 36 (8~64) winsize 57
6597 19:23:50.474934 [CA 3] Center 36 (8~64) winsize 57
6598 19:23:50.478417 [CA 4] Center 36 (8~64) winsize 57
6599 19:23:50.481632 [CA 5] Center 36 (8~64) winsize 57
6600 19:23:50.482056
6601 19:23:50.485215 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6602 19:23:50.485683
6603 19:23:50.488248 [CATrainingPosCal] consider 1 rank data
6604 19:23:50.492041 u2DelayCellTimex100 = 270/100 ps
6605 19:23:50.495275 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6606 19:23:50.498521 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6607 19:23:50.501385 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6608 19:23:50.505238 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6609 19:23:50.511613 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6610 19:23:50.515123 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6611 19:23:50.515674
6612 19:23:50.518128 CA PerBit enable=1, Macro0, CA PI delay=36
6613 19:23:50.518593
6614 19:23:50.521469 [CBTSetCACLKResult] CA Dly = 36
6615 19:23:50.522021 CS Dly: 1 (0~32)
6616 19:23:50.522393 ==
6617 19:23:50.524656 Dram Type= 6, Freq= 0, CH_1, rank 1
6618 19:23:50.527935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6619 19:23:50.531313 ==
6620 19:23:50.535008 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6621 19:23:50.541941 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6622 19:23:50.545025 [CA 0] Center 36 (8~64) winsize 57
6623 19:23:50.548813 [CA 1] Center 36 (8~64) winsize 57
6624 19:23:50.551874 [CA 2] Center 36 (8~64) winsize 57
6625 19:23:50.555098 [CA 3] Center 36 (8~64) winsize 57
6626 19:23:50.558361 [CA 4] Center 36 (8~64) winsize 57
6627 19:23:50.561509 [CA 5] Center 36 (8~64) winsize 57
6628 19:23:50.562063
6629 19:23:50.565057 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6630 19:23:50.565666
6631 19:23:50.568594 [CATrainingPosCal] consider 2 rank data
6632 19:23:50.571861 u2DelayCellTimex100 = 270/100 ps
6633 19:23:50.574789 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 19:23:50.578449 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 19:23:50.581962 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 19:23:50.584702 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 19:23:50.588308 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 19:23:50.591838 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 19:23:50.592394
6640 19:23:50.595249 CA PerBit enable=1, Macro0, CA PI delay=36
6641 19:23:50.595811
6642 19:23:50.598409 [CBTSetCACLKResult] CA Dly = 36
6643 19:23:50.601528 CS Dly: 1 (0~32)
6644 19:23:50.601996
6645 19:23:50.605070 ----->DramcWriteLeveling(PI) begin...
6646 19:23:50.605663 ==
6647 19:23:50.608524 Dram Type= 6, Freq= 0, CH_1, rank 0
6648 19:23:50.611486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6649 19:23:50.612049 ==
6650 19:23:50.614915 Write leveling (Byte 0): 40 => 8
6651 19:23:50.618190 Write leveling (Byte 1): 32 => 0
6652 19:23:50.621641 DramcWriteLeveling(PI) end<-----
6653 19:23:50.622201
6654 19:23:50.622570 ==
6655 19:23:50.624813 Dram Type= 6, Freq= 0, CH_1, rank 0
6656 19:23:50.627960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6657 19:23:50.628443 ==
6658 19:23:50.631326 [Gating] SW mode calibration
6659 19:23:50.637948 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6660 19:23:50.644752 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6661 19:23:50.648076 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6662 19:23:50.654715 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6663 19:23:50.657652 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6664 19:23:50.661272 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6665 19:23:50.668061 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6666 19:23:50.671419 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6667 19:23:50.674498 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6668 19:23:50.681200 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6669 19:23:50.684643 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6670 19:23:50.687942 Total UI for P1: 0, mck2ui 16
6671 19:23:50.691414 best dqsien dly found for B0: ( 0, 14, 24)
6672 19:23:50.694885 Total UI for P1: 0, mck2ui 16
6673 19:23:50.697825 best dqsien dly found for B1: ( 0, 14, 24)
6674 19:23:50.701025 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6675 19:23:50.704592 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6676 19:23:50.705083
6677 19:23:50.707543 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6678 19:23:50.711404 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6679 19:23:50.714674 [Gating] SW calibration Done
6680 19:23:50.715233 ==
6681 19:23:50.717714 Dram Type= 6, Freq= 0, CH_1, rank 0
6682 19:23:50.720923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6683 19:23:50.721423 ==
6684 19:23:50.724671 RX Vref Scan: 0
6685 19:23:50.725223
6686 19:23:50.727530 RX Vref 0 -> 0, step: 1
6687 19:23:50.728010
6688 19:23:50.728618 RX Delay -410 -> 252, step: 16
6689 19:23:50.734613 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6690 19:23:50.737790 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6691 19:23:50.740857 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6692 19:23:50.744437 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6693 19:23:50.750964 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6694 19:23:50.754185 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6695 19:23:50.757758 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6696 19:23:50.761136 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6697 19:23:50.767878 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6698 19:23:50.771148 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6699 19:23:50.774027 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6700 19:23:50.777708 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6701 19:23:50.784686 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6702 19:23:50.787343 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6703 19:23:50.791035 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6704 19:23:50.797469 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6705 19:23:50.798023 ==
6706 19:23:50.801038 Dram Type= 6, Freq= 0, CH_1, rank 0
6707 19:23:50.804360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6708 19:23:50.804921 ==
6709 19:23:50.805291 DQS Delay:
6710 19:23:50.807653 DQS0 = 27, DQS1 = 43
6711 19:23:50.808117 DQM Delay:
6712 19:23:50.810806 DQM0 = 8, DQM1 = 17
6713 19:23:50.811364 DQ Delay:
6714 19:23:50.814195 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6715 19:23:50.817879 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =0
6716 19:23:50.820529 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6717 19:23:50.824064 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =24
6718 19:23:50.824635
6719 19:23:50.825006
6720 19:23:50.825373 ==
6721 19:23:50.827101 Dram Type= 6, Freq= 0, CH_1, rank 0
6722 19:23:50.830473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6723 19:23:50.830946 ==
6724 19:23:50.831314
6725 19:23:50.831651
6726 19:23:50.833780 TX Vref Scan disable
6727 19:23:50.834243 == TX Byte 0 ==
6728 19:23:50.840461 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6729 19:23:50.843855 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6730 19:23:50.844321 == TX Byte 1 ==
6731 19:23:50.850413 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6732 19:23:50.853815 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6733 19:23:50.854369 ==
6734 19:23:50.857189 Dram Type= 6, Freq= 0, CH_1, rank 0
6735 19:23:50.860480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6736 19:23:50.861036 ==
6737 19:23:50.861443
6738 19:23:50.861788
6739 19:23:50.863717 TX Vref Scan disable
6740 19:23:50.867446 == TX Byte 0 ==
6741 19:23:50.870736 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6742 19:23:50.873797 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6743 19:23:50.877239 == TX Byte 1 ==
6744 19:23:50.880572 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6745 19:23:50.883862 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6746 19:23:50.884352
6747 19:23:50.884723 [DATLAT]
6748 19:23:50.887505 Freq=400, CH1 RK0
6749 19:23:50.888060
6750 19:23:50.888429 DATLAT Default: 0xf
6751 19:23:50.890249 0, 0xFFFF, sum = 0
6752 19:23:50.890724 1, 0xFFFF, sum = 0
6753 19:23:50.893859 2, 0xFFFF, sum = 0
6754 19:23:50.894400 3, 0xFFFF, sum = 0
6755 19:23:50.897410 4, 0xFFFF, sum = 0
6756 19:23:50.900446 5, 0xFFFF, sum = 0
6757 19:23:50.900948 6, 0xFFFF, sum = 0
6758 19:23:50.904168 7, 0xFFFF, sum = 0
6759 19:23:50.904724 8, 0xFFFF, sum = 0
6760 19:23:50.906873 9, 0xFFFF, sum = 0
6761 19:23:50.907344 10, 0xFFFF, sum = 0
6762 19:23:50.910645 11, 0xFFFF, sum = 0
6763 19:23:50.911211 12, 0xFFFF, sum = 0
6764 19:23:50.913704 13, 0x0, sum = 1
6765 19:23:50.914272 14, 0x0, sum = 2
6766 19:23:50.917233 15, 0x0, sum = 3
6767 19:23:50.917836 16, 0x0, sum = 4
6768 19:23:50.920247 best_step = 14
6769 19:23:50.920715
6770 19:23:50.921082 ==
6771 19:23:50.923645 Dram Type= 6, Freq= 0, CH_1, rank 0
6772 19:23:50.927014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6773 19:23:50.927487 ==
6774 19:23:50.927860 RX Vref Scan: 1
6775 19:23:50.930019
6776 19:23:50.930478 RX Vref 0 -> 0, step: 1
6777 19:23:50.930848
6778 19:23:50.933815 RX Delay -327 -> 252, step: 8
6779 19:23:50.934370
6780 19:23:50.936784 Set Vref, RX VrefLevel [Byte0]: 51
6781 19:23:50.940098 [Byte1]: 52
6782 19:23:50.944243
6783 19:23:50.944710 Final RX Vref Byte 0 = 51 to rank0
6784 19:23:50.947682 Final RX Vref Byte 1 = 52 to rank0
6785 19:23:50.951334 Final RX Vref Byte 0 = 51 to rank1
6786 19:23:50.954217 Final RX Vref Byte 1 = 52 to rank1==
6787 19:23:50.957674 Dram Type= 6, Freq= 0, CH_1, rank 0
6788 19:23:50.964085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6789 19:23:50.964635 ==
6790 19:23:50.965005 DQS Delay:
6791 19:23:50.967842 DQS0 = 32, DQS1 = 40
6792 19:23:50.968401 DQM Delay:
6793 19:23:50.968774 DQM0 = 12, DQM1 = 13
6794 19:23:50.970905 DQ Delay:
6795 19:23:50.974236 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6796 19:23:50.974779 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6797 19:23:50.977367 DQ8 =4, DQ9 =0, DQ10 =20, DQ11 =4
6798 19:23:50.980667 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6799 19:23:50.981136
6800 19:23:50.984229
6801 19:23:50.990437 [DQSOSCAuto] RK0, (LSB)MR18= 0x97d3, (MSB)MR19= 0xc0c, tDQSOscB0 = 383 ps tDQSOscB1 = 390 ps
6802 19:23:50.994222 CH1 RK0: MR19=C0C, MR18=97D3
6803 19:23:51.001071 CH1_RK0: MR19=0xC0C, MR18=0x97D3, DQSOSC=383, MR23=63, INC=402, DEC=268
6804 19:23:51.001691 ==
6805 19:23:51.004007 Dram Type= 6, Freq= 0, CH_1, rank 1
6806 19:23:51.007097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6807 19:23:51.007569 ==
6808 19:23:51.010959 [Gating] SW mode calibration
6809 19:23:51.017498 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6810 19:23:51.023647 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6811 19:23:51.027278 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6812 19:23:51.030368 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6813 19:23:51.037735 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6814 19:23:51.040999 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6815 19:23:51.043992 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6816 19:23:51.047309 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6817 19:23:51.053912 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6818 19:23:51.057530 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6819 19:23:51.060864 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6820 19:23:51.063862 Total UI for P1: 0, mck2ui 16
6821 19:23:51.067300 best dqsien dly found for B0: ( 0, 14, 24)
6822 19:23:51.070295 Total UI for P1: 0, mck2ui 16
6823 19:23:51.073944 best dqsien dly found for B1: ( 0, 14, 24)
6824 19:23:51.077416 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6825 19:23:51.080302 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6826 19:23:51.084234
6827 19:23:51.087080 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6828 19:23:51.090661 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6829 19:23:51.094212 [Gating] SW calibration Done
6830 19:23:51.094771 ==
6831 19:23:51.096881 Dram Type= 6, Freq= 0, CH_1, rank 1
6832 19:23:51.100237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6833 19:23:51.100704 ==
6834 19:23:51.101071 RX Vref Scan: 0
6835 19:23:51.101447
6836 19:23:51.103768 RX Vref 0 -> 0, step: 1
6837 19:23:51.104244
6838 19:23:51.107334 RX Delay -410 -> 252, step: 16
6839 19:23:51.110554 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6840 19:23:51.117270 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6841 19:23:51.120613 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6842 19:23:51.124026 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6843 19:23:51.127339 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6844 19:23:51.133816 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6845 19:23:51.137335 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6846 19:23:51.140702 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6847 19:23:51.143721 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6848 19:23:51.150593 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6849 19:23:51.153997 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6850 19:23:51.157478 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6851 19:23:51.160469 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6852 19:23:51.167049 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6853 19:23:51.170014 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6854 19:23:51.173984 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6855 19:23:51.174548 ==
6856 19:23:51.177337 Dram Type= 6, Freq= 0, CH_1, rank 1
6857 19:23:51.180372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6858 19:23:51.183642 ==
6859 19:23:51.184107 DQS Delay:
6860 19:23:51.184471 DQS0 = 35, DQS1 = 43
6861 19:23:51.186844 DQM Delay:
6862 19:23:51.187368 DQM0 = 17, DQM1 = 18
6863 19:23:51.190750 DQ Delay:
6864 19:23:51.191311 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6865 19:23:51.193815 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =16
6866 19:23:51.197551 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6867 19:23:51.200278 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =32
6868 19:23:51.200756
6869 19:23:51.201122
6870 19:23:51.203827 ==
6871 19:23:51.206916 Dram Type= 6, Freq= 0, CH_1, rank 1
6872 19:23:51.210659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6873 19:23:51.211218 ==
6874 19:23:51.211588
6875 19:23:51.211927
6876 19:23:51.213264 TX Vref Scan disable
6877 19:23:51.213764 == TX Byte 0 ==
6878 19:23:51.216984 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6879 19:23:51.223712 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6880 19:23:51.224275 == TX Byte 1 ==
6881 19:23:51.226680 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6882 19:23:51.233529 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6883 19:23:51.234083 ==
6884 19:23:51.237096 Dram Type= 6, Freq= 0, CH_1, rank 1
6885 19:23:51.240668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6886 19:23:51.241231 ==
6887 19:23:51.241658
6888 19:23:51.242001
6889 19:23:51.243682 TX Vref Scan disable
6890 19:23:51.244154 == TX Byte 0 ==
6891 19:23:51.246821 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6892 19:23:51.253364 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6893 19:23:51.254017 == TX Byte 1 ==
6894 19:23:51.256659 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6895 19:23:51.263673 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6896 19:23:51.264303
6897 19:23:51.264669 [DATLAT]
6898 19:23:51.265003 Freq=400, CH1 RK1
6899 19:23:51.265362
6900 19:23:51.266595 DATLAT Default: 0xe
6901 19:23:51.269809 0, 0xFFFF, sum = 0
6902 19:23:51.270320 1, 0xFFFF, sum = 0
6903 19:23:51.273187 2, 0xFFFF, sum = 0
6904 19:23:51.273702 3, 0xFFFF, sum = 0
6905 19:23:51.276817 4, 0xFFFF, sum = 0
6906 19:23:51.277428 5, 0xFFFF, sum = 0
6907 19:23:51.280112 6, 0xFFFF, sum = 0
6908 19:23:51.280576 7, 0xFFFF, sum = 0
6909 19:23:51.283614 8, 0xFFFF, sum = 0
6910 19:23:51.284176 9, 0xFFFF, sum = 0
6911 19:23:51.286464 10, 0xFFFF, sum = 0
6912 19:23:51.286929 11, 0xFFFF, sum = 0
6913 19:23:51.289732 12, 0xFFFF, sum = 0
6914 19:23:51.290195 13, 0x0, sum = 1
6915 19:23:51.293341 14, 0x0, sum = 2
6916 19:23:51.293984 15, 0x0, sum = 3
6917 19:23:51.296310 16, 0x0, sum = 4
6918 19:23:51.296908 best_step = 14
6919 19:23:51.297289
6920 19:23:51.297688 ==
6921 19:23:51.299666 Dram Type= 6, Freq= 0, CH_1, rank 1
6922 19:23:51.303107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6923 19:23:51.306569 ==
6924 19:23:51.306984 RX Vref Scan: 0
6925 19:23:51.307330
6926 19:23:51.309594 RX Vref 0 -> 0, step: 1
6927 19:23:51.310008
6928 19:23:51.313369 RX Delay -327 -> 252, step: 8
6929 19:23:51.316607 iDelay=217, Bit 0, Center -16 (-231 ~ 200) 432
6930 19:23:51.323527 iDelay=217, Bit 1, Center -24 (-239 ~ 192) 432
6931 19:23:51.326747 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6932 19:23:51.329663 iDelay=217, Bit 3, Center -20 (-247 ~ 208) 456
6933 19:23:51.333162 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6934 19:23:51.339811 iDelay=217, Bit 5, Center -12 (-239 ~ 216) 456
6935 19:23:51.342984 iDelay=217, Bit 6, Center -16 (-239 ~ 208) 448
6936 19:23:51.346187 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
6937 19:23:51.349988 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6938 19:23:51.356670 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6939 19:23:51.359582 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
6940 19:23:51.363027 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6941 19:23:51.366188 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6942 19:23:51.372987 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
6943 19:23:51.376533 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6944 19:23:51.379938 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6945 19:23:51.380511 ==
6946 19:23:51.382621 Dram Type= 6, Freq= 0, CH_1, rank 1
6947 19:23:51.389600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6948 19:23:51.390173 ==
6949 19:23:51.390543 DQS Delay:
6950 19:23:51.392847 DQS0 = 32, DQS1 = 36
6951 19:23:51.393466 DQM Delay:
6952 19:23:51.393846 DQM0 = 12, DQM1 = 12
6953 19:23:51.396545 DQ Delay:
6954 19:23:51.399531 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6955 19:23:51.403223 DQ4 =16, DQ5 =20, DQ6 =16, DQ7 =12
6956 19:23:51.403689 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =8
6957 19:23:51.406487 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =24
6958 19:23:51.409668
6959 19:23:51.410224
6960 19:23:51.416597 [DQSOSCAuto] RK1, (LSB)MR18= 0xa751, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 389 ps
6961 19:23:51.419619 CH1 RK1: MR19=C0C, MR18=A751
6962 19:23:51.426404 CH1_RK1: MR19=0xC0C, MR18=0xA751, DQSOSC=389, MR23=63, INC=390, DEC=260
6963 19:23:51.429760 [RxdqsGatingPostProcess] freq 400
6964 19:23:51.432916 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6965 19:23:51.436124 best DQS0 dly(2T, 0.5T) = (0, 10)
6966 19:23:51.439593 best DQS1 dly(2T, 0.5T) = (0, 10)
6967 19:23:51.442905 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6968 19:23:51.446483 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6969 19:23:51.449355 best DQS0 dly(2T, 0.5T) = (0, 10)
6970 19:23:51.453258 best DQS1 dly(2T, 0.5T) = (0, 10)
6971 19:23:51.456917 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6972 19:23:51.459841 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6973 19:23:51.462973 Pre-setting of DQS Precalculation
6974 19:23:51.466196 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6975 19:23:51.473020 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6976 19:23:51.483152 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6977 19:23:51.483730
6978 19:23:51.484157
6979 19:23:51.484504 [Calibration Summary] 800 Mbps
6980 19:23:51.486142 CH 0, Rank 0
6981 19:23:51.486609 SW Impedance : PASS
6982 19:23:51.489547 DUTY Scan : NO K
6983 19:23:51.493011 ZQ Calibration : PASS
6984 19:23:51.493598 Jitter Meter : NO K
6985 19:23:51.496772 CBT Training : PASS
6986 19:23:51.499607 Write leveling : PASS
6987 19:23:51.500165 RX DQS gating : PASS
6988 19:23:51.502857 RX DQ/DQS(RDDQC) : PASS
6989 19:23:51.506319 TX DQ/DQS : PASS
6990 19:23:51.506786 RX DATLAT : PASS
6991 19:23:51.509551 RX DQ/DQS(Engine): PASS
6992 19:23:51.513363 TX OE : NO K
6993 19:23:51.513928 All Pass.
6994 19:23:51.514301
6995 19:23:51.514646 CH 0, Rank 1
6996 19:23:51.516721 SW Impedance : PASS
6997 19:23:51.519584 DUTY Scan : NO K
6998 19:23:51.520143 ZQ Calibration : PASS
6999 19:23:51.522896 Jitter Meter : NO K
7000 19:23:51.526265 CBT Training : PASS
7001 19:23:51.526824 Write leveling : NO K
7002 19:23:51.529481 RX DQS gating : PASS
7003 19:23:51.529950 RX DQ/DQS(RDDQC) : PASS
7004 19:23:51.533291 TX DQ/DQS : PASS
7005 19:23:51.536520 RX DATLAT : PASS
7006 19:23:51.537077 RX DQ/DQS(Engine): PASS
7007 19:23:51.539721 TX OE : NO K
7008 19:23:51.540288 All Pass.
7009 19:23:51.540659
7010 19:23:51.542703 CH 1, Rank 0
7011 19:23:51.543169 SW Impedance : PASS
7012 19:23:51.546195 DUTY Scan : NO K
7013 19:23:51.549918 ZQ Calibration : PASS
7014 19:23:51.550476 Jitter Meter : NO K
7015 19:23:51.553397 CBT Training : PASS
7016 19:23:51.555895 Write leveling : PASS
7017 19:23:51.556359 RX DQS gating : PASS
7018 19:23:51.559651 RX DQ/DQS(RDDQC) : PASS
7019 19:23:51.562698 TX DQ/DQS : PASS
7020 19:23:51.563260 RX DATLAT : PASS
7021 19:23:51.565836 RX DQ/DQS(Engine): PASS
7022 19:23:51.569169 TX OE : NO K
7023 19:23:51.569666 All Pass.
7024 19:23:51.570034
7025 19:23:51.570377 CH 1, Rank 1
7026 19:23:51.572802 SW Impedance : PASS
7027 19:23:51.576014 DUTY Scan : NO K
7028 19:23:51.576436 ZQ Calibration : PASS
7029 19:23:51.579200 Jitter Meter : NO K
7030 19:23:51.579625 CBT Training : PASS
7031 19:23:51.582543 Write leveling : NO K
7032 19:23:51.585786 RX DQS gating : PASS
7033 19:23:51.586209 RX DQ/DQS(RDDQC) : PASS
7034 19:23:51.589247 TX DQ/DQS : PASS
7035 19:23:51.592816 RX DATLAT : PASS
7036 19:23:51.593230 RX DQ/DQS(Engine): PASS
7037 19:23:51.595876 TX OE : NO K
7038 19:23:51.596293 All Pass.
7039 19:23:51.596619
7040 19:23:51.599024 DramC Write-DBI off
7041 19:23:51.602348 PER_BANK_REFRESH: Hybrid Mode
7042 19:23:51.602958 TX_TRACKING: ON
7043 19:23:51.612491 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7044 19:23:51.615225 [FAST_K] Save calibration result to emmc
7045 19:23:51.618723 dramc_set_vcore_voltage set vcore to 725000
7046 19:23:51.622011 Read voltage for 1600, 0
7047 19:23:51.622119 Vio18 = 0
7048 19:23:51.622221 Vcore = 725000
7049 19:23:51.625405 Vdram = 0
7050 19:23:51.625490 Vddq = 0
7051 19:23:51.625555 Vmddr = 0
7052 19:23:51.632428 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7053 19:23:51.635466 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7054 19:23:51.639095 MEM_TYPE=3, freq_sel=13
7055 19:23:51.642093 sv_algorithm_assistance_LP4_3733
7056 19:23:51.645646 ============ PULL DRAM RESETB DOWN ============
7057 19:23:51.648644 ========== PULL DRAM RESETB DOWN end =========
7058 19:23:51.655462 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7059 19:23:51.658854 ===================================
7060 19:23:51.662695 LPDDR4 DRAM CONFIGURATION
7061 19:23:51.663116 ===================================
7062 19:23:51.665989 EX_ROW_EN[0] = 0x0
7063 19:23:51.669230 EX_ROW_EN[1] = 0x0
7064 19:23:51.669676 LP4Y_EN = 0x0
7065 19:23:51.672193 WORK_FSP = 0x1
7066 19:23:51.672613 WL = 0x5
7067 19:23:51.675846 RL = 0x5
7068 19:23:51.676270 BL = 0x2
7069 19:23:51.678972 RPST = 0x0
7070 19:23:51.679394 RD_PRE = 0x0
7071 19:23:51.682232 WR_PRE = 0x1
7072 19:23:51.682654 WR_PST = 0x1
7073 19:23:51.685711 DBI_WR = 0x0
7074 19:23:51.686137 DBI_RD = 0x0
7075 19:23:51.689194 OTF = 0x1
7076 19:23:51.692370 ===================================
7077 19:23:51.695874 ===================================
7078 19:23:51.696296 ANA top config
7079 19:23:51.698976 ===================================
7080 19:23:51.702655 DLL_ASYNC_EN = 0
7081 19:23:51.705685 ALL_SLAVE_EN = 0
7082 19:23:51.708848 NEW_RANK_MODE = 1
7083 19:23:51.709279 DLL_IDLE_MODE = 1
7084 19:23:51.712509 LP45_APHY_COMB_EN = 1
7085 19:23:51.715823 TX_ODT_DIS = 0
7086 19:23:51.719076 NEW_8X_MODE = 1
7087 19:23:51.722610 ===================================
7088 19:23:51.725805 ===================================
7089 19:23:51.729199 data_rate = 3200
7090 19:23:51.729793 CKR = 1
7091 19:23:51.732080 DQ_P2S_RATIO = 8
7092 19:23:51.735583 ===================================
7093 19:23:51.739133 CA_P2S_RATIO = 8
7094 19:23:51.742441 DQ_CA_OPEN = 0
7095 19:23:51.745499 DQ_SEMI_OPEN = 0
7096 19:23:51.748875 CA_SEMI_OPEN = 0
7097 19:23:51.749381 CA_FULL_RATE = 0
7098 19:23:51.752175 DQ_CKDIV4_EN = 0
7099 19:23:51.755714 CA_CKDIV4_EN = 0
7100 19:23:51.759259 CA_PREDIV_EN = 0
7101 19:23:51.761939 PH8_DLY = 12
7102 19:23:51.765442 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7103 19:23:51.769093 DQ_AAMCK_DIV = 4
7104 19:23:51.769698 CA_AAMCK_DIV = 4
7105 19:23:51.772239 CA_ADMCK_DIV = 4
7106 19:23:51.775646 DQ_TRACK_CA_EN = 0
7107 19:23:51.778964 CA_PICK = 1600
7108 19:23:51.781981 CA_MCKIO = 1600
7109 19:23:51.785567 MCKIO_SEMI = 0
7110 19:23:51.788876 PLL_FREQ = 3068
7111 19:23:51.789475 DQ_UI_PI_RATIO = 32
7112 19:23:51.791823 CA_UI_PI_RATIO = 0
7113 19:23:51.795482 ===================================
7114 19:23:51.798527 ===================================
7115 19:23:51.801725 memory_type:LPDDR4
7116 19:23:51.805114 GP_NUM : 10
7117 19:23:51.805594 SRAM_EN : 1
7118 19:23:51.808360 MD32_EN : 0
7119 19:23:51.811754 ===================================
7120 19:23:51.812218 [ANA_INIT] >>>>>>>>>>>>>>
7121 19:23:51.814901 <<<<<< [CONFIGURE PHASE]: ANA_TX
7122 19:23:51.818525 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7123 19:23:51.821874 ===================================
7124 19:23:51.825179 data_rate = 3200,PCW = 0X7600
7125 19:23:51.828434 ===================================
7126 19:23:51.831942 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7127 19:23:51.838151 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7128 19:23:51.845073 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7129 19:23:51.848433 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7130 19:23:51.851746 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7131 19:23:51.854902 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7132 19:23:51.858142 [ANA_INIT] flow start
7133 19:23:51.858602 [ANA_INIT] PLL >>>>>>>>
7134 19:23:51.861915 [ANA_INIT] PLL <<<<<<<<
7135 19:23:51.865360 [ANA_INIT] MIDPI >>>>>>>>
7136 19:23:51.865918 [ANA_INIT] MIDPI <<<<<<<<
7137 19:23:51.868608 [ANA_INIT] DLL >>>>>>>>
7138 19:23:51.871333 [ANA_INIT] DLL <<<<<<<<
7139 19:23:51.871791 [ANA_INIT] flow end
7140 19:23:51.878657 ============ LP4 DIFF to SE enter ============
7141 19:23:51.881376 ============ LP4 DIFF to SE exit ============
7142 19:23:51.884921 [ANA_INIT] <<<<<<<<<<<<<
7143 19:23:51.888203 [Flow] Enable top DCM control >>>>>
7144 19:23:51.888765 [Flow] Enable top DCM control <<<<<
7145 19:23:51.891699 Enable DLL master slave shuffle
7146 19:23:51.898048 ==============================================================
7147 19:23:51.901500 Gating Mode config
7148 19:23:51.905080 ==============================================================
7149 19:23:51.907964 Config description:
7150 19:23:51.917870 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7151 19:23:51.925149 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7152 19:23:51.928151 SELPH_MODE 0: By rank 1: By Phase
7153 19:23:51.934615 ==============================================================
7154 19:23:51.938243 GAT_TRACK_EN = 1
7155 19:23:51.941853 RX_GATING_MODE = 2
7156 19:23:51.944832 RX_GATING_TRACK_MODE = 2
7157 19:23:51.945448 SELPH_MODE = 1
7158 19:23:51.948152 PICG_EARLY_EN = 1
7159 19:23:51.951791 VALID_LAT_VALUE = 1
7160 19:23:51.957982 ==============================================================
7161 19:23:51.961687 Enter into Gating configuration >>>>
7162 19:23:51.964615 Exit from Gating configuration <<<<
7163 19:23:51.968117 Enter into DVFS_PRE_config >>>>>
7164 19:23:51.978224 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7165 19:23:51.981366 Exit from DVFS_PRE_config <<<<<
7166 19:23:51.984500 Enter into PICG configuration >>>>
7167 19:23:51.987960 Exit from PICG configuration <<<<
7168 19:23:51.990965 [RX_INPUT] configuration >>>>>
7169 19:23:51.994417 [RX_INPUT] configuration <<<<<
7170 19:23:51.997667 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7171 19:23:52.004732 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7172 19:23:52.010972 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7173 19:23:52.017508 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7174 19:23:52.024686 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7175 19:23:52.027399 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7176 19:23:52.034461 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7177 19:23:52.037528 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7178 19:23:52.040699 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7179 19:23:52.044037 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7180 19:23:52.047433 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7181 19:23:52.054740 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7182 19:23:52.057683 ===================================
7183 19:23:52.061171 LPDDR4 DRAM CONFIGURATION
7184 19:23:52.064535 ===================================
7185 19:23:52.065095 EX_ROW_EN[0] = 0x0
7186 19:23:52.067624 EX_ROW_EN[1] = 0x0
7187 19:23:52.068248 LP4Y_EN = 0x0
7188 19:23:52.070703 WORK_FSP = 0x1
7189 19:23:52.071164 WL = 0x5
7190 19:23:52.074428 RL = 0x5
7191 19:23:52.074989 BL = 0x2
7192 19:23:52.077885 RPST = 0x0
7193 19:23:52.078441 RD_PRE = 0x0
7194 19:23:52.080800 WR_PRE = 0x1
7195 19:23:52.081385 WR_PST = 0x1
7196 19:23:52.084188 DBI_WR = 0x0
7197 19:23:52.084745 DBI_RD = 0x0
7198 19:23:52.087509 OTF = 0x1
7199 19:23:52.090822 ===================================
7200 19:23:52.093975 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7201 19:23:52.097267 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7202 19:23:52.104120 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7203 19:23:52.107204 ===================================
7204 19:23:52.107666 LPDDR4 DRAM CONFIGURATION
7205 19:23:52.110556 ===================================
7206 19:23:52.114214 EX_ROW_EN[0] = 0x10
7207 19:23:52.117447 EX_ROW_EN[1] = 0x0
7208 19:23:52.117997 LP4Y_EN = 0x0
7209 19:23:52.120647 WORK_FSP = 0x1
7210 19:23:52.121205 WL = 0x5
7211 19:23:52.124106 RL = 0x5
7212 19:23:52.124564 BL = 0x2
7213 19:23:52.127317 RPST = 0x0
7214 19:23:52.127776 RD_PRE = 0x0
7215 19:23:52.130436 WR_PRE = 0x1
7216 19:23:52.130894 WR_PST = 0x1
7217 19:23:52.134043 DBI_WR = 0x0
7218 19:23:52.134601 DBI_RD = 0x0
7219 19:23:52.137277 OTF = 0x1
7220 19:23:52.140599 ===================================
7221 19:23:52.147337 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7222 19:23:52.147907 ==
7223 19:23:52.150495 Dram Type= 6, Freq= 0, CH_0, rank 0
7224 19:23:52.154226 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7225 19:23:52.154786 ==
7226 19:23:52.157213 [Duty_Offset_Calibration]
7227 19:23:52.157815 B0:2 B1:0 CA:1
7228 19:23:52.158178
7229 19:23:52.160492 [DutyScan_Calibration_Flow] k_type=0
7230 19:23:52.170275
7231 19:23:52.170831 ==CLK 0==
7232 19:23:52.173890 Final CLK duty delay cell = -4
7233 19:23:52.177194 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7234 19:23:52.180763 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7235 19:23:52.184130 [-4] AVG Duty = 4922%(X100)
7236 19:23:52.184687
7237 19:23:52.187524 CH0 CLK Duty spec in!! Max-Min= 156%
7238 19:23:52.190272 [DutyScan_Calibration_Flow] ====Done====
7239 19:23:52.190835
7240 19:23:52.193423 [DutyScan_Calibration_Flow] k_type=1
7241 19:23:52.209830
7242 19:23:52.210514 ==DQS 0 ==
7243 19:23:52.212987 Final DQS duty delay cell = 0
7244 19:23:52.216137 [0] MAX Duty = 5249%(X100), DQS PI = 34
7245 19:23:52.219608 [0] MIN Duty = 4969%(X100), DQS PI = 0
7246 19:23:52.223459 [0] AVG Duty = 5109%(X100)
7247 19:23:52.224096
7248 19:23:52.224537 ==DQS 1 ==
7249 19:23:52.226077 Final DQS duty delay cell = -4
7250 19:23:52.229531 [-4] MAX Duty = 5094%(X100), DQS PI = 28
7251 19:23:52.232789 [-4] MIN Duty = 4875%(X100), DQS PI = 4
7252 19:23:52.236214 [-4] AVG Duty = 4984%(X100)
7253 19:23:52.236834
7254 19:23:52.239489 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7255 19:23:52.239953
7256 19:23:52.243019 CH0 DQS 1 Duty spec in!! Max-Min= 219%
7257 19:23:52.246415 [DutyScan_Calibration_Flow] ====Done====
7258 19:23:52.247023
7259 19:23:52.249704 [DutyScan_Calibration_Flow] k_type=3
7260 19:23:52.267211
7261 19:23:52.267655 ==DQM 0 ==
7262 19:23:52.270423 Final DQM duty delay cell = 0
7263 19:23:52.273712 [0] MAX Duty = 5062%(X100), DQS PI = 12
7264 19:23:52.277061 [0] MIN Duty = 4813%(X100), DQS PI = 50
7265 19:23:52.277586 [0] AVG Duty = 4937%(X100)
7266 19:23:52.280635
7267 19:23:52.281085 ==DQM 1 ==
7268 19:23:52.283708 Final DQM duty delay cell = 0
7269 19:23:52.287100 [0] MAX Duty = 5249%(X100), DQS PI = 28
7270 19:23:52.290326 [0] MIN Duty = 5000%(X100), DQS PI = 20
7271 19:23:52.293998 [0] AVG Duty = 5124%(X100)
7272 19:23:52.294437
7273 19:23:52.297149 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7274 19:23:52.297645
7275 19:23:52.300524 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7276 19:23:52.303773 [DutyScan_Calibration_Flow] ====Done====
7277 19:23:52.304221
7278 19:23:52.307098 [DutyScan_Calibration_Flow] k_type=2
7279 19:23:52.324269
7280 19:23:52.324727 ==DQ 0 ==
7281 19:23:52.327788 Final DQ duty delay cell = 0
7282 19:23:52.330761 [0] MAX Duty = 5124%(X100), DQS PI = 34
7283 19:23:52.334564 [0] MIN Duty = 5000%(X100), DQS PI = 0
7284 19:23:52.335009 [0] AVG Duty = 5062%(X100)
7285 19:23:52.335370
7286 19:23:52.337809 ==DQ 1 ==
7287 19:23:52.340684 Final DQ duty delay cell = 0
7288 19:23:52.344425 [0] MAX Duty = 4969%(X100), DQS PI = 44
7289 19:23:52.347491 [0] MIN Duty = 4875%(X100), DQS PI = 10
7290 19:23:52.347919 [0] AVG Duty = 4922%(X100)
7291 19:23:52.348434
7292 19:23:52.350719 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7293 19:23:52.354073
7294 19:23:52.357551 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7295 19:23:52.360796 [DutyScan_Calibration_Flow] ====Done====
7296 19:23:52.361287 ==
7297 19:23:52.363858 Dram Type= 6, Freq= 0, CH_1, rank 0
7298 19:23:52.367193 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7299 19:23:52.367689 ==
7300 19:23:52.370530 [Duty_Offset_Calibration]
7301 19:23:52.370870 B0:0 B1:-1 CA:2
7302 19:23:52.371175
7303 19:23:52.374018 [DutyScan_Calibration_Flow] k_type=0
7304 19:23:52.384427
7305 19:23:52.384641 ==CLK 0==
7306 19:23:52.387877 Final CLK duty delay cell = 0
7307 19:23:52.390744 [0] MAX Duty = 5156%(X100), DQS PI = 10
7308 19:23:52.394167 [0] MIN Duty = 4938%(X100), DQS PI = 44
7309 19:23:52.397698 [0] AVG Duty = 5047%(X100)
7310 19:23:52.397916
7311 19:23:52.400774 CH1 CLK Duty spec in!! Max-Min= 218%
7312 19:23:52.404288 [DutyScan_Calibration_Flow] ====Done====
7313 19:23:52.404506
7314 19:23:52.407496 [DutyScan_Calibration_Flow] k_type=1
7315 19:23:52.423834
7316 19:23:52.424119 ==DQS 0 ==
7317 19:23:52.427193 Final DQS duty delay cell = 0
7318 19:23:52.430742 [0] MAX Duty = 5093%(X100), DQS PI = 26
7319 19:23:52.434037 [0] MIN Duty = 4969%(X100), DQS PI = 4
7320 19:23:52.434445 [0] AVG Duty = 5031%(X100)
7321 19:23:52.437516
7322 19:23:52.437921 ==DQS 1 ==
7323 19:23:52.440883 Final DQS duty delay cell = 0
7324 19:23:52.444313 [0] MAX Duty = 5187%(X100), DQS PI = 0
7325 19:23:52.447423 [0] MIN Duty = 4844%(X100), DQS PI = 32
7326 19:23:52.447828 [0] AVG Duty = 5015%(X100)
7327 19:23:52.450674
7328 19:23:52.453929 CH1 DQS 0 Duty spec in!! Max-Min= 124%
7329 19:23:52.454334
7330 19:23:52.457584 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7331 19:23:52.460633 [DutyScan_Calibration_Flow] ====Done====
7332 19:23:52.461158
7333 19:23:52.464173 [DutyScan_Calibration_Flow] k_type=3
7334 19:23:52.481753
7335 19:23:52.482191 ==DQM 0 ==
7336 19:23:52.485455 Final DQM duty delay cell = 4
7337 19:23:52.488344 [4] MAX Duty = 5156%(X100), DQS PI = 24
7338 19:23:52.491898 [4] MIN Duty = 4969%(X100), DQS PI = 44
7339 19:23:52.495261 [4] AVG Duty = 5062%(X100)
7340 19:23:52.495665
7341 19:23:52.495980 ==DQM 1 ==
7342 19:23:52.498633 Final DQM duty delay cell = 0
7343 19:23:52.501776 [0] MAX Duty = 5281%(X100), DQS PI = 60
7344 19:23:52.505325 [0] MIN Duty = 4876%(X100), DQS PI = 34
7345 19:23:52.508156 [0] AVG Duty = 5078%(X100)
7346 19:23:52.508559
7347 19:23:52.511902 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7348 19:23:52.512306
7349 19:23:52.515212 CH1 DQM 1 Duty spec in!! Max-Min= 405%
7350 19:23:52.518365 [DutyScan_Calibration_Flow] ====Done====
7351 19:23:52.518769
7352 19:23:52.521668 [DutyScan_Calibration_Flow] k_type=2
7353 19:23:52.538840
7354 19:23:52.539255 ==DQ 0 ==
7355 19:23:52.542351 Final DQ duty delay cell = 0
7356 19:23:52.545397 [0] MAX Duty = 5062%(X100), DQS PI = 20
7357 19:23:52.548636 [0] MIN Duty = 4969%(X100), DQS PI = 2
7358 19:23:52.549048 [0] AVG Duty = 5015%(X100)
7359 19:23:52.552107
7360 19:23:52.552515 ==DQ 1 ==
7361 19:23:52.555475 Final DQ duty delay cell = 0
7362 19:23:52.558646 [0] MAX Duty = 5062%(X100), DQS PI = 0
7363 19:23:52.561899 [0] MIN Duty = 4813%(X100), DQS PI = 34
7364 19:23:52.562312 [0] AVG Duty = 4937%(X100)
7365 19:23:52.562638
7366 19:23:52.564982 CH1 DQ 0 Duty spec in!! Max-Min= 93%
7367 19:23:52.568671
7368 19:23:52.571832 CH1 DQ 1 Duty spec in!! Max-Min= 249%
7369 19:23:52.575266 [DutyScan_Calibration_Flow] ====Done====
7370 19:23:52.578449 nWR fixed to 30
7371 19:23:52.578862 [ModeRegInit_LP4] CH0 RK0
7372 19:23:52.581793 [ModeRegInit_LP4] CH0 RK1
7373 19:23:52.585275 [ModeRegInit_LP4] CH1 RK0
7374 19:23:52.585724 [ModeRegInit_LP4] CH1 RK1
7375 19:23:52.588283 match AC timing 5
7376 19:23:52.591790 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7377 19:23:52.595282 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7378 19:23:52.602069 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7379 19:23:52.605576 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7380 19:23:52.611625 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7381 19:23:52.612048 [MiockJmeterHQA]
7382 19:23:52.612379
7383 19:23:52.615416 [DramcMiockJmeter] u1RxGatingPI = 0
7384 19:23:52.618510 0 : 4253, 4027
7385 19:23:52.618940 4 : 4258, 4029
7386 19:23:52.619280 8 : 4368, 4140
7387 19:23:52.622154 12 : 4258, 4029
7388 19:23:52.622584 16 : 4368, 4140
7389 19:23:52.625384 20 : 4363, 4137
7390 19:23:52.625817 24 : 4255, 4027
7391 19:23:52.628672 28 : 4254, 4029
7392 19:23:52.629156 32 : 4252, 4027
7393 19:23:52.631551 36 : 4252, 4027
7394 19:23:52.631980 40 : 4255, 4029
7395 19:23:52.632394 44 : 4363, 4137
7396 19:23:52.634901 48 : 4250, 4026
7397 19:23:52.635339 52 : 4252, 4027
7398 19:23:52.638232 56 : 4249, 4027
7399 19:23:52.638662 60 : 4253, 4029
7400 19:23:52.641803 64 : 4253, 4029
7401 19:23:52.642228 68 : 4360, 4137
7402 19:23:52.642566 72 : 4361, 4137
7403 19:23:52.644768 76 : 4252, 4030
7404 19:23:52.645196 80 : 4250, 4026
7405 19:23:52.648067 84 : 4250, 4027
7406 19:23:52.648493 88 : 4249, 3409
7407 19:23:52.651639 92 : 4253, 0
7408 19:23:52.652067 96 : 4250, 0
7409 19:23:52.652404 100 : 4361, 0
7410 19:23:52.654650 104 : 4250, 0
7411 19:23:52.655079 108 : 4361, 0
7412 19:23:52.657915 112 : 4250, 0
7413 19:23:52.658345 116 : 4360, 0
7414 19:23:52.658688 120 : 4250, 0
7415 19:23:52.661268 124 : 4249, 0
7416 19:23:52.661753 128 : 4250, 0
7417 19:23:52.665078 132 : 4250, 0
7418 19:23:52.665554 136 : 4253, 0
7419 19:23:52.665913 140 : 4249, 0
7420 19:23:52.667994 144 : 4250, 0
7421 19:23:52.668421 148 : 4252, 0
7422 19:23:52.668763 152 : 4360, 0
7423 19:23:52.671406 156 : 4361, 0
7424 19:23:52.671834 160 : 4363, 0
7425 19:23:52.674655 164 : 4250, 0
7426 19:23:52.675086 168 : 4249, 0
7427 19:23:52.675430 172 : 4250, 0
7428 19:23:52.677769 176 : 4250, 0
7429 19:23:52.678200 180 : 4250, 0
7430 19:23:52.681423 184 : 4250, 0
7431 19:23:52.681849 188 : 4253, 0
7432 19:23:52.682193 192 : 4249, 0
7433 19:23:52.684954 196 : 4250, 0
7434 19:23:52.685409 200 : 4250, 37
7435 19:23:52.687940 204 : 4249, 3057
7436 19:23:52.688393 208 : 4250, 4026
7437 19:23:52.691425 212 : 4250, 4026
7438 19:23:52.691851 216 : 4250, 4027
7439 19:23:52.692209 220 : 4249, 4027
7440 19:23:52.694745 224 : 4360, 4137
7441 19:23:52.695174 228 : 4250, 4026
7442 19:23:52.697870 232 : 4250, 4027
7443 19:23:52.698363 236 : 4360, 4137
7444 19:23:52.701271 240 : 4249, 4027
7445 19:23:52.701740 244 : 4250, 4026
7446 19:23:52.704667 248 : 4361, 4137
7447 19:23:52.705097 252 : 4250, 4027
7448 19:23:52.707870 256 : 4249, 4027
7449 19:23:52.708326 260 : 4250, 4026
7450 19:23:52.711378 264 : 4253, 4029
7451 19:23:52.711843 268 : 4249, 4027
7452 19:23:52.714474 272 : 4249, 4027
7453 19:23:52.714903 276 : 4360, 4137
7454 19:23:52.715243 280 : 4250, 4026
7455 19:23:52.717766 284 : 4250, 4027
7456 19:23:52.718198 288 : 4361, 4137
7457 19:23:52.721230 292 : 4250, 4027
7458 19:23:52.721720 296 : 4250, 4026
7459 19:23:52.724441 300 : 4363, 4140
7460 19:23:52.724912 304 : 4249, 4027
7461 19:23:52.727888 308 : 4249, 4027
7462 19:23:52.728315 312 : 4250, 3767
7463 19:23:52.731302 316 : 4250, 1838
7464 19:23:52.731731
7465 19:23:52.732067 MIOCK jitter meter ch=0
7466 19:23:52.732454
7467 19:23:52.734568 1T = (316-92) = 224 dly cells
7468 19:23:52.741510 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7469 19:23:52.741999 ==
7470 19:23:52.744674 Dram Type= 6, Freq= 0, CH_0, rank 0
7471 19:23:52.747621 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7472 19:23:52.748034 ==
7473 19:23:52.754473 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7474 19:23:52.757840 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7475 19:23:52.761384 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7476 19:23:52.767628 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7477 19:23:52.777435 [CA 0] Center 43 (13~73) winsize 61
7478 19:23:52.780912 [CA 1] Center 43 (13~73) winsize 61
7479 19:23:52.784128 [CA 2] Center 38 (8~68) winsize 61
7480 19:23:52.787557 [CA 3] Center 37 (8~67) winsize 60
7481 19:23:52.790568 [CA 4] Center 36 (6~66) winsize 61
7482 19:23:52.793864 [CA 5] Center 35 (5~65) winsize 61
7483 19:23:52.794281
7484 19:23:52.797175 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7485 19:23:52.797612
7486 19:23:52.800662 [CATrainingPosCal] consider 1 rank data
7487 19:23:52.803891 u2DelayCellTimex100 = 290/100 ps
7488 19:23:52.807513 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7489 19:23:52.813956 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7490 19:23:52.817264 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7491 19:23:52.820702 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7492 19:23:52.824159 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7493 19:23:52.827254 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7494 19:23:52.827670
7495 19:23:52.830608 CA PerBit enable=1, Macro0, CA PI delay=35
7496 19:23:52.831024
7497 19:23:52.833963 [CBTSetCACLKResult] CA Dly = 35
7498 19:23:52.837149 CS Dly: 9 (0~40)
7499 19:23:52.840365 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7500 19:23:52.843702 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7501 19:23:52.844100 ==
7502 19:23:52.846997 Dram Type= 6, Freq= 0, CH_0, rank 1
7503 19:23:52.850320 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7504 19:23:52.853878 ==
7505 19:23:52.857253 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7506 19:23:52.860267 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7507 19:23:52.867258 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7508 19:23:52.870311 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7509 19:23:52.880380 [CA 0] Center 43 (13~73) winsize 61
7510 19:23:52.883780 [CA 1] Center 43 (13~73) winsize 61
7511 19:23:52.887162 [CA 2] Center 38 (9~68) winsize 60
7512 19:23:52.890589 [CA 3] Center 38 (8~68) winsize 61
7513 19:23:52.893985 [CA 4] Center 37 (7~67) winsize 61
7514 19:23:52.897162 [CA 5] Center 36 (6~66) winsize 61
7515 19:23:52.897261
7516 19:23:52.900230 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7517 19:23:52.900304
7518 19:23:52.903683 [CATrainingPosCal] consider 2 rank data
7519 19:23:52.907081 u2DelayCellTimex100 = 290/100 ps
7520 19:23:52.910117 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7521 19:23:52.916956 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7522 19:23:52.920335 CA2 delay=38 (9~68),Diff = 3 PI (10 cell)
7523 19:23:52.923721 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7524 19:23:52.927131 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7525 19:23:52.930372 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7526 19:23:52.930442
7527 19:23:52.933743 CA PerBit enable=1, Macro0, CA PI delay=35
7528 19:23:52.933812
7529 19:23:52.937070 [CBTSetCACLKResult] CA Dly = 35
7530 19:23:52.940385 CS Dly: 11 (0~44)
7531 19:23:52.943776 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7532 19:23:52.946947 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7533 19:23:52.947015
7534 19:23:52.950455 ----->DramcWriteLeveling(PI) begin...
7535 19:23:52.950526 ==
7536 19:23:52.954039 Dram Type= 6, Freq= 0, CH_0, rank 0
7537 19:23:52.956991 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7538 19:23:52.960568 ==
7539 19:23:52.960637 Write leveling (Byte 0): 37 => 37
7540 19:23:52.963436 Write leveling (Byte 1): 30 => 30
7541 19:23:52.966845 DramcWriteLeveling(PI) end<-----
7542 19:23:52.966912
7543 19:23:52.966972 ==
7544 19:23:52.970327 Dram Type= 6, Freq= 0, CH_0, rank 0
7545 19:23:52.976707 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7546 19:23:52.976777 ==
7547 19:23:52.976838 [Gating] SW mode calibration
7548 19:23:52.986751 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7549 19:23:52.990205 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7550 19:23:52.996946 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7551 19:23:53.000248 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7552 19:23:53.003613 1 4 8 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
7553 19:23:53.006774 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7554 19:23:53.013615 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7555 19:23:53.016749 1 4 20 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
7556 19:23:53.020160 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7557 19:23:53.026918 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7558 19:23:53.030243 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7559 19:23:53.033603 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7560 19:23:53.039867 1 5 8 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
7561 19:23:53.043256 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7562 19:23:53.046529 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7563 19:23:53.053370 1 5 20 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
7564 19:23:53.056462 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7565 19:23:53.059862 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7566 19:23:53.066254 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7567 19:23:53.069498 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7568 19:23:53.072958 1 6 8 | B1->B0 | 2323 3f3f | 0 1 | (0 0) (0 0)
7569 19:23:53.079642 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7570 19:23:53.083260 1 6 16 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
7571 19:23:53.086049 1 6 20 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
7572 19:23:53.092924 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7573 19:23:53.096300 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7574 19:23:53.099427 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7575 19:23:53.106055 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7576 19:23:53.109498 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7577 19:23:53.112670 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7578 19:23:53.119290 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7579 19:23:53.122552 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7580 19:23:53.125614 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7581 19:23:53.132378 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 19:23:53.135627 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 19:23:53.139275 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 19:23:53.145666 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 19:23:53.148941 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 19:23:53.152628 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 19:23:53.158954 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7588 19:23:53.162540 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7589 19:23:53.165793 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7590 19:23:53.172231 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7591 19:23:53.175583 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7592 19:23:53.179129 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7593 19:23:53.185615 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7594 19:23:53.188950 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7595 19:23:53.192312 Total UI for P1: 0, mck2ui 16
7596 19:23:53.195678 best dqsien dly found for B0: ( 1, 9, 10)
7597 19:23:53.199150 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7598 19:23:53.202569 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7599 19:23:53.205534 Total UI for P1: 0, mck2ui 16
7600 19:23:53.208823 best dqsien dly found for B1: ( 1, 9, 20)
7601 19:23:53.215799 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7602 19:23:53.218673 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7603 19:23:53.218756
7604 19:23:53.222104 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7605 19:23:53.225703 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7606 19:23:53.228745 [Gating] SW calibration Done
7607 19:23:53.228828 ==
7608 19:23:53.232190 Dram Type= 6, Freq= 0, CH_0, rank 0
7609 19:23:53.235249 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7610 19:23:53.235333 ==
7611 19:23:53.238953 RX Vref Scan: 0
7612 19:23:53.239035
7613 19:23:53.239099 RX Vref 0 -> 0, step: 1
7614 19:23:53.239159
7615 19:23:53.242152 RX Delay 0 -> 252, step: 8
7616 19:23:53.245165 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7617 19:23:53.248512 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7618 19:23:53.255233 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7619 19:23:53.258628 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7620 19:23:53.262047 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7621 19:23:53.265476 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7622 19:23:53.268441 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7623 19:23:53.275479 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7624 19:23:53.278512 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7625 19:23:53.281992 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7626 19:23:53.285437 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7627 19:23:53.288405 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
7628 19:23:53.294988 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7629 19:23:53.298614 iDelay=200, Bit 13, Center 131 (88 ~ 175) 88
7630 19:23:53.302051 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7631 19:23:53.305058 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7632 19:23:53.305140 ==
7633 19:23:53.308455 Dram Type= 6, Freq= 0, CH_0, rank 0
7634 19:23:53.314869 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7635 19:23:53.314953 ==
7636 19:23:53.315018 DQS Delay:
7637 19:23:53.318236 DQS0 = 0, DQS1 = 0
7638 19:23:53.318341 DQM Delay:
7639 19:23:53.318409 DQM0 = 137, DQM1 = 127
7640 19:23:53.321415 DQ Delay:
7641 19:23:53.325012 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
7642 19:23:53.328141 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =147
7643 19:23:53.331735 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =127
7644 19:23:53.334876 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7645 19:23:53.334959
7646 19:23:53.335024
7647 19:23:53.335082 ==
7648 19:23:53.338407 Dram Type= 6, Freq= 0, CH_0, rank 0
7649 19:23:53.341512 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7650 19:23:53.345081 ==
7651 19:23:53.345191
7652 19:23:53.345284
7653 19:23:53.345389 TX Vref Scan disable
7654 19:23:53.348375 == TX Byte 0 ==
7655 19:23:53.351379 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7656 19:23:53.354725 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7657 19:23:53.358569 == TX Byte 1 ==
7658 19:23:53.361458 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7659 19:23:53.364976 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7660 19:23:53.365059 ==
7661 19:23:53.368363 Dram Type= 6, Freq= 0, CH_0, rank 0
7662 19:23:53.374711 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7663 19:23:53.374795 ==
7664 19:23:53.387585
7665 19:23:53.390405 TX Vref early break, caculate TX vref
7666 19:23:53.393773 TX Vref=16, minBit 0, minWin=23, winSum=378
7667 19:23:53.397255 TX Vref=18, minBit 7, minWin=23, winSum=389
7668 19:23:53.400751 TX Vref=20, minBit 6, minWin=23, winSum=396
7669 19:23:53.404211 TX Vref=22, minBit 7, minWin=24, winSum=408
7670 19:23:53.407089 TX Vref=24, minBit 2, minWin=25, winSum=421
7671 19:23:53.414050 TX Vref=26, minBit 12, minWin=25, winSum=427
7672 19:23:53.417074 TX Vref=28, minBit 2, minWin=25, winSum=426
7673 19:23:53.420476 TX Vref=30, minBit 0, minWin=25, winSum=417
7674 19:23:53.423661 TX Vref=32, minBit 0, minWin=25, winSum=412
7675 19:23:53.427215 TX Vref=34, minBit 2, minWin=24, winSum=400
7676 19:23:53.433807 [TxChooseVref] Worse bit 12, Min win 25, Win sum 427, Final Vref 26
7677 19:23:53.433889
7678 19:23:53.436860 Final TX Range 0 Vref 26
7679 19:23:53.436943
7680 19:23:53.437007 ==
7681 19:23:53.440693 Dram Type= 6, Freq= 0, CH_0, rank 0
7682 19:23:53.443637 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7683 19:23:53.443721 ==
7684 19:23:53.443788
7685 19:23:53.443850
7686 19:23:53.447274 TX Vref Scan disable
7687 19:23:53.453679 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7688 19:23:53.453761 == TX Byte 0 ==
7689 19:23:53.456746 u2DelayCellOfst[0]=10 cells (3 PI)
7690 19:23:53.460254 u2DelayCellOfst[1]=13 cells (4 PI)
7691 19:23:53.463975 u2DelayCellOfst[2]=10 cells (3 PI)
7692 19:23:53.466814 u2DelayCellOfst[3]=10 cells (3 PI)
7693 19:23:53.470214 u2DelayCellOfst[4]=6 cells (2 PI)
7694 19:23:53.473669 u2DelayCellOfst[5]=0 cells (0 PI)
7695 19:23:53.477020 u2DelayCellOfst[6]=16 cells (5 PI)
7696 19:23:53.479962 u2DelayCellOfst[7]=13 cells (4 PI)
7697 19:23:53.483394 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7698 19:23:53.486869 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7699 19:23:53.490419 == TX Byte 1 ==
7700 19:23:53.493231 u2DelayCellOfst[8]=0 cells (0 PI)
7701 19:23:53.493336 u2DelayCellOfst[9]=0 cells (0 PI)
7702 19:23:53.496640 u2DelayCellOfst[10]=6 cells (2 PI)
7703 19:23:53.500285 u2DelayCellOfst[11]=3 cells (1 PI)
7704 19:23:53.503537 u2DelayCellOfst[12]=13 cells (4 PI)
7705 19:23:53.506993 u2DelayCellOfst[13]=10 cells (3 PI)
7706 19:23:53.509955 u2DelayCellOfst[14]=13 cells (4 PI)
7707 19:23:53.513662 u2DelayCellOfst[15]=10 cells (3 PI)
7708 19:23:53.516951 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7709 19:23:53.523493 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7710 19:23:53.523576 DramC Write-DBI on
7711 19:23:53.523642 ==
7712 19:23:53.526966 Dram Type= 6, Freq= 0, CH_0, rank 0
7713 19:23:53.530155 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7714 19:23:53.533547 ==
7715 19:23:53.533629
7716 19:23:53.533694
7717 19:23:53.533753 TX Vref Scan disable
7718 19:23:53.537153 == TX Byte 0 ==
7719 19:23:53.540180 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7720 19:23:53.543541 == TX Byte 1 ==
7721 19:23:53.546898 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7722 19:23:53.550523 DramC Write-DBI off
7723 19:23:53.550598
7724 19:23:53.550666 [DATLAT]
7725 19:23:53.550724 Freq=1600, CH0 RK0
7726 19:23:53.550783
7727 19:23:53.553446 DATLAT Default: 0xf
7728 19:23:53.553514 0, 0xFFFF, sum = 0
7729 19:23:53.556919 1, 0xFFFF, sum = 0
7730 19:23:53.557000 2, 0xFFFF, sum = 0
7731 19:23:53.560159 3, 0xFFFF, sum = 0
7732 19:23:53.563415 4, 0xFFFF, sum = 0
7733 19:23:53.563493 5, 0xFFFF, sum = 0
7734 19:23:53.566812 6, 0xFFFF, sum = 0
7735 19:23:53.566885 7, 0xFFFF, sum = 0
7736 19:23:53.570233 8, 0xFFFF, sum = 0
7737 19:23:53.570310 9, 0xFFFF, sum = 0
7738 19:23:53.573521 10, 0xFFFF, sum = 0
7739 19:23:53.573594 11, 0xFFFF, sum = 0
7740 19:23:53.576891 12, 0xFFFF, sum = 0
7741 19:23:53.576964 13, 0xFFFF, sum = 0
7742 19:23:53.579966 14, 0x0, sum = 1
7743 19:23:53.580040 15, 0x0, sum = 2
7744 19:23:53.583395 16, 0x0, sum = 3
7745 19:23:53.583470 17, 0x0, sum = 4
7746 19:23:53.587018 best_step = 15
7747 19:23:53.587086
7748 19:23:53.587146 ==
7749 19:23:53.589900 Dram Type= 6, Freq= 0, CH_0, rank 0
7750 19:23:53.593282 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7751 19:23:53.593365 ==
7752 19:23:53.596678 RX Vref Scan: 1
7753 19:23:53.596745
7754 19:23:53.596804 Set Vref Range= 24 -> 127
7755 19:23:53.596862
7756 19:23:53.600080 RX Vref 24 -> 127, step: 1
7757 19:23:53.600150
7758 19:23:53.603614 RX Delay 19 -> 252, step: 4
7759 19:23:53.603686
7760 19:23:53.606998 Set Vref, RX VrefLevel [Byte0]: 24
7761 19:23:53.610041 [Byte1]: 24
7762 19:23:53.610113
7763 19:23:53.613484 Set Vref, RX VrefLevel [Byte0]: 25
7764 19:23:53.616714 [Byte1]: 25
7765 19:23:53.616785
7766 19:23:53.620211 Set Vref, RX VrefLevel [Byte0]: 26
7767 19:23:53.623496 [Byte1]: 26
7768 19:23:53.627490
7769 19:23:53.627564 Set Vref, RX VrefLevel [Byte0]: 27
7770 19:23:53.631025 [Byte1]: 27
7771 19:23:53.634818
7772 19:23:53.634890 Set Vref, RX VrefLevel [Byte0]: 28
7773 19:23:53.638240 [Byte1]: 28
7774 19:23:53.642449
7775 19:23:53.642525 Set Vref, RX VrefLevel [Byte0]: 29
7776 19:23:53.645533 [Byte1]: 29
7777 19:23:53.649997
7778 19:23:53.650078 Set Vref, RX VrefLevel [Byte0]: 30
7779 19:23:53.653603 [Byte1]: 30
7780 19:23:53.657533
7781 19:23:53.657614 Set Vref, RX VrefLevel [Byte0]: 31
7782 19:23:53.660881 [Byte1]: 31
7783 19:23:53.665025
7784 19:23:53.665106 Set Vref, RX VrefLevel [Byte0]: 32
7785 19:23:53.668540 [Byte1]: 32
7786 19:23:53.672968
7787 19:23:53.673049 Set Vref, RX VrefLevel [Byte0]: 33
7788 19:23:53.676035 [Byte1]: 33
7789 19:23:53.680053
7790 19:23:53.680134 Set Vref, RX VrefLevel [Byte0]: 34
7791 19:23:53.683396 [Byte1]: 34
7792 19:23:53.687776
7793 19:23:53.687849 Set Vref, RX VrefLevel [Byte0]: 35
7794 19:23:53.691225 [Byte1]: 35
7795 19:23:53.695554
7796 19:23:53.695636 Set Vref, RX VrefLevel [Byte0]: 36
7797 19:23:53.698523 [Byte1]: 36
7798 19:23:53.703000
7799 19:23:53.703082 Set Vref, RX VrefLevel [Byte0]: 37
7800 19:23:53.706350 [Byte1]: 37
7801 19:23:53.710658
7802 19:23:53.710760 Set Vref, RX VrefLevel [Byte0]: 38
7803 19:23:53.714225 [Byte1]: 38
7804 19:23:53.718170
7805 19:23:53.718254 Set Vref, RX VrefLevel [Byte0]: 39
7806 19:23:53.721541 [Byte1]: 39
7807 19:23:53.725711
7808 19:23:53.725792 Set Vref, RX VrefLevel [Byte0]: 40
7809 19:23:53.729148 [Byte1]: 40
7810 19:23:53.733448
7811 19:23:53.733529 Set Vref, RX VrefLevel [Byte0]: 41
7812 19:23:53.736383 [Byte1]: 41
7813 19:23:53.740834
7814 19:23:53.740916 Set Vref, RX VrefLevel [Byte0]: 42
7815 19:23:53.743913 [Byte1]: 42
7816 19:23:53.748370
7817 19:23:53.748523 Set Vref, RX VrefLevel [Byte0]: 43
7818 19:23:53.751905 [Byte1]: 43
7819 19:23:53.755892
7820 19:23:53.755975 Set Vref, RX VrefLevel [Byte0]: 44
7821 19:23:53.759444 [Byte1]: 44
7822 19:23:53.763509
7823 19:23:53.763591 Set Vref, RX VrefLevel [Byte0]: 45
7824 19:23:53.766811 [Byte1]: 45
7825 19:23:53.771090
7826 19:23:53.771171 Set Vref, RX VrefLevel [Byte0]: 46
7827 19:23:53.774718 [Byte1]: 46
7828 19:23:53.778587
7829 19:23:53.778669 Set Vref, RX VrefLevel [Byte0]: 47
7830 19:23:53.781889 [Byte1]: 47
7831 19:23:53.786337
7832 19:23:53.786419 Set Vref, RX VrefLevel [Byte0]: 48
7833 19:23:53.789757 [Byte1]: 48
7834 19:23:53.793704
7835 19:23:53.793785 Set Vref, RX VrefLevel [Byte0]: 49
7836 19:23:53.797125 [Byte1]: 49
7837 19:23:53.801517
7838 19:23:53.801598 Set Vref, RX VrefLevel [Byte0]: 50
7839 19:23:53.804839 [Byte1]: 50
7840 19:23:53.808756
7841 19:23:53.808837 Set Vref, RX VrefLevel [Byte0]: 51
7842 19:23:53.812303 [Byte1]: 51
7843 19:23:53.816557
7844 19:23:53.816642 Set Vref, RX VrefLevel [Byte0]: 52
7845 19:23:53.819931 [Byte1]: 52
7846 19:23:53.823922
7847 19:23:53.824034 Set Vref, RX VrefLevel [Byte0]: 53
7848 19:23:53.827564 [Byte1]: 53
7849 19:23:53.831816
7850 19:23:53.831900 Set Vref, RX VrefLevel [Byte0]: 54
7851 19:23:53.835211 [Byte1]: 54
7852 19:23:53.838952
7853 19:23:53.839037 Set Vref, RX VrefLevel [Byte0]: 55
7854 19:23:53.842396 [Byte1]: 55
7855 19:23:53.846731
7856 19:23:53.846816 Set Vref, RX VrefLevel [Byte0]: 56
7857 19:23:53.850012 [Byte1]: 56
7858 19:23:53.854431
7859 19:23:53.854516 Set Vref, RX VrefLevel [Byte0]: 57
7860 19:23:53.857485 [Byte1]: 57
7861 19:23:53.861996
7862 19:23:53.862080 Set Vref, RX VrefLevel [Byte0]: 58
7863 19:23:53.865256 [Byte1]: 58
7864 19:23:53.869654
7865 19:23:53.869743 Set Vref, RX VrefLevel [Byte0]: 59
7866 19:23:53.873009 [Byte1]: 59
7867 19:23:53.877177
7868 19:23:53.877265 Set Vref, RX VrefLevel [Byte0]: 60
7869 19:23:53.880358 [Byte1]: 60
7870 19:23:53.885003
7871 19:23:53.885087 Set Vref, RX VrefLevel [Byte0]: 61
7872 19:23:53.887903 [Byte1]: 61
7873 19:23:53.892223
7874 19:23:53.892308 Set Vref, RX VrefLevel [Byte0]: 62
7875 19:23:53.895659 [Byte1]: 62
7876 19:23:53.900005
7877 19:23:53.900089 Set Vref, RX VrefLevel [Byte0]: 63
7878 19:23:53.903049 [Byte1]: 63
7879 19:23:53.907498
7880 19:23:53.907583 Set Vref, RX VrefLevel [Byte0]: 64
7881 19:23:53.910571 [Byte1]: 64
7882 19:23:53.914862
7883 19:23:53.914947 Set Vref, RX VrefLevel [Byte0]: 65
7884 19:23:53.918249 [Byte1]: 65
7885 19:23:53.922625
7886 19:23:53.922710 Set Vref, RX VrefLevel [Byte0]: 66
7887 19:23:53.926056 [Byte1]: 66
7888 19:23:53.930035
7889 19:23:53.930120 Set Vref, RX VrefLevel [Byte0]: 67
7890 19:23:53.933410 [Byte1]: 67
7891 19:23:53.937631
7892 19:23:53.937716 Set Vref, RX VrefLevel [Byte0]: 68
7893 19:23:53.940956 [Byte1]: 68
7894 19:23:53.945585
7895 19:23:53.945670 Set Vref, RX VrefLevel [Byte0]: 69
7896 19:23:53.948395 [Byte1]: 69
7897 19:23:53.952830
7898 19:23:53.952915 Set Vref, RX VrefLevel [Byte0]: 70
7899 19:23:53.955995 [Byte1]: 70
7900 19:23:53.960492
7901 19:23:53.960576 Set Vref, RX VrefLevel [Byte0]: 71
7902 19:23:53.963760 [Byte1]: 71
7903 19:23:53.968133
7904 19:23:53.968218 Set Vref, RX VrefLevel [Byte0]: 72
7905 19:23:53.971243 [Byte1]: 72
7906 19:23:53.975736
7907 19:23:53.975821 Set Vref, RX VrefLevel [Byte0]: 73
7908 19:23:53.978767 [Byte1]: 73
7909 19:23:53.983246
7910 19:23:53.983330 Set Vref, RX VrefLevel [Byte0]: 74
7911 19:23:53.986468 [Byte1]: 74
7912 19:23:53.990615
7913 19:23:53.990700 Set Vref, RX VrefLevel [Byte0]: 75
7914 19:23:53.994047 [Byte1]: 75
7915 19:23:53.998461
7916 19:23:53.998546 Set Vref, RX VrefLevel [Byte0]: 76
7917 19:23:54.001427 [Byte1]: 76
7918 19:23:54.005761
7919 19:23:54.005845 Set Vref, RX VrefLevel [Byte0]: 77
7920 19:23:54.009213 [Byte1]: 77
7921 19:23:54.013569
7922 19:23:54.013654 Set Vref, RX VrefLevel [Byte0]: 78
7923 19:23:54.016662 [Byte1]: 78
7924 19:23:54.020955
7925 19:23:54.021040 Set Vref, RX VrefLevel [Byte0]: 79
7926 19:23:54.024074 [Byte1]: 79
7927 19:23:54.028490
7928 19:23:54.028575 Set Vref, RX VrefLevel [Byte0]: 80
7929 19:23:54.032021 [Byte1]: 80
7930 19:23:54.035875
7931 19:23:54.035963 Final RX Vref Byte 0 = 59 to rank0
7932 19:23:54.039707 Final RX Vref Byte 1 = 62 to rank0
7933 19:23:54.042495 Final RX Vref Byte 0 = 59 to rank1
7934 19:23:54.045917 Final RX Vref Byte 1 = 62 to rank1==
7935 19:23:54.049424 Dram Type= 6, Freq= 0, CH_0, rank 0
7936 19:23:54.056194 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7937 19:23:54.056279 ==
7938 19:23:54.056365 DQS Delay:
7939 19:23:54.056445 DQS0 = 0, DQS1 = 0
7940 19:23:54.059526 DQM Delay:
7941 19:23:54.059610 DQM0 = 136, DQM1 = 124
7942 19:23:54.062799 DQ Delay:
7943 19:23:54.066087 DQ0 =136, DQ1 =138, DQ2 =132, DQ3 =132
7944 19:23:54.069144 DQ4 =140, DQ5 =124, DQ6 =142, DQ7 =144
7945 19:23:54.072745 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =118
7946 19:23:54.076048 DQ12 =128, DQ13 =128, DQ14 =134, DQ15 =134
7947 19:23:54.076134
7948 19:23:54.076219
7949 19:23:54.076299
7950 19:23:54.078982 [DramC_TX_OE_Calibration] TA2
7951 19:23:54.082215 Original DQ_B0 (3 6) =30, OEN = 27
7952 19:23:54.085611 Original DQ_B1 (3 6) =30, OEN = 27
7953 19:23:54.088974 24, 0x0, End_B0=24 End_B1=24
7954 19:23:54.089060 25, 0x0, End_B0=25 End_B1=25
7955 19:23:54.092354 26, 0x0, End_B0=26 End_B1=26
7956 19:23:54.095607 27, 0x0, End_B0=27 End_B1=27
7957 19:23:54.099029 28, 0x0, End_B0=28 End_B1=28
7958 19:23:54.102209 29, 0x0, End_B0=29 End_B1=29
7959 19:23:54.102295 30, 0x0, End_B0=30 End_B1=30
7960 19:23:54.105539 31, 0x5151, End_B0=30 End_B1=30
7961 19:23:54.108958 Byte0 end_step=30 best_step=27
7962 19:23:54.112489 Byte1 end_step=30 best_step=27
7963 19:23:54.115385 Byte0 TX OE(2T, 0.5T) = (3, 3)
7964 19:23:54.118889 Byte1 TX OE(2T, 0.5T) = (3, 3)
7965 19:23:54.118974
7966 19:23:54.119058
7967 19:23:54.125434 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
7968 19:23:54.128926 CH0 RK0: MR19=303, MR18=1E1C
7969 19:23:54.135320 CH0_RK0: MR19=0x303, MR18=0x1E1C, DQSOSC=394, MR23=63, INC=23, DEC=15
7970 19:23:54.135405
7971 19:23:54.138616 ----->DramcWriteLeveling(PI) begin...
7972 19:23:54.138701 ==
7973 19:23:54.141888 Dram Type= 6, Freq= 0, CH_0, rank 1
7974 19:23:54.145083 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7975 19:23:54.145168 ==
7976 19:23:54.148528 Write leveling (Byte 0): 37 => 37
7977 19:23:54.151894 Write leveling (Byte 1): 30 => 30
7978 19:23:54.155269 DramcWriteLeveling(PI) end<-----
7979 19:23:54.155355
7980 19:23:54.155440 ==
7981 19:23:54.158713 Dram Type= 6, Freq= 0, CH_0, rank 1
7982 19:23:54.162104 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7983 19:23:54.162189 ==
7984 19:23:54.165446 [Gating] SW mode calibration
7985 19:23:54.171949 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7986 19:23:54.178618 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7987 19:23:54.181823 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7988 19:23:54.188710 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7989 19:23:54.191889 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7990 19:23:54.195060 1 4 12 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
7991 19:23:54.201971 1 4 16 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
7992 19:23:54.204857 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7993 19:23:54.208488 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7994 19:23:54.214752 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7995 19:23:54.218124 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7996 19:23:54.221609 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7997 19:23:54.228036 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7998 19:23:54.231466 1 5 12 | B1->B0 | 3434 2c2c | 1 1 | (1 1) (1 0)
7999 19:23:54.234965 1 5 16 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
8000 19:23:54.238296 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8001 19:23:54.244612 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8002 19:23:54.247866 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8003 19:23:54.251353 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8004 19:23:54.258251 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8005 19:23:54.261177 1 6 8 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
8006 19:23:54.264679 1 6 12 | B1->B0 | 2a2a 4141 | 0 0 | (0 0) (1 1)
8007 19:23:54.271297 1 6 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8008 19:23:54.274775 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8009 19:23:54.278127 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8010 19:23:54.284782 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8011 19:23:54.288107 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8012 19:23:54.291229 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8013 19:23:54.297818 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8014 19:23:54.301138 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8015 19:23:54.304513 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8016 19:23:54.311046 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8017 19:23:54.314706 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8018 19:23:54.317715 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8019 19:23:54.324478 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8020 19:23:54.327482 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8021 19:23:54.330884 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8022 19:23:54.337995 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8023 19:23:54.341020 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8024 19:23:54.344597 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8025 19:23:54.350934 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8026 19:23:54.354581 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8027 19:23:54.357967 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8028 19:23:54.364412 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8029 19:23:54.367832 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8030 19:23:54.371339 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8031 19:23:54.377505 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8032 19:23:54.377587 Total UI for P1: 0, mck2ui 16
8033 19:23:54.381019 best dqsien dly found for B0: ( 1, 9, 12)
8034 19:23:54.387635 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8035 19:23:54.390792 Total UI for P1: 0, mck2ui 16
8036 19:23:54.394589 best dqsien dly found for B1: ( 1, 9, 14)
8037 19:23:54.397436 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8038 19:23:54.400976 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8039 19:23:54.401059
8040 19:23:54.404103 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8041 19:23:54.407693 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8042 19:23:54.411061 [Gating] SW calibration Done
8043 19:23:54.411144 ==
8044 19:23:54.414519 Dram Type= 6, Freq= 0, CH_0, rank 1
8045 19:23:54.417586 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8046 19:23:54.417670 ==
8047 19:23:54.420732 RX Vref Scan: 0
8048 19:23:54.420829
8049 19:23:54.424296 RX Vref 0 -> 0, step: 1
8050 19:23:54.424379
8051 19:23:54.424460 RX Delay 0 -> 252, step: 8
8052 19:23:54.431177 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8053 19:23:54.433991 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8054 19:23:54.437504 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8055 19:23:54.440995 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8056 19:23:54.443937 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8057 19:23:54.450623 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8058 19:23:54.454039 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8059 19:23:54.457286 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8060 19:23:54.460734 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8061 19:23:54.464145 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8062 19:23:54.467646 iDelay=200, Bit 10, Center 127 (80 ~ 175) 96
8063 19:23:54.473974 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8064 19:23:54.477547 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
8065 19:23:54.480460 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8066 19:23:54.484060 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8067 19:23:54.490534 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8068 19:23:54.490616 ==
8069 19:23:54.494037 Dram Type= 6, Freq= 0, CH_0, rank 1
8070 19:23:54.497222 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8071 19:23:54.497351 ==
8072 19:23:54.497418 DQS Delay:
8073 19:23:54.500350 DQS0 = 0, DQS1 = 0
8074 19:23:54.500432 DQM Delay:
8075 19:23:54.504197 DQM0 = 136, DQM1 = 126
8076 19:23:54.504280 DQ Delay:
8077 19:23:54.506974 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =131
8078 19:23:54.510634 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8079 19:23:54.514079 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =123
8080 19:23:54.516873 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
8081 19:23:54.516956
8082 19:23:54.517021
8083 19:23:54.520553 ==
8084 19:23:54.523612 Dram Type= 6, Freq= 0, CH_0, rank 1
8085 19:23:54.526974 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8086 19:23:54.527057 ==
8087 19:23:54.527122
8088 19:23:54.527182
8089 19:23:54.530232 TX Vref Scan disable
8090 19:23:54.530330 == TX Byte 0 ==
8091 19:23:54.533754 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8092 19:23:54.540220 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8093 19:23:54.540303 == TX Byte 1 ==
8094 19:23:54.547063 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8095 19:23:54.550017 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8096 19:23:54.550100 ==
8097 19:23:54.553400 Dram Type= 6, Freq= 0, CH_0, rank 1
8098 19:23:54.556908 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8099 19:23:54.556991 ==
8100 19:23:54.571046
8101 19:23:54.574196 TX Vref early break, caculate TX vref
8102 19:23:54.577627 TX Vref=16, minBit 8, minWin=23, winSum=391
8103 19:23:54.581062 TX Vref=18, minBit 0, minWin=24, winSum=404
8104 19:23:54.584041 TX Vref=20, minBit 8, minWin=24, winSum=409
8105 19:23:54.587626 TX Vref=22, minBit 0, minWin=25, winSum=418
8106 19:23:54.590924 TX Vref=24, minBit 0, minWin=24, winSum=421
8107 19:23:54.597523 TX Vref=26, minBit 0, minWin=26, winSum=431
8108 19:23:54.600765 TX Vref=28, minBit 2, minWin=25, winSum=429
8109 19:23:54.604054 TX Vref=30, minBit 1, minWin=25, winSum=420
8110 19:23:54.607751 TX Vref=32, minBit 2, minWin=24, winSum=411
8111 19:23:54.610672 TX Vref=34, minBit 0, minWin=24, winSum=406
8112 19:23:54.617442 [TxChooseVref] Worse bit 0, Min win 26, Win sum 431, Final Vref 26
8113 19:23:54.617522
8114 19:23:54.620742 Final TX Range 0 Vref 26
8115 19:23:54.620814
8116 19:23:54.620875 ==
8117 19:23:54.624483 Dram Type= 6, Freq= 0, CH_0, rank 1
8118 19:23:54.627544 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8119 19:23:54.627615 ==
8120 19:23:54.627676
8121 19:23:54.627737
8122 19:23:54.630801 TX Vref Scan disable
8123 19:23:54.637645 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8124 19:23:54.637724 == TX Byte 0 ==
8125 19:23:54.640902 u2DelayCellOfst[0]=16 cells (5 PI)
8126 19:23:54.643825 u2DelayCellOfst[1]=20 cells (6 PI)
8127 19:23:54.647275 u2DelayCellOfst[2]=13 cells (4 PI)
8128 19:23:54.650599 u2DelayCellOfst[3]=13 cells (4 PI)
8129 19:23:54.654162 u2DelayCellOfst[4]=10 cells (3 PI)
8130 19:23:54.657324 u2DelayCellOfst[5]=0 cells (0 PI)
8131 19:23:54.660809 u2DelayCellOfst[6]=20 cells (6 PI)
8132 19:23:54.660874 u2DelayCellOfst[7]=20 cells (6 PI)
8133 19:23:54.667449 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8134 19:23:54.670949 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8135 19:23:54.671017 == TX Byte 1 ==
8136 19:23:54.673942 u2DelayCellOfst[8]=0 cells (0 PI)
8137 19:23:54.677197 u2DelayCellOfst[9]=3 cells (1 PI)
8138 19:23:54.680310 u2DelayCellOfst[10]=6 cells (2 PI)
8139 19:23:54.683631 u2DelayCellOfst[11]=3 cells (1 PI)
8140 19:23:54.687157 u2DelayCellOfst[12]=13 cells (4 PI)
8141 19:23:54.690516 u2DelayCellOfst[13]=13 cells (4 PI)
8142 19:23:54.693784 u2DelayCellOfst[14]=13 cells (4 PI)
8143 19:23:54.696924 u2DelayCellOfst[15]=10 cells (3 PI)
8144 19:23:54.700383 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8145 19:23:54.707013 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8146 19:23:54.707089 DramC Write-DBI on
8147 19:23:54.707155 ==
8148 19:23:54.710299 Dram Type= 6, Freq= 0, CH_0, rank 1
8149 19:23:54.713956 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8150 19:23:54.716710 ==
8151 19:23:54.716778
8152 19:23:54.716839
8153 19:23:54.716900 TX Vref Scan disable
8154 19:23:54.720239 == TX Byte 0 ==
8155 19:23:54.723722 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8156 19:23:54.727439 == TX Byte 1 ==
8157 19:23:54.730311 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8158 19:23:54.733987 DramC Write-DBI off
8159 19:23:54.734055
8160 19:23:54.734113 [DATLAT]
8161 19:23:54.734173 Freq=1600, CH0 RK1
8162 19:23:54.734228
8163 19:23:54.736994 DATLAT Default: 0xf
8164 19:23:54.737058 0, 0xFFFF, sum = 0
8165 19:23:54.740394 1, 0xFFFF, sum = 0
8166 19:23:54.740469 2, 0xFFFF, sum = 0
8167 19:23:54.743874 3, 0xFFFF, sum = 0
8168 19:23:54.747250 4, 0xFFFF, sum = 0
8169 19:23:54.747320 5, 0xFFFF, sum = 0
8170 19:23:54.750251 6, 0xFFFF, sum = 0
8171 19:23:54.750320 7, 0xFFFF, sum = 0
8172 19:23:54.753684 8, 0xFFFF, sum = 0
8173 19:23:54.753750 9, 0xFFFF, sum = 0
8174 19:23:54.757135 10, 0xFFFF, sum = 0
8175 19:23:54.757200 11, 0xFFFF, sum = 0
8176 19:23:54.760443 12, 0xFFFF, sum = 0
8177 19:23:54.760509 13, 0xFFFF, sum = 0
8178 19:23:54.763966 14, 0x0, sum = 1
8179 19:23:54.764031 15, 0x0, sum = 2
8180 19:23:54.766995 16, 0x0, sum = 3
8181 19:23:54.767063 17, 0x0, sum = 4
8182 19:23:54.770281 best_step = 15
8183 19:23:54.770346
8184 19:23:54.770408 ==
8185 19:23:54.773723 Dram Type= 6, Freq= 0, CH_0, rank 1
8186 19:23:54.777159 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8187 19:23:54.777227 ==
8188 19:23:54.777285 RX Vref Scan: 0
8189 19:23:54.777350
8190 19:23:54.780435 RX Vref 0 -> 0, step: 1
8191 19:23:54.780497
8192 19:23:54.783831 RX Delay 11 -> 252, step: 4
8193 19:23:54.787234 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8194 19:23:54.793646 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8195 19:23:54.797079 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8196 19:23:54.800247 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8197 19:23:54.803678 iDelay=191, Bit 4, Center 134 (87 ~ 182) 96
8198 19:23:54.806952 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8199 19:23:54.810136 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8200 19:23:54.817089 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8201 19:23:54.820303 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8202 19:23:54.823420 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8203 19:23:54.827010 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8204 19:23:54.833423 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8205 19:23:54.836808 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8206 19:23:54.840083 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8207 19:23:54.843593 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8208 19:23:54.846754 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8209 19:23:54.846825 ==
8210 19:23:54.850187 Dram Type= 6, Freq= 0, CH_0, rank 1
8211 19:23:54.856910 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8212 19:23:54.856983 ==
8213 19:23:54.857051 DQS Delay:
8214 19:23:54.859871 DQS0 = 0, DQS1 = 0
8215 19:23:54.859939 DQM Delay:
8216 19:23:54.863734 DQM0 = 133, DQM1 = 123
8217 19:23:54.863802 DQ Delay:
8218 19:23:54.866674 DQ0 =132, DQ1 =136, DQ2 =130, DQ3 =130
8219 19:23:54.869979 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =138
8220 19:23:54.873188 DQ8 =116, DQ9 =110, DQ10 =124, DQ11 =120
8221 19:23:54.876572 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =128
8222 19:23:54.876647
8223 19:23:54.876708
8224 19:23:54.876764
8225 19:23:54.880436 [DramC_TX_OE_Calibration] TA2
8226 19:23:54.883339 Original DQ_B0 (3 6) =30, OEN = 27
8227 19:23:54.886740 Original DQ_B1 (3 6) =30, OEN = 27
8228 19:23:54.890169 24, 0x0, End_B0=24 End_B1=24
8229 19:23:54.890244 25, 0x0, End_B0=25 End_B1=25
8230 19:23:54.893549 26, 0x0, End_B0=26 End_B1=26
8231 19:23:54.896729 27, 0x0, End_B0=27 End_B1=27
8232 19:23:54.900059 28, 0x0, End_B0=28 End_B1=28
8233 19:23:54.903533 29, 0x0, End_B0=29 End_B1=29
8234 19:23:54.903602 30, 0x0, End_B0=30 End_B1=30
8235 19:23:54.906984 31, 0x4141, End_B0=30 End_B1=30
8236 19:23:54.910046 Byte0 end_step=30 best_step=27
8237 19:23:54.913418 Byte1 end_step=30 best_step=27
8238 19:23:54.916644 Byte0 TX OE(2T, 0.5T) = (3, 3)
8239 19:23:54.920144 Byte1 TX OE(2T, 0.5T) = (3, 3)
8240 19:23:54.920212
8241 19:23:54.920277
8242 19:23:54.926739 [DQSOSCAuto] RK1, (LSB)MR18= 0x210e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 393 ps
8243 19:23:54.930206 CH0 RK1: MR19=303, MR18=210E
8244 19:23:54.936801 CH0_RK1: MR19=0x303, MR18=0x210E, DQSOSC=393, MR23=63, INC=23, DEC=15
8245 19:23:54.939990 [RxdqsGatingPostProcess] freq 1600
8246 19:23:54.943117 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8247 19:23:54.946692 best DQS0 dly(2T, 0.5T) = (1, 1)
8248 19:23:54.949691 best DQS1 dly(2T, 0.5T) = (1, 1)
8249 19:23:54.953413 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8250 19:23:54.956519 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8251 19:23:54.960001 best DQS0 dly(2T, 0.5T) = (1, 1)
8252 19:23:54.962972 best DQS1 dly(2T, 0.5T) = (1, 1)
8253 19:23:54.966237 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8254 19:23:54.969681 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8255 19:23:54.973135 Pre-setting of DQS Precalculation
8256 19:23:54.976438 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8257 19:23:54.976507 ==
8258 19:23:54.979690 Dram Type= 6, Freq= 0, CH_1, rank 0
8259 19:23:54.983112 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8260 19:23:54.986484 ==
8261 19:23:54.990045 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8262 19:23:54.992983 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8263 19:23:54.999849 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8264 19:23:55.003111 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8265 19:23:55.013611 [CA 0] Center 40 (11~70) winsize 60
8266 19:23:55.016971 [CA 1] Center 41 (11~71) winsize 61
8267 19:23:55.020293 [CA 2] Center 36 (7~66) winsize 60
8268 19:23:55.023514 [CA 3] Center 36 (7~66) winsize 60
8269 19:23:55.026596 [CA 4] Center 36 (6~67) winsize 62
8270 19:23:55.029756 [CA 5] Center 35 (5~66) winsize 62
8271 19:23:55.029824
8272 19:23:55.033443 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8273 19:23:55.033512
8274 19:23:55.036578 [CATrainingPosCal] consider 1 rank data
8275 19:23:55.040259 u2DelayCellTimex100 = 290/100 ps
8276 19:23:55.043617 CA0 delay=40 (11~70),Diff = 5 PI (16 cell)
8277 19:23:55.049866 CA1 delay=41 (11~71),Diff = 6 PI (20 cell)
8278 19:23:55.053443 CA2 delay=36 (7~66),Diff = 1 PI (3 cell)
8279 19:23:55.056790 CA3 delay=36 (7~66),Diff = 1 PI (3 cell)
8280 19:23:55.060270 CA4 delay=36 (6~67),Diff = 1 PI (3 cell)
8281 19:23:55.063602 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
8282 19:23:55.063675
8283 19:23:55.066545 CA PerBit enable=1, Macro0, CA PI delay=35
8284 19:23:55.066620
8285 19:23:55.070000 [CBTSetCACLKResult] CA Dly = 35
8286 19:23:55.070074 CS Dly: 9 (0~40)
8287 19:23:55.076277 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8288 19:23:55.079782 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8289 19:23:55.079851 ==
8290 19:23:55.082979 Dram Type= 6, Freq= 0, CH_1, rank 1
8291 19:23:55.086160 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8292 19:23:55.086229 ==
8293 19:23:55.093040 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8294 19:23:55.096418 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8295 19:23:55.103429 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8296 19:23:55.106144 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8297 19:23:55.116404 [CA 0] Center 42 (13~72) winsize 60
8298 19:23:55.119965 [CA 1] Center 42 (13~72) winsize 60
8299 19:23:55.122877 [CA 2] Center 38 (9~68) winsize 60
8300 19:23:55.126194 [CA 3] Center 37 (8~67) winsize 60
8301 19:23:55.129446 [CA 4] Center 38 (9~68) winsize 60
8302 19:23:55.133063 [CA 5] Center 37 (8~67) winsize 60
8303 19:23:55.133129
8304 19:23:55.136539 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8305 19:23:55.136616
8306 19:23:55.139748 [CATrainingPosCal] consider 2 rank data
8307 19:23:55.143214 u2DelayCellTimex100 = 290/100 ps
8308 19:23:55.146221 CA0 delay=41 (13~70),Diff = 4 PI (13 cell)
8309 19:23:55.153254 CA1 delay=42 (13~71),Diff = 5 PI (16 cell)
8310 19:23:55.156337 CA2 delay=37 (9~66),Diff = 0 PI (0 cell)
8311 19:23:55.159929 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8312 19:23:55.162968 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8313 19:23:55.166397 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8314 19:23:55.166465
8315 19:23:55.169955 CA PerBit enable=1, Macro0, CA PI delay=37
8316 19:23:55.170024
8317 19:23:55.172908 [CBTSetCACLKResult] CA Dly = 37
8318 19:23:55.172976 CS Dly: 9 (0~41)
8319 19:23:55.179713 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8320 19:23:55.182994 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8321 19:23:55.183061
8322 19:23:55.186282 ----->DramcWriteLeveling(PI) begin...
8323 19:23:55.186351 ==
8324 19:23:55.189768 Dram Type= 6, Freq= 0, CH_1, rank 0
8325 19:23:55.193357 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8326 19:23:55.196171 ==
8327 19:23:55.196238 Write leveling (Byte 0): 26 => 26
8328 19:23:55.199476 Write leveling (Byte 1): 27 => 27
8329 19:23:55.202953 DramcWriteLeveling(PI) end<-----
8330 19:23:55.203021
8331 19:23:55.203086 ==
8332 19:23:55.206329 Dram Type= 6, Freq= 0, CH_1, rank 0
8333 19:23:55.212832 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8334 19:23:55.212902 ==
8335 19:23:55.212961 [Gating] SW mode calibration
8336 19:23:55.223058 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8337 19:23:55.226412 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8338 19:23:55.229830 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8339 19:23:55.236159 1 4 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
8340 19:23:55.239561 1 4 8 | B1->B0 | 2d2d 3231 | 1 1 | (0 0) (0 0)
8341 19:23:55.242920 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8342 19:23:55.249434 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8343 19:23:55.253133 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8344 19:23:55.256427 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8345 19:23:55.262906 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8346 19:23:55.266462 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8347 19:23:55.269501 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8348 19:23:55.276427 1 5 8 | B1->B0 | 2e2e 2a2a | 1 0 | (1 0) (1 0)
8349 19:23:55.279396 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
8350 19:23:55.282939 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8351 19:23:55.289695 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8352 19:23:55.292885 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8353 19:23:55.296006 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8354 19:23:55.302978 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8355 19:23:55.305891 1 6 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8356 19:23:55.309545 1 6 8 | B1->B0 | 4141 4444 | 0 0 | (0 0) (0 0)
8357 19:23:55.316108 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8358 19:23:55.319545 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8359 19:23:55.322820 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8360 19:23:55.326239 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8361 19:23:55.332636 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8362 19:23:55.336415 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8363 19:23:55.339536 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8364 19:23:55.345883 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8365 19:23:55.349161 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8366 19:23:55.352760 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8367 19:23:55.359457 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8368 19:23:55.362726 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8369 19:23:55.365972 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8370 19:23:55.372798 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8371 19:23:55.375932 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8372 19:23:55.379381 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8373 19:23:55.385853 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8374 19:23:55.389492 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8375 19:23:55.392725 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8376 19:23:55.399225 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8377 19:23:55.402675 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8378 19:23:55.406118 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8379 19:23:55.412580 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8380 19:23:55.415934 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8381 19:23:55.419249 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8382 19:23:55.423050 Total UI for P1: 0, mck2ui 16
8383 19:23:55.426005 best dqsien dly found for B0: ( 1, 9, 6)
8384 19:23:55.429239 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8385 19:23:55.432683 Total UI for P1: 0, mck2ui 16
8386 19:23:55.436073 best dqsien dly found for B1: ( 1, 9, 10)
8387 19:23:55.439480 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8388 19:23:55.443220 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8389 19:23:55.443294
8390 19:23:55.449422 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8391 19:23:55.452681 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8392 19:23:55.456438 [Gating] SW calibration Done
8393 19:23:55.456508 ==
8394 19:23:55.459573 Dram Type= 6, Freq= 0, CH_1, rank 0
8395 19:23:55.462713 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8396 19:23:55.462781 ==
8397 19:23:55.462848 RX Vref Scan: 0
8398 19:23:55.462905
8399 19:23:55.466328 RX Vref 0 -> 0, step: 1
8400 19:23:55.466407
8401 19:23:55.469326 RX Delay 0 -> 252, step: 8
8402 19:23:55.472639 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8403 19:23:55.475914 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8404 19:23:55.482500 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8405 19:23:55.486199 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8406 19:23:55.489524 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8407 19:23:55.492404 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8408 19:23:55.495726 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8409 19:23:55.499065 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8410 19:23:55.505815 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8411 19:23:55.509256 iDelay=200, Bit 9, Center 123 (80 ~ 167) 88
8412 19:23:55.512229 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8413 19:23:55.515695 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8414 19:23:55.522135 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8415 19:23:55.525709 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8416 19:23:55.529009 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8417 19:23:55.532510 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8418 19:23:55.532578 ==
8419 19:23:55.535478 Dram Type= 6, Freq= 0, CH_1, rank 0
8420 19:23:55.542247 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8421 19:23:55.542321 ==
8422 19:23:55.542389 DQS Delay:
8423 19:23:55.542495 DQS0 = 0, DQS1 = 0
8424 19:23:55.545515 DQM Delay:
8425 19:23:55.545591 DQM0 = 136, DQM1 = 131
8426 19:23:55.548585 DQ Delay:
8427 19:23:55.551940 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8428 19:23:55.555302 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8429 19:23:55.558953 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123
8430 19:23:55.562263 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =139
8431 19:23:55.562344
8432 19:23:55.562409
8433 19:23:55.562478 ==
8434 19:23:55.565678 Dram Type= 6, Freq= 0, CH_1, rank 0
8435 19:23:55.568878 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8436 19:23:55.571895 ==
8437 19:23:55.571969
8438 19:23:55.572032
8439 19:23:55.572091 TX Vref Scan disable
8440 19:23:55.575240 == TX Byte 0 ==
8441 19:23:55.578432 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8442 19:23:55.582045 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8443 19:23:55.585180 == TX Byte 1 ==
8444 19:23:55.588446 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8445 19:23:55.591864 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8446 19:23:55.591945 ==
8447 19:23:55.595290 Dram Type= 6, Freq= 0, CH_1, rank 0
8448 19:23:55.601877 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8449 19:23:55.601959 ==
8450 19:23:55.613653
8451 19:23:55.616489 TX Vref early break, caculate TX vref
8452 19:23:55.619837 TX Vref=16, minBit 10, minWin=21, winSum=374
8453 19:23:55.623378 TX Vref=18, minBit 0, minWin=22, winSum=380
8454 19:23:55.626605 TX Vref=20, minBit 10, minWin=23, winSum=390
8455 19:23:55.630136 TX Vref=22, minBit 10, minWin=23, winSum=405
8456 19:23:55.636643 TX Vref=24, minBit 0, minWin=24, winSum=413
8457 19:23:55.640011 TX Vref=26, minBit 14, minWin=24, winSum=421
8458 19:23:55.642917 TX Vref=28, minBit 14, minWin=25, winSum=421
8459 19:23:55.646368 TX Vref=30, minBit 15, minWin=24, winSum=413
8460 19:23:55.649685 TX Vref=32, minBit 10, minWin=24, winSum=405
8461 19:23:55.653398 TX Vref=34, minBit 12, minWin=23, winSum=392
8462 19:23:55.659816 [TxChooseVref] Worse bit 14, Min win 25, Win sum 421, Final Vref 28
8463 19:23:55.659898
8464 19:23:55.663278 Final TX Range 0 Vref 28
8465 19:23:55.663360
8466 19:23:55.663424 ==
8467 19:23:55.666583 Dram Type= 6, Freq= 0, CH_1, rank 0
8468 19:23:55.669731 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8469 19:23:55.669812 ==
8470 19:23:55.669876
8471 19:23:55.673204
8472 19:23:55.673285 TX Vref Scan disable
8473 19:23:55.680068 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8474 19:23:55.680150 == TX Byte 0 ==
8475 19:23:55.683333 u2DelayCellOfst[0]=13 cells (4 PI)
8476 19:23:55.686607 u2DelayCellOfst[1]=10 cells (3 PI)
8477 19:23:55.689853 u2DelayCellOfst[2]=0 cells (0 PI)
8478 19:23:55.693198 u2DelayCellOfst[3]=6 cells (2 PI)
8479 19:23:55.696155 u2DelayCellOfst[4]=3 cells (1 PI)
8480 19:23:55.699625 u2DelayCellOfst[5]=16 cells (5 PI)
8481 19:23:55.703046 u2DelayCellOfst[6]=16 cells (5 PI)
8482 19:23:55.706340 u2DelayCellOfst[7]=3 cells (1 PI)
8483 19:23:55.709498 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8484 19:23:55.713008 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8485 19:23:55.716167 == TX Byte 1 ==
8486 19:23:55.719551 u2DelayCellOfst[8]=0 cells (0 PI)
8487 19:23:55.723056 u2DelayCellOfst[9]=6 cells (2 PI)
8488 19:23:55.726044 u2DelayCellOfst[10]=13 cells (4 PI)
8489 19:23:55.726125 u2DelayCellOfst[11]=6 cells (2 PI)
8490 19:23:55.729416 u2DelayCellOfst[12]=16 cells (5 PI)
8491 19:23:55.732846 u2DelayCellOfst[13]=23 cells (7 PI)
8492 19:23:55.736463 u2DelayCellOfst[14]=20 cells (6 PI)
8493 19:23:55.739584 u2DelayCellOfst[15]=20 cells (6 PI)
8494 19:23:55.745956 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8495 19:23:55.749423 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8496 19:23:55.749504 DramC Write-DBI on
8497 19:23:55.749568 ==
8498 19:23:55.752724 Dram Type= 6, Freq= 0, CH_1, rank 0
8499 19:23:55.759199 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8500 19:23:55.759285 ==
8501 19:23:55.759349
8502 19:23:55.759407
8503 19:23:55.759464 TX Vref Scan disable
8504 19:23:55.763561 == TX Byte 0 ==
8505 19:23:55.766943 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8506 19:23:55.770124 == TX Byte 1 ==
8507 19:23:55.773224 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8508 19:23:55.776837 DramC Write-DBI off
8509 19:23:55.776919
8510 19:23:55.776982 [DATLAT]
8511 19:23:55.777040 Freq=1600, CH1 RK0
8512 19:23:55.777099
8513 19:23:55.779911 DATLAT Default: 0xf
8514 19:23:55.779991 0, 0xFFFF, sum = 0
8515 19:23:55.783266 1, 0xFFFF, sum = 0
8516 19:23:55.783348 2, 0xFFFF, sum = 0
8517 19:23:55.786972 3, 0xFFFF, sum = 0
8518 19:23:55.790145 4, 0xFFFF, sum = 0
8519 19:23:55.790228 5, 0xFFFF, sum = 0
8520 19:23:55.793230 6, 0xFFFF, sum = 0
8521 19:23:55.793335 7, 0xFFFF, sum = 0
8522 19:23:55.796771 8, 0xFFFF, sum = 0
8523 19:23:55.796854 9, 0xFFFF, sum = 0
8524 19:23:55.799820 10, 0xFFFF, sum = 0
8525 19:23:55.799903 11, 0xFFFF, sum = 0
8526 19:23:55.803179 12, 0xFFFF, sum = 0
8527 19:23:55.803262 13, 0xFFFF, sum = 0
8528 19:23:55.806766 14, 0x0, sum = 1
8529 19:23:55.806848 15, 0x0, sum = 2
8530 19:23:55.810083 16, 0x0, sum = 3
8531 19:23:55.810165 17, 0x0, sum = 4
8532 19:23:55.813191 best_step = 15
8533 19:23:55.813288
8534 19:23:55.813402 ==
8535 19:23:55.816621 Dram Type= 6, Freq= 0, CH_1, rank 0
8536 19:23:55.819949 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8537 19:23:55.820031 ==
8538 19:23:55.822932 RX Vref Scan: 1
8539 19:23:55.823013
8540 19:23:55.823077 Set Vref Range= 24 -> 127
8541 19:23:55.823135
8542 19:23:55.826433 RX Vref 24 -> 127, step: 1
8543 19:23:55.826515
8544 19:23:55.829857 RX Delay 19 -> 252, step: 4
8545 19:23:55.829938
8546 19:23:55.832770 Set Vref, RX VrefLevel [Byte0]: 24
8547 19:23:55.836102 [Byte1]: 24
8548 19:23:55.836184
8549 19:23:55.839649 Set Vref, RX VrefLevel [Byte0]: 25
8550 19:23:55.842598 [Byte1]: 25
8551 19:23:55.846355
8552 19:23:55.846436 Set Vref, RX VrefLevel [Byte0]: 26
8553 19:23:55.849257 [Byte1]: 26
8554 19:23:55.853604
8555 19:23:55.853685 Set Vref, RX VrefLevel [Byte0]: 27
8556 19:23:55.856794 [Byte1]: 27
8557 19:23:55.861424
8558 19:23:55.861504 Set Vref, RX VrefLevel [Byte0]: 28
8559 19:23:55.864800 [Byte1]: 28
8560 19:23:55.868964
8561 19:23:55.869045 Set Vref, RX VrefLevel [Byte0]: 29
8562 19:23:55.872155 [Byte1]: 29
8563 19:23:55.876401
8564 19:23:55.876482 Set Vref, RX VrefLevel [Byte0]: 30
8565 19:23:55.879988 [Byte1]: 30
8566 19:23:55.883827
8567 19:23:55.883908 Set Vref, RX VrefLevel [Byte0]: 31
8568 19:23:55.887325 [Byte1]: 31
8569 19:23:55.891523
8570 19:23:55.891604 Set Vref, RX VrefLevel [Byte0]: 32
8571 19:23:55.895029 [Byte1]: 32
8572 19:23:55.899100
8573 19:23:55.899181 Set Vref, RX VrefLevel [Byte0]: 33
8574 19:23:55.902516 [Byte1]: 33
8575 19:23:55.906436
8576 19:23:55.906517 Set Vref, RX VrefLevel [Byte0]: 34
8577 19:23:55.910054 [Byte1]: 34
8578 19:23:55.914480
8579 19:23:55.914561 Set Vref, RX VrefLevel [Byte0]: 35
8580 19:23:55.917703 [Byte1]: 35
8581 19:23:55.921597
8582 19:23:55.921678 Set Vref, RX VrefLevel [Byte0]: 36
8583 19:23:55.925021 [Byte1]: 36
8584 19:23:55.929419
8585 19:23:55.929500 Set Vref, RX VrefLevel [Byte0]: 37
8586 19:23:55.932911 [Byte1]: 37
8587 19:23:55.936795
8588 19:23:55.936876 Set Vref, RX VrefLevel [Byte0]: 38
8589 19:23:55.940703 [Byte1]: 38
8590 19:23:55.944472
8591 19:23:55.944553 Set Vref, RX VrefLevel [Byte0]: 39
8592 19:23:55.947712 [Byte1]: 39
8593 19:23:55.951992
8594 19:23:55.952073 Set Vref, RX VrefLevel [Byte0]: 40
8595 19:23:55.955407 [Byte1]: 40
8596 19:23:55.959792
8597 19:23:55.959873 Set Vref, RX VrefLevel [Byte0]: 41
8598 19:23:55.963014 [Byte1]: 41
8599 19:23:55.967234
8600 19:23:55.967314 Set Vref, RX VrefLevel [Byte0]: 42
8601 19:23:55.970571 [Byte1]: 42
8602 19:23:55.974891
8603 19:23:55.974972 Set Vref, RX VrefLevel [Byte0]: 43
8604 19:23:55.977949 [Byte1]: 43
8605 19:23:55.982565
8606 19:23:55.982647 Set Vref, RX VrefLevel [Byte0]: 44
8607 19:23:55.985531 [Byte1]: 44
8608 19:23:55.989934
8609 19:23:55.990015 Set Vref, RX VrefLevel [Byte0]: 45
8610 19:23:55.993028 [Byte1]: 45
8611 19:23:55.997770
8612 19:23:55.997851 Set Vref, RX VrefLevel [Byte0]: 46
8613 19:23:56.001089 [Byte1]: 46
8614 19:23:56.005007
8615 19:23:56.005114 Set Vref, RX VrefLevel [Byte0]: 47
8616 19:23:56.008525 [Byte1]: 47
8617 19:23:56.012488
8618 19:23:56.012569 Set Vref, RX VrefLevel [Byte0]: 48
8619 19:23:56.015829 [Byte1]: 48
8620 19:23:56.020188
8621 19:23:56.020268 Set Vref, RX VrefLevel [Byte0]: 49
8622 19:23:56.023577 [Byte1]: 49
8623 19:23:56.027870
8624 19:23:56.027951 Set Vref, RX VrefLevel [Byte0]: 50
8625 19:23:56.031321 [Byte1]: 50
8626 19:23:56.035222
8627 19:23:56.035303 Set Vref, RX VrefLevel [Byte0]: 51
8628 19:23:56.038641 [Byte1]: 51
8629 19:23:56.043014
8630 19:23:56.043115 Set Vref, RX VrefLevel [Byte0]: 52
8631 19:23:56.046437 [Byte1]: 52
8632 19:23:56.050468
8633 19:23:56.050549 Set Vref, RX VrefLevel [Byte0]: 53
8634 19:23:56.053785 [Byte1]: 53
8635 19:23:56.058212
8636 19:23:56.058293 Set Vref, RX VrefLevel [Byte0]: 54
8637 19:23:56.061557 [Byte1]: 54
8638 19:23:56.065723
8639 19:23:56.065805 Set Vref, RX VrefLevel [Byte0]: 55
8640 19:23:56.069005 [Byte1]: 55
8641 19:23:56.073563
8642 19:23:56.073644 Set Vref, RX VrefLevel [Byte0]: 56
8643 19:23:56.076794 [Byte1]: 56
8644 19:23:56.080788
8645 19:23:56.080868 Set Vref, RX VrefLevel [Byte0]: 57
8646 19:23:56.084184 [Byte1]: 57
8647 19:23:56.088506
8648 19:23:56.088586 Set Vref, RX VrefLevel [Byte0]: 58
8649 19:23:56.091826 [Byte1]: 58
8650 19:23:56.095787
8651 19:23:56.095868 Set Vref, RX VrefLevel [Byte0]: 59
8652 19:23:56.099421 [Byte1]: 59
8653 19:23:56.103515
8654 19:23:56.103597 Set Vref, RX VrefLevel [Byte0]: 60
8655 19:23:56.106884 [Byte1]: 60
8656 19:23:56.111136
8657 19:23:56.111243 Set Vref, RX VrefLevel [Byte0]: 61
8658 19:23:56.114351 [Byte1]: 61
8659 19:23:56.118837
8660 19:23:56.118918 Set Vref, RX VrefLevel [Byte0]: 62
8661 19:23:56.121991 [Byte1]: 62
8662 19:23:56.126494
8663 19:23:56.126575 Set Vref, RX VrefLevel [Byte0]: 63
8664 19:23:56.129529 [Byte1]: 63
8665 19:23:56.133923
8666 19:23:56.134004 Set Vref, RX VrefLevel [Byte0]: 64
8667 19:23:56.137240 [Byte1]: 64
8668 19:23:56.141553
8669 19:23:56.141634 Set Vref, RX VrefLevel [Byte0]: 65
8670 19:23:56.145004 [Byte1]: 65
8671 19:23:56.149198
8672 19:23:56.149328 Set Vref, RX VrefLevel [Byte0]: 66
8673 19:23:56.152566 [Byte1]: 66
8674 19:23:56.156557
8675 19:23:56.156638 Set Vref, RX VrefLevel [Byte0]: 67
8676 19:23:56.160113 [Byte1]: 67
8677 19:23:56.163928
8678 19:23:56.164009 Set Vref, RX VrefLevel [Byte0]: 68
8679 19:23:56.167175 [Byte1]: 68
8680 19:23:56.171799
8681 19:23:56.171880 Set Vref, RX VrefLevel [Byte0]: 69
8682 19:23:56.175015 [Byte1]: 69
8683 19:23:56.179599
8684 19:23:56.179680 Set Vref, RX VrefLevel [Byte0]: 70
8685 19:23:56.182369 [Byte1]: 70
8686 19:23:56.186670
8687 19:23:56.186751 Set Vref, RX VrefLevel [Byte0]: 71
8688 19:23:56.190126 [Byte1]: 71
8689 19:23:56.194396
8690 19:23:56.194478 Set Vref, RX VrefLevel [Byte0]: 72
8691 19:23:56.197902 [Byte1]: 72
8692 19:23:56.201763
8693 19:23:56.201844 Set Vref, RX VrefLevel [Byte0]: 73
8694 19:23:56.205248 [Byte1]: 73
8695 19:23:56.209577
8696 19:23:56.209658 Set Vref, RX VrefLevel [Byte0]: 74
8697 19:23:56.212766 [Byte1]: 74
8698 19:23:56.216913
8699 19:23:56.216994 Final RX Vref Byte 0 = 59 to rank0
8700 19:23:56.220450 Final RX Vref Byte 1 = 63 to rank0
8701 19:23:56.223990 Final RX Vref Byte 0 = 59 to rank1
8702 19:23:56.227140 Final RX Vref Byte 1 = 63 to rank1==
8703 19:23:56.230471 Dram Type= 6, Freq= 0, CH_1, rank 0
8704 19:23:56.236807 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8705 19:23:56.236891 ==
8706 19:23:56.236956 DQS Delay:
8707 19:23:56.237016 DQS0 = 0, DQS1 = 0
8708 19:23:56.240348 DQM Delay:
8709 19:23:56.240430 DQM0 = 134, DQM1 = 129
8710 19:23:56.243632 DQ Delay:
8711 19:23:56.247105 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =132
8712 19:23:56.250400 DQ4 =130, DQ5 =144, DQ6 =146, DQ7 =132
8713 19:23:56.253793 DQ8 =118, DQ9 =118, DQ10 =134, DQ11 =122
8714 19:23:56.256928 DQ12 =140, DQ13 =134, DQ14 =136, DQ15 =136
8715 19:23:56.257010
8716 19:23:56.257074
8717 19:23:56.257133
8718 19:23:56.260335 [DramC_TX_OE_Calibration] TA2
8719 19:23:56.263647 Original DQ_B0 (3 6) =30, OEN = 27
8720 19:23:56.266971 Original DQ_B1 (3 6) =30, OEN = 27
8721 19:23:56.270432 24, 0x0, End_B0=24 End_B1=24
8722 19:23:56.270515 25, 0x0, End_B0=25 End_B1=25
8723 19:23:56.273289 26, 0x0, End_B0=26 End_B1=26
8724 19:23:56.277014 27, 0x0, End_B0=27 End_B1=27
8725 19:23:56.280611 28, 0x0, End_B0=28 End_B1=28
8726 19:23:56.280695 29, 0x0, End_B0=29 End_B1=29
8727 19:23:56.283406 30, 0x0, End_B0=30 End_B1=30
8728 19:23:56.286971 31, 0x4141, End_B0=30 End_B1=30
8729 19:23:56.290414 Byte0 end_step=30 best_step=27
8730 19:23:56.293431 Byte1 end_step=30 best_step=27
8731 19:23:56.296763 Byte0 TX OE(2T, 0.5T) = (3, 3)
8732 19:23:56.296845 Byte1 TX OE(2T, 0.5T) = (3, 3)
8733 19:23:56.300147
8734 19:23:56.300228
8735 19:23:56.306788 [DQSOSCAuto] RK0, (LSB)MR18= 0x1927, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8736 19:23:56.310175 CH1 RK0: MR19=303, MR18=1927
8737 19:23:56.316959 CH1_RK0: MR19=0x303, MR18=0x1927, DQSOSC=390, MR23=63, INC=24, DEC=16
8738 19:23:56.317044
8739 19:23:56.319987 ----->DramcWriteLeveling(PI) begin...
8740 19:23:56.320070 ==
8741 19:23:56.323178 Dram Type= 6, Freq= 0, CH_1, rank 1
8742 19:23:56.326790 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8743 19:23:56.326873 ==
8744 19:23:56.329839 Write leveling (Byte 0): 25 => 25
8745 19:23:56.333252 Write leveling (Byte 1): 28 => 28
8746 19:23:56.336549 DramcWriteLeveling(PI) end<-----
8747 19:23:56.336631
8748 19:23:56.336695 ==
8749 19:23:56.340092 Dram Type= 6, Freq= 0, CH_1, rank 1
8750 19:23:56.343522 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8751 19:23:56.343608 ==
8752 19:23:56.346401 [Gating] SW mode calibration
8753 19:23:56.353143 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8754 19:23:56.359843 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8755 19:23:56.363023 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8756 19:23:56.366618 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8757 19:23:56.372965 1 4 8 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
8758 19:23:56.376191 1 4 12 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 0)
8759 19:23:56.379590 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8760 19:23:56.386380 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8761 19:23:56.389568 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8762 19:23:56.393491 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8763 19:23:56.399826 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8764 19:23:56.402878 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8765 19:23:56.406293 1 5 8 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 0)
8766 19:23:56.412695 1 5 12 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 1)
8767 19:23:56.416185 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8768 19:23:56.419346 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8769 19:23:56.426044 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8770 19:23:56.429343 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8771 19:23:56.432951 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8772 19:23:56.439431 1 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8773 19:23:56.442721 1 6 8 | B1->B0 | 4646 2525 | 0 0 | (0 0) (0 0)
8774 19:23:56.446127 1 6 12 | B1->B0 | 4646 3f3f | 0 0 | (0 0) (0 0)
8775 19:23:56.453006 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8776 19:23:56.456528 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8777 19:23:56.459495 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8778 19:23:56.465891 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8779 19:23:56.469305 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8780 19:23:56.472628 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8781 19:23:56.479407 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8782 19:23:56.482622 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8783 19:23:56.485875 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8784 19:23:56.492643 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8785 19:23:56.495923 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8786 19:23:56.499299 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8787 19:23:56.505805 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8788 19:23:56.509073 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8789 19:23:56.512503 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8790 19:23:56.519034 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8791 19:23:56.522115 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8792 19:23:56.525631 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8793 19:23:56.532520 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8794 19:23:56.535832 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8795 19:23:56.538645 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8796 19:23:56.545218 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8797 19:23:56.548728 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8798 19:23:56.551935 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8799 19:23:56.555590 Total UI for P1: 0, mck2ui 16
8800 19:23:56.558440 best dqsien dly found for B1: ( 1, 9, 8)
8801 19:23:56.561856 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8802 19:23:56.565189 Total UI for P1: 0, mck2ui 16
8803 19:23:56.568590 best dqsien dly found for B0: ( 1, 9, 10)
8804 19:23:56.571727 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8805 19:23:56.575246 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8806 19:23:56.578681
8807 19:23:56.582156 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8808 19:23:56.585416 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8809 19:23:56.588582 [Gating] SW calibration Done
8810 19:23:56.588666 ==
8811 19:23:56.591856 Dram Type= 6, Freq= 0, CH_1, rank 1
8812 19:23:56.595288 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8813 19:23:56.595374 ==
8814 19:23:56.598254 RX Vref Scan: 0
8815 19:23:56.598339
8816 19:23:56.598423 RX Vref 0 -> 0, step: 1
8817 19:23:56.598503
8818 19:23:56.601618 RX Delay 0 -> 252, step: 8
8819 19:23:56.605011 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8820 19:23:56.608426 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8821 19:23:56.614973 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8822 19:23:56.618638 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8823 19:23:56.621892 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8824 19:23:56.624957 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8825 19:23:56.628209 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8826 19:23:56.634921 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8827 19:23:56.638282 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8828 19:23:56.641720 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8829 19:23:56.644885 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8830 19:23:56.648269 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8831 19:23:56.654775 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8832 19:23:56.658177 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8833 19:23:56.661532 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8834 19:23:56.664917 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8835 19:23:56.664998 ==
8836 19:23:56.668452 Dram Type= 6, Freq= 0, CH_1, rank 1
8837 19:23:56.674954 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8838 19:23:56.675029 ==
8839 19:23:56.675090 DQS Delay:
8840 19:23:56.675149 DQS0 = 0, DQS1 = 0
8841 19:23:56.678274 DQM Delay:
8842 19:23:56.678346 DQM0 = 136, DQM1 = 132
8843 19:23:56.681508 DQ Delay:
8844 19:23:56.684554 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8845 19:23:56.688198 DQ4 =139, DQ5 =147, DQ6 =139, DQ7 =135
8846 19:23:56.691383 DQ8 =115, DQ9 =123, DQ10 =131, DQ11 =127
8847 19:23:56.694669 DQ12 =143, DQ13 =139, DQ14 =139, DQ15 =143
8848 19:23:56.694741
8849 19:23:56.694808
8850 19:23:56.694866 ==
8851 19:23:56.698116 Dram Type= 6, Freq= 0, CH_1, rank 1
8852 19:23:56.701401 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8853 19:23:56.704905 ==
8854 19:23:56.705005
8855 19:23:56.705085
8856 19:23:56.705146 TX Vref Scan disable
8857 19:23:56.707787 == TX Byte 0 ==
8858 19:23:56.711169 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8859 19:23:56.714695 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8860 19:23:56.718095 == TX Byte 1 ==
8861 19:23:56.721522 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8862 19:23:56.724422 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8863 19:23:56.724495 ==
8864 19:23:56.728130 Dram Type= 6, Freq= 0, CH_1, rank 1
8865 19:23:56.734611 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8866 19:23:56.734694 ==
8867 19:23:56.746424
8868 19:23:56.749554 TX Vref early break, caculate TX vref
8869 19:23:56.753181 TX Vref=16, minBit 12, minWin=22, winSum=380
8870 19:23:56.756398 TX Vref=18, minBit 12, minWin=22, winSum=393
8871 19:23:56.759506 TX Vref=20, minBit 9, minWin=23, winSum=401
8872 19:23:56.762909 TX Vref=22, minBit 10, minWin=23, winSum=405
8873 19:23:56.769649 TX Vref=24, minBit 11, minWin=24, winSum=414
8874 19:23:56.773002 TX Vref=26, minBit 0, minWin=26, winSum=425
8875 19:23:56.776492 TX Vref=28, minBit 10, minWin=24, winSum=418
8876 19:23:56.779642 TX Vref=30, minBit 10, minWin=24, winSum=412
8877 19:23:56.783090 TX Vref=32, minBit 0, minWin=24, winSum=404
8878 19:23:56.786543 TX Vref=34, minBit 9, minWin=23, winSum=396
8879 19:23:56.793211 [TxChooseVref] Worse bit 0, Min win 26, Win sum 425, Final Vref 26
8880 19:23:56.793348
8881 19:23:56.796169 Final TX Range 0 Vref 26
8882 19:23:56.796250
8883 19:23:56.796315 ==
8884 19:23:56.799849 Dram Type= 6, Freq= 0, CH_1, rank 1
8885 19:23:56.802853 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8886 19:23:56.802938 ==
8887 19:23:56.803003
8888 19:23:56.803061
8889 19:23:56.806259 TX Vref Scan disable
8890 19:23:56.812689 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8891 19:23:56.812771 == TX Byte 0 ==
8892 19:23:56.816578 u2DelayCellOfst[0]=13 cells (4 PI)
8893 19:23:56.819412 u2DelayCellOfst[1]=10 cells (3 PI)
8894 19:23:56.822902 u2DelayCellOfst[2]=0 cells (0 PI)
8895 19:23:56.826032 u2DelayCellOfst[3]=3 cells (1 PI)
8896 19:23:56.829360 u2DelayCellOfst[4]=6 cells (2 PI)
8897 19:23:56.833029 u2DelayCellOfst[5]=16 cells (5 PI)
8898 19:23:56.835996 u2DelayCellOfst[6]=16 cells (5 PI)
8899 19:23:56.839372 u2DelayCellOfst[7]=3 cells (1 PI)
8900 19:23:56.842430 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8901 19:23:56.846136 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8902 19:23:56.849193 == TX Byte 1 ==
8903 19:23:56.852735 u2DelayCellOfst[8]=0 cells (0 PI)
8904 19:23:56.852817 u2DelayCellOfst[9]=3 cells (1 PI)
8905 19:23:56.855897 u2DelayCellOfst[10]=10 cells (3 PI)
8906 19:23:56.859208 u2DelayCellOfst[11]=3 cells (1 PI)
8907 19:23:56.862338 u2DelayCellOfst[12]=13 cells (4 PI)
8908 19:23:56.865935 u2DelayCellOfst[13]=16 cells (5 PI)
8909 19:23:56.869245 u2DelayCellOfst[14]=20 cells (6 PI)
8910 19:23:56.872638 u2DelayCellOfst[15]=20 cells (6 PI)
8911 19:23:56.875981 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8912 19:23:56.882605 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8913 19:23:56.882687 DramC Write-DBI on
8914 19:23:56.882750 ==
8915 19:23:56.885814 Dram Type= 6, Freq= 0, CH_1, rank 1
8916 19:23:56.892097 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8917 19:23:56.892179 ==
8918 19:23:56.892244
8919 19:23:56.892302
8920 19:23:56.892358 TX Vref Scan disable
8921 19:23:56.895957 == TX Byte 0 ==
8922 19:23:56.899624 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8923 19:23:56.902984 == TX Byte 1 ==
8924 19:23:56.905983 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8925 19:23:56.909449 DramC Write-DBI off
8926 19:23:56.909530
8927 19:23:56.909593 [DATLAT]
8928 19:23:56.909652 Freq=1600, CH1 RK1
8929 19:23:56.909710
8930 19:23:56.912975 DATLAT Default: 0xf
8931 19:23:56.913082 0, 0xFFFF, sum = 0
8932 19:23:56.916501 1, 0xFFFF, sum = 0
8933 19:23:56.916584 2, 0xFFFF, sum = 0
8934 19:23:56.919525 3, 0xFFFF, sum = 0
8935 19:23:56.922986 4, 0xFFFF, sum = 0
8936 19:23:56.923069 5, 0xFFFF, sum = 0
8937 19:23:56.925940 6, 0xFFFF, sum = 0
8938 19:23:56.926023 7, 0xFFFF, sum = 0
8939 19:23:56.929252 8, 0xFFFF, sum = 0
8940 19:23:56.929386 9, 0xFFFF, sum = 0
8941 19:23:56.932734 10, 0xFFFF, sum = 0
8942 19:23:56.932817 11, 0xFFFF, sum = 0
8943 19:23:56.936399 12, 0xFFFF, sum = 0
8944 19:23:56.936481 13, 0xFFFF, sum = 0
8945 19:23:56.939380 14, 0x0, sum = 1
8946 19:23:56.939463 15, 0x0, sum = 2
8947 19:23:56.942988 16, 0x0, sum = 3
8948 19:23:56.943070 17, 0x0, sum = 4
8949 19:23:56.946151 best_step = 15
8950 19:23:56.946233
8951 19:23:56.946296 ==
8952 19:23:56.949174 Dram Type= 6, Freq= 0, CH_1, rank 1
8953 19:23:56.952935 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8954 19:23:56.953016 ==
8955 19:23:56.953081 RX Vref Scan: 0
8956 19:23:56.956154
8957 19:23:56.956236 RX Vref 0 -> 0, step: 1
8958 19:23:56.956300
8959 19:23:56.959167 RX Delay 19 -> 252, step: 4
8960 19:23:56.962688 iDelay=195, Bit 0, Center 138 (95 ~ 182) 88
8961 19:23:56.969441 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8962 19:23:56.972685 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
8963 19:23:56.976067 iDelay=195, Bit 3, Center 132 (83 ~ 182) 100
8964 19:23:56.979502 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
8965 19:23:56.982345 iDelay=195, Bit 5, Center 144 (99 ~ 190) 92
8966 19:23:56.985841 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
8967 19:23:56.992572 iDelay=195, Bit 7, Center 132 (83 ~ 182) 100
8968 19:23:56.995980 iDelay=195, Bit 8, Center 114 (67 ~ 162) 96
8969 19:23:56.999296 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8970 19:23:57.002652 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
8971 19:23:57.005850 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8972 19:23:57.012524 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
8973 19:23:57.015499 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8974 19:23:57.018947 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
8975 19:23:57.022390 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
8976 19:23:57.022472 ==
8977 19:23:57.025887 Dram Type= 6, Freq= 0, CH_1, rank 1
8978 19:23:57.032222 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8979 19:23:57.032304 ==
8980 19:23:57.032369 DQS Delay:
8981 19:23:57.035571 DQS0 = 0, DQS1 = 0
8982 19:23:57.035652 DQM Delay:
8983 19:23:57.035717 DQM0 = 134, DQM1 = 130
8984 19:23:57.038987 DQ Delay:
8985 19:23:57.042163 DQ0 =138, DQ1 =130, DQ2 =120, DQ3 =132
8986 19:23:57.045577 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =132
8987 19:23:57.049239 DQ8 =114, DQ9 =118, DQ10 =130, DQ11 =124
8988 19:23:57.051982 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =140
8989 19:23:57.052092
8990 19:23:57.052187
8991 19:23:57.052264
8992 19:23:57.055490 [DramC_TX_OE_Calibration] TA2
8993 19:23:57.058720 Original DQ_B0 (3 6) =30, OEN = 27
8994 19:23:57.062318 Original DQ_B1 (3 6) =30, OEN = 27
8995 19:23:57.065311 24, 0x0, End_B0=24 End_B1=24
8996 19:23:57.065396 25, 0x0, End_B0=25 End_B1=25
8997 19:23:57.069123 26, 0x0, End_B0=26 End_B1=26
8998 19:23:57.072396 27, 0x0, End_B0=27 End_B1=27
8999 19:23:57.075725 28, 0x0, End_B0=28 End_B1=28
9000 19:23:57.079375 29, 0x0, End_B0=29 End_B1=29
9001 19:23:57.079458 30, 0x0, End_B0=30 End_B1=30
9002 19:23:57.082376 31, 0x4141, End_B0=30 End_B1=30
9003 19:23:57.085425 Byte0 end_step=30 best_step=27
9004 19:23:57.088939 Byte1 end_step=30 best_step=27
9005 19:23:57.092139 Byte0 TX OE(2T, 0.5T) = (3, 3)
9006 19:23:57.095536 Byte1 TX OE(2T, 0.5T) = (3, 3)
9007 19:23:57.095619
9008 19:23:57.095683
9009 19:23:57.102361 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c06, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 395 ps
9010 19:23:57.105582 CH1 RK1: MR19=303, MR18=1C06
9011 19:23:57.112290 CH1_RK1: MR19=0x303, MR18=0x1C06, DQSOSC=395, MR23=63, INC=23, DEC=15
9012 19:23:57.115635 [RxdqsGatingPostProcess] freq 1600
9013 19:23:57.118687 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9014 19:23:57.122465 best DQS0 dly(2T, 0.5T) = (1, 1)
9015 19:23:57.125496 best DQS1 dly(2T, 0.5T) = (1, 1)
9016 19:23:57.128985 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9017 19:23:57.131973 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9018 19:23:57.135464 best DQS0 dly(2T, 0.5T) = (1, 1)
9019 19:23:57.138877 best DQS1 dly(2T, 0.5T) = (1, 1)
9020 19:23:57.142208 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9021 19:23:57.145618 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9022 19:23:57.148596 Pre-setting of DQS Precalculation
9023 19:23:57.151852 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9024 19:23:57.158622 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9025 19:23:57.165540 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9026 19:23:57.168912
9027 19:23:57.168993
9028 19:23:57.169057 [Calibration Summary] 3200 Mbps
9029 19:23:57.171569 CH 0, Rank 0
9030 19:23:57.171650 SW Impedance : PASS
9031 19:23:57.175274 DUTY Scan : NO K
9032 19:23:57.178287 ZQ Calibration : PASS
9033 19:23:57.178369 Jitter Meter : NO K
9034 19:23:57.181709 CBT Training : PASS
9035 19:23:57.184965 Write leveling : PASS
9036 19:23:57.185047 RX DQS gating : PASS
9037 19:23:57.188298 RX DQ/DQS(RDDQC) : PASS
9038 19:23:57.191713 TX DQ/DQS : PASS
9039 19:23:57.191796 RX DATLAT : PASS
9040 19:23:57.194912 RX DQ/DQS(Engine): PASS
9041 19:23:57.198218 TX OE : PASS
9042 19:23:57.198300 All Pass.
9043 19:23:57.198365
9044 19:23:57.198424 CH 0, Rank 1
9045 19:23:57.201523 SW Impedance : PASS
9046 19:23:57.205040 DUTY Scan : NO K
9047 19:23:57.205122 ZQ Calibration : PASS
9048 19:23:57.208277 Jitter Meter : NO K
9049 19:23:57.211588 CBT Training : PASS
9050 19:23:57.211669 Write leveling : PASS
9051 19:23:57.214854 RX DQS gating : PASS
9052 19:23:57.218116 RX DQ/DQS(RDDQC) : PASS
9053 19:23:57.218199 TX DQ/DQS : PASS
9054 19:23:57.221543 RX DATLAT : PASS
9055 19:23:57.221625 RX DQ/DQS(Engine): PASS
9056 19:23:57.224828 TX OE : PASS
9057 19:23:57.224910 All Pass.
9058 19:23:57.224974
9059 19:23:57.228425 CH 1, Rank 0
9060 19:23:57.228507 SW Impedance : PASS
9061 19:23:57.231408 DUTY Scan : NO K
9062 19:23:57.234671 ZQ Calibration : PASS
9063 19:23:57.234753 Jitter Meter : NO K
9064 19:23:57.238201 CBT Training : PASS
9065 19:23:57.241503 Write leveling : PASS
9066 19:23:57.241585 RX DQS gating : PASS
9067 19:23:57.245028 RX DQ/DQS(RDDQC) : PASS
9068 19:23:57.248384 TX DQ/DQS : PASS
9069 19:23:57.248473 RX DATLAT : PASS
9070 19:23:57.251178 RX DQ/DQS(Engine): PASS
9071 19:23:57.254780 TX OE : PASS
9072 19:23:57.254862 All Pass.
9073 19:23:57.254927
9074 19:23:57.254986 CH 1, Rank 1
9075 19:23:57.258060 SW Impedance : PASS
9076 19:23:57.261393 DUTY Scan : NO K
9077 19:23:57.261475 ZQ Calibration : PASS
9078 19:23:57.264737 Jitter Meter : NO K
9079 19:23:57.268169 CBT Training : PASS
9080 19:23:57.268251 Write leveling : PASS
9081 19:23:57.271514 RX DQS gating : PASS
9082 19:23:57.271596 RX DQ/DQS(RDDQC) : PASS
9083 19:23:57.274958 TX DQ/DQS : PASS
9084 19:23:57.278407 RX DATLAT : PASS
9085 19:23:57.278489 RX DQ/DQS(Engine): PASS
9086 19:23:57.281447 TX OE : PASS
9087 19:23:57.281529 All Pass.
9088 19:23:57.281594
9089 19:23:57.284886 DramC Write-DBI on
9090 19:23:57.288417 PER_BANK_REFRESH: Hybrid Mode
9091 19:23:57.288499 TX_TRACKING: ON
9092 19:23:57.298510 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9093 19:23:57.305119 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9094 19:23:57.311362 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9095 19:23:57.314525 [FAST_K] Save calibration result to emmc
9096 19:23:57.318202 sync common calibartion params.
9097 19:23:57.321626 sync cbt_mode0:1, 1:1
9098 19:23:57.324494 dram_init: ddr_geometry: 2
9099 19:23:57.324576 dram_init: ddr_geometry: 2
9100 19:23:57.327844 dram_init: ddr_geometry: 2
9101 19:23:57.331381 0:dram_rank_size:100000000
9102 19:23:57.334651 1:dram_rank_size:100000000
9103 19:23:57.338026 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9104 19:23:57.341432 DFS_SHUFFLE_HW_MODE: ON
9105 19:23:57.344376 dramc_set_vcore_voltage set vcore to 725000
9106 19:23:57.347932 Read voltage for 1600, 0
9107 19:23:57.348014 Vio18 = 0
9108 19:23:57.348079 Vcore = 725000
9109 19:23:57.350835 Vdram = 0
9110 19:23:57.350917 Vddq = 0
9111 19:23:57.350981 Vmddr = 0
9112 19:23:57.354164 switch to 3200 Mbps bootup
9113 19:23:57.357594 [DramcRunTimeConfig]
9114 19:23:57.357675 PHYPLL
9115 19:23:57.357740 DPM_CONTROL_AFTERK: ON
9116 19:23:57.360787 PER_BANK_REFRESH: ON
9117 19:23:57.364451 REFRESH_OVERHEAD_REDUCTION: ON
9118 19:23:57.364534 CMD_PICG_NEW_MODE: OFF
9119 19:23:57.367632 XRTWTW_NEW_MODE: ON
9120 19:23:57.370807 XRTRTR_NEW_MODE: ON
9121 19:23:57.370889 TX_TRACKING: ON
9122 19:23:57.374574 RDSEL_TRACKING: OFF
9123 19:23:57.374656 DQS Precalculation for DVFS: ON
9124 19:23:57.377795 RX_TRACKING: OFF
9125 19:23:57.377877 HW_GATING DBG: ON
9126 19:23:57.381264 ZQCS_ENABLE_LP4: ON
9127 19:23:57.381393 RX_PICG_NEW_MODE: ON
9128 19:23:57.384397 TX_PICG_NEW_MODE: ON
9129 19:23:57.387560 ENABLE_RX_DCM_DPHY: ON
9130 19:23:57.391021 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9131 19:23:57.391103 DUMMY_READ_FOR_TRACKING: OFF
9132 19:23:57.394256 !!! SPM_CONTROL_AFTERK: OFF
9133 19:23:57.397463 !!! SPM could not control APHY
9134 19:23:57.401256 IMPEDANCE_TRACKING: ON
9135 19:23:57.401369 TEMP_SENSOR: ON
9136 19:23:57.404156 HW_SAVE_FOR_SR: OFF
9137 19:23:57.404238 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9138 19:23:57.411047 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9139 19:23:57.411130 Read ODT Tracking: ON
9140 19:23:57.414475 Refresh Rate DeBounce: ON
9141 19:23:57.417513 DFS_NO_QUEUE_FLUSH: ON
9142 19:23:57.417595 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9143 19:23:57.420722 ENABLE_DFS_RUNTIME_MRW: OFF
9144 19:23:57.424126 DDR_RESERVE_NEW_MODE: ON
9145 19:23:57.427542 MR_CBT_SWITCH_FREQ: ON
9146 19:23:57.427624 =========================
9147 19:23:57.446859 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9148 19:23:57.450381 dram_init: ddr_geometry: 2
9149 19:23:57.468700 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9150 19:23:57.472113 dram_init: dram init end (result: 0)
9151 19:23:57.478432 DRAM-K: Full calibration passed in 24500 msecs
9152 19:23:57.481901 MRC: failed to locate region type 0.
9153 19:23:57.481983 DRAM rank0 size:0x100000000,
9154 19:23:57.485386 DRAM rank1 size=0x100000000
9155 19:23:57.495081 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9156 19:23:57.501591 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9157 19:23:57.508372 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9158 19:23:57.515059 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9159 19:23:57.518386 DRAM rank0 size:0x100000000,
9160 19:23:57.521844 DRAM rank1 size=0x100000000
9161 19:23:57.521977 CBMEM:
9162 19:23:57.525154 IMD: root @ 0xfffff000 254 entries.
9163 19:23:57.528541 IMD: root @ 0xffffec00 62 entries.
9164 19:23:57.531851 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9165 19:23:57.534862 WARNING: RO_VPD is uninitialized or empty.
9166 19:23:57.541607 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9167 19:23:57.548538 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9168 19:23:57.561199 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9169 19:23:57.572836 BS: romstage times (exec / console): total (unknown) / 23999 ms
9170 19:23:57.572919
9171 19:23:57.572984
9172 19:23:57.582577 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9173 19:23:57.586191 ARM64: Exception handlers installed.
9174 19:23:57.589533 ARM64: Testing exception
9175 19:23:57.592816 ARM64: Done test exception
9176 19:23:57.592899 Enumerating buses...
9177 19:23:57.596227 Show all devs... Before device enumeration.
9178 19:23:57.599544 Root Device: enabled 1
9179 19:23:57.602553 CPU_CLUSTER: 0: enabled 1
9180 19:23:57.602636 CPU: 00: enabled 1
9181 19:23:57.605832 Compare with tree...
9182 19:23:57.605914 Root Device: enabled 1
9183 19:23:57.609721 CPU_CLUSTER: 0: enabled 1
9184 19:23:57.612625 CPU: 00: enabled 1
9185 19:23:57.612707 Root Device scanning...
9186 19:23:57.615773 scan_static_bus for Root Device
9187 19:23:57.619554 CPU_CLUSTER: 0 enabled
9188 19:23:57.622820 scan_static_bus for Root Device done
9189 19:23:57.625623 scan_bus: bus Root Device finished in 8 msecs
9190 19:23:57.625706 done
9191 19:23:57.632610 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9192 19:23:57.635618 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9193 19:23:57.642412 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9194 19:23:57.645466 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9195 19:23:57.649067 Allocating resources...
9196 19:23:57.652125 Reading resources...
9197 19:23:57.655375 Root Device read_resources bus 0 link: 0
9198 19:23:57.655463 DRAM rank0 size:0x100000000,
9199 19:23:57.658626 DRAM rank1 size=0x100000000
9200 19:23:57.662035 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9201 19:23:57.665644 CPU: 00 missing read_resources
9202 19:23:57.671963 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9203 19:23:57.675391 Root Device read_resources bus 0 link: 0 done
9204 19:23:57.675474 Done reading resources.
9205 19:23:57.682086 Show resources in subtree (Root Device)...After reading.
9206 19:23:57.685288 Root Device child on link 0 CPU_CLUSTER: 0
9207 19:23:57.688338 CPU_CLUSTER: 0 child on link 0 CPU: 00
9208 19:23:57.698372 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9209 19:23:57.698456 CPU: 00
9210 19:23:57.701583 Root Device assign_resources, bus 0 link: 0
9211 19:23:57.705403 CPU_CLUSTER: 0 missing set_resources
9212 19:23:57.712109 Root Device assign_resources, bus 0 link: 0 done
9213 19:23:57.712191 Done setting resources.
9214 19:23:57.718443 Show resources in subtree (Root Device)...After assigning values.
9215 19:23:57.721561 Root Device child on link 0 CPU_CLUSTER: 0
9216 19:23:57.724904 CPU_CLUSTER: 0 child on link 0 CPU: 00
9217 19:23:57.735252 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9218 19:23:57.735336 CPU: 00
9219 19:23:57.738615 Done allocating resources.
9220 19:23:57.742153 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9221 19:23:57.745272 Enabling resources...
9222 19:23:57.745393 done.
9223 19:23:57.751767 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9224 19:23:57.751851 Initializing devices...
9225 19:23:57.755106 Root Device init
9226 19:23:57.755189 init hardware done!
9227 19:23:57.758699 0x00000018: ctrlr->caps
9228 19:23:57.762001 52.000 MHz: ctrlr->f_max
9229 19:23:57.762086 0.400 MHz: ctrlr->f_min
9230 19:23:57.765045 0x40ff8080: ctrlr->voltages
9231 19:23:57.765129 sclk: 390625
9232 19:23:57.768495 Bus Width = 1
9233 19:23:57.768577 sclk: 390625
9234 19:23:57.771686 Bus Width = 1
9235 19:23:57.771769 Early init status = 3
9236 19:23:57.778176 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9237 19:23:57.781490 in-header: 03 fc 00 00 01 00 00 00
9238 19:23:57.784986 in-data: 00
9239 19:23:57.788153 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9240 19:23:57.793596 in-header: 03 fd 00 00 00 00 00 00
9241 19:23:57.797185 in-data:
9242 19:23:57.800662 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9243 19:23:57.804904 in-header: 03 fc 00 00 01 00 00 00
9244 19:23:57.808214 in-data: 00
9245 19:23:57.811381 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9246 19:23:57.817099 in-header: 03 fd 00 00 00 00 00 00
9247 19:23:57.820322 in-data:
9248 19:23:57.823739 [SSUSB] Setting up USB HOST controller...
9249 19:23:57.826843 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9250 19:23:57.829944 [SSUSB] phy power-on done.
9251 19:23:57.833398 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9252 19:23:57.839806 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9253 19:23:57.843427 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9254 19:23:57.849751 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9255 19:23:57.856198 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9256 19:23:57.863141 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9257 19:23:57.869788 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9258 19:23:57.876376 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9259 19:23:57.879292 SPM: binary array size = 0x9dc
9260 19:23:57.882727 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9261 19:23:57.889468 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9262 19:23:57.896245 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9263 19:23:57.902628 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9264 19:23:57.906121 configure_display: Starting display init
9265 19:23:57.940246 anx7625_power_on_init: Init interface.
9266 19:23:57.943468 anx7625_disable_pd_protocol: Disabled PD feature.
9267 19:23:57.946494 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9268 19:23:57.974343 anx7625_start_dp_work: Secure OCM version=00
9269 19:23:57.977654 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9270 19:23:57.992765 sp_tx_get_edid_block: EDID Block = 1
9271 19:23:58.095434 Extracted contents:
9272 19:23:58.098663 header: 00 ff ff ff ff ff ff 00
9273 19:23:58.101747 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9274 19:23:58.105235 version: 01 04
9275 19:23:58.108372 basic params: 95 1f 11 78 0a
9276 19:23:58.111916 chroma info: 76 90 94 55 54 90 27 21 50 54
9277 19:23:58.115190 established: 00 00 00
9278 19:23:58.121571 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9279 19:23:58.124948 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9280 19:23:58.131642 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9281 19:23:58.138261 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9282 19:23:58.145101 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9283 19:23:58.148374 extensions: 00
9284 19:23:58.148492 checksum: fb
9285 19:23:58.148592
9286 19:23:58.151792 Manufacturer: IVO Model 57d Serial Number 0
9287 19:23:58.154758 Made week 0 of 2020
9288 19:23:58.154842 EDID version: 1.4
9289 19:23:58.158169 Digital display
9290 19:23:58.161810 6 bits per primary color channel
9291 19:23:58.161911 DisplayPort interface
9292 19:23:58.164847 Maximum image size: 31 cm x 17 cm
9293 19:23:58.168342 Gamma: 220%
9294 19:23:58.168423 Check DPMS levels
9295 19:23:58.171836 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9296 19:23:58.174590 First detailed timing is preferred timing
9297 19:23:58.178228 Established timings supported:
9298 19:23:58.181539 Standard timings supported:
9299 19:23:58.185054 Detailed timings
9300 19:23:58.188039 Hex of detail: 383680a07038204018303c0035ae10000019
9301 19:23:58.191007 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9302 19:23:58.197982 0780 0798 07c8 0820 hborder 0
9303 19:23:58.201083 0438 043b 0447 0458 vborder 0
9304 19:23:58.204460 -hsync -vsync
9305 19:23:58.204541 Did detailed timing
9306 19:23:58.211278 Hex of detail: 000000000000000000000000000000000000
9307 19:23:58.211359 Manufacturer-specified data, tag 0
9308 19:23:58.217959 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9309 19:23:58.221140 ASCII string: InfoVision
9310 19:23:58.224395 Hex of detail: 000000fe00523134304e574635205248200a
9311 19:23:58.227619 ASCII string: R140NWF5 RH
9312 19:23:58.227699 Checksum
9313 19:23:58.230849 Checksum: 0xfb (valid)
9314 19:23:58.234383 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9315 19:23:58.237729 DSI data_rate: 832800000 bps
9316 19:23:58.244103 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9317 19:23:58.247435 anx7625_parse_edid: pixelclock(138800).
9318 19:23:58.250663 hactive(1920), hsync(48), hfp(24), hbp(88)
9319 19:23:58.253960 vactive(1080), vsync(12), vfp(3), vbp(17)
9320 19:23:58.257532 anx7625_dsi_config: config dsi.
9321 19:23:58.263928 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9322 19:23:58.277009 anx7625_dsi_config: success to config DSI
9323 19:23:58.280554 anx7625_dp_start: MIPI phy setup OK.
9324 19:23:58.284000 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9325 19:23:58.287301 mtk_ddp_mode_set invalid vrefresh 60
9326 19:23:58.290697 main_disp_path_setup
9327 19:23:58.290777 ovl_layer_smi_id_en
9328 19:23:58.294108 ovl_layer_smi_id_en
9329 19:23:58.294189 ccorr_config
9330 19:23:58.294253 aal_config
9331 19:23:58.297559 gamma_config
9332 19:23:58.297639 postmask_config
9333 19:23:58.300424 dither_config
9334 19:23:58.303811 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9335 19:23:58.310178 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9336 19:23:58.313457 Root Device init finished in 555 msecs
9337 19:23:58.317156 CPU_CLUSTER: 0 init
9338 19:23:58.323681 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9339 19:23:58.326910 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9340 19:23:58.329957 APU_MBOX 0x190000b0 = 0x10001
9341 19:23:58.333387 APU_MBOX 0x190001b0 = 0x10001
9342 19:23:58.336788 APU_MBOX 0x190005b0 = 0x10001
9343 19:23:58.340181 APU_MBOX 0x190006b0 = 0x10001
9344 19:23:58.343687 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9345 19:23:58.356600 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9346 19:23:58.368680 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9347 19:23:58.375072 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9348 19:23:58.386685 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9349 19:23:58.396221 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9350 19:23:58.399200 CPU_CLUSTER: 0 init finished in 81 msecs
9351 19:23:58.402769 Devices initialized
9352 19:23:58.406073 Show all devs... After init.
9353 19:23:58.406154 Root Device: enabled 1
9354 19:23:58.409058 CPU_CLUSTER: 0: enabled 1
9355 19:23:58.412587 CPU: 00: enabled 1
9356 19:23:58.415951 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9357 19:23:58.419052 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9358 19:23:58.422523 ELOG: NV offset 0x57f000 size 0x1000
9359 19:23:58.429108 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9360 19:23:58.435941 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9361 19:23:58.439398 ELOG: Event(17) added with size 13 at 2024-04-18 19:22:45 UTC
9362 19:23:58.442378 out: cmd=0x121: 03 db 21 01 00 00 00 00
9363 19:23:58.446226 in-header: 03 33 00 00 2c 00 00 00
9364 19:23:58.459585 in-data: 2c 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9365 19:23:58.465977 ELOG: Event(A1) added with size 10 at 2024-04-18 19:22:45 UTC
9366 19:23:58.472727 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9367 19:23:58.479135 ELOG: Event(A0) added with size 9 at 2024-04-18 19:22:45 UTC
9368 19:23:58.482786 elog_add_boot_reason: Logged dev mode boot
9369 19:23:58.485598 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9370 19:23:58.489039 Finalize devices...
9371 19:23:58.489120 Devices finalized
9372 19:23:58.495716 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9373 19:23:58.499384 Writing coreboot table at 0xffe64000
9374 19:23:58.502212 0. 000000000010a000-0000000000113fff: RAMSTAGE
9375 19:23:58.505466 1. 0000000040000000-00000000400fffff: RAM
9376 19:23:58.512052 2. 0000000040100000-000000004032afff: RAMSTAGE
9377 19:23:58.515443 3. 000000004032b000-00000000545fffff: RAM
9378 19:23:58.518807 4. 0000000054600000-000000005465ffff: BL31
9379 19:23:58.522407 5. 0000000054660000-00000000ffe63fff: RAM
9380 19:23:58.528491 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9381 19:23:58.532036 7. 0000000100000000-000000023fffffff: RAM
9382 19:23:58.535285 Passing 5 GPIOs to payload:
9383 19:23:58.538431 NAME | PORT | POLARITY | VALUE
9384 19:23:58.541618 EC in RW | 0x000000aa | low | undefined
9385 19:23:58.548528 EC interrupt | 0x00000005 | low | undefined
9386 19:23:58.551418 TPM interrupt | 0x000000ab | high | undefined
9387 19:23:58.558227 SD card detect | 0x00000011 | high | undefined
9388 19:23:58.561605 speaker enable | 0x00000093 | high | undefined
9389 19:23:58.564790 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9390 19:23:58.568095 in-header: 03 f9 00 00 02 00 00 00
9391 19:23:58.571476 in-data: 02 00
9392 19:23:58.574892 ADC[4]: Raw value=901401 ID=7
9393 19:23:58.574975 ADC[3]: Raw value=213179 ID=1
9394 19:23:58.577968 RAM Code: 0x71
9395 19:23:58.581247 ADC[6]: Raw value=74502 ID=0
9396 19:23:58.581357 ADC[5]: Raw value=212072 ID=1
9397 19:23:58.585152 SKU Code: 0x1
9398 19:23:58.588030 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 7bd6
9399 19:23:58.591451 coreboot table: 964 bytes.
9400 19:23:58.594496 IMD ROOT 0. 0xfffff000 0x00001000
9401 19:23:58.597877 IMD SMALL 1. 0xffffe000 0x00001000
9402 19:23:58.601221 RO MCACHE 2. 0xffffc000 0x00001104
9403 19:23:58.604569 CONSOLE 3. 0xfff7c000 0x00080000
9404 19:23:58.607694 FMAP 4. 0xfff7b000 0x00000452
9405 19:23:58.611046 TIME STAMP 5. 0xfff7a000 0x00000910
9406 19:23:58.614566 VBOOT WORK 6. 0xfff66000 0x00014000
9407 19:23:58.617959 RAMOOPS 7. 0xffe66000 0x00100000
9408 19:23:58.621082 COREBOOT 8. 0xffe64000 0x00002000
9409 19:23:58.624174 IMD small region:
9410 19:23:58.627605 IMD ROOT 0. 0xffffec00 0x00000400
9411 19:23:58.631208 VPD 1. 0xffffeb80 0x0000006c
9412 19:23:58.634503 MMC STATUS 2. 0xffffeb60 0x00000004
9413 19:23:58.637340 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9414 19:23:58.641080 Probing TPM: done!
9415 19:23:58.644181 Connected to device vid:did:rid of 1ae0:0028:00
9416 19:23:58.654872 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9417 19:23:58.658299 Initialized TPM device CR50 revision 0
9418 19:23:58.662042 Checking cr50 for pending updates
9419 19:23:58.665794 Reading cr50 TPM mode
9420 19:23:58.674433 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9421 19:23:58.681027 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9422 19:23:58.721166 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9423 19:23:58.724403 Checking segment from ROM address 0x40100000
9424 19:23:58.727618 Checking segment from ROM address 0x4010001c
9425 19:23:58.734347 Loading segment from ROM address 0x40100000
9426 19:23:58.734430 code (compression=0)
9427 19:23:58.744375 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9428 19:23:58.750873 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9429 19:23:58.750956 it's not compressed!
9430 19:23:58.757769 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9431 19:23:58.761247 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9432 19:23:58.781494 Loading segment from ROM address 0x4010001c
9433 19:23:58.781577 Entry Point 0x80000000
9434 19:23:58.784931 Loaded segments
9435 19:23:58.788157 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9436 19:23:58.795024 Jumping to boot code at 0x80000000(0xffe64000)
9437 19:23:58.801592 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9438 19:23:58.807906 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9439 19:23:58.816071 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9440 19:23:58.819475 Checking segment from ROM address 0x40100000
9441 19:23:58.822509 Checking segment from ROM address 0x4010001c
9442 19:23:58.828990 Loading segment from ROM address 0x40100000
9443 19:23:58.829073 code (compression=1)
9444 19:23:58.835675 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9445 19:23:58.845923 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9446 19:23:58.846007 using LZMA
9447 19:23:58.854270 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9448 19:23:58.861209 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9449 19:23:58.864359 Loading segment from ROM address 0x4010001c
9450 19:23:58.864442 Entry Point 0x54601000
9451 19:23:58.867538 Loaded segments
9452 19:23:58.871131 NOTICE: MT8192 bl31_setup
9453 19:23:58.877702 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9454 19:23:58.881125 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9455 19:23:58.884516 WARNING: region 0:
9456 19:23:58.888040 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9457 19:23:58.888123 WARNING: region 1:
9458 19:23:58.894371 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9459 19:23:58.897907 WARNING: region 2:
9460 19:23:58.901229 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9461 19:23:58.904412 WARNING: region 3:
9462 19:23:58.908347 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9463 19:23:58.911505 WARNING: region 4:
9464 19:23:58.917931 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9465 19:23:58.918015 WARNING: region 5:
9466 19:23:58.921402 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9467 19:23:58.924850 WARNING: region 6:
9468 19:23:58.928140 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9469 19:23:58.928222 WARNING: region 7:
9470 19:23:58.934578 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9471 19:23:58.941775 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9472 19:23:58.945108 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9473 19:23:58.948024 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9474 19:23:58.955059 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9475 19:23:58.958346 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9476 19:23:58.961303 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9477 19:23:58.968050 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9478 19:23:58.971251 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9479 19:23:58.974975 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9480 19:23:58.981525 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9481 19:23:58.984820 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9482 19:23:58.988226 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9483 19:23:58.995092 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9484 19:23:58.998392 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9485 19:23:59.004638 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9486 19:23:59.008271 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9487 19:23:59.011681 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9488 19:23:59.018488 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9489 19:23:59.021427 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9490 19:23:59.024742 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9491 19:23:59.031403 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9492 19:23:59.035214 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9493 19:23:59.041532 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9494 19:23:59.045121 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9495 19:23:59.048203 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9496 19:23:59.054848 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9497 19:23:59.058543 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9498 19:23:59.065229 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9499 19:23:59.068184 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9500 19:23:59.071810 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9501 19:23:59.078426 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9502 19:23:59.081947 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9503 19:23:59.085007 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9504 19:23:59.092021 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9505 19:23:59.094986 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9506 19:23:59.098370 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9507 19:23:59.101733 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9508 19:23:59.108517 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9509 19:23:59.111864 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9510 19:23:59.115054 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9511 19:23:59.118443 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9512 19:23:59.124904 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9513 19:23:59.128522 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9514 19:23:59.131754 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9515 19:23:59.134774 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9516 19:23:59.141907 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9517 19:23:59.145066 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9518 19:23:59.148236 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9519 19:23:59.155142 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9520 19:23:59.158517 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9521 19:23:59.161644 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9522 19:23:59.168749 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9523 19:23:59.171752 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9524 19:23:59.178492 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9525 19:23:59.181891 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9526 19:23:59.185267 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9527 19:23:59.191983 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9528 19:23:59.195621 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9529 19:23:59.201877 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9530 19:23:59.205294 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9531 19:23:59.211606 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9532 19:23:59.215332 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9533 19:23:59.221998 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9534 19:23:59.225435 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9535 19:23:59.228534 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9536 19:23:59.235037 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9537 19:23:59.238680 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9538 19:23:59.245017 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9539 19:23:59.248540 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9540 19:23:59.255039 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9541 19:23:59.258516 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9542 19:23:59.261999 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9543 19:23:59.268606 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9544 19:23:59.272178 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9545 19:23:59.278337 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9546 19:23:59.281968 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9547 19:23:59.288613 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9548 19:23:59.291840 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9549 19:23:59.295426 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9550 19:23:59.302165 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9551 19:23:59.305481 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9552 19:23:59.312129 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9553 19:23:59.315453 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9554 19:23:59.322316 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9555 19:23:59.325541 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9556 19:23:59.328489 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9557 19:23:59.335418 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9558 19:23:59.338626 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9559 19:23:59.345394 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9560 19:23:59.348660 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9561 19:23:59.352302 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9562 19:23:59.358886 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9563 19:23:59.362484 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9564 19:23:59.368789 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9565 19:23:59.372472 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9566 19:23:59.379125 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9567 19:23:59.382644 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9568 19:23:59.385520 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9569 19:23:59.388809 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9570 19:23:59.395556 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9571 19:23:59.399006 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9572 19:23:59.402416 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9573 19:23:59.409085 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9574 19:23:59.412574 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9575 19:23:59.419343 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9576 19:23:59.422302 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9577 19:23:59.425874 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9578 19:23:59.432747 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9579 19:23:59.436107 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9580 19:23:59.439415 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9581 19:23:59.446126 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9582 19:23:59.449468 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9583 19:23:59.455906 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9584 19:23:59.459224 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9585 19:23:59.462646 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9586 19:23:59.469241 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9587 19:23:59.472513 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9588 19:23:59.476063 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9589 19:23:59.482799 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9590 19:23:59.486290 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9591 19:23:59.489257 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9592 19:23:59.492694 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9593 19:23:59.496045 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9594 19:23:59.502768 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9595 19:23:59.506249 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9596 19:23:59.512520 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9597 19:23:59.515896 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9598 19:23:59.519174 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9599 19:23:59.526051 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9600 19:23:59.529415 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9601 19:23:59.532724 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9602 19:23:59.539563 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9603 19:23:59.542957 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9604 19:23:59.549756 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9605 19:23:59.553134 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9606 19:23:59.555962 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9607 19:23:59.562890 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9608 19:23:59.566229 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9609 19:23:59.573170 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9610 19:23:59.576340 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9611 19:23:59.579513 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9612 19:23:59.586070 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9613 19:23:59.589410 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9614 19:23:59.596296 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9615 19:23:59.599726 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9616 19:23:59.602873 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9617 19:23:59.609619 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9618 19:23:59.612600 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9619 19:23:59.616028 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9620 19:23:59.622819 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9621 19:23:59.626148 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9622 19:23:59.632726 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9623 19:23:59.636055 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9624 19:23:59.639457 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9625 19:23:59.645960 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9626 19:23:59.649746 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9627 19:23:59.655701 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9628 19:23:59.659135 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9629 19:23:59.662644 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9630 19:23:59.669514 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9631 19:23:59.672469 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9632 19:23:59.675795 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9633 19:23:59.682449 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9634 19:23:59.686114 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9635 19:23:59.692445 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9636 19:23:59.695956 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9637 19:23:59.699270 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9638 19:23:59.705576 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9639 19:23:59.709174 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9640 19:23:59.715466 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9641 19:23:59.718870 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9642 19:23:59.722224 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9643 19:23:59.728759 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9644 19:23:59.732158 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9645 19:23:59.738725 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9646 19:23:59.742087 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9647 19:23:59.745593 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9648 19:23:59.752157 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9649 19:23:59.755457 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9650 19:23:59.758983 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9651 19:23:59.765408 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9652 19:23:59.768830 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9653 19:23:59.775320 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9654 19:23:59.778821 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9655 19:23:59.785138 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9656 19:23:59.789070 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9657 19:23:59.792205 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9658 19:23:59.798898 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9659 19:23:59.801770 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9660 19:23:59.808537 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9661 19:23:59.811780 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9662 19:23:59.815092 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9663 19:23:59.821913 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9664 19:23:59.825325 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9665 19:23:59.831888 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9666 19:23:59.835339 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9667 19:23:59.838706 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9668 19:23:59.845237 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9669 19:23:59.848322 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9670 19:23:59.855334 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9671 19:23:59.858361 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9672 19:23:59.864901 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9673 19:23:59.868365 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9674 19:23:59.871605 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9675 19:23:59.878257 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9676 19:23:59.881441 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9677 19:23:59.887982 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9678 19:23:59.891475 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9679 19:23:59.897816 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9680 19:23:59.901255 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9681 19:23:59.904372 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9682 19:23:59.911235 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9683 19:23:59.914561 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9684 19:23:59.921400 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9685 19:23:59.924361 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9686 19:23:59.927479 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9687 19:23:59.934439 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9688 19:23:59.937663 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9689 19:23:59.944367 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9690 19:23:59.947597 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9691 19:23:59.954483 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9692 19:23:59.957468 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9693 19:23:59.960744 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9694 19:23:59.967407 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9695 19:23:59.970592 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9696 19:23:59.977346 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9697 19:23:59.980487 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9698 19:23:59.986955 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9699 19:23:59.990510 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9700 19:23:59.993679 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9701 19:23:59.997109 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9702 19:24:00.003610 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9703 19:24:00.006740 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9704 19:24:00.010121 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9705 19:24:00.013789 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9706 19:24:00.020277 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9707 19:24:00.023403 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9708 19:24:00.030177 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9709 19:24:00.033478 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9710 19:24:00.036928 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9711 19:24:00.043362 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9712 19:24:00.046662 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9713 19:24:00.053592 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9714 19:24:00.056480 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9715 19:24:00.060003 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9716 19:24:00.066472 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9717 19:24:00.069847 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9718 19:24:00.073219 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9719 19:24:00.080047 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9720 19:24:00.083263 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9721 19:24:00.086765 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9722 19:24:00.093236 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9723 19:24:00.096412 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9724 19:24:00.099769 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9725 19:24:00.106616 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9726 19:24:00.109621 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9727 19:24:00.116786 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9728 19:24:00.119858 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9729 19:24:00.123456 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9730 19:24:00.129440 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9731 19:24:00.132862 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9732 19:24:00.136324 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9733 19:24:00.142932 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9734 19:24:00.146269 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9735 19:24:00.149740 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9736 19:24:00.156399 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9737 19:24:00.159354 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9738 19:24:00.166205 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9739 19:24:00.169489 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9740 19:24:00.172705 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9741 19:24:00.176235 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9742 19:24:00.182433 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9743 19:24:00.185972 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9744 19:24:00.189142 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9745 19:24:00.192606 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9746 19:24:00.199429 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9747 19:24:00.202788 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9748 19:24:00.205895 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9749 19:24:00.209203 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9750 19:24:00.215671 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9751 19:24:00.219425 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9752 19:24:00.222271 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9753 19:24:00.229106 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9754 19:24:00.232492 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9755 19:24:00.235606 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9756 19:24:00.242315 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9757 19:24:00.245521 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9758 19:24:00.252262 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9759 19:24:00.255666 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9760 19:24:00.258975 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9761 19:24:00.265588 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9762 19:24:00.269078 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9763 19:24:00.275540 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9764 19:24:00.279077 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9765 19:24:00.285541 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9766 19:24:00.288864 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9767 19:24:00.292203 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9768 19:24:00.298998 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9769 19:24:00.302015 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9770 19:24:00.308837 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9771 19:24:00.312061 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9772 19:24:00.315530 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9773 19:24:00.322083 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9774 19:24:00.325505 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9775 19:24:00.332160 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9776 19:24:00.335484 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9777 19:24:00.338831 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9778 19:24:00.345195 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9779 19:24:00.348725 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9780 19:24:00.355409 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9781 19:24:00.358844 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9782 19:24:00.365025 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9783 19:24:00.368421 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9784 19:24:00.371862 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9785 19:24:00.378423 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9786 19:24:00.381855 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9787 19:24:00.388662 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9788 19:24:00.391670 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9789 19:24:00.394865 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9790 19:24:00.401538 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9791 19:24:00.405132 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9792 19:24:00.411435 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9793 19:24:00.414647 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9794 19:24:00.418134 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9795 19:24:00.424721 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9796 19:24:00.428267 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9797 19:24:00.434728 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9798 19:24:00.438074 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9799 19:24:00.444711 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9800 19:24:00.447740 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9801 19:24:00.451207 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9802 19:24:00.457737 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9803 19:24:00.461079 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9804 19:24:00.467632 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9805 19:24:00.470656 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9806 19:24:00.474003 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9807 19:24:00.480767 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9808 19:24:00.484101 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9809 19:24:00.490967 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9810 19:24:00.493924 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9811 19:24:00.497394 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9812 19:24:00.504224 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9813 19:24:00.507236 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9814 19:24:00.514047 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9815 19:24:00.517357 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9816 19:24:00.520563 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9817 19:24:00.527226 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9818 19:24:00.530699 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9819 19:24:00.537491 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9820 19:24:00.540615 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9821 19:24:00.547053 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9822 19:24:00.550378 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9823 19:24:00.553820 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9824 19:24:00.560639 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9825 19:24:00.564047 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9826 19:24:00.570543 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9827 19:24:00.574143 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9828 19:24:00.577115 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9829 19:24:00.583906 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9830 19:24:00.587202 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9831 19:24:00.593892 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9832 19:24:00.597411 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9833 19:24:00.604144 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9834 19:24:00.607081 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9835 19:24:00.610482 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9836 19:24:00.617626 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9837 19:24:00.620911 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9838 19:24:00.627678 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9839 19:24:00.630915 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9840 19:24:00.634325 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9841 19:24:00.640521 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9842 19:24:00.643696 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9843 19:24:00.650492 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9844 19:24:00.653734 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9845 19:24:00.660484 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9846 19:24:00.663738 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9847 19:24:00.670509 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9848 19:24:00.673642 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9849 19:24:00.677076 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9850 19:24:00.683476 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9851 19:24:00.686547 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9852 19:24:00.693676 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9853 19:24:00.696703 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9854 19:24:00.703306 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9855 19:24:00.706663 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9856 19:24:00.713602 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9857 19:24:00.716431 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9858 19:24:00.720097 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9859 19:24:00.726764 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9860 19:24:00.730050 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9861 19:24:00.736668 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9862 19:24:00.740011 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9863 19:24:00.746180 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9864 19:24:00.749508 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9865 19:24:00.756478 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9866 19:24:00.759912 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9867 19:24:00.762993 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9868 19:24:00.769453 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9869 19:24:00.772570 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9870 19:24:00.779405 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9871 19:24:00.782556 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9872 19:24:00.789428 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9873 19:24:00.792413 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9874 19:24:00.796098 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9875 19:24:00.802476 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9876 19:24:00.805953 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9877 19:24:00.812726 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9878 19:24:00.815547 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9879 19:24:00.822315 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9880 19:24:00.825348 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9881 19:24:00.832017 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9882 19:24:00.835308 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9883 19:24:00.842065 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9884 19:24:00.845436 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9885 19:24:00.852312 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9886 19:24:00.855560 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9887 19:24:00.862061 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9888 19:24:00.865833 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9889 19:24:00.872289 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9890 19:24:00.875510 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9891 19:24:00.882099 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9892 19:24:00.885698 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9893 19:24:00.892163 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9894 19:24:00.895539 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9895 19:24:00.902020 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9896 19:24:00.905570 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9897 19:24:00.912018 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9898 19:24:00.915800 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9899 19:24:00.921906 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9900 19:24:00.925433 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9901 19:24:00.931841 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9902 19:24:00.935526 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9903 19:24:00.942000 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9904 19:24:00.945224 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9905 19:24:00.948702 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9906 19:24:00.952243 INFO: [APUAPC] vio 0
9907 19:24:00.958504 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9908 19:24:00.962012 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9909 19:24:00.965252 INFO: [APUAPC] D0_APC_0: 0x400510
9910 19:24:00.968496 INFO: [APUAPC] D0_APC_1: 0x0
9911 19:24:00.971676 INFO: [APUAPC] D0_APC_2: 0x1540
9912 19:24:00.975332 INFO: [APUAPC] D0_APC_3: 0x0
9913 19:24:00.978241 INFO: [APUAPC] D1_APC_0: 0xffffffff
9914 19:24:00.981800 INFO: [APUAPC] D1_APC_1: 0xffffffff
9915 19:24:00.984931 INFO: [APUAPC] D1_APC_2: 0x3fffff
9916 19:24:00.985017 INFO: [APUAPC] D1_APC_3: 0x0
9917 19:24:00.991574 INFO: [APUAPC] D2_APC_0: 0xffffffff
9918 19:24:00.994810 INFO: [APUAPC] D2_APC_1: 0xffffffff
9919 19:24:00.998431 INFO: [APUAPC] D2_APC_2: 0x3fffff
9920 19:24:00.998513 INFO: [APUAPC] D2_APC_3: 0x0
9921 19:24:01.001585 INFO: [APUAPC] D3_APC_0: 0xffffffff
9922 19:24:01.004818 INFO: [APUAPC] D3_APC_1: 0xffffffff
9923 19:24:01.008206 INFO: [APUAPC] D3_APC_2: 0x3fffff
9924 19:24:01.011816 INFO: [APUAPC] D3_APC_3: 0x0
9925 19:24:01.014591 INFO: [APUAPC] D4_APC_0: 0xffffffff
9926 19:24:01.018066 INFO: [APUAPC] D4_APC_1: 0xffffffff
9927 19:24:01.021277 INFO: [APUAPC] D4_APC_2: 0x3fffff
9928 19:24:01.024761 INFO: [APUAPC] D4_APC_3: 0x0
9929 19:24:01.028066 INFO: [APUAPC] D5_APC_0: 0xffffffff
9930 19:24:01.031202 INFO: [APUAPC] D5_APC_1: 0xffffffff
9931 19:24:01.034650 INFO: [APUAPC] D5_APC_2: 0x3fffff
9932 19:24:01.037913 INFO: [APUAPC] D5_APC_3: 0x0
9933 19:24:01.041212 INFO: [APUAPC] D6_APC_0: 0xffffffff
9934 19:24:01.044547 INFO: [APUAPC] D6_APC_1: 0xffffffff
9935 19:24:01.047647 INFO: [APUAPC] D6_APC_2: 0x3fffff
9936 19:24:01.050995 INFO: [APUAPC] D6_APC_3: 0x0
9937 19:24:01.054561 INFO: [APUAPC] D7_APC_0: 0xffffffff
9938 19:24:01.057940 INFO: [APUAPC] D7_APC_1: 0xffffffff
9939 19:24:01.061146 INFO: [APUAPC] D7_APC_2: 0x3fffff
9940 19:24:01.064625 INFO: [APUAPC] D7_APC_3: 0x0
9941 19:24:01.067993 INFO: [APUAPC] D8_APC_0: 0xffffffff
9942 19:24:01.071232 INFO: [APUAPC] D8_APC_1: 0xffffffff
9943 19:24:01.074591 INFO: [APUAPC] D8_APC_2: 0x3fffff
9944 19:24:01.077820 INFO: [APUAPC] D8_APC_3: 0x0
9945 19:24:01.080828 INFO: [APUAPC] D9_APC_0: 0xffffffff
9946 19:24:01.084220 INFO: [APUAPC] D9_APC_1: 0xffffffff
9947 19:24:01.087615 INFO: [APUAPC] D9_APC_2: 0x3fffff
9948 19:24:01.091165 INFO: [APUAPC] D9_APC_3: 0x0
9949 19:24:01.094236 INFO: [APUAPC] D10_APC_0: 0xffffffff
9950 19:24:01.097405 INFO: [APUAPC] D10_APC_1: 0xffffffff
9951 19:24:01.100574 INFO: [APUAPC] D10_APC_2: 0x3fffff
9952 19:24:01.103869 INFO: [APUAPC] D10_APC_3: 0x0
9953 19:24:01.107767 INFO: [APUAPC] D11_APC_0: 0xffffffff
9954 19:24:01.110578 INFO: [APUAPC] D11_APC_1: 0xffffffff
9955 19:24:01.113956 INFO: [APUAPC] D11_APC_2: 0x3fffff
9956 19:24:01.117257 INFO: [APUAPC] D11_APC_3: 0x0
9957 19:24:01.120587 INFO: [APUAPC] D12_APC_0: 0xffffffff
9958 19:24:01.123916 INFO: [APUAPC] D12_APC_1: 0xffffffff
9959 19:24:01.127243 INFO: [APUAPC] D12_APC_2: 0x3fffff
9960 19:24:01.130654 INFO: [APUAPC] D12_APC_3: 0x0
9961 19:24:01.133976 INFO: [APUAPC] D13_APC_0: 0xffffffff
9962 19:24:01.137440 INFO: [APUAPC] D13_APC_1: 0xffffffff
9963 19:24:01.140408 INFO: [APUAPC] D13_APC_2: 0x3fffff
9964 19:24:01.143622 INFO: [APUAPC] D13_APC_3: 0x0
9965 19:24:01.146987 INFO: [APUAPC] D14_APC_0: 0xffffffff
9966 19:24:01.150279 INFO: [APUAPC] D14_APC_1: 0xffffffff
9967 19:24:01.153666 INFO: [APUAPC] D14_APC_2: 0x3fffff
9968 19:24:01.157162 INFO: [APUAPC] D14_APC_3: 0x0
9969 19:24:01.160520 INFO: [APUAPC] D15_APC_0: 0xffffffff
9970 19:24:01.163575 INFO: [APUAPC] D15_APC_1: 0xffffffff
9971 19:24:01.166946 INFO: [APUAPC] D15_APC_2: 0x3fffff
9972 19:24:01.170360 INFO: [APUAPC] D15_APC_3: 0x0
9973 19:24:01.173643 INFO: [APUAPC] APC_CON: 0x4
9974 19:24:01.177045 INFO: [NOCDAPC] D0_APC_0: 0x0
9975 19:24:01.180360 INFO: [NOCDAPC] D0_APC_1: 0x0
9976 19:24:01.183461 INFO: [NOCDAPC] D1_APC_0: 0x0
9977 19:24:01.186978 INFO: [NOCDAPC] D1_APC_1: 0xfff
9978 19:24:01.187078 INFO: [NOCDAPC] D2_APC_0: 0x0
9979 19:24:01.190085 INFO: [NOCDAPC] D2_APC_1: 0xfff
9980 19:24:01.193730 INFO: [NOCDAPC] D3_APC_0: 0x0
9981 19:24:01.196943 INFO: [NOCDAPC] D3_APC_1: 0xfff
9982 19:24:01.200590 INFO: [NOCDAPC] D4_APC_0: 0x0
9983 19:24:01.203536 INFO: [NOCDAPC] D4_APC_1: 0xfff
9984 19:24:01.206821 INFO: [NOCDAPC] D5_APC_0: 0x0
9985 19:24:01.210060 INFO: [NOCDAPC] D5_APC_1: 0xfff
9986 19:24:01.213274 INFO: [NOCDAPC] D6_APC_0: 0x0
9987 19:24:01.216804 INFO: [NOCDAPC] D6_APC_1: 0xfff
9988 19:24:01.216892 INFO: [NOCDAPC] D7_APC_0: 0x0
9989 19:24:01.220202 INFO: [NOCDAPC] D7_APC_1: 0xfff
9990 19:24:01.223669 INFO: [NOCDAPC] D8_APC_0: 0x0
9991 19:24:01.227057 INFO: [NOCDAPC] D8_APC_1: 0xfff
9992 19:24:01.230359 INFO: [NOCDAPC] D9_APC_0: 0x0
9993 19:24:01.233266 INFO: [NOCDAPC] D9_APC_1: 0xfff
9994 19:24:01.236782 INFO: [NOCDAPC] D10_APC_0: 0x0
9995 19:24:01.239925 INFO: [NOCDAPC] D10_APC_1: 0xfff
9996 19:24:01.243400 INFO: [NOCDAPC] D11_APC_0: 0x0
9997 19:24:01.246720 INFO: [NOCDAPC] D11_APC_1: 0xfff
9998 19:24:01.249954 INFO: [NOCDAPC] D12_APC_0: 0x0
9999 19:24:01.253366 INFO: [NOCDAPC] D12_APC_1: 0xfff
10000 19:24:01.256637 INFO: [NOCDAPC] D13_APC_0: 0x0
10001 19:24:01.260097 INFO: [NOCDAPC] D13_APC_1: 0xfff
10002 19:24:01.260180 INFO: [NOCDAPC] D14_APC_0: 0x0
10003 19:24:01.263212 INFO: [NOCDAPC] D14_APC_1: 0xfff
10004 19:24:01.266565 INFO: [NOCDAPC] D15_APC_0: 0x0
10005 19:24:01.270042 INFO: [NOCDAPC] D15_APC_1: 0xfff
10006 19:24:01.273579 INFO: [NOCDAPC] APC_CON: 0x4
10007 19:24:01.276411 INFO: [APUAPC] set_apusys_apc done
10008 19:24:01.279761 INFO: [DEVAPC] devapc_init done
10009 19:24:01.283280 INFO: GICv3 without legacy support detected.
10010 19:24:01.289641 INFO: ARM GICv3 driver initialized in EL3
10011 19:24:01.293291 INFO: Maximum SPI INTID supported: 639
10012 19:24:01.296509 INFO: BL31: Initializing runtime services
10013 19:24:01.303230 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10014 19:24:01.303332 INFO: SPM: enable CPC mode
10015 19:24:01.309922 INFO: mcdi ready for mcusys-off-idle and system suspend
10016 19:24:01.313035 INFO: BL31: Preparing for EL3 exit to normal world
10017 19:24:01.316453 INFO: Entry point address = 0x80000000
10018 19:24:01.319963 INFO: SPSR = 0x8
10019 19:24:01.325397
10020 19:24:01.325491
10021 19:24:01.325590
10022 19:24:01.328776 Starting depthcharge on Spherion...
10023 19:24:01.328846
10024 19:24:01.328984 Wipe memory regions:
10025 19:24:01.329105
10026 19:24:01.329804 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10027 19:24:01.329910 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10028 19:24:01.330027 Setting prompt string to ['asurada:']
10029 19:24:01.330138 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10030 19:24:01.332135 [0x00000040000000, 0x00000054600000)
10031 19:24:01.454548
10032 19:24:01.454698 [0x00000054660000, 0x00000080000000)
10033 19:24:01.715126
10034 19:24:01.715270 [0x000000821a7280, 0x000000ffe64000)
10035 19:24:02.460474
10036 19:24:02.460648 [0x00000100000000, 0x00000240000000)
10037 19:24:04.350718
10038 19:24:04.354129 Initializing XHCI USB controller at 0x11200000.
10039 19:24:05.392121
10040 19:24:05.395605 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10041 19:24:05.396084
10042 19:24:05.396450
10043 19:24:05.396797
10044 19:24:05.397603 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10046 19:24:05.498791 asurada: tftpboot 192.168.201.1 13420357/tftp-deploy-lhsbc3e1/kernel/image.itb 13420357/tftp-deploy-lhsbc3e1/kernel/cmdline
10047 19:24:05.499349 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10048 19:24:05.499795 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10049 19:24:05.503837 tftpboot 192.168.201.1 13420357/tftp-deploy-lhsbc3e1/kernel/image.itp-deploy-lhsbc3e1/kernel/cmdline
10050 19:24:05.504315
10051 19:24:05.504687 Waiting for link
10052 19:24:05.664484
10053 19:24:05.665006 R8152: Initializing
10054 19:24:05.665442
10055 19:24:05.667701 Version 9 (ocp_data = 6010)
10056 19:24:05.668171
10057 19:24:05.670847 R8152: Done initializing
10058 19:24:05.671315
10059 19:24:05.671683 Adding net device
10060 19:24:07.613257
10061 19:24:07.613433 done.
10062 19:24:07.613501
10063 19:24:07.613563 MAC: 00:e0:4c:72:2d:d6
10064 19:24:07.613623
10065 19:24:07.616476 Sending DHCP discover... done.
10066 19:24:07.616560
10067 19:24:07.619652 Waiting for reply... done.
10068 19:24:07.619736
10069 19:24:07.622846 Sending DHCP request... done.
10070 19:24:07.622929
10071 19:24:07.622996 Waiting for reply... done.
10072 19:24:07.623058
10073 19:24:07.626110 My ip is 192.168.201.21
10074 19:24:07.626218
10075 19:24:07.629724 The DHCP server ip is 192.168.201.1
10076 19:24:07.629808
10077 19:24:07.632938 TFTP server IP predefined by user: 192.168.201.1
10078 19:24:07.633022
10079 19:24:07.639391 Bootfile predefined by user: 13420357/tftp-deploy-lhsbc3e1/kernel/image.itb
10080 19:24:07.639475
10081 19:24:07.642796 Sending tftp read request... done.
10082 19:24:07.642880
10083 19:24:07.646180 Waiting for the transfer...
10084 19:24:07.646263
10085 19:24:07.916337 00000000 ################################################################
10086 19:24:07.916471
10087 19:24:08.185857 00080000 ################################################################
10088 19:24:08.185993
10089 19:24:08.448979 00100000 ################################################################
10090 19:24:08.449108
10091 19:24:08.712432 00180000 ################################################################
10092 19:24:08.712571
10093 19:24:08.978499 00200000 ################################################################
10094 19:24:08.978641
10095 19:24:09.228607 00280000 ################################################################
10096 19:24:09.228743
10097 19:24:09.478108 00300000 ################################################################
10098 19:24:09.478239
10099 19:24:09.727622 00380000 ################################################################
10100 19:24:09.727761
10101 19:24:09.973898 00400000 ################################################################
10102 19:24:09.974031
10103 19:24:10.226543 00480000 ################################################################
10104 19:24:10.226679
10105 19:24:10.497931 00500000 ################################################################
10106 19:24:10.498053
10107 19:24:10.763080 00580000 ################################################################
10108 19:24:10.763210
10109 19:24:11.055628 00600000 ################################################################
10110 19:24:11.055760
10111 19:24:11.351600 00680000 ################################################################
10112 19:24:11.351727
10113 19:24:11.647669 00700000 ################################################################
10114 19:24:11.647795
10115 19:24:11.934638 00780000 ################################################################
10116 19:24:11.934767
10117 19:24:12.235219 00800000 ################################################################
10118 19:24:12.235347
10119 19:24:12.517650 00880000 ################################################################
10120 19:24:12.517783
10121 19:24:12.781193 00900000 ################################################################
10122 19:24:12.781372
10123 19:24:13.029798 00980000 ################################################################
10124 19:24:13.029930
10125 19:24:13.278547 00a00000 ################################################################
10126 19:24:13.278696
10127 19:24:13.533536 00a80000 ################################################################
10128 19:24:13.533661
10129 19:24:13.799227 00b00000 ################################################################
10130 19:24:13.799388
10131 19:24:14.081869 00b80000 ################################################################
10132 19:24:14.082011
10133 19:24:14.378820 00c00000 ################################################################
10134 19:24:14.378950
10135 19:24:14.629764 00c80000 ################################################################
10136 19:24:14.629931
10137 19:24:14.894293 00d00000 ################################################################
10138 19:24:14.894430
10139 19:24:15.174298 00d80000 ################################################################
10140 19:24:15.174434
10141 19:24:15.439819 00e00000 ################################################################
10142 19:24:15.439973
10143 19:24:15.710804 00e80000 ################################################################
10144 19:24:15.710952
10145 19:24:15.961069 00f00000 ################################################################
10146 19:24:15.961195
10147 19:24:16.255353 00f80000 ################################################################
10148 19:24:16.255485
10149 19:24:16.551687 01000000 ################################################################
10150 19:24:16.551815
10151 19:24:16.835636 01080000 ################################################################
10152 19:24:16.835794
10153 19:24:17.128141 01100000 ################################################################
10154 19:24:17.128275
10155 19:24:17.499606 01180000 ################################################################
10156 19:24:17.500157
10157 19:24:17.871193 01200000 ################################################################
10158 19:24:17.871762
10159 19:24:18.253128 01280000 ################################################################
10160 19:24:18.253667
10161 19:24:18.644135 01300000 ################################################################
10162 19:24:18.644646
10163 19:24:19.028659 01380000 ################################################################
10164 19:24:19.029192
10165 19:24:19.420712 01400000 ################################################################
10166 19:24:19.421211
10167 19:24:19.811410 01480000 ################################################################
10168 19:24:19.811933
10169 19:24:20.216398 01500000 ################################################################
10170 19:24:20.216952
10171 19:24:20.508979 01580000 ################################################################
10172 19:24:20.509148
10173 19:24:20.774562 01600000 ################################################################
10174 19:24:20.774715
10175 19:24:21.024952 01680000 ################################################################
10176 19:24:21.025121
10177 19:24:21.279675 01700000 ################################################################
10178 19:24:21.279820
10179 19:24:21.531607 01780000 ################################################################
10180 19:24:21.531749
10181 19:24:21.794806 01800000 ################################################################
10182 19:24:21.794955
10183 19:24:22.079735 01880000 ################################################################
10184 19:24:22.079884
10185 19:24:22.383135 01900000 ################################################################
10186 19:24:22.383646
10187 19:24:22.705263 01980000 ################################################################
10188 19:24:22.705440
10189 19:24:23.084821 01a00000 ################################################################
10190 19:24:23.085487
10191 19:24:23.384925 01a80000 ################################################################
10192 19:24:23.385077
10193 19:24:23.732803 01b00000 ################################################################
10194 19:24:23.732962
10195 19:24:24.012951 01b80000 ################################################################
10196 19:24:24.013100
10197 19:24:24.306064 01c00000 ################################################################
10198 19:24:24.306191
10199 19:24:24.569245 01c80000 ################################################################
10200 19:24:24.569381
10201 19:24:24.818149 01d00000 ################################################################
10202 19:24:24.818273
10203 19:24:25.066894 01d80000 ################################################################
10204 19:24:25.067056
10205 19:24:25.316752 01e00000 ################################################################
10206 19:24:25.316906
10207 19:24:25.582257 01e80000 ################################################################
10208 19:24:25.582377
10209 19:24:25.879119 01f00000 ################################################################
10210 19:24:25.879247
10211 19:24:26.172357 01f80000 ################################################################
10212 19:24:26.172493
10213 19:24:26.460042 02000000 ################################################################
10214 19:24:26.460195
10215 19:24:26.757209 02080000 ################################################################
10216 19:24:26.757384
10217 19:24:27.051894 02100000 ################################################################
10218 19:24:27.052082
10219 19:24:27.423396 02180000 ################################################################
10220 19:24:27.423617
10221 19:24:27.716527 02200000 ################################################################
10222 19:24:27.716682
10223 19:24:28.015756 02280000 ################################################################
10224 19:24:28.015880
10225 19:24:28.412059 02300000 ################################################################
10226 19:24:28.412352
10227 19:24:28.708971 02380000 ################################################################
10228 19:24:28.709114
10229 19:24:28.957962 02400000 ################################################################
10230 19:24:28.958094
10231 19:24:29.207035 02480000 ################################################################
10232 19:24:29.207168
10233 19:24:29.456306 02500000 ################################################################
10234 19:24:29.456449
10235 19:24:29.710332 02580000 ################################################################
10236 19:24:29.710530
10237 19:24:29.966301 02600000 ################################################################
10238 19:24:29.966443
10239 19:24:30.235339 02680000 ################################################################
10240 19:24:30.235490
10241 19:24:30.514462 02700000 ################################################################
10242 19:24:30.514637
10243 19:24:30.801507 02780000 ################################################################
10244 19:24:30.801657
10245 19:24:31.089112 02800000 ################################################################
10246 19:24:31.089262
10247 19:24:31.385569 02880000 ################################################################
10248 19:24:31.385731
10249 19:24:31.684577 02900000 ################################################################
10250 19:24:31.684723
10251 19:24:31.957743 02980000 ################################################################
10252 19:24:31.957901
10253 19:24:32.219360 02a00000 ################################################################
10254 19:24:32.219509
10255 19:24:32.468925 02a80000 ################################################################
10256 19:24:32.469076
10257 19:24:32.717945 02b00000 ################################################################
10258 19:24:32.718074
10259 19:24:32.967112 02b80000 ################################################################
10260 19:24:32.967243
10261 19:24:33.242286 02c00000 ################################################################
10262 19:24:33.242423
10263 19:24:33.510060 02c80000 ################################################################
10264 19:24:33.510185
10265 19:24:33.809938 02d00000 ################################################################
10266 19:24:33.810080
10267 19:24:34.087646 02d80000 ################################################################
10268 19:24:34.087851
10269 19:24:34.373688 02e00000 ################################################################
10270 19:24:34.373839
10271 19:24:34.625795 02e80000 ################################################################
10272 19:24:34.625931
10273 19:24:34.880883 02f00000 ################################################################
10274 19:24:34.881016
10275 19:24:35.148014 02f80000 ################################################################
10276 19:24:35.148150
10277 19:24:35.403475 03000000 ################################################################
10278 19:24:35.403608
10279 19:24:35.653615 03080000 ################################################################
10280 19:24:35.653761
10281 19:24:35.903364 03100000 ################################################################
10282 19:24:35.903528
10283 19:24:36.154409 03180000 ################################################################
10284 19:24:36.154568
10285 19:24:36.403630 03200000 ################################################################
10286 19:24:36.403780
10287 19:24:36.653994 03280000 ################################################################
10288 19:24:36.654121
10289 19:24:36.902208 03300000 ################################################################
10290 19:24:36.902330
10291 19:24:37.013650 03380000 ########################### done.
10292 19:24:37.013759
10293 19:24:37.016373 The bootfile was 54215710 bytes long.
10294 19:24:37.016462
10295 19:24:37.019799 Sending tftp read request... done.
10296 19:24:37.019895
10297 19:24:37.023057 Waiting for the transfer...
10298 19:24:37.023153
10299 19:24:37.023228 00000000 # done.
10300 19:24:37.023299
10301 19:24:37.030139 Command line loaded dynamically from TFTP file: 13420357/tftp-deploy-lhsbc3e1/kernel/cmdline
10302 19:24:37.032911
10303 19:24:37.046342 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10304 19:24:37.046469
10305 19:24:37.046565 Loading FIT.
10306 19:24:37.046655
10307 19:24:37.049875 Image ramdisk-1 has 41256090 bytes.
10308 19:24:37.050028
10309 19:24:37.053142 Image fdt-1 has 47230 bytes.
10310 19:24:37.053277
10311 19:24:37.056226 Image kernel-1 has 12910355 bytes.
10312 19:24:37.056410
10313 19:24:37.062886 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10314 19:24:37.063024
10315 19:24:37.083241 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10316 19:24:37.083469
10317 19:24:37.086237 Choosing best match conf-1 for compat google,spherion-rev2.
10318 19:24:37.090859
10319 19:24:37.095724 Connected to device vid:did:rid of 1ae0:0028:00
10320 19:24:37.103465
10321 19:24:37.106991 tpm_get_response: command 0x17b, return code 0x0
10322 19:24:37.107127
10323 19:24:37.110102 ec_init: CrosEC protocol v3 supported (256, 248)
10324 19:24:37.115416
10325 19:24:37.118680 tpm_cleanup: add release locality here.
10326 19:24:37.118819
10327 19:24:37.118932 Shutting down all USB controllers.
10328 19:24:37.121964
10329 19:24:37.122099 Removing current net device
10330 19:24:37.122249
10331 19:24:37.128832 Exiting depthcharge with code 4 at timestamp: 65100823
10332 19:24:37.128969
10333 19:24:37.131955 LZMA decompressing kernel-1 to 0x821a6718
10334 19:24:37.132092
10335 19:24:37.135349 LZMA decompressing kernel-1 to 0x40000000
10336 19:24:38.730683
10337 19:24:38.731220 jumping to kernel
10338 19:24:38.733592 end: 2.2.4 bootloader-commands (duration 00:00:37) [common]
10339 19:24:38.734147 start: 2.2.5 auto-login-action (timeout 00:03:48) [common]
10340 19:24:38.734564 Setting prompt string to ['Linux version [0-9]']
10341 19:24:38.734952 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10342 19:24:38.735345 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10343 19:24:38.812445
10344 19:24:38.815918 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10345 19:24:38.819140 start: 2.2.5.1 login-action (timeout 00:03:48) [common]
10346 19:24:38.819233 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10347 19:24:38.819305 Setting prompt string to []
10348 19:24:38.819387 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10349 19:24:38.819462 Using line separator: #'\n'#
10350 19:24:38.819522 No login prompt set.
10351 19:24:38.819585 Parsing kernel messages
10352 19:24:38.819641 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10353 19:24:38.819741 [login-action] Waiting for messages, (timeout 00:03:48)
10354 19:24:38.819805 Waiting using forced prompt support (timeout 00:01:54)
10355 19:24:38.838581 [ 0.000000] Linux version 6.1.86-cip19 (KernelCI@build-j170728-arm64-gcc-10-defconfig-arm64-chromebook-wrkxq) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Apr 18 19:05:54 UTC 2024
10356 19:24:38.841778 [ 0.000000] random: crng init done
10357 19:24:38.848794 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10358 19:24:38.851703 [ 0.000000] efi: UEFI not found.
10359 19:24:38.858533 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10360 19:24:38.864950 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10361 19:24:38.875544 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10362 19:24:38.885081 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10363 19:24:38.891910 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10364 19:24:38.898155 [ 0.000000] printk: bootconsole [mtk8250] enabled
10365 19:24:38.905023 [ 0.000000] NUMA: No NUMA configuration found
10366 19:24:38.911300 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10367 19:24:38.914962 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10368 19:24:38.918089 [ 0.000000] Zone ranges:
10369 19:24:38.925572 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10370 19:24:38.927834 [ 0.000000] DMA32 empty
10371 19:24:38.934557 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10372 19:24:38.938202 [ 0.000000] Movable zone start for each node
10373 19:24:38.941302 [ 0.000000] Early memory node ranges
10374 19:24:38.947710 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10375 19:24:38.954386 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10376 19:24:38.961145 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10377 19:24:38.967794 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10378 19:24:38.974558 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10379 19:24:38.981198 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10380 19:24:39.036927 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10381 19:24:39.043866 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10382 19:24:39.050748 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10383 19:24:39.053780 [ 0.000000] psci: probing for conduit method from DT.
10384 19:24:39.060010 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10385 19:24:39.063779 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10386 19:24:39.070327 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10387 19:24:39.073704 [ 0.000000] psci: SMC Calling Convention v1.2
10388 19:24:39.080422 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10389 19:24:39.083935 [ 0.000000] Detected VIPT I-cache on CPU0
10390 19:24:39.090030 [ 0.000000] CPU features: detected: GIC system register CPU interface
10391 19:24:39.097003 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10392 19:24:39.103457 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10393 19:24:39.110003 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10394 19:24:39.116835 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10395 19:24:39.123375 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10396 19:24:39.130089 [ 0.000000] alternatives: applying boot alternatives
10397 19:24:39.133690 [ 0.000000] Fallback order for Node 0: 0
10398 19:24:39.140190 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10399 19:24:39.143530 [ 0.000000] Policy zone: Normal
10400 19:24:39.160100 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10401 19:24:39.170190 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10402 19:24:39.181275 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10403 19:24:39.191219 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10404 19:24:39.197781 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10405 19:24:39.201161 <6>[ 0.000000] software IO TLB: area num 8.
10406 19:24:39.257947 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10407 19:24:39.407395 <6>[ 0.000000] Memory: 7924284K/8385536K available (18048K kernel code, 4118K rwdata, 22288K rodata, 8448K init, 616K bss, 428484K reserved, 32768K cma-reserved)
10408 19:24:39.414194 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10409 19:24:39.420554 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10410 19:24:39.423888 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10411 19:24:39.430550 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10412 19:24:39.437153 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10413 19:24:39.440593 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10414 19:24:39.450613 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10415 19:24:39.457207 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10416 19:24:39.463465 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10417 19:24:39.470125 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10418 19:24:39.473493 <6>[ 0.000000] GICv3: 608 SPIs implemented
10419 19:24:39.476696 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10420 19:24:39.483607 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10421 19:24:39.486950 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10422 19:24:39.493390 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10423 19:24:39.506511 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10424 19:24:39.519979 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10425 19:24:39.526652 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10426 19:24:39.533958 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10427 19:24:39.547507 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10428 19:24:39.553743 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10429 19:24:39.560888 <6>[ 0.009232] Console: colour dummy device 80x25
10430 19:24:39.570509 <6>[ 0.013951] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10431 19:24:39.577218 <6>[ 0.024458] pid_max: default: 32768 minimum: 301
10432 19:24:39.580428 <6>[ 0.029330] LSM: Security Framework initializing
10433 19:24:39.587491 <6>[ 0.034269] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10434 19:24:39.596955 <6>[ 0.042086] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10435 19:24:39.607154 <6>[ 0.051499] cblist_init_generic: Setting adjustable number of callback queues.
10436 19:24:39.610378 <6>[ 0.058942] cblist_init_generic: Setting shift to 3 and lim to 1.
10437 19:24:39.620379 <6>[ 0.065280] cblist_init_generic: Setting adjustable number of callback queues.
10438 19:24:39.626887 <6>[ 0.072707] cblist_init_generic: Setting shift to 3 and lim to 1.
10439 19:24:39.630341 <6>[ 0.079106] rcu: Hierarchical SRCU implementation.
10440 19:24:39.636808 <6>[ 0.084152] rcu: Max phase no-delay instances is 1000.
10441 19:24:39.643206 <6>[ 0.091211] EFI services will not be available.
10442 19:24:39.646503 <6>[ 0.096165] smp: Bringing up secondary CPUs ...
10443 19:24:39.654659 <6>[ 0.101211] Detected VIPT I-cache on CPU1
10444 19:24:39.661546 <6>[ 0.101280] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10445 19:24:39.668173 <6>[ 0.101314] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10446 19:24:39.671545 <6>[ 0.101647] Detected VIPT I-cache on CPU2
10447 19:24:39.678210 <6>[ 0.101701] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10448 19:24:39.684969 <6>[ 0.101719] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10449 19:24:39.691510 <6>[ 0.101978] Detected VIPT I-cache on CPU3
10450 19:24:39.698196 <6>[ 0.102026] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10451 19:24:39.704648 <6>[ 0.102040] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10452 19:24:39.708124 <6>[ 0.102346] CPU features: detected: Spectre-v4
10453 19:24:39.714723 <6>[ 0.102353] CPU features: detected: Spectre-BHB
10454 19:24:39.717925 <6>[ 0.102358] Detected PIPT I-cache on CPU4
10455 19:24:39.724259 <6>[ 0.102415] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10456 19:24:39.731436 <6>[ 0.102431] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10457 19:24:39.738059 <6>[ 0.102726] Detected PIPT I-cache on CPU5
10458 19:24:39.744507 <6>[ 0.102789] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10459 19:24:39.750876 <6>[ 0.102805] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10460 19:24:39.754160 <6>[ 0.103084] Detected PIPT I-cache on CPU6
10461 19:24:39.761020 <6>[ 0.103149] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10462 19:24:39.767414 <6>[ 0.103165] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10463 19:24:39.773970 <6>[ 0.103464] Detected PIPT I-cache on CPU7
10464 19:24:39.780756 <6>[ 0.103529] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10465 19:24:39.787071 <6>[ 0.103545] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10466 19:24:39.790954 <6>[ 0.103592] smp: Brought up 1 node, 8 CPUs
10467 19:24:39.797258 <6>[ 0.244893] SMP: Total of 8 processors activated.
10468 19:24:39.800701 <6>[ 0.249814] CPU features: detected: 32-bit EL0 Support
10469 19:24:39.810173 <6>[ 0.255177] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10470 19:24:39.816985 <6>[ 0.263977] CPU features: detected: Common not Private translations
10471 19:24:39.823551 <6>[ 0.270453] CPU features: detected: CRC32 instructions
10472 19:24:39.826904 <6>[ 0.275804] CPU features: detected: RCpc load-acquire (LDAPR)
10473 19:24:39.833509 <6>[ 0.281801] CPU features: detected: LSE atomic instructions
10474 19:24:39.840518 <6>[ 0.287618] CPU features: detected: Privileged Access Never
10475 19:24:39.846792 <6>[ 0.293434] CPU features: detected: RAS Extension Support
10476 19:24:39.853398 <6>[ 0.299042] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10477 19:24:39.856720 <6>[ 0.306306] CPU: All CPU(s) started at EL2
10478 19:24:39.863400 <6>[ 0.310623] alternatives: applying system-wide alternatives
10479 19:24:39.872961 <6>[ 0.321476] devtmpfs: initialized
10480 19:24:39.884986 <6>[ 0.330352] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10481 19:24:39.895137 <6>[ 0.340317] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10482 19:24:39.901658 <6>[ 0.348545] pinctrl core: initialized pinctrl subsystem
10483 19:24:39.905177 <6>[ 0.355214] DMI not present or invalid.
10484 19:24:39.911467 <6>[ 0.359622] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10485 19:24:39.921986 <6>[ 0.366450] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10486 19:24:39.928397 <6>[ 0.374039] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10487 19:24:39.938468 <6>[ 0.382265] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10488 19:24:39.941750 <6>[ 0.390509] audit: initializing netlink subsys (disabled)
10489 19:24:39.952011 <5>[ 0.396201] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10490 19:24:39.958413 <6>[ 0.396905] thermal_sys: Registered thermal governor 'step_wise'
10491 19:24:39.964809 <6>[ 0.404165] thermal_sys: Registered thermal governor 'power_allocator'
10492 19:24:39.968279 <6>[ 0.410418] cpuidle: using governor menu
10493 19:24:39.974963 <6>[ 0.421377] NET: Registered PF_QIPCRTR protocol family
10494 19:24:39.981246 <6>[ 0.426863] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10495 19:24:39.984632 <6>[ 0.433969] ASID allocator initialised with 32768 entries
10496 19:24:39.992184 <6>[ 0.440541] Serial: AMBA PL011 UART driver
10497 19:24:40.000945 <4>[ 0.449295] Trying to register duplicate clock ID: 134
10498 19:24:40.054962 <6>[ 0.507061] KASLR enabled
10499 19:24:40.069418 <6>[ 0.514783] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10500 19:24:40.076273 <6>[ 0.521798] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10501 19:24:40.082505 <6>[ 0.528284] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10502 19:24:40.089000 <6>[ 0.535289] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10503 19:24:40.095930 <6>[ 0.541775] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10504 19:24:40.102705 <6>[ 0.548780] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10505 19:24:40.109329 <6>[ 0.555263] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10506 19:24:40.115771 <6>[ 0.562267] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10507 19:24:40.119109 <6>[ 0.569778] ACPI: Interpreter disabled.
10508 19:24:40.127421 <6>[ 0.576199] iommu: Default domain type: Translated
10509 19:24:40.134304 <6>[ 0.581314] iommu: DMA domain TLB invalidation policy: strict mode
10510 19:24:40.137215 <5>[ 0.587975] SCSI subsystem initialized
10511 19:24:40.144140 <6>[ 0.592152] usbcore: registered new interface driver usbfs
10512 19:24:40.151044 <6>[ 0.597882] usbcore: registered new interface driver hub
10513 19:24:40.154139 <6>[ 0.603435] usbcore: registered new device driver usb
10514 19:24:40.160738 <6>[ 0.609530] pps_core: LinuxPPS API ver. 1 registered
10515 19:24:40.170486 <6>[ 0.614724] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10516 19:24:40.174179 <6>[ 0.624072] PTP clock support registered
10517 19:24:40.176938 <6>[ 0.628312] EDAC MC: Ver: 3.0.0
10518 19:24:40.184686 <6>[ 0.633451] FPGA manager framework
10519 19:24:40.191290 <6>[ 0.637131] Advanced Linux Sound Architecture Driver Initialized.
10520 19:24:40.194745 <6>[ 0.643913] vgaarb: loaded
10521 19:24:40.201220 <6>[ 0.647086] clocksource: Switched to clocksource arch_sys_counter
10522 19:24:40.204636 <5>[ 0.653529] VFS: Disk quotas dquot_6.6.0
10523 19:24:40.211088 <6>[ 0.657717] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10524 19:24:40.214403 <6>[ 0.664906] pnp: PnP ACPI: disabled
10525 19:24:40.222972 <6>[ 0.671559] NET: Registered PF_INET protocol family
10526 19:24:40.232529 <6>[ 0.677156] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10527 19:24:40.244323 <6>[ 0.689476] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10528 19:24:40.254342 <6>[ 0.698286] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10529 19:24:40.260929 <6>[ 0.706252] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10530 19:24:40.267343 <6>[ 0.714951] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10531 19:24:40.279397 <6>[ 0.724710] TCP: Hash tables configured (established 65536 bind 65536)
10532 19:24:40.285814 <6>[ 0.731573] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10533 19:24:40.292707 <6>[ 0.738770] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10534 19:24:40.299303 <6>[ 0.746465] NET: Registered PF_UNIX/PF_LOCAL protocol family
10535 19:24:40.305697 <6>[ 0.752614] RPC: Registered named UNIX socket transport module.
10536 19:24:40.309293 <6>[ 0.758769] RPC: Registered udp transport module.
10537 19:24:40.316168 <6>[ 0.763704] RPC: Registered tcp transport module.
10538 19:24:40.322403 <6>[ 0.768637] RPC: Registered tcp NFSv4.1 backchannel transport module.
10539 19:24:40.325958 <6>[ 0.775304] PCI: CLS 0 bytes, default 64
10540 19:24:40.328997 <6>[ 0.779654] Unpacking initramfs...
10541 19:24:40.354050 <6>[ 0.799200] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10542 19:24:40.364415 <6>[ 0.807870] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10543 19:24:40.367371 <6>[ 0.816719] kvm [1]: IPA Size Limit: 40 bits
10544 19:24:40.373975 <6>[ 0.821243] kvm [1]: GICv3: no GICV resource entry
10545 19:24:40.377502 <6>[ 0.826264] kvm [1]: disabling GICv2 emulation
10546 19:24:40.383721 <6>[ 0.830949] kvm [1]: GIC system register CPU interface enabled
10547 19:24:40.387069 <6>[ 0.837108] kvm [1]: vgic interrupt IRQ18
10548 19:24:40.393674 <6>[ 0.841456] kvm [1]: VHE mode initialized successfully
10549 19:24:40.400374 <5>[ 0.847833] Initialise system trusted keyrings
10550 19:24:40.406991 <6>[ 0.852648] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10551 19:24:40.414581 <6>[ 0.862659] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10552 19:24:40.420682 <5>[ 0.869035] NFS: Registering the id_resolver key type
10553 19:24:40.424045 <5>[ 0.874333] Key type id_resolver registered
10554 19:24:40.430446 <5>[ 0.878749] Key type id_legacy registered
10555 19:24:40.437365 <6>[ 0.883027] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10556 19:24:40.443605 <6>[ 0.889951] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10557 19:24:40.450487 <6>[ 0.897665] 9p: Installing v9fs 9p2000 file system support
10558 19:24:40.487257 <5>[ 0.935517] Key type asymmetric registered
10559 19:24:40.490605 <5>[ 0.939845] Asymmetric key parser 'x509' registered
10560 19:24:40.500679 <6>[ 0.944982] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10561 19:24:40.503697 <6>[ 0.952597] io scheduler mq-deadline registered
10562 19:24:40.507003 <6>[ 0.957374] io scheduler kyber registered
10563 19:24:40.525790 <6>[ 0.974290] EINJ: ACPI disabled.
10564 19:24:40.558344 <4>[ 0.999887] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10565 19:24:40.568150 <4>[ 1.010506] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10566 19:24:40.582646 <6>[ 1.031067] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10567 19:24:40.590561 <6>[ 1.039065] printk: console [ttyS0] disabled
10568 19:24:40.618215 <6>[ 1.063691] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10569 19:24:40.624711 <6>[ 1.073162] printk: console [ttyS0] enabled
10570 19:24:40.628172 <6>[ 1.073162] printk: console [ttyS0] enabled
10571 19:24:40.634892 <6>[ 1.082062] printk: bootconsole [mtk8250] disabled
10572 19:24:40.638178 <6>[ 1.082062] printk: bootconsole [mtk8250] disabled
10573 19:24:40.644898 <6>[ 1.093059] SuperH (H)SCI(F) driver initialized
10574 19:24:40.647962 <6>[ 1.098329] msm_serial: driver initialized
10575 19:24:40.661756 <6>[ 1.107232] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10576 19:24:40.671735 <6>[ 1.115775] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10577 19:24:40.678137 <6>[ 1.124316] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10578 19:24:40.688391 <6>[ 1.132942] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10579 19:24:40.698144 <6>[ 1.141648] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10580 19:24:40.704447 <6>[ 1.150361] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10581 19:24:40.715115 <6>[ 1.158901] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10582 19:24:40.721241 <6>[ 1.167704] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10583 19:24:40.731559 <6>[ 1.176246] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10584 19:24:40.742851 <6>[ 1.191819] loop: module loaded
10585 19:24:40.749683 <6>[ 1.197652] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10586 19:24:40.771630 <4>[ 1.220634] mtk-pmic-keys: Failed to locate of_node [id: -1]
10587 19:24:40.778895 <6>[ 1.227491] megasas: 07.719.03.00-rc1
10588 19:24:40.788664 <6>[ 1.237066] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10589 19:24:40.797981 <6>[ 1.246478] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10590 19:24:40.814703 <6>[ 1.263192] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10591 19:24:40.871494 <6>[ 1.313397] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10592 19:24:42.060717 <6>[ 2.508828] Freeing initrd memory: 40284K
10593 19:24:42.071447 <6>[ 2.520385] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10594 19:24:42.083047 <6>[ 2.531522] tun: Universal TUN/TAP device driver, 1.6
10595 19:24:42.086483 <6>[ 2.537593] thunder_xcv, ver 1.0
10596 19:24:42.089418 <6>[ 2.541098] thunder_bgx, ver 1.0
10597 19:24:42.092881 <6>[ 2.544592] nicpf, ver 1.0
10598 19:24:42.103204 <6>[ 2.548624] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10599 19:24:42.106832 <6>[ 2.556099] hns3: Copyright (c) 2017 Huawei Corporation.
10600 19:24:42.113558 <6>[ 2.561687] hclge is initializing
10601 19:24:42.116720 <6>[ 2.565268] e1000: Intel(R) PRO/1000 Network Driver
10602 19:24:42.123406 <6>[ 2.570397] e1000: Copyright (c) 1999-2006 Intel Corporation.
10603 19:24:42.126857 <6>[ 2.576413] e1000e: Intel(R) PRO/1000 Network Driver
10604 19:24:42.133373 <6>[ 2.581628] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10605 19:24:42.140263 <6>[ 2.587812] igb: Intel(R) Gigabit Ethernet Network Driver
10606 19:24:42.146682 <6>[ 2.593463] igb: Copyright (c) 2007-2014 Intel Corporation.
10607 19:24:42.153061 <6>[ 2.599299] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10608 19:24:42.159828 <6>[ 2.605817] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10609 19:24:42.162996 <6>[ 2.612283] sky2: driver version 1.30
10610 19:24:42.169730 <6>[ 2.617281] VFIO - User Level meta-driver version: 0.3
10611 19:24:42.177070 <6>[ 2.625554] usbcore: registered new interface driver usb-storage
10612 19:24:42.183890 <6>[ 2.631997] usbcore: registered new device driver onboard-usb-hub
10613 19:24:42.192815 <6>[ 2.641183] mt6397-rtc mt6359-rtc: registered as rtc0
10614 19:24:42.202140 <6>[ 2.646649] mt6397-rtc mt6359-rtc: setting system clock to 2024-04-18T19:23:29 UTC (1713468209)
10615 19:24:42.205481 <6>[ 2.656216] i2c_dev: i2c /dev entries driver
10616 19:24:42.222970 <6>[ 2.668099] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10617 19:24:42.229019 <4>[ 2.676827] cpu cpu0: supply cpu not found, using dummy regulator
10618 19:24:42.235797 <4>[ 2.683270] cpu cpu1: supply cpu not found, using dummy regulator
10619 19:24:42.242508 <4>[ 2.689674] cpu cpu2: supply cpu not found, using dummy regulator
10620 19:24:42.249362 <4>[ 2.696077] cpu cpu3: supply cpu not found, using dummy regulator
10621 19:24:42.255758 <4>[ 2.702474] cpu cpu4: supply cpu not found, using dummy regulator
10622 19:24:42.262617 <4>[ 2.708868] cpu cpu5: supply cpu not found, using dummy regulator
10623 19:24:42.269220 <4>[ 2.715281] cpu cpu6: supply cpu not found, using dummy regulator
10624 19:24:42.275860 <4>[ 2.721679] cpu cpu7: supply cpu not found, using dummy regulator
10625 19:24:42.293604 <6>[ 2.742326] cpu cpu0: EM: created perf domain
10626 19:24:42.296963 <6>[ 2.747261] cpu cpu4: EM: created perf domain
10627 19:24:42.304233 <6>[ 2.752896] sdhci: Secure Digital Host Controller Interface driver
10628 19:24:42.310875 <6>[ 2.759332] sdhci: Copyright(c) Pierre Ossman
10629 19:24:42.317685 <6>[ 2.764291] Synopsys Designware Multimedia Card Interface Driver
10630 19:24:42.324122 <6>[ 2.770922] sdhci-pltfm: SDHCI platform and OF driver helper
10631 19:24:42.327475 <6>[ 2.770930] mmc0: CQHCI version 5.10
10632 19:24:42.334083 <6>[ 2.780799] ledtrig-cpu: registered to indicate activity on CPUs
10633 19:24:42.340889 <6>[ 2.787933] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10634 19:24:42.346962 <6>[ 2.795001] usbcore: registered new interface driver usbhid
10635 19:24:42.350159 <6>[ 2.800826] usbhid: USB HID core driver
10636 19:24:42.356847 <6>[ 2.805029] spi_master spi0: will run message pump with realtime priority
10637 19:24:42.405039 <6>[ 2.847636] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10638 19:24:42.424993 <6>[ 2.863872] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10639 19:24:42.428841 <6>[ 2.877925] mmc0: Command Queue Engine enabled
10640 19:24:42.435482 <6>[ 2.878694] cros-ec-spi spi0.0: Chrome EC device registered
10641 19:24:42.442170 <6>[ 2.882662] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10642 19:24:42.445739 <6>[ 2.895761] mmcblk0: mmc0:0001 DA4128 116 GiB
10643 19:24:42.456015 <6>[ 2.901263] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10644 19:24:42.462641 <6>[ 2.905861] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10645 19:24:42.469235 <6>[ 2.911702] NET: Registered PF_PACKET protocol family
10646 19:24:42.472687 <6>[ 2.917965] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10647 19:24:42.479391 <6>[ 2.921869] 9pnet: Installing 9P2000 support
10648 19:24:42.482285 <6>[ 2.927653] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10649 19:24:42.488942 <5>[ 2.931559] Key type dns_resolver registered
10650 19:24:42.495482 <6>[ 2.937398] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10651 19:24:42.498695 <6>[ 2.941677] registered taskstats version 1
10652 19:24:42.502291 <5>[ 2.952154] Loading compiled-in X.509 certificates
10653 19:24:42.532201 <4>[ 2.974390] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10654 19:24:42.541967 <4>[ 2.985081] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10655 19:24:42.548930 <3>[ 2.995608] debugfs: File 'uA_load' in directory '/' already present!
10656 19:24:42.555591 <3>[ 3.002308] debugfs: File 'min_uV' in directory '/' already present!
10657 19:24:42.561699 <3>[ 3.008976] debugfs: File 'max_uV' in directory '/' already present!
10658 19:24:42.568263 <3>[ 3.015589] debugfs: File 'constraint_flags' in directory '/' already present!
10659 19:24:42.579337 <3>[ 3.025124] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10660 19:24:42.588545 <6>[ 3.037592] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10661 19:24:42.595698 <6>[ 3.044511] xhci-mtk 11200000.usb: xHCI Host Controller
10662 19:24:42.601903 <6>[ 3.050013] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10663 19:24:42.612347 <6>[ 3.057858] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10664 19:24:42.619245 <6>[ 3.067274] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10665 19:24:42.625666 <6>[ 3.073340] xhci-mtk 11200000.usb: xHCI Host Controller
10666 19:24:42.632460 <6>[ 3.078815] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10667 19:24:42.639149 <6>[ 3.086462] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10668 19:24:42.645752 <6>[ 3.094115] hub 1-0:1.0: USB hub found
10669 19:24:42.649756 <6>[ 3.098124] hub 1-0:1.0: 1 port detected
10670 19:24:42.655971 <6>[ 3.102402] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10671 19:24:42.662714 <6>[ 3.110941] hub 2-0:1.0: USB hub found
10672 19:24:42.665730 <6>[ 3.114945] hub 2-0:1.0: 1 port detected
10673 19:24:42.674331 <6>[ 3.122879] mtk-msdc 11f70000.mmc: Got CD GPIO
10674 19:24:42.685933 <6>[ 3.131258] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10675 19:24:42.692515 <6>[ 3.139280] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10676 19:24:42.702756 <4>[ 3.147178] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10677 19:24:42.712306 <6>[ 3.156711] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10678 19:24:42.719421 <6>[ 3.164788] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10679 19:24:42.726145 <6>[ 3.172914] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10680 19:24:42.736217 <6>[ 3.180840] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10681 19:24:42.742587 <6>[ 3.188656] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10682 19:24:42.752357 <6>[ 3.196473] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10683 19:24:42.762108 <6>[ 3.206846] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10684 19:24:42.768765 <6>[ 3.215232] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10685 19:24:42.778969 <6>[ 3.223574] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10686 19:24:42.785010 <6>[ 3.231913] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10687 19:24:42.795175 <6>[ 3.240254] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10688 19:24:42.802063 <6>[ 3.248600] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10689 19:24:42.811751 <6>[ 3.256939] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10690 19:24:42.818428 <6>[ 3.265278] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10691 19:24:42.828339 <6>[ 3.273616] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10692 19:24:42.838075 <6>[ 3.281954] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10693 19:24:42.845017 <6>[ 3.290293] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10694 19:24:42.854855 <6>[ 3.298631] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10695 19:24:42.861468 <6>[ 3.306968] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10696 19:24:42.871163 <6>[ 3.315306] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10697 19:24:42.878244 <6>[ 3.323643] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10698 19:24:42.884629 <6>[ 3.332237] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10699 19:24:42.891071 <6>[ 3.339520] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10700 19:24:42.898018 <6>[ 3.346443] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10701 19:24:42.907946 <6>[ 3.353336] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10702 19:24:42.914760 <6>[ 3.360377] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10703 19:24:42.921204 <6>[ 3.367245] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10704 19:24:42.931193 <6>[ 3.376375] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10705 19:24:42.941465 <6>[ 3.385495] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10706 19:24:42.950972 <6>[ 3.394790] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10707 19:24:42.961010 <6>[ 3.404257] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10708 19:24:42.970877 <6>[ 3.413724] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10709 19:24:42.977600 <6>[ 3.422844] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10710 19:24:42.987423 <6>[ 3.432317] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10711 19:24:42.997449 <6>[ 3.441437] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10712 19:24:43.006910 <6>[ 3.450731] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10713 19:24:43.017403 <6>[ 3.460892] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10714 19:24:43.027299 <6>[ 3.472692] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10715 19:24:43.073814 <6>[ 3.519339] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10716 19:24:43.229055 <6>[ 3.677444] hub 1-1:1.0: USB hub found
10717 19:24:43.231975 <6>[ 3.681989] hub 1-1:1.0: 4 ports detected
10718 19:24:43.242122 <6>[ 3.690798] hub 1-1:1.0: USB hub found
10719 19:24:43.245444 <6>[ 3.695299] hub 1-1:1.0: 4 ports detected
10720 19:24:43.354137 <6>[ 3.799690] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10721 19:24:43.379825 <6>[ 3.828926] hub 2-1:1.0: USB hub found
10722 19:24:43.383291 <6>[ 3.833417] hub 2-1:1.0: 3 ports detected
10723 19:24:43.392440 <6>[ 3.841439] hub 2-1:1.0: USB hub found
10724 19:24:43.395935 <6>[ 3.845957] hub 2-1:1.0: 3 ports detected
10725 19:24:43.569986 <6>[ 4.015372] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10726 19:24:43.701790 <6>[ 4.150940] hub 1-1.4:1.0: USB hub found
10727 19:24:43.704986 <6>[ 4.155553] hub 1-1.4:1.0: 2 ports detected
10728 19:24:43.713836 <6>[ 4.162721] hub 1-1.4:1.0: USB hub found
10729 19:24:43.717049 <6>[ 4.167266] hub 1-1.4:1.0: 2 ports detected
10730 19:24:43.786154 <6>[ 4.231498] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10731 19:24:44.013832 <6>[ 4.459403] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10732 19:24:44.205865 <6>[ 4.651381] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10733 19:24:55.307064 <6>[ 15.760405] ALSA device list:
10734 19:24:55.313515 <6>[ 15.763694] No soundcards found.
10735 19:24:55.321489 <6>[ 15.771664] Freeing unused kernel memory: 8448K
10736 19:24:55.324803 <6>[ 15.777162] Run /init as init process
10737 19:24:55.355753 <6>[ 15.805918] NET: Registered PF_INET6 protocol family
10738 19:24:55.362705 <6>[ 15.812238] Segment Routing with IPv6
10739 19:24:55.365666 <6>[ 15.816180] In-situ OAM (IOAM) with IPv6
10740 19:24:55.408030 <30>[ 15.831370] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10741 19:24:55.414428 <30>[ 15.864463] systemd[1]: Detected architecture arm64.
10742 19:24:55.414906
10743 19:24:55.421096 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10744 19:24:55.421703
10745 19:24:55.422201
10746 19:24:55.433346 <30>[ 15.883453] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10747 19:24:55.568952 <30>[ 16.015771] systemd[1]: Queued start job for default target graphical.target.
10748 19:24:55.598863 <30>[ 16.045484] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10749 19:24:55.605535 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10750 19:24:55.606016
10751 19:24:55.625479 <30>[ 16.072042] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10752 19:24:55.635132 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10753 19:24:55.635703
10754 19:24:55.653909 <30>[ 16.100318] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10755 19:24:55.663605 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10756 19:24:55.664098
10757 19:24:55.680833 <30>[ 16.127828] systemd[1]: Created slice user.slice - User and Session Slice.
10758 19:24:55.687803 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10759 19:24:55.688499
10760 19:24:55.708094 <30>[ 16.151468] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10761 19:24:55.714936 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10762 19:24:55.715410
10763 19:24:55.737020 <30>[ 16.180109] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10764 19:24:55.743463 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10765 19:24:55.743981
10766 19:24:55.770569 <30>[ 16.207539] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10767 19:24:55.781002 <30>[ 16.227377] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10768 19:24:55.787135 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10769 19:24:55.787608
10770 19:24:55.805054 <30>[ 16.251816] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10771 19:24:55.815134 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10772 19:24:55.815611
10773 19:24:55.832929 <30>[ 16.279534] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10774 19:24:55.842999 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10775 19:24:55.843645
10776 19:24:55.857936 <30>[ 16.307939] systemd[1]: Reached target paths.target - Path Units.
10777 19:24:55.864817 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10778 19:24:55.867745
10779 19:24:55.885016 <30>[ 16.331830] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10780 19:24:55.891747 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10781 19:24:55.892298
10782 19:24:55.905490 <30>[ 16.355402] systemd[1]: Reached target slices.target - Slice Units.
10783 19:24:55.915254 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10784 19:24:55.915810
10785 19:24:55.930193 <30>[ 16.379901] systemd[1]: Reached target swap.target - Swaps.
10786 19:24:55.936559 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10787 19:24:55.937029
10788 19:24:55.956650 <30>[ 16.403463] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10789 19:24:55.966597 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10790 19:24:55.967172
10791 19:24:55.985754 <30>[ 16.432352] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10792 19:24:55.995236 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10793 19:24:55.995712
10794 19:24:56.014217 <30>[ 16.460927] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10795 19:24:56.024053 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10796 19:24:56.024626
10797 19:24:56.041063 <30>[ 16.488145] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10798 19:24:56.050964 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10799 19:24:56.051441
10800 19:24:56.069153 <30>[ 16.516027] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10801 19:24:56.075746 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10802 19:24:56.076216
10803 19:24:56.093274 <30>[ 16.540086] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10804 19:24:56.103030 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10805 19:24:56.103508
10806 19:24:56.121834 <30>[ 16.568794] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10807 19:24:56.131854 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10808 19:24:56.132327
10809 19:24:56.149185 <30>[ 16.595907] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10810 19:24:56.159161 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10811 19:24:56.159634
10812 19:24:56.216732 <30>[ 16.663465] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10813 19:24:56.223760 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10814 19:24:56.224339
10815 19:24:56.236729 <30>[ 16.683096] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10816 19:24:56.243250 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10817 19:24:56.243727
10818 19:24:56.264482 <30>[ 16.711293] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10819 19:24:56.270884 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10820 19:24:56.271359
10821 19:24:56.295292 <30>[ 16.735639] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10822 19:24:56.333447 <30>[ 16.779761] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10823 19:24:56.342752 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10824 19:24:56.343313
10825 19:24:56.365424 <30>[ 16.812383] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10826 19:24:56.372289 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10827 19:24:56.372829
10828 19:24:56.396955 <30>[ 16.844391] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10829 19:24:56.410253 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel<6>[ 16.858238] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10830 19:24:56.413279 Module dm_mod...
10831 19:24:56.413369
10832 19:24:56.473193 <30>[ 16.920031] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10833 19:24:56.479095 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10834 19:24:56.479179
10835 19:24:56.505652 <30>[ 16.952787] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10836 19:24:56.515032 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10837 19:24:56.515119
10838 19:24:56.537620 <30>[ 16.984817] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10839 19:24:56.544055 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10840 19:24:56.544176
10841 19:24:56.608759 <30>[ 17.055939] systemd[1]: Starting systemd-journald.service - Journal Service...
10842 19:24:56.615402 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10843 19:24:56.615643
10844 19:24:56.635472 <30>[ 17.082896] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10845 19:24:56.642184 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10846 19:24:56.642459
10847 19:24:56.667641 <30>[ 17.111303] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10848 19:24:56.674081 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10849 19:24:56.674162
10850 19:24:56.721062 <30>[ 17.168167] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10851 19:24:56.731030 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10852 19:24:56.731472
10853 19:24:56.751995 <30>[ 17.198984] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10854 19:24:56.761749 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10855 19:24:56.762227
10856 19:24:56.789097 <30>[ 17.236457] systemd[1]: Started systemd-journald.service - Journal Service.
10857 19:24:56.795453 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10858 19:24:56.795563
10859 19:24:56.818488 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10860 19:24:56.818579
10861 19:24:56.837262 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10862 19:24:56.837406
10863 19:24:56.857052 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10864 19:24:56.857139
10865 19:24:56.877280 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10866 19:24:56.877414
10867 19:24:56.897259 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10868 19:24:56.897396
10869 19:24:56.917393 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10870 19:24:56.917479
10871 19:24:56.938151 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10872 19:24:56.938270
10873 19:24:56.957973 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10874 19:24:56.958100
10875 19:24:56.977739 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10876 19:24:56.977824
10877 19:24:56.997755 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10878 19:24:56.997866
10879 19:24:57.018004 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10880 19:24:57.018116
10881 19:24:57.038831 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10882 19:24:57.038916
10883 19:24:57.056711 See 'systemctl status systemd-remount-fs.service' for details.
10884 19:24:57.056795
10885 19:24:57.067325 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10886 19:24:57.067410
10887 19:24:57.086977 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10888 19:24:57.087064
10889 19:24:57.132596 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10890 19:24:57.132689
10891 19:24:57.152738 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10892 19:24:57.152823
10893 19:24:57.173503 <46>[ 17.621192] systemd-journald[184]: Received client request to flush runtime journal.
10894 19:24:57.180335 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10895 19:24:57.180437
10896 19:24:57.205756 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10897 19:24:57.205871
10898 19:24:57.253047 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10899 19:24:57.253167
10900 19:24:57.282890 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10901 19:24:57.282977
10902 19:24:57.301502 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10903 19:24:57.301588
10904 19:24:57.321212 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10905 19:24:57.321310
10906 19:24:57.341614 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10907 19:24:57.341740
10908 19:24:57.361375 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10909 19:24:57.361582
10910 19:24:57.405200 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10911 19:24:57.405670
10912 19:24:57.430428 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10913 19:24:57.430964
10914 19:24:57.448406 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10915 19:24:57.448491
10916 19:24:57.468067 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10917 19:24:57.468156
10918 19:24:57.520316 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10919 19:24:57.520649
10920 19:24:57.540947 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10921 19:24:57.541578
10922 19:24:57.564812 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10923 19:24:57.565450
10924 19:24:57.611661 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10925 19:24:57.612209
10926 19:24:57.633748 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10927 19:24:57.634304
10928 19:24:57.657491 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10929 19:24:57.658064
10930 19:24:57.692532 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10931 19:24:57.693103
10932 19:24:57.717119 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10933 19:24:57.717751
10934 19:24:57.739391 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10935 19:24:57.739856
10936 19:24:57.841801 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10937 19:24:57.842353
10938 19:24:57.861772 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10939 19:24:57.862330
10940 19:24:57.881926 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10941 19:24:57.882490
10942 19:24:57.901457 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10943 19:24:57.902002
10944 19:24:57.922219 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10945 19:24:57.922698
10946 19:24:57.938480 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10947 19:24:57.938975
10948 19:24:57.956918 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10949 19:24:57.957601
10950 19:24:57.964012 <6>[ 18.411954] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10951 19:24:57.976488 <6>[ 18.426591] remoteproc remoteproc0: scp is available
10952 19:24:57.982813 <6>[ 18.432260] remoteproc remoteproc0: powering up scp
10953 19:24:57.989563 <6>[ 18.437407] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10954 19:24:57.999607 <3>[ 18.441801] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10955 19:24:58.006206 <6>[ 18.442143] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10956 19:24:58.016190 <6>[ 18.442183] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10957 19:24:58.023075 <6>[ 18.442191] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10958 19:24:58.029533 <6>[ 18.445876] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10959 19:24:58.036285 <3>[ 18.484759] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10960 19:24:58.046610 <3>[ 18.493127] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10961 19:24:58.061552 <3>[ 18.508355] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10962 19:24:58.068273 <3>[ 18.516661] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10963 19:24:58.078070 <4>[ 18.524041] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10964 19:24:58.085050 <3>[ 18.525209] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10965 19:24:58.094407 Startin<3>[ 18.540194] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10966 19:24:58.101212 <3>[ 18.549642] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10967 19:24:58.111275 g [0;1;39msystemd-networkd.…i<4>[ 18.559441] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10968 19:24:58.121004 ce[0m - Network<3>[ 18.563119] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10969 19:24:58.131072 <6>[ 18.571591] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10970 19:24:58.137519 Configuration..<6>[ 18.571599] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10971 19:24:58.138101 .
10972 19:24:58.141110
10973 19:24:58.144233 <6>[ 18.576740] mc: Linux media interface: v0.10
10974 19:24:58.150846 <3>[ 18.578036] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10975 19:24:58.157169 <6>[ 18.583466] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10976 19:24:58.163832 <6>[ 18.583482] pci_bus 0000:00: root bus resource [bus 00-ff]
10977 19:24:58.170526 <6>[ 18.583490] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10978 19:24:58.180609 <6>[ 18.583493] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10979 19:24:58.187452 <6>[ 18.583539] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10980 19:24:58.197557 <6>[ 18.583555] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10981 19:24:58.200449 <6>[ 18.583645] pci 0000:00:00.0: supports D1 D2
10982 19:24:58.207549 <6>[ 18.583647] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10983 19:24:58.217381 <6>[ 18.584767] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10984 19:24:58.220519 <6>[ 18.585864] remoteproc remoteproc0: remote processor scp is now up
10985 19:24:58.229952 <3>[ 18.594256] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10986 19:24:58.236855 <6>[ 18.600520] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10987 19:24:58.247004 <3>[ 18.607198] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10988 19:24:58.253266 <6>[ 18.615602] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10989 19:24:58.259850 <3>[ 18.616474] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10990 19:24:58.266748 <3>[ 18.616496] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10991 19:24:58.276423 <3>[ 18.616500] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10992 19:24:58.283276 <3>[ 18.616509] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10993 19:24:58.292903 <3>[ 18.616515] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10994 19:24:58.299747 <3>[ 18.629619] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10995 19:24:58.306444 <6>[ 18.637193] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10996 19:24:58.313397 <6>[ 18.650437] usbcore: registered new device driver r8152-cfgselector
10997 19:24:58.323179 <6>[ 18.651281] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10998 19:24:58.326648 <6>[ 18.663920] videodev: Linux video capture interface: v2.00
10999 19:24:58.336612 <6>[ 18.670840] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11000 19:24:58.346192 <6>[ 18.679618] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
11001 19:24:58.349476 <6>[ 18.685723] pci 0000:01:00.0: supports D1 D2
11002 19:24:58.359641 <6>[ 18.685774] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
11003 19:24:58.365913 <6>[ 18.686723] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
11004 19:24:58.376018 <6>[ 18.689218] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
11005 19:24:58.385875 <6>[ 18.693230] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
11006 19:24:58.392529 <6>[ 18.701022] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11007 19:24:58.396033 <6>[ 18.756810] Bluetooth: Core ver 2.22
11008 19:24:58.402230 <6>[ 18.759577] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
11009 19:24:58.412322 <6>[ 18.765415] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11010 19:24:58.415622 <6>[ 18.769971] NET: Registered PF_BLUETOOTH protocol family
11011 19:24:58.422185 <6>[ 18.769973] Bluetooth: HCI device and connection manager initialized
11012 19:24:58.428518 <6>[ 18.769992] Bluetooth: HCI socket layer initialized
11013 19:24:58.434899 <5>[ 18.773571] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11014 19:24:58.448484 <6>[ 18.778667] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11015 19:24:58.454816 <6>[ 18.779158] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11016 19:24:58.462048 <6>[ 18.779193] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11017 19:24:58.472851 <6>[ 18.779197] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11018 19:24:58.479496 <6>[ 18.779205] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11019 19:24:58.486022 <6>[ 18.779218] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11020 19:24:58.496960 <6>[ 18.779230] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11021 19:24:58.499980 <6>[ 18.779242] pci 0000:00:00.0: PCI bridge to [bus 01]
11022 19:24:58.509940 <6>[ 18.779248] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11023 19:24:58.516558 <6>[ 18.779453] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11024 19:24:58.520405 <6>[ 18.780129] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
11025 19:24:58.527164 <6>[ 18.781192] pcieport 0000:00:00.0: AER: enabled with IRQ 282
11026 19:24:58.533865 <6>[ 18.783210] Bluetooth: L2CAP socket layer initialized
11027 19:24:58.537439 <6>[ 18.783244] Bluetooth: SCO socket layer initialized
11028 19:24:58.547796 <4>[ 18.791012] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
11029 19:24:58.554406 <6>[ 18.791365] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11030 19:24:58.561211 <6>[ 18.791672] usbcore: registered new interface driver uvcvideo
11031 19:24:58.567779 <4>[ 18.796917] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
11032 19:24:58.575364 <4>[ 18.796917] Fallback method does not support PEC.
11033 19:24:58.578568 <5>[ 18.800273] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11034 19:24:58.588644 <5>[ 18.800841] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
11035 19:24:58.595425 <4>[ 18.808459] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
11036 19:24:58.605364 <4>[ 18.814941] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11037 19:24:58.612223 <6>[ 18.867540] usbcore: registered new interface driver btusb
11038 19:24:58.621689 <4>[ 18.868849] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11039 19:24:58.628624 <3>[ 18.868857] Bluetooth: hci0: Failed to load firmware file (-2)
11040 19:24:58.635144 <3>[ 18.868859] Bluetooth: hci0: Failed to set up firmware (-2)
11041 19:24:58.645445 <4>[ 18.868863] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11042 19:24:58.648130 <6>[ 18.872098] cfg80211: failed to load regulatory.db
11043 19:24:58.654879 <6>[ 18.879539] r8152 2-1.3:1.0 eth0: v1.12.13
11044 19:24:58.661742 <6>[ 18.911588] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11045 19:24:58.667965 <6>[ 18.919372] usbcore: registered new interface driver r8152
11046 19:24:58.671422 <6>[ 18.927401] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11047 19:24:58.681671 <3>[ 18.929290] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11048 19:24:58.691211 <3>[ 18.930135] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11049 19:24:58.694781 <6>[ 18.947200] mt7921e 0000:01:00.0: ASIC revision: 79610010
11050 19:24:58.700915 <6>[ 18.951843] usbcore: registered new interface driver cdc_ether
11051 19:24:58.711400 <3>[ 18.954220] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11052 19:24:58.718385 <3>[ 18.990962] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11053 19:24:58.725162 <6>[ 19.002649] usbcore: registered new interface driver r8153_ecm
11054 19:24:58.735253 <3>[ 19.009125] power_supply sbs-5-000b: driver failed to report `capacity_error_margin' property: -6
11055 19:24:58.745162 <3>[ 19.030158] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11056 19:24:58.748423 <6>[ 19.111021] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0
11057 19:24:58.758263 <6>[ 19.117022] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
11058 19:24:58.761980 <6>[ 19.117022]
11059 19:24:58.768132 <3>[ 19.171068] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11060 19:24:58.774530 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11061 19:24:58.775096
11062 19:24:58.799833 <3>[ 19.246950] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11063 19:24:58.814399 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11064 19:24:58.814947
11065 19:24:58.829169 <3>[ 19.276293] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11066 19:24:58.847534 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11067 19:24:58.848092
11068 19:24:58.858806 <3>[ 19.305689] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11069 19:24:58.868929 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11070 19:24:58.869545
11071 19:24:58.884635 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11072 19:24:58.885184
11073 19:24:58.938092 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11074 19:24:58.938640
11075 19:24:58.960420 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11076 19:24:58.960990
11077 19:24:58.977450 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11078 19:24:58.978011
11079 19:24:58.990890 <6>[ 19.438195] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
11080 19:24:58.997996 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11081 19:24:58.998559
11082 19:24:59.017593 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11083 19:24:59.018199
11084 19:24:59.061441 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11085 19:24:59.061998
11086 19:24:59.085273 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11087 19:24:59.085886
11088 19:24:59.106330 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11089 19:24:59.106889
11090 19:24:59.127315 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11091 19:24:59.127895
11092 19:24:59.177664 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11093 19:24:59.178230
11094 19:24:59.199691 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11095 19:24:59.200266
11096 19:24:59.218231 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11097 19:24:59.218798
11098 19:24:59.233570 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11099 19:24:59.234143
11100 19:24:59.253204 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11101 19:24:59.253806
11102 19:24:59.306034 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11103 19:24:59.306757
11104 19:24:59.331150 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11105 19:24:59.331716
11106 19:24:59.353339 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11107 19:24:59.353911
11108 19:24:59.394253 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11109 19:24:59.394822
11110 19:24:59.437736
11111 19:24:59.438289
11112 19:24:59.441451 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11113 19:24:59.442002
11114 19:24:59.444837 debian-bookworm-arm64 login: root (automatic login)
11115 19:24:59.445473
11116 19:24:59.445847
11117 19:24:59.458229 Linux debian-bookworm-arm64 6.1.86-cip19 #1 SMP PREEMPT Thu Apr 18 19:05:54 UTC 2024 aarch64
11118 19:24:59.458790
11119 19:24:59.464876 The programs included with the Debian GNU/Linux system are free software;
11120 19:24:59.471289 the exact distribution terms for each program are described in the
11121 19:24:59.474583 individual files in /usr/share/doc/*/copyright.
11122 19:24:59.475165
11123 19:24:59.481385 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11124 19:24:59.484667 permitted by applicable law.
11125 19:24:59.486226 Matched prompt #10: / #
11127 19:24:59.487354 Setting prompt string to ['/ #']
11128 19:24:59.487835 end: 2.2.5.1 login-action (duration 00:00:21) [common]
11130 19:24:59.488890 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
11131 19:24:59.489408 start: 2.2.6 expect-shell-connection (timeout 00:03:27) [common]
11132 19:24:59.489804 Setting prompt string to ['/ #']
11133 19:24:59.490138 Forcing a shell prompt, looking for ['/ #']
11135 19:24:59.540992 / #
11136 19:24:59.541779 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11137 19:24:59.542246 Waiting using forced prompt support (timeout 00:02:30)
11138 19:24:59.547932
11139 19:24:59.548867 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11140 19:24:59.549433 start: 2.2.7 export-device-env (timeout 00:03:27) [common]
11141 19:24:59.550006 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11142 19:24:59.550491 end: 2.2 depthcharge-retry (duration 00:01:33) [common]
11143 19:24:59.550953 end: 2 depthcharge-action (duration 00:01:33) [common]
11144 19:24:59.551438 start: 3 lava-test-retry (timeout 00:08:06) [common]
11145 19:24:59.551936 start: 3.1 lava-test-shell (timeout 00:08:06) [common]
11146 19:24:59.552354 Using namespace: common
11148 19:24:59.653554 / # #
11149 19:24:59.654196 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11150 19:24:59.660204 #
11151 19:24:59.661093 Using /lava-13420357
11153 19:24:59.762367 / # export SHELL=/bin/sh
11154 19:24:59.767614 export SHELL=/bin/sh
11156 19:24:59.868173 / # . /lava-13420357/environment
11157 19:24:59.868414 . /lava-13420357/environment<6>[ 20.299386] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11158 19:24:59.873280
11160 19:24:59.973884 / # /lava-13420357/bin/lava-test-runner /lava-13420357/0
11161 19:24:59.974064 Test shell timeout: 10s (minimum of the action and connection timeout)
11162 19:24:59.979640 /lava-13420357/bin/lava-test-runner /lava-13420357/0
11163 19:25:00.002595 + export TESTRUN_ID=0_v4l2-compliance-uvc
11164 19:25:00.008974 + cd /lava-13420357/0/tests/0_v4l2-co<6>[ 20.459658] r8152 2-1.3:1.0 enx00e04c722dd6: carrier on
11165 19:25:00.012477 mpliance-uvc
11166 19:25:00.012564 + cat uuid
11167 19:25:00.015838 + UUID=13420357_1.5.2.3.1
11168 19:25:00.015940 + set +x
11169 19:25:00.022335 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-uvc 13420357_1.5.2.3.1>
11170 19:25:00.022598 Received signal: <STARTRUN> 0_v4l2-compliance-uvc 13420357_1.5.2.3.1
11171 19:25:00.022673 Starting test lava.0_v4l2-compliance-uvc (13420357_1.5.2.3.1)
11172 19:25:00.022760 Skipping test definition patterns.
11173 19:25:00.025495 + /usr/bin/v4l2-parser.sh -d uvcvideo
11174 19:25:00.029117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11175 19:25:00.029381 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11177 19:25:00.032277 device: /dev/video0
11178 19:25:00.569049 <6>[ 21.016332] IPv6: ADDRCONF(NETDEV_CHANGE): enx00e04c722dd6: link becomes ready
11179 19:25:06.519916 v4l2-compliance 1.27.0-1, 64 bits, 64-bit time_t
11180 19:25:06.530203 v4l2-compliance SHA: a18611d8960f 2024-03-08 13:09:54
11181 19:25:06.538613
11182 19:25:06.554779 Compliance test for uvcvideo device /dev/video0:
11183 19:25:06.562863
11184 19:25:06.573915 Driver Info:
11185 19:25:06.589864 Driver name : uvcvideo
11186 19:25:06.603855 Card type : HD User Facing: HD User Facing
11187 19:25:06.614767 Bus info : usb-11200000.usb-1.4.1
11188 19:25:06.624444 Driver version : 6.1.86
11189 19:25:06.637668 Capabilities : 0x84a00001
11190 19:25:06.650763 Metadata Capture
11191 19:25:06.664773 Streaming
11192 19:25:06.675586 Extended Pix Format
11193 19:25:06.687977 Device Capabilities
11194 19:25:06.699089 Device Caps : 0x04200001
11195 19:25:06.711470 Streaming
11196 19:25:06.724279 Extended Pix Format
11197 19:25:06.734533 Media Driver Info:
11198 19:25:06.746627 Driver name : uvcvideo
11199 19:25:06.762047 Model : HD User Facing: HD User Facing
11200 19:25:06.770872 Serial : 200901010001
11201 19:25:06.784512 Bus info : usb-11200000.usb-1.4.1
11202 19:25:06.791724 Media version : 6.1.86
11203 19:25:06.805566 Hardware revision: 0x00009758 (38744)
11204 19:25:06.813037 Driver version : 6.1.86
11205 19:25:06.825109 Interface Info:
11206 19:25:06.841833 <LAVA_SIGNAL_TESTSET START Interface-Info>
11207 19:25:06.842403 ID : 0x03000002
11208 19:25:06.843055 Received signal: <TESTSET> START Interface-Info
11209 19:25:06.843465 Starting test_set Interface-Info
11210 19:25:06.853601 Type : V4L Video
11211 19:25:06.866008 Entity Info:
11212 19:25:06.873288 <LAVA_SIGNAL_TESTSET STOP>
11213 19:25:06.874168 Received signal: <TESTSET> STOP
11214 19:25:06.874585 Closing test_set Interface-Info
11215 19:25:06.882729 <LAVA_SIGNAL_TESTSET START Entity-Info>
11216 19:25:06.883573 Received signal: <TESTSET> START Entity-Info
11217 19:25:06.883968 Starting test_set Entity-Info
11218 19:25:06.885417 ID : 0x00000001 (1)
11219 19:25:06.897258 Name : HD User Facing: HD User Facing
11220 19:25:06.905840 Function : V4L2 I/O
11221 19:25:06.920161 Flags : default
11222 19:25:06.930959 Pad 0x01000007 : 0: Sink
11223 19:25:06.952909 Link 0x02000013: from remote pad 0x100000a of entity 'Realtek Extended Controls Unit' (Video Pixel Formatter): Data, Enabled, Immutable
11224 19:25:06.953531
11225 19:25:06.969604 Required ioctls:
11226 19:25:06.978283 <LAVA_SIGNAL_TESTSET STOP>
11227 19:25:06.979137 Received signal: <TESTSET> STOP
11228 19:25:06.979532 Closing test_set Entity-Info
11229 19:25:06.990599 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11230 19:25:06.991444 Received signal: <TESTSET> START Required-ioctls
11231 19:25:06.991837 Starting test_set Required-ioctls
11232 19:25:06.993700 test MC information (see 'Media Driver Info' above): OK
11233 19:25:07.016784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass>
11234 19:25:07.017652 Received signal: <TESTCASE> TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass
11236 19:25:07.019657 test VIDIOC_QUERYCAP: OK
11237 19:25:07.038681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11238 19:25:07.039503 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11240 19:25:07.042154 test invalid ioctls: OK
11241 19:25:07.065461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11242 19:25:07.066031
11243 19:25:07.066677 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11245 19:25:07.074544 Allow for multiple opens:
11246 19:25:07.082016 <LAVA_SIGNAL_TESTSET STOP>
11247 19:25:07.082851 Received signal: <TESTSET> STOP
11248 19:25:07.083236 Closing test_set Required-ioctls
11249 19:25:07.091176 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11250 19:25:07.092016 Received signal: <TESTSET> START Allow-for-multiple-opens
11251 19:25:07.092420 Starting test_set Allow-for-multiple-opens
11252 19:25:07.094899 test second /dev/video0 open: OK
11253 19:25:07.116104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video0-open RESULT=pass>
11254 19:25:07.116945 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video0-open RESULT=pass
11256 19:25:07.119476 test VIDIOC_QUERYCAP: OK
11257 19:25:07.140435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11258 19:25:07.141278 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11260 19:25:07.143547 test VIDIOC_G/S_PRIORITY: OK
11261 19:25:07.165816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11262 19:25:07.166654 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11264 19:25:07.168932 test for unlimited opens: OK
11265 19:25:07.193593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11266 19:25:07.194159
11267 19:25:07.194792 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11269 19:25:07.204421 Debug ioctls:
11270 19:25:07.214811 <LAVA_SIGNAL_TESTSET STOP>
11271 19:25:07.215651 Received signal: <TESTSET> STOP
11272 19:25:07.216044 Closing test_set Allow-for-multiple-opens
11273 19:25:07.225730 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11274 19:25:07.226580 Received signal: <TESTSET> START Debug-ioctls
11275 19:25:07.226992 Starting test_set Debug-ioctls
11276 19:25:07.228471 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11277 19:25:07.250591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11278 19:25:07.251416 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11280 19:25:07.257291 test VIDIOC_LOG_STATUS: OK (Not Supported)
11281 19:25:07.275076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11282 19:25:07.275656
11283 19:25:07.276302 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11285 19:25:07.284628 Input ioctls:
11286 19:25:07.291940 <LAVA_SIGNAL_TESTSET STOP>
11287 19:25:07.292782 Received signal: <TESTSET> STOP
11288 19:25:07.293174 Closing test_set Debug-ioctls
11289 19:25:07.301932 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11290 19:25:07.302790 Received signal: <TESTSET> START Input-ioctls
11291 19:25:07.303208 Starting test_set Input-ioctls
11292 19:25:07.305046 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11293 19:25:07.331098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11294 19:25:07.331946 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11296 19:25:07.333807 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11297 19:25:07.353038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11298 19:25:07.353893 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11300 19:25:07.359696 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11301 19:25:07.379012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11302 19:25:07.379863 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11304 19:25:07.385710 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11305 19:25:07.403035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11306 19:25:07.403871 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11308 19:25:07.406048 test VIDIOC_G/S/ENUMINPUT: OK
11309 19:25:07.428542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11310 19:25:07.429446 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11312 19:25:07.432074 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11313 19:25:07.453382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11314 19:25:07.454198 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11316 19:25:07.456729 Inputs: 1 Audio Inputs: 0 Tuners: 0
11317 19:25:07.469456
11318 19:25:07.486395 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11319 19:25:07.508692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11320 19:25:07.509526 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11322 19:25:07.515307 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11323 19:25:07.533748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11324 19:25:07.534727 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11326 19:25:07.540508 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11327 19:25:07.559043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11328 19:25:07.559879 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11330 19:25:07.565221 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11331 19:25:07.586078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11332 19:25:07.586913 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11334 19:25:07.591984 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11335 19:25:07.608963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11336 19:25:07.609563
11337 19:25:07.610207 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11339 19:25:07.627459 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11340 19:25:07.648817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11341 19:25:07.649706 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11343 19:25:07.655372 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11344 19:25:07.680086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11345 19:25:07.680925 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11347 19:25:07.683662 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11348 19:25:07.701950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11349 19:25:07.702814 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11351 19:25:07.705551 test VIDIOC_G/S_EDID: OK (Not Supported)
11352 19:25:07.726405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11353 19:25:07.726988
11354 19:25:07.727745 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11356 19:25:07.737945 Control ioctls (Input 0):
11357 19:25:07.744810 <LAVA_SIGNAL_TESTSET STOP>
11358 19:25:07.745702 Received signal: <TESTSET> STOP
11359 19:25:07.746121 Closing test_set Input-ioctls
11360 19:25:07.754844 <LAVA_SIGNAL_TESTSET START Control-ioctls-Input-0>
11361 19:25:07.755724 Received signal: <TESTSET> START Control-ioctls-Input-0
11362 19:25:07.756151 Starting test_set Control-ioctls-Input-0
11363 19:25:07.758098 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11364 19:25:07.782465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11365 19:25:07.783045 test VIDIOC_QUERYCTRL: OK
11366 19:25:07.783797 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11368 19:25:07.804952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11369 19:25:07.806010 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11371 19:25:07.807656 test VIDIOC_G/S_CTRL: OK
11372 19:25:07.828769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11373 19:25:07.829637 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11375 19:25:07.832490 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11376 19:25:07.854101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11377 19:25:07.854947 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11379 19:25:07.860740 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
11380 19:25:07.881646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass>
11381 19:25:07.882474 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass
11383 19:25:07.885196 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11384 19:25:07.902617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11385 19:25:07.903454 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11387 19:25:07.905755 Standard Controls: 16 Private Controls: 0
11388 19:25:07.917943
11389 19:25:07.929012 Format ioctls (Input 0):
11390 19:25:07.935941 <LAVA_SIGNAL_TESTSET STOP>
11391 19:25:07.936781 Received signal: <TESTSET> STOP
11392 19:25:07.937171 Closing test_set Control-ioctls-Input-0
11393 19:25:07.945282 <LAVA_SIGNAL_TESTSET START Format-ioctls-Input-0>
11394 19:25:07.946202 Received signal: <TESTSET> START Format-ioctls-Input-0
11395 19:25:07.946626 Starting test_set Format-ioctls-Input-0
11396 19:25:07.948649 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11397 19:25:07.973929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11398 19:25:07.974778 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11400 19:25:07.976815 test VIDIOC_G/S_PARM: OK
11401 19:25:07.994981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11402 19:25:07.995822 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11404 19:25:07.997970 test VIDIOC_G_FBUF: OK (Not Supported)
11405 19:25:08.019819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11406 19:25:08.020664 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11408 19:25:08.023058 test VIDIOC_G_FMT: OK
11409 19:25:08.045496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11410 19:25:08.046499 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11412 19:25:08.048209 test VIDIOC_TRY_FMT: OK
11413 19:25:08.073997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11414 19:25:08.074839 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11416 19:25:08.080687 warn: v4l2-test-formats.cpp(1046): Could not set fmt2
11417 19:25:08.088194 test VIDIOC_S_FMT: OK
11418 19:25:08.112499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass>
11419 19:25:08.113393 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass
11421 19:25:08.115371 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11422 19:25:08.137947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11423 19:25:08.138826 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11425 19:25:08.141063 test Cropping: OK (Not Supported)
11426 19:25:08.162838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11427 19:25:08.163658 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11429 19:25:08.165807 test Composing: OK (Not Supported)
11430 19:25:08.187610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11431 19:25:08.188458 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11433 19:25:08.190436 test Scaling: OK (Not Supported)
11434 19:25:08.211498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11435 19:25:08.212096
11436 19:25:08.212784 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11438 19:25:08.222440 Codec ioctls (Input 0):
11439 19:25:08.229459 <LAVA_SIGNAL_TESTSET STOP>
11440 19:25:08.230295 Received signal: <TESTSET> STOP
11441 19:25:08.230694 Closing test_set Format-ioctls-Input-0
11442 19:25:08.238974 <LAVA_SIGNAL_TESTSET START Codec-ioctls-Input-0>
11443 19:25:08.239808 Received signal: <TESTSET> START Codec-ioctls-Input-0
11444 19:25:08.240238 Starting test_set Codec-ioctls-Input-0
11445 19:25:08.242256 test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
11446 19:25:08.265357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11447 19:25:08.266220 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11449 19:25:08.271569 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11450 19:25:08.288981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11451 19:25:08.289882 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11453 19:25:08.295769 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11454 19:25:08.325884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11455 19:25:08.326458
11456 19:25:08.327103 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11458 19:25:08.335742 Buffer ioctls (Input 0):
11459 19:25:08.343511 <LAVA_SIGNAL_TESTSET STOP>
11460 19:25:08.344363 Received signal: <TESTSET> STOP
11461 19:25:08.344772 Closing test_set Codec-ioctls-Input-0
11462 19:25:08.353283 <LAVA_SIGNAL_TESTSET START Buffer-ioctls-Input-0>
11463 19:25:08.354151 Received signal: <TESTSET> START Buffer-ioctls-Input-0
11464 19:25:08.354550 Starting test_set Buffer-ioctls-Input-0
11465 19:25:08.356690 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11466 19:25:08.385530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11467 19:25:08.386369 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11469 19:25:08.389202 test CREATE_BUFS maximum buffers: OK
11470 19:25:08.404888 Received signal: <TESTCASE> TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass
11472 19:25:08.408638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass>
11473 19:25:08.409225 test VIDIOC_EXPBUF: OK
11474 19:25:08.434057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11475 19:25:08.434901 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11477 19:25:08.437511 test Requests: OK (Not Supported)
11478 19:25:08.460459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11479 19:25:08.461037
11480 19:25:08.461785 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11482 19:25:08.471236 Test input 0:
11483 19:25:08.480943
11484 19:25:08.499740 Streaming ioctls:
11485 19:25:08.507334 <LAVA_SIGNAL_TESTSET STOP>
11486 19:25:08.508184 Received signal: <TESTSET> STOP
11487 19:25:08.508609 Closing test_set Buffer-ioctls-Input-0
11488 19:25:08.516710 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11489 19:25:08.517586 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11490 19:25:08.517988 Starting test_set Streaming-ioctls_Test-input-0
11491 19:25:08.520094 test read/write: OK (Not Supported)
11492 19:25:08.542237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11493 19:25:08.543122 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11495 19:25:08.545425 test blocking wait: OK
11496 19:25:08.565424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=pass>
11497 19:25:08.566253 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=pass
11499 19:25:08.571851 fail: v4l2-test-buffers.cpp(1377): node->streamon(q.g_type()) != EINVAL
11500 19:25:08.576733 test MMAP (no poll): FAIL
11501 19:25:08.603711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-no-poll RESULT=fail>
11502 19:25:08.604554 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-no-poll RESULT=fail
11504 19:25:08.610287 fail: v4l2-test-buffers.cpp(1377): node->streamon(q.g_type()) != EINVAL
11505 19:25:08.613682 test MMAP (select): FAIL
11506 19:25:08.638882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11507 19:25:08.639730 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11509 19:25:08.644676 fail: v4l2-test-buffers.cpp(1377): node->streamon(q.g_type()) != EINVAL
11510 19:25:08.650771 test MMAP (epoll): FAIL
11511 19:25:08.674174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11512 19:25:08.674742
11513 19:25:08.675388 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11515 19:25:08.686400
11516 19:25:08.864001
11517 19:25:08.870952 test USERPTR (no poll): OK
11518 19:25:08.899189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-no-poll RESULT=pass>
11519 19:25:08.899774
11520 19:25:08.900418 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-no-poll RESULT=pass
11522 19:25:08.919339
11523 19:25:09.102764
11524 19:25:09.111200 test USERPTR (select): OK
11525 19:25:09.140434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=pass>
11526 19:25:09.141274 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=pass
11528 19:25:09.147046 test DMABUF: Cannot test, specify --expbuf-device
11529 19:25:09.155455
11530 19:25:09.173527 Total for uvcvideo device /dev/video0: 54, Succeeded: 51, Failed: 3, Warnings: 3
11531 19:25:09.177441 <LAVA_TEST_RUNNER EXIT>
11532 19:25:09.178271 ok: lava_test_shell seems to have completed
11533 19:25:09.178673 Marking unfinished test run as failed
11535 19:25:09.183891 CREATE_BUFS-maximum-buffers:
result: pass
set: Buffer-ioctls-Input-0
Composing:
result: pass
set: Format-ioctls-Input-0
Cropping:
result: pass
set: Format-ioctls-Input-0
MC-information-see-Media-Driver-Info-above:
result: pass
set: Required-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-no-poll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls-Input-0
Scaling:
result: pass
set: Format-ioctls-Input-0
USERPTR-no-poll:
result: pass
set: Streaming-ioctls_Test-input-0
USERPTR-select:
result: pass
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls-Input-0
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls-Input-0
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls-Input-0
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_S_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: pass
set: Control-ioctls-Input-0
blocking-wait:
result: pass
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video0-open:
result: pass
set: Allow-for-multiple-opens
11536 19:25:09.184567 end: 3.1 lava-test-shell (duration 00:00:10) [common]
11537 19:25:09.185044 end: 3 lava-test-retry (duration 00:00:10) [common]
11538 19:25:09.185555 start: 4 finalize (timeout 00:07:57) [common]
11539 19:25:09.186051 start: 4.1 power-off (timeout 00:00:30) [common]
11540 19:25:09.186862 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
11541 19:25:09.269739 >> Command sent successfully.
11542 19:25:09.274310 Returned 0 in 0 seconds
11543 19:25:09.375275 end: 4.1 power-off (duration 00:00:00) [common]
11545 19:25:09.376775 start: 4.2 read-feedback (timeout 00:07:56) [common]
11546 19:25:09.378076 Listened to connection for namespace 'common' for up to 1s
11547 19:25:10.378830 Finalising connection for namespace 'common'
11548 19:25:10.379564 Disconnecting from shell: Finalise
11549 19:25:10.380022 / #
11550 19:25:10.481042 end: 4.2 read-feedback (duration 00:00:01) [common]
11551 19:25:10.481766 end: 4 finalize (duration 00:00:01) [common]
11552 19:25:10.482375 Cleaning after the job
11553 19:25:10.483028 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13420357/tftp-deploy-lhsbc3e1/ramdisk
11554 19:25:10.505048 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13420357/tftp-deploy-lhsbc3e1/kernel
11555 19:25:10.524088 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13420357/tftp-deploy-lhsbc3e1/dtb
11556 19:25:10.524388 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13420357/tftp-deploy-lhsbc3e1/modules
11557 19:25:10.533446 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/13420357
11558 19:25:10.593844 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/13420357
11559 19:25:10.594025 Job finished correctly