Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 24
- Errors: 0
- Kernel Errors: 36
- Boot result: PASS
1 19:21:19.504566 lava-dispatcher, installed at version: 2024.01
2 19:21:19.504770 start: 0 validate
3 19:21:19.504893 Start time: 2024-04-18 19:21:19.504885+00:00 (UTC)
4 19:21:19.505011 Using caching service: 'http://localhost/cache/?uri=%s'
5 19:21:19.505135 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 19:21:19.766518 Using caching service: 'http://localhost/cache/?uri=%s'
7 19:21:19.767164 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 19:21:45.777510 Using caching service: 'http://localhost/cache/?uri=%s'
9 19:21:45.777681 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 19:21:46.035433 Using caching service: 'http://localhost/cache/?uri=%s'
11 19:21:46.036132 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 19:21:46.556432 Using caching service: 'http://localhost/cache/?uri=%s'
13 19:21:46.557085 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 19:21:48.566055 validate duration: 29.06
16 19:21:48.566338 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 19:21:48.566433 start: 1.1 download-retry (timeout 00:10:00) [common]
18 19:21:48.566520 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 19:21:48.566644 Not decompressing ramdisk as can be used compressed.
20 19:21:48.566727 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/initrd.cpio.gz
21 19:21:48.566793 saving as /var/lib/lava/dispatcher/tmp/13420331/tftp-deploy-9vswnwe8/ramdisk/initrd.cpio.gz
22 19:21:48.566855 total size: 5628182 (5 MB)
23 19:21:48.824586 progress 0 % (0 MB)
24 19:21:48.826350 progress 5 % (0 MB)
25 19:21:48.828078 progress 10 % (0 MB)
26 19:21:48.829474 progress 15 % (0 MB)
27 19:21:48.831014 progress 20 % (1 MB)
28 19:21:48.832477 progress 25 % (1 MB)
29 19:21:48.834317 progress 30 % (1 MB)
30 19:21:48.836088 progress 35 % (1 MB)
31 19:21:48.837460 progress 40 % (2 MB)
32 19:21:48.838985 progress 45 % (2 MB)
33 19:21:48.840589 progress 50 % (2 MB)
34 19:21:48.842142 progress 55 % (2 MB)
35 19:21:48.843656 progress 60 % (3 MB)
36 19:21:48.845177 progress 65 % (3 MB)
37 19:21:48.846738 progress 70 % (3 MB)
38 19:21:48.848148 progress 75 % (4 MB)
39 19:21:48.849659 progress 80 % (4 MB)
40 19:21:48.851168 progress 85 % (4 MB)
41 19:21:48.852867 progress 90 % (4 MB)
42 19:21:48.854435 progress 95 % (5 MB)
43 19:21:48.856074 progress 100 % (5 MB)
44 19:21:48.856314 5 MB downloaded in 0.29 s (18.54 MB/s)
45 19:21:48.856546 end: 1.1.1 http-download (duration 00:00:00) [common]
47 19:21:48.856782 end: 1.1 download-retry (duration 00:00:00) [common]
48 19:21:48.856869 start: 1.2 download-retry (timeout 00:10:00) [common]
49 19:21:48.856954 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 19:21:48.857090 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 19:21:48.857158 saving as /var/lib/lava/dispatcher/tmp/13420331/tftp-deploy-9vswnwe8/kernel/Image
52 19:21:48.857222 total size: 54286848 (51 MB)
53 19:21:48.857283 No compression specified
54 19:21:48.858488 progress 0 % (0 MB)
55 19:21:48.872913 progress 5 % (2 MB)
56 19:21:48.887426 progress 10 % (5 MB)
57 19:21:48.903070 progress 15 % (7 MB)
58 19:21:48.918686 progress 20 % (10 MB)
59 19:21:48.932707 progress 25 % (12 MB)
60 19:21:48.947343 progress 30 % (15 MB)
61 19:21:48.961520 progress 35 % (18 MB)
62 19:21:48.975759 progress 40 % (20 MB)
63 19:21:48.990087 progress 45 % (23 MB)
64 19:21:49.004455 progress 50 % (25 MB)
65 19:21:49.018778 progress 55 % (28 MB)
66 19:21:49.033030 progress 60 % (31 MB)
67 19:21:49.047135 progress 65 % (33 MB)
68 19:21:49.061418 progress 70 % (36 MB)
69 19:21:49.075661 progress 75 % (38 MB)
70 19:21:49.089888 progress 80 % (41 MB)
71 19:21:49.104148 progress 85 % (44 MB)
72 19:21:49.118202 progress 90 % (46 MB)
73 19:21:49.132126 progress 95 % (49 MB)
74 19:21:49.145987 progress 100 % (51 MB)
75 19:21:49.146239 51 MB downloaded in 0.29 s (179.14 MB/s)
76 19:21:49.146404 end: 1.2.1 http-download (duration 00:00:00) [common]
78 19:21:49.146637 end: 1.2 download-retry (duration 00:00:00) [common]
79 19:21:49.146725 start: 1.3 download-retry (timeout 00:09:59) [common]
80 19:21:49.146813 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 19:21:49.146956 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 19:21:49.147024 saving as /var/lib/lava/dispatcher/tmp/13420331/tftp-deploy-9vswnwe8/dtb/mt8192-asurada-spherion-r0.dtb
83 19:21:49.147085 total size: 47230 (0 MB)
84 19:21:49.147145 No compression specified
85 19:21:49.148244 progress 69 % (0 MB)
86 19:21:49.148511 progress 100 % (0 MB)
87 19:21:49.148664 0 MB downloaded in 0.00 s (28.57 MB/s)
88 19:21:49.148786 end: 1.3.1 http-download (duration 00:00:00) [common]
90 19:21:49.149081 end: 1.3 download-retry (duration 00:00:00) [common]
91 19:21:49.149204 start: 1.4 download-retry (timeout 00:09:59) [common]
92 19:21:49.149286 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 19:21:49.149403 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/full.rootfs.tar.xz
94 19:21:49.149469 saving as /var/lib/lava/dispatcher/tmp/13420331/tftp-deploy-9vswnwe8/nfsrootfs/full.rootfs.tar
95 19:21:49.149528 total size: 107552908 (102 MB)
96 19:21:49.149589 Using unxz to decompress xz
97 19:21:49.153973 progress 0 % (0 MB)
98 19:21:49.450803 progress 5 % (5 MB)
99 19:21:49.787301 progress 10 % (10 MB)
100 19:21:50.114218 progress 15 % (15 MB)
101 19:21:50.442536 progress 20 % (20 MB)
102 19:21:50.705397 progress 25 % (25 MB)
103 19:21:50.994562 progress 30 % (30 MB)
104 19:21:51.311975 progress 35 % (35 MB)
105 19:21:51.480273 progress 40 % (41 MB)
106 19:21:51.678755 progress 45 % (46 MB)
107 19:21:51.983807 progress 50 % (51 MB)
108 19:21:52.290969 progress 55 % (56 MB)
109 19:21:52.632697 progress 60 % (61 MB)
110 19:21:52.970899 progress 65 % (66 MB)
111 19:21:53.307489 progress 70 % (71 MB)
112 19:21:53.650928 progress 75 % (76 MB)
113 19:21:53.957738 progress 80 % (82 MB)
114 19:21:54.275389 progress 85 % (87 MB)
115 19:21:54.598176 progress 90 % (92 MB)
116 19:21:54.926759 progress 95 % (97 MB)
117 19:21:55.264220 progress 100 % (102 MB)
118 19:21:55.269629 102 MB downloaded in 6.12 s (16.76 MB/s)
119 19:21:55.269926 end: 1.4.1 http-download (duration 00:00:06) [common]
121 19:21:55.270207 end: 1.4 download-retry (duration 00:00:06) [common]
122 19:21:55.270305 start: 1.5 download-retry (timeout 00:09:53) [common]
123 19:21:55.270396 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 19:21:55.270556 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 19:21:55.270627 saving as /var/lib/lava/dispatcher/tmp/13420331/tftp-deploy-9vswnwe8/modules/modules.tar
126 19:21:55.270689 total size: 8631416 (8 MB)
127 19:21:55.270753 Using unxz to decompress xz
128 19:21:55.274910 progress 0 % (0 MB)
129 19:21:55.294637 progress 5 % (0 MB)
130 19:21:55.322427 progress 10 % (0 MB)
131 19:21:55.348628 progress 15 % (1 MB)
132 19:21:55.373987 progress 20 % (1 MB)
133 19:21:55.400411 progress 25 % (2 MB)
134 19:21:55.427833 progress 30 % (2 MB)
135 19:21:55.453325 progress 35 % (2 MB)
136 19:21:55.480257 progress 40 % (3 MB)
137 19:21:55.505131 progress 45 % (3 MB)
138 19:21:55.532193 progress 50 % (4 MB)
139 19:21:55.559161 progress 55 % (4 MB)
140 19:21:55.588966 progress 60 % (4 MB)
141 19:21:55.615048 progress 65 % (5 MB)
142 19:21:55.641260 progress 70 % (5 MB)
143 19:21:55.666493 progress 75 % (6 MB)
144 19:21:55.692406 progress 80 % (6 MB)
145 19:21:55.718623 progress 85 % (7 MB)
146 19:21:55.748614 progress 90 % (7 MB)
147 19:21:55.779772 progress 95 % (7 MB)
148 19:21:55.807799 progress 100 % (8 MB)
149 19:21:55.813642 8 MB downloaded in 0.54 s (15.16 MB/s)
150 19:21:55.813988 end: 1.5.1 http-download (duration 00:00:01) [common]
152 19:21:55.814306 end: 1.5 download-retry (duration 00:00:01) [common]
153 19:21:55.814419 start: 1.6 prepare-tftp-overlay (timeout 00:09:53) [common]
154 19:21:55.814531 start: 1.6.1 extract-nfsrootfs (timeout 00:09:53) [common]
155 19:21:58.083294 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/13420331/extract-nfsrootfs-8q2m2gfc
156 19:21:58.083498 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 19:21:58.083601 start: 1.6.2 lava-overlay (timeout 00:09:50) [common]
158 19:21:58.083773 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/13420331/lava-overlay-7hmtc9xc
159 19:21:58.084040 makedir: /var/lib/lava/dispatcher/tmp/13420331/lava-overlay-7hmtc9xc/lava-13420331/bin
160 19:21:58.084145 makedir: /var/lib/lava/dispatcher/tmp/13420331/lava-overlay-7hmtc9xc/lava-13420331/tests
161 19:21:58.084255 makedir: /var/lib/lava/dispatcher/tmp/13420331/lava-overlay-7hmtc9xc/lava-13420331/results
162 19:21:58.084388 Creating /var/lib/lava/dispatcher/tmp/13420331/lava-overlay-7hmtc9xc/lava-13420331/bin/lava-add-keys
163 19:21:58.084564 Creating /var/lib/lava/dispatcher/tmp/13420331/lava-overlay-7hmtc9xc/lava-13420331/bin/lava-add-sources
164 19:21:58.084723 Creating /var/lib/lava/dispatcher/tmp/13420331/lava-overlay-7hmtc9xc/lava-13420331/bin/lava-background-process-start
165 19:21:58.084880 Creating /var/lib/lava/dispatcher/tmp/13420331/lava-overlay-7hmtc9xc/lava-13420331/bin/lava-background-process-stop
166 19:21:58.085035 Creating /var/lib/lava/dispatcher/tmp/13420331/lava-overlay-7hmtc9xc/lava-13420331/bin/lava-common-functions
167 19:21:58.085161 Creating /var/lib/lava/dispatcher/tmp/13420331/lava-overlay-7hmtc9xc/lava-13420331/bin/lava-echo-ipv4
168 19:21:58.085282 Creating /var/lib/lava/dispatcher/tmp/13420331/lava-overlay-7hmtc9xc/lava-13420331/bin/lava-install-packages
169 19:21:58.085402 Creating /var/lib/lava/dispatcher/tmp/13420331/lava-overlay-7hmtc9xc/lava-13420331/bin/lava-installed-packages
170 19:21:58.085521 Creating /var/lib/lava/dispatcher/tmp/13420331/lava-overlay-7hmtc9xc/lava-13420331/bin/lava-os-build
171 19:21:58.085641 Creating /var/lib/lava/dispatcher/tmp/13420331/lava-overlay-7hmtc9xc/lava-13420331/bin/lava-probe-channel
172 19:21:58.085760 Creating /var/lib/lava/dispatcher/tmp/13420331/lava-overlay-7hmtc9xc/lava-13420331/bin/lava-probe-ip
173 19:21:58.085878 Creating /var/lib/lava/dispatcher/tmp/13420331/lava-overlay-7hmtc9xc/lava-13420331/bin/lava-target-ip
174 19:21:58.085996 Creating /var/lib/lava/dispatcher/tmp/13420331/lava-overlay-7hmtc9xc/lava-13420331/bin/lava-target-mac
175 19:21:58.086115 Creating /var/lib/lava/dispatcher/tmp/13420331/lava-overlay-7hmtc9xc/lava-13420331/bin/lava-target-storage
176 19:21:58.086259 Creating /var/lib/lava/dispatcher/tmp/13420331/lava-overlay-7hmtc9xc/lava-13420331/bin/lava-test-case
177 19:21:58.086379 Creating /var/lib/lava/dispatcher/tmp/13420331/lava-overlay-7hmtc9xc/lava-13420331/bin/lava-test-event
178 19:21:58.086498 Creating /var/lib/lava/dispatcher/tmp/13420331/lava-overlay-7hmtc9xc/lava-13420331/bin/lava-test-feedback
179 19:21:58.086622 Creating /var/lib/lava/dispatcher/tmp/13420331/lava-overlay-7hmtc9xc/lava-13420331/bin/lava-test-raise
180 19:21:58.086742 Creating /var/lib/lava/dispatcher/tmp/13420331/lava-overlay-7hmtc9xc/lava-13420331/bin/lava-test-reference
181 19:21:58.086863 Creating /var/lib/lava/dispatcher/tmp/13420331/lava-overlay-7hmtc9xc/lava-13420331/bin/lava-test-runner
182 19:21:58.086982 Creating /var/lib/lava/dispatcher/tmp/13420331/lava-overlay-7hmtc9xc/lava-13420331/bin/lava-test-set
183 19:21:58.087100 Creating /var/lib/lava/dispatcher/tmp/13420331/lava-overlay-7hmtc9xc/lava-13420331/bin/lava-test-shell
184 19:21:58.087223 Updating /var/lib/lava/dispatcher/tmp/13420331/lava-overlay-7hmtc9xc/lava-13420331/bin/lava-install-packages (oe)
185 19:21:58.087373 Updating /var/lib/lava/dispatcher/tmp/13420331/lava-overlay-7hmtc9xc/lava-13420331/bin/lava-installed-packages (oe)
186 19:21:58.087491 Creating /var/lib/lava/dispatcher/tmp/13420331/lava-overlay-7hmtc9xc/lava-13420331/environment
187 19:21:58.087582 LAVA metadata
188 19:21:58.087650 - LAVA_JOB_ID=13420331
189 19:21:58.087715 - LAVA_DISPATCHER_IP=192.168.201.1
190 19:21:58.087853 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:50) [common]
191 19:21:58.087970 skipped lava-vland-overlay
192 19:21:58.088047 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 19:21:58.088129 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:50) [common]
194 19:21:58.088208 skipped lava-multinode-overlay
195 19:21:58.088323 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 19:21:58.088430 start: 1.6.2.3 test-definition (timeout 00:09:50) [common]
197 19:21:58.088532 Loading test definitions
198 19:21:58.088663 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:50) [common]
199 19:21:58.088763 Using /lava-13420331 at stage 0
200 19:21:58.089182 uuid=13420331_1.6.2.3.1 testdef=None
201 19:21:58.089298 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 19:21:58.089409 start: 1.6.2.3.2 test-overlay (timeout 00:09:50) [common]
203 19:21:58.090117 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 19:21:58.090470 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:50) [common]
206 19:21:58.091378 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 19:21:58.091739 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:50) [common]
209 19:21:58.092644 runner path: /var/lib/lava/dispatcher/tmp/13420331/lava-overlay-7hmtc9xc/lava-13420331/0/tests/0_dmesg test_uuid 13420331_1.6.2.3.1
210 19:21:58.092800 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 19:21:58.093003 Creating lava-test-runner.conf files
213 19:21:58.093064 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/13420331/lava-overlay-7hmtc9xc/lava-13420331/0 for stage 0
214 19:21:58.093155 - 0_dmesg
215 19:21:58.093289 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
216 19:21:58.093372 start: 1.6.2.4 compress-overlay (timeout 00:09:50) [common]
217 19:21:58.099581 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
218 19:21:58.099712 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:50) [common]
219 19:21:58.099796 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
220 19:21:58.099880 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
221 19:21:58.100007 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:50) [common]
222 19:21:58.268779 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
223 19:21:58.269160 start: 1.6.4 extract-modules (timeout 00:09:50) [common]
224 19:21:58.269277 extracting modules file /var/lib/lava/dispatcher/tmp/13420331/tftp-deploy-9vswnwe8/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13420331/extract-nfsrootfs-8q2m2gfc
225 19:21:58.504813 extracting modules file /var/lib/lava/dispatcher/tmp/13420331/tftp-deploy-9vswnwe8/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13420331/extract-overlay-ramdisk-vc46c91z/ramdisk
226 19:21:58.747468 end: 1.6.4 extract-modules (duration 00:00:00) [common]
227 19:21:58.747696 start: 1.6.5 apply-overlay-tftp (timeout 00:09:50) [common]
228 19:21:58.747830 [common] Applying overlay to NFS
229 19:21:58.747976 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13420331/compress-overlay-z41rlgl_/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/13420331/extract-nfsrootfs-8q2m2gfc
230 19:21:58.756434 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
231 19:21:58.756599 start: 1.6.6 configure-preseed-file (timeout 00:09:50) [common]
232 19:21:58.756714 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
233 19:21:58.756840 start: 1.6.7 compress-ramdisk (timeout 00:09:50) [common]
234 19:21:58.756930 Building ramdisk /var/lib/lava/dispatcher/tmp/13420331/extract-overlay-ramdisk-vc46c91z/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/13420331/extract-overlay-ramdisk-vc46c91z/ramdisk
235 19:21:59.105865 >> 130624 blocks
236 19:22:01.206641 rename /var/lib/lava/dispatcher/tmp/13420331/extract-overlay-ramdisk-vc46c91z/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/13420331/tftp-deploy-9vswnwe8/ramdisk/ramdisk.cpio.gz
237 19:22:01.207190 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
238 19:22:01.207367 start: 1.6.8 prepare-kernel (timeout 00:09:47) [common]
239 19:22:01.207516 start: 1.6.8.1 prepare-fit (timeout 00:09:47) [common]
240 19:22:01.207669 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/13420331/tftp-deploy-9vswnwe8/kernel/Image'
241 19:22:15.693207 Returned 0 in 14 seconds
242 19:22:15.793878 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/13420331/tftp-deploy-9vswnwe8/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/13420331/tftp-deploy-9vswnwe8/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/13420331/tftp-deploy-9vswnwe8/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/13420331/tftp-deploy-9vswnwe8/kernel/image.itb
243 19:22:16.205160 output: FIT description: Kernel Image image with one or more FDT blobs
244 19:22:16.205522 output: Created: Thu Apr 18 20:22:16 2024
245 19:22:16.205622 output: Image 0 (kernel-1)
246 19:22:16.205705 output: Description:
247 19:22:16.205787 output: Created: Thu Apr 18 20:22:16 2024
248 19:22:16.205905 output: Type: Kernel Image
249 19:22:16.205986 output: Compression: lzma compressed
250 19:22:16.206082 output: Data Size: 12910355 Bytes = 12607.77 KiB = 12.31 MiB
251 19:22:16.206181 output: Architecture: AArch64
252 19:22:16.206277 output: OS: Linux
253 19:22:16.206374 output: Load Address: 0x00000000
254 19:22:16.206470 output: Entry Point: 0x00000000
255 19:22:16.206564 output: Hash algo: crc32
256 19:22:16.206659 output: Hash value: bbac8b0b
257 19:22:16.206753 output: Image 1 (fdt-1)
258 19:22:16.206845 output: Description: mt8192-asurada-spherion-r0
259 19:22:16.206937 output: Created: Thu Apr 18 20:22:16 2024
260 19:22:16.207028 output: Type: Flat Device Tree
261 19:22:16.207119 output: Compression: uncompressed
262 19:22:16.207210 output: Data Size: 47230 Bytes = 46.12 KiB = 0.05 MiB
263 19:22:16.207300 output: Architecture: AArch64
264 19:22:16.207459 output: Hash algo: crc32
265 19:22:16.207549 output: Hash value: 4bf0d1ac
266 19:22:16.207639 output: Image 2 (ramdisk-1)
267 19:22:16.207729 output: Description: unavailable
268 19:22:16.207819 output: Created: Thu Apr 18 20:22:16 2024
269 19:22:16.207939 output: Type: RAMDisk Image
270 19:22:16.208045 output: Compression: Unknown Compression
271 19:22:16.208137 output: Data Size: 18769254 Bytes = 18329.35 KiB = 17.90 MiB
272 19:22:16.208229 output: Architecture: AArch64
273 19:22:16.208319 output: OS: Linux
274 19:22:16.208409 output: Load Address: unavailable
275 19:22:16.208499 output: Entry Point: unavailable
276 19:22:16.208588 output: Hash algo: crc32
277 19:22:16.208678 output: Hash value: 75b5c482
278 19:22:16.208775 output: Default Configuration: 'conf-1'
279 19:22:16.208869 output: Configuration 0 (conf-1)
280 19:22:16.209002 output: Description: mt8192-asurada-spherion-r0
281 19:22:16.209148 output: Kernel: kernel-1
282 19:22:16.209254 output: Init Ramdisk: ramdisk-1
283 19:22:16.209344 output: FDT: fdt-1
284 19:22:16.209436 output: Loadables: kernel-1
285 19:22:16.209534 output:
286 19:22:16.209791 end: 1.6.8.1 prepare-fit (duration 00:00:15) [common]
287 19:22:16.209929 end: 1.6.8 prepare-kernel (duration 00:00:15) [common]
288 19:22:16.210073 end: 1.6 prepare-tftp-overlay (duration 00:00:20) [common]
289 19:22:16.210209 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:32) [common]
290 19:22:16.210328 No LXC device requested
291 19:22:16.210448 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
292 19:22:16.210578 start: 1.8 deploy-device-env (timeout 00:09:32) [common]
293 19:22:16.210694 end: 1.8 deploy-device-env (duration 00:00:00) [common]
294 19:22:16.210804 Checking files for TFTP limit of 4294967296 bytes.
295 19:22:16.211392 end: 1 tftp-deploy (duration 00:00:28) [common]
296 19:22:16.211512 start: 2 depthcharge-action (timeout 00:05:00) [common]
297 19:22:16.211642 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
298 19:22:16.211824 substitutions:
299 19:22:16.211950 - {DTB}: 13420331/tftp-deploy-9vswnwe8/dtb/mt8192-asurada-spherion-r0.dtb
300 19:22:16.212034 - {INITRD}: 13420331/tftp-deploy-9vswnwe8/ramdisk/ramdisk.cpio.gz
301 19:22:16.212114 - {KERNEL}: 13420331/tftp-deploy-9vswnwe8/kernel/Image
302 19:22:16.212213 - {LAVA_MAC}: None
303 19:22:16.212309 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/13420331/extract-nfsrootfs-8q2m2gfc
304 19:22:16.212405 - {NFS_SERVER_IP}: 192.168.201.1
305 19:22:16.212500 - {PRESEED_CONFIG}: None
306 19:22:16.212594 - {PRESEED_LOCAL}: None
307 19:22:16.212689 - {RAMDISK}: 13420331/tftp-deploy-9vswnwe8/ramdisk/ramdisk.cpio.gz
308 19:22:16.212784 - {ROOT_PART}: None
309 19:22:16.212878 - {ROOT}: None
310 19:22:16.212972 - {SERVER_IP}: 192.168.201.1
311 19:22:16.213065 - {TEE}: None
312 19:22:16.213158 Parsed boot commands:
313 19:22:16.213253 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
314 19:22:16.213577 Parsed boot commands: tftpboot 192.168.201.1 13420331/tftp-deploy-9vswnwe8/kernel/image.itb 13420331/tftp-deploy-9vswnwe8/kernel/cmdline
315 19:22:16.213737 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
316 19:22:16.213868 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
317 19:22:16.214005 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
318 19:22:16.214152 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
319 19:22:16.214271 Not connected, no need to disconnect.
320 19:22:16.214386 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
321 19:22:16.214505 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
322 19:22:16.214608 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
323 19:22:16.219257 Setting prompt string to ['lava-test: # ']
324 19:22:16.219725 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
325 19:22:16.219915 end: 2.2.1 reset-connection (duration 00:00:00) [common]
326 19:22:16.220037 start: 2.2.2 reset-device (timeout 00:05:00) [common]
327 19:22:16.220177 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
328 19:22:16.220526 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=reboot'
329 19:22:21.353862 >> Command sent successfully.
330 19:22:21.356407 Returned 0 in 5 seconds
331 19:22:21.456855 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
333 19:22:21.457223 end: 2.2.2 reset-device (duration 00:00:05) [common]
334 19:22:21.457341 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
335 19:22:21.457444 Setting prompt string to 'Starting depthcharge on Spherion...'
336 19:22:21.457541 Changing prompt to 'Starting depthcharge on Spherion...'
337 19:22:21.457663 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
338 19:22:21.458040 [Enter `^Ec?' for help]
339 19:22:21.859687
340 19:22:21.859874
341 19:22:21.860020 F0: 102B 0000
342 19:22:21.860127
343 19:22:21.860220 F3: 1001 0000 [0200]
344 19:22:21.862698
345 19:22:21.862804 F3: 1001 0000
346 19:22:21.862894
347 19:22:21.862981 F7: 102D 0000
348 19:22:21.863058
349 19:22:21.865753 F1: 0000 0000
350 19:22:21.865852
351 19:22:21.865940 V0: 0000 0000 [0001]
352 19:22:21.866038
353 19:22:21.869355 00: 0007 8000
354 19:22:21.869464
355 19:22:21.869562 01: 0000 0000
356 19:22:21.869653
357 19:22:21.872399 BP: 0C00 0209 [0000]
358 19:22:21.872500
359 19:22:21.872596 G0: 1182 0000
360 19:22:21.872686
361 19:22:21.876047 EC: 0000 0021 [4000]
362 19:22:21.876140
363 19:22:21.876236 S7: 0000 0000 [0000]
364 19:22:21.876339
365 19:22:21.879098 CC: 0000 0000 [0001]
366 19:22:21.879195
367 19:22:21.879282 T0: 0000 0040 [010F]
368 19:22:21.879370
369 19:22:21.882157 Jump to BL
370 19:22:21.882270
371 19:22:21.906270
372 19:22:21.906451
373 19:22:21.906520
374 19:22:21.916006 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
375 19:22:21.918986 ARM64: Exception handlers installed.
376 19:22:21.919080 ARM64: Testing exception
377 19:22:21.922324 ARM64: Done test exception
378 19:22:21.929160 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
379 19:22:21.939868 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
380 19:22:21.946596 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
381 19:22:21.957353 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
382 19:22:21.963601 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
383 19:22:21.973920 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
384 19:22:21.983722 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
385 19:22:21.990492 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
386 19:22:22.009328 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
387 19:22:22.012326 WDT: Last reset was cold boot
388 19:22:22.015965 SPI1(PAD0) initialized at 2873684 Hz
389 19:22:22.019643 SPI5(PAD0) initialized at 992727 Hz
390 19:22:22.022582 VBOOT: Loading verstage.
391 19:22:22.029011 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
392 19:22:22.032380 FMAP: Found "FLASH" version 1.1 at 0x20000.
393 19:22:22.036036 FMAP: base = 0x0 size = 0x800000 #areas = 25
394 19:22:22.039060 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
395 19:22:22.046817 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
396 19:22:22.053344 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
397 19:22:22.063949 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
398 19:22:22.064113
399 19:22:22.064186
400 19:22:22.074283 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
401 19:22:22.077232 ARM64: Exception handlers installed.
402 19:22:22.080585 ARM64: Testing exception
403 19:22:22.080682 ARM64: Done test exception
404 19:22:22.087477 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
405 19:22:22.090598 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
406 19:22:22.105575 Probing TPM: . done!
407 19:22:22.105724 TPM ready after 0 ms
408 19:22:22.111665 Connected to device vid:did:rid of 1ae0:0028:00
409 19:22:22.122107 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
410 19:22:22.189468 Initialized TPM device CR50 revision 0
411 19:22:22.208056 tlcl_send_startup: Startup return code is 0
412 19:22:22.217150 TPM: setup succeeded
413 19:22:22.232868 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
414 19:22:22.240765 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
415 19:22:22.253757 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
416 19:22:22.262731 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
417 19:22:22.265657 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
418 19:22:22.269369 in-header: 03 07 00 00 08 00 00 00
419 19:22:22.273040 in-data: aa e4 47 04 13 02 00 00
420 19:22:22.276747 Chrome EC: UHEPI supported
421 19:22:22.280349 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
422 19:22:22.285121 in-header: 03 ad 00 00 08 00 00 00
423 19:22:22.288687 in-data: 00 20 20 08 00 00 00 00
424 19:22:22.288781 Phase 1
425 19:22:22.294813 FMAP: area GBB found @ 3f5000 (12032 bytes)
426 19:22:22.302097 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
427 19:22:22.304968 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
428 19:22:22.308505 Recovery requested (1009000e)
429 19:22:22.316448 TPM: Extending digest for VBOOT: boot mode into PCR 0
430 19:22:22.321765 tlcl_extend: response is 0
431 19:22:22.330950 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
432 19:22:22.335239 tlcl_extend: response is 0
433 19:22:22.341906 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
434 19:22:22.362918 read SPI 0x210d4 0x2173b: 15140 us, 9050 KB/s, 72.400 Mbps
435 19:22:22.369318 BS: bootblock times (exec / console): total (unknown) / 148 ms
436 19:22:22.369565
437 19:22:22.369683
438 19:22:22.379019 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
439 19:22:22.382648 ARM64: Exception handlers installed.
440 19:22:22.385546 ARM64: Testing exception
441 19:22:22.385719 ARM64: Done test exception
442 19:22:22.407695 pmic_efuse_setting: Set efuses in 11 msecs
443 19:22:22.411392 pmwrap_interface_init: Select PMIF_VLD_RDY
444 19:22:22.417569 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
445 19:22:22.421184 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
446 19:22:22.427723 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
447 19:22:22.430847 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
448 19:22:22.437423 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
449 19:22:22.440651 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
450 19:22:22.447394 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
451 19:22:22.450777 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
452 19:22:22.454347 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
453 19:22:22.460932 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
454 19:22:22.463936 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
455 19:22:22.470538 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
456 19:22:22.474183 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
457 19:22:22.481145 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
458 19:22:22.487271 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
459 19:22:22.490802 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
460 19:22:22.497115 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
461 19:22:22.503874 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
462 19:22:22.507548 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
463 19:22:22.513630 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
464 19:22:22.520349 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
465 19:22:22.524154 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
466 19:22:22.530258 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
467 19:22:22.536700 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
468 19:22:22.540017 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
469 19:22:22.546949 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
470 19:22:22.553407 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
471 19:22:22.556666 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
472 19:22:22.563682 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
473 19:22:22.566720 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
474 19:22:22.573532 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
475 19:22:22.576626 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
476 19:22:22.583181 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
477 19:22:22.586457 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
478 19:22:22.593361 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
479 19:22:22.596288 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
480 19:22:22.603220 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
481 19:22:22.606343 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
482 19:22:22.609792 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
483 19:22:22.616531 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
484 19:22:22.619646 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
485 19:22:22.623290 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
486 19:22:22.629441 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
487 19:22:22.633269 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
488 19:22:22.636244 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
489 19:22:22.643031 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
490 19:22:22.646144 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
491 19:22:22.649525 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
492 19:22:22.655895 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
493 19:22:22.659456 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
494 19:22:22.662858 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
495 19:22:22.669213 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
496 19:22:22.679423 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
497 19:22:22.682454 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
498 19:22:22.692727 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
499 19:22:22.699007 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
500 19:22:22.705540 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
501 19:22:22.709032 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
502 19:22:22.712072 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
503 19:22:22.720620 [RTC]rtc_enable_dcxo,68: con=0x406, osc32con=0xde6b, sec=0x0
504 19:22:22.726837 [RTC]rtc_check_state,173: con=406, pwrkey1=a357, pwrkey2=67d2
505 19:22:22.730555 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
506 19:22:22.737199 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
507 19:22:22.745182 [RTC]rtc_get_frequency_meter,154: input=15, output=853
508 19:22:22.754688 [RTC]rtc_get_frequency_meter,154: input=7, output=726
509 19:22:22.764082 [RTC]rtc_get_frequency_meter,154: input=11, output=790
510 19:22:22.773315 [RTC]rtc_get_frequency_meter,154: input=13, output=822
511 19:22:22.782786 [RTC]rtc_get_frequency_meter,154: input=12, output=805
512 19:22:22.792128 [RTC]rtc_get_frequency_meter,154: input=11, output=788
513 19:22:22.801995 [RTC]rtc_get_frequency_meter,154: input=12, output=805
514 19:22:22.805053 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
515 19:22:22.812400 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
516 19:22:22.815683 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
517 19:22:22.818851 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
518 19:22:22.825647 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
519 19:22:22.828768 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
520 19:22:22.832246 ADC[4]: Raw value=904433 ID=7
521 19:22:22.832359 ADC[3]: Raw value=213916 ID=1
522 19:22:22.836006 RAM Code: 0x71
523 19:22:22.839039 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
524 19:22:22.845692 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
525 19:22:22.852516 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
526 19:22:22.859100 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
527 19:22:22.862071 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
528 19:22:22.865481 in-header: 03 07 00 00 08 00 00 00
529 19:22:22.869070 in-data: aa e4 47 04 13 02 00 00
530 19:22:22.872074 Chrome EC: UHEPI supported
531 19:22:22.879237 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
532 19:22:22.882044 in-header: 03 ed 00 00 08 00 00 00
533 19:22:22.885676 in-data: 80 20 60 08 00 00 00 00
534 19:22:22.888846 MRC: failed to locate region type 0.
535 19:22:22.895271 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
536 19:22:22.898753 DRAM-K: Running full calibration
537 19:22:22.905906 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
538 19:22:22.906036 header.status = 0x0
539 19:22:22.909553 header.version = 0x6 (expected: 0x6)
540 19:22:22.913719 header.size = 0xd00 (expected: 0xd00)
541 19:22:22.913811 header.flags = 0x0
542 19:22:22.920526 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
543 19:22:22.938922 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
544 19:22:22.946286 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
545 19:22:22.949420 dram_init: ddr_geometry: 2
546 19:22:22.949520 [EMI] MDL number = 2
547 19:22:22.952414 [EMI] Get MDL freq = 0
548 19:22:22.956131 dram_init: ddr_type: 0
549 19:22:22.956223 is_discrete_lpddr4: 1
550 19:22:22.959184 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
551 19:22:22.959288
552 19:22:22.959376
553 19:22:22.962782 [Bian_co] ETT version 0.0.0.1
554 19:22:22.965839 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
555 19:22:22.965991
556 19:22:22.972231 dramc_set_vcore_voltage set vcore to 650000
557 19:22:22.972327 Read voltage for 800, 4
558 19:22:22.975764 Vio18 = 0
559 19:22:22.975877 Vcore = 650000
560 19:22:22.975987 Vdram = 0
561 19:22:22.979335 Vddq = 0
562 19:22:22.979461 Vmddr = 0
563 19:22:22.982377 dram_init: config_dvfs: 1
564 19:22:22.985922 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
565 19:22:22.992345 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
566 19:22:22.995473 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
567 19:22:22.999173 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
568 19:22:23.002218 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
569 19:22:23.005506 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
570 19:22:23.009098 MEM_TYPE=3, freq_sel=18
571 19:22:23.012033 sv_algorithm_assistance_LP4_1600
572 19:22:23.015634 ============ PULL DRAM RESETB DOWN ============
573 19:22:23.018599 ========== PULL DRAM RESETB DOWN end =========
574 19:22:23.025356 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
575 19:22:23.028651 ===================================
576 19:22:23.028785 LPDDR4 DRAM CONFIGURATION
577 19:22:23.032319 ===================================
578 19:22:23.035305 EX_ROW_EN[0] = 0x0
579 19:22:23.038815 EX_ROW_EN[1] = 0x0
580 19:22:23.038903 LP4Y_EN = 0x0
581 19:22:23.042278 WORK_FSP = 0x0
582 19:22:23.042368 WL = 0x2
583 19:22:23.045062 RL = 0x2
584 19:22:23.045149 BL = 0x2
585 19:22:23.048738 RPST = 0x0
586 19:22:23.048833 RD_PRE = 0x0
587 19:22:23.051813 WR_PRE = 0x1
588 19:22:23.051914 WR_PST = 0x0
589 19:22:23.055008 DBI_WR = 0x0
590 19:22:23.055100 DBI_RD = 0x0
591 19:22:23.058690 OTF = 0x1
592 19:22:23.061627 ===================================
593 19:22:23.065211 ===================================
594 19:22:23.065302 ANA top config
595 19:22:23.068323 ===================================
596 19:22:23.072088 DLL_ASYNC_EN = 0
597 19:22:23.075111 ALL_SLAVE_EN = 1
598 19:22:23.078523 NEW_RANK_MODE = 1
599 19:22:23.078652 DLL_IDLE_MODE = 1
600 19:22:23.082079 LP45_APHY_COMB_EN = 1
601 19:22:23.085101 TX_ODT_DIS = 1
602 19:22:23.088764 NEW_8X_MODE = 1
603 19:22:23.091734 ===================================
604 19:22:23.095414 ===================================
605 19:22:23.095500 data_rate = 1600
606 19:22:23.098865 CKR = 1
607 19:22:23.102480 DQ_P2S_RATIO = 8
608 19:22:23.105963 ===================================
609 19:22:23.110121 CA_P2S_RATIO = 8
610 19:22:23.110247 DQ_CA_OPEN = 0
611 19:22:23.112980 DQ_SEMI_OPEN = 0
612 19:22:23.116462 CA_SEMI_OPEN = 0
613 19:22:23.120110 CA_FULL_RATE = 0
614 19:22:23.124340 DQ_CKDIV4_EN = 1
615 19:22:23.124450 CA_CKDIV4_EN = 1
616 19:22:23.127477 CA_PREDIV_EN = 0
617 19:22:23.130978 PH8_DLY = 0
618 19:22:23.134561 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
619 19:22:23.134655 DQ_AAMCK_DIV = 4
620 19:22:23.138714 CA_AAMCK_DIV = 4
621 19:22:23.142346 CA_ADMCK_DIV = 4
622 19:22:23.145294 DQ_TRACK_CA_EN = 0
623 19:22:23.148423 CA_PICK = 800
624 19:22:23.152141 CA_MCKIO = 800
625 19:22:23.152230 MCKIO_SEMI = 0
626 19:22:23.154896 PLL_FREQ = 3068
627 19:22:23.158396 DQ_UI_PI_RATIO = 32
628 19:22:23.161779 CA_UI_PI_RATIO = 0
629 19:22:23.164972 ===================================
630 19:22:23.168697 ===================================
631 19:22:23.171780 memory_type:LPDDR4
632 19:22:23.171931 GP_NUM : 10
633 19:22:23.174913 SRAM_EN : 1
634 19:22:23.178487 MD32_EN : 0
635 19:22:23.182067 ===================================
636 19:22:23.182193 [ANA_INIT] >>>>>>>>>>>>>>
637 19:22:23.184857 <<<<<< [CONFIGURE PHASE]: ANA_TX
638 19:22:23.188360 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
639 19:22:23.191395 ===================================
640 19:22:23.195002 data_rate = 1600,PCW = 0X7600
641 19:22:23.197996 ===================================
642 19:22:23.202190 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
643 19:22:23.205560 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
644 19:22:23.212730 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
645 19:22:23.216193 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
646 19:22:23.219327 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
647 19:22:23.223362 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
648 19:22:23.226987 [ANA_INIT] flow start
649 19:22:23.227102 [ANA_INIT] PLL >>>>>>>>
650 19:22:23.230637 [ANA_INIT] PLL <<<<<<<<
651 19:22:23.234286 [ANA_INIT] MIDPI >>>>>>>>
652 19:22:23.234416 [ANA_INIT] MIDPI <<<<<<<<
653 19:22:23.237801 [ANA_INIT] DLL >>>>>>>>
654 19:22:23.241442 [ANA_INIT] flow end
655 19:22:23.245371 ============ LP4 DIFF to SE enter ============
656 19:22:23.248382 ============ LP4 DIFF to SE exit ============
657 19:22:23.248532 [ANA_INIT] <<<<<<<<<<<<<
658 19:22:23.252165 [Flow] Enable top DCM control >>>>>
659 19:22:23.255774 [Flow] Enable top DCM control <<<<<
660 19:22:23.259524 Enable DLL master slave shuffle
661 19:22:23.267395 ==============================================================
662 19:22:23.267561 Gating Mode config
663 19:22:23.274166 ==============================================================
664 19:22:23.274287 Config description:
665 19:22:23.285264 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
666 19:22:23.292778 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
667 19:22:23.296353 SELPH_MODE 0: By rank 1: By Phase
668 19:22:23.300141 ==============================================================
669 19:22:23.303727 GAT_TRACK_EN = 1
670 19:22:23.306853 RX_GATING_MODE = 2
671 19:22:23.310473 RX_GATING_TRACK_MODE = 2
672 19:22:23.314206 SELPH_MODE = 1
673 19:22:23.316920 PICG_EARLY_EN = 1
674 19:22:23.320426 VALID_LAT_VALUE = 1
675 19:22:23.323187 ==============================================================
676 19:22:23.326671 Enter into Gating configuration >>>>
677 19:22:23.330392 Exit from Gating configuration <<<<
678 19:22:23.333502 Enter into DVFS_PRE_config >>>>>
679 19:22:23.344428 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
680 19:22:23.347511 Exit from DVFS_PRE_config <<<<<
681 19:22:23.351093 Enter into PICG configuration >>>>
682 19:22:23.354639 Exit from PICG configuration <<<<
683 19:22:23.357456 [RX_INPUT] configuration >>>>>
684 19:22:23.360699 [RX_INPUT] configuration <<<<<
685 19:22:23.364222 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
686 19:22:23.370882 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
687 19:22:23.377615 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
688 19:22:23.384254 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
689 19:22:23.391380 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
690 19:22:23.394866 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
691 19:22:23.398285 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
692 19:22:23.401870 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
693 19:22:23.409994 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
694 19:22:23.413678 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
695 19:22:23.417272 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
696 19:22:23.420747 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
697 19:22:23.424837 ===================================
698 19:22:23.424938 LPDDR4 DRAM CONFIGURATION
699 19:22:23.428797 ===================================
700 19:22:23.432289 EX_ROW_EN[0] = 0x0
701 19:22:23.432376 EX_ROW_EN[1] = 0x0
702 19:22:23.435720 LP4Y_EN = 0x0
703 19:22:23.435821 WORK_FSP = 0x0
704 19:22:23.439406 WL = 0x2
705 19:22:23.439496 RL = 0x2
706 19:22:23.443149 BL = 0x2
707 19:22:23.443234 RPST = 0x0
708 19:22:23.446773 RD_PRE = 0x0
709 19:22:23.446863 WR_PRE = 0x1
710 19:22:23.450396 WR_PST = 0x0
711 19:22:23.450483 DBI_WR = 0x0
712 19:22:23.454684 DBI_RD = 0x0
713 19:22:23.454772 OTF = 0x1
714 19:22:23.458394 ===================================
715 19:22:23.461946 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
716 19:22:23.465547 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
717 19:22:23.469043 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
718 19:22:23.472739 ===================================
719 19:22:23.476383 LPDDR4 DRAM CONFIGURATION
720 19:22:23.480093 ===================================
721 19:22:23.480214 EX_ROW_EN[0] = 0x10
722 19:22:23.484293 EX_ROW_EN[1] = 0x0
723 19:22:23.484415 LP4Y_EN = 0x0
724 19:22:23.487275 WORK_FSP = 0x0
725 19:22:23.487382 WL = 0x2
726 19:22:23.491524 RL = 0x2
727 19:22:23.491655 BL = 0x2
728 19:22:23.494897 RPST = 0x0
729 19:22:23.495066 RD_PRE = 0x0
730 19:22:23.498540 WR_PRE = 0x1
731 19:22:23.498669 WR_PST = 0x0
732 19:22:23.498786 DBI_WR = 0x0
733 19:22:23.502262 DBI_RD = 0x0
734 19:22:23.502369 OTF = 0x1
735 19:22:23.505709 ===================================
736 19:22:23.513047 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
737 19:22:23.517253 nWR fixed to 40
738 19:22:23.520961 [ModeRegInit_LP4] CH0 RK0
739 19:22:23.521049 [ModeRegInit_LP4] CH0 RK1
740 19:22:23.524646 [ModeRegInit_LP4] CH1 RK0
741 19:22:23.524732 [ModeRegInit_LP4] CH1 RK1
742 19:22:23.528178 match AC timing 13
743 19:22:23.531998 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
744 19:22:23.534879 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
745 19:22:23.542196 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
746 19:22:23.545729 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
747 19:22:23.549400 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
748 19:22:23.553002 [EMI DOE] emi_dcm 0
749 19:22:23.556730 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
750 19:22:23.556819 ==
751 19:22:23.560445 Dram Type= 6, Freq= 0, CH_0, rank 0
752 19:22:23.564065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
753 19:22:23.564153 ==
754 19:22:23.568228 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
755 19:22:23.574833 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
756 19:22:23.584607 [CA 0] Center 38 (7~69) winsize 63
757 19:22:23.588685 [CA 1] Center 37 (6~68) winsize 63
758 19:22:23.592389 [CA 2] Center 34 (4~65) winsize 62
759 19:22:23.596111 [CA 3] Center 34 (4~65) winsize 62
760 19:22:23.599629 [CA 4] Center 33 (3~64) winsize 62
761 19:22:23.603320 [CA 5] Center 33 (3~64) winsize 62
762 19:22:23.603434
763 19:22:23.606674 [CmdBusTrainingLP45] Vref(ca) range 1: 34
764 19:22:23.606783
765 19:22:23.610449 [CATrainingPosCal] consider 1 rank data
766 19:22:23.610566 u2DelayCellTimex100 = 270/100 ps
767 19:22:23.614217 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
768 19:22:23.617815 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
769 19:22:23.621628 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
770 19:22:23.625275 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
771 19:22:23.628989 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
772 19:22:23.634174 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
773 19:22:23.634287
774 19:22:23.636495 CA PerBit enable=1, Macro0, CA PI delay=33
775 19:22:23.636582
776 19:22:23.639925 [CBTSetCACLKResult] CA Dly = 33
777 19:22:23.643315 CS Dly: 5 (0~36)
778 19:22:23.643427 ==
779 19:22:23.646876 Dram Type= 6, Freq= 0, CH_0, rank 1
780 19:22:23.650556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 19:22:23.650643 ==
782 19:22:23.654468 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
783 19:22:23.661381 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
784 19:22:23.671124 [CA 0] Center 38 (7~69) winsize 63
785 19:22:23.674853 [CA 1] Center 37 (7~68) winsize 62
786 19:22:23.678510 [CA 2] Center 35 (4~66) winsize 63
787 19:22:23.682111 [CA 3] Center 35 (4~66) winsize 63
788 19:22:23.685760 [CA 4] Center 34 (3~65) winsize 63
789 19:22:23.689720 [CA 5] Center 33 (3~64) winsize 62
790 19:22:23.689854
791 19:22:23.693212 [CmdBusTrainingLP45] Vref(ca) range 1: 34
792 19:22:23.693319
793 19:22:23.696837 [CATrainingPosCal] consider 2 rank data
794 19:22:23.696960 u2DelayCellTimex100 = 270/100 ps
795 19:22:23.700619 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
796 19:22:23.704293 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
797 19:22:23.707956 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
798 19:22:23.711076 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
799 19:22:23.715142 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
800 19:22:23.718515 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
801 19:22:23.718626
802 19:22:23.726202 CA PerBit enable=1, Macro0, CA PI delay=33
803 19:22:23.726335
804 19:22:23.726443 [CBTSetCACLKResult] CA Dly = 33
805 19:22:23.729920 CS Dly: 6 (0~38)
806 19:22:23.730026
807 19:22:23.733027 ----->DramcWriteLeveling(PI) begin...
808 19:22:23.733139 ==
809 19:22:23.736622 Dram Type= 6, Freq= 0, CH_0, rank 0
810 19:22:23.740467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 19:22:23.740595 ==
812 19:22:23.744094 Write leveling (Byte 0): 30 => 30
813 19:22:23.747724 Write leveling (Byte 1): 27 => 27
814 19:22:23.747835 DramcWriteLeveling(PI) end<-----
815 19:22:23.747958
816 19:22:23.751290 ==
817 19:22:23.751399 Dram Type= 6, Freq= 0, CH_0, rank 0
818 19:22:23.758810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
819 19:22:23.758929 ==
820 19:22:23.759024 [Gating] SW mode calibration
821 19:22:23.765914 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
822 19:22:23.773681 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
823 19:22:23.777483 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
824 19:22:23.780537 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
825 19:22:23.784136 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
826 19:22:23.787876 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 19:22:23.795278 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 19:22:23.799208 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 19:22:23.802726 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 19:22:23.806304 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 19:22:23.810457 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 19:22:23.817313 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 19:22:23.821039 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 19:22:23.824699 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
835 19:22:23.828377 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
836 19:22:23.835370 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 19:22:23.839193 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 19:22:23.842816 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 19:22:23.846592 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
840 19:22:23.850818 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
841 19:22:23.854439 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
842 19:22:23.861775 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 19:22:23.865332 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 19:22:23.868773 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 19:22:23.872606 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 19:22:23.876412 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 19:22:23.883344 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 19:22:23.887096 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
849 19:22:23.890240 0 9 8 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
850 19:22:23.893824 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
851 19:22:23.900039 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
852 19:22:23.903617 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
853 19:22:23.906989 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
854 19:22:23.913665 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
855 19:22:23.917014 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
856 19:22:23.919849 0 10 4 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
857 19:22:23.926759 0 10 8 | B1->B0 | 3232 2424 | 0 0 | (0 0) (0 0)
858 19:22:23.929807 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 19:22:23.933439 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 19:22:23.939710 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 19:22:23.943230 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 19:22:23.946577 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 19:22:23.953119 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 19:22:23.956576 0 11 4 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
865 19:22:23.959782 0 11 8 | B1->B0 | 2626 4242 | 0 0 | (0 0) (0 0)
866 19:22:23.966538 0 11 12 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
867 19:22:23.970259 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 19:22:23.973241 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 19:22:23.980211 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
870 19:22:23.983001 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
871 19:22:23.986648 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
872 19:22:23.993399 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
873 19:22:23.996866 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
874 19:22:23.999800 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 19:22:24.006456 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 19:22:24.009967 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 19:22:24.013045 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 19:22:24.016599 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 19:22:24.022794 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 19:22:24.026744 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 19:22:24.029754 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 19:22:24.036539 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 19:22:24.039538 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 19:22:24.043117 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 19:22:24.049825 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
886 19:22:24.052931 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
887 19:22:24.055872 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
888 19:22:24.062732 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
889 19:22:24.065988 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
890 19:22:24.069418 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
891 19:22:24.073072 Total UI for P1: 0, mck2ui 16
892 19:22:24.076091 best dqsien dly found for B0: ( 0, 14, 8)
893 19:22:24.079147 Total UI for P1: 0, mck2ui 16
894 19:22:24.082799 best dqsien dly found for B1: ( 0, 14, 10)
895 19:22:24.085702 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
896 19:22:24.092791 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
897 19:22:24.092939
898 19:22:24.095788 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
899 19:22:24.099458 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
900 19:22:24.102859 [Gating] SW calibration Done
901 19:22:24.102974 ==
902 19:22:24.106194 Dram Type= 6, Freq= 0, CH_0, rank 0
903 19:22:24.109595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
904 19:22:24.109708 ==
905 19:22:24.109804 RX Vref Scan: 0
906 19:22:24.109898
907 19:22:24.112571 RX Vref 0 -> 0, step: 1
908 19:22:24.112707
909 19:22:24.115962 RX Delay -130 -> 252, step: 16
910 19:22:24.119062 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
911 19:22:24.122755 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
912 19:22:24.129159 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
913 19:22:24.132410 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
914 19:22:24.135783 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
915 19:22:24.138827 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
916 19:22:24.142569 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
917 19:22:24.149291 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
918 19:22:24.152835 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
919 19:22:24.156605 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
920 19:22:24.159588 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
921 19:22:24.163785 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
922 19:22:24.167288 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
923 19:22:24.171458 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
924 19:22:24.174579 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
925 19:22:24.182122 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
926 19:22:24.182263 ==
927 19:22:24.182379 Dram Type= 6, Freq= 0, CH_0, rank 0
928 19:22:24.188933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
929 19:22:24.189073 ==
930 19:22:24.189173 DQS Delay:
931 19:22:24.192512 DQS0 = 0, DQS1 = 0
932 19:22:24.192735 DQM Delay:
933 19:22:24.192867 DQM0 = 91, DQM1 = 75
934 19:22:24.195196 DQ Delay:
935 19:22:24.198866 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =93
936 19:22:24.201995 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
937 19:22:24.205620 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69
938 19:22:24.208484 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
939 19:22:24.208612
940 19:22:24.208710
941 19:22:24.208812 ==
942 19:22:24.212068 Dram Type= 6, Freq= 0, CH_0, rank 0
943 19:22:24.215358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
944 19:22:24.215474 ==
945 19:22:24.215570
946 19:22:24.215671
947 19:22:24.218659 TX Vref Scan disable
948 19:22:24.222140 == TX Byte 0 ==
949 19:22:24.225108 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
950 19:22:24.228247 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
951 19:22:24.231813 == TX Byte 1 ==
952 19:22:24.235415 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
953 19:22:24.238393 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
954 19:22:24.238482 ==
955 19:22:24.241795 Dram Type= 6, Freq= 0, CH_0, rank 0
956 19:22:24.248343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
957 19:22:24.248434 ==
958 19:22:24.259739 TX Vref=22, minBit 0, minWin=27, winSum=439
959 19:22:24.262761 TX Vref=24, minBit 7, minWin=26, winSum=438
960 19:22:24.266376 TX Vref=26, minBit 0, minWin=27, winSum=443
961 19:22:24.269402 TX Vref=28, minBit 1, minWin=27, winSum=449
962 19:22:24.273053 TX Vref=30, minBit 1, minWin=27, winSum=444
963 19:22:24.279387 TX Vref=32, minBit 2, minWin=27, winSum=446
964 19:22:24.282796 [TxChooseVref] Worse bit 1, Min win 27, Win sum 449, Final Vref 28
965 19:22:24.282918
966 19:22:24.286253 Final TX Range 1 Vref 28
967 19:22:24.286362
968 19:22:24.286460 ==
969 19:22:24.289893 Dram Type= 6, Freq= 0, CH_0, rank 0
970 19:22:24.292939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
971 19:22:24.293036 ==
972 19:22:24.295952
973 19:22:24.296040
974 19:22:24.296128 TX Vref Scan disable
975 19:22:24.299924 == TX Byte 0 ==
976 19:22:24.303057 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
977 19:22:24.306060 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
978 19:22:24.309688 == TX Byte 1 ==
979 19:22:24.312758 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
980 19:22:24.319332 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
981 19:22:24.319450
982 19:22:24.319556 [DATLAT]
983 19:22:24.319650 Freq=800, CH0 RK0
984 19:22:24.319755
985 19:22:24.322839 DATLAT Default: 0xa
986 19:22:24.322964 0, 0xFFFF, sum = 0
987 19:22:24.326132 1, 0xFFFF, sum = 0
988 19:22:24.326252 2, 0xFFFF, sum = 0
989 19:22:24.329465 3, 0xFFFF, sum = 0
990 19:22:24.333046 4, 0xFFFF, sum = 0
991 19:22:24.333127 5, 0xFFFF, sum = 0
992 19:22:24.336635 6, 0xFFFF, sum = 0
993 19:22:24.336716 7, 0xFFFF, sum = 0
994 19:22:24.336784 8, 0xFFFF, sum = 0
995 19:22:24.340277 9, 0x0, sum = 1
996 19:22:24.340352 10, 0x0, sum = 2
997 19:22:24.343971 11, 0x0, sum = 3
998 19:22:24.344043 12, 0x0, sum = 4
999 19:22:24.347321 best_step = 10
1000 19:22:24.347391
1001 19:22:24.347451 ==
1002 19:22:24.350661 Dram Type= 6, Freq= 0, CH_0, rank 0
1003 19:22:24.353705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1004 19:22:24.353818 ==
1005 19:22:24.353924 RX Vref Scan: 1
1006 19:22:24.356853
1007 19:22:24.356923 Set Vref Range= 32 -> 127
1008 19:22:24.356982
1009 19:22:24.360478 RX Vref 32 -> 127, step: 1
1010 19:22:24.360590
1011 19:22:24.363539 RX Delay -111 -> 252, step: 8
1012 19:22:24.363638
1013 19:22:24.367158 Set Vref, RX VrefLevel [Byte0]: 32
1014 19:22:24.370208 [Byte1]: 32
1015 19:22:24.370308
1016 19:22:24.373775 Set Vref, RX VrefLevel [Byte0]: 33
1017 19:22:24.376690 [Byte1]: 33
1018 19:22:24.380286
1019 19:22:24.380369 Set Vref, RX VrefLevel [Byte0]: 34
1020 19:22:24.383782 [Byte1]: 34
1021 19:22:24.387826
1022 19:22:24.387960 Set Vref, RX VrefLevel [Byte0]: 35
1023 19:22:24.391261 [Byte1]: 35
1024 19:22:24.395370
1025 19:22:24.395481 Set Vref, RX VrefLevel [Byte0]: 36
1026 19:22:24.398499 [Byte1]: 36
1027 19:22:24.403248
1028 19:22:24.406100 Set Vref, RX VrefLevel [Byte0]: 37
1029 19:22:24.409252 [Byte1]: 37
1030 19:22:24.409338
1031 19:22:24.413007 Set Vref, RX VrefLevel [Byte0]: 38
1032 19:22:24.416123 [Byte1]: 38
1033 19:22:24.416204
1034 19:22:24.419597 Set Vref, RX VrefLevel [Byte0]: 39
1035 19:22:24.422673 [Byte1]: 39
1036 19:22:24.426536
1037 19:22:24.426621 Set Vref, RX VrefLevel [Byte0]: 40
1038 19:22:24.429585 [Byte1]: 40
1039 19:22:24.433550
1040 19:22:24.433642 Set Vref, RX VrefLevel [Byte0]: 41
1041 19:22:24.436958 [Byte1]: 41
1042 19:22:24.441497
1043 19:22:24.441582 Set Vref, RX VrefLevel [Byte0]: 42
1044 19:22:24.445009 [Byte1]: 42
1045 19:22:24.449267
1046 19:22:24.449350 Set Vref, RX VrefLevel [Byte0]: 43
1047 19:22:24.452340 [Byte1]: 43
1048 19:22:24.456425
1049 19:22:24.456507 Set Vref, RX VrefLevel [Byte0]: 44
1050 19:22:24.459748 [Byte1]: 44
1051 19:22:24.464108
1052 19:22:24.464192 Set Vref, RX VrefLevel [Byte0]: 45
1053 19:22:24.467716 [Byte1]: 45
1054 19:22:24.472133
1055 19:22:24.472216 Set Vref, RX VrefLevel [Byte0]: 46
1056 19:22:24.475155 [Byte1]: 46
1057 19:22:24.479404
1058 19:22:24.479484 Set Vref, RX VrefLevel [Byte0]: 47
1059 19:22:24.482863 [Byte1]: 47
1060 19:22:24.487275
1061 19:22:24.487355 Set Vref, RX VrefLevel [Byte0]: 48
1062 19:22:24.490747 [Byte1]: 48
1063 19:22:24.494658
1064 19:22:24.494757 Set Vref, RX VrefLevel [Byte0]: 49
1065 19:22:24.498259 [Byte1]: 49
1066 19:22:24.502730
1067 19:22:24.502857 Set Vref, RX VrefLevel [Byte0]: 50
1068 19:22:24.505759 [Byte1]: 50
1069 19:22:24.509792
1070 19:22:24.509918 Set Vref, RX VrefLevel [Byte0]: 51
1071 19:22:24.513399 [Byte1]: 51
1072 19:22:24.518011
1073 19:22:24.518134 Set Vref, RX VrefLevel [Byte0]: 52
1074 19:22:24.521047 [Byte1]: 52
1075 19:22:24.525147
1076 19:22:24.525272 Set Vref, RX VrefLevel [Byte0]: 53
1077 19:22:24.528995 [Byte1]: 53
1078 19:22:24.533191
1079 19:22:24.533297 Set Vref, RX VrefLevel [Byte0]: 54
1080 19:22:24.536070 [Byte1]: 54
1081 19:22:24.540996
1082 19:22:24.541106 Set Vref, RX VrefLevel [Byte0]: 55
1083 19:22:24.543811 [Byte1]: 55
1084 19:22:24.548362
1085 19:22:24.548470 Set Vref, RX VrefLevel [Byte0]: 56
1086 19:22:24.551796 [Byte1]: 56
1087 19:22:24.555991
1088 19:22:24.556077 Set Vref, RX VrefLevel [Byte0]: 57
1089 19:22:24.559622 [Byte1]: 57
1090 19:22:24.563724
1091 19:22:24.563844 Set Vref, RX VrefLevel [Byte0]: 58
1092 19:22:24.567048 [Byte1]: 58
1093 19:22:24.571165
1094 19:22:24.571289 Set Vref, RX VrefLevel [Byte0]: 59
1095 19:22:24.574801 [Byte1]: 59
1096 19:22:24.578830
1097 19:22:24.578940 Set Vref, RX VrefLevel [Byte0]: 60
1098 19:22:24.581963 [Byte1]: 60
1099 19:22:24.586673
1100 19:22:24.586783 Set Vref, RX VrefLevel [Byte0]: 61
1101 19:22:24.589654 [Byte1]: 61
1102 19:22:24.594172
1103 19:22:24.594310 Set Vref, RX VrefLevel [Byte0]: 62
1104 19:22:24.597428 [Byte1]: 62
1105 19:22:24.601713
1106 19:22:24.601832 Set Vref, RX VrefLevel [Byte0]: 63
1107 19:22:24.605262 [Byte1]: 63
1108 19:22:24.609445
1109 19:22:24.609564 Set Vref, RX VrefLevel [Byte0]: 64
1110 19:22:24.612468 [Byte1]: 64
1111 19:22:24.617132
1112 19:22:24.617245 Set Vref, RX VrefLevel [Byte0]: 65
1113 19:22:24.620740 [Byte1]: 65
1114 19:22:24.624931
1115 19:22:24.625040 Set Vref, RX VrefLevel [Byte0]: 66
1116 19:22:24.627834 [Byte1]: 66
1117 19:22:24.632753
1118 19:22:24.632862 Set Vref, RX VrefLevel [Byte0]: 67
1119 19:22:24.635779 [Byte1]: 67
1120 19:22:24.639837
1121 19:22:24.639937 Set Vref, RX VrefLevel [Byte0]: 68
1122 19:22:24.643531 [Byte1]: 68
1123 19:22:24.647773
1124 19:22:24.647893 Set Vref, RX VrefLevel [Byte0]: 69
1125 19:22:24.650850 [Byte1]: 69
1126 19:22:24.655477
1127 19:22:24.655582 Set Vref, RX VrefLevel [Byte0]: 70
1128 19:22:24.658772 [Byte1]: 70
1129 19:22:24.662783
1130 19:22:24.662886 Set Vref, RX VrefLevel [Byte0]: 71
1131 19:22:24.666440 [Byte1]: 71
1132 19:22:24.670644
1133 19:22:24.670756 Set Vref, RX VrefLevel [Byte0]: 72
1134 19:22:24.674228 [Byte1]: 72
1135 19:22:24.678114
1136 19:22:24.678198 Set Vref, RX VrefLevel [Byte0]: 73
1137 19:22:24.681653 [Byte1]: 73
1138 19:22:24.686051
1139 19:22:24.686181 Set Vref, RX VrefLevel [Byte0]: 74
1140 19:22:24.689547 [Byte1]: 74
1141 19:22:24.693819
1142 19:22:24.693938 Final RX Vref Byte 0 = 54 to rank0
1143 19:22:24.696832 Final RX Vref Byte 1 = 58 to rank0
1144 19:22:24.700355 Final RX Vref Byte 0 = 54 to rank1
1145 19:22:24.703875 Final RX Vref Byte 1 = 58 to rank1==
1146 19:22:24.706862 Dram Type= 6, Freq= 0, CH_0, rank 0
1147 19:22:24.713815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1148 19:22:24.713945 ==
1149 19:22:24.714042 DQS Delay:
1150 19:22:24.714134 DQS0 = 0, DQS1 = 0
1151 19:22:24.716952 DQM Delay:
1152 19:22:24.717038 DQM0 = 88, DQM1 = 76
1153 19:22:24.720452 DQ Delay:
1154 19:22:24.723248 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =88
1155 19:22:24.726901 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1156 19:22:24.730457 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =72
1157 19:22:24.730549 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =84
1158 19:22:24.730653
1159 19:22:24.730755
1160 19:22:24.742017 [DQSOSCAuto] RK0, (LSB)MR18= 0x332c, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
1161 19:22:24.742157 CH0 RK0: MR19=606, MR18=332C
1162 19:22:24.748887 CH0_RK0: MR19=0x606, MR18=0x332C, DQSOSC=396, MR23=63, INC=94, DEC=62
1163 19:22:24.748994
1164 19:22:24.751998 ----->DramcWriteLeveling(PI) begin...
1165 19:22:24.752085 ==
1166 19:22:24.755701 Dram Type= 6, Freq= 0, CH_0, rank 1
1167 19:22:24.759392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1168 19:22:24.759542 ==
1169 19:22:24.762936 Write leveling (Byte 0): 28 => 28
1170 19:22:24.766272 Write leveling (Byte 1): 28 => 28
1171 19:22:24.769591 DramcWriteLeveling(PI) end<-----
1172 19:22:24.769678
1173 19:22:24.769779 ==
1174 19:22:24.772690 Dram Type= 6, Freq= 0, CH_0, rank 1
1175 19:22:24.775807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1176 19:22:24.779585 ==
1177 19:22:24.779671 [Gating] SW mode calibration
1178 19:22:24.789421 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1179 19:22:24.792389 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1180 19:22:24.795934 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1181 19:22:24.802321 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1182 19:22:24.805833 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 19:22:24.808955 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 19:22:24.815493 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 19:22:24.818864 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 19:22:24.822290 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 19:22:24.828964 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 19:22:24.832487 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 19:22:24.835433 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 19:22:24.842203 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 19:22:24.845737 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 19:22:24.848661 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 19:22:24.855490 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 19:22:24.858686 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 19:22:24.861767 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 19:22:24.868633 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 19:22:24.872072 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1198 19:22:24.875449 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 19:22:24.881898 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 19:22:24.885495 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 19:22:24.888518 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 19:22:24.891994 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 19:22:24.898778 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 19:22:24.901932 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 19:22:24.905526 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1206 19:22:24.912154 0 9 8 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
1207 19:22:24.915215 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1208 19:22:24.918381 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1209 19:22:24.925044 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1210 19:22:24.928519 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1211 19:22:24.931765 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1212 19:22:24.938156 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1213 19:22:24.941731 0 10 4 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
1214 19:22:24.944710 0 10 8 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
1215 19:22:24.951776 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 19:22:24.954909 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 19:22:24.958648 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 19:22:24.965211 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 19:22:24.968346 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 19:22:24.971458 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 19:22:24.978102 0 11 4 | B1->B0 | 2323 3333 | 0 1 | (0 0) (0 0)
1222 19:22:24.981608 0 11 8 | B1->B0 | 2e2e 4646 | 0 0 | (0 0) (0 0)
1223 19:22:24.985025 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1224 19:22:24.991767 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1225 19:22:24.994692 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1226 19:22:24.998550 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1227 19:22:25.004767 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1228 19:22:25.007994 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1229 19:22:25.011653 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1230 19:22:25.018297 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1231 19:22:25.021396 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1232 19:22:25.024376 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1233 19:22:25.031184 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1234 19:22:25.034782 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1235 19:22:25.037645 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1236 19:22:25.044723 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1237 19:22:25.048183 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1238 19:22:25.051233 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1239 19:22:25.057821 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1240 19:22:25.061036 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1241 19:22:25.064118 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1242 19:22:25.070937 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1243 19:22:25.073994 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1244 19:22:25.077676 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1245 19:22:25.084495 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1246 19:22:25.087470 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1247 19:22:25.090762 Total UI for P1: 0, mck2ui 16
1248 19:22:25.093707 best dqsien dly found for B0: ( 0, 14, 4)
1249 19:22:25.097353 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1250 19:22:25.100954 Total UI for P1: 0, mck2ui 16
1251 19:22:25.103974 best dqsien dly found for B1: ( 0, 14, 8)
1252 19:22:25.107041 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1253 19:22:25.110543 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1254 19:22:25.110627
1255 19:22:25.114011 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1256 19:22:25.117599 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1257 19:22:25.120551 [Gating] SW calibration Done
1258 19:22:25.120640 ==
1259 19:22:25.123700 Dram Type= 6, Freq= 0, CH_0, rank 1
1260 19:22:25.130606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1261 19:22:25.130698 ==
1262 19:22:25.130787 RX Vref Scan: 0
1263 19:22:25.130866
1264 19:22:25.133696 RX Vref 0 -> 0, step: 1
1265 19:22:25.133804
1266 19:22:25.137309 RX Delay -130 -> 252, step: 16
1267 19:22:25.140428 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1268 19:22:25.143994 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1269 19:22:25.146870 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1270 19:22:25.153769 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1271 19:22:25.157209 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1272 19:22:25.160600 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1273 19:22:25.163962 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1274 19:22:25.167024 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1275 19:22:25.170735 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1276 19:22:25.176880 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1277 19:22:25.180692 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1278 19:22:25.183696 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1279 19:22:25.186902 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1280 19:22:25.193467 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1281 19:22:25.197048 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1282 19:22:25.200252 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1283 19:22:25.200355 ==
1284 19:22:25.203314 Dram Type= 6, Freq= 0, CH_0, rank 1
1285 19:22:25.207084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1286 19:22:25.207169 ==
1287 19:22:25.209956 DQS Delay:
1288 19:22:25.210045 DQS0 = 0, DQS1 = 0
1289 19:22:25.213617 DQM Delay:
1290 19:22:25.213720 DQM0 = 85, DQM1 = 77
1291 19:22:25.213819 DQ Delay:
1292 19:22:25.216502 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1293 19:22:25.219792 DQ4 =85, DQ5 =77, DQ6 =93, DQ7 =93
1294 19:22:25.223165 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1295 19:22:25.226561 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1296 19:22:25.226647
1297 19:22:25.226733
1298 19:22:25.230247 ==
1299 19:22:25.233328 Dram Type= 6, Freq= 0, CH_0, rank 1
1300 19:22:25.236868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1301 19:22:25.236975 ==
1302 19:22:25.237114
1303 19:22:25.237234
1304 19:22:25.239843 TX Vref Scan disable
1305 19:22:25.239971 == TX Byte 0 ==
1306 19:22:25.242845 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1307 19:22:25.249770 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1308 19:22:25.249872 == TX Byte 1 ==
1309 19:22:25.253415 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1310 19:22:25.259952 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1311 19:22:25.260055 ==
1312 19:22:25.262886 Dram Type= 6, Freq= 0, CH_0, rank 1
1313 19:22:25.266498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1314 19:22:25.266588 ==
1315 19:22:25.279586 TX Vref=22, minBit 0, minWin=27, winSum=441
1316 19:22:25.283217 TX Vref=24, minBit 2, minWin=27, winSum=447
1317 19:22:25.286234 TX Vref=26, minBit 3, minWin=27, winSum=451
1318 19:22:25.289311 TX Vref=28, minBit 6, minWin=27, winSum=453
1319 19:22:25.293098 TX Vref=30, minBit 3, minWin=27, winSum=454
1320 19:22:25.299219 TX Vref=32, minBit 6, minWin=27, winSum=453
1321 19:22:25.302797 [TxChooseVref] Worse bit 3, Min win 27, Win sum 454, Final Vref 30
1322 19:22:25.302900
1323 19:22:25.306376 Final TX Range 1 Vref 30
1324 19:22:25.306464
1325 19:22:25.306567 ==
1326 19:22:25.309591 Dram Type= 6, Freq= 0, CH_0, rank 1
1327 19:22:25.312988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1328 19:22:25.313099 ==
1329 19:22:25.316048
1330 19:22:25.316131
1331 19:22:25.316194 TX Vref Scan disable
1332 19:22:25.319682 == TX Byte 0 ==
1333 19:22:25.322667 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1334 19:22:25.329473 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1335 19:22:25.329566 == TX Byte 1 ==
1336 19:22:25.332767 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1337 19:22:25.339632 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1338 19:22:25.339721
1339 19:22:25.339784 [DATLAT]
1340 19:22:25.339844 Freq=800, CH0 RK1
1341 19:22:25.339932
1342 19:22:25.342513 DATLAT Default: 0xa
1343 19:22:25.342582 0, 0xFFFF, sum = 0
1344 19:22:25.345631 1, 0xFFFF, sum = 0
1345 19:22:25.349224 2, 0xFFFF, sum = 0
1346 19:22:25.349301 3, 0xFFFF, sum = 0
1347 19:22:25.352281 4, 0xFFFF, sum = 0
1348 19:22:25.352355 5, 0xFFFF, sum = 0
1349 19:22:25.356088 6, 0xFFFF, sum = 0
1350 19:22:25.356163 7, 0xFFFF, sum = 0
1351 19:22:25.358967 8, 0xFFFF, sum = 0
1352 19:22:25.359083 9, 0x0, sum = 1
1353 19:22:25.362640 10, 0x0, sum = 2
1354 19:22:25.362726 11, 0x0, sum = 3
1355 19:22:25.365484 12, 0x0, sum = 4
1356 19:22:25.365572 best_step = 10
1357 19:22:25.365635
1358 19:22:25.365695 ==
1359 19:22:25.368913 Dram Type= 6, Freq= 0, CH_0, rank 1
1360 19:22:25.372643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1361 19:22:25.372726 ==
1362 19:22:25.375648 RX Vref Scan: 0
1363 19:22:25.375729
1364 19:22:25.379180 RX Vref 0 -> 0, step: 1
1365 19:22:25.379267
1366 19:22:25.379332 RX Delay -95 -> 252, step: 8
1367 19:22:25.386424 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1368 19:22:25.389450 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1369 19:22:25.392549 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1370 19:22:25.396341 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1371 19:22:25.399953 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1372 19:22:25.404303 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1373 19:22:25.407524 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1374 19:22:25.411865 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1375 19:22:25.418800 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1376 19:22:25.422740 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1377 19:22:25.426498 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1378 19:22:25.430245 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1379 19:22:25.433303 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1380 19:22:25.436817 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1381 19:22:25.440081 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1382 19:22:25.443737 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1383 19:22:25.446793 ==
1384 19:22:25.446875 Dram Type= 6, Freq= 0, CH_0, rank 1
1385 19:22:25.453629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1386 19:22:25.453720 ==
1387 19:22:25.453786 DQS Delay:
1388 19:22:25.456678 DQS0 = 0, DQS1 = 0
1389 19:22:25.456758 DQM Delay:
1390 19:22:25.460372 DQM0 = 86, DQM1 = 76
1391 19:22:25.460453 DQ Delay:
1392 19:22:25.463440 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =80
1393 19:22:25.466905 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1394 19:22:25.469752 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =72
1395 19:22:25.473069 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1396 19:22:25.473155
1397 19:22:25.473220
1398 19:22:25.480085 [DQSOSCAuto] RK1, (LSB)MR18= 0x2926, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 399 ps
1399 19:22:25.483155 CH0 RK1: MR19=606, MR18=2926
1400 19:22:25.489918 CH0_RK1: MR19=0x606, MR18=0x2926, DQSOSC=399, MR23=63, INC=92, DEC=61
1401 19:22:25.493269 [RxdqsGatingPostProcess] freq 800
1402 19:22:25.499862 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1403 19:22:25.500007 Pre-setting of DQS Precalculation
1404 19:22:25.506014 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1405 19:22:25.506102 ==
1406 19:22:25.509799 Dram Type= 6, Freq= 0, CH_1, rank 0
1407 19:22:25.512870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1408 19:22:25.512955 ==
1409 19:22:25.519634 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1410 19:22:25.526347 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1411 19:22:25.534363 [CA 0] Center 36 (6~67) winsize 62
1412 19:22:25.538100 [CA 1] Center 37 (6~68) winsize 63
1413 19:22:25.540870 [CA 2] Center 35 (5~65) winsize 61
1414 19:22:25.544459 [CA 3] Center 34 (4~65) winsize 62
1415 19:22:25.547896 [CA 4] Center 34 (4~65) winsize 62
1416 19:22:25.550745 [CA 5] Center 34 (3~65) winsize 63
1417 19:22:25.550827
1418 19:22:25.554105 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1419 19:22:25.554188
1420 19:22:25.557459 [CATrainingPosCal] consider 1 rank data
1421 19:22:25.561040 u2DelayCellTimex100 = 270/100 ps
1422 19:22:25.564005 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1423 19:22:25.570959 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1424 19:22:25.574018 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1425 19:22:25.577585 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1426 19:22:25.581014 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1427 19:22:25.584198 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1428 19:22:25.584291
1429 19:22:25.587363 CA PerBit enable=1, Macro0, CA PI delay=34
1430 19:22:25.587529
1431 19:22:25.591138 [CBTSetCACLKResult] CA Dly = 34
1432 19:22:25.591224 CS Dly: 4 (0~35)
1433 19:22:25.594205 ==
1434 19:22:25.597760 Dram Type= 6, Freq= 0, CH_1, rank 1
1435 19:22:25.600743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1436 19:22:25.600831 ==
1437 19:22:25.603894 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1438 19:22:25.610646 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1439 19:22:25.620860 [CA 0] Center 37 (6~68) winsize 63
1440 19:22:25.623823 [CA 1] Center 36 (6~67) winsize 62
1441 19:22:25.627432 [CA 2] Center 34 (4~65) winsize 62
1442 19:22:25.630488 [CA 3] Center 34 (4~64) winsize 61
1443 19:22:25.634250 [CA 4] Center 34 (3~65) winsize 63
1444 19:22:25.637356 [CA 5] Center 34 (3~65) winsize 63
1445 19:22:25.637442
1446 19:22:25.640369 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1447 19:22:25.640452
1448 19:22:25.643802 [CATrainingPosCal] consider 2 rank data
1449 19:22:25.647264 u2DelayCellTimex100 = 270/100 ps
1450 19:22:25.650522 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1451 19:22:25.657195 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1452 19:22:25.660109 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1453 19:22:25.663483 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1454 19:22:25.667009 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1455 19:22:25.670434 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1456 19:22:25.670529
1457 19:22:25.673551 CA PerBit enable=1, Macro0, CA PI delay=34
1458 19:22:25.673637
1459 19:22:25.677328 [CBTSetCACLKResult] CA Dly = 34
1460 19:22:25.677416 CS Dly: 5 (0~37)
1461 19:22:25.680465
1462 19:22:25.683453 ----->DramcWriteLeveling(PI) begin...
1463 19:22:25.683540 ==
1464 19:22:25.687071 Dram Type= 6, Freq= 0, CH_1, rank 0
1465 19:22:25.690007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1466 19:22:25.690096 ==
1467 19:22:25.693389 Write leveling (Byte 0): 25 => 25
1468 19:22:25.696828 Write leveling (Byte 1): 29 => 29
1469 19:22:25.699763 DramcWriteLeveling(PI) end<-----
1470 19:22:25.699853
1471 19:22:25.699963 ==
1472 19:22:25.702954 Dram Type= 6, Freq= 0, CH_1, rank 0
1473 19:22:25.706534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1474 19:22:25.706620 ==
1475 19:22:25.710152 [Gating] SW mode calibration
1476 19:22:25.716402 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1477 19:22:25.723234 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1478 19:22:25.726192 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1479 19:22:25.729823 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1480 19:22:25.736131 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 19:22:25.739728 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 19:22:25.742777 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 19:22:25.749632 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 19:22:25.753129 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 19:22:25.756058 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 19:22:25.762919 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 19:22:25.766260 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 19:22:25.769554 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 19:22:25.775843 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 19:22:25.779317 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 19:22:25.782490 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 19:22:25.789275 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 19:22:25.792836 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 19:22:25.795855 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1495 19:22:25.802823 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1496 19:22:25.805723 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1497 19:22:25.809145 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 19:22:25.815669 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 19:22:25.819408 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 19:22:25.822451 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 19:22:25.829244 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 19:22:25.832170 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 19:22:25.835830 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 19:22:25.842556 0 9 8 | B1->B0 | 3333 3434 | 1 0 | (1 1) (0 0)
1505 19:22:25.845676 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1506 19:22:25.848662 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1507 19:22:25.852252 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1508 19:22:25.858803 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1509 19:22:25.870113 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1510 19:22:25.870237 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1511 19:22:25.872152 0 10 4 | B1->B0 | 3232 3030 | 0 0 | (1 0) (1 0)
1512 19:22:25.875343 0 10 8 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
1513 19:22:25.878703 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 19:22:25.885229 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 19:22:25.888516 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 19:22:25.892017 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 19:22:25.898439 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 19:22:25.901991 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 19:22:25.905503 0 11 4 | B1->B0 | 2525 2d2d | 0 0 | (0 0) (0 0)
1520 19:22:25.911807 0 11 8 | B1->B0 | 3d3d 4545 | 0 0 | (0 0) (0 0)
1521 19:22:25.915295 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1522 19:22:25.918414 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1523 19:22:25.925126 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1524 19:22:25.928686 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1525 19:22:25.931762 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1526 19:22:25.938224 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1527 19:22:25.941744 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1528 19:22:25.945138 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1529 19:22:25.951911 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1530 19:22:25.955075 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1531 19:22:25.958672 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1532 19:22:25.964840 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1533 19:22:25.968298 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1534 19:22:25.971811 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1535 19:22:25.978731 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1536 19:22:25.982199 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1537 19:22:25.985155 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1538 19:22:25.988525 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1539 19:22:25.995504 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1540 19:22:25.998805 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1541 19:22:26.002163 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1542 19:22:26.008284 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1543 19:22:26.011812 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1544 19:22:26.015243 Total UI for P1: 0, mck2ui 16
1545 19:22:26.018297 best dqsien dly found for B0: ( 0, 14, 0)
1546 19:22:26.021755 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1547 19:22:26.024950 Total UI for P1: 0, mck2ui 16
1548 19:22:26.028343 best dqsien dly found for B1: ( 0, 14, 4)
1549 19:22:26.031817 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1550 19:22:26.034745 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1551 19:22:26.034835
1552 19:22:26.041619 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1553 19:22:26.044565 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1554 19:22:26.044659 [Gating] SW calibration Done
1555 19:22:26.048115 ==
1556 19:22:26.051060 Dram Type= 6, Freq= 0, CH_1, rank 0
1557 19:22:26.054575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1558 19:22:26.054660 ==
1559 19:22:26.054724 RX Vref Scan: 0
1560 19:22:26.054784
1561 19:22:26.058228 RX Vref 0 -> 0, step: 1
1562 19:22:26.058300
1563 19:22:26.061195 RX Delay -130 -> 252, step: 16
1564 19:22:26.064755 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1565 19:22:26.067791 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1566 19:22:26.074326 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1567 19:22:26.077921 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1568 19:22:26.080816 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1569 19:22:26.084163 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1570 19:22:26.087687 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1571 19:22:26.094389 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1572 19:22:26.097871 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1573 19:22:26.100793 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1574 19:22:26.104359 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1575 19:22:26.107609 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1576 19:22:26.114281 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1577 19:22:26.117547 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1578 19:22:26.120698 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1579 19:22:26.124204 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1580 19:22:26.127231 ==
1581 19:22:26.127344 Dram Type= 6, Freq= 0, CH_1, rank 0
1582 19:22:26.134156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1583 19:22:26.134292 ==
1584 19:22:26.134386 DQS Delay:
1585 19:22:26.137495 DQS0 = 0, DQS1 = 0
1586 19:22:26.137606 DQM Delay:
1587 19:22:26.140773 DQM0 = 88, DQM1 = 80
1588 19:22:26.140884 DQ Delay:
1589 19:22:26.144059 DQ0 =93, DQ1 =85, DQ2 =69, DQ3 =85
1590 19:22:26.146979 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1591 19:22:26.150495 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1592 19:22:26.153952 DQ12 =93, DQ13 =85, DQ14 =85, DQ15 =85
1593 19:22:26.154038
1594 19:22:26.154102
1595 19:22:26.154160 ==
1596 19:22:26.156888 Dram Type= 6, Freq= 0, CH_1, rank 0
1597 19:22:26.160537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1598 19:22:26.160615 ==
1599 19:22:26.160677
1600 19:22:26.160734
1601 19:22:26.163572 TX Vref Scan disable
1602 19:22:26.166962 == TX Byte 0 ==
1603 19:22:26.170652 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1604 19:22:26.173533 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1605 19:22:26.177032 == TX Byte 1 ==
1606 19:22:26.179867 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1607 19:22:26.183685 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1608 19:22:26.183813 ==
1609 19:22:26.186594 Dram Type= 6, Freq= 0, CH_1, rank 0
1610 19:22:26.193177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1611 19:22:26.193349 ==
1612 19:22:26.205305 TX Vref=22, minBit 1, minWin=27, winSum=442
1613 19:22:26.208952 TX Vref=24, minBit 2, minWin=27, winSum=445
1614 19:22:26.211778 TX Vref=26, minBit 4, minWin=27, winSum=451
1615 19:22:26.215373 TX Vref=28, minBit 2, minWin=27, winSum=455
1616 19:22:26.218873 TX Vref=30, minBit 5, minWin=27, winSum=455
1617 19:22:26.225070 TX Vref=32, minBit 0, minWin=27, winSum=454
1618 19:22:26.228614 [TxChooseVref] Worse bit 2, Min win 27, Win sum 455, Final Vref 28
1619 19:22:26.228711
1620 19:22:26.232112 Final TX Range 1 Vref 28
1621 19:22:26.232199
1622 19:22:26.232291 ==
1623 19:22:26.235257 Dram Type= 6, Freq= 0, CH_1, rank 0
1624 19:22:26.238337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1625 19:22:26.241783 ==
1626 19:22:26.241901
1627 19:22:26.241980
1628 19:22:26.242040 TX Vref Scan disable
1629 19:22:26.245674 == TX Byte 0 ==
1630 19:22:26.248718 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1631 19:22:26.255318 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1632 19:22:26.255416 == TX Byte 1 ==
1633 19:22:26.258986 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1634 19:22:26.265405 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1635 19:22:26.265504
1636 19:22:26.265570 [DATLAT]
1637 19:22:26.265631 Freq=800, CH1 RK0
1638 19:22:26.265691
1639 19:22:26.268965 DATLAT Default: 0xa
1640 19:22:26.269049 0, 0xFFFF, sum = 0
1641 19:22:26.271863 1, 0xFFFF, sum = 0
1642 19:22:26.271959 2, 0xFFFF, sum = 0
1643 19:22:26.275516 3, 0xFFFF, sum = 0
1644 19:22:26.278455 4, 0xFFFF, sum = 0
1645 19:22:26.278542 5, 0xFFFF, sum = 0
1646 19:22:26.281919 6, 0xFFFF, sum = 0
1647 19:22:26.282000 7, 0xFFFF, sum = 0
1648 19:22:26.285403 8, 0xFFFF, sum = 0
1649 19:22:26.285488 9, 0x0, sum = 1
1650 19:22:26.288381 10, 0x0, sum = 2
1651 19:22:26.288465 11, 0x0, sum = 3
1652 19:22:26.288532 12, 0x0, sum = 4
1653 19:22:26.292087 best_step = 10
1654 19:22:26.292171
1655 19:22:26.292236 ==
1656 19:22:26.295060 Dram Type= 6, Freq= 0, CH_1, rank 0
1657 19:22:26.298422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1658 19:22:26.298512 ==
1659 19:22:26.301943 RX Vref Scan: 1
1660 19:22:26.302028
1661 19:22:26.305120 Set Vref Range= 32 -> 127
1662 19:22:26.305206
1663 19:22:26.305272 RX Vref 32 -> 127, step: 1
1664 19:22:26.305335
1665 19:22:26.308520 RX Delay -95 -> 252, step: 8
1666 19:22:26.308605
1667 19:22:26.311518 Set Vref, RX VrefLevel [Byte0]: 32
1668 19:22:26.314596 [Byte1]: 32
1669 19:22:26.318186
1670 19:22:26.318274 Set Vref, RX VrefLevel [Byte0]: 33
1671 19:22:26.321696 [Byte1]: 33
1672 19:22:26.325915
1673 19:22:26.326002 Set Vref, RX VrefLevel [Byte0]: 34
1674 19:22:26.328946 [Byte1]: 34
1675 19:22:26.333469
1676 19:22:26.333556 Set Vref, RX VrefLevel [Byte0]: 35
1677 19:22:26.336488 [Byte1]: 35
1678 19:22:26.340707
1679 19:22:26.340831 Set Vref, RX VrefLevel [Byte0]: 36
1680 19:22:26.344075 [Byte1]: 36
1681 19:22:26.348727
1682 19:22:26.348852 Set Vref, RX VrefLevel [Byte0]: 37
1683 19:22:26.351721 [Byte1]: 37
1684 19:22:26.356260
1685 19:22:26.356356 Set Vref, RX VrefLevel [Byte0]: 38
1686 19:22:26.359527 [Byte1]: 38
1687 19:22:26.363484
1688 19:22:26.363598 Set Vref, RX VrefLevel [Byte0]: 39
1689 19:22:26.367239 [Byte1]: 39
1690 19:22:26.371084
1691 19:22:26.371253 Set Vref, RX VrefLevel [Byte0]: 40
1692 19:22:26.374417 [Byte1]: 40
1693 19:22:26.378759
1694 19:22:26.378935 Set Vref, RX VrefLevel [Byte0]: 41
1695 19:22:26.382230 [Byte1]: 41
1696 19:22:26.386331
1697 19:22:26.386528 Set Vref, RX VrefLevel [Byte0]: 42
1698 19:22:26.389990 [Byte1]: 42
1699 19:22:26.394252
1700 19:22:26.394417 Set Vref, RX VrefLevel [Byte0]: 43
1701 19:22:26.397708 [Byte1]: 43
1702 19:22:26.401714
1703 19:22:26.401896 Set Vref, RX VrefLevel [Byte0]: 44
1704 19:22:26.405274 [Byte1]: 44
1705 19:22:26.409312
1706 19:22:26.409473 Set Vref, RX VrefLevel [Byte0]: 45
1707 19:22:26.412514 [Byte1]: 45
1708 19:22:26.417116
1709 19:22:26.417301 Set Vref, RX VrefLevel [Byte0]: 46
1710 19:22:26.420141 [Byte1]: 46
1711 19:22:26.424787
1712 19:22:26.424969 Set Vref, RX VrefLevel [Byte0]: 47
1713 19:22:26.427760 [Byte1]: 47
1714 19:22:26.431957
1715 19:22:26.432098 Set Vref, RX VrefLevel [Byte0]: 48
1716 19:22:26.435538 [Byte1]: 48
1717 19:22:26.439602
1718 19:22:26.439797 Set Vref, RX VrefLevel [Byte0]: 49
1719 19:22:26.443271 [Byte1]: 49
1720 19:22:26.447226
1721 19:22:26.447386 Set Vref, RX VrefLevel [Byte0]: 50
1722 19:22:26.450753 [Byte1]: 50
1723 19:22:26.454781
1724 19:22:26.454944 Set Vref, RX VrefLevel [Byte0]: 51
1725 19:22:26.458222 [Byte1]: 51
1726 19:22:26.462593
1727 19:22:26.462751 Set Vref, RX VrefLevel [Byte0]: 52
1728 19:22:26.465678 [Byte1]: 52
1729 19:22:26.469996
1730 19:22:26.470172 Set Vref, RX VrefLevel [Byte0]: 53
1731 19:22:26.473364 [Byte1]: 53
1732 19:22:26.478015
1733 19:22:26.478177 Set Vref, RX VrefLevel [Byte0]: 54
1734 19:22:26.480763 [Byte1]: 54
1735 19:22:26.485339
1736 19:22:26.485519 Set Vref, RX VrefLevel [Byte0]: 55
1737 19:22:26.488693 [Byte1]: 55
1738 19:22:26.493113
1739 19:22:26.493290 Set Vref, RX VrefLevel [Byte0]: 56
1740 19:22:26.496199 [Byte1]: 56
1741 19:22:26.500813
1742 19:22:26.500982 Set Vref, RX VrefLevel [Byte0]: 57
1743 19:22:26.503874 [Byte1]: 57
1744 19:22:26.508061
1745 19:22:26.508219 Set Vref, RX VrefLevel [Byte0]: 58
1746 19:22:26.511582 [Byte1]: 58
1747 19:22:26.515539
1748 19:22:26.515702 Set Vref, RX VrefLevel [Byte0]: 59
1749 19:22:26.518842 [Byte1]: 59
1750 19:22:26.523110
1751 19:22:26.523265 Set Vref, RX VrefLevel [Byte0]: 60
1752 19:22:26.526595 [Byte1]: 60
1753 19:22:26.530877
1754 19:22:26.531063 Set Vref, RX VrefLevel [Byte0]: 61
1755 19:22:26.534426 [Byte1]: 61
1756 19:22:26.538595
1757 19:22:26.538756 Set Vref, RX VrefLevel [Byte0]: 62
1758 19:22:26.541603 [Byte1]: 62
1759 19:22:26.546341
1760 19:22:26.546494 Set Vref, RX VrefLevel [Byte0]: 63
1761 19:22:26.549241 [Byte1]: 63
1762 19:22:26.553851
1763 19:22:26.554005 Set Vref, RX VrefLevel [Byte0]: 64
1764 19:22:26.556767 [Byte1]: 64
1765 19:22:26.561490
1766 19:22:26.561647 Set Vref, RX VrefLevel [Byte0]: 65
1767 19:22:26.564421 [Byte1]: 65
1768 19:22:26.569226
1769 19:22:26.569421 Set Vref, RX VrefLevel [Byte0]: 66
1770 19:22:26.571940 [Byte1]: 66
1771 19:22:26.576745
1772 19:22:26.576922 Set Vref, RX VrefLevel [Byte0]: 67
1773 19:22:26.579812 [Byte1]: 67
1774 19:22:26.584459
1775 19:22:26.584620 Set Vref, RX VrefLevel [Byte0]: 68
1776 19:22:26.587651 [Byte1]: 68
1777 19:22:26.591534
1778 19:22:26.591672 Set Vref, RX VrefLevel [Byte0]: 69
1779 19:22:26.595263 [Byte1]: 69
1780 19:22:26.599471
1781 19:22:26.599635 Set Vref, RX VrefLevel [Byte0]: 70
1782 19:22:26.602639 [Byte1]: 70
1783 19:22:26.606697
1784 19:22:26.606868 Set Vref, RX VrefLevel [Byte0]: 71
1785 19:22:26.610264 [Byte1]: 71
1786 19:22:26.614460
1787 19:22:26.614639 Set Vref, RX VrefLevel [Byte0]: 72
1788 19:22:26.618041 [Byte1]: 72
1789 19:22:26.622175
1790 19:22:26.622342 Set Vref, RX VrefLevel [Byte0]: 73
1791 19:22:26.625352 [Byte1]: 73
1792 19:22:26.629678
1793 19:22:26.629858 Set Vref, RX VrefLevel [Byte0]: 74
1794 19:22:26.633060 [Byte1]: 74
1795 19:22:26.637224
1796 19:22:26.637395 Set Vref, RX VrefLevel [Byte0]: 75
1797 19:22:26.640696 [Byte1]: 75
1798 19:22:26.644797
1799 19:22:26.644960 Set Vref, RX VrefLevel [Byte0]: 76
1800 19:22:26.648318 [Byte1]: 76
1801 19:22:26.652387
1802 19:22:26.652547 Set Vref, RX VrefLevel [Byte0]: 77
1803 19:22:26.655836 [Byte1]: 77
1804 19:22:26.660418
1805 19:22:26.660599 Final RX Vref Byte 0 = 54 to rank0
1806 19:22:26.663339 Final RX Vref Byte 1 = 57 to rank0
1807 19:22:26.666894 Final RX Vref Byte 0 = 54 to rank1
1808 19:22:26.669957 Final RX Vref Byte 1 = 57 to rank1==
1809 19:22:26.672895 Dram Type= 6, Freq= 0, CH_1, rank 0
1810 19:22:26.680034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1811 19:22:26.680205 ==
1812 19:22:26.680278 DQS Delay:
1813 19:22:26.682951 DQS0 = 0, DQS1 = 0
1814 19:22:26.683113 DQM Delay:
1815 19:22:26.683186 DQM0 = 84, DQM1 = 80
1816 19:22:26.686420 DQ Delay:
1817 19:22:26.689742 DQ0 =92, DQ1 =80, DQ2 =72, DQ3 =84
1818 19:22:26.692905 DQ4 =80, DQ5 =96, DQ6 =96, DQ7 =76
1819 19:22:26.696456 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =72
1820 19:22:26.699713 DQ12 =88, DQ13 =88, DQ14 =84, DQ15 =88
1821 19:22:26.699918
1822 19:22:26.700024
1823 19:22:26.706209 [DQSOSCAuto] RK0, (LSB)MR18= 0x192d, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 403 ps
1824 19:22:26.710047 CH1 RK0: MR19=606, MR18=192D
1825 19:22:26.716122 CH1_RK0: MR19=0x606, MR18=0x192D, DQSOSC=398, MR23=63, INC=93, DEC=62
1826 19:22:26.716316
1827 19:22:26.719464 ----->DramcWriteLeveling(PI) begin...
1828 19:22:26.719656 ==
1829 19:22:26.722992 Dram Type= 6, Freq= 0, CH_1, rank 1
1830 19:22:26.726552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1831 19:22:26.726708 ==
1832 19:22:26.729650 Write leveling (Byte 0): 25 => 25
1833 19:22:26.732912 Write leveling (Byte 1): 29 => 29
1834 19:22:26.736129 DramcWriteLeveling(PI) end<-----
1835 19:22:26.736318
1836 19:22:26.736424 ==
1837 19:22:26.739463 Dram Type= 6, Freq= 0, CH_1, rank 1
1838 19:22:26.742804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1839 19:22:26.742996 ==
1840 19:22:26.746373 [Gating] SW mode calibration
1841 19:22:26.752857 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1842 19:22:26.759737 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1843 19:22:26.762640 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1844 19:22:26.769721 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1845 19:22:26.772761 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1846 19:22:26.776359 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 19:22:26.782493 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 19:22:26.786132 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 19:22:26.789717 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 19:22:26.792593 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 19:22:26.799446 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 19:22:26.802484 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 19:22:26.806229 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 19:22:26.812776 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 19:22:26.815723 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 19:22:26.818989 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 19:22:26.825751 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 19:22:26.828990 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 19:22:26.832264 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1860 19:22:26.838894 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1861 19:22:26.842367 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 19:22:26.845623 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 19:22:26.852732 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 19:22:26.856030 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 19:22:26.858992 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 19:22:26.865327 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 19:22:26.868773 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 19:22:26.872414 0 9 4 | B1->B0 | 2323 2727 | 0 1 | (0 0) (1 1)
1869 19:22:26.878945 0 9 8 | B1->B0 | 2f2f 3434 | 1 1 | (0 0) (1 1)
1870 19:22:26.881945 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1871 19:22:26.885701 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1872 19:22:26.892252 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1873 19:22:26.895118 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1874 19:22:26.898800 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1875 19:22:26.905292 0 10 0 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
1876 19:22:26.908652 0 10 4 | B1->B0 | 3232 2828 | 0 1 | (0 1) (1 0)
1877 19:22:26.911929 0 10 8 | B1->B0 | 2d2d 2323 | 1 0 | (0 0) (0 0)
1878 19:22:26.918586 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 19:22:26.921677 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 19:22:26.925190 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 19:22:26.931735 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 19:22:26.934917 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 19:22:26.938540 0 11 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1884 19:22:26.945493 0 11 4 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
1885 19:22:26.948389 0 11 8 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
1886 19:22:26.951660 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1887 19:22:26.958307 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1888 19:22:26.961637 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1889 19:22:26.964777 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1890 19:22:26.968241 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1891 19:22:26.974871 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1892 19:22:26.978567 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1893 19:22:26.981417 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1894 19:22:26.988536 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1895 19:22:26.991529 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1896 19:22:26.994970 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1897 19:22:27.001612 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1898 19:22:27.004637 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1899 19:22:27.008139 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1900 19:22:27.014901 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1901 19:22:27.017886 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1902 19:22:27.021321 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1903 19:22:27.027845 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1904 19:22:27.031430 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1905 19:22:27.034411 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1906 19:22:27.041095 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1907 19:22:27.044520 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1908 19:22:27.048045 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1909 19:22:27.051037 Total UI for P1: 0, mck2ui 16
1910 19:22:27.054360 best dqsien dly found for B0: ( 0, 14, 2)
1911 19:22:27.061892 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1912 19:22:27.062001 Total UI for P1: 0, mck2ui 16
1913 19:22:27.067778 best dqsien dly found for B1: ( 0, 14, 4)
1914 19:22:27.071199 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1915 19:22:27.074409 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1916 19:22:27.074530
1917 19:22:27.077951 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1918 19:22:27.081589 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1919 19:22:27.084496 [Gating] SW calibration Done
1920 19:22:27.084582 ==
1921 19:22:27.087539 Dram Type= 6, Freq= 0, CH_1, rank 1
1922 19:22:27.090867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1923 19:22:27.090952 ==
1924 19:22:27.094059 RX Vref Scan: 0
1925 19:22:27.094139
1926 19:22:27.094204 RX Vref 0 -> 0, step: 1
1927 19:22:27.094263
1928 19:22:27.097652 RX Delay -130 -> 252, step: 16
1929 19:22:27.101080 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1930 19:22:27.107840 iDelay=206, Bit 1, Center 77 (-50 ~ 205) 256
1931 19:22:27.110918 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1932 19:22:27.114429 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1933 19:22:27.117315 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1934 19:22:27.120913 iDelay=206, Bit 5, Center 85 (-34 ~ 205) 240
1935 19:22:27.127486 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1936 19:22:27.130873 iDelay=206, Bit 7, Center 77 (-50 ~ 205) 256
1937 19:22:27.134202 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1938 19:22:27.137410 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1939 19:22:27.140916 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1940 19:22:27.147436 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1941 19:22:27.150508 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1942 19:22:27.153943 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1943 19:22:27.157618 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1944 19:22:27.163614 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1945 19:22:27.163711 ==
1946 19:22:27.167405 Dram Type= 6, Freq= 0, CH_1, rank 1
1947 19:22:27.170769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1948 19:22:27.170854 ==
1949 19:22:27.170917 DQS Delay:
1950 19:22:27.173990 DQS0 = 0, DQS1 = 0
1951 19:22:27.174075 DQM Delay:
1952 19:22:27.177096 DQM0 = 81, DQM1 = 79
1953 19:22:27.177180 DQ Delay:
1954 19:22:27.180140 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1955 19:22:27.183670 DQ4 =85, DQ5 =85, DQ6 =85, DQ7 =77
1956 19:22:27.187203 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1957 19:22:27.190630 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1958 19:22:27.190738
1959 19:22:27.190832
1960 19:22:27.190920 ==
1961 19:22:27.193429 Dram Type= 6, Freq= 0, CH_1, rank 1
1962 19:22:27.196905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1963 19:22:27.196997 ==
1964 19:22:27.197064
1965 19:22:27.197124
1966 19:22:27.200550 TX Vref Scan disable
1967 19:22:27.203710 == TX Byte 0 ==
1968 19:22:27.207145 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1969 19:22:27.210365 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1970 19:22:27.213789 == TX Byte 1 ==
1971 19:22:27.217357 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1972 19:22:27.220312 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1973 19:22:27.220392 ==
1974 19:22:27.223840 Dram Type= 6, Freq= 0, CH_1, rank 1
1975 19:22:27.230577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1976 19:22:27.230679 ==
1977 19:22:27.242417 TX Vref=22, minBit 0, minWin=27, winSum=444
1978 19:22:27.245314 TX Vref=24, minBit 1, minWin=27, winSum=449
1979 19:22:27.248582 TX Vref=26, minBit 5, minWin=27, winSum=452
1980 19:22:27.252121 TX Vref=28, minBit 1, minWin=28, winSum=456
1981 19:22:27.255274 TX Vref=30, minBit 5, minWin=27, winSum=453
1982 19:22:27.261692 TX Vref=32, minBit 0, minWin=27, winSum=453
1983 19:22:27.265320 [TxChooseVref] Worse bit 1, Min win 28, Win sum 456, Final Vref 28
1984 19:22:27.265447
1985 19:22:27.268304 Final TX Range 1 Vref 28
1986 19:22:27.268428
1987 19:22:27.268570 ==
1988 19:22:27.271786 Dram Type= 6, Freq= 0, CH_1, rank 1
1989 19:22:27.275322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1990 19:22:27.278270 ==
1991 19:22:27.278370
1992 19:22:27.278466
1993 19:22:27.278540 TX Vref Scan disable
1994 19:22:27.282478 == TX Byte 0 ==
1995 19:22:27.285528 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1996 19:22:27.291808 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1997 19:22:27.291951 == TX Byte 1 ==
1998 19:22:27.295165 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1999 19:22:27.302276 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2000 19:22:27.302420
2001 19:22:27.302516 [DATLAT]
2002 19:22:27.302622 Freq=800, CH1 RK1
2003 19:22:27.302713
2004 19:22:27.305202 DATLAT Default: 0xa
2005 19:22:27.305332 0, 0xFFFF, sum = 0
2006 19:22:27.308702 1, 0xFFFF, sum = 0
2007 19:22:27.308872 2, 0xFFFF, sum = 0
2008 19:22:27.312208 3, 0xFFFF, sum = 0
2009 19:22:27.312332 4, 0xFFFF, sum = 0
2010 19:22:27.315579 5, 0xFFFF, sum = 0
2011 19:22:27.318966 6, 0xFFFF, sum = 0
2012 19:22:27.319076 7, 0xFFFF, sum = 0
2013 19:22:27.322193 8, 0xFFFF, sum = 0
2014 19:22:27.322272 9, 0x0, sum = 1
2015 19:22:27.322336 10, 0x0, sum = 2
2016 19:22:27.325242 11, 0x0, sum = 3
2017 19:22:27.325346 12, 0x0, sum = 4
2018 19:22:27.328799 best_step = 10
2019 19:22:27.328874
2020 19:22:27.328944 ==
2021 19:22:27.331741 Dram Type= 6, Freq= 0, CH_1, rank 1
2022 19:22:27.335335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2023 19:22:27.335412 ==
2024 19:22:27.338876 RX Vref Scan: 0
2025 19:22:27.338951
2026 19:22:27.339021 RX Vref 0 -> 0, step: 1
2027 19:22:27.339081
2028 19:22:27.341847 RX Delay -95 -> 252, step: 8
2029 19:22:27.348907 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
2030 19:22:27.351891 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
2031 19:22:27.355365 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
2032 19:22:27.358755 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
2033 19:22:27.361901 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
2034 19:22:27.368909 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
2035 19:22:27.371809 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2036 19:22:27.375396 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
2037 19:22:27.378373 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
2038 19:22:27.381873 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2039 19:22:27.388340 iDelay=209, Bit 10, Center 84 (-31 ~ 200) 232
2040 19:22:27.391681 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
2041 19:22:27.395149 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
2042 19:22:27.398259 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2043 19:22:27.405065 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2044 19:22:27.408186 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2045 19:22:27.408273 ==
2046 19:22:27.411638 Dram Type= 6, Freq= 0, CH_1, rank 1
2047 19:22:27.415040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2048 19:22:27.415138 ==
2049 19:22:27.418544 DQS Delay:
2050 19:22:27.418626 DQS0 = 0, DQS1 = 0
2051 19:22:27.418704 DQM Delay:
2052 19:22:27.421654 DQM0 = 86, DQM1 = 81
2053 19:22:27.421742 DQ Delay:
2054 19:22:27.425039 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =84
2055 19:22:27.428355 DQ4 =84, DQ5 =96, DQ6 =92, DQ7 =84
2056 19:22:27.431588 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =72
2057 19:22:27.434862 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
2058 19:22:27.434953
2059 19:22:27.435041
2060 19:22:27.444781 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e3a, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 402 ps
2061 19:22:27.444889 CH1 RK1: MR19=606, MR18=1E3A
2062 19:22:27.451349 CH1_RK1: MR19=0x606, MR18=0x1E3A, DQSOSC=395, MR23=63, INC=94, DEC=63
2063 19:22:27.454863 [RxdqsGatingPostProcess] freq 800
2064 19:22:27.461325 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2065 19:22:27.464851 Pre-setting of DQS Precalculation
2066 19:22:27.468301 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2067 19:22:27.474985 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2068 19:22:27.484934 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2069 19:22:27.485081
2070 19:22:27.485153
2071 19:22:27.487876 [Calibration Summary] 1600 Mbps
2072 19:22:27.487996 CH 0, Rank 0
2073 19:22:27.491407 SW Impedance : PASS
2074 19:22:27.491487 DUTY Scan : NO K
2075 19:22:27.494987 ZQ Calibration : PASS
2076 19:22:27.495065 Jitter Meter : NO K
2077 19:22:27.498453 CBT Training : PASS
2078 19:22:27.501406 Write leveling : PASS
2079 19:22:27.501535 RX DQS gating : PASS
2080 19:22:27.504810 RX DQ/DQS(RDDQC) : PASS
2081 19:22:27.508030 TX DQ/DQS : PASS
2082 19:22:27.508136 RX DATLAT : PASS
2083 19:22:27.511194 RX DQ/DQS(Engine): PASS
2084 19:22:27.514321 TX OE : NO K
2085 19:22:27.514442 All Pass.
2086 19:22:27.514537
2087 19:22:27.514641 CH 0, Rank 1
2088 19:22:27.517747 SW Impedance : PASS
2089 19:22:27.521096 DUTY Scan : NO K
2090 19:22:27.521219 ZQ Calibration : PASS
2091 19:22:27.524587 Jitter Meter : NO K
2092 19:22:27.528292 CBT Training : PASS
2093 19:22:27.528400 Write leveling : PASS
2094 19:22:27.531013 RX DQS gating : PASS
2095 19:22:27.534520 RX DQ/DQS(RDDQC) : PASS
2096 19:22:27.534636 TX DQ/DQS : PASS
2097 19:22:27.538184 RX DATLAT : PASS
2098 19:22:27.538274 RX DQ/DQS(Engine): PASS
2099 19:22:27.541491 TX OE : NO K
2100 19:22:27.541582 All Pass.
2101 19:22:27.541669
2102 19:22:27.544511 CH 1, Rank 0
2103 19:22:27.544598 SW Impedance : PASS
2104 19:22:27.547821 DUTY Scan : NO K
2105 19:22:27.551388 ZQ Calibration : PASS
2106 19:22:27.551507 Jitter Meter : NO K
2107 19:22:27.554367 CBT Training : PASS
2108 19:22:27.557883 Write leveling : PASS
2109 19:22:27.557974 RX DQS gating : PASS
2110 19:22:27.560883 RX DQ/DQS(RDDQC) : PASS
2111 19:22:27.564519 TX DQ/DQS : PASS
2112 19:22:27.564611 RX DATLAT : PASS
2113 19:22:27.567566 RX DQ/DQS(Engine): PASS
2114 19:22:27.571080 TX OE : NO K
2115 19:22:27.571178 All Pass.
2116 19:22:27.571268
2117 19:22:27.571351 CH 1, Rank 1
2118 19:22:27.574090 SW Impedance : PASS
2119 19:22:27.577498 DUTY Scan : NO K
2120 19:22:27.577587 ZQ Calibration : PASS
2121 19:22:27.581079 Jitter Meter : NO K
2122 19:22:27.584430 CBT Training : PASS
2123 19:22:27.584516 Write leveling : PASS
2124 19:22:27.587605 RX DQS gating : PASS
2125 19:22:27.591133 RX DQ/DQS(RDDQC) : PASS
2126 19:22:27.591223 TX DQ/DQS : PASS
2127 19:22:27.594061 RX DATLAT : PASS
2128 19:22:27.597523 RX DQ/DQS(Engine): PASS
2129 19:22:27.597619 TX OE : NO K
2130 19:22:27.597691 All Pass.
2131 19:22:27.600997
2132 19:22:27.601084 DramC Write-DBI off
2133 19:22:27.603905 PER_BANK_REFRESH: Hybrid Mode
2134 19:22:27.603992 TX_TRACKING: ON
2135 19:22:27.607562 [GetDramInforAfterCalByMRR] Vendor 6.
2136 19:22:27.610994 [GetDramInforAfterCalByMRR] Revision 606.
2137 19:22:27.617193 [GetDramInforAfterCalByMRR] Revision 2 0.
2138 19:22:27.617296 MR0 0x3b3b
2139 19:22:27.617368 MR8 0x5151
2140 19:22:27.620891 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2141 19:22:27.620978
2142 19:22:27.623671 MR0 0x3b3b
2143 19:22:27.623765 MR8 0x5151
2144 19:22:27.627045 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2145 19:22:27.627134
2146 19:22:27.636857 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2147 19:22:27.640379 [FAST_K] Save calibration result to emmc
2148 19:22:27.643825 [FAST_K] Save calibration result to emmc
2149 19:22:27.646814 dram_init: config_dvfs: 1
2150 19:22:27.650075 dramc_set_vcore_voltage set vcore to 662500
2151 19:22:27.653411 Read voltage for 1200, 2
2152 19:22:27.653507 Vio18 = 0
2153 19:22:27.653594 Vcore = 662500
2154 19:22:27.657110 Vdram = 0
2155 19:22:27.657201 Vddq = 0
2156 19:22:27.657288 Vmddr = 0
2157 19:22:27.663765 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2158 19:22:27.666596 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2159 19:22:27.670290 MEM_TYPE=3, freq_sel=15
2160 19:22:27.673380 sv_algorithm_assistance_LP4_1600
2161 19:22:27.676930 ============ PULL DRAM RESETB DOWN ============
2162 19:22:27.680408 ========== PULL DRAM RESETB DOWN end =========
2163 19:22:27.687089 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2164 19:22:27.690055 ===================================
2165 19:22:27.690153 LPDDR4 DRAM CONFIGURATION
2166 19:22:27.693371 ===================================
2167 19:22:27.696854 EX_ROW_EN[0] = 0x0
2168 19:22:27.700247 EX_ROW_EN[1] = 0x0
2169 19:22:27.700368 LP4Y_EN = 0x0
2170 19:22:27.703321 WORK_FSP = 0x0
2171 19:22:27.703405 WL = 0x4
2172 19:22:27.706751 RL = 0x4
2173 19:22:27.706838 BL = 0x2
2174 19:22:27.710308 RPST = 0x0
2175 19:22:27.710395 RD_PRE = 0x0
2176 19:22:27.713263 WR_PRE = 0x1
2177 19:22:27.713347 WR_PST = 0x0
2178 19:22:27.716941 DBI_WR = 0x0
2179 19:22:27.717028 DBI_RD = 0x0
2180 19:22:27.719917 OTF = 0x1
2181 19:22:27.723570 ===================================
2182 19:22:27.726506 ===================================
2183 19:22:27.726611 ANA top config
2184 19:22:27.729876 ===================================
2185 19:22:27.733205 DLL_ASYNC_EN = 0
2186 19:22:27.736555 ALL_SLAVE_EN = 0
2187 19:22:27.740089 NEW_RANK_MODE = 1
2188 19:22:27.740198 DLL_IDLE_MODE = 1
2189 19:22:27.743424 LP45_APHY_COMB_EN = 1
2190 19:22:27.746358 TX_ODT_DIS = 1
2191 19:22:27.750056 NEW_8X_MODE = 1
2192 19:22:27.753277 ===================================
2193 19:22:27.756491 ===================================
2194 19:22:27.759799 data_rate = 2400
2195 19:22:27.759909 CKR = 1
2196 19:22:27.763206 DQ_P2S_RATIO = 8
2197 19:22:27.766872 ===================================
2198 19:22:27.769868 CA_P2S_RATIO = 8
2199 19:22:27.773424 DQ_CA_OPEN = 0
2200 19:22:27.776854 DQ_SEMI_OPEN = 0
2201 19:22:27.776955 CA_SEMI_OPEN = 0
2202 19:22:27.779998 CA_FULL_RATE = 0
2203 19:22:27.783455 DQ_CKDIV4_EN = 0
2204 19:22:27.786552 CA_CKDIV4_EN = 0
2205 19:22:27.790067 CA_PREDIV_EN = 0
2206 19:22:27.793050 PH8_DLY = 17
2207 19:22:27.796379 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2208 19:22:27.796476 DQ_AAMCK_DIV = 4
2209 19:22:27.799905 CA_AAMCK_DIV = 4
2210 19:22:27.803455 CA_ADMCK_DIV = 4
2211 19:22:27.806352 DQ_TRACK_CA_EN = 0
2212 19:22:27.809919 CA_PICK = 1200
2213 19:22:27.813373 CA_MCKIO = 1200
2214 19:22:27.813458 MCKIO_SEMI = 0
2215 19:22:27.816354 PLL_FREQ = 2366
2216 19:22:27.819954 DQ_UI_PI_RATIO = 32
2217 19:22:27.823410 CA_UI_PI_RATIO = 0
2218 19:22:27.826352 ===================================
2219 19:22:27.830028 ===================================
2220 19:22:27.832961 memory_type:LPDDR4
2221 19:22:27.833057 GP_NUM : 10
2222 19:22:27.836374 SRAM_EN : 1
2223 19:22:27.839844 MD32_EN : 0
2224 19:22:27.843344 ===================================
2225 19:22:27.843428 [ANA_INIT] >>>>>>>>>>>>>>
2226 19:22:27.846230 <<<<<< [CONFIGURE PHASE]: ANA_TX
2227 19:22:27.849704 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2228 19:22:27.853135 ===================================
2229 19:22:27.856852 data_rate = 2400,PCW = 0X5b00
2230 19:22:27.860134 ===================================
2231 19:22:27.863364 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2232 19:22:27.870024 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2233 19:22:27.872911 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2234 19:22:27.879429 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2235 19:22:27.883046 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2236 19:22:27.886022 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2237 19:22:27.886104 [ANA_INIT] flow start
2238 19:22:27.889489 [ANA_INIT] PLL >>>>>>>>
2239 19:22:27.893227 [ANA_INIT] PLL <<<<<<<<
2240 19:22:27.893310 [ANA_INIT] MIDPI >>>>>>>>
2241 19:22:27.896585 [ANA_INIT] MIDPI <<<<<<<<
2242 19:22:27.899439 [ANA_INIT] DLL >>>>>>>>
2243 19:22:27.902895 [ANA_INIT] DLL <<<<<<<<
2244 19:22:27.902969 [ANA_INIT] flow end
2245 19:22:27.906190 ============ LP4 DIFF to SE enter ============
2246 19:22:27.913005 ============ LP4 DIFF to SE exit ============
2247 19:22:27.913090 [ANA_INIT] <<<<<<<<<<<<<
2248 19:22:27.916428 [Flow] Enable top DCM control >>>>>
2249 19:22:27.919416 [Flow] Enable top DCM control <<<<<
2250 19:22:27.923029 Enable DLL master slave shuffle
2251 19:22:27.929462 ==============================================================
2252 19:22:27.929545 Gating Mode config
2253 19:22:27.936159 ==============================================================
2254 19:22:27.939551 Config description:
2255 19:22:27.949277 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2256 19:22:27.955860 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2257 19:22:27.959354 SELPH_MODE 0: By rank 1: By Phase
2258 19:22:27.965599 ==============================================================
2259 19:22:27.968805 GAT_TRACK_EN = 1
2260 19:22:27.972585 RX_GATING_MODE = 2
2261 19:22:27.972668 RX_GATING_TRACK_MODE = 2
2262 19:22:27.976029 SELPH_MODE = 1
2263 19:22:27.978990 PICG_EARLY_EN = 1
2264 19:22:27.982148 VALID_LAT_VALUE = 1
2265 19:22:27.988640 ==============================================================
2266 19:22:27.992187 Enter into Gating configuration >>>>
2267 19:22:27.995645 Exit from Gating configuration <<<<
2268 19:22:27.998574 Enter into DVFS_PRE_config >>>>>
2269 19:22:28.008748 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2270 19:22:28.012151 Exit from DVFS_PRE_config <<<<<
2271 19:22:28.015596 Enter into PICG configuration >>>>
2272 19:22:28.018963 Exit from PICG configuration <<<<
2273 19:22:28.022115 [RX_INPUT] configuration >>>>>
2274 19:22:28.025541 [RX_INPUT] configuration <<<<<
2275 19:22:28.028529 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2276 19:22:28.035213 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2277 19:22:28.041747 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2278 19:22:28.048394 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2279 19:22:28.051727 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2280 19:22:28.058713 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2281 19:22:28.061665 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2282 19:22:28.068574 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2283 19:22:28.071483 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2284 19:22:28.074940 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2285 19:22:28.078353 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2286 19:22:28.084990 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2287 19:22:28.088552 ===================================
2288 19:22:28.091376 LPDDR4 DRAM CONFIGURATION
2289 19:22:28.095060 ===================================
2290 19:22:28.095134 EX_ROW_EN[0] = 0x0
2291 19:22:28.097937 EX_ROW_EN[1] = 0x0
2292 19:22:28.098018 LP4Y_EN = 0x0
2293 19:22:28.101391 WORK_FSP = 0x0
2294 19:22:28.101465 WL = 0x4
2295 19:22:28.105156 RL = 0x4
2296 19:22:28.105239 BL = 0x2
2297 19:22:28.107959 RPST = 0x0
2298 19:22:28.108041 RD_PRE = 0x0
2299 19:22:28.111534 WR_PRE = 0x1
2300 19:22:28.111616 WR_PST = 0x0
2301 19:22:28.114398 DBI_WR = 0x0
2302 19:22:28.114480 DBI_RD = 0x0
2303 19:22:28.118039 OTF = 0x1
2304 19:22:28.121472 ===================================
2305 19:22:28.124391 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2306 19:22:28.127663 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2307 19:22:28.134754 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2308 19:22:28.137727 ===================================
2309 19:22:28.137814 LPDDR4 DRAM CONFIGURATION
2310 19:22:28.141312 ===================================
2311 19:22:28.144371 EX_ROW_EN[0] = 0x10
2312 19:22:28.147777 EX_ROW_EN[1] = 0x0
2313 19:22:28.147878 LP4Y_EN = 0x0
2314 19:22:28.151322 WORK_FSP = 0x0
2315 19:22:28.151396 WL = 0x4
2316 19:22:28.154280 RL = 0x4
2317 19:22:28.154353 BL = 0x2
2318 19:22:28.157576 RPST = 0x0
2319 19:22:28.157658 RD_PRE = 0x0
2320 19:22:28.161150 WR_PRE = 0x1
2321 19:22:28.161232 WR_PST = 0x0
2322 19:22:28.164188 DBI_WR = 0x0
2323 19:22:28.164269 DBI_RD = 0x0
2324 19:22:28.167711 OTF = 0x1
2325 19:22:28.171098 ===================================
2326 19:22:28.177951 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2327 19:22:28.178043 ==
2328 19:22:28.180813 Dram Type= 6, Freq= 0, CH_0, rank 0
2329 19:22:28.184497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2330 19:22:28.184584 ==
2331 19:22:28.187348 [Duty_Offset_Calibration]
2332 19:22:28.187430 B0:2 B1:0 CA:4
2333 19:22:28.187495
2334 19:22:28.190818 [DutyScan_Calibration_Flow] k_type=0
2335 19:22:28.201486
2336 19:22:28.201590 ==CLK 0==
2337 19:22:28.204873 Final CLK duty delay cell = 0
2338 19:22:28.208149 [0] MAX Duty = 5156%(X100), DQS PI = 14
2339 19:22:28.211541 [0] MIN Duty = 5000%(X100), DQS PI = 8
2340 19:22:28.214505 [0] AVG Duty = 5078%(X100)
2341 19:22:28.214589
2342 19:22:28.217941 CH0 CLK Duty spec in!! Max-Min= 156%
2343 19:22:28.221589 [DutyScan_Calibration_Flow] ====Done====
2344 19:22:28.221672
2345 19:22:28.224518 [DutyScan_Calibration_Flow] k_type=1
2346 19:22:28.240597
2347 19:22:28.240703 ==DQS 0 ==
2348 19:22:28.244115 Final DQS duty delay cell = 0
2349 19:22:28.247083 [0] MAX Duty = 5156%(X100), DQS PI = 18
2350 19:22:28.250702 [0] MIN Duty = 5093%(X100), DQS PI = 0
2351 19:22:28.254080 [0] AVG Duty = 5124%(X100)
2352 19:22:28.254161
2353 19:22:28.254224 ==DQS 1 ==
2354 19:22:28.257190 Final DQS duty delay cell = 0
2355 19:22:28.260546 [0] MAX Duty = 5125%(X100), DQS PI = 4
2356 19:22:28.263909 [0] MIN Duty = 4969%(X100), DQS PI = 14
2357 19:22:28.266884 [0] AVG Duty = 5047%(X100)
2358 19:22:28.266965
2359 19:22:28.270458 CH0 DQS 0 Duty spec in!! Max-Min= 63%
2360 19:22:28.270539
2361 19:22:28.273864 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2362 19:22:28.277326 [DutyScan_Calibration_Flow] ====Done====
2363 19:22:28.277407
2364 19:22:28.280076 [DutyScan_Calibration_Flow] k_type=3
2365 19:22:28.297415
2366 19:22:28.297539 ==DQM 0 ==
2367 19:22:28.300320 Final DQM duty delay cell = 0
2368 19:22:28.303679 [0] MAX Duty = 5093%(X100), DQS PI = 18
2369 19:22:28.306919 [0] MIN Duty = 4844%(X100), DQS PI = 50
2370 19:22:28.310332 [0] AVG Duty = 4968%(X100)
2371 19:22:28.310413
2372 19:22:28.310477 ==DQM 1 ==
2373 19:22:28.313911 Final DQM duty delay cell = 0
2374 19:22:28.316992 [0] MAX Duty = 4969%(X100), DQS PI = 2
2375 19:22:28.320566 [0] MIN Duty = 4875%(X100), DQS PI = 18
2376 19:22:28.320648 [0] AVG Duty = 4922%(X100)
2377 19:22:28.323495
2378 19:22:28.327076 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2379 19:22:28.327157
2380 19:22:28.330448 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2381 19:22:28.333418 [DutyScan_Calibration_Flow] ====Done====
2382 19:22:28.333499
2383 19:22:28.337010 [DutyScan_Calibration_Flow] k_type=2
2384 19:22:28.353413
2385 19:22:28.353507 ==DQ 0 ==
2386 19:22:28.356388 Final DQ duty delay cell = 0
2387 19:22:28.359785 [0] MAX Duty = 5125%(X100), DQS PI = 18
2388 19:22:28.363147 [0] MIN Duty = 4969%(X100), DQS PI = 52
2389 19:22:28.363229 [0] AVG Duty = 5047%(X100)
2390 19:22:28.366525
2391 19:22:28.366639 ==DQ 1 ==
2392 19:22:28.370021 Final DQ duty delay cell = 0
2393 19:22:28.373046 [0] MAX Duty = 5156%(X100), DQS PI = 6
2394 19:22:28.376631 [0] MIN Duty = 4938%(X100), DQS PI = 14
2395 19:22:28.376712 [0] AVG Duty = 5047%(X100)
2396 19:22:28.376776
2397 19:22:28.380132 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2398 19:22:28.383507
2399 19:22:28.386718 CH0 DQ 1 Duty spec in!! Max-Min= 218%
2400 19:22:28.390147 [DutyScan_Calibration_Flow] ====Done====
2401 19:22:28.390229 ==
2402 19:22:28.392973 Dram Type= 6, Freq= 0, CH_1, rank 0
2403 19:22:28.396454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2404 19:22:28.396536 ==
2405 19:22:28.400039 [Duty_Offset_Calibration]
2406 19:22:28.400125 B0:0 B1:-1 CA:3
2407 19:22:28.400190
2408 19:22:28.402883 [DutyScan_Calibration_Flow] k_type=0
2409 19:22:28.412684
2410 19:22:28.412770 ==CLK 0==
2411 19:22:28.415739 Final CLK duty delay cell = -4
2412 19:22:28.419298 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2413 19:22:28.422293 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2414 19:22:28.425729 [-4] AVG Duty = 4938%(X100)
2415 19:22:28.425810
2416 19:22:28.429256 CH1 CLK Duty spec in!! Max-Min= 124%
2417 19:22:28.432746 [DutyScan_Calibration_Flow] ====Done====
2418 19:22:28.432828
2419 19:22:28.435624 [DutyScan_Calibration_Flow] k_type=1
2420 19:22:28.452091
2421 19:22:28.452190 ==DQS 0 ==
2422 19:22:28.455769 Final DQS duty delay cell = 0
2423 19:22:28.458849 [0] MAX Duty = 5187%(X100), DQS PI = 18
2424 19:22:28.462391 [0] MIN Duty = 4907%(X100), DQS PI = 38
2425 19:22:28.462475 [0] AVG Duty = 5047%(X100)
2426 19:22:28.465346
2427 19:22:28.465428 ==DQS 1 ==
2428 19:22:28.468964 Final DQS duty delay cell = 0
2429 19:22:28.472202 [0] MAX Duty = 5156%(X100), DQS PI = 8
2430 19:22:28.475685 [0] MIN Duty = 5031%(X100), DQS PI = 18
2431 19:22:28.478758 [0] AVG Duty = 5093%(X100)
2432 19:22:28.478842
2433 19:22:28.481745 CH1 DQS 0 Duty spec in!! Max-Min= 280%
2434 19:22:28.481827
2435 19:22:28.485268 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2436 19:22:28.488649 [DutyScan_Calibration_Flow] ====Done====
2437 19:22:28.488732
2438 19:22:28.491915 [DutyScan_Calibration_Flow] k_type=3
2439 19:22:28.508590
2440 19:22:28.508713 ==DQM 0 ==
2441 19:22:28.511613 Final DQM duty delay cell = 0
2442 19:22:28.515159 [0] MAX Duty = 5031%(X100), DQS PI = 28
2443 19:22:28.518638 [0] MIN Duty = 4813%(X100), DQS PI = 38
2444 19:22:28.521479 [0] AVG Duty = 4922%(X100)
2445 19:22:28.521561
2446 19:22:28.521626 ==DQM 1 ==
2447 19:22:28.525242 Final DQM duty delay cell = 0
2448 19:22:28.528166 [0] MAX Duty = 5000%(X100), DQS PI = 34
2449 19:22:28.531519 [0] MIN Duty = 4813%(X100), DQS PI = 16
2450 19:22:28.535210 [0] AVG Duty = 4906%(X100)
2451 19:22:28.535292
2452 19:22:28.538045 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2453 19:22:28.538126
2454 19:22:28.541680 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2455 19:22:28.545258 [DutyScan_Calibration_Flow] ====Done====
2456 19:22:28.545341
2457 19:22:28.548298 [DutyScan_Calibration_Flow] k_type=2
2458 19:22:28.564865
2459 19:22:28.564969 ==DQ 0 ==
2460 19:22:28.568328 Final DQ duty delay cell = -4
2461 19:22:28.571850 [-4] MAX Duty = 5000%(X100), DQS PI = 14
2462 19:22:28.574835 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2463 19:22:28.578158 [-4] AVG Duty = 4922%(X100)
2464 19:22:28.578242
2465 19:22:28.578306 ==DQ 1 ==
2466 19:22:28.581605 Final DQ duty delay cell = 4
2467 19:22:28.584988 [4] MAX Duty = 5156%(X100), DQS PI = 28
2468 19:22:28.588485 [4] MIN Duty = 5031%(X100), DQS PI = 62
2469 19:22:28.591358 [4] AVG Duty = 5093%(X100)
2470 19:22:28.591441
2471 19:22:28.594707 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2472 19:22:28.594789
2473 19:22:28.598489 CH1 DQ 1 Duty spec in!! Max-Min= 125%
2474 19:22:28.601743 [DutyScan_Calibration_Flow] ====Done====
2475 19:22:28.605113 nWR fixed to 30
2476 19:22:28.608541 [ModeRegInit_LP4] CH0 RK0
2477 19:22:28.608619 [ModeRegInit_LP4] CH0 RK1
2478 19:22:28.611433 [ModeRegInit_LP4] CH1 RK0
2479 19:22:28.614469 [ModeRegInit_LP4] CH1 RK1
2480 19:22:28.614542 match AC timing 7
2481 19:22:28.621077 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2482 19:22:28.624789 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2483 19:22:28.628218 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2484 19:22:28.634423 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2485 19:22:28.637619 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2486 19:22:28.637696 ==
2487 19:22:28.641018 Dram Type= 6, Freq= 0, CH_0, rank 0
2488 19:22:28.644516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2489 19:22:28.644640 ==
2490 19:22:28.651074 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2491 19:22:28.657370 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2492 19:22:28.665166 [CA 0] Center 39 (9~70) winsize 62
2493 19:22:28.669053 [CA 1] Center 39 (9~69) winsize 61
2494 19:22:28.671997 [CA 2] Center 35 (5~66) winsize 62
2495 19:22:28.675172 [CA 3] Center 35 (5~66) winsize 62
2496 19:22:28.678607 [CA 4] Center 33 (3~64) winsize 62
2497 19:22:28.682067 [CA 5] Center 33 (3~63) winsize 61
2498 19:22:28.682158
2499 19:22:28.685569 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2500 19:22:28.685720
2501 19:22:28.688751 [CATrainingPosCal] consider 1 rank data
2502 19:22:28.692187 u2DelayCellTimex100 = 270/100 ps
2503 19:22:28.695183 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2504 19:22:28.702078 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2505 19:22:28.705446 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2506 19:22:28.708463 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2507 19:22:28.711805 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2508 19:22:28.715241 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2509 19:22:28.715326
2510 19:22:28.718117 CA PerBit enable=1, Macro0, CA PI delay=33
2511 19:22:28.718202
2512 19:22:28.721669 [CBTSetCACLKResult] CA Dly = 33
2513 19:22:28.721754 CS Dly: 7 (0~38)
2514 19:22:28.725142 ==
2515 19:22:28.728202 Dram Type= 6, Freq= 0, CH_0, rank 1
2516 19:22:28.731770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2517 19:22:28.731905 ==
2518 19:22:28.738272 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2519 19:22:28.741695 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2520 19:22:28.751383 [CA 0] Center 39 (9~70) winsize 62
2521 19:22:28.754723 [CA 1] Center 39 (9~70) winsize 62
2522 19:22:28.757773 [CA 2] Center 35 (5~66) winsize 62
2523 19:22:28.761365 [CA 3] Center 35 (5~66) winsize 62
2524 19:22:28.764461 [CA 4] Center 34 (4~65) winsize 62
2525 19:22:28.767911 [CA 5] Center 33 (3~64) winsize 62
2526 19:22:28.768007
2527 19:22:28.770825 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2528 19:22:28.770906
2529 19:22:28.774374 [CATrainingPosCal] consider 2 rank data
2530 19:22:28.777366 u2DelayCellTimex100 = 270/100 ps
2531 19:22:28.780952 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2532 19:22:28.787727 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2533 19:22:28.790664 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2534 19:22:28.793981 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2535 19:22:28.797485 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2536 19:22:28.801001 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2537 19:22:28.801094
2538 19:22:28.803948 CA PerBit enable=1, Macro0, CA PI delay=33
2539 19:22:28.804030
2540 19:22:28.807389 [CBTSetCACLKResult] CA Dly = 33
2541 19:22:28.810976 CS Dly: 8 (0~41)
2542 19:22:28.811107
2543 19:22:28.814288 ----->DramcWriteLeveling(PI) begin...
2544 19:22:28.814490 ==
2545 19:22:28.817491 Dram Type= 6, Freq= 0, CH_0, rank 0
2546 19:22:28.820544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2547 19:22:28.820638 ==
2548 19:22:28.824350 Write leveling (Byte 0): 31 => 31
2549 19:22:28.827509 Write leveling (Byte 1): 25 => 25
2550 19:22:28.830472 DramcWriteLeveling(PI) end<-----
2551 19:22:28.830612
2552 19:22:28.830720 ==
2553 19:22:28.834017 Dram Type= 6, Freq= 0, CH_0, rank 0
2554 19:22:28.836967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2555 19:22:28.837127 ==
2556 19:22:28.840489 [Gating] SW mode calibration
2557 19:22:28.846877 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2558 19:22:28.853856 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2559 19:22:28.856779 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2560 19:22:28.860476 0 15 4 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
2561 19:22:28.866982 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2562 19:22:28.870479 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2563 19:22:28.873541 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2564 19:22:28.880588 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2565 19:22:28.883536 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2566 19:22:28.887105 0 15 28 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 1)
2567 19:22:28.893968 1 0 0 | B1->B0 | 3131 2323 | 0 0 | (1 0) (0 0)
2568 19:22:28.896824 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2569 19:22:28.900450 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2570 19:22:28.906656 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2571 19:22:28.910332 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2572 19:22:28.913401 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2573 19:22:28.919904 1 0 24 | B1->B0 | 2323 3030 | 0 1 | (0 0) (0 0)
2574 19:22:28.923377 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2575 19:22:28.926582 1 1 0 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
2576 19:22:28.933624 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2577 19:22:28.936754 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2578 19:22:28.940211 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2579 19:22:28.946523 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2580 19:22:28.950133 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2581 19:22:28.953107 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2582 19:22:28.956521 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2583 19:22:28.963004 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2584 19:22:28.966324 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2585 19:22:28.969669 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2586 19:22:28.976165 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2587 19:22:28.979733 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2588 19:22:28.983080 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2589 19:22:28.989597 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2590 19:22:28.992563 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2591 19:22:28.996052 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2592 19:22:29.002469 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2593 19:22:29.006163 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2594 19:22:29.009146 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2595 19:22:29.015771 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2596 19:22:29.019372 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2597 19:22:29.022520 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2598 19:22:29.029343 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2599 19:22:29.032815 Total UI for P1: 0, mck2ui 16
2600 19:22:29.036195 best dqsien dly found for B0: ( 1, 3, 24)
2601 19:22:29.039462 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2602 19:22:29.042715 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2603 19:22:29.045844 Total UI for P1: 0, mck2ui 16
2604 19:22:29.049169 best dqsien dly found for B1: ( 1, 3, 30)
2605 19:22:29.052431 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2606 19:22:29.055836 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2607 19:22:29.055956
2608 19:22:29.062321 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2609 19:22:29.065966 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2610 19:22:29.068946 [Gating] SW calibration Done
2611 19:22:29.069028 ==
2612 19:22:29.072297 Dram Type= 6, Freq= 0, CH_0, rank 0
2613 19:22:29.075593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2614 19:22:29.075700 ==
2615 19:22:29.075793 RX Vref Scan: 0
2616 19:22:29.075885
2617 19:22:29.079069 RX Vref 0 -> 0, step: 1
2618 19:22:29.079151
2619 19:22:29.082542 RX Delay -40 -> 252, step: 8
2620 19:22:29.085504 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2621 19:22:29.088700 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2622 19:22:29.095623 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2623 19:22:29.098602 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2624 19:22:29.102214 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2625 19:22:29.105122 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2626 19:22:29.108634 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2627 19:22:29.115180 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
2628 19:22:29.118645 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2629 19:22:29.122034 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2630 19:22:29.125394 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2631 19:22:29.128372 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2632 19:22:29.135365 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2633 19:22:29.138362 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2634 19:22:29.141811 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2635 19:22:29.145241 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2636 19:22:29.145349 ==
2637 19:22:29.148541 Dram Type= 6, Freq= 0, CH_0, rank 0
2638 19:22:29.154743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2639 19:22:29.154844 ==
2640 19:22:29.154977 DQS Delay:
2641 19:22:29.158298 DQS0 = 0, DQS1 = 0
2642 19:22:29.158396 DQM Delay:
2643 19:22:29.158496 DQM0 = 119, DQM1 = 107
2644 19:22:29.161901 DQ Delay:
2645 19:22:29.164803 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2646 19:22:29.168406 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =123
2647 19:22:29.172036 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2648 19:22:29.174863 DQ12 =119, DQ13 =111, DQ14 =115, DQ15 =111
2649 19:22:29.174934
2650 19:22:29.174998
2651 19:22:29.175056 ==
2652 19:22:29.178312 Dram Type= 6, Freq= 0, CH_0, rank 0
2653 19:22:29.181903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2654 19:22:29.185297 ==
2655 19:22:29.185370
2656 19:22:29.185433
2657 19:22:29.185491 TX Vref Scan disable
2658 19:22:29.188583 == TX Byte 0 ==
2659 19:22:29.191601 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2660 19:22:29.195245 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2661 19:22:29.198253 == TX Byte 1 ==
2662 19:22:29.201697 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2663 19:22:29.205155 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2664 19:22:29.205235 ==
2665 19:22:29.208204 Dram Type= 6, Freq= 0, CH_0, rank 0
2666 19:22:29.214703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2667 19:22:29.214805 ==
2668 19:22:29.225952 TX Vref=22, minBit 3, minWin=24, winSum=408
2669 19:22:29.229936 TX Vref=24, minBit 7, minWin=25, winSum=418
2670 19:22:29.232642 TX Vref=26, minBit 1, minWin=25, winSum=421
2671 19:22:29.236063 TX Vref=28, minBit 0, minWin=26, winSum=428
2672 19:22:29.239489 TX Vref=30, minBit 3, minWin=26, winSum=429
2673 19:22:29.245900 TX Vref=32, minBit 0, minWin=26, winSum=429
2674 19:22:29.249388 [TxChooseVref] Worse bit 3, Min win 26, Win sum 429, Final Vref 30
2675 19:22:29.249496
2676 19:22:29.252319 Final TX Range 1 Vref 30
2677 19:22:29.252394
2678 19:22:29.252455 ==
2679 19:22:29.255894 Dram Type= 6, Freq= 0, CH_0, rank 0
2680 19:22:29.258816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2681 19:22:29.262174 ==
2682 19:22:29.262249
2683 19:22:29.262312
2684 19:22:29.262375 TX Vref Scan disable
2685 19:22:29.265850 == TX Byte 0 ==
2686 19:22:29.269001 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2687 19:22:29.275781 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2688 19:22:29.275895 == TX Byte 1 ==
2689 19:22:29.279236 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2690 19:22:29.285613 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2691 19:22:29.285693
2692 19:22:29.285758 [DATLAT]
2693 19:22:29.285818 Freq=1200, CH0 RK0
2694 19:22:29.285881
2695 19:22:29.289022 DATLAT Default: 0xd
2696 19:22:29.289121 0, 0xFFFF, sum = 0
2697 19:22:29.292405 1, 0xFFFF, sum = 0
2698 19:22:29.295851 2, 0xFFFF, sum = 0
2699 19:22:29.295993 3, 0xFFFF, sum = 0
2700 19:22:29.298841 4, 0xFFFF, sum = 0
2701 19:22:29.298972 5, 0xFFFF, sum = 0
2702 19:22:29.302345 6, 0xFFFF, sum = 0
2703 19:22:29.302447 7, 0xFFFF, sum = 0
2704 19:22:29.305314 8, 0xFFFF, sum = 0
2705 19:22:29.305413 9, 0xFFFF, sum = 0
2706 19:22:29.308737 10, 0xFFFF, sum = 0
2707 19:22:29.308823 11, 0xFFFF, sum = 0
2708 19:22:29.312381 12, 0x0, sum = 1
2709 19:22:29.312467 13, 0x0, sum = 2
2710 19:22:29.315263 14, 0x0, sum = 3
2711 19:22:29.315354 15, 0x0, sum = 4
2712 19:22:29.318842 best_step = 13
2713 19:22:29.318952
2714 19:22:29.319018 ==
2715 19:22:29.321875 Dram Type= 6, Freq= 0, CH_0, rank 0
2716 19:22:29.325380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2717 19:22:29.325478 ==
2718 19:22:29.328339 RX Vref Scan: 1
2719 19:22:29.328415
2720 19:22:29.328476 Set Vref Range= 32 -> 127
2721 19:22:29.328536
2722 19:22:29.331942 RX Vref 32 -> 127, step: 1
2723 19:22:29.332043
2724 19:22:29.334884 RX Delay -21 -> 252, step: 4
2725 19:22:29.334959
2726 19:22:29.338355 Set Vref, RX VrefLevel [Byte0]: 32
2727 19:22:29.341704 [Byte1]: 32
2728 19:22:29.341809
2729 19:22:29.344872 Set Vref, RX VrefLevel [Byte0]: 33
2730 19:22:29.348358 [Byte1]: 33
2731 19:22:29.352566
2732 19:22:29.352644 Set Vref, RX VrefLevel [Byte0]: 34
2733 19:22:29.355845 [Byte1]: 34
2734 19:22:29.360110
2735 19:22:29.360188 Set Vref, RX VrefLevel [Byte0]: 35
2736 19:22:29.363636 [Byte1]: 35
2737 19:22:29.368228
2738 19:22:29.368302 Set Vref, RX VrefLevel [Byte0]: 36
2739 19:22:29.371232 [Byte1]: 36
2740 19:22:29.375872
2741 19:22:29.376015 Set Vref, RX VrefLevel [Byte0]: 37
2742 19:22:29.379263 [Byte1]: 37
2743 19:22:29.383820
2744 19:22:29.383965 Set Vref, RX VrefLevel [Byte0]: 38
2745 19:22:29.387149 [Byte1]: 38
2746 19:22:29.391851
2747 19:22:29.391982 Set Vref, RX VrefLevel [Byte0]: 39
2748 19:22:29.395132 [Byte1]: 39
2749 19:22:29.400126
2750 19:22:29.400205 Set Vref, RX VrefLevel [Byte0]: 40
2751 19:22:29.403344 [Byte1]: 40
2752 19:22:29.407843
2753 19:22:29.407968 Set Vref, RX VrefLevel [Byte0]: 41
2754 19:22:29.411302 [Byte1]: 41
2755 19:22:29.415503
2756 19:22:29.415606 Set Vref, RX VrefLevel [Byte0]: 42
2757 19:22:29.419099 [Byte1]: 42
2758 19:22:29.423815
2759 19:22:29.423925 Set Vref, RX VrefLevel [Byte0]: 43
2760 19:22:29.426815 [Byte1]: 43
2761 19:22:29.431688
2762 19:22:29.431795 Set Vref, RX VrefLevel [Byte0]: 44
2763 19:22:29.434621 [Byte1]: 44
2764 19:22:29.439356
2765 19:22:29.439458 Set Vref, RX VrefLevel [Byte0]: 45
2766 19:22:29.442941 [Byte1]: 45
2767 19:22:29.447686
2768 19:22:29.447800 Set Vref, RX VrefLevel [Byte0]: 46
2769 19:22:29.450680 [Byte1]: 46
2770 19:22:29.455409
2771 19:22:29.455590 Set Vref, RX VrefLevel [Byte0]: 47
2772 19:22:29.458697 [Byte1]: 47
2773 19:22:29.463147
2774 19:22:29.463300 Set Vref, RX VrefLevel [Byte0]: 48
2775 19:22:29.466602 [Byte1]: 48
2776 19:22:29.471479
2777 19:22:29.471632 Set Vref, RX VrefLevel [Byte0]: 49
2778 19:22:29.474398 [Byte1]: 49
2779 19:22:29.479254
2780 19:22:29.479356 Set Vref, RX VrefLevel [Byte0]: 50
2781 19:22:29.482231 [Byte1]: 50
2782 19:22:29.487077
2783 19:22:29.487220 Set Vref, RX VrefLevel [Byte0]: 51
2784 19:22:29.490362 [Byte1]: 51
2785 19:22:29.494843
2786 19:22:29.494990 Set Vref, RX VrefLevel [Byte0]: 52
2787 19:22:29.498488 [Byte1]: 52
2788 19:22:29.502805
2789 19:22:29.502923 Set Vref, RX VrefLevel [Byte0]: 53
2790 19:22:29.506216 [Byte1]: 53
2791 19:22:29.510774
2792 19:22:29.510882 Set Vref, RX VrefLevel [Byte0]: 54
2793 19:22:29.514304 [Byte1]: 54
2794 19:22:29.518574
2795 19:22:29.518674 Set Vref, RX VrefLevel [Byte0]: 55
2796 19:22:29.522333 [Byte1]: 55
2797 19:22:29.526874
2798 19:22:29.526976 Set Vref, RX VrefLevel [Byte0]: 56
2799 19:22:29.530255 [Byte1]: 56
2800 19:22:29.534368
2801 19:22:29.537870 Set Vref, RX VrefLevel [Byte0]: 57
2802 19:22:29.540897 [Byte1]: 57
2803 19:22:29.540985
2804 19:22:29.544336 Set Vref, RX VrefLevel [Byte0]: 58
2805 19:22:29.548040 [Byte1]: 58
2806 19:22:29.548115
2807 19:22:29.550928 Set Vref, RX VrefLevel [Byte0]: 59
2808 19:22:29.554510 [Byte1]: 59
2809 19:22:29.558629
2810 19:22:29.558704 Set Vref, RX VrefLevel [Byte0]: 60
2811 19:22:29.561601 [Byte1]: 60
2812 19:22:29.566245
2813 19:22:29.566334 Set Vref, RX VrefLevel [Byte0]: 61
2814 19:22:29.569966 [Byte1]: 61
2815 19:22:29.574409
2816 19:22:29.574534 Set Vref, RX VrefLevel [Byte0]: 62
2817 19:22:29.577880 [Byte1]: 62
2818 19:22:29.582020
2819 19:22:29.582097 Set Vref, RX VrefLevel [Byte0]: 63
2820 19:22:29.585594 [Byte1]: 63
2821 19:22:29.590367
2822 19:22:29.590472 Set Vref, RX VrefLevel [Byte0]: 64
2823 19:22:29.593394 [Byte1]: 64
2824 19:22:29.598172
2825 19:22:29.598288 Set Vref, RX VrefLevel [Byte0]: 65
2826 19:22:29.601087 [Byte1]: 65
2827 19:22:29.605766
2828 19:22:29.605869 Set Vref, RX VrefLevel [Byte0]: 66
2829 19:22:29.609193 [Byte1]: 66
2830 19:22:29.613705
2831 19:22:29.613879 Set Vref, RX VrefLevel [Byte0]: 67
2832 19:22:29.616924 [Byte1]: 67
2833 19:22:29.621778
2834 19:22:29.621879 Set Vref, RX VrefLevel [Byte0]: 68
2835 19:22:29.625133 [Byte1]: 68
2836 19:22:29.629971
2837 19:22:29.630073 Final RX Vref Byte 0 = 58 to rank0
2838 19:22:29.633317 Final RX Vref Byte 1 = 49 to rank0
2839 19:22:29.636120 Final RX Vref Byte 0 = 58 to rank1
2840 19:22:29.639867 Final RX Vref Byte 1 = 49 to rank1==
2841 19:22:29.642868 Dram Type= 6, Freq= 0, CH_0, rank 0
2842 19:22:29.649161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2843 19:22:29.649254 ==
2844 19:22:29.649320 DQS Delay:
2845 19:22:29.652870 DQS0 = 0, DQS1 = 0
2846 19:22:29.652970 DQM Delay:
2847 19:22:29.655859 DQM0 = 119, DQM1 = 106
2848 19:22:29.655999 DQ Delay:
2849 19:22:29.659451 DQ0 =118, DQ1 =118, DQ2 =116, DQ3 =116
2850 19:22:29.662443 DQ4 =122, DQ5 =114, DQ6 =128, DQ7 =122
2851 19:22:29.666201 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =100
2852 19:22:29.669081 DQ12 =116, DQ13 =110, DQ14 =116, DQ15 =114
2853 19:22:29.669186
2854 19:22:29.669277
2855 19:22:29.679167 [DQSOSCAuto] RK0, (LSB)MR18= 0x1fc, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 409 ps
2856 19:22:29.679274 CH0 RK0: MR19=403, MR18=1FC
2857 19:22:29.685764 CH0_RK0: MR19=0x403, MR18=0x1FC, DQSOSC=409, MR23=63, INC=39, DEC=26
2858 19:22:29.685850
2859 19:22:29.688938 ----->DramcWriteLeveling(PI) begin...
2860 19:22:29.689042 ==
2861 19:22:29.692455 Dram Type= 6, Freq= 0, CH_0, rank 1
2862 19:22:29.698947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2863 19:22:29.699026 ==
2864 19:22:29.702514 Write leveling (Byte 0): 33 => 33
2865 19:22:29.702627 Write leveling (Byte 1): 24 => 24
2866 19:22:29.705531 DramcWriteLeveling(PI) end<-----
2867 19:22:29.705627
2868 19:22:29.708957 ==
2869 19:22:29.709028 Dram Type= 6, Freq= 0, CH_0, rank 1
2870 19:22:29.715769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2871 19:22:29.715901 ==
2872 19:22:29.719161 [Gating] SW mode calibration
2873 19:22:29.725333 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2874 19:22:29.728709 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2875 19:22:29.735583 0 15 0 | B1->B0 | 2423 3434 | 1 1 | (0 0) (1 1)
2876 19:22:29.739059 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2877 19:22:29.742442 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2878 19:22:29.748486 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2879 19:22:29.751830 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2880 19:22:29.755304 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2881 19:22:29.762304 0 15 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
2882 19:22:29.765343 0 15 28 | B1->B0 | 3333 2424 | 0 0 | (0 0) (1 1)
2883 19:22:29.768763 1 0 0 | B1->B0 | 2929 2323 | 0 0 | (0 1) (0 0)
2884 19:22:29.775295 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2885 19:22:29.778920 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2886 19:22:29.781925 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2887 19:22:29.788369 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2888 19:22:29.791539 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2889 19:22:29.795137 1 0 24 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
2890 19:22:29.801583 1 0 28 | B1->B0 | 2a29 4646 | 1 0 | (0 0) (0 0)
2891 19:22:29.805074 1 1 0 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
2892 19:22:29.808556 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2893 19:22:29.815038 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2894 19:22:29.818513 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2895 19:22:29.821858 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2896 19:22:29.825229 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2897 19:22:29.831443 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2898 19:22:29.834713 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
2899 19:22:29.838232 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2900 19:22:29.844720 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2901 19:22:29.848104 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2902 19:22:29.851383 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2903 19:22:29.858073 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2904 19:22:29.861434 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2905 19:22:29.864497 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2906 19:22:29.871273 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2907 19:22:29.875029 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2908 19:22:29.878092 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2909 19:22:29.884770 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2910 19:22:29.887819 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2911 19:22:29.891097 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2912 19:22:29.897658 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2913 19:22:29.901204 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2914 19:22:29.904533 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2915 19:22:29.907936 Total UI for P1: 0, mck2ui 16
2916 19:22:29.911171 best dqsien dly found for B0: ( 1, 3, 22)
2917 19:22:29.917992 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2918 19:22:29.920964 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2919 19:22:29.924718 Total UI for P1: 0, mck2ui 16
2920 19:22:29.928010 best dqsien dly found for B1: ( 1, 3, 30)
2921 19:22:29.930855 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
2922 19:22:29.934302 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2923 19:22:29.934402
2924 19:22:29.937836 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
2925 19:22:29.941215 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2926 19:22:29.944334 [Gating] SW calibration Done
2927 19:22:29.944414 ==
2928 19:22:29.948023 Dram Type= 6, Freq= 0, CH_0, rank 1
2929 19:22:29.951229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2930 19:22:29.954298 ==
2931 19:22:29.954377 RX Vref Scan: 0
2932 19:22:29.954441
2933 19:22:29.957681 RX Vref 0 -> 0, step: 1
2934 19:22:29.957774
2935 19:22:29.960681 RX Delay -40 -> 252, step: 8
2936 19:22:29.964208 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
2937 19:22:29.967598 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2938 19:22:29.970702 iDelay=200, Bit 2, Center 115 (48 ~ 183) 136
2939 19:22:29.974328 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2940 19:22:29.980595 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2941 19:22:29.984299 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2942 19:22:29.987243 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2943 19:22:29.990999 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2944 19:22:29.994044 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2945 19:22:29.997158 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2946 19:22:30.004013 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2947 19:22:30.007649 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2948 19:22:30.010914 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2949 19:22:30.014364 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2950 19:22:30.020695 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2951 19:22:30.023779 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2952 19:22:30.023859 ==
2953 19:22:30.027991 Dram Type= 6, Freq= 0, CH_0, rank 1
2954 19:22:30.030640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2955 19:22:30.030720 ==
2956 19:22:30.030784 DQS Delay:
2957 19:22:30.034037 DQS0 = 0, DQS1 = 0
2958 19:22:30.034117 DQM Delay:
2959 19:22:30.037387 DQM0 = 119, DQM1 = 107
2960 19:22:30.037467 DQ Delay:
2961 19:22:30.040927 DQ0 =115, DQ1 =119, DQ2 =115, DQ3 =115
2962 19:22:30.043816 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2963 19:22:30.047360 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2964 19:22:30.050697 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =115
2965 19:22:30.053770
2966 19:22:30.053849
2967 19:22:30.053913 ==
2968 19:22:30.057494 Dram Type= 6, Freq= 0, CH_0, rank 1
2969 19:22:30.060420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2970 19:22:30.060538 ==
2971 19:22:30.060603
2972 19:22:30.060661
2973 19:22:30.063838 TX Vref Scan disable
2974 19:22:30.063957 == TX Byte 0 ==
2975 19:22:30.070210 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2976 19:22:30.073730 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2977 19:22:30.073810 == TX Byte 1 ==
2978 19:22:30.080557 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2979 19:22:30.083616 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2980 19:22:30.083748 ==
2981 19:22:30.087365 Dram Type= 6, Freq= 0, CH_0, rank 1
2982 19:22:30.090443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2983 19:22:30.090526 ==
2984 19:22:30.103846 TX Vref=22, minBit 0, minWin=26, winSum=419
2985 19:22:30.106891 TX Vref=24, minBit 0, minWin=26, winSum=419
2986 19:22:30.110591 TX Vref=26, minBit 1, minWin=26, winSum=428
2987 19:22:30.113689 TX Vref=28, minBit 10, minWin=26, winSum=431
2988 19:22:30.117056 TX Vref=30, minBit 5, minWin=26, winSum=430
2989 19:22:30.120515 TX Vref=32, minBit 5, minWin=26, winSum=430
2990 19:22:30.127215 [TxChooseVref] Worse bit 10, Min win 26, Win sum 431, Final Vref 28
2991 19:22:30.127297
2992 19:22:30.130518 Final TX Range 1 Vref 28
2993 19:22:30.130598
2994 19:22:30.130661 ==
2995 19:22:30.133729 Dram Type= 6, Freq= 0, CH_0, rank 1
2996 19:22:30.137048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2997 19:22:30.137128 ==
2998 19:22:30.140070
2999 19:22:30.140148
3000 19:22:30.140213 TX Vref Scan disable
3001 19:22:30.143457 == TX Byte 0 ==
3002 19:22:30.146819 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3003 19:22:30.153715 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3004 19:22:30.153798 == TX Byte 1 ==
3005 19:22:30.157201 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3006 19:22:30.163289 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3007 19:22:30.163366
3008 19:22:30.163434 [DATLAT]
3009 19:22:30.163496 Freq=1200, CH0 RK1
3010 19:22:30.163555
3011 19:22:30.167051 DATLAT Default: 0xd
3012 19:22:30.167144 0, 0xFFFF, sum = 0
3013 19:22:30.170017 1, 0xFFFF, sum = 0
3014 19:22:30.170118 2, 0xFFFF, sum = 0
3015 19:22:30.173481 3, 0xFFFF, sum = 0
3016 19:22:30.176985 4, 0xFFFF, sum = 0
3017 19:22:30.177054 5, 0xFFFF, sum = 0
3018 19:22:30.179857 6, 0xFFFF, sum = 0
3019 19:22:30.179978 7, 0xFFFF, sum = 0
3020 19:22:30.183563 8, 0xFFFF, sum = 0
3021 19:22:30.183644 9, 0xFFFF, sum = 0
3022 19:22:30.186680 10, 0xFFFF, sum = 0
3023 19:22:30.186761 11, 0xFFFF, sum = 0
3024 19:22:30.190400 12, 0x0, sum = 1
3025 19:22:30.190480 13, 0x0, sum = 2
3026 19:22:30.193526 14, 0x0, sum = 3
3027 19:22:30.193620 15, 0x0, sum = 4
3028 19:22:30.193688 best_step = 13
3029 19:22:30.197059
3030 19:22:30.197138 ==
3031 19:22:30.200214 Dram Type= 6, Freq= 0, CH_0, rank 1
3032 19:22:30.203283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3033 19:22:30.203383 ==
3034 19:22:30.203474 RX Vref Scan: 0
3035 19:22:30.203569
3036 19:22:30.206893 RX Vref 0 -> 0, step: 1
3037 19:22:30.206989
3038 19:22:30.210003 RX Delay -21 -> 252, step: 4
3039 19:22:30.213625 iDelay=195, Bit 0, Center 116 (51 ~ 182) 132
3040 19:22:30.220326 iDelay=195, Bit 1, Center 118 (51 ~ 186) 136
3041 19:22:30.223621 iDelay=195, Bit 2, Center 114 (51 ~ 178) 128
3042 19:22:30.226469 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3043 19:22:30.230281 iDelay=195, Bit 4, Center 120 (59 ~ 182) 124
3044 19:22:30.233477 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3045 19:22:30.240056 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3046 19:22:30.243416 iDelay=195, Bit 7, Center 122 (55 ~ 190) 136
3047 19:22:30.246759 iDelay=195, Bit 8, Center 96 (27 ~ 166) 140
3048 19:22:30.249869 iDelay=195, Bit 9, Center 94 (27 ~ 162) 136
3049 19:22:30.253039 iDelay=195, Bit 10, Center 108 (43 ~ 174) 132
3050 19:22:30.259858 iDelay=195, Bit 11, Center 98 (31 ~ 166) 136
3051 19:22:30.263114 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3052 19:22:30.266425 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
3053 19:22:30.270430 iDelay=195, Bit 14, Center 120 (55 ~ 186) 132
3054 19:22:30.272943 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3055 19:22:30.276663 ==
3056 19:22:30.276738 Dram Type= 6, Freq= 0, CH_0, rank 1
3057 19:22:30.282858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3058 19:22:30.282938 ==
3059 19:22:30.283009 DQS Delay:
3060 19:22:30.286182 DQS0 = 0, DQS1 = 0
3061 19:22:30.286286 DQM Delay:
3062 19:22:30.289529 DQM0 = 118, DQM1 = 106
3063 19:22:30.289630 DQ Delay:
3064 19:22:30.293183 DQ0 =116, DQ1 =118, DQ2 =114, DQ3 =114
3065 19:22:30.296215 DQ4 =120, DQ5 =114, DQ6 =128, DQ7 =122
3066 19:22:30.299750 DQ8 =96, DQ9 =94, DQ10 =108, DQ11 =98
3067 19:22:30.302903 DQ12 =112, DQ13 =112, DQ14 =120, DQ15 =114
3068 19:22:30.303009
3069 19:22:30.303130
3070 19:22:30.312702 [DQSOSCAuto] RK1, (LSB)MR18= 0x200, (MSB)MR19= 0x404, tDQSOscB0 = 410 ps tDQSOscB1 = 409 ps
3071 19:22:30.312785 CH0 RK1: MR19=404, MR18=200
3072 19:22:30.319329 CH0_RK1: MR19=0x404, MR18=0x200, DQSOSC=409, MR23=63, INC=39, DEC=26
3073 19:22:30.322915 [RxdqsGatingPostProcess] freq 1200
3074 19:22:30.329732 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3075 19:22:30.332593 best DQS0 dly(2T, 0.5T) = (0, 11)
3076 19:22:30.336117 best DQS1 dly(2T, 0.5T) = (0, 11)
3077 19:22:30.339152 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3078 19:22:30.342918 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3079 19:22:30.345882 best DQS0 dly(2T, 0.5T) = (0, 11)
3080 19:22:30.345960 best DQS1 dly(2T, 0.5T) = (0, 11)
3081 19:22:30.349509 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3082 19:22:30.352909 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3083 19:22:30.355747 Pre-setting of DQS Precalculation
3084 19:22:30.362883 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3085 19:22:30.362954 ==
3086 19:22:30.365887 Dram Type= 6, Freq= 0, CH_1, rank 0
3087 19:22:30.369228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3088 19:22:30.369325 ==
3089 19:22:30.375792 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3090 19:22:30.382495 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3091 19:22:30.389791 [CA 0] Center 38 (8~68) winsize 61
3092 19:22:30.393087 [CA 1] Center 37 (7~68) winsize 62
3093 19:22:30.396575 [CA 2] Center 35 (5~65) winsize 61
3094 19:22:30.399736 [CA 3] Center 34 (4~64) winsize 61
3095 19:22:30.403255 [CA 4] Center 34 (4~64) winsize 61
3096 19:22:30.406287 [CA 5] Center 33 (4~63) winsize 60
3097 19:22:30.406392
3098 19:22:30.409318 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3099 19:22:30.409415
3100 19:22:30.413059 [CATrainingPosCal] consider 1 rank data
3101 19:22:30.416111 u2DelayCellTimex100 = 270/100 ps
3102 19:22:30.420146 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3103 19:22:30.422839 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3104 19:22:30.429495 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3105 19:22:30.433165 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3106 19:22:30.436079 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3107 19:22:30.439766 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3108 19:22:30.439851
3109 19:22:30.442810 CA PerBit enable=1, Macro0, CA PI delay=33
3110 19:22:30.442904
3111 19:22:30.445894 [CBTSetCACLKResult] CA Dly = 33
3112 19:22:30.445967 CS Dly: 5 (0~36)
3113 19:22:30.449666 ==
3114 19:22:30.449734 Dram Type= 6, Freq= 0, CH_1, rank 1
3115 19:22:30.456206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3116 19:22:30.456275 ==
3117 19:22:30.459132 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3118 19:22:30.466003 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3119 19:22:30.475404 [CA 0] Center 37 (7~68) winsize 62
3120 19:22:30.478564 [CA 1] Center 38 (8~68) winsize 61
3121 19:22:30.481942 [CA 2] Center 35 (5~65) winsize 61
3122 19:22:30.485360 [CA 3] Center 33 (3~64) winsize 62
3123 19:22:30.488710 [CA 4] Center 34 (4~64) winsize 61
3124 19:22:30.492094 [CA 5] Center 33 (3~64) winsize 62
3125 19:22:30.492173
3126 19:22:30.495169 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3127 19:22:30.495249
3128 19:22:30.498353 [CATrainingPosCal] consider 2 rank data
3129 19:22:30.501942 u2DelayCellTimex100 = 270/100 ps
3130 19:22:30.505147 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3131 19:22:30.508562 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3132 19:22:30.515342 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3133 19:22:30.518517 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3134 19:22:30.521584 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3135 19:22:30.525150 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3136 19:22:30.525221
3137 19:22:30.528866 CA PerBit enable=1, Macro0, CA PI delay=33
3138 19:22:30.528943
3139 19:22:30.531720 [CBTSetCACLKResult] CA Dly = 33
3140 19:22:30.531816 CS Dly: 6 (0~39)
3141 19:22:30.531921
3142 19:22:30.538305 ----->DramcWriteLeveling(PI) begin...
3143 19:22:30.538403 ==
3144 19:22:30.541534 Dram Type= 6, Freq= 0, CH_1, rank 0
3145 19:22:30.544890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3146 19:22:30.544982 ==
3147 19:22:30.548508 Write leveling (Byte 0): 25 => 25
3148 19:22:30.551604 Write leveling (Byte 1): 28 => 28
3149 19:22:30.554689 DramcWriteLeveling(PI) end<-----
3150 19:22:30.554758
3151 19:22:30.554816 ==
3152 19:22:30.558359 Dram Type= 6, Freq= 0, CH_1, rank 0
3153 19:22:30.561398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3154 19:22:30.561494 ==
3155 19:22:30.564895 [Gating] SW mode calibration
3156 19:22:30.571319 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3157 19:22:30.577679 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3158 19:22:30.581360 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3159 19:22:30.584882 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3160 19:22:30.591378 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3161 19:22:30.594732 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3162 19:22:30.597640 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3163 19:22:30.604761 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3164 19:22:30.607993 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 0)
3165 19:22:30.611230 0 15 28 | B1->B0 | 2a2a 2424 | 0 0 | (1 0) (0 0)
3166 19:22:30.618017 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3167 19:22:30.620870 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3168 19:22:30.624380 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3169 19:22:30.631060 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3170 19:22:30.634078 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3171 19:22:30.637624 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3172 19:22:30.644283 1 0 24 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
3173 19:22:30.647799 1 0 28 | B1->B0 | 4444 4646 | 1 0 | (0 0) (0 0)
3174 19:22:30.650878 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3175 19:22:30.657627 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3176 19:22:30.660552 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3177 19:22:30.664155 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3178 19:22:30.670683 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3179 19:22:30.674225 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3180 19:22:30.677314 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3181 19:22:30.680676 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3182 19:22:30.687571 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3183 19:22:30.690931 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3184 19:22:30.693819 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3185 19:22:30.700612 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3186 19:22:30.704317 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3187 19:22:30.707523 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3188 19:22:30.713930 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3189 19:22:30.717491 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3190 19:22:30.720472 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3191 19:22:30.727243 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3192 19:22:30.730632 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3193 19:22:30.733684 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3194 19:22:30.740346 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3195 19:22:30.743483 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3196 19:22:30.747107 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3197 19:22:30.753865 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3198 19:22:30.753946 Total UI for P1: 0, mck2ui 16
3199 19:22:30.760533 best dqsien dly found for B0: ( 1, 3, 24)
3200 19:22:30.763576 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3201 19:22:30.766734 Total UI for P1: 0, mck2ui 16
3202 19:22:30.770450 best dqsien dly found for B1: ( 1, 3, 28)
3203 19:22:30.773806 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3204 19:22:30.776849 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3205 19:22:30.776930
3206 19:22:30.780543 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3207 19:22:30.783675 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3208 19:22:30.786655 [Gating] SW calibration Done
3209 19:22:30.786734 ==
3210 19:22:30.790245 Dram Type= 6, Freq= 0, CH_1, rank 0
3211 19:22:30.793520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3212 19:22:30.797047 ==
3213 19:22:30.797152 RX Vref Scan: 0
3214 19:22:30.797245
3215 19:22:30.800300 RX Vref 0 -> 0, step: 1
3216 19:22:30.800380
3217 19:22:30.800444 RX Delay -40 -> 252, step: 8
3218 19:22:30.807333 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3219 19:22:30.810579 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3220 19:22:30.813508 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3221 19:22:30.816882 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3222 19:22:30.820469 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3223 19:22:30.827049 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3224 19:22:30.830517 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3225 19:22:30.833510 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3226 19:22:30.836881 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3227 19:22:30.840341 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3228 19:22:30.846823 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3229 19:22:30.849968 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3230 19:22:30.853469 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3231 19:22:30.856511 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3232 19:22:30.863231 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3233 19:22:30.866916 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3234 19:22:30.866996 ==
3235 19:22:30.869929 Dram Type= 6, Freq= 0, CH_1, rank 0
3236 19:22:30.873082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3237 19:22:30.873162 ==
3238 19:22:30.873227 DQS Delay:
3239 19:22:30.876530 DQS0 = 0, DQS1 = 0
3240 19:22:30.876610 DQM Delay:
3241 19:22:30.880215 DQM0 = 115, DQM1 = 112
3242 19:22:30.880295 DQ Delay:
3243 19:22:30.883146 DQ0 =123, DQ1 =111, DQ2 =103, DQ3 =115
3244 19:22:30.886942 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =111
3245 19:22:30.889960 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3246 19:22:30.896730 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3247 19:22:30.896818
3248 19:22:30.896936
3249 19:22:30.897077 ==
3250 19:22:30.899720 Dram Type= 6, Freq= 0, CH_1, rank 0
3251 19:22:30.903443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3252 19:22:30.903553 ==
3253 19:22:30.903646
3254 19:22:30.903734
3255 19:22:30.906765 TX Vref Scan disable
3256 19:22:30.906845 == TX Byte 0 ==
3257 19:22:30.912920 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3258 19:22:30.916117 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3259 19:22:30.916220 == TX Byte 1 ==
3260 19:22:30.923107 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3261 19:22:30.926316 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3262 19:22:30.926424 ==
3263 19:22:30.929664 Dram Type= 6, Freq= 0, CH_1, rank 0
3264 19:22:30.932718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3265 19:22:30.932824 ==
3266 19:22:30.945200 TX Vref=22, minBit 0, minWin=25, winSum=412
3267 19:22:30.948651 TX Vref=24, minBit 11, minWin=25, winSum=420
3268 19:22:30.952331 TX Vref=26, minBit 2, minWin=25, winSum=422
3269 19:22:30.955396 TX Vref=28, minBit 3, minWin=26, winSum=429
3270 19:22:30.958915 TX Vref=30, minBit 3, minWin=26, winSum=426
3271 19:22:30.965140 TX Vref=32, minBit 10, minWin=26, winSum=428
3272 19:22:30.968741 [TxChooseVref] Worse bit 3, Min win 26, Win sum 429, Final Vref 28
3273 19:22:30.968859
3274 19:22:30.971820 Final TX Range 1 Vref 28
3275 19:22:30.971950
3276 19:22:30.972063 ==
3277 19:22:30.975486 Dram Type= 6, Freq= 0, CH_1, rank 0
3278 19:22:30.978593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3279 19:22:30.981438 ==
3280 19:22:30.981531
3281 19:22:30.981617
3282 19:22:30.981705 TX Vref Scan disable
3283 19:22:30.985151 == TX Byte 0 ==
3284 19:22:30.988751 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3285 19:22:30.995514 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3286 19:22:30.995594 == TX Byte 1 ==
3287 19:22:30.998489 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3288 19:22:31.005101 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3289 19:22:31.005183
3290 19:22:31.005247 [DATLAT]
3291 19:22:31.005307 Freq=1200, CH1 RK0
3292 19:22:31.005365
3293 19:22:31.008635 DATLAT Default: 0xd
3294 19:22:31.008715 0, 0xFFFF, sum = 0
3295 19:22:31.011794 1, 0xFFFF, sum = 0
3296 19:22:31.014863 2, 0xFFFF, sum = 0
3297 19:22:31.014944 3, 0xFFFF, sum = 0
3298 19:22:31.018163 4, 0xFFFF, sum = 0
3299 19:22:31.018244 5, 0xFFFF, sum = 0
3300 19:22:31.021660 6, 0xFFFF, sum = 0
3301 19:22:31.021742 7, 0xFFFF, sum = 0
3302 19:22:31.025166 8, 0xFFFF, sum = 0
3303 19:22:31.025249 9, 0xFFFF, sum = 0
3304 19:22:31.028456 10, 0xFFFF, sum = 0
3305 19:22:31.028552 11, 0xFFFF, sum = 0
3306 19:22:31.031478 12, 0x0, sum = 1
3307 19:22:31.031560 13, 0x0, sum = 2
3308 19:22:31.034654 14, 0x0, sum = 3
3309 19:22:31.034736 15, 0x0, sum = 4
3310 19:22:31.038145 best_step = 13
3311 19:22:31.038225
3312 19:22:31.038289 ==
3313 19:22:31.041521 Dram Type= 6, Freq= 0, CH_1, rank 0
3314 19:22:31.044998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3315 19:22:31.045079 ==
3316 19:22:31.045143 RX Vref Scan: 1
3317 19:22:31.048351
3318 19:22:31.048441 Set Vref Range= 32 -> 127
3319 19:22:31.048541
3320 19:22:31.051536 RX Vref 32 -> 127, step: 1
3321 19:22:31.051616
3322 19:22:31.055041 RX Delay -13 -> 252, step: 4
3323 19:22:31.055121
3324 19:22:31.058576 Set Vref, RX VrefLevel [Byte0]: 32
3325 19:22:31.061376 [Byte1]: 32
3326 19:22:31.061456
3327 19:22:31.064840 Set Vref, RX VrefLevel [Byte0]: 33
3328 19:22:31.067850 [Byte1]: 33
3329 19:22:31.071622
3330 19:22:31.071702 Set Vref, RX VrefLevel [Byte0]: 34
3331 19:22:31.075269 [Byte1]: 34
3332 19:22:31.079567
3333 19:22:31.079647 Set Vref, RX VrefLevel [Byte0]: 35
3334 19:22:31.083300 [Byte1]: 35
3335 19:22:31.087337
3336 19:22:31.087416 Set Vref, RX VrefLevel [Byte0]: 36
3337 19:22:31.090908 [Byte1]: 36
3338 19:22:31.095195
3339 19:22:31.095274 Set Vref, RX VrefLevel [Byte0]: 37
3340 19:22:31.098824 [Byte1]: 37
3341 19:22:31.103146
3342 19:22:31.103227 Set Vref, RX VrefLevel [Byte0]: 38
3343 19:22:31.106711 [Byte1]: 38
3344 19:22:31.110882
3345 19:22:31.110962 Set Vref, RX VrefLevel [Byte0]: 39
3346 19:22:31.114710 [Byte1]: 39
3347 19:22:31.119282
3348 19:22:31.119361 Set Vref, RX VrefLevel [Byte0]: 40
3349 19:22:31.122663 [Byte1]: 40
3350 19:22:31.126829
3351 19:22:31.126909 Set Vref, RX VrefLevel [Byte0]: 41
3352 19:22:31.130338 [Byte1]: 41
3353 19:22:31.135071
3354 19:22:31.135151 Set Vref, RX VrefLevel [Byte0]: 42
3355 19:22:31.137953 [Byte1]: 42
3356 19:22:31.142852
3357 19:22:31.142935 Set Vref, RX VrefLevel [Byte0]: 43
3358 19:22:31.149109 [Byte1]: 43
3359 19:22:31.149189
3360 19:22:31.152245 Set Vref, RX VrefLevel [Byte0]: 44
3361 19:22:31.155739 [Byte1]: 44
3362 19:22:31.155819
3363 19:22:31.159206 Set Vref, RX VrefLevel [Byte0]: 45
3364 19:22:31.162512 [Byte1]: 45
3365 19:22:31.166226
3366 19:22:31.166305 Set Vref, RX VrefLevel [Byte0]: 46
3367 19:22:31.169797 [Byte1]: 46
3368 19:22:31.174012
3369 19:22:31.174092 Set Vref, RX VrefLevel [Byte0]: 47
3370 19:22:31.177759 [Byte1]: 47
3371 19:22:31.181894
3372 19:22:31.181974 Set Vref, RX VrefLevel [Byte0]: 48
3373 19:22:31.185517 [Byte1]: 48
3374 19:22:31.190135
3375 19:22:31.190214 Set Vref, RX VrefLevel [Byte0]: 49
3376 19:22:31.193275 [Byte1]: 49
3377 19:22:31.198083
3378 19:22:31.198163 Set Vref, RX VrefLevel [Byte0]: 50
3379 19:22:31.201194 [Byte1]: 50
3380 19:22:31.205467
3381 19:22:31.205547 Set Vref, RX VrefLevel [Byte0]: 51
3382 19:22:31.209196 [Byte1]: 51
3383 19:22:31.213789
3384 19:22:31.213869 Set Vref, RX VrefLevel [Byte0]: 52
3385 19:22:31.216916 [Byte1]: 52
3386 19:22:31.221733
3387 19:22:31.221812 Set Vref, RX VrefLevel [Byte0]: 53
3388 19:22:31.224806 [Byte1]: 53
3389 19:22:31.229005
3390 19:22:31.229086 Set Vref, RX VrefLevel [Byte0]: 54
3391 19:22:31.232937 [Byte1]: 54
3392 19:22:31.237479
3393 19:22:31.237560 Set Vref, RX VrefLevel [Byte0]: 55
3394 19:22:31.240516 [Byte1]: 55
3395 19:22:31.244768
3396 19:22:31.244848 Set Vref, RX VrefLevel [Byte0]: 56
3397 19:22:31.248375 [Byte1]: 56
3398 19:22:31.252940
3399 19:22:31.253021 Set Vref, RX VrefLevel [Byte0]: 57
3400 19:22:31.256250 [Byte1]: 57
3401 19:22:31.261101
3402 19:22:31.261221 Set Vref, RX VrefLevel [Byte0]: 58
3403 19:22:31.264130 [Byte1]: 58
3404 19:22:31.268909
3405 19:22:31.268989 Set Vref, RX VrefLevel [Byte0]: 59
3406 19:22:31.272453 [Byte1]: 59
3407 19:22:31.276512
3408 19:22:31.276592 Set Vref, RX VrefLevel [Byte0]: 60
3409 19:22:31.279856 [Byte1]: 60
3410 19:22:31.284751
3411 19:22:31.284831 Set Vref, RX VrefLevel [Byte0]: 61
3412 19:22:31.287795 [Byte1]: 61
3413 19:22:31.292593
3414 19:22:31.292673 Set Vref, RX VrefLevel [Byte0]: 62
3415 19:22:31.295699 [Byte1]: 62
3416 19:22:31.300479
3417 19:22:31.300560 Set Vref, RX VrefLevel [Byte0]: 63
3418 19:22:31.303628 [Byte1]: 63
3419 19:22:31.307914
3420 19:22:31.308009 Set Vref, RX VrefLevel [Byte0]: 64
3421 19:22:31.311638 [Byte1]: 64
3422 19:22:31.316200
3423 19:22:31.316309 Final RX Vref Byte 0 = 51 to rank0
3424 19:22:31.319779 Final RX Vref Byte 1 = 51 to rank0
3425 19:22:31.322622 Final RX Vref Byte 0 = 51 to rank1
3426 19:22:31.325715 Final RX Vref Byte 1 = 51 to rank1==
3427 19:22:31.329336 Dram Type= 6, Freq= 0, CH_1, rank 0
3428 19:22:31.336140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3429 19:22:31.336222 ==
3430 19:22:31.336287 DQS Delay:
3431 19:22:31.339165 DQS0 = 0, DQS1 = 0
3432 19:22:31.339246 DQM Delay:
3433 19:22:31.339310 DQM0 = 114, DQM1 = 112
3434 19:22:31.342040 DQ Delay:
3435 19:22:31.345378 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =114
3436 19:22:31.349080 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110
3437 19:22:31.352195 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
3438 19:22:31.355769 DQ12 =120, DQ13 =120, DQ14 =120, DQ15 =120
3439 19:22:31.355875
3440 19:22:31.355984
3441 19:22:31.365513 [DQSOSCAuto] RK0, (LSB)MR18= 0xf804, (MSB)MR19= 0x304, tDQSOscB0 = 408 ps tDQSOscB1 = 413 ps
3442 19:22:31.365595 CH1 RK0: MR19=304, MR18=F804
3443 19:22:31.371791 CH1_RK0: MR19=0x304, MR18=0xF804, DQSOSC=408, MR23=63, INC=39, DEC=26
3444 19:22:31.371935
3445 19:22:31.375509 ----->DramcWriteLeveling(PI) begin...
3446 19:22:31.378549 ==
3447 19:22:31.378630 Dram Type= 6, Freq= 0, CH_1, rank 1
3448 19:22:31.385132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3449 19:22:31.385213 ==
3450 19:22:31.388510 Write leveling (Byte 0): 25 => 25
3451 19:22:31.391711 Write leveling (Byte 1): 29 => 29
3452 19:22:31.395055 DramcWriteLeveling(PI) end<-----
3453 19:22:31.395135
3454 19:22:31.395199 ==
3455 19:22:31.398177 Dram Type= 6, Freq= 0, CH_1, rank 1
3456 19:22:31.401353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3457 19:22:31.401433 ==
3458 19:22:31.404949 [Gating] SW mode calibration
3459 19:22:31.411117 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3460 19:22:31.417877 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3461 19:22:31.421506 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3462 19:22:31.424345 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3463 19:22:31.431295 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3464 19:22:31.434254 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3465 19:22:31.437930 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3466 19:22:31.444310 0 15 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3467 19:22:31.447717 0 15 24 | B1->B0 | 3434 2626 | 1 0 | (1 1) (1 0)
3468 19:22:31.451004 0 15 28 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
3469 19:22:31.457640 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3470 19:22:31.460752 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3471 19:22:31.463825 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3472 19:22:31.470713 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3473 19:22:31.474311 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3474 19:22:31.477663 1 0 20 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
3475 19:22:31.484056 1 0 24 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
3476 19:22:31.487111 1 0 28 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
3477 19:22:31.490611 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3478 19:22:31.497193 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3479 19:22:31.500503 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3480 19:22:31.503632 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3481 19:22:31.510122 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3482 19:22:31.513879 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3483 19:22:31.517040 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3484 19:22:31.523173 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3485 19:22:31.526763 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 19:22:31.529766 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 19:22:31.536929 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 19:22:31.539955 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 19:22:31.543048 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 19:22:31.549704 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 19:22:31.553191 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 19:22:31.556231 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 19:22:31.562802 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 19:22:31.566152 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 19:22:31.569450 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 19:22:31.576055 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3497 19:22:31.579243 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3498 19:22:31.582844 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3499 19:22:31.589090 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3500 19:22:31.592651 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3501 19:22:31.595660 Total UI for P1: 0, mck2ui 16
3502 19:22:31.599190 best dqsien dly found for B0: ( 1, 3, 22)
3503 19:22:31.602225 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3504 19:22:31.605924 Total UI for P1: 0, mck2ui 16
3505 19:22:31.609032 best dqsien dly found for B1: ( 1, 3, 28)
3506 19:22:31.611986 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3507 19:22:31.615523 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3508 19:22:31.615608
3509 19:22:31.622244 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3510 19:22:31.625143 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3511 19:22:31.628883 [Gating] SW calibration Done
3512 19:22:31.628968 ==
3513 19:22:31.632038 Dram Type= 6, Freq= 0, CH_1, rank 1
3514 19:22:31.634934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3515 19:22:31.635018 ==
3516 19:22:31.635103 RX Vref Scan: 0
3517 19:22:31.635184
3518 19:22:31.638385 RX Vref 0 -> 0, step: 1
3519 19:22:31.638468
3520 19:22:31.642049 RX Delay -40 -> 252, step: 8
3521 19:22:31.645162 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3522 19:22:31.648240 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3523 19:22:31.655016 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3524 19:22:31.657976 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3525 19:22:31.661670 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3526 19:22:31.664691 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3527 19:22:31.668196 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3528 19:22:31.674920 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3529 19:22:31.678228 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3530 19:22:31.681132 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3531 19:22:31.684694 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3532 19:22:31.688345 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3533 19:22:31.694649 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3534 19:22:31.697861 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3535 19:22:31.701075 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3536 19:22:31.704546 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3537 19:22:31.704631 ==
3538 19:22:31.707600 Dram Type= 6, Freq= 0, CH_1, rank 1
3539 19:22:31.714312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3540 19:22:31.714397 ==
3541 19:22:31.714483 DQS Delay:
3542 19:22:31.717346 DQS0 = 0, DQS1 = 0
3543 19:22:31.717430 DQM Delay:
3544 19:22:31.721118 DQM0 = 115, DQM1 = 112
3545 19:22:31.721202 DQ Delay:
3546 19:22:31.724088 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3547 19:22:31.727517 DQ4 =115, DQ5 =127, DQ6 =119, DQ7 =115
3548 19:22:31.730614 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3549 19:22:31.734046 DQ12 =123, DQ13 =119, DQ14 =115, DQ15 =119
3550 19:22:31.734130
3551 19:22:31.734231
3552 19:22:31.734329 ==
3553 19:22:31.737409 Dram Type= 6, Freq= 0, CH_1, rank 1
3554 19:22:31.743723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3555 19:22:31.743808 ==
3556 19:22:31.743943
3557 19:22:31.744023
3558 19:22:31.744103 TX Vref Scan disable
3559 19:22:31.747288 == TX Byte 0 ==
3560 19:22:31.750954 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3561 19:22:31.757278 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3562 19:22:31.757364 == TX Byte 1 ==
3563 19:22:31.761006 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3564 19:22:31.767278 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3565 19:22:31.767362 ==
3566 19:22:31.770379 Dram Type= 6, Freq= 0, CH_1, rank 1
3567 19:22:31.773884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3568 19:22:31.773969 ==
3569 19:22:31.785197 TX Vref=22, minBit 1, minWin=25, winSum=419
3570 19:22:31.788545 TX Vref=24, minBit 7, minWin=25, winSum=423
3571 19:22:31.792012 TX Vref=26, minBit 1, minWin=26, winSum=425
3572 19:22:31.795172 TX Vref=28, minBit 2, minWin=26, winSum=433
3573 19:22:31.798766 TX Vref=30, minBit 7, minWin=26, winSum=430
3574 19:22:31.805090 TX Vref=32, minBit 7, minWin=26, winSum=433
3575 19:22:31.808343 [TxChooseVref] Worse bit 2, Min win 26, Win sum 433, Final Vref 28
3576 19:22:31.808432
3577 19:22:31.811411 Final TX Range 1 Vref 28
3578 19:22:31.811534
3579 19:22:31.811637 ==
3580 19:22:31.814890 Dram Type= 6, Freq= 0, CH_1, rank 1
3581 19:22:31.821109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3582 19:22:31.821194 ==
3583 19:22:31.821279
3584 19:22:31.821360
3585 19:22:31.821439 TX Vref Scan disable
3586 19:22:31.824829 == TX Byte 0 ==
3587 19:22:31.828371 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3588 19:22:31.834916 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3589 19:22:31.835031 == TX Byte 1 ==
3590 19:22:31.838004 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3591 19:22:31.845089 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3592 19:22:31.845193
3593 19:22:31.845314 [DATLAT]
3594 19:22:31.845396 Freq=1200, CH1 RK1
3595 19:22:31.845539
3596 19:22:31.848184 DATLAT Default: 0xd
3597 19:22:31.851683 0, 0xFFFF, sum = 0
3598 19:22:31.851784 1, 0xFFFF, sum = 0
3599 19:22:31.854991 2, 0xFFFF, sum = 0
3600 19:22:31.855077 3, 0xFFFF, sum = 0
3601 19:22:31.858247 4, 0xFFFF, sum = 0
3602 19:22:31.858333 5, 0xFFFF, sum = 0
3603 19:22:31.861169 6, 0xFFFF, sum = 0
3604 19:22:31.861255 7, 0xFFFF, sum = 0
3605 19:22:31.864657 8, 0xFFFF, sum = 0
3606 19:22:31.864743 9, 0xFFFF, sum = 0
3607 19:22:31.867757 10, 0xFFFF, sum = 0
3608 19:22:31.867842 11, 0xFFFF, sum = 0
3609 19:22:31.871377 12, 0x0, sum = 1
3610 19:22:31.871463 13, 0x0, sum = 2
3611 19:22:31.874382 14, 0x0, sum = 3
3612 19:22:31.874467 15, 0x0, sum = 4
3613 19:22:31.877860 best_step = 13
3614 19:22:31.877944
3615 19:22:31.878029 ==
3616 19:22:31.880882 Dram Type= 6, Freq= 0, CH_1, rank 1
3617 19:22:31.884473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3618 19:22:31.884558 ==
3619 19:22:31.887625 RX Vref Scan: 0
3620 19:22:31.887738
3621 19:22:31.887841 RX Vref 0 -> 0, step: 1
3622 19:22:31.887964
3623 19:22:31.890553 RX Delay -13 -> 252, step: 4
3624 19:22:31.897263 iDelay=195, Bit 0, Center 116 (47 ~ 186) 140
3625 19:22:31.900737 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3626 19:22:31.903551 iDelay=195, Bit 2, Center 106 (39 ~ 174) 136
3627 19:22:31.907123 iDelay=195, Bit 3, Center 114 (47 ~ 182) 136
3628 19:22:31.913709 iDelay=195, Bit 4, Center 114 (47 ~ 182) 136
3629 19:22:31.917087 iDelay=195, Bit 5, Center 124 (55 ~ 194) 140
3630 19:22:31.920375 iDelay=195, Bit 6, Center 122 (55 ~ 190) 136
3631 19:22:31.923502 iDelay=195, Bit 7, Center 112 (43 ~ 182) 140
3632 19:22:31.926579 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3633 19:22:31.933290 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3634 19:22:31.936865 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3635 19:22:31.939857 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3636 19:22:31.943640 iDelay=195, Bit 12, Center 120 (59 ~ 182) 124
3637 19:22:31.946643 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3638 19:22:31.953413 iDelay=195, Bit 14, Center 116 (55 ~ 178) 124
3639 19:22:31.956430 iDelay=195, Bit 15, Center 122 (59 ~ 186) 128
3640 19:22:31.956512 ==
3641 19:22:31.960014 Dram Type= 6, Freq= 0, CH_1, rank 1
3642 19:22:31.963354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3643 19:22:31.963436 ==
3644 19:22:31.966155 DQS Delay:
3645 19:22:31.966237 DQS0 = 0, DQS1 = 0
3646 19:22:31.969564 DQM Delay:
3647 19:22:31.969645 DQM0 = 115, DQM1 = 112
3648 19:22:31.969711 DQ Delay:
3649 19:22:31.972598 DQ0 =116, DQ1 =112, DQ2 =106, DQ3 =114
3650 19:22:31.979642 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =112
3651 19:22:31.982607 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
3652 19:22:31.986049 DQ12 =120, DQ13 =118, DQ14 =116, DQ15 =122
3653 19:22:31.986131
3654 19:22:31.986195
3655 19:22:31.992725 [DQSOSCAuto] RK1, (LSB)MR18= 0xf90b, (MSB)MR19= 0x304, tDQSOscB0 = 405 ps tDQSOscB1 = 412 ps
3656 19:22:31.995775 CH1 RK1: MR19=304, MR18=F90B
3657 19:22:32.002383 CH1_RK1: MR19=0x304, MR18=0xF90B, DQSOSC=405, MR23=63, INC=39, DEC=26
3658 19:22:32.005781 [RxdqsGatingPostProcess] freq 1200
3659 19:22:32.012427 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3660 19:22:32.015542 best DQS0 dly(2T, 0.5T) = (0, 11)
3661 19:22:32.015622 best DQS1 dly(2T, 0.5T) = (0, 11)
3662 19:22:32.019169 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3663 19:22:32.022209 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3664 19:22:32.025688 best DQS0 dly(2T, 0.5T) = (0, 11)
3665 19:22:32.028845 best DQS1 dly(2T, 0.5T) = (0, 11)
3666 19:22:32.032370 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3667 19:22:32.035498 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3668 19:22:32.038713 Pre-setting of DQS Precalculation
3669 19:22:32.045473 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3670 19:22:32.051683 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3671 19:22:32.058244 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3672 19:22:32.058325
3673 19:22:32.058390
3674 19:22:32.061967 [Calibration Summary] 2400 Mbps
3675 19:22:32.062048 CH 0, Rank 0
3676 19:22:32.065003 SW Impedance : PASS
3677 19:22:32.068065 DUTY Scan : NO K
3678 19:22:32.068146 ZQ Calibration : PASS
3679 19:22:32.071730 Jitter Meter : NO K
3680 19:22:32.075082 CBT Training : PASS
3681 19:22:32.075163 Write leveling : PASS
3682 19:22:32.078695 RX DQS gating : PASS
3683 19:22:32.081577 RX DQ/DQS(RDDQC) : PASS
3684 19:22:32.081658 TX DQ/DQS : PASS
3685 19:22:32.084891 RX DATLAT : PASS
3686 19:22:32.087795 RX DQ/DQS(Engine): PASS
3687 19:22:32.087926 TX OE : NO K
3688 19:22:32.091258 All Pass.
3689 19:22:32.091339
3690 19:22:32.091403 CH 0, Rank 1
3691 19:22:32.094752 SW Impedance : PASS
3692 19:22:32.094834 DUTY Scan : NO K
3693 19:22:32.097820 ZQ Calibration : PASS
3694 19:22:32.101419 Jitter Meter : NO K
3695 19:22:32.101500 CBT Training : PASS
3696 19:22:32.104467 Write leveling : PASS
3697 19:22:32.107568 RX DQS gating : PASS
3698 19:22:32.107649 RX DQ/DQS(RDDQC) : PASS
3699 19:22:32.111480 TX DQ/DQS : PASS
3700 19:22:32.114661 RX DATLAT : PASS
3701 19:22:32.114742 RX DQ/DQS(Engine): PASS
3702 19:22:32.117895 TX OE : NO K
3703 19:22:32.117977 All Pass.
3704 19:22:32.118042
3705 19:22:32.120817 CH 1, Rank 0
3706 19:22:32.120968 SW Impedance : PASS
3707 19:22:32.123928 DUTY Scan : NO K
3708 19:22:32.127665 ZQ Calibration : PASS
3709 19:22:32.127766 Jitter Meter : NO K
3710 19:22:32.130640 CBT Training : PASS
3711 19:22:32.134228 Write leveling : PASS
3712 19:22:32.134306 RX DQS gating : PASS
3713 19:22:32.137260 RX DQ/DQS(RDDQC) : PASS
3714 19:22:32.140820 TX DQ/DQS : PASS
3715 19:22:32.140930 RX DATLAT : PASS
3716 19:22:32.143625 RX DQ/DQS(Engine): PASS
3717 19:22:32.143733 TX OE : NO K
3718 19:22:32.147278 All Pass.
3719 19:22:32.147376
3720 19:22:32.147468 CH 1, Rank 1
3721 19:22:32.150466 SW Impedance : PASS
3722 19:22:32.153632 DUTY Scan : NO K
3723 19:22:32.153718 ZQ Calibration : PASS
3724 19:22:32.156735 Jitter Meter : NO K
3725 19:22:32.156811 CBT Training : PASS
3726 19:22:32.160341 Write leveling : PASS
3727 19:22:32.163418 RX DQS gating : PASS
3728 19:22:32.163518 RX DQ/DQS(RDDQC) : PASS
3729 19:22:32.166493 TX DQ/DQS : PASS
3730 19:22:32.170227 RX DATLAT : PASS
3731 19:22:32.170323 RX DQ/DQS(Engine): PASS
3732 19:22:32.173253 TX OE : NO K
3733 19:22:32.173356 All Pass.
3734 19:22:32.173447
3735 19:22:32.176783 DramC Write-DBI off
3736 19:22:32.179768 PER_BANK_REFRESH: Hybrid Mode
3737 19:22:32.179867 TX_TRACKING: ON
3738 19:22:32.189747 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3739 19:22:32.193320 [FAST_K] Save calibration result to emmc
3740 19:22:32.196195 dramc_set_vcore_voltage set vcore to 650000
3741 19:22:32.199514 Read voltage for 600, 5
3742 19:22:32.199613 Vio18 = 0
3743 19:22:32.202649 Vcore = 650000
3744 19:22:32.202748 Vdram = 0
3745 19:22:32.202839 Vddq = 0
3746 19:22:32.202936 Vmddr = 0
3747 19:22:32.209496 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3748 19:22:32.215681 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3749 19:22:32.215765 MEM_TYPE=3, freq_sel=19
3750 19:22:32.219329 sv_algorithm_assistance_LP4_1600
3751 19:22:32.222218 ============ PULL DRAM RESETB DOWN ============
3752 19:22:32.229277 ========== PULL DRAM RESETB DOWN end =========
3753 19:22:32.232328 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3754 19:22:32.236034 ===================================
3755 19:22:32.239102 LPDDR4 DRAM CONFIGURATION
3756 19:22:32.242172 ===================================
3757 19:22:32.242258 EX_ROW_EN[0] = 0x0
3758 19:22:32.245792 EX_ROW_EN[1] = 0x0
3759 19:22:32.248843 LP4Y_EN = 0x0
3760 19:22:32.248928 WORK_FSP = 0x0
3761 19:22:32.252490 WL = 0x2
3762 19:22:32.252573 RL = 0x2
3763 19:22:32.255330 BL = 0x2
3764 19:22:32.255445 RPST = 0x0
3765 19:22:32.258975 RD_PRE = 0x0
3766 19:22:32.259059 WR_PRE = 0x1
3767 19:22:32.262266 WR_PST = 0x0
3768 19:22:32.262350 DBI_WR = 0x0
3769 19:22:32.265532 DBI_RD = 0x0
3770 19:22:32.265616 OTF = 0x1
3771 19:22:32.268624 ===================================
3772 19:22:32.271736 ===================================
3773 19:22:32.275342 ANA top config
3774 19:22:32.278414 ===================================
3775 19:22:32.278498 DLL_ASYNC_EN = 0
3776 19:22:32.282073 ALL_SLAVE_EN = 1
3777 19:22:32.285058 NEW_RANK_MODE = 1
3778 19:22:32.288615 DLL_IDLE_MODE = 1
3779 19:22:32.291555 LP45_APHY_COMB_EN = 1
3780 19:22:32.291646 TX_ODT_DIS = 1
3781 19:22:32.295085 NEW_8X_MODE = 1
3782 19:22:32.298191 ===================================
3783 19:22:32.301792 ===================================
3784 19:22:32.304891 data_rate = 1200
3785 19:22:32.308304 CKR = 1
3786 19:22:32.311426 DQ_P2S_RATIO = 8
3787 19:22:32.314680 ===================================
3788 19:22:32.317647 CA_P2S_RATIO = 8
3789 19:22:32.317725 DQ_CA_OPEN = 0
3790 19:22:32.321323 DQ_SEMI_OPEN = 0
3791 19:22:32.324427 CA_SEMI_OPEN = 0
3792 19:22:32.327569 CA_FULL_RATE = 0
3793 19:22:32.330875 DQ_CKDIV4_EN = 1
3794 19:22:32.334161 CA_CKDIV4_EN = 1
3795 19:22:32.337670 CA_PREDIV_EN = 0
3796 19:22:32.337772 PH8_DLY = 0
3797 19:22:32.340633 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3798 19:22:32.344402 DQ_AAMCK_DIV = 4
3799 19:22:32.347349 CA_AAMCK_DIV = 4
3800 19:22:32.351202 CA_ADMCK_DIV = 4
3801 19:22:32.353949 DQ_TRACK_CA_EN = 0
3802 19:22:32.354047 CA_PICK = 600
3803 19:22:32.357464 CA_MCKIO = 600
3804 19:22:32.360534 MCKIO_SEMI = 0
3805 19:22:32.364201 PLL_FREQ = 2288
3806 19:22:32.367214 DQ_UI_PI_RATIO = 32
3807 19:22:32.370729 CA_UI_PI_RATIO = 0
3808 19:22:32.373683 ===================================
3809 19:22:32.376922 ===================================
3810 19:22:32.380120 memory_type:LPDDR4
3811 19:22:32.380189 GP_NUM : 10
3812 19:22:32.383388 SRAM_EN : 1
3813 19:22:32.383457 MD32_EN : 0
3814 19:22:32.386810 ===================================
3815 19:22:32.389881 [ANA_INIT] >>>>>>>>>>>>>>
3816 19:22:32.393345 <<<<<< [CONFIGURE PHASE]: ANA_TX
3817 19:22:32.396706 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3818 19:22:32.400124 ===================================
3819 19:22:32.403042 data_rate = 1200,PCW = 0X5800
3820 19:22:32.406536 ===================================
3821 19:22:32.409678 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3822 19:22:32.416022 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3823 19:22:32.419371 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3824 19:22:32.426125 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3825 19:22:32.429152 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3826 19:22:32.432865 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3827 19:22:32.432964 [ANA_INIT] flow start
3828 19:22:32.435840 [ANA_INIT] PLL >>>>>>>>
3829 19:22:32.439144 [ANA_INIT] PLL <<<<<<<<
3830 19:22:32.442378 [ANA_INIT] MIDPI >>>>>>>>
3831 19:22:32.442462 [ANA_INIT] MIDPI <<<<<<<<
3832 19:22:32.445765 [ANA_INIT] DLL >>>>>>>>
3833 19:22:32.449381 [ANA_INIT] flow end
3834 19:22:32.452493 ============ LP4 DIFF to SE enter ============
3835 19:22:32.455517 ============ LP4 DIFF to SE exit ============
3836 19:22:32.458570 [ANA_INIT] <<<<<<<<<<<<<
3837 19:22:32.462240 [Flow] Enable top DCM control >>>>>
3838 19:22:32.465282 [Flow] Enable top DCM control <<<<<
3839 19:22:32.468891 Enable DLL master slave shuffle
3840 19:22:32.472175 ==============================================================
3841 19:22:32.475060 Gating Mode config
3842 19:22:32.481796 ==============================================================
3843 19:22:32.481880 Config description:
3844 19:22:32.491952 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3845 19:22:32.498376 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3846 19:22:32.505236 SELPH_MODE 0: By rank 1: By Phase
3847 19:22:32.508599 ==============================================================
3848 19:22:32.511448 GAT_TRACK_EN = 1
3849 19:22:32.514886 RX_GATING_MODE = 2
3850 19:22:32.517972 RX_GATING_TRACK_MODE = 2
3851 19:22:32.521583 SELPH_MODE = 1
3852 19:22:32.524901 PICG_EARLY_EN = 1
3853 19:22:32.527785 VALID_LAT_VALUE = 1
3854 19:22:32.531418 ==============================================================
3855 19:22:32.534563 Enter into Gating configuration >>>>
3856 19:22:32.537683 Exit from Gating configuration <<<<
3857 19:22:32.540772 Enter into DVFS_PRE_config >>>>>
3858 19:22:32.554299 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3859 19:22:32.557648 Exit from DVFS_PRE_config <<<<<
3860 19:22:32.560791 Enter into PICG configuration >>>>
3861 19:22:32.564386 Exit from PICG configuration <<<<
3862 19:22:32.564470 [RX_INPUT] configuration >>>>>
3863 19:22:32.567187 [RX_INPUT] configuration <<<<<
3864 19:22:32.574450 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3865 19:22:32.580511 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3866 19:22:32.583623 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3867 19:22:32.590403 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3868 19:22:32.597174 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3869 19:22:32.603705 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3870 19:22:32.606956 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3871 19:22:32.610163 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3872 19:22:32.616512 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3873 19:22:32.619749 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3874 19:22:32.623278 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3875 19:22:32.629784 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3876 19:22:32.633293 ===================================
3877 19:22:32.633378 LPDDR4 DRAM CONFIGURATION
3878 19:22:32.636152 ===================================
3879 19:22:32.639811 EX_ROW_EN[0] = 0x0
3880 19:22:32.643114 EX_ROW_EN[1] = 0x0
3881 19:22:32.643199 LP4Y_EN = 0x0
3882 19:22:32.645914 WORK_FSP = 0x0
3883 19:22:32.645999 WL = 0x2
3884 19:22:32.649614 RL = 0x2
3885 19:22:32.649699 BL = 0x2
3886 19:22:32.652504 RPST = 0x0
3887 19:22:32.652588 RD_PRE = 0x0
3888 19:22:32.655911 WR_PRE = 0x1
3889 19:22:32.656020 WR_PST = 0x0
3890 19:22:32.659291 DBI_WR = 0x0
3891 19:22:32.659368 DBI_RD = 0x0
3892 19:22:32.662738 OTF = 0x1
3893 19:22:32.665826 ===================================
3894 19:22:32.669743 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3895 19:22:32.672480 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3896 19:22:32.679034 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3897 19:22:32.682661 ===================================
3898 19:22:32.682746 LPDDR4 DRAM CONFIGURATION
3899 19:22:32.685664 ===================================
3900 19:22:32.689384 EX_ROW_EN[0] = 0x10
3901 19:22:32.692412 EX_ROW_EN[1] = 0x0
3902 19:22:32.692521 LP4Y_EN = 0x0
3903 19:22:32.696091 WORK_FSP = 0x0
3904 19:22:32.696176 WL = 0x2
3905 19:22:32.699166 RL = 0x2
3906 19:22:32.699250 BL = 0x2
3907 19:22:32.702266 RPST = 0x0
3908 19:22:32.702345 RD_PRE = 0x0
3909 19:22:32.705862 WR_PRE = 0x1
3910 19:22:32.705971 WR_PST = 0x0
3911 19:22:32.708911 DBI_WR = 0x0
3912 19:22:32.709024 DBI_RD = 0x0
3913 19:22:32.712489 OTF = 0x1
3914 19:22:32.715817 ===================================
3915 19:22:32.722295 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3916 19:22:32.725806 nWR fixed to 30
3917 19:22:32.728611 [ModeRegInit_LP4] CH0 RK0
3918 19:22:32.728689 [ModeRegInit_LP4] CH0 RK1
3919 19:22:32.732094 [ModeRegInit_LP4] CH1 RK0
3920 19:22:32.735537 [ModeRegInit_LP4] CH1 RK1
3921 19:22:32.735636 match AC timing 17
3922 19:22:32.742145 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3923 19:22:32.745322 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3924 19:22:32.748580 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3925 19:22:32.755031 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3926 19:22:32.758686 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3927 19:22:32.758786 ==
3928 19:22:32.761597 Dram Type= 6, Freq= 0, CH_0, rank 0
3929 19:22:32.764998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3930 19:22:32.765076 ==
3931 19:22:32.771880 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3932 19:22:32.778471 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3933 19:22:32.781508 [CA 0] Center 36 (6~67) winsize 62
3934 19:22:32.784545 [CA 1] Center 36 (6~66) winsize 61
3935 19:22:32.788249 [CA 2] Center 34 (4~65) winsize 62
3936 19:22:32.791393 [CA 3] Center 34 (4~65) winsize 62
3937 19:22:32.794475 [CA 4] Center 34 (3~65) winsize 63
3938 19:22:32.798232 [CA 5] Center 33 (3~64) winsize 62
3939 19:22:32.798329
3940 19:22:32.801254 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3941 19:22:32.801349
3942 19:22:32.804369 [CATrainingPosCal] consider 1 rank data
3943 19:22:32.808031 u2DelayCellTimex100 = 270/100 ps
3944 19:22:32.811089 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3945 19:22:32.814695 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3946 19:22:32.817923 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3947 19:22:32.821239 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3948 19:22:32.824222 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
3949 19:22:32.830805 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3950 19:22:32.830909
3951 19:22:32.834255 CA PerBit enable=1, Macro0, CA PI delay=33
3952 19:22:32.834331
3953 19:22:32.837897 [CBTSetCACLKResult] CA Dly = 33
3954 19:22:32.837999 CS Dly: 4 (0~35)
3955 19:22:32.838090 ==
3956 19:22:32.841050 Dram Type= 6, Freq= 0, CH_0, rank 1
3957 19:22:32.847648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3958 19:22:32.847750 ==
3959 19:22:32.851085 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3960 19:22:32.857165 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3961 19:22:32.860356 [CA 0] Center 36 (6~67) winsize 62
3962 19:22:32.863977 [CA 1] Center 36 (6~67) winsize 62
3963 19:22:32.867451 [CA 2] Center 34 (4~65) winsize 62
3964 19:22:32.870469 [CA 3] Center 34 (3~65) winsize 63
3965 19:22:32.873838 [CA 4] Center 34 (3~65) winsize 63
3966 19:22:32.877369 [CA 5] Center 33 (3~64) winsize 62
3967 19:22:32.877469
3968 19:22:32.880520 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3969 19:22:32.880618
3970 19:22:32.883760 [CATrainingPosCal] consider 2 rank data
3971 19:22:32.887262 u2DelayCellTimex100 = 270/100 ps
3972 19:22:32.890302 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3973 19:22:32.897008 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3974 19:22:32.900055 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3975 19:22:32.903711 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3976 19:22:32.906764 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
3977 19:22:32.910381 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3978 19:22:32.910491
3979 19:22:32.913509 CA PerBit enable=1, Macro0, CA PI delay=33
3980 19:22:32.913584
3981 19:22:32.916466 [CBTSetCACLKResult] CA Dly = 33
3982 19:22:32.919973 CS Dly: 5 (0~38)
3983 19:22:32.920072
3984 19:22:32.923426 ----->DramcWriteLeveling(PI) begin...
3985 19:22:32.923504 ==
3986 19:22:32.926294 Dram Type= 6, Freq= 0, CH_0, rank 0
3987 19:22:32.929847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3988 19:22:32.929952 ==
3989 19:22:32.932928 Write leveling (Byte 0): 33 => 33
3990 19:22:32.936447 Write leveling (Byte 1): 28 => 28
3991 19:22:32.939993 DramcWriteLeveling(PI) end<-----
3992 19:22:32.940067
3993 19:22:32.940133 ==
3994 19:22:32.943024 Dram Type= 6, Freq= 0, CH_0, rank 0
3995 19:22:32.946161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3996 19:22:32.946262 ==
3997 19:22:32.949843 [Gating] SW mode calibration
3998 19:22:32.956349 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3999 19:22:32.962966 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4000 19:22:32.966439 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4001 19:22:32.969196 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4002 19:22:32.976192 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4003 19:22:32.979127 0 9 12 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 1)
4004 19:22:32.982686 0 9 16 | B1->B0 | 2f2f 2929 | 1 0 | (0 1) (0 0)
4005 19:22:32.988857 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4006 19:22:32.992968 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4007 19:22:32.996023 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4008 19:22:33.002522 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4009 19:22:33.005541 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4010 19:22:33.008661 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4011 19:22:33.015259 0 10 12 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (1 1)
4012 19:22:33.018845 0 10 16 | B1->B0 | 3b3b 4444 | 0 0 | (0 0) (0 0)
4013 19:22:33.021884 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4014 19:22:33.029020 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4015 19:22:33.031807 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4016 19:22:33.035320 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4017 19:22:33.041872 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4018 19:22:33.044966 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4019 19:22:33.048517 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4020 19:22:33.054803 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4021 19:22:33.058340 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 19:22:33.061384 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 19:22:33.068204 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 19:22:33.071686 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 19:22:33.074741 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 19:22:33.081444 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 19:22:33.084846 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 19:22:33.088268 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 19:22:33.094759 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 19:22:33.097906 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 19:22:33.101030 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 19:22:33.107965 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 19:22:33.110940 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 19:22:33.114158 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 19:22:33.121243 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4036 19:22:33.124403 Total UI for P1: 0, mck2ui 16
4037 19:22:33.127343 best dqsien dly found for B0: ( 0, 13, 10)
4038 19:22:33.130803 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4039 19:22:33.133973 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4040 19:22:33.137519 Total UI for P1: 0, mck2ui 16
4041 19:22:33.141044 best dqsien dly found for B1: ( 0, 13, 18)
4042 19:22:33.143961 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4043 19:22:33.150406 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4044 19:22:33.150509
4045 19:22:33.154093 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4046 19:22:33.156965 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4047 19:22:33.160655 [Gating] SW calibration Done
4048 19:22:33.160754 ==
4049 19:22:33.163727 Dram Type= 6, Freq= 0, CH_0, rank 0
4050 19:22:33.166811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4051 19:22:33.166910 ==
4052 19:22:33.170559 RX Vref Scan: 0
4053 19:22:33.170658
4054 19:22:33.170748 RX Vref 0 -> 0, step: 1
4055 19:22:33.170845
4056 19:22:33.173680 RX Delay -230 -> 252, step: 16
4057 19:22:33.176671 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4058 19:22:33.183396 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4059 19:22:33.187076 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4060 19:22:33.190028 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4061 19:22:33.193431 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4062 19:22:33.199823 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4063 19:22:33.203397 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4064 19:22:33.206504 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4065 19:22:33.209520 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4066 19:22:33.216113 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4067 19:22:33.219920 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4068 19:22:33.223016 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4069 19:22:33.226503 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4070 19:22:33.232535 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4071 19:22:33.236093 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4072 19:22:33.239324 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4073 19:22:33.239431 ==
4074 19:22:33.242725 Dram Type= 6, Freq= 0, CH_0, rank 0
4075 19:22:33.245705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4076 19:22:33.249292 ==
4077 19:22:33.249451 DQS Delay:
4078 19:22:33.249559 DQS0 = 0, DQS1 = 0
4079 19:22:33.252182 DQM Delay:
4080 19:22:33.252284 DQM0 = 45, DQM1 = 35
4081 19:22:33.255775 DQ Delay:
4082 19:22:33.258828 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4083 19:22:33.258937 DQ4 =41, DQ5 =41, DQ6 =57, DQ7 =57
4084 19:22:33.262389 DQ8 =25, DQ9 =17, DQ10 =41, DQ11 =33
4085 19:22:33.269022 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4086 19:22:33.269128
4087 19:22:33.269219
4088 19:22:33.269310 ==
4089 19:22:33.272068 Dram Type= 6, Freq= 0, CH_0, rank 0
4090 19:22:33.275151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4091 19:22:33.275254 ==
4092 19:22:33.275345
4093 19:22:33.275431
4094 19:22:33.278820 TX Vref Scan disable
4095 19:22:33.278916 == TX Byte 0 ==
4096 19:22:33.284894 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4097 19:22:33.288517 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4098 19:22:33.288595 == TX Byte 1 ==
4099 19:22:33.295266 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4100 19:22:33.298113 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4101 19:22:33.298211 ==
4102 19:22:33.301495 Dram Type= 6, Freq= 0, CH_0, rank 0
4103 19:22:33.304876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4104 19:22:33.304979 ==
4105 19:22:33.308586
4106 19:22:33.308659
4107 19:22:33.308725 TX Vref Scan disable
4108 19:22:33.311831 == TX Byte 0 ==
4109 19:22:33.315011 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4110 19:22:33.321719 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4111 19:22:33.321818 == TX Byte 1 ==
4112 19:22:33.324845 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4113 19:22:33.331851 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4114 19:22:33.331999
4115 19:22:33.332065 [DATLAT]
4116 19:22:33.332125 Freq=600, CH0 RK0
4117 19:22:33.332184
4118 19:22:33.335444 DATLAT Default: 0x9
4119 19:22:33.338373 0, 0xFFFF, sum = 0
4120 19:22:33.338469 1, 0xFFFF, sum = 0
4121 19:22:33.341840 2, 0xFFFF, sum = 0
4122 19:22:33.341938 3, 0xFFFF, sum = 0
4123 19:22:33.345254 4, 0xFFFF, sum = 0
4124 19:22:33.345403 5, 0xFFFF, sum = 0
4125 19:22:33.348012 6, 0xFFFF, sum = 0
4126 19:22:33.348087 7, 0xFFFF, sum = 0
4127 19:22:33.351251 8, 0x0, sum = 1
4128 19:22:33.351324 9, 0x0, sum = 2
4129 19:22:33.354829 10, 0x0, sum = 3
4130 19:22:33.354903 11, 0x0, sum = 4
4131 19:22:33.354972 best_step = 9
4132 19:22:33.355031
4133 19:22:33.358155 ==
4134 19:22:33.360991 Dram Type= 6, Freq= 0, CH_0, rank 0
4135 19:22:33.364718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4136 19:22:33.364787 ==
4137 19:22:33.364848 RX Vref Scan: 1
4138 19:22:33.364908
4139 19:22:33.367909 RX Vref 0 -> 0, step: 1
4140 19:22:33.368016
4141 19:22:33.371333 RX Delay -195 -> 252, step: 8
4142 19:22:33.371426
4143 19:22:33.374446 Set Vref, RX VrefLevel [Byte0]: 58
4144 19:22:33.377545 [Byte1]: 49
4145 19:22:33.377617
4146 19:22:33.381389 Final RX Vref Byte 0 = 58 to rank0
4147 19:22:33.384112 Final RX Vref Byte 1 = 49 to rank0
4148 19:22:33.387837 Final RX Vref Byte 0 = 58 to rank1
4149 19:22:33.390730 Final RX Vref Byte 1 = 49 to rank1==
4150 19:22:33.394324 Dram Type= 6, Freq= 0, CH_0, rank 0
4151 19:22:33.400929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4152 19:22:33.401003 ==
4153 19:22:33.401072 DQS Delay:
4154 19:22:33.401131 DQS0 = 0, DQS1 = 0
4155 19:22:33.403960 DQM Delay:
4156 19:22:33.404034 DQM0 = 44, DQM1 = 37
4157 19:22:33.407692 DQ Delay:
4158 19:22:33.410988 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4159 19:22:33.413954 DQ4 =48, DQ5 =36, DQ6 =52, DQ7 =48
4160 19:22:33.417383 DQ8 =28, DQ9 =28, DQ10 =36, DQ11 =32
4161 19:22:33.420368 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =44
4162 19:22:33.420464
4163 19:22:33.420529
4164 19:22:33.427096 [DQSOSCAuto] RK0, (LSB)MR18= 0x4f47, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 394 ps
4165 19:22:33.430124 CH0 RK0: MR19=808, MR18=4F47
4166 19:22:33.436644 CH0_RK0: MR19=0x808, MR18=0x4F47, DQSOSC=394, MR23=63, INC=168, DEC=112
4167 19:22:33.436726
4168 19:22:33.440296 ----->DramcWriteLeveling(PI) begin...
4169 19:22:33.440370 ==
4170 19:22:33.443416 Dram Type= 6, Freq= 0, CH_0, rank 1
4171 19:22:33.446603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4172 19:22:33.446699 ==
4173 19:22:33.450044 Write leveling (Byte 0): 34 => 34
4174 19:22:33.453384 Write leveling (Byte 1): 30 => 30
4175 19:22:33.456851 DramcWriteLeveling(PI) end<-----
4176 19:22:33.456936
4177 19:22:33.457001 ==
4178 19:22:33.460202 Dram Type= 6, Freq= 0, CH_0, rank 1
4179 19:22:33.463455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4180 19:22:33.466568 ==
4181 19:22:33.466650 [Gating] SW mode calibration
4182 19:22:33.476462 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4183 19:22:33.479509 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4184 19:22:33.482717 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4185 19:22:33.489601 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4186 19:22:33.492636 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4187 19:22:33.496345 0 9 12 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
4188 19:22:33.502725 0 9 16 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
4189 19:22:33.505855 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4190 19:22:33.509436 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4191 19:22:33.516242 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4192 19:22:33.519177 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4193 19:22:33.522088 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4194 19:22:33.528732 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4195 19:22:33.531907 0 10 12 | B1->B0 | 2727 3131 | 0 0 | (0 0) (0 0)
4196 19:22:33.538770 0 10 16 | B1->B0 | 3b3b 4646 | 0 0 | (1 1) (0 0)
4197 19:22:33.542333 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4198 19:22:33.545518 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4199 19:22:33.549118 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4200 19:22:33.555802 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4201 19:22:33.559312 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4202 19:22:33.562391 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4203 19:22:33.568999 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 19:22:33.571945 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4205 19:22:33.575462 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 19:22:33.582282 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 19:22:33.585614 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 19:22:33.588749 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 19:22:33.595130 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 19:22:33.598597 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 19:22:33.602097 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 19:22:33.608690 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 19:22:33.611561 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 19:22:33.614882 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 19:22:33.621453 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 19:22:33.625037 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 19:22:33.631235 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 19:22:33.634984 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 19:22:33.638322 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4220 19:22:33.644714 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4221 19:22:33.645261 Total UI for P1: 0, mck2ui 16
4222 19:22:33.647605 best dqsien dly found for B0: ( 0, 13, 12)
4223 19:22:33.654329 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4224 19:22:33.657861 Total UI for P1: 0, mck2ui 16
4225 19:22:33.660942 best dqsien dly found for B1: ( 0, 13, 16)
4226 19:22:33.664391 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4227 19:22:33.667337 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4228 19:22:33.667858
4229 19:22:33.670980 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4230 19:22:33.674464 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4231 19:22:33.677531 [Gating] SW calibration Done
4232 19:22:33.677976 ==
4233 19:22:33.680645 Dram Type= 6, Freq= 0, CH_0, rank 1
4234 19:22:33.684214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4235 19:22:33.687051 ==
4236 19:22:33.687464 RX Vref Scan: 0
4237 19:22:33.687794
4238 19:22:33.690734 RX Vref 0 -> 0, step: 1
4239 19:22:33.691190
4240 19:22:33.693770 RX Delay -230 -> 252, step: 16
4241 19:22:33.697354 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4242 19:22:33.700223 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4243 19:22:33.703777 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4244 19:22:33.710389 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4245 19:22:33.713620 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4246 19:22:33.717105 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4247 19:22:33.720412 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4248 19:22:33.726592 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4249 19:22:33.730196 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4250 19:22:33.733631 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4251 19:22:33.736613 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4252 19:22:33.743342 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4253 19:22:33.746416 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4254 19:22:33.749972 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4255 19:22:33.752883 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4256 19:22:33.759643 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4257 19:22:33.760085 ==
4258 19:22:33.762710 Dram Type= 6, Freq= 0, CH_0, rank 1
4259 19:22:33.766294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4260 19:22:33.766716 ==
4261 19:22:33.767104 DQS Delay:
4262 19:22:33.769313 DQS0 = 0, DQS1 = 0
4263 19:22:33.769727 DQM Delay:
4264 19:22:33.772943 DQM0 = 46, DQM1 = 36
4265 19:22:33.773357 DQ Delay:
4266 19:22:33.775992 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4267 19:22:33.779383 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4268 19:22:33.782381 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4269 19:22:33.786187 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4270 19:22:33.786603
4271 19:22:33.786935
4272 19:22:33.787243 ==
4273 19:22:33.789059 Dram Type= 6, Freq= 0, CH_0, rank 1
4274 19:22:33.792475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4275 19:22:33.792930 ==
4276 19:22:33.793268
4277 19:22:33.796193
4278 19:22:33.796603 TX Vref Scan disable
4279 19:22:33.799348 == TX Byte 0 ==
4280 19:22:33.802608 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4281 19:22:33.806083 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4282 19:22:33.808853 == TX Byte 1 ==
4283 19:22:33.812347 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4284 19:22:33.815729 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4285 19:22:33.818952 ==
4286 19:22:33.819371 Dram Type= 6, Freq= 0, CH_0, rank 1
4287 19:22:33.825534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4288 19:22:33.826003 ==
4289 19:22:33.826357
4290 19:22:33.826670
4291 19:22:33.828739 TX Vref Scan disable
4292 19:22:33.829159 == TX Byte 0 ==
4293 19:22:33.835391 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4294 19:22:33.838851 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4295 19:22:33.842008 == TX Byte 1 ==
4296 19:22:33.845312 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4297 19:22:33.848415 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4298 19:22:33.848854
4299 19:22:33.849215 [DATLAT]
4300 19:22:33.852065 Freq=600, CH0 RK1
4301 19:22:33.852680
4302 19:22:33.853025 DATLAT Default: 0x9
4303 19:22:33.855292 0, 0xFFFF, sum = 0
4304 19:22:33.858287 1, 0xFFFF, sum = 0
4305 19:22:33.858761 2, 0xFFFF, sum = 0
4306 19:22:33.861992 3, 0xFFFF, sum = 0
4307 19:22:33.862426 4, 0xFFFF, sum = 0
4308 19:22:33.865325 5, 0xFFFF, sum = 0
4309 19:22:33.865857 6, 0xFFFF, sum = 0
4310 19:22:33.868064 7, 0xFFFF, sum = 0
4311 19:22:33.868490 8, 0x0, sum = 1
4312 19:22:33.871707 9, 0x0, sum = 2
4313 19:22:33.872193 10, 0x0, sum = 3
4314 19:22:33.875122 11, 0x0, sum = 4
4315 19:22:33.875549 best_step = 9
4316 19:22:33.875926
4317 19:22:33.876256 ==
4318 19:22:33.878123 Dram Type= 6, Freq= 0, CH_0, rank 1
4319 19:22:33.881680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4320 19:22:33.882105 ==
4321 19:22:33.884638 RX Vref Scan: 0
4322 19:22:33.885057
4323 19:22:33.888381 RX Vref 0 -> 0, step: 1
4324 19:22:33.888802
4325 19:22:33.889134 RX Delay -179 -> 252, step: 8
4326 19:22:33.895927 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4327 19:22:33.899021 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4328 19:22:33.902066 iDelay=205, Bit 2, Center 40 (-107 ~ 188) 296
4329 19:22:33.905775 iDelay=205, Bit 3, Center 40 (-107 ~ 188) 296
4330 19:22:33.912417 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4331 19:22:33.915318 iDelay=205, Bit 5, Center 32 (-115 ~ 180) 296
4332 19:22:33.918952 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4333 19:22:33.921822 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4334 19:22:33.928895 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4335 19:22:33.931710 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4336 19:22:33.935264 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4337 19:22:33.938394 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4338 19:22:33.944947 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4339 19:22:33.948088 iDelay=205, Bit 13, Center 40 (-107 ~ 188) 296
4340 19:22:33.951365 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4341 19:22:33.954319 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4342 19:22:33.954400 ==
4343 19:22:33.957891 Dram Type= 6, Freq= 0, CH_0, rank 1
4344 19:22:33.964100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4345 19:22:33.964182 ==
4346 19:22:33.964247 DQS Delay:
4347 19:22:33.967646 DQS0 = 0, DQS1 = 0
4348 19:22:33.967733 DQM Delay:
4349 19:22:33.967801 DQM0 = 43, DQM1 = 36
4350 19:22:33.970721 DQ Delay:
4351 19:22:33.974400 DQ0 =40, DQ1 =44, DQ2 =40, DQ3 =40
4352 19:22:33.977412 DQ4 =48, DQ5 =32, DQ6 =56, DQ7 =48
4353 19:22:33.981059 DQ8 =28, DQ9 =24, DQ10 =36, DQ11 =32
4354 19:22:33.984096 DQ12 =40, DQ13 =40, DQ14 =48, DQ15 =44
4355 19:22:33.984205
4356 19:22:33.984292
4357 19:22:33.990809 [DQSOSCAuto] RK1, (LSB)MR18= 0x4642, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 396 ps
4358 19:22:33.994432 CH0 RK1: MR19=808, MR18=4642
4359 19:22:34.000459 CH0_RK1: MR19=0x808, MR18=0x4642, DQSOSC=396, MR23=63, INC=167, DEC=111
4360 19:22:34.004052 [RxdqsGatingPostProcess] freq 600
4361 19:22:34.007191 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4362 19:22:34.010838 Pre-setting of DQS Precalculation
4363 19:22:34.017517 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4364 19:22:34.017817 ==
4365 19:22:34.020467 Dram Type= 6, Freq= 0, CH_1, rank 0
4366 19:22:34.024157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4367 19:22:34.024542 ==
4368 19:22:34.030546 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4369 19:22:34.037360 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4370 19:22:34.040911 [CA 0] Center 36 (6~66) winsize 61
4371 19:22:34.043725 [CA 1] Center 35 (5~66) winsize 62
4372 19:22:34.046855 [CA 2] Center 34 (4~65) winsize 62
4373 19:22:34.050181 [CA 3] Center 34 (3~65) winsize 63
4374 19:22:34.053420 [CA 4] Center 34 (4~65) winsize 62
4375 19:22:34.056932 [CA 5] Center 34 (3~65) winsize 63
4376 19:22:34.057013
4377 19:22:34.059794 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4378 19:22:34.059875
4379 19:22:34.063255 [CATrainingPosCal] consider 1 rank data
4380 19:22:34.066708 u2DelayCellTimex100 = 270/100 ps
4381 19:22:34.069873 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4382 19:22:34.073448 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4383 19:22:34.076639 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4384 19:22:34.079510 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
4385 19:22:34.082797 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4386 19:22:34.089478 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4387 19:22:34.089665
4388 19:22:34.092828 CA PerBit enable=1, Macro0, CA PI delay=34
4389 19:22:34.092966
4390 19:22:34.096051 [CBTSetCACLKResult] CA Dly = 34
4391 19:22:34.096186 CS Dly: 4 (0~35)
4392 19:22:34.096292 ==
4393 19:22:34.099653 Dram Type= 6, Freq= 0, CH_1, rank 1
4394 19:22:34.102912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4395 19:22:34.106333 ==
4396 19:22:34.109301 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4397 19:22:34.116049 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4398 19:22:34.119498 [CA 0] Center 35 (5~66) winsize 62
4399 19:22:34.122699 [CA 1] Center 35 (5~66) winsize 62
4400 19:22:34.126229 [CA 2] Center 34 (4~65) winsize 62
4401 19:22:34.129598 [CA 3] Center 34 (3~65) winsize 63
4402 19:22:34.132518 [CA 4] Center 34 (4~65) winsize 62
4403 19:22:34.136086 [CA 5] Center 34 (3~65) winsize 63
4404 19:22:34.136505
4405 19:22:34.139593 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4406 19:22:34.140044
4407 19:22:34.143157 [CATrainingPosCal] consider 2 rank data
4408 19:22:34.146118 u2DelayCellTimex100 = 270/100 ps
4409 19:22:34.149000 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4410 19:22:34.152838 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4411 19:22:34.159339 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4412 19:22:34.162378 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
4413 19:22:34.165851 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4414 19:22:34.168987 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4415 19:22:34.169404
4416 19:22:34.172515 CA PerBit enable=1, Macro0, CA PI delay=34
4417 19:22:34.172931
4418 19:22:34.175612 [CBTSetCACLKResult] CA Dly = 34
4419 19:22:34.176122 CS Dly: 4 (0~36)
4420 19:22:34.176475
4421 19:22:34.178840 ----->DramcWriteLeveling(PI) begin...
4422 19:22:34.182215 ==
4423 19:22:34.185589 Dram Type= 6, Freq= 0, CH_1, rank 0
4424 19:22:34.189070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4425 19:22:34.189587 ==
4426 19:22:34.192113 Write leveling (Byte 0): 30 => 30
4427 19:22:34.195601 Write leveling (Byte 1): 30 => 30
4428 19:22:34.198286 DramcWriteLeveling(PI) end<-----
4429 19:22:34.198729
4430 19:22:34.199068 ==
4431 19:22:34.201997 Dram Type= 6, Freq= 0, CH_1, rank 0
4432 19:22:34.205456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4433 19:22:34.205876 ==
4434 19:22:34.208392 [Gating] SW mode calibration
4435 19:22:34.214966 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4436 19:22:34.221630 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4437 19:22:34.224687 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4438 19:22:34.228261 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4439 19:22:34.235035 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4440 19:22:34.238198 0 9 12 | B1->B0 | 3232 2f2f | 1 0 | (0 0) (0 0)
4441 19:22:34.241143 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4442 19:22:34.247791 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4443 19:22:34.251213 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4444 19:22:34.254505 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4445 19:22:34.260847 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4446 19:22:34.264736 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4447 19:22:34.267745 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4448 19:22:34.274378 0 10 12 | B1->B0 | 3333 3e3e | 0 0 | (0 0) (0 0)
4449 19:22:34.277557 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4450 19:22:34.281422 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4451 19:22:34.287621 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4452 19:22:34.291223 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4453 19:22:34.294096 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4454 19:22:34.300659 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4455 19:22:34.303983 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4456 19:22:34.307200 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4457 19:22:34.314041 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 19:22:34.317301 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 19:22:34.320669 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 19:22:34.327458 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 19:22:34.330320 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 19:22:34.333941 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 19:22:34.340440 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 19:22:34.343623 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 19:22:34.346657 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 19:22:34.353895 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 19:22:34.356938 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 19:22:34.359959 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 19:22:34.366448 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 19:22:34.369708 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 19:22:34.373065 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 19:22:34.379485 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4473 19:22:34.382975 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4474 19:22:34.386626 Total UI for P1: 0, mck2ui 16
4475 19:22:34.389660 best dqsien dly found for B0: ( 0, 13, 12)
4476 19:22:34.393356 Total UI for P1: 0, mck2ui 16
4477 19:22:34.395985 best dqsien dly found for B1: ( 0, 13, 12)
4478 19:22:34.399401 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4479 19:22:34.402661 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4480 19:22:34.403130
4481 19:22:34.405920 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4482 19:22:34.409176 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4483 19:22:34.412668 [Gating] SW calibration Done
4484 19:22:34.413196 ==
4485 19:22:34.416067 Dram Type= 6, Freq= 0, CH_1, rank 0
4486 19:22:34.422541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4487 19:22:34.423098 ==
4488 19:22:34.423580 RX Vref Scan: 0
4489 19:22:34.424117
4490 19:22:34.425770 RX Vref 0 -> 0, step: 1
4491 19:22:34.426259
4492 19:22:34.429173 RX Delay -230 -> 252, step: 16
4493 19:22:34.432749 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4494 19:22:34.435757 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4495 19:22:34.439240 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4496 19:22:34.445316 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4497 19:22:34.449001 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4498 19:22:34.452327 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4499 19:22:34.455639 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4500 19:22:34.461745 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4501 19:22:34.465145 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4502 19:22:34.468234 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4503 19:22:34.471653 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4504 19:22:34.478297 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4505 19:22:34.481276 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4506 19:22:34.484876 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4507 19:22:34.488426 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4508 19:22:34.494450 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4509 19:22:34.494527 ==
4510 19:22:34.498210 Dram Type= 6, Freq= 0, CH_1, rank 0
4511 19:22:34.501424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4512 19:22:34.501593 ==
4513 19:22:34.501720 DQS Delay:
4514 19:22:34.504810 DQS0 = 0, DQS1 = 0
4515 19:22:34.504948 DQM Delay:
4516 19:22:34.507738 DQM0 = 42, DQM1 = 39
4517 19:22:34.507914 DQ Delay:
4518 19:22:34.511352 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4519 19:22:34.514678 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4520 19:22:34.518032 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4521 19:22:34.521142 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4522 19:22:34.521340
4523 19:22:34.521485
4524 19:22:34.521609 ==
4525 19:22:34.524799 Dram Type= 6, Freq= 0, CH_1, rank 0
4526 19:22:34.527482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4527 19:22:34.527619 ==
4528 19:22:34.531026
4529 19:22:34.531255
4530 19:22:34.531466 TX Vref Scan disable
4531 19:22:34.534442 == TX Byte 0 ==
4532 19:22:34.537595 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4533 19:22:34.541003 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4534 19:22:34.544352 == TX Byte 1 ==
4535 19:22:34.547425 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4536 19:22:34.550493 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4537 19:22:34.554098 ==
4538 19:22:34.557081 Dram Type= 6, Freq= 0, CH_1, rank 0
4539 19:22:34.560654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4540 19:22:34.560739 ==
4541 19:22:34.560821
4542 19:22:34.560887
4543 19:22:34.563737 TX Vref Scan disable
4544 19:22:34.563811 == TX Byte 0 ==
4545 19:22:34.570667 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4546 19:22:34.573519 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4547 19:22:34.577253 == TX Byte 1 ==
4548 19:22:34.580749 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4549 19:22:34.583797 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4550 19:22:34.584007
4551 19:22:34.584177 [DATLAT]
4552 19:22:34.586769 Freq=600, CH1 RK0
4553 19:22:34.586994
4554 19:22:34.587175 DATLAT Default: 0x9
4555 19:22:34.590432 0, 0xFFFF, sum = 0
4556 19:22:34.593225 1, 0xFFFF, sum = 0
4557 19:22:34.593381 2, 0xFFFF, sum = 0
4558 19:22:34.596978 3, 0xFFFF, sum = 0
4559 19:22:34.597190 4, 0xFFFF, sum = 0
4560 19:22:34.600013 5, 0xFFFF, sum = 0
4561 19:22:34.600190 6, 0xFFFF, sum = 0
4562 19:22:34.603705 7, 0xFFFF, sum = 0
4563 19:22:34.603969 8, 0x0, sum = 1
4564 19:22:34.606756 9, 0x0, sum = 2
4565 19:22:34.607003 10, 0x0, sum = 3
4566 19:22:34.607308 11, 0x0, sum = 4
4567 19:22:34.610385 best_step = 9
4568 19:22:34.610642
4569 19:22:34.610928 ==
4570 19:22:34.613410 Dram Type= 6, Freq= 0, CH_1, rank 0
4571 19:22:34.616729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4572 19:22:34.616823 ==
4573 19:22:34.619737 RX Vref Scan: 1
4574 19:22:34.619850
4575 19:22:34.623327 RX Vref 0 -> 0, step: 1
4576 19:22:34.623411
4577 19:22:34.623504 RX Delay -179 -> 252, step: 8
4578 19:22:34.623603
4579 19:22:34.626350 Set Vref, RX VrefLevel [Byte0]: 51
4580 19:22:34.629737 [Byte1]: 51
4581 19:22:34.634143
4582 19:22:34.634257 Final RX Vref Byte 0 = 51 to rank0
4583 19:22:34.637730 Final RX Vref Byte 1 = 51 to rank0
4584 19:22:34.641115 Final RX Vref Byte 0 = 51 to rank1
4585 19:22:34.644350 Final RX Vref Byte 1 = 51 to rank1==
4586 19:22:34.647643 Dram Type= 6, Freq= 0, CH_1, rank 0
4587 19:22:34.654310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4588 19:22:34.654436 ==
4589 19:22:34.654561 DQS Delay:
4590 19:22:34.657355 DQS0 = 0, DQS1 = 0
4591 19:22:34.657506 DQM Delay:
4592 19:22:34.657647 DQM0 = 41, DQM1 = 34
4593 19:22:34.660382 DQ Delay:
4594 19:22:34.664177 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4595 19:22:34.667369 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =36
4596 19:22:34.670410 DQ8 =20, DQ9 =24, DQ10 =32, DQ11 =28
4597 19:22:34.674078 DQ12 =44, DQ13 =44, DQ14 =40, DQ15 =40
4598 19:22:34.674369
4599 19:22:34.674596
4600 19:22:34.680488 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f49, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 400 ps
4601 19:22:34.683656 CH1 RK0: MR19=808, MR18=2F49
4602 19:22:34.690769 CH1_RK0: MR19=0x808, MR18=0x2F49, DQSOSC=396, MR23=63, INC=167, DEC=111
4603 19:22:34.691377
4604 19:22:34.693445 ----->DramcWriteLeveling(PI) begin...
4605 19:22:34.693953 ==
4606 19:22:34.696852 Dram Type= 6, Freq= 0, CH_1, rank 1
4607 19:22:34.700310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4608 19:22:34.700825 ==
4609 19:22:34.703462 Write leveling (Byte 0): 32 => 32
4610 19:22:34.706180 Write leveling (Byte 1): 31 => 31
4611 19:22:34.709453 DramcWriteLeveling(PI) end<-----
4612 19:22:34.709561
4613 19:22:34.709645 ==
4614 19:22:34.713273 Dram Type= 6, Freq= 0, CH_1, rank 1
4615 19:22:34.719810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4616 19:22:34.719931 ==
4617 19:22:34.720021 [Gating] SW mode calibration
4618 19:22:34.729253 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4619 19:22:34.732891 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4620 19:22:34.739346 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4621 19:22:34.742733 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4622 19:22:34.745996 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4623 19:22:34.752871 0 9 12 | B1->B0 | 3333 2b2b | 0 0 | (0 0) (0 1)
4624 19:22:34.756109 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4625 19:22:34.759468 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4626 19:22:34.765479 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4627 19:22:34.768896 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4628 19:22:34.772526 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4629 19:22:34.779111 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4630 19:22:34.782152 0 10 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
4631 19:22:34.785819 0 10 12 | B1->B0 | 2f2f 4040 | 0 0 | (0 0) (0 0)
4632 19:22:34.792174 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4633 19:22:34.795881 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4634 19:22:34.798868 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4635 19:22:34.805530 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4636 19:22:34.808430 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4637 19:22:34.812219 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4638 19:22:34.818494 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4639 19:22:34.821735 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4640 19:22:34.825417 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 19:22:34.831948 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 19:22:34.835014 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 19:22:34.838305 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 19:22:34.844857 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 19:22:34.848184 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 19:22:34.851123 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 19:22:34.858122 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 19:22:34.861064 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 19:22:34.864398 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 19:22:34.870939 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 19:22:34.874429 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 19:22:34.877669 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 19:22:34.883951 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 19:22:34.887521 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4655 19:22:34.890541 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4656 19:22:34.897101 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4657 19:22:34.900577 Total UI for P1: 0, mck2ui 16
4658 19:22:34.903572 best dqsien dly found for B0: ( 0, 13, 10)
4659 19:22:34.904014 Total UI for P1: 0, mck2ui 16
4660 19:22:34.910449 best dqsien dly found for B1: ( 0, 13, 12)
4661 19:22:34.913507 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4662 19:22:34.917081 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4663 19:22:34.917519
4664 19:22:34.920196 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4665 19:22:34.923699 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4666 19:22:34.926648 [Gating] SW calibration Done
4667 19:22:34.927067 ==
4668 19:22:34.930042 Dram Type= 6, Freq= 0, CH_1, rank 1
4669 19:22:34.933606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4670 19:22:34.934084 ==
4671 19:22:34.937040 RX Vref Scan: 0
4672 19:22:34.937525
4673 19:22:34.940106 RX Vref 0 -> 0, step: 1
4674 19:22:34.940518
4675 19:22:34.940847 RX Delay -230 -> 252, step: 16
4676 19:22:34.946628 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4677 19:22:34.950385 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4678 19:22:34.953282 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4679 19:22:34.956718 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4680 19:22:34.962859 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4681 19:22:34.966405 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4682 19:22:34.970029 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4683 19:22:34.972792 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4684 19:22:34.979286 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4685 19:22:34.982729 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4686 19:22:34.986014 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4687 19:22:34.989577 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4688 19:22:34.996087 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4689 19:22:34.999492 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4690 19:22:35.002638 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4691 19:22:35.006214 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4692 19:22:35.006695 ==
4693 19:22:35.009244 Dram Type= 6, Freq= 0, CH_1, rank 1
4694 19:22:35.015859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4695 19:22:35.016376 ==
4696 19:22:35.016811 DQS Delay:
4697 19:22:35.019379 DQS0 = 0, DQS1 = 0
4698 19:22:35.019806 DQM Delay:
4699 19:22:35.020319 DQM0 = 42, DQM1 = 38
4700 19:22:35.022278 DQ Delay:
4701 19:22:35.025925 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4702 19:22:35.028876 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4703 19:22:35.032533 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4704 19:22:35.035379 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4705 19:22:35.035805
4706 19:22:35.036266
4707 19:22:35.036742 ==
4708 19:22:35.038770 Dram Type= 6, Freq= 0, CH_1, rank 1
4709 19:22:35.042111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4710 19:22:35.042629 ==
4711 19:22:35.043085
4712 19:22:35.043498
4713 19:22:35.045572 TX Vref Scan disable
4714 19:22:35.048653 == TX Byte 0 ==
4715 19:22:35.051755 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4716 19:22:35.055278 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4717 19:22:35.058851 == TX Byte 1 ==
4718 19:22:35.061699 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4719 19:22:35.065167 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4720 19:22:35.065631 ==
4721 19:22:35.068090 Dram Type= 6, Freq= 0, CH_1, rank 1
4722 19:22:35.074858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4723 19:22:35.075335 ==
4724 19:22:35.075827
4725 19:22:35.076355
4726 19:22:35.076832 TX Vref Scan disable
4727 19:22:35.079380 == TX Byte 0 ==
4728 19:22:35.082251 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4729 19:22:35.088880 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4730 19:22:35.089299 == TX Byte 1 ==
4731 19:22:35.092302 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4732 19:22:35.098822 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4733 19:22:35.099352
4734 19:22:35.099878 [DATLAT]
4735 19:22:35.100443 Freq=600, CH1 RK1
4736 19:22:35.101063
4737 19:22:35.102456 DATLAT Default: 0x9
4738 19:22:35.105377 0, 0xFFFF, sum = 0
4739 19:22:35.105825 1, 0xFFFF, sum = 0
4740 19:22:35.109254 2, 0xFFFF, sum = 0
4741 19:22:35.109675 3, 0xFFFF, sum = 0
4742 19:22:35.111975 4, 0xFFFF, sum = 0
4743 19:22:35.112680 5, 0xFFFF, sum = 0
4744 19:22:35.115691 6, 0xFFFF, sum = 0
4745 19:22:35.116289 7, 0xFFFF, sum = 0
4746 19:22:35.118373 8, 0x0, sum = 1
4747 19:22:35.118858 9, 0x0, sum = 2
4748 19:22:35.121785 10, 0x0, sum = 3
4749 19:22:35.122255 11, 0x0, sum = 4
4750 19:22:35.122762 best_step = 9
4751 19:22:35.123209
4752 19:22:35.125392 ==
4753 19:22:35.128427 Dram Type= 6, Freq= 0, CH_1, rank 1
4754 19:22:35.131457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4755 19:22:35.131957 ==
4756 19:22:35.132393 RX Vref Scan: 0
4757 19:22:35.132847
4758 19:22:35.134984 RX Vref 0 -> 0, step: 1
4759 19:22:35.135411
4760 19:22:35.138188 RX Delay -179 -> 252, step: 8
4761 19:22:35.144880 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4762 19:22:35.148324 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4763 19:22:35.151732 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4764 19:22:35.154745 iDelay=205, Bit 3, Center 36 (-123 ~ 196) 320
4765 19:22:35.161193 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4766 19:22:35.164257 iDelay=205, Bit 5, Center 44 (-115 ~ 204) 320
4767 19:22:35.167716 iDelay=205, Bit 6, Center 44 (-107 ~ 196) 304
4768 19:22:35.171614 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4769 19:22:35.177644 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4770 19:22:35.181252 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4771 19:22:35.184197 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4772 19:22:35.187486 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4773 19:22:35.190724 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4774 19:22:35.197180 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4775 19:22:35.200634 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4776 19:22:35.203953 iDelay=205, Bit 15, Center 44 (-115 ~ 204) 320
4777 19:22:35.204362 ==
4778 19:22:35.206911 Dram Type= 6, Freq= 0, CH_1, rank 1
4779 19:22:35.213587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4780 19:22:35.214005 ==
4781 19:22:35.214363 DQS Delay:
4782 19:22:35.217161 DQS0 = 0, DQS1 = 0
4783 19:22:35.217580 DQM Delay:
4784 19:22:35.217913 DQM0 = 37, DQM1 = 35
4785 19:22:35.220089 DQ Delay:
4786 19:22:35.223799 DQ0 =40, DQ1 =36, DQ2 =24, DQ3 =36
4787 19:22:35.226828 DQ4 =40, DQ5 =44, DQ6 =44, DQ7 =32
4788 19:22:35.230313 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =28
4789 19:22:35.233520 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =44
4790 19:22:35.233979
4791 19:22:35.234307
4792 19:22:35.240134 [DQSOSCAuto] RK1, (LSB)MR18= 0x3c60, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
4793 19:22:35.243044 CH1 RK1: MR19=808, MR18=3C60
4794 19:22:35.250106 CH1_RK1: MR19=0x808, MR18=0x3C60, DQSOSC=391, MR23=63, INC=171, DEC=114
4795 19:22:35.253200 [RxdqsGatingPostProcess] freq 600
4796 19:22:35.259655 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4797 19:22:35.260273 Pre-setting of DQS Precalculation
4798 19:22:35.266494 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4799 19:22:35.273133 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4800 19:22:35.279962 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4801 19:22:35.280390
4802 19:22:35.280723
4803 19:22:35.283078 [Calibration Summary] 1200 Mbps
4804 19:22:35.286330 CH 0, Rank 0
4805 19:22:35.286886 SW Impedance : PASS
4806 19:22:35.289296 DUTY Scan : NO K
4807 19:22:35.292925 ZQ Calibration : PASS
4808 19:22:35.293477 Jitter Meter : NO K
4809 19:22:35.295821 CBT Training : PASS
4810 19:22:35.299202 Write leveling : PASS
4811 19:22:35.299610 RX DQS gating : PASS
4812 19:22:35.302742 RX DQ/DQS(RDDQC) : PASS
4813 19:22:35.306125 TX DQ/DQS : PASS
4814 19:22:35.306540 RX DATLAT : PASS
4815 19:22:35.308887 RX DQ/DQS(Engine): PASS
4816 19:22:35.309303 TX OE : NO K
4817 19:22:35.312417 All Pass.
4818 19:22:35.313050
4819 19:22:35.313403 CH 0, Rank 1
4820 19:22:35.315762 SW Impedance : PASS
4821 19:22:35.318840 DUTY Scan : NO K
4822 19:22:35.319250 ZQ Calibration : PASS
4823 19:22:35.322876 Jitter Meter : NO K
4824 19:22:35.323390 CBT Training : PASS
4825 19:22:35.325650 Write leveling : PASS
4826 19:22:35.328495 RX DQS gating : PASS
4827 19:22:35.328924 RX DQ/DQS(RDDQC) : PASS
4828 19:22:35.332052 TX DQ/DQS : PASS
4829 19:22:35.335591 RX DATLAT : PASS
4830 19:22:35.336063 RX DQ/DQS(Engine): PASS
4831 19:22:35.338549 TX OE : NO K
4832 19:22:35.338972 All Pass.
4833 19:22:35.339309
4834 19:22:35.342144 CH 1, Rank 0
4835 19:22:35.342561 SW Impedance : PASS
4836 19:22:35.345185 DUTY Scan : NO K
4837 19:22:35.349037 ZQ Calibration : PASS
4838 19:22:35.349563 Jitter Meter : NO K
4839 19:22:35.351951 CBT Training : PASS
4840 19:22:35.355482 Write leveling : PASS
4841 19:22:35.356002 RX DQS gating : PASS
4842 19:22:35.358642 RX DQ/DQS(RDDQC) : PASS
4843 19:22:35.361501 TX DQ/DQS : PASS
4844 19:22:35.361925 RX DATLAT : PASS
4845 19:22:35.365037 RX DQ/DQS(Engine): PASS
4846 19:22:35.368474 TX OE : NO K
4847 19:22:35.368894 All Pass.
4848 19:22:35.369235
4849 19:22:35.369546 CH 1, Rank 1
4850 19:22:35.371971 SW Impedance : PASS
4851 19:22:35.375269 DUTY Scan : NO K
4852 19:22:35.375687 ZQ Calibration : PASS
4853 19:22:35.378615 Jitter Meter : NO K
4854 19:22:35.381921 CBT Training : PASS
4855 19:22:35.382350 Write leveling : PASS
4856 19:22:35.384848 RX DQS gating : PASS
4857 19:22:35.388189 RX DQ/DQS(RDDQC) : PASS
4858 19:22:35.388609 TX DQ/DQS : PASS
4859 19:22:35.391604 RX DATLAT : PASS
4860 19:22:35.392157 RX DQ/DQS(Engine): PASS
4861 19:22:35.394932 TX OE : NO K
4862 19:22:35.395358 All Pass.
4863 19:22:35.395695
4864 19:22:35.398014 DramC Write-DBI off
4865 19:22:35.401620 PER_BANK_REFRESH: Hybrid Mode
4866 19:22:35.402042 TX_TRACKING: ON
4867 19:22:35.411368 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4868 19:22:35.414857 [FAST_K] Save calibration result to emmc
4869 19:22:35.418152 dramc_set_vcore_voltage set vcore to 662500
4870 19:22:35.421740 Read voltage for 933, 3
4871 19:22:35.422158 Vio18 = 0
4872 19:22:35.422532 Vcore = 662500
4873 19:22:35.424866 Vdram = 0
4874 19:22:35.425283 Vddq = 0
4875 19:22:35.425619 Vmddr = 0
4876 19:22:35.431448 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4877 19:22:35.438192 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4878 19:22:35.438877 MEM_TYPE=3, freq_sel=17
4879 19:22:35.441056 sv_algorithm_assistance_LP4_1600
4880 19:22:35.444174 ============ PULL DRAM RESETB DOWN ============
4881 19:22:35.450899 ========== PULL DRAM RESETB DOWN end =========
4882 19:22:35.454579 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4883 19:22:35.457608 ===================================
4884 19:22:35.460713 LPDDR4 DRAM CONFIGURATION
4885 19:22:35.464392 ===================================
4886 19:22:35.464816 EX_ROW_EN[0] = 0x0
4887 19:22:35.467311 EX_ROW_EN[1] = 0x0
4888 19:22:35.467798 LP4Y_EN = 0x0
4889 19:22:35.470837 WORK_FSP = 0x0
4890 19:22:35.474168 WL = 0x3
4891 19:22:35.474597 RL = 0x3
4892 19:22:35.477037 BL = 0x2
4893 19:22:35.477519 RPST = 0x0
4894 19:22:35.480731 RD_PRE = 0x0
4895 19:22:35.481240 WR_PRE = 0x1
4896 19:22:35.483773 WR_PST = 0x0
4897 19:22:35.484218 DBI_WR = 0x0
4898 19:22:35.487074 DBI_RD = 0x0
4899 19:22:35.487586 OTF = 0x1
4900 19:22:35.490117 ===================================
4901 19:22:35.493928 ===================================
4902 19:22:35.496980 ANA top config
4903 19:22:35.500026 ===================================
4904 19:22:35.500458 DLL_ASYNC_EN = 0
4905 19:22:35.503607 ALL_SLAVE_EN = 1
4906 19:22:35.506645 NEW_RANK_MODE = 1
4907 19:22:35.509992 DLL_IDLE_MODE = 1
4908 19:22:35.513481 LP45_APHY_COMB_EN = 1
4909 19:22:35.514169 TX_ODT_DIS = 1
4910 19:22:35.516424 NEW_8X_MODE = 1
4911 19:22:35.520037 ===================================
4912 19:22:35.523012 ===================================
4913 19:22:35.526387 data_rate = 1866
4914 19:22:35.529902 CKR = 1
4915 19:22:35.533367 DQ_P2S_RATIO = 8
4916 19:22:35.536450 ===================================
4917 19:22:35.539468 CA_P2S_RATIO = 8
4918 19:22:35.540009 DQ_CA_OPEN = 0
4919 19:22:35.542893 DQ_SEMI_OPEN = 0
4920 19:22:35.545966 CA_SEMI_OPEN = 0
4921 19:22:35.549699 CA_FULL_RATE = 0
4922 19:22:35.552662 DQ_CKDIV4_EN = 1
4923 19:22:35.556331 CA_CKDIV4_EN = 1
4924 19:22:35.556829 CA_PREDIV_EN = 0
4925 19:22:35.559470 PH8_DLY = 0
4926 19:22:35.562571 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4927 19:22:35.566030 DQ_AAMCK_DIV = 4
4928 19:22:35.569177 CA_AAMCK_DIV = 4
4929 19:22:35.572684 CA_ADMCK_DIV = 4
4930 19:22:35.573204 DQ_TRACK_CA_EN = 0
4931 19:22:35.576145 CA_PICK = 933
4932 19:22:35.579024 CA_MCKIO = 933
4933 19:22:35.582763 MCKIO_SEMI = 0
4934 19:22:35.585810 PLL_FREQ = 3732
4935 19:22:35.589447 DQ_UI_PI_RATIO = 32
4936 19:22:35.592448 CA_UI_PI_RATIO = 0
4937 19:22:35.595522 ===================================
4938 19:22:35.599130 ===================================
4939 19:22:35.599637 memory_type:LPDDR4
4940 19:22:35.602288 GP_NUM : 10
4941 19:22:35.605781 SRAM_EN : 1
4942 19:22:35.606274 MD32_EN : 0
4943 19:22:35.608759 ===================================
4944 19:22:35.612192 [ANA_INIT] >>>>>>>>>>>>>>
4945 19:22:35.615681 <<<<<< [CONFIGURE PHASE]: ANA_TX
4946 19:22:35.618690 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4947 19:22:35.622460 ===================================
4948 19:22:35.625278 data_rate = 1866,PCW = 0X8f00
4949 19:22:35.628953 ===================================
4950 19:22:35.631965 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4951 19:22:35.635590 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4952 19:22:35.641783 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4953 19:22:35.644971 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4954 19:22:35.652299 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4955 19:22:35.655262 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4956 19:22:35.655790 [ANA_INIT] flow start
4957 19:22:35.658904 [ANA_INIT] PLL >>>>>>>>
4958 19:22:35.661580 [ANA_INIT] PLL <<<<<<<<
4959 19:22:35.662008 [ANA_INIT] MIDPI >>>>>>>>
4960 19:22:35.665639 [ANA_INIT] MIDPI <<<<<<<<
4961 19:22:35.668523 [ANA_INIT] DLL >>>>>>>>
4962 19:22:35.669052 [ANA_INIT] flow end
4963 19:22:35.671994 ============ LP4 DIFF to SE enter ============
4964 19:22:35.678297 ============ LP4 DIFF to SE exit ============
4965 19:22:35.678827 [ANA_INIT] <<<<<<<<<<<<<
4966 19:22:35.681438 [Flow] Enable top DCM control >>>>>
4967 19:22:35.684803 [Flow] Enable top DCM control <<<<<
4968 19:22:35.688364 Enable DLL master slave shuffle
4969 19:22:35.694482 ==============================================================
4970 19:22:35.698271 Gating Mode config
4971 19:22:35.701085 ==============================================================
4972 19:22:35.704738 Config description:
4973 19:22:35.714252 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4974 19:22:35.721108 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4975 19:22:35.724552 SELPH_MODE 0: By rank 1: By Phase
4976 19:22:35.730984 ==============================================================
4977 19:22:35.733896 GAT_TRACK_EN = 1
4978 19:22:35.737347 RX_GATING_MODE = 2
4979 19:22:35.740793 RX_GATING_TRACK_MODE = 2
4980 19:22:35.744429 SELPH_MODE = 1
4981 19:22:35.744847 PICG_EARLY_EN = 1
4982 19:22:35.747282 VALID_LAT_VALUE = 1
4983 19:22:35.753924 ==============================================================
4984 19:22:35.757239 Enter into Gating configuration >>>>
4985 19:22:35.760554 Exit from Gating configuration <<<<
4986 19:22:35.763804 Enter into DVFS_PRE_config >>>>>
4987 19:22:35.773781 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4988 19:22:35.776833 Exit from DVFS_PRE_config <<<<<
4989 19:22:35.780399 Enter into PICG configuration >>>>
4990 19:22:35.783393 Exit from PICG configuration <<<<
4991 19:22:35.786940 [RX_INPUT] configuration >>>>>
4992 19:22:35.790105 [RX_INPUT] configuration <<<<<
4993 19:22:35.796788 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4994 19:22:35.799781 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4995 19:22:35.806425 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4996 19:22:35.813277 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4997 19:22:35.820143 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4998 19:22:35.826116 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4999 19:22:35.829701 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5000 19:22:35.832797 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5001 19:22:35.835984 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5002 19:22:35.843496 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5003 19:22:35.845723 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5004 19:22:35.849465 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5005 19:22:35.852419 ===================================
5006 19:22:35.856049 LPDDR4 DRAM CONFIGURATION
5007 19:22:35.858816 ===================================
5008 19:22:35.862281 EX_ROW_EN[0] = 0x0
5009 19:22:35.862864 EX_ROW_EN[1] = 0x0
5010 19:22:35.865691 LP4Y_EN = 0x0
5011 19:22:35.866272 WORK_FSP = 0x0
5012 19:22:35.869054 WL = 0x3
5013 19:22:35.869599 RL = 0x3
5014 19:22:35.872341 BL = 0x2
5015 19:22:35.872759 RPST = 0x0
5016 19:22:35.875452 RD_PRE = 0x0
5017 19:22:35.875532 WR_PRE = 0x1
5018 19:22:35.879233 WR_PST = 0x0
5019 19:22:35.879324 DBI_WR = 0x0
5020 19:22:35.881874 DBI_RD = 0x0
5021 19:22:35.881967 OTF = 0x1
5022 19:22:35.885155 ===================================
5023 19:22:35.891650 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5024 19:22:35.895089 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5025 19:22:35.898050 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5026 19:22:35.901674 ===================================
5027 19:22:35.905277 LPDDR4 DRAM CONFIGURATION
5028 19:22:35.908250 ===================================
5029 19:22:35.911470 EX_ROW_EN[0] = 0x10
5030 19:22:35.911542 EX_ROW_EN[1] = 0x0
5031 19:22:35.914699 LP4Y_EN = 0x0
5032 19:22:35.914771 WORK_FSP = 0x0
5033 19:22:35.917778 WL = 0x3
5034 19:22:35.917880 RL = 0x3
5035 19:22:35.921503 BL = 0x2
5036 19:22:35.921574 RPST = 0x0
5037 19:22:35.924786 RD_PRE = 0x0
5038 19:22:35.924913 WR_PRE = 0x1
5039 19:22:35.927849 WR_PST = 0x0
5040 19:22:35.928000 DBI_WR = 0x0
5041 19:22:35.931544 DBI_RD = 0x0
5042 19:22:35.931645 OTF = 0x1
5043 19:22:35.934623 ===================================
5044 19:22:35.940886 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5045 19:22:35.945937 nWR fixed to 30
5046 19:22:35.949726 [ModeRegInit_LP4] CH0 RK0
5047 19:22:35.949816 [ModeRegInit_LP4] CH0 RK1
5048 19:22:35.952704 [ModeRegInit_LP4] CH1 RK0
5049 19:22:35.956346 [ModeRegInit_LP4] CH1 RK1
5050 19:22:35.956440 match AC timing 9
5051 19:22:35.962796 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5052 19:22:35.965830 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5053 19:22:35.969650 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5054 19:22:35.976051 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5055 19:22:35.979413 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5056 19:22:35.979503 ==
5057 19:22:35.982414 Dram Type= 6, Freq= 0, CH_0, rank 0
5058 19:22:35.985429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5059 19:22:35.985554 ==
5060 19:22:35.992460 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5061 19:22:35.998873 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5062 19:22:36.001860 [CA 0] Center 38 (8~69) winsize 62
5063 19:22:36.005695 [CA 1] Center 37 (7~68) winsize 62
5064 19:22:36.008514 [CA 2] Center 34 (4~65) winsize 62
5065 19:22:36.011600 [CA 3] Center 34 (4~65) winsize 62
5066 19:22:36.015221 [CA 4] Center 33 (3~64) winsize 62
5067 19:22:36.018346 [CA 5] Center 32 (2~63) winsize 62
5068 19:22:36.018449
5069 19:22:36.021950 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5070 19:22:36.022028
5071 19:22:36.025012 [CATrainingPosCal] consider 1 rank data
5072 19:22:36.028198 u2DelayCellTimex100 = 270/100 ps
5073 19:22:36.031993 CA0 delay=38 (8~69),Diff = 6 PI (37 cell)
5074 19:22:36.035029 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5075 19:22:36.038277 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5076 19:22:36.044618 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5077 19:22:36.048255 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5078 19:22:36.051525 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5079 19:22:36.051608
5080 19:22:36.055003 CA PerBit enable=1, Macro0, CA PI delay=32
5081 19:22:36.055095
5082 19:22:36.057922 [CBTSetCACLKResult] CA Dly = 32
5083 19:22:36.058002 CS Dly: 6 (0~37)
5084 19:22:36.061652 ==
5085 19:22:36.061736 Dram Type= 6, Freq= 0, CH_0, rank 1
5086 19:22:36.068175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5087 19:22:36.068257 ==
5088 19:22:36.071099 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5089 19:22:36.077307 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5090 19:22:36.081464 [CA 0] Center 38 (8~69) winsize 62
5091 19:22:36.084605 [CA 1] Center 38 (7~69) winsize 63
5092 19:22:36.088111 [CA 2] Center 35 (5~65) winsize 61
5093 19:22:36.091293 [CA 3] Center 34 (4~65) winsize 62
5094 19:22:36.094622 [CA 4] Center 33 (3~64) winsize 62
5095 19:22:36.097687 [CA 5] Center 33 (3~64) winsize 62
5096 19:22:36.097767
5097 19:22:36.101266 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5098 19:22:36.101346
5099 19:22:36.104706 [CATrainingPosCal] consider 2 rank data
5100 19:22:36.108353 u2DelayCellTimex100 = 270/100 ps
5101 19:22:36.111128 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5102 19:22:36.118341 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5103 19:22:36.120991 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5104 19:22:36.124688 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5105 19:22:36.127729 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5106 19:22:36.130932 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5107 19:22:36.131347
5108 19:22:36.134168 CA PerBit enable=1, Macro0, CA PI delay=33
5109 19:22:36.134579
5110 19:22:36.137692 [CBTSetCACLKResult] CA Dly = 33
5111 19:22:36.141260 CS Dly: 7 (0~39)
5112 19:22:36.141674
5113 19:22:36.143989 ----->DramcWriteLeveling(PI) begin...
5114 19:22:36.144412 ==
5115 19:22:36.147670 Dram Type= 6, Freq= 0, CH_0, rank 0
5116 19:22:36.150812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5117 19:22:36.151226 ==
5118 19:22:36.154571 Write leveling (Byte 0): 31 => 31
5119 19:22:36.157378 Write leveling (Byte 1): 29 => 29
5120 19:22:36.160970 DramcWriteLeveling(PI) end<-----
5121 19:22:36.161402
5122 19:22:36.161744 ==
5123 19:22:36.164044 Dram Type= 6, Freq= 0, CH_0, rank 0
5124 19:22:36.167537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5125 19:22:36.168130 ==
5126 19:22:36.170548 [Gating] SW mode calibration
5127 19:22:36.176868 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5128 19:22:36.183263 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5129 19:22:36.187001 0 14 0 | B1->B0 | 2424 3232 | 0 1 | (0 0) (0 0)
5130 19:22:36.193496 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5131 19:22:36.196413 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5132 19:22:36.200514 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5133 19:22:36.206512 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5134 19:22:36.209610 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5135 19:22:36.213156 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5136 19:22:36.220043 0 14 28 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (1 1)
5137 19:22:36.222886 0 15 0 | B1->B0 | 3131 2323 | 0 0 | (0 1) (0 0)
5138 19:22:36.226476 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5139 19:22:36.233215 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5140 19:22:36.235940 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5141 19:22:36.239096 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5142 19:22:36.245925 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5143 19:22:36.249203 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5144 19:22:36.252600 0 15 28 | B1->B0 | 2323 3434 | 0 0 | (0 0) (1 1)
5145 19:22:36.259070 1 0 0 | B1->B0 | 3434 4545 | 1 0 | (0 0) (0 0)
5146 19:22:36.262601 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5147 19:22:36.265546 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5148 19:22:36.272120 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5149 19:22:36.275216 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5150 19:22:36.278993 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5151 19:22:36.285538 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5152 19:22:36.288694 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5153 19:22:36.291768 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5154 19:22:36.298277 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 19:22:36.301762 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 19:22:36.305116 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 19:22:36.311136 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 19:22:36.314953 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 19:22:36.318144 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 19:22:36.324398 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 19:22:36.327707 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 19:22:36.330741 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 19:22:36.337443 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 19:22:36.341432 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 19:22:36.344191 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 19:22:36.350571 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 19:22:36.354168 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5168 19:22:36.357215 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5169 19:22:36.363487 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5170 19:22:36.367127 Total UI for P1: 0, mck2ui 16
5171 19:22:36.370468 best dqsien dly found for B0: ( 1, 2, 26)
5172 19:22:36.373623 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5173 19:22:36.376748 Total UI for P1: 0, mck2ui 16
5174 19:22:36.380290 best dqsien dly found for B1: ( 1, 3, 0)
5175 19:22:36.383237 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5176 19:22:36.387196 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5177 19:22:36.387304
5178 19:22:36.390156 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5179 19:22:36.396843 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5180 19:22:36.396924 [Gating] SW calibration Done
5181 19:22:36.396990 ==
5182 19:22:36.400010 Dram Type= 6, Freq= 0, CH_0, rank 0
5183 19:22:36.406554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5184 19:22:36.406635 ==
5185 19:22:36.406699 RX Vref Scan: 0
5186 19:22:36.406777
5187 19:22:36.409398 RX Vref 0 -> 0, step: 1
5188 19:22:36.409479
5189 19:22:36.413254 RX Delay -80 -> 252, step: 8
5190 19:22:36.416745 iDelay=200, Bit 0, Center 107 (16 ~ 199) 184
5191 19:22:36.419804 iDelay=200, Bit 1, Center 107 (16 ~ 199) 184
5192 19:22:36.422961 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5193 19:22:36.429666 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5194 19:22:36.432749 iDelay=200, Bit 4, Center 107 (16 ~ 199) 184
5195 19:22:36.436017 iDelay=200, Bit 5, Center 91 (0 ~ 183) 184
5196 19:22:36.439046 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5197 19:22:36.442882 iDelay=200, Bit 7, Center 107 (16 ~ 199) 184
5198 19:22:36.448811 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5199 19:22:36.452458 iDelay=200, Bit 9, Center 75 (-16 ~ 167) 184
5200 19:22:36.456081 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5201 19:22:36.459217 iDelay=200, Bit 11, Center 87 (-8 ~ 183) 192
5202 19:22:36.462375 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5203 19:22:36.469039 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5204 19:22:36.471980 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5205 19:22:36.475401 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5206 19:22:36.475484 ==
5207 19:22:36.478539 Dram Type= 6, Freq= 0, CH_0, rank 0
5208 19:22:36.481763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5209 19:22:36.481846 ==
5210 19:22:36.485459 DQS Delay:
5211 19:22:36.485542 DQS0 = 0, DQS1 = 0
5212 19:22:36.485608 DQM Delay:
5213 19:22:36.488620 DQM0 = 102, DQM1 = 88
5214 19:22:36.488702 DQ Delay:
5215 19:22:36.491979 DQ0 =107, DQ1 =107, DQ2 =95, DQ3 =99
5216 19:22:36.495590 DQ4 =107, DQ5 =91, DQ6 =107, DQ7 =107
5217 19:22:36.498729 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =87
5218 19:22:36.501782 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5219 19:22:36.501864
5220 19:22:36.505052
5221 19:22:36.505135 ==
5222 19:22:36.508114 Dram Type= 6, Freq= 0, CH_0, rank 0
5223 19:22:36.511961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5224 19:22:36.512043 ==
5225 19:22:36.512108
5226 19:22:36.512169
5227 19:22:36.514948 TX Vref Scan disable
5228 19:22:36.515030 == TX Byte 0 ==
5229 19:22:36.521441 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5230 19:22:36.524763 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5231 19:22:36.524846 == TX Byte 1 ==
5232 19:22:36.531488 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5233 19:22:36.534592 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5234 19:22:36.534702 ==
5235 19:22:36.538212 Dram Type= 6, Freq= 0, CH_0, rank 0
5236 19:22:36.541673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5237 19:22:36.541793 ==
5238 19:22:36.541897
5239 19:22:36.541997
5240 19:22:36.544647 TX Vref Scan disable
5241 19:22:36.547734 == TX Byte 0 ==
5242 19:22:36.551535 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5243 19:22:36.554450 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5244 19:22:36.558066 == TX Byte 1 ==
5245 19:22:36.560964 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5246 19:22:36.564959 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5247 19:22:36.565364
5248 19:22:36.568289 [DATLAT]
5249 19:22:36.568865 Freq=933, CH0 RK0
5250 19:22:36.569292
5251 19:22:36.571092 DATLAT Default: 0xd
5252 19:22:36.571561 0, 0xFFFF, sum = 0
5253 19:22:36.574948 1, 0xFFFF, sum = 0
5254 19:22:36.575398 2, 0xFFFF, sum = 0
5255 19:22:36.577800 3, 0xFFFF, sum = 0
5256 19:22:36.578477 4, 0xFFFF, sum = 0
5257 19:22:36.580967 5, 0xFFFF, sum = 0
5258 19:22:36.581564 6, 0xFFFF, sum = 0
5259 19:22:36.584599 7, 0xFFFF, sum = 0
5260 19:22:36.588063 8, 0xFFFF, sum = 0
5261 19:22:36.588664 9, 0xFFFF, sum = 0
5262 19:22:36.590993 10, 0x0, sum = 1
5263 19:22:36.591518 11, 0x0, sum = 2
5264 19:22:36.592032 12, 0x0, sum = 3
5265 19:22:36.594393 13, 0x0, sum = 4
5266 19:22:36.594810 best_step = 11
5267 19:22:36.595140
5268 19:22:36.595444 ==
5269 19:22:36.597578 Dram Type= 6, Freq= 0, CH_0, rank 0
5270 19:22:36.604548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5271 19:22:36.604970 ==
5272 19:22:36.605338 RX Vref Scan: 1
5273 19:22:36.605661
5274 19:22:36.608127 RX Vref 0 -> 0, step: 1
5275 19:22:36.608549
5276 19:22:36.610674 RX Delay -61 -> 252, step: 4
5277 19:22:36.611273
5278 19:22:36.614359 Set Vref, RX VrefLevel [Byte0]: 58
5279 19:22:36.617468 [Byte1]: 49
5280 19:22:36.617914
5281 19:22:36.620545 Final RX Vref Byte 0 = 58 to rank0
5282 19:22:36.624117 Final RX Vref Byte 1 = 49 to rank0
5283 19:22:36.627169 Final RX Vref Byte 0 = 58 to rank1
5284 19:22:36.630732 Final RX Vref Byte 1 = 49 to rank1==
5285 19:22:36.633595 Dram Type= 6, Freq= 0, CH_0, rank 0
5286 19:22:36.637127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5287 19:22:36.640219 ==
5288 19:22:36.640306 DQS Delay:
5289 19:22:36.640372 DQS0 = 0, DQS1 = 0
5290 19:22:36.643692 DQM Delay:
5291 19:22:36.643801 DQM0 = 102, DQM1 = 90
5292 19:22:36.646483 DQ Delay:
5293 19:22:36.650266 DQ0 =104, DQ1 =102, DQ2 =98, DQ3 =98
5294 19:22:36.653276 DQ4 =104, DQ5 =94, DQ6 =110, DQ7 =110
5295 19:22:36.656908 DQ8 =80, DQ9 =76, DQ10 =92, DQ11 =86
5296 19:22:36.659847 DQ12 =98, DQ13 =94, DQ14 =98, DQ15 =96
5297 19:22:36.659939
5298 19:22:36.660013
5299 19:22:36.666671 [DQSOSCAuto] RK0, (LSB)MR18= 0x1813, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 414 ps
5300 19:22:36.669852 CH0 RK0: MR19=505, MR18=1813
5301 19:22:36.676575 CH0_RK0: MR19=0x505, MR18=0x1813, DQSOSC=414, MR23=63, INC=63, DEC=42
5302 19:22:36.676663
5303 19:22:36.679689 ----->DramcWriteLeveling(PI) begin...
5304 19:22:36.679774 ==
5305 19:22:36.682759 Dram Type= 6, Freq= 0, CH_0, rank 1
5306 19:22:36.686379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5307 19:22:36.686463 ==
5308 19:22:36.689369 Write leveling (Byte 0): 32 => 32
5309 19:22:36.692842 Write leveling (Byte 1): 29 => 29
5310 19:22:36.696256 DramcWriteLeveling(PI) end<-----
5311 19:22:36.696365
5312 19:22:36.696466 ==
5313 19:22:36.699177 Dram Type= 6, Freq= 0, CH_0, rank 1
5314 19:22:36.702359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5315 19:22:36.705820 ==
5316 19:22:36.705932 [Gating] SW mode calibration
5317 19:22:36.715586 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5318 19:22:36.719505 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5319 19:22:36.722248 0 14 0 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
5320 19:22:36.728608 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5321 19:22:36.732297 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5322 19:22:36.735278 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5323 19:22:36.742070 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5324 19:22:36.745352 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5325 19:22:36.748742 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5326 19:22:36.755352 0 14 28 | B1->B0 | 3434 2e2e | 1 0 | (1 0) (0 0)
5327 19:22:36.758444 0 15 0 | B1->B0 | 3131 2727 | 0 0 | (1 1) (1 1)
5328 19:22:36.762235 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
5329 19:22:36.768395 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5330 19:22:36.771838 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5331 19:22:36.774933 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5332 19:22:36.781775 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5333 19:22:36.784944 0 15 24 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
5334 19:22:36.791091 0 15 28 | B1->B0 | 2928 3c3c | 1 0 | (0 0) (0 0)
5335 19:22:36.794703 1 0 0 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
5336 19:22:36.797817 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5337 19:22:36.801582 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5338 19:22:36.808267 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5339 19:22:36.811115 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5340 19:22:36.817861 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5341 19:22:36.820919 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5342 19:22:36.824396 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 19:22:36.831103 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5344 19:22:36.834245 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 19:22:36.837916 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 19:22:36.844396 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 19:22:36.847419 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 19:22:36.850411 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 19:22:36.857118 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 19:22:36.860481 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 19:22:36.863852 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 19:22:36.870507 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 19:22:36.874294 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 19:22:36.877194 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 19:22:36.883517 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 19:22:36.887434 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 19:22:36.890417 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5358 19:22:36.896692 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5359 19:22:36.900280 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5360 19:22:36.903343 Total UI for P1: 0, mck2ui 16
5361 19:22:36.906960 best dqsien dly found for B0: ( 1, 2, 26)
5362 19:22:36.909897 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5363 19:22:36.913133 Total UI for P1: 0, mck2ui 16
5364 19:22:36.916329 best dqsien dly found for B1: ( 1, 2, 30)
5365 19:22:36.919848 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5366 19:22:36.922759 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5367 19:22:36.922945
5368 19:22:36.929724 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5369 19:22:36.932890 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5370 19:22:36.933070 [Gating] SW calibration Done
5371 19:22:36.936506 ==
5372 19:22:36.939626 Dram Type= 6, Freq= 0, CH_0, rank 1
5373 19:22:36.942727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5374 19:22:36.943147 ==
5375 19:22:36.943481 RX Vref Scan: 0
5376 19:22:36.943796
5377 19:22:36.946429 RX Vref 0 -> 0, step: 1
5378 19:22:36.946969
5379 19:22:36.949487 RX Delay -80 -> 252, step: 8
5380 19:22:36.953059 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5381 19:22:36.956012 iDelay=200, Bit 1, Center 103 (8 ~ 199) 192
5382 19:22:36.959264 iDelay=200, Bit 2, Center 95 (8 ~ 183) 176
5383 19:22:36.965846 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5384 19:22:36.969307 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5385 19:22:36.972786 iDelay=200, Bit 5, Center 91 (0 ~ 183) 184
5386 19:22:36.975612 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5387 19:22:36.979073 iDelay=200, Bit 7, Center 107 (16 ~ 199) 184
5388 19:22:36.985416 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5389 19:22:36.989134 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5390 19:22:36.992313 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5391 19:22:36.995607 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5392 19:22:36.999056 iDelay=200, Bit 12, Center 99 (8 ~ 191) 184
5393 19:22:37.005859 iDelay=200, Bit 13, Center 99 (8 ~ 191) 184
5394 19:22:37.008981 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5395 19:22:37.011948 iDelay=200, Bit 15, Center 91 (0 ~ 183) 184
5396 19:22:37.012324 ==
5397 19:22:37.015547 Dram Type= 6, Freq= 0, CH_0, rank 1
5398 19:22:37.018563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5399 19:22:37.019340 ==
5400 19:22:37.021637 DQS Delay:
5401 19:22:37.021967 DQS0 = 0, DQS1 = 0
5402 19:22:37.022258 DQM Delay:
5403 19:22:37.025345 DQM0 = 100, DQM1 = 90
5404 19:22:37.025749 DQ Delay:
5405 19:22:37.028238 DQ0 =99, DQ1 =103, DQ2 =95, DQ3 =99
5406 19:22:37.031443 DQ4 =103, DQ5 =91, DQ6 =107, DQ7 =107
5407 19:22:37.034965 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5408 19:22:37.038203 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =91
5409 19:22:37.038605
5410 19:22:37.041469
5411 19:22:37.041852 ==
5412 19:22:37.045043 Dram Type= 6, Freq= 0, CH_0, rank 1
5413 19:22:37.048088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5414 19:22:37.048172 ==
5415 19:22:37.048238
5416 19:22:37.048300
5417 19:22:37.051005 TX Vref Scan disable
5418 19:22:37.051116 == TX Byte 0 ==
5419 19:22:37.057822 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5420 19:22:37.060747 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5421 19:22:37.060859 == TX Byte 1 ==
5422 19:22:37.067619 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5423 19:22:37.071074 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5424 19:22:37.071186 ==
5425 19:22:37.074094 Dram Type= 6, Freq= 0, CH_0, rank 1
5426 19:22:37.077624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5427 19:22:37.077734 ==
5428 19:22:37.077831
5429 19:22:37.077925
5430 19:22:37.080625 TX Vref Scan disable
5431 19:22:37.084269 == TX Byte 0 ==
5432 19:22:37.087319 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5433 19:22:37.090667 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5434 19:22:37.094057 == TX Byte 1 ==
5435 19:22:37.097270 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5436 19:22:37.100477 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5437 19:22:37.103855
5438 19:22:37.103972 [DATLAT]
5439 19:22:37.104067 Freq=933, CH0 RK1
5440 19:22:37.104161
5441 19:22:37.107086 DATLAT Default: 0xb
5442 19:22:37.107200 0, 0xFFFF, sum = 0
5443 19:22:37.110084 1, 0xFFFF, sum = 0
5444 19:22:37.110197 2, 0xFFFF, sum = 0
5445 19:22:37.113973 3, 0xFFFF, sum = 0
5446 19:22:37.114057 4, 0xFFFF, sum = 0
5447 19:22:37.116913 5, 0xFFFF, sum = 0
5448 19:22:37.120400 6, 0xFFFF, sum = 0
5449 19:22:37.120512 7, 0xFFFF, sum = 0
5450 19:22:37.123618 8, 0xFFFF, sum = 0
5451 19:22:37.123727 9, 0xFFFF, sum = 0
5452 19:22:37.126628 10, 0x0, sum = 1
5453 19:22:37.126699 11, 0x0, sum = 2
5454 19:22:37.126762 12, 0x0, sum = 3
5455 19:22:37.130481 13, 0x0, sum = 4
5456 19:22:37.130564 best_step = 11
5457 19:22:37.130629
5458 19:22:37.133503 ==
5459 19:22:37.133585 Dram Type= 6, Freq= 0, CH_0, rank 1
5460 19:22:37.140221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5461 19:22:37.140304 ==
5462 19:22:37.140370 RX Vref Scan: 0
5463 19:22:37.140431
5464 19:22:37.143461 RX Vref 0 -> 0, step: 1
5465 19:22:37.143540
5466 19:22:37.147035 RX Delay -61 -> 252, step: 4
5467 19:22:37.150134 iDelay=195, Bit 0, Center 100 (15 ~ 186) 172
5468 19:22:37.157098 iDelay=195, Bit 1, Center 102 (15 ~ 190) 176
5469 19:22:37.159947 iDelay=195, Bit 2, Center 94 (11 ~ 178) 168
5470 19:22:37.163046 iDelay=195, Bit 3, Center 98 (11 ~ 186) 176
5471 19:22:37.166629 iDelay=195, Bit 4, Center 104 (19 ~ 190) 172
5472 19:22:37.169537 iDelay=195, Bit 5, Center 92 (7 ~ 178) 172
5473 19:22:37.176566 iDelay=195, Bit 6, Center 110 (27 ~ 194) 168
5474 19:22:37.179868 iDelay=195, Bit 7, Center 106 (19 ~ 194) 176
5475 19:22:37.182771 iDelay=195, Bit 8, Center 80 (-5 ~ 166) 172
5476 19:22:37.186178 iDelay=195, Bit 9, Center 78 (-9 ~ 166) 176
5477 19:22:37.189385 iDelay=195, Bit 10, Center 92 (7 ~ 178) 172
5478 19:22:37.195977 iDelay=195, Bit 11, Center 84 (-1 ~ 170) 172
5479 19:22:37.199376 iDelay=195, Bit 12, Center 96 (11 ~ 182) 172
5480 19:22:37.202593 iDelay=195, Bit 13, Center 96 (11 ~ 182) 172
5481 19:22:37.205866 iDelay=195, Bit 14, Center 102 (19 ~ 186) 168
5482 19:22:37.209087 iDelay=195, Bit 15, Center 96 (11 ~ 182) 172
5483 19:22:37.212478 ==
5484 19:22:37.216054 Dram Type= 6, Freq= 0, CH_0, rank 1
5485 19:22:37.219145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5486 19:22:37.219797 ==
5487 19:22:37.220357 DQS Delay:
5488 19:22:37.222548 DQS0 = 0, DQS1 = 0
5489 19:22:37.223100 DQM Delay:
5490 19:22:37.225631 DQM0 = 100, DQM1 = 90
5491 19:22:37.226153 DQ Delay:
5492 19:22:37.229228 DQ0 =100, DQ1 =102, DQ2 =94, DQ3 =98
5493 19:22:37.232144 DQ4 =104, DQ5 =92, DQ6 =110, DQ7 =106
5494 19:22:37.235730 DQ8 =80, DQ9 =78, DQ10 =92, DQ11 =84
5495 19:22:37.238671 DQ12 =96, DQ13 =96, DQ14 =102, DQ15 =96
5496 19:22:37.239139
5497 19:22:37.239605
5498 19:22:37.249288 [DQSOSCAuto] RK1, (LSB)MR18= 0x1714, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 414 ps
5499 19:22:37.249833 CH0 RK1: MR19=505, MR18=1714
5500 19:22:37.255266 CH0_RK1: MR19=0x505, MR18=0x1714, DQSOSC=414, MR23=63, INC=63, DEC=42
5501 19:22:37.258767 [RxdqsGatingPostProcess] freq 933
5502 19:22:37.264858 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5503 19:22:37.268710 best DQS0 dly(2T, 0.5T) = (0, 10)
5504 19:22:37.271761 best DQS1 dly(2T, 0.5T) = (0, 11)
5505 19:22:37.274711 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5506 19:22:37.278257 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5507 19:22:37.281316 best DQS0 dly(2T, 0.5T) = (0, 10)
5508 19:22:37.284942 best DQS1 dly(2T, 0.5T) = (0, 10)
5509 19:22:37.287801 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5510 19:22:37.291158 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5511 19:22:37.291701 Pre-setting of DQS Precalculation
5512 19:22:37.297730 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5513 19:22:37.298268 ==
5514 19:22:37.301149 Dram Type= 6, Freq= 0, CH_1, rank 0
5515 19:22:37.304515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5516 19:22:37.305116 ==
5517 19:22:37.311144 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5518 19:22:37.317498 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5519 19:22:37.320921 [CA 0] Center 36 (6~67) winsize 62
5520 19:22:37.324147 [CA 1] Center 36 (6~67) winsize 62
5521 19:22:37.327513 [CA 2] Center 34 (4~65) winsize 62
5522 19:22:37.330391 [CA 3] Center 34 (4~64) winsize 61
5523 19:22:37.334074 [CA 4] Center 34 (4~65) winsize 62
5524 19:22:37.337098 [CA 5] Center 33 (3~64) winsize 62
5525 19:22:37.337246
5526 19:22:37.340323 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5527 19:22:37.340485
5528 19:22:37.343719 [CATrainingPosCal] consider 1 rank data
5529 19:22:37.347208 u2DelayCellTimex100 = 270/100 ps
5530 19:22:37.350263 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5531 19:22:37.353412 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5532 19:22:37.357067 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5533 19:22:37.360169 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5534 19:22:37.366727 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5535 19:22:37.369743 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5536 19:22:37.369847
5537 19:22:37.373592 CA PerBit enable=1, Macro0, CA PI delay=33
5538 19:22:37.373691
5539 19:22:37.376721 [CBTSetCACLKResult] CA Dly = 33
5540 19:22:37.376802 CS Dly: 5 (0~36)
5541 19:22:37.376896 ==
5542 19:22:37.379698 Dram Type= 6, Freq= 0, CH_1, rank 1
5543 19:22:37.386244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5544 19:22:37.386351 ==
5545 19:22:37.390034 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5546 19:22:37.396506 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5547 19:22:37.399371 [CA 0] Center 36 (6~67) winsize 62
5548 19:22:37.402845 [CA 1] Center 36 (6~67) winsize 62
5549 19:22:37.406056 [CA 2] Center 34 (4~65) winsize 62
5550 19:22:37.409464 [CA 3] Center 33 (3~64) winsize 62
5551 19:22:37.412681 [CA 4] Center 33 (3~64) winsize 62
5552 19:22:37.415734 [CA 5] Center 33 (3~63) winsize 61
5553 19:22:37.415817
5554 19:22:37.419060 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5555 19:22:37.419173
5556 19:22:37.422844 [CATrainingPosCal] consider 2 rank data
5557 19:22:37.425836 u2DelayCellTimex100 = 270/100 ps
5558 19:22:37.429223 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5559 19:22:37.435990 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5560 19:22:37.439034 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5561 19:22:37.442414 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5562 19:22:37.446045 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5563 19:22:37.449013 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5564 19:22:37.449095
5565 19:22:37.452373 CA PerBit enable=1, Macro0, CA PI delay=33
5566 19:22:37.452455
5567 19:22:37.456027 [CBTSetCACLKResult] CA Dly = 33
5568 19:22:37.456109 CS Dly: 6 (0~38)
5569 19:22:37.459087
5570 19:22:37.462163 ----->DramcWriteLeveling(PI) begin...
5571 19:22:37.462246 ==
5572 19:22:37.465843 Dram Type= 6, Freq= 0, CH_1, rank 0
5573 19:22:37.468803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5574 19:22:37.468885 ==
5575 19:22:37.471791 Write leveling (Byte 0): 28 => 28
5576 19:22:37.475526 Write leveling (Byte 1): 28 => 28
5577 19:22:37.478560 DramcWriteLeveling(PI) end<-----
5578 19:22:37.478642
5579 19:22:37.478707 ==
5580 19:22:37.481643 Dram Type= 6, Freq= 0, CH_1, rank 0
5581 19:22:37.485336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5582 19:22:37.485419 ==
5583 19:22:37.488413 [Gating] SW mode calibration
5584 19:22:37.494939 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5585 19:22:37.501474 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5586 19:22:37.505122 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5587 19:22:37.508008 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5588 19:22:37.514761 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5589 19:22:37.517762 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5590 19:22:37.521298 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5591 19:22:37.527773 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5592 19:22:37.531410 0 14 24 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 0)
5593 19:22:37.534707 0 14 28 | B1->B0 | 2828 2525 | 0 0 | (0 0) (0 0)
5594 19:22:37.541019 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5595 19:22:37.544265 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5596 19:22:37.547477 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5597 19:22:37.554439 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5598 19:22:37.557809 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5599 19:22:37.561174 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5600 19:22:37.567781 0 15 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
5601 19:22:37.570754 0 15 28 | B1->B0 | 3b3b 4646 | 0 0 | (1 1) (0 0)
5602 19:22:37.573921 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5603 19:22:37.580584 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5604 19:22:37.584232 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5605 19:22:37.587592 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5606 19:22:37.594048 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5607 19:22:37.596926 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5608 19:22:37.600493 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5609 19:22:37.606964 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 19:22:37.610522 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5611 19:22:37.613584 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 19:22:37.620065 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 19:22:37.623499 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 19:22:37.626829 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 19:22:37.633438 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 19:22:37.636491 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 19:22:37.643273 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 19:22:37.646250 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 19:22:37.649456 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 19:22:37.656584 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 19:22:37.659483 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 19:22:37.662966 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 19:22:37.669786 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 19:22:37.672725 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5625 19:22:37.676170 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5626 19:22:37.682854 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5627 19:22:37.682965 Total UI for P1: 0, mck2ui 16
5628 19:22:37.685805 best dqsien dly found for B0: ( 1, 2, 26)
5629 19:22:37.689504 Total UI for P1: 0, mck2ui 16
5630 19:22:37.692676 best dqsien dly found for B1: ( 1, 2, 26)
5631 19:22:37.699312 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5632 19:22:37.702361 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5633 19:22:37.702534
5634 19:22:37.706051 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5635 19:22:37.709029 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5636 19:22:37.712489 [Gating] SW calibration Done
5637 19:22:37.712732 ==
5638 19:22:37.715553 Dram Type= 6, Freq= 0, CH_1, rank 0
5639 19:22:37.719109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5640 19:22:37.719497 ==
5641 19:22:37.722162 RX Vref Scan: 0
5642 19:22:37.722546
5643 19:22:37.722853 RX Vref 0 -> 0, step: 1
5644 19:22:37.723192
5645 19:22:37.725632 RX Delay -80 -> 252, step: 8
5646 19:22:37.729050 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5647 19:22:37.735696 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5648 19:22:37.739224 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5649 19:22:37.742278 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5650 19:22:37.745119 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5651 19:22:37.748782 iDelay=208, Bit 5, Center 107 (16 ~ 199) 184
5652 19:22:37.751747 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5653 19:22:37.758615 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5654 19:22:37.761630 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5655 19:22:37.765269 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5656 19:22:37.768394 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5657 19:22:37.771992 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5658 19:22:37.778082 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5659 19:22:37.781496 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5660 19:22:37.784622 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5661 19:22:37.788397 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5662 19:22:37.788480 ==
5663 19:22:37.790831 Dram Type= 6, Freq= 0, CH_1, rank 0
5664 19:22:37.797753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5665 19:22:37.797841 ==
5666 19:22:37.797912 DQS Delay:
5667 19:22:37.797977 DQS0 = 0, DQS1 = 0
5668 19:22:37.800879 DQM Delay:
5669 19:22:37.800965 DQM0 = 99, DQM1 = 95
5670 19:22:37.804428 DQ Delay:
5671 19:22:37.807440 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5672 19:22:37.810562 DQ4 =95, DQ5 =107, DQ6 =111, DQ7 =95
5673 19:22:37.814223 DQ8 =79, DQ9 =87, DQ10 =95, DQ11 =91
5674 19:22:37.817187 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5675 19:22:37.817279
5676 19:22:37.817349
5677 19:22:37.817412 ==
5678 19:22:37.820866 Dram Type= 6, Freq= 0, CH_1, rank 0
5679 19:22:37.824198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5680 19:22:37.824316 ==
5681 19:22:37.824417
5682 19:22:37.824511
5683 19:22:37.827299 TX Vref Scan disable
5684 19:22:37.830402 == TX Byte 0 ==
5685 19:22:37.833722 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5686 19:22:37.837065 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5687 19:22:37.840309 == TX Byte 1 ==
5688 19:22:37.843516 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5689 19:22:37.846972 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5690 19:22:37.847060 ==
5691 19:22:37.850304 Dram Type= 6, Freq= 0, CH_1, rank 0
5692 19:22:37.856799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5693 19:22:37.856887 ==
5694 19:22:37.856957
5695 19:22:37.857023
5696 19:22:37.857086 TX Vref Scan disable
5697 19:22:37.860549 == TX Byte 0 ==
5698 19:22:37.863997 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5699 19:22:37.870983 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5700 19:22:37.871086 == TX Byte 1 ==
5701 19:22:37.874409 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5702 19:22:37.880358 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5703 19:22:37.880480
5704 19:22:37.880577 [DATLAT]
5705 19:22:37.880667 Freq=933, CH1 RK0
5706 19:22:37.880756
5707 19:22:37.884127 DATLAT Default: 0xd
5708 19:22:37.887047 0, 0xFFFF, sum = 0
5709 19:22:37.887184 1, 0xFFFF, sum = 0
5710 19:22:37.890542 2, 0xFFFF, sum = 0
5711 19:22:37.890695 3, 0xFFFF, sum = 0
5712 19:22:37.893439 4, 0xFFFF, sum = 0
5713 19:22:37.893602 5, 0xFFFF, sum = 0
5714 19:22:37.897097 6, 0xFFFF, sum = 0
5715 19:22:37.897251 7, 0xFFFF, sum = 0
5716 19:22:37.899948 8, 0xFFFF, sum = 0
5717 19:22:37.900151 9, 0xFFFF, sum = 0
5718 19:22:37.903623 10, 0x0, sum = 1
5719 19:22:37.903793 11, 0x0, sum = 2
5720 19:22:37.906827 12, 0x0, sum = 3
5721 19:22:37.906993 13, 0x0, sum = 4
5722 19:22:37.910461 best_step = 11
5723 19:22:37.910592
5724 19:22:37.910725 ==
5725 19:22:37.913480 Dram Type= 6, Freq= 0, CH_1, rank 0
5726 19:22:37.916555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5727 19:22:37.916699 ==
5728 19:22:37.916821 RX Vref Scan: 1
5729 19:22:37.920171
5730 19:22:37.920322 RX Vref 0 -> 0, step: 1
5731 19:22:37.920442
5732 19:22:37.923210 RX Delay -61 -> 252, step: 4
5733 19:22:37.923364
5734 19:22:37.926745 Set Vref, RX VrefLevel [Byte0]: 51
5735 19:22:37.929827 [Byte1]: 51
5736 19:22:37.933699
5737 19:22:37.933862 Final RX Vref Byte 0 = 51 to rank0
5738 19:22:37.936751 Final RX Vref Byte 1 = 51 to rank0
5739 19:22:37.939802 Final RX Vref Byte 0 = 51 to rank1
5740 19:22:37.943020 Final RX Vref Byte 1 = 51 to rank1==
5741 19:22:37.946539 Dram Type= 6, Freq= 0, CH_1, rank 0
5742 19:22:37.952920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5743 19:22:37.953124 ==
5744 19:22:37.953300 DQS Delay:
5745 19:22:37.956199 DQS0 = 0, DQS1 = 0
5746 19:22:37.956425 DQM Delay:
5747 19:22:37.956611 DQM0 = 98, DQM1 = 95
5748 19:22:37.959751 DQ Delay:
5749 19:22:37.962785 DQ0 =104, DQ1 =92, DQ2 =88, DQ3 =100
5750 19:22:37.966396 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =94
5751 19:22:37.969344 DQ8 =80, DQ9 =84, DQ10 =94, DQ11 =88
5752 19:22:37.973004 DQ12 =104, DQ13 =104, DQ14 =102, DQ15 =104
5753 19:22:37.973202
5754 19:22:37.973379
5755 19:22:37.979694 [DQSOSCAuto] RK0, (LSB)MR18= 0xd1d, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 417 ps
5756 19:22:37.982822 CH1 RK0: MR19=505, MR18=D1D
5757 19:22:37.989412 CH1_RK0: MR19=0x505, MR18=0xD1D, DQSOSC=412, MR23=63, INC=63, DEC=42
5758 19:22:37.989741
5759 19:22:37.993087 ----->DramcWriteLeveling(PI) begin...
5760 19:22:37.993438 ==
5761 19:22:37.996113 Dram Type= 6, Freq= 0, CH_1, rank 1
5762 19:22:37.999160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5763 19:22:37.999728 ==
5764 19:22:38.002699 Write leveling (Byte 0): 23 => 23
5765 19:22:38.006402 Write leveling (Byte 1): 26 => 26
5766 19:22:38.009514 DramcWriteLeveling(PI) end<-----
5767 19:22:38.010039
5768 19:22:38.010535 ==
5769 19:22:38.012327 Dram Type= 6, Freq= 0, CH_1, rank 1
5770 19:22:38.018938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5771 19:22:38.019590 ==
5772 19:22:38.022359 [Gating] SW mode calibration
5773 19:22:38.028909 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5774 19:22:38.032262 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5775 19:22:38.038747 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5776 19:22:38.041816 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5777 19:22:38.045519 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5778 19:22:38.051989 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5779 19:22:38.055102 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5780 19:22:38.058679 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5781 19:22:38.065390 0 14 24 | B1->B0 | 3333 2e2e | 0 0 | (0 0) (0 0)
5782 19:22:38.068621 0 14 28 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
5783 19:22:38.071795 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5784 19:22:38.078074 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5785 19:22:38.081316 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5786 19:22:38.084405 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5787 19:22:38.091221 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5788 19:22:38.094341 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5789 19:22:38.097532 0 15 24 | B1->B0 | 2525 3433 | 1 1 | (0 0) (0 0)
5790 19:22:38.104521 0 15 28 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5791 19:22:38.107594 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5792 19:22:38.110789 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5793 19:22:38.117534 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5794 19:22:38.120591 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5795 19:22:38.124223 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5796 19:22:38.130572 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5797 19:22:38.134134 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5798 19:22:38.137320 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 19:22:38.143859 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 19:22:38.146847 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 19:22:38.150498 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 19:22:38.156857 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 19:22:38.160316 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 19:22:38.163431 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 19:22:38.170188 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 19:22:38.173330 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 19:22:38.176409 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 19:22:38.183174 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 19:22:38.186286 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 19:22:38.190046 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 19:22:38.196343 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 19:22:38.199977 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 19:22:38.203471 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5814 19:22:38.209431 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5815 19:22:38.209535 Total UI for P1: 0, mck2ui 16
5816 19:22:38.215943 best dqsien dly found for B0: ( 1, 2, 24)
5817 19:22:38.219528 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5818 19:22:38.222784 Total UI for P1: 0, mck2ui 16
5819 19:22:38.226254 best dqsien dly found for B1: ( 1, 2, 28)
5820 19:22:38.229361 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5821 19:22:38.232827 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5822 19:22:38.232930
5823 19:22:38.236186 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5824 19:22:38.239160 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5825 19:22:38.242659 [Gating] SW calibration Done
5826 19:22:38.242759 ==
5827 19:22:38.245718 Dram Type= 6, Freq= 0, CH_1, rank 1
5828 19:22:38.252374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5829 19:22:38.252476 ==
5830 19:22:38.252567 RX Vref Scan: 0
5831 19:22:38.252660
5832 19:22:38.255826 RX Vref 0 -> 0, step: 1
5833 19:22:38.255925
5834 19:22:38.258771 RX Delay -80 -> 252, step: 8
5835 19:22:38.262043 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5836 19:22:38.265812 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5837 19:22:38.268709 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5838 19:22:38.272241 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5839 19:22:38.278495 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5840 19:22:38.281827 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5841 19:22:38.285322 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5842 19:22:38.288744 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5843 19:22:38.291593 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5844 19:22:38.295100 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5845 19:22:38.301910 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5846 19:22:38.305050 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5847 19:22:38.308094 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5848 19:22:38.311831 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5849 19:22:38.314771 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5850 19:22:38.321554 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5851 19:22:38.321656 ==
5852 19:22:38.324675 Dram Type= 6, Freq= 0, CH_1, rank 1
5853 19:22:38.328348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5854 19:22:38.328451 ==
5855 19:22:38.328545 DQS Delay:
5856 19:22:38.331485 DQS0 = 0, DQS1 = 0
5857 19:22:38.331589 DQM Delay:
5858 19:22:38.334477 DQM0 = 97, DQM1 = 94
5859 19:22:38.334576 DQ Delay:
5860 19:22:38.337845 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =95
5861 19:22:38.341186 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5862 19:22:38.344323 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5863 19:22:38.347988 DQ12 =103, DQ13 =99, DQ14 =99, DQ15 =103
5864 19:22:38.348085
5865 19:22:38.348176
5866 19:22:38.348273 ==
5867 19:22:38.351130 Dram Type= 6, Freq= 0, CH_1, rank 1
5868 19:22:38.354792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5869 19:22:38.357682 ==
5870 19:22:38.357783
5871 19:22:38.357875
5872 19:22:38.357964 TX Vref Scan disable
5873 19:22:38.361366 == TX Byte 0 ==
5874 19:22:38.364428 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5875 19:22:38.368123 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5876 19:22:38.371069 == TX Byte 1 ==
5877 19:22:38.374680 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5878 19:22:38.381258 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5879 19:22:38.381359 ==
5880 19:22:38.384101 Dram Type= 6, Freq= 0, CH_1, rank 1
5881 19:22:38.387333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5882 19:22:38.387435 ==
5883 19:22:38.387524
5884 19:22:38.387620
5885 19:22:38.390840 TX Vref Scan disable
5886 19:22:38.390939 == TX Byte 0 ==
5887 19:22:38.397229 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5888 19:22:38.400590 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5889 19:22:38.400693 == TX Byte 1 ==
5890 19:22:38.407447 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5891 19:22:38.410488 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5892 19:22:38.410586
5893 19:22:38.410675 [DATLAT]
5894 19:22:38.413944 Freq=933, CH1 RK1
5895 19:22:38.414047
5896 19:22:38.414139 DATLAT Default: 0xb
5897 19:22:38.417274 0, 0xFFFF, sum = 0
5898 19:22:38.420411 1, 0xFFFF, sum = 0
5899 19:22:38.420500 2, 0xFFFF, sum = 0
5900 19:22:38.423601 3, 0xFFFF, sum = 0
5901 19:22:38.423706 4, 0xFFFF, sum = 0
5902 19:22:38.427205 5, 0xFFFF, sum = 0
5903 19:22:38.427279 6, 0xFFFF, sum = 0
5904 19:22:38.430316 7, 0xFFFF, sum = 0
5905 19:22:38.430417 8, 0xFFFF, sum = 0
5906 19:22:38.433951 9, 0xFFFF, sum = 0
5907 19:22:38.434050 10, 0x0, sum = 1
5908 19:22:38.436961 11, 0x0, sum = 2
5909 19:22:38.437060 12, 0x0, sum = 3
5910 19:22:38.440125 13, 0x0, sum = 4
5911 19:22:38.440225 best_step = 11
5912 19:22:38.440315
5913 19:22:38.440400 ==
5914 19:22:38.443686 Dram Type= 6, Freq= 0, CH_1, rank 1
5915 19:22:38.446909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5916 19:22:38.446990 ==
5917 19:22:38.450391 RX Vref Scan: 0
5918 19:22:38.450496
5919 19:22:38.453365 RX Vref 0 -> 0, step: 1
5920 19:22:38.453460
5921 19:22:38.453550 RX Delay -53 -> 252, step: 4
5922 19:22:38.461176 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5923 19:22:38.464769 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5924 19:22:38.467937 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5925 19:22:38.471422 iDelay=199, Bit 3, Center 94 (3 ~ 186) 184
5926 19:22:38.474765 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5927 19:22:38.481272 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5928 19:22:38.484461 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5929 19:22:38.487805 iDelay=199, Bit 7, Center 92 (-1 ~ 186) 188
5930 19:22:38.491229 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5931 19:22:38.494502 iDelay=199, Bit 9, Center 82 (-9 ~ 174) 184
5932 19:22:38.497786 iDelay=199, Bit 10, Center 92 (-1 ~ 186) 188
5933 19:22:38.504182 iDelay=199, Bit 11, Center 86 (-5 ~ 178) 184
5934 19:22:38.507767 iDelay=199, Bit 12, Center 100 (11 ~ 190) 180
5935 19:22:38.511142 iDelay=199, Bit 13, Center 100 (11 ~ 190) 180
5936 19:22:38.514057 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5937 19:22:38.520790 iDelay=199, Bit 15, Center 102 (11 ~ 194) 184
5938 19:22:38.520889 ==
5939 19:22:38.524050 Dram Type= 6, Freq= 0, CH_1, rank 1
5940 19:22:38.527226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5941 19:22:38.527323 ==
5942 19:22:38.527413 DQS Delay:
5943 19:22:38.530643 DQS0 = 0, DQS1 = 0
5944 19:22:38.530723 DQM Delay:
5945 19:22:38.534158 DQM0 = 96, DQM1 = 92
5946 19:22:38.534255 DQ Delay:
5947 19:22:38.537249 DQ0 =102, DQ1 =94, DQ2 =86, DQ3 =94
5948 19:22:38.540257 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =92
5949 19:22:38.543854 DQ8 =80, DQ9 =82, DQ10 =92, DQ11 =86
5950 19:22:38.546924 DQ12 =100, DQ13 =100, DQ14 =98, DQ15 =102
5951 19:22:38.547020
5952 19:22:38.547109
5953 19:22:38.557277 [DQSOSCAuto] RK1, (LSB)MR18= 0x1026, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 416 ps
5954 19:22:38.557382 CH1 RK1: MR19=505, MR18=1026
5955 19:22:38.563336 CH1_RK1: MR19=0x505, MR18=0x1026, DQSOSC=409, MR23=63, INC=64, DEC=43
5956 19:22:38.566768 [RxdqsGatingPostProcess] freq 933
5957 19:22:38.573545 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5958 19:22:38.576478 best DQS0 dly(2T, 0.5T) = (0, 10)
5959 19:22:38.580212 best DQS1 dly(2T, 0.5T) = (0, 10)
5960 19:22:38.583252 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5961 19:22:38.586222 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5962 19:22:38.589851 best DQS0 dly(2T, 0.5T) = (0, 10)
5963 19:22:38.592927 best DQS1 dly(2T, 0.5T) = (0, 10)
5964 19:22:38.596553 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5965 19:22:38.599255 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5966 19:22:38.602688 Pre-setting of DQS Precalculation
5967 19:22:38.605819 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5968 19:22:38.612493 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5969 19:22:38.619386 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5970 19:22:38.619494
5971 19:22:38.622352
5972 19:22:38.622469 [Calibration Summary] 1866 Mbps
5973 19:22:38.625832 CH 0, Rank 0
5974 19:22:38.625935 SW Impedance : PASS
5975 19:22:38.629441 DUTY Scan : NO K
5976 19:22:38.632253 ZQ Calibration : PASS
5977 19:22:38.632351 Jitter Meter : NO K
5978 19:22:38.635862 CBT Training : PASS
5979 19:22:38.638951 Write leveling : PASS
5980 19:22:38.639049 RX DQS gating : PASS
5981 19:22:38.642177 RX DQ/DQS(RDDQC) : PASS
5982 19:22:38.645340 TX DQ/DQS : PASS
5983 19:22:38.645443 RX DATLAT : PASS
5984 19:22:38.649005 RX DQ/DQS(Engine): PASS
5985 19:22:38.652067 TX OE : NO K
5986 19:22:38.652152 All Pass.
5987 19:22:38.652217
5988 19:22:38.652275 CH 0, Rank 1
5989 19:22:38.655186 SW Impedance : PASS
5990 19:22:38.658875 DUTY Scan : NO K
5991 19:22:38.658973 ZQ Calibration : PASS
5992 19:22:38.662201 Jitter Meter : NO K
5993 19:22:38.665485 CBT Training : PASS
5994 19:22:38.665573 Write leveling : PASS
5995 19:22:38.668388 RX DQS gating : PASS
5996 19:22:38.671825 RX DQ/DQS(RDDQC) : PASS
5997 19:22:38.671969 TX DQ/DQS : PASS
5998 19:22:38.674866 RX DATLAT : PASS
5999 19:22:38.678443 RX DQ/DQS(Engine): PASS
6000 19:22:38.678541 TX OE : NO K
6001 19:22:38.678640 All Pass.
6002 19:22:38.681485
6003 19:22:38.681580 CH 1, Rank 0
6004 19:22:38.685064 SW Impedance : PASS
6005 19:22:38.685167 DUTY Scan : NO K
6006 19:22:38.688117 ZQ Calibration : PASS
6007 19:22:38.691240 Jitter Meter : NO K
6008 19:22:38.691343 CBT Training : PASS
6009 19:22:38.694931 Write leveling : PASS
6010 19:22:38.695056 RX DQS gating : PASS
6011 19:22:38.698052 RX DQ/DQS(RDDQC) : PASS
6012 19:22:38.701162 TX DQ/DQS : PASS
6013 19:22:38.701261 RX DATLAT : PASS
6014 19:22:38.704789 RX DQ/DQS(Engine): PASS
6015 19:22:38.707788 TX OE : NO K
6016 19:22:38.707906 All Pass.
6017 19:22:38.707991
6018 19:22:38.708079 CH 1, Rank 1
6019 19:22:38.711417 SW Impedance : PASS
6020 19:22:38.714335 DUTY Scan : NO K
6021 19:22:38.714430 ZQ Calibration : PASS
6022 19:22:38.717605 Jitter Meter : NO K
6023 19:22:38.721042 CBT Training : PASS
6024 19:22:38.721137 Write leveling : PASS
6025 19:22:38.724391 RX DQS gating : PASS
6026 19:22:38.727699 RX DQ/DQS(RDDQC) : PASS
6027 19:22:38.727806 TX DQ/DQS : PASS
6028 19:22:38.731053 RX DATLAT : PASS
6029 19:22:38.734769 RX DQ/DQS(Engine): PASS
6030 19:22:38.734867 TX OE : NO K
6031 19:22:38.737742 All Pass.
6032 19:22:38.737836
6033 19:22:38.737924 DramC Write-DBI off
6034 19:22:38.741378 PER_BANK_REFRESH: Hybrid Mode
6035 19:22:38.741481 TX_TRACKING: ON
6036 19:22:38.750831 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6037 19:22:38.753970 [FAST_K] Save calibration result to emmc
6038 19:22:38.757222 dramc_set_vcore_voltage set vcore to 650000
6039 19:22:38.760709 Read voltage for 400, 6
6040 19:22:38.760808 Vio18 = 0
6041 19:22:38.763801 Vcore = 650000
6042 19:22:38.763903 Vdram = 0
6043 19:22:38.764008 Vddq = 0
6044 19:22:38.767414 Vmddr = 0
6045 19:22:38.770288 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6046 19:22:38.776832 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6047 19:22:38.776932 MEM_TYPE=3, freq_sel=20
6048 19:22:38.780683 sv_algorithm_assistance_LP4_800
6049 19:22:38.786947 ============ PULL DRAM RESETB DOWN ============
6050 19:22:38.790232 ========== PULL DRAM RESETB DOWN end =========
6051 19:22:38.793276 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6052 19:22:38.796973 ===================================
6053 19:22:38.800111 LPDDR4 DRAM CONFIGURATION
6054 19:22:38.803265 ===================================
6055 19:22:38.806509 EX_ROW_EN[0] = 0x0
6056 19:22:38.806632 EX_ROW_EN[1] = 0x0
6057 19:22:38.810034 LP4Y_EN = 0x0
6058 19:22:38.810195 WORK_FSP = 0x0
6059 19:22:38.813124 WL = 0x2
6060 19:22:38.813234 RL = 0x2
6061 19:22:38.816886 BL = 0x2
6062 19:22:38.817044 RPST = 0x0
6063 19:22:38.819721 RD_PRE = 0x0
6064 19:22:38.819842 WR_PRE = 0x1
6065 19:22:38.823192 WR_PST = 0x0
6066 19:22:38.823334 DBI_WR = 0x0
6067 19:22:38.826707 DBI_RD = 0x0
6068 19:22:38.826781 OTF = 0x1
6069 19:22:38.829661 ===================================
6070 19:22:38.833135 ===================================
6071 19:22:38.836099 ANA top config
6072 19:22:38.839746 ===================================
6073 19:22:38.842831 DLL_ASYNC_EN = 0
6074 19:22:38.842939 ALL_SLAVE_EN = 1
6075 19:22:38.846004 NEW_RANK_MODE = 1
6076 19:22:38.849654 DLL_IDLE_MODE = 1
6077 19:22:38.852830 LP45_APHY_COMB_EN = 1
6078 19:22:38.855969 TX_ODT_DIS = 1
6079 19:22:38.856049 NEW_8X_MODE = 1
6080 19:22:38.859628 ===================================
6081 19:22:38.862493 ===================================
6082 19:22:38.866172 data_rate = 800
6083 19:22:38.869271 CKR = 1
6084 19:22:38.872350 DQ_P2S_RATIO = 4
6085 19:22:38.876078 ===================================
6086 19:22:38.879021 CA_P2S_RATIO = 4
6087 19:22:38.882580 DQ_CA_OPEN = 0
6088 19:22:38.882714 DQ_SEMI_OPEN = 1
6089 19:22:38.885656 CA_SEMI_OPEN = 1
6090 19:22:38.888998 CA_FULL_RATE = 0
6091 19:22:38.892442 DQ_CKDIV4_EN = 0
6092 19:22:38.895614 CA_CKDIV4_EN = 1
6093 19:22:38.898835 CA_PREDIV_EN = 0
6094 19:22:38.898937 PH8_DLY = 0
6095 19:22:38.901992 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6096 19:22:38.905762 DQ_AAMCK_DIV = 0
6097 19:22:38.908782 CA_AAMCK_DIV = 0
6098 19:22:38.912488 CA_ADMCK_DIV = 4
6099 19:22:38.915229 DQ_TRACK_CA_EN = 0
6100 19:22:38.918793 CA_PICK = 800
6101 19:22:38.918883 CA_MCKIO = 400
6102 19:22:38.922094 MCKIO_SEMI = 400
6103 19:22:38.925079 PLL_FREQ = 3016
6104 19:22:38.928708 DQ_UI_PI_RATIO = 32
6105 19:22:38.932148 CA_UI_PI_RATIO = 32
6106 19:22:38.935113 ===================================
6107 19:22:38.938676 ===================================
6108 19:22:38.941526 memory_type:LPDDR4
6109 19:22:38.941609 GP_NUM : 10
6110 19:22:38.944760 SRAM_EN : 1
6111 19:22:38.948264 MD32_EN : 0
6112 19:22:38.951858 ===================================
6113 19:22:38.951963 [ANA_INIT] >>>>>>>>>>>>>>
6114 19:22:38.954960 <<<<<< [CONFIGURE PHASE]: ANA_TX
6115 19:22:38.958110 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6116 19:22:38.961328 ===================================
6117 19:22:38.964584 data_rate = 800,PCW = 0X7400
6118 19:22:38.968290 ===================================
6119 19:22:38.971389 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6120 19:22:38.978009 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6121 19:22:38.987486 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6122 19:22:38.994393 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6123 19:22:38.997688 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6124 19:22:39.000836 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6125 19:22:39.000934 [ANA_INIT] flow start
6126 19:22:39.004216 [ANA_INIT] PLL >>>>>>>>
6127 19:22:39.007278 [ANA_INIT] PLL <<<<<<<<
6128 19:22:39.007402 [ANA_INIT] MIDPI >>>>>>>>
6129 19:22:39.010972 [ANA_INIT] MIDPI <<<<<<<<
6130 19:22:39.013915 [ANA_INIT] DLL >>>>>>>>
6131 19:22:39.014002 [ANA_INIT] flow end
6132 19:22:39.020551 ============ LP4 DIFF to SE enter ============
6133 19:22:39.023612 ============ LP4 DIFF to SE exit ============
6134 19:22:39.027305 [ANA_INIT] <<<<<<<<<<<<<
6135 19:22:39.030231 [Flow] Enable top DCM control >>>>>
6136 19:22:39.033739 [Flow] Enable top DCM control <<<<<
6137 19:22:39.037142 Enable DLL master slave shuffle
6138 19:22:39.040591 ==============================================================
6139 19:22:39.043664 Gating Mode config
6140 19:22:39.047110 ==============================================================
6141 19:22:39.050088 Config description:
6142 19:22:39.060112 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6143 19:22:39.066789 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6144 19:22:39.069864 SELPH_MODE 0: By rank 1: By Phase
6145 19:22:39.076379 ==============================================================
6146 19:22:39.080138 GAT_TRACK_EN = 0
6147 19:22:39.083232 RX_GATING_MODE = 2
6148 19:22:39.086640 RX_GATING_TRACK_MODE = 2
6149 19:22:39.089553 SELPH_MODE = 1
6150 19:22:39.093131 PICG_EARLY_EN = 1
6151 19:22:39.096225 VALID_LAT_VALUE = 1
6152 19:22:39.100018 ==============================================================
6153 19:22:39.103460 Enter into Gating configuration >>>>
6154 19:22:39.106258 Exit from Gating configuration <<<<
6155 19:22:39.109680 Enter into DVFS_PRE_config >>>>>
6156 19:22:39.122960 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6157 19:22:39.123048 Exit from DVFS_PRE_config <<<<<
6158 19:22:39.126018 Enter into PICG configuration >>>>
6159 19:22:39.129156 Exit from PICG configuration <<<<
6160 19:22:39.132847 [RX_INPUT] configuration >>>>>
6161 19:22:39.135947 [RX_INPUT] configuration <<<<<
6162 19:22:39.142720 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6163 19:22:39.145980 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6164 19:22:39.152416 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6165 19:22:39.159071 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6166 19:22:39.165639 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6167 19:22:39.172620 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6168 19:22:39.175644 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6169 19:22:39.178750 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6170 19:22:39.181790 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6171 19:22:39.188533 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6172 19:22:39.191650 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6173 19:22:39.195232 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6174 19:22:39.198652 ===================================
6175 19:22:39.201438 LPDDR4 DRAM CONFIGURATION
6176 19:22:39.205221 ===================================
6177 19:22:39.208402 EX_ROW_EN[0] = 0x0
6178 19:22:39.208478 EX_ROW_EN[1] = 0x0
6179 19:22:39.211368 LP4Y_EN = 0x0
6180 19:22:39.211443 WORK_FSP = 0x0
6181 19:22:39.215000 WL = 0x2
6182 19:22:39.215075 RL = 0x2
6183 19:22:39.217939 BL = 0x2
6184 19:22:39.218015 RPST = 0x0
6185 19:22:39.222140 RD_PRE = 0x0
6186 19:22:39.222221 WR_PRE = 0x1
6187 19:22:39.224586 WR_PST = 0x0
6188 19:22:39.228445 DBI_WR = 0x0
6189 19:22:39.228552 DBI_RD = 0x0
6190 19:22:39.231691 OTF = 0x1
6191 19:22:39.235011 ===================================
6192 19:22:39.238009 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6193 19:22:39.241125 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6194 19:22:39.244413 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6195 19:22:39.248294 ===================================
6196 19:22:39.251464 LPDDR4 DRAM CONFIGURATION
6197 19:22:39.254249 ===================================
6198 19:22:39.257483 EX_ROW_EN[0] = 0x10
6199 19:22:39.257667 EX_ROW_EN[1] = 0x0
6200 19:22:39.261153 LP4Y_EN = 0x0
6201 19:22:39.261233 WORK_FSP = 0x0
6202 19:22:39.264167 WL = 0x2
6203 19:22:39.264248 RL = 0x2
6204 19:22:39.267732 BL = 0x2
6205 19:22:39.267835 RPST = 0x0
6206 19:22:39.271346 RD_PRE = 0x0
6207 19:22:39.271422 WR_PRE = 0x1
6208 19:22:39.274373 WR_PST = 0x0
6209 19:22:39.277603 DBI_WR = 0x0
6210 19:22:39.277702 DBI_RD = 0x0
6211 19:22:39.280635 OTF = 0x1
6212 19:22:39.284632 ===================================
6213 19:22:39.287293 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6214 19:22:39.292659 nWR fixed to 30
6215 19:22:39.296304 [ModeRegInit_LP4] CH0 RK0
6216 19:22:39.296381 [ModeRegInit_LP4] CH0 RK1
6217 19:22:39.299594 [ModeRegInit_LP4] CH1 RK0
6218 19:22:39.302459 [ModeRegInit_LP4] CH1 RK1
6219 19:22:39.302531 match AC timing 19
6220 19:22:39.309254 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6221 19:22:39.312396 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6222 19:22:39.315802 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6223 19:22:39.322149 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6224 19:22:39.325805 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6225 19:22:39.325886 ==
6226 19:22:39.329029 Dram Type= 6, Freq= 0, CH_0, rank 0
6227 19:22:39.332386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6228 19:22:39.332472 ==
6229 19:22:39.338490 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6230 19:22:39.345175 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6231 19:22:39.348533 [CA 0] Center 36 (8~64) winsize 57
6232 19:22:39.352187 [CA 1] Center 36 (8~64) winsize 57
6233 19:22:39.355118 [CA 2] Center 36 (8~64) winsize 57
6234 19:22:39.358483 [CA 3] Center 36 (8~64) winsize 57
6235 19:22:39.361861 [CA 4] Center 36 (8~64) winsize 57
6236 19:22:39.365090 [CA 5] Center 36 (8~64) winsize 57
6237 19:22:39.365190
6238 19:22:39.368472 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6239 19:22:39.368548
6240 19:22:39.371907 [CATrainingPosCal] consider 1 rank data
6241 19:22:39.374895 u2DelayCellTimex100 = 270/100 ps
6242 19:22:39.378327 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 19:22:39.381354 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 19:22:39.385004 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 19:22:39.388071 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 19:22:39.391062 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 19:22:39.394793 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 19:22:39.394891
6249 19:22:39.400970 CA PerBit enable=1, Macro0, CA PI delay=36
6250 19:22:39.401051
6251 19:22:39.404830 [CBTSetCACLKResult] CA Dly = 36
6252 19:22:39.404912 CS Dly: 1 (0~32)
6253 19:22:39.404978 ==
6254 19:22:39.407738 Dram Type= 6, Freq= 0, CH_0, rank 1
6255 19:22:39.411368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6256 19:22:39.411450 ==
6257 19:22:39.417555 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6258 19:22:39.424095 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6259 19:22:39.427291 [CA 0] Center 36 (8~64) winsize 57
6260 19:22:39.431172 [CA 1] Center 36 (8~64) winsize 57
6261 19:22:39.434326 [CA 2] Center 36 (8~64) winsize 57
6262 19:22:39.437317 [CA 3] Center 36 (8~64) winsize 57
6263 19:22:39.440748 [CA 4] Center 36 (8~64) winsize 57
6264 19:22:39.443780 [CA 5] Center 36 (8~64) winsize 57
6265 19:22:39.443880
6266 19:22:39.447352 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6267 19:22:39.447427
6268 19:22:39.450757 [CATrainingPosCal] consider 2 rank data
6269 19:22:39.453936 u2DelayCellTimex100 = 270/100 ps
6270 19:22:39.457521 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6271 19:22:39.460360 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6272 19:22:39.463790 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6273 19:22:39.467148 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6274 19:22:39.469980 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6275 19:22:39.473482 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6276 19:22:39.473564
6277 19:22:39.480204 CA PerBit enable=1, Macro0, CA PI delay=36
6278 19:22:39.480286
6279 19:22:39.483133 [CBTSetCACLKResult] CA Dly = 36
6280 19:22:39.483214 CS Dly: 1 (0~32)
6281 19:22:39.483304
6282 19:22:39.486730 ----->DramcWriteLeveling(PI) begin...
6283 19:22:39.486813 ==
6284 19:22:39.489883 Dram Type= 6, Freq= 0, CH_0, rank 0
6285 19:22:39.493255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6286 19:22:39.496245 ==
6287 19:22:39.496326 Write leveling (Byte 0): 40 => 8
6288 19:22:39.499914 Write leveling (Byte 1): 40 => 8
6289 19:22:39.503026 DramcWriteLeveling(PI) end<-----
6290 19:22:39.503107
6291 19:22:39.503172 ==
6292 19:22:39.506066 Dram Type= 6, Freq= 0, CH_0, rank 0
6293 19:22:39.512745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6294 19:22:39.512827 ==
6295 19:22:39.515816 [Gating] SW mode calibration
6296 19:22:39.522583 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6297 19:22:39.525671 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6298 19:22:39.532342 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6299 19:22:39.535860 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6300 19:22:39.539142 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6301 19:22:39.545335 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6302 19:22:39.548797 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6303 19:22:39.552274 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6304 19:22:39.558505 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6305 19:22:39.562062 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6306 19:22:39.565018 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6307 19:22:39.568657 Total UI for P1: 0, mck2ui 16
6308 19:22:39.572128 best dqsien dly found for B0: ( 0, 14, 24)
6309 19:22:39.575208 Total UI for P1: 0, mck2ui 16
6310 19:22:39.578490 best dqsien dly found for B1: ( 0, 14, 24)
6311 19:22:39.581836 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6312 19:22:39.585119 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6313 19:22:39.585199
6314 19:22:39.591624 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6315 19:22:39.595086 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6316 19:22:39.598606 [Gating] SW calibration Done
6317 19:22:39.598682 ==
6318 19:22:39.601682 Dram Type= 6, Freq= 0, CH_0, rank 0
6319 19:22:39.604708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6320 19:22:39.604783 ==
6321 19:22:39.604862 RX Vref Scan: 0
6322 19:22:39.604937
6323 19:22:39.608392 RX Vref 0 -> 0, step: 1
6324 19:22:39.608475
6325 19:22:39.611241 RX Delay -410 -> 252, step: 16
6326 19:22:39.615006 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6327 19:22:39.621340 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6328 19:22:39.624621 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6329 19:22:39.627626 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6330 19:22:39.631332 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6331 19:22:39.637699 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6332 19:22:39.641400 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6333 19:22:39.644441 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6334 19:22:39.647913 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6335 19:22:39.654430 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6336 19:22:39.657582 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6337 19:22:39.660826 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6338 19:22:39.664133 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6339 19:22:39.670815 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6340 19:22:39.673851 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6341 19:22:39.677536 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6342 19:22:39.677619 ==
6343 19:22:39.680491 Dram Type= 6, Freq= 0, CH_0, rank 0
6344 19:22:39.687388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6345 19:22:39.687526 ==
6346 19:22:39.687622 DQS Delay:
6347 19:22:39.690732 DQS0 = 35, DQS1 = 51
6348 19:22:39.690807 DQM Delay:
6349 19:22:39.690868 DQM0 = 5, DQM1 = 10
6350 19:22:39.694145 DQ Delay:
6351 19:22:39.697252 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6352 19:22:39.700506 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6353 19:22:39.700587 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6354 19:22:39.703840 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6355 19:22:39.703993
6356 19:22:39.707073
6357 19:22:39.707157 ==
6358 19:22:39.710177 Dram Type= 6, Freq= 0, CH_0, rank 0
6359 19:22:39.713717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6360 19:22:39.713822 ==
6361 19:22:39.713917
6362 19:22:39.714014
6363 19:22:39.716737 TX Vref Scan disable
6364 19:22:39.716810 == TX Byte 0 ==
6365 19:22:39.720406 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6366 19:22:39.727019 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6367 19:22:39.727126 == TX Byte 1 ==
6368 19:22:39.729944 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6369 19:22:39.736786 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6370 19:22:39.736884 ==
6371 19:22:39.739802 Dram Type= 6, Freq= 0, CH_0, rank 0
6372 19:22:39.743527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6373 19:22:39.743605 ==
6374 19:22:39.743671
6375 19:22:39.743729
6376 19:22:39.746552 TX Vref Scan disable
6377 19:22:39.746627 == TX Byte 0 ==
6378 19:22:39.753211 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6379 19:22:39.756164 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6380 19:22:39.756241 == TX Byte 1 ==
6381 19:22:39.763142 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6382 19:22:39.766017 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6383 19:22:39.766092
6384 19:22:39.766154 [DATLAT]
6385 19:22:39.769215 Freq=400, CH0 RK0
6386 19:22:39.769286
6387 19:22:39.769364 DATLAT Default: 0xf
6388 19:22:39.772849 0, 0xFFFF, sum = 0
6389 19:22:39.772928 1, 0xFFFF, sum = 0
6390 19:22:39.776143 2, 0xFFFF, sum = 0
6391 19:22:39.776224 3, 0xFFFF, sum = 0
6392 19:22:39.779323 4, 0xFFFF, sum = 0
6393 19:22:39.779402 5, 0xFFFF, sum = 0
6394 19:22:39.782565 6, 0xFFFF, sum = 0
6395 19:22:39.782684 7, 0xFFFF, sum = 0
6396 19:22:39.785736 8, 0xFFFF, sum = 0
6397 19:22:39.789377 9, 0xFFFF, sum = 0
6398 19:22:39.789453 10, 0xFFFF, sum = 0
6399 19:22:39.792487 11, 0xFFFF, sum = 0
6400 19:22:39.792571 12, 0xFFFF, sum = 0
6401 19:22:39.795980 13, 0x0, sum = 1
6402 19:22:39.796065 14, 0x0, sum = 2
6403 19:22:39.798986 15, 0x0, sum = 3
6404 19:22:39.799086 16, 0x0, sum = 4
6405 19:22:39.799167 best_step = 14
6406 19:22:39.802446
6407 19:22:39.802543 ==
6408 19:22:39.805998 Dram Type= 6, Freq= 0, CH_0, rank 0
6409 19:22:39.809161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6410 19:22:39.809234 ==
6411 19:22:39.809301 RX Vref Scan: 1
6412 19:22:39.809369
6413 19:22:39.812395 RX Vref 0 -> 0, step: 1
6414 19:22:39.812470
6415 19:22:39.815300 RX Delay -343 -> 252, step: 8
6416 19:22:39.815403
6417 19:22:39.818895 Set Vref, RX VrefLevel [Byte0]: 58
6418 19:22:39.821870 [Byte1]: 49
6419 19:22:39.826226
6420 19:22:39.826303 Final RX Vref Byte 0 = 58 to rank0
6421 19:22:39.829315 Final RX Vref Byte 1 = 49 to rank0
6422 19:22:39.832912 Final RX Vref Byte 0 = 58 to rank1
6423 19:22:39.835836 Final RX Vref Byte 1 = 49 to rank1==
6424 19:22:39.839061 Dram Type= 6, Freq= 0, CH_0, rank 0
6425 19:22:39.845706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6426 19:22:39.845783 ==
6427 19:22:39.845850 DQS Delay:
6428 19:22:39.849416 DQS0 = 44, DQS1 = 60
6429 19:22:39.849486 DQM Delay:
6430 19:22:39.849546 DQM0 = 11, DQM1 = 18
6431 19:22:39.852413 DQ Delay:
6432 19:22:39.856052 DQ0 =12, DQ1 =12, DQ2 =12, DQ3 =4
6433 19:22:39.859139 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6434 19:22:39.862215 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =12
6435 19:22:39.865701 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =28
6436 19:22:39.865775
6437 19:22:39.865847
6438 19:22:39.872376 [DQSOSCAuto] RK0, (LSB)MR18= 0x998d, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
6439 19:22:39.875426 CH0 RK0: MR19=C0C, MR18=998D
6440 19:22:39.882255 CH0_RK0: MR19=0xC0C, MR18=0x998D, DQSOSC=390, MR23=63, INC=388, DEC=258
6441 19:22:39.882338 ==
6442 19:22:39.885408 Dram Type= 6, Freq= 0, CH_0, rank 1
6443 19:22:39.888582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6444 19:22:39.888660 ==
6445 19:22:39.891847 [Gating] SW mode calibration
6446 19:22:39.898883 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6447 19:22:39.904862 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6448 19:22:39.908454 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6449 19:22:39.911485 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6450 19:22:39.918333 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6451 19:22:39.921233 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6452 19:22:39.924717 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6453 19:22:39.931304 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6454 19:22:39.934853 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6455 19:22:39.941023 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6456 19:22:39.944651 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6457 19:22:39.947681 Total UI for P1: 0, mck2ui 16
6458 19:22:39.951337 best dqsien dly found for B0: ( 0, 14, 24)
6459 19:22:39.954346 Total UI for P1: 0, mck2ui 16
6460 19:22:39.957519 best dqsien dly found for B1: ( 0, 14, 24)
6461 19:22:39.961144 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6462 19:22:39.964214 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6463 19:22:39.964293
6464 19:22:39.967731 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6465 19:22:39.970650 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6466 19:22:39.974301 [Gating] SW calibration Done
6467 19:22:39.974380 ==
6468 19:22:39.977433 Dram Type= 6, Freq= 0, CH_0, rank 1
6469 19:22:39.980919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6470 19:22:39.983732 ==
6471 19:22:39.983841 RX Vref Scan: 0
6472 19:22:39.983940
6473 19:22:39.987195 RX Vref 0 -> 0, step: 1
6474 19:22:39.987280
6475 19:22:39.990995 RX Delay -410 -> 252, step: 16
6476 19:22:39.993911 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6477 19:22:39.996905 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6478 19:22:40.000387 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6479 19:22:40.007091 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6480 19:22:40.010307 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6481 19:22:40.013749 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6482 19:22:40.017212 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6483 19:22:40.023324 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6484 19:22:40.026736 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6485 19:22:40.030279 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6486 19:22:40.036690 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6487 19:22:40.040315 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6488 19:22:40.043328 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6489 19:22:40.046440 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6490 19:22:40.053152 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6491 19:22:40.056221 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6492 19:22:40.056292 ==
6493 19:22:40.059794 Dram Type= 6, Freq= 0, CH_0, rank 1
6494 19:22:40.062912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6495 19:22:40.062984 ==
6496 19:22:40.066510 DQS Delay:
6497 19:22:40.066584 DQS0 = 35, DQS1 = 59
6498 19:22:40.069537 DQM Delay:
6499 19:22:40.069612 DQM0 = 7, DQM1 = 17
6500 19:22:40.069676 DQ Delay:
6501 19:22:40.073081 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6502 19:22:40.076536 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6503 19:22:40.079564 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =8
6504 19:22:40.083130 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6505 19:22:40.083204
6506 19:22:40.083264
6507 19:22:40.083326 ==
6508 19:22:40.086181 Dram Type= 6, Freq= 0, CH_0, rank 1
6509 19:22:40.089528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6510 19:22:40.092926 ==
6511 19:22:40.093002
6512 19:22:40.093064
6513 19:22:40.093128 TX Vref Scan disable
6514 19:22:40.096364 == TX Byte 0 ==
6515 19:22:40.099656 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6516 19:22:40.102753 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6517 19:22:40.105767 == TX Byte 1 ==
6518 19:22:40.109429 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6519 19:22:40.112404 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6520 19:22:40.116021 ==
6521 19:22:40.116105 Dram Type= 6, Freq= 0, CH_0, rank 1
6522 19:22:40.122489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6523 19:22:40.122576 ==
6524 19:22:40.122660
6525 19:22:40.122738
6526 19:22:40.125672 TX Vref Scan disable
6527 19:22:40.125773 == TX Byte 0 ==
6528 19:22:40.128844 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6529 19:22:40.135675 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6530 19:22:40.135808 == TX Byte 1 ==
6531 19:22:40.138745 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6532 19:22:40.145425 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6533 19:22:40.145508
6534 19:22:40.145591 [DATLAT]
6535 19:22:40.145677 Freq=400, CH0 RK1
6536 19:22:40.145784
6537 19:22:40.148550 DATLAT Default: 0xe
6538 19:22:40.151697 0, 0xFFFF, sum = 0
6539 19:22:40.151818 1, 0xFFFF, sum = 0
6540 19:22:40.155345 2, 0xFFFF, sum = 0
6541 19:22:40.155426 3, 0xFFFF, sum = 0
6542 19:22:40.158392 4, 0xFFFF, sum = 0
6543 19:22:40.158474 5, 0xFFFF, sum = 0
6544 19:22:40.162160 6, 0xFFFF, sum = 0
6545 19:22:40.162241 7, 0xFFFF, sum = 0
6546 19:22:40.165361 8, 0xFFFF, sum = 0
6547 19:22:40.165443 9, 0xFFFF, sum = 0
6548 19:22:40.168763 10, 0xFFFF, sum = 0
6549 19:22:40.168843 11, 0xFFFF, sum = 0
6550 19:22:40.171889 12, 0xFFFF, sum = 0
6551 19:22:40.171971 13, 0x0, sum = 1
6552 19:22:40.174830 14, 0x0, sum = 2
6553 19:22:40.174916 15, 0x0, sum = 3
6554 19:22:40.178324 16, 0x0, sum = 4
6555 19:22:40.178408 best_step = 14
6556 19:22:40.178492
6557 19:22:40.178570 ==
6558 19:22:40.181780 Dram Type= 6, Freq= 0, CH_0, rank 1
6559 19:22:40.188488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6560 19:22:40.188571 ==
6561 19:22:40.188654 RX Vref Scan: 0
6562 19:22:40.188733
6563 19:22:40.191514 RX Vref 0 -> 0, step: 1
6564 19:22:40.191596
6565 19:22:40.194910 RX Delay -359 -> 252, step: 8
6566 19:22:40.201192 iDelay=217, Bit 0, Center -36 (-271 ~ 200) 472
6567 19:22:40.204333 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6568 19:22:40.208136 iDelay=217, Bit 2, Center -36 (-271 ~ 200) 472
6569 19:22:40.214493 iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480
6570 19:22:40.217905 iDelay=217, Bit 4, Center -32 (-271 ~ 208) 480
6571 19:22:40.221148 iDelay=217, Bit 5, Center -40 (-279 ~ 200) 480
6572 19:22:40.224063 iDelay=217, Bit 6, Center -24 (-263 ~ 216) 480
6573 19:22:40.230808 iDelay=217, Bit 7, Center -32 (-271 ~ 208) 480
6574 19:22:40.234383 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6575 19:22:40.237322 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6576 19:22:40.241174 iDelay=217, Bit 10, Center -40 (-279 ~ 200) 480
6577 19:22:40.247206 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6578 19:22:40.250849 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6579 19:22:40.253729 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6580 19:22:40.257156 iDelay=217, Bit 14, Center -32 (-271 ~ 208) 480
6581 19:22:40.263744 iDelay=217, Bit 15, Center -40 (-279 ~ 200) 480
6582 19:22:40.263828 ==
6583 19:22:40.266731 Dram Type= 6, Freq= 0, CH_0, rank 1
6584 19:22:40.270095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6585 19:22:40.270214 ==
6586 19:22:40.273775 DQS Delay:
6587 19:22:40.273881 DQS0 = 40, DQS1 = 60
6588 19:22:40.273974 DQM Delay:
6589 19:22:40.276978 DQM0 = 6, DQM1 = 15
6590 19:22:40.277058 DQ Delay:
6591 19:22:40.280198 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =0
6592 19:22:40.283482 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =8
6593 19:22:40.286917 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =8
6594 19:22:40.289889 DQ12 =16, DQ13 =20, DQ14 =28, DQ15 =20
6595 19:22:40.289977
6596 19:22:40.290043
6597 19:22:40.296619 [DQSOSCAuto] RK1, (LSB)MR18= 0x847d, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
6598 19:22:40.300225 CH0 RK1: MR19=C0C, MR18=847D
6599 19:22:40.306262 CH0_RK1: MR19=0xC0C, MR18=0x847D, DQSOSC=393, MR23=63, INC=382, DEC=254
6600 19:22:40.309816 [RxdqsGatingPostProcess] freq 400
6601 19:22:40.316478 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6602 19:22:40.320054 best DQS0 dly(2T, 0.5T) = (0, 10)
6603 19:22:40.323129 best DQS1 dly(2T, 0.5T) = (0, 10)
6604 19:22:40.326175 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6605 19:22:40.329744 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6606 19:22:40.329814 best DQS0 dly(2T, 0.5T) = (0, 10)
6607 19:22:40.332864 best DQS1 dly(2T, 0.5T) = (0, 10)
6608 19:22:40.336463 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6609 19:22:40.339470 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6610 19:22:40.343175 Pre-setting of DQS Precalculation
6611 19:22:40.349314 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6612 19:22:40.349390 ==
6613 19:22:40.352941 Dram Type= 6, Freq= 0, CH_1, rank 0
6614 19:22:40.355871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6615 19:22:40.355977 ==
6616 19:22:40.362798 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6617 19:22:40.369302 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6618 19:22:40.372410 [CA 0] Center 36 (8~64) winsize 57
6619 19:22:40.375867 [CA 1] Center 36 (8~64) winsize 57
6620 19:22:40.378677 [CA 2] Center 36 (8~64) winsize 57
6621 19:22:40.378777 [CA 3] Center 36 (8~64) winsize 57
6622 19:22:40.382297 [CA 4] Center 36 (8~64) winsize 57
6623 19:22:40.385328 [CA 5] Center 36 (8~64) winsize 57
6624 19:22:40.385429
6625 19:22:40.392304 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6626 19:22:40.392410
6627 19:22:40.395354 [CATrainingPosCal] consider 1 rank data
6628 19:22:40.398726 u2DelayCellTimex100 = 270/100 ps
6629 19:22:40.402082 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 19:22:40.405515 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 19:22:40.408483 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 19:22:40.411760 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 19:22:40.415082 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 19:22:40.418552 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 19:22:40.418633
6636 19:22:40.421629 CA PerBit enable=1, Macro0, CA PI delay=36
6637 19:22:40.421710
6638 19:22:40.425335 [CBTSetCACLKResult] CA Dly = 36
6639 19:22:40.428457 CS Dly: 1 (0~32)
6640 19:22:40.428564 ==
6641 19:22:40.431471 Dram Type= 6, Freq= 0, CH_1, rank 1
6642 19:22:40.435161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6643 19:22:40.435243 ==
6644 19:22:40.441828 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6645 19:22:40.448014 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6646 19:22:40.451146 [CA 0] Center 36 (8~64) winsize 57
6647 19:22:40.454985 [CA 1] Center 36 (8~64) winsize 57
6648 19:22:40.455067 [CA 2] Center 36 (8~64) winsize 57
6649 19:22:40.458337 [CA 3] Center 36 (8~64) winsize 57
6650 19:22:40.460908 [CA 4] Center 36 (8~64) winsize 57
6651 19:22:40.464341 [CA 5] Center 36 (8~64) winsize 57
6652 19:22:40.464439
6653 19:22:40.467560 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6654 19:22:40.471063
6655 19:22:40.474685 [CATrainingPosCal] consider 2 rank data
6656 19:22:40.474767 u2DelayCellTimex100 = 270/100 ps
6657 19:22:40.480848 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6658 19:22:40.484457 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6659 19:22:40.487484 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6660 19:22:40.490952 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6661 19:22:40.493837 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6662 19:22:40.497115 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6663 19:22:40.497196
6664 19:22:40.500467 CA PerBit enable=1, Macro0, CA PI delay=36
6665 19:22:40.500548
6666 19:22:40.504142 [CBTSetCACLKResult] CA Dly = 36
6667 19:22:40.507033 CS Dly: 1 (0~32)
6668 19:22:40.507115
6669 19:22:40.510486 ----->DramcWriteLeveling(PI) begin...
6670 19:22:40.510568 ==
6671 19:22:40.514266 Dram Type= 6, Freq= 0, CH_1, rank 0
6672 19:22:40.516885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6673 19:22:40.516967 ==
6674 19:22:40.520310 Write leveling (Byte 0): 40 => 8
6675 19:22:40.523388 Write leveling (Byte 1): 40 => 8
6676 19:22:40.526768 DramcWriteLeveling(PI) end<-----
6677 19:22:40.526894
6678 19:22:40.526959 ==
6679 19:22:40.530195 Dram Type= 6, Freq= 0, CH_1, rank 0
6680 19:22:40.533438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6681 19:22:40.533520 ==
6682 19:22:40.537007 [Gating] SW mode calibration
6683 19:22:40.543066 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6684 19:22:40.549845 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6685 19:22:40.552930 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6686 19:22:40.559708 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6687 19:22:40.563248 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6688 19:22:40.566301 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6689 19:22:40.573354 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6690 19:22:40.576159 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6691 19:22:40.579294 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6692 19:22:40.586271 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6693 19:22:40.589393 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6694 19:22:40.592480 Total UI for P1: 0, mck2ui 16
6695 19:22:40.596172 best dqsien dly found for B0: ( 0, 14, 24)
6696 19:22:40.599537 Total UI for P1: 0, mck2ui 16
6697 19:22:40.602759 best dqsien dly found for B1: ( 0, 14, 24)
6698 19:22:40.605855 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6699 19:22:40.609119 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6700 19:22:40.609201
6701 19:22:40.612434 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6702 19:22:40.615634 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6703 19:22:40.619168 [Gating] SW calibration Done
6704 19:22:40.619250 ==
6705 19:22:40.622160 Dram Type= 6, Freq= 0, CH_1, rank 0
6706 19:22:40.628963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6707 19:22:40.629048 ==
6708 19:22:40.629114 RX Vref Scan: 0
6709 19:22:40.629175
6710 19:22:40.631813 RX Vref 0 -> 0, step: 1
6711 19:22:40.631904
6712 19:22:40.635259 RX Delay -410 -> 252, step: 16
6713 19:22:40.638548 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6714 19:22:40.641670 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6715 19:22:40.648873 iDelay=230, Bit 2, Center -43 (-282 ~ 197) 480
6716 19:22:40.652049 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6717 19:22:40.654982 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6718 19:22:40.658705 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6719 19:22:40.665239 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6720 19:22:40.668163 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6721 19:22:40.671814 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6722 19:22:40.674887 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6723 19:22:40.681586 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6724 19:22:40.685013 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6725 19:22:40.687880 iDelay=230, Bit 12, Center -19 (-266 ~ 229) 496
6726 19:22:40.691396 iDelay=230, Bit 13, Center -19 (-266 ~ 229) 496
6727 19:22:40.697830 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6728 19:22:40.701482 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6729 19:22:40.701581 ==
6730 19:22:40.704487 Dram Type= 6, Freq= 0, CH_1, rank 0
6731 19:22:40.707573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6732 19:22:40.711221 ==
6733 19:22:40.711303 DQS Delay:
6734 19:22:40.711368 DQS0 = 43, DQS1 = 51
6735 19:22:40.714179 DQM Delay:
6736 19:22:40.714261 DQM0 = 13, DQM1 = 15
6737 19:22:40.717543 DQ Delay:
6738 19:22:40.717624 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6739 19:22:40.720728 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6740 19:22:40.724155 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6741 19:22:40.727665 DQ12 =32, DQ13 =32, DQ14 =16, DQ15 =16
6742 19:22:40.727748
6743 19:22:40.727812
6744 19:22:40.727873 ==
6745 19:22:40.730612 Dram Type= 6, Freq= 0, CH_1, rank 0
6746 19:22:40.737220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6747 19:22:40.737303 ==
6748 19:22:40.737368
6749 19:22:40.737428
6750 19:22:40.740888 TX Vref Scan disable
6751 19:22:40.740969 == TX Byte 0 ==
6752 19:22:40.743854 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6753 19:22:40.750522 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6754 19:22:40.750605 == TX Byte 1 ==
6755 19:22:40.753913 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6756 19:22:40.760265 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6757 19:22:40.760348 ==
6758 19:22:40.763812 Dram Type= 6, Freq= 0, CH_1, rank 0
6759 19:22:40.766871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6760 19:22:40.766953 ==
6761 19:22:40.767017
6762 19:22:40.767077
6763 19:22:40.770391 TX Vref Scan disable
6764 19:22:40.770473 == TX Byte 0 ==
6765 19:22:40.773396 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6766 19:22:40.780154 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6767 19:22:40.780239 == TX Byte 1 ==
6768 19:22:40.783237 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6769 19:22:40.790051 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6770 19:22:40.790135
6771 19:22:40.790200 [DATLAT]
6772 19:22:40.793107 Freq=400, CH1 RK0
6773 19:22:40.793189
6774 19:22:40.793255 DATLAT Default: 0xf
6775 19:22:40.796521 0, 0xFFFF, sum = 0
6776 19:22:40.796605 1, 0xFFFF, sum = 0
6777 19:22:40.800017 2, 0xFFFF, sum = 0
6778 19:22:40.800092 3, 0xFFFF, sum = 0
6779 19:22:40.802992 4, 0xFFFF, sum = 0
6780 19:22:40.803066 5, 0xFFFF, sum = 0
6781 19:22:40.806603 6, 0xFFFF, sum = 0
6782 19:22:40.806675 7, 0xFFFF, sum = 0
6783 19:22:40.809639 8, 0xFFFF, sum = 0
6784 19:22:40.809711 9, 0xFFFF, sum = 0
6785 19:22:40.812627 10, 0xFFFF, sum = 0
6786 19:22:40.812701 11, 0xFFFF, sum = 0
6787 19:22:40.816231 12, 0xFFFF, sum = 0
6788 19:22:40.816328 13, 0x0, sum = 1
6789 19:22:40.819301 14, 0x0, sum = 2
6790 19:22:40.819373 15, 0x0, sum = 3
6791 19:22:40.822874 16, 0x0, sum = 4
6792 19:22:40.822975 best_step = 14
6793 19:22:40.823063
6794 19:22:40.823148 ==
6795 19:22:40.825829 Dram Type= 6, Freq= 0, CH_1, rank 0
6796 19:22:40.832580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6797 19:22:40.832658 ==
6798 19:22:40.832722 RX Vref Scan: 1
6799 19:22:40.832782
6800 19:22:40.835720 RX Vref 0 -> 0, step: 1
6801 19:22:40.835789
6802 19:22:40.839540 RX Delay -343 -> 252, step: 8
6803 19:22:40.839616
6804 19:22:40.842741 Set Vref, RX VrefLevel [Byte0]: 51
6805 19:22:40.845468 [Byte1]: 51
6806 19:22:40.849330
6807 19:22:40.849401 Final RX Vref Byte 0 = 51 to rank0
6808 19:22:40.852256 Final RX Vref Byte 1 = 51 to rank0
6809 19:22:40.855857 Final RX Vref Byte 0 = 51 to rank1
6810 19:22:40.859030 Final RX Vref Byte 1 = 51 to rank1==
6811 19:22:40.862309 Dram Type= 6, Freq= 0, CH_1, rank 0
6812 19:22:40.868984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6813 19:22:40.869081 ==
6814 19:22:40.869160 DQS Delay:
6815 19:22:40.872297 DQS0 = 44, DQS1 = 52
6816 19:22:40.872378 DQM Delay:
6817 19:22:40.875393 DQM0 = 10, DQM1 = 11
6818 19:22:40.875473 DQ Delay:
6819 19:22:40.879058 DQ0 =20, DQ1 =4, DQ2 =0, DQ3 =8
6820 19:22:40.882017 DQ4 =4, DQ5 =20, DQ6 =24, DQ7 =4
6821 19:22:40.882092 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6822 19:22:40.885382 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =16
6823 19:22:40.888762
6824 19:22:40.888843
6825 19:22:40.895294 [DQSOSCAuto] RK0, (LSB)MR18= 0x6f96, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 395 ps
6826 19:22:40.899100 CH1 RK0: MR19=C0C, MR18=6F96
6827 19:22:40.905181 CH1_RK0: MR19=0xC0C, MR18=0x6F96, DQSOSC=391, MR23=63, INC=386, DEC=257
6828 19:22:40.905258 ==
6829 19:22:40.908655 Dram Type= 6, Freq= 0, CH_1, rank 1
6830 19:22:40.911720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6831 19:22:40.911792 ==
6832 19:22:40.914817 [Gating] SW mode calibration
6833 19:22:40.921561 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6834 19:22:40.928363 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6835 19:22:40.931395 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6836 19:22:40.935061 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6837 19:22:40.941538 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6838 19:22:40.944807 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6839 19:22:40.948136 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6840 19:22:40.954708 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6841 19:22:40.957734 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6842 19:22:40.961255 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6843 19:22:40.967632 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6844 19:22:40.971319 Total UI for P1: 0, mck2ui 16
6845 19:22:40.974362 best dqsien dly found for B0: ( 0, 14, 24)
6846 19:22:40.974443 Total UI for P1: 0, mck2ui 16
6847 19:22:40.980938 best dqsien dly found for B1: ( 0, 14, 24)
6848 19:22:40.984297 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6849 19:22:40.987489 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6850 19:22:40.987571
6851 19:22:40.990879 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6852 19:22:40.994408 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6853 19:22:40.997476 [Gating] SW calibration Done
6854 19:22:40.997557 ==
6855 19:22:41.001011 Dram Type= 6, Freq= 0, CH_1, rank 1
6856 19:22:41.004310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6857 19:22:41.004424 ==
6858 19:22:41.007361 RX Vref Scan: 0
6859 19:22:41.007441
6860 19:22:41.010327 RX Vref 0 -> 0, step: 1
6861 19:22:41.010408
6862 19:22:41.010474 RX Delay -410 -> 252, step: 16
6863 19:22:41.017513 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6864 19:22:41.020665 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6865 19:22:41.023745 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6866 19:22:41.030493 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6867 19:22:41.033775 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6868 19:22:41.037091 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6869 19:22:41.040129 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6870 19:22:41.046851 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6871 19:22:41.049997 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6872 19:22:41.053579 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6873 19:22:41.056623 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6874 19:22:41.063391 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6875 19:22:41.066699 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6876 19:22:41.069742 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6877 19:22:41.073137 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6878 19:22:41.079401 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6879 19:22:41.079555 ==
6880 19:22:41.083119 Dram Type= 6, Freq= 0, CH_1, rank 1
6881 19:22:41.086102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6882 19:22:41.086184 ==
6883 19:22:41.089648 DQS Delay:
6884 19:22:41.089729 DQS0 = 43, DQS1 = 51
6885 19:22:41.089793 DQM Delay:
6886 19:22:41.092916 DQM0 = 9, DQM1 = 14
6887 19:22:41.092988 DQ Delay:
6888 19:22:41.096328 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6889 19:22:41.099394 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6890 19:22:41.102878 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6891 19:22:41.105754 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6892 19:22:41.105829
6893 19:22:41.105890
6894 19:22:41.105947 ==
6895 19:22:41.109393 Dram Type= 6, Freq= 0, CH_1, rank 1
6896 19:22:41.112571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6897 19:22:41.115900 ==
6898 19:22:41.116017
6899 19:22:41.116109
6900 19:22:41.116197 TX Vref Scan disable
6901 19:22:41.119309 == TX Byte 0 ==
6902 19:22:41.122658 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6903 19:22:41.125760 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6904 19:22:41.129168 == TX Byte 1 ==
6905 19:22:41.132258 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6906 19:22:41.135742 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6907 19:22:41.135868 ==
6908 19:22:41.138809 Dram Type= 6, Freq= 0, CH_1, rank 1
6909 19:22:41.145446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6910 19:22:41.145529 ==
6911 19:22:41.145594
6912 19:22:41.145688
6913 19:22:41.145746 TX Vref Scan disable
6914 19:22:41.148536 == TX Byte 0 ==
6915 19:22:41.152077 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6916 19:22:41.158271 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6917 19:22:41.158354 == TX Byte 1 ==
6918 19:22:41.161859 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6919 19:22:41.168160 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6920 19:22:41.168242
6921 19:22:41.168307 [DATLAT]
6922 19:22:41.168367 Freq=400, CH1 RK1
6923 19:22:41.168426
6924 19:22:41.171762 DATLAT Default: 0xe
6925 19:22:41.174608 0, 0xFFFF, sum = 0
6926 19:22:41.174691 1, 0xFFFF, sum = 0
6927 19:22:41.178031 2, 0xFFFF, sum = 0
6928 19:22:41.178113 3, 0xFFFF, sum = 0
6929 19:22:41.181233 4, 0xFFFF, sum = 0
6930 19:22:41.181316 5, 0xFFFF, sum = 0
6931 19:22:41.184753 6, 0xFFFF, sum = 0
6932 19:22:41.184836 7, 0xFFFF, sum = 0
6933 19:22:41.187956 8, 0xFFFF, sum = 0
6934 19:22:41.188039 9, 0xFFFF, sum = 0
6935 19:22:41.191122 10, 0xFFFF, sum = 0
6936 19:22:41.191204 11, 0xFFFF, sum = 0
6937 19:22:41.194634 12, 0xFFFF, sum = 0
6938 19:22:41.194717 13, 0x0, sum = 1
6939 19:22:41.198236 14, 0x0, sum = 2
6940 19:22:41.198318 15, 0x0, sum = 3
6941 19:22:41.201094 16, 0x0, sum = 4
6942 19:22:41.201176 best_step = 14
6943 19:22:41.201241
6944 19:22:41.201301 ==
6945 19:22:41.204664 Dram Type= 6, Freq= 0, CH_1, rank 1
6946 19:22:41.211222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6947 19:22:41.211304 ==
6948 19:22:41.211369 RX Vref Scan: 0
6949 19:22:41.211430
6950 19:22:41.214314 RX Vref 0 -> 0, step: 1
6951 19:22:41.214396
6952 19:22:41.217741 RX Delay -343 -> 252, step: 8
6953 19:22:41.224331 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6954 19:22:41.227409 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6955 19:22:41.230858 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6956 19:22:41.234243 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6957 19:22:41.240418 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6958 19:22:41.243701 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6959 19:22:41.247294 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6960 19:22:41.250452 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6961 19:22:41.257203 iDelay=217, Bit 8, Center -56 (-295 ~ 184) 480
6962 19:22:41.260157 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6963 19:22:41.263681 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6964 19:22:41.270460 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6965 19:22:41.273541 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6966 19:22:41.276582 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6967 19:22:41.280347 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6968 19:22:41.286365 iDelay=217, Bit 15, Center -32 (-279 ~ 216) 496
6969 19:22:41.286447 ==
6970 19:22:41.289821 Dram Type= 6, Freq= 0, CH_1, rank 1
6971 19:22:41.293157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6972 19:22:41.293238 ==
6973 19:22:41.293304 DQS Delay:
6974 19:22:41.296864 DQS0 = 48, DQS1 = 56
6975 19:22:41.296945 DQM Delay:
6976 19:22:41.299865 DQM0 = 11, DQM1 = 14
6977 19:22:41.299988 DQ Delay:
6978 19:22:41.303107 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =12
6979 19:22:41.306139 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
6980 19:22:41.309665 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6981 19:22:41.312910 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
6982 19:22:41.312992
6983 19:22:41.313057
6984 19:22:41.322692 [DQSOSCAuto] RK1, (LSB)MR18= 0x77ad, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 394 ps
6985 19:22:41.322775 CH1 RK1: MR19=C0C, MR18=77AD
6986 19:22:41.329463 CH1_RK1: MR19=0xC0C, MR18=0x77AD, DQSOSC=388, MR23=63, INC=392, DEC=261
6987 19:22:41.332435 [RxdqsGatingPostProcess] freq 400
6988 19:22:41.339020 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6989 19:22:41.342579 best DQS0 dly(2T, 0.5T) = (0, 10)
6990 19:22:41.345901 best DQS1 dly(2T, 0.5T) = (0, 10)
6991 19:22:41.348921 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6992 19:22:41.352294 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6993 19:22:41.355589 best DQS0 dly(2T, 0.5T) = (0, 10)
6994 19:22:41.359199 best DQS1 dly(2T, 0.5T) = (0, 10)
6995 19:22:41.359280 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6996 19:22:41.362569 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6997 19:22:41.365637 Pre-setting of DQS Precalculation
6998 19:22:41.372379 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6999 19:22:41.379087 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7000 19:22:41.385119 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7001 19:22:41.385201
7002 19:22:41.385266
7003 19:22:41.388900 [Calibration Summary] 800 Mbps
7004 19:22:41.391819 CH 0, Rank 0
7005 19:22:41.391950 SW Impedance : PASS
7006 19:22:41.395042 DUTY Scan : NO K
7007 19:22:41.398433 ZQ Calibration : PASS
7008 19:22:41.398515 Jitter Meter : NO K
7009 19:22:41.402088 CBT Training : PASS
7010 19:22:41.405159 Write leveling : PASS
7011 19:22:41.405240 RX DQS gating : PASS
7012 19:22:41.408184 RX DQ/DQS(RDDQC) : PASS
7013 19:22:41.408292 TX DQ/DQS : PASS
7014 19:22:41.411598 RX DATLAT : PASS
7015 19:22:41.415104 RX DQ/DQS(Engine): PASS
7016 19:22:41.415193 TX OE : NO K
7017 19:22:41.418465 All Pass.
7018 19:22:41.418547
7019 19:22:41.418612 CH 0, Rank 1
7020 19:22:41.421671 SW Impedance : PASS
7021 19:22:41.421767 DUTY Scan : NO K
7022 19:22:41.425312 ZQ Calibration : PASS
7023 19:22:41.428441 Jitter Meter : NO K
7024 19:22:41.428523 CBT Training : PASS
7025 19:22:41.431543 Write leveling : NO K
7026 19:22:41.435074 RX DQS gating : PASS
7027 19:22:41.435161 RX DQ/DQS(RDDQC) : PASS
7028 19:22:41.438614 TX DQ/DQS : PASS
7029 19:22:41.441775 RX DATLAT : PASS
7030 19:22:41.441857 RX DQ/DQS(Engine): PASS
7031 19:22:41.444834 TX OE : NO K
7032 19:22:41.444916 All Pass.
7033 19:22:41.444981
7034 19:22:41.448483 CH 1, Rank 0
7035 19:22:41.448563 SW Impedance : PASS
7036 19:22:41.451463 DUTY Scan : NO K
7037 19:22:41.455218 ZQ Calibration : PASS
7038 19:22:41.455299 Jitter Meter : NO K
7039 19:22:41.458131 CBT Training : PASS
7040 19:22:41.461640 Write leveling : PASS
7041 19:22:41.461721 RX DQS gating : PASS
7042 19:22:41.464417 RX DQ/DQS(RDDQC) : PASS
7043 19:22:41.467854 TX DQ/DQS : PASS
7044 19:22:41.467959 RX DATLAT : PASS
7045 19:22:41.471204 RX DQ/DQS(Engine): PASS
7046 19:22:41.474639 TX OE : NO K
7047 19:22:41.474720 All Pass.
7048 19:22:41.474785
7049 19:22:41.474846 CH 1, Rank 1
7050 19:22:41.477768 SW Impedance : PASS
7051 19:22:41.480834 DUTY Scan : NO K
7052 19:22:41.480915 ZQ Calibration : PASS
7053 19:22:41.484667 Jitter Meter : NO K
7054 19:22:41.484749 CBT Training : PASS
7055 19:22:41.487673 Write leveling : NO K
7056 19:22:41.490712 RX DQS gating : PASS
7057 19:22:41.490793 RX DQ/DQS(RDDQC) : PASS
7058 19:22:41.494221 TX DQ/DQS : PASS
7059 19:22:41.497238 RX DATLAT : PASS
7060 19:22:41.497319 RX DQ/DQS(Engine): PASS
7061 19:22:41.500734 TX OE : NO K
7062 19:22:41.500815 All Pass.
7063 19:22:41.500880
7064 19:22:41.504093 DramC Write-DBI off
7065 19:22:41.507083 PER_BANK_REFRESH: Hybrid Mode
7066 19:22:41.507165 TX_TRACKING: ON
7067 19:22:41.517011 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7068 19:22:41.520492 [FAST_K] Save calibration result to emmc
7069 19:22:41.523691 dramc_set_vcore_voltage set vcore to 725000
7070 19:22:41.527187 Read voltage for 1600, 0
7071 19:22:41.527268 Vio18 = 0
7072 19:22:41.530150 Vcore = 725000
7073 19:22:41.530230 Vdram = 0
7074 19:22:41.530295 Vddq = 0
7075 19:22:41.530355 Vmddr = 0
7076 19:22:41.537192 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7077 19:22:41.543374 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7078 19:22:41.543452 MEM_TYPE=3, freq_sel=13
7079 19:22:41.547055 sv_algorithm_assistance_LP4_3733
7080 19:22:41.550237 ============ PULL DRAM RESETB DOWN ============
7081 19:22:41.556993 ========== PULL DRAM RESETB DOWN end =========
7082 19:22:41.560067 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7083 19:22:41.563117 ===================================
7084 19:22:41.566702 LPDDR4 DRAM CONFIGURATION
7085 19:22:41.569857 ===================================
7086 19:22:41.569930 EX_ROW_EN[0] = 0x0
7087 19:22:41.573365 EX_ROW_EN[1] = 0x0
7088 19:22:41.576270 LP4Y_EN = 0x0
7089 19:22:41.576343 WORK_FSP = 0x1
7090 19:22:41.579741 WL = 0x5
7091 19:22:41.579841 RL = 0x5
7092 19:22:41.583205 BL = 0x2
7093 19:22:41.583277 RPST = 0x0
7094 19:22:41.586269 RD_PRE = 0x0
7095 19:22:41.586341 WR_PRE = 0x1
7096 19:22:41.589996 WR_PST = 0x1
7097 19:22:41.590103 DBI_WR = 0x0
7098 19:22:41.593074 DBI_RD = 0x0
7099 19:22:41.593153 OTF = 0x1
7100 19:22:41.596110 ===================================
7101 19:22:41.599727 ===================================
7102 19:22:41.602901 ANA top config
7103 19:22:41.606288 ===================================
7104 19:22:41.606369 DLL_ASYNC_EN = 0
7105 19:22:41.609602 ALL_SLAVE_EN = 0
7106 19:22:41.612790 NEW_RANK_MODE = 1
7107 19:22:41.615781 DLL_IDLE_MODE = 1
7108 19:22:41.619444 LP45_APHY_COMB_EN = 1
7109 19:22:41.619520 TX_ODT_DIS = 0
7110 19:22:41.622335 NEW_8X_MODE = 1
7111 19:22:41.625918 ===================================
7112 19:22:41.629148 ===================================
7113 19:22:41.632647 data_rate = 3200
7114 19:22:41.635518 CKR = 1
7115 19:22:41.639044 DQ_P2S_RATIO = 8
7116 19:22:41.642168 ===================================
7117 19:22:41.645814 CA_P2S_RATIO = 8
7118 19:22:41.645885 DQ_CA_OPEN = 0
7119 19:22:41.648755 DQ_SEMI_OPEN = 0
7120 19:22:41.652110 CA_SEMI_OPEN = 0
7121 19:22:41.655670 CA_FULL_RATE = 0
7122 19:22:41.658935 DQ_CKDIV4_EN = 0
7123 19:22:41.661935 CA_CKDIV4_EN = 0
7124 19:22:41.662016 CA_PREDIV_EN = 0
7125 19:22:41.665697 PH8_DLY = 12
7126 19:22:41.668483 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7127 19:22:41.672128 DQ_AAMCK_DIV = 4
7128 19:22:41.675194 CA_AAMCK_DIV = 4
7129 19:22:41.678161 CA_ADMCK_DIV = 4
7130 19:22:41.681540 DQ_TRACK_CA_EN = 0
7131 19:22:41.681613 CA_PICK = 1600
7132 19:22:41.685076 CA_MCKIO = 1600
7133 19:22:41.688465 MCKIO_SEMI = 0
7134 19:22:41.691475 PLL_FREQ = 3068
7135 19:22:41.695053 DQ_UI_PI_RATIO = 32
7136 19:22:41.698210 CA_UI_PI_RATIO = 0
7137 19:22:41.701311 ===================================
7138 19:22:41.704859 ===================================
7139 19:22:41.707783 memory_type:LPDDR4
7140 19:22:41.707895 GP_NUM : 10
7141 19:22:41.711510 SRAM_EN : 1
7142 19:22:41.711591 MD32_EN : 0
7143 19:22:41.714517 ===================================
7144 19:22:41.717960 [ANA_INIT] >>>>>>>>>>>>>>
7145 19:22:41.721365 <<<<<< [CONFIGURE PHASE]: ANA_TX
7146 19:22:41.724251 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7147 19:22:41.727648 ===================================
7148 19:22:41.730743 data_rate = 3200,PCW = 0X7600
7149 19:22:41.734448 ===================================
7150 19:22:41.737683 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7151 19:22:41.744034 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7152 19:22:41.747692 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7153 19:22:41.753807 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7154 19:22:41.757359 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7155 19:22:41.760487 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7156 19:22:41.760570 [ANA_INIT] flow start
7157 19:22:41.764177 [ANA_INIT] PLL >>>>>>>>
7158 19:22:41.767143 [ANA_INIT] PLL <<<<<<<<
7159 19:22:41.770427 [ANA_INIT] MIDPI >>>>>>>>
7160 19:22:41.770511 [ANA_INIT] MIDPI <<<<<<<<
7161 19:22:41.773567 [ANA_INIT] DLL >>>>>>>>
7162 19:22:41.777177 [ANA_INIT] DLL <<<<<<<<
7163 19:22:41.777258 [ANA_INIT] flow end
7164 19:22:41.780526 ============ LP4 DIFF to SE enter ============
7165 19:22:41.786971 ============ LP4 DIFF to SE exit ============
7166 19:22:41.787052 [ANA_INIT] <<<<<<<<<<<<<
7167 19:22:41.790300 [Flow] Enable top DCM control >>>>>
7168 19:22:41.793514 [Flow] Enable top DCM control <<<<<
7169 19:22:41.797090 Enable DLL master slave shuffle
7170 19:22:41.803242 ==============================================================
7171 19:22:41.806718 Gating Mode config
7172 19:22:41.809811 ==============================================================
7173 19:22:41.813462 Config description:
7174 19:22:41.823091 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7175 19:22:41.829841 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7176 19:22:41.833101 SELPH_MODE 0: By rank 1: By Phase
7177 19:22:41.839824 ==============================================================
7178 19:22:41.842801 GAT_TRACK_EN = 1
7179 19:22:41.846339 RX_GATING_MODE = 2
7180 19:22:41.849202 RX_GATING_TRACK_MODE = 2
7181 19:22:41.852631 SELPH_MODE = 1
7182 19:22:41.852714 PICG_EARLY_EN = 1
7183 19:22:41.856249 VALID_LAT_VALUE = 1
7184 19:22:41.862525 ==============================================================
7185 19:22:41.865614 Enter into Gating configuration >>>>
7186 19:22:41.869154 Exit from Gating configuration <<<<
7187 19:22:41.872174 Enter into DVFS_PRE_config >>>>>
7188 19:22:41.882055 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7189 19:22:41.885662 Exit from DVFS_PRE_config <<<<<
7190 19:22:41.888793 Enter into PICG configuration >>>>
7191 19:22:41.892241 Exit from PICG configuration <<<<
7192 19:22:41.895510 [RX_INPUT] configuration >>>>>
7193 19:22:41.898830 [RX_INPUT] configuration <<<<<
7194 19:22:41.902102 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7195 19:22:41.908720 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7196 19:22:41.915200 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7197 19:22:41.921981 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7198 19:22:41.928164 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7199 19:22:41.934698 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7200 19:22:41.938047 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7201 19:22:41.941372 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7202 19:22:41.944572 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7203 19:22:41.951252 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7204 19:22:41.954633 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7205 19:22:41.958085 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7206 19:22:41.961123 ===================================
7207 19:22:41.964617 LPDDR4 DRAM CONFIGURATION
7208 19:22:41.967573 ===================================
7209 19:22:41.971189 EX_ROW_EN[0] = 0x0
7210 19:22:41.971271 EX_ROW_EN[1] = 0x0
7211 19:22:41.974187 LP4Y_EN = 0x0
7212 19:22:41.974282 WORK_FSP = 0x1
7213 19:22:41.977750 WL = 0x5
7214 19:22:41.977846 RL = 0x5
7215 19:22:41.980841 BL = 0x2
7216 19:22:41.980935 RPST = 0x0
7217 19:22:41.984487 RD_PRE = 0x0
7218 19:22:41.984569 WR_PRE = 0x1
7219 19:22:41.987705 WR_PST = 0x1
7220 19:22:41.987788 DBI_WR = 0x0
7221 19:22:41.990764 DBI_RD = 0x0
7222 19:22:41.990846 OTF = 0x1
7223 19:22:41.994385 ===================================
7224 19:22:42.000918 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7225 19:22:42.003893 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7226 19:22:42.007375 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7227 19:22:42.010945 ===================================
7228 19:22:42.014440 LPDDR4 DRAM CONFIGURATION
7229 19:22:42.017173 ===================================
7230 19:22:42.020710 EX_ROW_EN[0] = 0x10
7231 19:22:42.020791 EX_ROW_EN[1] = 0x0
7232 19:22:42.024038 LP4Y_EN = 0x0
7233 19:22:42.024119 WORK_FSP = 0x1
7234 19:22:42.027143 WL = 0x5
7235 19:22:42.027224 RL = 0x5
7236 19:22:42.030899 BL = 0x2
7237 19:22:42.031007 RPST = 0x0
7238 19:22:42.033756 RD_PRE = 0x0
7239 19:22:42.033837 WR_PRE = 0x1
7240 19:22:42.037431 WR_PST = 0x1
7241 19:22:42.037534 DBI_WR = 0x0
7242 19:22:42.040542 DBI_RD = 0x0
7243 19:22:42.040624 OTF = 0x1
7244 19:22:42.043726 ===================================
7245 19:22:42.050633 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7246 19:22:42.050712 ==
7247 19:22:42.053887 Dram Type= 6, Freq= 0, CH_0, rank 0
7248 19:22:42.059863 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7249 19:22:42.060009 ==
7250 19:22:42.060080 [Duty_Offset_Calibration]
7251 19:22:42.063368 B0:2 B1:0 CA:4
7252 19:22:42.063448
7253 19:22:42.066684 [DutyScan_Calibration_Flow] k_type=0
7254 19:22:42.075514
7255 19:22:42.075620 ==CLK 0==
7256 19:22:42.078476 Final CLK duty delay cell = -4
7257 19:22:42.082247 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7258 19:22:42.085242 [-4] MIN Duty = 4844%(X100), DQS PI = 2
7259 19:22:42.088372 [-4] AVG Duty = 4937%(X100)
7260 19:22:42.088452
7261 19:22:42.091973 CH0 CLK Duty spec in!! Max-Min= 187%
7262 19:22:42.094845 [DutyScan_Calibration_Flow] ====Done====
7263 19:22:42.094924
7264 19:22:42.098323 [DutyScan_Calibration_Flow] k_type=1
7265 19:22:42.115514
7266 19:22:42.115595 ==DQS 0 ==
7267 19:22:42.119116 Final DQS duty delay cell = 0
7268 19:22:42.122155 [0] MAX Duty = 5249%(X100), DQS PI = 38
7269 19:22:42.125690 [0] MIN Duty = 5093%(X100), DQS PI = 4
7270 19:22:42.128927 [0] AVG Duty = 5171%(X100)
7271 19:22:42.129008
7272 19:22:42.129072 ==DQS 1 ==
7273 19:22:42.132034 Final DQS duty delay cell = 0
7274 19:22:42.135486 [0] MAX Duty = 5156%(X100), DQS PI = 2
7275 19:22:42.138677 [0] MIN Duty = 4938%(X100), DQS PI = 58
7276 19:22:42.142233 [0] AVG Duty = 5047%(X100)
7277 19:22:42.142313
7278 19:22:42.145260 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7279 19:22:42.145341
7280 19:22:42.148328 CH0 DQS 1 Duty spec in!! Max-Min= 218%
7281 19:22:42.152350 [DutyScan_Calibration_Flow] ====Done====
7282 19:22:42.152435
7283 19:22:42.155058 [DutyScan_Calibration_Flow] k_type=3
7284 19:22:42.172587
7285 19:22:42.172672 ==DQM 0 ==
7286 19:22:42.176155 Final DQM duty delay cell = 0
7287 19:22:42.179139 [0] MAX Duty = 5124%(X100), DQS PI = 22
7288 19:22:42.182673 [0] MIN Duty = 4875%(X100), DQS PI = 54
7289 19:22:42.185658 [0] AVG Duty = 4999%(X100)
7290 19:22:42.185740
7291 19:22:42.185804 ==DQM 1 ==
7292 19:22:42.188710 Final DQM duty delay cell = 0
7293 19:22:42.192421 [0] MAX Duty = 5000%(X100), DQS PI = 2
7294 19:22:42.195388 [0] MIN Duty = 4813%(X100), DQS PI = 16
7295 19:22:42.198835 [0] AVG Duty = 4906%(X100)
7296 19:22:42.198919
7297 19:22:42.202371 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7298 19:22:42.202453
7299 19:22:42.205240 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7300 19:22:42.208787 [DutyScan_Calibration_Flow] ====Done====
7301 19:22:42.208869
7302 19:22:42.211707 [DutyScan_Calibration_Flow] k_type=2
7303 19:22:42.229654
7304 19:22:42.229746 ==DQ 0 ==
7305 19:22:42.233325 Final DQ duty delay cell = 0
7306 19:22:42.236285 [0] MAX Duty = 5156%(X100), DQS PI = 22
7307 19:22:42.239921 [0] MIN Duty = 4938%(X100), DQS PI = 12
7308 19:22:42.240003 [0] AVG Duty = 5047%(X100)
7309 19:22:42.242951
7310 19:22:42.243031 ==DQ 1 ==
7311 19:22:42.246186 Final DQ duty delay cell = 0
7312 19:22:42.250048 [0] MAX Duty = 5218%(X100), DQS PI = 4
7313 19:22:42.252725 [0] MIN Duty = 4907%(X100), DQS PI = 34
7314 19:22:42.252807 [0] AVG Duty = 5062%(X100)
7315 19:22:42.256387
7316 19:22:42.259480 CH0 DQ 0 Duty spec in!! Max-Min= 218%
7317 19:22:42.259561
7318 19:22:42.262638 CH0 DQ 1 Duty spec in!! Max-Min= 311%
7319 19:22:42.266187 [DutyScan_Calibration_Flow] ====Done====
7320 19:22:42.266268 ==
7321 19:22:42.269281 Dram Type= 6, Freq= 0, CH_1, rank 0
7322 19:22:42.272619 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7323 19:22:42.272713 ==
7324 19:22:42.276008 [Duty_Offset_Calibration]
7325 19:22:42.276091 B0:0 B1:-1 CA:3
7326 19:22:42.276178
7327 19:22:42.279353 [DutyScan_Calibration_Flow] k_type=0
7328 19:22:42.289308
7329 19:22:42.289400 ==CLK 0==
7330 19:22:42.292421 Final CLK duty delay cell = -4
7331 19:22:42.295748 [-4] MAX Duty = 5031%(X100), DQS PI = 34
7332 19:22:42.298915 [-4] MIN Duty = 4813%(X100), DQS PI = 4
7333 19:22:42.302532 [-4] AVG Duty = 4922%(X100)
7334 19:22:42.302648
7335 19:22:42.305562 CH1 CLK Duty spec in!! Max-Min= 218%
7336 19:22:42.309181 [DutyScan_Calibration_Flow] ====Done====
7337 19:22:42.309261
7338 19:22:42.312084 [DutyScan_Calibration_Flow] k_type=1
7339 19:22:42.328240
7340 19:22:42.328327 ==DQS 0 ==
7341 19:22:42.331876 Final DQS duty delay cell = 0
7342 19:22:42.334753 [0] MAX Duty = 5156%(X100), DQS PI = 0
7343 19:22:42.338387 [0] MIN Duty = 4907%(X100), DQS PI = 8
7344 19:22:42.341468 [0] AVG Duty = 5031%(X100)
7345 19:22:42.341550
7346 19:22:42.341615 ==DQS 1 ==
7347 19:22:42.345088 Final DQS duty delay cell = -4
7348 19:22:42.348098 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7349 19:22:42.351653 [-4] MIN Duty = 4813%(X100), DQS PI = 50
7350 19:22:42.354447 [-4] AVG Duty = 4906%(X100)
7351 19:22:42.354526
7352 19:22:42.357980 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7353 19:22:42.358065
7354 19:22:42.361089 CH1 DQS 1 Duty spec in!! Max-Min= 187%
7355 19:22:42.364557 [DutyScan_Calibration_Flow] ====Done====
7356 19:22:42.364637
7357 19:22:42.367565 [DutyScan_Calibration_Flow] k_type=3
7358 19:22:42.385332
7359 19:22:42.385411 ==DQM 0 ==
7360 19:22:42.388639 Final DQM duty delay cell = 0
7361 19:22:42.392080 [0] MAX Duty = 5031%(X100), DQS PI = 36
7362 19:22:42.395106 [0] MIN Duty = 4750%(X100), DQS PI = 8
7363 19:22:42.398482 [0] AVG Duty = 4890%(X100)
7364 19:22:42.398614
7365 19:22:42.398708 ==DQM 1 ==
7366 19:22:42.401779 Final DQM duty delay cell = 0
7367 19:22:42.405002 [0] MAX Duty = 4969%(X100), DQS PI = 0
7368 19:22:42.408597 [0] MIN Duty = 4813%(X100), DQS PI = 28
7369 19:22:42.411503 [0] AVG Duty = 4891%(X100)
7370 19:22:42.411577
7371 19:22:42.414813 CH1 DQM 0 Duty spec in!! Max-Min= 281%
7372 19:22:42.414890
7373 19:22:42.418427 CH1 DQM 1 Duty spec in!! Max-Min= 156%
7374 19:22:42.421495 [DutyScan_Calibration_Flow] ====Done====
7375 19:22:42.421567
7376 19:22:42.424938 [DutyScan_Calibration_Flow] k_type=2
7377 19:22:42.442430
7378 19:22:42.442520 ==DQ 0 ==
7379 19:22:42.445445 Final DQ duty delay cell = 0
7380 19:22:42.449091 [0] MAX Duty = 5187%(X100), DQS PI = 0
7381 19:22:42.452093 [0] MIN Duty = 5031%(X100), DQS PI = 6
7382 19:22:42.452172 [0] AVG Duty = 5109%(X100)
7383 19:22:42.452235
7384 19:22:42.455717 ==DQ 1 ==
7385 19:22:42.458814 Final DQ duty delay cell = 0
7386 19:22:42.462439 [0] MAX Duty = 5031%(X100), DQS PI = 0
7387 19:22:42.465532 [0] MIN Duty = 4844%(X100), DQS PI = 28
7388 19:22:42.465625 [0] AVG Duty = 4937%(X100)
7389 19:22:42.465709
7390 19:22:42.468444 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7391 19:22:42.468531
7392 19:22:42.475590 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7393 19:22:42.478609 [DutyScan_Calibration_Flow] ====Done====
7394 19:22:42.482135 nWR fixed to 30
7395 19:22:42.482218 [ModeRegInit_LP4] CH0 RK0
7396 19:22:42.485133 [ModeRegInit_LP4] CH0 RK1
7397 19:22:42.488165 [ModeRegInit_LP4] CH1 RK0
7398 19:22:42.491715 [ModeRegInit_LP4] CH1 RK1
7399 19:22:42.491822 match AC timing 5
7400 19:22:42.498140 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7401 19:22:42.501811 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7402 19:22:42.504872 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7403 19:22:42.511371 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7404 19:22:42.514505 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7405 19:22:42.514586 [MiockJmeterHQA]
7406 19:22:42.514651
7407 19:22:42.517765 [DramcMiockJmeter] u1RxGatingPI = 0
7408 19:22:42.521315 0 : 4258, 4032
7409 19:22:42.521397 4 : 4363, 4138
7410 19:22:42.524688 8 : 4253, 4026
7411 19:22:42.524771 12 : 4253, 4027
7412 19:22:42.528073 16 : 4252, 4027
7413 19:22:42.528182 20 : 4253, 4027
7414 19:22:42.528283 24 : 4363, 4137
7415 19:22:42.531157 28 : 4363, 4137
7416 19:22:42.531266 32 : 4252, 4027
7417 19:22:42.534425 36 : 4252, 4027
7418 19:22:42.534510 40 : 4253, 4027
7419 19:22:42.538024 44 : 4252, 4027
7420 19:22:42.538108 48 : 4252, 4027
7421 19:22:42.540986 52 : 4255, 4030
7422 19:22:42.541070 56 : 4252, 4027
7423 19:22:42.541155 60 : 4253, 4027
7424 19:22:42.544530 64 : 4254, 4029
7425 19:22:42.544614 68 : 4255, 4029
7426 19:22:42.547464 72 : 4255, 4030
7427 19:22:42.547572 76 : 4360, 4137
7428 19:22:42.551125 80 : 4361, 4137
7429 19:22:42.551208 84 : 4363, 4140
7430 19:22:42.554126 88 : 4253, 4029
7431 19:22:42.554234 92 : 4252, 4030
7432 19:22:42.554337 96 : 4249, 2777
7433 19:22:42.557210 100 : 4250, 0
7434 19:22:42.557281 104 : 4250, 0
7435 19:22:42.560854 108 : 4250, 0
7436 19:22:42.560924 112 : 4363, 0
7437 19:22:42.560997 116 : 4361, 0
7438 19:22:42.564415 120 : 4361, 0
7439 19:22:42.564495 124 : 4250, 0
7440 19:22:42.567439 128 : 4250, 0
7441 19:22:42.567540 132 : 4250, 0
7442 19:22:42.567629 136 : 4250, 0
7443 19:22:42.570539 140 : 4250, 0
7444 19:22:42.570635 144 : 4250, 0
7445 19:22:42.570731 148 : 4250, 0
7446 19:22:42.574204 152 : 4252, 0
7447 19:22:42.574300 156 : 4250, 0
7448 19:22:42.577190 160 : 4250, 0
7449 19:22:42.577267 164 : 4255, 0
7450 19:22:42.577327 168 : 4361, 0
7451 19:22:42.580655 172 : 4360, 0
7452 19:22:42.580737 176 : 4363, 0
7453 19:22:42.583868 180 : 4250, 0
7454 19:22:42.583973 184 : 4250, 0
7455 19:22:42.584035 188 : 4250, 0
7456 19:22:42.586963 192 : 4250, 0
7457 19:22:42.587057 196 : 4250, 0
7458 19:22:42.590710 200 : 4253, 0
7459 19:22:42.590827 204 : 4252, 0
7460 19:22:42.590926 208 : 4250, 0
7461 19:22:42.593801 212 : 4254, 0
7462 19:22:42.593900 216 : 4252, 0
7463 19:22:42.597273 220 : 4361, 604
7464 19:22:42.597378 224 : 4250, 3993
7465 19:22:42.600263 228 : 4250, 4027
7466 19:22:42.600367 232 : 4253, 4029
7467 19:22:42.600458 236 : 4250, 4027
7468 19:22:42.603881 240 : 4363, 4139
7469 19:22:42.604003 244 : 4250, 4027
7470 19:22:42.606826 248 : 4250, 4027
7471 19:22:42.606921 252 : 4363, 4140
7472 19:22:42.610523 256 : 4250, 4026
7473 19:22:42.610618 260 : 4250, 4027
7474 19:22:42.613561 264 : 4361, 4137
7475 19:22:42.613638 268 : 4360, 4137
7476 19:22:42.616546 272 : 4250, 4026
7477 19:22:42.616627 276 : 4250, 4027
7478 19:22:42.620123 280 : 4250, 4027
7479 19:22:42.620221 284 : 4251, 4027
7480 19:22:42.623736 288 : 4250, 4027
7481 19:22:42.623839 292 : 4361, 4137
7482 19:22:42.626951 296 : 4250, 4027
7483 19:22:42.627047 300 : 4249, 4027
7484 19:22:42.627144 304 : 4364, 4140
7485 19:22:42.629664 308 : 4248, 4024
7486 19:22:42.629768 312 : 4250, 4027
7487 19:22:42.633043 316 : 4361, 4137
7488 19:22:42.633129 320 : 4361, 4137
7489 19:22:42.636708 324 : 4250, 4026
7490 19:22:42.636794 328 : 4250, 4027
7491 19:22:42.639996 332 : 4252, 3936
7492 19:22:42.640079 336 : 4249, 1533
7493 19:22:42.640148
7494 19:22:42.643072 MIOCK jitter meter ch=0
7495 19:22:42.643153
7496 19:22:42.646485 1T = (336-100) = 236 dly cells
7497 19:22:42.653247 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7498 19:22:42.653338 ==
7499 19:22:42.656335 Dram Type= 6, Freq= 0, CH_0, rank 0
7500 19:22:42.659421 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7501 19:22:42.659523 ==
7502 19:22:42.666058 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7503 19:22:42.669665 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7504 19:22:42.672800 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7505 19:22:42.679395 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7506 19:22:42.688016 [CA 0] Center 43 (13~74) winsize 62
7507 19:22:42.691891 [CA 1] Center 42 (12~73) winsize 62
7508 19:22:42.694586 [CA 2] Center 37 (8~67) winsize 60
7509 19:22:42.698047 [CA 3] Center 37 (8~67) winsize 60
7510 19:22:42.701231 [CA 4] Center 36 (6~66) winsize 61
7511 19:22:42.705115 [CA 5] Center 35 (5~66) winsize 62
7512 19:22:42.705191
7513 19:22:42.708107 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7514 19:22:42.708178
7515 19:22:42.714457 [CATrainingPosCal] consider 1 rank data
7516 19:22:42.714533 u2DelayCellTimex100 = 275/100 ps
7517 19:22:42.721126 CA0 delay=43 (13~74),Diff = 8 PI (28 cell)
7518 19:22:42.724628 CA1 delay=42 (12~73),Diff = 7 PI (24 cell)
7519 19:22:42.727616 CA2 delay=37 (8~67),Diff = 2 PI (7 cell)
7520 19:22:42.731212 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7521 19:22:42.734321 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7522 19:22:42.737892 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
7523 19:22:42.737990
7524 19:22:42.740829 CA PerBit enable=1, Macro0, CA PI delay=35
7525 19:22:42.740901
7526 19:22:42.744192 [CBTSetCACLKResult] CA Dly = 35
7527 19:22:42.747723 CS Dly: 11 (0~42)
7528 19:22:42.750807 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7529 19:22:42.753940 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7530 19:22:42.754044 ==
7531 19:22:42.757273 Dram Type= 6, Freq= 0, CH_0, rank 1
7532 19:22:42.763937 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7533 19:22:42.764034 ==
7534 19:22:42.767364 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7535 19:22:42.774094 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7536 19:22:42.777124 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7537 19:22:42.783753 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7538 19:22:42.791660 [CA 0] Center 43 (13~74) winsize 62
7539 19:22:42.794825 [CA 1] Center 43 (13~74) winsize 62
7540 19:22:42.797942 [CA 2] Center 38 (9~68) winsize 60
7541 19:22:42.801661 [CA 3] Center 38 (9~68) winsize 60
7542 19:22:42.804694 [CA 4] Center 36 (6~67) winsize 62
7543 19:22:42.808187 [CA 5] Center 36 (6~66) winsize 61
7544 19:22:42.808269
7545 19:22:42.811050 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7546 19:22:42.811131
7547 19:22:42.818447 [CATrainingPosCal] consider 2 rank data
7548 19:22:42.818529 u2DelayCellTimex100 = 275/100 ps
7549 19:22:42.824182 CA0 delay=43 (13~74),Diff = 7 PI (24 cell)
7550 19:22:42.827686 CA1 delay=43 (13~73),Diff = 7 PI (24 cell)
7551 19:22:42.831187 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
7552 19:22:42.834280 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7553 19:22:42.837330 CA4 delay=36 (6~66),Diff = 0 PI (0 cell)
7554 19:22:42.840498 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7555 19:22:42.840579
7556 19:22:42.844118 CA PerBit enable=1, Macro0, CA PI delay=36
7557 19:22:42.844199
7558 19:22:42.847121 [CBTSetCACLKResult] CA Dly = 36
7559 19:22:42.850462 CS Dly: 12 (0~44)
7560 19:22:42.853955 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7561 19:22:42.857430 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7562 19:22:42.857511
7563 19:22:42.860553 ----->DramcWriteLeveling(PI) begin...
7564 19:22:42.863672 ==
7565 19:22:42.867065 Dram Type= 6, Freq= 0, CH_0, rank 0
7566 19:22:42.870396 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7567 19:22:42.870482 ==
7568 19:22:42.873691 Write leveling (Byte 0): 36 => 36
7569 19:22:42.876986 Write leveling (Byte 1): 27 => 27
7570 19:22:42.880253 DramcWriteLeveling(PI) end<-----
7571 19:22:42.880358
7572 19:22:42.880448 ==
7573 19:22:42.883314 Dram Type= 6, Freq= 0, CH_0, rank 0
7574 19:22:42.886557 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7575 19:22:42.886639 ==
7576 19:22:42.889876 [Gating] SW mode calibration
7577 19:22:42.896483 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7578 19:22:42.903177 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7579 19:22:42.906227 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7580 19:22:42.909960 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7581 19:22:42.916297 1 4 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7582 19:22:42.919425 1 4 12 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
7583 19:22:42.923062 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7584 19:22:42.929377 1 4 20 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
7585 19:22:42.932703 1 4 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7586 19:22:42.935841 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7587 19:22:42.942488 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7588 19:22:42.945661 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7589 19:22:42.949180 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
7590 19:22:42.955869 1 5 12 | B1->B0 | 3434 2525 | 1 0 | (1 1) (1 0)
7591 19:22:42.958866 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7592 19:22:42.962535 1 5 20 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
7593 19:22:42.969216 1 5 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
7594 19:22:42.972213 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7595 19:22:42.975720 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7596 19:22:42.982201 1 6 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
7597 19:22:42.985991 1 6 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (0 0)
7598 19:22:42.988823 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7599 19:22:42.995467 1 6 16 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
7600 19:22:42.998580 1 6 20 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
7601 19:22:43.001619 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7602 19:22:43.008661 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7603 19:22:43.011646 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7604 19:22:43.015247 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7605 19:22:43.021736 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7606 19:22:43.024805 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7607 19:22:43.028313 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7608 19:22:43.035019 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7609 19:22:43.037815 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7610 19:22:43.041148 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7611 19:22:43.048202 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7612 19:22:43.051759 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7613 19:22:43.054448 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7614 19:22:43.061300 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7615 19:22:43.064330 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 19:22:43.067800 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 19:22:43.074493 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 19:22:43.078047 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 19:22:43.081124 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 19:22:43.087233 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7621 19:22:43.090905 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7622 19:22:43.093913 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7623 19:22:43.100603 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7624 19:22:43.104250 Total UI for P1: 0, mck2ui 16
7625 19:22:43.107669 best dqsien dly found for B0: ( 1, 9, 8)
7626 19:22:43.110846 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7627 19:22:43.114060 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7628 19:22:43.120461 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7629 19:22:43.120543 Total UI for P1: 0, mck2ui 16
7630 19:22:43.127030 best dqsien dly found for B1: ( 1, 9, 22)
7631 19:22:43.129968 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
7632 19:22:43.133650 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7633 19:22:43.133737
7634 19:22:43.136683 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
7635 19:22:43.140411 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7636 19:22:43.143466 [Gating] SW calibration Done
7637 19:22:43.143563 ==
7638 19:22:43.146953 Dram Type= 6, Freq= 0, CH_0, rank 0
7639 19:22:43.150358 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7640 19:22:43.150463 ==
7641 19:22:43.153195 RX Vref Scan: 0
7642 19:22:43.153272
7643 19:22:43.156820 RX Vref 0 -> 0, step: 1
7644 19:22:43.156895
7645 19:22:43.156966 RX Delay 0 -> 252, step: 8
7646 19:22:43.163028 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7647 19:22:43.166556 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7648 19:22:43.169646 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7649 19:22:43.173257 iDelay=192, Bit 3, Center 127 (80 ~ 175) 96
7650 19:22:43.176531 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7651 19:22:43.179831 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7652 19:22:43.186130 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7653 19:22:43.189707 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7654 19:22:43.193397 iDelay=192, Bit 8, Center 119 (64 ~ 175) 112
7655 19:22:43.196240 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7656 19:22:43.199848 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7657 19:22:43.206605 iDelay=192, Bit 11, Center 123 (72 ~ 175) 104
7658 19:22:43.209633 iDelay=192, Bit 12, Center 135 (80 ~ 191) 112
7659 19:22:43.213181 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7660 19:22:43.216117 iDelay=192, Bit 14, Center 139 (88 ~ 191) 104
7661 19:22:43.222637 iDelay=192, Bit 15, Center 131 (80 ~ 183) 104
7662 19:22:43.222741 ==
7663 19:22:43.225857 Dram Type= 6, Freq= 0, CH_0, rank 0
7664 19:22:43.229128 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7665 19:22:43.229255 ==
7666 19:22:43.229322 DQS Delay:
7667 19:22:43.232773 DQS0 = 0, DQS1 = 0
7668 19:22:43.232884 DQM Delay:
7669 19:22:43.236342 DQM0 = 131, DQM1 = 127
7670 19:22:43.236438 DQ Delay:
7671 19:22:43.239261 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7672 19:22:43.242361 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7673 19:22:43.246177 DQ8 =119, DQ9 =111, DQ10 =127, DQ11 =123
7674 19:22:43.249030 DQ12 =135, DQ13 =131, DQ14 =139, DQ15 =131
7675 19:22:43.249141
7676 19:22:43.252196
7677 19:22:43.252276 ==
7678 19:22:43.255786 Dram Type= 6, Freq= 0, CH_0, rank 0
7679 19:22:43.258936 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7680 19:22:43.259018 ==
7681 19:22:43.259083
7682 19:22:43.259143
7683 19:22:43.262102 TX Vref Scan disable
7684 19:22:43.262184 == TX Byte 0 ==
7685 19:22:43.268736 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7686 19:22:43.272090 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7687 19:22:43.272172 == TX Byte 1 ==
7688 19:22:43.278493 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7689 19:22:43.282132 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7690 19:22:43.282214 ==
7691 19:22:43.285342 Dram Type= 6, Freq= 0, CH_0, rank 0
7692 19:22:43.288388 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7693 19:22:43.288469 ==
7694 19:22:43.303088
7695 19:22:43.306623 TX Vref early break, caculate TX vref
7696 19:22:43.309634 TX Vref=16, minBit 4, minWin=22, winSum=370
7697 19:22:43.313258 TX Vref=18, minBit 8, minWin=22, winSum=376
7698 19:22:43.316262 TX Vref=20, minBit 8, minWin=23, winSum=389
7699 19:22:43.320087 TX Vref=22, minBit 8, minWin=23, winSum=404
7700 19:22:43.323100 TX Vref=24, minBit 1, minWin=25, winSum=415
7701 19:22:43.329601 TX Vref=26, minBit 4, minWin=25, winSum=419
7702 19:22:43.332808 TX Vref=28, minBit 6, minWin=25, winSum=421
7703 19:22:43.336456 TX Vref=30, minBit 2, minWin=25, winSum=416
7704 19:22:43.339701 TX Vref=32, minBit 0, minWin=25, winSum=410
7705 19:22:43.342994 TX Vref=34, minBit 0, minWin=24, winSum=397
7706 19:22:43.349730 [TxChooseVref] Worse bit 6, Min win 25, Win sum 421, Final Vref 28
7707 19:22:43.349816
7708 19:22:43.352783 Final TX Range 0 Vref 28
7709 19:22:43.352865
7710 19:22:43.352929 ==
7711 19:22:43.356421 Dram Type= 6, Freq= 0, CH_0, rank 0
7712 19:22:43.359539 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7713 19:22:43.359631 ==
7714 19:22:43.359699
7715 19:22:43.359759
7716 19:22:43.362590 TX Vref Scan disable
7717 19:22:43.369257 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7718 19:22:43.369339 == TX Byte 0 ==
7719 19:22:43.372349 u2DelayCellOfst[0]=14 cells (4 PI)
7720 19:22:43.375806 u2DelayCellOfst[1]=17 cells (5 PI)
7721 19:22:43.379048 u2DelayCellOfst[2]=14 cells (4 PI)
7722 19:22:43.382459 u2DelayCellOfst[3]=14 cells (4 PI)
7723 19:22:43.385945 u2DelayCellOfst[4]=10 cells (3 PI)
7724 19:22:43.389029 u2DelayCellOfst[5]=0 cells (0 PI)
7725 19:22:43.392074 u2DelayCellOfst[6]=21 cells (6 PI)
7726 19:22:43.395564 u2DelayCellOfst[7]=17 cells (5 PI)
7727 19:22:43.398631 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7728 19:22:43.401841 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7729 19:22:43.405114 == TX Byte 1 ==
7730 19:22:43.408596 u2DelayCellOfst[8]=0 cells (0 PI)
7731 19:22:43.411849 u2DelayCellOfst[9]=0 cells (0 PI)
7732 19:22:43.415489 u2DelayCellOfst[10]=7 cells (2 PI)
7733 19:22:43.418502 u2DelayCellOfst[11]=3 cells (1 PI)
7734 19:22:43.418584 u2DelayCellOfst[12]=7 cells (2 PI)
7735 19:22:43.421579 u2DelayCellOfst[13]=10 cells (3 PI)
7736 19:22:43.425251 u2DelayCellOfst[14]=14 cells (4 PI)
7737 19:22:43.428332 u2DelayCellOfst[15]=10 cells (3 PI)
7738 19:22:43.435108 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7739 19:22:43.438047 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7740 19:22:43.438129 DramC Write-DBI on
7741 19:22:43.441590 ==
7742 19:22:43.444841 Dram Type= 6, Freq= 0, CH_0, rank 0
7743 19:22:43.448205 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7744 19:22:43.448290 ==
7745 19:22:43.448355
7746 19:22:43.448415
7747 19:22:43.451392 TX Vref Scan disable
7748 19:22:43.451519 == TX Byte 0 ==
7749 19:22:43.458017 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7750 19:22:43.458099 == TX Byte 1 ==
7751 19:22:43.461054 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7752 19:22:43.464746 DramC Write-DBI off
7753 19:22:43.464829
7754 19:22:43.464894 [DATLAT]
7755 19:22:43.467839 Freq=1600, CH0 RK0
7756 19:22:43.467944
7757 19:22:43.468009 DATLAT Default: 0xf
7758 19:22:43.471439 0, 0xFFFF, sum = 0
7759 19:22:43.471521 1, 0xFFFF, sum = 0
7760 19:22:43.474735 2, 0xFFFF, sum = 0
7761 19:22:43.477892 3, 0xFFFF, sum = 0
7762 19:22:43.477975 4, 0xFFFF, sum = 0
7763 19:22:43.480904 5, 0xFFFF, sum = 0
7764 19:22:43.480986 6, 0xFFFF, sum = 0
7765 19:22:43.484363 7, 0xFFFF, sum = 0
7766 19:22:43.484448 8, 0xFFFF, sum = 0
7767 19:22:43.487803 9, 0xFFFF, sum = 0
7768 19:22:43.487932 10, 0xFFFF, sum = 0
7769 19:22:43.491163 11, 0xFFFF, sum = 0
7770 19:22:43.491245 12, 0xFFFF, sum = 0
7771 19:22:43.494093 13, 0xFFFF, sum = 0
7772 19:22:43.494176 14, 0x0, sum = 1
7773 19:22:43.497934 15, 0x0, sum = 2
7774 19:22:43.498017 16, 0x0, sum = 3
7775 19:22:43.500821 17, 0x0, sum = 4
7776 19:22:43.500904 best_step = 15
7777 19:22:43.500968
7778 19:22:43.501028 ==
7779 19:22:43.503971 Dram Type= 6, Freq= 0, CH_0, rank 0
7780 19:22:43.507496 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7781 19:22:43.511069 ==
7782 19:22:43.511149 RX Vref Scan: 1
7783 19:22:43.511214
7784 19:22:43.513816 Set Vref Range= 24 -> 127
7785 19:22:43.513896
7786 19:22:43.517683 RX Vref 24 -> 127, step: 1
7787 19:22:43.517764
7788 19:22:43.517828 RX Delay 11 -> 252, step: 4
7789 19:22:43.517889
7790 19:22:43.520956 Set Vref, RX VrefLevel [Byte0]: 24
7791 19:22:43.524044 [Byte1]: 24
7792 19:22:43.528202
7793 19:22:43.528282 Set Vref, RX VrefLevel [Byte0]: 25
7794 19:22:43.531240 [Byte1]: 25
7795 19:22:43.535699
7796 19:22:43.535808 Set Vref, RX VrefLevel [Byte0]: 26
7797 19:22:43.539081 [Byte1]: 26
7798 19:22:43.543212
7799 19:22:43.543293 Set Vref, RX VrefLevel [Byte0]: 27
7800 19:22:43.546243 [Byte1]: 27
7801 19:22:43.550927
7802 19:22:43.551008 Set Vref, RX VrefLevel [Byte0]: 28
7803 19:22:43.553833 [Byte1]: 28
7804 19:22:43.558441
7805 19:22:43.558521 Set Vref, RX VrefLevel [Byte0]: 29
7806 19:22:43.561693 [Byte1]: 29
7807 19:22:43.565773
7808 19:22:43.565888 Set Vref, RX VrefLevel [Byte0]: 30
7809 19:22:43.569453 [Byte1]: 30
7810 19:22:43.573688
7811 19:22:43.576760 Set Vref, RX VrefLevel [Byte0]: 31
7812 19:22:43.580484 [Byte1]: 31
7813 19:22:43.580558
7814 19:22:43.583337 Set Vref, RX VrefLevel [Byte0]: 32
7815 19:22:43.586792 [Byte1]: 32
7816 19:22:43.586889
7817 19:22:43.589666 Set Vref, RX VrefLevel [Byte0]: 33
7818 19:22:43.593194 [Byte1]: 33
7819 19:22:43.596494
7820 19:22:43.596600 Set Vref, RX VrefLevel [Byte0]: 34
7821 19:22:43.599981 [Byte1]: 34
7822 19:22:43.604084
7823 19:22:43.604164 Set Vref, RX VrefLevel [Byte0]: 35
7824 19:22:43.607123 [Byte1]: 35
7825 19:22:43.612017
7826 19:22:43.612097 Set Vref, RX VrefLevel [Byte0]: 36
7827 19:22:43.615075 [Byte1]: 36
7828 19:22:43.619319
7829 19:22:43.619399 Set Vref, RX VrefLevel [Byte0]: 37
7830 19:22:43.622630 [Byte1]: 37
7831 19:22:43.627051
7832 19:22:43.627132 Set Vref, RX VrefLevel [Byte0]: 38
7833 19:22:43.630012 [Byte1]: 38
7834 19:22:43.634623
7835 19:22:43.634704 Set Vref, RX VrefLevel [Byte0]: 39
7836 19:22:43.637607 [Byte1]: 39
7837 19:22:43.641893
7838 19:22:43.641974 Set Vref, RX VrefLevel [Byte0]: 40
7839 19:22:43.645564 [Byte1]: 40
7840 19:22:43.649737
7841 19:22:43.649817 Set Vref, RX VrefLevel [Byte0]: 41
7842 19:22:43.653196 [Byte1]: 41
7843 19:22:43.657412
7844 19:22:43.657492 Set Vref, RX VrefLevel [Byte0]: 42
7845 19:22:43.660451 [Byte1]: 42
7846 19:22:43.665343
7847 19:22:43.665423 Set Vref, RX VrefLevel [Byte0]: 43
7848 19:22:43.668503 [Byte1]: 43
7849 19:22:43.672399
7850 19:22:43.672480 Set Vref, RX VrefLevel [Byte0]: 44
7851 19:22:43.676113 [Byte1]: 44
7852 19:22:43.680378
7853 19:22:43.680459 Set Vref, RX VrefLevel [Byte0]: 45
7854 19:22:43.683444 [Byte1]: 45
7855 19:22:43.687745
7856 19:22:43.687826 Set Vref, RX VrefLevel [Byte0]: 46
7857 19:22:43.691167 [Byte1]: 46
7858 19:22:43.695171
7859 19:22:43.695252 Set Vref, RX VrefLevel [Byte0]: 47
7860 19:22:43.698541 [Byte1]: 47
7861 19:22:43.703263
7862 19:22:43.703346 Set Vref, RX VrefLevel [Byte0]: 48
7863 19:22:43.706653 [Byte1]: 48
7864 19:22:43.710684
7865 19:22:43.710765 Set Vref, RX VrefLevel [Byte0]: 49
7866 19:22:43.713705 [Byte1]: 49
7867 19:22:43.718073
7868 19:22:43.718155 Set Vref, RX VrefLevel [Byte0]: 50
7869 19:22:43.721674 [Byte1]: 50
7870 19:22:43.725906
7871 19:22:43.725987 Set Vref, RX VrefLevel [Byte0]: 51
7872 19:22:43.728908 [Byte1]: 51
7873 19:22:43.733618
7874 19:22:43.733702 Set Vref, RX VrefLevel [Byte0]: 52
7875 19:22:43.736941 [Byte1]: 52
7876 19:22:43.741413
7877 19:22:43.741494 Set Vref, RX VrefLevel [Byte0]: 53
7878 19:22:43.744253 [Byte1]: 53
7879 19:22:43.748824
7880 19:22:43.748907 Set Vref, RX VrefLevel [Byte0]: 54
7881 19:22:43.751981 [Byte1]: 54
7882 19:22:43.756062
7883 19:22:43.756142 Set Vref, RX VrefLevel [Byte0]: 55
7884 19:22:43.759622 [Byte1]: 55
7885 19:22:43.763842
7886 19:22:43.763966 Set Vref, RX VrefLevel [Byte0]: 56
7887 19:22:43.766987 [Byte1]: 56
7888 19:22:43.771270
7889 19:22:43.771350 Set Vref, RX VrefLevel [Byte0]: 57
7890 19:22:43.774830 [Byte1]: 57
7891 19:22:43.779236
7892 19:22:43.779394 Set Vref, RX VrefLevel [Byte0]: 58
7893 19:22:43.782236 [Byte1]: 58
7894 19:22:43.786572
7895 19:22:43.786695 Set Vref, RX VrefLevel [Byte0]: 59
7896 19:22:43.790062 [Byte1]: 59
7897 19:22:43.794441
7898 19:22:43.794521 Set Vref, RX VrefLevel [Byte0]: 60
7899 19:22:43.797933 [Byte1]: 60
7900 19:22:43.801889
7901 19:22:43.801970 Set Vref, RX VrefLevel [Byte0]: 61
7902 19:22:43.805281 [Byte1]: 61
7903 19:22:43.809479
7904 19:22:43.809556 Set Vref, RX VrefLevel [Byte0]: 62
7905 19:22:43.812999 [Byte1]: 62
7906 19:22:43.817484
7907 19:22:43.817558 Set Vref, RX VrefLevel [Byte0]: 63
7908 19:22:43.820342 [Byte1]: 63
7909 19:22:43.824598
7910 19:22:43.824672 Set Vref, RX VrefLevel [Byte0]: 64
7911 19:22:43.828291 [Byte1]: 64
7912 19:22:43.832495
7913 19:22:43.832573 Set Vref, RX VrefLevel [Byte0]: 65
7914 19:22:43.835644 [Byte1]: 65
7915 19:22:43.839942
7916 19:22:43.840086 Set Vref, RX VrefLevel [Byte0]: 66
7917 19:22:43.843395 [Byte1]: 66
7918 19:22:43.847441
7919 19:22:43.847521 Set Vref, RX VrefLevel [Byte0]: 67
7920 19:22:43.851088 [Byte1]: 67
7921 19:22:43.855362
7922 19:22:43.855458 Set Vref, RX VrefLevel [Byte0]: 68
7923 19:22:43.858309 [Byte1]: 68
7924 19:22:43.863068
7925 19:22:43.863148 Set Vref, RX VrefLevel [Byte0]: 69
7926 19:22:43.866057 [Byte1]: 69
7927 19:22:43.870321
7928 19:22:43.870402 Set Vref, RX VrefLevel [Byte0]: 70
7929 19:22:43.873999 [Byte1]: 70
7930 19:22:43.878203
7931 19:22:43.878283 Set Vref, RX VrefLevel [Byte0]: 71
7932 19:22:43.881247 [Byte1]: 71
7933 19:22:43.886178
7934 19:22:43.886259 Set Vref, RX VrefLevel [Byte0]: 72
7935 19:22:43.888709 [Byte1]: 72
7936 19:22:43.893429
7937 19:22:43.893511 Set Vref, RX VrefLevel [Byte0]: 73
7938 19:22:43.896411 [Byte1]: 73
7939 19:22:43.901245
7940 19:22:43.901326 Set Vref, RX VrefLevel [Byte0]: 74
7941 19:22:43.904210 [Byte1]: 74
7942 19:22:43.908757
7943 19:22:43.908837 Set Vref, RX VrefLevel [Byte0]: 75
7944 19:22:43.911534 [Byte1]: 75
7945 19:22:43.915909
7946 19:22:43.916033 Set Vref, RX VrefLevel [Byte0]: 76
7947 19:22:43.919611 [Byte1]: 76
7948 19:22:43.923786
7949 19:22:43.923916 Final RX Vref Byte 0 = 55 to rank0
7950 19:22:43.926921 Final RX Vref Byte 1 = 60 to rank0
7951 19:22:43.930442 Final RX Vref Byte 0 = 55 to rank1
7952 19:22:43.933414 Final RX Vref Byte 1 = 60 to rank1==
7953 19:22:43.937101 Dram Type= 6, Freq= 0, CH_0, rank 0
7954 19:22:43.943316 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7955 19:22:43.943400 ==
7956 19:22:43.943466 DQS Delay:
7957 19:22:43.946840 DQS0 = 0, DQS1 = 0
7958 19:22:43.946943 DQM Delay:
7959 19:22:43.947036 DQM0 = 129, DQM1 = 123
7960 19:22:43.949845 DQ Delay:
7961 19:22:43.953436 DQ0 =130, DQ1 =130, DQ2 =126, DQ3 =126
7962 19:22:43.956860 DQ4 =130, DQ5 =118, DQ6 =138, DQ7 =134
7963 19:22:43.960263 DQ8 =112, DQ9 =112, DQ10 =124, DQ11 =120
7964 19:22:43.963454 DQ12 =132, DQ13 =128, DQ14 =132, DQ15 =130
7965 19:22:43.963535
7966 19:22:43.963600
7967 19:22:43.963659
7968 19:22:43.966694 [DramC_TX_OE_Calibration] TA2
7969 19:22:43.969778 Original DQ_B0 (3 6) =30, OEN = 27
7970 19:22:43.973212 Original DQ_B1 (3 6) =30, OEN = 27
7971 19:22:43.976311 24, 0x0, End_B0=24 End_B1=24
7972 19:22:43.979367 25, 0x0, End_B0=25 End_B1=25
7973 19:22:43.979449 26, 0x0, End_B0=26 End_B1=26
7974 19:22:43.983055 27, 0x0, End_B0=27 End_B1=27
7975 19:22:43.986127 28, 0x0, End_B0=28 End_B1=28
7976 19:22:43.989736 29, 0x0, End_B0=29 End_B1=29
7977 19:22:43.989819 30, 0x0, End_B0=30 End_B1=30
7978 19:22:43.992838 31, 0x4141, End_B0=30 End_B1=30
7979 19:22:43.996285 Byte0 end_step=30 best_step=27
7980 19:22:43.999675 Byte1 end_step=30 best_step=27
7981 19:22:44.002985 Byte0 TX OE(2T, 0.5T) = (3, 3)
7982 19:22:44.006257 Byte1 TX OE(2T, 0.5T) = (3, 3)
7983 19:22:44.006365
7984 19:22:44.006458
7985 19:22:44.012778 [DQSOSCAuto] RK0, (LSB)MR18= 0x1714, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
7986 19:22:44.016164 CH0 RK0: MR19=303, MR18=1714
7987 19:22:44.022679 CH0_RK0: MR19=0x303, MR18=0x1714, DQSOSC=398, MR23=63, INC=23, DEC=15
7988 19:22:44.022796
7989 19:22:44.025627 ----->DramcWriteLeveling(PI) begin...
7990 19:22:44.025711 ==
7991 19:22:44.028762 Dram Type= 6, Freq= 0, CH_0, rank 1
7992 19:22:44.032438 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7993 19:22:44.032536 ==
7994 19:22:44.035836 Write leveling (Byte 0): 35 => 35
7995 19:22:44.038807 Write leveling (Byte 1): 28 => 28
7996 19:22:44.042485 DramcWriteLeveling(PI) end<-----
7997 19:22:44.042566
7998 19:22:44.042631 ==
7999 19:22:44.045500 Dram Type= 6, Freq= 0, CH_0, rank 1
8000 19:22:44.052184 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8001 19:22:44.052265 ==
8002 19:22:44.052330 [Gating] SW mode calibration
8003 19:22:44.061852 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8004 19:22:44.065410 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8005 19:22:44.068496 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8006 19:22:44.075449 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8007 19:22:44.078317 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8008 19:22:44.085064 1 4 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
8009 19:22:44.088848 1 4 16 | B1->B0 | 2626 3434 | 0 1 | (1 1) (1 1)
8010 19:22:44.091776 1 4 20 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
8011 19:22:44.094875 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8012 19:22:44.101663 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8013 19:22:44.104722 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8014 19:22:44.108062 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8015 19:22:44.114982 1 5 8 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
8016 19:22:44.117886 1 5 12 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
8017 19:22:44.121319 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8018 19:22:44.128261 1 5 20 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
8019 19:22:44.131319 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8020 19:22:44.134967 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8021 19:22:44.141375 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8022 19:22:44.144825 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8023 19:22:44.147735 1 6 8 | B1->B0 | 2323 3f3f | 0 0 | (0 0) (0 0)
8024 19:22:44.154572 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8025 19:22:44.157616 1 6 16 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
8026 19:22:44.161029 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8027 19:22:44.167505 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8028 19:22:44.171087 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8029 19:22:44.177409 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8030 19:22:44.180740 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8031 19:22:44.184006 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8032 19:22:44.190610 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8033 19:22:44.193992 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8034 19:22:44.196958 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8035 19:22:44.203482 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8036 19:22:44.207155 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8037 19:22:44.210199 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8038 19:22:44.216696 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8039 19:22:44.220275 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8040 19:22:44.223816 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8041 19:22:44.230120 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 19:22:44.233178 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 19:22:44.236527 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 19:22:44.242942 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 19:22:44.246591 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8046 19:22:44.249373 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8047 19:22:44.256141 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8048 19:22:44.259747 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8049 19:22:44.262860 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8050 19:22:44.266607 Total UI for P1: 0, mck2ui 16
8051 19:22:44.269584 best dqsien dly found for B0: ( 1, 9, 8)
8052 19:22:44.276090 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8053 19:22:44.279149 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8054 19:22:44.282710 Total UI for P1: 0, mck2ui 16
8055 19:22:44.285756 best dqsien dly found for B1: ( 1, 9, 18)
8056 19:22:44.289429 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8057 19:22:44.292459 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8058 19:22:44.292540
8059 19:22:44.296145 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8060 19:22:44.299115 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8061 19:22:44.302618 [Gating] SW calibration Done
8062 19:22:44.302699 ==
8063 19:22:44.305504 Dram Type= 6, Freq= 0, CH_0, rank 1
8064 19:22:44.308819 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8065 19:22:44.312284 ==
8066 19:22:44.312365 RX Vref Scan: 0
8067 19:22:44.312431
8068 19:22:44.315399 RX Vref 0 -> 0, step: 1
8069 19:22:44.315479
8070 19:22:44.315544 RX Delay 0 -> 252, step: 8
8071 19:22:44.322325 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8072 19:22:44.325329 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8073 19:22:44.328758 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8074 19:22:44.332077 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8075 19:22:44.335366 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8076 19:22:44.342086 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8077 19:22:44.345413 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8078 19:22:44.348430 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8079 19:22:44.352123 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8080 19:22:44.358290 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8081 19:22:44.362099 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8082 19:22:44.365157 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8083 19:22:44.368252 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8084 19:22:44.371846 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8085 19:22:44.378506 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8086 19:22:44.381521 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8087 19:22:44.381601 ==
8088 19:22:44.385093 Dram Type= 6, Freq= 0, CH_0, rank 1
8089 19:22:44.388251 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8090 19:22:44.388332 ==
8091 19:22:44.391302 DQS Delay:
8092 19:22:44.391410 DQS0 = 0, DQS1 = 0
8093 19:22:44.391479 DQM Delay:
8094 19:22:44.394918 DQM0 = 132, DQM1 = 127
8095 19:22:44.394999 DQ Delay:
8096 19:22:44.397847 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
8097 19:22:44.401489 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
8098 19:22:44.407831 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =119
8099 19:22:44.410918 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =135
8100 19:22:44.411017
8101 19:22:44.411107
8102 19:22:44.411194 ==
8103 19:22:44.414612 Dram Type= 6, Freq= 0, CH_0, rank 1
8104 19:22:44.417551 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8105 19:22:44.417639 ==
8106 19:22:44.417728
8107 19:22:44.417820
8108 19:22:44.420986 TX Vref Scan disable
8109 19:22:44.424301 == TX Byte 0 ==
8110 19:22:44.427475 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8111 19:22:44.430801 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8112 19:22:44.434211 == TX Byte 1 ==
8113 19:22:44.437499 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8114 19:22:44.440692 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8115 19:22:44.440774 ==
8116 19:22:44.444058 Dram Type= 6, Freq= 0, CH_0, rank 1
8117 19:22:44.450452 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8118 19:22:44.450536 ==
8119 19:22:44.462773
8120 19:22:44.466138 TX Vref early break, caculate TX vref
8121 19:22:44.469172 TX Vref=16, minBit 1, minWin=23, winSum=379
8122 19:22:44.472700 TX Vref=18, minBit 0, minWin=24, winSum=391
8123 19:22:44.475786 TX Vref=20, minBit 2, minWin=24, winSum=395
8124 19:22:44.478834 TX Vref=22, minBit 0, minWin=25, winSum=407
8125 19:22:44.482442 TX Vref=24, minBit 1, minWin=25, winSum=416
8126 19:22:44.489066 TX Vref=26, minBit 4, minWin=25, winSum=420
8127 19:22:44.492149 TX Vref=28, minBit 3, minWin=25, winSum=422
8128 19:22:44.495753 TX Vref=30, minBit 0, minWin=25, winSum=418
8129 19:22:44.498842 TX Vref=32, minBit 1, minWin=24, winSum=406
8130 19:22:44.501974 TX Vref=34, minBit 0, minWin=24, winSum=397
8131 19:22:44.508441 [TxChooseVref] Worse bit 3, Min win 25, Win sum 422, Final Vref 28
8132 19:22:44.508530
8133 19:22:44.512025 Final TX Range 0 Vref 28
8134 19:22:44.512107
8135 19:22:44.512172 ==
8136 19:22:44.515113 Dram Type= 6, Freq= 0, CH_0, rank 1
8137 19:22:44.518691 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8138 19:22:44.518773 ==
8139 19:22:44.518838
8140 19:22:44.518899
8141 19:22:44.521753 TX Vref Scan disable
8142 19:22:44.528303 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8143 19:22:44.528386 == TX Byte 0 ==
8144 19:22:44.531723 u2DelayCellOfst[0]=10 cells (3 PI)
8145 19:22:44.535187 u2DelayCellOfst[1]=14 cells (4 PI)
8146 19:22:44.538305 u2DelayCellOfst[2]=7 cells (2 PI)
8147 19:22:44.541735 u2DelayCellOfst[3]=10 cells (3 PI)
8148 19:22:44.544828 u2DelayCellOfst[4]=7 cells (2 PI)
8149 19:22:44.548244 u2DelayCellOfst[5]=0 cells (0 PI)
8150 19:22:44.551301 u2DelayCellOfst[6]=14 cells (4 PI)
8151 19:22:44.554950 u2DelayCellOfst[7]=14 cells (4 PI)
8152 19:22:44.558078 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8153 19:22:44.561073 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8154 19:22:44.565127 == TX Byte 1 ==
8155 19:22:44.568070 u2DelayCellOfst[8]=0 cells (0 PI)
8156 19:22:44.571433 u2DelayCellOfst[9]=0 cells (0 PI)
8157 19:22:44.574675 u2DelayCellOfst[10]=3 cells (1 PI)
8158 19:22:44.577475 u2DelayCellOfst[11]=3 cells (1 PI)
8159 19:22:44.581040 u2DelayCellOfst[12]=10 cells (3 PI)
8160 19:22:44.581121 u2DelayCellOfst[13]=10 cells (3 PI)
8161 19:22:44.584046 u2DelayCellOfst[14]=17 cells (5 PI)
8162 19:22:44.587375 u2DelayCellOfst[15]=10 cells (3 PI)
8163 19:22:44.594045 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8164 19:22:44.597611 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8165 19:22:44.597692 DramC Write-DBI on
8166 19:22:44.601160 ==
8167 19:22:44.604137 Dram Type= 6, Freq= 0, CH_0, rank 1
8168 19:22:44.607245 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8169 19:22:44.607326 ==
8170 19:22:44.607390
8171 19:22:44.607450
8172 19:22:44.610862 TX Vref Scan disable
8173 19:22:44.610943 == TX Byte 0 ==
8174 19:22:44.617279 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8175 19:22:44.617360 == TX Byte 1 ==
8176 19:22:44.620829 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8177 19:22:44.623837 DramC Write-DBI off
8178 19:22:44.623959
8179 19:22:44.624055 [DATLAT]
8180 19:22:44.626899 Freq=1600, CH0 RK1
8181 19:22:44.626979
8182 19:22:44.627049 DATLAT Default: 0xf
8183 19:22:44.630549 0, 0xFFFF, sum = 0
8184 19:22:44.630631 1, 0xFFFF, sum = 0
8185 19:22:44.633487 2, 0xFFFF, sum = 0
8186 19:22:44.637155 3, 0xFFFF, sum = 0
8187 19:22:44.637235 4, 0xFFFF, sum = 0
8188 19:22:44.640193 5, 0xFFFF, sum = 0
8189 19:22:44.640265 6, 0xFFFF, sum = 0
8190 19:22:44.643532 7, 0xFFFF, sum = 0
8191 19:22:44.643604 8, 0xFFFF, sum = 0
8192 19:22:44.646969 9, 0xFFFF, sum = 0
8193 19:22:44.647039 10, 0xFFFF, sum = 0
8194 19:22:44.650294 11, 0xFFFF, sum = 0
8195 19:22:44.650368 12, 0xFFFF, sum = 0
8196 19:22:44.653544 13, 0xFFFF, sum = 0
8197 19:22:44.653626 14, 0x0, sum = 1
8198 19:22:44.656903 15, 0x0, sum = 2
8199 19:22:44.656988 16, 0x0, sum = 3
8200 19:22:44.660189 17, 0x0, sum = 4
8201 19:22:44.660274 best_step = 15
8202 19:22:44.660337
8203 19:22:44.660401 ==
8204 19:22:44.663183 Dram Type= 6, Freq= 0, CH_0, rank 1
8205 19:22:44.669751 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8206 19:22:44.669833 ==
8207 19:22:44.669897 RX Vref Scan: 0
8208 19:22:44.669957
8209 19:22:44.673415 RX Vref 0 -> 0, step: 1
8210 19:22:44.673496
8211 19:22:44.676947 RX Delay 19 -> 252, step: 4
8212 19:22:44.679727 iDelay=187, Bit 0, Center 126 (75 ~ 178) 104
8213 19:22:44.682977 iDelay=187, Bit 1, Center 130 (79 ~ 182) 104
8214 19:22:44.686227 iDelay=187, Bit 2, Center 124 (75 ~ 174) 100
8215 19:22:44.693043 iDelay=187, Bit 3, Center 126 (75 ~ 178) 104
8216 19:22:44.696485 iDelay=187, Bit 4, Center 132 (83 ~ 182) 100
8217 19:22:44.699728 iDelay=187, Bit 5, Center 118 (63 ~ 174) 112
8218 19:22:44.702991 iDelay=187, Bit 6, Center 136 (87 ~ 186) 100
8219 19:22:44.705911 iDelay=187, Bit 7, Center 134 (83 ~ 186) 104
8220 19:22:44.712571 iDelay=187, Bit 8, Center 114 (63 ~ 166) 104
8221 19:22:44.716153 iDelay=187, Bit 9, Center 110 (59 ~ 162) 104
8222 19:22:44.719114 iDelay=187, Bit 10, Center 126 (71 ~ 182) 112
8223 19:22:44.722649 iDelay=187, Bit 11, Center 118 (67 ~ 170) 104
8224 19:22:44.729276 iDelay=187, Bit 12, Center 128 (75 ~ 182) 108
8225 19:22:44.732247 iDelay=187, Bit 13, Center 130 (79 ~ 182) 104
8226 19:22:44.735996 iDelay=187, Bit 14, Center 134 (83 ~ 186) 104
8227 19:22:44.738972 iDelay=187, Bit 15, Center 130 (75 ~ 186) 112
8228 19:22:44.739052 ==
8229 19:22:44.742066 Dram Type= 6, Freq= 0, CH_0, rank 1
8230 19:22:44.749106 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8231 19:22:44.749187 ==
8232 19:22:44.749252 DQS Delay:
8233 19:22:44.752251 DQS0 = 0, DQS1 = 0
8234 19:22:44.752331 DQM Delay:
8235 19:22:44.752395 DQM0 = 128, DQM1 = 123
8236 19:22:44.755567 DQ Delay:
8237 19:22:44.758642 DQ0 =126, DQ1 =130, DQ2 =124, DQ3 =126
8238 19:22:44.762105 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =134
8239 19:22:44.764981 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =118
8240 19:22:44.768823 DQ12 =128, DQ13 =130, DQ14 =134, DQ15 =130
8241 19:22:44.768931
8242 19:22:44.768998
8243 19:22:44.769059
8244 19:22:44.771806 [DramC_TX_OE_Calibration] TA2
8245 19:22:44.775480 Original DQ_B0 (3 6) =30, OEN = 27
8246 19:22:44.778285 Original DQ_B1 (3 6) =30, OEN = 27
8247 19:22:44.781722 24, 0x0, End_B0=24 End_B1=24
8248 19:22:44.785264 25, 0x0, End_B0=25 End_B1=25
8249 19:22:44.785347 26, 0x0, End_B0=26 End_B1=26
8250 19:22:44.788332 27, 0x0, End_B0=27 End_B1=27
8251 19:22:44.792054 28, 0x0, End_B0=28 End_B1=28
8252 19:22:44.795014 29, 0x0, End_B0=29 End_B1=29
8253 19:22:44.795097 30, 0x0, End_B0=30 End_B1=30
8254 19:22:44.798414 31, 0x4141, End_B0=30 End_B1=30
8255 19:22:44.801316 Byte0 end_step=30 best_step=27
8256 19:22:44.804623 Byte1 end_step=30 best_step=27
8257 19:22:44.808235 Byte0 TX OE(2T, 0.5T) = (3, 3)
8258 19:22:44.811278 Byte1 TX OE(2T, 0.5T) = (3, 3)
8259 19:22:44.811359
8260 19:22:44.811423
8261 19:22:44.818305 [DQSOSCAuto] RK1, (LSB)MR18= 0x1412, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 399 ps
8262 19:22:44.821742 CH0 RK1: MR19=303, MR18=1412
8263 19:22:44.828070 CH0_RK1: MR19=0x303, MR18=0x1412, DQSOSC=399, MR23=63, INC=23, DEC=15
8264 19:22:44.831057 [RxdqsGatingPostProcess] freq 1600
8265 19:22:44.837673 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8266 19:22:44.837755 best DQS0 dly(2T, 0.5T) = (1, 1)
8267 19:22:44.841293 best DQS1 dly(2T, 0.5T) = (1, 1)
8268 19:22:44.844424 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8269 19:22:44.847501 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8270 19:22:44.851058 best DQS0 dly(2T, 0.5T) = (1, 1)
8271 19:22:44.854025 best DQS1 dly(2T, 0.5T) = (1, 1)
8272 19:22:44.857622 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8273 19:22:44.860560 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8274 19:22:44.864152 Pre-setting of DQS Precalculation
8275 19:22:44.867260 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8276 19:22:44.870756 ==
8277 19:22:44.870837 Dram Type= 6, Freq= 0, CH_1, rank 0
8278 19:22:44.877346 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8279 19:22:44.877451 ==
8280 19:22:44.880517 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8281 19:22:44.886727 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8282 19:22:44.890334 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8283 19:22:44.897286 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8284 19:22:44.905313 [CA 0] Center 42 (12~72) winsize 61
8285 19:22:44.908168 [CA 1] Center 42 (12~72) winsize 61
8286 19:22:44.911613 [CA 2] Center 38 (9~68) winsize 60
8287 19:22:44.915247 [CA 3] Center 37 (8~66) winsize 59
8288 19:22:44.918154 [CA 4] Center 38 (8~68) winsize 61
8289 19:22:44.921552 [CA 5] Center 36 (7~66) winsize 60
8290 19:22:44.921633
8291 19:22:44.924772 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8292 19:22:44.924854
8293 19:22:44.931543 [CATrainingPosCal] consider 1 rank data
8294 19:22:44.931624 u2DelayCellTimex100 = 275/100 ps
8295 19:22:44.938464 CA0 delay=42 (12~72),Diff = 6 PI (21 cell)
8296 19:22:44.941147 CA1 delay=42 (12~72),Diff = 6 PI (21 cell)
8297 19:22:44.944804 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
8298 19:22:44.947829 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8299 19:22:44.951483 CA4 delay=38 (8~68),Diff = 2 PI (7 cell)
8300 19:22:44.954452 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8301 19:22:44.954551
8302 19:22:44.957970 CA PerBit enable=1, Macro0, CA PI delay=36
8303 19:22:44.958063
8304 19:22:44.960869 [CBTSetCACLKResult] CA Dly = 36
8305 19:22:44.964535 CS Dly: 7 (0~38)
8306 19:22:44.967521 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8307 19:22:44.971222 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8308 19:22:44.971310 ==
8309 19:22:44.974092 Dram Type= 6, Freq= 0, CH_1, rank 1
8310 19:22:44.980599 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8311 19:22:44.980673 ==
8312 19:22:44.984016 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8313 19:22:44.990565 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8314 19:22:44.994156 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8315 19:22:45.000790 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8316 19:22:45.008054 [CA 0] Center 42 (12~72) winsize 61
8317 19:22:45.011583 [CA 1] Center 43 (14~72) winsize 59
8318 19:22:45.015116 [CA 2] Center 37 (8~67) winsize 60
8319 19:22:45.018087 [CA 3] Center 37 (7~67) winsize 61
8320 19:22:45.021147 [CA 4] Center 37 (7~67) winsize 61
8321 19:22:45.024776 [CA 5] Center 37 (7~67) winsize 61
8322 19:22:45.024845
8323 19:22:45.027800 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8324 19:22:45.027917
8325 19:22:45.034908 [CATrainingPosCal] consider 2 rank data
8326 19:22:45.034991 u2DelayCellTimex100 = 275/100 ps
8327 19:22:45.041039 CA0 delay=42 (12~72),Diff = 6 PI (21 cell)
8328 19:22:45.044676 CA1 delay=43 (14~72),Diff = 7 PI (24 cell)
8329 19:22:45.048036 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8330 19:22:45.051650 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8331 19:22:45.054357 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8332 19:22:45.057957 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8333 19:22:45.058038
8334 19:22:45.061314 CA PerBit enable=1, Macro0, CA PI delay=36
8335 19:22:45.061394
8336 19:22:45.064319 [CBTSetCACLKResult] CA Dly = 36
8337 19:22:45.068096 CS Dly: 9 (0~42)
8338 19:22:45.070976 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8339 19:22:45.074018 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8340 19:22:45.074099
8341 19:22:45.077393 ----->DramcWriteLeveling(PI) begin...
8342 19:22:45.077537 ==
8343 19:22:45.080989 Dram Type= 6, Freq= 0, CH_1, rank 0
8344 19:22:45.087177 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8345 19:22:45.087259 ==
8346 19:22:45.090679 Write leveling (Byte 0): 23 => 23
8347 19:22:45.094154 Write leveling (Byte 1): 26 => 26
8348 19:22:45.094234 DramcWriteLeveling(PI) end<-----
8349 19:22:45.096978
8350 19:22:45.097057 ==
8351 19:22:45.100213 Dram Type= 6, Freq= 0, CH_1, rank 0
8352 19:22:45.103798 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8353 19:22:45.103880 ==
8354 19:22:45.107261 [Gating] SW mode calibration
8355 19:22:45.114041 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8356 19:22:45.116972 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8357 19:22:45.123659 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8358 19:22:45.126768 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8359 19:22:45.130244 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8360 19:22:45.136674 1 4 12 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
8361 19:22:45.140209 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8362 19:22:45.143452 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8363 19:22:45.149979 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8364 19:22:45.153219 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8365 19:22:45.156545 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8366 19:22:45.163037 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8367 19:22:45.166459 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8368 19:22:45.172930 1 5 12 | B1->B0 | 3232 2929 | 1 0 | (1 0) (1 0)
8369 19:22:45.175834 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8370 19:22:45.179581 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8371 19:22:45.186105 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8372 19:22:45.189125 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8373 19:22:45.192817 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8374 19:22:45.199410 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8375 19:22:45.202283 1 6 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8376 19:22:45.205672 1 6 12 | B1->B0 | 3b3b 4646 | 1 0 | (0 0) (0 0)
8377 19:22:45.212512 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8378 19:22:45.215630 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8379 19:22:45.218635 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8380 19:22:45.225229 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8381 19:22:45.228811 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8382 19:22:45.231769 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8383 19:22:45.238386 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8384 19:22:45.242053 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8385 19:22:45.245285 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8386 19:22:45.252067 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8387 19:22:45.255062 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8388 19:22:45.258039 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8389 19:22:45.264632 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8390 19:22:45.268030 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8391 19:22:45.271266 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8392 19:22:45.277796 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 19:22:45.281689 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 19:22:45.284670 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 19:22:45.291381 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 19:22:45.294417 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 19:22:45.298090 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 19:22:45.304221 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 19:22:45.307830 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 19:22:45.310814 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8401 19:22:45.317619 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8402 19:22:45.317702 Total UI for P1: 0, mck2ui 16
8403 19:22:45.324115 best dqsien dly found for B0: ( 1, 9, 12)
8404 19:22:45.327620 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8405 19:22:45.330590 Total UI for P1: 0, mck2ui 16
8406 19:22:45.334187 best dqsien dly found for B1: ( 1, 9, 14)
8407 19:22:45.337295 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8408 19:22:45.340962 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8409 19:22:45.341036
8410 19:22:45.344026 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8411 19:22:45.347121 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8412 19:22:45.350761 [Gating] SW calibration Done
8413 19:22:45.350832 ==
8414 19:22:45.354141 Dram Type= 6, Freq= 0, CH_1, rank 0
8415 19:22:45.360600 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8416 19:22:45.360681 ==
8417 19:22:45.360744 RX Vref Scan: 0
8418 19:22:45.360804
8419 19:22:45.363690 RX Vref 0 -> 0, step: 1
8420 19:22:45.363770
8421 19:22:45.367197 RX Delay 0 -> 252, step: 8
8422 19:22:45.370290 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8423 19:22:45.374020 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8424 19:22:45.376658 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8425 19:22:45.380147 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8426 19:22:45.386908 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8427 19:22:45.390244 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8428 19:22:45.393597 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8429 19:22:45.396755 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8430 19:22:45.400061 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8431 19:22:45.406753 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8432 19:22:45.409872 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8433 19:22:45.412974 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8434 19:22:45.416699 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8435 19:22:45.423074 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8436 19:22:45.426260 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8437 19:22:45.429364 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8438 19:22:45.429445 ==
8439 19:22:45.433182 Dram Type= 6, Freq= 0, CH_1, rank 0
8440 19:22:45.436122 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8441 19:22:45.436204 ==
8442 19:22:45.439675 DQS Delay:
8443 19:22:45.439762 DQS0 = 0, DQS1 = 0
8444 19:22:45.442746 DQM Delay:
8445 19:22:45.442825 DQM0 = 134, DQM1 = 129
8446 19:22:45.445750 DQ Delay:
8447 19:22:45.449374 DQ0 =139, DQ1 =127, DQ2 =123, DQ3 =135
8448 19:22:45.452374 DQ4 =131, DQ5 =143, DQ6 =147, DQ7 =127
8449 19:22:45.455985 DQ8 =111, DQ9 =119, DQ10 =127, DQ11 =123
8450 19:22:45.459314 DQ12 =139, DQ13 =143, DQ14 =135, DQ15 =135
8451 19:22:45.459394
8452 19:22:45.459460
8453 19:22:45.459520 ==
8454 19:22:45.462466 Dram Type= 6, Freq= 0, CH_1, rank 0
8455 19:22:45.465602 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8456 19:22:45.465682 ==
8457 19:22:45.465746
8458 19:22:45.468744
8459 19:22:45.468824 TX Vref Scan disable
8460 19:22:45.472341 == TX Byte 0 ==
8461 19:22:45.475371 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8462 19:22:45.478757 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8463 19:22:45.482106 == TX Byte 1 ==
8464 19:22:45.485204 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8465 19:22:45.488519 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8466 19:22:45.488600 ==
8467 19:22:45.492180 Dram Type= 6, Freq= 0, CH_1, rank 0
8468 19:22:45.498480 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8469 19:22:45.498561 ==
8470 19:22:45.510727
8471 19:22:45.513601 TX Vref early break, caculate TX vref
8472 19:22:45.517259 TX Vref=16, minBit 8, minWin=21, winSum=369
8473 19:22:45.520468 TX Vref=18, minBit 11, minWin=22, winSum=381
8474 19:22:45.523455 TX Vref=20, minBit 6, minWin=23, winSum=389
8475 19:22:45.527031 TX Vref=22, minBit 9, minWin=23, winSum=397
8476 19:22:45.530462 TX Vref=24, minBit 6, minWin=24, winSum=408
8477 19:22:45.536668 TX Vref=26, minBit 8, minWin=25, winSum=418
8478 19:22:45.539951 TX Vref=28, minBit 0, minWin=26, winSum=420
8479 19:22:45.543512 TX Vref=30, minBit 0, minWin=24, winSum=410
8480 19:22:45.546703 TX Vref=32, minBit 1, minWin=24, winSum=404
8481 19:22:45.549708 TX Vref=34, minBit 1, minWin=23, winSum=391
8482 19:22:45.556430 [TxChooseVref] Worse bit 0, Min win 26, Win sum 420, Final Vref 28
8483 19:22:45.556516
8484 19:22:45.560154 Final TX Range 0 Vref 28
8485 19:22:45.560249
8486 19:22:45.560330 ==
8487 19:22:45.563187 Dram Type= 6, Freq= 0, CH_1, rank 0
8488 19:22:45.566228 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8489 19:22:45.566310 ==
8490 19:22:45.566375
8491 19:22:45.566435
8492 19:22:45.569719 TX Vref Scan disable
8493 19:22:45.576482 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8494 19:22:45.576564 == TX Byte 0 ==
8495 19:22:45.579486 u2DelayCellOfst[0]=14 cells (4 PI)
8496 19:22:45.582558 u2DelayCellOfst[1]=7 cells (2 PI)
8497 19:22:45.586145 u2DelayCellOfst[2]=0 cells (0 PI)
8498 19:22:45.589192 u2DelayCellOfst[3]=3 cells (1 PI)
8499 19:22:45.592617 u2DelayCellOfst[4]=7 cells (2 PI)
8500 19:22:45.595763 u2DelayCellOfst[5]=14 cells (4 PI)
8501 19:22:45.599104 u2DelayCellOfst[6]=14 cells (4 PI)
8502 19:22:45.602594 u2DelayCellOfst[7]=3 cells (1 PI)
8503 19:22:45.605720 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8504 19:22:45.609306 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8505 19:22:45.613046 == TX Byte 1 ==
8506 19:22:45.615536 u2DelayCellOfst[8]=0 cells (0 PI)
8507 19:22:45.619077 u2DelayCellOfst[9]=3 cells (1 PI)
8508 19:22:45.622189 u2DelayCellOfst[10]=10 cells (3 PI)
8509 19:22:45.625193 u2DelayCellOfst[11]=7 cells (2 PI)
8510 19:22:45.625275 u2DelayCellOfst[12]=14 cells (4 PI)
8511 19:22:45.628835 u2DelayCellOfst[13]=14 cells (4 PI)
8512 19:22:45.631977 u2DelayCellOfst[14]=17 cells (5 PI)
8513 19:22:45.635438 u2DelayCellOfst[15]=17 cells (5 PI)
8514 19:22:45.641974 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8515 19:22:45.644904 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8516 19:22:45.648365 DramC Write-DBI on
8517 19:22:45.648440 ==
8518 19:22:45.651627 Dram Type= 6, Freq= 0, CH_1, rank 0
8519 19:22:45.654859 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8520 19:22:45.654931 ==
8521 19:22:45.654993
8522 19:22:45.655052
8523 19:22:45.658471 TX Vref Scan disable
8524 19:22:45.658552 == TX Byte 0 ==
8525 19:22:45.664553 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8526 19:22:45.664634 == TX Byte 1 ==
8527 19:22:45.668170 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8528 19:22:45.671195 DramC Write-DBI off
8529 19:22:45.671276
8530 19:22:45.671341 [DATLAT]
8531 19:22:45.674621 Freq=1600, CH1 RK0
8532 19:22:45.674702
8533 19:22:45.674767 DATLAT Default: 0xf
8534 19:22:45.677710 0, 0xFFFF, sum = 0
8535 19:22:45.681323 1, 0xFFFF, sum = 0
8536 19:22:45.681406 2, 0xFFFF, sum = 0
8537 19:22:45.684729 3, 0xFFFF, sum = 0
8538 19:22:45.684812 4, 0xFFFF, sum = 0
8539 19:22:45.687539 5, 0xFFFF, sum = 0
8540 19:22:45.687621 6, 0xFFFF, sum = 0
8541 19:22:45.691166 7, 0xFFFF, sum = 0
8542 19:22:45.691249 8, 0xFFFF, sum = 0
8543 19:22:45.694175 9, 0xFFFF, sum = 0
8544 19:22:45.694258 10, 0xFFFF, sum = 0
8545 19:22:45.697875 11, 0xFFFF, sum = 0
8546 19:22:45.697958 12, 0xFFFF, sum = 0
8547 19:22:45.700888 13, 0xFFFF, sum = 0
8548 19:22:45.700971 14, 0x0, sum = 1
8549 19:22:45.704154 15, 0x0, sum = 2
8550 19:22:45.704237 16, 0x0, sum = 3
8551 19:22:45.707811 17, 0x0, sum = 4
8552 19:22:45.707903 best_step = 15
8553 19:22:45.707983
8554 19:22:45.708044 ==
8555 19:22:45.710986 Dram Type= 6, Freq= 0, CH_1, rank 0
8556 19:22:45.717548 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8557 19:22:45.717629 ==
8558 19:22:45.717694 RX Vref Scan: 1
8559 19:22:45.717753
8560 19:22:45.721095 Set Vref Range= 24 -> 127
8561 19:22:45.721185
8562 19:22:45.724020 RX Vref 24 -> 127, step: 1
8563 19:22:45.724096
8564 19:22:45.724159 RX Delay 11 -> 252, step: 4
8565 19:22:45.724219
8566 19:22:45.727512 Set Vref, RX VrefLevel [Byte0]: 24
8567 19:22:45.730984 [Byte1]: 24
8568 19:22:45.734610
8569 19:22:45.734688 Set Vref, RX VrefLevel [Byte0]: 25
8570 19:22:45.738184 [Byte1]: 25
8571 19:22:45.742374
8572 19:22:45.742454 Set Vref, RX VrefLevel [Byte0]: 26
8573 19:22:45.745983 [Byte1]: 26
8574 19:22:45.749880
8575 19:22:45.749960 Set Vref, RX VrefLevel [Byte0]: 27
8576 19:22:45.753553 [Byte1]: 27
8577 19:22:45.757610
8578 19:22:45.757691 Set Vref, RX VrefLevel [Byte0]: 28
8579 19:22:45.760893 [Byte1]: 28
8580 19:22:45.765282
8581 19:22:45.765362 Set Vref, RX VrefLevel [Byte0]: 29
8582 19:22:45.768599 [Byte1]: 29
8583 19:22:45.772857
8584 19:22:45.772938 Set Vref, RX VrefLevel [Byte0]: 30
8585 19:22:45.776526 [Byte1]: 30
8586 19:22:45.780601
8587 19:22:45.780680 Set Vref, RX VrefLevel [Byte0]: 31
8588 19:22:45.783565 [Byte1]: 31
8589 19:22:45.787866
8590 19:22:45.787988 Set Vref, RX VrefLevel [Byte0]: 32
8591 19:22:45.791454 [Byte1]: 32
8592 19:22:45.795808
8593 19:22:45.795913 Set Vref, RX VrefLevel [Byte0]: 33
8594 19:22:45.798814 [Byte1]: 33
8595 19:22:45.803009
8596 19:22:45.803096 Set Vref, RX VrefLevel [Byte0]: 34
8597 19:22:45.806741 [Byte1]: 34
8598 19:22:45.811034
8599 19:22:45.811113 Set Vref, RX VrefLevel [Byte0]: 35
8600 19:22:45.813988 [Byte1]: 35
8601 19:22:45.818647
8602 19:22:45.818717 Set Vref, RX VrefLevel [Byte0]: 36
8603 19:22:45.821863 [Byte1]: 36
8604 19:22:45.826079
8605 19:22:45.826152 Set Vref, RX VrefLevel [Byte0]: 37
8606 19:22:45.829205 [Byte1]: 37
8607 19:22:45.833738
8608 19:22:45.833819 Set Vref, RX VrefLevel [Byte0]: 38
8609 19:22:45.836963 [Byte1]: 38
8610 19:22:45.841613
8611 19:22:45.841693 Set Vref, RX VrefLevel [Byte0]: 39
8612 19:22:45.844592 [Byte1]: 39
8613 19:22:45.849370
8614 19:22:45.849451 Set Vref, RX VrefLevel [Byte0]: 40
8615 19:22:45.852347 [Byte1]: 40
8616 19:22:45.856542
8617 19:22:45.856627 Set Vref, RX VrefLevel [Byte0]: 41
8618 19:22:45.860152 [Byte1]: 41
8619 19:22:45.864221
8620 19:22:45.864302 Set Vref, RX VrefLevel [Byte0]: 42
8621 19:22:45.867670 [Byte1]: 42
8622 19:22:45.871670
8623 19:22:45.871753 Set Vref, RX VrefLevel [Byte0]: 43
8624 19:22:45.875217 [Byte1]: 43
8625 19:22:45.879314
8626 19:22:45.879394 Set Vref, RX VrefLevel [Byte0]: 44
8627 19:22:45.882722 [Byte1]: 44
8628 19:22:45.887108
8629 19:22:45.887189 Set Vref, RX VrefLevel [Byte0]: 45
8630 19:22:45.890160 [Byte1]: 45
8631 19:22:45.894381
8632 19:22:45.894461 Set Vref, RX VrefLevel [Byte0]: 46
8633 19:22:45.898060 [Byte1]: 46
8634 19:22:45.902243
8635 19:22:45.902323 Set Vref, RX VrefLevel [Byte0]: 47
8636 19:22:45.905877 [Byte1]: 47
8637 19:22:45.910113
8638 19:22:45.910193 Set Vref, RX VrefLevel [Byte0]: 48
8639 19:22:45.913162 [Byte1]: 48
8640 19:22:45.917344
8641 19:22:45.917418 Set Vref, RX VrefLevel [Byte0]: 49
8642 19:22:45.920970 [Byte1]: 49
8643 19:22:45.925094
8644 19:22:45.925174 Set Vref, RX VrefLevel [Byte0]: 50
8645 19:22:45.928722 [Byte1]: 50
8646 19:22:45.932586
8647 19:22:45.932665 Set Vref, RX VrefLevel [Byte0]: 51
8648 19:22:45.935726 [Byte1]: 51
8649 19:22:45.940021
8650 19:22:45.943233 Set Vref, RX VrefLevel [Byte0]: 52
8651 19:22:45.947078 [Byte1]: 52
8652 19:22:45.947158
8653 19:22:45.950308 Set Vref, RX VrefLevel [Byte0]: 53
8654 19:22:45.953462 [Byte1]: 53
8655 19:22:45.953542
8656 19:22:45.956663 Set Vref, RX VrefLevel [Byte0]: 54
8657 19:22:45.960033 [Byte1]: 54
8658 19:22:45.960108
8659 19:22:45.963602 Set Vref, RX VrefLevel [Byte0]: 55
8660 19:22:45.966586 [Byte1]: 55
8661 19:22:45.970731
8662 19:22:45.970803 Set Vref, RX VrefLevel [Byte0]: 56
8663 19:22:45.974245 [Byte1]: 56
8664 19:22:45.978313
8665 19:22:45.978386 Set Vref, RX VrefLevel [Byte0]: 57
8666 19:22:45.981569 [Byte1]: 57
8667 19:22:45.985921
8668 19:22:45.986001 Set Vref, RX VrefLevel [Byte0]: 58
8669 19:22:45.989325 [Byte1]: 58
8670 19:22:45.993383
8671 19:22:45.993463 Set Vref, RX VrefLevel [Byte0]: 59
8672 19:22:45.997081 [Byte1]: 59
8673 19:22:46.001248
8674 19:22:46.001329 Set Vref, RX VrefLevel [Byte0]: 60
8675 19:22:46.004394 [Byte1]: 60
8676 19:22:46.009170
8677 19:22:46.009251 Set Vref, RX VrefLevel [Byte0]: 61
8678 19:22:46.012223 [Byte1]: 61
8679 19:22:46.016492
8680 19:22:46.016574 Set Vref, RX VrefLevel [Byte0]: 62
8681 19:22:46.019547 [Byte1]: 62
8682 19:22:46.023858
8683 19:22:46.023967 Set Vref, RX VrefLevel [Byte0]: 63
8684 19:22:46.027203 [Byte1]: 63
8685 19:22:46.031475
8686 19:22:46.031554 Set Vref, RX VrefLevel [Byte0]: 64
8687 19:22:46.035026 [Byte1]: 64
8688 19:22:46.039209
8689 19:22:46.039286 Set Vref, RX VrefLevel [Byte0]: 65
8690 19:22:46.042797 [Byte1]: 65
8691 19:22:46.046779
8692 19:22:46.046884 Set Vref, RX VrefLevel [Byte0]: 66
8693 19:22:46.050043 [Byte1]: 66
8694 19:22:46.054701
8695 19:22:46.054809 Set Vref, RX VrefLevel [Byte0]: 67
8696 19:22:46.058006 [Byte1]: 67
8697 19:22:46.062206
8698 19:22:46.062331 Set Vref, RX VrefLevel [Byte0]: 68
8699 19:22:46.065625 [Byte1]: 68
8700 19:22:46.069953
8701 19:22:46.070028 Set Vref, RX VrefLevel [Byte0]: 69
8702 19:22:46.072938 [Byte1]: 69
8703 19:22:46.077554
8704 19:22:46.077635 Set Vref, RX VrefLevel [Byte0]: 70
8705 19:22:46.080466 [Byte1]: 70
8706 19:22:46.085268
8707 19:22:46.085348 Set Vref, RX VrefLevel [Byte0]: 71
8708 19:22:46.088089 [Byte1]: 71
8709 19:22:46.092752
8710 19:22:46.092832 Set Vref, RX VrefLevel [Byte0]: 72
8711 19:22:46.096078 [Byte1]: 72
8712 19:22:46.100251
8713 19:22:46.100331 Final RX Vref Byte 0 = 57 to rank0
8714 19:22:46.103214 Final RX Vref Byte 1 = 61 to rank0
8715 19:22:46.106849 Final RX Vref Byte 0 = 57 to rank1
8716 19:22:46.110037 Final RX Vref Byte 1 = 61 to rank1==
8717 19:22:46.113296 Dram Type= 6, Freq= 0, CH_1, rank 0
8718 19:22:46.119771 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8719 19:22:46.119846 ==
8720 19:22:46.119950 DQS Delay:
8721 19:22:46.123465 DQS0 = 0, DQS1 = 0
8722 19:22:46.123534 DQM Delay:
8723 19:22:46.123598 DQM0 = 132, DQM1 = 128
8724 19:22:46.126598 DQ Delay:
8725 19:22:46.129775 DQ0 =140, DQ1 =128, DQ2 =118, DQ3 =132
8726 19:22:46.133225 DQ4 =128, DQ5 =142, DQ6 =144, DQ7 =126
8727 19:22:46.136253 DQ8 =114, DQ9 =116, DQ10 =128, DQ11 =120
8728 19:22:46.139874 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =138
8729 19:22:46.139993
8730 19:22:46.140058
8731 19:22:46.140117
8732 19:22:46.142884 [DramC_TX_OE_Calibration] TA2
8733 19:22:46.146428 Original DQ_B0 (3 6) =30, OEN = 27
8734 19:22:46.149483 Original DQ_B1 (3 6) =30, OEN = 27
8735 19:22:46.153096 24, 0x0, End_B0=24 End_B1=24
8736 19:22:46.156071 25, 0x0, End_B0=25 End_B1=25
8737 19:22:46.156152 26, 0x0, End_B0=26 End_B1=26
8738 19:22:46.159429 27, 0x0, End_B0=27 End_B1=27
8739 19:22:46.162341 28, 0x0, End_B0=28 End_B1=28
8740 19:22:46.166439 29, 0x0, End_B0=29 End_B1=29
8741 19:22:46.166524 30, 0x0, End_B0=30 End_B1=30
8742 19:22:46.169275 31, 0x4141, End_B0=30 End_B1=30
8743 19:22:46.172626 Byte0 end_step=30 best_step=27
8744 19:22:46.176037 Byte1 end_step=30 best_step=27
8745 19:22:46.179344 Byte0 TX OE(2T, 0.5T) = (3, 3)
8746 19:22:46.182163 Byte1 TX OE(2T, 0.5T) = (3, 3)
8747 19:22:46.182239
8748 19:22:46.182302
8749 19:22:46.189392 [DQSOSCAuto] RK0, (LSB)MR18= 0xc15, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 403 ps
8750 19:22:46.192406 CH1 RK0: MR19=303, MR18=C15
8751 19:22:46.199027 CH1_RK0: MR19=0x303, MR18=0xC15, DQSOSC=399, MR23=63, INC=23, DEC=15
8752 19:22:46.199112
8753 19:22:46.202375 ----->DramcWriteLeveling(PI) begin...
8754 19:22:46.202457 ==
8755 19:22:46.205358 Dram Type= 6, Freq= 0, CH_1, rank 1
8756 19:22:46.208944 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8757 19:22:46.209025 ==
8758 19:22:46.212039 Write leveling (Byte 0): 25 => 25
8759 19:22:46.215044 Write leveling (Byte 1): 26 => 26
8760 19:22:46.218701 DramcWriteLeveling(PI) end<-----
8761 19:22:46.218781
8762 19:22:46.218845 ==
8763 19:22:46.221555 Dram Type= 6, Freq= 0, CH_1, rank 1
8764 19:22:46.228456 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8765 19:22:46.228537 ==
8766 19:22:46.228602 [Gating] SW mode calibration
8767 19:22:46.238112 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8768 19:22:46.241825 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8769 19:22:46.244874 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8770 19:22:46.251421 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8771 19:22:46.254574 1 4 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8772 19:22:46.258136 1 4 12 | B1->B0 | 2928 3434 | 1 1 | (1 1) (1 1)
8773 19:22:46.264900 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8774 19:22:46.268075 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8775 19:22:46.271159 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8776 19:22:46.278067 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8777 19:22:46.280994 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8778 19:22:46.284304 1 5 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8779 19:22:46.291042 1 5 8 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
8780 19:22:46.294281 1 5 12 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
8781 19:22:46.298007 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8782 19:22:46.304432 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8783 19:22:46.307906 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8784 19:22:46.310797 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8785 19:22:46.317789 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8786 19:22:46.320847 1 6 4 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
8787 19:22:46.324158 1 6 8 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
8788 19:22:46.330702 1 6 12 | B1->B0 | 3535 4646 | 1 0 | (0 0) (0 0)
8789 19:22:46.333762 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8790 19:22:46.337305 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8791 19:22:46.344310 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8792 19:22:46.347342 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8793 19:22:46.350828 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8794 19:22:46.357334 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8795 19:22:46.360343 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8796 19:22:46.363872 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8797 19:22:46.370410 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8798 19:22:46.373583 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 19:22:46.376850 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 19:22:46.383510 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 19:22:46.387047 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 19:22:46.389840 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 19:22:46.396791 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 19:22:46.399641 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 19:22:46.403055 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 19:22:46.409543 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 19:22:46.413155 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 19:22:46.416651 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 19:22:46.423231 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 19:22:46.426292 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8811 19:22:46.429352 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8812 19:22:46.436074 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8813 19:22:46.439665 Total UI for P1: 0, mck2ui 16
8814 19:22:46.442720 best dqsien dly found for B0: ( 1, 9, 6)
8815 19:22:46.446297 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8816 19:22:46.449258 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8817 19:22:46.452292 Total UI for P1: 0, mck2ui 16
8818 19:22:46.455833 best dqsien dly found for B1: ( 1, 9, 14)
8819 19:22:46.459402 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8820 19:22:46.462384 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8821 19:22:46.465512
8822 19:22:46.469184 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8823 19:22:46.472302 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8824 19:22:46.475474 [Gating] SW calibration Done
8825 19:22:46.475556 ==
8826 19:22:46.479105 Dram Type= 6, Freq= 0, CH_1, rank 1
8827 19:22:46.482633 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8828 19:22:46.482716 ==
8829 19:22:46.485352 RX Vref Scan: 0
8830 19:22:46.485433
8831 19:22:46.485497 RX Vref 0 -> 0, step: 1
8832 19:22:46.485558
8833 19:22:46.488721 RX Delay 0 -> 252, step: 8
8834 19:22:46.492234 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8835 19:22:46.495387 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8836 19:22:46.501856 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8837 19:22:46.505337 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8838 19:22:46.508672 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8839 19:22:46.512093 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8840 19:22:46.518233 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8841 19:22:46.521575 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8842 19:22:46.524887 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8843 19:22:46.528399 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8844 19:22:46.531468 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8845 19:22:46.538193 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8846 19:22:46.541439 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8847 19:22:46.544476 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8848 19:22:46.548329 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8849 19:22:46.554772 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8850 19:22:46.554852 ==
8851 19:22:46.557766 Dram Type= 6, Freq= 0, CH_1, rank 1
8852 19:22:46.561273 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8853 19:22:46.561354 ==
8854 19:22:46.561418 DQS Delay:
8855 19:22:46.564395 DQS0 = 0, DQS1 = 0
8856 19:22:46.564476 DQM Delay:
8857 19:22:46.567521 DQM0 = 132, DQM1 = 129
8858 19:22:46.567602 DQ Delay:
8859 19:22:46.571153 DQ0 =135, DQ1 =131, DQ2 =119, DQ3 =127
8860 19:22:46.574204 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =135
8861 19:22:46.577818 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =123
8862 19:22:46.580809 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =135
8863 19:22:46.580889
8864 19:22:46.580954
8865 19:22:46.583985 ==
8866 19:22:46.587722 Dram Type= 6, Freq= 0, CH_1, rank 1
8867 19:22:46.590501 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8868 19:22:46.590582 ==
8869 19:22:46.590651
8870 19:22:46.590712
8871 19:22:46.593931 TX Vref Scan disable
8872 19:22:46.594013 == TX Byte 0 ==
8873 19:22:46.600489 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8874 19:22:46.604098 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8875 19:22:46.604178 == TX Byte 1 ==
8876 19:22:46.610566 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8877 19:22:46.613469 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8878 19:22:46.613544 ==
8879 19:22:46.616811 Dram Type= 6, Freq= 0, CH_1, rank 1
8880 19:22:46.620101 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8881 19:22:46.620174 ==
8882 19:22:46.634603
8883 19:22:46.638041 TX Vref early break, caculate TX vref
8884 19:22:46.641325 TX Vref=16, minBit 9, minWin=22, winSum=381
8885 19:22:46.644656 TX Vref=18, minBit 9, minWin=22, winSum=391
8886 19:22:46.647615 TX Vref=20, minBit 9, minWin=22, winSum=395
8887 19:22:46.651304 TX Vref=22, minBit 9, minWin=22, winSum=403
8888 19:22:46.654338 TX Vref=24, minBit 9, minWin=24, winSum=414
8889 19:22:46.660806 TX Vref=26, minBit 9, minWin=23, winSum=419
8890 19:22:46.664451 TX Vref=28, minBit 9, minWin=24, winSum=419
8891 19:22:46.667295 TX Vref=30, minBit 0, minWin=25, winSum=417
8892 19:22:46.670927 TX Vref=32, minBit 8, minWin=24, winSum=406
8893 19:22:46.674033 TX Vref=34, minBit 9, minWin=23, winSum=400
8894 19:22:46.680718 TX Vref=36, minBit 0, minWin=22, winSum=392
8895 19:22:46.683820 [TxChooseVref] Worse bit 0, Min win 25, Win sum 417, Final Vref 30
8896 19:22:46.683930
8897 19:22:46.687285 Final TX Range 0 Vref 30
8898 19:22:46.687364
8899 19:22:46.687445 ==
8900 19:22:46.690319 Dram Type= 6, Freq= 0, CH_1, rank 1
8901 19:22:46.693769 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8902 19:22:46.697281 ==
8903 19:22:46.697375
8904 19:22:46.697458
8905 19:22:46.697536 TX Vref Scan disable
8906 19:22:46.703973 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8907 19:22:46.704111 == TX Byte 0 ==
8908 19:22:46.706924 u2DelayCellOfst[0]=17 cells (5 PI)
8909 19:22:46.710549 u2DelayCellOfst[1]=14 cells (4 PI)
8910 19:22:46.713783 u2DelayCellOfst[2]=0 cells (0 PI)
8911 19:22:46.717347 u2DelayCellOfst[3]=7 cells (2 PI)
8912 19:22:46.720495 u2DelayCellOfst[4]=7 cells (2 PI)
8913 19:22:46.723392 u2DelayCellOfst[5]=17 cells (5 PI)
8914 19:22:46.727049 u2DelayCellOfst[6]=17 cells (5 PI)
8915 19:22:46.730222 u2DelayCellOfst[7]=3 cells (1 PI)
8916 19:22:46.733669 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8917 19:22:46.736620 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8918 19:22:46.739911 == TX Byte 1 ==
8919 19:22:46.743043 u2DelayCellOfst[8]=0 cells (0 PI)
8920 19:22:46.746671 u2DelayCellOfst[9]=3 cells (1 PI)
8921 19:22:46.749867 u2DelayCellOfst[10]=10 cells (3 PI)
8922 19:22:46.753192 u2DelayCellOfst[11]=7 cells (2 PI)
8923 19:22:46.756237 u2DelayCellOfst[12]=14 cells (4 PI)
8924 19:22:46.759739 u2DelayCellOfst[13]=14 cells (4 PI)
8925 19:22:46.762874 u2DelayCellOfst[14]=17 cells (5 PI)
8926 19:22:46.762948 u2DelayCellOfst[15]=17 cells (5 PI)
8927 19:22:46.770081 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8928 19:22:46.773124 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8929 19:22:46.776316 DramC Write-DBI on
8930 19:22:46.776438 ==
8931 19:22:46.779341 Dram Type= 6, Freq= 0, CH_1, rank 1
8932 19:22:46.783055 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8933 19:22:46.783127 ==
8934 19:22:46.783188
8935 19:22:46.783245
8936 19:22:46.786072 TX Vref Scan disable
8937 19:22:46.786152 == TX Byte 0 ==
8938 19:22:46.792755 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8939 19:22:46.792836 == TX Byte 1 ==
8940 19:22:46.796412 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8941 19:22:46.799265 DramC Write-DBI off
8942 19:22:46.799346
8943 19:22:46.799410 [DATLAT]
8944 19:22:46.802738 Freq=1600, CH1 RK1
8945 19:22:46.802818
8946 19:22:46.802883 DATLAT Default: 0xf
8947 19:22:46.805613 0, 0xFFFF, sum = 0
8948 19:22:46.809332 1, 0xFFFF, sum = 0
8949 19:22:46.809414 2, 0xFFFF, sum = 0
8950 19:22:46.812418 3, 0xFFFF, sum = 0
8951 19:22:46.812500 4, 0xFFFF, sum = 0
8952 19:22:46.815487 5, 0xFFFF, sum = 0
8953 19:22:46.815571 6, 0xFFFF, sum = 0
8954 19:22:46.819104 7, 0xFFFF, sum = 0
8955 19:22:46.819186 8, 0xFFFF, sum = 0
8956 19:22:46.822137 9, 0xFFFF, sum = 0
8957 19:22:46.822223 10, 0xFFFF, sum = 0
8958 19:22:46.825605 11, 0xFFFF, sum = 0
8959 19:22:46.825687 12, 0xFFFF, sum = 0
8960 19:22:46.828698 13, 0xFFFF, sum = 0
8961 19:22:46.828780 14, 0x0, sum = 1
8962 19:22:46.832363 15, 0x0, sum = 2
8963 19:22:46.832445 16, 0x0, sum = 3
8964 19:22:46.835700 17, 0x0, sum = 4
8965 19:22:46.835816 best_step = 15
8966 19:22:46.835944
8967 19:22:46.836032 ==
8968 19:22:46.838980 Dram Type= 6, Freq= 0, CH_1, rank 1
8969 19:22:46.845762 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8970 19:22:46.845846 ==
8971 19:22:46.845931 RX Vref Scan: 0
8972 19:22:46.846012
8973 19:22:46.848685 RX Vref 0 -> 0, step: 1
8974 19:22:46.848763
8975 19:22:46.852084 RX Delay 11 -> 252, step: 4
8976 19:22:46.855441 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
8977 19:22:46.858450 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8978 19:22:46.861819 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
8979 19:22:46.868655 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8980 19:22:46.871666 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
8981 19:22:46.875059 iDelay=195, Bit 5, Center 142 (91 ~ 194) 104
8982 19:22:46.878106 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8983 19:22:46.884759 iDelay=195, Bit 7, Center 128 (75 ~ 182) 108
8984 19:22:46.888286 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8985 19:22:46.891358 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8986 19:22:46.894983 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8987 19:22:46.898120 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8988 19:22:46.904595 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
8989 19:22:46.908099 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8990 19:22:46.911179 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8991 19:22:46.914780 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
8992 19:22:46.914860 ==
8993 19:22:46.917801 Dram Type= 6, Freq= 0, CH_1, rank 1
8994 19:22:46.924479 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8995 19:22:46.924555 ==
8996 19:22:46.924621 DQS Delay:
8997 19:22:46.927984 DQS0 = 0, DQS1 = 0
8998 19:22:46.928053 DQM Delay:
8999 19:22:46.928158 DQM0 = 131, DQM1 = 128
9000 19:22:46.931057 DQ Delay:
9001 19:22:46.934197 DQ0 =134, DQ1 =130, DQ2 =120, DQ3 =128
9002 19:22:46.937784 DQ4 =130, DQ5 =142, DQ6 =138, DQ7 =128
9003 19:22:46.940783 DQ8 =116, DQ9 =118, DQ10 =128, DQ11 =120
9004 19:22:46.944410 DQ12 =136, DQ13 =136, DQ14 =132, DQ15 =138
9005 19:22:46.944488
9006 19:22:46.944573
9007 19:22:46.944649
9008 19:22:46.947853 [DramC_TX_OE_Calibration] TA2
9009 19:22:46.951145 Original DQ_B0 (3 6) =30, OEN = 27
9010 19:22:46.954343 Original DQ_B1 (3 6) =30, OEN = 27
9011 19:22:46.957683 24, 0x0, End_B0=24 End_B1=24
9012 19:22:46.960749 25, 0x0, End_B0=25 End_B1=25
9013 19:22:46.960826 26, 0x0, End_B0=26 End_B1=26
9014 19:22:46.964211 27, 0x0, End_B0=27 End_B1=27
9015 19:22:46.967341 28, 0x0, End_B0=28 End_B1=28
9016 19:22:46.970388 29, 0x0, End_B0=29 End_B1=29
9017 19:22:46.970465 30, 0x0, End_B0=30 End_B1=30
9018 19:22:46.973737 31, 0x4141, End_B0=30 End_B1=30
9019 19:22:46.977160 Byte0 end_step=30 best_step=27
9020 19:22:46.980517 Byte1 end_step=30 best_step=27
9021 19:22:46.984087 Byte0 TX OE(2T, 0.5T) = (3, 3)
9022 19:22:46.987217 Byte1 TX OE(2T, 0.5T) = (3, 3)
9023 19:22:46.987295
9024 19:22:46.987364
9025 19:22:46.993607 [DQSOSCAuto] RK1, (LSB)MR18= 0x121f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 400 ps
9026 19:22:46.997171 CH1 RK1: MR19=303, MR18=121F
9027 19:22:47.003794 CH1_RK1: MR19=0x303, MR18=0x121F, DQSOSC=394, MR23=63, INC=23, DEC=15
9028 19:22:47.007365 [RxdqsGatingPostProcess] freq 1600
9029 19:22:47.010304 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9030 19:22:47.013902 best DQS0 dly(2T, 0.5T) = (1, 1)
9031 19:22:47.016842 best DQS1 dly(2T, 0.5T) = (1, 1)
9032 19:22:47.020406 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9033 19:22:47.023485 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9034 19:22:47.026619 best DQS0 dly(2T, 0.5T) = (1, 1)
9035 19:22:47.030144 best DQS1 dly(2T, 0.5T) = (1, 1)
9036 19:22:47.033199 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9037 19:22:47.036803 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9038 19:22:47.039999 Pre-setting of DQS Precalculation
9039 19:22:47.043546 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9040 19:22:47.053374 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9041 19:22:47.059656 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9042 19:22:47.059737
9043 19:22:47.059802
9044 19:22:47.062942 [Calibration Summary] 3200 Mbps
9045 19:22:47.063011 CH 0, Rank 0
9046 19:22:47.066319 SW Impedance : PASS
9047 19:22:47.066400 DUTY Scan : NO K
9048 19:22:47.069790 ZQ Calibration : PASS
9049 19:22:47.072798 Jitter Meter : NO K
9050 19:22:47.072879 CBT Training : PASS
9051 19:22:47.075991 Write leveling : PASS
9052 19:22:47.079635 RX DQS gating : PASS
9053 19:22:47.079716 RX DQ/DQS(RDDQC) : PASS
9054 19:22:47.082706 TX DQ/DQS : PASS
9055 19:22:47.086433 RX DATLAT : PASS
9056 19:22:47.086513 RX DQ/DQS(Engine): PASS
9057 19:22:47.089383 TX OE : PASS
9058 19:22:47.089464 All Pass.
9059 19:22:47.089543
9060 19:22:47.092839 CH 0, Rank 1
9061 19:22:47.092923 SW Impedance : PASS
9062 19:22:47.096053 DUTY Scan : NO K
9063 19:22:47.099440 ZQ Calibration : PASS
9064 19:22:47.099555 Jitter Meter : NO K
9065 19:22:47.102760 CBT Training : PASS
9066 19:22:47.105834 Write leveling : PASS
9067 19:22:47.105912 RX DQS gating : PASS
9068 19:22:47.109019 RX DQ/DQS(RDDQC) : PASS
9069 19:22:47.112292 TX DQ/DQS : PASS
9070 19:22:47.112372 RX DATLAT : PASS
9071 19:22:47.115666 RX DQ/DQS(Engine): PASS
9072 19:22:47.115769 TX OE : PASS
9073 19:22:47.119220 All Pass.
9074 19:22:47.119325
9075 19:22:47.119424 CH 1, Rank 0
9076 19:22:47.122370 SW Impedance : PASS
9077 19:22:47.125970 DUTY Scan : NO K
9078 19:22:47.126048 ZQ Calibration : PASS
9079 19:22:47.129039 Jitter Meter : NO K
9080 19:22:47.129115 CBT Training : PASS
9081 19:22:47.132127 Write leveling : PASS
9082 19:22:47.135653 RX DQS gating : PASS
9083 19:22:47.135758 RX DQ/DQS(RDDQC) : PASS
9084 19:22:47.139107 TX DQ/DQS : PASS
9085 19:22:47.142159 RX DATLAT : PASS
9086 19:22:47.142236 RX DQ/DQS(Engine): PASS
9087 19:22:47.145174 TX OE : PASS
9088 19:22:47.145253 All Pass.
9089 19:22:47.145334
9090 19:22:47.148727 CH 1, Rank 1
9091 19:22:47.148801 SW Impedance : PASS
9092 19:22:47.151834 DUTY Scan : NO K
9093 19:22:47.155013 ZQ Calibration : PASS
9094 19:22:47.155112 Jitter Meter : NO K
9095 19:22:47.158556 CBT Training : PASS
9096 19:22:47.161568 Write leveling : PASS
9097 19:22:47.161640 RX DQS gating : PASS
9098 19:22:47.165077 RX DQ/DQS(RDDQC) : PASS
9099 19:22:47.168506 TX DQ/DQS : PASS
9100 19:22:47.168586 RX DATLAT : PASS
9101 19:22:47.171745 RX DQ/DQS(Engine): PASS
9102 19:22:47.174756 TX OE : PASS
9103 19:22:47.174858 All Pass.
9104 19:22:47.174944
9105 19:22:47.178392 DramC Write-DBI on
9106 19:22:47.178507 PER_BANK_REFRESH: Hybrid Mode
9107 19:22:47.181174 TX_TRACKING: ON
9108 19:22:47.191343 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9109 19:22:47.198246 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9110 19:22:47.204804 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9111 19:22:47.207690 [FAST_K] Save calibration result to emmc
9112 19:22:47.211527 sync common calibartion params.
9113 19:22:47.214921 sync cbt_mode0:1, 1:1
9114 19:22:47.215003 dram_init: ddr_geometry: 2
9115 19:22:47.217797 dram_init: ddr_geometry: 2
9116 19:22:47.220961 dram_init: ddr_geometry: 2
9117 19:22:47.224193 0:dram_rank_size:100000000
9118 19:22:47.224275 1:dram_rank_size:100000000
9119 19:22:47.231022 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9120 19:22:47.234055 DFS_SHUFFLE_HW_MODE: ON
9121 19:22:47.237829 dramc_set_vcore_voltage set vcore to 725000
9122 19:22:47.240655 Read voltage for 1600, 0
9123 19:22:47.240736 Vio18 = 0
9124 19:22:47.240802 Vcore = 725000
9125 19:22:47.244297 Vdram = 0
9126 19:22:47.244377 Vddq = 0
9127 19:22:47.244443 Vmddr = 0
9128 19:22:47.247276 switch to 3200 Mbps bootup
9129 19:22:47.247358 [DramcRunTimeConfig]
9130 19:22:47.250871 PHYPLL
9131 19:22:47.250952 DPM_CONTROL_AFTERK: ON
9132 19:22:47.254003 PER_BANK_REFRESH: ON
9133 19:22:47.256931 REFRESH_OVERHEAD_REDUCTION: ON
9134 19:22:47.257012 CMD_PICG_NEW_MODE: OFF
9135 19:22:47.260561 XRTWTW_NEW_MODE: ON
9136 19:22:47.260641 XRTRTR_NEW_MODE: ON
9137 19:22:47.263573 TX_TRACKING: ON
9138 19:22:47.263662 RDSEL_TRACKING: OFF
9139 19:22:47.267202 DQS Precalculation for DVFS: ON
9140 19:22:47.270307 RX_TRACKING: OFF
9141 19:22:47.270387 HW_GATING DBG: ON
9142 19:22:47.273396 ZQCS_ENABLE_LP4: ON
9143 19:22:47.273500 RX_PICG_NEW_MODE: ON
9144 19:22:47.276529 TX_PICG_NEW_MODE: ON
9145 19:22:47.280048 ENABLE_RX_DCM_DPHY: ON
9146 19:22:47.280129 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9147 19:22:47.283199 DUMMY_READ_FOR_TRACKING: OFF
9148 19:22:47.286800 !!! SPM_CONTROL_AFTERK: OFF
9149 19:22:47.290082 !!! SPM could not control APHY
9150 19:22:47.293179 IMPEDANCE_TRACKING: ON
9151 19:22:47.293259 TEMP_SENSOR: ON
9152 19:22:47.293342 HW_SAVE_FOR_SR: OFF
9153 19:22:47.296800 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9154 19:22:47.303320 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9155 19:22:47.303401 Read ODT Tracking: ON
9156 19:22:47.306381 Refresh Rate DeBounce: ON
9157 19:22:47.306461 DFS_NO_QUEUE_FLUSH: ON
9158 19:22:47.310083 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9159 19:22:47.313043 ENABLE_DFS_RUNTIME_MRW: OFF
9160 19:22:47.316619 DDR_RESERVE_NEW_MODE: ON
9161 19:22:47.319684 MR_CBT_SWITCH_FREQ: ON
9162 19:22:47.319756 =========================
9163 19:22:47.339041 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9164 19:22:47.342488 dram_init: ddr_geometry: 2
9165 19:22:47.360779 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9166 19:22:47.364431 dram_init: dram init end (result: 0)
9167 19:22:47.370409 DRAM-K: Full calibration passed in 24460 msecs
9168 19:22:47.374020 MRC: failed to locate region type 0.
9169 19:22:47.374109 DRAM rank0 size:0x100000000,
9170 19:22:47.377082 DRAM rank1 size=0x100000000
9171 19:22:47.387257 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9172 19:22:47.393653 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9173 19:22:47.400245 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9174 19:22:47.410121 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9175 19:22:47.410205 DRAM rank0 size:0x100000000,
9176 19:22:47.413430 DRAM rank1 size=0x100000000
9177 19:22:47.413513 CBMEM:
9178 19:22:47.416423 IMD: root @ 0xfffff000 254 entries.
9179 19:22:47.419932 IMD: root @ 0xffffec00 62 entries.
9180 19:22:47.422965 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9181 19:22:47.429631 WARNING: RO_VPD is uninitialized or empty.
9182 19:22:47.433200 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9183 19:22:47.441089 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9184 19:22:47.453405 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9185 19:22:47.465031 BS: romstage times (exec / console): total (unknown) / 23981 ms
9186 19:22:47.465117
9187 19:22:47.465188
9188 19:22:47.475086 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9189 19:22:47.478152 ARM64: Exception handlers installed.
9190 19:22:47.481115 ARM64: Testing exception
9191 19:22:47.484829 ARM64: Done test exception
9192 19:22:47.484905 Enumerating buses...
9193 19:22:47.487949 Show all devs... Before device enumeration.
9194 19:22:47.491041 Root Device: enabled 1
9195 19:22:47.494663 CPU_CLUSTER: 0: enabled 1
9196 19:22:47.494748 CPU: 00: enabled 1
9197 19:22:47.497724 Compare with tree...
9198 19:22:47.497797 Root Device: enabled 1
9199 19:22:47.501423 CPU_CLUSTER: 0: enabled 1
9200 19:22:47.504328 CPU: 00: enabled 1
9201 19:22:47.504399 Root Device scanning...
9202 19:22:47.507746 scan_static_bus for Root Device
9203 19:22:47.511023 CPU_CLUSTER: 0 enabled
9204 19:22:47.514354 scan_static_bus for Root Device done
9205 19:22:47.517877 scan_bus: bus Root Device finished in 8 msecs
9206 19:22:47.517959 done
9207 19:22:47.524264 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9208 19:22:47.527735 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9209 19:22:47.534052 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9210 19:22:47.537634 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9211 19:22:47.540700 Allocating resources...
9212 19:22:47.544452 Reading resources...
9213 19:22:47.547372 Root Device read_resources bus 0 link: 0
9214 19:22:47.550768 DRAM rank0 size:0x100000000,
9215 19:22:47.550851 DRAM rank1 size=0x100000000
9216 19:22:47.557733 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9217 19:22:47.557815 CPU: 00 missing read_resources
9218 19:22:47.564049 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9219 19:22:47.567067 Root Device read_resources bus 0 link: 0 done
9220 19:22:47.570483 Done reading resources.
9221 19:22:47.573809 Show resources in subtree (Root Device)...After reading.
9222 19:22:47.577362 Root Device child on link 0 CPU_CLUSTER: 0
9223 19:22:47.580134 CPU_CLUSTER: 0 child on link 0 CPU: 00
9224 19:22:47.590121 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9225 19:22:47.590232 CPU: 00
9226 19:22:47.596356 Root Device assign_resources, bus 0 link: 0
9227 19:22:47.600059 CPU_CLUSTER: 0 missing set_resources
9228 19:22:47.603060 Root Device assign_resources, bus 0 link: 0 done
9229 19:22:47.606682 Done setting resources.
9230 19:22:47.609738 Show resources in subtree (Root Device)...After assigning values.
9231 19:22:47.612732 Root Device child on link 0 CPU_CLUSTER: 0
9232 19:22:47.619789 CPU_CLUSTER: 0 child on link 0 CPU: 00
9233 19:22:47.626360 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9234 19:22:47.629394 CPU: 00
9235 19:22:47.629473 Done allocating resources.
9236 19:22:47.636234 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9237 19:22:47.636332 Enabling resources...
9238 19:22:47.639301 done.
9239 19:22:47.642409 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9240 19:22:47.646262 Initializing devices...
9241 19:22:47.646370 Root Device init
9242 19:22:47.649272 init hardware done!
9243 19:22:47.649349 0x00000018: ctrlr->caps
9244 19:22:47.652411 52.000 MHz: ctrlr->f_max
9245 19:22:47.655750 0.400 MHz: ctrlr->f_min
9246 19:22:47.658772 0x40ff8080: ctrlr->voltages
9247 19:22:47.658849 sclk: 390625
9248 19:22:47.658929 Bus Width = 1
9249 19:22:47.662451 sclk: 390625
9250 19:22:47.662541 Bus Width = 1
9251 19:22:47.665565 Early init status = 3
9252 19:22:47.669021 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9253 19:22:47.673142 in-header: 03 fc 00 00 01 00 00 00
9254 19:22:47.676731 in-data: 00
9255 19:22:47.680062 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9256 19:22:47.685462 in-header: 03 fd 00 00 00 00 00 00
9257 19:22:47.688691 in-data:
9258 19:22:47.692218 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9259 19:22:47.696327 in-header: 03 fc 00 00 01 00 00 00
9260 19:22:47.700023 in-data: 00
9261 19:22:47.703059 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9262 19:22:47.708584 in-header: 03 fd 00 00 00 00 00 00
9263 19:22:47.712260 in-data:
9264 19:22:47.715254 [SSUSB] Setting up USB HOST controller...
9265 19:22:47.718954 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9266 19:22:47.721990 [SSUSB] phy power-on done.
9267 19:22:47.725319 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9268 19:22:47.732014 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9269 19:22:47.734875 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9270 19:22:47.741577 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9271 19:22:47.748275 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9272 19:22:47.754898 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9273 19:22:47.761781 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9274 19:22:47.768346 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9275 19:22:47.771353 SPM: binary array size = 0x9dc
9276 19:22:47.774898 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9277 19:22:47.781109 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9278 19:22:47.788239 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9279 19:22:47.794767 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9280 19:22:47.797635 configure_display: Starting display init
9281 19:22:47.832152 anx7625_power_on_init: Init interface.
9282 19:22:47.835048 anx7625_disable_pd_protocol: Disabled PD feature.
9283 19:22:47.838764 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9284 19:22:47.866390 anx7625_start_dp_work: Secure OCM version=00
9285 19:22:47.869511 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9286 19:22:47.884390 sp_tx_get_edid_block: EDID Block = 1
9287 19:22:47.987372 Extracted contents:
9288 19:22:47.990110 header: 00 ff ff ff ff ff ff 00
9289 19:22:47.993500 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9290 19:22:47.997167 version: 01 04
9291 19:22:48.000273 basic params: 95 1f 11 78 0a
9292 19:22:48.003845 chroma info: 76 90 94 55 54 90 27 21 50 54
9293 19:22:48.007083 established: 00 00 00
9294 19:22:48.013381 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9295 19:22:48.020073 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9296 19:22:48.023410 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9297 19:22:48.029906 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9298 19:22:48.036581 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9299 19:22:48.039594 extensions: 00
9300 19:22:48.039670 checksum: fb
9301 19:22:48.039743
9302 19:22:48.043275 Manufacturer: IVO Model 57d Serial Number 0
9303 19:22:48.046342 Made week 0 of 2020
9304 19:22:48.049821 EDID version: 1.4
9305 19:22:48.049898 Digital display
9306 19:22:48.052698 6 bits per primary color channel
9307 19:22:48.052775 DisplayPort interface
9308 19:22:48.056025 Maximum image size: 31 cm x 17 cm
9309 19:22:48.059683 Gamma: 220%
9310 19:22:48.059757 Check DPMS levels
9311 19:22:48.065989 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9312 19:22:48.069593 First detailed timing is preferred timing
9313 19:22:48.069671 Established timings supported:
9314 19:22:48.072621 Standard timings supported:
9315 19:22:48.076258 Detailed timings
9316 19:22:48.079250 Hex of detail: 383680a07038204018303c0035ae10000019
9317 19:22:48.085693 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9318 19:22:48.089238 0780 0798 07c8 0820 hborder 0
9319 19:22:48.092726 0438 043b 0447 0458 vborder 0
9320 19:22:48.095539 -hsync -vsync
9321 19:22:48.095612 Did detailed timing
9322 19:22:48.102288 Hex of detail: 000000000000000000000000000000000000
9323 19:22:48.105267 Manufacturer-specified data, tag 0
9324 19:22:48.108772 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9325 19:22:48.112299 ASCII string: InfoVision
9326 19:22:48.115447 Hex of detail: 000000fe00523134304e574635205248200a
9327 19:22:48.118778 ASCII string: R140NWF5 RH
9328 19:22:48.118859 Checksum
9329 19:22:48.122119 Checksum: 0xfb (valid)
9330 19:22:48.125384 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9331 19:22:48.128951 DSI data_rate: 832800000 bps
9332 19:22:48.135672 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9333 19:22:48.138657 anx7625_parse_edid: pixelclock(138800).
9334 19:22:48.141668 hactive(1920), hsync(48), hfp(24), hbp(88)
9335 19:22:48.145337 vactive(1080), vsync(12), vfp(3), vbp(17)
9336 19:22:48.148305 anx7625_dsi_config: config dsi.
9337 19:22:48.155025 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9338 19:22:48.169293 anx7625_dsi_config: success to config DSI
9339 19:22:48.172433 anx7625_dp_start: MIPI phy setup OK.
9340 19:22:48.175484 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9341 19:22:48.179001 mtk_ddp_mode_set invalid vrefresh 60
9342 19:22:48.182470 main_disp_path_setup
9343 19:22:48.182550 ovl_layer_smi_id_en
9344 19:22:48.185591 ovl_layer_smi_id_en
9345 19:22:48.185671 ccorr_config
9346 19:22:48.185738 aal_config
9347 19:22:48.188645 gamma_config
9348 19:22:48.188723 postmask_config
9349 19:22:48.192312 dither_config
9350 19:22:48.195145 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9351 19:22:48.201553 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9352 19:22:48.205002 Root Device init finished in 555 msecs
9353 19:22:48.208342 CPU_CLUSTER: 0 init
9354 19:22:48.214990 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9355 19:22:48.222022 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9356 19:22:48.222102 APU_MBOX 0x190000b0 = 0x10001
9357 19:22:48.224928 APU_MBOX 0x190001b0 = 0x10001
9358 19:22:48.228048 APU_MBOX 0x190005b0 = 0x10001
9359 19:22:48.231843 APU_MBOX 0x190006b0 = 0x10001
9360 19:22:48.237900 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9361 19:22:48.248319 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9362 19:22:48.260473 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9363 19:22:48.267128 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9364 19:22:48.278804 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9365 19:22:48.287816 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9366 19:22:48.290862 CPU_CLUSTER: 0 init finished in 81 msecs
9367 19:22:48.294545 Devices initialized
9368 19:22:48.297487 Show all devs... After init.
9369 19:22:48.297561 Root Device: enabled 1
9370 19:22:48.301082 CPU_CLUSTER: 0: enabled 1
9371 19:22:48.304515 CPU: 00: enabled 1
9372 19:22:48.307378 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9373 19:22:48.310666 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9374 19:22:48.314032 ELOG: NV offset 0x57f000 size 0x1000
9375 19:22:48.321290 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9376 19:22:48.327538 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9377 19:22:48.330968 ELOG: Event(17) added with size 13 at 2024-04-18 19:22:47 UTC
9378 19:22:48.337769 out: cmd=0x121: 03 db 21 01 00 00 00 00
9379 19:22:48.341171 in-header: 03 0e 00 00 2c 00 00 00
9380 19:22:48.350838 in-data: 50 69 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9381 19:22:48.357596 ELOG: Event(A1) added with size 10 at 2024-04-18 19:22:47 UTC
9382 19:22:48.364201 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9383 19:22:48.370476 ELOG: Event(A0) added with size 9 at 2024-04-18 19:22:47 UTC
9384 19:22:48.374011 elog_add_boot_reason: Logged dev mode boot
9385 19:22:48.380556 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9386 19:22:48.380634 Finalize devices...
9387 19:22:48.383819 Devices finalized
9388 19:22:48.387064 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9389 19:22:48.390140 Writing coreboot table at 0xffe64000
9390 19:22:48.393578 0. 000000000010a000-0000000000113fff: RAMSTAGE
9391 19:22:48.400415 1. 0000000040000000-00000000400fffff: RAM
9392 19:22:48.403427 2. 0000000040100000-000000004032afff: RAMSTAGE
9393 19:22:48.406971 3. 000000004032b000-00000000545fffff: RAM
9394 19:22:48.409837 4. 0000000054600000-000000005465ffff: BL31
9395 19:22:48.413258 5. 0000000054660000-00000000ffe63fff: RAM
9396 19:22:48.420064 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9397 19:22:48.423307 7. 0000000100000000-000000023fffffff: RAM
9398 19:22:48.426731 Passing 5 GPIOs to payload:
9399 19:22:48.429789 NAME | PORT | POLARITY | VALUE
9400 19:22:48.436382 EC in RW | 0x000000aa | low | undefined
9401 19:22:48.440023 EC interrupt | 0x00000005 | low | undefined
9402 19:22:48.443113 TPM interrupt | 0x000000ab | high | undefined
9403 19:22:48.449667 SD card detect | 0x00000011 | high | undefined
9404 19:22:48.452713 speaker enable | 0x00000093 | high | undefined
9405 19:22:48.455998 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9406 19:22:48.459615 in-header: 03 f9 00 00 02 00 00 00
9407 19:22:48.462732 in-data: 02 00
9408 19:22:48.465709 ADC[4]: Raw value=902955 ID=7
9409 19:22:48.469432 ADC[3]: Raw value=213546 ID=1
9410 19:22:48.469511 RAM Code: 0x71
9411 19:22:48.472513 ADC[6]: Raw value=75000 ID=0
9412 19:22:48.475624 ADC[5]: Raw value=213546 ID=1
9413 19:22:48.475698 SKU Code: 0x1
9414 19:22:48.482275 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum f149
9415 19:22:48.482359 coreboot table: 964 bytes.
9416 19:22:48.485994 IMD ROOT 0. 0xfffff000 0x00001000
9417 19:22:48.489013 IMD SMALL 1. 0xffffe000 0x00001000
9418 19:22:48.492334 RO MCACHE 2. 0xffffc000 0x00001104
9419 19:22:48.495730 CONSOLE 3. 0xfff7c000 0x00080000
9420 19:22:48.499125 FMAP 4. 0xfff7b000 0x00000452
9421 19:22:48.502328 TIME STAMP 5. 0xfff7a000 0x00000910
9422 19:22:48.505353 VBOOT WORK 6. 0xfff66000 0x00014000
9423 19:22:48.508886 RAMOOPS 7. 0xffe66000 0x00100000
9424 19:22:48.512070 COREBOOT 8. 0xffe64000 0x00002000
9425 19:22:48.515622 IMD small region:
9426 19:22:48.518521 IMD ROOT 0. 0xffffec00 0x00000400
9427 19:22:48.521820 VPD 1. 0xffffeb80 0x0000006c
9428 19:22:48.525326 MMC STATUS 2. 0xffffeb60 0x00000004
9429 19:22:48.531455 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9430 19:22:48.531533 Probing TPM: done!
9431 19:22:48.538214 Connected to device vid:did:rid of 1ae0:0028:00
9432 19:22:48.544827 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
9433 19:22:48.548447 Initialized TPM device CR50 revision 0
9434 19:22:48.552099 Checking cr50 for pending updates
9435 19:22:48.557917 Reading cr50 TPM mode
9436 19:22:48.566305 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9437 19:22:48.572961 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9438 19:22:48.613022 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9439 19:22:48.616229 Checking segment from ROM address 0x40100000
9440 19:22:48.619769 Checking segment from ROM address 0x4010001c
9441 19:22:48.626302 Loading segment from ROM address 0x40100000
9442 19:22:48.626406 code (compression=0)
9443 19:22:48.636277 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9444 19:22:48.642640 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9445 19:22:48.642723 it's not compressed!
9446 19:22:48.649289 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9447 19:22:48.655779 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9448 19:22:48.673431 Loading segment from ROM address 0x4010001c
9449 19:22:48.673538 Entry Point 0x80000000
9450 19:22:48.676483 Loaded segments
9451 19:22:48.680168 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9452 19:22:48.686669 Jumping to boot code at 0x80000000(0xffe64000)
9453 19:22:48.693341 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9454 19:22:48.699952 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9455 19:22:48.707694 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9456 19:22:48.711424 Checking segment from ROM address 0x40100000
9457 19:22:48.714595 Checking segment from ROM address 0x4010001c
9458 19:22:48.721323 Loading segment from ROM address 0x40100000
9459 19:22:48.721410 code (compression=1)
9460 19:22:48.727857 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9461 19:22:48.737621 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9462 19:22:48.737740 using LZMA
9463 19:22:48.746451 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9464 19:22:48.752999 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9465 19:22:48.756419 Loading segment from ROM address 0x4010001c
9466 19:22:48.756507 Entry Point 0x54601000
9467 19:22:48.759724 Loaded segments
9468 19:22:48.762741 NOTICE: MT8192 bl31_setup
9469 19:22:48.769685 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9470 19:22:48.773383 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9471 19:22:48.776129 WARNING: region 0:
9472 19:22:48.779348 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9473 19:22:48.779425 WARNING: region 1:
9474 19:22:48.786585 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9475 19:22:48.789561 WARNING: region 2:
9476 19:22:48.792620 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9477 19:22:48.796351 WARNING: region 3:
9478 19:22:48.799711 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9479 19:22:48.803020 WARNING: region 4:
9480 19:22:48.809477 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9481 19:22:48.809557 WARNING: region 5:
9482 19:22:48.813103 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9483 19:22:48.816118 WARNING: region 6:
9484 19:22:48.819771 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9485 19:22:48.822790 WARNING: region 7:
9486 19:22:48.826421 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9487 19:22:48.832550 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9488 19:22:48.836074 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9489 19:22:48.839234 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9490 19:22:48.846028 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9491 19:22:48.849153 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9492 19:22:48.856088 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9493 19:22:48.859093 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9494 19:22:48.862773 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9495 19:22:48.869273 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9496 19:22:48.872777 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9497 19:22:48.876159 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9498 19:22:48.882559 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9499 19:22:48.885899 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9500 19:22:48.892538 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9501 19:22:48.895837 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9502 19:22:48.899280 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9503 19:22:48.905529 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9504 19:22:48.909209 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9505 19:22:48.912682 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9506 19:22:48.918701 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9507 19:22:48.922347 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9508 19:22:48.929176 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9509 19:22:48.932251 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9510 19:22:48.935288 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9511 19:22:48.942049 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9512 19:22:48.945645 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9513 19:22:48.952415 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9514 19:22:48.955552 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9515 19:22:48.958748 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9516 19:22:48.965025 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9517 19:22:48.968478 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9518 19:22:48.975031 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9519 19:22:48.978637 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9520 19:22:48.981681 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9521 19:22:48.985307 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9522 19:22:48.992294 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9523 19:22:48.995190 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9524 19:22:48.998326 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9525 19:22:49.001800 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9526 19:22:49.008471 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9527 19:22:49.011711 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9528 19:22:49.015138 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9529 19:22:49.018697 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9530 19:22:49.025240 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9531 19:22:49.028236 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9532 19:22:49.031817 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9533 19:22:49.035020 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9534 19:22:49.041712 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9535 19:22:49.044787 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9536 19:22:49.051993 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9537 19:22:49.054825 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9538 19:22:49.058523 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9539 19:22:49.065073 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9540 19:22:49.067955 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9541 19:22:49.074932 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9542 19:22:49.078103 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9543 19:22:49.084797 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9544 19:22:49.087912 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9545 19:22:49.091417 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9546 19:22:49.097856 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9547 19:22:49.101456 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9548 19:22:49.108054 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9549 19:22:49.111157 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9550 19:22:49.118145 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9551 19:22:49.121356 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9552 19:22:49.128085 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9553 19:22:49.130978 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9554 19:22:49.134568 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9555 19:22:49.141298 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9556 19:22:49.144412 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9557 19:22:49.151143 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9558 19:22:49.154698 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9559 19:22:49.161273 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9560 19:22:49.164379 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9561 19:22:49.167790 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9562 19:22:49.174595 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9563 19:22:49.177595 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9564 19:22:49.184582 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9565 19:22:49.187384 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9566 19:22:49.194457 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9567 19:22:49.197533 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9568 19:22:49.203970 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9569 19:22:49.207456 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9570 19:22:49.213997 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9571 19:22:49.217590 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9572 19:22:49.220650 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9573 19:22:49.227414 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9574 19:22:49.230859 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9575 19:22:49.237214 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9576 19:22:49.240984 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9577 19:22:49.244162 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9578 19:22:49.250977 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9579 19:22:49.253946 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9580 19:22:49.260499 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9581 19:22:49.264132 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9582 19:22:49.270698 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9583 19:22:49.273823 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9584 19:22:49.277559 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9585 19:22:49.283588 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9586 19:22:49.287195 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9587 19:22:49.290613 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9588 19:22:49.293651 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9589 19:22:49.300106 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9590 19:22:49.303435 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9591 19:22:49.310369 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9592 19:22:49.313691 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9593 19:22:49.316984 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9594 19:22:49.323372 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9595 19:22:49.327305 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9596 19:22:49.333755 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9597 19:22:49.336741 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9598 19:22:49.340347 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9599 19:22:49.346770 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9600 19:22:49.350096 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9601 19:22:49.356758 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9602 19:22:49.360376 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9603 19:22:49.363445 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9604 19:22:49.369946 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9605 19:22:49.373554 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9606 19:22:49.376916 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9607 19:22:49.379989 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9608 19:22:49.386647 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9609 19:22:49.390262 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9610 19:22:49.393221 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9611 19:22:49.399816 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9612 19:22:49.402883 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9613 19:22:49.406468 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9614 19:22:49.413041 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9615 19:22:49.416470 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9616 19:22:49.422975 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9617 19:22:49.426066 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9618 19:22:49.429404 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9619 19:22:49.435970 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9620 19:22:49.439669 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9621 19:22:49.446293 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9622 19:22:49.449317 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9623 19:22:49.452906 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9624 19:22:49.459407 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9625 19:22:49.462646 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9626 19:22:49.469478 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9627 19:22:49.472960 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9628 19:22:49.476016 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9629 19:22:49.482685 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9630 19:22:49.486157 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9631 19:22:49.489115 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9632 19:22:49.495814 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9633 19:22:49.499338 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9634 19:22:49.505805 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9635 19:22:49.508936 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9636 19:22:49.515456 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9637 19:22:49.519101 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9638 19:22:49.522106 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9639 19:22:49.529218 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9640 19:22:49.532075 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9641 19:22:49.535392 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9642 19:22:49.542363 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9643 19:22:49.545426 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9644 19:22:49.552170 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9645 19:22:49.555856 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9646 19:22:49.559033 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9647 19:22:49.565661 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9648 19:22:49.568701 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9649 19:22:49.575298 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9650 19:22:49.578826 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9651 19:22:49.582179 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9652 19:22:49.588806 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9653 19:22:49.592196 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9654 19:22:49.598645 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9655 19:22:49.601643 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9656 19:22:49.605133 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9657 19:22:49.611908 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9658 19:22:49.614812 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9659 19:22:49.621527 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9660 19:22:49.624595 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9661 19:22:49.628298 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9662 19:22:49.634265 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9663 19:22:49.637918 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9664 19:22:49.644574 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9665 19:22:49.647803 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9666 19:22:49.650720 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9667 19:22:49.657567 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9668 19:22:49.661013 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9669 19:22:49.667605 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9670 19:22:49.670647 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9671 19:22:49.677074 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9672 19:22:49.680531 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9673 19:22:49.684127 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9674 19:22:49.690694 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9675 19:22:49.693634 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9676 19:22:49.700140 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9677 19:22:49.703796 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9678 19:22:49.706824 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9679 19:22:49.713564 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9680 19:22:49.717014 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9681 19:22:49.723622 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9682 19:22:49.726659 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9683 19:22:49.733448 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9684 19:22:49.736410 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9685 19:22:49.740120 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9686 19:22:49.746827 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9687 19:22:49.749853 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9688 19:22:49.756497 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9689 19:22:49.759471 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9690 19:22:49.766186 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9691 19:22:49.769107 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9692 19:22:49.772816 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9693 19:22:49.779237 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9694 19:22:49.782259 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9695 19:22:49.789044 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9696 19:22:49.792574 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9697 19:22:49.799616 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9698 19:22:49.802499 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9699 19:22:49.809010 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9700 19:22:49.811835 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9701 19:22:49.815476 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9702 19:22:49.822289 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9703 19:22:49.825210 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9704 19:22:49.831994 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9705 19:22:49.835017 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9706 19:22:49.838661 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9707 19:22:49.845235 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9708 19:22:49.848272 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9709 19:22:49.855075 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9710 19:22:49.858097 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9711 19:22:49.864920 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9712 19:22:49.868341 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9713 19:22:49.871327 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9714 19:22:49.878165 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9715 19:22:49.881462 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9716 19:22:49.884771 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9717 19:22:49.891170 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9718 19:22:49.894719 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9719 19:22:49.898001 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9720 19:22:49.901141 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9721 19:22:49.907871 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9722 19:22:49.911122 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9723 19:22:49.918193 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9724 19:22:49.920913 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9725 19:22:49.924532 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9726 19:22:49.931012 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9727 19:22:49.934147 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9728 19:22:49.940722 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9729 19:22:49.943867 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9730 19:22:49.947183 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9731 19:22:49.953941 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9732 19:22:49.957000 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9733 19:22:49.960115 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9734 19:22:49.966704 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9735 19:22:49.970242 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9736 19:22:49.976984 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9737 19:22:49.980032 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9738 19:22:49.983022 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9739 19:22:49.989591 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9740 19:22:49.993147 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9741 19:22:49.996570 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9742 19:22:50.003069 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9743 19:22:50.006609 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9744 19:22:50.013218 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9745 19:22:50.016381 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9746 19:22:50.019730 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9747 19:22:50.026718 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9748 19:22:50.029646 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9749 19:22:50.032836 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9750 19:22:50.039284 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9751 19:22:50.042932 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9752 19:22:50.049540 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9753 19:22:50.052432 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9754 19:22:50.056008 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9755 19:22:50.062609 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9756 19:22:50.065788 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9757 19:22:50.068843 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9758 19:22:50.072465 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9759 19:22:50.075992 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9760 19:22:50.082190 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9761 19:22:50.085878 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9762 19:22:50.088960 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9763 19:22:50.092354 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9764 19:22:50.098928 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9765 19:22:50.101792 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9766 19:22:50.105296 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9767 19:22:50.112015 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9768 19:22:50.115608 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9769 19:22:50.118544 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9770 19:22:50.125300 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9771 19:22:50.128565 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9772 19:22:50.135139 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9773 19:22:50.138408 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9774 19:22:50.145379 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9775 19:22:50.148287 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9776 19:22:50.151762 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9777 19:22:50.158389 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9778 19:22:50.161486 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9779 19:22:50.168364 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9780 19:22:50.171414 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9781 19:22:50.174476 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9782 19:22:50.181238 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9783 19:22:50.184327 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9784 19:22:50.191061 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9785 19:22:50.194056 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9786 19:22:50.200979 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9787 19:22:50.204019 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9788 19:22:50.207594 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9789 19:22:50.214032 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9790 19:22:50.216934 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9791 19:22:50.223542 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9792 19:22:50.227226 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9793 19:22:50.230613 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9794 19:22:50.237030 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9795 19:22:50.240267 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9796 19:22:50.246848 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9797 19:22:50.250171 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9798 19:22:50.256897 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9799 19:22:50.260075 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9800 19:22:50.263190 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9801 19:22:50.269880 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9802 19:22:50.273026 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9803 19:22:50.279756 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9804 19:22:50.282757 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9805 19:22:50.289452 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9806 19:22:50.293197 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9807 19:22:50.296167 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9808 19:22:50.302730 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9809 19:22:50.305802 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9810 19:22:50.312517 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9811 19:22:50.315586 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9812 19:22:50.322795 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9813 19:22:50.325783 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9814 19:22:50.328739 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9815 19:22:50.335425 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9816 19:22:50.338466 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9817 19:22:50.345296 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9818 19:22:50.348721 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9819 19:22:50.352156 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9820 19:22:50.358535 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9821 19:22:50.362190 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9822 19:22:50.368496 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9823 19:22:50.371705 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9824 19:22:50.378338 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9825 19:22:50.381849 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9826 19:22:50.384762 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9827 19:22:50.391410 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9828 19:22:50.394536 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9829 19:22:50.401116 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9830 19:22:50.404679 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9831 19:22:50.411455 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9832 19:22:50.414428 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9833 19:22:50.418205 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9834 19:22:50.424574 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9835 19:22:50.428062 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9836 19:22:50.434496 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9837 19:22:50.437282 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9838 19:22:50.444016 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9839 19:22:50.447615 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9840 19:22:50.450844 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9841 19:22:50.457478 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9842 19:22:50.460842 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9843 19:22:50.467481 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9844 19:22:50.470489 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9845 19:22:50.477641 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9846 19:22:50.480871 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9847 19:22:50.483758 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9848 19:22:50.490839 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9849 19:22:50.494210 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9850 19:22:50.500825 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9851 19:22:50.503915 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9852 19:22:50.510501 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9853 19:22:50.513476 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9854 19:22:50.517154 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9855 19:22:50.523296 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9856 19:22:50.526831 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9857 19:22:50.533491 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9858 19:22:50.536593 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9859 19:22:50.543288 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9860 19:22:50.546320 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9861 19:22:50.553045 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9862 19:22:50.556487 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9863 19:22:50.563147 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9864 19:22:50.566408 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9865 19:22:50.569702 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9866 19:22:50.576560 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9867 19:22:50.579383 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9868 19:22:50.585673 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9869 19:22:50.589385 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9870 19:22:50.596012 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9871 19:22:50.599299 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9872 19:22:50.602557 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9873 19:22:50.608954 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9874 19:22:50.612440 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9875 19:22:50.618981 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9876 19:22:50.621953 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9877 19:22:50.628747 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9878 19:22:50.632366 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9879 19:22:50.638851 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9880 19:22:50.641795 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9881 19:22:50.645521 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9882 19:22:50.651560 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9883 19:22:50.655106 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9884 19:22:50.661469 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9885 19:22:50.665011 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9886 19:22:50.671686 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9887 19:22:50.674650 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9888 19:22:50.681640 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9889 19:22:50.684517 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9890 19:22:50.687872 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9891 19:22:50.694370 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9892 19:22:50.698017 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9893 19:22:50.704519 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9894 19:22:50.708113 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9895 19:22:50.714830 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9896 19:22:50.717398 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9897 19:22:50.724481 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9898 19:22:50.727482 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9899 19:22:50.734140 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9900 19:22:50.737202 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9901 19:22:50.743928 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9902 19:22:50.747513 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9903 19:22:50.753685 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9904 19:22:50.757425 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9905 19:22:50.764336 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9906 19:22:50.767246 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9907 19:22:50.773892 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9908 19:22:50.777235 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9909 19:22:50.783708 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9910 19:22:50.786659 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9911 19:22:50.793345 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9912 19:22:50.796872 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9913 19:22:50.803260 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9914 19:22:50.806331 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9915 19:22:50.813006 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9916 19:22:50.816457 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9917 19:22:50.823385 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9918 19:22:50.826399 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9919 19:22:50.832668 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9920 19:22:50.836357 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9921 19:22:50.842486 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9922 19:22:50.842569 INFO: [APUAPC] vio 0
9923 19:22:50.849517 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9924 19:22:50.853258 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9925 19:22:50.856212 INFO: [APUAPC] D0_APC_0: 0x400510
9926 19:22:50.859878 INFO: [APUAPC] D0_APC_1: 0x0
9927 19:22:50.862987 INFO: [APUAPC] D0_APC_2: 0x1540
9928 19:22:50.866055 INFO: [APUAPC] D0_APC_3: 0x0
9929 19:22:50.869696 INFO: [APUAPC] D1_APC_0: 0xffffffff
9930 19:22:50.872649 INFO: [APUAPC] D1_APC_1: 0xffffffff
9931 19:22:50.876212 INFO: [APUAPC] D1_APC_2: 0x3fffff
9932 19:22:50.879474 INFO: [APUAPC] D1_APC_3: 0x0
9933 19:22:50.882948 INFO: [APUAPC] D2_APC_0: 0xffffffff
9934 19:22:50.886216 INFO: [APUAPC] D2_APC_1: 0xffffffff
9935 19:22:50.889434 INFO: [APUAPC] D2_APC_2: 0x3fffff
9936 19:22:50.892623 INFO: [APUAPC] D2_APC_3: 0x0
9937 19:22:50.896472 INFO: [APUAPC] D3_APC_0: 0xffffffff
9938 19:22:50.899116 INFO: [APUAPC] D3_APC_1: 0xffffffff
9939 19:22:50.902653 INFO: [APUAPC] D3_APC_2: 0x3fffff
9940 19:22:50.906073 INFO: [APUAPC] D3_APC_3: 0x0
9941 19:22:50.908990 INFO: [APUAPC] D4_APC_0: 0xffffffff
9942 19:22:50.912631 INFO: [APUAPC] D4_APC_1: 0xffffffff
9943 19:22:50.915667 INFO: [APUAPC] D4_APC_2: 0x3fffff
9944 19:22:50.919377 INFO: [APUAPC] D4_APC_3: 0x0
9945 19:22:50.922302 INFO: [APUAPC] D5_APC_0: 0xffffffff
9946 19:22:50.925868 INFO: [APUAPC] D5_APC_1: 0xffffffff
9947 19:22:50.929181 INFO: [APUAPC] D5_APC_2: 0x3fffff
9948 19:22:50.929263 INFO: [APUAPC] D5_APC_3: 0x0
9949 19:22:50.935394 INFO: [APUAPC] D6_APC_0: 0xffffffff
9950 19:22:50.938767 INFO: [APUAPC] D6_APC_1: 0xffffffff
9951 19:22:50.942252 INFO: [APUAPC] D6_APC_2: 0x3fffff
9952 19:22:50.942336 INFO: [APUAPC] D6_APC_3: 0x0
9953 19:22:50.945408 INFO: [APUAPC] D7_APC_0: 0xffffffff
9954 19:22:50.952009 INFO: [APUAPC] D7_APC_1: 0xffffffff
9955 19:22:50.955149 INFO: [APUAPC] D7_APC_2: 0x3fffff
9956 19:22:50.955231 INFO: [APUAPC] D7_APC_3: 0x0
9957 19:22:50.958669 INFO: [APUAPC] D8_APC_0: 0xffffffff
9958 19:22:50.964908 INFO: [APUAPC] D8_APC_1: 0xffffffff
9959 19:22:50.968470 INFO: [APUAPC] D8_APC_2: 0x3fffff
9960 19:22:50.968575 INFO: [APUAPC] D8_APC_3: 0x0
9961 19:22:50.972133 INFO: [APUAPC] D9_APC_0: 0xffffffff
9962 19:22:50.975071 INFO: [APUAPC] D9_APC_1: 0xffffffff
9963 19:22:50.978169 INFO: [APUAPC] D9_APC_2: 0x3fffff
9964 19:22:50.981727 INFO: [APUAPC] D9_APC_3: 0x0
9965 19:22:50.984793 INFO: [APUAPC] D10_APC_0: 0xffffffff
9966 19:22:50.988181 INFO: [APUAPC] D10_APC_1: 0xffffffff
9967 19:22:50.991746 INFO: [APUAPC] D10_APC_2: 0x3fffff
9968 19:22:50.994587 INFO: [APUAPC] D10_APC_3: 0x0
9969 19:22:50.998027 INFO: [APUAPC] D11_APC_0: 0xffffffff
9970 19:22:51.004838 INFO: [APUAPC] D11_APC_1: 0xffffffff
9971 19:22:51.007725 INFO: [APUAPC] D11_APC_2: 0x3fffff
9972 19:22:51.007806 INFO: [APUAPC] D11_APC_3: 0x0
9973 19:22:51.011295 INFO: [APUAPC] D12_APC_0: 0xffffffff
9974 19:22:51.018207 INFO: [APUAPC] D12_APC_1: 0xffffffff
9975 19:22:51.021351 INFO: [APUAPC] D12_APC_2: 0x3fffff
9976 19:22:51.021509 INFO: [APUAPC] D12_APC_3: 0x0
9977 19:22:51.028016 INFO: [APUAPC] D13_APC_0: 0xffffffff
9978 19:22:51.030984 INFO: [APUAPC] D13_APC_1: 0xffffffff
9979 19:22:51.034470 INFO: [APUAPC] D13_APC_2: 0x3fffff
9980 19:22:51.037724 INFO: [APUAPC] D13_APC_3: 0x0
9981 19:22:51.041202 INFO: [APUAPC] D14_APC_0: 0xffffffff
9982 19:22:51.044720 INFO: [APUAPC] D14_APC_1: 0xffffffff
9983 19:22:51.047472 INFO: [APUAPC] D14_APC_2: 0x3fffff
9984 19:22:51.051057 INFO: [APUAPC] D14_APC_3: 0x0
9985 19:22:51.054580 INFO: [APUAPC] D15_APC_0: 0xffffffff
9986 19:22:51.057655 INFO: [APUAPC] D15_APC_1: 0xffffffff
9987 19:22:51.060719 INFO: [APUAPC] D15_APC_2: 0x3fffff
9988 19:22:51.064356 INFO: [APUAPC] D15_APC_3: 0x0
9989 19:22:51.064438 INFO: [APUAPC] APC_CON: 0x4
9990 19:22:51.067447 INFO: [NOCDAPC] D0_APC_0: 0x0
9991 19:22:51.071094 INFO: [NOCDAPC] D0_APC_1: 0x0
9992 19:22:51.074164 INFO: [NOCDAPC] D1_APC_0: 0x0
9993 19:22:51.077275 INFO: [NOCDAPC] D1_APC_1: 0xfff
9994 19:22:51.080846 INFO: [NOCDAPC] D2_APC_0: 0x0
9995 19:22:51.083846 INFO: [NOCDAPC] D2_APC_1: 0xfff
9996 19:22:51.087421 INFO: [NOCDAPC] D3_APC_0: 0x0
9997 19:22:51.090369 INFO: [NOCDAPC] D3_APC_1: 0xfff
9998 19:22:51.093633 INFO: [NOCDAPC] D4_APC_0: 0x0
9999 19:22:51.097350 INFO: [NOCDAPC] D4_APC_1: 0xfff
10000 19:22:51.097433 INFO: [NOCDAPC] D5_APC_0: 0x0
10001 19:22:51.100329 INFO: [NOCDAPC] D5_APC_1: 0xfff
10002 19:22:51.103384 INFO: [NOCDAPC] D6_APC_0: 0x0
10003 19:22:51.106708 INFO: [NOCDAPC] D6_APC_1: 0xfff
10004 19:22:51.110117 INFO: [NOCDAPC] D7_APC_0: 0x0
10005 19:22:51.113600 INFO: [NOCDAPC] D7_APC_1: 0xfff
10006 19:22:51.116715 INFO: [NOCDAPC] D8_APC_0: 0x0
10007 19:22:51.120234 INFO: [NOCDAPC] D8_APC_1: 0xfff
10008 19:22:51.123514 INFO: [NOCDAPC] D9_APC_0: 0x0
10009 19:22:51.126518 INFO: [NOCDAPC] D9_APC_1: 0xfff
10010 19:22:51.130111 INFO: [NOCDAPC] D10_APC_0: 0x0
10011 19:22:51.133163 INFO: [NOCDAPC] D10_APC_1: 0xfff
10012 19:22:51.133244 INFO: [NOCDAPC] D11_APC_0: 0x0
10013 19:22:51.136980 INFO: [NOCDAPC] D11_APC_1: 0xfff
10014 19:22:51.139769 INFO: [NOCDAPC] D12_APC_0: 0x0
10015 19:22:51.143287 INFO: [NOCDAPC] D12_APC_1: 0xfff
10016 19:22:51.146410 INFO: [NOCDAPC] D13_APC_0: 0x0
10017 19:22:51.150043 INFO: [NOCDAPC] D13_APC_1: 0xfff
10018 19:22:51.152795 INFO: [NOCDAPC] D14_APC_0: 0x0
10019 19:22:51.156199 INFO: [NOCDAPC] D14_APC_1: 0xfff
10020 19:22:51.159563 INFO: [NOCDAPC] D15_APC_0: 0x0
10021 19:22:51.162800 INFO: [NOCDAPC] D15_APC_1: 0xfff
10022 19:22:51.166368 INFO: [NOCDAPC] APC_CON: 0x4
10023 19:22:51.169335 INFO: [APUAPC] set_apusys_apc done
10024 19:22:51.172954 INFO: [DEVAPC] devapc_init done
10025 19:22:51.176103 INFO: GICv3 without legacy support detected.
10026 19:22:51.179176 INFO: ARM GICv3 driver initialized in EL3
10027 19:22:51.182796 INFO: Maximum SPI INTID supported: 639
10028 19:22:51.188785 INFO: BL31: Initializing runtime services
10029 19:22:51.192535 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10030 19:22:51.195427 INFO: SPM: enable CPC mode
10031 19:22:51.202708 INFO: mcdi ready for mcusys-off-idle and system suspend
10032 19:22:51.205734 INFO: BL31: Preparing for EL3 exit to normal world
10033 19:22:51.208881 INFO: Entry point address = 0x80000000
10034 19:22:51.211922 INFO: SPSR = 0x8
10035 19:22:51.217914
10036 19:22:51.217995
10037 19:22:51.218059
10038 19:22:51.221268 Starting depthcharge on Spherion...
10039 19:22:51.221348
10040 19:22:51.221412 Wipe memory regions:
10041 19:22:51.221472
10042 19:22:51.222158 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10043 19:22:51.222258 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10044 19:22:51.222337 Setting prompt string to ['asurada:']
10045 19:22:51.222420 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10046 19:22:51.224083 [0x00000040000000, 0x00000054600000)
10047 19:22:51.346543
10048 19:22:51.346744 [0x00000054660000, 0x00000080000000)
10049 19:22:51.607282
10050 19:22:51.607413 [0x000000821a7280, 0x000000ffe64000)
10051 19:22:52.351794
10052 19:22:52.351975 [0x00000100000000, 0x00000240000000)
10053 19:22:54.241662
10054 19:22:54.244421 Initializing XHCI USB controller at 0x11200000.
10055 19:22:55.282718
10056 19:22:55.286172 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10057 19:22:55.286288
10058 19:22:55.286381
10059 19:22:55.286470
10060 19:22:55.286752 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10062 19:22:55.387074 asurada: tftpboot 192.168.201.1 13420331/tftp-deploy-9vswnwe8/kernel/image.itb 13420331/tftp-deploy-9vswnwe8/kernel/cmdline
10063 19:22:55.387251 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10064 19:22:55.387393 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10065 19:22:55.391401 tftpboot 192.168.201.1 13420331/tftp-deploy-9vswnwe8/kernel/image.itp-deploy-9vswnwe8/kernel/cmdline
10066 19:22:55.391486
10067 19:22:55.391551 Waiting for link
10068 19:22:55.549477
10069 19:22:55.549615 R8152: Initializing
10070 19:22:55.549684
10071 19:22:55.553017 Version 6 (ocp_data = 5c30)
10072 19:22:55.553099
10073 19:22:55.556038 R8152: Done initializing
10074 19:22:55.556119
10075 19:22:55.556183 Adding net device
10076 19:22:57.414028
10077 19:22:57.414182 done.
10078 19:22:57.414279
10079 19:22:57.414370 MAC: 00:24:32:30:7c:7b
10080 19:22:57.414432
10081 19:22:57.417400 Sending DHCP discover... done.
10082 19:22:57.417484
10083 19:22:57.420322 Waiting for reply... done.
10084 19:22:57.420403
10085 19:22:57.424093 Sending DHCP request... done.
10086 19:22:57.424174
10087 19:22:57.428827 Waiting for reply... done.
10088 19:22:57.428912
10089 19:22:57.428977 My ip is 192.168.201.14
10090 19:22:57.429038
10091 19:22:57.431876 The DHCP server ip is 192.168.201.1
10092 19:22:57.432007
10093 19:22:57.438526 TFTP server IP predefined by user: 192.168.201.1
10094 19:22:57.438628
10095 19:22:57.445267 Bootfile predefined by user: 13420331/tftp-deploy-9vswnwe8/kernel/image.itb
10096 19:22:57.445374
10097 19:22:57.448319 Sending tftp read request... done.
10098 19:22:57.448427
10099 19:22:57.452560 Waiting for the transfer...
10100 19:22:57.452644
10101 19:22:57.973738 00000000 ################################################################
10102 19:22:57.973895
10103 19:22:58.493807 00080000 ################################################################
10104 19:22:58.493952
10105 19:22:59.011829 00100000 ################################################################
10106 19:22:59.011996
10107 19:22:59.532867 00180000 ################################################################
10108 19:22:59.533002
10109 19:23:00.088068 00200000 ################################################################
10110 19:23:00.088204
10111 19:23:00.651990 00280000 ################################################################
10112 19:23:00.652147
10113 19:23:01.242614 00300000 ################################################################
10114 19:23:01.242771
10115 19:23:01.825311 00380000 ################################################################
10116 19:23:01.825444
10117 19:23:02.420008 00400000 ################################################################
10118 19:23:02.420503
10119 19:23:03.046946 00480000 ################################################################
10120 19:23:03.047075
10121 19:23:03.635662 00500000 ################################################################
10122 19:23:03.635795
10123 19:23:04.199537 00580000 ################################################################
10124 19:23:04.199667
10125 19:23:04.770735 00600000 ################################################################
10126 19:23:04.770872
10127 19:23:05.305756 00680000 ################################################################
10128 19:23:05.305905
10129 19:23:05.858057 00700000 ################################################################
10130 19:23:05.858194
10131 19:23:06.450631 00780000 ################################################################
10132 19:23:06.450780
10133 19:23:07.048389 00800000 ################################################################
10134 19:23:07.048534
10135 19:23:07.623526 00880000 ################################################################
10136 19:23:07.623685
10137 19:23:08.256118 00900000 ################################################################
10138 19:23:08.256275
10139 19:23:08.850279 00980000 ################################################################
10140 19:23:08.850418
10141 19:23:09.431957 00a00000 ################################################################
10142 19:23:09.432103
10143 19:23:10.016885 00a80000 ################################################################
10144 19:23:10.017042
10145 19:23:10.616079 00b00000 ################################################################
10146 19:23:10.616230
10147 19:23:11.229126 00b80000 ################################################################
10148 19:23:11.229276
10149 19:23:11.831678 00c00000 ################################################################
10150 19:23:11.831821
10151 19:23:12.458742 00c80000 ################################################################
10152 19:23:12.458888
10153 19:23:13.039165 00d00000 ################################################################
10154 19:23:13.039311
10155 19:23:13.611129 00d80000 ################################################################
10156 19:23:13.611281
10157 19:23:14.158666 00e00000 ################################################################
10158 19:23:14.158800
10159 19:23:14.754852 00e80000 ################################################################
10160 19:23:14.754990
10161 19:23:15.370812 00f00000 ################################################################
10162 19:23:15.371310
10163 19:23:15.973927 00f80000 ################################################################
10164 19:23:15.974073
10165 19:23:16.547635 01000000 ################################################################
10166 19:23:16.547794
10167 19:23:17.134469 01080000 ################################################################
10168 19:23:17.134641
10169 19:23:17.774271 01100000 ################################################################
10170 19:23:17.774784
10171 19:23:18.404154 01180000 ################################################################
10172 19:23:18.404299
10173 19:23:19.018526 01200000 ################################################################
10174 19:23:19.018659
10175 19:23:19.614123 01280000 ################################################################
10176 19:23:19.614253
10177 19:23:20.196344 01300000 ################################################################
10178 19:23:20.196520
10179 19:23:20.769656 01380000 ################################################################
10180 19:23:20.769819
10181 19:23:21.327593 01400000 ################################################################
10182 19:23:21.327730
10183 19:23:21.889421 01480000 ################################################################
10184 19:23:21.889567
10185 19:23:22.459451 01500000 ################################################################
10186 19:23:22.459610
10187 19:23:23.035834 01580000 ################################################################
10188 19:23:23.036008
10189 19:23:23.619717 01600000 ################################################################
10190 19:23:23.619866
10191 19:23:24.205069 01680000 ################################################################
10192 19:23:24.205202
10193 19:23:24.797798 01700000 ################################################################
10194 19:23:24.797940
10195 19:23:25.392184 01780000 ################################################################
10196 19:23:25.392344
10197 19:23:25.982190 01800000 ################################################################
10198 19:23:25.982359
10199 19:23:26.525711 01880000 ################################################################
10200 19:23:26.525849
10201 19:23:27.074026 01900000 ################################################################
10202 19:23:27.074176
10203 19:23:27.625214 01980000 ################################################################
10204 19:23:27.625345
10205 19:23:28.172874 01a00000 ################################################################
10206 19:23:28.173009
10207 19:23:28.741156 01a80000 ################################################################
10208 19:23:28.741291
10209 19:23:29.313263 01b00000 ################################################################
10210 19:23:29.313395
10211 19:23:29.883233 01b80000 ################################################################
10212 19:23:29.883408
10213 19:23:30.423760 01c00000 ################################################################
10214 19:23:30.423960
10215 19:23:30.988778 01c80000 ################################################################
10216 19:23:30.988959
10217 19:23:31.541550 01d00000 ################################################################
10218 19:23:31.541705
10219 19:23:32.126821 01d80000 ################################################################
10220 19:23:32.126956
10221 19:23:32.453472 01e00000 ################################## done.
10222 19:23:32.454115
10223 19:23:32.456496 The bootfile was 31728874 bytes long.
10224 19:23:32.456936
10225 19:23:32.460182 Sending tftp read request... done.
10226 19:23:32.460640
10227 19:23:32.463216 Waiting for the transfer...
10228 19:23:32.463650
10229 19:23:32.466836 00000000 # done.
10230 19:23:32.467273
10231 19:23:32.473127 Command line loaded dynamically from TFTP file: 13420331/tftp-deploy-9vswnwe8/kernel/cmdline
10232 19:23:32.473575
10233 19:23:32.496175 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/13420331/extract-nfsrootfs-8q2m2gfc,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10234 19:23:32.496642
10235 19:23:32.497035 Loading FIT.
10236 19:23:32.497347
10237 19:23:32.499878 Image ramdisk-1 has 18769254 bytes.
10238 19:23:32.500359
10239 19:23:32.503419 Image fdt-1 has 47230 bytes.
10240 19:23:32.503834
10241 19:23:32.506245 Image kernel-1 has 12910355 bytes.
10242 19:23:32.506658
10243 19:23:32.512744 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10244 19:23:32.512825
10245 19:23:32.532447 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10246 19:23:32.532538
10247 19:23:32.536054 Choosing best match conf-1 for compat google,spherion-rev2.
10248 19:23:32.540754
10249 19:23:32.545377 Connected to device vid:did:rid of 1ae0:0028:00
10250 19:23:32.552465
10251 19:23:32.555675 tpm_get_response: command 0x17b, return code 0x0
10252 19:23:32.555812
10253 19:23:32.558747 ec_init: CrosEC protocol v3 supported (256, 248)
10254 19:23:32.562864
10255 19:23:32.565874 tpm_cleanup: add release locality here.
10256 19:23:32.566010
10257 19:23:32.566116 Shutting down all USB controllers.
10258 19:23:32.569225
10259 19:23:32.569301 Removing current net device
10260 19:23:32.569364
10261 19:23:32.576082 Exiting depthcharge with code 4 at timestamp: 70665966
10262 19:23:32.576159
10263 19:23:32.579558 LZMA decompressing kernel-1 to 0x821a6718
10264 19:23:32.579642
10265 19:23:32.582849 LZMA decompressing kernel-1 to 0x40000000
10266 19:23:34.178214
10267 19:23:34.178815 jumping to kernel
10268 19:23:34.180550 end: 2.2.4 bootloader-commands (duration 00:00:43) [common]
10269 19:23:34.181049 start: 2.2.5 auto-login-action (timeout 00:03:42) [common]
10270 19:23:34.181418 Setting prompt string to ['Linux version [0-9]']
10271 19:23:34.181753 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10272 19:23:34.182091 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10273 19:23:34.260857
10274 19:23:34.264255 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10275 19:23:34.268191 start: 2.2.5.1 login-action (timeout 00:03:42) [common]
10276 19:23:34.268648 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10277 19:23:34.269039 Setting prompt string to []
10278 19:23:34.269423 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10279 19:23:34.269778 Using line separator: #'\n'#
10280 19:23:34.270123 No login prompt set.
10281 19:23:34.270492 Parsing kernel messages
10282 19:23:34.270786 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10283 19:23:34.271338 [login-action] Waiting for messages, (timeout 00:03:42)
10284 19:23:34.271663 Waiting using forced prompt support (timeout 00:01:51)
10285 19:23:34.287352 [ 0.000000] Linux version 6.1.86-cip19 (KernelCI@build-j170728-arm64-gcc-10-defconfig-arm64-chromebook-wrkxq) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Apr 18 19:05:54 UTC 2024
10286 19:23:34.290789 [ 0.000000] random: crng init done
10287 19:23:34.297653 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10288 19:23:34.298153 [ 0.000000] efi: UEFI not found.
10289 19:23:34.307445 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10290 19:23:34.313880 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10291 19:23:34.324257 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10292 19:23:34.333977 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10293 19:23:34.340678 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10294 19:23:34.347499 [ 0.000000] printk: bootconsole [mtk8250] enabled
10295 19:23:34.350664 [ 0.000000] NUMA: No NUMA configuration found
10296 19:23:34.360783 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10297 19:23:34.363794 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10298 19:23:34.366606 [ 0.000000] Zone ranges:
10299 19:23:34.373377 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10300 19:23:34.376938 [ 0.000000] DMA32 empty
10301 19:23:34.383569 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10302 19:23:34.386802 [ 0.000000] Movable zone start for each node
10303 19:23:34.390098 [ 0.000000] Early memory node ranges
10304 19:23:34.396577 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10305 19:23:34.403498 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10306 19:23:34.410088 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10307 19:23:34.416899 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10308 19:23:34.419672 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10309 19:23:34.429744 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10310 19:23:34.484857 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10311 19:23:34.491481 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10312 19:23:34.498225 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10313 19:23:34.501396 [ 0.000000] psci: probing for conduit method from DT.
10314 19:23:34.508235 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10315 19:23:34.511310 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10316 19:23:34.517798 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10317 19:23:34.521380 [ 0.000000] psci: SMC Calling Convention v1.2
10318 19:23:34.528556 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10319 19:23:34.532058 [ 0.000000] Detected VIPT I-cache on CPU0
10320 19:23:34.538207 [ 0.000000] CPU features: detected: GIC system register CPU interface
10321 19:23:34.544854 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10322 19:23:34.551647 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10323 19:23:34.558592 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10324 19:23:34.564630 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10325 19:23:34.571130 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10326 19:23:34.578104 [ 0.000000] alternatives: applying boot alternatives
10327 19:23:34.581205 [ 0.000000] Fallback order for Node 0: 0
10328 19:23:34.591057 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10329 19:23:34.591552 [ 0.000000] Policy zone: Normal
10330 19:23:34.614663 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/13420331/extract-nfsrootfs-8q2m2gfc,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10331 19:23:34.627708 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10332 19:23:34.637932 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10333 19:23:34.648029 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10334 19:23:34.654523 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10335 19:23:34.657846 <6>[ 0.000000] software IO TLB: area num 8.
10336 19:23:34.714493 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10337 19:23:34.863115 <6>[ 0.000000] Memory: 7946244K/8385536K available (18048K kernel code, 4118K rwdata, 22288K rodata, 8448K init, 616K bss, 406524K reserved, 32768K cma-reserved)
10338 19:23:34.869588 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10339 19:23:34.876301 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10340 19:23:34.879760 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10341 19:23:34.886189 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10342 19:23:34.893180 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10343 19:23:34.895950 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10344 19:23:34.906106 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10345 19:23:34.913108 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10346 19:23:34.919388 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10347 19:23:34.926318 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10348 19:23:34.929326 <6>[ 0.000000] GICv3: 608 SPIs implemented
10349 19:23:34.932830 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10350 19:23:34.939370 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10351 19:23:34.942769 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10352 19:23:34.949176 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10353 19:23:34.962515 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10354 19:23:34.975457 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10355 19:23:34.982090 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10356 19:23:34.989910 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10357 19:23:35.003584 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10358 19:23:35.010268 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10359 19:23:35.016571 <6>[ 0.009235] Console: colour dummy device 80x25
10360 19:23:35.026786 <6>[ 0.013962] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10361 19:23:35.030623 <6>[ 0.024404] pid_max: default: 32768 minimum: 301
10362 19:23:35.036369 <6>[ 0.029276] LSM: Security Framework initializing
10363 19:23:35.043530 <6>[ 0.034213] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10364 19:23:35.053220 <6>[ 0.042027] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10365 19:23:35.059495 <6>[ 0.051448] cblist_init_generic: Setting adjustable number of callback queues.
10366 19:23:35.066467 <6>[ 0.058937] cblist_init_generic: Setting shift to 3 and lim to 1.
10367 19:23:35.076280 <6>[ 0.065276] cblist_init_generic: Setting adjustable number of callback queues.
10368 19:23:35.082642 <6>[ 0.072703] cblist_init_generic: Setting shift to 3 and lim to 1.
10369 19:23:35.086333 <6>[ 0.079104] rcu: Hierarchical SRCU implementation.
10370 19:23:35.092713 <6>[ 0.084150] rcu: Max phase no-delay instances is 1000.
10371 19:23:35.099056 <6>[ 0.091172] EFI services will not be available.
10372 19:23:35.102819 <6>[ 0.096157] smp: Bringing up secondary CPUs ...
10373 19:23:35.110750 <6>[ 0.101202] Detected VIPT I-cache on CPU1
10374 19:23:35.117623 <6>[ 0.101270] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10375 19:23:35.124542 <6>[ 0.101303] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10376 19:23:35.127188 <6>[ 0.101635] Detected VIPT I-cache on CPU2
10377 19:23:35.133823 <6>[ 0.101687] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10378 19:23:35.143990 <6>[ 0.101706] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10379 19:23:35.147375 <6>[ 0.101966] Detected VIPT I-cache on CPU3
10380 19:23:35.153623 <6>[ 0.102014] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10381 19:23:35.160172 <6>[ 0.102028] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10382 19:23:35.163601 <6>[ 0.102329] CPU features: detected: Spectre-v4
10383 19:23:35.170449 <6>[ 0.102335] CPU features: detected: Spectre-BHB
10384 19:23:35.173719 <6>[ 0.102340] Detected PIPT I-cache on CPU4
10385 19:23:35.180155 <6>[ 0.102399] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10386 19:23:35.186740 <6>[ 0.102416] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10387 19:23:35.193757 <6>[ 0.102711] Detected PIPT I-cache on CPU5
10388 19:23:35.199811 <6>[ 0.102775] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10389 19:23:35.206265 <6>[ 0.102791] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10390 19:23:35.209365 <6>[ 0.103069] Detected PIPT I-cache on CPU6
10391 19:23:35.216279 <6>[ 0.103135] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10392 19:23:35.223491 <6>[ 0.103151] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10393 19:23:35.229920 <6>[ 0.103447] Detected PIPT I-cache on CPU7
10394 19:23:35.236648 <6>[ 0.103515] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10395 19:23:35.243217 <6>[ 0.103531] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10396 19:23:35.246474 <6>[ 0.103578] smp: Brought up 1 node, 8 CPUs
10397 19:23:35.253281 <6>[ 0.244958] SMP: Total of 8 processors activated.
10398 19:23:35.256478 <6>[ 0.249910] CPU features: detected: 32-bit EL0 Support
10399 19:23:35.266700 <6>[ 0.255273] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10400 19:23:35.273356 <6>[ 0.264074] CPU features: detected: Common not Private translations
10401 19:23:35.280012 <6>[ 0.270590] CPU features: detected: CRC32 instructions
10402 19:23:35.283302 <6>[ 0.275941] CPU features: detected: RCpc load-acquire (LDAPR)
10403 19:23:35.289732 <6>[ 0.281938] CPU features: detected: LSE atomic instructions
10404 19:23:35.297034 <6>[ 0.287720] CPU features: detected: Privileged Access Never
10405 19:23:35.302952 <6>[ 0.293536] CPU features: detected: RAS Extension Support
10406 19:23:35.309551 <6>[ 0.299145] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10407 19:23:35.312963 <6>[ 0.306409] CPU: All CPU(s) started at EL2
10408 19:23:35.319766 <6>[ 0.310726] alternatives: applying system-wide alternatives
10409 19:23:35.328864 <6>[ 0.321543] devtmpfs: initialized
10410 19:23:35.340768 <6>[ 0.330476] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10411 19:23:35.351346 <6>[ 0.340441] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10412 19:23:35.357662 <6>[ 0.348564] pinctrl core: initialized pinctrl subsystem
10413 19:23:35.360698 <6>[ 0.355365] DMI not present or invalid.
10414 19:23:35.367682 <6>[ 0.359777] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10415 19:23:35.377548 <6>[ 0.366655] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10416 19:23:35.383988 <6>[ 0.374238] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10417 19:23:35.393947 <6>[ 0.382451] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10418 19:23:35.397637 <6>[ 0.390693] audit: initializing netlink subsys (disabled)
10419 19:23:35.407703 <5>[ 0.396389] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10420 19:23:35.414147 <6>[ 0.397129] thermal_sys: Registered thermal governor 'step_wise'
10421 19:23:35.420373 <6>[ 0.404357] thermal_sys: Registered thermal governor 'power_allocator'
10422 19:23:35.424382 <6>[ 0.410613] cpuidle: using governor menu
10423 19:23:35.430707 <6>[ 0.421571] NET: Registered PF_QIPCRTR protocol family
10424 19:23:35.437455 <6>[ 0.427072] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10425 19:23:35.440546 <6>[ 0.434175] ASID allocator initialised with 32768 entries
10426 19:23:35.447757 <6>[ 0.440788] Serial: AMBA PL011 UART driver
10427 19:23:35.456811 <4>[ 0.449852] Trying to register duplicate clock ID: 134
10428 19:23:35.513703 <6>[ 0.510099] KASLR enabled
10429 19:23:35.527789 <6>[ 0.517786] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10430 19:23:35.534760 <6>[ 0.524801] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10431 19:23:35.541216 <6>[ 0.531287] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10432 19:23:35.547852 <6>[ 0.538292] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10433 19:23:35.554580 <6>[ 0.544781] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10434 19:23:35.561191 <6>[ 0.551786] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10435 19:23:35.567947 <6>[ 0.558270] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10436 19:23:35.574143 <6>[ 0.565274] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10437 19:23:35.577937 <6>[ 0.572759] ACPI: Interpreter disabled.
10438 19:23:35.585916 <6>[ 0.579285] iommu: Default domain type: Translated
10439 19:23:35.592542 <6>[ 0.584402] iommu: DMA domain TLB invalidation policy: strict mode
10440 19:23:35.596017 <5>[ 0.591070] SCSI subsystem initialized
10441 19:23:35.603001 <6>[ 0.595337] usbcore: registered new interface driver usbfs
10442 19:23:35.609170 <6>[ 0.601067] usbcore: registered new interface driver hub
10443 19:23:35.612440 <6>[ 0.606618] usbcore: registered new device driver usb
10444 19:23:35.619358 <6>[ 0.612772] pps_core: LinuxPPS API ver. 1 registered
10445 19:23:35.629250 <6>[ 0.617962] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10446 19:23:35.632589 <6>[ 0.627303] PTP clock support registered
10447 19:23:35.636033 <6>[ 0.631548] EDAC MC: Ver: 3.0.0
10448 19:23:35.643320 <6>[ 0.636758] FPGA manager framework
10449 19:23:35.650369 <6>[ 0.640435] Advanced Linux Sound Architecture Driver Initialized.
10450 19:23:35.653639 <6>[ 0.647211] vgaarb: loaded
10451 19:23:35.660047 <6>[ 0.650322] clocksource: Switched to clocksource arch_sys_counter
10452 19:23:35.663475 <5>[ 0.656773] VFS: Disk quotas dquot_6.6.0
10453 19:23:35.670085 <6>[ 0.660962] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10454 19:23:35.673061 <6>[ 0.668155] pnp: PnP ACPI: disabled
10455 19:23:35.681402 <6>[ 0.674842] NET: Registered PF_INET protocol family
10456 19:23:35.691172 <6>[ 0.680437] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10457 19:23:35.702993 <6>[ 0.692776] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10458 19:23:35.713086 <6>[ 0.701593] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10459 19:23:35.719397 <6>[ 0.709562] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10460 19:23:35.729046 <6>[ 0.718265] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10461 19:23:35.735396 <6>[ 0.728025] TCP: Hash tables configured (established 65536 bind 65536)
10462 19:23:35.742442 <6>[ 0.734890] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10463 19:23:35.752335 <6>[ 0.742085] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10464 19:23:35.759384 <6>[ 0.749796] NET: Registered PF_UNIX/PF_LOCAL protocol family
10465 19:23:35.765730 <6>[ 0.755942] RPC: Registered named UNIX socket transport module.
10466 19:23:35.769385 <6>[ 0.762097] RPC: Registered udp transport module.
10467 19:23:35.775721 <6>[ 0.767031] RPC: Registered tcp transport module.
10468 19:23:35.781839 <6>[ 0.771963] RPC: Registered tcp NFSv4.1 backchannel transport module.
10469 19:23:35.785162 <6>[ 0.778627] PCI: CLS 0 bytes, default 64
10470 19:23:35.788750 <6>[ 0.782967] Unpacking initramfs...
10471 19:23:35.798516 <6>[ 0.786738] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10472 19:23:35.805055 <6>[ 0.795362] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10473 19:23:35.811584 <6>[ 0.804174] kvm [1]: IPA Size Limit: 40 bits
10474 19:23:35.814977 <6>[ 0.808697] kvm [1]: GICv3: no GICV resource entry
10475 19:23:35.821358 <6>[ 0.813716] kvm [1]: disabling GICv2 emulation
10476 19:23:35.828237 <6>[ 0.818401] kvm [1]: GIC system register CPU interface enabled
10477 19:23:35.831357 <6>[ 0.824566] kvm [1]: vgic interrupt IRQ18
10478 19:23:35.838100 <6>[ 0.830408] kvm [1]: VHE mode initialized successfully
10479 19:23:35.844538 <5>[ 0.836831] Initialise system trusted keyrings
10480 19:23:35.850851 <6>[ 0.841628] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10481 19:23:35.858633 <6>[ 0.851661] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10482 19:23:35.865270 <5>[ 0.858031] NFS: Registering the id_resolver key type
10483 19:23:35.868482 <5>[ 0.863332] Key type id_resolver registered
10484 19:23:35.875271 <5>[ 0.867744] Key type id_legacy registered
10485 19:23:35.881940 <6>[ 0.872033] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10486 19:23:35.889049 <6>[ 0.878955] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10487 19:23:35.894862 <6>[ 0.886664] 9p: Installing v9fs 9p2000 file system support
10488 19:23:35.931374 <5>[ 0.924185] Key type asymmetric registered
10489 19:23:35.934816 <5>[ 0.928513] Asymmetric key parser 'x509' registered
10490 19:23:35.944308 <6>[ 0.933652] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10491 19:23:35.947786 <6>[ 0.941267] io scheduler mq-deadline registered
10492 19:23:35.951146 <6>[ 0.946027] io scheduler kyber registered
10493 19:23:35.970635 <6>[ 0.963377] EINJ: ACPI disabled.
10494 19:23:36.003445 <4>[ 0.989491] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10495 19:23:36.012856 <4>[ 1.000105] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10496 19:23:36.027868 <6>[ 1.020947] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10497 19:23:36.035709 <6>[ 1.028946] printk: console [ttyS0] disabled
10498 19:23:36.064004 <6>[ 1.053571] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10499 19:23:36.070607 <6>[ 1.063042] printk: console [ttyS0] enabled
10500 19:23:36.073968 <6>[ 1.063042] printk: console [ttyS0] enabled
10501 19:23:36.080484 <6>[ 1.071936] printk: bootconsole [mtk8250] disabled
10502 19:23:36.084038 <6>[ 1.071936] printk: bootconsole [mtk8250] disabled
10503 19:23:36.090739 <6>[ 1.082995] SuperH (H)SCI(F) driver initialized
10504 19:23:36.093680 <6>[ 1.088288] msm_serial: driver initialized
10505 19:23:36.107458 <6>[ 1.097297] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10506 19:23:36.117009 <6>[ 1.105847] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10507 19:23:36.123919 <6>[ 1.114392] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10508 19:23:36.133525 <6>[ 1.123020] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10509 19:23:36.143210 <6>[ 1.131728] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10510 19:23:36.150032 <6>[ 1.140448] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10511 19:23:36.160116 <6>[ 1.148988] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10512 19:23:36.166531 <6>[ 1.157786] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10513 19:23:36.176314 <6>[ 1.166331] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10514 19:23:36.188793 <6>[ 1.182151] loop: module loaded
10515 19:23:36.195184 <6>[ 1.187904] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10516 19:23:36.218073 <4>[ 1.211275] mtk-pmic-keys: Failed to locate of_node [id: -1]
10517 19:23:36.224863 <6>[ 1.218075] megasas: 07.719.03.00-rc1
10518 19:23:36.234595 <6>[ 1.227680] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10519 19:23:36.241367 <6>[ 1.233735] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10520 19:23:36.256428 <6>[ 1.249720] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10521 19:23:36.312105 <6>[ 1.298867] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10522 19:23:36.587303 <6>[ 1.580544] Freeing initrd memory: 18324K
10523 19:23:36.598851 <6>[ 1.592063] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10524 19:23:36.610275 <6>[ 1.603330] tun: Universal TUN/TAP device driver, 1.6
10525 19:23:36.613155 <6>[ 1.609429] thunder_xcv, ver 1.0
10526 19:23:36.616649 <6>[ 1.612937] thunder_bgx, ver 1.0
10527 19:23:36.619815 <6>[ 1.616436] nicpf, ver 1.0
10528 19:23:36.630536 <6>[ 1.620512] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10529 19:23:36.633884 <6>[ 1.627988] hns3: Copyright (c) 2017 Huawei Corporation.
10530 19:23:36.640291 <6>[ 1.633579] hclge is initializing
10531 19:23:36.643697 <6>[ 1.637158] e1000: Intel(R) PRO/1000 Network Driver
10532 19:23:36.650111 <6>[ 1.642287] e1000: Copyright (c) 1999-2006 Intel Corporation.
10533 19:23:36.653865 <6>[ 1.648304] e1000e: Intel(R) PRO/1000 Network Driver
10534 19:23:36.660339 <6>[ 1.653520] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10535 19:23:36.667104 <6>[ 1.659706] igb: Intel(R) Gigabit Ethernet Network Driver
10536 19:23:36.673699 <6>[ 1.665356] igb: Copyright (c) 2007-2014 Intel Corporation.
10537 19:23:36.680160 <6>[ 1.671195] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10538 19:23:36.686505 <6>[ 1.677714] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10539 19:23:36.690837 <6>[ 1.684185] sky2: driver version 1.30
10540 19:23:36.696465 <6>[ 1.689218] VFIO - User Level meta-driver version: 0.3
10541 19:23:36.704128 <6>[ 1.697515] usbcore: registered new interface driver usb-storage
10542 19:23:36.711010 <6>[ 1.703972] usbcore: registered new device driver onboard-usb-hub
10543 19:23:36.719612 <6>[ 1.713216] mt6397-rtc mt6359-rtc: registered as rtc0
10544 19:23:36.729893 <6>[ 1.718681] mt6397-rtc mt6359-rtc: setting system clock to 2024-04-18T19:23:35 UTC (1713468215)
10545 19:23:36.733070 <6>[ 1.728266] i2c_dev: i2c /dev entries driver
10546 19:23:36.750215 <6>[ 1.740318] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10547 19:23:36.756810 <4>[ 1.749058] cpu cpu0: supply cpu not found, using dummy regulator
10548 19:23:36.763276 <4>[ 1.755480] cpu cpu1: supply cpu not found, using dummy regulator
10549 19:23:36.770210 <4>[ 1.761889] cpu cpu2: supply cpu not found, using dummy regulator
10550 19:23:36.776939 <4>[ 1.768308] cpu cpu3: supply cpu not found, using dummy regulator
10551 19:23:36.783567 <4>[ 1.774708] cpu cpu4: supply cpu not found, using dummy regulator
10552 19:23:36.789761 <4>[ 1.781106] cpu cpu5: supply cpu not found, using dummy regulator
10553 19:23:36.796624 <4>[ 1.787501] cpu cpu6: supply cpu not found, using dummy regulator
10554 19:23:36.803334 <4>[ 1.793906] cpu cpu7: supply cpu not found, using dummy regulator
10555 19:23:36.821540 <6>[ 1.814566] cpu cpu0: EM: created perf domain
10556 19:23:36.825207 <6>[ 1.819499] cpu cpu4: EM: created perf domain
10557 19:23:36.832392 <6>[ 1.825133] sdhci: Secure Digital Host Controller Interface driver
10558 19:23:36.838898 <6>[ 1.831565] sdhci: Copyright(c) Pierre Ossman
10559 19:23:36.845250 <6>[ 1.836555] Synopsys Designware Multimedia Card Interface Driver
10560 19:23:36.852501 <6>[ 1.843202] sdhci-pltfm: SDHCI platform and OF driver helper
10561 19:23:36.855386 <6>[ 1.843242] mmc0: CQHCI version 5.10
10562 19:23:36.861731 <6>[ 1.853372] ledtrig-cpu: registered to indicate activity on CPUs
10563 19:23:36.868745 <6>[ 1.860508] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10564 19:23:36.875666 <6>[ 1.867570] usbcore: registered new interface driver usbhid
10565 19:23:36.878874 <6>[ 1.873394] usbhid: USB HID core driver
10566 19:23:36.885470 <6>[ 1.877602] spi_master spi0: will run message pump with realtime priority
10567 19:23:36.932834 <6>[ 1.918921] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10568 19:23:36.951855 <6>[ 1.934567] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10569 19:23:36.959038 <6>[ 1.949857] cros-ec-spi spi0.0: Chrome EC device registered
10570 19:23:36.962049 <6>[ 1.955946] mmc0: Command Queue Engine enabled
10571 19:23:36.968614 <6>[ 1.960719] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10572 19:23:36.975528 <6>[ 1.968058] mmcblk0: mmc0:0001 DA4128 116 GiB
10573 19:23:36.985800 <6>[ 1.970586] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10574 19:23:36.988674 <6>[ 1.979412] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10575 19:23:36.995528 <6>[ 1.983219] NET: Registered PF_PACKET protocol family
10576 19:23:37.001610 <6>[ 1.989293] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10577 19:23:37.005116 <6>[ 1.993357] 9pnet: Installing 9P2000 support
10578 19:23:37.011710 <6>[ 1.999156] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10579 19:23:37.015072 <5>[ 2.003058] Key type dns_resolver registered
10580 19:23:37.021958 <6>[ 2.008850] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10581 19:23:37.024902 <6>[ 2.013309] registered taskstats version 1
10582 19:23:37.031312 <5>[ 2.023668] Loading compiled-in X.509 certificates
10583 19:23:37.062084 <4>[ 2.048560] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10584 19:23:37.072398 <4>[ 2.059277] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10585 19:23:37.078679 <3>[ 2.069815] debugfs: File 'uA_load' in directory '/' already present!
10586 19:23:37.085325 <3>[ 2.076519] debugfs: File 'min_uV' in directory '/' already present!
10587 19:23:37.091937 <3>[ 2.083186] debugfs: File 'max_uV' in directory '/' already present!
10588 19:23:37.097806 <3>[ 2.089799] debugfs: File 'constraint_flags' in directory '/' already present!
10589 19:23:37.109581 <3>[ 2.099687] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10590 19:23:37.121590 <6>[ 2.115264] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10591 19:23:37.128741 <6>[ 2.122089] xhci-mtk 11200000.usb: xHCI Host Controller
10592 19:23:37.135045 <6>[ 2.127593] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10593 19:23:37.145290 <6>[ 2.135470] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10594 19:23:37.152050 <6>[ 2.144918] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10595 19:23:37.159094 <6>[ 2.151025] xhci-mtk 11200000.usb: xHCI Host Controller
10596 19:23:37.164981 <6>[ 2.156651] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10597 19:23:37.171811 <6>[ 2.164341] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10598 19:23:37.178873 <6>[ 2.172229] hub 1-0:1.0: USB hub found
10599 19:23:37.182074 <6>[ 2.176255] hub 1-0:1.0: 1 port detected
10600 19:23:37.192322 <6>[ 2.180553] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10601 19:23:37.195305 <6>[ 2.189341] hub 2-0:1.0: USB hub found
10602 19:23:37.198919 <6>[ 2.193367] hub 2-0:1.0: 1 port detected
10603 19:23:37.208008 <6>[ 2.201587] mtk-msdc 11f70000.mmc: Got CD GPIO
10604 19:23:37.220168 <6>[ 2.210241] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10605 19:23:37.226636 <6>[ 2.218270] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10606 19:23:37.236832 <4>[ 2.226219] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10607 19:23:37.247008 <6>[ 2.235758] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10608 19:23:37.253287 <6>[ 2.243836] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10609 19:23:37.260227 <6>[ 2.251846] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10610 19:23:37.270044 <6>[ 2.259768] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10611 19:23:37.276514 <6>[ 2.267590] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10612 19:23:37.286158 <6>[ 2.275407] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10613 19:23:37.296463 <6>[ 2.285792] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10614 19:23:37.302705 <6>[ 2.294149] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10615 19:23:37.312974 <6>[ 2.302501] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10616 19:23:37.319444 <6>[ 2.310840] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10617 19:23:37.329114 <6>[ 2.319178] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10618 19:23:37.336061 <6>[ 2.327515] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10619 19:23:37.345795 <6>[ 2.335852] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10620 19:23:37.356126 <6>[ 2.344189] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10621 19:23:37.362128 <6>[ 2.352527] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10622 19:23:37.372170 <6>[ 2.360866] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10623 19:23:37.378607 <6>[ 2.369203] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10624 19:23:37.388650 <6>[ 2.377545] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10625 19:23:37.395212 <6>[ 2.385883] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10626 19:23:37.405074 <6>[ 2.394222] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10627 19:23:37.411657 <6>[ 2.402559] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10628 19:23:37.418392 <6>[ 2.411283] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10629 19:23:37.425313 <6>[ 2.418458] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10630 19:23:37.431732 <6>[ 2.425228] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10631 19:23:37.441927 <6>[ 2.432001] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10632 19:23:37.448326 <6>[ 2.438928] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10633 19:23:37.455108 <6>[ 2.445790] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10634 19:23:37.465342 <6>[ 2.454932] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10635 19:23:37.474808 <6>[ 2.464051] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10636 19:23:37.484979 <6>[ 2.473344] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10637 19:23:37.494538 <6>[ 2.482818] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10638 19:23:37.504818 <6>[ 2.492286] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10639 19:23:37.511096 <6>[ 2.501405] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10640 19:23:37.522104 <6>[ 2.510872] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10641 19:23:37.531305 <6>[ 2.519990] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10642 19:23:37.540995 <6>[ 2.529285] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10643 19:23:37.550623 <6>[ 2.539446] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10644 19:23:37.561588 <6>[ 2.551325] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10645 19:23:37.567661 <6>[ 2.560805] Trying to probe devices needed for running init ...
10646 19:23:37.608156 <6>[ 2.598600] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10647 19:23:37.763223 <6>[ 2.756545] hub 1-1:1.0: USB hub found
10648 19:23:37.766132 <6>[ 2.761054] hub 1-1:1.0: 4 ports detected
10649 19:23:37.776109 <6>[ 2.769799] hub 1-1:1.0: USB hub found
10650 19:23:37.779844 <6>[ 2.774178] hub 1-1:1.0: 4 ports detected
10651 19:23:37.888702 <6>[ 2.878943] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10652 19:23:37.914951 <6>[ 2.908447] hub 2-1:1.0: USB hub found
10653 19:23:37.918321 <6>[ 2.912943] hub 2-1:1.0: 3 ports detected
10654 19:23:37.927034 <6>[ 2.920767] hub 2-1:1.0: USB hub found
10655 19:23:37.930468 <6>[ 2.925210] hub 2-1:1.0: 3 ports detected
10656 19:23:38.104524 <6>[ 3.094450] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10657 19:23:38.236966 <6>[ 3.230197] hub 1-1.4:1.0: USB hub found
10658 19:23:38.240327 <6>[ 3.234840] hub 1-1.4:1.0: 2 ports detected
10659 19:23:38.250188 <6>[ 3.243122] hub 1-1.4:1.0: USB hub found
10660 19:23:38.253281 <6>[ 3.247725] hub 1-1.4:1.0: 2 ports detected
10661 19:23:38.320773 <6>[ 3.310822] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10662 19:23:38.548717 <6>[ 3.538622] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10663 19:23:38.740627 <6>[ 3.730608] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10664 19:23:49.866053 <6>[ 14.863837] ALSA device list:
10665 19:23:49.872430 <6>[ 14.867305] No soundcards found.
10666 19:23:49.880075 <6>[ 14.874569] Freeing unused kernel memory: 8448K
10667 19:23:49.883112 <6>[ 14.879520] Run /init as init process
10668 19:23:49.892430 Loading, please wait...
10669 19:23:49.917720 Starting systemd-udevd version 252.22-1~deb12u1
10670 19:23:49.917853
10671 19:23:50.204765 <6>[ 15.196514] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10672 19:23:50.214195 <6>[ 15.209290] remoteproc remoteproc0: scp is available
10673 19:23:50.221120 <6>[ 15.210808] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10674 19:23:50.227774 <6>[ 15.215830] remoteproc remoteproc0: powering up scp
10675 19:23:50.237613 <6>[ 15.222840] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10676 19:23:50.244078 <6>[ 15.227393] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10677 19:23:50.250660 <6>[ 15.230587] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10678 19:23:50.260789 <3>[ 15.230819] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10679 19:23:50.267650 <3>[ 15.230847] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10680 19:23:50.277224 <3>[ 15.230856] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10681 19:23:50.284074 <6>[ 15.236805] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10682 19:23:50.293675 <3>[ 15.237659] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10683 19:23:50.300294 <3>[ 15.237674] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10684 19:23:50.310373 <3>[ 15.237678] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10685 19:23:50.316409 <3>[ 15.237686] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10686 19:23:50.326404 <3>[ 15.237690] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10687 19:23:50.333202 <3>[ 15.237770] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10688 19:23:50.343453 <3>[ 15.237814] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10689 19:23:50.349672 <3>[ 15.237817] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10690 19:23:50.359335 <3>[ 15.237820] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10691 19:23:50.366520 <3>[ 15.237847] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10692 19:23:50.376678 <3>[ 15.237851] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10693 19:23:50.383320 <3>[ 15.237854] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10694 19:23:50.389094 <3>[ 15.237857] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10695 19:23:50.399452 <3>[ 15.237859] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10696 19:23:50.405972 <3>[ 15.237873] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10697 19:23:50.412550 <6>[ 15.244473] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10698 19:23:50.415535 <6>[ 15.291444] mc: Linux media interface: v0.10
10699 19:23:50.425431 <4>[ 15.291849] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10700 19:23:50.432096 <4>[ 15.292061] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10701 19:23:50.438538 <6>[ 15.302668] usbcore: registered new device driver r8152-cfgselector
10702 19:23:50.445439 <4>[ 15.316075] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10703 19:23:50.451790 <4>[ 15.316075] Fallback method does not support PEC.
10704 19:23:50.458949 <6>[ 15.370045] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10705 19:23:50.468538 <6>[ 15.374707] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10706 19:23:50.475460 <6>[ 15.392631] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10707 19:23:50.482309 <6>[ 15.398762] remoteproc remoteproc0: remote processor scp is now up
10708 19:23:50.492009 <6>[ 15.402794] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10709 19:23:50.498278 <6>[ 15.406737] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10710 19:23:50.508860 <6>[ 15.408962] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10711 19:23:50.515209 <6>[ 15.411805] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10712 19:23:50.521829 <6>[ 15.411812] pci_bus 0000:00: root bus resource [bus 00-ff]
10713 19:23:50.528169 <6>[ 15.411819] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10714 19:23:50.538181 <6>[ 15.411824] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10715 19:23:50.544895 <6>[ 15.411857] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10716 19:23:50.551521 <6>[ 15.411877] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10717 19:23:50.554904 <6>[ 15.411955] pci 0000:00:00.0: supports D1 D2
10718 19:23:50.562116 <6>[ 15.411958] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10719 19:23:50.572306 <6>[ 15.413537] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10720 19:23:50.582199 <6>[ 15.551737] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10721 19:23:50.589325 <6>[ 15.556400] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10722 19:23:50.595541 <4>[ 15.559799] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10723 19:23:50.605465 <4>[ 15.559819] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10724 19:23:50.615696 <6>[ 15.563645] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10725 19:23:50.622230 <3>[ 15.565471] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10726 19:23:50.628529 <6>[ 15.571286] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10727 19:23:50.638652 <3>[ 15.589350] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10728 19:23:50.645378 <6>[ 15.597359] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10729 19:23:50.651619 <6>[ 15.597545] videodev: Linux video capture interface: v2.00
10730 19:23:50.655229 <6>[ 15.618522] r8152 2-1.3:1.0 eth0: v1.12.13
10731 19:23:50.664783 <6>[ 15.622633] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10732 19:23:50.668343 <6>[ 15.623167] Bluetooth: Core ver 2.22
10733 19:23:50.674668 <6>[ 15.623235] NET: Registered PF_BLUETOOTH protocol family
10734 19:23:50.681699 <6>[ 15.623236] Bluetooth: HCI device and connection manager initialized
10735 19:23:50.684979 <6>[ 15.623251] Bluetooth: HCI socket layer initialized
10736 19:23:50.691457 <6>[ 15.623256] Bluetooth: L2CAP socket layer initialized
10737 19:23:50.694984 <6>[ 15.623265] Bluetooth: SCO socket layer initialized
10738 19:23:50.701512 <6>[ 15.630879] usbcore: registered new interface driver r8152
10739 19:23:50.704636 <6>[ 15.638969] pci 0000:01:00.0: supports D1 D2
10740 19:23:50.711256 <6>[ 15.653337] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10741 19:23:50.721188 <6>[ 15.656407] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10742 19:23:50.724372 <6>[ 15.664206] usbcore: registered new interface driver cdc_ether
10743 19:23:50.731307 <6>[ 15.664536] usbcore: registered new interface driver btusb
10744 19:23:50.741075 <4>[ 15.665269] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10745 19:23:50.747407 <3>[ 15.665285] Bluetooth: hci0: Failed to load firmware file (-2)
10746 19:23:50.754001 <3>[ 15.665290] Bluetooth: hci0: Failed to set up firmware (-2)
10747 19:23:50.764211 <4>[ 15.665298] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10748 19:23:50.777082 <6>[ 15.668846] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10749 19:23:50.784234 <6>[ 15.670462] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10750 19:23:50.790291 <6>[ 15.670492] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10751 19:23:50.800472 <6>[ 15.670496] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10752 19:23:50.807384 <6>[ 15.670503] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10753 19:23:50.816905 <6>[ 15.670516] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10754 19:23:50.823588 <6>[ 15.670529] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10755 19:23:50.830271 <6>[ 15.670541] pci 0000:00:00.0: PCI bridge to [bus 01]
10756 19:23:50.837070 <6>[ 15.670546] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10757 19:23:50.843791 <6>[ 15.670685] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10758 19:23:50.850438 <6>[ 15.671127] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10759 19:23:50.856884 <6>[ 15.671550] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10760 19:23:50.863125 <6>[ 15.675602] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10761 19:23:50.866242 <6>[ 15.680238] usbcore: registered new interface driver uvcvideo
10762 19:23:50.873515 <6>[ 15.680247] usbcore: registered new interface driver r8153_ecm
10763 19:23:50.882842 <5>[ 15.687269] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10764 19:23:50.886458 <6>[ 15.689184] r8152 2-1.3:1.0 enx002432307c7b: renamed from eth0
10765 19:23:50.910019 <5>[ 15.901761] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10766 19:23:50.916930 <5>[ 15.908830] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10767 19:23:50.926319 <4>[ 15.917241] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10768 19:23:50.930219 <6>[ 15.926114] cfg80211: failed to load regulatory.db
10769 19:23:50.971286 <6>[ 15.963074] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10770 19:23:50.977904 <6>[ 15.970610] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10771 19:23:51.002250 <6>[ 15.997257] mt7921e 0000:01:00.0: ASIC revision: 79610010
10772 19:23:51.106151 <6>[ 16.097974] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10773 19:23:51.109281 <6>[ 16.097974]
10774 19:23:51.120552 Begin: Loading essential drivers ... done.
10775 19:23:51.123785 Begin: Running /scripts/init-premount ... done.
10776 19:23:51.130534 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10777 19:23:51.140817 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10778 19:23:51.143421 Device /sys/class/net/enx002432307c7b found
10779 19:23:51.143520 done.
10780 19:23:51.167637 Begin: Waiting up to 180 secs for any network device to become available ... done.
10781 19:23:51.219204 IP-Config: enx002432307c7b hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10782 19:23:51.378453 <6>[ 16.370240] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10783 19:23:52.171795 <6>[ 17.166988] r8152 2-1.3:1.0 enx002432307c7b: carrier on
10784 19:23:52.224015 IP-Config: no response after 2 secs - giving up
10785 19:23:52.230367 IP-Config: enx002432307c7b hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10786 19:23:52.247767 <6>[ 17.242688] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10787 19:23:52.279896 /sys/class/net/wlan0/flags: No such file or directory
10788 19:23:53.409821 IP-Config: enx002432307c7b complete (dhcp from 192.168.201.1):
10789 19:23:53.416274 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10790 19:23:53.426242 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10791 19:23:53.432727 host : mt8192-asurada-spherion-r0-cbg-2
10792 19:23:53.439528 domain : lava-rack
10793 19:23:53.442775 rootserver: 192.168.201.1 rootpath:
10794 19:23:53.442863 filename :
10795 19:23:53.524987 done.
10796 19:23:53.531756 Begin: Running /scripts/nfs-bottom ... done.
10797 19:23:53.545454 Begin: Running /scripts/init-bottom ... done.
10798 19:23:54.895362 <6>[ 19.890421] NET: Registered PF_INET6 protocol family
10799 19:23:54.902092 <6>[ 19.897424] Segment Routing with IPv6
10800 19:23:54.905519 <6>[ 19.901405] In-situ OAM (IOAM) with IPv6
10801 19:23:55.070257 <30>[ 20.039114] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10802 19:23:55.077844 <30>[ 20.072962] systemd[1]: Detected architecture arm64.
10803 19:23:55.095478
10804 19:23:55.099032 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10805 19:23:55.099149
10806 19:23:55.099215
10807 19:23:55.120895 <30>[ 20.116152] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10808 19:23:56.221672 <30>[ 21.213925] systemd[1]: Queued start job for default target graphical.target.
10809 19:23:56.264116 <30>[ 21.255805] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10810 19:23:56.270155 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10811 19:23:56.270313
10812 19:23:56.292170 <30>[ 21.284409] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10813 19:23:56.302143 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10814 19:23:56.302283
10815 19:23:56.320356 <30>[ 21.312373] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10816 19:23:56.329976 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10817 19:23:56.330115
10818 19:23:56.347634 <30>[ 21.339988] systemd[1]: Created slice user.slice - User and Session Slice.
10819 19:23:56.354349 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10820 19:23:56.354469
10821 19:23:56.378493 <30>[ 21.367500] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10822 19:23:56.388242 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10823 19:23:56.388385
10824 19:23:56.405728 <30>[ 21.394856] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10825 19:23:56.412758 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10826 19:23:56.412891
10827 19:23:56.441152 <30>[ 21.423294] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10828 19:23:56.450854 <30>[ 21.443188] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10829 19:23:56.457414 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10830 19:23:56.457536
10831 19:23:56.474538 <30>[ 21.466682] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10832 19:23:56.480962 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10833 19:23:56.481089
10834 19:23:56.498814 <30>[ 21.490670] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10835 19:23:56.508251 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10836 19:23:56.508390
10837 19:23:56.523355 <30>[ 21.518751] systemd[1]: Reached target paths.target - Path Units.
10838 19:23:56.529952 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10839 19:23:56.530074
10840 19:23:56.550729 <30>[ 21.543084] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10841 19:23:56.557397 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10842 19:23:56.557564
10843 19:23:56.571377 <30>[ 21.566602] systemd[1]: Reached target slices.target - Slice Units.
10844 19:23:56.580811 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10845 19:23:56.580982
10846 19:23:56.595823 <30>[ 21.591125] systemd[1]: Reached target swap.target - Swaps.
10847 19:23:56.602352 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10848 19:23:56.602507
10849 19:23:56.622869 <30>[ 21.615151] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10850 19:23:56.632979 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10851 19:23:56.633165
10852 19:23:56.651522 <30>[ 21.643608] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10853 19:23:56.661430 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10854 19:23:56.661608
10855 19:23:56.682147 <30>[ 21.673866] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10856 19:23:56.691680 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10857 19:23:56.691832
10858 19:23:56.707872 <30>[ 21.700041] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10859 19:23:56.717640 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10860 19:23:56.717817
10861 19:23:56.735190 <30>[ 21.727273] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10862 19:23:56.741862 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10863 19:23:56.742017
10864 19:23:56.759839 <30>[ 21.752150] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10865 19:23:56.769872 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10866 19:23:56.770053
10867 19:23:56.789235 <30>[ 21.781564] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10868 19:23:56.799235 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10869 19:23:56.799417
10870 19:23:56.814750 <30>[ 21.807118] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10871 19:23:56.824804 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10872 19:23:56.824993
10873 19:23:56.882643 <30>[ 21.874851] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10874 19:23:56.889260 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10875 19:23:56.889425
10876 19:23:56.910965 <30>[ 21.903207] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10877 19:23:56.917334 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10878 19:23:56.917497
10879 19:23:56.942901 <30>[ 21.934840] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10880 19:23:56.949131 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10881 19:23:56.949297
10882 19:23:56.973252 <30>[ 21.959014] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10883 19:23:56.988358 <30>[ 21.980318] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10884 19:23:56.998031 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10885 19:23:56.998204
10886 19:23:57.018115 <30>[ 22.010703] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10887 19:23:57.025132 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10888 19:23:57.025272
10889 19:23:57.052069 <30>[ 22.044262] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10890 19:23:57.058672 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10891 19:23:57.058839
10892 19:23:57.083714 <30>[ 22.076134] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10893 19:23:57.096841 Starting [0;1;39mmodprobe@drm.service<6>[ 22.087378] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10894 19:23:57.100177 [0m - Load Kernel Module drm...
10895 19:23:57.100318
10896 19:23:57.123807 <30>[ 22.116069] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10897 19:23:57.133599 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10898 19:23:57.133781
10899 19:23:57.166997 <30>[ 22.159306] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10900 19:23:57.173673 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10901 19:23:57.173858
10902 19:23:57.200059 <30>[ 22.192497] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10903 19:23:57.210207 Starting [0;1;39mmodprobe@loop.ser…e<6>[ 22.203769] fuse: init (API version 7.37)
10904 19:23:57.210393 [0m - Load Kernel Module loop...
10905 19:23:57.213339
10906 19:23:57.240343 <30>[ 22.232383] systemd[1]: Starting systemd-journald.service - Journal Service...
10907 19:23:57.246425 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10908 19:23:57.246594
10909 19:23:57.279380 <30>[ 22.271584] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10910 19:23:57.285814 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10911 19:23:57.285980
10912 19:23:57.315870 <30>[ 22.304997] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10913 19:23:57.322723 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10914 19:23:57.322879
10915 19:23:57.348017 <30>[ 22.340035] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10916 19:23:57.357779 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10917 19:23:57.357958
10918 19:23:57.384523 <30>[ 22.377075] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10919 19:23:57.394306 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10920 19:23:57.394485
10921 19:23:57.425160 <30>[ 22.417447] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10922 19:23:57.431568 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10923 19:23:57.431727
10924 19:23:57.451674 <30>[ 22.443842] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10925 19:23:57.458428 <3>[ 22.451446] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10926 19:23:57.468893 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10927 19:23:57.469036
10928 19:23:57.487270 <30>[ 22.478911] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10929 19:23:57.493405 <3>[ 22.481163] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10930 19:23:57.503833 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10931 19:23:57.504052
10932 19:23:57.523059 <30>[ 22.515470] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10933 19:23:57.533385 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10934 19:23:57.533578
10935 19:23:57.540435 <3>[ 22.533139] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10936 19:23:57.551658 <30>[ 22.544118] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10937 19:23:57.558860 <30>[ 22.552388] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10938 19:23:57.572425 [[0;32m OK [0m] Finished [0<3>[ 22.563017] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10939 19:23:57.575804 ;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10940 19:23:57.578765
10941 19:23:57.596560 <30>[ 22.587634] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10942 19:23:57.603104 <30>[ 22.595488] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10943 19:23:57.612867 <3>[ 22.597082] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10944 19:23:57.619394 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10945 19:23:57.619554
10946 19:23:57.640349 <30>[ 22.632244] systemd[1]: modprobe@drm.service: Deactivated successfully.
10947 19:23:57.647308 <3>[ 22.635970] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10948 19:23:57.656860 <30>[ 22.640089] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10949 19:23:57.662981 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10950 19:23:57.663128
10951 19:23:57.679322 <3>[ 22.671811] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10952 19:23:57.690552 <30>[ 22.682692] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10953 19:23:57.701042 <30>[ 22.691595] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10954 19:23:57.711162 [[0;32m OK [0m] Finished [0<3>[ 22.702713] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10955 19:23:57.717599 ;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10956 19:23:57.717758
10957 19:23:57.736975 <30>[ 22.728932] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10958 19:23:57.743638 <30>[ 22.737460] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10959 19:23:57.753524 <3>[ 22.742627] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10960 19:23:57.760057 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10961 19:23:57.763531
10962 19:23:57.778009 <30>[ 22.772744] systemd[1]: modprobe@loop.service: Deactivated successfully.
10963 19:23:57.787597 <3>[ 22.779256] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10964 19:23:57.794038 <30>[ 22.780793] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
10965 19:23:57.804702 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10966 19:23:57.804882
10967 19:23:57.824983 <30>[ 22.816765] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.
10968 19:23:57.848535 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Ker<4>[ 22.831494] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10969 19:23:57.855543 <3>[ 22.847619] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10970 19:23:57.855713 nel Modules.
10971 19:23:57.855817
10972 19:23:57.883493 <30>[ 22.871749] systemd[1]: Finished systemd-network-generator.service - Generate network units from Kernel command line.
10973 19:23:57.890134 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10974 19:23:57.890291
10975 19:23:57.911028 <30>[ 22.903559] systemd[1]: Started systemd-journald.service - Journal Service.
10976 19:23:57.917406 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10977 19:23:57.917557
10978 19:23:57.938795 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10979 19:23:57.938995
10980 19:23:57.955477 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10981 19:23:57.955662
10982 19:23:57.977197 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10983 19:23:57.977396
10984 19:23:58.014982 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10985 19:23:58.015176
10986 19:23:58.032870 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10987 19:23:58.033091
10988 19:23:58.053540 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10989 19:23:58.053728
10990 19:23:58.074458 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10991 19:23:58.074658
10992 19:23:58.100133 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10993 19:23:58.100325
10994 19:23:58.133249 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users..<46>[ 23.125260] systemd-journald[298]: Received client request to flush runtime journal.
10995 19:23:58.133421 .
10996 19:23:58.133523
10997 19:23:58.168534 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10998 19:23:58.168677
10999 19:23:58.179132 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
11000 19:23:58.179268
11001 19:23:58.199647 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
11002 19:23:58.199846
11003 19:23:58.220141 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
11004 19:23:58.220332
11005 19:23:58.468606 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
11006 19:23:58.468785
11007 19:23:58.527332 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
11008 19:23:58.527515
11009 19:23:59.547223 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11010 19:23:59.547360
11011 19:23:59.591606 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11012 19:23:59.591787
11013 19:23:59.614205 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11014 19:23:59.614374
11015 19:23:59.630196 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11016 19:23:59.630362
11017 19:23:59.670543 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11018 19:23:59.670720
11019 19:23:59.692770 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11020 19:23:59.693015
11021 19:23:59.922029 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11022 19:23:59.922168
11023 19:23:59.983571 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11024 19:23:59.983773
11025 19:24:00.095418 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11026 19:24:00.095620
11027 19:24:00.347828 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11028 19:24:00.348058
11029 19:24:00.416025 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11030 19:24:00.416195
11031 19:24:00.436002 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11032 19:24:00.436201
11033 19:24:00.519017 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11034 19:24:00.519150
11035 19:24:00.538565 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11036 19:24:00.538701
11037 19:24:00.586057 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11038 19:24:00.586208
11039 19:24:00.607630 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11040 19:24:00.607765
11041 19:24:00.619860 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11042 19:24:00.620002
11043 19:24:00.640265 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11044 19:24:00.640366
11045 19:24:00.681047 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11046 19:24:00.681188
11047 19:24:00.752136 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11048 19:24:00.752270
11049 19:24:00.778834 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11050 19:24:00.779011
11051 19:24:00.810916 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11052 19:24:00.811042
11053 19:24:00.830529 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11054 19:24:00.830640
11055 19:24:00.846320 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11056 19:24:00.846424
11057 19:24:00.862141 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11058 19:24:00.862276
11059 19:24:00.878056 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11060 19:24:00.878176
11061 19:24:00.922506 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11062 19:24:00.922665
11063 19:24:00.940983 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11064 19:24:00.941099
11065 19:24:00.958087 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11066 19:24:00.958209
11067 19:24:00.977439 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11068 19:24:00.977702
11069 19:24:00.997335 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11070 19:24:00.997453
11071 19:24:01.013832 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11072 19:24:01.013944
11073 19:24:01.032406 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11074 19:24:01.032544
11075 19:24:01.049517 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11076 19:24:01.049628
11077 19:24:01.066467 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11078 19:24:01.066587
11079 19:24:01.103812 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11080 19:24:01.104006
11081 19:24:01.137935 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11082 19:24:01.138131
11083 19:24:01.206965 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11084 19:24:01.207136
11085 19:24:01.232006 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11086 19:24:01.232145
11087 19:24:01.286897 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11088 19:24:01.287065
11089 19:24:01.331278 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11090 19:24:01.331421
11091 19:24:01.353249 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11092 19:24:01.353387
11093 19:24:01.374527 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11094 19:24:01.374664
11095 19:24:01.501886 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11096 19:24:01.502023
11097 19:24:01.564401 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11098 19:24:01.564535
11099 19:24:01.587833 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11100 19:24:01.587985
11101 19:24:01.611128 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11102 19:24:01.611267
11103 19:24:01.631032 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11104 19:24:01.631164
11105 19:24:01.685554 Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
11106 19:24:01.685733
11107 19:24:01.710201 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11108 19:24:01.710354
11109 19:24:01.764413 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11110 19:24:01.764549
11111 19:24:01.793989 [[0;32m OK [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
11112 19:24:01.794126
11113 19:24:01.882232
11114 19:24:01.882361
11115 19:24:01.885456 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11116 19:24:01.885541
11117 19:24:01.889215 debian-bookworm-arm64 login: root (automatic login)
11118 19:24:01.889368
11119 19:24:01.889448
11120 19:24:02.141948 Linux debian-bookworm-arm64 6.1.86-cip19 #1 SMP PREEMPT Thu Apr 18 19:05:54 UTC 2024 aarch64
11121 19:24:02.142130
11122 19:24:02.148728 The programs included with the Debian GNU/Linux system are free software;
11123 19:24:02.155156 the exact distribution terms for each program are described in the
11124 19:24:02.158398 individual files in /usr/share/doc/*/copyright.
11125 19:24:02.158498
11126 19:24:02.164810 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11127 19:24:02.168143 permitted by applicable law.
11128 19:24:02.269606 Matched prompt #10: / #
11130 19:24:02.269885 Setting prompt string to ['/ #']
11131 19:24:02.269980 end: 2.2.5.1 login-action (duration 00:00:28) [common]
11133 19:24:02.270178 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
11134 19:24:02.270264 start: 2.2.6 expect-shell-connection (timeout 00:03:14) [common]
11135 19:24:02.270335 Setting prompt string to ['/ #']
11136 19:24:02.270434 Forcing a shell prompt, looking for ['/ #']
11138 19:24:02.320667 / #
11139 19:24:02.320835 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11140 19:24:02.320950 Waiting using forced prompt support (timeout 00:02:30)
11141 19:24:02.326239
11142 19:24:02.326562 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11143 19:24:02.326678 start: 2.2.7 export-device-env (timeout 00:03:14) [common]
11145 19:24:02.427025 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/13420331/extract-nfsrootfs-8q2m2gfc'
11146 19:24:02.432289 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/13420331/extract-nfsrootfs-8q2m2gfc'
11148 19:24:02.532848 / # export NFS_SERVER_IP='192.168.201.1'
11149 19:24:02.538477 export NFS_SERVER_IP='192.168.201.1'
11150 19:24:02.538806 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11151 19:24:02.538918 end: 2.2 depthcharge-retry (duration 00:01:46) [common]
11152 19:24:02.539033 end: 2 depthcharge-action (duration 00:01:46) [common]
11153 19:24:02.539153 start: 3 lava-test-retry (timeout 00:01:00) [common]
11154 19:24:02.539285 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
11155 19:24:02.539360 Using namespace: common
11157 19:24:02.639732 / # #
11158 19:24:02.639928 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11159 19:24:02.644480 #
11160 19:24:02.644818 Using /lava-13420331
11162 19:24:02.745206 / # export SHELL=/bin/sh
11163 19:24:02.750341 export SHELL=/bin/sh
11165 19:24:02.850906 / # . /lava-13420331/environment
11166 19:24:02.856064 . /lava-13420331/environment
11168 19:24:02.962609 / # /lava-13420331/bin/lava-test-runner /lava-13420331/0
11169 19:24:02.962779 Test shell timeout: 10s (minimum of the action and connection timeout)
11170 19:24:02.967689 /lava-13420331/bin/lava-test-runner /lava-13420331/0
11171 19:24:03.214485 + export TESTRUN_ID=0_dmesg
11172 19:24:03.217221 + cd /lava-13420331/0/tests/0_dmesg
11173 19:24:03.221157 + cat uuid
11174 19:24:03.236560 + UUID=13420331_<8>[ 28.229719] <LAVA_SIGNAL_STARTRUN 0_dmesg 13420331_1.6.2.3.1>
11175 19:24:03.236704 1.6.2.3.1
11176 19:24:03.236776 + set +x
11177 19:24:03.237044 Received signal: <STARTRUN> 0_dmesg 13420331_1.6.2.3.1
11178 19:24:03.237118 Starting test lava.0_dmesg (13420331_1.6.2.3.1)
11179 19:24:03.237203 Skipping test definition patterns.
11180 19:24:03.242898 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
11181 19:24:03.357074 <8>[ 28.350000] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
11182 19:24:03.357396 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
11184 19:24:03.439736 <8>[ 28.432469] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
11185 19:24:03.440123 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
11187 19:24:03.520350 <8>[ 28.513606] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
11188 19:24:03.520677 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
11190 19:24:03.528270 + <8>[ 28.524649] <LAVA_SIGNAL_ENDRUN 0_dmesg 13420331_1.6.2.3.1>
11191 19:24:03.528571 Received signal: <ENDRUN> 0_dmesg 13420331_1.6.2.3.1
11192 19:24:03.528659 Ending use of test pattern.
11193 19:24:03.528723 Ending test lava.0_dmesg (13420331_1.6.2.3.1), duration 0.29
11195 19:24:03.531480 set +x
11196 19:24:03.534653 <LAVA_TEST_RUNNER EXIT>
11197 19:24:03.534919 ok: lava_test_shell seems to have completed
11198 19:24:03.535024 alert: pass
crit: pass
emerg: pass
11199 19:24:03.535113 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11200 19:24:03.535197 end: 3 lava-test-retry (duration 00:00:01) [common]
11201 19:24:03.535315 start: 4 finalize (timeout 00:07:45) [common]
11202 19:24:03.535404 start: 4.1 power-off (timeout 00:00:30) [common]
11203 19:24:03.535559 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=off'
11204 19:24:03.612403 >> Command sent successfully.
11205 19:24:03.614963 Returned 0 in 0 seconds
11206 19:24:03.715401 end: 4.1 power-off (duration 00:00:00) [common]
11208 19:24:03.715859 start: 4.2 read-feedback (timeout 00:07:45) [common]
11209 19:24:03.716147 Listened to connection for namespace 'common' for up to 1s
11210 19:24:04.717031 Finalising connection for namespace 'common'
11211 19:24:04.717214 Disconnecting from shell: Finalise
11212 19:24:04.717315 / #
11213 19:24:04.817670 end: 4.2 read-feedback (duration 00:00:01) [common]
11214 19:24:04.817896 end: 4 finalize (duration 00:00:01) [common]
11215 19:24:04.818062 Cleaning after the job
11216 19:24:04.818202 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13420331/tftp-deploy-9vswnwe8/ramdisk
11217 19:24:04.820477 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13420331/tftp-deploy-9vswnwe8/kernel
11218 19:24:04.832156 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13420331/tftp-deploy-9vswnwe8/dtb
11219 19:24:04.832378 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13420331/tftp-deploy-9vswnwe8/nfsrootfs
11220 19:24:04.891282 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13420331/tftp-deploy-9vswnwe8/modules
11221 19:24:04.897059 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/13420331
11222 19:24:05.215211 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/13420331
11223 19:24:05.215418 Job finished correctly