Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 25
- Errors: 0
- Kernel Errors: 36
- Boot result: PASS
1 19:21:30.992992 lava-dispatcher, installed at version: 2024.01
2 19:21:30.993200 start: 0 validate
3 19:21:30.993370 Start time: 2024-04-18 19:21:30.993362+00:00 (UTC)
4 19:21:30.993497 Using caching service: 'http://localhost/cache/?uri=%s'
5 19:21:30.993630 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 19:21:31.255132 Using caching service: 'http://localhost/cache/?uri=%s'
7 19:21:31.255771 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 19:21:54.262235 Using caching service: 'http://localhost/cache/?uri=%s'
9 19:21:54.262400 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 19:21:54.520857 Using caching service: 'http://localhost/cache/?uri=%s'
11 19:21:54.521029 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 19:21:54.778306 Using caching service: 'http://localhost/cache/?uri=%s'
13 19:21:54.778977 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 19:21:57.294285 validate duration: 26.30
16 19:21:57.295785 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 19:21:57.296541 start: 1.1 download-retry (timeout 00:10:00) [common]
18 19:21:57.297164 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 19:21:57.297873 Not decompressing ramdisk as can be used compressed.
20 19:21:57.298406 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 19:21:57.298782 saving as /var/lib/lava/dispatcher/tmp/13420348/tftp-deploy-g80fdqkg/ramdisk/initrd.cpio.gz
22 19:21:57.299206 total size: 5628169 (5 MB)
23 19:21:57.568562 progress 0 % (0 MB)
24 19:21:57.570346 progress 5 % (0 MB)
25 19:21:57.572056 progress 10 % (0 MB)
26 19:21:57.573549 progress 15 % (0 MB)
27 19:21:57.575223 progress 20 % (1 MB)
28 19:21:57.576679 progress 25 % (1 MB)
29 19:21:57.578331 progress 30 % (1 MB)
30 19:21:57.579985 progress 35 % (1 MB)
31 19:21:57.581435 progress 40 % (2 MB)
32 19:21:57.583025 progress 45 % (2 MB)
33 19:21:57.584471 progress 50 % (2 MB)
34 19:21:57.586065 progress 55 % (2 MB)
35 19:21:57.587709 progress 60 % (3 MB)
36 19:21:57.589175 progress 65 % (3 MB)
37 19:21:57.590791 progress 70 % (3 MB)
38 19:21:57.592191 progress 75 % (4 MB)
39 19:21:57.593772 progress 80 % (4 MB)
40 19:21:57.595171 progress 85 % (4 MB)
41 19:21:57.596761 progress 90 % (4 MB)
42 19:21:57.598328 progress 95 % (5 MB)
43 19:21:57.599743 progress 100 % (5 MB)
44 19:21:57.599956 5 MB downloaded in 0.30 s (17.85 MB/s)
45 19:21:57.600117 end: 1.1.1 http-download (duration 00:00:00) [common]
47 19:21:57.600385 end: 1.1 download-retry (duration 00:00:00) [common]
48 19:21:57.600475 start: 1.2 download-retry (timeout 00:10:00) [common]
49 19:21:57.600562 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 19:21:57.600700 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 19:21:57.600773 saving as /var/lib/lava/dispatcher/tmp/13420348/tftp-deploy-g80fdqkg/kernel/Image
52 19:21:57.600838 total size: 54286848 (51 MB)
53 19:21:57.600902 No compression specified
54 19:21:57.601965 progress 0 % (0 MB)
55 19:21:57.615836 progress 5 % (2 MB)
56 19:21:57.629830 progress 10 % (5 MB)
57 19:21:57.643837 progress 15 % (7 MB)
58 19:21:57.657762 progress 20 % (10 MB)
59 19:21:57.672324 progress 25 % (12 MB)
60 19:21:57.686501 progress 30 % (15 MB)
61 19:21:57.700588 progress 35 % (18 MB)
62 19:21:57.715158 progress 40 % (20 MB)
63 19:21:57.729045 progress 45 % (23 MB)
64 19:21:57.742959 progress 50 % (25 MB)
65 19:21:57.757018 progress 55 % (28 MB)
66 19:21:57.771070 progress 60 % (31 MB)
67 19:21:57.784839 progress 65 % (33 MB)
68 19:21:57.798882 progress 70 % (36 MB)
69 19:21:57.812885 progress 75 % (38 MB)
70 19:21:57.826792 progress 80 % (41 MB)
71 19:21:57.840939 progress 85 % (44 MB)
72 19:21:57.855228 progress 90 % (46 MB)
73 19:21:57.868983 progress 95 % (49 MB)
74 19:21:57.883026 progress 100 % (51 MB)
75 19:21:57.883291 51 MB downloaded in 0.28 s (183.30 MB/s)
76 19:21:57.883487 end: 1.2.1 http-download (duration 00:00:00) [common]
78 19:21:57.883723 end: 1.2 download-retry (duration 00:00:00) [common]
79 19:21:57.883854 start: 1.3 download-retry (timeout 00:09:59) [common]
80 19:21:57.883955 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 19:21:57.884095 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 19:21:57.884165 saving as /var/lib/lava/dispatcher/tmp/13420348/tftp-deploy-g80fdqkg/dtb/mt8192-asurada-spherion-r0.dtb
83 19:21:57.884228 total size: 47230 (0 MB)
84 19:21:57.884290 No compression specified
85 19:21:57.885469 progress 69 % (0 MB)
86 19:21:57.885741 progress 100 % (0 MB)
87 19:21:57.885939 0 MB downloaded in 0.00 s (26.37 MB/s)
88 19:21:57.886064 end: 1.3.1 http-download (duration 00:00:00) [common]
90 19:21:57.886323 end: 1.3 download-retry (duration 00:00:00) [common]
91 19:21:57.886409 start: 1.4 download-retry (timeout 00:09:59) [common]
92 19:21:57.886492 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 19:21:57.886648 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 19:21:57.886721 saving as /var/lib/lava/dispatcher/tmp/13420348/tftp-deploy-g80fdqkg/nfsrootfs/full.rootfs.tar
95 19:21:57.886814 total size: 120894716 (115 MB)
96 19:21:57.886881 Using unxz to decompress xz
97 19:21:57.891012 progress 0 % (0 MB)
98 19:21:58.248554 progress 5 % (5 MB)
99 19:21:58.616806 progress 10 % (11 MB)
100 19:21:58.974767 progress 15 % (17 MB)
101 19:21:59.311463 progress 20 % (23 MB)
102 19:21:59.609565 progress 25 % (28 MB)
103 19:21:59.979562 progress 30 % (34 MB)
104 19:22:00.328540 progress 35 % (40 MB)
105 19:22:00.505682 progress 40 % (46 MB)
106 19:22:00.692838 progress 45 % (51 MB)
107 19:22:01.026953 progress 50 % (57 MB)
108 19:22:01.417950 progress 55 % (63 MB)
109 19:22:01.771982 progress 60 % (69 MB)
110 19:22:02.122570 progress 65 % (74 MB)
111 19:22:02.475691 progress 70 % (80 MB)
112 19:22:02.857413 progress 75 % (86 MB)
113 19:22:03.225384 progress 80 % (92 MB)
114 19:22:03.576026 progress 85 % (98 MB)
115 19:22:03.942186 progress 90 % (103 MB)
116 19:22:04.278008 progress 95 % (109 MB)
117 19:22:04.647144 progress 100 % (115 MB)
118 19:22:04.652614 115 MB downloaded in 6.77 s (17.04 MB/s)
119 19:22:04.652927 end: 1.4.1 http-download (duration 00:00:07) [common]
121 19:22:04.653315 end: 1.4 download-retry (duration 00:00:07) [common]
122 19:22:04.653410 start: 1.5 download-retry (timeout 00:09:53) [common]
123 19:22:04.653500 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 19:22:04.653648 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 19:22:04.653718 saving as /var/lib/lava/dispatcher/tmp/13420348/tftp-deploy-g80fdqkg/modules/modules.tar
126 19:22:04.653781 total size: 8631416 (8 MB)
127 19:22:04.653846 Using unxz to decompress xz
128 19:22:04.658081 progress 0 % (0 MB)
129 19:22:04.677454 progress 5 % (0 MB)
130 19:22:04.702549 progress 10 % (0 MB)
131 19:22:04.726973 progress 15 % (1 MB)
132 19:22:04.750836 progress 20 % (1 MB)
133 19:22:04.775988 progress 25 % (2 MB)
134 19:22:04.802149 progress 30 % (2 MB)
135 19:22:04.826599 progress 35 % (2 MB)
136 19:22:04.852271 progress 40 % (3 MB)
137 19:22:04.876592 progress 45 % (3 MB)
138 19:22:04.902169 progress 50 % (4 MB)
139 19:22:04.927462 progress 55 % (4 MB)
140 19:22:04.955974 progress 60 % (4 MB)
141 19:22:04.981717 progress 65 % (5 MB)
142 19:22:05.006938 progress 70 % (5 MB)
143 19:22:05.031469 progress 75 % (6 MB)
144 19:22:05.057184 progress 80 % (6 MB)
145 19:22:05.083280 progress 85 % (7 MB)
146 19:22:05.113432 progress 90 % (7 MB)
147 19:22:05.143148 progress 95 % (7 MB)
148 19:22:05.169896 progress 100 % (8 MB)
149 19:22:05.175516 8 MB downloaded in 0.52 s (15.78 MB/s)
150 19:22:05.175776 end: 1.5.1 http-download (duration 00:00:01) [common]
152 19:22:05.176050 end: 1.5 download-retry (duration 00:00:01) [common]
153 19:22:05.176162 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 19:22:05.176261 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 19:22:08.875608 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/13420348/extract-nfsrootfs-oiegi9vu
156 19:22:08.875817 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 19:22:08.875917 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 19:22:08.876082 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/13420348/lava-overlay-8lvhpqip
159 19:22:08.876212 makedir: /var/lib/lava/dispatcher/tmp/13420348/lava-overlay-8lvhpqip/lava-13420348/bin
160 19:22:08.876312 makedir: /var/lib/lava/dispatcher/tmp/13420348/lava-overlay-8lvhpqip/lava-13420348/tests
161 19:22:08.876410 makedir: /var/lib/lava/dispatcher/tmp/13420348/lava-overlay-8lvhpqip/lava-13420348/results
162 19:22:08.876509 Creating /var/lib/lava/dispatcher/tmp/13420348/lava-overlay-8lvhpqip/lava-13420348/bin/lava-add-keys
163 19:22:08.876649 Creating /var/lib/lava/dispatcher/tmp/13420348/lava-overlay-8lvhpqip/lava-13420348/bin/lava-add-sources
164 19:22:08.876785 Creating /var/lib/lava/dispatcher/tmp/13420348/lava-overlay-8lvhpqip/lava-13420348/bin/lava-background-process-start
165 19:22:08.876909 Creating /var/lib/lava/dispatcher/tmp/13420348/lava-overlay-8lvhpqip/lava-13420348/bin/lava-background-process-stop
166 19:22:08.877031 Creating /var/lib/lava/dispatcher/tmp/13420348/lava-overlay-8lvhpqip/lava-13420348/bin/lava-common-functions
167 19:22:08.877152 Creating /var/lib/lava/dispatcher/tmp/13420348/lava-overlay-8lvhpqip/lava-13420348/bin/lava-echo-ipv4
168 19:22:08.877314 Creating /var/lib/lava/dispatcher/tmp/13420348/lava-overlay-8lvhpqip/lava-13420348/bin/lava-install-packages
169 19:22:08.877436 Creating /var/lib/lava/dispatcher/tmp/13420348/lava-overlay-8lvhpqip/lava-13420348/bin/lava-installed-packages
170 19:22:08.877558 Creating /var/lib/lava/dispatcher/tmp/13420348/lava-overlay-8lvhpqip/lava-13420348/bin/lava-os-build
171 19:22:08.877679 Creating /var/lib/lava/dispatcher/tmp/13420348/lava-overlay-8lvhpqip/lava-13420348/bin/lava-probe-channel
172 19:22:08.877810 Creating /var/lib/lava/dispatcher/tmp/13420348/lava-overlay-8lvhpqip/lava-13420348/bin/lava-probe-ip
173 19:22:08.877930 Creating /var/lib/lava/dispatcher/tmp/13420348/lava-overlay-8lvhpqip/lava-13420348/bin/lava-target-ip
174 19:22:08.878054 Creating /var/lib/lava/dispatcher/tmp/13420348/lava-overlay-8lvhpqip/lava-13420348/bin/lava-target-mac
175 19:22:08.878173 Creating /var/lib/lava/dispatcher/tmp/13420348/lava-overlay-8lvhpqip/lava-13420348/bin/lava-target-storage
176 19:22:08.878305 Creating /var/lib/lava/dispatcher/tmp/13420348/lava-overlay-8lvhpqip/lava-13420348/bin/lava-test-case
177 19:22:08.878428 Creating /var/lib/lava/dispatcher/tmp/13420348/lava-overlay-8lvhpqip/lava-13420348/bin/lava-test-event
178 19:22:08.878548 Creating /var/lib/lava/dispatcher/tmp/13420348/lava-overlay-8lvhpqip/lava-13420348/bin/lava-test-feedback
179 19:22:08.878673 Creating /var/lib/lava/dispatcher/tmp/13420348/lava-overlay-8lvhpqip/lava-13420348/bin/lava-test-raise
180 19:22:08.878802 Creating /var/lib/lava/dispatcher/tmp/13420348/lava-overlay-8lvhpqip/lava-13420348/bin/lava-test-reference
181 19:22:08.878925 Creating /var/lib/lava/dispatcher/tmp/13420348/lava-overlay-8lvhpqip/lava-13420348/bin/lava-test-runner
182 19:22:08.879045 Creating /var/lib/lava/dispatcher/tmp/13420348/lava-overlay-8lvhpqip/lava-13420348/bin/lava-test-set
183 19:22:08.879165 Creating /var/lib/lava/dispatcher/tmp/13420348/lava-overlay-8lvhpqip/lava-13420348/bin/lava-test-shell
184 19:22:08.879286 Updating /var/lib/lava/dispatcher/tmp/13420348/lava-overlay-8lvhpqip/lava-13420348/bin/lava-add-keys (debian)
185 19:22:08.879441 Updating /var/lib/lava/dispatcher/tmp/13420348/lava-overlay-8lvhpqip/lava-13420348/bin/lava-add-sources (debian)
186 19:22:08.879579 Updating /var/lib/lava/dispatcher/tmp/13420348/lava-overlay-8lvhpqip/lava-13420348/bin/lava-install-packages (debian)
187 19:22:08.879713 Updating /var/lib/lava/dispatcher/tmp/13420348/lava-overlay-8lvhpqip/lava-13420348/bin/lava-installed-packages (debian)
188 19:22:08.879847 Updating /var/lib/lava/dispatcher/tmp/13420348/lava-overlay-8lvhpqip/lava-13420348/bin/lava-os-build (debian)
189 19:22:08.879972 Creating /var/lib/lava/dispatcher/tmp/13420348/lava-overlay-8lvhpqip/lava-13420348/environment
190 19:22:08.880065 LAVA metadata
191 19:22:08.880135 - LAVA_JOB_ID=13420348
192 19:22:08.880196 - LAVA_DISPATCHER_IP=192.168.201.1
193 19:22:08.880292 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 19:22:08.880357 skipped lava-vland-overlay
195 19:22:08.880428 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 19:22:08.880512 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 19:22:08.880573 skipped lava-multinode-overlay
198 19:22:08.880642 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 19:22:08.880730 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 19:22:08.880802 Loading test definitions
201 19:22:08.880887 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 19:22:08.880957 Using /lava-13420348 at stage 0
203 19:22:08.881248 uuid=13420348_1.6.2.3.1 testdef=None
204 19:22:08.881336 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 19:22:08.881420 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 19:22:08.881865 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 19:22:08.882080 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 19:22:08.882630 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 19:22:08.882864 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 19:22:08.883386 runner path: /var/lib/lava/dispatcher/tmp/13420348/lava-overlay-8lvhpqip/lava-13420348/0/tests/0_timesync-off test_uuid 13420348_1.6.2.3.1
213 19:22:08.883539 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 19:22:08.883772 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 19:22:08.883844 Using /lava-13420348 at stage 0
217 19:22:08.883939 Fetching tests from https://github.com/kernelci/test-definitions.git
218 19:22:08.884025 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/13420348/lava-overlay-8lvhpqip/lava-13420348/0/tests/1_kselftest-arm64'
219 19:22:12.152088 Running '/usr/bin/git checkout kernelci.org
220 19:22:12.262971 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/13420348/lava-overlay-8lvhpqip/lava-13420348/0/tests/1_kselftest-arm64/automated/linux/kselftest/kselftest.yaml
221 19:22:12.263698 uuid=13420348_1.6.2.3.5 testdef=None
222 19:22:12.263857 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 19:22:12.264104 start: 1.6.2.3.6 test-overlay (timeout 00:09:45) [common]
225 19:22:12.264849 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 19:22:12.265092 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:45) [common]
228 19:22:12.266232 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 19:22:12.266466 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:45) [common]
231 19:22:12.267416 runner path: /var/lib/lava/dispatcher/tmp/13420348/lava-overlay-8lvhpqip/lava-13420348/0/tests/1_kselftest-arm64 test_uuid 13420348_1.6.2.3.5
232 19:22:12.267507 BOARD='mt8192-asurada-spherion-r0'
233 19:22:12.267572 BRANCH='cip'
234 19:22:12.267650 SKIPFILE='/dev/null'
235 19:22:12.267722 SKIP_INSTALL='True'
236 19:22:12.267778 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 19:22:12.267836 TST_CASENAME=''
238 19:22:12.267890 TST_CMDFILES='arm64'
239 19:22:12.268027 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 19:22:12.268235 Creating lava-test-runner.conf files
242 19:22:12.268298 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/13420348/lava-overlay-8lvhpqip/lava-13420348/0 for stage 0
243 19:22:12.268389 - 0_timesync-off
244 19:22:12.268459 - 1_kselftest-arm64
245 19:22:12.268553 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 19:22:12.268648 start: 1.6.2.4 compress-overlay (timeout 00:09:45) [common]
247 19:22:19.987592 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 19:22:19.987808 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:37) [common]
249 19:22:19.987937 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 19:22:19.988078 end: 1.6.2 lava-overlay (duration 00:00:11) [common]
251 19:22:19.988199 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:37) [common]
252 19:22:20.159528 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 19:22:20.159917 start: 1.6.4 extract-modules (timeout 00:09:37) [common]
254 19:22:20.160036 extracting modules file /var/lib/lava/dispatcher/tmp/13420348/tftp-deploy-g80fdqkg/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13420348/extract-nfsrootfs-oiegi9vu
255 19:22:20.382292 extracting modules file /var/lib/lava/dispatcher/tmp/13420348/tftp-deploy-g80fdqkg/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13420348/extract-overlay-ramdisk-_j7q87w_/ramdisk
256 19:22:20.610965 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 19:22:20.611139 start: 1.6.5 apply-overlay-tftp (timeout 00:09:37) [common]
258 19:22:20.611238 [common] Applying overlay to NFS
259 19:22:20.611309 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13420348/compress-overlay-1u7jdbzw/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/13420348/extract-nfsrootfs-oiegi9vu
260 19:22:21.569947 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 19:22:21.570136 start: 1.6.6 configure-preseed-file (timeout 00:09:36) [common]
262 19:22:21.570254 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 19:22:21.570361 start: 1.6.7 compress-ramdisk (timeout 00:09:36) [common]
264 19:22:21.570456 Building ramdisk /var/lib/lava/dispatcher/tmp/13420348/extract-overlay-ramdisk-_j7q87w_/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/13420348/extract-overlay-ramdisk-_j7q87w_/ramdisk
265 19:22:21.880999 >> 130624 blocks
266 19:22:23.975835 rename /var/lib/lava/dispatcher/tmp/13420348/extract-overlay-ramdisk-_j7q87w_/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/13420348/tftp-deploy-g80fdqkg/ramdisk/ramdisk.cpio.gz
267 19:22:23.976319 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 19:22:23.976470 start: 1.6.8 prepare-kernel (timeout 00:09:33) [common]
269 19:22:23.976602 start: 1.6.8.1 prepare-fit (timeout 00:09:33) [common]
270 19:22:23.976712 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/13420348/tftp-deploy-g80fdqkg/kernel/Image'
271 19:22:38.388571 Returned 0 in 14 seconds
272 19:22:38.489224 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/13420348/tftp-deploy-g80fdqkg/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/13420348/tftp-deploy-g80fdqkg/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/13420348/tftp-deploy-g80fdqkg/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/13420348/tftp-deploy-g80fdqkg/kernel/image.itb
273 19:22:38.862247 output: FIT description: Kernel Image image with one or more FDT blobs
274 19:22:38.862635 output: Created: Thu Apr 18 20:22:38 2024
275 19:22:38.862740 output: Image 0 (kernel-1)
276 19:22:38.862835 output: Description:
277 19:22:38.862932 output: Created: Thu Apr 18 20:22:38 2024
278 19:22:38.863019 output: Type: Kernel Image
279 19:22:38.863104 output: Compression: lzma compressed
280 19:22:38.863205 output: Data Size: 12910355 Bytes = 12607.77 KiB = 12.31 MiB
281 19:22:38.863306 output: Architecture: AArch64
282 19:22:38.863410 output: OS: Linux
283 19:22:38.863507 output: Load Address: 0x00000000
284 19:22:38.863609 output: Entry Point: 0x00000000
285 19:22:38.863708 output: Hash algo: crc32
286 19:22:38.863806 output: Hash value: bbac8b0b
287 19:22:38.863905 output: Image 1 (fdt-1)
288 19:22:38.864002 output: Description: mt8192-asurada-spherion-r0
289 19:22:38.864097 output: Created: Thu Apr 18 20:22:38 2024
290 19:22:38.864192 output: Type: Flat Device Tree
291 19:22:38.864287 output: Compression: uncompressed
292 19:22:38.864381 output: Data Size: 47230 Bytes = 46.12 KiB = 0.05 MiB
293 19:22:38.864479 output: Architecture: AArch64
294 19:22:38.864574 output: Hash algo: crc32
295 19:22:38.864667 output: Hash value: 4bf0d1ac
296 19:22:38.864760 output: Image 2 (ramdisk-1)
297 19:22:38.864853 output: Description: unavailable
298 19:22:38.864946 output: Created: Thu Apr 18 20:22:38 2024
299 19:22:38.865039 output: Type: RAMDisk Image
300 19:22:38.865133 output: Compression: Unknown Compression
301 19:22:38.865241 output: Data Size: 18772366 Bytes = 18332.39 KiB = 17.90 MiB
302 19:22:38.865338 output: Architecture: AArch64
303 19:22:38.865433 output: OS: Linux
304 19:22:38.865527 output: Load Address: unavailable
305 19:22:38.865621 output: Entry Point: unavailable
306 19:22:38.865714 output: Hash algo: crc32
307 19:22:38.865807 output: Hash value: 6b7e4b64
308 19:22:38.865900 output: Default Configuration: 'conf-1'
309 19:22:38.865994 output: Configuration 0 (conf-1)
310 19:22:38.866087 output: Description: mt8192-asurada-spherion-r0
311 19:22:38.866180 output: Kernel: kernel-1
312 19:22:38.866273 output: Init Ramdisk: ramdisk-1
313 19:22:38.866366 output: FDT: fdt-1
314 19:22:38.866460 output: Loadables: kernel-1
315 19:22:38.866553 output:
316 19:22:38.866811 end: 1.6.8.1 prepare-fit (duration 00:00:15) [common]
317 19:22:38.866955 end: 1.6.8 prepare-kernel (duration 00:00:15) [common]
318 19:22:38.867104 end: 1.6 prepare-tftp-overlay (duration 00:00:34) [common]
319 19:22:38.867248 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:18) [common]
320 19:22:38.867370 No LXC device requested
321 19:22:38.867496 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 19:22:38.867629 start: 1.8 deploy-device-env (timeout 00:09:18) [common]
323 19:22:38.867749 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 19:22:38.867860 Checking files for TFTP limit of 4294967296 bytes.
325 19:22:38.868548 end: 1 tftp-deploy (duration 00:00:42) [common]
326 19:22:38.868697 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 19:22:38.868840 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 19:22:38.869026 substitutions:
329 19:22:38.869130 - {DTB}: 13420348/tftp-deploy-g80fdqkg/dtb/mt8192-asurada-spherion-r0.dtb
330 19:22:38.869242 - {INITRD}: 13420348/tftp-deploy-g80fdqkg/ramdisk/ramdisk.cpio.gz
331 19:22:38.869346 - {KERNEL}: 13420348/tftp-deploy-g80fdqkg/kernel/Image
332 19:22:38.869428 - {LAVA_MAC}: None
333 19:22:38.869508 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/13420348/extract-nfsrootfs-oiegi9vu
334 19:22:38.869607 - {NFS_SERVER_IP}: 192.168.201.1
335 19:22:38.869705 - {PRESEED_CONFIG}: None
336 19:22:38.869802 - {PRESEED_LOCAL}: None
337 19:22:38.869899 - {RAMDISK}: 13420348/tftp-deploy-g80fdqkg/ramdisk/ramdisk.cpio.gz
338 19:22:38.869996 - {ROOT_PART}: None
339 19:22:38.870092 - {ROOT}: None
340 19:22:38.870191 - {SERVER_IP}: 192.168.201.1
341 19:22:38.870288 - {TEE}: None
342 19:22:38.870390 Parsed boot commands:
343 19:22:38.870486 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 19:22:38.870727 Parsed boot commands: tftpboot 192.168.201.1 13420348/tftp-deploy-g80fdqkg/kernel/image.itb 13420348/tftp-deploy-g80fdqkg/kernel/cmdline
345 19:22:38.870858 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 19:22:38.870988 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 19:22:38.871123 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 19:22:38.871253 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 19:22:38.871365 Not connected, no need to disconnect.
350 19:22:38.871486 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 19:22:38.871615 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 19:22:38.871722 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
353 19:22:38.875619 Setting prompt string to ['lava-test: # ']
354 19:22:38.876035 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 19:22:38.876166 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 19:22:38.876303 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 19:22:38.876441 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 19:22:38.876802 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=reboot'
359 19:22:44.024189 >> Command sent successfully.
360 19:22:44.035672 Returned 0 in 5 seconds
361 19:22:44.136983 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 19:22:44.138631 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 19:22:44.139243 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 19:22:44.139743 Setting prompt string to 'Starting depthcharge on Spherion...'
366 19:22:44.140304 Changing prompt to 'Starting depthcharge on Spherion...'
367 19:22:44.140793 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 19:22:44.142333 [Enter `^Ec?' for help]
369 19:22:44.526135
370 19:22:44.526833
371 19:22:44.527424 F0: 102B 0000
372 19:22:44.527998
373 19:22:44.528499 F3: 1001 0000 [0200]
374 19:22:44.529696
375 19:22:44.530275 F3: 1001 0000
376 19:22:44.530860
377 19:22:44.531408 F7: 102D 0000
378 19:22:44.531933
379 19:22:44.532821 F1: 0000 0000
380 19:22:44.533393
381 19:22:44.533898 V0: 0000 0000 [0001]
382 19:22:44.534469
383 19:22:44.535932 00: 0007 8000
384 19:22:44.536477
385 19:22:44.536995 01: 0000 0000
386 19:22:44.537558
387 19:22:44.539678 BP: 0C00 0209 [0000]
388 19:22:44.540219
389 19:22:44.540750 G0: 1182 0000
390 19:22:44.541294
391 19:22:44.542645 EC: 0000 0021 [4000]
392 19:22:44.543261
393 19:22:44.543796 S7: 0000 0000 [0000]
394 19:22:44.544313
395 19:22:44.546286 CC: 0000 0000 [0001]
396 19:22:44.546893
397 19:22:44.547438 T0: 0000 0040 [010F]
398 19:22:44.548000
399 19:22:44.549313 Jump to BL
400 19:22:44.549771
401 19:22:44.572815
402 19:22:44.573119
403 19:22:44.573396
404 19:22:44.582823 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 19:22:44.586658 ARM64: Exception handlers installed.
406 19:22:44.586961 ARM64: Testing exception
407 19:22:44.589759 ARM64: Done test exception
408 19:22:44.596545 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 19:22:44.607052 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 19:22:44.613253 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 19:22:44.624378 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 19:22:44.630575 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 19:22:44.641042 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 19:22:44.650723 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 19:22:44.657460 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 19:22:44.676637 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 19:22:44.679193 WDT: Last reset was cold boot
418 19:22:44.682396 SPI1(PAD0) initialized at 2873684 Hz
419 19:22:44.686251 SPI5(PAD0) initialized at 992727 Hz
420 19:22:44.689197 VBOOT: Loading verstage.
421 19:22:44.696048 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 19:22:44.699500 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 19:22:44.702504 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 19:22:44.706275 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 19:22:44.713513 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 19:22:44.719953 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 19:22:44.731108 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 19:22:44.731737
429 19:22:44.732270
430 19:22:44.740751 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 19:22:44.744624 ARM64: Exception handlers installed.
432 19:22:44.747728 ARM64: Testing exception
433 19:22:44.748176 ARM64: Done test exception
434 19:22:44.754684 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 19:22:44.758191 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 19:22:44.772288 Probing TPM: . done!
437 19:22:44.772793 TPM ready after 0 ms
438 19:22:44.778814 Connected to device vid:did:rid of 1ae0:0028:00
439 19:22:44.785569 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
440 19:22:44.876032 Initialized TPM device CR50 revision 0
441 19:22:44.902854 tlcl_send_startup: Startup return code is 0
442 19:22:44.903525 TPM: setup succeeded
443 19:22:44.917117 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 19:22:44.926422 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 19:22:44.938107 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 19:22:44.947616 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 19:22:44.951042 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 19:22:44.954487 in-header: 03 07 00 00 08 00 00 00
449 19:22:44.958065 in-data: aa e4 47 04 13 02 00 00
450 19:22:44.961173 Chrome EC: UHEPI supported
451 19:22:44.967959 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 19:22:44.971824 in-header: 03 ad 00 00 08 00 00 00
453 19:22:44.974800 in-data: 00 20 20 08 00 00 00 00
454 19:22:44.975379 Phase 1
455 19:22:44.978589 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 19:22:44.985371 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 19:22:44.988764 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 19:22:44.992137 Recovery requested (1009000e)
459 19:22:45.000603 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 19:22:45.006114 tlcl_extend: response is 0
461 19:22:45.015639 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 19:22:45.021075 tlcl_extend: response is 0
463 19:22:45.028468 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 19:22:45.048494 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 19:22:45.054678 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 19:22:45.055379
467 19:22:45.055982
468 19:22:45.064786 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 19:22:45.068322 ARM64: Exception handlers installed.
470 19:22:45.071641 ARM64: Testing exception
471 19:22:45.072197 ARM64: Done test exception
472 19:22:45.093365 pmic_efuse_setting: Set efuses in 11 msecs
473 19:22:45.096526 pmwrap_interface_init: Select PMIF_VLD_RDY
474 19:22:45.103685 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 19:22:45.106887 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 19:22:45.113715 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 19:22:45.116852 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 19:22:45.120380 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 19:22:45.127035 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 19:22:45.130133 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 19:22:45.137366 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 19:22:45.140470 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 19:22:45.147479 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 19:22:45.150542 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 19:22:45.153626 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 19:22:45.160906 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 19:22:45.167058 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 19:22:45.170835 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 19:22:45.177321 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 19:22:45.183957 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 19:22:45.187178 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 19:22:45.194017 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 19:22:45.200679 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 19:22:45.203748 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 19:22:45.210542 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 19:22:45.217481 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 19:22:45.220626 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 19:22:45.227552 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 19:22:45.234215 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 19:22:45.237332 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 19:22:45.244509 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 19:22:45.247513 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 19:22:45.250988 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 19:22:45.258076 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 19:22:45.261538 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 19:22:45.267710 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 19:22:45.271091 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 19:22:45.278141 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 19:22:45.281299 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 19:22:45.287872 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 19:22:45.291272 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 19:22:45.298046 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 19:22:45.301058 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 19:22:45.304844 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 19:22:45.311410 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 19:22:45.314719 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 19:22:45.317813 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 19:22:45.321976 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 19:22:45.328121 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 19:22:45.331673 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 19:22:45.334727 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 19:22:45.341813 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 19:22:45.344852 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 19:22:45.348622 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 19:22:45.354804 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 19:22:45.365294 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 19:22:45.368311 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 19:22:45.378351 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 19:22:45.384969 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 19:22:45.391801 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 19:22:45.395475 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 19:22:45.398510 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 19:22:45.405961 [RTC]rtc_enable_dcxo,68: con=0x406, osc32con=0xde6f, sec=0x8
534 19:22:45.412549 [RTC]rtc_check_state,173: con=406, pwrkey1=a357, pwrkey2=67d2
535 19:22:45.416356 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
536 19:22:45.419367 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 19:22:45.430673 [RTC]rtc_get_frequency_meter,154: input=15, output=791
538 19:22:45.440066 [RTC]rtc_get_frequency_meter,154: input=23, output=979
539 19:22:45.449822 [RTC]rtc_get_frequency_meter,154: input=19, output=885
540 19:22:45.458947 [RTC]rtc_get_frequency_meter,154: input=17, output=839
541 19:22:45.468845 [RTC]rtc_get_frequency_meter,154: input=16, output=815
542 19:22:45.478104 [RTC]rtc_get_frequency_meter,154: input=15, output=790
543 19:22:45.487887 [RTC]rtc_get_frequency_meter,154: input=16, output=814
544 19:22:45.491055 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
545 19:22:45.498409 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
546 19:22:45.501499 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 19:22:45.505054 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
548 19:22:45.511472 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 19:22:45.515082 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
550 19:22:45.518033 ADC[4]: Raw value=900959 ID=7
551 19:22:45.518657 ADC[3]: Raw value=213336 ID=1
552 19:22:45.521323 RAM Code: 0x71
553 19:22:45.525106 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 19:22:45.531706 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 19:22:45.538050 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 19:22:45.544681 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 19:22:45.548129 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 19:22:45.551628 in-header: 03 07 00 00 08 00 00 00
559 19:22:45.554744 in-data: aa e4 47 04 13 02 00 00
560 19:22:45.558179 Chrome EC: UHEPI supported
561 19:22:45.564876 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 19:22:45.568349 in-header: 03 ed 00 00 08 00 00 00
563 19:22:45.571624 in-data: 80 20 60 08 00 00 00 00
564 19:22:45.574580 MRC: failed to locate region type 0.
565 19:22:45.582058 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 19:22:45.585605 DRAM-K: Running full calibration
567 19:22:45.589727 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 19:22:45.593407 header.status = 0x0
569 19:22:45.597248 header.version = 0x6 (expected: 0x6)
570 19:22:45.600336 header.size = 0xd00 (expected: 0xd00)
571 19:22:45.600857 header.flags = 0x0
572 19:22:45.607489 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 19:22:45.624235 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
574 19:22:45.631044 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 19:22:45.634247 dram_init: ddr_geometry: 2
576 19:22:45.634835 [EMI] MDL number = 2
577 19:22:45.637593 [EMI] Get MDL freq = 0
578 19:22:45.640868 dram_init: ddr_type: 0
579 19:22:45.641602 is_discrete_lpddr4: 1
580 19:22:45.644694 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 19:22:45.645351
582 19:22:45.645942
583 19:22:45.647708 [Bian_co] ETT version 0.0.0.1
584 19:22:45.654838 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 19:22:45.655479
586 19:22:45.657737 dramc_set_vcore_voltage set vcore to 650000
587 19:22:45.658190 Read voltage for 800, 4
588 19:22:45.661653 Vio18 = 0
589 19:22:45.662082 Vcore = 650000
590 19:22:45.662594 Vdram = 0
591 19:22:45.664930 Vddq = 0
592 19:22:45.665418 Vmddr = 0
593 19:22:45.668217 dram_init: config_dvfs: 1
594 19:22:45.671320 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 19:22:45.678208 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 19:22:45.681455 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
597 19:22:45.684774 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
598 19:22:45.688256 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
599 19:22:45.691178 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
600 19:22:45.694887 MEM_TYPE=3, freq_sel=18
601 19:22:45.697966 sv_algorithm_assistance_LP4_1600
602 19:22:45.701684 ============ PULL DRAM RESETB DOWN ============
603 19:22:45.704400 ========== PULL DRAM RESETB DOWN end =========
604 19:22:45.711223 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 19:22:45.714852 ===================================
606 19:22:45.714946 LPDDR4 DRAM CONFIGURATION
607 19:22:45.717864 ===================================
608 19:22:45.721565 EX_ROW_EN[0] = 0x0
609 19:22:45.724702 EX_ROW_EN[1] = 0x0
610 19:22:45.724782 LP4Y_EN = 0x0
611 19:22:45.728107 WORK_FSP = 0x0
612 19:22:45.728231 WL = 0x2
613 19:22:45.731238 RL = 0x2
614 19:22:45.731323 BL = 0x2
615 19:22:45.734905 RPST = 0x0
616 19:22:45.735026 RD_PRE = 0x0
617 19:22:45.738240 WR_PRE = 0x1
618 19:22:45.738333 WR_PST = 0x0
619 19:22:45.741287 DBI_WR = 0x0
620 19:22:45.741370 DBI_RD = 0x0
621 19:22:45.744957 OTF = 0x1
622 19:22:45.747907 ===================================
623 19:22:45.751404 ===================================
624 19:22:45.751511 ANA top config
625 19:22:45.754783 ===================================
626 19:22:45.758547 DLL_ASYNC_EN = 0
627 19:22:45.761803 ALL_SLAVE_EN = 1
628 19:22:45.761894 NEW_RANK_MODE = 1
629 19:22:45.764894 DLL_IDLE_MODE = 1
630 19:22:45.768680 LP45_APHY_COMB_EN = 1
631 19:22:45.772131 TX_ODT_DIS = 1
632 19:22:45.772239 NEW_8X_MODE = 1
633 19:22:45.775580 ===================================
634 19:22:45.779215 ===================================
635 19:22:45.782943 data_rate = 1600
636 19:22:45.786564 CKR = 1
637 19:22:45.790180 DQ_P2S_RATIO = 8
638 19:22:45.790265 ===================================
639 19:22:45.793986 CA_P2S_RATIO = 8
640 19:22:45.797696 DQ_CA_OPEN = 0
641 19:22:45.801387 DQ_SEMI_OPEN = 0
642 19:22:45.801477 CA_SEMI_OPEN = 0
643 19:22:45.805086 CA_FULL_RATE = 0
644 19:22:45.808541 DQ_CKDIV4_EN = 1
645 19:22:45.812312 CA_CKDIV4_EN = 1
646 19:22:45.812402 CA_PREDIV_EN = 0
647 19:22:45.815556 PH8_DLY = 0
648 19:22:45.819098 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 19:22:45.822840 DQ_AAMCK_DIV = 4
650 19:22:45.825886 CA_AAMCK_DIV = 4
651 19:22:45.825968 CA_ADMCK_DIV = 4
652 19:22:45.829074 DQ_TRACK_CA_EN = 0
653 19:22:45.832660 CA_PICK = 800
654 19:22:45.835679 CA_MCKIO = 800
655 19:22:45.839734 MCKIO_SEMI = 0
656 19:22:45.842531 PLL_FREQ = 3068
657 19:22:45.842630 DQ_UI_PI_RATIO = 32
658 19:22:45.845804 CA_UI_PI_RATIO = 0
659 19:22:45.849527 ===================================
660 19:22:45.853001 ===================================
661 19:22:45.856057 memory_type:LPDDR4
662 19:22:45.859448 GP_NUM : 10
663 19:22:45.859525 SRAM_EN : 1
664 19:22:45.862954 MD32_EN : 0
665 19:22:45.866115 ===================================
666 19:22:45.869543 [ANA_INIT] >>>>>>>>>>>>>>
667 19:22:45.869622 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 19:22:45.872922 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 19:22:45.877081 ===================================
670 19:22:45.880778 data_rate = 1600,PCW = 0X7600
671 19:22:45.884180 ===================================
672 19:22:45.887840 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 19:22:45.891570 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 19:22:45.898812 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 19:22:45.902527 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 19:22:45.906341 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 19:22:45.909371 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 19:22:45.913650 [ANA_INIT] flow start
679 19:22:45.913795 [ANA_INIT] PLL >>>>>>>>
680 19:22:45.916821 [ANA_INIT] PLL <<<<<<<<
681 19:22:45.916953 [ANA_INIT] MIDPI >>>>>>>>
682 19:22:45.920643 [ANA_INIT] MIDPI <<<<<<<<
683 19:22:45.924666 [ANA_INIT] DLL >>>>>>>>
684 19:22:45.924756 [ANA_INIT] flow end
685 19:22:45.928511 ============ LP4 DIFF to SE enter ============
686 19:22:45.931570 ============ LP4 DIFF to SE exit ============
687 19:22:45.935982 [ANA_INIT] <<<<<<<<<<<<<
688 19:22:45.939226 [Flow] Enable top DCM control >>>>>
689 19:22:45.942995 [Flow] Enable top DCM control <<<<<
690 19:22:45.947256 Enable DLL master slave shuffle
691 19:22:45.950935 ==============================================================
692 19:22:45.951021 Gating Mode config
693 19:22:45.958280 ==============================================================
694 19:22:45.958377 Config description:
695 19:22:45.969244 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 19:22:45.976931 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 19:22:45.980452 SELPH_MODE 0: By rank 1: By Phase
698 19:22:45.987210 ==============================================================
699 19:22:45.989993 GAT_TRACK_EN = 1
700 19:22:45.993590 RX_GATING_MODE = 2
701 19:22:45.996775 RX_GATING_TRACK_MODE = 2
702 19:22:45.996862 SELPH_MODE = 1
703 19:22:46.000328 PICG_EARLY_EN = 1
704 19:22:46.004028 VALID_LAT_VALUE = 1
705 19:22:46.011266 ==============================================================
706 19:22:46.014444 Enter into Gating configuration >>>>
707 19:22:46.017533 Exit from Gating configuration <<<<
708 19:22:46.021113 Enter into DVFS_PRE_config >>>>>
709 19:22:46.031018 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 19:22:46.034781 Exit from DVFS_PRE_config <<<<<
711 19:22:46.037875 Enter into PICG configuration >>>>
712 19:22:46.040841 Exit from PICG configuration <<<<
713 19:22:46.044560 [RX_INPUT] configuration >>>>>
714 19:22:46.044646 [RX_INPUT] configuration <<<<<
715 19:22:46.051392 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 19:22:46.058028 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 19:22:46.061584 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 19:22:46.068948 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 19:22:46.076663 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 19:22:46.079706 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 19:22:46.083814 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 19:22:46.087270 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 19:22:46.095042 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 19:22:46.098235 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 19:22:46.102462 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 19:22:46.106378 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 19:22:46.109866 ===================================
728 19:22:46.113432 LPDDR4 DRAM CONFIGURATION
729 19:22:46.117495 ===================================
730 19:22:46.117923 EX_ROW_EN[0] = 0x0
731 19:22:46.121187 EX_ROW_EN[1] = 0x0
732 19:22:46.121770 LP4Y_EN = 0x0
733 19:22:46.122309 WORK_FSP = 0x0
734 19:22:46.124874 WL = 0x2
735 19:22:46.125386 RL = 0x2
736 19:22:46.128636 BL = 0x2
737 19:22:46.129106 RPST = 0x0
738 19:22:46.132199 RD_PRE = 0x0
739 19:22:46.132869 WR_PRE = 0x1
740 19:22:46.135927 WR_PST = 0x0
741 19:22:46.136355 DBI_WR = 0x0
742 19:22:46.139716 DBI_RD = 0x0
743 19:22:46.140176 OTF = 0x1
744 19:22:46.143526 ===================================
745 19:22:46.147228 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 19:22:46.150864 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 19:22:46.154188 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 19:22:46.158324 ===================================
749 19:22:46.162177 LPDDR4 DRAM CONFIGURATION
750 19:22:46.165955 ===================================
751 19:22:46.166048 EX_ROW_EN[0] = 0x10
752 19:22:46.169425 EX_ROW_EN[1] = 0x0
753 19:22:46.169506 LP4Y_EN = 0x0
754 19:22:46.173016 WORK_FSP = 0x0
755 19:22:46.173108 WL = 0x2
756 19:22:46.176863 RL = 0x2
757 19:22:46.176948 BL = 0x2
758 19:22:46.180362 RPST = 0x0
759 19:22:46.180444 RD_PRE = 0x0
760 19:22:46.184175 WR_PRE = 0x1
761 19:22:46.184255 WR_PST = 0x0
762 19:22:46.187768 DBI_WR = 0x0
763 19:22:46.187906 DBI_RD = 0x0
764 19:22:46.187972 OTF = 0x1
765 19:22:46.191280 ===================================
766 19:22:46.198211 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 19:22:46.202734 nWR fixed to 40
768 19:22:46.206396 [ModeRegInit_LP4] CH0 RK0
769 19:22:46.206478 [ModeRegInit_LP4] CH0 RK1
770 19:22:46.210570 [ModeRegInit_LP4] CH1 RK0
771 19:22:46.210662 [ModeRegInit_LP4] CH1 RK1
772 19:22:46.213546 match AC timing 13
773 19:22:46.217241 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 19:22:46.221042 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 19:22:46.224840 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 19:22:46.232122 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 19:22:46.236250 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 19:22:46.236333 [EMI DOE] emi_dcm 0
779 19:22:46.243014 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 19:22:46.243128 ==
781 19:22:46.246773 Dram Type= 6, Freq= 0, CH_0, rank 0
782 19:22:46.250636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 19:22:46.250722 ==
784 19:22:46.254273 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 19:22:46.260975 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 19:22:46.270304 [CA 0] Center 37 (7~68) winsize 62
787 19:22:46.274508 [CA 1] Center 37 (6~68) winsize 63
788 19:22:46.278162 [CA 2] Center 35 (5~66) winsize 62
789 19:22:46.282038 [CA 3] Center 34 (4~65) winsize 62
790 19:22:46.285021 [CA 4] Center 34 (3~65) winsize 63
791 19:22:46.285124 [CA 5] Center 33 (3~64) winsize 62
792 19:22:46.288629
793 19:22:46.292519 [CmdBusTrainingLP45] Vref(ca) range 1: 32
794 19:22:46.292599
795 19:22:46.296327 [CATrainingPosCal] consider 1 rank data
796 19:22:46.296415 u2DelayCellTimex100 = 270/100 ps
797 19:22:46.300114 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
798 19:22:46.303403 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
799 19:22:46.308040 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
800 19:22:46.311328 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
801 19:22:46.315511 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
802 19:22:46.319224 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 19:22:46.319307
804 19:22:46.323125 CA PerBit enable=1, Macro0, CA PI delay=33
805 19:22:46.323208
806 19:22:46.326617 [CBTSetCACLKResult] CA Dly = 33
807 19:22:46.326710 CS Dly: 5 (0~36)
808 19:22:46.330382 ==
809 19:22:46.330455 Dram Type= 6, Freq= 0, CH_0, rank 1
810 19:22:46.338045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 19:22:46.338668 ==
812 19:22:46.341700 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 19:22:46.348870 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 19:22:46.357362 [CA 0] Center 37 (6~68) winsize 63
815 19:22:46.360975 [CA 1] Center 37 (6~68) winsize 63
816 19:22:46.364781 [CA 2] Center 35 (5~66) winsize 62
817 19:22:46.368331 [CA 3] Center 35 (4~66) winsize 63
818 19:22:46.372064 [CA 4] Center 34 (3~65) winsize 63
819 19:22:46.372537 [CA 5] Center 33 (3~64) winsize 62
820 19:22:46.375803
821 19:22:46.376214 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 19:22:46.379458
823 19:22:46.383190 [CATrainingPosCal] consider 2 rank data
824 19:22:46.383814 u2DelayCellTimex100 = 270/100 ps
825 19:22:46.386996 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
826 19:22:46.390563 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
827 19:22:46.394264 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
828 19:22:46.398130 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
829 19:22:46.401770 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
830 19:22:46.405275 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 19:22:46.405721
832 19:22:46.409300 CA PerBit enable=1, Macro0, CA PI delay=33
833 19:22:46.409746
834 19:22:46.412903 [CBTSetCACLKResult] CA Dly = 33
835 19:22:46.416316 CS Dly: 6 (0~38)
836 19:22:46.416761
837 19:22:46.420321 ----->DramcWriteLeveling(PI) begin...
838 19:22:46.420802 ==
839 19:22:46.421303 Dram Type= 6, Freq= 0, CH_0, rank 0
840 19:22:46.427945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 19:22:46.428394 ==
842 19:22:46.428850 Write leveling (Byte 0): 29 => 29
843 19:22:46.431813 Write leveling (Byte 1): 29 => 29
844 19:22:46.435338 DramcWriteLeveling(PI) end<-----
845 19:22:46.435908
846 19:22:46.436447 ==
847 19:22:46.438881 Dram Type= 6, Freq= 0, CH_0, rank 0
848 19:22:46.442977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 19:22:46.443452 ==
850 19:22:46.446469 [Gating] SW mode calibration
851 19:22:46.454073 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 19:22:46.457854 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 19:22:46.461690 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 19:22:46.465297 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
855 19:22:46.472845 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
856 19:22:46.476296 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
857 19:22:46.479918 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 19:22:46.483392 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 19:22:46.487766 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 19:22:46.494499 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 19:22:46.498260 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 19:22:46.502040 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 19:22:46.505793 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 19:22:46.509554 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 19:22:46.516811 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 19:22:46.520337 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 19:22:46.524299 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 19:22:46.528244 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 19:22:46.532174 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 19:22:46.535775 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 19:22:46.543127 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
872 19:22:46.546345 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
873 19:22:46.549991 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 19:22:46.553794 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 19:22:46.557324 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 19:22:46.564499 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 19:22:46.568451 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 19:22:46.572367 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 19:22:46.575799 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
880 19:22:46.579597 0 9 12 | B1->B0 | 2727 3131 | 1 0 | (0 0) (0 0)
881 19:22:46.586100 0 9 16 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
882 19:22:46.589675 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 19:22:46.592742 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 19:22:46.599657 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 19:22:46.602693 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 19:22:46.606429 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
887 19:22:46.613322 0 10 8 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
888 19:22:46.616198 0 10 12 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
889 19:22:46.619934 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 19:22:46.626426 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 19:22:46.629865 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 19:22:46.633148 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 19:22:46.636446 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 19:22:46.643419 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
895 19:22:46.646788 0 11 8 | B1->B0 | 2323 2c2c | 1 1 | (0 0) (0 0)
896 19:22:46.649922 0 11 12 | B1->B0 | 3939 4141 | 0 0 | (0 0) (0 0)
897 19:22:46.656868 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 19:22:46.659972 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 19:22:46.663488 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 19:22:46.670133 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 19:22:46.673499 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 19:22:46.676646 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
903 19:22:46.683716 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
904 19:22:46.686713 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
905 19:22:46.690523 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 19:22:46.693937 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 19:22:46.700114 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 19:22:46.703833 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 19:22:46.707149 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 19:22:46.713841 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 19:22:46.716958 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 19:22:46.720535 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 19:22:46.727379 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 19:22:46.731070 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 19:22:46.733909 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 19:22:46.740464 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 19:22:46.743840 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 19:22:46.747275 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
919 19:22:46.750589 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
920 19:22:46.757323 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
921 19:22:46.761097 Total UI for P1: 0, mck2ui 16
922 19:22:46.764092 best dqsien dly found for B0: ( 0, 14, 8)
923 19:22:46.767488 Total UI for P1: 0, mck2ui 16
924 19:22:46.771400 best dqsien dly found for B1: ( 0, 14, 10)
925 19:22:46.774316 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
926 19:22:46.777189 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
927 19:22:46.777668
928 19:22:46.780509 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
929 19:22:46.783920 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
930 19:22:46.787465 [Gating] SW calibration Done
931 19:22:46.787898 ==
932 19:22:46.790717 Dram Type= 6, Freq= 0, CH_0, rank 0
933 19:22:46.794266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 19:22:46.794834 ==
935 19:22:46.797842 RX Vref Scan: 0
936 19:22:46.798313
937 19:22:46.798835 RX Vref 0 -> 0, step: 1
938 19:22:46.799436
939 19:22:46.800848 RX Delay -130 -> 252, step: 16
940 19:22:46.804538 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
941 19:22:46.811388 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
942 19:22:46.814374 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
943 19:22:46.817786 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
944 19:22:46.821004 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
945 19:22:46.824871 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
946 19:22:46.828355 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
947 19:22:46.835538 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
948 19:22:46.839084 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
949 19:22:46.843300 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
950 19:22:46.846430 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
951 19:22:46.850707 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
952 19:22:46.854720 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
953 19:22:46.858758 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
954 19:22:46.862144 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
955 19:22:46.865650 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
956 19:22:46.866095 ==
957 19:22:46.869254 Dram Type= 6, Freq= 0, CH_0, rank 0
958 19:22:46.872482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 19:22:46.872880 ==
960 19:22:46.875389 DQS Delay:
961 19:22:46.876066 DQS0 = 0, DQS1 = 0
962 19:22:46.878909 DQM Delay:
963 19:22:46.879513 DQM0 = 89, DQM1 = 81
964 19:22:46.879938 DQ Delay:
965 19:22:46.882189 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
966 19:22:46.885678 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
967 19:22:46.889185 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
968 19:22:46.892516 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =93
969 19:22:46.893008
970 19:22:46.893627
971 19:22:46.895943 ==
972 19:22:46.896419 Dram Type= 6, Freq= 0, CH_0, rank 0
973 19:22:46.902487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 19:22:46.902937 ==
975 19:22:46.903278
976 19:22:46.903598
977 19:22:46.905953 TX Vref Scan disable
978 19:22:46.906392 == TX Byte 0 ==
979 19:22:46.908993 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
980 19:22:46.915927 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
981 19:22:46.916482 == TX Byte 1 ==
982 19:22:46.919448 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
983 19:22:46.926751 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
984 19:22:46.927228 ==
985 19:22:46.929592 Dram Type= 6, Freq= 0, CH_0, rank 0
986 19:22:46.932811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 19:22:46.933282 ==
988 19:22:46.945465 TX Vref=22, minBit 5, minWin=26, winSum=438
989 19:22:46.949303 TX Vref=24, minBit 5, minWin=27, winSum=444
990 19:22:46.952454 TX Vref=26, minBit 5, minWin=27, winSum=446
991 19:22:46.955497 TX Vref=28, minBit 15, minWin=27, winSum=449
992 19:22:46.958994 TX Vref=30, minBit 1, minWin=28, winSum=451
993 19:22:46.962600 TX Vref=32, minBit 3, minWin=27, winSum=452
994 19:22:46.969175 [TxChooseVref] Worse bit 1, Min win 28, Win sum 451, Final Vref 30
995 19:22:46.969782
996 19:22:46.972842 Final TX Range 1 Vref 30
997 19:22:46.973445
998 19:22:46.973794 ==
999 19:22:46.975683 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 19:22:46.979219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 19:22:46.979652 ==
1002 19:22:46.979993
1003 19:22:46.980310
1004 19:22:46.982512 TX Vref Scan disable
1005 19:22:46.985866 == TX Byte 0 ==
1006 19:22:46.989459 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1007 19:22:46.992650 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1008 19:22:46.995610 == TX Byte 1 ==
1009 19:22:46.999084 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1010 19:22:47.002816 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1011 19:22:47.003247
1012 19:22:47.005811 [DATLAT]
1013 19:22:47.006238 Freq=800, CH0 RK0
1014 19:22:47.006576
1015 19:22:47.009486 DATLAT Default: 0xa
1016 19:22:47.009962 0, 0xFFFF, sum = 0
1017 19:22:47.012743 1, 0xFFFF, sum = 0
1018 19:22:47.013183 2, 0xFFFF, sum = 0
1019 19:22:47.015975 3, 0xFFFF, sum = 0
1020 19:22:47.016551 4, 0xFFFF, sum = 0
1021 19:22:47.019644 5, 0xFFFF, sum = 0
1022 19:22:47.020077 6, 0xFFFF, sum = 0
1023 19:22:47.022589 7, 0xFFFF, sum = 0
1024 19:22:47.022995 8, 0xFFFF, sum = 0
1025 19:22:47.026300 9, 0x0, sum = 1
1026 19:22:47.026755 10, 0x0, sum = 2
1027 19:22:47.029961 11, 0x0, sum = 3
1028 19:22:47.030401 12, 0x0, sum = 4
1029 19:22:47.032998 best_step = 10
1030 19:22:47.033516
1031 19:22:47.033849 ==
1032 19:22:47.036705 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 19:22:47.039736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 19:22:47.040159 ==
1035 19:22:47.040491 RX Vref Scan: 1
1036 19:22:47.042780
1037 19:22:47.043197 Set Vref Range= 32 -> 127
1038 19:22:47.043559
1039 19:22:47.046182 RX Vref 32 -> 127, step: 1
1040 19:22:47.046602
1041 19:22:47.049835 RX Delay -95 -> 252, step: 8
1042 19:22:47.050268
1043 19:22:47.053067 Set Vref, RX VrefLevel [Byte0]: 32
1044 19:22:47.056722 [Byte1]: 32
1045 19:22:47.057141
1046 19:22:47.059634 Set Vref, RX VrefLevel [Byte0]: 33
1047 19:22:47.063282 [Byte1]: 33
1048 19:22:47.063749
1049 19:22:47.066712 Set Vref, RX VrefLevel [Byte0]: 34
1050 19:22:47.069893 [Byte1]: 34
1051 19:22:47.073540
1052 19:22:47.073957 Set Vref, RX VrefLevel [Byte0]: 35
1053 19:22:47.077180 [Byte1]: 35
1054 19:22:47.080992
1055 19:22:47.081496 Set Vref, RX VrefLevel [Byte0]: 36
1056 19:22:47.084309 [Byte1]: 36
1057 19:22:47.088438
1058 19:22:47.089002 Set Vref, RX VrefLevel [Byte0]: 37
1059 19:22:47.091740 [Byte1]: 37
1060 19:22:47.096171
1061 19:22:47.096587 Set Vref, RX VrefLevel [Byte0]: 38
1062 19:22:47.099591 [Byte1]: 38
1063 19:22:47.103776
1064 19:22:47.104270 Set Vref, RX VrefLevel [Byte0]: 39
1065 19:22:47.107159 [Byte1]: 39
1066 19:22:47.111481
1067 19:22:47.111897 Set Vref, RX VrefLevel [Byte0]: 40
1068 19:22:47.114540 [Byte1]: 40
1069 19:22:47.119206
1070 19:22:47.119654 Set Vref, RX VrefLevel [Byte0]: 41
1071 19:22:47.122076 [Byte1]: 41
1072 19:22:47.126661
1073 19:22:47.127123 Set Vref, RX VrefLevel [Byte0]: 42
1074 19:22:47.130142 [Byte1]: 42
1075 19:22:47.134550
1076 19:22:47.134980 Set Vref, RX VrefLevel [Byte0]: 43
1077 19:22:47.137522 [Byte1]: 43
1078 19:22:47.141894
1079 19:22:47.142312 Set Vref, RX VrefLevel [Byte0]: 44
1080 19:22:47.145500 [Byte1]: 44
1081 19:22:47.149177
1082 19:22:47.149652 Set Vref, RX VrefLevel [Byte0]: 45
1083 19:22:47.152512 [Byte1]: 45
1084 19:22:47.157057
1085 19:22:47.157556 Set Vref, RX VrefLevel [Byte0]: 46
1086 19:22:47.160072 [Byte1]: 46
1087 19:22:47.164988
1088 19:22:47.165522 Set Vref, RX VrefLevel [Byte0]: 47
1089 19:22:47.167912 [Byte1]: 47
1090 19:22:47.172690
1091 19:22:47.173125 Set Vref, RX VrefLevel [Byte0]: 48
1092 19:22:47.175451 [Byte1]: 48
1093 19:22:47.179728
1094 19:22:47.180144 Set Vref, RX VrefLevel [Byte0]: 49
1095 19:22:47.183327 [Byte1]: 49
1096 19:22:47.187781
1097 19:22:47.188197 Set Vref, RX VrefLevel [Byte0]: 50
1098 19:22:47.190750 [Byte1]: 50
1099 19:22:47.195164
1100 19:22:47.195583 Set Vref, RX VrefLevel [Byte0]: 51
1101 19:22:47.198779 [Byte1]: 51
1102 19:22:47.202671
1103 19:22:47.203088 Set Vref, RX VrefLevel [Byte0]: 52
1104 19:22:47.205745 [Byte1]: 52
1105 19:22:47.209997
1106 19:22:47.210586 Set Vref, RX VrefLevel [Byte0]: 53
1107 19:22:47.213361 [Byte1]: 53
1108 19:22:47.217611
1109 19:22:47.218143 Set Vref, RX VrefLevel [Byte0]: 54
1110 19:22:47.221061 [Byte1]: 54
1111 19:22:47.225335
1112 19:22:47.225950 Set Vref, RX VrefLevel [Byte0]: 55
1113 19:22:47.228907 [Byte1]: 55
1114 19:22:47.232999
1115 19:22:47.233602 Set Vref, RX VrefLevel [Byte0]: 56
1116 19:22:47.236286 [Byte1]: 56
1117 19:22:47.240387
1118 19:22:47.240962 Set Vref, RX VrefLevel [Byte0]: 57
1119 19:22:47.243631 [Byte1]: 57
1120 19:22:47.247932
1121 19:22:47.248497 Set Vref, RX VrefLevel [Byte0]: 58
1122 19:22:47.251634 [Byte1]: 58
1123 19:22:47.255744
1124 19:22:47.256359 Set Vref, RX VrefLevel [Byte0]: 59
1125 19:22:47.258869 [Byte1]: 59
1126 19:22:47.263818
1127 19:22:47.264420 Set Vref, RX VrefLevel [Byte0]: 60
1128 19:22:47.266815 [Byte1]: 60
1129 19:22:47.271146
1130 19:22:47.271756 Set Vref, RX VrefLevel [Byte0]: 61
1131 19:22:47.274186 [Byte1]: 61
1132 19:22:47.278347
1133 19:22:47.278955 Set Vref, RX VrefLevel [Byte0]: 62
1134 19:22:47.281634 [Byte1]: 62
1135 19:22:47.285890
1136 19:22:47.286311 Set Vref, RX VrefLevel [Byte0]: 63
1137 19:22:47.289709 [Byte1]: 63
1138 19:22:47.293521
1139 19:22:47.293975 Set Vref, RX VrefLevel [Byte0]: 64
1140 19:22:47.297245 [Byte1]: 64
1141 19:22:47.301412
1142 19:22:47.302019 Set Vref, RX VrefLevel [Byte0]: 65
1143 19:22:47.304379 [Byte1]: 65
1144 19:22:47.308925
1145 19:22:47.309493 Set Vref, RX VrefLevel [Byte0]: 66
1146 19:22:47.312637 [Byte1]: 66
1147 19:22:47.316901
1148 19:22:47.317516 Set Vref, RX VrefLevel [Byte0]: 67
1149 19:22:47.319928 [Byte1]: 67
1150 19:22:47.323953
1151 19:22:47.324370 Set Vref, RX VrefLevel [Byte0]: 68
1152 19:22:47.327381 [Byte1]: 68
1153 19:22:47.331531
1154 19:22:47.331951 Set Vref, RX VrefLevel [Byte0]: 69
1155 19:22:47.335086 [Byte1]: 69
1156 19:22:47.339434
1157 19:22:47.340037 Set Vref, RX VrefLevel [Byte0]: 70
1158 19:22:47.342324 [Byte1]: 70
1159 19:22:47.346999
1160 19:22:47.347419 Set Vref, RX VrefLevel [Byte0]: 71
1161 19:22:47.350639 [Byte1]: 71
1162 19:22:47.354160
1163 19:22:47.354579 Set Vref, RX VrefLevel [Byte0]: 72
1164 19:22:47.358037 [Byte1]: 72
1165 19:22:47.362153
1166 19:22:47.362575 Set Vref, RX VrefLevel [Byte0]: 73
1167 19:22:47.365187 [Byte1]: 73
1168 19:22:47.370029
1169 19:22:47.370496 Set Vref, RX VrefLevel [Byte0]: 74
1170 19:22:47.373105 [Byte1]: 74
1171 19:22:47.377162
1172 19:22:47.377714 Set Vref, RX VrefLevel [Byte0]: 75
1173 19:22:47.381043 [Byte1]: 75
1174 19:22:47.384894
1175 19:22:47.385403 Set Vref, RX VrefLevel [Byte0]: 76
1176 19:22:47.388370 [Byte1]: 76
1177 19:22:47.392629
1178 19:22:47.393095 Set Vref, RX VrefLevel [Byte0]: 77
1179 19:22:47.395827 [Byte1]: 77
1180 19:22:47.400082
1181 19:22:47.400503 Final RX Vref Byte 0 = 60 to rank0
1182 19:22:47.403825 Final RX Vref Byte 1 = 58 to rank0
1183 19:22:47.406887 Final RX Vref Byte 0 = 60 to rank1
1184 19:22:47.410361 Final RX Vref Byte 1 = 58 to rank1==
1185 19:22:47.414068 Dram Type= 6, Freq= 0, CH_0, rank 0
1186 19:22:47.417768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1187 19:22:47.418224 ==
1188 19:22:47.421629 DQS Delay:
1189 19:22:47.422067 DQS0 = 0, DQS1 = 0
1190 19:22:47.422498 DQM Delay:
1191 19:22:47.425270 DQM0 = 87, DQM1 = 79
1192 19:22:47.425796 DQ Delay:
1193 19:22:47.428424 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1194 19:22:47.431913 DQ4 =84, DQ5 =76, DQ6 =96, DQ7 =96
1195 19:22:47.435468 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =76
1196 19:22:47.438911 DQ12 =84, DQ13 =80, DQ14 =92, DQ15 =88
1197 19:22:47.439336
1198 19:22:47.439669
1199 19:22:47.445537 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f16, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 397 ps
1200 19:22:47.449481 CH0 RK0: MR19=606, MR18=2F16
1201 19:22:47.455637 CH0_RK0: MR19=0x606, MR18=0x2F16, DQSOSC=397, MR23=63, INC=93, DEC=62
1202 19:22:47.455720
1203 19:22:47.459317 ----->DramcWriteLeveling(PI) begin...
1204 19:22:47.459430 ==
1205 19:22:47.462410 Dram Type= 6, Freq= 0, CH_0, rank 1
1206 19:22:47.465954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1207 19:22:47.466037 ==
1208 19:22:47.469435 Write leveling (Byte 0): 32 => 32
1209 19:22:47.472487 Write leveling (Byte 1): 33 => 33
1210 19:22:47.476206 DramcWriteLeveling(PI) end<-----
1211 19:22:47.476289
1212 19:22:47.476353 ==
1213 19:22:47.479260 Dram Type= 6, Freq= 0, CH_0, rank 1
1214 19:22:47.483128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1215 19:22:47.483219 ==
1216 19:22:47.485994 [Gating] SW mode calibration
1217 19:22:47.492860 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1218 19:22:47.499654 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1219 19:22:47.502949 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1220 19:22:47.506647 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1221 19:22:47.512979 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 19:22:47.516759 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 19:22:47.519847 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 19:22:47.526531 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 19:22:47.529819 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 19:22:47.533384 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 19:22:47.540128 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 19:22:47.543087 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 19:22:47.547179 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 19:22:47.553470 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 19:22:47.556665 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 19:22:47.559944 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 19:22:47.563333 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 19:22:47.569983 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 19:22:47.573838 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 19:22:47.576723 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1237 19:22:47.583868 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1238 19:22:47.586845 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 19:22:47.590590 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 19:22:47.596958 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 19:22:47.600198 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 19:22:47.603843 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 19:22:47.610847 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 19:22:47.613582 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 19:22:47.617289 0 9 8 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
1246 19:22:47.620212 0 9 12 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
1247 19:22:47.627388 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1248 19:22:47.630323 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1249 19:22:47.633776 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1250 19:22:47.640592 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1251 19:22:47.643709 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1252 19:22:47.647229 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
1253 19:22:47.653902 0 10 8 | B1->B0 | 3232 2424 | 0 0 | (0 1) (0 0)
1254 19:22:47.657363 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (1 1) (0 0)
1255 19:22:47.660824 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 19:22:47.667685 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 19:22:47.671132 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 19:22:47.673887 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 19:22:47.677784 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 19:22:47.684199 0 11 4 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
1261 19:22:47.687368 0 11 8 | B1->B0 | 2e2e 4141 | 0 0 | (0 0) (0 0)
1262 19:22:47.690924 0 11 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
1263 19:22:47.697491 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1264 19:22:47.701000 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1265 19:22:47.704603 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 19:22:47.711357 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1267 19:22:47.714371 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1268 19:22:47.717720 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1269 19:22:47.724712 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1270 19:22:47.727794 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 19:22:47.731480 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 19:22:47.738027 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 19:22:47.741044 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 19:22:47.744773 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 19:22:47.748264 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 19:22:47.754389 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 19:22:47.757961 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 19:22:47.761310 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 19:22:47.768108 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 19:22:47.771150 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 19:22:47.774635 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 19:22:47.780996 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 19:22:47.784467 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 19:22:47.788278 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1285 19:22:47.795005 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
1286 19:22:47.795462 Total UI for P1: 0, mck2ui 16
1287 19:22:47.801593 best dqsien dly found for B0: ( 0, 14, 4)
1288 19:22:47.805078 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1289 19:22:47.808240 Total UI for P1: 0, mck2ui 16
1290 19:22:47.811185 best dqsien dly found for B1: ( 0, 14, 10)
1291 19:22:47.814767 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1292 19:22:47.818198 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1293 19:22:47.818480
1294 19:22:47.821406 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1295 19:22:47.824504 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1296 19:22:47.828211 [Gating] SW calibration Done
1297 19:22:47.828416 ==
1298 19:22:47.831196 Dram Type= 6, Freq= 0, CH_0, rank 1
1299 19:22:47.834938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1300 19:22:47.835088 ==
1301 19:22:47.838036 RX Vref Scan: 0
1302 19:22:47.838181
1303 19:22:47.838324 RX Vref 0 -> 0, step: 1
1304 19:22:47.841180
1305 19:22:47.841321 RX Delay -130 -> 252, step: 16
1306 19:22:47.847949 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1307 19:22:47.851556 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1308 19:22:47.854652 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1309 19:22:47.857808 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1310 19:22:47.861468 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1311 19:22:47.867876 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1312 19:22:47.871461 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1313 19:22:47.875254 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1314 19:22:47.878333 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1315 19:22:47.881582 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1316 19:22:47.884930 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1317 19:22:47.891742 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1318 19:22:47.895716 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1319 19:22:47.899135 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1320 19:22:47.901756 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1321 19:22:47.905546 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1322 19:22:47.908657 ==
1323 19:22:47.911964 Dram Type= 6, Freq= 0, CH_0, rank 1
1324 19:22:47.915603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1325 19:22:47.916061 ==
1326 19:22:47.916396 DQS Delay:
1327 19:22:47.918732 DQS0 = 0, DQS1 = 0
1328 19:22:47.919151 DQM Delay:
1329 19:22:47.922608 DQM0 = 86, DQM1 = 76
1330 19:22:47.923075 DQ Delay:
1331 19:22:47.925514 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1332 19:22:47.929128 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =93
1333 19:22:47.932216 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1334 19:22:47.935917 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1335 19:22:47.936342
1336 19:22:47.936673
1337 19:22:47.936981 ==
1338 19:22:47.938930 Dram Type= 6, Freq= 0, CH_0, rank 1
1339 19:22:47.942616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1340 19:22:47.943073 ==
1341 19:22:47.943411
1342 19:22:47.943743
1343 19:22:47.945699 TX Vref Scan disable
1344 19:22:47.949280 == TX Byte 0 ==
1345 19:22:47.952432 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1346 19:22:47.956212 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1347 19:22:47.956635 == TX Byte 1 ==
1348 19:22:47.962560 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1349 19:22:47.966137 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1350 19:22:47.966558 ==
1351 19:22:47.969194 Dram Type= 6, Freq= 0, CH_0, rank 1
1352 19:22:47.972923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1353 19:22:47.973486 ==
1354 19:22:47.986409 TX Vref=22, minBit 5, minWin=27, winSum=447
1355 19:22:47.989847 TX Vref=24, minBit 0, minWin=28, winSum=451
1356 19:22:47.993476 TX Vref=26, minBit 2, minWin=28, winSum=452
1357 19:22:47.996829 TX Vref=28, minBit 9, minWin=27, winSum=456
1358 19:22:47.999756 TX Vref=30, minBit 2, minWin=28, winSum=455
1359 19:22:48.003551 TX Vref=32, minBit 2, minWin=28, winSum=454
1360 19:22:48.010092 [TxChooseVref] Worse bit 2, Min win 28, Win sum 455, Final Vref 30
1361 19:22:48.010514
1362 19:22:48.013264 Final TX Range 1 Vref 30
1363 19:22:48.013709
1364 19:22:48.014046 ==
1365 19:22:48.017109 Dram Type= 6, Freq= 0, CH_0, rank 1
1366 19:22:48.020252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1367 19:22:48.020673 ==
1368 19:22:48.021003
1369 19:22:48.021357
1370 19:22:48.023558 TX Vref Scan disable
1371 19:22:48.026530 == TX Byte 0 ==
1372 19:22:48.029913 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1373 19:22:48.033361 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1374 19:22:48.037087 == TX Byte 1 ==
1375 19:22:48.040226 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1376 19:22:48.043411 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1377 19:22:48.043636
1378 19:22:48.046569 [DATLAT]
1379 19:22:48.046793 Freq=800, CH0 RK1
1380 19:22:48.046971
1381 19:22:48.049955 DATLAT Default: 0xa
1382 19:22:48.050186 0, 0xFFFF, sum = 0
1383 19:22:48.053597 1, 0xFFFF, sum = 0
1384 19:22:48.053825 2, 0xFFFF, sum = 0
1385 19:22:48.056708 3, 0xFFFF, sum = 0
1386 19:22:48.057088 4, 0xFFFF, sum = 0
1387 19:22:48.060592 5, 0xFFFF, sum = 0
1388 19:22:48.060870 6, 0xFFFF, sum = 0
1389 19:22:48.063691 7, 0xFFFF, sum = 0
1390 19:22:48.064124 8, 0xFFFF, sum = 0
1391 19:22:48.067218 9, 0x0, sum = 1
1392 19:22:48.067796 10, 0x0, sum = 2
1393 19:22:48.070399 11, 0x0, sum = 3
1394 19:22:48.070836 12, 0x0, sum = 4
1395 19:22:48.074149 best_step = 10
1396 19:22:48.074663
1397 19:22:48.074998 ==
1398 19:22:48.077058 Dram Type= 6, Freq= 0, CH_0, rank 1
1399 19:22:48.081156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1400 19:22:48.081802 ==
1401 19:22:48.082180 RX Vref Scan: 0
1402 19:22:48.082500
1403 19:22:48.084728 RX Vref 0 -> 0, step: 1
1404 19:22:48.085356
1405 19:22:48.088289 RX Delay -95 -> 252, step: 8
1406 19:22:48.092507 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
1407 19:22:48.095819 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1408 19:22:48.099617 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1409 19:22:48.102892 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1410 19:22:48.106955 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1411 19:22:48.110671 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1412 19:22:48.114555 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1413 19:22:48.121098 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1414 19:22:48.124683 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1415 19:22:48.127804 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1416 19:22:48.131522 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1417 19:22:48.135034 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1418 19:22:48.141457 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1419 19:22:48.144646 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1420 19:22:48.147572 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1421 19:22:48.151130 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1422 19:22:48.151432 ==
1423 19:22:48.154655 Dram Type= 6, Freq= 0, CH_0, rank 1
1424 19:22:48.158113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1425 19:22:48.161181 ==
1426 19:22:48.161384 DQS Delay:
1427 19:22:48.161527 DQS0 = 0, DQS1 = 0
1428 19:22:48.164299 DQM Delay:
1429 19:22:48.164449 DQM0 = 87, DQM1 = 78
1430 19:22:48.167399 DQ Delay:
1431 19:22:48.171200 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =84
1432 19:22:48.171333 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1433 19:22:48.174106 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1434 19:22:48.177641 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =88
1435 19:22:48.180797
1436 19:22:48.180915
1437 19:22:48.187649 [DQSOSCAuto] RK1, (LSB)MR18= 0x351f, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
1438 19:22:48.191282 CH0 RK1: MR19=606, MR18=351F
1439 19:22:48.197404 CH0_RK1: MR19=0x606, MR18=0x351F, DQSOSC=396, MR23=63, INC=94, DEC=62
1440 19:22:48.201113 [RxdqsGatingPostProcess] freq 800
1441 19:22:48.204091 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1442 19:22:48.207455 Pre-setting of DQS Precalculation
1443 19:22:48.214517 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1444 19:22:48.214607 ==
1445 19:22:48.217730 Dram Type= 6, Freq= 0, CH_1, rank 0
1446 19:22:48.220924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1447 19:22:48.221008 ==
1448 19:22:48.227329 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1449 19:22:48.230542 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1450 19:22:48.240896 [CA 0] Center 36 (6~66) winsize 61
1451 19:22:48.243981 [CA 1] Center 36 (6~66) winsize 61
1452 19:22:48.247521 [CA 2] Center 34 (4~65) winsize 62
1453 19:22:48.250983 [CA 3] Center 34 (3~65) winsize 63
1454 19:22:48.254134 [CA 4] Center 34 (3~65) winsize 63
1455 19:22:48.258136 [CA 5] Center 33 (3~64) winsize 62
1456 19:22:48.258219
1457 19:22:48.261419 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1458 19:22:48.261502
1459 19:22:48.264601 [CATrainingPosCal] consider 1 rank data
1460 19:22:48.267583 u2DelayCellTimex100 = 270/100 ps
1461 19:22:48.271156 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1462 19:22:48.274221 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1463 19:22:48.277937 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1464 19:22:48.284654 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1465 19:22:48.287667 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
1466 19:22:48.291406 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1467 19:22:48.291490
1468 19:22:48.294276 CA PerBit enable=1, Macro0, CA PI delay=33
1469 19:22:48.294359
1470 19:22:48.297799 [CBTSetCACLKResult] CA Dly = 33
1471 19:22:48.297883 CS Dly: 4 (0~35)
1472 19:22:48.297948 ==
1473 19:22:48.301466 Dram Type= 6, Freq= 0, CH_1, rank 1
1474 19:22:48.307695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1475 19:22:48.307780 ==
1476 19:22:48.311442 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1477 19:22:48.318233 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1478 19:22:48.327144 [CA 0] Center 36 (6~66) winsize 61
1479 19:22:48.330275 [CA 1] Center 36 (6~66) winsize 61
1480 19:22:48.333704 [CA 2] Center 34 (4~64) winsize 61
1481 19:22:48.336814 [CA 3] Center 33 (3~64) winsize 62
1482 19:22:48.340505 [CA 4] Center 34 (3~65) winsize 63
1483 19:22:48.343677 [CA 5] Center 33 (3~64) winsize 62
1484 19:22:48.343762
1485 19:22:48.346843 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1486 19:22:48.346926
1487 19:22:48.350487 [CATrainingPosCal] consider 2 rank data
1488 19:22:48.354218 u2DelayCellTimex100 = 270/100 ps
1489 19:22:48.357116 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1490 19:22:48.360436 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1491 19:22:48.363956 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1492 19:22:48.370522 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1493 19:22:48.373971 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
1494 19:22:48.376979 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1495 19:22:48.377062
1496 19:22:48.380633 CA PerBit enable=1, Macro0, CA PI delay=33
1497 19:22:48.380721
1498 19:22:48.384048 [CBTSetCACLKResult] CA Dly = 33
1499 19:22:48.384131 CS Dly: 4 (0~36)
1500 19:22:48.384197
1501 19:22:48.387666 ----->DramcWriteLeveling(PI) begin...
1502 19:22:48.387751 ==
1503 19:22:48.390774 Dram Type= 6, Freq= 0, CH_1, rank 0
1504 19:22:48.397408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1505 19:22:48.397494 ==
1506 19:22:48.400881 Write leveling (Byte 0): 26 => 26
1507 19:22:48.400963 Write leveling (Byte 1): 29 => 29
1508 19:22:48.404562 DramcWriteLeveling(PI) end<-----
1509 19:22:48.404644
1510 19:22:48.404709 ==
1511 19:22:48.407572 Dram Type= 6, Freq= 0, CH_1, rank 0
1512 19:22:48.414422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1513 19:22:48.414508 ==
1514 19:22:48.417480 [Gating] SW mode calibration
1515 19:22:48.424103 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1516 19:22:48.427775 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1517 19:22:48.431234 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1518 19:22:48.437515 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1519 19:22:48.440902 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1520 19:22:48.444004 0 6 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1521 19:22:48.451092 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 19:22:48.455035 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 19:22:48.458192 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 19:22:48.464818 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 19:22:48.468352 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 19:22:48.471698 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 19:22:48.478202 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 19:22:48.481422 0 7 12 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1529 19:22:48.484864 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 19:22:48.491764 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 19:22:48.495347 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 19:22:48.498168 0 7 28 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1533 19:22:48.501607 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 19:22:48.508641 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1535 19:22:48.511738 0 8 8 | B1->B0 | 2424 2323 | 0 0 | (1 1) (1 1)
1536 19:22:48.514897 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 19:22:48.521103 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 19:22:48.524813 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 19:22:48.528407 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 19:22:48.534694 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 19:22:48.538310 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 19:22:48.541792 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 19:22:48.548451 0 9 8 | B1->B0 | 2828 2626 | 0 0 | (0 0) (0 0)
1544 19:22:48.551371 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1545 19:22:48.555002 0 9 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1546 19:22:48.558259 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1547 19:22:48.564974 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1548 19:22:48.568721 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1549 19:22:48.571629 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1550 19:22:48.578827 0 10 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1551 19:22:48.582313 0 10 8 | B1->B0 | 2929 3131 | 0 0 | (1 0) (0 0)
1552 19:22:48.585166 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1553 19:22:48.592154 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 19:22:48.595646 0 10 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1555 19:22:48.598828 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 19:22:48.605650 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 19:22:48.609175 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 19:22:48.612288 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1559 19:22:48.618865 0 11 8 | B1->B0 | 3434 3131 | 0 0 | (0 0) (0 0)
1560 19:22:48.622453 0 11 12 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
1561 19:22:48.625675 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1562 19:22:48.629338 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1563 19:22:48.635932 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1564 19:22:48.639116 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1565 19:22:48.642751 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1566 19:22:48.649530 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1567 19:22:48.652502 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1568 19:22:48.656219 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 19:22:48.663105 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 19:22:48.666953 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 19:22:48.670067 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 19:22:48.673423 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 19:22:48.680055 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 19:22:48.683017 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 19:22:48.686745 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 19:22:48.693276 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 19:22:48.696374 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 19:22:48.700188 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 19:22:48.706813 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 19:22:48.709643 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 19:22:48.713367 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 19:22:48.719919 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1583 19:22:48.723218 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1584 19:22:48.726722 Total UI for P1: 0, mck2ui 16
1585 19:22:48.730013 best dqsien dly found for B0: ( 0, 14, 6)
1586 19:22:48.732983 Total UI for P1: 0, mck2ui 16
1587 19:22:48.736731 best dqsien dly found for B1: ( 0, 14, 4)
1588 19:22:48.740034 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1589 19:22:48.743366 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1590 19:22:48.743465
1591 19:22:48.746555 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1592 19:22:48.750178 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1593 19:22:48.753217 [Gating] SW calibration Done
1594 19:22:48.753354 ==
1595 19:22:48.756816 Dram Type= 6, Freq= 0, CH_1, rank 0
1596 19:22:48.760056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1597 19:22:48.760161 ==
1598 19:22:48.763110 RX Vref Scan: 0
1599 19:22:48.763209
1600 19:22:48.763301 RX Vref 0 -> 0, step: 1
1601 19:22:48.763388
1602 19:22:48.766839 RX Delay -130 -> 252, step: 16
1603 19:22:48.770556 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1604 19:22:48.776937 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1605 19:22:48.780286 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1606 19:22:48.783335 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1607 19:22:48.786857 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1608 19:22:48.790337 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1609 19:22:48.796851 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1610 19:22:48.800186 iDelay=206, Bit 7, Center 69 (-50 ~ 189) 240
1611 19:22:48.803362 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1612 19:22:48.807124 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1613 19:22:48.810200 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1614 19:22:48.816839 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1615 19:22:48.819936 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1616 19:22:48.822979 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1617 19:22:48.826562 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1618 19:22:48.830222 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1619 19:22:48.833365 ==
1620 19:22:48.836815 Dram Type= 6, Freq= 0, CH_1, rank 0
1621 19:22:48.840044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1622 19:22:48.840148 ==
1623 19:22:48.840241 DQS Delay:
1624 19:22:48.843198 DQS0 = 0, DQS1 = 0
1625 19:22:48.843298 DQM Delay:
1626 19:22:48.846652 DQM0 = 81, DQM1 = 77
1627 19:22:48.846751 DQ Delay:
1628 19:22:48.850350 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1629 19:22:48.853360 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =69
1630 19:22:48.857110 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1631 19:22:48.860228 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1632 19:22:48.860330
1633 19:22:48.860428
1634 19:22:48.860520 ==
1635 19:22:48.863364 Dram Type= 6, Freq= 0, CH_1, rank 0
1636 19:22:48.866974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1637 19:22:48.867076 ==
1638 19:22:48.867176
1639 19:22:48.867266
1640 19:22:48.869954 TX Vref Scan disable
1641 19:22:48.873683 == TX Byte 0 ==
1642 19:22:48.876754 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1643 19:22:48.880001 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1644 19:22:48.883438 == TX Byte 1 ==
1645 19:22:48.887151 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1646 19:22:48.890190 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1647 19:22:48.890305 ==
1648 19:22:48.893776 Dram Type= 6, Freq= 0, CH_1, rank 0
1649 19:22:48.897030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1650 19:22:48.897129 ==
1651 19:22:48.911089 TX Vref=22, minBit 0, minWin=27, winSum=439
1652 19:22:48.914774 TX Vref=24, minBit 0, minWin=27, winSum=440
1653 19:22:48.917953 TX Vref=26, minBit 4, minWin=27, winSum=447
1654 19:22:48.921040 TX Vref=28, minBit 0, minWin=27, winSum=452
1655 19:22:48.924724 TX Vref=30, minBit 4, minWin=27, winSum=453
1656 19:22:48.927871 TX Vref=32, minBit 2, minWin=28, winSum=456
1657 19:22:48.934601 [TxChooseVref] Worse bit 2, Min win 28, Win sum 456, Final Vref 32
1658 19:22:48.934709
1659 19:22:48.938316 Final TX Range 1 Vref 32
1660 19:22:48.938419
1661 19:22:48.938516 ==
1662 19:22:48.941809 Dram Type= 6, Freq= 0, CH_1, rank 0
1663 19:22:48.944862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1664 19:22:48.944967 ==
1665 19:22:48.945059
1666 19:22:48.945146
1667 19:22:48.948486 TX Vref Scan disable
1668 19:22:48.951472 == TX Byte 0 ==
1669 19:22:48.955057 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1670 19:22:48.958132 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1671 19:22:48.961801 == TX Byte 1 ==
1672 19:22:48.965105 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1673 19:22:48.968442 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1674 19:22:48.968570
1675 19:22:48.971578 [DATLAT]
1676 19:22:48.971689 Freq=800, CH1 RK0
1677 19:22:48.971826
1678 19:22:48.975230 DATLAT Default: 0xa
1679 19:22:48.975334 0, 0xFFFF, sum = 0
1680 19:22:48.978253 1, 0xFFFF, sum = 0
1681 19:22:48.978353 2, 0xFFFF, sum = 0
1682 19:22:48.982097 3, 0xFFFF, sum = 0
1683 19:22:48.982210 4, 0xFFFF, sum = 0
1684 19:22:48.984926 5, 0xFFFF, sum = 0
1685 19:22:48.985027 6, 0xFFFF, sum = 0
1686 19:22:48.988494 7, 0xFFFF, sum = 0
1687 19:22:48.988601 8, 0xFFFF, sum = 0
1688 19:22:48.991528 9, 0x0, sum = 1
1689 19:22:48.991648 10, 0x0, sum = 2
1690 19:22:48.995391 11, 0x0, sum = 3
1691 19:22:48.995494 12, 0x0, sum = 4
1692 19:22:48.998487 best_step = 10
1693 19:22:48.998584
1694 19:22:48.998684 ==
1695 19:22:49.002100 Dram Type= 6, Freq= 0, CH_1, rank 0
1696 19:22:49.005287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1697 19:22:49.005366 ==
1698 19:22:49.005441 RX Vref Scan: 1
1699 19:22:49.005528
1700 19:22:49.008949 Set Vref Range= 32 -> 127
1701 19:22:49.009045
1702 19:22:49.011724 RX Vref 32 -> 127, step: 1
1703 19:22:49.011822
1704 19:22:49.015240 RX Delay -95 -> 252, step: 8
1705 19:22:49.015339
1706 19:22:49.018705 Set Vref, RX VrefLevel [Byte0]: 32
1707 19:22:49.022011 [Byte1]: 32
1708 19:22:49.022097
1709 19:22:49.025616 Set Vref, RX VrefLevel [Byte0]: 33
1710 19:22:49.028871 [Byte1]: 33
1711 19:22:49.028972
1712 19:22:49.032301 Set Vref, RX VrefLevel [Byte0]: 34
1713 19:22:49.035129 [Byte1]: 34
1714 19:22:49.038824
1715 19:22:49.038928 Set Vref, RX VrefLevel [Byte0]: 35
1716 19:22:49.042384 [Byte1]: 35
1717 19:22:49.046459
1718 19:22:49.046557 Set Vref, RX VrefLevel [Byte0]: 36
1719 19:22:49.050177 [Byte1]: 36
1720 19:22:49.054557
1721 19:22:49.054637 Set Vref, RX VrefLevel [Byte0]: 37
1722 19:22:49.057638 [Byte1]: 37
1723 19:22:49.062008
1724 19:22:49.062082 Set Vref, RX VrefLevel [Byte0]: 38
1725 19:22:49.064999 [Byte1]: 38
1726 19:22:49.069578
1727 19:22:49.069658 Set Vref, RX VrefLevel [Byte0]: 39
1728 19:22:49.072617 [Byte1]: 39
1729 19:22:49.077340
1730 19:22:49.077414 Set Vref, RX VrefLevel [Byte0]: 40
1731 19:22:49.080113 [Byte1]: 40
1732 19:22:49.084926
1733 19:22:49.085026 Set Vref, RX VrefLevel [Byte0]: 41
1734 19:22:49.088147 [Byte1]: 41
1735 19:22:49.092514
1736 19:22:49.092588 Set Vref, RX VrefLevel [Byte0]: 42
1737 19:22:49.095675 [Byte1]: 42
1738 19:22:49.099838
1739 19:22:49.099937 Set Vref, RX VrefLevel [Byte0]: 43
1740 19:22:49.103019 [Byte1]: 43
1741 19:22:49.107243
1742 19:22:49.107330 Set Vref, RX VrefLevel [Byte0]: 44
1743 19:22:49.111103 [Byte1]: 44
1744 19:22:49.114892
1745 19:22:49.114969 Set Vref, RX VrefLevel [Byte0]: 45
1746 19:22:49.118557 [Byte1]: 45
1747 19:22:49.122715
1748 19:22:49.122817 Set Vref, RX VrefLevel [Byte0]: 46
1749 19:22:49.125684 [Byte1]: 46
1750 19:22:49.130554
1751 19:22:49.130657 Set Vref, RX VrefLevel [Byte0]: 47
1752 19:22:49.133739 [Byte1]: 47
1753 19:22:49.137944
1754 19:22:49.138025 Set Vref, RX VrefLevel [Byte0]: 48
1755 19:22:49.141065 [Byte1]: 48
1756 19:22:49.145397
1757 19:22:49.145478 Set Vref, RX VrefLevel [Byte0]: 49
1758 19:22:49.148533 [Byte1]: 49
1759 19:22:49.152826
1760 19:22:49.152928 Set Vref, RX VrefLevel [Byte0]: 50
1761 19:22:49.156399 [Byte1]: 50
1762 19:22:49.160718
1763 19:22:49.160820 Set Vref, RX VrefLevel [Byte0]: 51
1764 19:22:49.163839 [Byte1]: 51
1765 19:22:49.168249
1766 19:22:49.168340 Set Vref, RX VrefLevel [Byte0]: 52
1767 19:22:49.171254 [Byte1]: 52
1768 19:22:49.175996
1769 19:22:49.176095 Set Vref, RX VrefLevel [Byte0]: 53
1770 19:22:49.178911 [Byte1]: 53
1771 19:22:49.183231
1772 19:22:49.183331 Set Vref, RX VrefLevel [Byte0]: 54
1773 19:22:49.186799 [Byte1]: 54
1774 19:22:49.190828
1775 19:22:49.190934 Set Vref, RX VrefLevel [Byte0]: 55
1776 19:22:49.194393 [Byte1]: 55
1777 19:22:49.198648
1778 19:22:49.198751 Set Vref, RX VrefLevel [Byte0]: 56
1779 19:22:49.202239 [Byte1]: 56
1780 19:22:49.206496
1781 19:22:49.206572 Set Vref, RX VrefLevel [Byte0]: 57
1782 19:22:49.209704 [Byte1]: 57
1783 19:22:49.213991
1784 19:22:49.214069 Set Vref, RX VrefLevel [Byte0]: 58
1785 19:22:49.217005 [Byte1]: 58
1786 19:22:49.221083
1787 19:22:49.221183 Set Vref, RX VrefLevel [Byte0]: 59
1788 19:22:49.224804 [Byte1]: 59
1789 19:22:49.229000
1790 19:22:49.229101 Set Vref, RX VrefLevel [Byte0]: 60
1791 19:22:49.232171 [Byte1]: 60
1792 19:22:49.236838
1793 19:22:49.236946 Set Vref, RX VrefLevel [Byte0]: 61
1794 19:22:49.239991 [Byte1]: 61
1795 19:22:49.244486
1796 19:22:49.244588 Set Vref, RX VrefLevel [Byte0]: 62
1797 19:22:49.247381 [Byte1]: 62
1798 19:22:49.251514
1799 19:22:49.251629 Set Vref, RX VrefLevel [Byte0]: 63
1800 19:22:49.254931 [Byte1]: 63
1801 19:22:49.259051
1802 19:22:49.259133 Set Vref, RX VrefLevel [Byte0]: 64
1803 19:22:49.262952 [Byte1]: 64
1804 19:22:49.266779
1805 19:22:49.266885 Set Vref, RX VrefLevel [Byte0]: 65
1806 19:22:49.270501 [Byte1]: 65
1807 19:22:49.274230
1808 19:22:49.274342 Set Vref, RX VrefLevel [Byte0]: 66
1809 19:22:49.277739 [Byte1]: 66
1810 19:22:49.281932
1811 19:22:49.282008 Set Vref, RX VrefLevel [Byte0]: 67
1812 19:22:49.285631 [Byte1]: 67
1813 19:22:49.289958
1814 19:22:49.290064 Set Vref, RX VrefLevel [Byte0]: 68
1815 19:22:49.292945 [Byte1]: 68
1816 19:22:49.297133
1817 19:22:49.297274 Set Vref, RX VrefLevel [Byte0]: 69
1818 19:22:49.300889 [Byte1]: 69
1819 19:22:49.304981
1820 19:22:49.305084 Set Vref, RX VrefLevel [Byte0]: 70
1821 19:22:49.308240 [Byte1]: 70
1822 19:22:49.312655
1823 19:22:49.312757 Set Vref, RX VrefLevel [Byte0]: 71
1824 19:22:49.315687 [Byte1]: 71
1825 19:22:49.319957
1826 19:22:49.320031 Set Vref, RX VrefLevel [Byte0]: 72
1827 19:22:49.323503 [Byte1]: 72
1828 19:22:49.327660
1829 19:22:49.327761 Set Vref, RX VrefLevel [Byte0]: 73
1830 19:22:49.330830 [Byte1]: 73
1831 19:22:49.335239
1832 19:22:49.335319 Set Vref, RX VrefLevel [Byte0]: 74
1833 19:22:49.338691 [Byte1]: 74
1834 19:22:49.342646
1835 19:22:49.342758 Set Vref, RX VrefLevel [Byte0]: 75
1836 19:22:49.346401 [Byte1]: 75
1837 19:22:49.350734
1838 19:22:49.350810 Set Vref, RX VrefLevel [Byte0]: 76
1839 19:22:49.353663 [Byte1]: 76
1840 19:22:49.358221
1841 19:22:49.358340 Set Vref, RX VrefLevel [Byte0]: 77
1842 19:22:49.361180 [Byte1]: 77
1843 19:22:49.365930
1844 19:22:49.366035 Final RX Vref Byte 0 = 57 to rank0
1845 19:22:49.368747 Final RX Vref Byte 1 = 58 to rank0
1846 19:22:49.372444 Final RX Vref Byte 0 = 57 to rank1
1847 19:22:49.375442 Final RX Vref Byte 1 = 58 to rank1==
1848 19:22:49.379319 Dram Type= 6, Freq= 0, CH_1, rank 0
1849 19:22:49.382278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1850 19:22:49.385926 ==
1851 19:22:49.385999 DQS Delay:
1852 19:22:49.386061 DQS0 = 0, DQS1 = 0
1853 19:22:49.388976 DQM Delay:
1854 19:22:49.389076 DQM0 = 83, DQM1 = 74
1855 19:22:49.392232 DQ Delay:
1856 19:22:49.395825 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =84
1857 19:22:49.395924 DQ4 =84, DQ5 =92, DQ6 =92, DQ7 =76
1858 19:22:49.398882 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =72
1859 19:22:49.402553 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =76
1860 19:22:49.405700
1861 19:22:49.405814
1862 19:22:49.412893 [DQSOSCAuto] RK0, (LSB)MR18= 0x3105, (MSB)MR19= 0x606, tDQSOscB0 = 408 ps tDQSOscB1 = 397 ps
1863 19:22:49.415769 CH1 RK0: MR19=606, MR18=3105
1864 19:22:49.422504 CH1_RK0: MR19=0x606, MR18=0x3105, DQSOSC=397, MR23=63, INC=93, DEC=62
1865 19:22:49.422611
1866 19:22:49.425990 ----->DramcWriteLeveling(PI) begin...
1867 19:22:49.426094 ==
1868 19:22:49.428929 Dram Type= 6, Freq= 0, CH_1, rank 1
1869 19:22:49.432688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1870 19:22:49.432786 ==
1871 19:22:49.436089 Write leveling (Byte 0): 25 => 25
1872 19:22:49.439155 Write leveling (Byte 1): 30 => 30
1873 19:22:49.442668 DramcWriteLeveling(PI) end<-----
1874 19:22:49.442759
1875 19:22:49.442861 ==
1876 19:22:49.445705 Dram Type= 6, Freq= 0, CH_1, rank 1
1877 19:22:49.449066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1878 19:22:49.449171 ==
1879 19:22:49.452602 [Gating] SW mode calibration
1880 19:22:49.459176 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1881 19:22:49.465778 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1882 19:22:49.468986 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1883 19:22:49.472466 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1884 19:22:49.479298 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 19:22:49.482813 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 19:22:49.486111 0 6 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1887 19:22:49.489342 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 19:22:49.496111 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 19:22:49.499226 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 19:22:49.502729 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 19:22:49.509334 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 19:22:49.513037 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 19:22:49.516147 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 19:22:49.522838 0 7 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1895 19:22:49.526349 0 7 20 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1896 19:22:49.529278 0 7 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1897 19:22:49.536270 0 7 28 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1898 19:22:49.539850 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1899 19:22:49.543077 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1900 19:22:49.546572 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 19:22:49.553120 0 8 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1902 19:22:49.557868 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 19:22:49.560003 0 8 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1904 19:22:49.566503 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 19:22:49.570160 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 19:22:49.573194 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 19:22:49.579752 0 9 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
1908 19:22:49.583517 0 9 8 | B1->B0 | 2e2e 3434 | 1 1 | (0 0) (1 1)
1909 19:22:49.587118 0 9 12 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
1910 19:22:49.593597 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1911 19:22:49.596584 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1912 19:22:49.599798 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1913 19:22:49.606736 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1914 19:22:49.609822 0 10 0 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
1915 19:22:49.613473 0 10 4 | B1->B0 | 3131 2e2e | 0 1 | (0 1) (1 0)
1916 19:22:49.616688 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1917 19:22:49.623389 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1918 19:22:49.627104 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1919 19:22:49.630382 0 10 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1920 19:22:49.637039 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1921 19:22:49.640553 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1922 19:22:49.643477 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1923 19:22:49.650174 0 11 4 | B1->B0 | 2727 3a3a | 0 0 | (0 0) (0 0)
1924 19:22:49.653799 0 11 8 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
1925 19:22:49.657026 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1926 19:22:49.663503 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1927 19:22:49.666932 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1928 19:22:49.670413 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1929 19:22:49.677441 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1930 19:22:49.680416 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1931 19:22:49.683980 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1932 19:22:49.686913 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 19:22:49.694113 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 19:22:49.697356 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 19:22:49.700783 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 19:22:49.707263 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 19:22:49.710763 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 19:22:49.714033 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 19:22:49.720841 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 19:22:49.724403 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 19:22:49.727621 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 19:22:49.734404 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 19:22:49.737547 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1944 19:22:49.741286 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1945 19:22:49.744467 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1946 19:22:49.751093 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1947 19:22:49.754226 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1948 19:22:49.757663 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1949 19:22:49.760932 Total UI for P1: 0, mck2ui 16
1950 19:22:49.764352 best dqsien dly found for B0: ( 0, 14, 4)
1951 19:22:49.767678 Total UI for P1: 0, mck2ui 16
1952 19:22:49.771082 best dqsien dly found for B1: ( 0, 14, 6)
1953 19:22:49.774075 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1954 19:22:49.777412 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1955 19:22:49.777510
1956 19:22:49.784497 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1957 19:22:49.787905 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1958 19:22:49.788026 [Gating] SW calibration Done
1959 19:22:49.790938 ==
1960 19:22:49.791060 Dram Type= 6, Freq= 0, CH_1, rank 1
1961 19:22:49.797852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1962 19:22:49.797976 ==
1963 19:22:49.798075 RX Vref Scan: 0
1964 19:22:49.798163
1965 19:22:49.801014 RX Vref 0 -> 0, step: 1
1966 19:22:49.801119
1967 19:22:49.804787 RX Delay -130 -> 252, step: 16
1968 19:22:49.807840 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1969 19:22:49.811291 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1970 19:22:49.814780 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1971 19:22:49.821298 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1972 19:22:49.824670 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
1973 19:22:49.828418 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1974 19:22:49.831472 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1975 19:22:49.835204 iDelay=206, Bit 7, Center 69 (-50 ~ 189) 240
1976 19:22:49.838204 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1977 19:22:49.845086 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1978 19:22:49.848235 iDelay=206, Bit 10, Center 77 (-50 ~ 205) 256
1979 19:22:49.851330 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1980 19:22:49.854956 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1981 19:22:49.857960 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1982 19:22:49.865216 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1983 19:22:49.868060 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1984 19:22:49.868175 ==
1985 19:22:49.871768 Dram Type= 6, Freq= 0, CH_1, rank 1
1986 19:22:49.874725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1987 19:22:49.874830 ==
1988 19:22:49.878108 DQS Delay:
1989 19:22:49.878216 DQS0 = 0, DQS1 = 0
1990 19:22:49.878304 DQM Delay:
1991 19:22:49.881456 DQM0 = 79, DQM1 = 78
1992 19:22:49.881557 DQ Delay:
1993 19:22:49.884811 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1994 19:22:49.888246 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =69
1995 19:22:49.891890 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1996 19:22:49.895068 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1997 19:22:49.895164
1998 19:22:49.895232
1999 19:22:49.895295 ==
2000 19:22:49.898253 Dram Type= 6, Freq= 0, CH_1, rank 1
2001 19:22:49.905218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2002 19:22:49.905307 ==
2003 19:22:49.905374
2004 19:22:49.905443
2005 19:22:49.905503 TX Vref Scan disable
2006 19:22:49.908504 == TX Byte 0 ==
2007 19:22:49.912024 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2008 19:22:49.915324 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2009 19:22:49.918307 == TX Byte 1 ==
2010 19:22:49.921993 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2011 19:22:49.925513 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2012 19:22:49.928386 ==
2013 19:22:49.928496 Dram Type= 6, Freq= 0, CH_1, rank 1
2014 19:22:49.935094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2015 19:22:49.935203 ==
2016 19:22:49.948050 TX Vref=22, minBit 3, minWin=27, winSum=444
2017 19:22:49.951592 TX Vref=24, minBit 1, minWin=27, winSum=445
2018 19:22:49.954602 TX Vref=26, minBit 0, minWin=28, winSum=451
2019 19:22:49.958296 TX Vref=28, minBit 0, minWin=28, winSum=451
2020 19:22:49.961362 TX Vref=30, minBit 0, minWin=28, winSum=451
2021 19:22:49.964477 TX Vref=32, minBit 0, minWin=28, winSum=455
2022 19:22:49.971706 [TxChooseVref] Worse bit 0, Min win 28, Win sum 455, Final Vref 32
2023 19:22:49.971819
2024 19:22:49.974868 Final TX Range 1 Vref 32
2025 19:22:49.974944
2026 19:22:49.975013 ==
2027 19:22:49.977961 Dram Type= 6, Freq= 0, CH_1, rank 1
2028 19:22:49.981129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2029 19:22:49.981242 ==
2030 19:22:49.981308
2031 19:22:49.981368
2032 19:22:49.984634 TX Vref Scan disable
2033 19:22:49.987710 == TX Byte 0 ==
2034 19:22:49.991578 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
2035 19:22:49.994504 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
2036 19:22:49.998036 == TX Byte 1 ==
2037 19:22:50.001689 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2038 19:22:50.004713 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2039 19:22:50.004822
2040 19:22:50.008267 [DATLAT]
2041 19:22:50.008348 Freq=800, CH1 RK1
2042 19:22:50.008413
2043 19:22:50.011339 DATLAT Default: 0xa
2044 19:22:50.011446 0, 0xFFFF, sum = 0
2045 19:22:50.014732 1, 0xFFFF, sum = 0
2046 19:22:50.014840 2, 0xFFFF, sum = 0
2047 19:22:50.018271 3, 0xFFFF, sum = 0
2048 19:22:50.018380 4, 0xFFFF, sum = 0
2049 19:22:50.021191 5, 0xFFFF, sum = 0
2050 19:22:50.021304 6, 0xFFFF, sum = 0
2051 19:22:50.024973 7, 0xFFFF, sum = 0
2052 19:22:50.025086 8, 0xFFFF, sum = 0
2053 19:22:50.028359 9, 0x0, sum = 1
2054 19:22:50.028473 10, 0x0, sum = 2
2055 19:22:50.031538 11, 0x0, sum = 3
2056 19:22:50.031651 12, 0x0, sum = 4
2057 19:22:50.034957 best_step = 10
2058 19:22:50.035065
2059 19:22:50.035162 ==
2060 19:22:50.038221 Dram Type= 6, Freq= 0, CH_1, rank 1
2061 19:22:50.041675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2062 19:22:50.041785 ==
2063 19:22:50.044720 RX Vref Scan: 0
2064 19:22:50.044829
2065 19:22:50.044924 RX Vref 0 -> 0, step: 1
2066 19:22:50.045014
2067 19:22:50.048298 RX Delay -95 -> 252, step: 8
2068 19:22:50.055214 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
2069 19:22:50.058143 iDelay=209, Bit 1, Center 76 (-39 ~ 192) 232
2070 19:22:50.061932 iDelay=209, Bit 2, Center 68 (-47 ~ 184) 232
2071 19:22:50.065044 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
2072 19:22:50.068651 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
2073 19:22:50.071837 iDelay=209, Bit 5, Center 92 (-23 ~ 208) 232
2074 19:22:50.078789 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2075 19:22:50.081735 iDelay=209, Bit 7, Center 76 (-39 ~ 192) 232
2076 19:22:50.085408 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2077 19:22:50.088508 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
2078 19:22:50.092103 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
2079 19:22:50.098409 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2080 19:22:50.102263 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
2081 19:22:50.105220 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
2082 19:22:50.108810 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2083 19:22:50.111888 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
2084 19:22:50.111999 ==
2085 19:22:50.115619 Dram Type= 6, Freq= 0, CH_1, rank 1
2086 19:22:50.122304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2087 19:22:50.122417 ==
2088 19:22:50.122513 DQS Delay:
2089 19:22:50.125231 DQS0 = 0, DQS1 = 0
2090 19:22:50.125351 DQM Delay:
2091 19:22:50.125453 DQM0 = 80, DQM1 = 75
2092 19:22:50.128704 DQ Delay:
2093 19:22:50.132208 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
2094 19:22:50.135320 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
2095 19:22:50.138936 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
2096 19:22:50.142339 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
2097 19:22:50.142449
2098 19:22:50.142547
2099 19:22:50.148808 [DQSOSCAuto] RK1, (LSB)MR18= 0x2630, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 400 ps
2100 19:22:50.152238 CH1 RK1: MR19=606, MR18=2630
2101 19:22:50.159054 CH1_RK1: MR19=0x606, MR18=0x2630, DQSOSC=397, MR23=63, INC=93, DEC=62
2102 19:22:50.162166 [RxdqsGatingPostProcess] freq 800
2103 19:22:50.165848 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2104 19:22:50.168753 Pre-setting of DQS Precalculation
2105 19:22:50.176126 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2106 19:22:50.182567 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2107 19:22:50.189383 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2108 19:22:50.189469
2109 19:22:50.189549
2110 19:22:50.192423 [Calibration Summary] 1600 Mbps
2111 19:22:50.192511 CH 0, Rank 0
2112 19:22:50.196112 SW Impedance : PASS
2113 19:22:50.199193 DUTY Scan : NO K
2114 19:22:50.199299 ZQ Calibration : PASS
2115 19:22:50.202668 Jitter Meter : NO K
2116 19:22:50.202750 CBT Training : PASS
2117 19:22:50.206158 Write leveling : PASS
2118 19:22:50.209235 RX DQS gating : PASS
2119 19:22:50.209334 RX DQ/DQS(RDDQC) : PASS
2120 19:22:50.212379 TX DQ/DQS : PASS
2121 19:22:50.215727 RX DATLAT : PASS
2122 19:22:50.215839 RX DQ/DQS(Engine): PASS
2123 19:22:50.219279 TX OE : NO K
2124 19:22:50.219384 All Pass.
2125 19:22:50.219485
2126 19:22:50.222484 CH 0, Rank 1
2127 19:22:50.222594 SW Impedance : PASS
2128 19:22:50.226257 DUTY Scan : NO K
2129 19:22:50.229191 ZQ Calibration : PASS
2130 19:22:50.229279 Jitter Meter : NO K
2131 19:22:50.232887 CBT Training : PASS
2132 19:22:50.235900 Write leveling : PASS
2133 19:22:50.236015 RX DQS gating : PASS
2134 19:22:50.239523 RX DQ/DQS(RDDQC) : PASS
2135 19:22:50.239640 TX DQ/DQS : PASS
2136 19:22:50.243029 RX DATLAT : PASS
2137 19:22:50.246114 RX DQ/DQS(Engine): PASS
2138 19:22:50.246190 TX OE : NO K
2139 19:22:50.249877 All Pass.
2140 19:22:50.249983
2141 19:22:50.250078 CH 1, Rank 0
2142 19:22:50.252996 SW Impedance : PASS
2143 19:22:50.253101 DUTY Scan : NO K
2144 19:22:50.256509 ZQ Calibration : PASS
2145 19:22:50.259450 Jitter Meter : NO K
2146 19:22:50.259542 CBT Training : PASS
2147 19:22:50.262976 Write leveling : PASS
2148 19:22:50.266199 RX DQS gating : PASS
2149 19:22:50.266312 RX DQ/DQS(RDDQC) : PASS
2150 19:22:50.269742 TX DQ/DQS : PASS
2151 19:22:50.269818 RX DATLAT : PASS
2152 19:22:50.273146 RX DQ/DQS(Engine): PASS
2153 19:22:50.276123 TX OE : NO K
2154 19:22:50.276221 All Pass.
2155 19:22:50.276285
2156 19:22:50.276346 CH 1, Rank 1
2157 19:22:50.279469 SW Impedance : PASS
2158 19:22:50.283034 DUTY Scan : NO K
2159 19:22:50.283113 ZQ Calibration : PASS
2160 19:22:50.286705 Jitter Meter : NO K
2161 19:22:50.289881 CBT Training : PASS
2162 19:22:50.289986 Write leveling : PASS
2163 19:22:50.293036 RX DQS gating : PASS
2164 19:22:50.296705 RX DQ/DQS(RDDQC) : PASS
2165 19:22:50.296797 TX DQ/DQS : PASS
2166 19:22:50.299726 RX DATLAT : PASS
2167 19:22:50.303509 RX DQ/DQS(Engine): PASS
2168 19:22:50.303619 TX OE : NO K
2169 19:22:50.303716 All Pass.
2170 19:22:50.306634
2171 19:22:50.306719 DramC Write-DBI off
2172 19:22:50.310138 PER_BANK_REFRESH: Hybrid Mode
2173 19:22:50.310246 TX_TRACKING: ON
2174 19:22:50.313078 [GetDramInforAfterCalByMRR] Vendor 6.
2175 19:22:50.316812 [GetDramInforAfterCalByMRR] Revision 606.
2176 19:22:50.323302 [GetDramInforAfterCalByMRR] Revision 2 0.
2177 19:22:50.323411 MR0 0x3b3b
2178 19:22:50.323508 MR8 0x5151
2179 19:22:50.326726 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2180 19:22:50.326830
2181 19:22:50.330290 MR0 0x3b3b
2182 19:22:50.330396 MR8 0x5151
2183 19:22:50.333359 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2184 19:22:50.333472
2185 19:22:50.343521 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2186 19:22:50.346663 [FAST_K] Save calibration result to emmc
2187 19:22:50.350389 [FAST_K] Save calibration result to emmc
2188 19:22:50.353553 dram_init: config_dvfs: 1
2189 19:22:50.356535 dramc_set_vcore_voltage set vcore to 662500
2190 19:22:50.356639 Read voltage for 1200, 2
2191 19:22:50.360200 Vio18 = 0
2192 19:22:50.360304 Vcore = 662500
2193 19:22:50.360426 Vdram = 0
2194 19:22:50.363371 Vddq = 0
2195 19:22:50.363474 Vmddr = 0
2196 19:22:50.367128 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2197 19:22:50.373725 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2198 19:22:50.376601 MEM_TYPE=3, freq_sel=15
2199 19:22:50.380051 sv_algorithm_assistance_LP4_1600
2200 19:22:50.383311 ============ PULL DRAM RESETB DOWN ============
2201 19:22:50.386628 ========== PULL DRAM RESETB DOWN end =========
2202 19:22:50.390164 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2203 19:22:50.393777 ===================================
2204 19:22:50.396744 LPDDR4 DRAM CONFIGURATION
2205 19:22:50.400237 ===================================
2206 19:22:50.403838 EX_ROW_EN[0] = 0x0
2207 19:22:50.403943 EX_ROW_EN[1] = 0x0
2208 19:22:50.406986 LP4Y_EN = 0x0
2209 19:22:50.407089 WORK_FSP = 0x0
2210 19:22:50.410558 WL = 0x4
2211 19:22:50.410628 RL = 0x4
2212 19:22:50.413710 BL = 0x2
2213 19:22:50.413792 RPST = 0x0
2214 19:22:50.417265 RD_PRE = 0x0
2215 19:22:50.417428 WR_PRE = 0x1
2216 19:22:50.420904 WR_PST = 0x0
2217 19:22:50.420987 DBI_WR = 0x0
2218 19:22:50.423883 DBI_RD = 0x0
2219 19:22:50.423979 OTF = 0x1
2220 19:22:50.426844 ===================================
2221 19:22:50.430489 ===================================
2222 19:22:50.433972 ANA top config
2223 19:22:50.437224 ===================================
2224 19:22:50.440480 DLL_ASYNC_EN = 0
2225 19:22:50.440562 ALL_SLAVE_EN = 0
2226 19:22:50.443717 NEW_RANK_MODE = 1
2227 19:22:50.447242 DLL_IDLE_MODE = 1
2228 19:22:50.450636 LP45_APHY_COMB_EN = 1
2229 19:22:50.450719 TX_ODT_DIS = 1
2230 19:22:50.454254 NEW_8X_MODE = 1
2231 19:22:50.457168 ===================================
2232 19:22:50.460974 ===================================
2233 19:22:50.464085 data_rate = 2400
2234 19:22:50.467142 CKR = 1
2235 19:22:50.470852 DQ_P2S_RATIO = 8
2236 19:22:50.473748 ===================================
2237 19:22:50.473853 CA_P2S_RATIO = 8
2238 19:22:50.477339 DQ_CA_OPEN = 0
2239 19:22:50.481044 DQ_SEMI_OPEN = 0
2240 19:22:50.483945 CA_SEMI_OPEN = 0
2241 19:22:50.487722 CA_FULL_RATE = 0
2242 19:22:50.490769 DQ_CKDIV4_EN = 0
2243 19:22:50.490875 CA_CKDIV4_EN = 0
2244 19:22:50.494423 CA_PREDIV_EN = 0
2245 19:22:50.497331 PH8_DLY = 17
2246 19:22:50.500830 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2247 19:22:50.503978 DQ_AAMCK_DIV = 4
2248 19:22:50.507214 CA_AAMCK_DIV = 4
2249 19:22:50.507303 CA_ADMCK_DIV = 4
2250 19:22:50.510698 DQ_TRACK_CA_EN = 0
2251 19:22:50.514150 CA_PICK = 1200
2252 19:22:50.517779 CA_MCKIO = 1200
2253 19:22:50.520818 MCKIO_SEMI = 0
2254 19:22:50.524307 PLL_FREQ = 2366
2255 19:22:50.528074 DQ_UI_PI_RATIO = 32
2256 19:22:50.528179 CA_UI_PI_RATIO = 0
2257 19:22:50.531066 ===================================
2258 19:22:50.534145 ===================================
2259 19:22:50.537662 memory_type:LPDDR4
2260 19:22:50.541089 GP_NUM : 10
2261 19:22:50.541166 SRAM_EN : 1
2262 19:22:50.544281 MD32_EN : 0
2263 19:22:50.547963 ===================================
2264 19:22:50.551549 [ANA_INIT] >>>>>>>>>>>>>>
2265 19:22:50.551633 <<<<<< [CONFIGURE PHASE]: ANA_TX
2266 19:22:50.554582 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2267 19:22:50.558070 ===================================
2268 19:22:50.561229 data_rate = 2400,PCW = 0X5b00
2269 19:22:50.565064 ===================================
2270 19:22:50.567967 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2271 19:22:50.574663 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2272 19:22:50.581326 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2273 19:22:50.585099 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2274 19:22:50.587996 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2275 19:22:50.591720 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2276 19:22:50.594870 [ANA_INIT] flow start
2277 19:22:50.594981 [ANA_INIT] PLL >>>>>>>>
2278 19:22:50.598258 [ANA_INIT] PLL <<<<<<<<
2279 19:22:50.601481 [ANA_INIT] MIDPI >>>>>>>>
2280 19:22:50.601559 [ANA_INIT] MIDPI <<<<<<<<
2281 19:22:50.605092 [ANA_INIT] DLL >>>>>>>>
2282 19:22:50.608084 [ANA_INIT] DLL <<<<<<<<
2283 19:22:50.608158 [ANA_INIT] flow end
2284 19:22:50.611810 ============ LP4 DIFF to SE enter ============
2285 19:22:50.618301 ============ LP4 DIFF to SE exit ============
2286 19:22:50.618384 [ANA_INIT] <<<<<<<<<<<<<
2287 19:22:50.621583 [Flow] Enable top DCM control >>>>>
2288 19:22:50.624986 [Flow] Enable top DCM control <<<<<
2289 19:22:50.628261 Enable DLL master slave shuffle
2290 19:22:50.634988 ==============================================================
2291 19:22:50.635068 Gating Mode config
2292 19:22:50.641549 ==============================================================
2293 19:22:50.645085 Config description:
2294 19:22:50.651795 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2295 19:22:50.658351 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2296 19:22:50.665082 SELPH_MODE 0: By rank 1: By Phase
2297 19:22:50.671715 ==============================================================
2298 19:22:50.671828 GAT_TRACK_EN = 1
2299 19:22:50.675448 RX_GATING_MODE = 2
2300 19:22:50.678543 RX_GATING_TRACK_MODE = 2
2301 19:22:50.682221 SELPH_MODE = 1
2302 19:22:50.685159 PICG_EARLY_EN = 1
2303 19:22:50.688729 VALID_LAT_VALUE = 1
2304 19:22:50.695509 ==============================================================
2305 19:22:50.699103 Enter into Gating configuration >>>>
2306 19:22:50.702206 Exit from Gating configuration <<<<
2307 19:22:50.705267 Enter into DVFS_PRE_config >>>>>
2308 19:22:50.715583 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2309 19:22:50.718663 Exit from DVFS_PRE_config <<<<<
2310 19:22:50.722198 Enter into PICG configuration >>>>
2311 19:22:50.725663 Exit from PICG configuration <<<<
2312 19:22:50.725744 [RX_INPUT] configuration >>>>>
2313 19:22:50.728914 [RX_INPUT] configuration <<<<<
2314 19:22:50.736006 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2315 19:22:50.739004 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2316 19:22:50.746015 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2317 19:22:50.752612 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2318 19:22:50.759352 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2319 19:22:50.765887 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2320 19:22:50.769627 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2321 19:22:50.772660 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2322 19:22:50.776223 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2323 19:22:50.782541 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2324 19:22:50.786348 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2325 19:22:50.789249 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2326 19:22:50.792922 ===================================
2327 19:22:50.796086 LPDDR4 DRAM CONFIGURATION
2328 19:22:50.799305 ===================================
2329 19:22:50.799391 EX_ROW_EN[0] = 0x0
2330 19:22:50.802751 EX_ROW_EN[1] = 0x0
2331 19:22:50.806273 LP4Y_EN = 0x0
2332 19:22:50.806362 WORK_FSP = 0x0
2333 19:22:50.809411 WL = 0x4
2334 19:22:50.809520 RL = 0x4
2335 19:22:50.813095 BL = 0x2
2336 19:22:50.813220 RPST = 0x0
2337 19:22:50.816156 RD_PRE = 0x0
2338 19:22:50.816238 WR_PRE = 0x1
2339 19:22:50.819836 WR_PST = 0x0
2340 19:22:50.819917 DBI_WR = 0x0
2341 19:22:50.822992 DBI_RD = 0x0
2342 19:22:50.823096 OTF = 0x1
2343 19:22:50.826541 ===================================
2344 19:22:50.829608 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2345 19:22:50.836182 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2346 19:22:50.839609 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2347 19:22:50.843194 ===================================
2348 19:22:50.846768 LPDDR4 DRAM CONFIGURATION
2349 19:22:50.849716 ===================================
2350 19:22:50.849818 EX_ROW_EN[0] = 0x10
2351 19:22:50.853402 EX_ROW_EN[1] = 0x0
2352 19:22:50.853509 LP4Y_EN = 0x0
2353 19:22:50.856371 WORK_FSP = 0x0
2354 19:22:50.856475 WL = 0x4
2355 19:22:50.859605 RL = 0x4
2356 19:22:50.859724 BL = 0x2
2357 19:22:50.863343 RPST = 0x0
2358 19:22:50.863446 RD_PRE = 0x0
2359 19:22:50.866746 WR_PRE = 0x1
2360 19:22:50.866846 WR_PST = 0x0
2361 19:22:50.869754 DBI_WR = 0x0
2362 19:22:50.869859 DBI_RD = 0x0
2363 19:22:50.873394 OTF = 0x1
2364 19:22:50.876390 ===================================
2365 19:22:50.883136 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2366 19:22:50.883280 ==
2367 19:22:50.886501 Dram Type= 6, Freq= 0, CH_0, rank 0
2368 19:22:50.889733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2369 19:22:50.889868 ==
2370 19:22:50.893457 [Duty_Offset_Calibration]
2371 19:22:50.893533 B0:3 B1:-1 CA:1
2372 19:22:50.893602
2373 19:22:50.896322 [DutyScan_Calibration_Flow] k_type=0
2374 19:22:50.906310
2375 19:22:50.906457 ==CLK 0==
2376 19:22:50.909776 Final CLK duty delay cell = -4
2377 19:22:50.912878 [-4] MAX Duty = 5000%(X100), DQS PI = 4
2378 19:22:50.916646 [-4] MIN Duty = 4875%(X100), DQS PI = 30
2379 19:22:50.919669 [-4] AVG Duty = 4937%(X100)
2380 19:22:50.919776
2381 19:22:50.923333 CH0 CLK Duty spec in!! Max-Min= 125%
2382 19:22:50.926481 [DutyScan_Calibration_Flow] ====Done====
2383 19:22:50.926593
2384 19:22:50.930102 [DutyScan_Calibration_Flow] k_type=1
2385 19:22:50.944188
2386 19:22:50.944296 ==DQS 0 ==
2387 19:22:50.948026 Final DQS duty delay cell = -4
2388 19:22:50.951483 [-4] MAX Duty = 5000%(X100), DQS PI = 54
2389 19:22:50.954617 [-4] MIN Duty = 4875%(X100), DQS PI = 12
2390 19:22:50.958089 [-4] AVG Duty = 4937%(X100)
2391 19:22:50.958194
2392 19:22:50.958293 ==DQS 1 ==
2393 19:22:50.961510 Final DQS duty delay cell = -4
2394 19:22:50.964475 [-4] MAX Duty = 5124%(X100), DQS PI = 18
2395 19:22:50.967873 [-4] MIN Duty = 5000%(X100), DQS PI = 48
2396 19:22:50.971052 [-4] AVG Duty = 5062%(X100)
2397 19:22:50.971167
2398 19:22:50.975020 CH0 DQS 0 Duty spec in!! Max-Min= 125%
2399 19:22:50.975123
2400 19:22:50.977754 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2401 19:22:50.981246 [DutyScan_Calibration_Flow] ====Done====
2402 19:22:50.981350
2403 19:22:50.984675 [DutyScan_Calibration_Flow] k_type=3
2404 19:22:51.002016
2405 19:22:51.002151 ==DQM 0 ==
2406 19:22:51.004962 Final DQM duty delay cell = 0
2407 19:22:51.008627 [0] MAX Duty = 5000%(X100), DQS PI = 54
2408 19:22:51.011687 [0] MIN Duty = 4875%(X100), DQS PI = 4
2409 19:22:51.011803 [0] AVG Duty = 4937%(X100)
2410 19:22:51.015257
2411 19:22:51.015363 ==DQM 1 ==
2412 19:22:51.018366 Final DQM duty delay cell = 0
2413 19:22:51.022040 [0] MAX Duty = 5156%(X100), DQS PI = 62
2414 19:22:51.025094 [0] MIN Duty = 4969%(X100), DQS PI = 58
2415 19:22:51.025202 [0] AVG Duty = 5062%(X100)
2416 19:22:51.028173
2417 19:22:51.031913 CH0 DQM 0 Duty spec in!! Max-Min= 125%
2418 19:22:51.032017
2419 19:22:51.035033 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2420 19:22:51.038449 [DutyScan_Calibration_Flow] ====Done====
2421 19:22:51.038554
2422 19:22:51.041404 [DutyScan_Calibration_Flow] k_type=2
2423 19:22:51.057404
2424 19:22:51.057534 ==DQ 0 ==
2425 19:22:51.061027 Final DQ duty delay cell = -4
2426 19:22:51.063914 [-4] MAX Duty = 5062%(X100), DQS PI = 54
2427 19:22:51.067390 [-4] MIN Duty = 4875%(X100), DQS PI = 12
2428 19:22:51.070959 [-4] AVG Duty = 4968%(X100)
2429 19:22:51.071053
2430 19:22:51.071149 ==DQ 1 ==
2431 19:22:51.073907 Final DQ duty delay cell = 0
2432 19:22:51.077593 [0] MAX Duty = 5031%(X100), DQS PI = 18
2433 19:22:51.081190 [0] MIN Duty = 4907%(X100), DQS PI = 44
2434 19:22:51.081286 [0] AVG Duty = 4969%(X100)
2435 19:22:51.084127
2436 19:22:51.087715 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2437 19:22:51.087825
2438 19:22:51.090857 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2439 19:22:51.094002 [DutyScan_Calibration_Flow] ====Done====
2440 19:22:51.094112 ==
2441 19:22:51.097351 Dram Type= 6, Freq= 0, CH_1, rank 0
2442 19:22:51.100896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2443 19:22:51.100983 ==
2444 19:22:51.104391 [Duty_Offset_Calibration]
2445 19:22:51.104509 B0:1 B1:1 CA:2
2446 19:22:51.104581
2447 19:22:51.108051 [DutyScan_Calibration_Flow] k_type=0
2448 19:22:51.117518
2449 19:22:51.117635 ==CLK 0==
2450 19:22:51.121254 Final CLK duty delay cell = 0
2451 19:22:51.124311 [0] MAX Duty = 5156%(X100), DQS PI = 24
2452 19:22:51.127976 [0] MIN Duty = 4938%(X100), DQS PI = 48
2453 19:22:51.128087 [0] AVG Duty = 5047%(X100)
2454 19:22:51.131187
2455 19:22:51.131296 CH1 CLK Duty spec in!! Max-Min= 218%
2456 19:22:51.137861 [DutyScan_Calibration_Flow] ====Done====
2457 19:22:51.138003
2458 19:22:51.140880 [DutyScan_Calibration_Flow] k_type=1
2459 19:22:51.156939
2460 19:22:51.157097 ==DQS 0 ==
2461 19:22:51.160420 Final DQS duty delay cell = 0
2462 19:22:51.163748 [0] MAX Duty = 5031%(X100), DQS PI = 18
2463 19:22:51.167157 [0] MIN Duty = 4813%(X100), DQS PI = 48
2464 19:22:51.167250 [0] AVG Duty = 4922%(X100)
2465 19:22:51.170723
2466 19:22:51.170816 ==DQS 1 ==
2467 19:22:51.174229 Final DQS duty delay cell = 0
2468 19:22:51.177303 [0] MAX Duty = 5062%(X100), DQS PI = 36
2469 19:22:51.180201 [0] MIN Duty = 4907%(X100), DQS PI = 2
2470 19:22:51.180300 [0] AVG Duty = 4984%(X100)
2471 19:22:51.184107
2472 19:22:51.187079 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2473 19:22:51.187174
2474 19:22:51.190610 CH1 DQS 1 Duty spec in!! Max-Min= 155%
2475 19:22:51.194207 [DutyScan_Calibration_Flow] ====Done====
2476 19:22:51.194341
2477 19:22:51.197104 [DutyScan_Calibration_Flow] k_type=3
2478 19:22:51.213371
2479 19:22:51.213479 ==DQM 0 ==
2480 19:22:51.217220 Final DQM duty delay cell = 0
2481 19:22:51.220048 [0] MAX Duty = 5093%(X100), DQS PI = 18
2482 19:22:51.223724 [0] MIN Duty = 4907%(X100), DQS PI = 44
2483 19:22:51.223833 [0] AVG Duty = 5000%(X100)
2484 19:22:51.226701
2485 19:22:51.226841 ==DQM 1 ==
2486 19:22:51.230395 Final DQM duty delay cell = 0
2487 19:22:51.234101 [0] MAX Duty = 5125%(X100), DQS PI = 0
2488 19:22:51.237126 [0] MIN Duty = 4938%(X100), DQS PI = 22
2489 19:22:51.237263 [0] AVG Duty = 5031%(X100)
2490 19:22:51.240088
2491 19:22:51.243773 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2492 19:22:51.243883
2493 19:22:51.247194 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2494 19:22:51.250241 [DutyScan_Calibration_Flow] ====Done====
2495 19:22:51.250362
2496 19:22:51.253441 [DutyScan_Calibration_Flow] k_type=2
2497 19:22:51.270401
2498 19:22:51.270643 ==DQ 0 ==
2499 19:22:51.273104 Final DQ duty delay cell = 0
2500 19:22:51.276886 [0] MAX Duty = 5093%(X100), DQS PI = 18
2501 19:22:51.279835 [0] MIN Duty = 4938%(X100), DQS PI = 50
2502 19:22:51.279927 [0] AVG Duty = 5015%(X100)
2503 19:22:51.283202
2504 19:22:51.283316 ==DQ 1 ==
2505 19:22:51.286792 Final DQ duty delay cell = 0
2506 19:22:51.289909 [0] MAX Duty = 5093%(X100), DQS PI = 10
2507 19:22:51.293375 [0] MIN Duty = 5000%(X100), DQS PI = 50
2508 19:22:51.293508 [0] AVG Duty = 5046%(X100)
2509 19:22:51.293618
2510 19:22:51.296683 CH1 DQ 0 Duty spec in!! Max-Min= 155%
2511 19:22:51.296827
2512 19:22:51.300314 CH1 DQ 1 Duty spec in!! Max-Min= 93%
2513 19:22:51.307039 [DutyScan_Calibration_Flow] ====Done====
2514 19:22:51.310771 nWR fixed to 30
2515 19:22:51.310894 [ModeRegInit_LP4] CH0 RK0
2516 19:22:51.313602 [ModeRegInit_LP4] CH0 RK1
2517 19:22:51.316858 [ModeRegInit_LP4] CH1 RK0
2518 19:22:51.316975 [ModeRegInit_LP4] CH1 RK1
2519 19:22:51.320464 match AC timing 7
2520 19:22:51.323797 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2521 19:22:51.326969 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2522 19:22:51.333851 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2523 19:22:51.336867 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2524 19:22:51.343640 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2525 19:22:51.343764 ==
2526 19:22:51.347487 Dram Type= 6, Freq= 0, CH_0, rank 0
2527 19:22:51.350358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2528 19:22:51.350471 ==
2529 19:22:51.353912 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2530 19:22:51.360884 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2531 19:22:51.370050 [CA 0] Center 40 (10~71) winsize 62
2532 19:22:51.373720 [CA 1] Center 39 (9~70) winsize 62
2533 19:22:51.376649 [CA 2] Center 36 (6~67) winsize 62
2534 19:22:51.380154 [CA 3] Center 36 (5~67) winsize 63
2535 19:22:51.383489 [CA 4] Center 35 (5~65) winsize 61
2536 19:22:51.387144 [CA 5] Center 34 (4~64) winsize 61
2537 19:22:51.387261
2538 19:22:51.390517 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2539 19:22:51.390626
2540 19:22:51.393910 [CATrainingPosCal] consider 1 rank data
2541 19:22:51.396833 u2DelayCellTimex100 = 270/100 ps
2542 19:22:51.400376 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2543 19:22:51.403533 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2544 19:22:51.410179 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2545 19:22:51.413709 CA3 delay=36 (5~67),Diff = 2 PI (9 cell)
2546 19:22:51.416823 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2547 19:22:51.420287 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2548 19:22:51.420403
2549 19:22:51.424017 CA PerBit enable=1, Macro0, CA PI delay=34
2550 19:22:51.424132
2551 19:22:51.427105 [CBTSetCACLKResult] CA Dly = 34
2552 19:22:51.427216 CS Dly: 7 (0~38)
2553 19:22:51.427321 ==
2554 19:22:51.430201 Dram Type= 6, Freq= 0, CH_0, rank 1
2555 19:22:51.437168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2556 19:22:51.437299 ==
2557 19:22:51.440791 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2558 19:22:51.446997 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2559 19:22:51.456207 [CA 0] Center 39 (9~70) winsize 62
2560 19:22:51.459293 [CA 1] Center 40 (10~70) winsize 61
2561 19:22:51.463029 [CA 2] Center 36 (6~67) winsize 62
2562 19:22:51.466201 [CA 3] Center 36 (5~67) winsize 63
2563 19:22:51.469385 [CA 4] Center 34 (4~65) winsize 62
2564 19:22:51.472635 [CA 5] Center 34 (4~64) winsize 61
2565 19:22:51.472716
2566 19:22:51.476249 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2567 19:22:51.476337
2568 19:22:51.479213 [CATrainingPosCal] consider 2 rank data
2569 19:22:51.483071 u2DelayCellTimex100 = 270/100 ps
2570 19:22:51.486016 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2571 19:22:51.489431 CA1 delay=40 (10~70),Diff = 6 PI (28 cell)
2572 19:22:51.496364 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2573 19:22:51.499975 CA3 delay=36 (5~67),Diff = 2 PI (9 cell)
2574 19:22:51.503166 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2575 19:22:51.506355 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2576 19:22:51.506438
2577 19:22:51.509969 CA PerBit enable=1, Macro0, CA PI delay=34
2578 19:22:51.510048
2579 19:22:51.512967 [CBTSetCACLKResult] CA Dly = 34
2580 19:22:51.513076 CS Dly: 8 (0~41)
2581 19:22:51.513169
2582 19:22:51.516243 ----->DramcWriteLeveling(PI) begin...
2583 19:22:51.516325 ==
2584 19:22:51.520064 Dram Type= 6, Freq= 0, CH_0, rank 0
2585 19:22:51.526682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2586 19:22:51.526764 ==
2587 19:22:51.530238 Write leveling (Byte 0): 32 => 32
2588 19:22:51.533278 Write leveling (Byte 1): 30 => 30
2589 19:22:51.533357 DramcWriteLeveling(PI) end<-----
2590 19:22:51.533421
2591 19:22:51.536396 ==
2592 19:22:51.540001 Dram Type= 6, Freq= 0, CH_0, rank 0
2593 19:22:51.543189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2594 19:22:51.543266 ==
2595 19:22:51.546755 [Gating] SW mode calibration
2596 19:22:51.553031 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2597 19:22:51.556642 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2598 19:22:51.563345 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2599 19:22:51.566616 0 15 4 | B1->B0 | 2323 3030 | 0 1 | (0 0) (0 0)
2600 19:22:51.570097 0 15 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2601 19:22:51.576632 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2602 19:22:51.580435 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2603 19:22:51.583424 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2604 19:22:51.590279 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2605 19:22:51.593321 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2606 19:22:51.596789 1 0 0 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
2607 19:22:51.600197 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2608 19:22:51.606900 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2609 19:22:51.610447 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2610 19:22:51.613763 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2611 19:22:51.620141 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2612 19:22:51.623987 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2613 19:22:51.626869 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2614 19:22:51.634138 1 1 0 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
2615 19:22:51.637184 1 1 4 | B1->B0 | 3b3b 4646 | 1 0 | (0 0) (0 0)
2616 19:22:51.640849 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2617 19:22:51.647474 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2618 19:22:51.650649 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2619 19:22:51.654223 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2620 19:22:51.657073 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2621 19:22:51.664015 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2622 19:22:51.667470 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2623 19:22:51.670788 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2624 19:22:51.677469 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 19:22:51.680622 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 19:22:51.684148 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 19:22:51.690888 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 19:22:51.694481 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 19:22:51.697564 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 19:22:51.704537 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 19:22:51.707961 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 19:22:51.710856 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2633 19:22:51.714615 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2634 19:22:51.721068 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2635 19:22:51.724920 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2636 19:22:51.727657 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2637 19:22:51.734527 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2638 19:22:51.737886 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2639 19:22:51.741251 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2640 19:22:51.744342 Total UI for P1: 0, mck2ui 16
2641 19:22:51.748033 best dqsien dly found for B0: ( 1, 4, 0)
2642 19:22:51.754843 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2643 19:22:51.754926 Total UI for P1: 0, mck2ui 16
2644 19:22:51.761377 best dqsien dly found for B1: ( 1, 4, 2)
2645 19:22:51.764554 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2646 19:22:51.768144 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2647 19:22:51.768255
2648 19:22:51.771295 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2649 19:22:51.774795 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2650 19:22:51.777841 [Gating] SW calibration Done
2651 19:22:51.777947 ==
2652 19:22:51.781392 Dram Type= 6, Freq= 0, CH_0, rank 0
2653 19:22:51.785057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2654 19:22:51.785164 ==
2655 19:22:51.785270 RX Vref Scan: 0
2656 19:22:51.787933
2657 19:22:51.788038 RX Vref 0 -> 0, step: 1
2658 19:22:51.788142
2659 19:22:51.791304 RX Delay -40 -> 252, step: 8
2660 19:22:51.794922 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2661 19:22:51.798069 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2662 19:22:51.804828 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2663 19:22:51.807865 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2664 19:22:51.811452 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2665 19:22:51.814719 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2666 19:22:51.817914 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2667 19:22:51.821392 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2668 19:22:51.828835 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2669 19:22:51.831776 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2670 19:22:51.834911 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2671 19:22:51.838471 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2672 19:22:51.841985 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2673 19:22:51.848603 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2674 19:22:51.851600 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2675 19:22:51.855363 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2676 19:22:51.855473 ==
2677 19:22:51.858376 Dram Type= 6, Freq= 0, CH_0, rank 0
2678 19:22:51.862104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2679 19:22:51.862212 ==
2680 19:22:51.864981 DQS Delay:
2681 19:22:51.865089 DQS0 = 0, DQS1 = 0
2682 19:22:51.868882 DQM Delay:
2683 19:22:51.868996 DQM0 = 116, DQM1 = 107
2684 19:22:51.869101 DQ Delay:
2685 19:22:51.871881 DQ0 =115, DQ1 =115, DQ2 =115, DQ3 =111
2686 19:22:51.874995 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2687 19:22:51.878630 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2688 19:22:51.885544 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2689 19:22:51.885628
2690 19:22:51.885695
2691 19:22:51.885764 ==
2692 19:22:51.888575 Dram Type= 6, Freq= 0, CH_0, rank 0
2693 19:22:51.892272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2694 19:22:51.892347 ==
2695 19:22:51.892410
2696 19:22:51.892469
2697 19:22:51.895380 TX Vref Scan disable
2698 19:22:51.895469 == TX Byte 0 ==
2699 19:22:51.902061 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2700 19:22:51.905290 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2701 19:22:51.905372 == TX Byte 1 ==
2702 19:22:51.911909 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2703 19:22:51.915406 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2704 19:22:51.915523 ==
2705 19:22:51.918877 Dram Type= 6, Freq= 0, CH_0, rank 0
2706 19:22:51.922319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2707 19:22:51.922401 ==
2708 19:22:51.934792 TX Vref=22, minBit 1, minWin=24, winSum=415
2709 19:22:51.938522 TX Vref=24, minBit 1, minWin=25, winSum=417
2710 19:22:51.941617 TX Vref=26, minBit 0, minWin=26, winSum=423
2711 19:22:51.945351 TX Vref=28, minBit 0, minWin=26, winSum=431
2712 19:22:51.948641 TX Vref=30, minBit 0, minWin=26, winSum=432
2713 19:22:51.951590 TX Vref=32, minBit 0, minWin=26, winSum=429
2714 19:22:51.958268 [TxChooseVref] Worse bit 0, Min win 26, Win sum 432, Final Vref 30
2715 19:22:51.958355
2716 19:22:51.962032 Final TX Range 1 Vref 30
2717 19:22:51.962111
2718 19:22:51.962175 ==
2719 19:22:51.964990 Dram Type= 6, Freq= 0, CH_0, rank 0
2720 19:22:51.968718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2721 19:22:51.968836 ==
2722 19:22:51.968934
2723 19:22:51.969030
2724 19:22:51.971607 TX Vref Scan disable
2725 19:22:51.975223 == TX Byte 0 ==
2726 19:22:51.978144 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2727 19:22:51.981644 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2728 19:22:51.985427 == TX Byte 1 ==
2729 19:22:51.988324 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2730 19:22:51.992003 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2731 19:22:51.992109
2732 19:22:51.995144 [DATLAT]
2733 19:22:51.995255 Freq=1200, CH0 RK0
2734 19:22:51.995363
2735 19:22:51.998230 DATLAT Default: 0xd
2736 19:22:51.998339 0, 0xFFFF, sum = 0
2737 19:22:52.002013 1, 0xFFFF, sum = 0
2738 19:22:52.002134 2, 0xFFFF, sum = 0
2739 19:22:52.005093 3, 0xFFFF, sum = 0
2740 19:22:52.005227 4, 0xFFFF, sum = 0
2741 19:22:52.008664 5, 0xFFFF, sum = 0
2742 19:22:52.008784 6, 0xFFFF, sum = 0
2743 19:22:52.012106 7, 0xFFFF, sum = 0
2744 19:22:52.012213 8, 0xFFFF, sum = 0
2745 19:22:52.015166 9, 0xFFFF, sum = 0
2746 19:22:52.015276 10, 0xFFFF, sum = 0
2747 19:22:52.018639 11, 0xFFFF, sum = 0
2748 19:22:52.018750 12, 0x0, sum = 1
2749 19:22:52.021976 13, 0x0, sum = 2
2750 19:22:52.022089 14, 0x0, sum = 3
2751 19:22:52.025147 15, 0x0, sum = 4
2752 19:22:52.025261 best_step = 13
2753 19:22:52.025361
2754 19:22:52.025454 ==
2755 19:22:52.028530 Dram Type= 6, Freq= 0, CH_0, rank 0
2756 19:22:52.035424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2757 19:22:52.035545 ==
2758 19:22:52.035649 RX Vref Scan: 1
2759 19:22:52.035741
2760 19:22:52.038670 Set Vref Range= 32 -> 127
2761 19:22:52.038779
2762 19:22:52.041878 RX Vref 32 -> 127, step: 1
2763 19:22:52.041990
2764 19:22:52.042092 RX Delay -21 -> 252, step: 4
2765 19:22:52.042197
2766 19:22:52.045236 Set Vref, RX VrefLevel [Byte0]: 32
2767 19:22:52.048894 [Byte1]: 32
2768 19:22:52.053066
2769 19:22:52.053174 Set Vref, RX VrefLevel [Byte0]: 33
2770 19:22:52.056056 [Byte1]: 33
2771 19:22:52.060752
2772 19:22:52.060861 Set Vref, RX VrefLevel [Byte0]: 34
2773 19:22:52.064173 [Byte1]: 34
2774 19:22:52.068959
2775 19:22:52.069076 Set Vref, RX VrefLevel [Byte0]: 35
2776 19:22:52.072298 [Byte1]: 35
2777 19:22:52.076664
2778 19:22:52.076771 Set Vref, RX VrefLevel [Byte0]: 36
2779 19:22:52.080431 [Byte1]: 36
2780 19:22:52.084708
2781 19:22:52.084811 Set Vref, RX VrefLevel [Byte0]: 37
2782 19:22:52.088208 [Byte1]: 37
2783 19:22:52.092538
2784 19:22:52.092644 Set Vref, RX VrefLevel [Byte0]: 38
2785 19:22:52.096265 [Byte1]: 38
2786 19:22:52.100613
2787 19:22:52.100721 Set Vref, RX VrefLevel [Byte0]: 39
2788 19:22:52.104215 [Byte1]: 39
2789 19:22:52.108526
2790 19:22:52.108629 Set Vref, RX VrefLevel [Byte0]: 40
2791 19:22:52.112127 [Byte1]: 40
2792 19:22:52.116195
2793 19:22:52.116309 Set Vref, RX VrefLevel [Byte0]: 41
2794 19:22:52.120077 [Byte1]: 41
2795 19:22:52.124311
2796 19:22:52.124397 Set Vref, RX VrefLevel [Byte0]: 42
2797 19:22:52.127956 [Byte1]: 42
2798 19:22:52.132411
2799 19:22:52.132519 Set Vref, RX VrefLevel [Byte0]: 43
2800 19:22:52.135800 [Byte1]: 43
2801 19:22:52.140109
2802 19:22:52.140200 Set Vref, RX VrefLevel [Byte0]: 44
2803 19:22:52.143251 [Byte1]: 44
2804 19:22:52.148321
2805 19:22:52.148430 Set Vref, RX VrefLevel [Byte0]: 45
2806 19:22:52.151695 [Byte1]: 45
2807 19:22:52.156423
2808 19:22:52.156538 Set Vref, RX VrefLevel [Byte0]: 46
2809 19:22:52.159249 [Byte1]: 46
2810 19:22:52.164014
2811 19:22:52.164124 Set Vref, RX VrefLevel [Byte0]: 47
2812 19:22:52.167025 [Byte1]: 47
2813 19:22:52.171687
2814 19:22:52.171798 Set Vref, RX VrefLevel [Byte0]: 48
2815 19:22:52.175144 [Byte1]: 48
2816 19:22:52.179862
2817 19:22:52.179974 Set Vref, RX VrefLevel [Byte0]: 49
2818 19:22:52.183038 [Byte1]: 49
2819 19:22:52.188049
2820 19:22:52.188162 Set Vref, RX VrefLevel [Byte0]: 50
2821 19:22:52.191041 [Byte1]: 50
2822 19:22:52.195734
2823 19:22:52.195847 Set Vref, RX VrefLevel [Byte0]: 51
2824 19:22:52.199372 [Byte1]: 51
2825 19:22:52.203767
2826 19:22:52.203881 Set Vref, RX VrefLevel [Byte0]: 52
2827 19:22:52.206842 [Byte1]: 52
2828 19:22:52.211705
2829 19:22:52.211811 Set Vref, RX VrefLevel [Byte0]: 53
2830 19:22:52.214846 [Byte1]: 53
2831 19:22:52.219630
2832 19:22:52.219743 Set Vref, RX VrefLevel [Byte0]: 54
2833 19:22:52.222684 [Byte1]: 54
2834 19:22:52.227585
2835 19:22:52.227698 Set Vref, RX VrefLevel [Byte0]: 55
2836 19:22:52.230739 [Byte1]: 55
2837 19:22:52.235070
2838 19:22:52.235175 Set Vref, RX VrefLevel [Byte0]: 56
2839 19:22:52.238682 [Byte1]: 56
2840 19:22:52.242949
2841 19:22:52.243058 Set Vref, RX VrefLevel [Byte0]: 57
2842 19:22:52.246320 [Byte1]: 57
2843 19:22:52.251332
2844 19:22:52.251447 Set Vref, RX VrefLevel [Byte0]: 58
2845 19:22:52.254656 [Byte1]: 58
2846 19:22:52.258962
2847 19:22:52.259069 Set Vref, RX VrefLevel [Byte0]: 59
2848 19:22:52.262458 [Byte1]: 59
2849 19:22:52.267035
2850 19:22:52.267126 Set Vref, RX VrefLevel [Byte0]: 60
2851 19:22:52.270051 [Byte1]: 60
2852 19:22:52.275108
2853 19:22:52.275197 Set Vref, RX VrefLevel [Byte0]: 61
2854 19:22:52.278447 [Byte1]: 61
2855 19:22:52.282937
2856 19:22:52.283016 Set Vref, RX VrefLevel [Byte0]: 62
2857 19:22:52.286524 [Byte1]: 62
2858 19:22:52.290918
2859 19:22:52.291002 Set Vref, RX VrefLevel [Byte0]: 63
2860 19:22:52.294375 [Byte1]: 63
2861 19:22:52.299195
2862 19:22:52.299284 Set Vref, RX VrefLevel [Byte0]: 64
2863 19:22:52.302331 [Byte1]: 64
2864 19:22:52.306571
2865 19:22:52.306680 Set Vref, RX VrefLevel [Byte0]: 65
2866 19:22:52.310206 [Byte1]: 65
2867 19:22:52.314468
2868 19:22:52.314573 Set Vref, RX VrefLevel [Byte0]: 66
2869 19:22:52.318165 [Byte1]: 66
2870 19:22:52.322190
2871 19:22:52.322296 Set Vref, RX VrefLevel [Byte0]: 67
2872 19:22:52.325861 [Byte1]: 67
2873 19:22:52.330200
2874 19:22:52.330305 Set Vref, RX VrefLevel [Byte0]: 68
2875 19:22:52.333877 [Byte1]: 68
2876 19:22:52.338318
2877 19:22:52.338426 Set Vref, RX VrefLevel [Byte0]: 69
2878 19:22:52.341381 [Byte1]: 69
2879 19:22:52.346349
2880 19:22:52.346454 Final RX Vref Byte 0 = 51 to rank0
2881 19:22:52.350053 Final RX Vref Byte 1 = 50 to rank0
2882 19:22:52.353127 Final RX Vref Byte 0 = 51 to rank1
2883 19:22:52.356126 Final RX Vref Byte 1 = 50 to rank1==
2884 19:22:52.359679 Dram Type= 6, Freq= 0, CH_0, rank 0
2885 19:22:52.363181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2886 19:22:52.366089 ==
2887 19:22:52.366197 DQS Delay:
2888 19:22:52.366287 DQS0 = 0, DQS1 = 0
2889 19:22:52.369857 DQM Delay:
2890 19:22:52.369939 DQM0 = 115, DQM1 = 104
2891 19:22:52.372731 DQ Delay:
2892 19:22:52.376318 DQ0 =116, DQ1 =114, DQ2 =112, DQ3 =114
2893 19:22:52.379924 DQ4 =116, DQ5 =108, DQ6 =120, DQ7 =122
2894 19:22:52.383216 DQ8 =92, DQ9 =90, DQ10 =104, DQ11 =96
2895 19:22:52.386212 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =112
2896 19:22:52.386325
2897 19:22:52.386429
2898 19:22:52.393715 [DQSOSCAuto] RK0, (LSB)MR18= 0xfdec, (MSB)MR19= 0x303, tDQSOscB0 = 418 ps tDQSOscB1 = 411 ps
2899 19:22:52.396796 CH0 RK0: MR19=303, MR18=FDEC
2900 19:22:52.403147 CH0_RK0: MR19=0x303, MR18=0xFDEC, DQSOSC=411, MR23=63, INC=38, DEC=25
2901 19:22:52.403268
2902 19:22:52.406638 ----->DramcWriteLeveling(PI) begin...
2903 19:22:52.406728 ==
2904 19:22:52.409881 Dram Type= 6, Freq= 0, CH_0, rank 1
2905 19:22:52.413545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2906 19:22:52.413633 ==
2907 19:22:52.416615 Write leveling (Byte 0): 34 => 34
2908 19:22:52.419785 Write leveling (Byte 1): 28 => 28
2909 19:22:52.423374 DramcWriteLeveling(PI) end<-----
2910 19:22:52.423486
2911 19:22:52.423591 ==
2912 19:22:52.426274 Dram Type= 6, Freq= 0, CH_0, rank 1
2913 19:22:52.430024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2914 19:22:52.433119 ==
2915 19:22:52.433244 [Gating] SW mode calibration
2916 19:22:52.440004 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2917 19:22:52.446642 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2918 19:22:52.450172 0 15 0 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
2919 19:22:52.456934 0 15 4 | B1->B0 | 2a2a 3434 | 1 0 | (1 1) (0 0)
2920 19:22:52.459977 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2921 19:22:52.463583 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2922 19:22:52.469995 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2923 19:22:52.473249 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2924 19:22:52.476865 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2925 19:22:52.479988 0 15 28 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
2926 19:22:52.487036 1 0 0 | B1->B0 | 2f2f 2525 | 0 0 | (1 0) (0 0)
2927 19:22:52.490331 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2928 19:22:52.493751 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2929 19:22:52.500553 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2930 19:22:52.503727 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2931 19:22:52.507043 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2932 19:22:52.513807 1 0 24 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
2933 19:22:52.517322 1 0 28 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
2934 19:22:52.520656 1 1 0 | B1->B0 | 2c2c 3a3a | 1 0 | (0 0) (0 0)
2935 19:22:52.526855 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2936 19:22:52.530525 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2937 19:22:52.534093 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2938 19:22:52.540709 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2939 19:22:52.543751 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2940 19:22:52.547449 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2941 19:22:52.550464 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2942 19:22:52.557226 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2943 19:22:52.560811 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2944 19:22:52.563874 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2945 19:22:52.570617 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2946 19:22:52.573690 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2947 19:22:52.577095 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2948 19:22:52.583712 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 19:22:52.587431 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 19:22:52.590493 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 19:22:52.597058 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 19:22:52.600470 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 19:22:52.604043 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2954 19:22:52.610567 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2955 19:22:52.613994 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2956 19:22:52.617443 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2957 19:22:52.624107 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2958 19:22:52.627187 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2959 19:22:52.630673 Total UI for P1: 0, mck2ui 16
2960 19:22:52.634184 best dqsien dly found for B0: ( 1, 3, 26)
2961 19:22:52.637777 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2962 19:22:52.640883 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2963 19:22:52.643845 Total UI for P1: 0, mck2ui 16
2964 19:22:52.647495 best dqsien dly found for B1: ( 1, 4, 2)
2965 19:22:52.650583 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2966 19:22:52.654169 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2967 19:22:52.654270
2968 19:22:52.660795 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2969 19:22:52.663902 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2970 19:22:52.663979 [Gating] SW calibration Done
2971 19:22:52.667667 ==
2972 19:22:52.670762 Dram Type= 6, Freq= 0, CH_0, rank 1
2973 19:22:52.674454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2974 19:22:52.674537 ==
2975 19:22:52.674602 RX Vref Scan: 0
2976 19:22:52.674661
2977 19:22:52.677468 RX Vref 0 -> 0, step: 1
2978 19:22:52.677549
2979 19:22:52.681218 RX Delay -40 -> 252, step: 8
2980 19:22:52.684553 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2981 19:22:52.687973 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2982 19:22:52.691484 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2983 19:22:52.697391 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2984 19:22:52.701158 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2985 19:22:52.704133 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2986 19:22:52.707558 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2987 19:22:52.711265 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2988 19:22:52.714155 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2989 19:22:52.721129 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2990 19:22:52.724164 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2991 19:22:52.727882 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2992 19:22:52.731287 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2993 19:22:52.734671 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2994 19:22:52.741111 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2995 19:22:52.744936 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2996 19:22:52.745015 ==
2997 19:22:52.748017 Dram Type= 6, Freq= 0, CH_0, rank 1
2998 19:22:52.751045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2999 19:22:52.751125 ==
3000 19:22:52.754589 DQS Delay:
3001 19:22:52.754684 DQS0 = 0, DQS1 = 0
3002 19:22:52.754777 DQM Delay:
3003 19:22:52.758244 DQM0 = 115, DQM1 = 105
3004 19:22:52.758328 DQ Delay:
3005 19:22:52.761204 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
3006 19:22:52.764971 DQ4 =115, DQ5 =103, DQ6 =123, DQ7 =123
3007 19:22:52.768060 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
3008 19:22:52.771745 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
3009 19:22:52.774824
3010 19:22:52.774907
3011 19:22:52.774991 ==
3012 19:22:52.778467 Dram Type= 6, Freq= 0, CH_0, rank 1
3013 19:22:52.781536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3014 19:22:52.781621 ==
3015 19:22:52.781705
3016 19:22:52.781784
3017 19:22:52.784630 TX Vref Scan disable
3018 19:22:52.784715 == TX Byte 0 ==
3019 19:22:52.788254 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3020 19:22:52.795135 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3021 19:22:52.795218 == TX Byte 1 ==
3022 19:22:52.798439 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3023 19:22:52.805293 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3024 19:22:52.805371 ==
3025 19:22:52.808287 Dram Type= 6, Freq= 0, CH_0, rank 1
3026 19:22:52.812052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3027 19:22:52.812132 ==
3028 19:22:52.824211 TX Vref=22, minBit 1, minWin=25, winSum=425
3029 19:22:52.827630 TX Vref=24, minBit 3, minWin=25, winSum=430
3030 19:22:52.831219 TX Vref=26, minBit 3, minWin=25, winSum=429
3031 19:22:52.834218 TX Vref=28, minBit 3, minWin=25, winSum=435
3032 19:22:52.837821 TX Vref=30, minBit 0, minWin=27, winSum=441
3033 19:22:52.841380 TX Vref=32, minBit 1, minWin=26, winSum=435
3034 19:22:52.847896 [TxChooseVref] Worse bit 0, Min win 27, Win sum 441, Final Vref 30
3035 19:22:52.847981
3036 19:22:52.851243 Final TX Range 1 Vref 30
3037 19:22:52.851320
3038 19:22:52.851398 ==
3039 19:22:52.854491 Dram Type= 6, Freq= 0, CH_0, rank 1
3040 19:22:52.857944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3041 19:22:52.858024 ==
3042 19:22:52.858107
3043 19:22:52.858184
3044 19:22:52.861120 TX Vref Scan disable
3045 19:22:52.865147 == TX Byte 0 ==
3046 19:22:52.868249 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3047 19:22:52.871348 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3048 19:22:52.875160 == TX Byte 1 ==
3049 19:22:52.878319 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3050 19:22:52.881887 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3051 19:22:52.881971
3052 19:22:52.884927 [DATLAT]
3053 19:22:52.884999 Freq=1200, CH0 RK1
3054 19:22:52.885085
3055 19:22:52.888192 DATLAT Default: 0xd
3056 19:22:52.888279 0, 0xFFFF, sum = 0
3057 19:22:52.891858 1, 0xFFFF, sum = 0
3058 19:22:52.891944 2, 0xFFFF, sum = 0
3059 19:22:52.894967 3, 0xFFFF, sum = 0
3060 19:22:52.895080 4, 0xFFFF, sum = 0
3061 19:22:52.898486 5, 0xFFFF, sum = 0
3062 19:22:52.898572 6, 0xFFFF, sum = 0
3063 19:22:52.901481 7, 0xFFFF, sum = 0
3064 19:22:52.901567 8, 0xFFFF, sum = 0
3065 19:22:52.905322 9, 0xFFFF, sum = 0
3066 19:22:52.905429 10, 0xFFFF, sum = 0
3067 19:22:52.908269 11, 0xFFFF, sum = 0
3068 19:22:52.908345 12, 0x0, sum = 1
3069 19:22:52.911996 13, 0x0, sum = 2
3070 19:22:52.912105 14, 0x0, sum = 3
3071 19:22:52.915051 15, 0x0, sum = 4
3072 19:22:52.915134 best_step = 13
3073 19:22:52.915221
3074 19:22:52.915297 ==
3075 19:22:52.918715 Dram Type= 6, Freq= 0, CH_0, rank 1
3076 19:22:52.921607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3077 19:22:52.925115 ==
3078 19:22:52.925230 RX Vref Scan: 0
3079 19:22:52.925319
3080 19:22:52.928778 RX Vref 0 -> 0, step: 1
3081 19:22:52.928895
3082 19:22:52.931601 RX Delay -21 -> 252, step: 4
3083 19:22:52.935216 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3084 19:22:52.938625 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3085 19:22:52.941540 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3086 19:22:52.948274 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3087 19:22:52.951960 iDelay=195, Bit 4, Center 114 (47 ~ 182) 136
3088 19:22:52.955360 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3089 19:22:52.958975 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3090 19:22:52.962283 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3091 19:22:52.965888 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3092 19:22:52.972007 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3093 19:22:52.975902 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3094 19:22:52.978908 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3095 19:22:52.982532 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3096 19:22:52.985553 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3097 19:22:52.992398 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3098 19:22:52.995475 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3099 19:22:52.995551 ==
3100 19:22:52.999132 Dram Type= 6, Freq= 0, CH_0, rank 1
3101 19:22:53.002310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3102 19:22:53.002390 ==
3103 19:22:53.002451 DQS Delay:
3104 19:22:53.005869 DQS0 = 0, DQS1 = 0
3105 19:22:53.005953 DQM Delay:
3106 19:22:53.008857 DQM0 = 114, DQM1 = 104
3107 19:22:53.008930 DQ Delay:
3108 19:22:53.012347 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3109 19:22:53.015591 DQ4 =114, DQ5 =104, DQ6 =122, DQ7 =122
3110 19:22:53.019435 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =94
3111 19:22:53.022409 DQ12 =110, DQ13 =110, DQ14 =116, DQ15 =112
3112 19:22:53.022481
3113 19:22:53.022542
3114 19:22:53.032671 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f3, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 409 ps
3115 19:22:53.035749 CH0 RK1: MR19=403, MR18=1F3
3116 19:22:53.039389 CH0_RK1: MR19=0x403, MR18=0x1F3, DQSOSC=409, MR23=63, INC=39, DEC=26
3117 19:22:53.042538 [RxdqsGatingPostProcess] freq 1200
3118 19:22:53.049321 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3119 19:22:53.052692 best DQS0 dly(2T, 0.5T) = (0, 12)
3120 19:22:53.056460 best DQS1 dly(2T, 0.5T) = (0, 12)
3121 19:22:53.059361 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3122 19:22:53.062634 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3123 19:22:53.066119 best DQS0 dly(2T, 0.5T) = (0, 11)
3124 19:22:53.069614 best DQS1 dly(2T, 0.5T) = (0, 12)
3125 19:22:53.072521 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3126 19:22:53.072605 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3127 19:22:53.076186 Pre-setting of DQS Precalculation
3128 19:22:53.083080 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3129 19:22:53.083212 ==
3130 19:22:53.085973 Dram Type= 6, Freq= 0, CH_1, rank 0
3131 19:22:53.089736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3132 19:22:53.089821 ==
3133 19:22:53.096463 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3134 19:22:53.102748 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3135 19:22:53.110055 [CA 0] Center 38 (8~68) winsize 61
3136 19:22:53.113078 [CA 1] Center 38 (8~68) winsize 61
3137 19:22:53.116805 [CA 2] Center 35 (5~65) winsize 61
3138 19:22:53.119765 [CA 3] Center 34 (4~64) winsize 61
3139 19:22:53.123091 [CA 4] Center 34 (4~65) winsize 62
3140 19:22:53.126515 [CA 5] Center 33 (3~64) winsize 62
3141 19:22:53.126646
3142 19:22:53.129935 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3143 19:22:53.130037
3144 19:22:53.133558 [CATrainingPosCal] consider 1 rank data
3145 19:22:53.136694 u2DelayCellTimex100 = 270/100 ps
3146 19:22:53.140297 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3147 19:22:53.143462 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3148 19:22:53.146912 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3149 19:22:53.153870 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3150 19:22:53.156488 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3151 19:22:53.160331 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3152 19:22:53.160413
3153 19:22:53.163480 CA PerBit enable=1, Macro0, CA PI delay=33
3154 19:22:53.163561
3155 19:22:53.166687 [CBTSetCACLKResult] CA Dly = 33
3156 19:22:53.166770 CS Dly: 6 (0~37)
3157 19:22:53.166854 ==
3158 19:22:53.170270 Dram Type= 6, Freq= 0, CH_1, rank 1
3159 19:22:53.176734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3160 19:22:53.176819 ==
3161 19:22:53.180298 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3162 19:22:53.187163 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3163 19:22:53.195348 [CA 0] Center 38 (8~68) winsize 61
3164 19:22:53.199108 [CA 1] Center 38 (9~68) winsize 60
3165 19:22:53.202201 [CA 2] Center 34 (4~65) winsize 62
3166 19:22:53.205867 [CA 3] Center 34 (4~65) winsize 62
3167 19:22:53.208840 [CA 4] Center 34 (4~65) winsize 62
3168 19:22:53.212024 [CA 5] Center 33 (3~64) winsize 62
3169 19:22:53.212106
3170 19:22:53.215548 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3171 19:22:53.215623
3172 19:22:53.219164 [CATrainingPosCal] consider 2 rank data
3173 19:22:53.222277 u2DelayCellTimex100 = 270/100 ps
3174 19:22:53.225175 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3175 19:22:53.228867 CA1 delay=38 (9~68),Diff = 5 PI (24 cell)
3176 19:22:53.232271 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3177 19:22:53.239036 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3178 19:22:53.242281 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3179 19:22:53.245722 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3180 19:22:53.245808
3181 19:22:53.249341 CA PerBit enable=1, Macro0, CA PI delay=33
3182 19:22:53.249416
3183 19:22:53.252200 [CBTSetCACLKResult] CA Dly = 33
3184 19:22:53.252295 CS Dly: 7 (0~40)
3185 19:22:53.252358
3186 19:22:53.255899 ----->DramcWriteLeveling(PI) begin...
3187 19:22:53.255990 ==
3188 19:22:53.258875 Dram Type= 6, Freq= 0, CH_1, rank 0
3189 19:22:53.265647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3190 19:22:53.265729 ==
3191 19:22:53.269199 Write leveling (Byte 0): 25 => 25
3192 19:22:53.272337 Write leveling (Byte 1): 27 => 27
3193 19:22:53.272427 DramcWriteLeveling(PI) end<-----
3194 19:22:53.272492
3195 19:22:53.275636 ==
3196 19:22:53.275711 Dram Type= 6, Freq= 0, CH_1, rank 0
3197 19:22:53.282507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3198 19:22:53.282587 ==
3199 19:22:53.285708 [Gating] SW mode calibration
3200 19:22:53.292808 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3201 19:22:53.296235 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3202 19:22:53.302944 0 15 0 | B1->B0 | 2d2c 2525 | 1 0 | (0 0) (0 0)
3203 19:22:53.305959 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3204 19:22:53.309007 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3205 19:22:53.315814 0 15 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3206 19:22:53.319479 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3207 19:22:53.323175 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3208 19:22:53.326214 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3209 19:22:53.332848 0 15 28 | B1->B0 | 3333 3434 | 1 0 | (1 1) (0 1)
3210 19:22:53.336048 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3211 19:22:53.339670 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3212 19:22:53.346245 1 0 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3213 19:22:53.349979 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3214 19:22:53.353134 1 0 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3215 19:22:53.359471 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3216 19:22:53.362977 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3217 19:22:53.366455 1 0 28 | B1->B0 | 2e2e 2a2a | 0 1 | (0 0) (0 0)
3218 19:22:53.373137 1 1 0 | B1->B0 | 4444 3636 | 0 0 | (0 0) (0 0)
3219 19:22:53.376791 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3220 19:22:53.379832 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3221 19:22:53.383082 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3222 19:22:53.390014 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3223 19:22:53.392947 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3224 19:22:53.396451 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3225 19:22:53.402969 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3226 19:22:53.406944 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3227 19:22:53.409932 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3228 19:22:53.416547 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3229 19:22:53.420214 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3230 19:22:53.423179 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 19:22:53.429824 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 19:22:53.433516 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 19:22:53.436589 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 19:22:53.440257 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3235 19:22:53.447120 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3236 19:22:53.450162 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3237 19:22:53.453720 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3238 19:22:53.460372 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3239 19:22:53.463711 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3240 19:22:53.466882 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3241 19:22:53.473862 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3242 19:22:53.476957 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3243 19:22:53.480437 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3244 19:22:53.484082 Total UI for P1: 0, mck2ui 16
3245 19:22:53.487142 best dqsien dly found for B0: ( 1, 3, 30)
3246 19:22:53.490237 Total UI for P1: 0, mck2ui 16
3247 19:22:53.493652 best dqsien dly found for B1: ( 1, 3, 30)
3248 19:22:53.496970 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3249 19:22:53.500660 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3250 19:22:53.500760
3251 19:22:53.506787 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3252 19:22:53.510250 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3253 19:22:53.510341 [Gating] SW calibration Done
3254 19:22:53.513759 ==
3255 19:22:53.513852 Dram Type= 6, Freq= 0, CH_1, rank 0
3256 19:22:53.520659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3257 19:22:53.520757 ==
3258 19:22:53.520825 RX Vref Scan: 0
3259 19:22:53.520887
3260 19:22:53.523432 RX Vref 0 -> 0, step: 1
3261 19:22:53.523522
3262 19:22:53.527070 RX Delay -40 -> 252, step: 8
3263 19:22:53.530159 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3264 19:22:53.534000 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3265 19:22:53.536965 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3266 19:22:53.543869 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3267 19:22:53.547011 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3268 19:22:53.550690 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3269 19:22:53.554275 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3270 19:22:53.557325 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3271 19:22:53.560399 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3272 19:22:53.567084 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3273 19:22:53.570679 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3274 19:22:53.574152 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3275 19:22:53.577307 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3276 19:22:53.580761 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3277 19:22:53.587161 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3278 19:22:53.590359 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3279 19:22:53.590445 ==
3280 19:22:53.593783 Dram Type= 6, Freq= 0, CH_1, rank 0
3281 19:22:53.597408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3282 19:22:53.597497 ==
3283 19:22:53.600436 DQS Delay:
3284 19:22:53.600519 DQS0 = 0, DQS1 = 0
3285 19:22:53.600594 DQM Delay:
3286 19:22:53.603896 DQM0 = 117, DQM1 = 109
3287 19:22:53.603977 DQ Delay:
3288 19:22:53.607157 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =119
3289 19:22:53.610720 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =115
3290 19:22:53.614390 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =107
3291 19:22:53.617391 DQ12 =119, DQ13 =115, DQ14 =111, DQ15 =115
3292 19:22:53.620960
3293 19:22:53.621064
3294 19:22:53.621156 ==
3295 19:22:53.624107 Dram Type= 6, Freq= 0, CH_1, rank 0
3296 19:22:53.627908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3297 19:22:53.628015 ==
3298 19:22:53.628108
3299 19:22:53.628196
3300 19:22:53.630978 TX Vref Scan disable
3301 19:22:53.631061 == TX Byte 0 ==
3302 19:22:53.637480 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3303 19:22:53.640866 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3304 19:22:53.640948 == TX Byte 1 ==
3305 19:22:53.647689 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3306 19:22:53.650729 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3307 19:22:53.650835 ==
3308 19:22:53.654339 Dram Type= 6, Freq= 0, CH_1, rank 0
3309 19:22:53.657589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3310 19:22:53.657690 ==
3311 19:22:53.670020 TX Vref=22, minBit 1, minWin=25, winSum=411
3312 19:22:53.673024 TX Vref=24, minBit 1, minWin=25, winSum=416
3313 19:22:53.676605 TX Vref=26, minBit 8, minWin=25, winSum=420
3314 19:22:53.680173 TX Vref=28, minBit 0, minWin=26, winSum=426
3315 19:22:53.683216 TX Vref=30, minBit 0, minWin=26, winSum=429
3316 19:22:53.686388 TX Vref=32, minBit 11, minWin=25, winSum=431
3317 19:22:53.693003 [TxChooseVref] Worse bit 0, Min win 26, Win sum 429, Final Vref 30
3318 19:22:53.693108
3319 19:22:53.696359 Final TX Range 1 Vref 30
3320 19:22:53.696440
3321 19:22:53.696514 ==
3322 19:22:53.699641 Dram Type= 6, Freq= 0, CH_1, rank 0
3323 19:22:53.703384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3324 19:22:53.703489 ==
3325 19:22:53.703590
3326 19:22:53.703679
3327 19:22:53.706542 TX Vref Scan disable
3328 19:22:53.709887 == TX Byte 0 ==
3329 19:22:53.713045 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3330 19:22:53.716706 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3331 19:22:53.720332 == TX Byte 1 ==
3332 19:22:53.723420 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3333 19:22:53.727083 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3334 19:22:53.727182
3335 19:22:53.730364 [DATLAT]
3336 19:22:53.730440 Freq=1200, CH1 RK0
3337 19:22:53.730504
3338 19:22:53.733482 DATLAT Default: 0xd
3339 19:22:53.733566 0, 0xFFFF, sum = 0
3340 19:22:53.736813 1, 0xFFFF, sum = 0
3341 19:22:53.736899 2, 0xFFFF, sum = 0
3342 19:22:53.740347 3, 0xFFFF, sum = 0
3343 19:22:53.740432 4, 0xFFFF, sum = 0
3344 19:22:53.743570 5, 0xFFFF, sum = 0
3345 19:22:53.743666 6, 0xFFFF, sum = 0
3346 19:22:53.746827 7, 0xFFFF, sum = 0
3347 19:22:53.746920 8, 0xFFFF, sum = 0
3348 19:22:53.750138 9, 0xFFFF, sum = 0
3349 19:22:53.750235 10, 0xFFFF, sum = 0
3350 19:22:53.753702 11, 0xFFFF, sum = 0
3351 19:22:53.753788 12, 0x0, sum = 1
3352 19:22:53.756796 13, 0x0, sum = 2
3353 19:22:53.756888 14, 0x0, sum = 3
3354 19:22:53.760527 15, 0x0, sum = 4
3355 19:22:53.760611 best_step = 13
3356 19:22:53.760677
3357 19:22:53.760739 ==
3358 19:22:53.763502 Dram Type= 6, Freq= 0, CH_1, rank 0
3359 19:22:53.770294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3360 19:22:53.770385 ==
3361 19:22:53.770451 RX Vref Scan: 1
3362 19:22:53.770512
3363 19:22:53.773857 Set Vref Range= 32 -> 127
3364 19:22:53.773940
3365 19:22:53.777028 RX Vref 32 -> 127, step: 1
3366 19:22:53.777118
3367 19:22:53.777184 RX Delay -21 -> 252, step: 4
3368 19:22:53.777264
3369 19:22:53.780712 Set Vref, RX VrefLevel [Byte0]: 32
3370 19:22:53.783692 [Byte1]: 32
3371 19:22:53.788380
3372 19:22:53.788476 Set Vref, RX VrefLevel [Byte0]: 33
3373 19:22:53.791419 [Byte1]: 33
3374 19:22:53.796367
3375 19:22:53.796509 Set Vref, RX VrefLevel [Byte0]: 34
3376 19:22:53.799219 [Byte1]: 34
3377 19:22:53.804044
3378 19:22:53.804129 Set Vref, RX VrefLevel [Byte0]: 35
3379 19:22:53.807422 [Byte1]: 35
3380 19:22:53.811737
3381 19:22:53.811827 Set Vref, RX VrefLevel [Byte0]: 36
3382 19:22:53.815560 [Byte1]: 36
3383 19:22:53.819975
3384 19:22:53.820061 Set Vref, RX VrefLevel [Byte0]: 37
3385 19:22:53.823541 [Byte1]: 37
3386 19:22:53.827889
3387 19:22:53.827996 Set Vref, RX VrefLevel [Byte0]: 38
3388 19:22:53.831133 [Byte1]: 38
3389 19:22:53.835802
3390 19:22:53.835919 Set Vref, RX VrefLevel [Byte0]: 39
3391 19:22:53.839402 [Byte1]: 39
3392 19:22:53.843545
3393 19:22:53.843628 Set Vref, RX VrefLevel [Byte0]: 40
3394 19:22:53.847148 [Byte1]: 40
3395 19:22:53.851280
3396 19:22:53.851390 Set Vref, RX VrefLevel [Byte0]: 41
3397 19:22:53.854693 [Byte1]: 41
3398 19:22:53.859372
3399 19:22:53.859503 Set Vref, RX VrefLevel [Byte0]: 42
3400 19:22:53.862724 [Byte1]: 42
3401 19:22:53.867482
3402 19:22:53.867569 Set Vref, RX VrefLevel [Byte0]: 43
3403 19:22:53.870670 [Byte1]: 43
3404 19:22:53.875489
3405 19:22:53.875596 Set Vref, RX VrefLevel [Byte0]: 44
3406 19:22:53.878472 [Byte1]: 44
3407 19:22:53.883307
3408 19:22:53.883418 Set Vref, RX VrefLevel [Byte0]: 45
3409 19:22:53.886468 [Byte1]: 45
3410 19:22:53.891148
3411 19:22:53.891279 Set Vref, RX VrefLevel [Byte0]: 46
3412 19:22:53.894159 [Byte1]: 46
3413 19:22:53.899085
3414 19:22:53.899189 Set Vref, RX VrefLevel [Byte0]: 47
3415 19:22:53.902254 [Byte1]: 47
3416 19:22:53.907178
3417 19:22:53.907306 Set Vref, RX VrefLevel [Byte0]: 48
3418 19:22:53.910151 [Byte1]: 48
3419 19:22:53.915135
3420 19:22:53.915238 Set Vref, RX VrefLevel [Byte0]: 49
3421 19:22:53.918199 [Byte1]: 49
3422 19:22:53.923111
3423 19:22:53.923198 Set Vref, RX VrefLevel [Byte0]: 50
3424 19:22:53.926570 [Byte1]: 50
3425 19:22:53.930752
3426 19:22:53.930853 Set Vref, RX VrefLevel [Byte0]: 51
3427 19:22:53.933845 [Byte1]: 51
3428 19:22:53.938794
3429 19:22:53.938928 Set Vref, RX VrefLevel [Byte0]: 52
3430 19:22:53.941712 [Byte1]: 52
3431 19:22:53.946343
3432 19:22:53.946463 Set Vref, RX VrefLevel [Byte0]: 53
3433 19:22:53.949766 [Byte1]: 53
3434 19:22:53.954689
3435 19:22:53.954783 Set Vref, RX VrefLevel [Byte0]: 54
3436 19:22:53.957868 [Byte1]: 54
3437 19:22:53.962400
3438 19:22:53.962519 Set Vref, RX VrefLevel [Byte0]: 55
3439 19:22:53.965392 [Byte1]: 55
3440 19:22:53.970546
3441 19:22:53.970672 Set Vref, RX VrefLevel [Byte0]: 56
3442 19:22:53.973408 [Byte1]: 56
3443 19:22:53.978238
3444 19:22:53.978340 Set Vref, RX VrefLevel [Byte0]: 57
3445 19:22:53.981826 [Byte1]: 57
3446 19:22:53.986107
3447 19:22:53.986194 Set Vref, RX VrefLevel [Byte0]: 58
3448 19:22:53.989194 [Byte1]: 58
3449 19:22:53.993745
3450 19:22:53.993875 Set Vref, RX VrefLevel [Byte0]: 59
3451 19:22:53.997392 [Byte1]: 59
3452 19:22:54.001799
3453 19:22:54.001892 Set Vref, RX VrefLevel [Byte0]: 60
3454 19:22:54.005544 [Byte1]: 60
3455 19:22:54.009883
3456 19:22:54.009977 Set Vref, RX VrefLevel [Byte0]: 61
3457 19:22:54.013371 [Byte1]: 61
3458 19:22:54.017607
3459 19:22:54.017702 Set Vref, RX VrefLevel [Byte0]: 62
3460 19:22:54.021183 [Byte1]: 62
3461 19:22:54.025565
3462 19:22:54.025658 Set Vref, RX VrefLevel [Byte0]: 63
3463 19:22:54.029293 [Byte1]: 63
3464 19:22:54.033685
3465 19:22:54.033805 Set Vref, RX VrefLevel [Byte0]: 64
3466 19:22:54.037275 [Byte1]: 64
3467 19:22:54.041300
3468 19:22:54.041386 Set Vref, RX VrefLevel [Byte0]: 65
3469 19:22:54.044721 [Byte1]: 65
3470 19:22:54.049460
3471 19:22:54.049573 Set Vref, RX VrefLevel [Byte0]: 66
3472 19:22:54.052588 [Byte1]: 66
3473 19:22:54.057391
3474 19:22:54.057500 Set Vref, RX VrefLevel [Byte0]: 67
3475 19:22:54.060508 [Byte1]: 67
3476 19:22:54.065164
3477 19:22:54.065271 Set Vref, RX VrefLevel [Byte0]: 68
3478 19:22:54.068712 [Byte1]: 68
3479 19:22:54.073254
3480 19:22:54.073358 Set Vref, RX VrefLevel [Byte0]: 69
3481 19:22:54.076578 [Byte1]: 69
3482 19:22:54.081148
3483 19:22:54.081246 Set Vref, RX VrefLevel [Byte0]: 70
3484 19:22:54.084730 [Byte1]: 70
3485 19:22:54.089056
3486 19:22:54.089159 Set Vref, RX VrefLevel [Byte0]: 71
3487 19:22:54.092131 [Byte1]: 71
3488 19:22:54.097011
3489 19:22:54.097102 Final RX Vref Byte 0 = 59 to rank0
3490 19:22:54.100619 Final RX Vref Byte 1 = 53 to rank0
3491 19:22:54.103572 Final RX Vref Byte 0 = 59 to rank1
3492 19:22:54.107390 Final RX Vref Byte 1 = 53 to rank1==
3493 19:22:54.110326 Dram Type= 6, Freq= 0, CH_1, rank 0
3494 19:22:54.113522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3495 19:22:54.117176 ==
3496 19:22:54.117271 DQS Delay:
3497 19:22:54.117339 DQS0 = 0, DQS1 = 0
3498 19:22:54.120310 DQM Delay:
3499 19:22:54.120396 DQM0 = 116, DQM1 = 109
3500 19:22:54.123823 DQ Delay:
3501 19:22:54.127486 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3502 19:22:54.130512 DQ4 =116, DQ5 =126, DQ6 =126, DQ7 =114
3503 19:22:54.133599 DQ8 =98, DQ9 =98, DQ10 =112, DQ11 =104
3504 19:22:54.137340 DQ12 =118, DQ13 =116, DQ14 =116, DQ15 =114
3505 19:22:54.137434
3506 19:22:54.137503
3507 19:22:54.143575 [DQSOSCAuto] RK0, (LSB)MR18= 0xe3, (MSB)MR19= 0x403, tDQSOscB0 = 422 ps tDQSOscB1 = 410 ps
3508 19:22:54.147232 CH1 RK0: MR19=403, MR18=E3
3509 19:22:54.153685 CH1_RK0: MR19=0x403, MR18=0xE3, DQSOSC=410, MR23=63, INC=39, DEC=26
3510 19:22:54.153789
3511 19:22:54.157462 ----->DramcWriteLeveling(PI) begin...
3512 19:22:54.157555 ==
3513 19:22:54.160431 Dram Type= 6, Freq= 0, CH_1, rank 1
3514 19:22:54.163998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3515 19:22:54.164094 ==
3516 19:22:54.167224 Write leveling (Byte 0): 27 => 27
3517 19:22:54.170615 Write leveling (Byte 1): 27 => 27
3518 19:22:54.174444 DramcWriteLeveling(PI) end<-----
3519 19:22:54.174533
3520 19:22:54.174599 ==
3521 19:22:54.177332 Dram Type= 6, Freq= 0, CH_1, rank 1
3522 19:22:54.180347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3523 19:22:54.180443 ==
3524 19:22:54.183794 [Gating] SW mode calibration
3525 19:22:54.190366 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3526 19:22:54.197267 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3527 19:22:54.200679 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3528 19:22:54.207312 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3529 19:22:54.210344 0 15 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3530 19:22:54.214236 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3531 19:22:54.220548 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3532 19:22:54.224202 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3533 19:22:54.227188 0 15 24 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 0)
3534 19:22:54.230328 0 15 28 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
3535 19:22:54.237086 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3536 19:22:54.240853 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3537 19:22:54.243924 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3538 19:22:54.250475 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3539 19:22:54.254385 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3540 19:22:54.257285 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3541 19:22:54.263981 1 0 24 | B1->B0 | 2626 4343 | 0 0 | (0 0) (0 0)
3542 19:22:54.267455 1 0 28 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3543 19:22:54.270381 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3544 19:22:54.277041 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3545 19:22:54.280817 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3546 19:22:54.283792 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3547 19:22:54.290854 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3548 19:22:54.293833 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3549 19:22:54.297215 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3550 19:22:54.303531 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3551 19:22:54.307417 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3552 19:22:54.310454 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3553 19:22:54.314019 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3554 19:22:54.320551 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3555 19:22:54.324341 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3556 19:22:54.327335 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3557 19:22:54.333943 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3558 19:22:54.337610 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3559 19:22:54.340694 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3560 19:22:54.347482 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3561 19:22:54.350535 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3562 19:22:54.354107 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3563 19:22:54.360856 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3564 19:22:54.363846 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3565 19:22:54.367476 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3566 19:22:54.374343 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3567 19:22:54.377358 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3568 19:22:54.380742 Total UI for P1: 0, mck2ui 16
3569 19:22:54.384118 best dqsien dly found for B0: ( 1, 3, 24)
3570 19:22:54.387144 Total UI for P1: 0, mck2ui 16
3571 19:22:54.390736 best dqsien dly found for B1: ( 1, 3, 30)
3572 19:22:54.394233 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3573 19:22:54.397358 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3574 19:22:54.397477
3575 19:22:54.400878 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3576 19:22:54.404036 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3577 19:22:54.407511 [Gating] SW calibration Done
3578 19:22:54.407596 ==
3579 19:22:54.410672 Dram Type= 6, Freq= 0, CH_1, rank 1
3580 19:22:54.413735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3581 19:22:54.413821 ==
3582 19:22:54.417243 RX Vref Scan: 0
3583 19:22:54.417340
3584 19:22:54.420422 RX Vref 0 -> 0, step: 1
3585 19:22:54.420510
3586 19:22:54.420619 RX Delay -40 -> 252, step: 8
3587 19:22:54.427143 iDelay=192, Bit 0, Center 115 (40 ~ 191) 152
3588 19:22:54.430838 iDelay=192, Bit 1, Center 111 (40 ~ 183) 144
3589 19:22:54.433647 iDelay=192, Bit 2, Center 103 (32 ~ 175) 144
3590 19:22:54.437385 iDelay=192, Bit 3, Center 111 (40 ~ 183) 144
3591 19:22:54.440899 iDelay=192, Bit 4, Center 111 (40 ~ 183) 144
3592 19:22:54.447166 iDelay=192, Bit 5, Center 123 (56 ~ 191) 136
3593 19:22:54.450754 iDelay=192, Bit 6, Center 119 (48 ~ 191) 144
3594 19:22:54.453929 iDelay=192, Bit 7, Center 107 (40 ~ 175) 136
3595 19:22:54.457504 iDelay=192, Bit 8, Center 103 (32 ~ 175) 144
3596 19:22:54.460578 iDelay=192, Bit 9, Center 95 (24 ~ 167) 144
3597 19:22:54.467047 iDelay=192, Bit 10, Center 111 (40 ~ 183) 144
3598 19:22:54.470537 iDelay=192, Bit 11, Center 103 (32 ~ 175) 144
3599 19:22:54.473566 iDelay=192, Bit 12, Center 115 (48 ~ 183) 136
3600 19:22:54.477299 iDelay=192, Bit 13, Center 119 (48 ~ 191) 144
3601 19:22:54.480988 iDelay=192, Bit 14, Center 119 (48 ~ 191) 144
3602 19:22:54.487598 iDelay=192, Bit 15, Center 119 (48 ~ 191) 144
3603 19:22:54.487685 ==
3604 19:22:54.490487 Dram Type= 6, Freq= 0, CH_1, rank 1
3605 19:22:54.493918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3606 19:22:54.494006 ==
3607 19:22:54.494092 DQS Delay:
3608 19:22:54.497454 DQS0 = 0, DQS1 = 0
3609 19:22:54.497574 DQM Delay:
3610 19:22:54.500896 DQM0 = 112, DQM1 = 110
3611 19:22:54.500980 DQ Delay:
3612 19:22:54.503871 DQ0 =115, DQ1 =111, DQ2 =103, DQ3 =111
3613 19:22:54.507517 DQ4 =111, DQ5 =123, DQ6 =119, DQ7 =107
3614 19:22:54.510564 DQ8 =103, DQ9 =95, DQ10 =111, DQ11 =103
3615 19:22:54.513566 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =119
3616 19:22:54.513660
3617 19:22:54.513727
3618 19:22:54.517228 ==
3619 19:22:54.517312 Dram Type= 6, Freq= 0, CH_1, rank 1
3620 19:22:54.524073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3621 19:22:54.524160 ==
3622 19:22:54.524226
3623 19:22:54.524287
3624 19:22:54.527173 TX Vref Scan disable
3625 19:22:54.527257 == TX Byte 0 ==
3626 19:22:54.530606 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3627 19:22:54.537286 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3628 19:22:54.537381 == TX Byte 1 ==
3629 19:22:54.540552 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3630 19:22:54.547393 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3631 19:22:54.547484 ==
3632 19:22:54.550704 Dram Type= 6, Freq= 0, CH_1, rank 1
3633 19:22:54.553763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3634 19:22:54.553892 ==
3635 19:22:54.565401 TX Vref=22, minBit 0, minWin=25, winSum=414
3636 19:22:54.568704 TX Vref=24, minBit 1, minWin=25, winSum=423
3637 19:22:54.572449 TX Vref=26, minBit 2, minWin=25, winSum=425
3638 19:22:54.575588 TX Vref=28, minBit 11, minWin=26, winSum=432
3639 19:22:54.578736 TX Vref=30, minBit 2, minWin=26, winSum=429
3640 19:22:54.581940 TX Vref=32, minBit 1, minWin=26, winSum=431
3641 19:22:54.588637 [TxChooseVref] Worse bit 11, Min win 26, Win sum 432, Final Vref 28
3642 19:22:54.588718
3643 19:22:54.592231 Final TX Range 1 Vref 28
3644 19:22:54.592311
3645 19:22:54.592399 ==
3646 19:22:54.595628 Dram Type= 6, Freq= 0, CH_1, rank 1
3647 19:22:54.599086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3648 19:22:54.599212 ==
3649 19:22:54.599311
3650 19:22:54.602127
3651 19:22:54.602211 TX Vref Scan disable
3652 19:22:54.605470 == TX Byte 0 ==
3653 19:22:54.608876 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3654 19:22:54.611979 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3655 19:22:54.615668 == TX Byte 1 ==
3656 19:22:54.618785 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3657 19:22:54.622225 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3658 19:22:54.625352
3659 19:22:54.625436 [DATLAT]
3660 19:22:54.625580 Freq=1200, CH1 RK1
3661 19:22:54.625660
3662 19:22:54.629080 DATLAT Default: 0xd
3663 19:22:54.629192 0, 0xFFFF, sum = 0
3664 19:22:54.632327 1, 0xFFFF, sum = 0
3665 19:22:54.632415 2, 0xFFFF, sum = 0
3666 19:22:54.635287 3, 0xFFFF, sum = 0
3667 19:22:54.635375 4, 0xFFFF, sum = 0
3668 19:22:54.638851 5, 0xFFFF, sum = 0
3669 19:22:54.642023 6, 0xFFFF, sum = 0
3670 19:22:54.642172 7, 0xFFFF, sum = 0
3671 19:22:54.645693 8, 0xFFFF, sum = 0
3672 19:22:54.645781 9, 0xFFFF, sum = 0
3673 19:22:54.648522 10, 0xFFFF, sum = 0
3674 19:22:54.648610 11, 0xFFFF, sum = 0
3675 19:22:54.651900 12, 0x0, sum = 1
3676 19:22:54.651992 13, 0x0, sum = 2
3677 19:22:54.655850 14, 0x0, sum = 3
3678 19:22:54.655981 15, 0x0, sum = 4
3679 19:22:54.656068 best_step = 13
3680 19:22:54.656149
3681 19:22:54.659056 ==
3682 19:22:54.662141 Dram Type= 6, Freq= 0, CH_1, rank 1
3683 19:22:54.665796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3684 19:22:54.665925 ==
3685 19:22:54.666021 RX Vref Scan: 0
3686 19:22:54.666117
3687 19:22:54.668503 RX Vref 0 -> 0, step: 1
3688 19:22:54.668637
3689 19:22:54.672195 RX Delay -21 -> 252, step: 4
3690 19:22:54.675640 iDelay=191, Bit 0, Center 114 (47 ~ 182) 136
3691 19:22:54.682426 iDelay=191, Bit 1, Center 108 (43 ~ 174) 132
3692 19:22:54.685472 iDelay=191, Bit 2, Center 104 (39 ~ 170) 132
3693 19:22:54.689112 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3694 19:22:54.692262 iDelay=191, Bit 4, Center 116 (51 ~ 182) 132
3695 19:22:54.695246 iDelay=191, Bit 5, Center 124 (59 ~ 190) 132
3696 19:22:54.698723 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3697 19:22:54.705418 iDelay=191, Bit 7, Center 110 (47 ~ 174) 128
3698 19:22:54.708467 iDelay=191, Bit 8, Center 98 (31 ~ 166) 136
3699 19:22:54.712057 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3700 19:22:54.715347 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3701 19:22:54.718523 iDelay=191, Bit 11, Center 102 (35 ~ 170) 136
3702 19:22:54.725220 iDelay=191, Bit 12, Center 116 (51 ~ 182) 132
3703 19:22:54.728886 iDelay=191, Bit 13, Center 120 (55 ~ 186) 132
3704 19:22:54.732043 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3705 19:22:54.735078 iDelay=191, Bit 15, Center 120 (55 ~ 186) 132
3706 19:22:54.735162 ==
3707 19:22:54.738479 Dram Type= 6, Freq= 0, CH_1, rank 1
3708 19:22:54.745373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3709 19:22:54.745475 ==
3710 19:22:54.745579 DQS Delay:
3711 19:22:54.745662 DQS0 = 0, DQS1 = 0
3712 19:22:54.748992 DQM Delay:
3713 19:22:54.749079 DQM0 = 113, DQM1 = 110
3714 19:22:54.752025 DQ Delay:
3715 19:22:54.755507 DQ0 =114, DQ1 =108, DQ2 =104, DQ3 =112
3716 19:22:54.759187 DQ4 =116, DQ5 =124, DQ6 =122, DQ7 =110
3717 19:22:54.762173 DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =102
3718 19:22:54.765545 DQ12 =116, DQ13 =120, DQ14 =118, DQ15 =120
3719 19:22:54.765631
3720 19:22:54.765717
3721 19:22:54.772484 [DQSOSCAuto] RK1, (LSB)MR18= 0xf8ff, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 413 ps
3722 19:22:54.775700 CH1 RK1: MR19=303, MR18=F8FF
3723 19:22:54.782553 CH1_RK1: MR19=0x303, MR18=0xF8FF, DQSOSC=410, MR23=63, INC=39, DEC=26
3724 19:22:54.785778 [RxdqsGatingPostProcess] freq 1200
3725 19:22:54.792484 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3726 19:22:54.795615 best DQS0 dly(2T, 0.5T) = (0, 11)
3727 19:22:54.795698 best DQS1 dly(2T, 0.5T) = (0, 11)
3728 19:22:54.799296 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3729 19:22:54.802159 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3730 19:22:54.805763 best DQS0 dly(2T, 0.5T) = (0, 11)
3731 19:22:54.808788 best DQS1 dly(2T, 0.5T) = (0, 11)
3732 19:22:54.812417 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3733 19:22:54.815514 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3734 19:22:54.819236 Pre-setting of DQS Precalculation
3735 19:22:54.825690 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3736 19:22:54.832509 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3737 19:22:54.839251 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3738 19:22:54.839366
3739 19:22:54.839455
3740 19:22:54.842347 [Calibration Summary] 2400 Mbps
3741 19:22:54.842434 CH 0, Rank 0
3742 19:22:54.845723 SW Impedance : PASS
3743 19:22:54.845809 DUTY Scan : NO K
3744 19:22:54.849383 ZQ Calibration : PASS
3745 19:22:54.852445 Jitter Meter : NO K
3746 19:22:54.852523 CBT Training : PASS
3747 19:22:54.855513 Write leveling : PASS
3748 19:22:54.859084 RX DQS gating : PASS
3749 19:22:54.859161 RX DQ/DQS(RDDQC) : PASS
3750 19:22:54.862645 TX DQ/DQS : PASS
3751 19:22:54.865725 RX DATLAT : PASS
3752 19:22:54.865810 RX DQ/DQS(Engine): PASS
3753 19:22:54.868838 TX OE : NO K
3754 19:22:54.868920 All Pass.
3755 19:22:54.869015
3756 19:22:54.872460 CH 0, Rank 1
3757 19:22:54.872545 SW Impedance : PASS
3758 19:22:54.876050 DUTY Scan : NO K
3759 19:22:54.879112 ZQ Calibration : PASS
3760 19:22:54.879199 Jitter Meter : NO K
3761 19:22:54.882607 CBT Training : PASS
3762 19:22:54.886159 Write leveling : PASS
3763 19:22:54.886269 RX DQS gating : PASS
3764 19:22:54.889045 RX DQ/DQS(RDDQC) : PASS
3765 19:22:54.889151 TX DQ/DQS : PASS
3766 19:22:54.892279 RX DATLAT : PASS
3767 19:22:54.896027 RX DQ/DQS(Engine): PASS
3768 19:22:54.896106 TX OE : NO K
3769 19:22:54.899361 All Pass.
3770 19:22:54.899453
3771 19:22:54.899522 CH 1, Rank 0
3772 19:22:54.902360 SW Impedance : PASS
3773 19:22:54.902449 DUTY Scan : NO K
3774 19:22:54.906234 ZQ Calibration : PASS
3775 19:22:54.909100 Jitter Meter : NO K
3776 19:22:54.909190 CBT Training : PASS
3777 19:22:54.912873 Write leveling : PASS
3778 19:22:54.915769 RX DQS gating : PASS
3779 19:22:54.915897 RX DQ/DQS(RDDQC) : PASS
3780 19:22:54.919418 TX DQ/DQS : PASS
3781 19:22:54.922568 RX DATLAT : PASS
3782 19:22:54.922656 RX DQ/DQS(Engine): PASS
3783 19:22:54.926043 TX OE : NO K
3784 19:22:54.926138 All Pass.
3785 19:22:54.926216
3786 19:22:54.929113 CH 1, Rank 1
3787 19:22:54.929203 SW Impedance : PASS
3788 19:22:54.932676 DUTY Scan : NO K
3789 19:22:54.932762 ZQ Calibration : PASS
3790 19:22:54.936376 Jitter Meter : NO K
3791 19:22:54.939293 CBT Training : PASS
3792 19:22:54.939392 Write leveling : PASS
3793 19:22:54.942635 RX DQS gating : PASS
3794 19:22:54.946028 RX DQ/DQS(RDDQC) : PASS
3795 19:22:54.946116 TX DQ/DQS : PASS
3796 19:22:54.949087 RX DATLAT : PASS
3797 19:22:54.952371 RX DQ/DQS(Engine): PASS
3798 19:22:54.952459 TX OE : NO K
3799 19:22:54.955686 All Pass.
3800 19:22:54.955810
3801 19:22:54.955930 DramC Write-DBI off
3802 19:22:54.959116 PER_BANK_REFRESH: Hybrid Mode
3803 19:22:54.959204 TX_TRACKING: ON
3804 19:22:54.969230 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3805 19:22:54.972459 [FAST_K] Save calibration result to emmc
3806 19:22:54.975729 dramc_set_vcore_voltage set vcore to 650000
3807 19:22:54.979452 Read voltage for 600, 5
3808 19:22:54.979571 Vio18 = 0
3809 19:22:54.983098 Vcore = 650000
3810 19:22:54.983190 Vdram = 0
3811 19:22:54.983257 Vddq = 0
3812 19:22:54.983318 Vmddr = 0
3813 19:22:54.989211 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3814 19:22:54.995917 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3815 19:22:54.996037 MEM_TYPE=3, freq_sel=19
3816 19:22:54.999492 sv_algorithm_assistance_LP4_1600
3817 19:22:55.003168 ============ PULL DRAM RESETB DOWN ============
3818 19:22:55.009202 ========== PULL DRAM RESETB DOWN end =========
3819 19:22:55.012468 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3820 19:22:55.016038 ===================================
3821 19:22:55.019178 LPDDR4 DRAM CONFIGURATION
3822 19:22:55.022612 ===================================
3823 19:22:55.022775 EX_ROW_EN[0] = 0x0
3824 19:22:55.026223 EX_ROW_EN[1] = 0x0
3825 19:22:55.026407 LP4Y_EN = 0x0
3826 19:22:55.029232 WORK_FSP = 0x0
3827 19:22:55.029396 WL = 0x2
3828 19:22:55.033019 RL = 0x2
3829 19:22:55.033210 BL = 0x2
3830 19:22:55.036072 RPST = 0x0
3831 19:22:55.036244 RD_PRE = 0x0
3832 19:22:55.039206 WR_PRE = 0x1
3833 19:22:55.042954 WR_PST = 0x0
3834 19:22:55.043115 DBI_WR = 0x0
3835 19:22:55.046101 DBI_RD = 0x0
3836 19:22:55.046268 OTF = 0x1
3837 19:22:55.049732 ===================================
3838 19:22:55.053188 ===================================
3839 19:22:55.053351 ANA top config
3840 19:22:55.056086 ===================================
3841 19:22:55.059599 DLL_ASYNC_EN = 0
3842 19:22:55.063035 ALL_SLAVE_EN = 1
3843 19:22:55.066492 NEW_RANK_MODE = 1
3844 19:22:55.066655 DLL_IDLE_MODE = 1
3845 19:22:55.069782 LP45_APHY_COMB_EN = 1
3846 19:22:55.072825 TX_ODT_DIS = 1
3847 19:22:55.076477 NEW_8X_MODE = 1
3848 19:22:55.079532 ===================================
3849 19:22:55.083083 ===================================
3850 19:22:55.086318 data_rate = 1200
3851 19:22:55.086477 CKR = 1
3852 19:22:55.089895 DQ_P2S_RATIO = 8
3853 19:22:55.092918 ===================================
3854 19:22:55.096092 CA_P2S_RATIO = 8
3855 19:22:55.099647 DQ_CA_OPEN = 0
3856 19:22:55.102801 DQ_SEMI_OPEN = 0
3857 19:22:55.106362 CA_SEMI_OPEN = 0
3858 19:22:55.106525 CA_FULL_RATE = 0
3859 19:22:55.109923 DQ_CKDIV4_EN = 1
3860 19:22:55.112926 CA_CKDIV4_EN = 1
3861 19:22:55.116297 CA_PREDIV_EN = 0
3862 19:22:55.120073 PH8_DLY = 0
3863 19:22:55.123373 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3864 19:22:55.123525 DQ_AAMCK_DIV = 4
3865 19:22:55.126110 CA_AAMCK_DIV = 4
3866 19:22:55.129420 CA_ADMCK_DIV = 4
3867 19:22:55.133162 DQ_TRACK_CA_EN = 0
3868 19:22:55.136307 CA_PICK = 600
3869 19:22:55.139483 CA_MCKIO = 600
3870 19:22:55.139656 MCKIO_SEMI = 0
3871 19:22:55.143175 PLL_FREQ = 2288
3872 19:22:55.146252 DQ_UI_PI_RATIO = 32
3873 19:22:55.149921 CA_UI_PI_RATIO = 0
3874 19:22:55.153030 ===================================
3875 19:22:55.156549 ===================================
3876 19:22:55.159357 memory_type:LPDDR4
3877 19:22:55.159520 GP_NUM : 10
3878 19:22:55.163159 SRAM_EN : 1
3879 19:22:55.166077 MD32_EN : 0
3880 19:22:55.169631 ===================================
3881 19:22:55.169804 [ANA_INIT] >>>>>>>>>>>>>>
3882 19:22:55.173111 <<<<<< [CONFIGURE PHASE]: ANA_TX
3883 19:22:55.176366 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3884 19:22:55.179563 ===================================
3885 19:22:55.182833 data_rate = 1200,PCW = 0X5800
3886 19:22:55.186210 ===================================
3887 19:22:55.189715 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3888 19:22:55.196475 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3889 19:22:55.199548 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3890 19:22:55.206261 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3891 19:22:55.209527 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3892 19:22:55.213201 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3893 19:22:55.213366 [ANA_INIT] flow start
3894 19:22:55.216173 [ANA_INIT] PLL >>>>>>>>
3895 19:22:55.219722 [ANA_INIT] PLL <<<<<<<<
3896 19:22:55.219905 [ANA_INIT] MIDPI >>>>>>>>
3897 19:22:55.222839 [ANA_INIT] MIDPI <<<<<<<<
3898 19:22:55.226789 [ANA_INIT] DLL >>>>>>>>
3899 19:22:55.226970 [ANA_INIT] flow end
3900 19:22:55.232938 ============ LP4 DIFF to SE enter ============
3901 19:22:55.236525 ============ LP4 DIFF to SE exit ============
3902 19:22:55.239941 [ANA_INIT] <<<<<<<<<<<<<
3903 19:22:55.240102 [Flow] Enable top DCM control >>>>>
3904 19:22:55.243210 [Flow] Enable top DCM control <<<<<
3905 19:22:55.246612 Enable DLL master slave shuffle
3906 19:22:55.253075 ==============================================================
3907 19:22:55.256736 Gating Mode config
3908 19:22:55.259893 ==============================================================
3909 19:22:55.263646 Config description:
3910 19:22:55.272994 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3911 19:22:55.279673 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3912 19:22:55.283080 SELPH_MODE 0: By rank 1: By Phase
3913 19:22:55.289986 ==============================================================
3914 19:22:55.293031 GAT_TRACK_EN = 1
3915 19:22:55.296722 RX_GATING_MODE = 2
3916 19:22:55.296888 RX_GATING_TRACK_MODE = 2
3917 19:22:55.299802 SELPH_MODE = 1
3918 19:22:55.303443 PICG_EARLY_EN = 1
3919 19:22:55.306529 VALID_LAT_VALUE = 1
3920 19:22:55.313148 ==============================================================
3921 19:22:55.316956 Enter into Gating configuration >>>>
3922 19:22:55.320118 Exit from Gating configuration <<<<
3923 19:22:55.323142 Enter into DVFS_PRE_config >>>>>
3924 19:22:55.333168 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3925 19:22:55.336806 Exit from DVFS_PRE_config <<<<<
3926 19:22:55.340390 Enter into PICG configuration >>>>
3927 19:22:55.343400 Exit from PICG configuration <<<<
3928 19:22:55.346979 [RX_INPUT] configuration >>>>>
3929 19:22:55.347084 [RX_INPUT] configuration <<<<<
3930 19:22:55.353470 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3931 19:22:55.359946 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3932 19:22:55.367214 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3933 19:22:55.370226 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3934 19:22:55.376701 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3935 19:22:55.383335 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3936 19:22:55.387000 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3937 19:22:55.390399 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3938 19:22:55.396960 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3939 19:22:55.400289 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3940 19:22:55.403273 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3941 19:22:55.410537 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3942 19:22:55.410623 ===================================
3943 19:22:55.413730 LPDDR4 DRAM CONFIGURATION
3944 19:22:55.417259 ===================================
3945 19:22:55.420361 EX_ROW_EN[0] = 0x0
3946 19:22:55.420444 EX_ROW_EN[1] = 0x0
3947 19:22:55.423478 LP4Y_EN = 0x0
3948 19:22:55.423562 WORK_FSP = 0x0
3949 19:22:55.427083 WL = 0x2
3950 19:22:55.427166 RL = 0x2
3951 19:22:55.430144 BL = 0x2
3952 19:22:55.430227 RPST = 0x0
3953 19:22:55.433781 RD_PRE = 0x0
3954 19:22:55.433864 WR_PRE = 0x1
3955 19:22:55.436761 WR_PST = 0x0
3956 19:22:55.440207 DBI_WR = 0x0
3957 19:22:55.440291 DBI_RD = 0x0
3958 19:22:55.443712 OTF = 0x1
3959 19:22:55.446882 ===================================
3960 19:22:55.450403 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3961 19:22:55.453698 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3962 19:22:55.456721 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3963 19:22:55.460187 ===================================
3964 19:22:55.463656 LPDDR4 DRAM CONFIGURATION
3965 19:22:55.466982 ===================================
3966 19:22:55.470356 EX_ROW_EN[0] = 0x10
3967 19:22:55.470442 EX_ROW_EN[1] = 0x0
3968 19:22:55.473835 LP4Y_EN = 0x0
3969 19:22:55.473919 WORK_FSP = 0x0
3970 19:22:55.476733 WL = 0x2
3971 19:22:55.476816 RL = 0x2
3972 19:22:55.480398 BL = 0x2
3973 19:22:55.480482 RPST = 0x0
3974 19:22:55.483481 RD_PRE = 0x0
3975 19:22:55.483565 WR_PRE = 0x1
3976 19:22:55.487202 WR_PST = 0x0
3977 19:22:55.487285 DBI_WR = 0x0
3978 19:22:55.490103 DBI_RD = 0x0
3979 19:22:55.490186 OTF = 0x1
3980 19:22:55.493806 ===================================
3981 19:22:55.500143 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3982 19:22:55.504945 nWR fixed to 30
3983 19:22:55.508456 [ModeRegInit_LP4] CH0 RK0
3984 19:22:55.508533 [ModeRegInit_LP4] CH0 RK1
3985 19:22:55.511935 [ModeRegInit_LP4] CH1 RK0
3986 19:22:55.514939 [ModeRegInit_LP4] CH1 RK1
3987 19:22:55.515011 match AC timing 17
3988 19:22:55.521781 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3989 19:22:55.524922 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3990 19:22:55.528162 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3991 19:22:55.535494 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3992 19:22:55.538555 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3993 19:22:55.538632 ==
3994 19:22:55.541497 Dram Type= 6, Freq= 0, CH_0, rank 0
3995 19:22:55.544918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3996 19:22:55.545026 ==
3997 19:22:55.551439 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3998 19:22:55.558021 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3999 19:22:55.561436 [CA 0] Center 36 (6~66) winsize 61
4000 19:22:55.565113 [CA 1] Center 36 (6~66) winsize 61
4001 19:22:55.568000 [CA 2] Center 34 (4~65) winsize 62
4002 19:22:55.571444 [CA 3] Center 34 (4~65) winsize 62
4003 19:22:55.575076 [CA 4] Center 34 (4~64) winsize 61
4004 19:22:55.578298 [CA 5] Center 33 (3~64) winsize 62
4005 19:22:55.578381
4006 19:22:55.581830 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4007 19:22:55.581913
4008 19:22:55.585013 [CATrainingPosCal] consider 1 rank data
4009 19:22:55.587873 u2DelayCellTimex100 = 270/100 ps
4010 19:22:55.591531 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4011 19:22:55.594567 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4012 19:22:55.598291 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4013 19:22:55.601580 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4014 19:22:55.604556 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4015 19:22:55.608176 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4016 19:22:55.611111
4017 19:22:55.614433 CA PerBit enable=1, Macro0, CA PI delay=33
4018 19:22:55.614546
4019 19:22:55.618099 [CBTSetCACLKResult] CA Dly = 33
4020 19:22:55.618205 CS Dly: 5 (0~36)
4021 19:22:55.618305 ==
4022 19:22:55.621639 Dram Type= 6, Freq= 0, CH_0, rank 1
4023 19:22:55.624634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4024 19:22:55.624713 ==
4025 19:22:55.631254 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4026 19:22:55.637886 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4027 19:22:55.641448 [CA 0] Center 36 (6~66) winsize 61
4028 19:22:55.644488 [CA 1] Center 36 (6~66) winsize 61
4029 19:22:55.648162 [CA 2] Center 34 (4~65) winsize 62
4030 19:22:55.651218 [CA 3] Center 34 (4~65) winsize 62
4031 19:22:55.654502 [CA 4] Center 33 (3~64) winsize 62
4032 19:22:55.658008 [CA 5] Center 33 (3~64) winsize 62
4033 19:22:55.658113
4034 19:22:55.661656 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4035 19:22:55.661733
4036 19:22:55.664519 [CATrainingPosCal] consider 2 rank data
4037 19:22:55.668166 u2DelayCellTimex100 = 270/100 ps
4038 19:22:55.671716 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4039 19:22:55.674676 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4040 19:22:55.678324 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4041 19:22:55.681184 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4042 19:22:55.684605 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4043 19:22:55.687996 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4044 19:22:55.691386
4045 19:22:55.695039 CA PerBit enable=1, Macro0, CA PI delay=33
4046 19:22:55.695155
4047 19:22:55.698082 [CBTSetCACLKResult] CA Dly = 33
4048 19:22:55.698194 CS Dly: 5 (0~37)
4049 19:22:55.698289
4050 19:22:55.701184 ----->DramcWriteLeveling(PI) begin...
4051 19:22:55.701313 ==
4052 19:22:55.704303 Dram Type= 6, Freq= 0, CH_0, rank 0
4053 19:22:55.708369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4054 19:22:55.711613 ==
4055 19:22:55.711698 Write leveling (Byte 0): 32 => 32
4056 19:22:55.714666 Write leveling (Byte 1): 28 => 28
4057 19:22:55.718183 DramcWriteLeveling(PI) end<-----
4058 19:22:55.718273
4059 19:22:55.718345 ==
4060 19:22:55.721611 Dram Type= 6, Freq= 0, CH_0, rank 0
4061 19:22:55.728212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4062 19:22:55.728299 ==
4063 19:22:55.728365 [Gating] SW mode calibration
4064 19:22:55.738097 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4065 19:22:55.741182 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4066 19:22:55.744968 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4067 19:22:55.751680 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4068 19:22:55.754787 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4069 19:22:55.757800 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4070 19:22:55.764671 0 9 16 | B1->B0 | 2f2f 2c2c | 1 1 | (1 1) (1 0)
4071 19:22:55.768140 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4072 19:22:55.771475 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4073 19:22:55.778449 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4074 19:22:55.781384 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4075 19:22:55.785025 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4076 19:22:55.791516 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4077 19:22:55.795349 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4078 19:22:55.798498 0 10 16 | B1->B0 | 2c2c 3a3a | 0 0 | (0 0) (1 1)
4079 19:22:55.802161 0 10 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4080 19:22:55.808249 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4081 19:22:55.811776 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4082 19:22:55.815344 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4083 19:22:55.821943 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4084 19:22:55.824883 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4085 19:22:55.828543 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4086 19:22:55.835135 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4087 19:22:55.838630 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4088 19:22:55.841744 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4089 19:22:55.848654 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4090 19:22:55.851689 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4091 19:22:55.854796 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4092 19:22:55.861690 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4093 19:22:55.864746 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4094 19:22:55.868343 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4095 19:22:55.875187 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4096 19:22:55.878710 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4097 19:22:55.881538 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4098 19:22:55.888428 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4099 19:22:55.891586 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4100 19:22:55.895035 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4101 19:22:55.901452 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4102 19:22:55.905057 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4103 19:22:55.907937 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4104 19:22:55.911350 Total UI for P1: 0, mck2ui 16
4105 19:22:55.915145 best dqsien dly found for B0: ( 0, 13, 16)
4106 19:22:55.918079 Total UI for P1: 0, mck2ui 16
4107 19:22:55.921687 best dqsien dly found for B1: ( 0, 13, 14)
4108 19:22:55.925132 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4109 19:22:55.928353 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4110 19:22:55.928440
4111 19:22:55.931667 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4112 19:22:55.938010 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4113 19:22:55.938091 [Gating] SW calibration Done
4114 19:22:55.938166 ==
4115 19:22:55.941593 Dram Type= 6, Freq= 0, CH_0, rank 0
4116 19:22:55.947798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4117 19:22:55.947883 ==
4118 19:22:55.947952 RX Vref Scan: 0
4119 19:22:55.948014
4120 19:22:55.951393 RX Vref 0 -> 0, step: 1
4121 19:22:55.951473
4122 19:22:55.954570 RX Delay -230 -> 252, step: 16
4123 19:22:55.958254 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4124 19:22:55.961371 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4125 19:22:55.964558 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4126 19:22:55.971265 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4127 19:22:55.974882 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4128 19:22:55.978044 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4129 19:22:55.981122 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4130 19:22:55.988441 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4131 19:22:55.991289 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4132 19:22:55.994747 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4133 19:22:55.998101 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4134 19:22:56.001369 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4135 19:22:56.008179 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4136 19:22:56.011210 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4137 19:22:56.014704 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4138 19:22:56.018228 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4139 19:22:56.021247 ==
4140 19:22:56.021330 Dram Type= 6, Freq= 0, CH_0, rank 0
4141 19:22:56.028167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4142 19:22:56.028252 ==
4143 19:22:56.028319 DQS Delay:
4144 19:22:56.031165 DQS0 = 0, DQS1 = 0
4145 19:22:56.031250 DQM Delay:
4146 19:22:56.034640 DQM0 = 42, DQM1 = 34
4147 19:22:56.034724 DQ Delay:
4148 19:22:56.038278 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4149 19:22:56.041676 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4150 19:22:56.044522 DQ8 =17, DQ9 =17, DQ10 =41, DQ11 =25
4151 19:22:56.047942 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4152 19:22:56.048029
4153 19:22:56.048097
4154 19:22:56.048158 ==
4155 19:22:56.051391 Dram Type= 6, Freq= 0, CH_0, rank 0
4156 19:22:56.054504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4157 19:22:56.054588 ==
4158 19:22:56.054655
4159 19:22:56.054716
4160 19:22:56.058296 TX Vref Scan disable
4161 19:22:56.061373 == TX Byte 0 ==
4162 19:22:56.065080 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4163 19:22:56.068109 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4164 19:22:56.071381 == TX Byte 1 ==
4165 19:22:56.074945 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4166 19:22:56.078534 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4167 19:22:56.078620 ==
4168 19:22:56.081635 Dram Type= 6, Freq= 0, CH_0, rank 0
4169 19:22:56.084685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4170 19:22:56.084769 ==
4171 19:22:56.088488
4172 19:22:56.088571
4173 19:22:56.088640 TX Vref Scan disable
4174 19:22:56.091834 == TX Byte 0 ==
4175 19:22:56.095031 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4176 19:22:56.101830 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4177 19:22:56.101920 == TX Byte 1 ==
4178 19:22:56.105516 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4179 19:22:56.108520 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4180 19:22:56.111997
4181 19:22:56.112081 [DATLAT]
4182 19:22:56.112148 Freq=600, CH0 RK0
4183 19:22:56.112213
4184 19:22:56.115276 DATLAT Default: 0x9
4185 19:22:56.115360 0, 0xFFFF, sum = 0
4186 19:22:56.118662 1, 0xFFFF, sum = 0
4187 19:22:56.118747 2, 0xFFFF, sum = 0
4188 19:22:56.121679 3, 0xFFFF, sum = 0
4189 19:22:56.121764 4, 0xFFFF, sum = 0
4190 19:22:56.124938 5, 0xFFFF, sum = 0
4191 19:22:56.128606 6, 0xFFFF, sum = 0
4192 19:22:56.128714 7, 0xFFFF, sum = 0
4193 19:22:56.128821 8, 0x0, sum = 1
4194 19:22:56.132098 9, 0x0, sum = 2
4195 19:22:56.132184 10, 0x0, sum = 3
4196 19:22:56.135060 11, 0x0, sum = 4
4197 19:22:56.135146 best_step = 9
4198 19:22:56.135213
4199 19:22:56.135275 ==
4200 19:22:56.138777 Dram Type= 6, Freq= 0, CH_0, rank 0
4201 19:22:56.144991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4202 19:22:56.145076 ==
4203 19:22:56.145142 RX Vref Scan: 1
4204 19:22:56.145205
4205 19:22:56.148829 RX Vref 0 -> 0, step: 1
4206 19:22:56.148913
4207 19:22:56.152203 RX Delay -195 -> 252, step: 8
4208 19:22:56.152288
4209 19:22:56.155425 Set Vref, RX VrefLevel [Byte0]: 51
4210 19:22:56.158765 [Byte1]: 50
4211 19:22:56.158849
4212 19:22:56.161800 Final RX Vref Byte 0 = 51 to rank0
4213 19:22:56.165451 Final RX Vref Byte 1 = 50 to rank0
4214 19:22:56.168445 Final RX Vref Byte 0 = 51 to rank1
4215 19:22:56.172103 Final RX Vref Byte 1 = 50 to rank1==
4216 19:22:56.175251 Dram Type= 6, Freq= 0, CH_0, rank 0
4217 19:22:56.178418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4218 19:22:56.178504 ==
4219 19:22:56.181865 DQS Delay:
4220 19:22:56.181949 DQS0 = 0, DQS1 = 0
4221 19:22:56.182021 DQM Delay:
4222 19:22:56.184994 DQM0 = 42, DQM1 = 33
4223 19:22:56.185085 DQ Delay:
4224 19:22:56.188696 DQ0 =44, DQ1 =44, DQ2 =36, DQ3 =40
4225 19:22:56.191751 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4226 19:22:56.195616 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4227 19:22:56.198644 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4228 19:22:56.198728
4229 19:22:56.198795
4230 19:22:56.208147 [DQSOSCAuto] RK0, (LSB)MR18= 0x4726, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
4231 19:22:56.208266 CH0 RK0: MR19=808, MR18=4726
4232 19:22:56.214948 CH0_RK0: MR19=0x808, MR18=0x4726, DQSOSC=396, MR23=63, INC=167, DEC=111
4233 19:22:56.215031
4234 19:22:56.218596 ----->DramcWriteLeveling(PI) begin...
4235 19:22:56.222036 ==
4236 19:22:56.222111 Dram Type= 6, Freq= 0, CH_0, rank 1
4237 19:22:56.228542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4238 19:22:56.228632 ==
4239 19:22:56.231886 Write leveling (Byte 0): 32 => 32
4240 19:22:56.234753 Write leveling (Byte 1): 31 => 31
4241 19:22:56.238258 DramcWriteLeveling(PI) end<-----
4242 19:22:56.238343
4243 19:22:56.238409 ==
4244 19:22:56.241588 Dram Type= 6, Freq= 0, CH_0, rank 1
4245 19:22:56.244890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4246 19:22:56.244983 ==
4247 19:22:56.248474 [Gating] SW mode calibration
4248 19:22:56.254853 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4249 19:22:56.258162 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4250 19:22:56.265035 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4251 19:22:56.268051 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4252 19:22:56.271219 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4253 19:22:56.278128 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (0 0)
4254 19:22:56.281699 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
4255 19:22:56.284693 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4256 19:22:56.291337 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4257 19:22:56.295076 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4258 19:22:56.298080 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4259 19:22:56.304817 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4260 19:22:56.308270 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4261 19:22:56.311293 0 10 12 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
4262 19:22:56.317932 0 10 16 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
4263 19:22:56.321742 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4264 19:22:56.324894 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4265 19:22:56.331490 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4266 19:22:56.335011 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4267 19:22:56.338011 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4268 19:22:56.344646 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4269 19:22:56.348279 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4270 19:22:56.351632 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4271 19:22:56.354861 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4272 19:22:56.361300 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4273 19:22:56.365003 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4274 19:22:56.368260 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4275 19:22:56.374945 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4276 19:22:56.378049 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4277 19:22:56.381556 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4278 19:22:56.388287 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4279 19:22:56.391191 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4280 19:22:56.395004 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4281 19:22:56.401549 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4282 19:22:56.405185 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4283 19:22:56.408231 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4284 19:22:56.414996 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4285 19:22:56.418642 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4286 19:22:56.421750 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4287 19:22:56.424986 Total UI for P1: 0, mck2ui 16
4288 19:22:56.428592 best dqsien dly found for B0: ( 0, 13, 12)
4289 19:22:56.431556 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4290 19:22:56.435041 Total UI for P1: 0, mck2ui 16
4291 19:22:56.438509 best dqsien dly found for B1: ( 0, 13, 16)
4292 19:22:56.442075 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4293 19:22:56.448704 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4294 19:22:56.448790
4295 19:22:56.452056 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4296 19:22:56.455043 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4297 19:22:56.458685 [Gating] SW calibration Done
4298 19:22:56.458819 ==
4299 19:22:56.461489 Dram Type= 6, Freq= 0, CH_0, rank 1
4300 19:22:56.464837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4301 19:22:56.464942 ==
4302 19:22:56.465050 RX Vref Scan: 0
4303 19:22:56.468574
4304 19:22:56.468651 RX Vref 0 -> 0, step: 1
4305 19:22:56.468716
4306 19:22:56.471923 RX Delay -230 -> 252, step: 16
4307 19:22:56.475330 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4308 19:22:56.481459 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4309 19:22:56.484961 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4310 19:22:56.488350 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4311 19:22:56.492007 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4312 19:22:56.494844 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4313 19:22:56.501701 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4314 19:22:56.504749 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4315 19:22:56.508341 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4316 19:22:56.511445 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4317 19:22:56.518710 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4318 19:22:56.521774 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4319 19:22:56.524803 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4320 19:22:56.528510 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4321 19:22:56.531539 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4322 19:22:56.538182 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4323 19:22:56.538269 ==
4324 19:22:56.541740 Dram Type= 6, Freq= 0, CH_0, rank 1
4325 19:22:56.545173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4326 19:22:56.545275 ==
4327 19:22:56.545342 DQS Delay:
4328 19:22:56.548748 DQS0 = 0, DQS1 = 0
4329 19:22:56.548857 DQM Delay:
4330 19:22:56.551987 DQM0 = 41, DQM1 = 32
4331 19:22:56.552076 DQ Delay:
4332 19:22:56.555088 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4333 19:22:56.558789 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4334 19:22:56.561896 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4335 19:22:56.565009 DQ12 =33, DQ13 =41, DQ14 =41, DQ15 =41
4336 19:22:56.565100
4337 19:22:56.565173
4338 19:22:56.565247 ==
4339 19:22:56.568735 Dram Type= 6, Freq= 0, CH_0, rank 1
4340 19:22:56.571552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4341 19:22:56.571639 ==
4342 19:22:56.574952
4343 19:22:56.575035
4344 19:22:56.575135 TX Vref Scan disable
4345 19:22:56.578220 == TX Byte 0 ==
4346 19:22:56.581957 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4347 19:22:56.585012 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4348 19:22:56.588323 == TX Byte 1 ==
4349 19:22:56.591673 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4350 19:22:56.594980 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4351 19:22:56.595067 ==
4352 19:22:56.598284 Dram Type= 6, Freq= 0, CH_0, rank 1
4353 19:22:56.605067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4354 19:22:56.605177 ==
4355 19:22:56.605274
4356 19:22:56.605338
4357 19:22:56.605398 TX Vref Scan disable
4358 19:22:56.609983 == TX Byte 0 ==
4359 19:22:56.613140 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4360 19:22:56.619786 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4361 19:22:56.619873 == TX Byte 1 ==
4362 19:22:56.622775 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4363 19:22:56.629503 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4364 19:22:56.629591
4365 19:22:56.629662 [DATLAT]
4366 19:22:56.629725 Freq=600, CH0 RK1
4367 19:22:56.629783
4368 19:22:56.633181 DATLAT Default: 0x9
4369 19:22:56.633273 0, 0xFFFF, sum = 0
4370 19:22:56.636256 1, 0xFFFF, sum = 0
4371 19:22:56.636334 2, 0xFFFF, sum = 0
4372 19:22:56.639832 3, 0xFFFF, sum = 0
4373 19:22:56.639909 4, 0xFFFF, sum = 0
4374 19:22:56.642688 5, 0xFFFF, sum = 0
4375 19:22:56.646328 6, 0xFFFF, sum = 0
4376 19:22:56.646447 7, 0xFFFF, sum = 0
4377 19:22:56.646549 8, 0x0, sum = 1
4378 19:22:56.649817 9, 0x0, sum = 2
4379 19:22:56.649895 10, 0x0, sum = 3
4380 19:22:56.653316 11, 0x0, sum = 4
4381 19:22:56.653395 best_step = 9
4382 19:22:56.653469
4383 19:22:56.653558 ==
4384 19:22:56.656745 Dram Type= 6, Freq= 0, CH_0, rank 1
4385 19:22:56.662910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4386 19:22:56.662998 ==
4387 19:22:56.663076 RX Vref Scan: 0
4388 19:22:56.663138
4389 19:22:56.666508 RX Vref 0 -> 0, step: 1
4390 19:22:56.666616
4391 19:22:56.669514 RX Delay -195 -> 252, step: 8
4392 19:22:56.673155 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4393 19:22:56.679899 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4394 19:22:56.682825 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4395 19:22:56.686150 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4396 19:22:56.689678 iDelay=205, Bit 4, Center 40 (-107 ~ 188) 296
4397 19:22:56.692834 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4398 19:22:56.699662 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4399 19:22:56.703051 iDelay=205, Bit 7, Center 44 (-107 ~ 196) 304
4400 19:22:56.706302 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4401 19:22:56.709755 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4402 19:22:56.716625 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4403 19:22:56.719864 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4404 19:22:56.723182 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4405 19:22:56.726355 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4406 19:22:56.730017 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4407 19:22:56.736203 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4408 19:22:56.736295 ==
4409 19:22:56.739789 Dram Type= 6, Freq= 0, CH_0, rank 1
4410 19:22:56.743487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4411 19:22:56.743572 ==
4412 19:22:56.743641 DQS Delay:
4413 19:22:56.746438 DQS0 = 0, DQS1 = 0
4414 19:22:56.746547 DQM Delay:
4415 19:22:56.749514 DQM0 = 40, DQM1 = 33
4416 19:22:56.749589 DQ Delay:
4417 19:22:56.753114 DQ0 =44, DQ1 =40, DQ2 =36, DQ3 =40
4418 19:22:56.756629 DQ4 =40, DQ5 =28, DQ6 =48, DQ7 =44
4419 19:22:56.759837 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =24
4420 19:22:56.762930 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
4421 19:22:56.763019
4422 19:22:56.763098
4423 19:22:56.769971 [DQSOSCAuto] RK1, (LSB)MR18= 0x4e30, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 395 ps
4424 19:22:56.773114 CH0 RK1: MR19=808, MR18=4E30
4425 19:22:56.779961 CH0_RK1: MR19=0x808, MR18=0x4E30, DQSOSC=395, MR23=63, INC=168, DEC=112
4426 19:22:56.783049 [RxdqsGatingPostProcess] freq 600
4427 19:22:56.790064 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4428 19:22:56.793430 Pre-setting of DQS Precalculation
4429 19:22:56.796869 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4430 19:22:56.796990 ==
4431 19:22:56.800062 Dram Type= 6, Freq= 0, CH_1, rank 0
4432 19:22:56.803227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4433 19:22:56.803316 ==
4434 19:22:56.810059 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4435 19:22:56.816810 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4436 19:22:56.819811 [CA 0] Center 35 (5~66) winsize 62
4437 19:22:56.823399 [CA 1] Center 35 (5~65) winsize 61
4438 19:22:56.826958 [CA 2] Center 33 (3~64) winsize 62
4439 19:22:56.829747 [CA 3] Center 33 (3~64) winsize 62
4440 19:22:56.833254 [CA 4] Center 33 (3~64) winsize 62
4441 19:22:56.836885 [CA 5] Center 33 (3~64) winsize 62
4442 19:22:56.837002
4443 19:22:56.839935 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4444 19:22:56.840021
4445 19:22:56.843427 [CATrainingPosCal] consider 1 rank data
4446 19:22:56.847052 u2DelayCellTimex100 = 270/100 ps
4447 19:22:56.849883 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4448 19:22:56.853524 CA1 delay=35 (5~65),Diff = 2 PI (19 cell)
4449 19:22:56.856576 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4450 19:22:56.860295 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4451 19:22:56.863902 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4452 19:22:56.866714 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4453 19:22:56.866804
4454 19:22:56.873714 CA PerBit enable=1, Macro0, CA PI delay=33
4455 19:22:56.873811
4456 19:22:56.873879 [CBTSetCACLKResult] CA Dly = 33
4457 19:22:56.876997 CS Dly: 5 (0~36)
4458 19:22:56.877070 ==
4459 19:22:56.879964 Dram Type= 6, Freq= 0, CH_1, rank 1
4460 19:22:56.883596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4461 19:22:56.883680 ==
4462 19:22:56.890411 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4463 19:22:56.896949 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4464 19:22:56.899808 [CA 0] Center 35 (5~66) winsize 62
4465 19:22:56.903375 [CA 1] Center 36 (6~66) winsize 61
4466 19:22:56.906585 [CA 2] Center 34 (4~65) winsize 62
4467 19:22:56.910321 [CA 3] Center 34 (3~65) winsize 63
4468 19:22:56.913372 [CA 4] Center 34 (3~65) winsize 63
4469 19:22:56.916675 [CA 5] Center 33 (3~64) winsize 62
4470 19:22:56.916758
4471 19:22:56.920057 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4472 19:22:56.920141
4473 19:22:56.923727 [CATrainingPosCal] consider 2 rank data
4474 19:22:56.926781 u2DelayCellTimex100 = 270/100 ps
4475 19:22:56.929925 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4476 19:22:56.933456 CA1 delay=35 (6~65),Diff = 2 PI (19 cell)
4477 19:22:56.936764 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4478 19:22:56.940519 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4479 19:22:56.943403 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4480 19:22:56.946695 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4481 19:22:56.946808
4482 19:22:56.953135 CA PerBit enable=1, Macro0, CA PI delay=33
4483 19:22:56.953229
4484 19:22:56.956777 [CBTSetCACLKResult] CA Dly = 33
4485 19:22:56.956861 CS Dly: 5 (0~36)
4486 19:22:56.956931
4487 19:22:56.960389 ----->DramcWriteLeveling(PI) begin...
4488 19:22:56.960472 ==
4489 19:22:56.963435 Dram Type= 6, Freq= 0, CH_1, rank 0
4490 19:22:56.966406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4491 19:22:56.969800 ==
4492 19:22:56.969885 Write leveling (Byte 0): 30 => 30
4493 19:22:56.973303 Write leveling (Byte 1): 31 => 31
4494 19:22:56.976670 DramcWriteLeveling(PI) end<-----
4495 19:22:56.976753
4496 19:22:56.976818 ==
4497 19:22:56.980137 Dram Type= 6, Freq= 0, CH_1, rank 0
4498 19:22:56.986311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4499 19:22:56.986396 ==
4500 19:22:56.986473 [Gating] SW mode calibration
4501 19:22:56.996620 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4502 19:22:56.999484 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4503 19:22:57.003014 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4504 19:22:57.009630 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4505 19:22:57.013165 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4506 19:22:57.016348 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
4507 19:22:57.022915 0 9 16 | B1->B0 | 2828 2626 | 0 0 | (1 1) (0 0)
4508 19:22:57.026255 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4509 19:22:57.030024 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4510 19:22:57.035961 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4511 19:22:57.039705 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4512 19:22:57.042888 0 10 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4513 19:22:57.049663 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4514 19:22:57.053164 0 10 12 | B1->B0 | 2525 2626 | 0 0 | (0 0) (0 0)
4515 19:22:57.056012 0 10 16 | B1->B0 | 3c3c 4040 | 1 0 | (0 0) (0 0)
4516 19:22:57.063091 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4517 19:22:57.066192 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4518 19:22:57.069530 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4519 19:22:57.076513 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4520 19:22:57.079887 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4521 19:22:57.083206 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4522 19:22:57.089873 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4523 19:22:57.093053 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4524 19:22:57.096534 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4525 19:22:57.099754 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4526 19:22:57.106767 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4527 19:22:57.109878 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4528 19:22:57.113377 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4529 19:22:57.120029 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4530 19:22:57.122981 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4531 19:22:57.126610 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4532 19:22:57.133080 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4533 19:22:57.136147 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4534 19:22:57.139686 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4535 19:22:57.146693 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4536 19:22:57.149736 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4537 19:22:57.153351 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4538 19:22:57.159932 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4539 19:22:57.162995 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4540 19:22:57.166541 Total UI for P1: 0, mck2ui 16
4541 19:22:57.170164 best dqsien dly found for B0: ( 0, 13, 12)
4542 19:22:57.172924 Total UI for P1: 0, mck2ui 16
4543 19:22:57.176687 best dqsien dly found for B1: ( 0, 13, 12)
4544 19:22:57.179617 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4545 19:22:57.183334 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4546 19:22:57.183452
4547 19:22:57.186467 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4548 19:22:57.189910 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4549 19:22:57.193063 [Gating] SW calibration Done
4550 19:22:57.193163 ==
4551 19:22:57.196564 Dram Type= 6, Freq= 0, CH_1, rank 0
4552 19:22:57.199737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4553 19:22:57.199838 ==
4554 19:22:57.203524 RX Vref Scan: 0
4555 19:22:57.203637
4556 19:22:57.206427 RX Vref 0 -> 0, step: 1
4557 19:22:57.206504
4558 19:22:57.206573 RX Delay -230 -> 252, step: 16
4559 19:22:57.213176 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4560 19:22:57.216752 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4561 19:22:57.219649 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4562 19:22:57.223108 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4563 19:22:57.230309 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4564 19:22:57.233194 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4565 19:22:57.236556 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4566 19:22:57.239749 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4567 19:22:57.243283 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4568 19:22:57.250259 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4569 19:22:57.253331 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4570 19:22:57.257005 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4571 19:22:57.260163 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4572 19:22:57.266717 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4573 19:22:57.269694 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4574 19:22:57.273281 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4575 19:22:57.273356 ==
4576 19:22:57.276428 Dram Type= 6, Freq= 0, CH_1, rank 0
4577 19:22:57.280079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4578 19:22:57.280159 ==
4579 19:22:57.283165 DQS Delay:
4580 19:22:57.283237 DQS0 = 0, DQS1 = 0
4581 19:22:57.287110 DQM Delay:
4582 19:22:57.287192 DQM0 = 44, DQM1 = 36
4583 19:22:57.287259 DQ Delay:
4584 19:22:57.289970 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4585 19:22:57.293456 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4586 19:22:57.296723 DQ8 =17, DQ9 =25, DQ10 =41, DQ11 =33
4587 19:22:57.300033 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4588 19:22:57.300138
4589 19:22:57.300242
4590 19:22:57.300315 ==
4591 19:22:57.303324 Dram Type= 6, Freq= 0, CH_1, rank 0
4592 19:22:57.310198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4593 19:22:57.310289 ==
4594 19:22:57.310356
4595 19:22:57.310424
4596 19:22:57.310487 TX Vref Scan disable
4597 19:22:57.314080 == TX Byte 0 ==
4598 19:22:57.317134 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4599 19:22:57.323899 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4600 19:22:57.323976 == TX Byte 1 ==
4601 19:22:57.327297 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4602 19:22:57.331033 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4603 19:22:57.333935 ==
4604 19:22:57.337252 Dram Type= 6, Freq= 0, CH_1, rank 0
4605 19:22:57.340906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4606 19:22:57.340986 ==
4607 19:22:57.341049
4608 19:22:57.341109
4609 19:22:57.344004 TX Vref Scan disable
4610 19:22:57.344074 == TX Byte 0 ==
4611 19:22:57.350624 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4612 19:22:57.354176 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4613 19:22:57.354260 == TX Byte 1 ==
4614 19:22:57.360978 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4615 19:22:57.363864 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4616 19:22:57.363952
4617 19:22:57.364022 [DATLAT]
4618 19:22:57.367380 Freq=600, CH1 RK0
4619 19:22:57.367455
4620 19:22:57.367517 DATLAT Default: 0x9
4621 19:22:57.371091 0, 0xFFFF, sum = 0
4622 19:22:57.371177 1, 0xFFFF, sum = 0
4623 19:22:57.374111 2, 0xFFFF, sum = 0
4624 19:22:57.374195 3, 0xFFFF, sum = 0
4625 19:22:57.377756 4, 0xFFFF, sum = 0
4626 19:22:57.377840 5, 0xFFFF, sum = 0
4627 19:22:57.380780 6, 0xFFFF, sum = 0
4628 19:22:57.380857 7, 0xFFFF, sum = 0
4629 19:22:57.384455 8, 0x0, sum = 1
4630 19:22:57.384551 9, 0x0, sum = 2
4631 19:22:57.387476 10, 0x0, sum = 3
4632 19:22:57.387547 11, 0x0, sum = 4
4633 19:22:57.391011 best_step = 9
4634 19:22:57.391091
4635 19:22:57.391156 ==
4636 19:22:57.393985 Dram Type= 6, Freq= 0, CH_1, rank 0
4637 19:22:57.397059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4638 19:22:57.397131 ==
4639 19:22:57.400636 RX Vref Scan: 1
4640 19:22:57.400716
4641 19:22:57.400780 RX Vref 0 -> 0, step: 1
4642 19:22:57.400840
4643 19:22:57.403988 RX Delay -195 -> 252, step: 8
4644 19:22:57.404069
4645 19:22:57.407282 Set Vref, RX VrefLevel [Byte0]: 59
4646 19:22:57.410463 [Byte1]: 53
4647 19:22:57.414570
4648 19:22:57.414649 Final RX Vref Byte 0 = 59 to rank0
4649 19:22:57.417898 Final RX Vref Byte 1 = 53 to rank0
4650 19:22:57.421232 Final RX Vref Byte 0 = 59 to rank1
4651 19:22:57.424403 Final RX Vref Byte 1 = 53 to rank1==
4652 19:22:57.428038 Dram Type= 6, Freq= 0, CH_1, rank 0
4653 19:22:57.434468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4654 19:22:57.434560 ==
4655 19:22:57.434628 DQS Delay:
4656 19:22:57.434716 DQS0 = 0, DQS1 = 0
4657 19:22:57.437909 DQM Delay:
4658 19:22:57.437994 DQM0 = 40, DQM1 = 33
4659 19:22:57.440855 DQ Delay:
4660 19:22:57.444633 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4661 19:22:57.444743 DQ4 =40, DQ5 =48, DQ6 =52, DQ7 =36
4662 19:22:57.447642 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =28
4663 19:22:57.454341 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4664 19:22:57.454424
4665 19:22:57.454489
4666 19:22:57.461035 [DQSOSCAuto] RK0, (LSB)MR18= 0x4a0f, (MSB)MR19= 0x808, tDQSOscB0 = 407 ps tDQSOscB1 = 395 ps
4667 19:22:57.464590 CH1 RK0: MR19=808, MR18=4A0F
4668 19:22:57.471494 CH1_RK0: MR19=0x808, MR18=0x4A0F, DQSOSC=395, MR23=63, INC=168, DEC=112
4669 19:22:57.471578
4670 19:22:57.474466 ----->DramcWriteLeveling(PI) begin...
4671 19:22:57.474551 ==
4672 19:22:57.478204 Dram Type= 6, Freq= 0, CH_1, rank 1
4673 19:22:57.481087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4674 19:22:57.481199 ==
4675 19:22:57.484823 Write leveling (Byte 0): 29 => 29
4676 19:22:57.487851 Write leveling (Byte 1): 29 => 29
4677 19:22:57.491002 DramcWriteLeveling(PI) end<-----
4678 19:22:57.491086
4679 19:22:57.491152 ==
4680 19:22:57.494489 Dram Type= 6, Freq= 0, CH_1, rank 1
4681 19:22:57.498082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4682 19:22:57.498193 ==
4683 19:22:57.501032 [Gating] SW mode calibration
4684 19:22:57.508007 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4685 19:22:57.514652 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4686 19:22:57.517575 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4687 19:22:57.521144 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4688 19:22:57.527709 0 9 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 0)
4689 19:22:57.530922 0 9 12 | B1->B0 | 2f2f 2f2f | 0 0 | (0 0) (0 0)
4690 19:22:57.534431 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4691 19:22:57.541198 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4692 19:22:57.544180 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4693 19:22:57.548075 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4694 19:22:57.554206 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4695 19:22:57.557622 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4696 19:22:57.561398 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4697 19:22:57.567558 0 10 12 | B1->B0 | 2f2f 3e3e | 0 0 | (0 0) (0 0)
4698 19:22:57.571411 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4699 19:22:57.574547 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4700 19:22:57.580878 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4701 19:22:57.584061 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4702 19:22:57.587696 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4703 19:22:57.594643 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4704 19:22:57.597626 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4705 19:22:57.601099 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4706 19:22:57.604170 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4707 19:22:57.610967 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4708 19:22:57.614312 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4709 19:22:57.617972 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4710 19:22:57.624254 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4711 19:22:57.627895 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4712 19:22:57.630837 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4713 19:22:57.637741 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4714 19:22:57.640892 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4715 19:22:57.644391 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4716 19:22:57.650896 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4717 19:22:57.654259 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4718 19:22:57.657576 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4719 19:22:57.664729 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4720 19:22:57.667886 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4721 19:22:57.671078 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4722 19:22:57.677867 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4723 19:22:57.677962 Total UI for P1: 0, mck2ui 16
4724 19:22:57.681417 best dqsien dly found for B0: ( 0, 13, 12)
4725 19:22:57.684320 Total UI for P1: 0, mck2ui 16
4726 19:22:57.688019 best dqsien dly found for B1: ( 0, 13, 14)
4727 19:22:57.691043 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4728 19:22:57.697889 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4729 19:22:57.697983
4730 19:22:57.701119 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4731 19:22:57.704662 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4732 19:22:57.708034 [Gating] SW calibration Done
4733 19:22:57.708121 ==
4734 19:22:57.711077 Dram Type= 6, Freq= 0, CH_1, rank 1
4735 19:22:57.714684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4736 19:22:57.714771 ==
4737 19:22:57.714840 RX Vref Scan: 0
4738 19:22:57.717693
4739 19:22:57.717767 RX Vref 0 -> 0, step: 1
4740 19:22:57.717831
4741 19:22:57.721361 RX Delay -230 -> 252, step: 16
4742 19:22:57.724675 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4743 19:22:57.731157 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4744 19:22:57.734322 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4745 19:22:57.737820 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4746 19:22:57.741169 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4747 19:22:57.744702 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4748 19:22:57.751352 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4749 19:22:57.754386 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4750 19:22:57.758122 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4751 19:22:57.761006 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4752 19:22:57.768056 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4753 19:22:57.771048 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4754 19:22:57.774315 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4755 19:22:57.778228 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4756 19:22:57.781125 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4757 19:22:57.787757 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4758 19:22:57.787853 ==
4759 19:22:57.791620 Dram Type= 6, Freq= 0, CH_1, rank 1
4760 19:22:57.794741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4761 19:22:57.794821 ==
4762 19:22:57.794907 DQS Delay:
4763 19:22:57.797811 DQS0 = 0, DQS1 = 0
4764 19:22:57.797886 DQM Delay:
4765 19:22:57.801419 DQM0 = 41, DQM1 = 37
4766 19:22:57.801496 DQ Delay:
4767 19:22:57.804500 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41
4768 19:22:57.807615 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4769 19:22:57.810986 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4770 19:22:57.814554 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4771 19:22:57.814642
4772 19:22:57.814728
4773 19:22:57.814807 ==
4774 19:22:57.817706 Dram Type= 6, Freq= 0, CH_1, rank 1
4775 19:22:57.821364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4776 19:22:57.821447 ==
4777 19:22:57.824517
4778 19:22:57.824603
4779 19:22:57.824690 TX Vref Scan disable
4780 19:22:57.827650 == TX Byte 0 ==
4781 19:22:57.831239 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4782 19:22:57.834184 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4783 19:22:57.837694 == TX Byte 1 ==
4784 19:22:57.840906 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4785 19:22:57.844124 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4786 19:22:57.847430 ==
4787 19:22:57.847525 Dram Type= 6, Freq= 0, CH_1, rank 1
4788 19:22:57.854550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4789 19:22:57.854653 ==
4790 19:22:57.854742
4791 19:22:57.854826
4792 19:22:57.857435 TX Vref Scan disable
4793 19:22:57.857516 == TX Byte 0 ==
4794 19:22:57.863982 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4795 19:22:57.867345 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4796 19:22:57.867439 == TX Byte 1 ==
4797 19:22:57.874398 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4798 19:22:57.877355 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4799 19:22:57.877483
4800 19:22:57.877586 [DATLAT]
4801 19:22:57.880694 Freq=600, CH1 RK1
4802 19:22:57.880817
4803 19:22:57.880929 DATLAT Default: 0x9
4804 19:22:57.884027 0, 0xFFFF, sum = 0
4805 19:22:57.884118 1, 0xFFFF, sum = 0
4806 19:22:57.887584 2, 0xFFFF, sum = 0
4807 19:22:57.887681 3, 0xFFFF, sum = 0
4808 19:22:57.891120 4, 0xFFFF, sum = 0
4809 19:22:57.891212 5, 0xFFFF, sum = 0
4810 19:22:57.894313 6, 0xFFFF, sum = 0
4811 19:22:57.897431 7, 0xFFFF, sum = 0
4812 19:22:57.897574 8, 0x0, sum = 1
4813 19:22:57.897684 9, 0x0, sum = 2
4814 19:22:57.900541 10, 0x0, sum = 3
4815 19:22:57.900632 11, 0x0, sum = 4
4816 19:22:57.904282 best_step = 9
4817 19:22:57.904388
4818 19:22:57.904459 ==
4819 19:22:57.907484 Dram Type= 6, Freq= 0, CH_1, rank 1
4820 19:22:57.910967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4821 19:22:57.911054 ==
4822 19:22:57.913846 RX Vref Scan: 0
4823 19:22:57.913927
4824 19:22:57.914002 RX Vref 0 -> 0, step: 1
4825 19:22:57.914065
4826 19:22:57.917242 RX Delay -179 -> 252, step: 8
4827 19:22:57.924717 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4828 19:22:57.927764 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4829 19:22:57.930840 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4830 19:22:57.934477 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4831 19:22:57.941078 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4832 19:22:57.944726 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4833 19:22:57.947524 iDelay=205, Bit 6, Center 52 (-99 ~ 204) 304
4834 19:22:57.951074 iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304
4835 19:22:57.954283 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4836 19:22:57.961229 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4837 19:22:57.964690 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4838 19:22:57.968096 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4839 19:22:57.971104 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4840 19:22:57.977937 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4841 19:22:57.981271 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4842 19:22:57.984645 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4843 19:22:57.984768 ==
4844 19:22:57.987806 Dram Type= 6, Freq= 0, CH_1, rank 1
4845 19:22:57.991244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4846 19:22:57.991339 ==
4847 19:22:57.995189 DQS Delay:
4848 19:22:57.995288 DQS0 = 0, DQS1 = 0
4849 19:22:57.997982 DQM Delay:
4850 19:22:57.998075 DQM0 = 39, DQM1 = 33
4851 19:22:57.998163 DQ Delay:
4852 19:22:58.001598 DQ0 =44, DQ1 =32, DQ2 =24, DQ3 =36
4853 19:22:58.004700 DQ4 =40, DQ5 =48, DQ6 =52, DQ7 =36
4854 19:22:58.008404 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =24
4855 19:22:58.011424 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =40
4856 19:22:58.011520
4857 19:22:58.011599
4858 19:22:58.021728 [DQSOSCAuto] RK1, (LSB)MR18= 0x3f4d, (MSB)MR19= 0x808, tDQSOscB0 = 395 ps tDQSOscB1 = 397 ps
4859 19:22:58.024859 CH1 RK1: MR19=808, MR18=3F4D
4860 19:22:58.027968 CH1_RK1: MR19=0x808, MR18=0x3F4D, DQSOSC=395, MR23=63, INC=168, DEC=112
4861 19:22:58.031730 [RxdqsGatingPostProcess] freq 600
4862 19:22:58.038459 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4863 19:22:58.041420 Pre-setting of DQS Precalculation
4864 19:22:58.045228 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4865 19:22:58.051823 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4866 19:22:58.061886 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4867 19:22:58.062029
4868 19:22:58.062100
4869 19:22:58.064906 [Calibration Summary] 1200 Mbps
4870 19:22:58.065029 CH 0, Rank 0
4871 19:22:58.068471 SW Impedance : PASS
4872 19:22:58.068556 DUTY Scan : NO K
4873 19:22:58.071737 ZQ Calibration : PASS
4874 19:22:58.071858 Jitter Meter : NO K
4875 19:22:58.075053 CBT Training : PASS
4876 19:22:58.078625 Write leveling : PASS
4877 19:22:58.078725 RX DQS gating : PASS
4878 19:22:58.081479 RX DQ/DQS(RDDQC) : PASS
4879 19:22:58.085100 TX DQ/DQS : PASS
4880 19:22:58.085238 RX DATLAT : PASS
4881 19:22:58.088427 RX DQ/DQS(Engine): PASS
4882 19:22:58.091605 TX OE : NO K
4883 19:22:58.091729 All Pass.
4884 19:22:58.091825
4885 19:22:58.091915 CH 0, Rank 1
4886 19:22:58.095363 SW Impedance : PASS
4887 19:22:58.098644 DUTY Scan : NO K
4888 19:22:58.098742 ZQ Calibration : PASS
4889 19:22:58.102049 Jitter Meter : NO K
4890 19:22:58.105180 CBT Training : PASS
4891 19:22:58.105333 Write leveling : PASS
4892 19:22:58.108319 RX DQS gating : PASS
4893 19:22:58.108417 RX DQ/DQS(RDDQC) : PASS
4894 19:22:58.111888 TX DQ/DQS : PASS
4895 19:22:58.114998 RX DATLAT : PASS
4896 19:22:58.115122 RX DQ/DQS(Engine): PASS
4897 19:22:58.118737 TX OE : NO K
4898 19:22:58.118849 All Pass.
4899 19:22:58.118950
4900 19:22:58.121929 CH 1, Rank 0
4901 19:22:58.122022 SW Impedance : PASS
4902 19:22:58.125416 DUTY Scan : NO K
4903 19:22:58.128426 ZQ Calibration : PASS
4904 19:22:58.128520 Jitter Meter : NO K
4905 19:22:58.132062 CBT Training : PASS
4906 19:22:58.134941 Write leveling : PASS
4907 19:22:58.135048 RX DQS gating : PASS
4908 19:22:58.138737 RX DQ/DQS(RDDQC) : PASS
4909 19:22:58.141727 TX DQ/DQS : PASS
4910 19:22:58.141815 RX DATLAT : PASS
4911 19:22:58.145382 RX DQ/DQS(Engine): PASS
4912 19:22:58.148558 TX OE : NO K
4913 19:22:58.148642 All Pass.
4914 19:22:58.148727
4915 19:22:58.148807 CH 1, Rank 1
4916 19:22:58.151624 SW Impedance : PASS
4917 19:22:58.155301 DUTY Scan : NO K
4918 19:22:58.155386 ZQ Calibration : PASS
4919 19:22:58.158251 Jitter Meter : NO K
4920 19:22:58.158337 CBT Training : PASS
4921 19:22:58.161791 Write leveling : PASS
4922 19:22:58.165354 RX DQS gating : PASS
4923 19:22:58.165457 RX DQ/DQS(RDDQC) : PASS
4924 19:22:58.168315 TX DQ/DQS : PASS
4925 19:22:58.172103 RX DATLAT : PASS
4926 19:22:58.172194 RX DQ/DQS(Engine): PASS
4927 19:22:58.174937 TX OE : NO K
4928 19:22:58.175020 All Pass.
4929 19:22:58.175104
4930 19:22:58.178699 DramC Write-DBI off
4931 19:22:58.181732 PER_BANK_REFRESH: Hybrid Mode
4932 19:22:58.181822 TX_TRACKING: ON
4933 19:22:58.191754 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4934 19:22:58.195217 [FAST_K] Save calibration result to emmc
4935 19:22:58.198689 dramc_set_vcore_voltage set vcore to 662500
4936 19:22:58.202003 Read voltage for 933, 3
4937 19:22:58.202117 Vio18 = 0
4938 19:22:58.202219 Vcore = 662500
4939 19:22:58.205274 Vdram = 0
4940 19:22:58.205405 Vddq = 0
4941 19:22:58.205503 Vmddr = 0
4942 19:22:58.211975 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4943 19:22:58.215132 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4944 19:22:58.218375 MEM_TYPE=3, freq_sel=17
4945 19:22:58.221860 sv_algorithm_assistance_LP4_1600
4946 19:22:58.225010 ============ PULL DRAM RESETB DOWN ============
4947 19:22:58.228502 ========== PULL DRAM RESETB DOWN end =========
4948 19:22:58.235264 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4949 19:22:58.238126 ===================================
4950 19:22:58.238221 LPDDR4 DRAM CONFIGURATION
4951 19:22:58.241795 ===================================
4952 19:22:58.244795 EX_ROW_EN[0] = 0x0
4953 19:22:58.248505 EX_ROW_EN[1] = 0x0
4954 19:22:58.248595 LP4Y_EN = 0x0
4955 19:22:58.251626 WORK_FSP = 0x0
4956 19:22:58.251723 WL = 0x3
4957 19:22:58.255206 RL = 0x3
4958 19:22:58.255295 BL = 0x2
4959 19:22:58.258247 RPST = 0x0
4960 19:22:58.258367 RD_PRE = 0x0
4961 19:22:58.261821 WR_PRE = 0x1
4962 19:22:58.261936 WR_PST = 0x0
4963 19:22:58.265182 DBI_WR = 0x0
4964 19:22:58.265286 DBI_RD = 0x0
4965 19:22:58.268305 OTF = 0x1
4966 19:22:58.272069 ===================================
4967 19:22:58.275278 ===================================
4968 19:22:58.275387 ANA top config
4969 19:22:58.278716 ===================================
4970 19:22:58.281833 DLL_ASYNC_EN = 0
4971 19:22:58.284870 ALL_SLAVE_EN = 1
4972 19:22:58.284969 NEW_RANK_MODE = 1
4973 19:22:58.288367 DLL_IDLE_MODE = 1
4974 19:22:58.292064 LP45_APHY_COMB_EN = 1
4975 19:22:58.294888 TX_ODT_DIS = 1
4976 19:22:58.298321 NEW_8X_MODE = 1
4977 19:22:58.301869 ===================================
4978 19:22:58.305395 ===================================
4979 19:22:58.305549 data_rate = 1866
4980 19:22:58.308244 CKR = 1
4981 19:22:58.311847 DQ_P2S_RATIO = 8
4982 19:22:58.315476 ===================================
4983 19:22:58.318531 CA_P2S_RATIO = 8
4984 19:22:58.321557 DQ_CA_OPEN = 0
4985 19:22:58.325168 DQ_SEMI_OPEN = 0
4986 19:22:58.325278 CA_SEMI_OPEN = 0
4987 19:22:58.328294 CA_FULL_RATE = 0
4988 19:22:58.331600 DQ_CKDIV4_EN = 1
4989 19:22:58.335190 CA_CKDIV4_EN = 1
4990 19:22:58.338500 CA_PREDIV_EN = 0
4991 19:22:58.341903 PH8_DLY = 0
4992 19:22:58.341996 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4993 19:22:58.345300 DQ_AAMCK_DIV = 4
4994 19:22:58.348375 CA_AAMCK_DIV = 4
4995 19:22:58.352112 CA_ADMCK_DIV = 4
4996 19:22:58.355145 DQ_TRACK_CA_EN = 0
4997 19:22:58.358256 CA_PICK = 933
4998 19:22:58.358395 CA_MCKIO = 933
4999 19:22:58.361923 MCKIO_SEMI = 0
5000 19:22:58.364836 PLL_FREQ = 3732
5001 19:22:58.368370 DQ_UI_PI_RATIO = 32
5002 19:22:58.371988 CA_UI_PI_RATIO = 0
5003 19:22:58.374970 ===================================
5004 19:22:58.378162 ===================================
5005 19:22:58.381795 memory_type:LPDDR4
5006 19:22:58.381896 GP_NUM : 10
5007 19:22:58.384825 SRAM_EN : 1
5008 19:22:58.384912 MD32_EN : 0
5009 19:22:58.388517 ===================================
5010 19:22:58.391414 [ANA_INIT] >>>>>>>>>>>>>>
5011 19:22:58.394952 <<<<<< [CONFIGURE PHASE]: ANA_TX
5012 19:22:58.398521 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5013 19:22:58.401466 ===================================
5014 19:22:58.404838 data_rate = 1866,PCW = 0X8f00
5015 19:22:58.408322 ===================================
5016 19:22:58.412039 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5017 19:22:58.414974 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5018 19:22:58.421557 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5019 19:22:58.425141 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5020 19:22:58.428316 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5021 19:22:58.435070 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5022 19:22:58.435196 [ANA_INIT] flow start
5023 19:22:58.438693 [ANA_INIT] PLL >>>>>>>>
5024 19:22:58.438802 [ANA_INIT] PLL <<<<<<<<
5025 19:22:58.441770 [ANA_INIT] MIDPI >>>>>>>>
5026 19:22:58.445203 [ANA_INIT] MIDPI <<<<<<<<
5027 19:22:58.448132 [ANA_INIT] DLL >>>>>>>>
5028 19:22:58.448218 [ANA_INIT] flow end
5029 19:22:58.451619 ============ LP4 DIFF to SE enter ============
5030 19:22:58.458352 ============ LP4 DIFF to SE exit ============
5031 19:22:58.458492 [ANA_INIT] <<<<<<<<<<<<<
5032 19:22:58.462002 [Flow] Enable top DCM control >>>>>
5033 19:22:58.464728 [Flow] Enable top DCM control <<<<<
5034 19:22:58.468325 Enable DLL master slave shuffle
5035 19:22:58.474787 ==============================================================
5036 19:22:58.474896 Gating Mode config
5037 19:22:58.482093 ==============================================================
5038 19:22:58.485166 Config description:
5039 19:22:58.491950 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5040 19:22:58.498544 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5041 19:22:58.504923 SELPH_MODE 0: By rank 1: By Phase
5042 19:22:58.511930 ==============================================================
5043 19:22:58.512071 GAT_TRACK_EN = 1
5044 19:22:58.515289 RX_GATING_MODE = 2
5045 19:22:58.518156 RX_GATING_TRACK_MODE = 2
5046 19:22:58.521838 SELPH_MODE = 1
5047 19:22:58.525234 PICG_EARLY_EN = 1
5048 19:22:58.528258 VALID_LAT_VALUE = 1
5049 19:22:58.535007 ==============================================================
5050 19:22:58.538642 Enter into Gating configuration >>>>
5051 19:22:58.541780 Exit from Gating configuration <<<<
5052 19:22:58.544811 Enter into DVFS_PRE_config >>>>>
5053 19:22:58.555198 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5054 19:22:58.558376 Exit from DVFS_PRE_config <<<<<
5055 19:22:58.562007 Enter into PICG configuration >>>>
5056 19:22:58.565542 Exit from PICG configuration <<<<
5057 19:22:58.568424 [RX_INPUT] configuration >>>>>
5058 19:22:58.568512 [RX_INPUT] configuration <<<<<
5059 19:22:58.575096 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5060 19:22:58.582177 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5061 19:22:58.585557 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5062 19:22:58.592017 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5063 19:22:58.598195 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5064 19:22:58.605566 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5065 19:22:58.608450 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5066 19:22:58.611933 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5067 19:22:58.618425 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5068 19:22:58.621743 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5069 19:22:58.624890 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5070 19:22:58.628561 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5071 19:22:58.631603 ===================================
5072 19:22:58.634967 LPDDR4 DRAM CONFIGURATION
5073 19:22:58.638627 ===================================
5074 19:22:58.641616 EX_ROW_EN[0] = 0x0
5075 19:22:58.641711 EX_ROW_EN[1] = 0x0
5076 19:22:58.645460 LP4Y_EN = 0x0
5077 19:22:58.645570 WORK_FSP = 0x0
5078 19:22:58.648532 WL = 0x3
5079 19:22:58.648645 RL = 0x3
5080 19:22:58.651599 BL = 0x2
5081 19:22:58.651699 RPST = 0x0
5082 19:22:58.655318 RD_PRE = 0x0
5083 19:22:58.655425 WR_PRE = 0x1
5084 19:22:58.658284 WR_PST = 0x0
5085 19:22:58.658393 DBI_WR = 0x0
5086 19:22:58.661873 DBI_RD = 0x0
5087 19:22:58.665477 OTF = 0x1
5088 19:22:58.665571 ===================================
5089 19:22:58.671674 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5090 19:22:58.675256 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5091 19:22:58.678805 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5092 19:22:58.681824 ===================================
5093 19:22:58.685459 LPDDR4 DRAM CONFIGURATION
5094 19:22:58.688486 ===================================
5095 19:22:58.691922 EX_ROW_EN[0] = 0x10
5096 19:22:58.692017 EX_ROW_EN[1] = 0x0
5097 19:22:58.695321 LP4Y_EN = 0x0
5098 19:22:58.695400 WORK_FSP = 0x0
5099 19:22:58.698884 WL = 0x3
5100 19:22:58.698962 RL = 0x3
5101 19:22:58.702036 BL = 0x2
5102 19:22:58.702125 RPST = 0x0
5103 19:22:58.705565 RD_PRE = 0x0
5104 19:22:58.705665 WR_PRE = 0x1
5105 19:22:58.708786 WR_PST = 0x0
5106 19:22:58.708871 DBI_WR = 0x0
5107 19:22:58.712139 DBI_RD = 0x0
5108 19:22:58.712229 OTF = 0x1
5109 19:22:58.715373 ===================================
5110 19:22:58.721815 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5111 19:22:58.726647 nWR fixed to 30
5112 19:22:58.730048 [ModeRegInit_LP4] CH0 RK0
5113 19:22:58.730180 [ModeRegInit_LP4] CH0 RK1
5114 19:22:58.733135 [ModeRegInit_LP4] CH1 RK0
5115 19:22:58.736862 [ModeRegInit_LP4] CH1 RK1
5116 19:22:58.736955 match AC timing 9
5117 19:22:58.743345 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5118 19:22:58.746484 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5119 19:22:58.750154 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5120 19:22:58.756401 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5121 19:22:58.760065 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5122 19:22:58.760192 ==
5123 19:22:58.763076 Dram Type= 6, Freq= 0, CH_0, rank 0
5124 19:22:58.766228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5125 19:22:58.766326 ==
5126 19:22:58.772862 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5127 19:22:58.779757 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5128 19:22:58.783280 [CA 0] Center 38 (8~69) winsize 62
5129 19:22:58.786712 [CA 1] Center 38 (8~68) winsize 61
5130 19:22:58.789802 [CA 2] Center 35 (5~66) winsize 62
5131 19:22:58.792962 [CA 3] Center 34 (4~65) winsize 62
5132 19:22:58.796690 [CA 4] Center 34 (4~65) winsize 62
5133 19:22:58.799828 [CA 5] Center 34 (4~64) winsize 61
5134 19:22:58.799912
5135 19:22:58.803390 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5136 19:22:58.803472
5137 19:22:58.806491 [CATrainingPosCal] consider 1 rank data
5138 19:22:58.809890 u2DelayCellTimex100 = 270/100 ps
5139 19:22:58.813372 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5140 19:22:58.817030 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5141 19:22:58.819971 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5142 19:22:58.823306 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5143 19:22:58.826428 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5144 19:22:58.829691 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5145 19:22:58.829791
5146 19:22:58.833008 CA PerBit enable=1, Macro0, CA PI delay=34
5147 19:22:58.836662
5148 19:22:58.836789 [CBTSetCACLKResult] CA Dly = 34
5149 19:22:58.839935 CS Dly: 6 (0~37)
5150 19:22:58.840042 ==
5151 19:22:58.843063 Dram Type= 6, Freq= 0, CH_0, rank 1
5152 19:22:58.846580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5153 19:22:58.846722 ==
5154 19:22:58.853441 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5155 19:22:58.859906 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5156 19:22:58.863038 [CA 0] Center 38 (8~69) winsize 62
5157 19:22:58.866594 [CA 1] Center 38 (8~69) winsize 62
5158 19:22:58.869791 [CA 2] Center 35 (5~66) winsize 62
5159 19:22:58.873293 [CA 3] Center 35 (4~66) winsize 63
5160 19:22:58.876336 [CA 4] Center 34 (3~65) winsize 63
5161 19:22:58.880090 [CA 5] Center 33 (3~64) winsize 62
5162 19:22:58.880187
5163 19:22:58.883054 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5164 19:22:58.883155
5165 19:22:58.886714 [CATrainingPosCal] consider 2 rank data
5166 19:22:58.890251 u2DelayCellTimex100 = 270/100 ps
5167 19:22:58.893316 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5168 19:22:58.896414 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5169 19:22:58.900132 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5170 19:22:58.903190 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5171 19:22:58.906973 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5172 19:22:58.910082 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5173 19:22:58.910168
5174 19:22:58.913122 CA PerBit enable=1, Macro0, CA PI delay=34
5175 19:22:58.916587
5176 19:22:58.916673 [CBTSetCACLKResult] CA Dly = 34
5177 19:22:58.919957 CS Dly: 7 (0~39)
5178 19:22:58.920039
5179 19:22:58.923607 ----->DramcWriteLeveling(PI) begin...
5180 19:22:58.923712 ==
5181 19:22:58.926554 Dram Type= 6, Freq= 0, CH_0, rank 0
5182 19:22:58.930169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5183 19:22:58.930269 ==
5184 19:22:58.933194 Write leveling (Byte 0): 30 => 30
5185 19:22:58.936785 Write leveling (Byte 1): 28 => 28
5186 19:22:58.940121 DramcWriteLeveling(PI) end<-----
5187 19:22:58.940205
5188 19:22:58.940269 ==
5189 19:22:58.942908 Dram Type= 6, Freq= 0, CH_0, rank 0
5190 19:22:58.946452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5191 19:22:58.946539 ==
5192 19:22:58.949847 [Gating] SW mode calibration
5193 19:22:58.956220 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5194 19:22:58.963126 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5195 19:22:58.966792 0 14 0 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
5196 19:22:58.973273 0 14 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5197 19:22:58.976258 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5198 19:22:58.979943 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5199 19:22:58.986675 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5200 19:22:58.989840 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5201 19:22:58.993388 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5202 19:22:58.996503 0 14 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5203 19:22:59.003161 0 15 0 | B1->B0 | 3232 2e2e | 1 0 | (1 0) (0 0)
5204 19:22:59.006959 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
5205 19:22:59.009989 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5206 19:22:59.016684 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5207 19:22:59.019952 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5208 19:22:59.023555 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5209 19:22:59.030366 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5210 19:22:59.033428 0 15 28 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
5211 19:22:59.037144 1 0 0 | B1->B0 | 3333 3e3e | 0 0 | (0 0) (0 0)
5212 19:22:59.043893 1 0 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5213 19:22:59.046631 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5214 19:22:59.050228 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5215 19:22:59.056836 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5216 19:22:59.060297 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5217 19:22:59.063226 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5218 19:22:59.066893 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5219 19:22:59.073595 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5220 19:22:59.076910 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5221 19:22:59.080345 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5222 19:22:59.086670 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5223 19:22:59.090386 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5224 19:22:59.093431 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5225 19:22:59.099912 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5226 19:22:59.103535 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5227 19:22:59.106518 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5228 19:22:59.113406 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5229 19:22:59.116500 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5230 19:22:59.120148 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5231 19:22:59.126763 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5232 19:22:59.130000 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5233 19:22:59.133454 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5234 19:22:59.140471 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5235 19:22:59.143477 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5236 19:22:59.147031 Total UI for P1: 0, mck2ui 16
5237 19:22:59.150757 best dqsien dly found for B0: ( 1, 2, 30)
5238 19:22:59.153986 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5239 19:22:59.157035 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5240 19:22:59.160043 Total UI for P1: 0, mck2ui 16
5241 19:22:59.163676 best dqsien dly found for B1: ( 1, 3, 2)
5242 19:22:59.167266 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5243 19:22:59.170169 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5244 19:22:59.170262
5245 19:22:59.177204 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5246 19:22:59.180316 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5247 19:22:59.180417 [Gating] SW calibration Done
5248 19:22:59.183744 ==
5249 19:22:59.187216 Dram Type= 6, Freq= 0, CH_0, rank 0
5250 19:22:59.190200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5251 19:22:59.190300 ==
5252 19:22:59.190372 RX Vref Scan: 0
5253 19:22:59.190436
5254 19:22:59.193775 RX Vref 0 -> 0, step: 1
5255 19:22:59.193900
5256 19:22:59.197028 RX Delay -80 -> 252, step: 8
5257 19:22:59.200286 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5258 19:22:59.203587 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5259 19:22:59.207263 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5260 19:22:59.213950 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5261 19:22:59.217012 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5262 19:22:59.220136 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5263 19:22:59.223669 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5264 19:22:59.226865 iDelay=208, Bit 7, Center 107 (16 ~ 199) 184
5265 19:22:59.230580 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5266 19:22:59.237184 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5267 19:22:59.240119 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5268 19:22:59.243673 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5269 19:22:59.246884 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5270 19:22:59.250397 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5271 19:22:59.257251 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5272 19:22:59.260135 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5273 19:22:59.260261 ==
5274 19:22:59.263150 Dram Type= 6, Freq= 0, CH_0, rank 0
5275 19:22:59.266674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5276 19:22:59.266782 ==
5277 19:22:59.266872 DQS Delay:
5278 19:22:59.270084 DQS0 = 0, DQS1 = 0
5279 19:22:59.270178 DQM Delay:
5280 19:22:59.273567 DQM0 = 99, DQM1 = 87
5281 19:22:59.273665 DQ Delay:
5282 19:22:59.277056 DQ0 =99, DQ1 =103, DQ2 =95, DQ3 =95
5283 19:22:59.279961 DQ4 =103, DQ5 =83, DQ6 =111, DQ7 =107
5284 19:22:59.283041 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5285 19:22:59.286645 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5286 19:22:59.286776
5287 19:22:59.286876
5288 19:22:59.286969 ==
5289 19:22:59.290008 Dram Type= 6, Freq= 0, CH_0, rank 0
5290 19:22:59.296759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5291 19:22:59.296907 ==
5292 19:22:59.297012
5293 19:22:59.297121
5294 19:22:59.297232 TX Vref Scan disable
5295 19:22:59.300344 == TX Byte 0 ==
5296 19:22:59.303462 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5297 19:22:59.306871 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5298 19:22:59.310417 == TX Byte 1 ==
5299 19:22:59.313288 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5300 19:22:59.316780 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5301 19:22:59.319919 ==
5302 19:22:59.323701 Dram Type= 6, Freq= 0, CH_0, rank 0
5303 19:22:59.327109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5304 19:22:59.327209 ==
5305 19:22:59.327303
5306 19:22:59.327391
5307 19:22:59.330116 TX Vref Scan disable
5308 19:22:59.330199 == TX Byte 0 ==
5309 19:22:59.337091 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5310 19:22:59.340161 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5311 19:22:59.340262 == TX Byte 1 ==
5312 19:22:59.346900 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5313 19:22:59.350296 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5314 19:22:59.350409
5315 19:22:59.350501 [DATLAT]
5316 19:22:59.353628 Freq=933, CH0 RK0
5317 19:22:59.353725
5318 19:22:59.353816 DATLAT Default: 0xd
5319 19:22:59.356963 0, 0xFFFF, sum = 0
5320 19:22:59.357101 1, 0xFFFF, sum = 0
5321 19:22:59.360004 2, 0xFFFF, sum = 0
5322 19:22:59.360097 3, 0xFFFF, sum = 0
5323 19:22:59.363658 4, 0xFFFF, sum = 0
5324 19:22:59.363759 5, 0xFFFF, sum = 0
5325 19:22:59.367169 6, 0xFFFF, sum = 0
5326 19:22:59.367286 7, 0xFFFF, sum = 0
5327 19:22:59.370516 8, 0xFFFF, sum = 0
5328 19:22:59.370613 9, 0xFFFF, sum = 0
5329 19:22:59.373430 10, 0x0, sum = 1
5330 19:22:59.373550 11, 0x0, sum = 2
5331 19:22:59.376938 12, 0x0, sum = 3
5332 19:22:59.377031 13, 0x0, sum = 4
5333 19:22:59.380330 best_step = 11
5334 19:22:59.380429
5335 19:22:59.380524 ==
5336 19:22:59.383848 Dram Type= 6, Freq= 0, CH_0, rank 0
5337 19:22:59.386895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5338 19:22:59.386991 ==
5339 19:22:59.390407 RX Vref Scan: 1
5340 19:22:59.390507
5341 19:22:59.390600 RX Vref 0 -> 0, step: 1
5342 19:22:59.390684
5343 19:22:59.393480 RX Delay -61 -> 252, step: 4
5344 19:22:59.393571
5345 19:22:59.396894 Set Vref, RX VrefLevel [Byte0]: 51
5346 19:22:59.400484 [Byte1]: 50
5347 19:22:59.404217
5348 19:22:59.404307 Final RX Vref Byte 0 = 51 to rank0
5349 19:22:59.407333 Final RX Vref Byte 1 = 50 to rank0
5350 19:22:59.410410 Final RX Vref Byte 0 = 51 to rank1
5351 19:22:59.413946 Final RX Vref Byte 1 = 50 to rank1==
5352 19:22:59.417529 Dram Type= 6, Freq= 0, CH_0, rank 0
5353 19:22:59.424032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5354 19:22:59.424138 ==
5355 19:22:59.424232 DQS Delay:
5356 19:22:59.424318 DQS0 = 0, DQS1 = 0
5357 19:22:59.427667 DQM Delay:
5358 19:22:59.427762 DQM0 = 97, DQM1 = 87
5359 19:22:59.430873 DQ Delay:
5360 19:22:59.433975 DQ0 =98, DQ1 =98, DQ2 =92, DQ3 =96
5361 19:22:59.437756 DQ4 =98, DQ5 =86, DQ6 =104, DQ7 =104
5362 19:22:59.440894 DQ8 =76, DQ9 =74, DQ10 =88, DQ11 =82
5363 19:22:59.444042 DQ12 =96, DQ13 =90, DQ14 =96, DQ15 =94
5364 19:22:59.444137
5365 19:22:59.444208
5366 19:22:59.450812 [DQSOSCAuto] RK0, (LSB)MR18= 0x1803, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 414 ps
5367 19:22:59.454025 CH0 RK0: MR19=505, MR18=1803
5368 19:22:59.461120 CH0_RK0: MR19=0x505, MR18=0x1803, DQSOSC=414, MR23=63, INC=63, DEC=42
5369 19:22:59.461263
5370 19:22:59.464028 ----->DramcWriteLeveling(PI) begin...
5371 19:22:59.464108 ==
5372 19:22:59.467715 Dram Type= 6, Freq= 0, CH_0, rank 1
5373 19:22:59.471327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5374 19:22:59.471423 ==
5375 19:22:59.474168 Write leveling (Byte 0): 30 => 30
5376 19:22:59.477485 Write leveling (Byte 1): 30 => 30
5377 19:22:59.480960 DramcWriteLeveling(PI) end<-----
5378 19:22:59.481045
5379 19:22:59.481109 ==
5380 19:22:59.484477 Dram Type= 6, Freq= 0, CH_0, rank 1
5381 19:22:59.487243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5382 19:22:59.487331 ==
5383 19:22:59.490660 [Gating] SW mode calibration
5384 19:22:59.497372 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5385 19:22:59.504189 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5386 19:22:59.507950 0 14 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
5387 19:22:59.510884 0 14 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5388 19:22:59.517813 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5389 19:22:59.520829 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5390 19:22:59.524488 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5391 19:22:59.531063 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5392 19:22:59.533921 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5393 19:22:59.537681 0 14 28 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
5394 19:22:59.544181 0 15 0 | B1->B0 | 2c2c 2323 | 1 0 | (1 1) (1 0)
5395 19:22:59.547822 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5396 19:22:59.550805 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5397 19:22:59.557293 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5398 19:22:59.561311 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5399 19:22:59.564301 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5400 19:22:59.567881 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5401 19:22:59.574661 0 15 28 | B1->B0 | 2c2c 3939 | 0 0 | (0 0) (1 1)
5402 19:22:59.578033 1 0 0 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
5403 19:22:59.580731 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5404 19:22:59.587647 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5405 19:22:59.590894 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5406 19:22:59.594287 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5407 19:22:59.600843 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5408 19:22:59.604584 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5409 19:22:59.607727 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5410 19:22:59.614271 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5411 19:22:59.618049 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5412 19:22:59.621070 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5413 19:22:59.628076 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5414 19:22:59.631207 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5415 19:22:59.634104 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5416 19:22:59.640847 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5417 19:22:59.644257 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5418 19:22:59.647565 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5419 19:22:59.650975 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5420 19:22:59.657595 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5421 19:22:59.661395 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5422 19:22:59.664474 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5423 19:22:59.671365 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5424 19:22:59.674184 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5425 19:22:59.677768 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5426 19:22:59.680644 Total UI for P1: 0, mck2ui 16
5427 19:22:59.684524 best dqsien dly found for B0: ( 1, 2, 26)
5428 19:22:59.690809 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5429 19:22:59.694339 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5430 19:22:59.697313 Total UI for P1: 0, mck2ui 16
5431 19:22:59.701102 best dqsien dly found for B1: ( 1, 2, 30)
5432 19:22:59.704068 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5433 19:22:59.707840 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5434 19:22:59.707981
5435 19:22:59.711026 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5436 19:22:59.714027 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5437 19:22:59.717679 [Gating] SW calibration Done
5438 19:22:59.717778 ==
5439 19:22:59.720785 Dram Type= 6, Freq= 0, CH_0, rank 1
5440 19:22:59.724436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5441 19:22:59.727474 ==
5442 19:22:59.727567 RX Vref Scan: 0
5443 19:22:59.727656
5444 19:22:59.731072 RX Vref 0 -> 0, step: 1
5445 19:22:59.731165
5446 19:22:59.731252 RX Delay -80 -> 252, step: 8
5447 19:22:59.737710 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5448 19:22:59.741280 iDelay=200, Bit 1, Center 95 (0 ~ 191) 192
5449 19:22:59.744436 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5450 19:22:59.747918 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5451 19:22:59.751555 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5452 19:22:59.754747 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5453 19:22:59.761352 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5454 19:22:59.764652 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5455 19:22:59.767746 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5456 19:22:59.771379 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5457 19:22:59.774528 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5458 19:22:59.778179 iDelay=200, Bit 11, Center 75 (-16 ~ 167) 184
5459 19:22:59.784366 iDelay=200, Bit 12, Center 91 (0 ~ 183) 184
5460 19:22:59.788047 iDelay=200, Bit 13, Center 91 (0 ~ 183) 184
5461 19:22:59.791451 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5462 19:22:59.794819 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5463 19:22:59.794916 ==
5464 19:22:59.797804 Dram Type= 6, Freq= 0, CH_0, rank 1
5465 19:22:59.801090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5466 19:22:59.804646 ==
5467 19:22:59.804746 DQS Delay:
5468 19:22:59.804840 DQS0 = 0, DQS1 = 0
5469 19:22:59.808091 DQM Delay:
5470 19:22:59.808187 DQM0 = 96, DQM1 = 87
5471 19:22:59.808290 DQ Delay:
5472 19:22:59.811292 DQ0 =95, DQ1 =95, DQ2 =95, DQ3 =95
5473 19:22:59.814747 DQ4 =95, DQ5 =87, DQ6 =103, DQ7 =103
5474 19:22:59.817873 DQ8 =83, DQ9 =79, DQ10 =87, DQ11 =75
5475 19:22:59.821449 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =95
5476 19:22:59.821545
5477 19:22:59.824873
5478 19:22:59.824969 ==
5479 19:22:59.827690 Dram Type= 6, Freq= 0, CH_0, rank 1
5480 19:22:59.831310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5481 19:22:59.831403 ==
5482 19:22:59.831496
5483 19:22:59.831577
5484 19:22:59.834446 TX Vref Scan disable
5485 19:22:59.834535 == TX Byte 0 ==
5486 19:22:59.841172 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5487 19:22:59.844780 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5488 19:22:59.844877 == TX Byte 1 ==
5489 19:22:59.851338 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5490 19:22:59.854398 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5491 19:22:59.854502 ==
5492 19:22:59.858102 Dram Type= 6, Freq= 0, CH_0, rank 1
5493 19:22:59.861144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5494 19:22:59.861262 ==
5495 19:22:59.861355
5496 19:22:59.861436
5497 19:22:59.864797 TX Vref Scan disable
5498 19:22:59.867811 == TX Byte 0 ==
5499 19:22:59.870921 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5500 19:22:59.874373 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5501 19:22:59.877608 == TX Byte 1 ==
5502 19:22:59.880830 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5503 19:22:59.884612 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5504 19:22:59.884711
5505 19:22:59.887683 [DATLAT]
5506 19:22:59.887774 Freq=933, CH0 RK1
5507 19:22:59.887867
5508 19:22:59.891294 DATLAT Default: 0xb
5509 19:22:59.891382 0, 0xFFFF, sum = 0
5510 19:22:59.894211 1, 0xFFFF, sum = 0
5511 19:22:59.894300 2, 0xFFFF, sum = 0
5512 19:22:59.897653 3, 0xFFFF, sum = 0
5513 19:22:59.897755 4, 0xFFFF, sum = 0
5514 19:22:59.901103 5, 0xFFFF, sum = 0
5515 19:22:59.901223 6, 0xFFFF, sum = 0
5516 19:22:59.904821 7, 0xFFFF, sum = 0
5517 19:22:59.904948 8, 0xFFFF, sum = 0
5518 19:22:59.908018 9, 0xFFFF, sum = 0
5519 19:22:59.908141 10, 0x0, sum = 1
5520 19:22:59.911200 11, 0x0, sum = 2
5521 19:22:59.911280 12, 0x0, sum = 3
5522 19:22:59.914735 13, 0x0, sum = 4
5523 19:22:59.914851 best_step = 11
5524 19:22:59.914945
5525 19:22:59.915034 ==
5526 19:22:59.918033 Dram Type= 6, Freq= 0, CH_0, rank 1
5527 19:22:59.921502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5528 19:22:59.921596 ==
5529 19:22:59.924450 RX Vref Scan: 0
5530 19:22:59.924536
5531 19:22:59.927732 RX Vref 0 -> 0, step: 1
5532 19:22:59.927821
5533 19:22:59.927888 RX Delay -61 -> 252, step: 4
5534 19:22:59.935772 iDelay=199, Bit 0, Center 96 (3 ~ 190) 188
5535 19:22:59.939282 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5536 19:22:59.942245 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5537 19:22:59.945916 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5538 19:22:59.949578 iDelay=199, Bit 4, Center 96 (7 ~ 186) 180
5539 19:22:59.952469 iDelay=199, Bit 5, Center 84 (-9 ~ 178) 188
5540 19:22:59.959643 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5541 19:22:59.962905 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5542 19:22:59.965986 iDelay=199, Bit 8, Center 78 (-9 ~ 166) 176
5543 19:22:59.969642 iDelay=199, Bit 9, Center 80 (-9 ~ 170) 180
5544 19:22:59.972732 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5545 19:22:59.976267 iDelay=199, Bit 11, Center 80 (-5 ~ 166) 172
5546 19:22:59.983048 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5547 19:22:59.985980 iDelay=199, Bit 13, Center 92 (3 ~ 182) 180
5548 19:22:59.989102 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5549 19:22:59.992928 iDelay=199, Bit 15, Center 94 (7 ~ 182) 176
5550 19:22:59.993025 ==
5551 19:22:59.995835 Dram Type= 6, Freq= 0, CH_0, rank 1
5552 19:22:59.999337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5553 19:23:00.002316 ==
5554 19:23:00.002398 DQS Delay:
5555 19:23:00.002462 DQS0 = 0, DQS1 = 0
5556 19:23:00.005840 DQM Delay:
5557 19:23:00.005922 DQM0 = 95, DQM1 = 87
5558 19:23:00.009163 DQ Delay:
5559 19:23:00.009275 DQ0 =96, DQ1 =96, DQ2 =92, DQ3 =94
5560 19:23:00.012553 DQ4 =96, DQ5 =84, DQ6 =104, DQ7 =102
5561 19:23:00.016073 DQ8 =78, DQ9 =80, DQ10 =88, DQ11 =80
5562 19:23:00.019018 DQ12 =92, DQ13 =92, DQ14 =98, DQ15 =94
5563 19:23:00.022601
5564 19:23:00.022696
5565 19:23:00.029258 [DQSOSCAuto] RK1, (LSB)MR18= 0x200d, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 411 ps
5566 19:23:00.032946 CH0 RK1: MR19=505, MR18=200D
5567 19:23:00.039196 CH0_RK1: MR19=0x505, MR18=0x200D, DQSOSC=411, MR23=63, INC=64, DEC=42
5568 19:23:00.039324 [RxdqsGatingPostProcess] freq 933
5569 19:23:00.046215 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5570 19:23:00.049523 best DQS0 dly(2T, 0.5T) = (0, 10)
5571 19:23:00.052380 best DQS1 dly(2T, 0.5T) = (0, 11)
5572 19:23:00.056308 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5573 19:23:00.059253 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5574 19:23:00.062955 best DQS0 dly(2T, 0.5T) = (0, 10)
5575 19:23:00.065744 best DQS1 dly(2T, 0.5T) = (0, 10)
5576 19:23:00.069498 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5577 19:23:00.072473 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5578 19:23:00.076289 Pre-setting of DQS Precalculation
5579 19:23:00.079447 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5580 19:23:00.079537 ==
5581 19:23:00.082531 Dram Type= 6, Freq= 0, CH_1, rank 0
5582 19:23:00.086148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5583 19:23:00.086249 ==
5584 19:23:00.092784 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5585 19:23:00.099253 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5586 19:23:00.102478 [CA 0] Center 36 (6~67) winsize 62
5587 19:23:00.106174 [CA 1] Center 36 (6~67) winsize 62
5588 19:23:00.109441 [CA 2] Center 33 (3~64) winsize 62
5589 19:23:00.112985 [CA 3] Center 33 (3~64) winsize 62
5590 19:23:00.115822 [CA 4] Center 33 (3~64) winsize 62
5591 19:23:00.119306 [CA 5] Center 33 (3~63) winsize 61
5592 19:23:00.119394
5593 19:23:00.122736 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5594 19:23:00.122827
5595 19:23:00.126217 [CATrainingPosCal] consider 1 rank data
5596 19:23:00.129362 u2DelayCellTimex100 = 270/100 ps
5597 19:23:00.132419 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5598 19:23:00.136133 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5599 19:23:00.139202 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
5600 19:23:00.142873 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5601 19:23:00.145857 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5602 19:23:00.152551 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5603 19:23:00.152672
5604 19:23:00.155750 CA PerBit enable=1, Macro0, CA PI delay=33
5605 19:23:00.155849
5606 19:23:00.159409 [CBTSetCACLKResult] CA Dly = 33
5607 19:23:00.159493 CS Dly: 4 (0~35)
5608 19:23:00.159559 ==
5609 19:23:00.162858 Dram Type= 6, Freq= 0, CH_1, rank 1
5610 19:23:00.165887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5611 19:23:00.165986 ==
5612 19:23:00.173160 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5613 19:23:00.179335 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5614 19:23:00.183030 [CA 0] Center 36 (6~67) winsize 62
5615 19:23:00.186195 [CA 1] Center 36 (6~67) winsize 62
5616 19:23:00.189283 [CA 2] Center 33 (3~64) winsize 62
5617 19:23:00.193045 [CA 3] Center 33 (3~64) winsize 62
5618 19:23:00.195913 [CA 4] Center 34 (4~65) winsize 62
5619 19:23:00.199683 [CA 5] Center 33 (3~63) winsize 61
5620 19:23:00.199773
5621 19:23:00.202595 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5622 19:23:00.202678
5623 19:23:00.206341 [CATrainingPosCal] consider 2 rank data
5624 19:23:00.209401 u2DelayCellTimex100 = 270/100 ps
5625 19:23:00.212694 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5626 19:23:00.216164 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5627 19:23:00.219353 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
5628 19:23:00.222869 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5629 19:23:00.226286 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5630 19:23:00.229268 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5631 19:23:00.229360
5632 19:23:00.236075 CA PerBit enable=1, Macro0, CA PI delay=33
5633 19:23:00.236197
5634 19:23:00.239953 [CBTSetCACLKResult] CA Dly = 33
5635 19:23:00.240052 CS Dly: 5 (0~38)
5636 19:23:00.240121
5637 19:23:00.242638 ----->DramcWriteLeveling(PI) begin...
5638 19:23:00.242729 ==
5639 19:23:00.246232 Dram Type= 6, Freq= 0, CH_1, rank 0
5640 19:23:00.249899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5641 19:23:00.250000 ==
5642 19:23:00.252946 Write leveling (Byte 0): 24 => 24
5643 19:23:00.256340 Write leveling (Byte 1): 26 => 26
5644 19:23:00.259741 DramcWriteLeveling(PI) end<-----
5645 19:23:00.259855
5646 19:23:00.259965 ==
5647 19:23:00.263040 Dram Type= 6, Freq= 0, CH_1, rank 0
5648 19:23:00.266213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5649 19:23:00.269651 ==
5650 19:23:00.269744 [Gating] SW mode calibration
5651 19:23:00.279803 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5652 19:23:00.282819 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5653 19:23:00.286590 0 14 0 | B1->B0 | 3131 3333 | 1 1 | (1 1) (0 0)
5654 19:23:00.292825 0 14 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5655 19:23:00.296402 0 14 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5656 19:23:00.299426 0 14 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5657 19:23:00.306231 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5658 19:23:00.309379 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5659 19:23:00.313061 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
5660 19:23:00.319535 0 14 28 | B1->B0 | 302f 3232 | 1 0 | (0 1) (0 1)
5661 19:23:00.323245 0 15 0 | B1->B0 | 2525 2323 | 0 0 | (1 0) (1 0)
5662 19:23:00.326248 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5663 19:23:00.333126 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5664 19:23:00.336277 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5665 19:23:00.339471 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5666 19:23:00.343138 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5667 19:23:00.349938 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5668 19:23:00.353047 0 15 28 | B1->B0 | 2e2e 2727 | 0 0 | (1 1) (0 0)
5669 19:23:00.356471 1 0 0 | B1->B0 | 4545 4141 | 0 0 | (0 0) (0 0)
5670 19:23:00.363222 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5671 19:23:00.366570 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5672 19:23:00.369604 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5673 19:23:00.376152 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5674 19:23:00.379432 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5675 19:23:00.382834 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5676 19:23:00.390184 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5677 19:23:00.393190 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5678 19:23:00.396289 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5679 19:23:00.403191 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5680 19:23:00.406177 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5681 19:23:00.409974 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5682 19:23:00.416635 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5683 19:23:00.419668 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5684 19:23:00.423471 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5685 19:23:00.426704 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5686 19:23:00.433430 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5687 19:23:00.436579 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5688 19:23:00.439947 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5689 19:23:00.446370 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5690 19:23:00.450062 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5691 19:23:00.453110 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5692 19:23:00.459674 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5693 19:23:00.463493 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5694 19:23:00.466512 Total UI for P1: 0, mck2ui 16
5695 19:23:00.470434 best dqsien dly found for B0: ( 1, 2, 26)
5696 19:23:00.473060 Total UI for P1: 0, mck2ui 16
5697 19:23:00.476495 best dqsien dly found for B1: ( 1, 2, 28)
5698 19:23:00.479756 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5699 19:23:00.483485 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5700 19:23:00.483577
5701 19:23:00.486387 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5702 19:23:00.489894 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5703 19:23:00.493184 [Gating] SW calibration Done
5704 19:23:00.493290 ==
5705 19:23:00.496282 Dram Type= 6, Freq= 0, CH_1, rank 0
5706 19:23:00.499573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5707 19:23:00.503057 ==
5708 19:23:00.503186 RX Vref Scan: 0
5709 19:23:00.503289
5710 19:23:00.506966 RX Vref 0 -> 0, step: 1
5711 19:23:00.507085
5712 19:23:00.507185 RX Delay -80 -> 252, step: 8
5713 19:23:00.513518 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5714 19:23:00.516868 iDelay=200, Bit 1, Center 87 (-8 ~ 183) 192
5715 19:23:00.520194 iDelay=200, Bit 2, Center 79 (-16 ~ 175) 192
5716 19:23:00.523224 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5717 19:23:00.527060 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5718 19:23:00.530007 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5719 19:23:00.536692 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5720 19:23:00.540365 iDelay=200, Bit 7, Center 91 (-8 ~ 191) 200
5721 19:23:00.543344 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5722 19:23:00.546751 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5723 19:23:00.550408 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5724 19:23:00.556991 iDelay=200, Bit 11, Center 83 (-16 ~ 183) 200
5725 19:23:00.560039 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5726 19:23:00.563570 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5727 19:23:00.566625 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5728 19:23:00.570246 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5729 19:23:00.570334 ==
5730 19:23:00.573508 Dram Type= 6, Freq= 0, CH_1, rank 0
5731 19:23:00.577107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5732 19:23:00.580136 ==
5733 19:23:00.580245 DQS Delay:
5734 19:23:00.580346 DQS0 = 0, DQS1 = 0
5735 19:23:00.583326 DQM Delay:
5736 19:23:00.583427 DQM0 = 94, DQM1 = 88
5737 19:23:00.586800 DQ Delay:
5738 19:23:00.590340 DQ0 =99, DQ1 =87, DQ2 =79, DQ3 =95
5739 19:23:00.590453 DQ4 =95, DQ5 =103, DQ6 =107, DQ7 =91
5740 19:23:00.593876 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5741 19:23:00.599880 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5742 19:23:00.599983
5743 19:23:00.600050
5744 19:23:00.600111 ==
5745 19:23:00.603604 Dram Type= 6, Freq= 0, CH_1, rank 0
5746 19:23:00.606644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5747 19:23:00.606735 ==
5748 19:23:00.606819
5749 19:23:00.606883
5750 19:23:00.610486 TX Vref Scan disable
5751 19:23:00.610585 == TX Byte 0 ==
5752 19:23:00.617034 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5753 19:23:00.620200 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5754 19:23:00.620326 == TX Byte 1 ==
5755 19:23:00.626841 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5756 19:23:00.630412 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5757 19:23:00.630536 ==
5758 19:23:00.633363 Dram Type= 6, Freq= 0, CH_1, rank 0
5759 19:23:00.637161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5760 19:23:00.637285 ==
5761 19:23:00.637381
5762 19:23:00.637464
5763 19:23:00.640262 TX Vref Scan disable
5764 19:23:00.643714 == TX Byte 0 ==
5765 19:23:00.646703 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5766 19:23:00.650340 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5767 19:23:00.653468 == TX Byte 1 ==
5768 19:23:00.656994 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5769 19:23:00.659976 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5770 19:23:00.660073
5771 19:23:00.663533 [DATLAT]
5772 19:23:00.663642 Freq=933, CH1 RK0
5773 19:23:00.663736
5774 19:23:00.667051 DATLAT Default: 0xd
5775 19:23:00.667131 0, 0xFFFF, sum = 0
5776 19:23:00.670161 1, 0xFFFF, sum = 0
5777 19:23:00.670271 2, 0xFFFF, sum = 0
5778 19:23:00.673245 3, 0xFFFF, sum = 0
5779 19:23:00.673325 4, 0xFFFF, sum = 0
5780 19:23:00.677061 5, 0xFFFF, sum = 0
5781 19:23:00.677152 6, 0xFFFF, sum = 0
5782 19:23:00.679992 7, 0xFFFF, sum = 0
5783 19:23:00.680109 8, 0xFFFF, sum = 0
5784 19:23:00.683745 9, 0xFFFF, sum = 0
5785 19:23:00.683840 10, 0x0, sum = 1
5786 19:23:00.686713 11, 0x0, sum = 2
5787 19:23:00.686848 12, 0x0, sum = 3
5788 19:23:00.690436 13, 0x0, sum = 4
5789 19:23:00.690535 best_step = 11
5790 19:23:00.690603
5791 19:23:00.690670 ==
5792 19:23:00.693368 Dram Type= 6, Freq= 0, CH_1, rank 0
5793 19:23:00.697017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5794 19:23:00.699742 ==
5795 19:23:00.699830 RX Vref Scan: 1
5796 19:23:00.699896
5797 19:23:00.703346 RX Vref 0 -> 0, step: 1
5798 19:23:00.703435
5799 19:23:00.706506 RX Delay -61 -> 252, step: 4
5800 19:23:00.706589
5801 19:23:00.710194 Set Vref, RX VrefLevel [Byte0]: 59
5802 19:23:00.713713 [Byte1]: 53
5803 19:23:00.713807
5804 19:23:00.716939 Final RX Vref Byte 0 = 59 to rank0
5805 19:23:00.720372 Final RX Vref Byte 1 = 53 to rank0
5806 19:23:00.723786 Final RX Vref Byte 0 = 59 to rank1
5807 19:23:00.726730 Final RX Vref Byte 1 = 53 to rank1==
5808 19:23:00.730137 Dram Type= 6, Freq= 0, CH_1, rank 0
5809 19:23:00.733499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5810 19:23:00.733598 ==
5811 19:23:00.733668 DQS Delay:
5812 19:23:00.736725 DQS0 = 0, DQS1 = 0
5813 19:23:00.736837 DQM Delay:
5814 19:23:00.740195 DQM0 = 97, DQM1 = 91
5815 19:23:00.740319 DQ Delay:
5816 19:23:00.743129 DQ0 =102, DQ1 =92, DQ2 =88, DQ3 =96
5817 19:23:00.746745 DQ4 =96, DQ5 =108, DQ6 =106, DQ7 =94
5818 19:23:00.749812 DQ8 =82, DQ9 =78, DQ10 =92, DQ11 =86
5819 19:23:00.753290 DQ12 =100, DQ13 =98, DQ14 =100, DQ15 =94
5820 19:23:00.753416
5821 19:23:00.753509
5822 19:23:00.762945 [DQSOSCAuto] RK0, (LSB)MR18= 0x1bf6, (MSB)MR19= 0x504, tDQSOscB0 = 425 ps tDQSOscB1 = 413 ps
5823 19:23:00.766552 CH1 RK0: MR19=504, MR18=1BF6
5824 19:23:00.770132 CH1_RK0: MR19=0x504, MR18=0x1BF6, DQSOSC=413, MR23=63, INC=63, DEC=42
5825 19:23:00.770245
5826 19:23:00.773177 ----->DramcWriteLeveling(PI) begin...
5827 19:23:00.776878 ==
5828 19:23:00.776985 Dram Type= 6, Freq= 0, CH_1, rank 1
5829 19:23:00.783809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5830 19:23:00.783921 ==
5831 19:23:00.786719 Write leveling (Byte 0): 27 => 27
5832 19:23:00.790364 Write leveling (Byte 1): 28 => 28
5833 19:23:00.793273 DramcWriteLeveling(PI) end<-----
5834 19:23:00.793384
5835 19:23:00.793461 ==
5836 19:23:00.797014 Dram Type= 6, Freq= 0, CH_1, rank 1
5837 19:23:00.800063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5838 19:23:00.800154 ==
5839 19:23:00.803584 [Gating] SW mode calibration
5840 19:23:00.809946 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5841 19:23:00.813610 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5842 19:23:00.820387 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5843 19:23:00.823272 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5844 19:23:00.826586 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5845 19:23:00.833550 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5846 19:23:00.837005 0 14 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5847 19:23:00.840541 0 14 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5848 19:23:00.846902 0 14 24 | B1->B0 | 3333 2f2f | 0 0 | (0 0) (0 0)
5849 19:23:00.850136 0 14 28 | B1->B0 | 2a2a 2323 | 1 0 | (0 0) (0 0)
5850 19:23:00.853686 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5851 19:23:00.860177 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5852 19:23:00.863383 0 15 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5853 19:23:00.866868 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5854 19:23:00.873199 0 15 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5855 19:23:00.876914 0 15 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5856 19:23:00.880016 0 15 24 | B1->B0 | 2828 3434 | 0 0 | (0 0) (1 1)
5857 19:23:00.886884 0 15 28 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
5858 19:23:00.889890 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5859 19:23:00.893487 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5860 19:23:00.896566 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5861 19:23:00.903251 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5862 19:23:00.906937 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5863 19:23:00.909925 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5864 19:23:00.916694 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5865 19:23:00.919605 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5866 19:23:00.923311 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5867 19:23:00.929684 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5868 19:23:00.933375 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5869 19:23:00.936318 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5870 19:23:00.943387 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5871 19:23:00.946458 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5872 19:23:00.949693 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5873 19:23:00.956734 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5874 19:23:00.960001 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5875 19:23:00.963155 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5876 19:23:00.970027 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5877 19:23:00.973589 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5878 19:23:00.976511 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5879 19:23:00.983167 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5880 19:23:00.986922 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5881 19:23:00.990005 Total UI for P1: 0, mck2ui 16
5882 19:23:00.993651 best dqsien dly found for B0: ( 1, 2, 22)
5883 19:23:00.996542 Total UI for P1: 0, mck2ui 16
5884 19:23:01.000171 best dqsien dly found for B1: ( 1, 2, 22)
5885 19:23:01.003283 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5886 19:23:01.007012 best DQS1 dly(MCK, UI, PI) = (1, 2, 22)
5887 19:23:01.007126
5888 19:23:01.009968 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5889 19:23:01.013636 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 22)
5890 19:23:01.016867 [Gating] SW calibration Done
5891 19:23:01.016960 ==
5892 19:23:01.020209 Dram Type= 6, Freq= 0, CH_1, rank 1
5893 19:23:01.023132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5894 19:23:01.023214 ==
5895 19:23:01.026804 RX Vref Scan: 0
5896 19:23:01.026887
5897 19:23:01.026956 RX Vref 0 -> 0, step: 1
5898 19:23:01.029837
5899 19:23:01.029922 RX Delay -80 -> 252, step: 8
5900 19:23:01.036787 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5901 19:23:01.039914 iDelay=200, Bit 1, Center 91 (0 ~ 183) 184
5902 19:23:01.043426 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5903 19:23:01.046918 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5904 19:23:01.049645 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5905 19:23:01.053088 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5906 19:23:01.056695 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5907 19:23:01.063535 iDelay=200, Bit 7, Center 91 (0 ~ 183) 184
5908 19:23:01.066585 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5909 19:23:01.070106 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5910 19:23:01.073385 iDelay=200, Bit 10, Center 95 (0 ~ 191) 192
5911 19:23:01.076599 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5912 19:23:01.079855 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5913 19:23:01.086477 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5914 19:23:01.089972 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5915 19:23:01.093139 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5916 19:23:01.093253 ==
5917 19:23:01.096988 Dram Type= 6, Freq= 0, CH_1, rank 1
5918 19:23:01.099899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5919 19:23:01.100002 ==
5920 19:23:01.103012 DQS Delay:
5921 19:23:01.103111 DQS0 = 0, DQS1 = 0
5922 19:23:01.106652 DQM Delay:
5923 19:23:01.106772 DQM0 = 95, DQM1 = 89
5924 19:23:01.106866 DQ Delay:
5925 19:23:01.109763 DQ0 =95, DQ1 =91, DQ2 =87, DQ3 =95
5926 19:23:01.113323 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =91
5927 19:23:01.116878 DQ8 =79, DQ9 =79, DQ10 =95, DQ11 =79
5928 19:23:01.120079 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5929 19:23:01.120170
5930 19:23:01.120234
5931 19:23:01.123323 ==
5932 19:23:01.123398 Dram Type= 6, Freq= 0, CH_1, rank 1
5933 19:23:01.129841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5934 19:23:01.129947 ==
5935 19:23:01.130016
5936 19:23:01.130077
5937 19:23:01.133351 TX Vref Scan disable
5938 19:23:01.133425 == TX Byte 0 ==
5939 19:23:01.136453 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5940 19:23:01.142717 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5941 19:23:01.142829 == TX Byte 1 ==
5942 19:23:01.146479 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5943 19:23:01.153130 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5944 19:23:01.153251 ==
5945 19:23:01.156156 Dram Type= 6, Freq= 0, CH_1, rank 1
5946 19:23:01.159832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5947 19:23:01.159923 ==
5948 19:23:01.160006
5949 19:23:01.160071
5950 19:23:01.163069 TX Vref Scan disable
5951 19:23:01.166755 == TX Byte 0 ==
5952 19:23:01.169659 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5953 19:23:01.173386 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5954 19:23:01.176300 == TX Byte 1 ==
5955 19:23:01.179953 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5956 19:23:01.183027 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5957 19:23:01.183114
5958 19:23:01.183186 [DATLAT]
5959 19:23:01.186452 Freq=933, CH1 RK1
5960 19:23:01.186536
5961 19:23:01.186624 DATLAT Default: 0xb
5962 19:23:01.189570 0, 0xFFFF, sum = 0
5963 19:23:01.193387 1, 0xFFFF, sum = 0
5964 19:23:01.193484 2, 0xFFFF, sum = 0
5965 19:23:01.196705 3, 0xFFFF, sum = 0
5966 19:23:01.196796 4, 0xFFFF, sum = 0
5967 19:23:01.199933 5, 0xFFFF, sum = 0
5968 19:23:01.200020 6, 0xFFFF, sum = 0
5969 19:23:01.203031 7, 0xFFFF, sum = 0
5970 19:23:01.203115 8, 0xFFFF, sum = 0
5971 19:23:01.206333 9, 0xFFFF, sum = 0
5972 19:23:01.206452 10, 0x0, sum = 1
5973 19:23:01.209945 11, 0x0, sum = 2
5974 19:23:01.210040 12, 0x0, sum = 3
5975 19:23:01.213481 13, 0x0, sum = 4
5976 19:23:01.213569 best_step = 11
5977 19:23:01.213640
5978 19:23:01.213706 ==
5979 19:23:01.216578 Dram Type= 6, Freq= 0, CH_1, rank 1
5980 19:23:01.220146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5981 19:23:01.220236 ==
5982 19:23:01.223221 RX Vref Scan: 0
5983 19:23:01.223299
5984 19:23:01.226286 RX Vref 0 -> 0, step: 1
5985 19:23:01.226364
5986 19:23:01.226436 RX Delay -61 -> 252, step: 4
5987 19:23:01.234015 iDelay=195, Bit 0, Center 98 (7 ~ 190) 184
5988 19:23:01.237616 iDelay=195, Bit 1, Center 90 (-1 ~ 182) 184
5989 19:23:01.240668 iDelay=195, Bit 2, Center 84 (-5 ~ 174) 180
5990 19:23:01.244114 iDelay=195, Bit 3, Center 94 (3 ~ 186) 184
5991 19:23:01.247458 iDelay=195, Bit 4, Center 96 (7 ~ 186) 180
5992 19:23:01.250972 iDelay=195, Bit 5, Center 104 (15 ~ 194) 180
5993 19:23:01.257143 iDelay=195, Bit 6, Center 102 (11 ~ 194) 184
5994 19:23:01.260629 iDelay=195, Bit 7, Center 92 (7 ~ 178) 172
5995 19:23:01.264067 iDelay=195, Bit 8, Center 80 (-13 ~ 174) 188
5996 19:23:01.267445 iDelay=195, Bit 9, Center 80 (-9 ~ 170) 180
5997 19:23:01.270349 iDelay=195, Bit 10, Center 90 (-5 ~ 186) 192
5998 19:23:01.277217 iDelay=195, Bit 11, Center 82 (-9 ~ 174) 184
5999 19:23:01.280824 iDelay=195, Bit 12, Center 96 (7 ~ 186) 180
6000 19:23:01.283918 iDelay=195, Bit 13, Center 98 (7 ~ 190) 184
6001 19:23:01.287451 iDelay=195, Bit 14, Center 98 (7 ~ 190) 184
6002 19:23:01.290585 iDelay=195, Bit 15, Center 98 (7 ~ 190) 184
6003 19:23:01.290702 ==
6004 19:23:01.294254 Dram Type= 6, Freq= 0, CH_1, rank 1
6005 19:23:01.297226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6006 19:23:01.300634 ==
6007 19:23:01.300721 DQS Delay:
6008 19:23:01.300787 DQS0 = 0, DQS1 = 0
6009 19:23:01.304042 DQM Delay:
6010 19:23:01.304124 DQM0 = 95, DQM1 = 90
6011 19:23:01.307338 DQ Delay:
6012 19:23:01.307450 DQ0 =98, DQ1 =90, DQ2 =84, DQ3 =94
6013 19:23:01.310572 DQ4 =96, DQ5 =104, DQ6 =102, DQ7 =92
6014 19:23:01.313855 DQ8 =80, DQ9 =80, DQ10 =90, DQ11 =82
6015 19:23:01.317622 DQ12 =96, DQ13 =98, DQ14 =98, DQ15 =98
6016 19:23:01.320418
6017 19:23:01.320499
6018 19:23:01.327012 [DQSOSCAuto] RK1, (LSB)MR18= 0x1019, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 416 ps
6019 19:23:01.331120 CH1 RK1: MR19=505, MR18=1019
6020 19:23:01.337702 CH1_RK1: MR19=0x505, MR18=0x1019, DQSOSC=413, MR23=63, INC=63, DEC=42
6021 19:23:01.340556 [RxdqsGatingPostProcess] freq 933
6022 19:23:01.344296 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6023 19:23:01.347349 best DQS0 dly(2T, 0.5T) = (0, 10)
6024 19:23:01.350956 best DQS1 dly(2T, 0.5T) = (0, 10)
6025 19:23:01.354308 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6026 19:23:01.357744 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6027 19:23:01.360815 best DQS0 dly(2T, 0.5T) = (0, 10)
6028 19:23:01.363944 best DQS1 dly(2T, 0.5T) = (0, 10)
6029 19:23:01.367693 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6030 19:23:01.370576 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6031 19:23:01.373866 Pre-setting of DQS Precalculation
6032 19:23:01.377390 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6033 19:23:01.384144 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6034 19:23:01.391013 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6035 19:23:01.391130
6036 19:23:01.394541
6037 19:23:01.394624 [Calibration Summary] 1866 Mbps
6038 19:23:01.397581 CH 0, Rank 0
6039 19:23:01.397662 SW Impedance : PASS
6040 19:23:01.401200 DUTY Scan : NO K
6041 19:23:01.404309 ZQ Calibration : PASS
6042 19:23:01.404389 Jitter Meter : NO K
6043 19:23:01.407988 CBT Training : PASS
6044 19:23:01.410894 Write leveling : PASS
6045 19:23:01.410987 RX DQS gating : PASS
6046 19:23:01.414351 RX DQ/DQS(RDDQC) : PASS
6047 19:23:01.417823 TX DQ/DQS : PASS
6048 19:23:01.417919 RX DATLAT : PASS
6049 19:23:01.420756 RX DQ/DQS(Engine): PASS
6050 19:23:01.420833 TX OE : NO K
6051 19:23:01.424086 All Pass.
6052 19:23:01.424166
6053 19:23:01.424245 CH 0, Rank 1
6054 19:23:01.427231 SW Impedance : PASS
6055 19:23:01.427336 DUTY Scan : NO K
6056 19:23:01.431174 ZQ Calibration : PASS
6057 19:23:01.433847 Jitter Meter : NO K
6058 19:23:01.433938 CBT Training : PASS
6059 19:23:01.437324 Write leveling : PASS
6060 19:23:01.440827 RX DQS gating : PASS
6061 19:23:01.440923 RX DQ/DQS(RDDQC) : PASS
6062 19:23:01.444314 TX DQ/DQS : PASS
6063 19:23:01.447331 RX DATLAT : PASS
6064 19:23:01.447416 RX DQ/DQS(Engine): PASS
6065 19:23:01.451082 TX OE : NO K
6066 19:23:01.451167 All Pass.
6067 19:23:01.451232
6068 19:23:01.454036 CH 1, Rank 0
6069 19:23:01.454114 SW Impedance : PASS
6070 19:23:01.457846 DUTY Scan : NO K
6071 19:23:01.460680 ZQ Calibration : PASS
6072 19:23:01.460775 Jitter Meter : NO K
6073 19:23:01.463803 CBT Training : PASS
6074 19:23:01.467432 Write leveling : PASS
6075 19:23:01.467570 RX DQS gating : PASS
6076 19:23:01.471048 RX DQ/DQS(RDDQC) : PASS
6077 19:23:01.471148 TX DQ/DQS : PASS
6078 19:23:01.474083 RX DATLAT : PASS
6079 19:23:01.477664 RX DQ/DQS(Engine): PASS
6080 19:23:01.477768 TX OE : NO K
6081 19:23:01.480536 All Pass.
6082 19:23:01.480632
6083 19:23:01.480710 CH 1, Rank 1
6084 19:23:01.483802 SW Impedance : PASS
6085 19:23:01.483919 DUTY Scan : NO K
6086 19:23:01.487567 ZQ Calibration : PASS
6087 19:23:01.490575 Jitter Meter : NO K
6088 19:23:01.490662 CBT Training : PASS
6089 19:23:01.494373 Write leveling : PASS
6090 19:23:01.497261 RX DQS gating : PASS
6091 19:23:01.497353 RX DQ/DQS(RDDQC) : PASS
6092 19:23:01.500513 TX DQ/DQS : PASS
6093 19:23:01.503806 RX DATLAT : PASS
6094 19:23:01.503936 RX DQ/DQS(Engine): PASS
6095 19:23:01.507501 TX OE : NO K
6096 19:23:01.507629 All Pass.
6097 19:23:01.507727
6098 19:23:01.510476 DramC Write-DBI off
6099 19:23:01.514363 PER_BANK_REFRESH: Hybrid Mode
6100 19:23:01.514482 TX_TRACKING: ON
6101 19:23:01.524230 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6102 19:23:01.527300 [FAST_K] Save calibration result to emmc
6103 19:23:01.530866 dramc_set_vcore_voltage set vcore to 650000
6104 19:23:01.533903 Read voltage for 400, 6
6105 19:23:01.534025 Vio18 = 0
6106 19:23:01.534120 Vcore = 650000
6107 19:23:01.537501 Vdram = 0
6108 19:23:01.537592 Vddq = 0
6109 19:23:01.537659 Vmddr = 0
6110 19:23:01.544237 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6111 19:23:01.547496 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6112 19:23:01.550622 MEM_TYPE=3, freq_sel=20
6113 19:23:01.553868 sv_algorithm_assistance_LP4_800
6114 19:23:01.557059 ============ PULL DRAM RESETB DOWN ============
6115 19:23:01.560483 ========== PULL DRAM RESETB DOWN end =========
6116 19:23:01.567203 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6117 19:23:01.570645 ===================================
6118 19:23:01.570742 LPDDR4 DRAM CONFIGURATION
6119 19:23:01.574039 ===================================
6120 19:23:01.577214 EX_ROW_EN[0] = 0x0
6121 19:23:01.580890 EX_ROW_EN[1] = 0x0
6122 19:23:01.581009 LP4Y_EN = 0x0
6123 19:23:01.583896 WORK_FSP = 0x0
6124 19:23:01.584008 WL = 0x2
6125 19:23:01.587450 RL = 0x2
6126 19:23:01.587529 BL = 0x2
6127 19:23:01.590618 RPST = 0x0
6128 19:23:01.590695 RD_PRE = 0x0
6129 19:23:01.594170 WR_PRE = 0x1
6130 19:23:01.594252 WR_PST = 0x0
6131 19:23:01.597160 DBI_WR = 0x0
6132 19:23:01.597250 DBI_RD = 0x0
6133 19:23:01.600927 OTF = 0x1
6134 19:23:01.603897 ===================================
6135 19:23:01.607520 ===================================
6136 19:23:01.607617 ANA top config
6137 19:23:01.610493 ===================================
6138 19:23:01.614134 DLL_ASYNC_EN = 0
6139 19:23:01.617384 ALL_SLAVE_EN = 1
6140 19:23:01.617480 NEW_RANK_MODE = 1
6141 19:23:01.620943 DLL_IDLE_MODE = 1
6142 19:23:01.623985 LP45_APHY_COMB_EN = 1
6143 19:23:01.627541 TX_ODT_DIS = 1
6144 19:23:01.627653 NEW_8X_MODE = 1
6145 19:23:01.630462 ===================================
6146 19:23:01.633928 ===================================
6147 19:23:01.637479 data_rate = 800
6148 19:23:01.641252 CKR = 1
6149 19:23:01.644206 DQ_P2S_RATIO = 4
6150 19:23:01.647352 ===================================
6151 19:23:01.650841 CA_P2S_RATIO = 4
6152 19:23:01.654373 DQ_CA_OPEN = 0
6153 19:23:01.654473 DQ_SEMI_OPEN = 1
6154 19:23:01.657161 CA_SEMI_OPEN = 1
6155 19:23:01.660713 CA_FULL_RATE = 0
6156 19:23:01.664202 DQ_CKDIV4_EN = 0
6157 19:23:01.667357 CA_CKDIV4_EN = 1
6158 19:23:01.671017 CA_PREDIV_EN = 0
6159 19:23:01.671104 PH8_DLY = 0
6160 19:23:01.674055 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6161 19:23:01.677563 DQ_AAMCK_DIV = 0
6162 19:23:01.680914 CA_AAMCK_DIV = 0
6163 19:23:01.684561 CA_ADMCK_DIV = 4
6164 19:23:01.687383 DQ_TRACK_CA_EN = 0
6165 19:23:01.687519 CA_PICK = 800
6166 19:23:01.691186 CA_MCKIO = 400
6167 19:23:01.694064 MCKIO_SEMI = 400
6168 19:23:01.697580 PLL_FREQ = 3016
6169 19:23:01.700829 DQ_UI_PI_RATIO = 32
6170 19:23:01.704028 CA_UI_PI_RATIO = 32
6171 19:23:01.707635 ===================================
6172 19:23:01.711131 ===================================
6173 19:23:01.711224 memory_type:LPDDR4
6174 19:23:01.714131 GP_NUM : 10
6175 19:23:01.717725 SRAM_EN : 1
6176 19:23:01.717834 MD32_EN : 0
6177 19:23:01.720849 ===================================
6178 19:23:01.724505 [ANA_INIT] >>>>>>>>>>>>>>
6179 19:23:01.727530 <<<<<< [CONFIGURE PHASE]: ANA_TX
6180 19:23:01.731179 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6181 19:23:01.734199 ===================================
6182 19:23:01.737723 data_rate = 800,PCW = 0X7400
6183 19:23:01.741072 ===================================
6184 19:23:01.744569 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6185 19:23:01.747717 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6186 19:23:01.760941 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6187 19:23:01.764339 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6188 19:23:01.767488 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6189 19:23:01.771272 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6190 19:23:01.774314 [ANA_INIT] flow start
6191 19:23:01.774402 [ANA_INIT] PLL >>>>>>>>
6192 19:23:01.777625 [ANA_INIT] PLL <<<<<<<<
6193 19:23:01.781094 [ANA_INIT] MIDPI >>>>>>>>
6194 19:23:01.784198 [ANA_INIT] MIDPI <<<<<<<<
6195 19:23:01.784319 [ANA_INIT] DLL >>>>>>>>
6196 19:23:01.787929 [ANA_INIT] flow end
6197 19:23:01.791196 ============ LP4 DIFF to SE enter ============
6198 19:23:01.794297 ============ LP4 DIFF to SE exit ============
6199 19:23:01.797541 [ANA_INIT] <<<<<<<<<<<<<
6200 19:23:01.801347 [Flow] Enable top DCM control >>>>>
6201 19:23:01.804203 [Flow] Enable top DCM control <<<<<
6202 19:23:01.807431 Enable DLL master slave shuffle
6203 19:23:01.814326 ==============================================================
6204 19:23:01.814444 Gating Mode config
6205 19:23:01.821201 ==============================================================
6206 19:23:01.821349 Config description:
6207 19:23:01.830826 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6208 19:23:01.837641 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6209 19:23:01.844304 SELPH_MODE 0: By rank 1: By Phase
6210 19:23:01.847916 ==============================================================
6211 19:23:01.850754 GAT_TRACK_EN = 0
6212 19:23:01.854374 RX_GATING_MODE = 2
6213 19:23:01.857875 RX_GATING_TRACK_MODE = 2
6214 19:23:01.860953 SELPH_MODE = 1
6215 19:23:01.864055 PICG_EARLY_EN = 1
6216 19:23:01.867519 VALID_LAT_VALUE = 1
6217 19:23:01.871077 ==============================================================
6218 19:23:01.874707 Enter into Gating configuration >>>>
6219 19:23:01.877735 Exit from Gating configuration <<<<
6220 19:23:01.880893 Enter into DVFS_PRE_config >>>>>
6221 19:23:01.894479 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6222 19:23:01.897326 Exit from DVFS_PRE_config <<<<<
6223 19:23:01.897429 Enter into PICG configuration >>>>
6224 19:23:01.900779 Exit from PICG configuration <<<<
6225 19:23:01.904519 [RX_INPUT] configuration >>>>>
6226 19:23:01.907650 [RX_INPUT] configuration <<<<<
6227 19:23:01.914306 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6228 19:23:01.917682 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6229 19:23:01.924218 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6230 19:23:01.930970 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6231 19:23:01.937177 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6232 19:23:01.943918 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6233 19:23:01.947573 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6234 19:23:01.950621 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6235 19:23:01.954073 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6236 19:23:01.960991 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6237 19:23:01.964062 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6238 19:23:01.967669 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6239 19:23:01.970839 ===================================
6240 19:23:01.974313 LPDDR4 DRAM CONFIGURATION
6241 19:23:01.977871 ===================================
6242 19:23:01.977965 EX_ROW_EN[0] = 0x0
6243 19:23:01.981049 EX_ROW_EN[1] = 0x0
6244 19:23:01.984180 LP4Y_EN = 0x0
6245 19:23:01.984268 WORK_FSP = 0x0
6246 19:23:01.987628 WL = 0x2
6247 19:23:01.987744 RL = 0x2
6248 19:23:01.990765 BL = 0x2
6249 19:23:01.990859 RPST = 0x0
6250 19:23:01.994405 RD_PRE = 0x0
6251 19:23:01.994495 WR_PRE = 0x1
6252 19:23:01.997766 WR_PST = 0x0
6253 19:23:01.997858 DBI_WR = 0x0
6254 19:23:02.000846 DBI_RD = 0x0
6255 19:23:02.000936 OTF = 0x1
6256 19:23:02.004549 ===================================
6257 19:23:02.007644 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6258 19:23:02.014694 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6259 19:23:02.017564 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6260 19:23:02.021020 ===================================
6261 19:23:02.024263 LPDDR4 DRAM CONFIGURATION
6262 19:23:02.027995 ===================================
6263 19:23:02.028101 EX_ROW_EN[0] = 0x10
6264 19:23:02.031003 EX_ROW_EN[1] = 0x0
6265 19:23:02.031092 LP4Y_EN = 0x0
6266 19:23:02.034196 WORK_FSP = 0x0
6267 19:23:02.034291 WL = 0x2
6268 19:23:02.037455 RL = 0x2
6269 19:23:02.037556 BL = 0x2
6270 19:23:02.041081 RPST = 0x0
6271 19:23:02.041186 RD_PRE = 0x0
6272 19:23:02.044139 WR_PRE = 0x1
6273 19:23:02.047863 WR_PST = 0x0
6274 19:23:02.047964 DBI_WR = 0x0
6275 19:23:02.050918 DBI_RD = 0x0
6276 19:23:02.051006 OTF = 0x1
6277 19:23:02.054532 ===================================
6278 19:23:02.061100 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6279 19:23:02.064705 nWR fixed to 30
6280 19:23:02.067982 [ModeRegInit_LP4] CH0 RK0
6281 19:23:02.068082 [ModeRegInit_LP4] CH0 RK1
6282 19:23:02.071479 [ModeRegInit_LP4] CH1 RK0
6283 19:23:02.074672 [ModeRegInit_LP4] CH1 RK1
6284 19:23:02.074760 match AC timing 19
6285 19:23:02.081105 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6286 19:23:02.084655 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6287 19:23:02.087935 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6288 19:23:02.094503 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6289 19:23:02.098165 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6290 19:23:02.098270 ==
6291 19:23:02.101663 Dram Type= 6, Freq= 0, CH_0, rank 0
6292 19:23:02.104482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6293 19:23:02.104564 ==
6294 19:23:02.111700 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6295 19:23:02.117930 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6296 19:23:02.121471 [CA 0] Center 36 (8~64) winsize 57
6297 19:23:02.124809 [CA 1] Center 36 (8~64) winsize 57
6298 19:23:02.124930 [CA 2] Center 36 (8~64) winsize 57
6299 19:23:02.127937 [CA 3] Center 36 (8~64) winsize 57
6300 19:23:02.131662 [CA 4] Center 36 (8~64) winsize 57
6301 19:23:02.134620 [CA 5] Center 36 (8~64) winsize 57
6302 19:23:02.134718
6303 19:23:02.138027 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6304 19:23:02.138113
6305 19:23:02.144657 [CATrainingPosCal] consider 1 rank data
6306 19:23:02.144771 u2DelayCellTimex100 = 270/100 ps
6307 19:23:02.148057 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6308 19:23:02.155049 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6309 19:23:02.158199 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6310 19:23:02.161830 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6311 19:23:02.164670 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6312 19:23:02.168295 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6313 19:23:02.168391
6314 19:23:02.171304 CA PerBit enable=1, Macro0, CA PI delay=36
6315 19:23:02.171392
6316 19:23:02.174856 [CBTSetCACLKResult] CA Dly = 36
6317 19:23:02.174946 CS Dly: 1 (0~32)
6318 19:23:02.178187 ==
6319 19:23:02.181199 Dram Type= 6, Freq= 0, CH_0, rank 1
6320 19:23:02.184778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6321 19:23:02.184872 ==
6322 19:23:02.188256 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6323 19:23:02.195057 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6324 19:23:02.198099 [CA 0] Center 36 (8~64) winsize 57
6325 19:23:02.201855 [CA 1] Center 36 (8~64) winsize 57
6326 19:23:02.204935 [CA 2] Center 36 (8~64) winsize 57
6327 19:23:02.208293 [CA 3] Center 36 (8~64) winsize 57
6328 19:23:02.211256 [CA 4] Center 36 (8~64) winsize 57
6329 19:23:02.214935 [CA 5] Center 36 (8~64) winsize 57
6330 19:23:02.215041
6331 19:23:02.218103 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6332 19:23:02.218195
6333 19:23:02.221313 [CATrainingPosCal] consider 2 rank data
6334 19:23:02.224894 u2DelayCellTimex100 = 270/100 ps
6335 19:23:02.227848 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6336 19:23:02.231676 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6337 19:23:02.234677 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6338 19:23:02.238367 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6339 19:23:02.241418 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6340 19:23:02.247859 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6341 19:23:02.247977
6342 19:23:02.251387 CA PerBit enable=1, Macro0, CA PI delay=36
6343 19:23:02.251484
6344 19:23:02.254703 [CBTSetCACLKResult] CA Dly = 36
6345 19:23:02.254796 CS Dly: 1 (0~32)
6346 19:23:02.254894
6347 19:23:02.258207 ----->DramcWriteLeveling(PI) begin...
6348 19:23:02.258298 ==
6349 19:23:02.261231 Dram Type= 6, Freq= 0, CH_0, rank 0
6350 19:23:02.264842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6351 19:23:02.267902 ==
6352 19:23:02.268026 Write leveling (Byte 0): 40 => 8
6353 19:23:02.271485 Write leveling (Byte 1): 32 => 0
6354 19:23:02.274747 DramcWriteLeveling(PI) end<-----
6355 19:23:02.274840
6356 19:23:02.274906 ==
6357 19:23:02.277926 Dram Type= 6, Freq= 0, CH_0, rank 0
6358 19:23:02.284999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6359 19:23:02.285107 ==
6360 19:23:02.285176 [Gating] SW mode calibration
6361 19:23:02.294939 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6362 19:23:02.298397 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6363 19:23:02.301492 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6364 19:23:02.308262 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6365 19:23:02.311158 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6366 19:23:02.314730 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6367 19:23:02.321326 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6368 19:23:02.324407 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6369 19:23:02.328128 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6370 19:23:02.334176 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6371 19:23:02.337759 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6372 19:23:02.341122 Total UI for P1: 0, mck2ui 16
6373 19:23:02.344826 best dqsien dly found for B0: ( 0, 14, 24)
6374 19:23:02.347760 Total UI for P1: 0, mck2ui 16
6375 19:23:02.351326 best dqsien dly found for B1: ( 0, 14, 24)
6376 19:23:02.354773 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6377 19:23:02.357754 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6378 19:23:02.357865
6379 19:23:02.361141 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6380 19:23:02.364140 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6381 19:23:02.367632 [Gating] SW calibration Done
6382 19:23:02.367729 ==
6383 19:23:02.371288 Dram Type= 6, Freq= 0, CH_0, rank 0
6384 19:23:02.377983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6385 19:23:02.378100 ==
6386 19:23:02.378169 RX Vref Scan: 0
6387 19:23:02.378230
6388 19:23:02.381068 RX Vref 0 -> 0, step: 1
6389 19:23:02.381196
6390 19:23:02.384657 RX Delay -410 -> 252, step: 16
6391 19:23:02.387836 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6392 19:23:02.391407 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6393 19:23:02.394347 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6394 19:23:02.401222 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6395 19:23:02.404129 iDelay=230, Bit 4, Center -19 (-266 ~ 229) 496
6396 19:23:02.407770 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6397 19:23:02.411029 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6398 19:23:02.417528 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6399 19:23:02.421118 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6400 19:23:02.424601 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6401 19:23:02.427580 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6402 19:23:02.434343 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6403 19:23:02.437598 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6404 19:23:02.441232 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6405 19:23:02.444695 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6406 19:23:02.450892 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6407 19:23:02.451008 ==
6408 19:23:02.454300 Dram Type= 6, Freq= 0, CH_0, rank 0
6409 19:23:02.457691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6410 19:23:02.457788 ==
6411 19:23:02.457855 DQS Delay:
6412 19:23:02.461126 DQS0 = 35, DQS1 = 51
6413 19:23:02.461275 DQM Delay:
6414 19:23:02.464060 DQM0 = 8, DQM1 = 11
6415 19:23:02.464145 DQ Delay:
6416 19:23:02.467394 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6417 19:23:02.471043 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6418 19:23:02.474766 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6419 19:23:02.477584 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =24
6420 19:23:02.477676
6421 19:23:02.477742
6422 19:23:02.477803 ==
6423 19:23:02.481387 Dram Type= 6, Freq= 0, CH_0, rank 0
6424 19:23:02.484431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6425 19:23:02.484517 ==
6426 19:23:02.484583
6427 19:23:02.484643
6428 19:23:02.487572 TX Vref Scan disable
6429 19:23:02.491229 == TX Byte 0 ==
6430 19:23:02.494205 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6431 19:23:02.497809 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6432 19:23:02.497904 == TX Byte 1 ==
6433 19:23:02.504546 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6434 19:23:02.508007 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6435 19:23:02.508119 ==
6436 19:23:02.510892 Dram Type= 6, Freq= 0, CH_0, rank 0
6437 19:23:02.514336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6438 19:23:02.514461 ==
6439 19:23:02.514556
6440 19:23:02.514647
6441 19:23:02.518048 TX Vref Scan disable
6442 19:23:02.521029 == TX Byte 0 ==
6443 19:23:02.524404 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6444 19:23:02.527966 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6445 19:23:02.531011 == TX Byte 1 ==
6446 19:23:02.534644 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6447 19:23:02.537693 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6448 19:23:02.537790
6449 19:23:02.537857 [DATLAT]
6450 19:23:02.541438 Freq=400, CH0 RK0
6451 19:23:02.541525
6452 19:23:02.541591 DATLAT Default: 0xf
6453 19:23:02.544457 0, 0xFFFF, sum = 0
6454 19:23:02.544544 1, 0xFFFF, sum = 0
6455 19:23:02.548047 2, 0xFFFF, sum = 0
6456 19:23:02.551084 3, 0xFFFF, sum = 0
6457 19:23:02.551187 4, 0xFFFF, sum = 0
6458 19:23:02.554481 5, 0xFFFF, sum = 0
6459 19:23:02.554577 6, 0xFFFF, sum = 0
6460 19:23:02.558177 7, 0xFFFF, sum = 0
6461 19:23:02.558267 8, 0xFFFF, sum = 0
6462 19:23:02.561001 9, 0xFFFF, sum = 0
6463 19:23:02.561088 10, 0xFFFF, sum = 0
6464 19:23:02.564796 11, 0xFFFF, sum = 0
6465 19:23:02.564885 12, 0xFFFF, sum = 0
6466 19:23:02.567959 13, 0x0, sum = 1
6467 19:23:02.568046 14, 0x0, sum = 2
6468 19:23:02.571364 15, 0x0, sum = 3
6469 19:23:02.571453 16, 0x0, sum = 4
6470 19:23:02.571519 best_step = 14
6471 19:23:02.574439
6472 19:23:02.574524 ==
6473 19:23:02.577825 Dram Type= 6, Freq= 0, CH_0, rank 0
6474 19:23:02.581358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6475 19:23:02.581449 ==
6476 19:23:02.581515 RX Vref Scan: 1
6477 19:23:02.581576
6478 19:23:02.584371 RX Vref 0 -> 0, step: 1
6479 19:23:02.584458
6480 19:23:02.588221 RX Delay -343 -> 252, step: 8
6481 19:23:02.588349
6482 19:23:02.591119 Set Vref, RX VrefLevel [Byte0]: 51
6483 19:23:02.594837 [Byte1]: 50
6484 19:23:02.598476
6485 19:23:02.598567 Final RX Vref Byte 0 = 51 to rank0
6486 19:23:02.601614 Final RX Vref Byte 1 = 50 to rank0
6487 19:23:02.605393 Final RX Vref Byte 0 = 51 to rank1
6488 19:23:02.608292 Final RX Vref Byte 1 = 50 to rank1==
6489 19:23:02.611439 Dram Type= 6, Freq= 0, CH_0, rank 0
6490 19:23:02.618524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6491 19:23:02.618646 ==
6492 19:23:02.618716 DQS Delay:
6493 19:23:02.618777 DQS0 = 44, DQS1 = 60
6494 19:23:02.621854 DQM Delay:
6495 19:23:02.621941 DQM0 = 11, DQM1 = 14
6496 19:23:02.625129 DQ Delay:
6497 19:23:02.628129 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =8
6498 19:23:02.628218 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6499 19:23:02.631754 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6500 19:23:02.635117 DQ12 =20, DQ13 =16, DQ14 =28, DQ15 =24
6501 19:23:02.635216
6502 19:23:02.635282
6503 19:23:02.644857 [DQSOSCAuto] RK0, (LSB)MR18= 0x8b5a, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 392 ps
6504 19:23:02.648615 CH0 RK0: MR19=C0C, MR18=8B5A
6505 19:23:02.655357 CH0_RK0: MR19=0xC0C, MR18=0x8B5A, DQSOSC=392, MR23=63, INC=384, DEC=256
6506 19:23:02.655488 ==
6507 19:23:02.658323 Dram Type= 6, Freq= 0, CH_0, rank 1
6508 19:23:02.661894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6509 19:23:02.661990 ==
6510 19:23:02.665551 [Gating] SW mode calibration
6511 19:23:02.671877 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6512 19:23:02.675213 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6513 19:23:02.681915 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6514 19:23:02.685367 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6515 19:23:02.688202 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6516 19:23:02.695386 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6517 19:23:02.698515 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6518 19:23:02.701405 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6519 19:23:02.708631 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6520 19:23:02.711675 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6521 19:23:02.715332 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6522 19:23:02.718398 Total UI for P1: 0, mck2ui 16
6523 19:23:02.721482 best dqsien dly found for B0: ( 0, 14, 24)
6524 19:23:02.725268 Total UI for P1: 0, mck2ui 16
6525 19:23:02.728285 best dqsien dly found for B1: ( 0, 14, 24)
6526 19:23:02.731723 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6527 19:23:02.734914 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6528 19:23:02.735030
6529 19:23:02.741923 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6530 19:23:02.745402 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6531 19:23:02.745500 [Gating] SW calibration Done
6532 19:23:02.748486 ==
6533 19:23:02.748581 Dram Type= 6, Freq= 0, CH_0, rank 1
6534 19:23:02.755119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6535 19:23:02.755267 ==
6536 19:23:02.755371 RX Vref Scan: 0
6537 19:23:02.755463
6538 19:23:02.758232 RX Vref 0 -> 0, step: 1
6539 19:23:02.758311
6540 19:23:02.761766 RX Delay -410 -> 252, step: 16
6541 19:23:02.765132 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6542 19:23:02.768058 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6543 19:23:02.774848 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6544 19:23:02.778316 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6545 19:23:02.781652 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6546 19:23:02.784589 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496
6547 19:23:02.791651 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6548 19:23:02.795002 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6549 19:23:02.798425 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6550 19:23:02.801374 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6551 19:23:02.808242 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6552 19:23:02.811706 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6553 19:23:02.814776 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6554 19:23:02.818579 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6555 19:23:02.824798 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6556 19:23:02.827793 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6557 19:23:02.827926 ==
6558 19:23:02.831563 Dram Type= 6, Freq= 0, CH_0, rank 1
6559 19:23:02.834554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6560 19:23:02.834682 ==
6561 19:23:02.838185 DQS Delay:
6562 19:23:02.838302 DQS0 = 51, DQS1 = 51
6563 19:23:02.841782 DQM Delay:
6564 19:23:02.841905 DQM0 = 18, DQM1 = 9
6565 19:23:02.842001 DQ Delay:
6566 19:23:02.844759 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6567 19:23:02.847944 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6568 19:23:02.851612 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6569 19:23:02.854893 DQ12 =8, DQ13 =16, DQ14 =16, DQ15 =16
6570 19:23:02.855012
6571 19:23:02.855120
6572 19:23:02.855220 ==
6573 19:23:02.857986 Dram Type= 6, Freq= 0, CH_0, rank 1
6574 19:23:02.864559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6575 19:23:02.864689 ==
6576 19:23:02.864796
6577 19:23:02.864887
6578 19:23:02.864984 TX Vref Scan disable
6579 19:23:02.867998 == TX Byte 0 ==
6580 19:23:02.871585 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6581 19:23:02.874457 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6582 19:23:02.877967 == TX Byte 1 ==
6583 19:23:02.881547 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6584 19:23:02.884572 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6585 19:23:02.884652 ==
6586 19:23:02.888014 Dram Type= 6, Freq= 0, CH_0, rank 1
6587 19:23:02.894961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6588 19:23:02.895096 ==
6589 19:23:02.895202
6590 19:23:02.895294
6591 19:23:02.895383 TX Vref Scan disable
6592 19:23:02.898025 == TX Byte 0 ==
6593 19:23:02.901527 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6594 19:23:02.905011 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6595 19:23:02.907826 == TX Byte 1 ==
6596 19:23:02.911471 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6597 19:23:02.915098 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6598 19:23:02.915192
6599 19:23:02.918303 [DATLAT]
6600 19:23:02.918391 Freq=400, CH0 RK1
6601 19:23:02.918460
6602 19:23:02.921710 DATLAT Default: 0xe
6603 19:23:02.921800 0, 0xFFFF, sum = 0
6604 19:23:02.924811 1, 0xFFFF, sum = 0
6605 19:23:02.924927 2, 0xFFFF, sum = 0
6606 19:23:02.928531 3, 0xFFFF, sum = 0
6607 19:23:02.928623 4, 0xFFFF, sum = 0
6608 19:23:02.931583 5, 0xFFFF, sum = 0
6609 19:23:02.931673 6, 0xFFFF, sum = 0
6610 19:23:02.934703 7, 0xFFFF, sum = 0
6611 19:23:02.934792 8, 0xFFFF, sum = 0
6612 19:23:02.938423 9, 0xFFFF, sum = 0
6613 19:23:02.938530 10, 0xFFFF, sum = 0
6614 19:23:02.941536 11, 0xFFFF, sum = 0
6615 19:23:02.941627 12, 0xFFFF, sum = 0
6616 19:23:02.945114 13, 0x0, sum = 1
6617 19:23:02.945212 14, 0x0, sum = 2
6618 19:23:02.948236 15, 0x0, sum = 3
6619 19:23:02.948323 16, 0x0, sum = 4
6620 19:23:02.951401 best_step = 14
6621 19:23:02.951489
6622 19:23:02.951569 ==
6623 19:23:02.954967 Dram Type= 6, Freq= 0, CH_0, rank 1
6624 19:23:02.958342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6625 19:23:02.958434 ==
6626 19:23:02.961862 RX Vref Scan: 0
6627 19:23:02.961951
6628 19:23:02.962022 RX Vref 0 -> 0, step: 1
6629 19:23:02.962096
6630 19:23:02.965149 RX Delay -343 -> 252, step: 8
6631 19:23:02.973344 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6632 19:23:02.976410 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6633 19:23:02.979506 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6634 19:23:02.982986 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6635 19:23:02.989594 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6636 19:23:02.992645 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6637 19:23:02.996162 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6638 19:23:02.999449 iDelay=217, Bit 7, Center -32 (-271 ~ 208) 480
6639 19:23:03.006238 iDelay=217, Bit 8, Center -56 (-295 ~ 184) 480
6640 19:23:03.009792 iDelay=217, Bit 9, Center -56 (-295 ~ 184) 480
6641 19:23:03.012703 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6642 19:23:03.016178 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6643 19:23:03.022778 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6644 19:23:03.025780 iDelay=217, Bit 13, Center -44 (-287 ~ 200) 488
6645 19:23:03.029452 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6646 19:23:03.036381 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6647 19:23:03.036525 ==
6648 19:23:03.039424 Dram Type= 6, Freq= 0, CH_0, rank 1
6649 19:23:03.042568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6650 19:23:03.042687 ==
6651 19:23:03.042785 DQS Delay:
6652 19:23:03.046048 DQS0 = 48, DQS1 = 56
6653 19:23:03.046154 DQM Delay:
6654 19:23:03.049143 DQM0 = 12, DQM1 = 9
6655 19:23:03.049270 DQ Delay:
6656 19:23:03.052744 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =12
6657 19:23:03.055775 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6658 19:23:03.059495 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6659 19:23:03.062574 DQ12 =12, DQ13 =12, DQ14 =20, DQ15 =20
6660 19:23:03.062690
6661 19:23:03.062783
6662 19:23:03.069115 [DQSOSCAuto] RK1, (LSB)MR18= 0x996b, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 390 ps
6663 19:23:03.072814 CH0 RK1: MR19=C0C, MR18=996B
6664 19:23:03.079105 CH0_RK1: MR19=0xC0C, MR18=0x996B, DQSOSC=390, MR23=63, INC=388, DEC=258
6665 19:23:03.082685 [RxdqsGatingPostProcess] freq 400
6666 19:23:03.088974 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6667 19:23:03.089117 best DQS0 dly(2T, 0.5T) = (0, 10)
6668 19:23:03.092327 best DQS1 dly(2T, 0.5T) = (0, 10)
6669 19:23:03.095923 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6670 19:23:03.098948 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6671 19:23:03.102658 best DQS0 dly(2T, 0.5T) = (0, 10)
6672 19:23:03.106000 best DQS1 dly(2T, 0.5T) = (0, 10)
6673 19:23:03.109129 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6674 19:23:03.112550 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6675 19:23:03.115465 Pre-setting of DQS Precalculation
6676 19:23:03.122385 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6677 19:23:03.122544 ==
6678 19:23:03.125933 Dram Type= 6, Freq= 0, CH_1, rank 0
6679 19:23:03.129298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6680 19:23:03.129410 ==
6681 19:23:03.132563 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6682 19:23:03.139262 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6683 19:23:03.142975 [CA 0] Center 36 (8~64) winsize 57
6684 19:23:03.145946 [CA 1] Center 36 (8~64) winsize 57
6685 19:23:03.149029 [CA 2] Center 36 (8~64) winsize 57
6686 19:23:03.152815 [CA 3] Center 36 (8~64) winsize 57
6687 19:23:03.155787 [CA 4] Center 36 (8~64) winsize 57
6688 19:23:03.159477 [CA 5] Center 36 (8~64) winsize 57
6689 19:23:03.159598
6690 19:23:03.162606 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6691 19:23:03.162715
6692 19:23:03.165844 [CATrainingPosCal] consider 1 rank data
6693 19:23:03.168915 u2DelayCellTimex100 = 270/100 ps
6694 19:23:03.172456 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6695 19:23:03.176048 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6696 19:23:03.179578 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6697 19:23:03.182712 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6698 19:23:03.186241 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6699 19:23:03.192814 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6700 19:23:03.192958
6701 19:23:03.195725 CA PerBit enable=1, Macro0, CA PI delay=36
6702 19:23:03.195808
6703 19:23:03.199424 [CBTSetCACLKResult] CA Dly = 36
6704 19:23:03.199515 CS Dly: 1 (0~32)
6705 19:23:03.199583 ==
6706 19:23:03.202680 Dram Type= 6, Freq= 0, CH_1, rank 1
6707 19:23:03.206189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6708 19:23:03.206295 ==
6709 19:23:03.212489 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6710 19:23:03.219114 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6711 19:23:03.222431 [CA 0] Center 36 (8~64) winsize 57
6712 19:23:03.225952 [CA 1] Center 36 (8~64) winsize 57
6713 19:23:03.229154 [CA 2] Center 36 (8~64) winsize 57
6714 19:23:03.233008 [CA 3] Center 36 (8~64) winsize 57
6715 19:23:03.235697 [CA 4] Center 36 (8~64) winsize 57
6716 19:23:03.235791 [CA 5] Center 36 (8~64) winsize 57
6717 19:23:03.239051
6718 19:23:03.242903 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6719 19:23:03.243027
6720 19:23:03.245911 [CATrainingPosCal] consider 2 rank data
6721 19:23:03.249615 u2DelayCellTimex100 = 270/100 ps
6722 19:23:03.252758 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6723 19:23:03.256377 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6724 19:23:03.259443 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6725 19:23:03.262579 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6726 19:23:03.266333 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6727 19:23:03.269448 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6728 19:23:03.269542
6729 19:23:03.272501 CA PerBit enable=1, Macro0, CA PI delay=36
6730 19:23:03.272587
6731 19:23:03.276072 [CBTSetCACLKResult] CA Dly = 36
6732 19:23:03.279718 CS Dly: 1 (0~32)
6733 19:23:03.279810
6734 19:23:03.282443 ----->DramcWriteLeveling(PI) begin...
6735 19:23:03.282559 ==
6736 19:23:03.286277 Dram Type= 6, Freq= 0, CH_1, rank 0
6737 19:23:03.289650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6738 19:23:03.289742 ==
6739 19:23:03.292894 Write leveling (Byte 0): 40 => 8
6740 19:23:03.296491 Write leveling (Byte 1): 40 => 8
6741 19:23:03.299728 DramcWriteLeveling(PI) end<-----
6742 19:23:03.299822
6743 19:23:03.299889 ==
6744 19:23:03.302657 Dram Type= 6, Freq= 0, CH_1, rank 0
6745 19:23:03.306126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6746 19:23:03.306216 ==
6747 19:23:03.309850 [Gating] SW mode calibration
6748 19:23:03.315949 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6749 19:23:03.322484 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6750 19:23:03.326214 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6751 19:23:03.329461 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6752 19:23:03.336014 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6753 19:23:03.339716 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6754 19:23:03.342590 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6755 19:23:03.349060 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6756 19:23:03.352905 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6757 19:23:03.356120 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6758 19:23:03.362918 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6759 19:23:03.363076 Total UI for P1: 0, mck2ui 16
6760 19:23:03.365970 best dqsien dly found for B0: ( 0, 14, 24)
6761 19:23:03.369649 Total UI for P1: 0, mck2ui 16
6762 19:23:03.372725 best dqsien dly found for B1: ( 0, 14, 24)
6763 19:23:03.375837 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6764 19:23:03.383195 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6765 19:23:03.383339
6766 19:23:03.386167 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6767 19:23:03.389553 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6768 19:23:03.393038 [Gating] SW calibration Done
6769 19:23:03.393156 ==
6770 19:23:03.396014 Dram Type= 6, Freq= 0, CH_1, rank 0
6771 19:23:03.399891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6772 19:23:03.400022 ==
6773 19:23:03.400108 RX Vref Scan: 0
6774 19:23:03.402833
6775 19:23:03.402970 RX Vref 0 -> 0, step: 1
6776 19:23:03.403067
6777 19:23:03.406186 RX Delay -410 -> 252, step: 16
6778 19:23:03.409417 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6779 19:23:03.416521 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6780 19:23:03.419679 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6781 19:23:03.423420 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6782 19:23:03.426488 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6783 19:23:03.433148 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6784 19:23:03.436214 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6785 19:23:03.439784 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6786 19:23:03.442895 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6787 19:23:03.446325 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6788 19:23:03.452879 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6789 19:23:03.456293 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6790 19:23:03.459469 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6791 19:23:03.466340 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6792 19:23:03.469555 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6793 19:23:03.472926 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6794 19:23:03.473052 ==
6795 19:23:03.476076 Dram Type= 6, Freq= 0, CH_1, rank 0
6796 19:23:03.479678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6797 19:23:03.482827 ==
6798 19:23:03.482929 DQS Delay:
6799 19:23:03.483027 DQS0 = 51, DQS1 = 59
6800 19:23:03.485923 DQM Delay:
6801 19:23:03.486034 DQM0 = 19, DQM1 = 16
6802 19:23:03.489645 DQ Delay:
6803 19:23:03.492624 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6804 19:23:03.492702 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6805 19:23:03.496137 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6806 19:23:03.499511 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6807 19:23:03.499633
6808 19:23:03.502586
6809 19:23:03.502691 ==
6810 19:23:03.506175 Dram Type= 6, Freq= 0, CH_1, rank 0
6811 19:23:03.509200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6812 19:23:03.509293 ==
6813 19:23:03.509360
6814 19:23:03.509436
6815 19:23:03.512920 TX Vref Scan disable
6816 19:23:03.513036 == TX Byte 0 ==
6817 19:23:03.515976 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6818 19:23:03.522980 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6819 19:23:03.523128 == TX Byte 1 ==
6820 19:23:03.525979 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6821 19:23:03.532957 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6822 19:23:03.533094 ==
6823 19:23:03.536069 Dram Type= 6, Freq= 0, CH_1, rank 0
6824 19:23:03.539582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6825 19:23:03.539682 ==
6826 19:23:03.539777
6827 19:23:03.539866
6828 19:23:03.542623 TX Vref Scan disable
6829 19:23:03.542710 == TX Byte 0 ==
6830 19:23:03.546181 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6831 19:23:03.552801 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6832 19:23:03.552937 == TX Byte 1 ==
6833 19:23:03.555874 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6834 19:23:03.562724 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6835 19:23:03.562861
6836 19:23:03.562957 [DATLAT]
6837 19:23:03.563055 Freq=400, CH1 RK0
6838 19:23:03.563146
6839 19:23:03.565948 DATLAT Default: 0xf
6840 19:23:03.569385 0, 0xFFFF, sum = 0
6841 19:23:03.569497 1, 0xFFFF, sum = 0
6842 19:23:03.572816 2, 0xFFFF, sum = 0
6843 19:23:03.572895 3, 0xFFFF, sum = 0
6844 19:23:03.576202 4, 0xFFFF, sum = 0
6845 19:23:03.576315 5, 0xFFFF, sum = 0
6846 19:23:03.579325 6, 0xFFFF, sum = 0
6847 19:23:03.579432 7, 0xFFFF, sum = 0
6848 19:23:03.582914 8, 0xFFFF, sum = 0
6849 19:23:03.582996 9, 0xFFFF, sum = 0
6850 19:23:03.586336 10, 0xFFFF, sum = 0
6851 19:23:03.586449 11, 0xFFFF, sum = 0
6852 19:23:03.589085 12, 0xFFFF, sum = 0
6853 19:23:03.589222 13, 0x0, sum = 1
6854 19:23:03.592720 14, 0x0, sum = 2
6855 19:23:03.592832 15, 0x0, sum = 3
6856 19:23:03.596467 16, 0x0, sum = 4
6857 19:23:03.596586 best_step = 14
6858 19:23:03.596684
6859 19:23:03.596784 ==
6860 19:23:03.599349 Dram Type= 6, Freq= 0, CH_1, rank 0
6861 19:23:03.602879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6862 19:23:03.605909 ==
6863 19:23:03.606004 RX Vref Scan: 1
6864 19:23:03.606072
6865 19:23:03.609544 RX Vref 0 -> 0, step: 1
6866 19:23:03.609664
6867 19:23:03.612516 RX Delay -359 -> 252, step: 8
6868 19:23:03.612635
6869 19:23:03.616189 Set Vref, RX VrefLevel [Byte0]: 59
6870 19:23:03.616309 [Byte1]: 53
6871 19:23:03.622178
6872 19:23:03.622292 Final RX Vref Byte 0 = 59 to rank0
6873 19:23:03.625061 Final RX Vref Byte 1 = 53 to rank0
6874 19:23:03.628313 Final RX Vref Byte 0 = 59 to rank1
6875 19:23:03.632026 Final RX Vref Byte 1 = 53 to rank1==
6876 19:23:03.634983 Dram Type= 6, Freq= 0, CH_1, rank 0
6877 19:23:03.641632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6878 19:23:03.641773 ==
6879 19:23:03.641873 DQS Delay:
6880 19:23:03.641962 DQS0 = 48, DQS1 = 60
6881 19:23:03.645130 DQM Delay:
6882 19:23:03.645282 DQM0 = 12, DQM1 = 13
6883 19:23:03.648591 DQ Delay:
6884 19:23:03.651669 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6885 19:23:03.651782 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =8
6886 19:23:03.655192 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =12
6887 19:23:03.658596 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6888 19:23:03.658690
6889 19:23:03.658782
6890 19:23:03.668564 [DQSOSCAuto] RK0, (LSB)MR18= 0x8e33, (MSB)MR19= 0xc0c, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
6891 19:23:03.671649 CH1 RK0: MR19=C0C, MR18=8E33
6892 19:23:03.678237 CH1_RK0: MR19=0xC0C, MR18=0x8E33, DQSOSC=392, MR23=63, INC=384, DEC=256
6893 19:23:03.678393 ==
6894 19:23:03.681983 Dram Type= 6, Freq= 0, CH_1, rank 1
6895 19:23:03.684973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6896 19:23:03.685077 ==
6897 19:23:03.688296 [Gating] SW mode calibration
6898 19:23:03.695159 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6899 19:23:03.698555 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6900 19:23:03.705002 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6901 19:23:03.708607 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6902 19:23:03.711582 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6903 19:23:03.718164 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6904 19:23:03.721796 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6905 19:23:03.725260 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6906 19:23:03.732153 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6907 19:23:03.734838 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6908 19:23:03.738248 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6909 19:23:03.741784 Total UI for P1: 0, mck2ui 16
6910 19:23:03.744786 best dqsien dly found for B0: ( 0, 14, 24)
6911 19:23:03.748377 Total UI for P1: 0, mck2ui 16
6912 19:23:03.751352 best dqsien dly found for B1: ( 0, 14, 24)
6913 19:23:03.754923 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6914 19:23:03.758040 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6915 19:23:03.758135
6916 19:23:03.764991 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6917 19:23:03.768181 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6918 19:23:03.771934 [Gating] SW calibration Done
6919 19:23:03.772058 ==
6920 19:23:03.774999 Dram Type= 6, Freq= 0, CH_1, rank 1
6921 19:23:03.778038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6922 19:23:03.778148 ==
6923 19:23:03.778253 RX Vref Scan: 0
6924 19:23:03.778344
6925 19:23:03.781872 RX Vref 0 -> 0, step: 1
6926 19:23:03.781982
6927 19:23:03.784944 RX Delay -410 -> 252, step: 16
6928 19:23:03.788506 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6929 19:23:03.791625 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6930 19:23:03.798385 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6931 19:23:03.801843 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6932 19:23:03.805299 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6933 19:23:03.808283 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6934 19:23:03.815348 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6935 19:23:03.818277 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6936 19:23:03.821642 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6937 19:23:03.825183 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6938 19:23:03.831593 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6939 19:23:03.835277 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6940 19:23:03.838203 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6941 19:23:03.841588 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6942 19:23:03.848639 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6943 19:23:03.851728 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6944 19:23:03.851823 ==
6945 19:23:03.855071 Dram Type= 6, Freq= 0, CH_1, rank 1
6946 19:23:03.858690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6947 19:23:03.858779 ==
6948 19:23:03.861688 DQS Delay:
6949 19:23:03.861765 DQS0 = 51, DQS1 = 59
6950 19:23:03.865099 DQM Delay:
6951 19:23:03.865232 DQM0 = 17, DQM1 = 19
6952 19:23:03.865339 DQ Delay:
6953 19:23:03.868333 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =16
6954 19:23:03.871993 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6955 19:23:03.875065 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6956 19:23:03.878695 DQ12 =24, DQ13 =32, DQ14 =24, DQ15 =32
6957 19:23:03.878827
6958 19:23:03.878950
6959 19:23:03.879069 ==
6960 19:23:03.881721 Dram Type= 6, Freq= 0, CH_1, rank 1
6961 19:23:03.888255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6962 19:23:03.888356 ==
6963 19:23:03.888422
6964 19:23:03.888482
6965 19:23:03.888542 TX Vref Scan disable
6966 19:23:03.891936 == TX Byte 0 ==
6967 19:23:03.895505 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6968 19:23:03.898561 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6969 19:23:03.902319 == TX Byte 1 ==
6970 19:23:03.905305 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6971 19:23:03.908841 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6972 19:23:03.908974 ==
6973 19:23:03.911644 Dram Type= 6, Freq= 0, CH_1, rank 1
6974 19:23:03.918283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6975 19:23:03.918422 ==
6976 19:23:03.918522
6977 19:23:03.918614
6978 19:23:03.918708 TX Vref Scan disable
6979 19:23:03.921972 == TX Byte 0 ==
6980 19:23:03.925344 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6981 19:23:03.928660 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6982 19:23:03.931772 == TX Byte 1 ==
6983 19:23:03.935124 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6984 19:23:03.938712 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6985 19:23:03.938801
6986 19:23:03.942589 [DATLAT]
6987 19:23:03.942704 Freq=400, CH1 RK1
6988 19:23:03.942774
6989 19:23:03.945314 DATLAT Default: 0xe
6990 19:23:03.945394 0, 0xFFFF, sum = 0
6991 19:23:03.948436 1, 0xFFFF, sum = 0
6992 19:23:03.948545 2, 0xFFFF, sum = 0
6993 19:23:03.951758 3, 0xFFFF, sum = 0
6994 19:23:03.951870 4, 0xFFFF, sum = 0
6995 19:23:03.954993 5, 0xFFFF, sum = 0
6996 19:23:03.955102 6, 0xFFFF, sum = 0
6997 19:23:03.958670 7, 0xFFFF, sum = 0
6998 19:23:03.958798 8, 0xFFFF, sum = 0
6999 19:23:03.961614 9, 0xFFFF, sum = 0
7000 19:23:03.961729 10, 0xFFFF, sum = 0
7001 19:23:03.965137 11, 0xFFFF, sum = 0
7002 19:23:03.965258 12, 0xFFFF, sum = 0
7003 19:23:03.968595 13, 0x0, sum = 1
7004 19:23:03.968708 14, 0x0, sum = 2
7005 19:23:03.972117 15, 0x0, sum = 3
7006 19:23:03.972230 16, 0x0, sum = 4
7007 19:23:03.975154 best_step = 14
7008 19:23:03.975261
7009 19:23:03.975356 ==
7010 19:23:03.978322 Dram Type= 6, Freq= 0, CH_1, rank 1
7011 19:23:03.981974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7012 19:23:03.982060 ==
7013 19:23:03.985553 RX Vref Scan: 0
7014 19:23:03.985637
7015 19:23:03.985707 RX Vref 0 -> 0, step: 1
7016 19:23:03.985768
7017 19:23:03.988557 RX Delay -359 -> 252, step: 8
7018 19:23:03.996432 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
7019 19:23:04.000098 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
7020 19:23:04.003084 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
7021 19:23:04.006197 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
7022 19:23:04.013322 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
7023 19:23:04.016260 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
7024 19:23:04.019994 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
7025 19:23:04.023080 iDelay=217, Bit 7, Center -40 (-279 ~ 200) 480
7026 19:23:04.029766 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
7027 19:23:04.032822 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
7028 19:23:04.036356 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
7029 19:23:04.039842 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
7030 19:23:04.046209 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
7031 19:23:04.049774 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
7032 19:23:04.053009 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
7033 19:23:04.059855 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
7034 19:23:04.059996 ==
7035 19:23:04.062906 Dram Type= 6, Freq= 0, CH_1, rank 1
7036 19:23:04.066580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7037 19:23:04.066699 ==
7038 19:23:04.066797 DQS Delay:
7039 19:23:04.069681 DQS0 = 52, DQS1 = 56
7040 19:23:04.069803 DQM Delay:
7041 19:23:04.073114 DQM0 = 14, DQM1 = 9
7042 19:23:04.073256 DQ Delay:
7043 19:23:04.076463 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
7044 19:23:04.079887 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =12
7045 19:23:04.083121 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
7046 19:23:04.086846 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
7047 19:23:04.086959
7048 19:23:04.087083
7049 19:23:04.093096 [DQSOSCAuto] RK1, (LSB)MR18= 0x768b, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 394 ps
7050 19:23:04.096709 CH1 RK1: MR19=C0C, MR18=768B
7051 19:23:04.103219 CH1_RK1: MR19=0xC0C, MR18=0x768B, DQSOSC=392, MR23=63, INC=384, DEC=256
7052 19:23:04.106774 [RxdqsGatingPostProcess] freq 400
7053 19:23:04.109917 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7054 19:23:04.113630 best DQS0 dly(2T, 0.5T) = (0, 10)
7055 19:23:04.116450 best DQS1 dly(2T, 0.5T) = (0, 10)
7056 19:23:04.120046 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7057 19:23:04.123720 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7058 19:23:04.126893 best DQS0 dly(2T, 0.5T) = (0, 10)
7059 19:23:04.129898 best DQS1 dly(2T, 0.5T) = (0, 10)
7060 19:23:04.133614 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7061 19:23:04.136866 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7062 19:23:04.139677 Pre-setting of DQS Precalculation
7063 19:23:04.143145 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7064 19:23:04.153451 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7065 19:23:04.160031 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7066 19:23:04.160219
7067 19:23:04.160315
7068 19:23:04.163072 [Calibration Summary] 800 Mbps
7069 19:23:04.163171 CH 0, Rank 0
7070 19:23:04.166726 SW Impedance : PASS
7071 19:23:04.166826 DUTY Scan : NO K
7072 19:23:04.169688 ZQ Calibration : PASS
7073 19:23:04.173031 Jitter Meter : NO K
7074 19:23:04.173132 CBT Training : PASS
7075 19:23:04.176227 Write leveling : PASS
7076 19:23:04.179828 RX DQS gating : PASS
7077 19:23:04.179939 RX DQ/DQS(RDDQC) : PASS
7078 19:23:04.183059 TX DQ/DQS : PASS
7079 19:23:04.183167 RX DATLAT : PASS
7080 19:23:04.186424 RX DQ/DQS(Engine): PASS
7081 19:23:04.189839 TX OE : NO K
7082 19:23:04.189959 All Pass.
7083 19:23:04.190056
7084 19:23:04.190147 CH 0, Rank 1
7085 19:23:04.193269 SW Impedance : PASS
7086 19:23:04.196503 DUTY Scan : NO K
7087 19:23:04.196610 ZQ Calibration : PASS
7088 19:23:04.199579 Jitter Meter : NO K
7089 19:23:04.203347 CBT Training : PASS
7090 19:23:04.203470 Write leveling : NO K
7091 19:23:04.206165 RX DQS gating : PASS
7092 19:23:04.209819 RX DQ/DQS(RDDQC) : PASS
7093 19:23:04.209930 TX DQ/DQS : PASS
7094 19:23:04.212822 RX DATLAT : PASS
7095 19:23:04.216512 RX DQ/DQS(Engine): PASS
7096 19:23:04.216625 TX OE : NO K
7097 19:23:04.219711 All Pass.
7098 19:23:04.219817
7099 19:23:04.219910 CH 1, Rank 0
7100 19:23:04.223189 SW Impedance : PASS
7101 19:23:04.223300 DUTY Scan : NO K
7102 19:23:04.226500 ZQ Calibration : PASS
7103 19:23:04.229515 Jitter Meter : NO K
7104 19:23:04.229623 CBT Training : PASS
7105 19:23:04.233205 Write leveling : PASS
7106 19:23:04.233346 RX DQS gating : PASS
7107 19:23:04.236184 RX DQ/DQS(RDDQC) : PASS
7108 19:23:04.239435 TX DQ/DQS : PASS
7109 19:23:04.239544 RX DATLAT : PASS
7110 19:23:04.243191 RX DQ/DQS(Engine): PASS
7111 19:23:04.246134 TX OE : NO K
7112 19:23:04.246243 All Pass.
7113 19:23:04.246339
7114 19:23:04.246435 CH 1, Rank 1
7115 19:23:04.249647 SW Impedance : PASS
7116 19:23:04.253375 DUTY Scan : NO K
7117 19:23:04.253486 ZQ Calibration : PASS
7118 19:23:04.256416 Jitter Meter : NO K
7119 19:23:04.259925 CBT Training : PASS
7120 19:23:04.260046 Write leveling : NO K
7121 19:23:04.262979 RX DQS gating : PASS
7122 19:23:04.266645 RX DQ/DQS(RDDQC) : PASS
7123 19:23:04.266763 TX DQ/DQS : PASS
7124 19:23:04.269818 RX DATLAT : PASS
7125 19:23:04.269924 RX DQ/DQS(Engine): PASS
7126 19:23:04.272894 TX OE : NO K
7127 19:23:04.272994 All Pass.
7128 19:23:04.273084
7129 19:23:04.276529 DramC Write-DBI off
7130 19:23:04.279588 PER_BANK_REFRESH: Hybrid Mode
7131 19:23:04.279696 TX_TRACKING: ON
7132 19:23:04.289801 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7133 19:23:04.293163 [FAST_K] Save calibration result to emmc
7134 19:23:04.296397 dramc_set_vcore_voltage set vcore to 725000
7135 19:23:04.300105 Read voltage for 1600, 0
7136 19:23:04.300221 Vio18 = 0
7137 19:23:04.300333 Vcore = 725000
7138 19:23:04.303507 Vdram = 0
7139 19:23:04.303609 Vddq = 0
7140 19:23:04.303702 Vmddr = 0
7141 19:23:04.309832 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7142 19:23:04.313311 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7143 19:23:04.316483 MEM_TYPE=3, freq_sel=13
7144 19:23:04.319632 sv_algorithm_assistance_LP4_3733
7145 19:23:04.323336 ============ PULL DRAM RESETB DOWN ============
7146 19:23:04.329860 ========== PULL DRAM RESETB DOWN end =========
7147 19:23:04.333524 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7148 19:23:04.336524 ===================================
7149 19:23:04.340182 LPDDR4 DRAM CONFIGURATION
7150 19:23:04.343286 ===================================
7151 19:23:04.343412 EX_ROW_EN[0] = 0x0
7152 19:23:04.346980 EX_ROW_EN[1] = 0x0
7153 19:23:04.347096 LP4Y_EN = 0x0
7154 19:23:04.349938 WORK_FSP = 0x1
7155 19:23:04.350048 WL = 0x5
7156 19:23:04.353002 RL = 0x5
7157 19:23:04.353115 BL = 0x2
7158 19:23:04.356341 RPST = 0x0
7159 19:23:04.356455 RD_PRE = 0x0
7160 19:23:04.359984 WR_PRE = 0x1
7161 19:23:04.360083 WR_PST = 0x1
7162 19:23:04.363082 DBI_WR = 0x0
7163 19:23:04.363174 DBI_RD = 0x0
7164 19:23:04.366667 OTF = 0x1
7165 19:23:04.369640 ===================================
7166 19:23:04.373395 ===================================
7167 19:23:04.373495 ANA top config
7168 19:23:04.376360 ===================================
7169 19:23:04.379614 DLL_ASYNC_EN = 0
7170 19:23:04.383198 ALL_SLAVE_EN = 0
7171 19:23:04.386400 NEW_RANK_MODE = 1
7172 19:23:04.386499 DLL_IDLE_MODE = 1
7173 19:23:04.389769 LP45_APHY_COMB_EN = 1
7174 19:23:04.393345 TX_ODT_DIS = 0
7175 19:23:04.396329 NEW_8X_MODE = 1
7176 19:23:04.399693 ===================================
7177 19:23:04.402864 ===================================
7178 19:23:04.406585 data_rate = 3200
7179 19:23:04.409674 CKR = 1
7180 19:23:04.409786 DQ_P2S_RATIO = 8
7181 19:23:04.412837 ===================================
7182 19:23:04.415885 CA_P2S_RATIO = 8
7183 19:23:04.419634 DQ_CA_OPEN = 0
7184 19:23:04.422950 DQ_SEMI_OPEN = 0
7185 19:23:04.426285 CA_SEMI_OPEN = 0
7186 19:23:04.429444 CA_FULL_RATE = 0
7187 19:23:04.429541 DQ_CKDIV4_EN = 0
7188 19:23:04.433112 CA_CKDIV4_EN = 0
7189 19:23:04.435943 CA_PREDIV_EN = 0
7190 19:23:04.439214 PH8_DLY = 12
7191 19:23:04.442780 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7192 19:23:04.446053 DQ_AAMCK_DIV = 4
7193 19:23:04.446182 CA_AAMCK_DIV = 4
7194 19:23:04.449570 CA_ADMCK_DIV = 4
7195 19:23:04.452513 DQ_TRACK_CA_EN = 0
7196 19:23:04.455826 CA_PICK = 1600
7197 19:23:04.459458 CA_MCKIO = 1600
7198 19:23:04.462408 MCKIO_SEMI = 0
7199 19:23:04.466022 PLL_FREQ = 3068
7200 19:23:04.466112 DQ_UI_PI_RATIO = 32
7201 19:23:04.469011 CA_UI_PI_RATIO = 0
7202 19:23:04.472552 ===================================
7203 19:23:04.475586 ===================================
7204 19:23:04.479095 memory_type:LPDDR4
7205 19:23:04.482308 GP_NUM : 10
7206 19:23:04.482428 SRAM_EN : 1
7207 19:23:04.486020 MD32_EN : 0
7208 19:23:04.489062 ===================================
7209 19:23:04.492517 [ANA_INIT] >>>>>>>>>>>>>>
7210 19:23:04.492643 <<<<<< [CONFIGURE PHASE]: ANA_TX
7211 19:23:04.495648 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7212 19:23:04.499378 ===================================
7213 19:23:04.502310 data_rate = 3200,PCW = 0X7600
7214 19:23:04.505785 ===================================
7215 19:23:04.508895 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7216 19:23:04.515701 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7217 19:23:04.522529 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7218 19:23:04.525547 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7219 19:23:04.529057 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7220 19:23:04.532271 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7221 19:23:04.535937 [ANA_INIT] flow start
7222 19:23:04.536054 [ANA_INIT] PLL >>>>>>>>
7223 19:23:04.538896 [ANA_INIT] PLL <<<<<<<<
7224 19:23:04.542472 [ANA_INIT] MIDPI >>>>>>>>
7225 19:23:04.542574 [ANA_INIT] MIDPI <<<<<<<<
7226 19:23:04.546099 [ANA_INIT] DLL >>>>>>>>
7227 19:23:04.549138 [ANA_INIT] DLL <<<<<<<<
7228 19:23:04.549280 [ANA_INIT] flow end
7229 19:23:04.557512 ============ LP4 DIFF to SE enter ============
7230 19:23:04.558947 ============ LP4 DIFF to SE exit ============
7231 19:23:04.559044 [ANA_INIT] <<<<<<<<<<<<<
7232 19:23:04.562407 [Flow] Enable top DCM control >>>>>
7233 19:23:04.565557 [Flow] Enable top DCM control <<<<<
7234 19:23:04.569523 Enable DLL master slave shuffle
7235 19:23:04.575916 ==============================================================
7236 19:23:04.579379 Gating Mode config
7237 19:23:04.582579 ==============================================================
7238 19:23:04.586146 Config description:
7239 19:23:04.595941 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7240 19:23:04.602569 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7241 19:23:04.606174 SELPH_MODE 0: By rank 1: By Phase
7242 19:23:04.613105 ==============================================================
7243 19:23:04.616304 GAT_TRACK_EN = 1
7244 19:23:04.616411 RX_GATING_MODE = 2
7245 19:23:04.619346 RX_GATING_TRACK_MODE = 2
7246 19:23:04.622581 SELPH_MODE = 1
7247 19:23:04.626283 PICG_EARLY_EN = 1
7248 19:23:04.629285 VALID_LAT_VALUE = 1
7249 19:23:04.636007 ==============================================================
7250 19:23:04.639561 Enter into Gating configuration >>>>
7251 19:23:04.642579 Exit from Gating configuration <<<<
7252 19:23:04.646177 Enter into DVFS_PRE_config >>>>>
7253 19:23:04.656460 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7254 19:23:04.659546 Exit from DVFS_PRE_config <<<<<
7255 19:23:04.662563 Enter into PICG configuration >>>>
7256 19:23:04.666285 Exit from PICG configuration <<<<
7257 19:23:04.669359 [RX_INPUT] configuration >>>>>
7258 19:23:04.669477 [RX_INPUT] configuration <<<<<
7259 19:23:04.676373 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7260 19:23:04.683029 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7261 19:23:04.686183 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7262 19:23:04.692749 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7263 19:23:04.699853 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7264 19:23:04.706148 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7265 19:23:04.709375 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7266 19:23:04.712840 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7267 19:23:04.719645 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7268 19:23:04.723235 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7269 19:23:04.726271 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7270 19:23:04.733104 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7271 19:23:04.736106 ===================================
7272 19:23:04.736195 LPDDR4 DRAM CONFIGURATION
7273 19:23:04.739825 ===================================
7274 19:23:04.742916 EX_ROW_EN[0] = 0x0
7275 19:23:04.743001 EX_ROW_EN[1] = 0x0
7276 19:23:04.746046 LP4Y_EN = 0x0
7277 19:23:04.746128 WORK_FSP = 0x1
7278 19:23:04.749835 WL = 0x5
7279 19:23:04.749918 RL = 0x5
7280 19:23:04.752901 BL = 0x2
7281 19:23:04.752984 RPST = 0x0
7282 19:23:04.756382 RD_PRE = 0x0
7283 19:23:04.756466 WR_PRE = 0x1
7284 19:23:04.759534 WR_PST = 0x1
7285 19:23:04.763157 DBI_WR = 0x0
7286 19:23:04.763241 DBI_RD = 0x0
7287 19:23:04.766290 OTF = 0x1
7288 19:23:04.769343 ===================================
7289 19:23:04.773110 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7290 19:23:04.776274 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7291 19:23:04.779836 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7292 19:23:04.782951 ===================================
7293 19:23:04.786542 LPDDR4 DRAM CONFIGURATION
7294 19:23:04.789560 ===================================
7295 19:23:04.793258 EX_ROW_EN[0] = 0x10
7296 19:23:04.793341 EX_ROW_EN[1] = 0x0
7297 19:23:04.796445 LP4Y_EN = 0x0
7298 19:23:04.796528 WORK_FSP = 0x1
7299 19:23:04.799907 WL = 0x5
7300 19:23:04.799989 RL = 0x5
7301 19:23:04.802702 BL = 0x2
7302 19:23:04.802818 RPST = 0x0
7303 19:23:04.806087 RD_PRE = 0x0
7304 19:23:04.806172 WR_PRE = 0x1
7305 19:23:04.809885 WR_PST = 0x1
7306 19:23:04.809984 DBI_WR = 0x0
7307 19:23:04.813105 DBI_RD = 0x0
7308 19:23:04.813188 OTF = 0x1
7309 19:23:04.816483 ===================================
7310 19:23:04.823385 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7311 19:23:04.823474 ==
7312 19:23:04.826616 Dram Type= 6, Freq= 0, CH_0, rank 0
7313 19:23:04.833245 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7314 19:23:04.833334 ==
7315 19:23:04.833410 [Duty_Offset_Calibration]
7316 19:23:04.836235 B0:2 B1:-1 CA:1
7317 19:23:04.836321
7318 19:23:04.839475 [DutyScan_Calibration_Flow] k_type=0
7319 19:23:04.847887
7320 19:23:04.847975 ==CLK 0==
7321 19:23:04.851481 Final CLK duty delay cell = -4
7322 19:23:04.854716 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7323 19:23:04.858203 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7324 19:23:04.861280 [-4] AVG Duty = 4937%(X100)
7325 19:23:04.861364
7326 19:23:04.865025 CH0 CLK Duty spec in!! Max-Min= 187%
7327 19:23:04.868069 [DutyScan_Calibration_Flow] ====Done====
7328 19:23:04.868182
7329 19:23:04.871076 [DutyScan_Calibration_Flow] k_type=1
7330 19:23:04.887777
7331 19:23:04.887868 ==DQS 0 ==
7332 19:23:04.890814 Final DQS duty delay cell = 0
7333 19:23:04.894628 [0] MAX Duty = 5125%(X100), DQS PI = 56
7334 19:23:04.897560 [0] MIN Duty = 5000%(X100), DQS PI = 16
7335 19:23:04.897645 [0] AVG Duty = 5062%(X100)
7336 19:23:04.900677
7337 19:23:04.900774 ==DQS 1 ==
7338 19:23:04.904089 Final DQS duty delay cell = -4
7339 19:23:04.907907 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7340 19:23:04.910738 [-4] MIN Duty = 5000%(X100), DQS PI = 40
7341 19:23:04.914256 [-4] AVG Duty = 5046%(X100)
7342 19:23:04.914339
7343 19:23:04.917874 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7344 19:23:04.917960
7345 19:23:04.921198 CH0 DQS 1 Duty spec in!! Max-Min= 93%
7346 19:23:04.924225 [DutyScan_Calibration_Flow] ====Done====
7347 19:23:04.924311
7348 19:23:04.927935 [DutyScan_Calibration_Flow] k_type=3
7349 19:23:04.945051
7350 19:23:04.945190 ==DQM 0 ==
7351 19:23:04.948156 Final DQM duty delay cell = 0
7352 19:23:04.951524 [0] MAX Duty = 5000%(X100), DQS PI = 18
7353 19:23:04.955017 [0] MIN Duty = 4875%(X100), DQS PI = 4
7354 19:23:04.955102 [0] AVG Duty = 4937%(X100)
7355 19:23:04.957949
7356 19:23:04.958033 ==DQM 1 ==
7357 19:23:04.961651 Final DQM duty delay cell = 0
7358 19:23:04.965116 [0] MAX Duty = 5218%(X100), DQS PI = 60
7359 19:23:04.968334 [0] MIN Duty = 4969%(X100), DQS PI = 20
7360 19:23:04.971325 [0] AVG Duty = 5093%(X100)
7361 19:23:04.971408
7362 19:23:04.975052 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7363 19:23:04.975136
7364 19:23:04.978147 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7365 19:23:04.981780 [DutyScan_Calibration_Flow] ====Done====
7366 19:23:04.981862
7367 19:23:04.984919 [DutyScan_Calibration_Flow] k_type=2
7368 19:23:05.001449
7369 19:23:05.001565 ==DQ 0 ==
7370 19:23:05.004405 Final DQ duty delay cell = -4
7371 19:23:05.007955 [-4] MAX Duty = 5000%(X100), DQS PI = 0
7372 19:23:05.011229 [-4] MIN Duty = 4844%(X100), DQS PI = 12
7373 19:23:05.011311 [-4] AVG Duty = 4922%(X100)
7374 19:23:05.014632
7375 19:23:05.014714 ==DQ 1 ==
7376 19:23:05.017716 Final DQ duty delay cell = 0
7377 19:23:05.021400 [0] MAX Duty = 5031%(X100), DQS PI = 30
7378 19:23:05.024781 [0] MIN Duty = 4907%(X100), DQS PI = 18
7379 19:23:05.024895 [0] AVG Duty = 4969%(X100)
7380 19:23:05.028198
7381 19:23:05.031447 CH0 DQ 0 Duty spec in!! Max-Min= 156%
7382 19:23:05.031547
7383 19:23:05.034732 CH0 DQ 1 Duty spec in!! Max-Min= 124%
7384 19:23:05.038333 [DutyScan_Calibration_Flow] ====Done====
7385 19:23:05.038414 ==
7386 19:23:05.041349 Dram Type= 6, Freq= 0, CH_1, rank 0
7387 19:23:05.044978 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7388 19:23:05.045082 ==
7389 19:23:05.047781 [Duty_Offset_Calibration]
7390 19:23:05.047881 B0:1 B1:1 CA:2
7391 19:23:05.047971
7392 19:23:05.051571 [DutyScan_Calibration_Flow] k_type=0
7393 19:23:05.061607
7394 19:23:05.061685 ==CLK 0==
7395 19:23:05.065387 Final CLK duty delay cell = 0
7396 19:23:05.068552 [0] MAX Duty = 5187%(X100), DQS PI = 24
7397 19:23:05.071661 [0] MIN Duty = 4969%(X100), DQS PI = 40
7398 19:23:05.071762 [0] AVG Duty = 5078%(X100)
7399 19:23:05.075236
7400 19:23:05.078307 CH1 CLK Duty spec in!! Max-Min= 218%
7401 19:23:05.081635 [DutyScan_Calibration_Flow] ====Done====
7402 19:23:05.081721
7403 19:23:05.085371 [DutyScan_Calibration_Flow] k_type=1
7404 19:23:05.101928
7405 19:23:05.102011 ==DQS 0 ==
7406 19:23:05.104575 Final DQS duty delay cell = 0
7407 19:23:05.108376 [0] MAX Duty = 5062%(X100), DQS PI = 22
7408 19:23:05.111502 [0] MIN Duty = 4813%(X100), DQS PI = 50
7409 19:23:05.115066 [0] AVG Duty = 4937%(X100)
7410 19:23:05.115194
7411 19:23:05.115278 ==DQS 1 ==
7412 19:23:05.118174 Final DQS duty delay cell = 0
7413 19:23:05.121367 [0] MAX Duty = 5031%(X100), DQS PI = 34
7414 19:23:05.124730 [0] MIN Duty = 4938%(X100), DQS PI = 12
7415 19:23:05.124813 [0] AVG Duty = 4984%(X100)
7416 19:23:05.128082
7417 19:23:05.131682 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7418 19:23:05.131764
7419 19:23:05.135061 CH1 DQS 1 Duty spec in!! Max-Min= 93%
7420 19:23:05.137899 [DutyScan_Calibration_Flow] ====Done====
7421 19:23:05.137981
7422 19:23:05.141197 [DutyScan_Calibration_Flow] k_type=3
7423 19:23:05.158534
7424 19:23:05.158638 ==DQM 0 ==
7425 19:23:05.161540 Final DQM duty delay cell = 0
7426 19:23:05.165152 [0] MAX Duty = 5156%(X100), DQS PI = 20
7427 19:23:05.168375 [0] MIN Duty = 4813%(X100), DQS PI = 50
7428 19:23:05.171540 [0] AVG Duty = 4984%(X100)
7429 19:23:05.171621
7430 19:23:05.171686 ==DQM 1 ==
7431 19:23:05.175207 Final DQM duty delay cell = 0
7432 19:23:05.178383 [0] MAX Duty = 5156%(X100), DQS PI = 60
7433 19:23:05.181468 [0] MIN Duty = 4907%(X100), DQS PI = 18
7434 19:23:05.185477 [0] AVG Duty = 5031%(X100)
7435 19:23:05.185559
7436 19:23:05.188255 CH1 DQM 0 Duty spec in!! Max-Min= 343%
7437 19:23:05.188341
7438 19:23:05.191764 CH1 DQM 1 Duty spec in!! Max-Min= 249%
7439 19:23:05.195352 [DutyScan_Calibration_Flow] ====Done====
7440 19:23:05.195474
7441 19:23:05.198540 [DutyScan_Calibration_Flow] k_type=2
7442 19:23:05.215177
7443 19:23:05.215270 ==DQ 0 ==
7444 19:23:05.218429 Final DQ duty delay cell = 0
7445 19:23:05.222070 [0] MAX Duty = 5125%(X100), DQS PI = 18
7446 19:23:05.225173 [0] MIN Duty = 4907%(X100), DQS PI = 52
7447 19:23:05.225282 [0] AVG Duty = 5016%(X100)
7448 19:23:05.228688
7449 19:23:05.228770 ==DQ 1 ==
7450 19:23:05.231861 Final DQ duty delay cell = 0
7451 19:23:05.235333 [0] MAX Duty = 5093%(X100), DQS PI = 6
7452 19:23:05.238962 [0] MIN Duty = 5031%(X100), DQS PI = 0
7453 19:23:05.239045 [0] AVG Duty = 5062%(X100)
7454 19:23:05.239108
7455 19:23:05.242097 CH1 DQ 0 Duty spec in!! Max-Min= 218%
7456 19:23:05.242182
7457 19:23:05.245219 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7458 19:23:05.252150 [DutyScan_Calibration_Flow] ====Done====
7459 19:23:05.255516 nWR fixed to 30
7460 19:23:05.255599 [ModeRegInit_LP4] CH0 RK0
7461 19:23:05.258702 [ModeRegInit_LP4] CH0 RK1
7462 19:23:05.262119 [ModeRegInit_LP4] CH1 RK0
7463 19:23:05.262202 [ModeRegInit_LP4] CH1 RK1
7464 19:23:05.265396 match AC timing 5
7465 19:23:05.268827 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7466 19:23:05.271820 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7467 19:23:05.278604 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7468 19:23:05.282330 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7469 19:23:05.288548 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7470 19:23:05.288641 [MiockJmeterHQA]
7471 19:23:05.288706
7472 19:23:05.291669 [DramcMiockJmeter] u1RxGatingPI = 0
7473 19:23:05.291751 0 : 4253, 4027
7474 19:23:05.295348 4 : 4252, 4027
7475 19:23:05.295431 8 : 4366, 4140
7476 19:23:05.298362 12 : 4363, 4138
7477 19:23:05.298446 16 : 4363, 4137
7478 19:23:05.301861 20 : 4253, 4027
7479 19:23:05.301947 24 : 4253, 4026
7480 19:23:05.302015 28 : 4252, 4027
7481 19:23:05.305334 32 : 4252, 4027
7482 19:23:05.305409 36 : 4255, 4029
7483 19:23:05.308620 40 : 4363, 4137
7484 19:23:05.308723 44 : 4253, 4026
7485 19:23:05.311851 48 : 4252, 4027
7486 19:23:05.311953 52 : 4249, 4027
7487 19:23:05.315552 56 : 4253, 4029
7488 19:23:05.315675 60 : 4250, 4027
7489 19:23:05.315770 64 : 4360, 4137
7490 19:23:05.318599 68 : 4361, 4137
7491 19:23:05.318714 72 : 4249, 4027
7492 19:23:05.321891 76 : 4252, 4029
7493 19:23:05.321997 80 : 4250, 4027
7494 19:23:05.325494 84 : 4249, 4027
7495 19:23:05.325601 88 : 4253, 4029
7496 19:23:05.328483 92 : 4360, 4138
7497 19:23:05.328589 96 : 4250, 3036
7498 19:23:05.328684 100 : 4250, 0
7499 19:23:05.332271 104 : 4250, 0
7500 19:23:05.332351 108 : 4250, 0
7501 19:23:05.335439 112 : 4250, 0
7502 19:23:05.335539 116 : 4253, 0
7503 19:23:05.335632 120 : 4252, 0
7504 19:23:05.339014 124 : 4250, 0
7505 19:23:05.339123 128 : 4253, 0
7506 19:23:05.339217 132 : 4360, 0
7507 19:23:05.342195 136 : 4360, 0
7508 19:23:05.342296 140 : 4250, 0
7509 19:23:05.345357 144 : 4253, 0
7510 19:23:05.345464 148 : 4250, 0
7511 19:23:05.345549 152 : 4250, 0
7512 19:23:05.348906 156 : 4253, 0
7513 19:23:05.349014 160 : 4249, 0
7514 19:23:05.351896 164 : 4250, 0
7515 19:23:05.352000 168 : 4253, 0
7516 19:23:05.352095 172 : 4249, 0
7517 19:23:05.355415 176 : 4361, 0
7518 19:23:05.355516 180 : 4250, 0
7519 19:23:05.355606 184 : 4360, 0
7520 19:23:05.358873 188 : 4360, 0
7521 19:23:05.358983 192 : 4363, 0
7522 19:23:05.361871 196 : 4253, 0
7523 19:23:05.361985 200 : 4360, 0
7524 19:23:05.362082 204 : 4250, 0
7525 19:23:05.365277 208 : 4250, 0
7526 19:23:05.365365 212 : 4249, 95
7527 19:23:05.369192 216 : 4363, 3764
7528 19:23:05.369368 220 : 4250, 4027
7529 19:23:05.372018 224 : 4249, 4027
7530 19:23:05.372131 228 : 4250, 4026
7531 19:23:05.375478 232 : 4253, 4029
7532 19:23:05.375590 236 : 4250, 4027
7533 19:23:05.375686 240 : 4249, 4027
7534 19:23:05.378789 244 : 4360, 4137
7535 19:23:05.378906 248 : 4250, 4026
7536 19:23:05.382226 252 : 4250, 4027
7537 19:23:05.382309 256 : 4360, 4138
7538 19:23:05.385360 260 : 4249, 4027
7539 19:23:05.385466 264 : 4250, 4026
7540 19:23:05.388483 268 : 4363, 4140
7541 19:23:05.388586 272 : 4250, 4027
7542 19:23:05.392307 276 : 4249, 4027
7543 19:23:05.392383 280 : 4250, 4026
7544 19:23:05.395353 284 : 4253, 4029
7545 19:23:05.395427 288 : 4250, 4027
7546 19:23:05.398998 292 : 4249, 4027
7547 19:23:05.399102 296 : 4360, 4137
7548 19:23:05.399194 300 : 4250, 4026
7549 19:23:05.402065 304 : 4250, 4027
7550 19:23:05.402176 308 : 4360, 4138
7551 19:23:05.404928 312 : 4249, 4027
7552 19:23:05.405033 316 : 4250, 4026
7553 19:23:05.408560 320 : 4363, 4140
7554 19:23:05.408674 324 : 4250, 4027
7555 19:23:05.411689 328 : 4249, 4027
7556 19:23:05.411805 332 : 4250, 2895
7557 19:23:05.415454 336 : 4253, 36
7558 19:23:05.415593
7559 19:23:05.415719 MIOCK jitter meter ch=0
7560 19:23:05.415824
7561 19:23:05.418476 1T = (336-100) = 236 dly cells
7562 19:23:05.424903 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7563 19:23:05.425016 ==
7564 19:23:05.428222 Dram Type= 6, Freq= 0, CH_0, rank 0
7565 19:23:05.431558 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7566 19:23:05.431672 ==
7567 19:23:05.438068 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7568 19:23:05.441812 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7569 19:23:05.448010 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7570 19:23:05.451567 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7571 19:23:05.461604 [CA 0] Center 44 (14~75) winsize 62
7572 19:23:05.465111 [CA 1] Center 44 (14~74) winsize 61
7573 19:23:05.468349 [CA 2] Center 39 (10~68) winsize 59
7574 19:23:05.471895 [CA 3] Center 39 (10~68) winsize 59
7575 19:23:05.474848 [CA 4] Center 37 (7~67) winsize 61
7576 19:23:05.478253 [CA 5] Center 37 (7~67) winsize 61
7577 19:23:05.478339
7578 19:23:05.481809 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7579 19:23:05.481890
7580 19:23:05.485323 [CATrainingPosCal] consider 1 rank data
7581 19:23:05.488680 u2DelayCellTimex100 = 275/100 ps
7582 19:23:05.491533 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7583 19:23:05.498250 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7584 19:23:05.501453 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7585 19:23:05.505111 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7586 19:23:05.508441 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
7587 19:23:05.511563 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7588 19:23:05.511644
7589 19:23:05.515136 CA PerBit enable=1, Macro0, CA PI delay=37
7590 19:23:05.515245
7591 19:23:05.518309 [CBTSetCACLKResult] CA Dly = 37
7592 19:23:05.521882 CS Dly: 10 (0~41)
7593 19:23:05.525144 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7594 19:23:05.528158 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7595 19:23:05.528272 ==
7596 19:23:05.531694 Dram Type= 6, Freq= 0, CH_0, rank 1
7597 19:23:05.534929 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7598 19:23:05.538554 ==
7599 19:23:05.541618 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7600 19:23:05.545007 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7601 19:23:05.551897 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7602 19:23:05.555279 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7603 19:23:05.565548 [CA 0] Center 43 (13~74) winsize 62
7604 19:23:05.568638 [CA 1] Center 43 (13~74) winsize 62
7605 19:23:05.572288 [CA 2] Center 39 (10~69) winsize 60
7606 19:23:05.575155 [CA 3] Center 38 (9~68) winsize 60
7607 19:23:05.578952 [CA 4] Center 37 (7~67) winsize 61
7608 19:23:05.582237 [CA 5] Center 36 (6~67) winsize 62
7609 19:23:05.582340
7610 19:23:05.585677 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7611 19:23:05.585833
7612 19:23:05.588793 [CATrainingPosCal] consider 2 rank data
7613 19:23:05.592308 u2DelayCellTimex100 = 275/100 ps
7614 19:23:05.595470 CA0 delay=44 (14~74),Diff = 7 PI (24 cell)
7615 19:23:05.602431 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7616 19:23:05.605717 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7617 19:23:05.608965 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7618 19:23:05.612004 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
7619 19:23:05.615591 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7620 19:23:05.615737
7621 19:23:05.618807 CA PerBit enable=1, Macro0, CA PI delay=37
7622 19:23:05.618940
7623 19:23:05.622348 [CBTSetCACLKResult] CA Dly = 37
7624 19:23:05.625475 CS Dly: 11 (0~44)
7625 19:23:05.629108 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7626 19:23:05.632085 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7627 19:23:05.632205
7628 19:23:05.635861 ----->DramcWriteLeveling(PI) begin...
7629 19:23:05.635994 ==
7630 19:23:05.638828 Dram Type= 6, Freq= 0, CH_0, rank 0
7631 19:23:05.642553 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7632 19:23:05.645682 ==
7633 19:23:05.645831 Write leveling (Byte 0): 32 => 32
7634 19:23:05.648845 Write leveling (Byte 1): 28 => 28
7635 19:23:05.652542 DramcWriteLeveling(PI) end<-----
7636 19:23:05.652686
7637 19:23:05.652787 ==
7638 19:23:05.655636 Dram Type= 6, Freq= 0, CH_0, rank 0
7639 19:23:05.662244 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7640 19:23:05.662366 ==
7641 19:23:05.662442 [Gating] SW mode calibration
7642 19:23:05.672418 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7643 19:23:05.675473 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7644 19:23:05.678856 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7645 19:23:05.685406 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7646 19:23:05.689055 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7647 19:23:05.692318 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7648 19:23:05.698902 1 4 16 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
7649 19:23:05.702208 1 4 20 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
7650 19:23:05.705398 1 4 24 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
7651 19:23:05.712025 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7652 19:23:05.715470 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7653 19:23:05.718670 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7654 19:23:05.725739 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7655 19:23:05.728719 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7656 19:23:05.732466 1 5 16 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 1)
7657 19:23:05.738624 1 5 20 | B1->B0 | 3434 2727 | 1 0 | (1 1) (1 0)
7658 19:23:05.742295 1 5 24 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
7659 19:23:05.745361 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7660 19:23:05.752263 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7661 19:23:05.755350 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7662 19:23:05.758926 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7663 19:23:05.762175 1 6 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7664 19:23:05.768899 1 6 16 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
7665 19:23:05.772167 1 6 20 | B1->B0 | 2828 4545 | 0 0 | (0 0) (0 0)
7666 19:23:05.775746 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7667 19:23:05.782297 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7668 19:23:05.785506 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7669 19:23:05.788876 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7670 19:23:05.795516 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7671 19:23:05.799194 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7672 19:23:05.802349 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7673 19:23:05.808696 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7674 19:23:05.811980 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7675 19:23:05.815241 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7676 19:23:05.822462 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7677 19:23:05.825427 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7678 19:23:05.828584 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7679 19:23:05.835524 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7680 19:23:05.838514 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7681 19:23:05.841784 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7682 19:23:05.848554 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7683 19:23:05.852180 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7684 19:23:05.855165 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7685 19:23:05.861875 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7686 19:23:05.865593 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7687 19:23:05.868663 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7688 19:23:05.875477 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7689 19:23:05.878648 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7690 19:23:05.881704 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7691 19:23:05.885485 Total UI for P1: 0, mck2ui 16
7692 19:23:05.888570 best dqsien dly found for B0: ( 1, 9, 18)
7693 19:23:05.891685 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7694 19:23:05.895339 Total UI for P1: 0, mck2ui 16
7695 19:23:05.898486 best dqsien dly found for B1: ( 1, 9, 20)
7696 19:23:05.904975 best DQS0 dly(MCK, UI, PI) = (1, 9, 18)
7697 19:23:05.908681 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7698 19:23:05.908793
7699 19:23:05.911963 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 18)
7700 19:23:05.914873 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7701 19:23:05.918644 [Gating] SW calibration Done
7702 19:23:05.918758 ==
7703 19:23:05.921993 Dram Type= 6, Freq= 0, CH_0, rank 0
7704 19:23:05.925369 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7705 19:23:05.925482 ==
7706 19:23:05.928452 RX Vref Scan: 0
7707 19:23:05.928564
7708 19:23:05.928660 RX Vref 0 -> 0, step: 1
7709 19:23:05.928755
7710 19:23:05.931874 RX Delay 0 -> 252, step: 8
7711 19:23:05.935068 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7712 19:23:05.941974 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7713 19:23:05.944760 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7714 19:23:05.948317 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7715 19:23:05.951225 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7716 19:23:05.954745 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7717 19:23:05.958479 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7718 19:23:05.964703 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7719 19:23:05.968364 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7720 19:23:05.971468 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7721 19:23:05.974542 iDelay=200, Bit 10, Center 119 (64 ~ 175) 112
7722 19:23:05.978287 iDelay=200, Bit 11, Center 119 (72 ~ 167) 96
7723 19:23:05.985051 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7724 19:23:05.987996 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7725 19:23:05.991701 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7726 19:23:05.994784 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7727 19:23:05.994870 ==
7728 19:23:05.997957 Dram Type= 6, Freq= 0, CH_0, rank 0
7729 19:23:06.004687 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7730 19:23:06.004801 ==
7731 19:23:06.004896 DQS Delay:
7732 19:23:06.008414 DQS0 = 0, DQS1 = 0
7733 19:23:06.008512 DQM Delay:
7734 19:23:06.008600 DQM0 = 132, DQM1 = 124
7735 19:23:06.011405 DQ Delay:
7736 19:23:06.015100 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7737 19:23:06.018135 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7738 19:23:06.021831 DQ8 =111, DQ9 =115, DQ10 =119, DQ11 =119
7739 19:23:06.024864 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7740 19:23:06.024975
7741 19:23:06.025068
7742 19:23:06.025157 ==
7743 19:23:06.028372 Dram Type= 6, Freq= 0, CH_0, rank 0
7744 19:23:06.031415 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7745 19:23:06.035231 ==
7746 19:23:06.035356
7747 19:23:06.035450
7748 19:23:06.035540 TX Vref Scan disable
7749 19:23:06.038562 == TX Byte 0 ==
7750 19:23:06.041588 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7751 19:23:06.044686 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7752 19:23:06.047837 == TX Byte 1 ==
7753 19:23:06.051619 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7754 19:23:06.055311 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7755 19:23:06.055412 ==
7756 19:23:06.057858 Dram Type= 6, Freq= 0, CH_0, rank 0
7757 19:23:06.064626 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7758 19:23:06.064726 ==
7759 19:23:06.078208
7760 19:23:06.081828 TX Vref early break, caculate TX vref
7761 19:23:06.084755 TX Vref=16, minBit 7, minWin=21, winSum=360
7762 19:23:06.088475 TX Vref=18, minBit 0, minWin=22, winSum=368
7763 19:23:06.091547 TX Vref=20, minBit 3, minWin=22, winSum=375
7764 19:23:06.095157 TX Vref=22, minBit 0, minWin=23, winSum=387
7765 19:23:06.098351 TX Vref=24, minBit 1, minWin=23, winSum=399
7766 19:23:06.105163 TX Vref=26, minBit 0, minWin=24, winSum=409
7767 19:23:06.108348 TX Vref=28, minBit 4, minWin=24, winSum=415
7768 19:23:06.111486 TX Vref=30, minBit 4, minWin=24, winSum=418
7769 19:23:06.115068 TX Vref=32, minBit 4, minWin=23, winSum=409
7770 19:23:06.118152 TX Vref=34, minBit 4, minWin=23, winSum=400
7771 19:23:06.121758 TX Vref=36, minBit 4, minWin=22, winSum=392
7772 19:23:06.128423 [TxChooseVref] Worse bit 4, Min win 24, Win sum 418, Final Vref 30
7773 19:23:06.128540
7774 19:23:06.131430 Final TX Range 0 Vref 30
7775 19:23:06.131537
7776 19:23:06.131632 ==
7777 19:23:06.135129 Dram Type= 6, Freq= 0, CH_0, rank 0
7778 19:23:06.138338 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7779 19:23:06.138445 ==
7780 19:23:06.138540
7781 19:23:06.138633
7782 19:23:06.142103 TX Vref Scan disable
7783 19:23:06.148327 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7784 19:23:06.148444 == TX Byte 0 ==
7785 19:23:06.151930 u2DelayCellOfst[0]=14 cells (4 PI)
7786 19:23:06.155121 u2DelayCellOfst[1]=17 cells (5 PI)
7787 19:23:06.158708 u2DelayCellOfst[2]=10 cells (3 PI)
7788 19:23:06.161652 u2DelayCellOfst[3]=14 cells (4 PI)
7789 19:23:06.165385 u2DelayCellOfst[4]=7 cells (2 PI)
7790 19:23:06.168387 u2DelayCellOfst[5]=0 cells (0 PI)
7791 19:23:06.171485 u2DelayCellOfst[6]=17 cells (5 PI)
7792 19:23:06.175173 u2DelayCellOfst[7]=17 cells (5 PI)
7793 19:23:06.178245 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7794 19:23:06.181725 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7795 19:23:06.181806 == TX Byte 1 ==
7796 19:23:06.185072 u2DelayCellOfst[8]=0 cells (0 PI)
7797 19:23:06.188248 u2DelayCellOfst[9]=0 cells (0 PI)
7798 19:23:06.191756 u2DelayCellOfst[10]=10 cells (3 PI)
7799 19:23:06.194879 u2DelayCellOfst[11]=0 cells (0 PI)
7800 19:23:06.198271 u2DelayCellOfst[12]=14 cells (4 PI)
7801 19:23:06.201837 u2DelayCellOfst[13]=14 cells (4 PI)
7802 19:23:06.204884 u2DelayCellOfst[14]=17 cells (5 PI)
7803 19:23:06.208362 u2DelayCellOfst[15]=10 cells (3 PI)
7804 19:23:06.211801 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7805 19:23:06.218183 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7806 19:23:06.218309 DramC Write-DBI on
7807 19:23:06.218409 ==
7808 19:23:06.221915 Dram Type= 6, Freq= 0, CH_0, rank 0
7809 19:23:06.225090 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7810 19:23:06.225204 ==
7811 19:23:06.228119
7812 19:23:06.228225
7813 19:23:06.228322 TX Vref Scan disable
7814 19:23:06.232056 == TX Byte 0 ==
7815 19:23:06.234913 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7816 19:23:06.238441 == TX Byte 1 ==
7817 19:23:06.241446 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7818 19:23:06.245088 DramC Write-DBI off
7819 19:23:06.245196
7820 19:23:06.245317 [DATLAT]
7821 19:23:06.245414 Freq=1600, CH0 RK0
7822 19:23:06.245506
7823 19:23:06.248197 DATLAT Default: 0xf
7824 19:23:06.248297 0, 0xFFFF, sum = 0
7825 19:23:06.251697 1, 0xFFFF, sum = 0
7826 19:23:06.251800 2, 0xFFFF, sum = 0
7827 19:23:06.254846 3, 0xFFFF, sum = 0
7828 19:23:06.258567 4, 0xFFFF, sum = 0
7829 19:23:06.258645 5, 0xFFFF, sum = 0
7830 19:23:06.261692 6, 0xFFFF, sum = 0
7831 19:23:06.261767 7, 0xFFFF, sum = 0
7832 19:23:06.264908 8, 0xFFFF, sum = 0
7833 19:23:06.264993 9, 0xFFFF, sum = 0
7834 19:23:06.268430 10, 0xFFFF, sum = 0
7835 19:23:06.268543 11, 0xFFFF, sum = 0
7836 19:23:06.272155 12, 0xFFFF, sum = 0
7837 19:23:06.272267 13, 0xFFFF, sum = 0
7838 19:23:06.275190 14, 0x0, sum = 1
7839 19:23:06.275298 15, 0x0, sum = 2
7840 19:23:06.278328 16, 0x0, sum = 3
7841 19:23:06.278413 17, 0x0, sum = 4
7842 19:23:06.278480 best_step = 15
7843 19:23:06.282004
7844 19:23:06.282113 ==
7845 19:23:06.285025 Dram Type= 6, Freq= 0, CH_0, rank 0
7846 19:23:06.288600 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7847 19:23:06.288708 ==
7848 19:23:06.288801 RX Vref Scan: 1
7849 19:23:06.288889
7850 19:23:06.291903 Set Vref Range= 24 -> 127
7851 19:23:06.292015
7852 19:23:06.295509 RX Vref 24 -> 127, step: 1
7853 19:23:06.295596
7854 19:23:06.298544 RX Delay 11 -> 252, step: 4
7855 19:23:06.298628
7856 19:23:06.301629 Set Vref, RX VrefLevel [Byte0]: 24
7857 19:23:06.305167 [Byte1]: 24
7858 19:23:06.305302
7859 19:23:06.308431 Set Vref, RX VrefLevel [Byte0]: 25
7860 19:23:06.311557 [Byte1]: 25
7861 19:23:06.311669
7862 19:23:06.314837 Set Vref, RX VrefLevel [Byte0]: 26
7863 19:23:06.318288 [Byte1]: 26
7864 19:23:06.322064
7865 19:23:06.322245 Set Vref, RX VrefLevel [Byte0]: 27
7866 19:23:06.325075 [Byte1]: 27
7867 19:23:06.329465
7868 19:23:06.329553 Set Vref, RX VrefLevel [Byte0]: 28
7869 19:23:06.333339 [Byte1]: 28
7870 19:23:06.337100
7871 19:23:06.337241 Set Vref, RX VrefLevel [Byte0]: 29
7872 19:23:06.340914 [Byte1]: 29
7873 19:23:06.344862
7874 19:23:06.344976 Set Vref, RX VrefLevel [Byte0]: 30
7875 19:23:06.347863 [Byte1]: 30
7876 19:23:06.352687
7877 19:23:06.352769 Set Vref, RX VrefLevel [Byte0]: 31
7878 19:23:06.356020 [Byte1]: 31
7879 19:23:06.360186
7880 19:23:06.360291 Set Vref, RX VrefLevel [Byte0]: 32
7881 19:23:06.363578 [Byte1]: 32
7882 19:23:06.367894
7883 19:23:06.367978 Set Vref, RX VrefLevel [Byte0]: 33
7884 19:23:06.370831 [Byte1]: 33
7885 19:23:06.375110
7886 19:23:06.375214 Set Vref, RX VrefLevel [Byte0]: 34
7887 19:23:06.378355 [Byte1]: 34
7888 19:23:06.383109
7889 19:23:06.383198 Set Vref, RX VrefLevel [Byte0]: 35
7890 19:23:06.386118 [Byte1]: 35
7891 19:23:06.390586
7892 19:23:06.390700 Set Vref, RX VrefLevel [Byte0]: 36
7893 19:23:06.393592 [Byte1]: 36
7894 19:23:06.398435
7895 19:23:06.398514 Set Vref, RX VrefLevel [Byte0]: 37
7896 19:23:06.401411 [Byte1]: 37
7897 19:23:06.405729
7898 19:23:06.405834 Set Vref, RX VrefLevel [Byte0]: 38
7899 19:23:06.408860 [Byte1]: 38
7900 19:23:06.413147
7901 19:23:06.413299 Set Vref, RX VrefLevel [Byte0]: 39
7902 19:23:06.416828 [Byte1]: 39
7903 19:23:06.421190
7904 19:23:06.421321 Set Vref, RX VrefLevel [Byte0]: 40
7905 19:23:06.424273 [Byte1]: 40
7906 19:23:06.428435
7907 19:23:06.428522 Set Vref, RX VrefLevel [Byte0]: 41
7908 19:23:06.431698 [Byte1]: 41
7909 19:23:06.436468
7910 19:23:06.436554 Set Vref, RX VrefLevel [Byte0]: 42
7911 19:23:06.439509 [Byte1]: 42
7912 19:23:06.444007
7913 19:23:06.444123 Set Vref, RX VrefLevel [Byte0]: 43
7914 19:23:06.446967 [Byte1]: 43
7915 19:23:06.451290
7916 19:23:06.451409 Set Vref, RX VrefLevel [Byte0]: 44
7917 19:23:06.454559 [Byte1]: 44
7918 19:23:06.459231
7919 19:23:06.459346 Set Vref, RX VrefLevel [Byte0]: 45
7920 19:23:06.462342 [Byte1]: 45
7921 19:23:06.466818
7922 19:23:06.466928 Set Vref, RX VrefLevel [Byte0]: 46
7923 19:23:06.469909 [Byte1]: 46
7924 19:23:06.474229
7925 19:23:06.474365 Set Vref, RX VrefLevel [Byte0]: 47
7926 19:23:06.477397 [Byte1]: 47
7927 19:23:06.481836
7928 19:23:06.481927 Set Vref, RX VrefLevel [Byte0]: 48
7929 19:23:06.485218 [Byte1]: 48
7930 19:23:06.489256
7931 19:23:06.489399 Set Vref, RX VrefLevel [Byte0]: 49
7932 19:23:06.492931 [Byte1]: 49
7933 19:23:06.497105
7934 19:23:06.497192 Set Vref, RX VrefLevel [Byte0]: 50
7935 19:23:06.500092 [Byte1]: 50
7936 19:23:06.505054
7937 19:23:06.505138 Set Vref, RX VrefLevel [Byte0]: 51
7938 19:23:06.508135 [Byte1]: 51
7939 19:23:06.512482
7940 19:23:06.512565 Set Vref, RX VrefLevel [Byte0]: 52
7941 19:23:06.515406 [Byte1]: 52
7942 19:23:06.519837
7943 19:23:06.519921 Set Vref, RX VrefLevel [Byte0]: 53
7944 19:23:06.523605 [Byte1]: 53
7945 19:23:06.527396
7946 19:23:06.527482 Set Vref, RX VrefLevel [Byte0]: 54
7947 19:23:06.531060 [Byte1]: 54
7948 19:23:06.534980
7949 19:23:06.535064 Set Vref, RX VrefLevel [Byte0]: 55
7950 19:23:06.538430 [Byte1]: 55
7951 19:23:06.543057
7952 19:23:06.543163 Set Vref, RX VrefLevel [Byte0]: 56
7953 19:23:06.546241 [Byte1]: 56
7954 19:23:06.550582
7955 19:23:06.550658 Set Vref, RX VrefLevel [Byte0]: 57
7956 19:23:06.553709 [Byte1]: 57
7957 19:23:06.557846
7958 19:23:06.557934 Set Vref, RX VrefLevel [Byte0]: 58
7959 19:23:06.561432 [Byte1]: 58
7960 19:23:06.565553
7961 19:23:06.565642 Set Vref, RX VrefLevel [Byte0]: 59
7962 19:23:06.568960 [Byte1]: 59
7963 19:23:06.573136
7964 19:23:06.573243 Set Vref, RX VrefLevel [Byte0]: 60
7965 19:23:06.576215 [Byte1]: 60
7966 19:23:06.580605
7967 19:23:06.580688 Set Vref, RX VrefLevel [Byte0]: 61
7968 19:23:06.584142 [Byte1]: 61
7969 19:23:06.588532
7970 19:23:06.588616 Set Vref, RX VrefLevel [Byte0]: 62
7971 19:23:06.591551 [Byte1]: 62
7972 19:23:06.595980
7973 19:23:06.596063 Set Vref, RX VrefLevel [Byte0]: 63
7974 19:23:06.599357 [Byte1]: 63
7975 19:23:06.603446
7976 19:23:06.603530 Set Vref, RX VrefLevel [Byte0]: 64
7977 19:23:06.606840 [Byte1]: 64
7978 19:23:06.611345
7979 19:23:06.611430 Set Vref, RX VrefLevel [Byte0]: 65
7980 19:23:06.614386 [Byte1]: 65
7981 19:23:06.618632
7982 19:23:06.618766 Set Vref, RX VrefLevel [Byte0]: 66
7983 19:23:06.622885 [Byte1]: 66
7984 19:23:06.626304
7985 19:23:06.626421 Set Vref, RX VrefLevel [Byte0]: 67
7986 19:23:06.629884 [Byte1]: 67
7987 19:23:06.634198
7988 19:23:06.634394 Set Vref, RX VrefLevel [Byte0]: 68
7989 19:23:06.637079 [Byte1]: 68
7990 19:23:06.641723
7991 19:23:06.641857 Set Vref, RX VrefLevel [Byte0]: 69
7992 19:23:06.645204 [Byte1]: 69
7993 19:23:06.648951
7994 19:23:06.649112 Set Vref, RX VrefLevel [Byte0]: 70
7995 19:23:06.652356 [Byte1]: 70
7996 19:23:06.657339
7997 19:23:06.657495 Set Vref, RX VrefLevel [Byte0]: 71
7998 19:23:06.660171 [Byte1]: 71
7999 19:23:06.664364
8000 19:23:06.664477 Set Vref, RX VrefLevel [Byte0]: 72
8001 19:23:06.667948 [Byte1]: 72
8002 19:23:06.671997
8003 19:23:06.672108 Set Vref, RX VrefLevel [Byte0]: 73
8004 19:23:06.675510 [Byte1]: 73
8005 19:23:06.679643
8006 19:23:06.679731 Set Vref, RX VrefLevel [Byte0]: 74
8007 19:23:06.683298 [Byte1]: 74
8008 19:23:06.687564
8009 19:23:06.687643 Final RX Vref Byte 0 = 54 to rank0
8010 19:23:06.690596 Final RX Vref Byte 1 = 61 to rank0
8011 19:23:06.694351 Final RX Vref Byte 0 = 54 to rank1
8012 19:23:06.697316 Final RX Vref Byte 1 = 61 to rank1==
8013 19:23:06.701047 Dram Type= 6, Freq= 0, CH_0, rank 0
8014 19:23:06.707183 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8015 19:23:06.707301 ==
8016 19:23:06.707375 DQS Delay:
8017 19:23:06.707435 DQS0 = 0, DQS1 = 0
8018 19:23:06.710993 DQM Delay:
8019 19:23:06.711065 DQM0 = 129, DQM1 = 123
8020 19:23:06.713723 DQ Delay:
8021 19:23:06.717087 DQ0 =130, DQ1 =132, DQ2 =122, DQ3 =126
8022 19:23:06.720763 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =138
8023 19:23:06.724070 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
8024 19:23:06.727326 DQ12 =128, DQ13 =128, DQ14 =134, DQ15 =134
8025 19:23:06.727406
8026 19:23:06.727471
8027 19:23:06.727531
8028 19:23:06.730768 [DramC_TX_OE_Calibration] TA2
8029 19:23:06.734175 Original DQ_B0 (3 6) =30, OEN = 27
8030 19:23:06.737212 Original DQ_B1 (3 6) =30, OEN = 27
8031 19:23:06.740924 24, 0x0, End_B0=24 End_B1=24
8032 19:23:06.741009 25, 0x0, End_B0=25 End_B1=25
8033 19:23:06.743862 26, 0x0, End_B0=26 End_B1=26
8034 19:23:06.747628 27, 0x0, End_B0=27 End_B1=27
8035 19:23:06.750927 28, 0x0, End_B0=28 End_B1=28
8036 19:23:06.751021 29, 0x0, End_B0=29 End_B1=29
8037 19:23:06.753786 30, 0x0, End_B0=30 End_B1=30
8038 19:23:06.757230 31, 0x4141, End_B0=30 End_B1=30
8039 19:23:06.760422 Byte0 end_step=30 best_step=27
8040 19:23:06.764232 Byte1 end_step=30 best_step=27
8041 19:23:06.767590 Byte0 TX OE(2T, 0.5T) = (3, 3)
8042 19:23:06.767674 Byte1 TX OE(2T, 0.5T) = (3, 3)
8043 19:23:06.767741
8044 19:23:06.770597
8045 19:23:06.777409 [DQSOSCAuto] RK0, (LSB)MR18= 0x1509, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps
8046 19:23:06.780765 CH0 RK0: MR19=303, MR18=1509
8047 19:23:06.787209 CH0_RK0: MR19=0x303, MR18=0x1509, DQSOSC=399, MR23=63, INC=23, DEC=15
8048 19:23:06.787305
8049 19:23:06.790920 ----->DramcWriteLeveling(PI) begin...
8050 19:23:06.791023 ==
8051 19:23:06.793881 Dram Type= 6, Freq= 0, CH_0, rank 1
8052 19:23:06.797619 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8053 19:23:06.797706 ==
8054 19:23:06.800775 Write leveling (Byte 0): 33 => 33
8055 19:23:06.803722 Write leveling (Byte 1): 27 => 27
8056 19:23:06.807588 DramcWriteLeveling(PI) end<-----
8057 19:23:06.807673
8058 19:23:06.807744 ==
8059 19:23:06.810525 Dram Type= 6, Freq= 0, CH_0, rank 1
8060 19:23:06.814154 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8061 19:23:06.814284 ==
8062 19:23:06.817233 [Gating] SW mode calibration
8063 19:23:06.823724 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8064 19:23:06.830397 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8065 19:23:06.834157 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8066 19:23:06.837487 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8067 19:23:06.844128 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8068 19:23:06.847174 1 4 12 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
8069 19:23:06.850808 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8070 19:23:06.857477 1 4 20 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
8071 19:23:06.860570 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8072 19:23:06.863989 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8073 19:23:06.870341 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8074 19:23:06.873936 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8075 19:23:06.877591 1 5 8 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
8076 19:23:06.884157 1 5 12 | B1->B0 | 3434 2828 | 1 0 | (1 1) (1 0)
8077 19:23:06.887257 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8078 19:23:06.890674 1 5 20 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
8079 19:23:06.894050 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8080 19:23:06.900581 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8081 19:23:06.903511 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8082 19:23:06.906928 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8083 19:23:06.914135 1 6 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
8084 19:23:06.917174 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8085 19:23:06.920707 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8086 19:23:06.926854 1 6 20 | B1->B0 | 3939 4646 | 1 0 | (0 0) (0 0)
8087 19:23:06.930559 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8088 19:23:06.933596 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8089 19:23:06.940314 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8090 19:23:06.943955 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8091 19:23:06.947009 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8092 19:23:06.953610 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8093 19:23:06.956865 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8094 19:23:06.960251 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8095 19:23:06.967344 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8096 19:23:06.970684 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 19:23:06.973664 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 19:23:06.980357 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 19:23:06.983559 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8100 19:23:06.987278 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8101 19:23:06.993744 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8102 19:23:06.997116 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8103 19:23:07.000004 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8104 19:23:07.003443 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8105 19:23:07.010246 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8106 19:23:07.013403 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8107 19:23:07.017087 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8108 19:23:07.023613 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8109 19:23:07.026796 Total UI for P1: 0, mck2ui 16
8110 19:23:07.030315 best dqsien dly found for B0: ( 1, 9, 6)
8111 19:23:07.033782 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8112 19:23:07.036765 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8113 19:23:07.043535 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8114 19:23:07.046717 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8115 19:23:07.050400 Total UI for P1: 0, mck2ui 16
8116 19:23:07.053528 best dqsien dly found for B1: ( 1, 9, 22)
8117 19:23:07.057131 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8118 19:23:07.060318 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
8119 19:23:07.060407
8120 19:23:07.063959 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8121 19:23:07.067058 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
8122 19:23:07.070134 [Gating] SW calibration Done
8123 19:23:07.070271 ==
8124 19:23:07.073744 Dram Type= 6, Freq= 0, CH_0, rank 1
8125 19:23:07.076641 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8126 19:23:07.080222 ==
8127 19:23:07.080316 RX Vref Scan: 0
8128 19:23:07.080383
8129 19:23:07.083334 RX Vref 0 -> 0, step: 1
8130 19:23:07.083452
8131 19:23:07.083519 RX Delay 0 -> 252, step: 8
8132 19:23:07.090027 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8133 19:23:07.093686 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8134 19:23:07.096778 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8135 19:23:07.100323 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8136 19:23:07.103813 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8137 19:23:07.110198 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8138 19:23:07.113417 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8139 19:23:07.116553 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8140 19:23:07.120307 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8141 19:23:07.123153 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8142 19:23:07.129877 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8143 19:23:07.133641 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8144 19:23:07.137203 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8145 19:23:07.140312 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8146 19:23:07.143440 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8147 19:23:07.150322 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8148 19:23:07.150486 ==
8149 19:23:07.153944 Dram Type= 6, Freq= 0, CH_0, rank 1
8150 19:23:07.157145 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8151 19:23:07.157329 ==
8152 19:23:07.157437 DQS Delay:
8153 19:23:07.160123 DQS0 = 0, DQS1 = 0
8154 19:23:07.160221 DQM Delay:
8155 19:23:07.163894 DQM0 = 130, DQM1 = 125
8156 19:23:07.164033 DQ Delay:
8157 19:23:07.166890 DQ0 =131, DQ1 =131, DQ2 =123, DQ3 =131
8158 19:23:07.169957 DQ4 =131, DQ5 =115, DQ6 =139, DQ7 =139
8159 19:23:07.173588 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =119
8160 19:23:07.177105 DQ12 =127, DQ13 =135, DQ14 =135, DQ15 =131
8161 19:23:07.177250
8162 19:23:07.177323
8163 19:23:07.180297 ==
8164 19:23:07.183474 Dram Type= 6, Freq= 0, CH_0, rank 1
8165 19:23:07.186929 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8166 19:23:07.187039 ==
8167 19:23:07.187108
8168 19:23:07.187171
8169 19:23:07.190431 TX Vref Scan disable
8170 19:23:07.190533 == TX Byte 0 ==
8171 19:23:07.194062 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8172 19:23:07.199981 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8173 19:23:07.200080 == TX Byte 1 ==
8174 19:23:07.203692 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8175 19:23:07.210446 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8176 19:23:07.210551 ==
8177 19:23:07.213442 Dram Type= 6, Freq= 0, CH_0, rank 1
8178 19:23:07.216947 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8179 19:23:07.217066 ==
8180 19:23:07.232100
8181 19:23:07.235162 TX Vref early break, caculate TX vref
8182 19:23:07.238233 TX Vref=16, minBit 4, minWin=22, winSum=369
8183 19:23:07.241816 TX Vref=18, minBit 9, minWin=22, winSum=380
8184 19:23:07.244901 TX Vref=20, minBit 0, minWin=23, winSum=386
8185 19:23:07.248162 TX Vref=22, minBit 1, minWin=24, winSum=398
8186 19:23:07.251568 TX Vref=24, minBit 4, minWin=24, winSum=404
8187 19:23:07.258202 TX Vref=26, minBit 4, minWin=24, winSum=408
8188 19:23:07.261928 TX Vref=28, minBit 0, minWin=25, winSum=416
8189 19:23:07.265019 TX Vref=30, minBit 1, minWin=25, winSum=415
8190 19:23:07.268217 TX Vref=32, minBit 0, minWin=24, winSum=408
8191 19:23:07.271924 TX Vref=34, minBit 4, minWin=23, winSum=400
8192 19:23:07.274942 TX Vref=36, minBit 4, minWin=23, winSum=394
8193 19:23:07.281492 [TxChooseVref] Worse bit 0, Min win 25, Win sum 416, Final Vref 28
8194 19:23:07.281636
8195 19:23:07.285129 Final TX Range 0 Vref 28
8196 19:23:07.285245
8197 19:23:07.285317 ==
8198 19:23:07.288196 Dram Type= 6, Freq= 0, CH_0, rank 1
8199 19:23:07.291909 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8200 19:23:07.292025 ==
8201 19:23:07.292124
8202 19:23:07.292215
8203 19:23:07.294773 TX Vref Scan disable
8204 19:23:07.301385 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8205 19:23:07.301483 == TX Byte 0 ==
8206 19:23:07.304919 u2DelayCellOfst[0]=14 cells (4 PI)
8207 19:23:07.308051 u2DelayCellOfst[1]=17 cells (5 PI)
8208 19:23:07.311878 u2DelayCellOfst[2]=10 cells (3 PI)
8209 19:23:07.314885 u2DelayCellOfst[3]=10 cells (3 PI)
8210 19:23:07.317914 u2DelayCellOfst[4]=10 cells (3 PI)
8211 19:23:07.321506 u2DelayCellOfst[5]=0 cells (0 PI)
8212 19:23:07.325288 u2DelayCellOfst[6]=17 cells (5 PI)
8213 19:23:07.328359 u2DelayCellOfst[7]=17 cells (5 PI)
8214 19:23:07.331458 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8215 19:23:07.335179 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8216 19:23:07.338366 == TX Byte 1 ==
8217 19:23:07.341859 u2DelayCellOfst[8]=0 cells (0 PI)
8218 19:23:07.342040 u2DelayCellOfst[9]=0 cells (0 PI)
8219 19:23:07.344661 u2DelayCellOfst[10]=7 cells (2 PI)
8220 19:23:07.348210 u2DelayCellOfst[11]=0 cells (0 PI)
8221 19:23:07.351212 u2DelayCellOfst[12]=10 cells (3 PI)
8222 19:23:07.381660 u2DelayCellOfst[13]=10 cells (3 PI)
8223 19:23:07.381847 u2DelayCellOfst[14]=14 cells (4 PI)
8224 19:23:07.381952 u2DelayCellOfst[15]=10 cells (3 PI)
8225 19:23:07.382051 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8226 19:23:07.382146 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8227 19:23:07.382240 DramC Write-DBI on
8228 19:23:07.382331 ==
8229 19:23:07.382428 Dram Type= 6, Freq= 0, CH_0, rank 1
8230 19:23:07.382527 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8231 19:23:07.382591 ==
8232 19:23:07.382649
8233 19:23:07.382706
8234 19:23:07.382762 TX Vref Scan disable
8235 19:23:07.384982 == TX Byte 0 ==
8236 19:23:07.388276 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8237 19:23:07.392063 == TX Byte 1 ==
8238 19:23:07.395022 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8239 19:23:07.395138 DramC Write-DBI off
8240 19:23:07.398712
8241 19:23:07.398821 [DATLAT]
8242 19:23:07.398924 Freq=1600, CH0 RK1
8243 19:23:07.399031
8244 19:23:07.401610 DATLAT Default: 0xf
8245 19:23:07.401715 0, 0xFFFF, sum = 0
8246 19:23:07.413021 1, 0xFFFF, sum = 0
8247 19:23:07.413154 2, 0xFFFF, sum = 0
8248 19:23:07.413269 3, 0xFFFF, sum = 0
8249 19:23:07.413363 4, 0xFFFF, sum = 0
8250 19:23:07.413456 5, 0xFFFF, sum = 0
8251 19:23:07.414998 6, 0xFFFF, sum = 0
8252 19:23:07.415082 7, 0xFFFF, sum = 0
8253 19:23:07.418755 8, 0xFFFF, sum = 0
8254 19:23:07.418884 9, 0xFFFF, sum = 0
8255 19:23:07.421742 10, 0xFFFF, sum = 0
8256 19:23:07.421839 11, 0xFFFF, sum = 0
8257 19:23:07.425283 12, 0xFFFF, sum = 0
8258 19:23:07.425382 13, 0xFFFF, sum = 0
8259 19:23:07.429403 14, 0x0, sum = 1
8260 19:23:07.429592 15, 0x0, sum = 2
8261 19:23:07.432226 16, 0x0, sum = 3
8262 19:23:07.432328 17, 0x0, sum = 4
8263 19:23:07.435170 best_step = 15
8264 19:23:07.435255
8265 19:23:07.435321 ==
8266 19:23:07.438880 Dram Type= 6, Freq= 0, CH_0, rank 1
8267 19:23:07.441970 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8268 19:23:07.442056 ==
8269 19:23:07.442123 RX Vref Scan: 0
8270 19:23:07.442192
8271 19:23:07.445578 RX Vref 0 -> 0, step: 1
8272 19:23:07.445665
8273 19:23:07.448456 RX Delay 11 -> 252, step: 4
8274 19:23:07.451798 iDelay=191, Bit 0, Center 126 (71 ~ 182) 112
8275 19:23:07.458623 iDelay=191, Bit 1, Center 130 (75 ~ 186) 112
8276 19:23:07.462351 iDelay=191, Bit 2, Center 122 (67 ~ 178) 112
8277 19:23:07.465307 iDelay=191, Bit 3, Center 126 (71 ~ 182) 112
8278 19:23:07.469016 iDelay=191, Bit 4, Center 126 (75 ~ 178) 104
8279 19:23:07.471950 iDelay=191, Bit 5, Center 114 (59 ~ 170) 112
8280 19:23:07.475501 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8281 19:23:07.481962 iDelay=191, Bit 7, Center 136 (83 ~ 190) 108
8282 19:23:07.485134 iDelay=191, Bit 8, Center 112 (59 ~ 166) 108
8283 19:23:07.488938 iDelay=191, Bit 9, Center 110 (55 ~ 166) 112
8284 19:23:07.491806 iDelay=191, Bit 10, Center 122 (67 ~ 178) 112
8285 19:23:07.495377 iDelay=191, Bit 11, Center 116 (63 ~ 170) 108
8286 19:23:07.501751 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8287 19:23:07.505396 iDelay=191, Bit 13, Center 128 (75 ~ 182) 108
8288 19:23:07.508609 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8289 19:23:07.511750 iDelay=191, Bit 15, Center 132 (79 ~ 186) 108
8290 19:23:07.511839 ==
8291 19:23:07.515015 Dram Type= 6, Freq= 0, CH_0, rank 1
8292 19:23:07.522181 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8293 19:23:07.522285 ==
8294 19:23:07.522353 DQS Delay:
8295 19:23:07.525204 DQS0 = 0, DQS1 = 0
8296 19:23:07.525353 DQM Delay:
8297 19:23:07.525450 DQM0 = 126, DQM1 = 122
8298 19:23:07.528896 DQ Delay:
8299 19:23:07.531861 DQ0 =126, DQ1 =130, DQ2 =122, DQ3 =126
8300 19:23:07.535461 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =136
8301 19:23:07.538416 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
8302 19:23:07.542059 DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =132
8303 19:23:07.542132
8304 19:23:07.542192
8305 19:23:07.542250
8306 19:23:07.545084 [DramC_TX_OE_Calibration] TA2
8307 19:23:07.548864 Original DQ_B0 (3 6) =30, OEN = 27
8308 19:23:07.552029 Original DQ_B1 (3 6) =30, OEN = 27
8309 19:23:07.555594 24, 0x0, End_B0=24 End_B1=24
8310 19:23:07.555709 25, 0x0, End_B0=25 End_B1=25
8311 19:23:07.558477 26, 0x0, End_B0=26 End_B1=26
8312 19:23:07.562144 27, 0x0, End_B0=27 End_B1=27
8313 19:23:07.565184 28, 0x0, End_B0=28 End_B1=28
8314 19:23:07.568968 29, 0x0, End_B0=29 End_B1=29
8315 19:23:07.569054 30, 0x0, End_B0=30 End_B1=30
8316 19:23:07.572034 31, 0x4141, End_B0=30 End_B1=30
8317 19:23:07.575272 Byte0 end_step=30 best_step=27
8318 19:23:07.578837 Byte1 end_step=30 best_step=27
8319 19:23:07.581842 Byte0 TX OE(2T, 0.5T) = (3, 3)
8320 19:23:07.581916 Byte1 TX OE(2T, 0.5T) = (3, 3)
8321 19:23:07.585478
8322 19:23:07.585576
8323 19:23:07.592470 [DQSOSCAuto] RK1, (LSB)MR18= 0x170b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps
8324 19:23:07.595669 CH0 RK1: MR19=303, MR18=170B
8325 19:23:07.602070 CH0_RK1: MR19=0x303, MR18=0x170B, DQSOSC=398, MR23=63, INC=23, DEC=15
8326 19:23:07.605662 [RxdqsGatingPostProcess] freq 1600
8327 19:23:07.608568 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8328 19:23:07.612099 best DQS0 dly(2T, 0.5T) = (1, 1)
8329 19:23:07.615408 best DQS1 dly(2T, 0.5T) = (1, 1)
8330 19:23:07.618640 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8331 19:23:07.622155 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8332 19:23:07.625554 best DQS0 dly(2T, 0.5T) = (1, 1)
8333 19:23:07.628702 best DQS1 dly(2T, 0.5T) = (1, 1)
8334 19:23:07.631986 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8335 19:23:07.635658 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8336 19:23:07.635745 Pre-setting of DQS Precalculation
8337 19:23:07.641887 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8338 19:23:07.641980 ==
8339 19:23:07.645675 Dram Type= 6, Freq= 0, CH_1, rank 0
8340 19:23:07.648845 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8341 19:23:07.648944 ==
8342 19:23:07.655422 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8343 19:23:07.658590 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8344 19:23:07.662176 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8345 19:23:07.668748 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8346 19:23:07.678280 [CA 0] Center 42 (13~71) winsize 59
8347 19:23:07.681387 [CA 1] Center 42 (13~71) winsize 59
8348 19:23:07.685188 [CA 2] Center 37 (8~66) winsize 59
8349 19:23:07.688083 [CA 3] Center 36 (7~65) winsize 59
8350 19:23:07.691686 [CA 4] Center 37 (8~67) winsize 60
8351 19:23:07.694810 [CA 5] Center 36 (6~66) winsize 61
8352 19:23:07.694888
8353 19:23:07.698314 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8354 19:23:07.698415
8355 19:23:07.701841 [CATrainingPosCal] consider 1 rank data
8356 19:23:07.704501 u2DelayCellTimex100 = 275/100 ps
8357 19:23:07.708286 CA0 delay=42 (13~71),Diff = 6 PI (21 cell)
8358 19:23:07.714835 CA1 delay=42 (13~71),Diff = 6 PI (21 cell)
8359 19:23:07.717990 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8360 19:23:07.721442 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8361 19:23:07.724936 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8362 19:23:07.728427 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
8363 19:23:07.728517
8364 19:23:07.731349 CA PerBit enable=1, Macro0, CA PI delay=36
8365 19:23:07.731450
8366 19:23:07.734629 [CBTSetCACLKResult] CA Dly = 36
8367 19:23:07.738281 CS Dly: 8 (0~39)
8368 19:23:07.741241 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8369 19:23:07.744717 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8370 19:23:07.744797 ==
8371 19:23:07.748039 Dram Type= 6, Freq= 0, CH_1, rank 1
8372 19:23:07.751750 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8373 19:23:07.751867 ==
8374 19:23:07.758011 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8375 19:23:07.761686 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8376 19:23:07.768321 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8377 19:23:07.771875 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8378 19:23:07.781741 [CA 0] Center 43 (14~73) winsize 60
8379 19:23:07.784858 [CA 1] Center 43 (14~72) winsize 59
8380 19:23:07.788013 [CA 2] Center 38 (9~67) winsize 59
8381 19:23:07.791082 [CA 3] Center 37 (9~66) winsize 58
8382 19:23:07.794614 [CA 4] Center 38 (9~68) winsize 60
8383 19:23:07.798105 [CA 5] Center 37 (8~66) winsize 59
8384 19:23:07.798180
8385 19:23:07.801224 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8386 19:23:07.801319
8387 19:23:07.804835 [CATrainingPosCal] consider 2 rank data
8388 19:23:07.808001 u2DelayCellTimex100 = 275/100 ps
8389 19:23:07.811288 CA0 delay=42 (14~71),Diff = 5 PI (17 cell)
8390 19:23:07.817813 CA1 delay=42 (14~71),Diff = 5 PI (17 cell)
8391 19:23:07.821347 CA2 delay=37 (9~66),Diff = 0 PI (0 cell)
8392 19:23:07.825023 CA3 delay=37 (9~65),Diff = 0 PI (0 cell)
8393 19:23:07.828021 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8394 19:23:07.831526 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8395 19:23:07.831639
8396 19:23:07.834970 CA PerBit enable=1, Macro0, CA PI delay=37
8397 19:23:07.835082
8398 19:23:07.838131 [CBTSetCACLKResult] CA Dly = 37
8399 19:23:07.841546 CS Dly: 11 (0~45)
8400 19:23:07.844952 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8401 19:23:07.847647 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8402 19:23:07.847775
8403 19:23:07.851364 ----->DramcWriteLeveling(PI) begin...
8404 19:23:07.851476 ==
8405 19:23:07.854980 Dram Type= 6, Freq= 0, CH_1, rank 0
8406 19:23:07.857803 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8407 19:23:07.861030 ==
8408 19:23:07.861103 Write leveling (Byte 0): 26 => 26
8409 19:23:07.864932 Write leveling (Byte 1): 28 => 28
8410 19:23:07.867816 DramcWriteLeveling(PI) end<-----
8411 19:23:07.867905
8412 19:23:07.867969 ==
8413 19:23:07.871436 Dram Type= 6, Freq= 0, CH_1, rank 0
8414 19:23:07.877953 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8415 19:23:07.878057 ==
8416 19:23:07.878125 [Gating] SW mode calibration
8417 19:23:07.888185 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8418 19:23:07.891235 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8419 19:23:07.894917 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8420 19:23:07.901538 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8421 19:23:07.904594 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8422 19:23:07.908352 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8423 19:23:07.914879 1 4 16 | B1->B0 | 2929 2323 | 0 1 | (0 0) (1 1)
8424 19:23:07.917971 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8425 19:23:07.921573 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8426 19:23:07.928417 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8427 19:23:07.931550 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8428 19:23:07.934714 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8429 19:23:07.941148 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8430 19:23:07.945069 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8431 19:23:07.948221 1 5 16 | B1->B0 | 2626 3030 | 1 1 | (1 0) (1 0)
8432 19:23:07.954673 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
8433 19:23:07.958538 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8434 19:23:07.961601 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8435 19:23:07.964722 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8436 19:23:07.971774 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8437 19:23:07.974874 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8438 19:23:07.978147 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8439 19:23:07.984636 1 6 16 | B1->B0 | 3a3a 2c2c | 0 1 | (0 0) (0 0)
8440 19:23:07.988438 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8441 19:23:07.991571 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8442 19:23:07.998296 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8443 19:23:08.001382 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8444 19:23:08.004970 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8445 19:23:08.011567 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8446 19:23:08.014714 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8447 19:23:08.018241 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8448 19:23:08.024832 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8449 19:23:08.028500 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8450 19:23:08.031420 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8451 19:23:08.038161 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8452 19:23:08.041866 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8453 19:23:08.044911 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8454 19:23:08.051335 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8455 19:23:08.054929 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8456 19:23:08.058509 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8457 19:23:08.061754 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8458 19:23:08.068212 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8459 19:23:08.071289 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8460 19:23:08.074739 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8461 19:23:08.081398 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8462 19:23:08.084777 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8463 19:23:08.087937 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8464 19:23:08.094939 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8465 19:23:08.097946 Total UI for P1: 0, mck2ui 16
8466 19:23:08.101784 best dqsien dly found for B0: ( 1, 9, 14)
8467 19:23:08.104744 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8468 19:23:08.108243 Total UI for P1: 0, mck2ui 16
8469 19:23:08.111434 best dqsien dly found for B1: ( 1, 9, 16)
8470 19:23:08.114894 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8471 19:23:08.118049 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8472 19:23:08.118144
8473 19:23:08.121636 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8474 19:23:08.125366 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8475 19:23:08.128316 [Gating] SW calibration Done
8476 19:23:08.128422 ==
8477 19:23:08.131911 Dram Type= 6, Freq= 0, CH_1, rank 0
8478 19:23:08.134971 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8479 19:23:08.138626 ==
8480 19:23:08.138707 RX Vref Scan: 0
8481 19:23:08.138773
8482 19:23:08.141495 RX Vref 0 -> 0, step: 1
8483 19:23:08.141584
8484 19:23:08.141652 RX Delay 0 -> 252, step: 8
8485 19:23:08.148370 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8486 19:23:08.151568 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8487 19:23:08.155305 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8488 19:23:08.158026 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8489 19:23:08.161246 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8490 19:23:08.168202 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8491 19:23:08.171848 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8492 19:23:08.174930 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8493 19:23:08.178350 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8494 19:23:08.181592 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8495 19:23:08.188337 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8496 19:23:08.191451 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8497 19:23:08.195080 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8498 19:23:08.197855 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8499 19:23:08.204675 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8500 19:23:08.207931 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8501 19:23:08.208036 ==
8502 19:23:08.211382 Dram Type= 6, Freq= 0, CH_1, rank 0
8503 19:23:08.214889 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8504 19:23:08.214972 ==
8505 19:23:08.215038 DQS Delay:
8506 19:23:08.218047 DQS0 = 0, DQS1 = 0
8507 19:23:08.218138 DQM Delay:
8508 19:23:08.220968 DQM0 = 134, DQM1 = 127
8509 19:23:08.221092 DQ Delay:
8510 19:23:08.224679 DQ0 =139, DQ1 =127, DQ2 =123, DQ3 =135
8511 19:23:08.227808 DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =127
8512 19:23:08.231439 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =123
8513 19:23:08.237663 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8514 19:23:08.237760
8515 19:23:08.237827
8516 19:23:08.237887 ==
8517 19:23:08.241401 Dram Type= 6, Freq= 0, CH_1, rank 0
8518 19:23:08.244468 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8519 19:23:08.244554 ==
8520 19:23:08.244618
8521 19:23:08.244678
8522 19:23:08.247869 TX Vref Scan disable
8523 19:23:08.247952 == TX Byte 0 ==
8524 19:23:08.254703 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8525 19:23:08.257719 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8526 19:23:08.257805 == TX Byte 1 ==
8527 19:23:08.264343 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8528 19:23:08.267851 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8529 19:23:08.267945 ==
8530 19:23:08.271331 Dram Type= 6, Freq= 0, CH_1, rank 0
8531 19:23:08.274309 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8532 19:23:08.274396 ==
8533 19:23:08.289099
8534 19:23:08.292421 TX Vref early break, caculate TX vref
8535 19:23:08.295630 TX Vref=16, minBit 8, minWin=20, winSum=359
8536 19:23:08.298672 TX Vref=18, minBit 8, minWin=21, winSum=374
8537 19:23:08.302349 TX Vref=20, minBit 5, minWin=22, winSum=381
8538 19:23:08.305470 TX Vref=22, minBit 8, minWin=23, winSum=392
8539 19:23:08.309002 TX Vref=24, minBit 8, minWin=23, winSum=400
8540 19:23:08.315565 TX Vref=26, minBit 11, minWin=24, winSum=411
8541 19:23:08.318738 TX Vref=28, minBit 15, minWin=24, winSum=417
8542 19:23:08.321916 TX Vref=30, minBit 1, minWin=25, winSum=417
8543 19:23:08.325726 TX Vref=32, minBit 0, minWin=25, winSum=409
8544 19:23:08.328671 TX Vref=34, minBit 8, minWin=23, winSum=396
8545 19:23:08.332367 TX Vref=36, minBit 8, minWin=23, winSum=391
8546 19:23:08.338935 [TxChooseVref] Worse bit 1, Min win 25, Win sum 417, Final Vref 30
8547 19:23:08.339108
8548 19:23:08.342554 Final TX Range 0 Vref 30
8549 19:23:08.342639
8550 19:23:08.342706 ==
8551 19:23:08.345657 Dram Type= 6, Freq= 0, CH_1, rank 0
8552 19:23:08.348681 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8553 19:23:08.348762 ==
8554 19:23:08.348827
8555 19:23:08.348886
8556 19:23:08.352198 TX Vref Scan disable
8557 19:23:08.358687 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8558 19:23:08.358778 == TX Byte 0 ==
8559 19:23:08.361928 u2DelayCellOfst[0]=17 cells (5 PI)
8560 19:23:08.365932 u2DelayCellOfst[1]=14 cells (4 PI)
8561 19:23:08.369027 u2DelayCellOfst[2]=0 cells (0 PI)
8562 19:23:08.372326 u2DelayCellOfst[3]=7 cells (2 PI)
8563 19:23:08.375748 u2DelayCellOfst[4]=7 cells (2 PI)
8564 19:23:08.379224 u2DelayCellOfst[5]=17 cells (5 PI)
8565 19:23:08.382323 u2DelayCellOfst[6]=17 cells (5 PI)
8566 19:23:08.385465 u2DelayCellOfst[7]=7 cells (2 PI)
8567 19:23:08.389147 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8568 19:23:08.392187 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8569 19:23:08.395850 == TX Byte 1 ==
8570 19:23:08.395934 u2DelayCellOfst[8]=0 cells (0 PI)
8571 19:23:08.398851 u2DelayCellOfst[9]=7 cells (2 PI)
8572 19:23:08.402051 u2DelayCellOfst[10]=10 cells (3 PI)
8573 19:23:08.405838 u2DelayCellOfst[11]=7 cells (2 PI)
8574 19:23:08.408874 u2DelayCellOfst[12]=14 cells (4 PI)
8575 19:23:08.412296 u2DelayCellOfst[13]=17 cells (5 PI)
8576 19:23:08.415276 u2DelayCellOfst[14]=17 cells (5 PI)
8577 19:23:08.419013 u2DelayCellOfst[15]=17 cells (5 PI)
8578 19:23:08.422143 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8579 19:23:08.429278 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8580 19:23:08.429400 DramC Write-DBI on
8581 19:23:08.429493 ==
8582 19:23:08.432308 Dram Type= 6, Freq= 0, CH_1, rank 0
8583 19:23:08.435668 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8584 19:23:08.438943 ==
8585 19:23:08.439053
8586 19:23:08.439126
8587 19:23:08.439188 TX Vref Scan disable
8588 19:23:08.442106 == TX Byte 0 ==
8589 19:23:08.445817 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8590 19:23:08.448767 == TX Byte 1 ==
8591 19:23:08.452246 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8592 19:23:08.452346 DramC Write-DBI off
8593 19:23:08.452413
8594 19:23:08.455873 [DATLAT]
8595 19:23:08.456026 Freq=1600, CH1 RK0
8596 19:23:08.456153
8597 19:23:08.459109 DATLAT Default: 0xf
8598 19:23:08.459185 0, 0xFFFF, sum = 0
8599 19:23:08.462221 1, 0xFFFF, sum = 0
8600 19:23:08.462300 2, 0xFFFF, sum = 0
8601 19:23:08.465544 3, 0xFFFF, sum = 0
8602 19:23:08.465646 4, 0xFFFF, sum = 0
8603 19:23:08.468831 5, 0xFFFF, sum = 0
8604 19:23:08.468936 6, 0xFFFF, sum = 0
8605 19:23:08.472337 7, 0xFFFF, sum = 0
8606 19:23:08.472422 8, 0xFFFF, sum = 0
8607 19:23:08.475893 9, 0xFFFF, sum = 0
8608 19:23:08.479586 10, 0xFFFF, sum = 0
8609 19:23:08.479679 11, 0xFFFF, sum = 0
8610 19:23:08.482485 12, 0xFFFF, sum = 0
8611 19:23:08.482654 13, 0xFFFF, sum = 0
8612 19:23:08.486005 14, 0x0, sum = 1
8613 19:23:08.486088 15, 0x0, sum = 2
8614 19:23:08.489118 16, 0x0, sum = 3
8615 19:23:08.489194 17, 0x0, sum = 4
8616 19:23:08.489282 best_step = 15
8617 19:23:08.492171
8618 19:23:08.492242 ==
8619 19:23:08.495852 Dram Type= 6, Freq= 0, CH_1, rank 0
8620 19:23:08.498997 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8621 19:23:08.499156 ==
8622 19:23:08.499283 RX Vref Scan: 1
8623 19:23:08.499392
8624 19:23:08.502719 Set Vref Range= 24 -> 127
8625 19:23:08.502802
8626 19:23:08.505763 RX Vref 24 -> 127, step: 1
8627 19:23:08.505845
8628 19:23:08.509086 RX Delay 11 -> 252, step: 4
8629 19:23:08.509170
8630 19:23:08.512700 Set Vref, RX VrefLevel [Byte0]: 24
8631 19:23:08.515749 [Byte1]: 24
8632 19:23:08.515836
8633 19:23:08.518949 Set Vref, RX VrefLevel [Byte0]: 25
8634 19:23:08.522650 [Byte1]: 25
8635 19:23:08.522735
8636 19:23:08.525730 Set Vref, RX VrefLevel [Byte0]: 26
8637 19:23:08.529330 [Byte1]: 26
8638 19:23:08.532812
8639 19:23:08.532893 Set Vref, RX VrefLevel [Byte0]: 27
8640 19:23:08.535814 [Byte1]: 27
8641 19:23:08.540086
8642 19:23:08.540195 Set Vref, RX VrefLevel [Byte0]: 28
8643 19:23:08.543639 [Byte1]: 28
8644 19:23:08.547726
8645 19:23:08.547809 Set Vref, RX VrefLevel [Byte0]: 29
8646 19:23:08.551335 [Byte1]: 29
8647 19:23:08.555481
8648 19:23:08.555566 Set Vref, RX VrefLevel [Byte0]: 30
8649 19:23:08.558912 [Byte1]: 30
8650 19:23:08.563144
8651 19:23:08.563226 Set Vref, RX VrefLevel [Byte0]: 31
8652 19:23:08.566341 [Byte1]: 31
8653 19:23:08.570507
8654 19:23:08.570590 Set Vref, RX VrefLevel [Byte0]: 32
8655 19:23:08.573973 [Byte1]: 32
8656 19:23:08.578508
8657 19:23:08.578594 Set Vref, RX VrefLevel [Byte0]: 33
8658 19:23:08.581653 [Byte1]: 33
8659 19:23:08.585863
8660 19:23:08.585949 Set Vref, RX VrefLevel [Byte0]: 34
8661 19:23:08.589359 [Byte1]: 34
8662 19:23:08.593351
8663 19:23:08.593438 Set Vref, RX VrefLevel [Byte0]: 35
8664 19:23:08.597092 [Byte1]: 35
8665 19:23:08.601437
8666 19:23:08.601524 Set Vref, RX VrefLevel [Byte0]: 36
8667 19:23:08.604289 [Byte1]: 36
8668 19:23:08.608547
8669 19:23:08.608650 Set Vref, RX VrefLevel [Byte0]: 37
8670 19:23:08.612254 [Byte1]: 37
8671 19:23:08.616620
8672 19:23:08.616703 Set Vref, RX VrefLevel [Byte0]: 38
8673 19:23:08.619721 [Byte1]: 38
8674 19:23:08.623957
8675 19:23:08.624044 Set Vref, RX VrefLevel [Byte0]: 39
8676 19:23:08.627010 [Byte1]: 39
8677 19:23:08.631351
8678 19:23:08.631440 Set Vref, RX VrefLevel [Byte0]: 40
8679 19:23:08.634971 [Byte1]: 40
8680 19:23:08.639337
8681 19:23:08.639416 Set Vref, RX VrefLevel [Byte0]: 41
8682 19:23:08.642811 [Byte1]: 41
8683 19:23:08.646566
8684 19:23:08.646672 Set Vref, RX VrefLevel [Byte0]: 42
8685 19:23:08.650227 [Byte1]: 42
8686 19:23:08.654226
8687 19:23:08.654320 Set Vref, RX VrefLevel [Byte0]: 43
8688 19:23:08.657451 [Byte1]: 43
8689 19:23:08.661703
8690 19:23:08.661785 Set Vref, RX VrefLevel [Byte0]: 44
8691 19:23:08.665355 [Byte1]: 44
8692 19:23:08.669246
8693 19:23:08.669340 Set Vref, RX VrefLevel [Byte0]: 45
8694 19:23:08.672702 [Byte1]: 45
8695 19:23:08.677051
8696 19:23:08.677177 Set Vref, RX VrefLevel [Byte0]: 46
8697 19:23:08.680432 [Byte1]: 46
8698 19:23:08.684731
8699 19:23:08.684834 Set Vref, RX VrefLevel [Byte0]: 47
8700 19:23:08.687795 [Byte1]: 47
8701 19:23:08.692695
8702 19:23:08.692780 Set Vref, RX VrefLevel [Byte0]: 48
8703 19:23:08.695623 [Byte1]: 48
8704 19:23:08.700065
8705 19:23:08.700183 Set Vref, RX VrefLevel [Byte0]: 49
8706 19:23:08.703693 [Byte1]: 49
8707 19:23:08.707468
8708 19:23:08.707554 Set Vref, RX VrefLevel [Byte0]: 50
8709 19:23:08.711219 [Byte1]: 50
8710 19:23:08.715491
8711 19:23:08.715578 Set Vref, RX VrefLevel [Byte0]: 51
8712 19:23:08.718487 [Byte1]: 51
8713 19:23:08.722930
8714 19:23:08.723019 Set Vref, RX VrefLevel [Byte0]: 52
8715 19:23:08.726089 [Byte1]: 52
8716 19:23:08.730504
8717 19:23:08.730592 Set Vref, RX VrefLevel [Byte0]: 53
8718 19:23:08.734113 [Byte1]: 53
8719 19:23:08.738280
8720 19:23:08.738367 Set Vref, RX VrefLevel [Byte0]: 54
8721 19:23:08.741596 [Byte1]: 54
8722 19:23:08.745381
8723 19:23:08.745468 Set Vref, RX VrefLevel [Byte0]: 55
8724 19:23:08.749076 [Byte1]: 55
8725 19:23:08.752928
8726 19:23:08.753016 Set Vref, RX VrefLevel [Byte0]: 56
8727 19:23:08.756253 [Byte1]: 56
8728 19:23:08.760900
8729 19:23:08.760988 Set Vref, RX VrefLevel [Byte0]: 57
8730 19:23:08.763999 [Byte1]: 57
8731 19:23:08.768354
8732 19:23:08.768441 Set Vref, RX VrefLevel [Byte0]: 58
8733 19:23:08.771980 [Byte1]: 58
8734 19:23:08.776446
8735 19:23:08.776533 Set Vref, RX VrefLevel [Byte0]: 59
8736 19:23:08.779494 [Byte1]: 59
8737 19:23:08.783521
8738 19:23:08.783607 Set Vref, RX VrefLevel [Byte0]: 60
8739 19:23:08.786917 [Byte1]: 60
8740 19:23:08.791169
8741 19:23:08.791256 Set Vref, RX VrefLevel [Byte0]: 61
8742 19:23:08.794500 [Byte1]: 61
8743 19:23:08.799294
8744 19:23:08.799382 Set Vref, RX VrefLevel [Byte0]: 62
8745 19:23:08.802169 [Byte1]: 62
8746 19:23:08.806174
8747 19:23:08.806333 Set Vref, RX VrefLevel [Byte0]: 63
8748 19:23:08.810036 [Byte1]: 63
8749 19:23:08.814366
8750 19:23:08.814466 Set Vref, RX VrefLevel [Byte0]: 64
8751 19:23:08.817438 [Byte1]: 64
8752 19:23:08.821836
8753 19:23:08.821941 Set Vref, RX VrefLevel [Byte0]: 65
8754 19:23:08.824899 [Byte1]: 65
8755 19:23:08.829187
8756 19:23:08.829316 Set Vref, RX VrefLevel [Byte0]: 66
8757 19:23:08.832971 [Byte1]: 66
8758 19:23:08.837159
8759 19:23:08.837295 Set Vref, RX VrefLevel [Byte0]: 67
8760 19:23:08.840386 [Byte1]: 67
8761 19:23:08.844561
8762 19:23:08.844647 Set Vref, RX VrefLevel [Byte0]: 68
8763 19:23:08.848104 [Byte1]: 68
8764 19:23:08.852234
8765 19:23:08.852319 Set Vref, RX VrefLevel [Byte0]: 69
8766 19:23:08.855654 [Byte1]: 69
8767 19:23:08.860101
8768 19:23:08.860183 Set Vref, RX VrefLevel [Byte0]: 70
8769 19:23:08.863391 [Byte1]: 70
8770 19:23:08.867344
8771 19:23:08.867423 Set Vref, RX VrefLevel [Byte0]: 71
8772 19:23:08.870670 [Byte1]: 71
8773 19:23:08.875159
8774 19:23:08.875264 Set Vref, RX VrefLevel [Byte0]: 72
8775 19:23:08.878211 [Byte1]: 72
8776 19:23:08.882485
8777 19:23:08.882592 Set Vref, RX VrefLevel [Byte0]: 73
8778 19:23:08.886223 [Byte1]: 73
8779 19:23:08.890541
8780 19:23:08.890632 Set Vref, RX VrefLevel [Byte0]: 74
8781 19:23:08.893448 [Byte1]: 74
8782 19:23:08.897957
8783 19:23:08.898038 Set Vref, RX VrefLevel [Byte0]: 75
8784 19:23:08.901107 [Byte1]: 75
8785 19:23:08.905378
8786 19:23:08.905487 Final RX Vref Byte 0 = 60 to rank0
8787 19:23:08.908892 Final RX Vref Byte 1 = 54 to rank0
8788 19:23:08.912137 Final RX Vref Byte 0 = 60 to rank1
8789 19:23:08.915375 Final RX Vref Byte 1 = 54 to rank1==
8790 19:23:08.918900 Dram Type= 6, Freq= 0, CH_1, rank 0
8791 19:23:08.926054 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8792 19:23:08.926148 ==
8793 19:23:08.926233 DQS Delay:
8794 19:23:08.926296 DQS0 = 0, DQS1 = 0
8795 19:23:08.929065 DQM Delay:
8796 19:23:08.929179 DQM0 = 131, DQM1 = 124
8797 19:23:08.932155 DQ Delay:
8798 19:23:08.935795 DQ0 =134, DQ1 =126, DQ2 =120, DQ3 =128
8799 19:23:08.939046 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =126
8800 19:23:08.942195 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =120
8801 19:23:08.945253 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =132
8802 19:23:08.945369
8803 19:23:08.945443
8804 19:23:08.945504
8805 19:23:08.948782 [DramC_TX_OE_Calibration] TA2
8806 19:23:08.952518 Original DQ_B0 (3 6) =30, OEN = 27
8807 19:23:08.955399 Original DQ_B1 (3 6) =30, OEN = 27
8808 19:23:08.958940 24, 0x0, End_B0=24 End_B1=24
8809 19:23:08.959041 25, 0x0, End_B0=25 End_B1=25
8810 19:23:08.962037 26, 0x0, End_B0=26 End_B1=26
8811 19:23:08.965444 27, 0x0, End_B0=27 End_B1=27
8812 19:23:08.968794 28, 0x0, End_B0=28 End_B1=28
8813 19:23:08.968882 29, 0x0, End_B0=29 End_B1=29
8814 19:23:08.972086 30, 0x0, End_B0=30 End_B1=30
8815 19:23:08.975492 31, 0x4141, End_B0=30 End_B1=30
8816 19:23:08.978664 Byte0 end_step=30 best_step=27
8817 19:23:08.982274 Byte1 end_step=30 best_step=27
8818 19:23:08.985717 Byte0 TX OE(2T, 0.5T) = (3, 3)
8819 19:23:08.985803 Byte1 TX OE(2T, 0.5T) = (3, 3)
8820 19:23:08.985868
8821 19:23:08.985929
8822 19:23:08.995943 [DQSOSCAuto] RK0, (LSB)MR18= 0x1701, (MSB)MR19= 0x303, tDQSOscB0 = 409 ps tDQSOscB1 = 398 ps
8823 19:23:08.998875 CH1 RK0: MR19=303, MR18=1701
8824 19:23:09.005365 CH1_RK0: MR19=0x303, MR18=0x1701, DQSOSC=398, MR23=63, INC=23, DEC=15
8825 19:23:09.005486
8826 19:23:09.009034 ----->DramcWriteLeveling(PI) begin...
8827 19:23:09.009120 ==
8828 19:23:09.012055 Dram Type= 6, Freq= 0, CH_1, rank 1
8829 19:23:09.015245 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8830 19:23:09.015330 ==
8831 19:23:09.018977 Write leveling (Byte 0): 26 => 26
8832 19:23:09.022075 Write leveling (Byte 1): 26 => 26
8833 19:23:09.025351 DramcWriteLeveling(PI) end<-----
8834 19:23:09.025439
8835 19:23:09.025506 ==
8836 19:23:09.028726 Dram Type= 6, Freq= 0, CH_1, rank 1
8837 19:23:09.031965 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8838 19:23:09.032051 ==
8839 19:23:09.035233 [Gating] SW mode calibration
8840 19:23:09.042232 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8841 19:23:09.049014 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8842 19:23:09.052101 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8843 19:23:09.055869 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8844 19:23:09.062494 1 4 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
8845 19:23:09.065704 1 4 12 | B1->B0 | 2a2a 3434 | 1 1 | (1 1) (1 1)
8846 19:23:09.069200 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8847 19:23:09.075920 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8848 19:23:09.079179 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8849 19:23:09.082111 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8850 19:23:09.085734 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8851 19:23:09.092078 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8852 19:23:09.095988 1 5 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
8853 19:23:09.099082 1 5 12 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
8854 19:23:09.105915 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8855 19:23:09.108957 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8856 19:23:09.112397 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8857 19:23:09.118882 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8858 19:23:09.122662 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8859 19:23:09.125815 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8860 19:23:09.132706 1 6 8 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
8861 19:23:09.135658 1 6 12 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
8862 19:23:09.139316 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8863 19:23:09.145777 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8864 19:23:09.149014 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8865 19:23:09.152382 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8866 19:23:09.159102 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8867 19:23:09.162121 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8868 19:23:09.165653 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8869 19:23:09.172335 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8870 19:23:09.175489 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8871 19:23:09.179212 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8872 19:23:09.182243 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8873 19:23:09.189218 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8874 19:23:09.192245 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8875 19:23:09.195803 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8876 19:23:09.202207 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8877 19:23:09.205688 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8878 19:23:09.209325 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8879 19:23:09.215421 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8880 19:23:09.219063 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8881 19:23:09.222065 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8882 19:23:09.228723 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8883 19:23:09.232352 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8884 19:23:09.235460 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8885 19:23:09.241920 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8886 19:23:09.242007 Total UI for P1: 0, mck2ui 16
8887 19:23:09.248808 best dqsien dly found for B0: ( 1, 9, 6)
8888 19:23:09.252385 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8889 19:23:09.255657 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8890 19:23:09.259160 Total UI for P1: 0, mck2ui 16
8891 19:23:09.262004 best dqsien dly found for B1: ( 1, 9, 14)
8892 19:23:09.265538 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8893 19:23:09.269190 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8894 19:23:09.269292
8895 19:23:09.272048 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8896 19:23:09.278981 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8897 19:23:09.279071 [Gating] SW calibration Done
8898 19:23:09.279135 ==
8899 19:23:09.282567 Dram Type= 6, Freq= 0, CH_1, rank 1
8900 19:23:09.289088 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8901 19:23:09.289215 ==
8902 19:23:09.289306 RX Vref Scan: 0
8903 19:23:09.289366
8904 19:23:09.292279 RX Vref 0 -> 0, step: 1
8905 19:23:09.292354
8906 19:23:09.295768 RX Delay 0 -> 252, step: 8
8907 19:23:09.298909 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8908 19:23:09.302524 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8909 19:23:09.305425 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8910 19:23:09.308886 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8911 19:23:09.315894 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8912 19:23:09.318794 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8913 19:23:09.322386 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8914 19:23:09.326064 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8915 19:23:09.329130 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8916 19:23:09.335747 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8917 19:23:09.338931 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8918 19:23:09.342444 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8919 19:23:09.346056 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8920 19:23:09.349252 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8921 19:23:09.355872 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8922 19:23:09.359321 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8923 19:23:09.359427 ==
8924 19:23:09.362706 Dram Type= 6, Freq= 0, CH_1, rank 1
8925 19:23:09.365628 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8926 19:23:09.365710 ==
8927 19:23:09.369013 DQS Delay:
8928 19:23:09.369088 DQS0 = 0, DQS1 = 0
8929 19:23:09.369151 DQM Delay:
8930 19:23:09.372403 DQM0 = 133, DQM1 = 127
8931 19:23:09.372489 DQ Delay:
8932 19:23:09.375514 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =135
8933 19:23:09.379114 DQ4 =131, DQ5 =147, DQ6 =143, DQ7 =127
8934 19:23:09.382086 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8935 19:23:09.389011 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8936 19:23:09.389100
8937 19:23:09.389214
8938 19:23:09.389294 ==
8939 19:23:09.392650 Dram Type= 6, Freq= 0, CH_1, rank 1
8940 19:23:09.395594 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8941 19:23:09.395669 ==
8942 19:23:09.395732
8943 19:23:09.395798
8944 19:23:09.398959 TX Vref Scan disable
8945 19:23:09.399034 == TX Byte 0 ==
8946 19:23:09.405631 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8947 19:23:09.409326 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8948 19:23:09.409404 == TX Byte 1 ==
8949 19:23:09.416009 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8950 19:23:09.419040 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8951 19:23:09.419117 ==
8952 19:23:09.422623 Dram Type= 6, Freq= 0, CH_1, rank 1
8953 19:23:09.425960 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8954 19:23:09.426045 ==
8955 19:23:09.440568
8956 19:23:09.443581 TX Vref early break, caculate TX vref
8957 19:23:09.446726 TX Vref=16, minBit 0, minWin=22, winSum=382
8958 19:23:09.450221 TX Vref=18, minBit 0, minWin=24, winSum=395
8959 19:23:09.453887 TX Vref=20, minBit 1, minWin=24, winSum=396
8960 19:23:09.457045 TX Vref=22, minBit 8, minWin=24, winSum=404
8961 19:23:09.460061 TX Vref=24, minBit 0, minWin=25, winSum=414
8962 19:23:09.466956 TX Vref=26, minBit 0, minWin=25, winSum=423
8963 19:23:09.470496 TX Vref=28, minBit 0, minWin=25, winSum=424
8964 19:23:09.473505 TX Vref=30, minBit 0, minWin=26, winSum=427
8965 19:23:09.477009 TX Vref=32, minBit 0, minWin=25, winSum=420
8966 19:23:09.480507 TX Vref=34, minBit 0, minWin=25, winSum=406
8967 19:23:09.483630 TX Vref=36, minBit 0, minWin=24, winSum=401
8968 19:23:09.490111 [TxChooseVref] Worse bit 0, Min win 26, Win sum 427, Final Vref 30
8969 19:23:09.490240
8970 19:23:09.493685 Final TX Range 0 Vref 30
8971 19:23:09.493792
8972 19:23:09.493858 ==
8973 19:23:09.496746 Dram Type= 6, Freq= 0, CH_1, rank 1
8974 19:23:09.499966 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8975 19:23:09.500062 ==
8976 19:23:09.500133
8977 19:23:09.500201
8978 19:23:09.503603 TX Vref Scan disable
8979 19:23:09.509931 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8980 19:23:09.510018 == TX Byte 0 ==
8981 19:23:09.513246 u2DelayCellOfst[0]=21 cells (6 PI)
8982 19:23:09.516640 u2DelayCellOfst[1]=14 cells (4 PI)
8983 19:23:09.520473 u2DelayCellOfst[2]=0 cells (0 PI)
8984 19:23:09.523443 u2DelayCellOfst[3]=10 cells (3 PI)
8985 19:23:09.527138 u2DelayCellOfst[4]=10 cells (3 PI)
8986 19:23:09.530203 u2DelayCellOfst[5]=21 cells (6 PI)
8987 19:23:09.533677 u2DelayCellOfst[6]=21 cells (6 PI)
8988 19:23:09.536818 u2DelayCellOfst[7]=7 cells (2 PI)
8989 19:23:09.539846 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8990 19:23:09.543670 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8991 19:23:09.546818 == TX Byte 1 ==
8992 19:23:09.546899 u2DelayCellOfst[8]=0 cells (0 PI)
8993 19:23:09.549960 u2DelayCellOfst[9]=3 cells (1 PI)
8994 19:23:09.553364 u2DelayCellOfst[10]=10 cells (3 PI)
8995 19:23:09.557131 u2DelayCellOfst[11]=3 cells (1 PI)
8996 19:23:09.560244 u2DelayCellOfst[12]=14 cells (4 PI)
8997 19:23:09.563393 u2DelayCellOfst[13]=14 cells (4 PI)
8998 19:23:09.567057 u2DelayCellOfst[14]=17 cells (5 PI)
8999 19:23:09.570009 u2DelayCellOfst[15]=14 cells (4 PI)
9000 19:23:09.573352 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
9001 19:23:09.580417 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
9002 19:23:09.580512 DramC Write-DBI on
9003 19:23:09.580599 ==
9004 19:23:09.583457 Dram Type= 6, Freq= 0, CH_1, rank 1
9005 19:23:09.587037 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9006 19:23:09.589943 ==
9007 19:23:09.590029
9008 19:23:09.590116
9009 19:23:09.590196 TX Vref Scan disable
9010 19:23:09.593186 == TX Byte 0 ==
9011 19:23:09.596727 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
9012 19:23:09.600365 == TX Byte 1 ==
9013 19:23:09.603416 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
9014 19:23:09.603506 DramC Write-DBI off
9015 19:23:09.607282
9016 19:23:09.607368 [DATLAT]
9017 19:23:09.607454 Freq=1600, CH1 RK1
9018 19:23:09.607537
9019 19:23:09.610352 DATLAT Default: 0xf
9020 19:23:09.610437 0, 0xFFFF, sum = 0
9021 19:23:09.613225 1, 0xFFFF, sum = 0
9022 19:23:09.613326 2, 0xFFFF, sum = 0
9023 19:23:09.616531 3, 0xFFFF, sum = 0
9024 19:23:09.619841 4, 0xFFFF, sum = 0
9025 19:23:09.619935 5, 0xFFFF, sum = 0
9026 19:23:09.623334 6, 0xFFFF, sum = 0
9027 19:23:09.623524 7, 0xFFFF, sum = 0
9028 19:23:09.626659 8, 0xFFFF, sum = 0
9029 19:23:09.626763 9, 0xFFFF, sum = 0
9030 19:23:09.630205 10, 0xFFFF, sum = 0
9031 19:23:09.630292 11, 0xFFFF, sum = 0
9032 19:23:09.633586 12, 0xFFFF, sum = 0
9033 19:23:09.633671 13, 0xFFFF, sum = 0
9034 19:23:09.636615 14, 0x0, sum = 1
9035 19:23:09.636701 15, 0x0, sum = 2
9036 19:23:09.640251 16, 0x0, sum = 3
9037 19:23:09.640336 17, 0x0, sum = 4
9038 19:23:09.643541 best_step = 15
9039 19:23:09.643654
9040 19:23:09.643748 ==
9041 19:23:09.646809 Dram Type= 6, Freq= 0, CH_1, rank 1
9042 19:23:09.649948 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9043 19:23:09.650033 ==
9044 19:23:09.650100 RX Vref Scan: 0
9045 19:23:09.650161
9046 19:23:09.653453 RX Vref 0 -> 0, step: 1
9047 19:23:09.653538
9048 19:23:09.656926 RX Delay 11 -> 252, step: 4
9049 19:23:09.659919 iDelay=195, Bit 0, Center 132 (83 ~ 182) 100
9050 19:23:09.666673 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
9051 19:23:09.670388 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
9052 19:23:09.673372 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
9053 19:23:09.676820 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
9054 19:23:09.680271 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
9055 19:23:09.683338 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
9056 19:23:09.690477 iDelay=195, Bit 7, Center 126 (75 ~ 178) 104
9057 19:23:09.693356 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
9058 19:23:09.696839 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
9059 19:23:09.700181 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9060 19:23:09.703614 iDelay=195, Bit 11, Center 118 (67 ~ 170) 104
9061 19:23:09.710046 iDelay=195, Bit 12, Center 134 (83 ~ 186) 104
9062 19:23:09.713560 iDelay=195, Bit 13, Center 134 (83 ~ 186) 104
9063 19:23:09.716680 iDelay=195, Bit 14, Center 134 (83 ~ 186) 104
9064 19:23:09.720316 iDelay=195, Bit 15, Center 134 (83 ~ 186) 104
9065 19:23:09.720453 ==
9066 19:23:09.723228 Dram Type= 6, Freq= 0, CH_1, rank 1
9067 19:23:09.730193 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9068 19:23:09.730349 ==
9069 19:23:09.730471 DQS Delay:
9070 19:23:09.733900 DQS0 = 0, DQS1 = 0
9071 19:23:09.734038 DQM Delay:
9072 19:23:09.736797 DQM0 = 130, DQM1 = 126
9073 19:23:09.736955 DQ Delay:
9074 19:23:09.739672 DQ0 =132, DQ1 =126, DQ2 =118, DQ3 =126
9075 19:23:09.743160 DQ4 =130, DQ5 =144, DQ6 =138, DQ7 =126
9076 19:23:09.746813 DQ8 =114, DQ9 =112, DQ10 =128, DQ11 =118
9077 19:23:09.749881 DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =134
9078 19:23:09.750053
9079 19:23:09.750172
9080 19:23:09.750285
9081 19:23:09.753153 [DramC_TX_OE_Calibration] TA2
9082 19:23:09.756584 Original DQ_B0 (3 6) =30, OEN = 27
9083 19:23:09.760075 Original DQ_B1 (3 6) =30, OEN = 27
9084 19:23:09.763522 24, 0x0, End_B0=24 End_B1=24
9085 19:23:09.763657 25, 0x0, End_B0=25 End_B1=25
9086 19:23:09.766559 26, 0x0, End_B0=26 End_B1=26
9087 19:23:09.770159 27, 0x0, End_B0=27 End_B1=27
9088 19:23:09.773237 28, 0x0, End_B0=28 End_B1=28
9089 19:23:09.776892 29, 0x0, End_B0=29 End_B1=29
9090 19:23:09.777023 30, 0x0, End_B0=30 End_B1=30
9091 19:23:09.779872 31, 0x4141, End_B0=30 End_B1=30
9092 19:23:09.783479 Byte0 end_step=30 best_step=27
9093 19:23:09.786918 Byte1 end_step=30 best_step=27
9094 19:23:09.789887 Byte0 TX OE(2T, 0.5T) = (3, 3)
9095 19:23:09.793304 Byte1 TX OE(2T, 0.5T) = (3, 3)
9096 19:23:09.793435
9097 19:23:09.793552
9098 19:23:09.800214 [DQSOSCAuto] RK1, (LSB)MR18= 0x1117, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 401 ps
9099 19:23:09.803271 CH1 RK1: MR19=303, MR18=1117
9100 19:23:09.809898 CH1_RK1: MR19=0x303, MR18=0x1117, DQSOSC=398, MR23=63, INC=23, DEC=15
9101 19:23:09.813331 [RxdqsGatingPostProcess] freq 1600
9102 19:23:09.816652 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9103 19:23:09.819722 best DQS0 dly(2T, 0.5T) = (1, 1)
9104 19:23:09.823403 best DQS1 dly(2T, 0.5T) = (1, 1)
9105 19:23:09.826322 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9106 19:23:09.829940 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9107 19:23:09.833060 best DQS0 dly(2T, 0.5T) = (1, 1)
9108 19:23:09.836538 best DQS1 dly(2T, 0.5T) = (1, 1)
9109 19:23:09.840051 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9110 19:23:09.842850 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9111 19:23:09.846415 Pre-setting of DQS Precalculation
9112 19:23:09.849569 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9113 19:23:09.856102 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9114 19:23:09.866264 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9115 19:23:09.866387
9116 19:23:09.866456
9117 19:23:09.866518 [Calibration Summary] 3200 Mbps
9118 19:23:09.870045 CH 0, Rank 0
9119 19:23:09.870122 SW Impedance : PASS
9120 19:23:09.873107 DUTY Scan : NO K
9121 19:23:09.876123 ZQ Calibration : PASS
9122 19:23:09.876227 Jitter Meter : NO K
9123 19:23:09.879769 CBT Training : PASS
9124 19:23:09.883284 Write leveling : PASS
9125 19:23:09.883360 RX DQS gating : PASS
9126 19:23:09.886852 RX DQ/DQS(RDDQC) : PASS
9127 19:23:09.889640 TX DQ/DQS : PASS
9128 19:23:09.889727 RX DATLAT : PASS
9129 19:23:09.893103 RX DQ/DQS(Engine): PASS
9130 19:23:09.896678 TX OE : PASS
9131 19:23:09.896767 All Pass.
9132 19:23:09.896833
9133 19:23:09.896895 CH 0, Rank 1
9134 19:23:09.899874 SW Impedance : PASS
9135 19:23:09.903331 DUTY Scan : NO K
9136 19:23:09.903452 ZQ Calibration : PASS
9137 19:23:09.906504 Jitter Meter : NO K
9138 19:23:09.909531 CBT Training : PASS
9139 19:23:09.909617 Write leveling : PASS
9140 19:23:09.912981 RX DQS gating : PASS
9141 19:23:09.913059 RX DQ/DQS(RDDQC) : PASS
9142 19:23:09.916121 TX DQ/DQS : PASS
9143 19:23:09.919969 RX DATLAT : PASS
9144 19:23:09.920057 RX DQ/DQS(Engine): PASS
9145 19:23:09.923498 TX OE : PASS
9146 19:23:09.923585 All Pass.
9147 19:23:09.923652
9148 19:23:09.926608 CH 1, Rank 0
9149 19:23:09.926695 SW Impedance : PASS
9150 19:23:09.929446 DUTY Scan : NO K
9151 19:23:09.933138 ZQ Calibration : PASS
9152 19:23:09.933253 Jitter Meter : NO K
9153 19:23:09.936789 CBT Training : PASS
9154 19:23:09.939794 Write leveling : PASS
9155 19:23:09.939906 RX DQS gating : PASS
9156 19:23:09.943260 RX DQ/DQS(RDDQC) : PASS
9157 19:23:09.946231 TX DQ/DQS : PASS
9158 19:23:09.946317 RX DATLAT : PASS
9159 19:23:09.949787 RX DQ/DQS(Engine): PASS
9160 19:23:09.949873 TX OE : PASS
9161 19:23:09.952932 All Pass.
9162 19:23:09.953022
9163 19:23:09.953125 CH 1, Rank 1
9164 19:23:09.956666 SW Impedance : PASS
9165 19:23:09.956744 DUTY Scan : NO K
9166 19:23:09.959579 ZQ Calibration : PASS
9167 19:23:09.963118 Jitter Meter : NO K
9168 19:23:09.963208 CBT Training : PASS
9169 19:23:09.966769 Write leveling : PASS
9170 19:23:09.969603 RX DQS gating : PASS
9171 19:23:09.969718 RX DQ/DQS(RDDQC) : PASS
9172 19:23:09.973257 TX DQ/DQS : PASS
9173 19:23:09.976551 RX DATLAT : PASS
9174 19:23:09.976638 RX DQ/DQS(Engine): PASS
9175 19:23:09.980345 TX OE : PASS
9176 19:23:09.980458 All Pass.
9177 19:23:09.980534
9178 19:23:09.983498 DramC Write-DBI on
9179 19:23:09.986514 PER_BANK_REFRESH: Hybrid Mode
9180 19:23:09.986598 TX_TRACKING: ON
9181 19:23:09.996760 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9182 19:23:10.003221 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9183 19:23:10.009831 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9184 19:23:10.013307 [FAST_K] Save calibration result to emmc
9185 19:23:10.016813 sync common calibartion params.
9186 19:23:10.020181 sync cbt_mode0:1, 1:1
9187 19:23:10.020270 dram_init: ddr_geometry: 2
9188 19:23:10.023051 dram_init: ddr_geometry: 2
9189 19:23:10.026443 dram_init: ddr_geometry: 2
9190 19:23:10.029985 0:dram_rank_size:100000000
9191 19:23:10.030080 1:dram_rank_size:100000000
9192 19:23:10.036439 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9193 19:23:10.040298 DFS_SHUFFLE_HW_MODE: ON
9194 19:23:10.043166 dramc_set_vcore_voltage set vcore to 725000
9195 19:23:10.046844 Read voltage for 1600, 0
9196 19:23:10.046953 Vio18 = 0
9197 19:23:10.047034 Vcore = 725000
9198 19:23:10.047096 Vdram = 0
9199 19:23:10.050297 Vddq = 0
9200 19:23:10.050382 Vmddr = 0
9201 19:23:10.053119 switch to 3200 Mbps bootup
9202 19:23:10.053214 [DramcRunTimeConfig]
9203 19:23:10.056835 PHYPLL
9204 19:23:10.056919 DPM_CONTROL_AFTERK: ON
9205 19:23:10.059880 PER_BANK_REFRESH: ON
9206 19:23:10.063355 REFRESH_OVERHEAD_REDUCTION: ON
9207 19:23:10.063440 CMD_PICG_NEW_MODE: OFF
9208 19:23:10.066629 XRTWTW_NEW_MODE: ON
9209 19:23:10.066713 XRTRTR_NEW_MODE: ON
9210 19:23:10.070112 TX_TRACKING: ON
9211 19:23:10.070199 RDSEL_TRACKING: OFF
9212 19:23:10.073589 DQS Precalculation for DVFS: ON
9213 19:23:10.076594 RX_TRACKING: OFF
9214 19:23:10.076679 HW_GATING DBG: ON
9215 19:23:10.079828 ZQCS_ENABLE_LP4: ON
9216 19:23:10.079912 RX_PICG_NEW_MODE: ON
9217 19:23:10.083782 TX_PICG_NEW_MODE: ON
9218 19:23:10.083869 ENABLE_RX_DCM_DPHY: ON
9219 19:23:10.086735 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9220 19:23:10.090242 DUMMY_READ_FOR_TRACKING: OFF
9221 19:23:10.093406 !!! SPM_CONTROL_AFTERK: OFF
9222 19:23:10.096989 !!! SPM could not control APHY
9223 19:23:10.097085 IMPEDANCE_TRACKING: ON
9224 19:23:10.099893 TEMP_SENSOR: ON
9225 19:23:10.099978 HW_SAVE_FOR_SR: OFF
9226 19:23:10.103096 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9227 19:23:10.106746 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9228 19:23:10.110306 Read ODT Tracking: ON
9229 19:23:10.113319 Refresh Rate DeBounce: ON
9230 19:23:10.113423 DFS_NO_QUEUE_FLUSH: ON
9231 19:23:10.116799 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9232 19:23:10.119817 ENABLE_DFS_RUNTIME_MRW: OFF
9233 19:23:10.123125 DDR_RESERVE_NEW_MODE: ON
9234 19:23:10.123247 MR_CBT_SWITCH_FREQ: ON
9235 19:23:10.126432 =========================
9236 19:23:10.145162 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9237 19:23:10.148408 dram_init: ddr_geometry: 2
9238 19:23:10.166591 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9239 19:23:10.170173 dram_init: dram init end (result: 0)
9240 19:23:10.176517 DRAM-K: Full calibration passed in 24581 msecs
9241 19:23:10.179827 MRC: failed to locate region type 0.
9242 19:23:10.179908 DRAM rank0 size:0x100000000,
9243 19:23:10.183285 DRAM rank1 size=0x100000000
9244 19:23:10.193609 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9245 19:23:10.200121 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9246 19:23:10.206823 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9247 19:23:10.213023 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9248 19:23:10.216438 DRAM rank0 size:0x100000000,
9249 19:23:10.220037 DRAM rank1 size=0x100000000
9250 19:23:10.220118 CBMEM:
9251 19:23:10.223082 IMD: root @ 0xfffff000 254 entries.
9252 19:23:10.226925 IMD: root @ 0xffffec00 62 entries.
9253 19:23:10.230143 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9254 19:23:10.233390 WARNING: RO_VPD is uninitialized or empty.
9255 19:23:10.239738 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9256 19:23:10.246480 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9257 19:23:10.259510 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9258 19:23:10.270612 BS: romstage times (exec / console): total (unknown) / 24086 ms
9259 19:23:10.270741
9260 19:23:10.270811
9261 19:23:10.281070 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9262 19:23:10.284221 ARM64: Exception handlers installed.
9263 19:23:10.287682 ARM64: Testing exception
9264 19:23:10.291097 ARM64: Done test exception
9265 19:23:10.291204 Enumerating buses...
9266 19:23:10.294258 Show all devs... Before device enumeration.
9267 19:23:10.297258 Root Device: enabled 1
9268 19:23:10.300600 CPU_CLUSTER: 0: enabled 1
9269 19:23:10.300684 CPU: 00: enabled 1
9270 19:23:10.303944 Compare with tree...
9271 19:23:10.304022 Root Device: enabled 1
9272 19:23:10.307634 CPU_CLUSTER: 0: enabled 1
9273 19:23:10.311080 CPU: 00: enabled 1
9274 19:23:10.311162 Root Device scanning...
9275 19:23:10.313908 scan_static_bus for Root Device
9276 19:23:10.317395 CPU_CLUSTER: 0 enabled
9277 19:23:10.320907 scan_static_bus for Root Device done
9278 19:23:10.324465 scan_bus: bus Root Device finished in 8 msecs
9279 19:23:10.324558 done
9280 19:23:10.331362 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9281 19:23:10.334163 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9282 19:23:10.340833 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9283 19:23:10.344174 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9284 19:23:10.347184 Allocating resources...
9285 19:23:10.347272 Reading resources...
9286 19:23:10.353830 Root Device read_resources bus 0 link: 0
9287 19:23:10.353928 DRAM rank0 size:0x100000000,
9288 19:23:10.357301 DRAM rank1 size=0x100000000
9289 19:23:10.360944 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9290 19:23:10.363817 CPU: 00 missing read_resources
9291 19:23:10.367451 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9292 19:23:10.374144 Root Device read_resources bus 0 link: 0 done
9293 19:23:10.374234 Done reading resources.
9294 19:23:10.380820 Show resources in subtree (Root Device)...After reading.
9295 19:23:10.383890 Root Device child on link 0 CPU_CLUSTER: 0
9296 19:23:10.387455 CPU_CLUSTER: 0 child on link 0 CPU: 00
9297 19:23:10.397201 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9298 19:23:10.397334 CPU: 00
9299 19:23:10.400503 Root Device assign_resources, bus 0 link: 0
9300 19:23:10.404263 CPU_CLUSTER: 0 missing set_resources
9301 19:23:10.407239 Root Device assign_resources, bus 0 link: 0 done
9302 19:23:10.410608 Done setting resources.
9303 19:23:10.417223 Show resources in subtree (Root Device)...After assigning values.
9304 19:23:10.420777 Root Device child on link 0 CPU_CLUSTER: 0
9305 19:23:10.424223 CPU_CLUSTER: 0 child on link 0 CPU: 00
9306 19:23:10.434411 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9307 19:23:10.434532 CPU: 00
9308 19:23:10.437388 Done allocating resources.
9309 19:23:10.441007 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9310 19:23:10.444000 Enabling resources...
9311 19:23:10.444114 done.
9312 19:23:10.447596 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9313 19:23:10.451276 Initializing devices...
9314 19:23:10.454239 Root Device init
9315 19:23:10.454357 init hardware done!
9316 19:23:10.457767 0x00000018: ctrlr->caps
9317 19:23:10.457845 52.000 MHz: ctrlr->f_max
9318 19:23:10.460915 0.400 MHz: ctrlr->f_min
9319 19:23:10.464018 0x40ff8080: ctrlr->voltages
9320 19:23:10.464150 sclk: 390625
9321 19:23:10.467931 Bus Width = 1
9322 19:23:10.468093 sclk: 390625
9323 19:23:10.468229 Bus Width = 1
9324 19:23:10.470822 Early init status = 3
9325 19:23:10.474423 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9326 19:23:10.479386 in-header: 03 fc 00 00 01 00 00 00
9327 19:23:10.482244 in-data: 00
9328 19:23:10.485943 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9329 19:23:10.491521 in-header: 03 fd 00 00 00 00 00 00
9330 19:23:10.494514 in-data:
9331 19:23:10.497908 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9332 19:23:10.502334 in-header: 03 fc 00 00 01 00 00 00
9333 19:23:10.505841 in-data: 00
9334 19:23:10.509338 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9335 19:23:10.514701 in-header: 03 fd 00 00 00 00 00 00
9336 19:23:10.517636 in-data:
9337 19:23:10.521083 [SSUSB] Setting up USB HOST controller...
9338 19:23:10.524412 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9339 19:23:10.527949 [SSUSB] phy power-on done.
9340 19:23:10.531341 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9341 19:23:10.537845 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9342 19:23:10.541508 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9343 19:23:10.548041 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9344 19:23:10.554590 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9345 19:23:10.561103 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9346 19:23:10.567754 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9347 19:23:10.574336 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9348 19:23:10.574453 SPM: binary array size = 0x9dc
9349 19:23:10.580922 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9350 19:23:10.587638 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9351 19:23:10.594477 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9352 19:23:10.597600 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9353 19:23:10.604115 configure_display: Starting display init
9354 19:23:10.638223 anx7625_power_on_init: Init interface.
9355 19:23:10.641139 anx7625_disable_pd_protocol: Disabled PD feature.
9356 19:23:10.644488 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9357 19:23:10.672414 anx7625_start_dp_work: Secure OCM version=00
9358 19:23:10.675327 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9359 19:23:10.690439 sp_tx_get_edid_block: EDID Block = 1
9360 19:23:10.793061 Extracted contents:
9361 19:23:10.796441 header: 00 ff ff ff ff ff ff 00
9362 19:23:10.799337 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9363 19:23:10.802885 version: 01 04
9364 19:23:10.806426 basic params: 95 1f 11 78 0a
9365 19:23:10.809376 chroma info: 76 90 94 55 54 90 27 21 50 54
9366 19:23:10.812957 established: 00 00 00
9367 19:23:10.819663 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9368 19:23:10.822631 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9369 19:23:10.829623 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9370 19:23:10.836259 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9371 19:23:10.842993 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9372 19:23:10.846123 extensions: 00
9373 19:23:10.846216 checksum: fb
9374 19:23:10.846283
9375 19:23:10.849696 Manufacturer: IVO Model 57d Serial Number 0
9376 19:23:10.853395 Made week 0 of 2020
9377 19:23:10.853485 EDID version: 1.4
9378 19:23:10.856043 Digital display
9379 19:23:10.859618 6 bits per primary color channel
9380 19:23:10.859701 DisplayPort interface
9381 19:23:10.863229 Maximum image size: 31 cm x 17 cm
9382 19:23:10.863313 Gamma: 220%
9383 19:23:10.866454 Check DPMS levels
9384 19:23:10.869532 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9385 19:23:10.872987 First detailed timing is preferred timing
9386 19:23:10.876274 Established timings supported:
9387 19:23:10.879408 Standard timings supported:
9388 19:23:10.879562 Detailed timings
9389 19:23:10.886057 Hex of detail: 383680a07038204018303c0035ae10000019
9390 19:23:10.889504 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9391 19:23:10.893109 0780 0798 07c8 0820 hborder 0
9392 19:23:10.899470 0438 043b 0447 0458 vborder 0
9393 19:23:10.899637 -hsync -vsync
9394 19:23:10.902915 Did detailed timing
9395 19:23:10.906421 Hex of detail: 000000000000000000000000000000000000
9396 19:23:10.909473 Manufacturer-specified data, tag 0
9397 19:23:10.916184 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9398 19:23:10.916328 ASCII string: InfoVision
9399 19:23:10.922741 Hex of detail: 000000fe00523134304e574635205248200a
9400 19:23:10.922897 ASCII string: R140NWF5 RH
9401 19:23:10.926288 Checksum
9402 19:23:10.926433 Checksum: 0xfb (valid)
9403 19:23:10.933038 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9404 19:23:10.933204 DSI data_rate: 832800000 bps
9405 19:23:10.940231 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9406 19:23:10.943762 anx7625_parse_edid: pixelclock(138800).
9407 19:23:10.946959 hactive(1920), hsync(48), hfp(24), hbp(88)
9408 19:23:10.950615 vactive(1080), vsync(12), vfp(3), vbp(17)
9409 19:23:10.954156 anx7625_dsi_config: config dsi.
9410 19:23:10.960466 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9411 19:23:10.975242 anx7625_dsi_config: success to config DSI
9412 19:23:10.978459 anx7625_dp_start: MIPI phy setup OK.
9413 19:23:10.981925 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9414 19:23:10.984644 mtk_ddp_mode_set invalid vrefresh 60
9415 19:23:10.988081 main_disp_path_setup
9416 19:23:10.988215 ovl_layer_smi_id_en
9417 19:23:10.991434 ovl_layer_smi_id_en
9418 19:23:10.991568 ccorr_config
9419 19:23:10.991686 aal_config
9420 19:23:10.994840 gamma_config
9421 19:23:10.994975 postmask_config
9422 19:23:10.997919 dither_config
9423 19:23:11.001427 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9424 19:23:11.008206 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9425 19:23:11.011598 Root Device init finished in 555 msecs
9426 19:23:11.014580 CPU_CLUSTER: 0 init
9427 19:23:11.021301 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9428 19:23:11.024632 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9429 19:23:11.027915 APU_MBOX 0x190000b0 = 0x10001
9430 19:23:11.031462 APU_MBOX 0x190001b0 = 0x10001
9431 19:23:11.034536 APU_MBOX 0x190005b0 = 0x10001
9432 19:23:11.038199 APU_MBOX 0x190006b0 = 0x10001
9433 19:23:11.041131 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9434 19:23:11.053646 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9435 19:23:11.066422 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9436 19:23:11.073160 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9437 19:23:11.084605 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9438 19:23:11.093590 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9439 19:23:11.097086 CPU_CLUSTER: 0 init finished in 81 msecs
9440 19:23:11.100197 Devices initialized
9441 19:23:11.103867 Show all devs... After init.
9442 19:23:11.104048 Root Device: enabled 1
9443 19:23:11.107247 CPU_CLUSTER: 0: enabled 1
9444 19:23:11.110314 CPU: 00: enabled 1
9445 19:23:11.113736 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9446 19:23:11.116882 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9447 19:23:11.120051 ELOG: NV offset 0x57f000 size 0x1000
9448 19:23:11.126820 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9449 19:23:11.133641 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9450 19:23:11.136744 ELOG: Event(17) added with size 13 at 2024-04-18 19:23:10 UTC
9451 19:23:11.140027 out: cmd=0x121: 03 db 21 01 00 00 00 00
9452 19:23:11.145030 in-header: 03 cc 00 00 2c 00 00 00
9453 19:23:11.158295 in-data: 92 69 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9454 19:23:11.165111 ELOG: Event(A1) added with size 10 at 2024-04-18 19:23:10 UTC
9455 19:23:11.171319 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9456 19:23:11.178370 ELOG: Event(A0) added with size 9 at 2024-04-18 19:23:10 UTC
9457 19:23:11.182129 elog_add_boot_reason: Logged dev mode boot
9458 19:23:11.185072 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9459 19:23:11.188130 Finalize devices...
9460 19:23:11.188214 Devices finalized
9461 19:23:11.195166 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9462 19:23:11.198118 Writing coreboot table at 0xffe64000
9463 19:23:11.201719 0. 000000000010a000-0000000000113fff: RAMSTAGE
9464 19:23:11.204742 1. 0000000040000000-00000000400fffff: RAM
9465 19:23:11.208156 2. 0000000040100000-000000004032afff: RAMSTAGE
9466 19:23:11.215278 3. 000000004032b000-00000000545fffff: RAM
9467 19:23:11.218225 4. 0000000054600000-000000005465ffff: BL31
9468 19:23:11.221581 5. 0000000054660000-00000000ffe63fff: RAM
9469 19:23:11.228264 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9470 19:23:11.231281 7. 0000000100000000-000000023fffffff: RAM
9471 19:23:11.231372 Passing 5 GPIOs to payload:
9472 19:23:11.238286 NAME | PORT | POLARITY | VALUE
9473 19:23:11.241625 EC in RW | 0x000000aa | low | undefined
9474 19:23:11.248164 EC interrupt | 0x00000005 | low | undefined
9475 19:23:11.251246 TPM interrupt | 0x000000ab | high | undefined
9476 19:23:11.254828 SD card detect | 0x00000011 | high | undefined
9477 19:23:11.261313 speaker enable | 0x00000093 | high | undefined
9478 19:23:11.264644 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9479 19:23:11.268361 in-header: 03 f9 00 00 02 00 00 00
9480 19:23:11.268495 in-data: 02 00
9481 19:23:11.271289 ADC[4]: Raw value=900221 ID=7
9482 19:23:11.274607 ADC[3]: Raw value=213336 ID=1
9483 19:23:11.274694 RAM Code: 0x71
9484 19:23:11.277991 ADC[6]: Raw value=74557 ID=0
9485 19:23:11.281505 ADC[5]: Raw value=211860 ID=1
9486 19:23:11.281592 SKU Code: 0x1
9487 19:23:11.288102 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 9485
9488 19:23:11.291815 coreboot table: 964 bytes.
9489 19:23:11.294860 IMD ROOT 0. 0xfffff000 0x00001000
9490 19:23:11.298321 IMD SMALL 1. 0xffffe000 0x00001000
9491 19:23:11.301774 RO MCACHE 2. 0xffffc000 0x00001104
9492 19:23:11.304931 CONSOLE 3. 0xfff7c000 0x00080000
9493 19:23:11.308444 FMAP 4. 0xfff7b000 0x00000452
9494 19:23:11.311568 TIME STAMP 5. 0xfff7a000 0x00000910
9495 19:23:11.314764 VBOOT WORK 6. 0xfff66000 0x00014000
9496 19:23:11.318150 RAMOOPS 7. 0xffe66000 0x00100000
9497 19:23:11.321660 COREBOOT 8. 0xffe64000 0x00002000
9498 19:23:11.321755 IMD small region:
9499 19:23:11.324559 IMD ROOT 0. 0xffffec00 0x00000400
9500 19:23:11.328063 VPD 1. 0xffffeb80 0x0000006c
9501 19:23:11.331722 MMC STATUS 2. 0xffffeb60 0x00000004
9502 19:23:11.338775 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9503 19:23:11.338894 Probing TPM: done!
9504 19:23:11.345014 Connected to device vid:did:rid of 1ae0:0028:00
9505 19:23:11.351560 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9506 19:23:11.355172 Initialized TPM device CR50 revision 0
9507 19:23:11.358605 Checking cr50 for pending updates
9508 19:23:11.364766 Reading cr50 TPM mode
9509 19:23:11.373086 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9510 19:23:11.379934 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9511 19:23:11.419753 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9512 19:23:11.423596 Checking segment from ROM address 0x40100000
9513 19:23:11.427086 Checking segment from ROM address 0x4010001c
9514 19:23:11.433700 Loading segment from ROM address 0x40100000
9515 19:23:11.433802 code (compression=0)
9516 19:23:11.440049 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9517 19:23:11.449994 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9518 19:23:11.450115 it's not compressed!
9519 19:23:11.456994 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9520 19:23:11.460372 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9521 19:23:11.480699 Loading segment from ROM address 0x4010001c
9522 19:23:11.480855 Entry Point 0x80000000
9523 19:23:11.483706 Loaded segments
9524 19:23:11.487232 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9525 19:23:11.493963 Jumping to boot code at 0x80000000(0xffe64000)
9526 19:23:11.500797 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9527 19:23:11.507009 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9528 19:23:11.515265 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9529 19:23:11.518198 Checking segment from ROM address 0x40100000
9530 19:23:11.521885 Checking segment from ROM address 0x4010001c
9531 19:23:11.528248 Loading segment from ROM address 0x40100000
9532 19:23:11.528363 code (compression=1)
9533 19:23:11.535210 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9534 19:23:11.544639 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9535 19:23:11.544757 using LZMA
9536 19:23:11.552942 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9537 19:23:11.559602 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9538 19:23:11.563071 Loading segment from ROM address 0x4010001c
9539 19:23:11.563182 Entry Point 0x54601000
9540 19:23:11.566508 Loaded segments
9541 19:23:11.569684 NOTICE: MT8192 bl31_setup
9542 19:23:11.576999 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9543 19:23:11.580128 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9544 19:23:11.583722 WARNING: region 0:
9545 19:23:11.586642 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9546 19:23:11.586739 WARNING: region 1:
9547 19:23:11.593355 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9548 19:23:11.597094 WARNING: region 2:
9549 19:23:11.599960 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9550 19:23:11.603605 WARNING: region 3:
9551 19:23:11.606647 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9552 19:23:11.610176 WARNING: region 4:
9553 19:23:11.616759 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9554 19:23:11.616892 WARNING: region 5:
9555 19:23:11.620253 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9556 19:23:11.623495 WARNING: region 6:
9557 19:23:11.626621 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9558 19:23:11.626707 WARNING: region 7:
9559 19:23:11.633596 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9560 19:23:11.639986 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9561 19:23:11.643341 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9562 19:23:11.646987 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9563 19:23:11.653493 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9564 19:23:11.656852 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9565 19:23:11.660364 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9566 19:23:11.667248 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9567 19:23:11.670230 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9568 19:23:11.673811 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9569 19:23:11.680582 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9570 19:23:11.683829 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9571 19:23:11.687221 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9572 19:23:11.693922 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9573 19:23:11.696935 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9574 19:23:11.703577 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9575 19:23:11.707107 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9576 19:23:11.710841 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9577 19:23:11.717438 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9578 19:23:11.720313 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9579 19:23:11.723893 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9580 19:23:11.730364 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9581 19:23:11.734181 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9582 19:23:11.740680 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9583 19:23:11.744203 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9584 19:23:11.747246 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9585 19:23:11.754096 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9586 19:23:11.757659 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9587 19:23:11.764040 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9588 19:23:11.767768 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9589 19:23:11.770601 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9590 19:23:11.777495 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9591 19:23:11.780998 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9592 19:23:11.783978 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9593 19:23:11.790917 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9594 19:23:11.794113 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9595 19:23:11.797546 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9596 19:23:11.800703 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9597 19:23:11.807508 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9598 19:23:11.810812 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9599 19:23:11.814272 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9600 19:23:11.817395 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9601 19:23:11.821015 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9602 19:23:11.827641 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9603 19:23:11.830795 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9604 19:23:11.834310 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9605 19:23:11.841004 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9606 19:23:11.844059 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9607 19:23:11.847858 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9608 19:23:11.850974 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9609 19:23:11.858089 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9610 19:23:11.860959 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9611 19:23:11.868399 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9612 19:23:11.871361 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9613 19:23:11.874511 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9614 19:23:11.881401 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9615 19:23:11.884660 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9616 19:23:11.891071 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9617 19:23:11.894880 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9618 19:23:11.901312 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9619 19:23:11.904820 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9620 19:23:11.908040 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9621 19:23:11.914805 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9622 19:23:11.917936 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9623 19:23:11.924515 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9624 19:23:11.928071 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9625 19:23:11.935157 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9626 19:23:11.938332 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9627 19:23:11.941400 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9628 19:23:11.948164 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9629 19:23:11.951376 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9630 19:23:11.958168 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9631 19:23:11.961965 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9632 19:23:11.968809 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9633 19:23:11.971996 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9634 19:23:11.974842 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9635 19:23:11.981606 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9636 19:23:11.985143 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9637 19:23:11.991654 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9638 19:23:11.995554 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9639 19:23:12.001911 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9640 19:23:12.005165 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9641 19:23:12.008548 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9642 19:23:12.015254 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9643 19:23:12.018393 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9644 19:23:12.025347 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9645 19:23:12.029064 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9646 19:23:12.032110 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9647 19:23:12.039022 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9648 19:23:12.042084 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9649 19:23:12.048953 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9650 19:23:12.052125 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9651 19:23:12.059041 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9652 19:23:12.062092 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9653 19:23:12.066045 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9654 19:23:12.072447 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9655 19:23:12.075679 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9656 19:23:12.082232 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9657 19:23:12.085958 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9658 19:23:12.088999 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9659 19:23:12.092463 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9660 19:23:12.099159 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9661 19:23:12.102553 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9662 19:23:12.106017 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9663 19:23:12.112295 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9664 19:23:12.116045 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9665 19:23:12.119434 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9666 19:23:12.126014 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9667 19:23:12.129024 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9668 19:23:12.135628 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9669 19:23:12.139544 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9670 19:23:12.142558 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9671 19:23:12.149119 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9672 19:23:12.152949 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9673 19:23:12.159217 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9674 19:23:12.163037 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9675 19:23:12.166028 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9676 19:23:12.172805 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9677 19:23:12.175824 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9678 19:23:12.179331 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9679 19:23:12.185959 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9680 19:23:12.189255 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9681 19:23:12.192832 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9682 19:23:12.195924 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9683 19:23:12.199356 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9684 19:23:12.206154 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9685 19:23:12.209189 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9686 19:23:12.215931 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9687 19:23:12.219548 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9688 19:23:12.223006 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9689 19:23:12.229543 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9690 19:23:12.232742 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9691 19:23:12.239523 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9692 19:23:12.243060 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9693 19:23:12.245897 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9694 19:23:12.252606 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9695 19:23:12.256454 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9696 19:23:12.259517 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9697 19:23:12.266390 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9698 19:23:12.269977 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9699 19:23:12.276913 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9700 19:23:12.279903 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9701 19:23:12.283541 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9702 19:23:12.290244 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9703 19:23:12.293895 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9704 19:23:12.297108 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9705 19:23:12.303567 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9706 19:23:12.307259 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9707 19:23:12.310237 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9708 19:23:12.317003 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9709 19:23:12.320232 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9710 19:23:12.327121 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9711 19:23:12.330562 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9712 19:23:12.333785 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9713 19:23:12.340388 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9714 19:23:12.344166 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9715 19:23:12.350495 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9716 19:23:12.353950 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9717 19:23:12.357105 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9718 19:23:12.363861 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9719 19:23:12.367036 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9720 19:23:12.373669 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9721 19:23:12.377501 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9722 19:23:12.380577 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9723 19:23:12.387206 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9724 19:23:12.390924 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9725 19:23:12.393878 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9726 19:23:12.400661 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9727 19:23:12.403540 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9728 19:23:12.410618 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9729 19:23:12.413806 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9730 19:23:12.417409 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9731 19:23:12.424067 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9732 19:23:12.429791 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9733 19:23:12.430526 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9734 19:23:12.436975 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9735 19:23:12.440538 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9736 19:23:12.447334 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9737 19:23:12.450297 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9738 19:23:12.453657 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9739 19:23:12.460163 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9740 19:23:12.463277 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9741 19:23:12.470453 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9742 19:23:12.473355 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9743 19:23:12.476777 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9744 19:23:12.483706 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9745 19:23:12.486600 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9746 19:23:12.493122 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9747 19:23:12.496940 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9748 19:23:12.499743 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9749 19:23:12.507075 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9750 19:23:12.510028 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9751 19:23:12.516889 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9752 19:23:12.519807 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9753 19:23:12.523673 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9754 19:23:12.529899 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9755 19:23:12.533391 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9756 19:23:12.540140 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9757 19:23:12.543160 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9758 19:23:12.549938 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9759 19:23:12.552968 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9760 19:23:12.556753 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9761 19:23:12.562913 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9762 19:23:12.566337 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9763 19:23:12.573132 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9764 19:23:12.576573 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9765 19:23:12.579769 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9766 19:23:12.586323 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9767 19:23:12.589550 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9768 19:23:12.596332 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9769 19:23:12.599326 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9770 19:23:12.606468 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9771 19:23:12.609746 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9772 19:23:12.612909 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9773 19:23:12.619742 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9774 19:23:12.622978 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9775 19:23:12.629447 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9776 19:23:12.633167 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9777 19:23:12.636279 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9778 19:23:12.643069 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9779 19:23:12.646308 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9780 19:23:12.653094 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9781 19:23:12.656127 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9782 19:23:12.659250 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9783 19:23:12.666098 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9784 19:23:12.669702 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9785 19:23:12.676335 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9786 19:23:12.679356 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9787 19:23:12.686639 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9788 19:23:12.689755 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9789 19:23:12.693247 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9790 19:23:12.696326 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9791 19:23:12.703155 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9792 19:23:12.706122 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9793 19:23:12.709745 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9794 19:23:12.712992 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9795 19:23:12.719560 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9796 19:23:12.723135 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9797 19:23:12.729720 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9798 19:23:12.732985 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9799 19:23:12.736291 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9800 19:23:12.742879 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9801 19:23:12.746348 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9802 19:23:12.750413 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9803 19:23:12.756511 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9804 19:23:12.759732 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9805 19:23:12.763445 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9806 19:23:12.770111 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9807 19:23:12.773237 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9808 19:23:12.776562 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9809 19:23:12.782959 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9810 19:23:12.786639 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9811 19:23:12.793274 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9812 19:23:12.796453 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9813 19:23:12.799562 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9814 19:23:12.806532 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9815 19:23:12.809320 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9816 19:23:12.813001 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9817 19:23:12.819717 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9818 19:23:12.823110 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9819 19:23:12.826362 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9820 19:23:12.832459 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9821 19:23:12.835999 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9822 19:23:12.842794 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9823 19:23:12.845950 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9824 19:23:12.849451 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9825 19:23:12.856255 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9826 19:23:12.859416 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9827 19:23:12.862508 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9828 19:23:12.869329 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9829 19:23:12.872725 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9830 19:23:12.875892 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9831 19:23:12.879688 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9832 19:23:12.886531 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9833 19:23:12.889692 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9834 19:23:12.892486 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9835 19:23:12.895918 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9836 19:23:12.902495 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9837 19:23:12.906567 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9838 19:23:12.909678 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9839 19:23:12.912690 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9840 19:23:12.919640 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9841 19:23:12.922541 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9842 19:23:12.926254 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9843 19:23:12.932593 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9844 19:23:12.936299 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9845 19:23:12.942660 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9846 19:23:12.945847 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9847 19:23:12.949166 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9848 19:23:12.955734 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9849 19:23:12.959263 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9850 19:23:12.962873 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9851 19:23:12.969549 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9852 19:23:12.972814 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9853 19:23:12.979505 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9854 19:23:12.982452 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9855 19:23:12.989391 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9856 19:23:12.992711 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9857 19:23:12.995713 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9858 19:23:13.002532 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9859 19:23:13.005893 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9860 19:23:13.012260 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9861 19:23:13.015665 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9862 19:23:13.018942 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9863 19:23:13.025698 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9864 19:23:13.029541 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9865 19:23:13.036284 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9866 19:23:13.039361 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9867 19:23:13.042558 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9868 19:23:13.049108 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9869 19:23:13.053029 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9870 19:23:13.059267 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9871 19:23:13.062716 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9872 19:23:13.069421 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9873 19:23:13.072425 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9874 19:23:13.075835 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9875 19:23:13.082321 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9876 19:23:13.085736 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9877 19:23:13.092100 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9878 19:23:13.095859 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9879 19:23:13.099287 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9880 19:23:13.105529 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9881 19:23:13.109376 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9882 19:23:13.112404 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9883 19:23:13.118839 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9884 19:23:13.122165 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9885 19:23:13.128928 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9886 19:23:13.132718 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9887 19:23:13.139338 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9888 19:23:13.142206 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9889 19:23:13.145564 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9890 19:23:13.152416 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9891 19:23:13.155392 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9892 19:23:13.162416 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9893 19:23:13.165414 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9894 19:23:13.169193 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9895 19:23:13.175480 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9896 19:23:13.178899 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9897 19:23:13.182517 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9898 19:23:13.188928 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9899 19:23:13.192327 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9900 19:23:13.199110 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9901 19:23:13.202504 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9902 19:23:13.209069 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9903 19:23:13.212231 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9904 19:23:13.215457 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9905 19:23:13.222323 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9906 19:23:13.225858 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9907 19:23:13.232322 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9908 19:23:13.235943 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9909 19:23:13.239004 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9910 19:23:13.245764 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9911 19:23:13.248997 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9912 19:23:13.255536 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9913 19:23:13.259100 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9914 19:23:13.262377 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9915 19:23:13.268576 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9916 19:23:13.272457 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9917 19:23:13.278531 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9918 19:23:13.281744 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9919 19:23:13.288929 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9920 19:23:13.291904 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9921 19:23:13.295695 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9922 19:23:13.302160 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9923 19:23:13.305682 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9924 19:23:13.311773 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9925 19:23:13.315239 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9926 19:23:13.322170 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9927 19:23:13.324994 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9928 19:23:13.331822 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9929 19:23:13.335345 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9930 19:23:13.338895 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9931 19:23:13.344931 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9932 19:23:13.348641 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9933 19:23:13.355376 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9934 19:23:13.358467 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9935 19:23:13.365291 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9936 19:23:13.368591 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9937 19:23:13.372230 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9938 19:23:13.378757 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9939 19:23:13.381855 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9940 19:23:13.388524 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9941 19:23:13.392110 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9942 19:23:13.398394 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9943 19:23:13.401809 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9944 19:23:13.408166 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9945 19:23:13.411680 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9946 19:23:13.415334 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9947 19:23:13.421873 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9948 19:23:13.425041 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9949 19:23:13.431486 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9950 19:23:13.435030 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9951 19:23:13.438754 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9952 19:23:13.444894 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9953 19:23:13.448540 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9954 19:23:13.455235 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9955 19:23:13.458351 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9956 19:23:13.465053 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9957 19:23:13.468565 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9958 19:23:13.471649 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9959 19:23:13.478669 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9960 19:23:13.481586 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9961 19:23:13.488483 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9962 19:23:13.492343 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9963 19:23:13.495101 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9964 19:23:13.501961 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9965 19:23:13.505510 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9966 19:23:13.511696 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9967 19:23:13.515272 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9968 19:23:13.521736 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9969 19:23:13.525351 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9970 19:23:13.531635 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9971 19:23:13.535119 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9972 19:23:13.541674 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9973 19:23:13.545263 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9974 19:23:13.552308 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9975 19:23:13.555105 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9976 19:23:13.562016 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9977 19:23:13.565312 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9978 19:23:13.571643 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9979 19:23:13.575455 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9980 19:23:13.578406 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9981 19:23:13.585267 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9982 19:23:13.588367 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9983 19:23:13.595196 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9984 19:23:13.598393 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9985 19:23:13.605283 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9986 19:23:13.608958 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9987 19:23:13.615206 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9988 19:23:13.618922 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9989 19:23:13.625452 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9990 19:23:13.628545 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9991 19:23:13.635645 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9992 19:23:13.638517 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9993 19:23:13.645310 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9994 19:23:13.648826 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9995 19:23:13.652465 INFO: [APUAPC] vio 0
9996 19:23:13.655053 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9997 19:23:13.661869 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9998 19:23:13.665174 INFO: [APUAPC] D0_APC_0: 0x400510
9999 19:23:13.665791 INFO: [APUAPC] D0_APC_1: 0x0
10000 19:23:13.668616 INFO: [APUAPC] D0_APC_2: 0x1540
10001 19:23:13.671782 INFO: [APUAPC] D0_APC_3: 0x0
10002 19:23:13.675348 INFO: [APUAPC] D1_APC_0: 0xffffffff
10003 19:23:13.678670 INFO: [APUAPC] D1_APC_1: 0xffffffff
10004 19:23:13.682180 INFO: [APUAPC] D1_APC_2: 0x3fffff
10005 19:23:13.685139 INFO: [APUAPC] D1_APC_3: 0x0
10006 19:23:13.688696 INFO: [APUAPC] D2_APC_0: 0xffffffff
10007 19:23:13.692201 INFO: [APUAPC] D2_APC_1: 0xffffffff
10008 19:23:13.695224 INFO: [APUAPC] D2_APC_2: 0x3fffff
10009 19:23:13.698948 INFO: [APUAPC] D2_APC_3: 0x0
10010 19:23:13.702389 INFO: [APUAPC] D3_APC_0: 0xffffffff
10011 19:23:13.705681 INFO: [APUAPC] D3_APC_1: 0xffffffff
10012 19:23:13.708733 INFO: [APUAPC] D3_APC_2: 0x3fffff
10013 19:23:13.711855 INFO: [APUAPC] D3_APC_3: 0x0
10014 19:23:13.714959 INFO: [APUAPC] D4_APC_0: 0xffffffff
10015 19:23:13.718681 INFO: [APUAPC] D4_APC_1: 0xffffffff
10016 19:23:13.721723 INFO: [APUAPC] D4_APC_2: 0x3fffff
10017 19:23:13.724850 INFO: [APUAPC] D4_APC_3: 0x0
10018 19:23:13.728652 INFO: [APUAPC] D5_APC_0: 0xffffffff
10019 19:23:13.731681 INFO: [APUAPC] D5_APC_1: 0xffffffff
10020 19:23:13.734839 INFO: [APUAPC] D5_APC_2: 0x3fffff
10021 19:23:13.738276 INFO: [APUAPC] D5_APC_3: 0x0
10022 19:23:13.741924 INFO: [APUAPC] D6_APC_0: 0xffffffff
10023 19:23:13.744960 INFO: [APUAPC] D6_APC_1: 0xffffffff
10024 19:23:13.748275 INFO: [APUAPC] D6_APC_2: 0x3fffff
10025 19:23:13.751325 INFO: [APUAPC] D6_APC_3: 0x0
10026 19:23:13.755081 INFO: [APUAPC] D7_APC_0: 0xffffffff
10027 19:23:13.758251 INFO: [APUAPC] D7_APC_1: 0xffffffff
10028 19:23:13.761505 INFO: [APUAPC] D7_APC_2: 0x3fffff
10029 19:23:13.764706 INFO: [APUAPC] D7_APC_3: 0x0
10030 19:23:13.768357 INFO: [APUAPC] D8_APC_0: 0xffffffff
10031 19:23:13.771946 INFO: [APUAPC] D8_APC_1: 0xffffffff
10032 19:23:13.774715 INFO: [APUAPC] D8_APC_2: 0x3fffff
10033 19:23:13.778218 INFO: [APUAPC] D8_APC_3: 0x0
10034 19:23:13.781468 INFO: [APUAPC] D9_APC_0: 0xffffffff
10035 19:23:13.784671 INFO: [APUAPC] D9_APC_1: 0xffffffff
10036 19:23:13.788185 INFO: [APUAPC] D9_APC_2: 0x3fffff
10037 19:23:13.791128 INFO: [APUAPC] D9_APC_3: 0x0
10038 19:23:13.794794 INFO: [APUAPC] D10_APC_0: 0xffffffff
10039 19:23:13.798302 INFO: [APUAPC] D10_APC_1: 0xffffffff
10040 19:23:13.801451 INFO: [APUAPC] D10_APC_2: 0x3fffff
10041 19:23:13.805123 INFO: [APUAPC] D10_APC_3: 0x0
10042 19:23:13.807956 INFO: [APUAPC] D11_APC_0: 0xffffffff
10043 19:23:13.811542 INFO: [APUAPC] D11_APC_1: 0xffffffff
10044 19:23:13.815053 INFO: [APUAPC] D11_APC_2: 0x3fffff
10045 19:23:13.818141 INFO: [APUAPC] D11_APC_3: 0x0
10046 19:23:13.821350 INFO: [APUAPC] D12_APC_0: 0xffffffff
10047 19:23:13.825197 INFO: [APUAPC] D12_APC_1: 0xffffffff
10048 19:23:13.828227 INFO: [APUAPC] D12_APC_2: 0x3fffff
10049 19:23:13.831315 INFO: [APUAPC] D12_APC_3: 0x0
10050 19:23:13.834486 INFO: [APUAPC] D13_APC_0: 0xffffffff
10051 19:23:13.838040 INFO: [APUAPC] D13_APC_1: 0xffffffff
10052 19:23:13.841190 INFO: [APUAPC] D13_APC_2: 0x3fffff
10053 19:23:13.844729 INFO: [APUAPC] D13_APC_3: 0x0
10054 19:23:13.847813 INFO: [APUAPC] D14_APC_0: 0xffffffff
10055 19:23:13.851567 INFO: [APUAPC] D14_APC_1: 0xffffffff
10056 19:23:13.854714 INFO: [APUAPC] D14_APC_2: 0x3fffff
10057 19:23:13.857855 INFO: [APUAPC] D14_APC_3: 0x0
10058 19:23:13.861534 INFO: [APUAPC] D15_APC_0: 0xffffffff
10059 19:23:13.864837 INFO: [APUAPC] D15_APC_1: 0xffffffff
10060 19:23:13.867974 INFO: [APUAPC] D15_APC_2: 0x3fffff
10061 19:23:13.871505 INFO: [APUAPC] D15_APC_3: 0x0
10062 19:23:13.872174 INFO: [APUAPC] APC_CON: 0x4
10063 19:23:13.874600 INFO: [NOCDAPC] D0_APC_0: 0x0
10064 19:23:13.878084 INFO: [NOCDAPC] D0_APC_1: 0x0
10065 19:23:13.881127 INFO: [NOCDAPC] D1_APC_0: 0x0
10066 19:23:13.884802 INFO: [NOCDAPC] D1_APC_1: 0xfff
10067 19:23:13.888240 INFO: [NOCDAPC] D2_APC_0: 0x0
10068 19:23:13.891650 INFO: [NOCDAPC] D2_APC_1: 0xfff
10069 19:23:13.894661 INFO: [NOCDAPC] D3_APC_0: 0x0
10070 19:23:13.898063 INFO: [NOCDAPC] D3_APC_1: 0xfff
10071 19:23:13.898290 INFO: [NOCDAPC] D4_APC_0: 0x0
10072 19:23:13.901554 INFO: [NOCDAPC] D4_APC_1: 0xfff
10073 19:23:13.905040 INFO: [NOCDAPC] D5_APC_0: 0x0
10074 19:23:13.907971 INFO: [NOCDAPC] D5_APC_1: 0xfff
10075 19:23:13.911215 INFO: [NOCDAPC] D6_APC_0: 0x0
10076 19:23:13.914956 INFO: [NOCDAPC] D6_APC_1: 0xfff
10077 19:23:13.917958 INFO: [NOCDAPC] D7_APC_0: 0x0
10078 19:23:13.921558 INFO: [NOCDAPC] D7_APC_1: 0xfff
10079 19:23:13.924568 INFO: [NOCDAPC] D8_APC_0: 0x0
10080 19:23:13.928376 INFO: [NOCDAPC] D8_APC_1: 0xfff
10081 19:23:13.928610 INFO: [NOCDAPC] D9_APC_0: 0x0
10082 19:23:13.931386 INFO: [NOCDAPC] D9_APC_1: 0xfff
10083 19:23:13.935023 INFO: [NOCDAPC] D10_APC_0: 0x0
10084 19:23:13.938129 INFO: [NOCDAPC] D10_APC_1: 0xfff
10085 19:23:13.941262 INFO: [NOCDAPC] D11_APC_0: 0x0
10086 19:23:13.944993 INFO: [NOCDAPC] D11_APC_1: 0xfff
10087 19:23:13.948535 INFO: [NOCDAPC] D12_APC_0: 0x0
10088 19:23:13.951715 INFO: [NOCDAPC] D12_APC_1: 0xfff
10089 19:23:13.954778 INFO: [NOCDAPC] D13_APC_0: 0x0
10090 19:23:13.958372 INFO: [NOCDAPC] D13_APC_1: 0xfff
10091 19:23:13.961752 INFO: [NOCDAPC] D14_APC_0: 0x0
10092 19:23:13.965337 INFO: [NOCDAPC] D14_APC_1: 0xfff
10093 19:23:13.968351 INFO: [NOCDAPC] D15_APC_0: 0x0
10094 19:23:13.971614 INFO: [NOCDAPC] D15_APC_1: 0xfff
10095 19:23:13.972054 INFO: [NOCDAPC] APC_CON: 0x4
10096 19:23:13.975085 INFO: [APUAPC] set_apusys_apc done
10097 19:23:13.978534 INFO: [DEVAPC] devapc_init done
10098 19:23:13.984934 INFO: GICv3 without legacy support detected.
10099 19:23:13.988341 INFO: ARM GICv3 driver initialized in EL3
10100 19:23:13.991321 INFO: Maximum SPI INTID supported: 639
10101 19:23:13.994622 INFO: BL31: Initializing runtime services
10102 19:23:14.001577 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10103 19:23:14.004975 INFO: SPM: enable CPC mode
10104 19:23:14.008195 INFO: mcdi ready for mcusys-off-idle and system suspend
10105 19:23:14.014586 INFO: BL31: Preparing for EL3 exit to normal world
10106 19:23:14.018396 INFO: Entry point address = 0x80000000
10107 19:23:14.018843 INFO: SPSR = 0x8
10108 19:23:14.025319
10109 19:23:14.025861
10110 19:23:14.026365
10111 19:23:14.028263 Starting depthcharge on Spherion...
10112 19:23:14.028835
10113 19:23:14.029398 Wipe memory regions:
10114 19:23:14.029818
10115 19:23:14.032460 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10116 19:23:14.033185 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10117 19:23:14.033869 Setting prompt string to ['asurada:']
10118 19:23:14.034528 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10119 19:23:14.035540 [0x00000040000000, 0x00000054600000)
10120 19:23:14.153918
10121 19:23:14.154074 [0x00000054660000, 0x00000080000000)
10122 19:23:14.414397
10123 19:23:14.415060 [0x000000821a7280, 0x000000ffe64000)
10124 19:23:15.159602
10125 19:23:15.160102 [0x00000100000000, 0x00000240000000)
10126 19:23:17.049471
10127 19:23:17.052926 Initializing XHCI USB controller at 0x11200000.
10128 19:23:18.091024
10129 19:23:18.094344 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10130 19:23:18.094465
10131 19:23:18.094564
10132 19:23:18.094655
10133 19:23:18.094981 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10135 19:23:18.195370 asurada: tftpboot 192.168.201.1 13420348/tftp-deploy-g80fdqkg/kernel/image.itb 13420348/tftp-deploy-g80fdqkg/kernel/cmdline
10136 19:23:18.195521 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10137 19:23:18.195607 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10138 19:23:18.199899 tftpboot 192.168.201.1 13420348/tftp-deploy-g80fdqkg/kernel/image.itp-deploy-g80fdqkg/kernel/cmdline
10139 19:23:18.200009
10140 19:23:18.200109 Waiting for link
10141 19:23:18.358261
10142 19:23:18.358539 R8152: Initializing
10143 19:23:18.358720
10144 19:23:18.361395 Version 6 (ocp_data = 5c30)
10145 19:23:18.361622
10146 19:23:18.364735 R8152: Done initializing
10147 19:23:18.365055
10148 19:23:18.365367 Adding net device
10149 19:23:20.301031
10150 19:23:20.301177 done.
10151 19:23:20.301285
10152 19:23:20.301363 MAC: 00:24:32:30:78:52
10153 19:23:20.301428
10154 19:23:20.304147 Sending DHCP discover... done.
10155 19:23:20.304231
10156 19:23:20.307667 Waiting for reply... done.
10157 19:23:20.307790
10158 19:23:20.310997 Sending DHCP request... done.
10159 19:23:20.311092
10160 19:23:20.315863 Waiting for reply... done.
10161 19:23:20.315960
10162 19:23:20.316067 My ip is 192.168.201.14
10163 19:23:20.316168
10164 19:23:20.319284 The DHCP server ip is 192.168.201.1
10165 19:23:20.319409
10166 19:23:20.325701 TFTP server IP predefined by user: 192.168.201.1
10167 19:23:20.325850
10168 19:23:20.332319 Bootfile predefined by user: 13420348/tftp-deploy-g80fdqkg/kernel/image.itb
10169 19:23:20.332500
10170 19:23:20.332659 Sending tftp read request... done.
10171 19:23:20.335532
10172 19:23:20.339756 Waiting for the transfer...
10173 19:23:20.339867
10174 19:23:20.867616 00000000 ################################################################
10175 19:23:20.867801
10176 19:23:21.407811 00080000 ################################################################
10177 19:23:21.407958
10178 19:23:21.931542 00100000 ################################################################
10179 19:23:21.931694
10180 19:23:22.456798 00180000 ################################################################
10181 19:23:22.456945
10182 19:23:22.982031 00200000 ################################################################
10183 19:23:22.982177
10184 19:23:23.521624 00280000 ################################################################
10185 19:23:23.521762
10186 19:23:24.054712 00300000 ################################################################
10187 19:23:24.054857
10188 19:23:24.577543 00380000 ################################################################
10189 19:23:24.577683
10190 19:23:25.114192 00400000 ################################################################
10191 19:23:25.114339
10192 19:23:25.632996 00480000 ################################################################
10193 19:23:25.633170
10194 19:23:26.188342 00500000 ################################################################
10195 19:23:26.188516
10196 19:23:26.708135 00580000 ################################################################
10197 19:23:26.708299
10198 19:23:27.232986 00600000 ################################################################
10199 19:23:27.233150
10200 19:23:27.758025 00680000 ################################################################
10201 19:23:27.758175
10202 19:23:28.282383 00700000 ################################################################
10203 19:23:28.282574
10204 19:23:28.800962 00780000 ################################################################
10205 19:23:28.801102
10206 19:23:29.325329 00800000 ################################################################
10207 19:23:29.325465
10208 19:23:29.843296 00880000 ################################################################
10209 19:23:29.843431
10210 19:23:30.360390 00900000 ################################################################
10211 19:23:30.360530
10212 19:23:30.883286 00980000 ################################################################
10213 19:23:30.883426
10214 19:23:31.407886 00a00000 ################################################################
10215 19:23:31.408074
10216 19:23:31.920947 00a80000 ################################################################
10217 19:23:31.921102
10218 19:23:32.446452 00b00000 ################################################################
10219 19:23:32.446592
10220 19:23:32.977044 00b80000 ################################################################
10221 19:23:32.977192
10222 19:23:33.499637 00c00000 ################################################################
10223 19:23:33.499775
10224 19:23:34.019503 00c80000 ################################################################
10225 19:23:34.019673
10226 19:23:34.547571 00d00000 ################################################################
10227 19:23:34.547752
10228 19:23:35.074895 00d80000 ################################################################
10229 19:23:35.075103
10230 19:23:35.606854 00e00000 ################################################################
10231 19:23:35.607013
10232 19:23:36.123020 00e80000 ################################################################
10233 19:23:36.123167
10234 19:23:36.638862 00f00000 ################################################################
10235 19:23:36.639007
10236 19:23:37.162362 00f80000 ################################################################
10237 19:23:37.162511
10238 19:23:37.693482 01000000 ################################################################
10239 19:23:37.693654
10240 19:23:38.224724 01080000 ################################################################
10241 19:23:38.224876
10242 19:23:38.811717 01100000 ################################################################
10243 19:23:38.812386
10244 19:23:39.470868 01180000 ################################################################
10245 19:23:39.471441
10246 19:23:40.112506 01200000 ################################################################
10247 19:23:40.113086
10248 19:23:40.674755 01280000 ################################################################
10249 19:23:40.674892
10250 19:23:41.193888 01300000 ################################################################
10251 19:23:41.194025
10252 19:23:41.712110 01380000 ################################################################
10253 19:23:41.712310
10254 19:23:42.255220 01400000 ################################################################
10255 19:23:42.255402
10256 19:23:42.800072 01480000 ################################################################
10257 19:23:42.800248
10258 19:23:43.345102 01500000 ################################################################
10259 19:23:43.345305
10260 19:23:43.881274 01580000 ################################################################
10261 19:23:43.881450
10262 19:23:44.431539 01600000 ################################################################
10263 19:23:44.431693
10264 19:23:45.032400 01680000 ################################################################
10265 19:23:45.032555
10266 19:23:45.603524 01700000 ################################################################
10267 19:23:45.603680
10268 19:23:46.157775 01780000 ################################################################
10269 19:23:46.157908
10270 19:23:46.728356 01800000 ################################################################
10271 19:23:46.728508
10272 19:23:47.338358 01880000 ################################################################
10273 19:23:47.339037
10274 19:23:47.919469 01900000 ################################################################
10275 19:23:47.919637
10276 19:23:48.497706 01980000 ################################################################
10277 19:23:48.497879
10278 19:23:49.104532 01a00000 ################################################################
10279 19:23:49.104678
10280 19:23:49.758070 01a80000 ################################################################
10281 19:23:49.758281
10282 19:23:50.431128 01b00000 ################################################################
10283 19:23:50.431634
10284 19:23:51.043395 01b80000 ################################################################
10285 19:23:51.043534
10286 19:23:51.664580 01c00000 ################################################################
10287 19:23:51.664948
10288 19:23:52.219734 01c80000 ################################################################
10289 19:23:52.219883
10290 19:23:52.757521 01d00000 ################################################################
10291 19:23:52.757674
10292 19:23:53.317076 01d80000 ################################################################
10293 19:23:53.317219
10294 19:23:53.609403 01e00000 ################################## done.
10295 19:23:53.609636
10296 19:23:53.612999 The bootfile was 31731986 bytes long.
10297 19:23:53.613130
10298 19:23:53.616647 Sending tftp read request... done.
10299 19:23:53.616757
10300 19:23:53.616845 Waiting for the transfer...
10301 19:23:53.616941
10302 19:23:53.619662 00000000 # done.
10303 19:23:53.619746
10304 19:23:53.626722 Command line loaded dynamically from TFTP file: 13420348/tftp-deploy-g80fdqkg/kernel/cmdline
10305 19:23:53.626808
10306 19:23:53.649980 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/13420348/extract-nfsrootfs-oiegi9vu,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10307 19:23:53.650092
10308 19:23:53.650158 Loading FIT.
10309 19:23:53.650218
10310 19:23:53.653324 Image ramdisk-1 has 18772366 bytes.
10311 19:23:53.653408
10312 19:23:53.656212 Image fdt-1 has 47230 bytes.
10313 19:23:53.656295
10314 19:23:53.659938 Image kernel-1 has 12910355 bytes.
10315 19:23:53.660022
10316 19:23:53.670125 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10317 19:23:53.670218
10318 19:23:53.686827 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10319 19:23:53.686938
10320 19:23:53.689824 Choosing best match conf-1 for compat google,spherion-rev2.
10321 19:23:53.695708
10322 19:23:53.700373 Connected to device vid:did:rid of 1ae0:0028:00
10323 19:23:53.707888
10324 19:23:53.711439 tpm_get_response: command 0x17b, return code 0x0
10325 19:23:53.711525
10326 19:23:53.714874 ec_init: CrosEC protocol v3 supported (256, 248)
10327 19:23:53.718469
10328 19:23:53.721995 tpm_cleanup: add release locality here.
10329 19:23:53.722080
10330 19:23:53.722146 Shutting down all USB controllers.
10331 19:23:53.725105
10332 19:23:53.725220 Removing current net device
10333 19:23:53.725321
10334 19:23:53.732060 Exiting depthcharge with code 4 at timestamp: 69155642
10335 19:23:53.732146
10336 19:23:53.735661 LZMA decompressing kernel-1 to 0x821a6718
10337 19:23:53.735745
10338 19:23:53.738697 LZMA decompressing kernel-1 to 0x40000000
10339 19:23:55.333193
10340 19:23:55.333383 jumping to kernel
10341 19:23:55.333841 end: 2.2.4 bootloader-commands (duration 00:00:41) [common]
10342 19:23:55.333941 start: 2.2.5 auto-login-action (timeout 00:03:44) [common]
10343 19:23:55.334020 Setting prompt string to ['Linux version [0-9]']
10344 19:23:55.334089 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10345 19:23:55.334156 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10346 19:23:55.415195
10347 19:23:55.418565 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10348 19:23:55.422064 start: 2.2.5.1 login-action (timeout 00:03:43) [common]
10349 19:23:55.422162 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10350 19:23:55.422234 Setting prompt string to []
10351 19:23:55.422328 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10352 19:23:55.422432 Using line separator: #'\n'#
10353 19:23:55.422520 No login prompt set.
10354 19:23:55.422610 Parsing kernel messages
10355 19:23:55.422693 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10356 19:23:55.422861 [login-action] Waiting for messages, (timeout 00:03:43)
10357 19:23:55.422952 Waiting using forced prompt support (timeout 00:01:52)
10358 19:23:55.441896 [ 0.000000] Linux version 6.1.86-cip19 (KernelCI@build-j170728-arm64-gcc-10-defconfig-arm64-chromebook-wrkxq) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Apr 18 19:05:54 UTC 2024
10359 19:23:55.444913 [ 0.000000] random: crng init done
10360 19:23:55.451813 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10361 19:23:55.455454 [ 0.000000] efi: UEFI not found.
10362 19:23:55.461492 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10363 19:23:55.468577 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10364 19:23:55.478611 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10365 19:23:55.488315 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10366 19:23:55.494792 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10367 19:23:55.498362 [ 0.000000] printk: bootconsole [mtk8250] enabled
10368 19:23:55.507160 [ 0.000000] NUMA: No NUMA configuration found
10369 19:23:55.513783 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10370 19:23:55.520438 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10371 19:23:55.520519 [ 0.000000] Zone ranges:
10372 19:23:55.527013 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10373 19:23:55.530716 [ 0.000000] DMA32 empty
10374 19:23:55.536765 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10375 19:23:55.540442 [ 0.000000] Movable zone start for each node
10376 19:23:55.543461 [ 0.000000] Early memory node ranges
10377 19:23:55.550399 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10378 19:23:55.556951 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10379 19:23:55.563631 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10380 19:23:55.570322 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10381 19:23:55.577027 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10382 19:23:55.583493 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10383 19:23:55.639807 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10384 19:23:55.646752 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10385 19:23:55.653079 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10386 19:23:55.655914 [ 0.000000] psci: probing for conduit method from DT.
10387 19:23:55.662714 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10388 19:23:55.665958 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10389 19:23:55.672918 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10390 19:23:55.675964 [ 0.000000] psci: SMC Calling Convention v1.2
10391 19:23:55.682732 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10392 19:23:55.686124 [ 0.000000] Detected VIPT I-cache on CPU0
10393 19:23:55.692900 [ 0.000000] CPU features: detected: GIC system register CPU interface
10394 19:23:55.699520 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10395 19:23:55.706052 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10396 19:23:55.712281 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10397 19:23:55.719048 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10398 19:23:55.729155 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10399 19:23:55.732306 [ 0.000000] alternatives: applying boot alternatives
10400 19:23:55.739374 [ 0.000000] Fallback order for Node 0: 0
10401 19:23:55.745742 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10402 19:23:55.745853 [ 0.000000] Policy zone: Normal
10403 19:23:55.772031 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/13420348/extract-nfsrootfs-oiegi9vu,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10404 19:23:55.782044 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10405 19:23:55.792681 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10406 19:23:55.802456 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10407 19:23:55.808967 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10408 19:23:55.812385 <6>[ 0.000000] software IO TLB: area num 8.
10409 19:23:55.868533 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10410 19:23:56.017966 <6>[ 0.000000] Memory: 7946240K/8385536K available (18048K kernel code, 4118K rwdata, 22288K rodata, 8448K init, 616K bss, 406528K reserved, 32768K cma-reserved)
10411 19:23:56.024364 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10412 19:23:56.031397 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10413 19:23:56.034341 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10414 19:23:56.040980 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10415 19:23:56.048106 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10416 19:23:56.051298 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10417 19:23:56.061673 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10418 19:23:56.068404 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10419 19:23:56.071302 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10420 19:23:56.078812 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10421 19:23:56.081948 <6>[ 0.000000] GICv3: 608 SPIs implemented
10422 19:23:56.088876 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10423 19:23:56.092511 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10424 19:23:56.095441 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10425 19:23:56.105577 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10426 19:23:56.115408 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10427 19:23:56.128641 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10428 19:23:56.135578 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10429 19:23:56.144295 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10430 19:23:56.157621 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10431 19:23:56.164651 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10432 19:23:56.171184 <6>[ 0.009186] Console: colour dummy device 80x25
10433 19:23:56.181394 <6>[ 0.013915] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10434 19:23:56.184850 <6>[ 0.024422] pid_max: default: 32768 minimum: 301
10435 19:23:56.191147 <6>[ 0.029324] LSM: Security Framework initializing
10436 19:23:56.197698 <6>[ 0.034291] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10437 19:23:56.207791 <6>[ 0.042107] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10438 19:23:56.214588 <6>[ 0.051523] cblist_init_generic: Setting adjustable number of callback queues.
10439 19:23:56.221187 <6>[ 0.058966] cblist_init_generic: Setting shift to 3 and lim to 1.
10440 19:23:56.227660 <6>[ 0.065304] cblist_init_generic: Setting adjustable number of callback queues.
10441 19:23:56.234469 <6>[ 0.072731] cblist_init_generic: Setting shift to 3 and lim to 1.
10442 19:23:56.240893 <6>[ 0.079169] rcu: Hierarchical SRCU implementation.
10443 19:23:56.247904 <6>[ 0.084216] rcu: Max phase no-delay instances is 1000.
10444 19:23:56.251331 <6>[ 0.091277] EFI services will not be available.
10445 19:23:56.257928 <6>[ 0.096235] smp: Bringing up secondary CPUs ...
10446 19:23:56.265698 <6>[ 0.101313] Detected VIPT I-cache on CPU1
10447 19:23:56.271699 <6>[ 0.101381] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10448 19:23:56.278543 <6>[ 0.101414] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10449 19:23:56.281826 <6>[ 0.101750] Detected VIPT I-cache on CPU2
10450 19:23:56.288259 <6>[ 0.101803] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10451 19:23:56.295029 <6>[ 0.101821] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10452 19:23:56.301941 <6>[ 0.102083] Detected VIPT I-cache on CPU3
10453 19:23:56.308583 <6>[ 0.102131] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10454 19:23:56.315370 <6>[ 0.102145] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10455 19:23:56.318277 <6>[ 0.102451] CPU features: detected: Spectre-v4
10456 19:23:56.324863 <6>[ 0.102457] CPU features: detected: Spectre-BHB
10457 19:23:56.328432 <6>[ 0.102461] Detected PIPT I-cache on CPU4
10458 19:23:56.335069 <6>[ 0.102519] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10459 19:23:56.341704 <6>[ 0.102536] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10460 19:23:56.348130 <6>[ 0.102833] Detected PIPT I-cache on CPU5
10461 19:23:56.354836 <6>[ 0.102895] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10462 19:23:56.361787 <6>[ 0.102911] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10463 19:23:56.364778 <6>[ 0.103190] Detected PIPT I-cache on CPU6
10464 19:23:56.371765 <6>[ 0.103254] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10465 19:23:56.378128 <6>[ 0.103270] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10466 19:23:56.385150 <6>[ 0.103567] Detected PIPT I-cache on CPU7
10467 19:23:56.391798 <6>[ 0.103631] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10468 19:23:56.398405 <6>[ 0.103647] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10469 19:23:56.401897 <6>[ 0.103693] smp: Brought up 1 node, 8 CPUs
10470 19:23:56.404894 <6>[ 0.245026] SMP: Total of 8 processors activated.
10471 19:23:56.411946 <6>[ 0.249948] CPU features: detected: 32-bit EL0 Support
10472 19:23:56.421394 <6>[ 0.255344] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10473 19:23:56.428102 <6>[ 0.264181] CPU features: detected: Common not Private translations
10474 19:23:56.431690 <6>[ 0.270697] CPU features: detected: CRC32 instructions
10475 19:23:56.438538 <6>[ 0.276048] CPU features: detected: RCpc load-acquire (LDAPR)
10476 19:23:56.445052 <6>[ 0.282008] CPU features: detected: LSE atomic instructions
10477 19:23:56.451777 <6>[ 0.287789] CPU features: detected: Privileged Access Never
10478 19:23:56.455346 <6>[ 0.293569] CPU features: detected: RAS Extension Support
10479 19:23:56.461403 <6>[ 0.299178] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10480 19:23:56.467942 <6>[ 0.306396] CPU: All CPU(s) started at EL2
10481 19:23:56.474418 <6>[ 0.310739] alternatives: applying system-wide alternatives
10482 19:23:56.483455 <6>[ 0.321552] devtmpfs: initialized
10483 19:23:56.495334 <6>[ 0.330455] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10484 19:23:56.505438 <6>[ 0.340412] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10485 19:23:56.511851 <6>[ 0.348621] pinctrl core: initialized pinctrl subsystem
10486 19:23:56.515452 <6>[ 0.355265] DMI not present or invalid.
10487 19:23:56.522122 <6>[ 0.359683] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10488 19:23:56.532376 <6>[ 0.366581] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10489 19:23:56.538779 <6>[ 0.374155] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10490 19:23:56.545534 <6>[ 0.382384] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10491 19:23:56.552541 <6>[ 0.390620] audit: initializing netlink subsys (disabled)
10492 19:23:56.562365 <5>[ 0.396312] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10493 19:23:56.565388 <6>[ 0.397003] thermal_sys: Registered thermal governor 'step_wise'
10494 19:23:56.575591 <6>[ 0.404282] thermal_sys: Registered thermal governor 'power_allocator'
10495 19:23:56.579078 <6>[ 0.410535] cpuidle: using governor menu
10496 19:23:56.581919 <6>[ 0.421493] NET: Registered PF_QIPCRTR protocol family
10497 19:23:56.591891 <6>[ 0.426994] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10498 19:23:56.595657 <6>[ 0.434096] ASID allocator initialised with 32768 entries
10499 19:23:56.602147 <6>[ 0.440652] Serial: AMBA PL011 UART driver
10500 19:23:56.611094 <4>[ 0.449362] Trying to register duplicate clock ID: 134
10501 19:23:56.665516 <6>[ 0.506927] KASLR enabled
10502 19:23:56.679863 <6>[ 0.514633] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10503 19:23:56.686091 <6>[ 0.521651] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10504 19:23:56.693072 <6>[ 0.528144] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10505 19:23:56.699867 <6>[ 0.535145] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10506 19:23:56.706479 <6>[ 0.541632] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10507 19:23:56.713176 <6>[ 0.548635] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10508 19:23:56.719624 <6>[ 0.555121] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10509 19:23:56.726725 <6>[ 0.562122] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10510 19:23:56.729223 <6>[ 0.569643] ACPI: Interpreter disabled.
10511 19:23:56.737692 <6>[ 0.576031] iommu: Default domain type: Translated
10512 19:23:56.744246 <6>[ 0.581144] iommu: DMA domain TLB invalidation policy: strict mode
10513 19:23:56.748061 <5>[ 0.587803] SCSI subsystem initialized
10514 19:23:56.754877 <6>[ 0.591951] usbcore: registered new interface driver usbfs
10515 19:23:56.761194 <6>[ 0.597685] usbcore: registered new interface driver hub
10516 19:23:56.764577 <6>[ 0.603235] usbcore: registered new device driver usb
10517 19:23:56.770927 <6>[ 0.609314] pps_core: LinuxPPS API ver. 1 registered
10518 19:23:56.780807 <6>[ 0.614507] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10519 19:23:56.784421 <6>[ 0.623850] PTP clock support registered
10520 19:23:56.787318 <6>[ 0.628092] EDAC MC: Ver: 3.0.0
10521 19:23:56.795103 <6>[ 0.633229] FPGA manager framework
10522 19:23:56.801833 <6>[ 0.636911] Advanced Linux Sound Architecture Driver Initialized.
10523 19:23:56.805001 <6>[ 0.643694] vgaarb: loaded
10524 19:23:56.812010 <6>[ 0.646879] clocksource: Switched to clocksource arch_sys_counter
10525 19:23:56.814968 <5>[ 0.653327] VFS: Disk quotas dquot_6.6.0
10526 19:23:56.821265 <6>[ 0.657511] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10527 19:23:56.825082 <6>[ 0.664700] pnp: PnP ACPI: disabled
10528 19:23:56.833444 <6>[ 0.671368] NET: Registered PF_INET protocol family
10529 19:23:56.843196 <6>[ 0.676966] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10530 19:23:56.855040 <6>[ 0.689306] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10531 19:23:56.864551 <6>[ 0.698125] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10532 19:23:56.871200 <6>[ 0.706096] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10533 19:23:56.878103 <6>[ 0.714801] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10534 19:23:56.889369 <6>[ 0.724552] TCP: Hash tables configured (established 65536 bind 65536)
10535 19:23:56.896500 <6>[ 0.731411] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10536 19:23:56.902609 <6>[ 0.738608] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10537 19:23:56.909595 <6>[ 0.746313] NET: Registered PF_UNIX/PF_LOCAL protocol family
10538 19:23:56.915988 <6>[ 0.752468] RPC: Registered named UNIX socket transport module.
10539 19:23:56.919566 <6>[ 0.758624] RPC: Registered udp transport module.
10540 19:23:56.926217 <6>[ 0.763557] RPC: Registered tcp transport module.
10541 19:23:56.933076 <6>[ 0.768489] RPC: Registered tcp NFSv4.1 backchannel transport module.
10542 19:23:56.936008 <6>[ 0.775158] PCI: CLS 0 bytes, default 64
10543 19:23:56.939655 <6>[ 0.779495] Unpacking initramfs...
10544 19:23:56.964072 <6>[ 0.798996] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10545 19:23:56.974296 <6>[ 0.807666] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10546 19:23:56.977199 <6>[ 0.816522] kvm [1]: IPA Size Limit: 40 bits
10547 19:23:56.983900 <6>[ 0.821050] kvm [1]: GICv3: no GICV resource entry
10548 19:23:56.987148 <6>[ 0.826071] kvm [1]: disabling GICv2 emulation
10549 19:23:56.993948 <6>[ 0.830759] kvm [1]: GIC system register CPU interface enabled
10550 19:23:56.997386 <6>[ 0.836963] kvm [1]: vgic interrupt IRQ18
10551 19:23:57.004358 <6>[ 0.841330] kvm [1]: VHE mode initialized successfully
10552 19:23:57.010886 <5>[ 0.847892] Initialise system trusted keyrings
10553 19:23:57.017109 <6>[ 0.852701] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10554 19:23:57.024182 <6>[ 0.862753] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10555 19:23:57.031018 <5>[ 0.869146] NFS: Registering the id_resolver key type
10556 19:23:57.034672 <5>[ 0.874452] Key type id_resolver registered
10557 19:23:57.041038 <5>[ 0.878863] Key type id_legacy registered
10558 19:23:57.047832 <6>[ 0.883143] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10559 19:23:57.054287 <6>[ 0.890060] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10560 19:23:57.061065 <6>[ 0.897756] 9p: Installing v9fs 9p2000 file system support
10561 19:23:57.097154 <5>[ 0.935687] Key type asymmetric registered
10562 19:23:57.100664 <5>[ 0.940016] Asymmetric key parser 'x509' registered
10563 19:23:57.110862 <6>[ 0.945194] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10564 19:23:57.113975 <6>[ 0.952814] io scheduler mq-deadline registered
10565 19:23:57.117487 <6>[ 0.957580] io scheduler kyber registered
10566 19:23:57.136017 <6>[ 0.974574] EINJ: ACPI disabled.
10567 19:23:57.168816 <4>[ 1.000297] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10568 19:23:57.178495 <4>[ 1.010908] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10569 19:23:57.193184 <6>[ 1.031466] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10570 19:23:57.201072 <6>[ 1.039445] printk: console [ttyS0] disabled
10571 19:23:57.229693 <6>[ 1.064071] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10572 19:23:57.236130 <6>[ 1.073534] printk: console [ttyS0] enabled
10573 19:23:57.239319 <6>[ 1.073534] printk: console [ttyS0] enabled
10574 19:23:57.245836 <6>[ 1.082428] printk: bootconsole [mtk8250] disabled
10575 19:23:57.249325 <6>[ 1.082428] printk: bootconsole [mtk8250] disabled
10576 19:23:57.256291 <6>[ 1.093455] SuperH (H)SCI(F) driver initialized
10577 19:23:57.259122 <6>[ 1.098728] msm_serial: driver initialized
10578 19:23:57.273081 <6>[ 1.107603] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10579 19:23:57.282869 <6>[ 1.116155] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10580 19:23:57.289520 <6>[ 1.124696] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10581 19:23:57.299732 <6>[ 1.133322] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10582 19:23:57.305887 <6>[ 1.142027] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10583 19:23:57.315748 <6>[ 1.150745] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10584 19:23:57.326267 <6>[ 1.159286] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10585 19:23:57.333076 <6>[ 1.168085] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10586 19:23:57.342432 <6>[ 1.176625] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10587 19:23:57.353911 <6>[ 1.192027] loop: module loaded
10588 19:23:57.360729 <6>[ 1.198031] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10589 19:23:57.382946 <4>[ 1.221254] mtk-pmic-keys: Failed to locate of_node [id: -1]
10590 19:23:57.390284 <6>[ 1.228026] megasas: 07.719.03.00-rc1
10591 19:23:57.399249 <6>[ 1.237532] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10592 19:23:57.408230 <6>[ 1.246252] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10593 19:23:57.479670 <6>[ 1.317297] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10594 19:23:57.536486 <6>[ 1.367549] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10595 19:23:57.732103 <6>[ 1.570518] Freeing initrd memory: 18328K
10596 19:23:57.744101 <6>[ 1.582037] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10597 19:23:57.754604 <6>[ 1.592926] tun: Universal TUN/TAP device driver, 1.6
10598 19:23:57.757855 <6>[ 1.598987] thunder_xcv, ver 1.0
10599 19:23:57.761444 <6>[ 1.602484] thunder_bgx, ver 1.0
10600 19:23:57.764572 <6>[ 1.605987] nicpf, ver 1.0
10601 19:23:57.775239 <6>[ 1.609990] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10602 19:23:57.778502 <6>[ 1.617466] hns3: Copyright (c) 2017 Huawei Corporation.
10603 19:23:57.781962 <6>[ 1.623054] hclge is initializing
10604 19:23:57.788805 <6>[ 1.626630] e1000: Intel(R) PRO/1000 Network Driver
10605 19:23:57.795204 <6>[ 1.631759] e1000: Copyright (c) 1999-2006 Intel Corporation.
10606 19:23:57.798867 <6>[ 1.637771] e1000e: Intel(R) PRO/1000 Network Driver
10607 19:23:57.805615 <6>[ 1.642987] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10608 19:23:57.812296 <6>[ 1.649171] igb: Intel(R) Gigabit Ethernet Network Driver
10609 19:23:57.818617 <6>[ 1.654820] igb: Copyright (c) 2007-2014 Intel Corporation.
10610 19:23:57.825347 <6>[ 1.660656] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10611 19:23:57.828892 <6>[ 1.667174] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10612 19:23:57.835896 <6>[ 1.673637] sky2: driver version 1.30
10613 19:23:57.842240 <6>[ 1.678631] VFIO - User Level meta-driver version: 0.3
10614 19:23:57.848705 <6>[ 1.686847] usbcore: registered new interface driver usb-storage
10615 19:23:57.855712 <6>[ 1.693297] usbcore: registered new device driver onboard-usb-hub
10616 19:23:57.864365 <6>[ 1.702456] mt6397-rtc mt6359-rtc: registered as rtc0
10617 19:23:57.874376 <6>[ 1.707921] mt6397-rtc mt6359-rtc: setting system clock to 2024-04-18T19:23:57 UTC (1713468237)
10618 19:23:57.877719 <6>[ 1.717477] i2c_dev: i2c /dev entries driver
10619 19:23:57.894739 <6>[ 1.729178] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10620 19:23:57.901299 <4>[ 1.737908] cpu cpu0: supply cpu not found, using dummy regulator
10621 19:23:57.907515 <4>[ 1.744334] cpu cpu1: supply cpu not found, using dummy regulator
10622 19:23:57.914553 <4>[ 1.750739] cpu cpu2: supply cpu not found, using dummy regulator
10623 19:23:57.920980 <4>[ 1.757156] cpu cpu3: supply cpu not found, using dummy regulator
10624 19:23:57.927621 <4>[ 1.763555] cpu cpu4: supply cpu not found, using dummy regulator
10625 19:23:57.934262 <4>[ 1.769952] cpu cpu5: supply cpu not found, using dummy regulator
10626 19:23:57.940802 <4>[ 1.776349] cpu cpu6: supply cpu not found, using dummy regulator
10627 19:23:57.944170 <4>[ 1.782742] cpu cpu7: supply cpu not found, using dummy regulator
10628 19:23:57.964973 <6>[ 1.803388] cpu cpu0: EM: created perf domain
10629 19:23:57.968493 <6>[ 1.808323] cpu cpu4: EM: created perf domain
10630 19:23:57.975466 <6>[ 1.813914] sdhci: Secure Digital Host Controller Interface driver
10631 19:23:57.982272 <6>[ 1.820347] sdhci: Copyright(c) Pierre Ossman
10632 19:23:57.988840 <6>[ 1.825301] Synopsys Designware Multimedia Card Interface Driver
10633 19:23:57.995745 <6>[ 1.831940] sdhci-pltfm: SDHCI platform and OF driver helper
10634 19:23:57.999676 <6>[ 1.831977] mmc0: CQHCI version 5.10
10635 19:23:58.005816 <6>[ 1.842294] ledtrig-cpu: registered to indicate activity on CPUs
10636 19:23:58.012223 <6>[ 1.849094] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10637 19:23:58.019112 <6>[ 1.856153] usbcore: registered new interface driver usbhid
10638 19:23:58.022248 <6>[ 1.861979] usbhid: USB HID core driver
10639 19:23:58.028700 <6>[ 1.866175] spi_master spi0: will run message pump with realtime priority
10640 19:23:58.072640 <6>[ 1.904216] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10641 19:23:58.092242 <6>[ 1.920182] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10642 19:23:58.099001 <6>[ 1.934926] cros-ec-spi spi0.0: Chrome EC device registered
10643 19:23:58.102967 <6>[ 1.940952] mmc0: Command Queue Engine enabled
10644 19:23:58.109168 <6>[ 1.945694] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10645 19:23:58.116065 <6>[ 1.953175] mmcblk0: mmc0:0001 DA4128 116 GiB
10646 19:23:58.122762 <6>[ 1.956070] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10647 19:23:58.129689 <6>[ 1.961385] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10648 19:23:58.136471 <6>[ 1.968378] NET: Registered PF_PACKET protocol family
10649 19:23:58.139585 <6>[ 1.974447] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10650 19:23:58.146221 <6>[ 1.978502] 9pnet: Installing 9P2000 support
10651 19:23:58.149754 <6>[ 1.984285] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10652 19:23:58.155988 <5>[ 1.988190] Key type dns_resolver registered
10653 19:23:58.162958 <6>[ 1.994002] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10654 19:23:58.166123 <6>[ 1.998400] registered taskstats version 1
10655 19:23:58.169698 <5>[ 2.008836] Loading compiled-in X.509 certificates
10656 19:23:58.198470 <4>[ 2.030283] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10657 19:23:58.208731 <4>[ 2.041014] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10658 19:23:58.215486 <3>[ 2.051539] debugfs: File 'uA_load' in directory '/' already present!
10659 19:23:58.221585 <3>[ 2.058238] debugfs: File 'min_uV' in directory '/' already present!
10660 19:23:58.228613 <3>[ 2.064846] debugfs: File 'max_uV' in directory '/' already present!
10661 19:23:58.235540 <3>[ 2.071512] debugfs: File 'constraint_flags' in directory '/' already present!
10662 19:23:58.245836 <3>[ 2.080907] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10663 19:23:58.254690 <6>[ 2.093104] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10664 19:23:58.261675 <6>[ 2.099960] xhci-mtk 11200000.usb: xHCI Host Controller
10665 19:23:58.268456 <6>[ 2.105451] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10666 19:23:58.278267 <6>[ 2.113306] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10667 19:23:58.285082 <6>[ 2.122727] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10668 19:23:58.291670 <6>[ 2.128816] xhci-mtk 11200000.usb: xHCI Host Controller
10669 19:23:58.298377 <6>[ 2.134406] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10670 19:23:58.305301 <6>[ 2.142098] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10671 19:23:58.311725 <6>[ 2.149903] hub 1-0:1.0: USB hub found
10672 19:23:58.314827 <6>[ 2.153928] hub 1-0:1.0: 1 port detected
10673 19:23:58.321798 <6>[ 2.158200] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10674 19:23:58.328930 <6>[ 2.166962] hub 2-0:1.0: USB hub found
10675 19:23:58.332127 <6>[ 2.170974] hub 2-0:1.0: 1 port detected
10676 19:23:58.341465 <6>[ 2.179444] mtk-msdc 11f70000.mmc: Got CD GPIO
10677 19:23:58.352603 <6>[ 2.187391] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10678 19:23:58.359376 <6>[ 2.195423] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10679 19:23:58.368877 <4>[ 2.203313] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10680 19:23:58.379063 <6>[ 2.212836] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10681 19:23:58.386086 <6>[ 2.220915] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10682 19:23:58.392701 <6>[ 2.228946] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10683 19:23:58.402343 <6>[ 2.236867] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10684 19:23:58.408875 <6>[ 2.244684] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10685 19:23:58.418941 <6>[ 2.252501] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10686 19:23:58.428882 <6>[ 2.262863] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10687 19:23:58.435668 <6>[ 2.271231] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10688 19:23:58.446253 <6>[ 2.279574] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10689 19:23:58.452512 <6>[ 2.287912] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10690 19:23:58.463065 <6>[ 2.296250] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10691 19:23:58.469377 <6>[ 2.304587] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10692 19:23:58.479680 <6>[ 2.312925] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10693 19:23:58.485984 <6>[ 2.321262] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10694 19:23:58.496162 <6>[ 2.329600] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10695 19:23:58.503494 <6>[ 2.337938] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10696 19:23:58.513051 <6>[ 2.346276] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10697 19:23:58.519732 <6>[ 2.354614] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10698 19:23:58.529413 <6>[ 2.362952] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10699 19:23:58.535829 <6>[ 2.371290] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10700 19:23:58.546053 <6>[ 2.379637] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10701 19:23:58.552906 <6>[ 2.388358] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10702 19:23:58.559004 <6>[ 2.395498] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10703 19:23:58.566005 <6>[ 2.402277] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10704 19:23:58.572594 <6>[ 2.409044] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10705 19:23:58.579103 <6>[ 2.415970] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10706 19:23:58.588598 <6>[ 2.422820] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10707 19:23:58.598443 <6>[ 2.431950] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10708 19:23:58.605060 <6>[ 2.441069] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10709 19:23:58.615426 <6>[ 2.450364] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10710 19:23:58.625145 <6>[ 2.459831] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10711 19:23:58.635268 <6>[ 2.469297] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10712 19:23:58.645450 <6>[ 2.478417] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10713 19:23:58.652002 <6>[ 2.487891] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10714 19:23:58.662185 <6>[ 2.497010] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10715 19:23:58.672171 <6>[ 2.506305] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10716 19:23:58.681817 <6>[ 2.516465] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10717 19:23:58.693036 <6>[ 2.527698] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10718 19:23:58.699141 <6>[ 2.537343] Trying to probe devices needed for running init ...
10719 19:23:58.740602 <6>[ 2.575176] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10720 19:23:58.894446 <6>[ 2.732889] hub 1-1:1.0: USB hub found
10721 19:23:58.897862 <6>[ 2.737363] hub 1-1:1.0: 4 ports detected
10722 19:23:58.907866 <6>[ 2.746151] hub 1-1:1.0: USB hub found
10723 19:23:58.911195 <6>[ 2.750494] hub 1-1:1.0: 4 ports detected
10724 19:23:59.017505 <6>[ 2.855520] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10725 19:23:59.046403 <6>[ 2.884900] hub 2-1:1.0: USB hub found
10726 19:23:59.049842 <6>[ 2.889397] hub 2-1:1.0: 3 ports detected
10727 19:23:59.059607 <6>[ 2.897534] hub 2-1:1.0: USB hub found
10728 19:23:59.062408 <6>[ 2.901980] hub 2-1:1.0: 3 ports detected
10729 19:23:59.235979 <6>[ 3.071194] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10730 19:23:59.368186 <6>[ 3.206555] hub 1-1.4:1.0: USB hub found
10731 19:23:59.371588 <6>[ 3.211217] hub 1-1.4:1.0: 2 ports detected
10732 19:23:59.380209 <6>[ 3.218382] hub 1-1.4:1.0: USB hub found
10733 19:23:59.383375 <6>[ 3.222888] hub 1-1.4:1.0: 2 ports detected
10734 19:23:59.451950 <6>[ 3.287279] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10735 19:23:59.680143 <6>[ 3.515195] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10736 19:23:59.872380 <6>[ 3.707168] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10737 19:24:10.989369 <6>[ 14.832198] ALSA device list:
10738 19:24:10.995604 <6>[ 14.835487] No soundcards found.
10739 19:24:11.004086 <6>[ 14.843406] Freeing unused kernel memory: 8448K
10740 19:24:11.007209 <6>[ 14.848948] Run /init as init process
10741 19:24:11.016818 Loading, please wait...
10742 19:24:11.042113 Starting systemd-udevd version 252.22-1~deb12u1
10743 19:24:11.042700
10744 19:24:11.276331 <6>[ 15.112816] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10745 19:24:11.299875 <6>[ 15.139703] remoteproc remoteproc0: scp is available
10746 19:24:11.306556 <6>[ 15.145082] remoteproc remoteproc0: powering up scp
10747 19:24:11.313336 <3>[ 15.147117] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10748 19:24:11.323653 <6>[ 15.150214] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10749 19:24:11.330107 <3>[ 15.158437] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10750 19:24:11.336730 <6>[ 15.164258] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10751 19:24:11.346942 <6>[ 15.164279] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10752 19:24:11.356179 <6>[ 15.164284] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10753 19:24:11.359332 <6>[ 15.166849] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10754 19:24:11.369134 <3>[ 15.174920] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10755 19:24:11.375968 <6>[ 15.176217] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10756 19:24:11.383453 <6>[ 15.189722] usbcore: registered new device driver r8152-cfgselector
10757 19:24:11.389982 <3>[ 15.191204] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10758 19:24:11.396499 <6>[ 15.197483] mc: Linux media interface: v0.10
10759 19:24:11.403427 <4>[ 15.205196] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10760 19:24:11.410721 <4>[ 15.205196] Fallback method does not support PEC.
10761 19:24:11.417268 <3>[ 15.205600] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10762 19:24:11.423297 <6>[ 15.229279] videodev: Linux video capture interface: v2.00
10763 19:24:11.430525 <3>[ 15.230326] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10764 19:24:11.440116 <3>[ 15.235819] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10765 19:24:11.446777 <3>[ 15.235830] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10766 19:24:11.457004 <3>[ 15.235834] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10767 19:24:11.463423 <4>[ 15.238576] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10768 19:24:11.470025 <3>[ 15.241765] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10769 19:24:11.480057 <3>[ 15.253625] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10770 19:24:11.486817 <4>[ 15.254805] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10771 19:24:11.496622 <3>[ 15.262625] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10772 19:24:11.503469 <6>[ 15.284329] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10773 19:24:11.509834 <3>[ 15.284881] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10774 19:24:11.516404 <6>[ 15.292966] pci_bus 0000:00: root bus resource [bus 00-ff]
10775 19:24:11.523229 <3>[ 15.301039] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10776 19:24:11.532995 <6>[ 15.308395] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10777 19:24:11.539536 <6>[ 15.308439] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10778 19:24:11.546191 <6>[ 15.308447] remoteproc remoteproc0: remote processor scp is now up
10779 19:24:11.552740 <6>[ 15.311109] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10780 19:24:11.562800 <6>[ 15.311115] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10781 19:24:11.569102 <6>[ 15.311145] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10782 19:24:11.575826 <6>[ 15.311159] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10783 19:24:11.582775 <6>[ 15.311224] pci 0000:00:00.0: supports D1 D2
10784 19:24:11.589243 <6>[ 15.311226] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10785 19:24:11.596171 <6>[ 15.312199] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10786 19:24:11.602800 <6>[ 15.312280] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10787 19:24:11.609596 <6>[ 15.312304] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10788 19:24:11.619800 <6>[ 15.312319] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10789 19:24:11.626452 <6>[ 15.312333] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10790 19:24:11.629361 <6>[ 15.312442] pci 0000:01:00.0: supports D1 D2
10791 19:24:11.636036 <6>[ 15.312443] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10792 19:24:11.646459 <3>[ 15.316465] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10793 19:24:11.653018 <6>[ 15.323061] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10794 19:24:11.659610 <6>[ 15.323084] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10795 19:24:11.669408 <6>[ 15.323086] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10796 19:24:11.676343 <6>[ 15.323094] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10797 19:24:11.686269 <6>[ 15.323107] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10798 19:24:11.692480 <6>[ 15.323119] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10799 19:24:11.699213 <6>[ 15.323131] pci 0000:00:00.0: PCI bridge to [bus 01]
10800 19:24:11.705990 <6>[ 15.323136] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10801 19:24:11.712925 <6>[ 15.323255] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10802 19:24:11.719244 <6>[ 15.323748] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10803 19:24:11.726077 <6>[ 15.324395] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10804 19:24:11.732607 <6>[ 15.327352] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10805 19:24:11.739322 <3>[ 15.332494] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10806 19:24:11.748931 <3>[ 15.332498] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10807 19:24:11.755584 <3>[ 15.332507] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10808 19:24:11.765562 <6>[ 15.334031] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10809 19:24:11.772630 <6>[ 15.336246] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10810 19:24:11.782119 <6>[ 15.343409] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10811 19:24:11.792478 <3>[ 15.347440] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10812 19:24:11.799073 <3>[ 15.347455] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10813 19:24:11.809294 <6>[ 15.355941] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10814 19:24:11.819230 <6>[ 15.442318] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10815 19:24:11.825373 <4>[ 15.453029] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10816 19:24:11.835682 <5>[ 15.477741] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10817 19:24:11.842188 <4>[ 15.483242] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10818 19:24:11.845102 <6>[ 15.493212] Bluetooth: Core ver 2.22
10819 19:24:11.855107 <5>[ 15.506394] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10820 19:24:11.861808 <6>[ 15.506752] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10821 19:24:11.871683 <6>[ 15.508072] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10822 19:24:11.878370 <6>[ 15.508297] usbcore: registered new interface driver uvcvideo
10823 19:24:11.885293 <6>[ 15.513619] NET: Registered PF_BLUETOOTH protocol family
10824 19:24:11.891405 <5>[ 15.521897] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10825 19:24:11.898429 <6>[ 15.529520] Bluetooth: HCI device and connection manager initialized
10826 19:24:11.904938 <6>[ 15.530232] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10827 19:24:11.914447 <4>[ 15.537571] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10828 19:24:11.921017 <6>[ 15.542845] Bluetooth: HCI socket layer initialized
10829 19:24:11.924669 <6>[ 15.550740] cfg80211: failed to load regulatory.db
10830 19:24:11.927682 <6>[ 15.555212] r8152 2-1.3:1.0 eth0: v1.12.13
10831 19:24:11.934553 <6>[ 15.557248] Bluetooth: L2CAP socket layer initialized
10832 19:24:11.941127 <6>[ 15.564119] usbcore: registered new interface driver r8152
10833 19:24:11.944605 <6>[ 15.569089] Bluetooth: SCO socket layer initialized
10834 19:24:11.951388 <6>[ 15.610918] usbcore: registered new interface driver btusb
10835 19:24:11.960913 <4>[ 15.613035] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10836 19:24:11.967789 <3>[ 15.613051] Bluetooth: hci0: Failed to load firmware file (-2)
10837 19:24:11.974191 <3>[ 15.613053] Bluetooth: hci0: Failed to set up firmware (-2)
10838 19:24:11.984557 <4>[ 15.613056] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10839 19:24:11.991206 <6>[ 15.637947] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10840 19:24:11.997803 <6>[ 15.644810] usbcore: registered new interface driver cdc_ether
10841 19:24:12.004896 <6>[ 15.653608] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10842 19:24:12.011669 <6>[ 15.672019] usbcore: registered new interface driver r8153_ecm
10843 19:24:12.014899 <6>[ 15.699117] mt7921e 0000:01:00.0: ASIC revision: 79610010
10844 19:24:12.021006 <6>[ 15.737122] r8152 2-1.3:1.0 enx002432307852: renamed from eth0
10845 19:24:12.030870 <6>[ 15.833630] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10846 19:24:12.030957 <6>[ 15.833630]
10847 19:24:12.049537 Begin: Loading essential drivers ... done.
10848 19:24:12.052745 Begin: Running /scripts/init-premount ... done.
10849 19:24:12.059726 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10850 19:24:12.069542 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10851 19:24:12.072836 Device /sys/class/net/enx002432307852 found
10852 19:24:12.072952 done.
10853 19:24:12.079187 Begin: Waiting up to 180 secs for any network device to become available ... done.
10854 19:24:12.126641 IP-Config: enx002432307852 hardware address 00:24:32:30:78:52 mtu 1500 DHCP
10855 19:24:12.299254 <6>[ 16.135296] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10856 19:24:13.142946 <6>[ 16.983056] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10857 19:24:13.304283 <6>[ 17.144786] r8152 2-1.3:1.0 enx002432307852: carrier on
10858 19:24:13.368033 IP-Config: no response after 2 secs - giving up
10859 19:24:13.406762 IP-Config: enx002432307852 hardware address 00:24:32:30:78:52 mtu 1500 DHCP
10860 19:24:13.442751 IP-Config: wlp1s0 hardware address d8:f3:bc:78:28:3d mtu 1500 DHCP
10861 19:24:14.218939 IP-Config: enx002432307852 complete (dhcp from 192.168.201.1):
10862 19:24:14.225227 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10863 19:24:14.231923 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10864 19:24:14.238571 host : mt8192-asurada-spherion-r0-cbg-3
10865 19:24:14.245528 domain : lava-rack
10866 19:24:14.248537 rootserver: 192.168.201.1 rootpath:
10867 19:24:14.251697 filename :
10868 19:24:14.384667 done.
10869 19:24:14.392910 Begin: Running /scripts/nfs-bottom ... done.
10870 19:24:14.408583 Begin: Running /scripts/init-bottom ... done.
10871 19:24:15.796505 <6>[ 19.637249] NET: Registered PF_INET6 protocol family
10872 19:24:15.804544 <6>[ 19.644776] Segment Routing with IPv6
10873 19:24:15.807598 <6>[ 19.648766] In-situ OAM (IOAM) with IPv6
10874 19:24:15.989098 <30>[ 19.803281] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10875 19:24:15.996042 <30>[ 19.836405] systemd[1]: Detected architecture arm64.
10876 19:24:16.005937
10877 19:24:16.008937 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10878 19:24:16.009023
10879 19:24:16.009086
10880 19:24:16.032826 <30>[ 19.873360] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10881 19:24:17.114956 <30>[ 20.952261] systemd[1]: Queued start job for default target graphical.target.
10882 19:24:17.151166 <30>[ 20.988438] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10883 19:24:17.158192 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10884 19:24:17.158608
10885 19:24:17.180017 <30>[ 21.017148] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10886 19:24:17.189705 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10887 19:24:17.190144
10888 19:24:17.208269 <30>[ 21.044929] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10889 19:24:17.217933 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10890 19:24:17.218448
10891 19:24:17.236659 <30>[ 21.073382] systemd[1]: Created slice user.slice - User and Session Slice.
10892 19:24:17.242776 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10893 19:24:17.243171
10894 19:24:17.266386 <30>[ 21.100037] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10895 19:24:17.272725 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10896 19:24:17.276230
10897 19:24:17.293707 <30>[ 21.127471] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10898 19:24:17.300708 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10899 19:24:17.301328
10900 19:24:17.327983 <30>[ 21.155359] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10901 19:24:17.337860 <30>[ 21.175173] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10902 19:24:17.344462 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10903 19:24:17.344623
10904 19:24:17.362154 <30>[ 21.199590] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10905 19:24:17.369107 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10906 19:24:17.369251
10907 19:24:17.390290 <30>[ 21.227678] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10908 19:24:17.400280 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10909 19:24:17.400387
10910 19:24:17.415302 <30>[ 21.255703] systemd[1]: Reached target paths.target - Path Units.
10911 19:24:17.422197 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10912 19:24:17.425038
10913 19:24:17.442190 <30>[ 21.279610] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10914 19:24:17.449221 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10915 19:24:17.449317
10916 19:24:17.465660 <30>[ 21.303177] systemd[1]: Reached target slices.target - Slice Units.
10917 19:24:17.472766 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10918 19:24:17.473035
10919 19:24:17.486989 <30>[ 21.327728] systemd[1]: Reached target swap.target - Swaps.
10920 19:24:17.493837 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10921 19:24:17.494143
10922 19:24:17.514959 <30>[ 21.351678] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10923 19:24:17.524701 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10924 19:24:17.525135
10925 19:24:17.542981 <30>[ 21.380125] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10926 19:24:17.552918 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10927 19:24:17.553345
10928 19:24:17.573981 <30>[ 21.411209] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10929 19:24:17.584012 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10930 19:24:17.584410
10931 19:24:17.603992 <30>[ 21.440771] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10932 19:24:17.613866 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10933 19:24:17.614316
10934 19:24:17.630944 <30>[ 21.467848] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10935 19:24:17.637715 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10936 19:24:17.638139
10937 19:24:17.656360 <30>[ 21.492905] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10938 19:24:17.665952 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10939 19:24:17.666589
10940 19:24:17.686665 <30>[ 21.523834] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10941 19:24:17.696619 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10942 19:24:17.697054
10943 19:24:17.714606 <30>[ 21.551673] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10944 19:24:17.721459 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10945 19:24:17.724466
10946 19:24:17.774712 <30>[ 21.611671] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10947 19:24:17.781504 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10948 19:24:17.781930
10949 19:24:17.800553 <30>[ 21.637948] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10950 19:24:17.807682 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10951 19:24:17.808117
10952 19:24:17.830580 <30>[ 21.667299] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10953 19:24:17.836923 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10954 19:24:17.837339
10955 19:24:17.861196 <30>[ 21.691765] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10956 19:24:17.895035 <30>[ 21.732061] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10957 19:24:17.905313 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10958 19:24:17.905959
10959 19:24:17.927768 <30>[ 21.764843] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10960 19:24:17.937448 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10961 19:24:17.937909
10962 19:24:17.982956 <30>[ 21.819917] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10963 19:24:17.989119 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10964 19:24:17.989765
10965 19:24:18.013580 <30>[ 21.850530] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10966 19:24:18.020032 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10967 19:24:18.020464
10968 19:24:18.031781 <6>[ 21.868583] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10969 19:24:18.044633 <30>[ 21.881744] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10970 19:24:18.054612 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10971 19:24:18.055046
10972 19:24:18.076065 <30>[ 21.913219] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10973 19:24:18.082619 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10974 19:24:18.083056
10975 19:24:18.107783 <30>[ 21.944887] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10976 19:24:18.117764 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop..<6>[ 21.959049] fuse: init (API version 7.37)
10977 19:24:18.118204 .
10978 19:24:18.118544
10979 19:24:18.183153 <30>[ 22.020085] systemd[1]: Starting systemd-journald.service - Journal Service...
10980 19:24:18.189618 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10981 19:24:18.190048
10982 19:24:18.242799 <30>[ 22.079718] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10983 19:24:18.249149 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10984 19:24:18.249633
10985 19:24:18.277337 <30>[ 22.111233] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10986 19:24:18.283684 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10987 19:24:18.284116
10988 19:24:18.306960 <30>[ 22.144156] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10989 19:24:18.317234 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10990 19:24:18.317678
10991 19:24:18.339076 <30>[ 22.176049] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10992 19:24:18.345796 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10993 19:24:18.349283
10994 19:24:18.363237 <3>[ 22.199941] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10995 19:24:18.377661 <30>[ 22.214901] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10996 19:24:18.384505 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10997 19:24:18.384938
10998 19:24:18.396711 <3>[ 22.233871] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10999 19:24:18.407181 <30>[ 22.243347] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
11000 19:24:18.413035 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
11001 19:24:18.413536
11002 19:24:18.430614 <30>[ 22.267603] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
11003 19:24:18.436941 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
11004 19:24:18.437429
11005 19:24:18.455642 <3>[ 22.292614] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11006 19:24:18.465307 <30>[ 22.302277] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
11007 19:24:18.476563 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
11008 19:24:18.477018
11009 19:24:18.486287 <3>[ 22.322277] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11010 19:24:18.493141 <30>[ 22.332650] systemd[1]: modprobe@configfs.service: Deactivated successfully.
11011 19:24:18.504603 <30>[ 22.340962] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
11012 19:24:18.517516 [[0;32m OK [0m] Finished [0;1;39mmodprobe@c<3>[ 22.352631] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11013 19:24:18.521069 onfigfs…[0m - Load Kernel Module configfs.
11014 19:24:18.521550
11015 19:24:18.540090 <30>[ 22.376082] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
11016 19:24:18.546981 <30>[ 22.384023] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
11017 19:24:18.556885 <3>[ 22.385228] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11018 19:24:18.562940 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
11019 19:24:18.563505
11020 19:24:18.583658 <30>[ 22.420701] systemd[1]: modprobe@drm.service: Deactivated successfully.
11021 19:24:18.590009 <3>[ 22.422364] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11022 19:24:18.599950 <30>[ 22.428771] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
11023 19:24:18.607095 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
11024 19:24:18.607524
11025 19:24:18.623483 <3>[ 22.460556] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11026 19:24:18.634964 <30>[ 22.472236] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
11027 19:24:18.645566 <30>[ 22.480779] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
11028 19:24:18.655896 [[0;32m OK [0m] Finished [0<3>[ 22.492057] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11029 19:24:18.662253 ;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
11030 19:24:18.662681
11031 19:24:18.677363 <30>[ 22.517086] systemd[1]: modprobe@fuse.service: Deactivated successfully.
11032 19:24:18.687190 <3>[ 22.522621] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11033 19:24:18.693509 <30>[ 22.525114] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
11034 19:24:18.704081 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
11035 19:24:18.704479
11036 19:24:18.723596 <30>[ 22.561045] systemd[1]: modprobe@loop.service: Deactivated successfully.
11037 19:24:18.730970 <30>[ 22.569116] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
11038 19:24:18.741255 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
11039 19:24:18.741713
11040 19:24:18.759052 <30>[ 22.596319] systemd[1]: Started systemd-journald.service - Journal Service.
11041 19:24:18.772885 <4>[ 22.599820] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
11042 19:24:18.782323 <3>[ 22.619299] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
11043 19:24:18.788790 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
11044 19:24:18.788967
11045 19:24:18.811959 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
11046 19:24:18.812406
11047 19:24:18.835257 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
11048 19:24:18.835427
11049 19:24:18.855455 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
11050 19:24:18.855581
11051 19:24:18.875421 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
11052 19:24:18.875629
11053 19:24:18.897257 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
11054 19:24:18.897779
11055 19:24:18.959161 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
11056 19:24:18.959608
11057 19:24:18.985203 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
11058 19:24:18.985311
11059 19:24:19.011592 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
11060 19:24:19.011682
11061 19:24:19.040430 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
11062 19:24:19.040516
11063 19:24:19.074043 Starting [0;1;39msystemd-sysctl.se…c<46>[ 22.911690] systemd-journald[305]: Received client request to flush runtime journal.
11064 19:24:19.076836 e[0m - Apply Kernel Variables...
11065 19:24:19.076939
11066 19:24:19.107517 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
11067 19:24:19.107631
11068 19:24:19.264699 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
11069 19:24:19.265257
11070 19:24:19.283222 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
11071 19:24:19.283798
11072 19:24:19.303500 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
11073 19:24:19.304280
11074 19:24:19.856252 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
11075 19:24:19.856410
11076 19:24:20.214873 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
11077 19:24:20.215068
11078 19:24:20.262961 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
11079 19:24:20.263051
11080 19:24:20.509262 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11081 19:24:20.509409
11082 19:24:20.642609 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11083 19:24:20.643109
11084 19:24:20.667041 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11085 19:24:20.667148
11086 19:24:20.686341 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11087 19:24:20.686503
11088 19:24:20.734722 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11089 19:24:20.735242
11090 19:24:20.761066 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11091 19:24:20.761157
11092 19:24:21.006700 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11093 19:24:21.006866
11094 19:24:21.068467 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11095 19:24:21.068566
11096 19:24:21.098137 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11097 19:24:21.098224
11098 19:24:21.381115 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11099 19:24:21.381300
11100 19:24:21.428588 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11101 19:24:21.428689
11102 19:24:21.472706 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11103 19:24:21.473140
11104 19:24:21.559458 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11105 19:24:21.559591
11106 19:24:21.605510 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11107 19:24:21.605656
11108 19:24:21.642154 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11109 19:24:21.642271
11110 19:24:21.658881 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11111 19:24:21.659023
11112 19:24:21.715004 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11113 19:24:21.715477
11114 19:24:21.744907 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11115 19:24:21.745476
11116 19:24:21.767462 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11117 19:24:21.768016
11118 19:24:21.787852 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11119 19:24:21.788302
11120 19:24:21.804097 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11121 19:24:21.804625
11122 19:24:21.843044 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11123 19:24:21.843572
11124 19:24:21.922890 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11125 19:24:21.923020
11126 19:24:21.941927 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11127 19:24:21.942014
11128 19:24:21.957088 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11129 19:24:21.957174
11130 19:24:21.973675 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11131 19:24:21.974108
11132 19:24:21.998835 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11133 19:24:21.999264
11134 19:24:22.022068 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11135 19:24:22.022612
11136 19:24:22.037868 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11137 19:24:22.038425
11138 19:24:22.058171 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11139 19:24:22.058635
11140 19:24:22.078087 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11141 19:24:22.078615
11142 19:24:22.093941 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11143 19:24:22.094463
11144 19:24:22.112979 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11145 19:24:22.113557
11146 19:24:22.129716 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11147 19:24:22.130252
11148 19:24:22.145714 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11149 19:24:22.146239
11150 19:24:22.186841 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11151 19:24:22.187303
11152 19:24:22.225193 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11153 19:24:22.225737
11154 19:24:22.347648 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11155 19:24:22.347868
11156 19:24:22.378383 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11157 19:24:22.378790
11158 19:24:22.523229 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11159 19:24:22.523395
11160 19:24:22.574948 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11161 19:24:22.575064
11162 19:24:22.630825 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11163 19:24:22.630980
11164 19:24:22.649284 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11165 19:24:22.649607
11166 19:24:22.670046 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11167 19:24:22.670614
11168 19:24:22.704475 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11169 19:24:22.705067
11170 19:24:22.725853 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11171 19:24:22.726407
11172 19:24:22.751645 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11173 19:24:22.752076
11174 19:24:22.768838 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11175 19:24:22.769313
11176 19:24:22.832202 Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
11177 19:24:22.832763
11178 19:24:22.852841 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11179 19:24:22.853424
11180 19:24:22.913882 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11181 19:24:22.914406
11182 19:24:23.017112 [[0;32m OK [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
11183 19:24:23.017699
11184 19:24:23.106763
11185 19:24:23.107262
11186 19:24:23.109741 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11187 19:24:23.110169
11188 19:24:23.113117 debian-bookworm-arm64 login: root (automatic login)
11189 19:24:23.113600
11190 19:24:23.113938
11191 19:24:23.461400 Linux debian-bookworm-arm64 6.1.86-cip19 #1 SMP PREEMPT Thu Apr 18 19:05:54 UTC 2024 aarch64
11192 19:24:23.461912
11193 19:24:23.468029 The programs included with the Debian GNU/Linux system are free software;
11194 19:24:23.474435 the exact distribution terms for each program are described in the
11195 19:24:23.478380 individual files in /usr/share/doc/*/copyright.
11196 19:24:23.478982
11197 19:24:23.484670 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11198 19:24:23.487808 permitted by applicable law.
11199 19:24:24.662319 Matched prompt #10: / #
11201 19:24:24.663473 Setting prompt string to ['/ #']
11202 19:24:24.663913 end: 2.2.5.1 login-action (duration 00:00:29) [common]
11204 19:24:24.664893 end: 2.2.5 auto-login-action (duration 00:00:29) [common]
11205 19:24:24.665364 start: 2.2.6 expect-shell-connection (timeout 00:03:14) [common]
11206 19:24:24.665742 Setting prompt string to ['/ #']
11207 19:24:24.666057 Forcing a shell prompt, looking for ['/ #']
11209 19:24:24.716754 / #
11210 19:24:24.717042 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11211 19:24:24.717353 Waiting using forced prompt support (timeout 00:02:30)
11212 19:24:24.721941
11213 19:24:24.722564 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11214 19:24:24.723015 start: 2.2.7 export-device-env (timeout 00:03:14) [common]
11216 19:24:24.824138 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/13420348/extract-nfsrootfs-oiegi9vu'
11217 19:24:24.830143 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/13420348/extract-nfsrootfs-oiegi9vu'
11219 19:24:24.931560 / # export NFS_SERVER_IP='192.168.201.1'
11220 19:24:24.937512 export NFS_SERVER_IP='192.168.201.1'
11221 19:24:24.938462 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11222 19:24:24.939174 end: 2.2 depthcharge-retry (duration 00:01:46) [common]
11223 19:24:24.939844 end: 2 depthcharge-action (duration 00:01:46) [common]
11224 19:24:24.940470 start: 3 lava-test-retry (timeout 00:07:32) [common]
11225 19:24:24.940991 start: 3.1 lava-test-shell (timeout 00:07:32) [common]
11226 19:24:24.941583 Using namespace: common
11228 19:24:25.042945 / # #
11229 19:24:25.043134 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11230 19:24:25.048604 #
11231 19:24:25.048981 Using /lava-13420348
11233 19:24:25.149526 / # export SHELL=/bin/bash
11234 19:24:25.155796 export SHELL=/bin/bash
11236 19:24:25.257154 / # . /lava-13420348/environment
11237 19:24:25.262522 . /lava-13420348/environment
11239 19:24:25.370078 / # /lava-13420348/bin/lava-test-runner /lava-13420348/0
11240 19:24:25.370726 Test shell timeout: 10s (minimum of the action and connection timeout)
11241 19:24:25.376604 /lava-13420348/bin/lava-test-runner /lava-13420348/0
11242 19:24:25.705474 + export TESTRUN_ID=0_timesync-off
11243 19:24:25.708567 + TESTRUN_ID=0_timesync-off
11244 19:24:25.711779 + cd /lava-13420348/0/tests/0_timesync-off
11245 19:24:25.715378 ++ cat uuid
11246 19:24:25.722554 + UUID=13420348_1.6.2.3.1
11247 19:24:25.722988 + set +x
11248 19:24:25.729672 <LAVA_SIGNAL_STARTRUN 0_timesync-off 13420348_1.6.2.3.1>
11249 19:24:25.730374 Received signal: <STARTRUN> 0_timesync-off 13420348_1.6.2.3.1
11250 19:24:25.730748 Starting test lava.0_timesync-off (13420348_1.6.2.3.1)
11251 19:24:25.731173 Skipping test definition patterns.
11252 19:24:25.732819 + systemctl stop systemd-timesyncd
11253 19:24:25.813706 + set +x
11254 19:24:25.816653 <LAVA_SIGNAL_ENDRUN 0_timesync-off 13420348_1.6.2.3.1>
11255 19:24:25.817331 Received signal: <ENDRUN> 0_timesync-off 13420348_1.6.2.3.1
11256 19:24:25.817745 Ending use of test pattern.
11257 19:24:25.818126 Ending test lava.0_timesync-off (13420348_1.6.2.3.1), duration 0.09
11259 19:24:25.919445 + export TESTRUN_ID=1_kselftest-arm64
11260 19:24:25.920153 + TESTRUN_ID=1_kselftest-arm64
11261 19:24:25.925602 + cd /lava-13420348/0/tests/1_kselftest-arm64
11262 19:24:25.925688 ++ cat uuid
11263 19:24:25.933131 + UUID=13420348_1.6.2.3.5
11264 19:24:25.933230 + set +x
11265 19:24:25.939810 <LAVA_SIGNAL_STARTRUN 1_kselftest-arm64 13420348_1.6.2.3.5>
11266 19:24:25.940082 Received signal: <STARTRUN> 1_kselftest-arm64 13420348_1.6.2.3.5
11267 19:24:25.940166 Starting test lava.1_kselftest-arm64 (13420348_1.6.2.3.5)
11268 19:24:25.940258 Skipping test definition patterns.
11269 19:24:25.943277 + cd ./automated/linux/kselftest/
11270 19:24:25.969345 + ./kselftest.sh -c arm64 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11271 19:24:26.023577 INFO: install_deps skipped
11272 19:24:26.551615 --2024-04-18 19:24:26-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11273 19:24:26.558349 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11274 19:24:26.690119 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11275 19:24:26.823503 HTTP request sent, awaiting response... 200 OK
11276 19:24:26.826904 Length: 1651832 (1.6M) [application/octet-stream]
11277 19:24:26.830275 Saving to: 'kselftest_armhf.tar.gz'
11278 19:24:26.830508
11279 19:24:26.830643
11280 19:24:27.091235 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11281 19:24:27.359597 kselftest_armhf.tar 2%[ ] 47.81K 174KB/s
11282 19:24:27.809014 kselftest_armhf.tar 13%[=> ] 219.84K 401KB/s
11283 19:24:27.895317 kselftest_armhf.tar 50%[=========> ] 817.06K 810KB/s
11284 19:24:27.901448 kselftest_armhf.tar 100%[===================>] 1.58M 1.44MB/s in 1.1s
11285 19:24:27.902060
11286 19:24:28.047969 2024-04-18 19:24:27 (1.44 MB/s) - 'kselftest_armhf.tar.gz' saved [1651832/1651832]
11287 19:24:28.048490
11288 19:24:32.828439 skiplist:
11289 19:24:32.832110 ========================================
11290 19:24:32.835049 ========================================
11291 19:24:32.888839 arm64:tags_test
11292 19:24:32.891964 arm64:run_tags_test.sh
11293 19:24:32.892062 arm64:fake_sigreturn_bad_magic
11294 19:24:32.895327 arm64:fake_sigreturn_bad_size
11295 19:24:32.898312 arm64:fake_sigreturn_bad_size_for_magic0
11296 19:24:32.902456 arm64:fake_sigreturn_duplicated_fpsimd
11297 19:24:32.905376 arm64:fake_sigreturn_misaligned_sp
11298 19:24:32.908789 arm64:fake_sigreturn_missing_fpsimd
11299 19:24:32.911867 arm64:fake_sigreturn_sme_change_vl
11300 19:24:32.915422 arm64:fake_sigreturn_sve_change_vl
11301 19:24:32.918479 arm64:mangle_pstate_invalid_compat_toggle
11302 19:24:32.921727 arm64:mangle_pstate_invalid_daif_bits
11303 19:24:32.924873 arm64:mangle_pstate_invalid_mode_el1h
11304 19:24:32.928359 arm64:mangle_pstate_invalid_mode_el1t
11305 19:24:32.931935 arm64:mangle_pstate_invalid_mode_el2h
11306 19:24:32.935157 arm64:mangle_pstate_invalid_mode_el2t
11307 19:24:32.938404 arm64:mangle_pstate_invalid_mode_el3h
11308 19:24:32.941474 arm64:mangle_pstate_invalid_mode_el3t
11309 19:24:32.944892 arm64:sme_trap_no_sm
11310 19:24:32.948152 arm64:sme_trap_non_streaming
11311 19:24:32.948304 arm64:sme_trap_za
11312 19:24:32.951455 arm64:sme_vl
11313 19:24:32.951568 arm64:ssve_regs
11314 19:24:32.955146 arm64:sve_regs
11315 19:24:32.955279 arm64:sve_vl
11316 19:24:32.955370 arm64:za_no_regs
11317 19:24:32.958304 arm64:za_regs
11318 19:24:32.958401 arm64:pac
11319 19:24:32.961709 arm64:fp-stress
11320 19:24:32.961789 arm64:sve-ptrace
11321 19:24:32.964821 arm64:sve-probe-vls
11322 19:24:32.964949 arm64:vec-syscfg
11323 19:24:32.965021 arm64:za-fork
11324 19:24:32.968116 arm64:za-ptrace
11325 19:24:32.971461 arm64:check_buffer_fill
11326 19:24:32.971560 arm64:check_child_memory
11327 19:24:32.974673 arm64:check_gcr_el1_cswitch
11328 19:24:32.977799 arm64:check_ksm_options
11329 19:24:32.977892 arm64:check_mmap_options
11330 19:24:32.981110 arm64:check_prctl
11331 19:24:32.984794 arm64:check_tags_inclusion
11332 19:24:32.984933 arm64:check_user_mem
11333 19:24:32.985047 arm64:btitest
11334 19:24:32.987742 arm64:nobtitest
11335 19:24:32.987828 arm64:hwcap
11336 19:24:32.991630 arm64:ptrace
11337 19:24:32.991717 arm64:syscall-abi
11338 19:24:32.991782 arm64:tpidr2
11339 19:24:32.997811 ============== Tests to run ===============
11340 19:24:32.997957 arm64:tags_test
11341 19:24:33.001646 arm64:run_tags_test.sh
11342 19:24:33.004412 arm64:fake_sigreturn_bad_magic
11343 19:24:33.004507 arm64:fake_sigreturn_bad_size
11344 19:24:33.011015 arm64:fake_sigreturn_bad_size_for_magic0
11345 19:24:33.014710 arm64:fake_sigreturn_duplicated_fpsimd
11346 19:24:33.014846 arm64:fake_sigreturn_misaligned_sp
11347 19:24:33.017760 arm64:fake_sigreturn_missing_fpsimd
11348 19:24:33.021735 arm64:fake_sigreturn_sme_change_vl
11349 19:24:33.024539 arm64:fake_sigreturn_sve_change_vl
11350 19:24:33.027859 arm64:mangle_pstate_invalid_compat_toggle
11351 19:24:33.031239 arm64:mangle_pstate_invalid_daif_bits
11352 19:24:33.037607 arm64:mangle_pstate_invalid_mode_el1h
11353 19:24:33.040970 arm64:mangle_pstate_invalid_mode_el1t
11354 19:24:33.044489 arm64:mangle_pstate_invalid_mode_el2h
11355 19:24:33.047624 arm64:mangle_pstate_invalid_mode_el2t
11356 19:24:33.050886 arm64:mangle_pstate_invalid_mode_el3h
11357 19:24:33.054344 arm64:mangle_pstate_invalid_mode_el3t
11358 19:24:33.054450 arm64:sme_trap_no_sm
11359 19:24:33.057824 arm64:sme_trap_non_streaming
11360 19:24:33.057935 arm64:sme_trap_za
11361 19:24:33.060874 arm64:sme_vl
11362 19:24:33.060976 arm64:ssve_regs
11363 19:24:33.064258 arm64:sve_regs
11364 19:24:33.064352 arm64:sve_vl
11365 19:24:33.067456 arm64:za_no_regs
11366 19:24:33.067566 arm64:za_regs
11367 19:24:33.067644 arm64:pac
11368 19:24:33.070622 arm64:fp-stress
11369 19:24:33.070716 arm64:sve-ptrace
11370 19:24:33.073961 arm64:sve-probe-vls
11371 19:24:33.074052 arm64:vec-syscfg
11372 19:24:33.077842 arm64:za-fork
11373 19:24:33.077962 arm64:za-ptrace
11374 19:24:33.080802 arm64:check_buffer_fill
11375 19:24:33.080895 arm64:check_child_memory
11376 19:24:33.084070 arm64:check_gcr_el1_cswitch
11377 19:24:33.087552 arm64:check_ksm_options
11378 19:24:33.087653 arm64:check_mmap_options
11379 19:24:33.090649 arm64:check_prctl
11380 19:24:33.094055 arm64:check_tags_inclusion
11381 19:24:33.094157 arm64:check_user_mem
11382 19:24:33.097230 arm64:btitest
11383 19:24:33.097326 arm64:nobtitest
11384 19:24:33.097394 arm64:hwcap
11385 19:24:33.100656 arm64:ptrace
11386 19:24:33.100776 arm64:syscall-abi
11387 19:24:33.103752 arm64:tpidr2
11388 19:24:33.107172 ===========End Tests to run ===============
11389 19:24:33.107270 shardfile-arm64 pass
11390 19:24:33.346165 <12>[ 37.188812] kselftest: Running tests in arm64
11391 19:24:33.359014 TAP version 13
11392 19:24:33.375602 1..48
11393 19:24:33.395107 # selftests: arm64: tags_test
11394 19:24:33.847645 ok 1 selftests: arm64: tags_test
11395 19:24:33.863620 # selftests: arm64: run_tags_test.sh
11396 19:24:33.915944 # --------------------
11397 19:24:33.919066 # running tags test
11398 19:24:33.919239 # --------------------
11399 19:24:33.922178 # [PASS]
11400 19:24:33.925319 ok 2 selftests: arm64: run_tags_test.sh
11401 19:24:33.939861 # selftests: arm64: fake_sigreturn_bad_magic
11402 19:24:33.987977 # Registered handlers for all signals.
11403 19:24:33.988176 # Detected MINSTKSIGSZ:4720
11404 19:24:33.991529 # Testcase initialized.
11405 19:24:33.994848 # uc context validated.
11406 19:24:33.998283 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11407 19:24:34.001198 # Handled SIG_COPYCTX
11408 19:24:34.001331 # Available space:3568
11409 19:24:34.007888 # Using badly built context - ERR: BAD MAGIC !
11410 19:24:34.014687 # SIG_OK -- SP:0xFFFFF6ABCB10 si_addr@:0xfffff6abcb10 si_code:2 token@:0xfffff6abb8b0 offset:-4704
11411 19:24:34.017994 # ==>> completed. PASS(1)
11412 19:24:34.024758 # # FAKE_SIGRETURN_BAD_MAGIC :: Trigger a sigreturn with a sigframe with a bad magic
11413 19:24:34.031176 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF6ABB8B0
11414 19:24:34.038358 ok 3 selftests: arm64: fake_sigreturn_bad_magic
11415 19:24:34.041120 # selftests: arm64: fake_sigreturn_bad_size
11416 19:24:34.058518 # Registered handlers for all signals.
11417 19:24:34.058714 # Detected MINSTKSIGSZ:4720
11418 19:24:34.061599 # Testcase initialized.
11419 19:24:34.065202 # uc context validated.
11420 19:24:34.068778 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11421 19:24:34.071772 # Handled SIG_COPYCTX
11422 19:24:34.071901 # Available space:3568
11423 19:24:34.074954 # uc context validated.
11424 19:24:34.081567 # Using badly built context - ERR: Bad size for esr_context
11425 19:24:34.088469 # SIG_OK -- SP:0xFFFFCCD1CD00 si_addr@:0xffffccd1cd00 si_code:2 token@:0xffffccd1baa0 offset:-4704
11426 19:24:34.091842 # ==>> completed. PASS(1)
11427 19:24:34.098495 # # FAKE_SIGRETURN_BAD_SIZE :: Triggers a sigreturn with a overrun __reserved area
11428 19:24:34.104920 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFCCD1BAA0
11429 19:24:34.108438 ok 4 selftests: arm64: fake_sigreturn_bad_size
11430 19:24:34.115140 # selftests: arm64: fake_sigreturn_bad_size_for_magic0
11431 19:24:34.146956 # Registered handlers for all signals.
11432 19:24:34.147150 # Detected MINSTKSIGSZ:4720
11433 19:24:34.150418 # Testcase initialized.
11434 19:24:34.153465 # uc context validated.
11435 19:24:34.156670 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11436 19:24:34.160361 # Handled SIG_COPYCTX
11437 19:24:34.160455 # Available space:3568
11438 19:24:34.166869 # Using badly built context - ERR: Bad size for terminator
11439 19:24:34.176890 # SIG_OK -- SP:0xFFFFDB60A780 si_addr@:0xffffdb60a780 si_code:2 token@:0xffffdb609520 offset:-4704
11440 19:24:34.177051 # ==>> completed. PASS(1)
11441 19:24:34.186974 # # FAKE_SIGRETURN_BAD_SIZE_FOR_TERMINATOR :: Trigger a sigreturn using non-zero size terminator
11442 19:24:34.193908 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFDB609520
11443 19:24:34.196819 ok 5 selftests: arm64: fake_sigreturn_bad_size_for_magic0
11444 19:24:34.203740 # selftests: arm64: fake_sigreturn_duplicated_fpsimd
11445 19:24:34.220541 # Registered handlers for all signals.
11446 19:24:34.220711 # Detected MINSTKSIGSZ:4720
11447 19:24:34.224169 # Testcase initialized.
11448 19:24:34.226828 # uc context validated.
11449 19:24:34.230464 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11450 19:24:34.233842 # Handled SIG_COPYCTX
11451 19:24:34.233962 # Available space:3568
11452 19:24:34.240486 # Using badly built context - ERR: Multiple FPSIMD_MAGIC
11453 19:24:34.250147 # SIG_OK -- SP:0xFFFFEF0C8FA0 si_addr@:0xffffef0c8fa0 si_code:2 token@:0xffffef0c7d40 offset:-4704
11454 19:24:34.250313 # ==>> completed. PASS(1)
11455 19:24:34.260709 # # FAKE_SIGRETURN_DUPLICATED_FPSIMD :: Triggers a sigreturn including two fpsimd_context
11456 19:24:34.267076 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFEF0C7D40
11457 19:24:34.270161 ok 6 selftests: arm64: fake_sigreturn_duplicated_fpsimd
11458 19:24:34.273907 # selftests: arm64: fake_sigreturn_misaligned_sp
11459 19:24:34.287857 # Registered handlers for all signals.
11460 19:24:34.288001 # Detected MINSTKSIGSZ:4720
11461 19:24:34.291233 # Testcase initialized.
11462 19:24:34.294430 # uc context validated.
11463 19:24:34.297853 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11464 19:24:34.301447 # Handled SIG_COPYCTX
11465 19:24:34.307569 # SIG_OK -- SP:0xFFFFDF4CEBF3 si_addr@:0xffffdf4cebf3 si_code:2 token@:0xffffdf4cebf3 offset:0
11466 19:24:34.311085 # ==>> completed. PASS(1)
11467 19:24:34.317751 # # FAKE_SIGRETURN_MISALIGNED_SP :: Triggers a sigreturn with a misaligned sigframe
11468 19:24:34.324360 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFDF4CEBF3
11469 19:24:34.331208 ok 7 selftests: arm64: fake_sigreturn_misaligned_sp
11470 19:24:34.334156 # selftests: arm64: fake_sigreturn_missing_fpsimd
11471 19:24:34.384207 # Registered handlers for all signals.
11472 19:24:34.384376 # Detected MINSTKSIGSZ:4720
11473 19:24:34.387826 # Testcase initialized.
11474 19:24:34.390533 # uc context validated.
11475 19:24:34.394127 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11476 19:24:34.397084 # Handled SIG_COPYCTX
11477 19:24:34.400572 # Mangling template header. Spare space:4096
11478 19:24:34.403961 # Using badly built context - ERR: Missing FPSIMD
11479 19:24:34.413844 # SIG_OK -- SP:0xFFFFE2A0BD80 si_addr@:0xffffe2a0bd80 si_code:2 token@:0xffffe2a0ab20 offset:-4704
11480 19:24:34.417372 # ==>> completed. PASS(1)
11481 19:24:34.424045 # # FAKE_SIGRETURN_MISSING_FPSIMD :: Triggers a sigreturn with a missing fpsimd_context
11482 19:24:34.430409 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFE2A0AB20
11483 19:24:34.433914 ok 8 selftests: arm64: fake_sigreturn_missing_fpsimd
11484 19:24:34.440777 # selftests: arm64: fake_sigreturn_sme_change_vl
11485 19:24:34.466047 # Registered handlers for all signals.
11486 19:24:34.466222 # Detected MINSTKSIGSZ:4720
11487 19:24:34.469824 # ==>> completed. SKIP.
11488 19:24:34.476355 # # FAKE_SIGRETURN_SSVE_CHANGE :: Attempt to change Streaming SVE VL
11489 19:24:34.479811 ok 9 selftests: arm64: fake_sigreturn_sme_change_vl # SKIP
11490 19:24:34.486504 # selftests: arm64: fake_sigreturn_sve_change_vl
11491 19:24:34.557803 # Registered handlers for all signals.
11492 19:24:34.557993 # Detected MINSTKSIGSZ:4720
11493 19:24:34.561029 # ==>> completed. SKIP.
11494 19:24:34.564463 # # FAKE_SIGRETURN_SVE_CHANGE :: Attempt to change SVE VL
11495 19:24:34.571287 ok 10 selftests: arm64: fake_sigreturn_sve_change_vl # SKIP
11496 19:24:34.578174 # selftests: arm64: mangle_pstate_invalid_compat_toggle
11497 19:24:34.643138 # Registered handlers for all signals.
11498 19:24:34.643293 # Detected MINSTKSIGSZ:4720
11499 19:24:34.646102 # Testcase initialized.
11500 19:24:34.649482 # uc context validated.
11501 19:24:34.649583 # Handled SIG_TRIG
11502 19:24:34.659659 # SIG_OK -- SP:0xFFFFD4B42020 si_addr@:0xffffd4b42020 si_code:2 token@:(nil) offset:-281474250317856
11503 19:24:34.663037 # ==>> completed. PASS(1)
11504 19:24:34.669416 # # MANGLE_PSTATE_INVALID_STATE_TOGGLE :: Mangling uc_mcontext with INVALID STATE_TOGGLE
11505 19:24:34.676407 ok 11 selftests: arm64: mangle_pstate_invalid_compat_toggle
11506 19:24:34.679624 # selftests: arm64: mangle_pstate_invalid_daif_bits
11507 19:24:34.730027 # Registered handlers for all signals.
11508 19:24:34.730195 # Detected MINSTKSIGSZ:4720
11509 19:24:34.733250 # Testcase initialized.
11510 19:24:34.736384 # uc context validated.
11511 19:24:34.736543 # Handled SIG_TRIG
11512 19:24:34.746478 # SIG_OK -- SP:0xFFFFDD6D8960 si_addr@:0xffffdd6d8960 si_code:2 token@:(nil) offset:-281474396686688
11513 19:24:34.749735 # ==>> completed. PASS(1)
11514 19:24:34.756151 # # MANGLE_PSTATE_INVALID_DAIF_BITS :: Mangling uc_mcontext with INVALID DAIF_BITS
11515 19:24:34.759477 ok 12 selftests: arm64: mangle_pstate_invalid_daif_bits
11516 19:24:34.766411 # selftests: arm64: mangle_pstate_invalid_mode_el1h
11517 19:24:34.811330 # Registered handlers for all signals.
11518 19:24:34.811476 # Detected MINSTKSIGSZ:4720
11519 19:24:34.814393 # Testcase initialized.
11520 19:24:34.817923 # uc context validated.
11521 19:24:34.818020 # Handled SIG_TRIG
11522 19:24:34.827708 # SIG_OK -- SP:0xFFFFD58988D0 si_addr@:0xffffd58988d0 si_code:2 token@:(nil) offset:-281474264303824
11523 19:24:34.830720 # ==>> completed. PASS(1)
11524 19:24:34.837606 # # MANGLE_PSTATE_INVALID_MODE_EL1h :: Mangling uc_mcontext INVALID MODE EL1h
11525 19:24:34.841095 ok 13 selftests: arm64: mangle_pstate_invalid_mode_el1h
11526 19:24:34.847446 # selftests: arm64: mangle_pstate_invalid_mode_el1t
11527 19:24:34.914739 # Registered handlers for all signals.
11528 19:24:34.914882 # Detected MINSTKSIGSZ:4720
11529 19:24:34.918020 # Testcase initialized.
11530 19:24:34.921645 # uc context validated.
11531 19:24:34.921740 # Handled SIG_TRIG
11532 19:24:34.931463 # SIG_OK -- SP:0xFFFFC953EFE0 si_addr@:0xffffc953efe0 si_code:2 token@:(nil) offset:-281474059464672
11533 19:24:34.935416 # ==>> completed. PASS(1)
11534 19:24:34.941583 # # MANGLE_PSTATE_INVALID_MODE_EL1t :: Mangling uc_mcontext INVALID MODE EL1t
11535 19:24:34.944970 ok 14 selftests: arm64: mangle_pstate_invalid_mode_el1t
11536 19:24:34.951558 # selftests: arm64: mangle_pstate_invalid_mode_el2h
11537 19:24:35.001880 # Registered handlers for all signals.
11538 19:24:35.002026 # Detected MINSTKSIGSZ:4720
11539 19:24:35.005499 # Testcase initialized.
11540 19:24:35.008797 # uc context validated.
11541 19:24:35.008887 # Handled SIG_TRIG
11542 19:24:35.018945 # SIG_OK -- SP:0xFFFFE6A436F0 si_addr@:0xffffe6a436f0 si_code:2 token@:(nil) offset:-281474551265008
11543 19:24:35.021898 # ==>> completed. PASS(1)
11544 19:24:35.028583 # # MANGLE_PSTATE_INVALID_MODE_EL2h :: Mangling uc_mcontext INVALID MODE EL2h
11545 19:24:35.031917 ok 15 selftests: arm64: mangle_pstate_invalid_mode_el2h
11546 19:24:35.038353 # selftests: arm64: mangle_pstate_invalid_mode_el2t
11547 19:24:35.088137 # Registered handlers for all signals.
11548 19:24:35.088315 # Detected MINSTKSIGSZ:4720
11549 19:24:35.091779 # Testcase initialized.
11550 19:24:35.095040 # uc context validated.
11551 19:24:35.095169 # Handled SIG_TRIG
11552 19:24:35.105471 # SIG_OK -- SP:0xFFFFE0B16160 si_addr@:0xffffe0b16160 si_code:2 token@:(nil) offset:-281474451464544
11553 19:24:35.108281 # ==>> completed. PASS(1)
11554 19:24:35.115323 # # MANGLE_PSTATE_INVALID_MODE_EL2t :: Mangling uc_mcontext INVALID MODE EL2t
11555 19:24:35.118088 ok 16 selftests: arm64: mangle_pstate_invalid_mode_el2t
11556 19:24:35.124957 # selftests: arm64: mangle_pstate_invalid_mode_el3h
11557 19:24:35.190658 # Registered handlers for all signals.
11558 19:24:35.190834 # Detected MINSTKSIGSZ:4720
11559 19:24:35.193873 # Testcase initialized.
11560 19:24:35.196774 # uc context validated.
11561 19:24:35.196897 # Handled SIG_TRIG
11562 19:24:35.207293 # SIG_OK -- SP:0xFFFFD7B41B80 si_addr@:0xffffd7b41b80 si_code:2 token@:(nil) offset:-281474300648320
11563 19:24:35.210506 # ==>> completed. PASS(1)
11564 19:24:35.216901 # # MANGLE_PSTATE_INVALID_MODE_EL3h :: Mangling uc_mcontext INVALID MODE EL3h
11565 19:24:35.220609 ok 17 selftests: arm64: mangle_pstate_invalid_mode_el3h
11566 19:24:35.223764 # selftests: arm64: mangle_pstate_invalid_mode_el3t
11567 19:24:35.295766 # Registered handlers for all signals.
11568 19:24:35.295980 # Detected MINSTKSIGSZ:4720
11569 19:24:35.298785 # Testcase initialized.
11570 19:24:35.301863 # uc context validated.
11571 19:24:35.301966 # Handled SIG_TRIG
11572 19:24:35.312421 # SIG_OK -- SP:0xFFFFF22EAB40 si_addr@:0xfffff22eab40 si_code:2 token@:(nil) offset:-281474744888128
11573 19:24:35.315142 # ==>> completed. PASS(1)
11574 19:24:35.321937 # # MANGLE_PSTATE_INVALID_MODE_EL3t :: Mangling uc_mcontext INVALID MODE EL3t
11575 19:24:35.325488 ok 18 selftests: arm64: mangle_pstate_invalid_mode_el3t
11576 19:24:35.328510 # selftests: arm64: sme_trap_no_sm
11577 19:24:35.390181 # Registered handlers for all signals.
11578 19:24:35.390374 # Detected MINSTKSIGSZ:4720
11579 19:24:35.392853 # ==>> completed. SKIP.
11580 19:24:35.402851 # # SME trap without SM :: Check that we get a SIGILL if we use streaming mode without enabling it
11581 19:24:35.406197 ok 19 selftests: arm64: sme_trap_no_sm # SKIP
11582 19:24:35.413605 # selftests: arm64: sme_trap_non_streaming
11583 19:24:35.468114 # Registered handlers for all signals.
11584 19:24:35.468287 # Detected MINSTKSIGSZ:4720
11585 19:24:35.471613 # ==>> completed. SKIP.
11586 19:24:35.481369 # # SME SM trap unsupported instruction :: Check that we get a SIGILL if we use an unsupported instruction in streaming mode
11587 19:24:35.487802 ok 20 selftests: arm64: sme_trap_non_streaming # SKIP
11588 19:24:35.491239 # selftests: arm64: sme_trap_za
11589 19:24:35.567160 # Registered handlers for all signals.
11590 19:24:35.567309 # Detected MINSTKSIGSZ:4720
11591 19:24:35.570605 # Testcase initialized.
11592 19:24:35.580271 # SIG_OK -- SP:0xFFFFEA4970C0 si_addr@:0xaaaaaf802510 si_code:1 token@:(nil) offset:-187650065573136
11593 19:24:35.580384 # ==>> completed. PASS(1)
11594 19:24:35.590069 # # SME ZA trap :: Check that we get a SIGILL if we access ZA without enabling
11595 19:24:35.590207 ok 21 selftests: arm64: sme_trap_za
11596 19:24:35.593084 # selftests: arm64: sme_vl
11597 19:24:35.644944 # Registered handlers for all signals.
11598 19:24:35.645103 # Detected MINSTKSIGSZ:4720
11599 19:24:35.648602 # ==>> completed. SKIP.
11600 19:24:35.651613 # # SME VL :: Check that we get the right SME VL reported
11601 19:24:35.657766 ok 22 selftests: arm64: sme_vl # SKIP
11602 19:24:35.661846 # selftests: arm64: ssve_regs
11603 19:24:35.719617 # Registered handlers for all signals.
11604 19:24:35.719770 # Detected MINSTKSIGSZ:4720
11605 19:24:35.723120 # ==>> completed. SKIP.
11606 19:24:35.729466 # # Streaming SVE registers :: Check that we get the right Streaming SVE registers reported
11607 19:24:35.735652 ok 23 selftests: arm64: ssve_regs # SKIP
11608 19:24:35.739718 # selftests: arm64: sve_regs
11609 19:24:35.801079 # Registered handlers for all signals.
11610 19:24:35.801295 # Detected MINSTKSIGSZ:4720
11611 19:24:35.803917 # ==>> completed. SKIP.
11612 19:24:35.810922 # # SVE registers :: Check that we get the right SVE registers reported
11613 19:24:35.814133 ok 24 selftests: arm64: sve_regs # SKIP
11614 19:24:35.820392 # selftests: arm64: sve_vl
11615 19:24:35.896304 # Registered handlers for all signals.
11616 19:24:35.896491 # Detected MINSTKSIGSZ:4720
11617 19:24:35.899699 # ==>> completed. SKIP.
11618 19:24:35.903151 # # SVE VL :: Check that we get the right SVE VL reported
11619 19:24:35.909773 ok 25 selftests: arm64: sve_vl # SKIP
11620 19:24:35.914153 # selftests: arm64: za_no_regs
11621 19:24:35.986905 # Registered handlers for all signals.
11622 19:24:35.987054 # Detected MINSTKSIGSZ:4720
11623 19:24:35.990545 # ==>> completed. SKIP.
11624 19:24:35.997123 # # ZA registers - ZA disabled :: Check ZA context with ZA disabled
11625 19:24:36.000038 ok 26 selftests: arm64: za_no_regs # SKIP
11626 19:24:36.006155 # selftests: arm64: za_regs
11627 19:24:36.063636 # Registered handlers for all signals.
11628 19:24:36.063790 # Detected MINSTKSIGSZ:4720
11629 19:24:36.066788 # ==>> completed. SKIP.
11630 19:24:36.073717 # # ZA register :: Check that we get the right ZA registers reported
11631 19:24:36.076526 ok 27 selftests: arm64: za_regs # SKIP
11632 19:24:36.083149 # selftests: arm64: pac
11633 19:24:36.153388 # TAP version 13
11634 19:24:36.153545 # 1..7
11635 19:24:36.156676 # # Starting 7 tests from 1 test cases.
11636 19:24:36.160090 # # RUN global.corrupt_pac ...
11637 19:24:36.163629 # # SKIP PAUTH not enabled
11638 19:24:36.166466 # # OK global.corrupt_pac
11639 19:24:36.170090 # ok 1 # SKIP PAUTH not enabled
11640 19:24:36.176486 # # RUN global.pac_instructions_not_nop ...
11641 19:24:36.180005 # # SKIP PAUTH not enabled
11642 19:24:36.183551 # # OK global.pac_instructions_not_nop
11643 19:24:36.186746 # ok 2 # SKIP PAUTH not enabled
11644 19:24:36.193603 # # RUN global.pac_instructions_not_nop_generic ...
11645 19:24:36.196617 # # SKIP Generic PAUTH not enabled
11646 19:24:36.199999 # # OK global.pac_instructions_not_nop_generic
11647 19:24:36.202952 # ok 3 # SKIP Generic PAUTH not enabled
11648 19:24:36.209788 # # RUN global.single_thread_different_keys ...
11649 19:24:36.213220 # # SKIP PAUTH not enabled
11650 19:24:36.216530 # # OK global.single_thread_different_keys
11651 19:24:36.219869 # ok 4 # SKIP PAUTH not enabled
11652 19:24:36.226377 # # RUN global.exec_changed_keys ...
11653 19:24:36.229940 # # SKIP PAUTH not enabled
11654 19:24:36.233023 # # OK global.exec_changed_keys
11655 19:24:36.236579 # ok 5 # SKIP PAUTH not enabled
11656 19:24:36.239870 # # RUN global.context_switch_keep_keys ...
11657 19:24:36.243373 # # SKIP PAUTH not enabled
11658 19:24:36.246200 # # OK global.context_switch_keep_keys
11659 19:24:36.249587 # ok 6 # SKIP PAUTH not enabled
11660 19:24:36.256325 # # RUN global.context_switch_keep_keys_generic ...
11661 19:24:36.259700 # # SKIP Generic PAUTH not enabled
11662 19:24:36.266572 # # OK global.context_switch_keep_keys_generic
11663 19:24:36.269629 # ok 7 # SKIP Generic PAUTH not enabled
11664 19:24:36.272776 # # PASSED: 7 / 7 tests passed.
11665 19:24:36.276358 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:7 error:0
11666 19:24:36.279529 ok 28 selftests: arm64: pac
11667 19:24:36.282695 # selftests: arm64: fp-stress
11668 19:24:41.985628 <6>[ 45.832382] vpu: disabling
11669 19:24:41.988808 <6>[ 45.835435] vproc2: disabling
11670 19:24:41.992126 <6>[ 45.838712] vproc1: disabling
11671 19:24:41.995551 <6>[ 45.841991] vaud18: disabling
11672 19:24:42.001824 <6>[ 45.845447] vsram_others: disabling
11673 19:24:42.005376 <6>[ 45.849357] va09: disabling
11674 19:24:42.008530 <6>[ 45.852480] vsram_md: disabling
11675 19:24:42.011538 <6>[ 45.855988] Vgpu: disabling
11676 19:24:46.190930 # TAP version 13
11677 19:24:46.191110 # 1..16
11678 19:24:46.194237 # # 8 CPUs, 0 SVE VLs, 0 SME VLs
11679 19:24:46.197411 # # Will run for 10s
11680 19:24:46.197505 # # Started FPSIMD-0-0
11681 19:24:46.200521 # # Started FPSIMD-0-1
11682 19:24:46.204258 # # Started FPSIMD-1-0
11683 19:24:46.204350 # # Started FPSIMD-1-1
11684 19:24:46.207515 # # Started FPSIMD-2-0
11685 19:24:46.207604 # # Started FPSIMD-2-1
11686 19:24:46.210397 # # Started FPSIMD-3-0
11687 19:24:46.213802 # # Started FPSIMD-3-1
11688 19:24:46.213892 # # Started FPSIMD-4-0
11689 19:24:46.217035 # # Started FPSIMD-4-1
11690 19:24:46.220591 # # Started FPSIMD-5-0
11691 19:24:46.220702 # # Started FPSIMD-5-1
11692 19:24:46.224083 # # Started FPSIMD-6-0
11693 19:24:46.224167 # # Started FPSIMD-6-1
11694 19:24:46.227416 # # Started FPSIMD-7-0
11695 19:24:46.230858 # # Started FPSIMD-7-1
11696 19:24:46.233573 # # FPSIMD-0-0: Vector length: 128 bits
11697 19:24:46.233657 # # FPSIMD-0-0: PID: 1166
11698 19:24:46.240770 # # FPSIMD-0-1: Vector length: 128 bits
11699 19:24:46.240875 # # FPSIMD-0-1: PID: 1167
11700 19:24:46.243567 # # FPSIMD-2-1: Vector length: 128 bits
11701 19:24:46.247025 # # FPSIMD-2-1: PID: 1171
11702 19:24:46.250402 # # FPSIMD-2-0: Vector length: 128 bits
11703 19:24:46.254047 # # FPSIMD-2-0: PID: 1170
11704 19:24:46.257124 # # FPSIMD-1-0: Vector length: 128 bits
11705 19:24:46.260409 # # FPSIMD-1-0: PID: 1168
11706 19:24:46.263734 # # FPSIMD-6-0: Vector length: 128 bits
11707 19:24:46.263826 # # FPSIMD-6-0: PID: 1178
11708 19:24:46.267482 # # FPSIMD-1-1: Vector length: 128 bits
11709 19:24:46.270226 # # FPSIMD-1-1: PID: 1169
11710 19:24:46.273724 # # FPSIMD-5-0: Vector length: 128 bits
11711 19:24:46.277387 # # FPSIMD-5-0: PID: 1176
11712 19:24:46.280223 # # FPSIMD-7-0: Vector length: 128 bits
11713 19:24:46.283748 # # FPSIMD-7-0: PID: 1180
11714 19:24:46.286664 # # FPSIMD-4-1: Vector length: 128 bits
11715 19:24:46.290072 # # FPSIMD-4-1: PID: 1175
11716 19:24:46.293326 # # FPSIMD-5-1: Vector length: 128 bits
11717 19:24:46.293416 # # FPSIMD-5-1: PID: 1177
11718 19:24:46.296805 # # FPSIMD-6-1: Vector length: 128 bits
11719 19:24:46.300071 # # FPSIMD-6-1: PID: 1179
11720 19:24:46.303141 # # FPSIMD-3-1: Vector length: 128 bits
11721 19:24:46.306735 # # FPSIMD-3-1: PID: 1173
11722 19:24:46.309880 # # FPSIMD-7-1: Vector length: 128 bits
11723 19:24:46.313456 # # FPSIMD-7-1: PID: 1181
11724 19:24:46.316793 # # FPSIMD-4-0: Vector length: 128 bits
11725 19:24:46.316894 # # FPSIMD-4-0: PID: 1174
11726 19:24:46.323379 # # FPSIMD-3-0: Vector length: 128 bits
11727 19:24:46.323485 # # FPSIMD-3-0: PID: 1172
11728 19:24:46.326787 # # Finishing up...
11729 19:24:46.333164 # # FPSIMD-2-1: Terminated by signal 15, no error, iterations=1216857, signals=10
11730 19:24:46.339773 # # FPSIMD-0-1: Terminated by signal 15, no error, iterations=1200221, signals=10
11731 19:24:46.346410 # # FPSIMD-2-0: Terminated by signal 15, no error, iterations=1149136, signals=10
11732 19:24:46.352938 # # FPSIMD-3-1: Terminated by signal 15, no error, iterations=1275518, signals=10
11733 19:24:46.362888 # # FPSIMD-1-0: Terminated by signal 15, no error, iterations=1305574, signals=10
11734 19:24:46.369723 # # FPSIMD-7-1: Terminated by signal 15, no error, iterations=1323105, signals=10
11735 19:24:46.376771 # # FPSIMD-7-0: Terminated by signal 15, no error, iterations=1227983, signals=10
11736 19:24:46.376899 # ok 1 FPSIMD-0-0
11737 19:24:46.379688 # ok 2 FPSIMD-0-1
11738 19:24:46.379778 # ok 3 FPSIMD-1-0
11739 19:24:46.383180 # ok 4 FPSIMD-1-1
11740 19:24:46.383270 # ok 5 FPSIMD-2-0
11741 19:24:46.386429 # ok 6 FPSIMD-2-1
11742 19:24:46.386519 # ok 7 FPSIMD-3-0
11743 19:24:46.389932 # ok 8 FPSIMD-3-1
11744 19:24:46.390020 # ok 9 FPSIMD-4-0
11745 19:24:46.392911 # ok 10 FPSIMD-4-1
11746 19:24:46.392995 # ok 11 FPSIMD-5-0
11747 19:24:46.396348 # ok 12 FPSIMD-5-1
11748 19:24:46.399753 # ok 13 FPSIMD-6-0
11749 19:24:46.399880 # ok 14 FPSIMD-6-1
11750 19:24:46.402494 # ok 15 FPSIMD-7-0
11751 19:24:46.402578 # ok 16 FPSIMD-7-1
11752 19:24:46.409495 # # FPSIMD-6-0: Terminated by signal 15, no error, iterations=1230567, signals=9
11753 19:24:46.416409 # # FPSIMD-6-1: Terminated by signal 15, no error, iterations=971447, signals=10
11754 19:24:46.425946 # # FPSIMD-4-1: Terminated by signal 15, no error, iterations=1575137, signals=10
11755 19:24:46.432432 # # FPSIMD-1-1: Terminated by signal 15, no error, iterations=1371641, signals=10
11756 19:24:46.439691 # # FPSIMD-5-0: Terminated by signal 15, no error, iterations=1284618, signals=9
11757 19:24:46.445816 # # FPSIMD-4-0: Terminated by signal 15, no error, iterations=1127558, signals=10
11758 19:24:46.452774 # # FPSIMD-0-0: Terminated by signal 15, no error, iterations=953870, signals=10
11759 19:24:46.459081 # # FPSIMD-5-1: Terminated by signal 15, no error, iterations=959474, signals=10
11760 19:24:46.469097 # # FPSIMD-3-0: Terminated by signal 15, no error, iterations=1146754, signals=9
11761 19:24:46.472616 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:0 error:0
11762 19:24:46.475648 ok 29 selftests: arm64: fp-stress
11763 19:24:46.479467 # selftests: arm64: sve-ptrace
11764 19:24:46.479557 # TAP version 13
11765 19:24:46.482471 # 1..4104
11766 19:24:46.482562 # ok 2 # SKIP SVE not available
11767 19:24:46.489071 # # Planned tests != run tests (4104 != 1)
11768 19:24:46.492369 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11769 19:24:46.495798 ok 30 selftests: arm64: sve-ptrace # SKIP
11770 19:24:46.499209 # selftests: arm64: sve-probe-vls
11771 19:24:46.502267 # TAP version 13
11772 19:24:46.502373 # 1..2
11773 19:24:46.505478 # ok 2 # SKIP SVE not available
11774 19:24:46.509203 # # Planned tests != run tests (2 != 1)
11775 19:24:46.512765 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11776 19:24:46.516136 ok 31 selftests: arm64: sve-probe-vls # SKIP
11777 19:24:46.518904 # selftests: arm64: vec-syscfg
11778 19:24:46.522222 # TAP version 13
11779 19:24:46.522318 # 1..20
11780 19:24:46.525648 # ok 1 # SKIP SVE not supported
11781 19:24:46.529422 # ok 2 # SKIP SVE not supported
11782 19:24:46.531976 # ok 3 # SKIP SVE not supported
11783 19:24:46.532088 # ok 4 # SKIP SVE not supported
11784 19:24:46.535425 # ok 5 # SKIP SVE not supported
11785 19:24:46.539054 # ok 6 # SKIP SVE not supported
11786 19:24:46.541972 # ok 7 # SKIP SVE not supported
11787 19:24:46.545630 # ok 8 # SKIP SVE not supported
11788 19:24:46.549246 # ok 9 # SKIP SVE not supported
11789 19:24:46.552637 # ok 10 # SKIP SVE not supported
11790 19:24:46.552742 # ok 11 # SKIP SME not supported
11791 19:24:46.555886 # ok 12 # SKIP SME not supported
11792 19:24:46.559257 # ok 13 # SKIP SME not supported
11793 19:24:46.562173 # ok 14 # SKIP SME not supported
11794 19:24:46.565592 # ok 15 # SKIP SME not supported
11795 19:24:46.568916 # ok 16 # SKIP SME not supported
11796 19:24:46.572113 # ok 17 # SKIP SME not supported
11797 19:24:46.575535 # ok 18 # SKIP SME not supported
11798 19:24:46.578975 # ok 19 # SKIP SME not supported
11799 19:24:46.579088 # ok 20 # SKIP SME not supported
11800 19:24:46.585334 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:20 error:0
11801 19:24:46.588901 ok 32 selftests: arm64: vec-syscfg
11802 19:24:46.592257 # selftests: arm64: za-fork
11803 19:24:46.592358 # TAP version 13
11804 19:24:46.592426 # 1..1
11805 19:24:46.595242 # # PID: 1258
11806 19:24:46.598832 # # SME support not present
11807 19:24:46.598929 # ok 0 skipped
11808 19:24:46.602144 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11809 19:24:46.605589 ok 33 selftests: arm64: za-fork
11810 19:24:46.608890 # selftests: arm64: za-ptrace
11811 19:24:46.611920 # TAP version 13
11812 19:24:46.612015 # 1..1
11813 19:24:46.615171 # ok 2 # SKIP SME not available
11814 19:24:46.618876 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11815 19:24:46.621777 ok 34 selftests: arm64: za-ptrace # SKIP
11816 19:24:46.632879 # selftests: arm64: check_buffer_fill
11817 19:24:46.691051 # # SKIP: MTE features unavailable
11818 19:24:46.698820 ok 35 selftests: arm64: check_buffer_fill # SKIP
11819 19:24:46.715903 # selftests: arm64: check_child_memory
11820 19:24:46.781598 # # SKIP: MTE features unavailable
11821 19:24:46.788427 ok 36 selftests: arm64: check_child_memory # SKIP
11822 19:24:46.806448 # selftests: arm64: check_gcr_el1_cswitch
11823 19:24:46.876809 # # SKIP: MTE features unavailable
11824 19:24:46.884381 ok 37 selftests: arm64: check_gcr_el1_cswitch # SKIP
11825 19:24:46.901078 # selftests: arm64: check_ksm_options
11826 19:24:46.968027 # # SKIP: MTE features unavailable
11827 19:24:46.975254 ok 38 selftests: arm64: check_ksm_options # SKIP
11828 19:24:46.994429 # selftests: arm64: check_mmap_options
11829 19:24:47.066552 # # SKIP: MTE features unavailable
11830 19:24:47.074265 ok 39 selftests: arm64: check_mmap_options # SKIP
11831 19:24:47.089174 # selftests: arm64: check_prctl
11832 19:24:47.146929 # TAP version 13
11833 19:24:47.147091 # 1..5
11834 19:24:47.150092 # ok 1 check_basic_read
11835 19:24:47.150183 # ok 2 NONE
11836 19:24:47.153446 # ok 3 # SKIP SYNC
11837 19:24:47.153535 # ok 4 # SKIP ASYNC
11838 19:24:47.156829 # ok 5 # SKIP SYNC+ASYNC
11839 19:24:47.160024 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:3 error:0
11840 19:24:47.163497 ok 40 selftests: arm64: check_prctl
11841 19:24:47.170246 # selftests: arm64: check_tags_inclusion
11842 19:24:47.228500 # # SKIP: MTE features unavailable
11843 19:24:47.235885 ok 41 selftests: arm64: check_tags_inclusion # SKIP
11844 19:24:47.248226 # selftests: arm64: check_user_mem
11845 19:24:47.314504 # # SKIP: MTE features unavailable
11846 19:24:47.322560 ok 42 selftests: arm64: check_user_mem # SKIP
11847 19:24:47.335758 # selftests: arm64: btitest
11848 19:24:47.403560 # TAP version 13
11849 19:24:47.403727 # 1..18
11850 19:24:47.406493 # # HWCAP_PACA not present
11851 19:24:47.409761 # # HWCAP2_BTI not present
11852 19:24:47.409855 # # Test binary built for BTI
11853 19:24:47.416644 # ok 1 nohint_func/call_using_br_x0 # SKIP
11854 19:24:47.419697 # ok 1 nohint_func/call_using_br_x16 # SKIP
11855 19:24:47.423125 # ok 1 nohint_func/call_using_blr # SKIP
11856 19:24:47.426887 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11857 19:24:47.429672 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11858 19:24:47.436116 # ok 1 bti_none_func/call_using_blr # SKIP
11859 19:24:47.439926 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11860 19:24:47.443007 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11861 19:24:47.446271 # ok 1 bti_c_func/call_using_blr # SKIP
11862 19:24:47.449598 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11863 19:24:47.453066 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11864 19:24:47.456055 # ok 1 bti_j_func/call_using_blr # SKIP
11865 19:24:47.459659 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11866 19:24:47.466185 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11867 19:24:47.469349 # ok 1 bti_jc_func/call_using_blr # SKIP
11868 19:24:47.472999 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11869 19:24:47.476088 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11870 19:24:47.479435 # ok 1 paciasp_func/call_using_blr # SKIP
11871 19:24:47.486213 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11872 19:24:47.489191 # # WARNING - EXPECTED TEST COUNT WRONG
11873 19:24:47.492669 ok 43 selftests: arm64: btitest
11874 19:24:47.492765 # selftests: arm64: nobtitest
11875 19:24:47.506649 # TAP version 13
11876 19:24:47.506799 # 1..18
11877 19:24:47.510354 # # HWCAP_PACA not present
11878 19:24:47.513508 # # HWCAP2_BTI not present
11879 19:24:47.516848 # # Test binary not built for BTI
11880 19:24:47.520542 # ok 1 nohint_func/call_using_br_x0 # SKIP
11881 19:24:47.523562 # ok 1 nohint_func/call_using_br_x16 # SKIP
11882 19:24:47.526684 # ok 1 nohint_func/call_using_blr # SKIP
11883 19:24:47.530103 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11884 19:24:47.533314 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11885 19:24:47.539938 # ok 1 bti_none_func/call_using_blr # SKIP
11886 19:24:47.543508 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11887 19:24:47.546682 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11888 19:24:47.549798 # ok 1 bti_c_func/call_using_blr # SKIP
11889 19:24:47.553106 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11890 19:24:47.556721 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11891 19:24:47.559762 # ok 1 bti_j_func/call_using_blr # SKIP
11892 19:24:47.562982 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11893 19:24:47.569996 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11894 19:24:47.572798 # ok 1 bti_jc_func/call_using_blr # SKIP
11895 19:24:47.576599 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11896 19:24:47.579644 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11897 19:24:47.582756 # ok 1 paciasp_func/call_using_blr # SKIP
11898 19:24:47.589701 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11899 19:24:47.593002 # # WARNING - EXPECTED TEST COUNT WRONG
11900 19:24:47.596230 ok 44 selftests: arm64: nobtitest
11901 19:24:47.599673 # selftests: arm64: hwcap
11902 19:24:47.599784 # TAP version 13
11903 19:24:47.599867 # 1..28
11904 19:24:47.602601 # ok 1 cpuinfo_match_RNG
11905 19:24:47.606206 # # SIGILL reported for RNG
11906 19:24:47.606302 # ok 2 # SKIP sigill_RNG
11907 19:24:47.609224 # ok 3 cpuinfo_match_SME
11908 19:24:47.612579 # ok 4 sigill_SME
11909 19:24:47.612672 # ok 5 cpuinfo_match_SVE
11910 19:24:47.615822 # ok 6 sigill_SVE
11911 19:24:47.615940 # ok 7 cpuinfo_match_SVE 2
11912 19:24:47.619197 # # SIGILL reported for SVE 2
11913 19:24:47.623032 # ok 8 # SKIP sigill_SVE 2
11914 19:24:47.626257 # ok 9 cpuinfo_match_SVE AES
11915 19:24:47.629153 # # SIGILL reported for SVE AES
11916 19:24:47.629331 # ok 10 # SKIP sigill_SVE AES
11917 19:24:47.632611 # ok 11 cpuinfo_match_SVE2 PMULL
11918 19:24:47.635737 # # SIGILL reported for SVE2 PMULL
11919 19:24:47.639307 # ok 12 # SKIP sigill_SVE2 PMULL
11920 19:24:47.642495 # ok 13 cpuinfo_match_SVE2 BITPERM
11921 19:24:47.645857 # # SIGILL reported for SVE2 BITPERM
11922 19:24:47.649403 # ok 14 # SKIP sigill_SVE2 BITPERM
11923 19:24:47.652583 # ok 15 cpuinfo_match_SVE2 SHA3
11924 19:24:47.655690 # # SIGILL reported for SVE2 SHA3
11925 19:24:47.659147 # ok 16 # SKIP sigill_SVE2 SHA3
11926 19:24:47.662544 # ok 17 cpuinfo_match_SVE2 SM4
11927 19:24:47.662647 # # SIGILL reported for SVE2 SM4
11928 19:24:47.666023 # ok 18 # SKIP sigill_SVE2 SM4
11929 19:24:47.669004 # ok 19 cpuinfo_match_SVE2 I8MM
11930 19:24:47.672482 # # SIGILL reported for SVE2 I8MM
11931 19:24:47.676056 # ok 20 # SKIP sigill_SVE2 I8MM
11932 19:24:47.678978 # ok 21 cpuinfo_match_SVE2 F32MM
11933 19:24:47.682644 # # SIGILL reported for SVE2 F32MM
11934 19:24:47.685875 # ok 22 # SKIP sigill_SVE2 F32MM
11935 19:24:47.689089 # ok 23 cpuinfo_match_SVE2 F64MM
11936 19:24:47.689228 # # SIGILL reported for SVE2 F64MM
11937 19:24:47.692519 # ok 24 # SKIP sigill_SVE2 F64MM
11938 19:24:47.695592 # ok 25 cpuinfo_match_SVE2 BF16
11939 19:24:47.699520 # # SIGILL reported for SVE2 BF16
11940 19:24:47.702338 # ok 26 # SKIP sigill_SVE2 BF16
11941 19:24:47.705269 # ok 27 cpuinfo_match_SVE2 EBF16
11942 19:24:47.708832 # ok 28 # SKIP sigill_SVE2 EBF16
11943 19:24:47.712044 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:12 error:0
11944 19:24:47.715591 ok 45 selftests: arm64: hwcap
11945 19:24:47.719109 # selftests: arm64: ptrace
11946 19:24:47.719220 # TAP version 13
11947 19:24:47.721925 # 1..7
11948 19:24:47.725551 # # Parent is 1500, child is 1501
11949 19:24:47.725645 # ok 1 read_tpidr_one
11950 19:24:47.729003 # ok 2 write_tpidr_one
11951 19:24:47.729090 # ok 3 verify_tpidr_one
11952 19:24:47.732350 # ok 4 count_tpidrs
11953 19:24:47.732436 # ok 5 tpidr2_write
11954 19:24:47.735857 # ok 6 tpidr2_read
11955 19:24:47.738765 # ok 7 write_tpidr_only
11956 19:24:47.741909 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
11957 19:24:47.745554 ok 46 selftests: arm64: ptrace
11958 19:24:47.748555 # selftests: arm64: syscall-abi
11959 19:24:47.758785 # TAP version 13
11960 19:24:47.758930 # 1..2
11961 19:24:47.762001 # ok 1 getpid() FPSIMD
11962 19:24:47.765137 # ok 2 sched_yield() FPSIMD
11963 19:24:47.768830 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0
11964 19:24:47.771754 ok 47 selftests: arm64: syscall-abi
11965 19:24:47.777159 # selftests: arm64: tpidr2
11966 19:24:47.843388 # TAP version 13
11967 19:24:47.843548 # 1..5
11968 19:24:47.846770 # # PID: 1537
11969 19:24:47.846861 # # SME support not present
11970 19:24:47.849567 # ok 0 skipped, TPIDR2 not supported
11971 19:24:47.853106 # ok 1 skipped, TPIDR2 not supported
11972 19:24:47.856182 # ok 2 skipped, TPIDR2 not supported
11973 19:24:47.859698 # ok 3 skipped, TPIDR2 not supported
11974 19:24:47.862947 # ok 4 skipped, TPIDR2 not supported
11975 19:24:47.869693 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
11976 19:24:47.872604 ok 48 selftests: arm64: tpidr2
11977 19:24:49.392833 arm64_tags_test pass
11978 19:24:49.396441 arm64_run_tags_test_sh pass
11979 19:24:49.399266 arm64_fake_sigreturn_bad_magic pass
11980 19:24:49.402914 arm64_fake_sigreturn_bad_size pass
11981 19:24:49.405965 arm64_fake_sigreturn_bad_size_for_magic0 pass
11982 19:24:49.409608 arm64_fake_sigreturn_duplicated_fpsimd pass
11983 19:24:49.413088 arm64_fake_sigreturn_misaligned_sp pass
11984 19:24:49.416303 arm64_fake_sigreturn_missing_fpsimd pass
11985 19:24:49.419448 arm64_fake_sigreturn_sme_change_vl skip
11986 19:24:49.422926 arm64_fake_sigreturn_sve_change_vl skip
11987 19:24:49.429391 arm64_mangle_pstate_invalid_compat_toggle pass
11988 19:24:49.432487 arm64_mangle_pstate_invalid_daif_bits pass
11989 19:24:49.436093 arm64_mangle_pstate_invalid_mode_el1h pass
11990 19:24:49.439391 arm64_mangle_pstate_invalid_mode_el1t pass
11991 19:24:49.442825 arm64_mangle_pstate_invalid_mode_el2h pass
11992 19:24:49.446156 arm64_mangle_pstate_invalid_mode_el2t pass
11993 19:24:49.452611 arm64_mangle_pstate_invalid_mode_el3h pass
11994 19:24:49.455674 arm64_mangle_pstate_invalid_mode_el3t pass
11995 19:24:49.459177 arm64_sme_trap_no_sm skip
11996 19:24:49.459265 arm64_sme_trap_non_streaming skip
11997 19:24:49.462485 arm64_sme_trap_za pass
11998 19:24:49.465894 arm64_sme_vl skip
11999 19:24:49.465976 arm64_ssve_regs skip
12000 19:24:49.468871 arm64_sve_regs skip
12001 19:24:49.468952 arm64_sve_vl skip
12002 19:24:49.472512 arm64_za_no_regs skip
12003 19:24:49.472595 arm64_za_regs skip
12004 19:24:49.475667 arm64_pac_PAUTH_not_enabled skip
12005 19:24:49.478856 arm64_pac_PAUTH_not_enabled_dup2 skip
12006 19:24:49.482434 arm64_pac_Generic_PAUTH_not_enabled skip
12007 19:24:49.485630 arm64_pac_PAUTH_not_enabled_dup3 skip
12008 19:24:49.488742 arm64_pac_PAUTH_not_enabled_dup4 skip
12009 19:24:49.492170 arm64_pac_PAUTH_not_enabled_dup5 skip
12010 19:24:49.499077 arm64_pac_Generic_PAUTH_not_enabled_dup2 skip
12011 19:24:49.499159 arm64_pac pass
12012 19:24:49.502621 arm64_fp-stress_FPSIMD-0-0 pass
12013 19:24:49.505787 arm64_fp-stress_FPSIMD-0-1 pass
12014 19:24:49.508845 arm64_fp-stress_FPSIMD-1-0 pass
12015 19:24:49.508926 arm64_fp-stress_FPSIMD-1-1 pass
12016 19:24:49.512470 arm64_fp-stress_FPSIMD-2-0 pass
12017 19:24:49.515352 arm64_fp-stress_FPSIMD-2-1 pass
12018 19:24:49.518749 arm64_fp-stress_FPSIMD-3-0 pass
12019 19:24:49.522378 arm64_fp-stress_FPSIMD-3-1 pass
12020 19:24:49.525364 arm64_fp-stress_FPSIMD-4-0 pass
12021 19:24:49.528855 arm64_fp-stress_FPSIMD-4-1 pass
12022 19:24:49.531817 arm64_fp-stress_FPSIMD-5-0 pass
12023 19:24:49.531900 arm64_fp-stress_FPSIMD-5-1 pass
12024 19:24:49.535369 arm64_fp-stress_FPSIMD-6-0 pass
12025 19:24:49.538972 arm64_fp-stress_FPSIMD-6-1 pass
12026 19:24:49.541939 arm64_fp-stress_FPSIMD-7-0 pass
12027 19:24:49.545138 arm64_fp-stress_FPSIMD-7-1 pass
12028 19:24:49.545225 arm64_fp-stress pass
12029 19:24:49.552196 arm64_sve-ptrace_SVE_not_available skip
12030 19:24:49.552278 arm64_sve-ptrace skip
12031 19:24:49.555325 arm64_sve-probe-vls_SVE_not_available skip
12032 19:24:49.558827 arm64_sve-probe-vls skip
12033 19:24:49.561815 arm64_vec-syscfg_SVE_not_supported skip
12034 19:24:49.565161 arm64_vec-syscfg_SVE_not_supported_dup2 skip
12035 19:24:49.569150 arm64_vec-syscfg_SVE_not_supported_dup3 skip
12036 19:24:49.574870 arm64_vec-syscfg_SVE_not_supported_dup4 skip
12037 19:24:49.578511 arm64_vec-syscfg_SVE_not_supported_dup5 skip
12038 19:24:49.581573 arm64_vec-syscfg_SVE_not_supported_dup6 skip
12039 19:24:49.585391 arm64_vec-syscfg_SVE_not_supported_dup7 skip
12040 19:24:49.588696 arm64_vec-syscfg_SVE_not_supported_dup8 skip
12041 19:24:49.594800 arm64_vec-syscfg_SVE_not_supported_dup9 skip
12042 19:24:49.598345 arm64_vec-syscfg_SVE_not_supported_dup10 skip
12043 19:24:49.601666 arm64_vec-syscfg_SME_not_supported skip
12044 19:24:49.604843 arm64_vec-syscfg_SME_not_supported_dup2 skip
12045 19:24:49.607904 arm64_vec-syscfg_SME_not_supported_dup3 skip
12046 19:24:49.615073 arm64_vec-syscfg_SME_not_supported_dup4 skip
12047 19:24:49.618174 arm64_vec-syscfg_SME_not_supported_dup5 skip
12048 19:24:49.621743 arm64_vec-syscfg_SME_not_supported_dup6 skip
12049 19:24:49.624593 arm64_vec-syscfg_SME_not_supported_dup7 skip
12050 19:24:49.628108 arm64_vec-syscfg_SME_not_supported_dup8 skip
12051 19:24:49.634735 arm64_vec-syscfg_SME_not_supported_dup9 skip
12052 19:24:49.637738 arm64_vec-syscfg_SME_not_supported_dup10 skip
12053 19:24:49.637820 arm64_vec-syscfg pass
12054 19:24:49.641400 arm64_za-fork_skipped pass
12055 19:24:49.644396 arm64_za-fork pass
12056 19:24:49.648134 arm64_za-ptrace_SME_not_available skip
12057 19:24:49.648216 arm64_za-ptrace skip
12058 19:24:49.651003 arm64_check_buffer_fill skip
12059 19:24:49.654521 arm64_check_child_memory skip
12060 19:24:49.658153 arm64_check_gcr_el1_cswitch skip
12061 19:24:49.660985 arm64_check_ksm_options skip
12062 19:24:49.661067 arm64_check_mmap_options skip
12063 19:24:49.667630 arm64_check_prctl_check_basic_read pass
12064 19:24:49.667712 arm64_check_prctl_NONE pass
12065 19:24:49.671052 arm64_check_prctl_SYNC skip
12066 19:24:49.674122 arm64_check_prctl_ASYNC skip
12067 19:24:49.677658 arm64_check_prctl_SYNC_ASYNC skip
12068 19:24:49.677740 arm64_check_prctl pass
12069 19:24:49.680928 arm64_check_tags_inclusion skip
12070 19:24:49.684493 arm64_check_user_mem skip
12071 19:24:49.687398 arm64_btitest_nohint_func_call_using_br_x0 skip
12072 19:24:49.694031 arm64_btitest_nohint_func_call_using_br_x16 skip
12073 19:24:49.697382 arm64_btitest_nohint_func_call_using_blr skip
12074 19:24:49.700991 arm64_btitest_bti_none_func_call_using_br_x0 skip
12075 19:24:49.704299 arm64_btitest_bti_none_func_call_using_br_x16 skip
12076 19:24:49.710758 arm64_btitest_bti_none_func_call_using_blr skip
12077 19:24:49.713927 arm64_btitest_bti_c_func_call_using_br_x0 skip
12078 19:24:49.717116 arm64_btitest_bti_c_func_call_using_br_x16 skip
12079 19:24:49.724031 arm64_btitest_bti_c_func_call_using_blr skip
12080 19:24:49.727405 arm64_btitest_bti_j_func_call_using_br_x0 skip
12081 19:24:49.730658 arm64_btitest_bti_j_func_call_using_br_x16 skip
12082 19:24:49.734119 arm64_btitest_bti_j_func_call_using_blr skip
12083 19:24:49.740524 arm64_btitest_bti_jc_func_call_using_br_x0 skip
12084 19:24:49.744202 arm64_btitest_bti_jc_func_call_using_br_x16 skip
12085 19:24:49.747071 arm64_btitest_bti_jc_func_call_using_blr skip
12086 19:24:49.750354 arm64_btitest_paciasp_func_call_using_br_x0 skip
12087 19:24:49.757081 arm64_btitest_paciasp_func_call_using_br_x16 skip
12088 19:24:49.760156 arm64_btitest_paciasp_func_call_using_blr skip
12089 19:24:49.763577 arm64_btitest pass
12090 19:24:49.766857 arm64_nobtitest_nohint_func_call_using_br_x0 skip
12091 19:24:49.770457 arm64_nobtitest_nohint_func_call_using_br_x16 skip
12092 19:24:49.776869 arm64_nobtitest_nohint_func_call_using_blr skip
12093 19:24:49.780224 arm64_nobtitest_bti_none_func_call_using_br_x0 skip
12094 19:24:49.783621 arm64_nobtitest_bti_none_func_call_using_br_x16 skip
12095 19:24:49.790513 arm64_nobtitest_bti_none_func_call_using_blr skip
12096 19:24:49.793581 arm64_nobtitest_bti_c_func_call_using_br_x0 skip
12097 19:24:49.796749 arm64_nobtitest_bti_c_func_call_using_br_x16 skip
12098 19:24:49.803527 arm64_nobtitest_bti_c_func_call_using_blr skip
12099 19:24:49.807077 arm64_nobtitest_bti_j_func_call_using_br_x0 skip
12100 19:24:49.810109 arm64_nobtitest_bti_j_func_call_using_br_x16 skip
12101 19:24:49.813501 arm64_nobtitest_bti_j_func_call_using_blr skip
12102 19:24:49.820102 arm64_nobtitest_bti_jc_func_call_using_br_x0 skip
12103 19:24:49.823350 arm64_nobtitest_bti_jc_func_call_using_br_x16 skip
12104 19:24:49.826752 arm64_nobtitest_bti_jc_func_call_using_blr skip
12105 19:24:49.833724 arm64_nobtitest_paciasp_func_call_using_br_x0 skip
12106 19:24:49.836751 arm64_nobtitest_paciasp_func_call_using_br_x16 skip
12107 19:24:49.839939 arm64_nobtitest_paciasp_func_call_using_blr skip
12108 19:24:49.843565 arm64_nobtitest pass
12109 19:24:49.846527 arm64_hwcap_cpuinfo_match_RNG pass
12110 19:24:49.849934 arm64_hwcap_sigill_RNG skip
12111 19:24:49.853507 arm64_hwcap_cpuinfo_match_SME pass
12112 19:24:49.853590 arm64_hwcap_sigill_SME pass
12113 19:24:49.856941 arm64_hwcap_cpuinfo_match_SVE pass
12114 19:24:49.859804 arm64_hwcap_sigill_SVE pass
12115 19:24:49.863366 arm64_hwcap_cpuinfo_match_SVE_2 pass
12116 19:24:49.866825 arm64_hwcap_sigill_SVE_2 skip
12117 19:24:49.870301 arm64_hwcap_cpuinfo_match_SVE_AES pass
12118 19:24:49.873197 arm64_hwcap_sigill_SVE_AES skip
12119 19:24:49.876170 arm64_hwcap_cpuinfo_match_SVE2_PMULL pass
12120 19:24:49.879652 arm64_hwcap_sigill_SVE2_PMULL skip
12121 19:24:49.882812 arm64_hwcap_cpuinfo_match_SVE2_BITPERM pass
12122 19:24:49.886272 arm64_hwcap_sigill_SVE2_BITPERM skip
12123 19:24:49.889525 arm64_hwcap_cpuinfo_match_SVE2_SHA3 pass
12124 19:24:49.893064 arm64_hwcap_sigill_SVE2_SHA3 skip
12125 19:24:49.896188 arm64_hwcap_cpuinfo_match_SVE2_SM4 pass
12126 19:24:49.899627 arm64_hwcap_sigill_SVE2_SM4 skip
12127 19:24:49.903150 arm64_hwcap_cpuinfo_match_SVE2_I8MM pass
12128 19:24:49.906196 arm64_hwcap_sigill_SVE2_I8MM skip
12129 19:24:49.909718 arm64_hwcap_cpuinfo_match_SVE2_F32MM pass
12130 19:24:49.912654 arm64_hwcap_sigill_SVE2_F32MM skip
12131 19:24:49.916067 arm64_hwcap_cpuinfo_match_SVE2_F64MM pass
12132 19:24:49.919800 arm64_hwcap_sigill_SVE2_F64MM skip
12133 19:24:49.922611 arm64_hwcap_cpuinfo_match_SVE2_BF16 pass
12134 19:24:49.926328 arm64_hwcap_sigill_SVE2_BF16 skip
12135 19:24:49.929483 arm64_hwcap_cpuinfo_match_SVE2_EBF16 pass
12136 19:24:49.933171 arm64_hwcap_sigill_SVE2_EBF16 skip
12137 19:24:49.936128 arm64_hwcap pass
12138 19:24:49.939454 arm64_ptrace_read_tpidr_one pass
12139 19:24:49.942587 arm64_ptrace_write_tpidr_one pass
12140 19:24:49.946182 arm64_ptrace_verify_tpidr_one pass
12141 19:24:49.946265 arm64_ptrace_count_tpidrs pass
12142 19:24:49.949773 arm64_ptrace_tpidr2_write pass
12143 19:24:49.953129 arm64_ptrace_tpidr2_read pass
12144 19:24:49.955973 arm64_ptrace_write_tpidr_only pass
12145 19:24:49.956056 arm64_ptrace pass
12146 19:24:49.959474 arm64_syscall-abi_getpid_FPSIMD pass
12147 19:24:49.965979 arm64_syscall-abi_sched_yield_FPSIMD pass
12148 19:24:49.966079 arm64_syscall-abi pass
12149 19:24:49.969614 arm64_tpidr2_skipped_TPIDR2_not_supported pass
12150 19:24:49.975991 arm64_tpidr2_skipped_TPIDR2_not_supported_dup2 pass
12151 19:24:49.979417 arm64_tpidr2_skipped_TPIDR2_not_supported_dup3 pass
12152 19:24:49.986108 arm64_tpidr2_skipped_TPIDR2_not_supported_dup4 pass
12153 19:24:49.988989 arm64_tpidr2_skipped_TPIDR2_not_supported_dup5 pass
12154 19:24:49.992664 arm64_tpidr2 pass
12155 19:24:49.995632 + ../../utils/send-to-lava.sh ./output/result.txt
12156 19:24:50.002802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-arm64 RESULT=pass>
12157 19:24:50.003083 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-arm64 RESULT=pass
12159 19:24:50.005785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tags_test RESULT=pass>
12160 19:24:50.006039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tags_test RESULT=pass
12162 19:24:50.013010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass>
12163 19:24:50.013316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass
12165 19:24:50.019230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass>
12166 19:24:50.019487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass
12168 19:24:50.025571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass>
12169 19:24:50.025824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass
12171 19:24:50.085129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass>
12172 19:24:50.085445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass
12174 19:24:50.143168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass>
12175 19:24:50.143444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass
12177 19:24:50.196533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass>
12178 19:24:50.196811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass
12180 19:24:50.252753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass>
12181 19:24:50.253019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass
12183 19:24:50.306621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip>
12184 19:24:50.306890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip
12186 19:24:50.365604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip>
12187 19:24:50.365889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip
12189 19:24:50.423216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass>
12190 19:24:50.423526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass
12192 19:24:50.478524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass>
12193 19:24:50.478824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass
12195 19:24:50.531206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass>
12196 19:24:50.531480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass
12198 19:24:50.587389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass>
12199 19:24:50.587708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass
12201 19:24:50.643931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass>
12202 19:24:50.644203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass
12204 19:24:50.697887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass>
12205 19:24:50.698235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass
12207 19:24:50.754868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass>
12208 19:24:50.755138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass
12210 19:24:50.811577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass>
12211 19:24:50.811859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass
12213 19:24:50.862330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip>
12214 19:24:50.862597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip
12216 19:24:50.918675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip
12218 19:24:50.921450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip>
12219 19:24:50.974338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_za RESULT=pass>
12220 19:24:50.974633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_za RESULT=pass
12222 19:24:51.030355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_vl RESULT=skip>
12223 19:24:51.030629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_vl RESULT=skip
12225 19:24:51.084446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ssve_regs RESULT=skip>
12226 19:24:51.084731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ssve_regs RESULT=skip
12228 19:24:51.140569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_regs RESULT=skip>
12229 19:24:51.140844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_regs RESULT=skip
12231 19:24:51.192894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_vl RESULT=skip>
12232 19:24:51.193183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_vl RESULT=skip
12234 19:24:51.249478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_no_regs RESULT=skip>
12235 19:24:51.249744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_no_regs RESULT=skip
12237 19:24:51.308240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_regs RESULT=skip>
12238 19:24:51.308514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_regs RESULT=skip
12240 19:24:51.367112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12241 19:24:51.367388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12243 19:24:51.421888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup2 RESULT=skip>
12244 19:24:51.422160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup2 RESULT=skip
12246 19:24:51.477710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip>
12247 19:24:51.477976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip
12249 19:24:51.532658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup3 RESULT=skip>
12250 19:24:51.532929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup3 RESULT=skip
12252 19:24:51.580854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup4 RESULT=skip>
12253 19:24:51.581186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup4 RESULT=skip
12255 19:24:51.634338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup5 RESULT=skip>
12256 19:24:51.634612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup5 RESULT=skip
12258 19:24:51.684279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled_dup2 RESULT=skip>
12259 19:24:51.684546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled_dup2 RESULT=skip
12261 19:24:51.733849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac RESULT=pass>
12262 19:24:51.734113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac RESULT=pass
12264 19:24:51.787231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass>
12265 19:24:51.787512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass
12267 19:24:51.839843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass
12269 19:24:51.842832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass>
12270 19:24:51.897118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass>
12271 19:24:51.897452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass
12273 19:24:51.953868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass>
12274 19:24:51.954136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass
12276 19:24:52.014245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass>
12277 19:24:52.014521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass
12279 19:24:52.074420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass>
12280 19:24:52.074684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass
12282 19:24:52.132968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass>
12283 19:24:52.133247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass
12285 19:24:52.188310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass>
12286 19:24:52.188631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass
12288 19:24:52.239670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass>
12289 19:24:52.239991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass
12291 19:24:52.296813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass>
12292 19:24:52.297167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass
12294 19:24:52.356713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass>
12295 19:24:52.357033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass
12297 19:24:52.413488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass>
12298 19:24:52.413811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass
12300 19:24:52.472785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass>
12301 19:24:52.473112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass
12303 19:24:52.529605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass>
12304 19:24:52.529962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass
12306 19:24:52.584917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass>
12307 19:24:52.585256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass
12309 19:24:52.643112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass>
12310 19:24:52.643441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass
12312 19:24:52.697621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress RESULT=pass>
12313 19:24:52.697953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress RESULT=pass
12315 19:24:52.756263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip>
12316 19:24:52.756588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip
12318 19:24:52.812153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace RESULT=skip>
12319 19:24:52.812485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace RESULT=skip
12321 19:24:52.869548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip>
12322 19:24:52.869873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip
12324 19:24:52.926877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip>
12325 19:24:52.927213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip
12327 19:24:52.985703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12328 19:24:52.986030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12330 19:24:53.045097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup2 RESULT=skip>
12331 19:24:53.045469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup2 RESULT=skip
12333 19:24:53.102586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup3 RESULT=skip>
12334 19:24:53.102911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup3 RESULT=skip
12336 19:24:53.157151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup4 RESULT=skip>
12337 19:24:53.157521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup4 RESULT=skip
12339 19:24:53.221606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup5 RESULT=skip>
12340 19:24:53.221941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup5 RESULT=skip
12342 19:24:53.279308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup6 RESULT=skip>
12343 19:24:53.279639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup6 RESULT=skip
12345 19:24:53.342659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup7 RESULT=skip>
12346 19:24:53.343016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup7 RESULT=skip
12348 19:24:53.395625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup8 RESULT=skip>
12349 19:24:53.395959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup8 RESULT=skip
12351 19:24:53.459576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup9 RESULT=skip>
12352 19:24:53.459911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup9 RESULT=skip
12354 19:24:53.519485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup10 RESULT=skip>
12355 19:24:53.519830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup10 RESULT=skip
12357 19:24:53.576310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12358 19:24:53.576640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12360 19:24:53.630239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup2 RESULT=skip>
12361 19:24:53.630592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup2 RESULT=skip
12363 19:24:53.694528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup3 RESULT=skip>
12364 19:24:53.694858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup3 RESULT=skip
12366 19:24:53.746732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup4 RESULT=skip>
12367 19:24:53.747062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup4 RESULT=skip
12369 19:24:53.803406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup5 RESULT=skip>
12370 19:24:53.803737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup5 RESULT=skip
12372 19:24:53.859711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup6 RESULT=skip>
12373 19:24:53.860042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup6 RESULT=skip
12375 19:24:53.921568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup7 RESULT=skip>
12376 19:24:53.921897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup7 RESULT=skip
12378 19:24:53.979858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup8 RESULT=skip>
12379 19:24:53.980193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup8 RESULT=skip
12381 19:24:54.038017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup9 RESULT=skip>
12382 19:24:54.038338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup9 RESULT=skip
12384 19:24:54.093548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup10 RESULT=skip>
12385 19:24:54.093881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup10 RESULT=skip
12387 19:24:54.151522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg RESULT=pass>
12388 19:24:54.151849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg RESULT=pass
12390 19:24:54.203652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass>
12391 19:24:54.203984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass
12393 19:24:54.265456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork RESULT=pass>
12394 19:24:54.265786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork RESULT=pass
12396 19:24:54.329550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip>
12397 19:24:54.329879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip
12399 19:24:54.393018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace RESULT=skip>
12400 19:24:54.393347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace RESULT=skip
12402 19:24:54.447855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip>
12403 19:24:54.448185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip
12405 19:24:54.503534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory RESULT=skip>
12406 19:24:54.503860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory RESULT=skip
12408 19:24:54.563399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip
12410 19:24:54.566188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip>
12411 19:24:54.623964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_ksm_options RESULT=skip>
12412 19:24:54.624295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_ksm_options RESULT=skip
12414 19:24:54.686976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options RESULT=skip>
12415 19:24:54.687312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options RESULT=skip
12417 19:24:54.742689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass>
12418 19:24:54.743019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass
12420 19:24:54.792261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass>
12421 19:24:54.792618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass
12423 19:24:54.852777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip>
12424 19:24:54.853110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip
12426 19:24:54.911945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip>
12427 19:24:54.912270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip
12429 19:24:54.975966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip>
12430 19:24:54.976320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip
12432 19:24:55.028480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl RESULT=pass>
12433 19:24:55.028813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl RESULT=pass
12435 19:24:55.090545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip>
12436 19:24:55.090872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip
12438 19:24:55.146974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem RESULT=skip>
12439 19:24:55.147300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem RESULT=skip
12441 19:24:55.213456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip>
12442 19:24:55.213789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip
12444 19:24:55.266708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip>
12445 19:24:55.267039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip
12447 19:24:55.319463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip>
12448 19:24:55.319782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip
12450 19:24:55.372782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip>
12451 19:24:55.373101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip
12453 19:24:55.427629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip>
12454 19:24:55.427944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip
12456 19:24:55.484654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip>
12457 19:24:55.484966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip
12459 19:24:55.542357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip>
12460 19:24:55.542692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip
12462 19:24:55.602311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip>
12463 19:24:55.602673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip
12465 19:24:55.656337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip>
12466 19:24:55.656663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip
12468 19:24:55.713142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip>
12469 19:24:55.713530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip
12471 19:24:55.777897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip>
12472 19:24:55.778245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip
12474 19:24:55.838021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip>
12475 19:24:55.838349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip
12477 19:24:55.898401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12478 19:24:55.898739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip
12480 19:24:55.957006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12481 19:24:55.957339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip
12483 19:24:56.014576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip>
12484 19:24:56.014908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip
12486 19:24:56.071653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip>
12487 19:24:56.072010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip
12489 19:24:56.131660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip>
12490 19:24:56.132015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip
12492 19:24:56.195938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip>
12493 19:24:56.196296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip
12495 19:24:56.255433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest RESULT=pass>
12496 19:24:56.255763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest RESULT=pass
12498 19:24:56.318448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip>
12499 19:24:56.318810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip
12501 19:24:56.380990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip>
12502 19:24:56.381347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip
12504 19:24:56.439895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip>
12505 19:24:56.440244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip
12507 19:24:56.495302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip>
12508 19:24:56.495626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip
12510 19:24:56.552093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip>
12511 19:24:56.552461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip
12513 19:24:56.609081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip>
12514 19:24:56.609455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip
12516 19:24:56.661124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip>
12517 19:24:56.661458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip
12519 19:24:56.719635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip>
12520 19:24:56.719965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip
12522 19:24:56.774464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip>
12523 19:24:56.774799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip
12525 19:24:56.830165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip>
12526 19:24:56.830513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip
12528 19:24:56.880764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip>
12529 19:24:56.881078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip
12531 19:24:56.945453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip>
12532 19:24:56.945771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip
12534 19:24:57.008021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12535 19:24:57.008355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip
12537 19:24:57.062933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12538 19:24:57.063266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip
12540 19:24:57.124748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip>
12541 19:24:57.125078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip
12543 19:24:57.186147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip>
12544 19:24:57.186481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip
12546 19:24:57.238504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip>
12547 19:24:57.238821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip
12549 19:24:57.296977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip>
12550 19:24:57.297292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip
12552 19:24:57.349794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest RESULT=pass>
12553 19:24:57.350119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest RESULT=pass
12555 19:24:57.414831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass>
12556 19:24:57.415144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass
12558 19:24:57.468429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip>
12559 19:24:57.468742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip
12561 19:24:57.532754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass>
12562 19:24:57.533096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass
12564 19:24:57.583418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass>
12565 19:24:57.583741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass
12567 19:24:57.648733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass>
12568 19:24:57.649043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass
12570 19:24:57.699904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass>
12571 19:24:57.700216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass
12573 19:24:57.757716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass>
12574 19:24:57.758027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass
12576 19:24:57.809983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip>
12577 19:24:57.810322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip
12579 19:24:57.872426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass>
12580 19:24:57.872764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass
12582 19:24:57.928979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip>
12583 19:24:57.929329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip
12585 19:24:57.991199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass>
12586 19:24:57.991519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass
12588 19:24:58.045061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip
12590 19:24:58.048329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip>
12591 19:24:58.106005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass>
12592 19:24:58.106342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass
12594 19:24:58.162707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip>
12595 19:24:58.163016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip
12597 19:24:58.218375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass>
12598 19:24:58.218691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass
12600 19:24:58.281647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip
12602 19:24:58.284247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip>
12603 19:24:58.348818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass>
12604 19:24:58.349140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass
12606 19:24:58.402375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip>
12607 19:24:58.402686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip
12609 19:24:58.471138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass>
12610 19:24:58.471484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass
12612 19:24:58.521376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip
12614 19:24:58.524364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip>
12615 19:24:58.581398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass>
12616 19:24:58.581712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass
12618 19:24:58.636136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip>
12619 19:24:58.636452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip
12621 19:24:58.695733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass>
12622 19:24:58.696074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass
12624 19:24:58.756683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip>
12625 19:24:58.757022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip
12627 19:24:58.811749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass>
12628 19:24:58.812112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass
12630 19:24:58.860982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip>
12631 19:24:58.861307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip
12633 19:24:58.925012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass>
12634 19:24:58.925353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass
12636 19:24:58.984843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip>
12637 19:24:58.985185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip
12639 19:24:59.037146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap RESULT=pass>
12640 19:24:59.037490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap RESULT=pass
12642 19:24:59.095840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass>
12643 19:24:59.096174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass
12645 19:24:59.157130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass
12647 19:24:59.160630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass>
12648 19:24:59.216093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass>
12649 19:24:59.216416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass
12651 19:24:59.268800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass>
12652 19:24:59.269101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass
12654 19:24:59.323908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass>
12655 19:24:59.324242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass
12657 19:24:59.380240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass>
12658 19:24:59.380565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass
12660 19:24:59.439628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass>
12661 19:24:59.439949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass
12663 19:24:59.493061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace RESULT=pass>
12664 19:24:59.493365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace RESULT=pass
12666 19:24:59.552810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass>
12667 19:24:59.553118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass
12669 19:24:59.607035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass>
12670 19:24:59.607338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass
12672 19:24:59.665428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi RESULT=pass>
12673 19:24:59.665762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi RESULT=pass
12675 19:24:59.721938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12676 19:24:59.722248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12678 19:24:59.781079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup2 RESULT=pass>
12679 19:24:59.781388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup2 RESULT=pass
12681 19:24:59.839475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup3 RESULT=pass>
12682 19:24:59.839786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup3 RESULT=pass
12684 19:24:59.900896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup4 RESULT=pass>
12685 19:24:59.901215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup4 RESULT=pass
12687 19:24:59.959920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup5 RESULT=pass>
12688 19:24:59.960236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup5 RESULT=pass
12690 19:25:00.012495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2 RESULT=pass>
12691 19:25:00.012651 + set +x
12692 19:25:00.012928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2 RESULT=pass
12694 19:25:00.018917 <LAVA_SIGNAL_ENDRUN 1_kselftest-arm64 13420348_1.6.2.3.5>
12695 19:25:00.019203 Received signal: <ENDRUN> 1_kselftest-arm64 13420348_1.6.2.3.5
12696 19:25:00.019282 Ending use of test pattern.
12697 19:25:00.019346 Ending test lava.1_kselftest-arm64 (13420348_1.6.2.3.5), duration 34.08
12699 19:25:00.022284 <LAVA_TEST_RUNNER EXIT>
12700 19:25:00.022541 ok: lava_test_shell seems to have completed
12701 19:25:00.023765 arm64_btitest: pass
arm64_btitest_bti_c_func_call_using_blr: skip
arm64_btitest_bti_c_func_call_using_br_x0: skip
arm64_btitest_bti_c_func_call_using_br_x16: skip
arm64_btitest_bti_j_func_call_using_blr: skip
arm64_btitest_bti_j_func_call_using_br_x0: skip
arm64_btitest_bti_j_func_call_using_br_x16: skip
arm64_btitest_bti_jc_func_call_using_blr: skip
arm64_btitest_bti_jc_func_call_using_br_x0: skip
arm64_btitest_bti_jc_func_call_using_br_x16: skip
arm64_btitest_bti_none_func_call_using_blr: skip
arm64_btitest_bti_none_func_call_using_br_x0: skip
arm64_btitest_bti_none_func_call_using_br_x16: skip
arm64_btitest_nohint_func_call_using_blr: skip
arm64_btitest_nohint_func_call_using_br_x0: skip
arm64_btitest_nohint_func_call_using_br_x16: skip
arm64_btitest_paciasp_func_call_using_blr: skip
arm64_btitest_paciasp_func_call_using_br_x0: skip
arm64_btitest_paciasp_func_call_using_br_x16: skip
arm64_check_buffer_fill: skip
arm64_check_child_memory: skip
arm64_check_gcr_el1_cswitch: skip
arm64_check_ksm_options: skip
arm64_check_mmap_options: skip
arm64_check_prctl: pass
arm64_check_prctl_ASYNC: skip
arm64_check_prctl_NONE: pass
arm64_check_prctl_SYNC: skip
arm64_check_prctl_SYNC_ASYNC: skip
arm64_check_prctl_check_basic_read: pass
arm64_check_tags_inclusion: skip
arm64_check_user_mem: skip
arm64_fake_sigreturn_bad_magic: pass
arm64_fake_sigreturn_bad_size: pass
arm64_fake_sigreturn_bad_size_for_magic0: pass
arm64_fake_sigreturn_duplicated_fpsimd: pass
arm64_fake_sigreturn_misaligned_sp: pass
arm64_fake_sigreturn_missing_fpsimd: pass
arm64_fake_sigreturn_sme_change_vl: skip
arm64_fake_sigreturn_sve_change_vl: skip
arm64_fp-stress: pass
arm64_fp-stress_FPSIMD-0-0: pass
arm64_fp-stress_FPSIMD-0-1: pass
arm64_fp-stress_FPSIMD-1-0: pass
arm64_fp-stress_FPSIMD-1-1: pass
arm64_fp-stress_FPSIMD-2-0: pass
arm64_fp-stress_FPSIMD-2-1: pass
arm64_fp-stress_FPSIMD-3-0: pass
arm64_fp-stress_FPSIMD-3-1: pass
arm64_fp-stress_FPSIMD-4-0: pass
arm64_fp-stress_FPSIMD-4-1: pass
arm64_fp-stress_FPSIMD-5-0: pass
arm64_fp-stress_FPSIMD-5-1: pass
arm64_fp-stress_FPSIMD-6-0: pass
arm64_fp-stress_FPSIMD-6-1: pass
arm64_fp-stress_FPSIMD-7-0: pass
arm64_fp-stress_FPSIMD-7-1: pass
arm64_hwcap: pass
arm64_hwcap_cpuinfo_match_RNG: pass
arm64_hwcap_cpuinfo_match_SME: pass
arm64_hwcap_cpuinfo_match_SVE: pass
arm64_hwcap_cpuinfo_match_SVE2_BF16: pass
arm64_hwcap_cpuinfo_match_SVE2_BITPERM: pass
arm64_hwcap_cpuinfo_match_SVE2_EBF16: pass
arm64_hwcap_cpuinfo_match_SVE2_F32MM: pass
arm64_hwcap_cpuinfo_match_SVE2_F64MM: pass
arm64_hwcap_cpuinfo_match_SVE2_I8MM: pass
arm64_hwcap_cpuinfo_match_SVE2_PMULL: pass
arm64_hwcap_cpuinfo_match_SVE2_SHA3: pass
arm64_hwcap_cpuinfo_match_SVE2_SM4: pass
arm64_hwcap_cpuinfo_match_SVE_2: pass
arm64_hwcap_cpuinfo_match_SVE_AES: pass
arm64_hwcap_sigill_RNG: skip
arm64_hwcap_sigill_SME: pass
arm64_hwcap_sigill_SVE: pass
arm64_hwcap_sigill_SVE2_BF16: skip
arm64_hwcap_sigill_SVE2_BITPERM: skip
arm64_hwcap_sigill_SVE2_EBF16: skip
arm64_hwcap_sigill_SVE2_F32MM: skip
arm64_hwcap_sigill_SVE2_F64MM: skip
arm64_hwcap_sigill_SVE2_I8MM: skip
arm64_hwcap_sigill_SVE2_PMULL: skip
arm64_hwcap_sigill_SVE2_SHA3: skip
arm64_hwcap_sigill_SVE2_SM4: skip
arm64_hwcap_sigill_SVE_2: skip
arm64_hwcap_sigill_SVE_AES: skip
arm64_mangle_pstate_invalid_compat_toggle: pass
arm64_mangle_pstate_invalid_daif_bits: pass
arm64_mangle_pstate_invalid_mode_el1h: pass
arm64_mangle_pstate_invalid_mode_el1t: pass
arm64_mangle_pstate_invalid_mode_el2h: pass
arm64_mangle_pstate_invalid_mode_el2t: pass
arm64_mangle_pstate_invalid_mode_el3h: pass
arm64_mangle_pstate_invalid_mode_el3t: pass
arm64_nobtitest: pass
arm64_nobtitest_bti_c_func_call_using_blr: skip
arm64_nobtitest_bti_c_func_call_using_br_x0: skip
arm64_nobtitest_bti_c_func_call_using_br_x16: skip
arm64_nobtitest_bti_j_func_call_using_blr: skip
arm64_nobtitest_bti_j_func_call_using_br_x0: skip
arm64_nobtitest_bti_j_func_call_using_br_x16: skip
arm64_nobtitest_bti_jc_func_call_using_blr: skip
arm64_nobtitest_bti_jc_func_call_using_br_x0: skip
arm64_nobtitest_bti_jc_func_call_using_br_x16: skip
arm64_nobtitest_bti_none_func_call_using_blr: skip
arm64_nobtitest_bti_none_func_call_using_br_x0: skip
arm64_nobtitest_bti_none_func_call_using_br_x16: skip
arm64_nobtitest_nohint_func_call_using_blr: skip
arm64_nobtitest_nohint_func_call_using_br_x0: skip
arm64_nobtitest_nohint_func_call_using_br_x16: skip
arm64_nobtitest_paciasp_func_call_using_blr: skip
arm64_nobtitest_paciasp_func_call_using_br_x0: skip
arm64_nobtitest_paciasp_func_call_using_br_x16: skip
arm64_pac: pass
arm64_pac_Generic_PAUTH_not_enabled: skip
arm64_pac_Generic_PAUTH_not_enabled_dup2: skip
arm64_pac_PAUTH_not_enabled: skip
arm64_pac_PAUTH_not_enabled_dup2: skip
arm64_pac_PAUTH_not_enabled_dup3: skip
arm64_pac_PAUTH_not_enabled_dup4: skip
arm64_pac_PAUTH_not_enabled_dup5: skip
arm64_ptrace: pass
arm64_ptrace_count_tpidrs: pass
arm64_ptrace_read_tpidr_one: pass
arm64_ptrace_tpidr2_read: pass
arm64_ptrace_tpidr2_write: pass
arm64_ptrace_verify_tpidr_one: pass
arm64_ptrace_write_tpidr_one: pass
arm64_ptrace_write_tpidr_only: pass
arm64_run_tags_test_sh: pass
arm64_sme_trap_no_sm: skip
arm64_sme_trap_non_streaming: skip
arm64_sme_trap_za: pass
arm64_sme_vl: skip
arm64_ssve_regs: skip
arm64_sve-probe-vls: skip
arm64_sve-probe-vls_SVE_not_available: skip
arm64_sve-ptrace: skip
arm64_sve-ptrace_SVE_not_available: skip
arm64_sve_regs: skip
arm64_sve_vl: skip
arm64_syscall-abi: pass
arm64_syscall-abi_getpid_FPSIMD: pass
arm64_syscall-abi_sched_yield_FPSIMD: pass
arm64_tags_test: pass
arm64_tpidr2: pass
arm64_tpidr2_skipped_TPIDR2_not_supported: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup2: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup3: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup4: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup5: pass
arm64_vec-syscfg: pass
arm64_vec-syscfg_SME_not_supported: skip
arm64_vec-syscfg_SME_not_supported_dup10: skip
arm64_vec-syscfg_SME_not_supported_dup2: skip
arm64_vec-syscfg_SME_not_supported_dup3: skip
arm64_vec-syscfg_SME_not_supported_dup4: skip
arm64_vec-syscfg_SME_not_supported_dup5: skip
arm64_vec-syscfg_SME_not_supported_dup6: skip
arm64_vec-syscfg_SME_not_supported_dup7: skip
arm64_vec-syscfg_SME_not_supported_dup8: skip
arm64_vec-syscfg_SME_not_supported_dup9: skip
arm64_vec-syscfg_SVE_not_supported: skip
arm64_vec-syscfg_SVE_not_supported_dup10: skip
arm64_vec-syscfg_SVE_not_supported_dup2: skip
arm64_vec-syscfg_SVE_not_supported_dup3: skip
arm64_vec-syscfg_SVE_not_supported_dup4: skip
arm64_vec-syscfg_SVE_not_supported_dup5: skip
arm64_vec-syscfg_SVE_not_supported_dup6: skip
arm64_vec-syscfg_SVE_not_supported_dup7: skip
arm64_vec-syscfg_SVE_not_supported_dup8: skip
arm64_vec-syscfg_SVE_not_supported_dup9: skip
arm64_za-fork: pass
arm64_za-fork_skipped: pass
arm64_za-ptrace: skip
arm64_za-ptrace_SME_not_available: skip
arm64_za_no_regs: skip
arm64_za_regs: skip
shardfile-arm64: pass
12702 19:25:00.023926 end: 3.1 lava-test-shell (duration 00:00:35) [common]
12703 19:25:00.024018 end: 3 lava-test-retry (duration 00:00:35) [common]
12704 19:25:00.024109 start: 4 finalize (timeout 00:06:57) [common]
12705 19:25:00.024202 start: 4.1 power-off (timeout 00:00:30) [common]
12706 19:25:00.024359 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=off'
12707 19:25:00.102596 >> Command sent successfully.
12708 19:25:00.105144 Returned 0 in 0 seconds
12709 19:25:00.205607 end: 4.1 power-off (duration 00:00:00) [common]
12711 19:25:00.205931 start: 4.2 read-feedback (timeout 00:06:57) [common]
12712 19:25:00.206194 Listened to connection for namespace 'common' for up to 1s
12713 19:25:01.206180 Finalising connection for namespace 'common'
12714 19:25:01.206349 Disconnecting from shell: Finalise
12715 19:25:01.206431 / #
12716 19:25:01.306751 end: 4.2 read-feedback (duration 00:00:01) [common]
12717 19:25:01.306916 end: 4 finalize (duration 00:00:01) [common]
12718 19:25:01.307040 Cleaning after the job
12719 19:25:01.307143 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13420348/tftp-deploy-g80fdqkg/ramdisk
12720 19:25:01.309299 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13420348/tftp-deploy-g80fdqkg/kernel
12721 19:25:01.320386 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13420348/tftp-deploy-g80fdqkg/dtb
12722 19:25:01.320604 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13420348/tftp-deploy-g80fdqkg/nfsrootfs
12723 19:25:01.383423 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13420348/tftp-deploy-g80fdqkg/modules
12724 19:25:01.388888 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/13420348
12725 19:25:01.957325 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/13420348
12726 19:25:01.957488 Job finished correctly