Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 25
- Errors: 0
- Kernel Errors: 37
- Boot result: PASS
1 19:24:39.363998 lava-dispatcher, installed at version: 2024.01
2 19:24:39.364210 start: 0 validate
3 19:24:39.364339 Start time: 2024-04-18 19:24:39.364332+00:00 (UTC)
4 19:24:39.364464 Using caching service: 'http://localhost/cache/?uri=%s'
5 19:24:39.364594 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 19:24:39.631420 Using caching service: 'http://localhost/cache/?uri=%s'
7 19:24:39.631592 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 19:24:39.890145 Using caching service: 'http://localhost/cache/?uri=%s'
9 19:24:39.890313 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 19:24:40.148002 Using caching service: 'http://localhost/cache/?uri=%s'
11 19:24:40.148173 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 19:24:40.405855 Using caching service: 'http://localhost/cache/?uri=%s'
13 19:24:40.406039 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 19:24:40.673072 validate duration: 1.31
16 19:24:40.673335 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 19:24:40.673433 start: 1.1 download-retry (timeout 00:10:00) [common]
18 19:24:40.673522 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 19:24:40.673641 Not decompressing ramdisk as can be used compressed.
20 19:24:40.673734 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 19:24:40.673799 saving as /var/lib/lava/dispatcher/tmp/13420384/tftp-deploy-v1rk1d3v/ramdisk/initrd.cpio.gz
22 19:24:40.673868 total size: 5628169 (5 MB)
23 19:24:40.674949 progress 0 % (0 MB)
24 19:24:40.676523 progress 5 % (0 MB)
25 19:24:40.678168 progress 10 % (0 MB)
26 19:24:40.679590 progress 15 % (0 MB)
27 19:24:40.681189 progress 20 % (1 MB)
28 19:24:40.682631 progress 25 % (1 MB)
29 19:24:40.684216 progress 30 % (1 MB)
30 19:24:40.685784 progress 35 % (1 MB)
31 19:24:40.687207 progress 40 % (2 MB)
32 19:24:40.688789 progress 45 % (2 MB)
33 19:24:40.690179 progress 50 % (2 MB)
34 19:24:40.691747 progress 55 % (2 MB)
35 19:24:40.693370 progress 60 % (3 MB)
36 19:24:40.694770 progress 65 % (3 MB)
37 19:24:40.696393 progress 70 % (3 MB)
38 19:24:40.697784 progress 75 % (4 MB)
39 19:24:40.699328 progress 80 % (4 MB)
40 19:24:40.700725 progress 85 % (4 MB)
41 19:24:40.702303 progress 90 % (4 MB)
42 19:24:40.703856 progress 95 % (5 MB)
43 19:24:40.705285 progress 100 % (5 MB)
44 19:24:40.705497 5 MB downloaded in 0.03 s (169.71 MB/s)
45 19:24:40.705661 end: 1.1.1 http-download (duration 00:00:00) [common]
47 19:24:40.705920 end: 1.1 download-retry (duration 00:00:00) [common]
48 19:24:40.706009 start: 1.2 download-retry (timeout 00:10:00) [common]
49 19:24:40.706097 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 19:24:40.706238 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 19:24:40.706308 saving as /var/lib/lava/dispatcher/tmp/13420384/tftp-deploy-v1rk1d3v/kernel/Image
52 19:24:40.706374 total size: 54286848 (51 MB)
53 19:24:40.706436 No compression specified
54 19:24:40.707531 progress 0 % (0 MB)
55 19:24:40.721351 progress 5 % (2 MB)
56 19:24:40.735379 progress 10 % (5 MB)
57 19:24:40.749343 progress 15 % (7 MB)
58 19:24:40.763280 progress 20 % (10 MB)
59 19:24:40.777242 progress 25 % (12 MB)
60 19:24:40.791267 progress 30 % (15 MB)
61 19:24:40.805344 progress 35 % (18 MB)
62 19:24:40.819923 progress 40 % (20 MB)
63 19:24:40.834173 progress 45 % (23 MB)
64 19:24:40.848183 progress 50 % (25 MB)
65 19:24:40.862100 progress 55 % (28 MB)
66 19:24:40.876079 progress 60 % (31 MB)
67 19:24:40.889823 progress 65 % (33 MB)
68 19:24:40.903910 progress 70 % (36 MB)
69 19:24:40.917982 progress 75 % (38 MB)
70 19:24:40.931975 progress 80 % (41 MB)
71 19:24:40.946028 progress 85 % (44 MB)
72 19:24:40.959994 progress 90 % (46 MB)
73 19:24:40.973659 progress 95 % (49 MB)
74 19:24:40.987275 progress 100 % (51 MB)
75 19:24:40.987525 51 MB downloaded in 0.28 s (184.15 MB/s)
76 19:24:40.987684 end: 1.2.1 http-download (duration 00:00:00) [common]
78 19:24:40.987928 end: 1.2 download-retry (duration 00:00:00) [common]
79 19:24:40.988019 start: 1.3 download-retry (timeout 00:10:00) [common]
80 19:24:40.988109 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 19:24:40.988248 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 19:24:40.988319 saving as /var/lib/lava/dispatcher/tmp/13420384/tftp-deploy-v1rk1d3v/dtb/mt8192-asurada-spherion-r0.dtb
83 19:24:40.988382 total size: 47230 (0 MB)
84 19:24:40.988444 No compression specified
85 19:24:40.989559 progress 69 % (0 MB)
86 19:24:40.989834 progress 100 % (0 MB)
87 19:24:40.989991 0 MB downloaded in 0.00 s (28.03 MB/s)
88 19:24:40.990118 end: 1.3.1 http-download (duration 00:00:00) [common]
90 19:24:40.990344 end: 1.3 download-retry (duration 00:00:00) [common]
91 19:24:40.990431 start: 1.4 download-retry (timeout 00:10:00) [common]
92 19:24:40.990516 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 19:24:40.990631 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 19:24:40.990701 saving as /var/lib/lava/dispatcher/tmp/13420384/tftp-deploy-v1rk1d3v/nfsrootfs/full.rootfs.tar
95 19:24:40.990763 total size: 120894716 (115 MB)
96 19:24:40.990826 Using unxz to decompress xz
97 19:24:40.994834 progress 0 % (0 MB)
98 19:24:41.355891 progress 5 % (5 MB)
99 19:24:41.714919 progress 10 % (11 MB)
100 19:24:42.066884 progress 15 % (17 MB)
101 19:24:42.394879 progress 20 % (23 MB)
102 19:24:42.690530 progress 25 % (28 MB)
103 19:24:43.054356 progress 30 % (34 MB)
104 19:24:43.403355 progress 35 % (40 MB)
105 19:24:43.569388 progress 40 % (46 MB)
106 19:24:43.750757 progress 45 % (51 MB)
107 19:24:44.065269 progress 50 % (57 MB)
108 19:24:44.455382 progress 55 % (63 MB)
109 19:24:44.812280 progress 60 % (69 MB)
110 19:24:45.155915 progress 65 % (74 MB)
111 19:24:45.502390 progress 70 % (80 MB)
112 19:24:45.863820 progress 75 % (86 MB)
113 19:24:46.207296 progress 80 % (92 MB)
114 19:24:46.551389 progress 85 % (98 MB)
115 19:24:46.921511 progress 90 % (103 MB)
116 19:24:47.263217 progress 95 % (109 MB)
117 19:24:47.628402 progress 100 % (115 MB)
118 19:24:47.633832 115 MB downloaded in 6.64 s (17.36 MB/s)
119 19:24:47.634145 end: 1.4.1 http-download (duration 00:00:07) [common]
121 19:24:47.634551 end: 1.4 download-retry (duration 00:00:07) [common]
122 19:24:47.634672 start: 1.5 download-retry (timeout 00:09:53) [common]
123 19:24:47.634768 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 19:24:47.634927 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 19:24:47.635035 saving as /var/lib/lava/dispatcher/tmp/13420384/tftp-deploy-v1rk1d3v/modules/modules.tar
126 19:24:47.635144 total size: 8631416 (8 MB)
127 19:24:47.635240 Using unxz to decompress xz
128 19:24:47.639530 progress 0 % (0 MB)
129 19:24:47.658927 progress 5 % (0 MB)
130 19:24:47.683873 progress 10 % (0 MB)
131 19:24:47.708128 progress 15 % (1 MB)
132 19:24:47.731738 progress 20 % (1 MB)
133 19:24:47.756895 progress 25 % (2 MB)
134 19:24:47.783902 progress 30 % (2 MB)
135 19:24:47.808240 progress 35 % (2 MB)
136 19:24:47.834325 progress 40 % (3 MB)
137 19:24:47.858806 progress 45 % (3 MB)
138 19:24:47.884465 progress 50 % (4 MB)
139 19:24:47.909380 progress 55 % (4 MB)
140 19:24:47.937939 progress 60 % (4 MB)
141 19:24:47.963232 progress 65 % (5 MB)
142 19:24:47.988463 progress 70 % (5 MB)
143 19:24:48.012915 progress 75 % (6 MB)
144 19:24:48.038376 progress 80 % (6 MB)
145 19:24:48.064533 progress 85 % (7 MB)
146 19:24:48.093857 progress 90 % (7 MB)
147 19:24:48.123238 progress 95 % (7 MB)
148 19:24:48.149803 progress 100 % (8 MB)
149 19:24:48.155274 8 MB downloaded in 0.52 s (15.83 MB/s)
150 19:24:48.155614 end: 1.5.1 http-download (duration 00:00:01) [common]
152 19:24:48.156047 end: 1.5 download-retry (duration 00:00:01) [common]
153 19:24:48.156194 start: 1.6 prepare-tftp-overlay (timeout 00:09:53) [common]
154 19:24:48.156344 start: 1.6.1 extract-nfsrootfs (timeout 00:09:53) [common]
155 19:24:51.696347 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/13420384/extract-nfsrootfs-5njzje7g
156 19:24:51.696553 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 19:24:51.696655 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 19:24:51.696817 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/13420384/lava-overlay-zm07si8g
159 19:24:51.696945 makedir: /var/lib/lava/dispatcher/tmp/13420384/lava-overlay-zm07si8g/lava-13420384/bin
160 19:24:51.697044 makedir: /var/lib/lava/dispatcher/tmp/13420384/lava-overlay-zm07si8g/lava-13420384/tests
161 19:24:51.697141 makedir: /var/lib/lava/dispatcher/tmp/13420384/lava-overlay-zm07si8g/lava-13420384/results
162 19:24:51.697242 Creating /var/lib/lava/dispatcher/tmp/13420384/lava-overlay-zm07si8g/lava-13420384/bin/lava-add-keys
163 19:24:51.697386 Creating /var/lib/lava/dispatcher/tmp/13420384/lava-overlay-zm07si8g/lava-13420384/bin/lava-add-sources
164 19:24:51.697512 Creating /var/lib/lava/dispatcher/tmp/13420384/lava-overlay-zm07si8g/lava-13420384/bin/lava-background-process-start
165 19:24:51.697636 Creating /var/lib/lava/dispatcher/tmp/13420384/lava-overlay-zm07si8g/lava-13420384/bin/lava-background-process-stop
166 19:24:51.697758 Creating /var/lib/lava/dispatcher/tmp/13420384/lava-overlay-zm07si8g/lava-13420384/bin/lava-common-functions
167 19:24:51.697878 Creating /var/lib/lava/dispatcher/tmp/13420384/lava-overlay-zm07si8g/lava-13420384/bin/lava-echo-ipv4
168 19:24:51.697999 Creating /var/lib/lava/dispatcher/tmp/13420384/lava-overlay-zm07si8g/lava-13420384/bin/lava-install-packages
169 19:24:51.698118 Creating /var/lib/lava/dispatcher/tmp/13420384/lava-overlay-zm07si8g/lava-13420384/bin/lava-installed-packages
170 19:24:51.698237 Creating /var/lib/lava/dispatcher/tmp/13420384/lava-overlay-zm07si8g/lava-13420384/bin/lava-os-build
171 19:24:51.698358 Creating /var/lib/lava/dispatcher/tmp/13420384/lava-overlay-zm07si8g/lava-13420384/bin/lava-probe-channel
172 19:24:51.698479 Creating /var/lib/lava/dispatcher/tmp/13420384/lava-overlay-zm07si8g/lava-13420384/bin/lava-probe-ip
173 19:24:51.698599 Creating /var/lib/lava/dispatcher/tmp/13420384/lava-overlay-zm07si8g/lava-13420384/bin/lava-target-ip
174 19:24:51.698719 Creating /var/lib/lava/dispatcher/tmp/13420384/lava-overlay-zm07si8g/lava-13420384/bin/lava-target-mac
175 19:24:51.698841 Creating /var/lib/lava/dispatcher/tmp/13420384/lava-overlay-zm07si8g/lava-13420384/bin/lava-target-storage
176 19:24:51.698964 Creating /var/lib/lava/dispatcher/tmp/13420384/lava-overlay-zm07si8g/lava-13420384/bin/lava-test-case
177 19:24:51.699086 Creating /var/lib/lava/dispatcher/tmp/13420384/lava-overlay-zm07si8g/lava-13420384/bin/lava-test-event
178 19:24:51.699206 Creating /var/lib/lava/dispatcher/tmp/13420384/lava-overlay-zm07si8g/lava-13420384/bin/lava-test-feedback
179 19:24:51.699325 Creating /var/lib/lava/dispatcher/tmp/13420384/lava-overlay-zm07si8g/lava-13420384/bin/lava-test-raise
180 19:24:51.699445 Creating /var/lib/lava/dispatcher/tmp/13420384/lava-overlay-zm07si8g/lava-13420384/bin/lava-test-reference
181 19:24:51.699567 Creating /var/lib/lava/dispatcher/tmp/13420384/lava-overlay-zm07si8g/lava-13420384/bin/lava-test-runner
182 19:24:51.699687 Creating /var/lib/lava/dispatcher/tmp/13420384/lava-overlay-zm07si8g/lava-13420384/bin/lava-test-set
183 19:24:51.699806 Creating /var/lib/lava/dispatcher/tmp/13420384/lava-overlay-zm07si8g/lava-13420384/bin/lava-test-shell
184 19:24:51.699976 Updating /var/lib/lava/dispatcher/tmp/13420384/lava-overlay-zm07si8g/lava-13420384/bin/lava-add-keys (debian)
185 19:24:51.700121 Updating /var/lib/lava/dispatcher/tmp/13420384/lava-overlay-zm07si8g/lava-13420384/bin/lava-add-sources (debian)
186 19:24:51.700263 Updating /var/lib/lava/dispatcher/tmp/13420384/lava-overlay-zm07si8g/lava-13420384/bin/lava-install-packages (debian)
187 19:24:51.700399 Updating /var/lib/lava/dispatcher/tmp/13420384/lava-overlay-zm07si8g/lava-13420384/bin/lava-installed-packages (debian)
188 19:24:51.700536 Updating /var/lib/lava/dispatcher/tmp/13420384/lava-overlay-zm07si8g/lava-13420384/bin/lava-os-build (debian)
189 19:24:51.700653 Creating /var/lib/lava/dispatcher/tmp/13420384/lava-overlay-zm07si8g/lava-13420384/environment
190 19:24:51.700751 LAVA metadata
191 19:24:51.700819 - LAVA_JOB_ID=13420384
192 19:24:51.700882 - LAVA_DISPATCHER_IP=192.168.201.1
193 19:24:51.700982 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
194 19:24:51.701048 skipped lava-vland-overlay
195 19:24:51.701121 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 19:24:51.701199 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
197 19:24:51.701259 skipped lava-multinode-overlay
198 19:24:51.701329 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 19:24:51.701405 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
200 19:24:51.701477 Loading test definitions
201 19:24:51.701563 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
202 19:24:51.701632 Using /lava-13420384 at stage 0
203 19:24:51.701917 uuid=13420384_1.6.2.3.1 testdef=None
204 19:24:51.702004 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 19:24:51.702086 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
206 19:24:51.702531 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 19:24:51.702745 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
209 19:24:51.703289 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 19:24:51.703515 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
212 19:24:51.704366 runner path: /var/lib/lava/dispatcher/tmp/13420384/lava-overlay-zm07si8g/lava-13420384/0/tests/0_timesync-off test_uuid 13420384_1.6.2.3.1
213 19:24:51.704523 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 19:24:51.704744 start: 1.6.2.3.5 git-repo-action (timeout 00:09:49) [common]
216 19:24:51.704816 Using /lava-13420384 at stage 0
217 19:24:51.704911 Fetching tests from https://github.com/kernelci/test-definitions.git
218 19:24:51.704995 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/13420384/lava-overlay-zm07si8g/lava-13420384/0/tests/1_kselftest-dt'
219 19:24:54.488269 Running '/usr/bin/git checkout kernelci.org
220 19:24:54.634511 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/13420384/lava-overlay-zm07si8g/lava-13420384/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
221 19:24:54.635274 uuid=13420384_1.6.2.3.5 testdef=None
222 19:24:54.635499 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 19:24:54.635791 start: 1.6.2.3.6 test-overlay (timeout 00:09:46) [common]
225 19:24:54.636618 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 19:24:54.636882 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:46) [common]
228 19:24:54.637873 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 19:24:54.638135 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:46) [common]
231 19:24:54.639066 runner path: /var/lib/lava/dispatcher/tmp/13420384/lava-overlay-zm07si8g/lava-13420384/0/tests/1_kselftest-dt test_uuid 13420384_1.6.2.3.5
232 19:24:54.639163 BOARD='mt8192-asurada-spherion-r0'
233 19:24:54.639239 BRANCH='cip'
234 19:24:54.639318 SKIPFILE='/dev/null'
235 19:24:54.639394 SKIP_INSTALL='True'
236 19:24:54.639489 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 19:24:54.639587 TST_CASENAME=''
238 19:24:54.639681 TST_CMDFILES='dt'
239 19:24:54.639878 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 19:24:54.640276 Creating lava-test-runner.conf files
242 19:24:54.640376 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/13420384/lava-overlay-zm07si8g/lava-13420384/0 for stage 0
243 19:24:54.640520 - 0_timesync-off
244 19:24:54.640620 - 1_kselftest-dt
245 19:24:54.640763 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 19:24:54.640890 start: 1.6.2.4 compress-overlay (timeout 00:09:46) [common]
247 19:25:02.135181 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 19:25:02.135339 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:39) [common]
249 19:25:02.135434 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 19:25:02.135529 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
251 19:25:02.135622 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:39) [common]
252 19:25:02.299220 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 19:25:02.299634 start: 1.6.4 extract-modules (timeout 00:09:38) [common]
254 19:25:02.299777 extracting modules file /var/lib/lava/dispatcher/tmp/13420384/tftp-deploy-v1rk1d3v/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13420384/extract-nfsrootfs-5njzje7g
255 19:25:02.524330 extracting modules file /var/lib/lava/dispatcher/tmp/13420384/tftp-deploy-v1rk1d3v/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13420384/extract-overlay-ramdisk-7d1jpe1v/ramdisk
256 19:25:02.744110 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 19:25:02.744287 start: 1.6.5 apply-overlay-tftp (timeout 00:09:38) [common]
258 19:25:02.744378 [common] Applying overlay to NFS
259 19:25:02.744447 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13420384/compress-overlay-4tn29omz/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/13420384/extract-nfsrootfs-5njzje7g
260 19:25:03.654841 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 19:25:03.654995 start: 1.6.6 configure-preseed-file (timeout 00:09:37) [common]
262 19:25:03.655093 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 19:25:03.655183 start: 1.6.7 compress-ramdisk (timeout 00:09:37) [common]
264 19:25:03.655265 Building ramdisk /var/lib/lava/dispatcher/tmp/13420384/extract-overlay-ramdisk-7d1jpe1v/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/13420384/extract-overlay-ramdisk-7d1jpe1v/ramdisk
265 19:25:03.964267 >> 130624 blocks
266 19:25:05.997744 rename /var/lib/lava/dispatcher/tmp/13420384/extract-overlay-ramdisk-7d1jpe1v/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/13420384/tftp-deploy-v1rk1d3v/ramdisk/ramdisk.cpio.gz
267 19:25:05.998185 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 19:25:05.998307 start: 1.6.8 prepare-kernel (timeout 00:09:35) [common]
269 19:25:05.998415 start: 1.6.8.1 prepare-fit (timeout 00:09:35) [common]
270 19:25:05.998521 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/13420384/tftp-deploy-v1rk1d3v/kernel/Image'
271 19:25:20.100161 Returned 0 in 14 seconds
272 19:25:20.200804 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/13420384/tftp-deploy-v1rk1d3v/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/13420384/tftp-deploy-v1rk1d3v/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/13420384/tftp-deploy-v1rk1d3v/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/13420384/tftp-deploy-v1rk1d3v/kernel/image.itb
273 19:25:20.560162 output: FIT description: Kernel Image image with one or more FDT blobs
274 19:25:20.560529 output: Created: Thu Apr 18 20:25:20 2024
275 19:25:20.560608 output: Image 0 (kernel-1)
276 19:25:20.560675 output: Description:
277 19:25:20.560738 output: Created: Thu Apr 18 20:25:20 2024
278 19:25:20.560804 output: Type: Kernel Image
279 19:25:20.560865 output: Compression: lzma compressed
280 19:25:20.560928 output: Data Size: 12910355 Bytes = 12607.77 KiB = 12.31 MiB
281 19:25:20.560989 output: Architecture: AArch64
282 19:25:20.561050 output: OS: Linux
283 19:25:20.561109 output: Load Address: 0x00000000
284 19:25:20.561165 output: Entry Point: 0x00000000
285 19:25:20.561224 output: Hash algo: crc32
286 19:25:20.561281 output: Hash value: bbac8b0b
287 19:25:20.561341 output: Image 1 (fdt-1)
288 19:25:20.561397 output: Description: mt8192-asurada-spherion-r0
289 19:25:20.561455 output: Created: Thu Apr 18 20:25:20 2024
290 19:25:20.561509 output: Type: Flat Device Tree
291 19:25:20.561562 output: Compression: uncompressed
292 19:25:20.561615 output: Data Size: 47230 Bytes = 46.12 KiB = 0.05 MiB
293 19:25:20.561669 output: Architecture: AArch64
294 19:25:20.561722 output: Hash algo: crc32
295 19:25:20.561774 output: Hash value: 4bf0d1ac
296 19:25:20.561837 output: Image 2 (ramdisk-1)
297 19:25:20.561927 output: Description: unavailable
298 19:25:20.562017 output: Created: Thu Apr 18 20:25:20 2024
299 19:25:20.562096 output: Type: RAMDisk Image
300 19:25:20.562179 output: Compression: Unknown Compression
301 19:25:20.562269 output: Data Size: 18768441 Bytes = 18328.56 KiB = 17.90 MiB
302 19:25:20.562360 output: Architecture: AArch64
303 19:25:20.562447 output: OS: Linux
304 19:25:20.562528 output: Load Address: unavailable
305 19:25:20.562611 output: Entry Point: unavailable
306 19:25:20.562698 output: Hash algo: crc32
307 19:25:20.562783 output: Hash value: 04e553c2
308 19:25:20.562871 output: Default Configuration: 'conf-1'
309 19:25:20.562958 output: Configuration 0 (conf-1)
310 19:25:20.563045 output: Description: mt8192-asurada-spherion-r0
311 19:25:20.563125 output: Kernel: kernel-1
312 19:25:20.563217 output: Init Ramdisk: ramdisk-1
313 19:25:20.563307 output: FDT: fdt-1
314 19:25:20.563393 output: Loadables: kernel-1
315 19:25:20.563471 output:
316 19:25:20.563736 end: 1.6.8.1 prepare-fit (duration 00:00:15) [common]
317 19:25:20.563879 end: 1.6.8 prepare-kernel (duration 00:00:15) [common]
318 19:25:20.564071 end: 1.6 prepare-tftp-overlay (duration 00:00:32) [common]
319 19:25:20.564203 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:20) [common]
320 19:25:20.564321 No LXC device requested
321 19:25:20.564503 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 19:25:20.564621 start: 1.8 deploy-device-env (timeout 00:09:20) [common]
323 19:25:20.564705 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 19:25:20.564785 Checking files for TFTP limit of 4294967296 bytes.
325 19:25:20.565619 end: 1 tftp-deploy (duration 00:00:40) [common]
326 19:25:20.565770 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 19:25:20.565895 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 19:25:20.566069 substitutions:
329 19:25:20.566177 - {DTB}: 13420384/tftp-deploy-v1rk1d3v/dtb/mt8192-asurada-spherion-r0.dtb
330 19:25:20.566290 - {INITRD}: 13420384/tftp-deploy-v1rk1d3v/ramdisk/ramdisk.cpio.gz
331 19:25:20.566381 - {KERNEL}: 13420384/tftp-deploy-v1rk1d3v/kernel/Image
332 19:25:20.566469 - {LAVA_MAC}: None
333 19:25:20.566554 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/13420384/extract-nfsrootfs-5njzje7g
334 19:25:20.566648 - {NFS_SERVER_IP}: 192.168.201.1
335 19:25:20.566740 - {PRESEED_CONFIG}: None
336 19:25:20.566822 - {PRESEED_LOCAL}: None
337 19:25:20.566910 - {RAMDISK}: 13420384/tftp-deploy-v1rk1d3v/ramdisk/ramdisk.cpio.gz
338 19:25:20.566999 - {ROOT_PART}: None
339 19:25:20.567088 - {ROOT}: None
340 19:25:20.567184 - {SERVER_IP}: 192.168.201.1
341 19:25:20.567356 - {TEE}: None
342 19:25:20.567450 Parsed boot commands:
343 19:25:20.567530 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 19:25:20.567775 Parsed boot commands: tftpboot 192.168.201.1 13420384/tftp-deploy-v1rk1d3v/kernel/image.itb 13420384/tftp-deploy-v1rk1d3v/kernel/cmdline
345 19:25:20.567930 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 19:25:20.568025 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 19:25:20.568121 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 19:25:20.568215 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 19:25:20.568291 Not connected, no need to disconnect.
350 19:25:20.568401 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 19:25:20.568522 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 19:25:20.568619 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
353 19:25:20.573294 Setting prompt string to ['lava-test: # ']
354 19:25:20.573684 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 19:25:20.573800 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 19:25:20.573947 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 19:25:20.574070 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 19:25:20.574283 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=reboot'
359 19:25:25.709443 >> Command sent successfully.
360 19:25:25.711991 Returned 0 in 5 seconds
361 19:25:25.812474 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 19:25:25.812801 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 19:25:25.812921 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 19:25:25.813017 Setting prompt string to 'Starting depthcharge on Spherion...'
366 19:25:25.813092 Changing prompt to 'Starting depthcharge on Spherion...'
367 19:25:25.813164 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 19:25:25.813439 [Enter `^Ec?' for help]
369 19:25:25.985373
370 19:25:25.985524
371 19:25:25.985596 F0: 102B 0000
372 19:25:25.985661
373 19:25:25.985722 F3: 1001 0000 [0200]
374 19:25:25.985781
375 19:25:25.989019 F3: 1001 0000
376 19:25:25.989103
377 19:25:25.989168 F7: 102D 0000
378 19:25:25.989230
379 19:25:25.989289 F1: 0000 0000
380 19:25:25.991974
381 19:25:25.992057 V0: 0000 0000 [0001]
382 19:25:25.992162
383 19:25:25.992223 00: 0007 8000
384 19:25:25.992286
385 19:25:25.995445 01: 0000 0000
386 19:25:25.995537
387 19:25:25.995605 BP: 0C00 0209 [0000]
388 19:25:25.995668
389 19:25:25.998870 G0: 1182 0000
390 19:25:25.998946
391 19:25:25.999008 EC: 0000 0021 [4000]
392 19:25:25.999067
393 19:25:26.002297 S7: 0000 0000 [0000]
394 19:25:26.002368
395 19:25:26.002427 CC: 0000 0000 [0001]
396 19:25:26.002484
397 19:25:26.005743 T0: 0000 0040 [010F]
398 19:25:26.005815
399 19:25:26.005876 Jump to BL
400 19:25:26.005934
401 19:25:26.031852
402 19:25:26.031988
403 19:25:26.032055
404 19:25:26.038501 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 19:25:26.042414 ARM64: Exception handlers installed.
406 19:25:26.045574 ARM64: Testing exception
407 19:25:26.049294 ARM64: Done test exception
408 19:25:26.055917 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 19:25:26.065718 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 19:25:26.072745 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 19:25:26.082627 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 19:25:26.089203 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 19:25:26.099748 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 19:25:26.109821 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 19:25:26.116503 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 19:25:26.134585 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 19:25:26.137536 WDT: Last reset was cold boot
418 19:25:26.141095 SPI1(PAD0) initialized at 2873684 Hz
419 19:25:26.144245 SPI5(PAD0) initialized at 992727 Hz
420 19:25:26.147905 VBOOT: Loading verstage.
421 19:25:26.154225 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 19:25:26.157427 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 19:25:26.160704 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 19:25:26.164255 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 19:25:26.171858 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 19:25:26.179118 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 19:25:26.189208 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
428 19:25:26.189291
429 19:25:26.189356
430 19:25:26.199730 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 19:25:26.202440 ARM64: Exception handlers installed.
432 19:25:26.205982 ARM64: Testing exception
433 19:25:26.209552 ARM64: Done test exception
434 19:25:26.213206 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 19:25:26.216806 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 19:25:26.230484 Probing TPM: . done!
437 19:25:26.230564 TPM ready after 0 ms
438 19:25:26.237229 Connected to device vid:did:rid of 1ae0:0028:00
439 19:25:26.244722 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
440 19:25:26.302320 Initialized TPM device CR50 revision 0
441 19:25:26.314723 tlcl_send_startup: Startup return code is 0
442 19:25:26.314828 TPM: setup succeeded
443 19:25:26.325672 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 19:25:26.334524 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 19:25:26.348273 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 19:25:26.355716 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 19:25:26.358376 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 19:25:26.365368 in-header: 03 07 00 00 08 00 00 00
449 19:25:26.369349 in-data: aa e4 47 04 13 02 00 00
450 19:25:26.372938 Chrome EC: UHEPI supported
451 19:25:26.380263 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 19:25:26.383817 in-header: 03 95 00 00 08 00 00 00
453 19:25:26.387122 in-data: 18 20 20 08 00 00 00 00
454 19:25:26.387205 Phase 1
455 19:25:26.390908 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 19:25:26.398501 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 19:25:26.402156 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 19:25:26.406164 Recovery requested (1009000e)
459 19:25:26.414289 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 19:25:26.420073 tlcl_extend: response is 0
461 19:25:26.429296 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 19:25:26.435083 tlcl_extend: response is 0
463 19:25:26.442008 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 19:25:26.462068 read SPI 0x210d4 0x2173b: 15141 us, 9049 KB/s, 72.392 Mbps
465 19:25:26.468272 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 19:25:26.468358
467 19:25:26.468422
468 19:25:26.477857 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 19:25:26.481335 ARM64: Exception handlers installed.
470 19:25:26.484791 ARM64: Testing exception
471 19:25:26.484873 ARM64: Done test exception
472 19:25:26.507188 pmic_efuse_setting: Set efuses in 11 msecs
473 19:25:26.510389 pmwrap_interface_init: Select PMIF_VLD_RDY
474 19:25:26.517168 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 19:25:26.520276 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 19:25:26.527304 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 19:25:26.531428 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 19:25:26.534386 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 19:25:26.541962 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 19:25:26.546020 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 19:25:26.549843 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 19:25:26.552848 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 19:25:26.560420 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 19:25:26.563947 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 19:25:26.567052 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 19:25:26.574253 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 19:25:26.578321 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 19:25:26.585578 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 19:25:26.592845 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 19:25:26.596340 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 19:25:26.603832 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 19:25:26.607414 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 19:25:26.614658 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 19:25:26.618429 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 19:25:26.625530 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 19:25:26.629380 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 19:25:26.636204 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 19:25:26.640249 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 19:25:26.647535 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 19:25:26.650731 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 19:25:26.658172 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 19:25:26.661728 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 19:25:26.665355 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 19:25:26.672362 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 19:25:26.676118 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 19:25:26.683349 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 19:25:26.686694 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 19:25:26.690865 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 19:25:26.698584 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 19:25:26.701546 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 19:25:26.705511 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 19:25:26.712449 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 19:25:26.715908 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 19:25:26.719927 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 19:25:26.723250 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 19:25:26.726769 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 19:25:26.734635 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 19:25:26.738110 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 19:25:26.741815 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 19:25:26.745140 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 19:25:26.748695 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 19:25:26.755602 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 19:25:26.759654 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 19:25:26.763374 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 19:25:26.770945 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 19:25:26.777668 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 19:25:26.785046 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 19:25:26.792087 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 19:25:26.799606 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 19:25:26.802961 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 19:25:26.810221 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 19:25:26.814087 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 19:25:26.821131 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x0
534 19:25:26.824588 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 19:25:26.831815 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
536 19:25:26.835313 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 19:25:26.844676 [RTC]rtc_get_frequency_meter,154: input=15, output=853
538 19:25:26.854509 [RTC]rtc_get_frequency_meter,154: input=7, output=725
539 19:25:26.863727 [RTC]rtc_get_frequency_meter,154: input=11, output=789
540 19:25:26.872880 [RTC]rtc_get_frequency_meter,154: input=13, output=821
541 19:25:26.882454 [RTC]rtc_get_frequency_meter,154: input=12, output=804
542 19:25:26.892346 [RTC]rtc_get_frequency_meter,154: input=11, output=788
543 19:25:26.902077 [RTC]rtc_get_frequency_meter,154: input=12, output=803
544 19:25:26.905159 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
545 19:25:26.913125 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
546 19:25:26.916710 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 19:25:26.920403 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
548 19:25:26.924492 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 19:25:26.927925 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
550 19:25:26.931996 ADC[4]: Raw value=904433 ID=7
551 19:25:26.932424 ADC[3]: Raw value=213916 ID=1
552 19:25:26.935462 RAM Code: 0x71
553 19:25:26.939087 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 19:25:26.942855 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 19:25:26.953891 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 19:25:26.958116 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 19:25:26.961338 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 19:25:26.965100 in-header: 03 07 00 00 08 00 00 00
559 19:25:26.969113 in-data: aa e4 47 04 13 02 00 00
560 19:25:26.972795 Chrome EC: UHEPI supported
561 19:25:26.980399 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 19:25:26.983674 in-header: 03 95 00 00 08 00 00 00
563 19:25:26.987223 in-data: 18 20 20 08 00 00 00 00
564 19:25:26.990992 MRC: failed to locate region type 0.
565 19:25:26.994367 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 19:25:26.998063 DRAM-K: Running full calibration
567 19:25:27.005450 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 19:25:27.006060 header.status = 0x0
569 19:25:27.009325 header.version = 0x6 (expected: 0x6)
570 19:25:27.012875 header.size = 0xd00 (expected: 0xd00)
571 19:25:27.016902 header.flags = 0x0
572 19:25:27.019953 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 19:25:27.040233 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
574 19:25:27.047826 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 19:25:27.048307 dram_init: ddr_geometry: 2
576 19:25:27.051595 [EMI] MDL number = 2
577 19:25:27.052235 [EMI] Get MDL freq = 0
578 19:25:27.055314 dram_init: ddr_type: 0
579 19:25:27.058379 is_discrete_lpddr4: 1
580 19:25:27.062453 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 19:25:27.062942
582 19:25:27.063297
583 19:25:27.063613 [Bian_co] ETT version 0.0.0.1
584 19:25:27.069982 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 19:25:27.070441
586 19:25:27.073394 dramc_set_vcore_voltage set vcore to 650000
587 19:25:27.073825 Read voltage for 800, 4
588 19:25:27.077530 Vio18 = 0
589 19:25:27.078074 Vcore = 650000
590 19:25:27.078638 Vdram = 0
591 19:25:27.079178 Vddq = 0
592 19:25:27.080786 Vmddr = 0
593 19:25:27.081411 dram_init: config_dvfs: 1
594 19:25:27.087830 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 19:25:27.092050 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 19:25:27.094914 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
597 19:25:27.098742 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
598 19:25:27.101686 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
599 19:25:27.108513 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
600 19:25:27.109015 MEM_TYPE=3, freq_sel=18
601 19:25:27.112018 sv_algorithm_assistance_LP4_1600
602 19:25:27.116066 ============ PULL DRAM RESETB DOWN ============
603 19:25:27.119426 ========== PULL DRAM RESETB DOWN end =========
604 19:25:27.126410 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 19:25:27.129830 ===================================
606 19:25:27.130254 LPDDR4 DRAM CONFIGURATION
607 19:25:27.133340 ===================================
608 19:25:27.136898 EX_ROW_EN[0] = 0x0
609 19:25:27.137352 EX_ROW_EN[1] = 0x0
610 19:25:27.140218 LP4Y_EN = 0x0
611 19:25:27.140639 WORK_FSP = 0x0
612 19:25:27.143764 WL = 0x2
613 19:25:27.144215 RL = 0x2
614 19:25:27.146925 BL = 0x2
615 19:25:27.147343 RPST = 0x0
616 19:25:27.150413 RD_PRE = 0x0
617 19:25:27.153595 WR_PRE = 0x1
618 19:25:27.154014 WR_PST = 0x0
619 19:25:27.156943 DBI_WR = 0x0
620 19:25:27.157423 DBI_RD = 0x0
621 19:25:27.160091 OTF = 0x1
622 19:25:27.163601 ===================================
623 19:25:27.166969 ===================================
624 19:25:27.167389 ANA top config
625 19:25:27.170068 ===================================
626 19:25:27.173706 DLL_ASYNC_EN = 0
627 19:25:27.177138 ALL_SLAVE_EN = 1
628 19:25:27.177578 NEW_RANK_MODE = 1
629 19:25:27.179808 DLL_IDLE_MODE = 1
630 19:25:27.183148 LP45_APHY_COMB_EN = 1
631 19:25:27.186620 TX_ODT_DIS = 1
632 19:25:27.187061 NEW_8X_MODE = 1
633 19:25:27.190464 ===================================
634 19:25:27.193219 ===================================
635 19:25:27.196872 data_rate = 1600
636 19:25:27.199829 CKR = 1
637 19:25:27.202931 DQ_P2S_RATIO = 8
638 19:25:27.206714 ===================================
639 19:25:27.210244 CA_P2S_RATIO = 8
640 19:25:27.210330 DQ_CA_OPEN = 0
641 19:25:27.213576 DQ_SEMI_OPEN = 0
642 19:25:27.216485 CA_SEMI_OPEN = 0
643 19:25:27.220123 CA_FULL_RATE = 0
644 19:25:27.223614 DQ_CKDIV4_EN = 1
645 19:25:27.226558 CA_CKDIV4_EN = 1
646 19:25:27.226643 CA_PREDIV_EN = 0
647 19:25:27.229800 PH8_DLY = 0
648 19:25:27.233173 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 19:25:27.236215 DQ_AAMCK_DIV = 4
650 19:25:27.239710 CA_AAMCK_DIV = 4
651 19:25:27.243029 CA_ADMCK_DIV = 4
652 19:25:27.243113 DQ_TRACK_CA_EN = 0
653 19:25:27.246734 CA_PICK = 800
654 19:25:27.249610 CA_MCKIO = 800
655 19:25:27.252972 MCKIO_SEMI = 0
656 19:25:27.256689 PLL_FREQ = 3068
657 19:25:27.260856 DQ_UI_PI_RATIO = 32
658 19:25:27.260943 CA_UI_PI_RATIO = 0
659 19:25:27.264197 ===================================
660 19:25:27.267764 ===================================
661 19:25:27.271312 memory_type:LPDDR4
662 19:25:27.275138 GP_NUM : 10
663 19:25:27.275225 SRAM_EN : 1
664 19:25:27.278887 MD32_EN : 0
665 19:25:27.278974 ===================================
666 19:25:27.282322 [ANA_INIT] >>>>>>>>>>>>>>
667 19:25:27.286055 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 19:25:27.289815 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 19:25:27.292672 ===================================
670 19:25:27.296175 data_rate = 1600,PCW = 0X7600
671 19:25:27.299757 ===================================
672 19:25:27.302578 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 19:25:27.306361 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 19:25:27.313255 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 19:25:27.316604 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 19:25:27.319414 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 19:25:27.322905 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 19:25:27.326537 [ANA_INIT] flow start
679 19:25:27.329583 [ANA_INIT] PLL >>>>>>>>
680 19:25:27.329665 [ANA_INIT] PLL <<<<<<<<
681 19:25:27.333000 [ANA_INIT] MIDPI >>>>>>>>
682 19:25:27.336365 [ANA_INIT] MIDPI <<<<<<<<
683 19:25:27.336448 [ANA_INIT] DLL >>>>>>>>
684 19:25:27.339489 [ANA_INIT] flow end
685 19:25:27.343478 ============ LP4 DIFF to SE enter ============
686 19:25:27.349671 ============ LP4 DIFF to SE exit ============
687 19:25:27.349754 [ANA_INIT] <<<<<<<<<<<<<
688 19:25:27.353366 [Flow] Enable top DCM control >>>>>
689 19:25:27.356278 [Flow] Enable top DCM control <<<<<
690 19:25:27.359765 Enable DLL master slave shuffle
691 19:25:27.366266 ==============================================================
692 19:25:27.366349 Gating Mode config
693 19:25:27.372756 ==============================================================
694 19:25:27.375914 Config description:
695 19:25:27.382886 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 19:25:27.389704 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 19:25:27.395938 SELPH_MODE 0: By rank 1: By Phase
698 19:25:27.402735 ==============================================================
699 19:25:27.405866 GAT_TRACK_EN = 1
700 19:25:27.405951 RX_GATING_MODE = 2
701 19:25:27.409147 RX_GATING_TRACK_MODE = 2
702 19:25:27.412715 SELPH_MODE = 1
703 19:25:27.416057 PICG_EARLY_EN = 1
704 19:25:27.419301 VALID_LAT_VALUE = 1
705 19:25:27.425889 ==============================================================
706 19:25:27.429698 Enter into Gating configuration >>>>
707 19:25:27.432290 Exit from Gating configuration <<<<
708 19:25:27.435840 Enter into DVFS_PRE_config >>>>>
709 19:25:27.445732 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 19:25:27.449117 Exit from DVFS_PRE_config <<<<<
711 19:25:27.452101 Enter into PICG configuration >>>>
712 19:25:27.455639 Exit from PICG configuration <<<<
713 19:25:27.459093 [RX_INPUT] configuration >>>>>
714 19:25:27.462581 [RX_INPUT] configuration <<<<<
715 19:25:27.465662 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 19:25:27.472029 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 19:25:27.478904 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 19:25:27.481785 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 19:25:27.488690 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 19:25:27.495590 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 19:25:27.498517 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 19:25:27.504878 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 19:25:27.508700 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 19:25:27.512123 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 19:25:27.514919 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 19:25:27.521498 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 19:25:27.525172 ===================================
728 19:25:27.525259 LPDDR4 DRAM CONFIGURATION
729 19:25:27.528039 ===================================
730 19:25:27.531357 EX_ROW_EN[0] = 0x0
731 19:25:27.534922 EX_ROW_EN[1] = 0x0
732 19:25:27.535004 LP4Y_EN = 0x0
733 19:25:27.538390 WORK_FSP = 0x0
734 19:25:27.538472 WL = 0x2
735 19:25:27.541224 RL = 0x2
736 19:25:27.541306 BL = 0x2
737 19:25:27.544640 RPST = 0x0
738 19:25:27.544721 RD_PRE = 0x0
739 19:25:27.548008 WR_PRE = 0x1
740 19:25:27.548095 WR_PST = 0x0
741 19:25:27.551687 DBI_WR = 0x0
742 19:25:27.551774 DBI_RD = 0x0
743 19:25:27.555281 OTF = 0x1
744 19:25:27.558513 ===================================
745 19:25:27.561712 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 19:25:27.564745 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 19:25:27.571451 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 19:25:27.574487 ===================================
749 19:25:27.574650 LPDDR4 DRAM CONFIGURATION
750 19:25:27.577947 ===================================
751 19:25:27.581387 EX_ROW_EN[0] = 0x10
752 19:25:27.585015 EX_ROW_EN[1] = 0x0
753 19:25:27.585192 LP4Y_EN = 0x0
754 19:25:27.587711 WORK_FSP = 0x0
755 19:25:27.587864 WL = 0x2
756 19:25:27.591226 RL = 0x2
757 19:25:27.591430 BL = 0x2
758 19:25:27.594701 RPST = 0x0
759 19:25:27.594958 RD_PRE = 0x0
760 19:25:27.597921 WR_PRE = 0x1
761 19:25:27.598255 WR_PST = 0x0
762 19:25:27.601468 DBI_WR = 0x0
763 19:25:27.601865 DBI_RD = 0x0
764 19:25:27.604864 OTF = 0x1
765 19:25:27.608180 ===================================
766 19:25:27.614606 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 19:25:27.618175 nWR fixed to 40
768 19:25:27.618648 [ModeRegInit_LP4] CH0 RK0
769 19:25:27.621754 [ModeRegInit_LP4] CH0 RK1
770 19:25:27.624708 [ModeRegInit_LP4] CH1 RK0
771 19:25:27.628042 [ModeRegInit_LP4] CH1 RK1
772 19:25:27.628463 match AC timing 13
773 19:25:27.634778 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 19:25:27.637960 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 19:25:27.641537 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 19:25:27.648221 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 19:25:27.651105 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 19:25:27.651528 [EMI DOE] emi_dcm 0
779 19:25:27.657791 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 19:25:27.658393 ==
781 19:25:27.661673 Dram Type= 6, Freq= 0, CH_0, rank 0
782 19:25:27.664705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 19:25:27.665129 ==
784 19:25:27.671113 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 19:25:27.674367 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 19:25:27.685487 [CA 0] Center 37 (7~68) winsize 62
787 19:25:27.688429 [CA 1] Center 37 (6~68) winsize 63
788 19:25:27.691964 [CA 2] Center 34 (4~65) winsize 62
789 19:25:27.694957 [CA 3] Center 35 (4~66) winsize 63
790 19:25:27.698678 [CA 4] Center 34 (3~65) winsize 63
791 19:25:27.701971 [CA 5] Center 33 (3~64) winsize 62
792 19:25:27.702414
793 19:25:27.705242 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 19:25:27.705684
795 19:25:27.708420 [CATrainingPosCal] consider 1 rank data
796 19:25:27.711797 u2DelayCellTimex100 = 270/100 ps
797 19:25:27.714913 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
798 19:25:27.718245 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
799 19:25:27.724533 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
800 19:25:27.728059 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
801 19:25:27.731651 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
802 19:25:27.735073 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 19:25:27.735531
804 19:25:27.738401 CA PerBit enable=1, Macro0, CA PI delay=33
805 19:25:27.738848
806 19:25:27.741454 [CBTSetCACLKResult] CA Dly = 33
807 19:25:27.741876 CS Dly: 6 (0~37)
808 19:25:27.744541 ==
809 19:25:27.748284 Dram Type= 6, Freq= 0, CH_0, rank 1
810 19:25:27.751509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 19:25:27.751994 ==
812 19:25:27.755043 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 19:25:27.761419 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 19:25:27.771306 [CA 0] Center 38 (7~69) winsize 63
815 19:25:27.774698 [CA 1] Center 37 (7~68) winsize 62
816 19:25:27.777878 [CA 2] Center 35 (4~66) winsize 63
817 19:25:27.781446 [CA 3] Center 35 (4~66) winsize 63
818 19:25:27.784730 [CA 4] Center 34 (3~65) winsize 63
819 19:25:27.788133 [CA 5] Center 33 (3~64) winsize 62
820 19:25:27.788555
821 19:25:27.791084 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 19:25:27.791505
823 19:25:27.794509 [CATrainingPosCal] consider 2 rank data
824 19:25:27.798064 u2DelayCellTimex100 = 270/100 ps
825 19:25:27.800959 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
826 19:25:27.807865 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
827 19:25:27.811586 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
828 19:25:27.814332 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
829 19:25:27.817812 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
830 19:25:27.821391 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 19:25:27.821837
832 19:25:27.824268 CA PerBit enable=1, Macro0, CA PI delay=33
833 19:25:27.824693
834 19:25:27.827638 [CBTSetCACLKResult] CA Dly = 33
835 19:25:27.831366 CS Dly: 6 (0~38)
836 19:25:27.831803
837 19:25:27.834801 ----->DramcWriteLeveling(PI) begin...
838 19:25:27.835242 ==
839 19:25:27.838351 Dram Type= 6, Freq= 0, CH_0, rank 0
840 19:25:27.841826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 19:25:27.842324 ==
842 19:25:27.845429 Write leveling (Byte 0): 33 => 33
843 19:25:27.845854 Write leveling (Byte 1): 26 => 26
844 19:25:27.849151 DramcWriteLeveling(PI) end<-----
845 19:25:27.849572
846 19:25:27.849910 ==
847 19:25:27.852690 Dram Type= 6, Freq= 0, CH_0, rank 0
848 19:25:27.859071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 19:25:27.859740 ==
850 19:25:27.860284 [Gating] SW mode calibration
851 19:25:27.866363 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 19:25:27.873417 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 19:25:27.876611 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 19:25:27.879953 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
855 19:25:27.886621 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
856 19:25:27.889820 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 19:25:27.893879 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 19:25:27.900329 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 19:25:27.903121 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 19:25:27.906625 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 19:25:27.913542 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 19:25:27.916383 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 19:25:27.919783 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 19:25:27.926954 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 19:25:27.929733 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 19:25:27.933172 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 19:25:27.939605 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 19:25:27.943175 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 19:25:27.946091 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 19:25:27.952681 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
871 19:25:27.955969 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
872 19:25:27.959335 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 19:25:27.966004 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 19:25:27.969605 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 19:25:27.972572 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 19:25:27.979307 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 19:25:27.982353 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 19:25:27.986019 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 19:25:27.992610 0 9 8 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
880 19:25:27.995725 0 9 12 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
881 19:25:27.999060 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 19:25:28.005464 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 19:25:28.009080 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 19:25:28.012476 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 19:25:28.018800 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 19:25:28.022861 0 10 4 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
887 19:25:28.025748 0 10 8 | B1->B0 | 3232 2828 | 0 0 | (0 0) (0 0)
888 19:25:28.032498 0 10 12 | B1->B0 | 2727 2323 | 1 0 | (1 0) (0 0)
889 19:25:28.035576 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 19:25:28.039156 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 19:25:28.042375 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 19:25:28.049150 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 19:25:28.052743 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 19:25:28.055553 0 11 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
895 19:25:28.062461 0 11 8 | B1->B0 | 2b2b 4343 | 0 0 | (0 0) (0 0)
896 19:25:28.065591 0 11 12 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
897 19:25:28.069474 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 19:25:28.075832 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 19:25:28.079490 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 19:25:28.082656 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 19:25:28.088929 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 19:25:28.092543 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
903 19:25:28.095620 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
904 19:25:28.102171 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 19:25:28.105713 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 19:25:28.109367 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 19:25:28.115819 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 19:25:28.119594 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 19:25:28.122509 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 19:25:28.129444 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 19:25:28.132772 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 19:25:28.135933 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 19:25:28.142388 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 19:25:28.145935 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 19:25:28.148789 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 19:25:28.155712 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 19:25:28.159163 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 19:25:28.162397 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
919 19:25:28.168890 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
920 19:25:28.169315 Total UI for P1: 0, mck2ui 16
921 19:25:28.172351 best dqsien dly found for B0: ( 0, 14, 4)
922 19:25:28.178623 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
923 19:25:28.181651 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
924 19:25:28.184924 Total UI for P1: 0, mck2ui 16
925 19:25:28.188355 best dqsien dly found for B1: ( 0, 14, 10)
926 19:25:28.192310 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
927 19:25:28.195061 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
928 19:25:28.195421
929 19:25:28.198765 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
930 19:25:28.205304 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
931 19:25:28.205676 [Gating] SW calibration Done
932 19:25:28.205990 ==
933 19:25:28.208995 Dram Type= 6, Freq= 0, CH_0, rank 0
934 19:25:28.215626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 19:25:28.216120 ==
936 19:25:28.216583 RX Vref Scan: 0
937 19:25:28.217048
938 19:25:28.218633 RX Vref 0 -> 0, step: 1
939 19:25:28.219098
940 19:25:28.222123 RX Delay -130 -> 252, step: 16
941 19:25:28.225432 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
942 19:25:28.228884 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
943 19:25:28.232170 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
944 19:25:28.235378 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
945 19:25:28.242097 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
946 19:25:28.245064 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
947 19:25:28.248439 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
948 19:25:28.252005 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
949 19:25:28.258316 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
950 19:25:28.261830 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
951 19:25:28.265096 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
952 19:25:28.268384 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
953 19:25:28.271858 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
954 19:25:28.278789 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
955 19:25:28.281853 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
956 19:25:28.285289 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
957 19:25:28.285742 ==
958 19:25:28.288554 Dram Type= 6, Freq= 0, CH_0, rank 0
959 19:25:28.291689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
960 19:25:28.292295 ==
961 19:25:28.295069 DQS Delay:
962 19:25:28.295596 DQS0 = 0, DQS1 = 0
963 19:25:28.298565 DQM Delay:
964 19:25:28.298979 DQM0 = 87, DQM1 = 76
965 19:25:28.299310 DQ Delay:
966 19:25:28.302179 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
967 19:25:28.305113 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =93
968 19:25:28.308519 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
969 19:25:28.312081 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
970 19:25:28.312499
971 19:25:28.312832
972 19:25:28.315575 ==
973 19:25:28.318491 Dram Type= 6, Freq= 0, CH_0, rank 0
974 19:25:28.321554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
975 19:25:28.322003 ==
976 19:25:28.322349
977 19:25:28.322699
978 19:25:28.325122 TX Vref Scan disable
979 19:25:28.325541 == TX Byte 0 ==
980 19:25:28.331617 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
981 19:25:28.334933 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
982 19:25:28.335484 == TX Byte 1 ==
983 19:25:28.341303 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
984 19:25:28.344946 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
985 19:25:28.345519 ==
986 19:25:28.348835 Dram Type= 6, Freq= 0, CH_0, rank 0
987 19:25:28.351503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
988 19:25:28.351953 ==
989 19:25:28.365574 TX Vref=22, minBit 4, minWin=26, winSum=438
990 19:25:28.369401 TX Vref=24, minBit 0, minWin=27, winSum=442
991 19:25:28.372411 TX Vref=26, minBit 1, minWin=27, winSum=444
992 19:25:28.375719 TX Vref=28, minBit 1, minWin=27, winSum=447
993 19:25:28.379315 TX Vref=30, minBit 0, minWin=28, winSum=450
994 19:25:28.382764 TX Vref=32, minBit 4, minWin=27, winSum=449
995 19:25:28.389286 [TxChooseVref] Worse bit 0, Min win 28, Win sum 450, Final Vref 30
996 19:25:28.389746
997 19:25:28.392229 Final TX Range 1 Vref 30
998 19:25:28.392650
999 19:25:28.392980 ==
1000 19:25:28.395567 Dram Type= 6, Freq= 0, CH_0, rank 0
1001 19:25:28.399674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1002 19:25:28.400247 ==
1003 19:25:28.400589
1004 19:25:28.402172
1005 19:25:28.402767 TX Vref Scan disable
1006 19:25:28.406300 == TX Byte 0 ==
1007 19:25:28.409277 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1008 19:25:28.415554 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1009 19:25:28.416028 == TX Byte 1 ==
1010 19:25:28.418779 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1011 19:25:28.425389 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1012 19:25:28.425884
1013 19:25:28.426382 [DATLAT]
1014 19:25:28.426879 Freq=800, CH0 RK0
1015 19:25:28.427335
1016 19:25:28.428813 DATLAT Default: 0xa
1017 19:25:28.429271 0, 0xFFFF, sum = 0
1018 19:25:28.432279 1, 0xFFFF, sum = 0
1019 19:25:28.432851 2, 0xFFFF, sum = 0
1020 19:25:28.435547 3, 0xFFFF, sum = 0
1021 19:25:28.438617 4, 0xFFFF, sum = 0
1022 19:25:28.439186 5, 0xFFFF, sum = 0
1023 19:25:28.442100 6, 0xFFFF, sum = 0
1024 19:25:28.442705 7, 0xFFFF, sum = 0
1025 19:25:28.445628 8, 0xFFFF, sum = 0
1026 19:25:28.446086 9, 0x0, sum = 1
1027 19:25:28.448557 10, 0x0, sum = 2
1028 19:25:28.448975 11, 0x0, sum = 3
1029 19:25:28.449311 12, 0x0, sum = 4
1030 19:25:28.452133 best_step = 10
1031 19:25:28.452641
1032 19:25:28.452991 ==
1033 19:25:28.455585 Dram Type= 6, Freq= 0, CH_0, rank 0
1034 19:25:28.458791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1035 19:25:28.459203 ==
1036 19:25:28.462344 RX Vref Scan: 1
1037 19:25:28.462745
1038 19:25:28.465292 Set Vref Range= 32 -> 127
1039 19:25:28.465726
1040 19:25:28.466060 RX Vref 32 -> 127, step: 1
1041 19:25:28.466380
1042 19:25:28.468674 RX Delay -95 -> 252, step: 8
1043 19:25:28.469146
1044 19:25:28.471848 Set Vref, RX VrefLevel [Byte0]: 32
1045 19:25:28.475228 [Byte1]: 32
1046 19:25:28.475642
1047 19:25:28.478359 Set Vref, RX VrefLevel [Byte0]: 33
1048 19:25:28.481930 [Byte1]: 33
1049 19:25:28.486102
1050 19:25:28.486543 Set Vref, RX VrefLevel [Byte0]: 34
1051 19:25:28.489198 [Byte1]: 34
1052 19:25:28.493299
1053 19:25:28.493729 Set Vref, RX VrefLevel [Byte0]: 35
1054 19:25:28.496850 [Byte1]: 35
1055 19:25:28.501984
1056 19:25:28.502429 Set Vref, RX VrefLevel [Byte0]: 36
1057 19:25:28.505138 [Byte1]: 36
1058 19:25:28.509390
1059 19:25:28.509845 Set Vref, RX VrefLevel [Byte0]: 37
1060 19:25:28.512442 [Byte1]: 37
1061 19:25:28.516942
1062 19:25:28.517508 Set Vref, RX VrefLevel [Byte0]: 38
1063 19:25:28.520199 [Byte1]: 38
1064 19:25:28.524317
1065 19:25:28.524737 Set Vref, RX VrefLevel [Byte0]: 39
1066 19:25:28.527668 [Byte1]: 39
1067 19:25:28.531677
1068 19:25:28.532173 Set Vref, RX VrefLevel [Byte0]: 40
1069 19:25:28.535063 [Byte1]: 40
1070 19:25:28.539273
1071 19:25:28.539714 Set Vref, RX VrefLevel [Byte0]: 41
1072 19:25:28.542631 [Byte1]: 41
1073 19:25:28.546706
1074 19:25:28.547157 Set Vref, RX VrefLevel [Byte0]: 42
1075 19:25:28.549724 [Byte1]: 42
1076 19:25:28.554541
1077 19:25:28.555257 Set Vref, RX VrefLevel [Byte0]: 43
1078 19:25:28.557649 [Byte1]: 43
1079 19:25:28.561652
1080 19:25:28.562362 Set Vref, RX VrefLevel [Byte0]: 44
1081 19:25:28.565184 [Byte1]: 44
1082 19:25:28.569769
1083 19:25:28.570207 Set Vref, RX VrefLevel [Byte0]: 45
1084 19:25:28.572854 [Byte1]: 45
1085 19:25:28.576840
1086 19:25:28.577340 Set Vref, RX VrefLevel [Byte0]: 46
1087 19:25:28.580227 [Byte1]: 46
1088 19:25:28.584599
1089 19:25:28.585130 Set Vref, RX VrefLevel [Byte0]: 47
1090 19:25:28.588310 [Byte1]: 47
1091 19:25:28.592019
1092 19:25:28.592435 Set Vref, RX VrefLevel [Byte0]: 48
1093 19:25:28.595381 [Byte1]: 48
1094 19:25:28.599878
1095 19:25:28.600458 Set Vref, RX VrefLevel [Byte0]: 49
1096 19:25:28.602853 [Byte1]: 49
1097 19:25:28.607732
1098 19:25:28.608229 Set Vref, RX VrefLevel [Byte0]: 50
1099 19:25:28.610774 [Byte1]: 50
1100 19:25:28.615223
1101 19:25:28.615752 Set Vref, RX VrefLevel [Byte0]: 51
1102 19:25:28.618416 [Byte1]: 51
1103 19:25:28.622552
1104 19:25:28.622972 Set Vref, RX VrefLevel [Byte0]: 52
1105 19:25:28.626360 [Byte1]: 52
1106 19:25:28.630379
1107 19:25:28.630814 Set Vref, RX VrefLevel [Byte0]: 53
1108 19:25:28.633917 [Byte1]: 53
1109 19:25:28.637872
1110 19:25:28.638171 Set Vref, RX VrefLevel [Byte0]: 54
1111 19:25:28.641153 [Byte1]: 54
1112 19:25:28.645711
1113 19:25:28.646040 Set Vref, RX VrefLevel [Byte0]: 55
1114 19:25:28.648934 [Byte1]: 55
1115 19:25:28.653090
1116 19:25:28.653483 Set Vref, RX VrefLevel [Byte0]: 56
1117 19:25:28.656166 [Byte1]: 56
1118 19:25:28.660821
1119 19:25:28.661237 Set Vref, RX VrefLevel [Byte0]: 57
1120 19:25:28.663833 [Byte1]: 57
1121 19:25:28.668009
1122 19:25:28.668308 Set Vref, RX VrefLevel [Byte0]: 58
1123 19:25:28.670996 [Byte1]: 58
1124 19:25:28.675775
1125 19:25:28.675858 Set Vref, RX VrefLevel [Byte0]: 59
1126 19:25:28.678881 [Byte1]: 59
1127 19:25:28.682959
1128 19:25:28.683042 Set Vref, RX VrefLevel [Byte0]: 60
1129 19:25:28.686273 [Byte1]: 60
1130 19:25:28.690991
1131 19:25:28.691074 Set Vref, RX VrefLevel [Byte0]: 61
1132 19:25:28.694031 [Byte1]: 61
1133 19:25:28.698547
1134 19:25:28.698630 Set Vref, RX VrefLevel [Byte0]: 62
1135 19:25:28.701934 [Byte1]: 62
1136 19:25:28.705670
1137 19:25:28.705753 Set Vref, RX VrefLevel [Byte0]: 63
1138 19:25:28.709513 [Byte1]: 63
1139 19:25:28.713692
1140 19:25:28.713777 Set Vref, RX VrefLevel [Byte0]: 64
1141 19:25:28.716908 [Byte1]: 64
1142 19:25:28.721026
1143 19:25:28.721109 Set Vref, RX VrefLevel [Byte0]: 65
1144 19:25:28.724264 [Byte1]: 65
1145 19:25:28.728892
1146 19:25:28.728975 Set Vref, RX VrefLevel [Byte0]: 66
1147 19:25:28.731848 [Byte1]: 66
1148 19:25:28.736304
1149 19:25:28.736389 Set Vref, RX VrefLevel [Byte0]: 67
1150 19:25:28.739528 [Byte1]: 67
1151 19:25:28.743812
1152 19:25:28.743916 Set Vref, RX VrefLevel [Byte0]: 68
1153 19:25:28.746797 [Byte1]: 68
1154 19:25:28.751391
1155 19:25:28.751473 Set Vref, RX VrefLevel [Byte0]: 69
1156 19:25:28.754565 [Byte1]: 69
1157 19:25:28.759029
1158 19:25:28.759110 Set Vref, RX VrefLevel [Byte0]: 70
1159 19:25:28.762539 [Byte1]: 70
1160 19:25:28.766551
1161 19:25:28.766633 Set Vref, RX VrefLevel [Byte0]: 71
1162 19:25:28.770166 [Byte1]: 71
1163 19:25:28.774168
1164 19:25:28.777659 Set Vref, RX VrefLevel [Byte0]: 72
1165 19:25:28.780694 [Byte1]: 72
1166 19:25:28.780780
1167 19:25:28.784235 Set Vref, RX VrefLevel [Byte0]: 73
1168 19:25:28.787193 [Byte1]: 73
1169 19:25:28.787274
1170 19:25:28.790768 Final RX Vref Byte 0 = 58 to rank0
1171 19:25:28.793776 Final RX Vref Byte 1 = 59 to rank0
1172 19:25:28.797123 Final RX Vref Byte 0 = 58 to rank1
1173 19:25:28.800589 Final RX Vref Byte 1 = 59 to rank1==
1174 19:25:28.803775 Dram Type= 6, Freq= 0, CH_0, rank 0
1175 19:25:28.807281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1176 19:25:28.807364 ==
1177 19:25:28.810572 DQS Delay:
1178 19:25:28.810654 DQS0 = 0, DQS1 = 0
1179 19:25:28.810718 DQM Delay:
1180 19:25:28.814014 DQM0 = 88, DQM1 = 76
1181 19:25:28.814096 DQ Delay:
1182 19:25:28.817071 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1183 19:25:28.820667 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1184 19:25:28.823610 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =72
1185 19:25:28.826817 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1186 19:25:28.826899
1187 19:25:28.826964
1188 19:25:28.836871 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e28, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
1189 19:25:28.836954 CH0 RK0: MR19=606, MR18=2E28
1190 19:25:28.843935 CH0_RK0: MR19=0x606, MR18=0x2E28, DQSOSC=398, MR23=63, INC=93, DEC=62
1191 19:25:28.844017
1192 19:25:28.847280 ----->DramcWriteLeveling(PI) begin...
1193 19:25:28.847363 ==
1194 19:25:28.850474 Dram Type= 6, Freq= 0, CH_0, rank 1
1195 19:25:28.856777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1196 19:25:28.856877 ==
1197 19:25:28.860243 Write leveling (Byte 0): 30 => 30
1198 19:25:28.863323 Write leveling (Byte 1): 29 => 29
1199 19:25:28.866792 DramcWriteLeveling(PI) end<-----
1200 19:25:28.866873
1201 19:25:28.866938 ==
1202 19:25:28.870533 Dram Type= 6, Freq= 0, CH_0, rank 1
1203 19:25:28.873320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1204 19:25:28.873402 ==
1205 19:25:28.876761 [Gating] SW mode calibration
1206 19:25:28.883380 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1207 19:25:28.886963 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1208 19:25:28.893252 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1209 19:25:28.896906 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1210 19:25:28.940489 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 19:25:28.940764 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 19:25:28.940834 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 19:25:28.940896 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 19:25:28.940966 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 19:25:28.941040 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 19:25:28.941194 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 19:25:28.941290 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 19:25:28.941356 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 19:25:28.941429 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 19:25:28.964427 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 19:25:28.964727 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 19:25:28.965173 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 19:25:28.965255 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 19:25:28.965503 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 19:25:28.968333 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1226 19:25:28.971391 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1227 19:25:28.974980 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 19:25:28.981109 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 19:25:28.984716 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 19:25:28.987648 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 19:25:28.994244 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 19:25:28.997967 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 19:25:29.001371 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 19:25:29.007955 0 9 8 | B1->B0 | 2424 3232 | 0 0 | (0 0) (0 0)
1235 19:25:29.011025 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1236 19:25:29.014576 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1237 19:25:29.021537 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1238 19:25:29.024799 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1239 19:25:29.027857 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1240 19:25:29.034485 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1241 19:25:29.037787 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 1)
1242 19:25:29.041286 0 10 8 | B1->B0 | 3232 2424 | 1 0 | (1 0) (0 0)
1243 19:25:29.047547 0 10 12 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
1244 19:25:29.051259 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 19:25:29.054372 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 19:25:29.060655 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 19:25:29.064072 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 19:25:29.067342 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 19:25:29.074370 0 11 4 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (0 0)
1250 19:25:29.077274 0 11 8 | B1->B0 | 3232 4343 | 1 0 | (0 0) (0 0)
1251 19:25:29.080747 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1252 19:25:29.084320 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1253 19:25:29.091669 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1254 19:25:29.095233 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1255 19:25:29.099188 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1256 19:25:29.102630 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1257 19:25:29.109215 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1258 19:25:29.113217 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1259 19:25:29.116458 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1260 19:25:29.122777 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1261 19:25:29.126321 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1262 19:25:29.129134 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1263 19:25:29.135788 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 19:25:29.139685 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 19:25:29.142834 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 19:25:29.149135 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 19:25:29.152754 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 19:25:29.156010 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 19:25:29.162842 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 19:25:29.165990 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 19:25:29.169264 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 19:25:29.175999 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 19:25:29.179316 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1274 19:25:29.182902 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1275 19:25:29.185739 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1276 19:25:29.189088 Total UI for P1: 0, mck2ui 16
1277 19:25:29.192566 best dqsien dly found for B0: ( 0, 14, 6)
1278 19:25:29.195643 Total UI for P1: 0, mck2ui 16
1279 19:25:29.199296 best dqsien dly found for B1: ( 0, 14, 8)
1280 19:25:29.202326 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1281 19:25:29.209316 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1282 19:25:29.209734
1283 19:25:29.212144 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1284 19:25:29.215563 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1285 19:25:29.218702 [Gating] SW calibration Done
1286 19:25:29.219120 ==
1287 19:25:29.222731 Dram Type= 6, Freq= 0, CH_0, rank 1
1288 19:25:29.225508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1289 19:25:29.225932 ==
1290 19:25:29.226266 RX Vref Scan: 0
1291 19:25:29.229336
1292 19:25:29.229751 RX Vref 0 -> 0, step: 1
1293 19:25:29.230083
1294 19:25:29.232236 RX Delay -130 -> 252, step: 16
1295 19:25:29.235605 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1296 19:25:29.238972 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1297 19:25:29.245710 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1298 19:25:29.248837 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1299 19:25:29.251927 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1300 19:25:29.255491 iDelay=206, Bit 5, Center 69 (-50 ~ 189) 240
1301 19:25:29.258788 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1302 19:25:29.265237 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1303 19:25:29.268677 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1304 19:25:29.271983 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1305 19:25:29.275470 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1306 19:25:29.281809 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1307 19:25:29.285408 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1308 19:25:29.288294 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1309 19:25:29.291844 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1310 19:25:29.295067 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1311 19:25:29.295624 ==
1312 19:25:29.298491 Dram Type= 6, Freq= 0, CH_0, rank 1
1313 19:25:29.305123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1314 19:25:29.305548 ==
1315 19:25:29.305910 DQS Delay:
1316 19:25:29.308470 DQS0 = 0, DQS1 = 0
1317 19:25:29.308915 DQM Delay:
1318 19:25:29.311959 DQM0 = 86, DQM1 = 76
1319 19:25:29.312403 DQ Delay:
1320 19:25:29.315222 DQ0 =85, DQ1 =93, DQ2 =77, DQ3 =85
1321 19:25:29.318170 DQ4 =93, DQ5 =69, DQ6 =93, DQ7 =93
1322 19:25:29.321590 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
1323 19:25:29.325019 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1324 19:25:29.325434
1325 19:25:29.325764
1326 19:25:29.326076 ==
1327 19:25:29.328370 Dram Type= 6, Freq= 0, CH_0, rank 1
1328 19:25:29.331753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1329 19:25:29.332248 ==
1330 19:25:29.332613
1331 19:25:29.333057
1332 19:25:29.334933 TX Vref Scan disable
1333 19:25:29.338619 == TX Byte 0 ==
1334 19:25:29.341095 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1335 19:25:29.344587 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1336 19:25:29.348106 == TX Byte 1 ==
1337 19:25:29.350907 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1338 19:25:29.354406 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1339 19:25:29.354512 ==
1340 19:25:29.357775 Dram Type= 6, Freq= 0, CH_0, rank 1
1341 19:25:29.361316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1342 19:25:29.364420 ==
1343 19:25:29.375538 TX Vref=22, minBit 0, minWin=27, winSum=438
1344 19:25:29.378957 TX Vref=24, minBit 0, minWin=27, winSum=446
1345 19:25:29.382116 TX Vref=26, minBit 2, minWin=27, winSum=449
1346 19:25:29.385275 TX Vref=28, minBit 2, minWin=27, winSum=447
1347 19:25:29.388400 TX Vref=30, minBit 1, minWin=27, winSum=448
1348 19:25:29.392202 TX Vref=32, minBit 2, minWin=27, winSum=448
1349 19:25:29.398710 [TxChooseVref] Worse bit 2, Min win 27, Win sum 449, Final Vref 26
1350 19:25:29.398793
1351 19:25:29.401923 Final TX Range 1 Vref 26
1352 19:25:29.402006
1353 19:25:29.402071 ==
1354 19:25:29.405839 Dram Type= 6, Freq= 0, CH_0, rank 1
1355 19:25:29.408593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1356 19:25:29.408675 ==
1357 19:25:29.411750
1358 19:25:29.411830
1359 19:25:29.411922 TX Vref Scan disable
1360 19:25:29.415409 == TX Byte 0 ==
1361 19:25:29.418712 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1362 19:25:29.425413 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1363 19:25:29.425514 == TX Byte 1 ==
1364 19:25:29.428738 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1365 19:25:29.434975 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1366 19:25:29.435099
1367 19:25:29.435195 [DATLAT]
1368 19:25:29.435282 Freq=800, CH0 RK1
1369 19:25:29.435368
1370 19:25:29.438608 DATLAT Default: 0xa
1371 19:25:29.438729 0, 0xFFFF, sum = 0
1372 19:25:29.441870 1, 0xFFFF, sum = 0
1373 19:25:29.442005 2, 0xFFFF, sum = 0
1374 19:25:29.445426 3, 0xFFFF, sum = 0
1375 19:25:29.448775 4, 0xFFFF, sum = 0
1376 19:25:29.448944 5, 0xFFFF, sum = 0
1377 19:25:29.451678 6, 0xFFFF, sum = 0
1378 19:25:29.451850 7, 0xFFFF, sum = 0
1379 19:25:29.455149 8, 0xFFFF, sum = 0
1380 19:25:29.455231 9, 0x0, sum = 1
1381 19:25:29.457974 10, 0x0, sum = 2
1382 19:25:29.458044 11, 0x0, sum = 3
1383 19:25:29.458105 12, 0x0, sum = 4
1384 19:25:29.461607 best_step = 10
1385 19:25:29.461687
1386 19:25:29.461751 ==
1387 19:25:29.465136 Dram Type= 6, Freq= 0, CH_0, rank 1
1388 19:25:29.468116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1389 19:25:29.468191 ==
1390 19:25:29.471447 RX Vref Scan: 0
1391 19:25:29.471556
1392 19:25:29.474921 RX Vref 0 -> 0, step: 1
1393 19:25:29.475040
1394 19:25:29.475103 RX Delay -95 -> 252, step: 8
1395 19:25:29.481860 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1396 19:25:29.485401 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1397 19:25:29.488259 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1398 19:25:29.491696 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1399 19:25:29.495268 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1400 19:25:29.501927 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1401 19:25:29.505072 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1402 19:25:29.508312 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1403 19:25:29.511542 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1404 19:25:29.515015 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1405 19:25:29.521286 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1406 19:25:29.524927 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1407 19:25:29.528318 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1408 19:25:29.531372 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1409 19:25:29.538256 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1410 19:25:29.541569 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1411 19:25:29.541650 ==
1412 19:25:29.544613 Dram Type= 6, Freq= 0, CH_0, rank 1
1413 19:25:29.548199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1414 19:25:29.548280 ==
1415 19:25:29.551304 DQS Delay:
1416 19:25:29.551422 DQS0 = 0, DQS1 = 0
1417 19:25:29.551486 DQM Delay:
1418 19:25:29.554602 DQM0 = 86, DQM1 = 77
1419 19:25:29.554682 DQ Delay:
1420 19:25:29.558018 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =80
1421 19:25:29.561515 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1422 19:25:29.564389 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =72
1423 19:25:29.568107 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1424 19:25:29.568188
1425 19:25:29.568250
1426 19:25:29.578092 [DQSOSCAuto] RK1, (LSB)MR18= 0x2320, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
1427 19:25:29.578179 CH0 RK1: MR19=606, MR18=2320
1428 19:25:29.584371 CH0_RK1: MR19=0x606, MR18=0x2320, DQSOSC=401, MR23=63, INC=91, DEC=61
1429 19:25:29.587962 [RxdqsGatingPostProcess] freq 800
1430 19:25:29.594555 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1431 19:25:29.597772 Pre-setting of DQS Precalculation
1432 19:25:29.601166 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1433 19:25:29.601247 ==
1434 19:25:29.604412 Dram Type= 6, Freq= 0, CH_1, rank 0
1435 19:25:29.611310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1436 19:25:29.611392 ==
1437 19:25:29.614183 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1438 19:25:29.621055 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1439 19:25:29.630392 [CA 0] Center 37 (6~68) winsize 63
1440 19:25:29.633237 [CA 1] Center 37 (6~68) winsize 63
1441 19:25:29.636920 [CA 2] Center 35 (5~65) winsize 61
1442 19:25:29.639835 [CA 3] Center 34 (4~65) winsize 62
1443 19:25:29.643501 [CA 4] Center 34 (4~65) winsize 62
1444 19:25:29.646712 [CA 5] Center 34 (3~65) winsize 63
1445 19:25:29.646793
1446 19:25:29.650209 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1447 19:25:29.650291
1448 19:25:29.653412 [CATrainingPosCal] consider 1 rank data
1449 19:25:29.656709 u2DelayCellTimex100 = 270/100 ps
1450 19:25:29.660126 CA0 delay=37 (6~68),Diff = 3 PI (21 cell)
1451 19:25:29.666377 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1452 19:25:29.669916 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1453 19:25:29.673546 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1454 19:25:29.676828 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1455 19:25:29.679720 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1456 19:25:29.679802
1457 19:25:29.683375 CA PerBit enable=1, Macro0, CA PI delay=34
1458 19:25:29.683457
1459 19:25:29.686775 [CBTSetCACLKResult] CA Dly = 34
1460 19:25:29.686855 CS Dly: 4 (0~35)
1461 19:25:29.689591 ==
1462 19:25:29.693097 Dram Type= 6, Freq= 0, CH_1, rank 1
1463 19:25:29.696462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1464 19:25:29.696543 ==
1465 19:25:29.700053 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1466 19:25:29.706388 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1467 19:25:29.716394 [CA 0] Center 36 (6~67) winsize 62
1468 19:25:29.719728 [CA 1] Center 37 (6~68) winsize 63
1469 19:25:29.722624 [CA 2] Center 34 (4~65) winsize 62
1470 19:25:29.726213 [CA 3] Center 34 (3~65) winsize 63
1471 19:25:29.729937 [CA 4] Center 34 (3~65) winsize 63
1472 19:25:29.732666 [CA 5] Center 33 (3~64) winsize 62
1473 19:25:29.732747
1474 19:25:29.736196 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1475 19:25:29.736277
1476 19:25:29.739729 [CATrainingPosCal] consider 2 rank data
1477 19:25:29.742790 u2DelayCellTimex100 = 270/100 ps
1478 19:25:29.745944 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1479 19:25:29.749956 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1480 19:25:29.753565 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1481 19:25:29.757242 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1482 19:25:29.760980 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1483 19:25:29.764549 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1484 19:25:29.764633
1485 19:25:29.768523 CA PerBit enable=1, Macro0, CA PI delay=33
1486 19:25:29.768605
1487 19:25:29.772700 [CBTSetCACLKResult] CA Dly = 33
1488 19:25:29.776251 CS Dly: 5 (0~37)
1489 19:25:29.776332
1490 19:25:29.779603 ----->DramcWriteLeveling(PI) begin...
1491 19:25:29.779685 ==
1492 19:25:29.783221 Dram Type= 6, Freq= 0, CH_1, rank 0
1493 19:25:29.786184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1494 19:25:29.786280 ==
1495 19:25:29.789556 Write leveling (Byte 0): 25 => 25
1496 19:25:29.793070 Write leveling (Byte 1): 28 => 28
1497 19:25:29.796474 DramcWriteLeveling(PI) end<-----
1498 19:25:29.796555
1499 19:25:29.796619 ==
1500 19:25:29.799512 Dram Type= 6, Freq= 0, CH_1, rank 0
1501 19:25:29.803036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1502 19:25:29.803117 ==
1503 19:25:29.806457 [Gating] SW mode calibration
1504 19:25:29.813283 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1505 19:25:29.816703 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1506 19:25:29.822927 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1507 19:25:29.825952 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1508 19:25:29.829827 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 19:25:29.836690 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 19:25:29.839490 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 19:25:29.843070 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 19:25:29.849485 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 19:25:29.853309 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 19:25:29.856637 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 19:25:29.862803 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 19:25:29.865865 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 19:25:29.869441 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 19:25:29.876221 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 19:25:29.879158 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 19:25:29.882416 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 19:25:29.889395 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 19:25:29.892602 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1523 19:25:29.895647 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1524 19:25:29.902348 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 19:25:29.905924 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 19:25:29.909450 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 19:25:29.915740 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 19:25:29.919090 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 19:25:29.922116 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 19:25:29.929141 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 19:25:29.932440 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1532 19:25:29.935557 0 9 8 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
1533 19:25:29.942493 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1534 19:25:29.945908 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1535 19:25:29.948759 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1536 19:25:29.955284 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1537 19:25:29.958897 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1538 19:25:29.962011 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1539 19:25:29.968742 0 10 4 | B1->B0 | 3434 3131 | 0 0 | (0 0) (0 0)
1540 19:25:29.972213 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
1541 19:25:29.975309 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 19:25:29.982057 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 19:25:29.985043 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 19:25:29.988610 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 19:25:29.995124 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 19:25:29.998491 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 19:25:30.002151 0 11 4 | B1->B0 | 2525 2b2b | 0 1 | (1 1) (0 0)
1548 19:25:30.004930 0 11 8 | B1->B0 | 3f3f 4545 | 0 0 | (0 0) (0 0)
1549 19:25:30.011921 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1550 19:25:30.015344 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1551 19:25:30.018219 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1552 19:25:30.025100 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1553 19:25:30.028407 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1554 19:25:30.031733 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1555 19:25:30.038193 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1556 19:25:30.041516 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1557 19:25:30.045171 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1558 19:25:30.051574 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1559 19:25:30.054494 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1560 19:25:30.057937 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1561 19:25:30.064420 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 19:25:30.068386 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 19:25:30.071356 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 19:25:30.077778 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 19:25:30.081402 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 19:25:30.084449 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 19:25:30.090957 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 19:25:30.094536 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 19:25:30.097747 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 19:25:30.104678 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 19:25:30.108087 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1572 19:25:30.111584 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1573 19:25:30.114725 Total UI for P1: 0, mck2ui 16
1574 19:25:30.117918 best dqsien dly found for B0: ( 0, 14, 4)
1575 19:25:30.120933 Total UI for P1: 0, mck2ui 16
1576 19:25:30.124372 best dqsien dly found for B1: ( 0, 14, 4)
1577 19:25:30.127833 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1578 19:25:30.131280 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1579 19:25:30.131361
1580 19:25:30.137484 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1581 19:25:30.141042 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1582 19:25:30.141123 [Gating] SW calibration Done
1583 19:25:30.144622 ==
1584 19:25:30.144703 Dram Type= 6, Freq= 0, CH_1, rank 0
1585 19:25:30.150865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1586 19:25:30.150947 ==
1587 19:25:30.151011 RX Vref Scan: 0
1588 19:25:30.151072
1589 19:25:30.154384 RX Vref 0 -> 0, step: 1
1590 19:25:30.154465
1591 19:25:30.157867 RX Delay -130 -> 252, step: 16
1592 19:25:30.161015 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1593 19:25:30.164005 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1594 19:25:30.167554 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1595 19:25:30.174016 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1596 19:25:30.177497 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1597 19:25:30.180988 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1598 19:25:30.184012 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1599 19:25:30.187519 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1600 19:25:30.193979 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1601 19:25:30.197476 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1602 19:25:30.200665 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1603 19:25:30.203926 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1604 19:25:30.210750 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1605 19:25:30.213912 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1606 19:25:30.217575 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1607 19:25:30.220536 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1608 19:25:30.220638 ==
1609 19:25:30.223942 Dram Type= 6, Freq= 0, CH_1, rank 0
1610 19:25:30.227506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1611 19:25:30.230908 ==
1612 19:25:30.231031 DQS Delay:
1613 19:25:30.231127 DQS0 = 0, DQS1 = 0
1614 19:25:30.233694 DQM Delay:
1615 19:25:30.233815 DQM0 = 86, DQM1 = 80
1616 19:25:30.237413 DQ Delay:
1617 19:25:30.240766 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1618 19:25:30.240917 DQ4 =85, DQ5 =101, DQ6 =93, DQ7 =85
1619 19:25:30.243759 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1620 19:25:30.247488 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1621 19:25:30.250458
1622 19:25:30.250538
1623 19:25:30.250602 ==
1624 19:25:30.254019 Dram Type= 6, Freq= 0, CH_1, rank 0
1625 19:25:30.257721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1626 19:25:30.257827 ==
1627 19:25:30.257918
1628 19:25:30.258005
1629 19:25:30.260405 TX Vref Scan disable
1630 19:25:30.260489 == TX Byte 0 ==
1631 19:25:30.267242 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1632 19:25:30.270491 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1633 19:25:30.270595 == TX Byte 1 ==
1634 19:25:30.277513 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1635 19:25:30.280672 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1636 19:25:30.280778 ==
1637 19:25:30.284285 Dram Type= 6, Freq= 0, CH_1, rank 0
1638 19:25:30.287138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1639 19:25:30.287220 ==
1640 19:25:30.301225 TX Vref=22, minBit 2, minWin=27, winSum=440
1641 19:25:30.304463 TX Vref=24, minBit 2, minWin=27, winSum=446
1642 19:25:30.308079 TX Vref=26, minBit 2, minWin=27, winSum=452
1643 19:25:30.311009 TX Vref=28, minBit 5, minWin=27, winSum=455
1644 19:25:30.314470 TX Vref=30, minBit 0, minWin=28, winSum=457
1645 19:25:30.320628 TX Vref=32, minBit 0, minWin=27, winSum=451
1646 19:25:30.324215 [TxChooseVref] Worse bit 0, Min win 28, Win sum 457, Final Vref 30
1647 19:25:30.324295
1648 19:25:30.328048 Final TX Range 1 Vref 30
1649 19:25:30.328129
1650 19:25:30.328212 ==
1651 19:25:30.331700 Dram Type= 6, Freq= 0, CH_1, rank 0
1652 19:25:30.335138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1653 19:25:30.335216 ==
1654 19:25:30.335284
1655 19:25:30.335373
1656 19:25:30.338483 TX Vref Scan disable
1657 19:25:30.341466 == TX Byte 0 ==
1658 19:25:30.344959 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1659 19:25:30.348014 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1660 19:25:30.351820 == TX Byte 1 ==
1661 19:25:30.355240 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1662 19:25:30.358333 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1663 19:25:30.358445
1664 19:25:30.361329 [DATLAT]
1665 19:25:30.361428 Freq=800, CH1 RK0
1666 19:25:30.361522
1667 19:25:30.364734 DATLAT Default: 0xa
1668 19:25:30.364833 0, 0xFFFF, sum = 0
1669 19:25:30.367933 1, 0xFFFF, sum = 0
1670 19:25:30.368013 2, 0xFFFF, sum = 0
1671 19:25:30.372037 3, 0xFFFF, sum = 0
1672 19:25:30.372112 4, 0xFFFF, sum = 0
1673 19:25:30.375129 5, 0xFFFF, sum = 0
1674 19:25:30.375232 6, 0xFFFF, sum = 0
1675 19:25:30.377884 7, 0xFFFF, sum = 0
1676 19:25:30.377954 8, 0xFFFF, sum = 0
1677 19:25:30.381383 9, 0x0, sum = 1
1678 19:25:30.381454 10, 0x0, sum = 2
1679 19:25:30.384914 11, 0x0, sum = 3
1680 19:25:30.384985 12, 0x0, sum = 4
1681 19:25:30.388494 best_step = 10
1682 19:25:30.388563
1683 19:25:30.388621 ==
1684 19:25:30.391309 Dram Type= 6, Freq= 0, CH_1, rank 0
1685 19:25:30.394802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1686 19:25:30.394873 ==
1687 19:25:30.397781 RX Vref Scan: 1
1688 19:25:30.397855
1689 19:25:30.397917 Set Vref Range= 32 -> 127
1690 19:25:30.397975
1691 19:25:30.401350 RX Vref 32 -> 127, step: 1
1692 19:25:30.401421
1693 19:25:30.404906 RX Delay -95 -> 252, step: 8
1694 19:25:30.404975
1695 19:25:30.407624 Set Vref, RX VrefLevel [Byte0]: 32
1696 19:25:30.411011 [Byte1]: 32
1697 19:25:30.411085
1698 19:25:30.414602 Set Vref, RX VrefLevel [Byte0]: 33
1699 19:25:30.417768 [Byte1]: 33
1700 19:25:30.421198
1701 19:25:30.421278 Set Vref, RX VrefLevel [Byte0]: 34
1702 19:25:30.424746 [Byte1]: 34
1703 19:25:30.428954
1704 19:25:30.429074 Set Vref, RX VrefLevel [Byte0]: 35
1705 19:25:30.432460 [Byte1]: 35
1706 19:25:30.436543
1707 19:25:30.436661 Set Vref, RX VrefLevel [Byte0]: 36
1708 19:25:30.440012 [Byte1]: 36
1709 19:25:30.444113
1710 19:25:30.444194 Set Vref, RX VrefLevel [Byte0]: 37
1711 19:25:30.447233 [Byte1]: 37
1712 19:25:30.451505
1713 19:25:30.451586 Set Vref, RX VrefLevel [Byte0]: 38
1714 19:25:30.454984 [Byte1]: 38
1715 19:25:30.459066
1716 19:25:30.459147 Set Vref, RX VrefLevel [Byte0]: 39
1717 19:25:30.462634 [Byte1]: 39
1718 19:25:30.466711
1719 19:25:30.466794 Set Vref, RX VrefLevel [Byte0]: 40
1720 19:25:30.470442 [Byte1]: 40
1721 19:25:30.474333
1722 19:25:30.474449 Set Vref, RX VrefLevel [Byte0]: 41
1723 19:25:30.477855 [Byte1]: 41
1724 19:25:30.482398
1725 19:25:30.482482 Set Vref, RX VrefLevel [Byte0]: 42
1726 19:25:30.485265 [Byte1]: 42
1727 19:25:30.489422
1728 19:25:30.489504 Set Vref, RX VrefLevel [Byte0]: 43
1729 19:25:30.493192 [Byte1]: 43
1730 19:25:30.497268
1731 19:25:30.497357 Set Vref, RX VrefLevel [Byte0]: 44
1732 19:25:30.500769 [Byte1]: 44
1733 19:25:30.504727
1734 19:25:30.504803 Set Vref, RX VrefLevel [Byte0]: 45
1735 19:25:30.508304 [Byte1]: 45
1736 19:25:30.512460
1737 19:25:30.512538 Set Vref, RX VrefLevel [Byte0]: 46
1738 19:25:30.516000 [Byte1]: 46
1739 19:25:30.520004
1740 19:25:30.520085 Set Vref, RX VrefLevel [Byte0]: 47
1741 19:25:30.523385 [Byte1]: 47
1742 19:25:30.527364
1743 19:25:30.527446 Set Vref, RX VrefLevel [Byte0]: 48
1744 19:25:30.530812 [Byte1]: 48
1745 19:25:30.535003
1746 19:25:30.535087 Set Vref, RX VrefLevel [Byte0]: 49
1747 19:25:30.538591 [Byte1]: 49
1748 19:25:30.542748
1749 19:25:30.542848 Set Vref, RX VrefLevel [Byte0]: 50
1750 19:25:30.546673 [Byte1]: 50
1751 19:25:30.550177
1752 19:25:30.550275 Set Vref, RX VrefLevel [Byte0]: 51
1753 19:25:30.553559 [Byte1]: 51
1754 19:25:30.558410
1755 19:25:30.558522 Set Vref, RX VrefLevel [Byte0]: 52
1756 19:25:30.561406 [Byte1]: 52
1757 19:25:30.565533
1758 19:25:30.565609 Set Vref, RX VrefLevel [Byte0]: 53
1759 19:25:30.568928 [Byte1]: 53
1760 19:25:30.573079
1761 19:25:30.573161 Set Vref, RX VrefLevel [Byte0]: 54
1762 19:25:30.576492 [Byte1]: 54
1763 19:25:30.580913
1764 19:25:30.580989 Set Vref, RX VrefLevel [Byte0]: 55
1765 19:25:30.584689 [Byte1]: 55
1766 19:25:30.588739
1767 19:25:30.588817 Set Vref, RX VrefLevel [Byte0]: 56
1768 19:25:30.591821 [Byte1]: 56
1769 19:25:30.595847
1770 19:25:30.595939 Set Vref, RX VrefLevel [Byte0]: 57
1771 19:25:30.599844 [Byte1]: 57
1772 19:25:30.603652
1773 19:25:30.603724 Set Vref, RX VrefLevel [Byte0]: 58
1774 19:25:30.606648 [Byte1]: 58
1775 19:25:30.611427
1776 19:25:30.611500 Set Vref, RX VrefLevel [Byte0]: 59
1777 19:25:30.614947 [Byte1]: 59
1778 19:25:30.618918
1779 19:25:30.619014 Set Vref, RX VrefLevel [Byte0]: 60
1780 19:25:30.622103 [Byte1]: 60
1781 19:25:30.626518
1782 19:25:30.626599 Set Vref, RX VrefLevel [Byte0]: 61
1783 19:25:30.629908 [Byte1]: 61
1784 19:25:30.633827
1785 19:25:30.633903 Set Vref, RX VrefLevel [Byte0]: 62
1786 19:25:30.637251 [Byte1]: 62
1787 19:25:30.641483
1788 19:25:30.641556 Set Vref, RX VrefLevel [Byte0]: 63
1789 19:25:30.645015 [Byte1]: 63
1790 19:25:30.649185
1791 19:25:30.649255 Set Vref, RX VrefLevel [Byte0]: 64
1792 19:25:30.652843 [Byte1]: 64
1793 19:25:30.656794
1794 19:25:30.656872 Set Vref, RX VrefLevel [Byte0]: 65
1795 19:25:30.660212 [Byte1]: 65
1796 19:25:30.664233
1797 19:25:30.664304 Set Vref, RX VrefLevel [Byte0]: 66
1798 19:25:30.667544 [Byte1]: 66
1799 19:25:30.672386
1800 19:25:30.672502 Set Vref, RX VrefLevel [Byte0]: 67
1801 19:25:30.675281 [Byte1]: 67
1802 19:25:30.679472
1803 19:25:30.679570 Set Vref, RX VrefLevel [Byte0]: 68
1804 19:25:30.682992 [Byte1]: 68
1805 19:25:30.686921
1806 19:25:30.687006 Set Vref, RX VrefLevel [Byte0]: 69
1807 19:25:30.690225 [Byte1]: 69
1808 19:25:30.694786
1809 19:25:30.694898 Set Vref, RX VrefLevel [Byte0]: 70
1810 19:25:30.698152 [Byte1]: 70
1811 19:25:30.702664
1812 19:25:30.702770 Set Vref, RX VrefLevel [Byte0]: 71
1813 19:25:30.705467 [Byte1]: 71
1814 19:25:30.709792
1815 19:25:30.709872 Set Vref, RX VrefLevel [Byte0]: 72
1816 19:25:30.713423 [Byte1]: 72
1817 19:25:30.717480
1818 19:25:30.717586 Set Vref, RX VrefLevel [Byte0]: 73
1819 19:25:30.721044 [Byte1]: 73
1820 19:25:30.725510
1821 19:25:30.725590 Set Vref, RX VrefLevel [Byte0]: 74
1822 19:25:30.728294 [Byte1]: 74
1823 19:25:30.732827
1824 19:25:30.732934 Set Vref, RX VrefLevel [Byte0]: 75
1825 19:25:30.736283 [Byte1]: 75
1826 19:25:30.740265
1827 19:25:30.743353 Final RX Vref Byte 0 = 55 to rank0
1828 19:25:30.743442 Final RX Vref Byte 1 = 59 to rank0
1829 19:25:30.747318 Final RX Vref Byte 0 = 55 to rank1
1830 19:25:30.750236 Final RX Vref Byte 1 = 59 to rank1==
1831 19:25:30.753891 Dram Type= 6, Freq= 0, CH_1, rank 0
1832 19:25:30.760244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1833 19:25:30.760326 ==
1834 19:25:30.760390 DQS Delay:
1835 19:25:30.763246 DQS0 = 0, DQS1 = 0
1836 19:25:30.763326 DQM Delay:
1837 19:25:30.763389 DQM0 = 85, DQM1 = 79
1838 19:25:30.766702 DQ Delay:
1839 19:25:30.770296 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1840 19:25:30.773303 DQ4 =80, DQ5 =96, DQ6 =96, DQ7 =80
1841 19:25:30.776804 DQ8 =64, DQ9 =72, DQ10 =76, DQ11 =72
1842 19:25:30.780026 DQ12 =88, DQ13 =92, DQ14 =84, DQ15 =88
1843 19:25:30.780107
1844 19:25:30.780170
1845 19:25:30.786689 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a2d, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 403 ps
1846 19:25:30.789745 CH1 RK0: MR19=606, MR18=1A2D
1847 19:25:30.797032 CH1_RK0: MR19=0x606, MR18=0x1A2D, DQSOSC=398, MR23=63, INC=93, DEC=62
1848 19:25:30.797155
1849 19:25:30.799555 ----->DramcWriteLeveling(PI) begin...
1850 19:25:30.799643 ==
1851 19:25:30.802989 Dram Type= 6, Freq= 0, CH_1, rank 1
1852 19:25:30.806526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1853 19:25:30.806664 ==
1854 19:25:30.809343 Write leveling (Byte 0): 25 => 25
1855 19:25:30.813249 Write leveling (Byte 1): 30 => 30
1856 19:25:30.816457 DramcWriteLeveling(PI) end<-----
1857 19:25:30.816539
1858 19:25:30.816603 ==
1859 19:25:30.819789 Dram Type= 6, Freq= 0, CH_1, rank 1
1860 19:25:30.822857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1861 19:25:30.822955 ==
1862 19:25:30.826269 [Gating] SW mode calibration
1863 19:25:30.832878 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1864 19:25:30.839540 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1865 19:25:30.842853 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1866 19:25:30.849284 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1867 19:25:30.852617 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1868 19:25:30.855903 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 19:25:30.862328 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 19:25:30.865826 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 19:25:30.868978 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 19:25:30.875618 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 19:25:30.879135 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 19:25:30.882187 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 19:25:30.889141 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 19:25:30.891989 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 19:25:30.895501 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 19:25:30.902352 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 19:25:30.905785 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 19:25:30.908747 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 19:25:30.915584 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1882 19:25:30.918882 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1883 19:25:30.922134 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 19:25:30.928449 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 19:25:30.931812 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 19:25:30.935313 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 19:25:30.941684 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 19:25:30.944896 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 19:25:30.948227 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 19:25:30.954848 0 9 4 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)
1891 19:25:30.958358 0 9 8 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
1892 19:25:30.961773 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1893 19:25:30.968325 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1894 19:25:30.971769 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1895 19:25:30.974811 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1896 19:25:30.981624 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1897 19:25:30.984601 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1898 19:25:30.988311 0 10 4 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (1 0)
1899 19:25:30.991513 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1900 19:25:30.998491 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 19:25:31.001397 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 19:25:31.004829 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 19:25:31.011634 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 19:25:31.015004 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 19:25:31.018441 0 11 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1906 19:25:31.024861 0 11 4 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
1907 19:25:31.027914 0 11 8 | B1->B0 | 3b3b 4646 | 1 0 | (0 0) (0 0)
1908 19:25:31.031313 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1909 19:25:31.037914 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1910 19:25:31.041189 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1911 19:25:31.044849 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1912 19:25:31.051276 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1913 19:25:31.054614 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1914 19:25:31.058071 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1915 19:25:31.064424 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1916 19:25:31.067873 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 19:25:31.071793 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 19:25:31.078158 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 19:25:31.081602 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 19:25:31.084410 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 19:25:31.091313 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 19:25:31.094323 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 19:25:31.097808 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 19:25:31.104700 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 19:25:31.107513 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 19:25:31.110917 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 19:25:31.117893 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 19:25:31.120836 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 19:25:31.124605 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1930 19:25:31.130801 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1931 19:25:31.130881 Total UI for P1: 0, mck2ui 16
1932 19:25:31.134081 best dqsien dly found for B0: ( 0, 14, 0)
1933 19:25:31.140589 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1934 19:25:31.143849 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1935 19:25:31.147511 Total UI for P1: 0, mck2ui 16
1936 19:25:31.150861 best dqsien dly found for B1: ( 0, 14, 6)
1937 19:25:31.154263 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1938 19:25:31.157191 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1939 19:25:31.157271
1940 19:25:31.160901 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1941 19:25:31.163836 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1942 19:25:31.167749 [Gating] SW calibration Done
1943 19:25:31.167847 ==
1944 19:25:31.170856 Dram Type= 6, Freq= 0, CH_1, rank 1
1945 19:25:31.177377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1946 19:25:31.177458 ==
1947 19:25:31.177522 RX Vref Scan: 0
1948 19:25:31.177582
1949 19:25:31.180992 RX Vref 0 -> 0, step: 1
1950 19:25:31.181072
1951 19:25:31.183825 RX Delay -130 -> 252, step: 16
1952 19:25:31.187447 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1953 19:25:31.190373 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1954 19:25:31.194161 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1955 19:25:31.200217 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1956 19:25:31.203704 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1957 19:25:31.206865 iDelay=206, Bit 5, Center 85 (-34 ~ 205) 240
1958 19:25:31.210405 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1959 19:25:31.213380 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1960 19:25:31.220366 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1961 19:25:31.223669 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1962 19:25:31.227276 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1963 19:25:31.230222 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1964 19:25:31.233221 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1965 19:25:31.240126 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1966 19:25:31.243630 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1967 19:25:31.247267 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1968 19:25:31.247348 ==
1969 19:25:31.250056 Dram Type= 6, Freq= 0, CH_1, rank 1
1970 19:25:31.253504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1971 19:25:31.253584 ==
1972 19:25:31.256672 DQS Delay:
1973 19:25:31.256752 DQS0 = 0, DQS1 = 0
1974 19:25:31.259829 DQM Delay:
1975 19:25:31.259943 DQM0 = 83, DQM1 = 79
1976 19:25:31.260007 DQ Delay:
1977 19:25:31.263429 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1978 19:25:31.266582 DQ4 =85, DQ5 =85, DQ6 =85, DQ7 =85
1979 19:25:31.269904 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1980 19:25:31.273398 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1981 19:25:31.273478
1982 19:25:31.273542
1983 19:25:31.276746 ==
1984 19:25:31.280325 Dram Type= 6, Freq= 0, CH_1, rank 1
1985 19:25:31.283511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1986 19:25:31.283591 ==
1987 19:25:31.283655
1988 19:25:31.283715
1989 19:25:31.286817 TX Vref Scan disable
1990 19:25:31.286897 == TX Byte 0 ==
1991 19:25:31.293236 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1992 19:25:31.296528 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1993 19:25:31.296608 == TX Byte 1 ==
1994 19:25:31.303188 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1995 19:25:31.306306 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1996 19:25:31.306386 ==
1997 19:25:31.309507 Dram Type= 6, Freq= 0, CH_1, rank 1
1998 19:25:31.313231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1999 19:25:31.313312 ==
2000 19:25:31.327077 TX Vref=22, minBit 1, minWin=27, winSum=448
2001 19:25:31.330480 TX Vref=24, minBit 1, minWin=27, winSum=449
2002 19:25:31.333988 TX Vref=26, minBit 4, minWin=27, winSum=452
2003 19:25:31.336944 TX Vref=28, minBit 1, minWin=27, winSum=455
2004 19:25:31.340378 TX Vref=30, minBit 2, minWin=27, winSum=452
2005 19:25:31.346795 TX Vref=32, minBit 5, minWin=27, winSum=454
2006 19:25:31.350223 [TxChooseVref] Worse bit 1, Min win 27, Win sum 455, Final Vref 28
2007 19:25:31.350305
2008 19:25:31.353580 Final TX Range 1 Vref 28
2009 19:25:31.353661
2010 19:25:31.353725 ==
2011 19:25:31.356669 Dram Type= 6, Freq= 0, CH_1, rank 1
2012 19:25:31.360660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2013 19:25:31.360771 ==
2014 19:25:31.363170
2015 19:25:31.363250
2016 19:25:31.363314 TX Vref Scan disable
2017 19:25:31.367386 == TX Byte 0 ==
2018 19:25:31.370374 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
2019 19:25:31.376765 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
2020 19:25:31.376846 == TX Byte 1 ==
2021 19:25:31.380256 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2022 19:25:31.386989 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2023 19:25:31.387092
2024 19:25:31.387189 [DATLAT]
2025 19:25:31.387278 Freq=800, CH1 RK1
2026 19:25:31.387368
2027 19:25:31.390329 DATLAT Default: 0xa
2028 19:25:31.390410 0, 0xFFFF, sum = 0
2029 19:25:31.393708 1, 0xFFFF, sum = 0
2030 19:25:31.393780 2, 0xFFFF, sum = 0
2031 19:25:31.396596 3, 0xFFFF, sum = 0
2032 19:25:31.400323 4, 0xFFFF, sum = 0
2033 19:25:31.400402 5, 0xFFFF, sum = 0
2034 19:25:31.403276 6, 0xFFFF, sum = 0
2035 19:25:31.403349 7, 0xFFFF, sum = 0
2036 19:25:31.407025 8, 0xFFFF, sum = 0
2037 19:25:31.407110 9, 0x0, sum = 1
2038 19:25:31.410145 10, 0x0, sum = 2
2039 19:25:31.410220 11, 0x0, sum = 3
2040 19:25:31.410281 12, 0x0, sum = 4
2041 19:25:31.413217 best_step = 10
2042 19:25:31.413287
2043 19:25:31.413350 ==
2044 19:25:31.416909 Dram Type= 6, Freq= 0, CH_1, rank 1
2045 19:25:31.420017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2046 19:25:31.420089 ==
2047 19:25:31.423550 RX Vref Scan: 0
2048 19:25:31.423624
2049 19:25:31.423684 RX Vref 0 -> 0, step: 1
2050 19:25:31.426483
2051 19:25:31.426551 RX Delay -95 -> 252, step: 8
2052 19:25:31.433934 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
2053 19:25:31.437096 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
2054 19:25:31.440420 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
2055 19:25:31.443408 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
2056 19:25:31.446873 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
2057 19:25:31.453815 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
2058 19:25:31.456826 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
2059 19:25:31.460244 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
2060 19:25:31.463657 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
2061 19:25:31.466570 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2062 19:25:31.473716 iDelay=209, Bit 10, Center 84 (-31 ~ 200) 232
2063 19:25:31.476842 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
2064 19:25:31.480463 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
2065 19:25:31.483334 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2066 19:25:31.489955 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2067 19:25:31.493553 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2068 19:25:31.493625 ==
2069 19:25:31.496919 Dram Type= 6, Freq= 0, CH_1, rank 1
2070 19:25:31.499777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2071 19:25:31.499851 ==
2072 19:25:31.499927 DQS Delay:
2073 19:25:31.503557 DQS0 = 0, DQS1 = 0
2074 19:25:31.503627 DQM Delay:
2075 19:25:31.506517 DQM0 = 87, DQM1 = 82
2076 19:25:31.506591 DQ Delay:
2077 19:25:31.509737 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =84
2078 19:25:31.513065 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
2079 19:25:31.516463 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =76
2080 19:25:31.520016 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
2081 19:25:31.520094
2082 19:25:31.520156
2083 19:25:31.529975 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c36, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 402 ps
2084 19:25:31.530057 CH1 RK1: MR19=606, MR18=1C36
2085 19:25:31.536342 CH1_RK1: MR19=0x606, MR18=0x1C36, DQSOSC=396, MR23=63, INC=94, DEC=62
2086 19:25:31.540183 [RxdqsGatingPostProcess] freq 800
2087 19:25:31.546638 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2088 19:25:31.549677 Pre-setting of DQS Precalculation
2089 19:25:31.553275 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2090 19:25:31.559822 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2091 19:25:31.570138 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2092 19:25:31.570224
2093 19:25:31.570291
2094 19:25:31.570351 [Calibration Summary] 1600 Mbps
2095 19:25:31.573046 CH 0, Rank 0
2096 19:25:31.573120 SW Impedance : PASS
2097 19:25:31.576599 DUTY Scan : NO K
2098 19:25:31.579689 ZQ Calibration : PASS
2099 19:25:31.579764 Jitter Meter : NO K
2100 19:25:31.583148 CBT Training : PASS
2101 19:25:31.586479 Write leveling : PASS
2102 19:25:31.586550 RX DQS gating : PASS
2103 19:25:31.589430 RX DQ/DQS(RDDQC) : PASS
2104 19:25:31.593066 TX DQ/DQS : PASS
2105 19:25:31.593138 RX DATLAT : PASS
2106 19:25:31.596584 RX DQ/DQS(Engine): PASS
2107 19:25:31.599688 TX OE : NO K
2108 19:25:31.599762 All Pass.
2109 19:25:31.599822
2110 19:25:31.599879 CH 0, Rank 1
2111 19:25:31.603305 SW Impedance : PASS
2112 19:25:31.606157 DUTY Scan : NO K
2113 19:25:31.606233 ZQ Calibration : PASS
2114 19:25:31.609849 Jitter Meter : NO K
2115 19:25:31.612774 CBT Training : PASS
2116 19:25:31.612846 Write leveling : PASS
2117 19:25:31.616010 RX DQS gating : PASS
2118 19:25:31.619623 RX DQ/DQS(RDDQC) : PASS
2119 19:25:31.619695 TX DQ/DQS : PASS
2120 19:25:31.623275 RX DATLAT : PASS
2121 19:25:31.623349 RX DQ/DQS(Engine): PASS
2122 19:25:31.626103 TX OE : NO K
2123 19:25:31.626175 All Pass.
2124 19:25:31.626235
2125 19:25:31.629346 CH 1, Rank 0
2126 19:25:31.629418 SW Impedance : PASS
2127 19:25:31.632896 DUTY Scan : NO K
2128 19:25:31.635863 ZQ Calibration : PASS
2129 19:25:31.635985 Jitter Meter : NO K
2130 19:25:31.639406 CBT Training : PASS
2131 19:25:31.642849 Write leveling : PASS
2132 19:25:31.642925 RX DQS gating : PASS
2133 19:25:31.646195 RX DQ/DQS(RDDQC) : PASS
2134 19:25:31.649010 TX DQ/DQS : PASS
2135 19:25:31.649088 RX DATLAT : PASS
2136 19:25:31.652904 RX DQ/DQS(Engine): PASS
2137 19:25:31.656009 TX OE : NO K
2138 19:25:31.656085 All Pass.
2139 19:25:31.656146
2140 19:25:31.656204 CH 1, Rank 1
2141 19:25:31.659495 SW Impedance : PASS
2142 19:25:31.662522 DUTY Scan : NO K
2143 19:25:31.662592 ZQ Calibration : PASS
2144 19:25:31.665916 Jitter Meter : NO K
2145 19:25:31.669303 CBT Training : PASS
2146 19:25:31.669381 Write leveling : PASS
2147 19:25:31.672494 RX DQS gating : PASS
2148 19:25:31.675645 RX DQ/DQS(RDDQC) : PASS
2149 19:25:31.675720 TX DQ/DQS : PASS
2150 19:25:31.678985 RX DATLAT : PASS
2151 19:25:31.682547 RX DQ/DQS(Engine): PASS
2152 19:25:31.682623 TX OE : NO K
2153 19:25:31.682685 All Pass.
2154 19:25:31.682744
2155 19:25:31.685439 DramC Write-DBI off
2156 19:25:31.689127 PER_BANK_REFRESH: Hybrid Mode
2157 19:25:31.689199 TX_TRACKING: ON
2158 19:25:31.692544 [GetDramInforAfterCalByMRR] Vendor 6.
2159 19:25:31.695713 [GetDramInforAfterCalByMRR] Revision 606.
2160 19:25:31.702395 [GetDramInforAfterCalByMRR] Revision 2 0.
2161 19:25:31.702474 MR0 0x3b3b
2162 19:25:31.702539 MR8 0x5151
2163 19:25:31.705617 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2164 19:25:31.705692
2165 19:25:31.708989 MR0 0x3b3b
2166 19:25:31.709072 MR8 0x5151
2167 19:25:31.712500 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2168 19:25:31.712581
2169 19:25:31.722457 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2170 19:25:31.725261 [FAST_K] Save calibration result to emmc
2171 19:25:31.728707 [FAST_K] Save calibration result to emmc
2172 19:25:31.732128 dram_init: config_dvfs: 1
2173 19:25:31.735436 dramc_set_vcore_voltage set vcore to 662500
2174 19:25:31.738572 Read voltage for 1200, 2
2175 19:25:31.738676 Vio18 = 0
2176 19:25:31.738775 Vcore = 662500
2177 19:25:31.742069 Vdram = 0
2178 19:25:31.742151 Vddq = 0
2179 19:25:31.742215 Vmddr = 0
2180 19:25:31.748556 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2181 19:25:31.752003 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2182 19:25:31.755262 MEM_TYPE=3, freq_sel=15
2183 19:25:31.758605 sv_algorithm_assistance_LP4_1600
2184 19:25:31.762176 ============ PULL DRAM RESETB DOWN ============
2185 19:25:31.765151 ========== PULL DRAM RESETB DOWN end =========
2186 19:25:31.771869 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2187 19:25:31.775350 ===================================
2188 19:25:31.775426 LPDDR4 DRAM CONFIGURATION
2189 19:25:31.778446 ===================================
2190 19:25:31.781809 EX_ROW_EN[0] = 0x0
2191 19:25:31.785059 EX_ROW_EN[1] = 0x0
2192 19:25:31.785134 LP4Y_EN = 0x0
2193 19:25:31.788212 WORK_FSP = 0x0
2194 19:25:31.788286 WL = 0x4
2195 19:25:31.791740 RL = 0x4
2196 19:25:31.791815 BL = 0x2
2197 19:25:31.795472 RPST = 0x0
2198 19:25:31.795544 RD_PRE = 0x0
2199 19:25:31.798657 WR_PRE = 0x1
2200 19:25:31.798728 WR_PST = 0x0
2201 19:25:31.801587 DBI_WR = 0x0
2202 19:25:31.801657 DBI_RD = 0x0
2203 19:25:31.805000 OTF = 0x1
2204 19:25:31.808145 ===================================
2205 19:25:31.811340 ===================================
2206 19:25:31.811412 ANA top config
2207 19:25:31.814587 ===================================
2208 19:25:31.818088 DLL_ASYNC_EN = 0
2209 19:25:31.821607 ALL_SLAVE_EN = 0
2210 19:25:31.825009 NEW_RANK_MODE = 1
2211 19:25:31.825083 DLL_IDLE_MODE = 1
2212 19:25:31.828373 LP45_APHY_COMB_EN = 1
2213 19:25:31.831460 TX_ODT_DIS = 1
2214 19:25:31.834657 NEW_8X_MODE = 1
2215 19:25:31.838478 ===================================
2216 19:25:31.841611 ===================================
2217 19:25:31.844998 data_rate = 2400
2218 19:25:31.845073 CKR = 1
2219 19:25:31.848261 DQ_P2S_RATIO = 8
2220 19:25:31.851554 ===================================
2221 19:25:31.855156 CA_P2S_RATIO = 8
2222 19:25:31.858292 DQ_CA_OPEN = 0
2223 19:25:31.861364 DQ_SEMI_OPEN = 0
2224 19:25:31.864694 CA_SEMI_OPEN = 0
2225 19:25:31.864769 CA_FULL_RATE = 0
2226 19:25:31.868150 DQ_CKDIV4_EN = 0
2227 19:25:31.871740 CA_CKDIV4_EN = 0
2228 19:25:31.874636 CA_PREDIV_EN = 0
2229 19:25:31.878740 PH8_DLY = 17
2230 19:25:31.878848 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2231 19:25:31.881648 DQ_AAMCK_DIV = 4
2232 19:25:31.884554 CA_AAMCK_DIV = 4
2233 19:25:31.888023 CA_ADMCK_DIV = 4
2234 19:25:31.891523 DQ_TRACK_CA_EN = 0
2235 19:25:31.894303 CA_PICK = 1200
2236 19:25:31.898222 CA_MCKIO = 1200
2237 19:25:31.898329 MCKIO_SEMI = 0
2238 19:25:31.901302 PLL_FREQ = 2366
2239 19:25:31.904401 DQ_UI_PI_RATIO = 32
2240 19:25:31.908078 CA_UI_PI_RATIO = 0
2241 19:25:31.910813 ===================================
2242 19:25:31.914491 ===================================
2243 19:25:31.918049 memory_type:LPDDR4
2244 19:25:31.918146 GP_NUM : 10
2245 19:25:31.921030 SRAM_EN : 1
2246 19:25:31.924490 MD32_EN : 0
2247 19:25:31.927836 ===================================
2248 19:25:31.927948 [ANA_INIT] >>>>>>>>>>>>>>
2249 19:25:31.930788 <<<<<< [CONFIGURE PHASE]: ANA_TX
2250 19:25:31.934518 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2251 19:25:31.937816 ===================================
2252 19:25:31.940849 data_rate = 2400,PCW = 0X5b00
2253 19:25:31.944223 ===================================
2254 19:25:31.947563 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2255 19:25:31.954404 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2256 19:25:31.957924 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2257 19:25:31.964156 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2258 19:25:31.967658 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2259 19:25:31.970915 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2260 19:25:31.973885 [ANA_INIT] flow start
2261 19:25:31.973966 [ANA_INIT] PLL >>>>>>>>
2262 19:25:31.977433 [ANA_INIT] PLL <<<<<<<<
2263 19:25:31.981063 [ANA_INIT] MIDPI >>>>>>>>
2264 19:25:31.981144 [ANA_INIT] MIDPI <<<<<<<<
2265 19:25:31.983891 [ANA_INIT] DLL >>>>>>>>
2266 19:25:31.987616 [ANA_INIT] DLL <<<<<<<<
2267 19:25:31.987731 [ANA_INIT] flow end
2268 19:25:31.993978 ============ LP4 DIFF to SE enter ============
2269 19:25:31.996968 ============ LP4 DIFF to SE exit ============
2270 19:25:31.997041 [ANA_INIT] <<<<<<<<<<<<<
2271 19:25:32.000547 [Flow] Enable top DCM control >>>>>
2272 19:25:32.003574 [Flow] Enable top DCM control <<<<<
2273 19:25:32.007061 Enable DLL master slave shuffle
2274 19:25:32.014358 ==============================================================
2275 19:25:32.017340 Gating Mode config
2276 19:25:32.020262 ==============================================================
2277 19:25:32.023547 Config description:
2278 19:25:32.034246 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2279 19:25:32.040319 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2280 19:25:32.043352 SELPH_MODE 0: By rank 1: By Phase
2281 19:25:32.050119 ==============================================================
2282 19:25:32.053587 GAT_TRACK_EN = 1
2283 19:25:32.056614 RX_GATING_MODE = 2
2284 19:25:32.059961 RX_GATING_TRACK_MODE = 2
2285 19:25:32.063565 SELPH_MODE = 1
2286 19:25:32.063671 PICG_EARLY_EN = 1
2287 19:25:32.066865 VALID_LAT_VALUE = 1
2288 19:25:32.073052 ==============================================================
2289 19:25:32.076492 Enter into Gating configuration >>>>
2290 19:25:32.079864 Exit from Gating configuration <<<<
2291 19:25:32.083573 Enter into DVFS_PRE_config >>>>>
2292 19:25:32.092894 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2293 19:25:32.096332 Exit from DVFS_PRE_config <<<<<
2294 19:25:32.099788 Enter into PICG configuration >>>>
2295 19:25:32.102880 Exit from PICG configuration <<<<
2296 19:25:32.106430 [RX_INPUT] configuration >>>>>
2297 19:25:32.109834 [RX_INPUT] configuration <<<<<
2298 19:25:32.113420 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2299 19:25:32.119321 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2300 19:25:32.126043 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2301 19:25:32.132962 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2302 19:25:32.139464 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2303 19:25:32.142721 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2304 19:25:32.149283 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2305 19:25:32.152556 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2306 19:25:32.155948 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2307 19:25:32.159155 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2308 19:25:32.166027 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2309 19:25:32.169087 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2310 19:25:32.172729 ===================================
2311 19:25:32.175620 LPDDR4 DRAM CONFIGURATION
2312 19:25:32.179183 ===================================
2313 19:25:32.179258 EX_ROW_EN[0] = 0x0
2314 19:25:32.182091 EX_ROW_EN[1] = 0x0
2315 19:25:32.182170 LP4Y_EN = 0x0
2316 19:25:32.185756 WORK_FSP = 0x0
2317 19:25:32.185831 WL = 0x4
2318 19:25:32.189208 RL = 0x4
2319 19:25:32.192177 BL = 0x2
2320 19:25:32.192254 RPST = 0x0
2321 19:25:32.196133 RD_PRE = 0x0
2322 19:25:32.196204 WR_PRE = 0x1
2323 19:25:32.198969 WR_PST = 0x0
2324 19:25:32.199044 DBI_WR = 0x0
2325 19:25:32.202576 DBI_RD = 0x0
2326 19:25:32.202643 OTF = 0x1
2327 19:25:32.205445 ===================================
2328 19:25:32.209462 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2329 19:25:32.215613 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2330 19:25:32.219254 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2331 19:25:32.222206 ===================================
2332 19:25:32.225667 LPDDR4 DRAM CONFIGURATION
2333 19:25:32.228761 ===================================
2334 19:25:32.228832 EX_ROW_EN[0] = 0x10
2335 19:25:32.232233 EX_ROW_EN[1] = 0x0
2336 19:25:32.232303 LP4Y_EN = 0x0
2337 19:25:32.235661 WORK_FSP = 0x0
2338 19:25:32.235731 WL = 0x4
2339 19:25:32.238759 RL = 0x4
2340 19:25:32.238825 BL = 0x2
2341 19:25:32.241993 RPST = 0x0
2342 19:25:32.242068 RD_PRE = 0x0
2343 19:25:32.245443 WR_PRE = 0x1
2344 19:25:32.245524 WR_PST = 0x0
2345 19:25:32.248865 DBI_WR = 0x0
2346 19:25:32.252368 DBI_RD = 0x0
2347 19:25:32.252442 OTF = 0x1
2348 19:25:32.255587 ===================================
2349 19:25:32.262791 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2350 19:25:32.262866 ==
2351 19:25:32.265345 Dram Type= 6, Freq= 0, CH_0, rank 0
2352 19:25:32.269134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2353 19:25:32.269216 ==
2354 19:25:32.272293 [Duty_Offset_Calibration]
2355 19:25:32.272373 B0:2 B1:0 CA:4
2356 19:25:32.272435
2357 19:25:32.275357 [DutyScan_Calibration_Flow] k_type=0
2358 19:25:32.285148
2359 19:25:32.285228 ==CLK 0==
2360 19:25:32.288742 Final CLK duty delay cell = -4
2361 19:25:32.292325 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2362 19:25:32.295542 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2363 19:25:32.298321 [-4] AVG Duty = 4937%(X100)
2364 19:25:32.298425
2365 19:25:32.301865 CH0 CLK Duty spec in!! Max-Min= 187%
2366 19:25:32.305262 [DutyScan_Calibration_Flow] ====Done====
2367 19:25:32.305369
2368 19:25:32.308604 [DutyScan_Calibration_Flow] k_type=1
2369 19:25:32.324985
2370 19:25:32.325147 ==DQS 0 ==
2371 19:25:32.328171 Final DQS duty delay cell = 0
2372 19:25:32.331781 [0] MAX Duty = 5156%(X100), DQS PI = 18
2373 19:25:32.335416 [0] MIN Duty = 5093%(X100), DQS PI = 0
2374 19:25:32.335489 [0] AVG Duty = 5124%(X100)
2375 19:25:32.338634
2376 19:25:32.338706 ==DQS 1 ==
2377 19:25:32.341740 Final DQS duty delay cell = 0
2378 19:25:32.344875 [0] MAX Duty = 5125%(X100), DQS PI = 50
2379 19:25:32.348298 [0] MIN Duty = 4969%(X100), DQS PI = 16
2380 19:25:32.351510 [0] AVG Duty = 5047%(X100)
2381 19:25:32.351589
2382 19:25:32.354777 CH0 DQS 0 Duty spec in!! Max-Min= 63%
2383 19:25:32.354853
2384 19:25:32.358273 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2385 19:25:32.361830 [DutyScan_Calibration_Flow] ====Done====
2386 19:25:32.361907
2387 19:25:32.364720 [DutyScan_Calibration_Flow] k_type=3
2388 19:25:32.381267
2389 19:25:32.381357 ==DQM 0 ==
2390 19:25:32.384589 Final DQM duty delay cell = 0
2391 19:25:32.388397 [0] MAX Duty = 5125%(X100), DQS PI = 20
2392 19:25:32.391413 [0] MIN Duty = 4844%(X100), DQS PI = 50
2393 19:25:32.394581 [0] AVG Duty = 4984%(X100)
2394 19:25:32.394672
2395 19:25:32.394741 ==DQM 1 ==
2396 19:25:32.398381 Final DQM duty delay cell = 0
2397 19:25:32.401464 [0] MAX Duty = 4969%(X100), DQS PI = 4
2398 19:25:32.404461 [0] MIN Duty = 4875%(X100), DQS PI = 20
2399 19:25:32.407637 [0] AVG Duty = 4922%(X100)
2400 19:25:32.407737
2401 19:25:32.411282 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2402 19:25:32.411367
2403 19:25:32.414361 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2404 19:25:32.417884 [DutyScan_Calibration_Flow] ====Done====
2405 19:25:32.417961
2406 19:25:32.421192 [DutyScan_Calibration_Flow] k_type=2
2407 19:25:32.437757
2408 19:25:32.437833 ==DQ 0 ==
2409 19:25:32.441085 Final DQ duty delay cell = 0
2410 19:25:32.445023 [0] MAX Duty = 5156%(X100), DQS PI = 18
2411 19:25:32.447606 [0] MIN Duty = 4969%(X100), DQS PI = 52
2412 19:25:32.447674 [0] AVG Duty = 5062%(X100)
2413 19:25:32.451230
2414 19:25:32.451297 ==DQ 1 ==
2415 19:25:32.454421 Final DQ duty delay cell = 0
2416 19:25:32.457568 [0] MAX Duty = 5125%(X100), DQS PI = 4
2417 19:25:32.461202 [0] MIN Duty = 4938%(X100), DQS PI = 14
2418 19:25:32.461280 [0] AVG Duty = 5031%(X100)
2419 19:25:32.461343
2420 19:25:32.464433 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2421 19:25:32.467697
2422 19:25:32.471179 CH0 DQ 1 Duty spec in!! Max-Min= 187%
2423 19:25:32.474208 [DutyScan_Calibration_Flow] ====Done====
2424 19:25:32.474307 ==
2425 19:25:32.477592 Dram Type= 6, Freq= 0, CH_1, rank 0
2426 19:25:32.481501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2427 19:25:32.481606 ==
2428 19:25:32.483960 [Duty_Offset_Calibration]
2429 19:25:32.484034 B0:0 B1:-1 CA:3
2430 19:25:32.484096
2431 19:25:32.487699 [DutyScan_Calibration_Flow] k_type=0
2432 19:25:32.497172
2433 19:25:32.497295 ==CLK 0==
2434 19:25:32.500298 Final CLK duty delay cell = -4
2435 19:25:32.503414 [-4] MAX Duty = 5031%(X100), DQS PI = 32
2436 19:25:32.507227 [-4] MIN Duty = 4844%(X100), DQS PI = 4
2437 19:25:32.510401 [-4] AVG Duty = 4937%(X100)
2438 19:25:32.510501
2439 19:25:32.513590 CH1 CLK Duty spec in!! Max-Min= 187%
2440 19:25:32.516616 [DutyScan_Calibration_Flow] ====Done====
2441 19:25:32.516692
2442 19:25:32.520011 [DutyScan_Calibration_Flow] k_type=1
2443 19:25:32.536663
2444 19:25:32.536768 ==DQS 0 ==
2445 19:25:32.539675 Final DQS duty delay cell = 0
2446 19:25:32.543272 [0] MAX Duty = 5187%(X100), DQS PI = 50
2447 19:25:32.546748 [0] MIN Duty = 4907%(X100), DQS PI = 6
2448 19:25:32.549661 [0] AVG Duty = 5047%(X100)
2449 19:25:32.549741
2450 19:25:32.549803 ==DQS 1 ==
2451 19:25:32.552916 Final DQS duty delay cell = 0
2452 19:25:32.556597 [0] MAX Duty = 5156%(X100), DQS PI = 26
2453 19:25:32.559773 [0] MIN Duty = 5000%(X100), DQS PI = 58
2454 19:25:32.563254 [0] AVG Duty = 5078%(X100)
2455 19:25:32.563366
2456 19:25:32.566196 CH1 DQS 0 Duty spec in!! Max-Min= 280%
2457 19:25:32.566294
2458 19:25:32.569652 CH1 DQS 1 Duty spec in!! Max-Min= 156%
2459 19:25:32.572740 [DutyScan_Calibration_Flow] ====Done====
2460 19:25:32.572820
2461 19:25:32.576105 [DutyScan_Calibration_Flow] k_type=3
2462 19:25:32.594133
2463 19:25:32.594208 ==DQM 0 ==
2464 19:25:32.596987 Final DQM duty delay cell = 0
2465 19:25:32.600491 [0] MAX Duty = 5031%(X100), DQS PI = 60
2466 19:25:32.603952 [0] MIN Duty = 4813%(X100), DQS PI = 6
2467 19:25:32.607405 [0] AVG Duty = 4922%(X100)
2468 19:25:32.607478
2469 19:25:32.607539 ==DQM 1 ==
2470 19:25:32.610675 Final DQM duty delay cell = 4
2471 19:25:32.613565 [4] MAX Duty = 5187%(X100), DQS PI = 16
2472 19:25:32.617192 [4] MIN Duty = 5062%(X100), DQS PI = 50
2473 19:25:32.620255 [4] AVG Duty = 5124%(X100)
2474 19:25:32.620323
2475 19:25:32.623729 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2476 19:25:32.623821
2477 19:25:32.626625 CH1 DQM 1 Duty spec in!! Max-Min= 125%
2478 19:25:32.629878 [DutyScan_Calibration_Flow] ====Done====
2479 19:25:32.629951
2480 19:25:32.633172 [DutyScan_Calibration_Flow] k_type=2
2481 19:25:32.649708
2482 19:25:32.649782 ==DQ 0 ==
2483 19:25:32.652599 Final DQ duty delay cell = -4
2484 19:25:32.656150 [-4] MAX Duty = 5031%(X100), DQS PI = 30
2485 19:25:32.659764 [-4] MIN Duty = 4813%(X100), DQS PI = 4
2486 19:25:32.662793 [-4] AVG Duty = 4922%(X100)
2487 19:25:32.662866
2488 19:25:32.662926 ==DQ 1 ==
2489 19:25:32.666331 Final DQ duty delay cell = 0
2490 19:25:32.669488 [0] MAX Duty = 5031%(X100), DQS PI = 2
2491 19:25:32.672688 [0] MIN Duty = 4844%(X100), DQS PI = 30
2492 19:25:32.672764 [0] AVG Duty = 4937%(X100)
2493 19:25:32.676139
2494 19:25:32.679212 CH1 DQ 0 Duty spec in!! Max-Min= 218%
2495 19:25:32.679280
2496 19:25:32.682872 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2497 19:25:32.686055 [DutyScan_Calibration_Flow] ====Done====
2498 19:25:32.689325 nWR fixed to 30
2499 19:25:32.689398 [ModeRegInit_LP4] CH0 RK0
2500 19:25:32.692957 [ModeRegInit_LP4] CH0 RK1
2501 19:25:32.696531 [ModeRegInit_LP4] CH1 RK0
2502 19:25:32.699441 [ModeRegInit_LP4] CH1 RK1
2503 19:25:32.699514 match AC timing 7
2504 19:25:32.702894 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2505 19:25:32.709246 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2506 19:25:32.713045 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2507 19:25:32.716398 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2508 19:25:32.723214 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2509 19:25:32.723287 ==
2510 19:25:32.726388 Dram Type= 6, Freq= 0, CH_0, rank 0
2511 19:25:32.729445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2512 19:25:32.729546 ==
2513 19:25:32.736434 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2514 19:25:32.739650 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2515 19:25:32.749954 [CA 0] Center 40 (10~70) winsize 61
2516 19:25:32.752841 [CA 1] Center 39 (9~69) winsize 61
2517 19:25:32.756440 [CA 2] Center 35 (5~66) winsize 62
2518 19:25:32.759867 [CA 3] Center 35 (5~66) winsize 62
2519 19:25:32.762970 [CA 4] Center 34 (4~64) winsize 61
2520 19:25:32.766373 [CA 5] Center 33 (3~64) winsize 62
2521 19:25:32.766484
2522 19:25:32.769962 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2523 19:25:32.770040
2524 19:25:32.772930 [CATrainingPosCal] consider 1 rank data
2525 19:25:32.776278 u2DelayCellTimex100 = 270/100 ps
2526 19:25:32.779763 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2527 19:25:32.786350 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2528 19:25:32.789481 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2529 19:25:32.793043 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2530 19:25:32.796168 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2531 19:25:32.799428 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2532 19:25:32.799499
2533 19:25:32.803191 CA PerBit enable=1, Macro0, CA PI delay=33
2534 19:25:32.803270
2535 19:25:32.805994 [CBTSetCACLKResult] CA Dly = 33
2536 19:25:32.809841 CS Dly: 7 (0~38)
2537 19:25:32.809910 ==
2538 19:25:32.812885 Dram Type= 6, Freq= 0, CH_0, rank 1
2539 19:25:32.816034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2540 19:25:32.816107 ==
2541 19:25:32.822730 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2542 19:25:32.825698 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2543 19:25:32.835959 [CA 0] Center 40 (10~70) winsize 61
2544 19:25:32.838859 [CA 1] Center 39 (9~70) winsize 62
2545 19:25:32.842341 [CA 2] Center 35 (5~66) winsize 62
2546 19:25:32.845911 [CA 3] Center 35 (5~66) winsize 62
2547 19:25:32.848942 [CA 4] Center 34 (4~65) winsize 62
2548 19:25:32.852334 [CA 5] Center 33 (3~64) winsize 62
2549 19:25:32.852410
2550 19:25:32.855688 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2551 19:25:32.855800
2552 19:25:32.858849 [CATrainingPosCal] consider 2 rank data
2553 19:25:32.862351 u2DelayCellTimex100 = 270/100 ps
2554 19:25:32.865595 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2555 19:25:32.872046 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2556 19:25:32.875539 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2557 19:25:32.879123 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2558 19:25:32.881946 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2559 19:25:32.885552 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2560 19:25:32.885623
2561 19:25:32.888508 CA PerBit enable=1, Macro0, CA PI delay=33
2562 19:25:32.888578
2563 19:25:32.892521 [CBTSetCACLKResult] CA Dly = 33
2564 19:25:32.895130 CS Dly: 8 (0~41)
2565 19:25:32.895206
2566 19:25:32.898486 ----->DramcWriteLeveling(PI) begin...
2567 19:25:32.898558 ==
2568 19:25:32.901725 Dram Type= 6, Freq= 0, CH_0, rank 0
2569 19:25:32.905280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2570 19:25:32.905400 ==
2571 19:25:32.908744 Write leveling (Byte 0): 31 => 31
2572 19:25:32.911917 Write leveling (Byte 1): 26 => 26
2573 19:25:32.915634 DramcWriteLeveling(PI) end<-----
2574 19:25:32.915729
2575 19:25:32.915823 ==
2576 19:25:32.918262 Dram Type= 6, Freq= 0, CH_0, rank 0
2577 19:25:32.921839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2578 19:25:32.921951 ==
2579 19:25:32.925138 [Gating] SW mode calibration
2580 19:25:32.931669 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2581 19:25:32.938597 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2582 19:25:32.941747 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2583 19:25:32.945503 0 15 4 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
2584 19:25:32.952004 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2585 19:25:32.954754 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2586 19:25:32.957982 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2587 19:25:32.964859 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2588 19:25:32.968062 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2589 19:25:32.971590 0 15 28 | B1->B0 | 3434 2727 | 1 0 | (1 1) (1 0)
2590 19:25:32.978331 1 0 0 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
2591 19:25:32.981669 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2592 19:25:32.984777 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2593 19:25:32.991334 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2594 19:25:32.995011 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2595 19:25:32.997781 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2596 19:25:33.004281 1 0 24 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (1 1)
2597 19:25:33.007605 1 0 28 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
2598 19:25:33.011185 1 1 0 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
2599 19:25:33.018124 1 1 4 | B1->B0 | 4444 4646 | 0 0 | (1 1) (0 0)
2600 19:25:33.021231 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2601 19:25:33.024386 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2602 19:25:33.031153 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2603 19:25:33.034255 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2604 19:25:33.037789 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2605 19:25:33.041349 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2606 19:25:33.047780 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2607 19:25:33.051462 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2608 19:25:33.054295 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2609 19:25:33.061475 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 19:25:33.064540 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 19:25:33.067564 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 19:25:33.074164 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 19:25:33.077567 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 19:25:33.081363 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 19:25:33.087697 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 19:25:33.091309 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 19:25:33.094344 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 19:25:33.101472 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 19:25:33.104415 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 19:25:33.107382 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2621 19:25:33.114229 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
2622 19:25:33.117524 Total UI for P1: 0, mck2ui 16
2623 19:25:33.120690 best dqsien dly found for B0: ( 1, 3, 24)
2624 19:25:33.124339 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2625 19:25:33.127204 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2626 19:25:33.134163 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2627 19:25:33.134245 Total UI for P1: 0, mck2ui 16
2628 19:25:33.140985 best dqsien dly found for B1: ( 1, 4, 2)
2629 19:25:33.144166 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2630 19:25:33.147316 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2631 19:25:33.147421
2632 19:25:33.150427 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2633 19:25:33.153474 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2634 19:25:33.156926 [Gating] SW calibration Done
2635 19:25:33.157011 ==
2636 19:25:33.160449 Dram Type= 6, Freq= 0, CH_0, rank 0
2637 19:25:33.163429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2638 19:25:33.163505 ==
2639 19:25:33.166960 RX Vref Scan: 0
2640 19:25:33.167055
2641 19:25:33.167142 RX Vref 0 -> 0, step: 1
2642 19:25:33.167234
2643 19:25:33.170265 RX Delay -40 -> 252, step: 8
2644 19:25:33.176482 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2645 19:25:33.179686 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2646 19:25:33.183143 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2647 19:25:33.186961 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2648 19:25:33.190072 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2649 19:25:33.196240 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2650 19:25:33.199861 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2651 19:25:33.203607 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2652 19:25:33.206335 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2653 19:25:33.209829 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2654 19:25:33.213195 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2655 19:25:33.219908 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2656 19:25:33.223390 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2657 19:25:33.226245 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2658 19:25:33.230013 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2659 19:25:33.236421 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2660 19:25:33.236502 ==
2661 19:25:33.239705 Dram Type= 6, Freq= 0, CH_0, rank 0
2662 19:25:33.242656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2663 19:25:33.242740 ==
2664 19:25:33.242806 DQS Delay:
2665 19:25:33.246068 DQS0 = 0, DQS1 = 0
2666 19:25:33.246151 DQM Delay:
2667 19:25:33.249622 DQM0 = 118, DQM1 = 107
2668 19:25:33.249705 DQ Delay:
2669 19:25:33.252582 DQ0 =115, DQ1 =119, DQ2 =119, DQ3 =111
2670 19:25:33.255909 DQ4 =119, DQ5 =111, DQ6 =127, DQ7 =127
2671 19:25:33.259360 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2672 19:25:33.262570 DQ12 =119, DQ13 =111, DQ14 =119, DQ15 =111
2673 19:25:33.262654
2674 19:25:33.262719
2675 19:25:33.266023 ==
2676 19:25:33.269354 Dram Type= 6, Freq= 0, CH_0, rank 0
2677 19:25:33.272570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2678 19:25:33.272655 ==
2679 19:25:33.272721
2680 19:25:33.272782
2681 19:25:33.275854 TX Vref Scan disable
2682 19:25:33.275944 == TX Byte 0 ==
2683 19:25:33.282442 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2684 19:25:33.285283 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2685 19:25:33.285366 == TX Byte 1 ==
2686 19:25:33.292148 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2687 19:25:33.295808 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2688 19:25:33.295900 ==
2689 19:25:33.298581 Dram Type= 6, Freq= 0, CH_0, rank 0
2690 19:25:33.302222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2691 19:25:33.302331 ==
2692 19:25:33.315074 TX Vref=22, minBit 0, minWin=25, winSum=408
2693 19:25:33.318107 TX Vref=24, minBit 3, minWin=25, winSum=416
2694 19:25:33.321216 TX Vref=26, minBit 3, minWin=25, winSum=421
2695 19:25:33.324523 TX Vref=28, minBit 4, minWin=25, winSum=422
2696 19:25:33.328343 TX Vref=30, minBit 5, minWin=25, winSum=426
2697 19:25:33.334432 TX Vref=32, minBit 4, minWin=26, winSum=426
2698 19:25:33.337816 [TxChooseVref] Worse bit 4, Min win 26, Win sum 426, Final Vref 32
2699 19:25:33.337892
2700 19:25:33.341220 Final TX Range 1 Vref 32
2701 19:25:33.341293
2702 19:25:33.341353 ==
2703 19:25:33.344664 Dram Type= 6, Freq= 0, CH_0, rank 0
2704 19:25:33.347526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2705 19:25:33.351078 ==
2706 19:25:33.351161
2707 19:25:33.351227
2708 19:25:33.351288 TX Vref Scan disable
2709 19:25:33.354705 == TX Byte 0 ==
2710 19:25:33.358475 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2711 19:25:33.364601 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2712 19:25:33.364684 == TX Byte 1 ==
2713 19:25:33.368061 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2714 19:25:33.374488 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2715 19:25:33.374573
2716 19:25:33.374638 [DATLAT]
2717 19:25:33.374700 Freq=1200, CH0 RK0
2718 19:25:33.374759
2719 19:25:33.378223 DATLAT Default: 0xd
2720 19:25:33.378305 0, 0xFFFF, sum = 0
2721 19:25:33.381091 1, 0xFFFF, sum = 0
2722 19:25:33.384598 2, 0xFFFF, sum = 0
2723 19:25:33.384682 3, 0xFFFF, sum = 0
2724 19:25:33.387557 4, 0xFFFF, sum = 0
2725 19:25:33.387641 5, 0xFFFF, sum = 0
2726 19:25:33.390886 6, 0xFFFF, sum = 0
2727 19:25:33.390970 7, 0xFFFF, sum = 0
2728 19:25:33.394527 8, 0xFFFF, sum = 0
2729 19:25:33.394611 9, 0xFFFF, sum = 0
2730 19:25:33.398196 10, 0xFFFF, sum = 0
2731 19:25:33.398280 11, 0xFFFF, sum = 0
2732 19:25:33.401495 12, 0x0, sum = 1
2733 19:25:33.401579 13, 0x0, sum = 2
2734 19:25:33.404868 14, 0x0, sum = 3
2735 19:25:33.404952 15, 0x0, sum = 4
2736 19:25:33.407932 best_step = 13
2737 19:25:33.408015
2738 19:25:33.408080 ==
2739 19:25:33.411145 Dram Type= 6, Freq= 0, CH_0, rank 0
2740 19:25:33.414357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2741 19:25:33.414465 ==
2742 19:25:33.414560 RX Vref Scan: 1
2743 19:25:33.414651
2744 19:25:33.417536 Set Vref Range= 32 -> 127
2745 19:25:33.417632
2746 19:25:33.421241 RX Vref 32 -> 127, step: 1
2747 19:25:33.421324
2748 19:25:33.424147 RX Delay -21 -> 252, step: 4
2749 19:25:33.424230
2750 19:25:33.427435 Set Vref, RX VrefLevel [Byte0]: 32
2751 19:25:33.431160 [Byte1]: 32
2752 19:25:33.431243
2753 19:25:33.434195 Set Vref, RX VrefLevel [Byte0]: 33
2754 19:25:33.438295 [Byte1]: 33
2755 19:25:33.440834
2756 19:25:33.440917 Set Vref, RX VrefLevel [Byte0]: 34
2757 19:25:33.444273 [Byte1]: 34
2758 19:25:33.449226
2759 19:25:33.449309 Set Vref, RX VrefLevel [Byte0]: 35
2760 19:25:33.452357 [Byte1]: 35
2761 19:25:33.457170
2762 19:25:33.457238 Set Vref, RX VrefLevel [Byte0]: 36
2763 19:25:33.460487 [Byte1]: 36
2764 19:25:33.464830
2765 19:25:33.464900 Set Vref, RX VrefLevel [Byte0]: 37
2766 19:25:33.468451 [Byte1]: 37
2767 19:25:33.472593
2768 19:25:33.472669 Set Vref, RX VrefLevel [Byte0]: 38
2769 19:25:33.476416 [Byte1]: 38
2770 19:25:33.480586
2771 19:25:33.480660 Set Vref, RX VrefLevel [Byte0]: 39
2772 19:25:33.484168 [Byte1]: 39
2773 19:25:33.488915
2774 19:25:33.488991 Set Vref, RX VrefLevel [Byte0]: 40
2775 19:25:33.491726 [Byte1]: 40
2776 19:25:33.496560
2777 19:25:33.496637 Set Vref, RX VrefLevel [Byte0]: 41
2778 19:25:33.500174 [Byte1]: 41
2779 19:25:33.504535
2780 19:25:33.504617 Set Vref, RX VrefLevel [Byte0]: 42
2781 19:25:33.508237 [Byte1]: 42
2782 19:25:33.512617
2783 19:25:33.512705 Set Vref, RX VrefLevel [Byte0]: 43
2784 19:25:33.515482 [Byte1]: 43
2785 19:25:33.520491
2786 19:25:33.520574 Set Vref, RX VrefLevel [Byte0]: 44
2787 19:25:33.523395 [Byte1]: 44
2788 19:25:33.528018
2789 19:25:33.528100 Set Vref, RX VrefLevel [Byte0]: 45
2790 19:25:33.531544 [Byte1]: 45
2791 19:25:33.536241
2792 19:25:33.536323 Set Vref, RX VrefLevel [Byte0]: 46
2793 19:25:33.539304 [Byte1]: 46
2794 19:25:33.544189
2795 19:25:33.544269 Set Vref, RX VrefLevel [Byte0]: 47
2796 19:25:33.547642 [Byte1]: 47
2797 19:25:33.552229
2798 19:25:33.552309 Set Vref, RX VrefLevel [Byte0]: 48
2799 19:25:33.555212 [Byte1]: 48
2800 19:25:33.559808
2801 19:25:33.559944 Set Vref, RX VrefLevel [Byte0]: 49
2802 19:25:33.563506 [Byte1]: 49
2803 19:25:33.568139
2804 19:25:33.568279 Set Vref, RX VrefLevel [Byte0]: 50
2805 19:25:33.571452 [Byte1]: 50
2806 19:25:33.575877
2807 19:25:33.576003 Set Vref, RX VrefLevel [Byte0]: 51
2808 19:25:33.579084 [Byte1]: 51
2809 19:25:33.583892
2810 19:25:33.583986 Set Vref, RX VrefLevel [Byte0]: 52
2811 19:25:33.586859 [Byte1]: 52
2812 19:25:33.591490
2813 19:25:33.591596 Set Vref, RX VrefLevel [Byte0]: 53
2814 19:25:33.594850 [Byte1]: 53
2815 19:25:33.599552
2816 19:25:33.599632 Set Vref, RX VrefLevel [Byte0]: 54
2817 19:25:33.603084 [Byte1]: 54
2818 19:25:33.607865
2819 19:25:33.607990 Set Vref, RX VrefLevel [Byte0]: 55
2820 19:25:33.610864 [Byte1]: 55
2821 19:25:33.615731
2822 19:25:33.615837 Set Vref, RX VrefLevel [Byte0]: 56
2823 19:25:33.618987 [Byte1]: 56
2824 19:25:33.623210
2825 19:25:33.623283 Set Vref, RX VrefLevel [Byte0]: 57
2826 19:25:33.626364 [Byte1]: 57
2827 19:25:33.631585
2828 19:25:33.631683 Set Vref, RX VrefLevel [Byte0]: 58
2829 19:25:33.634869 [Byte1]: 58
2830 19:25:33.639000
2831 19:25:33.639097 Set Vref, RX VrefLevel [Byte0]: 59
2832 19:25:33.642332 [Byte1]: 59
2833 19:25:33.647351
2834 19:25:33.647449 Set Vref, RX VrefLevel [Byte0]: 60
2835 19:25:33.650336 [Byte1]: 60
2836 19:25:33.654890
2837 19:25:33.655014 Set Vref, RX VrefLevel [Byte0]: 61
2838 19:25:33.658325 [Byte1]: 61
2839 19:25:33.662749
2840 19:25:33.662829 Set Vref, RX VrefLevel [Byte0]: 62
2841 19:25:33.666523 [Byte1]: 62
2842 19:25:33.670638
2843 19:25:33.670735 Set Vref, RX VrefLevel [Byte0]: 63
2844 19:25:33.674207 [Byte1]: 63
2845 19:25:33.678770
2846 19:25:33.678850 Set Vref, RX VrefLevel [Byte0]: 64
2847 19:25:33.682331 [Byte1]: 64
2848 19:25:33.687056
2849 19:25:33.687137 Set Vref, RX VrefLevel [Byte0]: 65
2850 19:25:33.690144 [Byte1]: 65
2851 19:25:33.694603
2852 19:25:33.694683 Set Vref, RX VrefLevel [Byte0]: 66
2853 19:25:33.697802 [Byte1]: 66
2854 19:25:33.702613
2855 19:25:33.702688 Set Vref, RX VrefLevel [Byte0]: 67
2856 19:25:33.705994 [Byte1]: 67
2857 19:25:33.710703
2858 19:25:33.710785 Set Vref, RX VrefLevel [Byte0]: 68
2859 19:25:33.713760 [Byte1]: 68
2860 19:25:33.718710
2861 19:25:33.718784 Set Vref, RX VrefLevel [Byte0]: 69
2862 19:25:33.721614 [Byte1]: 69
2863 19:25:33.726207
2864 19:25:33.726281 Final RX Vref Byte 0 = 52 to rank0
2865 19:25:33.729699 Final RX Vref Byte 1 = 60 to rank0
2866 19:25:33.733413 Final RX Vref Byte 0 = 52 to rank1
2867 19:25:33.736333 Final RX Vref Byte 1 = 60 to rank1==
2868 19:25:33.739619 Dram Type= 6, Freq= 0, CH_0, rank 0
2869 19:25:33.746057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2870 19:25:33.746139 ==
2871 19:25:33.746203 DQS Delay:
2872 19:25:33.746262 DQS0 = 0, DQS1 = 0
2873 19:25:33.749384 DQM Delay:
2874 19:25:33.749462 DQM0 = 117, DQM1 = 105
2875 19:25:33.752810 DQ Delay:
2876 19:25:33.756364 DQ0 =118, DQ1 =118, DQ2 =114, DQ3 =114
2877 19:25:33.759393 DQ4 =118, DQ5 =110, DQ6 =126, DQ7 =122
2878 19:25:33.762669 DQ8 =94, DQ9 =90, DQ10 =106, DQ11 =100
2879 19:25:33.766261 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2880 19:25:33.766334
2881 19:25:33.766400
2882 19:25:33.776178 [DQSOSCAuto] RK0, (LSB)MR18= 0xfffb, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 410 ps
2883 19:25:33.776259 CH0 RK0: MR19=303, MR18=FFFB
2884 19:25:33.782450 CH0_RK0: MR19=0x303, MR18=0xFFFB, DQSOSC=410, MR23=63, INC=39, DEC=26
2885 19:25:33.782528
2886 19:25:33.786050 ----->DramcWriteLeveling(PI) begin...
2887 19:25:33.786151 ==
2888 19:25:33.789422 Dram Type= 6, Freq= 0, CH_0, rank 1
2889 19:25:33.795800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2890 19:25:33.795904 ==
2891 19:25:33.799297 Write leveling (Byte 0): 31 => 31
2892 19:25:33.799369 Write leveling (Byte 1): 26 => 26
2893 19:25:33.802632 DramcWriteLeveling(PI) end<-----
2894 19:25:33.802707
2895 19:25:33.805859 ==
2896 19:25:33.805931 Dram Type= 6, Freq= 0, CH_0, rank 1
2897 19:25:33.812468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2898 19:25:33.812550 ==
2899 19:25:33.816074 [Gating] SW mode calibration
2900 19:25:33.822384 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2901 19:25:33.825994 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2902 19:25:33.832128 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2903 19:25:33.835770 0 15 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
2904 19:25:33.839122 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2905 19:25:33.845562 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2906 19:25:33.849038 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2907 19:25:33.852058 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2908 19:25:33.858481 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2909 19:25:33.861989 0 15 28 | B1->B0 | 3434 2626 | 0 0 | (0 0) (0 0)
2910 19:25:33.865273 1 0 0 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
2911 19:25:33.871659 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2912 19:25:33.875243 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2913 19:25:33.878758 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2914 19:25:33.885550 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2915 19:25:33.888496 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2916 19:25:33.891640 1 0 24 | B1->B0 | 2323 3130 | 0 1 | (0 0) (0 0)
2917 19:25:33.898571 1 0 28 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
2918 19:25:33.901619 1 1 0 | B1->B0 | 4141 4646 | 1 0 | (0 0) (0 0)
2919 19:25:33.905301 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2920 19:25:33.911693 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2921 19:25:33.915066 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2922 19:25:33.918218 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2923 19:25:33.925175 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2924 19:25:33.928070 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2925 19:25:33.931757 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2926 19:25:33.938355 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2927 19:25:33.941273 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 19:25:33.945011 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 19:25:33.951369 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 19:25:33.954700 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 19:25:33.957834 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 19:25:33.964729 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 19:25:33.968217 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 19:25:33.971373 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 19:25:33.978264 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 19:25:33.981151 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 19:25:33.984674 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 19:25:33.987572 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 19:25:33.994112 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 19:25:33.997643 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2941 19:25:34.000957 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2942 19:25:34.007965 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2943 19:25:34.011011 Total UI for P1: 0, mck2ui 16
2944 19:25:34.014586 best dqsien dly found for B0: ( 1, 3, 26)
2945 19:25:34.017834 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2946 19:25:34.020956 Total UI for P1: 0, mck2ui 16
2947 19:25:34.024401 best dqsien dly found for B1: ( 1, 4, 0)
2948 19:25:34.027426 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2949 19:25:34.031025 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2950 19:25:34.031099
2951 19:25:34.033986 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2952 19:25:34.037967 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2953 19:25:34.040783 [Gating] SW calibration Done
2954 19:25:34.040852 ==
2955 19:25:34.044086 Dram Type= 6, Freq= 0, CH_0, rank 1
2956 19:25:34.047716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2957 19:25:34.050954 ==
2958 19:25:34.051025 RX Vref Scan: 0
2959 19:25:34.051085
2960 19:25:34.054202 RX Vref 0 -> 0, step: 1
2961 19:25:34.054267
2962 19:25:34.057750 RX Delay -40 -> 252, step: 8
2963 19:25:34.060751 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
2964 19:25:34.064180 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2965 19:25:34.067415 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2966 19:25:34.070545 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2967 19:25:34.077536 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2968 19:25:34.080691 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2969 19:25:34.084108 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2970 19:25:34.087388 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
2971 19:25:34.090852 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2972 19:25:34.097767 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2973 19:25:34.100841 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2974 19:25:34.103996 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2975 19:25:34.106901 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2976 19:25:34.110392 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2977 19:25:34.117289 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2978 19:25:34.120391 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2979 19:25:34.120497 ==
2980 19:25:34.123800 Dram Type= 6, Freq= 0, CH_0, rank 1
2981 19:25:34.126872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2982 19:25:34.126967 ==
2983 19:25:34.130811 DQS Delay:
2984 19:25:34.130879 DQS0 = 0, DQS1 = 0
2985 19:25:34.130939 DQM Delay:
2986 19:25:34.133667 DQM0 = 116, DQM1 = 109
2987 19:25:34.133776 DQ Delay:
2988 19:25:34.136802 DQ0 =115, DQ1 =119, DQ2 =111, DQ3 =115
2989 19:25:34.140556 DQ4 =119, DQ5 =103, DQ6 =127, DQ7 =119
2990 19:25:34.143662 DQ8 =99, DQ9 =91, DQ10 =111, DQ11 =103
2991 19:25:34.150139 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =115
2992 19:25:34.150252
2993 19:25:34.150375
2994 19:25:34.150501 ==
2995 19:25:34.153631 Dram Type= 6, Freq= 0, CH_0, rank 1
2996 19:25:34.157297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2997 19:25:34.157402 ==
2998 19:25:34.157531
2999 19:25:34.157654
3000 19:25:34.160540 TX Vref Scan disable
3001 19:25:34.160647 == TX Byte 0 ==
3002 19:25:34.166575 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3003 19:25:34.170225 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3004 19:25:34.170344 == TX Byte 1 ==
3005 19:25:34.176679 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3006 19:25:34.180061 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3007 19:25:34.180196 ==
3008 19:25:34.183300 Dram Type= 6, Freq= 0, CH_0, rank 1
3009 19:25:34.186695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3010 19:25:34.186813 ==
3011 19:25:34.200276 TX Vref=22, minBit 1, minWin=25, winSum=414
3012 19:25:34.203206 TX Vref=24, minBit 1, minWin=25, winSum=409
3013 19:25:34.206460 TX Vref=26, minBit 0, minWin=26, winSum=421
3014 19:25:34.209939 TX Vref=28, minBit 5, minWin=25, winSum=422
3015 19:25:34.213270 TX Vref=30, minBit 4, minWin=26, winSum=425
3016 19:25:34.219748 TX Vref=32, minBit 1, minWin=26, winSum=423
3017 19:25:34.223199 [TxChooseVref] Worse bit 4, Min win 26, Win sum 425, Final Vref 30
3018 19:25:34.223272
3019 19:25:34.226520 Final TX Range 1 Vref 30
3020 19:25:34.226585
3021 19:25:34.226642 ==
3022 19:25:34.229672 Dram Type= 6, Freq= 0, CH_0, rank 1
3023 19:25:34.232994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3024 19:25:34.233062 ==
3025 19:25:34.236695
3026 19:25:34.236760
3027 19:25:34.236818 TX Vref Scan disable
3028 19:25:34.239581 == TX Byte 0 ==
3029 19:25:34.243671 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3030 19:25:34.246478 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3031 19:25:34.250143 == TX Byte 1 ==
3032 19:25:34.252958 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3033 19:25:34.259774 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3034 19:25:34.259854
3035 19:25:34.259934 [DATLAT]
3036 19:25:34.259995 Freq=1200, CH0 RK1
3037 19:25:34.260054
3038 19:25:34.263287 DATLAT Default: 0xd
3039 19:25:34.263357 0, 0xFFFF, sum = 0
3040 19:25:34.266341 1, 0xFFFF, sum = 0
3041 19:25:34.266412 2, 0xFFFF, sum = 0
3042 19:25:34.269805 3, 0xFFFF, sum = 0
3043 19:25:34.272760 4, 0xFFFF, sum = 0
3044 19:25:34.272834 5, 0xFFFF, sum = 0
3045 19:25:34.276026 6, 0xFFFF, sum = 0
3046 19:25:34.276097 7, 0xFFFF, sum = 0
3047 19:25:34.279719 8, 0xFFFF, sum = 0
3048 19:25:34.279822 9, 0xFFFF, sum = 0
3049 19:25:34.282600 10, 0xFFFF, sum = 0
3050 19:25:34.282674 11, 0xFFFF, sum = 0
3051 19:25:34.286293 12, 0x0, sum = 1
3052 19:25:34.286368 13, 0x0, sum = 2
3053 19:25:34.289331 14, 0x0, sum = 3
3054 19:25:34.289407 15, 0x0, sum = 4
3055 19:25:34.292833 best_step = 13
3056 19:25:34.292909
3057 19:25:34.292970 ==
3058 19:25:34.296162 Dram Type= 6, Freq= 0, CH_0, rank 1
3059 19:25:34.299625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3060 19:25:34.299725 ==
3061 19:25:34.299815 RX Vref Scan: 0
3062 19:25:34.299913
3063 19:25:34.302615 RX Vref 0 -> 0, step: 1
3064 19:25:34.302693
3065 19:25:34.306302 RX Delay -21 -> 252, step: 4
3066 19:25:34.309168 iDelay=195, Bit 0, Center 114 (51 ~ 178) 128
3067 19:25:34.316073 iDelay=195, Bit 1, Center 116 (47 ~ 186) 140
3068 19:25:34.319600 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3069 19:25:34.322522 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3070 19:25:34.325858 iDelay=195, Bit 4, Center 118 (51 ~ 186) 136
3071 19:25:34.329558 iDelay=195, Bit 5, Center 108 (43 ~ 174) 132
3072 19:25:34.335957 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3073 19:25:34.339523 iDelay=195, Bit 7, Center 122 (55 ~ 190) 136
3074 19:25:34.342873 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3075 19:25:34.346156 iDelay=195, Bit 9, Center 92 (27 ~ 158) 132
3076 19:25:34.349487 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3077 19:25:34.355928 iDelay=195, Bit 11, Center 102 (35 ~ 170) 136
3078 19:25:34.359408 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3079 19:25:34.362694 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
3080 19:25:34.366132 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3081 19:25:34.369106 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3082 19:25:34.372906 ==
3083 19:25:34.376348 Dram Type= 6, Freq= 0, CH_0, rank 1
3084 19:25:34.379174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3085 19:25:34.379256 ==
3086 19:25:34.379319 DQS Delay:
3087 19:25:34.382756 DQS0 = 0, DQS1 = 0
3088 19:25:34.382837 DQM Delay:
3089 19:25:34.385725 DQM0 = 115, DQM1 = 107
3090 19:25:34.385806 DQ Delay:
3091 19:25:34.389273 DQ0 =114, DQ1 =116, DQ2 =110, DQ3 =112
3092 19:25:34.392566 DQ4 =118, DQ5 =108, DQ6 =126, DQ7 =122
3093 19:25:34.396085 DQ8 =96, DQ9 =92, DQ10 =110, DQ11 =102
3094 19:25:34.399206 DQ12 =112, DQ13 =112, DQ14 =118, DQ15 =114
3095 19:25:34.399287
3096 19:25:34.399350
3097 19:25:34.408928 [DQSOSCAuto] RK1, (LSB)MR18= 0xfffc, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 410 ps
3098 19:25:34.412595 CH0 RK1: MR19=303, MR18=FFFC
3099 19:25:34.415786 CH0_RK1: MR19=0x303, MR18=0xFFFC, DQSOSC=410, MR23=63, INC=39, DEC=26
3100 19:25:34.419167 [RxdqsGatingPostProcess] freq 1200
3101 19:25:34.425621 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3102 19:25:34.429131 best DQS0 dly(2T, 0.5T) = (0, 11)
3103 19:25:34.432132 best DQS1 dly(2T, 0.5T) = (0, 12)
3104 19:25:34.435454 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3105 19:25:34.438800 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3106 19:25:34.442168 best DQS0 dly(2T, 0.5T) = (0, 11)
3107 19:25:34.445607 best DQS1 dly(2T, 0.5T) = (0, 12)
3108 19:25:34.448543 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3109 19:25:34.452315 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3110 19:25:34.452396 Pre-setting of DQS Precalculation
3111 19:25:34.458947 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3112 19:25:34.459028 ==
3113 19:25:34.462013 Dram Type= 6, Freq= 0, CH_1, rank 0
3114 19:25:34.465075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3115 19:25:34.465156 ==
3116 19:25:34.471723 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3117 19:25:34.478141 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3118 19:25:34.486395 [CA 0] Center 38 (8~68) winsize 61
3119 19:25:34.489631 [CA 1] Center 37 (7~68) winsize 62
3120 19:25:34.492856 [CA 2] Center 35 (5~65) winsize 61
3121 19:25:34.496114 [CA 3] Center 34 (4~64) winsize 61
3122 19:25:34.499443 [CA 4] Center 34 (4~65) winsize 62
3123 19:25:34.502623 [CA 5] Center 33 (3~63) winsize 61
3124 19:25:34.502703
3125 19:25:34.506075 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3126 19:25:34.506155
3127 19:25:34.509085 [CATrainingPosCal] consider 1 rank data
3128 19:25:34.512777 u2DelayCellTimex100 = 270/100 ps
3129 19:25:34.515785 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3130 19:25:34.522823 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3131 19:25:34.525687 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3132 19:25:34.529262 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3133 19:25:34.532194 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3134 19:25:34.535942 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3135 19:25:34.536024
3136 19:25:34.539187 CA PerBit enable=1, Macro0, CA PI delay=33
3137 19:25:34.539268
3138 19:25:34.542522 [CBTSetCACLKResult] CA Dly = 33
3139 19:25:34.542603 CS Dly: 5 (0~36)
3140 19:25:34.545887 ==
3141 19:25:34.548995 Dram Type= 6, Freq= 0, CH_1, rank 1
3142 19:25:34.552512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3143 19:25:34.552593 ==
3144 19:25:34.555522 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3145 19:25:34.562168 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3146 19:25:34.572506 [CA 0] Center 37 (7~68) winsize 62
3147 19:25:34.575049 [CA 1] Center 38 (8~68) winsize 61
3148 19:25:34.578304 [CA 2] Center 34 (4~65) winsize 62
3149 19:25:34.581717 [CA 3] Center 33 (3~64) winsize 62
3150 19:25:34.585352 [CA 4] Center 34 (4~64) winsize 61
3151 19:25:34.588381 [CA 5] Center 33 (3~64) winsize 62
3152 19:25:34.588461
3153 19:25:34.591838 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3154 19:25:34.591959
3155 19:25:34.595231 [CATrainingPosCal] consider 2 rank data
3156 19:25:34.598134 u2DelayCellTimex100 = 270/100 ps
3157 19:25:34.601645 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3158 19:25:34.605039 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3159 19:25:34.611744 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3160 19:25:34.615151 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3161 19:25:34.618414 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3162 19:25:34.621321 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3163 19:25:34.621402
3164 19:25:34.625019 CA PerBit enable=1, Macro0, CA PI delay=33
3165 19:25:34.625103
3166 19:25:34.627916 [CBTSetCACLKResult] CA Dly = 33
3167 19:25:34.627996 CS Dly: 6 (0~39)
3168 19:25:34.628060
3169 19:25:34.631729 ----->DramcWriteLeveling(PI) begin...
3170 19:25:34.635007 ==
3171 19:25:34.637992 Dram Type= 6, Freq= 0, CH_1, rank 0
3172 19:25:34.641561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3173 19:25:34.641643 ==
3174 19:25:34.644451 Write leveling (Byte 0): 25 => 25
3175 19:25:34.648003 Write leveling (Byte 1): 27 => 27
3176 19:25:34.651343 DramcWriteLeveling(PI) end<-----
3177 19:25:34.651424
3178 19:25:34.651488 ==
3179 19:25:34.654711 Dram Type= 6, Freq= 0, CH_1, rank 0
3180 19:25:34.657765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3181 19:25:34.657847 ==
3182 19:25:34.661343 [Gating] SW mode calibration
3183 19:25:34.668160 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3184 19:25:34.674553 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3185 19:25:34.677411 0 15 0 | B1->B0 | 3030 3434 | 1 1 | (0 0) (0 0)
3186 19:25:34.680908 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3187 19:25:34.687895 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3188 19:25:34.690858 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3189 19:25:34.694095 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3190 19:25:34.700953 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3191 19:25:34.704501 0 15 24 | B1->B0 | 3434 3131 | 0 0 | (0 0) (0 0)
3192 19:25:34.707398 0 15 28 | B1->B0 | 2626 2525 | 0 0 | (0 0) (1 0)
3193 19:25:34.710992 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3194 19:25:34.717500 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3195 19:25:34.720931 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3196 19:25:34.724017 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3197 19:25:34.731089 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3198 19:25:34.734368 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3199 19:25:34.737380 1 0 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
3200 19:25:34.744218 1 0 28 | B1->B0 | 3939 4646 | 0 0 | (1 1) (0 0)
3201 19:25:34.747239 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3202 19:25:34.750886 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3203 19:25:34.757744 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3204 19:25:34.760498 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3205 19:25:34.763798 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3206 19:25:34.770521 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3207 19:25:34.773895 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3208 19:25:34.777518 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3209 19:25:34.784219 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 19:25:34.787112 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 19:25:34.790426 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 19:25:34.797285 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 19:25:34.800237 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 19:25:34.803571 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 19:25:34.810643 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 19:25:34.813848 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 19:25:34.817249 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3218 19:25:34.823409 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 19:25:34.826779 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 19:25:34.830264 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 19:25:34.837008 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 19:25:34.839939 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 19:25:34.843468 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3224 19:25:34.849873 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3225 19:25:34.854056 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3226 19:25:34.856952 Total UI for P1: 0, mck2ui 16
3227 19:25:34.860402 best dqsien dly found for B0: ( 1, 3, 26)
3228 19:25:34.863264 Total UI for P1: 0, mck2ui 16
3229 19:25:34.866531 best dqsien dly found for B1: ( 1, 3, 28)
3230 19:25:34.870343 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3231 19:25:34.873270 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3232 19:25:34.873351
3233 19:25:34.876892 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3234 19:25:34.880658 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3235 19:25:34.883449 [Gating] SW calibration Done
3236 19:25:34.883530 ==
3237 19:25:34.886790 Dram Type= 6, Freq= 0, CH_1, rank 0
3238 19:25:34.890024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3239 19:25:34.890105 ==
3240 19:25:34.893374 RX Vref Scan: 0
3241 19:25:34.893456
3242 19:25:34.896948 RX Vref 0 -> 0, step: 1
3243 19:25:34.897029
3244 19:25:34.897099 RX Delay -40 -> 252, step: 8
3245 19:25:34.903385 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3246 19:25:34.906824 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3247 19:25:34.910220 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3248 19:25:34.913222 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3249 19:25:34.916971 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3250 19:25:34.923702 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3251 19:25:34.927022 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3252 19:25:34.930266 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3253 19:25:34.933398 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3254 19:25:34.936437 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3255 19:25:34.943395 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3256 19:25:34.946998 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3257 19:25:34.949803 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3258 19:25:34.953477 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3259 19:25:34.956341 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3260 19:25:34.963056 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3261 19:25:34.963154 ==
3262 19:25:34.966829 Dram Type= 6, Freq= 0, CH_1, rank 0
3263 19:25:34.969661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3264 19:25:34.969739 ==
3265 19:25:34.969802 DQS Delay:
3266 19:25:34.973257 DQS0 = 0, DQS1 = 0
3267 19:25:34.973338 DQM Delay:
3268 19:25:34.976570 DQM0 = 116, DQM1 = 112
3269 19:25:34.976643 DQ Delay:
3270 19:25:34.979916 DQ0 =123, DQ1 =115, DQ2 =103, DQ3 =119
3271 19:25:34.983189 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =115
3272 19:25:34.986114 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3273 19:25:34.989654 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3274 19:25:34.993077
3275 19:25:34.993143
3276 19:25:34.993208 ==
3277 19:25:34.996672 Dram Type= 6, Freq= 0, CH_1, rank 0
3278 19:25:34.999635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3279 19:25:34.999729 ==
3280 19:25:34.999824
3281 19:25:34.999948
3282 19:25:35.002943 TX Vref Scan disable
3283 19:25:35.003024 == TX Byte 0 ==
3284 19:25:35.009592 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3285 19:25:35.013074 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3286 19:25:35.013155 == TX Byte 1 ==
3287 19:25:35.019318 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3288 19:25:35.022676 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3289 19:25:35.022758 ==
3290 19:25:35.025868 Dram Type= 6, Freq= 0, CH_1, rank 0
3291 19:25:35.029277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3292 19:25:35.029358 ==
3293 19:25:35.041771 TX Vref=22, minBit 11, minWin=24, winSum=405
3294 19:25:35.045180 TX Vref=24, minBit 11, minWin=24, winSum=411
3295 19:25:35.048826 TX Vref=26, minBit 6, minWin=25, winSum=420
3296 19:25:35.051816 TX Vref=28, minBit 1, minWin=26, winSum=427
3297 19:25:35.055349 TX Vref=30, minBit 9, minWin=26, winSum=430
3298 19:25:35.061751 TX Vref=32, minBit 9, minWin=25, winSum=425
3299 19:25:35.065165 [TxChooseVref] Worse bit 9, Min win 26, Win sum 430, Final Vref 30
3300 19:25:35.065247
3301 19:25:35.068461 Final TX Range 1 Vref 30
3302 19:25:35.068542
3303 19:25:35.068606 ==
3304 19:25:35.071571 Dram Type= 6, Freq= 0, CH_1, rank 0
3305 19:25:35.075014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3306 19:25:35.078431 ==
3307 19:25:35.078512
3308 19:25:35.078595
3309 19:25:35.078686 TX Vref Scan disable
3310 19:25:35.081963 == TX Byte 0 ==
3311 19:25:35.085373 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3312 19:25:35.091590 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3313 19:25:35.091671 == TX Byte 1 ==
3314 19:25:35.095153 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3315 19:25:35.101821 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3316 19:25:35.101903
3317 19:25:35.101967 [DATLAT]
3318 19:25:35.102036 Freq=1200, CH1 RK0
3319 19:25:35.102126
3320 19:25:35.105177 DATLAT Default: 0xd
3321 19:25:35.105257 0, 0xFFFF, sum = 0
3322 19:25:35.108214 1, 0xFFFF, sum = 0
3323 19:25:35.111664 2, 0xFFFF, sum = 0
3324 19:25:35.111746 3, 0xFFFF, sum = 0
3325 19:25:35.114831 4, 0xFFFF, sum = 0
3326 19:25:35.114947 5, 0xFFFF, sum = 0
3327 19:25:35.118293 6, 0xFFFF, sum = 0
3328 19:25:35.118376 7, 0xFFFF, sum = 0
3329 19:25:35.121388 8, 0xFFFF, sum = 0
3330 19:25:35.121470 9, 0xFFFF, sum = 0
3331 19:25:35.125091 10, 0xFFFF, sum = 0
3332 19:25:35.125174 11, 0xFFFF, sum = 0
3333 19:25:35.128761 12, 0x0, sum = 1
3334 19:25:35.128842 13, 0x0, sum = 2
3335 19:25:35.131455 14, 0x0, sum = 3
3336 19:25:35.131536 15, 0x0, sum = 4
3337 19:25:35.135066 best_step = 13
3338 19:25:35.135147
3339 19:25:35.135210 ==
3340 19:25:35.138048 Dram Type= 6, Freq= 0, CH_1, rank 0
3341 19:25:35.141701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3342 19:25:35.141783 ==
3343 19:25:35.141847 RX Vref Scan: 1
3344 19:25:35.144522
3345 19:25:35.144602 Set Vref Range= 32 -> 127
3346 19:25:35.144666
3347 19:25:35.148008 RX Vref 32 -> 127, step: 1
3348 19:25:35.148088
3349 19:25:35.151190 RX Delay -13 -> 252, step: 4
3350 19:25:35.151271
3351 19:25:35.154590 Set Vref, RX VrefLevel [Byte0]: 32
3352 19:25:35.158202 [Byte1]: 32
3353 19:25:35.158282
3354 19:25:35.161084 Set Vref, RX VrefLevel [Byte0]: 33
3355 19:25:35.164059 [Byte1]: 33
3356 19:25:35.168420
3357 19:25:35.168501 Set Vref, RX VrefLevel [Byte0]: 34
3358 19:25:35.171562 [Byte1]: 34
3359 19:25:35.176076
3360 19:25:35.176156 Set Vref, RX VrefLevel [Byte0]: 35
3361 19:25:35.179208 [Byte1]: 35
3362 19:25:35.183709
3363 19:25:35.183814 Set Vref, RX VrefLevel [Byte0]: 36
3364 19:25:35.187342 [Byte1]: 36
3365 19:25:35.191823
3366 19:25:35.191943 Set Vref, RX VrefLevel [Byte0]: 37
3367 19:25:35.195207 [Byte1]: 37
3368 19:25:35.199957
3369 19:25:35.200047 Set Vref, RX VrefLevel [Byte0]: 38
3370 19:25:35.203192 [Byte1]: 38
3371 19:25:35.207276
3372 19:25:35.207355 Set Vref, RX VrefLevel [Byte0]: 39
3373 19:25:35.210866 [Byte1]: 39
3374 19:25:35.215399
3375 19:25:35.215479 Set Vref, RX VrefLevel [Byte0]: 40
3376 19:25:35.218673 [Byte1]: 40
3377 19:25:35.223078
3378 19:25:35.223158 Set Vref, RX VrefLevel [Byte0]: 41
3379 19:25:35.226572 [Byte1]: 41
3380 19:25:35.231221
3381 19:25:35.231301 Set Vref, RX VrefLevel [Byte0]: 42
3382 19:25:35.234465 [Byte1]: 42
3383 19:25:35.239235
3384 19:25:35.239314 Set Vref, RX VrefLevel [Byte0]: 43
3385 19:25:35.242325 [Byte1]: 43
3386 19:25:35.246936
3387 19:25:35.247017 Set Vref, RX VrefLevel [Byte0]: 44
3388 19:25:35.250381 [Byte1]: 44
3389 19:25:35.254868
3390 19:25:35.254948 Set Vref, RX VrefLevel [Byte0]: 45
3391 19:25:35.257906 [Byte1]: 45
3392 19:25:35.262685
3393 19:25:35.262764 Set Vref, RX VrefLevel [Byte0]: 46
3394 19:25:35.266136 [Byte1]: 46
3395 19:25:35.270873
3396 19:25:35.270953 Set Vref, RX VrefLevel [Byte0]: 47
3397 19:25:35.273659 [Byte1]: 47
3398 19:25:35.278321
3399 19:25:35.278401 Set Vref, RX VrefLevel [Byte0]: 48
3400 19:25:35.281837 [Byte1]: 48
3401 19:25:35.286188
3402 19:25:35.286290 Set Vref, RX VrefLevel [Byte0]: 49
3403 19:25:35.289430 [Byte1]: 49
3404 19:25:35.294175
3405 19:25:35.294297 Set Vref, RX VrefLevel [Byte0]: 50
3406 19:25:35.297388 [Byte1]: 50
3407 19:25:35.302355
3408 19:25:35.302436 Set Vref, RX VrefLevel [Byte0]: 51
3409 19:25:35.305365 [Byte1]: 51
3410 19:25:35.309883
3411 19:25:35.309963 Set Vref, RX VrefLevel [Byte0]: 52
3412 19:25:35.313433 [Byte1]: 52
3413 19:25:35.317492
3414 19:25:35.317573 Set Vref, RX VrefLevel [Byte0]: 53
3415 19:25:35.320994 [Byte1]: 53
3416 19:25:35.325606
3417 19:25:35.325688 Set Vref, RX VrefLevel [Byte0]: 54
3418 19:25:35.328639 [Byte1]: 54
3419 19:25:35.333678
3420 19:25:35.333759 Set Vref, RX VrefLevel [Byte0]: 55
3421 19:25:35.336826 [Byte1]: 55
3422 19:25:35.341367
3423 19:25:35.341458 Set Vref, RX VrefLevel [Byte0]: 56
3424 19:25:35.345089 [Byte1]: 56
3425 19:25:35.349378
3426 19:25:35.349510 Set Vref, RX VrefLevel [Byte0]: 57
3427 19:25:35.353052 [Byte1]: 57
3428 19:25:35.357505
3429 19:25:35.357608 Set Vref, RX VrefLevel [Byte0]: 58
3430 19:25:35.360403 [Byte1]: 58
3431 19:25:35.364805
3432 19:25:35.364920 Set Vref, RX VrefLevel [Byte0]: 59
3433 19:25:35.368578 [Byte1]: 59
3434 19:25:35.373309
3435 19:25:35.373405 Set Vref, RX VrefLevel [Byte0]: 60
3436 19:25:35.376099 [Byte1]: 60
3437 19:25:35.380737
3438 19:25:35.380824 Set Vref, RX VrefLevel [Byte0]: 61
3439 19:25:35.384343 [Byte1]: 61
3440 19:25:35.388853
3441 19:25:35.388952 Set Vref, RX VrefLevel [Byte0]: 62
3442 19:25:35.391819 [Byte1]: 62
3443 19:25:35.396443
3444 19:25:35.396524 Set Vref, RX VrefLevel [Byte0]: 63
3445 19:25:35.400072 [Byte1]: 63
3446 19:25:35.404305
3447 19:25:35.404387 Set Vref, RX VrefLevel [Byte0]: 64
3448 19:25:35.407875 [Byte1]: 64
3449 19:25:35.412732
3450 19:25:35.412815 Set Vref, RX VrefLevel [Byte0]: 65
3451 19:25:35.415537 [Byte1]: 65
3452 19:25:35.420174
3453 19:25:35.420258 Final RX Vref Byte 0 = 49 to rank0
3454 19:25:35.423716 Final RX Vref Byte 1 = 51 to rank0
3455 19:25:35.426653 Final RX Vref Byte 0 = 49 to rank1
3456 19:25:35.430507 Final RX Vref Byte 1 = 51 to rank1==
3457 19:25:35.433662 Dram Type= 6, Freq= 0, CH_1, rank 0
3458 19:25:35.439776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3459 19:25:35.439869 ==
3460 19:25:35.439992 DQS Delay:
3461 19:25:35.440078 DQS0 = 0, DQS1 = 0
3462 19:25:35.443175 DQM Delay:
3463 19:25:35.443266 DQM0 = 114, DQM1 = 112
3464 19:25:35.446612 DQ Delay:
3465 19:25:35.450192 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =114
3466 19:25:35.453675 DQ4 =110, DQ5 =122, DQ6 =124, DQ7 =110
3467 19:25:35.456666 DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =106
3468 19:25:35.460105 DQ12 =118, DQ13 =120, DQ14 =116, DQ15 =122
3469 19:25:35.460185
3470 19:25:35.460266
3471 19:25:35.469913 [DQSOSCAuto] RK0, (LSB)MR18= 0xf703, (MSB)MR19= 0x304, tDQSOscB0 = 408 ps tDQSOscB1 = 413 ps
3472 19:25:35.470001 CH1 RK0: MR19=304, MR18=F703
3473 19:25:35.476668 CH1_RK0: MR19=0x304, MR18=0xF703, DQSOSC=408, MR23=63, INC=39, DEC=26
3474 19:25:35.476752
3475 19:25:35.479741 ----->DramcWriteLeveling(PI) begin...
3476 19:25:35.479829 ==
3477 19:25:35.483302 Dram Type= 6, Freq= 0, CH_1, rank 1
3478 19:25:35.490216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3479 19:25:35.490298 ==
3480 19:25:35.493144 Write leveling (Byte 0): 25 => 25
3481 19:25:35.493229 Write leveling (Byte 1): 29 => 29
3482 19:25:35.496773 DramcWriteLeveling(PI) end<-----
3483 19:25:35.496851
3484 19:25:35.496932 ==
3485 19:25:35.499720 Dram Type= 6, Freq= 0, CH_1, rank 1
3486 19:25:35.506562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3487 19:25:35.506642 ==
3488 19:25:35.509871 [Gating] SW mode calibration
3489 19:25:35.516826 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3490 19:25:35.520072 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3491 19:25:35.526350 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3492 19:25:35.529284 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3493 19:25:35.532695 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3494 19:25:35.539605 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3495 19:25:35.542881 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3496 19:25:35.546011 0 15 20 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
3497 19:25:35.552726 0 15 24 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 0)
3498 19:25:35.556374 0 15 28 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
3499 19:25:35.559251 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3500 19:25:35.566208 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3501 19:25:35.569087 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3502 19:25:35.572737 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3503 19:25:35.579412 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3504 19:25:35.583005 1 0 20 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
3505 19:25:35.585832 1 0 24 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
3506 19:25:35.592583 1 0 28 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
3507 19:25:35.596209 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3508 19:25:35.599002 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3509 19:25:35.605391 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3510 19:25:35.608936 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3511 19:25:35.612351 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3512 19:25:35.618713 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3513 19:25:35.622134 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3514 19:25:35.625086 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3515 19:25:35.631825 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3516 19:25:35.635047 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 19:25:35.638388 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 19:25:35.644682 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3519 19:25:35.648143 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3520 19:25:35.651676 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3521 19:25:35.658484 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3522 19:25:35.661328 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3523 19:25:35.664877 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3524 19:25:35.671159 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3525 19:25:35.674647 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 19:25:35.677919 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 19:25:35.684379 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 19:25:35.688126 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 19:25:35.691162 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3530 19:25:35.697613 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3531 19:25:35.697695 Total UI for P1: 0, mck2ui 16
3532 19:25:35.704254 best dqsien dly found for B0: ( 1, 3, 24)
3533 19:25:35.708115 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3534 19:25:35.710696 Total UI for P1: 0, mck2ui 16
3535 19:25:35.714199 best dqsien dly found for B1: ( 1, 3, 28)
3536 19:25:35.717570 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3537 19:25:35.720981 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3538 19:25:35.721054
3539 19:25:35.724369 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3540 19:25:35.727363 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3541 19:25:35.730935 [Gating] SW calibration Done
3542 19:25:35.731006 ==
3543 19:25:35.733937 Dram Type= 6, Freq= 0, CH_1, rank 1
3544 19:25:35.740654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3545 19:25:35.740734 ==
3546 19:25:35.740797 RX Vref Scan: 0
3547 19:25:35.740856
3548 19:25:35.743717 RX Vref 0 -> 0, step: 1
3549 19:25:35.743785
3550 19:25:35.746902 RX Delay -40 -> 252, step: 8
3551 19:25:35.750165 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3552 19:25:35.753496 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3553 19:25:35.756988 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3554 19:25:35.763163 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3555 19:25:35.767081 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3556 19:25:35.769963 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3557 19:25:35.773445 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3558 19:25:35.776808 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3559 19:25:35.783363 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3560 19:25:35.786408 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3561 19:25:35.789938 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3562 19:25:35.792878 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3563 19:25:35.796374 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3564 19:25:35.802819 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3565 19:25:35.806013 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3566 19:25:35.809156 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3567 19:25:35.809233 ==
3568 19:25:35.812430 Dram Type= 6, Freq= 0, CH_1, rank 1
3569 19:25:35.815977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3570 19:25:35.819674 ==
3571 19:25:35.819754 DQS Delay:
3572 19:25:35.819818 DQS0 = 0, DQS1 = 0
3573 19:25:35.822596 DQM Delay:
3574 19:25:35.822679 DQM0 = 114, DQM1 = 111
3575 19:25:35.825857 DQ Delay:
3576 19:25:35.829252 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3577 19:25:35.832743 DQ4 =111, DQ5 =123, DQ6 =119, DQ7 =111
3578 19:25:35.835881 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =107
3579 19:25:35.838744 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3580 19:25:35.838824
3581 19:25:35.838887
3582 19:25:35.838946 ==
3583 19:25:35.842211 Dram Type= 6, Freq= 0, CH_1, rank 1
3584 19:25:35.845467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3585 19:25:35.845574 ==
3586 19:25:35.845666
3587 19:25:35.848900
3588 19:25:35.848980 TX Vref Scan disable
3589 19:25:35.852337 == TX Byte 0 ==
3590 19:25:35.855549 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3591 19:25:35.858679 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3592 19:25:35.862047 == TX Byte 1 ==
3593 19:25:35.865891 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3594 19:25:35.868908 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3595 19:25:35.868989 ==
3596 19:25:35.872600 Dram Type= 6, Freq= 0, CH_1, rank 1
3597 19:25:35.878768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3598 19:25:35.878850 ==
3599 19:25:35.889713 TX Vref=22, minBit 3, minWin=25, winSum=425
3600 19:25:35.892691 TX Vref=24, minBit 6, minWin=25, winSum=427
3601 19:25:35.896128 TX Vref=26, minBit 1, minWin=26, winSum=432
3602 19:25:35.899439 TX Vref=28, minBit 1, minWin=26, winSum=435
3603 19:25:35.902836 TX Vref=30, minBit 1, minWin=26, winSum=434
3604 19:25:35.909396 TX Vref=32, minBit 0, minWin=26, winSum=434
3605 19:25:35.912470 [TxChooseVref] Worse bit 1, Min win 26, Win sum 435, Final Vref 28
3606 19:25:35.912546
3607 19:25:35.916126 Final TX Range 1 Vref 28
3608 19:25:35.916205
3609 19:25:35.916284 ==
3610 19:25:35.918979 Dram Type= 6, Freq= 0, CH_1, rank 1
3611 19:25:35.922618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3612 19:25:35.925887 ==
3613 19:25:35.925963
3614 19:25:35.926040
3615 19:25:35.926114 TX Vref Scan disable
3616 19:25:35.929049 == TX Byte 0 ==
3617 19:25:35.932538 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3618 19:25:35.938879 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3619 19:25:35.938964 == TX Byte 1 ==
3620 19:25:35.942144 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3621 19:25:35.949188 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3622 19:25:35.949273
3623 19:25:35.949337 [DATLAT]
3624 19:25:35.949397 Freq=1200, CH1 RK1
3625 19:25:35.949454
3626 19:25:35.952432 DATLAT Default: 0xd
3627 19:25:35.955419 0, 0xFFFF, sum = 0
3628 19:25:35.955501 1, 0xFFFF, sum = 0
3629 19:25:35.958883 2, 0xFFFF, sum = 0
3630 19:25:35.958965 3, 0xFFFF, sum = 0
3631 19:25:35.962191 4, 0xFFFF, sum = 0
3632 19:25:35.962280 5, 0xFFFF, sum = 0
3633 19:25:35.965316 6, 0xFFFF, sum = 0
3634 19:25:35.965398 7, 0xFFFF, sum = 0
3635 19:25:35.968541 8, 0xFFFF, sum = 0
3636 19:25:35.968623 9, 0xFFFF, sum = 0
3637 19:25:35.971934 10, 0xFFFF, sum = 0
3638 19:25:35.972057 11, 0xFFFF, sum = 0
3639 19:25:35.974942 12, 0x0, sum = 1
3640 19:25:35.975024 13, 0x0, sum = 2
3641 19:25:35.978217 14, 0x0, sum = 3
3642 19:25:35.978299 15, 0x0, sum = 4
3643 19:25:35.981764 best_step = 13
3644 19:25:35.981845
3645 19:25:35.981908 ==
3646 19:25:35.984733 Dram Type= 6, Freq= 0, CH_1, rank 1
3647 19:25:35.988400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3648 19:25:35.988482 ==
3649 19:25:35.991500 RX Vref Scan: 0
3650 19:25:35.991606
3651 19:25:35.991697 RX Vref 0 -> 0, step: 1
3652 19:25:35.991784
3653 19:25:35.995060 RX Delay -13 -> 252, step: 4
3654 19:25:36.001480 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3655 19:25:36.005008 iDelay=195, Bit 1, Center 110 (43 ~ 178) 136
3656 19:25:36.007889 iDelay=195, Bit 2, Center 106 (39 ~ 174) 136
3657 19:25:36.011268 iDelay=195, Bit 3, Center 112 (43 ~ 182) 140
3658 19:25:36.014746 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3659 19:25:36.021262 iDelay=195, Bit 5, Center 124 (55 ~ 194) 140
3660 19:25:36.024671 iDelay=195, Bit 6, Center 122 (55 ~ 190) 136
3661 19:25:36.027708 iDelay=195, Bit 7, Center 112 (43 ~ 182) 140
3662 19:25:36.030870 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3663 19:25:36.037508 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3664 19:25:36.040873 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3665 19:25:36.044187 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3666 19:25:36.047868 iDelay=195, Bit 12, Center 120 (59 ~ 182) 124
3667 19:25:36.050688 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3668 19:25:36.057311 iDelay=195, Bit 14, Center 116 (55 ~ 178) 124
3669 19:25:36.060519 iDelay=195, Bit 15, Center 122 (59 ~ 186) 128
3670 19:25:36.060600 ==
3671 19:25:36.064237 Dram Type= 6, Freq= 0, CH_1, rank 1
3672 19:25:36.067767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3673 19:25:36.067873 ==
3674 19:25:36.070524 DQS Delay:
3675 19:25:36.070604 DQS0 = 0, DQS1 = 0
3676 19:25:36.070668 DQM Delay:
3677 19:25:36.074250 DQM0 = 114, DQM1 = 112
3678 19:25:36.074402 DQ Delay:
3679 19:25:36.077614 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =112
3680 19:25:36.081000 DQ4 =112, DQ5 =124, DQ6 =122, DQ7 =112
3681 19:25:36.087347 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
3682 19:25:36.090509 DQ12 =120, DQ13 =118, DQ14 =116, DQ15 =122
3683 19:25:36.090589
3684 19:25:36.090653
3685 19:25:36.097387 [DQSOSCAuto] RK1, (LSB)MR18= 0xf607, (MSB)MR19= 0x304, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps
3686 19:25:36.100766 CH1 RK1: MR19=304, MR18=F607
3687 19:25:36.106681 CH1_RK1: MR19=0x304, MR18=0xF607, DQSOSC=407, MR23=63, INC=39, DEC=26
3688 19:25:36.110172 [RxdqsGatingPostProcess] freq 1200
3689 19:25:36.116585 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3690 19:25:36.120305 best DQS0 dly(2T, 0.5T) = (0, 11)
3691 19:25:36.120387 best DQS1 dly(2T, 0.5T) = (0, 11)
3692 19:25:36.123242 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3693 19:25:36.126910 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3694 19:25:36.130185 best DQS0 dly(2T, 0.5T) = (0, 11)
3695 19:25:36.133211 best DQS1 dly(2T, 0.5T) = (0, 11)
3696 19:25:36.136577 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3697 19:25:36.139958 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3698 19:25:36.142742 Pre-setting of DQS Precalculation
3699 19:25:36.149619 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3700 19:25:36.156131 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3701 19:25:36.162577 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3702 19:25:36.162658
3703 19:25:36.162721
3704 19:25:36.165996 [Calibration Summary] 2400 Mbps
3705 19:25:36.166083 CH 0, Rank 0
3706 19:25:36.169183 SW Impedance : PASS
3707 19:25:36.172470 DUTY Scan : NO K
3708 19:25:36.172555 ZQ Calibration : PASS
3709 19:25:36.175933 Jitter Meter : NO K
3710 19:25:36.179326 CBT Training : PASS
3711 19:25:36.179410 Write leveling : PASS
3712 19:25:36.182660 RX DQS gating : PASS
3713 19:25:36.185371 RX DQ/DQS(RDDQC) : PASS
3714 19:25:36.185452 TX DQ/DQS : PASS
3715 19:25:36.188701 RX DATLAT : PASS
3716 19:25:36.192160 RX DQ/DQS(Engine): PASS
3717 19:25:36.192241 TX OE : NO K
3718 19:25:36.195721 All Pass.
3719 19:25:36.195828
3720 19:25:36.195953 CH 0, Rank 1
3721 19:25:36.198628 SW Impedance : PASS
3722 19:25:36.198709 DUTY Scan : NO K
3723 19:25:36.202171 ZQ Calibration : PASS
3724 19:25:36.205291 Jitter Meter : NO K
3725 19:25:36.205372 CBT Training : PASS
3726 19:25:36.208670 Write leveling : PASS
3727 19:25:36.211798 RX DQS gating : PASS
3728 19:25:36.211925 RX DQ/DQS(RDDQC) : PASS
3729 19:25:36.215072 TX DQ/DQS : PASS
3730 19:25:36.218763 RX DATLAT : PASS
3731 19:25:36.218844 RX DQ/DQS(Engine): PASS
3732 19:25:36.221740 TX OE : NO K
3733 19:25:36.221821 All Pass.
3734 19:25:36.221884
3735 19:25:36.225278 CH 1, Rank 0
3736 19:25:36.225359 SW Impedance : PASS
3737 19:25:36.228293 DUTY Scan : NO K
3738 19:25:36.231922 ZQ Calibration : PASS
3739 19:25:36.232003 Jitter Meter : NO K
3740 19:25:36.234739 CBT Training : PASS
3741 19:25:36.238341 Write leveling : PASS
3742 19:25:36.238422 RX DQS gating : PASS
3743 19:25:36.241788 RX DQ/DQS(RDDQC) : PASS
3744 19:25:36.244830 TX DQ/DQS : PASS
3745 19:25:36.244910 RX DATLAT : PASS
3746 19:25:36.248342 RX DQ/DQS(Engine): PASS
3747 19:25:36.248423 TX OE : NO K
3748 19:25:36.251215 All Pass.
3749 19:25:36.251295
3750 19:25:36.251358 CH 1, Rank 1
3751 19:25:36.254655 SW Impedance : PASS
3752 19:25:36.254739 DUTY Scan : NO K
3753 19:25:36.257985 ZQ Calibration : PASS
3754 19:25:36.261206 Jitter Meter : NO K
3755 19:25:36.261287 CBT Training : PASS
3756 19:25:36.264302 Write leveling : PASS
3757 19:25:36.267797 RX DQS gating : PASS
3758 19:25:36.267925 RX DQ/DQS(RDDQC) : PASS
3759 19:25:36.271813 TX DQ/DQS : PASS
3760 19:25:36.274539 RX DATLAT : PASS
3761 19:25:36.274620 RX DQ/DQS(Engine): PASS
3762 19:25:36.278233 TX OE : NO K
3763 19:25:36.278314 All Pass.
3764 19:25:36.278377
3765 19:25:36.281270 DramC Write-DBI off
3766 19:25:36.284407 PER_BANK_REFRESH: Hybrid Mode
3767 19:25:36.284488 TX_TRACKING: ON
3768 19:25:36.294245 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3769 19:25:36.297209 [FAST_K] Save calibration result to emmc
3770 19:25:36.300826 dramc_set_vcore_voltage set vcore to 650000
3771 19:25:36.304402 Read voltage for 600, 5
3772 19:25:36.304508 Vio18 = 0
3773 19:25:36.307277 Vcore = 650000
3774 19:25:36.307373 Vdram = 0
3775 19:25:36.307465 Vddq = 0
3776 19:25:36.307551 Vmddr = 0
3777 19:25:36.314327 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3778 19:25:36.320565 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3779 19:25:36.320646 MEM_TYPE=3, freq_sel=19
3780 19:25:36.323667 sv_algorithm_assistance_LP4_1600
3781 19:25:36.327483 ============ PULL DRAM RESETB DOWN ============
3782 19:25:36.333847 ========== PULL DRAM RESETB DOWN end =========
3783 19:25:36.336834 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3784 19:25:36.340447 ===================================
3785 19:25:36.343729 LPDDR4 DRAM CONFIGURATION
3786 19:25:36.347030 ===================================
3787 19:25:36.347111 EX_ROW_EN[0] = 0x0
3788 19:25:36.349985 EX_ROW_EN[1] = 0x0
3789 19:25:36.350066 LP4Y_EN = 0x0
3790 19:25:36.353522 WORK_FSP = 0x0
3791 19:25:36.356339 WL = 0x2
3792 19:25:36.356420 RL = 0x2
3793 19:25:36.359701 BL = 0x2
3794 19:25:36.359810 RPST = 0x0
3795 19:25:36.362973 RD_PRE = 0x0
3796 19:25:36.363053 WR_PRE = 0x1
3797 19:25:36.366404 WR_PST = 0x0
3798 19:25:36.366488 DBI_WR = 0x0
3799 19:25:36.369935 DBI_RD = 0x0
3800 19:25:36.370041 OTF = 0x1
3801 19:25:36.373159 ===================================
3802 19:25:36.376193 ===================================
3803 19:25:36.379770 ANA top config
3804 19:25:36.382885 ===================================
3805 19:25:36.382966 DLL_ASYNC_EN = 0
3806 19:25:36.385970 ALL_SLAVE_EN = 1
3807 19:25:36.389503 NEW_RANK_MODE = 1
3808 19:25:36.392973 DLL_IDLE_MODE = 1
3809 19:25:36.396142 LP45_APHY_COMB_EN = 1
3810 19:25:36.396224 TX_ODT_DIS = 1
3811 19:25:36.399124 NEW_8X_MODE = 1
3812 19:25:36.402633 ===================================
3813 19:25:36.405980 ===================================
3814 19:25:36.409445 data_rate = 1200
3815 19:25:36.412432 CKR = 1
3816 19:25:36.415944 DQ_P2S_RATIO = 8
3817 19:25:36.418914 ===================================
3818 19:25:36.422244 CA_P2S_RATIO = 8
3819 19:25:36.422327 DQ_CA_OPEN = 0
3820 19:25:36.425780 DQ_SEMI_OPEN = 0
3821 19:25:36.428825 CA_SEMI_OPEN = 0
3822 19:25:36.432308 CA_FULL_RATE = 0
3823 19:25:36.435577 DQ_CKDIV4_EN = 1
3824 19:25:36.439105 CA_CKDIV4_EN = 1
3825 19:25:36.439186 CA_PREDIV_EN = 0
3826 19:25:36.442077 PH8_DLY = 0
3827 19:25:36.445463 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3828 19:25:36.448404 DQ_AAMCK_DIV = 4
3829 19:25:36.451886 CA_AAMCK_DIV = 4
3830 19:25:36.455411 CA_ADMCK_DIV = 4
3831 19:25:36.455492 DQ_TRACK_CA_EN = 0
3832 19:25:36.458331 CA_PICK = 600
3833 19:25:36.461718 CA_MCKIO = 600
3834 19:25:36.465167 MCKIO_SEMI = 0
3835 19:25:36.468180 PLL_FREQ = 2288
3836 19:25:36.471592 DQ_UI_PI_RATIO = 32
3837 19:25:36.474911 CA_UI_PI_RATIO = 0
3838 19:25:36.478210 ===================================
3839 19:25:36.481871 ===================================
3840 19:25:36.484785 memory_type:LPDDR4
3841 19:25:36.484866 GP_NUM : 10
3842 19:25:36.488343 SRAM_EN : 1
3843 19:25:36.488425 MD32_EN : 0
3844 19:25:36.491270 ===================================
3845 19:25:36.494558 [ANA_INIT] >>>>>>>>>>>>>>
3846 19:25:36.497718 <<<<<< [CONFIGURE PHASE]: ANA_TX
3847 19:25:36.501145 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3848 19:25:36.504582 ===================================
3849 19:25:36.507629 data_rate = 1200,PCW = 0X5800
3850 19:25:36.511253 ===================================
3851 19:25:36.514281 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3852 19:25:36.520870 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3853 19:25:36.524441 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3854 19:25:36.530626 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3855 19:25:36.533858 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3856 19:25:36.537111 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3857 19:25:36.537221 [ANA_INIT] flow start
3858 19:25:36.540840 [ANA_INIT] PLL >>>>>>>>
3859 19:25:36.544192 [ANA_INIT] PLL <<<<<<<<
3860 19:25:36.544273 [ANA_INIT] MIDPI >>>>>>>>
3861 19:25:36.547158 [ANA_INIT] MIDPI <<<<<<<<
3862 19:25:36.550837 [ANA_INIT] DLL >>>>>>>>
3863 19:25:36.550920 [ANA_INIT] flow end
3864 19:25:36.557180 ============ LP4 DIFF to SE enter ============
3865 19:25:36.560056 ============ LP4 DIFF to SE exit ============
3866 19:25:36.563598 [ANA_INIT] <<<<<<<<<<<<<
3867 19:25:36.567026 [Flow] Enable top DCM control >>>>>
3868 19:25:36.570486 [Flow] Enable top DCM control <<<<<
3869 19:25:36.573453 Enable DLL master slave shuffle
3870 19:25:36.577197 ==============================================================
3871 19:25:36.580243 Gating Mode config
3872 19:25:36.583648 ==============================================================
3873 19:25:36.586938 Config description:
3874 19:25:36.596165 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3875 19:25:36.603089 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3876 19:25:36.606061 SELPH_MODE 0: By rank 1: By Phase
3877 19:25:36.612997 ==============================================================
3878 19:25:36.616123 GAT_TRACK_EN = 1
3879 19:25:36.619764 RX_GATING_MODE = 2
3880 19:25:36.622753 RX_GATING_TRACK_MODE = 2
3881 19:25:36.626233 SELPH_MODE = 1
3882 19:25:36.629374 PICG_EARLY_EN = 1
3883 19:25:36.632527 VALID_LAT_VALUE = 1
3884 19:25:36.636141 ==============================================================
3885 19:25:36.639348 Enter into Gating configuration >>>>
3886 19:25:36.642625 Exit from Gating configuration <<<<
3887 19:25:36.645673 Enter into DVFS_PRE_config >>>>>
3888 19:25:36.659043 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3889 19:25:36.662580 Exit from DVFS_PRE_config <<<<<
3890 19:25:36.662653 Enter into PICG configuration >>>>
3891 19:25:36.665543 Exit from PICG configuration <<<<
3892 19:25:36.669160 [RX_INPUT] configuration >>>>>
3893 19:25:36.672001 [RX_INPUT] configuration <<<<<
3894 19:25:36.678939 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3895 19:25:36.682174 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3896 19:25:36.688713 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3897 19:25:36.695518 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3898 19:25:36.701913 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3899 19:25:36.708465 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3900 19:25:36.711792 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3901 19:25:36.715328 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3902 19:25:36.721521 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3903 19:25:36.724976 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3904 19:25:36.728317 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3905 19:25:36.731402 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3906 19:25:36.734605 ===================================
3907 19:25:36.737622 LPDDR4 DRAM CONFIGURATION
3908 19:25:36.741334 ===================================
3909 19:25:36.744559 EX_ROW_EN[0] = 0x0
3910 19:25:36.744639 EX_ROW_EN[1] = 0x0
3911 19:25:36.747430 LP4Y_EN = 0x0
3912 19:25:36.747497 WORK_FSP = 0x0
3913 19:25:36.750961 WL = 0x2
3914 19:25:36.754514 RL = 0x2
3915 19:25:36.754584 BL = 0x2
3916 19:25:36.757791 RPST = 0x0
3917 19:25:36.757859 RD_PRE = 0x0
3918 19:25:36.760655 WR_PRE = 0x1
3919 19:25:36.760721 WR_PST = 0x0
3920 19:25:36.764412 DBI_WR = 0x0
3921 19:25:36.764504 DBI_RD = 0x0
3922 19:25:36.767471 OTF = 0x1
3923 19:25:36.771010 ===================================
3924 19:25:36.773789 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3925 19:25:36.777296 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3926 19:25:36.784349 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3927 19:25:36.787241 ===================================
3928 19:25:36.787319 LPDDR4 DRAM CONFIGURATION
3929 19:25:36.790770 ===================================
3930 19:25:36.793633 EX_ROW_EN[0] = 0x10
3931 19:25:36.793709 EX_ROW_EN[1] = 0x0
3932 19:25:36.797114 LP4Y_EN = 0x0
3933 19:25:36.797190 WORK_FSP = 0x0
3934 19:25:36.800472 WL = 0x2
3935 19:25:36.803604 RL = 0x2
3936 19:25:36.803676 BL = 0x2
3937 19:25:36.807066 RPST = 0x0
3938 19:25:36.807135 RD_PRE = 0x0
3939 19:25:36.809981 WR_PRE = 0x1
3940 19:25:36.810051 WR_PST = 0x0
3941 19:25:36.813444 DBI_WR = 0x0
3942 19:25:36.813512 DBI_RD = 0x0
3943 19:25:36.817045 OTF = 0x1
3944 19:25:36.820113 ===================================
3945 19:25:36.826580 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3946 19:25:36.829967 nWR fixed to 30
3947 19:25:36.830044 [ModeRegInit_LP4] CH0 RK0
3948 19:25:36.833438 [ModeRegInit_LP4] CH0 RK1
3949 19:25:36.836853 [ModeRegInit_LP4] CH1 RK0
3950 19:25:36.839580 [ModeRegInit_LP4] CH1 RK1
3951 19:25:36.839651 match AC timing 17
3952 19:25:36.846751 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3953 19:25:36.849423 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3954 19:25:36.852980 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3955 19:25:36.859712 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3956 19:25:36.862748 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3957 19:25:36.862829 ==
3958 19:25:36.866136 Dram Type= 6, Freq= 0, CH_0, rank 0
3959 19:25:36.869434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3960 19:25:36.869516 ==
3961 19:25:36.876131 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3962 19:25:36.882254 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3963 19:25:36.885983 [CA 0] Center 36 (6~67) winsize 62
3964 19:25:36.889576 [CA 1] Center 36 (6~67) winsize 62
3965 19:25:36.892523 [CA 2] Center 34 (4~65) winsize 62
3966 19:25:36.895552 [CA 3] Center 34 (3~65) winsize 63
3967 19:25:36.899161 [CA 4] Center 33 (3~64) winsize 62
3968 19:25:36.902769 [CA 5] Center 33 (3~64) winsize 62
3969 19:25:36.902850
3970 19:25:36.905608 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3971 19:25:36.905688
3972 19:25:36.908669 [CATrainingPosCal] consider 1 rank data
3973 19:25:36.912282 u2DelayCellTimex100 = 270/100 ps
3974 19:25:36.915812 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3975 19:25:36.918846 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3976 19:25:36.922309 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3977 19:25:36.925460 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3978 19:25:36.931802 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3979 19:25:36.935440 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3980 19:25:36.935513
3981 19:25:36.938278 CA PerBit enable=1, Macro0, CA PI delay=33
3982 19:25:36.938356
3983 19:25:36.941581 [CBTSetCACLKResult] CA Dly = 33
3984 19:25:36.941651 CS Dly: 5 (0~36)
3985 19:25:36.941710 ==
3986 19:25:36.945250 Dram Type= 6, Freq= 0, CH_0, rank 1
3987 19:25:36.951853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3988 19:25:36.951966 ==
3989 19:25:36.955034 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3990 19:25:36.961689 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3991 19:25:36.965049 [CA 0] Center 36 (6~67) winsize 62
3992 19:25:36.968246 [CA 1] Center 36 (6~67) winsize 62
3993 19:25:36.971750 [CA 2] Center 34 (4~65) winsize 62
3994 19:25:36.975387 [CA 3] Center 34 (4~65) winsize 62
3995 19:25:36.978315 [CA 4] Center 33 (3~64) winsize 62
3996 19:25:36.981333 [CA 5] Center 33 (3~64) winsize 62
3997 19:25:36.981433
3998 19:25:36.984899 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3999 19:25:36.985000
4000 19:25:36.988097 [CATrainingPosCal] consider 2 rank data
4001 19:25:36.991087 u2DelayCellTimex100 = 270/100 ps
4002 19:25:36.994642 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
4003 19:25:36.998319 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
4004 19:25:37.004173 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4005 19:25:37.007670 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4006 19:25:37.010679 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4007 19:25:37.014163 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4008 19:25:37.014238
4009 19:25:37.017840 CA PerBit enable=1, Macro0, CA PI delay=33
4010 19:25:37.017915
4011 19:25:37.020834 [CBTSetCACLKResult] CA Dly = 33
4012 19:25:37.024347 CS Dly: 5 (0~37)
4013 19:25:37.024418
4014 19:25:37.027370 ----->DramcWriteLeveling(PI) begin...
4015 19:25:37.027453 ==
4016 19:25:37.030981 Dram Type= 6, Freq= 0, CH_0, rank 0
4017 19:25:37.033869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4018 19:25:37.033940 ==
4019 19:25:37.037487 Write leveling (Byte 0): 34 => 34
4020 19:25:37.040469 Write leveling (Byte 1): 29 => 29
4021 19:25:37.044312 DramcWriteLeveling(PI) end<-----
4022 19:25:37.044395
4023 19:25:37.044459 ==
4024 19:25:37.047236 Dram Type= 6, Freq= 0, CH_0, rank 0
4025 19:25:37.050797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4026 19:25:37.050878 ==
4027 19:25:37.053646 [Gating] SW mode calibration
4028 19:25:37.060389 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4029 19:25:37.066882 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4030 19:25:37.070315 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4031 19:25:37.073363 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4032 19:25:37.080338 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4033 19:25:37.083137 0 9 12 | B1->B0 | 3434 3131 | 1 1 | (1 0) (1 0)
4034 19:25:37.087155 0 9 16 | B1->B0 | 2e2e 2525 | 0 0 | (1 1) (0 0)
4035 19:25:37.093287 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4036 19:25:37.096421 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4037 19:25:37.100071 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4038 19:25:37.106350 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4039 19:25:37.109375 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4040 19:25:37.112792 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4041 19:25:37.119135 0 10 12 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (1 1)
4042 19:25:37.122775 0 10 16 | B1->B0 | 3d3d 4242 | 1 0 | (0 0) (1 1)
4043 19:25:37.126347 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4044 19:25:37.132474 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4045 19:25:37.136109 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4046 19:25:37.139554 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4047 19:25:37.145928 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4048 19:25:37.148751 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4049 19:25:37.152551 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4050 19:25:37.158958 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4051 19:25:37.162376 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 19:25:37.165399 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 19:25:37.171814 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 19:25:37.175406 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 19:25:37.178577 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 19:25:37.185107 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 19:25:37.188460 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 19:25:37.192132 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 19:25:37.198683 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 19:25:37.201654 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 19:25:37.205118 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 19:25:37.211703 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 19:25:37.215298 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 19:25:37.218329 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 19:25:37.224789 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4066 19:25:37.227956 Total UI for P1: 0, mck2ui 16
4067 19:25:37.231683 best dqsien dly found for B0: ( 0, 13, 10)
4068 19:25:37.234563 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4069 19:25:37.238103 Total UI for P1: 0, mck2ui 16
4070 19:25:37.241571 best dqsien dly found for B1: ( 0, 13, 12)
4071 19:25:37.244649 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4072 19:25:37.248283 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4073 19:25:37.248364
4074 19:25:37.251880 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4075 19:25:37.257518 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4076 19:25:37.257599 [Gating] SW calibration Done
4077 19:25:37.260743 ==
4078 19:25:37.264658 Dram Type= 6, Freq= 0, CH_0, rank 0
4079 19:25:37.267505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4080 19:25:37.267617 ==
4081 19:25:37.267681 RX Vref Scan: 0
4082 19:25:37.267740
4083 19:25:37.270919 RX Vref 0 -> 0, step: 1
4084 19:25:37.271000
4085 19:25:37.274398 RX Delay -230 -> 252, step: 16
4086 19:25:37.277414 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4087 19:25:37.280545 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4088 19:25:37.287122 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4089 19:25:37.290558 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4090 19:25:37.294163 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4091 19:25:37.297465 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4092 19:25:37.303561 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4093 19:25:37.307168 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4094 19:25:37.310534 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4095 19:25:37.313808 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4096 19:25:37.320263 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4097 19:25:37.323822 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4098 19:25:37.326977 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4099 19:25:37.330307 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4100 19:25:37.336906 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4101 19:25:37.340257 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4102 19:25:37.340339 ==
4103 19:25:37.343670 Dram Type= 6, Freq= 0, CH_0, rank 0
4104 19:25:37.346366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4105 19:25:37.346447 ==
4106 19:25:37.350047 DQS Delay:
4107 19:25:37.350128 DQS0 = 0, DQS1 = 0
4108 19:25:37.350218 DQM Delay:
4109 19:25:37.353102 DQM0 = 42, DQM1 = 33
4110 19:25:37.353183 DQ Delay:
4111 19:25:37.356461 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4112 19:25:37.359490 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4113 19:25:37.362791 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4114 19:25:37.366147 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4115 19:25:37.366229
4116 19:25:37.366292
4117 19:25:37.366351 ==
4118 19:25:37.369413 Dram Type= 6, Freq= 0, CH_0, rank 0
4119 19:25:37.375836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4120 19:25:37.375958 ==
4121 19:25:37.376024
4122 19:25:37.376083
4123 19:25:37.376141 TX Vref Scan disable
4124 19:25:37.380096 == TX Byte 0 ==
4125 19:25:37.383396 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4126 19:25:37.389802 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4127 19:25:37.389884 == TX Byte 1 ==
4128 19:25:37.393274 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4129 19:25:37.399428 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4130 19:25:37.399510 ==
4131 19:25:37.403289 Dram Type= 6, Freq= 0, CH_0, rank 0
4132 19:25:37.406117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4133 19:25:37.406198 ==
4134 19:25:37.406262
4135 19:25:37.406321
4136 19:25:37.409532 TX Vref Scan disable
4137 19:25:37.413191 == TX Byte 0 ==
4138 19:25:37.416461 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4139 19:25:37.419374 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4140 19:25:37.422519 == TX Byte 1 ==
4141 19:25:37.426199 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4142 19:25:37.429194 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4143 19:25:37.429275
4144 19:25:37.432588 [DATLAT]
4145 19:25:37.432669 Freq=600, CH0 RK0
4146 19:25:37.432733
4147 19:25:37.436074 DATLAT Default: 0x9
4148 19:25:37.436155 0, 0xFFFF, sum = 0
4149 19:25:37.439094 1, 0xFFFF, sum = 0
4150 19:25:37.439176 2, 0xFFFF, sum = 0
4151 19:25:37.442641 3, 0xFFFF, sum = 0
4152 19:25:37.442723 4, 0xFFFF, sum = 0
4153 19:25:37.445576 5, 0xFFFF, sum = 0
4154 19:25:37.445658 6, 0xFFFF, sum = 0
4155 19:25:37.449059 7, 0xFFFF, sum = 0
4156 19:25:37.449141 8, 0x0, sum = 1
4157 19:25:37.452423 9, 0x0, sum = 2
4158 19:25:37.452505 10, 0x0, sum = 3
4159 19:25:37.455846 11, 0x0, sum = 4
4160 19:25:37.455949 best_step = 9
4161 19:25:37.456013
4162 19:25:37.456072 ==
4163 19:25:37.458682 Dram Type= 6, Freq= 0, CH_0, rank 0
4164 19:25:37.462264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4165 19:25:37.465334 ==
4166 19:25:37.465415 RX Vref Scan: 1
4167 19:25:37.465479
4168 19:25:37.468727 RX Vref 0 -> 0, step: 1
4169 19:25:37.468808
4170 19:25:37.472335 RX Delay -195 -> 252, step: 8
4171 19:25:37.472416
4172 19:25:37.475216 Set Vref, RX VrefLevel [Byte0]: 52
4173 19:25:37.478411 [Byte1]: 60
4174 19:25:37.478510
4175 19:25:37.481899 Final RX Vref Byte 0 = 52 to rank0
4176 19:25:37.485330 Final RX Vref Byte 1 = 60 to rank0
4177 19:25:37.488598 Final RX Vref Byte 0 = 52 to rank1
4178 19:25:37.491821 Final RX Vref Byte 1 = 60 to rank1==
4179 19:25:37.495501 Dram Type= 6, Freq= 0, CH_0, rank 0
4180 19:25:37.498129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4181 19:25:37.498210 ==
4182 19:25:37.501664 DQS Delay:
4183 19:25:37.501770 DQS0 = 0, DQS1 = 0
4184 19:25:37.501862 DQM Delay:
4185 19:25:37.505131 DQM0 = 41, DQM1 = 33
4186 19:25:37.505211 DQ Delay:
4187 19:25:37.508328 DQ0 =44, DQ1 =40, DQ2 =36, DQ3 =36
4188 19:25:37.511489 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4189 19:25:37.515150 DQ8 =24, DQ9 =16, DQ10 =32, DQ11 =28
4190 19:25:37.518292 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4191 19:25:37.518373
4192 19:25:37.518437
4193 19:25:37.527897 [DQSOSCAuto] RK0, (LSB)MR18= 0x453d, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
4194 19:25:37.531427 CH0 RK0: MR19=808, MR18=453D
4195 19:25:37.537649 CH0_RK0: MR19=0x808, MR18=0x453D, DQSOSC=396, MR23=63, INC=167, DEC=111
4196 19:25:37.537730
4197 19:25:37.541341 ----->DramcWriteLeveling(PI) begin...
4198 19:25:37.541423 ==
4199 19:25:37.544230 Dram Type= 6, Freq= 0, CH_0, rank 1
4200 19:25:37.547681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4201 19:25:37.547762 ==
4202 19:25:37.550997 Write leveling (Byte 0): 33 => 33
4203 19:25:37.554044 Write leveling (Byte 1): 28 => 28
4204 19:25:37.557462 DramcWriteLeveling(PI) end<-----
4205 19:25:37.557542
4206 19:25:37.557605 ==
4207 19:25:37.560965 Dram Type= 6, Freq= 0, CH_0, rank 1
4208 19:25:37.564359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4209 19:25:37.564441 ==
4210 19:25:37.567375 [Gating] SW mode calibration
4211 19:25:37.573730 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4212 19:25:37.580863 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4213 19:25:37.583706 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4214 19:25:37.587150 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4215 19:25:37.593651 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4216 19:25:37.597159 0 9 12 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 1)
4217 19:25:37.600233 0 9 16 | B1->B0 | 2d2d 2525 | 0 0 | (0 1) (0 0)
4218 19:25:37.606908 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4219 19:25:37.610562 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4220 19:25:37.613229 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4221 19:25:37.619947 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4222 19:25:37.623471 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4223 19:25:37.626526 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4224 19:25:37.633273 0 10 12 | B1->B0 | 2424 3636 | 0 0 | (0 0) (0 0)
4225 19:25:37.636166 0 10 16 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
4226 19:25:37.639646 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4227 19:25:37.646544 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4228 19:25:37.649456 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4229 19:25:37.652987 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4230 19:25:37.659546 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4231 19:25:37.663059 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4232 19:25:37.666409 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4233 19:25:37.673042 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4234 19:25:37.675749 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 19:25:37.679351 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 19:25:37.685799 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 19:25:37.689424 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 19:25:37.692159 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 19:25:37.698770 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 19:25:37.702364 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 19:25:37.708536 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 19:25:37.712436 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 19:25:37.715493 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 19:25:37.722260 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 19:25:37.725177 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 19:25:37.728748 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 19:25:37.734899 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 19:25:37.738078 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4249 19:25:37.741435 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4250 19:25:37.744811 Total UI for P1: 0, mck2ui 16
4251 19:25:37.748327 best dqsien dly found for B0: ( 0, 13, 12)
4252 19:25:37.754817 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4253 19:25:37.754899 Total UI for P1: 0, mck2ui 16
4254 19:25:37.757924 best dqsien dly found for B1: ( 0, 13, 16)
4255 19:25:37.764994 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4256 19:25:37.767717 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4257 19:25:37.767831
4258 19:25:37.771489 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4259 19:25:37.774708 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4260 19:25:37.777664 [Gating] SW calibration Done
4261 19:25:37.777746 ==
4262 19:25:37.781041 Dram Type= 6, Freq= 0, CH_0, rank 1
4263 19:25:37.784258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4264 19:25:37.784371 ==
4265 19:25:37.788171 RX Vref Scan: 0
4266 19:25:37.788267
4267 19:25:37.788346 RX Vref 0 -> 0, step: 1
4268 19:25:37.788406
4269 19:25:37.790899 RX Delay -230 -> 252, step: 16
4270 19:25:37.797909 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4271 19:25:37.800898 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4272 19:25:37.804437 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4273 19:25:37.807781 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4274 19:25:37.810726 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4275 19:25:37.817558 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4276 19:25:37.821078 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4277 19:25:37.823805 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4278 19:25:37.827175 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4279 19:25:37.834181 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4280 19:25:37.837596 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4281 19:25:37.840347 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4282 19:25:37.843608 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4283 19:25:37.850505 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4284 19:25:37.854007 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4285 19:25:37.857115 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4286 19:25:37.857233 ==
4287 19:25:37.860420 Dram Type= 6, Freq= 0, CH_0, rank 1
4288 19:25:37.863797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4289 19:25:37.866918 ==
4290 19:25:37.866998 DQS Delay:
4291 19:25:37.867062 DQS0 = 0, DQS1 = 0
4292 19:25:37.870374 DQM Delay:
4293 19:25:37.870455 DQM0 = 44, DQM1 = 35
4294 19:25:37.873307 DQ Delay:
4295 19:25:37.876850 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4296 19:25:37.876932 DQ4 =41, DQ5 =41, DQ6 =57, DQ7 =49
4297 19:25:37.879730 DQ8 =25, DQ9 =17, DQ10 =41, DQ11 =33
4298 19:25:37.886541 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4299 19:25:37.886621
4300 19:25:37.886684
4301 19:25:37.886743 ==
4302 19:25:37.890059 Dram Type= 6, Freq= 0, CH_0, rank 1
4303 19:25:37.892922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4304 19:25:37.893003 ==
4305 19:25:37.893068
4306 19:25:37.893126
4307 19:25:37.896447 TX Vref Scan disable
4308 19:25:37.896528 == TX Byte 0 ==
4309 19:25:37.902894 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4310 19:25:37.906407 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4311 19:25:37.909492 == TX Byte 1 ==
4312 19:25:37.913005 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4313 19:25:37.916303 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4314 19:25:37.916385 ==
4315 19:25:37.919533 Dram Type= 6, Freq= 0, CH_0, rank 1
4316 19:25:37.922823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4317 19:25:37.925677 ==
4318 19:25:37.925758
4319 19:25:37.925822
4320 19:25:37.925882 TX Vref Scan disable
4321 19:25:37.930231 == TX Byte 0 ==
4322 19:25:37.933030 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4323 19:25:37.940333 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4324 19:25:37.940414 == TX Byte 1 ==
4325 19:25:37.942968 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4326 19:25:37.949422 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4327 19:25:37.949504
4328 19:25:37.949569 [DATLAT]
4329 19:25:37.949628 Freq=600, CH0 RK1
4330 19:25:37.949686
4331 19:25:37.952825 DATLAT Default: 0x9
4332 19:25:37.956105 0, 0xFFFF, sum = 0
4333 19:25:37.956187 1, 0xFFFF, sum = 0
4334 19:25:37.959638 2, 0xFFFF, sum = 0
4335 19:25:37.959720 3, 0xFFFF, sum = 0
4336 19:25:37.962856 4, 0xFFFF, sum = 0
4337 19:25:37.962939 5, 0xFFFF, sum = 0
4338 19:25:37.966292 6, 0xFFFF, sum = 0
4339 19:25:37.966374 7, 0xFFFF, sum = 0
4340 19:25:37.969413 8, 0x0, sum = 1
4341 19:25:37.969533 9, 0x0, sum = 2
4342 19:25:37.972435 10, 0x0, sum = 3
4343 19:25:37.972517 11, 0x0, sum = 4
4344 19:25:37.972582 best_step = 9
4345 19:25:37.975659
4346 19:25:37.975776 ==
4347 19:25:37.978780 Dram Type= 6, Freq= 0, CH_0, rank 1
4348 19:25:37.982245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4349 19:25:37.982327 ==
4350 19:25:37.982391 RX Vref Scan: 0
4351 19:25:37.982482
4352 19:25:37.985810 RX Vref 0 -> 0, step: 1
4353 19:25:37.985890
4354 19:25:37.989106 RX Delay -195 -> 252, step: 8
4355 19:25:37.995380 iDelay=197, Bit 0, Center 40 (-107 ~ 188) 296
4356 19:25:37.998924 iDelay=197, Bit 1, Center 44 (-107 ~ 196) 304
4357 19:25:38.001812 iDelay=197, Bit 2, Center 36 (-115 ~ 188) 304
4358 19:25:38.005139 iDelay=197, Bit 3, Center 36 (-115 ~ 188) 304
4359 19:25:38.011667 iDelay=197, Bit 4, Center 44 (-107 ~ 196) 304
4360 19:25:38.015237 iDelay=197, Bit 5, Center 28 (-123 ~ 180) 304
4361 19:25:38.018819 iDelay=197, Bit 6, Center 48 (-99 ~ 196) 296
4362 19:25:38.021847 iDelay=197, Bit 7, Center 44 (-107 ~ 196) 304
4363 19:25:38.024810 iDelay=197, Bit 8, Center 24 (-131 ~ 180) 312
4364 19:25:38.031570 iDelay=197, Bit 9, Center 16 (-139 ~ 172) 312
4365 19:25:38.035138 iDelay=197, Bit 10, Center 36 (-123 ~ 196) 320
4366 19:25:38.037984 iDelay=197, Bit 11, Center 24 (-131 ~ 180) 312
4367 19:25:38.044687 iDelay=197, Bit 12, Center 40 (-115 ~ 196) 312
4368 19:25:38.048076 iDelay=197, Bit 13, Center 40 (-115 ~ 196) 312
4369 19:25:38.051275 iDelay=197, Bit 14, Center 40 (-115 ~ 196) 312
4370 19:25:38.054708 iDelay=197, Bit 15, Center 40 (-115 ~ 196) 312
4371 19:25:38.054788 ==
4372 19:25:38.057595 Dram Type= 6, Freq= 0, CH_0, rank 1
4373 19:25:38.064268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4374 19:25:38.064349 ==
4375 19:25:38.064412 DQS Delay:
4376 19:25:38.067576 DQS0 = 0, DQS1 = 0
4377 19:25:38.067695 DQM Delay:
4378 19:25:38.067801 DQM0 = 40, DQM1 = 32
4379 19:25:38.071168 DQ Delay:
4380 19:25:38.074261 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =36
4381 19:25:38.077996 DQ4 =44, DQ5 =28, DQ6 =48, DQ7 =44
4382 19:25:38.080965 DQ8 =24, DQ9 =16, DQ10 =36, DQ11 =24
4383 19:25:38.083811 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4384 19:25:38.083934
4385 19:25:38.083998
4386 19:25:38.090348 [DQSOSCAuto] RK1, (LSB)MR18= 0x403c, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
4387 19:25:38.093775 CH0 RK1: MR19=808, MR18=403C
4388 19:25:38.100687 CH0_RK1: MR19=0x808, MR18=0x403C, DQSOSC=397, MR23=63, INC=166, DEC=110
4389 19:25:38.103975 [RxdqsGatingPostProcess] freq 600
4390 19:25:38.110497 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4391 19:25:38.110577 Pre-setting of DQS Precalculation
4392 19:25:38.116965 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4393 19:25:38.117069 ==
4394 19:25:38.120072 Dram Type= 6, Freq= 0, CH_1, rank 0
4395 19:25:38.123736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4396 19:25:38.123816 ==
4397 19:25:38.129800 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4398 19:25:38.136318 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4399 19:25:38.140135 [CA 0] Center 36 (6~66) winsize 61
4400 19:25:38.143435 [CA 1] Center 36 (6~66) winsize 61
4401 19:25:38.146308 [CA 2] Center 35 (5~65) winsize 61
4402 19:25:38.149818 [CA 3] Center 34 (4~65) winsize 62
4403 19:25:38.153315 [CA 4] Center 34 (4~65) winsize 62
4404 19:25:38.156255 [CA 5] Center 33 (3~64) winsize 62
4405 19:25:38.156335
4406 19:25:38.159458 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4407 19:25:38.159537
4408 19:25:38.162877 [CATrainingPosCal] consider 1 rank data
4409 19:25:38.166228 u2DelayCellTimex100 = 270/100 ps
4410 19:25:38.169404 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4411 19:25:38.172734 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4412 19:25:38.176180 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
4413 19:25:38.179538 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4414 19:25:38.185785 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4415 19:25:38.189440 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4416 19:25:38.189520
4417 19:25:38.192448 CA PerBit enable=1, Macro0, CA PI delay=33
4418 19:25:38.192529
4419 19:25:38.195596 [CBTSetCACLKResult] CA Dly = 33
4420 19:25:38.195701 CS Dly: 5 (0~36)
4421 19:25:38.195794 ==
4422 19:25:38.199616 Dram Type= 6, Freq= 0, CH_1, rank 1
4423 19:25:38.205799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4424 19:25:38.205881 ==
4425 19:25:38.208998 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4426 19:25:38.215348 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4427 19:25:38.219330 [CA 0] Center 36 (6~66) winsize 61
4428 19:25:38.222273 [CA 1] Center 36 (6~66) winsize 61
4429 19:25:38.225618 [CA 2] Center 34 (4~65) winsize 62
4430 19:25:38.228698 [CA 3] Center 34 (4~65) winsize 62
4431 19:25:38.232121 [CA 4] Center 34 (4~64) winsize 61
4432 19:25:38.235418 [CA 5] Center 33 (3~64) winsize 62
4433 19:25:38.235498
4434 19:25:38.238871 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4435 19:25:38.238976
4436 19:25:38.241763 [CATrainingPosCal] consider 2 rank data
4437 19:25:38.245347 u2DelayCellTimex100 = 270/100 ps
4438 19:25:38.248828 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4439 19:25:38.255154 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4440 19:25:38.258637 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
4441 19:25:38.261467 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4442 19:25:38.264749 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4443 19:25:38.268129 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4444 19:25:38.268235
4445 19:25:38.271688 CA PerBit enable=1, Macro0, CA PI delay=33
4446 19:25:38.271771
4447 19:25:38.275223 [CBTSetCACLKResult] CA Dly = 33
4448 19:25:38.278230 CS Dly: 5 (0~36)
4449 19:25:38.278311
4450 19:25:38.281539 ----->DramcWriteLeveling(PI) begin...
4451 19:25:38.281636 ==
4452 19:25:38.285017 Dram Type= 6, Freq= 0, CH_1, rank 0
4453 19:25:38.288293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4454 19:25:38.288374 ==
4455 19:25:38.291514 Write leveling (Byte 0): 30 => 30
4456 19:25:38.295064 Write leveling (Byte 1): 29 => 29
4457 19:25:38.297962 DramcWriteLeveling(PI) end<-----
4458 19:25:38.298042
4459 19:25:38.298105 ==
4460 19:25:38.301045 Dram Type= 6, Freq= 0, CH_1, rank 0
4461 19:25:38.304444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4462 19:25:38.304525 ==
4463 19:25:38.308348 [Gating] SW mode calibration
4464 19:25:38.314285 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4465 19:25:38.321027 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4466 19:25:38.324125 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4467 19:25:38.330601 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4468 19:25:38.333827 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4469 19:25:38.337318 0 9 12 | B1->B0 | 3131 2e2e | 0 1 | (1 1) (1 0)
4470 19:25:38.344050 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4471 19:25:38.347418 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4472 19:25:38.350645 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4473 19:25:38.357533 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4474 19:25:38.360192 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4475 19:25:38.363799 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4476 19:25:38.370371 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4477 19:25:38.373682 0 10 12 | B1->B0 | 3333 3434 | 0 0 | (0 0) (0 0)
4478 19:25:38.376637 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4479 19:25:38.383507 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4480 19:25:38.386736 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4481 19:25:38.390398 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4482 19:25:38.396878 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4483 19:25:38.399984 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4484 19:25:38.403268 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4485 19:25:38.409828 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4486 19:25:38.412915 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4487 19:25:38.416577 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 19:25:38.423199 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 19:25:38.426025 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 19:25:38.429803 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 19:25:38.435945 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 19:25:38.439164 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 19:25:38.442607 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 19:25:38.448850 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 19:25:38.452363 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 19:25:38.455496 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 19:25:38.462234 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 19:25:38.465778 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 19:25:38.468826 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 19:25:38.475451 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 19:25:38.478745 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4502 19:25:38.482273 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4503 19:25:38.485725 Total UI for P1: 0, mck2ui 16
4504 19:25:38.488941 best dqsien dly found for B0: ( 0, 13, 14)
4505 19:25:38.492120 Total UI for P1: 0, mck2ui 16
4506 19:25:38.495400 best dqsien dly found for B1: ( 0, 13, 12)
4507 19:25:38.498873 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4508 19:25:38.501771 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4509 19:25:38.501852
4510 19:25:38.508664 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4511 19:25:38.512031 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4512 19:25:38.512127 [Gating] SW calibration Done
4513 19:25:38.515195 ==
4514 19:25:38.518454 Dram Type= 6, Freq= 0, CH_1, rank 0
4515 19:25:38.521505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4516 19:25:38.521586 ==
4517 19:25:38.521650 RX Vref Scan: 0
4518 19:25:38.521709
4519 19:25:38.525273 RX Vref 0 -> 0, step: 1
4520 19:25:38.525353
4521 19:25:38.528520 RX Delay -230 -> 252, step: 16
4522 19:25:38.531454 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4523 19:25:38.535192 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4524 19:25:38.541262 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4525 19:25:38.544763 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4526 19:25:38.548109 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4527 19:25:38.551542 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4528 19:25:38.557922 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4529 19:25:38.561332 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4530 19:25:38.564422 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4531 19:25:38.567821 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4532 19:25:38.574824 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4533 19:25:38.577906 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4534 19:25:38.581039 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4535 19:25:38.584359 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4536 19:25:38.591226 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4537 19:25:38.594228 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4538 19:25:38.594309 ==
4539 19:25:38.597793 Dram Type= 6, Freq= 0, CH_1, rank 0
4540 19:25:38.600789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4541 19:25:38.600871 ==
4542 19:25:38.603928 DQS Delay:
4543 19:25:38.604009 DQS0 = 0, DQS1 = 0
4544 19:25:38.604073 DQM Delay:
4545 19:25:38.607277 DQM0 = 45, DQM1 = 39
4546 19:25:38.607360 DQ Delay:
4547 19:25:38.610516 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4548 19:25:38.613916 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4549 19:25:38.616939 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4550 19:25:38.620296 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4551 19:25:38.620377
4552 19:25:38.620439
4553 19:25:38.620498 ==
4554 19:25:38.623452 Dram Type= 6, Freq= 0, CH_1, rank 0
4555 19:25:38.630732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4556 19:25:38.630814 ==
4557 19:25:38.630879
4558 19:25:38.630940
4559 19:25:38.630997 TX Vref Scan disable
4560 19:25:38.634299 == TX Byte 0 ==
4561 19:25:38.637370 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4562 19:25:38.644028 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4563 19:25:38.644109 == TX Byte 1 ==
4564 19:25:38.647208 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4565 19:25:38.654036 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4566 19:25:38.654117 ==
4567 19:25:38.657366 Dram Type= 6, Freq= 0, CH_1, rank 0
4568 19:25:38.660931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4569 19:25:38.661012 ==
4570 19:25:38.661077
4571 19:25:38.661136
4572 19:25:38.664129 TX Vref Scan disable
4573 19:25:38.667114 == TX Byte 0 ==
4574 19:25:38.670573 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4575 19:25:38.674112 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4576 19:25:38.677147 == TX Byte 1 ==
4577 19:25:38.680701 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4578 19:25:38.683726 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4579 19:25:38.683808
4580 19:25:38.683871 [DATLAT]
4581 19:25:38.687015 Freq=600, CH1 RK0
4582 19:25:38.687132
4583 19:25:38.690799 DATLAT Default: 0x9
4584 19:25:38.690880 0, 0xFFFF, sum = 0
4585 19:25:38.693592 1, 0xFFFF, sum = 0
4586 19:25:38.693676 2, 0xFFFF, sum = 0
4587 19:25:38.697159 3, 0xFFFF, sum = 0
4588 19:25:38.697241 4, 0xFFFF, sum = 0
4589 19:25:38.700713 5, 0xFFFF, sum = 0
4590 19:25:38.700795 6, 0xFFFF, sum = 0
4591 19:25:38.703584 7, 0xFFFF, sum = 0
4592 19:25:38.703666 8, 0x0, sum = 1
4593 19:25:38.707229 9, 0x0, sum = 2
4594 19:25:38.707311 10, 0x0, sum = 3
4595 19:25:38.710223 11, 0x0, sum = 4
4596 19:25:38.710305 best_step = 9
4597 19:25:38.710369
4598 19:25:38.710428 ==
4599 19:25:38.713576 Dram Type= 6, Freq= 0, CH_1, rank 0
4600 19:25:38.716418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4601 19:25:38.716500 ==
4602 19:25:38.719944 RX Vref Scan: 1
4603 19:25:38.720025
4604 19:25:38.723386 RX Vref 0 -> 0, step: 1
4605 19:25:38.723467
4606 19:25:38.723530 RX Delay -179 -> 252, step: 8
4607 19:25:38.726273
4608 19:25:38.726353 Set Vref, RX VrefLevel [Byte0]: 49
4609 19:25:38.729904 [Byte1]: 51
4610 19:25:38.734571
4611 19:25:38.734654 Final RX Vref Byte 0 = 49 to rank0
4612 19:25:38.738129 Final RX Vref Byte 1 = 51 to rank0
4613 19:25:38.741642 Final RX Vref Byte 0 = 49 to rank1
4614 19:25:38.744444 Final RX Vref Byte 1 = 51 to rank1==
4615 19:25:38.748036 Dram Type= 6, Freq= 0, CH_1, rank 0
4616 19:25:38.754569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4617 19:25:38.754651 ==
4618 19:25:38.754715 DQS Delay:
4619 19:25:38.757710 DQS0 = 0, DQS1 = 0
4620 19:25:38.757790 DQM Delay:
4621 19:25:38.757854 DQM0 = 40, DQM1 = 33
4622 19:25:38.761164 DQ Delay:
4623 19:25:38.764735 DQ0 =48, DQ1 =36, DQ2 =32, DQ3 =40
4624 19:25:38.767881 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =36
4625 19:25:38.770758 DQ8 =16, DQ9 =20, DQ10 =32, DQ11 =28
4626 19:25:38.774215 DQ12 =44, DQ13 =44, DQ14 =40, DQ15 =40
4627 19:25:38.774296
4628 19:25:38.774360
4629 19:25:38.780757 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c46, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 401 ps
4630 19:25:38.784318 CH1 RK0: MR19=808, MR18=2C46
4631 19:25:38.790472 CH1_RK0: MR19=0x808, MR18=0x2C46, DQSOSC=396, MR23=63, INC=167, DEC=111
4632 19:25:38.790584
4633 19:25:38.793769 ----->DramcWriteLeveling(PI) begin...
4634 19:25:38.793853 ==
4635 19:25:38.797035 Dram Type= 6, Freq= 0, CH_1, rank 1
4636 19:25:38.800201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4637 19:25:38.800310 ==
4638 19:25:38.803677 Write leveling (Byte 0): 28 => 28
4639 19:25:38.807249 Write leveling (Byte 1): 30 => 30
4640 19:25:38.810426 DramcWriteLeveling(PI) end<-----
4641 19:25:38.810506
4642 19:25:38.810570 ==
4643 19:25:38.813726 Dram Type= 6, Freq= 0, CH_1, rank 1
4644 19:25:38.820544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4645 19:25:38.820625 ==
4646 19:25:38.820690 [Gating] SW mode calibration
4647 19:25:38.830408 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4648 19:25:38.833148 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4649 19:25:38.840060 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4650 19:25:38.843178 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4651 19:25:38.846453 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4652 19:25:38.852970 0 9 12 | B1->B0 | 3030 2d2d | 1 1 | (1 1) (1 0)
4653 19:25:38.856857 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4654 19:25:38.859560 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4655 19:25:38.866167 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4656 19:25:38.869337 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4657 19:25:38.872450 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4658 19:25:38.878902 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4659 19:25:38.882634 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4660 19:25:38.885620 0 10 12 | B1->B0 | 3333 3737 | 0 0 | (0 0) (0 0)
4661 19:25:38.892339 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4662 19:25:38.896032 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4663 19:25:38.898621 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4664 19:25:38.905427 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4665 19:25:38.909010 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4666 19:25:38.911850 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4667 19:25:38.918384 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4668 19:25:38.921954 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4669 19:25:38.925230 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4670 19:25:38.931494 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 19:25:38.935117 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 19:25:38.938238 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 19:25:38.944884 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 19:25:38.948590 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 19:25:38.951483 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 19:25:38.958210 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 19:25:38.961191 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 19:25:38.964615 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 19:25:38.971503 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 19:25:38.974762 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 19:25:38.977633 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 19:25:38.984203 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 19:25:38.987620 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 19:25:38.990901 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4685 19:25:38.994163 Total UI for P1: 0, mck2ui 16
4686 19:25:38.997360 best dqsien dly found for B0: ( 0, 13, 10)
4687 19:25:39.001243 Total UI for P1: 0, mck2ui 16
4688 19:25:39.003834 best dqsien dly found for B1: ( 0, 13, 10)
4689 19:25:39.007548 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4690 19:25:39.010334 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4691 19:25:39.013766
4692 19:25:39.016934 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4693 19:25:39.020604 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4694 19:25:39.023645 [Gating] SW calibration Done
4695 19:25:39.023725 ==
4696 19:25:39.027185 Dram Type= 6, Freq= 0, CH_1, rank 1
4697 19:25:39.030422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4698 19:25:39.030503 ==
4699 19:25:39.033810 RX Vref Scan: 0
4700 19:25:39.033891
4701 19:25:39.033955 RX Vref 0 -> 0, step: 1
4702 19:25:39.034015
4703 19:25:39.036720 RX Delay -230 -> 252, step: 16
4704 19:25:39.040216 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4705 19:25:39.046746 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4706 19:25:39.049834 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4707 19:25:39.053656 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4708 19:25:39.056585 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4709 19:25:39.062895 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4710 19:25:39.066255 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4711 19:25:39.070027 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4712 19:25:39.073516 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4713 19:25:39.079634 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4714 19:25:39.083090 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4715 19:25:39.085992 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4716 19:25:39.089404 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4717 19:25:39.096034 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4718 19:25:39.099047 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4719 19:25:39.102439 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4720 19:25:39.102520 ==
4721 19:25:39.105705 Dram Type= 6, Freq= 0, CH_1, rank 1
4722 19:25:39.109182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4723 19:25:39.109264 ==
4724 19:25:39.112682 DQS Delay:
4725 19:25:39.112763 DQS0 = 0, DQS1 = 0
4726 19:25:39.115707 DQM Delay:
4727 19:25:39.115813 DQM0 = 42, DQM1 = 39
4728 19:25:39.115931 DQ Delay:
4729 19:25:39.119182 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4730 19:25:39.122159 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4731 19:25:39.125633 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4732 19:25:39.129199 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4733 19:25:39.129279
4734 19:25:39.132082
4735 19:25:39.132163 ==
4736 19:25:39.135740 Dram Type= 6, Freq= 0, CH_1, rank 1
4737 19:25:39.138619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4738 19:25:39.138704 ==
4739 19:25:39.138768
4740 19:25:39.138826
4741 19:25:39.142184 TX Vref Scan disable
4742 19:25:39.142267 == TX Byte 0 ==
4743 19:25:39.148754 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4744 19:25:39.152234 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4745 19:25:39.152322 == TX Byte 1 ==
4746 19:25:39.158494 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4747 19:25:39.161863 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4748 19:25:39.161948 ==
4749 19:25:39.165096 Dram Type= 6, Freq= 0, CH_1, rank 1
4750 19:25:39.168396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4751 19:25:39.168510 ==
4752 19:25:39.168602
4753 19:25:39.168690
4754 19:25:39.171853 TX Vref Scan disable
4755 19:25:39.175218 == TX Byte 0 ==
4756 19:25:39.178535 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4757 19:25:39.185056 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4758 19:25:39.185164 == TX Byte 1 ==
4759 19:25:39.187994 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4760 19:25:39.194503 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4761 19:25:39.194590
4762 19:25:39.194657 [DATLAT]
4763 19:25:39.194733 Freq=600, CH1 RK1
4764 19:25:39.194792
4765 19:25:39.197992 DATLAT Default: 0x9
4766 19:25:39.201323 0, 0xFFFF, sum = 0
4767 19:25:39.201409 1, 0xFFFF, sum = 0
4768 19:25:39.204542 2, 0xFFFF, sum = 0
4769 19:25:39.204626 3, 0xFFFF, sum = 0
4770 19:25:39.207876 4, 0xFFFF, sum = 0
4771 19:25:39.207990 5, 0xFFFF, sum = 0
4772 19:25:39.211269 6, 0xFFFF, sum = 0
4773 19:25:39.211355 7, 0xFFFF, sum = 0
4774 19:25:39.214183 8, 0x0, sum = 1
4775 19:25:39.214267 9, 0x0, sum = 2
4776 19:25:39.217541 10, 0x0, sum = 3
4777 19:25:39.217627 11, 0x0, sum = 4
4778 19:25:39.217695 best_step = 9
4779 19:25:39.221019
4780 19:25:39.221131 ==
4781 19:25:39.224139 Dram Type= 6, Freq= 0, CH_1, rank 1
4782 19:25:39.227653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4783 19:25:39.227750 ==
4784 19:25:39.227816 RX Vref Scan: 0
4785 19:25:39.227876
4786 19:25:39.231069 RX Vref 0 -> 0, step: 1
4787 19:25:39.231152
4788 19:25:39.234191 RX Delay -179 -> 252, step: 8
4789 19:25:39.240613 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4790 19:25:39.244104 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4791 19:25:39.246955 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4792 19:25:39.250408 iDelay=205, Bit 3, Center 36 (-123 ~ 196) 320
4793 19:25:39.257143 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4794 19:25:39.260050 iDelay=205, Bit 5, Center 44 (-115 ~ 204) 320
4795 19:25:39.263534 iDelay=205, Bit 6, Center 40 (-115 ~ 196) 312
4796 19:25:39.266893 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4797 19:25:39.273698 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4798 19:25:39.276668 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4799 19:25:39.280166 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4800 19:25:39.283515 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4801 19:25:39.286826 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4802 19:25:39.293264 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4803 19:25:39.296226 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4804 19:25:39.300033 iDelay=205, Bit 15, Center 44 (-115 ~ 204) 320
4805 19:25:39.300118 ==
4806 19:25:39.303285 Dram Type= 6, Freq= 0, CH_1, rank 1
4807 19:25:39.309960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4808 19:25:39.310059 ==
4809 19:25:39.310127 DQS Delay:
4810 19:25:39.312913 DQS0 = 0, DQS1 = 0
4811 19:25:39.313002 DQM Delay:
4812 19:25:39.313068 DQM0 = 35, DQM1 = 34
4813 19:25:39.316340 DQ Delay:
4814 19:25:39.319563 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =36
4815 19:25:39.322918 DQ4 =36, DQ5 =44, DQ6 =40, DQ7 =32
4816 19:25:39.326200 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =24
4817 19:25:39.329380 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =44
4818 19:25:39.329462
4819 19:25:39.329526
4820 19:25:39.336096 [DQSOSCAuto] RK1, (LSB)MR18= 0x3357, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
4821 19:25:39.339415 CH1 RK1: MR19=808, MR18=3357
4822 19:25:39.346006 CH1_RK1: MR19=0x808, MR18=0x3357, DQSOSC=393, MR23=63, INC=169, DEC=113
4823 19:25:39.348900 [RxdqsGatingPostProcess] freq 600
4824 19:25:39.356092 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4825 19:25:39.356215 Pre-setting of DQS Precalculation
4826 19:25:39.362274 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4827 19:25:39.369006 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4828 19:25:39.375725 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4829 19:25:39.375834
4830 19:25:39.375955
4831 19:25:39.378521 [Calibration Summary] 1200 Mbps
4832 19:25:39.381931 CH 0, Rank 0
4833 19:25:39.382012 SW Impedance : PASS
4834 19:25:39.385430 DUTY Scan : NO K
4835 19:25:39.388712 ZQ Calibration : PASS
4836 19:25:39.388794 Jitter Meter : NO K
4837 19:25:39.391856 CBT Training : PASS
4838 19:25:39.391960 Write leveling : PASS
4839 19:25:39.395470 RX DQS gating : PASS
4840 19:25:39.398382 RX DQ/DQS(RDDQC) : PASS
4841 19:25:39.398484 TX DQ/DQS : PASS
4842 19:25:39.401831 RX DATLAT : PASS
4843 19:25:39.405136 RX DQ/DQS(Engine): PASS
4844 19:25:39.405235 TX OE : NO K
4845 19:25:39.408083 All Pass.
4846 19:25:39.408151
4847 19:25:39.408213 CH 0, Rank 1
4848 19:25:39.411572 SW Impedance : PASS
4849 19:25:39.411670 DUTY Scan : NO K
4850 19:25:39.415078 ZQ Calibration : PASS
4851 19:25:39.417976 Jitter Meter : NO K
4852 19:25:39.418074 CBT Training : PASS
4853 19:25:39.421202 Write leveling : PASS
4854 19:25:39.424756 RX DQS gating : PASS
4855 19:25:39.424832 RX DQ/DQS(RDDQC) : PASS
4856 19:25:39.428282 TX DQ/DQS : PASS
4857 19:25:39.431524 RX DATLAT : PASS
4858 19:25:39.431620 RX DQ/DQS(Engine): PASS
4859 19:25:39.434568 TX OE : NO K
4860 19:25:39.434639 All Pass.
4861 19:25:39.434727
4862 19:25:39.437683 CH 1, Rank 0
4863 19:25:39.437778 SW Impedance : PASS
4864 19:25:39.441012 DUTY Scan : NO K
4865 19:25:39.444782 ZQ Calibration : PASS
4866 19:25:39.444853 Jitter Meter : NO K
4867 19:25:39.447855 CBT Training : PASS
4868 19:25:39.451170 Write leveling : PASS
4869 19:25:39.451268 RX DQS gating : PASS
4870 19:25:39.454272 RX DQ/DQS(RDDQC) : PASS
4871 19:25:39.457689 TX DQ/DQS : PASS
4872 19:25:39.457759 RX DATLAT : PASS
4873 19:25:39.460774 RX DQ/DQS(Engine): PASS
4874 19:25:39.464326 TX OE : NO K
4875 19:25:39.464419 All Pass.
4876 19:25:39.464507
4877 19:25:39.464592 CH 1, Rank 1
4878 19:25:39.467472 SW Impedance : PASS
4879 19:25:39.470710 DUTY Scan : NO K
4880 19:25:39.470802 ZQ Calibration : PASS
4881 19:25:39.474151 Jitter Meter : NO K
4882 19:25:39.477548 CBT Training : PASS
4883 19:25:39.477658 Write leveling : PASS
4884 19:25:39.480422 RX DQS gating : PASS
4885 19:25:39.480498 RX DQ/DQS(RDDQC) : PASS
4886 19:25:39.484430 TX DQ/DQS : PASS
4887 19:25:39.487406 RX DATLAT : PASS
4888 19:25:39.487500 RX DQ/DQS(Engine): PASS
4889 19:25:39.490862 TX OE : NO K
4890 19:25:39.490959 All Pass.
4891 19:25:39.491046
4892 19:25:39.494401 DramC Write-DBI off
4893 19:25:39.497340 PER_BANK_REFRESH: Hybrid Mode
4894 19:25:39.497432 TX_TRACKING: ON
4895 19:25:39.506824 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4896 19:25:39.510393 [FAST_K] Save calibration result to emmc
4897 19:25:39.513615 dramc_set_vcore_voltage set vcore to 662500
4898 19:25:39.516783 Read voltage for 933, 3
4899 19:25:39.516857 Vio18 = 0
4900 19:25:39.520346 Vcore = 662500
4901 19:25:39.520421 Vdram = 0
4902 19:25:39.520483 Vddq = 0
4903 19:25:39.520544 Vmddr = 0
4904 19:25:39.527166 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4905 19:25:39.533638 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4906 19:25:39.533717 MEM_TYPE=3, freq_sel=17
4907 19:25:39.536603 sv_algorithm_assistance_LP4_1600
4908 19:25:39.540062 ============ PULL DRAM RESETB DOWN ============
4909 19:25:39.546728 ========== PULL DRAM RESETB DOWN end =========
4910 19:25:39.549595 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4911 19:25:39.553280 ===================================
4912 19:25:39.556558 LPDDR4 DRAM CONFIGURATION
4913 19:25:39.559534 ===================================
4914 19:25:39.559610 EX_ROW_EN[0] = 0x0
4915 19:25:39.562872 EX_ROW_EN[1] = 0x0
4916 19:25:39.562970 LP4Y_EN = 0x0
4917 19:25:39.566791 WORK_FSP = 0x0
4918 19:25:39.569866 WL = 0x3
4919 19:25:39.569941 RL = 0x3
4920 19:25:39.573542 BL = 0x2
4921 19:25:39.573616 RPST = 0x0
4922 19:25:39.576439 RD_PRE = 0x0
4923 19:25:39.576536 WR_PRE = 0x1
4924 19:25:39.579623 WR_PST = 0x0
4925 19:25:39.579734 DBI_WR = 0x0
4926 19:25:39.582991 DBI_RD = 0x0
4927 19:25:39.583072 OTF = 0x1
4928 19:25:39.586497 ===================================
4929 19:25:39.589272 ===================================
4930 19:25:39.592732 ANA top config
4931 19:25:39.596308 ===================================
4932 19:25:39.596389 DLL_ASYNC_EN = 0
4933 19:25:39.599321 ALL_SLAVE_EN = 1
4934 19:25:39.602737 NEW_RANK_MODE = 1
4935 19:25:39.606208 DLL_IDLE_MODE = 1
4936 19:25:39.609711 LP45_APHY_COMB_EN = 1
4937 19:25:39.609792 TX_ODT_DIS = 1
4938 19:25:39.612618 NEW_8X_MODE = 1
4939 19:25:39.616023 ===================================
4940 19:25:39.619083 ===================================
4941 19:25:39.622499 data_rate = 1866
4942 19:25:39.625924 CKR = 1
4943 19:25:39.628876 DQ_P2S_RATIO = 8
4944 19:25:39.632441 ===================================
4945 19:25:39.635933 CA_P2S_RATIO = 8
4946 19:25:39.636014 DQ_CA_OPEN = 0
4947 19:25:39.638769 DQ_SEMI_OPEN = 0
4948 19:25:39.642304 CA_SEMI_OPEN = 0
4949 19:25:39.645285 CA_FULL_RATE = 0
4950 19:25:39.648878 DQ_CKDIV4_EN = 1
4951 19:25:39.652120 CA_CKDIV4_EN = 1
4952 19:25:39.652203 CA_PREDIV_EN = 0
4953 19:25:39.655259 PH8_DLY = 0
4954 19:25:39.658720 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4955 19:25:39.661783 DQ_AAMCK_DIV = 4
4956 19:25:39.665140 CA_AAMCK_DIV = 4
4957 19:25:39.668792 CA_ADMCK_DIV = 4
4958 19:25:39.668874 DQ_TRACK_CA_EN = 0
4959 19:25:39.671993 CA_PICK = 933
4960 19:25:39.675057 CA_MCKIO = 933
4961 19:25:39.678194 MCKIO_SEMI = 0
4962 19:25:39.681797 PLL_FREQ = 3732
4963 19:25:39.685008 DQ_UI_PI_RATIO = 32
4964 19:25:39.688195 CA_UI_PI_RATIO = 0
4965 19:25:39.691741 ===================================
4966 19:25:39.694601 ===================================
4967 19:25:39.694683 memory_type:LPDDR4
4968 19:25:39.698175 GP_NUM : 10
4969 19:25:39.701643 SRAM_EN : 1
4970 19:25:39.701724 MD32_EN : 0
4971 19:25:39.704555 ===================================
4972 19:25:39.708027 [ANA_INIT] >>>>>>>>>>>>>>
4973 19:25:39.711510 <<<<<< [CONFIGURE PHASE]: ANA_TX
4974 19:25:39.714331 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4975 19:25:39.717935 ===================================
4976 19:25:39.720883 data_rate = 1866,PCW = 0X8f00
4977 19:25:39.724711 ===================================
4978 19:25:39.727583 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4979 19:25:39.730936 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4980 19:25:39.737572 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4981 19:25:39.740681 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4982 19:25:39.747756 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4983 19:25:39.750667 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4984 19:25:39.750753 [ANA_INIT] flow start
4985 19:25:39.754098 [ANA_INIT] PLL >>>>>>>>
4986 19:25:39.757689 [ANA_INIT] PLL <<<<<<<<
4987 19:25:39.757770 [ANA_INIT] MIDPI >>>>>>>>
4988 19:25:39.760835 [ANA_INIT] MIDPI <<<<<<<<
4989 19:25:39.763773 [ANA_INIT] DLL >>>>>>>>
4990 19:25:39.763880 [ANA_INIT] flow end
4991 19:25:39.770508 ============ LP4 DIFF to SE enter ============
4992 19:25:39.774218 ============ LP4 DIFF to SE exit ============
4993 19:25:39.777308 [ANA_INIT] <<<<<<<<<<<<<
4994 19:25:39.780216 [Flow] Enable top DCM control >>>>>
4995 19:25:39.783549 [Flow] Enable top DCM control <<<<<
4996 19:25:39.783653 Enable DLL master slave shuffle
4997 19:25:39.790298 ==============================================================
4998 19:25:39.793644 Gating Mode config
4999 19:25:39.796563 ==============================================================
5000 19:25:39.800326 Config description:
5001 19:25:39.810201 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5002 19:25:39.816505 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5003 19:25:39.820028 SELPH_MODE 0: By rank 1: By Phase
5004 19:25:39.826442 ==============================================================
5005 19:25:39.829732 GAT_TRACK_EN = 1
5006 19:25:39.832974 RX_GATING_MODE = 2
5007 19:25:39.836161 RX_GATING_TRACK_MODE = 2
5008 19:25:39.839558 SELPH_MODE = 1
5009 19:25:39.843144 PICG_EARLY_EN = 1
5010 19:25:39.846125 VALID_LAT_VALUE = 1
5011 19:25:39.849566 ==============================================================
5012 19:25:39.852768 Enter into Gating configuration >>>>
5013 19:25:39.855752 Exit from Gating configuration <<<<
5014 19:25:39.859307 Enter into DVFS_PRE_config >>>>>
5015 19:25:39.872662 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5016 19:25:39.872768 Exit from DVFS_PRE_config <<<<<
5017 19:25:39.875573 Enter into PICG configuration >>>>
5018 19:25:39.879136 Exit from PICG configuration <<<<
5019 19:25:39.882263 [RX_INPUT] configuration >>>>>
5020 19:25:39.885783 [RX_INPUT] configuration <<<<<
5021 19:25:39.892211 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5022 19:25:39.895596 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5023 19:25:39.902402 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5024 19:25:39.908692 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5025 19:25:39.915187 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5026 19:25:39.922009 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5027 19:25:39.925071 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5028 19:25:39.928095 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5029 19:25:39.931819 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5030 19:25:39.937885 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5031 19:25:39.941812 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5032 19:25:39.944502 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5033 19:25:39.947827 ===================================
5034 19:25:39.951752 LPDDR4 DRAM CONFIGURATION
5035 19:25:39.954918 ===================================
5036 19:25:39.958287 EX_ROW_EN[0] = 0x0
5037 19:25:39.958376 EX_ROW_EN[1] = 0x0
5038 19:25:39.960979 LP4Y_EN = 0x0
5039 19:25:39.961060 WORK_FSP = 0x0
5040 19:25:39.964865 WL = 0x3
5041 19:25:39.964946 RL = 0x3
5042 19:25:39.968197 BL = 0x2
5043 19:25:39.968309 RPST = 0x0
5044 19:25:39.971054 RD_PRE = 0x0
5045 19:25:39.971135 WR_PRE = 0x1
5046 19:25:39.974421 WR_PST = 0x0
5047 19:25:39.977583 DBI_WR = 0x0
5048 19:25:39.977688 DBI_RD = 0x0
5049 19:25:39.980918 OTF = 0x1
5050 19:25:39.984352 ===================================
5051 19:25:39.987621 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5052 19:25:39.991125 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5053 19:25:39.993968 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5054 19:25:39.997551 ===================================
5055 19:25:40.000671 LPDDR4 DRAM CONFIGURATION
5056 19:25:40.003969 ===================================
5057 19:25:40.007544 EX_ROW_EN[0] = 0x10
5058 19:25:40.007625 EX_ROW_EN[1] = 0x0
5059 19:25:40.010418 LP4Y_EN = 0x0
5060 19:25:40.010498 WORK_FSP = 0x0
5061 19:25:40.014439 WL = 0x3
5062 19:25:40.014520 RL = 0x3
5063 19:25:40.017212 BL = 0x2
5064 19:25:40.017293 RPST = 0x0
5065 19:25:40.020358 RD_PRE = 0x0
5066 19:25:40.023995 WR_PRE = 0x1
5067 19:25:40.024128 WR_PST = 0x0
5068 19:25:40.027199 DBI_WR = 0x0
5069 19:25:40.027271 DBI_RD = 0x0
5070 19:25:40.030325 OTF = 0x1
5071 19:25:40.033960 ===================================
5072 19:25:40.036836 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5073 19:25:40.042639 nWR fixed to 30
5074 19:25:40.045477 [ModeRegInit_LP4] CH0 RK0
5075 19:25:40.045558 [ModeRegInit_LP4] CH0 RK1
5076 19:25:40.048799 [ModeRegInit_LP4] CH1 RK0
5077 19:25:40.052219 [ModeRegInit_LP4] CH1 RK1
5078 19:25:40.052300 match AC timing 9
5079 19:25:40.058956 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5080 19:25:40.062213 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5081 19:25:40.065676 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5082 19:25:40.071798 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5083 19:25:40.075513 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5084 19:25:40.075599 ==
5085 19:25:40.078396 Dram Type= 6, Freq= 0, CH_0, rank 0
5086 19:25:40.081482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5087 19:25:40.085142 ==
5088 19:25:40.088380 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5089 19:25:40.094670 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5090 19:25:40.098204 [CA 0] Center 38 (8~68) winsize 61
5091 19:25:40.101449 [CA 1] Center 37 (7~68) winsize 62
5092 19:25:40.105217 [CA 2] Center 34 (4~64) winsize 61
5093 19:25:40.107822 [CA 3] Center 34 (4~65) winsize 62
5094 19:25:40.111366 [CA 4] Center 33 (3~63) winsize 61
5095 19:25:40.114885 [CA 5] Center 32 (2~63) winsize 62
5096 19:25:40.114967
5097 19:25:40.117725 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5098 19:25:40.117806
5099 19:25:40.121143 [CATrainingPosCal] consider 1 rank data
5100 19:25:40.124519 u2DelayCellTimex100 = 270/100 ps
5101 19:25:40.127737 CA0 delay=38 (8~68),Diff = 6 PI (37 cell)
5102 19:25:40.130849 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5103 19:25:40.137418 CA2 delay=34 (4~64),Diff = 2 PI (12 cell)
5104 19:25:40.140804 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5105 19:25:40.144290 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5106 19:25:40.147384 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5107 19:25:40.147465
5108 19:25:40.151069 CA PerBit enable=1, Macro0, CA PI delay=32
5109 19:25:40.151184
5110 19:25:40.154166 [CBTSetCACLKResult] CA Dly = 32
5111 19:25:40.154247 CS Dly: 5 (0~36)
5112 19:25:40.157687 ==
5113 19:25:40.160393 Dram Type= 6, Freq= 0, CH_0, rank 1
5114 19:25:40.163739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5115 19:25:40.163820 ==
5116 19:25:40.170522 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5117 19:25:40.173325 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5118 19:25:40.177688 [CA 0] Center 38 (8~68) winsize 61
5119 19:25:40.180939 [CA 1] Center 37 (7~68) winsize 62
5120 19:25:40.183971 [CA 2] Center 34 (4~65) winsize 62
5121 19:25:40.187263 [CA 3] Center 34 (4~65) winsize 62
5122 19:25:40.190476 [CA 4] Center 33 (3~64) winsize 62
5123 19:25:40.193993 [CA 5] Center 32 (2~63) winsize 62
5124 19:25:40.194074
5125 19:25:40.197305 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5126 19:25:40.197385
5127 19:25:40.200248 [CATrainingPosCal] consider 2 rank data
5128 19:25:40.204199 u2DelayCellTimex100 = 270/100 ps
5129 19:25:40.207227 CA0 delay=38 (8~68),Diff = 6 PI (37 cell)
5130 19:25:40.213730 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5131 19:25:40.216695 CA2 delay=34 (4~64),Diff = 2 PI (12 cell)
5132 19:25:40.220238 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5133 19:25:40.223732 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5134 19:25:40.226528 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5135 19:25:40.226609
5136 19:25:40.230048 CA PerBit enable=1, Macro0, CA PI delay=32
5137 19:25:40.230130
5138 19:25:40.233385 [CBTSetCACLKResult] CA Dly = 32
5139 19:25:40.236892 CS Dly: 6 (0~39)
5140 19:25:40.236976
5141 19:25:40.239783 ----->DramcWriteLeveling(PI) begin...
5142 19:25:40.239865 ==
5143 19:25:40.243414 Dram Type= 6, Freq= 0, CH_0, rank 0
5144 19:25:40.246581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5145 19:25:40.246663 ==
5146 19:25:40.249989 Write leveling (Byte 0): 29 => 29
5147 19:25:40.253022 Write leveling (Byte 1): 29 => 29
5148 19:25:40.256198 DramcWriteLeveling(PI) end<-----
5149 19:25:40.256279
5150 19:25:40.256343 ==
5151 19:25:40.259398 Dram Type= 6, Freq= 0, CH_0, rank 0
5152 19:25:40.263101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5153 19:25:40.263182 ==
5154 19:25:40.266207 [Gating] SW mode calibration
5155 19:25:40.272955 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5156 19:25:40.279654 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5157 19:25:40.282581 0 14 0 | B1->B0 | 2a2a 3434 | 1 1 | (1 1) (1 1)
5158 19:25:40.289285 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5159 19:25:40.292669 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5160 19:25:40.296336 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5161 19:25:40.302615 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5162 19:25:40.305766 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5163 19:25:40.308713 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5164 19:25:40.315322 0 14 28 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (0 0)
5165 19:25:40.319230 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (0 0)
5166 19:25:40.321889 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5167 19:25:40.328359 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5168 19:25:40.331708 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5169 19:25:40.335232 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5170 19:25:40.341685 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5171 19:25:40.345281 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5172 19:25:40.348646 0 15 28 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
5173 19:25:40.354552 1 0 0 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
5174 19:25:40.358202 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5175 19:25:40.361816 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5176 19:25:40.367766 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5177 19:25:40.371154 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5178 19:25:40.374216 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5179 19:25:40.381033 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5180 19:25:40.384154 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5181 19:25:40.387430 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5182 19:25:40.394159 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5183 19:25:40.397681 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 19:25:40.401016 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 19:25:40.407251 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 19:25:40.410654 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 19:25:40.413807 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 19:25:40.420313 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 19:25:40.423744 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 19:25:40.427406 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 19:25:40.433678 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 19:25:40.437510 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 19:25:40.443418 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 19:25:40.446857 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 19:25:40.449753 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 19:25:40.456897 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5197 19:25:40.456982 Total UI for P1: 0, mck2ui 16
5198 19:25:40.459843 best dqsien dly found for B0: ( 1, 2, 26)
5199 19:25:40.466241 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5200 19:25:40.469844 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5201 19:25:40.472752 Total UI for P1: 0, mck2ui 16
5202 19:25:40.476277 best dqsien dly found for B1: ( 1, 2, 30)
5203 19:25:40.479783 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5204 19:25:40.482744 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5205 19:25:40.482825
5206 19:25:40.486382 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5207 19:25:40.492693 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5208 19:25:40.492775 [Gating] SW calibration Done
5209 19:25:40.495930 ==
5210 19:25:40.496012 Dram Type= 6, Freq= 0, CH_0, rank 0
5211 19:25:40.502709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5212 19:25:40.502790 ==
5213 19:25:40.502855 RX Vref Scan: 0
5214 19:25:40.502915
5215 19:25:40.506120 RX Vref 0 -> 0, step: 1
5216 19:25:40.506200
5217 19:25:40.509889 RX Delay -80 -> 252, step: 8
5218 19:25:40.512670 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5219 19:25:40.515565 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5220 19:25:40.519124 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5221 19:25:40.525633 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5222 19:25:40.528979 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5223 19:25:40.532551 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5224 19:25:40.535562 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5225 19:25:40.539004 iDelay=208, Bit 7, Center 107 (16 ~ 199) 184
5226 19:25:40.541906 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5227 19:25:40.548703 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5228 19:25:40.551813 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5229 19:25:40.555458 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5230 19:25:40.558335 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5231 19:25:40.561913 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5232 19:25:40.568408 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5233 19:25:40.571308 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5234 19:25:40.571389 ==
5235 19:25:40.574908 Dram Type= 6, Freq= 0, CH_0, rank 0
5236 19:25:40.578398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5237 19:25:40.578480 ==
5238 19:25:40.581295 DQS Delay:
5239 19:25:40.581490 DQS0 = 0, DQS1 = 0
5240 19:25:40.581566 DQM Delay:
5241 19:25:40.584803 DQM0 = 99, DQM1 = 88
5242 19:25:40.584884 DQ Delay:
5243 19:25:40.588240 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =95
5244 19:25:40.591159 DQ4 =103, DQ5 =87, DQ6 =111, DQ7 =107
5245 19:25:40.594712 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =83
5246 19:25:40.597965 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5247 19:25:40.598066
5248 19:25:40.598158
5249 19:25:40.598245 ==
5250 19:25:40.601307 Dram Type= 6, Freq= 0, CH_0, rank 0
5251 19:25:40.607643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5252 19:25:40.607718 ==
5253 19:25:40.607780
5254 19:25:40.607843
5255 19:25:40.610970 TX Vref Scan disable
5256 19:25:40.611069 == TX Byte 0 ==
5257 19:25:40.614327 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5258 19:25:40.620763 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5259 19:25:40.620838 == TX Byte 1 ==
5260 19:25:40.624106 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5261 19:25:40.630632 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5262 19:25:40.630733 ==
5263 19:25:40.633791 Dram Type= 6, Freq= 0, CH_0, rank 0
5264 19:25:40.637267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5265 19:25:40.637348 ==
5266 19:25:40.637437
5267 19:25:40.637524
5268 19:25:40.641020 TX Vref Scan disable
5269 19:25:40.644119 == TX Byte 0 ==
5270 19:25:40.647014 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5271 19:25:40.650641 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5272 19:25:40.654272 == TX Byte 1 ==
5273 19:25:40.656842 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5274 19:25:40.660585 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5275 19:25:40.660657
5276 19:25:40.663829 [DATLAT]
5277 19:25:40.663928 Freq=933, CH0 RK0
5278 19:25:40.663991
5279 19:25:40.666730 DATLAT Default: 0xd
5280 19:25:40.666825 0, 0xFFFF, sum = 0
5281 19:25:40.670207 1, 0xFFFF, sum = 0
5282 19:25:40.670279 2, 0xFFFF, sum = 0
5283 19:25:40.673238 3, 0xFFFF, sum = 0
5284 19:25:40.673311 4, 0xFFFF, sum = 0
5285 19:25:40.676797 5, 0xFFFF, sum = 0
5286 19:25:40.676867 6, 0xFFFF, sum = 0
5287 19:25:40.679693 7, 0xFFFF, sum = 0
5288 19:25:40.679801 8, 0xFFFF, sum = 0
5289 19:25:40.683127 9, 0xFFFF, sum = 0
5290 19:25:40.683228 10, 0x0, sum = 1
5291 19:25:40.686570 11, 0x0, sum = 2
5292 19:25:40.686670 12, 0x0, sum = 3
5293 19:25:40.690155 13, 0x0, sum = 4
5294 19:25:40.690254 best_step = 11
5295 19:25:40.690343
5296 19:25:40.690429 ==
5297 19:25:40.693191 Dram Type= 6, Freq= 0, CH_0, rank 0
5298 19:25:40.700125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5299 19:25:40.700203 ==
5300 19:25:40.700264 RX Vref Scan: 1
5301 19:25:40.700330
5302 19:25:40.703200 RX Vref 0 -> 0, step: 1
5303 19:25:40.703296
5304 19:25:40.706278 RX Delay -61 -> 252, step: 4
5305 19:25:40.706347
5306 19:25:40.710229 Set Vref, RX VrefLevel [Byte0]: 52
5307 19:25:40.712688 [Byte1]: 60
5308 19:25:40.712758
5309 19:25:40.716476 Final RX Vref Byte 0 = 52 to rank0
5310 19:25:40.720153 Final RX Vref Byte 1 = 60 to rank0
5311 19:25:40.722752 Final RX Vref Byte 0 = 52 to rank1
5312 19:25:40.726253 Final RX Vref Byte 1 = 60 to rank1==
5313 19:25:40.729253 Dram Type= 6, Freq= 0, CH_0, rank 0
5314 19:25:40.732862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5315 19:25:40.735523 ==
5316 19:25:40.735620 DQS Delay:
5317 19:25:40.735709 DQS0 = 0, DQS1 = 0
5318 19:25:40.739403 DQM Delay:
5319 19:25:40.739499 DQM0 = 99, DQM1 = 88
5320 19:25:40.742275 DQ Delay:
5321 19:25:40.745789 DQ0 =102, DQ1 =100, DQ2 =94, DQ3 =96
5322 19:25:40.748933 DQ4 =100, DQ5 =90, DQ6 =108, DQ7 =106
5323 19:25:40.752711 DQ8 =78, DQ9 =74, DQ10 =88, DQ11 =84
5324 19:25:40.755612 DQ12 =96, DQ13 =94, DQ14 =100, DQ15 =94
5325 19:25:40.755683
5326 19:25:40.755743
5327 19:25:40.762289 [DQSOSCAuto] RK0, (LSB)MR18= 0x1611, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 414 ps
5328 19:25:40.765445 CH0 RK0: MR19=505, MR18=1611
5329 19:25:40.772129 CH0_RK0: MR19=0x505, MR18=0x1611, DQSOSC=414, MR23=63, INC=63, DEC=42
5330 19:25:40.772204
5331 19:25:40.775667 ----->DramcWriteLeveling(PI) begin...
5332 19:25:40.775765 ==
5333 19:25:40.778823 Dram Type= 6, Freq= 0, CH_0, rank 1
5334 19:25:40.781895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5335 19:25:40.781997 ==
5336 19:25:40.785361 Write leveling (Byte 0): 32 => 32
5337 19:25:40.788179 Write leveling (Byte 1): 29 => 29
5338 19:25:40.791759 DramcWriteLeveling(PI) end<-----
5339 19:25:40.791856
5340 19:25:40.791983 ==
5341 19:25:40.795351 Dram Type= 6, Freq= 0, CH_0, rank 1
5342 19:25:40.798378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5343 19:25:40.801302 ==
5344 19:25:40.801373 [Gating] SW mode calibration
5345 19:25:40.811426 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5346 19:25:40.814537 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5347 19:25:40.817968 0 14 0 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
5348 19:25:40.824723 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5349 19:25:40.827712 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5350 19:25:40.831078 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5351 19:25:40.837823 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5352 19:25:40.840775 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5353 19:25:40.844203 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5354 19:25:40.851081 0 14 28 | B1->B0 | 3434 2424 | 1 0 | (1 0) (0 0)
5355 19:25:40.854154 0 15 0 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
5356 19:25:40.857403 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5357 19:25:40.864297 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5358 19:25:40.867655 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5359 19:25:40.870552 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5360 19:25:40.877533 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5361 19:25:40.880535 0 15 24 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
5362 19:25:40.884041 0 15 28 | B1->B0 | 2828 3d3d | 1 0 | (0 0) (0 0)
5363 19:25:40.890425 1 0 0 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5364 19:25:40.894017 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5365 19:25:40.896902 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5366 19:25:40.903420 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5367 19:25:40.906850 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5368 19:25:40.910311 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5369 19:25:40.917286 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5370 19:25:40.919999 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5371 19:25:40.926380 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5372 19:25:40.930060 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 19:25:40.932952 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 19:25:40.939637 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 19:25:40.943140 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 19:25:40.946121 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 19:25:40.952577 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 19:25:40.955962 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 19:25:40.959274 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 19:25:40.965579 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 19:25:40.969096 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 19:25:40.972361 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 19:25:40.979293 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 19:25:40.981961 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 19:25:40.985679 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 19:25:40.992224 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5387 19:25:40.992306 Total UI for P1: 0, mck2ui 16
5388 19:25:40.998589 best dqsien dly found for B0: ( 1, 2, 26)
5389 19:25:41.001984 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5390 19:25:41.005565 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5391 19:25:41.008393 Total UI for P1: 0, mck2ui 16
5392 19:25:41.012074 best dqsien dly found for B1: ( 1, 3, 0)
5393 19:25:41.015029 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5394 19:25:41.018607 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5395 19:25:41.018687
5396 19:25:41.024918 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5397 19:25:41.028394 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5398 19:25:41.028475 [Gating] SW calibration Done
5399 19:25:41.031205 ==
5400 19:25:41.034960 Dram Type= 6, Freq= 0, CH_0, rank 1
5401 19:25:41.037922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5402 19:25:41.038038 ==
5403 19:25:41.038102 RX Vref Scan: 0
5404 19:25:41.038161
5405 19:25:41.041281 RX Vref 0 -> 0, step: 1
5406 19:25:41.041365
5407 19:25:41.044659 RX Delay -80 -> 252, step: 8
5408 19:25:41.048105 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5409 19:25:41.051327 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5410 19:25:41.054318 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5411 19:25:41.060730 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5412 19:25:41.064675 iDelay=200, Bit 4, Center 99 (0 ~ 199) 200
5413 19:25:41.067547 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5414 19:25:41.071197 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5415 19:25:41.074413 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5416 19:25:41.077664 iDelay=200, Bit 8, Center 79 (-8 ~ 167) 176
5417 19:25:41.084388 iDelay=200, Bit 9, Center 79 (-8 ~ 167) 176
5418 19:25:41.087353 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5419 19:25:41.090700 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5420 19:25:41.094187 iDelay=200, Bit 12, Center 95 (8 ~ 183) 176
5421 19:25:41.097292 iDelay=200, Bit 13, Center 99 (8 ~ 191) 184
5422 19:25:41.103923 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5423 19:25:41.107516 iDelay=200, Bit 15, Center 99 (8 ~ 191) 184
5424 19:25:41.107598 ==
5425 19:25:41.110469 Dram Type= 6, Freq= 0, CH_0, rank 1
5426 19:25:41.113839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5427 19:25:41.113925 ==
5428 19:25:41.116709 DQS Delay:
5429 19:25:41.116790 DQS0 = 0, DQS1 = 0
5430 19:25:41.116854 DQM Delay:
5431 19:25:41.120262 DQM0 = 97, DQM1 = 90
5432 19:25:41.120346 DQ Delay:
5433 19:25:41.123761 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95
5434 19:25:41.126657 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =103
5435 19:25:41.130326 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5436 19:25:41.133143 DQ12 =95, DQ13 =99, DQ14 =99, DQ15 =99
5437 19:25:41.133229
5438 19:25:41.133299
5439 19:25:41.133358 ==
5440 19:25:41.136621 Dram Type= 6, Freq= 0, CH_0, rank 1
5441 19:25:41.143149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5442 19:25:41.143231 ==
5443 19:25:41.143300
5444 19:25:41.143360
5445 19:25:41.143417 TX Vref Scan disable
5446 19:25:41.146644 == TX Byte 0 ==
5447 19:25:41.150036 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5448 19:25:41.157138 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5449 19:25:41.157220 == TX Byte 1 ==
5450 19:25:41.160136 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5451 19:25:41.166694 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5452 19:25:41.166775 ==
5453 19:25:41.170640 Dram Type= 6, Freq= 0, CH_0, rank 1
5454 19:25:41.172886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5455 19:25:41.172967 ==
5456 19:25:41.173031
5457 19:25:41.173090
5458 19:25:41.176221 TX Vref Scan disable
5459 19:25:41.179869 == TX Byte 0 ==
5460 19:25:41.182900 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5461 19:25:41.186067 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5462 19:25:41.189743 == TX Byte 1 ==
5463 19:25:41.192979 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5464 19:25:41.195771 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5465 19:25:41.195853
5466 19:25:41.199443 [DATLAT]
5467 19:25:41.199523 Freq=933, CH0 RK1
5468 19:25:41.199588
5469 19:25:41.202554 DATLAT Default: 0xb
5470 19:25:41.202635 0, 0xFFFF, sum = 0
5471 19:25:41.205951 1, 0xFFFF, sum = 0
5472 19:25:41.206034 2, 0xFFFF, sum = 0
5473 19:25:41.209151 3, 0xFFFF, sum = 0
5474 19:25:41.209236 4, 0xFFFF, sum = 0
5475 19:25:41.212491 5, 0xFFFF, sum = 0
5476 19:25:41.212573 6, 0xFFFF, sum = 0
5477 19:25:41.215799 7, 0xFFFF, sum = 0
5478 19:25:41.215881 8, 0xFFFF, sum = 0
5479 19:25:41.219094 9, 0xFFFF, sum = 0
5480 19:25:41.219176 10, 0x0, sum = 1
5481 19:25:41.222437 11, 0x0, sum = 2
5482 19:25:41.222520 12, 0x0, sum = 3
5483 19:25:41.225377 13, 0x0, sum = 4
5484 19:25:41.225459 best_step = 11
5485 19:25:41.225523
5486 19:25:41.225583 ==
5487 19:25:41.228808 Dram Type= 6, Freq= 0, CH_0, rank 1
5488 19:25:41.235312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5489 19:25:41.235393 ==
5490 19:25:41.235457 RX Vref Scan: 0
5491 19:25:41.235517
5492 19:25:41.238868 RX Vref 0 -> 0, step: 1
5493 19:25:41.238949
5494 19:25:41.241855 RX Delay -53 -> 252, step: 4
5495 19:25:41.245193 iDelay=195, Bit 0, Center 94 (7 ~ 182) 176
5496 19:25:41.248557 iDelay=195, Bit 1, Center 98 (7 ~ 190) 184
5497 19:25:41.255318 iDelay=195, Bit 2, Center 90 (-1 ~ 182) 184
5498 19:25:41.258710 iDelay=195, Bit 3, Center 96 (7 ~ 186) 180
5499 19:25:41.262027 iDelay=195, Bit 4, Center 102 (11 ~ 194) 184
5500 19:25:41.265002 iDelay=195, Bit 5, Center 86 (-5 ~ 178) 184
5501 19:25:41.268265 iDelay=195, Bit 6, Center 106 (19 ~ 194) 176
5502 19:25:41.274899 iDelay=195, Bit 7, Center 104 (15 ~ 194) 180
5503 19:25:41.278388 iDelay=195, Bit 8, Center 80 (-5 ~ 166) 172
5504 19:25:41.281461 iDelay=195, Bit 9, Center 76 (-9 ~ 162) 172
5505 19:25:41.284933 iDelay=195, Bit 10, Center 90 (-1 ~ 182) 184
5506 19:25:41.287620 iDelay=195, Bit 11, Center 84 (-5 ~ 174) 180
5507 19:25:41.294200 iDelay=195, Bit 12, Center 96 (11 ~ 182) 172
5508 19:25:41.297471 iDelay=195, Bit 13, Center 94 (3 ~ 186) 184
5509 19:25:41.300868 iDelay=195, Bit 14, Center 98 (11 ~ 186) 176
5510 19:25:41.304482 iDelay=195, Bit 15, Center 96 (11 ~ 182) 172
5511 19:25:41.304563 ==
5512 19:25:41.307403 Dram Type= 6, Freq= 0, CH_0, rank 1
5513 19:25:41.311135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5514 19:25:41.314515 ==
5515 19:25:41.314596 DQS Delay:
5516 19:25:41.314660 DQS0 = 0, DQS1 = 0
5517 19:25:41.317360 DQM Delay:
5518 19:25:41.317441 DQM0 = 97, DQM1 = 89
5519 19:25:41.321196 DQ Delay:
5520 19:25:41.323834 DQ0 =94, DQ1 =98, DQ2 =90, DQ3 =96
5521 19:25:41.327662 DQ4 =102, DQ5 =86, DQ6 =106, DQ7 =104
5522 19:25:41.327743 DQ8 =80, DQ9 =76, DQ10 =90, DQ11 =84
5523 19:25:41.333990 DQ12 =96, DQ13 =94, DQ14 =98, DQ15 =96
5524 19:25:41.334071
5525 19:25:41.334135
5526 19:25:41.340604 [DQSOSCAuto] RK1, (LSB)MR18= 0x1311, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 415 ps
5527 19:25:41.344031 CH0 RK1: MR19=505, MR18=1311
5528 19:25:41.350506 CH0_RK1: MR19=0x505, MR18=0x1311, DQSOSC=415, MR23=63, INC=62, DEC=41
5529 19:25:41.353653 [RxdqsGatingPostProcess] freq 933
5530 19:25:41.356988 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5531 19:25:41.360473 best DQS0 dly(2T, 0.5T) = (0, 10)
5532 19:25:41.363368 best DQS1 dly(2T, 0.5T) = (0, 10)
5533 19:25:41.367160 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5534 19:25:41.370303 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5535 19:25:41.373614 best DQS0 dly(2T, 0.5T) = (0, 10)
5536 19:25:41.376621 best DQS1 dly(2T, 0.5T) = (0, 11)
5537 19:25:41.380196 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5538 19:25:41.383482 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5539 19:25:41.386373 Pre-setting of DQS Precalculation
5540 19:25:41.389875 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5541 19:25:41.393130 ==
5542 19:25:41.396415 Dram Type= 6, Freq= 0, CH_1, rank 0
5543 19:25:41.399441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5544 19:25:41.399526 ==
5545 19:25:41.402764 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5546 19:25:41.409616 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5547 19:25:41.413239 [CA 0] Center 36 (6~67) winsize 62
5548 19:25:41.417049 [CA 1] Center 36 (6~67) winsize 62
5549 19:25:41.419865 [CA 2] Center 34 (4~65) winsize 62
5550 19:25:41.423558 [CA 3] Center 34 (4~65) winsize 62
5551 19:25:41.426542 [CA 4] Center 34 (4~65) winsize 62
5552 19:25:41.430117 [CA 5] Center 33 (3~64) winsize 62
5553 19:25:41.430198
5554 19:25:41.433048 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5555 19:25:41.433120
5556 19:25:41.436431 [CATrainingPosCal] consider 1 rank data
5557 19:25:41.440258 u2DelayCellTimex100 = 270/100 ps
5558 19:25:41.443117 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5559 19:25:41.449561 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5560 19:25:41.453027 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5561 19:25:41.455999 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5562 19:25:41.459466 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5563 19:25:41.462761 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5564 19:25:41.462833
5565 19:25:41.466265 CA PerBit enable=1, Macro0, CA PI delay=33
5566 19:25:41.466362
5567 19:25:41.469284 [CBTSetCACLKResult] CA Dly = 33
5568 19:25:41.473094 CS Dly: 5 (0~36)
5569 19:25:41.473166 ==
5570 19:25:41.475604 Dram Type= 6, Freq= 0, CH_1, rank 1
5571 19:25:41.478862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5572 19:25:41.478965 ==
5573 19:25:41.485894 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5574 19:25:41.489215 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5575 19:25:41.493219 [CA 0] Center 36 (6~67) winsize 62
5576 19:25:41.496784 [CA 1] Center 36 (6~67) winsize 62
5577 19:25:41.500091 [CA 2] Center 34 (4~65) winsize 62
5578 19:25:41.503184 [CA 3] Center 33 (3~64) winsize 62
5579 19:25:41.506639 [CA 4] Center 33 (3~64) winsize 62
5580 19:25:41.509969 [CA 5] Center 33 (3~64) winsize 62
5581 19:25:41.510042
5582 19:25:41.512977 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5583 19:25:41.513049
5584 19:25:41.516352 [CATrainingPosCal] consider 2 rank data
5585 19:25:41.519673 u2DelayCellTimex100 = 270/100 ps
5586 19:25:41.523233 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5587 19:25:41.529485 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5588 19:25:41.533011 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5589 19:25:41.536358 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5590 19:25:41.539358 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5591 19:25:41.542856 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5592 19:25:41.542940
5593 19:25:41.545774 CA PerBit enable=1, Macro0, CA PI delay=33
5594 19:25:41.545855
5595 19:25:41.549428 [CBTSetCACLKResult] CA Dly = 33
5596 19:25:41.552648 CS Dly: 6 (0~38)
5597 19:25:41.552729
5598 19:25:41.556452 ----->DramcWriteLeveling(PI) begin...
5599 19:25:41.556534 ==
5600 19:25:41.558963 Dram Type= 6, Freq= 0, CH_1, rank 0
5601 19:25:41.562540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5602 19:25:41.562622 ==
5603 19:25:41.565965 Write leveling (Byte 0): 28 => 28
5604 19:25:41.569433 Write leveling (Byte 1): 28 => 28
5605 19:25:41.572222 DramcWriteLeveling(PI) end<-----
5606 19:25:41.572303
5607 19:25:41.572367 ==
5608 19:25:41.576120 Dram Type= 6, Freq= 0, CH_1, rank 0
5609 19:25:41.578927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5610 19:25:41.579008 ==
5611 19:25:41.582355 [Gating] SW mode calibration
5612 19:25:41.588945 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5613 19:25:41.595463 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5614 19:25:41.598503 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5615 19:25:41.605444 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5616 19:25:41.609237 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5617 19:25:41.611732 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5618 19:25:41.618507 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5619 19:25:41.621867 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5620 19:25:41.625096 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
5621 19:25:41.628516 0 14 28 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
5622 19:25:41.634876 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5623 19:25:41.638553 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5624 19:25:41.641706 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5625 19:25:41.648373 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5626 19:25:41.651338 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5627 19:25:41.654766 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5628 19:25:41.661224 0 15 24 | B1->B0 | 2525 2a2a | 0 1 | (0 0) (0 0)
5629 19:25:41.664772 0 15 28 | B1->B0 | 3939 4343 | 0 0 | (0 0) (0 0)
5630 19:25:41.671331 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5631 19:25:41.674220 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5632 19:25:41.677598 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5633 19:25:41.680920 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5634 19:25:41.687827 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5635 19:25:41.690954 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5636 19:25:41.694054 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5637 19:25:41.700830 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5638 19:25:41.704332 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5639 19:25:41.710714 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 19:25:41.714194 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 19:25:41.717232 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 19:25:41.724006 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 19:25:41.727193 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 19:25:41.730118 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 19:25:41.736823 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 19:25:41.740027 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 19:25:41.743243 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 19:25:41.750186 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 19:25:41.753589 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 19:25:41.756565 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 19:25:41.763525 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 19:25:41.766968 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 19:25:41.769979 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5654 19:25:41.776854 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5655 19:25:41.776932 Total UI for P1: 0, mck2ui 16
5656 19:25:41.783185 best dqsien dly found for B0: ( 1, 2, 28)
5657 19:25:41.786206 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5658 19:25:41.789456 Total UI for P1: 0, mck2ui 16
5659 19:25:41.793018 best dqsien dly found for B1: ( 1, 2, 30)
5660 19:25:41.796460 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5661 19:25:41.799389 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5662 19:25:41.799487
5663 19:25:41.803123 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5664 19:25:41.806123 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5665 19:25:41.809621 [Gating] SW calibration Done
5666 19:25:41.809692 ==
5667 19:25:41.813185 Dram Type= 6, Freq= 0, CH_1, rank 0
5668 19:25:41.816535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5669 19:25:41.816606 ==
5670 19:25:41.819283 RX Vref Scan: 0
5671 19:25:41.819355
5672 19:25:41.822829 RX Vref 0 -> 0, step: 1
5673 19:25:41.822900
5674 19:25:41.822960 RX Delay -80 -> 252, step: 8
5675 19:25:41.829344 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5676 19:25:41.832889 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5677 19:25:41.835808 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5678 19:25:41.839427 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5679 19:25:41.842503 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5680 19:25:41.849043 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5681 19:25:41.852456 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5682 19:25:41.855825 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5683 19:25:41.858748 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5684 19:25:41.862233 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5685 19:25:41.865781 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5686 19:25:41.872073 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5687 19:25:41.875461 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5688 19:25:41.878743 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5689 19:25:41.881801 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5690 19:25:41.885359 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5691 19:25:41.888813 ==
5692 19:25:41.892363 Dram Type= 6, Freq= 0, CH_1, rank 0
5693 19:25:41.895361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5694 19:25:41.895443 ==
5695 19:25:41.895508 DQS Delay:
5696 19:25:41.898687 DQS0 = 0, DQS1 = 0
5697 19:25:41.898768 DQM Delay:
5698 19:25:41.901968 DQM0 = 100, DQM1 = 95
5699 19:25:41.902048 DQ Delay:
5700 19:25:41.905074 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =99
5701 19:25:41.908212 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =95
5702 19:25:41.911648 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =87
5703 19:25:41.915220 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5704 19:25:41.915320
5705 19:25:41.915409
5706 19:25:41.915495 ==
5707 19:25:41.918174 Dram Type= 6, Freq= 0, CH_1, rank 0
5708 19:25:41.921688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5709 19:25:41.924760 ==
5710 19:25:41.924831
5711 19:25:41.924891
5712 19:25:41.924948 TX Vref Scan disable
5713 19:25:41.928339 == TX Byte 0 ==
5714 19:25:41.931785 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5715 19:25:41.934488 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5716 19:25:41.937966 == TX Byte 1 ==
5717 19:25:41.941631 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5718 19:25:41.944502 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5719 19:25:41.948164 ==
5720 19:25:41.951343 Dram Type= 6, Freq= 0, CH_1, rank 0
5721 19:25:41.954148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5722 19:25:41.954255 ==
5723 19:25:41.954346
5724 19:25:41.954433
5725 19:25:41.957668 TX Vref Scan disable
5726 19:25:41.957755 == TX Byte 0 ==
5727 19:25:41.964436 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5728 19:25:41.967596 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5729 19:25:41.967670 == TX Byte 1 ==
5730 19:25:41.974154 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5731 19:25:41.977091 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5732 19:25:41.977164
5733 19:25:41.977225 [DATLAT]
5734 19:25:41.980544 Freq=933, CH1 RK0
5735 19:25:41.980620
5736 19:25:41.980681 DATLAT Default: 0xd
5737 19:25:41.983894 0, 0xFFFF, sum = 0
5738 19:25:41.987347 1, 0xFFFF, sum = 0
5739 19:25:41.987448 2, 0xFFFF, sum = 0
5740 19:25:41.990365 3, 0xFFFF, sum = 0
5741 19:25:41.990463 4, 0xFFFF, sum = 0
5742 19:25:41.993889 5, 0xFFFF, sum = 0
5743 19:25:41.993988 6, 0xFFFF, sum = 0
5744 19:25:41.997346 7, 0xFFFF, sum = 0
5745 19:25:41.997443 8, 0xFFFF, sum = 0
5746 19:25:42.000641 9, 0xFFFF, sum = 0
5747 19:25:42.000738 10, 0x0, sum = 1
5748 19:25:42.003843 11, 0x0, sum = 2
5749 19:25:42.003981 12, 0x0, sum = 3
5750 19:25:42.006961 13, 0x0, sum = 4
5751 19:25:42.007057 best_step = 11
5752 19:25:42.007144
5753 19:25:42.007229 ==
5754 19:25:42.010524 Dram Type= 6, Freq= 0, CH_1, rank 0
5755 19:25:42.013899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5756 19:25:42.013996 ==
5757 19:25:42.016932 RX Vref Scan: 1
5758 19:25:42.017006
5759 19:25:42.020379 RX Vref 0 -> 0, step: 1
5760 19:25:42.020452
5761 19:25:42.020517 RX Delay -53 -> 252, step: 4
5762 19:25:42.023464
5763 19:25:42.023533 Set Vref, RX VrefLevel [Byte0]: 49
5764 19:25:42.027008 [Byte1]: 51
5765 19:25:42.031667
5766 19:25:42.031763 Final RX Vref Byte 0 = 49 to rank0
5767 19:25:42.035226 Final RX Vref Byte 1 = 51 to rank0
5768 19:25:42.038161 Final RX Vref Byte 0 = 49 to rank1
5769 19:25:42.041638 Final RX Vref Byte 1 = 51 to rank1==
5770 19:25:42.045094 Dram Type= 6, Freq= 0, CH_1, rank 0
5771 19:25:42.051784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5772 19:25:42.051924 ==
5773 19:25:42.051991 DQS Delay:
5774 19:25:42.055074 DQS0 = 0, DQS1 = 0
5775 19:25:42.055149 DQM Delay:
5776 19:25:42.055211 DQM0 = 97, DQM1 = 94
5777 19:25:42.058351 DQ Delay:
5778 19:25:42.061299 DQ0 =102, DQ1 =94, DQ2 =88, DQ3 =98
5779 19:25:42.064767 DQ4 =94, DQ5 =106, DQ6 =108, DQ7 =92
5780 19:25:42.068012 DQ8 =80, DQ9 =84, DQ10 =94, DQ11 =88
5781 19:25:42.071028 DQ12 =104, DQ13 =102, DQ14 =100, DQ15 =104
5782 19:25:42.071103
5783 19:25:42.071165
5784 19:25:42.077826 [DQSOSCAuto] RK0, (LSB)MR18= 0xb1a, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 418 ps
5785 19:25:42.080857 CH1 RK0: MR19=505, MR18=B1A
5786 19:25:42.087546 CH1_RK0: MR19=0x505, MR18=0xB1A, DQSOSC=413, MR23=63, INC=63, DEC=42
5787 19:25:42.087632
5788 19:25:42.091267 ----->DramcWriteLeveling(PI) begin...
5789 19:25:42.091343 ==
5790 19:25:42.093993 Dram Type= 6, Freq= 0, CH_1, rank 1
5791 19:25:42.097646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5792 19:25:42.097745 ==
5793 19:25:42.100982 Write leveling (Byte 0): 24 => 24
5794 19:25:42.104522 Write leveling (Byte 1): 29 => 29
5795 19:25:42.107353 DramcWriteLeveling(PI) end<-----
5796 19:25:42.107425
5797 19:25:42.107487 ==
5798 19:25:42.110448 Dram Type= 6, Freq= 0, CH_1, rank 1
5799 19:25:42.117393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5800 19:25:42.117471 ==
5801 19:25:42.117533 [Gating] SW mode calibration
5802 19:25:42.127157 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5803 19:25:42.130184 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5804 19:25:42.136766 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
5805 19:25:42.140610 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5806 19:25:42.143794 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5807 19:25:42.150322 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5808 19:25:42.153378 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5809 19:25:42.156765 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5810 19:25:42.163171 0 14 24 | B1->B0 | 3131 3030 | 1 0 | (1 1) (0 1)
5811 19:25:42.166622 0 14 28 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
5812 19:25:42.169763 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5813 19:25:42.176478 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5814 19:25:42.180491 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5815 19:25:42.183340 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5816 19:25:42.189669 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5817 19:25:42.193007 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5818 19:25:42.196498 0 15 24 | B1->B0 | 2d2d 3737 | 1 1 | (0 0) (0 0)
5819 19:25:42.202741 0 15 28 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
5820 19:25:42.205806 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5821 19:25:42.209724 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5822 19:25:42.215720 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5823 19:25:42.219217 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5824 19:25:42.222134 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5825 19:25:42.228795 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5826 19:25:42.232557 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5827 19:25:42.235782 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5828 19:25:42.242400 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 19:25:42.245314 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 19:25:42.248715 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 19:25:42.255170 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 19:25:42.258655 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 19:25:42.261895 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 19:25:42.268255 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 19:25:42.271754 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 19:25:42.275133 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 19:25:42.281387 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 19:25:42.284742 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 19:25:42.288213 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 19:25:42.295119 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 19:25:42.298185 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 19:25:42.301479 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5843 19:25:42.307822 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5844 19:25:42.311495 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5845 19:25:42.314929 Total UI for P1: 0, mck2ui 16
5846 19:25:42.317559 best dqsien dly found for B0: ( 1, 2, 26)
5847 19:25:42.321175 Total UI for P1: 0, mck2ui 16
5848 19:25:42.323958 best dqsien dly found for B1: ( 1, 2, 28)
5849 19:25:42.327388 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5850 19:25:42.330756 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5851 19:25:42.330867
5852 19:25:42.333960 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5853 19:25:42.337318 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5854 19:25:42.340811 [Gating] SW calibration Done
5855 19:25:42.340924 ==
5856 19:25:42.343664 Dram Type= 6, Freq= 0, CH_1, rank 1
5857 19:25:42.350911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5858 19:25:42.351018 ==
5859 19:25:42.351110 RX Vref Scan: 0
5860 19:25:42.351203
5861 19:25:42.353708 RX Vref 0 -> 0, step: 1
5862 19:25:42.353812
5863 19:25:42.357279 RX Delay -80 -> 252, step: 8
5864 19:25:42.360352 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5865 19:25:42.363990 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5866 19:25:42.367105 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5867 19:25:42.370261 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5868 19:25:42.376659 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5869 19:25:42.379962 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5870 19:25:42.383225 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5871 19:25:42.386919 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5872 19:25:42.390036 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5873 19:25:42.393580 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5874 19:25:42.400356 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5875 19:25:42.403353 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5876 19:25:42.406474 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5877 19:25:42.409928 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5878 19:25:42.413167 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5879 19:25:42.419583 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5880 19:25:42.419697 ==
5881 19:25:42.423068 Dram Type= 6, Freq= 0, CH_1, rank 1
5882 19:25:42.426092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5883 19:25:42.426204 ==
5884 19:25:42.426303 DQS Delay:
5885 19:25:42.429689 DQS0 = 0, DQS1 = 0
5886 19:25:42.429799 DQM Delay:
5887 19:25:42.433849 DQM0 = 97, DQM1 = 94
5888 19:25:42.433965 DQ Delay:
5889 19:25:42.436321 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =95
5890 19:25:42.439329 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5891 19:25:42.442663 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5892 19:25:42.446373 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5893 19:25:42.446483
5894 19:25:42.446583
5895 19:25:42.446677 ==
5896 19:25:42.449636 Dram Type= 6, Freq= 0, CH_1, rank 1
5897 19:25:42.455824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5898 19:25:42.455958 ==
5899 19:25:42.456056
5900 19:25:42.456151
5901 19:25:42.456245 TX Vref Scan disable
5902 19:25:42.459775 == TX Byte 0 ==
5903 19:25:42.462432 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5904 19:25:42.469303 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5905 19:25:42.469414 == TX Byte 1 ==
5906 19:25:42.472910 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5907 19:25:42.479623 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5908 19:25:42.479734 ==
5909 19:25:42.482550 Dram Type= 6, Freq= 0, CH_1, rank 1
5910 19:25:42.486013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5911 19:25:42.486119 ==
5912 19:25:42.486210
5913 19:25:42.486298
5914 19:25:42.489587 TX Vref Scan disable
5915 19:25:42.489699 == TX Byte 0 ==
5916 19:25:42.495968 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5917 19:25:42.498891 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5918 19:25:42.502611 == TX Byte 1 ==
5919 19:25:42.505760 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5920 19:25:42.509183 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5921 19:25:42.509294
5922 19:25:42.509393 [DATLAT]
5923 19:25:42.512340 Freq=933, CH1 RK1
5924 19:25:42.512452
5925 19:25:42.515451 DATLAT Default: 0xb
5926 19:25:42.515560 0, 0xFFFF, sum = 0
5927 19:25:42.518888 1, 0xFFFF, sum = 0
5928 19:25:42.519015 2, 0xFFFF, sum = 0
5929 19:25:42.522090 3, 0xFFFF, sum = 0
5930 19:25:42.522205 4, 0xFFFF, sum = 0
5931 19:25:42.525128 5, 0xFFFF, sum = 0
5932 19:25:42.525235 6, 0xFFFF, sum = 0
5933 19:25:42.528600 7, 0xFFFF, sum = 0
5934 19:25:42.528738 8, 0xFFFF, sum = 0
5935 19:25:42.531969 9, 0xFFFF, sum = 0
5936 19:25:42.532075 10, 0x0, sum = 1
5937 19:25:42.534856 11, 0x0, sum = 2
5938 19:25:42.534961 12, 0x0, sum = 3
5939 19:25:42.538506 13, 0x0, sum = 4
5940 19:25:42.538611 best_step = 11
5941 19:25:42.538706
5942 19:25:42.538795 ==
5943 19:25:42.541782 Dram Type= 6, Freq= 0, CH_1, rank 1
5944 19:25:42.545209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5945 19:25:42.548288 ==
5946 19:25:42.548395 RX Vref Scan: 0
5947 19:25:42.548489
5948 19:25:42.551381 RX Vref 0 -> 0, step: 1
5949 19:25:42.551494
5950 19:25:42.554530 RX Delay -53 -> 252, step: 4
5951 19:25:42.558184 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5952 19:25:42.561410 iDelay=199, Bit 1, Center 92 (-1 ~ 186) 188
5953 19:25:42.568116 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5954 19:25:42.570982 iDelay=199, Bit 3, Center 96 (3 ~ 190) 188
5955 19:25:42.574370 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5956 19:25:42.577923 iDelay=199, Bit 5, Center 104 (11 ~ 198) 188
5957 19:25:42.580925 iDelay=199, Bit 6, Center 104 (15 ~ 194) 180
5958 19:25:42.584281 iDelay=199, Bit 7, Center 92 (-1 ~ 186) 188
5959 19:25:42.590767 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5960 19:25:42.594275 iDelay=199, Bit 9, Center 84 (-5 ~ 174) 180
5961 19:25:42.597317 iDelay=199, Bit 10, Center 92 (-1 ~ 186) 188
5962 19:25:42.601090 iDelay=199, Bit 11, Center 84 (-9 ~ 178) 188
5963 19:25:42.607254 iDelay=199, Bit 12, Center 100 (11 ~ 190) 180
5964 19:25:42.610495 iDelay=199, Bit 13, Center 102 (11 ~ 194) 184
5965 19:25:42.613774 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5966 19:25:42.617052 iDelay=199, Bit 15, Center 102 (11 ~ 194) 184
5967 19:25:42.617158 ==
5968 19:25:42.620155 Dram Type= 6, Freq= 0, CH_1, rank 1
5969 19:25:42.623805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5970 19:25:42.626975 ==
5971 19:25:42.627080 DQS Delay:
5972 19:25:42.627172 DQS0 = 0, DQS1 = 0
5973 19:25:42.630346 DQM Delay:
5974 19:25:42.630450 DQM0 = 96, DQM1 = 92
5975 19:25:42.633533 DQ Delay:
5976 19:25:42.636745 DQ0 =102, DQ1 =92, DQ2 =86, DQ3 =96
5977 19:25:42.640284 DQ4 =96, DQ5 =104, DQ6 =104, DQ7 =92
5978 19:25:42.643123 DQ8 =80, DQ9 =84, DQ10 =92, DQ11 =84
5979 19:25:42.646924 DQ12 =100, DQ13 =102, DQ14 =96, DQ15 =102
5980 19:25:42.647031
5981 19:25:42.647127
5982 19:25:42.653205 [DQSOSCAuto] RK1, (LSB)MR18= 0xf26, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 417 ps
5983 19:25:42.656646 CH1 RK1: MR19=505, MR18=F26
5984 19:25:42.663093 CH1_RK1: MR19=0x505, MR18=0xF26, DQSOSC=409, MR23=63, INC=64, DEC=43
5985 19:25:42.666347 [RxdqsGatingPostProcess] freq 933
5986 19:25:42.669814 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5987 19:25:42.673284 best DQS0 dly(2T, 0.5T) = (0, 10)
5988 19:25:42.676224 best DQS1 dly(2T, 0.5T) = (0, 10)
5989 19:25:42.679680 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5990 19:25:42.683214 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5991 19:25:42.686162 best DQS0 dly(2T, 0.5T) = (0, 10)
5992 19:25:42.689458 best DQS1 dly(2T, 0.5T) = (0, 10)
5993 19:25:42.692665 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5994 19:25:42.696185 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5995 19:25:42.699422 Pre-setting of DQS Precalculation
5996 19:25:42.703020 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5997 19:25:42.712525 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5998 19:25:42.718833 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5999 19:25:42.718941
6000 19:25:42.719032
6001 19:25:42.722278 [Calibration Summary] 1866 Mbps
6002 19:25:42.722383 CH 0, Rank 0
6003 19:25:42.725779 SW Impedance : PASS
6004 19:25:42.729072 DUTY Scan : NO K
6005 19:25:42.729210 ZQ Calibration : PASS
6006 19:25:42.732012 Jitter Meter : NO K
6007 19:25:42.735600 CBT Training : PASS
6008 19:25:42.735708 Write leveling : PASS
6009 19:25:42.738476 RX DQS gating : PASS
6010 19:25:42.738581 RX DQ/DQS(RDDQC) : PASS
6011 19:25:42.742162 TX DQ/DQS : PASS
6012 19:25:42.745560 RX DATLAT : PASS
6013 19:25:42.745666 RX DQ/DQS(Engine): PASS
6014 19:25:42.749182 TX OE : NO K
6015 19:25:42.749286 All Pass.
6016 19:25:42.749382
6017 19:25:42.751719 CH 0, Rank 1
6018 19:25:42.751822 SW Impedance : PASS
6019 19:25:42.755142 DUTY Scan : NO K
6020 19:25:42.758706 ZQ Calibration : PASS
6021 19:25:42.758810 Jitter Meter : NO K
6022 19:25:42.762109 CBT Training : PASS
6023 19:25:42.764906 Write leveling : PASS
6024 19:25:42.765010 RX DQS gating : PASS
6025 19:25:42.768387 RX DQ/DQS(RDDQC) : PASS
6026 19:25:42.771513 TX DQ/DQS : PASS
6027 19:25:42.771647 RX DATLAT : PASS
6028 19:25:42.774988 RX DQ/DQS(Engine): PASS
6029 19:25:42.778590 TX OE : NO K
6030 19:25:42.778696 All Pass.
6031 19:25:42.778793
6032 19:25:42.778882 CH 1, Rank 0
6033 19:25:42.781510 SW Impedance : PASS
6034 19:25:42.785227 DUTY Scan : NO K
6035 19:25:42.785349 ZQ Calibration : PASS
6036 19:25:42.788221 Jitter Meter : NO K
6037 19:25:42.791247 CBT Training : PASS
6038 19:25:42.791350 Write leveling : PASS
6039 19:25:42.794931 RX DQS gating : PASS
6040 19:25:42.798559 RX DQ/DQS(RDDQC) : PASS
6041 19:25:42.798662 TX DQ/DQS : PASS
6042 19:25:42.801219 RX DATLAT : PASS
6043 19:25:42.804716 RX DQ/DQS(Engine): PASS
6044 19:25:42.804820 TX OE : NO K
6045 19:25:42.807822 All Pass.
6046 19:25:42.807962
6047 19:25:42.808057 CH 1, Rank 1
6048 19:25:42.811156 SW Impedance : PASS
6049 19:25:42.811262 DUTY Scan : NO K
6050 19:25:42.814419 ZQ Calibration : PASS
6051 19:25:42.817641 Jitter Meter : NO K
6052 19:25:42.817748 CBT Training : PASS
6053 19:25:42.820888 Write leveling : PASS
6054 19:25:42.824355 RX DQS gating : PASS
6055 19:25:42.824460 RX DQ/DQS(RDDQC) : PASS
6056 19:25:42.827712 TX DQ/DQS : PASS
6057 19:25:42.827819 RX DATLAT : PASS
6058 19:25:42.830685 RX DQ/DQS(Engine): PASS
6059 19:25:42.834390 TX OE : NO K
6060 19:25:42.834496 All Pass.
6061 19:25:42.834587
6062 19:25:42.837643 DramC Write-DBI off
6063 19:25:42.840966 PER_BANK_REFRESH: Hybrid Mode
6064 19:25:42.841071 TX_TRACKING: ON
6065 19:25:42.850358 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6066 19:25:42.853946 [FAST_K] Save calibration result to emmc
6067 19:25:42.857362 dramc_set_vcore_voltage set vcore to 650000
6068 19:25:42.860885 Read voltage for 400, 6
6069 19:25:42.860991 Vio18 = 0
6070 19:25:42.861083 Vcore = 650000
6071 19:25:42.863846 Vdram = 0
6072 19:25:42.863985 Vddq = 0
6073 19:25:42.864077 Vmddr = 0
6074 19:25:42.870872 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6075 19:25:42.873624 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6076 19:25:42.877361 MEM_TYPE=3, freq_sel=20
6077 19:25:42.880139 sv_algorithm_assistance_LP4_800
6078 19:25:42.883722 ============ PULL DRAM RESETB DOWN ============
6079 19:25:42.886659 ========== PULL DRAM RESETB DOWN end =========
6080 19:25:42.893271 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6081 19:25:42.896822 ===================================
6082 19:25:42.896926 LPDDR4 DRAM CONFIGURATION
6083 19:25:42.900231 ===================================
6084 19:25:42.903182 EX_ROW_EN[0] = 0x0
6085 19:25:42.906534 EX_ROW_EN[1] = 0x0
6086 19:25:42.906638 LP4Y_EN = 0x0
6087 19:25:42.909967 WORK_FSP = 0x0
6088 19:25:42.910071 WL = 0x2
6089 19:25:42.913302 RL = 0x2
6090 19:25:42.913407 BL = 0x2
6091 19:25:42.916379 RPST = 0x0
6092 19:25:42.916485 RD_PRE = 0x0
6093 19:25:42.919494 WR_PRE = 0x1
6094 19:25:42.919598 WR_PST = 0x0
6095 19:25:42.923175 DBI_WR = 0x0
6096 19:25:42.923317 DBI_RD = 0x0
6097 19:25:42.926244 OTF = 0x1
6098 19:25:42.929578 ===================================
6099 19:25:42.932977 ===================================
6100 19:25:42.933086 ANA top config
6101 19:25:42.936404 ===================================
6102 19:25:42.939373 DLL_ASYNC_EN = 0
6103 19:25:42.942768 ALL_SLAVE_EN = 1
6104 19:25:42.946334 NEW_RANK_MODE = 1
6105 19:25:42.946445 DLL_IDLE_MODE = 1
6106 19:25:42.949133 LP45_APHY_COMB_EN = 1
6107 19:25:42.952836 TX_ODT_DIS = 1
6108 19:25:42.956267 NEW_8X_MODE = 1
6109 19:25:42.959035 ===================================
6110 19:25:42.962737 ===================================
6111 19:25:42.965751 data_rate = 800
6112 19:25:42.969243 CKR = 1
6113 19:25:42.969356 DQ_P2S_RATIO = 4
6114 19:25:42.972135 ===================================
6115 19:25:42.975708 CA_P2S_RATIO = 4
6116 19:25:42.979144 DQ_CA_OPEN = 0
6117 19:25:42.982174 DQ_SEMI_OPEN = 1
6118 19:25:42.985876 CA_SEMI_OPEN = 1
6119 19:25:42.988563 CA_FULL_RATE = 0
6120 19:25:42.988676 DQ_CKDIV4_EN = 0
6121 19:25:42.992170 CA_CKDIV4_EN = 1
6122 19:25:42.995109 CA_PREDIV_EN = 0
6123 19:25:42.998719 PH8_DLY = 0
6124 19:25:43.002278 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6125 19:25:43.005153 DQ_AAMCK_DIV = 0
6126 19:25:43.008823 CA_AAMCK_DIV = 0
6127 19:25:43.008930 CA_ADMCK_DIV = 4
6128 19:25:43.012128 DQ_TRACK_CA_EN = 0
6129 19:25:43.015142 CA_PICK = 800
6130 19:25:43.018367 CA_MCKIO = 400
6131 19:25:43.021743 MCKIO_SEMI = 400
6132 19:25:43.025212 PLL_FREQ = 3016
6133 19:25:43.028437 DQ_UI_PI_RATIO = 32
6134 19:25:43.028547 CA_UI_PI_RATIO = 32
6135 19:25:43.031555 ===================================
6136 19:25:43.035157 ===================================
6137 19:25:43.038289 memory_type:LPDDR4
6138 19:25:43.041541 GP_NUM : 10
6139 19:25:43.041653 SRAM_EN : 1
6140 19:25:43.045162 MD32_EN : 0
6141 19:25:43.048270 ===================================
6142 19:25:43.051468 [ANA_INIT] >>>>>>>>>>>>>>
6143 19:25:43.054989 <<<<<< [CONFIGURE PHASE]: ANA_TX
6144 19:25:43.057796 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6145 19:25:43.061140 ===================================
6146 19:25:43.064579 data_rate = 800,PCW = 0X7400
6147 19:25:43.067562 ===================================
6148 19:25:43.071207 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6149 19:25:43.074322 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6150 19:25:43.087655 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6151 19:25:43.090863 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6152 19:25:43.094137 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6153 19:25:43.097278 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6154 19:25:43.100468 [ANA_INIT] flow start
6155 19:25:43.104039 [ANA_INIT] PLL >>>>>>>>
6156 19:25:43.104152 [ANA_INIT] PLL <<<<<<<<
6157 19:25:43.107025 [ANA_INIT] MIDPI >>>>>>>>
6158 19:25:43.110593 [ANA_INIT] MIDPI <<<<<<<<
6159 19:25:43.110704 [ANA_INIT] DLL >>>>>>>>
6160 19:25:43.114103 [ANA_INIT] flow end
6161 19:25:43.117103 ============ LP4 DIFF to SE enter ============
6162 19:25:43.120375 ============ LP4 DIFF to SE exit ============
6163 19:25:43.124041 [ANA_INIT] <<<<<<<<<<<<<
6164 19:25:43.126710 [Flow] Enable top DCM control >>>>>
6165 19:25:43.130167 [Flow] Enable top DCM control <<<<<
6166 19:25:43.133453 Enable DLL master slave shuffle
6167 19:25:43.140186 ==============================================================
6168 19:25:43.140306 Gating Mode config
6169 19:25:43.146593 ==============================================================
6170 19:25:43.150330 Config description:
6171 19:25:43.156362 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6172 19:25:43.163796 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6173 19:25:43.170400 SELPH_MODE 0: By rank 1: By Phase
6174 19:25:43.176756 ==============================================================
6175 19:25:43.176872 GAT_TRACK_EN = 0
6176 19:25:43.179811 RX_GATING_MODE = 2
6177 19:25:43.183936 RX_GATING_TRACK_MODE = 2
6178 19:25:43.186558 SELPH_MODE = 1
6179 19:25:43.189582 PICG_EARLY_EN = 1
6180 19:25:43.193094 VALID_LAT_VALUE = 1
6181 19:25:43.199831 ==============================================================
6182 19:25:43.202967 Enter into Gating configuration >>>>
6183 19:25:43.206521 Exit from Gating configuration <<<<
6184 19:25:43.209482 Enter into DVFS_PRE_config >>>>>
6185 19:25:43.219566 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6186 19:25:43.223095 Exit from DVFS_PRE_config <<<<<
6187 19:25:43.225775 Enter into PICG configuration >>>>
6188 19:25:43.229688 Exit from PICG configuration <<<<
6189 19:25:43.232924 [RX_INPUT] configuration >>>>>
6190 19:25:43.236108 [RX_INPUT] configuration <<<<<
6191 19:25:43.239781 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6192 19:25:43.245996 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6193 19:25:43.252279 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6194 19:25:43.258607 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6195 19:25:43.262313 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6196 19:25:43.269010 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6197 19:25:43.271808 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6198 19:25:43.278769 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6199 19:25:43.281659 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6200 19:25:43.285089 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6201 19:25:43.288299 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6202 19:25:43.295150 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6203 19:25:43.298371 ===================================
6204 19:25:43.301486 LPDDR4 DRAM CONFIGURATION
6205 19:25:43.304748 ===================================
6206 19:25:43.304832 EX_ROW_EN[0] = 0x0
6207 19:25:43.308517 EX_ROW_EN[1] = 0x0
6208 19:25:43.308602 LP4Y_EN = 0x0
6209 19:25:43.311606 WORK_FSP = 0x0
6210 19:25:43.311715 WL = 0x2
6211 19:25:43.314624 RL = 0x2
6212 19:25:43.314707 BL = 0x2
6213 19:25:43.318127 RPST = 0x0
6214 19:25:43.318209 RD_PRE = 0x0
6215 19:25:43.321295 WR_PRE = 0x1
6216 19:25:43.324655 WR_PST = 0x0
6217 19:25:43.324744 DBI_WR = 0x0
6218 19:25:43.327538 DBI_RD = 0x0
6219 19:25:43.327621 OTF = 0x1
6220 19:25:43.330913 ===================================
6221 19:25:43.334463 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6222 19:25:43.341024 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6223 19:25:43.344608 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6224 19:25:43.347450 ===================================
6225 19:25:43.350900 LPDDR4 DRAM CONFIGURATION
6226 19:25:43.353903 ===================================
6227 19:25:43.353993 EX_ROW_EN[0] = 0x10
6228 19:25:43.357450 EX_ROW_EN[1] = 0x0
6229 19:25:43.357532 LP4Y_EN = 0x0
6230 19:25:43.360516 WORK_FSP = 0x0
6231 19:25:43.360598 WL = 0x2
6232 19:25:43.364005 RL = 0x2
6233 19:25:43.367593 BL = 0x2
6234 19:25:43.367677 RPST = 0x0
6235 19:25:43.370730 RD_PRE = 0x0
6236 19:25:43.370813 WR_PRE = 0x1
6237 19:25:43.374031 WR_PST = 0x0
6238 19:25:43.374114 DBI_WR = 0x0
6239 19:25:43.377127 DBI_RD = 0x0
6240 19:25:43.377248 OTF = 0x1
6241 19:25:43.380687 ===================================
6242 19:25:43.387139 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6243 19:25:43.390839 nWR fixed to 30
6244 19:25:43.394019 [ModeRegInit_LP4] CH0 RK0
6245 19:25:43.394098 [ModeRegInit_LP4] CH0 RK1
6246 19:25:43.397805 [ModeRegInit_LP4] CH1 RK0
6247 19:25:43.400912 [ModeRegInit_LP4] CH1 RK1
6248 19:25:43.400988 match AC timing 19
6249 19:25:43.407847 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6250 19:25:43.410913 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6251 19:25:43.413692 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6252 19:25:43.420341 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6253 19:25:43.423809 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6254 19:25:43.423919 ==
6255 19:25:43.427377 Dram Type= 6, Freq= 0, CH_0, rank 0
6256 19:25:43.430694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6257 19:25:43.430783 ==
6258 19:25:43.436915 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6259 19:25:43.444032 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6260 19:25:43.446709 [CA 0] Center 36 (8~64) winsize 57
6261 19:25:43.450174 [CA 1] Center 36 (8~64) winsize 57
6262 19:25:43.453313 [CA 2] Center 36 (8~64) winsize 57
6263 19:25:43.456900 [CA 3] Center 36 (8~64) winsize 57
6264 19:25:43.459901 [CA 4] Center 36 (8~64) winsize 57
6265 19:25:43.463407 [CA 5] Center 36 (8~64) winsize 57
6266 19:25:43.463483
6267 19:25:43.466889 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6268 19:25:43.466965
6269 19:25:43.470238 [CATrainingPosCal] consider 1 rank data
6270 19:25:43.473450 u2DelayCellTimex100 = 270/100 ps
6271 19:25:43.476567 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6272 19:25:43.479574 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6273 19:25:43.483381 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6274 19:25:43.486346 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6275 19:25:43.489590 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6276 19:25:43.493101 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6277 19:25:43.493193
6278 19:25:43.499530 CA PerBit enable=1, Macro0, CA PI delay=36
6279 19:25:43.499618
6280 19:25:43.502716 [CBTSetCACLKResult] CA Dly = 36
6281 19:25:43.502793 CS Dly: 1 (0~32)
6282 19:25:43.502857 ==
6283 19:25:43.506111 Dram Type= 6, Freq= 0, CH_0, rank 1
6284 19:25:43.509461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6285 19:25:43.509547 ==
6286 19:25:43.516118 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6287 19:25:43.522624 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6288 19:25:43.525906 [CA 0] Center 36 (8~64) winsize 57
6289 19:25:43.529573 [CA 1] Center 36 (8~64) winsize 57
6290 19:25:43.532396 [CA 2] Center 36 (8~64) winsize 57
6291 19:25:43.535916 [CA 3] Center 36 (8~64) winsize 57
6292 19:25:43.539322 [CA 4] Center 36 (8~64) winsize 57
6293 19:25:43.539432 [CA 5] Center 36 (8~64) winsize 57
6294 19:25:43.542373
6295 19:25:43.545999 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6296 19:25:43.546101
6297 19:25:43.548648 [CATrainingPosCal] consider 2 rank data
6298 19:25:43.552077 u2DelayCellTimex100 = 270/100 ps
6299 19:25:43.555386 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6300 19:25:43.558967 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6301 19:25:43.561820 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6302 19:25:43.565350 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6303 19:25:43.568758 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6304 19:25:43.572067 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6305 19:25:43.572141
6306 19:25:43.578177 CA PerBit enable=1, Macro0, CA PI delay=36
6307 19:25:43.578262
6308 19:25:43.578328 [CBTSetCACLKResult] CA Dly = 36
6309 19:25:43.581686 CS Dly: 1 (0~32)
6310 19:25:43.581769
6311 19:25:43.584922 ----->DramcWriteLeveling(PI) begin...
6312 19:25:43.585007 ==
6313 19:25:43.588643 Dram Type= 6, Freq= 0, CH_0, rank 0
6314 19:25:43.591817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6315 19:25:43.591915 ==
6316 19:25:43.595025 Write leveling (Byte 0): 40 => 8
6317 19:25:43.600480 Write leveling (Byte 1): 40 => 8
6318 19:25:43.601466 DramcWriteLeveling(PI) end<-----
6319 19:25:43.601546
6320 19:25:43.601608 ==
6321 19:25:43.604957 Dram Type= 6, Freq= 0, CH_0, rank 0
6322 19:25:43.608370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6323 19:25:43.611581 ==
6324 19:25:43.611726 [Gating] SW mode calibration
6325 19:25:43.621148 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6326 19:25:43.624911 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6327 19:25:43.627601 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6328 19:25:43.634693 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6329 19:25:43.637677 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6330 19:25:43.641282 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6331 19:25:43.648218 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6332 19:25:43.650895 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6333 19:25:43.654272 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6334 19:25:43.661065 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6335 19:25:43.664511 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6336 19:25:43.667812 Total UI for P1: 0, mck2ui 16
6337 19:25:43.671121 best dqsien dly found for B0: ( 0, 14, 24)
6338 19:25:43.674247 Total UI for P1: 0, mck2ui 16
6339 19:25:43.677670 best dqsien dly found for B1: ( 0, 14, 24)
6340 19:25:43.680537 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6341 19:25:43.684110 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6342 19:25:43.684188
6343 19:25:43.687128 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6344 19:25:43.693880 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6345 19:25:43.693970 [Gating] SW calibration Done
6346 19:25:43.694057 ==
6347 19:25:43.697163 Dram Type= 6, Freq= 0, CH_0, rank 0
6348 19:25:43.703408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6349 19:25:43.703494 ==
6350 19:25:43.703597 RX Vref Scan: 0
6351 19:25:43.703696
6352 19:25:43.707219 RX Vref 0 -> 0, step: 1
6353 19:25:43.707304
6354 19:25:43.709916 RX Delay -410 -> 252, step: 16
6355 19:25:43.713525 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6356 19:25:43.716842 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6357 19:25:43.723105 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6358 19:25:43.726624 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6359 19:25:43.730213 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6360 19:25:43.733191 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6361 19:25:43.739909 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6362 19:25:43.743080 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6363 19:25:43.746550 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6364 19:25:43.749782 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6365 19:25:43.756062 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6366 19:25:43.759458 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6367 19:25:43.762660 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6368 19:25:43.769150 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6369 19:25:43.772593 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6370 19:25:43.776147 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6371 19:25:43.776227 ==
6372 19:25:43.779201 Dram Type= 6, Freq= 0, CH_0, rank 0
6373 19:25:43.785695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6374 19:25:43.785779 ==
6375 19:25:43.785842 DQS Delay:
6376 19:25:43.789260 DQS0 = 35, DQS1 = 51
6377 19:25:43.789340 DQM Delay:
6378 19:25:43.789403 DQM0 = 4, DQM1 = 10
6379 19:25:43.792350 DQ Delay:
6380 19:25:43.795715 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6381 19:25:43.795795 DQ4 =0, DQ5 =0, DQ6 =16, DQ7 =16
6382 19:25:43.799131 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6383 19:25:43.802530 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6384 19:25:43.802610
6385 19:25:43.805305
6386 19:25:43.805386 ==
6387 19:25:43.808737 Dram Type= 6, Freq= 0, CH_0, rank 0
6388 19:25:43.812066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6389 19:25:43.812146 ==
6390 19:25:43.812210
6391 19:25:43.812267
6392 19:25:43.816118 TX Vref Scan disable
6393 19:25:43.816198 == TX Byte 0 ==
6394 19:25:43.818618 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6395 19:25:43.824994 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6396 19:25:43.825104 == TX Byte 1 ==
6397 19:25:43.828361 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6398 19:25:43.835110 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6399 19:25:43.835213 ==
6400 19:25:43.838014 Dram Type= 6, Freq= 0, CH_0, rank 0
6401 19:25:43.841354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6402 19:25:43.841437 ==
6403 19:25:43.841501
6404 19:25:43.841560
6405 19:25:43.844869 TX Vref Scan disable
6406 19:25:43.844936 == TX Byte 0 ==
6407 19:25:43.851308 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6408 19:25:43.855252 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6409 19:25:43.855333 == TX Byte 1 ==
6410 19:25:43.861410 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6411 19:25:43.864696 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6412 19:25:43.864777
6413 19:25:43.864840 [DATLAT]
6414 19:25:43.867594 Freq=400, CH0 RK0
6415 19:25:43.867674
6416 19:25:43.867737 DATLAT Default: 0xf
6417 19:25:43.870857 0, 0xFFFF, sum = 0
6418 19:25:43.870940 1, 0xFFFF, sum = 0
6419 19:25:43.874471 2, 0xFFFF, sum = 0
6420 19:25:43.874552 3, 0xFFFF, sum = 0
6421 19:25:43.877913 4, 0xFFFF, sum = 0
6422 19:25:43.878023 5, 0xFFFF, sum = 0
6423 19:25:43.880954 6, 0xFFFF, sum = 0
6424 19:25:43.881036 7, 0xFFFF, sum = 0
6425 19:25:43.884377 8, 0xFFFF, sum = 0
6426 19:25:43.884458 9, 0xFFFF, sum = 0
6427 19:25:43.887335 10, 0xFFFF, sum = 0
6428 19:25:43.890854 11, 0xFFFF, sum = 0
6429 19:25:43.890936 12, 0xFFFF, sum = 0
6430 19:25:43.893847 13, 0x0, sum = 1
6431 19:25:43.893928 14, 0x0, sum = 2
6432 19:25:43.897209 15, 0x0, sum = 3
6433 19:25:43.897291 16, 0x0, sum = 4
6434 19:25:43.897355 best_step = 14
6435 19:25:43.900756
6436 19:25:43.900860 ==
6437 19:25:43.904021 Dram Type= 6, Freq= 0, CH_0, rank 0
6438 19:25:43.907095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6439 19:25:43.907199 ==
6440 19:25:43.907264 RX Vref Scan: 1
6441 19:25:43.907323
6442 19:25:43.910497 RX Vref 0 -> 0, step: 1
6443 19:25:43.910594
6444 19:25:43.913926 RX Delay -343 -> 252, step: 8
6445 19:25:43.914024
6446 19:25:43.917115 Set Vref, RX VrefLevel [Byte0]: 52
6447 19:25:43.920303 [Byte1]: 60
6448 19:25:43.924583
6449 19:25:43.924663 Final RX Vref Byte 0 = 52 to rank0
6450 19:25:43.928202 Final RX Vref Byte 1 = 60 to rank0
6451 19:25:43.931266 Final RX Vref Byte 0 = 52 to rank1
6452 19:25:43.934140 Final RX Vref Byte 1 = 60 to rank1==
6453 19:25:43.937450 Dram Type= 6, Freq= 0, CH_0, rank 0
6454 19:25:43.944236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6455 19:25:43.944314 ==
6456 19:25:43.944380 DQS Delay:
6457 19:25:43.947141 DQS0 = 44, DQS1 = 60
6458 19:25:43.947237 DQM Delay:
6459 19:25:43.947325 DQM0 = 10, DQM1 = 16
6460 19:25:43.950655 DQ Delay:
6461 19:25:43.954356 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =4
6462 19:25:43.957423 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6463 19:25:43.960769 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =12
6464 19:25:43.963856 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6465 19:25:43.963965
6466 19:25:43.964044
6467 19:25:43.970183 [DQSOSCAuto] RK0, (LSB)MR18= 0x9a8d, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
6468 19:25:43.973547 CH0 RK0: MR19=C0C, MR18=9A8D
6469 19:25:43.980471 CH0_RK0: MR19=0xC0C, MR18=0x9A8D, DQSOSC=390, MR23=63, INC=388, DEC=258
6470 19:25:43.980559 ==
6471 19:25:43.983470 Dram Type= 6, Freq= 0, CH_0, rank 1
6472 19:25:43.986896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6473 19:25:43.986980 ==
6474 19:25:43.989858 [Gating] SW mode calibration
6475 19:25:43.996773 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6476 19:25:44.002962 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6477 19:25:44.006875 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6478 19:25:44.009599 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6479 19:25:44.016501 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6480 19:25:44.019422 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6481 19:25:44.022760 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6482 19:25:44.029559 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6483 19:25:44.032980 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6484 19:25:44.035903 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6485 19:25:44.043006 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6486 19:25:44.046290 Total UI for P1: 0, mck2ui 16
6487 19:25:44.049612 best dqsien dly found for B0: ( 0, 14, 24)
6488 19:25:44.052583 Total UI for P1: 0, mck2ui 16
6489 19:25:44.056114 best dqsien dly found for B1: ( 0, 14, 24)
6490 19:25:44.059025 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6491 19:25:44.062449 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6492 19:25:44.062531
6493 19:25:44.065835 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6494 19:25:44.068782 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6495 19:25:44.072160 [Gating] SW calibration Done
6496 19:25:44.072242 ==
6497 19:25:44.075584 Dram Type= 6, Freq= 0, CH_0, rank 1
6498 19:25:44.078869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6499 19:25:44.082281 ==
6500 19:25:44.082362 RX Vref Scan: 0
6501 19:25:44.082426
6502 19:25:44.085532 RX Vref 0 -> 0, step: 1
6503 19:25:44.085613
6504 19:25:44.089074 RX Delay -410 -> 252, step: 16
6505 19:25:44.092167 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6506 19:25:44.095207 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6507 19:25:44.098617 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6508 19:25:44.105099 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6509 19:25:44.108629 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6510 19:25:44.111447 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6511 19:25:44.115054 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6512 19:25:44.121823 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6513 19:25:44.125097 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6514 19:25:44.128225 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6515 19:25:44.134875 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6516 19:25:44.137995 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6517 19:25:44.141555 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6518 19:25:44.144603 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6519 19:25:44.151457 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6520 19:25:44.154454 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6521 19:25:44.154563 ==
6522 19:25:44.157730 Dram Type= 6, Freq= 0, CH_0, rank 1
6523 19:25:44.161367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6524 19:25:44.161446 ==
6525 19:25:44.164590 DQS Delay:
6526 19:25:44.164664 DQS0 = 35, DQS1 = 59
6527 19:25:44.167444 DQM Delay:
6528 19:25:44.167517 DQM0 = 6, DQM1 = 16
6529 19:25:44.167579 DQ Delay:
6530 19:25:44.170978 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6531 19:25:44.174098 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6532 19:25:44.177606 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6533 19:25:44.180612 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6534 19:25:44.180698
6535 19:25:44.180784
6536 19:25:44.180865 ==
6537 19:25:44.184493 Dram Type= 6, Freq= 0, CH_0, rank 1
6538 19:25:44.191038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6539 19:25:44.191153 ==
6540 19:25:44.191251
6541 19:25:44.191344
6542 19:25:44.191407 TX Vref Scan disable
6543 19:25:44.193911 == TX Byte 0 ==
6544 19:25:44.197199 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6545 19:25:44.200246 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6546 19:25:44.203818 == TX Byte 1 ==
6547 19:25:44.206805 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6548 19:25:44.210501 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6549 19:25:44.210606 ==
6550 19:25:44.213330 Dram Type= 6, Freq= 0, CH_0, rank 1
6551 19:25:44.220106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6552 19:25:44.220193 ==
6553 19:25:44.220279
6554 19:25:44.220360
6555 19:25:44.223402 TX Vref Scan disable
6556 19:25:44.223507 == TX Byte 0 ==
6557 19:25:44.226857 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6558 19:25:44.233257 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6559 19:25:44.233340 == TX Byte 1 ==
6560 19:25:44.236614 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6561 19:25:44.243186 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6562 19:25:44.243275
6563 19:25:44.243361 [DATLAT]
6564 19:25:44.243442 Freq=400, CH0 RK1
6565 19:25:44.243522
6566 19:25:44.246453 DATLAT Default: 0xe
6567 19:25:44.246538 0, 0xFFFF, sum = 0
6568 19:25:44.250082 1, 0xFFFF, sum = 0
6569 19:25:44.252748 2, 0xFFFF, sum = 0
6570 19:25:44.252835 3, 0xFFFF, sum = 0
6571 19:25:44.255986 4, 0xFFFF, sum = 0
6572 19:25:44.256073 5, 0xFFFF, sum = 0
6573 19:25:44.259297 6, 0xFFFF, sum = 0
6574 19:25:44.259408 7, 0xFFFF, sum = 0
6575 19:25:44.262732 8, 0xFFFF, sum = 0
6576 19:25:44.262819 9, 0xFFFF, sum = 0
6577 19:25:44.266420 10, 0xFFFF, sum = 0
6578 19:25:44.266507 11, 0xFFFF, sum = 0
6579 19:25:44.269459 12, 0xFFFF, sum = 0
6580 19:25:44.269545 13, 0x0, sum = 1
6581 19:25:44.273266 14, 0x0, sum = 2
6582 19:25:44.273367 15, 0x0, sum = 3
6583 19:25:44.275817 16, 0x0, sum = 4
6584 19:25:44.275931 best_step = 14
6585 19:25:44.276017
6586 19:25:44.276098 ==
6587 19:25:44.279339 Dram Type= 6, Freq= 0, CH_0, rank 1
6588 19:25:44.286153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6589 19:25:44.286267 ==
6590 19:25:44.286355 RX Vref Scan: 0
6591 19:25:44.286438
6592 19:25:44.288813 RX Vref 0 -> 0, step: 1
6593 19:25:44.288927
6594 19:25:44.292262 RX Delay -359 -> 252, step: 8
6595 19:25:44.299129 iDelay=209, Bit 0, Center -36 (-271 ~ 200) 472
6596 19:25:44.302381 iDelay=209, Bit 1, Center -32 (-271 ~ 208) 480
6597 19:25:44.305497 iDelay=209, Bit 2, Center -40 (-279 ~ 200) 480
6598 19:25:44.308808 iDelay=209, Bit 3, Center -40 (-279 ~ 200) 480
6599 19:25:44.315268 iDelay=209, Bit 4, Center -32 (-271 ~ 208) 480
6600 19:25:44.318647 iDelay=209, Bit 5, Center -44 (-279 ~ 192) 472
6601 19:25:44.322182 iDelay=209, Bit 6, Center -28 (-263 ~ 208) 472
6602 19:25:44.325170 iDelay=209, Bit 7, Center -28 (-263 ~ 208) 472
6603 19:25:44.331803 iDelay=209, Bit 8, Center -52 (-295 ~ 192) 488
6604 19:25:44.334959 iDelay=209, Bit 9, Center -60 (-303 ~ 184) 488
6605 19:25:44.338659 iDelay=209, Bit 10, Center -44 (-287 ~ 200) 488
6606 19:25:44.342199 iDelay=209, Bit 11, Center -52 (-295 ~ 192) 488
6607 19:25:44.348574 iDelay=209, Bit 12, Center -36 (-279 ~ 208) 488
6608 19:25:44.351715 iDelay=209, Bit 13, Center -40 (-287 ~ 208) 496
6609 19:25:44.355066 iDelay=209, Bit 14, Center -36 (-279 ~ 208) 488
6610 19:25:44.361637 iDelay=209, Bit 15, Center -36 (-279 ~ 208) 488
6611 19:25:44.361755 ==
6612 19:25:44.365159 Dram Type= 6, Freq= 0, CH_0, rank 1
6613 19:25:44.368471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6614 19:25:44.368582 ==
6615 19:25:44.368686 DQS Delay:
6616 19:25:44.372001 DQS0 = 44, DQS1 = 60
6617 19:25:44.372087 DQM Delay:
6618 19:25:44.374885 DQM0 = 9, DQM1 = 15
6619 19:25:44.374971 DQ Delay:
6620 19:25:44.377843 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =4
6621 19:25:44.381547 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6622 19:25:44.384893 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6623 19:25:44.387741 DQ12 =24, DQ13 =20, DQ14 =24, DQ15 =24
6624 19:25:44.387870
6625 19:25:44.387986
6626 19:25:44.394508 [DQSOSCAuto] RK1, (LSB)MR18= 0x837d, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
6627 19:25:44.397597 CH0 RK1: MR19=C0C, MR18=837D
6628 19:25:44.404636 CH0_RK1: MR19=0xC0C, MR18=0x837D, DQSOSC=393, MR23=63, INC=382, DEC=254
6629 19:25:44.407424 [RxdqsGatingPostProcess] freq 400
6630 19:25:44.414194 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6631 19:25:44.417314 best DQS0 dly(2T, 0.5T) = (0, 10)
6632 19:25:44.420872 best DQS1 dly(2T, 0.5T) = (0, 10)
6633 19:25:44.424250 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6634 19:25:44.427589 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6635 19:25:44.427663 best DQS0 dly(2T, 0.5T) = (0, 10)
6636 19:25:44.430539 best DQS1 dly(2T, 0.5T) = (0, 10)
6637 19:25:44.433938 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6638 19:25:44.437488 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6639 19:25:44.440435 Pre-setting of DQS Precalculation
6640 19:25:44.447028 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6641 19:25:44.447106 ==
6642 19:25:44.450483 Dram Type= 6, Freq= 0, CH_1, rank 0
6643 19:25:44.454022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6644 19:25:44.454138 ==
6645 19:25:44.460462 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6646 19:25:44.466890 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6647 19:25:44.470517 [CA 0] Center 36 (8~64) winsize 57
6648 19:25:44.470631 [CA 1] Center 36 (8~64) winsize 57
6649 19:25:44.473951 [CA 2] Center 36 (8~64) winsize 57
6650 19:25:44.476879 [CA 3] Center 36 (8~64) winsize 57
6651 19:25:44.480191 [CA 4] Center 36 (8~64) winsize 57
6652 19:25:44.483526 [CA 5] Center 36 (8~64) winsize 57
6653 19:25:44.483605
6654 19:25:44.486805 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6655 19:25:44.486927
6656 19:25:44.493265 [CATrainingPosCal] consider 1 rank data
6657 19:25:44.493393 u2DelayCellTimex100 = 270/100 ps
6658 19:25:44.499797 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6659 19:25:44.503060 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6660 19:25:44.506513 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6661 19:25:44.509580 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6662 19:25:44.513127 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6663 19:25:44.516060 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6664 19:25:44.516149
6665 19:25:44.519780 CA PerBit enable=1, Macro0, CA PI delay=36
6666 19:25:44.519897
6667 19:25:44.523144 [CBTSetCACLKResult] CA Dly = 36
6668 19:25:44.526399 CS Dly: 1 (0~32)
6669 19:25:44.526477 ==
6670 19:25:44.529268 Dram Type= 6, Freq= 0, CH_1, rank 1
6671 19:25:44.532687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6672 19:25:44.532769 ==
6673 19:25:44.539062 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6674 19:25:44.546027 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6675 19:25:44.549211 [CA 0] Center 36 (8~64) winsize 57
6676 19:25:44.549293 [CA 1] Center 36 (8~64) winsize 57
6677 19:25:44.552119 [CA 2] Center 36 (8~64) winsize 57
6678 19:25:44.556091 [CA 3] Center 36 (8~64) winsize 57
6679 19:25:44.559047 [CA 4] Center 36 (8~64) winsize 57
6680 19:25:44.562082 [CA 5] Center 36 (8~64) winsize 57
6681 19:25:44.562160
6682 19:25:44.565917 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6683 19:25:44.566006
6684 19:25:44.572509 [CATrainingPosCal] consider 2 rank data
6685 19:25:44.572590 u2DelayCellTimex100 = 270/100 ps
6686 19:25:44.578808 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6687 19:25:44.582184 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6688 19:25:44.585469 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6689 19:25:44.588300 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6690 19:25:44.591686 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6691 19:25:44.595203 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6692 19:25:44.595279
6693 19:25:44.598342 CA PerBit enable=1, Macro0, CA PI delay=36
6694 19:25:44.598418
6695 19:25:44.601661 [CBTSetCACLKResult] CA Dly = 36
6696 19:25:44.605275 CS Dly: 1 (0~32)
6697 19:25:44.605349
6698 19:25:44.608233 ----->DramcWriteLeveling(PI) begin...
6699 19:25:44.608307 ==
6700 19:25:44.611825 Dram Type= 6, Freq= 0, CH_1, rank 0
6701 19:25:44.615260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6702 19:25:44.615331 ==
6703 19:25:44.618071 Write leveling (Byte 0): 40 => 8
6704 19:25:44.621499 Write leveling (Byte 1): 40 => 8
6705 19:25:44.624637 DramcWriteLeveling(PI) end<-----
6706 19:25:44.624737
6707 19:25:44.624828 ==
6708 19:25:44.628479 Dram Type= 6, Freq= 0, CH_1, rank 0
6709 19:25:44.631623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6710 19:25:44.631755 ==
6711 19:25:44.634781 [Gating] SW mode calibration
6712 19:25:44.641503 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6713 19:25:44.647815 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6714 19:25:44.650892 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6715 19:25:44.654577 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6716 19:25:44.660914 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6717 19:25:44.663950 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6718 19:25:44.670819 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6719 19:25:44.674268 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6720 19:25:44.677521 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6721 19:25:44.680747 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6722 19:25:44.687719 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6723 19:25:44.690821 Total UI for P1: 0, mck2ui 16
6724 19:25:44.693761 best dqsien dly found for B0: ( 0, 14, 24)
6725 19:25:44.697178 Total UI for P1: 0, mck2ui 16
6726 19:25:44.700590 best dqsien dly found for B1: ( 0, 14, 24)
6727 19:25:44.703756 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6728 19:25:44.707211 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6729 19:25:44.707350
6730 19:25:44.710206 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6731 19:25:44.713859 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6732 19:25:44.716833 [Gating] SW calibration Done
6733 19:25:44.716942 ==
6734 19:25:44.720178 Dram Type= 6, Freq= 0, CH_1, rank 0
6735 19:25:44.723584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6736 19:25:44.726606 ==
6737 19:25:44.726690 RX Vref Scan: 0
6738 19:25:44.726780
6739 19:25:44.730292 RX Vref 0 -> 0, step: 1
6740 19:25:44.730368
6741 19:25:44.733453 RX Delay -410 -> 252, step: 16
6742 19:25:44.737317 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6743 19:25:44.739873 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6744 19:25:44.743424 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6745 19:25:44.750010 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6746 19:25:44.753225 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6747 19:25:44.756791 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6748 19:25:44.759770 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6749 19:25:44.766229 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6750 19:25:44.769841 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6751 19:25:44.772764 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6752 19:25:44.779660 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6753 19:25:44.782961 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6754 19:25:44.785835 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6755 19:25:44.789259 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6756 19:25:44.795642 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6757 19:25:44.798815 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6758 19:25:44.798896 ==
6759 19:25:44.802175 Dram Type= 6, Freq= 0, CH_1, rank 0
6760 19:25:44.805412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6761 19:25:44.805489 ==
6762 19:25:44.809200 DQS Delay:
6763 19:25:44.809278 DQS0 = 35, DQS1 = 51
6764 19:25:44.812516 DQM Delay:
6765 19:25:44.812597 DQM0 = 6, DQM1 = 13
6766 19:25:44.812677 DQ Delay:
6767 19:25:44.815398 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6768 19:25:44.819029 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6769 19:25:44.822074 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6770 19:25:44.825111 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6771 19:25:44.825187
6772 19:25:44.825273
6773 19:25:44.825350 ==
6774 19:25:44.828544 Dram Type= 6, Freq= 0, CH_1, rank 0
6775 19:25:44.835769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6776 19:25:44.835877 ==
6777 19:25:44.835969
6778 19:25:44.836054
6779 19:25:44.836151 TX Vref Scan disable
6780 19:25:44.838412 == TX Byte 0 ==
6781 19:25:44.842025 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6782 19:25:44.844963 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6783 19:25:44.848214 == TX Byte 1 ==
6784 19:25:44.851755 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6785 19:25:44.855235 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6786 19:25:44.858323 ==
6787 19:25:44.858405 Dram Type= 6, Freq= 0, CH_1, rank 0
6788 19:25:44.865138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6789 19:25:44.865220 ==
6790 19:25:44.865303
6791 19:25:44.865383
6792 19:25:44.868094 TX Vref Scan disable
6793 19:25:44.868171 == TX Byte 0 ==
6794 19:25:44.871089 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6795 19:25:44.878186 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6796 19:25:44.878275 == TX Byte 1 ==
6797 19:25:44.881387 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6798 19:25:44.887761 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6799 19:25:44.887874
6800 19:25:44.887978 [DATLAT]
6801 19:25:44.888060 Freq=400, CH1 RK0
6802 19:25:44.888136
6803 19:25:44.891126 DATLAT Default: 0xf
6804 19:25:44.891271 0, 0xFFFF, sum = 0
6805 19:25:44.894773 1, 0xFFFF, sum = 0
6806 19:25:44.898116 2, 0xFFFF, sum = 0
6807 19:25:44.898195 3, 0xFFFF, sum = 0
6808 19:25:44.901113 4, 0xFFFF, sum = 0
6809 19:25:44.901191 5, 0xFFFF, sum = 0
6810 19:25:44.904349 6, 0xFFFF, sum = 0
6811 19:25:44.904431 7, 0xFFFF, sum = 0
6812 19:25:44.907755 8, 0xFFFF, sum = 0
6813 19:25:44.907837 9, 0xFFFF, sum = 0
6814 19:25:44.910876 10, 0xFFFF, sum = 0
6815 19:25:44.910949 11, 0xFFFF, sum = 0
6816 19:25:44.914822 12, 0xFFFF, sum = 0
6817 19:25:44.914898 13, 0x0, sum = 1
6818 19:25:44.917640 14, 0x0, sum = 2
6819 19:25:44.917718 15, 0x0, sum = 3
6820 19:25:44.920897 16, 0x0, sum = 4
6821 19:25:44.920969 best_step = 14
6822 19:25:44.921030
6823 19:25:44.921087 ==
6824 19:25:44.924101 Dram Type= 6, Freq= 0, CH_1, rank 0
6825 19:25:44.930868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6826 19:25:44.930978 ==
6827 19:25:44.931074 RX Vref Scan: 1
6828 19:25:44.931144
6829 19:25:44.934198 RX Vref 0 -> 0, step: 1
6830 19:25:44.934295
6831 19:25:44.937322 RX Delay -343 -> 252, step: 8
6832 19:25:44.937417
6833 19:25:44.940526 Set Vref, RX VrefLevel [Byte0]: 49
6834 19:25:44.943852 [Byte1]: 51
6835 19:25:44.943968
6836 19:25:44.947374 Final RX Vref Byte 0 = 49 to rank0
6837 19:25:44.950544 Final RX Vref Byte 1 = 51 to rank0
6838 19:25:44.953643 Final RX Vref Byte 0 = 49 to rank1
6839 19:25:44.957210 Final RX Vref Byte 1 = 51 to rank1==
6840 19:25:44.960189 Dram Type= 6, Freq= 0, CH_1, rank 0
6841 19:25:44.963552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6842 19:25:44.967027 ==
6843 19:25:44.967100 DQS Delay:
6844 19:25:44.967168 DQS0 = 44, DQS1 = 52
6845 19:25:44.970388 DQM Delay:
6846 19:25:44.970489 DQM0 = 11, DQM1 = 10
6847 19:25:44.973812 DQ Delay:
6848 19:25:44.977059 DQ0 =20, DQ1 =4, DQ2 =0, DQ3 =12
6849 19:25:44.977165 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =4
6850 19:25:44.980119 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6851 19:25:44.983559 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =16
6852 19:25:44.983661
6853 19:25:44.983750
6854 19:25:44.993201 [DQSOSCAuto] RK0, (LSB)MR18= 0x638a, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 397 ps
6855 19:25:44.996641 CH1 RK0: MR19=C0C, MR18=638A
6856 19:25:45.003267 CH1_RK0: MR19=0xC0C, MR18=0x638A, DQSOSC=392, MR23=63, INC=384, DEC=256
6857 19:25:45.003346 ==
6858 19:25:45.006525 Dram Type= 6, Freq= 0, CH_1, rank 1
6859 19:25:45.009623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6860 19:25:45.009712 ==
6861 19:25:45.012757 [Gating] SW mode calibration
6862 19:25:45.019310 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6863 19:25:45.026268 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6864 19:25:45.029301 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6865 19:25:45.032693 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6866 19:25:45.039417 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6867 19:25:45.042656 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6868 19:25:45.045540 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6869 19:25:45.052027 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6870 19:25:45.055348 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6871 19:25:45.059238 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6872 19:25:45.065371 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6873 19:25:45.065451 Total UI for P1: 0, mck2ui 16
6874 19:25:45.072493 best dqsien dly found for B0: ( 0, 14, 24)
6875 19:25:45.072610 Total UI for P1: 0, mck2ui 16
6876 19:25:45.078766 best dqsien dly found for B1: ( 0, 14, 24)
6877 19:25:45.081659 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6878 19:25:45.085167 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6879 19:25:45.085288
6880 19:25:45.088095 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6881 19:25:45.091510 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6882 19:25:45.094903 [Gating] SW calibration Done
6883 19:25:45.094976 ==
6884 19:25:45.098209 Dram Type= 6, Freq= 0, CH_1, rank 1
6885 19:25:45.101590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6886 19:25:45.101680 ==
6887 19:25:45.104716 RX Vref Scan: 0
6888 19:25:45.104787
6889 19:25:45.108279 RX Vref 0 -> 0, step: 1
6890 19:25:45.108361
6891 19:25:45.108426 RX Delay -410 -> 252, step: 16
6892 19:25:45.115283 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6893 19:25:45.117905 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6894 19:25:45.121230 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6895 19:25:45.127878 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6896 19:25:45.130950 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6897 19:25:45.134697 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6898 19:25:45.137843 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6899 19:25:45.144523 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6900 19:25:45.147422 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6901 19:25:45.150915 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6902 19:25:45.153914 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6903 19:25:45.160638 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6904 19:25:45.164326 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6905 19:25:45.167056 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6906 19:25:45.174336 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6907 19:25:45.177512 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6908 19:25:45.177587 ==
6909 19:25:45.180340 Dram Type= 6, Freq= 0, CH_1, rank 1
6910 19:25:45.183800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6911 19:25:45.183870 ==
6912 19:25:45.187137 DQS Delay:
6913 19:25:45.187214 DQS0 = 43, DQS1 = 51
6914 19:25:45.187283 DQM Delay:
6915 19:25:45.190466 DQM0 = 9, DQM1 = 14
6916 19:25:45.190551 DQ Delay:
6917 19:25:45.193304 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6918 19:25:45.196684 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6919 19:25:45.200126 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6920 19:25:45.203479 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6921 19:25:45.203551
6922 19:25:45.203618
6923 19:25:45.203676 ==
6924 19:25:45.206795 Dram Type= 6, Freq= 0, CH_1, rank 1
6925 19:25:45.210371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6926 19:25:45.213234 ==
6927 19:25:45.213309
6928 19:25:45.213376
6929 19:25:45.213435 TX Vref Scan disable
6930 19:25:45.216248 == TX Byte 0 ==
6931 19:25:45.219871 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6932 19:25:45.223074 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6933 19:25:45.226139 == TX Byte 1 ==
6934 19:25:45.229296 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6935 19:25:45.232611 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6936 19:25:45.232692 ==
6937 19:25:45.235822 Dram Type= 6, Freq= 0, CH_1, rank 1
6938 19:25:45.242708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6939 19:25:45.242795 ==
6940 19:25:45.242863
6941 19:25:45.242925
6942 19:25:45.243002 TX Vref Scan disable
6943 19:25:45.245861 == TX Byte 0 ==
6944 19:25:45.249138 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6945 19:25:45.252690 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6946 19:25:45.256165 == TX Byte 1 ==
6947 19:25:45.259066 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6948 19:25:45.262646 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6949 19:25:45.262716
6950 19:25:45.265795 [DATLAT]
6951 19:25:45.265864 Freq=400, CH1 RK1
6952 19:25:45.265924
6953 19:25:45.269185 DATLAT Default: 0xe
6954 19:25:45.269251 0, 0xFFFF, sum = 0
6955 19:25:45.272154 1, 0xFFFF, sum = 0
6956 19:25:45.272221 2, 0xFFFF, sum = 0
6957 19:25:45.275860 3, 0xFFFF, sum = 0
6958 19:25:45.275942 4, 0xFFFF, sum = 0
6959 19:25:45.279200 5, 0xFFFF, sum = 0
6960 19:25:45.279269 6, 0xFFFF, sum = 0
6961 19:25:45.282025 7, 0xFFFF, sum = 0
6962 19:25:45.285403 8, 0xFFFF, sum = 0
6963 19:25:45.285478 9, 0xFFFF, sum = 0
6964 19:25:45.288563 10, 0xFFFF, sum = 0
6965 19:25:45.288646 11, 0xFFFF, sum = 0
6966 19:25:45.292289 12, 0xFFFF, sum = 0
6967 19:25:45.292372 13, 0x0, sum = 1
6968 19:25:45.295294 14, 0x0, sum = 2
6969 19:25:45.295370 15, 0x0, sum = 3
6970 19:25:45.298961 16, 0x0, sum = 4
6971 19:25:45.299042 best_step = 14
6972 19:25:45.299105
6973 19:25:45.299172 ==
6974 19:25:45.302199 Dram Type= 6, Freq= 0, CH_1, rank 1
6975 19:25:45.305585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6976 19:25:45.305670 ==
6977 19:25:45.308201 RX Vref Scan: 0
6978 19:25:45.308286
6979 19:25:45.311496 RX Vref 0 -> 0, step: 1
6980 19:25:45.311601
6981 19:25:45.314789 RX Delay -343 -> 252, step: 8
6982 19:25:45.318248 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6983 19:25:45.325228 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6984 19:25:45.328113 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6985 19:25:45.331340 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6986 19:25:45.338087 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6987 19:25:45.341597 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6988 19:25:45.344829 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6989 19:25:45.347893 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6990 19:25:45.354548 iDelay=217, Bit 8, Center -56 (-295 ~ 184) 480
6991 19:25:45.357628 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6992 19:25:45.361311 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6993 19:25:45.364658 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6994 19:25:45.371061 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6995 19:25:45.374853 iDelay=217, Bit 13, Center -32 (-271 ~ 208) 480
6996 19:25:45.377482 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6997 19:25:45.381089 iDelay=217, Bit 15, Center -32 (-279 ~ 216) 496
6998 19:25:45.384260 ==
6999 19:25:45.387543 Dram Type= 6, Freq= 0, CH_1, rank 1
7000 19:25:45.390772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7001 19:25:45.390876 ==
7002 19:25:45.390944 DQS Delay:
7003 19:25:45.394369 DQS0 = 48, DQS1 = 56
7004 19:25:45.394445 DQM Delay:
7005 19:25:45.397249 DQM0 = 11, DQM1 = 14
7006 19:25:45.397357 DQ Delay:
7007 19:25:45.400655 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =12
7008 19:25:45.403686 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
7009 19:25:45.407020 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
7010 19:25:45.410224 DQ12 =24, DQ13 =24, DQ14 =20, DQ15 =24
7011 19:25:45.410307
7012 19:25:45.410371
7013 19:25:45.416931 [DQSOSCAuto] RK1, (LSB)MR18= 0x74aa, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
7014 19:25:45.420209 CH1 RK1: MR19=C0C, MR18=74AA
7015 19:25:45.427215 CH1_RK1: MR19=0xC0C, MR18=0x74AA, DQSOSC=388, MR23=63, INC=392, DEC=261
7016 19:25:45.429954 [RxdqsGatingPostProcess] freq 400
7017 19:25:45.437493 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7018 19:25:45.440337 best DQS0 dly(2T, 0.5T) = (0, 10)
7019 19:25:45.440427 best DQS1 dly(2T, 0.5T) = (0, 10)
7020 19:25:45.443450 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7021 19:25:45.446608 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7022 19:25:45.449944 best DQS0 dly(2T, 0.5T) = (0, 10)
7023 19:25:45.453268 best DQS1 dly(2T, 0.5T) = (0, 10)
7024 19:25:45.456689 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7025 19:25:45.459641 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7026 19:25:45.463222 Pre-setting of DQS Precalculation
7027 19:25:45.469782 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7028 19:25:45.476327 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7029 19:25:45.483217 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7030 19:25:45.483303
7031 19:25:45.483368
7032 19:25:45.485922 [Calibration Summary] 800 Mbps
7033 19:25:45.486020 CH 0, Rank 0
7034 19:25:45.489550 SW Impedance : PASS
7035 19:25:45.493353 DUTY Scan : NO K
7036 19:25:45.493457 ZQ Calibration : PASS
7037 19:25:45.496036 Jitter Meter : NO K
7038 19:25:45.499557 CBT Training : PASS
7039 19:25:45.499666 Write leveling : PASS
7040 19:25:45.502773 RX DQS gating : PASS
7041 19:25:45.505618 RX DQ/DQS(RDDQC) : PASS
7042 19:25:45.505693 TX DQ/DQS : PASS
7043 19:25:45.509237 RX DATLAT : PASS
7044 19:25:45.512130 RX DQ/DQS(Engine): PASS
7045 19:25:45.512233 TX OE : NO K
7046 19:25:45.515419 All Pass.
7047 19:25:45.515496
7048 19:25:45.515560 CH 0, Rank 1
7049 19:25:45.518921 SW Impedance : PASS
7050 19:25:45.519017 DUTY Scan : NO K
7051 19:25:45.522302 ZQ Calibration : PASS
7052 19:25:45.525700 Jitter Meter : NO K
7053 19:25:45.525784 CBT Training : PASS
7054 19:25:45.528844 Write leveling : NO K
7055 19:25:45.532398 RX DQS gating : PASS
7056 19:25:45.532479 RX DQ/DQS(RDDQC) : PASS
7057 19:25:45.535256 TX DQ/DQS : PASS
7058 19:25:45.539112 RX DATLAT : PASS
7059 19:25:45.539202 RX DQ/DQS(Engine): PASS
7060 19:25:45.541640 TX OE : NO K
7061 19:25:45.541714 All Pass.
7062 19:25:45.541779
7063 19:25:45.545484 CH 1, Rank 0
7064 19:25:45.545592 SW Impedance : PASS
7065 19:25:45.548728 DUTY Scan : NO K
7066 19:25:45.551964 ZQ Calibration : PASS
7067 19:25:45.552070 Jitter Meter : NO K
7068 19:25:45.555616 CBT Training : PASS
7069 19:25:45.558213 Write leveling : PASS
7070 19:25:45.558318 RX DQS gating : PASS
7071 19:25:45.561505 RX DQ/DQS(RDDQC) : PASS
7072 19:25:45.561615 TX DQ/DQS : PASS
7073 19:25:45.564952 RX DATLAT : PASS
7074 19:25:45.567985 RX DQ/DQS(Engine): PASS
7075 19:25:45.568067 TX OE : NO K
7076 19:25:45.571451 All Pass.
7077 19:25:45.571559
7078 19:25:45.571652 CH 1, Rank 1
7079 19:25:45.574806 SW Impedance : PASS
7080 19:25:45.574910 DUTY Scan : NO K
7081 19:25:45.577933 ZQ Calibration : PASS
7082 19:25:45.581402 Jitter Meter : NO K
7083 19:25:45.581506 CBT Training : PASS
7084 19:25:45.584872 Write leveling : NO K
7085 19:25:45.587709 RX DQS gating : PASS
7086 19:25:45.587819 RX DQ/DQS(RDDQC) : PASS
7087 19:25:45.591328 TX DQ/DQS : PASS
7088 19:25:45.594384 RX DATLAT : PASS
7089 19:25:45.594495 RX DQ/DQS(Engine): PASS
7090 19:25:45.597880 TX OE : NO K
7091 19:25:45.597987 All Pass.
7092 19:25:45.598084
7093 19:25:45.601213 DramC Write-DBI off
7094 19:25:45.604667 PER_BANK_REFRESH: Hybrid Mode
7095 19:25:45.604744 TX_TRACKING: ON
7096 19:25:45.614604 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7097 19:25:45.617453 [FAST_K] Save calibration result to emmc
7098 19:25:45.620967 dramc_set_vcore_voltage set vcore to 725000
7099 19:25:45.624465 Read voltage for 1600, 0
7100 19:25:45.624546 Vio18 = 0
7101 19:25:45.624611 Vcore = 725000
7102 19:25:45.627474 Vdram = 0
7103 19:25:45.627583 Vddq = 0
7104 19:25:45.627678 Vmddr = 0
7105 19:25:45.633881 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7106 19:25:45.637355 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7107 19:25:45.640594 MEM_TYPE=3, freq_sel=13
7108 19:25:45.644071 sv_algorithm_assistance_LP4_3733
7109 19:25:45.647246 ============ PULL DRAM RESETB DOWN ============
7110 19:25:45.654037 ========== PULL DRAM RESETB DOWN end =========
7111 19:25:45.657078 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7112 19:25:45.660175 ===================================
7113 19:25:45.663802 LPDDR4 DRAM CONFIGURATION
7114 19:25:45.666924 ===================================
7115 19:25:45.667028 EX_ROW_EN[0] = 0x0
7116 19:25:45.669935 EX_ROW_EN[1] = 0x0
7117 19:25:45.670032 LP4Y_EN = 0x0
7118 19:25:45.673191 WORK_FSP = 0x1
7119 19:25:45.676833 WL = 0x5
7120 19:25:45.676938 RL = 0x5
7121 19:25:45.679946 BL = 0x2
7122 19:25:45.680024 RPST = 0x0
7123 19:25:45.683256 RD_PRE = 0x0
7124 19:25:45.683357 WR_PRE = 0x1
7125 19:25:45.686643 WR_PST = 0x1
7126 19:25:45.686739 DBI_WR = 0x0
7127 19:25:45.689676 DBI_RD = 0x0
7128 19:25:45.689778 OTF = 0x1
7129 19:25:45.692871 ===================================
7130 19:25:45.696831 ===================================
7131 19:25:45.699815 ANA top config
7132 19:25:45.703201 ===================================
7133 19:25:45.703312 DLL_ASYNC_EN = 0
7134 19:25:45.706349 ALL_SLAVE_EN = 0
7135 19:25:45.710008 NEW_RANK_MODE = 1
7136 19:25:45.713765 DLL_IDLE_MODE = 1
7137 19:25:45.716258 LP45_APHY_COMB_EN = 1
7138 19:25:45.716363 TX_ODT_DIS = 0
7139 19:25:45.719418 NEW_8X_MODE = 1
7140 19:25:45.722672 ===================================
7141 19:25:45.726064 ===================================
7142 19:25:45.729890 data_rate = 3200
7143 19:25:45.732640 CKR = 1
7144 19:25:45.736118 DQ_P2S_RATIO = 8
7145 19:25:45.739025 ===================================
7146 19:25:45.742541 CA_P2S_RATIO = 8
7147 19:25:45.742615 DQ_CA_OPEN = 0
7148 19:25:45.746234 DQ_SEMI_OPEN = 0
7149 19:25:45.749195 CA_SEMI_OPEN = 0
7150 19:25:45.752791 CA_FULL_RATE = 0
7151 19:25:45.755554 DQ_CKDIV4_EN = 0
7152 19:25:45.759091 CA_CKDIV4_EN = 0
7153 19:25:45.759162 CA_PREDIV_EN = 0
7154 19:25:45.762633 PH8_DLY = 12
7155 19:25:45.765499 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7156 19:25:45.769126 DQ_AAMCK_DIV = 4
7157 19:25:45.772152 CA_AAMCK_DIV = 4
7158 19:25:45.775619 CA_ADMCK_DIV = 4
7159 19:25:45.775717 DQ_TRACK_CA_EN = 0
7160 19:25:45.778809 CA_PICK = 1600
7161 19:25:45.783133 CA_MCKIO = 1600
7162 19:25:45.785366 MCKIO_SEMI = 0
7163 19:25:45.788466 PLL_FREQ = 3068
7164 19:25:45.791937 DQ_UI_PI_RATIO = 32
7165 19:25:45.795176 CA_UI_PI_RATIO = 0
7166 19:25:45.798570 ===================================
7167 19:25:45.801543 ===================================
7168 19:25:45.805188 memory_type:LPDDR4
7169 19:25:45.805297 GP_NUM : 10
7170 19:25:45.808506 SRAM_EN : 1
7171 19:25:45.808608 MD32_EN : 0
7172 19:25:45.811383 ===================================
7173 19:25:45.814948 [ANA_INIT] >>>>>>>>>>>>>>
7174 19:25:45.818627 <<<<<< [CONFIGURE PHASE]: ANA_TX
7175 19:25:45.821935 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7176 19:25:45.824962 ===================================
7177 19:25:45.828372 data_rate = 3200,PCW = 0X7600
7178 19:25:45.831556 ===================================
7179 19:25:45.834944 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7180 19:25:45.838045 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7181 19:25:45.844514 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7182 19:25:45.851418 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7183 19:25:45.854509 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7184 19:25:45.857883 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7185 19:25:45.857989 [ANA_INIT] flow start
7186 19:25:45.861083 [ANA_INIT] PLL >>>>>>>>
7187 19:25:45.864663 [ANA_INIT] PLL <<<<<<<<
7188 19:25:45.864735 [ANA_INIT] MIDPI >>>>>>>>
7189 19:25:45.867934 [ANA_INIT] MIDPI <<<<<<<<
7190 19:25:45.871483 [ANA_INIT] DLL >>>>>>>>
7191 19:25:45.871580 [ANA_INIT] DLL <<<<<<<<
7192 19:25:45.874405 [ANA_INIT] flow end
7193 19:25:45.877847 ============ LP4 DIFF to SE enter ============
7194 19:25:45.883927 ============ LP4 DIFF to SE exit ============
7195 19:25:45.884007 [ANA_INIT] <<<<<<<<<<<<<
7196 19:25:45.887331 [Flow] Enable top DCM control >>>>>
7197 19:25:45.890694 [Flow] Enable top DCM control <<<<<
7198 19:25:45.894326 Enable DLL master slave shuffle
7199 19:25:45.901100 ==============================================================
7200 19:25:45.901186 Gating Mode config
7201 19:25:45.907725 ==============================================================
7202 19:25:45.910807 Config description:
7203 19:25:45.920940 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7204 19:25:45.927173 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7205 19:25:45.930215 SELPH_MODE 0: By rank 1: By Phase
7206 19:25:45.936744 ==============================================================
7207 19:25:45.940576 GAT_TRACK_EN = 1
7208 19:25:45.943435 RX_GATING_MODE = 2
7209 19:25:45.943542 RX_GATING_TRACK_MODE = 2
7210 19:25:45.946819 SELPH_MODE = 1
7211 19:25:45.949880 PICG_EARLY_EN = 1
7212 19:25:45.953998 VALID_LAT_VALUE = 1
7213 19:25:45.959815 ==============================================================
7214 19:25:45.963406 Enter into Gating configuration >>>>
7215 19:25:45.966291 Exit from Gating configuration <<<<
7216 19:25:45.969938 Enter into DVFS_PRE_config >>>>>
7217 19:25:45.979528 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7218 19:25:45.982650 Exit from DVFS_PRE_config <<<<<
7219 19:25:45.986179 Enter into PICG configuration >>>>
7220 19:25:45.989496 Exit from PICG configuration <<<<
7221 19:25:45.992683 [RX_INPUT] configuration >>>>>
7222 19:25:45.995862 [RX_INPUT] configuration <<<<<
7223 19:25:45.999107 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7224 19:25:46.005979 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7225 19:25:46.012368 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7226 19:25:46.019059 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7227 19:25:46.025590 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7228 19:25:46.032769 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7229 19:25:46.035373 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7230 19:25:46.038777 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7231 19:25:46.042214 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7232 19:25:46.048525 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7233 19:25:46.052165 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7234 19:25:46.055158 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7235 19:25:46.058528 ===================================
7236 19:25:46.062020 LPDDR4 DRAM CONFIGURATION
7237 19:25:46.064906 ===================================
7238 19:25:46.064996 EX_ROW_EN[0] = 0x0
7239 19:25:46.068285 EX_ROW_EN[1] = 0x0
7240 19:25:46.071611 LP4Y_EN = 0x0
7241 19:25:46.071712 WORK_FSP = 0x1
7242 19:25:46.075665 WL = 0x5
7243 19:25:46.075747 RL = 0x5
7244 19:25:46.078027 BL = 0x2
7245 19:25:46.078109 RPST = 0x0
7246 19:25:46.081460 RD_PRE = 0x0
7247 19:25:46.081554 WR_PRE = 0x1
7248 19:25:46.084606 WR_PST = 0x1
7249 19:25:46.084687 DBI_WR = 0x0
7250 19:25:46.088100 DBI_RD = 0x0
7251 19:25:46.088198 OTF = 0x1
7252 19:25:46.091309 ===================================
7253 19:25:46.094687 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7254 19:25:46.101473 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7255 19:25:46.104718 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7256 19:25:46.107676 ===================================
7257 19:25:46.111330 LPDDR4 DRAM CONFIGURATION
7258 19:25:46.114196 ===================================
7259 19:25:46.114296 EX_ROW_EN[0] = 0x10
7260 19:25:46.117960 EX_ROW_EN[1] = 0x0
7261 19:25:46.120908 LP4Y_EN = 0x0
7262 19:25:46.120990 WORK_FSP = 0x1
7263 19:25:46.124348 WL = 0x5
7264 19:25:46.124430 RL = 0x5
7265 19:25:46.127781 BL = 0x2
7266 19:25:46.127863 RPST = 0x0
7267 19:25:46.130906 RD_PRE = 0x0
7268 19:25:46.131003 WR_PRE = 0x1
7269 19:25:46.134551 WR_PST = 0x1
7270 19:25:46.134636 DBI_WR = 0x0
7271 19:25:46.137382 DBI_RD = 0x0
7272 19:25:46.137480 OTF = 0x1
7273 19:25:46.140559 ===================================
7274 19:25:46.147176 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7275 19:25:46.147269 ==
7276 19:25:46.150570 Dram Type= 6, Freq= 0, CH_0, rank 0
7277 19:25:46.157563 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7278 19:25:46.157660 ==
7279 19:25:46.157726 [Duty_Offset_Calibration]
7280 19:25:46.160901 B0:2 B1:0 CA:4
7281 19:25:46.160986
7282 19:25:46.163706 [DutyScan_Calibration_Flow] k_type=0
7283 19:25:46.172429
7284 19:25:46.172525 ==CLK 0==
7285 19:25:46.175710 Final CLK duty delay cell = -4
7286 19:25:46.178864 [-4] MAX Duty = 5000%(X100), DQS PI = 14
7287 19:25:46.182273 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7288 19:25:46.185166 [-4] AVG Duty = 4922%(X100)
7289 19:25:46.185252
7290 19:25:46.188788 CH0 CLK Duty spec in!! Max-Min= 156%
7291 19:25:46.191902 [DutyScan_Calibration_Flow] ====Done====
7292 19:25:46.191989
7293 19:25:46.195345 [DutyScan_Calibration_Flow] k_type=1
7294 19:25:46.212020
7295 19:25:46.212140 ==DQS 0 ==
7296 19:25:46.215354 Final DQS duty delay cell = -4
7297 19:25:46.218190 [-4] MAX Duty = 4907%(X100), DQS PI = 46
7298 19:25:46.221456 [-4] MIN Duty = 4782%(X100), DQS PI = 4
7299 19:25:46.225264 [-4] AVG Duty = 4844%(X100)
7300 19:25:46.225351
7301 19:25:46.225418 ==DQS 1 ==
7302 19:25:46.227955 Final DQS duty delay cell = 0
7303 19:25:46.231315 [0] MAX Duty = 5156%(X100), DQS PI = 0
7304 19:25:46.234786 [0] MIN Duty = 4938%(X100), DQS PI = 58
7305 19:25:46.238010 [0] AVG Duty = 5047%(X100)
7306 19:25:46.238092
7307 19:25:46.241897 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7308 19:25:46.242001
7309 19:25:46.244417 CH0 DQS 1 Duty spec in!! Max-Min= 218%
7310 19:25:46.248177 [DutyScan_Calibration_Flow] ====Done====
7311 19:25:46.248254
7312 19:25:46.250924 [DutyScan_Calibration_Flow] k_type=3
7313 19:25:46.268943
7314 19:25:46.269072 ==DQM 0 ==
7315 19:25:46.272572 Final DQM duty delay cell = 0
7316 19:25:46.275917 [0] MAX Duty = 5124%(X100), DQS PI = 22
7317 19:25:46.278757 [0] MIN Duty = 4875%(X100), DQS PI = 54
7318 19:25:46.282371 [0] AVG Duty = 4999%(X100)
7319 19:25:46.282454
7320 19:25:46.282518 ==DQM 1 ==
7321 19:25:46.286009 Final DQM duty delay cell = 0
7322 19:25:46.288584 [0] MAX Duty = 4969%(X100), DQS PI = 0
7323 19:25:46.291915 [0] MIN Duty = 4813%(X100), DQS PI = 34
7324 19:25:46.295359 [0] AVG Duty = 4891%(X100)
7325 19:25:46.295447
7326 19:25:46.298972 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7327 19:25:46.299056
7328 19:25:46.302235 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7329 19:25:46.305944 [DutyScan_Calibration_Flow] ====Done====
7330 19:25:46.306029
7331 19:25:46.308588 [DutyScan_Calibration_Flow] k_type=2
7332 19:25:46.326311
7333 19:25:46.326451 ==DQ 0 ==
7334 19:25:46.329472 Final DQ duty delay cell = 0
7335 19:25:46.332681 [0] MAX Duty = 5124%(X100), DQS PI = 20
7336 19:25:46.336291 [0] MIN Duty = 4938%(X100), DQS PI = 12
7337 19:25:46.336384 [0] AVG Duty = 5031%(X100)
7338 19:25:46.339494
7339 19:25:46.339577 ==DQ 1 ==
7340 19:25:46.342702 Final DQ duty delay cell = 0
7341 19:25:46.346084 [0] MAX Duty = 5187%(X100), DQS PI = 2
7342 19:25:46.349674 [0] MIN Duty = 4907%(X100), DQS PI = 34
7343 19:25:46.349764 [0] AVG Duty = 5047%(X100)
7344 19:25:46.352216
7345 19:25:46.355925 CH0 DQ 0 Duty spec in!! Max-Min= 186%
7346 19:25:46.356007
7347 19:25:46.358999 CH0 DQ 1 Duty spec in!! Max-Min= 280%
7348 19:25:46.362185 [DutyScan_Calibration_Flow] ====Done====
7349 19:25:46.362268 ==
7350 19:25:46.365785 Dram Type= 6, Freq= 0, CH_1, rank 0
7351 19:25:46.368647 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7352 19:25:46.368733 ==
7353 19:25:46.372099 [Duty_Offset_Calibration]
7354 19:25:46.372184 B0:0 B1:-1 CA:3
7355 19:25:46.372248
7356 19:25:46.376066 [DutyScan_Calibration_Flow] k_type=0
7357 19:25:46.385729
7358 19:25:46.385904 ==CLK 0==
7359 19:25:46.389103 Final CLK duty delay cell = -4
7360 19:25:46.391891 [-4] MAX Duty = 5000%(X100), DQS PI = 6
7361 19:25:46.395528 [-4] MIN Duty = 4875%(X100), DQS PI = 12
7362 19:25:46.399270 [-4] AVG Duty = 4937%(X100)
7363 19:25:46.399358
7364 19:25:46.402264 CH1 CLK Duty spec in!! Max-Min= 125%
7365 19:25:46.405265 [DutyScan_Calibration_Flow] ====Done====
7366 19:25:46.405387
7367 19:25:46.408436 [DutyScan_Calibration_Flow] k_type=1
7368 19:25:46.424812
7369 19:25:46.424957 ==DQS 0 ==
7370 19:25:46.428640 Final DQS duty delay cell = 0
7371 19:25:46.431354 [0] MAX Duty = 5218%(X100), DQS PI = 28
7372 19:25:46.434727 [0] MIN Duty = 4907%(X100), DQS PI = 58
7373 19:25:46.438134 [0] AVG Duty = 5062%(X100)
7374 19:25:46.438221
7375 19:25:46.438286 ==DQS 1 ==
7376 19:25:46.441125 Final DQS duty delay cell = -4
7377 19:25:46.444758 [-4] MAX Duty = 5000%(X100), DQS PI = 30
7378 19:25:46.448072 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7379 19:25:46.451657 [-4] AVG Duty = 4906%(X100)
7380 19:25:46.451776
7381 19:25:46.454681 CH1 DQS 0 Duty spec in!! Max-Min= 311%
7382 19:25:46.454780
7383 19:25:46.457719 CH1 DQS 1 Duty spec in!! Max-Min= 187%
7384 19:25:46.461089 [DutyScan_Calibration_Flow] ====Done====
7385 19:25:46.461163
7386 19:25:46.464675 [DutyScan_Calibration_Flow] k_type=3
7387 19:25:46.481867
7388 19:25:46.482004 ==DQM 0 ==
7389 19:25:46.485155 Final DQM duty delay cell = 0
7390 19:25:46.488449 [0] MAX Duty = 5031%(X100), DQS PI = 30
7391 19:25:46.491852 [0] MIN Duty = 4750%(X100), DQS PI = 40
7392 19:25:46.495446 [0] AVG Duty = 4890%(X100)
7393 19:25:46.495567
7394 19:25:46.495689 ==DQM 1 ==
7395 19:25:46.498359 Final DQM duty delay cell = 0
7396 19:25:46.502220 [0] MAX Duty = 4969%(X100), DQS PI = 28
7397 19:25:46.504864 [0] MIN Duty = 4782%(X100), DQS PI = 62
7398 19:25:46.508675 [0] AVG Duty = 4875%(X100)
7399 19:25:46.508774
7400 19:25:46.511773 CH1 DQM 0 Duty spec in!! Max-Min= 281%
7401 19:25:46.511879
7402 19:25:46.515211 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7403 19:25:46.518645 [DutyScan_Calibration_Flow] ====Done====
7404 19:25:46.518749
7405 19:25:46.521394 [DutyScan_Calibration_Flow] k_type=2
7406 19:25:46.537871
7407 19:25:46.538064 ==DQ 0 ==
7408 19:25:46.541371 Final DQ duty delay cell = -4
7409 19:25:46.544799 [-4] MAX Duty = 4969%(X100), DQS PI = 32
7410 19:25:46.547816 [-4] MIN Duty = 4813%(X100), DQS PI = 38
7411 19:25:46.551286 [-4] AVG Duty = 4891%(X100)
7412 19:25:46.551375
7413 19:25:46.551440 ==DQ 1 ==
7414 19:25:46.554556 Final DQ duty delay cell = 0
7415 19:25:46.557907 [0] MAX Duty = 5031%(X100), DQS PI = 46
7416 19:25:46.561143 [0] MIN Duty = 4844%(X100), DQS PI = 60
7417 19:25:46.564426 [0] AVG Duty = 4937%(X100)
7418 19:25:46.564513
7419 19:25:46.568138 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7420 19:25:46.568223
7421 19:25:46.570923 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7422 19:25:46.574015 [DutyScan_Calibration_Flow] ====Done====
7423 19:25:46.577696 nWR fixed to 30
7424 19:25:46.580892 [ModeRegInit_LP4] CH0 RK0
7425 19:25:46.580977 [ModeRegInit_LP4] CH0 RK1
7426 19:25:46.583998 [ModeRegInit_LP4] CH1 RK0
7427 19:25:46.587326 [ModeRegInit_LP4] CH1 RK1
7428 19:25:46.587413 match AC timing 5
7429 19:25:46.593685 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7430 19:25:46.597330 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7431 19:25:46.600739 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7432 19:25:46.607041 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7433 19:25:46.610125 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7434 19:25:46.613652 [MiockJmeterHQA]
7435 19:25:46.613744
7436 19:25:46.616976 [DramcMiockJmeter] u1RxGatingPI = 0
7437 19:25:46.617063 0 : 4258, 4029
7438 19:25:46.617131 4 : 4252, 4027
7439 19:25:46.620462 8 : 4252, 4027
7440 19:25:46.620548 12 : 4253, 4027
7441 19:25:46.623521 16 : 4363, 4138
7442 19:25:46.623606 20 : 4253, 4026
7443 19:25:46.626714 24 : 4252, 4027
7444 19:25:46.626803 28 : 4365, 4140
7445 19:25:46.630601 32 : 4252, 4027
7446 19:25:46.630687 36 : 4254, 4029
7447 19:25:46.630754 40 : 4253, 4026
7448 19:25:46.633332 44 : 4363, 4138
7449 19:25:46.633417 48 : 4253, 4026
7450 19:25:46.636694 52 : 4254, 4029
7451 19:25:46.636779 56 : 4254, 4029
7452 19:25:46.639859 60 : 4252, 4027
7453 19:25:46.639956 64 : 4252, 4027
7454 19:25:46.643234 68 : 4253, 4026
7455 19:25:46.643318 72 : 4250, 4026
7456 19:25:46.643383 76 : 4249, 4027
7457 19:25:46.646708 80 : 4363, 4140
7458 19:25:46.646794 84 : 4250, 4027
7459 19:25:46.650023 88 : 4252, 4029
7460 19:25:46.650107 92 : 4250, 4026
7461 19:25:46.653045 96 : 4361, 2889
7462 19:25:46.653129 100 : 4250, 0
7463 19:25:46.653195 104 : 4249, 0
7464 19:25:46.656692 108 : 4252, 0
7465 19:25:46.656781 112 : 4252, 0
7466 19:25:46.659745 116 : 4255, 0
7467 19:25:46.659830 120 : 4361, 0
7468 19:25:46.659938 124 : 4360, 0
7469 19:25:46.662702 128 : 4363, 0
7470 19:25:46.662789 132 : 4250, 0
7471 19:25:46.666122 136 : 4250, 0
7472 19:25:46.666206 140 : 4249, 0
7473 19:25:46.666272 144 : 4250, 0
7474 19:25:46.669365 148 : 4250, 0
7475 19:25:46.669453 152 : 4249, 0
7476 19:25:46.672512 156 : 4252, 0
7477 19:25:46.672596 160 : 4250, 0
7478 19:25:46.672662 164 : 4360, 0
7479 19:25:46.675912 168 : 4250, 0
7480 19:25:46.676010 172 : 4361, 0
7481 19:25:46.679192 176 : 4360, 0
7482 19:25:46.679307 180 : 4248, 0
7483 19:25:46.679379 184 : 4250, 0
7484 19:25:46.682719 188 : 4250, 0
7485 19:25:46.682803 192 : 4250, 0
7486 19:25:46.685787 196 : 4361, 0
7487 19:25:46.685872 200 : 4250, 0
7488 19:25:46.685937 204 : 4250, 0
7489 19:25:46.689047 208 : 4249, 0
7490 19:25:46.689136 212 : 4250, 0
7491 19:25:46.689227 216 : 4250, 0
7492 19:25:46.692503 220 : 4250, 428
7493 19:25:46.692587 224 : 4250, 3903
7494 19:25:46.695828 228 : 4252, 4029
7495 19:25:46.695981 232 : 4360, 4138
7496 19:25:46.698748 236 : 4360, 4138
7497 19:25:46.698853 240 : 4363, 4140
7498 19:25:46.702579 244 : 4250, 4026
7499 19:25:46.702666 248 : 4250, 4027
7500 19:25:46.705698 252 : 4250, 4027
7501 19:25:46.705808 256 : 4249, 4027
7502 19:25:46.709022 260 : 4250, 4027
7503 19:25:46.709110 264 : 4361, 4137
7504 19:25:46.712742 268 : 4250, 4027
7505 19:25:46.712829 272 : 4250, 4027
7506 19:25:46.715623 276 : 4250, 4027
7507 19:25:46.715734 280 : 4250, 4026
7508 19:25:46.715829 284 : 4360, 4138
7509 19:25:46.718988 288 : 4250, 4027
7510 19:25:46.719076 292 : 4360, 4138
7511 19:25:46.722284 296 : 4250, 4026
7512 19:25:46.722414 300 : 4250, 4027
7513 19:25:46.725659 304 : 4249, 4027
7514 19:25:46.725745 308 : 4250, 4027
7515 19:25:46.728923 312 : 4255, 4029
7516 19:25:46.729008 316 : 4361, 4137
7517 19:25:46.732285 320 : 4250, 4027
7518 19:25:46.732370 324 : 4250, 4027
7519 19:25:46.735141 328 : 4255, 4029
7520 19:25:46.735225 332 : 4250, 3954
7521 19:25:46.738598 336 : 4363, 1864
7522 19:25:46.738700
7523 19:25:46.738802 MIOCK jitter meter ch=0
7524 19:25:46.738925
7525 19:25:46.741916 1T = (336-100) = 236 dly cells
7526 19:25:46.749087 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7527 19:25:46.749185 ==
7528 19:25:46.751676 Dram Type= 6, Freq= 0, CH_0, rank 0
7529 19:25:46.754861 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7530 19:25:46.754946 ==
7531 19:25:46.761762 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7532 19:25:46.765082 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7533 19:25:46.768134 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7534 19:25:46.774680 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7535 19:25:46.788436 [CA 0] Center 43 (13~74) winsize 62
7536 19:25:46.788597 [CA 1] Center 42 (12~73) winsize 62
7537 19:25:46.791121 [CA 2] Center 37 (8~67) winsize 60
7538 19:25:46.794426 [CA 3] Center 37 (8~67) winsize 60
7539 19:25:46.797567 [CA 4] Center 36 (6~66) winsize 61
7540 19:25:46.801368 [CA 5] Center 35 (5~66) winsize 62
7541 19:25:46.801458
7542 19:25:46.804156 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7543 19:25:46.804250
7544 19:25:46.811084 [CATrainingPosCal] consider 1 rank data
7545 19:25:46.811183 u2DelayCellTimex100 = 275/100 ps
7546 19:25:46.817497 CA0 delay=43 (13~74),Diff = 8 PI (28 cell)
7547 19:25:46.820777 CA1 delay=42 (12~73),Diff = 7 PI (24 cell)
7548 19:25:46.824002 CA2 delay=37 (8~67),Diff = 2 PI (7 cell)
7549 19:25:46.827261 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7550 19:25:46.830634 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7551 19:25:46.833686 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
7552 19:25:46.833773
7553 19:25:46.837522 CA PerBit enable=1, Macro0, CA PI delay=35
7554 19:25:46.837623
7555 19:25:46.840621 [CBTSetCACLKResult] CA Dly = 35
7556 19:25:46.843754 CS Dly: 10 (0~41)
7557 19:25:46.847063 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7558 19:25:46.850432 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7559 19:25:46.850514 ==
7560 19:25:46.853547 Dram Type= 6, Freq= 0, CH_0, rank 1
7561 19:25:46.860094 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7562 19:25:46.860181 ==
7563 19:25:46.863498 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7564 19:25:46.870178 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7565 19:25:46.873748 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7566 19:25:46.880383 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7567 19:25:46.888014 [CA 0] Center 44 (14~75) winsize 62
7568 19:25:46.891246 [CA 1] Center 44 (14~74) winsize 61
7569 19:25:46.894975 [CA 2] Center 39 (10~69) winsize 60
7570 19:25:46.898165 [CA 3] Center 39 (10~68) winsize 59
7571 19:25:46.901413 [CA 4] Center 37 (7~67) winsize 61
7572 19:25:46.904665 [CA 5] Center 36 (6~66) winsize 61
7573 19:25:46.904750
7574 19:25:46.907710 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7575 19:25:46.907793
7576 19:25:46.914699 [CATrainingPosCal] consider 2 rank data
7577 19:25:46.914792 u2DelayCellTimex100 = 275/100 ps
7578 19:25:46.920853 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7579 19:25:46.924241 CA1 delay=43 (14~73),Diff = 7 PI (24 cell)
7580 19:25:46.927837 CA2 delay=38 (10~67),Diff = 2 PI (7 cell)
7581 19:25:46.931118 CA3 delay=38 (10~67),Diff = 2 PI (7 cell)
7582 19:25:46.934234 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7583 19:25:46.937854 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7584 19:25:46.937953
7585 19:25:46.940622 CA PerBit enable=1, Macro0, CA PI delay=36
7586 19:25:46.940743
7587 19:25:46.943811 [CBTSetCACLKResult] CA Dly = 36
7588 19:25:46.947211 CS Dly: 11 (0~44)
7589 19:25:46.950461 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7590 19:25:46.954101 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7591 19:25:46.954187
7592 19:25:46.957461 ----->DramcWriteLeveling(PI) begin...
7593 19:25:46.960379 ==
7594 19:25:46.963855 Dram Type= 6, Freq= 0, CH_0, rank 0
7595 19:25:46.967239 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7596 19:25:46.967326 ==
7597 19:25:46.970483 Write leveling (Byte 0): 35 => 35
7598 19:25:46.973577 Write leveling (Byte 1): 25 => 25
7599 19:25:46.977228 DramcWriteLeveling(PI) end<-----
7600 19:25:46.977313
7601 19:25:46.977377 ==
7602 19:25:46.980122 Dram Type= 6, Freq= 0, CH_0, rank 0
7603 19:25:46.983711 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7604 19:25:46.983794 ==
7605 19:25:46.987129 [Gating] SW mode calibration
7606 19:25:46.993782 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7607 19:25:46.999760 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7608 19:25:47.003208 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7609 19:25:47.006534 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7610 19:25:47.013119 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7611 19:25:47.016920 1 4 12 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
7612 19:25:47.019755 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7613 19:25:47.026451 1 4 20 | B1->B0 | 2a29 3434 | 1 1 | (0 0) (1 1)
7614 19:25:47.029576 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7615 19:25:47.032996 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7616 19:25:47.039637 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7617 19:25:47.042925 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7618 19:25:47.045882 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
7619 19:25:47.052394 1 5 12 | B1->B0 | 3434 2626 | 1 1 | (1 1) (1 0)
7620 19:25:47.056264 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7621 19:25:47.059343 1 5 20 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
7622 19:25:47.065646 1 5 24 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
7623 19:25:47.068932 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7624 19:25:47.072645 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7625 19:25:47.079344 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7626 19:25:47.082626 1 6 8 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (0 0)
7627 19:25:47.085690 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7628 19:25:47.092254 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7629 19:25:47.095440 1 6 20 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
7630 19:25:47.099119 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7631 19:25:47.105277 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7632 19:25:47.108936 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7633 19:25:47.112091 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7634 19:25:47.118364 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7635 19:25:47.121618 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7636 19:25:47.124789 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7637 19:25:47.131498 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7638 19:25:47.135213 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7639 19:25:47.138058 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 19:25:47.144955 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7641 19:25:47.148339 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7642 19:25:47.151420 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 19:25:47.158144 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7644 19:25:47.161247 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7645 19:25:47.164784 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7646 19:25:47.170970 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7647 19:25:47.174026 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7648 19:25:47.177515 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7649 19:25:47.184083 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7650 19:25:47.187284 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7651 19:25:47.190545 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7652 19:25:47.193782 Total UI for P1: 0, mck2ui 16
7653 19:25:47.197340 best dqsien dly found for B0: ( 1, 9, 8)
7654 19:25:47.203650 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7655 19:25:47.206981 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7656 19:25:47.210265 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7657 19:25:47.217290 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7658 19:25:47.220497 Total UI for P1: 0, mck2ui 16
7659 19:25:47.223826 best dqsien dly found for B1: ( 1, 9, 22)
7660 19:25:47.226713 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
7661 19:25:47.230565 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7662 19:25:47.230649
7663 19:25:47.233220 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
7664 19:25:47.236736 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7665 19:25:47.239989 [Gating] SW calibration Done
7666 19:25:47.240072 ==
7667 19:25:47.243366 Dram Type= 6, Freq= 0, CH_0, rank 0
7668 19:25:47.246640 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7669 19:25:47.246742 ==
7670 19:25:47.249817 RX Vref Scan: 0
7671 19:25:47.249899
7672 19:25:47.253370 RX Vref 0 -> 0, step: 1
7673 19:25:47.253455
7674 19:25:47.253519 RX Delay 0 -> 252, step: 8
7675 19:25:47.259404 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7676 19:25:47.262979 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7677 19:25:47.266156 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7678 19:25:47.269373 iDelay=192, Bit 3, Center 131 (80 ~ 183) 104
7679 19:25:47.272798 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7680 19:25:47.279378 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7681 19:25:47.282727 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7682 19:25:47.286198 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7683 19:25:47.289261 iDelay=192, Bit 8, Center 115 (64 ~ 167) 104
7684 19:25:47.295693 iDelay=192, Bit 9, Center 115 (64 ~ 167) 104
7685 19:25:47.299066 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7686 19:25:47.302561 iDelay=192, Bit 11, Center 123 (72 ~ 175) 104
7687 19:25:47.305869 iDelay=192, Bit 12, Center 135 (80 ~ 191) 112
7688 19:25:47.309100 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7689 19:25:47.315531 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7690 19:25:47.319214 iDelay=192, Bit 15, Center 131 (80 ~ 183) 104
7691 19:25:47.319332 ==
7692 19:25:47.322291 Dram Type= 6, Freq= 0, CH_0, rank 0
7693 19:25:47.325311 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7694 19:25:47.325386 ==
7695 19:25:47.328565 DQS Delay:
7696 19:25:47.328638 DQS0 = 0, DQS1 = 0
7697 19:25:47.328698 DQM Delay:
7698 19:25:47.331735 DQM0 = 132, DQM1 = 126
7699 19:25:47.331813 DQ Delay:
7700 19:25:47.335362 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =131
7701 19:25:47.338362 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7702 19:25:47.344966 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
7703 19:25:47.348416 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =131
7704 19:25:47.348504
7705 19:25:47.348568
7706 19:25:47.348628 ==
7707 19:25:47.351697 Dram Type= 6, Freq= 0, CH_0, rank 0
7708 19:25:47.355122 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7709 19:25:47.355204 ==
7710 19:25:47.355269
7711 19:25:47.355326
7712 19:25:47.358811 TX Vref Scan disable
7713 19:25:47.361312 == TX Byte 0 ==
7714 19:25:47.364852 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7715 19:25:47.368191 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7716 19:25:47.371615 == TX Byte 1 ==
7717 19:25:47.374869 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7718 19:25:47.378282 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7719 19:25:47.378366 ==
7720 19:25:47.381658 Dram Type= 6, Freq= 0, CH_0, rank 0
7721 19:25:47.387993 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7722 19:25:47.388077 ==
7723 19:25:47.401864
7724 19:25:47.404607 TX Vref early break, caculate TX vref
7725 19:25:47.407778 TX Vref=16, minBit 1, minWin=20, winSum=357
7726 19:25:47.411614 TX Vref=18, minBit 1, minWin=21, winSum=368
7727 19:25:47.414948 TX Vref=20, minBit 6, minWin=21, winSum=375
7728 19:25:47.417955 TX Vref=22, minBit 1, minWin=23, winSum=392
7729 19:25:47.421258 TX Vref=24, minBit 1, minWin=23, winSum=399
7730 19:25:47.427724 TX Vref=26, minBit 2, minWin=24, winSum=404
7731 19:25:47.431411 TX Vref=28, minBit 1, minWin=23, winSum=403
7732 19:25:47.434364 TX Vref=30, minBit 0, minWin=24, winSum=402
7733 19:25:47.437642 TX Vref=32, minBit 2, minWin=23, winSum=394
7734 19:25:47.441130 TX Vref=34, minBit 0, minWin=23, winSum=384
7735 19:25:47.447460 TX Vref=36, minBit 1, minWin=22, winSum=372
7736 19:25:47.450579 [TxChooseVref] Worse bit 2, Min win 24, Win sum 404, Final Vref 26
7737 19:25:47.450664
7738 19:25:47.453830 Final TX Range 0 Vref 26
7739 19:25:47.453914
7740 19:25:47.453978 ==
7741 19:25:47.457310 Dram Type= 6, Freq= 0, CH_0, rank 0
7742 19:25:47.460969 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7743 19:25:47.464169 ==
7744 19:25:47.464252
7745 19:25:47.464316
7746 19:25:47.464375 TX Vref Scan disable
7747 19:25:47.471105 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7748 19:25:47.471192 == TX Byte 0 ==
7749 19:25:47.473928 u2DelayCellOfst[0]=14 cells (4 PI)
7750 19:25:47.477463 u2DelayCellOfst[1]=17 cells (5 PI)
7751 19:25:47.480888 u2DelayCellOfst[2]=10 cells (3 PI)
7752 19:25:47.483665 u2DelayCellOfst[3]=10 cells (3 PI)
7753 19:25:47.487281 u2DelayCellOfst[4]=7 cells (2 PI)
7754 19:25:47.490287 u2DelayCellOfst[5]=0 cells (0 PI)
7755 19:25:47.493947 u2DelayCellOfst[6]=17 cells (5 PI)
7756 19:25:47.497043 u2DelayCellOfst[7]=17 cells (5 PI)
7757 19:25:47.500328 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7758 19:25:47.503760 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7759 19:25:47.507117 == TX Byte 1 ==
7760 19:25:47.509949 u2DelayCellOfst[8]=0 cells (0 PI)
7761 19:25:47.513470 u2DelayCellOfst[9]=0 cells (0 PI)
7762 19:25:47.516549 u2DelayCellOfst[10]=3 cells (1 PI)
7763 19:25:47.520383 u2DelayCellOfst[11]=0 cells (0 PI)
7764 19:25:47.523360 u2DelayCellOfst[12]=7 cells (2 PI)
7765 19:25:47.526391 u2DelayCellOfst[13]=10 cells (3 PI)
7766 19:25:47.529995 u2DelayCellOfst[14]=10 cells (3 PI)
7767 19:25:47.533545 u2DelayCellOfst[15]=10 cells (3 PI)
7768 19:25:47.536569 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7769 19:25:47.539598 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7770 19:25:47.542912 DramC Write-DBI on
7771 19:25:47.542995 ==
7772 19:25:47.546339 Dram Type= 6, Freq= 0, CH_0, rank 0
7773 19:25:47.549879 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7774 19:25:47.549988 ==
7775 19:25:47.550079
7776 19:25:47.550166
7777 19:25:47.553242 TX Vref Scan disable
7778 19:25:47.556083 == TX Byte 0 ==
7779 19:25:47.559732 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7780 19:25:47.559815 == TX Byte 1 ==
7781 19:25:47.566287 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7782 19:25:47.566369 DramC Write-DBI off
7783 19:25:47.566432
7784 19:25:47.566491 [DATLAT]
7785 19:25:47.569832 Freq=1600, CH0 RK0
7786 19:25:47.569912
7787 19:25:47.572963 DATLAT Default: 0xf
7788 19:25:47.573044 0, 0xFFFF, sum = 0
7789 19:25:47.576418 1, 0xFFFF, sum = 0
7790 19:25:47.576500 2, 0xFFFF, sum = 0
7791 19:25:47.579172 3, 0xFFFF, sum = 0
7792 19:25:47.579253 4, 0xFFFF, sum = 0
7793 19:25:47.582439 5, 0xFFFF, sum = 0
7794 19:25:47.582521 6, 0xFFFF, sum = 0
7795 19:25:47.586003 7, 0xFFFF, sum = 0
7796 19:25:47.586084 8, 0xFFFF, sum = 0
7797 19:25:47.589514 9, 0xFFFF, sum = 0
7798 19:25:47.589595 10, 0xFFFF, sum = 0
7799 19:25:47.592844 11, 0xFFFF, sum = 0
7800 19:25:47.592928 12, 0xFFFF, sum = 0
7801 19:25:47.596077 13, 0xFFFF, sum = 0
7802 19:25:47.596159 14, 0x0, sum = 1
7803 19:25:47.599062 15, 0x0, sum = 2
7804 19:25:47.599143 16, 0x0, sum = 3
7805 19:25:47.602667 17, 0x0, sum = 4
7806 19:25:47.602781 best_step = 15
7807 19:25:47.602876
7808 19:25:47.602967 ==
7809 19:25:47.606155 Dram Type= 6, Freq= 0, CH_0, rank 0
7810 19:25:47.612095 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7811 19:25:47.612179 ==
7812 19:25:47.612243 RX Vref Scan: 1
7813 19:25:47.612302
7814 19:25:47.615893 Set Vref Range= 24 -> 127
7815 19:25:47.615989
7816 19:25:47.618791 RX Vref 24 -> 127, step: 1
7817 19:25:47.618899
7818 19:25:47.622051 RX Delay 19 -> 252, step: 4
7819 19:25:47.622210
7820 19:25:47.625342 Set Vref, RX VrefLevel [Byte0]: 24
7821 19:25:47.628404 [Byte1]: 24
7822 19:25:47.628511
7823 19:25:47.632478 Set Vref, RX VrefLevel [Byte0]: 25
7824 19:25:47.635225 [Byte1]: 25
7825 19:25:47.635334
7826 19:25:47.638607 Set Vref, RX VrefLevel [Byte0]: 26
7827 19:25:47.641716 [Byte1]: 26
7828 19:25:47.645964
7829 19:25:47.646046 Set Vref, RX VrefLevel [Byte0]: 27
7830 19:25:47.648472 [Byte1]: 27
7831 19:25:47.652311
7832 19:25:47.652392 Set Vref, RX VrefLevel [Byte0]: 28
7833 19:25:47.655757 [Byte1]: 28
7834 19:25:47.660398
7835 19:25:47.660487 Set Vref, RX VrefLevel [Byte0]: 29
7836 19:25:47.663504 [Byte1]: 29
7837 19:25:47.667742
7838 19:25:47.667851 Set Vref, RX VrefLevel [Byte0]: 30
7839 19:25:47.671098 [Byte1]: 30
7840 19:25:47.675223
7841 19:25:47.675304 Set Vref, RX VrefLevel [Byte0]: 31
7842 19:25:47.678999 [Byte1]: 31
7843 19:25:47.682985
7844 19:25:47.683068 Set Vref, RX VrefLevel [Byte0]: 32
7845 19:25:47.686651 [Byte1]: 32
7846 19:25:47.690598
7847 19:25:47.690705 Set Vref, RX VrefLevel [Byte0]: 33
7848 19:25:47.693887 [Byte1]: 33
7849 19:25:47.698840
7850 19:25:47.698955 Set Vref, RX VrefLevel [Byte0]: 34
7851 19:25:47.701080 [Byte1]: 34
7852 19:25:47.705481
7853 19:25:47.705560 Set Vref, RX VrefLevel [Byte0]: 35
7854 19:25:47.709037 [Byte1]: 35
7855 19:25:47.713812
7856 19:25:47.713921 Set Vref, RX VrefLevel [Byte0]: 36
7857 19:25:47.716780 [Byte1]: 36
7858 19:25:47.720863
7859 19:25:47.721010 Set Vref, RX VrefLevel [Byte0]: 37
7860 19:25:47.724040 [Byte1]: 37
7861 19:25:47.728185
7862 19:25:47.728332 Set Vref, RX VrefLevel [Byte0]: 38
7863 19:25:47.732074 [Byte1]: 38
7864 19:25:47.736082
7865 19:25:47.736227 Set Vref, RX VrefLevel [Byte0]: 39
7866 19:25:47.739098 [Byte1]: 39
7867 19:25:47.743627
7868 19:25:47.743782 Set Vref, RX VrefLevel [Byte0]: 40
7869 19:25:47.746655 [Byte1]: 40
7870 19:25:47.751111
7871 19:25:47.751279 Set Vref, RX VrefLevel [Byte0]: 41
7872 19:25:47.754468 [Byte1]: 41
7873 19:25:47.758732
7874 19:25:47.758879 Set Vref, RX VrefLevel [Byte0]: 42
7875 19:25:47.761965 [Byte1]: 42
7876 19:25:47.766096
7877 19:25:47.766203 Set Vref, RX VrefLevel [Byte0]: 43
7878 19:25:47.769885 [Byte1]: 43
7879 19:25:47.773891
7880 19:25:47.773971 Set Vref, RX VrefLevel [Byte0]: 44
7881 19:25:47.777196 [Byte1]: 44
7882 19:25:47.781183
7883 19:25:47.781287 Set Vref, RX VrefLevel [Byte0]: 45
7884 19:25:47.784638 [Byte1]: 45
7885 19:25:47.788891
7886 19:25:47.788980 Set Vref, RX VrefLevel [Byte0]: 46
7887 19:25:47.792341 [Byte1]: 46
7888 19:25:47.796437
7889 19:25:47.796552 Set Vref, RX VrefLevel [Byte0]: 47
7890 19:25:47.800115 [Byte1]: 47
7891 19:25:47.803812
7892 19:25:47.807162 Set Vref, RX VrefLevel [Byte0]: 48
7893 19:25:47.810619 [Byte1]: 48
7894 19:25:47.810726
7895 19:25:47.813837 Set Vref, RX VrefLevel [Byte0]: 49
7896 19:25:47.817152 [Byte1]: 49
7897 19:25:47.817253
7898 19:25:47.820600 Set Vref, RX VrefLevel [Byte0]: 50
7899 19:25:47.824444 [Byte1]: 50
7900 19:25:47.824526
7901 19:25:47.827178 Set Vref, RX VrefLevel [Byte0]: 51
7902 19:25:47.830239 [Byte1]: 51
7903 19:25:47.834287
7904 19:25:47.834395 Set Vref, RX VrefLevel [Byte0]: 52
7905 19:25:47.837644 [Byte1]: 52
7906 19:25:47.841997
7907 19:25:47.842082 Set Vref, RX VrefLevel [Byte0]: 53
7908 19:25:47.844974 [Byte1]: 53
7909 19:25:47.849699
7910 19:25:47.849780 Set Vref, RX VrefLevel [Byte0]: 54
7911 19:25:47.853031 [Byte1]: 54
7912 19:25:47.857503
7913 19:25:47.857616 Set Vref, RX VrefLevel [Byte0]: 55
7914 19:25:47.860350 [Byte1]: 55
7915 19:25:47.864597
7916 19:25:47.864780 Set Vref, RX VrefLevel [Byte0]: 56
7917 19:25:47.868251 [Byte1]: 56
7918 19:25:47.872445
7919 19:25:47.872528 Set Vref, RX VrefLevel [Byte0]: 57
7920 19:25:47.875264 [Byte1]: 57
7921 19:25:47.879720
7922 19:25:47.879829 Set Vref, RX VrefLevel [Byte0]: 58
7923 19:25:47.883039 [Byte1]: 58
7924 19:25:47.887396
7925 19:25:47.887479 Set Vref, RX VrefLevel [Byte0]: 59
7926 19:25:47.890601 [Byte1]: 59
7927 19:25:47.894635
7928 19:25:47.894725 Set Vref, RX VrefLevel [Byte0]: 60
7929 19:25:47.898293 [Byte1]: 60
7930 19:25:47.902611
7931 19:25:47.902696 Set Vref, RX VrefLevel [Byte0]: 61
7932 19:25:47.906001 [Byte1]: 61
7933 19:25:47.909866
7934 19:25:47.909953 Set Vref, RX VrefLevel [Byte0]: 62
7935 19:25:47.913543 [Byte1]: 62
7936 19:25:47.917402
7937 19:25:47.917487 Set Vref, RX VrefLevel [Byte0]: 63
7938 19:25:47.921168 [Byte1]: 63
7939 19:25:47.925092
7940 19:25:47.925177 Set Vref, RX VrefLevel [Byte0]: 64
7941 19:25:47.928563 [Byte1]: 64
7942 19:25:47.932650
7943 19:25:47.932734 Set Vref, RX VrefLevel [Byte0]: 65
7944 19:25:47.936227 [Byte1]: 65
7945 19:25:47.940279
7946 19:25:47.940391 Set Vref, RX VrefLevel [Byte0]: 66
7947 19:25:47.943585 [Byte1]: 66
7948 19:25:47.948954
7949 19:25:47.949037 Set Vref, RX VrefLevel [Byte0]: 67
7950 19:25:47.951523 [Byte1]: 67
7951 19:25:47.955569
7952 19:25:47.955655 Set Vref, RX VrefLevel [Byte0]: 68
7953 19:25:47.958773 [Byte1]: 68
7954 19:25:47.963141
7955 19:25:47.963250 Set Vref, RX VrefLevel [Byte0]: 69
7956 19:25:47.966378 [Byte1]: 69
7957 19:25:47.970350
7958 19:25:47.970466 Set Vref, RX VrefLevel [Byte0]: 70
7959 19:25:47.974519 [Byte1]: 70
7960 19:25:47.978404
7961 19:25:47.978513 Set Vref, RX VrefLevel [Byte0]: 71
7962 19:25:47.981561 [Byte1]: 71
7963 19:25:47.986317
7964 19:25:47.986433 Set Vref, RX VrefLevel [Byte0]: 72
7965 19:25:47.989412 [Byte1]: 72
7966 19:25:47.993153
7967 19:25:47.993240 Set Vref, RX VrefLevel [Byte0]: 73
7968 19:25:47.996718 [Byte1]: 73
7969 19:25:48.000810
7970 19:25:48.003865 Set Vref, RX VrefLevel [Byte0]: 74
7971 19:25:48.007064 [Byte1]: 74
7972 19:25:48.007170
7973 19:25:48.010696 Set Vref, RX VrefLevel [Byte0]: 75
7974 19:25:48.014058 [Byte1]: 75
7975 19:25:48.014135
7976 19:25:48.017610 Set Vref, RX VrefLevel [Byte0]: 76
7977 19:25:48.020535 [Byte1]: 76
7978 19:25:48.020619
7979 19:25:48.023784 Set Vref, RX VrefLevel [Byte0]: 77
7980 19:25:48.027430 [Byte1]: 77
7981 19:25:48.031215
7982 19:25:48.031315 Final RX Vref Byte 0 = 56 to rank0
7983 19:25:48.034517 Final RX Vref Byte 1 = 57 to rank0
7984 19:25:48.037556 Final RX Vref Byte 0 = 56 to rank1
7985 19:25:48.041406 Final RX Vref Byte 1 = 57 to rank1==
7986 19:25:48.044477 Dram Type= 6, Freq= 0, CH_0, rank 0
7987 19:25:48.050754 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7988 19:25:48.050851 ==
7989 19:25:48.050943 DQS Delay:
7990 19:25:48.054218 DQS0 = 0, DQS1 = 0
7991 19:25:48.054312 DQM Delay:
7992 19:25:48.054399 DQM0 = 128, DQM1 = 124
7993 19:25:48.057680 DQ Delay:
7994 19:25:48.061120 DQ0 =130, DQ1 =130, DQ2 =124, DQ3 =124
7995 19:25:48.064810 DQ4 =132, DQ5 =118, DQ6 =138, DQ7 =134
7996 19:25:48.067240 DQ8 =112, DQ9 =110, DQ10 =126, DQ11 =120
7997 19:25:48.070658 DQ12 =130, DQ13 =128, DQ14 =134, DQ15 =132
7998 19:25:48.070758
7999 19:25:48.070817
8000 19:25:48.070882
8001 19:25:48.074099 [DramC_TX_OE_Calibration] TA2
8002 19:25:48.077332 Original DQ_B0 (3 6) =30, OEN = 27
8003 19:25:48.081305 Original DQ_B1 (3 6) =30, OEN = 27
8004 19:25:48.084160 24, 0x0, End_B0=24 End_B1=24
8005 19:25:48.084230 25, 0x0, End_B0=25 End_B1=25
8006 19:25:48.087185 26, 0x0, End_B0=26 End_B1=26
8007 19:25:48.090537 27, 0x0, End_B0=27 End_B1=27
8008 19:25:48.093804 28, 0x0, End_B0=28 End_B1=28
8009 19:25:48.097317 29, 0x0, End_B0=29 End_B1=29
8010 19:25:48.097392 30, 0x0, End_B0=30 End_B1=30
8011 19:25:48.100481 31, 0x4141, End_B0=30 End_B1=30
8012 19:25:48.104050 Byte0 end_step=30 best_step=27
8013 19:25:48.107375 Byte1 end_step=30 best_step=27
8014 19:25:48.110519 Byte0 TX OE(2T, 0.5T) = (3, 3)
8015 19:25:48.113842 Byte1 TX OE(2T, 0.5T) = (3, 3)
8016 19:25:48.113925
8017 19:25:48.113989
8018 19:25:48.120293 [DQSOSCAuto] RK0, (LSB)MR18= 0x1815, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 397 ps
8019 19:25:48.123943 CH0 RK0: MR19=303, MR18=1815
8020 19:25:48.130436 CH0_RK0: MR19=0x303, MR18=0x1815, DQSOSC=397, MR23=63, INC=23, DEC=15
8021 19:25:48.130595
8022 19:25:48.133476 ----->DramcWriteLeveling(PI) begin...
8023 19:25:48.133560 ==
8024 19:25:48.137128 Dram Type= 6, Freq= 0, CH_0, rank 1
8025 19:25:48.140325 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8026 19:25:48.140406 ==
8027 19:25:48.143254 Write leveling (Byte 0): 34 => 34
8028 19:25:48.146585 Write leveling (Byte 1): 26 => 26
8029 19:25:48.150497 DramcWriteLeveling(PI) end<-----
8030 19:25:48.150574
8031 19:25:48.150640 ==
8032 19:25:48.153066 Dram Type= 6, Freq= 0, CH_0, rank 1
8033 19:25:48.156897 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8034 19:25:48.159574 ==
8035 19:25:48.159649 [Gating] SW mode calibration
8036 19:25:48.169761 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8037 19:25:48.172967 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8038 19:25:48.176145 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8039 19:25:48.182686 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8040 19:25:48.186202 1 4 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
8041 19:25:48.189506 1 4 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
8042 19:25:48.195722 1 4 16 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
8043 19:25:48.199319 1 4 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8044 19:25:48.202824 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8045 19:25:48.209952 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8046 19:25:48.212269 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8047 19:25:48.215810 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8048 19:25:48.222324 1 5 8 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 0)
8049 19:25:48.225693 1 5 12 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 1)
8050 19:25:48.229276 1 5 16 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
8051 19:25:48.235476 1 5 20 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
8052 19:25:48.239273 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8053 19:25:48.245103 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8054 19:25:48.248735 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8055 19:25:48.251567 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8056 19:25:48.258200 1 6 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (1 1)
8057 19:25:48.261794 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8058 19:25:48.265471 1 6 16 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
8059 19:25:48.271349 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8060 19:25:48.274708 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8061 19:25:48.278587 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8062 19:25:48.284493 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8063 19:25:48.287854 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8064 19:25:48.291476 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8065 19:25:48.297713 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8066 19:25:48.301363 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8067 19:25:48.304195 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8068 19:25:48.310991 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8069 19:25:48.313982 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8070 19:25:48.317959 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8071 19:25:48.324157 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8072 19:25:48.327326 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8073 19:25:48.330673 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8074 19:25:48.337413 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8075 19:25:48.340542 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8076 19:25:48.344351 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8077 19:25:48.350389 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8078 19:25:48.353889 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8079 19:25:48.356918 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8080 19:25:48.363667 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8081 19:25:48.366914 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8082 19:25:48.370339 Total UI for P1: 0, mck2ui 16
8083 19:25:48.373247 best dqsien dly found for B0: ( 1, 9, 6)
8084 19:25:48.376782 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8085 19:25:48.383106 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8086 19:25:48.386535 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8087 19:25:48.389644 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8088 19:25:48.393127 Total UI for P1: 0, mck2ui 16
8089 19:25:48.396146 best dqsien dly found for B1: ( 1, 9, 20)
8090 19:25:48.399690 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8091 19:25:48.402716 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8092 19:25:48.402791
8093 19:25:48.409397 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8094 19:25:48.412745 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8095 19:25:48.416015 [Gating] SW calibration Done
8096 19:25:48.416089 ==
8097 19:25:48.419265 Dram Type= 6, Freq= 0, CH_0, rank 1
8098 19:25:48.422646 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8099 19:25:48.422721 ==
8100 19:25:48.422782 RX Vref Scan: 0
8101 19:25:48.425656
8102 19:25:48.425723 RX Vref 0 -> 0, step: 1
8103 19:25:48.425782
8104 19:25:48.428997 RX Delay 0 -> 252, step: 8
8105 19:25:48.432407 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8106 19:25:48.435793 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8107 19:25:48.442365 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8108 19:25:48.445507 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8109 19:25:48.449238 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8110 19:25:48.452142 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8111 19:25:48.455967 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8112 19:25:48.462233 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8113 19:25:48.465244 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8114 19:25:48.469250 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8115 19:25:48.472213 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8116 19:25:48.475318 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8117 19:25:48.482142 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8118 19:25:48.484976 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8119 19:25:48.488941 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8120 19:25:48.492488 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8121 19:25:48.495065 ==
8122 19:25:48.495177 Dram Type= 6, Freq= 0, CH_0, rank 1
8123 19:25:48.501766 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8124 19:25:48.501876 ==
8125 19:25:48.501980 DQS Delay:
8126 19:25:48.504862 DQS0 = 0, DQS1 = 0
8127 19:25:48.504943 DQM Delay:
8128 19:25:48.508371 DQM0 = 131, DQM1 = 127
8129 19:25:48.508478 DQ Delay:
8130 19:25:48.511598 DQ0 =127, DQ1 =135, DQ2 =127, DQ3 =127
8131 19:25:48.515073 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
8132 19:25:48.518425 DQ8 =119, DQ9 =111, DQ10 =131, DQ11 =119
8133 19:25:48.521488 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =135
8134 19:25:48.521569
8135 19:25:48.521633
8136 19:25:48.521691 ==
8137 19:25:48.524793 Dram Type= 6, Freq= 0, CH_0, rank 1
8138 19:25:48.531073 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8139 19:25:48.531154 ==
8140 19:25:48.531218
8141 19:25:48.531277
8142 19:25:48.534581 TX Vref Scan disable
8143 19:25:48.534661 == TX Byte 0 ==
8144 19:25:48.537836 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8145 19:25:48.544035 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8146 19:25:48.544118 == TX Byte 1 ==
8147 19:25:48.550341 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8148 19:25:48.553993 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8149 19:25:48.554071 ==
8150 19:25:48.557021 Dram Type= 6, Freq= 0, CH_0, rank 1
8151 19:25:48.560285 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8152 19:25:48.560385 ==
8153 19:25:48.575911
8154 19:25:48.579087 TX Vref early break, caculate TX vref
8155 19:25:48.582709 TX Vref=16, minBit 3, minWin=22, winSum=374
8156 19:25:48.585975 TX Vref=18, minBit 3, minWin=23, winSum=382
8157 19:25:48.589061 TX Vref=20, minBit 8, minWin=23, winSum=391
8158 19:25:48.592281 TX Vref=22, minBit 0, minWin=24, winSum=396
8159 19:25:48.595750 TX Vref=24, minBit 0, minWin=24, winSum=403
8160 19:25:48.602427 TX Vref=26, minBit 0, minWin=25, winSum=413
8161 19:25:48.605564 TX Vref=28, minBit 0, minWin=24, winSum=410
8162 19:25:48.608695 TX Vref=30, minBit 0, minWin=24, winSum=403
8163 19:25:48.612060 TX Vref=32, minBit 4, minWin=23, winSum=396
8164 19:25:48.615664 TX Vref=34, minBit 0, minWin=24, winSum=392
8165 19:25:48.619134 TX Vref=36, minBit 1, minWin=23, winSum=385
8166 19:25:48.625671 [TxChooseVref] Worse bit 0, Min win 25, Win sum 413, Final Vref 26
8167 19:25:48.625767
8168 19:25:48.628599 Final TX Range 0 Vref 26
8169 19:25:48.628682
8170 19:25:48.628746 ==
8171 19:25:48.632343 Dram Type= 6, Freq= 0, CH_0, rank 1
8172 19:25:48.634933 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8173 19:25:48.638427 ==
8174 19:25:48.638509
8175 19:25:48.638628
8176 19:25:48.638736 TX Vref Scan disable
8177 19:25:48.645117 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8178 19:25:48.645205 == TX Byte 0 ==
8179 19:25:48.648433 u2DelayCellOfst[0]=14 cells (4 PI)
8180 19:25:48.651836 u2DelayCellOfst[1]=17 cells (5 PI)
8181 19:25:48.655040 u2DelayCellOfst[2]=14 cells (4 PI)
8182 19:25:48.658480 u2DelayCellOfst[3]=14 cells (4 PI)
8183 19:25:48.662067 u2DelayCellOfst[4]=10 cells (3 PI)
8184 19:25:48.664840 u2DelayCellOfst[5]=0 cells (0 PI)
8185 19:25:48.668149 u2DelayCellOfst[6]=17 cells (5 PI)
8186 19:25:48.671698 u2DelayCellOfst[7]=17 cells (5 PI)
8187 19:25:48.674749 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8188 19:25:48.678122 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8189 19:25:48.681816 == TX Byte 1 ==
8190 19:25:48.684689 u2DelayCellOfst[8]=3 cells (1 PI)
8191 19:25:48.688193 u2DelayCellOfst[9]=0 cells (0 PI)
8192 19:25:48.691318 u2DelayCellOfst[10]=3 cells (1 PI)
8193 19:25:48.694776 u2DelayCellOfst[11]=3 cells (1 PI)
8194 19:25:48.697802 u2DelayCellOfst[12]=10 cells (3 PI)
8195 19:25:48.701792 u2DelayCellOfst[13]=10 cells (3 PI)
8196 19:25:48.704301 u2DelayCellOfst[14]=14 cells (4 PI)
8197 19:25:48.708229 u2DelayCellOfst[15]=10 cells (3 PI)
8198 19:25:48.711342 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8199 19:25:48.714192 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8200 19:25:48.717459 DramC Write-DBI on
8201 19:25:48.717570 ==
8202 19:25:48.720720 Dram Type= 6, Freq= 0, CH_0, rank 1
8203 19:25:48.724174 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8204 19:25:48.724255 ==
8205 19:25:48.724334
8206 19:25:48.724398
8207 19:25:48.727145 TX Vref Scan disable
8208 19:25:48.730453 == TX Byte 0 ==
8209 19:25:48.733794 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8210 19:25:48.733897 == TX Byte 1 ==
8211 19:25:48.740577 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8212 19:25:48.740659 DramC Write-DBI off
8213 19:25:48.740723
8214 19:25:48.743652 [DATLAT]
8215 19:25:48.743757 Freq=1600, CH0 RK1
8216 19:25:48.743848
8217 19:25:48.746751 DATLAT Default: 0xf
8218 19:25:48.746859 0, 0xFFFF, sum = 0
8219 19:25:48.750168 1, 0xFFFF, sum = 0
8220 19:25:48.750250 2, 0xFFFF, sum = 0
8221 19:25:48.753472 3, 0xFFFF, sum = 0
8222 19:25:48.753554 4, 0xFFFF, sum = 0
8223 19:25:48.756926 5, 0xFFFF, sum = 0
8224 19:25:48.757009 6, 0xFFFF, sum = 0
8225 19:25:48.760449 7, 0xFFFF, sum = 0
8226 19:25:48.760531 8, 0xFFFF, sum = 0
8227 19:25:48.764003 9, 0xFFFF, sum = 0
8228 19:25:48.764092 10, 0xFFFF, sum = 0
8229 19:25:48.767098 11, 0xFFFF, sum = 0
8230 19:25:48.767179 12, 0xFFFF, sum = 0
8231 19:25:48.770212 13, 0xFFFF, sum = 0
8232 19:25:48.773491 14, 0x0, sum = 1
8233 19:25:48.773573 15, 0x0, sum = 2
8234 19:25:48.773654 16, 0x0, sum = 3
8235 19:25:48.777125 17, 0x0, sum = 4
8236 19:25:48.777201 best_step = 15
8237 19:25:48.777280
8238 19:25:48.779735 ==
8239 19:25:48.779847 Dram Type= 6, Freq= 0, CH_0, rank 1
8240 19:25:48.786691 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8241 19:25:48.786774 ==
8242 19:25:48.786841 RX Vref Scan: 0
8243 19:25:48.786902
8244 19:25:48.789539 RX Vref 0 -> 0, step: 1
8245 19:25:48.789619
8246 19:25:48.793497 RX Delay 11 -> 252, step: 4
8247 19:25:48.796192 iDelay=191, Bit 0, Center 126 (75 ~ 178) 104
8248 19:25:48.800185 iDelay=191, Bit 1, Center 130 (79 ~ 182) 104
8249 19:25:48.806238 iDelay=191, Bit 2, Center 124 (75 ~ 174) 100
8250 19:25:48.809466 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8251 19:25:48.813042 iDelay=191, Bit 4, Center 132 (83 ~ 182) 100
8252 19:25:48.816002 iDelay=191, Bit 5, Center 118 (63 ~ 174) 112
8253 19:25:48.822780 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8254 19:25:48.826288 iDelay=191, Bit 7, Center 134 (83 ~ 186) 104
8255 19:25:48.829176 iDelay=191, Bit 8, Center 114 (63 ~ 166) 104
8256 19:25:48.832896 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8257 19:25:48.836036 iDelay=191, Bit 10, Center 124 (71 ~ 178) 108
8258 19:25:48.843208 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8259 19:25:48.846101 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8260 19:25:48.849024 iDelay=191, Bit 13, Center 130 (79 ~ 182) 104
8261 19:25:48.852465 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8262 19:25:48.855795 iDelay=191, Bit 15, Center 132 (79 ~ 186) 108
8263 19:25:48.858970 ==
8264 19:25:48.862474 Dram Type= 6, Freq= 0, CH_0, rank 1
8265 19:25:48.865647 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8266 19:25:48.865731 ==
8267 19:25:48.865796 DQS Delay:
8268 19:25:48.868949 DQS0 = 0, DQS1 = 0
8269 19:25:48.869026 DQM Delay:
8270 19:25:48.872907 DQM0 = 128, DQM1 = 124
8271 19:25:48.873012 DQ Delay:
8272 19:25:48.875421 DQ0 =126, DQ1 =130, DQ2 =124, DQ3 =126
8273 19:25:48.878657 DQ4 =132, DQ5 =118, DQ6 =138, DQ7 =134
8274 19:25:48.882006 DQ8 =114, DQ9 =110, DQ10 =124, DQ11 =120
8275 19:25:48.885504 DQ12 =128, DQ13 =130, DQ14 =136, DQ15 =132
8276 19:25:48.885609
8277 19:25:48.885686
8278 19:25:48.885745
8279 19:25:48.888647 [DramC_TX_OE_Calibration] TA2
8280 19:25:48.892092 Original DQ_B0 (3 6) =30, OEN = 27
8281 19:25:48.895282 Original DQ_B1 (3 6) =30, OEN = 27
8282 19:25:48.898603 24, 0x0, End_B0=24 End_B1=24
8283 19:25:48.901723 25, 0x0, End_B0=25 End_B1=25
8284 19:25:48.905318 26, 0x0, End_B0=26 End_B1=26
8285 19:25:48.905400 27, 0x0, End_B0=27 End_B1=27
8286 19:25:48.908246 28, 0x0, End_B0=28 End_B1=28
8287 19:25:48.911373 29, 0x0, End_B0=29 End_B1=29
8288 19:25:48.914840 30, 0x0, End_B0=30 End_B1=30
8289 19:25:48.918180 31, 0x4141, End_B0=30 End_B1=30
8290 19:25:48.918291 Byte0 end_step=30 best_step=27
8291 19:25:48.921547 Byte1 end_step=30 best_step=27
8292 19:25:48.924402 Byte0 TX OE(2T, 0.5T) = (3, 3)
8293 19:25:48.928035 Byte1 TX OE(2T, 0.5T) = (3, 3)
8294 19:25:48.928147
8295 19:25:48.928242
8296 19:25:48.937937 [DQSOSCAuto] RK1, (LSB)MR18= 0x1210, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 400 ps
8297 19:25:48.938049 CH0 RK1: MR19=303, MR18=1210
8298 19:25:48.944174 CH0_RK1: MR19=0x303, MR18=0x1210, DQSOSC=400, MR23=63, INC=23, DEC=15
8299 19:25:48.947461 [RxdqsGatingPostProcess] freq 1600
8300 19:25:48.953970 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8301 19:25:48.957594 best DQS0 dly(2T, 0.5T) = (1, 1)
8302 19:25:48.960565 best DQS1 dly(2T, 0.5T) = (1, 1)
8303 19:25:48.964081 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8304 19:25:48.967240 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8305 19:25:48.967350 best DQS0 dly(2T, 0.5T) = (1, 1)
8306 19:25:48.970733 best DQS1 dly(2T, 0.5T) = (1, 1)
8307 19:25:48.974006 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8308 19:25:48.977149 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8309 19:25:48.980759 Pre-setting of DQS Precalculation
8310 19:25:48.987184 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8311 19:25:48.987267 ==
8312 19:25:48.990147 Dram Type= 6, Freq= 0, CH_1, rank 0
8313 19:25:48.993533 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8314 19:25:48.993678 ==
8315 19:25:49.000334 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8316 19:25:49.003105 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8317 19:25:49.006540 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8318 19:25:49.013068 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8319 19:25:49.022733 [CA 0] Center 41 (12~71) winsize 60
8320 19:25:49.025705 [CA 1] Center 41 (11~72) winsize 62
8321 19:25:49.029284 [CA 2] Center 38 (9~67) winsize 59
8322 19:25:49.032781 [CA 3] Center 37 (8~66) winsize 59
8323 19:25:49.036141 [CA 4] Center 38 (8~68) winsize 61
8324 19:25:49.039421 [CA 5] Center 36 (7~66) winsize 60
8325 19:25:49.039505
8326 19:25:49.042204 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8327 19:25:49.042386
8328 19:25:49.048957 [CATrainingPosCal] consider 1 rank data
8329 19:25:49.049044 u2DelayCellTimex100 = 275/100 ps
8330 19:25:49.052496 CA0 delay=41 (12~71),Diff = 5 PI (17 cell)
8331 19:25:49.058691 CA1 delay=41 (11~72),Diff = 5 PI (17 cell)
8332 19:25:49.062415 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8333 19:25:49.065600 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8334 19:25:49.068904 CA4 delay=38 (8~68),Diff = 2 PI (7 cell)
8335 19:25:49.072263 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8336 19:25:49.072364
8337 19:25:49.075287 CA PerBit enable=1, Macro0, CA PI delay=36
8338 19:25:49.075363
8339 19:25:49.078479 [CBTSetCACLKResult] CA Dly = 36
8340 19:25:49.081930 CS Dly: 7 (0~38)
8341 19:25:49.084958 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8342 19:25:49.088670 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8343 19:25:49.088818 ==
8344 19:25:49.092063 Dram Type= 6, Freq= 0, CH_1, rank 1
8345 19:25:49.098110 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8346 19:25:49.098205 ==
8347 19:25:49.101770 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8348 19:25:49.108163 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8349 19:25:49.111244 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8350 19:25:49.117834 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8351 19:25:49.125872 [CA 0] Center 42 (12~72) winsize 61
8352 19:25:49.129272 [CA 1] Center 43 (14~72) winsize 59
8353 19:25:49.132114 [CA 2] Center 38 (9~68) winsize 60
8354 19:25:49.135617 [CA 3] Center 37 (8~66) winsize 59
8355 19:25:49.138954 [CA 4] Center 38 (8~68) winsize 61
8356 19:25:49.142256 [CA 5] Center 37 (8~67) winsize 60
8357 19:25:49.142339
8358 19:25:49.145138 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8359 19:25:49.145214
8360 19:25:49.151959 [CATrainingPosCal] consider 2 rank data
8361 19:25:49.152072 u2DelayCellTimex100 = 275/100 ps
8362 19:25:49.158671 CA0 delay=41 (12~71),Diff = 4 PI (14 cell)
8363 19:25:49.161901 CA1 delay=43 (14~72),Diff = 6 PI (21 cell)
8364 19:25:49.165052 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8365 19:25:49.168171 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8366 19:25:49.171768 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
8367 19:25:49.174957 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8368 19:25:49.175042
8369 19:25:49.178273 CA PerBit enable=1, Macro0, CA PI delay=37
8370 19:25:49.178357
8371 19:25:49.181544 [CBTSetCACLKResult] CA Dly = 37
8372 19:25:49.184960 CS Dly: 9 (0~42)
8373 19:25:49.188241 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8374 19:25:49.191520 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8375 19:25:49.191602
8376 19:25:49.195119 ----->DramcWriteLeveling(PI) begin...
8377 19:25:49.195206 ==
8378 19:25:49.197693 Dram Type= 6, Freq= 0, CH_1, rank 0
8379 19:25:49.205059 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8380 19:25:49.205144 ==
8381 19:25:49.207608 Write leveling (Byte 0): 25 => 25
8382 19:25:49.211137 Write leveling (Byte 1): 25 => 25
8383 19:25:49.214799 DramcWriteLeveling(PI) end<-----
8384 19:25:49.214881
8385 19:25:49.214944 ==
8386 19:25:49.217724 Dram Type= 6, Freq= 0, CH_1, rank 0
8387 19:25:49.221097 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8388 19:25:49.221179 ==
8389 19:25:49.224257 [Gating] SW mode calibration
8390 19:25:49.231064 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8391 19:25:49.237687 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8392 19:25:49.241013 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8393 19:25:49.244191 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8394 19:25:49.250657 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8395 19:25:49.253858 1 4 12 | B1->B0 | 2424 2f2f | 0 0 | (0 0) (0 0)
8396 19:25:49.257319 1 4 16 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8397 19:25:49.263597 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8398 19:25:49.266971 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8399 19:25:49.270542 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8400 19:25:49.277149 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8401 19:25:49.280032 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8402 19:25:49.283496 1 5 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
8403 19:25:49.290282 1 5 12 | B1->B0 | 2b2b 2323 | 0 0 | (0 1) (1 0)
8404 19:25:49.293391 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8405 19:25:49.296602 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8406 19:25:49.303207 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8407 19:25:49.306550 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8408 19:25:49.309841 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8409 19:25:49.316586 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8410 19:25:49.319946 1 6 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8411 19:25:49.323033 1 6 12 | B1->B0 | 2929 4444 | 0 0 | (0 0) (0 0)
8412 19:25:49.329937 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8413 19:25:49.333258 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8414 19:25:49.336683 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8415 19:25:49.342750 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8416 19:25:49.346552 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8417 19:25:49.349396 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8418 19:25:49.355954 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8419 19:25:49.359388 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8420 19:25:49.362702 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8421 19:25:49.369373 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8422 19:25:49.372524 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8423 19:25:49.375666 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8424 19:25:49.382345 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8425 19:25:49.386027 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8426 19:25:49.389149 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8427 19:25:49.395607 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8428 19:25:49.398936 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8429 19:25:49.402219 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8430 19:25:49.409006 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8431 19:25:49.411899 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8432 19:25:49.415331 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8433 19:25:49.422313 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8434 19:25:49.425472 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8435 19:25:49.428393 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8436 19:25:49.435084 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8437 19:25:49.435169 Total UI for P1: 0, mck2ui 16
8438 19:25:49.441752 best dqsien dly found for B0: ( 1, 9, 10)
8439 19:25:49.444984 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8440 19:25:49.448007 Total UI for P1: 0, mck2ui 16
8441 19:25:49.451510 best dqsien dly found for B1: ( 1, 9, 14)
8442 19:25:49.454840 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8443 19:25:49.457917 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8444 19:25:49.457998
8445 19:25:49.461742 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8446 19:25:49.464496 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8447 19:25:49.468480 [Gating] SW calibration Done
8448 19:25:49.468642 ==
8449 19:25:49.471396 Dram Type= 6, Freq= 0, CH_1, rank 0
8450 19:25:49.477747 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8451 19:25:49.477830 ==
8452 19:25:49.477896 RX Vref Scan: 0
8453 19:25:49.477955
8454 19:25:49.481483 RX Vref 0 -> 0, step: 1
8455 19:25:49.481564
8456 19:25:49.484881 RX Delay 0 -> 252, step: 8
8457 19:25:49.487794 iDelay=200, Bit 0, Center 143 (88 ~ 199) 112
8458 19:25:49.491016 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8459 19:25:49.494651 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8460 19:25:49.497540 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8461 19:25:49.504476 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8462 19:25:49.507451 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8463 19:25:49.510832 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8464 19:25:49.513963 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8465 19:25:49.517114 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8466 19:25:49.524295 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8467 19:25:49.527017 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8468 19:25:49.530689 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8469 19:25:49.533741 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8470 19:25:49.540667 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8471 19:25:49.543415 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8472 19:25:49.547128 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8473 19:25:49.547210 ==
8474 19:25:49.550359 Dram Type= 6, Freq= 0, CH_1, rank 0
8475 19:25:49.553604 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8476 19:25:49.553686 ==
8477 19:25:49.557108 DQS Delay:
8478 19:25:49.557188 DQS0 = 0, DQS1 = 0
8479 19:25:49.560079 DQM Delay:
8480 19:25:49.560160 DQM0 = 135, DQM1 = 132
8481 19:25:49.563632 DQ Delay:
8482 19:25:49.566962 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8483 19:25:49.570024 DQ4 =131, DQ5 =143, DQ6 =147, DQ7 =131
8484 19:25:49.573325 DQ8 =115, DQ9 =123, DQ10 =131, DQ11 =127
8485 19:25:49.576373 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139
8486 19:25:49.576457
8487 19:25:49.576520
8488 19:25:49.576580 ==
8489 19:25:49.579768 Dram Type= 6, Freq= 0, CH_1, rank 0
8490 19:25:49.583482 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8491 19:25:49.583565 ==
8492 19:25:49.583628
8493 19:25:49.583687
8494 19:25:49.586810 TX Vref Scan disable
8495 19:25:49.589823 == TX Byte 0 ==
8496 19:25:49.593076 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8497 19:25:49.596207 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8498 19:25:49.599777 == TX Byte 1 ==
8499 19:25:49.602845 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8500 19:25:49.606316 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8501 19:25:49.606399 ==
8502 19:25:49.609388 Dram Type= 6, Freq= 0, CH_1, rank 0
8503 19:25:49.616215 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8504 19:25:49.616297 ==
8505 19:25:49.628698
8506 19:25:49.632184 TX Vref early break, caculate TX vref
8507 19:25:49.635149 TX Vref=16, minBit 9, minWin=21, winSum=366
8508 19:25:49.638976 TX Vref=18, minBit 8, minWin=22, winSum=380
8509 19:25:49.641829 TX Vref=20, minBit 8, minWin=23, winSum=385
8510 19:25:49.645094 TX Vref=22, minBit 8, minWin=23, winSum=401
8511 19:25:49.648019 TX Vref=24, minBit 9, minWin=24, winSum=405
8512 19:25:49.654748 TX Vref=26, minBit 1, minWin=25, winSum=415
8513 19:25:49.658201 TX Vref=28, minBit 3, minWin=25, winSum=419
8514 19:25:49.661458 TX Vref=30, minBit 0, minWin=25, winSum=414
8515 19:25:49.664546 TX Vref=32, minBit 9, minWin=24, winSum=407
8516 19:25:49.667921 TX Vref=34, minBit 0, minWin=24, winSum=399
8517 19:25:49.674231 TX Vref=36, minBit 0, minWin=23, winSum=386
8518 19:25:49.677789 [TxChooseVref] Worse bit 3, Min win 25, Win sum 419, Final Vref 28
8519 19:25:49.677891
8520 19:25:49.681146 Final TX Range 0 Vref 28
8521 19:25:49.681218
8522 19:25:49.681290 ==
8523 19:25:49.684216 Dram Type= 6, Freq= 0, CH_1, rank 0
8524 19:25:49.687424 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8525 19:25:49.690556 ==
8526 19:25:49.690626
8527 19:25:49.690685
8528 19:25:49.690742 TX Vref Scan disable
8529 19:25:49.697592 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8530 19:25:49.697677 == TX Byte 0 ==
8531 19:25:49.701118 u2DelayCellOfst[0]=14 cells (4 PI)
8532 19:25:49.704614 u2DelayCellOfst[1]=10 cells (3 PI)
8533 19:25:49.707355 u2DelayCellOfst[2]=0 cells (0 PI)
8534 19:25:49.710852 u2DelayCellOfst[3]=7 cells (2 PI)
8535 19:25:49.714121 u2DelayCellOfst[4]=10 cells (3 PI)
8536 19:25:49.717627 u2DelayCellOfst[5]=17 cells (5 PI)
8537 19:25:49.720675 u2DelayCellOfst[6]=14 cells (4 PI)
8538 19:25:49.724223 u2DelayCellOfst[7]=7 cells (2 PI)
8539 19:25:49.727430 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8540 19:25:49.731058 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8541 19:25:49.733909 == TX Byte 1 ==
8542 19:25:49.737221 u2DelayCellOfst[8]=0 cells (0 PI)
8543 19:25:49.740061 u2DelayCellOfst[9]=3 cells (1 PI)
8544 19:25:49.743918 u2DelayCellOfst[10]=10 cells (3 PI)
8545 19:25:49.746878 u2DelayCellOfst[11]=3 cells (1 PI)
8546 19:25:49.750421 u2DelayCellOfst[12]=14 cells (4 PI)
8547 19:25:49.753720 u2DelayCellOfst[13]=17 cells (5 PI)
8548 19:25:49.756988 u2DelayCellOfst[14]=17 cells (5 PI)
8549 19:25:49.760043 u2DelayCellOfst[15]=17 cells (5 PI)
8550 19:25:49.763361 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8551 19:25:49.766749 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8552 19:25:49.769978 DramC Write-DBI on
8553 19:25:49.770059 ==
8554 19:25:49.773576 Dram Type= 6, Freq= 0, CH_1, rank 0
8555 19:25:49.776493 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8556 19:25:49.776576 ==
8557 19:25:49.776755
8558 19:25:49.776912
8559 19:25:49.779565 TX Vref Scan disable
8560 19:25:49.783329 == TX Byte 0 ==
8561 19:25:49.786429 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8562 19:25:49.786510 == TX Byte 1 ==
8563 19:25:49.793041 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8564 19:25:49.793124 DramC Write-DBI off
8565 19:25:49.793188
8566 19:25:49.793247 [DATLAT]
8567 19:25:49.796187 Freq=1600, CH1 RK0
8568 19:25:49.796270
8569 19:25:49.799622 DATLAT Default: 0xf
8570 19:25:49.799703 0, 0xFFFF, sum = 0
8571 19:25:49.803153 1, 0xFFFF, sum = 0
8572 19:25:49.803236 2, 0xFFFF, sum = 0
8573 19:25:49.806062 3, 0xFFFF, sum = 0
8574 19:25:49.806142 4, 0xFFFF, sum = 0
8575 19:25:49.809374 5, 0xFFFF, sum = 0
8576 19:25:49.809457 6, 0xFFFF, sum = 0
8577 19:25:49.812806 7, 0xFFFF, sum = 0
8578 19:25:49.812888 8, 0xFFFF, sum = 0
8579 19:25:49.815777 9, 0xFFFF, sum = 0
8580 19:25:49.815859 10, 0xFFFF, sum = 0
8581 19:25:49.819152 11, 0xFFFF, sum = 0
8582 19:25:49.819235 12, 0xFFFF, sum = 0
8583 19:25:49.822776 13, 0xFFFF, sum = 0
8584 19:25:49.822882 14, 0x0, sum = 1
8585 19:25:49.825675 15, 0x0, sum = 2
8586 19:25:49.825789 16, 0x0, sum = 3
8587 19:25:49.829412 17, 0x0, sum = 4
8588 19:25:49.829525 best_step = 15
8589 19:25:49.829589
8590 19:25:49.829647 ==
8591 19:25:49.832463 Dram Type= 6, Freq= 0, CH_1, rank 0
8592 19:25:49.839510 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8593 19:25:49.839621 ==
8594 19:25:49.839713 RX Vref Scan: 1
8595 19:25:49.839801
8596 19:25:49.842568 Set Vref Range= 24 -> 127
8597 19:25:49.842654
8598 19:25:49.845887 RX Vref 24 -> 127, step: 1
8599 19:25:49.845983
8600 19:25:49.848951 RX Delay 19 -> 252, step: 4
8601 19:25:49.849032
8602 19:25:49.852416 Set Vref, RX VrefLevel [Byte0]: 24
8603 19:25:49.855879 [Byte1]: 24
8604 19:25:49.855996
8605 19:25:49.858710 Set Vref, RX VrefLevel [Byte0]: 25
8606 19:25:49.862064 [Byte1]: 25
8607 19:25:49.862145
8608 19:25:49.865462 Set Vref, RX VrefLevel [Byte0]: 26
8609 19:25:49.868513 [Byte1]: 26
8610 19:25:49.872032
8611 19:25:49.872113 Set Vref, RX VrefLevel [Byte0]: 27
8612 19:25:49.875105 [Byte1]: 27
8613 19:25:49.879469
8614 19:25:49.879577 Set Vref, RX VrefLevel [Byte0]: 28
8615 19:25:49.882727 [Byte1]: 28
8616 19:25:49.887339
8617 19:25:49.887422 Set Vref, RX VrefLevel [Byte0]: 29
8618 19:25:49.890644 [Byte1]: 29
8619 19:25:49.895084
8620 19:25:49.895227 Set Vref, RX VrefLevel [Byte0]: 30
8621 19:25:49.898479 [Byte1]: 30
8622 19:25:49.902430
8623 19:25:49.902507 Set Vref, RX VrefLevel [Byte0]: 31
8624 19:25:49.905626 [Byte1]: 31
8625 19:25:49.909680
8626 19:25:49.909777 Set Vref, RX VrefLevel [Byte0]: 32
8627 19:25:49.913139 [Byte1]: 32
8628 19:25:49.917622
8629 19:25:49.917708 Set Vref, RX VrefLevel [Byte0]: 33
8630 19:25:49.920829 [Byte1]: 33
8631 19:25:49.924934
8632 19:25:49.925018 Set Vref, RX VrefLevel [Byte0]: 34
8633 19:25:49.928452 [Byte1]: 34
8634 19:25:49.932621
8635 19:25:49.932696 Set Vref, RX VrefLevel [Byte0]: 35
8636 19:25:49.936068 [Byte1]: 35
8637 19:25:49.940306
8638 19:25:49.943511 Set Vref, RX VrefLevel [Byte0]: 36
8639 19:25:49.946737 [Byte1]: 36
8640 19:25:49.946823
8641 19:25:49.949768 Set Vref, RX VrefLevel [Byte0]: 37
8642 19:25:49.953085 [Byte1]: 37
8643 19:25:49.953171
8644 19:25:49.956528 Set Vref, RX VrefLevel [Byte0]: 38
8645 19:25:49.959623 [Byte1]: 38
8646 19:25:49.959706
8647 19:25:49.963183 Set Vref, RX VrefLevel [Byte0]: 39
8648 19:25:49.966012 [Byte1]: 39
8649 19:25:49.970736
8650 19:25:49.970836 Set Vref, RX VrefLevel [Byte0]: 40
8651 19:25:49.973764 [Byte1]: 40
8652 19:25:49.978235
8653 19:25:49.978308 Set Vref, RX VrefLevel [Byte0]: 41
8654 19:25:49.981346 [Byte1]: 41
8655 19:25:49.985799
8656 19:25:49.985879 Set Vref, RX VrefLevel [Byte0]: 42
8657 19:25:49.989472 [Byte1]: 42
8658 19:25:49.994027
8659 19:25:49.994134 Set Vref, RX VrefLevel [Byte0]: 43
8660 19:25:49.996836 [Byte1]: 43
8661 19:25:50.000790
8662 19:25:50.000927 Set Vref, RX VrefLevel [Byte0]: 44
8663 19:25:50.003735 [Byte1]: 44
8664 19:25:50.008824
8665 19:25:50.008933 Set Vref, RX VrefLevel [Byte0]: 45
8666 19:25:50.011751 [Byte1]: 45
8667 19:25:50.015698
8668 19:25:50.015797 Set Vref, RX VrefLevel [Byte0]: 46
8669 19:25:50.018831 [Byte1]: 46
8670 19:25:50.023389
8671 19:25:50.023490 Set Vref, RX VrefLevel [Byte0]: 47
8672 19:25:50.026628 [Byte1]: 47
8673 19:25:50.030908
8674 19:25:50.030991 Set Vref, RX VrefLevel [Byte0]: 48
8675 19:25:50.034538 [Byte1]: 48
8676 19:25:50.038669
8677 19:25:50.042206 Set Vref, RX VrefLevel [Byte0]: 49
8678 19:25:50.044899 [Byte1]: 49
8679 19:25:50.044978
8680 19:25:50.048215 Set Vref, RX VrefLevel [Byte0]: 50
8681 19:25:50.051565 [Byte1]: 50
8682 19:25:50.051680
8683 19:25:50.054775 Set Vref, RX VrefLevel [Byte0]: 51
8684 19:25:50.058328 [Byte1]: 51
8685 19:25:50.058411
8686 19:25:50.061725 Set Vref, RX VrefLevel [Byte0]: 52
8687 19:25:50.065190 [Byte1]: 52
8688 19:25:50.069081
8689 19:25:50.069161 Set Vref, RX VrefLevel [Byte0]: 53
8690 19:25:50.072253 [Byte1]: 53
8691 19:25:50.076657
8692 19:25:50.076737 Set Vref, RX VrefLevel [Byte0]: 54
8693 19:25:50.079470 [Byte1]: 54
8694 19:25:50.084645
8695 19:25:50.084759 Set Vref, RX VrefLevel [Byte0]: 55
8696 19:25:50.087078 [Byte1]: 55
8697 19:25:50.091736
8698 19:25:50.091819 Set Vref, RX VrefLevel [Byte0]: 56
8699 19:25:50.094738 [Byte1]: 56
8700 19:25:50.099348
8701 19:25:50.099429 Set Vref, RX VrefLevel [Byte0]: 57
8702 19:25:50.102672 [Byte1]: 57
8703 19:25:50.106646
8704 19:25:50.106729 Set Vref, RX VrefLevel [Byte0]: 58
8705 19:25:50.110239 [Byte1]: 58
8706 19:25:50.114310
8707 19:25:50.114391 Set Vref, RX VrefLevel [Byte0]: 59
8708 19:25:50.117490 [Byte1]: 59
8709 19:25:50.121612
8710 19:25:50.121693 Set Vref, RX VrefLevel [Byte0]: 60
8711 19:25:50.125327 [Byte1]: 60
8712 19:25:50.129306
8713 19:25:50.129387 Set Vref, RX VrefLevel [Byte0]: 61
8714 19:25:50.133171 [Byte1]: 61
8715 19:25:50.137117
8716 19:25:50.137198 Set Vref, RX VrefLevel [Byte0]: 62
8717 19:25:50.140362 [Byte1]: 62
8718 19:25:50.144879
8719 19:25:50.144960 Set Vref, RX VrefLevel [Byte0]: 63
8720 19:25:50.148182 [Byte1]: 63
8721 19:25:50.152339
8722 19:25:50.152441 Set Vref, RX VrefLevel [Byte0]: 64
8723 19:25:50.155528 [Byte1]: 64
8724 19:25:50.159616
8725 19:25:50.159697 Set Vref, RX VrefLevel [Byte0]: 65
8726 19:25:50.163034 [Byte1]: 65
8727 19:25:50.167274
8728 19:25:50.167356 Set Vref, RX VrefLevel [Byte0]: 66
8729 19:25:50.170782 [Byte1]: 66
8730 19:25:50.174985
8731 19:25:50.175093 Set Vref, RX VrefLevel [Byte0]: 67
8732 19:25:50.177898 [Byte1]: 67
8733 19:25:50.182546
8734 19:25:50.182630 Set Vref, RX VrefLevel [Byte0]: 68
8735 19:25:50.185565 [Byte1]: 68
8736 19:25:50.189865
8737 19:25:50.189957 Set Vref, RX VrefLevel [Byte0]: 69
8738 19:25:50.193401 [Byte1]: 69
8739 19:25:50.197474
8740 19:25:50.197608 Final RX Vref Byte 0 = 52 to rank0
8741 19:25:50.201301 Final RX Vref Byte 1 = 61 to rank0
8742 19:25:50.204064 Final RX Vref Byte 0 = 52 to rank1
8743 19:25:50.207334 Final RX Vref Byte 1 = 61 to rank1==
8744 19:25:50.210771 Dram Type= 6, Freq= 0, CH_1, rank 0
8745 19:25:50.217675 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8746 19:25:50.217766 ==
8747 19:25:50.217834 DQS Delay:
8748 19:25:50.221133 DQS0 = 0, DQS1 = 0
8749 19:25:50.221232 DQM Delay:
8750 19:25:50.221297 DQM0 = 132, DQM1 = 130
8751 19:25:50.223717 DQ Delay:
8752 19:25:50.227112 DQ0 =138, DQ1 =130, DQ2 =120, DQ3 =132
8753 19:25:50.230414 DQ4 =126, DQ5 =142, DQ6 =144, DQ7 =126
8754 19:25:50.233947 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =122
8755 19:25:50.237104 DQ12 =142, DQ13 =140, DQ14 =136, DQ15 =140
8756 19:25:50.237217
8757 19:25:50.237316
8758 19:25:50.237409
8759 19:25:50.240471 [DramC_TX_OE_Calibration] TA2
8760 19:25:50.243903 Original DQ_B0 (3 6) =30, OEN = 27
8761 19:25:50.246713 Original DQ_B1 (3 6) =30, OEN = 27
8762 19:25:50.249998 24, 0x0, End_B0=24 End_B1=24
8763 19:25:50.253699 25, 0x0, End_B0=25 End_B1=25
8764 19:25:50.253784 26, 0x0, End_B0=26 End_B1=26
8765 19:25:50.257223 27, 0x0, End_B0=27 End_B1=27
8766 19:25:50.259734 28, 0x0, End_B0=28 End_B1=28
8767 19:25:50.263335 29, 0x0, End_B0=29 End_B1=29
8768 19:25:50.263417 30, 0x0, End_B0=30 End_B1=30
8769 19:25:50.266584 31, 0x5151, End_B0=30 End_B1=30
8770 19:25:50.270206 Byte0 end_step=30 best_step=27
8771 19:25:50.273869 Byte1 end_step=30 best_step=27
8772 19:25:50.276637 Byte0 TX OE(2T, 0.5T) = (3, 3)
8773 19:25:50.279798 Byte1 TX OE(2T, 0.5T) = (3, 3)
8774 19:25:50.279939
8775 19:25:50.280006
8776 19:25:50.286427 [DQSOSCAuto] RK0, (LSB)MR18= 0xd17, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 403 ps
8777 19:25:50.289862 CH1 RK0: MR19=303, MR18=D17
8778 19:25:50.295895 CH1_RK0: MR19=0x303, MR18=0xD17, DQSOSC=398, MR23=63, INC=23, DEC=15
8779 19:25:50.296014
8780 19:25:50.299498 ----->DramcWriteLeveling(PI) begin...
8781 19:25:50.299585 ==
8782 19:25:50.302832 Dram Type= 6, Freq= 0, CH_1, rank 1
8783 19:25:50.306085 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8784 19:25:50.306164 ==
8785 19:25:50.309867 Write leveling (Byte 0): 24 => 24
8786 19:25:50.313006 Write leveling (Byte 1): 25 => 25
8787 19:25:50.315711 DramcWriteLeveling(PI) end<-----
8788 19:25:50.315820
8789 19:25:50.315935 ==
8790 19:25:50.319036 Dram Type= 6, Freq= 0, CH_1, rank 1
8791 19:25:50.325720 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8792 19:25:50.325827 ==
8793 19:25:50.325920 [Gating] SW mode calibration
8794 19:25:50.335401 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8795 19:25:50.338899 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8796 19:25:50.342671 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8797 19:25:50.349063 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8798 19:25:50.352111 1 4 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8799 19:25:50.358780 1 4 12 | B1->B0 | 2828 3434 | 1 1 | (0 0) (1 1)
8800 19:25:50.362013 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8801 19:25:50.365502 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8802 19:25:50.371797 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8803 19:25:50.375175 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8804 19:25:50.378524 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8805 19:25:50.385374 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8806 19:25:50.388340 1 5 8 | B1->B0 | 3434 2828 | 1 0 | (1 0) (0 0)
8807 19:25:50.391680 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8808 19:25:50.398590 1 5 16 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
8809 19:25:50.401613 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8810 19:25:50.404789 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8811 19:25:50.411715 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8812 19:25:50.414580 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8813 19:25:50.418106 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8814 19:25:50.421648 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8815 19:25:50.427766 1 6 12 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
8816 19:25:50.431167 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8817 19:25:50.434838 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8818 19:25:50.441138 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8819 19:25:50.444307 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8820 19:25:50.448058 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8821 19:25:50.454143 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8822 19:25:50.457257 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8823 19:25:50.464278 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8824 19:25:50.467336 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8825 19:25:50.470817 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8826 19:25:50.477132 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8827 19:25:50.480457 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8828 19:25:50.483785 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8829 19:25:50.490381 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8830 19:25:50.493834 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8831 19:25:50.496838 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8832 19:25:50.503796 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8833 19:25:50.506901 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8834 19:25:50.510516 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8835 19:25:50.516736 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8836 19:25:50.520440 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8837 19:25:50.523401 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8838 19:25:50.529843 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8839 19:25:50.533443 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8840 19:25:50.536312 Total UI for P1: 0, mck2ui 16
8841 19:25:50.539757 best dqsien dly found for B0: ( 1, 9, 8)
8842 19:25:50.542834 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8843 19:25:50.546664 Total UI for P1: 0, mck2ui 16
8844 19:25:50.549723 best dqsien dly found for B1: ( 1, 9, 10)
8845 19:25:50.552919 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8846 19:25:50.556639 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8847 19:25:50.556721
8848 19:25:50.559619 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8849 19:25:50.566102 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8850 19:25:50.566184 [Gating] SW calibration Done
8851 19:25:50.569425 ==
8852 19:25:50.569506 Dram Type= 6, Freq= 0, CH_1, rank 1
8853 19:25:50.575855 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8854 19:25:50.575972 ==
8855 19:25:50.576037 RX Vref Scan: 0
8856 19:25:50.576097
8857 19:25:50.579190 RX Vref 0 -> 0, step: 1
8858 19:25:50.579271
8859 19:25:50.582577 RX Delay 0 -> 252, step: 8
8860 19:25:50.585620 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8861 19:25:50.589226 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8862 19:25:50.592165 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8863 19:25:50.599120 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8864 19:25:50.602136 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8865 19:25:50.605608 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8866 19:25:50.608636 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8867 19:25:50.612421 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8868 19:25:50.618661 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8869 19:25:50.621829 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8870 19:25:50.625760 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8871 19:25:50.628421 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8872 19:25:50.635028 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8873 19:25:50.638537 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8874 19:25:50.641830 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8875 19:25:50.644936 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8876 19:25:50.645020 ==
8877 19:25:50.648661 Dram Type= 6, Freq= 0, CH_1, rank 1
8878 19:25:50.655063 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8879 19:25:50.655147 ==
8880 19:25:50.655232 DQS Delay:
8881 19:25:50.658153 DQS0 = 0, DQS1 = 0
8882 19:25:50.658250 DQM Delay:
8883 19:25:50.661640 DQM0 = 134, DQM1 = 130
8884 19:25:50.661722 DQ Delay:
8885 19:25:50.664835 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =131
8886 19:25:50.668214 DQ4 =135, DQ5 =143, DQ6 =143, DQ7 =131
8887 19:25:50.671027 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8888 19:25:50.674685 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8889 19:25:50.674768
8890 19:25:50.674851
8891 19:25:50.674929 ==
8892 19:25:50.677892 Dram Type= 6, Freq= 0, CH_1, rank 1
8893 19:25:50.684577 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8894 19:25:50.684660 ==
8895 19:25:50.684746
8896 19:25:50.684824
8897 19:25:50.684901 TX Vref Scan disable
8898 19:25:50.687809 == TX Byte 0 ==
8899 19:25:50.691156 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8900 19:25:50.697693 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8901 19:25:50.697799 == TX Byte 1 ==
8902 19:25:50.701129 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8903 19:25:50.707676 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8904 19:25:50.707772 ==
8905 19:25:50.710860 Dram Type= 6, Freq= 0, CH_1, rank 1
8906 19:25:50.713865 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8907 19:25:50.714034 ==
8908 19:25:50.727433
8909 19:25:50.730764 TX Vref early break, caculate TX vref
8910 19:25:50.734083 TX Vref=16, minBit 13, minWin=22, winSum=380
8911 19:25:50.737633 TX Vref=18, minBit 9, minWin=22, winSum=387
8912 19:25:50.740678 TX Vref=20, minBit 9, minWin=22, winSum=395
8913 19:25:50.744321 TX Vref=22, minBit 9, minWin=23, winSum=397
8914 19:25:50.747590 TX Vref=24, minBit 9, minWin=23, winSum=405
8915 19:25:50.753766 TX Vref=26, minBit 9, minWin=24, winSum=414
8916 19:25:50.757374 TX Vref=28, minBit 1, minWin=25, winSum=421
8917 19:25:50.761002 TX Vref=30, minBit 5, minWin=25, winSum=420
8918 19:25:50.763840 TX Vref=32, minBit 0, minWin=24, winSum=409
8919 19:25:50.767124 TX Vref=34, minBit 9, minWin=23, winSum=402
8920 19:25:50.773629 TX Vref=36, minBit 9, minWin=23, winSum=398
8921 19:25:50.776862 [TxChooseVref] Worse bit 1, Min win 25, Win sum 421, Final Vref 28
8922 19:25:50.776944
8923 19:25:50.780612 Final TX Range 0 Vref 28
8924 19:25:50.780694
8925 19:25:50.780793 ==
8926 19:25:50.783528 Dram Type= 6, Freq= 0, CH_1, rank 1
8927 19:25:50.786928 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8928 19:25:50.790343 ==
8929 19:25:50.790424
8930 19:25:50.790488
8931 19:25:50.790546 TX Vref Scan disable
8932 19:25:50.797140 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8933 19:25:50.797222 == TX Byte 0 ==
8934 19:25:50.800256 u2DelayCellOfst[0]=14 cells (4 PI)
8935 19:25:50.803774 u2DelayCellOfst[1]=10 cells (3 PI)
8936 19:25:50.806581 u2DelayCellOfst[2]=0 cells (0 PI)
8937 19:25:50.810151 u2DelayCellOfst[3]=7 cells (2 PI)
8938 19:25:50.813227 u2DelayCellOfst[4]=7 cells (2 PI)
8939 19:25:50.816728 u2DelayCellOfst[5]=14 cells (4 PI)
8940 19:25:50.819571 u2DelayCellOfst[6]=14 cells (4 PI)
8941 19:25:50.823667 u2DelayCellOfst[7]=7 cells (2 PI)
8942 19:25:50.826605 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8943 19:25:50.829573 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8944 19:25:50.833123 == TX Byte 1 ==
8945 19:25:50.836216 u2DelayCellOfst[8]=0 cells (0 PI)
8946 19:25:50.839565 u2DelayCellOfst[9]=3 cells (1 PI)
8947 19:25:50.843011 u2DelayCellOfst[10]=10 cells (3 PI)
8948 19:25:50.846506 u2DelayCellOfst[11]=7 cells (2 PI)
8949 19:25:50.849434 u2DelayCellOfst[12]=10 cells (3 PI)
8950 19:25:50.852546 u2DelayCellOfst[13]=14 cells (4 PI)
8951 19:25:50.856221 u2DelayCellOfst[14]=17 cells (5 PI)
8952 19:25:50.856303 u2DelayCellOfst[15]=17 cells (5 PI)
8953 19:25:50.862574 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8954 19:25:50.866228 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8955 19:25:50.868977 DramC Write-DBI on
8956 19:25:50.869076 ==
8957 19:25:50.872500 Dram Type= 6, Freq= 0, CH_1, rank 1
8958 19:25:50.876312 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8959 19:25:50.876394 ==
8960 19:25:50.876459
8961 19:25:50.876517
8962 19:25:50.879516 TX Vref Scan disable
8963 19:25:50.879596 == TX Byte 0 ==
8964 19:25:50.885863 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8965 19:25:50.885944 == TX Byte 1 ==
8966 19:25:50.889089 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8967 19:25:50.892442 DramC Write-DBI off
8968 19:25:50.892523
8969 19:25:50.892586 [DATLAT]
8970 19:25:50.895619 Freq=1600, CH1 RK1
8971 19:25:50.895699
8972 19:25:50.895763 DATLAT Default: 0xf
8973 19:25:50.898981 0, 0xFFFF, sum = 0
8974 19:25:50.899066 1, 0xFFFF, sum = 0
8975 19:25:50.902695 2, 0xFFFF, sum = 0
8976 19:25:50.905730 3, 0xFFFF, sum = 0
8977 19:25:50.905813 4, 0xFFFF, sum = 0
8978 19:25:50.908846 5, 0xFFFF, sum = 0
8979 19:25:50.908931 6, 0xFFFF, sum = 0
8980 19:25:50.912317 7, 0xFFFF, sum = 0
8981 19:25:50.912402 8, 0xFFFF, sum = 0
8982 19:25:50.915573 9, 0xFFFF, sum = 0
8983 19:25:50.915674 10, 0xFFFF, sum = 0
8984 19:25:50.919158 11, 0xFFFF, sum = 0
8985 19:25:50.919242 12, 0xFFFF, sum = 0
8986 19:25:50.922162 13, 0xFFFF, sum = 0
8987 19:25:50.922271 14, 0x0, sum = 1
8988 19:25:50.925735 15, 0x0, sum = 2
8989 19:25:50.925819 16, 0x0, sum = 3
8990 19:25:50.929074 17, 0x0, sum = 4
8991 19:25:50.929158 best_step = 15
8992 19:25:50.929241
8993 19:25:50.929319 ==
8994 19:25:50.931999 Dram Type= 6, Freq= 0, CH_1, rank 1
8995 19:25:50.938558 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8996 19:25:50.938666 ==
8997 19:25:50.938751 RX Vref Scan: 0
8998 19:25:50.938830
8999 19:25:50.942329 RX Vref 0 -> 0, step: 1
9000 19:25:50.942436
9001 19:25:50.945512 RX Delay 19 -> 252, step: 4
9002 19:25:50.948555 iDelay=195, Bit 0, Center 136 (87 ~ 186) 100
9003 19:25:50.951802 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
9004 19:25:50.955330 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
9005 19:25:50.961642 iDelay=195, Bit 3, Center 130 (79 ~ 182) 104
9006 19:25:50.965119 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
9007 19:25:50.968576 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
9008 19:25:50.971685 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
9009 19:25:50.974780 iDelay=195, Bit 7, Center 130 (79 ~ 182) 104
9010 19:25:50.981153 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
9011 19:25:50.984528 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9012 19:25:50.988553 iDelay=195, Bit 10, Center 130 (75 ~ 186) 112
9013 19:25:50.991545 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9014 19:25:50.997915 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
9015 19:25:51.001295 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
9016 19:25:51.004290 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
9017 19:25:51.007830 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
9018 19:25:51.007934 ==
9019 19:25:51.011211 Dram Type= 6, Freq= 0, CH_1, rank 1
9020 19:25:51.017304 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9021 19:25:51.017416 ==
9022 19:25:51.017496 DQS Delay:
9023 19:25:51.021089 DQS0 = 0, DQS1 = 0
9024 19:25:51.021230 DQM Delay:
9025 19:25:51.021371 DQM0 = 132, DQM1 = 128
9026 19:25:51.024254 DQ Delay:
9027 19:25:51.027648 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =130
9028 19:25:51.030740 DQ4 =132, DQ5 =144, DQ6 =138, DQ7 =130
9029 19:25:51.034202 DQ8 =114, DQ9 =118, DQ10 =130, DQ11 =120
9030 19:25:51.037726 DQ12 =136, DQ13 =136, DQ14 =132, DQ15 =138
9031 19:25:51.037808
9032 19:25:51.037871
9033 19:25:51.037930
9034 19:25:51.041031 [DramC_TX_OE_Calibration] TA2
9035 19:25:51.044810 Original DQ_B0 (3 6) =30, OEN = 27
9036 19:25:51.047334 Original DQ_B1 (3 6) =30, OEN = 27
9037 19:25:51.050626 24, 0x0, End_B0=24 End_B1=24
9038 19:25:51.050709 25, 0x0, End_B0=25 End_B1=25
9039 19:25:51.054297 26, 0x0, End_B0=26 End_B1=26
9040 19:25:51.057315 27, 0x0, End_B0=27 End_B1=27
9041 19:25:51.060629 28, 0x0, End_B0=28 End_B1=28
9042 19:25:51.063586 29, 0x0, End_B0=29 End_B1=29
9043 19:25:51.063698 30, 0x0, End_B0=30 End_B1=30
9044 19:25:51.067296 31, 0x4141, End_B0=30 End_B1=30
9045 19:25:51.070557 Byte0 end_step=30 best_step=27
9046 19:25:51.073738 Byte1 end_step=30 best_step=27
9047 19:25:51.077152 Byte0 TX OE(2T, 0.5T) = (3, 3)
9048 19:25:51.080332 Byte1 TX OE(2T, 0.5T) = (3, 3)
9049 19:25:51.080413
9050 19:25:51.080478
9051 19:25:51.086808 [DQSOSCAuto] RK1, (LSB)MR18= 0x111e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 401 ps
9052 19:25:51.089994 CH1 RK1: MR19=303, MR18=111E
9053 19:25:51.096722 CH1_RK1: MR19=0x303, MR18=0x111E, DQSOSC=394, MR23=63, INC=23, DEC=15
9054 19:25:51.100167 [RxdqsGatingPostProcess] freq 1600
9055 19:25:51.106295 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9056 19:25:51.106440 best DQS0 dly(2T, 0.5T) = (1, 1)
9057 19:25:51.110024 best DQS1 dly(2T, 0.5T) = (1, 1)
9058 19:25:51.113331 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9059 19:25:51.116411 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9060 19:25:51.120193 best DQS0 dly(2T, 0.5T) = (1, 1)
9061 19:25:51.123012 best DQS1 dly(2T, 0.5T) = (1, 1)
9062 19:25:51.126421 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9063 19:25:51.129858 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9064 19:25:51.132803 Pre-setting of DQS Precalculation
9065 19:25:51.136087 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9066 19:25:51.146433 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9067 19:25:51.152889 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9068 19:25:51.152978
9069 19:25:51.153042
9070 19:25:51.155899 [Calibration Summary] 3200 Mbps
9071 19:25:51.155981 CH 0, Rank 0
9072 19:25:51.159158 SW Impedance : PASS
9073 19:25:51.159239 DUTY Scan : NO K
9074 19:25:51.162863 ZQ Calibration : PASS
9075 19:25:51.166219 Jitter Meter : NO K
9076 19:25:51.166301 CBT Training : PASS
9077 19:25:51.169559 Write leveling : PASS
9078 19:25:51.172310 RX DQS gating : PASS
9079 19:25:51.172392 RX DQ/DQS(RDDQC) : PASS
9080 19:25:51.176030 TX DQ/DQS : PASS
9081 19:25:51.179306 RX DATLAT : PASS
9082 19:25:51.179387 RX DQ/DQS(Engine): PASS
9083 19:25:51.182570 TX OE : PASS
9084 19:25:51.182652 All Pass.
9085 19:25:51.182717
9086 19:25:51.185612 CH 0, Rank 1
9087 19:25:51.185694 SW Impedance : PASS
9088 19:25:51.189201 DUTY Scan : NO K
9089 19:25:51.191939 ZQ Calibration : PASS
9090 19:25:51.192020 Jitter Meter : NO K
9091 19:25:51.195939 CBT Training : PASS
9092 19:25:51.199420 Write leveling : PASS
9093 19:25:51.199503 RX DQS gating : PASS
9094 19:25:51.202239 RX DQ/DQS(RDDQC) : PASS
9095 19:25:51.205296 TX DQ/DQS : PASS
9096 19:25:51.205378 RX DATLAT : PASS
9097 19:25:51.208731 RX DQ/DQS(Engine): PASS
9098 19:25:51.211953 TX OE : PASS
9099 19:25:51.212036 All Pass.
9100 19:25:51.212100
9101 19:25:51.212161 CH 1, Rank 0
9102 19:25:51.215104 SW Impedance : PASS
9103 19:25:51.218174 DUTY Scan : NO K
9104 19:25:51.218256 ZQ Calibration : PASS
9105 19:25:51.221686 Jitter Meter : NO K
9106 19:25:51.224812 CBT Training : PASS
9107 19:25:51.224894 Write leveling : PASS
9108 19:25:51.228629 RX DQS gating : PASS
9109 19:25:51.228711 RX DQ/DQS(RDDQC) : PASS
9110 19:25:51.231587 TX DQ/DQS : PASS
9111 19:25:51.235341 RX DATLAT : PASS
9112 19:25:51.235423 RX DQ/DQS(Engine): PASS
9113 19:25:51.238340 TX OE : PASS
9114 19:25:51.238422 All Pass.
9115 19:25:51.238486
9116 19:25:51.241461 CH 1, Rank 1
9117 19:25:51.241543 SW Impedance : PASS
9118 19:25:51.244610 DUTY Scan : NO K
9119 19:25:51.248140 ZQ Calibration : PASS
9120 19:25:51.248223 Jitter Meter : NO K
9121 19:25:51.251491 CBT Training : PASS
9122 19:25:51.255027 Write leveling : PASS
9123 19:25:51.255110 RX DQS gating : PASS
9124 19:25:51.258329 RX DQ/DQS(RDDQC) : PASS
9125 19:25:51.261510 TX DQ/DQS : PASS
9126 19:25:51.261594 RX DATLAT : PASS
9127 19:25:51.264831 RX DQ/DQS(Engine): PASS
9128 19:25:51.267998 TX OE : PASS
9129 19:25:51.268080 All Pass.
9130 19:25:51.268144
9131 19:25:51.270973 DramC Write-DBI on
9132 19:25:51.271054 PER_BANK_REFRESH: Hybrid Mode
9133 19:25:51.274300 TX_TRACKING: ON
9134 19:25:51.284266 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9135 19:25:51.291073 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9136 19:25:51.297632 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9137 19:25:51.300810 [FAST_K] Save calibration result to emmc
9138 19:25:51.304263 sync common calibartion params.
9139 19:25:51.307632 sync cbt_mode0:1, 1:1
9140 19:25:51.307716 dram_init: ddr_geometry: 2
9141 19:25:51.310677 dram_init: ddr_geometry: 2
9142 19:25:51.314063 dram_init: ddr_geometry: 2
9143 19:25:51.317338 0:dram_rank_size:100000000
9144 19:25:51.317425 1:dram_rank_size:100000000
9145 19:25:51.323754 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9146 19:25:51.326940 DFS_SHUFFLE_HW_MODE: ON
9147 19:25:51.330294 dramc_set_vcore_voltage set vcore to 725000
9148 19:25:51.333609 Read voltage for 1600, 0
9149 19:25:51.333718 Vio18 = 0
9150 19:25:51.333838 Vcore = 725000
9151 19:25:51.336594 Vdram = 0
9152 19:25:51.336678 Vddq = 0
9153 19:25:51.336742 Vmddr = 0
9154 19:25:51.339936 switch to 3200 Mbps bootup
9155 19:25:51.340018 [DramcRunTimeConfig]
9156 19:25:51.343326 PHYPLL
9157 19:25:51.343453 DPM_CONTROL_AFTERK: ON
9158 19:25:51.346497 PER_BANK_REFRESH: ON
9159 19:25:51.349610 REFRESH_OVERHEAD_REDUCTION: ON
9160 19:25:51.349708 CMD_PICG_NEW_MODE: OFF
9161 19:25:51.353400 XRTWTW_NEW_MODE: ON
9162 19:25:51.353503 XRTRTR_NEW_MODE: ON
9163 19:25:51.356275 TX_TRACKING: ON
9164 19:25:51.356352 RDSEL_TRACKING: OFF
9165 19:25:51.359614 DQS Precalculation for DVFS: ON
9166 19:25:51.363314 RX_TRACKING: OFF
9167 19:25:51.363412 HW_GATING DBG: ON
9168 19:25:51.366563 ZQCS_ENABLE_LP4: ON
9169 19:25:51.366664 RX_PICG_NEW_MODE: ON
9170 19:25:51.369749 TX_PICG_NEW_MODE: ON
9171 19:25:51.372843 ENABLE_RX_DCM_DPHY: ON
9172 19:25:51.376043 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9173 19:25:51.376120 DUMMY_READ_FOR_TRACKING: OFF
9174 19:25:51.379248 !!! SPM_CONTROL_AFTERK: OFF
9175 19:25:51.382574 !!! SPM could not control APHY
9176 19:25:51.386421 IMPEDANCE_TRACKING: ON
9177 19:25:51.386518 TEMP_SENSOR: ON
9178 19:25:51.389844 HW_SAVE_FOR_SR: OFF
9179 19:25:51.389915 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9180 19:25:51.395870 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9181 19:25:51.395997 Read ODT Tracking: ON
9182 19:25:51.399385 Refresh Rate DeBounce: ON
9183 19:25:51.402825 DFS_NO_QUEUE_FLUSH: ON
9184 19:25:51.405818 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9185 19:25:51.405902 ENABLE_DFS_RUNTIME_MRW: OFF
9186 19:25:51.409242 DDR_RESERVE_NEW_MODE: ON
9187 19:25:51.412565 MR_CBT_SWITCH_FREQ: ON
9188 19:25:51.412676 =========================
9189 19:25:51.432193 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9190 19:25:51.435366 dram_init: ddr_geometry: 2
9191 19:25:51.453758 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9192 19:25:51.456951 dram_init: dram init end (result: 0)
9193 19:25:51.464364 DRAM-K: Full calibration passed in 24453 msecs
9194 19:25:51.466766 MRC: failed to locate region type 0.
9195 19:25:51.466874 DRAM rank0 size:0x100000000,
9196 19:25:51.470165 DRAM rank1 size=0x100000000
9197 19:25:51.480665 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9198 19:25:51.486556 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9199 19:25:51.493822 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9200 19:25:51.503617 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9201 19:25:51.503746 DRAM rank0 size:0x100000000,
9202 19:25:51.506643 DRAM rank1 size=0x100000000
9203 19:25:51.506726 CBMEM:
9204 19:25:51.509686 IMD: root @ 0xfffff000 254 entries.
9205 19:25:51.513254 IMD: root @ 0xffffec00 62 entries.
9206 19:25:51.516387 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9207 19:25:51.522835 WARNING: RO_VPD is uninitialized or empty.
9208 19:25:51.525886 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9209 19:25:51.533577 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9210 19:25:51.546608 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9211 19:25:51.558148 BS: romstage times (exec / console): total (unknown) / 23982 ms
9212 19:25:51.558274
9213 19:25:51.558346
9214 19:25:51.567602 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9215 19:25:51.570974 ARM64: Exception handlers installed.
9216 19:25:51.574535 ARM64: Testing exception
9217 19:25:51.578126 ARM64: Done test exception
9218 19:25:51.578223 Enumerating buses...
9219 19:25:51.581092 Show all devs... Before device enumeration.
9220 19:25:51.584648 Root Device: enabled 1
9221 19:25:51.587582 CPU_CLUSTER: 0: enabled 1
9222 19:25:51.587669 CPU: 00: enabled 1
9223 19:25:51.591208 Compare with tree...
9224 19:25:51.591293 Root Device: enabled 1
9225 19:25:51.594007 CPU_CLUSTER: 0: enabled 1
9226 19:25:51.597398 CPU: 00: enabled 1
9227 19:25:51.597485 Root Device scanning...
9228 19:25:51.600841 scan_static_bus for Root Device
9229 19:25:51.604403 CPU_CLUSTER: 0 enabled
9230 19:25:51.607137 scan_static_bus for Root Device done
9231 19:25:51.610922 scan_bus: bus Root Device finished in 8 msecs
9232 19:25:51.611026 done
9233 19:25:51.617296 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9234 19:25:51.620594 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9235 19:25:51.627232 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9236 19:25:51.630421 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9237 19:25:51.633638 Allocating resources...
9238 19:25:51.637121 Reading resources...
9239 19:25:51.640185 Root Device read_resources bus 0 link: 0
9240 19:25:51.643923 DRAM rank0 size:0x100000000,
9241 19:25:51.644045 DRAM rank1 size=0x100000000
9242 19:25:51.650644 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9243 19:25:51.650754 CPU: 00 missing read_resources
9244 19:25:51.656895 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9245 19:25:51.660750 Root Device read_resources bus 0 link: 0 done
9246 19:25:51.663393 Done reading resources.
9247 19:25:51.666542 Show resources in subtree (Root Device)...After reading.
9248 19:25:51.669962 Root Device child on link 0 CPU_CLUSTER: 0
9249 19:25:51.673348 CPU_CLUSTER: 0 child on link 0 CPU: 00
9250 19:25:51.683419 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9251 19:25:51.683517 CPU: 00
9252 19:25:51.689633 Root Device assign_resources, bus 0 link: 0
9253 19:25:51.692985 CPU_CLUSTER: 0 missing set_resources
9254 19:25:51.696211 Root Device assign_resources, bus 0 link: 0 done
9255 19:25:51.696323 Done setting resources.
9256 19:25:51.702719 Show resources in subtree (Root Device)...After assigning values.
9257 19:25:51.706377 Root Device child on link 0 CPU_CLUSTER: 0
9258 19:25:51.712777 CPU_CLUSTER: 0 child on link 0 CPU: 00
9259 19:25:51.719299 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9260 19:25:51.722755 CPU: 00
9261 19:25:51.722897 Done allocating resources.
9262 19:25:51.729172 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9263 19:25:51.729291 Enabling resources...
9264 19:25:51.732414 done.
9265 19:25:51.735440 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9266 19:25:51.738927 Initializing devices...
9267 19:25:51.739046 Root Device init
9268 19:25:51.742329 init hardware done!
9269 19:25:51.742411 0x00000018: ctrlr->caps
9270 19:25:51.745639 52.000 MHz: ctrlr->f_max
9271 19:25:51.748959 0.400 MHz: ctrlr->f_min
9272 19:25:51.751879 0x40ff8080: ctrlr->voltages
9273 19:25:51.752016 sclk: 390625
9274 19:25:51.752084 Bus Width = 1
9275 19:25:51.755667 sclk: 390625
9276 19:25:51.755758 Bus Width = 1
9277 19:25:51.758952 Early init status = 3
9278 19:25:51.761968 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9279 19:25:51.765834 in-header: 03 fc 00 00 01 00 00 00
9280 19:25:51.768703 in-data: 00
9281 19:25:51.772080 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9282 19:25:51.777486 in-header: 03 fd 00 00 00 00 00 00
9283 19:25:51.780674 in-data:
9284 19:25:51.784078 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9285 19:25:51.788404 in-header: 03 fc 00 00 01 00 00 00
9286 19:25:51.791947 in-data: 00
9287 19:25:51.795381 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9288 19:25:51.800532 in-header: 03 fd 00 00 00 00 00 00
9289 19:25:51.804044 in-data:
9290 19:25:51.807163 [SSUSB] Setting up USB HOST controller...
9291 19:25:51.810442 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9292 19:25:51.814132 [SSUSB] phy power-on done.
9293 19:25:51.817386 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9294 19:25:51.823862 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9295 19:25:51.827205 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9296 19:25:51.833672 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9297 19:25:51.840962 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9298 19:25:51.846711 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9299 19:25:51.853581 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9300 19:25:51.860162 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9301 19:25:51.863476 SPM: binary array size = 0x9dc
9302 19:25:51.866893 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9303 19:25:51.873284 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9304 19:25:51.880145 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9305 19:25:51.886920 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9306 19:25:51.889828 configure_display: Starting display init
9307 19:25:51.923871 anx7625_power_on_init: Init interface.
9308 19:25:51.927255 anx7625_disable_pd_protocol: Disabled PD feature.
9309 19:25:51.930737 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9310 19:25:51.958130 anx7625_start_dp_work: Secure OCM version=00
9311 19:25:51.961363 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9312 19:25:51.976208 sp_tx_get_edid_block: EDID Block = 1
9313 19:25:52.079080 Extracted contents:
9314 19:25:52.082435 header: 00 ff ff ff ff ff ff 00
9315 19:25:52.085763 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9316 19:25:52.088912 version: 01 04
9317 19:25:52.092151 basic params: 95 1f 11 78 0a
9318 19:25:52.095825 chroma info: 76 90 94 55 54 90 27 21 50 54
9319 19:25:52.098619 established: 00 00 00
9320 19:25:52.105301 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9321 19:25:52.111586 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9322 19:25:52.115385 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9323 19:25:52.121821 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9324 19:25:52.128468 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9325 19:25:52.131750 extensions: 00
9326 19:25:52.131872 checksum: fb
9327 19:25:52.131979
9328 19:25:52.138432 Manufacturer: IVO Model 57d Serial Number 0
9329 19:25:52.138535 Made week 0 of 2020
9330 19:25:52.141504 EDID version: 1.4
9331 19:25:52.141604 Digital display
9332 19:25:52.144990 6 bits per primary color channel
9333 19:25:52.148565 DisplayPort interface
9334 19:25:52.148656 Maximum image size: 31 cm x 17 cm
9335 19:25:52.151235 Gamma: 220%
9336 19:25:52.151358 Check DPMS levels
9337 19:25:52.158018 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9338 19:25:52.160951 First detailed timing is preferred timing
9339 19:25:52.164432 Established timings supported:
9340 19:25:52.164523 Standard timings supported:
9341 19:25:52.168317 Detailed timings
9342 19:25:52.171222 Hex of detail: 383680a07038204018303c0035ae10000019
9343 19:25:52.177642 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9344 19:25:52.181627 0780 0798 07c8 0820 hborder 0
9345 19:25:52.184110 0438 043b 0447 0458 vborder 0
9346 19:25:52.187511 -hsync -vsync
9347 19:25:52.187628 Did detailed timing
9348 19:25:52.194603 Hex of detail: 000000000000000000000000000000000000
9349 19:25:52.197435 Manufacturer-specified data, tag 0
9350 19:25:52.200714 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9351 19:25:52.204216 ASCII string: InfoVision
9352 19:25:52.207169 Hex of detail: 000000fe00523134304e574635205248200a
9353 19:25:52.211107 ASCII string: R140NWF5 RH
9354 19:25:52.211218 Checksum
9355 19:25:52.214546 Checksum: 0xfb (valid)
9356 19:25:52.217001 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9357 19:25:52.221033 DSI data_rate: 832800000 bps
9358 19:25:52.227110 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9359 19:25:52.230252 anx7625_parse_edid: pixelclock(138800).
9360 19:25:52.233520 hactive(1920), hsync(48), hfp(24), hbp(88)
9361 19:25:52.236833 vactive(1080), vsync(12), vfp(3), vbp(17)
9362 19:25:52.240184 anx7625_dsi_config: config dsi.
9363 19:25:52.246818 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9364 19:25:52.261018 anx7625_dsi_config: success to config DSI
9365 19:25:52.264278 anx7625_dp_start: MIPI phy setup OK.
9366 19:25:52.267878 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9367 19:25:52.270609 mtk_ddp_mode_set invalid vrefresh 60
9368 19:25:52.274438 main_disp_path_setup
9369 19:25:52.274512 ovl_layer_smi_id_en
9370 19:25:52.277737 ovl_layer_smi_id_en
9371 19:25:52.277818 ccorr_config
9372 19:25:52.277883 aal_config
9373 19:25:52.280885 gamma_config
9374 19:25:52.280991 postmask_config
9375 19:25:52.284253 dither_config
9376 19:25:52.287635 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9377 19:25:52.293970 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9378 19:25:52.297222 Root Device init finished in 554 msecs
9379 19:25:52.300751 CPU_CLUSTER: 0 init
9380 19:25:52.307200 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9381 19:25:52.313913 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9382 19:25:52.314045 APU_MBOX 0x190000b0 = 0x10001
9383 19:25:52.317131 APU_MBOX 0x190001b0 = 0x10001
9384 19:25:52.320173 APU_MBOX 0x190005b0 = 0x10001
9385 19:25:52.323709 APU_MBOX 0x190006b0 = 0x10001
9386 19:25:52.330077 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9387 19:25:52.340091 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9388 19:25:52.352673 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9389 19:25:52.359455 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9390 19:25:52.370690 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9391 19:25:52.380108 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9392 19:25:52.383334 CPU_CLUSTER: 0 init finished in 81 msecs
9393 19:25:52.386143 Devices initialized
9394 19:25:52.389503 Show all devs... After init.
9395 19:25:52.389585 Root Device: enabled 1
9396 19:25:52.393313 CPU_CLUSTER: 0: enabled 1
9397 19:25:52.396431 CPU: 00: enabled 1
9398 19:25:52.399687 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9399 19:25:52.403204 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9400 19:25:52.406022 ELOG: NV offset 0x57f000 size 0x1000
9401 19:25:52.412897 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9402 19:25:52.419654 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9403 19:25:52.422720 ELOG: Event(17) added with size 13 at 2024-04-18 19:25:52 UTC
9404 19:25:52.429375 out: cmd=0x121: 03 db 21 01 00 00 00 00
9405 19:25:52.432919 in-header: 03 11 00 00 2c 00 00 00
9406 19:25:52.442619 in-data: 4e 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9407 19:25:52.449432 ELOG: Event(A1) added with size 10 at 2024-04-18 19:25:52 UTC
9408 19:25:52.456264 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9409 19:25:52.462413 ELOG: Event(A0) added with size 9 at 2024-04-18 19:25:52 UTC
9410 19:25:52.465964 elog_add_boot_reason: Logged dev mode boot
9411 19:25:52.472704 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9412 19:25:52.472885 Finalize devices...
9413 19:25:52.476259 Devices finalized
9414 19:25:52.479023 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9415 19:25:52.482110 Writing coreboot table at 0xffe64000
9416 19:25:52.485749 0. 000000000010a000-0000000000113fff: RAMSTAGE
9417 19:25:52.493592 1. 0000000040000000-00000000400fffff: RAM
9418 19:25:52.495328 2. 0000000040100000-000000004032afff: RAMSTAGE
9419 19:25:52.498692 3. 000000004032b000-00000000545fffff: RAM
9420 19:25:52.501914 4. 0000000054600000-000000005465ffff: BL31
9421 19:25:52.505131 5. 0000000054660000-00000000ffe63fff: RAM
9422 19:25:52.512338 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9423 19:25:52.515151 7. 0000000100000000-000000023fffffff: RAM
9424 19:25:52.518124 Passing 5 GPIOs to payload:
9425 19:25:52.521936 NAME | PORT | POLARITY | VALUE
9426 19:25:52.528280 EC in RW | 0x000000aa | low | undefined
9427 19:25:52.531932 EC interrupt | 0x00000005 | low | undefined
9428 19:25:52.534770 TPM interrupt | 0x000000ab | high | undefined
9429 19:25:52.541800 SD card detect | 0x00000011 | high | undefined
9430 19:25:52.544613 speaker enable | 0x00000093 | high | undefined
9431 19:25:52.548145 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9432 19:25:52.551860 in-header: 03 f9 00 00 02 00 00 00
9433 19:25:52.555579 in-data: 02 00
9434 19:25:52.559088 ADC[4]: Raw value=902955 ID=7
9435 19:25:52.562760 ADC[3]: Raw value=213916 ID=1
9436 19:25:52.562843 RAM Code: 0x71
9437 19:25:52.565561 ADC[6]: Raw value=75000 ID=0
9438 19:25:52.568312 ADC[5]: Raw value=213916 ID=1
9439 19:25:52.568423 SKU Code: 0x1
9440 19:25:52.575282 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum f149
9441 19:25:52.575394 coreboot table: 964 bytes.
9442 19:25:52.578232 IMD ROOT 0. 0xfffff000 0x00001000
9443 19:25:52.581314 IMD SMALL 1. 0xffffe000 0x00001000
9444 19:25:52.584693 RO MCACHE 2. 0xffffc000 0x00001104
9445 19:25:52.588299 CONSOLE 3. 0xfff7c000 0x00080000
9446 19:25:52.591681 FMAP 4. 0xfff7b000 0x00000452
9447 19:25:52.594666 TIME STAMP 5. 0xfff7a000 0x00000910
9448 19:25:52.597922 VBOOT WORK 6. 0xfff66000 0x00014000
9449 19:25:52.601414 RAMOOPS 7. 0xffe66000 0x00100000
9450 19:25:52.604484 COREBOOT 8. 0xffe64000 0x00002000
9451 19:25:52.608189 IMD small region:
9452 19:25:52.611636 IMD ROOT 0. 0xffffec00 0x00000400
9453 19:25:52.614478 VPD 1. 0xffffeb80 0x0000006c
9454 19:25:52.617656 MMC STATUS 2. 0xffffeb60 0x00000004
9455 19:25:52.624550 BS: BS_WRITE_TABLES run times (exec / console): 2 / 137 ms
9456 19:25:52.624636 Probing TPM: done!
9457 19:25:52.631279 Connected to device vid:did:rid of 1ae0:0028:00
9458 19:25:52.637841 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
9459 19:25:52.641562 Initialized TPM device CR50 revision 0
9460 19:25:52.644454 Checking cr50 for pending updates
9461 19:25:52.650395 Reading cr50 TPM mode
9462 19:25:52.658513 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9463 19:25:52.665211 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9464 19:25:52.705526 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9465 19:25:52.709084 Checking segment from ROM address 0x40100000
9466 19:25:52.712093 Checking segment from ROM address 0x4010001c
9467 19:25:52.718600 Loading segment from ROM address 0x40100000
9468 19:25:52.718716 code (compression=0)
9469 19:25:52.728300 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9470 19:25:52.735050 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9471 19:25:52.735155 it's not compressed!
9472 19:25:52.742178 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9473 19:25:52.748811 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9474 19:25:52.766191 Loading segment from ROM address 0x4010001c
9475 19:25:52.766327 Entry Point 0x80000000
9476 19:25:52.769317 Loaded segments
9477 19:25:52.772922 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9478 19:25:52.779114 Jumping to boot code at 0x80000000(0xffe64000)
9479 19:25:52.785749 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9480 19:25:52.792683 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9481 19:25:52.800122 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9482 19:25:52.803569 Checking segment from ROM address 0x40100000
9483 19:25:52.807273 Checking segment from ROM address 0x4010001c
9484 19:25:52.813622 Loading segment from ROM address 0x40100000
9485 19:25:52.813750 code (compression=1)
9486 19:25:52.820495 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9487 19:25:52.829824 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9488 19:25:52.829952 using LZMA
9489 19:25:52.838461 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9490 19:25:52.845051 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9491 19:25:52.848727 Loading segment from ROM address 0x4010001c
9492 19:25:52.848845 Entry Point 0x54601000
9493 19:25:52.852245 Loaded segments
9494 19:25:52.855219 NOTICE: MT8192 bl31_setup
9495 19:25:52.862430 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9496 19:25:52.865358 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9497 19:25:52.868895 WARNING: region 0:
9498 19:25:52.872261 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9499 19:25:52.872368 WARNING: region 1:
9500 19:25:52.878758 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9501 19:25:52.882311 WARNING: region 2:
9502 19:25:52.885281 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9503 19:25:52.889168 WARNING: region 3:
9504 19:25:52.892868 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9505 19:25:52.895662 WARNING: region 4:
9506 19:25:52.902312 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9507 19:25:52.902405 WARNING: region 5:
9508 19:25:52.905227 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9509 19:25:52.908702 WARNING: region 6:
9510 19:25:52.912157 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9511 19:25:52.915719 WARNING: region 7:
9512 19:25:52.918889 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9513 19:25:52.925387 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9514 19:25:52.928583 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9515 19:25:52.932254 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9516 19:25:52.938480 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9517 19:25:52.942029 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9518 19:25:52.945390 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9519 19:25:52.952324 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9520 19:25:52.955015 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9521 19:25:52.961669 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9522 19:25:52.965512 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9523 19:25:52.968608 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9524 19:25:52.975385 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9525 19:25:52.978318 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9526 19:25:52.985528 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9527 19:25:52.989099 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9528 19:25:52.991473 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9529 19:25:52.998281 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9530 19:25:53.001364 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9531 19:25:53.004857 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9532 19:25:53.011615 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9533 19:25:53.014916 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9534 19:25:53.021448 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9535 19:25:53.024665 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9536 19:25:53.028317 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9537 19:25:53.034876 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9538 19:25:53.038073 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9539 19:25:53.044785 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9540 19:25:53.047716 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9541 19:25:53.051486 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9542 19:25:53.057822 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9543 19:25:53.061134 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9544 19:25:53.068073 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9545 19:25:53.070802 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9546 19:25:53.074248 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9547 19:25:53.077941 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9548 19:25:53.084147 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9549 19:25:53.087818 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9550 19:25:53.090855 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9551 19:25:53.093950 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9552 19:25:53.101724 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9553 19:25:53.104325 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9554 19:25:53.107664 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9555 19:25:53.110774 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9556 19:25:53.117415 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9557 19:25:53.120937 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9558 19:25:53.123961 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9559 19:25:53.130680 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9560 19:25:53.133657 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9561 19:25:53.137086 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9562 19:25:53.143957 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9563 19:25:53.147060 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9564 19:25:53.153638 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9565 19:25:53.156797 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9566 19:25:53.160638 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9567 19:25:53.167594 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9568 19:25:53.170404 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9569 19:25:53.176944 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9570 19:25:53.180243 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9571 19:25:53.187313 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9572 19:25:53.190166 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9573 19:25:53.193793 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9574 19:25:53.200070 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9575 19:25:53.203490 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9576 19:25:53.210390 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9577 19:25:53.213709 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9578 19:25:53.220325 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9579 19:25:53.223442 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9580 19:25:53.230216 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9581 19:25:53.233262 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9582 19:25:53.236976 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9583 19:25:53.243507 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9584 19:25:53.246837 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9585 19:25:53.253460 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9586 19:25:53.256569 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9587 19:25:53.263287 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9588 19:25:53.266606 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9589 19:25:53.269947 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9590 19:25:53.276821 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9591 19:25:53.279893 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9592 19:25:53.286697 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9593 19:25:53.290191 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9594 19:25:53.296460 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9595 19:25:53.299568 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9596 19:25:53.306863 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9597 19:25:53.310275 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9598 19:25:53.313124 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9599 19:25:53.319929 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9600 19:25:53.323442 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9601 19:25:53.329661 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9602 19:25:53.333673 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9603 19:25:53.339564 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9604 19:25:53.343635 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9605 19:25:53.346520 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9606 19:25:53.353031 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9607 19:25:53.355876 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9608 19:25:53.362847 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9609 19:25:53.366163 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9610 19:25:53.369580 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9611 19:25:53.376474 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9612 19:25:53.379444 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9613 19:25:53.382427 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9614 19:25:53.389141 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9615 19:25:53.393059 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9616 19:25:53.396504 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9617 19:25:53.402754 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9618 19:25:53.406212 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9619 19:25:53.412641 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9620 19:25:53.415985 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9621 19:25:53.419583 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9622 19:25:53.425845 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9623 19:25:53.428951 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9624 19:25:53.435795 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9625 19:25:53.439386 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9626 19:25:53.442421 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9627 19:25:53.448931 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9628 19:25:53.452311 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9629 19:25:53.455833 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9630 19:25:53.462815 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9631 19:25:53.465685 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9632 19:25:53.469549 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9633 19:25:53.475800 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9634 19:25:53.478764 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9635 19:25:53.482638 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9636 19:25:53.485556 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9637 19:25:53.491878 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9638 19:25:53.495734 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9639 19:25:53.499088 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9640 19:25:53.505615 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9641 19:25:53.509011 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9642 19:25:53.515671 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9643 19:25:53.518684 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9644 19:25:53.521844 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9645 19:25:53.528555 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9646 19:25:53.532129 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9647 19:25:53.538745 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9648 19:25:53.541714 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9649 19:25:53.544944 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9650 19:25:53.551640 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9651 19:25:53.555139 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9652 19:25:53.562187 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9653 19:25:53.565275 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9654 19:25:53.568707 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9655 19:25:53.574942 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9656 19:25:53.578145 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9657 19:25:53.584833 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9658 19:25:53.588796 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9659 19:25:53.591755 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9660 19:25:53.598306 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9661 19:25:53.601995 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9662 19:25:53.604809 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9663 19:25:53.612089 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9664 19:25:53.615218 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9665 19:25:53.621786 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9666 19:25:53.624699 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9667 19:25:53.628363 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9668 19:25:53.635033 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9669 19:25:53.638165 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9670 19:25:53.644853 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9671 19:25:53.648327 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9672 19:25:53.651305 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9673 19:25:53.658066 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9674 19:25:53.661102 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9675 19:25:53.667807 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9676 19:25:53.670972 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9677 19:25:53.677499 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9678 19:25:53.681120 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9679 19:25:53.684172 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9680 19:25:53.690367 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9681 19:25:53.693694 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9682 19:25:53.700312 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9683 19:25:53.703813 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9684 19:25:53.706805 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9685 19:25:53.713751 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9686 19:25:53.717032 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9687 19:25:53.723707 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9688 19:25:53.727138 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9689 19:25:53.729982 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9690 19:25:53.736669 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9691 19:25:53.739822 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9692 19:25:53.746474 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9693 19:25:53.749695 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9694 19:25:53.753005 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9695 19:25:53.759789 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9696 19:25:53.762644 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9697 19:25:53.769447 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9698 19:25:53.772780 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9699 19:25:53.775843 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9700 19:25:53.782481 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9701 19:25:53.785936 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9702 19:25:53.792698 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9703 19:25:53.795784 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9704 19:25:53.802634 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9705 19:25:53.805502 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9706 19:25:53.808987 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9707 19:25:53.815371 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9708 19:25:53.819223 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9709 19:25:53.825387 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9710 19:25:53.828859 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9711 19:25:53.835560 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9712 19:25:53.838513 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9713 19:25:53.842105 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9714 19:25:53.848699 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9715 19:25:53.851955 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9716 19:25:53.858247 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9717 19:25:53.861972 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9718 19:25:53.868211 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9719 19:25:53.871864 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9720 19:25:53.874739 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9721 19:25:53.881385 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9722 19:25:53.884317 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9723 19:25:53.891279 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9724 19:25:53.894426 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9725 19:25:53.900893 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9726 19:25:53.904614 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9727 19:25:53.907554 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9728 19:25:53.914088 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9729 19:25:53.917309 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9730 19:25:53.923785 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9731 19:25:53.927505 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9732 19:25:53.933853 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9733 19:25:53.937331 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9734 19:25:53.940990 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9735 19:25:53.947223 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9736 19:25:53.950617 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9737 19:25:53.957180 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9738 19:25:53.960445 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9739 19:25:53.967042 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9740 19:25:53.970396 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9741 19:25:53.973916 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9742 19:25:53.979811 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9743 19:25:53.983435 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9744 19:25:53.986414 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9745 19:25:53.989948 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9746 19:25:53.996229 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9747 19:25:54.000382 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9748 19:25:54.002942 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9749 19:25:54.009535 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9750 19:25:54.012688 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9751 19:25:54.016602 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9752 19:25:54.023067 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9753 19:25:54.025983 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9754 19:25:54.032520 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9755 19:25:54.036330 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9756 19:25:54.039178 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9757 19:25:54.045390 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9758 19:25:54.048660 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9759 19:25:54.055226 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9760 19:25:54.058688 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9761 19:25:54.061847 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9762 19:25:54.068398 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9763 19:25:54.071676 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9764 19:25:54.078079 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9765 19:25:54.081528 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9766 19:25:54.085226 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9767 19:25:54.091267 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9768 19:25:54.094712 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9769 19:25:54.098077 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9770 19:25:54.104698 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9771 19:25:54.108432 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9772 19:25:54.114655 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9773 19:25:54.117766 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9774 19:25:54.121266 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9775 19:25:54.127550 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9776 19:25:54.130864 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9777 19:25:54.134340 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9778 19:25:54.140995 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9779 19:25:54.144087 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9780 19:25:54.150815 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9781 19:25:54.154815 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9782 19:25:54.157726 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9783 19:25:54.160949 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9784 19:25:54.164372 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9785 19:25:54.171078 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9786 19:25:54.174192 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9787 19:25:54.177253 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9788 19:25:54.180461 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9789 19:25:54.187332 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9790 19:25:54.190890 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9791 19:25:54.193939 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9792 19:25:54.200355 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9793 19:25:54.203814 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9794 19:25:54.207102 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9795 19:25:54.213625 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9796 19:25:54.217192 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9797 19:25:54.223278 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9798 19:25:54.226749 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9799 19:25:54.229657 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9800 19:25:54.236914 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9801 19:25:54.239742 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9802 19:25:54.246428 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9803 19:25:54.249690 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9804 19:25:54.253184 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9805 19:25:54.259475 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9806 19:25:54.262960 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9807 19:25:54.269311 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9808 19:25:54.272864 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9809 19:25:54.278969 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9810 19:25:54.282729 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9811 19:25:54.286111 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9812 19:25:54.292307 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9813 19:25:54.295508 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9814 19:25:54.302254 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9815 19:25:54.305337 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9816 19:25:54.312119 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9817 19:25:54.315725 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9818 19:25:54.318629 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9819 19:25:54.325629 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9820 19:25:54.328802 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9821 19:25:54.335416 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9822 19:25:54.338696 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9823 19:25:54.344959 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9824 19:25:54.348153 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9825 19:25:54.351395 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9826 19:25:54.358085 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9827 19:25:54.361763 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9828 19:25:54.367986 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9829 19:25:54.371242 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9830 19:25:54.374595 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9831 19:25:54.381586 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9832 19:25:54.384946 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9833 19:25:54.391211 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9834 19:25:54.394841 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9835 19:25:54.398005 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9836 19:25:54.404847 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9837 19:25:54.408104 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9838 19:25:54.414551 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9839 19:25:54.417750 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9840 19:25:54.424282 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9841 19:25:54.427749 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9842 19:25:54.430684 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9843 19:25:54.437135 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9844 19:25:54.440523 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9845 19:25:54.447125 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9846 19:25:54.450451 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9847 19:25:54.456726 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9848 19:25:54.460328 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9849 19:25:54.463640 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9850 19:25:54.469914 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9851 19:25:54.473570 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9852 19:25:54.480020 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9853 19:25:54.483219 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9854 19:25:54.489531 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9855 19:25:54.492924 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9856 19:25:54.496238 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9857 19:25:54.503094 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9858 19:25:54.506148 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9859 19:25:54.512856 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9860 19:25:54.516177 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9861 19:25:54.522531 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9862 19:25:54.526232 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9863 19:25:54.529462 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9864 19:25:54.535855 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9865 19:25:54.538996 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9866 19:25:54.545319 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9867 19:25:54.549213 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9868 19:25:54.552424 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9869 19:25:54.558714 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9870 19:25:54.561854 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9871 19:25:54.568421 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9872 19:25:54.571806 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9873 19:25:54.578206 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9874 19:25:54.581654 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9875 19:25:54.588263 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9876 19:25:54.591755 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9877 19:25:54.597946 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9878 19:25:54.601235 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9879 19:25:54.604849 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9880 19:25:54.611396 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9881 19:25:54.614617 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9882 19:25:54.621037 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9883 19:25:54.624427 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9884 19:25:54.631338 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9885 19:25:54.634068 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9886 19:25:54.641142 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9887 19:25:54.644033 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9888 19:25:54.650897 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9889 19:25:54.653954 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9890 19:25:54.657408 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9891 19:25:54.664344 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9892 19:25:54.667190 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9893 19:25:54.673686 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9894 19:25:54.677187 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9895 19:25:54.684043 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9896 19:25:54.687267 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9897 19:25:54.693656 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9898 19:25:54.697219 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9899 19:25:54.700794 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9900 19:25:54.706815 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9901 19:25:54.709936 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9902 19:25:54.716639 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9903 19:25:54.720009 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9904 19:25:54.726882 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9905 19:25:54.729764 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9906 19:25:54.733184 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9907 19:25:54.739572 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9908 19:25:54.742675 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9909 19:25:54.749427 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9910 19:25:54.752749 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9911 19:25:54.759348 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9912 19:25:54.762491 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9913 19:25:54.769031 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9914 19:25:54.772991 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9915 19:25:54.775898 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9916 19:25:54.782340 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9917 19:25:54.785842 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9918 19:25:54.792282 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9919 19:25:54.795675 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9920 19:25:54.802126 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9921 19:25:54.805506 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9922 19:25:54.812281 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9923 19:25:54.815297 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9924 19:25:54.821938 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9925 19:25:54.825388 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9926 19:25:54.832218 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9927 19:25:54.835542 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9928 19:25:54.842067 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9929 19:25:54.845152 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9930 19:25:54.851720 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9931 19:25:54.854948 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9932 19:25:54.861517 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9933 19:25:54.864891 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9934 19:25:54.871386 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9935 19:25:54.874690 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9936 19:25:54.881343 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9937 19:25:54.884390 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9938 19:25:54.891012 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9939 19:25:54.894373 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9940 19:25:54.901128 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9941 19:25:54.904472 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9942 19:25:54.910722 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9943 19:25:54.914292 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9944 19:25:54.920998 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9945 19:25:54.923915 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9946 19:25:54.930508 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9947 19:25:54.933706 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9948 19:25:54.937109 INFO: [APUAPC] vio 0
9949 19:25:54.941082 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9950 19:25:54.947315 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9951 19:25:54.950516 INFO: [APUAPC] D0_APC_0: 0x400510
9952 19:25:54.953562 INFO: [APUAPC] D0_APC_1: 0x0
9953 19:25:54.953650 INFO: [APUAPC] D0_APC_2: 0x1540
9954 19:25:54.956752 INFO: [APUAPC] D0_APC_3: 0x0
9955 19:25:54.960412 INFO: [APUAPC] D1_APC_0: 0xffffffff
9956 19:25:54.963661 INFO: [APUAPC] D1_APC_1: 0xffffffff
9957 19:25:54.966663 INFO: [APUAPC] D1_APC_2: 0x3fffff
9958 19:25:54.970030 INFO: [APUAPC] D1_APC_3: 0x0
9959 19:25:54.973455 INFO: [APUAPC] D2_APC_0: 0xffffffff
9960 19:25:54.976915 INFO: [APUAPC] D2_APC_1: 0xffffffff
9961 19:25:54.980082 INFO: [APUAPC] D2_APC_2: 0x3fffff
9962 19:25:54.983273 INFO: [APUAPC] D2_APC_3: 0x0
9963 19:25:54.986570 INFO: [APUAPC] D3_APC_0: 0xffffffff
9964 19:25:54.989582 INFO: [APUAPC] D3_APC_1: 0xffffffff
9965 19:25:54.993203 INFO: [APUAPC] D3_APC_2: 0x3fffff
9966 19:25:54.996492 INFO: [APUAPC] D3_APC_3: 0x0
9967 19:25:55.000116 INFO: [APUAPC] D4_APC_0: 0xffffffff
9968 19:25:55.003229 INFO: [APUAPC] D4_APC_1: 0xffffffff
9969 19:25:55.006168 INFO: [APUAPC] D4_APC_2: 0x3fffff
9970 19:25:55.010046 INFO: [APUAPC] D4_APC_3: 0x0
9971 19:25:55.013199 INFO: [APUAPC] D5_APC_0: 0xffffffff
9972 19:25:55.016142 INFO: [APUAPC] D5_APC_1: 0xffffffff
9973 19:25:55.019928 INFO: [APUAPC] D5_APC_2: 0x3fffff
9974 19:25:55.023175 INFO: [APUAPC] D5_APC_3: 0x0
9975 19:25:55.026046 INFO: [APUAPC] D6_APC_0: 0xffffffff
9976 19:25:55.029278 INFO: [APUAPC] D6_APC_1: 0xffffffff
9977 19:25:55.032502 INFO: [APUAPC] D6_APC_2: 0x3fffff
9978 19:25:55.036298 INFO: [APUAPC] D6_APC_3: 0x0
9979 19:25:55.039502 INFO: [APUAPC] D7_APC_0: 0xffffffff
9980 19:25:55.042520 INFO: [APUAPC] D7_APC_1: 0xffffffff
9981 19:25:55.045557 INFO: [APUAPC] D7_APC_2: 0x3fffff
9982 19:25:55.049034 INFO: [APUAPC] D7_APC_3: 0x0
9983 19:25:55.052393 INFO: [APUAPC] D8_APC_0: 0xffffffff
9984 19:25:55.056108 INFO: [APUAPC] D8_APC_1: 0xffffffff
9985 19:25:55.058894 INFO: [APUAPC] D8_APC_2: 0x3fffff
9986 19:25:55.062205 INFO: [APUAPC] D8_APC_3: 0x0
9987 19:25:55.065378 INFO: [APUAPC] D9_APC_0: 0xffffffff
9988 19:25:55.068868 INFO: [APUAPC] D9_APC_1: 0xffffffff
9989 19:25:55.072542 INFO: [APUAPC] D9_APC_2: 0x3fffff
9990 19:25:55.075693 INFO: [APUAPC] D9_APC_3: 0x0
9991 19:25:55.078978 INFO: [APUAPC] D10_APC_0: 0xffffffff
9992 19:25:55.082112 INFO: [APUAPC] D10_APC_1: 0xffffffff
9993 19:25:55.085058 INFO: [APUAPC] D10_APC_2: 0x3fffff
9994 19:25:55.088413 INFO: [APUAPC] D10_APC_3: 0x0
9995 19:25:55.091578 INFO: [APUAPC] D11_APC_0: 0xffffffff
9996 19:25:55.095074 INFO: [APUAPC] D11_APC_1: 0xffffffff
9997 19:25:55.098209 INFO: [APUAPC] D11_APC_2: 0x3fffff
9998 19:25:55.101947 INFO: [APUAPC] D11_APC_3: 0x0
9999 19:25:55.105182 INFO: [APUAPC] D12_APC_0: 0xffffffff
10000 19:25:55.108700 INFO: [APUAPC] D12_APC_1: 0xffffffff
10001 19:25:55.111848 INFO: [APUAPC] D12_APC_2: 0x3fffff
10002 19:25:55.114567 INFO: [APUAPC] D12_APC_3: 0x0
10003 19:25:55.117916 INFO: [APUAPC] D13_APC_0: 0xffffffff
10004 19:25:55.121178 INFO: [APUAPC] D13_APC_1: 0xffffffff
10005 19:25:55.124551 INFO: [APUAPC] D13_APC_2: 0x3fffff
10006 19:25:55.127658 INFO: [APUAPC] D13_APC_3: 0x0
10007 19:25:55.131628 INFO: [APUAPC] D14_APC_0: 0xffffffff
10008 19:25:55.134418 INFO: [APUAPC] D14_APC_1: 0xffffffff
10009 19:25:55.137892 INFO: [APUAPC] D14_APC_2: 0x3fffff
10010 19:25:55.141195 INFO: [APUAPC] D14_APC_3: 0x0
10011 19:25:55.144271 INFO: [APUAPC] D15_APC_0: 0xffffffff
10012 19:25:55.147800 INFO: [APUAPC] D15_APC_1: 0xffffffff
10013 19:25:55.150773 INFO: [APUAPC] D15_APC_2: 0x3fffff
10014 19:25:55.154099 INFO: [APUAPC] D15_APC_3: 0x0
10015 19:25:55.157998 INFO: [APUAPC] APC_CON: 0x4
10016 19:25:55.160913 INFO: [NOCDAPC] D0_APC_0: 0x0
10017 19:25:55.165029 INFO: [NOCDAPC] D0_APC_1: 0x0
10018 19:25:55.167439 INFO: [NOCDAPC] D1_APC_0: 0x0
10019 19:25:55.170932 INFO: [NOCDAPC] D1_APC_1: 0xfff
10020 19:25:55.173932 INFO: [NOCDAPC] D2_APC_0: 0x0
10021 19:25:55.177546 INFO: [NOCDAPC] D2_APC_1: 0xfff
10022 19:25:55.177642 INFO: [NOCDAPC] D3_APC_0: 0x0
10023 19:25:55.180583 INFO: [NOCDAPC] D3_APC_1: 0xfff
10024 19:25:55.183679 INFO: [NOCDAPC] D4_APC_0: 0x0
10025 19:25:55.187200 INFO: [NOCDAPC] D4_APC_1: 0xfff
10026 19:25:55.190367 INFO: [NOCDAPC] D5_APC_0: 0x0
10027 19:25:55.193740 INFO: [NOCDAPC] D5_APC_1: 0xfff
10028 19:25:55.197084 INFO: [NOCDAPC] D6_APC_0: 0x0
10029 19:25:55.200881 INFO: [NOCDAPC] D6_APC_1: 0xfff
10030 19:25:55.203953 INFO: [NOCDAPC] D7_APC_0: 0x0
10031 19:25:55.207187 INFO: [NOCDAPC] D7_APC_1: 0xfff
10032 19:25:55.210274 INFO: [NOCDAPC] D8_APC_0: 0x0
10033 19:25:55.213651 INFO: [NOCDAPC] D8_APC_1: 0xfff
10034 19:25:55.213740 INFO: [NOCDAPC] D9_APC_0: 0x0
10035 19:25:55.216572 INFO: [NOCDAPC] D9_APC_1: 0xfff
10036 19:25:55.219846 INFO: [NOCDAPC] D10_APC_0: 0x0
10037 19:25:55.223415 INFO: [NOCDAPC] D10_APC_1: 0xfff
10038 19:25:55.226628 INFO: [NOCDAPC] D11_APC_0: 0x0
10039 19:25:55.229918 INFO: [NOCDAPC] D11_APC_1: 0xfff
10040 19:25:55.233318 INFO: [NOCDAPC] D12_APC_0: 0x0
10041 19:25:55.236630 INFO: [NOCDAPC] D12_APC_1: 0xfff
10042 19:25:55.240067 INFO: [NOCDAPC] D13_APC_0: 0x0
10043 19:25:55.243131 INFO: [NOCDAPC] D13_APC_1: 0xfff
10044 19:25:55.246432 INFO: [NOCDAPC] D14_APC_0: 0x0
10045 19:25:55.249932 INFO: [NOCDAPC] D14_APC_1: 0xfff
10046 19:25:55.252924 INFO: [NOCDAPC] D15_APC_0: 0x0
10047 19:25:55.256218 INFO: [NOCDAPC] D15_APC_1: 0xfff
10048 19:25:55.259423 INFO: [NOCDAPC] APC_CON: 0x4
10049 19:25:55.262766 INFO: [APUAPC] set_apusys_apc done
10050 19:25:55.265971 INFO: [DEVAPC] devapc_init done
10051 19:25:55.269509 INFO: GICv3 without legacy support detected.
10052 19:25:55.272500 INFO: ARM GICv3 driver initialized in EL3
10053 19:25:55.276013 INFO: Maximum SPI INTID supported: 639
10054 19:25:55.279394 INFO: BL31: Initializing runtime services
10055 19:25:55.286163 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10056 19:25:55.289223 INFO: SPM: enable CPC mode
10057 19:25:55.295730 INFO: mcdi ready for mcusys-off-idle and system suspend
10058 19:25:55.298791 INFO: BL31: Preparing for EL3 exit to normal world
10059 19:25:55.302123 INFO: Entry point address = 0x80000000
10060 19:25:55.305344 INFO: SPSR = 0x8
10061 19:25:55.310268
10062 19:25:55.310370
10063 19:25:55.310437
10064 19:25:55.313887 Starting depthcharge on Spherion...
10065 19:25:55.313972
10066 19:25:55.314036 Wipe memory regions:
10067 19:25:55.314096
10068 19:25:55.314759 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10069 19:25:55.314861 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10070 19:25:55.314939 Setting prompt string to ['asurada:']
10071 19:25:55.315020 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10072 19:25:55.316657 [0x00000040000000, 0x00000054600000)
10073 19:25:55.439650
10074 19:25:55.439806 [0x00000054660000, 0x00000080000000)
10075 19:25:55.699786
10076 19:25:55.700008 [0x000000821a7280, 0x000000ffe64000)
10077 19:25:56.444858
10078 19:25:56.445014 [0x00000100000000, 0x00000240000000)
10079 19:25:58.335823
10080 19:25:58.338536 Initializing XHCI USB controller at 0x11200000.
10081 19:25:59.376538
10082 19:25:59.379858 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10083 19:25:59.379997
10084 19:25:59.380062
10085 19:25:59.380121
10086 19:25:59.380404 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10088 19:25:59.480781 asurada: tftpboot 192.168.201.1 13420384/tftp-deploy-v1rk1d3v/kernel/image.itb 13420384/tftp-deploy-v1rk1d3v/kernel/cmdline
10089 19:25:59.480960 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10090 19:25:59.481045 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10091 19:25:59.485636 tftpboot 192.168.201.1 13420384/tftp-deploy-v1rk1d3v/kernel/image.itp-deploy-v1rk1d3v/kernel/cmdline
10092 19:25:59.485764
10093 19:25:59.485828 Waiting for link
10094 19:25:59.646447
10095 19:25:59.646604 R8152: Initializing
10096 19:25:59.646672
10097 19:25:59.649135 Version 6 (ocp_data = 5c30)
10098 19:25:59.649216
10099 19:25:59.652376 R8152: Done initializing
10100 19:25:59.652456
10101 19:25:59.652520 Adding net device
10102 19:26:01.617772
10103 19:26:01.618274 done.
10104 19:26:01.618654
10105 19:26:01.619175 MAC: 00:24:32:30:7c:7b
10106 19:26:01.619579
10107 19:26:01.620881 Sending DHCP discover... done.
10108 19:26:01.621305
10109 19:26:06.689937 Waiting for reply... done.
10110 19:26:06.690440
10111 19:26:06.690804 Sending DHCP request... done.
10112 19:26:06.693158
10113 19:26:06.693563 Waiting for reply... done.
10114 19:26:06.693941
10115 19:26:06.696958 My ip is 192.168.201.14
10116 19:26:06.697370
10117 19:26:06.699906 The DHCP server ip is 192.168.201.1
10118 19:26:06.700317
10119 19:26:06.702816 TFTP server IP predefined by user: 192.168.201.1
10120 19:26:06.703228
10121 19:26:06.709737 Bootfile predefined by user: 13420384/tftp-deploy-v1rk1d3v/kernel/image.itb
10122 19:26:06.710148
10123 19:26:06.712888 Sending tftp read request... done.
10124 19:26:06.713300
10125 19:26:06.716271 Waiting for the transfer...
10126 19:26:06.716679
10127 19:26:07.373033 00000000 ################################################################
10128 19:26:07.373541
10129 19:26:08.050379 00080000 ################################################################
10130 19:26:08.050869
10131 19:26:08.691672 00100000 ################################################################
10132 19:26:08.691808
10133 19:26:09.282376 00180000 ################################################################
10134 19:26:09.282511
10135 19:26:09.878642 00200000 ################################################################
10136 19:26:09.878820
10137 19:26:10.532497 00280000 ################################################################
10138 19:26:10.532647
10139 19:26:11.198612 00300000 ################################################################
10140 19:26:11.199115
10141 19:26:11.870327 00380000 ################################################################
10142 19:26:11.871017
10143 19:26:12.479220 00400000 ################################################################
10144 19:26:12.479386
10145 19:26:13.134168 00480000 ################################################################
10146 19:26:13.134695
10147 19:26:13.773226 00500000 ################################################################
10148 19:26:13.773781
10149 19:26:14.408267 00580000 ################################################################
10150 19:26:14.408476
10151 19:26:14.980702 00600000 ################################################################
10152 19:26:14.980842
10153 19:26:15.566355 00680000 ################################################################
10154 19:26:15.566985
10155 19:26:16.237544 00700000 ################################################################
10156 19:26:16.237685
10157 19:26:16.820217 00780000 ################################################################
10158 19:26:16.820355
10159 19:26:17.377232 00800000 ################################################################
10160 19:26:17.377382
10161 19:26:17.923422 00880000 ################################################################
10162 19:26:17.923594
10163 19:26:18.466401 00900000 ################################################################
10164 19:26:18.466549
10165 19:26:19.011165 00980000 ################################################################
10166 19:26:19.011301
10167 19:26:19.558021 00a00000 ################################################################
10168 19:26:19.558213
10169 19:26:20.105159 00a80000 ################################################################
10170 19:26:20.105354
10171 19:26:20.654518 00b00000 ################################################################
10172 19:26:20.654672
10173 19:26:21.183420 00b80000 ################################################################
10174 19:26:21.183572
10175 19:26:21.716868 00c00000 ################################################################
10176 19:26:21.717057
10177 19:26:22.258878 00c80000 ################################################################
10178 19:26:22.259058
10179 19:26:22.785479 00d00000 ################################################################
10180 19:26:22.785647
10181 19:26:23.320341 00d80000 ################################################################
10182 19:26:23.320537
10183 19:26:23.840901 00e00000 ################################################################
10184 19:26:23.841055
10185 19:26:24.366808 00e80000 ################################################################
10186 19:26:24.367030
10187 19:26:24.913810 00f00000 ################################################################
10188 19:26:24.914021
10189 19:26:25.438093 00f80000 ################################################################
10190 19:26:25.438254
10191 19:26:25.984203 01000000 ################################################################
10192 19:26:25.984347
10193 19:26:26.527948 01080000 ################################################################
10194 19:26:26.528088
10195 19:26:27.067733 01100000 ################################################################
10196 19:26:27.067917
10197 19:26:27.619742 01180000 ################################################################
10198 19:26:27.619909
10199 19:26:28.159157 01200000 ################################################################
10200 19:26:28.159282
10201 19:26:28.719622 01280000 ################################################################
10202 19:26:28.719749
10203 19:26:29.270220 01300000 ################################################################
10204 19:26:29.270362
10205 19:26:29.815588 01380000 ################################################################
10206 19:26:29.815760
10207 19:26:30.362974 01400000 ################################################################
10208 19:26:30.363138
10209 19:26:30.904367 01480000 ################################################################
10210 19:26:30.904580
10211 19:26:31.419866 01500000 ################################################################
10212 19:26:31.420048
10213 19:26:31.952183 01580000 ################################################################
10214 19:26:31.952334
10215 19:26:32.520283 01600000 ################################################################
10216 19:26:32.520476
10217 19:26:33.084399 01680000 ################################################################
10218 19:26:33.084561
10219 19:26:33.642862 01700000 ################################################################
10220 19:26:33.643015
10221 19:26:34.224786 01780000 ################################################################
10222 19:26:34.224962
10223 19:26:34.785898 01800000 ################################################################
10224 19:26:34.786038
10225 19:26:35.326369 01880000 ################################################################
10226 19:26:35.326509
10227 19:26:35.875458 01900000 ################################################################
10228 19:26:35.875611
10229 19:26:36.418442 01980000 ################################################################
10230 19:26:36.418587
10231 19:26:36.984647 01a00000 ################################################################
10232 19:26:36.984782
10233 19:26:37.546699 01a80000 ################################################################
10234 19:26:37.546837
10235 19:26:38.120099 01b00000 ################################################################
10236 19:26:38.120236
10237 19:26:38.764858 01b80000 ################################################################
10238 19:26:38.765009
10239 19:26:39.446610 01c00000 ################################################################
10240 19:26:39.446764
10241 19:26:40.045375 01c80000 ################################################################
10242 19:26:40.045544
10243 19:26:40.608231 01d00000 ################################################################
10244 19:26:40.608455
10245 19:26:41.163329 01d80000 ################################################################
10246 19:26:41.163485
10247 19:26:41.457686 01e00000 ################################## done.
10248 19:26:41.457867
10249 19:26:41.461195 The bootfile was 31728062 bytes long.
10250 19:26:41.461334
10251 19:26:41.464128 Sending tftp read request... done.
10252 19:26:41.464261
10253 19:26:41.464401 Waiting for the transfer...
10254 19:26:41.467453
10255 19:26:41.467568 00000000 # done.
10256 19:26:41.467671
10257 19:26:41.474071 Command line loaded dynamically from TFTP file: 13420384/tftp-deploy-v1rk1d3v/kernel/cmdline
10258 19:26:41.474239
10259 19:26:41.496626 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/13420384/extract-nfsrootfs-5njzje7g,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10260 19:26:41.496775
10261 19:26:41.496845 Loading FIT.
10262 19:26:41.499824
10263 19:26:41.499952 Image ramdisk-1 has 18768441 bytes.
10264 19:26:41.500049
10265 19:26:41.503379 Image fdt-1 has 47230 bytes.
10266 19:26:41.503546
10267 19:26:41.506444 Image kernel-1 has 12910355 bytes.
10268 19:26:41.506539
10269 19:26:41.516553 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10270 19:26:41.516692
10271 19:26:41.533090 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10272 19:26:41.533236
10273 19:26:41.539181 Choosing best match conf-1 for compat google,spherion-rev2.
10274 19:26:41.543014
10275 19:26:41.547985 Connected to device vid:did:rid of 1ae0:0028:00
10276 19:26:41.556083
10277 19:26:41.559111 tpm_get_response: command 0x17b, return code 0x0
10278 19:26:41.559236
10279 19:26:41.562263 ec_init: CrosEC protocol v3 supported (256, 248)
10280 19:26:41.566728
10281 19:26:41.569956 tpm_cleanup: add release locality here.
10282 19:26:41.570103
10283 19:26:41.570202 Shutting down all USB controllers.
10284 19:26:41.573377
10285 19:26:41.573501 Removing current net device
10286 19:26:41.573599
10287 19:26:41.580262 Exiting depthcharge with code 4 at timestamp: 75544448
10288 19:26:41.580434
10289 19:26:41.583043 LZMA decompressing kernel-1 to 0x821a6718
10290 19:26:41.583173
10291 19:26:41.586326 LZMA decompressing kernel-1 to 0x40000000
10292 19:26:43.180424
10293 19:26:43.180559 jumping to kernel
10294 19:26:43.181045 end: 2.2.4 bootloader-commands (duration 00:00:48) [common]
10295 19:26:43.181158 start: 2.2.5 auto-login-action (timeout 00:03:37) [common]
10296 19:26:43.181248 Setting prompt string to ['Linux version [0-9]']
10297 19:26:43.181314 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10298 19:26:43.181381 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10299 19:26:43.263328
10300 19:26:43.266563 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10301 19:26:43.270400 start: 2.2.5.1 login-action (timeout 00:03:37) [common]
10302 19:26:43.270519 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10303 19:26:43.270599 Setting prompt string to []
10304 19:26:43.270675 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10305 19:26:43.270747 Using line separator: #'\n'#
10306 19:26:43.270805 No login prompt set.
10307 19:26:43.270865 Parsing kernel messages
10308 19:26:43.270919 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10309 19:26:43.271025 [login-action] Waiting for messages, (timeout 00:03:37)
10310 19:26:43.271088 Waiting using forced prompt support (timeout 00:01:49)
10311 19:26:43.289911 [ 0.000000] Linux version 6.1.86-cip19 (KernelCI@build-j170728-arm64-gcc-10-defconfig-arm64-chromebook-wrkxq) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Apr 18 19:05:54 UTC 2024
10312 19:26:43.293259 [ 0.000000] random: crng init done
10313 19:26:43.299526 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10314 19:26:43.303231 [ 0.000000] efi: UEFI not found.
10315 19:26:43.309415 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10316 19:26:43.319656 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10317 19:26:43.325991 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10318 19:26:43.335923 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10319 19:26:43.342191 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10320 19:26:43.349145 [ 0.000000] printk: bootconsole [mtk8250] enabled
10321 19:26:43.355643 [ 0.000000] NUMA: No NUMA configuration found
10322 19:26:43.362032 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10323 19:26:43.365718 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10324 19:26:43.369054 [ 0.000000] Zone ranges:
10325 19:26:43.375684 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10326 19:26:43.379024 [ 0.000000] DMA32 empty
10327 19:26:43.385716 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10328 19:26:43.388715 [ 0.000000] Movable zone start for each node
10329 19:26:43.392140 [ 0.000000] Early memory node ranges
10330 19:26:43.399100 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10331 19:26:43.405400 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10332 19:26:43.411803 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10333 19:26:43.418669 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10334 19:26:43.424911 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10335 19:26:43.431435 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10336 19:26:43.487629 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10337 19:26:43.494320 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10338 19:26:43.501210 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10339 19:26:43.504494 [ 0.000000] psci: probing for conduit method from DT.
10340 19:26:43.511227 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10341 19:26:43.514383 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10342 19:26:43.520681 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10343 19:26:43.524193 [ 0.000000] psci: SMC Calling Convention v1.2
10344 19:26:43.530897 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10345 19:26:43.534350 [ 0.000000] Detected VIPT I-cache on CPU0
10346 19:26:43.540677 [ 0.000000] CPU features: detected: GIC system register CPU interface
10347 19:26:43.547169 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10348 19:26:43.553648 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10349 19:26:43.560668 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10350 19:26:43.570010 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10351 19:26:43.576424 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10352 19:26:43.580252 [ 0.000000] alternatives: applying boot alternatives
10353 19:26:43.586756 [ 0.000000] Fallback order for Node 0: 0
10354 19:26:43.592934 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10355 19:26:43.596551 [ 0.000000] Policy zone: Normal
10356 19:26:43.619248 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/13420384/extract-nfsrootfs-5njzje7g,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10357 19:26:43.629452 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10358 19:26:43.639704 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10359 19:26:43.650025 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10360 19:26:43.656475 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10361 19:26:43.659937 <6>[ 0.000000] software IO TLB: area num 8.
10362 19:26:43.716571 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10363 19:26:43.865647 <6>[ 0.000000] Memory: 7946244K/8385536K available (18048K kernel code, 4118K rwdata, 22288K rodata, 8448K init, 616K bss, 406524K reserved, 32768K cma-reserved)
10364 19:26:43.872032 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10365 19:26:43.878855 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10366 19:26:43.882120 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10367 19:26:43.888563 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10368 19:26:43.895176 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10369 19:26:43.898533 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10370 19:26:43.908093 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10371 19:26:43.914567 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10372 19:26:43.921090 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10373 19:26:43.927881 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10374 19:26:43.931203 <6>[ 0.000000] GICv3: 608 SPIs implemented
10375 19:26:43.934531 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10376 19:26:43.941306 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10377 19:26:43.944260 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10378 19:26:43.951056 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10379 19:26:43.964213 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10380 19:26:43.976934 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10381 19:26:43.983574 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10382 19:26:43.991958 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10383 19:26:44.005288 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10384 19:26:44.011669 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10385 19:26:44.018536 <6>[ 0.009187] Console: colour dummy device 80x25
10386 19:26:44.028333 <6>[ 0.013917] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10387 19:26:44.034629 <6>[ 0.024423] pid_max: default: 32768 minimum: 301
10388 19:26:44.038652 <6>[ 0.029288] LSM: Security Framework initializing
10389 19:26:44.044797 <6>[ 0.034226] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10390 19:26:44.054876 <6>[ 0.042043] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10391 19:26:44.064335 <6>[ 0.051460] cblist_init_generic: Setting adjustable number of callback queues.
10392 19:26:44.071270 <6>[ 0.058950] cblist_init_generic: Setting shift to 3 and lim to 1.
10393 19:26:44.078239 <6>[ 0.065288] cblist_init_generic: Setting adjustable number of callback queues.
10394 19:26:44.084636 <6>[ 0.072761] cblist_init_generic: Setting shift to 3 and lim to 1.
10395 19:26:44.087692 <6>[ 0.079200] rcu: Hierarchical SRCU implementation.
10396 19:26:44.094445 <6>[ 0.084215] rcu: Max phase no-delay instances is 1000.
10397 19:26:44.101160 <6>[ 0.091238] EFI services will not be available.
10398 19:26:44.104006 <6>[ 0.096222] smp: Bringing up secondary CPUs ...
10399 19:26:44.113116 <6>[ 0.101272] Detected VIPT I-cache on CPU1
10400 19:26:44.119574 <6>[ 0.101344] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10401 19:26:44.126237 <6>[ 0.101376] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10402 19:26:44.129585 <6>[ 0.101710] Detected VIPT I-cache on CPU2
10403 19:26:44.136129 <6>[ 0.101765] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10404 19:26:44.146149 <6>[ 0.101782] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10405 19:26:44.149579 <6>[ 0.102046] Detected VIPT I-cache on CPU3
10406 19:26:44.155962 <6>[ 0.102093] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10407 19:26:44.162268 <6>[ 0.102108] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10408 19:26:44.165589 <6>[ 0.102412] CPU features: detected: Spectre-v4
10409 19:26:44.172428 <6>[ 0.102417] CPU features: detected: Spectre-BHB
10410 19:26:44.175913 <6>[ 0.102423] Detected PIPT I-cache on CPU4
10411 19:26:44.181959 <6>[ 0.102482] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10412 19:26:44.188675 <6>[ 0.102499] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10413 19:26:44.195197 <6>[ 0.102798] Detected PIPT I-cache on CPU5
10414 19:26:44.201866 <6>[ 0.102861] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10415 19:26:44.208185 <6>[ 0.102878] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10416 19:26:44.211860 <6>[ 0.103157] Detected PIPT I-cache on CPU6
10417 19:26:44.221329 <6>[ 0.103223] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10418 19:26:44.228312 <6>[ 0.103239] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10419 19:26:44.231646 <6>[ 0.103534] Detected PIPT I-cache on CPU7
10420 19:26:44.237824 <6>[ 0.103600] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10421 19:26:44.245187 <6>[ 0.103616] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10422 19:26:44.247929 <6>[ 0.103663] smp: Brought up 1 node, 8 CPUs
10423 19:26:44.254500 <6>[ 0.245156] SMP: Total of 8 processors activated.
10424 19:26:44.261132 <6>[ 0.250078] CPU features: detected: 32-bit EL0 Support
10425 19:26:44.267510 <6>[ 0.255441] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10426 19:26:44.273907 <6>[ 0.264241] CPU features: detected: Common not Private translations
10427 19:26:44.280934 <6>[ 0.270717] CPU features: detected: CRC32 instructions
10428 19:26:44.286910 <6>[ 0.276068] CPU features: detected: RCpc load-acquire (LDAPR)
10429 19:26:44.290519 <6>[ 0.282028] CPU features: detected: LSE atomic instructions
10430 19:26:44.297356 <6>[ 0.287810] CPU features: detected: Privileged Access Never
10431 19:26:44.303398 <6>[ 0.293626] CPU features: detected: RAS Extension Support
10432 19:26:44.310727 <6>[ 0.299234] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10433 19:26:44.313533 <6>[ 0.306455] CPU: All CPU(s) started at EL2
10434 19:26:44.320125 <6>[ 0.310798] alternatives: applying system-wide alternatives
10435 19:26:44.330680 <6>[ 0.321619] devtmpfs: initialized
10436 19:26:44.346530 <6>[ 0.330600] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10437 19:26:44.353192 <6>[ 0.340565] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10438 19:26:44.359861 <6>[ 0.348241] pinctrl core: initialized pinctrl subsystem
10439 19:26:44.362666 <6>[ 0.355036] DMI not present or invalid.
10440 19:26:44.369465 <6>[ 0.359451] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10441 19:26:44.379136 <6>[ 0.366348] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10442 19:26:44.385578 <6>[ 0.373940] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10443 19:26:44.396414 <6>[ 0.382173] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10444 19:26:44.398976 <6>[ 0.390414] audit: initializing netlink subsys (disabled)
10445 19:26:44.409509 <5>[ 0.396109] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10446 19:26:44.415555 <6>[ 0.396852] thermal_sys: Registered thermal governor 'step_wise'
10447 19:26:44.421983 <6>[ 0.404075] thermal_sys: Registered thermal governor 'power_allocator'
10448 19:26:44.425257 <6>[ 0.410327] cpuidle: using governor menu
10449 19:26:44.431853 <6>[ 0.421286] NET: Registered PF_QIPCRTR protocol family
10450 19:26:44.438966 <6>[ 0.426789] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10451 19:26:44.445117 <6>[ 0.433894] ASID allocator initialised with 32768 entries
10452 19:26:44.448320 <6>[ 0.440512] Serial: AMBA PL011 UART driver
10453 19:26:44.458781 <4>[ 0.449581] Trying to register duplicate clock ID: 134
10454 19:26:44.515566 <6>[ 0.509788] KASLR enabled
10455 19:26:44.530075 <6>[ 0.517522] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10456 19:26:44.537281 <6>[ 0.524532] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10457 19:26:44.543533 <6>[ 0.531022] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10458 19:26:44.550106 <6>[ 0.538027] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10459 19:26:44.556555 <6>[ 0.544513] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10460 19:26:44.563297 <6>[ 0.551513] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10461 19:26:44.569512 <6>[ 0.557999] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10462 19:26:44.576210 <6>[ 0.565006] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10463 19:26:44.579337 <6>[ 0.572543] ACPI: Interpreter disabled.
10464 19:26:44.588115 <6>[ 0.579012] iommu: Default domain type: Translated
10465 19:26:44.594876 <6>[ 0.584128] iommu: DMA domain TLB invalidation policy: strict mode
10466 19:26:44.598192 <5>[ 0.590789] SCSI subsystem initialized
10467 19:26:44.604826 <6>[ 0.594954] usbcore: registered new interface driver usbfs
10468 19:26:44.611797 <6>[ 0.600688] usbcore: registered new interface driver hub
10469 19:26:44.614523 <6>[ 0.606239] usbcore: registered new device driver usb
10470 19:26:44.621879 <6>[ 0.612370] pps_core: LinuxPPS API ver. 1 registered
10471 19:26:44.631712 <6>[ 0.617563] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10472 19:26:44.634645 <6>[ 0.626910] PTP clock support registered
10473 19:26:44.638042 <6>[ 0.631152] EDAC MC: Ver: 3.0.0
10474 19:26:44.645650 <6>[ 0.636340] FPGA manager framework
10475 19:26:44.652100 <6>[ 0.640022] Advanced Linux Sound Architecture Driver Initialized.
10476 19:26:44.655255 <6>[ 0.646810] vgaarb: loaded
10477 19:26:44.661764 <6>[ 0.649985] clocksource: Switched to clocksource arch_sys_counter
10478 19:26:44.665198 <5>[ 0.656427] VFS: Disk quotas dquot_6.6.0
10479 19:26:44.671437 <6>[ 0.660610] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10480 19:26:44.674663 <6>[ 0.667801] pnp: PnP ACPI: disabled
10481 19:26:44.683579 <6>[ 0.674472] NET: Registered PF_INET protocol family
10482 19:26:44.693725 <6>[ 0.680069] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10483 19:26:44.705152 <6>[ 0.692407] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10484 19:26:44.715016 <6>[ 0.701222] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10485 19:26:44.722033 <6>[ 0.709194] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10486 19:26:44.731552 <6>[ 0.717896] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10487 19:26:44.738014 <6>[ 0.727649] TCP: Hash tables configured (established 65536 bind 65536)
10488 19:26:44.744829 <6>[ 0.734511] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10489 19:26:44.754522 <6>[ 0.741711] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10490 19:26:44.761014 <6>[ 0.749411] NET: Registered PF_UNIX/PF_LOCAL protocol family
10491 19:26:44.767406 <6>[ 0.755571] RPC: Registered named UNIX socket transport module.
10492 19:26:44.770706 <6>[ 0.761726] RPC: Registered udp transport module.
10493 19:26:44.777366 <6>[ 0.766660] RPC: Registered tcp transport module.
10494 19:26:44.783868 <6>[ 0.771592] RPC: Registered tcp NFSv4.1 backchannel transport module.
10495 19:26:44.787581 <6>[ 0.778257] PCI: CLS 0 bytes, default 64
10496 19:26:44.790705 <6>[ 0.782582] Unpacking initramfs...
10497 19:26:44.814942 <6>[ 0.802097] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10498 19:26:44.825049 <6>[ 0.810767] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10499 19:26:44.827841 <6>[ 0.819648] kvm [1]: IPA Size Limit: 40 bits
10500 19:26:44.834573 <6>[ 0.824176] kvm [1]: GICv3: no GICV resource entry
10501 19:26:44.837869 <6>[ 0.829195] kvm [1]: disabling GICv2 emulation
10502 19:26:44.844289 <6>[ 0.833881] kvm [1]: GIC system register CPU interface enabled
10503 19:26:44.847868 <6>[ 0.840063] kvm [1]: vgic interrupt IRQ18
10504 19:26:44.854666 <6>[ 0.844424] kvm [1]: VHE mode initialized successfully
10505 19:26:44.861020 <5>[ 0.850847] Initialise system trusted keyrings
10506 19:26:44.867699 <6>[ 0.855657] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10507 19:26:44.875059 <6>[ 0.865708] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10508 19:26:44.881897 <5>[ 0.872085] NFS: Registering the id_resolver key type
10509 19:26:44.884672 <5>[ 0.877382] Key type id_resolver registered
10510 19:26:44.891512 <5>[ 0.881795] Key type id_legacy registered
10511 19:26:44.897925 <6>[ 0.886083] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10512 19:26:44.904414 <6>[ 0.893003] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10513 19:26:44.911230 <6>[ 0.900714] 9p: Installing v9fs 9p2000 file system support
10514 19:26:44.947642 <5>[ 0.938099] Key type asymmetric registered
10515 19:26:44.950816 <5>[ 0.942428] Asymmetric key parser 'x509' registered
10516 19:26:44.960207 <6>[ 0.947566] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10517 19:26:44.963918 <6>[ 0.955184] io scheduler mq-deadline registered
10518 19:26:44.966835 <6>[ 0.959958] io scheduler kyber registered
10519 19:26:44.986083 <6>[ 0.977230] EINJ: ACPI disabled.
10520 19:26:45.018216 <4>[ 1.002467] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10521 19:26:45.027745 <4>[ 1.013117] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10522 19:26:45.043221 <6>[ 1.034124] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10523 19:26:45.051210 <6>[ 1.042081] printk: console [ttyS0] disabled
10524 19:26:45.079165 <6>[ 1.066719] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10525 19:26:45.085671 <6>[ 1.076188] printk: console [ttyS0] enabled
10526 19:26:45.089347 <6>[ 1.076188] printk: console [ttyS0] enabled
10527 19:26:45.095658 <6>[ 1.085081] printk: bootconsole [mtk8250] disabled
10528 19:26:45.099351 <6>[ 1.085081] printk: bootconsole [mtk8250] disabled
10529 19:26:45.106105 <6>[ 1.096153] SuperH (H)SCI(F) driver initialized
10530 19:26:45.108807 <6>[ 1.101458] msm_serial: driver initialized
10531 19:26:45.123250 <6>[ 1.110542] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10532 19:26:45.132811 <6>[ 1.119088] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10533 19:26:45.139600 <6>[ 1.127631] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10534 19:26:45.149587 <6>[ 1.136258] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10535 19:26:45.159317 <6>[ 1.144968] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10536 19:26:45.166110 <6>[ 1.153682] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10537 19:26:45.176105 <6>[ 1.162222] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10538 19:26:45.182438 <6>[ 1.171022] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10539 19:26:45.192425 <6>[ 1.179563] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10540 19:26:45.204258 <6>[ 1.195249] loop: module loaded
10541 19:26:45.210691 <6>[ 1.201181] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10542 19:26:45.234117 <4>[ 1.224568] mtk-pmic-keys: Failed to locate of_node [id: -1]
10543 19:26:45.240698 <6>[ 1.231376] megasas: 07.719.03.00-rc1
10544 19:26:45.250013 <6>[ 1.240993] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10545 19:26:45.258975 <6>[ 1.249376] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10546 19:26:45.275472 <6>[ 1.265894] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10547 19:26:45.331013 <6>[ 1.315071] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10548 19:26:45.588264 <6>[ 1.579318] Freeing initrd memory: 18324K
10549 19:26:45.600104 <6>[ 1.590778] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10550 19:26:45.611348 <6>[ 1.601701] tun: Universal TUN/TAP device driver, 1.6
10551 19:26:45.614374 <6>[ 1.607784] thunder_xcv, ver 1.0
10552 19:26:45.617538 <6>[ 1.611290] thunder_bgx, ver 1.0
10553 19:26:45.620674 <6>[ 1.614784] nicpf, ver 1.0
10554 19:26:45.631493 <6>[ 1.618838] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10555 19:26:45.634484 <6>[ 1.626314] hns3: Copyright (c) 2017 Huawei Corporation.
10556 19:26:45.641181 <6>[ 1.631899] hclge is initializing
10557 19:26:45.644915 <6>[ 1.635477] e1000: Intel(R) PRO/1000 Network Driver
10558 19:26:45.651048 <6>[ 1.640606] e1000: Copyright (c) 1999-2006 Intel Corporation.
10559 19:26:45.654480 <6>[ 1.646619] e1000e: Intel(R) PRO/1000 Network Driver
10560 19:26:45.661323 <6>[ 1.651835] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10561 19:26:45.668005 <6>[ 1.658023] igb: Intel(R) Gigabit Ethernet Network Driver
10562 19:26:45.674573 <6>[ 1.663674] igb: Copyright (c) 2007-2014 Intel Corporation.
10563 19:26:45.680811 <6>[ 1.669510] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10564 19:26:45.687390 <6>[ 1.676028] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10565 19:26:45.690772 <6>[ 1.682490] sky2: driver version 1.30
10566 19:26:45.697123 <6>[ 1.687517] VFIO - User Level meta-driver version: 0.3
10567 19:26:45.704729 <6>[ 1.695833] usbcore: registered new interface driver usb-storage
10568 19:26:45.711612 <6>[ 1.702297] usbcore: registered new device driver onboard-usb-hub
10569 19:26:45.720507 <6>[ 1.711498] mt6397-rtc mt6359-rtc: registered as rtc0
10570 19:26:45.730633 <6>[ 1.716961] mt6397-rtc mt6359-rtc: setting system clock to 2024-04-18T19:26:45 UTC (1713468405)
10571 19:26:45.733960 <6>[ 1.726556] i2c_dev: i2c /dev entries driver
10572 19:26:45.775344 <6>[ 1.738527] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10573 19:26:45.775492 <4>[ 1.747260] cpu cpu0: supply cpu not found, using dummy regulator
10574 19:26:45.775564 <4>[ 1.753687] cpu cpu1: supply cpu not found, using dummy regulator
10575 19:26:45.775625 <4>[ 1.760090] cpu cpu2: supply cpu not found, using dummy regulator
10576 19:26:45.777353 <4>[ 1.766492] cpu cpu3: supply cpu not found, using dummy regulator
10577 19:26:45.784054 <4>[ 1.772910] cpu cpu4: supply cpu not found, using dummy regulator
10578 19:26:45.790826 <4>[ 1.779307] cpu cpu5: supply cpu not found, using dummy regulator
10579 19:26:45.797005 <4>[ 1.785705] cpu cpu6: supply cpu not found, using dummy regulator
10580 19:26:45.803706 <4>[ 1.792105] cpu cpu7: supply cpu not found, using dummy regulator
10581 19:26:45.821916 <6>[ 1.812756] cpu cpu0: EM: created perf domain
10582 19:26:45.824851 <6>[ 1.817693] cpu cpu4: EM: created perf domain
10583 19:26:45.832283 <6>[ 1.822968] sdhci: Secure Digital Host Controller Interface driver
10584 19:26:45.838687 <6>[ 1.829402] sdhci: Copyright(c) Pierre Ossman
10585 19:26:45.845156 <6>[ 1.834360] Synopsys Designware Multimedia Card Interface Driver
10586 19:26:45.848436 <6>[ 1.840977] mmc0: CQHCI version 5.10
10587 19:26:45.855452 <6>[ 1.841002] sdhci-pltfm: SDHCI platform and OF driver helper
10588 19:26:45.862106 <6>[ 1.851847] ledtrig-cpu: registered to indicate activity on CPUs
10589 19:26:45.868523 <6>[ 1.858956] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10590 19:26:45.875135 <6>[ 1.866014] usbcore: registered new interface driver usbhid
10591 19:26:45.878409 <6>[ 1.871853] usbhid: USB HID core driver
10592 19:26:45.888426 <6>[ 1.876071] spi_master spi0: will run message pump with realtime priority
10593 19:26:45.934397 <6>[ 1.918705] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10594 19:26:45.954350 <6>[ 1.934776] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10595 19:26:45.957498 <6>[ 1.948349] mmc0: Command Queue Engine enabled
10596 19:26:45.964496 <6>[ 1.950863] cros-ec-spi spi0.0: Chrome EC device registered
10597 19:26:45.971075 <6>[ 1.953108] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10598 19:26:45.974758 <6>[ 1.966305] mmcblk0: mmc0:0001 DA4128 116 GiB
10599 19:26:45.986525 <6>[ 1.973793] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10600 19:26:45.993116 <6>[ 1.976543] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10601 19:26:45.999419 <6>[ 1.984285] NET: Registered PF_PACKET protocol family
10602 19:26:46.003027 <6>[ 1.990112] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10603 19:26:46.009736 <6>[ 1.994442] 9pnet: Installing 9P2000 support
10604 19:26:46.013029 <6>[ 2.000294] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10605 19:26:46.019850 <5>[ 2.004114] Key type dns_resolver registered
10606 19:26:46.026237 <6>[ 2.010124] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10607 19:26:46.029623 <6>[ 2.014374] registered taskstats version 1
10608 19:26:46.032934 <5>[ 2.024756] Loading compiled-in X.509 certificates
10609 19:26:46.062109 <4>[ 2.045816] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10610 19:26:46.071432 <4>[ 2.056548] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10611 19:26:46.078057 <3>[ 2.067076] debugfs: File 'uA_load' in directory '/' already present!
10612 19:26:46.084441 <3>[ 2.073775] debugfs: File 'min_uV' in directory '/' already present!
10613 19:26:46.091116 <3>[ 2.080383] debugfs: File 'max_uV' in directory '/' already present!
10614 19:26:46.097675 <3>[ 2.087052] debugfs: File 'constraint_flags' in directory '/' already present!
10615 19:26:46.109192 <3>[ 2.096620] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10616 19:26:46.119174 <6>[ 2.109944] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10617 19:26:46.125690 <6>[ 2.116767] xhci-mtk 11200000.usb: xHCI Host Controller
10618 19:26:46.132366 <6>[ 2.122278] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10619 19:26:46.142716 <6>[ 2.130126] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10620 19:26:46.149364 <6>[ 2.139552] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10621 19:26:46.155666 <6>[ 2.145619] xhci-mtk 11200000.usb: xHCI Host Controller
10622 19:26:46.161973 <6>[ 2.151094] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10623 19:26:46.168608 <6>[ 2.158740] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10624 19:26:46.175557 <6>[ 2.166632] hub 1-0:1.0: USB hub found
10625 19:26:46.179082 <6>[ 2.170650] hub 1-0:1.0: 1 port detected
10626 19:26:46.185945 <6>[ 2.174924] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10627 19:26:46.192949 <6>[ 2.183631] hub 2-0:1.0: USB hub found
10628 19:26:46.195895 <6>[ 2.187653] hub 2-0:1.0: 1 port detected
10629 19:26:46.204814 <6>[ 2.195802] mtk-msdc 11f70000.mmc: Got CD GPIO
10630 19:26:46.217985 <6>[ 2.205799] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10631 19:26:46.224734 <6>[ 2.213843] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10632 19:26:46.234914 <4>[ 2.221834] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10633 19:26:46.244475 <6>[ 2.231377] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10634 19:26:46.251083 <6>[ 2.239486] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10635 19:26:46.257782 <6>[ 2.247515] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10636 19:26:46.268071 <6>[ 2.255450] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10637 19:26:46.274039 <6>[ 2.263268] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10638 19:26:46.284410 <6>[ 2.271096] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10639 19:26:46.294215 <6>[ 2.281394] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10640 19:26:46.300904 <6>[ 2.289776] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10641 19:26:46.310473 <6>[ 2.298120] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10642 19:26:46.317419 <6>[ 2.306469] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10643 19:26:46.326942 <6>[ 2.314808] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10644 19:26:46.337042 <6>[ 2.323158] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10645 19:26:46.343840 <6>[ 2.331497] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10646 19:26:46.353784 <6>[ 2.339846] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10647 19:26:46.360624 <6>[ 2.348185] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10648 19:26:46.370013 <6>[ 2.356532] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10649 19:26:46.376813 <6>[ 2.364870] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10650 19:26:46.387032 <6>[ 2.373212] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10651 19:26:46.393224 <6>[ 2.381550] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10652 19:26:46.402981 <6>[ 2.389887] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10653 19:26:46.409842 <6>[ 2.398224] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10654 19:26:46.416162 <6>[ 2.406986] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10655 19:26:46.423192 <6>[ 2.414242] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10656 19:26:46.430160 <6>[ 2.421129] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10657 19:26:46.440244 <6>[ 2.427999] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10658 19:26:46.447069 <6>[ 2.435010] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10659 19:26:46.454093 <6>[ 2.441881] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10660 19:26:46.463580 <6>[ 2.451011] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10661 19:26:46.473154 <6>[ 2.460133] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10662 19:26:46.483161 <6>[ 2.469444] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10663 19:26:46.492994 <6>[ 2.478916] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10664 19:26:46.502921 <6>[ 2.488384] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10665 19:26:46.509803 <6>[ 2.497503] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10666 19:26:46.519587 <6>[ 2.506971] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10667 19:26:46.529577 <6>[ 2.516090] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10668 19:26:46.539492 <6>[ 2.525385] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10669 19:26:46.549501 <6>[ 2.535546] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10670 19:26:46.560136 <6>[ 2.547552] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10671 19:26:46.566536 <6>[ 2.557140] Trying to probe devices needed for running init ...
10672 19:26:46.586643 <6>[ 2.574388] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10673 19:26:46.615219 <6>[ 2.606176] hub 2-1:1.0: USB hub found
10674 19:26:46.618684 <6>[ 2.610658] hub 2-1:1.0: 3 ports detected
10675 19:26:46.626758 <6>[ 2.617886] hub 2-1:1.0: USB hub found
10676 19:26:46.630399 <6>[ 2.622254] hub 2-1:1.0: 3 ports detected
10677 19:26:46.738574 <6>[ 2.726256] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10678 19:26:46.893223 <6>[ 2.884294] hub 1-1:1.0: USB hub found
10679 19:26:46.896829 <6>[ 2.888819] hub 1-1:1.0: 4 ports detected
10680 19:26:46.906573 <6>[ 2.897760] hub 1-1:1.0: USB hub found
10681 19:26:46.910276 <6>[ 2.902354] hub 1-1:1.0: 4 ports detected
10682 19:26:46.978844 <6>[ 2.966534] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10683 19:26:47.230766 <6>[ 3.218312] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10684 19:26:47.363432 <6>[ 3.354387] hub 1-1.4:1.0: USB hub found
10685 19:26:47.366756 <6>[ 3.359081] hub 1-1.4:1.0: 2 ports detected
10686 19:26:47.376999 <6>[ 3.367772] hub 1-1.4:1.0: USB hub found
10687 19:26:47.380114 <6>[ 3.372387] hub 1-1.4:1.0: 2 ports detected
10688 19:26:47.678296 <6>[ 3.666248] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10689 19:26:47.870416 <6>[ 3.858282] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10690 19:26:58.868695 <6>[ 14.863633] ALSA device list:
10691 19:26:58.874844 <6>[ 14.867098] No soundcards found.
10692 19:26:58.882496 <6>[ 14.874435] Freeing unused kernel memory: 8448K
10693 19:26:58.885759 <6>[ 14.879402] Run /init as init process
10694 19:26:58.894095 Loading, please wait...
10695 19:26:58.920722 Starting systemd-udevd version 252.22-1~deb12u1
10696 19:26:58.921246
10697 19:26:59.160820 <6>[ 15.149455] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10698 19:26:59.167138 <6>[ 15.157105] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10699 19:26:59.176957 <6>[ 15.165937] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10700 19:26:59.186784 <3>[ 15.175841] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10701 19:26:59.193917 <6>[ 15.179021] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10702 19:26:59.203320 <3>[ 15.184114] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10703 19:26:59.209736 <6>[ 15.193957] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10704 19:26:59.216601 <6>[ 15.195143] remoteproc remoteproc0: scp is available
10705 19:26:59.219610 <6>[ 15.195749] remoteproc remoteproc0: powering up scp
10706 19:26:59.230036 <6>[ 15.195753] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10707 19:26:59.233012 <6>[ 15.195778] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10708 19:26:59.242929 <3>[ 15.199503] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10709 19:26:59.249756 <4>[ 15.229907] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10710 19:26:59.255927 <3>[ 15.231768] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10711 19:26:59.266053 <4>[ 15.240264] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10712 19:26:59.269536 <4>[ 15.240264] Fallback method does not support PEC.
10713 19:26:59.279605 <3>[ 15.247059] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10714 19:26:59.286686 <4>[ 15.251561] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10715 19:26:59.293047 <6>[ 15.251707] mc: Linux media interface: v0.10
10716 19:26:59.299984 <3>[ 15.270288] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10717 19:26:59.306583 <6>[ 15.273507] usbcore: registered new device driver r8152-cfgselector
10718 19:26:59.316465 <3>[ 15.277366] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10719 19:26:59.319478 <6>[ 15.282665] videodev: Linux video capture interface: v2.00
10720 19:26:59.325961 <6>[ 15.298529] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10721 19:26:59.336397 <3>[ 15.304581] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10722 19:26:59.342907 <6>[ 15.312628] pci_bus 0000:00: root bus resource [bus 00-ff]
10723 19:26:59.349910 <3>[ 15.318246] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10724 19:26:59.356303 <3>[ 15.318308] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10725 19:26:59.366290 <6>[ 15.320928] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10726 19:26:59.373336 <6>[ 15.320936] remoteproc remoteproc0: remote processor scp is now up
10727 19:26:59.380112 <6>[ 15.320947] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10728 19:26:59.389994 <6>[ 15.322596] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10729 19:26:59.400307 <6>[ 15.322816] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10730 19:26:59.406645 <6>[ 15.325188] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10731 19:26:59.412924 <3>[ 15.333253] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10732 19:26:59.423047 <6>[ 15.334357] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10733 19:26:59.429415 <6>[ 15.335476] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10734 19:26:59.439571 <6>[ 15.338980] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10735 19:26:59.449562 <3>[ 15.347036] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10736 19:26:59.456105 <3>[ 15.347039] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10737 19:26:59.465793 <3>[ 15.347078] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10738 19:26:59.472869 <6>[ 15.355263] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10739 19:26:59.478833 <6>[ 15.362572] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10740 19:26:59.489555 <3>[ 15.363640] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10741 19:26:59.495842 <3>[ 15.363646] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10742 19:26:59.505576 <3>[ 15.363653] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10743 19:26:59.511932 <3>[ 15.363659] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10744 19:26:59.522053 <3>[ 15.363694] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10745 19:26:59.528770 <6>[ 15.370611] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10746 19:26:59.535555 <6>[ 15.370702] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10747 19:26:59.545459 <4>[ 15.401735] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10748 19:26:59.551604 <6>[ 15.404098] pci 0000:00:00.0: supports D1 D2
10749 19:26:59.555310 <6>[ 15.404320] Bluetooth: Core ver 2.22
10750 19:26:59.558183 <6>[ 15.404374] NET: Registered PF_BLUETOOTH protocol family
10751 19:26:59.565313 <6>[ 15.404376] Bluetooth: HCI device and connection manager initialized
10752 19:26:59.571667 <6>[ 15.404391] Bluetooth: HCI socket layer initialized
10753 19:26:59.578309 <6>[ 15.404396] Bluetooth: L2CAP socket layer initialized
10754 19:26:59.581809 <6>[ 15.404402] Bluetooth: SCO socket layer initialized
10755 19:26:59.591609 <4>[ 15.412096] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10756 19:26:59.598059 <6>[ 15.419875] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10757 19:26:59.604634 <6>[ 15.421926] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10758 19:26:59.611204 <6>[ 15.439305] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10759 19:26:59.617690 <6>[ 15.446450] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10760 19:26:59.624322 <6>[ 15.447216] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10761 19:26:59.637726 <6>[ 15.455852] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10762 19:26:59.644264 <6>[ 15.462364] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10763 19:26:59.650888 <6>[ 15.462820] usbcore: registered new interface driver btusb
10764 19:26:59.660600 <4>[ 15.463905] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10765 19:26:59.667066 <3>[ 15.463915] Bluetooth: hci0: Failed to load firmware file (-2)
10766 19:26:59.673946 <3>[ 15.463918] Bluetooth: hci0: Failed to set up firmware (-2)
10767 19:26:59.684018 <4>[ 15.463922] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10768 19:26:59.690348 <6>[ 15.468732] usbcore: registered new interface driver uvcvideo
10769 19:26:59.697296 <6>[ 15.477899] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10770 19:26:59.700460 <6>[ 15.478179] r8152 2-1.3:1.0 eth0: v1.12.13
10771 19:26:59.707014 <6>[ 15.478226] usbcore: registered new interface driver r8152
10772 19:26:59.713380 <6>[ 15.502448] usbcore: registered new interface driver cdc_ether
10773 19:26:59.719982 <6>[ 15.510220] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10774 19:26:59.726844 <6>[ 15.534267] usbcore: registered new interface driver r8153_ecm
10775 19:26:59.736815 <3>[ 15.543202] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10776 19:26:59.740196 <6>[ 15.543249] pci 0000:01:00.0: supports D1 D2
10777 19:26:59.746249 <6>[ 15.543252] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10778 19:26:59.752947 <6>[ 15.557683] r8152 2-1.3:1.0 enx002432307c7b: renamed from eth0
10779 19:26:59.759724 <6>[ 15.558041] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10780 19:26:59.766177 <6>[ 15.558071] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10781 19:26:59.776032 <6>[ 15.558074] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10782 19:26:59.783121 <6>[ 15.558082] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10783 19:26:59.792400 <6>[ 15.558095] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10784 19:26:59.799189 <6>[ 15.558108] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10785 19:26:59.805635 <6>[ 15.558119] pci 0000:00:00.0: PCI bridge to [bus 01]
10786 19:26:59.812518 <6>[ 15.558124] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10787 19:26:59.818958 <6>[ 15.558273] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10788 19:26:59.825520 <6>[ 15.558803] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10789 19:26:59.832490 <6>[ 15.559239] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10790 19:26:59.858118 <5>[ 15.847672] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10791 19:26:59.879982 <5>[ 15.869382] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10792 19:26:59.886912 <5>[ 15.876883] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10793 19:26:59.896939 <4>[ 15.885375] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10794 19:26:59.903096 <6>[ 15.894261] cfg80211: failed to load regulatory.db
10795 19:26:59.951766 <6>[ 15.940771] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10796 19:26:59.957817 <6>[ 15.948312] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10797 19:26:59.982858 <6>[ 15.975185] mt7921e 0000:01:00.0: ASIC revision: 79610010
10798 19:27:00.087332 <6>[ 16.076676] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10799 19:27:00.090804 <6>[ 16.076676]
10800 19:27:00.110270 Begin: Loading essential drivers ... done.
10801 19:27:00.113807 Begin: Running /scripts/init-premount ... done.
10802 19:27:00.120121 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10803 19:27:00.130131 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10804 19:27:00.133362 Device /sys/class/net/enx002432307c7b found
10805 19:27:00.133477 done.
10806 19:27:00.153203 Begin: Waiting up to 180 secs for any network device to become available ... done.
10807 19:27:00.213253 IP-Config: enx002432307c7b hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10808 19:27:00.359119 <6>[ 16.348454] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10809 19:27:01.041285 <6>[ 17.033785] r8152 2-1.3:1.0 enx002432307c7b: carrier on
10810 19:27:01.209209 <6>[ 17.202167] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10811 19:27:01.224462 IP-Config: no response after 2 secs - giving up
10812 19:27:01.230851 IP-Config: enx002432307c7b hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10813 19:27:01.269649 IP-Config: wlp1s0 hardware address d8:f3:bc:78:0c:a1 mtu 1500 DHCP
10814 19:27:01.906147 IP-Config: enx002432307c7b complete (dhcp from 192.168.201.1):
10815 19:27:01.912709 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10816 19:27:01.919765 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10817 19:27:01.925863 host : mt8192-asurada-spherion-r0-cbg-2
10818 19:27:01.932476 domain : lava-rack
10819 19:27:01.938946 rootserver: 192.168.201.1 rootpath:
10820 19:27:01.939082 filename :
10821 19:27:02.057812 done.
10822 19:27:02.065818 Begin: Running /scripts/nfs-bottom ... done.
10823 19:27:02.084613 Begin: Running /scripts/init-bottom ... done.
10824 19:27:03.453904 <6>[ 19.446923] NET: Registered PF_INET6 protocol family
10825 19:27:03.462228 <6>[ 19.454842] Segment Routing with IPv6
10826 19:27:03.465068 <6>[ 19.458835] In-situ OAM (IOAM) with IPv6
10827 19:27:03.665893 <30>[ 19.632380] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10828 19:27:03.672238 <30>[ 19.665494] systemd[1]: Detected architecture arm64.
10829 19:27:03.682212
10830 19:27:03.685314 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10831 19:27:03.685442
10832 19:27:03.685537
10833 19:27:03.710952 <30>[ 19.703991] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10834 19:27:04.858316 <30>[ 20.847898] systemd[1]: Queued start job for default target graphical.target.
10835 19:27:04.898849 <30>[ 20.888077] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10836 19:27:04.904821 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10837 19:27:04.905002
10838 19:27:04.926764 <30>[ 20.916334] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10839 19:27:04.936406 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10840 19:27:04.936548
10841 19:27:04.954750 <30>[ 20.944294] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10842 19:27:04.964517 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10843 19:27:04.964701
10844 19:27:04.982267 <30>[ 20.971853] systemd[1]: Created slice user.slice - User and Session Slice.
10845 19:27:04.988357 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10846 19:27:04.988543
10847 19:27:05.012000 <30>[ 20.998695] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10848 19:27:05.022161 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10849 19:27:05.022308
10850 19:27:05.040259 <30>[ 21.026553] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10851 19:27:05.046840 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10852 19:27:05.046963
10853 19:27:05.074739 <30>[ 21.054927] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10854 19:27:05.085336 <30>[ 21.074812] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10855 19:27:05.091280 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10856 19:27:05.091405
10857 19:27:05.108525 <30>[ 21.098362] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10858 19:27:05.115385 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10859 19:27:05.115514
10860 19:27:05.132300 <30>[ 21.122373] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10861 19:27:05.142086 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10862 19:27:05.142246
10863 19:27:05.157000 <30>[ 21.150430] systemd[1]: Reached target paths.target - Path Units.
10864 19:27:05.164231 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10865 19:27:05.166845
10866 19:27:05.185080 <30>[ 21.174763] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10867 19:27:05.191285 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10868 19:27:05.191422
10869 19:27:05.205149 <30>[ 21.198304] systemd[1]: Reached target slices.target - Slice Units.
10870 19:27:05.215248 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10871 19:27:05.215382
10872 19:27:05.229801 <30>[ 21.222810] systemd[1]: Reached target swap.target - Swaps.
10873 19:27:05.236315 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10874 19:27:05.236433
10875 19:27:05.256777 <30>[ 21.246853] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10876 19:27:05.266962 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10877 19:27:05.267104
10878 19:27:05.285251 <30>[ 21.275326] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10879 19:27:05.295108 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10880 19:27:05.295261
10881 19:27:05.315509 <30>[ 21.305153] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10882 19:27:05.325275 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10883 19:27:05.325414
10884 19:27:05.342054 <30>[ 21.331858] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10885 19:27:05.351942 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10886 19:27:05.352079
10887 19:27:05.369317 <30>[ 21.359085] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10888 19:27:05.375715 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10889 19:27:05.375847
10890 19:27:05.394166 <30>[ 21.384000] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10891 19:27:05.404060 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10892 19:27:05.404168
10893 19:27:05.424904 <30>[ 21.414524] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10894 19:27:05.434534 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10895 19:27:05.434636
10896 19:27:05.452950 <30>[ 21.442952] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10897 19:27:05.462727 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10898 19:27:05.462835
10899 19:27:05.512692 <30>[ 21.502738] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10900 19:27:05.519111 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10901 19:27:05.519214
10902 19:27:05.538813 <30>[ 21.528781] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10903 19:27:05.545495 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10904 19:27:05.545588
10905 19:27:05.568000 <30>[ 21.557786] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10906 19:27:05.574499 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10907 19:27:05.574616
10908 19:27:05.599297 <30>[ 21.582749] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10909 19:27:05.641024 <30>[ 21.631108] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10910 19:27:05.651558 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10911 19:27:05.651691
10912 19:27:05.674869 <30>[ 21.664547] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10913 19:27:05.681155 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10914 19:27:05.681246
10915 19:27:05.706885 <30>[ 21.696293] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10916 19:27:05.712797 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10917 19:27:05.712888
10918 19:27:05.748417 <6>[ 21.738208] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10919 19:27:05.769141 <30>[ 21.759288] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10920 19:27:05.776192 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10921 19:27:05.776303
10922 19:27:05.803370 <30>[ 21.792901] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10923 19:27:05.812962 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10924 19:27:05.813072
10925 19:27:05.835095 <30>[ 21.824740] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10926 19:27:05.841467 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10927 19:27:05.841566
10928 19:27:05.866780 <30>[ 21.856455] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10929 19:27:05.873478 Starting [0;1;39mmodpr<6>[ 21.866269] fuse: init (API version 7.37)
10930 19:27:05.876408 obe@loop.ser…e[0m - Load Kernel Module loop...
10931 19:27:05.880186
10932 19:27:05.906801 <30>[ 21.896515] systemd[1]: Starting systemd-journald.service - Journal Service...
10933 19:27:05.913265 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10934 19:27:05.913365
10935 19:27:05.947447 <30>[ 21.937363] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10936 19:27:05.953855 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10937 19:27:05.953963
10938 19:27:05.981292 <30>[ 21.968169] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10939 19:27:05.987830 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10940 19:27:05.988008
10941 19:27:06.055369 <3>[ 22.045024] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10942 19:27:06.065357 <30>[ 22.051092] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10943 19:27:06.071491 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10944 19:27:06.071604
10945 19:27:06.095675 <3>[ 22.085338] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10946 19:27:06.105661 <30>[ 22.086382] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10947 19:27:06.112500 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10948 19:27:06.112589
10949 19:27:06.139156 <3>[ 22.128653] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10950 19:27:06.145346 <30>[ 22.128734] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10951 19:27:06.155208 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10952 19:27:06.155329
10953 19:27:06.168487 <3>[ 22.158433] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10954 19:27:06.178632 <30>[ 22.167982] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10955 19:27:06.184746 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10956 19:27:06.184857
10957 19:27:06.198424 <3>[ 22.188095] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10958 19:27:06.208293 <30>[ 22.197575] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10959 19:27:06.215417 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10960 19:27:06.215506
10961 19:27:06.228255 <3>[ 22.217902] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10962 19:27:06.238591 <30>[ 22.228518] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10963 19:27:06.249095 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10964 19:27:06.249196
10965 19:27:06.259038 <3>[ 22.248528] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10966 19:27:06.268931 <30>[ 22.258933] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10967 19:27:06.280187 <30>[ 22.267413] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10968 19:27:06.289542 [[0;32m OK [0m] Finished [0;1;39mmodprobe@c<3>[ 22.279490] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10969 19:27:06.296004 onfigfs…[0m - Load Kernel Module configfs.
10970 19:27:06.296100
10971 19:27:06.314516 <30>[ 22.303935] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10972 19:27:06.321109 <3>[ 22.310278] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10973 19:27:06.331034 <30>[ 22.312154] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10974 19:27:06.338128 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10975 19:27:06.338258
10976 19:27:06.350993 <3>[ 22.340745] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10977 19:27:06.361689 <30>[ 22.351886] systemd[1]: modprobe@drm.service: Deactivated successfully.
10978 19:27:06.368539 <30>[ 22.359895] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10979 19:27:06.378421 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10980 19:27:06.378525
10981 19:27:06.398859 <30>[ 22.388919] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10982 19:27:06.409955 <30>[ 22.399095] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10983 19:27:06.419367 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10984 19:27:06.419468
10985 19:27:06.437425 <30>[ 22.427114] systemd[1]: Started systemd-journald.service - Journal Service.
10986 19:27:06.443958 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10987 19:27:06.444055
10988 19:27:06.470616 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10989 19:27:06.470727
10990 19:27:06.495474 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10991 19:27:06.495590
10992 19:27:06.519564 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10993 19:27:06.519711
10994 19:27:06.535780 <4>[ 22.517397] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10995 19:27:06.542840 <3>[ 22.533057] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10996 19:27:06.552040 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10997 19:27:06.552149
10998 19:27:06.575838 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10999 19:27:06.576004
11000 19:27:06.594166 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
11001 19:27:06.594284
11002 19:27:06.619303 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
11003 19:27:06.619423
11004 19:27:06.677341 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
11005 19:27:06.677474
11006 19:27:06.702913 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
11007 19:27:06.703039
11008 19:27:06.729793 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
11009 19:27:06.729918
11010 19:27:06.757593 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
11011 19:27:06.757717
11012 19:27:06.801400 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables..<46>[ 22.790942] systemd-journald[313]: Received client request to flush runtime journal.
11013 19:27:06.801598 .
11014 19:27:06.801724
11015 19:27:06.861440 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
11016 19:27:06.861602
11017 19:27:07.124481 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
11018 19:27:07.124613
11019 19:27:07.141603 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
11020 19:27:07.141728
11021 19:27:07.162047 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
11022 19:27:07.162175
11023 19:27:07.757467 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
11024 19:27:07.757597
11025 19:27:08.215518 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11026 19:27:08.215675
11027 19:27:08.233335 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
11028 19:27:08.233453
11029 19:27:08.289347 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
11030 19:27:08.289476
11031 19:27:08.385914 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11032 19:27:08.386118
11033 19:27:08.408871 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11034 19:27:08.409005
11035 19:27:08.428174 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11036 19:27:08.428269
11037 19:27:08.468709 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11038 19:27:08.468833
11039 19:27:08.491845 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11040 19:27:08.492072
11041 19:27:08.746437 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11042 19:27:08.746566
11043 19:27:08.811299 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11044 19:27:08.811464
11045 19:27:08.868017 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11046 19:27:08.868152
11047 19:27:09.125828 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11048 19:27:09.125965
11049 19:27:09.197830 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11050 19:27:09.197999
11051 19:27:09.224485 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11052 19:27:09.224591
11053 19:27:09.278490 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11054 19:27:09.278637
11055 19:27:09.297020 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11056 19:27:09.297118
11057 19:27:09.350530 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11058 19:27:09.350651
11059 19:27:09.380498 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11060 19:27:09.380609
11061 19:27:09.416320 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11062 19:27:09.416438
11063 19:27:09.437753 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11064 19:27:09.437855
11065 19:27:09.469125 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11066 19:27:09.469286
11067 19:27:09.512854 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11068 19:27:09.513001
11069 19:27:09.532813 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11070 19:27:09.532944
11071 19:27:09.552755 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11072 19:27:09.552934
11073 19:27:09.571290 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11074 19:27:09.571470
11075 19:27:09.592967 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11076 19:27:09.593113
11077 19:27:09.616335 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11078 19:27:09.616444
11079 19:27:09.632803 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11080 19:27:09.632894
11081 19:27:09.659678 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11082 19:27:09.659777
11083 19:27:09.683332 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11084 19:27:09.683426
11085 19:27:09.700564 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11086 19:27:09.700689
11087 19:27:09.755307 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11088 19:27:09.755445
11089 19:27:09.775664 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11090 19:27:09.775757
11091 19:27:09.791894 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11092 19:27:09.792006
11093 19:27:09.810272 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11094 19:27:09.810395
11095 19:27:09.828330 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11096 19:27:09.828416
11097 19:27:09.844241 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11098 19:27:09.844325
11099 19:27:09.897695 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11100 19:27:09.897829
11101 19:27:09.938487 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11102 19:27:09.938660
11103 19:27:10.014108 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11104 19:27:10.014265
11105 19:27:10.045646 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11106 19:27:10.045759
11107 19:27:10.182684 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11108 19:27:10.182845
11109 19:27:10.245209 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11110 19:27:10.245366
11111 19:27:10.308329 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11112 19:27:10.308465
11113 19:27:10.326102 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11114 19:27:10.326226
11115 19:27:10.346599 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11116 19:27:10.346707
11117 19:27:10.382776 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11118 19:27:10.382926
11119 19:27:10.405558 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11120 19:27:10.405710
11121 19:27:10.436207 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11122 19:27:10.436339
11123 19:27:10.454992 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11124 19:27:10.455098
11125 19:27:10.526291 Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
11126 19:27:10.526421
11127 19:27:10.547564 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11128 19:27:10.547703
11129 19:27:10.600260 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11130 19:27:10.600391
11131 19:27:10.672173 [[0;32m OK [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
11132 19:27:10.672288
11133 19:27:10.757613
11134 19:27:10.757733
11135 19:27:10.760968 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11136 19:27:10.761048
11137 19:27:10.764571 debian-bookworm-arm64 login: root (automatic login)
11138 19:27:10.764651
11139 19:27:10.764713
11140 19:27:11.077572 Linux debian-bookworm-arm64 6.1.86-cip19 #1 SMP PREEMPT Thu Apr 18 19:05:54 UTC 2024 aarch64
11141 19:27:11.077706
11142 19:27:11.084650 The programs included with the Debian GNU/Linux system are free software;
11143 19:27:11.090894 the exact distribution terms for each program are described in the
11144 19:27:11.094298 individual files in /usr/share/doc/*/copyright.
11145 19:27:11.094399
11146 19:27:11.100746 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11147 19:27:11.104198 permitted by applicable law.
11148 19:27:12.242630 Matched prompt #10: / #
11150 19:27:12.242925 Setting prompt string to ['/ #']
11151 19:27:12.243019 end: 2.2.5.1 login-action (duration 00:00:29) [common]
11153 19:27:12.243316 end: 2.2.5 auto-login-action (duration 00:00:29) [common]
11154 19:27:12.243439 start: 2.2.6 expect-shell-connection (timeout 00:03:08) [common]
11155 19:27:12.243551 Setting prompt string to ['/ #']
11156 19:27:12.243658 Forcing a shell prompt, looking for ['/ #']
11158 19:27:12.293918 / #
11159 19:27:12.294156 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11160 19:27:12.294302 Waiting using forced prompt support (timeout 00:02:30)
11161 19:27:12.299144
11162 19:27:12.299519 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11163 19:27:12.299669 start: 2.2.7 export-device-env (timeout 00:03:08) [common]
11165 19:27:12.400062 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/13420384/extract-nfsrootfs-5njzje7g'
11166 19:27:12.405444 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/13420384/extract-nfsrootfs-5njzje7g'
11168 19:27:12.505998 / # export NFS_SERVER_IP='192.168.201.1'
11169 19:27:12.511819 export NFS_SERVER_IP='192.168.201.1'
11170 19:27:12.512144 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11171 19:27:12.512246 end: 2.2 depthcharge-retry (duration 00:01:52) [common]
11172 19:27:12.512335 end: 2 depthcharge-action (duration 00:01:52) [common]
11173 19:27:12.512426 start: 3 lava-test-retry (timeout 00:07:28) [common]
11174 19:27:12.512513 start: 3.1 lava-test-shell (timeout 00:07:28) [common]
11175 19:27:12.512596 Using namespace: common
11177 19:27:12.613023 / # #
11178 19:27:12.613193 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11179 19:27:12.618767 #
11180 19:27:12.619069 Using /lava-13420384
11182 19:27:12.719444 / # export SHELL=/bin/bash
11183 19:27:12.724874 export SHELL=/bin/bash
11185 19:27:12.825465 / # . /lava-13420384/environment
11186 19:27:12.830632 . /lava-13420384/environment
11188 19:27:12.937609 / # /lava-13420384/bin/lava-test-runner /lava-13420384/0
11189 19:27:12.937765 Test shell timeout: 10s (minimum of the action and connection timeout)
11190 19:27:12.942878 /lava-13420384/bin/lava-test-runner /lava-13420384/0
11191 19:27:13.217684 + export TESTRUN_ID=0_timesync-off
11192 19:27:13.220907 + TESTRUN_ID=0_timesync-off
11193 19:27:13.223853 + cd /lava-13420384/0/tests/0_timesync-off
11194 19:27:13.227394 ++ cat uuid
11195 19:27:13.233730 + UUID=13420384_1.6.2.3.1
11196 19:27:13.233836 + set +x
11197 19:27:13.240102 <LAVA_SIGNAL_STARTRUN 0_timesync-off 13420384_1.6.2.3.1>
11198 19:27:13.240377 Received signal: <STARTRUN> 0_timesync-off 13420384_1.6.2.3.1
11199 19:27:13.240448 Starting test lava.0_timesync-off (13420384_1.6.2.3.1)
11200 19:27:13.240533 Skipping test definition patterns.
11201 19:27:13.243327 + systemctl stop systemd-timesyncd
11202 19:27:13.326064 + set +x
11203 19:27:13.329482 <LAVA_SIGNAL_ENDRUN 0_timesync-off 13420384_1.6.2.3.1>
11204 19:27:13.329775 Received signal: <ENDRUN> 0_timesync-off 13420384_1.6.2.3.1
11205 19:27:13.329887 Ending use of test pattern.
11206 19:27:13.329986 Ending test lava.0_timesync-off (13420384_1.6.2.3.1), duration 0.09
11208 19:27:13.402665 + export TESTRUN_ID=1_kselftest-dt
11209 19:27:13.405804 + TESTRUN_ID=1_kselftest-dt
11210 19:27:13.409064 + cd /lava-13420384/0/tests/1_kselftest-dt
11211 19:27:13.412307 ++ cat uuid
11212 19:27:13.416535 + UUID=13420384_1.6.2.3.5
11213 19:27:13.416614 + set +x
11214 19:27:13.423399 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 13420384_1.6.2.3.5>
11215 19:27:13.423666 Received signal: <STARTRUN> 1_kselftest-dt 13420384_1.6.2.3.5
11216 19:27:13.423738 Starting test lava.1_kselftest-dt (13420384_1.6.2.3.5)
11217 19:27:13.423823 Skipping test definition patterns.
11218 19:27:13.426927 + cd ./automated/linux/kselftest/
11219 19:27:13.449639 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11220 19:27:13.498673 INFO: install_deps skipped
11221 19:27:14.001290 --2024-04-18 19:27:13-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11222 19:27:14.014789 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11223 19:27:14.144801 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11224 19:27:14.274120 HTTP request sent, awaiting response... 200 OK
11225 19:27:14.277647 Length: 1651832 (1.6M) [application/octet-stream]
11226 19:27:14.280446 Saving to: 'kselftest_armhf.tar.gz'
11227 19:27:14.280551
11228 19:27:14.280648
11229 19:27:14.533211 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11230 19:27:14.792643 kselftest_armhf.tar 2%[ ] 47.81K 182KB/s
11231 19:27:15.082983 kselftest_armhf.tar 13%[=> ] 217.50K 413KB/s
11232 19:27:15.215730 kselftest_armhf.tar 39%[======> ] 636.06K 774KB/s
11233 19:27:15.222457 kselftest_armhf.tar 100%[===================>] 1.58M 1.65MB/s in 1.0s
11234 19:27:15.222605
11235 19:27:15.367977 2024-04-18 19:27:15 (1.65 MB/s) - 'kselftest_armhf.tar.gz' saved [1651832/1651832]
11236 19:27:15.368121
11237 19:27:20.285012 skiplist:
11238 19:27:20.288366 ========================================
11239 19:27:20.291300 ========================================
11240 19:27:20.371369 ============== Tests to run ===============
11241 19:27:20.377727 ===========End Tests to run ===============
11242 19:27:20.381945 shardfile-dt fail
11243 19:27:20.407777 ./kselftest.sh: 131: cannot open /lava-13420384/0/tests/1_kselftest-dt/automated/linux/kselftest/output/kselftest.txt: No such file
11244 19:27:20.411366 + ../../utils/send-to-lava.sh ./output/result.txt
11245 19:27:20.486584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=fail>
11246 19:27:20.486713 + set +x
11247 19:27:20.486961 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=fail
11249 19:27:20.493198 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 13420384_1.6.2.3.5>
11250 19:27:20.493281 <LAVA_TEST_RUNNER EXIT>
11251 19:27:20.493514 Received signal: <ENDRUN> 1_kselftest-dt 13420384_1.6.2.3.5
11252 19:27:20.493609 Ending use of test pattern.
11253 19:27:20.493707 Ending test lava.1_kselftest-dt (13420384_1.6.2.3.5), duration 7.07
11255 19:27:20.493937 ok: lava_test_shell seems to have completed
11256 19:27:20.494030 shardfile-dt: fail
11257 19:27:20.494117 end: 3.1 lava-test-shell (duration 00:00:08) [common]
11258 19:27:20.494207 end: 3 lava-test-retry (duration 00:00:08) [common]
11259 19:27:20.494295 start: 4 finalize (timeout 00:07:20) [common]
11260 19:27:20.494383 start: 4.1 power-off (timeout 00:00:30) [common]
11261 19:27:20.494537 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=off'
11262 19:27:20.569929 >> Command sent successfully.
11263 19:27:20.572381 Returned 0 in 0 seconds
11264 19:27:20.672748 end: 4.1 power-off (duration 00:00:00) [common]
11266 19:27:20.673139 start: 4.2 read-feedback (timeout 00:07:20) [common]
11267 19:27:20.673434 Listened to connection for namespace 'common' for up to 1s
11268 19:27:20.673735 Listened to connection for namespace 'common' for up to 1s
11269 19:27:21.674347 Finalising connection for namespace 'common'
11270 19:27:21.674555 Disconnecting from shell: Finalise
11271 19:27:21.674673 / #
11272 19:27:21.775029 end: 4.2 read-feedback (duration 00:00:01) [common]
11273 19:27:21.775213 end: 4 finalize (duration 00:00:01) [common]
11274 19:27:21.775365 Cleaning after the job
11275 19:27:21.775511 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13420384/tftp-deploy-v1rk1d3v/ramdisk
11276 19:27:21.777746 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13420384/tftp-deploy-v1rk1d3v/kernel
11277 19:27:21.789067 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13420384/tftp-deploy-v1rk1d3v/dtb
11278 19:27:21.789309 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13420384/tftp-deploy-v1rk1d3v/nfsrootfs
11279 19:27:21.855564 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13420384/tftp-deploy-v1rk1d3v/modules
11280 19:27:21.861712 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/13420384
11281 19:27:22.445623 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/13420384
11282 19:27:22.445786 Job finished correctly