Boot log: mt8192-asurada-spherion-r0
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Kernel Errors: 0
- Boot result: UNKNOWN
1 19:28:46.215982 lava-dispatcher, installed at version: 2024.01
2 19:28:46.216188 start: 0 validate
3 19:28:46.216320 Start time: 2024-04-18 19:28:46.216313+00:00 (UTC)
4 19:28:46.216442 Using caching service: 'http://localhost/cache/?uri=%s'
5 19:28:46.216571 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 19:28:46.479695 Using caching service: 'http://localhost/cache/?uri=%s'
7 19:28:46.479857 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 19:28:46.745581 Using caching service: 'http://localhost/cache/?uri=%s'
9 19:28:46.745790 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 19:28:47.002406 Using caching service: 'http://localhost/cache/?uri=%s'
11 19:28:47.002582 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 19:28:47.268269 Using caching service: 'http://localhost/cache/?uri=%s'
13 19:28:47.268449 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 19:28:47.527956 validate duration: 1.31
16 19:28:47.528218 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 19:28:47.528313 start: 1.1 download-retry (timeout 00:10:00) [common]
18 19:28:47.528455 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 19:28:47.528626 Not decompressing ramdisk as can be used compressed.
20 19:28:47.528722 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 19:28:47.528790 saving as /var/lib/lava/dispatcher/tmp/13420376/tftp-deploy-2a_ifze_/ramdisk/initrd.cpio.gz
22 19:28:47.528859 total size: 5628169 (5 MB)
23 19:28:47.530033 progress 0 % (0 MB)
24 19:28:47.531761 progress 5 % (0 MB)
25 19:28:47.533472 progress 10 % (0 MB)
26 19:28:47.534980 progress 15 % (0 MB)
27 19:28:47.536541 progress 20 % (1 MB)
28 19:28:47.538043 progress 25 % (1 MB)
29 19:28:47.539643 progress 30 % (1 MB)
30 19:28:47.541300 progress 35 % (1 MB)
31 19:28:47.542740 progress 40 % (2 MB)
32 19:28:47.544298 progress 45 % (2 MB)
33 19:28:47.545772 progress 50 % (2 MB)
34 19:28:47.547345 progress 55 % (2 MB)
35 19:28:47.549037 progress 60 % (3 MB)
36 19:28:47.550446 progress 65 % (3 MB)
37 19:28:47.551984 progress 70 % (3 MB)
38 19:28:47.553414 progress 75 % (4 MB)
39 19:28:47.555003 progress 80 % (4 MB)
40 19:28:47.556475 progress 85 % (4 MB)
41 19:28:47.558021 progress 90 % (4 MB)
42 19:28:47.559580 progress 95 % (5 MB)
43 19:28:47.561030 progress 100 % (5 MB)
44 19:28:47.561246 5 MB downloaded in 0.03 s (165.73 MB/s)
45 19:28:47.561405 end: 1.1.1 http-download (duration 00:00:00) [common]
47 19:28:47.561650 end: 1.1 download-retry (duration 00:00:00) [common]
48 19:28:47.561736 start: 1.2 download-retry (timeout 00:10:00) [common]
49 19:28:47.561822 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 19:28:47.561953 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 19:28:47.562022 saving as /var/lib/lava/dispatcher/tmp/13420376/tftp-deploy-2a_ifze_/kernel/Image
52 19:28:47.562087 total size: 54286848 (51 MB)
53 19:28:47.562150 No compression specified
54 19:28:47.563345 progress 0 % (0 MB)
55 19:28:47.577918 progress 5 % (2 MB)
56 19:28:47.592627 progress 10 % (5 MB)
57 19:28:47.607278 progress 15 % (7 MB)
58 19:28:47.621519 progress 20 % (10 MB)
59 19:28:47.635764 progress 25 % (12 MB)
60 19:28:47.649860 progress 30 % (15 MB)
61 19:28:47.663945 progress 35 % (18 MB)
62 19:28:47.678911 progress 40 % (20 MB)
63 19:28:47.693429 progress 45 % (23 MB)
64 19:28:47.708448 progress 50 % (25 MB)
65 19:28:47.724009 progress 55 % (28 MB)
66 19:28:47.739274 progress 60 % (31 MB)
67 19:28:47.754576 progress 65 % (33 MB)
68 19:28:47.769677 progress 70 % (36 MB)
69 19:28:47.784769 progress 75 % (38 MB)
70 19:28:47.799928 progress 80 % (41 MB)
71 19:28:47.814803 progress 85 % (44 MB)
72 19:28:47.828980 progress 90 % (46 MB)
73 19:28:47.842894 progress 95 % (49 MB)
74 19:28:47.856611 progress 100 % (51 MB)
75 19:28:47.856847 51 MB downloaded in 0.29 s (175.64 MB/s)
76 19:28:47.856999 end: 1.2.1 http-download (duration 00:00:00) [common]
78 19:28:47.857237 end: 1.2 download-retry (duration 00:00:00) [common]
79 19:28:47.857326 start: 1.3 download-retry (timeout 00:10:00) [common]
80 19:28:47.857447 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 19:28:47.857634 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 19:28:47.857718 saving as /var/lib/lava/dispatcher/tmp/13420376/tftp-deploy-2a_ifze_/dtb/mt8192-asurada-spherion-r0.dtb
83 19:28:47.857783 total size: 47230 (0 MB)
84 19:28:47.857846 No compression specified
85 19:28:47.858966 progress 69 % (0 MB)
86 19:28:47.859274 progress 100 % (0 MB)
87 19:28:47.859428 0 MB downloaded in 0.00 s (27.42 MB/s)
88 19:28:47.859552 end: 1.3.1 http-download (duration 00:00:00) [common]
90 19:28:47.859773 end: 1.3 download-retry (duration 00:00:00) [common]
91 19:28:47.859860 start: 1.4 download-retry (timeout 00:10:00) [common]
92 19:28:47.859943 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 19:28:47.860095 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 19:28:47.860164 saving as /var/lib/lava/dispatcher/tmp/13420376/tftp-deploy-2a_ifze_/nfsrootfs/full.rootfs.tar
95 19:28:47.860227 total size: 120894716 (115 MB)
96 19:28:47.860325 Using unxz to decompress xz
97 19:28:47.864549 progress 0 % (0 MB)
98 19:28:48.214467 progress 5 % (5 MB)
99 19:28:48.571708 progress 10 % (11 MB)
100 19:28:48.922207 progress 15 % (17 MB)
101 19:28:49.250799 progress 20 % (23 MB)
102 19:28:49.543010 progress 25 % (28 MB)
103 19:28:49.901702 progress 30 % (34 MB)
104 19:28:50.240971 progress 35 % (40 MB)
105 19:28:50.407332 progress 40 % (46 MB)
106 19:28:50.585663 progress 45 % (51 MB)
107 19:28:50.896970 progress 50 % (57 MB)
108 19:28:51.272204 progress 55 % (63 MB)
109 19:28:51.619824 progress 60 % (69 MB)
110 19:28:51.960032 progress 65 % (74 MB)
111 19:28:52.302468 progress 70 % (80 MB)
112 19:28:52.659012 progress 75 % (86 MB)
113 19:28:52.998833 progress 80 % (92 MB)
114 19:28:53.340266 progress 85 % (98 MB)
115 19:28:53.696727 progress 90 % (103 MB)
116 19:28:54.024528 progress 95 % (109 MB)
117 19:28:54.381733 progress 100 % (115 MB)
118 19:28:54.387141 115 MB downloaded in 6.53 s (17.66 MB/s)
119 19:28:54.387435 end: 1.4.1 http-download (duration 00:00:07) [common]
121 19:28:54.387841 end: 1.4 download-retry (duration 00:00:07) [common]
122 19:28:54.387970 start: 1.5 download-retry (timeout 00:09:53) [common]
123 19:28:54.388111 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 19:28:54.388303 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 19:28:54.388406 saving as /var/lib/lava/dispatcher/tmp/13420376/tftp-deploy-2a_ifze_/modules/modules.tar
126 19:28:54.388501 total size: 8631416 (8 MB)
127 19:28:54.388599 Using unxz to decompress xz
128 19:28:54.393141 progress 0 % (0 MB)
129 19:28:54.413284 progress 5 % (0 MB)
130 19:28:54.439059 progress 10 % (0 MB)
131 19:28:54.463923 progress 15 % (1 MB)
132 19:28:54.487073 progress 20 % (1 MB)
133 19:28:54.511578 progress 25 % (2 MB)
134 19:28:54.537813 progress 30 % (2 MB)
135 19:28:54.561813 progress 35 % (2 MB)
136 19:28:54.588587 progress 40 % (3 MB)
137 19:28:54.612589 progress 45 % (3 MB)
138 19:28:54.637335 progress 50 % (4 MB)
139 19:28:54.661883 progress 55 % (4 MB)
140 19:28:54.690004 progress 60 % (4 MB)
141 19:28:54.715611 progress 65 % (5 MB)
142 19:28:54.740514 progress 70 % (5 MB)
143 19:28:54.764531 progress 75 % (6 MB)
144 19:28:54.790009 progress 80 % (6 MB)
145 19:28:54.815715 progress 85 % (7 MB)
146 19:28:54.844108 progress 90 % (7 MB)
147 19:28:54.872765 progress 95 % (7 MB)
148 19:28:54.898589 progress 100 % (8 MB)
149 19:28:54.903898 8 MB downloaded in 0.52 s (15.97 MB/s)
150 19:28:54.904190 end: 1.5.1 http-download (duration 00:00:01) [common]
152 19:28:54.904606 end: 1.5 download-retry (duration 00:00:01) [common]
153 19:28:54.904740 start: 1.6 prepare-tftp-overlay (timeout 00:09:53) [common]
154 19:28:54.904869 start: 1.6.1 extract-nfsrootfs (timeout 00:09:53) [common]
155 19:28:58.365444 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/13420376/extract-nfsrootfs-h_kjid8j
156 19:28:58.365637 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 19:28:58.365735 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 19:28:58.365906 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/13420376/lava-overlay-2ktx8xw3
159 19:28:58.366034 makedir: /var/lib/lava/dispatcher/tmp/13420376/lava-overlay-2ktx8xw3/lava-13420376/bin
160 19:28:58.366137 makedir: /var/lib/lava/dispatcher/tmp/13420376/lava-overlay-2ktx8xw3/lava-13420376/tests
161 19:28:58.366236 makedir: /var/lib/lava/dispatcher/tmp/13420376/lava-overlay-2ktx8xw3/lava-13420376/results
162 19:28:58.366376 Creating /var/lib/lava/dispatcher/tmp/13420376/lava-overlay-2ktx8xw3/lava-13420376/bin/lava-add-keys
163 19:28:58.366520 Creating /var/lib/lava/dispatcher/tmp/13420376/lava-overlay-2ktx8xw3/lava-13420376/bin/lava-add-sources
164 19:28:58.366648 Creating /var/lib/lava/dispatcher/tmp/13420376/lava-overlay-2ktx8xw3/lava-13420376/bin/lava-background-process-start
165 19:28:58.366775 Creating /var/lib/lava/dispatcher/tmp/13420376/lava-overlay-2ktx8xw3/lava-13420376/bin/lava-background-process-stop
166 19:28:58.366899 Creating /var/lib/lava/dispatcher/tmp/13420376/lava-overlay-2ktx8xw3/lava-13420376/bin/lava-common-functions
167 19:28:58.367023 Creating /var/lib/lava/dispatcher/tmp/13420376/lava-overlay-2ktx8xw3/lava-13420376/bin/lava-echo-ipv4
168 19:28:58.367147 Creating /var/lib/lava/dispatcher/tmp/13420376/lava-overlay-2ktx8xw3/lava-13420376/bin/lava-install-packages
169 19:28:58.367271 Creating /var/lib/lava/dispatcher/tmp/13420376/lava-overlay-2ktx8xw3/lava-13420376/bin/lava-installed-packages
170 19:28:58.367393 Creating /var/lib/lava/dispatcher/tmp/13420376/lava-overlay-2ktx8xw3/lava-13420376/bin/lava-os-build
171 19:28:58.367515 Creating /var/lib/lava/dispatcher/tmp/13420376/lava-overlay-2ktx8xw3/lava-13420376/bin/lava-probe-channel
172 19:28:58.367636 Creating /var/lib/lava/dispatcher/tmp/13420376/lava-overlay-2ktx8xw3/lava-13420376/bin/lava-probe-ip
173 19:28:58.367760 Creating /var/lib/lava/dispatcher/tmp/13420376/lava-overlay-2ktx8xw3/lava-13420376/bin/lava-target-ip
174 19:28:58.367886 Creating /var/lib/lava/dispatcher/tmp/13420376/lava-overlay-2ktx8xw3/lava-13420376/bin/lava-target-mac
175 19:28:58.368007 Creating /var/lib/lava/dispatcher/tmp/13420376/lava-overlay-2ktx8xw3/lava-13420376/bin/lava-target-storage
176 19:28:58.368132 Creating /var/lib/lava/dispatcher/tmp/13420376/lava-overlay-2ktx8xw3/lava-13420376/bin/lava-test-case
177 19:28:58.368256 Creating /var/lib/lava/dispatcher/tmp/13420376/lava-overlay-2ktx8xw3/lava-13420376/bin/lava-test-event
178 19:28:58.368377 Creating /var/lib/lava/dispatcher/tmp/13420376/lava-overlay-2ktx8xw3/lava-13420376/bin/lava-test-feedback
179 19:28:58.368500 Creating /var/lib/lava/dispatcher/tmp/13420376/lava-overlay-2ktx8xw3/lava-13420376/bin/lava-test-raise
180 19:28:58.368622 Creating /var/lib/lava/dispatcher/tmp/13420376/lava-overlay-2ktx8xw3/lava-13420376/bin/lava-test-reference
181 19:28:58.368745 Creating /var/lib/lava/dispatcher/tmp/13420376/lava-overlay-2ktx8xw3/lava-13420376/bin/lava-test-runner
182 19:28:58.368867 Creating /var/lib/lava/dispatcher/tmp/13420376/lava-overlay-2ktx8xw3/lava-13420376/bin/lava-test-set
183 19:28:58.368987 Creating /var/lib/lava/dispatcher/tmp/13420376/lava-overlay-2ktx8xw3/lava-13420376/bin/lava-test-shell
184 19:28:58.369113 Updating /var/lib/lava/dispatcher/tmp/13420376/lava-overlay-2ktx8xw3/lava-13420376/bin/lava-add-keys (debian)
185 19:28:58.369263 Updating /var/lib/lava/dispatcher/tmp/13420376/lava-overlay-2ktx8xw3/lava-13420376/bin/lava-add-sources (debian)
186 19:28:58.369408 Updating /var/lib/lava/dispatcher/tmp/13420376/lava-overlay-2ktx8xw3/lava-13420376/bin/lava-install-packages (debian)
187 19:28:58.369549 Updating /var/lib/lava/dispatcher/tmp/13420376/lava-overlay-2ktx8xw3/lava-13420376/bin/lava-installed-packages (debian)
188 19:28:58.369687 Updating /var/lib/lava/dispatcher/tmp/13420376/lava-overlay-2ktx8xw3/lava-13420376/bin/lava-os-build (debian)
189 19:28:58.369808 Creating /var/lib/lava/dispatcher/tmp/13420376/lava-overlay-2ktx8xw3/lava-13420376/environment
190 19:28:58.369907 LAVA metadata
191 19:28:58.369976 - LAVA_JOB_ID=13420376
192 19:28:58.370040 - LAVA_DISPATCHER_IP=192.168.201.1
193 19:28:58.370141 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
194 19:28:58.370207 skipped lava-vland-overlay
195 19:28:58.370282 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 19:28:58.370398 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
197 19:28:58.370458 skipped lava-multinode-overlay
198 19:28:58.370529 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 19:28:58.370605 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
200 19:28:58.370677 Loading test definitions
201 19:28:58.370762 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
202 19:28:58.370834 Using /lava-13420376 at stage 0
203 19:28:58.371108 uuid=13420376_1.6.2.3.1 testdef=None
204 19:28:58.371195 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 19:28:58.371279 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
206 19:28:58.371717 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 19:28:58.371933 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
209 19:28:58.372498 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 19:28:58.372728 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
212 19:28:58.373254 runner path: /var/lib/lava/dispatcher/tmp/13420376/lava-overlay-2ktx8xw3/lava-13420376/0/tests/0_timesync-off test_uuid 13420376_1.6.2.3.1
213 19:28:58.373409 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 19:28:58.373631 start: 1.6.2.3.5 git-repo-action (timeout 00:09:49) [common]
216 19:28:58.373703 Using /lava-13420376 at stage 0
217 19:28:58.373798 Fetching tests from https://github.com/kernelci/test-definitions.git
218 19:28:58.373885 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/13420376/lava-overlay-2ktx8xw3/lava-13420376/0/tests/1_kselftest-rtc'
219 19:29:00.392985 Running '/usr/bin/git checkout kernelci.org
220 19:29:00.538947 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/13420376/lava-overlay-2ktx8xw3/lava-13420376/0/tests/1_kselftest-rtc/automated/linux/kselftest/kselftest.yaml
221 19:29:00.539811 uuid=13420376_1.6.2.3.5 testdef=None
222 19:29:00.539981 end: 1.6.2.3.5 git-repo-action (duration 00:00:02) [common]
224 19:29:00.540253 start: 1.6.2.3.6 test-overlay (timeout 00:09:47) [common]
225 19:29:00.541002 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 19:29:00.541363 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:47) [common]
228 19:29:00.542339 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 19:29:00.542601 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:47) [common]
231 19:29:00.543517 runner path: /var/lib/lava/dispatcher/tmp/13420376/lava-overlay-2ktx8xw3/lava-13420376/0/tests/1_kselftest-rtc test_uuid 13420376_1.6.2.3.5
232 19:29:00.543614 BOARD='mt8192-asurada-spherion-r0'
233 19:29:00.543691 BRANCH='cip'
234 19:29:00.543770 SKIPFILE='/dev/null'
235 19:29:00.543866 SKIP_INSTALL='True'
236 19:29:00.543962 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 19:29:00.544062 TST_CASENAME=''
238 19:29:00.544158 TST_CMDFILES='rtc'
239 19:29:00.544354 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 19:29:00.544712 Creating lava-test-runner.conf files
242 19:29:00.544814 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/13420376/lava-overlay-2ktx8xw3/lava-13420376/0 for stage 0
243 19:29:00.544951 - 0_timesync-off
244 19:29:00.545053 - 1_kselftest-rtc
245 19:29:00.545193 end: 1.6.2.3 test-definition (duration 00:00:02) [common]
246 19:29:00.545321 start: 1.6.2.4 compress-overlay (timeout 00:09:47) [common]
247 19:29:08.000469 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 19:29:08.000631 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:40) [common]
249 19:29:08.000724 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 19:29:08.000818 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
251 19:29:08.000908 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:40) [common]
252 19:29:08.162817 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 19:29:08.163201 start: 1.6.4 extract-modules (timeout 00:09:39) [common]
254 19:29:08.163317 extracting modules file /var/lib/lava/dispatcher/tmp/13420376/tftp-deploy-2a_ifze_/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13420376/extract-nfsrootfs-h_kjid8j
255 19:29:08.370934 extracting modules file /var/lib/lava/dispatcher/tmp/13420376/tftp-deploy-2a_ifze_/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13420376/extract-overlay-ramdisk-q9fax_hw/ramdisk
256 19:29:08.584888 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 19:29:08.585069 start: 1.6.5 apply-overlay-tftp (timeout 00:09:39) [common]
258 19:29:08.585171 [common] Applying overlay to NFS
259 19:29:08.585245 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13420376/compress-overlay-fntom_z0/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/13420376/extract-nfsrootfs-h_kjid8j
260 19:29:09.479798 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 19:29:09.479974 start: 1.6.6 configure-preseed-file (timeout 00:09:38) [common]
262 19:29:09.480069 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 19:29:09.480158 start: 1.6.7 compress-ramdisk (timeout 00:09:38) [common]
264 19:29:09.480235 Building ramdisk /var/lib/lava/dispatcher/tmp/13420376/extract-overlay-ramdisk-q9fax_hw/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/13420376/extract-overlay-ramdisk-q9fax_hw/ramdisk
265 19:29:09.816696 >> 130624 blocks
266 19:29:11.854762 rename /var/lib/lava/dispatcher/tmp/13420376/extract-overlay-ramdisk-q9fax_hw/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/13420376/tftp-deploy-2a_ifze_/ramdisk/ramdisk.cpio.gz
267 19:29:11.855217 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 19:29:11.855346 start: 1.6.8 prepare-kernel (timeout 00:09:36) [common]
269 19:29:11.855450 start: 1.6.8.1 prepare-fit (timeout 00:09:36) [common]
270 19:29:11.855559 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/13420376/tftp-deploy-2a_ifze_/kernel/Image'
271 19:29:24.796145 Returned 0 in 12 seconds
272 19:29:24.897082 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/13420376/tftp-deploy-2a_ifze_/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/13420376/tftp-deploy-2a_ifze_/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/13420376/tftp-deploy-2a_ifze_/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/13420376/tftp-deploy-2a_ifze_/kernel/image.itb
273 19:29:25.299455 output: FIT description: Kernel Image image with one or more FDT blobs
274 19:29:25.299813 output: Created: Thu Apr 18 20:29:25 2024
275 19:29:25.299889 output: Image 0 (kernel-1)
276 19:29:25.299973 output: Description:
277 19:29:25.300039 output: Created: Thu Apr 18 20:29:25 2024
278 19:29:25.300099 output: Type: Kernel Image
279 19:29:25.300161 output: Compression: lzma compressed
280 19:29:25.300219 output: Data Size: 12910355 Bytes = 12607.77 KiB = 12.31 MiB
281 19:29:25.300277 output: Architecture: AArch64
282 19:29:25.300333 output: OS: Linux
283 19:29:25.300390 output: Load Address: 0x00000000
284 19:29:25.300448 output: Entry Point: 0x00000000
285 19:29:25.300504 output: Hash algo: crc32
286 19:29:25.300600 output: Hash value: bbac8b0b
287 19:29:25.300687 output: Image 1 (fdt-1)
288 19:29:25.300778 output: Description: mt8192-asurada-spherion-r0
289 19:29:25.300869 output: Created: Thu Apr 18 20:29:25 2024
290 19:29:25.300955 output: Type: Flat Device Tree
291 19:29:25.301045 output: Compression: uncompressed
292 19:29:25.301128 output: Data Size: 47230 Bytes = 46.12 KiB = 0.05 MiB
293 19:29:25.301211 output: Architecture: AArch64
294 19:29:25.301293 output: Hash algo: crc32
295 19:29:25.301375 output: Hash value: 4bf0d1ac
296 19:29:25.301458 output: Image 2 (ramdisk-1)
297 19:29:25.301539 output: Description: unavailable
298 19:29:25.301625 output: Created: Thu Apr 18 20:29:25 2024
299 19:29:25.301682 output: Type: RAMDisk Image
300 19:29:25.301736 output: Compression: Unknown Compression
301 19:29:25.301789 output: Data Size: 18776771 Bytes = 18336.69 KiB = 17.91 MiB
302 19:29:25.301842 output: Architecture: AArch64
303 19:29:25.301894 output: OS: Linux
304 19:29:25.301947 output: Load Address: unavailable
305 19:29:25.301999 output: Entry Point: unavailable
306 19:29:25.302052 output: Hash algo: crc32
307 19:29:25.302103 output: Hash value: 4af5550e
308 19:29:25.302155 output: Default Configuration: 'conf-1'
309 19:29:25.302208 output: Configuration 0 (conf-1)
310 19:29:25.302272 output: Description: mt8192-asurada-spherion-r0
311 19:29:25.302382 output: Kernel: kernel-1
312 19:29:25.302436 output: Init Ramdisk: ramdisk-1
313 19:29:25.302492 output: FDT: fdt-1
314 19:29:25.302556 output: Loadables: kernel-1
315 19:29:25.302609 output:
316 19:29:25.302820 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 19:29:25.302918 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 19:29:25.303024 end: 1.6 prepare-tftp-overlay (duration 00:00:30) [common]
319 19:29:25.303115 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:22) [common]
320 19:29:25.303198 No LXC device requested
321 19:29:25.303310 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 19:29:25.303412 start: 1.8 deploy-device-env (timeout 00:09:22) [common]
323 19:29:25.303491 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 19:29:25.303559 Checking files for TFTP limit of 4294967296 bytes.
325 19:29:25.304068 end: 1 tftp-deploy (duration 00:00:38) [common]
326 19:29:25.304186 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 19:29:25.304280 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 19:29:25.304435 substitutions:
329 19:29:25.304532 - {DTB}: 13420376/tftp-deploy-2a_ifze_/dtb/mt8192-asurada-spherion-r0.dtb
330 19:29:25.304626 - {INITRD}: 13420376/tftp-deploy-2a_ifze_/ramdisk/ramdisk.cpio.gz
331 19:29:25.304714 - {KERNEL}: 13420376/tftp-deploy-2a_ifze_/kernel/Image
332 19:29:25.304801 - {LAVA_MAC}: None
333 19:29:25.304887 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/13420376/extract-nfsrootfs-h_kjid8j
334 19:29:25.304981 - {NFS_SERVER_IP}: 192.168.201.1
335 19:29:25.305067 - {PRESEED_CONFIG}: None
336 19:29:25.305151 - {PRESEED_LOCAL}: None
337 19:29:25.305273 - {RAMDISK}: 13420376/tftp-deploy-2a_ifze_/ramdisk/ramdisk.cpio.gz
338 19:29:25.305369 - {ROOT_PART}: None
339 19:29:25.305440 - {ROOT}: None
340 19:29:25.305497 - {SERVER_IP}: 192.168.201.1
341 19:29:25.305553 - {TEE}: None
342 19:29:25.305607 Parsed boot commands:
343 19:29:25.305661 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 19:29:25.305853 Parsed boot commands: tftpboot 192.168.201.1 13420376/tftp-deploy-2a_ifze_/kernel/image.itb 13420376/tftp-deploy-2a_ifze_/kernel/cmdline
345 19:29:25.305943 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 19:29:25.306028 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 19:29:25.306157 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 19:29:25.306277 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 19:29:25.306402 Not connected, no need to disconnect.
350 19:29:25.306478 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 19:29:25.306562 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 19:29:25.306629 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
353 19:29:25.310577 Setting prompt string to ['lava-test: # ']
354 19:29:25.310946 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 19:29:25.311062 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 19:29:25.311159 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 19:29:25.311252 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 19:29:25.311496 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
359 19:29:30.455345 >> Command sent successfully.
360 19:29:30.457743 Returned 0 in 5 seconds
361 19:29:30.558526 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 19:29:30.560298 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 19:29:30.561053 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 19:29:30.561557 Setting prompt string to 'Starting depthcharge on Spherion...'
366 19:29:30.562125 Changing prompt to 'Starting depthcharge on Spherion...'
367 19:29:30.562621 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 19:29:30.564152 [Enter `^Ec?' for help]
369 19:29:30.732381
370 19:29:30.733165
371 19:29:30.733815 F0: 102B 0000
372 19:29:30.734447
373 19:29:30.734994 F3: 1001 0000 [0200]
374 19:29:30.735895
375 19:29:30.736412 F3: 1001 0000
376 19:29:30.736920
377 19:29:30.737447 F7: 102D 0000
378 19:29:30.737915
379 19:29:30.738569 F1: 0000 0000
380 19:29:30.738955
381 19:29:30.739444 V0: 0000 0000 [0001]
382 19:29:30.739951
383 19:29:30.742373 00: 0007 8000
384 19:29:30.742823
385 19:29:30.743249 01: 0000 0000
386 19:29:30.743743
387 19:29:30.745636 BP: 0C00 0209 [0000]
388 19:29:30.746235
389 19:29:30.746776 G0: 1182 0000
390 19:29:30.747365
391 19:29:30.748945 EC: 0000 0021 [4000]
392 19:29:30.749540
393 19:29:30.750098 S7: 0000 0000 [0000]
394 19:29:30.750708
395 19:29:30.752935 CC: 0000 0000 [0001]
396 19:29:30.753499
397 19:29:30.754019 T0: 0000 0040 [010F]
398 19:29:30.754594
399 19:29:30.755018 Jump to BL
400 19:29:30.755587
401 19:29:30.779142
402 19:29:30.779584
403 19:29:30.779923
404 19:29:30.786943 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 19:29:30.790372 ARM64: Exception handlers installed.
406 19:29:30.793716 ARM64: Testing exception
407 19:29:30.797013 ARM64: Done test exception
408 19:29:30.803902 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 19:29:30.814161 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 19:29:30.820895 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 19:29:30.830942 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 19:29:30.837369 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 19:29:30.844250 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 19:29:30.856391 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 19:29:30.862812 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 19:29:30.881979 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 19:29:30.885330 WDT: Last reset was cold boot
418 19:29:30.889153 SPI1(PAD0) initialized at 2873684 Hz
419 19:29:30.891895 SPI5(PAD0) initialized at 992727 Hz
420 19:29:30.895488 VBOOT: Loading verstage.
421 19:29:30.901792 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 19:29:30.905568 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 19:29:30.908925 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 19:29:30.912181 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 19:29:30.919628 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 19:29:30.925835 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 19:29:30.937199 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 19:29:30.937794
429 19:29:30.938175
430 19:29:30.947595 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 19:29:30.950839 ARM64: Exception handlers installed.
432 19:29:30.954268 ARM64: Testing exception
433 19:29:30.954835 ARM64: Done test exception
434 19:29:30.957650 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 19:29:30.964558 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 19:29:30.978260 Probing TPM: . done!
437 19:29:30.978774 TPM ready after 0 ms
438 19:29:30.985008 Connected to device vid:did:rid of 1ae0:0028:00
439 19:29:30.992044 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
440 19:29:31.052899 Initialized TPM device CR50 revision 0
441 19:29:31.063508 tlcl_send_startup: Startup return code is 0
442 19:29:31.064144 TPM: setup succeeded
443 19:29:31.074750 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 19:29:31.083579 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 19:29:31.098161 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 19:29:31.104574 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 19:29:31.108355 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 19:29:31.112181 in-header: 03 07 00 00 08 00 00 00
449 19:29:31.115523 in-data: aa e4 47 04 13 02 00 00
450 19:29:31.119147 Chrome EC: UHEPI supported
451 19:29:31.122378 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 19:29:31.126686 in-header: 03 95 00 00 08 00 00 00
453 19:29:31.130203 in-data: 18 20 20 08 00 00 00 00
454 19:29:31.130287 Phase 1
455 19:29:31.133996 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 19:29:31.141127 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 19:29:31.148789 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 19:29:31.148877 Recovery requested (1009000e)
459 19:29:31.161629 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 19:29:31.164882 tlcl_extend: response is 0
461 19:29:31.174386 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 19:29:31.179544 tlcl_extend: response is 0
463 19:29:31.186243 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 19:29:31.206694 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 19:29:31.213102 BS: bootblock times (exec / console): total (unknown) / 149 ms
466 19:29:31.213194
467 19:29:31.213266
468 19:29:31.222802 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 19:29:31.226352 ARM64: Exception handlers installed.
470 19:29:31.229515 ARM64: Testing exception
471 19:29:31.229631 ARM64: Done test exception
472 19:29:31.252635 pmic_efuse_setting: Set efuses in 11 msecs
473 19:29:31.255773 pmwrap_interface_init: Select PMIF_VLD_RDY
474 19:29:31.262203 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 19:29:31.265556 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 19:29:31.273158 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 19:29:31.276618 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 19:29:31.280521 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 19:29:31.284014 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 19:29:31.291368 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 19:29:31.295379 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 19:29:31.299248 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 19:29:31.306598 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 19:29:31.310126 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 19:29:31.313899 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 19:29:31.317749 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 19:29:31.325484 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 19:29:31.329167 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 19:29:31.336112 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 19:29:31.343539 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 19:29:31.347973 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 19:29:31.351388 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 19:29:31.358650 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 19:29:31.362563 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 19:29:31.370432 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 19:29:31.373930 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 19:29:31.380960 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 19:29:31.384949 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 19:29:31.392544 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 19:29:31.396512 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 19:29:31.400453 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 19:29:31.407915 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 19:29:31.411194 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 19:29:31.415070 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 19:29:31.421796 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 19:29:31.425559 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 19:29:31.433026 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 19:29:31.437020 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 19:29:31.440957 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 19:29:31.448228 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 19:29:31.452042 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 19:29:31.455310 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 19:29:31.459282 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 19:29:31.466359 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 19:29:31.470100 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 19:29:31.473509 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 19:29:31.477569 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 19:29:31.481442 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 19:29:31.488790 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 19:29:31.492224 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 19:29:31.495441 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 19:29:31.499243 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 19:29:31.502634 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 19:29:31.506134 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 19:29:31.513321 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 19:29:31.524188 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 19:29:31.527626 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 19:29:31.534743 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 19:29:31.546115 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 19:29:31.549906 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 19:29:31.553110 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 19:29:31.557136 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 19:29:31.565699 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x32
534 19:29:31.569702 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 19:29:31.574386 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 19:29:31.581569 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 19:29:31.589943 [RTC]rtc_get_frequency_meter,154: input=15, output=759
538 19:29:31.599664 [RTC]rtc_get_frequency_meter,154: input=23, output=942
539 19:29:31.608565 [RTC]rtc_get_frequency_meter,154: input=19, output=850
540 19:29:31.618826 [RTC]rtc_get_frequency_meter,154: input=17, output=805
541 19:29:31.627775 [RTC]rtc_get_frequency_meter,154: input=16, output=782
542 19:29:31.637706 [RTC]rtc_get_frequency_meter,154: input=16, output=782
543 19:29:31.647882 [RTC]rtc_get_frequency_meter,154: input=17, output=803
544 19:29:31.651548 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
545 19:29:31.655018 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
546 19:29:31.658913 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 19:29:31.666792 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
548 19:29:31.670869 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 19:29:31.674207 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
550 19:29:31.674711 ADC[4]: Raw value=906573 ID=7
551 19:29:31.678112 ADC[3]: Raw value=213441 ID=1
552 19:29:31.682198 RAM Code: 0x71
553 19:29:31.685677 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 19:29:31.689419 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 19:29:31.697456 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 19:29:31.704831 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 19:29:31.708732 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 19:29:31.712313 in-header: 03 07 00 00 08 00 00 00
559 19:29:31.716061 in-data: aa e4 47 04 13 02 00 00
560 19:29:31.716499 Chrome EC: UHEPI supported
561 19:29:31.723192 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 19:29:31.727297 in-header: 03 95 00 00 08 00 00 00
563 19:29:31.731029 in-data: 18 20 20 08 00 00 00 00
564 19:29:31.734813 MRC: failed to locate region type 0.
565 19:29:31.738815 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 19:29:31.742253 DRAM-K: Running full calibration
567 19:29:31.749753 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 19:29:31.750184 header.status = 0x0
569 19:29:31.753410 header.version = 0x6 (expected: 0x6)
570 19:29:31.757559 header.size = 0xd00 (expected: 0xd00)
571 19:29:31.761140 header.flags = 0x0
572 19:29:31.764617 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 19:29:31.783980 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
574 19:29:31.791770 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 19:29:31.795465 dram_init: ddr_geometry: 2
576 19:29:31.795895 [EMI] MDL number = 2
577 19:29:31.799593 [EMI] Get MDL freq = 0
578 19:29:31.800051 dram_init: ddr_type: 0
579 19:29:31.803262 is_discrete_lpddr4: 1
580 19:29:31.803770 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 19:29:31.806778
582 19:29:31.807293
583 19:29:31.807656 [Bian_co] ETT version 0.0.0.1
584 19:29:31.810637 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 19:29:31.814519
586 19:29:31.818593 dramc_set_vcore_voltage set vcore to 650000
587 19:29:31.819023 Read voltage for 800, 4
588 19:29:31.819367 Vio18 = 0
589 19:29:31.821803 Vcore = 650000
590 19:29:31.822232 Vdram = 0
591 19:29:31.822635 Vddq = 0
592 19:29:31.822959 Vmddr = 0
593 19:29:31.825927 dram_init: config_dvfs: 1
594 19:29:31.829459 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 19:29:31.837024 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 19:29:31.841099 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
597 19:29:31.845097 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
598 19:29:31.848273 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
599 19:29:31.852855 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
600 19:29:31.853310 MEM_TYPE=3, freq_sel=18
601 19:29:31.856057 sv_algorithm_assistance_LP4_1600
602 19:29:31.859333 ============ PULL DRAM RESETB DOWN ============
603 19:29:31.866331 ========== PULL DRAM RESETB DOWN end =========
604 19:29:31.869680 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 19:29:31.873022 ===================================
606 19:29:31.877005 LPDDR4 DRAM CONFIGURATION
607 19:29:31.880618 ===================================
608 19:29:31.881051 EX_ROW_EN[0] = 0x0
609 19:29:31.884121 EX_ROW_EN[1] = 0x0
610 19:29:31.884552 LP4Y_EN = 0x0
611 19:29:31.888235 WORK_FSP = 0x0
612 19:29:31.888667 WL = 0x2
613 19:29:31.889151 RL = 0x2
614 19:29:31.891548 BL = 0x2
615 19:29:31.891978 RPST = 0x0
616 19:29:31.895474 RD_PRE = 0x0
617 19:29:31.895928 WR_PRE = 0x1
618 19:29:31.898985 WR_PST = 0x0
619 19:29:31.899493 DBI_WR = 0x0
620 19:29:31.902408 DBI_RD = 0x0
621 19:29:31.902840 OTF = 0x1
622 19:29:31.905696 ===================================
623 19:29:31.909042 ===================================
624 19:29:31.912610 ANA top config
625 19:29:31.916029 ===================================
626 19:29:31.916462 DLL_ASYNC_EN = 0
627 19:29:31.918924 ALL_SLAVE_EN = 1
628 19:29:31.922628 NEW_RANK_MODE = 1
629 19:29:31.925960 DLL_IDLE_MODE = 1
630 19:29:31.926483 LP45_APHY_COMB_EN = 1
631 19:29:31.929393 TX_ODT_DIS = 1
632 19:29:31.933165 NEW_8X_MODE = 1
633 19:29:31.936512 ===================================
634 19:29:31.940133 ===================================
635 19:29:31.943239 data_rate = 1600
636 19:29:31.943729 CKR = 1
637 19:29:31.946516 DQ_P2S_RATIO = 8
638 19:29:31.950245 ===================================
639 19:29:31.952983 CA_P2S_RATIO = 8
640 19:29:31.956811 DQ_CA_OPEN = 0
641 19:29:31.960216 DQ_SEMI_OPEN = 0
642 19:29:31.963307 CA_SEMI_OPEN = 0
643 19:29:31.963824 CA_FULL_RATE = 0
644 19:29:31.966619 DQ_CKDIV4_EN = 1
645 19:29:31.969700 CA_CKDIV4_EN = 1
646 19:29:31.973107 CA_PREDIV_EN = 0
647 19:29:31.976440 PH8_DLY = 0
648 19:29:31.979708 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 19:29:31.980205 DQ_AAMCK_DIV = 4
650 19:29:31.983493 CA_AAMCK_DIV = 4
651 19:29:31.986811 CA_ADMCK_DIV = 4
652 19:29:31.990126 DQ_TRACK_CA_EN = 0
653 19:29:31.993336 CA_PICK = 800
654 19:29:31.996715 CA_MCKIO = 800
655 19:29:31.997234 MCKIO_SEMI = 0
656 19:29:32.000723 PLL_FREQ = 3068
657 19:29:32.004429 DQ_UI_PI_RATIO = 32
658 19:29:32.008724 CA_UI_PI_RATIO = 0
659 19:29:32.009156 ===================================
660 19:29:32.012403 ===================================
661 19:29:32.016151 memory_type:LPDDR4
662 19:29:32.016593 GP_NUM : 10
663 19:29:32.020026 SRAM_EN : 1
664 19:29:32.023482 MD32_EN : 0
665 19:29:32.023934 ===================================
666 19:29:32.026923 [ANA_INIT] >>>>>>>>>>>>>>
667 19:29:32.030984 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 19:29:32.034606 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 19:29:32.037920 ===================================
670 19:29:32.041274 data_rate = 1600,PCW = 0X7600
671 19:29:32.041700 ===================================
672 19:29:32.048105 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 19:29:32.051305 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 19:29:32.058289 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 19:29:32.061617 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 19:29:32.064838 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 19:29:32.067957 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 19:29:32.071312 [ANA_INIT] flow start
679 19:29:32.074506 [ANA_INIT] PLL >>>>>>>>
680 19:29:32.074936 [ANA_INIT] PLL <<<<<<<<
681 19:29:32.077862 [ANA_INIT] MIDPI >>>>>>>>
682 19:29:32.081792 [ANA_INIT] MIDPI <<<<<<<<
683 19:29:32.082225 [ANA_INIT] DLL >>>>>>>>
684 19:29:32.085122 [ANA_INIT] flow end
685 19:29:32.088444 ============ LP4 DIFF to SE enter ============
686 19:29:32.091561 ============ LP4 DIFF to SE exit ============
687 19:29:32.094762 [ANA_INIT] <<<<<<<<<<<<<
688 19:29:32.098044 [Flow] Enable top DCM control >>>>>
689 19:29:32.101408 [Flow] Enable top DCM control <<<<<
690 19:29:32.104742 Enable DLL master slave shuffle
691 19:29:32.111854 ==============================================================
692 19:29:32.112285 Gating Mode config
693 19:29:32.118043 ==============================================================
694 19:29:32.118518 Config description:
695 19:29:32.128220 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 19:29:32.134630 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 19:29:32.141831 SELPH_MODE 0: By rank 1: By Phase
698 19:29:32.144927 ==============================================================
699 19:29:32.148310 GAT_TRACK_EN = 1
700 19:29:32.151746 RX_GATING_MODE = 2
701 19:29:32.154567 RX_GATING_TRACK_MODE = 2
702 19:29:32.158578 SELPH_MODE = 1
703 19:29:32.161492 PICG_EARLY_EN = 1
704 19:29:32.164628 VALID_LAT_VALUE = 1
705 19:29:32.167701 ==============================================================
706 19:29:32.171455 Enter into Gating configuration >>>>
707 19:29:32.175052 Exit from Gating configuration <<<<
708 19:29:32.178157 Enter into DVFS_PRE_config >>>>>
709 19:29:32.191541 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 19:29:32.192149 Exit from DVFS_PRE_config <<<<<
711 19:29:32.195010 Enter into PICG configuration >>>>
712 19:29:32.198201 Exit from PICG configuration <<<<
713 19:29:32.201601 [RX_INPUT] configuration >>>>>
714 19:29:32.205105 [RX_INPUT] configuration <<<<<
715 19:29:32.211816 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 19:29:32.215118 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 19:29:32.221933 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 19:29:32.228541 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 19:29:32.235373 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 19:29:32.242358 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 19:29:32.245573 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 19:29:32.248978 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 19:29:32.252112 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 19:29:32.258762 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 19:29:32.262087 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 19:29:32.265396 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 19:29:32.268610 ===================================
728 19:29:32.272484 LPDDR4 DRAM CONFIGURATION
729 19:29:32.275320 ===================================
730 19:29:32.275755 EX_ROW_EN[0] = 0x0
731 19:29:32.278589 EX_ROW_EN[1] = 0x0
732 19:29:32.279048 LP4Y_EN = 0x0
733 19:29:32.281873 WORK_FSP = 0x0
734 19:29:32.282354 WL = 0x2
735 19:29:32.285320 RL = 0x2
736 19:29:32.285752 BL = 0x2
737 19:29:32.289178 RPST = 0x0
738 19:29:32.292240 RD_PRE = 0x0
739 19:29:32.292673 WR_PRE = 0x1
740 19:29:32.295278 WR_PST = 0x0
741 19:29:32.295707 DBI_WR = 0x0
742 19:29:32.298925 DBI_RD = 0x0
743 19:29:32.299371 OTF = 0x1
744 19:29:32.302055 ===================================
745 19:29:32.305307 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 19:29:32.309062 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 19:29:32.316056 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 19:29:32.319232 ===================================
749 19:29:32.319667 LPDDR4 DRAM CONFIGURATION
750 19:29:32.322521 ===================================
751 19:29:32.325765 EX_ROW_EN[0] = 0x10
752 19:29:32.328717 EX_ROW_EN[1] = 0x0
753 19:29:32.329151 LP4Y_EN = 0x0
754 19:29:32.332247 WORK_FSP = 0x0
755 19:29:32.332677 WL = 0x2
756 19:29:32.335977 RL = 0x2
757 19:29:32.336412 BL = 0x2
758 19:29:32.339276 RPST = 0x0
759 19:29:32.339704 RD_PRE = 0x0
760 19:29:32.342408 WR_PRE = 0x1
761 19:29:32.342842 WR_PST = 0x0
762 19:29:32.345761 DBI_WR = 0x0
763 19:29:32.346294 DBI_RD = 0x0
764 19:29:32.349623 OTF = 0x1
765 19:29:32.352610 ===================================
766 19:29:32.359102 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 19:29:32.362786 nWR fixed to 40
768 19:29:32.363318 [ModeRegInit_LP4] CH0 RK0
769 19:29:32.365967 [ModeRegInit_LP4] CH0 RK1
770 19:29:32.369101 [ModeRegInit_LP4] CH1 RK0
771 19:29:32.372379 [ModeRegInit_LP4] CH1 RK1
772 19:29:32.372810 match AC timing 13
773 19:29:32.375709 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 19:29:32.383196 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 19:29:32.385943 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 19:29:32.389042 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 19:29:32.395840 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 19:29:32.396340 [EMI DOE] emi_dcm 0
779 19:29:32.402748 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 19:29:32.403187 ==
781 19:29:32.406288 Dram Type= 6, Freq= 0, CH_0, rank 0
782 19:29:32.409886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 19:29:32.410509 ==
784 19:29:32.412796 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 19:29:32.419464 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 19:29:32.429599 [CA 0] Center 36 (6~67) winsize 62
787 19:29:32.432757 [CA 1] Center 36 (6~67) winsize 62
788 19:29:32.436090 [CA 2] Center 34 (4~65) winsize 62
789 19:29:32.439145 [CA 3] Center 33 (3~64) winsize 62
790 19:29:32.443129 [CA 4] Center 33 (3~64) winsize 62
791 19:29:32.445918 [CA 5] Center 32 (3~62) winsize 60
792 19:29:32.446540
793 19:29:32.449813 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 19:29:32.450484
795 19:29:32.453011 [CATrainingPosCal] consider 1 rank data
796 19:29:32.456252 u2DelayCellTimex100 = 270/100 ps
797 19:29:32.459305 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
798 19:29:32.462908 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
799 19:29:32.469499 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
800 19:29:32.472866 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
801 19:29:32.476463 CA4 delay=33 (3~64),Diff = 1 PI (7 cell)
802 19:29:32.479542 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
803 19:29:32.480047
804 19:29:32.482889 CA PerBit enable=1, Macro0, CA PI delay=32
805 19:29:32.483320
806 19:29:32.486167 [CBTSetCACLKResult] CA Dly = 32
807 19:29:32.486628 CS Dly: 5 (0~36)
808 19:29:32.486971 ==
809 19:29:32.489320 Dram Type= 6, Freq= 0, CH_0, rank 1
810 19:29:32.496278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 19:29:32.496817 ==
812 19:29:32.499899 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 19:29:32.506228 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 19:29:32.515772 [CA 0] Center 36 (6~67) winsize 62
815 19:29:32.519261 [CA 1] Center 36 (6~67) winsize 62
816 19:29:32.522727 [CA 2] Center 34 (3~65) winsize 63
817 19:29:32.525629 [CA 3] Center 33 (3~64) winsize 62
818 19:29:32.528867 [CA 4] Center 33 (2~64) winsize 63
819 19:29:32.532530 [CA 5] Center 32 (2~63) winsize 62
820 19:29:32.533034
821 19:29:32.535912 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 19:29:32.536392
823 19:29:32.539108 [CATrainingPosCal] consider 2 rank data
824 19:29:32.542550 u2DelayCellTimex100 = 270/100 ps
825 19:29:32.546234 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
826 19:29:32.549165 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
827 19:29:32.555754 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
828 19:29:32.558996 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
829 19:29:32.562719 CA4 delay=33 (3~64),Diff = 1 PI (7 cell)
830 19:29:32.565780 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
831 19:29:32.566417
832 19:29:32.569293 CA PerBit enable=1, Macro0, CA PI delay=32
833 19:29:32.569776
834 19:29:32.572492 [CBTSetCACLKResult] CA Dly = 32
835 19:29:32.572981 CS Dly: 5 (0~37)
836 19:29:32.573360
837 19:29:32.576237 ----->DramcWriteLeveling(PI) begin...
838 19:29:32.579251 ==
839 19:29:32.579734 Dram Type= 6, Freq= 0, CH_0, rank 0
840 19:29:32.586594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 19:29:32.587206 ==
842 19:29:32.587593 Write leveling (Byte 0): 33 => 33
843 19:29:32.590867 Write leveling (Byte 1): 30 => 30
844 19:29:32.594206 DramcWriteLeveling(PI) end<-----
845 19:29:32.594699
846 19:29:32.595046 ==
847 19:29:32.597401 Dram Type= 6, Freq= 0, CH_0, rank 0
848 19:29:32.601552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 19:29:32.601989 ==
850 19:29:32.604558 [Gating] SW mode calibration
851 19:29:32.611957 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 19:29:32.618606 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 19:29:32.622235 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 19:29:32.625608 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
855 19:29:32.631702 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
856 19:29:32.635018 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 19:29:32.638532 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 19:29:32.641723 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 19:29:32.648572 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 19:29:32.652371 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 19:29:32.655303 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 19:29:32.662147 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 19:29:32.665423 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 19:29:32.668108 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 19:29:32.675155 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 19:29:32.678333 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 19:29:32.681656 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 19:29:32.688448 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 19:29:32.691438 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 19:29:32.694866 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
871 19:29:32.701476 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
872 19:29:32.704991 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 19:29:32.708607 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 19:29:32.715285 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 19:29:32.718412 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 19:29:32.722081 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 19:29:32.728326 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 19:29:32.731493 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 19:29:32.734806 0 9 8 | B1->B0 | 2323 2d2d | 1 0 | (1 1) (0 0)
880 19:29:32.738471 0 9 12 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
881 19:29:32.745442 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 19:29:32.748789 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 19:29:32.751925 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 19:29:32.758430 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 19:29:32.761881 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 19:29:32.765012 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (1 0)
887 19:29:32.772052 0 10 8 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
888 19:29:32.775120 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
889 19:29:32.778563 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 19:29:32.785565 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 19:29:32.788875 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 19:29:32.792074 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 19:29:32.799028 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 19:29:32.802005 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
895 19:29:32.805647 0 11 8 | B1->B0 | 3030 4141 | 1 0 | (0 0) (0 0)
896 19:29:32.811942 0 11 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
897 19:29:32.815415 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 19:29:32.818713 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 19:29:32.825411 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 19:29:32.828986 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 19:29:32.832054 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 19:29:32.835226 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
903 19:29:32.841890 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
904 19:29:32.845659 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
905 19:29:32.848373 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 19:29:32.854933 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 19:29:32.858158 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 19:29:32.861569 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 19:29:32.868098 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 19:29:32.871461 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 19:29:32.874806 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 19:29:32.881979 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 19:29:32.884998 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 19:29:32.888442 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 19:29:32.895400 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 19:29:32.898612 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 19:29:32.901770 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 19:29:32.908695 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
919 19:29:32.911972 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
920 19:29:32.915171 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
921 19:29:32.918104 Total UI for P1: 0, mck2ui 16
922 19:29:32.921360 best dqsien dly found for B0: ( 0, 14, 6)
923 19:29:32.925481 Total UI for P1: 0, mck2ui 16
924 19:29:32.928635 best dqsien dly found for B1: ( 0, 14, 8)
925 19:29:32.931912 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
926 19:29:32.935840 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
927 19:29:32.936308
928 19:29:32.938788 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
929 19:29:32.942155 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
930 19:29:32.945755 [Gating] SW calibration Done
931 19:29:32.946290 ==
932 19:29:32.948981 Dram Type= 6, Freq= 0, CH_0, rank 0
933 19:29:32.951999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 19:29:32.955612 ==
935 19:29:32.956045 RX Vref Scan: 0
936 19:29:32.956414
937 19:29:32.958514 RX Vref 0 -> 0, step: 1
938 19:29:32.958961
939 19:29:32.962646 RX Delay -130 -> 252, step: 16
940 19:29:32.965201 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
941 19:29:32.968877 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
942 19:29:32.971875 iDelay=206, Bit 2, Center 93 (-18 ~ 205) 224
943 19:29:32.975726 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
944 19:29:32.982161 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
945 19:29:32.985310 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
946 19:29:32.989033 iDelay=206, Bit 6, Center 101 (-2 ~ 205) 208
947 19:29:32.992042 iDelay=206, Bit 7, Center 101 (-2 ~ 205) 208
948 19:29:32.995576 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
949 19:29:32.998826 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
950 19:29:33.006136 iDelay=206, Bit 10, Center 85 (-18 ~ 189) 208
951 19:29:33.009525 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
952 19:29:33.012940 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
953 19:29:33.016083 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
954 19:29:33.019526 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
955 19:29:33.026050 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
956 19:29:33.026673 ==
957 19:29:33.028804 Dram Type= 6, Freq= 0, CH_0, rank 0
958 19:29:33.032436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 19:29:33.032933 ==
960 19:29:33.033316 DQS Delay:
961 19:29:33.035591 DQS0 = 0, DQS1 = 0
962 19:29:33.036022 DQM Delay:
963 19:29:33.038990 DQM0 = 93, DQM1 = 85
964 19:29:33.039455 DQ Delay:
965 19:29:33.042331 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
966 19:29:33.045884 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
967 19:29:33.049295 DQ8 =77, DQ9 =69, DQ10 =85, DQ11 =77
968 19:29:33.052483 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
969 19:29:33.053024
970 19:29:33.053372
971 19:29:33.053691 ==
972 19:29:33.055635 Dram Type= 6, Freq= 0, CH_0, rank 0
973 19:29:33.058881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 19:29:33.062400 ==
975 19:29:33.062993
976 19:29:33.063379
977 19:29:33.063734 TX Vref Scan disable
978 19:29:33.066376 == TX Byte 0 ==
979 19:29:33.068795 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
980 19:29:33.072573 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
981 19:29:33.075841 == TX Byte 1 ==
982 19:29:33.079196 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
983 19:29:33.082490 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
984 19:29:33.082947 ==
985 19:29:33.085793 Dram Type= 6, Freq= 0, CH_0, rank 0
986 19:29:33.092819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 19:29:33.093355 ==
988 19:29:33.104478 TX Vref=22, minBit 9, minWin=27, winSum=448
989 19:29:33.107799 TX Vref=24, minBit 7, minWin=27, winSum=451
990 19:29:33.111186 TX Vref=26, minBit 10, minWin=27, winSum=456
991 19:29:33.114429 TX Vref=28, minBit 4, minWin=28, winSum=459
992 19:29:33.117783 TX Vref=30, minBit 8, minWin=28, winSum=458
993 19:29:33.121066 TX Vref=32, minBit 6, minWin=28, winSum=458
994 19:29:33.128103 [TxChooseVref] Worse bit 4, Min win 28, Win sum 459, Final Vref 28
995 19:29:33.128590
996 19:29:33.131366 Final TX Range 1 Vref 28
997 19:29:33.131861
998 19:29:33.132211 ==
999 19:29:33.134570 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 19:29:33.138044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 19:29:33.138546 ==
1002 19:29:33.141038
1003 19:29:33.141497
1004 19:29:33.141846 TX Vref Scan disable
1005 19:29:33.144663 == TX Byte 0 ==
1006 19:29:33.147789 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1007 19:29:33.151158 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1008 19:29:33.154478 == TX Byte 1 ==
1009 19:29:33.157843 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1010 19:29:33.161203 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1011 19:29:33.164467
1012 19:29:33.164901 [DATLAT]
1013 19:29:33.165253 Freq=800, CH0 RK0
1014 19:29:33.165614
1015 19:29:33.168306 DATLAT Default: 0xa
1016 19:29:33.168756 0, 0xFFFF, sum = 0
1017 19:29:33.171071 1, 0xFFFF, sum = 0
1018 19:29:33.171538 2, 0xFFFF, sum = 0
1019 19:29:33.174330 3, 0xFFFF, sum = 0
1020 19:29:33.174810 4, 0xFFFF, sum = 0
1021 19:29:33.178144 5, 0xFFFF, sum = 0
1022 19:29:33.178607 6, 0xFFFF, sum = 0
1023 19:29:33.181456 7, 0xFFFF, sum = 0
1024 19:29:33.184763 8, 0xFFFF, sum = 0
1025 19:29:33.185228 9, 0x0, sum = 1
1026 19:29:33.185584 10, 0x0, sum = 2
1027 19:29:33.187975 11, 0x0, sum = 3
1028 19:29:33.188407 12, 0x0, sum = 4
1029 19:29:33.191334 best_step = 10
1030 19:29:33.191885
1031 19:29:33.192431 ==
1032 19:29:33.194649 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 19:29:33.197913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 19:29:33.198386 ==
1035 19:29:33.201246 RX Vref Scan: 1
1036 19:29:33.201672
1037 19:29:33.202011 Set Vref Range= 32 -> 127
1038 19:29:33.202366
1039 19:29:33.204659 RX Vref 32 -> 127, step: 1
1040 19:29:33.205084
1041 19:29:33.208404 RX Delay -95 -> 252, step: 8
1042 19:29:33.208830
1043 19:29:33.211583 Set Vref, RX VrefLevel [Byte0]: 32
1044 19:29:33.214836 [Byte1]: 32
1045 19:29:33.215262
1046 19:29:33.218033 Set Vref, RX VrefLevel [Byte0]: 33
1047 19:29:33.221582 [Byte1]: 33
1048 19:29:33.225376
1049 19:29:33.225924 Set Vref, RX VrefLevel [Byte0]: 34
1050 19:29:33.228012 [Byte1]: 34
1051 19:29:33.232330
1052 19:29:33.232763 Set Vref, RX VrefLevel [Byte0]: 35
1053 19:29:33.236113 [Byte1]: 35
1054 19:29:33.240419
1055 19:29:33.240837 Set Vref, RX VrefLevel [Byte0]: 36
1056 19:29:33.243575 [Byte1]: 36
1057 19:29:33.248007
1058 19:29:33.248428 Set Vref, RX VrefLevel [Byte0]: 37
1059 19:29:33.251620 [Byte1]: 37
1060 19:29:33.255882
1061 19:29:33.256457 Set Vref, RX VrefLevel [Byte0]: 38
1062 19:29:33.259566 [Byte1]: 38
1063 19:29:33.263479
1064 19:29:33.263900 Set Vref, RX VrefLevel [Byte0]: 39
1065 19:29:33.266788 [Byte1]: 39
1066 19:29:33.271425
1067 19:29:33.271848 Set Vref, RX VrefLevel [Byte0]: 40
1068 19:29:33.274838 [Byte1]: 40
1069 19:29:33.278852
1070 19:29:33.279283 Set Vref, RX VrefLevel [Byte0]: 41
1071 19:29:33.282151 [Byte1]: 41
1072 19:29:33.285886
1073 19:29:33.286328 Set Vref, RX VrefLevel [Byte0]: 42
1074 19:29:33.289304 [Byte1]: 42
1075 19:29:33.292999
1076 19:29:33.293417 Set Vref, RX VrefLevel [Byte0]: 43
1077 19:29:33.296470 [Byte1]: 43
1078 19:29:33.301060
1079 19:29:33.301477 Set Vref, RX VrefLevel [Byte0]: 44
1080 19:29:33.304421 [Byte1]: 44
1081 19:29:33.308546
1082 19:29:33.308967 Set Vref, RX VrefLevel [Byte0]: 45
1083 19:29:33.311871 [Byte1]: 45
1084 19:29:33.316366
1085 19:29:33.316786 Set Vref, RX VrefLevel [Byte0]: 46
1086 19:29:33.319833 [Byte1]: 46
1087 19:29:33.323900
1088 19:29:33.324572 Set Vref, RX VrefLevel [Byte0]: 47
1089 19:29:33.326961 [Byte1]: 47
1090 19:29:33.331300
1091 19:29:33.331726 Set Vref, RX VrefLevel [Byte0]: 48
1092 19:29:33.334639 [Byte1]: 48
1093 19:29:33.339062
1094 19:29:33.339484 Set Vref, RX VrefLevel [Byte0]: 49
1095 19:29:33.342050 [Byte1]: 49
1096 19:29:33.346457
1097 19:29:33.346933 Set Vref, RX VrefLevel [Byte0]: 50
1098 19:29:33.349574 [Byte1]: 50
1099 19:29:33.354035
1100 19:29:33.354517 Set Vref, RX VrefLevel [Byte0]: 51
1101 19:29:33.357379 [Byte1]: 51
1102 19:29:33.362166
1103 19:29:33.362861 Set Vref, RX VrefLevel [Byte0]: 52
1104 19:29:33.365362 [Byte1]: 52
1105 19:29:33.369007
1106 19:29:33.369486 Set Vref, RX VrefLevel [Byte0]: 53
1107 19:29:33.372545 [Byte1]: 53
1108 19:29:33.377083
1109 19:29:33.377634 Set Vref, RX VrefLevel [Byte0]: 54
1110 19:29:33.380073 [Byte1]: 54
1111 19:29:33.384314
1112 19:29:33.384733 Set Vref, RX VrefLevel [Byte0]: 55
1113 19:29:33.387658 [Byte1]: 55
1114 19:29:33.391899
1115 19:29:33.392324 Set Vref, RX VrefLevel [Byte0]: 56
1116 19:29:33.395104 [Byte1]: 56
1117 19:29:33.399439
1118 19:29:33.399909 Set Vref, RX VrefLevel [Byte0]: 57
1119 19:29:33.403180 [Byte1]: 57
1120 19:29:33.407158
1121 19:29:33.407582 Set Vref, RX VrefLevel [Byte0]: 58
1122 19:29:33.410823 [Byte1]: 58
1123 19:29:33.414988
1124 19:29:33.415407 Set Vref, RX VrefLevel [Byte0]: 59
1125 19:29:33.418105 [Byte1]: 59
1126 19:29:33.422740
1127 19:29:33.423159 Set Vref, RX VrefLevel [Byte0]: 60
1128 19:29:33.426017 [Byte1]: 60
1129 19:29:33.430417
1130 19:29:33.430838 Set Vref, RX VrefLevel [Byte0]: 61
1131 19:29:33.433062 [Byte1]: 61
1132 19:29:33.437938
1133 19:29:33.438376 Set Vref, RX VrefLevel [Byte0]: 62
1134 19:29:33.441143 [Byte1]: 62
1135 19:29:33.445587
1136 19:29:33.446006 Set Vref, RX VrefLevel [Byte0]: 63
1137 19:29:33.448696 [Byte1]: 63
1138 19:29:33.453025
1139 19:29:33.453442 Set Vref, RX VrefLevel [Byte0]: 64
1140 19:29:33.456306 [Byte1]: 64
1141 19:29:33.460660
1142 19:29:33.461077 Set Vref, RX VrefLevel [Byte0]: 65
1143 19:29:33.463808 [Byte1]: 65
1144 19:29:33.467639
1145 19:29:33.467721 Set Vref, RX VrefLevel [Byte0]: 66
1146 19:29:33.470930 [Byte1]: 66
1147 19:29:33.475121
1148 19:29:33.475203 Set Vref, RX VrefLevel [Byte0]: 67
1149 19:29:33.478416 [Byte1]: 67
1150 19:29:33.483292
1151 19:29:33.483374 Set Vref, RX VrefLevel [Byte0]: 68
1152 19:29:33.486441 [Byte1]: 68
1153 19:29:33.490588
1154 19:29:33.490670 Set Vref, RX VrefLevel [Byte0]: 69
1155 19:29:33.493914 [Byte1]: 69
1156 19:29:33.498041
1157 19:29:33.498127 Set Vref, RX VrefLevel [Byte0]: 70
1158 19:29:33.501678 [Byte1]: 70
1159 19:29:33.505826
1160 19:29:33.505920 Set Vref, RX VrefLevel [Byte0]: 71
1161 19:29:33.509237 [Byte1]: 71
1162 19:29:33.513551
1163 19:29:33.513667 Set Vref, RX VrefLevel [Byte0]: 72
1164 19:29:33.516577 [Byte1]: 72
1165 19:29:33.521294
1166 19:29:33.521387 Set Vref, RX VrefLevel [Byte0]: 73
1167 19:29:33.524417 [Byte1]: 73
1168 19:29:33.528318
1169 19:29:33.528436 Set Vref, RX VrefLevel [Byte0]: 74
1170 19:29:33.531961 [Byte1]: 74
1171 19:29:33.536241
1172 19:29:33.536363 Set Vref, RX VrefLevel [Byte0]: 75
1173 19:29:33.539184 [Byte1]: 75
1174 19:29:33.543728
1175 19:29:33.543879 Set Vref, RX VrefLevel [Byte0]: 76
1176 19:29:33.547546 [Byte1]: 76
1177 19:29:33.551324
1178 19:29:33.551497 Final RX Vref Byte 0 = 58 to rank0
1179 19:29:33.554921 Final RX Vref Byte 1 = 60 to rank0
1180 19:29:33.558130 Final RX Vref Byte 0 = 58 to rank1
1181 19:29:33.561555 Final RX Vref Byte 1 = 60 to rank1==
1182 19:29:33.565114 Dram Type= 6, Freq= 0, CH_0, rank 0
1183 19:29:33.571657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1184 19:29:33.572099 ==
1185 19:29:33.572436 DQS Delay:
1186 19:29:33.572748 DQS0 = 0, DQS1 = 0
1187 19:29:33.574922 DQM Delay:
1188 19:29:33.575354 DQM0 = 92, DQM1 = 86
1189 19:29:33.578355 DQ Delay:
1190 19:29:33.581713 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1191 19:29:33.584986 DQ4 =96, DQ5 =80, DQ6 =100, DQ7 =100
1192 19:29:33.585407 DQ8 =76, DQ9 =76, DQ10 =88, DQ11 =80
1193 19:29:33.591438 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =92
1194 19:29:33.591869
1195 19:29:33.592203
1196 19:29:33.598031 [DQSOSCAuto] RK0, (LSB)MR18= 0x4e44, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
1197 19:29:33.601978 CH0 RK0: MR19=606, MR18=4E44
1198 19:29:33.608622 CH0_RK0: MR19=0x606, MR18=0x4E44, DQSOSC=390, MR23=63, INC=97, DEC=64
1199 19:29:33.609049
1200 19:29:33.611949 ----->DramcWriteLeveling(PI) begin...
1201 19:29:33.612379 ==
1202 19:29:33.615298 Dram Type= 6, Freq= 0, CH_0, rank 1
1203 19:29:33.618505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1204 19:29:33.618973 ==
1205 19:29:33.621592 Write leveling (Byte 0): 33 => 33
1206 19:29:33.624940 Write leveling (Byte 1): 28 => 28
1207 19:29:33.628402 DramcWriteLeveling(PI) end<-----
1208 19:29:33.628840
1209 19:29:33.629201 ==
1210 19:29:33.631144 Dram Type= 6, Freq= 0, CH_0, rank 1
1211 19:29:33.634112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1212 19:29:33.634221 ==
1213 19:29:33.637675 [Gating] SW mode calibration
1214 19:29:33.644636 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1215 19:29:33.651048 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1216 19:29:33.695410 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1217 19:29:33.695532 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1218 19:29:33.695599 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1219 19:29:33.695852 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 19:29:33.696577 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 19:29:33.696845 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 19:29:33.696931 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 19:29:33.697023 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 19:29:33.697127 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 19:29:33.697218 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 19:29:33.704472 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 19:29:33.707892 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 19:29:33.708318 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 19:29:33.711147 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 19:29:33.717782 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 19:29:33.721021 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 19:29:33.724995 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 19:29:33.731251 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 19:29:33.734274 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1235 19:29:33.737322 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 19:29:33.744011 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 19:29:33.747532 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 19:29:33.751440 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 19:29:33.757588 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 19:29:33.761211 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 19:29:33.764597 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 19:29:33.767808 0 9 8 | B1->B0 | 3030 2c2c | 0 0 | (0 0) (1 1)
1243 19:29:33.774324 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1244 19:29:33.778111 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1245 19:29:33.781433 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1246 19:29:33.787508 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1247 19:29:33.791196 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1248 19:29:33.794806 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1249 19:29:33.800970 0 10 4 | B1->B0 | 3333 3434 | 1 0 | (1 1) (0 0)
1250 19:29:33.804772 0 10 8 | B1->B0 | 2e2e 2727 | 0 0 | (0 0) (0 0)
1251 19:29:33.808027 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 19:29:33.814512 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 19:29:33.817782 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 19:29:33.821316 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 19:29:33.824866 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 19:29:33.832229 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 19:29:33.836615 0 11 4 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
1258 19:29:33.840347 0 11 8 | B1->B0 | 3e3e 3939 | 0 0 | (0 0) (0 0)
1259 19:29:33.843495 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1260 19:29:33.846734 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1261 19:29:33.854141 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1262 19:29:33.857587 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1263 19:29:33.860871 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1264 19:29:33.867579 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1265 19:29:33.871072 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 19:29:33.874109 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1267 19:29:33.881587 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 19:29:33.884768 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 19:29:33.887799 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 19:29:33.890936 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 19:29:33.897886 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 19:29:33.901344 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 19:29:33.904350 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 19:29:33.910892 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 19:29:33.914469 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 19:29:33.917422 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 19:29:33.924789 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 19:29:33.927726 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 19:29:33.930960 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 19:29:33.937844 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 19:29:33.941551 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 19:29:33.944449 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1283 19:29:33.951178 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1284 19:29:33.951723 Total UI for P1: 0, mck2ui 16
1285 19:29:33.957637 best dqsien dly found for B0: ( 0, 14, 8)
1286 19:29:33.958074 Total UI for P1: 0, mck2ui 16
1287 19:29:33.961436 best dqsien dly found for B1: ( 0, 14, 8)
1288 19:29:33.968212 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1289 19:29:33.970960 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1290 19:29:33.971389
1291 19:29:33.974636 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1292 19:29:33.977789 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1293 19:29:33.981248 [Gating] SW calibration Done
1294 19:29:33.981807 ==
1295 19:29:33.984411 Dram Type= 6, Freq= 0, CH_0, rank 1
1296 19:29:33.987642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1297 19:29:33.988067 ==
1298 19:29:33.988401 RX Vref Scan: 0
1299 19:29:33.990863
1300 19:29:33.991282 RX Vref 0 -> 0, step: 1
1301 19:29:33.991619
1302 19:29:33.994209 RX Delay -130 -> 252, step: 16
1303 19:29:33.997612 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1304 19:29:34.000855 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1305 19:29:34.007494 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1306 19:29:34.010853 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1307 19:29:34.014426 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1308 19:29:34.018297 iDelay=222, Bit 5, Center 93 (-18 ~ 205) 224
1309 19:29:34.021621 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1310 19:29:34.028307 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1311 19:29:34.031431 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1312 19:29:34.034748 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1313 19:29:34.037454 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1314 19:29:34.041064 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1315 19:29:34.048172 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1316 19:29:34.051191 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1317 19:29:34.054432 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1318 19:29:34.057582 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1319 19:29:34.058063 ==
1320 19:29:34.061088 Dram Type= 6, Freq= 0, CH_0, rank 1
1321 19:29:34.067929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1322 19:29:34.068495 ==
1323 19:29:34.068862 DQS Delay:
1324 19:29:34.071223 DQS0 = 0, DQS1 = 0
1325 19:29:34.071734 DQM Delay:
1326 19:29:34.072136 DQM0 = 94, DQM1 = 85
1327 19:29:34.074641 DQ Delay:
1328 19:29:34.077464 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
1329 19:29:34.080839 DQ4 =93, DQ5 =93, DQ6 =93, DQ7 =101
1330 19:29:34.083953 DQ8 =77, DQ9 =69, DQ10 =85, DQ11 =77
1331 19:29:34.087307 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1332 19:29:34.087731
1333 19:29:34.088063
1334 19:29:34.088376 ==
1335 19:29:34.090973 Dram Type= 6, Freq= 0, CH_0, rank 1
1336 19:29:34.094270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1337 19:29:34.094740 ==
1338 19:29:34.095081
1339 19:29:34.095394
1340 19:29:34.097327 TX Vref Scan disable
1341 19:29:34.097748 == TX Byte 0 ==
1342 19:29:34.104080 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1343 19:29:34.107636 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1344 19:29:34.108063 == TX Byte 1 ==
1345 19:29:34.114273 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1346 19:29:34.117647 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1347 19:29:34.118070 ==
1348 19:29:34.121132 Dram Type= 6, Freq= 0, CH_0, rank 1
1349 19:29:34.124360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1350 19:29:34.124787 ==
1351 19:29:34.139226 TX Vref=22, minBit 9, minWin=27, winSum=446
1352 19:29:34.142749 TX Vref=24, minBit 12, minWin=27, winSum=452
1353 19:29:34.146216 TX Vref=26, minBit 1, minWin=28, winSum=457
1354 19:29:34.149529 TX Vref=28, minBit 7, minWin=28, winSum=461
1355 19:29:34.152863 TX Vref=30, minBit 4, minWin=28, winSum=458
1356 19:29:34.155790 TX Vref=32, minBit 2, minWin=28, winSum=455
1357 19:29:34.162518 [TxChooseVref] Worse bit 7, Min win 28, Win sum 461, Final Vref 28
1358 19:29:34.163069
1359 19:29:34.165676 Final TX Range 1 Vref 28
1360 19:29:34.166140
1361 19:29:34.166557 ==
1362 19:29:34.169071 Dram Type= 6, Freq= 0, CH_0, rank 1
1363 19:29:34.172228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1364 19:29:34.172697 ==
1365 19:29:34.173058
1366 19:29:34.175949
1367 19:29:34.176406 TX Vref Scan disable
1368 19:29:34.179061 == TX Byte 0 ==
1369 19:29:34.182402 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1370 19:29:34.185606 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1371 19:29:34.188742 == TX Byte 1 ==
1372 19:29:34.192104 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1373 19:29:34.195670 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1374 19:29:34.199181
1375 19:29:34.199479 [DATLAT]
1376 19:29:34.199715 Freq=800, CH0 RK1
1377 19:29:34.199936
1378 19:29:34.202083 DATLAT Default: 0xa
1379 19:29:34.202510 0, 0xFFFF, sum = 0
1380 19:29:34.205265 1, 0xFFFF, sum = 0
1381 19:29:34.205565 2, 0xFFFF, sum = 0
1382 19:29:34.209065 3, 0xFFFF, sum = 0
1383 19:29:34.209375 4, 0xFFFF, sum = 0
1384 19:29:34.211902 5, 0xFFFF, sum = 0
1385 19:29:34.215470 6, 0xFFFF, sum = 0
1386 19:29:34.215774 7, 0xFFFF, sum = 0
1387 19:29:34.218749 8, 0xFFFF, sum = 0
1388 19:29:34.219051 9, 0x0, sum = 1
1389 19:29:34.219291 10, 0x0, sum = 2
1390 19:29:34.222513 11, 0x0, sum = 3
1391 19:29:34.223024 12, 0x0, sum = 4
1392 19:29:34.225192 best_step = 10
1393 19:29:34.225576
1394 19:29:34.225909 ==
1395 19:29:34.228955 Dram Type= 6, Freq= 0, CH_0, rank 1
1396 19:29:34.231948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1397 19:29:34.232249 ==
1398 19:29:34.235396 RX Vref Scan: 0
1399 19:29:34.235853
1400 19:29:34.236250 RX Vref 0 -> 0, step: 1
1401 19:29:34.236642
1402 19:29:34.238603 RX Delay -95 -> 252, step: 8
1403 19:29:34.245633 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1404 19:29:34.249336 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1405 19:29:34.252664 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1406 19:29:34.255628 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1407 19:29:34.258852 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1408 19:29:34.266008 iDelay=209, Bit 5, Center 84 (-31 ~ 200) 232
1409 19:29:34.269315 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1410 19:29:34.272456 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1411 19:29:34.275738 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1412 19:29:34.279141 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1413 19:29:34.286122 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1414 19:29:34.289103 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1415 19:29:34.292395 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
1416 19:29:34.295824 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1417 19:29:34.298993 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1418 19:29:34.305332 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1419 19:29:34.305751 ==
1420 19:29:34.309468 Dram Type= 6, Freq= 0, CH_0, rank 1
1421 19:29:34.312768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1422 19:29:34.313337 ==
1423 19:29:34.313739 DQS Delay:
1424 19:29:34.315558 DQS0 = 0, DQS1 = 0
1425 19:29:34.316023 DQM Delay:
1426 19:29:34.319263 DQM0 = 92, DQM1 = 83
1427 19:29:34.319966 DQ Delay:
1428 19:29:34.322891 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1429 19:29:34.325851 DQ4 =92, DQ5 =84, DQ6 =100, DQ7 =100
1430 19:29:34.329403 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1431 19:29:34.332701 DQ12 =92, DQ13 =84, DQ14 =92, DQ15 =92
1432 19:29:34.333316
1433 19:29:34.333689
1434 19:29:34.338889 [DQSOSCAuto] RK1, (LSB)MR18= 0x4010, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
1435 19:29:34.342638 CH0 RK1: MR19=606, MR18=4010
1436 19:29:34.349250 CH0_RK1: MR19=0x606, MR18=0x4010, DQSOSC=393, MR23=63, INC=95, DEC=63
1437 19:29:34.352308 [RxdqsGatingPostProcess] freq 800
1438 19:29:34.359099 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1439 19:29:34.362065 Pre-setting of DQS Precalculation
1440 19:29:34.366098 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1441 19:29:34.366652 ==
1442 19:29:34.369159 Dram Type= 6, Freq= 0, CH_1, rank 0
1443 19:29:34.372648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1444 19:29:34.373072 ==
1445 19:29:34.379008 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1446 19:29:34.385575 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1447 19:29:34.394255 [CA 0] Center 36 (6~67) winsize 62
1448 19:29:34.397518 [CA 1] Center 36 (6~67) winsize 62
1449 19:29:34.400858 [CA 2] Center 35 (5~65) winsize 61
1450 19:29:34.404196 [CA 3] Center 35 (5~65) winsize 61
1451 19:29:34.407461 [CA 4] Center 34 (4~65) winsize 62
1452 19:29:34.410814 [CA 5] Center 34 (4~65) winsize 62
1453 19:29:34.411234
1454 19:29:34.414493 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1455 19:29:34.415004
1456 19:29:34.417780 [CATrainingPosCal] consider 1 rank data
1457 19:29:34.421032 u2DelayCellTimex100 = 270/100 ps
1458 19:29:34.423857 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1459 19:29:34.427612 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1460 19:29:34.434447 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1461 19:29:34.437579 CA3 delay=35 (5~65),Diff = 1 PI (7 cell)
1462 19:29:34.441189 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1463 19:29:34.444599 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1464 19:29:34.445122
1465 19:29:34.447948 CA PerBit enable=1, Macro0, CA PI delay=34
1466 19:29:34.448512
1467 19:29:34.451312 [CBTSetCACLKResult] CA Dly = 34
1468 19:29:34.451873 CS Dly: 5 (0~36)
1469 19:29:34.452245 ==
1470 19:29:34.454354 Dram Type= 6, Freq= 0, CH_1, rank 1
1471 19:29:34.460811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1472 19:29:34.461360 ==
1473 19:29:34.464545 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1474 19:29:34.470838 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1475 19:29:34.480534 [CA 0] Center 36 (6~67) winsize 62
1476 19:29:34.483515 [CA 1] Center 37 (6~68) winsize 63
1477 19:29:34.486685 [CA 2] Center 35 (5~66) winsize 62
1478 19:29:34.491357 [CA 3] Center 35 (5~65) winsize 61
1479 19:29:34.494540 [CA 4] Center 35 (5~66) winsize 62
1480 19:29:34.498112 [CA 5] Center 34 (4~65) winsize 62
1481 19:29:34.498626
1482 19:29:34.502043 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1483 19:29:34.502628
1484 19:29:34.505556 [CATrainingPosCal] consider 2 rank data
1485 19:29:34.509157 u2DelayCellTimex100 = 270/100 ps
1486 19:29:34.513210 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1487 19:29:34.516362 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1488 19:29:34.520362 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1489 19:29:34.524426 CA3 delay=35 (5~65),Diff = 1 PI (7 cell)
1490 19:29:34.527701 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1491 19:29:34.530877 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1492 19:29:34.531438
1493 19:29:34.533951 CA PerBit enable=1, Macro0, CA PI delay=34
1494 19:29:34.534404
1495 19:29:34.537289 [CBTSetCACLKResult] CA Dly = 34
1496 19:29:34.537710 CS Dly: 6 (0~38)
1497 19:29:34.538043
1498 19:29:34.540749 ----->DramcWriteLeveling(PI) begin...
1499 19:29:34.541274 ==
1500 19:29:34.544206 Dram Type= 6, Freq= 0, CH_1, rank 0
1501 19:29:34.550856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1502 19:29:34.551287 ==
1503 19:29:34.554275 Write leveling (Byte 0): 29 => 29
1504 19:29:34.554831 Write leveling (Byte 1): 28 => 28
1505 19:29:34.557666 DramcWriteLeveling(PI) end<-----
1506 19:29:34.558179
1507 19:29:34.558570 ==
1508 19:29:34.560955 Dram Type= 6, Freq= 0, CH_1, rank 0
1509 19:29:34.567519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1510 19:29:34.568042 ==
1511 19:29:34.570995 [Gating] SW mode calibration
1512 19:29:34.577316 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1513 19:29:34.580664 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1514 19:29:34.587636 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1515 19:29:34.590824 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1516 19:29:34.594185 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 19:29:34.597838 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 19:29:34.604453 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 19:29:34.607419 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 19:29:34.611119 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 19:29:34.617896 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 19:29:34.621150 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 19:29:34.624113 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 19:29:34.631070 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 19:29:34.633985 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 19:29:34.637686 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 19:29:34.644641 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 19:29:34.647862 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 19:29:34.651814 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 19:29:34.658396 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1531 19:29:34.661261 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 1)
1532 19:29:34.665028 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 19:29:34.671417 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 19:29:34.674716 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 19:29:34.678690 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 19:29:34.681536 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 19:29:34.688249 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 19:29:34.691047 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 19:29:34.694389 0 9 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1540 19:29:34.701528 0 9 8 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
1541 19:29:34.705019 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1542 19:29:34.707809 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1543 19:29:34.714447 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1544 19:29:34.718162 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1545 19:29:34.721387 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1546 19:29:34.727839 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
1547 19:29:34.731386 0 10 4 | B1->B0 | 3434 2d2d | 1 0 | (1 0) (0 0)
1548 19:29:34.734746 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1549 19:29:34.740907 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 19:29:34.744207 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 19:29:34.747994 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 19:29:34.754195 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 19:29:34.757793 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 19:29:34.761113 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 19:29:34.764719 0 11 4 | B1->B0 | 2727 3434 | 0 1 | (0 0) (0 0)
1556 19:29:34.770894 0 11 8 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
1557 19:29:34.774243 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1558 19:29:34.777597 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1559 19:29:34.784449 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1560 19:29:34.788119 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1561 19:29:34.791737 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1562 19:29:34.798025 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1563 19:29:34.801709 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1564 19:29:34.804956 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 19:29:34.811665 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 19:29:34.814994 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 19:29:34.818435 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 19:29:34.824845 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 19:29:34.828895 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 19:29:34.831908 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 19:29:34.834701 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 19:29:34.841761 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 19:29:34.844943 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 19:29:34.848348 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 19:29:34.854818 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 19:29:34.858956 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 19:29:34.861827 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 19:29:34.868444 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1579 19:29:34.871554 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1580 19:29:34.874765 Total UI for P1: 0, mck2ui 16
1581 19:29:34.878092 best dqsien dly found for B1: ( 0, 14, 0)
1582 19:29:34.881583 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1583 19:29:34.884964 Total UI for P1: 0, mck2ui 16
1584 19:29:34.888781 best dqsien dly found for B0: ( 0, 14, 4)
1585 19:29:34.891447 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1586 19:29:34.895275 best DQS1 dly(MCK, UI, PI) = (0, 14, 0)
1587 19:29:34.895739
1588 19:29:34.898713 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1589 19:29:34.905343 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 0)
1590 19:29:34.905811 [Gating] SW calibration Done
1591 19:29:34.906177 ==
1592 19:29:34.908536 Dram Type= 6, Freq= 0, CH_1, rank 0
1593 19:29:34.915310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1594 19:29:34.915875 ==
1595 19:29:34.916251 RX Vref Scan: 0
1596 19:29:34.916595
1597 19:29:34.918504 RX Vref 0 -> 0, step: 1
1598 19:29:34.918970
1599 19:29:34.921797 RX Delay -130 -> 252, step: 16
1600 19:29:34.925043 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1601 19:29:34.928891 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1602 19:29:34.931563 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1603 19:29:34.942351 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1604 19:29:34.942924 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1605 19:29:34.945437 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1606 19:29:34.948839 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
1607 19:29:34.951867 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1608 19:29:34.955227 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1609 19:29:34.961687 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1610 19:29:34.965607 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1611 19:29:34.968896 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1612 19:29:34.972029 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1613 19:29:34.978427 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1614 19:29:34.981635 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1615 19:29:34.984965 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1616 19:29:34.985434 ==
1617 19:29:34.989059 Dram Type= 6, Freq= 0, CH_1, rank 0
1618 19:29:34.992034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1619 19:29:34.992600 ==
1620 19:29:34.995232 DQS Delay:
1621 19:29:34.995694 DQS0 = 0, DQS1 = 0
1622 19:29:34.996061 DQM Delay:
1623 19:29:34.998550 DQM0 = 94, DQM1 = 88
1624 19:29:34.999014 DQ Delay:
1625 19:29:35.002493 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1626 19:29:35.005474 DQ4 =93, DQ5 =109, DQ6 =109, DQ7 =93
1627 19:29:35.008765 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
1628 19:29:35.012176 DQ12 =93, DQ13 =101, DQ14 =93, DQ15 =101
1629 19:29:35.012740
1630 19:29:35.013180
1631 19:29:35.013702 ==
1632 19:29:35.015441 Dram Type= 6, Freq= 0, CH_1, rank 0
1633 19:29:35.022079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1634 19:29:35.022550 ==
1635 19:29:35.022891
1636 19:29:35.023203
1637 19:29:35.023499 TX Vref Scan disable
1638 19:29:35.025687 == TX Byte 0 ==
1639 19:29:35.029007 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1640 19:29:35.032707 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1641 19:29:35.035905 == TX Byte 1 ==
1642 19:29:35.039043 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1643 19:29:35.042765 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1644 19:29:35.045519 ==
1645 19:29:35.048806 Dram Type= 6, Freq= 0, CH_1, rank 0
1646 19:29:35.052468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1647 19:29:35.052895 ==
1648 19:29:35.064891 TX Vref=22, minBit 0, minWin=26, winSum=439
1649 19:29:35.068104 TX Vref=24, minBit 1, minWin=27, winSum=446
1650 19:29:35.071316 TX Vref=26, minBit 2, minWin=27, winSum=447
1651 19:29:35.074701 TX Vref=28, minBit 1, minWin=27, winSum=450
1652 19:29:35.077991 TX Vref=30, minBit 1, minWin=27, winSum=454
1653 19:29:35.081013 TX Vref=32, minBit 1, minWin=27, winSum=449
1654 19:29:35.088202 [TxChooseVref] Worse bit 1, Min win 27, Win sum 454, Final Vref 30
1655 19:29:35.088337
1656 19:29:35.091804 Final TX Range 1 Vref 30
1657 19:29:35.091901
1658 19:29:35.091968 ==
1659 19:29:35.094889 Dram Type= 6, Freq= 0, CH_1, rank 0
1660 19:29:35.098151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1661 19:29:35.098285 ==
1662 19:29:35.098401
1663 19:29:35.101265
1664 19:29:35.101348 TX Vref Scan disable
1665 19:29:35.104626 == TX Byte 0 ==
1666 19:29:35.107885 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1667 19:29:35.111124 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1668 19:29:35.114771 == TX Byte 1 ==
1669 19:29:35.117817 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1670 19:29:35.120999 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1671 19:29:35.121083
1672 19:29:35.124688 [DATLAT]
1673 19:29:35.124772 Freq=800, CH1 RK0
1674 19:29:35.124837
1675 19:29:35.127866 DATLAT Default: 0xa
1676 19:29:35.127948 0, 0xFFFF, sum = 0
1677 19:29:35.131273 1, 0xFFFF, sum = 0
1678 19:29:35.131358 2, 0xFFFF, sum = 0
1679 19:29:35.134562 3, 0xFFFF, sum = 0
1680 19:29:35.134646 4, 0xFFFF, sum = 0
1681 19:29:35.138052 5, 0xFFFF, sum = 0
1682 19:29:35.138138 6, 0xFFFF, sum = 0
1683 19:29:35.141324 7, 0xFFFF, sum = 0
1684 19:29:35.141409 8, 0xFFFF, sum = 0
1685 19:29:35.144677 9, 0x0, sum = 1
1686 19:29:35.144763 10, 0x0, sum = 2
1687 19:29:35.147869 11, 0x0, sum = 3
1688 19:29:35.147953 12, 0x0, sum = 4
1689 19:29:35.151109 best_step = 10
1690 19:29:35.151193
1691 19:29:35.151300 ==
1692 19:29:35.154836 Dram Type= 6, Freq= 0, CH_1, rank 0
1693 19:29:35.157784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1694 19:29:35.157876 ==
1695 19:29:35.161348 RX Vref Scan: 1
1696 19:29:35.161491
1697 19:29:35.161584 Set Vref Range= 32 -> 127
1698 19:29:35.161674
1699 19:29:35.164576 RX Vref 32 -> 127, step: 1
1700 19:29:35.164660
1701 19:29:35.168021 RX Delay -79 -> 252, step: 8
1702 19:29:35.168108
1703 19:29:35.171286 Set Vref, RX VrefLevel [Byte0]: 32
1704 19:29:35.174661 [Byte1]: 32
1705 19:29:35.174749
1706 19:29:35.177945 Set Vref, RX VrefLevel [Byte0]: 33
1707 19:29:35.181123 [Byte1]: 33
1708 19:29:35.184363
1709 19:29:35.184475 Set Vref, RX VrefLevel [Byte0]: 34
1710 19:29:35.188245 [Byte1]: 34
1711 19:29:35.192246
1712 19:29:35.192331 Set Vref, RX VrefLevel [Byte0]: 35
1713 19:29:35.195695 [Byte1]: 35
1714 19:29:35.199636
1715 19:29:35.199730 Set Vref, RX VrefLevel [Byte0]: 36
1716 19:29:35.202785 [Byte1]: 36
1717 19:29:35.207326
1718 19:29:35.207413 Set Vref, RX VrefLevel [Byte0]: 37
1719 19:29:35.210703 [Byte1]: 37
1720 19:29:35.214611
1721 19:29:35.214693 Set Vref, RX VrefLevel [Byte0]: 38
1722 19:29:35.218271 [Byte1]: 38
1723 19:29:35.222561
1724 19:29:35.222644 Set Vref, RX VrefLevel [Byte0]: 39
1725 19:29:35.225477 [Byte1]: 39
1726 19:29:35.229809
1727 19:29:35.229893 Set Vref, RX VrefLevel [Byte0]: 40
1728 19:29:35.233075 [Byte1]: 40
1729 19:29:35.237445
1730 19:29:35.237529 Set Vref, RX VrefLevel [Byte0]: 41
1731 19:29:35.240691 [Byte1]: 41
1732 19:29:35.245120
1733 19:29:35.245203 Set Vref, RX VrefLevel [Byte0]: 42
1734 19:29:35.248062 [Byte1]: 42
1735 19:29:35.252359
1736 19:29:35.252442 Set Vref, RX VrefLevel [Byte0]: 43
1737 19:29:35.256070 [Byte1]: 43
1738 19:29:35.260264
1739 19:29:35.260348 Set Vref, RX VrefLevel [Byte0]: 44
1740 19:29:35.263648 [Byte1]: 44
1741 19:29:35.267364
1742 19:29:35.267447 Set Vref, RX VrefLevel [Byte0]: 45
1743 19:29:35.270886 [Byte1]: 45
1744 19:29:35.275074
1745 19:29:35.275158 Set Vref, RX VrefLevel [Byte0]: 46
1746 19:29:35.278294 [Byte1]: 46
1747 19:29:35.282599
1748 19:29:35.282683 Set Vref, RX VrefLevel [Byte0]: 47
1749 19:29:35.285933 [Byte1]: 47
1750 19:29:35.290099
1751 19:29:35.290181 Set Vref, RX VrefLevel [Byte0]: 48
1752 19:29:35.293614 [Byte1]: 48
1753 19:29:35.298198
1754 19:29:35.298338 Set Vref, RX VrefLevel [Byte0]: 49
1755 19:29:35.300892 [Byte1]: 49
1756 19:29:35.305354
1757 19:29:35.305436 Set Vref, RX VrefLevel [Byte0]: 50
1758 19:29:35.308684 [Byte1]: 50
1759 19:29:35.313174
1760 19:29:35.313256 Set Vref, RX VrefLevel [Byte0]: 51
1761 19:29:35.316476 [Byte1]: 51
1762 19:29:35.320518
1763 19:29:35.320600 Set Vref, RX VrefLevel [Byte0]: 52
1764 19:29:35.323712 [Byte1]: 52
1765 19:29:35.327647
1766 19:29:35.327729 Set Vref, RX VrefLevel [Byte0]: 53
1767 19:29:35.331519 [Byte1]: 53
1768 19:29:35.335607
1769 19:29:35.335689 Set Vref, RX VrefLevel [Byte0]: 54
1770 19:29:35.338611 [Byte1]: 54
1771 19:29:35.342826
1772 19:29:35.342908 Set Vref, RX VrefLevel [Byte0]: 55
1773 19:29:35.346173 [Byte1]: 55
1774 19:29:35.350678
1775 19:29:35.353844 Set Vref, RX VrefLevel [Byte0]: 56
1776 19:29:35.357100 [Byte1]: 56
1777 19:29:35.357183
1778 19:29:35.360389 Set Vref, RX VrefLevel [Byte0]: 57
1779 19:29:35.364128 [Byte1]: 57
1780 19:29:35.364210
1781 19:29:35.367106 Set Vref, RX VrefLevel [Byte0]: 58
1782 19:29:35.370435 [Byte1]: 58
1783 19:29:35.370517
1784 19:29:35.373654 Set Vref, RX VrefLevel [Byte0]: 59
1785 19:29:35.376937 [Byte1]: 59
1786 19:29:35.380882
1787 19:29:35.380963 Set Vref, RX VrefLevel [Byte0]: 60
1788 19:29:35.383797 [Byte1]: 60
1789 19:29:35.388335
1790 19:29:35.388417 Set Vref, RX VrefLevel [Byte0]: 61
1791 19:29:35.391742 [Byte1]: 61
1792 19:29:35.395775
1793 19:29:35.395857 Set Vref, RX VrefLevel [Byte0]: 62
1794 19:29:35.399227 [Byte1]: 62
1795 19:29:35.403204
1796 19:29:35.403286 Set Vref, RX VrefLevel [Byte0]: 63
1797 19:29:35.406469 [Byte1]: 63
1798 19:29:35.410956
1799 19:29:35.411038 Set Vref, RX VrefLevel [Byte0]: 64
1800 19:29:35.414256 [Byte1]: 64
1801 19:29:35.418685
1802 19:29:35.418767 Set Vref, RX VrefLevel [Byte0]: 65
1803 19:29:35.421986 [Byte1]: 65
1804 19:29:35.425835
1805 19:29:35.425917 Set Vref, RX VrefLevel [Byte0]: 66
1806 19:29:35.429202 [Byte1]: 66
1807 19:29:35.433779
1808 19:29:35.433860 Set Vref, RX VrefLevel [Byte0]: 67
1809 19:29:35.436915 [Byte1]: 67
1810 19:29:35.441163
1811 19:29:35.441245 Set Vref, RX VrefLevel [Byte0]: 68
1812 19:29:35.444368 [Byte1]: 68
1813 19:29:35.449123
1814 19:29:35.449206 Set Vref, RX VrefLevel [Byte0]: 69
1815 19:29:35.452333 [Byte1]: 69
1816 19:29:35.456105
1817 19:29:35.456201 Set Vref, RX VrefLevel [Byte0]: 70
1818 19:29:35.459820 [Byte1]: 70
1819 19:29:35.464156
1820 19:29:35.464238 Set Vref, RX VrefLevel [Byte0]: 71
1821 19:29:35.467399 [Byte1]: 71
1822 19:29:35.471251
1823 19:29:35.471332 Set Vref, RX VrefLevel [Byte0]: 72
1824 19:29:35.475056 [Byte1]: 72
1825 19:29:35.478772
1826 19:29:35.478876 Set Vref, RX VrefLevel [Byte0]: 73
1827 19:29:35.485628 [Byte1]: 73
1828 19:29:35.485787
1829 19:29:35.488773 Final RX Vref Byte 0 = 61 to rank0
1830 19:29:35.492671 Final RX Vref Byte 1 = 55 to rank0
1831 19:29:35.495525 Final RX Vref Byte 0 = 61 to rank1
1832 19:29:35.499144 Final RX Vref Byte 1 = 55 to rank1==
1833 19:29:35.502708 Dram Type= 6, Freq= 0, CH_1, rank 0
1834 19:29:35.505896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1835 19:29:35.506476 ==
1836 19:29:35.506825 DQS Delay:
1837 19:29:35.509175 DQS0 = 0, DQS1 = 0
1838 19:29:35.509750 DQM Delay:
1839 19:29:35.512150 DQM0 = 95, DQM1 = 90
1840 19:29:35.512570 DQ Delay:
1841 19:29:35.515984 DQ0 =100, DQ1 =88, DQ2 =84, DQ3 =88
1842 19:29:35.519160 DQ4 =92, DQ5 =108, DQ6 =108, DQ7 =92
1843 19:29:35.522390 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1844 19:29:35.525982 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =100
1845 19:29:35.526632
1846 19:29:35.526983
1847 19:29:35.532228 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e4a, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1848 19:29:35.537148 CH1 RK0: MR19=606, MR18=2E4A
1849 19:29:35.542235 CH1_RK0: MR19=0x606, MR18=0x2E4A, DQSOSC=391, MR23=63, INC=96, DEC=64
1850 19:29:35.542332
1851 19:29:35.545541 ----->DramcWriteLeveling(PI) begin...
1852 19:29:35.545631 ==
1853 19:29:35.548845 Dram Type= 6, Freq= 0, CH_1, rank 1
1854 19:29:35.551983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1855 19:29:35.555149 ==
1856 19:29:35.555254 Write leveling (Byte 0): 26 => 26
1857 19:29:35.558735 Write leveling (Byte 1): 30 => 30
1858 19:29:35.562397 DramcWriteLeveling(PI) end<-----
1859 19:29:35.562562
1860 19:29:35.562656 ==
1861 19:29:35.565441 Dram Type= 6, Freq= 0, CH_1, rank 1
1862 19:29:35.571852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1863 19:29:35.572018 ==
1864 19:29:35.572112 [Gating] SW mode calibration
1865 19:29:35.581865 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1866 19:29:35.585551 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1867 19:29:35.588896 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1868 19:29:35.595676 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1869 19:29:35.598734 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 19:29:35.602642 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 19:29:35.609400 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 19:29:35.612429 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 19:29:35.615489 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 19:29:35.622069 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 19:29:35.626003 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 19:29:35.629205 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 19:29:35.635806 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 19:29:35.638992 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 19:29:35.642180 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 19:29:35.649195 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 19:29:35.652188 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 19:29:35.655901 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1883 19:29:35.662289 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1884 19:29:35.665639 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1885 19:29:35.669164 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 19:29:35.673100 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 19:29:35.679227 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 19:29:35.682456 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 19:29:35.685502 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 19:29:35.692649 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 19:29:35.696317 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 19:29:35.699306 0 9 4 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
1893 19:29:35.705964 0 9 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
1894 19:29:35.709270 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1895 19:29:35.712665 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1896 19:29:35.719403 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1897 19:29:35.722626 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1898 19:29:35.726526 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1899 19:29:35.732600 0 10 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
1900 19:29:35.735830 0 10 4 | B1->B0 | 2727 2f2f | 0 0 | (0 0) (1 1)
1901 19:29:35.739083 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 19:29:35.745704 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 19:29:35.749207 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 19:29:35.752624 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 19:29:35.759091 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 19:29:35.762929 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 19:29:35.766049 0 11 0 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1908 19:29:35.769495 0 11 4 | B1->B0 | 3636 3131 | 0 0 | (0 0) (0 0)
1909 19:29:35.775901 0 11 8 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
1910 19:29:35.779557 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1911 19:29:35.782695 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1912 19:29:35.789485 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1913 19:29:35.792783 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1914 19:29:35.796276 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1915 19:29:35.802507 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1916 19:29:35.805775 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1917 19:29:35.809031 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 19:29:35.816281 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 19:29:35.819469 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 19:29:35.822382 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 19:29:35.829428 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 19:29:35.832787 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 19:29:35.835621 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 19:29:35.842784 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 19:29:35.846145 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 19:29:35.849370 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 19:29:35.852740 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 19:29:35.859160 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 19:29:35.862689 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 19:29:35.865573 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 19:29:35.873199 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1932 19:29:35.876106 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1933 19:29:35.879551 Total UI for P1: 0, mck2ui 16
1934 19:29:35.882922 best dqsien dly found for B0: ( 0, 14, 0)
1935 19:29:35.885855 Total UI for P1: 0, mck2ui 16
1936 19:29:35.889643 best dqsien dly found for B1: ( 0, 14, 2)
1937 19:29:35.892400 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1938 19:29:35.895900 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1939 19:29:35.896366
1940 19:29:35.899543 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1941 19:29:35.902858 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1942 19:29:35.906106 [Gating] SW calibration Done
1943 19:29:35.906688 ==
1944 19:29:35.909269 Dram Type= 6, Freq= 0, CH_1, rank 1
1945 19:29:35.912613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1946 19:29:35.913146 ==
1947 19:29:35.915909 RX Vref Scan: 0
1948 19:29:35.916336
1949 19:29:35.919034 RX Vref 0 -> 0, step: 1
1950 19:29:35.919454
1951 19:29:35.922479 RX Delay -130 -> 252, step: 16
1952 19:29:35.926388 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1953 19:29:35.929229 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1954 19:29:35.933051 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1955 19:29:35.935937 iDelay=222, Bit 3, Center 93 (-2 ~ 189) 192
1956 19:29:35.939570 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1957 19:29:35.945906 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1958 19:29:35.949294 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1959 19:29:35.952646 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1960 19:29:35.955710 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1961 19:29:35.959204 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1962 19:29:35.965739 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1963 19:29:35.969554 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1964 19:29:35.972589 iDelay=222, Bit 12, Center 101 (-2 ~ 205) 208
1965 19:29:35.975857 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1966 19:29:35.979669 iDelay=222, Bit 14, Center 101 (-2 ~ 205) 208
1967 19:29:35.985633 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1968 19:29:35.986105 ==
1969 19:29:35.989740 Dram Type= 6, Freq= 0, CH_1, rank 1
1970 19:29:35.992540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1971 19:29:35.992965 ==
1972 19:29:35.993301 DQS Delay:
1973 19:29:35.995856 DQS0 = 0, DQS1 = 0
1974 19:29:35.996275 DQM Delay:
1975 19:29:35.998954 DQM0 = 93, DQM1 = 91
1976 19:29:35.999376 DQ Delay:
1977 19:29:36.002591 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =93
1978 19:29:36.006022 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1979 19:29:36.009320 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =77
1980 19:29:36.012924 DQ12 =101, DQ13 =101, DQ14 =101, DQ15 =101
1981 19:29:36.013444
1982 19:29:36.013780
1983 19:29:36.014089 ==
1984 19:29:36.015931 Dram Type= 6, Freq= 0, CH_1, rank 1
1985 19:29:36.022608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1986 19:29:36.023038 ==
1987 19:29:36.023369
1988 19:29:36.023676
1989 19:29:36.023973 TX Vref Scan disable
1990 19:29:36.026046 == TX Byte 0 ==
1991 19:29:36.029389 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1992 19:29:36.033017 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1993 19:29:36.036524 == TX Byte 1 ==
1994 19:29:36.039634 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1995 19:29:36.042599 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1996 19:29:36.045852 ==
1997 19:29:36.049478 Dram Type= 6, Freq= 0, CH_1, rank 1
1998 19:29:36.053007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1999 19:29:36.053529 ==
2000 19:29:36.065715 TX Vref=22, minBit 1, minWin=26, winSum=440
2001 19:29:36.069039 TX Vref=24, minBit 0, minWin=27, winSum=445
2002 19:29:36.072107 TX Vref=26, minBit 3, minWin=27, winSum=451
2003 19:29:36.075447 TX Vref=28, minBit 2, minWin=27, winSum=450
2004 19:29:36.079142 TX Vref=30, minBit 2, minWin=27, winSum=450
2005 19:29:36.082044 TX Vref=32, minBit 0, minWin=27, winSum=449
2006 19:29:36.089012 [TxChooseVref] Worse bit 3, Min win 27, Win sum 451, Final Vref 26
2007 19:29:36.089564
2008 19:29:36.092133 Final TX Range 1 Vref 26
2009 19:29:36.092598
2010 19:29:36.092959 ==
2011 19:29:36.095147 Dram Type= 6, Freq= 0, CH_1, rank 1
2012 19:29:36.099118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2013 19:29:36.099642 ==
2014 19:29:36.099980
2015 19:29:36.102075
2016 19:29:36.102596 TX Vref Scan disable
2017 19:29:36.105313 == TX Byte 0 ==
2018 19:29:36.108629 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2019 19:29:36.112643 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2020 19:29:36.115428 == TX Byte 1 ==
2021 19:29:36.118989 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2022 19:29:36.122231 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2023 19:29:36.125481
2024 19:29:36.125991 [DATLAT]
2025 19:29:36.126362 Freq=800, CH1 RK1
2026 19:29:36.126687
2027 19:29:36.128925 DATLAT Default: 0xa
2028 19:29:36.129435 0, 0xFFFF, sum = 0
2029 19:29:36.132105 1, 0xFFFF, sum = 0
2030 19:29:36.132530 2, 0xFFFF, sum = 0
2031 19:29:36.135627 3, 0xFFFF, sum = 0
2032 19:29:36.136055 4, 0xFFFF, sum = 0
2033 19:29:36.138858 5, 0xFFFF, sum = 0
2034 19:29:36.139284 6, 0xFFFF, sum = 0
2035 19:29:36.142378 7, 0xFFFF, sum = 0
2036 19:29:36.145650 8, 0xFFFF, sum = 0
2037 19:29:36.146195 9, 0x0, sum = 1
2038 19:29:36.146583 10, 0x0, sum = 2
2039 19:29:36.148694 11, 0x0, sum = 3
2040 19:29:36.149121 12, 0x0, sum = 4
2041 19:29:36.152226 best_step = 10
2042 19:29:36.152744
2043 19:29:36.153082 ==
2044 19:29:36.155095 Dram Type= 6, Freq= 0, CH_1, rank 1
2045 19:29:36.159030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2046 19:29:36.159557 ==
2047 19:29:36.162345 RX Vref Scan: 0
2048 19:29:36.162875
2049 19:29:36.163351 RX Vref 0 -> 0, step: 1
2050 19:29:36.163695
2051 19:29:36.165619 RX Delay -79 -> 252, step: 8
2052 19:29:36.172099 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
2053 19:29:36.175509 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2054 19:29:36.179205 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2055 19:29:36.182365 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2056 19:29:36.185377 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2057 19:29:36.188934 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
2058 19:29:36.195454 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2059 19:29:36.199026 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2060 19:29:36.202441 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2061 19:29:36.205699 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2062 19:29:36.208708 iDelay=209, Bit 10, Center 92 (-15 ~ 200) 216
2063 19:29:36.215502 iDelay=209, Bit 11, Center 84 (-15 ~ 184) 200
2064 19:29:36.218614 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2065 19:29:36.222800 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2066 19:29:36.225639 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2067 19:29:36.228944 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2068 19:29:36.229515 ==
2069 19:29:36.232139 Dram Type= 6, Freq= 0, CH_1, rank 1
2070 19:29:36.238840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2071 19:29:36.239303 ==
2072 19:29:36.239671 DQS Delay:
2073 19:29:36.242635 DQS0 = 0, DQS1 = 0
2074 19:29:36.243307 DQM Delay:
2075 19:29:36.243686 DQM0 = 97, DQM1 = 90
2076 19:29:36.245436 DQ Delay:
2077 19:29:36.249206 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2078 19:29:36.252729 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2079 19:29:36.255336 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
2080 19:29:36.258782 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2081 19:29:36.259249
2082 19:29:36.259615
2083 19:29:36.265694 [DQSOSCAuto] RK1, (LSB)MR18= 0x4510, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 392 ps
2084 19:29:36.269149 CH1 RK1: MR19=606, MR18=4510
2085 19:29:36.275783 CH1_RK1: MR19=0x606, MR18=0x4510, DQSOSC=392, MR23=63, INC=96, DEC=64
2086 19:29:36.279234 [RxdqsGatingPostProcess] freq 800
2087 19:29:36.282730 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2088 19:29:36.285959 Pre-setting of DQS Precalculation
2089 19:29:36.292378 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2090 19:29:36.299282 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2091 19:29:36.305761 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2092 19:29:36.306377
2093 19:29:36.306762
2094 19:29:36.309065 [Calibration Summary] 1600 Mbps
2095 19:29:36.309631 CH 0, Rank 0
2096 19:29:36.312671 SW Impedance : PASS
2097 19:29:36.315896 DUTY Scan : NO K
2098 19:29:36.316364 ZQ Calibration : PASS
2099 19:29:36.318998 Jitter Meter : NO K
2100 19:29:36.322874 CBT Training : PASS
2101 19:29:36.323452 Write leveling : PASS
2102 19:29:36.325609 RX DQS gating : PASS
2103 19:29:36.329248 RX DQ/DQS(RDDQC) : PASS
2104 19:29:36.329815 TX DQ/DQS : PASS
2105 19:29:36.332392 RX DATLAT : PASS
2106 19:29:36.335874 RX DQ/DQS(Engine): PASS
2107 19:29:36.336338 TX OE : NO K
2108 19:29:36.336725 All Pass.
2109 19:29:36.339037
2110 19:29:36.339499 CH 0, Rank 1
2111 19:29:36.342371 SW Impedance : PASS
2112 19:29:36.342840 DUTY Scan : NO K
2113 19:29:36.345444 ZQ Calibration : PASS
2114 19:29:36.345888 Jitter Meter : NO K
2115 19:29:36.349310 CBT Training : PASS
2116 19:29:36.352462 Write leveling : PASS
2117 19:29:36.352991 RX DQS gating : PASS
2118 19:29:36.355767 RX DQ/DQS(RDDQC) : PASS
2119 19:29:36.359129 TX DQ/DQS : PASS
2120 19:29:36.359637 RX DATLAT : PASS
2121 19:29:36.362033 RX DQ/DQS(Engine): PASS
2122 19:29:36.365838 TX OE : NO K
2123 19:29:36.366258 All Pass.
2124 19:29:36.366673
2125 19:29:36.366992 CH 1, Rank 0
2126 19:29:36.368865 SW Impedance : PASS
2127 19:29:36.372273 DUTY Scan : NO K
2128 19:29:36.372693 ZQ Calibration : PASS
2129 19:29:36.375235 Jitter Meter : NO K
2130 19:29:36.378762 CBT Training : PASS
2131 19:29:36.379058 Write leveling : PASS
2132 19:29:36.381913 RX DQS gating : PASS
2133 19:29:36.385675 RX DQ/DQS(RDDQC) : PASS
2134 19:29:36.385897 TX DQ/DQS : PASS
2135 19:29:36.388732 RX DATLAT : PASS
2136 19:29:36.388913 RX DQ/DQS(Engine): PASS
2137 19:29:36.391867 TX OE : NO K
2138 19:29:36.392018 All Pass.
2139 19:29:36.392137
2140 19:29:36.395580 CH 1, Rank 1
2141 19:29:36.395731 SW Impedance : PASS
2142 19:29:36.398833 DUTY Scan : NO K
2143 19:29:36.401977 ZQ Calibration : PASS
2144 19:29:36.402091 Jitter Meter : NO K
2145 19:29:36.405122 CBT Training : PASS
2146 19:29:36.408987 Write leveling : PASS
2147 19:29:36.409088 RX DQS gating : PASS
2148 19:29:36.412084 RX DQ/DQS(RDDQC) : PASS
2149 19:29:36.415744 TX DQ/DQS : PASS
2150 19:29:36.415837 RX DATLAT : PASS
2151 19:29:36.418997 RX DQ/DQS(Engine): PASS
2152 19:29:36.419081 TX OE : NO K
2153 19:29:36.422289 All Pass.
2154 19:29:36.422376
2155 19:29:36.422441 DramC Write-DBI off
2156 19:29:36.425309 PER_BANK_REFRESH: Hybrid Mode
2157 19:29:36.429150 TX_TRACKING: ON
2158 19:29:36.432308 [GetDramInforAfterCalByMRR] Vendor 6.
2159 19:29:36.435578 [GetDramInforAfterCalByMRR] Revision 606.
2160 19:29:36.438624 [GetDramInforAfterCalByMRR] Revision 2 0.
2161 19:29:36.438707 MR0 0x3b3b
2162 19:29:36.438772 MR8 0x5151
2163 19:29:36.445550 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2164 19:29:36.445632
2165 19:29:36.445697 MR0 0x3b3b
2166 19:29:36.445757 MR8 0x5151
2167 19:29:36.448990 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2168 19:29:36.449072
2169 19:29:36.458528 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2170 19:29:36.461896 [FAST_K] Save calibration result to emmc
2171 19:29:36.465371 [FAST_K] Save calibration result to emmc
2172 19:29:36.468600 dram_init: config_dvfs: 1
2173 19:29:36.471923 dramc_set_vcore_voltage set vcore to 662500
2174 19:29:36.475300 Read voltage for 1200, 2
2175 19:29:36.475391 Vio18 = 0
2176 19:29:36.475464 Vcore = 662500
2177 19:29:36.478802 Vdram = 0
2178 19:29:36.478883 Vddq = 0
2179 19:29:36.478947 Vmddr = 0
2180 19:29:36.485372 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2181 19:29:36.488654 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2182 19:29:36.492070 MEM_TYPE=3, freq_sel=15
2183 19:29:36.495356 sv_algorithm_assistance_LP4_1600
2184 19:29:36.498328 ============ PULL DRAM RESETB DOWN ============
2185 19:29:36.505389 ========== PULL DRAM RESETB DOWN end =========
2186 19:29:36.508642 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2187 19:29:36.512323 ===================================
2188 19:29:36.515426 LPDDR4 DRAM CONFIGURATION
2189 19:29:36.518868 ===================================
2190 19:29:36.518951 EX_ROW_EN[0] = 0x0
2191 19:29:36.521971 EX_ROW_EN[1] = 0x0
2192 19:29:36.522053 LP4Y_EN = 0x0
2193 19:29:36.525318 WORK_FSP = 0x0
2194 19:29:36.525400 WL = 0x4
2195 19:29:36.528360 RL = 0x4
2196 19:29:36.528442 BL = 0x2
2197 19:29:36.532111 RPST = 0x0
2198 19:29:36.532192 RD_PRE = 0x0
2199 19:29:36.535273 WR_PRE = 0x1
2200 19:29:36.535354 WR_PST = 0x0
2201 19:29:36.538645 DBI_WR = 0x0
2202 19:29:36.538727 DBI_RD = 0x0
2203 19:29:36.542228 OTF = 0x1
2204 19:29:36.545419 ===================================
2205 19:29:36.548813 ===================================
2206 19:29:36.548894 ANA top config
2207 19:29:36.551903 ===================================
2208 19:29:36.555293 DLL_ASYNC_EN = 0
2209 19:29:36.559083 ALL_SLAVE_EN = 0
2210 19:29:36.562276 NEW_RANK_MODE = 1
2211 19:29:36.562365 DLL_IDLE_MODE = 1
2212 19:29:36.565618 LP45_APHY_COMB_EN = 1
2213 19:29:36.568530 TX_ODT_DIS = 1
2214 19:29:36.571768 NEW_8X_MODE = 1
2215 19:29:36.575198 ===================================
2216 19:29:36.578739 ===================================
2217 19:29:36.581679 data_rate = 2400
2218 19:29:36.581762 CKR = 1
2219 19:29:36.585067 DQ_P2S_RATIO = 8
2220 19:29:36.588601 ===================================
2221 19:29:36.592100 CA_P2S_RATIO = 8
2222 19:29:36.595457 DQ_CA_OPEN = 0
2223 19:29:36.598891 DQ_SEMI_OPEN = 0
2224 19:29:36.601853 CA_SEMI_OPEN = 0
2225 19:29:36.601935 CA_FULL_RATE = 0
2226 19:29:36.605263 DQ_CKDIV4_EN = 0
2227 19:29:36.608530 CA_CKDIV4_EN = 0
2228 19:29:36.612212 CA_PREDIV_EN = 0
2229 19:29:36.615464 PH8_DLY = 17
2230 19:29:36.618379 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2231 19:29:36.618461 DQ_AAMCK_DIV = 4
2232 19:29:36.621746 CA_AAMCK_DIV = 4
2233 19:29:36.625543 CA_ADMCK_DIV = 4
2234 19:29:36.628674 DQ_TRACK_CA_EN = 0
2235 19:29:36.631993 CA_PICK = 1200
2236 19:29:36.635139 CA_MCKIO = 1200
2237 19:29:36.638778 MCKIO_SEMI = 0
2238 19:29:36.638861 PLL_FREQ = 2366
2239 19:29:36.641960 DQ_UI_PI_RATIO = 32
2240 19:29:36.645211 CA_UI_PI_RATIO = 0
2241 19:29:36.648268 ===================================
2242 19:29:36.652412 ===================================
2243 19:29:36.655384 memory_type:LPDDR4
2244 19:29:36.655541 GP_NUM : 10
2245 19:29:36.658327 SRAM_EN : 1
2246 19:29:36.662254 MD32_EN : 0
2247 19:29:36.665047 ===================================
2248 19:29:36.665190 [ANA_INIT] >>>>>>>>>>>>>>
2249 19:29:36.668800 <<<<<< [CONFIGURE PHASE]: ANA_TX
2250 19:29:36.672383 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2251 19:29:36.675887 ===================================
2252 19:29:36.678678 data_rate = 2400,PCW = 0X5b00
2253 19:29:36.681754 ===================================
2254 19:29:36.684928 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2255 19:29:36.691948 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2256 19:29:36.695325 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2257 19:29:36.702353 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2258 19:29:36.705106 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2259 19:29:36.708592 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2260 19:29:36.708776 [ANA_INIT] flow start
2261 19:29:36.711728 [ANA_INIT] PLL >>>>>>>>
2262 19:29:36.715037 [ANA_INIT] PLL <<<<<<<<
2263 19:29:36.718614 [ANA_INIT] MIDPI >>>>>>>>
2264 19:29:36.718815 [ANA_INIT] MIDPI <<<<<<<<
2265 19:29:36.721978 [ANA_INIT] DLL >>>>>>>>
2266 19:29:36.725367 [ANA_INIT] DLL <<<<<<<<
2267 19:29:36.725626 [ANA_INIT] flow end
2268 19:29:36.728873 ============ LP4 DIFF to SE enter ============
2269 19:29:36.735512 ============ LP4 DIFF to SE exit ============
2270 19:29:36.735835 [ANA_INIT] <<<<<<<<<<<<<
2271 19:29:36.738412 [Flow] Enable top DCM control >>>>>
2272 19:29:36.742423 [Flow] Enable top DCM control <<<<<
2273 19:29:36.745611 Enable DLL master slave shuffle
2274 19:29:36.752276 ==============================================================
2275 19:29:36.752809 Gating Mode config
2276 19:29:36.759059 ==============================================================
2277 19:29:36.762177 Config description:
2278 19:29:36.772373 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2279 19:29:36.778761 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2280 19:29:36.782132 SELPH_MODE 0: By rank 1: By Phase
2281 19:29:36.789212 ==============================================================
2282 19:29:36.792415 GAT_TRACK_EN = 1
2283 19:29:36.792989 RX_GATING_MODE = 2
2284 19:29:36.795470 RX_GATING_TRACK_MODE = 2
2285 19:29:36.799341 SELPH_MODE = 1
2286 19:29:36.801783 PICG_EARLY_EN = 1
2287 19:29:36.805424 VALID_LAT_VALUE = 1
2288 19:29:36.812565 ==============================================================
2289 19:29:36.815365 Enter into Gating configuration >>>>
2290 19:29:36.818819 Exit from Gating configuration <<<<
2291 19:29:36.822174 Enter into DVFS_PRE_config >>>>>
2292 19:29:36.832308 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2293 19:29:36.835880 Exit from DVFS_PRE_config <<<<<
2294 19:29:36.838778 Enter into PICG configuration >>>>
2295 19:29:36.841906 Exit from PICG configuration <<<<
2296 19:29:36.845512 [RX_INPUT] configuration >>>>>
2297 19:29:36.845864 [RX_INPUT] configuration <<<<<
2298 19:29:36.851838 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2299 19:29:36.859119 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2300 19:29:36.862114 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2301 19:29:36.868441 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2302 19:29:36.875543 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2303 19:29:36.882083 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2304 19:29:36.885325 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2305 19:29:36.888917 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2306 19:29:36.895779 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2307 19:29:36.899032 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2308 19:29:36.901987 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2309 19:29:36.905711 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2310 19:29:36.908669 ===================================
2311 19:29:36.912177 LPDDR4 DRAM CONFIGURATION
2312 19:29:36.915345 ===================================
2313 19:29:36.919208 EX_ROW_EN[0] = 0x0
2314 19:29:36.919390 EX_ROW_EN[1] = 0x0
2315 19:29:36.922643 LP4Y_EN = 0x0
2316 19:29:36.922807 WORK_FSP = 0x0
2317 19:29:36.925817 WL = 0x4
2318 19:29:36.925961 RL = 0x4
2319 19:29:36.928436 BL = 0x2
2320 19:29:36.928636 RPST = 0x0
2321 19:29:36.932181 RD_PRE = 0x0
2322 19:29:36.932396 WR_PRE = 0x1
2323 19:29:36.935260 WR_PST = 0x0
2324 19:29:36.935428 DBI_WR = 0x0
2325 19:29:36.938481 DBI_RD = 0x0
2326 19:29:36.938680 OTF = 0x1
2327 19:29:36.942172 ===================================
2328 19:29:36.948698 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2329 19:29:36.952580 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2330 19:29:36.955632 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2331 19:29:36.958911 ===================================
2332 19:29:36.962256 LPDDR4 DRAM CONFIGURATION
2333 19:29:36.965850 ===================================
2334 19:29:36.969172 EX_ROW_EN[0] = 0x10
2335 19:29:36.969801 EX_ROW_EN[1] = 0x0
2336 19:29:36.972353 LP4Y_EN = 0x0
2337 19:29:36.972933 WORK_FSP = 0x0
2338 19:29:36.975608 WL = 0x4
2339 19:29:36.976073 RL = 0x4
2340 19:29:36.979553 BL = 0x2
2341 19:29:36.980121 RPST = 0x0
2342 19:29:36.982699 RD_PRE = 0x0
2343 19:29:36.983267 WR_PRE = 0x1
2344 19:29:36.985604 WR_PST = 0x0
2345 19:29:36.986081 DBI_WR = 0x0
2346 19:29:36.989137 DBI_RD = 0x0
2347 19:29:36.989669 OTF = 0x1
2348 19:29:36.992558 ===================================
2349 19:29:36.999013 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2350 19:29:36.999571 ==
2351 19:29:37.002707 Dram Type= 6, Freq= 0, CH_0, rank 0
2352 19:29:37.005735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2353 19:29:37.008760 ==
2354 19:29:37.009225 [Duty_Offset_Calibration]
2355 19:29:37.012359 B0:2 B1:1 CA:1
2356 19:29:37.012825
2357 19:29:37.015747 [DutyScan_Calibration_Flow] k_type=0
2358 19:29:37.024667
2359 19:29:37.025246 ==CLK 0==
2360 19:29:37.027690 Final CLK duty delay cell = 0
2361 19:29:37.031074 [0] MAX Duty = 5218%(X100), DQS PI = 24
2362 19:29:37.034296 [0] MIN Duty = 4844%(X100), DQS PI = 48
2363 19:29:37.037403 [0] AVG Duty = 5031%(X100)
2364 19:29:37.037816
2365 19:29:37.040873 CH0 CLK Duty spec in!! Max-Min= 374%
2366 19:29:37.043981 [DutyScan_Calibration_Flow] ====Done====
2367 19:29:37.044401
2368 19:29:37.047185 [DutyScan_Calibration_Flow] k_type=1
2369 19:29:37.063210
2370 19:29:37.063719 ==DQS 0 ==
2371 19:29:37.066409 Final DQS duty delay cell = -4
2372 19:29:37.069501 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2373 19:29:37.073000 [-4] MIN Duty = 4751%(X100), DQS PI = 0
2374 19:29:37.075829 [-4] AVG Duty = 4937%(X100)
2375 19:29:37.076249
2376 19:29:37.076579 ==DQS 1 ==
2377 19:29:37.079562 Final DQS duty delay cell = 0
2378 19:29:37.082691 [0] MAX Duty = 5156%(X100), DQS PI = 14
2379 19:29:37.086286 [0] MIN Duty = 5000%(X100), DQS PI = 32
2380 19:29:37.089756 [0] AVG Duty = 5078%(X100)
2381 19:29:37.090233
2382 19:29:37.092466 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2383 19:29:37.092926
2384 19:29:37.096008 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2385 19:29:37.099294 [DutyScan_Calibration_Flow] ====Done====
2386 19:29:37.099713
2387 19:29:37.102744 [DutyScan_Calibration_Flow] k_type=3
2388 19:29:37.119492
2389 19:29:37.120062 ==DQM 0 ==
2390 19:29:37.122868 Final DQM duty delay cell = 0
2391 19:29:37.126397 [0] MAX Duty = 5156%(X100), DQS PI = 28
2392 19:29:37.129647 [0] MIN Duty = 4906%(X100), DQS PI = 50
2393 19:29:37.130111 [0] AVG Duty = 5031%(X100)
2394 19:29:37.132902
2395 19:29:37.133330 ==DQM 1 ==
2396 19:29:37.136162 Final DQM duty delay cell = 0
2397 19:29:37.139442 [0] MAX Duty = 5093%(X100), DQS PI = 0
2398 19:29:37.143163 [0] MIN Duty = 5031%(X100), DQS PI = 14
2399 19:29:37.143581 [0] AVG Duty = 5062%(X100)
2400 19:29:37.146697
2401 19:29:37.149573 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2402 19:29:37.150005
2403 19:29:37.153515 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2404 19:29:37.156218 [DutyScan_Calibration_Flow] ====Done====
2405 19:29:37.156767
2406 19:29:37.159874 [DutyScan_Calibration_Flow] k_type=2
2407 19:29:37.176503
2408 19:29:37.177074 ==DQ 0 ==
2409 19:29:37.179419 Final DQ duty delay cell = 0
2410 19:29:37.182560 [0] MAX Duty = 5062%(X100), DQS PI = 32
2411 19:29:37.186443 [0] MIN Duty = 4875%(X100), DQS PI = 0
2412 19:29:37.187015 [0] AVG Duty = 4968%(X100)
2413 19:29:37.187384
2414 19:29:37.189276 ==DQ 1 ==
2415 19:29:37.192674 Final DQ duty delay cell = 0
2416 19:29:37.195855 [0] MAX Duty = 5093%(X100), DQS PI = 24
2417 19:29:37.199705 [0] MIN Duty = 4907%(X100), DQS PI = 36
2418 19:29:37.200271 [0] AVG Duty = 5000%(X100)
2419 19:29:37.200641
2420 19:29:37.202981 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2421 19:29:37.206145
2422 19:29:37.209680 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2423 19:29:37.212979 [DutyScan_Calibration_Flow] ====Done====
2424 19:29:37.213545 ==
2425 19:29:37.216332 Dram Type= 6, Freq= 0, CH_1, rank 0
2426 19:29:37.219351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2427 19:29:37.219918 ==
2428 19:29:37.223260 [Duty_Offset_Calibration]
2429 19:29:37.223832 B0:1 B1:0 CA:0
2430 19:29:37.224198
2431 19:29:37.225659 [DutyScan_Calibration_Flow] k_type=0
2432 19:29:37.235487
2433 19:29:37.236079 ==CLK 0==
2434 19:29:37.238519 Final CLK duty delay cell = -4
2435 19:29:37.242063 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2436 19:29:37.245301 [-4] MIN Duty = 4875%(X100), DQS PI = 50
2437 19:29:37.249035 [-4] AVG Duty = 4953%(X100)
2438 19:29:37.249510
2439 19:29:37.251762 CH1 CLK Duty spec in!! Max-Min= 156%
2440 19:29:37.255392 [DutyScan_Calibration_Flow] ====Done====
2441 19:29:37.255963
2442 19:29:37.258582 [DutyScan_Calibration_Flow] k_type=1
2443 19:29:37.275111
2444 19:29:37.275668 ==DQS 0 ==
2445 19:29:37.278734 Final DQS duty delay cell = 0
2446 19:29:37.282280 [0] MAX Duty = 5062%(X100), DQS PI = 22
2447 19:29:37.285102 [0] MIN Duty = 4844%(X100), DQS PI = 0
2448 19:29:37.285573 [0] AVG Duty = 4953%(X100)
2449 19:29:37.288242
2450 19:29:37.288702 ==DQS 1 ==
2451 19:29:37.291675 Final DQS duty delay cell = 0
2452 19:29:37.295507 [0] MAX Duty = 5187%(X100), DQS PI = 18
2453 19:29:37.298824 [0] MIN Duty = 4969%(X100), DQS PI = 10
2454 19:29:37.299398 [0] AVG Duty = 5078%(X100)
2455 19:29:37.301612
2456 19:29:37.305001 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2457 19:29:37.305466
2458 19:29:37.308444 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2459 19:29:37.311940 [DutyScan_Calibration_Flow] ====Done====
2460 19:29:37.312403
2461 19:29:37.314743 [DutyScan_Calibration_Flow] k_type=3
2462 19:29:37.331646
2463 19:29:37.332215 ==DQM 0 ==
2464 19:29:37.335438 Final DQM duty delay cell = 0
2465 19:29:37.338338 [0] MAX Duty = 5156%(X100), DQS PI = 6
2466 19:29:37.341805 [0] MIN Duty = 5000%(X100), DQS PI = 62
2467 19:29:37.342289 [0] AVG Duty = 5078%(X100)
2468 19:29:37.344718
2469 19:29:37.345187 ==DQM 1 ==
2470 19:29:37.348438 Final DQM duty delay cell = 0
2471 19:29:37.352039 [0] MAX Duty = 5031%(X100), DQS PI = 16
2472 19:29:37.355209 [0] MIN Duty = 4907%(X100), DQS PI = 34
2473 19:29:37.355769 [0] AVG Duty = 4969%(X100)
2474 19:29:37.358812
2475 19:29:37.362195 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2476 19:29:37.362859
2477 19:29:37.365418 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2478 19:29:37.368803 [DutyScan_Calibration_Flow] ====Done====
2479 19:29:37.369360
2480 19:29:37.371511 [DutyScan_Calibration_Flow] k_type=2
2481 19:29:37.387544
2482 19:29:37.388096 ==DQ 0 ==
2483 19:29:37.390811 Final DQ duty delay cell = -4
2484 19:29:37.394218 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2485 19:29:37.397667 [-4] MIN Duty = 4906%(X100), DQS PI = 46
2486 19:29:37.400755 [-4] AVG Duty = 4984%(X100)
2487 19:29:37.401226
2488 19:29:37.401599 ==DQ 1 ==
2489 19:29:37.404375 Final DQ duty delay cell = 0
2490 19:29:37.407562 [0] MAX Duty = 5125%(X100), DQS PI = 20
2491 19:29:37.410485 [0] MIN Duty = 4938%(X100), DQS PI = 34
2492 19:29:37.410971 [0] AVG Duty = 5031%(X100)
2493 19:29:37.414027
2494 19:29:37.417681 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2495 19:29:37.418150
2496 19:29:37.421214 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2497 19:29:37.424264 [DutyScan_Calibration_Flow] ====Done====
2498 19:29:37.427538 nWR fixed to 30
2499 19:29:37.428010 [ModeRegInit_LP4] CH0 RK0
2500 19:29:37.430854 [ModeRegInit_LP4] CH0 RK1
2501 19:29:37.434355 [ModeRegInit_LP4] CH1 RK0
2502 19:29:37.438080 [ModeRegInit_LP4] CH1 RK1
2503 19:29:37.438791 match AC timing 7
2504 19:29:37.441001 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2505 19:29:37.444269 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2506 19:29:37.451151 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2507 19:29:37.454581 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2508 19:29:37.461491 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2509 19:29:37.462058 ==
2510 19:29:37.464420 Dram Type= 6, Freq= 0, CH_0, rank 0
2511 19:29:37.467912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2512 19:29:37.468496 ==
2513 19:29:37.474364 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2514 19:29:37.477900 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2515 19:29:37.488158 [CA 0] Center 39 (8~70) winsize 63
2516 19:29:37.490893 [CA 1] Center 39 (8~70) winsize 63
2517 19:29:37.494377 [CA 2] Center 35 (5~66) winsize 62
2518 19:29:37.498077 [CA 3] Center 34 (4~65) winsize 62
2519 19:29:37.501240 [CA 4] Center 33 (3~64) winsize 62
2520 19:29:37.504700 [CA 5] Center 32 (3~62) winsize 60
2521 19:29:37.505167
2522 19:29:37.507856 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2523 19:29:37.508324
2524 19:29:37.511199 [CATrainingPosCal] consider 1 rank data
2525 19:29:37.514562 u2DelayCellTimex100 = 270/100 ps
2526 19:29:37.517517 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2527 19:29:37.521344 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2528 19:29:37.527528 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2529 19:29:37.531025 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2530 19:29:37.534403 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2531 19:29:37.537864 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2532 19:29:37.538440
2533 19:29:37.541332 CA PerBit enable=1, Macro0, CA PI delay=32
2534 19:29:37.541757
2535 19:29:37.544662 [CBTSetCACLKResult] CA Dly = 32
2536 19:29:37.545185 CS Dly: 5 (0~36)
2537 19:29:37.545525 ==
2538 19:29:37.548576 Dram Type= 6, Freq= 0, CH_0, rank 1
2539 19:29:37.554546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2540 19:29:37.555068 ==
2541 19:29:37.557800 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2542 19:29:37.564171 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2543 19:29:37.573953 [CA 0] Center 38 (8~69) winsize 62
2544 19:29:37.577198 [CA 1] Center 38 (8~69) winsize 62
2545 19:29:37.580472 [CA 2] Center 35 (5~66) winsize 62
2546 19:29:37.583440 [CA 3] Center 34 (4~65) winsize 62
2547 19:29:37.586529 [CA 4] Center 33 (3~64) winsize 62
2548 19:29:37.589884 [CA 5] Center 32 (2~62) winsize 61
2549 19:29:37.590375
2550 19:29:37.593110 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2551 19:29:37.593575
2552 19:29:37.596521 [CATrainingPosCal] consider 2 rank data
2553 19:29:37.600509 u2DelayCellTimex100 = 270/100 ps
2554 19:29:37.603478 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2555 19:29:37.610270 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2556 19:29:37.613595 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2557 19:29:37.616716 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2558 19:29:37.620103 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2559 19:29:37.623344 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2560 19:29:37.624006
2561 19:29:37.626674 CA PerBit enable=1, Macro0, CA PI delay=32
2562 19:29:37.627141
2563 19:29:37.630285 [CBTSetCACLKResult] CA Dly = 32
2564 19:29:37.630786 CS Dly: 6 (0~38)
2565 19:29:37.631156
2566 19:29:37.633179 ----->DramcWriteLeveling(PI) begin...
2567 19:29:37.636516 ==
2568 19:29:37.640052 Dram Type= 6, Freq= 0, CH_0, rank 0
2569 19:29:37.643335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2570 19:29:37.643815 ==
2571 19:29:37.646603 Write leveling (Byte 0): 35 => 35
2572 19:29:37.649885 Write leveling (Byte 1): 30 => 30
2573 19:29:37.653731 DramcWriteLeveling(PI) end<-----
2574 19:29:37.654342
2575 19:29:37.654725 ==
2576 19:29:37.656521 Dram Type= 6, Freq= 0, CH_0, rank 0
2577 19:29:37.659955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2578 19:29:37.660520 ==
2579 19:29:37.663536 [Gating] SW mode calibration
2580 19:29:37.670700 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2581 19:29:37.676629 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2582 19:29:37.679921 0 15 0 | B1->B0 | 2626 3232 | 0 0 | (0 0) (0 0)
2583 19:29:37.683877 0 15 4 | B1->B0 | 3232 3434 | 1 1 | (0 0) (1 1)
2584 19:29:37.686594 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2585 19:29:37.693792 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2586 19:29:37.697139 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2587 19:29:37.700355 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2588 19:29:37.707193 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2589 19:29:37.710543 0 15 28 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
2590 19:29:37.713601 1 0 0 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
2591 19:29:37.720373 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2592 19:29:37.723790 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2593 19:29:37.726799 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2594 19:29:37.733526 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2595 19:29:37.737047 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2596 19:29:37.740038 1 0 24 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
2597 19:29:37.746550 1 0 28 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
2598 19:29:37.750346 1 1 0 | B1->B0 | 3a3a 4646 | 1 0 | (0 0) (0 0)
2599 19:29:37.753547 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2600 19:29:37.760218 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2601 19:29:37.764023 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2602 19:29:37.766845 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2603 19:29:37.770691 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2604 19:29:37.776953 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2605 19:29:37.780224 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2606 19:29:37.783345 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2607 19:29:37.790356 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2608 19:29:37.793656 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2609 19:29:37.796712 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 19:29:37.803626 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 19:29:37.806681 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 19:29:37.810205 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 19:29:37.817347 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 19:29:37.820265 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 19:29:37.823822 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 19:29:37.830004 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 19:29:37.833949 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 19:29:37.837129 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 19:29:37.843736 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 19:29:37.846715 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2621 19:29:37.850488 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2622 19:29:37.856952 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2623 19:29:37.857526 Total UI for P1: 0, mck2ui 16
2624 19:29:37.860141 best dqsien dly found for B0: ( 1, 3, 26)
2625 19:29:37.866631 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2626 19:29:37.870781 Total UI for P1: 0, mck2ui 16
2627 19:29:37.873578 best dqsien dly found for B1: ( 1, 4, 0)
2628 19:29:37.876733 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2629 19:29:37.880037 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2630 19:29:37.880500
2631 19:29:37.883880 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2632 19:29:37.886843 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2633 19:29:37.889913 [Gating] SW calibration Done
2634 19:29:37.890423 ==
2635 19:29:37.893520 Dram Type= 6, Freq= 0, CH_0, rank 0
2636 19:29:37.896735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2637 19:29:37.897205 ==
2638 19:29:37.900763 RX Vref Scan: 0
2639 19:29:37.901322
2640 19:29:37.901707 RX Vref 0 -> 0, step: 1
2641 19:29:37.902152
2642 19:29:37.903620 RX Delay -40 -> 252, step: 8
2643 19:29:37.906699 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2644 19:29:37.913792 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2645 19:29:37.916989 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2646 19:29:37.920219 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2647 19:29:37.924036 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2648 19:29:37.926798 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2649 19:29:37.933692 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2650 19:29:37.937438 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2651 19:29:37.940010 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2652 19:29:37.944258 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2653 19:29:37.947325 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2654 19:29:37.953393 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2655 19:29:37.956945 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2656 19:29:37.960143 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2657 19:29:37.963464 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2658 19:29:37.966672 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2659 19:29:37.970396 ==
2660 19:29:37.970958 Dram Type= 6, Freq= 0, CH_0, rank 0
2661 19:29:37.977125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2662 19:29:37.977706 ==
2663 19:29:37.978076 DQS Delay:
2664 19:29:37.980075 DQS0 = 0, DQS1 = 0
2665 19:29:37.980619 DQM Delay:
2666 19:29:37.983933 DQM0 = 121, DQM1 = 113
2667 19:29:37.984410 DQ Delay:
2668 19:29:37.987144 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2669 19:29:37.990283 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2670 19:29:37.993847 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2671 19:29:37.996806 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2672 19:29:37.997278
2673 19:29:37.997644
2674 19:29:37.998023 ==
2675 19:29:38.000015 Dram Type= 6, Freq= 0, CH_0, rank 0
2676 19:29:38.007124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2677 19:29:38.007590 ==
2678 19:29:38.007960
2679 19:29:38.008301
2680 19:29:38.008625 TX Vref Scan disable
2681 19:29:38.010481 == TX Byte 0 ==
2682 19:29:38.013698 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2683 19:29:38.017297 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2684 19:29:38.020270 == TX Byte 1 ==
2685 19:29:38.023314 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2686 19:29:38.030056 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2687 19:29:38.030613 ==
2688 19:29:38.033475 Dram Type= 6, Freq= 0, CH_0, rank 0
2689 19:29:38.036399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2690 19:29:38.036941 ==
2691 19:29:38.048793 TX Vref=22, minBit 0, minWin=24, winSum=401
2692 19:29:38.051899 TX Vref=24, minBit 3, minWin=25, winSum=412
2693 19:29:38.055229 TX Vref=26, minBit 11, minWin=25, winSum=415
2694 19:29:38.058673 TX Vref=28, minBit 0, minWin=26, winSum=421
2695 19:29:38.061830 TX Vref=30, minBit 10, minWin=25, winSum=417
2696 19:29:38.068743 TX Vref=32, minBit 10, minWin=25, winSum=421
2697 19:29:38.071977 [TxChooseVref] Worse bit 0, Min win 26, Win sum 421, Final Vref 28
2698 19:29:38.072540
2699 19:29:38.075077 Final TX Range 1 Vref 28
2700 19:29:38.075639
2701 19:29:38.076010 ==
2702 19:29:38.078522 Dram Type= 6, Freq= 0, CH_0, rank 0
2703 19:29:38.081984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2704 19:29:38.082592 ==
2705 19:29:38.085354
2706 19:29:38.085910
2707 19:29:38.086276 TX Vref Scan disable
2708 19:29:38.088269 == TX Byte 0 ==
2709 19:29:38.091985 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2710 19:29:38.095127 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2711 19:29:38.098409 == TX Byte 1 ==
2712 19:29:38.102407 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2713 19:29:38.105152 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2714 19:29:38.108557
2715 19:29:38.109018 [DATLAT]
2716 19:29:38.109384 Freq=1200, CH0 RK0
2717 19:29:38.109727
2718 19:29:38.111742 DATLAT Default: 0xd
2719 19:29:38.112220 0, 0xFFFF, sum = 0
2720 19:29:38.115250 1, 0xFFFF, sum = 0
2721 19:29:38.115895 2, 0xFFFF, sum = 0
2722 19:29:38.118491 3, 0xFFFF, sum = 0
2723 19:29:38.118966 4, 0xFFFF, sum = 0
2724 19:29:38.121722 5, 0xFFFF, sum = 0
2725 19:29:38.124938 6, 0xFFFF, sum = 0
2726 19:29:38.125365 7, 0xFFFF, sum = 0
2727 19:29:38.128653 8, 0xFFFF, sum = 0
2728 19:29:38.129082 9, 0xFFFF, sum = 0
2729 19:29:38.132340 10, 0xFFFF, sum = 0
2730 19:29:38.132863 11, 0xFFFF, sum = 0
2731 19:29:38.135134 12, 0x0, sum = 1
2732 19:29:38.135561 13, 0x0, sum = 2
2733 19:29:38.138320 14, 0x0, sum = 3
2734 19:29:38.138754 15, 0x0, sum = 4
2735 19:29:38.139093 best_step = 13
2736 19:29:38.139405
2737 19:29:38.141848 ==
2738 19:29:38.145202 Dram Type= 6, Freq= 0, CH_0, rank 0
2739 19:29:38.148515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2740 19:29:38.149095 ==
2741 19:29:38.149600 RX Vref Scan: 1
2742 19:29:38.149947
2743 19:29:38.151934 Set Vref Range= 32 -> 127
2744 19:29:38.152358
2745 19:29:38.155195 RX Vref 32 -> 127, step: 1
2746 19:29:38.155783
2747 19:29:38.158581 RX Delay -13 -> 252, step: 4
2748 19:29:38.159047
2749 19:29:38.161866 Set Vref, RX VrefLevel [Byte0]: 32
2750 19:29:38.165733 [Byte1]: 32
2751 19:29:38.166263
2752 19:29:38.169037 Set Vref, RX VrefLevel [Byte0]: 33
2753 19:29:38.172122 [Byte1]: 33
2754 19:29:38.172695
2755 19:29:38.175189 Set Vref, RX VrefLevel [Byte0]: 34
2756 19:29:38.178998 [Byte1]: 34
2757 19:29:38.182949
2758 19:29:38.183592 Set Vref, RX VrefLevel [Byte0]: 35
2759 19:29:38.186778 [Byte1]: 35
2760 19:29:38.190953
2761 19:29:38.191520 Set Vref, RX VrefLevel [Byte0]: 36
2762 19:29:38.194568 [Byte1]: 36
2763 19:29:38.198715
2764 19:29:38.199178 Set Vref, RX VrefLevel [Byte0]: 37
2765 19:29:38.202388 [Byte1]: 37
2766 19:29:38.206102
2767 19:29:38.206720 Set Vref, RX VrefLevel [Byte0]: 38
2768 19:29:38.209661 [Byte1]: 38
2769 19:29:38.214073
2770 19:29:38.214715 Set Vref, RX VrefLevel [Byte0]: 39
2771 19:29:38.217499 [Byte1]: 39
2772 19:29:38.222518
2773 19:29:38.222981 Set Vref, RX VrefLevel [Byte0]: 40
2774 19:29:38.226152 [Byte1]: 40
2775 19:29:38.230464
2776 19:29:38.231023 Set Vref, RX VrefLevel [Byte0]: 41
2777 19:29:38.233554 [Byte1]: 41
2778 19:29:38.238202
2779 19:29:38.238814 Set Vref, RX VrefLevel [Byte0]: 42
2780 19:29:38.241286 [Byte1]: 42
2781 19:29:38.245825
2782 19:29:38.246426 Set Vref, RX VrefLevel [Byte0]: 43
2783 19:29:38.252850 [Byte1]: 43
2784 19:29:38.253417
2785 19:29:38.255731 Set Vref, RX VrefLevel [Byte0]: 44
2786 19:29:38.258640 [Byte1]: 44
2787 19:29:38.259105
2788 19:29:38.262607 Set Vref, RX VrefLevel [Byte0]: 45
2789 19:29:38.265288 [Byte1]: 45
2790 19:29:38.269599
2791 19:29:38.270160 Set Vref, RX VrefLevel [Byte0]: 46
2792 19:29:38.272866 [Byte1]: 46
2793 19:29:38.277489
2794 19:29:38.278102 Set Vref, RX VrefLevel [Byte0]: 47
2795 19:29:38.280363 [Byte1]: 47
2796 19:29:38.285233
2797 19:29:38.285723 Set Vref, RX VrefLevel [Byte0]: 48
2798 19:29:38.288670 [Byte1]: 48
2799 19:29:38.292813
2800 19:29:38.293274 Set Vref, RX VrefLevel [Byte0]: 49
2801 19:29:38.296613 [Byte1]: 49
2802 19:29:38.301120
2803 19:29:38.301682 Set Vref, RX VrefLevel [Byte0]: 50
2804 19:29:38.304886 [Byte1]: 50
2805 19:29:38.308804
2806 19:29:38.309270 Set Vref, RX VrefLevel [Byte0]: 51
2807 19:29:38.312224 [Byte1]: 51
2808 19:29:38.316594
2809 19:29:38.317057 Set Vref, RX VrefLevel [Byte0]: 52
2810 19:29:38.320099 [Byte1]: 52
2811 19:29:38.324831
2812 19:29:38.325252 Set Vref, RX VrefLevel [Byte0]: 53
2813 19:29:38.327669 [Byte1]: 53
2814 19:29:38.332856
2815 19:29:38.333385 Set Vref, RX VrefLevel [Byte0]: 54
2816 19:29:38.335689 [Byte1]: 54
2817 19:29:38.340506
2818 19:29:38.341030 Set Vref, RX VrefLevel [Byte0]: 55
2819 19:29:38.343710 [Byte1]: 55
2820 19:29:38.348253
2821 19:29:38.348720 Set Vref, RX VrefLevel [Byte0]: 56
2822 19:29:38.352320 [Byte1]: 56
2823 19:29:38.356248
2824 19:29:38.356816 Set Vref, RX VrefLevel [Byte0]: 57
2825 19:29:38.360093 [Byte1]: 57
2826 19:29:38.364638
2827 19:29:38.365235 Set Vref, RX VrefLevel [Byte0]: 58
2828 19:29:38.367469 [Byte1]: 58
2829 19:29:38.372399
2830 19:29:38.372966 Set Vref, RX VrefLevel [Byte0]: 59
2831 19:29:38.375587 [Byte1]: 59
2832 19:29:38.380280
2833 19:29:38.380817 Set Vref, RX VrefLevel [Byte0]: 60
2834 19:29:38.383311 [Byte1]: 60
2835 19:29:38.387753
2836 19:29:38.388337 Set Vref, RX VrefLevel [Byte0]: 61
2837 19:29:38.391104 [Byte1]: 61
2838 19:29:38.395690
2839 19:29:38.396374 Set Vref, RX VrefLevel [Byte0]: 62
2840 19:29:38.398873 [Byte1]: 62
2841 19:29:38.403849
2842 19:29:38.404420 Set Vref, RX VrefLevel [Byte0]: 63
2843 19:29:38.406872 [Byte1]: 63
2844 19:29:38.411636
2845 19:29:38.412219 Set Vref, RX VrefLevel [Byte0]: 64
2846 19:29:38.414703 [Byte1]: 64
2847 19:29:38.419515
2848 19:29:38.419980 Set Vref, RX VrefLevel [Byte0]: 65
2849 19:29:38.422714 [Byte1]: 65
2850 19:29:38.427355
2851 19:29:38.427926 Set Vref, RX VrefLevel [Byte0]: 66
2852 19:29:38.430408 [Byte1]: 66
2853 19:29:38.435261
2854 19:29:38.435827 Set Vref, RX VrefLevel [Byte0]: 67
2855 19:29:38.438703 [Byte1]: 67
2856 19:29:38.443059
2857 19:29:38.443527 Set Vref, RX VrefLevel [Byte0]: 68
2858 19:29:38.446434 [Byte1]: 68
2859 19:29:38.451363
2860 19:29:38.451930 Final RX Vref Byte 0 = 58 to rank0
2861 19:29:38.454689 Final RX Vref Byte 1 = 45 to rank0
2862 19:29:38.457932 Final RX Vref Byte 0 = 58 to rank1
2863 19:29:38.461086 Final RX Vref Byte 1 = 45 to rank1==
2864 19:29:38.464798 Dram Type= 6, Freq= 0, CH_0, rank 0
2865 19:29:38.467740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2866 19:29:38.470999 ==
2867 19:29:38.471464 DQS Delay:
2868 19:29:38.471830 DQS0 = 0, DQS1 = 0
2869 19:29:38.474784 DQM Delay:
2870 19:29:38.475350 DQM0 = 120, DQM1 = 110
2871 19:29:38.478026 DQ Delay:
2872 19:29:38.481343 DQ0 =120, DQ1 =122, DQ2 =120, DQ3 =118
2873 19:29:38.484523 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2874 19:29:38.487682 DQ8 =96, DQ9 =98, DQ10 =112, DQ11 =102
2875 19:29:38.491461 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =118
2876 19:29:38.491934
2877 19:29:38.492301
2878 19:29:38.498029 [DQSOSCAuto] RK0, (LSB)MR18= 0x120c, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
2879 19:29:38.501436 CH0 RK0: MR19=404, MR18=120C
2880 19:29:38.508255 CH0_RK0: MR19=0x404, MR18=0x120C, DQSOSC=403, MR23=63, INC=40, DEC=26
2881 19:29:38.508815
2882 19:29:38.511200 ----->DramcWriteLeveling(PI) begin...
2883 19:29:38.512033 ==
2884 19:29:38.514689 Dram Type= 6, Freq= 0, CH_0, rank 1
2885 19:29:38.517961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2886 19:29:38.518491 ==
2887 19:29:38.521335 Write leveling (Byte 0): 34 => 34
2888 19:29:38.524477 Write leveling (Byte 1): 28 => 28
2889 19:29:38.528054 DramcWriteLeveling(PI) end<-----
2890 19:29:38.528623
2891 19:29:38.528993 ==
2892 19:29:38.531425 Dram Type= 6, Freq= 0, CH_0, rank 1
2893 19:29:38.534866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2894 19:29:38.538409 ==
2895 19:29:38.538975 [Gating] SW mode calibration
2896 19:29:38.544683 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2897 19:29:38.551190 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2898 19:29:38.554649 0 15 0 | B1->B0 | 3333 2f2f | 1 1 | (1 1) (1 1)
2899 19:29:38.561539 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2900 19:29:38.564817 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2901 19:29:38.567671 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2902 19:29:38.574453 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2903 19:29:38.578445 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2904 19:29:38.581258 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2905 19:29:38.588086 0 15 28 | B1->B0 | 3232 3030 | 0 0 | (1 0) (0 1)
2906 19:29:38.591235 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
2907 19:29:38.595053 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2908 19:29:38.597947 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2909 19:29:38.604704 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2910 19:29:38.608197 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2911 19:29:38.611427 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2912 19:29:38.618137 1 0 24 | B1->B0 | 2525 2424 | 0 0 | (0 0) (0 0)
2913 19:29:38.621427 1 0 28 | B1->B0 | 3333 3736 | 0 1 | (0 0) (0 0)
2914 19:29:38.624783 1 1 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
2915 19:29:38.631177 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2916 19:29:38.634708 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2917 19:29:38.638859 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2918 19:29:38.644481 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2919 19:29:38.648467 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2920 19:29:38.651233 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
2921 19:29:38.658188 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2922 19:29:38.662023 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2923 19:29:38.665411 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 19:29:38.668152 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 19:29:38.675236 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 19:29:38.678757 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 19:29:38.681581 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 19:29:38.688420 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 19:29:38.692088 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 19:29:38.695053 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 19:29:38.701939 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 19:29:38.705408 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 19:29:38.708345 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 19:29:38.715023 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 19:29:38.718381 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 19:29:38.722039 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
2937 19:29:38.728498 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2938 19:29:38.732001 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2939 19:29:38.734875 Total UI for P1: 0, mck2ui 16
2940 19:29:38.738585 best dqsien dly found for B0: ( 1, 3, 28)
2941 19:29:38.741693 Total UI for P1: 0, mck2ui 16
2942 19:29:38.744631 best dqsien dly found for B1: ( 1, 3, 26)
2943 19:29:38.748731 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2944 19:29:38.752108 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
2945 19:29:38.752539
2946 19:29:38.754631 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2947 19:29:38.758230 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
2948 19:29:38.761563 [Gating] SW calibration Done
2949 19:29:38.762093 ==
2950 19:29:38.764596 Dram Type= 6, Freq= 0, CH_0, rank 1
2951 19:29:38.768440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2952 19:29:38.769033 ==
2953 19:29:38.771793 RX Vref Scan: 0
2954 19:29:38.772312
2955 19:29:38.775085 RX Vref 0 -> 0, step: 1
2956 19:29:38.775612
2957 19:29:38.775954 RX Delay -40 -> 252, step: 8
2958 19:29:38.781796 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2959 19:29:38.784849 iDelay=200, Bit 1, Center 123 (56 ~ 191) 136
2960 19:29:38.788356 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2961 19:29:38.791975 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2962 19:29:38.795230 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2963 19:29:38.801716 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2964 19:29:38.804985 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2965 19:29:38.808198 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2966 19:29:38.811672 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2967 19:29:38.815199 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2968 19:29:38.821883 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2969 19:29:38.825269 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2970 19:29:38.828108 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2971 19:29:38.831996 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2972 19:29:38.835241 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2973 19:29:38.841541 iDelay=200, Bit 15, Center 119 (56 ~ 183) 128
2974 19:29:38.842224 ==
2975 19:29:38.844518 Dram Type= 6, Freq= 0, CH_0, rank 1
2976 19:29:38.848173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2977 19:29:38.848601 ==
2978 19:29:38.848942 DQS Delay:
2979 19:29:38.851428 DQS0 = 0, DQS1 = 0
2980 19:29:38.851981 DQM Delay:
2981 19:29:38.855123 DQM0 = 122, DQM1 = 112
2982 19:29:38.855636 DQ Delay:
2983 19:29:38.858462 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2984 19:29:38.861467 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
2985 19:29:38.865116 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2986 19:29:38.868332 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =119
2987 19:29:38.868774
2988 19:29:38.869168
2989 19:29:38.871757 ==
2990 19:29:38.874862 Dram Type= 6, Freq= 0, CH_0, rank 1
2991 19:29:38.878243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2992 19:29:38.878838 ==
2993 19:29:38.879185
2994 19:29:38.879502
2995 19:29:38.881127 TX Vref Scan disable
2996 19:29:38.881553 == TX Byte 0 ==
2997 19:29:38.888071 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2998 19:29:38.891268 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2999 19:29:38.891696 == TX Byte 1 ==
3000 19:29:38.897830 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3001 19:29:38.901552 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3002 19:29:38.902192 ==
3003 19:29:38.905033 Dram Type= 6, Freq= 0, CH_0, rank 1
3004 19:29:38.907833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3005 19:29:38.908267 ==
3006 19:29:38.920718 TX Vref=22, minBit 3, minWin=25, winSum=415
3007 19:29:38.924151 TX Vref=24, minBit 3, minWin=25, winSum=418
3008 19:29:38.927605 TX Vref=26, minBit 0, minWin=26, winSum=425
3009 19:29:38.930436 TX Vref=28, minBit 5, minWin=25, winSum=425
3010 19:29:38.934083 TX Vref=30, minBit 10, minWin=25, winSum=422
3011 19:29:38.937364 TX Vref=32, minBit 3, minWin=26, winSum=426
3012 19:29:38.943567 [TxChooseVref] Worse bit 3, Min win 26, Win sum 426, Final Vref 32
3013 19:29:38.944096
3014 19:29:38.947448 Final TX Range 1 Vref 32
3015 19:29:38.948010
3016 19:29:38.948367 ==
3017 19:29:38.950819 Dram Type= 6, Freq= 0, CH_0, rank 1
3018 19:29:38.954149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3019 19:29:38.954769 ==
3020 19:29:38.957316
3021 19:29:38.957882
3022 19:29:38.958255 TX Vref Scan disable
3023 19:29:38.960928 == TX Byte 0 ==
3024 19:29:38.963853 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3025 19:29:38.970670 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3026 19:29:38.971239 == TX Byte 1 ==
3027 19:29:38.974466 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3028 19:29:38.977616 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3029 19:29:38.980393
3030 19:29:38.980862 [DATLAT]
3031 19:29:38.981259 Freq=1200, CH0 RK1
3032 19:29:38.981667
3033 19:29:38.984070 DATLAT Default: 0xd
3034 19:29:38.984538 0, 0xFFFF, sum = 0
3035 19:29:38.987627 1, 0xFFFF, sum = 0
3036 19:29:38.988205 2, 0xFFFF, sum = 0
3037 19:29:38.990494 3, 0xFFFF, sum = 0
3038 19:29:38.990994 4, 0xFFFF, sum = 0
3039 19:29:38.993919 5, 0xFFFF, sum = 0
3040 19:29:38.997338 6, 0xFFFF, sum = 0
3041 19:29:38.997910 7, 0xFFFF, sum = 0
3042 19:29:39.000804 8, 0xFFFF, sum = 0
3043 19:29:39.001276 9, 0xFFFF, sum = 0
3044 19:29:39.003893 10, 0xFFFF, sum = 0
3045 19:29:39.004366 11, 0xFFFF, sum = 0
3046 19:29:39.008069 12, 0x0, sum = 1
3047 19:29:39.008544 13, 0x0, sum = 2
3048 19:29:39.010865 14, 0x0, sum = 3
3049 19:29:39.011341 15, 0x0, sum = 4
3050 19:29:39.011720 best_step = 13
3051 19:29:39.012063
3052 19:29:39.014335 ==
3053 19:29:39.017380 Dram Type= 6, Freq= 0, CH_0, rank 1
3054 19:29:39.020411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3055 19:29:39.020844 ==
3056 19:29:39.021184 RX Vref Scan: 0
3057 19:29:39.021501
3058 19:29:39.024561 RX Vref 0 -> 0, step: 1
3059 19:29:39.025083
3060 19:29:39.027273 RX Delay -13 -> 252, step: 4
3061 19:29:39.030479 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3062 19:29:39.037276 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3063 19:29:39.040998 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3064 19:29:39.043926 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3065 19:29:39.047375 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3066 19:29:39.050299 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3067 19:29:39.053882 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3068 19:29:39.060800 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3069 19:29:39.064034 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3070 19:29:39.067084 iDelay=195, Bit 9, Center 96 (31 ~ 162) 132
3071 19:29:39.070468 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3072 19:29:39.074148 iDelay=195, Bit 11, Center 102 (39 ~ 166) 128
3073 19:29:39.080463 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3074 19:29:39.083735 iDelay=195, Bit 13, Center 114 (51 ~ 178) 128
3075 19:29:39.087761 iDelay=195, Bit 14, Center 120 (59 ~ 182) 124
3076 19:29:39.090690 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3077 19:29:39.091223 ==
3078 19:29:39.094457 Dram Type= 6, Freq= 0, CH_0, rank 1
3079 19:29:39.100560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3080 19:29:39.101241 ==
3081 19:29:39.101702 DQS Delay:
3082 19:29:39.104276 DQS0 = 0, DQS1 = 0
3083 19:29:39.104797 DQM Delay:
3084 19:29:39.105138 DQM0 = 120, DQM1 = 109
3085 19:29:39.107506 DQ Delay:
3086 19:29:39.110633 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
3087 19:29:39.114360 DQ4 =122, DQ5 =116, DQ6 =126, DQ7 =126
3088 19:29:39.117554 DQ8 =100, DQ9 =96, DQ10 =110, DQ11 =102
3089 19:29:39.120675 DQ12 =114, DQ13 =114, DQ14 =120, DQ15 =118
3090 19:29:39.121181
3091 19:29:39.121549
3092 19:29:39.127806 [DQSOSCAuto] RK1, (LSB)MR18= 0xdee, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 405 ps
3093 19:29:39.130867 CH0 RK1: MR19=403, MR18=DEE
3094 19:29:39.138041 CH0_RK1: MR19=0x403, MR18=0xDEE, DQSOSC=405, MR23=63, INC=39, DEC=26
3095 19:29:39.141115 [RxdqsGatingPostProcess] freq 1200
3096 19:29:39.147395 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3097 19:29:39.147867 best DQS0 dly(2T, 0.5T) = (0, 11)
3098 19:29:39.151571 best DQS1 dly(2T, 0.5T) = (0, 12)
3099 19:29:39.154895 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3100 19:29:39.158087 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3101 19:29:39.161365 best DQS0 dly(2T, 0.5T) = (0, 11)
3102 19:29:39.164307 best DQS1 dly(2T, 0.5T) = (0, 11)
3103 19:29:39.167923 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3104 19:29:39.171319 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3105 19:29:39.174244 Pre-setting of DQS Precalculation
3106 19:29:39.180868 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3107 19:29:39.181442 ==
3108 19:29:39.184168 Dram Type= 6, Freq= 0, CH_1, rank 0
3109 19:29:39.187451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3110 19:29:39.187924 ==
3111 19:29:39.194699 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3112 19:29:39.197561 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3113 19:29:39.206954 [CA 0] Center 37 (7~68) winsize 62
3114 19:29:39.210354 [CA 1] Center 37 (7~68) winsize 62
3115 19:29:39.213282 [CA 2] Center 35 (5~65) winsize 61
3116 19:29:39.217035 [CA 3] Center 34 (4~64) winsize 61
3117 19:29:39.220271 [CA 4] Center 34 (4~64) winsize 61
3118 19:29:39.223498 [CA 5] Center 33 (3~63) winsize 61
3119 19:29:39.223969
3120 19:29:39.226717 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3121 19:29:39.227188
3122 19:29:39.230002 [CATrainingPosCal] consider 1 rank data
3123 19:29:39.233748 u2DelayCellTimex100 = 270/100 ps
3124 19:29:39.236978 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3125 19:29:39.241005 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3126 19:29:39.247012 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3127 19:29:39.250536 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3128 19:29:39.253566 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3129 19:29:39.257326 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3130 19:29:39.257908
3131 19:29:39.260323 CA PerBit enable=1, Macro0, CA PI delay=33
3132 19:29:39.260795
3133 19:29:39.263859 [CBTSetCACLKResult] CA Dly = 33
3134 19:29:39.264429 CS Dly: 8 (0~39)
3135 19:29:39.264805 ==
3136 19:29:39.267108 Dram Type= 6, Freq= 0, CH_1, rank 1
3137 19:29:39.273799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3138 19:29:39.274401 ==
3139 19:29:39.277734 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3140 19:29:39.283919 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3141 19:29:39.292896 [CA 0] Center 37 (7~68) winsize 62
3142 19:29:39.295787 [CA 1] Center 38 (7~69) winsize 63
3143 19:29:39.299338 [CA 2] Center 35 (5~65) winsize 61
3144 19:29:39.302430 [CA 3] Center 34 (4~65) winsize 62
3145 19:29:39.306064 [CA 4] Center 34 (4~65) winsize 62
3146 19:29:39.309515 [CA 5] Center 33 (4~63) winsize 60
3147 19:29:39.309980
3148 19:29:39.312315 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3149 19:29:39.312797
3150 19:29:39.315610 [CATrainingPosCal] consider 2 rank data
3151 19:29:39.318617 u2DelayCellTimex100 = 270/100 ps
3152 19:29:39.321876 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3153 19:29:39.325170 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3154 19:29:39.331976 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3155 19:29:39.335825 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3156 19:29:39.338396 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3157 19:29:39.341993 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3158 19:29:39.342832
3159 19:29:39.345454 CA PerBit enable=1, Macro0, CA PI delay=33
3160 19:29:39.345875
3161 19:29:39.349168 [CBTSetCACLKResult] CA Dly = 33
3162 19:29:39.349592 CS Dly: 8 (0~40)
3163 19:29:39.349924
3164 19:29:39.352217 ----->DramcWriteLeveling(PI) begin...
3165 19:29:39.355426 ==
3166 19:29:39.358850 Dram Type= 6, Freq= 0, CH_1, rank 0
3167 19:29:39.361980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3168 19:29:39.362447 ==
3169 19:29:39.365952 Write leveling (Byte 0): 25 => 25
3170 19:29:39.369041 Write leveling (Byte 1): 30 => 30
3171 19:29:39.372733 DramcWriteLeveling(PI) end<-----
3172 19:29:39.373251
3173 19:29:39.373586 ==
3174 19:29:39.375631 Dram Type= 6, Freq= 0, CH_1, rank 0
3175 19:29:39.379289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3176 19:29:39.379811 ==
3177 19:29:39.382249 [Gating] SW mode calibration
3178 19:29:39.388902 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3179 19:29:39.395798 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3180 19:29:39.399011 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3181 19:29:39.402423 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3182 19:29:39.405913 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3183 19:29:39.412766 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3184 19:29:39.415569 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3185 19:29:39.419465 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3186 19:29:39.425525 0 15 24 | B1->B0 | 3131 2929 | 1 1 | (1 0) (1 0)
3187 19:29:39.429407 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3188 19:29:39.432421 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3189 19:29:39.438813 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3190 19:29:39.442498 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3191 19:29:39.445621 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3192 19:29:39.452850 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3193 19:29:39.455467 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3194 19:29:39.459238 1 0 24 | B1->B0 | 3636 4343 | 0 0 | (0 0) (0 0)
3195 19:29:39.465635 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3196 19:29:39.468887 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3197 19:29:39.472776 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3198 19:29:39.479033 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3199 19:29:39.482402 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3200 19:29:39.486647 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3201 19:29:39.489546 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3202 19:29:39.495623 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3203 19:29:39.499411 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3204 19:29:39.502363 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 19:29:39.508885 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 19:29:39.512621 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 19:29:39.515554 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 19:29:39.522754 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 19:29:39.525603 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 19:29:39.529864 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 19:29:39.536070 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 19:29:39.539055 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 19:29:39.542565 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 19:29:39.549239 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 19:29:39.552517 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 19:29:39.556427 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 19:29:39.562753 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3218 19:29:39.566229 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3219 19:29:39.568982 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3220 19:29:39.572838 Total UI for P1: 0, mck2ui 16
3221 19:29:39.576181 best dqsien dly found for B1: ( 1, 3, 24)
3222 19:29:39.579398 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3223 19:29:39.582267 Total UI for P1: 0, mck2ui 16
3224 19:29:39.585671 best dqsien dly found for B0: ( 1, 3, 24)
3225 19:29:39.589491 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3226 19:29:39.595815 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3227 19:29:39.596301
3228 19:29:39.598812 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3229 19:29:39.602370 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3230 19:29:39.606160 [Gating] SW calibration Done
3231 19:29:39.606668 ==
3232 19:29:39.609068 Dram Type= 6, Freq= 0, CH_1, rank 0
3233 19:29:39.612623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3234 19:29:39.613196 ==
3235 19:29:39.613570 RX Vref Scan: 0
3236 19:29:39.616045
3237 19:29:39.616511 RX Vref 0 -> 0, step: 1
3238 19:29:39.616886
3239 19:29:39.619251 RX Delay -40 -> 252, step: 8
3240 19:29:39.622259 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3241 19:29:39.625536 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3242 19:29:39.632145 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3243 19:29:39.635942 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3244 19:29:39.638920 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3245 19:29:39.642225 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3246 19:29:39.645799 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3247 19:29:39.652706 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3248 19:29:39.655974 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
3249 19:29:39.659132 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3250 19:29:39.662574 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3251 19:29:39.665999 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3252 19:29:39.672715 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3253 19:29:39.676082 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3254 19:29:39.679259 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3255 19:29:39.682851 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3256 19:29:39.683482 ==
3257 19:29:39.685999 Dram Type= 6, Freq= 0, CH_1, rank 0
3258 19:29:39.689083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3259 19:29:39.692778 ==
3260 19:29:39.693246 DQS Delay:
3261 19:29:39.693613 DQS0 = 0, DQS1 = 0
3262 19:29:39.695700 DQM Delay:
3263 19:29:39.696167 DQM0 = 120, DQM1 = 117
3264 19:29:39.699132 DQ Delay:
3265 19:29:39.702426 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3266 19:29:39.706381 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =123
3267 19:29:39.709019 DQ8 =107, DQ9 =107, DQ10 =115, DQ11 =111
3268 19:29:39.712969 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3269 19:29:39.713545
3270 19:29:39.713919
3271 19:29:39.714258 ==
3272 19:29:39.715761 Dram Type= 6, Freq= 0, CH_1, rank 0
3273 19:29:39.719269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3274 19:29:39.719783 ==
3275 19:29:39.720170
3276 19:29:39.722488
3277 19:29:39.722954 TX Vref Scan disable
3278 19:29:39.725712 == TX Byte 0 ==
3279 19:29:39.729158 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3280 19:29:39.732557 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3281 19:29:39.736043 == TX Byte 1 ==
3282 19:29:39.739382 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3283 19:29:39.742350 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3284 19:29:39.742829 ==
3285 19:29:39.745582 Dram Type= 6, Freq= 0, CH_1, rank 0
3286 19:29:39.752634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3287 19:29:39.753209 ==
3288 19:29:39.763267 TX Vref=22, minBit 3, minWin=25, winSum=414
3289 19:29:39.766469 TX Vref=24, minBit 9, minWin=25, winSum=420
3290 19:29:39.769715 TX Vref=26, minBit 1, minWin=26, winSum=426
3291 19:29:39.773380 TX Vref=28, minBit 2, minWin=26, winSum=428
3292 19:29:39.776742 TX Vref=30, minBit 2, minWin=26, winSum=429
3293 19:29:39.780129 TX Vref=32, minBit 10, minWin=25, winSum=430
3294 19:29:39.786295 [TxChooseVref] Worse bit 2, Min win 26, Win sum 429, Final Vref 30
3295 19:29:39.786813
3296 19:29:39.790429 Final TX Range 1 Vref 30
3297 19:29:39.791000
3298 19:29:39.791411 ==
3299 19:29:39.793350 Dram Type= 6, Freq= 0, CH_1, rank 0
3300 19:29:39.797040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3301 19:29:39.797614 ==
3302 19:29:39.797987
3303 19:29:39.799865
3304 19:29:39.800437 TX Vref Scan disable
3305 19:29:39.803359 == TX Byte 0 ==
3306 19:29:39.806514 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3307 19:29:39.809643 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3308 19:29:39.813247 == TX Byte 1 ==
3309 19:29:39.816769 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3310 19:29:39.820128 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3311 19:29:39.820712
3312 19:29:39.822912 [DATLAT]
3313 19:29:39.823371 Freq=1200, CH1 RK0
3314 19:29:39.823803
3315 19:29:39.826182 DATLAT Default: 0xd
3316 19:29:39.826714 0, 0xFFFF, sum = 0
3317 19:29:39.829287 1, 0xFFFF, sum = 0
3318 19:29:39.829759 2, 0xFFFF, sum = 0
3319 19:29:39.832763 3, 0xFFFF, sum = 0
3320 19:29:39.833231 4, 0xFFFF, sum = 0
3321 19:29:39.836582 5, 0xFFFF, sum = 0
3322 19:29:39.839605 6, 0xFFFF, sum = 0
3323 19:29:39.840093 7, 0xFFFF, sum = 0
3324 19:29:39.842883 8, 0xFFFF, sum = 0
3325 19:29:39.843394 9, 0xFFFF, sum = 0
3326 19:29:39.846185 10, 0xFFFF, sum = 0
3327 19:29:39.846709 11, 0xFFFF, sum = 0
3328 19:29:39.849620 12, 0x0, sum = 1
3329 19:29:39.850107 13, 0x0, sum = 2
3330 19:29:39.852770 14, 0x0, sum = 3
3331 19:29:39.853252 15, 0x0, sum = 4
3332 19:29:39.853782 best_step = 13
3333 19:29:39.854241
3334 19:29:39.856005 ==
3335 19:29:39.858995 Dram Type= 6, Freq= 0, CH_1, rank 0
3336 19:29:39.862521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3337 19:29:39.862956 ==
3338 19:29:39.863393 RX Vref Scan: 1
3339 19:29:39.863806
3340 19:29:39.866048 Set Vref Range= 32 -> 127
3341 19:29:39.866530
3342 19:29:39.868952 RX Vref 32 -> 127, step: 1
3343 19:29:39.869386
3344 19:29:39.872732 RX Delay -5 -> 252, step: 4
3345 19:29:39.873286
3346 19:29:39.876447 Set Vref, RX VrefLevel [Byte0]: 32
3347 19:29:39.879147 [Byte1]: 32
3348 19:29:39.879582
3349 19:29:39.882621 Set Vref, RX VrefLevel [Byte0]: 33
3350 19:29:39.886071 [Byte1]: 33
3351 19:29:39.889401
3352 19:29:39.889838 Set Vref, RX VrefLevel [Byte0]: 34
3353 19:29:39.892529 [Byte1]: 34
3354 19:29:39.897331
3355 19:29:39.897770 Set Vref, RX VrefLevel [Byte0]: 35
3356 19:29:39.900220 [Byte1]: 35
3357 19:29:39.904733
3358 19:29:39.905251 Set Vref, RX VrefLevel [Byte0]: 36
3359 19:29:39.908413 [Byte1]: 36
3360 19:29:39.912667
3361 19:29:39.913203 Set Vref, RX VrefLevel [Byte0]: 37
3362 19:29:39.915704 [Byte1]: 37
3363 19:29:39.920373
3364 19:29:39.920901 Set Vref, RX VrefLevel [Byte0]: 38
3365 19:29:39.923821 [Byte1]: 38
3366 19:29:39.928215
3367 19:29:39.928518 Set Vref, RX VrefLevel [Byte0]: 39
3368 19:29:39.931540 [Byte1]: 39
3369 19:29:39.936326
3370 19:29:39.936589 Set Vref, RX VrefLevel [Byte0]: 40
3371 19:29:39.939169 [Byte1]: 40
3372 19:29:39.944046
3373 19:29:39.944226 Set Vref, RX VrefLevel [Byte0]: 41
3374 19:29:39.947350 [Byte1]: 41
3375 19:29:39.951891
3376 19:29:39.952185 Set Vref, RX VrefLevel [Byte0]: 42
3377 19:29:39.955125 [Byte1]: 42
3378 19:29:39.959749
3379 19:29:39.960010 Set Vref, RX VrefLevel [Byte0]: 43
3380 19:29:39.962808 [Byte1]: 43
3381 19:29:39.967160
3382 19:29:39.967428 Set Vref, RX VrefLevel [Byte0]: 44
3383 19:29:39.970604 [Byte1]: 44
3384 19:29:39.975264
3385 19:29:39.975530 Set Vref, RX VrefLevel [Byte0]: 45
3386 19:29:39.978489 [Byte1]: 45
3387 19:29:39.983153
3388 19:29:39.983502 Set Vref, RX VrefLevel [Byte0]: 46
3389 19:29:39.986513 [Byte1]: 46
3390 19:29:39.990951
3391 19:29:39.991276 Set Vref, RX VrefLevel [Byte0]: 47
3392 19:29:39.994489 [Byte1]: 47
3393 19:29:39.999271
3394 19:29:39.999828 Set Vref, RX VrefLevel [Byte0]: 48
3395 19:29:40.002083 [Byte1]: 48
3396 19:29:40.006702
3397 19:29:40.007357 Set Vref, RX VrefLevel [Byte0]: 49
3398 19:29:40.009977 [Byte1]: 49
3399 19:29:40.014693
3400 19:29:40.015265 Set Vref, RX VrefLevel [Byte0]: 50
3401 19:29:40.018485 [Byte1]: 50
3402 19:29:40.022964
3403 19:29:40.023522 Set Vref, RX VrefLevel [Byte0]: 51
3404 19:29:40.026081 [Byte1]: 51
3405 19:29:40.030769
3406 19:29:40.031231 Set Vref, RX VrefLevel [Byte0]: 52
3407 19:29:40.034103 [Byte1]: 52
3408 19:29:40.038616
3409 19:29:40.039171 Set Vref, RX VrefLevel [Byte0]: 53
3410 19:29:40.041548 [Byte1]: 53
3411 19:29:40.046218
3412 19:29:40.046827 Set Vref, RX VrefLevel [Byte0]: 54
3413 19:29:40.049542 [Byte1]: 54
3414 19:29:40.054278
3415 19:29:40.054901 Set Vref, RX VrefLevel [Byte0]: 55
3416 19:29:40.057054 [Byte1]: 55
3417 19:29:40.062091
3418 19:29:40.062687 Set Vref, RX VrefLevel [Byte0]: 56
3419 19:29:40.065067 [Byte1]: 56
3420 19:29:40.070232
3421 19:29:40.070837 Set Vref, RX VrefLevel [Byte0]: 57
3422 19:29:40.073037 [Byte1]: 57
3423 19:29:40.077840
3424 19:29:40.078419 Set Vref, RX VrefLevel [Byte0]: 58
3425 19:29:40.080803 [Byte1]: 58
3426 19:29:40.085584
3427 19:29:40.086086 Set Vref, RX VrefLevel [Byte0]: 59
3428 19:29:40.088553 [Byte1]: 59
3429 19:29:40.093206
3430 19:29:40.096768 Set Vref, RX VrefLevel [Byte0]: 60
3431 19:29:40.099950 [Byte1]: 60
3432 19:29:40.100524
3433 19:29:40.103102 Set Vref, RX VrefLevel [Byte0]: 61
3434 19:29:40.106092 [Byte1]: 61
3435 19:29:40.106607
3436 19:29:40.109427 Set Vref, RX VrefLevel [Byte0]: 62
3437 19:29:40.112969 [Byte1]: 62
3438 19:29:40.117443
3439 19:29:40.118164 Set Vref, RX VrefLevel [Byte0]: 63
3440 19:29:40.120431 [Byte1]: 63
3441 19:29:40.124743
3442 19:29:40.125316 Set Vref, RX VrefLevel [Byte0]: 64
3443 19:29:40.127890 [Byte1]: 64
3444 19:29:40.132718
3445 19:29:40.133188 Set Vref, RX VrefLevel [Byte0]: 65
3446 19:29:40.135853 [Byte1]: 65
3447 19:29:40.140358
3448 19:29:40.140931 Set Vref, RX VrefLevel [Byte0]: 66
3449 19:29:40.143795 [Byte1]: 66
3450 19:29:40.148075
3451 19:29:40.148539 Set Vref, RX VrefLevel [Byte0]: 67
3452 19:29:40.151825 [Byte1]: 67
3453 19:29:40.156128
3454 19:29:40.156594 Set Vref, RX VrefLevel [Byte0]: 68
3455 19:29:40.159305 [Byte1]: 68
3456 19:29:40.163924
3457 19:29:40.164487 Set Vref, RX VrefLevel [Byte0]: 69
3458 19:29:40.167560 [Byte1]: 69
3459 19:29:40.171831
3460 19:29:40.172336 Set Vref, RX VrefLevel [Byte0]: 70
3461 19:29:40.175139 [Byte1]: 70
3462 19:29:40.179638
3463 19:29:40.180209 Final RX Vref Byte 0 = 52 to rank0
3464 19:29:40.183270 Final RX Vref Byte 1 = 47 to rank0
3465 19:29:40.186429 Final RX Vref Byte 0 = 52 to rank1
3466 19:29:40.189526 Final RX Vref Byte 1 = 47 to rank1==
3467 19:29:40.192555 Dram Type= 6, Freq= 0, CH_1, rank 0
3468 19:29:40.199581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3469 19:29:40.200171 ==
3470 19:29:40.200552 DQS Delay:
3471 19:29:40.200896 DQS0 = 0, DQS1 = 0
3472 19:29:40.203256 DQM Delay:
3473 19:29:40.203725 DQM0 = 120, DQM1 = 116
3474 19:29:40.206270 DQ Delay:
3475 19:29:40.209397 DQ0 =122, DQ1 =114, DQ2 =110, DQ3 =116
3476 19:29:40.212915 DQ4 =118, DQ5 =130, DQ6 =130, DQ7 =120
3477 19:29:40.216170 DQ8 =102, DQ9 =106, DQ10 =118, DQ11 =108
3478 19:29:40.219784 DQ12 =122, DQ13 =122, DQ14 =124, DQ15 =126
3479 19:29:40.220316
3480 19:29:40.220689
3481 19:29:40.226242 [DQSOSCAuto] RK0, (LSB)MR18= 0x214, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 409 ps
3482 19:29:40.229701 CH1 RK0: MR19=404, MR18=214
3483 19:29:40.236295 CH1_RK0: MR19=0x404, MR18=0x214, DQSOSC=402, MR23=63, INC=40, DEC=27
3484 19:29:40.236869
3485 19:29:40.239625 ----->DramcWriteLeveling(PI) begin...
3486 19:29:40.240206 ==
3487 19:29:40.242921 Dram Type= 6, Freq= 0, CH_1, rank 1
3488 19:29:40.246100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3489 19:29:40.246615 ==
3490 19:29:40.249758 Write leveling (Byte 0): 26 => 26
3491 19:29:40.252896 Write leveling (Byte 1): 29 => 29
3492 19:29:40.256225 DramcWriteLeveling(PI) end<-----
3493 19:29:40.256853
3494 19:29:40.257240 ==
3495 19:29:40.259389 Dram Type= 6, Freq= 0, CH_1, rank 1
3496 19:29:40.266455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3497 19:29:40.267235 ==
3498 19:29:40.267649 [Gating] SW mode calibration
3499 19:29:40.276492 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3500 19:29:40.279545 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3501 19:29:40.283130 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3502 19:29:40.289561 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3503 19:29:40.293334 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3504 19:29:40.296503 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3505 19:29:40.302798 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3506 19:29:40.306644 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3507 19:29:40.309656 0 15 24 | B1->B0 | 2828 3333 | 0 1 | (0 0) (1 0)
3508 19:29:40.316195 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 0)
3509 19:29:40.319549 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3510 19:29:40.322674 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3511 19:29:40.326496 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3512 19:29:40.332654 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3513 19:29:40.336367 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3514 19:29:40.339620 1 0 20 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3515 19:29:40.345873 1 0 24 | B1->B0 | 4343 2e2e | 0 0 | (0 0) (1 1)
3516 19:29:40.349749 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3517 19:29:40.352757 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3518 19:29:40.359099 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3519 19:29:40.362535 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3520 19:29:40.365866 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3521 19:29:40.372516 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3522 19:29:40.375747 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3523 19:29:40.379054 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3524 19:29:40.385727 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3525 19:29:40.388805 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 19:29:40.395318 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 19:29:40.398405 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 19:29:40.401780 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 19:29:40.405571 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3530 19:29:40.412352 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3531 19:29:40.415497 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3532 19:29:40.418517 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3533 19:29:40.425241 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3534 19:29:40.428378 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3535 19:29:40.431524 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3536 19:29:40.438935 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3537 19:29:40.441933 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3538 19:29:40.445076 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3539 19:29:40.452125 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3540 19:29:40.455384 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3541 19:29:40.458397 Total UI for P1: 0, mck2ui 16
3542 19:29:40.461891 best dqsien dly found for B0: ( 1, 3, 26)
3543 19:29:40.465088 Total UI for P1: 0, mck2ui 16
3544 19:29:40.468297 best dqsien dly found for B1: ( 1, 3, 24)
3545 19:29:40.472065 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3546 19:29:40.475404 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3547 19:29:40.475761
3548 19:29:40.478672 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3549 19:29:40.481950 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3550 19:29:40.484809 [Gating] SW calibration Done
3551 19:29:40.485222 ==
3552 19:29:40.488820 Dram Type= 6, Freq= 0, CH_1, rank 1
3553 19:29:40.495411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3554 19:29:40.495978 ==
3555 19:29:40.496349 RX Vref Scan: 0
3556 19:29:40.496689
3557 19:29:40.498596 RX Vref 0 -> 0, step: 1
3558 19:29:40.499055
3559 19:29:40.502086 RX Delay -40 -> 252, step: 8
3560 19:29:40.505420 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3561 19:29:40.508195 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3562 19:29:40.511432 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3563 19:29:40.514786 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3564 19:29:40.521548 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3565 19:29:40.524782 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3566 19:29:40.527970 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3567 19:29:40.532033 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3568 19:29:40.534821 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
3569 19:29:40.541310 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3570 19:29:40.544820 iDelay=200, Bit 10, Center 119 (56 ~ 183) 128
3571 19:29:40.547900 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3572 19:29:40.551774 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3573 19:29:40.558123 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3574 19:29:40.561500 iDelay=200, Bit 14, Center 119 (56 ~ 183) 128
3575 19:29:40.565132 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
3576 19:29:40.565665 ==
3577 19:29:40.568231 Dram Type= 6, Freq= 0, CH_1, rank 1
3578 19:29:40.571223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3579 19:29:40.571903 ==
3580 19:29:40.575226 DQS Delay:
3581 19:29:40.575802 DQS0 = 0, DQS1 = 0
3582 19:29:40.578243 DQM Delay:
3583 19:29:40.578887 DQM0 = 120, DQM1 = 118
3584 19:29:40.579270 DQ Delay:
3585 19:29:40.584675 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3586 19:29:40.588170 DQ4 =119, DQ5 =131, DQ6 =131, DQ7 =119
3587 19:29:40.591279 DQ8 =107, DQ9 =107, DQ10 =119, DQ11 =115
3588 19:29:40.594728 DQ12 =127, DQ13 =127, DQ14 =119, DQ15 =127
3589 19:29:40.595200
3590 19:29:40.595568
3591 19:29:40.595912 ==
3592 19:29:40.598050 Dram Type= 6, Freq= 0, CH_1, rank 1
3593 19:29:40.601820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3594 19:29:40.602421 ==
3595 19:29:40.602814
3596 19:29:40.603157
3597 19:29:40.604450 TX Vref Scan disable
3598 19:29:40.607840 == TX Byte 0 ==
3599 19:29:40.611039 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3600 19:29:40.615019 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3601 19:29:40.618170 == TX Byte 1 ==
3602 19:29:40.621068 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3603 19:29:40.624232 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3604 19:29:40.624739 ==
3605 19:29:40.628136 Dram Type= 6, Freq= 0, CH_1, rank 1
3606 19:29:40.630906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3607 19:29:40.634456 ==
3608 19:29:40.644955 TX Vref=22, minBit 2, minWin=25, winSum=421
3609 19:29:40.647570 TX Vref=24, minBit 9, minWin=25, winSum=423
3610 19:29:40.651052 TX Vref=26, minBit 2, minWin=26, winSum=428
3611 19:29:40.654379 TX Vref=28, minBit 9, minWin=26, winSum=432
3612 19:29:40.658036 TX Vref=30, minBit 9, minWin=26, winSum=434
3613 19:29:40.661021 TX Vref=32, minBit 1, minWin=26, winSum=436
3614 19:29:40.668080 [TxChooseVref] Worse bit 1, Min win 26, Win sum 436, Final Vref 32
3615 19:29:40.668643
3616 19:29:40.671735 Final TX Range 1 Vref 32
3617 19:29:40.672201
3618 19:29:40.672567 ==
3619 19:29:40.674750 Dram Type= 6, Freq= 0, CH_1, rank 1
3620 19:29:40.677658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3621 19:29:40.678217 ==
3622 19:29:40.678631
3623 19:29:40.681552
3624 19:29:40.682116 TX Vref Scan disable
3625 19:29:40.684524 == TX Byte 0 ==
3626 19:29:40.687715 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3627 19:29:40.690827 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3628 19:29:40.694509 == TX Byte 1 ==
3629 19:29:40.697669 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3630 19:29:40.700967 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3631 19:29:40.704548
3632 19:29:40.705163 [DATLAT]
3633 19:29:40.705703 Freq=1200, CH1 RK1
3634 19:29:40.706067
3635 19:29:40.707425 DATLAT Default: 0xd
3636 19:29:40.707893 0, 0xFFFF, sum = 0
3637 19:29:40.710734 1, 0xFFFF, sum = 0
3638 19:29:40.711210 2, 0xFFFF, sum = 0
3639 19:29:40.714190 3, 0xFFFF, sum = 0
3640 19:29:40.714715 4, 0xFFFF, sum = 0
3641 19:29:40.717288 5, 0xFFFF, sum = 0
3642 19:29:40.720985 6, 0xFFFF, sum = 0
3643 19:29:40.721420 7, 0xFFFF, sum = 0
3644 19:29:40.724667 8, 0xFFFF, sum = 0
3645 19:29:40.725237 9, 0xFFFF, sum = 0
3646 19:29:40.727769 10, 0xFFFF, sum = 0
3647 19:29:40.728337 11, 0xFFFF, sum = 0
3648 19:29:40.730755 12, 0x0, sum = 1
3649 19:29:40.731249 13, 0x0, sum = 2
3650 19:29:40.733695 14, 0x0, sum = 3
3651 19:29:40.734169 15, 0x0, sum = 4
3652 19:29:40.734620 best_step = 13
3653 19:29:40.737741
3654 19:29:40.738334 ==
3655 19:29:40.741212 Dram Type= 6, Freq= 0, CH_1, rank 1
3656 19:29:40.744123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3657 19:29:40.744620 ==
3658 19:29:40.745033 RX Vref Scan: 0
3659 19:29:40.745387
3660 19:29:40.747313 RX Vref 0 -> 0, step: 1
3661 19:29:40.747782
3662 19:29:40.750483 RX Delay -5 -> 252, step: 4
3663 19:29:40.753999 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3664 19:29:40.760688 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3665 19:29:40.764181 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3666 19:29:40.767353 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3667 19:29:40.770944 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3668 19:29:40.773918 iDelay=195, Bit 5, Center 132 (71 ~ 194) 124
3669 19:29:40.780371 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3670 19:29:40.784048 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3671 19:29:40.787450 iDelay=195, Bit 8, Center 104 (43 ~ 166) 124
3672 19:29:40.790609 iDelay=195, Bit 9, Center 104 (43 ~ 166) 124
3673 19:29:40.794191 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3674 19:29:40.800557 iDelay=195, Bit 11, Center 110 (51 ~ 170) 120
3675 19:29:40.803537 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3676 19:29:40.807356 iDelay=195, Bit 13, Center 122 (63 ~ 182) 120
3677 19:29:40.810184 iDelay=195, Bit 14, Center 120 (63 ~ 178) 116
3678 19:29:40.813886 iDelay=195, Bit 15, Center 124 (63 ~ 186) 124
3679 19:29:40.816960 ==
3680 19:29:40.820252 Dram Type= 6, Freq= 0, CH_1, rank 1
3681 19:29:40.823381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3682 19:29:40.823859 ==
3683 19:29:40.824231 DQS Delay:
3684 19:29:40.827005 DQS0 = 0, DQS1 = 0
3685 19:29:40.827476 DQM Delay:
3686 19:29:40.830475 DQM0 = 120, DQM1 = 115
3687 19:29:40.830944 DQ Delay:
3688 19:29:40.833691 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =118
3689 19:29:40.836734 DQ4 =116, DQ5 =132, DQ6 =130, DQ7 =120
3690 19:29:40.840553 DQ8 =104, DQ9 =104, DQ10 =116, DQ11 =110
3691 19:29:40.843660 DQ12 =126, DQ13 =122, DQ14 =120, DQ15 =124
3692 19:29:40.844130
3693 19:29:40.844495
3694 19:29:40.854101 [DQSOSCAuto] RK1, (LSB)MR18= 0x11ed, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 403 ps
3695 19:29:40.854731 CH1 RK1: MR19=403, MR18=11ED
3696 19:29:40.860346 CH1_RK1: MR19=0x403, MR18=0x11ED, DQSOSC=403, MR23=63, INC=40, DEC=26
3697 19:29:40.863758 [RxdqsGatingPostProcess] freq 1200
3698 19:29:40.870411 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3699 19:29:40.874205 best DQS0 dly(2T, 0.5T) = (0, 11)
3700 19:29:40.877077 best DQS1 dly(2T, 0.5T) = (0, 11)
3701 19:29:40.880466 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3702 19:29:40.883398 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3703 19:29:40.886602 best DQS0 dly(2T, 0.5T) = (0, 11)
3704 19:29:40.890148 best DQS1 dly(2T, 0.5T) = (0, 11)
3705 19:29:40.894019 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3706 19:29:40.896778 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3707 19:29:40.897249 Pre-setting of DQS Precalculation
3708 19:29:40.903446 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3709 19:29:40.910196 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3710 19:29:40.916399 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3711 19:29:40.916945
3712 19:29:40.917318
3713 19:29:40.920231 [Calibration Summary] 2400 Mbps
3714 19:29:40.923838 CH 0, Rank 0
3715 19:29:40.924413 SW Impedance : PASS
3716 19:29:40.927066 DUTY Scan : NO K
3717 19:29:40.930341 ZQ Calibration : PASS
3718 19:29:40.930824 Jitter Meter : NO K
3719 19:29:40.933547 CBT Training : PASS
3720 19:29:40.936492 Write leveling : PASS
3721 19:29:40.936962 RX DQS gating : PASS
3722 19:29:40.940017 RX DQ/DQS(RDDQC) : PASS
3723 19:29:40.940602 TX DQ/DQS : PASS
3724 19:29:40.943212 RX DATLAT : PASS
3725 19:29:40.946393 RX DQ/DQS(Engine): PASS
3726 19:29:40.947057 TX OE : NO K
3727 19:29:40.950040 All Pass.
3728 19:29:40.950575
3729 19:29:40.950952 CH 0, Rank 1
3730 19:29:40.953196 SW Impedance : PASS
3731 19:29:40.953661 DUTY Scan : NO K
3732 19:29:40.956673 ZQ Calibration : PASS
3733 19:29:40.960168 Jitter Meter : NO K
3734 19:29:40.960729 CBT Training : PASS
3735 19:29:40.963248 Write leveling : PASS
3736 19:29:40.966423 RX DQS gating : PASS
3737 19:29:40.966893 RX DQ/DQS(RDDQC) : PASS
3738 19:29:40.969558 TX DQ/DQS : PASS
3739 19:29:40.972822 RX DATLAT : PASS
3740 19:29:40.973290 RX DQ/DQS(Engine): PASS
3741 19:29:40.976763 TX OE : NO K
3742 19:29:40.977328 All Pass.
3743 19:29:40.977699
3744 19:29:40.979428 CH 1, Rank 0
3745 19:29:40.979896 SW Impedance : PASS
3746 19:29:40.983053 DUTY Scan : NO K
3747 19:29:40.986426 ZQ Calibration : PASS
3748 19:29:40.986900 Jitter Meter : NO K
3749 19:29:40.989631 CBT Training : PASS
3750 19:29:40.993016 Write leveling : PASS
3751 19:29:40.993575 RX DQS gating : PASS
3752 19:29:40.995934 RX DQ/DQS(RDDQC) : PASS
3753 19:29:40.999629 TX DQ/DQS : PASS
3754 19:29:41.000190 RX DATLAT : PASS
3755 19:29:41.003251 RX DQ/DQS(Engine): PASS
3756 19:29:41.005964 TX OE : NO K
3757 19:29:41.006479 All Pass.
3758 19:29:41.006859
3759 19:29:41.007207 CH 1, Rank 1
3760 19:29:41.009636 SW Impedance : PASS
3761 19:29:41.013339 DUTY Scan : NO K
3762 19:29:41.013903 ZQ Calibration : PASS
3763 19:29:41.016133 Jitter Meter : NO K
3764 19:29:41.016602 CBT Training : PASS
3765 19:29:41.019035 Write leveling : PASS
3766 19:29:41.022827 RX DQS gating : PASS
3767 19:29:41.023377 RX DQ/DQS(RDDQC) : PASS
3768 19:29:41.025952 TX DQ/DQS : PASS
3769 19:29:41.029388 RX DATLAT : PASS
3770 19:29:41.029949 RX DQ/DQS(Engine): PASS
3771 19:29:41.032259 TX OE : NO K
3772 19:29:41.032731 All Pass.
3773 19:29:41.033102
3774 19:29:41.035984 DramC Write-DBI off
3775 19:29:41.039094 PER_BANK_REFRESH: Hybrid Mode
3776 19:29:41.039564 TX_TRACKING: ON
3777 19:29:41.048801 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3778 19:29:41.052350 [FAST_K] Save calibration result to emmc
3779 19:29:41.055776 dramc_set_vcore_voltage set vcore to 650000
3780 19:29:41.059031 Read voltage for 600, 5
3781 19:29:41.059455 Vio18 = 0
3782 19:29:41.059794 Vcore = 650000
3783 19:29:41.062550 Vdram = 0
3784 19:29:41.063065 Vddq = 0
3785 19:29:41.063407 Vmddr = 0
3786 19:29:41.069066 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3787 19:29:41.072080 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3788 19:29:41.076029 MEM_TYPE=3, freq_sel=19
3789 19:29:41.079247 sv_algorithm_assistance_LP4_1600
3790 19:29:41.082671 ============ PULL DRAM RESETB DOWN ============
3791 19:29:41.085315 ========== PULL DRAM RESETB DOWN end =========
3792 19:29:41.092079 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3793 19:29:41.096233 ===================================
3794 19:29:41.099705 LPDDR4 DRAM CONFIGURATION
3795 19:29:41.102524 ===================================
3796 19:29:41.102990 EX_ROW_EN[0] = 0x0
3797 19:29:41.106048 EX_ROW_EN[1] = 0x0
3798 19:29:41.106653 LP4Y_EN = 0x0
3799 19:29:41.109159 WORK_FSP = 0x0
3800 19:29:41.109742 WL = 0x2
3801 19:29:41.112067 RL = 0x2
3802 19:29:41.112535 BL = 0x2
3803 19:29:41.115944 RPST = 0x0
3804 19:29:41.116503 RD_PRE = 0x0
3805 19:29:41.118905 WR_PRE = 0x1
3806 19:29:41.119369 WR_PST = 0x0
3807 19:29:41.121961 DBI_WR = 0x0
3808 19:29:41.122471 DBI_RD = 0x0
3809 19:29:41.125953 OTF = 0x1
3810 19:29:41.128969 ===================================
3811 19:29:41.132038 ===================================
3812 19:29:41.132505 ANA top config
3813 19:29:41.135786 ===================================
3814 19:29:41.138870 DLL_ASYNC_EN = 0
3815 19:29:41.142288 ALL_SLAVE_EN = 1
3816 19:29:41.145436 NEW_RANK_MODE = 1
3817 19:29:41.145947 DLL_IDLE_MODE = 1
3818 19:29:41.149036 LP45_APHY_COMB_EN = 1
3819 19:29:41.151914 TX_ODT_DIS = 1
3820 19:29:41.155266 NEW_8X_MODE = 1
3821 19:29:41.158518 ===================================
3822 19:29:41.162462 ===================================
3823 19:29:41.165440 data_rate = 1200
3824 19:29:41.169443 CKR = 1
3825 19:29:41.170002 DQ_P2S_RATIO = 8
3826 19:29:41.172008 ===================================
3827 19:29:41.175537 CA_P2S_RATIO = 8
3828 19:29:41.179002 DQ_CA_OPEN = 0
3829 19:29:41.182274 DQ_SEMI_OPEN = 0
3830 19:29:41.185058 CA_SEMI_OPEN = 0
3831 19:29:41.185527 CA_FULL_RATE = 0
3832 19:29:41.189107 DQ_CKDIV4_EN = 1
3833 19:29:41.192068 CA_CKDIV4_EN = 1
3834 19:29:41.195202 CA_PREDIV_EN = 0
3835 19:29:41.198775 PH8_DLY = 0
3836 19:29:41.201799 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3837 19:29:41.202265 DQ_AAMCK_DIV = 4
3838 19:29:41.205535 CA_AAMCK_DIV = 4
3839 19:29:41.208734 CA_ADMCK_DIV = 4
3840 19:29:41.211797 DQ_TRACK_CA_EN = 0
3841 19:29:41.215206 CA_PICK = 600
3842 19:29:41.218657 CA_MCKIO = 600
3843 19:29:41.219168 MCKIO_SEMI = 0
3844 19:29:41.222389 PLL_FREQ = 2288
3845 19:29:41.225593 DQ_UI_PI_RATIO = 32
3846 19:29:41.229025 CA_UI_PI_RATIO = 0
3847 19:29:41.232156 ===================================
3848 19:29:41.235489 ===================================
3849 19:29:41.238648 memory_type:LPDDR4
3850 19:29:41.239114 GP_NUM : 10
3851 19:29:41.241890 SRAM_EN : 1
3852 19:29:41.245336 MD32_EN : 0
3853 19:29:41.248627 ===================================
3854 19:29:41.249099 [ANA_INIT] >>>>>>>>>>>>>>
3855 19:29:41.251813 <<<<<< [CONFIGURE PHASE]: ANA_TX
3856 19:29:41.255139 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3857 19:29:41.258253 ===================================
3858 19:29:41.262099 data_rate = 1200,PCW = 0X5800
3859 19:29:41.265041 ===================================
3860 19:29:41.268587 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3861 19:29:41.274759 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3862 19:29:41.278370 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3863 19:29:41.285049 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3864 19:29:41.288129 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3865 19:29:41.291668 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3866 19:29:41.294517 [ANA_INIT] flow start
3867 19:29:41.294966 [ANA_INIT] PLL >>>>>>>>
3868 19:29:41.298278 [ANA_INIT] PLL <<<<<<<<
3869 19:29:41.301406 [ANA_INIT] MIDPI >>>>>>>>
3870 19:29:41.301923 [ANA_INIT] MIDPI <<<<<<<<
3871 19:29:41.304485 [ANA_INIT] DLL >>>>>>>>
3872 19:29:41.308020 [ANA_INIT] flow end
3873 19:29:41.311590 ============ LP4 DIFF to SE enter ============
3874 19:29:41.314881 ============ LP4 DIFF to SE exit ============
3875 19:29:41.318212 [ANA_INIT] <<<<<<<<<<<<<
3876 19:29:41.321262 [Flow] Enable top DCM control >>>>>
3877 19:29:41.324890 [Flow] Enable top DCM control <<<<<
3878 19:29:41.328271 Enable DLL master slave shuffle
3879 19:29:41.331330 ==============================================================
3880 19:29:41.334863 Gating Mode config
3881 19:29:41.341170 ==============================================================
3882 19:29:41.341748 Config description:
3883 19:29:41.350925 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3884 19:29:41.358137 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3885 19:29:41.361217 SELPH_MODE 0: By rank 1: By Phase
3886 19:29:41.367516 ==============================================================
3887 19:29:41.370966 GAT_TRACK_EN = 1
3888 19:29:41.373998 RX_GATING_MODE = 2
3889 19:29:41.377523 RX_GATING_TRACK_MODE = 2
3890 19:29:41.380638 SELPH_MODE = 1
3891 19:29:41.383866 PICG_EARLY_EN = 1
3892 19:29:41.387938 VALID_LAT_VALUE = 1
3893 19:29:41.390857 ==============================================================
3894 19:29:41.393955 Enter into Gating configuration >>>>
3895 19:29:41.397343 Exit from Gating configuration <<<<
3896 19:29:41.400796 Enter into DVFS_PRE_config >>>>>
3897 19:29:41.413946 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3898 19:29:41.414545 Exit from DVFS_PRE_config <<<<<
3899 19:29:41.417444 Enter into PICG configuration >>>>
3900 19:29:41.421212 Exit from PICG configuration <<<<
3901 19:29:41.424134 [RX_INPUT] configuration >>>>>
3902 19:29:41.427532 [RX_INPUT] configuration <<<<<
3903 19:29:41.433896 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3904 19:29:41.437509 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3905 19:29:41.443848 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3906 19:29:41.450539 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3907 19:29:41.456994 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3908 19:29:41.464072 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3909 19:29:41.467114 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3910 19:29:41.470350 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3911 19:29:41.474383 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3912 19:29:41.480976 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3913 19:29:41.483602 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3914 19:29:41.487509 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3915 19:29:41.490658 ===================================
3916 19:29:41.493962 LPDDR4 DRAM CONFIGURATION
3917 19:29:41.496979 ===================================
3918 19:29:41.497467 EX_ROW_EN[0] = 0x0
3919 19:29:41.500275 EX_ROW_EN[1] = 0x0
3920 19:29:41.503814 LP4Y_EN = 0x0
3921 19:29:41.504282 WORK_FSP = 0x0
3922 19:29:41.506813 WL = 0x2
3923 19:29:41.507283 RL = 0x2
3924 19:29:41.510166 BL = 0x2
3925 19:29:41.510681 RPST = 0x0
3926 19:29:41.513105 RD_PRE = 0x0
3927 19:29:41.513574 WR_PRE = 0x1
3928 19:29:41.516309 WR_PST = 0x0
3929 19:29:41.516733 DBI_WR = 0x0
3930 19:29:41.519825 DBI_RD = 0x0
3931 19:29:41.520247 OTF = 0x1
3932 19:29:41.523441 ===================================
3933 19:29:41.526596 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3934 19:29:41.533865 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3935 19:29:41.537048 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3936 19:29:41.539816 ===================================
3937 19:29:41.543314 LPDDR4 DRAM CONFIGURATION
3938 19:29:41.546746 ===================================
3939 19:29:41.547269 EX_ROW_EN[0] = 0x10
3940 19:29:41.549659 EX_ROW_EN[1] = 0x0
3941 19:29:41.553042 LP4Y_EN = 0x0
3942 19:29:41.553470 WORK_FSP = 0x0
3943 19:29:41.556655 WL = 0x2
3944 19:29:41.557079 RL = 0x2
3945 19:29:41.560033 BL = 0x2
3946 19:29:41.560554 RPST = 0x0
3947 19:29:41.563256 RD_PRE = 0x0
3948 19:29:41.563680 WR_PRE = 0x1
3949 19:29:41.566463 WR_PST = 0x0
3950 19:29:41.566886 DBI_WR = 0x0
3951 19:29:41.569984 DBI_RD = 0x0
3952 19:29:41.570555 OTF = 0x1
3953 19:29:41.572989 ===================================
3954 19:29:41.579850 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3955 19:29:41.584147 nWR fixed to 30
3956 19:29:41.587732 [ModeRegInit_LP4] CH0 RK0
3957 19:29:41.588194 [ModeRegInit_LP4] CH0 RK1
3958 19:29:41.590612 [ModeRegInit_LP4] CH1 RK0
3959 19:29:41.594558 [ModeRegInit_LP4] CH1 RK1
3960 19:29:41.595119 match AC timing 17
3961 19:29:41.601070 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3962 19:29:41.604067 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3963 19:29:41.607742 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3964 19:29:41.613938 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3965 19:29:41.617428 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3966 19:29:41.618004 ==
3967 19:29:41.620954 Dram Type= 6, Freq= 0, CH_0, rank 0
3968 19:29:41.624356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3969 19:29:41.624923 ==
3970 19:29:41.630992 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3971 19:29:41.637531 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3972 19:29:41.640540 [CA 0] Center 35 (5~66) winsize 62
3973 19:29:41.643974 [CA 1] Center 36 (5~67) winsize 63
3974 19:29:41.647114 [CA 2] Center 34 (3~65) winsize 63
3975 19:29:41.650778 [CA 3] Center 33 (3~64) winsize 62
3976 19:29:41.654366 [CA 4] Center 33 (2~64) winsize 63
3977 19:29:41.657559 [CA 5] Center 32 (2~63) winsize 62
3978 19:29:41.658122
3979 19:29:41.661023 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3980 19:29:41.661584
3981 19:29:41.664491 [CATrainingPosCal] consider 1 rank data
3982 19:29:41.667298 u2DelayCellTimex100 = 270/100 ps
3983 19:29:41.670896 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3984 19:29:41.674080 CA1 delay=36 (5~67),Diff = 4 PI (38 cell)
3985 19:29:41.677156 CA2 delay=34 (3~65),Diff = 2 PI (19 cell)
3986 19:29:41.680694 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3987 19:29:41.684065 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3988 19:29:41.687134 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3989 19:29:41.690483
3990 19:29:41.693851 CA PerBit enable=1, Macro0, CA PI delay=32
3991 19:29:41.694276
3992 19:29:41.697333 [CBTSetCACLKResult] CA Dly = 32
3993 19:29:41.697866 CS Dly: 4 (0~35)
3994 19:29:41.698208 ==
3995 19:29:41.700385 Dram Type= 6, Freq= 0, CH_0, rank 1
3996 19:29:41.703740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3997 19:29:41.704265 ==
3998 19:29:41.710563 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3999 19:29:41.717175 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4000 19:29:41.720120 [CA 0] Center 35 (5~66) winsize 62
4001 19:29:41.724182 [CA 1] Center 35 (5~66) winsize 62
4002 19:29:41.726976 [CA 2] Center 34 (3~65) winsize 63
4003 19:29:41.730480 [CA 3] Center 33 (3~64) winsize 62
4004 19:29:41.734332 [CA 4] Center 33 (2~64) winsize 63
4005 19:29:41.737173 [CA 5] Center 32 (2~63) winsize 62
4006 19:29:41.737699
4007 19:29:41.740560 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4008 19:29:41.741088
4009 19:29:41.743638 [CATrainingPosCal] consider 2 rank data
4010 19:29:41.746492 u2DelayCellTimex100 = 270/100 ps
4011 19:29:41.750016 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4012 19:29:41.753444 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
4013 19:29:41.756543 CA2 delay=34 (3~65),Diff = 2 PI (19 cell)
4014 19:29:41.760187 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4015 19:29:41.767117 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
4016 19:29:41.770374 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4017 19:29:41.770897
4018 19:29:41.773428 CA PerBit enable=1, Macro0, CA PI delay=32
4019 19:29:41.773855
4020 19:29:41.777001 [CBTSetCACLKResult] CA Dly = 32
4021 19:29:41.777519 CS Dly: 4 (0~36)
4022 19:29:41.777860
4023 19:29:41.780420 ----->DramcWriteLeveling(PI) begin...
4024 19:29:41.780956 ==
4025 19:29:41.783072 Dram Type= 6, Freq= 0, CH_0, rank 0
4026 19:29:41.789974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4027 19:29:41.790517 ==
4028 19:29:41.793133 Write leveling (Byte 0): 34 => 34
4029 19:29:41.796765 Write leveling (Byte 1): 30 => 30
4030 19:29:41.797304 DramcWriteLeveling(PI) end<-----
4031 19:29:41.797654
4032 19:29:41.799920 ==
4033 19:29:41.803796 Dram Type= 6, Freq= 0, CH_0, rank 0
4034 19:29:41.806502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4035 19:29:41.806933 ==
4036 19:29:41.809840 [Gating] SW mode calibration
4037 19:29:41.817032 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4038 19:29:41.819677 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4039 19:29:41.826661 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4040 19:29:41.830468 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4041 19:29:41.833652 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4042 19:29:41.839636 0 9 12 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
4043 19:29:41.842967 0 9 16 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
4044 19:29:41.846549 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4045 19:29:41.853454 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4046 19:29:41.856705 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4047 19:29:41.859843 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4048 19:29:41.866749 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4049 19:29:41.869759 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4050 19:29:41.873233 0 10 12 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
4051 19:29:41.879706 0 10 16 | B1->B0 | 3535 4646 | 1 0 | (0 0) (0 0)
4052 19:29:41.883233 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4053 19:29:41.886513 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4054 19:29:41.893269 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4055 19:29:41.895927 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4056 19:29:41.899942 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4057 19:29:41.903032 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4058 19:29:41.909260 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4059 19:29:41.913117 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4060 19:29:41.916510 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 19:29:41.922922 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 19:29:41.926607 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 19:29:41.929779 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 19:29:41.936708 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 19:29:41.939670 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 19:29:41.942808 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 19:29:41.949874 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 19:29:41.952939 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 19:29:41.956774 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 19:29:41.963112 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 19:29:41.966246 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 19:29:41.969464 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 19:29:41.976219 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 19:29:41.979219 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4075 19:29:41.982544 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4076 19:29:41.985905 Total UI for P1: 0, mck2ui 16
4077 19:29:41.989272 best dqsien dly found for B0: ( 0, 13, 12)
4078 19:29:41.995745 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4079 19:29:41.996300 Total UI for P1: 0, mck2ui 16
4080 19:29:41.999393 best dqsien dly found for B1: ( 0, 13, 16)
4081 19:29:42.005784 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4082 19:29:42.009885 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4083 19:29:42.010488
4084 19:29:42.012735 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4085 19:29:42.015788 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4086 19:29:42.019365 [Gating] SW calibration Done
4087 19:29:42.019832 ==
4088 19:29:42.022637 Dram Type= 6, Freq= 0, CH_0, rank 0
4089 19:29:42.026401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4090 19:29:42.026972 ==
4091 19:29:42.029560 RX Vref Scan: 0
4092 19:29:42.030027
4093 19:29:42.030446 RX Vref 0 -> 0, step: 1
4094 19:29:42.030803
4095 19:29:42.033015 RX Delay -230 -> 252, step: 16
4096 19:29:42.035849 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4097 19:29:42.042608 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4098 19:29:42.045808 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4099 19:29:42.049093 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4100 19:29:42.053251 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4101 19:29:42.059272 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4102 19:29:42.062824 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4103 19:29:42.065874 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4104 19:29:42.069817 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4105 19:29:42.072947 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4106 19:29:42.079122 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4107 19:29:42.082908 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4108 19:29:42.086148 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4109 19:29:42.089434 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4110 19:29:42.095986 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4111 19:29:42.098903 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4112 19:29:42.099377 ==
4113 19:29:42.102770 Dram Type= 6, Freq= 0, CH_0, rank 0
4114 19:29:42.105500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4115 19:29:42.106061 ==
4116 19:29:42.109067 DQS Delay:
4117 19:29:42.109626 DQS0 = 0, DQS1 = 0
4118 19:29:42.110004 DQM Delay:
4119 19:29:42.112256 DQM0 = 52, DQM1 = 45
4120 19:29:42.112724 DQ Delay:
4121 19:29:42.115698 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4122 19:29:42.118936 DQ4 =49, DQ5 =41, DQ6 =65, DQ7 =57
4123 19:29:42.122190 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4124 19:29:42.125764 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4125 19:29:42.126236
4126 19:29:42.126640
4127 19:29:42.126984 ==
4128 19:29:42.128737 Dram Type= 6, Freq= 0, CH_0, rank 0
4129 19:29:42.135653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4130 19:29:42.136125 ==
4131 19:29:42.136494
4132 19:29:42.136841
4133 19:29:42.137174 TX Vref Scan disable
4134 19:29:42.138853 == TX Byte 0 ==
4135 19:29:42.142242 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4136 19:29:42.148879 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4137 19:29:42.149391 == TX Byte 1 ==
4138 19:29:42.152446 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4139 19:29:42.158973 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4140 19:29:42.159400 ==
4141 19:29:42.162386 Dram Type= 6, Freq= 0, CH_0, rank 0
4142 19:29:42.166223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4143 19:29:42.166789 ==
4144 19:29:42.167133
4145 19:29:42.167447
4146 19:29:42.169316 TX Vref Scan disable
4147 19:29:42.172159 == TX Byte 0 ==
4148 19:29:42.175684 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4149 19:29:42.179273 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4150 19:29:42.182495 == TX Byte 1 ==
4151 19:29:42.185803 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4152 19:29:42.188636 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4153 19:29:42.189063
4154 19:29:42.189398 [DATLAT]
4155 19:29:42.192667 Freq=600, CH0 RK0
4156 19:29:42.193192
4157 19:29:42.193530 DATLAT Default: 0x9
4158 19:29:42.195464 0, 0xFFFF, sum = 0
4159 19:29:42.199017 1, 0xFFFF, sum = 0
4160 19:29:42.199446 2, 0xFFFF, sum = 0
4161 19:29:42.202248 3, 0xFFFF, sum = 0
4162 19:29:42.202803 4, 0xFFFF, sum = 0
4163 19:29:42.205338 5, 0xFFFF, sum = 0
4164 19:29:42.205767 6, 0xFFFF, sum = 0
4165 19:29:42.209248 7, 0xFFFF, sum = 0
4166 19:29:42.209798 8, 0x0, sum = 1
4167 19:29:42.212098 9, 0x0, sum = 2
4168 19:29:42.212532 10, 0x0, sum = 3
4169 19:29:42.212875 11, 0x0, sum = 4
4170 19:29:42.215129 best_step = 9
4171 19:29:42.215551
4172 19:29:42.215889 ==
4173 19:29:42.218929 Dram Type= 6, Freq= 0, CH_0, rank 0
4174 19:29:42.222204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4175 19:29:42.222702 ==
4176 19:29:42.225566 RX Vref Scan: 1
4177 19:29:42.226082
4178 19:29:42.226458 RX Vref 0 -> 0, step: 1
4179 19:29:42.229244
4180 19:29:42.229763 RX Delay -163 -> 252, step: 8
4181 19:29:42.230107
4182 19:29:42.232223 Set Vref, RX VrefLevel [Byte0]: 58
4183 19:29:42.235314 [Byte1]: 45
4184 19:29:42.239650
4185 19:29:42.240165 Final RX Vref Byte 0 = 58 to rank0
4186 19:29:42.242956 Final RX Vref Byte 1 = 45 to rank0
4187 19:29:42.245986 Final RX Vref Byte 0 = 58 to rank1
4188 19:29:42.249276 Final RX Vref Byte 1 = 45 to rank1==
4189 19:29:42.252727 Dram Type= 6, Freq= 0, CH_0, rank 0
4190 19:29:42.259099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4191 19:29:42.259607 ==
4192 19:29:42.259949 DQS Delay:
4193 19:29:42.260267 DQS0 = 0, DQS1 = 0
4194 19:29:42.262868 DQM Delay:
4195 19:29:42.263293 DQM0 = 52, DQM1 = 47
4196 19:29:42.266473 DQ Delay:
4197 19:29:42.269146 DQ0 =52, DQ1 =52, DQ2 =48, DQ3 =48
4198 19:29:42.272414 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =60
4199 19:29:42.272839 DQ8 =36, DQ9 =40, DQ10 =48, DQ11 =40
4200 19:29:42.279188 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =56
4201 19:29:42.279691
4202 19:29:42.280034
4203 19:29:42.286103 [DQSOSCAuto] RK0, (LSB)MR18= 0x7063, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 388 ps
4204 19:29:42.289286 CH0 RK0: MR19=808, MR18=7063
4205 19:29:42.296439 CH0_RK0: MR19=0x808, MR18=0x7063, DQSOSC=388, MR23=63, INC=174, DEC=116
4206 19:29:42.297006
4207 19:29:42.299602 ----->DramcWriteLeveling(PI) begin...
4208 19:29:42.300168 ==
4209 19:29:42.302578 Dram Type= 6, Freq= 0, CH_0, rank 1
4210 19:29:42.306517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4211 19:29:42.307095 ==
4212 19:29:42.309175 Write leveling (Byte 0): 35 => 35
4213 19:29:42.312884 Write leveling (Byte 1): 31 => 31
4214 19:29:42.315887 DramcWriteLeveling(PI) end<-----
4215 19:29:42.316402
4216 19:29:42.316781 ==
4217 19:29:42.319277 Dram Type= 6, Freq= 0, CH_0, rank 1
4218 19:29:42.322408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4219 19:29:42.322884 ==
4220 19:29:42.325831 [Gating] SW mode calibration
4221 19:29:42.332798 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4222 19:29:42.339257 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4223 19:29:42.342600 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4224 19:29:42.348935 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4225 19:29:42.352509 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4226 19:29:42.355669 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4227 19:29:42.359715 0 9 16 | B1->B0 | 2a2a 2525 | 0 0 | (1 1) (0 0)
4228 19:29:42.365858 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4229 19:29:42.369001 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4230 19:29:42.372139 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4231 19:29:42.379135 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4232 19:29:42.382456 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4233 19:29:42.386110 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4234 19:29:42.392158 0 10 12 | B1->B0 | 2727 2b2b | 0 1 | (0 0) (0 0)
4235 19:29:42.395851 0 10 16 | B1->B0 | 3f3f 4040 | 0 0 | (0 0) (0 0)
4236 19:29:42.398507 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4237 19:29:42.405538 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4238 19:29:42.408783 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4239 19:29:42.412172 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4240 19:29:42.418853 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4241 19:29:42.421933 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4242 19:29:42.425421 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4243 19:29:42.431967 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4244 19:29:42.435103 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 19:29:42.438846 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 19:29:42.445370 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 19:29:42.448711 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 19:29:42.452066 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 19:29:42.458543 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 19:29:42.461788 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 19:29:42.465511 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 19:29:42.472187 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 19:29:42.474739 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 19:29:42.478371 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 19:29:42.485471 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 19:29:42.488439 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 19:29:42.491441 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 19:29:42.498364 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4259 19:29:42.501887 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4260 19:29:42.505516 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4261 19:29:42.508428 Total UI for P1: 0, mck2ui 16
4262 19:29:42.511635 best dqsien dly found for B0: ( 0, 13, 14)
4263 19:29:42.514725 Total UI for P1: 0, mck2ui 16
4264 19:29:42.518365 best dqsien dly found for B1: ( 0, 13, 16)
4265 19:29:42.521710 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4266 19:29:42.524937 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4267 19:29:42.525516
4268 19:29:42.531005 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4269 19:29:42.534337 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4270 19:29:42.534804 [Gating] SW calibration Done
4271 19:29:42.538015 ==
4272 19:29:42.541177 Dram Type= 6, Freq= 0, CH_0, rank 1
4273 19:29:42.544353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4274 19:29:42.544815 ==
4275 19:29:42.545181 RX Vref Scan: 0
4276 19:29:42.545519
4277 19:29:42.547636 RX Vref 0 -> 0, step: 1
4278 19:29:42.548156
4279 19:29:42.551095 RX Delay -230 -> 252, step: 16
4280 19:29:42.554038 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4281 19:29:42.558116 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4282 19:29:42.564659 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4283 19:29:42.568167 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4284 19:29:42.571319 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4285 19:29:42.574290 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4286 19:29:42.577519 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4287 19:29:42.584533 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4288 19:29:42.587552 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4289 19:29:42.590841 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4290 19:29:42.594479 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4291 19:29:42.601126 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4292 19:29:42.604268 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4293 19:29:42.607644 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4294 19:29:42.611168 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4295 19:29:42.617810 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4296 19:29:42.618430 ==
4297 19:29:42.620683 Dram Type= 6, Freq= 0, CH_0, rank 1
4298 19:29:42.624201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4299 19:29:42.624679 ==
4300 19:29:42.625009 DQS Delay:
4301 19:29:42.627285 DQS0 = 0, DQS1 = 0
4302 19:29:42.627751 DQM Delay:
4303 19:29:42.630746 DQM0 = 50, DQM1 = 43
4304 19:29:42.631422 DQ Delay:
4305 19:29:42.634068 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4306 19:29:42.637455 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4307 19:29:42.640986 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =33
4308 19:29:42.644401 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4309 19:29:42.644873
4310 19:29:42.645239
4311 19:29:42.645578 ==
4312 19:29:42.647148 Dram Type= 6, Freq= 0, CH_0, rank 1
4313 19:29:42.650607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4314 19:29:42.654012 ==
4315 19:29:42.654522
4316 19:29:42.654897
4317 19:29:42.655244 TX Vref Scan disable
4318 19:29:42.657494 == TX Byte 0 ==
4319 19:29:42.660277 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4320 19:29:42.663399 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4321 19:29:42.666919 == TX Byte 1 ==
4322 19:29:42.670390 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4323 19:29:42.676888 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4324 19:29:42.677411 ==
4325 19:29:42.680577 Dram Type= 6, Freq= 0, CH_0, rank 1
4326 19:29:42.683907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4327 19:29:42.684429 ==
4328 19:29:42.684768
4329 19:29:42.685082
4330 19:29:42.686794 TX Vref Scan disable
4331 19:29:42.690231 == TX Byte 0 ==
4332 19:29:42.693212 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4333 19:29:42.696820 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4334 19:29:42.700307 == TX Byte 1 ==
4335 19:29:42.704115 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4336 19:29:42.707229 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4337 19:29:42.707756
4338 19:29:42.708097 [DATLAT]
4339 19:29:42.710063 Freq=600, CH0 RK1
4340 19:29:42.710625
4341 19:29:42.710959 DATLAT Default: 0x9
4342 19:29:42.713211 0, 0xFFFF, sum = 0
4343 19:29:42.716625 1, 0xFFFF, sum = 0
4344 19:29:42.717148 2, 0xFFFF, sum = 0
4345 19:29:42.720043 3, 0xFFFF, sum = 0
4346 19:29:42.720509 4, 0xFFFF, sum = 0
4347 19:29:42.723522 5, 0xFFFF, sum = 0
4348 19:29:42.724048 6, 0xFFFF, sum = 0
4349 19:29:42.726534 7, 0xFFFF, sum = 0
4350 19:29:42.727051 8, 0x0, sum = 1
4351 19:29:42.730515 9, 0x0, sum = 2
4352 19:29:42.731080 10, 0x0, sum = 3
4353 19:29:42.731451 11, 0x0, sum = 4
4354 19:29:42.733334 best_step = 9
4355 19:29:42.733890
4356 19:29:42.734262 ==
4357 19:29:42.736945 Dram Type= 6, Freq= 0, CH_0, rank 1
4358 19:29:42.740408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4359 19:29:42.741045 ==
4360 19:29:42.743575 RX Vref Scan: 0
4361 19:29:42.744038
4362 19:29:42.744404 RX Vref 0 -> 0, step: 1
4363 19:29:42.744744
4364 19:29:42.746285 RX Delay -163 -> 252, step: 8
4365 19:29:42.753761 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4366 19:29:42.757515 iDelay=205, Bit 1, Center 52 (-91 ~ 196) 288
4367 19:29:42.760462 iDelay=205, Bit 2, Center 52 (-91 ~ 196) 288
4368 19:29:42.764089 iDelay=205, Bit 3, Center 52 (-91 ~ 196) 288
4369 19:29:42.767435 iDelay=205, Bit 4, Center 56 (-83 ~ 196) 280
4370 19:29:42.774074 iDelay=205, Bit 5, Center 44 (-99 ~ 188) 288
4371 19:29:42.777480 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4372 19:29:42.780441 iDelay=205, Bit 7, Center 60 (-83 ~ 204) 288
4373 19:29:42.784099 iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288
4374 19:29:42.787128 iDelay=205, Bit 9, Center 32 (-107 ~ 172) 280
4375 19:29:42.794275 iDelay=205, Bit 10, Center 48 (-91 ~ 188) 280
4376 19:29:42.797389 iDelay=205, Bit 11, Center 40 (-99 ~ 180) 280
4377 19:29:42.800191 iDelay=205, Bit 12, Center 52 (-83 ~ 188) 272
4378 19:29:42.803940 iDelay=205, Bit 13, Center 48 (-91 ~ 188) 280
4379 19:29:42.810257 iDelay=205, Bit 14, Center 56 (-83 ~ 196) 280
4380 19:29:42.814166 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4381 19:29:42.814928 ==
4382 19:29:42.817298 Dram Type= 6, Freq= 0, CH_0, rank 1
4383 19:29:42.820296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4384 19:29:42.820808 ==
4385 19:29:42.824214 DQS Delay:
4386 19:29:42.824780 DQS0 = 0, DQS1 = 0
4387 19:29:42.825144 DQM Delay:
4388 19:29:42.827172 DQM0 = 53, DQM1 = 45
4389 19:29:42.827642 DQ Delay:
4390 19:29:42.830231 DQ0 =52, DQ1 =52, DQ2 =52, DQ3 =52
4391 19:29:42.833914 DQ4 =56, DQ5 =44, DQ6 =56, DQ7 =60
4392 19:29:42.837310 DQ8 =36, DQ9 =32, DQ10 =48, DQ11 =40
4393 19:29:42.840376 DQ12 =52, DQ13 =48, DQ14 =56, DQ15 =52
4394 19:29:42.840939
4395 19:29:42.841305
4396 19:29:42.850171 [DQSOSCAuto] RK1, (LSB)MR18= 0x6426, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 391 ps
4397 19:29:42.850768 CH0 RK1: MR19=808, MR18=6426
4398 19:29:42.856904 CH0_RK1: MR19=0x808, MR18=0x6426, DQSOSC=391, MR23=63, INC=171, DEC=114
4399 19:29:42.860626 [RxdqsGatingPostProcess] freq 600
4400 19:29:42.867074 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4401 19:29:42.870180 Pre-setting of DQS Precalculation
4402 19:29:42.873448 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4403 19:29:42.874030 ==
4404 19:29:42.876553 Dram Type= 6, Freq= 0, CH_1, rank 0
4405 19:29:42.883241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4406 19:29:42.883794 ==
4407 19:29:42.886739 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4408 19:29:42.893126 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4409 19:29:42.896617 [CA 0] Center 35 (5~66) winsize 62
4410 19:29:42.899655 [CA 1] Center 36 (5~67) winsize 63
4411 19:29:42.902884 [CA 2] Center 34 (4~65) winsize 62
4412 19:29:42.906390 [CA 3] Center 34 (4~65) winsize 62
4413 19:29:42.909449 [CA 4] Center 34 (4~65) winsize 62
4414 19:29:42.913394 [CA 5] Center 34 (4~64) winsize 61
4415 19:29:42.913961
4416 19:29:42.916142 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4417 19:29:42.916604
4418 19:29:42.919584 [CATrainingPosCal] consider 1 rank data
4419 19:29:42.922686 u2DelayCellTimex100 = 270/100 ps
4420 19:29:42.926787 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4421 19:29:42.929877 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4422 19:29:42.936225 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4423 19:29:42.939930 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4424 19:29:42.942950 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4425 19:29:42.946061 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4426 19:29:42.946620
4427 19:29:42.949758 CA PerBit enable=1, Macro0, CA PI delay=34
4428 19:29:42.950226
4429 19:29:42.953091 [CBTSetCACLKResult] CA Dly = 34
4430 19:29:42.953555 CS Dly: 5 (0~36)
4431 19:29:42.956406 ==
4432 19:29:42.956888 Dram Type= 6, Freq= 0, CH_1, rank 1
4433 19:29:42.963377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4434 19:29:42.963938 ==
4435 19:29:42.966038 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4436 19:29:42.972980 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4437 19:29:42.976619 [CA 0] Center 36 (6~67) winsize 62
4438 19:29:42.979424 [CA 1] Center 36 (5~67) winsize 63
4439 19:29:42.983211 [CA 2] Center 34 (4~65) winsize 62
4440 19:29:42.986749 [CA 3] Center 34 (4~65) winsize 62
4441 19:29:42.989391 [CA 4] Center 35 (4~66) winsize 63
4442 19:29:42.993328 [CA 5] Center 34 (4~65) winsize 62
4443 19:29:42.993795
4444 19:29:42.996109 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4445 19:29:42.996575
4446 19:29:42.999386 [CATrainingPosCal] consider 2 rank data
4447 19:29:43.003248 u2DelayCellTimex100 = 270/100 ps
4448 19:29:43.006018 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4449 19:29:43.012929 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4450 19:29:43.016089 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4451 19:29:43.019527 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4452 19:29:43.022621 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4453 19:29:43.026206 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4454 19:29:43.026718
4455 19:29:43.029758 CA PerBit enable=1, Macro0, CA PI delay=34
4456 19:29:43.030355
4457 19:29:43.033034 [CBTSetCACLKResult] CA Dly = 34
4458 19:29:43.033593 CS Dly: 6 (0~38)
4459 19:29:43.036085
4460 19:29:43.039523 ----->DramcWriteLeveling(PI) begin...
4461 19:29:43.040022 ==
4462 19:29:43.043022 Dram Type= 6, Freq= 0, CH_1, rank 0
4463 19:29:43.045829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4464 19:29:43.046253 ==
4465 19:29:43.049019 Write leveling (Byte 0): 30 => 30
4466 19:29:43.052875 Write leveling (Byte 1): 31 => 31
4467 19:29:43.056049 DramcWriteLeveling(PI) end<-----
4468 19:29:43.056474
4469 19:29:43.056808 ==
4470 19:29:43.059260 Dram Type= 6, Freq= 0, CH_1, rank 0
4471 19:29:43.062763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4472 19:29:43.063303 ==
4473 19:29:43.066575 [Gating] SW mode calibration
4474 19:29:43.073253 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4475 19:29:43.079774 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4476 19:29:43.082637 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4477 19:29:43.086290 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4478 19:29:43.092459 0 9 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
4479 19:29:43.095797 0 9 12 | B1->B0 | 2f2f 2a2a | 0 1 | (0 0) (1 0)
4480 19:29:43.099091 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
4481 19:29:43.105957 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4482 19:29:43.108824 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4483 19:29:43.112278 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4484 19:29:43.118810 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4485 19:29:43.122123 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4486 19:29:43.125739 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4487 19:29:43.131885 0 10 12 | B1->B0 | 3333 3838 | 1 0 | (0 0) (0 0)
4488 19:29:43.135502 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4489 19:29:43.138292 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4490 19:29:43.144967 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4491 19:29:43.148866 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4492 19:29:43.151615 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4493 19:29:43.158193 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4494 19:29:43.161468 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4495 19:29:43.165364 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4496 19:29:43.171782 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 19:29:43.175104 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 19:29:43.178157 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 19:29:43.181852 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 19:29:43.188281 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 19:29:43.191399 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 19:29:43.195192 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 19:29:43.201992 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 19:29:43.204920 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 19:29:43.208030 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 19:29:43.215091 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 19:29:43.218222 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 19:29:43.221235 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 19:29:43.228297 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 19:29:43.231566 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4511 19:29:43.234415 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4512 19:29:43.238223 Total UI for P1: 0, mck2ui 16
4513 19:29:43.241469 best dqsien dly found for B0: ( 0, 13, 8)
4514 19:29:43.248083 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4515 19:29:43.248595 Total UI for P1: 0, mck2ui 16
4516 19:29:43.254273 best dqsien dly found for B1: ( 0, 13, 10)
4517 19:29:43.257776 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4518 19:29:43.261218 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4519 19:29:43.261646
4520 19:29:43.264730 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4521 19:29:43.267941 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4522 19:29:43.271218 [Gating] SW calibration Done
4523 19:29:43.271653 ==
4524 19:29:43.274714 Dram Type= 6, Freq= 0, CH_1, rank 0
4525 19:29:43.277562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4526 19:29:43.278085 ==
4527 19:29:43.281459 RX Vref Scan: 0
4528 19:29:43.281977
4529 19:29:43.282364 RX Vref 0 -> 0, step: 1
4530 19:29:43.282740
4531 19:29:43.284067 RX Delay -230 -> 252, step: 16
4532 19:29:43.291226 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4533 19:29:43.294372 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4534 19:29:43.298000 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4535 19:29:43.301276 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4536 19:29:43.304402 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4537 19:29:43.311462 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4538 19:29:43.314819 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4539 19:29:43.317785 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4540 19:29:43.321287 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4541 19:29:43.327507 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4542 19:29:43.331229 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4543 19:29:43.334260 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4544 19:29:43.337809 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4545 19:29:43.343799 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4546 19:29:43.347638 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4547 19:29:43.350515 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4548 19:29:43.350942 ==
4549 19:29:43.354182 Dram Type= 6, Freq= 0, CH_1, rank 0
4550 19:29:43.357486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4551 19:29:43.358010 ==
4552 19:29:43.361423 DQS Delay:
4553 19:29:43.362147 DQS0 = 0, DQS1 = 0
4554 19:29:43.364463 DQM Delay:
4555 19:29:43.364887 DQM0 = 47, DQM1 = 46
4556 19:29:43.365224 DQ Delay:
4557 19:29:43.367881 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =41
4558 19:29:43.370824 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4559 19:29:43.373766 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4560 19:29:43.377139 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4561 19:29:43.377564
4562 19:29:43.377900
4563 19:29:43.380544 ==
4564 19:29:43.384452 Dram Type= 6, Freq= 0, CH_1, rank 0
4565 19:29:43.387161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4566 19:29:43.387596 ==
4567 19:29:43.387932
4568 19:29:43.388245
4569 19:29:43.390748 TX Vref Scan disable
4570 19:29:43.391190 == TX Byte 0 ==
4571 19:29:43.397679 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4572 19:29:43.400411 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4573 19:29:43.400844 == TX Byte 1 ==
4574 19:29:43.407452 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4575 19:29:43.410697 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4576 19:29:43.411222 ==
4577 19:29:43.413859 Dram Type= 6, Freq= 0, CH_1, rank 0
4578 19:29:43.416796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4579 19:29:43.417225 ==
4580 19:29:43.417561
4581 19:29:43.417868
4582 19:29:43.420583 TX Vref Scan disable
4583 19:29:43.423558 == TX Byte 0 ==
4584 19:29:43.426901 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4585 19:29:43.430084 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4586 19:29:43.433842 == TX Byte 1 ==
4587 19:29:43.436841 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4588 19:29:43.439867 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4589 19:29:43.440296
4590 19:29:43.443645 [DATLAT]
4591 19:29:43.444068 Freq=600, CH1 RK0
4592 19:29:43.444409
4593 19:29:43.446790 DATLAT Default: 0x9
4594 19:29:43.447309 0, 0xFFFF, sum = 0
4595 19:29:43.450104 1, 0xFFFF, sum = 0
4596 19:29:43.450555 2, 0xFFFF, sum = 0
4597 19:29:43.453260 3, 0xFFFF, sum = 0
4598 19:29:43.453694 4, 0xFFFF, sum = 0
4599 19:29:43.456854 5, 0xFFFF, sum = 0
4600 19:29:43.457329 6, 0xFFFF, sum = 0
4601 19:29:43.460294 7, 0xFFFF, sum = 0
4602 19:29:43.460914 8, 0x0, sum = 1
4603 19:29:43.463353 9, 0x0, sum = 2
4604 19:29:43.463829 10, 0x0, sum = 3
4605 19:29:43.466871 11, 0x0, sum = 4
4606 19:29:43.467349 best_step = 9
4607 19:29:43.467718
4608 19:29:43.468060 ==
4609 19:29:43.470398 Dram Type= 6, Freq= 0, CH_1, rank 0
4610 19:29:43.473940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4611 19:29:43.476787 ==
4612 19:29:43.477395 RX Vref Scan: 1
4613 19:29:43.477778
4614 19:29:43.480089 RX Vref 0 -> 0, step: 1
4615 19:29:43.480558
4616 19:29:43.483202 RX Delay -163 -> 252, step: 8
4617 19:29:43.483711
4618 19:29:43.486968 Set Vref, RX VrefLevel [Byte0]: 52
4619 19:29:43.490121 [Byte1]: 47
4620 19:29:43.490751
4621 19:29:43.493554 Final RX Vref Byte 0 = 52 to rank0
4622 19:29:43.496987 Final RX Vref Byte 1 = 47 to rank0
4623 19:29:43.499892 Final RX Vref Byte 0 = 52 to rank1
4624 19:29:43.503336 Final RX Vref Byte 1 = 47 to rank1==
4625 19:29:43.506447 Dram Type= 6, Freq= 0, CH_1, rank 0
4626 19:29:43.509895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4627 19:29:43.510411 ==
4628 19:29:43.513153 DQS Delay:
4629 19:29:43.513727 DQS0 = 0, DQS1 = 0
4630 19:29:43.514218 DQM Delay:
4631 19:29:43.516456 DQM0 = 48, DQM1 = 44
4632 19:29:43.516924 DQ Delay:
4633 19:29:43.520240 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =44
4634 19:29:43.523415 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4635 19:29:43.526688 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4636 19:29:43.529963 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4637 19:29:43.530570
4638 19:29:43.530950
4639 19:29:43.540039 [DQSOSCAuto] RK0, (LSB)MR18= 0x4a70, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4640 19:29:43.540616 CH1 RK0: MR19=808, MR18=4A70
4641 19:29:43.546916 CH1_RK0: MR19=0x808, MR18=0x4A70, DQSOSC=388, MR23=63, INC=174, DEC=116
4642 19:29:43.547482
4643 19:29:43.550089 ----->DramcWriteLeveling(PI) begin...
4644 19:29:43.550676 ==
4645 19:29:43.553106 Dram Type= 6, Freq= 0, CH_1, rank 1
4646 19:29:43.560301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4647 19:29:43.560911 ==
4648 19:29:43.563183 Write leveling (Byte 0): 30 => 30
4649 19:29:43.566469 Write leveling (Byte 1): 32 => 32
4650 19:29:43.567030 DramcWriteLeveling(PI) end<-----
4651 19:29:43.569660
4652 19:29:43.570213 ==
4653 19:29:43.573466 Dram Type= 6, Freq= 0, CH_1, rank 1
4654 19:29:43.576508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4655 19:29:43.576980 ==
4656 19:29:43.579817 [Gating] SW mode calibration
4657 19:29:43.586572 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4658 19:29:43.590025 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4659 19:29:43.596080 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4660 19:29:43.599594 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4661 19:29:43.603237 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4662 19:29:43.609812 0 9 12 | B1->B0 | 2e2e 2f2f | 0 0 | (0 0) (0 0)
4663 19:29:43.612805 0 9 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4664 19:29:43.616129 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4665 19:29:43.623130 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4666 19:29:43.626064 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4667 19:29:43.629342 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4668 19:29:43.636024 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4669 19:29:43.639814 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4670 19:29:43.642718 0 10 12 | B1->B0 | 4040 3434 | 0 0 | (0 0) (0 0)
4671 19:29:43.649912 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4672 19:29:43.653038 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4673 19:29:43.655929 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4674 19:29:43.662502 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4675 19:29:43.666405 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4676 19:29:43.669534 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4677 19:29:43.675904 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4678 19:29:43.679725 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 19:29:43.682450 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 19:29:43.689390 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 19:29:43.692809 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 19:29:43.695570 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 19:29:43.699098 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 19:29:43.705906 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 19:29:43.709372 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 19:29:43.712451 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 19:29:43.718930 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 19:29:43.722184 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 19:29:43.725362 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 19:29:43.732596 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 19:29:43.736328 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 19:29:43.739311 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 19:29:43.745702 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4694 19:29:43.749317 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4695 19:29:43.752875 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4696 19:29:43.756046 Total UI for P1: 0, mck2ui 16
4697 19:29:43.759300 best dqsien dly found for B0: ( 0, 13, 10)
4698 19:29:43.762477 Total UI for P1: 0, mck2ui 16
4699 19:29:43.766413 best dqsien dly found for B1: ( 0, 13, 10)
4700 19:29:43.769041 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4701 19:29:43.772669 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4702 19:29:43.773235
4703 19:29:43.778750 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4704 19:29:43.782522 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4705 19:29:43.785931 [Gating] SW calibration Done
4706 19:29:43.786570 ==
4707 19:29:43.788993 Dram Type= 6, Freq= 0, CH_1, rank 1
4708 19:29:43.792436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4709 19:29:43.792910 ==
4710 19:29:43.793281 RX Vref Scan: 0
4711 19:29:43.793623
4712 19:29:43.795639 RX Vref 0 -> 0, step: 1
4713 19:29:43.796106
4714 19:29:43.798897 RX Delay -230 -> 252, step: 16
4715 19:29:43.802613 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4716 19:29:43.805601 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4717 19:29:43.812303 iDelay=218, Bit 2, Center 41 (-102 ~ 185) 288
4718 19:29:43.815982 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4719 19:29:43.818916 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4720 19:29:43.822598 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4721 19:29:43.825313 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4722 19:29:43.832232 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4723 19:29:43.835844 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4724 19:29:43.839032 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4725 19:29:43.842117 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4726 19:29:43.849131 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4727 19:29:43.852106 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4728 19:29:43.855275 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4729 19:29:43.859184 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4730 19:29:43.865336 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4731 19:29:43.865800 ==
4732 19:29:43.868981 Dram Type= 6, Freq= 0, CH_1, rank 1
4733 19:29:43.872560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4734 19:29:43.873119 ==
4735 19:29:43.873494 DQS Delay:
4736 19:29:43.875688 DQS0 = 0, DQS1 = 0
4737 19:29:43.876249 DQM Delay:
4738 19:29:43.878763 DQM0 = 52, DQM1 = 46
4739 19:29:43.879236 DQ Delay:
4740 19:29:43.882177 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4741 19:29:43.885961 DQ4 =49, DQ5 =65, DQ6 =65, DQ7 =49
4742 19:29:43.888724 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4743 19:29:43.892032 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4744 19:29:43.892502
4745 19:29:43.892873
4746 19:29:43.893216 ==
4747 19:29:43.895274 Dram Type= 6, Freq= 0, CH_1, rank 1
4748 19:29:43.898488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4749 19:29:43.899017 ==
4750 19:29:43.899493
4751 19:29:43.899937
4752 19:29:43.902296 TX Vref Scan disable
4753 19:29:43.905586 == TX Byte 0 ==
4754 19:29:43.909082 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4755 19:29:43.912090 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4756 19:29:43.915058 == TX Byte 1 ==
4757 19:29:43.918634 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4758 19:29:43.921822 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4759 19:29:43.922334 ==
4760 19:29:43.925506 Dram Type= 6, Freq= 0, CH_1, rank 1
4761 19:29:43.931693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4762 19:29:43.932167 ==
4763 19:29:43.932538
4764 19:29:43.932877
4765 19:29:43.933207 TX Vref Scan disable
4766 19:29:43.936430 == TX Byte 0 ==
4767 19:29:43.939555 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4768 19:29:43.942827 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4769 19:29:43.945996 == TX Byte 1 ==
4770 19:29:43.949577 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4771 19:29:43.956388 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4772 19:29:43.956833
4773 19:29:43.957170 [DATLAT]
4774 19:29:43.957483 Freq=600, CH1 RK1
4775 19:29:43.957788
4776 19:29:43.959568 DATLAT Default: 0x9
4777 19:29:43.959992 0, 0xFFFF, sum = 0
4778 19:29:43.962840 1, 0xFFFF, sum = 0
4779 19:29:43.966459 2, 0xFFFF, sum = 0
4780 19:29:43.966982 3, 0xFFFF, sum = 0
4781 19:29:43.969360 4, 0xFFFF, sum = 0
4782 19:29:43.969790 5, 0xFFFF, sum = 0
4783 19:29:43.973232 6, 0xFFFF, sum = 0
4784 19:29:43.973763 7, 0xFFFF, sum = 0
4785 19:29:43.976045 8, 0x0, sum = 1
4786 19:29:43.976585 9, 0x0, sum = 2
4787 19:29:43.976990 10, 0x0, sum = 3
4788 19:29:43.979042 11, 0x0, sum = 4
4789 19:29:43.979472 best_step = 9
4790 19:29:43.979811
4791 19:29:43.980122 ==
4792 19:29:43.983272 Dram Type= 6, Freq= 0, CH_1, rank 1
4793 19:29:43.989591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4794 19:29:43.990121 ==
4795 19:29:43.990505 RX Vref Scan: 0
4796 19:29:43.990830
4797 19:29:43.992750 RX Vref 0 -> 0, step: 1
4798 19:29:43.993174
4799 19:29:43.996245 RX Delay -163 -> 252, step: 8
4800 19:29:43.999027 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4801 19:29:44.005960 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4802 19:29:44.009490 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4803 19:29:44.012826 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4804 19:29:44.015783 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4805 19:29:44.018724 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4806 19:29:44.025683 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4807 19:29:44.029439 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4808 19:29:44.032825 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4809 19:29:44.035691 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4810 19:29:44.039249 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4811 19:29:44.045819 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4812 19:29:44.049218 iDelay=205, Bit 12, Center 56 (-91 ~ 204) 296
4813 19:29:44.052416 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4814 19:29:44.055698 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4815 19:29:44.062450 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4816 19:29:44.062973 ==
4817 19:29:44.065294 Dram Type= 6, Freq= 0, CH_1, rank 1
4818 19:29:44.069142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4819 19:29:44.069574 ==
4820 19:29:44.069910 DQS Delay:
4821 19:29:44.072561 DQS0 = 0, DQS1 = 0
4822 19:29:44.073081 DQM Delay:
4823 19:29:44.075450 DQM0 = 49, DQM1 = 44
4824 19:29:44.075875 DQ Delay:
4825 19:29:44.078735 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4826 19:29:44.082400 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =48
4827 19:29:44.085863 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =36
4828 19:29:44.088764 DQ12 =56, DQ13 =52, DQ14 =48, DQ15 =52
4829 19:29:44.089239
4830 19:29:44.089631
4831 19:29:44.095282 [DQSOSCAuto] RK1, (LSB)MR18= 0x661d, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 390 ps
4832 19:29:44.098985 CH1 RK1: MR19=808, MR18=661D
4833 19:29:44.106074 CH1_RK1: MR19=0x808, MR18=0x661D, DQSOSC=390, MR23=63, INC=172, DEC=114
4834 19:29:44.109169 [RxdqsGatingPostProcess] freq 600
4835 19:29:44.115163 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4836 19:29:44.118411 Pre-setting of DQS Precalculation
4837 19:29:44.122453 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4838 19:29:44.128895 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4839 19:29:44.135486 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4840 19:29:44.136005
4841 19:29:44.136383
4842 19:29:44.138358 [Calibration Summary] 1200 Mbps
4843 19:29:44.142161 CH 0, Rank 0
4844 19:29:44.142626 SW Impedance : PASS
4845 19:29:44.145654 DUTY Scan : NO K
4846 19:29:44.148918 ZQ Calibration : PASS
4847 19:29:44.149475 Jitter Meter : NO K
4848 19:29:44.151721 CBT Training : PASS
4849 19:29:44.155611 Write leveling : PASS
4850 19:29:44.156138 RX DQS gating : PASS
4851 19:29:44.158454 RX DQ/DQS(RDDQC) : PASS
4852 19:29:44.158886 TX DQ/DQS : PASS
4853 19:29:44.162059 RX DATLAT : PASS
4854 19:29:44.165305 RX DQ/DQS(Engine): PASS
4855 19:29:44.165826 TX OE : NO K
4856 19:29:44.168451 All Pass.
4857 19:29:44.168995
4858 19:29:44.169345 CH 0, Rank 1
4859 19:29:44.172065 SW Impedance : PASS
4860 19:29:44.172582 DUTY Scan : NO K
4861 19:29:44.175361 ZQ Calibration : PASS
4862 19:29:44.178181 Jitter Meter : NO K
4863 19:29:44.178652 CBT Training : PASS
4864 19:29:44.181494 Write leveling : PASS
4865 19:29:44.185116 RX DQS gating : PASS
4866 19:29:44.185544 RX DQ/DQS(RDDQC) : PASS
4867 19:29:44.188401 TX DQ/DQS : PASS
4868 19:29:44.192317 RX DATLAT : PASS
4869 19:29:44.192858 RX DQ/DQS(Engine): PASS
4870 19:29:44.195183 TX OE : NO K
4871 19:29:44.195623 All Pass.
4872 19:29:44.195962
4873 19:29:44.198353 CH 1, Rank 0
4874 19:29:44.198777 SW Impedance : PASS
4875 19:29:44.201773 DUTY Scan : NO K
4876 19:29:44.205387 ZQ Calibration : PASS
4877 19:29:44.205906 Jitter Meter : NO K
4878 19:29:44.208564 CBT Training : PASS
4879 19:29:44.208988 Write leveling : PASS
4880 19:29:44.211632 RX DQS gating : PASS
4881 19:29:44.215093 RX DQ/DQS(RDDQC) : PASS
4882 19:29:44.215519 TX DQ/DQS : PASS
4883 19:29:44.218557 RX DATLAT : PASS
4884 19:29:44.221951 RX DQ/DQS(Engine): PASS
4885 19:29:44.222514 TX OE : NO K
4886 19:29:44.224801 All Pass.
4887 19:29:44.225241
4888 19:29:44.225582 CH 1, Rank 1
4889 19:29:44.228380 SW Impedance : PASS
4890 19:29:44.228805 DUTY Scan : NO K
4891 19:29:44.231352 ZQ Calibration : PASS
4892 19:29:44.235311 Jitter Meter : NO K
4893 19:29:44.235836 CBT Training : PASS
4894 19:29:44.238347 Write leveling : PASS
4895 19:29:44.241823 RX DQS gating : PASS
4896 19:29:44.242381 RX DQ/DQS(RDDQC) : PASS
4897 19:29:44.244918 TX DQ/DQS : PASS
4898 19:29:44.248184 RX DATLAT : PASS
4899 19:29:44.248708 RX DQ/DQS(Engine): PASS
4900 19:29:44.251714 TX OE : NO K
4901 19:29:44.252140 All Pass.
4902 19:29:44.252474
4903 19:29:44.254796 DramC Write-DBI off
4904 19:29:44.258719 PER_BANK_REFRESH: Hybrid Mode
4905 19:29:44.259148 TX_TRACKING: ON
4906 19:29:44.268877 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4907 19:29:44.271767 [FAST_K] Save calibration result to emmc
4908 19:29:44.274775 dramc_set_vcore_voltage set vcore to 662500
4909 19:29:44.278567 Read voltage for 933, 3
4910 19:29:44.279089 Vio18 = 0
4911 19:29:44.279462 Vcore = 662500
4912 19:29:44.281785 Vdram = 0
4913 19:29:44.282370 Vddq = 0
4914 19:29:44.282729 Vmddr = 0
4915 19:29:44.288136 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4916 19:29:44.291068 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4917 19:29:44.294489 MEM_TYPE=3, freq_sel=17
4918 19:29:44.297679 sv_algorithm_assistance_LP4_1600
4919 19:29:44.301486 ============ PULL DRAM RESETB DOWN ============
4920 19:29:44.304626 ========== PULL DRAM RESETB DOWN end =========
4921 19:29:44.311449 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4922 19:29:44.314629 ===================================
4923 19:29:44.315072 LPDDR4 DRAM CONFIGURATION
4924 19:29:44.317684 ===================================
4925 19:29:44.321196 EX_ROW_EN[0] = 0x0
4926 19:29:44.324619 EX_ROW_EN[1] = 0x0
4927 19:29:44.325053 LP4Y_EN = 0x0
4928 19:29:44.327566 WORK_FSP = 0x0
4929 19:29:44.328055 WL = 0x3
4930 19:29:44.331099 RL = 0x3
4931 19:29:44.331529 BL = 0x2
4932 19:29:44.334860 RPST = 0x0
4933 19:29:44.335297 RD_PRE = 0x0
4934 19:29:44.337521 WR_PRE = 0x1
4935 19:29:44.337874 WR_PST = 0x0
4936 19:29:44.340830 DBI_WR = 0x0
4937 19:29:44.341268 DBI_RD = 0x0
4938 19:29:44.344404 OTF = 0x1
4939 19:29:44.347658 ===================================
4940 19:29:44.351165 ===================================
4941 19:29:44.351587 ANA top config
4942 19:29:44.354141 ===================================
4943 19:29:44.358127 DLL_ASYNC_EN = 0
4944 19:29:44.360960 ALL_SLAVE_EN = 1
4945 19:29:44.363866 NEW_RANK_MODE = 1
4946 19:29:44.364479 DLL_IDLE_MODE = 1
4947 19:29:44.367552 LP45_APHY_COMB_EN = 1
4948 19:29:44.371166 TX_ODT_DIS = 1
4949 19:29:44.374011 NEW_8X_MODE = 1
4950 19:29:44.377550 ===================================
4951 19:29:44.381337 ===================================
4952 19:29:44.381767 data_rate = 1866
4953 19:29:44.384360 CKR = 1
4954 19:29:44.387387 DQ_P2S_RATIO = 8
4955 19:29:44.391021 ===================================
4956 19:29:44.394484 CA_P2S_RATIO = 8
4957 19:29:44.397465 DQ_CA_OPEN = 0
4958 19:29:44.401030 DQ_SEMI_OPEN = 0
4959 19:29:44.401464 CA_SEMI_OPEN = 0
4960 19:29:44.404263 CA_FULL_RATE = 0
4961 19:29:44.407481 DQ_CKDIV4_EN = 1
4962 19:29:44.411385 CA_CKDIV4_EN = 1
4963 19:29:44.414525 CA_PREDIV_EN = 0
4964 19:29:44.417634 PH8_DLY = 0
4965 19:29:44.418203 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4966 19:29:44.420782 DQ_AAMCK_DIV = 4
4967 19:29:44.424223 CA_AAMCK_DIV = 4
4968 19:29:44.427458 CA_ADMCK_DIV = 4
4969 19:29:44.431176 DQ_TRACK_CA_EN = 0
4970 19:29:44.434112 CA_PICK = 933
4971 19:29:44.434621 CA_MCKIO = 933
4972 19:29:44.437609 MCKIO_SEMI = 0
4973 19:29:44.441126 PLL_FREQ = 3732
4974 19:29:44.444574 DQ_UI_PI_RATIO = 32
4975 19:29:44.447547 CA_UI_PI_RATIO = 0
4976 19:29:44.451269 ===================================
4977 19:29:44.454369 ===================================
4978 19:29:44.457577 memory_type:LPDDR4
4979 19:29:44.458014 GP_NUM : 10
4980 19:29:44.461175 SRAM_EN : 1
4981 19:29:44.461596 MD32_EN : 0
4982 19:29:44.464425 ===================================
4983 19:29:44.467506 [ANA_INIT] >>>>>>>>>>>>>>
4984 19:29:44.470852 <<<<<< [CONFIGURE PHASE]: ANA_TX
4985 19:29:44.474210 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4986 19:29:44.477850 ===================================
4987 19:29:44.481236 data_rate = 1866,PCW = 0X8f00
4988 19:29:44.484039 ===================================
4989 19:29:44.487763 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4990 19:29:44.494010 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4991 19:29:44.497115 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4992 19:29:44.504361 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4993 19:29:44.507289 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4994 19:29:44.511059 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4995 19:29:44.511622 [ANA_INIT] flow start
4996 19:29:44.513938 [ANA_INIT] PLL >>>>>>>>
4997 19:29:44.516835 [ANA_INIT] PLL <<<<<<<<
4998 19:29:44.517261 [ANA_INIT] MIDPI >>>>>>>>
4999 19:29:44.520235 [ANA_INIT] MIDPI <<<<<<<<
5000 19:29:44.523570 [ANA_INIT] DLL >>>>>>>>
5001 19:29:44.523992 [ANA_INIT] flow end
5002 19:29:44.530763 ============ LP4 DIFF to SE enter ============
5003 19:29:44.533845 ============ LP4 DIFF to SE exit ============
5004 19:29:44.537603 [ANA_INIT] <<<<<<<<<<<<<
5005 19:29:44.540538 [Flow] Enable top DCM control >>>>>
5006 19:29:44.543753 [Flow] Enable top DCM control <<<<<
5007 19:29:44.544188 Enable DLL master slave shuffle
5008 19:29:44.550450 ==============================================================
5009 19:29:44.553752 Gating Mode config
5010 19:29:44.556726 ==============================================================
5011 19:29:44.560025 Config description:
5012 19:29:44.570585 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5013 19:29:44.576711 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5014 19:29:44.580154 SELPH_MODE 0: By rank 1: By Phase
5015 19:29:44.586619 ==============================================================
5016 19:29:44.590229 GAT_TRACK_EN = 1
5017 19:29:44.593690 RX_GATING_MODE = 2
5018 19:29:44.596680 RX_GATING_TRACK_MODE = 2
5019 19:29:44.600636 SELPH_MODE = 1
5020 19:29:44.601160 PICG_EARLY_EN = 1
5021 19:29:44.603499 VALID_LAT_VALUE = 1
5022 19:29:44.610221 ==============================================================
5023 19:29:44.613398 Enter into Gating configuration >>>>
5024 19:29:44.617275 Exit from Gating configuration <<<<
5025 19:29:44.620356 Enter into DVFS_PRE_config >>>>>
5026 19:29:44.630011 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5027 19:29:44.633523 Exit from DVFS_PRE_config <<<<<
5028 19:29:44.637155 Enter into PICG configuration >>>>
5029 19:29:44.640409 Exit from PICG configuration <<<<
5030 19:29:44.643362 [RX_INPUT] configuration >>>>>
5031 19:29:44.646866 [RX_INPUT] configuration <<<<<
5032 19:29:44.649867 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5033 19:29:44.656568 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5034 19:29:44.663177 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5035 19:29:44.669742 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5036 19:29:44.676152 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5037 19:29:44.680052 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5038 19:29:44.686239 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5039 19:29:44.689615 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5040 19:29:44.692805 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5041 19:29:44.696437 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5042 19:29:44.702529 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5043 19:29:44.706389 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5044 19:29:44.709609 ===================================
5045 19:29:44.712638 LPDDR4 DRAM CONFIGURATION
5046 19:29:44.716232 ===================================
5047 19:29:44.716702 EX_ROW_EN[0] = 0x0
5048 19:29:44.719273 EX_ROW_EN[1] = 0x0
5049 19:29:44.719741 LP4Y_EN = 0x0
5050 19:29:44.722804 WORK_FSP = 0x0
5051 19:29:44.723365 WL = 0x3
5052 19:29:44.726180 RL = 0x3
5053 19:29:44.726677 BL = 0x2
5054 19:29:44.729230 RPST = 0x0
5055 19:29:44.732214 RD_PRE = 0x0
5056 19:29:44.732684 WR_PRE = 0x1
5057 19:29:44.736046 WR_PST = 0x0
5058 19:29:44.736589 DBI_WR = 0x0
5059 19:29:44.739663 DBI_RD = 0x0
5060 19:29:44.740180 OTF = 0x1
5061 19:29:44.742796 ===================================
5062 19:29:44.746041 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5063 19:29:44.752970 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5064 19:29:44.755832 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5065 19:29:44.758832 ===================================
5066 19:29:44.762497 LPDDR4 DRAM CONFIGURATION
5067 19:29:44.765858 ===================================
5068 19:29:44.766429 EX_ROW_EN[0] = 0x10
5069 19:29:44.769083 EX_ROW_EN[1] = 0x0
5070 19:29:44.769605 LP4Y_EN = 0x0
5071 19:29:44.772472 WORK_FSP = 0x0
5072 19:29:44.772895 WL = 0x3
5073 19:29:44.776058 RL = 0x3
5074 19:29:44.776574 BL = 0x2
5075 19:29:44.778871 RPST = 0x0
5076 19:29:44.779337 RD_PRE = 0x0
5077 19:29:44.782890 WR_PRE = 0x1
5078 19:29:44.786107 WR_PST = 0x0
5079 19:29:44.786748 DBI_WR = 0x0
5080 19:29:44.788940 DBI_RD = 0x0
5081 19:29:44.789358 OTF = 0x1
5082 19:29:44.792343 ===================================
5083 19:29:44.799067 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5084 19:29:44.802543 nWR fixed to 30
5085 19:29:44.806060 [ModeRegInit_LP4] CH0 RK0
5086 19:29:44.806651 [ModeRegInit_LP4] CH0 RK1
5087 19:29:44.809109 [ModeRegInit_LP4] CH1 RK0
5088 19:29:44.812620 [ModeRegInit_LP4] CH1 RK1
5089 19:29:44.813149 match AC timing 9
5090 19:29:44.819106 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5091 19:29:44.822668 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5092 19:29:44.825619 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5093 19:29:44.832033 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5094 19:29:44.835459 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5095 19:29:44.835880 ==
5096 19:29:44.838834 Dram Type= 6, Freq= 0, CH_0, rank 0
5097 19:29:44.842284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5098 19:29:44.842874 ==
5099 19:29:44.849271 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5100 19:29:44.855819 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5101 19:29:44.858837 [CA 0] Center 37 (6~68) winsize 63
5102 19:29:44.862190 [CA 1] Center 37 (6~68) winsize 63
5103 19:29:44.865840 [CA 2] Center 34 (4~65) winsize 62
5104 19:29:44.869161 [CA 3] Center 34 (3~65) winsize 63
5105 19:29:44.872566 [CA 4] Center 33 (3~63) winsize 61
5106 19:29:44.875592 [CA 5] Center 32 (2~62) winsize 61
5107 19:29:44.876117
5108 19:29:44.879141 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5109 19:29:44.879632
5110 19:29:44.882559 [CATrainingPosCal] consider 1 rank data
5111 19:29:44.885605 u2DelayCellTimex100 = 270/100 ps
5112 19:29:44.889112 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5113 19:29:44.892325 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5114 19:29:44.895377 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5115 19:29:44.898719 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5116 19:29:44.901971 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5117 19:29:44.909114 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5118 19:29:44.909637
5119 19:29:44.912297 CA PerBit enable=1, Macro0, CA PI delay=32
5120 19:29:44.912816
5121 19:29:44.915139 [CBTSetCACLKResult] CA Dly = 32
5122 19:29:44.915577 CS Dly: 5 (0~36)
5123 19:29:44.915930 ==
5124 19:29:44.918937 Dram Type= 6, Freq= 0, CH_0, rank 1
5125 19:29:44.921946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5126 19:29:44.922487 ==
5127 19:29:44.928561 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5128 19:29:44.935375 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5129 19:29:44.938355 [CA 0] Center 37 (6~68) winsize 63
5130 19:29:44.942027 [CA 1] Center 37 (7~68) winsize 62
5131 19:29:44.945092 [CA 2] Center 34 (4~65) winsize 62
5132 19:29:44.948786 [CA 3] Center 34 (3~65) winsize 63
5133 19:29:44.951686 [CA 4] Center 33 (3~63) winsize 61
5134 19:29:44.955186 [CA 5] Center 32 (2~63) winsize 62
5135 19:29:44.955716
5136 19:29:44.958704 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5137 19:29:44.959126
5138 19:29:44.961948 [CATrainingPosCal] consider 2 rank data
5139 19:29:44.965522 u2DelayCellTimex100 = 270/100 ps
5140 19:29:44.968694 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5141 19:29:44.972282 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5142 19:29:44.975285 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5143 19:29:44.978970 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5144 19:29:44.985644 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5145 19:29:44.988763 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5146 19:29:44.989331
5147 19:29:44.991808 CA PerBit enable=1, Macro0, CA PI delay=32
5148 19:29:44.992378
5149 19:29:44.995166 [CBTSetCACLKResult] CA Dly = 32
5150 19:29:44.995747 CS Dly: 5 (0~37)
5151 19:29:44.996124
5152 19:29:44.998960 ----->DramcWriteLeveling(PI) begin...
5153 19:29:44.999536 ==
5154 19:29:45.001759 Dram Type= 6, Freq= 0, CH_0, rank 0
5155 19:29:45.008204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5156 19:29:45.008779 ==
5157 19:29:45.012236 Write leveling (Byte 0): 31 => 31
5158 19:29:45.014909 Write leveling (Byte 1): 28 => 28
5159 19:29:45.015380 DramcWriteLeveling(PI) end<-----
5160 19:29:45.015836
5161 19:29:45.018165 ==
5162 19:29:45.021405 Dram Type= 6, Freq= 0, CH_0, rank 0
5163 19:29:45.024745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5164 19:29:45.025169 ==
5165 19:29:45.028045 [Gating] SW mode calibration
5166 19:29:45.034674 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5167 19:29:45.038148 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5168 19:29:45.044871 0 14 0 | B1->B0 | 2727 3434 | 1 1 | (0 0) (1 1)
5169 19:29:45.047936 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5170 19:29:45.051642 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5171 19:29:45.058150 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5172 19:29:45.061196 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5173 19:29:45.064469 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5174 19:29:45.071120 0 14 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
5175 19:29:45.074617 0 14 28 | B1->B0 | 3434 2424 | 0 0 | (0 0) (0 0)
5176 19:29:45.078009 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
5177 19:29:45.084811 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5178 19:29:45.087868 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5179 19:29:45.091132 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5180 19:29:45.097907 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5181 19:29:45.101137 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5182 19:29:45.104906 0 15 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 1)
5183 19:29:45.111215 0 15 28 | B1->B0 | 2727 3c3c | 0 0 | (0 0) (0 0)
5184 19:29:45.114515 1 0 0 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
5185 19:29:45.117714 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5186 19:29:45.124756 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5187 19:29:45.127959 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5188 19:29:45.130554 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5189 19:29:45.137349 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5190 19:29:45.140954 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5191 19:29:45.144129 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5192 19:29:45.150795 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 19:29:45.154024 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 19:29:45.157370 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 19:29:45.163704 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 19:29:45.167615 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 19:29:45.170288 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 19:29:45.173803 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 19:29:45.180981 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 19:29:45.184445 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 19:29:45.187229 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 19:29:45.194285 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 19:29:45.197258 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 19:29:45.200595 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 19:29:45.207239 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 19:29:45.210500 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 19:29:45.213985 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5208 19:29:45.220212 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5209 19:29:45.223935 Total UI for P1: 0, mck2ui 16
5210 19:29:45.226918 best dqsien dly found for B0: ( 1, 2, 28)
5211 19:29:45.230075 Total UI for P1: 0, mck2ui 16
5212 19:29:45.233767 best dqsien dly found for B1: ( 1, 2, 28)
5213 19:29:45.236971 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5214 19:29:45.240266 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5215 19:29:45.240789
5216 19:29:45.244180 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5217 19:29:45.247078 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5218 19:29:45.250389 [Gating] SW calibration Done
5219 19:29:45.250966 ==
5220 19:29:45.253976 Dram Type= 6, Freq= 0, CH_0, rank 0
5221 19:29:45.256686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5222 19:29:45.257220 ==
5223 19:29:45.260219 RX Vref Scan: 0
5224 19:29:45.260696
5225 19:29:45.261216 RX Vref 0 -> 0, step: 1
5226 19:29:45.263425
5227 19:29:45.263875 RX Delay -80 -> 252, step: 8
5228 19:29:45.270271 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5229 19:29:45.273580 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5230 19:29:45.277133 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5231 19:29:45.279874 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5232 19:29:45.283286 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5233 19:29:45.286843 iDelay=208, Bit 5, Center 95 (8 ~ 183) 176
5234 19:29:45.293367 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5235 19:29:45.296810 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5236 19:29:45.300102 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5237 19:29:45.303090 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5238 19:29:45.306586 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5239 19:29:45.309785 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5240 19:29:45.316909 iDelay=208, Bit 12, Center 103 (16 ~ 191) 176
5241 19:29:45.319724 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5242 19:29:45.323451 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5243 19:29:45.326527 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5244 19:29:45.326993 ==
5245 19:29:45.330452 Dram Type= 6, Freq= 0, CH_0, rank 0
5246 19:29:45.336384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5247 19:29:45.336949 ==
5248 19:29:45.337320 DQS Delay:
5249 19:29:45.337664 DQS0 = 0, DQS1 = 0
5250 19:29:45.340008 DQM Delay:
5251 19:29:45.340576 DQM0 = 105, DQM1 = 96
5252 19:29:45.343296 DQ Delay:
5253 19:29:45.346922 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5254 19:29:45.349803 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =115
5255 19:29:45.353211 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =91
5256 19:29:45.356544 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5257 19:29:45.357009
5258 19:29:45.357376
5259 19:29:45.357719 ==
5260 19:29:45.359605 Dram Type= 6, Freq= 0, CH_0, rank 0
5261 19:29:45.363314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5262 19:29:45.363900 ==
5263 19:29:45.364273
5264 19:29:45.364616
5265 19:29:45.366392 TX Vref Scan disable
5266 19:29:45.369658 == TX Byte 0 ==
5267 19:29:45.373040 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5268 19:29:45.376513 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5269 19:29:45.379593 == TX Byte 1 ==
5270 19:29:45.383178 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5271 19:29:45.386764 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5272 19:29:45.387327 ==
5273 19:29:45.389428 Dram Type= 6, Freq= 0, CH_0, rank 0
5274 19:29:45.396223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5275 19:29:45.396777 ==
5276 19:29:45.397151
5277 19:29:45.397491
5278 19:29:45.397824 TX Vref Scan disable
5279 19:29:45.400940 == TX Byte 0 ==
5280 19:29:45.403551 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5281 19:29:45.410024 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5282 19:29:45.410630 == TX Byte 1 ==
5283 19:29:45.413417 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5284 19:29:45.420138 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5285 19:29:45.420683
5286 19:29:45.421049 [DATLAT]
5287 19:29:45.421390 Freq=933, CH0 RK0
5288 19:29:45.421726
5289 19:29:45.423137 DATLAT Default: 0xd
5290 19:29:45.423603 0, 0xFFFF, sum = 0
5291 19:29:45.427143 1, 0xFFFF, sum = 0
5292 19:29:45.430279 2, 0xFFFF, sum = 0
5293 19:29:45.430892 3, 0xFFFF, sum = 0
5294 19:29:45.433067 4, 0xFFFF, sum = 0
5295 19:29:45.433563 5, 0xFFFF, sum = 0
5296 19:29:45.437184 6, 0xFFFF, sum = 0
5297 19:29:45.437748 7, 0xFFFF, sum = 0
5298 19:29:45.440073 8, 0xFFFF, sum = 0
5299 19:29:45.440566 9, 0xFFFF, sum = 0
5300 19:29:45.443093 10, 0x0, sum = 1
5301 19:29:45.443562 11, 0x0, sum = 2
5302 19:29:45.446494 12, 0x0, sum = 3
5303 19:29:45.446966 13, 0x0, sum = 4
5304 19:29:45.447336 best_step = 11
5305 19:29:45.447677
5306 19:29:45.450475 ==
5307 19:29:45.453700 Dram Type= 6, Freq= 0, CH_0, rank 0
5308 19:29:45.456363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5309 19:29:45.456832 ==
5310 19:29:45.457195 RX Vref Scan: 1
5311 19:29:45.457531
5312 19:29:45.459822 RX Vref 0 -> 0, step: 1
5313 19:29:45.460436
5314 19:29:45.463471 RX Delay -45 -> 252, step: 4
5315 19:29:45.463934
5316 19:29:45.466729 Set Vref, RX VrefLevel [Byte0]: 58
5317 19:29:45.470124 [Byte1]: 45
5318 19:29:45.470792
5319 19:29:45.473322 Final RX Vref Byte 0 = 58 to rank0
5320 19:29:45.476971 Final RX Vref Byte 1 = 45 to rank0
5321 19:29:45.479757 Final RX Vref Byte 0 = 58 to rank1
5322 19:29:45.482844 Final RX Vref Byte 1 = 45 to rank1==
5323 19:29:45.486388 Dram Type= 6, Freq= 0, CH_0, rank 0
5324 19:29:45.489598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5325 19:29:45.493025 ==
5326 19:29:45.493595 DQS Delay:
5327 19:29:45.493966 DQS0 = 0, DQS1 = 0
5328 19:29:45.496447 DQM Delay:
5329 19:29:45.496910 DQM0 = 105, DQM1 = 94
5330 19:29:45.500063 DQ Delay:
5331 19:29:45.503053 DQ0 =104, DQ1 =106, DQ2 =104, DQ3 =102
5332 19:29:45.506196 DQ4 =106, DQ5 =96, DQ6 =114, DQ7 =110
5333 19:29:45.509257 DQ8 =84, DQ9 =82, DQ10 =96, DQ11 =90
5334 19:29:45.512490 DQ12 =98, DQ13 =98, DQ14 =106, DQ15 =100
5335 19:29:45.512962
5336 19:29:45.513329
5337 19:29:45.519089 [DQSOSCAuto] RK0, (LSB)MR18= 0x3129, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 406 ps
5338 19:29:45.522868 CH0 RK0: MR19=505, MR18=3129
5339 19:29:45.529322 CH0_RK0: MR19=0x505, MR18=0x3129, DQSOSC=406, MR23=63, INC=65, DEC=43
5340 19:29:45.529863
5341 19:29:45.532555 ----->DramcWriteLeveling(PI) begin...
5342 19:29:45.533098 ==
5343 19:29:45.535774 Dram Type= 6, Freq= 0, CH_0, rank 1
5344 19:29:45.539904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5345 19:29:45.540431 ==
5346 19:29:45.542903 Write leveling (Byte 0): 34 => 34
5347 19:29:45.546133 Write leveling (Byte 1): 26 => 26
5348 19:29:45.549021 DramcWriteLeveling(PI) end<-----
5349 19:29:45.549445
5350 19:29:45.549771 ==
5351 19:29:45.552420 Dram Type= 6, Freq= 0, CH_0, rank 1
5352 19:29:45.555673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5353 19:29:45.556096 ==
5354 19:29:45.559701 [Gating] SW mode calibration
5355 19:29:45.565757 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5356 19:29:45.572984 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5357 19:29:45.576511 0 14 0 | B1->B0 | 3333 3434 | 0 0 | (0 0) (0 0)
5358 19:29:45.582486 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5359 19:29:45.586257 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5360 19:29:45.589474 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5361 19:29:45.595944 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5362 19:29:45.599394 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5363 19:29:45.602819 0 14 24 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5364 19:29:45.609023 0 14 28 | B1->B0 | 2d2d 2e2e | 0 0 | (0 1) (0 1)
5365 19:29:45.612596 0 15 0 | B1->B0 | 2323 2525 | 0 1 | (0 0) (1 0)
5366 19:29:45.615892 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5367 19:29:45.622692 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5368 19:29:45.625574 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5369 19:29:45.628725 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5370 19:29:45.632350 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5371 19:29:45.639239 0 15 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5372 19:29:45.642246 0 15 28 | B1->B0 | 3a3a 3636 | 0 0 | (0 0) (0 0)
5373 19:29:45.645509 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5374 19:29:45.652269 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5375 19:29:45.655340 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5376 19:29:45.659081 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5377 19:29:45.665373 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5378 19:29:45.668985 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5379 19:29:45.672147 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5380 19:29:45.678563 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5381 19:29:45.682114 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5382 19:29:45.685071 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 19:29:45.691825 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 19:29:45.695594 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 19:29:45.698644 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 19:29:45.704946 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 19:29:45.708286 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 19:29:45.712009 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 19:29:45.718848 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 19:29:45.721854 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 19:29:45.725186 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 19:29:45.732348 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 19:29:45.735131 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 19:29:45.738635 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 19:29:45.744915 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 19:29:45.748176 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5397 19:29:45.751790 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5398 19:29:45.754948 Total UI for P1: 0, mck2ui 16
5399 19:29:45.758451 best dqsien dly found for B0: ( 1, 2, 28)
5400 19:29:45.761767 Total UI for P1: 0, mck2ui 16
5401 19:29:45.765217 best dqsien dly found for B1: ( 1, 2, 28)
5402 19:29:45.768151 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5403 19:29:45.771666 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5404 19:29:45.772133
5405 19:29:45.775279 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5406 19:29:45.781423 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5407 19:29:45.781974 [Gating] SW calibration Done
5408 19:29:45.784990 ==
5409 19:29:45.785554 Dram Type= 6, Freq= 0, CH_0, rank 1
5410 19:29:45.791565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5411 19:29:45.792130 ==
5412 19:29:45.792503 RX Vref Scan: 0
5413 19:29:45.792850
5414 19:29:45.794703 RX Vref 0 -> 0, step: 1
5415 19:29:45.795169
5416 19:29:45.798551 RX Delay -80 -> 252, step: 8
5417 19:29:45.801977 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5418 19:29:45.804859 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5419 19:29:45.808318 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5420 19:29:45.814840 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5421 19:29:45.818456 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5422 19:29:45.821432 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5423 19:29:45.825019 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5424 19:29:45.828245 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5425 19:29:45.831078 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5426 19:29:45.838570 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5427 19:29:45.841655 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5428 19:29:45.844584 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5429 19:29:45.848504 iDelay=208, Bit 12, Center 99 (16 ~ 183) 168
5430 19:29:45.851022 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5431 19:29:45.854768 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5432 19:29:45.861083 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5433 19:29:45.861555 ==
5434 19:29:45.864692 Dram Type= 6, Freq= 0, CH_0, rank 1
5435 19:29:45.868045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5436 19:29:45.868737 ==
5437 19:29:45.869128 DQS Delay:
5438 19:29:45.871437 DQS0 = 0, DQS1 = 0
5439 19:29:45.872002 DQM Delay:
5440 19:29:45.874432 DQM0 = 104, DQM1 = 94
5441 19:29:45.874897 DQ Delay:
5442 19:29:45.878147 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =99
5443 19:29:45.881297 DQ4 =107, DQ5 =95, DQ6 =107, DQ7 =111
5444 19:29:45.884506 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5445 19:29:45.888071 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5446 19:29:45.888634
5447 19:29:45.888996
5448 19:29:45.889334 ==
5449 19:29:45.891052 Dram Type= 6, Freq= 0, CH_0, rank 1
5450 19:29:45.897814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5451 19:29:45.898485 ==
5452 19:29:45.898865
5453 19:29:45.899204
5454 19:29:45.899527 TX Vref Scan disable
5455 19:29:45.901316 == TX Byte 0 ==
5456 19:29:45.904471 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5457 19:29:45.907970 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5458 19:29:45.911097 == TX Byte 1 ==
5459 19:29:45.914369 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5460 19:29:45.921026 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5461 19:29:45.921589 ==
5462 19:29:45.924658 Dram Type= 6, Freq= 0, CH_0, rank 1
5463 19:29:45.927500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5464 19:29:45.927963 ==
5465 19:29:45.928327
5466 19:29:45.928664
5467 19:29:45.931040 TX Vref Scan disable
5468 19:29:45.931672 == TX Byte 0 ==
5469 19:29:45.937778 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5470 19:29:45.941133 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5471 19:29:45.944195 == TX Byte 1 ==
5472 19:29:45.947250 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5473 19:29:45.950968 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5474 19:29:45.951533
5475 19:29:45.951904 [DATLAT]
5476 19:29:45.953906 Freq=933, CH0 RK1
5477 19:29:45.954421
5478 19:29:45.954802 DATLAT Default: 0xb
5479 19:29:45.957064 0, 0xFFFF, sum = 0
5480 19:29:45.960900 1, 0xFFFF, sum = 0
5481 19:29:45.961377 2, 0xFFFF, sum = 0
5482 19:29:45.963733 3, 0xFFFF, sum = 0
5483 19:29:45.964209 4, 0xFFFF, sum = 0
5484 19:29:45.967206 5, 0xFFFF, sum = 0
5485 19:29:45.967777 6, 0xFFFF, sum = 0
5486 19:29:45.970382 7, 0xFFFF, sum = 0
5487 19:29:45.970931 8, 0xFFFF, sum = 0
5488 19:29:45.974062 9, 0xFFFF, sum = 0
5489 19:29:45.974684 10, 0x0, sum = 1
5490 19:29:45.977066 11, 0x0, sum = 2
5491 19:29:45.977632 12, 0x0, sum = 3
5492 19:29:45.980520 13, 0x0, sum = 4
5493 19:29:45.981000 best_step = 11
5494 19:29:45.981370
5495 19:29:45.981714 ==
5496 19:29:45.984413 Dram Type= 6, Freq= 0, CH_0, rank 1
5497 19:29:45.987327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5498 19:29:45.987891 ==
5499 19:29:45.990603 RX Vref Scan: 0
5500 19:29:45.991072
5501 19:29:45.993907 RX Vref 0 -> 0, step: 1
5502 19:29:45.994614
5503 19:29:45.995019 RX Delay -45 -> 252, step: 4
5504 19:29:46.001970 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5505 19:29:46.004817 iDelay=199, Bit 1, Center 106 (23 ~ 190) 168
5506 19:29:46.007988 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5507 19:29:46.011562 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5508 19:29:46.014493 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5509 19:29:46.021772 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5510 19:29:46.024822 iDelay=199, Bit 6, Center 110 (23 ~ 198) 176
5511 19:29:46.027777 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5512 19:29:46.031613 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5513 19:29:46.034780 iDelay=199, Bit 9, Center 82 (-1 ~ 166) 168
5514 19:29:46.041421 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5515 19:29:46.044914 iDelay=199, Bit 11, Center 86 (3 ~ 170) 168
5516 19:29:46.048004 iDelay=199, Bit 12, Center 98 (19 ~ 178) 160
5517 19:29:46.051333 iDelay=199, Bit 13, Center 100 (19 ~ 182) 164
5518 19:29:46.054794 iDelay=199, Bit 14, Center 104 (23 ~ 186) 164
5519 19:29:46.061264 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5520 19:29:46.061697 ==
5521 19:29:46.064539 Dram Type= 6, Freq= 0, CH_0, rank 1
5522 19:29:46.067630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5523 19:29:46.068060 ==
5524 19:29:46.068395 DQS Delay:
5525 19:29:46.071297 DQS0 = 0, DQS1 = 0
5526 19:29:46.071725 DQM Delay:
5527 19:29:46.074263 DQM0 = 104, DQM1 = 93
5528 19:29:46.074738 DQ Delay:
5529 19:29:46.077774 DQ0 =102, DQ1 =106, DQ2 =102, DQ3 =102
5530 19:29:46.081171 DQ4 =106, DQ5 =98, DQ6 =110, DQ7 =112
5531 19:29:46.084207 DQ8 =84, DQ9 =82, DQ10 =94, DQ11 =86
5532 19:29:46.087158 DQ12 =98, DQ13 =100, DQ14 =104, DQ15 =102
5533 19:29:46.087390
5534 19:29:46.087571
5535 19:29:46.097056 [DQSOSCAuto] RK1, (LSB)MR18= 0x26ff, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 409 ps
5536 19:29:46.100259 CH0 RK1: MR19=504, MR18=26FF
5537 19:29:46.103697 CH0_RK1: MR19=0x504, MR18=0x26FF, DQSOSC=409, MR23=63, INC=64, DEC=43
5538 19:29:46.107010 [RxdqsGatingPostProcess] freq 933
5539 19:29:46.114050 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5540 19:29:46.117162 best DQS0 dly(2T, 0.5T) = (0, 10)
5541 19:29:46.120347 best DQS1 dly(2T, 0.5T) = (0, 10)
5542 19:29:46.123416 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5543 19:29:46.127119 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5544 19:29:46.130260 best DQS0 dly(2T, 0.5T) = (0, 10)
5545 19:29:46.133503 best DQS1 dly(2T, 0.5T) = (0, 10)
5546 19:29:46.136802 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5547 19:29:46.140393 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5548 19:29:46.140486 Pre-setting of DQS Precalculation
5549 19:29:46.147175 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5550 19:29:46.147262 ==
5551 19:29:46.150235 Dram Type= 6, Freq= 0, CH_1, rank 0
5552 19:29:46.153385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5553 19:29:46.153470 ==
5554 19:29:46.160647 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5555 19:29:46.167102 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5556 19:29:46.170341 [CA 0] Center 36 (6~67) winsize 62
5557 19:29:46.174107 [CA 1] Center 36 (6~67) winsize 62
5558 19:29:46.177365 [CA 2] Center 34 (4~65) winsize 62
5559 19:29:46.180528 [CA 3] Center 34 (4~64) winsize 61
5560 19:29:46.183668 [CA 4] Center 34 (4~64) winsize 61
5561 19:29:46.186870 [CA 5] Center 33 (3~64) winsize 62
5562 19:29:46.186955
5563 19:29:46.190352 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5564 19:29:46.190443
5565 19:29:46.193740 [CATrainingPosCal] consider 1 rank data
5566 19:29:46.197258 u2DelayCellTimex100 = 270/100 ps
5567 19:29:46.200402 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5568 19:29:46.203390 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5569 19:29:46.206807 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5570 19:29:46.210056 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5571 19:29:46.213451 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5572 19:29:46.216856 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5573 19:29:46.216943
5574 19:29:46.223387 CA PerBit enable=1, Macro0, CA PI delay=33
5575 19:29:46.223514
5576 19:29:46.223582 [CBTSetCACLKResult] CA Dly = 33
5577 19:29:46.226777 CS Dly: 6 (0~37)
5578 19:29:46.226864 ==
5579 19:29:46.230269 Dram Type= 6, Freq= 0, CH_1, rank 1
5580 19:29:46.233396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5581 19:29:46.233489 ==
5582 19:29:46.240303 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5583 19:29:46.246727 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5584 19:29:46.250102 [CA 0] Center 37 (7~67) winsize 61
5585 19:29:46.253137 [CA 1] Center 37 (7~68) winsize 62
5586 19:29:46.256627 [CA 2] Center 35 (5~65) winsize 61
5587 19:29:46.259962 [CA 3] Center 34 (4~65) winsize 62
5588 19:29:46.263541 [CA 4] Center 34 (4~65) winsize 62
5589 19:29:46.266588 [CA 5] Center 33 (3~64) winsize 62
5590 19:29:46.266690
5591 19:29:46.269928 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5592 19:29:46.270016
5593 19:29:46.273590 [CATrainingPosCal] consider 2 rank data
5594 19:29:46.276630 u2DelayCellTimex100 = 270/100 ps
5595 19:29:46.279887 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5596 19:29:46.283019 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5597 19:29:46.286233 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5598 19:29:46.289450 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5599 19:29:46.293146 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5600 19:29:46.299522 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5601 19:29:46.299613
5602 19:29:46.302863 CA PerBit enable=1, Macro0, CA PI delay=33
5603 19:29:46.303028
5604 19:29:46.306314 [CBTSetCACLKResult] CA Dly = 33
5605 19:29:46.306439 CS Dly: 7 (0~40)
5606 19:29:46.306519
5607 19:29:46.309360 ----->DramcWriteLeveling(PI) begin...
5608 19:29:46.309522 ==
5609 19:29:46.312946 Dram Type= 6, Freq= 0, CH_1, rank 0
5610 19:29:46.319500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5611 19:29:46.319657 ==
5612 19:29:46.322652 Write leveling (Byte 0): 26 => 26
5613 19:29:46.322777 Write leveling (Byte 1): 26 => 26
5614 19:29:46.326206 DramcWriteLeveling(PI) end<-----
5615 19:29:46.326420
5616 19:29:46.329415 ==
5617 19:29:46.329560 Dram Type= 6, Freq= 0, CH_1, rank 0
5618 19:29:46.335958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5619 19:29:46.336090 ==
5620 19:29:46.339014 [Gating] SW mode calibration
5621 19:29:46.345978 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5622 19:29:46.349883 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5623 19:29:46.356364 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5624 19:29:46.359321 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5625 19:29:46.362961 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5626 19:29:46.369266 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5627 19:29:46.373072 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5628 19:29:46.376094 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5629 19:29:46.382592 0 14 24 | B1->B0 | 3333 3030 | 1 0 | (1 0) (0 1)
5630 19:29:46.386373 0 14 28 | B1->B0 | 2929 2323 | 0 0 | (1 0) (1 0)
5631 19:29:46.389407 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5632 19:29:46.396063 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5633 19:29:46.399623 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5634 19:29:46.402917 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5635 19:29:46.409296 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5636 19:29:46.412985 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5637 19:29:46.416047 0 15 24 | B1->B0 | 2424 3737 | 0 1 | (0 0) (0 0)
5638 19:29:46.422813 0 15 28 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5639 19:29:46.426089 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5640 19:29:46.429354 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5641 19:29:46.435371 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5642 19:29:46.438771 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5643 19:29:46.442696 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5644 19:29:46.445851 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5645 19:29:46.451988 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5646 19:29:46.455634 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 19:29:46.458757 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 19:29:46.465204 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 19:29:46.468808 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 19:29:46.472077 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 19:29:46.478829 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 19:29:46.481796 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 19:29:46.485622 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 19:29:46.491813 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5655 19:29:46.496137 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 19:29:46.499072 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 19:29:46.505295 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5658 19:29:46.508725 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5659 19:29:46.512109 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5660 19:29:46.518381 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5661 19:29:46.522354 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5662 19:29:46.525414 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5663 19:29:46.531818 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5664 19:29:46.535039 Total UI for P1: 0, mck2ui 16
5665 19:29:46.538728 best dqsien dly found for B0: ( 1, 2, 26)
5666 19:29:46.539193 Total UI for P1: 0, mck2ui 16
5667 19:29:46.545310 best dqsien dly found for B1: ( 1, 2, 28)
5668 19:29:46.548357 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5669 19:29:46.551319 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5670 19:29:46.551783
5671 19:29:46.555027 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5672 19:29:46.558062 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5673 19:29:46.561300 [Gating] SW calibration Done
5674 19:29:46.561760 ==
5675 19:29:46.565197 Dram Type= 6, Freq= 0, CH_1, rank 0
5676 19:29:46.568536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5677 19:29:46.569093 ==
5678 19:29:46.571666 RX Vref Scan: 0
5679 19:29:46.572127
5680 19:29:46.572487 RX Vref 0 -> 0, step: 1
5681 19:29:46.572821
5682 19:29:46.574595 RX Delay -80 -> 252, step: 8
5683 19:29:46.581396 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5684 19:29:46.584660 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5685 19:29:46.588259 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5686 19:29:46.591784 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5687 19:29:46.594889 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5688 19:29:46.598113 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5689 19:29:46.601657 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5690 19:29:46.608285 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5691 19:29:46.611118 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5692 19:29:46.614635 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5693 19:29:46.618110 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5694 19:29:46.621065 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5695 19:29:46.627954 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5696 19:29:46.631322 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5697 19:29:46.634708 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5698 19:29:46.637540 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5699 19:29:46.638006 ==
5700 19:29:46.641678 Dram Type= 6, Freq= 0, CH_1, rank 0
5701 19:29:46.648023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5702 19:29:46.648596 ==
5703 19:29:46.648973 DQS Delay:
5704 19:29:46.649318 DQS0 = 0, DQS1 = 0
5705 19:29:46.650847 DQM Delay:
5706 19:29:46.651317 DQM0 = 102, DQM1 = 98
5707 19:29:46.654334 DQ Delay:
5708 19:29:46.657650 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5709 19:29:46.660976 DQ4 =99, DQ5 =115, DQ6 =111, DQ7 =103
5710 19:29:46.664462 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5711 19:29:46.667674 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5712 19:29:46.668240
5713 19:29:46.668612
5714 19:29:46.668957 ==
5715 19:29:46.671095 Dram Type= 6, Freq= 0, CH_1, rank 0
5716 19:29:46.674450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5717 19:29:46.675013 ==
5718 19:29:46.675390
5719 19:29:46.675736
5720 19:29:46.677969 TX Vref Scan disable
5721 19:29:46.681198 == TX Byte 0 ==
5722 19:29:46.684481 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5723 19:29:46.687964 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5724 19:29:46.690939 == TX Byte 1 ==
5725 19:29:46.694909 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5726 19:29:46.697624 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5727 19:29:46.698182 ==
5728 19:29:46.701403 Dram Type= 6, Freq= 0, CH_1, rank 0
5729 19:29:46.704267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5730 19:29:46.704732 ==
5731 19:29:46.707877
5732 19:29:46.708437
5733 19:29:46.708884 TX Vref Scan disable
5734 19:29:46.710911 == TX Byte 0 ==
5735 19:29:46.714263 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5736 19:29:46.717971 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5737 19:29:46.720759 == TX Byte 1 ==
5738 19:29:46.724258 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5739 19:29:46.727609 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5740 19:29:46.730809
5741 19:29:46.731268 [DATLAT]
5742 19:29:46.731633 Freq=933, CH1 RK0
5743 19:29:46.731975
5744 19:29:46.734536 DATLAT Default: 0xd
5745 19:29:46.734976 0, 0xFFFF, sum = 0
5746 19:29:46.737608 1, 0xFFFF, sum = 0
5747 19:29:46.738037 2, 0xFFFF, sum = 0
5748 19:29:46.741221 3, 0xFFFF, sum = 0
5749 19:29:46.744425 4, 0xFFFF, sum = 0
5750 19:29:46.744962 5, 0xFFFF, sum = 0
5751 19:29:46.747360 6, 0xFFFF, sum = 0
5752 19:29:46.747787 7, 0xFFFF, sum = 0
5753 19:29:46.750725 8, 0xFFFF, sum = 0
5754 19:29:46.751150 9, 0xFFFF, sum = 0
5755 19:29:46.754700 10, 0x0, sum = 1
5756 19:29:46.755222 11, 0x0, sum = 2
5757 19:29:46.755560 12, 0x0, sum = 3
5758 19:29:46.757613 13, 0x0, sum = 4
5759 19:29:46.758034 best_step = 11
5760 19:29:46.758422
5761 19:29:46.760868 ==
5762 19:29:46.761286 Dram Type= 6, Freq= 0, CH_1, rank 0
5763 19:29:46.767576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5764 19:29:46.768095 ==
5765 19:29:46.768432 RX Vref Scan: 1
5766 19:29:46.768744
5767 19:29:46.770709 RX Vref 0 -> 0, step: 1
5768 19:29:46.771225
5769 19:29:46.774559 RX Delay -45 -> 252, step: 4
5770 19:29:46.775072
5771 19:29:46.777223 Set Vref, RX VrefLevel [Byte0]: 52
5772 19:29:46.780980 [Byte1]: 47
5773 19:29:46.781500
5774 19:29:46.784022 Final RX Vref Byte 0 = 52 to rank0
5775 19:29:46.786969 Final RX Vref Byte 1 = 47 to rank0
5776 19:29:46.790264 Final RX Vref Byte 0 = 52 to rank1
5777 19:29:46.794360 Final RX Vref Byte 1 = 47 to rank1==
5778 19:29:46.797271 Dram Type= 6, Freq= 0, CH_1, rank 0
5779 19:29:46.800544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5780 19:29:46.800972 ==
5781 19:29:46.804085 DQS Delay:
5782 19:29:46.804612 DQS0 = 0, DQS1 = 0
5783 19:29:46.806894 DQM Delay:
5784 19:29:46.807310 DQM0 = 103, DQM1 = 99
5785 19:29:46.810463 DQ Delay:
5786 19:29:46.813588 DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =100
5787 19:29:46.817065 DQ4 =104, DQ5 =112, DQ6 =112, DQ7 =102
5788 19:29:46.820454 DQ8 =88, DQ9 =88, DQ10 =98, DQ11 =92
5789 19:29:46.824108 DQ12 =106, DQ13 =106, DQ14 =108, DQ15 =108
5790 19:29:46.824630
5791 19:29:46.824968
5792 19:29:46.830089 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a31, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
5793 19:29:46.833536 CH1 RK0: MR19=505, MR18=1A31
5794 19:29:46.840465 CH1_RK0: MR19=0x505, MR18=0x1A31, DQSOSC=406, MR23=63, INC=65, DEC=43
5795 19:29:46.840932
5796 19:29:46.843659 ----->DramcWriteLeveling(PI) begin...
5797 19:29:46.844128 ==
5798 19:29:46.846785 Dram Type= 6, Freq= 0, CH_1, rank 1
5799 19:29:46.850436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5800 19:29:46.851002 ==
5801 19:29:46.853809 Write leveling (Byte 0): 26 => 26
5802 19:29:46.856785 Write leveling (Byte 1): 31 => 31
5803 19:29:46.859958 DramcWriteLeveling(PI) end<-----
5804 19:29:46.860419
5805 19:29:46.860808 ==
5806 19:29:46.863364 Dram Type= 6, Freq= 0, CH_1, rank 1
5807 19:29:46.867054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5808 19:29:46.870626 ==
5809 19:29:46.871189 [Gating] SW mode calibration
5810 19:29:46.879957 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5811 19:29:46.883489 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5812 19:29:46.886995 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5813 19:29:46.893223 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5814 19:29:46.896375 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5815 19:29:46.900268 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5816 19:29:46.906437 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5817 19:29:46.909777 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5818 19:29:46.913588 0 14 24 | B1->B0 | 2b2b 3232 | 1 1 | (1 1) (1 1)
5819 19:29:46.919780 0 14 28 | B1->B0 | 2323 2323 | 0 1 | (1 0) (1 0)
5820 19:29:46.922906 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5821 19:29:46.926376 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5822 19:29:46.932936 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5823 19:29:46.936308 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5824 19:29:46.939464 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5825 19:29:46.946790 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5826 19:29:46.949580 0 15 24 | B1->B0 | 3636 2e2e | 1 1 | (0 0) (1 1)
5827 19:29:46.952760 0 15 28 | B1->B0 | 4646 4141 | 0 1 | (0 0) (0 0)
5828 19:29:46.959300 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5829 19:29:46.962699 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5830 19:29:46.965896 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5831 19:29:46.972696 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5832 19:29:46.975845 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5833 19:29:46.979339 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5834 19:29:46.986132 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5835 19:29:46.989484 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5836 19:29:46.992814 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 19:29:46.995928 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 19:29:47.002979 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 19:29:47.005995 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 19:29:47.012835 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 19:29:47.015743 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 19:29:47.019452 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5843 19:29:47.022719 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5844 19:29:47.029006 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5845 19:29:47.032921 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5846 19:29:47.035899 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5847 19:29:47.042332 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5848 19:29:47.045779 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5849 19:29:47.049055 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 19:29:47.055786 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5851 19:29:47.058672 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5852 19:29:47.062284 Total UI for P1: 0, mck2ui 16
5853 19:29:47.065618 best dqsien dly found for B0: ( 1, 2, 26)
5854 19:29:47.068851 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5855 19:29:47.072622 Total UI for P1: 0, mck2ui 16
5856 19:29:47.075516 best dqsien dly found for B1: ( 1, 2, 26)
5857 19:29:47.079290 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5858 19:29:47.082625 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5859 19:29:47.083094
5860 19:29:47.088955 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5861 19:29:47.091890 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5862 19:29:47.092318 [Gating] SW calibration Done
5863 19:29:47.095662 ==
5864 19:29:47.099023 Dram Type= 6, Freq= 0, CH_1, rank 1
5865 19:29:47.102126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5866 19:29:47.102625 ==
5867 19:29:47.103002 RX Vref Scan: 0
5868 19:29:47.103353
5869 19:29:47.105228 RX Vref 0 -> 0, step: 1
5870 19:29:47.105652
5871 19:29:47.109267 RX Delay -80 -> 252, step: 8
5872 19:29:47.112396 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5873 19:29:47.115105 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5874 19:29:47.118971 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5875 19:29:47.126027 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5876 19:29:47.128984 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5877 19:29:47.132329 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5878 19:29:47.135793 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5879 19:29:47.138646 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5880 19:29:47.141640 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5881 19:29:47.148975 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5882 19:29:47.151624 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5883 19:29:47.155304 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5884 19:29:47.158486 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5885 19:29:47.161903 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5886 19:29:47.169094 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5887 19:29:47.172292 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5888 19:29:47.172869 ==
5889 19:29:47.175677 Dram Type= 6, Freq= 0, CH_1, rank 1
5890 19:29:47.178679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5891 19:29:47.179155 ==
5892 19:29:47.179530 DQS Delay:
5893 19:29:47.182225 DQS0 = 0, DQS1 = 0
5894 19:29:47.182768 DQM Delay:
5895 19:29:47.185319 DQM0 = 102, DQM1 = 97
5896 19:29:47.185786 DQ Delay:
5897 19:29:47.189133 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =99
5898 19:29:47.191951 DQ4 =95, DQ5 =115, DQ6 =115, DQ7 =99
5899 19:29:47.195474 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5900 19:29:47.199069 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5901 19:29:47.199650
5902 19:29:47.200111
5903 19:29:47.200482 ==
5904 19:29:47.202341 Dram Type= 6, Freq= 0, CH_1, rank 1
5905 19:29:47.209263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5906 19:29:47.209842 ==
5907 19:29:47.210219
5908 19:29:47.210629
5909 19:29:47.210970 TX Vref Scan disable
5910 19:29:47.211942 == TX Byte 0 ==
5911 19:29:47.215972 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5912 19:29:47.218939 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5913 19:29:47.222373 == TX Byte 1 ==
5914 19:29:47.225708 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5915 19:29:47.232051 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5916 19:29:47.232629 ==
5917 19:29:47.235285 Dram Type= 6, Freq= 0, CH_1, rank 1
5918 19:29:47.238547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5919 19:29:47.239121 ==
5920 19:29:47.239497
5921 19:29:47.239841
5922 19:29:47.241999 TX Vref Scan disable
5923 19:29:47.242504 == TX Byte 0 ==
5924 19:29:47.248856 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5925 19:29:47.251567 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5926 19:29:47.255358 == TX Byte 1 ==
5927 19:29:47.258454 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5928 19:29:47.261870 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5929 19:29:47.262479
5930 19:29:47.262855 [DATLAT]
5931 19:29:47.264638 Freq=933, CH1 RK1
5932 19:29:47.265109
5933 19:29:47.265483 DATLAT Default: 0xb
5934 19:29:47.268256 0, 0xFFFF, sum = 0
5935 19:29:47.271573 1, 0xFFFF, sum = 0
5936 19:29:47.272000 2, 0xFFFF, sum = 0
5937 19:29:47.275046 3, 0xFFFF, sum = 0
5938 19:29:47.275524 4, 0xFFFF, sum = 0
5939 19:29:47.277867 5, 0xFFFF, sum = 0
5940 19:29:47.278380 6, 0xFFFF, sum = 0
5941 19:29:47.281116 7, 0xFFFF, sum = 0
5942 19:29:47.281590 8, 0xFFFF, sum = 0
5943 19:29:47.284459 9, 0xFFFF, sum = 0
5944 19:29:47.284944 10, 0x0, sum = 1
5945 19:29:47.288368 11, 0x0, sum = 2
5946 19:29:47.288941 12, 0x0, sum = 3
5947 19:29:47.291702 13, 0x0, sum = 4
5948 19:29:47.292275 best_step = 11
5949 19:29:47.292651
5950 19:29:47.293001 ==
5951 19:29:47.294481 Dram Type= 6, Freq= 0, CH_1, rank 1
5952 19:29:47.298046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5953 19:29:47.298585 ==
5954 19:29:47.301018 RX Vref Scan: 0
5955 19:29:47.301486
5956 19:29:47.304853 RX Vref 0 -> 0, step: 1
5957 19:29:47.305426
5958 19:29:47.305805 RX Delay -45 -> 252, step: 4
5959 19:29:47.312533 iDelay=203, Bit 0, Center 108 (27 ~ 190) 164
5960 19:29:47.315884 iDelay=203, Bit 1, Center 100 (19 ~ 182) 164
5961 19:29:47.318994 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5962 19:29:47.322233 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5963 19:29:47.325716 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5964 19:29:47.332315 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5965 19:29:47.335930 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5966 19:29:47.339384 iDelay=203, Bit 7, Center 102 (19 ~ 186) 168
5967 19:29:47.342472 iDelay=203, Bit 8, Center 90 (7 ~ 174) 168
5968 19:29:47.345752 iDelay=203, Bit 9, Center 90 (7 ~ 174) 168
5969 19:29:47.352571 iDelay=203, Bit 10, Center 98 (15 ~ 182) 168
5970 19:29:47.355879 iDelay=203, Bit 11, Center 92 (7 ~ 178) 172
5971 19:29:47.358864 iDelay=203, Bit 12, Center 108 (23 ~ 194) 172
5972 19:29:47.361900 iDelay=203, Bit 13, Center 106 (23 ~ 190) 168
5973 19:29:47.365949 iDelay=203, Bit 14, Center 104 (23 ~ 186) 164
5974 19:29:47.372263 iDelay=203, Bit 15, Center 108 (23 ~ 194) 172
5975 19:29:47.372837 ==
5976 19:29:47.375343 Dram Type= 6, Freq= 0, CH_1, rank 1
5977 19:29:47.378975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5978 19:29:47.379452 ==
5979 19:29:47.379824 DQS Delay:
5980 19:29:47.381989 DQS0 = 0, DQS1 = 0
5981 19:29:47.382608 DQM Delay:
5982 19:29:47.385263 DQM0 = 104, DQM1 = 99
5983 19:29:47.385826 DQ Delay:
5984 19:29:47.389371 DQ0 =108, DQ1 =100, DQ2 =94, DQ3 =100
5985 19:29:47.392069 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =102
5986 19:29:47.395067 DQ8 =90, DQ9 =90, DQ10 =98, DQ11 =92
5987 19:29:47.398436 DQ12 =108, DQ13 =106, DQ14 =104, DQ15 =108
5988 19:29:47.398906
5989 19:29:47.399278
5990 19:29:47.408479 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f03, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 407 ps
5991 19:29:47.411900 CH1 RK1: MR19=505, MR18=2F03
5992 19:29:47.414891 CH1_RK1: MR19=0x505, MR18=0x2F03, DQSOSC=407, MR23=63, INC=65, DEC=43
5993 19:29:47.419002 [RxdqsGatingPostProcess] freq 933
5994 19:29:47.425243 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5995 19:29:47.428857 best DQS0 dly(2T, 0.5T) = (0, 10)
5996 19:29:47.431900 best DQS1 dly(2T, 0.5T) = (0, 10)
5997 19:29:47.434798 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5998 19:29:47.438324 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5999 19:29:47.441369 best DQS0 dly(2T, 0.5T) = (0, 10)
6000 19:29:47.445293 best DQS1 dly(2T, 0.5T) = (0, 10)
6001 19:29:47.448376 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6002 19:29:47.451270 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6003 19:29:47.455268 Pre-setting of DQS Precalculation
6004 19:29:47.458130 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6005 19:29:47.465471 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6006 19:29:47.471606 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6007 19:29:47.472169
6008 19:29:47.472541
6009 19:29:47.475431 [Calibration Summary] 1866 Mbps
6010 19:29:47.478601 CH 0, Rank 0
6011 19:29:47.479070 SW Impedance : PASS
6012 19:29:47.481960 DUTY Scan : NO K
6013 19:29:47.485171 ZQ Calibration : PASS
6014 19:29:47.485639 Jitter Meter : NO K
6015 19:29:47.488382 CBT Training : PASS
6016 19:29:47.488956 Write leveling : PASS
6017 19:29:47.491851 RX DQS gating : PASS
6018 19:29:47.495116 RX DQ/DQS(RDDQC) : PASS
6019 19:29:47.495590 TX DQ/DQS : PASS
6020 19:29:47.498585 RX DATLAT : PASS
6021 19:29:47.501480 RX DQ/DQS(Engine): PASS
6022 19:29:47.501952 TX OE : NO K
6023 19:29:47.504635 All Pass.
6024 19:29:47.505118
6025 19:29:47.505503 CH 0, Rank 1
6026 19:29:47.508176 SW Impedance : PASS
6027 19:29:47.508643 DUTY Scan : NO K
6028 19:29:47.511603 ZQ Calibration : PASS
6029 19:29:47.514493 Jitter Meter : NO K
6030 19:29:47.514921 CBT Training : PASS
6031 19:29:47.518030 Write leveling : PASS
6032 19:29:47.521380 RX DQS gating : PASS
6033 19:29:47.521903 RX DQ/DQS(RDDQC) : PASS
6034 19:29:47.524845 TX DQ/DQS : PASS
6035 19:29:47.528290 RX DATLAT : PASS
6036 19:29:47.528852 RX DQ/DQS(Engine): PASS
6037 19:29:47.531361 TX OE : NO K
6038 19:29:47.531866 All Pass.
6039 19:29:47.532253
6040 19:29:47.534490 CH 1, Rank 0
6041 19:29:47.534961 SW Impedance : PASS
6042 19:29:47.538443 DUTY Scan : NO K
6043 19:29:47.541492 ZQ Calibration : PASS
6044 19:29:47.541924 Jitter Meter : NO K
6045 19:29:47.544695 CBT Training : PASS
6046 19:29:47.545167 Write leveling : PASS
6047 19:29:47.547769 RX DQS gating : PASS
6048 19:29:47.551486 RX DQ/DQS(RDDQC) : PASS
6049 19:29:47.551926 TX DQ/DQS : PASS
6050 19:29:47.554828 RX DATLAT : PASS
6051 19:29:47.558081 RX DQ/DQS(Engine): PASS
6052 19:29:47.558539 TX OE : NO K
6053 19:29:47.561543 All Pass.
6054 19:29:47.561966
6055 19:29:47.562361 CH 1, Rank 1
6056 19:29:47.564933 SW Impedance : PASS
6057 19:29:47.565357 DUTY Scan : NO K
6058 19:29:47.568403 ZQ Calibration : PASS
6059 19:29:47.571406 Jitter Meter : NO K
6060 19:29:47.571931 CBT Training : PASS
6061 19:29:47.574463 Write leveling : PASS
6062 19:29:47.578066 RX DQS gating : PASS
6063 19:29:47.578539 RX DQ/DQS(RDDQC) : PASS
6064 19:29:47.581485 TX DQ/DQS : PASS
6065 19:29:47.584300 RX DATLAT : PASS
6066 19:29:47.584742 RX DQ/DQS(Engine): PASS
6067 19:29:47.588421 TX OE : NO K
6068 19:29:47.588947 All Pass.
6069 19:29:47.589291
6070 19:29:47.591389 DramC Write-DBI off
6071 19:29:47.594594 PER_BANK_REFRESH: Hybrid Mode
6072 19:29:47.595023 TX_TRACKING: ON
6073 19:29:47.604635 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6074 19:29:47.607518 [FAST_K] Save calibration result to emmc
6075 19:29:47.610880 dramc_set_vcore_voltage set vcore to 650000
6076 19:29:47.614448 Read voltage for 400, 6
6077 19:29:47.614965 Vio18 = 0
6078 19:29:47.615444 Vcore = 650000
6079 19:29:47.617564 Vdram = 0
6080 19:29:47.618092 Vddq = 0
6081 19:29:47.618484 Vmddr = 0
6082 19:29:47.624219 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6083 19:29:47.627317 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6084 19:29:47.630696 MEM_TYPE=3, freq_sel=20
6085 19:29:47.634102 sv_algorithm_assistance_LP4_800
6086 19:29:47.637421 ============ PULL DRAM RESETB DOWN ============
6087 19:29:47.640943 ========== PULL DRAM RESETB DOWN end =========
6088 19:29:47.647822 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6089 19:29:47.650472 ===================================
6090 19:29:47.650900 LPDDR4 DRAM CONFIGURATION
6091 19:29:47.654289 ===================================
6092 19:29:47.657262 EX_ROW_EN[0] = 0x0
6093 19:29:47.660512 EX_ROW_EN[1] = 0x0
6094 19:29:47.660818 LP4Y_EN = 0x0
6095 19:29:47.664057 WORK_FSP = 0x0
6096 19:29:47.664287 WL = 0x2
6097 19:29:47.666996 RL = 0x2
6098 19:29:47.667182 BL = 0x2
6099 19:29:47.670581 RPST = 0x0
6100 19:29:47.670765 RD_PRE = 0x0
6101 19:29:47.673406 WR_PRE = 0x1
6102 19:29:47.673560 WR_PST = 0x0
6103 19:29:47.677428 DBI_WR = 0x0
6104 19:29:47.677560 DBI_RD = 0x0
6105 19:29:47.680015 OTF = 0x1
6106 19:29:47.683584 ===================================
6107 19:29:47.686864 ===================================
6108 19:29:47.686969 ANA top config
6109 19:29:47.689977 ===================================
6110 19:29:47.693148 DLL_ASYNC_EN = 0
6111 19:29:47.697214 ALL_SLAVE_EN = 1
6112 19:29:47.700351 NEW_RANK_MODE = 1
6113 19:29:47.700437 DLL_IDLE_MODE = 1
6114 19:29:47.703556 LP45_APHY_COMB_EN = 1
6115 19:29:47.706473 TX_ODT_DIS = 1
6116 19:29:47.710199 NEW_8X_MODE = 1
6117 19:29:47.713167 ===================================
6118 19:29:47.716568 ===================================
6119 19:29:47.720094 data_rate = 800
6120 19:29:47.720178 CKR = 1
6121 19:29:47.723481 DQ_P2S_RATIO = 4
6122 19:29:47.726662 ===================================
6123 19:29:47.730364 CA_P2S_RATIO = 4
6124 19:29:47.733174 DQ_CA_OPEN = 0
6125 19:29:47.736715 DQ_SEMI_OPEN = 1
6126 19:29:47.736798 CA_SEMI_OPEN = 1
6127 19:29:47.739846 CA_FULL_RATE = 0
6128 19:29:47.743297 DQ_CKDIV4_EN = 0
6129 19:29:47.746520 CA_CKDIV4_EN = 1
6130 19:29:47.750040 CA_PREDIV_EN = 0
6131 19:29:47.753772 PH8_DLY = 0
6132 19:29:47.753856 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6133 19:29:47.756325 DQ_AAMCK_DIV = 0
6134 19:29:47.760117 CA_AAMCK_DIV = 0
6135 19:29:47.763303 CA_ADMCK_DIV = 4
6136 19:29:47.766463 DQ_TRACK_CA_EN = 0
6137 19:29:47.770088 CA_PICK = 800
6138 19:29:47.773219 CA_MCKIO = 400
6139 19:29:47.773303 MCKIO_SEMI = 400
6140 19:29:47.776606 PLL_FREQ = 3016
6141 19:29:47.780216 DQ_UI_PI_RATIO = 32
6142 19:29:47.783411 CA_UI_PI_RATIO = 32
6143 19:29:47.786322 ===================================
6144 19:29:47.790116 ===================================
6145 19:29:47.793322 memory_type:LPDDR4
6146 19:29:47.793407 GP_NUM : 10
6147 19:29:47.796290 SRAM_EN : 1
6148 19:29:47.799657 MD32_EN : 0
6149 19:29:47.803035 ===================================
6150 19:29:47.803119 [ANA_INIT] >>>>>>>>>>>>>>
6151 19:29:47.806284 <<<<<< [CONFIGURE PHASE]: ANA_TX
6152 19:29:47.809919 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6153 19:29:47.812993 ===================================
6154 19:29:47.816727 data_rate = 800,PCW = 0X7400
6155 19:29:47.819748 ===================================
6156 19:29:47.823467 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6157 19:29:47.829486 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6158 19:29:47.840039 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6159 19:29:47.846247 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6160 19:29:47.849838 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6161 19:29:47.852746 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6162 19:29:47.852831 [ANA_INIT] flow start
6163 19:29:47.856093 [ANA_INIT] PLL >>>>>>>>
6164 19:29:47.859697 [ANA_INIT] PLL <<<<<<<<
6165 19:29:47.859781 [ANA_INIT] MIDPI >>>>>>>>
6166 19:29:47.862674 [ANA_INIT] MIDPI <<<<<<<<
6167 19:29:47.865808 [ANA_INIT] DLL >>>>>>>>
6168 19:29:47.865891 [ANA_INIT] flow end
6169 19:29:47.872684 ============ LP4 DIFF to SE enter ============
6170 19:29:47.875879 ============ LP4 DIFF to SE exit ============
6171 19:29:47.875964 [ANA_INIT] <<<<<<<<<<<<<
6172 19:29:47.879567 [Flow] Enable top DCM control >>>>>
6173 19:29:47.882953 [Flow] Enable top DCM control <<<<<
6174 19:29:47.886421 Enable DLL master slave shuffle
6175 19:29:47.893015 ==============================================================
6176 19:29:47.896218 Gating Mode config
6177 19:29:47.899272 ==============================================================
6178 19:29:47.902478 Config description:
6179 19:29:47.912445 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6180 19:29:47.919573 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6181 19:29:47.922831 SELPH_MODE 0: By rank 1: By Phase
6182 19:29:47.929135 ==============================================================
6183 19:29:47.932769 GAT_TRACK_EN = 0
6184 19:29:47.935887 RX_GATING_MODE = 2
6185 19:29:47.935971 RX_GATING_TRACK_MODE = 2
6186 19:29:47.939559 SELPH_MODE = 1
6187 19:29:47.942528 PICG_EARLY_EN = 1
6188 19:29:47.945872 VALID_LAT_VALUE = 1
6189 19:29:47.952791 ==============================================================
6190 19:29:47.955882 Enter into Gating configuration >>>>
6191 19:29:47.958867 Exit from Gating configuration <<<<
6192 19:29:47.962253 Enter into DVFS_PRE_config >>>>>
6193 19:29:47.972682 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6194 19:29:47.975589 Exit from DVFS_PRE_config <<<<<
6195 19:29:47.979314 Enter into PICG configuration >>>>
6196 19:29:47.982448 Exit from PICG configuration <<<<
6197 19:29:47.985583 [RX_INPUT] configuration >>>>>
6198 19:29:47.988762 [RX_INPUT] configuration <<<<<
6199 19:29:47.992348 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6200 19:29:47.998822 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6201 19:29:48.005582 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6202 19:29:48.011920 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6203 19:29:48.015623 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6204 19:29:48.021986 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6205 19:29:48.025737 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6206 19:29:48.031878 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6207 19:29:48.035205 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6208 19:29:48.038638 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6209 19:29:48.042407 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6210 19:29:48.048623 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6211 19:29:48.051849 ===================================
6212 19:29:48.055416 LPDDR4 DRAM CONFIGURATION
6213 19:29:48.058502 ===================================
6214 19:29:48.058585 EX_ROW_EN[0] = 0x0
6215 19:29:48.061527 EX_ROW_EN[1] = 0x0
6216 19:29:48.061609 LP4Y_EN = 0x0
6217 19:29:48.065141 WORK_FSP = 0x0
6218 19:29:48.065231 WL = 0x2
6219 19:29:48.068161 RL = 0x2
6220 19:29:48.068244 BL = 0x2
6221 19:29:48.071698 RPST = 0x0
6222 19:29:48.071782 RD_PRE = 0x0
6223 19:29:48.074727 WR_PRE = 0x1
6224 19:29:48.074811 WR_PST = 0x0
6225 19:29:48.078165 DBI_WR = 0x0
6226 19:29:48.078248 DBI_RD = 0x0
6227 19:29:48.081711 OTF = 0x1
6228 19:29:48.085157 ===================================
6229 19:29:48.088277 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6230 19:29:48.091982 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6231 19:29:48.098352 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6232 19:29:48.101564 ===================================
6233 19:29:48.101654 LPDDR4 DRAM CONFIGURATION
6234 19:29:48.104579 ===================================
6235 19:29:48.108184 EX_ROW_EN[0] = 0x10
6236 19:29:48.111330 EX_ROW_EN[1] = 0x0
6237 19:29:48.111413 LP4Y_EN = 0x0
6238 19:29:48.115032 WORK_FSP = 0x0
6239 19:29:48.115115 WL = 0x2
6240 19:29:48.118215 RL = 0x2
6241 19:29:48.118297 BL = 0x2
6242 19:29:48.121292 RPST = 0x0
6243 19:29:48.121374 RD_PRE = 0x0
6244 19:29:48.125139 WR_PRE = 0x1
6245 19:29:48.125222 WR_PST = 0x0
6246 19:29:48.128128 DBI_WR = 0x0
6247 19:29:48.128214 DBI_RD = 0x0
6248 19:29:48.131289 OTF = 0x1
6249 19:29:48.134586 ===================================
6250 19:29:48.141413 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6251 19:29:48.144712 nWR fixed to 30
6252 19:29:48.148516 [ModeRegInit_LP4] CH0 RK0
6253 19:29:48.148599 [ModeRegInit_LP4] CH0 RK1
6254 19:29:48.151286 [ModeRegInit_LP4] CH1 RK0
6255 19:29:48.154740 [ModeRegInit_LP4] CH1 RK1
6256 19:29:48.154822 match AC timing 19
6257 19:29:48.161531 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6258 19:29:48.164880 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6259 19:29:48.168283 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6260 19:29:48.174632 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6261 19:29:48.178108 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6262 19:29:48.178192 ==
6263 19:29:48.181604 Dram Type= 6, Freq= 0, CH_0, rank 0
6264 19:29:48.184627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6265 19:29:48.184711 ==
6266 19:29:48.191387 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6267 19:29:48.198142 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6268 19:29:48.201057 [CA 0] Center 36 (8~64) winsize 57
6269 19:29:48.204294 [CA 1] Center 36 (8~64) winsize 57
6270 19:29:48.204378 [CA 2] Center 36 (8~64) winsize 57
6271 19:29:48.207782 [CA 3] Center 36 (8~64) winsize 57
6272 19:29:48.211235 [CA 4] Center 36 (8~64) winsize 57
6273 19:29:48.214822 [CA 5] Center 36 (8~64) winsize 57
6274 19:29:48.214905
6275 19:29:48.217865 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6276 19:29:48.217948
6277 19:29:48.224866 [CATrainingPosCal] consider 1 rank data
6278 19:29:48.224950 u2DelayCellTimex100 = 270/100 ps
6279 19:29:48.231201 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6280 19:29:48.234398 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6281 19:29:48.237556 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6282 19:29:48.240722 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6283 19:29:48.244471 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6284 19:29:48.247817 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6285 19:29:48.247899
6286 19:29:48.250959 CA PerBit enable=1, Macro0, CA PI delay=36
6287 19:29:48.251041
6288 19:29:48.254003 [CBTSetCACLKResult] CA Dly = 36
6289 19:29:48.257703 CS Dly: 1 (0~32)
6290 19:29:48.257786 ==
6291 19:29:48.260934 Dram Type= 6, Freq= 0, CH_0, rank 1
6292 19:29:48.264217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6293 19:29:48.264300 ==
6294 19:29:48.270902 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6295 19:29:48.273950 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6296 19:29:48.277346 [CA 0] Center 36 (8~64) winsize 57
6297 19:29:48.280898 [CA 1] Center 36 (8~64) winsize 57
6298 19:29:48.284190 [CA 2] Center 36 (8~64) winsize 57
6299 19:29:48.287218 [CA 3] Center 36 (8~64) winsize 57
6300 19:29:48.290910 [CA 4] Center 36 (8~64) winsize 57
6301 19:29:48.293969 [CA 5] Center 36 (8~64) winsize 57
6302 19:29:48.294052
6303 19:29:48.297137 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6304 19:29:48.297219
6305 19:29:48.300940 [CATrainingPosCal] consider 2 rank data
6306 19:29:48.304114 u2DelayCellTimex100 = 270/100 ps
6307 19:29:48.307222 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6308 19:29:48.310431 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6309 19:29:48.313787 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6310 19:29:48.320505 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6311 19:29:48.323652 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6312 19:29:48.327105 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6313 19:29:48.327244
6314 19:29:48.330122 CA PerBit enable=1, Macro0, CA PI delay=36
6315 19:29:48.330205
6316 19:29:48.333548 [CBTSetCACLKResult] CA Dly = 36
6317 19:29:48.333631 CS Dly: 1 (0~32)
6318 19:29:48.333696
6319 19:29:48.336888 ----->DramcWriteLeveling(PI) begin...
6320 19:29:48.340747 ==
6321 19:29:48.340829 Dram Type= 6, Freq= 0, CH_0, rank 0
6322 19:29:48.347222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6323 19:29:48.347309 ==
6324 19:29:48.350508 Write leveling (Byte 0): 40 => 8
6325 19:29:48.353473 Write leveling (Byte 1): 40 => 8
6326 19:29:48.353556 DramcWriteLeveling(PI) end<-----
6327 19:29:48.356669
6328 19:29:48.356751 ==
6329 19:29:48.360501 Dram Type= 6, Freq= 0, CH_0, rank 0
6330 19:29:48.363640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6331 19:29:48.363723 ==
6332 19:29:48.366749 [Gating] SW mode calibration
6333 19:29:48.373583 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6334 19:29:48.376583 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6335 19:29:48.383198 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6336 19:29:48.386770 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6337 19:29:48.390121 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6338 19:29:48.396486 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6339 19:29:48.400106 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6340 19:29:48.403259 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6341 19:29:48.409584 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6342 19:29:48.412784 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6343 19:29:48.416440 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6344 19:29:48.419678 Total UI for P1: 0, mck2ui 16
6345 19:29:48.423166 best dqsien dly found for B0: ( 0, 14, 24)
6346 19:29:48.426205 Total UI for P1: 0, mck2ui 16
6347 19:29:48.429403 best dqsien dly found for B1: ( 0, 14, 24)
6348 19:29:48.432812 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6349 19:29:48.439679 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6350 19:29:48.439762
6351 19:29:48.442708 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6352 19:29:48.446063 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6353 19:29:48.449476 [Gating] SW calibration Done
6354 19:29:48.449559 ==
6355 19:29:48.452605 Dram Type= 6, Freq= 0, CH_0, rank 0
6356 19:29:48.456073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6357 19:29:48.456157 ==
6358 19:29:48.459618 RX Vref Scan: 0
6359 19:29:48.459701
6360 19:29:48.459766 RX Vref 0 -> 0, step: 1
6361 19:29:48.459827
6362 19:29:48.462607 RX Delay -410 -> 252, step: 16
6363 19:29:48.466138 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6364 19:29:48.472625 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6365 19:29:48.475823 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6366 19:29:48.479465 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6367 19:29:48.483032 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6368 19:29:48.489318 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6369 19:29:48.492335 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6370 19:29:48.496031 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6371 19:29:48.499463 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6372 19:29:48.505727 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6373 19:29:48.508931 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6374 19:29:48.512721 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6375 19:29:48.515953 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6376 19:29:48.522181 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6377 19:29:48.525540 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6378 19:29:48.529149 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6379 19:29:48.529230 ==
6380 19:29:48.532430 Dram Type= 6, Freq= 0, CH_0, rank 0
6381 19:29:48.539296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6382 19:29:48.539379 ==
6383 19:29:48.539443 DQS Delay:
6384 19:29:48.542678 DQS0 = 27, DQS1 = 35
6385 19:29:48.542759 DQM Delay:
6386 19:29:48.542822 DQM0 = 10, DQM1 = 11
6387 19:29:48.545695 DQ Delay:
6388 19:29:48.548839 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6389 19:29:48.548925 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6390 19:29:48.552711 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6391 19:29:48.555750 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6392 19:29:48.555836
6393 19:29:48.559100
6394 19:29:48.559191 ==
6395 19:29:48.562016 Dram Type= 6, Freq= 0, CH_0, rank 0
6396 19:29:48.565362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6397 19:29:48.565444 ==
6398 19:29:48.565509
6399 19:29:48.565569
6400 19:29:48.568620 TX Vref Scan disable
6401 19:29:48.568702 == TX Byte 0 ==
6402 19:29:48.572165 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6403 19:29:48.578696 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6404 19:29:48.578779 == TX Byte 1 ==
6405 19:29:48.581924 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6406 19:29:48.588733 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6407 19:29:48.588815 ==
6408 19:29:48.591846 Dram Type= 6, Freq= 0, CH_0, rank 0
6409 19:29:48.595160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6410 19:29:48.595243 ==
6411 19:29:48.595307
6412 19:29:48.595368
6413 19:29:48.598518 TX Vref Scan disable
6414 19:29:48.598599 == TX Byte 0 ==
6415 19:29:48.602039 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6416 19:29:48.608468 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6417 19:29:48.608550 == TX Byte 1 ==
6418 19:29:48.611669 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6419 19:29:48.618709 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6420 19:29:48.618791
6421 19:29:48.618856 [DATLAT]
6422 19:29:48.618917 Freq=400, CH0 RK0
6423 19:29:48.621857
6424 19:29:48.621937 DATLAT Default: 0xf
6425 19:29:48.625691 0, 0xFFFF, sum = 0
6426 19:29:48.625775 1, 0xFFFF, sum = 0
6427 19:29:48.628819 2, 0xFFFF, sum = 0
6428 19:29:48.628901 3, 0xFFFF, sum = 0
6429 19:29:48.632007 4, 0xFFFF, sum = 0
6430 19:29:48.632090 5, 0xFFFF, sum = 0
6431 19:29:48.635070 6, 0xFFFF, sum = 0
6432 19:29:48.635153 7, 0xFFFF, sum = 0
6433 19:29:48.638598 8, 0xFFFF, sum = 0
6434 19:29:48.638681 9, 0xFFFF, sum = 0
6435 19:29:48.641581 10, 0xFFFF, sum = 0
6436 19:29:48.641681 11, 0xFFFF, sum = 0
6437 19:29:48.645361 12, 0xFFFF, sum = 0
6438 19:29:48.645444 13, 0x0, sum = 1
6439 19:29:48.648353 14, 0x0, sum = 2
6440 19:29:48.648437 15, 0x0, sum = 3
6441 19:29:48.651613 16, 0x0, sum = 4
6442 19:29:48.651696 best_step = 14
6443 19:29:48.651760
6444 19:29:48.651822 ==
6445 19:29:48.655318 Dram Type= 6, Freq= 0, CH_0, rank 0
6446 19:29:48.661883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6447 19:29:48.661965 ==
6448 19:29:48.662031 RX Vref Scan: 1
6449 19:29:48.662091
6450 19:29:48.664947 RX Vref 0 -> 0, step: 1
6451 19:29:48.665029
6452 19:29:48.668627 RX Delay -311 -> 252, step: 8
6453 19:29:48.668710
6454 19:29:48.671871 Set Vref, RX VrefLevel [Byte0]: 58
6455 19:29:48.674766 [Byte1]: 45
6456 19:29:48.674847
6457 19:29:48.678616 Final RX Vref Byte 0 = 58 to rank0
6458 19:29:48.681489 Final RX Vref Byte 1 = 45 to rank0
6459 19:29:48.684746 Final RX Vref Byte 0 = 58 to rank1
6460 19:29:48.688018 Final RX Vref Byte 1 = 45 to rank1==
6461 19:29:48.691378 Dram Type= 6, Freq= 0, CH_0, rank 0
6462 19:29:48.694791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6463 19:29:48.694872 ==
6464 19:29:48.698430 DQS Delay:
6465 19:29:48.698511 DQS0 = 24, DQS1 = 36
6466 19:29:48.701594 DQM Delay:
6467 19:29:48.701675 DQM0 = 7, DQM1 = 13
6468 19:29:48.704769 DQ Delay:
6469 19:29:48.704850 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6470 19:29:48.708226 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6471 19:29:48.711316 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6472 19:29:48.714608 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6473 19:29:48.714690
6474 19:29:48.714754
6475 19:29:48.725012 [DQSOSCAuto] RK0, (LSB)MR18= 0xcdba, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 384 ps
6476 19:29:48.725098 CH0 RK0: MR19=C0C, MR18=CDBA
6477 19:29:48.731768 CH0_RK0: MR19=0xC0C, MR18=0xCDBA, DQSOSC=384, MR23=63, INC=400, DEC=267
6478 19:29:48.734989 ==
6479 19:29:48.735071 Dram Type= 6, Freq= 0, CH_0, rank 1
6480 19:29:48.741077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6481 19:29:48.741159 ==
6482 19:29:48.744565 [Gating] SW mode calibration
6483 19:29:48.751448 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6484 19:29:48.754664 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6485 19:29:48.761040 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6486 19:29:48.764658 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6487 19:29:48.767701 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6488 19:29:48.774588 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6489 19:29:48.777774 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6490 19:29:48.780952 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6491 19:29:48.787737 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6492 19:29:48.791303 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6493 19:29:48.794542 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6494 19:29:48.797624 Total UI for P1: 0, mck2ui 16
6495 19:29:48.801023 best dqsien dly found for B0: ( 0, 14, 24)
6496 19:29:48.804770 Total UI for P1: 0, mck2ui 16
6497 19:29:48.807991 best dqsien dly found for B1: ( 0, 14, 24)
6498 19:29:48.810961 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6499 19:29:48.814659 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6500 19:29:48.814741
6501 19:29:48.817665 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6502 19:29:48.824579 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6503 19:29:48.824660 [Gating] SW calibration Done
6504 19:29:48.824725 ==
6505 19:29:48.827909 Dram Type= 6, Freq= 0, CH_0, rank 1
6506 19:29:48.834489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6507 19:29:48.834573 ==
6508 19:29:48.834638 RX Vref Scan: 0
6509 19:29:48.834699
6510 19:29:48.837518 RX Vref 0 -> 0, step: 1
6511 19:29:48.837599
6512 19:29:48.841157 RX Delay -410 -> 252, step: 16
6513 19:29:48.844308 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6514 19:29:48.847633 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6515 19:29:48.854262 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6516 19:29:48.857272 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6517 19:29:48.861287 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6518 19:29:48.864480 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6519 19:29:48.870661 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6520 19:29:48.874441 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6521 19:29:48.877302 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6522 19:29:48.880544 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6523 19:29:48.887559 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6524 19:29:48.891273 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6525 19:29:48.894239 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6526 19:29:48.898092 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6527 19:29:48.903898 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6528 19:29:48.907511 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6529 19:29:48.907599 ==
6530 19:29:48.911158 Dram Type= 6, Freq= 0, CH_0, rank 1
6531 19:29:48.914180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6532 19:29:48.914264 ==
6533 19:29:48.917247 DQS Delay:
6534 19:29:48.917329 DQS0 = 27, DQS1 = 35
6535 19:29:48.921037 DQM Delay:
6536 19:29:48.921120 DQM0 = 12, DQM1 = 11
6537 19:29:48.921184 DQ Delay:
6538 19:29:48.924176 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6539 19:29:48.927444 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6540 19:29:48.930713 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6541 19:29:48.934266 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6542 19:29:48.934384
6543 19:29:48.934448
6544 19:29:48.934507 ==
6545 19:29:48.937387 Dram Type= 6, Freq= 0, CH_0, rank 1
6546 19:29:48.944172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6547 19:29:48.944257 ==
6548 19:29:48.944321
6549 19:29:48.944382
6550 19:29:48.944439 TX Vref Scan disable
6551 19:29:48.946939 == TX Byte 0 ==
6552 19:29:48.950422 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6553 19:29:48.953676 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6554 19:29:48.956948 == TX Byte 1 ==
6555 19:29:48.960603 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6556 19:29:48.964148 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6557 19:29:48.964230 ==
6558 19:29:48.966906 Dram Type= 6, Freq= 0, CH_0, rank 1
6559 19:29:48.973734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6560 19:29:48.973817 ==
6561 19:29:48.973881
6562 19:29:48.973942
6563 19:29:48.974000 TX Vref Scan disable
6564 19:29:48.976991 == TX Byte 0 ==
6565 19:29:48.980218 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6566 19:29:48.983571 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6567 19:29:48.987294 == TX Byte 1 ==
6568 19:29:48.990413 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6569 19:29:48.993360 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6570 19:29:48.993443
6571 19:29:48.997025 [DATLAT]
6572 19:29:48.997108 Freq=400, CH0 RK1
6573 19:29:48.997173
6574 19:29:49.000055 DATLAT Default: 0xe
6575 19:29:49.000137 0, 0xFFFF, sum = 0
6576 19:29:49.004125 1, 0xFFFF, sum = 0
6577 19:29:49.004208 2, 0xFFFF, sum = 0
6578 19:29:49.007076 3, 0xFFFF, sum = 0
6579 19:29:49.007159 4, 0xFFFF, sum = 0
6580 19:29:49.010352 5, 0xFFFF, sum = 0
6581 19:29:49.010463 6, 0xFFFF, sum = 0
6582 19:29:49.013603 7, 0xFFFF, sum = 0
6583 19:29:49.013687 8, 0xFFFF, sum = 0
6584 19:29:49.016936 9, 0xFFFF, sum = 0
6585 19:29:49.017019 10, 0xFFFF, sum = 0
6586 19:29:49.020677 11, 0xFFFF, sum = 0
6587 19:29:49.023730 12, 0xFFFF, sum = 0
6588 19:29:49.023814 13, 0x0, sum = 1
6589 19:29:49.023880 14, 0x0, sum = 2
6590 19:29:49.026787 15, 0x0, sum = 3
6591 19:29:49.026869 16, 0x0, sum = 4
6592 19:29:49.030446 best_step = 14
6593 19:29:49.030561
6594 19:29:49.030629 ==
6595 19:29:49.033597 Dram Type= 6, Freq= 0, CH_0, rank 1
6596 19:29:49.036736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6597 19:29:49.036818 ==
6598 19:29:49.039849 RX Vref Scan: 0
6599 19:29:49.039931
6600 19:29:49.039996 RX Vref 0 -> 0, step: 1
6601 19:29:49.040057
6602 19:29:49.043495 RX Delay -311 -> 252, step: 8
6603 19:29:49.051678 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6604 19:29:49.054807 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6605 19:29:49.058043 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6606 19:29:49.061603 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6607 19:29:49.067773 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6608 19:29:49.071283 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6609 19:29:49.074961 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6610 19:29:49.077808 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6611 19:29:49.084784 iDelay=217, Bit 8, Center -32 (-247 ~ 184) 432
6612 19:29:49.087756 iDelay=217, Bit 9, Center -36 (-255 ~ 184) 440
6613 19:29:49.091198 iDelay=217, Bit 10, Center -24 (-239 ~ 192) 432
6614 19:29:49.097727 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6615 19:29:49.100990 iDelay=217, Bit 12, Center -16 (-231 ~ 200) 432
6616 19:29:49.104540 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6617 19:29:49.107603 iDelay=217, Bit 14, Center -16 (-231 ~ 200) 432
6618 19:29:49.114171 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6619 19:29:49.114256 ==
6620 19:29:49.117688 Dram Type= 6, Freq= 0, CH_0, rank 1
6621 19:29:49.121220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6622 19:29:49.121302 ==
6623 19:29:49.121367 DQS Delay:
6624 19:29:49.124156 DQS0 = 24, DQS1 = 36
6625 19:29:49.124237 DQM Delay:
6626 19:29:49.127926 DQM0 = 8, DQM1 = 12
6627 19:29:49.128007 DQ Delay:
6628 19:29:49.130979 DQ0 =8, DQ1 =8, DQ2 =4, DQ3 =8
6629 19:29:49.134726 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6630 19:29:49.137758 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6631 19:29:49.140926 DQ12 =20, DQ13 =16, DQ14 =20, DQ15 =20
6632 19:29:49.141008
6633 19:29:49.141072
6634 19:29:49.147676 [DQSOSCAuto] RK1, (LSB)MR18= 0xb959, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps
6635 19:29:49.150976 CH0 RK1: MR19=C0C, MR18=B959
6636 19:29:49.157795 CH0_RK1: MR19=0xC0C, MR18=0xB959, DQSOSC=386, MR23=63, INC=396, DEC=264
6637 19:29:49.160957 [RxdqsGatingPostProcess] freq 400
6638 19:29:49.167339 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6639 19:29:49.167422 best DQS0 dly(2T, 0.5T) = (0, 10)
6640 19:29:49.170980 best DQS1 dly(2T, 0.5T) = (0, 10)
6641 19:29:49.174167 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6642 19:29:49.177597 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6643 19:29:49.180686 best DQS0 dly(2T, 0.5T) = (0, 10)
6644 19:29:49.184584 best DQS1 dly(2T, 0.5T) = (0, 10)
6645 19:29:49.187912 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6646 19:29:49.190906 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6647 19:29:49.194599 Pre-setting of DQS Precalculation
6648 19:29:49.197763 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6649 19:29:49.201146 ==
6650 19:29:49.201227 Dram Type= 6, Freq= 0, CH_1, rank 0
6651 19:29:49.207328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6652 19:29:49.207410 ==
6653 19:29:49.210563 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6654 19:29:49.217633 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6655 19:29:49.220752 [CA 0] Center 36 (8~64) winsize 57
6656 19:29:49.224192 [CA 1] Center 36 (8~64) winsize 57
6657 19:29:49.227392 [CA 2] Center 36 (8~64) winsize 57
6658 19:29:49.230430 [CA 3] Center 36 (8~64) winsize 57
6659 19:29:49.234026 [CA 4] Center 36 (8~64) winsize 57
6660 19:29:49.237642 [CA 5] Center 36 (8~64) winsize 57
6661 19:29:49.237723
6662 19:29:49.240948 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6663 19:29:49.241030
6664 19:29:49.243770 [CATrainingPosCal] consider 1 rank data
6665 19:29:49.247274 u2DelayCellTimex100 = 270/100 ps
6666 19:29:49.250425 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6667 19:29:49.253770 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6668 19:29:49.257456 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6669 19:29:49.260615 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6670 19:29:49.263757 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6671 19:29:49.270580 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6672 19:29:49.270664
6673 19:29:49.273697 CA PerBit enable=1, Macro0, CA PI delay=36
6674 19:29:49.273778
6675 19:29:49.277632 [CBTSetCACLKResult] CA Dly = 36
6676 19:29:49.277715 CS Dly: 1 (0~32)
6677 19:29:49.277779 ==
6678 19:29:49.280546 Dram Type= 6, Freq= 0, CH_1, rank 1
6679 19:29:49.284043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6680 19:29:49.287042 ==
6681 19:29:49.290248 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6682 19:29:49.296963 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6683 19:29:49.300670 [CA 0] Center 36 (8~64) winsize 57
6684 19:29:49.303748 [CA 1] Center 36 (8~64) winsize 57
6685 19:29:49.306894 [CA 2] Center 36 (8~64) winsize 57
6686 19:29:49.310760 [CA 3] Center 36 (8~64) winsize 57
6687 19:29:49.313726 [CA 4] Center 36 (8~64) winsize 57
6688 19:29:49.317239 [CA 5] Center 36 (8~64) winsize 57
6689 19:29:49.317322
6690 19:29:49.320632 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6691 19:29:49.320714
6692 19:29:49.323581 [CATrainingPosCal] consider 2 rank data
6693 19:29:49.326571 u2DelayCellTimex100 = 270/100 ps
6694 19:29:49.330245 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6695 19:29:49.333271 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6696 19:29:49.336879 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6697 19:29:49.339956 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6698 19:29:49.343114 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6699 19:29:49.347049 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6700 19:29:49.347131
6701 19:29:49.353249 CA PerBit enable=1, Macro0, CA PI delay=36
6702 19:29:49.353332
6703 19:29:49.353396 [CBTSetCACLKResult] CA Dly = 36
6704 19:29:49.356839 CS Dly: 1 (0~32)
6705 19:29:49.356920
6706 19:29:49.360113 ----->DramcWriteLeveling(PI) begin...
6707 19:29:49.360202 ==
6708 19:29:49.363355 Dram Type= 6, Freq= 0, CH_1, rank 0
6709 19:29:49.366543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6710 19:29:49.366625 ==
6711 19:29:49.370236 Write leveling (Byte 0): 40 => 8
6712 19:29:49.373413 Write leveling (Byte 1): 40 => 8
6713 19:29:49.376999 DramcWriteLeveling(PI) end<-----
6714 19:29:49.377081
6715 19:29:49.377145 ==
6716 19:29:49.380034 Dram Type= 6, Freq= 0, CH_1, rank 0
6717 19:29:49.383164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6718 19:29:49.386806 ==
6719 19:29:49.386887 [Gating] SW mode calibration
6720 19:29:49.393224 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6721 19:29:49.399641 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6722 19:29:49.403333 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6723 19:29:49.410425 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6724 19:29:49.413004 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6725 19:29:49.416127 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6726 19:29:49.422988 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6727 19:29:49.426390 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6728 19:29:49.429674 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6729 19:29:49.435991 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6730 19:29:49.439702 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6731 19:29:49.443239 Total UI for P1: 0, mck2ui 16
6732 19:29:49.445965 best dqsien dly found for B0: ( 0, 14, 24)
6733 19:29:49.449120 Total UI for P1: 0, mck2ui 16
6734 19:29:49.452943 best dqsien dly found for B1: ( 0, 14, 24)
6735 19:29:49.456059 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6736 19:29:49.459017 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6737 19:29:49.459098
6738 19:29:49.462362 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6739 19:29:49.465811 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6740 19:29:49.469517 [Gating] SW calibration Done
6741 19:29:49.469598 ==
6742 19:29:49.472450 Dram Type= 6, Freq= 0, CH_1, rank 0
6743 19:29:49.479334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6744 19:29:49.479416 ==
6745 19:29:49.479481 RX Vref Scan: 0
6746 19:29:49.479542
6747 19:29:49.482568 RX Vref 0 -> 0, step: 1
6748 19:29:49.482649
6749 19:29:49.485884 RX Delay -410 -> 252, step: 16
6750 19:29:49.489091 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6751 19:29:49.492287 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6752 19:29:49.495563 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6753 19:29:49.502774 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6754 19:29:49.505723 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6755 19:29:49.508885 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6756 19:29:49.512604 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6757 19:29:49.518988 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6758 19:29:49.522667 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6759 19:29:49.525881 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6760 19:29:49.529053 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6761 19:29:49.535923 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6762 19:29:49.539025 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6763 19:29:49.542198 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6764 19:29:49.545834 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6765 19:29:49.552436 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6766 19:29:49.552518 ==
6767 19:29:49.556076 Dram Type= 6, Freq= 0, CH_1, rank 0
6768 19:29:49.559016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6769 19:29:49.559098 ==
6770 19:29:49.559162 DQS Delay:
6771 19:29:49.562229 DQS0 = 35, DQS1 = 35
6772 19:29:49.562368 DQM Delay:
6773 19:29:49.565372 DQM0 = 17, DQM1 = 13
6774 19:29:49.565452 DQ Delay:
6775 19:29:49.568888 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =16
6776 19:29:49.572244 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6777 19:29:49.575604 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6778 19:29:49.579005 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6779 19:29:49.579086
6780 19:29:49.579150
6781 19:29:49.579208 ==
6782 19:29:49.582102 Dram Type= 6, Freq= 0, CH_1, rank 0
6783 19:29:49.585760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6784 19:29:49.585841 ==
6785 19:29:49.588887
6786 19:29:49.588967
6787 19:29:49.589031 TX Vref Scan disable
6788 19:29:49.592493 == TX Byte 0 ==
6789 19:29:49.595754 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6790 19:29:49.599007 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6791 19:29:49.602466 == TX Byte 1 ==
6792 19:29:49.605287 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6793 19:29:49.609017 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6794 19:29:49.609098 ==
6795 19:29:49.612435 Dram Type= 6, Freq= 0, CH_1, rank 0
6796 19:29:49.615678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6797 19:29:49.618909 ==
6798 19:29:49.618990
6799 19:29:49.619053
6800 19:29:49.619113 TX Vref Scan disable
6801 19:29:49.622114 == TX Byte 0 ==
6802 19:29:49.625759 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6803 19:29:49.628792 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6804 19:29:49.631966 == TX Byte 1 ==
6805 19:29:49.635643 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6806 19:29:49.638714 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6807 19:29:49.638795
6808 19:29:49.638860 [DATLAT]
6809 19:29:49.642498 Freq=400, CH1 RK0
6810 19:29:49.642579
6811 19:29:49.645324 DATLAT Default: 0xf
6812 19:29:49.645405 0, 0xFFFF, sum = 0
6813 19:29:49.649059 1, 0xFFFF, sum = 0
6814 19:29:49.649142 2, 0xFFFF, sum = 0
6815 19:29:49.652310 3, 0xFFFF, sum = 0
6816 19:29:49.652393 4, 0xFFFF, sum = 0
6817 19:29:49.655261 5, 0xFFFF, sum = 0
6818 19:29:49.655344 6, 0xFFFF, sum = 0
6819 19:29:49.658888 7, 0xFFFF, sum = 0
6820 19:29:49.658970 8, 0xFFFF, sum = 0
6821 19:29:49.662223 9, 0xFFFF, sum = 0
6822 19:29:49.662312 10, 0xFFFF, sum = 0
6823 19:29:49.665636 11, 0xFFFF, sum = 0
6824 19:29:49.665718 12, 0xFFFF, sum = 0
6825 19:29:49.668648 13, 0x0, sum = 1
6826 19:29:49.668730 14, 0x0, sum = 2
6827 19:29:49.671997 15, 0x0, sum = 3
6828 19:29:49.672082 16, 0x0, sum = 4
6829 19:29:49.675629 best_step = 14
6830 19:29:49.675709
6831 19:29:49.675773 ==
6832 19:29:49.678932 Dram Type= 6, Freq= 0, CH_1, rank 0
6833 19:29:49.681923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6834 19:29:49.682005 ==
6835 19:29:49.685136 RX Vref Scan: 1
6836 19:29:49.685217
6837 19:29:49.685280 RX Vref 0 -> 0, step: 1
6838 19:29:49.685341
6839 19:29:49.689019 RX Delay -311 -> 252, step: 8
6840 19:29:49.689099
6841 19:29:49.692100 Set Vref, RX VrefLevel [Byte0]: 52
6842 19:29:49.695357 [Byte1]: 47
6843 19:29:49.699241
6844 19:29:49.699322 Final RX Vref Byte 0 = 52 to rank0
6845 19:29:49.702693 Final RX Vref Byte 1 = 47 to rank0
6846 19:29:49.706478 Final RX Vref Byte 0 = 52 to rank1
6847 19:29:49.709691 Final RX Vref Byte 1 = 47 to rank1==
6848 19:29:49.712448 Dram Type= 6, Freq= 0, CH_1, rank 0
6849 19:29:49.719640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6850 19:29:49.719722 ==
6851 19:29:49.719787 DQS Delay:
6852 19:29:49.722598 DQS0 = 32, DQS1 = 32
6853 19:29:49.722679 DQM Delay:
6854 19:29:49.722743 DQM0 = 14, DQM1 = 11
6855 19:29:49.725886 DQ Delay:
6856 19:29:49.729406 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6857 19:29:49.732697 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =12
6858 19:29:49.732778 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6859 19:29:49.735939 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =20
6860 19:29:49.738992
6861 19:29:49.739072
6862 19:29:49.745805 [DQSOSCAuto] RK0, (LSB)MR18= 0x94cb, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6863 19:29:49.749346 CH1 RK0: MR19=C0C, MR18=94CB
6864 19:29:49.755613 CH1_RK0: MR19=0xC0C, MR18=0x94CB, DQSOSC=384, MR23=63, INC=400, DEC=267
6865 19:29:49.755696 ==
6866 19:29:49.758961 Dram Type= 6, Freq= 0, CH_1, rank 1
6867 19:29:49.762639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6868 19:29:49.762723 ==
6869 19:29:49.765698 [Gating] SW mode calibration
6870 19:29:49.772155 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6871 19:29:49.779110 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6872 19:29:49.782510 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6873 19:29:49.785407 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6874 19:29:49.792457 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6875 19:29:49.795419 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6876 19:29:49.798937 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6877 19:29:49.805730 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6878 19:29:49.809042 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6879 19:29:49.812521 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6880 19:29:49.818874 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6881 19:29:49.818961 Total UI for P1: 0, mck2ui 16
6882 19:29:49.821943 best dqsien dly found for B0: ( 0, 14, 24)
6883 19:29:49.825714 Total UI for P1: 0, mck2ui 16
6884 19:29:49.828761 best dqsien dly found for B1: ( 0, 14, 24)
6885 19:29:49.835320 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6886 19:29:49.838629 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6887 19:29:49.838712
6888 19:29:49.842270 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6889 19:29:49.845227 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6890 19:29:49.849019 [Gating] SW calibration Done
6891 19:29:49.849103 ==
6892 19:29:49.851895 Dram Type= 6, Freq= 0, CH_1, rank 1
6893 19:29:49.855408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6894 19:29:49.855498 ==
6895 19:29:49.858708 RX Vref Scan: 0
6896 19:29:49.858789
6897 19:29:49.858852 RX Vref 0 -> 0, step: 1
6898 19:29:49.858912
6899 19:29:49.862231 RX Delay -410 -> 252, step: 16
6900 19:29:49.868726 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6901 19:29:49.871955 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6902 19:29:49.875042 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6903 19:29:49.878803 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6904 19:29:49.885212 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6905 19:29:49.888371 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6906 19:29:49.891651 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6907 19:29:49.894790 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6908 19:29:49.898495 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6909 19:29:49.905118 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6910 19:29:49.908656 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6911 19:29:49.911618 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6912 19:29:49.918233 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6913 19:29:49.921709 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6914 19:29:49.925014 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6915 19:29:49.928495 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6916 19:29:49.928577 ==
6917 19:29:49.931523 Dram Type= 6, Freq= 0, CH_1, rank 1
6918 19:29:49.938240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6919 19:29:49.938362 ==
6920 19:29:49.938429 DQS Delay:
6921 19:29:49.941323 DQS0 = 35, DQS1 = 35
6922 19:29:49.941404 DQM Delay:
6923 19:29:49.944898 DQM0 = 18, DQM1 = 13
6924 19:29:49.944979 DQ Delay:
6925 19:29:49.948477 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6926 19:29:49.951943 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6927 19:29:49.954727 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6928 19:29:49.957953 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6929 19:29:49.958035
6930 19:29:49.958099
6931 19:29:49.958158 ==
6932 19:29:49.961682 Dram Type= 6, Freq= 0, CH_1, rank 1
6933 19:29:49.964642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6934 19:29:49.964724 ==
6935 19:29:49.964789
6936 19:29:49.964849
6937 19:29:49.968304 TX Vref Scan disable
6938 19:29:49.968386 == TX Byte 0 ==
6939 19:29:49.971935 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6940 19:29:49.978416 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6941 19:29:49.978497 == TX Byte 1 ==
6942 19:29:49.981646 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6943 19:29:49.988052 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6944 19:29:49.988134 ==
6945 19:29:49.991336 Dram Type= 6, Freq= 0, CH_1, rank 1
6946 19:29:49.994947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6947 19:29:49.995029 ==
6948 19:29:49.995095
6949 19:29:49.995154
6950 19:29:49.998126 TX Vref Scan disable
6951 19:29:49.998207 == TX Byte 0 ==
6952 19:29:50.005106 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6953 19:29:50.008012 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6954 19:29:50.008093 == TX Byte 1 ==
6955 19:29:50.014265 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6956 19:29:50.017784 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6957 19:29:50.017865
6958 19:29:50.017930 [DATLAT]
6959 19:29:50.021401 Freq=400, CH1 RK1
6960 19:29:50.021483
6961 19:29:50.021546 DATLAT Default: 0xe
6962 19:29:50.024400 0, 0xFFFF, sum = 0
6963 19:29:50.024483 1, 0xFFFF, sum = 0
6964 19:29:50.028259 2, 0xFFFF, sum = 0
6965 19:29:50.028341 3, 0xFFFF, sum = 0
6966 19:29:50.031360 4, 0xFFFF, sum = 0
6967 19:29:50.031442 5, 0xFFFF, sum = 0
6968 19:29:50.034616 6, 0xFFFF, sum = 0
6969 19:29:50.034698 7, 0xFFFF, sum = 0
6970 19:29:50.038247 8, 0xFFFF, sum = 0
6971 19:29:50.038334 9, 0xFFFF, sum = 0
6972 19:29:50.041080 10, 0xFFFF, sum = 0
6973 19:29:50.041163 11, 0xFFFF, sum = 0
6974 19:29:50.044454 12, 0xFFFF, sum = 0
6975 19:29:50.044536 13, 0x0, sum = 1
6976 19:29:50.048054 14, 0x0, sum = 2
6977 19:29:50.048137 15, 0x0, sum = 3
6978 19:29:50.051109 16, 0x0, sum = 4
6979 19:29:50.051191 best_step = 14
6980 19:29:50.051255
6981 19:29:50.051314 ==
6982 19:29:50.054946 Dram Type= 6, Freq= 0, CH_1, rank 1
6983 19:29:50.061057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6984 19:29:50.061147 ==
6985 19:29:50.061213 RX Vref Scan: 0
6986 19:29:50.061273
6987 19:29:50.064362 RX Vref 0 -> 0, step: 1
6988 19:29:50.064444
6989 19:29:50.067660 RX Delay -311 -> 252, step: 8
6990 19:29:50.074475 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6991 19:29:50.077677 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6992 19:29:50.081148 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6993 19:29:50.084879 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6994 19:29:50.091332 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6995 19:29:50.094633 iDelay=217, Bit 5, Center -4 (-223 ~ 216) 440
6996 19:29:50.097704 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6997 19:29:50.100969 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
6998 19:29:50.104643 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6999 19:29:50.110943 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
7000 19:29:50.114783 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
7001 19:29:50.117602 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
7002 19:29:50.124770 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
7003 19:29:50.128037 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
7004 19:29:50.131007 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
7005 19:29:50.134235 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
7006 19:29:50.134341 ==
7007 19:29:50.138056 Dram Type= 6, Freq= 0, CH_1, rank 1
7008 19:29:50.144506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7009 19:29:50.144588 ==
7010 19:29:50.144653 DQS Delay:
7011 19:29:50.148057 DQS0 = 28, DQS1 = 32
7012 19:29:50.148139 DQM Delay:
7013 19:29:50.148204 DQM0 = 10, DQM1 = 11
7014 19:29:50.150878 DQ Delay:
7015 19:29:50.154139 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
7016 19:29:50.157681 DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =8
7017 19:29:50.157763 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
7018 19:29:50.160908 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
7019 19:29:50.164486
7020 19:29:50.164567
7021 19:29:50.171257 [DQSOSCAuto] RK1, (LSB)MR18= 0xc95a, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 384 ps
7022 19:29:50.174198 CH1 RK1: MR19=C0C, MR18=C95A
7023 19:29:50.181373 CH1_RK1: MR19=0xC0C, MR18=0xC95A, DQSOSC=384, MR23=63, INC=400, DEC=267
7024 19:29:50.184603 [RxdqsGatingPostProcess] freq 400
7025 19:29:50.187571 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7026 19:29:50.191043 best DQS0 dly(2T, 0.5T) = (0, 10)
7027 19:29:50.194226 best DQS1 dly(2T, 0.5T) = (0, 10)
7028 19:29:50.197486 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7029 19:29:50.201045 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7030 19:29:50.204064 best DQS0 dly(2T, 0.5T) = (0, 10)
7031 19:29:50.207277 best DQS1 dly(2T, 0.5T) = (0, 10)
7032 19:29:50.210993 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7033 19:29:50.214260 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7034 19:29:50.217374 Pre-setting of DQS Precalculation
7035 19:29:50.220651 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7036 19:29:50.227313 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7037 19:29:50.237362 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7038 19:29:50.237448
7039 19:29:50.237512
7040 19:29:50.240337 [Calibration Summary] 800 Mbps
7041 19:29:50.240422 CH 0, Rank 0
7042 19:29:50.244075 SW Impedance : PASS
7043 19:29:50.244156 DUTY Scan : NO K
7044 19:29:50.247279 ZQ Calibration : PASS
7045 19:29:50.250284 Jitter Meter : NO K
7046 19:29:50.250404 CBT Training : PASS
7047 19:29:50.254085 Write leveling : PASS
7048 19:29:50.257158 RX DQS gating : PASS
7049 19:29:50.257240 RX DQ/DQS(RDDQC) : PASS
7050 19:29:50.260623 TX DQ/DQS : PASS
7051 19:29:50.260707 RX DATLAT : PASS
7052 19:29:50.263975 RX DQ/DQS(Engine): PASS
7053 19:29:50.266899 TX OE : NO K
7054 19:29:50.266981 All Pass.
7055 19:29:50.267046
7056 19:29:50.267106 CH 0, Rank 1
7057 19:29:50.270354 SW Impedance : PASS
7058 19:29:50.273641 DUTY Scan : NO K
7059 19:29:50.273723 ZQ Calibration : PASS
7060 19:29:50.276835 Jitter Meter : NO K
7061 19:29:50.280495 CBT Training : PASS
7062 19:29:50.280576 Write leveling : NO K
7063 19:29:50.283873 RX DQS gating : PASS
7064 19:29:50.287111 RX DQ/DQS(RDDQC) : PASS
7065 19:29:50.287192 TX DQ/DQS : PASS
7066 19:29:50.290131 RX DATLAT : PASS
7067 19:29:50.293425 RX DQ/DQS(Engine): PASS
7068 19:29:50.293506 TX OE : NO K
7069 19:29:50.297133 All Pass.
7070 19:29:50.297215
7071 19:29:50.297278 CH 1, Rank 0
7072 19:29:50.300435 SW Impedance : PASS
7073 19:29:50.300516 DUTY Scan : NO K
7074 19:29:50.303468 ZQ Calibration : PASS
7075 19:29:50.306948 Jitter Meter : NO K
7076 19:29:50.307030 CBT Training : PASS
7077 19:29:50.310118 Write leveling : PASS
7078 19:29:50.310199 RX DQS gating : PASS
7079 19:29:50.313628 RX DQ/DQS(RDDQC) : PASS
7080 19:29:50.316840 TX DQ/DQS : PASS
7081 19:29:50.316926 RX DATLAT : PASS
7082 19:29:50.320276 RX DQ/DQS(Engine): PASS
7083 19:29:50.323205 TX OE : NO K
7084 19:29:50.323308 All Pass.
7085 19:29:50.323391
7086 19:29:50.323450 CH 1, Rank 1
7087 19:29:50.327060 SW Impedance : PASS
7088 19:29:50.330148 DUTY Scan : NO K
7089 19:29:50.330228 ZQ Calibration : PASS
7090 19:29:50.333424 Jitter Meter : NO K
7091 19:29:50.337267 CBT Training : PASS
7092 19:29:50.337348 Write leveling : NO K
7093 19:29:50.340347 RX DQS gating : PASS
7094 19:29:50.343345 RX DQ/DQS(RDDQC) : PASS
7095 19:29:50.343421 TX DQ/DQS : PASS
7096 19:29:50.346664 RX DATLAT : PASS
7097 19:29:50.350011 RX DQ/DQS(Engine): PASS
7098 19:29:50.350088 TX OE : NO K
7099 19:29:50.350152 All Pass.
7100 19:29:50.353634
7101 19:29:50.353731 DramC Write-DBI off
7102 19:29:50.356718 PER_BANK_REFRESH: Hybrid Mode
7103 19:29:50.356795 TX_TRACKING: ON
7104 19:29:50.366871 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7105 19:29:50.370265 [FAST_K] Save calibration result to emmc
7106 19:29:50.373239 dramc_set_vcore_voltage set vcore to 725000
7107 19:29:50.376797 Read voltage for 1600, 0
7108 19:29:50.376878 Vio18 = 0
7109 19:29:50.379845 Vcore = 725000
7110 19:29:50.379930 Vdram = 0
7111 19:29:50.379995 Vddq = 0
7112 19:29:50.380056 Vmddr = 0
7113 19:29:50.386445 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7114 19:29:50.393492 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7115 19:29:50.393576 MEM_TYPE=3, freq_sel=13
7116 19:29:50.396438 sv_algorithm_assistance_LP4_3733
7117 19:29:50.399955 ============ PULL DRAM RESETB DOWN ============
7118 19:29:50.406242 ========== PULL DRAM RESETB DOWN end =========
7119 19:29:50.410066 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7120 19:29:50.413107 ===================================
7121 19:29:50.417249 LPDDR4 DRAM CONFIGURATION
7122 19:29:50.419626 ===================================
7123 19:29:50.419708 EX_ROW_EN[0] = 0x0
7124 19:29:50.423485 EX_ROW_EN[1] = 0x0
7125 19:29:50.423567 LP4Y_EN = 0x0
7126 19:29:50.426783 WORK_FSP = 0x1
7127 19:29:50.426864 WL = 0x5
7128 19:29:50.429653 RL = 0x5
7129 19:29:50.432921 BL = 0x2
7130 19:29:50.433003 RPST = 0x0
7131 19:29:50.436552 RD_PRE = 0x0
7132 19:29:50.436633 WR_PRE = 0x1
7133 19:29:50.439746 WR_PST = 0x1
7134 19:29:50.439826 DBI_WR = 0x0
7135 19:29:50.443009 DBI_RD = 0x0
7136 19:29:50.443091 OTF = 0x1
7137 19:29:50.446671 ===================================
7138 19:29:50.449804 ===================================
7139 19:29:50.452930 ANA top config
7140 19:29:50.456398 ===================================
7141 19:29:50.456511 DLL_ASYNC_EN = 0
7142 19:29:50.460045 ALL_SLAVE_EN = 0
7143 19:29:50.463375 NEW_RANK_MODE = 1
7144 19:29:50.466400 DLL_IDLE_MODE = 1
7145 19:29:50.466510 LP45_APHY_COMB_EN = 1
7146 19:29:50.469666 TX_ODT_DIS = 0
7147 19:29:50.472863 NEW_8X_MODE = 1
7148 19:29:50.476391 ===================================
7149 19:29:50.479741 ===================================
7150 19:29:50.483236 data_rate = 3200
7151 19:29:50.486178 CKR = 1
7152 19:29:50.489750 DQ_P2S_RATIO = 8
7153 19:29:50.492930 ===================================
7154 19:29:50.493012 CA_P2S_RATIO = 8
7155 19:29:50.496438 DQ_CA_OPEN = 0
7156 19:29:50.499221 DQ_SEMI_OPEN = 0
7157 19:29:50.503012 CA_SEMI_OPEN = 0
7158 19:29:50.506231 CA_FULL_RATE = 0
7159 19:29:50.509444 DQ_CKDIV4_EN = 0
7160 19:29:50.509525 CA_CKDIV4_EN = 0
7161 19:29:50.512393 CA_PREDIV_EN = 0
7162 19:29:50.516223 PH8_DLY = 12
7163 19:29:50.519646 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7164 19:29:50.522377 DQ_AAMCK_DIV = 4
7165 19:29:50.525601 CA_AAMCK_DIV = 4
7166 19:29:50.525680 CA_ADMCK_DIV = 4
7167 19:29:50.529446 DQ_TRACK_CA_EN = 0
7168 19:29:50.532784 CA_PICK = 1600
7169 19:29:50.535998 CA_MCKIO = 1600
7170 19:29:50.539614 MCKIO_SEMI = 0
7171 19:29:50.542944 PLL_FREQ = 3068
7172 19:29:50.545816 DQ_UI_PI_RATIO = 32
7173 19:29:50.545900 CA_UI_PI_RATIO = 0
7174 19:29:50.549000 ===================================
7175 19:29:50.552359 ===================================
7176 19:29:50.555938 memory_type:LPDDR4
7177 19:29:50.558982 GP_NUM : 10
7178 19:29:50.559069 SRAM_EN : 1
7179 19:29:50.562626 MD32_EN : 0
7180 19:29:50.565373 ===================================
7181 19:29:50.568712 [ANA_INIT] >>>>>>>>>>>>>>
7182 19:29:50.572300 <<<<<< [CONFIGURE PHASE]: ANA_TX
7183 19:29:50.575518 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7184 19:29:50.579427 ===================================
7185 19:29:50.579507 data_rate = 3200,PCW = 0X7600
7186 19:29:50.582683 ===================================
7187 19:29:50.585604 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7188 19:29:50.592388 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7189 19:29:50.599082 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7190 19:29:50.602399 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7191 19:29:50.606122 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7192 19:29:50.608885 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7193 19:29:50.612300 [ANA_INIT] flow start
7194 19:29:50.615573 [ANA_INIT] PLL >>>>>>>>
7195 19:29:50.615654 [ANA_INIT] PLL <<<<<<<<
7196 19:29:50.618689 [ANA_INIT] MIDPI >>>>>>>>
7197 19:29:50.621905 [ANA_INIT] MIDPI <<<<<<<<
7198 19:29:50.622010 [ANA_INIT] DLL >>>>>>>>
7199 19:29:50.625449 [ANA_INIT] DLL <<<<<<<<
7200 19:29:50.628786 [ANA_INIT] flow end
7201 19:29:50.632567 ============ LP4 DIFF to SE enter ============
7202 19:29:50.635672 ============ LP4 DIFF to SE exit ============
7203 19:29:50.638894 [ANA_INIT] <<<<<<<<<<<<<
7204 19:29:50.642492 [Flow] Enable top DCM control >>>>>
7205 19:29:50.645575 [Flow] Enable top DCM control <<<<<
7206 19:29:50.648684 Enable DLL master slave shuffle
7207 19:29:50.651840 ==============================================================
7208 19:29:50.655605 Gating Mode config
7209 19:29:50.661698 ==============================================================
7210 19:29:50.661777 Config description:
7211 19:29:50.672239 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7212 19:29:50.678802 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7213 19:29:50.681836 SELPH_MODE 0: By rank 1: By Phase
7214 19:29:50.688795 ==============================================================
7215 19:29:50.691911 GAT_TRACK_EN = 1
7216 19:29:50.694904 RX_GATING_MODE = 2
7217 19:29:50.698597 RX_GATING_TRACK_MODE = 2
7218 19:29:50.701906 SELPH_MODE = 1
7219 19:29:50.705413 PICG_EARLY_EN = 1
7220 19:29:50.708577 VALID_LAT_VALUE = 1
7221 19:29:50.711598 ==============================================================
7222 19:29:50.715075 Enter into Gating configuration >>>>
7223 19:29:50.718048 Exit from Gating configuration <<<<
7224 19:29:50.721569 Enter into DVFS_PRE_config >>>>>
7225 19:29:50.731731 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7226 19:29:50.735168 Exit from DVFS_PRE_config <<<<<
7227 19:29:50.738684 Enter into PICG configuration >>>>
7228 19:29:50.741744 Exit from PICG configuration <<<<
7229 19:29:50.745137 [RX_INPUT] configuration >>>>>
7230 19:29:50.748075 [RX_INPUT] configuration <<<<<
7231 19:29:50.755155 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7232 19:29:50.758281 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7233 19:29:50.765262 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7234 19:29:50.771568 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7235 19:29:50.777883 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7236 19:29:50.784753 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7237 19:29:50.788296 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7238 19:29:50.791670 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7239 19:29:50.794550 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7240 19:29:50.801254 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7241 19:29:50.805175 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7242 19:29:50.808249 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7243 19:29:50.811341 ===================================
7244 19:29:50.814698 LPDDR4 DRAM CONFIGURATION
7245 19:29:50.818209 ===================================
7246 19:29:50.818316 EX_ROW_EN[0] = 0x0
7247 19:29:50.821523 EX_ROW_EN[1] = 0x0
7248 19:29:50.824780 LP4Y_EN = 0x0
7249 19:29:50.824862 WORK_FSP = 0x1
7250 19:29:50.828002 WL = 0x5
7251 19:29:50.828083 RL = 0x5
7252 19:29:50.831212 BL = 0x2
7253 19:29:50.831293 RPST = 0x0
7254 19:29:50.834752 RD_PRE = 0x0
7255 19:29:50.834833 WR_PRE = 0x1
7256 19:29:50.837589 WR_PST = 0x1
7257 19:29:50.837670 DBI_WR = 0x0
7258 19:29:50.841266 DBI_RD = 0x0
7259 19:29:50.841347 OTF = 0x1
7260 19:29:50.844766 ===================================
7261 19:29:50.847679 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7262 19:29:50.854184 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7263 19:29:50.857953 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7264 19:29:50.861229 ===================================
7265 19:29:50.864333 LPDDR4 DRAM CONFIGURATION
7266 19:29:50.867435 ===================================
7267 19:29:50.867517 EX_ROW_EN[0] = 0x10
7268 19:29:50.871211 EX_ROW_EN[1] = 0x0
7269 19:29:50.871319 LP4Y_EN = 0x0
7270 19:29:50.874573 WORK_FSP = 0x1
7271 19:29:50.874655 WL = 0x5
7272 19:29:50.877704 RL = 0x5
7273 19:29:50.881096 BL = 0x2
7274 19:29:50.881177 RPST = 0x0
7275 19:29:50.884591 RD_PRE = 0x0
7276 19:29:50.884672 WR_PRE = 0x1
7277 19:29:50.887795 WR_PST = 0x1
7278 19:29:50.887876 DBI_WR = 0x0
7279 19:29:50.890996 DBI_RD = 0x0
7280 19:29:50.891077 OTF = 0x1
7281 19:29:50.894161 ===================================
7282 19:29:50.901770 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7283 19:29:50.901853 ==
7284 19:29:50.904110 Dram Type= 6, Freq= 0, CH_0, rank 0
7285 19:29:50.907776 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7286 19:29:50.907859 ==
7287 19:29:50.910888 [Duty_Offset_Calibration]
7288 19:29:50.914450 B0:2 B1:1 CA:1
7289 19:29:50.914532
7290 19:29:50.917198 [DutyScan_Calibration_Flow] k_type=0
7291 19:29:50.926069
7292 19:29:50.926153 ==CLK 0==
7293 19:29:50.929334 Final CLK duty delay cell = 0
7294 19:29:50.932371 [0] MAX Duty = 5156%(X100), DQS PI = 22
7295 19:29:50.935968 [0] MIN Duty = 4875%(X100), DQS PI = 0
7296 19:29:50.936050 [0] AVG Duty = 5015%(X100)
7297 19:29:50.939306
7298 19:29:50.939387 CH0 CLK Duty spec in!! Max-Min= 281%
7299 19:29:50.945723 [DutyScan_Calibration_Flow] ====Done====
7300 19:29:50.945805
7301 19:29:50.948765 [DutyScan_Calibration_Flow] k_type=1
7302 19:29:50.964878
7303 19:29:50.964965 ==DQS 0 ==
7304 19:29:50.968493 Final DQS duty delay cell = -4
7305 19:29:50.971713 [-4] MAX Duty = 5125%(X100), DQS PI = 26
7306 19:29:50.975076 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7307 19:29:50.978165 [-4] AVG Duty = 4891%(X100)
7308 19:29:50.978272
7309 19:29:50.978389 ==DQS 1 ==
7310 19:29:50.981280 Final DQS duty delay cell = 0
7311 19:29:50.985076 [0] MAX Duty = 5218%(X100), DQS PI = 22
7312 19:29:50.988157 [0] MIN Duty = 5031%(X100), DQS PI = 52
7313 19:29:50.991443 [0] AVG Duty = 5124%(X100)
7314 19:29:50.991525
7315 19:29:50.995207 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7316 19:29:50.995288
7317 19:29:50.998445 CH0 DQS 1 Duty spec in!! Max-Min= 187%
7318 19:29:51.001559 [DutyScan_Calibration_Flow] ====Done====
7319 19:29:51.001641
7320 19:29:51.004668 [DutyScan_Calibration_Flow] k_type=3
7321 19:29:51.021875
7322 19:29:51.021968 ==DQM 0 ==
7323 19:29:51.024884 Final DQM duty delay cell = 0
7324 19:29:51.027948 [0] MAX Duty = 5187%(X100), DQS PI = 28
7325 19:29:51.031778 [0] MIN Duty = 4875%(X100), DQS PI = 60
7326 19:29:51.034601 [0] AVG Duty = 5031%(X100)
7327 19:29:51.034709
7328 19:29:51.034802 ==DQM 1 ==
7329 19:29:51.038045 Final DQM duty delay cell = -4
7330 19:29:51.041578 [-4] MAX Duty = 4938%(X100), DQS PI = 0
7331 19:29:51.045008 [-4] MIN Duty = 4813%(X100), DQS PI = 12
7332 19:29:51.048155 [-4] AVG Duty = 4875%(X100)
7333 19:29:51.048237
7334 19:29:51.051472 CH0 DQM 0 Duty spec in!! Max-Min= 312%
7335 19:29:51.051555
7336 19:29:51.054698 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7337 19:29:51.057884 [DutyScan_Calibration_Flow] ====Done====
7338 19:29:51.057966
7339 19:29:51.061186 [DutyScan_Calibration_Flow] k_type=2
7340 19:29:51.078897
7341 19:29:51.078984 ==DQ 0 ==
7342 19:29:51.082266 Final DQ duty delay cell = 0
7343 19:29:51.085669 [0] MAX Duty = 5062%(X100), DQS PI = 26
7344 19:29:51.089052 [0] MIN Duty = 4907%(X100), DQS PI = 0
7345 19:29:51.089135 [0] AVG Duty = 4984%(X100)
7346 19:29:51.092236
7347 19:29:51.092316 ==DQ 1 ==
7348 19:29:51.095491 Final DQ duty delay cell = 0
7349 19:29:51.098824 [0] MAX Duty = 5124%(X100), DQS PI = 22
7350 19:29:51.102042 [0] MIN Duty = 4907%(X100), DQS PI = 34
7351 19:29:51.102123 [0] AVG Duty = 5015%(X100)
7352 19:29:51.105558
7353 19:29:51.108655 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7354 19:29:51.108736
7355 19:29:51.112675 CH0 DQ 1 Duty spec in!! Max-Min= 217%
7356 19:29:51.115584 [DutyScan_Calibration_Flow] ====Done====
7357 19:29:51.115666 ==
7358 19:29:51.119214 Dram Type= 6, Freq= 0, CH_1, rank 0
7359 19:29:51.122043 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7360 19:29:51.122124 ==
7361 19:29:51.125502 [Duty_Offset_Calibration]
7362 19:29:51.125584 B0:1 B1:0 CA:0
7363 19:29:51.125648
7364 19:29:51.128573 [DutyScan_Calibration_Flow] k_type=0
7365 19:29:51.138465
7366 19:29:51.138547 ==CLK 0==
7367 19:29:51.142029 Final CLK duty delay cell = -4
7368 19:29:51.145142 [-4] MAX Duty = 4969%(X100), DQS PI = 24
7369 19:29:51.148607 [-4] MIN Duty = 4844%(X100), DQS PI = 50
7370 19:29:51.152227 [-4] AVG Duty = 4906%(X100)
7371 19:29:51.152307
7372 19:29:51.154812 CH1 CLK Duty spec in!! Max-Min= 125%
7373 19:29:51.158668 [DutyScan_Calibration_Flow] ====Done====
7374 19:29:51.158749
7375 19:29:51.161618 [DutyScan_Calibration_Flow] k_type=1
7376 19:29:51.178447
7377 19:29:51.178529 ==DQS 0 ==
7378 19:29:51.181965 Final DQS duty delay cell = 0
7379 19:29:51.185080 [0] MAX Duty = 5094%(X100), DQS PI = 34
7380 19:29:51.188612 [0] MIN Duty = 4844%(X100), DQS PI = 0
7381 19:29:51.188692 [0] AVG Duty = 4969%(X100)
7382 19:29:51.191801
7383 19:29:51.191881 ==DQS 1 ==
7384 19:29:51.195329 Final DQS duty delay cell = 0
7385 19:29:51.198139 [0] MAX Duty = 5249%(X100), DQS PI = 16
7386 19:29:51.201899 [0] MIN Duty = 4969%(X100), DQS PI = 6
7387 19:29:51.205006 [0] AVG Duty = 5109%(X100)
7388 19:29:51.205087
7389 19:29:51.208322 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7390 19:29:51.208403
7391 19:29:51.211927 CH1 DQS 1 Duty spec in!! Max-Min= 280%
7392 19:29:51.215237 [DutyScan_Calibration_Flow] ====Done====
7393 19:29:51.215317
7394 19:29:51.218319 [DutyScan_Calibration_Flow] k_type=3
7395 19:29:51.235774
7396 19:29:51.235857 ==DQM 0 ==
7397 19:29:51.238540 Final DQM duty delay cell = 0
7398 19:29:51.241994 [0] MAX Duty = 5218%(X100), DQS PI = 20
7399 19:29:51.244975 [0] MIN Duty = 4969%(X100), DQS PI = 48
7400 19:29:51.248444 [0] AVG Duty = 5093%(X100)
7401 19:29:51.248539
7402 19:29:51.248602 ==DQM 1 ==
7403 19:29:51.251561 Final DQM duty delay cell = 0
7404 19:29:51.255183 [0] MAX Duty = 5062%(X100), DQS PI = 14
7405 19:29:51.258648 [0] MIN Duty = 4907%(X100), DQS PI = 32
7406 19:29:51.261926 [0] AVG Duty = 4984%(X100)
7407 19:29:51.262006
7408 19:29:51.265001 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7409 19:29:51.265082
7410 19:29:51.268602 CH1 DQM 1 Duty spec in!! Max-Min= 155%
7411 19:29:51.271444 [DutyScan_Calibration_Flow] ====Done====
7412 19:29:51.271526
7413 19:29:51.275231 [DutyScan_Calibration_Flow] k_type=2
7414 19:29:51.291472
7415 19:29:51.291558 ==DQ 0 ==
7416 19:29:51.294741 Final DQ duty delay cell = -4
7417 19:29:51.298289 [-4] MAX Duty = 5031%(X100), DQS PI = 10
7418 19:29:51.301441 [-4] MIN Duty = 4844%(X100), DQS PI = 50
7419 19:29:51.304460 [-4] AVG Duty = 4937%(X100)
7420 19:29:51.304542
7421 19:29:51.304605 ==DQ 1 ==
7422 19:29:51.307729 Final DQ duty delay cell = 0
7423 19:29:51.311544 [0] MAX Duty = 5124%(X100), DQS PI = 16
7424 19:29:51.314314 [0] MIN Duty = 4938%(X100), DQS PI = 8
7425 19:29:51.317926 [0] AVG Duty = 5031%(X100)
7426 19:29:51.318007
7427 19:29:51.321095 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7428 19:29:51.321177
7429 19:29:51.324302 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7430 19:29:51.328073 [DutyScan_Calibration_Flow] ====Done====
7431 19:29:51.331252 nWR fixed to 30
7432 19:29:51.334566 [ModeRegInit_LP4] CH0 RK0
7433 19:29:51.334648 [ModeRegInit_LP4] CH0 RK1
7434 19:29:51.337772 [ModeRegInit_LP4] CH1 RK0
7435 19:29:51.340917 [ModeRegInit_LP4] CH1 RK1
7436 19:29:51.341009 match AC timing 5
7437 19:29:51.347630 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7438 19:29:51.350913 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7439 19:29:51.354257 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7440 19:29:51.361298 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7441 19:29:51.364169 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7442 19:29:51.364258 [MiockJmeterHQA]
7443 19:29:51.364324
7444 19:29:51.367961 [DramcMiockJmeter] u1RxGatingPI = 0
7445 19:29:51.371102 0 : 4365, 4137
7446 19:29:51.371187 4 : 4257, 4029
7447 19:29:51.374092 8 : 4252, 4027
7448 19:29:51.374176 12 : 4363, 4137
7449 19:29:51.377564 16 : 4257, 4027
7450 19:29:51.377647 20 : 4368, 4140
7451 19:29:51.377713 24 : 4253, 4026
7452 19:29:51.381112 28 : 4255, 4029
7453 19:29:51.381196 32 : 4253, 4027
7454 19:29:51.384198 36 : 4253, 4026
7455 19:29:51.384282 40 : 4361, 4137
7456 19:29:51.387493 44 : 4250, 4027
7457 19:29:51.387577 48 : 4250, 4027
7458 19:29:51.387643 52 : 4249, 4027
7459 19:29:51.391018 56 : 4250, 4027
7460 19:29:51.391102 60 : 4253, 4029
7461 19:29:51.394200 64 : 4361, 4138
7462 19:29:51.394283 68 : 4360, 4137
7463 19:29:51.397826 72 : 4360, 4138
7464 19:29:51.397911 76 : 4252, 4029
7465 19:29:51.400610 80 : 4250, 4027
7466 19:29:51.400721 84 : 4252, 4029
7467 19:29:51.400816 88 : 4250, 40
7468 19:29:51.404119 92 : 4250, 0
7469 19:29:51.404202 96 : 4253, 0
7470 19:29:51.407234 100 : 4250, 0
7471 19:29:51.407344 104 : 4250, 0
7472 19:29:51.407438 108 : 4360, 0
7473 19:29:51.410681 112 : 4360, 0
7474 19:29:51.410763 116 : 4363, 0
7475 19:29:51.410828 120 : 4250, 0
7476 19:29:51.413997 124 : 4363, 0
7477 19:29:51.414079 128 : 4250, 0
7478 19:29:51.417522 132 : 4255, 0
7479 19:29:51.417604 136 : 4250, 0
7480 19:29:51.417668 140 : 4250, 0
7481 19:29:51.420370 144 : 4252, 0
7482 19:29:51.420453 148 : 4250, 0
7483 19:29:51.423888 152 : 4250, 0
7484 19:29:51.423970 156 : 4253, 0
7485 19:29:51.424036 160 : 4360, 0
7486 19:29:51.427176 164 : 4252, 0
7487 19:29:51.427258 168 : 4361, 0
7488 19:29:51.430958 172 : 4255, 0
7489 19:29:51.431041 176 : 4249, 0
7490 19:29:51.431106 180 : 4250, 0
7491 19:29:51.433993 184 : 4253, 0
7492 19:29:51.434076 188 : 4249, 0
7493 19:29:51.436986 192 : 4250, 0
7494 19:29:51.437068 196 : 4253, 0
7495 19:29:51.437134 200 : 4250, 0
7496 19:29:51.440716 204 : 4250, 1158
7497 19:29:51.440798 208 : 4249, 4016
7498 19:29:51.443922 212 : 4250, 4027
7499 19:29:51.444004 216 : 4255, 4031
7500 19:29:51.446861 220 : 4250, 4026
7501 19:29:51.446943 224 : 4251, 4027
7502 19:29:51.450679 228 : 4250, 4027
7503 19:29:51.450761 232 : 4250, 4026
7504 19:29:51.450826 236 : 4250, 4027
7505 19:29:51.453744 240 : 4363, 4140
7506 19:29:51.453826 244 : 4363, 4138
7507 19:29:51.456996 248 : 4250, 4027
7508 19:29:51.457079 252 : 4361, 4137
7509 19:29:51.460114 256 : 4250, 4027
7510 19:29:51.460196 260 : 4250, 4027
7511 19:29:51.463875 264 : 4250, 4026
7512 19:29:51.463958 268 : 4363, 4140
7513 19:29:51.467022 272 : 4253, 4029
7514 19:29:51.467132 276 : 4250, 4027
7515 19:29:51.470375 280 : 4363, 4140
7516 19:29:51.470458 284 : 4250, 4027
7517 19:29:51.473844 288 : 4250, 4027
7518 19:29:51.473926 292 : 4364, 4140
7519 19:29:51.477164 296 : 4361, 4138
7520 19:29:51.477249 300 : 4250, 4027
7521 19:29:51.477314 304 : 4250, 4027
7522 19:29:51.480104 308 : 4253, 3941
7523 19:29:51.480185 312 : 4250, 2077
7524 19:29:51.480251
7525 19:29:51.483894 MIOCK jitter meter ch=0
7526 19:29:51.483976
7527 19:29:51.486842 1T = (312-88) = 224 dly cells
7528 19:29:51.493182 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7529 19:29:51.493265 ==
7530 19:29:51.496555 Dram Type= 6, Freq= 0, CH_0, rank 0
7531 19:29:51.500220 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7532 19:29:51.500303 ==
7533 19:29:51.506674 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7534 19:29:51.510470 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7535 19:29:51.513494 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7536 19:29:51.519747 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7537 19:29:51.529311 [CA 0] Center 43 (12~74) winsize 63
7538 19:29:51.532280 [CA 1] Center 43 (13~74) winsize 62
7539 19:29:51.535385 [CA 2] Center 38 (9~68) winsize 60
7540 19:29:51.539074 [CA 3] Center 38 (8~68) winsize 61
7541 19:29:51.542243 [CA 4] Center 37 (7~67) winsize 61
7542 19:29:51.546023 [CA 5] Center 35 (6~65) winsize 60
7543 19:29:51.546104
7544 19:29:51.549176 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7545 19:29:51.549258
7546 19:29:51.552346 [CATrainingPosCal] consider 1 rank data
7547 19:29:51.555691 u2DelayCellTimex100 = 290/100 ps
7548 19:29:51.558840 CA0 delay=43 (12~74),Diff = 8 PI (26 cell)
7549 19:29:51.565641 CA1 delay=43 (13~74),Diff = 8 PI (26 cell)
7550 19:29:51.568932 CA2 delay=38 (9~68),Diff = 3 PI (10 cell)
7551 19:29:51.572097 CA3 delay=38 (8~68),Diff = 3 PI (10 cell)
7552 19:29:51.575782 CA4 delay=37 (7~67),Diff = 2 PI (6 cell)
7553 19:29:51.578929 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7554 19:29:51.579047
7555 19:29:51.582409 CA PerBit enable=1, Macro0, CA PI delay=35
7556 19:29:51.582493
7557 19:29:51.585584 [CBTSetCACLKResult] CA Dly = 35
7558 19:29:51.588849 CS Dly: 9 (0~40)
7559 19:29:51.591770 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7560 19:29:51.595149 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7561 19:29:51.595232 ==
7562 19:29:51.598767 Dram Type= 6, Freq= 0, CH_0, rank 1
7563 19:29:51.601820 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7564 19:29:51.605353 ==
7565 19:29:51.608728 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7566 19:29:51.612106 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7567 19:29:51.618196 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7568 19:29:51.621759 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7569 19:29:51.632245 [CA 0] Center 42 (12~73) winsize 62
7570 19:29:51.635618 [CA 1] Center 42 (12~73) winsize 62
7571 19:29:51.638948 [CA 2] Center 38 (8~68) winsize 61
7572 19:29:51.642265 [CA 3] Center 37 (7~68) winsize 62
7573 19:29:51.645478 [CA 4] Center 35 (6~65) winsize 60
7574 19:29:51.648696 [CA 5] Center 35 (5~65) winsize 61
7575 19:29:51.648779
7576 19:29:51.652170 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7577 19:29:51.652254
7578 19:29:51.655980 [CATrainingPosCal] consider 2 rank data
7579 19:29:51.659152 u2DelayCellTimex100 = 290/100 ps
7580 19:29:51.662261 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7581 19:29:51.668576 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7582 19:29:51.672406 CA2 delay=38 (9~68),Diff = 3 PI (10 cell)
7583 19:29:51.675591 CA3 delay=38 (8~68),Diff = 3 PI (10 cell)
7584 19:29:51.678723 CA4 delay=36 (7~65),Diff = 1 PI (3 cell)
7585 19:29:51.681930 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7586 19:29:51.682013
7587 19:29:51.685609 CA PerBit enable=1, Macro0, CA PI delay=35
7588 19:29:51.685692
7589 19:29:51.688418 [CBTSetCACLKResult] CA Dly = 35
7590 19:29:51.692213 CS Dly: 10 (0~42)
7591 19:29:51.695223 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7592 19:29:51.698459 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7593 19:29:51.698542
7594 19:29:51.702271 ----->DramcWriteLeveling(PI) begin...
7595 19:29:51.702391 ==
7596 19:29:51.705610 Dram Type= 6, Freq= 0, CH_0, rank 0
7597 19:29:51.711771 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7598 19:29:51.711855 ==
7599 19:29:51.715240 Write leveling (Byte 0): 37 => 37
7600 19:29:51.715323 Write leveling (Byte 1): 27 => 27
7601 19:29:51.718934 DramcWriteLeveling(PI) end<-----
7602 19:29:51.719017
7603 19:29:51.719081 ==
7604 19:29:51.722275 Dram Type= 6, Freq= 0, CH_0, rank 0
7605 19:29:51.728868 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7606 19:29:51.728951 ==
7607 19:29:51.731886 [Gating] SW mode calibration
7608 19:29:51.738754 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7609 19:29:51.741686 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7610 19:29:51.748436 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7611 19:29:51.751615 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7612 19:29:51.754879 1 4 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7613 19:29:51.761900 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7614 19:29:51.765297 1 4 16 | B1->B0 | 2424 1313 | 0 1 | (0 0) (0 0)
7615 19:29:51.768357 1 4 20 | B1->B0 | 3434 3837 | 1 1 | (1 1) (0 0)
7616 19:29:51.775178 1 4 24 | B1->B0 | 3434 3636 | 1 1 | (1 1) (0 0)
7617 19:29:51.778235 1 4 28 | B1->B0 | 3434 3636 | 1 1 | (1 1) (0 0)
7618 19:29:51.781442 1 5 0 | B1->B0 | 3434 3939 | 1 1 | (1 1) (1 1)
7619 19:29:51.788410 1 5 4 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7620 19:29:51.791411 1 5 8 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 0)
7621 19:29:51.794855 1 5 12 | B1->B0 | 3434 2b2a | 1 1 | (1 1) (1 0)
7622 19:29:51.801532 1 5 16 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
7623 19:29:51.804941 1 5 20 | B1->B0 | 2727 2625 | 0 1 | (1 0) (0 0)
7624 19:29:51.807962 1 5 24 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (1 1)
7625 19:29:51.814346 1 5 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7626 19:29:51.818092 1 6 0 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7627 19:29:51.821154 1 6 4 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
7628 19:29:51.825082 1 6 8 | B1->B0 | 2323 2d2c | 0 1 | (0 0) (0 0)
7629 19:29:51.831410 1 6 12 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
7630 19:29:51.834740 1 6 16 | B1->B0 | 2929 4646 | 0 0 | (1 1) (0 0)
7631 19:29:51.837957 1 6 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
7632 19:29:51.844436 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7633 19:29:51.848002 1 6 28 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7634 19:29:51.851312 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7635 19:29:51.857674 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7636 19:29:51.861367 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7637 19:29:51.864325 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7638 19:29:51.870956 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7639 19:29:51.874581 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7640 19:29:51.877810 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7641 19:29:51.884318 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7642 19:29:51.888016 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 19:29:51.891349 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7644 19:29:51.897766 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7645 19:29:51.901208 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7646 19:29:51.904242 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7647 19:29:51.911067 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7648 19:29:51.914231 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7649 19:29:51.917422 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7650 19:29:51.924469 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7651 19:29:51.927380 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7652 19:29:51.931138 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7653 19:29:51.937436 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7654 19:29:51.940695 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7655 19:29:51.944332 Total UI for P1: 0, mck2ui 16
7656 19:29:51.947236 best dqsien dly found for B0: ( 1, 9, 12)
7657 19:29:51.950738 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7658 19:29:51.954151 Total UI for P1: 0, mck2ui 16
7659 19:29:51.957262 best dqsien dly found for B1: ( 1, 9, 18)
7660 19:29:51.960432 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7661 19:29:51.963970 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7662 19:29:51.964125
7663 19:29:51.970249 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7664 19:29:51.973633 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7665 19:29:51.973716 [Gating] SW calibration Done
7666 19:29:51.977248 ==
7667 19:29:51.980444 Dram Type= 6, Freq= 0, CH_0, rank 0
7668 19:29:51.983804 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7669 19:29:51.983888 ==
7670 19:29:51.983953 RX Vref Scan: 0
7671 19:29:51.984015
7672 19:29:51.987126 RX Vref 0 -> 0, step: 1
7673 19:29:51.987208
7674 19:29:51.990715 RX Delay 0 -> 252, step: 8
7675 19:29:51.993779 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7676 19:29:51.997500 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7677 19:29:52.000126 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7678 19:29:52.006827 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7679 19:29:52.010187 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7680 19:29:52.013641 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7681 19:29:52.016985 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
7682 19:29:52.020240 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7683 19:29:52.027110 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7684 19:29:52.030338 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7685 19:29:52.033812 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7686 19:29:52.037220 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7687 19:29:52.040222 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
7688 19:29:52.046723 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7689 19:29:52.050370 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7690 19:29:52.053570 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7691 19:29:52.053653 ==
7692 19:29:52.057138 Dram Type= 6, Freq= 0, CH_0, rank 0
7693 19:29:52.060114 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7694 19:29:52.060197 ==
7695 19:29:52.063338 DQS Delay:
7696 19:29:52.063422 DQS0 = 0, DQS1 = 0
7697 19:29:52.066896 DQM Delay:
7698 19:29:52.066979 DQM0 = 136, DQM1 = 129
7699 19:29:52.069823 DQ Delay:
7700 19:29:52.073629 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =131
7701 19:29:52.076555 DQ4 =139, DQ5 =123, DQ6 =143, DQ7 =143
7702 19:29:52.079742 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
7703 19:29:52.083453 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =135
7704 19:29:52.083535
7705 19:29:52.083601
7706 19:29:52.083661 ==
7707 19:29:52.086583 Dram Type= 6, Freq= 0, CH_0, rank 0
7708 19:29:52.089734 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7709 19:29:52.089843 ==
7710 19:29:52.089937
7711 19:29:52.090026
7712 19:29:52.093030 TX Vref Scan disable
7713 19:29:52.096899 == TX Byte 0 ==
7714 19:29:52.099688 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7715 19:29:52.103248 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7716 19:29:52.106733 == TX Byte 1 ==
7717 19:29:52.109955 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7718 19:29:52.113247 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7719 19:29:52.113331 ==
7720 19:29:52.116353 Dram Type= 6, Freq= 0, CH_0, rank 0
7721 19:29:52.122840 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7722 19:29:52.122923 ==
7723 19:29:52.134235
7724 19:29:52.137799 TX Vref early break, caculate TX vref
7725 19:29:52.141148 TX Vref=16, minBit 4, minWin=21, winSum=380
7726 19:29:52.144681 TX Vref=18, minBit 1, minWin=23, winSum=386
7727 19:29:52.147942 TX Vref=20, minBit 4, minWin=23, winSum=401
7728 19:29:52.151205 TX Vref=22, minBit 2, minWin=24, winSum=408
7729 19:29:52.154491 TX Vref=24, minBit 0, minWin=25, winSum=413
7730 19:29:52.160705 TX Vref=26, minBit 2, minWin=25, winSum=425
7731 19:29:52.164257 TX Vref=28, minBit 0, minWin=25, winSum=423
7732 19:29:52.167417 TX Vref=30, minBit 0, minWin=25, winSum=412
7733 19:29:52.170642 TX Vref=32, minBit 6, minWin=23, winSum=402
7734 19:29:52.177269 [TxChooseVref] Worse bit 2, Min win 25, Win sum 425, Final Vref 26
7735 19:29:52.177353
7736 19:29:52.181074 Final TX Range 0 Vref 26
7737 19:29:52.181157
7738 19:29:52.181223 ==
7739 19:29:52.184269 Dram Type= 6, Freq= 0, CH_0, rank 0
7740 19:29:52.187438 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7741 19:29:52.187521 ==
7742 19:29:52.187586
7743 19:29:52.187646
7744 19:29:52.190295 TX Vref Scan disable
7745 19:29:52.193942 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7746 19:29:52.197461 == TX Byte 0 ==
7747 19:29:52.201029 u2DelayCellOfst[0]=13 cells (4 PI)
7748 19:29:52.203831 u2DelayCellOfst[1]=16 cells (5 PI)
7749 19:29:52.207411 u2DelayCellOfst[2]=13 cells (4 PI)
7750 19:29:52.210972 u2DelayCellOfst[3]=10 cells (3 PI)
7751 19:29:52.213904 u2DelayCellOfst[4]=10 cells (3 PI)
7752 19:29:52.217519 u2DelayCellOfst[5]=0 cells (0 PI)
7753 19:29:52.217601 u2DelayCellOfst[6]=16 cells (5 PI)
7754 19:29:52.220925 u2DelayCellOfst[7]=16 cells (5 PI)
7755 19:29:52.227518 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7756 19:29:52.230475 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7757 19:29:52.230558 == TX Byte 1 ==
7758 19:29:52.234191 u2DelayCellOfst[8]=0 cells (0 PI)
7759 19:29:52.237497 u2DelayCellOfst[9]=0 cells (0 PI)
7760 19:29:52.240646 u2DelayCellOfst[10]=10 cells (3 PI)
7761 19:29:52.243896 u2DelayCellOfst[11]=6 cells (2 PI)
7762 19:29:52.247465 u2DelayCellOfst[12]=10 cells (3 PI)
7763 19:29:52.250653 u2DelayCellOfst[13]=13 cells (4 PI)
7764 19:29:52.253612 u2DelayCellOfst[14]=16 cells (5 PI)
7765 19:29:52.257650 u2DelayCellOfst[15]=10 cells (3 PI)
7766 19:29:52.260688 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7767 19:29:52.263823 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7768 19:29:52.267040 DramC Write-DBI on
7769 19:29:52.267124 ==
7770 19:29:52.270265 Dram Type= 6, Freq= 0, CH_0, rank 0
7771 19:29:52.273766 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7772 19:29:52.273849 ==
7773 19:29:52.273915
7774 19:29:52.277559
7775 19:29:52.277641 TX Vref Scan disable
7776 19:29:52.280733 == TX Byte 0 ==
7777 19:29:52.283783 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7778 19:29:52.287598 == TX Byte 1 ==
7779 19:29:52.290652 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7780 19:29:52.290735 DramC Write-DBI off
7781 19:29:52.290800
7782 19:29:52.293524 [DATLAT]
7783 19:29:52.293605 Freq=1600, CH0 RK0
7784 19:29:52.293671
7785 19:29:52.297365 DATLAT Default: 0xf
7786 19:29:52.297448 0, 0xFFFF, sum = 0
7787 19:29:52.300256 1, 0xFFFF, sum = 0
7788 19:29:52.300340 2, 0xFFFF, sum = 0
7789 19:29:52.303856 3, 0xFFFF, sum = 0
7790 19:29:52.303939 4, 0xFFFF, sum = 0
7791 19:29:52.307287 5, 0xFFFF, sum = 0
7792 19:29:52.307371 6, 0xFFFF, sum = 0
7793 19:29:52.310280 7, 0xFFFF, sum = 0
7794 19:29:52.313788 8, 0xFFFF, sum = 0
7795 19:29:52.313872 9, 0xFFFF, sum = 0
7796 19:29:52.317300 10, 0xFFFF, sum = 0
7797 19:29:52.317384 11, 0xFFFF, sum = 0
7798 19:29:52.320214 12, 0xFFFF, sum = 0
7799 19:29:52.320298 13, 0xFFFF, sum = 0
7800 19:29:52.323608 14, 0x0, sum = 1
7801 19:29:52.323692 15, 0x0, sum = 2
7802 19:29:52.326910 16, 0x0, sum = 3
7803 19:29:52.326994 17, 0x0, sum = 4
7804 19:29:52.327061 best_step = 15
7805 19:29:52.330694
7806 19:29:52.330777 ==
7807 19:29:52.333798 Dram Type= 6, Freq= 0, CH_0, rank 0
7808 19:29:52.336928 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7809 19:29:52.337011 ==
7810 19:29:52.337076 RX Vref Scan: 1
7811 19:29:52.337136
7812 19:29:52.340384 Set Vref Range= 24 -> 127
7813 19:29:52.340467
7814 19:29:52.343943 RX Vref 24 -> 127, step: 1
7815 19:29:52.344025
7816 19:29:52.346943 RX Delay 19 -> 252, step: 4
7817 19:29:52.347029
7818 19:29:52.350327 Set Vref, RX VrefLevel [Byte0]: 24
7819 19:29:52.353627 [Byte1]: 24
7820 19:29:52.353710
7821 19:29:52.356810 Set Vref, RX VrefLevel [Byte0]: 25
7822 19:29:52.360288 [Byte1]: 25
7823 19:29:52.360371
7824 19:29:52.363291 Set Vref, RX VrefLevel [Byte0]: 26
7825 19:29:52.367092 [Byte1]: 26
7826 19:29:52.370260
7827 19:29:52.370373 Set Vref, RX VrefLevel [Byte0]: 27
7828 19:29:52.373973 [Byte1]: 27
7829 19:29:52.377921
7830 19:29:52.378003 Set Vref, RX VrefLevel [Byte0]: 28
7831 19:29:52.381639 [Byte1]: 28
7832 19:29:52.385417
7833 19:29:52.385499 Set Vref, RX VrefLevel [Byte0]: 29
7834 19:29:52.389111 [Byte1]: 29
7835 19:29:52.393263
7836 19:29:52.393345 Set Vref, RX VrefLevel [Byte0]: 30
7837 19:29:52.396601 [Byte1]: 30
7838 19:29:52.400805
7839 19:29:52.400888 Set Vref, RX VrefLevel [Byte0]: 31
7840 19:29:52.403875 [Byte1]: 31
7841 19:29:52.408068
7842 19:29:52.408150 Set Vref, RX VrefLevel [Byte0]: 32
7843 19:29:52.411759 [Byte1]: 32
7844 19:29:52.415988
7845 19:29:52.416070 Set Vref, RX VrefLevel [Byte0]: 33
7846 19:29:52.419453 [Byte1]: 33
7847 19:29:52.423580
7848 19:29:52.423662 Set Vref, RX VrefLevel [Byte0]: 34
7849 19:29:52.426949 [Byte1]: 34
7850 19:29:52.431152
7851 19:29:52.431235 Set Vref, RX VrefLevel [Byte0]: 35
7852 19:29:52.434253 [Byte1]: 35
7853 19:29:52.438592
7854 19:29:52.438674 Set Vref, RX VrefLevel [Byte0]: 36
7855 19:29:52.441664 [Byte1]: 36
7856 19:29:52.446248
7857 19:29:52.446367 Set Vref, RX VrefLevel [Byte0]: 37
7858 19:29:52.449452 [Byte1]: 37
7859 19:29:52.453745
7860 19:29:52.453828 Set Vref, RX VrefLevel [Byte0]: 38
7861 19:29:52.456967 [Byte1]: 38
7862 19:29:52.461086
7863 19:29:52.461168 Set Vref, RX VrefLevel [Byte0]: 39
7864 19:29:52.464552 [Byte1]: 39
7865 19:29:52.468996
7866 19:29:52.469078 Set Vref, RX VrefLevel [Byte0]: 40
7867 19:29:52.472489 [Byte1]: 40
7868 19:29:52.476294
7869 19:29:52.476376 Set Vref, RX VrefLevel [Byte0]: 41
7870 19:29:52.479982 [Byte1]: 41
7871 19:29:52.484055
7872 19:29:52.484137 Set Vref, RX VrefLevel [Byte0]: 42
7873 19:29:52.487111 [Byte1]: 42
7874 19:29:52.491705
7875 19:29:52.491788 Set Vref, RX VrefLevel [Byte0]: 43
7876 19:29:52.494917 [Byte1]: 43
7877 19:29:52.499008
7878 19:29:52.499090 Set Vref, RX VrefLevel [Byte0]: 44
7879 19:29:52.502833 [Byte1]: 44
7880 19:29:52.506585
7881 19:29:52.506700 Set Vref, RX VrefLevel [Byte0]: 45
7882 19:29:52.510124 [Byte1]: 45
7883 19:29:52.514142
7884 19:29:52.514228 Set Vref, RX VrefLevel [Byte0]: 46
7885 19:29:52.518089 [Byte1]: 46
7886 19:29:52.521726
7887 19:29:52.521808 Set Vref, RX VrefLevel [Byte0]: 47
7888 19:29:52.525459 [Byte1]: 47
7889 19:29:52.529393
7890 19:29:52.529475 Set Vref, RX VrefLevel [Byte0]: 48
7891 19:29:52.533033 [Byte1]: 48
7892 19:29:52.537045
7893 19:29:52.537128 Set Vref, RX VrefLevel [Byte0]: 49
7894 19:29:52.540474 [Byte1]: 49
7895 19:29:52.544905
7896 19:29:52.544990 Set Vref, RX VrefLevel [Byte0]: 50
7897 19:29:52.547944 [Byte1]: 50
7898 19:29:52.552011
7899 19:29:52.552094 Set Vref, RX VrefLevel [Byte0]: 51
7900 19:29:52.555382 [Byte1]: 51
7901 19:29:52.559666
7902 19:29:52.559748 Set Vref, RX VrefLevel [Byte0]: 52
7903 19:29:52.562974 [Byte1]: 52
7904 19:29:52.567344
7905 19:29:52.567426 Set Vref, RX VrefLevel [Byte0]: 53
7906 19:29:52.570973 [Byte1]: 53
7907 19:29:52.575118
7908 19:29:52.575200 Set Vref, RX VrefLevel [Byte0]: 54
7909 19:29:52.578629 [Byte1]: 54
7910 19:29:52.582292
7911 19:29:52.582409 Set Vref, RX VrefLevel [Byte0]: 55
7912 19:29:52.585638 [Byte1]: 55
7913 19:29:52.590511
7914 19:29:52.590594 Set Vref, RX VrefLevel [Byte0]: 56
7915 19:29:52.593556 [Byte1]: 56
7916 19:29:52.597831
7917 19:29:52.597912 Set Vref, RX VrefLevel [Byte0]: 57
7918 19:29:52.601062 [Byte1]: 57
7919 19:29:52.605358
7920 19:29:52.605439 Set Vref, RX VrefLevel [Byte0]: 58
7921 19:29:52.608773 [Byte1]: 58
7922 19:29:52.612983
7923 19:29:52.613066 Set Vref, RX VrefLevel [Byte0]: 59
7924 19:29:52.616003 [Byte1]: 59
7925 19:29:52.620056
7926 19:29:52.620137 Set Vref, RX VrefLevel [Byte0]: 60
7927 19:29:52.623778 [Byte1]: 60
7928 19:29:52.628192
7929 19:29:52.628272 Set Vref, RX VrefLevel [Byte0]: 61
7930 19:29:52.631482 [Byte1]: 61
7931 19:29:52.635389
7932 19:29:52.635470 Set Vref, RX VrefLevel [Byte0]: 62
7933 19:29:52.638976 [Byte1]: 62
7934 19:29:52.643121
7935 19:29:52.643202 Set Vref, RX VrefLevel [Byte0]: 63
7936 19:29:52.646558 [Byte1]: 63
7937 19:29:52.651103
7938 19:29:52.651185 Set Vref, RX VrefLevel [Byte0]: 64
7939 19:29:52.653947 [Byte1]: 64
7940 19:29:52.658567
7941 19:29:52.658648 Set Vref, RX VrefLevel [Byte0]: 65
7942 19:29:52.661306 [Byte1]: 65
7943 19:29:52.666158
7944 19:29:52.666266 Set Vref, RX VrefLevel [Byte0]: 66
7945 19:29:52.669217 [Byte1]: 66
7946 19:29:52.673442
7947 19:29:52.673527 Set Vref, RX VrefLevel [Byte0]: 67
7948 19:29:52.676557 [Byte1]: 67
7949 19:29:52.681121
7950 19:29:52.681202 Set Vref, RX VrefLevel [Byte0]: 68
7951 19:29:52.684205 [Byte1]: 68
7952 19:29:52.688494
7953 19:29:52.688576 Set Vref, RX VrefLevel [Byte0]: 69
7954 19:29:52.691663 [Byte1]: 69
7955 19:29:52.696099
7956 19:29:52.696182 Set Vref, RX VrefLevel [Byte0]: 70
7957 19:29:52.699368 [Byte1]: 70
7958 19:29:52.703235
7959 19:29:52.707164 Set Vref, RX VrefLevel [Byte0]: 71
7960 19:29:52.710249 [Byte1]: 71
7961 19:29:52.710353
7962 19:29:52.713410 Set Vref, RX VrefLevel [Byte0]: 72
7963 19:29:52.716770 [Byte1]: 72
7964 19:29:52.716853
7965 19:29:52.719714 Set Vref, RX VrefLevel [Byte0]: 73
7966 19:29:52.723123 [Byte1]: 73
7967 19:29:52.723206
7968 19:29:52.726396 Set Vref, RX VrefLevel [Byte0]: 74
7969 19:29:52.729677 [Byte1]: 74
7970 19:29:52.733883
7971 19:29:52.733965 Set Vref, RX VrefLevel [Byte0]: 75
7972 19:29:52.737204 [Byte1]: 75
7973 19:29:52.741796
7974 19:29:52.741878 Final RX Vref Byte 0 = 60 to rank0
7975 19:29:52.744723 Final RX Vref Byte 1 = 59 to rank0
7976 19:29:52.747881 Final RX Vref Byte 0 = 60 to rank1
7977 19:29:52.751371 Final RX Vref Byte 1 = 59 to rank1==
7978 19:29:52.754732 Dram Type= 6, Freq= 0, CH_0, rank 0
7979 19:29:52.761593 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7980 19:29:52.761675 ==
7981 19:29:52.761739 DQS Delay:
7982 19:29:52.761799 DQS0 = 0, DQS1 = 0
7983 19:29:52.765079 DQM Delay:
7984 19:29:52.765160 DQM0 = 134, DQM1 = 127
7985 19:29:52.767942 DQ Delay:
7986 19:29:52.771964 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =132
7987 19:29:52.774830 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =140
7988 19:29:52.778066 DQ8 =116, DQ9 =118, DQ10 =128, DQ11 =120
7989 19:29:52.781105 DQ12 =134, DQ13 =132, DQ14 =138, DQ15 =134
7990 19:29:52.781186
7991 19:29:52.781250
7992 19:29:52.781310
7993 19:29:52.784733 [DramC_TX_OE_Calibration] TA2
7994 19:29:52.788043 Original DQ_B0 (3 6) =30, OEN = 27
7995 19:29:52.791142 Original DQ_B1 (3 6) =30, OEN = 27
7996 19:29:52.794841 24, 0x0, End_B0=24 End_B1=24
7997 19:29:52.794924 25, 0x0, End_B0=25 End_B1=25
7998 19:29:52.797869 26, 0x0, End_B0=26 End_B1=26
7999 19:29:52.800881 27, 0x0, End_B0=27 End_B1=27
8000 19:29:52.804826 28, 0x0, End_B0=28 End_B1=28
8001 19:29:52.808030 29, 0x0, End_B0=29 End_B1=29
8002 19:29:52.808115 30, 0x0, End_B0=30 End_B1=30
8003 19:29:52.811173 31, 0x4141, End_B0=30 End_B1=30
8004 19:29:52.814376 Byte0 end_step=30 best_step=27
8005 19:29:52.817724 Byte1 end_step=30 best_step=27
8006 19:29:52.821352 Byte0 TX OE(2T, 0.5T) = (3, 3)
8007 19:29:52.824730 Byte1 TX OE(2T, 0.5T) = (3, 3)
8008 19:29:52.824815
8009 19:29:52.824880
8010 19:29:52.831011 [DQSOSCAuto] RK0, (LSB)MR18= 0x2521, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
8011 19:29:52.834417 CH0 RK0: MR19=303, MR18=2521
8012 19:29:52.841214 CH0_RK0: MR19=0x303, MR18=0x2521, DQSOSC=391, MR23=63, INC=24, DEC=16
8013 19:29:52.841296
8014 19:29:52.844323 ----->DramcWriteLeveling(PI) begin...
8015 19:29:52.844405 ==
8016 19:29:52.847622 Dram Type= 6, Freq= 0, CH_0, rank 1
8017 19:29:52.851264 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8018 19:29:52.851351 ==
8019 19:29:52.854174 Write leveling (Byte 0): 35 => 35
8020 19:29:52.858010 Write leveling (Byte 1): 29 => 29
8021 19:29:52.860921 DramcWriteLeveling(PI) end<-----
8022 19:29:52.861002
8023 19:29:52.861065 ==
8024 19:29:52.864242 Dram Type= 6, Freq= 0, CH_0, rank 1
8025 19:29:52.867837 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8026 19:29:52.867919 ==
8027 19:29:52.870790 [Gating] SW mode calibration
8028 19:29:52.877694 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8029 19:29:52.884450 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8030 19:29:52.887424 1 4 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8031 19:29:52.891208 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8032 19:29:52.897426 1 4 8 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
8033 19:29:52.900421 1 4 12 | B1->B0 | 2424 2c2c | 0 0 | (0 0) (0 0)
8034 19:29:52.904070 1 4 16 | B1->B0 | 2f2f 3837 | 1 1 | (1 1) (1 1)
8035 19:29:52.910752 1 4 20 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
8036 19:29:52.913820 1 4 24 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
8037 19:29:52.917049 1 4 28 | B1->B0 | 3434 3838 | 1 0 | (1 1) (0 0)
8038 19:29:52.924078 1 5 0 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
8039 19:29:52.927005 1 5 4 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
8040 19:29:52.930564 1 5 8 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
8041 19:29:52.936741 1 5 12 | B1->B0 | 3434 3736 | 1 1 | (1 0) (1 0)
8042 19:29:52.940671 1 5 16 | B1->B0 | 3030 2525 | 1 0 | (1 0) (1 0)
8043 19:29:52.943705 1 5 20 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
8044 19:29:52.950262 1 5 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8045 19:29:52.953634 1 5 28 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (0 0)
8046 19:29:52.956835 1 6 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8047 19:29:52.963570 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8048 19:29:52.966977 1 6 8 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
8049 19:29:52.970482 1 6 12 | B1->B0 | 2424 3635 | 0 1 | (0 0) (1 1)
8050 19:29:52.976997 1 6 16 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
8051 19:29:52.979910 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8052 19:29:52.983296 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8053 19:29:52.990390 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8054 19:29:52.993774 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8055 19:29:52.996833 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8056 19:29:53.003398 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8057 19:29:53.006333 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8058 19:29:53.009849 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8059 19:29:53.016563 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 19:29:53.019723 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8061 19:29:53.023274 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8062 19:29:53.030181 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8063 19:29:53.033188 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8064 19:29:53.036264 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8065 19:29:53.043296 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8066 19:29:53.046372 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8067 19:29:53.049615 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8068 19:29:53.056604 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8069 19:29:53.059841 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8070 19:29:53.062893 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8071 19:29:53.069779 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8072 19:29:53.073201 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8073 19:29:53.076238 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8074 19:29:53.082899 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8075 19:29:53.082981 Total UI for P1: 0, mck2ui 16
8076 19:29:53.086137 best dqsien dly found for B0: ( 1, 9, 10)
8077 19:29:53.089716 Total UI for P1: 0, mck2ui 16
8078 19:29:53.092817 best dqsien dly found for B1: ( 1, 9, 12)
8079 19:29:53.096332 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8080 19:29:53.102876 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8081 19:29:53.102961
8082 19:29:53.105979 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8083 19:29:53.109563 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8084 19:29:53.112758 [Gating] SW calibration Done
8085 19:29:53.112840 ==
8086 19:29:53.116428 Dram Type= 6, Freq= 0, CH_0, rank 1
8087 19:29:53.119657 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8088 19:29:53.119739 ==
8089 19:29:53.122961 RX Vref Scan: 0
8090 19:29:53.123042
8091 19:29:53.123105 RX Vref 0 -> 0, step: 1
8092 19:29:53.123164
8093 19:29:53.126177 RX Delay 0 -> 252, step: 8
8094 19:29:53.129294 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8095 19:29:53.136171 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8096 19:29:53.139888 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8097 19:29:53.143111 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8098 19:29:53.145728 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8099 19:29:53.149105 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8100 19:29:53.152603 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8101 19:29:53.158976 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8102 19:29:53.162891 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8103 19:29:53.165868 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8104 19:29:53.168929 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8105 19:29:53.172663 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8106 19:29:53.179057 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8107 19:29:53.182422 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8108 19:29:53.186080 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8109 19:29:53.188991 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8110 19:29:53.189073 ==
8111 19:29:53.192409 Dram Type= 6, Freq= 0, CH_0, rank 1
8112 19:29:53.199374 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8113 19:29:53.199456 ==
8114 19:29:53.199521 DQS Delay:
8115 19:29:53.202521 DQS0 = 0, DQS1 = 0
8116 19:29:53.202602 DQM Delay:
8117 19:29:53.205869 DQM0 = 137, DQM1 = 128
8118 19:29:53.205951 DQ Delay:
8119 19:29:53.209011 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8120 19:29:53.212317 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8121 19:29:53.215603 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8122 19:29:53.219294 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8123 19:29:53.219376
8124 19:29:53.219440
8125 19:29:53.219500 ==
8126 19:29:53.222763 Dram Type= 6, Freq= 0, CH_0, rank 1
8127 19:29:53.225604 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8128 19:29:53.229332 ==
8129 19:29:53.229414
8130 19:29:53.229505
8131 19:29:53.229579 TX Vref Scan disable
8132 19:29:53.232420 == TX Byte 0 ==
8133 19:29:53.235992 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8134 19:29:53.239410 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8135 19:29:53.242496 == TX Byte 1 ==
8136 19:29:53.245814 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8137 19:29:53.249173 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8138 19:29:53.252962 ==
8139 19:29:53.253045 Dram Type= 6, Freq= 0, CH_0, rank 1
8140 19:29:53.258629 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8141 19:29:53.258712 ==
8142 19:29:53.271771
8143 19:29:53.275402 TX Vref early break, caculate TX vref
8144 19:29:53.278509 TX Vref=16, minBit 1, minWin=22, winSum=389
8145 19:29:53.281676 TX Vref=18, minBit 2, minWin=23, winSum=398
8146 19:29:53.284938 TX Vref=20, minBit 1, minWin=24, winSum=404
8147 19:29:53.288173 TX Vref=22, minBit 1, minWin=24, winSum=412
8148 19:29:53.291866 TX Vref=24, minBit 1, minWin=25, winSum=424
8149 19:29:53.298649 TX Vref=26, minBit 7, minWin=25, winSum=426
8150 19:29:53.301756 TX Vref=28, minBit 7, minWin=25, winSum=425
8151 19:29:53.304789 TX Vref=30, minBit 0, minWin=25, winSum=418
8152 19:29:53.308337 TX Vref=32, minBit 2, minWin=24, winSum=408
8153 19:29:53.311894 TX Vref=34, minBit 1, minWin=24, winSum=402
8154 19:29:53.318428 [TxChooseVref] Worse bit 7, Min win 25, Win sum 426, Final Vref 26
8155 19:29:53.318512
8156 19:29:53.321569 Final TX Range 0 Vref 26
8157 19:29:53.321650
8158 19:29:53.321714 ==
8159 19:29:53.324970 Dram Type= 6, Freq= 0, CH_0, rank 1
8160 19:29:53.328460 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8161 19:29:53.328541 ==
8162 19:29:53.328605
8163 19:29:53.328665
8164 19:29:53.331645 TX Vref Scan disable
8165 19:29:53.338269 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8166 19:29:53.338391 == TX Byte 0 ==
8167 19:29:53.341489 u2DelayCellOfst[0]=10 cells (3 PI)
8168 19:29:53.344915 u2DelayCellOfst[1]=16 cells (5 PI)
8169 19:29:53.348297 u2DelayCellOfst[2]=10 cells (3 PI)
8170 19:29:53.351400 u2DelayCellOfst[3]=10 cells (3 PI)
8171 19:29:53.354945 u2DelayCellOfst[4]=6 cells (2 PI)
8172 19:29:53.358180 u2DelayCellOfst[5]=0 cells (0 PI)
8173 19:29:53.361478 u2DelayCellOfst[6]=16 cells (5 PI)
8174 19:29:53.364697 u2DelayCellOfst[7]=13 cells (4 PI)
8175 19:29:53.368018 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8176 19:29:53.371920 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8177 19:29:53.375047 == TX Byte 1 ==
8178 19:29:53.375129 u2DelayCellOfst[8]=0 cells (0 PI)
8179 19:29:53.377911 u2DelayCellOfst[9]=0 cells (0 PI)
8180 19:29:53.381220 u2DelayCellOfst[10]=6 cells (2 PI)
8181 19:29:53.385074 u2DelayCellOfst[11]=6 cells (2 PI)
8182 19:29:53.388370 u2DelayCellOfst[12]=13 cells (4 PI)
8183 19:29:53.391384 u2DelayCellOfst[13]=13 cells (4 PI)
8184 19:29:53.394619 u2DelayCellOfst[14]=13 cells (4 PI)
8185 19:29:53.398238 u2DelayCellOfst[15]=10 cells (3 PI)
8186 19:29:53.401440 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8187 19:29:53.408236 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8188 19:29:53.408320 DramC Write-DBI on
8189 19:29:53.408385 ==
8190 19:29:53.411396 Dram Type= 6, Freq= 0, CH_0, rank 1
8191 19:29:53.414701 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8192 19:29:53.417565 ==
8193 19:29:53.417647
8194 19:29:53.417711
8195 19:29:53.417779 TX Vref Scan disable
8196 19:29:53.421061 == TX Byte 0 ==
8197 19:29:53.424738 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8198 19:29:53.428003 == TX Byte 1 ==
8199 19:29:53.431343 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8200 19:29:53.434485 DramC Write-DBI off
8201 19:29:53.434571
8202 19:29:53.434637 [DATLAT]
8203 19:29:53.434698 Freq=1600, CH0 RK1
8204 19:29:53.434756
8205 19:29:53.437593 DATLAT Default: 0xf
8206 19:29:53.437675 0, 0xFFFF, sum = 0
8207 19:29:53.441401 1, 0xFFFF, sum = 0
8208 19:29:53.444297 2, 0xFFFF, sum = 0
8209 19:29:53.444383 3, 0xFFFF, sum = 0
8210 19:29:53.448019 4, 0xFFFF, sum = 0
8211 19:29:53.448105 5, 0xFFFF, sum = 0
8212 19:29:53.450961 6, 0xFFFF, sum = 0
8213 19:29:53.451072 7, 0xFFFF, sum = 0
8214 19:29:53.454691 8, 0xFFFF, sum = 0
8215 19:29:53.454777 9, 0xFFFF, sum = 0
8216 19:29:53.457797 10, 0xFFFF, sum = 0
8217 19:29:53.457898 11, 0xFFFF, sum = 0
8218 19:29:53.461558 12, 0xFFFF, sum = 0
8219 19:29:53.461641 13, 0xFFFF, sum = 0
8220 19:29:53.464605 14, 0x0, sum = 1
8221 19:29:53.464714 15, 0x0, sum = 2
8222 19:29:53.468021 16, 0x0, sum = 3
8223 19:29:53.468104 17, 0x0, sum = 4
8224 19:29:53.471108 best_step = 15
8225 19:29:53.471189
8226 19:29:53.471253 ==
8227 19:29:53.474213 Dram Type= 6, Freq= 0, CH_0, rank 1
8228 19:29:53.478027 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8229 19:29:53.478109 ==
8230 19:29:53.481240 RX Vref Scan: 0
8231 19:29:53.481321
8232 19:29:53.481386 RX Vref 0 -> 0, step: 1
8233 19:29:53.481446
8234 19:29:53.484724 RX Delay 19 -> 252, step: 4
8235 19:29:53.487974 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8236 19:29:53.494360 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8237 19:29:53.497843 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8238 19:29:53.501233 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8239 19:29:53.504277 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8240 19:29:53.507788 iDelay=191, Bit 5, Center 126 (75 ~ 178) 104
8241 19:29:53.514580 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8242 19:29:53.517715 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8243 19:29:53.521037 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8244 19:29:53.524202 iDelay=191, Bit 9, Center 116 (63 ~ 170) 108
8245 19:29:53.527656 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8246 19:29:53.530895 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8247 19:29:53.537721 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8248 19:29:53.541533 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8249 19:29:53.544538 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8250 19:29:53.547900 iDelay=191, Bit 15, Center 136 (87 ~ 186) 100
8251 19:29:53.547986 ==
8252 19:29:53.551228 Dram Type= 6, Freq= 0, CH_0, rank 1
8253 19:29:53.557837 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8254 19:29:53.557924 ==
8255 19:29:53.557992 DQS Delay:
8256 19:29:53.560864 DQS0 = 0, DQS1 = 0
8257 19:29:53.560945 DQM Delay:
8258 19:29:53.564589 DQM0 = 134, DQM1 = 127
8259 19:29:53.564670 DQ Delay:
8260 19:29:53.567596 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =134
8261 19:29:53.571231 DQ4 =136, DQ5 =126, DQ6 =140, DQ7 =140
8262 19:29:53.574455 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118
8263 19:29:53.577556 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =136
8264 19:29:53.577639
8265 19:29:53.577704
8266 19:29:53.577764
8267 19:29:53.580720 [DramC_TX_OE_Calibration] TA2
8268 19:29:53.584414 Original DQ_B0 (3 6) =30, OEN = 27
8269 19:29:53.587718 Original DQ_B1 (3 6) =30, OEN = 27
8270 19:29:53.590763 24, 0x0, End_B0=24 End_B1=24
8271 19:29:53.594056 25, 0x0, End_B0=25 End_B1=25
8272 19:29:53.594140 26, 0x0, End_B0=26 End_B1=26
8273 19:29:53.597587 27, 0x0, End_B0=27 End_B1=27
8274 19:29:53.600772 28, 0x0, End_B0=28 End_B1=28
8275 19:29:53.603869 29, 0x0, End_B0=29 End_B1=29
8276 19:29:53.607160 30, 0x0, End_B0=30 End_B1=30
8277 19:29:53.607243 31, 0x4545, End_B0=30 End_B1=30
8278 19:29:53.610807 Byte0 end_step=30 best_step=27
8279 19:29:53.613776 Byte1 end_step=30 best_step=27
8280 19:29:53.616999 Byte0 TX OE(2T, 0.5T) = (3, 3)
8281 19:29:53.620936 Byte1 TX OE(2T, 0.5T) = (3, 3)
8282 19:29:53.621035
8283 19:29:53.621124
8284 19:29:53.627106 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f07, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 394 ps
8285 19:29:53.630685 CH0 RK1: MR19=303, MR18=1F07
8286 19:29:53.637330 CH0_RK1: MR19=0x303, MR18=0x1F07, DQSOSC=394, MR23=63, INC=23, DEC=15
8287 19:29:53.640359 [RxdqsGatingPostProcess] freq 1600
8288 19:29:53.647473 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8289 19:29:53.647556 best DQS0 dly(2T, 0.5T) = (1, 1)
8290 19:29:53.650325 best DQS1 dly(2T, 0.5T) = (1, 1)
8291 19:29:53.654035 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8292 19:29:53.657445 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8293 19:29:53.660534 best DQS0 dly(2T, 0.5T) = (1, 1)
8294 19:29:53.663423 best DQS1 dly(2T, 0.5T) = (1, 1)
8295 19:29:53.666898 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8296 19:29:53.670355 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8297 19:29:53.673322 Pre-setting of DQS Precalculation
8298 19:29:53.677016 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8299 19:29:53.677102 ==
8300 19:29:53.680410 Dram Type= 6, Freq= 0, CH_1, rank 0
8301 19:29:53.686989 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8302 19:29:53.687074 ==
8303 19:29:53.690128 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8304 19:29:53.697075 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8305 19:29:53.700081 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8306 19:29:53.706777 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8307 19:29:53.714509 [CA 0] Center 42 (13~72) winsize 60
8308 19:29:53.717468 [CA 1] Center 42 (12~72) winsize 61
8309 19:29:53.721089 [CA 2] Center 38 (9~68) winsize 60
8310 19:29:53.724250 [CA 3] Center 38 (9~67) winsize 59
8311 19:29:53.727559 [CA 4] Center 38 (9~68) winsize 60
8312 19:29:53.730673 [CA 5] Center 37 (8~67) winsize 60
8313 19:29:53.730748
8314 19:29:53.734239 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8315 19:29:53.734347
8316 19:29:53.737386 [CATrainingPosCal] consider 1 rank data
8317 19:29:53.740569 u2DelayCellTimex100 = 290/100 ps
8318 19:29:53.747418 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8319 19:29:53.750606 CA1 delay=42 (12~72),Diff = 5 PI (16 cell)
8320 19:29:53.754233 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8321 19:29:53.757398 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8322 19:29:53.761199 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8323 19:29:53.763983 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8324 19:29:53.764064
8325 19:29:53.767311 CA PerBit enable=1, Macro0, CA PI delay=37
8326 19:29:53.767395
8327 19:29:53.770420 [CBTSetCACLKResult] CA Dly = 37
8328 19:29:53.773962 CS Dly: 11 (0~42)
8329 19:29:53.777491 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8330 19:29:53.780471 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8331 19:29:53.780554 ==
8332 19:29:53.784050 Dram Type= 6, Freq= 0, CH_1, rank 1
8333 19:29:53.787087 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8334 19:29:53.790489 ==
8335 19:29:53.794081 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8336 19:29:53.797215 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8337 19:29:53.803597 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8338 19:29:53.810243 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8339 19:29:53.817710 [CA 0] Center 42 (12~72) winsize 61
8340 19:29:53.821133 [CA 1] Center 42 (12~72) winsize 61
8341 19:29:53.824784 [CA 2] Center 38 (9~68) winsize 60
8342 19:29:53.827613 [CA 3] Center 38 (8~68) winsize 61
8343 19:29:53.831153 [CA 4] Center 38 (8~68) winsize 61
8344 19:29:53.834548 [CA 5] Center 37 (7~67) winsize 61
8345 19:29:53.834630
8346 19:29:53.837433 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8347 19:29:53.837518
8348 19:29:53.841029 [CATrainingPosCal] consider 2 rank data
8349 19:29:53.844044 u2DelayCellTimex100 = 290/100 ps
8350 19:29:53.847211 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8351 19:29:53.854241 CA1 delay=42 (12~72),Diff = 5 PI (16 cell)
8352 19:29:53.857395 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8353 19:29:53.860416 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8354 19:29:53.864199 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8355 19:29:53.867116 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8356 19:29:53.867197
8357 19:29:53.871196 CA PerBit enable=1, Macro0, CA PI delay=37
8358 19:29:53.871279
8359 19:29:53.874379 [CBTSetCACLKResult] CA Dly = 37
8360 19:29:53.877442 CS Dly: 12 (0~45)
8361 19:29:53.881012 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8362 19:29:53.884046 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8363 19:29:53.884129
8364 19:29:53.887831 ----->DramcWriteLeveling(PI) begin...
8365 19:29:53.887940 ==
8366 19:29:53.890638 Dram Type= 6, Freq= 0, CH_1, rank 0
8367 19:29:53.894141 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8368 19:29:53.897484 ==
8369 19:29:53.897566 Write leveling (Byte 0): 25 => 25
8370 19:29:53.900451 Write leveling (Byte 1): 26 => 26
8371 19:29:53.904070 DramcWriteLeveling(PI) end<-----
8372 19:29:53.904152
8373 19:29:53.904216 ==
8374 19:29:53.910515 Dram Type= 6, Freq= 0, CH_1, rank 0
8375 19:29:53.914259 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8376 19:29:53.914382 ==
8377 19:29:53.914447 [Gating] SW mode calibration
8378 19:29:53.924045 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8379 19:29:53.927094 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8380 19:29:53.931117 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8381 19:29:53.937122 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8382 19:29:53.940882 1 4 8 | B1->B0 | 2323 2423 | 0 1 | (0 0) (1 1)
8383 19:29:53.943624 1 4 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8384 19:29:53.950615 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8385 19:29:53.953555 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8386 19:29:53.956961 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8387 19:29:53.963595 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8388 19:29:53.967187 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8389 19:29:53.970344 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8390 19:29:53.976845 1 5 8 | B1->B0 | 3434 2e2e | 1 0 | (1 0) (0 0)
8391 19:29:53.980643 1 5 12 | B1->B0 | 2929 2323 | 0 0 | (0 1) (1 0)
8392 19:29:53.983579 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8393 19:29:53.990339 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8394 19:29:53.993358 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8395 19:29:53.996999 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8396 19:29:54.003652 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8397 19:29:54.007038 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8398 19:29:54.010093 1 6 8 | B1->B0 | 2323 2f2e | 0 1 | (0 0) (0 0)
8399 19:29:54.016859 1 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8400 19:29:54.020023 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8401 19:29:54.023263 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8402 19:29:54.029956 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8403 19:29:54.033549 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8404 19:29:54.036590 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8405 19:29:54.043187 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8406 19:29:54.046865 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8407 19:29:54.050071 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8408 19:29:54.056952 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8409 19:29:54.059877 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 19:29:54.063294 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 19:29:54.069896 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 19:29:54.073111 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 19:29:54.076561 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8414 19:29:54.083068 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8415 19:29:54.086214 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8416 19:29:54.089886 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8417 19:29:54.096612 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8418 19:29:54.099742 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8419 19:29:54.103446 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8420 19:29:54.106522 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8421 19:29:54.113038 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8422 19:29:54.116439 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8423 19:29:54.119592 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8424 19:29:54.126656 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8425 19:29:54.129629 Total UI for P1: 0, mck2ui 16
8426 19:29:54.132750 best dqsien dly found for B1: ( 1, 9, 10)
8427 19:29:54.136409 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8428 19:29:54.139493 Total UI for P1: 0, mck2ui 16
8429 19:29:54.143354 best dqsien dly found for B0: ( 1, 9, 12)
8430 19:29:54.146291 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8431 19:29:54.149623 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8432 19:29:54.149706
8433 19:29:54.152971 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8434 19:29:54.159374 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8435 19:29:54.159459 [Gating] SW calibration Done
8436 19:29:54.159527 ==
8437 19:29:54.162787 Dram Type= 6, Freq= 0, CH_1, rank 0
8438 19:29:54.169585 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8439 19:29:54.169670 ==
8440 19:29:54.169736 RX Vref Scan: 0
8441 19:29:54.169797
8442 19:29:54.172660 RX Vref 0 -> 0, step: 1
8443 19:29:54.172742
8444 19:29:54.176085 RX Delay 0 -> 252, step: 8
8445 19:29:54.179475 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8446 19:29:54.182560 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8447 19:29:54.185823 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8448 19:29:54.189178 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8449 19:29:54.196000 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8450 19:29:54.199449 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8451 19:29:54.203057 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8452 19:29:54.206452 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8453 19:29:54.209873 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8454 19:29:54.216313 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8455 19:29:54.219120 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8456 19:29:54.222888 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8457 19:29:54.225827 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8458 19:29:54.229558 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8459 19:29:54.235990 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8460 19:29:54.238900 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8461 19:29:54.238983 ==
8462 19:29:54.242702 Dram Type= 6, Freq= 0, CH_1, rank 0
8463 19:29:54.245743 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8464 19:29:54.245826 ==
8465 19:29:54.249540 DQS Delay:
8466 19:29:54.249623 DQS0 = 0, DQS1 = 0
8467 19:29:54.249689 DQM Delay:
8468 19:29:54.252480 DQM0 = 136, DQM1 = 132
8469 19:29:54.252562 DQ Delay:
8470 19:29:54.255636 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8471 19:29:54.259629 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8472 19:29:54.262293 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8473 19:29:54.269160 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139
8474 19:29:54.269247
8475 19:29:54.269312
8476 19:29:54.269372 ==
8477 19:29:54.272356 Dram Type= 6, Freq= 0, CH_1, rank 0
8478 19:29:54.275742 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8479 19:29:54.275825 ==
8480 19:29:54.275891
8481 19:29:54.275951
8482 19:29:54.279231 TX Vref Scan disable
8483 19:29:54.279314 == TX Byte 0 ==
8484 19:29:54.286079 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8485 19:29:54.288933 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8486 19:29:54.289016 == TX Byte 1 ==
8487 19:29:54.295951 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8488 19:29:54.299197 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8489 19:29:54.299281 ==
8490 19:29:54.302886 Dram Type= 6, Freq= 0, CH_1, rank 0
8491 19:29:54.305431 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8492 19:29:54.305515 ==
8493 19:29:54.320454
8494 19:29:54.323343 TX Vref early break, caculate TX vref
8495 19:29:54.326981 TX Vref=16, minBit 0, minWin=23, winSum=380
8496 19:29:54.330337 TX Vref=18, minBit 1, minWin=23, winSum=392
8497 19:29:54.333687 TX Vref=20, minBit 3, minWin=24, winSum=406
8498 19:29:54.337049 TX Vref=22, minBit 1, minWin=25, winSum=411
8499 19:29:54.340040 TX Vref=24, minBit 0, minWin=25, winSum=420
8500 19:29:54.346740 TX Vref=26, minBit 0, minWin=25, winSum=426
8501 19:29:54.349909 TX Vref=28, minBit 0, minWin=25, winSum=426
8502 19:29:54.353504 TX Vref=30, minBit 0, minWin=25, winSum=421
8503 19:29:54.356772 TX Vref=32, minBit 6, minWin=24, winSum=416
8504 19:29:54.359898 TX Vref=34, minBit 0, minWin=24, winSum=404
8505 19:29:54.363110 TX Vref=36, minBit 0, minWin=23, winSum=398
8506 19:29:54.370204 [TxChooseVref] Worse bit 0, Min win 25, Win sum 426, Final Vref 26
8507 19:29:54.370288
8508 19:29:54.373300 Final TX Range 0 Vref 26
8509 19:29:54.373383
8510 19:29:54.373448 ==
8511 19:29:54.376748 Dram Type= 6, Freq= 0, CH_1, rank 0
8512 19:29:54.379773 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8513 19:29:54.379857 ==
8514 19:29:54.379922
8515 19:29:54.382805
8516 19:29:54.382887 TX Vref Scan disable
8517 19:29:54.389668 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8518 19:29:54.389752 == TX Byte 0 ==
8519 19:29:54.393348 u2DelayCellOfst[0]=16 cells (5 PI)
8520 19:29:54.396403 u2DelayCellOfst[1]=10 cells (3 PI)
8521 19:29:54.399566 u2DelayCellOfst[2]=0 cells (0 PI)
8522 19:29:54.402804 u2DelayCellOfst[3]=6 cells (2 PI)
8523 19:29:54.406358 u2DelayCellOfst[4]=6 cells (2 PI)
8524 19:29:54.409941 u2DelayCellOfst[5]=16 cells (5 PI)
8525 19:29:54.412983 u2DelayCellOfst[6]=16 cells (5 PI)
8526 19:29:54.416016 u2DelayCellOfst[7]=3 cells (1 PI)
8527 19:29:54.419414 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8528 19:29:54.422983 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8529 19:29:54.426038 == TX Byte 1 ==
8530 19:29:54.429394 u2DelayCellOfst[8]=0 cells (0 PI)
8531 19:29:54.429516 u2DelayCellOfst[9]=3 cells (1 PI)
8532 19:29:54.433209 u2DelayCellOfst[10]=13 cells (4 PI)
8533 19:29:54.436522 u2DelayCellOfst[11]=3 cells (1 PI)
8534 19:29:54.439688 u2DelayCellOfst[12]=16 cells (5 PI)
8535 19:29:54.442633 u2DelayCellOfst[13]=16 cells (5 PI)
8536 19:29:54.445993 u2DelayCellOfst[14]=16 cells (5 PI)
8537 19:29:54.449151 u2DelayCellOfst[15]=16 cells (5 PI)
8538 19:29:54.456092 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8539 19:29:54.459185 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8540 19:29:54.459334 DramC Write-DBI on
8541 19:29:54.459424 ==
8542 19:29:54.462891 Dram Type= 6, Freq= 0, CH_1, rank 0
8543 19:29:54.469539 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8544 19:29:54.469628 ==
8545 19:29:54.469694
8546 19:29:54.469754
8547 19:29:54.469812 TX Vref Scan disable
8548 19:29:54.473569 == TX Byte 0 ==
8549 19:29:54.476659 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8550 19:29:54.479800 == TX Byte 1 ==
8551 19:29:54.482958 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8552 19:29:54.486679 DramC Write-DBI off
8553 19:29:54.486763
8554 19:29:54.486827 [DATLAT]
8555 19:29:54.486887 Freq=1600, CH1 RK0
8556 19:29:54.486944
8557 19:29:54.489642 DATLAT Default: 0xf
8558 19:29:54.489724 0, 0xFFFF, sum = 0
8559 19:29:54.492893 1, 0xFFFF, sum = 0
8560 19:29:54.496366 2, 0xFFFF, sum = 0
8561 19:29:54.496449 3, 0xFFFF, sum = 0
8562 19:29:54.500132 4, 0xFFFF, sum = 0
8563 19:29:54.500216 5, 0xFFFF, sum = 0
8564 19:29:54.503221 6, 0xFFFF, sum = 0
8565 19:29:54.503304 7, 0xFFFF, sum = 0
8566 19:29:54.506611 8, 0xFFFF, sum = 0
8567 19:29:54.506694 9, 0xFFFF, sum = 0
8568 19:29:54.509590 10, 0xFFFF, sum = 0
8569 19:29:54.509673 11, 0xFFFF, sum = 0
8570 19:29:54.512780 12, 0xFFFF, sum = 0
8571 19:29:54.512863 13, 0xFFFF, sum = 0
8572 19:29:54.516293 14, 0x0, sum = 1
8573 19:29:54.516377 15, 0x0, sum = 2
8574 19:29:54.519820 16, 0x0, sum = 3
8575 19:29:54.519903 17, 0x0, sum = 4
8576 19:29:54.523399 best_step = 15
8577 19:29:54.523480
8578 19:29:54.523545 ==
8579 19:29:54.526068 Dram Type= 6, Freq= 0, CH_1, rank 0
8580 19:29:54.529804 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8581 19:29:54.529886 ==
8582 19:29:54.532920 RX Vref Scan: 1
8583 19:29:54.533002
8584 19:29:54.533067 Set Vref Range= 24 -> 127
8585 19:29:54.533127
8586 19:29:54.536174 RX Vref 24 -> 127, step: 1
8587 19:29:54.536256
8588 19:29:54.539780 RX Delay 27 -> 252, step: 4
8589 19:29:54.539861
8590 19:29:54.542542 Set Vref, RX VrefLevel [Byte0]: 24
8591 19:29:54.546009 [Byte1]: 24
8592 19:29:54.546090
8593 19:29:54.549534 Set Vref, RX VrefLevel [Byte0]: 25
8594 19:29:54.553142 [Byte1]: 25
8595 19:29:54.553227
8596 19:29:54.556262 Set Vref, RX VrefLevel [Byte0]: 26
8597 19:29:54.559402 [Byte1]: 26
8598 19:29:54.563657
8599 19:29:54.563739 Set Vref, RX VrefLevel [Byte0]: 27
8600 19:29:54.566574 [Byte1]: 27
8601 19:29:54.571126
8602 19:29:54.571208 Set Vref, RX VrefLevel [Byte0]: 28
8603 19:29:54.574082 [Byte1]: 28
8604 19:29:54.578557
8605 19:29:54.578642 Set Vref, RX VrefLevel [Byte0]: 29
8606 19:29:54.581717 [Byte1]: 29
8607 19:29:54.585842
8608 19:29:54.585924 Set Vref, RX VrefLevel [Byte0]: 30
8609 19:29:54.589598 [Byte1]: 30
8610 19:29:54.593866
8611 19:29:54.593948 Set Vref, RX VrefLevel [Byte0]: 31
8612 19:29:54.597094 [Byte1]: 31
8613 19:29:54.601454
8614 19:29:54.601535 Set Vref, RX VrefLevel [Byte0]: 32
8615 19:29:54.604575 [Byte1]: 32
8616 19:29:54.608342
8617 19:29:54.608423 Set Vref, RX VrefLevel [Byte0]: 33
8618 19:29:54.612372 [Byte1]: 33
8619 19:29:54.616102
8620 19:29:54.616185 Set Vref, RX VrefLevel [Byte0]: 34
8621 19:29:54.619264 [Byte1]: 34
8622 19:29:54.623543
8623 19:29:54.623625 Set Vref, RX VrefLevel [Byte0]: 35
8624 19:29:54.627027 [Byte1]: 35
8625 19:29:54.631112
8626 19:29:54.631194 Set Vref, RX VrefLevel [Byte0]: 36
8627 19:29:54.634581 [Byte1]: 36
8628 19:29:54.638723
8629 19:29:54.638807 Set Vref, RX VrefLevel [Byte0]: 37
8630 19:29:54.641884 [Byte1]: 37
8631 19:29:54.646655
8632 19:29:54.646737 Set Vref, RX VrefLevel [Byte0]: 38
8633 19:29:54.649387 [Byte1]: 38
8634 19:29:54.653962
8635 19:29:54.654044 Set Vref, RX VrefLevel [Byte0]: 39
8636 19:29:54.656831 [Byte1]: 39
8637 19:29:54.661204
8638 19:29:54.661288 Set Vref, RX VrefLevel [Byte0]: 40
8639 19:29:54.664643 [Byte1]: 40
8640 19:29:54.669027
8641 19:29:54.669109 Set Vref, RX VrefLevel [Byte0]: 41
8642 19:29:54.672147 [Byte1]: 41
8643 19:29:54.676629
8644 19:29:54.676710 Set Vref, RX VrefLevel [Byte0]: 42
8645 19:29:54.683000 [Byte1]: 42
8646 19:29:54.683082
8647 19:29:54.686498 Set Vref, RX VrefLevel [Byte0]: 43
8648 19:29:54.689278 [Byte1]: 43
8649 19:29:54.689360
8650 19:29:54.692534 Set Vref, RX VrefLevel [Byte0]: 44
8651 19:29:54.696193 [Byte1]: 44
8652 19:29:54.696276
8653 19:29:54.699653 Set Vref, RX VrefLevel [Byte0]: 45
8654 19:29:54.702663 [Byte1]: 45
8655 19:29:54.706334
8656 19:29:54.706424 Set Vref, RX VrefLevel [Byte0]: 46
8657 19:29:54.709707 [Byte1]: 46
8658 19:29:54.714090
8659 19:29:54.714164 Set Vref, RX VrefLevel [Byte0]: 47
8660 19:29:54.717251 [Byte1]: 47
8661 19:29:54.721691
8662 19:29:54.721763 Set Vref, RX VrefLevel [Byte0]: 48
8663 19:29:54.724794 [Byte1]: 48
8664 19:29:54.729330
8665 19:29:54.729429 Set Vref, RX VrefLevel [Byte0]: 49
8666 19:29:54.732322 [Byte1]: 49
8667 19:29:54.736977
8668 19:29:54.737060 Set Vref, RX VrefLevel [Byte0]: 50
8669 19:29:54.740235 [Byte1]: 50
8670 19:29:54.743912
8671 19:29:54.743993 Set Vref, RX VrefLevel [Byte0]: 51
8672 19:29:54.747715 [Byte1]: 51
8673 19:29:54.751420
8674 19:29:54.751501 Set Vref, RX VrefLevel [Byte0]: 52
8675 19:29:54.755522 [Byte1]: 52
8676 19:29:54.759110
8677 19:29:54.759191 Set Vref, RX VrefLevel [Byte0]: 53
8678 19:29:54.762471 [Byte1]: 53
8679 19:29:54.766577
8680 19:29:54.766656 Set Vref, RX VrefLevel [Byte0]: 54
8681 19:29:54.769836 [Byte1]: 54
8682 19:29:54.774669
8683 19:29:54.774754 Set Vref, RX VrefLevel [Byte0]: 55
8684 19:29:54.777703 [Byte1]: 55
8685 19:29:54.781601
8686 19:29:54.781688 Set Vref, RX VrefLevel [Byte0]: 56
8687 19:29:54.785363 [Byte1]: 56
8688 19:29:54.789689
8689 19:29:54.789770 Set Vref, RX VrefLevel [Byte0]: 57
8690 19:29:54.793108 [Byte1]: 57
8691 19:29:54.796849
8692 19:29:54.796932 Set Vref, RX VrefLevel [Byte0]: 58
8693 19:29:54.800025 [Byte1]: 58
8694 19:29:54.804702
8695 19:29:54.804784 Set Vref, RX VrefLevel [Byte0]: 59
8696 19:29:54.807567 [Byte1]: 59
8697 19:29:54.811938
8698 19:29:54.812040 Set Vref, RX VrefLevel [Byte0]: 60
8699 19:29:54.815043 [Byte1]: 60
8700 19:29:54.819307
8701 19:29:54.819416 Set Vref, RX VrefLevel [Byte0]: 61
8702 19:29:54.823006 [Byte1]: 61
8703 19:29:54.826934
8704 19:29:54.827016 Set Vref, RX VrefLevel [Byte0]: 62
8705 19:29:54.830668 [Byte1]: 62
8706 19:29:54.834723
8707 19:29:54.834804 Set Vref, RX VrefLevel [Byte0]: 63
8708 19:29:54.837683 [Byte1]: 63
8709 19:29:54.841833
8710 19:29:54.841915 Set Vref, RX VrefLevel [Byte0]: 64
8711 19:29:54.845232 [Byte1]: 64
8712 19:29:54.849738
8713 19:29:54.849820 Set Vref, RX VrefLevel [Byte0]: 65
8714 19:29:54.852950 [Byte1]: 65
8715 19:29:54.857154
8716 19:29:54.857258 Set Vref, RX VrefLevel [Byte0]: 66
8717 19:29:54.860470 [Byte1]: 66
8718 19:29:54.865024
8719 19:29:54.865107 Set Vref, RX VrefLevel [Byte0]: 67
8720 19:29:54.867994 [Byte1]: 67
8721 19:29:54.872648
8722 19:29:54.872730 Set Vref, RX VrefLevel [Byte0]: 68
8723 19:29:54.875561 [Byte1]: 68
8724 19:29:54.879584
8725 19:29:54.879665 Set Vref, RX VrefLevel [Byte0]: 69
8726 19:29:54.883381 [Byte1]: 69
8727 19:29:54.887219
8728 19:29:54.887300 Set Vref, RX VrefLevel [Byte0]: 70
8729 19:29:54.890690 [Byte1]: 70
8730 19:29:54.894582
8731 19:29:54.894663 Set Vref, RX VrefLevel [Byte0]: 71
8732 19:29:54.898291 [Byte1]: 71
8733 19:29:54.902088
8734 19:29:54.902189 Set Vref, RX VrefLevel [Byte0]: 72
8735 19:29:54.905375 [Byte1]: 72
8736 19:29:54.909813
8737 19:29:54.912928 Set Vref, RX VrefLevel [Byte0]: 73
8738 19:29:54.913011 [Byte1]: 73
8739 19:29:54.917419
8740 19:29:54.917534 Set Vref, RX VrefLevel [Byte0]: 74
8741 19:29:54.921602 [Byte1]: 74
8742 19:29:54.924824
8743 19:29:54.924938 Set Vref, RX VrefLevel [Byte0]: 75
8744 19:29:54.928477 [Byte1]: 75
8745 19:29:54.932331
8746 19:29:54.932445 Set Vref, RX VrefLevel [Byte0]: 76
8747 19:29:54.935554 [Byte1]: 76
8748 19:29:54.939959
8749 19:29:54.940047 Final RX Vref Byte 0 = 57 to rank0
8750 19:29:54.943470 Final RX Vref Byte 1 = 56 to rank0
8751 19:29:54.946266 Final RX Vref Byte 0 = 57 to rank1
8752 19:29:54.949750 Final RX Vref Byte 1 = 56 to rank1==
8753 19:29:54.952993 Dram Type= 6, Freq= 0, CH_1, rank 0
8754 19:29:54.959623 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8755 19:29:54.959705 ==
8756 19:29:54.959770 DQS Delay:
8757 19:29:54.963177 DQS0 = 0, DQS1 = 0
8758 19:29:54.963258 DQM Delay:
8759 19:29:54.963322 DQM0 = 134, DQM1 = 131
8760 19:29:54.966658 DQ Delay:
8761 19:29:54.970111 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8762 19:29:54.973315 DQ4 =134, DQ5 =144, DQ6 =144, DQ7 =132
8763 19:29:54.976444 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8764 19:29:54.979560 DQ12 =138, DQ13 =138, DQ14 =140, DQ15 =140
8765 19:29:54.979641
8766 19:29:54.979705
8767 19:29:54.979764
8768 19:29:54.983255 [DramC_TX_OE_Calibration] TA2
8769 19:29:54.986230 Original DQ_B0 (3 6) =30, OEN = 27
8770 19:29:54.989992 Original DQ_B1 (3 6) =30, OEN = 27
8771 19:29:54.993033 24, 0x0, End_B0=24 End_B1=24
8772 19:29:54.993115 25, 0x0, End_B0=25 End_B1=25
8773 19:29:54.996225 26, 0x0, End_B0=26 End_B1=26
8774 19:29:54.999814 27, 0x0, End_B0=27 End_B1=27
8775 19:29:55.002771 28, 0x0, End_B0=28 End_B1=28
8776 19:29:55.005910 29, 0x0, End_B0=29 End_B1=29
8777 19:29:55.005992 30, 0x0, End_B0=30 End_B1=30
8778 19:29:55.009114 31, 0x4141, End_B0=30 End_B1=30
8779 19:29:55.012960 Byte0 end_step=30 best_step=27
8780 19:29:55.016060 Byte1 end_step=30 best_step=27
8781 19:29:55.019278 Byte0 TX OE(2T, 0.5T) = (3, 3)
8782 19:29:55.022430 Byte1 TX OE(2T, 0.5T) = (3, 3)
8783 19:29:55.022511
8784 19:29:55.022574
8785 19:29:55.029358 [DQSOSCAuto] RK0, (LSB)MR18= 0x1523, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
8786 19:29:55.032561 CH1 RK0: MR19=303, MR18=1523
8787 19:29:55.039392 CH1_RK0: MR19=0x303, MR18=0x1523, DQSOSC=392, MR23=63, INC=24, DEC=16
8788 19:29:55.039473
8789 19:29:55.042588 ----->DramcWriteLeveling(PI) begin...
8790 19:29:55.042670 ==
8791 19:29:55.045631 Dram Type= 6, Freq= 0, CH_1, rank 1
8792 19:29:55.049170 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8793 19:29:55.049252 ==
8794 19:29:55.052604 Write leveling (Byte 0): 25 => 25
8795 19:29:55.055630 Write leveling (Byte 1): 28 => 28
8796 19:29:55.059211 DramcWriteLeveling(PI) end<-----
8797 19:29:55.059295
8798 19:29:55.059379 ==
8799 19:29:55.062684 Dram Type= 6, Freq= 0, CH_1, rank 1
8800 19:29:55.065747 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8801 19:29:55.065831 ==
8802 19:29:55.068801 [Gating] SW mode calibration
8803 19:29:55.075609 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8804 19:29:55.082917 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8805 19:29:55.085680 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8806 19:29:55.092222 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8807 19:29:55.095956 1 4 8 | B1->B0 | 2929 2323 | 1 0 | (0 0) (0 0)
8808 19:29:55.099403 1 4 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
8809 19:29:55.105788 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8810 19:29:55.109260 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8811 19:29:55.112993 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8812 19:29:55.118996 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8813 19:29:55.122012 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8814 19:29:55.125845 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8815 19:29:55.129022 1 5 8 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 1)
8816 19:29:55.135397 1 5 12 | B1->B0 | 2323 2828 | 0 1 | (0 0) (1 0)
8817 19:29:55.138570 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
8818 19:29:55.142356 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8819 19:29:55.148552 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8820 19:29:55.152259 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8821 19:29:55.155666 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8822 19:29:55.161662 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8823 19:29:55.165524 1 6 8 | B1->B0 | 4141 2323 | 0 0 | (0 0) (0 0)
8824 19:29:55.168635 1 6 12 | B1->B0 | 4646 4545 | 0 1 | (0 0) (0 0)
8825 19:29:55.175211 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8826 19:29:55.178567 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8827 19:29:55.182084 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8828 19:29:55.188330 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8829 19:29:55.191611 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8830 19:29:55.194787 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8831 19:29:55.201916 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8832 19:29:55.205098 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8833 19:29:55.208455 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8834 19:29:55.214937 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8835 19:29:55.218242 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8836 19:29:55.221290 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8837 19:29:55.227931 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8838 19:29:55.231871 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8839 19:29:55.234700 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8840 19:29:55.241121 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8841 19:29:55.245123 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8842 19:29:55.248025 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8843 19:29:55.254546 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8844 19:29:55.257674 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8845 19:29:55.261255 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8846 19:29:55.267565 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8847 19:29:55.271198 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8848 19:29:55.274465 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8849 19:29:55.277646 Total UI for P1: 0, mck2ui 16
8850 19:29:55.281230 best dqsien dly found for B1: ( 1, 9, 6)
8851 19:29:55.287593 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8852 19:29:55.291004 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8853 19:29:55.294643 Total UI for P1: 0, mck2ui 16
8854 19:29:55.297615 best dqsien dly found for B0: ( 1, 9, 14)
8855 19:29:55.300911 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8856 19:29:55.304414 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8857 19:29:55.304501
8858 19:29:55.307459 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8859 19:29:55.311042 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8860 19:29:55.314191 [Gating] SW calibration Done
8861 19:29:55.314276 ==
8862 19:29:55.318037 Dram Type= 6, Freq= 0, CH_1, rank 1
8863 19:29:55.320771 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8864 19:29:55.324404 ==
8865 19:29:55.324487 RX Vref Scan: 0
8866 19:29:55.324571
8867 19:29:55.327420 RX Vref 0 -> 0, step: 1
8868 19:29:55.327504
8869 19:29:55.327587 RX Delay 0 -> 252, step: 8
8870 19:29:55.334036 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8871 19:29:55.337587 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8872 19:29:55.340862 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8873 19:29:55.344126 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8874 19:29:55.347599 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8875 19:29:55.354574 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8876 19:29:55.357366 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8877 19:29:55.360569 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8878 19:29:55.364384 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8879 19:29:55.367584 iDelay=208, Bit 9, Center 123 (72 ~ 175) 104
8880 19:29:55.374047 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8881 19:29:55.377442 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8882 19:29:55.380926 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8883 19:29:55.384164 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8884 19:29:55.387252 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8885 19:29:55.393939 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8886 19:29:55.394023 ==
8887 19:29:55.397513 Dram Type= 6, Freq= 0, CH_1, rank 1
8888 19:29:55.400519 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8889 19:29:55.400603 ==
8890 19:29:55.400687 DQS Delay:
8891 19:29:55.403967 DQS0 = 0, DQS1 = 0
8892 19:29:55.404052 DQM Delay:
8893 19:29:55.407455 DQM0 = 136, DQM1 = 134
8894 19:29:55.407541 DQ Delay:
8895 19:29:55.410561 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8896 19:29:55.413502 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8897 19:29:55.417213 DQ8 =119, DQ9 =123, DQ10 =135, DQ11 =127
8898 19:29:55.423584 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8899 19:29:55.423668
8900 19:29:55.423753
8901 19:29:55.423831 ==
8902 19:29:55.427498 Dram Type= 6, Freq= 0, CH_1, rank 1
8903 19:29:55.430518 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8904 19:29:55.430603 ==
8905 19:29:55.430687
8906 19:29:55.430765
8907 19:29:55.433792 TX Vref Scan disable
8908 19:29:55.433876 == TX Byte 0 ==
8909 19:29:55.440630 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8910 19:29:55.444238 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8911 19:29:55.444323 == TX Byte 1 ==
8912 19:29:55.450340 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8913 19:29:55.453847 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8914 19:29:55.453928 ==
8915 19:29:55.456803 Dram Type= 6, Freq= 0, CH_1, rank 1
8916 19:29:55.460179 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8917 19:29:55.460262 ==
8918 19:29:55.473836
8919 19:29:55.476872 TX Vref early break, caculate TX vref
8920 19:29:55.480391 TX Vref=16, minBit 0, minWin=23, winSum=382
8921 19:29:55.483992 TX Vref=18, minBit 0, minWin=23, winSum=393
8922 19:29:55.487208 TX Vref=20, minBit 0, minWin=24, winSum=396
8923 19:29:55.490268 TX Vref=22, minBit 0, minWin=24, winSum=411
8924 19:29:55.493924 TX Vref=24, minBit 0, minWin=25, winSum=419
8925 19:29:55.500651 TX Vref=26, minBit 0, minWin=25, winSum=428
8926 19:29:55.503757 TX Vref=28, minBit 0, minWin=26, winSum=429
8927 19:29:55.507377 TX Vref=30, minBit 0, minWin=25, winSum=418
8928 19:29:55.510035 TX Vref=32, minBit 0, minWin=25, winSum=412
8929 19:29:55.513453 TX Vref=34, minBit 0, minWin=24, winSum=405
8930 19:29:55.520252 [TxChooseVref] Worse bit 0, Min win 26, Win sum 429, Final Vref 28
8931 19:29:55.520335
8932 19:29:55.523206 Final TX Range 0 Vref 28
8933 19:29:55.523288
8934 19:29:55.523353 ==
8935 19:29:55.526895 Dram Type= 6, Freq= 0, CH_1, rank 1
8936 19:29:55.530054 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8937 19:29:55.530135 ==
8938 19:29:55.530200
8939 19:29:55.530260
8940 19:29:55.533140 TX Vref Scan disable
8941 19:29:55.539883 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8942 19:29:55.539965 == TX Byte 0 ==
8943 19:29:55.543578 u2DelayCellOfst[0]=16 cells (5 PI)
8944 19:29:55.546737 u2DelayCellOfst[1]=10 cells (3 PI)
8945 19:29:55.549981 u2DelayCellOfst[2]=0 cells (0 PI)
8946 19:29:55.553078 u2DelayCellOfst[3]=6 cells (2 PI)
8947 19:29:55.556495 u2DelayCellOfst[4]=10 cells (3 PI)
8948 19:29:55.560041 u2DelayCellOfst[5]=16 cells (5 PI)
8949 19:29:55.563323 u2DelayCellOfst[6]=16 cells (5 PI)
8950 19:29:55.566467 u2DelayCellOfst[7]=6 cells (2 PI)
8951 19:29:55.570110 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8952 19:29:55.573075 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8953 19:29:55.573157 == TX Byte 1 ==
8954 19:29:55.576933 u2DelayCellOfst[8]=0 cells (0 PI)
8955 19:29:55.579804 u2DelayCellOfst[9]=3 cells (1 PI)
8956 19:29:55.582986 u2DelayCellOfst[10]=10 cells (3 PI)
8957 19:29:55.586240 u2DelayCellOfst[11]=3 cells (1 PI)
8958 19:29:55.590066 u2DelayCellOfst[12]=13 cells (4 PI)
8959 19:29:55.593287 u2DelayCellOfst[13]=13 cells (4 PI)
8960 19:29:55.596283 u2DelayCellOfst[14]=16 cells (5 PI)
8961 19:29:55.599769 u2DelayCellOfst[15]=16 cells (5 PI)
8962 19:29:55.603082 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8963 19:29:55.609731 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8964 19:29:55.609812 DramC Write-DBI on
8965 19:29:55.609876 ==
8966 19:29:55.612829 Dram Type= 6, Freq= 0, CH_1, rank 1
8967 19:29:55.615960 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8968 19:29:55.619689 ==
8969 19:29:55.619770
8970 19:29:55.619833
8971 19:29:55.619892 TX Vref Scan disable
8972 19:29:55.623242 == TX Byte 0 ==
8973 19:29:55.626707 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8974 19:29:55.630004 == TX Byte 1 ==
8975 19:29:55.632897 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8976 19:29:55.636557 DramC Write-DBI off
8977 19:29:55.636637
8978 19:29:55.636701 [DATLAT]
8979 19:29:55.636761 Freq=1600, CH1 RK1
8980 19:29:55.636820
8981 19:29:55.639615 DATLAT Default: 0xf
8982 19:29:55.639696 0, 0xFFFF, sum = 0
8983 19:29:55.642673 1, 0xFFFF, sum = 0
8984 19:29:55.646470 2, 0xFFFF, sum = 0
8985 19:29:55.646552 3, 0xFFFF, sum = 0
8986 19:29:55.649605 4, 0xFFFF, sum = 0
8987 19:29:55.649687 5, 0xFFFF, sum = 0
8988 19:29:55.652719 6, 0xFFFF, sum = 0
8989 19:29:55.652801 7, 0xFFFF, sum = 0
8990 19:29:55.656613 8, 0xFFFF, sum = 0
8991 19:29:55.656696 9, 0xFFFF, sum = 0
8992 19:29:55.659804 10, 0xFFFF, sum = 0
8993 19:29:55.659887 11, 0xFFFF, sum = 0
8994 19:29:55.662830 12, 0xFFFF, sum = 0
8995 19:29:55.662914 13, 0xFFFF, sum = 0
8996 19:29:55.665995 14, 0x0, sum = 1
8997 19:29:55.666076 15, 0x0, sum = 2
8998 19:29:55.669755 16, 0x0, sum = 3
8999 19:29:55.669837 17, 0x0, sum = 4
9000 19:29:55.672982 best_step = 15
9001 19:29:55.673061
9002 19:29:55.673125 ==
9003 19:29:55.675842 Dram Type= 6, Freq= 0, CH_1, rank 1
9004 19:29:55.679761 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9005 19:29:55.679842 ==
9006 19:29:55.682740 RX Vref Scan: 0
9007 19:29:55.682820
9008 19:29:55.682884 RX Vref 0 -> 0, step: 1
9009 19:29:55.682944
9010 19:29:55.685730 RX Delay 19 -> 252, step: 4
9011 19:29:55.689215 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
9012 19:29:55.695865 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
9013 19:29:55.699216 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
9014 19:29:55.702856 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
9015 19:29:55.706012 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
9016 19:29:55.709223 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
9017 19:29:55.712526 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
9018 19:29:55.719490 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
9019 19:29:55.722700 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
9020 19:29:55.725753 iDelay=195, Bit 9, Center 120 (67 ~ 174) 108
9021 19:29:55.729376 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
9022 19:29:55.736170 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
9023 19:29:55.739036 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
9024 19:29:55.742198 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9025 19:29:55.745851 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
9026 19:29:55.749418 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
9027 19:29:55.752633 ==
9028 19:29:55.752715 Dram Type= 6, Freq= 0, CH_1, rank 1
9029 19:29:55.758932 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9030 19:29:55.759013 ==
9031 19:29:55.759078 DQS Delay:
9032 19:29:55.762728 DQS0 = 0, DQS1 = 0
9033 19:29:55.762809 DQM Delay:
9034 19:29:55.765804 DQM0 = 134, DQM1 = 130
9035 19:29:55.765885 DQ Delay:
9036 19:29:55.768996 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130
9037 19:29:55.772702 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
9038 19:29:55.776046 DQ8 =116, DQ9 =120, DQ10 =132, DQ11 =124
9039 19:29:55.779291 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
9040 19:29:55.779373
9041 19:29:55.779435
9042 19:29:55.779494
9043 19:29:55.782195 [DramC_TX_OE_Calibration] TA2
9044 19:29:55.785876 Original DQ_B0 (3 6) =30, OEN = 27
9045 19:29:55.788790 Original DQ_B1 (3 6) =30, OEN = 27
9046 19:29:55.792004 24, 0x0, End_B0=24 End_B1=24
9047 19:29:55.795804 25, 0x0, End_B0=25 End_B1=25
9048 19:29:55.795887 26, 0x0, End_B0=26 End_B1=26
9049 19:29:55.798650 27, 0x0, End_B0=27 End_B1=27
9050 19:29:55.802415 28, 0x0, End_B0=28 End_B1=28
9051 19:29:55.805929 29, 0x0, End_B0=29 End_B1=29
9052 19:29:55.806011 30, 0x0, End_B0=30 End_B1=30
9053 19:29:55.808908 31, 0x4141, End_B0=30 End_B1=30
9054 19:29:55.812077 Byte0 end_step=30 best_step=27
9055 19:29:55.815425 Byte1 end_step=30 best_step=27
9056 19:29:55.818641 Byte0 TX OE(2T, 0.5T) = (3, 3)
9057 19:29:55.822193 Byte1 TX OE(2T, 0.5T) = (3, 3)
9058 19:29:55.822274
9059 19:29:55.822344
9060 19:29:55.828555 [DQSOSCAuto] RK1, (LSB)MR18= 0x2106, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 393 ps
9061 19:29:55.831949 CH1 RK1: MR19=303, MR18=2106
9062 19:29:55.838567 CH1_RK1: MR19=0x303, MR18=0x2106, DQSOSC=393, MR23=63, INC=23, DEC=15
9063 19:29:55.841744 [RxdqsGatingPostProcess] freq 1600
9064 19:29:55.845316 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9065 19:29:55.848762 best DQS0 dly(2T, 0.5T) = (1, 1)
9066 19:29:55.851948 best DQS1 dly(2T, 0.5T) = (1, 1)
9067 19:29:55.855314 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9068 19:29:55.858423 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9069 19:29:55.861675 best DQS0 dly(2T, 0.5T) = (1, 1)
9070 19:29:55.865032 best DQS1 dly(2T, 0.5T) = (1, 1)
9071 19:29:55.868296 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9072 19:29:55.871940 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9073 19:29:55.875166 Pre-setting of DQS Precalculation
9074 19:29:55.878193 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9075 19:29:55.884925 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9076 19:29:55.894766 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9077 19:29:55.894856
9078 19:29:55.894920
9079 19:29:55.898658 [Calibration Summary] 3200 Mbps
9080 19:29:55.898740 CH 0, Rank 0
9081 19:29:55.901561 SW Impedance : PASS
9082 19:29:55.901643 DUTY Scan : NO K
9083 19:29:55.905113 ZQ Calibration : PASS
9084 19:29:55.908386 Jitter Meter : NO K
9085 19:29:55.908468 CBT Training : PASS
9086 19:29:55.911654 Write leveling : PASS
9087 19:29:55.914794 RX DQS gating : PASS
9088 19:29:55.914876 RX DQ/DQS(RDDQC) : PASS
9089 19:29:55.918296 TX DQ/DQS : PASS
9090 19:29:55.918419 RX DATLAT : PASS
9091 19:29:55.922028 RX DQ/DQS(Engine): PASS
9092 19:29:55.924663 TX OE : PASS
9093 19:29:55.924745 All Pass.
9094 19:29:55.924809
9095 19:29:55.924869 CH 0, Rank 1
9096 19:29:55.928184 SW Impedance : PASS
9097 19:29:55.931583 DUTY Scan : NO K
9098 19:29:55.931666 ZQ Calibration : PASS
9099 19:29:55.934783 Jitter Meter : NO K
9100 19:29:55.937900 CBT Training : PASS
9101 19:29:55.937982 Write leveling : PASS
9102 19:29:55.941662 RX DQS gating : PASS
9103 19:29:55.944790 RX DQ/DQS(RDDQC) : PASS
9104 19:29:55.944872 TX DQ/DQS : PASS
9105 19:29:55.947835 RX DATLAT : PASS
9106 19:29:55.951501 RX DQ/DQS(Engine): PASS
9107 19:29:55.951583 TX OE : PASS
9108 19:29:55.954624 All Pass.
9109 19:29:55.954706
9110 19:29:55.954770 CH 1, Rank 0
9111 19:29:55.958072 SW Impedance : PASS
9112 19:29:55.958154 DUTY Scan : NO K
9113 19:29:55.960987 ZQ Calibration : PASS
9114 19:29:55.964538 Jitter Meter : NO K
9115 19:29:55.964621 CBT Training : PASS
9116 19:29:55.967615 Write leveling : PASS
9117 19:29:55.971145 RX DQS gating : PASS
9118 19:29:55.971227 RX DQ/DQS(RDDQC) : PASS
9119 19:29:55.974544 TX DQ/DQS : PASS
9120 19:29:55.974627 RX DATLAT : PASS
9121 19:29:55.977786 RX DQ/DQS(Engine): PASS
9122 19:29:55.981156 TX OE : PASS
9123 19:29:55.981239 All Pass.
9124 19:29:55.981304
9125 19:29:55.981365 CH 1, Rank 1
9126 19:29:55.984575 SW Impedance : PASS
9127 19:29:55.987826 DUTY Scan : NO K
9128 19:29:55.987908 ZQ Calibration : PASS
9129 19:29:55.991258 Jitter Meter : NO K
9130 19:29:55.994544 CBT Training : PASS
9131 19:29:55.994625 Write leveling : PASS
9132 19:29:55.997475 RX DQS gating : PASS
9133 19:29:56.001336 RX DQ/DQS(RDDQC) : PASS
9134 19:29:56.001417 TX DQ/DQS : PASS
9135 19:29:56.004431 RX DATLAT : PASS
9136 19:29:56.007546 RX DQ/DQS(Engine): PASS
9137 19:29:56.007628 TX OE : PASS
9138 19:29:56.011357 All Pass.
9139 19:29:56.011438
9140 19:29:56.011502 DramC Write-DBI on
9141 19:29:56.014554 PER_BANK_REFRESH: Hybrid Mode
9142 19:29:56.014636 TX_TRACKING: ON
9143 19:29:56.024809 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9144 19:29:56.033970 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9145 19:29:56.040797 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9146 19:29:56.043910 [FAST_K] Save calibration result to emmc
9147 19:29:56.047683 sync common calibartion params.
9148 19:29:56.047766 sync cbt_mode0:1, 1:1
9149 19:29:56.050798 dram_init: ddr_geometry: 2
9150 19:29:56.053864 dram_init: ddr_geometry: 2
9151 19:29:56.053946 dram_init: ddr_geometry: 2
9152 19:29:56.057735 0:dram_rank_size:100000000
9153 19:29:56.060891 1:dram_rank_size:100000000
9154 19:29:56.067197 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9155 19:29:56.067281 DFS_SHUFFLE_HW_MODE: ON
9156 19:29:56.071105 dramc_set_vcore_voltage set vcore to 725000
9157 19:29:56.074068 Read voltage for 1600, 0
9158 19:29:56.074150 Vio18 = 0
9159 19:29:56.077452 Vcore = 725000
9160 19:29:56.077534 Vdram = 0
9161 19:29:56.077598 Vddq = 0
9162 19:29:56.080573 Vmddr = 0
9163 19:29:56.080655 switch to 3200 Mbps bootup
9164 19:29:56.084333 [DramcRunTimeConfig]
9165 19:29:56.084415 PHYPLL
9166 19:29:56.087190 DPM_CONTROL_AFTERK: ON
9167 19:29:56.087272 PER_BANK_REFRESH: ON
9168 19:29:56.090767 REFRESH_OVERHEAD_REDUCTION: ON
9169 19:29:56.093899 CMD_PICG_NEW_MODE: OFF
9170 19:29:56.093979 XRTWTW_NEW_MODE: ON
9171 19:29:56.097579 XRTRTR_NEW_MODE: ON
9172 19:29:56.097761 TX_TRACKING: ON
9173 19:29:56.100547 RDSEL_TRACKING: OFF
9174 19:29:56.103982 DQS Precalculation for DVFS: ON
9175 19:29:56.104063 RX_TRACKING: OFF
9176 19:29:56.107128 HW_GATING DBG: ON
9177 19:29:56.107209 ZQCS_ENABLE_LP4: ON
9178 19:29:56.110572 RX_PICG_NEW_MODE: ON
9179 19:29:56.110653 TX_PICG_NEW_MODE: ON
9180 19:29:56.113891 ENABLE_RX_DCM_DPHY: ON
9181 19:29:56.117099 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9182 19:29:56.120756 DUMMY_READ_FOR_TRACKING: OFF
9183 19:29:56.120837 !!! SPM_CONTROL_AFTERK: OFF
9184 19:29:56.123945 !!! SPM could not control APHY
9185 19:29:56.127469 IMPEDANCE_TRACKING: ON
9186 19:29:56.127566 TEMP_SENSOR: ON
9187 19:29:56.130587 HW_SAVE_FOR_SR: OFF
9188 19:29:56.133844 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9189 19:29:56.137052 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9190 19:29:56.137133 Read ODT Tracking: ON
9191 19:29:56.140929 Refresh Rate DeBounce: ON
9192 19:29:56.143806 DFS_NO_QUEUE_FLUSH: ON
9193 19:29:56.147389 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9194 19:29:56.147470 ENABLE_DFS_RUNTIME_MRW: OFF
9195 19:29:56.150642 DDR_RESERVE_NEW_MODE: ON
9196 19:29:56.153873 MR_CBT_SWITCH_FREQ: ON
9197 19:29:56.153953 =========================
9198 19:29:56.174074 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9199 19:29:56.177197 dram_init: ddr_geometry: 2
9200 19:29:56.195682 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9201 19:29:56.198914 dram_init: dram init end (result: 0)
9202 19:29:56.205627 DRAM-K: Full calibration passed in 24450 msecs
9203 19:29:56.208657 MRC: failed to locate region type 0.
9204 19:29:56.208740 DRAM rank0 size:0x100000000,
9205 19:29:56.212258 DRAM rank1 size=0x100000000
9206 19:29:56.222340 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9207 19:29:56.229019 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9208 19:29:56.235481 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9209 19:29:56.241722 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9210 19:29:56.245360 DRAM rank0 size:0x100000000,
9211 19:29:56.248958 DRAM rank1 size=0x100000000
9212 19:29:56.249040 CBMEM:
9213 19:29:56.252016 IMD: root @ 0xfffff000 254 entries.
9214 19:29:56.255166 IMD: root @ 0xffffec00 62 entries.
9215 19:29:56.258835 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9216 19:29:56.262240 WARNING: RO_VPD is uninitialized or empty.
9217 19:29:56.268720 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9218 19:29:56.275603 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9219 19:29:56.288639 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9220 19:29:56.299902 BS: romstage times (exec / console): total (unknown) / 23979 ms
9221 19:29:56.299986
9222 19:29:56.300050
9223 19:29:56.309904 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9224 19:29:56.313179 ARM64: Exception handlers installed.
9225 19:29:56.316380 ARM64: Testing exception
9226 19:29:56.319761 ARM64: Done test exception
9227 19:29:56.319844 Enumerating buses...
9228 19:29:56.323273 Show all devs... Before device enumeration.
9229 19:29:56.326269 Root Device: enabled 1
9230 19:29:56.329539 CPU_CLUSTER: 0: enabled 1
9231 19:29:56.329621 CPU: 00: enabled 1
9232 19:29:56.333366 Compare with tree...
9233 19:29:56.333460 Root Device: enabled 1
9234 19:29:56.336410 CPU_CLUSTER: 0: enabled 1
9235 19:29:56.339489 CPU: 00: enabled 1
9236 19:29:56.339572 Root Device scanning...
9237 19:29:56.343130 scan_static_bus for Root Device
9238 19:29:56.346045 CPU_CLUSTER: 0 enabled
9239 19:29:56.349817 scan_static_bus for Root Device done
9240 19:29:56.352718 scan_bus: bus Root Device finished in 8 msecs
9241 19:29:56.352801 done
9242 19:29:56.359404 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9243 19:29:56.363163 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9244 19:29:56.369565 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9245 19:29:56.372811 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9246 19:29:56.375736 Allocating resources...
9247 19:29:56.379946 Reading resources...
9248 19:29:56.382583 Root Device read_resources bus 0 link: 0
9249 19:29:56.382666 DRAM rank0 size:0x100000000,
9250 19:29:56.386288 DRAM rank1 size=0x100000000
9251 19:29:56.389391 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9252 19:29:56.392937 CPU: 00 missing read_resources
9253 19:29:56.396325 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9254 19:29:56.402754 Root Device read_resources bus 0 link: 0 done
9255 19:29:56.402837 Done reading resources.
9256 19:29:56.409692 Show resources in subtree (Root Device)...After reading.
9257 19:29:56.412891 Root Device child on link 0 CPU_CLUSTER: 0
9258 19:29:56.416092 CPU_CLUSTER: 0 child on link 0 CPU: 00
9259 19:29:56.425586 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9260 19:29:56.425668 CPU: 00
9261 19:29:56.429102 Root Device assign_resources, bus 0 link: 0
9262 19:29:56.432242 CPU_CLUSTER: 0 missing set_resources
9263 19:29:56.439078 Root Device assign_resources, bus 0 link: 0 done
9264 19:29:56.439160 Done setting resources.
9265 19:29:56.445803 Show resources in subtree (Root Device)...After assigning values.
9266 19:29:56.449044 Root Device child on link 0 CPU_CLUSTER: 0
9267 19:29:56.452778 CPU_CLUSTER: 0 child on link 0 CPU: 00
9268 19:29:56.462616 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9269 19:29:56.462700 CPU: 00
9270 19:29:56.465688 Done allocating resources.
9271 19:29:56.469072 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9272 19:29:56.472526 Enabling resources...
9273 19:29:56.472608 done.
9274 19:29:56.479092 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9275 19:29:56.479175 Initializing devices...
9276 19:29:56.482232 Root Device init
9277 19:29:56.482373 init hardware done!
9278 19:29:56.485298 0x00000018: ctrlr->caps
9279 19:29:56.488986 52.000 MHz: ctrlr->f_max
9280 19:29:56.489071 0.400 MHz: ctrlr->f_min
9281 19:29:56.492170 0x40ff8080: ctrlr->voltages
9282 19:29:56.492257 sclk: 390625
9283 19:29:56.495924 Bus Width = 1
9284 19:29:56.496006 sclk: 390625
9285 19:29:56.498804 Bus Width = 1
9286 19:29:56.498887 Early init status = 3
9287 19:29:56.505344 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9288 19:29:56.508995 in-header: 03 fc 00 00 01 00 00 00
9289 19:29:56.509077 in-data: 00
9290 19:29:56.515073 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9291 19:29:56.518846 in-header: 03 fd 00 00 00 00 00 00
9292 19:29:56.521862 in-data:
9293 19:29:56.524995 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9294 19:29:56.528856 in-header: 03 fc 00 00 01 00 00 00
9295 19:29:56.532385 in-data: 00
9296 19:29:56.535143 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9297 19:29:56.539718 in-header: 03 fd 00 00 00 00 00 00
9298 19:29:56.543190 in-data:
9299 19:29:56.546396 [SSUSB] Setting up USB HOST controller...
9300 19:29:56.550106 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9301 19:29:56.553220 [SSUSB] phy power-on done.
9302 19:29:56.556231 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9303 19:29:56.563287 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9304 19:29:56.566239 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9305 19:29:56.573080 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9306 19:29:56.579683 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9307 19:29:56.586258 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9308 19:29:56.592825 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9309 19:29:56.599630 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9310 19:29:56.602878 SPM: binary array size = 0x9dc
9311 19:29:56.606630 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9312 19:29:56.613050 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9313 19:29:56.619576 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9314 19:29:56.623085 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9315 19:29:56.629284 configure_display: Starting display init
9316 19:29:56.662897 anx7625_power_on_init: Init interface.
9317 19:29:56.666510 anx7625_disable_pd_protocol: Disabled PD feature.
9318 19:29:56.669579 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9319 19:29:56.697619 anx7625_start_dp_work: Secure OCM version=00
9320 19:29:56.700732 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9321 19:29:56.715806 sp_tx_get_edid_block: EDID Block = 1
9322 19:29:56.818161 Extracted contents:
9323 19:29:56.821491 header: 00 ff ff ff ff ff ff 00
9324 19:29:56.824779 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9325 19:29:56.828163 version: 01 04
9326 19:29:56.831351 basic params: 95 1f 11 78 0a
9327 19:29:56.835034 chroma info: 76 90 94 55 54 90 27 21 50 54
9328 19:29:56.838092 established: 00 00 00
9329 19:29:56.844869 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9330 19:29:56.847928 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9331 19:29:56.854705 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9332 19:29:56.861551 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9333 19:29:56.868203 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9334 19:29:56.871347 extensions: 00
9335 19:29:56.871429 checksum: fb
9336 19:29:56.871493
9337 19:29:56.874620 Manufacturer: IVO Model 57d Serial Number 0
9338 19:29:56.878117 Made week 0 of 2020
9339 19:29:56.878199 EDID version: 1.4
9340 19:29:56.881048 Digital display
9341 19:29:56.884855 6 bits per primary color channel
9342 19:29:56.884939 DisplayPort interface
9343 19:29:56.888065 Maximum image size: 31 cm x 17 cm
9344 19:29:56.891259 Gamma: 220%
9345 19:29:56.891341 Check DPMS levels
9346 19:29:56.894734 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9347 19:29:56.898334 First detailed timing is preferred timing
9348 19:29:56.901539 Established timings supported:
9349 19:29:56.904661 Standard timings supported:
9350 19:29:56.904743 Detailed timings
9351 19:29:56.911117 Hex of detail: 383680a07038204018303c0035ae10000019
9352 19:29:56.915073 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9353 19:29:56.921402 0780 0798 07c8 0820 hborder 0
9354 19:29:56.924329 0438 043b 0447 0458 vborder 0
9355 19:29:56.927850 -hsync -vsync
9356 19:29:56.927933 Did detailed timing
9357 19:29:56.931321 Hex of detail: 000000000000000000000000000000000000
9358 19:29:56.934537 Manufacturer-specified data, tag 0
9359 19:29:56.941105 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9360 19:29:56.941192 ASCII string: InfoVision
9361 19:29:56.947436 Hex of detail: 000000fe00523134304e574635205248200a
9362 19:29:56.950851 ASCII string: R140NWF5 RH
9363 19:29:56.950948 Checksum
9364 19:29:56.951013 Checksum: 0xfb (valid)
9365 19:29:56.957767 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9366 19:29:56.960709 DSI data_rate: 832800000 bps
9367 19:29:56.964629 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9368 19:29:56.970928 anx7625_parse_edid: pixelclock(138800).
9369 19:29:56.974119 hactive(1920), hsync(48), hfp(24), hbp(88)
9370 19:29:56.977678 vactive(1080), vsync(12), vfp(3), vbp(17)
9371 19:29:56.981231 anx7625_dsi_config: config dsi.
9372 19:29:56.987700 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9373 19:29:57.000686 anx7625_dsi_config: success to config DSI
9374 19:29:57.003874 anx7625_dp_start: MIPI phy setup OK.
9375 19:29:57.007156 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9376 19:29:57.010247 mtk_ddp_mode_set invalid vrefresh 60
9377 19:29:57.013367 main_disp_path_setup
9378 19:29:57.013450 ovl_layer_smi_id_en
9379 19:29:57.017110 ovl_layer_smi_id_en
9380 19:29:57.017193 ccorr_config
9381 19:29:57.017258 aal_config
9382 19:29:57.020452 gamma_config
9383 19:29:57.020535 postmask_config
9384 19:29:57.023660 dither_config
9385 19:29:57.026712 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9386 19:29:57.033535 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9387 19:29:57.036609 Root Device init finished in 551 msecs
9388 19:29:57.036692 CPU_CLUSTER: 0 init
9389 19:29:57.047367 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9390 19:29:57.050575 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9391 19:29:57.053366 APU_MBOX 0x190000b0 = 0x10001
9392 19:29:57.056749 APU_MBOX 0x190001b0 = 0x10001
9393 19:29:57.060015 APU_MBOX 0x190005b0 = 0x10001
9394 19:29:57.063160 APU_MBOX 0x190006b0 = 0x10001
9395 19:29:57.066428 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9396 19:29:57.079704 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9397 19:29:57.091722 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9398 19:29:57.098252 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9399 19:29:57.109987 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9400 19:29:57.119265 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9401 19:29:57.122634 CPU_CLUSTER: 0 init finished in 81 msecs
9402 19:29:57.125629 Devices initialized
9403 19:29:57.128956 Show all devs... After init.
9404 19:29:57.129050 Root Device: enabled 1
9405 19:29:57.132615 CPU_CLUSTER: 0: enabled 1
9406 19:29:57.135615 CPU: 00: enabled 1
9407 19:29:57.138810 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9408 19:29:57.142521 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9409 19:29:57.145478 ELOG: NV offset 0x57f000 size 0x1000
9410 19:29:57.151862 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9411 19:29:57.158878 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9412 19:29:57.162104 ELOG: Event(17) added with size 13 at 2024-04-18 19:25:46 UTC
9413 19:29:57.168795 out: cmd=0x121: 03 db 21 01 00 00 00 00
9414 19:29:57.171868 in-header: 03 eb 00 00 2c 00 00 00
9415 19:29:57.181555 in-data: 74 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9416 19:29:57.188576 ELOG: Event(A1) added with size 10 at 2024-04-18 19:25:46 UTC
9417 19:29:57.195329 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9418 19:29:57.201270 ELOG: Event(A0) added with size 9 at 2024-04-18 19:25:46 UTC
9419 19:29:57.204790 elog_add_boot_reason: Logged dev mode boot
9420 19:29:57.211786 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9421 19:29:57.211873 Finalize devices...
9422 19:29:57.215155 Devices finalized
9423 19:29:57.218057 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9424 19:29:57.221451 Writing coreboot table at 0xffe64000
9425 19:29:57.224921 0. 000000000010a000-0000000000113fff: RAMSTAGE
9426 19:29:57.228512 1. 0000000040000000-00000000400fffff: RAM
9427 19:29:57.234924 2. 0000000040100000-000000004032afff: RAMSTAGE
9428 19:29:57.237975 3. 000000004032b000-00000000545fffff: RAM
9429 19:29:57.241228 4. 0000000054600000-000000005465ffff: BL31
9430 19:29:57.245031 5. 0000000054660000-00000000ffe63fff: RAM
9431 19:29:57.251783 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9432 19:29:57.254840 7. 0000000100000000-000000023fffffff: RAM
9433 19:29:57.258074 Passing 5 GPIOs to payload:
9434 19:29:57.261217 NAME | PORT | POLARITY | VALUE
9435 19:29:57.268373 EC in RW | 0x000000aa | low | undefined
9436 19:29:57.271387 EC interrupt | 0x00000005 | low | undefined
9437 19:29:57.274676 TPM interrupt | 0x000000ab | high | undefined
9438 19:29:57.281182 SD card detect | 0x00000011 | high | undefined
9439 19:29:57.284655 speaker enable | 0x00000093 | high | undefined
9440 19:29:57.287751 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9441 19:29:57.291197 in-header: 03 f9 00 00 02 00 00 00
9442 19:29:57.294685 in-data: 02 00
9443 19:29:57.298149 ADC[4]: Raw value=904726 ID=7
9444 19:29:57.298232 ADC[3]: Raw value=213441 ID=1
9445 19:29:57.301197 RAM Code: 0x71
9446 19:29:57.304426 ADC[6]: Raw value=75701 ID=0
9447 19:29:57.304509 ADC[5]: Raw value=213072 ID=1
9448 19:29:57.307946 SKU Code: 0x1
9449 19:29:57.311234 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 9a37
9450 19:29:57.314438 coreboot table: 964 bytes.
9451 19:29:57.317542 IMD ROOT 0. 0xfffff000 0x00001000
9452 19:29:57.321323 IMD SMALL 1. 0xffffe000 0x00001000
9453 19:29:57.324076 RO MCACHE 2. 0xffffc000 0x00001104
9454 19:29:57.327798 CONSOLE 3. 0xfff7c000 0x00080000
9455 19:29:57.330754 FMAP 4. 0xfff7b000 0x00000452
9456 19:29:57.334031 TIME STAMP 5. 0xfff7a000 0x00000910
9457 19:29:57.337317 VBOOT WORK 6. 0xfff66000 0x00014000
9458 19:29:57.340917 RAMOOPS 7. 0xffe66000 0x00100000
9459 19:29:57.343850 COREBOOT 8. 0xffe64000 0x00002000
9460 19:29:57.347357 IMD small region:
9461 19:29:57.350992 IMD ROOT 0. 0xffffec00 0x00000400
9462 19:29:57.354174 VPD 1. 0xffffeb80 0x0000006c
9463 19:29:57.357276 MMC STATUS 2. 0xffffeb60 0x00000004
9464 19:29:57.360398 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9465 19:29:57.364193 Probing TPM: done!
9466 19:29:57.367234 Connected to device vid:did:rid of 1ae0:0028:00
9467 19:29:57.378103 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9468 19:29:57.381831 Initialized TPM device CR50 revision 0
9469 19:29:57.385102 Checking cr50 for pending updates
9470 19:29:57.388757 Reading cr50 TPM mode
9471 19:29:57.397549 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9472 19:29:57.404230 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9473 19:29:57.444402 read SPI 0x3990ec 0x4f1b0: 34852 us, 9296 KB/s, 74.368 Mbps
9474 19:29:57.447560 Checking segment from ROM address 0x40100000
9475 19:29:57.450960 Checking segment from ROM address 0x4010001c
9476 19:29:57.457493 Loading segment from ROM address 0x40100000
9477 19:29:57.457577 code (compression=0)
9478 19:29:57.467615 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9479 19:29:57.474278 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9480 19:29:57.474380 it's not compressed!
9481 19:29:57.480592 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9482 19:29:57.487688 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9483 19:29:57.504889 Loading segment from ROM address 0x4010001c
9484 19:29:57.505011 Entry Point 0x80000000
9485 19:29:57.508603 Loaded segments
9486 19:29:57.511731 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9487 19:29:57.517977 Jumping to boot code at 0x80000000(0xffe64000)
9488 19:29:57.524768 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9489 19:29:57.531720 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9490 19:29:57.539367 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9491 19:29:57.542487 Checking segment from ROM address 0x40100000
9492 19:29:57.545797 Checking segment from ROM address 0x4010001c
9493 19:29:57.552489 Loading segment from ROM address 0x40100000
9494 19:29:57.552583 code (compression=1)
9495 19:29:57.559409 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9496 19:29:57.569336 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9497 19:29:57.569451 using LZMA
9498 19:29:57.577715 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9499 19:29:57.584114 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9500 19:29:57.587542 Loading segment from ROM address 0x4010001c
9501 19:29:57.587684 Entry Point 0x54601000
9502 19:29:57.590985 Loaded segments
9503 19:29:57.594273 NOTICE: MT8192 bl31_setup
9504 19:29:57.601240 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9505 19:29:57.604216 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9506 19:29:57.607964 WARNING: region 0:
9507 19:29:57.611016 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9508 19:29:57.611100 WARNING: region 1:
9509 19:29:57.617948 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9510 19:29:57.621190 WARNING: region 2:
9511 19:29:57.625085 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9512 19:29:57.628091 WARNING: region 3:
9513 19:29:57.631259 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9514 19:29:57.634783 WARNING: region 4:
9515 19:29:57.641237 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9516 19:29:57.641327 WARNING: region 5:
9517 19:29:57.644269 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9518 19:29:57.647571 WARNING: region 6:
9519 19:29:57.650908 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9520 19:29:57.654179 WARNING: region 7:
9521 19:29:57.657960 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9522 19:29:57.664874 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9523 19:29:57.668162 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9524 19:29:57.671164 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9525 19:29:57.678076 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9526 19:29:57.681227 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9527 19:29:57.684907 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9528 19:29:57.691167 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9529 19:29:57.694588 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9530 19:29:57.697991 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9531 19:29:57.704610 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9532 19:29:57.708230 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9533 19:29:57.714577 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9534 19:29:57.718110 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9535 19:29:57.721367 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9536 19:29:57.727795 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9537 19:29:57.731624 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9538 19:29:57.734700 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9539 19:29:57.741846 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9540 19:29:57.744678 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9541 19:29:57.748107 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9542 19:29:57.754698 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9543 19:29:57.758406 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9544 19:29:57.765076 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9545 19:29:57.768487 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9546 19:29:57.771529 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9547 19:29:57.778599 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9548 19:29:57.781670 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9549 19:29:57.788303 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9550 19:29:57.791536 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9551 19:29:57.794746 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9552 19:29:57.801634 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9553 19:29:57.805456 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9554 19:29:57.808379 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9555 19:29:57.814922 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9556 19:29:57.818176 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9557 19:29:57.821942 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9558 19:29:57.825042 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9559 19:29:57.831926 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9560 19:29:57.835353 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9561 19:29:57.838614 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9562 19:29:57.841588 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9563 19:29:57.848487 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9564 19:29:57.852034 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9565 19:29:57.855339 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9566 19:29:57.858337 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9567 19:29:57.865334 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9568 19:29:57.868600 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9569 19:29:57.871837 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9570 19:29:57.878464 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9571 19:29:57.882205 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9572 19:29:57.884960 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9573 19:29:57.892007 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9574 19:29:57.895154 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9575 19:29:57.901545 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9576 19:29:57.905327 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9577 19:29:57.908967 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9578 19:29:57.915323 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9579 19:29:57.919085 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9580 19:29:57.925292 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9581 19:29:57.929041 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9582 19:29:57.935582 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9583 19:29:57.938473 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9584 19:29:57.945533 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9585 19:29:57.948264 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9586 19:29:57.952065 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9587 19:29:57.958760 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9588 19:29:57.961751 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9589 19:29:57.968423 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9590 19:29:57.971701 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9591 19:29:57.978727 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9592 19:29:57.982132 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9593 19:29:57.985000 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9594 19:29:57.991773 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9595 19:29:57.995324 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9596 19:29:58.002048 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9597 19:29:58.005497 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9598 19:29:58.011555 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9599 19:29:58.015191 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9600 19:29:58.018364 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9601 19:29:58.025504 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9602 19:29:58.028597 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9603 19:29:58.035317 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9604 19:29:58.038433 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9605 19:29:58.045393 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9606 19:29:58.048935 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9607 19:29:58.051921 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9608 19:29:58.058685 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9609 19:29:58.061977 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9610 19:29:58.068719 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9611 19:29:58.072032 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9612 19:29:58.078335 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9613 19:29:58.082133 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9614 19:29:58.085337 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9615 19:29:58.091780 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9616 19:29:58.095265 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9617 19:29:58.101975 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9618 19:29:58.105206 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9619 19:29:58.108402 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9620 19:29:58.115088 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9621 19:29:58.118629 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9622 19:29:58.121831 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9623 19:29:58.125661 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9624 19:29:58.131826 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9625 19:29:58.135772 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9626 19:29:58.141941 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9627 19:29:58.145248 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9628 19:29:58.148932 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9629 19:29:58.155557 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9630 19:29:58.158794 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9631 19:29:58.165756 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9632 19:29:58.169018 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9633 19:29:58.172543 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9634 19:29:58.179206 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9635 19:29:58.182476 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9636 19:29:58.185848 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9637 19:29:58.192625 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9638 19:29:58.195624 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9639 19:29:58.199164 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9640 19:29:58.205582 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9641 19:29:58.209062 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9642 19:29:58.212282 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9643 19:29:58.216092 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9644 19:29:58.222764 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9645 19:29:58.225677 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9646 19:29:58.229321 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9647 19:29:58.235776 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9648 19:29:58.239280 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9649 19:29:58.242592 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9650 19:29:58.249540 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9651 19:29:58.252688 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9652 19:29:58.259510 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9653 19:29:58.262733 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9654 19:29:58.265830 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9655 19:29:58.272611 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9656 19:29:58.276123 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9657 19:29:58.282644 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9658 19:29:58.285713 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9659 19:29:58.289150 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9660 19:29:58.295863 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9661 19:29:58.300019 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9662 19:29:58.302482 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9663 19:29:58.309009 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9664 19:29:58.312377 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9665 19:29:58.319271 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9666 19:29:58.322494 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9667 19:29:58.326228 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9668 19:29:58.333061 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9669 19:29:58.336109 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9670 19:29:58.339230 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9671 19:29:58.346008 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9672 19:29:58.349718 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9673 19:29:58.356353 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9674 19:29:58.359692 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9675 19:29:58.362767 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9676 19:29:58.369134 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9677 19:29:58.372945 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9678 19:29:58.379393 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9679 19:29:58.382879 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9680 19:29:58.386716 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9681 19:29:58.392841 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9682 19:29:58.395793 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9683 19:29:58.399663 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9684 19:29:58.406142 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9685 19:29:58.409664 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9686 19:29:58.416361 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9687 19:29:58.419413 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9688 19:29:58.422974 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9689 19:29:58.429175 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9690 19:29:58.432572 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9691 19:29:58.439126 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9692 19:29:58.442343 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9693 19:29:58.446290 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9694 19:29:58.452868 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9695 19:29:58.456010 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9696 19:29:58.462264 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9697 19:29:58.465463 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9698 19:29:58.469105 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9699 19:29:58.475571 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9700 19:29:58.478714 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9701 19:29:58.485801 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9702 19:29:58.489029 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9703 19:29:58.492449 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9704 19:29:58.498888 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9705 19:29:58.502291 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9706 19:29:58.509333 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9707 19:29:58.512103 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9708 19:29:58.515007 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9709 19:29:58.522476 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9710 19:29:58.525851 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9711 19:29:58.532130 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9712 19:29:58.535244 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9713 19:29:58.541639 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9714 19:29:58.545538 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9715 19:29:58.548437 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9716 19:29:58.555620 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9717 19:29:58.558790 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9718 19:29:58.565163 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9719 19:29:58.568749 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9720 19:29:58.571675 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9721 19:29:58.578138 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9722 19:29:58.581885 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9723 19:29:58.588333 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9724 19:29:58.592155 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9725 19:29:58.598072 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9726 19:29:58.601652 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9727 19:29:58.604950 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9728 19:29:58.612130 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9729 19:29:58.615002 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9730 19:29:58.621527 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9731 19:29:58.625156 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9732 19:29:58.628225 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9733 19:29:58.635004 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9734 19:29:58.638233 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9735 19:29:58.644625 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9736 19:29:58.647723 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9737 19:29:58.654372 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9738 19:29:58.657721 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9739 19:29:58.660820 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9740 19:29:58.667565 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9741 19:29:58.671115 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9742 19:29:58.677796 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9743 19:29:58.680727 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9744 19:29:58.687493 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9745 19:29:58.690656 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9746 19:29:58.694185 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9747 19:29:58.701134 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9748 19:29:58.704592 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9749 19:29:58.710612 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9750 19:29:58.714296 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9751 19:29:58.717359 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9752 19:29:58.720705 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9753 19:29:58.727726 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9754 19:29:58.730592 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9755 19:29:58.734506 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9756 19:29:58.741001 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9757 19:29:58.744092 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9758 19:29:58.747409 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9759 19:29:58.754247 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9760 19:29:58.757395 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9761 19:29:58.760723 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9762 19:29:58.767557 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9763 19:29:58.770596 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9764 19:29:58.777264 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9765 19:29:58.780460 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9766 19:29:58.783459 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9767 19:29:58.790434 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9768 19:29:58.793483 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9769 19:29:58.796702 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9770 19:29:58.803731 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9771 19:29:58.806888 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9772 19:29:58.810185 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9773 19:29:58.816852 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9774 19:29:58.820210 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9775 19:29:58.823285 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9776 19:29:58.830544 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9777 19:29:58.833506 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9778 19:29:58.840188 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9779 19:29:58.843238 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9780 19:29:58.846477 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9781 19:29:58.853126 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9782 19:29:58.856197 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9783 19:29:58.862933 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9784 19:29:58.866145 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9785 19:29:58.869249 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9786 19:29:58.875699 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9787 19:29:58.879592 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9788 19:29:58.882735 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9789 19:29:58.889439 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9790 19:29:58.892692 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9791 19:29:58.895571 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9792 19:29:58.899045 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9793 19:29:58.905994 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9794 19:29:58.908952 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9795 19:29:58.912781 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9796 19:29:58.916055 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9797 19:29:58.922277 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9798 19:29:58.926111 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9799 19:29:58.928955 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9800 19:29:58.932481 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9801 19:29:58.939609 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9802 19:29:58.942322 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9803 19:29:58.945518 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9804 19:29:58.952547 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9805 19:29:58.955967 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9806 19:29:58.958655 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9807 19:29:58.965550 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9808 19:29:58.968908 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9809 19:29:58.975678 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9810 19:29:58.978866 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9811 19:29:58.982037 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9812 19:29:58.988940 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9813 19:29:58.991969 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9814 19:29:58.998743 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9815 19:29:59.001951 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9816 19:29:59.009331 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9817 19:29:59.012306 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9818 19:29:59.015325 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9819 19:29:59.022545 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9820 19:29:59.026144 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9821 19:29:59.029458 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9822 19:29:59.035691 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9823 19:29:59.038834 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9824 19:29:59.045468 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9825 19:29:59.049142 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9826 19:29:59.055674 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9827 19:29:59.058924 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9828 19:29:59.062160 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9829 19:29:59.068375 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9830 19:29:59.072174 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9831 19:29:59.078876 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9832 19:29:59.082045 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9833 19:29:59.088600 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9834 19:29:59.092000 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9835 19:29:59.095023 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9836 19:29:59.101899 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9837 19:29:59.105460 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9838 19:29:59.111798 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9839 19:29:59.115222 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9840 19:29:59.118441 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9841 19:29:59.125315 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9842 19:29:59.128512 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9843 19:29:59.134986 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9844 19:29:59.138373 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9845 19:29:59.141334 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9846 19:29:59.148124 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9847 19:29:59.151710 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9848 19:29:59.158278 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9849 19:29:59.161235 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9850 19:29:59.168280 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9851 19:29:59.171177 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9852 19:29:59.174937 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9853 19:29:59.181608 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9854 19:29:59.184942 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9855 19:29:59.188071 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9856 19:29:59.194608 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9857 19:29:59.198492 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9858 19:29:59.204770 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9859 19:29:59.208118 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9860 19:29:59.211740 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9861 19:29:59.218539 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9862 19:29:59.221361 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9863 19:29:59.228122 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9864 19:29:59.231916 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9865 19:29:59.238261 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9866 19:29:59.241397 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9867 19:29:59.245008 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9868 19:29:59.251767 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9869 19:29:59.255024 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9870 19:29:59.258365 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9871 19:29:59.265479 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9872 19:29:59.268511 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9873 19:29:59.275337 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9874 19:29:59.278504 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9875 19:29:59.281301 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9876 19:29:59.287949 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9877 19:29:59.291500 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9878 19:29:59.298073 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9879 19:29:59.301843 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9880 19:29:59.308056 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9881 19:29:59.311958 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9882 19:29:59.318156 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9883 19:29:59.321130 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9884 19:29:59.324858 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9885 19:29:59.331526 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9886 19:29:59.334607 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9887 19:29:59.341706 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9888 19:29:59.344855 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9889 19:29:59.351233 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9890 19:29:59.355127 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9891 19:29:59.357892 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9892 19:29:59.364400 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9893 19:29:59.368190 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9894 19:29:59.374781 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9895 19:29:59.377564 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9896 19:29:59.385059 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9897 19:29:59.387618 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9898 19:29:59.394454 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9899 19:29:59.397505 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9900 19:29:59.400691 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9901 19:29:59.407477 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9902 19:29:59.411081 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9903 19:29:59.417300 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9904 19:29:59.421001 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9905 19:29:59.427325 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9906 19:29:59.431012 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9907 19:29:59.434063 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9908 19:29:59.441038 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9909 19:29:59.443960 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9910 19:29:59.450947 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9911 19:29:59.454286 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9912 19:29:59.460611 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9913 19:29:59.463682 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9914 19:29:59.470619 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9915 19:29:59.473760 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9916 19:29:59.477043 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9917 19:29:59.483842 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9918 19:29:59.487313 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9919 19:29:59.493565 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9920 19:29:59.497590 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9921 19:29:59.503822 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9922 19:29:59.507052 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9923 19:29:59.510520 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9924 19:29:59.517142 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9925 19:29:59.520287 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9926 19:29:59.526792 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9927 19:29:59.529881 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9928 19:29:59.536840 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9929 19:29:59.539896 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9930 19:29:59.546596 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9931 19:29:59.549949 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9932 19:29:59.553279 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9933 19:29:59.560064 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9934 19:29:59.563090 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9935 19:29:59.570250 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9936 19:29:59.573089 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9937 19:29:59.580079 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9938 19:29:59.583839 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9939 19:29:59.590549 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9940 19:29:59.593353 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9941 19:29:59.600161 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9942 19:29:59.603054 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9943 19:29:59.609682 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9944 19:29:59.613343 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9945 19:29:59.619910 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9946 19:29:59.622865 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9947 19:29:59.629573 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9948 19:29:59.633242 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9949 19:29:59.639496 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9950 19:29:59.643140 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9951 19:29:59.649398 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9952 19:29:59.652691 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9953 19:29:59.659601 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9954 19:29:59.662830 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9955 19:29:59.669092 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9956 19:29:59.672599 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9957 19:29:59.676375 INFO: [APUAPC] vio 0
9958 19:29:59.679468 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9959 19:29:59.685617 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9960 19:29:59.689378 INFO: [APUAPC] D0_APC_0: 0x400510
9961 19:29:59.692227 INFO: [APUAPC] D0_APC_1: 0x0
9962 19:29:59.692324 INFO: [APUAPC] D0_APC_2: 0x1540
9963 19:29:59.695774 INFO: [APUAPC] D0_APC_3: 0x0
9964 19:29:59.699391 INFO: [APUAPC] D1_APC_0: 0xffffffff
9965 19:29:59.702221 INFO: [APUAPC] D1_APC_1: 0xffffffff
9966 19:29:59.705899 INFO: [APUAPC] D1_APC_2: 0x3fffff
9967 19:29:59.708895 INFO: [APUAPC] D1_APC_3: 0x0
9968 19:29:59.712155 INFO: [APUAPC] D2_APC_0: 0xffffffff
9969 19:29:59.715918 INFO: [APUAPC] D2_APC_1: 0xffffffff
9970 19:29:59.719088 INFO: [APUAPC] D2_APC_2: 0x3fffff
9971 19:29:59.722561 INFO: [APUAPC] D2_APC_3: 0x0
9972 19:29:59.725521 INFO: [APUAPC] D3_APC_0: 0xffffffff
9973 19:29:59.729432 INFO: [APUAPC] D3_APC_1: 0xffffffff
9974 19:29:59.732409 INFO: [APUAPC] D3_APC_2: 0x3fffff
9975 19:29:59.735471 INFO: [APUAPC] D3_APC_3: 0x0
9976 19:29:59.739059 INFO: [APUAPC] D4_APC_0: 0xffffffff
9977 19:29:59.742443 INFO: [APUAPC] D4_APC_1: 0xffffffff
9978 19:29:59.745580 INFO: [APUAPC] D4_APC_2: 0x3fffff
9979 19:29:59.749106 INFO: [APUAPC] D4_APC_3: 0x0
9980 19:29:59.751897 INFO: [APUAPC] D5_APC_0: 0xffffffff
9981 19:29:59.755431 INFO: [APUAPC] D5_APC_1: 0xffffffff
9982 19:29:59.759459 INFO: [APUAPC] D5_APC_2: 0x3fffff
9983 19:29:59.762039 INFO: [APUAPC] D5_APC_3: 0x0
9984 19:29:59.765635 INFO: [APUAPC] D6_APC_0: 0xffffffff
9985 19:29:59.768729 INFO: [APUAPC] D6_APC_1: 0xffffffff
9986 19:29:59.771904 INFO: [APUAPC] D6_APC_2: 0x3fffff
9987 19:29:59.775304 INFO: [APUAPC] D6_APC_3: 0x0
9988 19:29:59.778912 INFO: [APUAPC] D7_APC_0: 0xffffffff
9989 19:29:59.782346 INFO: [APUAPC] D7_APC_1: 0xffffffff
9990 19:29:59.785463 INFO: [APUAPC] D7_APC_2: 0x3fffff
9991 19:29:59.788761 INFO: [APUAPC] D7_APC_3: 0x0
9992 19:29:59.791756 INFO: [APUAPC] D8_APC_0: 0xffffffff
9993 19:29:59.795563 INFO: [APUAPC] D8_APC_1: 0xffffffff
9994 19:29:59.798490 INFO: [APUAPC] D8_APC_2: 0x3fffff
9995 19:29:59.802074 INFO: [APUAPC] D8_APC_3: 0x0
9996 19:29:59.805028 INFO: [APUAPC] D9_APC_0: 0xffffffff
9997 19:29:59.808984 INFO: [APUAPC] D9_APC_1: 0xffffffff
9998 19:29:59.811991 INFO: [APUAPC] D9_APC_2: 0x3fffff
9999 19:29:59.815321 INFO: [APUAPC] D9_APC_3: 0x0
10000 19:29:59.818280 INFO: [APUAPC] D10_APC_0: 0xffffffff
10001 19:29:59.822077 INFO: [APUAPC] D10_APC_1: 0xffffffff
10002 19:29:59.825317 INFO: [APUAPC] D10_APC_2: 0x3fffff
10003 19:29:59.828108 INFO: [APUAPC] D10_APC_3: 0x0
10004 19:29:59.831457 INFO: [APUAPC] D11_APC_0: 0xffffffff
10005 19:29:59.835062 INFO: [APUAPC] D11_APC_1: 0xffffffff
10006 19:29:59.838111 INFO: [APUAPC] D11_APC_2: 0x3fffff
10007 19:29:59.841749 INFO: [APUAPC] D11_APC_3: 0x0
10008 19:29:59.844951 INFO: [APUAPC] D12_APC_0: 0xffffffff
10009 19:29:59.847882 INFO: [APUAPC] D12_APC_1: 0xffffffff
10010 19:29:59.851569 INFO: [APUAPC] D12_APC_2: 0x3fffff
10011 19:29:59.854498 INFO: [APUAPC] D12_APC_3: 0x0
10012 19:29:59.857848 INFO: [APUAPC] D13_APC_0: 0xffffffff
10013 19:29:59.861414 INFO: [APUAPC] D13_APC_1: 0xffffffff
10014 19:29:59.864362 INFO: [APUAPC] D13_APC_2: 0x3fffff
10015 19:29:59.867610 INFO: [APUAPC] D13_APC_3: 0x0
10016 19:29:59.871113 INFO: [APUAPC] D14_APC_0: 0xffffffff
10017 19:29:59.874665 INFO: [APUAPC] D14_APC_1: 0xffffffff
10018 19:29:59.877862 INFO: [APUAPC] D14_APC_2: 0x3fffff
10019 19:29:59.881091 INFO: [APUAPC] D14_APC_3: 0x0
10020 19:29:59.884532 INFO: [APUAPC] D15_APC_0: 0xffffffff
10021 19:29:59.887646 INFO: [APUAPC] D15_APC_1: 0xffffffff
10022 19:29:59.890860 INFO: [APUAPC] D15_APC_2: 0x3fffff
10023 19:29:59.894043 INFO: [APUAPC] D15_APC_3: 0x0
10024 19:29:59.897144 INFO: [APUAPC] APC_CON: 0x4
10025 19:29:59.900892 INFO: [NOCDAPC] D0_APC_0: 0x0
10026 19:29:59.904065 INFO: [NOCDAPC] D0_APC_1: 0x0
10027 19:29:59.904195 INFO: [NOCDAPC] D1_APC_0: 0x0
10028 19:29:59.907579 INFO: [NOCDAPC] D1_APC_1: 0xfff
10029 19:29:59.910685 INFO: [NOCDAPC] D2_APC_0: 0x0
10030 19:29:59.913944 INFO: [NOCDAPC] D2_APC_1: 0xfff
10031 19:29:59.916775 INFO: [NOCDAPC] D3_APC_0: 0x0
10032 19:29:59.920153 INFO: [NOCDAPC] D3_APC_1: 0xfff
10033 19:29:59.923997 INFO: [NOCDAPC] D4_APC_0: 0x0
10034 19:29:59.926657 INFO: [NOCDAPC] D4_APC_1: 0xfff
10035 19:29:59.930259 INFO: [NOCDAPC] D5_APC_0: 0x0
10036 19:29:59.933433 INFO: [NOCDAPC] D5_APC_1: 0xfff
10037 19:29:59.937559 INFO: [NOCDAPC] D6_APC_0: 0x0
10038 19:29:59.940346 INFO: [NOCDAPC] D6_APC_1: 0xfff
10039 19:29:59.940457 INFO: [NOCDAPC] D7_APC_0: 0x0
10040 19:29:59.943899 INFO: [NOCDAPC] D7_APC_1: 0xfff
10041 19:29:59.947064 INFO: [NOCDAPC] D8_APC_0: 0x0
10042 19:29:59.950641 INFO: [NOCDAPC] D8_APC_1: 0xfff
10043 19:29:59.953676 INFO: [NOCDAPC] D9_APC_0: 0x0
10044 19:29:59.957185 INFO: [NOCDAPC] D9_APC_1: 0xfff
10045 19:29:59.960274 INFO: [NOCDAPC] D10_APC_0: 0x0
10046 19:29:59.963721 INFO: [NOCDAPC] D10_APC_1: 0xfff
10047 19:29:59.967214 INFO: [NOCDAPC] D11_APC_0: 0x0
10048 19:29:59.970659 INFO: [NOCDAPC] D11_APC_1: 0xfff
10049 19:29:59.973699 INFO: [NOCDAPC] D12_APC_0: 0x0
10050 19:29:59.976828 INFO: [NOCDAPC] D12_APC_1: 0xfff
10051 19:29:59.980257 INFO: [NOCDAPC] D13_APC_0: 0x0
10052 19:29:59.983509 INFO: [NOCDAPC] D13_APC_1: 0xfff
10053 19:29:59.986794 INFO: [NOCDAPC] D14_APC_0: 0x0
10054 19:29:59.987212 INFO: [NOCDAPC] D14_APC_1: 0xfff
10055 19:29:59.990074 INFO: [NOCDAPC] D15_APC_0: 0x0
10056 19:29:59.993794 INFO: [NOCDAPC] D15_APC_1: 0xfff
10057 19:29:59.996891 INFO: [NOCDAPC] APC_CON: 0x4
10058 19:29:59.999973 INFO: [APUAPC] set_apusys_apc done
10059 19:30:00.003113 INFO: [DEVAPC] devapc_init done
10060 19:30:00.006270 INFO: GICv3 without legacy support detected.
10061 19:30:00.012817 INFO: ARM GICv3 driver initialized in EL3
10062 19:30:00.016826 INFO: Maximum SPI INTID supported: 639
10063 19:30:00.019622 INFO: BL31: Initializing runtime services
10064 19:30:00.026174 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10065 19:30:00.029563 INFO: SPM: enable CPC mode
10066 19:30:00.032690 INFO: mcdi ready for mcusys-off-idle and system suspend
10067 19:30:00.039601 INFO: BL31: Preparing for EL3 exit to normal world
10068 19:30:00.042917 INFO: Entry point address = 0x80000000
10069 19:30:00.043018 INFO: SPSR = 0x8
10070 19:30:00.049556
10071 19:30:00.049640
10072 19:30:00.049707
10073 19:30:00.052586 Starting depthcharge on Spherion...
10074 19:30:00.052670
10075 19:30:00.052735 Wipe memory regions:
10076 19:30:00.052796
10077 19:30:00.053455 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10078 19:30:00.053555 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10079 19:30:00.053638 Setting prompt string to ['asurada:']
10080 19:30:00.053721 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10081 19:30:00.055939 [0x00000040000000, 0x00000054600000)
10082 19:30:00.178371
10083 19:30:00.178526 [0x00000054660000, 0x00000080000000)
10084 19:30:00.438639
10085 19:30:00.438781 [0x000000821a7280, 0x000000ffe64000)
10086 19:30:01.183765
10087 19:30:01.183983 [0x00000100000000, 0x00000240000000)
10088 19:30:03.074164
10089 19:30:03.077385 Initializing XHCI USB controller at 0x11200000.
10090 19:30:04.115254
10091 19:30:04.118562 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10092 19:30:04.118652
10093 19:30:04.118719
10094 19:30:04.118780
10095 19:30:04.119061 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10097 19:30:04.219348 asurada: tftpboot 192.168.201.1 13420376/tftp-deploy-2a_ifze_/kernel/image.itb 13420376/tftp-deploy-2a_ifze_/kernel/cmdline
10098 19:30:04.219486 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10099 19:30:04.219597 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10100 19:30:04.224170 tftpboot 192.168.201.1 13420376/tftp-deploy-2a_ifze_/kernel/image.ittp-deploy-2a_ifze_/kernel/cmdline
10101 19:30:04.224253
10102 19:30:04.224318 Waiting for link
10103 19:30:04.384883
10104 19:30:04.385026 R8152: Initializing
10105 19:30:04.385104
10106 19:30:04.388088 Version 9 (ocp_data = 6010)
10107 19:30:04.388172
10108 19:30:04.391593 R8152: Done initializing
10109 19:30:04.391675
10110 19:30:04.391743 Adding net device
10111 19:30:06.336972
10112 19:30:06.337236 done.
10113 19:30:06.337343
10114 19:30:06.337425 MAC: 00:e0:4c:78:7a:aa
10115 19:30:06.337505
10116 19:30:06.340047 Sending DHCP discover... done.
10117 19:30:06.340132
10119 19:34:25.053852 end: 2.2.4 bootloader-commands (duration 00:04:25) [common]
10121 19:34:25.054051 depthcharge-retry failed: 1 of 1 attempts. 'bootloader-commands timed out after 265 seconds'
10123 19:34:25.054279 end: 2.2 depthcharge-retry (duration 00:05:00) [common]
10126 19:34:25.054614 end: 2 depthcharge-action (duration 00:05:00) [common]
10128 19:34:25.054844 Cleaning after the job
10129 19:34:25.054938 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13420376/tftp-deploy-2a_ifze_/ramdisk
10130 19:34:25.057026 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13420376/tftp-deploy-2a_ifze_/kernel
10131 19:34:25.067632 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13420376/tftp-deploy-2a_ifze_/dtb
10132 19:34:25.067801 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13420376/tftp-deploy-2a_ifze_/nfsrootfs
10133 19:34:25.130186 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13420376/tftp-deploy-2a_ifze_/modules
10134 19:34:25.135754 start: 4.1 power-off (timeout 00:00:30) [common]
10135 19:34:25.135933 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
10136 19:34:25.211912 >> Command sent successfully.
10137 19:34:25.214372 Returned 0 in 0 seconds
10138 19:34:25.314767 end: 4.1 power-off (duration 00:00:00) [common]
10140 19:34:25.315091 start: 4.2 read-feedback (timeout 00:10:00) [common]
10141 19:34:25.315342 Listened to connection for namespace 'common' for up to 1s
10142 19:34:26.316331 Finalising connection for namespace 'common'
10143 19:34:26.316502 Disconnecting from shell: Finalise
10144 19:34:26.316583 Waiting for reply...
10145 19:34:26.416904 end: 4.2 read-feedback (duration 00:00:01) [common]
10146 19:34:26.417059 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/13420376
10147 19:34:26.971510 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/13420376
10148 19:34:26.971702 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.