Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 44
- Errors: 0
- Kernel Errors: 35
- Boot result: PASS
1 19:21:19.526360 lava-dispatcher, installed at version: 2024.01
2 19:21:19.526558 start: 0 validate
3 19:21:19.526680 Start time: 2024-04-18 19:21:19.526673+00:00 (UTC)
4 19:21:19.526795 Using caching service: 'http://localhost/cache/?uri=%s'
5 19:21:19.526913 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 19:21:19.786058 Using caching service: 'http://localhost/cache/?uri=%s'
7 19:21:19.786257 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 19:21:54.074755 Using caching service: 'http://localhost/cache/?uri=%s'
9 19:21:54.075322 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 19:21:54.345027 Using caching service: 'http://localhost/cache/?uri=%s'
11 19:21:54.345855 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.86-cip19%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 19:21:57.114990 validate duration: 37.59
14 19:21:57.116260 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 19:21:57.117060 start: 1.1 download-retry (timeout 00:10:00) [common]
16 19:21:57.117561 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 19:21:57.118198 Not decompressing ramdisk as can be used compressed.
18 19:21:57.118669 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/rootfs.cpio.gz
19 19:21:57.119031 saving as /var/lib/lava/dispatcher/tmp/13420363/tftp-deploy-v5h0r7fo/ramdisk/rootfs.cpio.gz
20 19:21:57.119394 total size: 95552279 (91 MB)
21 19:21:57.382131 progress 0 % (0 MB)
22 19:21:57.406475 progress 5 % (4 MB)
23 19:21:57.430970 progress 10 % (9 MB)
24 19:21:57.454889 progress 15 % (13 MB)
25 19:21:57.478713 progress 20 % (18 MB)
26 19:21:57.502828 progress 25 % (22 MB)
27 19:21:57.526893 progress 30 % (27 MB)
28 19:21:57.551108 progress 35 % (31 MB)
29 19:21:57.574878 progress 40 % (36 MB)
30 19:21:57.598855 progress 45 % (41 MB)
31 19:21:57.623214 progress 50 % (45 MB)
32 19:21:57.647335 progress 55 % (50 MB)
33 19:21:57.671549 progress 60 % (54 MB)
34 19:21:57.695795 progress 65 % (59 MB)
35 19:21:57.720007 progress 70 % (63 MB)
36 19:21:57.744289 progress 75 % (68 MB)
37 19:21:57.768308 progress 80 % (72 MB)
38 19:21:57.792622 progress 85 % (77 MB)
39 19:21:57.816770 progress 90 % (82 MB)
40 19:21:57.840913 progress 95 % (86 MB)
41 19:21:57.864484 progress 100 % (91 MB)
42 19:21:57.864648 91 MB downloaded in 0.75 s (122.27 MB/s)
43 19:21:57.864820 end: 1.1.1 http-download (duration 00:00:01) [common]
45 19:21:57.865063 end: 1.1 download-retry (duration 00:00:01) [common]
46 19:21:57.865149 start: 1.2 download-retry (timeout 00:09:59) [common]
47 19:21:57.865231 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 19:21:57.865366 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 19:21:57.865435 saving as /var/lib/lava/dispatcher/tmp/13420363/tftp-deploy-v5h0r7fo/kernel/Image
50 19:21:57.865497 total size: 54286848 (51 MB)
51 19:21:57.865559 No compression specified
52 19:21:57.866660 progress 0 % (0 MB)
53 19:21:57.880215 progress 5 % (2 MB)
54 19:21:57.894210 progress 10 % (5 MB)
55 19:21:57.908243 progress 15 % (7 MB)
56 19:21:57.922002 progress 20 % (10 MB)
57 19:21:57.935705 progress 25 % (12 MB)
58 19:21:57.949789 progress 30 % (15 MB)
59 19:21:57.963696 progress 35 % (18 MB)
60 19:21:57.977778 progress 40 % (20 MB)
61 19:21:57.991739 progress 45 % (23 MB)
62 19:21:58.005765 progress 50 % (25 MB)
63 19:21:58.019641 progress 55 % (28 MB)
64 19:21:58.033467 progress 60 % (31 MB)
65 19:21:58.047681 progress 65 % (33 MB)
66 19:21:58.063015 progress 70 % (36 MB)
67 19:21:58.077794 progress 75 % (38 MB)
68 19:21:58.092077 progress 80 % (41 MB)
69 19:21:58.106488 progress 85 % (44 MB)
70 19:21:58.120764 progress 90 % (46 MB)
71 19:21:58.135010 progress 95 % (49 MB)
72 19:21:58.149131 progress 100 % (51 MB)
73 19:21:58.149437 51 MB downloaded in 0.28 s (182.34 MB/s)
74 19:21:58.149637 end: 1.2.1 http-download (duration 00:00:00) [common]
76 19:21:58.149875 end: 1.2 download-retry (duration 00:00:00) [common]
77 19:21:58.149965 start: 1.3 download-retry (timeout 00:09:59) [common]
78 19:21:58.150077 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 19:21:58.150211 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 19:21:58.150280 saving as /var/lib/lava/dispatcher/tmp/13420363/tftp-deploy-v5h0r7fo/dtb/mt8192-asurada-spherion-r0.dtb
81 19:21:58.150346 total size: 47230 (0 MB)
82 19:21:58.150407 No compression specified
83 19:21:58.151592 progress 69 % (0 MB)
84 19:21:58.151869 progress 100 % (0 MB)
85 19:21:58.152023 0 MB downloaded in 0.00 s (26.88 MB/s)
86 19:21:58.152149 end: 1.3.1 http-download (duration 00:00:00) [common]
88 19:21:58.152372 end: 1.3 download-retry (duration 00:00:00) [common]
89 19:21:58.152456 start: 1.4 download-retry (timeout 00:09:59) [common]
90 19:21:58.152536 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 19:21:58.152653 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.86-cip19/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 19:21:58.152720 saving as /var/lib/lava/dispatcher/tmp/13420363/tftp-deploy-v5h0r7fo/modules/modules.tar
93 19:21:58.152780 total size: 8631416 (8 MB)
94 19:21:58.152841 Using unxz to decompress xz
95 19:21:58.157005 progress 0 % (0 MB)
96 19:21:58.176881 progress 5 % (0 MB)
97 19:21:58.201965 progress 10 % (0 MB)
98 19:21:58.226540 progress 15 % (1 MB)
99 19:21:58.250149 progress 20 % (1 MB)
100 19:21:58.274872 progress 25 % (2 MB)
101 19:21:58.300858 progress 30 % (2 MB)
102 19:21:58.325098 progress 35 % (2 MB)
103 19:21:58.350367 progress 40 % (3 MB)
104 19:21:58.374091 progress 45 % (3 MB)
105 19:21:58.399477 progress 50 % (4 MB)
106 19:21:58.424722 progress 55 % (4 MB)
107 19:21:58.452545 progress 60 % (4 MB)
108 19:21:58.477547 progress 65 % (5 MB)
109 19:21:58.502773 progress 70 % (5 MB)
110 19:21:58.528158 progress 75 % (6 MB)
111 19:21:58.553736 progress 80 % (6 MB)
112 19:21:58.579939 progress 85 % (7 MB)
113 19:21:58.609041 progress 90 % (7 MB)
114 19:21:58.638852 progress 95 % (7 MB)
115 19:21:58.665223 progress 100 % (8 MB)
116 19:21:58.670674 8 MB downloaded in 0.52 s (15.89 MB/s)
117 19:21:58.670931 end: 1.4.1 http-download (duration 00:00:01) [common]
119 19:21:58.671199 end: 1.4 download-retry (duration 00:00:01) [common]
120 19:21:58.671294 start: 1.5 prepare-tftp-overlay (timeout 00:09:58) [common]
121 19:21:58.671391 start: 1.5.1 extract-nfsrootfs (timeout 00:09:58) [common]
122 19:21:58.671472 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 19:21:58.671560 start: 1.5.2 lava-overlay (timeout 00:09:58) [common]
124 19:21:58.671779 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/13420363/lava-overlay-01lrlebu
125 19:21:58.671915 makedir: /var/lib/lava/dispatcher/tmp/13420363/lava-overlay-01lrlebu/lava-13420363/bin
126 19:21:58.672020 makedir: /var/lib/lava/dispatcher/tmp/13420363/lava-overlay-01lrlebu/lava-13420363/tests
127 19:21:58.672119 makedir: /var/lib/lava/dispatcher/tmp/13420363/lava-overlay-01lrlebu/lava-13420363/results
128 19:21:58.672234 Creating /var/lib/lava/dispatcher/tmp/13420363/lava-overlay-01lrlebu/lava-13420363/bin/lava-add-keys
129 19:21:58.672380 Creating /var/lib/lava/dispatcher/tmp/13420363/lava-overlay-01lrlebu/lava-13420363/bin/lava-add-sources
130 19:21:58.672509 Creating /var/lib/lava/dispatcher/tmp/13420363/lava-overlay-01lrlebu/lava-13420363/bin/lava-background-process-start
131 19:21:58.672676 Creating /var/lib/lava/dispatcher/tmp/13420363/lava-overlay-01lrlebu/lava-13420363/bin/lava-background-process-stop
132 19:21:58.672800 Creating /var/lib/lava/dispatcher/tmp/13420363/lava-overlay-01lrlebu/lava-13420363/bin/lava-common-functions
133 19:21:58.672924 Creating /var/lib/lava/dispatcher/tmp/13420363/lava-overlay-01lrlebu/lava-13420363/bin/lava-echo-ipv4
134 19:21:58.673083 Creating /var/lib/lava/dispatcher/tmp/13420363/lava-overlay-01lrlebu/lava-13420363/bin/lava-install-packages
135 19:21:58.673231 Creating /var/lib/lava/dispatcher/tmp/13420363/lava-overlay-01lrlebu/lava-13420363/bin/lava-installed-packages
136 19:21:58.673366 Creating /var/lib/lava/dispatcher/tmp/13420363/lava-overlay-01lrlebu/lava-13420363/bin/lava-os-build
137 19:21:58.673490 Creating /var/lib/lava/dispatcher/tmp/13420363/lava-overlay-01lrlebu/lava-13420363/bin/lava-probe-channel
138 19:21:58.673615 Creating /var/lib/lava/dispatcher/tmp/13420363/lava-overlay-01lrlebu/lava-13420363/bin/lava-probe-ip
139 19:21:58.673740 Creating /var/lib/lava/dispatcher/tmp/13420363/lava-overlay-01lrlebu/lava-13420363/bin/lava-target-ip
140 19:21:58.673862 Creating /var/lib/lava/dispatcher/tmp/13420363/lava-overlay-01lrlebu/lava-13420363/bin/lava-target-mac
141 19:21:58.673984 Creating /var/lib/lava/dispatcher/tmp/13420363/lava-overlay-01lrlebu/lava-13420363/bin/lava-target-storage
142 19:21:58.674152 Creating /var/lib/lava/dispatcher/tmp/13420363/lava-overlay-01lrlebu/lava-13420363/bin/lava-test-case
143 19:21:58.674277 Creating /var/lib/lava/dispatcher/tmp/13420363/lava-overlay-01lrlebu/lava-13420363/bin/lava-test-event
144 19:21:58.674399 Creating /var/lib/lava/dispatcher/tmp/13420363/lava-overlay-01lrlebu/lava-13420363/bin/lava-test-feedback
145 19:21:58.674524 Creating /var/lib/lava/dispatcher/tmp/13420363/lava-overlay-01lrlebu/lava-13420363/bin/lava-test-raise
146 19:21:58.674648 Creating /var/lib/lava/dispatcher/tmp/13420363/lava-overlay-01lrlebu/lava-13420363/bin/lava-test-reference
147 19:21:58.674771 Creating /var/lib/lava/dispatcher/tmp/13420363/lava-overlay-01lrlebu/lava-13420363/bin/lava-test-runner
148 19:21:58.674895 Creating /var/lib/lava/dispatcher/tmp/13420363/lava-overlay-01lrlebu/lava-13420363/bin/lava-test-set
149 19:21:58.675050 Creating /var/lib/lava/dispatcher/tmp/13420363/lava-overlay-01lrlebu/lava-13420363/bin/lava-test-shell
150 19:21:58.675177 Updating /var/lib/lava/dispatcher/tmp/13420363/lava-overlay-01lrlebu/lava-13420363/bin/lava-install-packages (oe)
151 19:21:58.675329 Updating /var/lib/lava/dispatcher/tmp/13420363/lava-overlay-01lrlebu/lava-13420363/bin/lava-installed-packages (oe)
152 19:21:58.675467 Creating /var/lib/lava/dispatcher/tmp/13420363/lava-overlay-01lrlebu/lava-13420363/environment
153 19:21:58.675581 LAVA metadata
154 19:21:58.675658 - LAVA_JOB_ID=13420363
155 19:21:58.675724 - LAVA_DISPATCHER_IP=192.168.201.1
156 19:21:58.675825 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:58) [common]
157 19:21:58.675890 skipped lava-vland-overlay
158 19:21:58.675964 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 19:21:58.676043 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:58) [common]
160 19:21:58.676106 skipped lava-multinode-overlay
161 19:21:58.676181 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 19:21:58.676284 start: 1.5.2.3 test-definition (timeout 00:09:58) [common]
163 19:21:58.676361 Loading test definitions
164 19:21:58.676455 start: 1.5.2.3.1 git-repo-action (timeout 00:09:58) [common]
165 19:21:58.676528 Using /lava-13420363 at stage 0
166 19:21:58.676625 Fetching tests from https://github.com/kernelci/kernelci-core
167 19:21:58.676718 Running '/usr/bin/git clone -b kernelci.org --depth=1 https://github.com/kernelci/kernelci-core /var/lib/lava/dispatcher/tmp/13420363/lava-overlay-01lrlebu/lava-13420363/0/tests/0_sleep'
168 19:21:59.344942 Removing '.git' directory in /var/lib/lava/dispatcher/tmp/13420363/lava-overlay-01lrlebu/lava-13420363/0/tests/0_sleep
169 19:21:59.346225 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/13420363/lava-overlay-01lrlebu/lava-13420363/0/tests/0_sleep/config/lava/sleep/sleep.yaml
170 19:21:59.346611 uuid=13420363_1.5.2.3.1 testdef=None
171 19:21:59.346756 end: 1.5.2.3.1 git-repo-action (duration 00:00:01) [common]
173 19:21:59.347010 start: 1.5.2.3.2 test-overlay (timeout 00:09:58) [common]
174 19:21:59.347572 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
176 19:21:59.347800 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:58) [common]
177 19:21:59.348542 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
179 19:21:59.348779 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:58) [common]
180 19:21:59.349442 runner path: /var/lib/lava/dispatcher/tmp/13420363/lava-overlay-01lrlebu/lava-13420363/0/tests/0_sleep test_uuid 13420363_1.5.2.3.1
181 19:21:59.349527 sleep_params='mem'
182 19:21:59.349670 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
184 19:21:59.349889 Creating lava-test-runner.conf files
185 19:21:59.349954 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/13420363/lava-overlay-01lrlebu/lava-13420363/0 for stage 0
186 19:21:59.350070 - 0_sleep
187 19:21:59.350185 end: 1.5.2.3 test-definition (duration 00:00:01) [common]
188 19:21:59.350272 start: 1.5.2.4 compress-overlay (timeout 00:09:58) [common]
189 19:21:59.494756 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
190 19:21:59.494917 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:58) [common]
191 19:21:59.495012 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
192 19:21:59.495109 end: 1.5.2 lava-overlay (duration 00:00:01) [common]
193 19:21:59.495197 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:58) [common]
194 19:22:02.371377 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:03) [common]
195 19:22:02.371932 start: 1.5.4 extract-modules (timeout 00:09:55) [common]
196 19:22:02.372125 extracting modules file /var/lib/lava/dispatcher/tmp/13420363/tftp-deploy-v5h0r7fo/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13420363/extract-overlay-ramdisk-dc67pbiy/ramdisk
197 19:22:02.612922 end: 1.5.4 extract-modules (duration 00:00:00) [common]
198 19:22:02.613106 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
199 19:22:02.613211 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13420363/compress-overlay-zgtpa3cs/overlay-1.5.2.4.tar.gz to ramdisk
200 19:22:02.613285 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13420363/compress-overlay-zgtpa3cs/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/13420363/extract-overlay-ramdisk-dc67pbiy/ramdisk
201 19:22:02.716281 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
202 19:22:02.716440 start: 1.5.6 configure-preseed-file (timeout 00:09:54) [common]
203 19:22:02.716537 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
204 19:22:02.716629 start: 1.5.7 compress-ramdisk (timeout 00:09:54) [common]
205 19:22:02.716712 Building ramdisk /var/lib/lava/dispatcher/tmp/13420363/extract-overlay-ramdisk-dc67pbiy/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/13420363/extract-overlay-ramdisk-dc67pbiy/ramdisk
206 19:22:04.457621 >> 675492 blocks
207 19:22:15.696301 rename /var/lib/lava/dispatcher/tmp/13420363/extract-overlay-ramdisk-dc67pbiy/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/13420363/tftp-deploy-v5h0r7fo/ramdisk/ramdisk.cpio.gz
208 19:22:15.696760 end: 1.5.7 compress-ramdisk (duration 00:00:13) [common]
209 19:22:15.696886 start: 1.5.8 prepare-kernel (timeout 00:09:41) [common]
210 19:22:15.696984 start: 1.5.8.1 prepare-fit (timeout 00:09:41) [common]
211 19:22:15.697095 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/13420363/tftp-deploy-v5h0r7fo/kernel/Image'
212 19:22:28.762598 Returned 0 in 13 seconds
213 19:22:28.863221 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/13420363/tftp-deploy-v5h0r7fo/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/13420363/tftp-deploy-v5h0r7fo/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/13420363/tftp-deploy-v5h0r7fo/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/13420363/tftp-deploy-v5h0r7fo/kernel/image.itb
214 19:22:30.238128 output: FIT description: Kernel Image image with one or more FDT blobs
215 19:22:30.238499 output: Created: Thu Apr 18 20:22:29 2024
216 19:22:30.238575 output: Image 0 (kernel-1)
217 19:22:30.238642 output: Description:
218 19:22:30.238704 output: Created: Thu Apr 18 20:22:29 2024
219 19:22:30.238768 output: Type: Kernel Image
220 19:22:30.238830 output: Compression: lzma compressed
221 19:22:30.238889 output: Data Size: 12910355 Bytes = 12607.77 KiB = 12.31 MiB
222 19:22:30.238949 output: Architecture: AArch64
223 19:22:30.239008 output: OS: Linux
224 19:22:30.239067 output: Load Address: 0x00000000
225 19:22:30.239122 output: Entry Point: 0x00000000
226 19:22:30.239176 output: Hash algo: crc32
227 19:22:30.239230 output: Hash value: bbac8b0b
228 19:22:30.239286 output: Image 1 (fdt-1)
229 19:22:30.239340 output: Description: mt8192-asurada-spherion-r0
230 19:22:30.239395 output: Created: Thu Apr 18 20:22:29 2024
231 19:22:30.239450 output: Type: Flat Device Tree
232 19:22:30.239504 output: Compression: uncompressed
233 19:22:30.239557 output: Data Size: 47230 Bytes = 46.12 KiB = 0.05 MiB
234 19:22:30.239611 output: Architecture: AArch64
235 19:22:30.239663 output: Hash algo: crc32
236 19:22:30.239716 output: Hash value: 4bf0d1ac
237 19:22:30.239770 output: Image 2 (ramdisk-1)
238 19:22:30.239823 output: Description: unavailable
239 19:22:30.239876 output: Created: Thu Apr 18 20:22:29 2024
240 19:22:30.239930 output: Type: RAMDisk Image
241 19:22:30.239984 output: Compression: Unknown Compression
242 19:22:30.240038 output: Data Size: 109022000 Bytes = 106466.80 KiB = 103.97 MiB
243 19:22:30.240120 output: Architecture: AArch64
244 19:22:30.240174 output: OS: Linux
245 19:22:30.240227 output: Load Address: unavailable
246 19:22:30.240280 output: Entry Point: unavailable
247 19:22:30.240346 output: Hash algo: crc32
248 19:22:30.240413 output: Hash value: 58cdb17e
249 19:22:30.240466 output: Default Configuration: 'conf-1'
250 19:22:30.240519 output: Configuration 0 (conf-1)
251 19:22:30.240571 output: Description: mt8192-asurada-spherion-r0
252 19:22:30.240624 output: Kernel: kernel-1
253 19:22:30.240676 output: Init Ramdisk: ramdisk-1
254 19:22:30.240729 output: FDT: fdt-1
255 19:22:30.240781 output: Loadables: kernel-1
256 19:22:30.240834 output:
257 19:22:30.241043 end: 1.5.8.1 prepare-fit (duration 00:00:15) [common]
258 19:22:30.241139 end: 1.5.8 prepare-kernel (duration 00:00:15) [common]
259 19:22:30.241240 end: 1.5 prepare-tftp-overlay (duration 00:00:32) [common]
260 19:22:30.241338 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:27) [common]
261 19:22:30.241419 No LXC device requested
262 19:22:30.241498 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
263 19:22:30.241581 start: 1.7 deploy-device-env (timeout 00:09:27) [common]
264 19:22:30.241658 end: 1.7 deploy-device-env (duration 00:00:00) [common]
265 19:22:30.241729 Checking files for TFTP limit of 4294967296 bytes.
266 19:22:30.242262 end: 1 tftp-deploy (duration 00:00:33) [common]
267 19:22:30.242374 start: 2 depthcharge-action (timeout 00:05:00) [common]
268 19:22:30.242481 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
269 19:22:30.242610 substitutions:
270 19:22:30.242682 - {DTB}: 13420363/tftp-deploy-v5h0r7fo/dtb/mt8192-asurada-spherion-r0.dtb
271 19:22:30.242747 - {INITRD}: 13420363/tftp-deploy-v5h0r7fo/ramdisk/ramdisk.cpio.gz
272 19:22:30.242807 - {KERNEL}: 13420363/tftp-deploy-v5h0r7fo/kernel/Image
273 19:22:30.242866 - {LAVA_MAC}: None
274 19:22:30.242936 - {PRESEED_CONFIG}: None
275 19:22:30.243000 - {PRESEED_LOCAL}: None
276 19:22:30.243059 - {RAMDISK}: 13420363/tftp-deploy-v5h0r7fo/ramdisk/ramdisk.cpio.gz
277 19:22:30.243117 - {ROOT_PART}: None
278 19:22:30.243174 - {ROOT}: None
279 19:22:30.243248 - {SERVER_IP}: 192.168.201.1
280 19:22:30.243306 - {TEE}: None
281 19:22:30.243363 Parsed boot commands:
282 19:22:30.243418 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
283 19:22:30.243600 Parsed boot commands: tftpboot 192.168.201.1 13420363/tftp-deploy-v5h0r7fo/kernel/image.itb 13420363/tftp-deploy-v5h0r7fo/kernel/cmdline
284 19:22:30.243693 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
285 19:22:30.243778 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
286 19:22:30.243873 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
287 19:22:30.243980 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
288 19:22:30.244054 Not connected, no need to disconnect.
289 19:22:30.244130 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
290 19:22:30.244211 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
291 19:22:30.244278 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
292 19:22:30.248338 Setting prompt string to ['lava-test: # ']
293 19:22:30.248754 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
294 19:22:30.248863 end: 2.2.1 reset-connection (duration 00:00:00) [common]
295 19:22:30.248963 start: 2.2.2 reset-device (timeout 00:05:00) [common]
296 19:22:30.249057 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
297 19:22:30.249258 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=reboot'
298 19:22:35.380910 >> Command sent successfully.
299 19:22:35.383195 Returned 0 in 5 seconds
300 19:22:35.483588 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
302 19:22:35.483922 end: 2.2.2 reset-device (duration 00:00:05) [common]
303 19:22:35.484021 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
304 19:22:35.484111 Setting prompt string to 'Starting depthcharge on Spherion...'
305 19:22:35.484184 Changing prompt to 'Starting depthcharge on Spherion...'
306 19:22:35.484254 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
307 19:22:35.484518 [Enter `^Ec?' for help]
308 19:22:35.892190 ol-activate state changed from w
309 19:22:35.892724 F0: 102B 0000
310 19:22:35.893093
311 19:22:35.894993 F3: 1001 0000 [0200]
312 19:22:35.895469
313 19:22:35.895866 F3: 1001 0000
314 19:22:35.896200
315 19:22:35.896515 F7: 102D 0000
316 19:22:35.896822
317 19:22:35.898532 F1: 0000 0000
318 19:22:35.898968
319 19:22:35.899343 V0: 0000 0000 [0001]
320 19:22:35.899692
321 19:22:35.902230 00: 0007 8000
322 19:22:35.902825
323 19:22:35.903294 01: 0000 0000
324 19:22:35.903809
325 19:22:35.905389 BP: 0C00 0209 [0000]
326 19:22:35.905935
327 19:22:35.906377 G0: 1182 0000
328 19:22:35.906785
329 19:22:35.908536 EC: 0000 0021 [4000]
330 19:22:35.909137
331 19:22:35.909674 S7: 0000 0000 [0000]
332 19:22:35.910226
333 19:22:35.912009 CC: 0000 0000 [0001]
334 19:22:35.912618
335 19:22:35.913159 T0: 0000 0040 [010F]
336 19:22:35.913681
337 19:22:35.915043 Jump to BL
338 19:22:35.915592
339 19:22:35.938561
340 19:22:35.939175
341 19:22:35.939795
342 19:22:35.948518 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
343 19:22:35.952050 ARM64: Exception handlers installed.
344 19:22:35.952691 ARM64: Testing exception
345 19:22:35.955480 ARM64: Done test exception
346 19:22:35.962192 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
347 19:22:35.972278 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
348 19:22:35.978949 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
349 19:22:35.989944 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
350 19:22:35.996256 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
351 19:22:36.006856 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
352 19:22:36.016968 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
353 19:22:36.023766 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
354 19:22:36.041618 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
355 19:22:36.045200 WDT: Last reset was cold boot
356 19:22:36.048428 SPI1(PAD0) initialized at 2873684 Hz
357 19:22:36.051529 SPI5(PAD0) initialized at 992727 Hz
358 19:22:36.055459 VBOOT: Loading verstage.
359 19:22:36.061311 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
360 19:22:36.065180 FMAP: Found "FLASH" version 1.1 at 0x20000.
361 19:22:36.068690 FMAP: base = 0x0 size = 0x800000 #areas = 25
362 19:22:36.071510 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
363 19:22:36.079368 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
364 19:22:36.085838 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
365 19:22:36.096525 read SPI 0x96554 0xa1eb: 4595 us, 9020 KB/s, 72.160 Mbps
366 19:22:36.097112
367 19:22:36.097696
368 19:22:36.106591 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
369 19:22:36.109974 ARM64: Exception handlers installed.
370 19:22:36.113174 ARM64: Testing exception
371 19:22:36.113805 ARM64: Done test exception
372 19:22:36.120154 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
373 19:22:36.123526 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
374 19:22:36.137855 Probing TPM: . done!
375 19:22:36.138338 TPM ready after 0 ms
376 19:22:36.144479 Connected to device vid:did:rid of 1ae0:0028:00
377 19:22:36.151039 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
378 19:22:36.212956 Initialized TPM device CR50 revision 0
379 19:22:36.241807 tlcl_send_startup: Startup return code is 0
380 19:22:36.242303 TPM: setup succeeded
381 19:22:36.255804 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
382 19:22:36.264885 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
383 19:22:36.277498 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
384 19:22:36.287044 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
385 19:22:36.290744 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
386 19:22:36.293833 in-header: 03 07 00 00 08 00 00 00
387 19:22:36.297803 in-data: aa e4 47 04 13 02 00 00
388 19:22:36.301303 Chrome EC: UHEPI supported
389 19:22:36.304745 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
390 19:22:36.311582 in-header: 03 ad 00 00 08 00 00 00
391 19:22:36.315024 in-data: 00 20 20 08 00 00 00 00
392 19:22:36.315452 Phase 1
393 19:22:36.318909 FMAP: area GBB found @ 3f5000 (12032 bytes)
394 19:22:36.325573 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
395 19:22:36.333243 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
396 19:22:36.333760 Recovery requested (1009000e)
397 19:22:36.343619 TPM: Extending digest for VBOOT: boot mode into PCR 0
398 19:22:36.349417 tlcl_extend: response is 0
399 19:22:36.358541 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
400 19:22:36.364434 tlcl_extend: response is 0
401 19:22:36.370906 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
402 19:22:36.391617 read SPI 0x210d4 0x2173b: 15144 us, 9047 KB/s, 72.376 Mbps
403 19:22:36.398660 BS: bootblock times (exec / console): total (unknown) / 148 ms
404 19:22:36.399093
405 19:22:36.399515
406 19:22:36.409938 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
407 19:22:36.410437 ARM64: Exception handlers installed.
408 19:22:36.413128 ARM64: Testing exception
409 19:22:36.416243 ARM64: Done test exception
410 19:22:36.436676 pmic_efuse_setting: Set efuses in 11 msecs
411 19:22:36.440022 pmwrap_interface_init: Select PMIF_VLD_RDY
412 19:22:36.447011 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
413 19:22:36.450072 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
414 19:22:36.456919 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
415 19:22:36.460008 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
416 19:22:36.466632 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
417 19:22:36.469828 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
418 19:22:36.473427 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
419 19:22:36.479872 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
420 19:22:36.483456 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
421 19:22:36.490169 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
422 19:22:36.493364 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
423 19:22:36.496655 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
424 19:22:36.503253 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
425 19:22:36.510103 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
426 19:22:36.513013 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
427 19:22:36.519768 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
428 19:22:36.526786 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
429 19:22:36.533019 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
430 19:22:36.536182 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
431 19:22:36.543085 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
432 19:22:36.549706 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
433 19:22:36.553023 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
434 19:22:36.559836 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
435 19:22:36.566610 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
436 19:22:36.569605 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
437 19:22:36.576567 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
438 19:22:36.579635 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
439 19:22:36.586674 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
440 19:22:36.589581 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
441 19:22:36.596171 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
442 19:22:36.599657 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
443 19:22:36.606440 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
444 19:22:36.610093 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
445 19:22:36.616079 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
446 19:22:36.619581 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
447 19:22:36.626237 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
448 19:22:36.629638 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
449 19:22:36.636289 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
450 19:22:36.639396 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
451 19:22:36.646209 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
452 19:22:36.649693 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
453 19:22:36.652581 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
454 19:22:36.656067 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
455 19:22:36.662659 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
456 19:22:36.665853 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
457 19:22:36.669394 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
458 19:22:36.675723 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
459 19:22:36.679325 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
460 19:22:36.682801 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
461 19:22:36.689343 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
462 19:22:36.692507 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
463 19:22:36.699061 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
464 19:22:36.708939 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
465 19:22:36.712319 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
466 19:22:36.718984 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
467 19:22:36.728930 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
468 19:22:36.732090 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
469 19:22:36.738992 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
470 19:22:36.742140 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
471 19:22:36.749449 [RTC]rtc_enable_dcxo,68: con=0x406, osc32con=0xde70, sec=0xe
472 19:22:36.755974 [RTC]rtc_check_state,173: con=406, pwrkey1=a357, pwrkey2=67d2
473 19:22:36.759117 [RTC]rtc_osc_init,62: osc32con val = 0xde70
474 19:22:36.762578 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
475 19:22:36.773843 [RTC]rtc_get_frequency_meter,154: input=15, output=764
476 19:22:36.783017 [RTC]rtc_get_frequency_meter,154: input=23, output=947
477 19:22:36.792714 [RTC]rtc_get_frequency_meter,154: input=19, output=856
478 19:22:36.801941 [RTC]rtc_get_frequency_meter,154: input=17, output=810
479 19:22:36.811891 [RTC]rtc_get_frequency_meter,154: input=16, output=788
480 19:22:36.820999 [RTC]rtc_get_frequency_meter,154: input=16, output=787
481 19:22:36.830941 [RTC]rtc_get_frequency_meter,154: input=17, output=811
482 19:22:36.834066 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
483 19:22:36.841474 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
484 19:22:36.844763 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
485 19:22:36.847959 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
486 19:22:36.854541 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
487 19:22:36.857984 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
488 19:22:36.861113 ADC[4]: Raw value=669695 ID=5
489 19:22:36.861211 ADC[3]: Raw value=212917 ID=1
490 19:22:36.864300 RAM Code: 0x51
491 19:22:36.867642 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
492 19:22:36.874626 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
493 19:22:36.881027 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
494 19:22:36.887863 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
495 19:22:36.890930 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
496 19:22:36.894440 in-header: 03 07 00 00 08 00 00 00
497 19:22:36.897759 in-data: aa e4 47 04 13 02 00 00
498 19:22:36.901025 Chrome EC: UHEPI supported
499 19:22:36.907914 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
500 19:22:36.911188 in-header: 03 ed 00 00 08 00 00 00
501 19:22:36.914955 in-data: 80 20 60 08 00 00 00 00
502 19:22:36.915039 MRC: failed to locate region type 0.
503 19:22:36.921189 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
504 19:22:36.924401 DRAM-K: Running full calibration
505 19:22:36.931484 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
506 19:22:36.934666 header.status = 0x0
507 19:22:36.938635 header.version = 0x6 (expected: 0x6)
508 19:22:36.938720 header.size = 0xd00 (expected: 0xd00)
509 19:22:36.942100 header.flags = 0x0
510 19:22:36.949002 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
511 19:22:36.966244 read SPI 0x72590 0x1c583: 12503 us, 9285 KB/s, 74.280 Mbps
512 19:22:36.973189 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
513 19:22:36.976400 dram_init: ddr_geometry: 0
514 19:22:36.976486 [EMI] MDL number = 0
515 19:22:36.979764 [EMI] Get MDL freq = 0
516 19:22:36.979849 dram_init: ddr_type: 0
517 19:22:36.983180 is_discrete_lpddr4: 1
518 19:22:36.986483 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
519 19:22:36.986571
520 19:22:36.986639
521 19:22:36.989957 [Bian_co] ETT version 0.0.0.1
522 19:22:36.993377 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
523 19:22:36.993461
524 19:22:36.999972 dramc_set_vcore_voltage set vcore to 650000
525 19:22:37.000056 Read voltage for 800, 4
526 19:22:37.003230 Vio18 = 0
527 19:22:37.003314 Vcore = 650000
528 19:22:37.003381 Vdram = 0
529 19:22:37.003444 Vddq = 0
530 19:22:37.006418 Vmddr = 0
531 19:22:37.006501 dram_init: config_dvfs: 1
532 19:22:37.013054 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
533 19:22:37.019859 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
534 19:22:37.023280 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
535 19:22:37.026429 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
536 19:22:37.029637 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
537 19:22:37.032773 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
538 19:22:37.036549 MEM_TYPE=3, freq_sel=18
539 19:22:37.039850 sv_algorithm_assistance_LP4_1600
540 19:22:37.043020 ============ PULL DRAM RESETB DOWN ============
541 19:22:37.046670 ========== PULL DRAM RESETB DOWN end =========
542 19:22:37.052810 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
543 19:22:37.055930 ===================================
544 19:22:37.056015 LPDDR4 DRAM CONFIGURATION
545 19:22:37.059173 ===================================
546 19:22:37.062588 EX_ROW_EN[0] = 0x0
547 19:22:37.062672 EX_ROW_EN[1] = 0x0
548 19:22:37.065937 LP4Y_EN = 0x0
549 19:22:37.069416 WORK_FSP = 0x0
550 19:22:37.069500 WL = 0x2
551 19:22:37.072625 RL = 0x2
552 19:22:37.072709 BL = 0x2
553 19:22:37.076114 RPST = 0x0
554 19:22:37.076198 RD_PRE = 0x0
555 19:22:37.079295 WR_PRE = 0x1
556 19:22:37.079379 WR_PST = 0x0
557 19:22:37.082895 DBI_WR = 0x0
558 19:22:37.082980 DBI_RD = 0x0
559 19:22:37.086055 OTF = 0x1
560 19:22:37.089188 ===================================
561 19:22:37.092463 ===================================
562 19:22:37.092548 ANA top config
563 19:22:37.095882 ===================================
564 19:22:37.099038 DLL_ASYNC_EN = 0
565 19:22:37.102554 ALL_SLAVE_EN = 1
566 19:22:37.102655 NEW_RANK_MODE = 1
567 19:22:37.106161 DLL_IDLE_MODE = 1
568 19:22:37.109260 LP45_APHY_COMB_EN = 1
569 19:22:37.112627 TX_ODT_DIS = 1
570 19:22:37.116279 NEW_8X_MODE = 1
571 19:22:37.116365 ===================================
572 19:22:37.119498 ===================================
573 19:22:37.122861 data_rate = 1600
574 19:22:37.126007 CKR = 1
575 19:22:37.129555 DQ_P2S_RATIO = 8
576 19:22:37.133243 ===================================
577 19:22:37.136335 CA_P2S_RATIO = 8
578 19:22:37.139311 DQ_CA_OPEN = 0
579 19:22:37.142635 DQ_SEMI_OPEN = 0
580 19:22:37.142720 CA_SEMI_OPEN = 0
581 19:22:37.145812 CA_FULL_RATE = 0
582 19:22:37.149288 DQ_CKDIV4_EN = 1
583 19:22:37.152399 CA_CKDIV4_EN = 1
584 19:22:37.155764 CA_PREDIV_EN = 0
585 19:22:37.159261 PH8_DLY = 0
586 19:22:37.159345 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
587 19:22:37.162431 DQ_AAMCK_DIV = 4
588 19:22:37.165941 CA_AAMCK_DIV = 4
589 19:22:37.169190 CA_ADMCK_DIV = 4
590 19:22:37.172478 DQ_TRACK_CA_EN = 0
591 19:22:37.176039 CA_PICK = 800
592 19:22:37.176121 CA_MCKIO = 800
593 19:22:37.179313 MCKIO_SEMI = 0
594 19:22:37.182663 PLL_FREQ = 3068
595 19:22:37.186607 DQ_UI_PI_RATIO = 32
596 19:22:37.189850 CA_UI_PI_RATIO = 0
597 19:22:37.192917 ===================================
598 19:22:37.195700 ===================================
599 19:22:37.199181 memory_type:LPDDR4
600 19:22:37.199265 GP_NUM : 10
601 19:22:37.202569 SRAM_EN : 1
602 19:22:37.202653 MD32_EN : 0
603 19:22:37.205914 ===================================
604 19:22:37.209069 [ANA_INIT] >>>>>>>>>>>>>>
605 19:22:37.212376 <<<<<< [CONFIGURE PHASE]: ANA_TX
606 19:22:37.215749 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
607 19:22:37.219073 ===================================
608 19:22:37.222386 data_rate = 1600,PCW = 0X7600
609 19:22:37.225891 ===================================
610 19:22:37.229045 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
611 19:22:37.232565 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
612 19:22:37.239136 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
613 19:22:37.242396 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
614 19:22:37.246169 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
615 19:22:37.252506 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
616 19:22:37.252593 [ANA_INIT] flow start
617 19:22:37.255987 [ANA_INIT] PLL >>>>>>>>
618 19:22:37.256070 [ANA_INIT] PLL <<<<<<<<
619 19:22:37.259136 [ANA_INIT] MIDPI >>>>>>>>
620 19:22:37.262465 [ANA_INIT] MIDPI <<<<<<<<
621 19:22:37.265561 [ANA_INIT] DLL >>>>>>>>
622 19:22:37.265631 [ANA_INIT] flow end
623 19:22:37.268992 ============ LP4 DIFF to SE enter ============
624 19:22:37.276451 ============ LP4 DIFF to SE exit ============
625 19:22:37.276535 [ANA_INIT] <<<<<<<<<<<<<
626 19:22:37.279575 [Flow] Enable top DCM control >>>>>
627 19:22:37.283117 [Flow] Enable top DCM control <<<<<
628 19:22:37.286494 Enable DLL master slave shuffle
629 19:22:37.293220 ==============================================================
630 19:22:37.293307 Gating Mode config
631 19:22:37.299876 ==============================================================
632 19:22:37.299963 Config description:
633 19:22:37.309727 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
634 19:22:37.316885 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
635 19:22:37.323005 SELPH_MODE 0: By rank 1: By Phase
636 19:22:37.326555 ==============================================================
637 19:22:37.329989 GAT_TRACK_EN = 1
638 19:22:37.332929 RX_GATING_MODE = 2
639 19:22:37.336181 RX_GATING_TRACK_MODE = 2
640 19:22:37.339953 SELPH_MODE = 1
641 19:22:37.343051 PICG_EARLY_EN = 1
642 19:22:37.346190 VALID_LAT_VALUE = 1
643 19:22:37.353039 ==============================================================
644 19:22:37.356229 Enter into Gating configuration >>>>
645 19:22:37.359938 Exit from Gating configuration <<<<
646 19:22:37.363085 Enter into DVFS_PRE_config >>>>>
647 19:22:37.372671 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
648 19:22:37.376445 Exit from DVFS_PRE_config <<<<<
649 19:22:37.379355 Enter into PICG configuration >>>>
650 19:22:37.383185 Exit from PICG configuration <<<<
651 19:22:37.383287 [RX_INPUT] configuration >>>>>
652 19:22:37.386526 [RX_INPUT] configuration <<<<<
653 19:22:37.393464 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
654 19:22:37.396943 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
655 19:22:37.404505 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
656 19:22:37.410813 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
657 19:22:37.417281 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
658 19:22:37.423878 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
659 19:22:37.427393 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
660 19:22:37.430555 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
661 19:22:37.434411 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
662 19:22:37.441008 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
663 19:22:37.443854 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
664 19:22:37.447638 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
665 19:22:37.450582 ===================================
666 19:22:37.454189 LPDDR4 DRAM CONFIGURATION
667 19:22:37.457522 ===================================
668 19:22:37.457605 EX_ROW_EN[0] = 0x0
669 19:22:37.460701 EX_ROW_EN[1] = 0x0
670 19:22:37.460783 LP4Y_EN = 0x0
671 19:22:37.463877 WORK_FSP = 0x0
672 19:22:37.463960 WL = 0x2
673 19:22:37.467426 RL = 0x2
674 19:22:37.467508 BL = 0x2
675 19:22:37.470942 RPST = 0x0
676 19:22:37.473877 RD_PRE = 0x0
677 19:22:37.473988 WR_PRE = 0x1
678 19:22:37.477431 WR_PST = 0x0
679 19:22:37.477513 DBI_WR = 0x0
680 19:22:37.480538 DBI_RD = 0x0
681 19:22:37.480621 OTF = 0x1
682 19:22:37.483939 ===================================
683 19:22:37.487221 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
684 19:22:37.490683 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
685 19:22:37.497770 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
686 19:22:37.501019 ===================================
687 19:22:37.504177 LPDDR4 DRAM CONFIGURATION
688 19:22:37.507280 ===================================
689 19:22:37.507362 EX_ROW_EN[0] = 0x10
690 19:22:37.510829 EX_ROW_EN[1] = 0x0
691 19:22:37.510911 LP4Y_EN = 0x0
692 19:22:37.514517 WORK_FSP = 0x0
693 19:22:37.514600 WL = 0x2
694 19:22:37.517966 RL = 0x2
695 19:22:37.518101 BL = 0x2
696 19:22:37.521811 RPST = 0x0
697 19:22:37.521893 RD_PRE = 0x0
698 19:22:37.525392 WR_PRE = 0x1
699 19:22:37.525473 WR_PST = 0x0
700 19:22:37.528946 DBI_WR = 0x0
701 19:22:37.529028 DBI_RD = 0x0
702 19:22:37.529093 OTF = 0x1
703 19:22:37.532211 ===================================
704 19:22:37.539303 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
705 19:22:37.544264 nWR fixed to 40
706 19:22:37.544348 [ModeRegInit_LP4] CH0 RK0
707 19:22:37.547675 [ModeRegInit_LP4] CH0 RK1
708 19:22:37.550836 [ModeRegInit_LP4] CH1 RK0
709 19:22:37.554556 [ModeRegInit_LP4] CH1 RK1
710 19:22:37.554639 match AC timing 12
711 19:22:37.557779 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
712 19:22:37.561559 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
713 19:22:37.568432 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
714 19:22:37.572007 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
715 19:22:37.576250 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
716 19:22:37.579504 [EMI DOE] emi_dcm 0
717 19:22:37.582974 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
718 19:22:37.583059 ==
719 19:22:37.586321 Dram Type= 6, Freq= 0, CH_0, rank 0
720 19:22:37.589870 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
721 19:22:37.589998 ==
722 19:22:37.597619 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
723 19:22:37.600831 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
724 19:22:37.611462 [CA 0] Center 37 (7~68) winsize 62
725 19:22:37.615053 [CA 1] Center 37 (7~68) winsize 62
726 19:22:37.618340 [CA 2] Center 35 (5~66) winsize 62
727 19:22:37.621735 [CA 3] Center 35 (5~66) winsize 62
728 19:22:37.624889 [CA 4] Center 34 (4~65) winsize 62
729 19:22:37.627977 [CA 5] Center 33 (3~64) winsize 62
730 19:22:37.628061
731 19:22:37.631428 [CmdBusTrainingLP45] Vref(ca) range 1: 32
732 19:22:37.631512
733 19:22:37.634931 [CATrainingPosCal] consider 1 rank data
734 19:22:37.638846 u2DelayCellTimex100 = 270/100 ps
735 19:22:37.641584 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
736 19:22:37.644735 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
737 19:22:37.648522 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
738 19:22:37.654741 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
739 19:22:37.658503 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
740 19:22:37.662338 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
741 19:22:37.662436
742 19:22:37.665888 CA PerBit enable=1, Macro0, CA PI delay=33
743 19:22:37.666044
744 19:22:37.669266 [CBTSetCACLKResult] CA Dly = 33
745 19:22:37.669349 CS Dly: 6 (0~37)
746 19:22:37.669416 ==
747 19:22:37.672857 Dram Type= 6, Freq= 0, CH_0, rank 1
748 19:22:37.676482 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
749 19:22:37.676566 ==
750 19:22:37.683238 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
751 19:22:37.690153 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
752 19:22:37.697364 [CA 0] Center 37 (7~68) winsize 62
753 19:22:37.701403 [CA 1] Center 37 (6~68) winsize 63
754 19:22:37.704822 [CA 2] Center 35 (5~66) winsize 62
755 19:22:37.708528 [CA 3] Center 35 (4~66) winsize 63
756 19:22:37.711702 [CA 4] Center 34 (4~64) winsize 61
757 19:22:37.715439 [CA 5] Center 34 (3~65) winsize 63
758 19:22:37.715518
759 19:22:37.719336 [CmdBusTrainingLP45] Vref(ca) range 1: 34
760 19:22:37.719419
761 19:22:37.723058 [CATrainingPosCal] consider 2 rank data
762 19:22:37.723141 u2DelayCellTimex100 = 270/100 ps
763 19:22:37.730014 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
764 19:22:37.734241 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
765 19:22:37.737554 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
766 19:22:37.741009 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
767 19:22:37.744711 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
768 19:22:37.748635 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
769 19:22:37.748748
770 19:22:37.752183 CA PerBit enable=1, Macro0, CA PI delay=33
771 19:22:37.752282
772 19:22:37.752353 [CBTSetCACLKResult] CA Dly = 33
773 19:22:37.756048 CS Dly: 6 (0~37)
774 19:22:37.756163
775 19:22:37.759391 ----->DramcWriteLeveling(PI) begin...
776 19:22:37.759474 ==
777 19:22:37.762910 Dram Type= 6, Freq= 0, CH_0, rank 0
778 19:22:37.767024 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
779 19:22:37.767107 ==
780 19:22:37.769813 Write leveling (Byte 0): 30 => 30
781 19:22:37.773120 Write leveling (Byte 1): 30 => 30
782 19:22:37.776453 DramcWriteLeveling(PI) end<-----
783 19:22:37.776535
784 19:22:37.776600 ==
785 19:22:37.779752 Dram Type= 6, Freq= 0, CH_0, rank 0
786 19:22:37.783338 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
787 19:22:37.783422 ==
788 19:22:37.786523 [Gating] SW mode calibration
789 19:22:37.792856 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
790 19:22:37.799482 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
791 19:22:37.803150 0 6 0 | B1->B0 | 3333 3333 | 1 1 | (0 0) (1 0)
792 19:22:37.806535 0 6 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
793 19:22:37.813098 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 19:22:37.816363 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 19:22:37.819817 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 19:22:37.826576 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 19:22:37.829510 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 19:22:37.832775 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 19:22:37.839622 0 7 0 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (0 0)
800 19:22:37.842703 0 7 4 | B1->B0 | 3b3b 4343 | 0 0 | (0 0) (0 0)
801 19:22:37.846466 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
802 19:22:37.852716 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
803 19:22:37.855953 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
804 19:22:37.859330 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
805 19:22:37.866697 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
806 19:22:37.870195 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
807 19:22:37.873851 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
808 19:22:37.877481 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
809 19:22:37.880961 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
810 19:22:37.888613 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
811 19:22:37.892240 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
812 19:22:37.895967 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
813 19:22:37.899349 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
814 19:22:37.903026 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
815 19:22:37.910484 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
816 19:22:37.914513 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
817 19:22:37.917711 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
818 19:22:37.921457 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
819 19:22:37.925126 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
820 19:22:37.932301 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
821 19:22:37.935858 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
822 19:22:37.939665 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
823 19:22:37.943464 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
824 19:22:37.946789 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
825 19:22:37.950665 Total UI for P1: 0, mck2ui 16
826 19:22:37.954749 best dqsien dly found for B0: ( 0, 10, 0)
827 19:22:37.957889 Total UI for P1: 0, mck2ui 16
828 19:22:37.961518 best dqsien dly found for B1: ( 0, 10, 0)
829 19:22:37.964854 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
830 19:22:37.968604 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
831 19:22:37.968688
832 19:22:37.971661 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
833 19:22:37.975128 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
834 19:22:37.978426 [Gating] SW calibration Done
835 19:22:37.978510 ==
836 19:22:37.982052 Dram Type= 6, Freq= 0, CH_0, rank 0
837 19:22:37.985720 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
838 19:22:37.985805 ==
839 19:22:37.989330 RX Vref Scan: 0
840 19:22:37.989412
841 19:22:37.989479 RX Vref 0 -> 0, step: 1
842 19:22:37.989540
843 19:22:37.992762 RX Delay -130 -> 252, step: 16
844 19:22:37.996789 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
845 19:22:38.000148 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
846 19:22:38.003829 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
847 19:22:38.011053 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
848 19:22:38.014537 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
849 19:22:38.017871 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
850 19:22:38.021725 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
851 19:22:38.025392 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
852 19:22:38.028958 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
853 19:22:38.032611 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
854 19:22:38.036441 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
855 19:22:38.039710 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
856 19:22:38.043551 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
857 19:22:38.051108 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
858 19:22:38.054311 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
859 19:22:38.058264 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
860 19:22:38.058343 ==
861 19:22:38.061454 Dram Type= 6, Freq= 0, CH_0, rank 0
862 19:22:38.065241 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
863 19:22:38.065354 ==
864 19:22:38.065449 DQS Delay:
865 19:22:38.069260 DQS0 = 0, DQS1 = 0
866 19:22:38.069358 DQM Delay:
867 19:22:38.072865 DQM0 = 81, DQM1 = 75
868 19:22:38.072943 DQ Delay:
869 19:22:38.076285 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
870 19:22:38.076385 DQ4 =77, DQ5 =69, DQ6 =93, DQ7 =93
871 19:22:38.080196 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69
872 19:22:38.083962 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
873 19:22:38.084065
874 19:22:38.084166
875 19:22:38.087589 ==
876 19:22:38.087664 Dram Type= 6, Freq= 0, CH_0, rank 0
877 19:22:38.094389 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
878 19:22:38.094479 ==
879 19:22:38.094577
880 19:22:38.094639
881 19:22:38.094710 TX Vref Scan disable
882 19:22:38.098119 == TX Byte 0 ==
883 19:22:38.101953 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
884 19:22:38.105881 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
885 19:22:38.109151 == TX Byte 1 ==
886 19:22:38.113164 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
887 19:22:38.116687 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
888 19:22:38.116792 ==
889 19:22:38.120714 Dram Type= 6, Freq= 0, CH_0, rank 0
890 19:22:38.123551 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
891 19:22:38.123623 ==
892 19:22:38.133970 TX Vref=22, minBit 0, minWin=27, winSum=442
893 19:22:38.141167 TX Vref=24, minBit 0, minWin=27, winSum=447
894 19:22:38.144486 TX Vref=26, minBit 0, minWin=28, winSum=454
895 19:22:38.148318 TX Vref=28, minBit 4, minWin=27, winSum=457
896 19:22:38.151857 TX Vref=30, minBit 0, minWin=28, winSum=457
897 19:22:38.155457 TX Vref=32, minBit 0, minWin=28, winSum=453
898 19:22:38.158952 [TxChooseVref] Worse bit 0, Min win 28, Win sum 457, Final Vref 30
899 19:22:38.162414
900 19:22:38.162487 Final TX Range 1 Vref 30
901 19:22:38.162551
902 19:22:38.162611 ==
903 19:22:38.166611 Dram Type= 6, Freq= 0, CH_0, rank 0
904 19:22:38.169829 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
905 19:22:38.169960 ==
906 19:22:38.170079
907 19:22:38.173637
908 19:22:38.173735 TX Vref Scan disable
909 19:22:38.177056 == TX Byte 0 ==
910 19:22:38.180970 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
911 19:22:38.184189 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
912 19:22:38.187979 == TX Byte 1 ==
913 19:22:38.191449 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
914 19:22:38.195014 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
915 19:22:38.195106
916 19:22:38.195170 [DATLAT]
917 19:22:38.198717 Freq=800, CH0 RK0
918 19:22:38.198826
919 19:22:38.198920 DATLAT Default: 0xa
920 19:22:38.202336 0, 0xFFFF, sum = 0
921 19:22:38.202436 1, 0xFFFF, sum = 0
922 19:22:38.205955 2, 0xFFFF, sum = 0
923 19:22:38.206081 3, 0xFFFF, sum = 0
924 19:22:38.209393 4, 0xFFFF, sum = 0
925 19:22:38.209491 5, 0xFFFF, sum = 0
926 19:22:38.213073 6, 0xFFFF, sum = 0
927 19:22:38.213179 7, 0xFFFF, sum = 0
928 19:22:38.213272 8, 0x0, sum = 1
929 19:22:38.216695 9, 0x0, sum = 2
930 19:22:38.216793 10, 0x0, sum = 3
931 19:22:38.220646 11, 0x0, sum = 4
932 19:22:38.220744 best_step = 9
933 19:22:38.220842
934 19:22:38.220931 ==
935 19:22:38.223955 Dram Type= 6, Freq= 0, CH_0, rank 0
936 19:22:38.227628 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
937 19:22:38.227711 ==
938 19:22:38.231275 RX Vref Scan: 1
939 19:22:38.231346
940 19:22:38.231417 Set Vref Range= 32 -> 127
941 19:22:38.231484
942 19:22:38.234749 RX Vref 32 -> 127, step: 1
943 19:22:38.234854
944 19:22:38.238341 RX Delay -111 -> 252, step: 8
945 19:22:38.238423
946 19:22:38.242113 Set Vref, RX VrefLevel [Byte0]: 32
947 19:22:38.245875 [Byte1]: 32
948 19:22:38.245973
949 19:22:38.249064 Set Vref, RX VrefLevel [Byte0]: 33
950 19:22:38.253262 [Byte1]: 33
951 19:22:38.253363
952 19:22:38.256662 Set Vref, RX VrefLevel [Byte0]: 34
953 19:22:38.260092 [Byte1]: 34
954 19:22:38.260176
955 19:22:38.264448 Set Vref, RX VrefLevel [Byte0]: 35
956 19:22:38.267775 [Byte1]: 35
957 19:22:38.267858
958 19:22:38.271571 Set Vref, RX VrefLevel [Byte0]: 36
959 19:22:38.275046 [Byte1]: 36
960 19:22:38.275131
961 19:22:38.278709 Set Vref, RX VrefLevel [Byte0]: 37
962 19:22:38.282294 [Byte1]: 37
963 19:22:38.285480
964 19:22:38.285564 Set Vref, RX VrefLevel [Byte0]: 38
965 19:22:38.289393 [Byte1]: 38
966 19:22:38.293245
967 19:22:38.293328 Set Vref, RX VrefLevel [Byte0]: 39
968 19:22:38.296598 [Byte1]: 39
969 19:22:38.301622
970 19:22:38.301705 Set Vref, RX VrefLevel [Byte0]: 40
971 19:22:38.304756 [Byte1]: 40
972 19:22:38.309005
973 19:22:38.309115 Set Vref, RX VrefLevel [Byte0]: 41
974 19:22:38.311941 [Byte1]: 41
975 19:22:38.316411
976 19:22:38.316494 Set Vref, RX VrefLevel [Byte0]: 42
977 19:22:38.320017 [Byte1]: 42
978 19:22:38.324132
979 19:22:38.324236 Set Vref, RX VrefLevel [Byte0]: 43
980 19:22:38.327890 [Byte1]: 43
981 19:22:38.331924
982 19:22:38.332000 Set Vref, RX VrefLevel [Byte0]: 44
983 19:22:38.335463 [Byte1]: 44
984 19:22:38.339698
985 19:22:38.339783 Set Vref, RX VrefLevel [Byte0]: 45
986 19:22:38.343077 [Byte1]: 45
987 19:22:38.347355
988 19:22:38.347432 Set Vref, RX VrefLevel [Byte0]: 46
989 19:22:38.350790 [Byte1]: 46
990 19:22:38.354914
991 19:22:38.354986 Set Vref, RX VrefLevel [Byte0]: 47
992 19:22:38.358513 [Byte1]: 47
993 19:22:38.362234
994 19:22:38.362343 Set Vref, RX VrefLevel [Byte0]: 48
995 19:22:38.365634 [Byte1]: 48
996 19:22:38.369717
997 19:22:38.369803 Set Vref, RX VrefLevel [Byte0]: 49
998 19:22:38.373235 [Byte1]: 49
999 19:22:38.377288
1000 19:22:38.377372 Set Vref, RX VrefLevel [Byte0]: 50
1001 19:22:38.380759 [Byte1]: 50
1002 19:22:38.385502
1003 19:22:38.385627 Set Vref, RX VrefLevel [Byte0]: 51
1004 19:22:38.388755 [Byte1]: 51
1005 19:22:38.393216
1006 19:22:38.393319 Set Vref, RX VrefLevel [Byte0]: 52
1007 19:22:38.396456 [Byte1]: 52
1008 19:22:38.400609
1009 19:22:38.400709 Set Vref, RX VrefLevel [Byte0]: 53
1010 19:22:38.404178 [Byte1]: 53
1011 19:22:38.408877
1012 19:22:38.408953 Set Vref, RX VrefLevel [Byte0]: 54
1013 19:22:38.412087 [Byte1]: 54
1014 19:22:38.415795
1015 19:22:38.415879 Set Vref, RX VrefLevel [Byte0]: 55
1016 19:22:38.418983 [Byte1]: 55
1017 19:22:38.423733
1018 19:22:38.423817 Set Vref, RX VrefLevel [Byte0]: 56
1019 19:22:38.426867 [Byte1]: 56
1020 19:22:38.430980
1021 19:22:38.431062 Set Vref, RX VrefLevel [Byte0]: 57
1022 19:22:38.434404 [Byte1]: 57
1023 19:22:38.439049
1024 19:22:38.439132 Set Vref, RX VrefLevel [Byte0]: 58
1025 19:22:38.442083 [Byte1]: 58
1026 19:22:38.446185
1027 19:22:38.446268 Set Vref, RX VrefLevel [Byte0]: 59
1028 19:22:38.449394 [Byte1]: 59
1029 19:22:38.454019
1030 19:22:38.454161 Set Vref, RX VrefLevel [Byte0]: 60
1031 19:22:38.457632 [Byte1]: 60
1032 19:22:38.461860
1033 19:22:38.461960 Set Vref, RX VrefLevel [Byte0]: 61
1034 19:22:38.465243 [Byte1]: 61
1035 19:22:38.469574
1036 19:22:38.469673 Set Vref, RX VrefLevel [Byte0]: 62
1037 19:22:38.473092 [Byte1]: 62
1038 19:22:38.476926
1039 19:22:38.477028 Set Vref, RX VrefLevel [Byte0]: 63
1040 19:22:38.480413 [Byte1]: 63
1041 19:22:38.484951
1042 19:22:38.485034 Set Vref, RX VrefLevel [Byte0]: 64
1043 19:22:38.488295 [Byte1]: 64
1044 19:22:38.492157
1045 19:22:38.492238 Set Vref, RX VrefLevel [Byte0]: 65
1046 19:22:38.495286 [Byte1]: 65
1047 19:22:38.499570
1048 19:22:38.499652 Set Vref, RX VrefLevel [Byte0]: 66
1049 19:22:38.503031 [Byte1]: 66
1050 19:22:38.507202
1051 19:22:38.507274 Set Vref, RX VrefLevel [Byte0]: 67
1052 19:22:38.510821 [Byte1]: 67
1053 19:22:38.514997
1054 19:22:38.515068 Set Vref, RX VrefLevel [Byte0]: 68
1055 19:22:38.518563 [Byte1]: 68
1056 19:22:38.522640
1057 19:22:38.522721 Set Vref, RX VrefLevel [Byte0]: 69
1058 19:22:38.525674 [Byte1]: 69
1059 19:22:38.529980
1060 19:22:38.530106 Set Vref, RX VrefLevel [Byte0]: 70
1061 19:22:38.533474 [Byte1]: 70
1062 19:22:38.537926
1063 19:22:38.538048 Set Vref, RX VrefLevel [Byte0]: 71
1064 19:22:38.541177 [Byte1]: 71
1065 19:22:38.545281
1066 19:22:38.545352 Set Vref, RX VrefLevel [Byte0]: 72
1067 19:22:38.548786 [Byte1]: 72
1068 19:22:38.553318
1069 19:22:38.553400 Set Vref, RX VrefLevel [Byte0]: 73
1070 19:22:38.556417 [Byte1]: 73
1071 19:22:38.560852
1072 19:22:38.560966 Set Vref, RX VrefLevel [Byte0]: 74
1073 19:22:38.564461 [Byte1]: 74
1074 19:22:38.568282
1075 19:22:38.568374 Set Vref, RX VrefLevel [Byte0]: 75
1076 19:22:38.571947 [Byte1]: 75
1077 19:22:38.576105
1078 19:22:38.576205 Final RX Vref Byte 0 = 53 to rank0
1079 19:22:38.579164 Final RX Vref Byte 1 = 55 to rank0
1080 19:22:38.582548 Final RX Vref Byte 0 = 53 to rank1
1081 19:22:38.585898 Final RX Vref Byte 1 = 55 to rank1==
1082 19:22:38.589679 Dram Type= 6, Freq= 0, CH_0, rank 0
1083 19:22:38.596053 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1084 19:22:38.596136 ==
1085 19:22:38.596201 DQS Delay:
1086 19:22:38.596263 DQS0 = 0, DQS1 = 0
1087 19:22:38.599731 DQM Delay:
1088 19:22:38.599813 DQM0 = 83, DQM1 = 73
1089 19:22:38.602796 DQ Delay:
1090 19:22:38.605945 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1091 19:22:38.609311 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =92
1092 19:22:38.609394 DQ8 =64, DQ9 =56, DQ10 =76, DQ11 =64
1093 19:22:38.615943 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1094 19:22:38.616050
1095 19:22:38.616152
1096 19:22:38.622464 [DQSOSCAuto] RK0, (LSB)MR18= 0x3636, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
1097 19:22:38.626238 CH0 RK0: MR19=606, MR18=3636
1098 19:22:38.632477 CH0_RK0: MR19=0x606, MR18=0x3636, DQSOSC=396, MR23=63, INC=94, DEC=62
1099 19:22:38.632592
1100 19:22:38.635974 ----->DramcWriteLeveling(PI) begin...
1101 19:22:38.636082 ==
1102 19:22:38.639420 Dram Type= 6, Freq= 0, CH_0, rank 1
1103 19:22:38.642445 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1104 19:22:38.642529 ==
1105 19:22:38.645972 Write leveling (Byte 0): 29 => 29
1106 19:22:38.649156 Write leveling (Byte 1): 29 => 29
1107 19:22:38.652586 DramcWriteLeveling(PI) end<-----
1108 19:22:38.652668
1109 19:22:38.652732 ==
1110 19:22:38.655973 Dram Type= 6, Freq= 0, CH_0, rank 1
1111 19:22:38.659343 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1112 19:22:38.659426 ==
1113 19:22:38.662633 [Gating] SW mode calibration
1114 19:22:38.668959 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1115 19:22:38.676079 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1116 19:22:38.679273 0 6 0 | B1->B0 | 3030 2f2f | 0 0 | (0 1) (0 0)
1117 19:22:38.682469 0 6 4 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
1118 19:22:38.688985 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1119 19:22:38.692808 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1120 19:22:38.695880 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1121 19:22:38.702642 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1122 19:22:38.705773 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1123 19:22:38.709240 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1124 19:22:38.715728 0 7 0 | B1->B0 | 2a2a 3030 | 0 0 | (1 1) (0 0)
1125 19:22:38.719070 0 7 4 | B1->B0 | 4040 4545 | 0 0 | (0 0) (0 0)
1126 19:22:38.722302 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1127 19:22:38.729180 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1128 19:22:38.732623 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1129 19:22:38.735890 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1130 19:22:38.742721 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1131 19:22:38.746212 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1132 19:22:38.749248 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1133 19:22:38.752687 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1134 19:22:38.759309 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1135 19:22:38.763089 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1136 19:22:38.766833 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1137 19:22:38.770378 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1138 19:22:38.777397 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1139 19:22:38.780874 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1140 19:22:38.783836 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1141 19:22:38.787462 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1142 19:22:38.794721 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1143 19:22:38.797997 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1144 19:22:38.801233 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1145 19:22:38.807908 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1146 19:22:38.811142 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1147 19:22:38.814604 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1148 19:22:38.821086 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1149 19:22:38.824484 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1150 19:22:38.827643 Total UI for P1: 0, mck2ui 16
1151 19:22:38.830944 best dqsien dly found for B0: ( 0, 10, 2)
1152 19:22:38.834385 Total UI for P1: 0, mck2ui 16
1153 19:22:38.837874 best dqsien dly found for B1: ( 0, 10, 2)
1154 19:22:38.841088 best DQS0 dly(MCK, UI, PI) = (0, 10, 2)
1155 19:22:38.844592 best DQS1 dly(MCK, UI, PI) = (0, 10, 2)
1156 19:22:38.844674
1157 19:22:38.847809 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 2)
1158 19:22:38.851003 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 2)
1159 19:22:38.854423 [Gating] SW calibration Done
1160 19:22:38.854505 ==
1161 19:22:38.857898 Dram Type= 6, Freq= 0, CH_0, rank 1
1162 19:22:38.861031 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1163 19:22:38.861114 ==
1164 19:22:38.864904 RX Vref Scan: 0
1165 19:22:38.864987
1166 19:22:38.867632 RX Vref 0 -> 0, step: 1
1167 19:22:38.867714
1168 19:22:38.867780 RX Delay -130 -> 252, step: 16
1169 19:22:38.874601 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1170 19:22:38.878387 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1171 19:22:38.881146 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1172 19:22:38.884778 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1173 19:22:38.887853 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1174 19:22:38.894668 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1175 19:22:38.897952 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1176 19:22:38.901331 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1177 19:22:38.904828 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1178 19:22:38.908016 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1179 19:22:38.914468 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1180 19:22:38.917992 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1181 19:22:38.921529 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1182 19:22:38.924469 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1183 19:22:38.927816 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1184 19:22:38.934653 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1185 19:22:38.934735 ==
1186 19:22:38.938009 Dram Type= 6, Freq= 0, CH_0, rank 1
1187 19:22:38.941409 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1188 19:22:38.941492 ==
1189 19:22:38.941557 DQS Delay:
1190 19:22:38.944947 DQS0 = 0, DQS1 = 0
1191 19:22:38.945028 DQM Delay:
1192 19:22:38.947880 DQM0 = 82, DQM1 = 74
1193 19:22:38.947962 DQ Delay:
1194 19:22:38.951122 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
1195 19:22:38.954622 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1196 19:22:38.957832 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
1197 19:22:38.961152 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1198 19:22:38.961234
1199 19:22:38.961298
1200 19:22:38.961360 ==
1201 19:22:38.964440 Dram Type= 6, Freq= 0, CH_0, rank 1
1202 19:22:38.968025 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1203 19:22:38.968108 ==
1204 19:22:38.970980
1205 19:22:38.971062
1206 19:22:38.971126 TX Vref Scan disable
1207 19:22:38.974588 == TX Byte 0 ==
1208 19:22:38.977808 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1209 19:22:38.981151 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1210 19:22:38.984781 == TX Byte 1 ==
1211 19:22:38.987670 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1212 19:22:38.990887 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1213 19:22:38.990970 ==
1214 19:22:38.994110 Dram Type= 6, Freq= 0, CH_0, rank 1
1215 19:22:39.000971 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1216 19:22:39.001053 ==
1217 19:22:39.012601 TX Vref=22, minBit 4, minWin=27, winSum=448
1218 19:22:39.016101 TX Vref=24, minBit 0, minWin=28, winSum=451
1219 19:22:39.019272 TX Vref=26, minBit 2, minWin=28, winSum=458
1220 19:22:39.022865 TX Vref=28, minBit 2, minWin=28, winSum=458
1221 19:22:39.026255 TX Vref=30, minBit 4, minWin=28, winSum=461
1222 19:22:39.032594 TX Vref=32, minBit 2, minWin=28, winSum=459
1223 19:22:39.036002 [TxChooseVref] Worse bit 4, Min win 28, Win sum 461, Final Vref 30
1224 19:22:39.036085
1225 19:22:39.039811 Final TX Range 1 Vref 30
1226 19:22:39.039894
1227 19:22:39.039959 ==
1228 19:22:39.042741 Dram Type= 6, Freq= 0, CH_0, rank 1
1229 19:22:39.046231 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1230 19:22:39.046313 ==
1231 19:22:39.046377
1232 19:22:39.049398
1233 19:22:39.049480 TX Vref Scan disable
1234 19:22:39.052579 == TX Byte 0 ==
1235 19:22:39.056207 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1236 19:22:39.059602 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1237 19:22:39.062888 == TX Byte 1 ==
1238 19:22:39.065964 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1239 19:22:39.069348 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1240 19:22:39.069431
1241 19:22:39.073200 [DATLAT]
1242 19:22:39.073284 Freq=800, CH0 RK1
1243 19:22:39.073380
1244 19:22:39.076216 DATLAT Default: 0x9
1245 19:22:39.076298 0, 0xFFFF, sum = 0
1246 19:22:39.079806 1, 0xFFFF, sum = 0
1247 19:22:39.079890 2, 0xFFFF, sum = 0
1248 19:22:39.082765 3, 0xFFFF, sum = 0
1249 19:22:39.082849 4, 0xFFFF, sum = 0
1250 19:22:39.086036 5, 0xFFFF, sum = 0
1251 19:22:39.086167 6, 0xFFFF, sum = 0
1252 19:22:39.089508 7, 0xFFFF, sum = 0
1253 19:22:39.089591 8, 0x0, sum = 1
1254 19:22:39.092594 9, 0x0, sum = 2
1255 19:22:39.092678 10, 0x0, sum = 3
1256 19:22:39.095886 11, 0x0, sum = 4
1257 19:22:39.095969 best_step = 9
1258 19:22:39.096035
1259 19:22:39.096095 ==
1260 19:22:39.099233 Dram Type= 6, Freq= 0, CH_0, rank 1
1261 19:22:39.105823 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1262 19:22:39.105932 ==
1263 19:22:39.106014 RX Vref Scan: 0
1264 19:22:39.106099
1265 19:22:39.109279 RX Vref 0 -> 0, step: 1
1266 19:22:39.109394
1267 19:22:39.112593 RX Delay -111 -> 252, step: 8
1268 19:22:39.116167 iDelay=217, Bit 0, Center 80 (-39 ~ 200) 240
1269 19:22:39.119695 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1270 19:22:39.125683 iDelay=217, Bit 2, Center 88 (-31 ~ 208) 240
1271 19:22:39.129185 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1272 19:22:39.132355 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1273 19:22:39.135731 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1274 19:22:39.138941 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1275 19:22:39.145538 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1276 19:22:39.149141 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1277 19:22:39.152305 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1278 19:22:39.155830 iDelay=217, Bit 10, Center 72 (-47 ~ 192) 240
1279 19:22:39.159190 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1280 19:22:39.165758 iDelay=217, Bit 12, Center 80 (-31 ~ 192) 224
1281 19:22:39.168931 iDelay=217, Bit 13, Center 80 (-39 ~ 200) 240
1282 19:22:39.172512 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1283 19:22:39.175894 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1284 19:22:39.175977 ==
1285 19:22:39.178916 Dram Type= 6, Freq= 0, CH_0, rank 1
1286 19:22:39.185889 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1287 19:22:39.185999 ==
1288 19:22:39.186114 DQS Delay:
1289 19:22:39.186176 DQS0 = 0, DQS1 = 0
1290 19:22:39.189098 DQM Delay:
1291 19:22:39.189179 DQM0 = 86, DQM1 = 73
1292 19:22:39.191862 DQ Delay:
1293 19:22:39.195848 DQ0 =80, DQ1 =88, DQ2 =88, DQ3 =80
1294 19:22:39.198984 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1295 19:22:39.202172 DQ8 =64, DQ9 =60, DQ10 =72, DQ11 =64
1296 19:22:39.205317 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =84
1297 19:22:39.205399
1298 19:22:39.205463
1299 19:22:39.212175 [DQSOSCAuto] RK1, (LSB)MR18= 0x4949, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
1300 19:22:39.215297 CH0 RK1: MR19=606, MR18=4949
1301 19:22:39.221947 CH0_RK1: MR19=0x606, MR18=0x4949, DQSOSC=391, MR23=63, INC=96, DEC=64
1302 19:22:39.225267 [RxdqsGatingPostProcess] freq 800
1303 19:22:39.228567 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1304 19:22:39.232170 Pre-setting of DQS Precalculation
1305 19:22:39.238394 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1306 19:22:39.238502 ==
1307 19:22:39.241683 Dram Type= 6, Freq= 0, CH_1, rank 0
1308 19:22:39.245192 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1309 19:22:39.245275 ==
1310 19:22:39.251602 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1311 19:22:39.254919 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1312 19:22:39.265397 [CA 0] Center 37 (6~68) winsize 63
1313 19:22:39.269058 [CA 1] Center 37 (6~68) winsize 63
1314 19:22:39.272042 [CA 2] Center 34 (4~65) winsize 62
1315 19:22:39.275508 [CA 3] Center 34 (4~65) winsize 62
1316 19:22:39.278446 [CA 4] Center 33 (3~64) winsize 62
1317 19:22:39.282029 [CA 5] Center 33 (3~64) winsize 62
1318 19:22:39.282144
1319 19:22:39.285482 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1320 19:22:39.285564
1321 19:22:39.288895 [CATrainingPosCal] consider 1 rank data
1322 19:22:39.292027 u2DelayCellTimex100 = 270/100 ps
1323 19:22:39.295157 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1324 19:22:39.298501 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1325 19:22:39.305111 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1326 19:22:39.308846 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1327 19:22:39.311941 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1328 19:22:39.315263 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1329 19:22:39.315344
1330 19:22:39.318822 CA PerBit enable=1, Macro0, CA PI delay=33
1331 19:22:39.318911
1332 19:22:39.321726 [CBTSetCACLKResult] CA Dly = 33
1333 19:22:39.321828 CS Dly: 5 (0~36)
1334 19:22:39.325433 ==
1335 19:22:39.325515 Dram Type= 6, Freq= 0, CH_1, rank 1
1336 19:22:39.332076 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1337 19:22:39.332179 ==
1338 19:22:39.334993 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1339 19:22:39.341973 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1340 19:22:39.351256 [CA 0] Center 37 (6~68) winsize 63
1341 19:22:39.354401 [CA 1] Center 37 (6~68) winsize 63
1342 19:22:39.357822 [CA 2] Center 34 (4~65) winsize 62
1343 19:22:39.360919 [CA 3] Center 34 (4~65) winsize 62
1344 19:22:39.364483 [CA 4] Center 33 (3~64) winsize 62
1345 19:22:39.367754 [CA 5] Center 33 (3~64) winsize 62
1346 19:22:39.367824
1347 19:22:39.371137 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1348 19:22:39.371222
1349 19:22:39.374657 [CATrainingPosCal] consider 2 rank data
1350 19:22:39.377990 u2DelayCellTimex100 = 270/100 ps
1351 19:22:39.381012 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1352 19:22:39.384240 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1353 19:22:39.390888 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1354 19:22:39.394402 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1355 19:22:39.397837 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1356 19:22:39.400954 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1357 19:22:39.401048
1358 19:22:39.404620 CA PerBit enable=1, Macro0, CA PI delay=33
1359 19:22:39.404716
1360 19:22:39.407552 [CBTSetCACLKResult] CA Dly = 33
1361 19:22:39.407646 CS Dly: 5 (0~37)
1362 19:22:39.407739
1363 19:22:39.411328 ----->DramcWriteLeveling(PI) begin...
1364 19:22:39.414222 ==
1365 19:22:39.417662 Dram Type= 6, Freq= 0, CH_1, rank 0
1366 19:22:39.421390 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1367 19:22:39.421505 ==
1368 19:22:39.424967 Write leveling (Byte 0): 26 => 26
1369 19:22:39.428386 Write leveling (Byte 1): 25 => 25
1370 19:22:39.428500 DramcWriteLeveling(PI) end<-----
1371 19:22:39.428603
1372 19:22:39.432042 ==
1373 19:22:39.432116 Dram Type= 6, Freq= 0, CH_1, rank 0
1374 19:22:39.436399 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1375 19:22:39.439641 ==
1376 19:22:39.439713 [Gating] SW mode calibration
1377 19:22:39.447034 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1378 19:22:39.454354 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1379 19:22:39.458206 0 6 0 | B1->B0 | 3030 2424 | 0 0 | (1 1) (0 0)
1380 19:22:39.461709 0 6 4 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1381 19:22:39.464695 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1382 19:22:39.471277 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1383 19:22:39.474555 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1384 19:22:39.478056 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1385 19:22:39.484539 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1386 19:22:39.487892 0 6 28 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
1387 19:22:39.491101 0 7 0 | B1->B0 | 2d2d 4444 | 0 0 | (0 0) (1 1)
1388 19:22:39.497824 0 7 4 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
1389 19:22:39.501233 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1390 19:22:39.504426 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1391 19:22:39.511103 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1392 19:22:39.514490 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1393 19:22:39.518086 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1394 19:22:39.524934 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1395 19:22:39.527762 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1396 19:22:39.531275 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1397 19:22:39.534425 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1398 19:22:39.540973 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1399 19:22:39.544841 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1400 19:22:39.548025 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1401 19:22:39.554743 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1402 19:22:39.557815 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1403 19:22:39.560857 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1404 19:22:39.567993 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1405 19:22:39.571236 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1406 19:22:39.574695 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1407 19:22:39.581356 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1408 19:22:39.584498 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1409 19:22:39.587977 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1410 19:22:39.594942 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1411 19:22:39.597978 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1412 19:22:39.601733 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1413 19:22:39.604435 Total UI for P1: 0, mck2ui 16
1414 19:22:39.607697 best dqsien dly found for B0: ( 0, 10, 0)
1415 19:22:39.611260 Total UI for P1: 0, mck2ui 16
1416 19:22:39.614503 best dqsien dly found for B1: ( 0, 10, 0)
1417 19:22:39.618479 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
1418 19:22:39.620886 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1419 19:22:39.620968
1420 19:22:39.624452 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
1421 19:22:39.631255 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1422 19:22:39.631337 [Gating] SW calibration Done
1423 19:22:39.634430 ==
1424 19:22:39.634513 Dram Type= 6, Freq= 0, CH_1, rank 0
1425 19:22:39.641310 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1426 19:22:39.641393 ==
1427 19:22:39.641459 RX Vref Scan: 0
1428 19:22:39.641521
1429 19:22:39.644480 RX Vref 0 -> 0, step: 1
1430 19:22:39.644562
1431 19:22:39.647553 RX Delay -130 -> 252, step: 16
1432 19:22:39.650917 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1433 19:22:39.653850 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1434 19:22:39.660580 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1435 19:22:39.663962 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1436 19:22:39.667619 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1437 19:22:39.670814 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1438 19:22:39.674185 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1439 19:22:39.677361 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1440 19:22:39.684433 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1441 19:22:39.687331 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1442 19:22:39.691016 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1443 19:22:39.693864 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1444 19:22:39.700687 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1445 19:22:39.704072 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1446 19:22:39.706959 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1447 19:22:39.710524 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1448 19:22:39.710607 ==
1449 19:22:39.714125 Dram Type= 6, Freq= 0, CH_1, rank 0
1450 19:22:39.717563 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1451 19:22:39.720382 ==
1452 19:22:39.720465 DQS Delay:
1453 19:22:39.720530 DQS0 = 0, DQS1 = 0
1454 19:22:39.723698 DQM Delay:
1455 19:22:39.723780 DQM0 = 81, DQM1 = 74
1456 19:22:39.726912 DQ Delay:
1457 19:22:39.730301 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1458 19:22:39.730383 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1459 19:22:39.734276 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =69
1460 19:22:39.737309 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =85
1461 19:22:39.740676
1462 19:22:39.740758
1463 19:22:39.740823 ==
1464 19:22:39.743581 Dram Type= 6, Freq= 0, CH_1, rank 0
1465 19:22:39.747468 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1466 19:22:39.747551 ==
1467 19:22:39.747616
1468 19:22:39.747677
1469 19:22:39.750733 TX Vref Scan disable
1470 19:22:39.750816 == TX Byte 0 ==
1471 19:22:39.756827 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1472 19:22:39.760369 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1473 19:22:39.760452 == TX Byte 1 ==
1474 19:22:39.767374 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1475 19:22:39.770301 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1476 19:22:39.770398 ==
1477 19:22:39.773766 Dram Type= 6, Freq= 0, CH_1, rank 0
1478 19:22:39.776897 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1479 19:22:39.776980 ==
1480 19:22:39.790887 TX Vref=22, minBit 2, minWin=27, winSum=445
1481 19:22:39.793877 TX Vref=24, minBit 3, minWin=27, winSum=449
1482 19:22:39.796955 TX Vref=26, minBit 3, minWin=27, winSum=451
1483 19:22:39.800542 TX Vref=28, minBit 0, minWin=28, winSum=457
1484 19:22:39.803680 TX Vref=30, minBit 0, minWin=28, winSum=459
1485 19:22:39.807134 TX Vref=32, minBit 0, minWin=28, winSum=459
1486 19:22:39.813835 [TxChooseVref] Worse bit 0, Min win 28, Win sum 459, Final Vref 30
1487 19:22:39.813918
1488 19:22:39.817022 Final TX Range 1 Vref 30
1489 19:22:39.817104
1490 19:22:39.817169 ==
1491 19:22:39.820383 Dram Type= 6, Freq= 0, CH_1, rank 0
1492 19:22:39.823817 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1493 19:22:39.823900 ==
1494 19:22:39.826857
1495 19:22:39.826938
1496 19:22:39.827022 TX Vref Scan disable
1497 19:22:39.830494 == TX Byte 0 ==
1498 19:22:39.833653 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1499 19:22:39.837336 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1500 19:22:39.840398 == TX Byte 1 ==
1501 19:22:39.843432 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1502 19:22:39.850390 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1503 19:22:39.850473
1504 19:22:39.850539 [DATLAT]
1505 19:22:39.850625 Freq=800, CH1 RK0
1506 19:22:39.850715
1507 19:22:39.853491 DATLAT Default: 0xa
1508 19:22:39.853574 0, 0xFFFF, sum = 0
1509 19:22:39.856980 1, 0xFFFF, sum = 0
1510 19:22:39.857064 2, 0xFFFF, sum = 0
1511 19:22:39.860323 3, 0xFFFF, sum = 0
1512 19:22:39.863441 4, 0xFFFF, sum = 0
1513 19:22:39.863525 5, 0xFFFF, sum = 0
1514 19:22:39.867086 6, 0xFFFF, sum = 0
1515 19:22:39.867170 7, 0xFFFF, sum = 0
1516 19:22:39.867237 8, 0x0, sum = 1
1517 19:22:39.870291 9, 0x0, sum = 2
1518 19:22:39.870375 10, 0x0, sum = 3
1519 19:22:39.873411 11, 0x0, sum = 4
1520 19:22:39.873494 best_step = 9
1521 19:22:39.873560
1522 19:22:39.873620 ==
1523 19:22:39.876806 Dram Type= 6, Freq= 0, CH_1, rank 0
1524 19:22:39.883806 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1525 19:22:39.883891 ==
1526 19:22:39.883956 RX Vref Scan: 1
1527 19:22:39.884016
1528 19:22:39.886952 Set Vref Range= 32 -> 127
1529 19:22:39.887035
1530 19:22:39.890558 RX Vref 32 -> 127, step: 1
1531 19:22:39.890656
1532 19:22:39.890723 RX Delay -111 -> 252, step: 8
1533 19:22:39.893731
1534 19:22:39.893813 Set Vref, RX VrefLevel [Byte0]: 32
1535 19:22:39.896966 [Byte1]: 32
1536 19:22:39.901414
1537 19:22:39.901496 Set Vref, RX VrefLevel [Byte0]: 33
1538 19:22:39.904446 [Byte1]: 33
1539 19:22:39.909311
1540 19:22:39.909393 Set Vref, RX VrefLevel [Byte0]: 34
1541 19:22:39.912260 [Byte1]: 34
1542 19:22:39.916477
1543 19:22:39.916559 Set Vref, RX VrefLevel [Byte0]: 35
1544 19:22:39.920369 [Byte1]: 35
1545 19:22:39.924416
1546 19:22:39.924498 Set Vref, RX VrefLevel [Byte0]: 36
1547 19:22:39.927374 [Byte1]: 36
1548 19:22:39.932492
1549 19:22:39.932574 Set Vref, RX VrefLevel [Byte0]: 37
1550 19:22:39.935542 [Byte1]: 37
1551 19:22:39.939479
1552 19:22:39.939563 Set Vref, RX VrefLevel [Byte0]: 38
1553 19:22:39.942764 [Byte1]: 38
1554 19:22:39.947047
1555 19:22:39.947130 Set Vref, RX VrefLevel [Byte0]: 39
1556 19:22:39.950363 [Byte1]: 39
1557 19:22:39.954632
1558 19:22:39.954714 Set Vref, RX VrefLevel [Byte0]: 40
1559 19:22:39.958225 [Byte1]: 40
1560 19:22:39.962524
1561 19:22:39.962606 Set Vref, RX VrefLevel [Byte0]: 41
1562 19:22:39.965968 [Byte1]: 41
1563 19:22:39.970396
1564 19:22:39.970478 Set Vref, RX VrefLevel [Byte0]: 42
1565 19:22:39.973275 [Byte1]: 42
1566 19:22:39.977874
1567 19:22:39.977956 Set Vref, RX VrefLevel [Byte0]: 43
1568 19:22:39.981201 [Byte1]: 43
1569 19:22:39.985179
1570 19:22:39.985262 Set Vref, RX VrefLevel [Byte0]: 44
1571 19:22:39.988585 [Byte1]: 44
1572 19:22:39.993144
1573 19:22:39.993230 Set Vref, RX VrefLevel [Byte0]: 45
1574 19:22:39.996169 [Byte1]: 45
1575 19:22:40.000833
1576 19:22:40.000915 Set Vref, RX VrefLevel [Byte0]: 46
1577 19:22:40.004011 [Byte1]: 46
1578 19:22:40.009248
1579 19:22:40.009331 Set Vref, RX VrefLevel [Byte0]: 47
1580 19:22:40.011923 [Byte1]: 47
1581 19:22:40.015833
1582 19:22:40.015915 Set Vref, RX VrefLevel [Byte0]: 48
1583 19:22:40.019103 [Byte1]: 48
1584 19:22:40.023511
1585 19:22:40.023594 Set Vref, RX VrefLevel [Byte0]: 49
1586 19:22:40.027256 [Byte1]: 49
1587 19:22:40.031783
1588 19:22:40.031865 Set Vref, RX VrefLevel [Byte0]: 50
1589 19:22:40.034568 [Byte1]: 50
1590 19:22:40.038894
1591 19:22:40.038976 Set Vref, RX VrefLevel [Byte0]: 51
1592 19:22:40.042443 [Byte1]: 51
1593 19:22:40.046814
1594 19:22:40.046896 Set Vref, RX VrefLevel [Byte0]: 52
1595 19:22:40.049883 [Byte1]: 52
1596 19:22:40.054166
1597 19:22:40.054248 Set Vref, RX VrefLevel [Byte0]: 53
1598 19:22:40.057577 [Byte1]: 53
1599 19:22:40.061739
1600 19:22:40.061821 Set Vref, RX VrefLevel [Byte0]: 54
1601 19:22:40.065029 [Byte1]: 54
1602 19:22:40.069443
1603 19:22:40.069524 Set Vref, RX VrefLevel [Byte0]: 55
1604 19:22:40.072862 [Byte1]: 55
1605 19:22:40.077091
1606 19:22:40.077173 Set Vref, RX VrefLevel [Byte0]: 56
1607 19:22:40.080647 [Byte1]: 56
1608 19:22:40.085105
1609 19:22:40.085187 Set Vref, RX VrefLevel [Byte0]: 57
1610 19:22:40.088473 [Byte1]: 57
1611 19:22:40.092201
1612 19:22:40.092283 Set Vref, RX VrefLevel [Byte0]: 58
1613 19:22:40.095982 [Byte1]: 58
1614 19:22:40.100026
1615 19:22:40.100108 Set Vref, RX VrefLevel [Byte0]: 59
1616 19:22:40.103187 [Byte1]: 59
1617 19:22:40.107530
1618 19:22:40.107612 Set Vref, RX VrefLevel [Byte0]: 60
1619 19:22:40.111158 [Byte1]: 60
1620 19:22:40.115225
1621 19:22:40.115307 Set Vref, RX VrefLevel [Byte0]: 61
1622 19:22:40.118817 [Byte1]: 61
1623 19:22:40.123118
1624 19:22:40.123200 Set Vref, RX VrefLevel [Byte0]: 62
1625 19:22:40.126312 [Byte1]: 62
1626 19:22:40.130659
1627 19:22:40.130757 Set Vref, RX VrefLevel [Byte0]: 63
1628 19:22:40.134066 [Byte1]: 63
1629 19:22:40.138168
1630 19:22:40.138250 Set Vref, RX VrefLevel [Byte0]: 64
1631 19:22:40.141868 [Byte1]: 64
1632 19:22:40.145864
1633 19:22:40.145945 Set Vref, RX VrefLevel [Byte0]: 65
1634 19:22:40.152414 [Byte1]: 65
1635 19:22:40.152497
1636 19:22:40.155915 Set Vref, RX VrefLevel [Byte0]: 66
1637 19:22:40.158953 [Byte1]: 66
1638 19:22:40.159039
1639 19:22:40.162289 Set Vref, RX VrefLevel [Byte0]: 67
1640 19:22:40.165908 [Byte1]: 67
1641 19:22:40.165991
1642 19:22:40.168993 Set Vref, RX VrefLevel [Byte0]: 68
1643 19:22:40.172337 [Byte1]: 68
1644 19:22:40.176415
1645 19:22:40.176497 Set Vref, RX VrefLevel [Byte0]: 69
1646 19:22:40.180218 [Byte1]: 69
1647 19:22:40.184264
1648 19:22:40.184346 Set Vref, RX VrefLevel [Byte0]: 70
1649 19:22:40.187629 [Byte1]: 70
1650 19:22:40.192257
1651 19:22:40.192339 Set Vref, RX VrefLevel [Byte0]: 71
1652 19:22:40.195580 [Byte1]: 71
1653 19:22:40.199796
1654 19:22:40.199878 Set Vref, RX VrefLevel [Byte0]: 72
1655 19:22:40.202945 [Byte1]: 72
1656 19:22:40.207351
1657 19:22:40.207433 Set Vref, RX VrefLevel [Byte0]: 73
1658 19:22:40.210758 [Byte1]: 73
1659 19:22:40.214976
1660 19:22:40.215058 Set Vref, RX VrefLevel [Byte0]: 74
1661 19:22:40.218339 [Byte1]: 74
1662 19:22:40.222227
1663 19:22:40.222309 Set Vref, RX VrefLevel [Byte0]: 75
1664 19:22:40.226132 [Byte1]: 75
1665 19:22:40.229954
1666 19:22:40.230042 Set Vref, RX VrefLevel [Byte0]: 76
1667 19:22:40.233601 [Byte1]: 76
1668 19:22:40.237931
1669 19:22:40.238012 Final RX Vref Byte 0 = 60 to rank0
1670 19:22:40.241187 Final RX Vref Byte 1 = 56 to rank0
1671 19:22:40.244162 Final RX Vref Byte 0 = 60 to rank1
1672 19:22:40.247747 Final RX Vref Byte 1 = 56 to rank1==
1673 19:22:40.251251 Dram Type= 6, Freq= 0, CH_1, rank 0
1674 19:22:40.254336 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1675 19:22:40.257933 ==
1676 19:22:40.258016 DQS Delay:
1677 19:22:40.258122 DQS0 = 0, DQS1 = 0
1678 19:22:40.261307 DQM Delay:
1679 19:22:40.261389 DQM0 = 81, DQM1 = 75
1680 19:22:40.264281 DQ Delay:
1681 19:22:40.267689 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =76
1682 19:22:40.267771 DQ4 =80, DQ5 =92, DQ6 =88, DQ7 =76
1683 19:22:40.270965 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =68
1684 19:22:40.277769 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =84
1685 19:22:40.277850
1686 19:22:40.277914
1687 19:22:40.284131 [DQSOSCAuto] RK0, (LSB)MR18= 0x5050, (MSB)MR19= 0x606, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
1688 19:22:40.287512 CH1 RK0: MR19=606, MR18=5050
1689 19:22:40.294086 CH1_RK0: MR19=0x606, MR18=0x5050, DQSOSC=389, MR23=63, INC=97, DEC=65
1690 19:22:40.294168
1691 19:22:40.297585 ----->DramcWriteLeveling(PI) begin...
1692 19:22:40.297668 ==
1693 19:22:40.301018 Dram Type= 6, Freq= 0, CH_1, rank 1
1694 19:22:40.304331 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1695 19:22:40.304423 ==
1696 19:22:40.307675 Write leveling (Byte 0): 23 => 23
1697 19:22:40.310882 Write leveling (Byte 1): 23 => 23
1698 19:22:40.314048 DramcWriteLeveling(PI) end<-----
1699 19:22:40.314143
1700 19:22:40.314208 ==
1701 19:22:40.317436 Dram Type= 6, Freq= 0, CH_1, rank 1
1702 19:22:40.320923 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1703 19:22:40.321008 ==
1704 19:22:40.324294 [Gating] SW mode calibration
1705 19:22:40.330966 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1706 19:22:40.337542 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1707 19:22:40.341557 0 6 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
1708 19:22:40.344235 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1709 19:22:40.350707 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1710 19:22:40.353866 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1711 19:22:40.357442 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1712 19:22:40.364071 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1713 19:22:40.367554 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1714 19:22:40.370800 0 6 28 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
1715 19:22:40.377359 0 7 0 | B1->B0 | 3939 4646 | 1 0 | (1 1) (0 0)
1716 19:22:40.380690 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1717 19:22:40.384093 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1718 19:22:40.390401 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1719 19:22:40.393812 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1720 19:22:40.397161 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1721 19:22:40.403936 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1722 19:22:40.407285 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1723 19:22:40.410537 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1724 19:22:40.417265 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1725 19:22:40.420435 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1726 19:22:40.423761 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1727 19:22:40.430387 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1728 19:22:40.433945 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1729 19:22:40.437048 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1730 19:22:40.443488 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1731 19:22:40.447263 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1732 19:22:40.450427 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1733 19:22:40.453527 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1734 19:22:40.460225 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1735 19:22:40.463728 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1736 19:22:40.466998 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1737 19:22:40.473986 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1738 19:22:40.476936 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1739 19:22:40.480792 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1740 19:22:40.483557 Total UI for P1: 0, mck2ui 16
1741 19:22:40.486881 best dqsien dly found for B0: ( 0, 9, 28)
1742 19:22:40.490390 Total UI for P1: 0, mck2ui 16
1743 19:22:40.493701 best dqsien dly found for B1: ( 0, 9, 30)
1744 19:22:40.496819 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1745 19:22:40.500290 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1746 19:22:40.500378
1747 19:22:40.507081 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1748 19:22:40.510406 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1749 19:22:40.513425 [Gating] SW calibration Done
1750 19:22:40.513508 ==
1751 19:22:40.517004 Dram Type= 6, Freq= 0, CH_1, rank 1
1752 19:22:40.520579 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1753 19:22:40.520664 ==
1754 19:22:40.520747 RX Vref Scan: 0
1755 19:22:40.523519
1756 19:22:40.523603 RX Vref 0 -> 0, step: 1
1757 19:22:40.523689
1758 19:22:40.527061 RX Delay -130 -> 252, step: 16
1759 19:22:40.530267 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1760 19:22:40.533378 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1761 19:22:40.540551 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1762 19:22:40.543591 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1763 19:22:40.547100 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1764 19:22:40.550387 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1765 19:22:40.553762 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1766 19:22:40.560146 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1767 19:22:40.563766 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1768 19:22:40.566987 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1769 19:22:40.570469 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1770 19:22:40.573477 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1771 19:22:40.579988 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1772 19:22:40.583617 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1773 19:22:40.586574 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1774 19:22:40.590051 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1775 19:22:40.590148 ==
1776 19:22:40.593477 Dram Type= 6, Freq= 0, CH_1, rank 1
1777 19:22:40.600090 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1778 19:22:40.600165 ==
1779 19:22:40.600227 DQS Delay:
1780 19:22:40.603787 DQS0 = 0, DQS1 = 0
1781 19:22:40.603884 DQM Delay:
1782 19:22:40.603979 DQM0 = 85, DQM1 = 74
1783 19:22:40.606750 DQ Delay:
1784 19:22:40.610159 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1785 19:22:40.613131 DQ4 =85, DQ5 =101, DQ6 =85, DQ7 =85
1786 19:22:40.616636 DQ8 =53, DQ9 =69, DQ10 =69, DQ11 =69
1787 19:22:40.619554 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =85
1788 19:22:40.619635
1789 19:22:40.619700
1790 19:22:40.619758 ==
1791 19:22:40.622972 Dram Type= 6, Freq= 0, CH_1, rank 1
1792 19:22:40.626558 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1793 19:22:40.626665 ==
1794 19:22:40.626756
1795 19:22:40.626842
1796 19:22:40.629686 TX Vref Scan disable
1797 19:22:40.629780 == TX Byte 0 ==
1798 19:22:40.636299 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1799 19:22:40.639859 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1800 19:22:40.642924 == TX Byte 1 ==
1801 19:22:40.646701 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1802 19:22:40.649777 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1803 19:22:40.649873 ==
1804 19:22:40.652931 Dram Type= 6, Freq= 0, CH_1, rank 1
1805 19:22:40.656470 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1806 19:22:40.656542 ==
1807 19:22:40.670388 TX Vref=22, minBit 0, minWin=28, winSum=451
1808 19:22:40.673842 TX Vref=24, minBit 8, minWin=27, winSum=453
1809 19:22:40.677206 TX Vref=26, minBit 6, minWin=28, winSum=461
1810 19:22:40.681089 TX Vref=28, minBit 0, minWin=28, winSum=460
1811 19:22:40.683750 TX Vref=30, minBit 8, minWin=28, winSum=460
1812 19:22:40.687632 TX Vref=32, minBit 9, minWin=27, winSum=456
1813 19:22:40.693845 [TxChooseVref] Worse bit 6, Min win 28, Win sum 461, Final Vref 26
1814 19:22:40.693927
1815 19:22:40.697553 Final TX Range 1 Vref 26
1816 19:22:40.697634
1817 19:22:40.697698 ==
1818 19:22:40.701019 Dram Type= 6, Freq= 0, CH_1, rank 1
1819 19:22:40.704174 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1820 19:22:40.704256 ==
1821 19:22:40.704321
1822 19:22:40.704380
1823 19:22:40.707539 TX Vref Scan disable
1824 19:22:40.710557 == TX Byte 0 ==
1825 19:22:40.713749 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1826 19:22:40.717016 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1827 19:22:40.720482 == TX Byte 1 ==
1828 19:22:40.723831 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1829 19:22:40.727102 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1830 19:22:40.730181
1831 19:22:40.730261 [DATLAT]
1832 19:22:40.730325 Freq=800, CH1 RK1
1833 19:22:40.730385
1834 19:22:40.733607 DATLAT Default: 0x9
1835 19:22:40.733704 0, 0xFFFF, sum = 0
1836 19:22:40.736750 1, 0xFFFF, sum = 0
1837 19:22:40.736832 2, 0xFFFF, sum = 0
1838 19:22:40.740505 3, 0xFFFF, sum = 0
1839 19:22:40.740625 4, 0xFFFF, sum = 0
1840 19:22:40.743730 5, 0xFFFF, sum = 0
1841 19:22:40.747323 6, 0xFFFF, sum = 0
1842 19:22:40.747406 7, 0xFFFF, sum = 0
1843 19:22:40.750319 8, 0x0, sum = 1
1844 19:22:40.750401 9, 0x0, sum = 2
1845 19:22:40.750467 10, 0x0, sum = 3
1846 19:22:40.753587 11, 0x0, sum = 4
1847 19:22:40.753669 best_step = 9
1848 19:22:40.753732
1849 19:22:40.753791 ==
1850 19:22:40.756717 Dram Type= 6, Freq= 0, CH_1, rank 1
1851 19:22:40.763570 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1852 19:22:40.763651 ==
1853 19:22:40.763715 RX Vref Scan: 0
1854 19:22:40.763787
1855 19:22:40.766711 RX Vref 0 -> 0, step: 1
1856 19:22:40.766792
1857 19:22:40.770296 RX Delay -111 -> 252, step: 8
1858 19:22:40.773339 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
1859 19:22:40.776730 iDelay=209, Bit 1, Center 76 (-39 ~ 192) 232
1860 19:22:40.783501 iDelay=209, Bit 2, Center 72 (-47 ~ 192) 240
1861 19:22:40.786979 iDelay=209, Bit 3, Center 80 (-39 ~ 200) 240
1862 19:22:40.790276 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
1863 19:22:40.793444 iDelay=209, Bit 5, Center 92 (-23 ~ 208) 232
1864 19:22:40.796559 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1865 19:22:40.803489 iDelay=209, Bit 7, Center 80 (-39 ~ 200) 240
1866 19:22:40.806593 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1867 19:22:40.809559 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
1868 19:22:40.813217 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1869 19:22:40.816522 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1870 19:22:40.823306 iDelay=209, Bit 12, Center 84 (-39 ~ 208) 248
1871 19:22:40.826598 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1872 19:22:40.830020 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1873 19:22:40.833151 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1874 19:22:40.833232 ==
1875 19:22:40.836555 Dram Type= 6, Freq= 0, CH_1, rank 1
1876 19:22:40.843140 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1877 19:22:40.843221 ==
1878 19:22:40.843285 DQS Delay:
1879 19:22:40.846521 DQS0 = 0, DQS1 = 0
1880 19:22:40.846602 DQM Delay:
1881 19:22:40.846666 DQM0 = 82, DQM1 = 74
1882 19:22:40.850447 DQ Delay:
1883 19:22:40.853051 DQ0 =84, DQ1 =76, DQ2 =72, DQ3 =80
1884 19:22:40.856313 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =80
1885 19:22:40.859709 DQ8 =60, DQ9 =64, DQ10 =72, DQ11 =64
1886 19:22:40.863718 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =84
1887 19:22:40.863799
1888 19:22:40.863863
1889 19:22:40.869686 [DQSOSCAuto] RK1, (LSB)MR18= 0x3636, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
1890 19:22:40.873625 CH1 RK1: MR19=606, MR18=3636
1891 19:22:40.879821 CH1_RK1: MR19=0x606, MR18=0x3636, DQSOSC=396, MR23=63, INC=94, DEC=62
1892 19:22:40.883107 [RxdqsGatingPostProcess] freq 800
1893 19:22:40.886723 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1894 19:22:40.889988 Pre-setting of DQS Precalculation
1895 19:22:40.896695 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1896 19:22:40.902879 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1897 19:22:40.909940 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1898 19:22:40.910044
1899 19:22:40.910124
1900 19:22:40.912995 [Calibration Summary] 1600 Mbps
1901 19:22:40.913075 CH 0, Rank 0
1902 19:22:40.916151 SW Impedance : PASS
1903 19:22:40.919578 DUTY Scan : NO K
1904 19:22:40.919658 ZQ Calibration : PASS
1905 19:22:40.922826 Jitter Meter : NO K
1906 19:22:40.926352 CBT Training : PASS
1907 19:22:40.926432 Write leveling : PASS
1908 19:22:40.929632 RX DQS gating : PASS
1909 19:22:40.929714 RX DQ/DQS(RDDQC) : PASS
1910 19:22:40.932980 TX DQ/DQS : PASS
1911 19:22:40.935987 RX DATLAT : PASS
1912 19:22:40.936086 RX DQ/DQS(Engine): PASS
1913 19:22:40.939384 TX OE : NO K
1914 19:22:40.939480 All Pass.
1915 19:22:40.939569
1916 19:22:40.942902 CH 0, Rank 1
1917 19:22:40.942973 SW Impedance : PASS
1918 19:22:40.946291 DUTY Scan : NO K
1919 19:22:40.949689 ZQ Calibration : PASS
1920 19:22:40.949786 Jitter Meter : NO K
1921 19:22:40.953195 CBT Training : PASS
1922 19:22:40.956208 Write leveling : PASS
1923 19:22:40.956290 RX DQS gating : PASS
1924 19:22:40.959570 RX DQ/DQS(RDDQC) : PASS
1925 19:22:40.963045 TX DQ/DQS : PASS
1926 19:22:40.963126 RX DATLAT : PASS
1927 19:22:40.966016 RX DQ/DQS(Engine): PASS
1928 19:22:40.969736 TX OE : NO K
1929 19:22:40.969817 All Pass.
1930 19:22:40.969880
1931 19:22:40.969941 CH 1, Rank 0
1932 19:22:40.972621 SW Impedance : PASS
1933 19:22:40.976260 DUTY Scan : NO K
1934 19:22:40.976341 ZQ Calibration : PASS
1935 19:22:40.979442 Jitter Meter : NO K
1936 19:22:40.979527 CBT Training : PASS
1937 19:22:40.982975 Write leveling : PASS
1938 19:22:40.986293 RX DQS gating : PASS
1939 19:22:40.986367 RX DQ/DQS(RDDQC) : PASS
1940 19:22:40.989340 TX DQ/DQS : PASS
1941 19:22:40.992919 RX DATLAT : PASS
1942 19:22:40.993017 RX DQ/DQS(Engine): PASS
1943 19:22:40.996076 TX OE : NO K
1944 19:22:40.996149 All Pass.
1945 19:22:40.996209
1946 19:22:40.999856 CH 1, Rank 1
1947 19:22:40.999962 SW Impedance : PASS
1948 19:22:41.002903 DUTY Scan : NO K
1949 19:22:41.005941 ZQ Calibration : PASS
1950 19:22:41.006043 Jitter Meter : NO K
1951 19:22:41.009174 CBT Training : PASS
1952 19:22:41.012463 Write leveling : PASS
1953 19:22:41.012563 RX DQS gating : PASS
1954 19:22:41.016000 RX DQ/DQS(RDDQC) : PASS
1955 19:22:41.019170 TX DQ/DQS : PASS
1956 19:22:41.019243 RX DATLAT : PASS
1957 19:22:41.022534 RX DQ/DQS(Engine): PASS
1958 19:22:41.026313 TX OE : NO K
1959 19:22:41.026405 All Pass.
1960 19:22:41.026482
1961 19:22:41.026543 DramC Write-DBI off
1962 19:22:41.029281 PER_BANK_REFRESH: Hybrid Mode
1963 19:22:41.032773 TX_TRACKING: ON
1964 19:22:41.035840 [GetDramInforAfterCalByMRR] Vendor 6.
1965 19:22:41.039245 [GetDramInforAfterCalByMRR] Revision 606.
1966 19:22:41.043048 [GetDramInforAfterCalByMRR] Revision 2 0.
1967 19:22:41.043129 MR0 0x3939
1968 19:22:41.045782 MR8 0x1111
1969 19:22:41.049674 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
1970 19:22:41.049786
1971 19:22:41.049878 MR0 0x3939
1972 19:22:41.049973 MR8 0x1111
1973 19:22:41.052580 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
1974 19:22:41.052677
1975 19:22:41.062661 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
1976 19:22:41.065787 [FAST_K] Save calibration result to emmc
1977 19:22:41.069267 [FAST_K] Save calibration result to emmc
1978 19:22:41.073212 dram_init: config_dvfs: 1
1979 19:22:41.076211 dramc_set_vcore_voltage set vcore to 662500
1980 19:22:41.079256 Read voltage for 1200, 2
1981 19:22:41.079341 Vio18 = 0
1982 19:22:41.079433 Vcore = 662500
1983 19:22:41.082477 Vdram = 0
1984 19:22:41.082549 Vddq = 0
1985 19:22:41.082610 Vmddr = 0
1986 19:22:41.089128 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
1987 19:22:41.092807 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
1988 19:22:41.095963 MEM_TYPE=3, freq_sel=15
1989 19:22:41.099421 sv_algorithm_assistance_LP4_1600
1990 19:22:41.102827 ============ PULL DRAM RESETB DOWN ============
1991 19:22:41.109559 ========== PULL DRAM RESETB DOWN end =========
1992 19:22:41.112572 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
1993 19:22:41.115985 ===================================
1994 19:22:41.119136 LPDDR4 DRAM CONFIGURATION
1995 19:22:41.122730 ===================================
1996 19:22:41.122801 EX_ROW_EN[0] = 0x0
1997 19:22:41.125767 EX_ROW_EN[1] = 0x0
1998 19:22:41.125868 LP4Y_EN = 0x0
1999 19:22:41.129082 WORK_FSP = 0x0
2000 19:22:41.129155 WL = 0x4
2001 19:22:41.132363 RL = 0x4
2002 19:22:41.132464 BL = 0x2
2003 19:22:41.136065 RPST = 0x0
2004 19:22:41.136158 RD_PRE = 0x0
2005 19:22:41.139345 WR_PRE = 0x1
2006 19:22:41.139437 WR_PST = 0x0
2007 19:22:41.142435 DBI_WR = 0x0
2008 19:22:41.142505 DBI_RD = 0x0
2009 19:22:41.145837 OTF = 0x1
2010 19:22:41.149220 ===================================
2011 19:22:41.152719 ===================================
2012 19:22:41.152821 ANA top config
2013 19:22:41.155990 ===================================
2014 19:22:41.159253 DLL_ASYNC_EN = 0
2015 19:22:41.162560 ALL_SLAVE_EN = 0
2016 19:22:41.166204 NEW_RANK_MODE = 1
2017 19:22:41.166276 DLL_IDLE_MODE = 1
2018 19:22:41.169579 LP45_APHY_COMB_EN = 1
2019 19:22:41.172512 TX_ODT_DIS = 1
2020 19:22:41.175702 NEW_8X_MODE = 1
2021 19:22:41.179130 ===================================
2022 19:22:41.182629 ===================================
2023 19:22:41.186065 data_rate = 2400
2024 19:22:41.186148 CKR = 1
2025 19:22:41.189122 DQ_P2S_RATIO = 8
2026 19:22:41.192721 ===================================
2027 19:22:41.196164 CA_P2S_RATIO = 8
2028 19:22:41.199192 DQ_CA_OPEN = 0
2029 19:22:41.202353 DQ_SEMI_OPEN = 0
2030 19:22:41.206034 CA_SEMI_OPEN = 0
2031 19:22:41.206148 CA_FULL_RATE = 0
2032 19:22:41.209060 DQ_CKDIV4_EN = 0
2033 19:22:41.212504 CA_CKDIV4_EN = 0
2034 19:22:41.215700 CA_PREDIV_EN = 0
2035 19:22:41.219355 PH8_DLY = 17
2036 19:22:41.222456 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2037 19:22:41.222541 DQ_AAMCK_DIV = 4
2038 19:22:41.225438 CA_AAMCK_DIV = 4
2039 19:22:41.229075 CA_ADMCK_DIV = 4
2040 19:22:41.232331 DQ_TRACK_CA_EN = 0
2041 19:22:41.235501 CA_PICK = 1200
2042 19:22:41.238821 CA_MCKIO = 1200
2043 19:22:41.242196 MCKIO_SEMI = 0
2044 19:22:41.242268 PLL_FREQ = 2366
2045 19:22:41.245602 DQ_UI_PI_RATIO = 32
2046 19:22:41.248922 CA_UI_PI_RATIO = 0
2047 19:22:41.252251 ===================================
2048 19:22:41.255863 ===================================
2049 19:22:41.259060 memory_type:LPDDR4
2050 19:22:41.259132 GP_NUM : 10
2051 19:22:41.262427 SRAM_EN : 1
2052 19:22:41.265935 MD32_EN : 0
2053 19:22:41.269215 ===================================
2054 19:22:41.269313 [ANA_INIT] >>>>>>>>>>>>>>
2055 19:22:41.272792 <<<<<< [CONFIGURE PHASE]: ANA_TX
2056 19:22:41.276379 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2057 19:22:41.279263 ===================================
2058 19:22:41.282538 data_rate = 2400,PCW = 0X5b00
2059 19:22:41.285729 ===================================
2060 19:22:41.289465 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2061 19:22:41.295689 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2062 19:22:41.299043 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2063 19:22:41.305569 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2064 19:22:41.308873 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2065 19:22:41.312404 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2066 19:22:41.312485 [ANA_INIT] flow start
2067 19:22:41.315726 [ANA_INIT] PLL >>>>>>>>
2068 19:22:41.319158 [ANA_INIT] PLL <<<<<<<<
2069 19:22:41.319238 [ANA_INIT] MIDPI >>>>>>>>
2070 19:22:41.322209 [ANA_INIT] MIDPI <<<<<<<<
2071 19:22:41.325704 [ANA_INIT] DLL >>>>>>>>
2072 19:22:41.329030 [ANA_INIT] DLL <<<<<<<<
2073 19:22:41.329111 [ANA_INIT] flow end
2074 19:22:41.332327 ============ LP4 DIFF to SE enter ============
2075 19:22:41.338967 ============ LP4 DIFF to SE exit ============
2076 19:22:41.339045 [ANA_INIT] <<<<<<<<<<<<<
2077 19:22:41.342496 [Flow] Enable top DCM control >>>>>
2078 19:22:41.345622 [Flow] Enable top DCM control <<<<<
2079 19:22:41.349313 Enable DLL master slave shuffle
2080 19:22:41.355445 ==============================================================
2081 19:22:41.355553 Gating Mode config
2082 19:22:41.362734 ==============================================================
2083 19:22:41.365689 Config description:
2084 19:22:41.372570 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2085 19:22:41.379421 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2086 19:22:41.385468 SELPH_MODE 0: By rank 1: By Phase
2087 19:22:41.392168 ==============================================================
2088 19:22:41.395449 GAT_TRACK_EN = 1
2089 19:22:41.395530 RX_GATING_MODE = 2
2090 19:22:41.398729 RX_GATING_TRACK_MODE = 2
2091 19:22:41.402357 SELPH_MODE = 1
2092 19:22:41.405662 PICG_EARLY_EN = 1
2093 19:22:41.408784 VALID_LAT_VALUE = 1
2094 19:22:41.415390 ==============================================================
2095 19:22:41.418878 Enter into Gating configuration >>>>
2096 19:22:41.422370 Exit from Gating configuration <<<<
2097 19:22:41.425512 Enter into DVFS_PRE_config >>>>>
2098 19:22:41.435556 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2099 19:22:41.438843 Exit from DVFS_PRE_config <<<<<
2100 19:22:41.441971 Enter into PICG configuration >>>>
2101 19:22:41.445542 Exit from PICG configuration <<<<
2102 19:22:41.448748 [RX_INPUT] configuration >>>>>
2103 19:22:41.452110 [RX_INPUT] configuration <<<<<
2104 19:22:41.455592 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2105 19:22:41.462015 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2106 19:22:41.468746 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2107 19:22:41.472051 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2108 19:22:41.478427 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2109 19:22:41.485468 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2110 19:22:41.488689 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2111 19:22:41.492314 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2112 19:22:41.498799 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2113 19:22:41.502301 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2114 19:22:41.505267 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2115 19:22:41.512505 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2116 19:22:41.515506 ===================================
2117 19:22:41.515587 LPDDR4 DRAM CONFIGURATION
2118 19:22:41.518708 ===================================
2119 19:22:41.521849 EX_ROW_EN[0] = 0x0
2120 19:22:41.521957 EX_ROW_EN[1] = 0x0
2121 19:22:41.525530 LP4Y_EN = 0x0
2122 19:22:41.525618 WORK_FSP = 0x0
2123 19:22:41.528613 WL = 0x4
2124 19:22:41.528693 RL = 0x4
2125 19:22:41.532220 BL = 0x2
2126 19:22:41.536050 RPST = 0x0
2127 19:22:41.536131 RD_PRE = 0x0
2128 19:22:41.538937 WR_PRE = 0x1
2129 19:22:41.539017 WR_PST = 0x0
2130 19:22:41.541890 DBI_WR = 0x0
2131 19:22:41.541995 DBI_RD = 0x0
2132 19:22:41.545361 OTF = 0x1
2133 19:22:41.548790 ===================================
2134 19:22:41.552249 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2135 19:22:41.555463 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2136 19:22:41.558634 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2137 19:22:41.562078 ===================================
2138 19:22:41.565290 LPDDR4 DRAM CONFIGURATION
2139 19:22:41.568956 ===================================
2140 19:22:41.571801 EX_ROW_EN[0] = 0x10
2141 19:22:41.571879 EX_ROW_EN[1] = 0x0
2142 19:22:41.575023 LP4Y_EN = 0x0
2143 19:22:41.575130 WORK_FSP = 0x0
2144 19:22:41.578517 WL = 0x4
2145 19:22:41.578597 RL = 0x4
2146 19:22:41.581815 BL = 0x2
2147 19:22:41.581887 RPST = 0x0
2148 19:22:41.585096 RD_PRE = 0x0
2149 19:22:41.585177 WR_PRE = 0x1
2150 19:22:41.588737 WR_PST = 0x0
2151 19:22:41.592019 DBI_WR = 0x0
2152 19:22:41.592100 DBI_RD = 0x0
2153 19:22:41.595546 OTF = 0x1
2154 19:22:41.598394 ===================================
2155 19:22:41.601599 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2156 19:22:41.601680 ==
2157 19:22:41.605332 Dram Type= 6, Freq= 0, CH_0, rank 0
2158 19:22:41.611704 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2159 19:22:41.611786 ==
2160 19:22:41.611851 [Duty_Offset_Calibration]
2161 19:22:41.615478 B0:0 B1:2 CA:1
2162 19:22:41.615558
2163 19:22:41.618236 [DutyScan_Calibration_Flow] k_type=0
2164 19:22:41.627886
2165 19:22:41.627967 ==CLK 0==
2166 19:22:41.631111 Final CLK duty delay cell = 0
2167 19:22:41.634442 [0] MAX Duty = 5093%(X100), DQS PI = 12
2168 19:22:41.637920 [0] MIN Duty = 4938%(X100), DQS PI = 54
2169 19:22:41.638051 [0] AVG Duty = 5015%(X100)
2170 19:22:41.641035
2171 19:22:41.644548 CH0 CLK Duty spec in!! Max-Min= 155%
2172 19:22:41.647397 [DutyScan_Calibration_Flow] ====Done====
2173 19:22:41.647477
2174 19:22:41.651144 [DutyScan_Calibration_Flow] k_type=1
2175 19:22:41.667002
2176 19:22:41.667086 ==DQS 0 ==
2177 19:22:41.670411 Final DQS duty delay cell = 0
2178 19:22:41.673508 [0] MAX Duty = 5125%(X100), DQS PI = 32
2179 19:22:41.677047 [0] MIN Duty = 5031%(X100), DQS PI = 6
2180 19:22:41.677128 [0] AVG Duty = 5078%(X100)
2181 19:22:41.680071
2182 19:22:41.680151 ==DQS 1 ==
2183 19:22:41.683987 Final DQS duty delay cell = 0
2184 19:22:41.686815 [0] MAX Duty = 5062%(X100), DQS PI = 58
2185 19:22:41.690874 [0] MIN Duty = 4906%(X100), DQS PI = 16
2186 19:22:41.690955 [0] AVG Duty = 4984%(X100)
2187 19:22:41.693483
2188 19:22:41.696842 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2189 19:22:41.696923
2190 19:22:41.700452 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2191 19:22:41.703517 [DutyScan_Calibration_Flow] ====Done====
2192 19:22:41.703599
2193 19:22:41.706793 [DutyScan_Calibration_Flow] k_type=3
2194 19:22:41.724294
2195 19:22:41.724375 ==DQM 0 ==
2196 19:22:41.727574 Final DQM duty delay cell = 0
2197 19:22:41.730827 [0] MAX Duty = 5124%(X100), DQS PI = 20
2198 19:22:41.733923 [0] MIN Duty = 4969%(X100), DQS PI = 40
2199 19:22:41.737389 [0] AVG Duty = 5046%(X100)
2200 19:22:41.737464
2201 19:22:41.737526 ==DQM 1 ==
2202 19:22:41.740660 Final DQM duty delay cell = 4
2203 19:22:41.744251 [4] MAX Duty = 5187%(X100), DQS PI = 54
2204 19:22:41.747477 [4] MIN Duty = 5000%(X100), DQS PI = 16
2205 19:22:41.750596 [4] AVG Duty = 5093%(X100)
2206 19:22:41.750677
2207 19:22:41.753910 CH0 DQM 0 Duty spec in!! Max-Min= 155%
2208 19:22:41.754016
2209 19:22:41.757589 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2210 19:22:41.760623 [DutyScan_Calibration_Flow] ====Done====
2211 19:22:41.760704
2212 19:22:41.764370 [DutyScan_Calibration_Flow] k_type=2
2213 19:22:41.778893
2214 19:22:41.778973 ==DQ 0 ==
2215 19:22:41.782685 Final DQ duty delay cell = -4
2216 19:22:41.786168 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2217 19:22:41.789169 [-4] MIN Duty = 4813%(X100), DQS PI = 54
2218 19:22:41.792760 [-4] AVG Duty = 4937%(X100)
2219 19:22:41.792867
2220 19:22:41.792958 ==DQ 1 ==
2221 19:22:41.795623 Final DQ duty delay cell = -4
2222 19:22:41.799083 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2223 19:22:41.802064 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2224 19:22:41.805765 [-4] AVG Duty = 4969%(X100)
2225 19:22:41.805846
2226 19:22:41.809551 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2227 19:22:41.809632
2228 19:22:41.812252 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2229 19:22:41.815693 [DutyScan_Calibration_Flow] ====Done====
2230 19:22:41.815774 ==
2231 19:22:41.818680 Dram Type= 6, Freq= 0, CH_1, rank 0
2232 19:22:41.822391 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2233 19:22:41.822472 ==
2234 19:22:41.825645 [Duty_Offset_Calibration]
2235 19:22:41.825725 B0:0 B1:5 CA:-5
2236 19:22:41.828907
2237 19:22:41.828987 [DutyScan_Calibration_Flow] k_type=0
2238 19:22:41.839904
2239 19:22:41.839984 ==CLK 0==
2240 19:22:41.842997 Final CLK duty delay cell = 0
2241 19:22:41.846439 [0] MAX Duty = 5094%(X100), DQS PI = 24
2242 19:22:41.849676 [0] MIN Duty = 4875%(X100), DQS PI = 46
2243 19:22:41.849757 [0] AVG Duty = 4984%(X100)
2244 19:22:41.852965
2245 19:22:41.856768 CH1 CLK Duty spec in!! Max-Min= 219%
2246 19:22:41.860188 [DutyScan_Calibration_Flow] ====Done====
2247 19:22:41.860269
2248 19:22:41.862926 [DutyScan_Calibration_Flow] k_type=1
2249 19:22:41.878468
2250 19:22:41.878547 ==DQS 0 ==
2251 19:22:41.881513 Final DQS duty delay cell = 0
2252 19:22:41.884787 [0] MAX Duty = 5125%(X100), DQS PI = 16
2253 19:22:41.888430 [0] MIN Duty = 4875%(X100), DQS PI = 40
2254 19:22:41.891472 [0] AVG Duty = 5000%(X100)
2255 19:22:41.891553
2256 19:22:41.891616 ==DQS 1 ==
2257 19:22:41.894955 Final DQS duty delay cell = -4
2258 19:22:41.898261 [-4] MAX Duty = 5000%(X100), DQS PI = 18
2259 19:22:41.901504 [-4] MIN Duty = 4907%(X100), DQS PI = 44
2260 19:22:41.904705 [-4] AVG Duty = 4953%(X100)
2261 19:22:41.904786
2262 19:22:41.908583 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2263 19:22:41.908663
2264 19:22:41.911454 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2265 19:22:41.915008 [DutyScan_Calibration_Flow] ====Done====
2266 19:22:41.915088
2267 19:22:41.918287 [DutyScan_Calibration_Flow] k_type=3
2268 19:22:41.933728
2269 19:22:41.933808 ==DQM 0 ==
2270 19:22:41.936846 Final DQM duty delay cell = -4
2271 19:22:41.939961 [-4] MAX Duty = 5093%(X100), DQS PI = 30
2272 19:22:41.943735 [-4] MIN Duty = 4844%(X100), DQS PI = 40
2273 19:22:41.947143 [-4] AVG Duty = 4968%(X100)
2274 19:22:41.947223
2275 19:22:41.947324 ==DQM 1 ==
2276 19:22:41.950159 Final DQM duty delay cell = -4
2277 19:22:41.953564 [-4] MAX Duty = 5062%(X100), DQS PI = 4
2278 19:22:41.957037 [-4] MIN Duty = 4906%(X100), DQS PI = 42
2279 19:22:41.960036 [-4] AVG Duty = 4984%(X100)
2280 19:22:41.960117
2281 19:22:41.963333 CH1 DQM 0 Duty spec in!! Max-Min= 249%
2282 19:22:41.963415
2283 19:22:41.966469 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2284 19:22:41.970134 [DutyScan_Calibration_Flow] ====Done====
2285 19:22:41.970215
2286 19:22:41.973650 [DutyScan_Calibration_Flow] k_type=2
2287 19:22:41.990783
2288 19:22:41.990865 ==DQ 0 ==
2289 19:22:41.994171 Final DQ duty delay cell = 0
2290 19:22:41.997470 [0] MAX Duty = 5062%(X100), DQS PI = 0
2291 19:22:42.000497 [0] MIN Duty = 4969%(X100), DQS PI = 42
2292 19:22:42.000578 [0] AVG Duty = 5015%(X100)
2293 19:22:42.000642
2294 19:22:42.004021 ==DQ 1 ==
2295 19:22:42.007393 Final DQ duty delay cell = 0
2296 19:22:42.010658 [0] MAX Duty = 5000%(X100), DQS PI = 6
2297 19:22:42.014059 [0] MIN Duty = 4907%(X100), DQS PI = 0
2298 19:22:42.014154 [0] AVG Duty = 4953%(X100)
2299 19:22:42.014218
2300 19:22:42.017480 CH1 DQ 0 Duty spec in!! Max-Min= 93%
2301 19:22:42.017560
2302 19:22:42.020686 CH1 DQ 1 Duty spec in!! Max-Min= 93%
2303 19:22:42.027592 [DutyScan_Calibration_Flow] ====Done====
2304 19:22:42.030793 nWR fixed to 30
2305 19:22:42.030878 [ModeRegInit_LP4] CH0 RK0
2306 19:22:42.033790 [ModeRegInit_LP4] CH0 RK1
2307 19:22:42.036713 [ModeRegInit_LP4] CH1 RK0
2308 19:22:42.036793 [ModeRegInit_LP4] CH1 RK1
2309 19:22:42.040719 match AC timing 6
2310 19:22:42.043400 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2311 19:22:42.047331 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2312 19:22:42.053628 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2313 19:22:42.057044 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2314 19:22:42.064011 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2315 19:22:42.064092 ==
2316 19:22:42.066703 Dram Type= 6, Freq= 0, CH_0, rank 0
2317 19:22:42.070368 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2318 19:22:42.070449 ==
2319 19:22:42.076877 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2320 19:22:42.080275 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2321 19:22:42.090059 [CA 0] Center 39 (9~70) winsize 62
2322 19:22:42.093650 [CA 1] Center 39 (9~70) winsize 62
2323 19:22:42.096639 [CA 2] Center 36 (5~67) winsize 63
2324 19:22:42.099906 [CA 3] Center 35 (5~66) winsize 62
2325 19:22:42.103518 [CA 4] Center 34 (3~65) winsize 63
2326 19:22:42.106578 [CA 5] Center 33 (3~64) winsize 62
2327 19:22:42.106659
2328 19:22:42.110012 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2329 19:22:42.110113
2330 19:22:42.113265 [CATrainingPosCal] consider 1 rank data
2331 19:22:42.116834 u2DelayCellTimex100 = 270/100 ps
2332 19:22:42.120184 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2333 19:22:42.126745 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2334 19:22:42.130136 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2335 19:22:42.133096 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2336 19:22:42.136760 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2337 19:22:42.139620 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2338 19:22:42.139701
2339 19:22:42.143081 CA PerBit enable=1, Macro0, CA PI delay=33
2340 19:22:42.143162
2341 19:22:42.146599 [CBTSetCACLKResult] CA Dly = 33
2342 19:22:42.146679 CS Dly: 7 (0~38)
2343 19:22:42.149873 ==
2344 19:22:42.153185 Dram Type= 6, Freq= 0, CH_0, rank 1
2345 19:22:42.156400 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2346 19:22:42.156480 ==
2347 19:22:42.159693 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2348 19:22:42.166371 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2349 19:22:42.175431 [CA 0] Center 39 (8~70) winsize 63
2350 19:22:42.178976 [CA 1] Center 39 (8~70) winsize 63
2351 19:22:42.182334 [CA 2] Center 36 (5~67) winsize 63
2352 19:22:42.185265 [CA 3] Center 35 (4~66) winsize 63
2353 19:22:42.188634 [CA 4] Center 33 (3~64) winsize 62
2354 19:22:42.191972 [CA 5] Center 34 (3~65) winsize 63
2355 19:22:42.192053
2356 19:22:42.195391 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2357 19:22:42.195472
2358 19:22:42.198434 [CATrainingPosCal] consider 2 rank data
2359 19:22:42.202286 u2DelayCellTimex100 = 270/100 ps
2360 19:22:42.205274 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2361 19:22:42.211735 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2362 19:22:42.215194 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2363 19:22:42.218995 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2364 19:22:42.222362 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2365 19:22:42.225824 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2366 19:22:42.225925
2367 19:22:42.229136 CA PerBit enable=1, Macro0, CA PI delay=33
2368 19:22:42.229245
2369 19:22:42.232039 [CBTSetCACLKResult] CA Dly = 33
2370 19:22:42.232143 CS Dly: 7 (0~39)
2371 19:22:42.235049
2372 19:22:42.238573 ----->DramcWriteLeveling(PI) begin...
2373 19:22:42.238654 ==
2374 19:22:42.241668 Dram Type= 6, Freq= 0, CH_0, rank 0
2375 19:22:42.245300 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2376 19:22:42.245381 ==
2377 19:22:42.248481 Write leveling (Byte 0): 28 => 28
2378 19:22:42.251935 Write leveling (Byte 1): 25 => 25
2379 19:22:42.255323 DramcWriteLeveling(PI) end<-----
2380 19:22:42.255404
2381 19:22:42.255467 ==
2382 19:22:42.258467 Dram Type= 6, Freq= 0, CH_0, rank 0
2383 19:22:42.261930 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2384 19:22:42.262011 ==
2385 19:22:42.265130 [Gating] SW mode calibration
2386 19:22:42.272022 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2387 19:22:42.278369 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2388 19:22:42.281539 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2389 19:22:42.284929 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2390 19:22:42.291343 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2391 19:22:42.294909 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2392 19:22:42.297970 0 11 16 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2393 19:22:42.304639 0 11 20 | B1->B0 | 2d2d 2b2b | 1 1 | (1 0) (0 0)
2394 19:22:42.308108 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2395 19:22:42.311859 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2396 19:22:42.318417 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2397 19:22:42.321683 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2398 19:22:42.324829 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2399 19:22:42.328349 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2400 19:22:42.334750 0 12 16 | B1->B0 | 2424 2929 | 0 0 | (0 0) (0 0)
2401 19:22:42.337945 0 12 20 | B1->B0 | 3838 3d3d | 0 0 | (0 0) (0 0)
2402 19:22:42.341392 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2403 19:22:42.348010 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2404 19:22:42.351366 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2405 19:22:42.354721 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2406 19:22:42.361390 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2407 19:22:42.364638 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2408 19:22:42.368582 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2409 19:22:42.374686 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2410 19:22:42.378379 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2411 19:22:42.381253 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2412 19:22:42.388147 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2413 19:22:42.391255 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2414 19:22:42.395269 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2415 19:22:42.401625 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2416 19:22:42.404933 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2417 19:22:42.408131 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2418 19:22:42.415125 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2419 19:22:42.418239 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2420 19:22:42.421209 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2421 19:22:42.428274 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2422 19:22:42.431460 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2423 19:22:42.434882 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2424 19:22:42.438251 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2425 19:22:42.445014 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2426 19:22:42.448002 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2427 19:22:42.451414 Total UI for P1: 0, mck2ui 16
2428 19:22:42.454414 best dqsien dly found for B0: ( 0, 15, 20)
2429 19:22:42.458408 Total UI for P1: 0, mck2ui 16
2430 19:22:42.461254 best dqsien dly found for B1: ( 0, 15, 20)
2431 19:22:42.464650 best DQS0 dly(MCK, UI, PI) = (0, 15, 20)
2432 19:22:42.468001 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2433 19:22:42.468086
2434 19:22:42.471403 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 20)
2435 19:22:42.477735 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2436 19:22:42.477849 [Gating] SW calibration Done
2437 19:22:42.477945 ==
2438 19:22:42.481162 Dram Type= 6, Freq= 0, CH_0, rank 0
2439 19:22:42.488091 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2440 19:22:42.488199 ==
2441 19:22:42.488296 RX Vref Scan: 0
2442 19:22:42.488390
2443 19:22:42.490885 RX Vref 0 -> 0, step: 1
2444 19:22:42.490993
2445 19:22:42.494515 RX Delay -40 -> 252, step: 8
2446 19:22:42.497697 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2447 19:22:42.501678 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2448 19:22:42.504370 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2449 19:22:42.510974 iDelay=200, Bit 3, Center 111 (32 ~ 191) 160
2450 19:22:42.514210 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2451 19:22:42.517708 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2452 19:22:42.520789 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2453 19:22:42.524226 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2454 19:22:42.527820 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2455 19:22:42.534244 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2456 19:22:42.537922 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2457 19:22:42.540905 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2458 19:22:42.544494 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2459 19:22:42.547752 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2460 19:22:42.554200 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2461 19:22:42.557654 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2462 19:22:42.557852 ==
2463 19:22:42.561217 Dram Type= 6, Freq= 0, CH_0, rank 0
2464 19:22:42.564429 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2465 19:22:42.564656 ==
2466 19:22:42.567539 DQS Delay:
2467 19:22:42.567795 DQS0 = 0, DQS1 = 0
2468 19:22:42.568044 DQM Delay:
2469 19:22:42.571122 DQM0 = 115, DQM1 = 105
2470 19:22:42.571428 DQ Delay:
2471 19:22:42.574585 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =111
2472 19:22:42.578006 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2473 19:22:42.581115 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =99
2474 19:22:42.588037 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =115
2475 19:22:42.588628
2476 19:22:42.589198
2477 19:22:42.589750 ==
2478 19:22:42.591296 Dram Type= 6, Freq= 0, CH_0, rank 0
2479 19:22:42.594350 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2480 19:22:42.594985 ==
2481 19:22:42.595547
2482 19:22:42.596129
2483 19:22:42.598002 TX Vref Scan disable
2484 19:22:42.598494 == TX Byte 0 ==
2485 19:22:42.605032 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2486 19:22:42.608261 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2487 19:22:42.608689 == TX Byte 1 ==
2488 19:22:42.614692 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2489 19:22:42.617688 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2490 19:22:42.618322 ==
2491 19:22:42.621520 Dram Type= 6, Freq= 0, CH_0, rank 0
2492 19:22:42.624728 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2493 19:22:42.625338 ==
2494 19:22:42.637207 TX Vref=22, minBit 8, minWin=25, winSum=415
2495 19:22:42.640746 TX Vref=24, minBit 8, minWin=25, winSum=423
2496 19:22:42.644133 TX Vref=26, minBit 10, minWin=24, winSum=430
2497 19:22:42.647333 TX Vref=28, minBit 13, minWin=25, winSum=431
2498 19:22:42.651029 TX Vref=30, minBit 8, minWin=26, winSum=435
2499 19:22:42.657261 TX Vref=32, minBit 8, minWin=26, winSum=436
2500 19:22:42.660569 [TxChooseVref] Worse bit 8, Min win 26, Win sum 436, Final Vref 32
2501 19:22:42.661146
2502 19:22:42.663844 Final TX Range 1 Vref 32
2503 19:22:42.664445
2504 19:22:42.664970 ==
2505 19:22:42.667726 Dram Type= 6, Freq= 0, CH_0, rank 0
2506 19:22:42.670156 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2507 19:22:42.673988 ==
2508 19:22:42.674605
2509 19:22:42.675142
2510 19:22:42.675653 TX Vref Scan disable
2511 19:22:42.677377 == TX Byte 0 ==
2512 19:22:42.680284 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2513 19:22:42.687173 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2514 19:22:42.687624 == TX Byte 1 ==
2515 19:22:42.690523 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2516 19:22:42.696887 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2517 19:22:42.697327
2518 19:22:42.697663 [DATLAT]
2519 19:22:42.697979 Freq=1200, CH0 RK0
2520 19:22:42.698392
2521 19:22:42.700416 DATLAT Default: 0xd
2522 19:22:42.700862 0, 0xFFFF, sum = 0
2523 19:22:42.704062 1, 0xFFFF, sum = 0
2524 19:22:42.704492 2, 0xFFFF, sum = 0
2525 19:22:42.707056 3, 0xFFFF, sum = 0
2526 19:22:42.710192 4, 0xFFFF, sum = 0
2527 19:22:42.710637 5, 0xFFFF, sum = 0
2528 19:22:42.713997 6, 0xFFFF, sum = 0
2529 19:22:42.714494 7, 0xFFFF, sum = 0
2530 19:22:42.716955 8, 0xFFFF, sum = 0
2531 19:22:42.717400 9, 0xFFFF, sum = 0
2532 19:22:42.720800 10, 0xFFFF, sum = 0
2533 19:22:42.721243 11, 0x0, sum = 1
2534 19:22:42.723955 12, 0x0, sum = 2
2535 19:22:42.724399 13, 0x0, sum = 3
2536 19:22:42.724846 14, 0x0, sum = 4
2537 19:22:42.727816 best_step = 12
2538 19:22:42.728250
2539 19:22:42.728690 ==
2540 19:22:42.730963 Dram Type= 6, Freq= 0, CH_0, rank 0
2541 19:22:42.733960 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2542 19:22:42.734443 ==
2543 19:22:42.737205 RX Vref Scan: 1
2544 19:22:42.737639
2545 19:22:42.740715 Set Vref Range= 32 -> 127
2546 19:22:42.741147
2547 19:22:42.741492 RX Vref 32 -> 127, step: 1
2548 19:22:42.741811
2549 19:22:42.743802 RX Delay -21 -> 252, step: 4
2550 19:22:42.744284
2551 19:22:42.747458 Set Vref, RX VrefLevel [Byte0]: 32
2552 19:22:42.750306 [Byte1]: 32
2553 19:22:42.753961
2554 19:22:42.754480 Set Vref, RX VrefLevel [Byte0]: 33
2555 19:22:42.757084 [Byte1]: 33
2556 19:22:42.761737
2557 19:22:42.762211 Set Vref, RX VrefLevel [Byte0]: 34
2558 19:22:42.765111 [Byte1]: 34
2559 19:22:42.770115
2560 19:22:42.770552 Set Vref, RX VrefLevel [Byte0]: 35
2561 19:22:42.773190 [Byte1]: 35
2562 19:22:42.777894
2563 19:22:42.778504 Set Vref, RX VrefLevel [Byte0]: 36
2564 19:22:42.781258 [Byte1]: 36
2565 19:22:42.785823
2566 19:22:42.786307 Set Vref, RX VrefLevel [Byte0]: 37
2567 19:22:42.789005 [Byte1]: 37
2568 19:22:42.793618
2569 19:22:42.794083 Set Vref, RX VrefLevel [Byte0]: 38
2570 19:22:42.796619 [Byte1]: 38
2571 19:22:42.801679
2572 19:22:42.802153 Set Vref, RX VrefLevel [Byte0]: 39
2573 19:22:42.804679 [Byte1]: 39
2574 19:22:42.809421
2575 19:22:42.809857 Set Vref, RX VrefLevel [Byte0]: 40
2576 19:22:42.812396 [Byte1]: 40
2577 19:22:42.817101
2578 19:22:42.817536 Set Vref, RX VrefLevel [Byte0]: 41
2579 19:22:42.820469 [Byte1]: 41
2580 19:22:42.825385
2581 19:22:42.825823 Set Vref, RX VrefLevel [Byte0]: 42
2582 19:22:42.828796 [Byte1]: 42
2583 19:22:42.832952
2584 19:22:42.833363 Set Vref, RX VrefLevel [Byte0]: 43
2585 19:22:42.836574 [Byte1]: 43
2586 19:22:42.840942
2587 19:22:42.841022 Set Vref, RX VrefLevel [Byte0]: 44
2588 19:22:42.844251 [Byte1]: 44
2589 19:22:42.848843
2590 19:22:42.848928 Set Vref, RX VrefLevel [Byte0]: 45
2591 19:22:42.852017 [Byte1]: 45
2592 19:22:42.856904
2593 19:22:42.856987 Set Vref, RX VrefLevel [Byte0]: 46
2594 19:22:42.860014 [Byte1]: 46
2595 19:22:42.864684
2596 19:22:42.864836 Set Vref, RX VrefLevel [Byte0]: 47
2597 19:22:42.867860 [Byte1]: 47
2598 19:22:42.872480
2599 19:22:42.872583 Set Vref, RX VrefLevel [Byte0]: 48
2600 19:22:42.875517 [Byte1]: 48
2601 19:22:42.880392
2602 19:22:42.880477 Set Vref, RX VrefLevel [Byte0]: 49
2603 19:22:42.883763 [Byte1]: 49
2604 19:22:42.888221
2605 19:22:42.888328 Set Vref, RX VrefLevel [Byte0]: 50
2606 19:22:42.891560 [Byte1]: 50
2607 19:22:42.896423
2608 19:22:42.896494 Set Vref, RX VrefLevel [Byte0]: 51
2609 19:22:42.899617 [Byte1]: 51
2610 19:22:42.904409
2611 19:22:42.904489 Set Vref, RX VrefLevel [Byte0]: 52
2612 19:22:42.907473 [Byte1]: 52
2613 19:22:42.912141
2614 19:22:42.912221 Set Vref, RX VrefLevel [Byte0]: 53
2615 19:22:42.915677 [Byte1]: 53
2616 19:22:42.920268
2617 19:22:42.920349 Set Vref, RX VrefLevel [Byte0]: 54
2618 19:22:42.923626 [Byte1]: 54
2619 19:22:42.928124
2620 19:22:42.928204 Set Vref, RX VrefLevel [Byte0]: 55
2621 19:22:42.931132 [Byte1]: 55
2622 19:22:42.936217
2623 19:22:42.936298 Set Vref, RX VrefLevel [Byte0]: 56
2624 19:22:42.939472 [Byte1]: 56
2625 19:22:42.943968
2626 19:22:42.944050 Set Vref, RX VrefLevel [Byte0]: 57
2627 19:22:42.947283 [Byte1]: 57
2628 19:22:42.951749
2629 19:22:42.951831 Set Vref, RX VrefLevel [Byte0]: 58
2630 19:22:42.958060 [Byte1]: 58
2631 19:22:42.958143
2632 19:22:42.961591 Set Vref, RX VrefLevel [Byte0]: 59
2633 19:22:42.964939 [Byte1]: 59
2634 19:22:42.965021
2635 19:22:42.968479 Set Vref, RX VrefLevel [Byte0]: 60
2636 19:22:42.971670 [Byte1]: 60
2637 19:22:42.975469
2638 19:22:42.975551 Set Vref, RX VrefLevel [Byte0]: 61
2639 19:22:42.978654 [Byte1]: 61
2640 19:22:42.983557
2641 19:22:42.983639 Set Vref, RX VrefLevel [Byte0]: 62
2642 19:22:42.986654 [Byte1]: 62
2643 19:22:42.991718
2644 19:22:42.991801 Set Vref, RX VrefLevel [Byte0]: 63
2645 19:22:42.994535 [Byte1]: 63
2646 19:22:42.999305
2647 19:22:42.999385 Set Vref, RX VrefLevel [Byte0]: 64
2648 19:22:43.002572 [Byte1]: 64
2649 19:22:43.007065
2650 19:22:43.007146 Set Vref, RX VrefLevel [Byte0]: 65
2651 19:22:43.010637 [Byte1]: 65
2652 19:22:43.015219
2653 19:22:43.015300 Set Vref, RX VrefLevel [Byte0]: 66
2654 19:22:43.018757 [Byte1]: 66
2655 19:22:43.023168
2656 19:22:43.023249 Final RX Vref Byte 0 = 52 to rank0
2657 19:22:43.026251 Final RX Vref Byte 1 = 46 to rank0
2658 19:22:43.029931 Final RX Vref Byte 0 = 52 to rank1
2659 19:22:43.032878 Final RX Vref Byte 1 = 46 to rank1==
2660 19:22:43.036223 Dram Type= 6, Freq= 0, CH_0, rank 0
2661 19:22:43.042773 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2662 19:22:43.042855 ==
2663 19:22:43.042920 DQS Delay:
2664 19:22:43.042981 DQS0 = 0, DQS1 = 0
2665 19:22:43.046301 DQM Delay:
2666 19:22:43.046382 DQM0 = 114, DQM1 = 104
2667 19:22:43.049564 DQ Delay:
2668 19:22:43.052915 DQ0 =110, DQ1 =114, DQ2 =114, DQ3 =110
2669 19:22:43.056347 DQ4 =118, DQ5 =106, DQ6 =124, DQ7 =120
2670 19:22:43.059447 DQ8 =94, DQ9 =86, DQ10 =106, DQ11 =96
2671 19:22:43.062702 DQ12 =112, DQ13 =112, DQ14 =118, DQ15 =114
2672 19:22:43.062783
2673 19:22:43.062847
2674 19:22:43.069497 [DQSOSCAuto] RK0, (LSB)MR18= 0xb0b, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
2675 19:22:43.072977 CH0 RK0: MR19=404, MR18=B0B
2676 19:22:43.079645 CH0_RK0: MR19=0x404, MR18=0xB0B, DQSOSC=405, MR23=63, INC=39, DEC=26
2677 19:22:43.079727
2678 19:22:43.082767 ----->DramcWriteLeveling(PI) begin...
2679 19:22:43.082850 ==
2680 19:22:43.086309 Dram Type= 6, Freq= 0, CH_0, rank 1
2681 19:22:43.090032 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2682 19:22:43.090150 ==
2683 19:22:43.093145 Write leveling (Byte 0): 28 => 28
2684 19:22:43.096435 Write leveling (Byte 1): 26 => 26
2685 19:22:43.099947 DramcWriteLeveling(PI) end<-----
2686 19:22:43.100028
2687 19:22:43.100092 ==
2688 19:22:43.103048 Dram Type= 6, Freq= 0, CH_0, rank 1
2689 19:22:43.106405 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2690 19:22:43.109919 ==
2691 19:22:43.110001 [Gating] SW mode calibration
2692 19:22:43.116813 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2693 19:22:43.123020 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2694 19:22:43.126012 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2695 19:22:43.133078 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2696 19:22:43.136299 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2697 19:22:43.139457 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2698 19:22:43.146293 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
2699 19:22:43.149566 0 11 20 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (1 0)
2700 19:22:43.152916 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2701 19:22:43.159472 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2702 19:22:43.162792 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2703 19:22:43.166147 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2704 19:22:43.172669 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2705 19:22:43.176118 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2706 19:22:43.179327 0 12 16 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
2707 19:22:43.185909 0 12 20 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
2708 19:22:43.189530 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2709 19:22:43.192333 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2710 19:22:43.199650 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2711 19:22:43.202631 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2712 19:22:43.205778 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2713 19:22:43.212513 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2714 19:22:43.215705 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2715 19:22:43.219362 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2716 19:22:43.225630 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2717 19:22:43.228920 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2718 19:22:43.232706 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2719 19:22:43.239130 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2720 19:22:43.242498 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2721 19:22:43.245480 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2722 19:22:43.248992 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2723 19:22:43.255355 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2724 19:22:43.259223 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2725 19:22:43.262175 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2726 19:22:43.269021 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2727 19:22:43.272156 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2728 19:22:43.275376 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2729 19:22:43.281980 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2730 19:22:43.285771 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2731 19:22:43.288953 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2732 19:22:43.291941 Total UI for P1: 0, mck2ui 16
2733 19:22:43.295671 best dqsien dly found for B0: ( 0, 15, 16)
2734 19:22:43.301922 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2735 19:22:43.305335 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2736 19:22:43.308616 Total UI for P1: 0, mck2ui 16
2737 19:22:43.312228 best dqsien dly found for B1: ( 0, 15, 20)
2738 19:22:43.315148 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
2739 19:22:43.319004 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2740 19:22:43.319085
2741 19:22:43.322074 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
2742 19:22:43.325426 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2743 19:22:43.329147 [Gating] SW calibration Done
2744 19:22:43.329228 ==
2745 19:22:43.332430 Dram Type= 6, Freq= 0, CH_0, rank 1
2746 19:22:43.335714 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2747 19:22:43.338570 ==
2748 19:22:43.338652 RX Vref Scan: 0
2749 19:22:43.338716
2750 19:22:43.342201 RX Vref 0 -> 0, step: 1
2751 19:22:43.342282
2752 19:22:43.345415 RX Delay -40 -> 252, step: 8
2753 19:22:43.348655 iDelay=200, Bit 0, Center 107 (32 ~ 183) 152
2754 19:22:43.352027 iDelay=200, Bit 1, Center 119 (40 ~ 199) 160
2755 19:22:43.355279 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2756 19:22:43.358441 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2757 19:22:43.365244 iDelay=200, Bit 4, Center 119 (40 ~ 199) 160
2758 19:22:43.369029 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2759 19:22:43.372176 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2760 19:22:43.375408 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2761 19:22:43.378772 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2762 19:22:43.381940 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2763 19:22:43.388396 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2764 19:22:43.392302 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2765 19:22:43.395037 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2766 19:22:43.398384 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2767 19:22:43.405060 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2768 19:22:43.408553 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2769 19:22:43.408635 ==
2770 19:22:43.411821 Dram Type= 6, Freq= 0, CH_0, rank 1
2771 19:22:43.415209 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2772 19:22:43.415291 ==
2773 19:22:43.415356 DQS Delay:
2774 19:22:43.418581 DQS0 = 0, DQS1 = 0
2775 19:22:43.418663 DQM Delay:
2776 19:22:43.421821 DQM0 = 115, DQM1 = 106
2777 19:22:43.421904 DQ Delay:
2778 19:22:43.425244 DQ0 =107, DQ1 =119, DQ2 =115, DQ3 =107
2779 19:22:43.428488 DQ4 =119, DQ5 =107, DQ6 =123, DQ7 =123
2780 19:22:43.431975 DQ8 =91, DQ9 =91, DQ10 =107, DQ11 =99
2781 19:22:43.435427 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2782 19:22:43.435508
2783 19:22:43.438796
2784 19:22:43.438877 ==
2785 19:22:43.441811 Dram Type= 6, Freq= 0, CH_0, rank 1
2786 19:22:43.445738 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2787 19:22:43.445820 ==
2788 19:22:43.445884
2789 19:22:43.445944
2790 19:22:43.448490 TX Vref Scan disable
2791 19:22:43.448572 == TX Byte 0 ==
2792 19:22:43.452250 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2793 19:22:43.458705 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2794 19:22:43.458787 == TX Byte 1 ==
2795 19:22:43.461964 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2796 19:22:43.468492 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2797 19:22:43.468573 ==
2798 19:22:43.472342 Dram Type= 6, Freq= 0, CH_0, rank 1
2799 19:22:43.475262 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2800 19:22:43.475344 ==
2801 19:22:43.487257 TX Vref=22, minBit 8, minWin=25, winSum=421
2802 19:22:43.490773 TX Vref=24, minBit 1, minWin=26, winSum=428
2803 19:22:43.493903 TX Vref=26, minBit 9, minWin=26, winSum=430
2804 19:22:43.497320 TX Vref=28, minBit 9, minWin=26, winSum=433
2805 19:22:43.500896 TX Vref=30, minBit 8, minWin=26, winSum=434
2806 19:22:43.507112 TX Vref=32, minBit 10, minWin=25, winSum=433
2807 19:22:43.510790 [TxChooseVref] Worse bit 8, Min win 26, Win sum 434, Final Vref 30
2808 19:22:43.510872
2809 19:22:43.513753 Final TX Range 1 Vref 30
2810 19:22:43.513834
2811 19:22:43.513900 ==
2812 19:22:43.517220 Dram Type= 6, Freq= 0, CH_0, rank 1
2813 19:22:43.520471 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2814 19:22:43.520553 ==
2815 19:22:43.523826
2816 19:22:43.523906
2817 19:22:43.523969 TX Vref Scan disable
2818 19:22:43.527044 == TX Byte 0 ==
2819 19:22:43.530427 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2820 19:22:43.533880 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2821 19:22:43.537657 == TX Byte 1 ==
2822 19:22:43.540583 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2823 19:22:43.543841 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2824 19:22:43.547070
2825 19:22:43.547151 [DATLAT]
2826 19:22:43.547216 Freq=1200, CH0 RK1
2827 19:22:43.547278
2828 19:22:43.550545 DATLAT Default: 0xc
2829 19:22:43.550626 0, 0xFFFF, sum = 0
2830 19:22:43.553901 1, 0xFFFF, sum = 0
2831 19:22:43.553983 2, 0xFFFF, sum = 0
2832 19:22:43.557322 3, 0xFFFF, sum = 0
2833 19:22:43.557404 4, 0xFFFF, sum = 0
2834 19:22:43.560746 5, 0xFFFF, sum = 0
2835 19:22:43.563624 6, 0xFFFF, sum = 0
2836 19:22:43.563709 7, 0xFFFF, sum = 0
2837 19:22:43.566978 8, 0xFFFF, sum = 0
2838 19:22:43.567061 9, 0xFFFF, sum = 0
2839 19:22:43.570203 10, 0xFFFF, sum = 0
2840 19:22:43.570285 11, 0x0, sum = 1
2841 19:22:43.573877 12, 0x0, sum = 2
2842 19:22:43.573959 13, 0x0, sum = 3
2843 19:22:43.576998 14, 0x0, sum = 4
2844 19:22:43.577080 best_step = 12
2845 19:22:43.577145
2846 19:22:43.577204 ==
2847 19:22:43.580266 Dram Type= 6, Freq= 0, CH_0, rank 1
2848 19:22:43.583571 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2849 19:22:43.583652 ==
2850 19:22:43.587000 RX Vref Scan: 0
2851 19:22:43.587082
2852 19:22:43.590402 RX Vref 0 -> 0, step: 1
2853 19:22:43.590483
2854 19:22:43.590547 RX Delay -21 -> 252, step: 4
2855 19:22:43.597922 iDelay=199, Bit 0, Center 110 (39 ~ 182) 144
2856 19:22:43.600789 iDelay=199, Bit 1, Center 116 (43 ~ 190) 148
2857 19:22:43.604396 iDelay=199, Bit 2, Center 114 (43 ~ 186) 144
2858 19:22:43.607498 iDelay=199, Bit 3, Center 110 (39 ~ 182) 144
2859 19:22:43.611148 iDelay=199, Bit 4, Center 118 (43 ~ 194) 152
2860 19:22:43.618141 iDelay=199, Bit 5, Center 108 (39 ~ 178) 140
2861 19:22:43.620770 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
2862 19:22:43.624342 iDelay=199, Bit 7, Center 124 (51 ~ 198) 148
2863 19:22:43.627516 iDelay=199, Bit 8, Center 92 (31 ~ 154) 124
2864 19:22:43.630925 iDelay=199, Bit 9, Center 90 (27 ~ 154) 128
2865 19:22:43.637509 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
2866 19:22:43.640983 iDelay=199, Bit 11, Center 96 (35 ~ 158) 124
2867 19:22:43.644193 iDelay=199, Bit 12, Center 112 (47 ~ 178) 132
2868 19:22:43.647448 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
2869 19:22:43.650931 iDelay=199, Bit 14, Center 116 (51 ~ 182) 132
2870 19:22:43.657555 iDelay=199, Bit 15, Center 114 (51 ~ 178) 128
2871 19:22:43.657637 ==
2872 19:22:43.660887 Dram Type= 6, Freq= 0, CH_0, rank 1
2873 19:22:43.664303 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2874 19:22:43.664385 ==
2875 19:22:43.664449 DQS Delay:
2876 19:22:43.667593 DQS0 = 0, DQS1 = 0
2877 19:22:43.667674 DQM Delay:
2878 19:22:43.670928 DQM0 = 115, DQM1 = 105
2879 19:22:43.671009 DQ Delay:
2880 19:22:43.674044 DQ0 =110, DQ1 =116, DQ2 =114, DQ3 =110
2881 19:22:43.677715 DQ4 =118, DQ5 =108, DQ6 =122, DQ7 =124
2882 19:22:43.681256 DQ8 =92, DQ9 =90, DQ10 =110, DQ11 =96
2883 19:22:43.684195 DQ12 =112, DQ13 =112, DQ14 =116, DQ15 =114
2884 19:22:43.684276
2885 19:22:43.684340
2886 19:22:43.694382 [DQSOSCAuto] RK1, (LSB)MR18= 0xe0e, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
2887 19:22:43.697406 CH0 RK1: MR19=404, MR18=E0E
2888 19:22:43.701007 CH0_RK1: MR19=0x404, MR18=0xE0E, DQSOSC=404, MR23=63, INC=40, DEC=26
2889 19:22:43.704067 [RxdqsGatingPostProcess] freq 1200
2890 19:22:43.710705 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2891 19:22:43.714167 Pre-setting of DQS Precalculation
2892 19:22:43.717770 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2893 19:22:43.717851 ==
2894 19:22:43.720937 Dram Type= 6, Freq= 0, CH_1, rank 0
2895 19:22:43.727491 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2896 19:22:43.727573 ==
2897 19:22:43.730660 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2898 19:22:43.737252 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2899 19:22:43.746123 [CA 0] Center 37 (7~68) winsize 62
2900 19:22:43.749327 [CA 1] Center 37 (7~68) winsize 62
2901 19:22:43.752556 [CA 2] Center 34 (4~65) winsize 62
2902 19:22:43.756316 [CA 3] Center 33 (3~64) winsize 62
2903 19:22:43.759184 [CA 4] Center 32 (2~63) winsize 62
2904 19:22:43.762797 [CA 5] Center 32 (2~63) winsize 62
2905 19:22:43.762898
2906 19:22:43.766009 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2907 19:22:43.766099
2908 19:22:43.769533 [CATrainingPosCal] consider 1 rank data
2909 19:22:43.772666 u2DelayCellTimex100 = 270/100 ps
2910 19:22:43.776175 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2911 19:22:43.779614 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2912 19:22:43.785967 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2913 19:22:43.789384 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2914 19:22:43.792862 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2915 19:22:43.795847 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2916 19:22:43.795928
2917 19:22:43.799112 CA PerBit enable=1, Macro0, CA PI delay=32
2918 19:22:43.799194
2919 19:22:43.802986 [CBTSetCACLKResult] CA Dly = 32
2920 19:22:43.803067 CS Dly: 5 (0~36)
2921 19:22:43.805935 ==
2922 19:22:43.806017 Dram Type= 6, Freq= 0, CH_1, rank 1
2923 19:22:43.812560 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2924 19:22:43.812642 ==
2925 19:22:43.816230 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2926 19:22:43.822504 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2927 19:22:43.831107 [CA 0] Center 37 (7~68) winsize 62
2928 19:22:43.834637 [CA 1] Center 37 (7~68) winsize 62
2929 19:22:43.838207 [CA 2] Center 34 (3~65) winsize 63
2930 19:22:43.841673 [CA 3] Center 33 (3~64) winsize 62
2931 19:22:43.844583 [CA 4] Center 32 (2~63) winsize 62
2932 19:22:43.847672 [CA 5] Center 32 (1~63) winsize 63
2933 19:22:43.847753
2934 19:22:43.851025 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2935 19:22:43.851106
2936 19:22:43.854518 [CATrainingPosCal] consider 2 rank data
2937 19:22:43.857622 u2DelayCellTimex100 = 270/100 ps
2938 19:22:43.861011 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2939 19:22:43.864474 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2940 19:22:43.871425 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2941 19:22:43.874831 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2942 19:22:43.877946 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2943 19:22:43.881061 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2944 19:22:43.881143
2945 19:22:43.884424 CA PerBit enable=1, Macro0, CA PI delay=32
2946 19:22:43.884505
2947 19:22:43.887982 [CBTSetCACLKResult] CA Dly = 32
2948 19:22:43.888063 CS Dly: 6 (0~38)
2949 19:22:43.888127
2950 19:22:43.891172 ----->DramcWriteLeveling(PI) begin...
2951 19:22:43.894323 ==
2952 19:22:43.897818 Dram Type= 6, Freq= 0, CH_1, rank 0
2953 19:22:43.900974 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2954 19:22:43.901055 ==
2955 19:22:43.904532 Write leveling (Byte 0): 22 => 22
2956 19:22:43.907862 Write leveling (Byte 1): 22 => 22
2957 19:22:43.910890 DramcWriteLeveling(PI) end<-----
2958 19:22:43.910972
2959 19:22:43.911036 ==
2960 19:22:43.914702 Dram Type= 6, Freq= 0, CH_1, rank 0
2961 19:22:43.917651 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2962 19:22:43.917733 ==
2963 19:22:43.920972 [Gating] SW mode calibration
2964 19:22:43.927514 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2965 19:22:43.934294 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2966 19:22:43.937773 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2967 19:22:43.941056 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2968 19:22:43.944436 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2969 19:22:43.950984 0 11 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2970 19:22:43.954263 0 11 16 | B1->B0 | 3434 2a2a | 1 1 | (1 1) (1 0)
2971 19:22:43.957343 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2972 19:22:43.964193 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2973 19:22:43.967571 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2974 19:22:43.970706 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2975 19:22:43.977966 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2976 19:22:43.980852 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2977 19:22:43.984539 0 12 12 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
2978 19:22:43.990745 0 12 16 | B1->B0 | 2c2c 4343 | 1 0 | (0 0) (0 0)
2979 19:22:43.994243 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2980 19:22:43.997798 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2981 19:22:44.004420 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2982 19:22:44.007848 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2983 19:22:44.010907 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2984 19:22:44.017790 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2985 19:22:44.020562 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2986 19:22:44.023764 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2987 19:22:44.030564 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2988 19:22:44.033890 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2989 19:22:44.037224 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2990 19:22:44.043606 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2991 19:22:44.047080 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2992 19:22:44.050455 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2993 19:22:44.057039 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2994 19:22:44.060547 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2995 19:22:44.063781 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2996 19:22:44.070653 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2997 19:22:44.073607 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2998 19:22:44.076844 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2999 19:22:44.084050 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3000 19:22:44.087283 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3001 19:22:44.090533 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3002 19:22:44.093654 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3003 19:22:44.100543 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3004 19:22:44.103852 Total UI for P1: 0, mck2ui 16
3005 19:22:44.107155 best dqsien dly found for B0: ( 0, 15, 14)
3006 19:22:44.109979 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3007 19:22:44.113427 Total UI for P1: 0, mck2ui 16
3008 19:22:44.117248 best dqsien dly found for B1: ( 0, 15, 18)
3009 19:22:44.120253 best DQS0 dly(MCK, UI, PI) = (0, 15, 14)
3010 19:22:44.123505 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
3011 19:22:44.123585
3012 19:22:44.126723 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 14)
3013 19:22:44.133715 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
3014 19:22:44.133796 [Gating] SW calibration Done
3015 19:22:44.133860 ==
3016 19:22:44.136775 Dram Type= 6, Freq= 0, CH_1, rank 0
3017 19:22:44.143251 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3018 19:22:44.143333 ==
3019 19:22:44.143397 RX Vref Scan: 0
3020 19:22:44.143456
3021 19:22:44.146832 RX Vref 0 -> 0, step: 1
3022 19:22:44.146913
3023 19:22:44.150167 RX Delay -40 -> 252, step: 8
3024 19:22:44.153621 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3025 19:22:44.156840 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152
3026 19:22:44.160213 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3027 19:22:44.166989 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3028 19:22:44.169980 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3029 19:22:44.173445 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3030 19:22:44.176638 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3031 19:22:44.180200 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3032 19:22:44.183391 iDelay=208, Bit 8, Center 87 (16 ~ 159) 144
3033 19:22:44.189895 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3034 19:22:44.193621 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3035 19:22:44.196725 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3036 19:22:44.199962 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3037 19:22:44.203440 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3038 19:22:44.209845 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3039 19:22:44.213740 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3040 19:22:44.213820 ==
3041 19:22:44.216554 Dram Type= 6, Freq= 0, CH_1, rank 0
3042 19:22:44.220028 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3043 19:22:44.220109 ==
3044 19:22:44.223340 DQS Delay:
3045 19:22:44.223420 DQS0 = 0, DQS1 = 0
3046 19:22:44.223483 DQM Delay:
3047 19:22:44.226686 DQM0 = 116, DQM1 = 108
3048 19:22:44.226767 DQ Delay:
3049 19:22:44.229968 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3050 19:22:44.233147 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3051 19:22:44.236856 DQ8 =87, DQ9 =95, DQ10 =111, DQ11 =99
3052 19:22:44.243480 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3053 19:22:44.243561
3054 19:22:44.243625
3055 19:22:44.243684 ==
3056 19:22:44.246431 Dram Type= 6, Freq= 0, CH_1, rank 0
3057 19:22:44.249739 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3058 19:22:44.249820 ==
3059 19:22:44.249884
3060 19:22:44.249943
3061 19:22:44.253587 TX Vref Scan disable
3062 19:22:44.253667 == TX Byte 0 ==
3063 19:22:44.259780 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3064 19:22:44.263098 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3065 19:22:44.263179 == TX Byte 1 ==
3066 19:22:44.269785 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3067 19:22:44.273355 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3068 19:22:44.273436 ==
3069 19:22:44.276442 Dram Type= 6, Freq= 0, CH_1, rank 0
3070 19:22:44.280148 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3071 19:22:44.280229 ==
3072 19:22:44.292334 TX Vref=22, minBit 8, minWin=25, winSum=417
3073 19:22:44.295684 TX Vref=24, minBit 8, minWin=25, winSum=425
3074 19:22:44.299225 TX Vref=26, minBit 0, minWin=26, winSum=426
3075 19:22:44.301968 TX Vref=28, minBit 1, minWin=26, winSum=430
3076 19:22:44.305757 TX Vref=30, minBit 8, minWin=26, winSum=434
3077 19:22:44.308841 TX Vref=32, minBit 9, minWin=26, winSum=431
3078 19:22:44.315509 [TxChooseVref] Worse bit 8, Min win 26, Win sum 434, Final Vref 30
3079 19:22:44.315590
3080 19:22:44.318729 Final TX Range 1 Vref 30
3081 19:22:44.318812
3082 19:22:44.318876 ==
3083 19:22:44.322040 Dram Type= 6, Freq= 0, CH_1, rank 0
3084 19:22:44.325693 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3085 19:22:44.325775 ==
3086 19:22:44.329030
3087 19:22:44.329111
3088 19:22:44.329175 TX Vref Scan disable
3089 19:22:44.331950 == TX Byte 0 ==
3090 19:22:44.335288 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3091 19:22:44.338865 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3092 19:22:44.342132 == TX Byte 1 ==
3093 19:22:44.345556 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3094 19:22:44.348756 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3095 19:22:44.348838
3096 19:22:44.352316 [DATLAT]
3097 19:22:44.352396 Freq=1200, CH1 RK0
3098 19:22:44.352460
3099 19:22:44.355238 DATLAT Default: 0xd
3100 19:22:44.355318 0, 0xFFFF, sum = 0
3101 19:22:44.358650 1, 0xFFFF, sum = 0
3102 19:22:44.358731 2, 0xFFFF, sum = 0
3103 19:22:44.362536 3, 0xFFFF, sum = 0
3104 19:22:44.362618 4, 0xFFFF, sum = 0
3105 19:22:44.365693 5, 0xFFFF, sum = 0
3106 19:22:44.365775 6, 0xFFFF, sum = 0
3107 19:22:44.368682 7, 0xFFFF, sum = 0
3108 19:22:44.372197 8, 0xFFFF, sum = 0
3109 19:22:44.372279 9, 0xFFFF, sum = 0
3110 19:22:44.375654 10, 0xFFFF, sum = 0
3111 19:22:44.375737 11, 0x0, sum = 1
3112 19:22:44.378969 12, 0x0, sum = 2
3113 19:22:44.379063 13, 0x0, sum = 3
3114 19:22:44.379130 14, 0x0, sum = 4
3115 19:22:44.381931 best_step = 12
3116 19:22:44.382012
3117 19:22:44.382086 ==
3118 19:22:44.385247 Dram Type= 6, Freq= 0, CH_1, rank 0
3119 19:22:44.388670 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3120 19:22:44.388751 ==
3121 19:22:44.392056 RX Vref Scan: 1
3122 19:22:44.392137
3123 19:22:44.395436 Set Vref Range= 32 -> 127
3124 19:22:44.395517
3125 19:22:44.395580 RX Vref 32 -> 127, step: 1
3126 19:22:44.395640
3127 19:22:44.398595 RX Delay -29 -> 252, step: 4
3128 19:22:44.398676
3129 19:22:44.402309 Set Vref, RX VrefLevel [Byte0]: 32
3130 19:22:44.405370 [Byte1]: 32
3131 19:22:44.408938
3132 19:22:44.409019 Set Vref, RX VrefLevel [Byte0]: 33
3133 19:22:44.411752 [Byte1]: 33
3134 19:22:44.416444
3135 19:22:44.416525 Set Vref, RX VrefLevel [Byte0]: 34
3136 19:22:44.419953 [Byte1]: 34
3137 19:22:44.424688
3138 19:22:44.424769 Set Vref, RX VrefLevel [Byte0]: 35
3139 19:22:44.427968 [Byte1]: 35
3140 19:22:44.432715
3141 19:22:44.432796 Set Vref, RX VrefLevel [Byte0]: 36
3142 19:22:44.435799 [Byte1]: 36
3143 19:22:44.440505
3144 19:22:44.440586 Set Vref, RX VrefLevel [Byte0]: 37
3145 19:22:44.444118 [Byte1]: 37
3146 19:22:44.448246
3147 19:22:44.448357 Set Vref, RX VrefLevel [Byte0]: 38
3148 19:22:44.451961 [Byte1]: 38
3149 19:22:44.456289
3150 19:22:44.456380 Set Vref, RX VrefLevel [Byte0]: 39
3151 19:22:44.459668 [Byte1]: 39
3152 19:22:44.464150
3153 19:22:44.464232 Set Vref, RX VrefLevel [Byte0]: 40
3154 19:22:44.467500 [Byte1]: 40
3155 19:22:44.472440
3156 19:22:44.472521 Set Vref, RX VrefLevel [Byte0]: 41
3157 19:22:44.475508 [Byte1]: 41
3158 19:22:44.480250
3159 19:22:44.480334 Set Vref, RX VrefLevel [Byte0]: 42
3160 19:22:44.483551 [Byte1]: 42
3161 19:22:44.488013
3162 19:22:44.488094 Set Vref, RX VrefLevel [Byte0]: 43
3163 19:22:44.491520 [Byte1]: 43
3164 19:22:44.496401
3165 19:22:44.496508 Set Vref, RX VrefLevel [Byte0]: 44
3166 19:22:44.499429 [Byte1]: 44
3167 19:22:44.503914
3168 19:22:44.503995 Set Vref, RX VrefLevel [Byte0]: 45
3169 19:22:44.507406 [Byte1]: 45
3170 19:22:44.512141
3171 19:22:44.512223 Set Vref, RX VrefLevel [Byte0]: 46
3172 19:22:44.515424 [Byte1]: 46
3173 19:22:44.520474
3174 19:22:44.520555 Set Vref, RX VrefLevel [Byte0]: 47
3175 19:22:44.523631 [Byte1]: 47
3176 19:22:44.527935
3177 19:22:44.528017 Set Vref, RX VrefLevel [Byte0]: 48
3178 19:22:44.531524 [Byte1]: 48
3179 19:22:44.536124
3180 19:22:44.536204 Set Vref, RX VrefLevel [Byte0]: 49
3181 19:22:44.539549 [Byte1]: 49
3182 19:22:44.543965
3183 19:22:44.544046 Set Vref, RX VrefLevel [Byte0]: 50
3184 19:22:44.547108 [Byte1]: 50
3185 19:22:44.552400
3186 19:22:44.552481 Set Vref, RX VrefLevel [Byte0]: 51
3187 19:22:44.555323 [Byte1]: 51
3188 19:22:44.559919
3189 19:22:44.560000 Set Vref, RX VrefLevel [Byte0]: 52
3190 19:22:44.563324 [Byte1]: 52
3191 19:22:44.567708
3192 19:22:44.567789 Set Vref, RX VrefLevel [Byte0]: 53
3193 19:22:44.570963 [Byte1]: 53
3194 19:22:44.575911
3195 19:22:44.575992 Set Vref, RX VrefLevel [Byte0]: 54
3196 19:22:44.579086 [Byte1]: 54
3197 19:22:44.583917
3198 19:22:44.583999 Set Vref, RX VrefLevel [Byte0]: 55
3199 19:22:44.586995 [Byte1]: 55
3200 19:22:44.591808
3201 19:22:44.591889 Set Vref, RX VrefLevel [Byte0]: 56
3202 19:22:44.595397 [Byte1]: 56
3203 19:22:44.599698
3204 19:22:44.599779 Set Vref, RX VrefLevel [Byte0]: 57
3205 19:22:44.602946 [Byte1]: 57
3206 19:22:44.607500
3207 19:22:44.607581 Set Vref, RX VrefLevel [Byte0]: 58
3208 19:22:44.610732 [Byte1]: 58
3209 19:22:44.615659
3210 19:22:44.615739 Set Vref, RX VrefLevel [Byte0]: 59
3211 19:22:44.619010 [Byte1]: 59
3212 19:22:44.623311
3213 19:22:44.623392 Set Vref, RX VrefLevel [Byte0]: 60
3214 19:22:44.626987 [Byte1]: 60
3215 19:22:44.631237
3216 19:22:44.631318 Set Vref, RX VrefLevel [Byte0]: 61
3217 19:22:44.634945 [Byte1]: 61
3218 19:22:44.639427
3219 19:22:44.639508 Set Vref, RX VrefLevel [Byte0]: 62
3220 19:22:44.642808 [Byte1]: 62
3221 19:22:44.647648
3222 19:22:44.647732 Set Vref, RX VrefLevel [Byte0]: 63
3223 19:22:44.650759 [Byte1]: 63
3224 19:22:44.655213
3225 19:22:44.655294 Set Vref, RX VrefLevel [Byte0]: 64
3226 19:22:44.658793 [Byte1]: 64
3227 19:22:44.663112
3228 19:22:44.663193 Set Vref, RX VrefLevel [Byte0]: 65
3229 19:22:44.666714 [Byte1]: 65
3230 19:22:44.671667
3231 19:22:44.671748 Final RX Vref Byte 0 = 56 to rank0
3232 19:22:44.674592 Final RX Vref Byte 1 = 49 to rank0
3233 19:22:44.678486 Final RX Vref Byte 0 = 56 to rank1
3234 19:22:44.681146 Final RX Vref Byte 1 = 49 to rank1==
3235 19:22:44.684777 Dram Type= 6, Freq= 0, CH_1, rank 0
3236 19:22:44.691355 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3237 19:22:44.691462 ==
3238 19:22:44.691575 DQS Delay:
3239 19:22:44.691643 DQS0 = 0, DQS1 = 0
3240 19:22:44.694274 DQM Delay:
3241 19:22:44.694356 DQM0 = 115, DQM1 = 105
3242 19:22:44.698020 DQ Delay:
3243 19:22:44.700991 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3244 19:22:44.704395 DQ4 =114, DQ5 =124, DQ6 =120, DQ7 =114
3245 19:22:44.708077 DQ8 =86, DQ9 =94, DQ10 =108, DQ11 =98
3246 19:22:44.711486 DQ12 =112, DQ13 =116, DQ14 =114, DQ15 =118
3247 19:22:44.711567
3248 19:22:44.711632
3249 19:22:44.717889 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b1b, (MSB)MR19= 0x404, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
3250 19:22:44.721237 CH1 RK0: MR19=404, MR18=1B1B
3251 19:22:44.727883 CH1_RK0: MR19=0x404, MR18=0x1B1B, DQSOSC=399, MR23=63, INC=41, DEC=27
3252 19:22:44.727965
3253 19:22:44.731268 ----->DramcWriteLeveling(PI) begin...
3254 19:22:44.731351 ==
3255 19:22:44.734771 Dram Type= 6, Freq= 0, CH_1, rank 1
3256 19:22:44.738194 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3257 19:22:44.741205 ==
3258 19:22:44.741313 Write leveling (Byte 0): 23 => 23
3259 19:22:44.744685 Write leveling (Byte 1): 23 => 23
3260 19:22:44.747732 DramcWriteLeveling(PI) end<-----
3261 19:22:44.747814
3262 19:22:44.747878 ==
3263 19:22:44.751112 Dram Type= 6, Freq= 0, CH_1, rank 1
3264 19:22:44.758162 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3265 19:22:44.758244 ==
3266 19:22:44.758308 [Gating] SW mode calibration
3267 19:22:44.767808 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3268 19:22:44.771360 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3269 19:22:44.774129 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3270 19:22:44.780894 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3271 19:22:44.784239 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3272 19:22:44.787501 0 11 12 | B1->B0 | 3434 2e2e | 1 0 | (1 0) (0 1)
3273 19:22:44.794398 0 11 16 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
3274 19:22:44.798148 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3275 19:22:44.800803 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3276 19:22:44.807435 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3277 19:22:44.811233 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3278 19:22:44.814158 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3279 19:22:44.821115 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3280 19:22:44.824383 0 12 12 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
3281 19:22:44.827872 0 12 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3282 19:22:44.834189 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3283 19:22:44.837875 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3284 19:22:44.840813 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3285 19:22:44.847870 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3286 19:22:44.850805 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3287 19:22:44.854517 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3288 19:22:44.860758 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3289 19:22:44.863967 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3290 19:22:44.867486 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3291 19:22:44.874244 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3292 19:22:44.877380 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3293 19:22:44.880795 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3294 19:22:44.887173 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3295 19:22:44.890754 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3296 19:22:44.894437 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3297 19:22:44.897162 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3298 19:22:44.904082 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3299 19:22:44.907311 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3300 19:22:44.910772 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3301 19:22:44.917337 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3302 19:22:44.920740 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3303 19:22:44.924093 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3304 19:22:44.930588 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3305 19:22:44.933830 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3306 19:22:44.937351 Total UI for P1: 0, mck2ui 16
3307 19:22:44.940611 best dqsien dly found for B0: ( 0, 15, 12)
3308 19:22:44.944087 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3309 19:22:44.950433 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3310 19:22:44.950516 Total UI for P1: 0, mck2ui 16
3311 19:22:44.957474 best dqsien dly found for B1: ( 0, 15, 16)
3312 19:22:44.960707 best DQS0 dly(MCK, UI, PI) = (0, 15, 12)
3313 19:22:44.964312 best DQS1 dly(MCK, UI, PI) = (0, 15, 16)
3314 19:22:44.964394
3315 19:22:44.967162 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 12)
3316 19:22:44.970744 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 16)
3317 19:22:44.973976 [Gating] SW calibration Done
3318 19:22:44.974096 ==
3319 19:22:44.977012 Dram Type= 6, Freq= 0, CH_1, rank 1
3320 19:22:44.980409 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3321 19:22:44.980491 ==
3322 19:22:44.983884 RX Vref Scan: 0
3323 19:22:44.983965
3324 19:22:44.984029 RX Vref 0 -> 0, step: 1
3325 19:22:44.984089
3326 19:22:44.987237 RX Delay -40 -> 252, step: 8
3327 19:22:44.990659 iDelay=208, Bit 0, Center 119 (48 ~ 191) 144
3328 19:22:44.997274 iDelay=208, Bit 1, Center 115 (40 ~ 191) 152
3329 19:22:45.000609 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3330 19:22:45.003793 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3331 19:22:45.007181 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3332 19:22:45.010917 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3333 19:22:45.016898 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3334 19:22:45.020441 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3335 19:22:45.024025 iDelay=208, Bit 8, Center 91 (16 ~ 167) 152
3336 19:22:45.027189 iDelay=208, Bit 9, Center 91 (16 ~ 167) 152
3337 19:22:45.030968 iDelay=208, Bit 10, Center 107 (32 ~ 183) 152
3338 19:22:45.037309 iDelay=208, Bit 11, Center 99 (24 ~ 175) 152
3339 19:22:45.040808 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3340 19:22:45.044032 iDelay=208, Bit 13, Center 115 (40 ~ 191) 152
3341 19:22:45.047263 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3342 19:22:45.050562 iDelay=208, Bit 15, Center 111 (40 ~ 183) 144
3343 19:22:45.050649 ==
3344 19:22:45.054197 Dram Type= 6, Freq= 0, CH_1, rank 1
3345 19:22:45.060388 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3346 19:22:45.060474 ==
3347 19:22:45.060538 DQS Delay:
3348 19:22:45.063984 DQS0 = 0, DQS1 = 0
3349 19:22:45.064080 DQM Delay:
3350 19:22:45.066899 DQM0 = 117, DQM1 = 105
3351 19:22:45.066985 DQ Delay:
3352 19:22:45.070343 DQ0 =119, DQ1 =115, DQ2 =107, DQ3 =115
3353 19:22:45.074161 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3354 19:22:45.077425 DQ8 =91, DQ9 =91, DQ10 =107, DQ11 =99
3355 19:22:45.080608 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =111
3356 19:22:45.080678
3357 19:22:45.080740
3358 19:22:45.080804 ==
3359 19:22:45.083815 Dram Type= 6, Freq= 0, CH_1, rank 1
3360 19:22:45.086979 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3361 19:22:45.090412 ==
3362 19:22:45.090519
3363 19:22:45.090611
3364 19:22:45.090697 TX Vref Scan disable
3365 19:22:45.093749 == TX Byte 0 ==
3366 19:22:45.097065 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3367 19:22:45.100244 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3368 19:22:45.103763 == TX Byte 1 ==
3369 19:22:45.107149 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3370 19:22:45.110469 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3371 19:22:45.113594 ==
3372 19:22:45.113662 Dram Type= 6, Freq= 0, CH_1, rank 1
3373 19:22:45.120353 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3374 19:22:45.120449 ==
3375 19:22:45.131037 TX Vref=22, minBit 7, minWin=25, winSum=418
3376 19:22:45.134702 TX Vref=24, minBit 9, minWin=25, winSum=423
3377 19:22:45.138012 TX Vref=26, minBit 3, minWin=26, winSum=425
3378 19:22:45.141373 TX Vref=28, minBit 9, minWin=26, winSum=432
3379 19:22:45.144444 TX Vref=30, minBit 8, minWin=26, winSum=430
3380 19:22:45.147768 TX Vref=32, minBit 0, minWin=26, winSum=429
3381 19:22:45.154748 [TxChooseVref] Worse bit 9, Min win 26, Win sum 432, Final Vref 28
3382 19:22:45.154850
3383 19:22:45.157743 Final TX Range 1 Vref 28
3384 19:22:45.157822
3385 19:22:45.157913 ==
3386 19:22:45.161181 Dram Type= 6, Freq= 0, CH_1, rank 1
3387 19:22:45.164407 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3388 19:22:45.164505 ==
3389 19:22:45.164593
3390 19:22:45.164682
3391 19:22:45.167644 TX Vref Scan disable
3392 19:22:45.171249 == TX Byte 0 ==
3393 19:22:45.174538 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3394 19:22:45.178100 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3395 19:22:45.181187 == TX Byte 1 ==
3396 19:22:45.184364 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3397 19:22:45.187738 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3398 19:22:45.187835
3399 19:22:45.191090 [DATLAT]
3400 19:22:45.191186 Freq=1200, CH1 RK1
3401 19:22:45.191279
3402 19:22:45.194560 DATLAT Default: 0xc
3403 19:22:45.194661 0, 0xFFFF, sum = 0
3404 19:22:45.197893 1, 0xFFFF, sum = 0
3405 19:22:45.198007 2, 0xFFFF, sum = 0
3406 19:22:45.200915 3, 0xFFFF, sum = 0
3407 19:22:45.201013 4, 0xFFFF, sum = 0
3408 19:22:45.204316 5, 0xFFFF, sum = 0
3409 19:22:45.204414 6, 0xFFFF, sum = 0
3410 19:22:45.208008 7, 0xFFFF, sum = 0
3411 19:22:45.208107 8, 0xFFFF, sum = 0
3412 19:22:45.211095 9, 0xFFFF, sum = 0
3413 19:22:45.214306 10, 0xFFFF, sum = 0
3414 19:22:45.214382 11, 0x0, sum = 1
3415 19:22:45.214449 12, 0x0, sum = 2
3416 19:22:45.217763 13, 0x0, sum = 3
3417 19:22:45.217852 14, 0x0, sum = 4
3418 19:22:45.221331 best_step = 12
3419 19:22:45.221412
3420 19:22:45.221476 ==
3421 19:22:45.224655 Dram Type= 6, Freq= 0, CH_1, rank 1
3422 19:22:45.227941 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3423 19:22:45.228022 ==
3424 19:22:45.230995 RX Vref Scan: 0
3425 19:22:45.231076
3426 19:22:45.231140 RX Vref 0 -> 0, step: 1
3427 19:22:45.231200
3428 19:22:45.234544 RX Delay -29 -> 252, step: 4
3429 19:22:45.241259 iDelay=199, Bit 0, Center 114 (43 ~ 186) 144
3430 19:22:45.245016 iDelay=199, Bit 1, Center 110 (39 ~ 182) 144
3431 19:22:45.247778 iDelay=199, Bit 2, Center 106 (39 ~ 174) 136
3432 19:22:45.251239 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3433 19:22:45.254657 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144
3434 19:22:45.261288 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3435 19:22:45.264698 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3436 19:22:45.267716 iDelay=199, Bit 7, Center 114 (43 ~ 186) 144
3437 19:22:45.271171 iDelay=199, Bit 8, Center 86 (19 ~ 154) 136
3438 19:22:45.274367 iDelay=199, Bit 9, Center 92 (27 ~ 158) 132
3439 19:22:45.281237 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3440 19:22:45.284456 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3441 19:22:45.287929 iDelay=199, Bit 12, Center 114 (47 ~ 182) 136
3442 19:22:45.291202 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
3443 19:22:45.294121 iDelay=199, Bit 14, Center 112 (43 ~ 182) 140
3444 19:22:45.301142 iDelay=199, Bit 15, Center 110 (43 ~ 178) 136
3445 19:22:45.301218 ==
3446 19:22:45.304393 Dram Type= 6, Freq= 0, CH_1, rank 1
3447 19:22:45.307686 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3448 19:22:45.307781 ==
3449 19:22:45.307874 DQS Delay:
3450 19:22:45.311358 DQS0 = 0, DQS1 = 0
3451 19:22:45.311499 DQM Delay:
3452 19:22:45.314600 DQM0 = 114, DQM1 = 103
3453 19:22:45.314672 DQ Delay:
3454 19:22:45.317844 DQ0 =114, DQ1 =110, DQ2 =106, DQ3 =112
3455 19:22:45.320751 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =114
3456 19:22:45.324247 DQ8 =86, DQ9 =92, DQ10 =106, DQ11 =98
3457 19:22:45.327585 DQ12 =114, DQ13 =112, DQ14 =112, DQ15 =110
3458 19:22:45.327685
3459 19:22:45.327776
3460 19:22:45.337344 [DQSOSCAuto] RK1, (LSB)MR18= 0xa0a, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
3461 19:22:45.340991 CH1 RK1: MR19=404, MR18=A0A
3462 19:22:45.344113 CH1_RK1: MR19=0x404, MR18=0xA0A, DQSOSC=406, MR23=63, INC=39, DEC=26
3463 19:22:45.347686 [RxdqsGatingPostProcess] freq 1200
3464 19:22:45.354332 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3465 19:22:45.357739 Pre-setting of DQS Precalculation
3466 19:22:45.360829 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3467 19:22:45.370687 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3468 19:22:45.377130 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3469 19:22:45.377213
3470 19:22:45.377278
3471 19:22:45.380397 [Calibration Summary] 2400 Mbps
3472 19:22:45.380509 CH 0, Rank 0
3473 19:22:45.383741 SW Impedance : PASS
3474 19:22:45.383831 DUTY Scan : NO K
3475 19:22:45.386974 ZQ Calibration : PASS
3476 19:22:45.390637 Jitter Meter : NO K
3477 19:22:45.390718 CBT Training : PASS
3478 19:22:45.393530 Write leveling : PASS
3479 19:22:45.396872 RX DQS gating : PASS
3480 19:22:45.396953 RX DQ/DQS(RDDQC) : PASS
3481 19:22:45.400342 TX DQ/DQS : PASS
3482 19:22:45.403631 RX DATLAT : PASS
3483 19:22:45.403715 RX DQ/DQS(Engine): PASS
3484 19:22:45.407169 TX OE : NO K
3485 19:22:45.407251 All Pass.
3486 19:22:45.407316
3487 19:22:45.410838 CH 0, Rank 1
3488 19:22:45.410919 SW Impedance : PASS
3489 19:22:45.413610 DUTY Scan : NO K
3490 19:22:45.416823 ZQ Calibration : PASS
3491 19:22:45.416905 Jitter Meter : NO K
3492 19:22:45.419983 CBT Training : PASS
3493 19:22:45.423462 Write leveling : PASS
3494 19:22:45.423543 RX DQS gating : PASS
3495 19:22:45.426715 RX DQ/DQS(RDDQC) : PASS
3496 19:22:45.430078 TX DQ/DQS : PASS
3497 19:22:45.430159 RX DATLAT : PASS
3498 19:22:45.433141 RX DQ/DQS(Engine): PASS
3499 19:22:45.436620 TX OE : NO K
3500 19:22:45.436701 All Pass.
3501 19:22:45.436766
3502 19:22:45.436857 CH 1, Rank 0
3503 19:22:45.439768 SW Impedance : PASS
3504 19:22:45.443577 DUTY Scan : NO K
3505 19:22:45.443658 ZQ Calibration : PASS
3506 19:22:45.446419 Jitter Meter : NO K
3507 19:22:45.449802 CBT Training : PASS
3508 19:22:45.449883 Write leveling : PASS
3509 19:22:45.452983 RX DQS gating : PASS
3510 19:22:45.453064 RX DQ/DQS(RDDQC) : PASS
3511 19:22:45.456741 TX DQ/DQS : PASS
3512 19:22:45.459819 RX DATLAT : PASS
3513 19:22:45.459901 RX DQ/DQS(Engine): PASS
3514 19:22:45.463059 TX OE : NO K
3515 19:22:45.463141 All Pass.
3516 19:22:45.463205
3517 19:22:45.466203 CH 1, Rank 1
3518 19:22:45.466284 SW Impedance : PASS
3519 19:22:45.469645 DUTY Scan : NO K
3520 19:22:45.473190 ZQ Calibration : PASS
3521 19:22:45.473272 Jitter Meter : NO K
3522 19:22:45.476359 CBT Training : PASS
3523 19:22:45.479429 Write leveling : PASS
3524 19:22:45.479511 RX DQS gating : PASS
3525 19:22:45.483004 RX DQ/DQS(RDDQC) : PASS
3526 19:22:45.485981 TX DQ/DQS : PASS
3527 19:22:45.486103 RX DATLAT : PASS
3528 19:22:45.489489 RX DQ/DQS(Engine): PASS
3529 19:22:45.492815 TX OE : NO K
3530 19:22:45.492897 All Pass.
3531 19:22:45.492963
3532 19:22:45.495798 DramC Write-DBI off
3533 19:22:45.495880 PER_BANK_REFRESH: Hybrid Mode
3534 19:22:45.499364 TX_TRACKING: ON
3535 19:22:45.506016 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3536 19:22:45.512508 [FAST_K] Save calibration result to emmc
3537 19:22:45.515479 dramc_set_vcore_voltage set vcore to 650000
3538 19:22:45.515561 Read voltage for 600, 5
3539 19:22:45.518958 Vio18 = 0
3540 19:22:45.519040 Vcore = 650000
3541 19:22:45.519105 Vdram = 0
3542 19:22:45.522263 Vddq = 0
3543 19:22:45.522344 Vmddr = 0
3544 19:22:45.525731 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3545 19:22:45.532251 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3546 19:22:45.535214 MEM_TYPE=3, freq_sel=19
3547 19:22:45.538974 sv_algorithm_assistance_LP4_1600
3548 19:22:45.541822 ============ PULL DRAM RESETB DOWN ============
3549 19:22:45.545555 ========== PULL DRAM RESETB DOWN end =========
3550 19:22:45.552337 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3551 19:22:45.555178 ===================================
3552 19:22:45.555261 LPDDR4 DRAM CONFIGURATION
3553 19:22:45.558872 ===================================
3554 19:22:45.562399 EX_ROW_EN[0] = 0x0
3555 19:22:45.565100 EX_ROW_EN[1] = 0x0
3556 19:22:45.565183 LP4Y_EN = 0x0
3557 19:22:45.568385 WORK_FSP = 0x0
3558 19:22:45.568466 WL = 0x2
3559 19:22:45.572016 RL = 0x2
3560 19:22:45.572099 BL = 0x2
3561 19:22:45.575277 RPST = 0x0
3562 19:22:45.575359 RD_PRE = 0x0
3563 19:22:45.578463 WR_PRE = 0x1
3564 19:22:45.578545 WR_PST = 0x0
3565 19:22:45.581799 DBI_WR = 0x0
3566 19:22:45.581881 DBI_RD = 0x0
3567 19:22:45.585102 OTF = 0x1
3568 19:22:45.588657 ===================================
3569 19:22:45.592091 ===================================
3570 19:22:45.592175 ANA top config
3571 19:22:45.594642 ===================================
3572 19:22:45.598002 DLL_ASYNC_EN = 0
3573 19:22:45.601212 ALL_SLAVE_EN = 1
3574 19:22:45.604607 NEW_RANK_MODE = 1
3575 19:22:45.604691 DLL_IDLE_MODE = 1
3576 19:22:45.608251 LP45_APHY_COMB_EN = 1
3577 19:22:45.611464 TX_ODT_DIS = 1
3578 19:22:45.614750 NEW_8X_MODE = 1
3579 19:22:45.617837 ===================================
3580 19:22:45.621296 ===================================
3581 19:22:45.624511 data_rate = 1200
3582 19:22:45.624595 CKR = 1
3583 19:22:45.628013 DQ_P2S_RATIO = 8
3584 19:22:45.631456 ===================================
3585 19:22:45.634888 CA_P2S_RATIO = 8
3586 19:22:45.638003 DQ_CA_OPEN = 0
3587 19:22:45.641114 DQ_SEMI_OPEN = 0
3588 19:22:45.644612 CA_SEMI_OPEN = 0
3589 19:22:45.644694 CA_FULL_RATE = 0
3590 19:22:45.648063 DQ_CKDIV4_EN = 1
3591 19:22:45.651076 CA_CKDIV4_EN = 1
3592 19:22:45.654528 CA_PREDIV_EN = 0
3593 19:22:45.657739 PH8_DLY = 0
3594 19:22:45.660986 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3595 19:22:45.661072 DQ_AAMCK_DIV = 4
3596 19:22:45.664124 CA_AAMCK_DIV = 4
3597 19:22:45.667658 CA_ADMCK_DIV = 4
3598 19:22:45.670751 DQ_TRACK_CA_EN = 0
3599 19:22:45.673963 CA_PICK = 600
3600 19:22:45.677505 CA_MCKIO = 600
3601 19:22:45.680913 MCKIO_SEMI = 0
3602 19:22:45.680995 PLL_FREQ = 2288
3603 19:22:45.684161 DQ_UI_PI_RATIO = 32
3604 19:22:45.687516 CA_UI_PI_RATIO = 0
3605 19:22:45.690808 ===================================
3606 19:22:45.694222 ===================================
3607 19:22:45.697103 memory_type:LPDDR4
3608 19:22:45.700321 GP_NUM : 10
3609 19:22:45.700420 SRAM_EN : 1
3610 19:22:45.703818 MD32_EN : 0
3611 19:22:45.707159 ===================================
3612 19:22:45.707242 [ANA_INIT] >>>>>>>>>>>>>>
3613 19:22:45.710294 <<<<<< [CONFIGURE PHASE]: ANA_TX
3614 19:22:45.713650 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3615 19:22:45.716943 ===================================
3616 19:22:45.720347 data_rate = 1200,PCW = 0X5800
3617 19:22:45.723622 ===================================
3618 19:22:45.726806 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3619 19:22:45.733543 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3620 19:22:45.740077 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3621 19:22:45.743625 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3622 19:22:45.746539 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3623 19:22:45.749829 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3624 19:22:45.753724 [ANA_INIT] flow start
3625 19:22:45.753806 [ANA_INIT] PLL >>>>>>>>
3626 19:22:45.756670 [ANA_INIT] PLL <<<<<<<<
3627 19:22:45.759887 [ANA_INIT] MIDPI >>>>>>>>
3628 19:22:45.763183 [ANA_INIT] MIDPI <<<<<<<<
3629 19:22:45.763266 [ANA_INIT] DLL >>>>>>>>
3630 19:22:45.766307 [ANA_INIT] flow end
3631 19:22:45.769714 ============ LP4 DIFF to SE enter ============
3632 19:22:45.772910 ============ LP4 DIFF to SE exit ============
3633 19:22:45.776683 [ANA_INIT] <<<<<<<<<<<<<
3634 19:22:45.779519 [Flow] Enable top DCM control >>>>>
3635 19:22:45.782933 [Flow] Enable top DCM control <<<<<
3636 19:22:45.786263 Enable DLL master slave shuffle
3637 19:22:45.792968 ==============================================================
3638 19:22:45.793051 Gating Mode config
3639 19:22:45.799817 ==============================================================
3640 19:22:45.799900 Config description:
3641 19:22:45.809169 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3642 19:22:45.815811 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3643 19:22:45.823025 SELPH_MODE 0: By rank 1: By Phase
3644 19:22:45.825638 ==============================================================
3645 19:22:45.828878 GAT_TRACK_EN = 1
3646 19:22:45.832359 RX_GATING_MODE = 2
3647 19:22:45.835511 RX_GATING_TRACK_MODE = 2
3648 19:22:45.838896 SELPH_MODE = 1
3649 19:22:45.842175 PICG_EARLY_EN = 1
3650 19:22:45.845923 VALID_LAT_VALUE = 1
3651 19:22:45.852337 ==============================================================
3652 19:22:45.855919 Enter into Gating configuration >>>>
3653 19:22:45.858742 Exit from Gating configuration <<<<
3654 19:22:45.858824 Enter into DVFS_PRE_config >>>>>
3655 19:22:45.872174 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3656 19:22:45.875533 Exit from DVFS_PRE_config <<<<<
3657 19:22:45.878610 Enter into PICG configuration >>>>
3658 19:22:45.881781 Exit from PICG configuration <<<<
3659 19:22:45.881862 [RX_INPUT] configuration >>>>>
3660 19:22:45.885138 [RX_INPUT] configuration <<<<<
3661 19:22:45.892144 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3662 19:22:45.898646 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3663 19:22:45.902254 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3664 19:22:45.908631 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3665 19:22:45.914913 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3666 19:22:45.922007 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3667 19:22:45.925135 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3668 19:22:45.928121 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3669 19:22:45.934733 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3670 19:22:45.938323 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3671 19:22:45.941279 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3672 19:22:45.948130 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3673 19:22:45.951265 ===================================
3674 19:22:45.951348 LPDDR4 DRAM CONFIGURATION
3675 19:22:45.954591 ===================================
3676 19:22:45.957874 EX_ROW_EN[0] = 0x0
3677 19:22:45.957956 EX_ROW_EN[1] = 0x0
3678 19:22:45.961016 LP4Y_EN = 0x0
3679 19:22:45.964817 WORK_FSP = 0x0
3680 19:22:45.964898 WL = 0x2
3681 19:22:45.967858 RL = 0x2
3682 19:22:45.967939 BL = 0x2
3683 19:22:45.970846 RPST = 0x0
3684 19:22:45.970927 RD_PRE = 0x0
3685 19:22:45.974364 WR_PRE = 0x1
3686 19:22:45.974446 WR_PST = 0x0
3687 19:22:45.977435 DBI_WR = 0x0
3688 19:22:45.977517 DBI_RD = 0x0
3689 19:22:45.981206 OTF = 0x1
3690 19:22:45.984374 ===================================
3691 19:22:45.987697 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3692 19:22:45.990883 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3693 19:22:45.997634 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3694 19:22:46.000860 ===================================
3695 19:22:46.000943 LPDDR4 DRAM CONFIGURATION
3696 19:22:46.004314 ===================================
3697 19:22:46.007466 EX_ROW_EN[0] = 0x10
3698 19:22:46.007548 EX_ROW_EN[1] = 0x0
3699 19:22:46.010674 LP4Y_EN = 0x0
3700 19:22:46.013990 WORK_FSP = 0x0
3701 19:22:46.014110 WL = 0x2
3702 19:22:46.017371 RL = 0x2
3703 19:22:46.017452 BL = 0x2
3704 19:22:46.020526 RPST = 0x0
3705 19:22:46.020608 RD_PRE = 0x0
3706 19:22:46.024010 WR_PRE = 0x1
3707 19:22:46.024092 WR_PST = 0x0
3708 19:22:46.027350 DBI_WR = 0x0
3709 19:22:46.027432 DBI_RD = 0x0
3710 19:22:46.030621 OTF = 0x1
3711 19:22:46.033897 ===================================
3712 19:22:46.040288 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3713 19:22:46.043609 nWR fixed to 30
3714 19:22:46.043694 [ModeRegInit_LP4] CH0 RK0
3715 19:22:46.046788 [ModeRegInit_LP4] CH0 RK1
3716 19:22:46.050273 [ModeRegInit_LP4] CH1 RK0
3717 19:22:46.053382 [ModeRegInit_LP4] CH1 RK1
3718 19:22:46.053463 match AC timing 16
3719 19:22:46.060065 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3720 19:22:46.063676 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3721 19:22:46.067191 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3722 19:22:46.073434 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3723 19:22:46.077030 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3724 19:22:46.077111 ==
3725 19:22:46.080087 Dram Type= 6, Freq= 0, CH_0, rank 0
3726 19:22:46.083457 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3727 19:22:46.083539 ==
3728 19:22:46.090268 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3729 19:22:46.096561 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3730 19:22:46.099866 [CA 0] Center 35 (5~66) winsize 62
3731 19:22:46.103381 [CA 1] Center 35 (5~66) winsize 62
3732 19:22:46.106626 [CA 2] Center 34 (4~65) winsize 62
3733 19:22:46.109961 [CA 3] Center 34 (3~65) winsize 63
3734 19:22:46.113154 [CA 4] Center 33 (3~64) winsize 62
3735 19:22:46.116426 [CA 5] Center 33 (3~64) winsize 62
3736 19:22:46.116507
3737 19:22:46.119587 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3738 19:22:46.119669
3739 19:22:46.122811 [CATrainingPosCal] consider 1 rank data
3740 19:22:46.126633 u2DelayCellTimex100 = 270/100 ps
3741 19:22:46.129376 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3742 19:22:46.133350 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3743 19:22:46.136403 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3744 19:22:46.139513 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3745 19:22:46.142863 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3746 19:22:46.145989 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3747 19:22:46.146110
3748 19:22:46.152733 CA PerBit enable=1, Macro0, CA PI delay=33
3749 19:22:46.152814
3750 19:22:46.155760 [CBTSetCACLKResult] CA Dly = 33
3751 19:22:46.155842 CS Dly: 5 (0~36)
3752 19:22:46.155906 ==
3753 19:22:46.159216 Dram Type= 6, Freq= 0, CH_0, rank 1
3754 19:22:46.162556 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3755 19:22:46.162638 ==
3756 19:22:46.169050 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3757 19:22:46.175601 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3758 19:22:46.179145 [CA 0] Center 35 (5~66) winsize 62
3759 19:22:46.182323 [CA 1] Center 35 (5~66) winsize 62
3760 19:22:46.185891 [CA 2] Center 34 (4~65) winsize 62
3761 19:22:46.189008 [CA 3] Center 34 (4~65) winsize 62
3762 19:22:46.192243 [CA 4] Center 33 (3~64) winsize 62
3763 19:22:46.196062 [CA 5] Center 33 (3~64) winsize 62
3764 19:22:46.196143
3765 19:22:46.199105 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3766 19:22:46.199195
3767 19:22:46.202222 [CATrainingPosCal] consider 2 rank data
3768 19:22:46.205865 u2DelayCellTimex100 = 270/100 ps
3769 19:22:46.208995 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3770 19:22:46.212150 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3771 19:22:46.215566 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3772 19:22:46.218902 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3773 19:22:46.225576 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3774 19:22:46.228542 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3775 19:22:46.228624
3776 19:22:46.231949 CA PerBit enable=1, Macro0, CA PI delay=33
3777 19:22:46.232031
3778 19:22:46.235348 [CBTSetCACLKResult] CA Dly = 33
3779 19:22:46.235430 CS Dly: 5 (0~36)
3780 19:22:46.235494
3781 19:22:46.238346 ----->DramcWriteLeveling(PI) begin...
3782 19:22:46.238463 ==
3783 19:22:46.241780 Dram Type= 6, Freq= 0, CH_0, rank 0
3784 19:22:46.248438 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3785 19:22:46.248536 ==
3786 19:22:46.251935 Write leveling (Byte 0): 31 => 31
3787 19:22:46.255140 Write leveling (Byte 1): 31 => 31
3788 19:22:46.255222 DramcWriteLeveling(PI) end<-----
3789 19:22:46.258622
3790 19:22:46.258712 ==
3791 19:22:46.261747 Dram Type= 6, Freq= 0, CH_0, rank 0
3792 19:22:46.264804 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3793 19:22:46.264916 ==
3794 19:22:46.268377 [Gating] SW mode calibration
3795 19:22:46.274832 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3796 19:22:46.278764 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3797 19:22:46.284510 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3798 19:22:46.287959 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3799 19:22:46.291412 0 5 8 | B1->B0 | 3232 3030 | 1 0 | (1 0) (0 1)
3800 19:22:46.297861 0 5 12 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
3801 19:22:46.301211 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3802 19:22:46.304484 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3803 19:22:46.311223 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3804 19:22:46.314398 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3805 19:22:46.317941 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3806 19:22:46.324564 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3807 19:22:46.327464 0 6 8 | B1->B0 | 2b2b 3434 | 0 0 | (0 0) (0 0)
3808 19:22:46.331227 0 6 12 | B1->B0 | 3c3c 4646 | 1 0 | (0 0) (0 0)
3809 19:22:46.337941 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3810 19:22:46.340967 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3811 19:22:46.344395 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3812 19:22:46.350863 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3813 19:22:46.354290 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3814 19:22:46.357452 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3815 19:22:46.363739 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3816 19:22:46.367280 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3817 19:22:46.370585 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3818 19:22:46.377268 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3819 19:22:46.380707 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3820 19:22:46.383880 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3821 19:22:46.390297 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3822 19:22:46.394032 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3823 19:22:46.397100 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3824 19:22:46.403637 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3825 19:22:46.407203 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3826 19:22:46.410735 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3827 19:22:46.416959 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3828 19:22:46.420486 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3829 19:22:46.423425 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3830 19:22:46.429883 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3831 19:22:46.433358 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
3832 19:22:46.436675 Total UI for P1: 0, mck2ui 16
3833 19:22:46.440253 best dqsien dly found for B0: ( 0, 9, 6)
3834 19:22:46.443620 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3835 19:22:46.446617 Total UI for P1: 0, mck2ui 16
3836 19:22:46.449927 best dqsien dly found for B1: ( 0, 9, 10)
3837 19:22:46.453174 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
3838 19:22:46.456534 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
3839 19:22:46.456616
3840 19:22:46.462940 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
3841 19:22:46.466428 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
3842 19:22:46.469546 [Gating] SW calibration Done
3843 19:22:46.469627 ==
3844 19:22:46.472983 Dram Type= 6, Freq= 0, CH_0, rank 0
3845 19:22:46.476298 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3846 19:22:46.476381 ==
3847 19:22:46.476446 RX Vref Scan: 0
3848 19:22:46.476506
3849 19:22:46.479926 RX Vref 0 -> 0, step: 1
3850 19:22:46.480007
3851 19:22:46.482739 RX Delay -230 -> 252, step: 16
3852 19:22:46.486350 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3853 19:22:46.489423 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
3854 19:22:46.496031 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
3855 19:22:46.499687 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3856 19:22:46.503301 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
3857 19:22:46.505949 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
3858 19:22:46.512394 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3859 19:22:46.515700 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3860 19:22:46.519177 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3861 19:22:46.522844 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3862 19:22:46.529142 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3863 19:22:46.532572 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3864 19:22:46.535807 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3865 19:22:46.539059 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3866 19:22:46.545456 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3867 19:22:46.549189 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3868 19:22:46.549270 ==
3869 19:22:46.552409 Dram Type= 6, Freq= 0, CH_0, rank 0
3870 19:22:46.555614 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3871 19:22:46.555696 ==
3872 19:22:46.559041 DQS Delay:
3873 19:22:46.559122 DQS0 = 0, DQS1 = 0
3874 19:22:46.559186 DQM Delay:
3875 19:22:46.561957 DQM0 = 38, DQM1 = 33
3876 19:22:46.562123 DQ Delay:
3877 19:22:46.565801 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
3878 19:22:46.569044 DQ4 =49, DQ5 =25, DQ6 =49, DQ7 =49
3879 19:22:46.572110 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3880 19:22:46.575515 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3881 19:22:46.575596
3882 19:22:46.575660
3883 19:22:46.575720 ==
3884 19:22:46.578492 Dram Type= 6, Freq= 0, CH_0, rank 0
3885 19:22:46.585094 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3886 19:22:46.585176 ==
3887 19:22:46.585241
3888 19:22:46.585301
3889 19:22:46.585358 TX Vref Scan disable
3890 19:22:46.588959 == TX Byte 0 ==
3891 19:22:46.592328 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
3892 19:22:46.598793 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
3893 19:22:46.598876 == TX Byte 1 ==
3894 19:22:46.602282 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
3895 19:22:46.609345 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
3896 19:22:46.609427 ==
3897 19:22:46.611989 Dram Type= 6, Freq= 0, CH_0, rank 0
3898 19:22:46.615366 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3899 19:22:46.615449 ==
3900 19:22:46.615514
3901 19:22:46.615575
3902 19:22:46.618595 TX Vref Scan disable
3903 19:22:46.622377 == TX Byte 0 ==
3904 19:22:46.625363 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
3905 19:22:46.628399 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
3906 19:22:46.631815 == TX Byte 1 ==
3907 19:22:46.635159 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3908 19:22:46.638294 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3909 19:22:46.638377
3910 19:22:46.638442 [DATLAT]
3911 19:22:46.641567 Freq=600, CH0 RK0
3912 19:22:46.641649
3913 19:22:46.645042 DATLAT Default: 0x9
3914 19:22:46.645124 0, 0xFFFF, sum = 0
3915 19:22:46.647965 1, 0xFFFF, sum = 0
3916 19:22:46.648048 2, 0xFFFF, sum = 0
3917 19:22:46.651537 3, 0xFFFF, sum = 0
3918 19:22:46.651620 4, 0xFFFF, sum = 0
3919 19:22:46.654996 5, 0xFFFF, sum = 0
3920 19:22:46.655079 6, 0xFFFF, sum = 0
3921 19:22:46.658086 7, 0x0, sum = 1
3922 19:22:46.658170 8, 0x0, sum = 2
3923 19:22:46.661566 9, 0x0, sum = 3
3924 19:22:46.661650 10, 0x0, sum = 4
3925 19:22:46.661716 best_step = 8
3926 19:22:46.661777
3927 19:22:46.664567 ==
3928 19:22:46.668073 Dram Type= 6, Freq= 0, CH_0, rank 0
3929 19:22:46.671233 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3930 19:22:46.671315 ==
3931 19:22:46.671380 RX Vref Scan: 1
3932 19:22:46.671441
3933 19:22:46.675225 RX Vref 0 -> 0, step: 1
3934 19:22:46.675307
3935 19:22:46.678354 RX Delay -195 -> 252, step: 8
3936 19:22:46.678436
3937 19:22:46.681077 Set Vref, RX VrefLevel [Byte0]: 52
3938 19:22:46.684489 [Byte1]: 46
3939 19:22:46.687505
3940 19:22:46.687587 Final RX Vref Byte 0 = 52 to rank0
3941 19:22:46.691237 Final RX Vref Byte 1 = 46 to rank0
3942 19:22:46.694250 Final RX Vref Byte 0 = 52 to rank1
3943 19:22:46.697465 Final RX Vref Byte 1 = 46 to rank1==
3944 19:22:46.700905 Dram Type= 6, Freq= 0, CH_0, rank 0
3945 19:22:46.707509 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3946 19:22:46.707618 ==
3947 19:22:46.707711 DQS Delay:
3948 19:22:46.707802 DQS0 = 0, DQS1 = 0
3949 19:22:46.711023 DQM Delay:
3950 19:22:46.711106 DQM0 = 39, DQM1 = 30
3951 19:22:46.713963 DQ Delay:
3952 19:22:46.717199 DQ0 =36, DQ1 =40, DQ2 =40, DQ3 =36
3953 19:22:46.720588 DQ4 =40, DQ5 =28, DQ6 =48, DQ7 =48
3954 19:22:46.723699 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
3955 19:22:46.727722 DQ12 =36, DQ13 =40, DQ14 =40, DQ15 =40
3956 19:22:46.727804
3957 19:22:46.727868
3958 19:22:46.733939 [DQSOSCAuto] RK0, (LSB)MR18= 0x5757, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
3959 19:22:46.737341 CH0 RK0: MR19=808, MR18=5757
3960 19:22:46.743798 CH0_RK0: MR19=0x808, MR18=0x5757, DQSOSC=393, MR23=63, INC=169, DEC=113
3961 19:22:46.743881
3962 19:22:46.747229 ----->DramcWriteLeveling(PI) begin...
3963 19:22:46.747313 ==
3964 19:22:46.750422 Dram Type= 6, Freq= 0, CH_0, rank 1
3965 19:22:46.753473 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3966 19:22:46.753556 ==
3967 19:22:46.756811 Write leveling (Byte 0): 32 => 32
3968 19:22:46.760215 Write leveling (Byte 1): 28 => 28
3969 19:22:46.763678 DramcWriteLeveling(PI) end<-----
3970 19:22:46.763760
3971 19:22:46.763825 ==
3972 19:22:46.767138 Dram Type= 6, Freq= 0, CH_0, rank 1
3973 19:22:46.770347 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3974 19:22:46.773512 ==
3975 19:22:46.773594 [Gating] SW mode calibration
3976 19:22:46.780418 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3977 19:22:46.786435 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3978 19:22:46.790161 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3979 19:22:46.796726 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3980 19:22:46.799797 0 5 8 | B1->B0 | 3232 2f2f | 1 1 | (1 0) (1 0)
3981 19:22:46.803544 0 5 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
3982 19:22:46.809585 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3983 19:22:46.812874 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3984 19:22:46.816409 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3985 19:22:46.822732 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3986 19:22:46.826354 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3987 19:22:46.829715 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3988 19:22:46.835866 0 6 8 | B1->B0 | 2929 3737 | 0 0 | (0 0) (0 0)
3989 19:22:46.839521 0 6 12 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
3990 19:22:46.842838 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3991 19:22:46.849314 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3992 19:22:46.852624 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3993 19:22:46.856133 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3994 19:22:46.862387 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3995 19:22:46.866046 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3996 19:22:46.869337 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 19:22:46.875971 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3998 19:22:46.879264 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 19:22:46.882161 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 19:22:46.889003 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 19:22:46.892105 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 19:22:46.896024 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 19:22:46.902417 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 19:22:46.905368 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 19:22:46.908521 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 19:22:46.915436 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 19:22:46.918598 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 19:22:46.921966 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 19:22:46.928668 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 19:22:46.931939 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 19:22:46.935536 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4012 19:22:46.941716 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 19:22:46.945477 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4014 19:22:46.948475 Total UI for P1: 0, mck2ui 16
4015 19:22:46.951851 best dqsien dly found for B0: ( 0, 9, 10)
4016 19:22:46.955153 Total UI for P1: 0, mck2ui 16
4017 19:22:46.958461 best dqsien dly found for B1: ( 0, 9, 10)
4018 19:22:46.961678 best DQS0 dly(MCK, UI, PI) = (0, 9, 10)
4019 19:22:46.964972 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
4020 19:22:46.965054
4021 19:22:46.968509 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 10)
4022 19:22:46.971657 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
4023 19:22:46.975064 [Gating] SW calibration Done
4024 19:22:46.975145 ==
4025 19:22:46.978182 Dram Type= 6, Freq= 0, CH_0, rank 1
4026 19:22:46.981314 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4027 19:22:46.985011 ==
4028 19:22:46.985093 RX Vref Scan: 0
4029 19:22:46.985157
4030 19:22:46.988085 RX Vref 0 -> 0, step: 1
4031 19:22:46.988166
4032 19:22:46.991270 RX Delay -230 -> 252, step: 16
4033 19:22:46.994798 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4034 19:22:46.998247 iDelay=218, Bit 1, Center 41 (-134 ~ 217) 352
4035 19:22:47.001246 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4036 19:22:47.007781 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4037 19:22:47.011019 iDelay=218, Bit 4, Center 41 (-134 ~ 217) 352
4038 19:22:47.014485 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4039 19:22:47.017634 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4040 19:22:47.020869 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4041 19:22:47.027578 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4042 19:22:47.030832 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4043 19:22:47.034265 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4044 19:22:47.037449 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4045 19:22:47.043906 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4046 19:22:47.047760 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4047 19:22:47.050501 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4048 19:22:47.053948 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4049 19:22:47.057546 ==
4050 19:22:47.060520 Dram Type= 6, Freq= 0, CH_0, rank 1
4051 19:22:47.063787 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4052 19:22:47.063869 ==
4053 19:22:47.063933 DQS Delay:
4054 19:22:47.067245 DQS0 = 0, DQS1 = 0
4055 19:22:47.067326 DQM Delay:
4056 19:22:47.070704 DQM0 = 39, DQM1 = 31
4057 19:22:47.070785 DQ Delay:
4058 19:22:47.073779 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4059 19:22:47.077252 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4060 19:22:47.080232 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4061 19:22:47.083602 DQ12 =41, DQ13 =33, DQ14 =33, DQ15 =41
4062 19:22:47.083683
4063 19:22:47.083747
4064 19:22:47.083806 ==
4065 19:22:47.086981 Dram Type= 6, Freq= 0, CH_0, rank 1
4066 19:22:47.090840 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4067 19:22:47.090922 ==
4068 19:22:47.090987
4069 19:22:47.091047
4070 19:22:47.093390 TX Vref Scan disable
4071 19:22:47.097340 == TX Byte 0 ==
4072 19:22:47.100041 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4073 19:22:47.103498 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4074 19:22:47.106919 == TX Byte 1 ==
4075 19:22:47.109935 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4076 19:22:47.113394 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4077 19:22:47.113476 ==
4078 19:22:47.116861 Dram Type= 6, Freq= 0, CH_0, rank 1
4079 19:22:47.123195 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4080 19:22:47.123276 ==
4081 19:22:47.123341
4082 19:22:47.123401
4083 19:22:47.123458 TX Vref Scan disable
4084 19:22:47.127837 == TX Byte 0 ==
4085 19:22:47.131042 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4086 19:22:47.137659 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4087 19:22:47.137741 == TX Byte 1 ==
4088 19:22:47.140989 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4089 19:22:47.147689 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4090 19:22:47.147770
4091 19:22:47.147835 [DATLAT]
4092 19:22:47.147895 Freq=600, CH0 RK1
4093 19:22:47.147953
4094 19:22:47.150902 DATLAT Default: 0x8
4095 19:22:47.150983 0, 0xFFFF, sum = 0
4096 19:22:47.154355 1, 0xFFFF, sum = 0
4097 19:22:47.157381 2, 0xFFFF, sum = 0
4098 19:22:47.157464 3, 0xFFFF, sum = 0
4099 19:22:47.161018 4, 0xFFFF, sum = 0
4100 19:22:47.161100 5, 0xFFFF, sum = 0
4101 19:22:47.164340 6, 0xFFFF, sum = 0
4102 19:22:47.164422 7, 0x0, sum = 1
4103 19:22:47.164488 8, 0x0, sum = 2
4104 19:22:47.167359 9, 0x0, sum = 3
4105 19:22:47.167444 10, 0x0, sum = 4
4106 19:22:47.170838 best_step = 8
4107 19:22:47.170919
4108 19:22:47.170989 ==
4109 19:22:47.174098 Dram Type= 6, Freq= 0, CH_0, rank 1
4110 19:22:47.177333 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4111 19:22:47.177416 ==
4112 19:22:47.180629 RX Vref Scan: 0
4113 19:22:47.180710
4114 19:22:47.180775 RX Vref 0 -> 0, step: 1
4115 19:22:47.180836
4116 19:22:47.183860 RX Delay -195 -> 252, step: 8
4117 19:22:47.191337 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4118 19:22:47.195209 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4119 19:22:47.198158 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4120 19:22:47.201424 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4121 19:22:47.208246 iDelay=205, Bit 4, Center 44 (-115 ~ 204) 320
4122 19:22:47.211528 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4123 19:22:47.214905 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4124 19:22:47.217848 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4125 19:22:47.224837 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4126 19:22:47.227730 iDelay=205, Bit 9, Center 16 (-131 ~ 164) 296
4127 19:22:47.231227 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4128 19:22:47.234214 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4129 19:22:47.241096 iDelay=205, Bit 12, Center 40 (-107 ~ 188) 296
4130 19:22:47.244469 iDelay=205, Bit 13, Center 36 (-115 ~ 188) 304
4131 19:22:47.247867 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4132 19:22:47.251365 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4133 19:22:47.251447 ==
4134 19:22:47.254210 Dram Type= 6, Freq= 0, CH_0, rank 1
4135 19:22:47.260747 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4136 19:22:47.260829 ==
4137 19:22:47.260894 DQS Delay:
4138 19:22:47.264165 DQS0 = 0, DQS1 = 0
4139 19:22:47.264246 DQM Delay:
4140 19:22:47.264310 DQM0 = 41, DQM1 = 32
4141 19:22:47.267369 DQ Delay:
4142 19:22:47.270551 DQ0 =40, DQ1 =40, DQ2 =40, DQ3 =36
4143 19:22:47.273845 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4144 19:22:47.277193 DQ8 =20, DQ9 =16, DQ10 =32, DQ11 =24
4145 19:22:47.280512 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4146 19:22:47.280593
4147 19:22:47.280657
4148 19:22:47.287533 [DQSOSCAuto] RK1, (LSB)MR18= 0x6b6b, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
4149 19:22:47.290526 CH0 RK1: MR19=808, MR18=6B6B
4150 19:22:47.297468 CH0_RK1: MR19=0x808, MR18=0x6B6B, DQSOSC=389, MR23=63, INC=173, DEC=115
4151 19:22:47.300525 [RxdqsGatingPostProcess] freq 600
4152 19:22:47.303628 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4153 19:22:47.306956 Pre-setting of DQS Precalculation
4154 19:22:47.313811 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4155 19:22:47.313920 ==
4156 19:22:47.317132 Dram Type= 6, Freq= 0, CH_1, rank 0
4157 19:22:47.320091 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4158 19:22:47.320173 ==
4159 19:22:47.326967 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4160 19:22:47.333636 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4161 19:22:47.336689 [CA 0] Center 35 (5~66) winsize 62
4162 19:22:47.339945 [CA 1] Center 35 (5~65) winsize 61
4163 19:22:47.343367 [CA 2] Center 33 (3~64) winsize 62
4164 19:22:47.346928 [CA 3] Center 33 (3~64) winsize 62
4165 19:22:47.349995 [CA 4] Center 33 (2~64) winsize 63
4166 19:22:47.353431 [CA 5] Center 33 (2~64) winsize 63
4167 19:22:47.353513
4168 19:22:47.356868 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4169 19:22:47.356950
4170 19:22:47.359943 [CATrainingPosCal] consider 1 rank data
4171 19:22:47.363295 u2DelayCellTimex100 = 270/100 ps
4172 19:22:47.366847 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4173 19:22:47.369965 CA1 delay=35 (5~65),Diff = 2 PI (19 cell)
4174 19:22:47.373187 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4175 19:22:47.376630 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4176 19:22:47.380081 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4177 19:22:47.382959 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4178 19:22:47.383041
4179 19:22:47.390003 CA PerBit enable=1, Macro0, CA PI delay=33
4180 19:22:47.390125
4181 19:22:47.390190 [CBTSetCACLKResult] CA Dly = 33
4182 19:22:47.392923 CS Dly: 4 (0~35)
4183 19:22:47.393004 ==
4184 19:22:47.396407 Dram Type= 6, Freq= 0, CH_1, rank 1
4185 19:22:47.399623 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4186 19:22:47.399706 ==
4187 19:22:47.406471 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4188 19:22:47.413165 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4189 19:22:47.416159 [CA 0] Center 35 (5~66) winsize 62
4190 19:22:47.419601 [CA 1] Center 34 (4~65) winsize 62
4191 19:22:47.422752 [CA 2] Center 33 (3~64) winsize 62
4192 19:22:47.426055 [CA 3] Center 33 (2~64) winsize 63
4193 19:22:47.429522 [CA 4] Center 32 (2~63) winsize 62
4194 19:22:47.433131 [CA 5] Center 32 (2~63) winsize 62
4195 19:22:47.433213
4196 19:22:47.436067 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4197 19:22:47.436149
4198 19:22:47.439091 [CATrainingPosCal] consider 2 rank data
4199 19:22:47.442541 u2DelayCellTimex100 = 270/100 ps
4200 19:22:47.445872 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4201 19:22:47.449002 CA1 delay=35 (5~65),Diff = 3 PI (28 cell)
4202 19:22:47.452734 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4203 19:22:47.455831 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4204 19:22:47.459224 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4205 19:22:47.465941 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4206 19:22:47.466084
4207 19:22:47.469161 CA PerBit enable=1, Macro0, CA PI delay=32
4208 19:22:47.469242
4209 19:22:47.472225 [CBTSetCACLKResult] CA Dly = 32
4210 19:22:47.472306 CS Dly: 5 (0~37)
4211 19:22:47.472370
4212 19:22:47.475365 ----->DramcWriteLeveling(PI) begin...
4213 19:22:47.475448 ==
4214 19:22:47.479423 Dram Type= 6, Freq= 0, CH_1, rank 0
4215 19:22:47.486052 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4216 19:22:47.486149 ==
4217 19:22:47.488753 Write leveling (Byte 0): 29 => 29
4218 19:22:47.492305 Write leveling (Byte 1): 29 => 29
4219 19:22:47.492386 DramcWriteLeveling(PI) end<-----
4220 19:22:47.492450
4221 19:22:47.495195 ==
4222 19:22:47.498976 Dram Type= 6, Freq= 0, CH_1, rank 0
4223 19:22:47.501917 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4224 19:22:47.502030 ==
4225 19:22:47.505483 [Gating] SW mode calibration
4226 19:22:47.511767 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4227 19:22:47.515263 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4228 19:22:47.521751 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4229 19:22:47.524996 0 5 4 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
4230 19:22:47.528555 0 5 8 | B1->B0 | 2f2f 2525 | 0 0 | (0 0) (0 0)
4231 19:22:47.535276 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
4232 19:22:47.538405 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4233 19:22:47.541921 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4234 19:22:47.548228 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4235 19:22:47.551541 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4236 19:22:47.555056 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4237 19:22:47.562105 0 6 4 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
4238 19:22:47.565211 0 6 8 | B1->B0 | 3434 3d3d | 0 0 | (0 0) (1 1)
4239 19:22:47.567916 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4240 19:22:47.574946 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4241 19:22:47.578104 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4242 19:22:47.581489 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4243 19:22:47.587923 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4244 19:22:47.591131 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4245 19:22:47.594433 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4246 19:22:47.601285 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4247 19:22:47.604997 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 19:22:47.607976 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 19:22:47.614354 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 19:22:47.617733 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 19:22:47.621278 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 19:22:47.627557 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 19:22:47.631013 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 19:22:47.634214 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 19:22:47.640921 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 19:22:47.644470 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 19:22:47.647688 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 19:22:47.654272 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 19:22:47.657485 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 19:22:47.660651 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 19:22:47.667670 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4262 19:22:47.670606 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4263 19:22:47.674430 Total UI for P1: 0, mck2ui 16
4264 19:22:47.677962 best dqsien dly found for B0: ( 0, 9, 4)
4265 19:22:47.680926 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4266 19:22:47.684173 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4267 19:22:47.687561 Total UI for P1: 0, mck2ui 16
4268 19:22:47.690740 best dqsien dly found for B1: ( 0, 9, 12)
4269 19:22:47.694477 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4270 19:22:47.698210 best DQS1 dly(MCK, UI, PI) = (0, 9, 12)
4271 19:22:47.698293
4272 19:22:47.704059 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4273 19:22:47.707426 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 12)
4274 19:22:47.710845 [Gating] SW calibration Done
4275 19:22:47.710926 ==
4276 19:22:47.713850 Dram Type= 6, Freq= 0, CH_1, rank 0
4277 19:22:47.717675 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4278 19:22:47.717782 ==
4279 19:22:47.717875 RX Vref Scan: 0
4280 19:22:47.720441
4281 19:22:47.720541 RX Vref 0 -> 0, step: 1
4282 19:22:47.720649
4283 19:22:47.723897 RX Delay -230 -> 252, step: 16
4284 19:22:47.726986 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4285 19:22:47.733725 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4286 19:22:47.737161 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4287 19:22:47.740290 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4288 19:22:47.743752 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4289 19:22:47.747098 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4290 19:22:47.753826 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4291 19:22:47.756858 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4292 19:22:47.760354 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4293 19:22:47.763808 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4294 19:22:47.769980 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4295 19:22:47.773262 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4296 19:22:47.776958 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4297 19:22:47.780165 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4298 19:22:47.786576 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4299 19:22:47.789855 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4300 19:22:47.789963 ==
4301 19:22:47.793396 Dram Type= 6, Freq= 0, CH_1, rank 0
4302 19:22:47.796891 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4303 19:22:47.796975 ==
4304 19:22:47.799914 DQS Delay:
4305 19:22:47.799995 DQS0 = 0, DQS1 = 0
4306 19:22:47.800059 DQM Delay:
4307 19:22:47.803574 DQM0 = 39, DQM1 = 33
4308 19:22:47.803655 DQ Delay:
4309 19:22:47.806690 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4310 19:22:47.809741 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4311 19:22:47.813336 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4312 19:22:47.816835 DQ12 =33, DQ13 =49, DQ14 =33, DQ15 =49
4313 19:22:47.816916
4314 19:22:47.816980
4315 19:22:47.817039 ==
4316 19:22:47.819926 Dram Type= 6, Freq= 0, CH_1, rank 0
4317 19:22:47.826488 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4318 19:22:47.826569 ==
4319 19:22:47.826633
4320 19:22:47.826692
4321 19:22:47.826749 TX Vref Scan disable
4322 19:22:47.829973 == TX Byte 0 ==
4323 19:22:47.833325 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4324 19:22:47.840267 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4325 19:22:47.840356 == TX Byte 1 ==
4326 19:22:47.843303 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4327 19:22:47.850346 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4328 19:22:47.850429 ==
4329 19:22:47.853881 Dram Type= 6, Freq= 0, CH_1, rank 0
4330 19:22:47.857100 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4331 19:22:47.857182 ==
4332 19:22:47.857246
4333 19:22:47.857305
4334 19:22:47.860054 TX Vref Scan disable
4335 19:22:47.860135 == TX Byte 0 ==
4336 19:22:47.866679 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4337 19:22:47.869909 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4338 19:22:47.872906 == TX Byte 1 ==
4339 19:22:47.876485 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4340 19:22:47.879628 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4341 19:22:47.879713
4342 19:22:47.879780 [DATLAT]
4343 19:22:47.882865 Freq=600, CH1 RK0
4344 19:22:47.882945
4345 19:22:47.886214 DATLAT Default: 0x9
4346 19:22:47.886295 0, 0xFFFF, sum = 0
4347 19:22:47.889927 1, 0xFFFF, sum = 0
4348 19:22:47.890057 2, 0xFFFF, sum = 0
4349 19:22:47.892838 3, 0xFFFF, sum = 0
4350 19:22:47.892922 4, 0xFFFF, sum = 0
4351 19:22:47.896297 5, 0xFFFF, sum = 0
4352 19:22:47.896417 6, 0xFFFF, sum = 0
4353 19:22:47.899635 7, 0x0, sum = 1
4354 19:22:47.899717 8, 0x0, sum = 2
4355 19:22:47.899782 9, 0x0, sum = 3
4356 19:22:47.903097 10, 0x0, sum = 4
4357 19:22:47.903179 best_step = 8
4358 19:22:47.903243
4359 19:22:47.903302 ==
4360 19:22:47.906223 Dram Type= 6, Freq= 0, CH_1, rank 0
4361 19:22:47.912877 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4362 19:22:47.912984 ==
4363 19:22:47.913076 RX Vref Scan: 1
4364 19:22:47.913163
4365 19:22:47.916012 RX Vref 0 -> 0, step: 1
4366 19:22:47.916093
4367 19:22:47.919776 RX Delay -195 -> 252, step: 8
4368 19:22:47.919858
4369 19:22:47.923244 Set Vref, RX VrefLevel [Byte0]: 56
4370 19:22:47.925980 [Byte1]: 49
4371 19:22:47.926095
4372 19:22:47.929582 Final RX Vref Byte 0 = 56 to rank0
4373 19:22:47.932621 Final RX Vref Byte 1 = 49 to rank0
4374 19:22:47.935909 Final RX Vref Byte 0 = 56 to rank1
4375 19:22:47.939288 Final RX Vref Byte 1 = 49 to rank1==
4376 19:22:47.942454 Dram Type= 6, Freq= 0, CH_1, rank 0
4377 19:22:47.946020 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4378 19:22:47.946165 ==
4379 19:22:47.949296 DQS Delay:
4380 19:22:47.949377 DQS0 = 0, DQS1 = 0
4381 19:22:47.952519 DQM Delay:
4382 19:22:47.952600 DQM0 = 38, DQM1 = 30
4383 19:22:47.955697 DQ Delay:
4384 19:22:47.955804 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4385 19:22:47.959370 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4386 19:22:47.962236 DQ8 =12, DQ9 =20, DQ10 =32, DQ11 =24
4387 19:22:47.965680 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4388 19:22:47.965762
4389 19:22:47.969219
4390 19:22:47.975588 [DQSOSCAuto] RK0, (LSB)MR18= 0x7d7d, (MSB)MR19= 0x808, tDQSOscB0 = 386 ps tDQSOscB1 = 386 ps
4391 19:22:47.979018 CH1 RK0: MR19=808, MR18=7D7D
4392 19:22:47.985457 CH1_RK0: MR19=0x808, MR18=0x7D7D, DQSOSC=386, MR23=63, INC=176, DEC=117
4393 19:22:47.985539
4394 19:22:47.989025 ----->DramcWriteLeveling(PI) begin...
4395 19:22:47.989107 ==
4396 19:22:47.992244 Dram Type= 6, Freq= 0, CH_1, rank 1
4397 19:22:47.995393 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4398 19:22:47.995476 ==
4399 19:22:47.999254 Write leveling (Byte 0): 28 => 28
4400 19:22:48.002135 Write leveling (Byte 1): 28 => 28
4401 19:22:48.005591 DramcWriteLeveling(PI) end<-----
4402 19:22:48.005672
4403 19:22:48.005735 ==
4404 19:22:48.008813 Dram Type= 6, Freq= 0, CH_1, rank 1
4405 19:22:48.012472 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4406 19:22:48.012555 ==
4407 19:22:48.015686 [Gating] SW mode calibration
4408 19:22:48.022178 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4409 19:22:48.028688 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4410 19:22:48.032187 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4411 19:22:48.035445 0 5 4 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
4412 19:22:48.041756 0 5 8 | B1->B0 | 3232 2828 | 0 0 | (1 1) (0 0)
4413 19:22:48.044997 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4414 19:22:48.048697 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4415 19:22:48.055004 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4416 19:22:48.058490 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4417 19:22:48.061463 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4418 19:22:48.068518 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4419 19:22:48.071678 0 6 4 | B1->B0 | 2323 3131 | 0 1 | (0 0) (0 0)
4420 19:22:48.074670 0 6 8 | B1->B0 | 3636 4343 | 0 0 | (1 1) (0 0)
4421 19:22:48.081220 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4422 19:22:48.084684 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4423 19:22:48.088013 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4424 19:22:48.094720 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4425 19:22:48.098194 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4426 19:22:48.101515 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4427 19:22:48.107864 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4428 19:22:48.111250 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 19:22:48.114901 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 19:22:48.121458 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 19:22:48.124361 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 19:22:48.127640 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 19:22:48.134688 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 19:22:48.137662 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 19:22:48.141216 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 19:22:48.147706 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 19:22:48.150841 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 19:22:48.154337 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 19:22:48.161081 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 19:22:48.164384 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 19:22:48.167453 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 19:22:48.173946 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 19:22:48.177419 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4444 19:22:48.180511 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4445 19:22:48.183813 Total UI for P1: 0, mck2ui 16
4446 19:22:48.187493 best dqsien dly found for B0: ( 0, 9, 4)
4447 19:22:48.194151 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4448 19:22:48.194233 Total UI for P1: 0, mck2ui 16
4449 19:22:48.200716 best dqsien dly found for B1: ( 0, 9, 10)
4450 19:22:48.203944 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4451 19:22:48.207092 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
4452 19:22:48.207174
4453 19:22:48.210477 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4454 19:22:48.214187 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
4455 19:22:48.217352 [Gating] SW calibration Done
4456 19:22:48.217433 ==
4457 19:22:48.220468 Dram Type= 6, Freq= 0, CH_1, rank 1
4458 19:22:48.224093 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4459 19:22:48.224176 ==
4460 19:22:48.227042 RX Vref Scan: 0
4461 19:22:48.227124
4462 19:22:48.227188 RX Vref 0 -> 0, step: 1
4463 19:22:48.227248
4464 19:22:48.230560 RX Delay -230 -> 252, step: 16
4465 19:22:48.233664 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4466 19:22:48.240292 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4467 19:22:48.243791 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4468 19:22:48.247154 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4469 19:22:48.250489 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4470 19:22:48.257050 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4471 19:22:48.260003 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4472 19:22:48.263249 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4473 19:22:48.266754 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4474 19:22:48.273588 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4475 19:22:48.276849 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4476 19:22:48.280481 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4477 19:22:48.283409 iDelay=218, Bit 12, Center 41 (-134 ~ 217) 352
4478 19:22:48.289915 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4479 19:22:48.293680 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4480 19:22:48.296568 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4481 19:22:48.296651 ==
4482 19:22:48.299728 Dram Type= 6, Freq= 0, CH_1, rank 1
4483 19:22:48.303139 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4484 19:22:48.303222 ==
4485 19:22:48.306363 DQS Delay:
4486 19:22:48.306445 DQS0 = 0, DQS1 = 0
4487 19:22:48.309599 DQM Delay:
4488 19:22:48.309708 DQM0 = 40, DQM1 = 33
4489 19:22:48.309801 DQ Delay:
4490 19:22:48.313209 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4491 19:22:48.316523 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =33
4492 19:22:48.319800 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4493 19:22:48.323566 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4494 19:22:48.323647
4495 19:22:48.323713
4496 19:22:48.326179 ==
4497 19:22:48.329390 Dram Type= 6, Freq= 0, CH_1, rank 1
4498 19:22:48.332893 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4499 19:22:48.332976 ==
4500 19:22:48.333041
4501 19:22:48.333101
4502 19:22:48.336457 TX Vref Scan disable
4503 19:22:48.336539 == TX Byte 0 ==
4504 19:22:48.342833 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4505 19:22:48.346145 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4506 19:22:48.346248 == TX Byte 1 ==
4507 19:22:48.352726 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4508 19:22:48.355865 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4509 19:22:48.355948 ==
4510 19:22:48.359429 Dram Type= 6, Freq= 0, CH_1, rank 1
4511 19:22:48.362508 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4512 19:22:48.362591 ==
4513 19:22:48.362657
4514 19:22:48.362717
4515 19:22:48.365918 TX Vref Scan disable
4516 19:22:48.369462 == TX Byte 0 ==
4517 19:22:48.372631 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4518 19:22:48.376062 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4519 19:22:48.378963 == TX Byte 1 ==
4520 19:22:48.382752 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4521 19:22:48.385744 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4522 19:22:48.385826
4523 19:22:48.388782 [DATLAT]
4524 19:22:48.388864 Freq=600, CH1 RK1
4525 19:22:48.388930
4526 19:22:48.392096 DATLAT Default: 0x8
4527 19:22:48.392178 0, 0xFFFF, sum = 0
4528 19:22:48.395792 1, 0xFFFF, sum = 0
4529 19:22:48.395910 2, 0xFFFF, sum = 0
4530 19:22:48.399119 3, 0xFFFF, sum = 0
4531 19:22:48.399203 4, 0xFFFF, sum = 0
4532 19:22:48.402057 5, 0xFFFF, sum = 0
4533 19:22:48.405298 6, 0xFFFF, sum = 0
4534 19:22:48.405382 7, 0x0, sum = 1
4535 19:22:48.405448 8, 0x0, sum = 2
4536 19:22:48.408577 9, 0x0, sum = 3
4537 19:22:48.408661 10, 0x0, sum = 4
4538 19:22:48.411833 best_step = 8
4539 19:22:48.411915
4540 19:22:48.411980 ==
4541 19:22:48.415403 Dram Type= 6, Freq= 0, CH_1, rank 1
4542 19:22:48.418625 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4543 19:22:48.418708 ==
4544 19:22:48.422180 RX Vref Scan: 0
4545 19:22:48.422262
4546 19:22:48.422328 RX Vref 0 -> 0, step: 1
4547 19:22:48.422388
4548 19:22:48.425688 RX Delay -195 -> 252, step: 8
4549 19:22:48.432626 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4550 19:22:48.435612 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4551 19:22:48.439194 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4552 19:22:48.442365 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4553 19:22:48.449324 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4554 19:22:48.452175 iDelay=205, Bit 5, Center 44 (-115 ~ 204) 320
4555 19:22:48.455748 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4556 19:22:48.458743 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4557 19:22:48.465541 iDelay=205, Bit 8, Center 16 (-139 ~ 172) 312
4558 19:22:48.468782 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4559 19:22:48.472104 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4560 19:22:48.475229 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4561 19:22:48.482006 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4562 19:22:48.485031 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4563 19:22:48.488496 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4564 19:22:48.491878 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4565 19:22:48.491960 ==
4566 19:22:48.495475 Dram Type= 6, Freq= 0, CH_1, rank 1
4567 19:22:48.502351 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4568 19:22:48.502435 ==
4569 19:22:48.502500 DQS Delay:
4570 19:22:48.505175 DQS0 = 0, DQS1 = 0
4571 19:22:48.505272 DQM Delay:
4572 19:22:48.505338 DQM0 = 36, DQM1 = 29
4573 19:22:48.508082 DQ Delay:
4574 19:22:48.511739 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4575 19:22:48.514994 DQ4 =36, DQ5 =44, DQ6 =44, DQ7 =36
4576 19:22:48.518220 DQ8 =16, DQ9 =20, DQ10 =28, DQ11 =20
4577 19:22:48.521433 DQ12 =36, DQ13 =40, DQ14 =36, DQ15 =40
4578 19:22:48.521515
4579 19:22:48.521579
4580 19:22:48.528079 [DQSOSCAuto] RK1, (LSB)MR18= 0x6464, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
4581 19:22:48.531519 CH1 RK1: MR19=808, MR18=6464
4582 19:22:48.538386 CH1_RK1: MR19=0x808, MR18=0x6464, DQSOSC=391, MR23=63, INC=171, DEC=114
4583 19:22:48.541333 [RxdqsGatingPostProcess] freq 600
4584 19:22:48.545012 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4585 19:22:48.547975 Pre-setting of DQS Precalculation
4586 19:22:48.554816 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4587 19:22:48.561553 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4588 19:22:48.567730 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4589 19:22:48.567813
4590 19:22:48.567880
4591 19:22:48.571486 [Calibration Summary] 1200 Mbps
4592 19:22:48.571571 CH 0, Rank 0
4593 19:22:48.574550 SW Impedance : PASS
4594 19:22:48.578172 DUTY Scan : NO K
4595 19:22:48.578254 ZQ Calibration : PASS
4596 19:22:48.580891 Jitter Meter : NO K
4597 19:22:48.584634 CBT Training : PASS
4598 19:22:48.584716 Write leveling : PASS
4599 19:22:48.587652 RX DQS gating : PASS
4600 19:22:48.590938 RX DQ/DQS(RDDQC) : PASS
4601 19:22:48.591046 TX DQ/DQS : PASS
4602 19:22:48.594196 RX DATLAT : PASS
4603 19:22:48.597627 RX DQ/DQS(Engine): PASS
4604 19:22:48.597751 TX OE : NO K
4605 19:22:48.600918 All Pass.
4606 19:22:48.600999
4607 19:22:48.601064 CH 0, Rank 1
4608 19:22:48.604215 SW Impedance : PASS
4609 19:22:48.604297 DUTY Scan : NO K
4610 19:22:48.607425 ZQ Calibration : PASS
4611 19:22:48.610777 Jitter Meter : NO K
4612 19:22:48.610859 CBT Training : PASS
4613 19:22:48.614227 Write leveling : PASS
4614 19:22:48.617441 RX DQS gating : PASS
4615 19:22:48.617523 RX DQ/DQS(RDDQC) : PASS
4616 19:22:48.620948 TX DQ/DQS : PASS
4617 19:22:48.623777 RX DATLAT : PASS
4618 19:22:48.623859 RX DQ/DQS(Engine): PASS
4619 19:22:48.626999 TX OE : NO K
4620 19:22:48.627082 All Pass.
4621 19:22:48.627148
4622 19:22:48.630679 CH 1, Rank 0
4623 19:22:48.630763 SW Impedance : PASS
4624 19:22:48.634134 DUTY Scan : NO K
4625 19:22:48.634216 ZQ Calibration : PASS
4626 19:22:48.637082 Jitter Meter : NO K
4627 19:22:48.640620 CBT Training : PASS
4628 19:22:48.640701 Write leveling : PASS
4629 19:22:48.643526 RX DQS gating : PASS
4630 19:22:48.647170 RX DQ/DQS(RDDQC) : PASS
4631 19:22:48.647252 TX DQ/DQS : PASS
4632 19:22:48.650579 RX DATLAT : PASS
4633 19:22:48.653477 RX DQ/DQS(Engine): PASS
4634 19:22:48.653559 TX OE : NO K
4635 19:22:48.657155 All Pass.
4636 19:22:48.657237
4637 19:22:48.657302 CH 1, Rank 1
4638 19:22:48.660362 SW Impedance : PASS
4639 19:22:48.660445 DUTY Scan : NO K
4640 19:22:48.663792 ZQ Calibration : PASS
4641 19:22:48.666708 Jitter Meter : NO K
4642 19:22:48.666790 CBT Training : PASS
4643 19:22:48.670138 Write leveling : PASS
4644 19:22:48.673448 RX DQS gating : PASS
4645 19:22:48.673530 RX DQ/DQS(RDDQC) : PASS
4646 19:22:48.676976 TX DQ/DQS : PASS
4647 19:22:48.680026 RX DATLAT : PASS
4648 19:22:48.680108 RX DQ/DQS(Engine): PASS
4649 19:22:48.683487 TX OE : NO K
4650 19:22:48.683569 All Pass.
4651 19:22:48.683636
4652 19:22:48.686599 DramC Write-DBI off
4653 19:22:48.690417 PER_BANK_REFRESH: Hybrid Mode
4654 19:22:48.690500 TX_TRACKING: ON
4655 19:22:48.699717 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4656 19:22:48.703246 [FAST_K] Save calibration result to emmc
4657 19:22:48.706419 dramc_set_vcore_voltage set vcore to 662500
4658 19:22:48.709878 Read voltage for 933, 3
4659 19:22:48.709986 Vio18 = 0
4660 19:22:48.710105 Vcore = 662500
4661 19:22:48.713282 Vdram = 0
4662 19:22:48.713363 Vddq = 0
4663 19:22:48.713428 Vmddr = 0
4664 19:22:48.719791 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4665 19:22:48.723371 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4666 19:22:48.726312 MEM_TYPE=3, freq_sel=17
4667 19:22:48.730138 sv_algorithm_assistance_LP4_1600
4668 19:22:48.733017 ============ PULL DRAM RESETB DOWN ============
4669 19:22:48.736529 ========== PULL DRAM RESETB DOWN end =========
4670 19:22:48.743295 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4671 19:22:48.746183 ===================================
4672 19:22:48.746265 LPDDR4 DRAM CONFIGURATION
4673 19:22:48.749590 ===================================
4674 19:22:48.753429 EX_ROW_EN[0] = 0x0
4675 19:22:48.756096 EX_ROW_EN[1] = 0x0
4676 19:22:48.756178 LP4Y_EN = 0x0
4677 19:22:48.759488 WORK_FSP = 0x0
4678 19:22:48.759571 WL = 0x3
4679 19:22:48.762985 RL = 0x3
4680 19:22:48.763067 BL = 0x2
4681 19:22:48.766266 RPST = 0x0
4682 19:22:48.766374 RD_PRE = 0x0
4683 19:22:48.769317 WR_PRE = 0x1
4684 19:22:48.769418 WR_PST = 0x0
4685 19:22:48.772641 DBI_WR = 0x0
4686 19:22:48.772723 DBI_RD = 0x0
4687 19:22:48.775889 OTF = 0x1
4688 19:22:48.779547 ===================================
4689 19:22:48.782526 ===================================
4690 19:22:48.782608 ANA top config
4691 19:22:48.785776 ===================================
4692 19:22:48.789317 DLL_ASYNC_EN = 0
4693 19:22:48.792563 ALL_SLAVE_EN = 1
4694 19:22:48.795955 NEW_RANK_MODE = 1
4695 19:22:48.796039 DLL_IDLE_MODE = 1
4696 19:22:48.799077 LP45_APHY_COMB_EN = 1
4697 19:22:48.802666 TX_ODT_DIS = 1
4698 19:22:48.805564 NEW_8X_MODE = 1
4699 19:22:48.809010 ===================================
4700 19:22:48.812288 ===================================
4701 19:22:48.815538 data_rate = 1866
4702 19:22:48.818717 CKR = 1
4703 19:22:48.818800 DQ_P2S_RATIO = 8
4704 19:22:48.822600 ===================================
4705 19:22:48.825374 CA_P2S_RATIO = 8
4706 19:22:48.829007 DQ_CA_OPEN = 0
4707 19:22:48.832049 DQ_SEMI_OPEN = 0
4708 19:22:48.835682 CA_SEMI_OPEN = 0
4709 19:22:48.835765 CA_FULL_RATE = 0
4710 19:22:48.838721 DQ_CKDIV4_EN = 1
4711 19:22:48.842390 CA_CKDIV4_EN = 1
4712 19:22:48.845288 CA_PREDIV_EN = 0
4713 19:22:48.848405 PH8_DLY = 0
4714 19:22:48.852062 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4715 19:22:48.855248 DQ_AAMCK_DIV = 4
4716 19:22:48.855330 CA_AAMCK_DIV = 4
4717 19:22:48.858336 CA_ADMCK_DIV = 4
4718 19:22:48.861579 DQ_TRACK_CA_EN = 0
4719 19:22:48.865618 CA_PICK = 933
4720 19:22:48.868502 CA_MCKIO = 933
4721 19:22:48.871604 MCKIO_SEMI = 0
4722 19:22:48.875115 PLL_FREQ = 3732
4723 19:22:48.875201 DQ_UI_PI_RATIO = 32
4724 19:22:48.878379 CA_UI_PI_RATIO = 0
4725 19:22:48.881561 ===================================
4726 19:22:48.884744 ===================================
4727 19:22:48.888176 memory_type:LPDDR4
4728 19:22:48.891256 GP_NUM : 10
4729 19:22:48.891338 SRAM_EN : 1
4730 19:22:48.895187 MD32_EN : 0
4731 19:22:48.898180 ===================================
4732 19:22:48.901760 [ANA_INIT] >>>>>>>>>>>>>>
4733 19:22:48.901843 <<<<<< [CONFIGURE PHASE]: ANA_TX
4734 19:22:48.908054 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4735 19:22:48.908174 ===================================
4736 19:22:48.911321 data_rate = 1866,PCW = 0X8f00
4737 19:22:48.914606 ===================================
4738 19:22:48.917769 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4739 19:22:48.924458 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4740 19:22:48.931303 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4741 19:22:48.934509 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4742 19:22:48.937995 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4743 19:22:48.941385 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4744 19:22:48.944107 [ANA_INIT] flow start
4745 19:22:48.944229 [ANA_INIT] PLL >>>>>>>>
4746 19:22:48.947525 [ANA_INIT] PLL <<<<<<<<
4747 19:22:48.950799 [ANA_INIT] MIDPI >>>>>>>>
4748 19:22:48.954351 [ANA_INIT] MIDPI <<<<<<<<
4749 19:22:48.954434 [ANA_INIT] DLL >>>>>>>>
4750 19:22:48.957430 [ANA_INIT] flow end
4751 19:22:48.961027 ============ LP4 DIFF to SE enter ============
4752 19:22:48.964226 ============ LP4 DIFF to SE exit ============
4753 19:22:48.967699 [ANA_INIT] <<<<<<<<<<<<<
4754 19:22:48.970680 [Flow] Enable top DCM control >>>>>
4755 19:22:48.974065 [Flow] Enable top DCM control <<<<<
4756 19:22:48.977095 Enable DLL master slave shuffle
4757 19:22:48.983967 ==============================================================
4758 19:22:48.984050 Gating Mode config
4759 19:22:48.990806 ==============================================================
4760 19:22:48.990890 Config description:
4761 19:22:49.000378 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4762 19:22:49.006791 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4763 19:22:49.013608 SELPH_MODE 0: By rank 1: By Phase
4764 19:22:49.016576 ==============================================================
4765 19:22:49.020100 GAT_TRACK_EN = 1
4766 19:22:49.023373 RX_GATING_MODE = 2
4767 19:22:49.026602 RX_GATING_TRACK_MODE = 2
4768 19:22:49.029809 SELPH_MODE = 1
4769 19:22:49.033367 PICG_EARLY_EN = 1
4770 19:22:49.036396 VALID_LAT_VALUE = 1
4771 19:22:49.043017 ==============================================================
4772 19:22:49.046859 Enter into Gating configuration >>>>
4773 19:22:49.049903 Exit from Gating configuration <<<<
4774 19:22:49.053409 Enter into DVFS_PRE_config >>>>>
4775 19:22:49.063101 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4776 19:22:49.066181 Exit from DVFS_PRE_config <<<<<
4777 19:22:49.069549 Enter into PICG configuration >>>>
4778 19:22:49.072966 Exit from PICG configuration <<<<
4779 19:22:49.076705 [RX_INPUT] configuration >>>>>
4780 19:22:49.076787 [RX_INPUT] configuration <<<<<
4781 19:22:49.083065 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4782 19:22:49.089859 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4783 19:22:49.096444 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4784 19:22:49.099615 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4785 19:22:49.106260 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4786 19:22:49.113018 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4787 19:22:49.116039 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4788 19:22:49.119286 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4789 19:22:49.126148 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4790 19:22:49.129710 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4791 19:22:49.132546 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4792 19:22:49.139390 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4793 19:22:49.142540 ===================================
4794 19:22:49.142623 LPDDR4 DRAM CONFIGURATION
4795 19:22:49.145747 ===================================
4796 19:22:49.149012 EX_ROW_EN[0] = 0x0
4797 19:22:49.152981 EX_ROW_EN[1] = 0x0
4798 19:22:49.153063 LP4Y_EN = 0x0
4799 19:22:49.156020 WORK_FSP = 0x0
4800 19:22:49.156103 WL = 0x3
4801 19:22:49.159220 RL = 0x3
4802 19:22:49.159302 BL = 0x2
4803 19:22:49.162323 RPST = 0x0
4804 19:22:49.162405 RD_PRE = 0x0
4805 19:22:49.165442 WR_PRE = 0x1
4806 19:22:49.165523 WR_PST = 0x0
4807 19:22:49.168841 DBI_WR = 0x0
4808 19:22:49.168923 DBI_RD = 0x0
4809 19:22:49.172633 OTF = 0x1
4810 19:22:49.175638 ===================================
4811 19:22:49.179015 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4812 19:22:49.182012 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4813 19:22:49.188901 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4814 19:22:49.192046 ===================================
4815 19:22:49.192128 LPDDR4 DRAM CONFIGURATION
4816 19:22:49.195576 ===================================
4817 19:22:49.198752 EX_ROW_EN[0] = 0x10
4818 19:22:49.201962 EX_ROW_EN[1] = 0x0
4819 19:22:49.202077 LP4Y_EN = 0x0
4820 19:22:49.205865 WORK_FSP = 0x0
4821 19:22:49.205973 WL = 0x3
4822 19:22:49.208636 RL = 0x3
4823 19:22:49.208717 BL = 0x2
4824 19:22:49.211983 RPST = 0x0
4825 19:22:49.212066 RD_PRE = 0x0
4826 19:22:49.215499 WR_PRE = 0x1
4827 19:22:49.215580 WR_PST = 0x0
4828 19:22:49.218400 DBI_WR = 0x0
4829 19:22:49.218482 DBI_RD = 0x0
4830 19:22:49.221776 OTF = 0x1
4831 19:22:49.225320 ===================================
4832 19:22:49.231586 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4833 19:22:49.234961 nWR fixed to 30
4834 19:22:49.235047 [ModeRegInit_LP4] CH0 RK0
4835 19:22:49.238318 [ModeRegInit_LP4] CH0 RK1
4836 19:22:49.241692 [ModeRegInit_LP4] CH1 RK0
4837 19:22:49.244960 [ModeRegInit_LP4] CH1 RK1
4838 19:22:49.245042 match AC timing 8
4839 19:22:49.251682 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4840 19:22:49.254636 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4841 19:22:49.258237 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4842 19:22:49.264746 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4843 19:22:49.268124 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4844 19:22:49.268206 ==
4845 19:22:49.271151 Dram Type= 6, Freq= 0, CH_0, rank 0
4846 19:22:49.275105 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4847 19:22:49.275191 ==
4848 19:22:49.281230 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4849 19:22:49.288174 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4850 19:22:49.291100 [CA 0] Center 38 (8~69) winsize 62
4851 19:22:49.294821 [CA 1] Center 38 (8~69) winsize 62
4852 19:22:49.298064 [CA 2] Center 36 (6~67) winsize 62
4853 19:22:49.301352 [CA 3] Center 36 (6~66) winsize 61
4854 19:22:49.304487 [CA 4] Center 35 (5~65) winsize 61
4855 19:22:49.307581 [CA 5] Center 34 (4~64) winsize 61
4856 19:22:49.307663
4857 19:22:49.310861 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4858 19:22:49.310944
4859 19:22:49.314503 [CATrainingPosCal] consider 1 rank data
4860 19:22:49.317586 u2DelayCellTimex100 = 270/100 ps
4861 19:22:49.320957 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4862 19:22:49.324223 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4863 19:22:49.327322 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4864 19:22:49.330750 CA3 delay=36 (6~66),Diff = 2 PI (12 cell)
4865 19:22:49.333992 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
4866 19:22:49.337411 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4867 19:22:49.340817
4868 19:22:49.344109 CA PerBit enable=1, Macro0, CA PI delay=34
4869 19:22:49.344211
4870 19:22:49.347391 [CBTSetCACLKResult] CA Dly = 34
4871 19:22:49.347513 CS Dly: 7 (0~38)
4872 19:22:49.347625 ==
4873 19:22:49.350719 Dram Type= 6, Freq= 0, CH_0, rank 1
4874 19:22:49.354211 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4875 19:22:49.354315 ==
4876 19:22:49.360841 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4877 19:22:49.367179 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4878 19:22:49.370491 [CA 0] Center 38 (8~69) winsize 62
4879 19:22:49.373772 [CA 1] Center 38 (8~69) winsize 62
4880 19:22:49.377066 [CA 2] Center 36 (6~67) winsize 62
4881 19:22:49.380690 [CA 3] Center 35 (5~66) winsize 62
4882 19:22:49.383821 [CA 4] Center 34 (4~65) winsize 62
4883 19:22:49.387080 [CA 5] Center 34 (4~65) winsize 62
4884 19:22:49.387162
4885 19:22:49.390409 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4886 19:22:49.390517
4887 19:22:49.393678 [CATrainingPosCal] consider 2 rank data
4888 19:22:49.396695 u2DelayCellTimex100 = 270/100 ps
4889 19:22:49.400088 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4890 19:22:49.403258 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4891 19:22:49.406797 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4892 19:22:49.410403 CA3 delay=36 (6~66),Diff = 2 PI (12 cell)
4893 19:22:49.416737 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
4894 19:22:49.420208 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4895 19:22:49.420290
4896 19:22:49.423221 CA PerBit enable=1, Macro0, CA PI delay=34
4897 19:22:49.423303
4898 19:22:49.426662 [CBTSetCACLKResult] CA Dly = 34
4899 19:22:49.426744 CS Dly: 7 (0~39)
4900 19:22:49.426809
4901 19:22:49.430026 ----->DramcWriteLeveling(PI) begin...
4902 19:22:49.430111 ==
4903 19:22:49.433342 Dram Type= 6, Freq= 0, CH_0, rank 0
4904 19:22:49.439580 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4905 19:22:49.439663 ==
4906 19:22:49.443395 Write leveling (Byte 0): 26 => 26
4907 19:22:49.446449 Write leveling (Byte 1): 28 => 28
4908 19:22:49.450217 DramcWriteLeveling(PI) end<-----
4909 19:22:49.450324
4910 19:22:49.450417 ==
4911 19:22:49.452922 Dram Type= 6, Freq= 0, CH_0, rank 0
4912 19:22:49.456095 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4913 19:22:49.456177 ==
4914 19:22:49.459547 [Gating] SW mode calibration
4915 19:22:49.466829 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4916 19:22:49.469756 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4917 19:22:49.476449 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4918 19:22:49.479661 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4919 19:22:49.482911 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4920 19:22:49.489083 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4921 19:22:49.492614 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4922 19:22:49.495780 0 10 20 | B1->B0 | 3232 3030 | 1 1 | (1 0) (1 0)
4923 19:22:49.502370 0 10 24 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
4924 19:22:49.505579 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4925 19:22:49.509245 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4926 19:22:49.515791 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4927 19:22:49.519405 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4928 19:22:49.522209 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4929 19:22:49.529103 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4930 19:22:49.532078 0 11 20 | B1->B0 | 2626 2a2a | 0 0 | (0 0) (1 1)
4931 19:22:49.535416 0 11 24 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
4932 19:22:49.542137 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4933 19:22:49.545538 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4934 19:22:49.549022 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4935 19:22:49.555596 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4936 19:22:49.558403 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4937 19:22:49.561980 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4938 19:22:49.568809 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4939 19:22:49.571813 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4940 19:22:49.574967 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4941 19:22:49.581528 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4942 19:22:49.584697 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4943 19:22:49.588114 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4944 19:22:49.594866 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4945 19:22:49.598334 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4946 19:22:49.601770 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4947 19:22:49.608070 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4948 19:22:49.611668 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4949 19:22:49.615166 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4950 19:22:49.621401 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4951 19:22:49.624975 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4952 19:22:49.627950 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4953 19:22:49.634885 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4954 19:22:49.638252 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4955 19:22:49.641149 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4956 19:22:49.647758 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4957 19:22:49.651029 Total UI for P1: 0, mck2ui 16
4958 19:22:49.654323 best dqsien dly found for B0: ( 0, 14, 22)
4959 19:22:49.654405 Total UI for P1: 0, mck2ui 16
4960 19:22:49.660976 best dqsien dly found for B1: ( 0, 14, 22)
4961 19:22:49.664944 best DQS0 dly(MCK, UI, PI) = (0, 14, 22)
4962 19:22:49.667750 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
4963 19:22:49.667832
4964 19:22:49.671003 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 22)
4965 19:22:49.674054 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
4966 19:22:49.677459 [Gating] SW calibration Done
4967 19:22:49.677541 ==
4968 19:22:49.681125 Dram Type= 6, Freq= 0, CH_0, rank 0
4969 19:22:49.684009 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4970 19:22:49.684092 ==
4971 19:22:49.687132 RX Vref Scan: 0
4972 19:22:49.687215
4973 19:22:49.690369 RX Vref 0 -> 0, step: 1
4974 19:22:49.690451
4975 19:22:49.690516 RX Delay -80 -> 252, step: 8
4976 19:22:49.697048 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
4977 19:22:49.700346 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
4978 19:22:49.703827 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
4979 19:22:49.707474 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
4980 19:22:49.710360 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
4981 19:22:49.713703 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
4982 19:22:49.720808 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
4983 19:22:49.723606 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
4984 19:22:49.727103 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
4985 19:22:49.730339 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
4986 19:22:49.733679 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
4987 19:22:49.740531 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
4988 19:22:49.743732 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
4989 19:22:49.747122 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
4990 19:22:49.750038 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
4991 19:22:49.753108 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
4992 19:22:49.756530 ==
4993 19:22:49.760018 Dram Type= 6, Freq= 0, CH_0, rank 0
4994 19:22:49.763254 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4995 19:22:49.763337 ==
4996 19:22:49.763401 DQS Delay:
4997 19:22:49.766840 DQS0 = 0, DQS1 = 0
4998 19:22:49.766923 DQM Delay:
4999 19:22:49.769985 DQM0 = 96, DQM1 = 85
5000 19:22:49.770105 DQ Delay:
5001 19:22:49.773223 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5002 19:22:49.776554 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5003 19:22:49.780123 DQ8 =79, DQ9 =71, DQ10 =83, DQ11 =79
5004 19:22:49.783104 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =91
5005 19:22:49.783186
5006 19:22:49.783251
5007 19:22:49.783311 ==
5008 19:22:49.786837 Dram Type= 6, Freq= 0, CH_0, rank 0
5009 19:22:49.789780 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5010 19:22:49.789862 ==
5011 19:22:49.789928
5012 19:22:49.789989
5013 19:22:49.792993 TX Vref Scan disable
5014 19:22:49.796174 == TX Byte 0 ==
5015 19:22:49.799615 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5016 19:22:49.803098 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5017 19:22:49.806297 == TX Byte 1 ==
5018 19:22:49.809319 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5019 19:22:49.812943 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5020 19:22:49.813026 ==
5021 19:22:49.816155 Dram Type= 6, Freq= 0, CH_0, rank 0
5022 19:22:49.823168 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5023 19:22:49.823281 ==
5024 19:22:49.823348
5025 19:22:49.823409
5026 19:22:49.823468 TX Vref Scan disable
5027 19:22:49.826843 == TX Byte 0 ==
5028 19:22:49.829886 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5029 19:22:49.836900 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5030 19:22:49.836983 == TX Byte 1 ==
5031 19:22:49.840029 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5032 19:22:49.846888 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5033 19:22:49.846971
5034 19:22:49.847036 [DATLAT]
5035 19:22:49.847096 Freq=933, CH0 RK0
5036 19:22:49.847155
5037 19:22:49.850037 DATLAT Default: 0xd
5038 19:22:49.850144 0, 0xFFFF, sum = 0
5039 19:22:49.853091 1, 0xFFFF, sum = 0
5040 19:22:49.856503 2, 0xFFFF, sum = 0
5041 19:22:49.856587 3, 0xFFFF, sum = 0
5042 19:22:49.859815 4, 0xFFFF, sum = 0
5043 19:22:49.859899 5, 0xFFFF, sum = 0
5044 19:22:49.863127 6, 0xFFFF, sum = 0
5045 19:22:49.863210 7, 0xFFFF, sum = 0
5046 19:22:49.866434 8, 0xFFFF, sum = 0
5047 19:22:49.866517 9, 0xFFFF, sum = 0
5048 19:22:49.869581 10, 0x0, sum = 1
5049 19:22:49.869664 11, 0x0, sum = 2
5050 19:22:49.873078 12, 0x0, sum = 3
5051 19:22:49.873165 13, 0x0, sum = 4
5052 19:22:49.873232 best_step = 11
5053 19:22:49.873293
5054 19:22:49.876361 ==
5055 19:22:49.879660 Dram Type= 6, Freq= 0, CH_0, rank 0
5056 19:22:49.882945 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5057 19:22:49.883027 ==
5058 19:22:49.883093 RX Vref Scan: 1
5059 19:22:49.883153
5060 19:22:49.886376 RX Vref 0 -> 0, step: 1
5061 19:22:49.886458
5062 19:22:49.889462 RX Delay -69 -> 252, step: 4
5063 19:22:49.889545
5064 19:22:49.893243 Set Vref, RX VrefLevel [Byte0]: 52
5065 19:22:49.895852 [Byte1]: 46
5066 19:22:49.899470
5067 19:22:49.899589 Final RX Vref Byte 0 = 52 to rank0
5068 19:22:49.902590 Final RX Vref Byte 1 = 46 to rank0
5069 19:22:49.906261 Final RX Vref Byte 0 = 52 to rank1
5070 19:22:49.909206 Final RX Vref Byte 1 = 46 to rank1==
5071 19:22:49.912954 Dram Type= 6, Freq= 0, CH_0, rank 0
5072 19:22:49.919458 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5073 19:22:49.919541 ==
5074 19:22:49.919606 DQS Delay:
5075 19:22:49.919666 DQS0 = 0, DQS1 = 0
5076 19:22:49.922784 DQM Delay:
5077 19:22:49.922867 DQM0 = 96, DQM1 = 86
5078 19:22:49.926001 DQ Delay:
5079 19:22:49.929315 DQ0 =92, DQ1 =96, DQ2 =96, DQ3 =92
5080 19:22:49.932764 DQ4 =100, DQ5 =86, DQ6 =104, DQ7 =102
5081 19:22:49.935915 DQ8 =74, DQ9 =70, DQ10 =88, DQ11 =80
5082 19:22:49.939160 DQ12 =94, DQ13 =92, DQ14 =98, DQ15 =96
5083 19:22:49.939242
5084 19:22:49.939308
5085 19:22:49.945702 [DQSOSCAuto] RK0, (LSB)MR18= 0x2424, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
5086 19:22:49.949079 CH0 RK0: MR19=505, MR18=2424
5087 19:22:49.955817 CH0_RK0: MR19=0x505, MR18=0x2424, DQSOSC=410, MR23=63, INC=64, DEC=42
5088 19:22:49.955901
5089 19:22:49.959037 ----->DramcWriteLeveling(PI) begin...
5090 19:22:49.959120 ==
5091 19:22:49.962383 Dram Type= 6, Freq= 0, CH_0, rank 1
5092 19:22:49.965503 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5093 19:22:49.965584 ==
5094 19:22:49.968921 Write leveling (Byte 0): 28 => 28
5095 19:22:49.972250 Write leveling (Byte 1): 28 => 28
5096 19:22:49.975681 DramcWriteLeveling(PI) end<-----
5097 19:22:49.975763
5098 19:22:49.975827 ==
5099 19:22:49.978678 Dram Type= 6, Freq= 0, CH_0, rank 1
5100 19:22:49.982038 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5101 19:22:49.985220 ==
5102 19:22:49.985302 [Gating] SW mode calibration
5103 19:22:49.992086 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5104 19:22:49.998981 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5105 19:22:50.001981 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5106 19:22:50.008737 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5107 19:22:50.011771 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5108 19:22:50.015258 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5109 19:22:50.021733 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5110 19:22:50.025548 0 10 20 | B1->B0 | 3232 2c2c | 1 1 | (1 0) (1 0)
5111 19:22:50.028333 0 10 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5112 19:22:50.035046 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5113 19:22:50.038143 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5114 19:22:50.041698 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5115 19:22:50.048168 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5116 19:22:50.051703 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5117 19:22:50.055361 0 11 16 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
5118 19:22:50.061530 0 11 20 | B1->B0 | 2d2d 3838 | 1 0 | (0 0) (1 1)
5119 19:22:50.064882 0 11 24 | B1->B0 | 4242 4646 | 0 0 | (1 1) (0 0)
5120 19:22:50.068112 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5121 19:22:50.074775 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5122 19:22:50.077915 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5123 19:22:50.081121 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5124 19:22:50.088313 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5125 19:22:50.091206 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5126 19:22:50.094276 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5127 19:22:50.100930 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5128 19:22:50.104438 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 19:22:50.107968 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 19:22:50.114173 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 19:22:50.117541 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 19:22:50.121015 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 19:22:50.127632 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 19:22:50.131224 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 19:22:50.134367 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 19:22:50.140758 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 19:22:50.144375 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 19:22:50.147844 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 19:22:50.151048 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 19:22:50.157447 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 19:22:50.160655 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 19:22:50.167742 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 19:22:50.170437 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5144 19:22:50.173860 Total UI for P1: 0, mck2ui 16
5145 19:22:50.177134 best dqsien dly found for B0: ( 0, 14, 22)
5146 19:22:50.180876 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5147 19:22:50.183847 Total UI for P1: 0, mck2ui 16
5148 19:22:50.187166 best dqsien dly found for B1: ( 0, 14, 24)
5149 19:22:50.190403 best DQS0 dly(MCK, UI, PI) = (0, 14, 22)
5150 19:22:50.193518 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
5151 19:22:50.193600
5152 19:22:50.197222 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 22)
5153 19:22:50.203636 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 24)
5154 19:22:50.203738 [Gating] SW calibration Done
5155 19:22:50.206733 ==
5156 19:22:50.206817 Dram Type= 6, Freq= 0, CH_0, rank 1
5157 19:22:50.213725 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5158 19:22:50.213811 ==
5159 19:22:50.213877 RX Vref Scan: 0
5160 19:22:50.213939
5161 19:22:50.216965 RX Vref 0 -> 0, step: 1
5162 19:22:50.217078
5163 19:22:50.220222 RX Delay -80 -> 252, step: 8
5164 19:22:50.223683 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5165 19:22:50.227079 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5166 19:22:50.229939 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5167 19:22:50.236724 iDelay=208, Bit 3, Center 87 (-8 ~ 183) 192
5168 19:22:50.240022 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5169 19:22:50.243462 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5170 19:22:50.246793 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5171 19:22:50.250264 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5172 19:22:50.253201 iDelay=208, Bit 8, Center 79 (-8 ~ 167) 176
5173 19:22:50.260137 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5174 19:22:50.263302 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5175 19:22:50.266499 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5176 19:22:50.269549 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5177 19:22:50.273182 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5178 19:22:50.279570 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5179 19:22:50.283055 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5180 19:22:50.283138 ==
5181 19:22:50.286303 Dram Type= 6, Freq= 0, CH_0, rank 1
5182 19:22:50.289404 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5183 19:22:50.289486 ==
5184 19:22:50.289552 DQS Delay:
5185 19:22:50.292936 DQS0 = 0, DQS1 = 0
5186 19:22:50.293018 DQM Delay:
5187 19:22:50.296456 DQM0 = 95, DQM1 = 87
5188 19:22:50.296538 DQ Delay:
5189 19:22:50.299453 DQ0 =91, DQ1 =99, DQ2 =91, DQ3 =87
5190 19:22:50.302965 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =107
5191 19:22:50.305911 DQ8 =79, DQ9 =71, DQ10 =91, DQ11 =83
5192 19:22:50.309636 DQ12 =95, DQ13 =91, DQ14 =91, DQ15 =95
5193 19:22:50.309719
5194 19:22:50.309784
5195 19:22:50.309844 ==
5196 19:22:50.313270 Dram Type= 6, Freq= 0, CH_0, rank 1
5197 19:22:50.319368 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5198 19:22:50.319451 ==
5199 19:22:50.319516
5200 19:22:50.319582
5201 19:22:50.319681 TX Vref Scan disable
5202 19:22:50.322777 == TX Byte 0 ==
5203 19:22:50.326129 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5204 19:22:50.329498 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5205 19:22:50.332566 == TX Byte 1 ==
5206 19:22:50.335916 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5207 19:22:50.342752 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5208 19:22:50.342835 ==
5209 19:22:50.346076 Dram Type= 6, Freq= 0, CH_0, rank 1
5210 19:22:50.349256 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5211 19:22:50.349339 ==
5212 19:22:50.349405
5213 19:22:50.349465
5214 19:22:50.352775 TX Vref Scan disable
5215 19:22:50.352860 == TX Byte 0 ==
5216 19:22:50.359476 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5217 19:22:50.362430 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5218 19:22:50.362514 == TX Byte 1 ==
5219 19:22:50.368965 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5220 19:22:50.372826 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5221 19:22:50.372908
5222 19:22:50.372973 [DATLAT]
5223 19:22:50.375904 Freq=933, CH0 RK1
5224 19:22:50.375986
5225 19:22:50.376052 DATLAT Default: 0xb
5226 19:22:50.379125 0, 0xFFFF, sum = 0
5227 19:22:50.379209 1, 0xFFFF, sum = 0
5228 19:22:50.382275 2, 0xFFFF, sum = 0
5229 19:22:50.385509 3, 0xFFFF, sum = 0
5230 19:22:50.385593 4, 0xFFFF, sum = 0
5231 19:22:50.388657 5, 0xFFFF, sum = 0
5232 19:22:50.388740 6, 0xFFFF, sum = 0
5233 19:22:50.392200 7, 0xFFFF, sum = 0
5234 19:22:50.392283 8, 0xFFFF, sum = 0
5235 19:22:50.395460 9, 0xFFFF, sum = 0
5236 19:22:50.395543 10, 0x0, sum = 1
5237 19:22:50.398937 11, 0x0, sum = 2
5238 19:22:50.399020 12, 0x0, sum = 3
5239 19:22:50.401901 13, 0x0, sum = 4
5240 19:22:50.402011 best_step = 11
5241 19:22:50.402174
5242 19:22:50.402241 ==
5243 19:22:50.405628 Dram Type= 6, Freq= 0, CH_0, rank 1
5244 19:22:50.408762 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5245 19:22:50.408844 ==
5246 19:22:50.411666 RX Vref Scan: 0
5247 19:22:50.411758
5248 19:22:50.415626 RX Vref 0 -> 0, step: 1
5249 19:22:50.415707
5250 19:22:50.415772 RX Delay -69 -> 252, step: 4
5251 19:22:50.423009 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5252 19:22:50.426580 iDelay=203, Bit 1, Center 96 (-1 ~ 194) 196
5253 19:22:50.429933 iDelay=203, Bit 2, Center 96 (3 ~ 190) 188
5254 19:22:50.433108 iDelay=203, Bit 3, Center 92 (-1 ~ 186) 188
5255 19:22:50.436707 iDelay=203, Bit 4, Center 100 (7 ~ 194) 188
5256 19:22:50.439865 iDelay=203, Bit 5, Center 88 (-5 ~ 182) 188
5257 19:22:50.446291 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5258 19:22:50.449700 iDelay=203, Bit 7, Center 108 (15 ~ 202) 188
5259 19:22:50.453060 iDelay=203, Bit 8, Center 76 (-9 ~ 162) 172
5260 19:22:50.456243 iDelay=203, Bit 9, Center 72 (-17 ~ 162) 180
5261 19:22:50.459987 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5262 19:22:50.466047 iDelay=203, Bit 11, Center 78 (-9 ~ 166) 176
5263 19:22:50.469669 iDelay=203, Bit 12, Center 94 (7 ~ 182) 176
5264 19:22:50.472636 iDelay=203, Bit 13, Center 90 (-1 ~ 182) 184
5265 19:22:50.476498 iDelay=203, Bit 14, Center 94 (3 ~ 186) 184
5266 19:22:50.479477 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5267 19:22:50.479560 ==
5268 19:22:50.482747 Dram Type= 6, Freq= 0, CH_0, rank 1
5269 19:22:50.489377 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5270 19:22:50.489460 ==
5271 19:22:50.489525 DQS Delay:
5272 19:22:50.492841 DQS0 = 0, DQS1 = 0
5273 19:22:50.492926 DQM Delay:
5274 19:22:50.492991 DQM0 = 97, DQM1 = 86
5275 19:22:50.496253 DQ Delay:
5276 19:22:50.499254 DQ0 =92, DQ1 =96, DQ2 =96, DQ3 =92
5277 19:22:50.502534 DQ4 =100, DQ5 =88, DQ6 =104, DQ7 =108
5278 19:22:50.505936 DQ8 =76, DQ9 =72, DQ10 =88, DQ11 =78
5279 19:22:50.509422 DQ12 =94, DQ13 =90, DQ14 =94, DQ15 =96
5280 19:22:50.509504
5281 19:22:50.509569
5282 19:22:50.515979 [DQSOSCAuto] RK1, (LSB)MR18= 0x2929, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 408 ps
5283 19:22:50.519404 CH0 RK1: MR19=505, MR18=2929
5284 19:22:50.525677 CH0_RK1: MR19=0x505, MR18=0x2929, DQSOSC=408, MR23=63, INC=65, DEC=43
5285 19:22:50.529376 [RxdqsGatingPostProcess] freq 933
5286 19:22:50.535677 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5287 19:22:50.535760 Pre-setting of DQS Precalculation
5288 19:22:50.542447 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5289 19:22:50.542530 ==
5290 19:22:50.545644 Dram Type= 6, Freq= 0, CH_1, rank 0
5291 19:22:50.548650 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5292 19:22:50.548733 ==
5293 19:22:50.555304 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5294 19:22:50.561697 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5295 19:22:50.565243 [CA 0] Center 37 (7~68) winsize 62
5296 19:22:50.568744 [CA 1] Center 37 (6~68) winsize 63
5297 19:22:50.571989 [CA 2] Center 34 (4~65) winsize 62
5298 19:22:50.575265 [CA 3] Center 34 (3~65) winsize 63
5299 19:22:50.578411 [CA 4] Center 33 (2~64) winsize 63
5300 19:22:50.581702 [CA 5] Center 33 (3~64) winsize 62
5301 19:22:50.581784
5302 19:22:50.585234 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5303 19:22:50.585316
5304 19:22:50.588597 [CATrainingPosCal] consider 1 rank data
5305 19:22:50.591891 u2DelayCellTimex100 = 270/100 ps
5306 19:22:50.594966 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5307 19:22:50.598801 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5308 19:22:50.601603 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5309 19:22:50.604840 CA3 delay=34 (3~65),Diff = 1 PI (6 cell)
5310 19:22:50.608079 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5311 19:22:50.615010 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5312 19:22:50.615092
5313 19:22:50.618035 CA PerBit enable=1, Macro0, CA PI delay=33
5314 19:22:50.618132
5315 19:22:50.621753 [CBTSetCACLKResult] CA Dly = 33
5316 19:22:50.621835 CS Dly: 5 (0~36)
5317 19:22:50.621900 ==
5318 19:22:50.625034 Dram Type= 6, Freq= 0, CH_1, rank 1
5319 19:22:50.628047 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5320 19:22:50.631227 ==
5321 19:22:50.634933 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5322 19:22:50.641291 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5323 19:22:50.644561 [CA 0] Center 37 (6~68) winsize 63
5324 19:22:50.647746 [CA 1] Center 37 (6~68) winsize 63
5325 19:22:50.651543 [CA 2] Center 34 (4~65) winsize 62
5326 19:22:50.654528 [CA 3] Center 34 (3~65) winsize 63
5327 19:22:50.657850 [CA 4] Center 33 (3~64) winsize 62
5328 19:22:50.661313 [CA 5] Center 32 (2~63) winsize 62
5329 19:22:50.661394
5330 19:22:50.664486 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5331 19:22:50.664569
5332 19:22:50.668026 [CATrainingPosCal] consider 2 rank data
5333 19:22:50.671156 u2DelayCellTimex100 = 270/100 ps
5334 19:22:50.674164 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5335 19:22:50.677683 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5336 19:22:50.680845 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5337 19:22:50.687432 CA3 delay=34 (3~65),Diff = 1 PI (6 cell)
5338 19:22:50.690948 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5339 19:22:50.693952 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5340 19:22:50.694094
5341 19:22:50.697447 CA PerBit enable=1, Macro0, CA PI delay=33
5342 19:22:50.697530
5343 19:22:50.700897 [CBTSetCACLKResult] CA Dly = 33
5344 19:22:50.700979 CS Dly: 5 (0~37)
5345 19:22:50.701044
5346 19:22:50.703708 ----->DramcWriteLeveling(PI) begin...
5347 19:22:50.707321 ==
5348 19:22:50.710660 Dram Type= 6, Freq= 0, CH_1, rank 0
5349 19:22:50.714049 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5350 19:22:50.714146 ==
5351 19:22:50.716777 Write leveling (Byte 0): 23 => 23
5352 19:22:50.720795 Write leveling (Byte 1): 23 => 23
5353 19:22:50.723732 DramcWriteLeveling(PI) end<-----
5354 19:22:50.723813
5355 19:22:50.723879 ==
5356 19:22:50.726762 Dram Type= 6, Freq= 0, CH_1, rank 0
5357 19:22:50.730151 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5358 19:22:50.730235 ==
5359 19:22:50.733837 [Gating] SW mode calibration
5360 19:22:50.740104 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5361 19:22:50.746566 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5362 19:22:50.749732 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5363 19:22:50.753428 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5364 19:22:50.760356 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5365 19:22:50.763282 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5366 19:22:50.766191 0 10 16 | B1->B0 | 3434 3030 | 1 0 | (1 0) (1 0)
5367 19:22:50.773194 0 10 20 | B1->B0 | 3434 2323 | 1 0 | (0 1) (1 0)
5368 19:22:50.776445 0 10 24 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
5369 19:22:50.779606 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5370 19:22:50.786490 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5371 19:22:50.789598 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5372 19:22:50.792879 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5373 19:22:50.800079 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5374 19:22:50.802759 0 11 16 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
5375 19:22:50.805876 0 11 20 | B1->B0 | 2828 4242 | 1 0 | (0 0) (0 0)
5376 19:22:50.813276 0 11 24 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
5377 19:22:50.815921 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5378 19:22:50.819491 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5379 19:22:50.826114 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5380 19:22:50.829435 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5381 19:22:50.832386 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5382 19:22:50.839322 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5383 19:22:50.842246 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5384 19:22:50.845819 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5385 19:22:50.852374 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 19:22:50.855578 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 19:22:50.859116 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 19:22:50.865344 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 19:22:50.868920 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 19:22:50.872165 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 19:22:50.879211 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 19:22:50.881935 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 19:22:50.885732 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 19:22:50.892028 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 19:22:50.895689 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 19:22:50.898475 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 19:22:50.905337 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 19:22:50.908650 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5399 19:22:50.912007 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5400 19:22:50.915382 Total UI for P1: 0, mck2ui 16
5401 19:22:50.918309 best dqsien dly found for B0: ( 0, 14, 16)
5402 19:22:50.925368 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5403 19:22:50.925793 Total UI for P1: 0, mck2ui 16
5404 19:22:50.928382 best dqsien dly found for B1: ( 0, 14, 18)
5405 19:22:50.935020 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5406 19:22:50.938384 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5407 19:22:50.938807
5408 19:22:50.941984 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5409 19:22:50.945148 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5410 19:22:50.948068 [Gating] SW calibration Done
5411 19:22:50.948490 ==
5412 19:22:50.951755 Dram Type= 6, Freq= 0, CH_1, rank 0
5413 19:22:50.954985 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5414 19:22:50.955407 ==
5415 19:22:50.958259 RX Vref Scan: 0
5416 19:22:50.958710
5417 19:22:50.959205 RX Vref 0 -> 0, step: 1
5418 19:22:50.959548
5419 19:22:50.961498 RX Delay -80 -> 252, step: 8
5420 19:22:50.965055 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5421 19:22:50.971543 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5422 19:22:50.974591 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5423 19:22:50.977899 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5424 19:22:50.981431 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5425 19:22:50.984461 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5426 19:22:50.991497 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5427 19:22:50.995135 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5428 19:22:50.997990 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5429 19:22:51.001090 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5430 19:22:51.004164 iDelay=208, Bit 10, Center 87 (-16 ~ 191) 208
5431 19:22:51.011415 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5432 19:22:51.014413 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5433 19:22:51.017688 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5434 19:22:51.021478 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5435 19:22:51.024331 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5436 19:22:51.024899 ==
5437 19:22:51.027883 Dram Type= 6, Freq= 0, CH_1, rank 0
5438 19:22:51.034411 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5439 19:22:51.034992 ==
5440 19:22:51.035367 DQS Delay:
5441 19:22:51.037726 DQS0 = 0, DQS1 = 0
5442 19:22:51.038237 DQM Delay:
5443 19:22:51.038623 DQM0 = 94, DQM1 = 86
5444 19:22:51.040815 DQ Delay:
5445 19:22:51.044247 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5446 19:22:51.047539 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5447 19:22:51.050803 DQ8 =71, DQ9 =75, DQ10 =87, DQ11 =79
5448 19:22:51.054247 DQ12 =91, DQ13 =99, DQ14 =91, DQ15 =99
5449 19:22:51.054820
5450 19:22:51.055190
5451 19:22:51.055533 ==
5452 19:22:51.057316 Dram Type= 6, Freq= 0, CH_1, rank 0
5453 19:22:51.060716 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5454 19:22:51.061326 ==
5455 19:22:51.061882
5456 19:22:51.062314
5457 19:22:51.064157 TX Vref Scan disable
5458 19:22:51.067154 == TX Byte 0 ==
5459 19:22:51.070825 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5460 19:22:51.073895 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5461 19:22:51.076905 == TX Byte 1 ==
5462 19:22:51.080216 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5463 19:22:51.083352 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5464 19:22:51.083836 ==
5465 19:22:51.087180 Dram Type= 6, Freq= 0, CH_1, rank 0
5466 19:22:51.090204 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5467 19:22:51.093750 ==
5468 19:22:51.094387
5469 19:22:51.094768
5470 19:22:51.095112 TX Vref Scan disable
5471 19:22:51.097171 == TX Byte 0 ==
5472 19:22:51.100369 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5473 19:22:51.106890 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5474 19:22:51.107356 == TX Byte 1 ==
5475 19:22:51.110363 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5476 19:22:51.117363 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5477 19:22:51.118011
5478 19:22:51.118605 [DATLAT]
5479 19:22:51.118989 Freq=933, CH1 RK0
5480 19:22:51.119340
5481 19:22:51.120075 DATLAT Default: 0xd
5482 19:22:51.123855 0, 0xFFFF, sum = 0
5483 19:22:51.124430 1, 0xFFFF, sum = 0
5484 19:22:51.126539 2, 0xFFFF, sum = 0
5485 19:22:51.127010 3, 0xFFFF, sum = 0
5486 19:22:51.130108 4, 0xFFFF, sum = 0
5487 19:22:51.130685 5, 0xFFFF, sum = 0
5488 19:22:51.133866 6, 0xFFFF, sum = 0
5489 19:22:51.134512 7, 0xFFFF, sum = 0
5490 19:22:51.136668 8, 0xFFFF, sum = 0
5491 19:22:51.137260 9, 0xFFFF, sum = 0
5492 19:22:51.140149 10, 0x0, sum = 1
5493 19:22:51.140726 11, 0x0, sum = 2
5494 19:22:51.143204 12, 0x0, sum = 3
5495 19:22:51.143676 13, 0x0, sum = 4
5496 19:22:51.146843 best_step = 11
5497 19:22:51.147405
5498 19:22:51.147783 ==
5499 19:22:51.149979 Dram Type= 6, Freq= 0, CH_1, rank 0
5500 19:22:51.153160 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5501 19:22:51.153730 ==
5502 19:22:51.154143 RX Vref Scan: 1
5503 19:22:51.156597
5504 19:22:51.157160 RX Vref 0 -> 0, step: 1
5505 19:22:51.157535
5506 19:22:51.159873 RX Delay -69 -> 252, step: 4
5507 19:22:51.160439
5508 19:22:51.162963 Set Vref, RX VrefLevel [Byte0]: 56
5509 19:22:51.166534 [Byte1]: 49
5510 19:22:51.169690
5511 19:22:51.170249 Final RX Vref Byte 0 = 56 to rank0
5512 19:22:51.172792 Final RX Vref Byte 1 = 49 to rank0
5513 19:22:51.176273 Final RX Vref Byte 0 = 56 to rank1
5514 19:22:51.179618 Final RX Vref Byte 1 = 49 to rank1==
5515 19:22:51.182977 Dram Type= 6, Freq= 0, CH_1, rank 0
5516 19:22:51.189183 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5517 19:22:51.189745 ==
5518 19:22:51.190169 DQS Delay:
5519 19:22:51.193084 DQS0 = 0, DQS1 = 0
5520 19:22:51.193653 DQM Delay:
5521 19:22:51.194130 DQM0 = 94, DQM1 = 88
5522 19:22:51.196473 DQ Delay:
5523 19:22:51.199387 DQ0 =96, DQ1 =88, DQ2 =86, DQ3 =92
5524 19:22:51.202371 DQ4 =94, DQ5 =104, DQ6 =100, DQ7 =92
5525 19:22:51.205794 DQ8 =72, DQ9 =76, DQ10 =90, DQ11 =80
5526 19:22:51.209749 DQ12 =94, DQ13 =98, DQ14 =96, DQ15 =98
5527 19:22:51.210424
5528 19:22:51.210809
5529 19:22:51.216060 [DQSOSCAuto] RK0, (LSB)MR18= 0x3535, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
5530 19:22:51.218958 CH1 RK0: MR19=505, MR18=3535
5531 19:22:51.226249 CH1_RK0: MR19=0x505, MR18=0x3535, DQSOSC=405, MR23=63, INC=66, DEC=44
5532 19:22:51.226817
5533 19:22:51.228886 ----->DramcWriteLeveling(PI) begin...
5534 19:22:51.229358 ==
5535 19:22:51.232702 Dram Type= 6, Freq= 0, CH_1, rank 1
5536 19:22:51.235772 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5537 19:22:51.236239 ==
5538 19:22:51.238786 Write leveling (Byte 0): 24 => 24
5539 19:22:51.242223 Write leveling (Byte 1): 24 => 24
5540 19:22:51.245683 DramcWriteLeveling(PI) end<-----
5541 19:22:51.246176
5542 19:22:51.246624 ==
5543 19:22:51.249119 Dram Type= 6, Freq= 0, CH_1, rank 1
5544 19:22:51.252067 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5545 19:22:51.255236 ==
5546 19:22:51.255706 [Gating] SW mode calibration
5547 19:22:51.265106 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5548 19:22:51.268740 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5549 19:22:51.271794 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5550 19:22:51.278066 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5551 19:22:51.281869 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5552 19:22:51.285320 0 10 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5553 19:22:51.291455 0 10 16 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 0)
5554 19:22:51.294727 0 10 20 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
5555 19:22:51.298267 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5556 19:22:51.305145 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5557 19:22:51.308533 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5558 19:22:51.311539 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5559 19:22:51.317870 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5560 19:22:51.321514 0 11 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5561 19:22:51.324520 0 11 16 | B1->B0 | 2323 3939 | 0 1 | (0 0) (0 0)
5562 19:22:51.331155 0 11 20 | B1->B0 | 3838 4646 | 1 0 | (0 0) (0 0)
5563 19:22:51.334402 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5564 19:22:51.338305 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5565 19:22:51.344830 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5566 19:22:51.348109 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5567 19:22:51.351548 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5568 19:22:51.357982 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5569 19:22:51.360964 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5570 19:22:51.364486 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5571 19:22:51.371134 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5572 19:22:51.374469 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5573 19:22:51.377316 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5574 19:22:51.384433 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5575 19:22:51.387365 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5576 19:22:51.390684 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5577 19:22:51.397715 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5578 19:22:51.400538 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5579 19:22:51.403709 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5580 19:22:51.410833 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 19:22:51.414070 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 19:22:51.417599 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 19:22:51.423810 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 19:22:51.427146 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 19:22:51.430564 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5586 19:22:51.437134 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5587 19:22:51.437719 Total UI for P1: 0, mck2ui 16
5588 19:22:51.443693 best dqsien dly found for B0: ( 0, 14, 16)
5589 19:22:51.446906 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5590 19:22:51.450215 Total UI for P1: 0, mck2ui 16
5591 19:22:51.453756 best dqsien dly found for B1: ( 0, 14, 18)
5592 19:22:51.456813 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5593 19:22:51.460314 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5594 19:22:51.460892
5595 19:22:51.463231 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5596 19:22:51.466989 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5597 19:22:51.469851 [Gating] SW calibration Done
5598 19:22:51.470362 ==
5599 19:22:51.473435 Dram Type= 6, Freq= 0, CH_1, rank 1
5600 19:22:51.480040 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5601 19:22:51.480617 ==
5602 19:22:51.480995 RX Vref Scan: 0
5603 19:22:51.481344
5604 19:22:51.483497 RX Vref 0 -> 0, step: 1
5605 19:22:51.484067
5606 19:22:51.486860 RX Delay -80 -> 252, step: 8
5607 19:22:51.490197 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5608 19:22:51.493376 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5609 19:22:51.496807 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5610 19:22:51.500586 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5611 19:22:51.506386 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5612 19:22:51.509987 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5613 19:22:51.513144 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5614 19:22:51.516100 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5615 19:22:51.519474 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5616 19:22:51.522734 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5617 19:22:51.529845 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5618 19:22:51.532799 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5619 19:22:51.535983 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5620 19:22:51.539405 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5621 19:22:51.542793 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5622 19:22:51.549362 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5623 19:22:51.549957 ==
5624 19:22:51.552730 Dram Type= 6, Freq= 0, CH_1, rank 1
5625 19:22:51.555688 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5626 19:22:51.556161 ==
5627 19:22:51.556536 DQS Delay:
5628 19:22:51.559059 DQS0 = 0, DQS1 = 0
5629 19:22:51.559609 DQM Delay:
5630 19:22:51.562798 DQM0 = 96, DQM1 = 87
5631 19:22:51.563538 DQ Delay:
5632 19:22:51.566114 DQ0 =99, DQ1 =91, DQ2 =87, DQ3 =95
5633 19:22:51.569114 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =91
5634 19:22:51.572674 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =75
5635 19:22:51.575858 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =95
5636 19:22:51.576332
5637 19:22:51.576716
5638 19:22:51.577063 ==
5639 19:22:51.579041 Dram Type= 6, Freq= 0, CH_1, rank 1
5640 19:22:51.582138 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5641 19:22:51.585646 ==
5642 19:22:51.586163
5643 19:22:51.586564
5644 19:22:51.586916 TX Vref Scan disable
5645 19:22:51.588883 == TX Byte 0 ==
5646 19:22:51.592267 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5647 19:22:51.595960 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5648 19:22:51.598896 == TX Byte 1 ==
5649 19:22:51.602283 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5650 19:22:51.605288 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5651 19:22:51.609190 ==
5652 19:22:51.609760 Dram Type= 6, Freq= 0, CH_1, rank 1
5653 19:22:51.615560 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5654 19:22:51.616138 ==
5655 19:22:51.616515
5656 19:22:51.616859
5657 19:22:51.618634 TX Vref Scan disable
5658 19:22:51.619100 == TX Byte 0 ==
5659 19:22:51.625564 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5660 19:22:51.629214 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5661 19:22:51.629787 == TX Byte 1 ==
5662 19:22:51.635310 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5663 19:22:51.638249 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5664 19:22:51.638716
5665 19:22:51.639082 [DATLAT]
5666 19:22:51.642193 Freq=933, CH1 RK1
5667 19:22:51.642659
5668 19:22:51.643029 DATLAT Default: 0xb
5669 19:22:51.645041 0, 0xFFFF, sum = 0
5670 19:22:51.645514 1, 0xFFFF, sum = 0
5671 19:22:51.648567 2, 0xFFFF, sum = 0
5672 19:22:51.649141 3, 0xFFFF, sum = 0
5673 19:22:51.651696 4, 0xFFFF, sum = 0
5674 19:22:51.652168 5, 0xFFFF, sum = 0
5675 19:22:51.655059 6, 0xFFFF, sum = 0
5676 19:22:51.655606 7, 0xFFFF, sum = 0
5677 19:22:51.658560 8, 0xFFFF, sum = 0
5678 19:22:51.659186 9, 0xFFFF, sum = 0
5679 19:22:51.661779 10, 0x0, sum = 1
5680 19:22:51.662307 11, 0x0, sum = 2
5681 19:22:51.664871 12, 0x0, sum = 3
5682 19:22:51.665344 13, 0x0, sum = 4
5683 19:22:51.668215 best_step = 11
5684 19:22:51.668822
5685 19:22:51.669210 ==
5686 19:22:51.671552 Dram Type= 6, Freq= 0, CH_1, rank 1
5687 19:22:51.675002 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5688 19:22:51.675474 ==
5689 19:22:51.678079 RX Vref Scan: 0
5690 19:22:51.678548
5691 19:22:51.678923 RX Vref 0 -> 0, step: 1
5692 19:22:51.679272
5693 19:22:51.681398 RX Delay -69 -> 252, step: 4
5694 19:22:51.689150 iDelay=203, Bit 0, Center 96 (3 ~ 190) 188
5695 19:22:51.692862 iDelay=203, Bit 1, Center 92 (-1 ~ 186) 188
5696 19:22:51.695466 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5697 19:22:51.698612 iDelay=203, Bit 3, Center 92 (-1 ~ 186) 188
5698 19:22:51.702337 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5699 19:22:51.705702 iDelay=203, Bit 5, Center 106 (11 ~ 202) 192
5700 19:22:51.712436 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5701 19:22:51.715625 iDelay=203, Bit 7, Center 92 (-1 ~ 186) 188
5702 19:22:51.718765 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5703 19:22:51.721967 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5704 19:22:51.725096 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5705 19:22:51.732126 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5706 19:22:51.735460 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5707 19:22:51.738687 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180
5708 19:22:51.741997 iDelay=203, Bit 14, Center 94 (-1 ~ 190) 192
5709 19:22:51.745128 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5710 19:22:51.745697 ==
5711 19:22:51.748597 Dram Type= 6, Freq= 0, CH_1, rank 1
5712 19:22:51.754977 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5713 19:22:51.755570 ==
5714 19:22:51.755976 DQS Delay:
5715 19:22:51.758144 DQS0 = 0, DQS1 = 0
5716 19:22:51.758609 DQM Delay:
5717 19:22:51.761995 DQM0 = 95, DQM1 = 87
5718 19:22:51.762618 DQ Delay:
5719 19:22:51.764914 DQ0 =96, DQ1 =92, DQ2 =88, DQ3 =92
5720 19:22:51.768414 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =92
5721 19:22:51.771750 DQ8 =74, DQ9 =74, DQ10 =88, DQ11 =80
5722 19:22:51.775048 DQ12 =96, DQ13 =96, DQ14 =94, DQ15 =96
5723 19:22:51.775513
5724 19:22:51.775880
5725 19:22:51.782341 [DQSOSCAuto] RK1, (LSB)MR18= 0x2828, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 409 ps
5726 19:22:51.785021 CH1 RK1: MR19=505, MR18=2828
5727 19:22:51.791758 CH1_RK1: MR19=0x505, MR18=0x2828, DQSOSC=409, MR23=63, INC=64, DEC=43
5728 19:22:51.794924 [RxdqsGatingPostProcess] freq 933
5729 19:22:51.801427 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5730 19:22:51.801988 Pre-setting of DQS Precalculation
5731 19:22:51.808089 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5732 19:22:51.814765 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5733 19:22:51.821198 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5734 19:22:51.821775
5735 19:22:51.822208
5736 19:22:51.824506 [Calibration Summary] 1866 Mbps
5737 19:22:51.828207 CH 0, Rank 0
5738 19:22:51.828805 SW Impedance : PASS
5739 19:22:51.830882 DUTY Scan : NO K
5740 19:22:51.834994 ZQ Calibration : PASS
5741 19:22:51.835566 Jitter Meter : NO K
5742 19:22:51.837745 CBT Training : PASS
5743 19:22:51.841328 Write leveling : PASS
5744 19:22:51.841902 RX DQS gating : PASS
5745 19:22:51.844497 RX DQ/DQS(RDDQC) : PASS
5746 19:22:51.847911 TX DQ/DQS : PASS
5747 19:22:51.848487 RX DATLAT : PASS
5748 19:22:51.850933 RX DQ/DQS(Engine): PASS
5749 19:22:51.851412 TX OE : NO K
5750 19:22:51.854098 All Pass.
5751 19:22:51.854568
5752 19:22:51.854941 CH 0, Rank 1
5753 19:22:51.857603 SW Impedance : PASS
5754 19:22:51.858226 DUTY Scan : NO K
5755 19:22:51.861317 ZQ Calibration : PASS
5756 19:22:51.864263 Jitter Meter : NO K
5757 19:22:51.864730 CBT Training : PASS
5758 19:22:51.867813 Write leveling : PASS
5759 19:22:51.870992 RX DQS gating : PASS
5760 19:22:51.871467 RX DQ/DQS(RDDQC) : PASS
5761 19:22:51.874578 TX DQ/DQS : PASS
5762 19:22:51.877495 RX DATLAT : PASS
5763 19:22:51.878137 RX DQ/DQS(Engine): PASS
5764 19:22:51.880816 TX OE : NO K
5765 19:22:51.881285 All Pass.
5766 19:22:51.881656
5767 19:22:51.884322 CH 1, Rank 0
5768 19:22:51.884894 SW Impedance : PASS
5769 19:22:51.887628 DUTY Scan : NO K
5770 19:22:51.891171 ZQ Calibration : PASS
5771 19:22:51.891744 Jitter Meter : NO K
5772 19:22:51.894065 CBT Training : PASS
5773 19:22:51.897472 Write leveling : PASS
5774 19:22:51.897939 RX DQS gating : PASS
5775 19:22:51.900732 RX DQ/DQS(RDDQC) : PASS
5776 19:22:51.901293 TX DQ/DQS : PASS
5777 19:22:51.903786 RX DATLAT : PASS
5778 19:22:51.907102 RX DQ/DQS(Engine): PASS
5779 19:22:51.907794 TX OE : NO K
5780 19:22:51.910567 All Pass.
5781 19:22:51.911135
5782 19:22:51.911506 CH 1, Rank 1
5783 19:22:51.914016 SW Impedance : PASS
5784 19:22:51.914644 DUTY Scan : NO K
5785 19:22:51.917323 ZQ Calibration : PASS
5786 19:22:51.920832 Jitter Meter : NO K
5787 19:22:51.921400 CBT Training : PASS
5788 19:22:51.923924 Write leveling : PASS
5789 19:22:51.927290 RX DQS gating : PASS
5790 19:22:51.927761 RX DQ/DQS(RDDQC) : PASS
5791 19:22:51.930748 TX DQ/DQS : PASS
5792 19:22:51.933975 RX DATLAT : PASS
5793 19:22:51.934594 RX DQ/DQS(Engine): PASS
5794 19:22:51.936886 TX OE : NO K
5795 19:22:51.937359 All Pass.
5796 19:22:51.937733
5797 19:22:51.940515 DramC Write-DBI off
5798 19:22:51.943527 PER_BANK_REFRESH: Hybrid Mode
5799 19:22:51.943995 TX_TRACKING: ON
5800 19:22:51.953713 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5801 19:22:51.956761 [FAST_K] Save calibration result to emmc
5802 19:22:51.960134 dramc_set_vcore_voltage set vcore to 650000
5803 19:22:51.963682 Read voltage for 400, 6
5804 19:22:51.964254 Vio18 = 0
5805 19:22:51.964628 Vcore = 650000
5806 19:22:51.966498 Vdram = 0
5807 19:22:51.966966 Vddq = 0
5808 19:22:51.967338 Vmddr = 0
5809 19:22:51.973579 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5810 19:22:51.976863 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5811 19:22:51.980374 MEM_TYPE=3, freq_sel=20
5812 19:22:51.983918 sv_algorithm_assistance_LP4_800
5813 19:22:51.986891 ============ PULL DRAM RESETB DOWN ============
5814 19:22:51.990221 ========== PULL DRAM RESETB DOWN end =========
5815 19:22:51.996609 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5816 19:22:52.000264 ===================================
5817 19:22:52.003281 LPDDR4 DRAM CONFIGURATION
5818 19:22:52.006388 ===================================
5819 19:22:52.007083 EX_ROW_EN[0] = 0x0
5820 19:22:52.009529 EX_ROW_EN[1] = 0x0
5821 19:22:52.010000 LP4Y_EN = 0x0
5822 19:22:52.012997 WORK_FSP = 0x0
5823 19:22:52.013566 WL = 0x2
5824 19:22:52.016502 RL = 0x2
5825 19:22:52.017087 BL = 0x2
5826 19:22:52.019796 RPST = 0x0
5827 19:22:52.020266 RD_PRE = 0x0
5828 19:22:52.023252 WR_PRE = 0x1
5829 19:22:52.023716 WR_PST = 0x0
5830 19:22:52.026222 DBI_WR = 0x0
5831 19:22:52.026740 DBI_RD = 0x0
5832 19:22:52.030396 OTF = 0x1
5833 19:22:52.033184 ===================================
5834 19:22:52.036736 ===================================
5835 19:22:52.037308 ANA top config
5836 19:22:52.039778 ===================================
5837 19:22:52.043051 DLL_ASYNC_EN = 0
5838 19:22:52.046672 ALL_SLAVE_EN = 1
5839 19:22:52.049814 NEW_RANK_MODE = 1
5840 19:22:52.050432 DLL_IDLE_MODE = 1
5841 19:22:52.052677 LP45_APHY_COMB_EN = 1
5842 19:22:52.056451 TX_ODT_DIS = 1
5843 19:22:52.060015 NEW_8X_MODE = 1
5844 19:22:52.062998 ===================================
5845 19:22:52.066356 ===================================
5846 19:22:52.069652 data_rate = 800
5847 19:22:52.072468 CKR = 1
5848 19:22:52.072935 DQ_P2S_RATIO = 4
5849 19:22:52.075790 ===================================
5850 19:22:52.079341 CA_P2S_RATIO = 4
5851 19:22:52.082983 DQ_CA_OPEN = 0
5852 19:22:52.086122 DQ_SEMI_OPEN = 1
5853 19:22:52.089547 CA_SEMI_OPEN = 1
5854 19:22:52.092548 CA_FULL_RATE = 0
5855 19:22:52.093013 DQ_CKDIV4_EN = 0
5856 19:22:52.096404 CA_CKDIV4_EN = 1
5857 19:22:52.099475 CA_PREDIV_EN = 0
5858 19:22:52.102646 PH8_DLY = 0
5859 19:22:52.105877 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5860 19:22:52.108927 DQ_AAMCK_DIV = 0
5861 19:22:52.109411 CA_AAMCK_DIV = 0
5862 19:22:52.113219 CA_ADMCK_DIV = 4
5863 19:22:52.116154 DQ_TRACK_CA_EN = 0
5864 19:22:52.119479 CA_PICK = 800
5865 19:22:52.122191 CA_MCKIO = 400
5866 19:22:52.126502 MCKIO_SEMI = 400
5867 19:22:52.129260 PLL_FREQ = 3016
5868 19:22:52.129832 DQ_UI_PI_RATIO = 32
5869 19:22:52.132407 CA_UI_PI_RATIO = 32
5870 19:22:52.135634 ===================================
5871 19:22:52.138718 ===================================
5872 19:22:52.142432 memory_type:LPDDR4
5873 19:22:52.145500 GP_NUM : 10
5874 19:22:52.146202 SRAM_EN : 1
5875 19:22:52.149219 MD32_EN : 0
5876 19:22:52.151880 ===================================
5877 19:22:52.155334 [ANA_INIT] >>>>>>>>>>>>>>
5878 19:22:52.158857 <<<<<< [CONFIGURE PHASE]: ANA_TX
5879 19:22:52.162173 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5880 19:22:52.165330 ===================================
5881 19:22:52.165908 data_rate = 800,PCW = 0X7400
5882 19:22:52.168990 ===================================
5883 19:22:52.171912 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5884 19:22:52.178876 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5885 19:22:52.188658 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5886 19:22:52.195369 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5887 19:22:52.198379 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5888 19:22:52.201779 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5889 19:22:52.204788 [ANA_INIT] flow start
5890 19:22:52.205262 [ANA_INIT] PLL >>>>>>>>
5891 19:22:52.208214 [ANA_INIT] PLL <<<<<<<<
5892 19:22:52.211569 [ANA_INIT] MIDPI >>>>>>>>
5893 19:22:52.212148 [ANA_INIT] MIDPI <<<<<<<<
5894 19:22:52.214895 [ANA_INIT] DLL >>>>>>>>
5895 19:22:52.218263 [ANA_INIT] flow end
5896 19:22:52.221400 ============ LP4 DIFF to SE enter ============
5897 19:22:52.225242 ============ LP4 DIFF to SE exit ============
5898 19:22:52.228450 [ANA_INIT] <<<<<<<<<<<<<
5899 19:22:52.231309 [Flow] Enable top DCM control >>>>>
5900 19:22:52.235051 [Flow] Enable top DCM control <<<<<
5901 19:22:52.238197 Enable DLL master slave shuffle
5902 19:22:52.241931 ==============================================================
5903 19:22:52.244902 Gating Mode config
5904 19:22:52.251345 ==============================================================
5905 19:22:52.251989 Config description:
5906 19:22:52.261175 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5907 19:22:52.267705 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5908 19:22:52.274908 SELPH_MODE 0: By rank 1: By Phase
5909 19:22:52.277601 ==============================================================
5910 19:22:52.281719 GAT_TRACK_EN = 0
5911 19:22:52.284485 RX_GATING_MODE = 2
5912 19:22:52.287948 RX_GATING_TRACK_MODE = 2
5913 19:22:52.291037 SELPH_MODE = 1
5914 19:22:52.294568 PICG_EARLY_EN = 1
5915 19:22:52.297785 VALID_LAT_VALUE = 1
5916 19:22:52.301211 ==============================================================
5917 19:22:52.304319 Enter into Gating configuration >>>>
5918 19:22:52.307559 Exit from Gating configuration <<<<
5919 19:22:52.311215 Enter into DVFS_PRE_config >>>>>
5920 19:22:52.324293 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5921 19:22:52.327569 Exit from DVFS_PRE_config <<<<<
5922 19:22:52.330498 Enter into PICG configuration >>>>
5923 19:22:52.330965 Exit from PICG configuration <<<<
5924 19:22:52.334117 [RX_INPUT] configuration >>>>>
5925 19:22:52.337469 [RX_INPUT] configuration <<<<<
5926 19:22:52.344193 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5927 19:22:52.347596 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5928 19:22:52.353776 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5929 19:22:52.360463 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5930 19:22:52.367158 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5931 19:22:52.373425 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5932 19:22:52.376642 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5933 19:22:52.380101 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5934 19:22:52.387119 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5935 19:22:52.390099 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5936 19:22:52.393294 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5937 19:22:52.396700 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5938 19:22:52.400438 ===================================
5939 19:22:52.403106 LPDDR4 DRAM CONFIGURATION
5940 19:22:52.406380 ===================================
5941 19:22:52.409840 EX_ROW_EN[0] = 0x0
5942 19:22:52.410355 EX_ROW_EN[1] = 0x0
5943 19:22:52.413249 LP4Y_EN = 0x0
5944 19:22:52.413819 WORK_FSP = 0x0
5945 19:22:52.417241 WL = 0x2
5946 19:22:52.417806 RL = 0x2
5947 19:22:52.419896 BL = 0x2
5948 19:22:52.420364 RPST = 0x0
5949 19:22:52.422924 RD_PRE = 0x0
5950 19:22:52.423389 WR_PRE = 0x1
5951 19:22:52.426536 WR_PST = 0x0
5952 19:22:52.429968 DBI_WR = 0x0
5953 19:22:52.430469 DBI_RD = 0x0
5954 19:22:52.433144 OTF = 0x1
5955 19:22:52.436383 ===================================
5956 19:22:52.439793 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5957 19:22:52.442956 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5958 19:22:52.446910 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5959 19:22:52.449989 ===================================
5960 19:22:52.452930 LPDDR4 DRAM CONFIGURATION
5961 19:22:52.456139 ===================================
5962 19:22:52.459451 EX_ROW_EN[0] = 0x10
5963 19:22:52.459870 EX_ROW_EN[1] = 0x0
5964 19:22:52.463266 LP4Y_EN = 0x0
5965 19:22:52.463688 WORK_FSP = 0x0
5966 19:22:52.466313 WL = 0x2
5967 19:22:52.466734 RL = 0x2
5968 19:22:52.469500 BL = 0x2
5969 19:22:52.469916 RPST = 0x0
5970 19:22:52.472677 RD_PRE = 0x0
5971 19:22:52.473097 WR_PRE = 0x1
5972 19:22:52.476275 WR_PST = 0x0
5973 19:22:52.476694 DBI_WR = 0x0
5974 19:22:52.479491 DBI_RD = 0x0
5975 19:22:52.482843 OTF = 0x1
5976 19:22:52.486240 ===================================
5977 19:22:52.489502 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5978 19:22:52.494499 nWR fixed to 30
5979 19:22:52.497610 [ModeRegInit_LP4] CH0 RK0
5980 19:22:52.498063 [ModeRegInit_LP4] CH0 RK1
5981 19:22:52.501213 [ModeRegInit_LP4] CH1 RK0
5982 19:22:52.504142 [ModeRegInit_LP4] CH1 RK1
5983 19:22:52.504562 match AC timing 18
5984 19:22:52.510974 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
5985 19:22:52.514601 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5986 19:22:52.517965 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
5987 19:22:52.524965 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
5988 19:22:52.527750 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
5989 19:22:52.528279 ==
5990 19:22:52.531439 Dram Type= 6, Freq= 0, CH_0, rank 0
5991 19:22:52.534339 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
5992 19:22:52.534762 ==
5993 19:22:52.540973 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
5994 19:22:52.547550 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5995 19:22:52.550703 [CA 0] Center 36 (8~64) winsize 57
5996 19:22:52.554066 [CA 1] Center 36 (8~64) winsize 57
5997 19:22:52.557579 [CA 2] Center 36 (8~64) winsize 57
5998 19:22:52.561156 [CA 3] Center 36 (8~64) winsize 57
5999 19:22:52.561684 [CA 4] Center 36 (8~64) winsize 57
6000 19:22:52.564507 [CA 5] Center 36 (8~64) winsize 57
6001 19:22:52.565040
6002 19:22:52.570928 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6003 19:22:52.571349
6004 19:22:52.574070 [CATrainingPosCal] consider 1 rank data
6005 19:22:52.577681 u2DelayCellTimex100 = 270/100 ps
6006 19:22:52.580709 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6007 19:22:52.584537 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6008 19:22:52.587062 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6009 19:22:52.590676 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6010 19:22:52.594265 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6011 19:22:52.597658 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6012 19:22:52.598116
6013 19:22:52.600564 CA PerBit enable=1, Macro0, CA PI delay=36
6014 19:22:52.600995
6015 19:22:52.603853 [CBTSetCACLKResult] CA Dly = 36
6016 19:22:52.607276 CS Dly: 1 (0~32)
6017 19:22:52.607706 ==
6018 19:22:52.610457 Dram Type= 6, Freq= 0, CH_0, rank 1
6019 19:22:52.613554 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6020 19:22:52.613976 ==
6021 19:22:52.620357 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6022 19:22:52.627110 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6023 19:22:52.629935 [CA 0] Center 36 (8~64) winsize 57
6024 19:22:52.630403 [CA 1] Center 36 (8~64) winsize 57
6025 19:22:52.633714 [CA 2] Center 36 (8~64) winsize 57
6026 19:22:52.637016 [CA 3] Center 36 (8~64) winsize 57
6027 19:22:52.640447 [CA 4] Center 36 (8~64) winsize 57
6028 19:22:52.643523 [CA 5] Center 36 (8~64) winsize 57
6029 19:22:52.644049
6030 19:22:52.646863 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6031 19:22:52.647288
6032 19:22:52.653283 [CATrainingPosCal] consider 2 rank data
6033 19:22:52.653780 u2DelayCellTimex100 = 270/100 ps
6034 19:22:52.656457 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6035 19:22:52.663114 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6036 19:22:52.666283 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6037 19:22:52.669839 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6038 19:22:52.673009 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6039 19:22:52.676160 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6040 19:22:52.676585
6041 19:22:52.679542 CA PerBit enable=1, Macro0, CA PI delay=36
6042 19:22:52.679963
6043 19:22:52.683184 [CBTSetCACLKResult] CA Dly = 36
6044 19:22:52.686361 CS Dly: 1 (0~32)
6045 19:22:52.686858
6046 19:22:52.689660 ----->DramcWriteLeveling(PI) begin...
6047 19:22:52.690215 ==
6048 19:22:52.692649 Dram Type= 6, Freq= 0, CH_0, rank 0
6049 19:22:52.696383 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6050 19:22:52.696807 ==
6051 19:22:52.700021 Write leveling (Byte 0): 32 => 0
6052 19:22:52.702671 Write leveling (Byte 1): 32 => 0
6053 19:22:52.706248 DramcWriteLeveling(PI) end<-----
6054 19:22:52.706670
6055 19:22:52.707004 ==
6056 19:22:52.709431 Dram Type= 6, Freq= 0, CH_0, rank 0
6057 19:22:52.713262 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6058 19:22:52.713688 ==
6059 19:22:52.716338 [Gating] SW mode calibration
6060 19:22:52.722731 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6061 19:22:52.729457 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6062 19:22:52.732740 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6063 19:22:52.736195 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6064 19:22:52.742493 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6065 19:22:52.746337 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6066 19:22:52.749351 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6067 19:22:52.755570 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6068 19:22:52.759709 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6069 19:22:52.762939 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6070 19:22:52.769308 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6071 19:22:52.769901 Total UI for P1: 0, mck2ui 16
6072 19:22:52.775858 best dqsien dly found for B0: ( 0, 10, 16)
6073 19:22:52.776349 Total UI for P1: 0, mck2ui 16
6074 19:22:52.778998 best dqsien dly found for B1: ( 0, 10, 16)
6075 19:22:52.785846 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6076 19:22:52.788732 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6077 19:22:52.789265
6078 19:22:52.792705 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6079 19:22:52.795334 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6080 19:22:52.799384 [Gating] SW calibration Done
6081 19:22:52.800041 ==
6082 19:22:52.802294 Dram Type= 6, Freq= 0, CH_0, rank 0
6083 19:22:52.805498 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6084 19:22:52.805989 ==
6085 19:22:52.808605 RX Vref Scan: 0
6086 19:22:52.809125
6087 19:22:52.809689 RX Vref 0 -> 0, step: 1
6088 19:22:52.810105
6089 19:22:52.812101 RX Delay -410 -> 252, step: 16
6090 19:22:52.818935 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6091 19:22:52.822469 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6092 19:22:52.825362 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6093 19:22:52.828648 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6094 19:22:52.835062 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6095 19:22:52.838672 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496
6096 19:22:52.842218 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6097 19:22:52.845058 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6098 19:22:52.851457 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6099 19:22:52.855214 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6100 19:22:52.858337 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6101 19:22:52.861712 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6102 19:22:52.868120 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6103 19:22:52.871645 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6104 19:22:52.874862 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6105 19:22:52.881422 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6106 19:22:52.881888 ==
6107 19:22:52.884948 Dram Type= 6, Freq= 0, CH_0, rank 0
6108 19:22:52.887792 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6109 19:22:52.888220 ==
6110 19:22:52.888571 DQS Delay:
6111 19:22:52.891627 DQS0 = 51, DQS1 = 59
6112 19:22:52.892122 DQM Delay:
6113 19:22:52.894931 DQM0 = 11, DQM1 = 13
6114 19:22:52.895357 DQ Delay:
6115 19:22:52.897697 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6116 19:22:52.901267 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6117 19:22:52.904318 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6118 19:22:52.907784 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6119 19:22:52.908224
6120 19:22:52.908667
6121 19:22:52.909142 ==
6122 19:22:52.910988 Dram Type= 6, Freq= 0, CH_0, rank 0
6123 19:22:52.914434 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6124 19:22:52.914864 ==
6125 19:22:52.915201
6126 19:22:52.915515
6127 19:22:52.917915 TX Vref Scan disable
6128 19:22:52.921636 == TX Byte 0 ==
6129 19:22:52.924102 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6130 19:22:52.928395 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6131 19:22:52.930765 == TX Byte 1 ==
6132 19:22:52.934519 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6133 19:22:52.937582 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6134 19:22:52.938145 ==
6135 19:22:52.940789 Dram Type= 6, Freq= 0, CH_0, rank 0
6136 19:22:52.944203 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6137 19:22:52.947638 ==
6138 19:22:52.948120
6139 19:22:52.948460
6140 19:22:52.948978 TX Vref Scan disable
6141 19:22:52.950686 == TX Byte 0 ==
6142 19:22:52.954010 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6143 19:22:52.957354 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6144 19:22:52.960609 == TX Byte 1 ==
6145 19:22:52.964131 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6146 19:22:52.967388 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6147 19:22:52.967815
6148 19:22:52.970361 [DATLAT]
6149 19:22:52.970784 Freq=400, CH0 RK0
6150 19:22:52.971124
6151 19:22:52.973924 DATLAT Default: 0xf
6152 19:22:52.974465 0, 0xFFFF, sum = 0
6153 19:22:52.976875 1, 0xFFFF, sum = 0
6154 19:22:52.977320 2, 0xFFFF, sum = 0
6155 19:22:52.980645 3, 0xFFFF, sum = 0
6156 19:22:52.981179 4, 0xFFFF, sum = 0
6157 19:22:52.983712 5, 0xFFFF, sum = 0
6158 19:22:52.984144 6, 0xFFFF, sum = 0
6159 19:22:52.986880 7, 0xFFFF, sum = 0
6160 19:22:52.987408 8, 0xFFFF, sum = 0
6161 19:22:52.990478 9, 0xFFFF, sum = 0
6162 19:22:52.990982 10, 0xFFFF, sum = 0
6163 19:22:52.993836 11, 0xFFFF, sum = 0
6164 19:22:52.994311 12, 0x0, sum = 1
6165 19:22:52.997156 13, 0x0, sum = 2
6166 19:22:52.997692 14, 0x0, sum = 3
6167 19:22:53.000225 15, 0x0, sum = 4
6168 19:22:53.000661 best_step = 13
6169 19:22:53.000996
6170 19:22:53.001311 ==
6171 19:22:53.003316 Dram Type= 6, Freq= 0, CH_0, rank 0
6172 19:22:53.010130 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6173 19:22:53.010589 ==
6174 19:22:53.010927 RX Vref Scan: 1
6175 19:22:53.011238
6176 19:22:53.013475 RX Vref 0 -> 0, step: 1
6177 19:22:53.013894
6178 19:22:53.016929 RX Delay -359 -> 252, step: 8
6179 19:22:53.017449
6180 19:22:53.020238 Set Vref, RX VrefLevel [Byte0]: 52
6181 19:22:53.023419 [Byte1]: 46
6182 19:22:53.026835
6183 19:22:53.027312 Final RX Vref Byte 0 = 52 to rank0
6184 19:22:53.030120 Final RX Vref Byte 1 = 46 to rank0
6185 19:22:53.033639 Final RX Vref Byte 0 = 52 to rank1
6186 19:22:53.037440 Final RX Vref Byte 1 = 46 to rank1==
6187 19:22:53.040525 Dram Type= 6, Freq= 0, CH_0, rank 0
6188 19:22:53.047171 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6189 19:22:53.047758 ==
6190 19:22:53.048136 DQS Delay:
6191 19:22:53.050424 DQS0 = 52, DQS1 = 68
6192 19:22:53.050884 DQM Delay:
6193 19:22:53.051251 DQM0 = 8, DQM1 = 17
6194 19:22:53.053536 DQ Delay:
6195 19:22:53.053996 DQ0 =4, DQ1 =8, DQ2 =8, DQ3 =4
6196 19:22:53.057245 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6197 19:22:53.060114 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6198 19:22:53.063373 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =28
6199 19:22:53.063840
6200 19:22:53.064212
6201 19:22:53.073091 [DQSOSCAuto] RK0, (LSB)MR18= 0xaeae, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
6202 19:22:53.076740 CH0 RK0: MR19=C0C, MR18=AEAE
6203 19:22:53.083406 CH0_RK0: MR19=0xC0C, MR18=0xAEAE, DQSOSC=388, MR23=63, INC=392, DEC=261
6204 19:22:53.083951 ==
6205 19:22:53.086360 Dram Type= 6, Freq= 0, CH_0, rank 1
6206 19:22:53.090219 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6207 19:22:53.090803 ==
6208 19:22:53.093103 [Gating] SW mode calibration
6209 19:22:53.099554 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6210 19:22:53.106292 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6211 19:22:53.109483 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6212 19:22:53.112686 0 7 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
6213 19:22:53.119617 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6214 19:22:53.123115 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6215 19:22:53.125916 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6216 19:22:53.129737 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6217 19:22:53.136040 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6218 19:22:53.139376 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6219 19:22:53.142847 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6220 19:22:53.146074 Total UI for P1: 0, mck2ui 16
6221 19:22:53.149536 best dqsien dly found for B0: ( 0, 10, 16)
6222 19:22:53.152635 Total UI for P1: 0, mck2ui 16
6223 19:22:53.156054 best dqsien dly found for B1: ( 0, 10, 16)
6224 19:22:53.159147 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6225 19:22:53.166136 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6226 19:22:53.166863
6227 19:22:53.169003 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6228 19:22:53.172770 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6229 19:22:53.175725 [Gating] SW calibration Done
6230 19:22:53.176349 ==
6231 19:22:53.179289 Dram Type= 6, Freq= 0, CH_0, rank 1
6232 19:22:53.182336 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6233 19:22:53.182823 ==
6234 19:22:53.185637 RX Vref Scan: 0
6235 19:22:53.186137
6236 19:22:53.186516 RX Vref 0 -> 0, step: 1
6237 19:22:53.186861
6238 19:22:53.189225 RX Delay -410 -> 252, step: 16
6239 19:22:53.196043 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6240 19:22:53.198993 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6241 19:22:53.202111 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6242 19:22:53.205597 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6243 19:22:53.212393 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6244 19:22:53.215528 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6245 19:22:53.219065 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6246 19:22:53.222104 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6247 19:22:53.228924 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6248 19:22:53.232043 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6249 19:22:53.235283 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6250 19:22:53.238561 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6251 19:22:53.245118 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6252 19:22:53.248424 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6253 19:22:53.251564 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6254 19:22:53.255160 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6255 19:22:53.258660 ==
6256 19:22:53.261599 Dram Type= 6, Freq= 0, CH_0, rank 1
6257 19:22:53.265159 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6258 19:22:53.265707 ==
6259 19:22:53.266130 DQS Delay:
6260 19:22:53.268111 DQS0 = 43, DQS1 = 59
6261 19:22:53.268580 DQM Delay:
6262 19:22:53.271938 DQM0 = 6, DQM1 = 15
6263 19:22:53.272404 DQ Delay:
6264 19:22:53.275012 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6265 19:22:53.277958 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6266 19:22:53.281534 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6267 19:22:53.285083 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6268 19:22:53.285672
6269 19:22:53.286092
6270 19:22:53.286551 ==
6271 19:22:53.288004 Dram Type= 6, Freq= 0, CH_0, rank 1
6272 19:22:53.291620 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6273 19:22:53.292090 ==
6274 19:22:53.292525
6275 19:22:53.292952
6276 19:22:53.295278 TX Vref Scan disable
6277 19:22:53.295993 == TX Byte 0 ==
6278 19:22:53.301085 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6279 19:22:53.304574 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6280 19:22:53.305044 == TX Byte 1 ==
6281 19:22:53.311160 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6282 19:22:53.314326 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6283 19:22:53.314795 ==
6284 19:22:53.317520 Dram Type= 6, Freq= 0, CH_0, rank 1
6285 19:22:53.321543 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6286 19:22:53.322204 ==
6287 19:22:53.322675
6288 19:22:53.323035
6289 19:22:53.324571 TX Vref Scan disable
6290 19:22:53.325036 == TX Byte 0 ==
6291 19:22:53.330807 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6292 19:22:53.334226 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6293 19:22:53.334699 == TX Byte 1 ==
6294 19:22:53.341342 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6295 19:22:53.344215 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6296 19:22:53.344684
6297 19:22:53.345054 [DATLAT]
6298 19:22:53.347474 Freq=400, CH0 RK1
6299 19:22:53.347936
6300 19:22:53.348307 DATLAT Default: 0xd
6301 19:22:53.350949 0, 0xFFFF, sum = 0
6302 19:22:53.351423 1, 0xFFFF, sum = 0
6303 19:22:53.354113 2, 0xFFFF, sum = 0
6304 19:22:53.354584 3, 0xFFFF, sum = 0
6305 19:22:53.357564 4, 0xFFFF, sum = 0
6306 19:22:53.358059 5, 0xFFFF, sum = 0
6307 19:22:53.360920 6, 0xFFFF, sum = 0
6308 19:22:53.361348 7, 0xFFFF, sum = 0
6309 19:22:53.363955 8, 0xFFFF, sum = 0
6310 19:22:53.367306 9, 0xFFFF, sum = 0
6311 19:22:53.367611 10, 0xFFFF, sum = 0
6312 19:22:53.370447 11, 0xFFFF, sum = 0
6313 19:22:53.370750 12, 0x0, sum = 1
6314 19:22:53.374376 13, 0x0, sum = 2
6315 19:22:53.374694 14, 0x0, sum = 3
6316 19:22:53.374901 15, 0x0, sum = 4
6317 19:22:53.376912 best_step = 13
6318 19:22:53.377096
6319 19:22:53.377240 ==
6320 19:22:53.380088 Dram Type= 6, Freq= 0, CH_0, rank 1
6321 19:22:53.383422 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6322 19:22:53.383609 ==
6323 19:22:53.387282 RX Vref Scan: 0
6324 19:22:53.387801
6325 19:22:53.390529 RX Vref 0 -> 0, step: 1
6326 19:22:53.391008
6327 19:22:53.391408 RX Delay -359 -> 252, step: 8
6328 19:22:53.399157 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6329 19:22:53.402192 iDelay=217, Bit 1, Center -40 (-295 ~ 216) 512
6330 19:22:53.406076 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6331 19:22:53.412024 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6332 19:22:53.415210 iDelay=217, Bit 4, Center -36 (-287 ~ 216) 504
6333 19:22:53.418882 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6334 19:22:53.422004 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6335 19:22:53.428927 iDelay=217, Bit 7, Center -32 (-279 ~ 216) 496
6336 19:22:53.432697 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6337 19:22:53.435261 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6338 19:22:53.438340 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6339 19:22:53.445203 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6340 19:22:53.448525 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6341 19:22:53.451942 iDelay=217, Bit 13, Center -44 (-287 ~ 200) 488
6342 19:22:53.455528 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6343 19:22:53.461950 iDelay=217, Bit 15, Center -44 (-287 ~ 200) 488
6344 19:22:53.462492 ==
6345 19:22:53.465143 Dram Type= 6, Freq= 0, CH_0, rank 1
6346 19:22:53.468761 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6347 19:22:53.469252 ==
6348 19:22:53.469586 DQS Delay:
6349 19:22:53.471734 DQS0 = 52, DQS1 = 60
6350 19:22:53.472243 DQM Delay:
6351 19:22:53.475067 DQM0 = 10, DQM1 = 10
6352 19:22:53.475486 DQ Delay:
6353 19:22:53.478191 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =4
6354 19:22:53.482085 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =20
6355 19:22:53.485196 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6356 19:22:53.488504 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =16
6357 19:22:53.489004
6358 19:22:53.489343
6359 19:22:53.495089 [DQSOSCAuto] RK1, (LSB)MR18= 0xc1c1, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 385 ps
6360 19:22:53.498171 CH0 RK1: MR19=C0C, MR18=C1C1
6361 19:22:53.504725 CH0_RK1: MR19=0xC0C, MR18=0xC1C1, DQSOSC=385, MR23=63, INC=398, DEC=265
6362 19:22:53.508583 [RxdqsGatingPostProcess] freq 400
6363 19:22:53.514414 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6364 19:22:53.518257 Pre-setting of DQS Precalculation
6365 19:22:53.521570 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6366 19:22:53.522073 ==
6367 19:22:53.524656 Dram Type= 6, Freq= 0, CH_1, rank 0
6368 19:22:53.528055 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6369 19:22:53.528508 ==
6370 19:22:53.534593 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6371 19:22:53.541271 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6372 19:22:53.544532 [CA 0] Center 36 (8~64) winsize 57
6373 19:22:53.548026 [CA 1] Center 36 (8~64) winsize 57
6374 19:22:53.551255 [CA 2] Center 36 (8~64) winsize 57
6375 19:22:53.554652 [CA 3] Center 36 (8~64) winsize 57
6376 19:22:53.557663 [CA 4] Center 36 (8~64) winsize 57
6377 19:22:53.560921 [CA 5] Center 36 (8~64) winsize 57
6378 19:22:53.561473
6379 19:22:53.564028 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6380 19:22:53.564391
6381 19:22:53.568128 [CATrainingPosCal] consider 1 rank data
6382 19:22:53.571130 u2DelayCellTimex100 = 270/100 ps
6383 19:22:53.574363 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6384 19:22:53.577647 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6385 19:22:53.581124 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6386 19:22:53.584420 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6387 19:22:53.588023 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6388 19:22:53.590714 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6389 19:22:53.591145
6390 19:22:53.594368 CA PerBit enable=1, Macro0, CA PI delay=36
6391 19:22:53.597531
6392 19:22:53.598140 [CBTSetCACLKResult] CA Dly = 36
6393 19:22:53.601028 CS Dly: 1 (0~32)
6394 19:22:53.601486 ==
6395 19:22:53.603959 Dram Type= 6, Freq= 0, CH_1, rank 1
6396 19:22:53.607863 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6397 19:22:53.608290 ==
6398 19:22:53.613956 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6399 19:22:53.620798 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6400 19:22:53.624649 [CA 0] Center 36 (8~64) winsize 57
6401 19:22:53.627217 [CA 1] Center 36 (8~64) winsize 57
6402 19:22:53.630511 [CA 2] Center 36 (8~64) winsize 57
6403 19:22:53.630934 [CA 3] Center 36 (8~64) winsize 57
6404 19:22:53.633850 [CA 4] Center 36 (8~64) winsize 57
6405 19:22:53.637426 [CA 5] Center 36 (8~64) winsize 57
6406 19:22:53.637853
6407 19:22:53.640893 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6408 19:22:53.643909
6409 19:22:53.647045 [CATrainingPosCal] consider 2 rank data
6410 19:22:53.647613 u2DelayCellTimex100 = 270/100 ps
6411 19:22:53.654410 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6412 19:22:53.657598 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6413 19:22:53.660562 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6414 19:22:53.664276 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6415 19:22:53.667135 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6416 19:22:53.670588 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6417 19:22:53.671012
6418 19:22:53.673914 CA PerBit enable=1, Macro0, CA PI delay=36
6419 19:22:53.674384
6420 19:22:53.677289 [CBTSetCACLKResult] CA Dly = 36
6421 19:22:53.680513 CS Dly: 1 (0~32)
6422 19:22:53.681036
6423 19:22:53.683374 ----->DramcWriteLeveling(PI) begin...
6424 19:22:53.683804 ==
6425 19:22:53.687021 Dram Type= 6, Freq= 0, CH_1, rank 0
6426 19:22:53.690146 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6427 19:22:53.690589 ==
6428 19:22:53.694014 Write leveling (Byte 0): 32 => 0
6429 19:22:53.697030 Write leveling (Byte 1): 32 => 0
6430 19:22:53.700505 DramcWriteLeveling(PI) end<-----
6431 19:22:53.701024
6432 19:22:53.701363 ==
6433 19:22:53.703759 Dram Type= 6, Freq= 0, CH_1, rank 0
6434 19:22:53.707163 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6435 19:22:53.707595 ==
6436 19:22:53.710696 [Gating] SW mode calibration
6437 19:22:53.716851 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6438 19:22:53.723359 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6439 19:22:53.726430 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6440 19:22:53.729780 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6441 19:22:53.736573 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6442 19:22:53.739903 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6443 19:22:53.743217 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6444 19:22:53.749663 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6445 19:22:53.753167 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6446 19:22:53.756404 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6447 19:22:53.763116 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6448 19:22:53.763544 Total UI for P1: 0, mck2ui 16
6449 19:22:53.769320 best dqsien dly found for B0: ( 0, 10, 16)
6450 19:22:53.769748 Total UI for P1: 0, mck2ui 16
6451 19:22:53.776422 best dqsien dly found for B1: ( 0, 10, 16)
6452 19:22:53.779369 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6453 19:22:53.782815 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6454 19:22:53.783245
6455 19:22:53.786355 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6456 19:22:53.789514 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6457 19:22:53.793034 [Gating] SW calibration Done
6458 19:22:53.793547 ==
6459 19:22:53.795961 Dram Type= 6, Freq= 0, CH_1, rank 0
6460 19:22:53.799491 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6461 19:22:53.800027 ==
6462 19:22:53.802937 RX Vref Scan: 0
6463 19:22:53.803431
6464 19:22:53.806353 RX Vref 0 -> 0, step: 1
6465 19:22:53.806876
6466 19:22:53.807214 RX Delay -410 -> 252, step: 16
6467 19:22:53.812943 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6468 19:22:53.816027 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6469 19:22:53.819648 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6470 19:22:53.822836 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6471 19:22:53.829515 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6472 19:22:53.832677 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6473 19:22:53.836114 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6474 19:22:53.839480 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6475 19:22:53.846084 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6476 19:22:53.849165 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6477 19:22:53.852901 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6478 19:22:53.855783 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6479 19:22:53.862599 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6480 19:22:53.865752 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6481 19:22:53.869343 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6482 19:22:53.875367 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6483 19:22:53.875834 ==
6484 19:22:53.878619 Dram Type= 6, Freq= 0, CH_1, rank 0
6485 19:22:53.882268 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6486 19:22:53.882737 ==
6487 19:22:53.883107 DQS Delay:
6488 19:22:53.885431 DQS0 = 43, DQS1 = 59
6489 19:22:53.885897 DQM Delay:
6490 19:22:53.889239 DQM0 = 6, DQM1 = 15
6491 19:22:53.889801 DQ Delay:
6492 19:22:53.891843 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6493 19:22:53.895253 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6494 19:22:53.898739 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6495 19:22:53.901969 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =32
6496 19:22:53.902468
6497 19:22:53.902840
6498 19:22:53.903181 ==
6499 19:22:53.905498 Dram Type= 6, Freq= 0, CH_1, rank 0
6500 19:22:53.908854 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6501 19:22:53.909279 ==
6502 19:22:53.909617
6503 19:22:53.909929
6504 19:22:53.911945 TX Vref Scan disable
6505 19:22:53.915504 == TX Byte 0 ==
6506 19:22:53.918526 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6507 19:22:53.922007 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6508 19:22:53.925502 == TX Byte 1 ==
6509 19:22:53.928750 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6510 19:22:53.931947 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6511 19:22:53.932468 ==
6512 19:22:53.934908 Dram Type= 6, Freq= 0, CH_1, rank 0
6513 19:22:53.938820 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6514 19:22:53.942512 ==
6515 19:22:53.943031
6516 19:22:53.943446
6517 19:22:53.943767 TX Vref Scan disable
6518 19:22:53.945115 == TX Byte 0 ==
6519 19:22:53.948927 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6520 19:22:53.952216 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6521 19:22:53.955340 == TX Byte 1 ==
6522 19:22:53.958194 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6523 19:22:53.961853 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6524 19:22:53.962442
6525 19:22:53.965373 [DATLAT]
6526 19:22:53.965893 Freq=400, CH1 RK0
6527 19:22:53.966372
6528 19:22:53.968012 DATLAT Default: 0xf
6529 19:22:53.968452 0, 0xFFFF, sum = 0
6530 19:22:53.971715 1, 0xFFFF, sum = 0
6531 19:22:53.972146 2, 0xFFFF, sum = 0
6532 19:22:53.974847 3, 0xFFFF, sum = 0
6533 19:22:53.975276 4, 0xFFFF, sum = 0
6534 19:22:53.977964 5, 0xFFFF, sum = 0
6535 19:22:53.978431 6, 0xFFFF, sum = 0
6536 19:22:53.981272 7, 0xFFFF, sum = 0
6537 19:22:53.981700 8, 0xFFFF, sum = 0
6538 19:22:53.984989 9, 0xFFFF, sum = 0
6539 19:22:53.985412 10, 0xFFFF, sum = 0
6540 19:22:53.987983 11, 0xFFFF, sum = 0
6541 19:22:53.988411 12, 0x0, sum = 1
6542 19:22:53.991373 13, 0x0, sum = 2
6543 19:22:53.991802 14, 0x0, sum = 3
6544 19:22:53.994903 15, 0x0, sum = 4
6545 19:22:53.995485 best_step = 13
6546 19:22:53.995844
6547 19:22:53.996159 ==
6548 19:22:53.998134 Dram Type= 6, Freq= 0, CH_1, rank 0
6549 19:22:54.004807 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6550 19:22:54.005333 ==
6551 19:22:54.005676 RX Vref Scan: 1
6552 19:22:54.005992
6553 19:22:54.008085 RX Vref 0 -> 0, step: 1
6554 19:22:54.008507
6555 19:22:54.011095 RX Delay -359 -> 252, step: 8
6556 19:22:54.011520
6557 19:22:54.014390 Set Vref, RX VrefLevel [Byte0]: 56
6558 19:22:54.017816 [Byte1]: 49
6559 19:22:54.021178
6560 19:22:54.021615 Final RX Vref Byte 0 = 56 to rank0
6561 19:22:54.024889 Final RX Vref Byte 1 = 49 to rank0
6562 19:22:54.028151 Final RX Vref Byte 0 = 56 to rank1
6563 19:22:54.031320 Final RX Vref Byte 1 = 49 to rank1==
6564 19:22:54.034491 Dram Type= 6, Freq= 0, CH_1, rank 0
6565 19:22:54.041151 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6566 19:22:54.041865 ==
6567 19:22:54.042322 DQS Delay:
6568 19:22:54.044296 DQS0 = 52, DQS1 = 64
6569 19:22:54.044813 DQM Delay:
6570 19:22:54.045155 DQM0 = 10, DQM1 = 16
6571 19:22:54.047632 DQ Delay:
6572 19:22:54.051097 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6573 19:22:54.051538 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
6574 19:22:54.054366 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6575 19:22:54.058244 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6576 19:22:54.058768
6577 19:22:54.060892
6578 19:22:54.067308 [DQSOSCAuto] RK0, (LSB)MR18= 0xdada, (MSB)MR19= 0xc0c, tDQSOscB0 = 382 ps tDQSOscB1 = 382 ps
6579 19:22:54.070629 CH1 RK0: MR19=C0C, MR18=DADA
6580 19:22:54.077053 CH1_RK0: MR19=0xC0C, MR18=0xDADA, DQSOSC=382, MR23=63, INC=404, DEC=269
6581 19:22:54.077521 ==
6582 19:22:54.081264 Dram Type= 6, Freq= 0, CH_1, rank 1
6583 19:22:54.083848 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6584 19:22:54.084318 ==
6585 19:22:54.087650 [Gating] SW mode calibration
6586 19:22:54.094244 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6587 19:22:54.100774 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6588 19:22:54.104111 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6589 19:22:54.107220 0 7 16 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
6590 19:22:54.113786 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6591 19:22:54.117536 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
6592 19:22:54.120437 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6593 19:22:54.123961 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6594 19:22:54.130732 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6595 19:22:54.133680 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
6596 19:22:54.137275 Total UI for P1: 0, mck2ui 16
6597 19:22:54.140112 best dqsien dly found for B0: ( 0, 10, 8)
6598 19:22:54.143726 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6599 19:22:54.146678 Total UI for P1: 0, mck2ui 16
6600 19:22:54.150333 best dqsien dly found for B1: ( 0, 10, 16)
6601 19:22:54.153535 best DQS0 dly(MCK, UI, PI) = (0, 10, 8)
6602 19:22:54.160190 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6603 19:22:54.160657
6604 19:22:54.163576 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 8)
6605 19:22:54.167136 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6606 19:22:54.170339 [Gating] SW calibration Done
6607 19:22:54.170902 ==
6608 19:22:54.173585 Dram Type= 6, Freq= 0, CH_1, rank 1
6609 19:22:54.177174 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6610 19:22:54.177644 ==
6611 19:22:54.180119 RX Vref Scan: 0
6612 19:22:54.180576
6613 19:22:54.180941 RX Vref 0 -> 0, step: 1
6614 19:22:54.181285
6615 19:22:54.183454 RX Delay -410 -> 252, step: 16
6616 19:22:54.186933 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6617 19:22:54.193669 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6618 19:22:54.196797 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6619 19:22:54.199920 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6620 19:22:54.203754 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6621 19:22:54.209623 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6622 19:22:54.212980 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6623 19:22:54.216488 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6624 19:22:54.219745 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6625 19:22:54.226323 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6626 19:22:54.229837 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6627 19:22:54.233285 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6628 19:22:54.239942 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6629 19:22:54.242988 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6630 19:22:54.246791 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6631 19:22:54.249753 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6632 19:22:54.250374 ==
6633 19:22:54.252854 Dram Type= 6, Freq= 0, CH_1, rank 1
6634 19:22:54.259567 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6635 19:22:54.260121 ==
6636 19:22:54.260491 DQS Delay:
6637 19:22:54.262811 DQS0 = 43, DQS1 = 59
6638 19:22:54.263273 DQM Delay:
6639 19:22:54.266399 DQM0 = 9, DQM1 = 17
6640 19:22:54.266959 DQ Delay:
6641 19:22:54.269595 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6642 19:22:54.273267 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6643 19:22:54.273830 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6644 19:22:54.279486 DQ12 =32, DQ13 =32, DQ14 =24, DQ15 =24
6645 19:22:54.280089
6646 19:22:54.280477
6647 19:22:54.280823 ==
6648 19:22:54.282606 Dram Type= 6, Freq= 0, CH_1, rank 1
6649 19:22:54.285669 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6650 19:22:54.286272 ==
6651 19:22:54.286653
6652 19:22:54.286999
6653 19:22:54.289268 TX Vref Scan disable
6654 19:22:54.289731 == TX Byte 0 ==
6655 19:22:54.292879 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6656 19:22:54.299443 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6657 19:22:54.300003 == TX Byte 1 ==
6658 19:22:54.302602 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6659 19:22:54.308859 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6660 19:22:54.309361 ==
6661 19:22:54.312760 Dram Type= 6, Freq= 0, CH_1, rank 1
6662 19:22:54.315573 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6663 19:22:54.316257 ==
6664 19:22:54.316664
6665 19:22:54.317301
6666 19:22:54.318795 TX Vref Scan disable
6667 19:22:54.319337 == TX Byte 0 ==
6668 19:22:54.325496 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6669 19:22:54.329307 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6670 19:22:54.329871 == TX Byte 1 ==
6671 19:22:54.335400 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6672 19:22:54.339268 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6673 19:22:54.339846
6674 19:22:54.340215 [DATLAT]
6675 19:22:54.342181 Freq=400, CH1 RK1
6676 19:22:54.342740
6677 19:22:54.343109 DATLAT Default: 0xd
6678 19:22:54.345576 0, 0xFFFF, sum = 0
6679 19:22:54.346179 1, 0xFFFF, sum = 0
6680 19:22:54.348793 2, 0xFFFF, sum = 0
6681 19:22:54.349360 3, 0xFFFF, sum = 0
6682 19:22:54.351786 4, 0xFFFF, sum = 0
6683 19:22:54.352256 5, 0xFFFF, sum = 0
6684 19:22:54.355369 6, 0xFFFF, sum = 0
6685 19:22:54.355839 7, 0xFFFF, sum = 0
6686 19:22:54.358592 8, 0xFFFF, sum = 0
6687 19:22:54.359122 9, 0xFFFF, sum = 0
6688 19:22:54.361724 10, 0xFFFF, sum = 0
6689 19:22:54.362213 11, 0xFFFF, sum = 0
6690 19:22:54.365645 12, 0x0, sum = 1
6691 19:22:54.366260 13, 0x0, sum = 2
6692 19:22:54.368586 14, 0x0, sum = 3
6693 19:22:54.369174 15, 0x0, sum = 4
6694 19:22:54.371860 best_step = 13
6695 19:22:54.372322
6696 19:22:54.372691 ==
6697 19:22:54.375003 Dram Type= 6, Freq= 0, CH_1, rank 1
6698 19:22:54.378383 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6699 19:22:54.378948 ==
6700 19:22:54.381796 RX Vref Scan: 0
6701 19:22:54.382406
6702 19:22:54.382777 RX Vref 0 -> 0, step: 1
6703 19:22:54.383120
6704 19:22:54.384916 RX Delay -359 -> 252, step: 8
6705 19:22:54.393655 iDelay=225, Bit 0, Center -36 (-279 ~ 208) 488
6706 19:22:54.396441 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
6707 19:22:54.400578 iDelay=225, Bit 2, Center -48 (-295 ~ 200) 496
6708 19:22:54.406716 iDelay=225, Bit 3, Center -44 (-287 ~ 200) 488
6709 19:22:54.410278 iDelay=225, Bit 4, Center -40 (-287 ~ 208) 496
6710 19:22:54.413050 iDelay=225, Bit 5, Center -24 (-271 ~ 224) 496
6711 19:22:54.416402 iDelay=225, Bit 6, Center -32 (-279 ~ 216) 496
6712 19:22:54.422990 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
6713 19:22:54.426371 iDelay=225, Bit 8, Center -64 (-311 ~ 184) 496
6714 19:22:54.429897 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
6715 19:22:54.433325 iDelay=225, Bit 10, Center -48 (-295 ~ 200) 496
6716 19:22:54.439258 iDelay=225, Bit 11, Center -56 (-303 ~ 192) 496
6717 19:22:54.442980 iDelay=225, Bit 12, Center -40 (-287 ~ 208) 496
6718 19:22:54.445850 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
6719 19:22:54.449138 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
6720 19:22:54.455959 iDelay=225, Bit 15, Center -44 (-287 ~ 200) 488
6721 19:22:54.456420 ==
6722 19:22:54.459123 Dram Type= 6, Freq= 0, CH_1, rank 1
6723 19:22:54.462572 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6724 19:22:54.463035 ==
6725 19:22:54.463400 DQS Delay:
6726 19:22:54.465871 DQS0 = 48, DQS1 = 64
6727 19:22:54.466362 DQM Delay:
6728 19:22:54.469514 DQM0 = 9, DQM1 = 15
6729 19:22:54.470129 DQ Delay:
6730 19:22:54.472307 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6731 19:22:54.475796 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6732 19:22:54.479017 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6733 19:22:54.482557 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =20
6734 19:22:54.483021
6735 19:22:54.483388
6736 19:22:54.489447 [DQSOSCAuto] RK1, (LSB)MR18= 0xb5b5, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
6737 19:22:54.492262 CH1 RK1: MR19=C0C, MR18=B5B5
6738 19:22:54.499017 CH1_RK1: MR19=0xC0C, MR18=0xB5B5, DQSOSC=387, MR23=63, INC=394, DEC=262
6739 19:22:54.502258 [RxdqsGatingPostProcess] freq 400
6740 19:22:54.508591 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6741 19:22:54.511867 Pre-setting of DQS Precalculation
6742 19:22:54.515314 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6743 19:22:54.521872 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6744 19:22:54.529213 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6745 19:22:54.529786
6746 19:22:54.532258
6747 19:22:54.532813 [Calibration Summary] 800 Mbps
6748 19:22:54.535326 CH 0, Rank 0
6749 19:22:54.535789 SW Impedance : PASS
6750 19:22:54.538629 DUTY Scan : NO K
6751 19:22:54.542241 ZQ Calibration : PASS
6752 19:22:54.542796 Jitter Meter : NO K
6753 19:22:54.545118 CBT Training : PASS
6754 19:22:54.548562 Write leveling : PASS
6755 19:22:54.549155 RX DQS gating : PASS
6756 19:22:54.551715 RX DQ/DQS(RDDQC) : PASS
6757 19:22:54.555076 TX DQ/DQS : PASS
6758 19:22:54.555549 RX DATLAT : PASS
6759 19:22:54.558443 RX DQ/DQS(Engine): PASS
6760 19:22:54.561543 TX OE : NO K
6761 19:22:54.562008 All Pass.
6762 19:22:54.562460
6763 19:22:54.563031 CH 0, Rank 1
6764 19:22:54.564822 SW Impedance : PASS
6765 19:22:54.568205 DUTY Scan : NO K
6766 19:22:54.568675 ZQ Calibration : PASS
6767 19:22:54.571372 Jitter Meter : NO K
6768 19:22:54.574905 CBT Training : PASS
6769 19:22:54.575383 Write leveling : NO K
6770 19:22:54.578406 RX DQS gating : PASS
6771 19:22:54.578927 RX DQ/DQS(RDDQC) : PASS
6772 19:22:54.581360 TX DQ/DQS : PASS
6773 19:22:54.584708 RX DATLAT : PASS
6774 19:22:54.585336 RX DQ/DQS(Engine): PASS
6775 19:22:54.587858 TX OE : NO K
6776 19:22:54.588383 All Pass.
6777 19:22:54.588758
6778 19:22:54.591378 CH 1, Rank 0
6779 19:22:54.591792 SW Impedance : PASS
6780 19:22:54.594519 DUTY Scan : NO K
6781 19:22:54.597758 ZQ Calibration : PASS
6782 19:22:54.598195 Jitter Meter : NO K
6783 19:22:54.601256 CBT Training : PASS
6784 19:22:54.604729 Write leveling : PASS
6785 19:22:54.605153 RX DQS gating : PASS
6786 19:22:54.607953 RX DQ/DQS(RDDQC) : PASS
6787 19:22:54.611087 TX DQ/DQS : PASS
6788 19:22:54.611556 RX DATLAT : PASS
6789 19:22:54.614675 RX DQ/DQS(Engine): PASS
6790 19:22:54.617660 TX OE : NO K
6791 19:22:54.618127 All Pass.
6792 19:22:54.618467
6793 19:22:54.618776 CH 1, Rank 1
6794 19:22:54.621413 SW Impedance : PASS
6795 19:22:54.624591 DUTY Scan : NO K
6796 19:22:54.625109 ZQ Calibration : PASS
6797 19:22:54.627689 Jitter Meter : NO K
6798 19:22:54.631558 CBT Training : PASS
6799 19:22:54.632113 Write leveling : NO K
6800 19:22:54.634332 RX DQS gating : PASS
6801 19:22:54.638109 RX DQ/DQS(RDDQC) : PASS
6802 19:22:54.638722 TX DQ/DQS : PASS
6803 19:22:54.641172 RX DATLAT : PASS
6804 19:22:54.644445 RX DQ/DQS(Engine): PASS
6805 19:22:54.645357 TX OE : NO K
6806 19:22:54.646002 All Pass.
6807 19:22:54.647514
6808 19:22:54.648211 DramC Write-DBI off
6809 19:22:54.650660 PER_BANK_REFRESH: Hybrid Mode
6810 19:22:54.651357 TX_TRACKING: ON
6811 19:22:54.660699 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6812 19:22:54.664227 [FAST_K] Save calibration result to emmc
6813 19:22:54.667667 dramc_set_vcore_voltage set vcore to 725000
6814 19:22:54.670598 Read voltage for 1600, 0
6815 19:22:54.671069 Vio18 = 0
6816 19:22:54.673812 Vcore = 725000
6817 19:22:54.674383 Vdram = 0
6818 19:22:54.674759 Vddq = 0
6819 19:22:54.675098 Vmddr = 0
6820 19:22:54.680473 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6821 19:22:54.687243 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6822 19:22:54.687732 MEM_TYPE=3, freq_sel=13
6823 19:22:54.690374 sv_algorithm_assistance_LP4_3733
6824 19:22:54.693789 ============ PULL DRAM RESETB DOWN ============
6825 19:22:54.700541 ========== PULL DRAM RESETB DOWN end =========
6826 19:22:54.703754 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6827 19:22:54.707377 ===================================
6828 19:22:54.710425 LPDDR4 DRAM CONFIGURATION
6829 19:22:54.714215 ===================================
6830 19:22:54.714630 EX_ROW_EN[0] = 0x0
6831 19:22:54.716766 EX_ROW_EN[1] = 0x0
6832 19:22:54.720021 LP4Y_EN = 0x0
6833 19:22:54.720432 WORK_FSP = 0x1
6834 19:22:54.723511 WL = 0x5
6835 19:22:54.723930 RL = 0x5
6836 19:22:54.727087 BL = 0x2
6837 19:22:54.727511 RPST = 0x0
6838 19:22:54.730499 RD_PRE = 0x0
6839 19:22:54.730922 WR_PRE = 0x1
6840 19:22:54.733332 WR_PST = 0x1
6841 19:22:54.733755 DBI_WR = 0x0
6842 19:22:54.737248 DBI_RD = 0x0
6843 19:22:54.737767 OTF = 0x1
6844 19:22:54.739967 ===================================
6845 19:22:54.743593 ===================================
6846 19:22:54.747009 ANA top config
6847 19:22:54.749925 ===================================
6848 19:22:54.750398 DLL_ASYNC_EN = 0
6849 19:22:54.753295 ALL_SLAVE_EN = 0
6850 19:22:54.756838 NEW_RANK_MODE = 1
6851 19:22:54.759932 DLL_IDLE_MODE = 1
6852 19:22:54.763190 LP45_APHY_COMB_EN = 1
6853 19:22:54.763864 TX_ODT_DIS = 0
6854 19:22:54.766395 NEW_8X_MODE = 1
6855 19:22:54.769747 ===================================
6856 19:22:54.773161 ===================================
6857 19:22:54.776488 data_rate = 3200
6858 19:22:54.779654 CKR = 1
6859 19:22:54.783219 DQ_P2S_RATIO = 8
6860 19:22:54.786243 ===================================
6861 19:22:54.789690 CA_P2S_RATIO = 8
6862 19:22:54.790403 DQ_CA_OPEN = 0
6863 19:22:54.792832 DQ_SEMI_OPEN = 0
6864 19:22:54.796398 CA_SEMI_OPEN = 0
6865 19:22:54.799484 CA_FULL_RATE = 0
6866 19:22:54.802968 DQ_CKDIV4_EN = 0
6867 19:22:54.805971 CA_CKDIV4_EN = 0
6868 19:22:54.806590 CA_PREDIV_EN = 0
6869 19:22:54.809338 PH8_DLY = 12
6870 19:22:54.812953 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6871 19:22:54.816247 DQ_AAMCK_DIV = 4
6872 19:22:54.819411 CA_AAMCK_DIV = 4
6873 19:22:54.822998 CA_ADMCK_DIV = 4
6874 19:22:54.823592 DQ_TRACK_CA_EN = 0
6875 19:22:54.825912 CA_PICK = 1600
6876 19:22:54.829637 CA_MCKIO = 1600
6877 19:22:54.832724 MCKIO_SEMI = 0
6878 19:22:54.836381 PLL_FREQ = 3068
6879 19:22:54.839475 DQ_UI_PI_RATIO = 32
6880 19:22:54.842660 CA_UI_PI_RATIO = 0
6881 19:22:54.845595 ===================================
6882 19:22:54.849239 ===================================
6883 19:22:54.849757 memory_type:LPDDR4
6884 19:22:54.852543 GP_NUM : 10
6885 19:22:54.856055 SRAM_EN : 1
6886 19:22:54.856538 MD32_EN : 0
6887 19:22:54.859422 ===================================
6888 19:22:54.862310 [ANA_INIT] >>>>>>>>>>>>>>
6889 19:22:54.865637 <<<<<< [CONFIGURE PHASE]: ANA_TX
6890 19:22:54.869172 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6891 19:22:54.872150 ===================================
6892 19:22:54.875588 data_rate = 3200,PCW = 0X7600
6893 19:22:54.879072 ===================================
6894 19:22:54.882102 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6895 19:22:54.885313 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6896 19:22:54.892134 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6897 19:22:54.895409 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6898 19:22:54.898706 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6899 19:22:54.905843 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6900 19:22:54.906458 [ANA_INIT] flow start
6901 19:22:54.908593 [ANA_INIT] PLL >>>>>>>>
6902 19:22:54.909085 [ANA_INIT] PLL <<<<<<<<
6903 19:22:54.912298 [ANA_INIT] MIDPI >>>>>>>>
6904 19:22:54.915265 [ANA_INIT] MIDPI <<<<<<<<
6905 19:22:54.918326 [ANA_INIT] DLL >>>>>>>>
6906 19:22:54.918775 [ANA_INIT] DLL <<<<<<<<
6907 19:22:54.921765 [ANA_INIT] flow end
6908 19:22:54.925108 ============ LP4 DIFF to SE enter ============
6909 19:22:54.928714 ============ LP4 DIFF to SE exit ============
6910 19:22:54.932278 [ANA_INIT] <<<<<<<<<<<<<
6911 19:22:54.934915 [Flow] Enable top DCM control >>>>>
6912 19:22:54.938420 [Flow] Enable top DCM control <<<<<
6913 19:22:54.941965 Enable DLL master slave shuffle
6914 19:22:54.948399 ==============================================================
6915 19:22:54.948965 Gating Mode config
6916 19:22:54.955241 ==============================================================
6917 19:22:54.955800 Config description:
6918 19:22:54.965019 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6919 19:22:54.971734 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6920 19:22:54.978678 SELPH_MODE 0: By rank 1: By Phase
6921 19:22:54.981296 ==============================================================
6922 19:22:54.984651 GAT_TRACK_EN = 1
6923 19:22:54.988755 RX_GATING_MODE = 2
6924 19:22:54.991898 RX_GATING_TRACK_MODE = 2
6925 19:22:54.995268 SELPH_MODE = 1
6926 19:22:54.998156 PICG_EARLY_EN = 1
6927 19:22:55.001709 VALID_LAT_VALUE = 1
6928 19:22:55.008515 ==============================================================
6929 19:22:55.011030 Enter into Gating configuration >>>>
6930 19:22:55.014364 Exit from Gating configuration <<<<
6931 19:22:55.018182 Enter into DVFS_PRE_config >>>>>
6932 19:22:55.027649 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6933 19:22:55.030936 Exit from DVFS_PRE_config <<<<<
6934 19:22:55.034234 Enter into PICG configuration >>>>
6935 19:22:55.037576 Exit from PICG configuration <<<<
6936 19:22:55.040876 [RX_INPUT] configuration >>>>>
6937 19:22:55.041347 [RX_INPUT] configuration <<<<<
6938 19:22:55.047893 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6939 19:22:55.054289 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6940 19:22:55.057645 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6941 19:22:55.064449 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6942 19:22:55.070872 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6943 19:22:55.077377 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6944 19:22:55.080835 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6945 19:22:55.083873 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6946 19:22:55.090761 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6947 19:22:55.093900 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6948 19:22:55.097704 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6949 19:22:55.103742 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6950 19:22:55.107667 ===================================
6951 19:22:55.108235 LPDDR4 DRAM CONFIGURATION
6952 19:22:55.110901 ===================================
6953 19:22:55.113637 EX_ROW_EN[0] = 0x0
6954 19:22:55.114146 EX_ROW_EN[1] = 0x0
6955 19:22:55.116928 LP4Y_EN = 0x0
6956 19:22:55.120387 WORK_FSP = 0x1
6957 19:22:55.120858 WL = 0x5
6958 19:22:55.123821 RL = 0x5
6959 19:22:55.124287 BL = 0x2
6960 19:22:55.127099 RPST = 0x0
6961 19:22:55.127572 RD_PRE = 0x0
6962 19:22:55.130521 WR_PRE = 0x1
6963 19:22:55.130986 WR_PST = 0x1
6964 19:22:55.133509 DBI_WR = 0x0
6965 19:22:55.133977 DBI_RD = 0x0
6966 19:22:55.137130 OTF = 0x1
6967 19:22:55.139918 ===================================
6968 19:22:55.143722 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6969 19:22:55.146943 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6970 19:22:55.153214 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6971 19:22:55.156907 ===================================
6972 19:22:55.157493 LPDDR4 DRAM CONFIGURATION
6973 19:22:55.160119 ===================================
6974 19:22:55.163191 EX_ROW_EN[0] = 0x10
6975 19:22:55.163754 EX_ROW_EN[1] = 0x0
6976 19:22:55.166365 LP4Y_EN = 0x0
6977 19:22:55.169741 WORK_FSP = 0x1
6978 19:22:55.170340 WL = 0x5
6979 19:22:55.173207 RL = 0x5
6980 19:22:55.173671 BL = 0x2
6981 19:22:55.176527 RPST = 0x0
6982 19:22:55.177004 RD_PRE = 0x0
6983 19:22:55.179837 WR_PRE = 0x1
6984 19:22:55.180303 WR_PST = 0x1
6985 19:22:55.182965 DBI_WR = 0x0
6986 19:22:55.183432 DBI_RD = 0x0
6987 19:22:55.186358 OTF = 0x1
6988 19:22:55.189694 ===================================
6989 19:22:55.196484 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6990 19:22:55.197050 ==
6991 19:22:55.199694 Dram Type= 6, Freq= 0, CH_0, rank 0
6992 19:22:55.203060 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
6993 19:22:55.203531 ==
6994 19:22:55.206585 [Duty_Offset_Calibration]
6995 19:22:55.207132 B0:0 B1:2 CA:1
6996 19:22:55.207509
6997 19:22:55.209780 [DutyScan_Calibration_Flow] k_type=0
6998 19:22:55.220008
6999 19:22:55.220481 ==CLK 0==
7000 19:22:55.223057 Final CLK duty delay cell = 0
7001 19:22:55.227165 [0] MAX Duty = 5156%(X100), DQS PI = 22
7002 19:22:55.230321 [0] MIN Duty = 4938%(X100), DQS PI = 52
7003 19:22:55.233647 [0] AVG Duty = 5047%(X100)
7004 19:22:55.234194
7005 19:22:55.236756 CH0 CLK Duty spec in!! Max-Min= 218%
7006 19:22:55.239953 [DutyScan_Calibration_Flow] ====Done====
7007 19:22:55.240377
7008 19:22:55.243278 [DutyScan_Calibration_Flow] k_type=1
7009 19:22:55.259983
7010 19:22:55.260588 ==DQS 0 ==
7011 19:22:55.263162 Final DQS duty delay cell = 0
7012 19:22:55.266454 [0] MAX Duty = 5156%(X100), DQS PI = 34
7013 19:22:55.270246 [0] MIN Duty = 5031%(X100), DQS PI = 6
7014 19:22:55.273233 [0] AVG Duty = 5093%(X100)
7015 19:22:55.273657
7016 19:22:55.273993 ==DQS 1 ==
7017 19:22:55.276169 Final DQS duty delay cell = 0
7018 19:22:55.279707 [0] MAX Duty = 5031%(X100), DQS PI = 6
7019 19:22:55.282715 [0] MIN Duty = 4876%(X100), DQS PI = 18
7020 19:22:55.286407 [0] AVG Duty = 4953%(X100)
7021 19:22:55.286832
7022 19:22:55.289302 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7023 19:22:55.289729
7024 19:22:55.292684 CH0 DQS 1 Duty spec in!! Max-Min= 155%
7025 19:22:55.296581 [DutyScan_Calibration_Flow] ====Done====
7026 19:22:55.297106
7027 19:22:55.299543 [DutyScan_Calibration_Flow] k_type=3
7028 19:22:55.317239
7029 19:22:55.317779 ==DQM 0 ==
7030 19:22:55.320339 Final DQM duty delay cell = 0
7031 19:22:55.323272 [0] MAX Duty = 5187%(X100), DQS PI = 24
7032 19:22:55.327048 [0] MIN Duty = 4907%(X100), DQS PI = 42
7033 19:22:55.330287 [0] AVG Duty = 5047%(X100)
7034 19:22:55.330712
7035 19:22:55.331050 ==DQM 1 ==
7036 19:22:55.333373 Final DQM duty delay cell = 0
7037 19:22:55.336813 [0] MAX Duty = 5031%(X100), DQS PI = 50
7038 19:22:55.339852 [0] MIN Duty = 4782%(X100), DQS PI = 14
7039 19:22:55.343280 [0] AVG Duty = 4906%(X100)
7040 19:22:55.343705
7041 19:22:55.347271 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7042 19:22:55.347803
7043 19:22:55.349810 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7044 19:22:55.353442 [DutyScan_Calibration_Flow] ====Done====
7045 19:22:55.353965
7046 19:22:55.356466 [DutyScan_Calibration_Flow] k_type=2
7047 19:22:55.373126
7048 19:22:55.373627 ==DQ 0 ==
7049 19:22:55.376674 Final DQ duty delay cell = 0
7050 19:22:55.380033 [0] MAX Duty = 5218%(X100), DQS PI = 18
7051 19:22:55.383584 [0] MIN Duty = 4938%(X100), DQS PI = 56
7052 19:22:55.384008 [0] AVG Duty = 5078%(X100)
7053 19:22:55.386377
7054 19:22:55.386797 ==DQ 1 ==
7055 19:22:55.389908 Final DQ duty delay cell = -4
7056 19:22:55.393493 [-4] MAX Duty = 5062%(X100), DQS PI = 4
7057 19:22:55.396368 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7058 19:22:55.399945 [-4] AVG Duty = 4953%(X100)
7059 19:22:55.400369
7060 19:22:55.402875 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7061 19:22:55.403350
7062 19:22:55.406416 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7063 19:22:55.410015 [DutyScan_Calibration_Flow] ====Done====
7064 19:22:55.410491 ==
7065 19:22:55.413020 Dram Type= 6, Freq= 0, CH_1, rank 0
7066 19:22:55.416703 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7067 19:22:55.417156 ==
7068 19:22:55.419607 [Duty_Offset_Calibration]
7069 19:22:55.420041 B0:0 B1:4 CA:-5
7070 19:22:55.420489
7071 19:22:55.423005 [DutyScan_Calibration_Flow] k_type=0
7072 19:22:55.433711
7073 19:22:55.434244 ==CLK 0==
7074 19:22:55.437461 Final CLK duty delay cell = 0
7075 19:22:55.441043 [0] MAX Duty = 5156%(X100), DQS PI = 20
7076 19:22:55.444222 [0] MIN Duty = 4906%(X100), DQS PI = 50
7077 19:22:55.447155 [0] AVG Duty = 5031%(X100)
7078 19:22:55.447594
7079 19:22:55.450782 CH1 CLK Duty spec in!! Max-Min= 250%
7080 19:22:55.453618 [DutyScan_Calibration_Flow] ====Done====
7081 19:22:55.454069
7082 19:22:55.456828 [DutyScan_Calibration_Flow] k_type=1
7083 19:22:55.472702
7084 19:22:55.473240 ==DQS 0 ==
7085 19:22:55.476316 Final DQS duty delay cell = 0
7086 19:22:55.479703 [0] MAX Duty = 5187%(X100), DQS PI = 20
7087 19:22:55.482683 [0] MIN Duty = 4876%(X100), DQS PI = 42
7088 19:22:55.486021 [0] AVG Duty = 5031%(X100)
7089 19:22:55.486532
7090 19:22:55.486903 ==DQS 1 ==
7091 19:22:55.489861 Final DQS duty delay cell = -4
7092 19:22:55.492815 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7093 19:22:55.496378 [-4] MIN Duty = 4844%(X100), DQS PI = 56
7094 19:22:55.499377 [-4] AVG Duty = 4922%(X100)
7095 19:22:55.499845
7096 19:22:55.502708 CH1 DQS 0 Duty spec in!! Max-Min= 311%
7097 19:22:55.503271
7098 19:22:55.506100 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7099 19:22:55.509335 [DutyScan_Calibration_Flow] ====Done====
7100 19:22:55.509889
7101 19:22:55.512833 [DutyScan_Calibration_Flow] k_type=3
7102 19:22:55.528305
7103 19:22:55.528863 ==DQM 0 ==
7104 19:22:55.531992 Final DQM duty delay cell = -4
7105 19:22:55.534907 [-4] MAX Duty = 5093%(X100), DQS PI = 34
7106 19:22:55.538608 [-4] MIN Duty = 4782%(X100), DQS PI = 46
7107 19:22:55.541663 [-4] AVG Duty = 4937%(X100)
7108 19:22:55.542163
7109 19:22:55.542544 ==DQM 1 ==
7110 19:22:55.544884 Final DQM duty delay cell = -4
7111 19:22:55.548118 [-4] MAX Duty = 5093%(X100), DQS PI = 16
7112 19:22:55.551727 [-4] MIN Duty = 4907%(X100), DQS PI = 32
7113 19:22:55.554706 [-4] AVG Duty = 5000%(X100)
7114 19:22:55.555131
7115 19:22:55.558313 CH1 DQM 0 Duty spec in!! Max-Min= 311%
7116 19:22:55.558806
7117 19:22:55.562061 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7118 19:22:55.564992 [DutyScan_Calibration_Flow] ====Done====
7119 19:22:55.565417
7120 19:22:55.568379 [DutyScan_Calibration_Flow] k_type=2
7121 19:22:55.586019
7122 19:22:55.586587 ==DQ 0 ==
7123 19:22:55.589293 Final DQ duty delay cell = 0
7124 19:22:55.592639 [0] MAX Duty = 5093%(X100), DQS PI = 2
7125 19:22:55.596110 [0] MIN Duty = 4938%(X100), DQS PI = 46
7126 19:22:55.596536 [0] AVG Duty = 5015%(X100)
7127 19:22:55.599136
7128 19:22:55.599627 ==DQ 1 ==
7129 19:22:55.602960 Final DQ duty delay cell = 0
7130 19:22:55.606154 [0] MAX Duty = 5031%(X100), DQS PI = 4
7131 19:22:55.609002 [0] MIN Duty = 4876%(X100), DQS PI = 26
7132 19:22:55.609443 [0] AVG Duty = 4953%(X100)
7133 19:22:55.609887
7134 19:22:55.615986 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7135 19:22:55.616466
7136 19:22:55.619312 CH1 DQ 1 Duty spec in!! Max-Min= 155%
7137 19:22:55.622217 [DutyScan_Calibration_Flow] ====Done====
7138 19:22:55.625683 nWR fixed to 30
7139 19:22:55.626194 [ModeRegInit_LP4] CH0 RK0
7140 19:22:55.629123 [ModeRegInit_LP4] CH0 RK1
7141 19:22:55.632598 [ModeRegInit_LP4] CH1 RK0
7142 19:22:55.636144 [ModeRegInit_LP4] CH1 RK1
7143 19:22:55.636677 match AC timing 4
7144 19:22:55.642622 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7145 19:22:55.645808 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7146 19:22:55.649063 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7147 19:22:55.655763 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7148 19:22:55.658927 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7149 19:22:55.659368 [MiockJmeterHQA]
7150 19:22:55.659839
7151 19:22:55.661725 [DramcMiockJmeter] u1RxGatingPI = 0
7152 19:22:55.665476 0 : 4252, 4027
7153 19:22:55.665910 4 : 4253, 4026
7154 19:22:55.668843 8 : 4252, 4027
7155 19:22:55.669381 12 : 4252, 4026
7156 19:22:55.669894 16 : 4252, 4027
7157 19:22:55.671877 20 : 4363, 4137
7158 19:22:55.672330 24 : 4252, 4027
7159 19:22:55.675280 28 : 4363, 4137
7160 19:22:55.675728 32 : 4252, 4026
7161 19:22:55.678485 36 : 4252, 4027
7162 19:22:55.678916 40 : 4253, 4027
7163 19:22:55.681855 44 : 4255, 4029
7164 19:22:55.682347 48 : 4363, 4137
7165 19:22:55.682730 52 : 4252, 4029
7166 19:22:55.685039 56 : 4365, 4140
7167 19:22:55.685469 60 : 4250, 4026
7168 19:22:55.688988 64 : 4253, 4029
7169 19:22:55.689419 68 : 4250, 4026
7170 19:22:55.691526 72 : 4365, 4139
7171 19:22:55.691959 76 : 4250, 4027
7172 19:22:55.694859 80 : 4360, 4138
7173 19:22:55.695289 84 : 4250, 4026
7174 19:22:55.695634 88 : 4249, 4027
7175 19:22:55.698380 92 : 4250, 4026
7176 19:22:55.698815 96 : 4252, 4029
7177 19:22:55.702003 100 : 4250, 1761
7178 19:22:55.702474 104 : 4254, 0
7179 19:22:55.705160 108 : 4363, 0
7180 19:22:55.705687 112 : 4250, 0
7181 19:22:55.706082 116 : 4250, 0
7182 19:22:55.708439 120 : 4360, 0
7183 19:22:55.708869 124 : 4249, 0
7184 19:22:55.711387 128 : 4363, 0
7185 19:22:55.711822 132 : 4250, 0
7186 19:22:55.712386 136 : 4361, 0
7187 19:22:55.714829 140 : 4249, 0
7188 19:22:55.715262 144 : 4360, 0
7189 19:22:55.715606 148 : 4249, 0
7190 19:22:55.718527 152 : 4250, 0
7191 19:22:55.718959 156 : 4250, 0
7192 19:22:55.721275 160 : 4249, 0
7193 19:22:55.721707 164 : 4250, 0
7194 19:22:55.722080 168 : 4250, 0
7195 19:22:55.724951 172 : 4250, 0
7196 19:22:55.725384 176 : 4253, 0
7197 19:22:55.728203 180 : 4250, 0
7198 19:22:55.728637 184 : 4361, 0
7199 19:22:55.728983 188 : 4361, 0
7200 19:22:55.731390 192 : 4249, 0
7201 19:22:55.731822 196 : 4250, 0
7202 19:22:55.734847 200 : 4249, 0
7203 19:22:55.735281 204 : 4249, 0
7204 19:22:55.735647 208 : 4249, 0
7205 19:22:55.737813 212 : 4250, 0
7206 19:22:55.738284 216 : 4250, 0
7207 19:22:55.741346 220 : 4361, 398
7208 19:22:55.741867 224 : 4253, 3979
7209 19:22:55.744832 228 : 4250, 4026
7210 19:22:55.745259 232 : 4254, 4030
7211 19:22:55.745605 236 : 4360, 4138
7212 19:22:55.748163 240 : 4253, 4029
7213 19:22:55.748667 244 : 4250, 4026
7214 19:22:55.751327 248 : 4360, 4137
7215 19:22:55.751771 252 : 4250, 4027
7216 19:22:55.754735 256 : 4253, 4029
7217 19:22:55.755182 260 : 4360, 4137
7218 19:22:55.757964 264 : 4250, 4027
7219 19:22:55.758436 268 : 4250, 4026
7220 19:22:55.761099 272 : 4250, 4027
7221 19:22:55.761578 276 : 4253, 4029
7222 19:22:55.764451 280 : 4249, 4027
7223 19:22:55.764882 284 : 4250, 4027
7224 19:22:55.768170 288 : 4250, 4027
7225 19:22:55.768705 292 : 4254, 4032
7226 19:22:55.770956 296 : 4249, 4027
7227 19:22:55.771403 300 : 4360, 4138
7228 19:22:55.771751 304 : 4250, 4027
7229 19:22:55.774148 308 : 4253, 4029
7230 19:22:55.774585 312 : 4361, 4137
7231 19:22:55.777501 316 : 4360, 4137
7232 19:22:55.777968 320 : 4252, 4029
7233 19:22:55.781141 324 : 4250, 4027
7234 19:22:55.781571 328 : 4254, 4032
7235 19:22:55.783916 332 : 4249, 4027
7236 19:22:55.784348 336 : 4249, 3772
7237 19:22:55.788137 340 : 4252, 1762
7238 19:22:55.788627
7239 19:22:55.788969 MIOCK jitter meter ch=0
7240 19:22:55.789289
7241 19:22:55.791136 1T = (340-100) = 240 dly cells
7242 19:22:55.797539 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7243 19:22:55.798152 ==
7244 19:22:55.800747 Dram Type= 6, Freq= 0, CH_0, rank 0
7245 19:22:55.803925 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7246 19:22:55.804355 ==
7247 19:22:55.810337 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7248 19:22:55.814249 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7249 19:22:55.820330 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7250 19:22:55.823581 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7251 19:22:55.833187 [CA 0] Center 42 (12~73) winsize 62
7252 19:22:55.836688 [CA 1] Center 42 (12~73) winsize 62
7253 19:22:55.839843 [CA 2] Center 39 (9~69) winsize 61
7254 19:22:55.843068 [CA 3] Center 38 (9~68) winsize 60
7255 19:22:55.846452 [CA 4] Center 37 (7~67) winsize 61
7256 19:22:55.850121 [CA 5] Center 36 (6~66) winsize 61
7257 19:22:55.850630
7258 19:22:55.852964 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7259 19:22:55.853475
7260 19:22:55.856432 [CATrainingPosCal] consider 1 rank data
7261 19:22:55.860697 u2DelayCellTimex100 = 271/100 ps
7262 19:22:55.863412 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7263 19:22:55.870108 CA1 delay=42 (12~73),Diff = 6 PI (21 cell)
7264 19:22:55.873056 CA2 delay=39 (9~69),Diff = 3 PI (10 cell)
7265 19:22:55.876935 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7266 19:22:55.879751 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
7267 19:22:55.883150 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7268 19:22:55.883578
7269 19:22:55.886442 CA PerBit enable=1, Macro0, CA PI delay=36
7270 19:22:55.886946
7271 19:22:55.889899 [CBTSetCACLKResult] CA Dly = 36
7272 19:22:55.893387 CS Dly: 10 (0~41)
7273 19:22:55.896317 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7274 19:22:55.899613 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7275 19:22:55.900044 ==
7276 19:22:55.902919 Dram Type= 6, Freq= 0, CH_0, rank 1
7277 19:22:55.906240 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7278 19:22:55.909641 ==
7279 19:22:55.913058 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7280 19:22:55.916399 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7281 19:22:55.922926 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7282 19:22:55.929225 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7283 19:22:55.935916 [CA 0] Center 42 (12~73) winsize 62
7284 19:22:55.939380 [CA 1] Center 41 (11~72) winsize 62
7285 19:22:55.942600 [CA 2] Center 38 (8~68) winsize 61
7286 19:22:55.945968 [CA 3] Center 37 (7~67) winsize 61
7287 19:22:55.949022 [CA 4] Center 35 (5~65) winsize 61
7288 19:22:55.952693 [CA 5] Center 35 (5~66) winsize 62
7289 19:22:55.953192
7290 19:22:55.955487 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7291 19:22:55.955913
7292 19:22:55.959010 [CATrainingPosCal] consider 2 rank data
7293 19:22:55.962356 u2DelayCellTimex100 = 271/100 ps
7294 19:22:55.969033 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7295 19:22:55.972304 CA1 delay=42 (12~72),Diff = 6 PI (21 cell)
7296 19:22:55.975600 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7297 19:22:55.979197 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7298 19:22:55.982407 CA4 delay=36 (7~65),Diff = 0 PI (0 cell)
7299 19:22:55.985602 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7300 19:22:55.986091
7301 19:22:55.989252 CA PerBit enable=1, Macro0, CA PI delay=36
7302 19:22:55.989717
7303 19:22:55.992346 [CBTSetCACLKResult] CA Dly = 36
7304 19:22:55.995768 CS Dly: 11 (0~43)
7305 19:22:55.999103 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7306 19:22:56.002130 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7307 19:22:56.002553
7308 19:22:56.005440 ----->DramcWriteLeveling(PI) begin...
7309 19:22:56.005867 ==
7310 19:22:56.008812 Dram Type= 6, Freq= 0, CH_0, rank 0
7311 19:22:56.015218 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7312 19:22:56.015642 ==
7313 19:22:56.019303 Write leveling (Byte 0): 28 => 28
7314 19:22:56.019739 Write leveling (Byte 1): 28 => 28
7315 19:22:56.022383 DramcWriteLeveling(PI) end<-----
7316 19:22:56.022910
7317 19:22:56.025242 ==
7318 19:22:56.025686 Dram Type= 6, Freq= 0, CH_0, rank 0
7319 19:22:56.032491 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7320 19:22:56.032964 ==
7321 19:22:56.035073 [Gating] SW mode calibration
7322 19:22:56.042092 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7323 19:22:56.045340 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7324 19:22:56.052153 0 12 0 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
7325 19:22:56.055087 0 12 4 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
7326 19:22:56.058414 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7327 19:22:56.065177 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7328 19:22:56.068441 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7329 19:22:56.071788 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7330 19:22:56.078383 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7331 19:22:56.081609 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7332 19:22:56.084597 0 13 0 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 0)
7333 19:22:56.091905 0 13 4 | B1->B0 | 3333 2424 | 1 0 | (1 0) (1 0)
7334 19:22:56.094617 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7335 19:22:56.098131 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7336 19:22:56.104866 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7337 19:22:56.108347 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7338 19:22:56.111093 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7339 19:22:56.117654 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7340 19:22:56.121210 0 14 0 | B1->B0 | 2323 3636 | 0 1 | (0 0) (0 0)
7341 19:22:56.124658 0 14 4 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
7342 19:22:56.131182 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7343 19:22:56.134290 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7344 19:22:56.137459 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7345 19:22:56.144368 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7346 19:22:56.148114 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7347 19:22:56.150698 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7348 19:22:56.157725 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7349 19:22:56.160828 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7350 19:22:56.164375 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7351 19:22:56.171314 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7352 19:22:56.174624 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7353 19:22:56.178064 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7354 19:22:56.184033 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7355 19:22:56.187418 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7356 19:22:56.190844 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7357 19:22:56.197293 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7358 19:22:56.200428 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7359 19:22:56.204307 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7360 19:22:56.210736 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7361 19:22:56.213924 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7362 19:22:56.217560 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7363 19:22:56.224113 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7364 19:22:56.226885 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7365 19:22:56.230549 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7366 19:22:56.236925 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7367 19:22:56.237498 Total UI for P1: 0, mck2ui 16
7368 19:22:56.240467 best dqsien dly found for B0: ( 1, 1, 2)
7369 19:22:56.243725 Total UI for P1: 0, mck2ui 16
7370 19:22:56.247120 best dqsien dly found for B1: ( 1, 1, 4)
7371 19:22:56.250679 best DQS0 dly(MCK, UI, PI) = (1, 1, 2)
7372 19:22:56.256571 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
7373 19:22:56.257127
7374 19:22:56.259785 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 2)
7375 19:22:56.263279 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
7376 19:22:56.266694 [Gating] SW calibration Done
7377 19:22:56.267165 ==
7378 19:22:56.270389 Dram Type= 6, Freq= 0, CH_0, rank 0
7379 19:22:56.273624 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7380 19:22:56.274237 ==
7381 19:22:56.274626 RX Vref Scan: 0
7382 19:22:56.274983
7383 19:22:56.276483 RX Vref 0 -> 0, step: 1
7384 19:22:56.276950
7385 19:22:56.280035 RX Delay 0 -> 252, step: 8
7386 19:22:56.283500 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7387 19:22:56.286896 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7388 19:22:56.290504 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
7389 19:22:56.296719 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7390 19:22:56.299999 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7391 19:22:56.303554 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7392 19:22:56.306629 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
7393 19:22:56.309956 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7394 19:22:56.317003 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
7395 19:22:56.319968 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7396 19:22:56.323228 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7397 19:22:56.326634 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7398 19:22:56.332999 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7399 19:22:56.336762 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7400 19:22:56.340368 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7401 19:22:56.342826 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7402 19:22:56.343300 ==
7403 19:22:56.346349 Dram Type= 6, Freq= 0, CH_0, rank 0
7404 19:22:56.353188 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7405 19:22:56.353761 ==
7406 19:22:56.354185 DQS Delay:
7407 19:22:56.354542 DQS0 = 0, DQS1 = 0
7408 19:22:56.355896 DQM Delay:
7409 19:22:56.356365 DQM0 = 129, DQM1 = 124
7410 19:22:56.359777 DQ Delay:
7411 19:22:56.362702 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =127
7412 19:22:56.366188 DQ4 =135, DQ5 =119, DQ6 =135, DQ7 =139
7413 19:22:56.369749 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
7414 19:22:56.372831 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7415 19:22:56.373406
7416 19:22:56.373784
7417 19:22:56.374187 ==
7418 19:22:56.376248 Dram Type= 6, Freq= 0, CH_0, rank 0
7419 19:22:56.379038 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7420 19:22:56.382657 ==
7421 19:22:56.383230
7422 19:22:56.383607
7423 19:22:56.383958 TX Vref Scan disable
7424 19:22:56.386127 == TX Byte 0 ==
7425 19:22:56.389278 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7426 19:22:56.392623 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7427 19:22:56.396008 == TX Byte 1 ==
7428 19:22:56.398958 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7429 19:22:56.402483 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7430 19:22:56.405731 ==
7431 19:22:56.409073 Dram Type= 6, Freq= 0, CH_0, rank 0
7432 19:22:56.411876 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7433 19:22:56.412354 ==
7434 19:22:56.424016
7435 19:22:56.427371 TX Vref early break, caculate TX vref
7436 19:22:56.431043 TX Vref=16, minBit 8, minWin=22, winSum=379
7437 19:22:56.434395 TX Vref=18, minBit 7, minWin=23, winSum=385
7438 19:22:56.437661 TX Vref=20, minBit 9, minWin=23, winSum=393
7439 19:22:56.441041 TX Vref=22, minBit 8, minWin=24, winSum=406
7440 19:22:56.444289 TX Vref=24, minBit 8, minWin=25, winSum=416
7441 19:22:56.450742 TX Vref=26, minBit 8, minWin=25, winSum=420
7442 19:22:56.454296 TX Vref=28, minBit 1, minWin=26, winSum=422
7443 19:22:56.457535 TX Vref=30, minBit 1, minWin=25, winSum=416
7444 19:22:56.460655 TX Vref=32, minBit 8, minWin=24, winSum=407
7445 19:22:56.463963 TX Vref=34, minBit 8, minWin=22, winSum=395
7446 19:22:56.470742 [TxChooseVref] Worse bit 1, Min win 26, Win sum 422, Final Vref 28
7447 19:22:56.471315
7448 19:22:56.473549 Final TX Range 0 Vref 28
7449 19:22:56.474016
7450 19:22:56.474420 ==
7451 19:22:56.477614 Dram Type= 6, Freq= 0, CH_0, rank 0
7452 19:22:56.480820 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7453 19:22:56.481394 ==
7454 19:22:56.481771
7455 19:22:56.482170
7456 19:22:56.484067 TX Vref Scan disable
7457 19:22:56.490478 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7458 19:22:56.491058 == TX Byte 0 ==
7459 19:22:56.494010 u2DelayCellOfst[0]=10 cells (3 PI)
7460 19:22:56.497430 u2DelayCellOfst[1]=14 cells (4 PI)
7461 19:22:56.500303 u2DelayCellOfst[2]=14 cells (4 PI)
7462 19:22:56.503511 u2DelayCellOfst[3]=10 cells (3 PI)
7463 19:22:56.506876 u2DelayCellOfst[4]=10 cells (3 PI)
7464 19:22:56.510463 u2DelayCellOfst[5]=0 cells (0 PI)
7465 19:22:56.513407 u2DelayCellOfst[6]=18 cells (5 PI)
7466 19:22:56.516801 u2DelayCellOfst[7]=18 cells (5 PI)
7467 19:22:56.520227 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7468 19:22:56.523732 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7469 19:22:56.526977 == TX Byte 1 ==
7470 19:22:56.530087 u2DelayCellOfst[8]=0 cells (0 PI)
7471 19:22:56.530696 u2DelayCellOfst[9]=0 cells (0 PI)
7472 19:22:56.533782 u2DelayCellOfst[10]=10 cells (3 PI)
7473 19:22:56.537057 u2DelayCellOfst[11]=3 cells (1 PI)
7474 19:22:56.540165 u2DelayCellOfst[12]=10 cells (3 PI)
7475 19:22:56.543200 u2DelayCellOfst[13]=10 cells (3 PI)
7476 19:22:56.546741 u2DelayCellOfst[14]=18 cells (5 PI)
7477 19:22:56.550167 u2DelayCellOfst[15]=14 cells (4 PI)
7478 19:22:56.553345 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7479 19:22:56.559789 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7480 19:22:56.560362 DramC Write-DBI on
7481 19:22:56.560740 ==
7482 19:22:56.562662 Dram Type= 6, Freq= 0, CH_0, rank 0
7483 19:22:56.569549 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7484 19:22:56.570154 ==
7485 19:22:56.570541
7486 19:22:56.570935
7487 19:22:56.571453 TX Vref Scan disable
7488 19:22:56.573808 == TX Byte 0 ==
7489 19:22:56.577191 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7490 19:22:56.580269 == TX Byte 1 ==
7491 19:22:56.583559 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7492 19:22:56.586923 DramC Write-DBI off
7493 19:22:56.587391
7494 19:22:56.587765 [DATLAT]
7495 19:22:56.588203 Freq=1600, CH0 RK0
7496 19:22:56.588551
7497 19:22:56.590016 DATLAT Default: 0xf
7498 19:22:56.590529 0, 0xFFFF, sum = 0
7499 19:22:56.593404 1, 0xFFFF, sum = 0
7500 19:22:56.596786 2, 0xFFFF, sum = 0
7501 19:22:56.597365 3, 0xFFFF, sum = 0
7502 19:22:56.600100 4, 0xFFFF, sum = 0
7503 19:22:56.600682 5, 0xFFFF, sum = 0
7504 19:22:56.603709 6, 0xFFFF, sum = 0
7505 19:22:56.604288 7, 0xFFFF, sum = 0
7506 19:22:56.606410 8, 0xFFFF, sum = 0
7507 19:22:56.606888 9, 0xFFFF, sum = 0
7508 19:22:56.610155 10, 0xFFFF, sum = 0
7509 19:22:56.610729 11, 0xFFFF, sum = 0
7510 19:22:56.613200 12, 0xFFF, sum = 0
7511 19:22:56.613782 13, 0x0, sum = 1
7512 19:22:56.616948 14, 0x0, sum = 2
7513 19:22:56.617437 15, 0x0, sum = 3
7514 19:22:56.620103 16, 0x0, sum = 4
7515 19:22:56.620703 best_step = 14
7516 19:22:56.621196
7517 19:22:56.621658 ==
7518 19:22:56.623283 Dram Type= 6, Freq= 0, CH_0, rank 0
7519 19:22:56.626539 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7520 19:22:56.630120 ==
7521 19:22:56.630605 RX Vref Scan: 1
7522 19:22:56.631092
7523 19:22:56.633309 Set Vref Range= 24 -> 127
7524 19:22:56.633788
7525 19:22:56.636643 RX Vref 24 -> 127, step: 1
7526 19:22:56.637242
7527 19:22:56.637733 RX Delay 11 -> 252, step: 4
7528 19:22:56.638301
7529 19:22:56.639602 Set Vref, RX VrefLevel [Byte0]: 24
7530 19:22:56.643087 [Byte1]: 24
7531 19:22:56.646725
7532 19:22:56.647302 Set Vref, RX VrefLevel [Byte0]: 25
7533 19:22:56.650433 [Byte1]: 25
7534 19:22:56.654718
7535 19:22:56.655295 Set Vref, RX VrefLevel [Byte0]: 26
7536 19:22:56.657662 [Byte1]: 26
7537 19:22:56.662271
7538 19:22:56.662743 Set Vref, RX VrefLevel [Byte0]: 27
7539 19:22:56.665307 [Byte1]: 27
7540 19:22:56.669833
7541 19:22:56.670440 Set Vref, RX VrefLevel [Byte0]: 28
7542 19:22:56.673155 [Byte1]: 28
7543 19:22:56.677592
7544 19:22:56.678209 Set Vref, RX VrefLevel [Byte0]: 29
7545 19:22:56.680541 [Byte1]: 29
7546 19:22:56.685251
7547 19:22:56.685747 Set Vref, RX VrefLevel [Byte0]: 30
7548 19:22:56.688225 [Byte1]: 30
7549 19:22:56.693213
7550 19:22:56.693788 Set Vref, RX VrefLevel [Byte0]: 31
7551 19:22:56.695940 [Byte1]: 31
7552 19:22:56.700209
7553 19:22:56.700781 Set Vref, RX VrefLevel [Byte0]: 32
7554 19:22:56.703156 [Byte1]: 32
7555 19:22:56.707936
7556 19:22:56.708506 Set Vref, RX VrefLevel [Byte0]: 33
7557 19:22:56.710870 [Byte1]: 33
7558 19:22:56.715222
7559 19:22:56.715701 Set Vref, RX VrefLevel [Byte0]: 34
7560 19:22:56.719030 [Byte1]: 34
7561 19:22:56.722956
7562 19:22:56.723522 Set Vref, RX VrefLevel [Byte0]: 35
7563 19:22:56.726506 [Byte1]: 35
7564 19:22:56.730267
7565 19:22:56.730740 Set Vref, RX VrefLevel [Byte0]: 36
7566 19:22:56.734144 [Byte1]: 36
7567 19:22:56.738402
7568 19:22:56.738972 Set Vref, RX VrefLevel [Byte0]: 37
7569 19:22:56.741803 [Byte1]: 37
7570 19:22:56.746150
7571 19:22:56.746737 Set Vref, RX VrefLevel [Byte0]: 38
7572 19:22:56.749785 [Byte1]: 38
7573 19:22:56.753447
7574 19:22:56.754018 Set Vref, RX VrefLevel [Byte0]: 39
7575 19:22:56.756780 [Byte1]: 39
7576 19:22:56.761739
7577 19:22:56.762346 Set Vref, RX VrefLevel [Byte0]: 40
7578 19:22:56.764185 [Byte1]: 40
7579 19:22:56.768867
7580 19:22:56.769437 Set Vref, RX VrefLevel [Byte0]: 41
7581 19:22:56.772028 [Byte1]: 41
7582 19:22:56.776277
7583 19:22:56.776845 Set Vref, RX VrefLevel [Byte0]: 42
7584 19:22:56.779614 [Byte1]: 42
7585 19:22:56.783846
7586 19:22:56.784316 Set Vref, RX VrefLevel [Byte0]: 43
7587 19:22:56.787154 [Byte1]: 43
7588 19:22:56.791787
7589 19:22:56.792356 Set Vref, RX VrefLevel [Byte0]: 44
7590 19:22:56.794502 [Byte1]: 44
7591 19:22:56.799220
7592 19:22:56.799800 Set Vref, RX VrefLevel [Byte0]: 45
7593 19:22:56.802651 [Byte1]: 45
7594 19:22:56.806540
7595 19:22:56.807008 Set Vref, RX VrefLevel [Byte0]: 46
7596 19:22:56.810650 [Byte1]: 46
7597 19:22:56.814217
7598 19:22:56.814791 Set Vref, RX VrefLevel [Byte0]: 47
7599 19:22:56.817673 [Byte1]: 47
7600 19:22:56.822081
7601 19:22:56.822659 Set Vref, RX VrefLevel [Byte0]: 48
7602 19:22:56.825412 [Byte1]: 48
7603 19:22:56.829394
7604 19:22:56.830136 Set Vref, RX VrefLevel [Byte0]: 49
7605 19:22:56.832789 [Byte1]: 49
7606 19:22:56.837326
7607 19:22:56.837888 Set Vref, RX VrefLevel [Byte0]: 50
7608 19:22:56.840447 [Byte1]: 50
7609 19:22:56.844807
7610 19:22:56.845351 Set Vref, RX VrefLevel [Byte0]: 51
7611 19:22:56.848116 [Byte1]: 51
7612 19:22:56.852787
7613 19:22:56.853366 Set Vref, RX VrefLevel [Byte0]: 52
7614 19:22:56.855480 [Byte1]: 52
7615 19:22:56.859939
7616 19:22:56.860527 Set Vref, RX VrefLevel [Byte0]: 53
7617 19:22:56.863280 [Byte1]: 53
7618 19:22:56.867933
7619 19:22:56.868493 Set Vref, RX VrefLevel [Byte0]: 54
7620 19:22:56.870820 [Byte1]: 54
7621 19:22:56.875106
7622 19:22:56.875573 Set Vref, RX VrefLevel [Byte0]: 55
7623 19:22:56.878690 [Byte1]: 55
7624 19:22:56.882860
7625 19:22:56.883342 Set Vref, RX VrefLevel [Byte0]: 56
7626 19:22:56.886116 [Byte1]: 56
7627 19:22:56.890692
7628 19:22:56.891177 Set Vref, RX VrefLevel [Byte0]: 57
7629 19:22:56.893857 [Byte1]: 57
7630 19:22:56.898011
7631 19:22:56.898582 Set Vref, RX VrefLevel [Byte0]: 58
7632 19:22:56.901503 [Byte1]: 58
7633 19:22:56.905779
7634 19:22:56.906298 Set Vref, RX VrefLevel [Byte0]: 59
7635 19:22:56.908736 [Byte1]: 59
7636 19:22:56.913467
7637 19:22:56.914000 Set Vref, RX VrefLevel [Byte0]: 60
7638 19:22:56.916340 [Byte1]: 60
7639 19:22:56.921215
7640 19:22:56.921743 Set Vref, RX VrefLevel [Byte0]: 61
7641 19:22:56.924113 [Byte1]: 61
7642 19:22:56.928393
7643 19:22:56.928833 Set Vref, RX VrefLevel [Byte0]: 62
7644 19:22:56.931865 [Byte1]: 62
7645 19:22:56.936424
7646 19:22:56.936950 Set Vref, RX VrefLevel [Byte0]: 63
7647 19:22:56.939474 [Byte1]: 63
7648 19:22:56.943447
7649 19:22:56.943870 Set Vref, RX VrefLevel [Byte0]: 64
7650 19:22:56.946838 [Byte1]: 64
7651 19:22:56.951678
7652 19:22:56.952143 Set Vref, RX VrefLevel [Byte0]: 65
7653 19:22:56.954689 [Byte1]: 65
7654 19:22:56.958982
7655 19:22:56.959509 Set Vref, RX VrefLevel [Byte0]: 66
7656 19:22:56.962300 [Byte1]: 66
7657 19:22:56.966750
7658 19:22:56.967332 Set Vref, RX VrefLevel [Byte0]: 67
7659 19:22:56.970216 [Byte1]: 67
7660 19:22:56.974198
7661 19:22:56.974773 Set Vref, RX VrefLevel [Byte0]: 68
7662 19:22:56.977491 [Byte1]: 68
7663 19:22:56.982186
7664 19:22:56.982752 Set Vref, RX VrefLevel [Byte0]: 69
7665 19:22:56.985425 [Byte1]: 69
7666 19:22:56.989335
7667 19:22:56.989919 Set Vref, RX VrefLevel [Byte0]: 70
7668 19:22:56.992599 [Byte1]: 70
7669 19:22:56.997207
7670 19:22:56.997779 Set Vref, RX VrefLevel [Byte0]: 71
7671 19:22:57.000442 [Byte1]: 71
7672 19:22:57.004657
7673 19:22:57.005222 Set Vref, RX VrefLevel [Byte0]: 72
7674 19:22:57.007782 [Byte1]: 72
7675 19:22:57.012369
7676 19:22:57.012938 Final RX Vref Byte 0 = 54 to rank0
7677 19:22:57.015497 Final RX Vref Byte 1 = 55 to rank0
7678 19:22:57.018706 Final RX Vref Byte 0 = 54 to rank1
7679 19:22:57.022248 Final RX Vref Byte 1 = 55 to rank1==
7680 19:22:57.025387 Dram Type= 6, Freq= 0, CH_0, rank 0
7681 19:22:57.031592 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7682 19:22:57.032156 ==
7683 19:22:57.032533 DQS Delay:
7684 19:22:57.035240 DQS0 = 0, DQS1 = 0
7685 19:22:57.035709 DQM Delay:
7686 19:22:57.038202 DQM0 = 127, DQM1 = 121
7687 19:22:57.038731 DQ Delay:
7688 19:22:57.041385 DQ0 =124, DQ1 =128, DQ2 =124, DQ3 =122
7689 19:22:57.045182 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7690 19:22:57.048422 DQ8 =112, DQ9 =104, DQ10 =120, DQ11 =112
7691 19:22:57.051984 DQ12 =126, DQ13 =126, DQ14 =136, DQ15 =134
7692 19:22:57.052563
7693 19:22:57.052938
7694 19:22:57.053282
7695 19:22:57.054991 [DramC_TX_OE_Calibration] TA2
7696 19:22:57.058710 Original DQ_B0 (3 6) =30, OEN = 27
7697 19:22:57.061292 Original DQ_B1 (3 6) =30, OEN = 27
7698 19:22:57.064843 24, 0x0, End_B0=24 End_B1=24
7699 19:22:57.068276 25, 0x0, End_B0=25 End_B1=25
7700 19:22:57.068860 26, 0x0, End_B0=26 End_B1=26
7701 19:22:57.071774 27, 0x0, End_B0=27 End_B1=27
7702 19:22:57.074897 28, 0x0, End_B0=28 End_B1=28
7703 19:22:57.078101 29, 0x0, End_B0=29 End_B1=29
7704 19:22:57.078699 30, 0x0, End_B0=30 End_B1=30
7705 19:22:57.081828 31, 0x4141, End_B0=30 End_B1=30
7706 19:22:57.084899 Byte0 end_step=30 best_step=27
7707 19:22:57.088464 Byte1 end_step=30 best_step=27
7708 19:22:57.091252 Byte0 TX OE(2T, 0.5T) = (3, 3)
7709 19:22:57.095040 Byte1 TX OE(2T, 0.5T) = (3, 3)
7710 19:22:57.095603
7711 19:22:57.095979
7712 19:22:57.101739 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
7713 19:22:57.104820 CH0 RK0: MR19=303, MR18=1C1C
7714 19:22:57.111756 CH0_RK0: MR19=0x303, MR18=0x1C1C, DQSOSC=395, MR23=63, INC=23, DEC=15
7715 19:22:57.112315
7716 19:22:57.114214 ----->DramcWriteLeveling(PI) begin...
7717 19:22:57.114687 ==
7718 19:22:57.117770 Dram Type= 6, Freq= 0, CH_0, rank 1
7719 19:22:57.121146 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7720 19:22:57.121706 ==
7721 19:22:57.124217 Write leveling (Byte 0): 29 => 29
7722 19:22:57.127609 Write leveling (Byte 1): 29 => 29
7723 19:22:57.130927 DramcWriteLeveling(PI) end<-----
7724 19:22:57.131563
7725 19:22:57.131948 ==
7726 19:22:57.133907 Dram Type= 6, Freq= 0, CH_0, rank 1
7727 19:22:57.137638 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7728 19:22:57.140826 ==
7729 19:22:57.141389 [Gating] SW mode calibration
7730 19:22:57.150491 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7731 19:22:57.154181 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7732 19:22:57.157097 0 12 0 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
7733 19:22:57.163941 0 12 4 | B1->B0 | 2c2c 3434 | 1 1 | (1 1) (1 1)
7734 19:22:57.166786 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7735 19:22:57.170434 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7736 19:22:57.177099 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7737 19:22:57.180118 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7738 19:22:57.183588 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7739 19:22:57.190301 0 12 28 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
7740 19:22:57.193846 0 13 0 | B1->B0 | 3434 2b2b | 1 0 | (1 0) (1 0)
7741 19:22:57.196869 0 13 4 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
7742 19:22:57.203749 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7743 19:22:57.206848 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7744 19:22:57.210554 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7745 19:22:57.216485 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7746 19:22:57.219837 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7747 19:22:57.223022 0 13 28 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
7748 19:22:57.230122 0 14 0 | B1->B0 | 2323 3939 | 0 1 | (0 0) (0 0)
7749 19:22:57.232948 0 14 4 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
7750 19:22:57.236787 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7751 19:22:57.243187 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7752 19:22:57.246105 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7753 19:22:57.249629 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7754 19:22:57.256509 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7755 19:22:57.259547 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7756 19:22:57.262710 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7757 19:22:57.269863 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7758 19:22:57.272683 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7759 19:22:57.276126 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7760 19:22:57.282618 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7761 19:22:57.285713 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7762 19:22:57.289400 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7763 19:22:57.295839 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7764 19:22:57.298721 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7765 19:22:57.302913 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7766 19:22:57.308616 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7767 19:22:57.311971 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7768 19:22:57.315698 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7769 19:22:57.322374 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7770 19:22:57.325812 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7771 19:22:57.328936 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7772 19:22:57.335380 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7773 19:22:57.338618 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7774 19:22:57.342319 Total UI for P1: 0, mck2ui 16
7775 19:22:57.345445 best dqsien dly found for B0: ( 1, 0, 30)
7776 19:22:57.348832 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7777 19:22:57.352066 Total UI for P1: 0, mck2ui 16
7778 19:22:57.355227 best dqsien dly found for B1: ( 1, 1, 2)
7779 19:22:57.358556 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7780 19:22:57.361745 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
7781 19:22:57.362344
7782 19:22:57.368580 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7783 19:22:57.371742 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
7784 19:22:57.375185 [Gating] SW calibration Done
7785 19:22:57.375744 ==
7786 19:22:57.378239 Dram Type= 6, Freq= 0, CH_0, rank 1
7787 19:22:57.381515 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7788 19:22:57.382148 ==
7789 19:22:57.382644 RX Vref Scan: 0
7790 19:22:57.383105
7791 19:22:57.384629 RX Vref 0 -> 0, step: 1
7792 19:22:57.385111
7793 19:22:57.388152 RX Delay 0 -> 252, step: 8
7794 19:22:57.391411 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7795 19:22:57.394431 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7796 19:22:57.401750 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7797 19:22:57.404633 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
7798 19:22:57.407619 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7799 19:22:57.411509 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7800 19:22:57.414432 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7801 19:22:57.421893 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
7802 19:22:57.424543 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7803 19:22:57.428136 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7804 19:22:57.431437 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7805 19:22:57.434527 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7806 19:22:57.441093 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7807 19:22:57.444356 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7808 19:22:57.447455 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7809 19:22:57.450924 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7810 19:22:57.451411 ==
7811 19:22:57.454209 Dram Type= 6, Freq= 0, CH_0, rank 1
7812 19:22:57.460721 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7813 19:22:57.461306 ==
7814 19:22:57.461796 DQS Delay:
7815 19:22:57.464532 DQS0 = 0, DQS1 = 0
7816 19:22:57.465289 DQM Delay:
7817 19:22:57.465797 DQM0 = 131, DQM1 = 124
7818 19:22:57.467683 DQ Delay:
7819 19:22:57.470988 DQ0 =127, DQ1 =135, DQ2 =131, DQ3 =123
7820 19:22:57.474605 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =143
7821 19:22:57.477588 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =119
7822 19:22:57.480769 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
7823 19:22:57.481251
7824 19:22:57.481736
7825 19:22:57.482287 ==
7826 19:22:57.484429 Dram Type= 6, Freq= 0, CH_0, rank 1
7827 19:22:57.487405 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7828 19:22:57.490968 ==
7829 19:22:57.491547
7830 19:22:57.492035
7831 19:22:57.492495 TX Vref Scan disable
7832 19:22:57.494571 == TX Byte 0 ==
7833 19:22:57.497372 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7834 19:22:57.500443 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7835 19:22:57.503821 == TX Byte 1 ==
7836 19:22:57.507228 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7837 19:22:57.510825 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7838 19:22:57.513788 ==
7839 19:22:57.516851 Dram Type= 6, Freq= 0, CH_0, rank 1
7840 19:22:57.520264 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7841 19:22:57.520730 ==
7842 19:22:57.533587
7843 19:22:57.537127 TX Vref early break, caculate TX vref
7844 19:22:57.540237 TX Vref=16, minBit 9, minWin=22, winSum=385
7845 19:22:57.543600 TX Vref=18, minBit 0, minWin=23, winSum=386
7846 19:22:57.546728 TX Vref=20, minBit 7, minWin=24, winSum=400
7847 19:22:57.550143 TX Vref=22, minBit 1, minWin=24, winSum=405
7848 19:22:57.553226 TX Vref=24, minBit 1, minWin=24, winSum=411
7849 19:22:57.559732 TX Vref=26, minBit 0, minWin=25, winSum=416
7850 19:22:57.563246 TX Vref=28, minBit 1, minWin=25, winSum=422
7851 19:22:57.566531 TX Vref=30, minBit 1, minWin=24, winSum=416
7852 19:22:57.570181 TX Vref=32, minBit 1, minWin=24, winSum=407
7853 19:22:57.573278 TX Vref=34, minBit 8, minWin=23, winSum=403
7854 19:22:57.579536 TX Vref=36, minBit 8, minWin=23, winSum=394
7855 19:22:57.582701 [TxChooseVref] Worse bit 1, Min win 25, Win sum 422, Final Vref 28
7856 19:22:57.583169
7857 19:22:57.585869 Final TX Range 0 Vref 28
7858 19:22:57.586375
7859 19:22:57.586809 ==
7860 19:22:57.589621 Dram Type= 6, Freq= 0, CH_0, rank 1
7861 19:22:57.592777 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7862 19:22:57.593380 ==
7863 19:22:57.595974
7864 19:22:57.596523
7865 19:22:57.596896 TX Vref Scan disable
7866 19:22:57.602912 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7867 19:22:57.603472 == TX Byte 0 ==
7868 19:22:57.606110 u2DelayCellOfst[0]=10 cells (3 PI)
7869 19:22:57.609692 u2DelayCellOfst[1]=18 cells (5 PI)
7870 19:22:57.612388 u2DelayCellOfst[2]=10 cells (3 PI)
7871 19:22:57.615596 u2DelayCellOfst[3]=10 cells (3 PI)
7872 19:22:57.619087 u2DelayCellOfst[4]=7 cells (2 PI)
7873 19:22:57.622664 u2DelayCellOfst[5]=0 cells (0 PI)
7874 19:22:57.626225 u2DelayCellOfst[6]=14 cells (4 PI)
7875 19:22:57.629097 u2DelayCellOfst[7]=14 cells (4 PI)
7876 19:22:57.632537 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7877 19:22:57.635492 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7878 19:22:57.639092 == TX Byte 1 ==
7879 19:22:57.642626 u2DelayCellOfst[8]=0 cells (0 PI)
7880 19:22:57.646000 u2DelayCellOfst[9]=0 cells (0 PI)
7881 19:22:57.649175 u2DelayCellOfst[10]=10 cells (3 PI)
7882 19:22:57.652530 u2DelayCellOfst[11]=7 cells (2 PI)
7883 19:22:57.655463 u2DelayCellOfst[12]=14 cells (4 PI)
7884 19:22:57.659051 u2DelayCellOfst[13]=14 cells (4 PI)
7885 19:22:57.662392 u2DelayCellOfst[14]=18 cells (5 PI)
7886 19:22:57.662958 u2DelayCellOfst[15]=14 cells (4 PI)
7887 19:22:57.668682 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7888 19:22:57.672491 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7889 19:22:57.675128 DramC Write-DBI on
7890 19:22:57.675593 ==
7891 19:22:57.678658 Dram Type= 6, Freq= 0, CH_0, rank 1
7892 19:22:57.682065 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7893 19:22:57.682542 ==
7894 19:22:57.682912
7895 19:22:57.683256
7896 19:22:57.685192 TX Vref Scan disable
7897 19:22:57.685652 == TX Byte 0 ==
7898 19:22:57.692360 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7899 19:22:57.692924 == TX Byte 1 ==
7900 19:22:57.694942 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7901 19:22:57.698309 DramC Write-DBI off
7902 19:22:57.698891
7903 19:22:57.699267 [DATLAT]
7904 19:22:57.701638 Freq=1600, CH0 RK1
7905 19:22:57.702218
7906 19:22:57.702605 DATLAT Default: 0xe
7907 19:22:57.704972 0, 0xFFFF, sum = 0
7908 19:22:57.705443 1, 0xFFFF, sum = 0
7909 19:22:57.708415 2, 0xFFFF, sum = 0
7910 19:22:57.711850 3, 0xFFFF, sum = 0
7911 19:22:57.712419 4, 0xFFFF, sum = 0
7912 19:22:57.715140 5, 0xFFFF, sum = 0
7913 19:22:57.715610 6, 0xFFFF, sum = 0
7914 19:22:57.718110 7, 0xFFFF, sum = 0
7915 19:22:57.718583 8, 0xFFFF, sum = 0
7916 19:22:57.721674 9, 0xFFFF, sum = 0
7917 19:22:57.722283 10, 0xFFFF, sum = 0
7918 19:22:57.724635 11, 0xFFFF, sum = 0
7919 19:22:57.725104 12, 0x8FFF, sum = 0
7920 19:22:57.728495 13, 0x0, sum = 1
7921 19:22:57.729067 14, 0x0, sum = 2
7922 19:22:57.731825 15, 0x0, sum = 3
7923 19:22:57.732393 16, 0x0, sum = 4
7924 19:22:57.734391 best_step = 14
7925 19:22:57.735127
7926 19:22:57.735749 ==
7927 19:22:57.737950 Dram Type= 6, Freq= 0, CH_0, rank 1
7928 19:22:57.741698 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7929 19:22:57.742307 ==
7930 19:22:57.744669 RX Vref Scan: 0
7931 19:22:57.745131
7932 19:22:57.745499 RX Vref 0 -> 0, step: 1
7933 19:22:57.745845
7934 19:22:57.747980 RX Delay 11 -> 252, step: 4
7935 19:22:57.750846 iDelay=195, Bit 0, Center 124 (71 ~ 178) 108
7936 19:22:57.757918 iDelay=195, Bit 1, Center 132 (79 ~ 186) 108
7937 19:22:57.761285 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7938 19:22:57.764577 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
7939 19:22:57.767760 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
7940 19:22:57.771053 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
7941 19:22:57.777519 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
7942 19:22:57.781098 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7943 19:22:57.784003 iDelay=195, Bit 8, Center 108 (55 ~ 162) 108
7944 19:22:57.787677 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
7945 19:22:57.794145 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
7946 19:22:57.797258 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
7947 19:22:57.800487 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
7948 19:22:57.803743 iDelay=195, Bit 13, Center 128 (75 ~ 182) 108
7949 19:22:57.807421 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
7950 19:22:57.813741 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
7951 19:22:57.814328 ==
7952 19:22:57.816931 Dram Type= 6, Freq= 0, CH_0, rank 1
7953 19:22:57.820391 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7954 19:22:57.820889 ==
7955 19:22:57.821374 DQS Delay:
7956 19:22:57.823865 DQS0 = 0, DQS1 = 0
7957 19:22:57.824432 DQM Delay:
7958 19:22:57.826845 DQM0 = 129, DQM1 = 120
7959 19:22:57.827328 DQ Delay:
7960 19:22:57.830517 DQ0 =124, DQ1 =132, DQ2 =126, DQ3 =124
7961 19:22:57.833514 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =138
7962 19:22:57.836675 DQ8 =108, DQ9 =106, DQ10 =122, DQ11 =112
7963 19:22:57.840186 DQ12 =126, DQ13 =128, DQ14 =132, DQ15 =130
7964 19:22:57.843605
7965 19:22:57.844185
7966 19:22:57.844563
7967 19:22:57.844906 [DramC_TX_OE_Calibration] TA2
7968 19:22:57.846705 Original DQ_B0 (3 6) =30, OEN = 27
7969 19:22:57.850210 Original DQ_B1 (3 6) =30, OEN = 27
7970 19:22:57.853222 24, 0x0, End_B0=24 End_B1=24
7971 19:22:57.856891 25, 0x0, End_B0=25 End_B1=25
7972 19:22:57.860145 26, 0x0, End_B0=26 End_B1=26
7973 19:22:57.860712 27, 0x0, End_B0=27 End_B1=27
7974 19:22:57.863859 28, 0x0, End_B0=28 End_B1=28
7975 19:22:57.866580 29, 0x0, End_B0=29 End_B1=29
7976 19:22:57.869940 30, 0x0, End_B0=30 End_B1=30
7977 19:22:57.873397 31, 0x5151, End_B0=30 End_B1=30
7978 19:22:57.876683 Byte0 end_step=30 best_step=27
7979 19:22:57.877254 Byte1 end_step=30 best_step=27
7980 19:22:57.879894 Byte0 TX OE(2T, 0.5T) = (3, 3)
7981 19:22:57.882785 Byte1 TX OE(2T, 0.5T) = (3, 3)
7982 19:22:57.883268
7983 19:22:57.883753
7984 19:22:57.892967 [DQSOSCAuto] RK1, (LSB)MR18= 0x2121, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
7985 19:22:57.893541 CH0 RK1: MR19=303, MR18=2121
7986 19:22:57.899493 CH0_RK1: MR19=0x303, MR18=0x2121, DQSOSC=393, MR23=63, INC=23, DEC=15
7987 19:22:57.902992 [RxdqsGatingPostProcess] freq 1600
7988 19:22:57.909793 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
7989 19:22:57.912876 Pre-setting of DQS Precalculation
7990 19:22:57.916157 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7991 19:22:57.916646 ==
7992 19:22:57.919260 Dram Type= 6, Freq= 0, CH_1, rank 0
7993 19:22:57.926183 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7994 19:22:57.926763 ==
7995 19:22:57.929405 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7996 19:22:57.935823 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
7997 19:22:57.939485 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
7998 19:22:57.945953 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7999 19:22:57.952685 [CA 0] Center 41 (11~71) winsize 61
8000 19:22:57.956294 [CA 1] Center 41 (11~72) winsize 62
8001 19:22:57.959550 [CA 2] Center 37 (7~67) winsize 61
8002 19:22:57.962674 [CA 3] Center 36 (7~66) winsize 60
8003 19:22:57.966400 [CA 4] Center 34 (4~64) winsize 61
8004 19:22:57.968918 [CA 5] Center 34 (5~64) winsize 60
8005 19:22:57.969384
8006 19:22:57.972932 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8007 19:22:57.973501
8008 19:22:57.975846 [CATrainingPosCal] consider 1 rank data
8009 19:22:57.979142 u2DelayCellTimex100 = 271/100 ps
8010 19:22:57.982502 CA0 delay=41 (11~71),Diff = 7 PI (25 cell)
8011 19:22:57.989422 CA1 delay=41 (11~72),Diff = 7 PI (25 cell)
8012 19:22:57.992800 CA2 delay=37 (7~67),Diff = 3 PI (10 cell)
8013 19:22:57.996192 CA3 delay=36 (7~66),Diff = 2 PI (7 cell)
8014 19:22:57.999036 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
8015 19:22:58.002508 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
8016 19:22:58.002974
8017 19:22:58.005904 CA PerBit enable=1, Macro0, CA PI delay=34
8018 19:22:58.006409
8019 19:22:58.009290 [CBTSetCACLKResult] CA Dly = 34
8020 19:22:58.012733 CS Dly: 8 (0~39)
8021 19:22:58.015715 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8022 19:22:58.018912 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8023 19:22:58.019375 ==
8024 19:22:58.022411 Dram Type= 6, Freq= 0, CH_1, rank 1
8025 19:22:58.025746 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8026 19:22:58.029082 ==
8027 19:22:58.032559 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8028 19:22:58.035654 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8029 19:22:58.042238 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8030 19:22:58.045350 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8031 19:22:58.055636 [CA 0] Center 39 (10~69) winsize 60
8032 19:22:58.058494 [CA 1] Center 39 (9~69) winsize 61
8033 19:22:58.061678 [CA 2] Center 35 (6~65) winsize 60
8034 19:22:58.065301 [CA 3] Center 35 (6~64) winsize 59
8035 19:22:58.068168 [CA 4] Center 33 (3~63) winsize 61
8036 19:22:58.071431 [CA 5] Center 33 (3~63) winsize 61
8037 19:22:58.071900
8038 19:22:58.074626 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8039 19:22:58.075095
8040 19:22:58.077980 [CATrainingPosCal] consider 2 rank data
8041 19:22:58.081189 u2DelayCellTimex100 = 271/100 ps
8042 19:22:58.087558 CA0 delay=40 (11~69),Diff = 7 PI (25 cell)
8043 19:22:58.091472 CA1 delay=40 (11~69),Diff = 7 PI (25 cell)
8044 19:22:58.094770 CA2 delay=36 (7~65),Diff = 3 PI (10 cell)
8045 19:22:58.097605 CA3 delay=35 (7~64),Diff = 2 PI (7 cell)
8046 19:22:58.101622 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
8047 19:22:58.104172 CA5 delay=34 (5~63),Diff = 1 PI (3 cell)
8048 19:22:58.104600
8049 19:22:58.107636 CA PerBit enable=1, Macro0, CA PI delay=33
8050 19:22:58.108075
8051 19:22:58.111103 [CBTSetCACLKResult] CA Dly = 33
8052 19:22:58.114735 CS Dly: 9 (0~41)
8053 19:22:58.117524 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8054 19:22:58.120798 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8055 19:22:58.121233
8056 19:22:58.124520 ----->DramcWriteLeveling(PI) begin...
8057 19:22:58.124978 ==
8058 19:22:58.127894 Dram Type= 6, Freq= 0, CH_1, rank 0
8059 19:22:58.134551 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8060 19:22:58.135118 ==
8061 19:22:58.137295 Write leveling (Byte 0): 20 => 20
8062 19:22:58.141050 Write leveling (Byte 1): 23 => 23
8063 19:22:58.141489 DramcWriteLeveling(PI) end<-----
8064 19:22:58.142012
8065 19:22:58.143987 ==
8066 19:22:58.147298 Dram Type= 6, Freq= 0, CH_1, rank 0
8067 19:22:58.151513 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8068 19:22:58.152045 ==
8069 19:22:58.153957 [Gating] SW mode calibration
8070 19:22:58.160641 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8071 19:22:58.164314 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8072 19:22:58.170853 0 12 0 | B1->B0 | 2625 3434 | 1 0 | (0 0) (0 0)
8073 19:22:58.174444 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8074 19:22:58.177393 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8075 19:22:58.184066 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8076 19:22:58.187592 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8077 19:22:58.190932 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8078 19:22:58.197441 0 12 24 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
8079 19:22:58.200667 0 12 28 | B1->B0 | 3434 2525 | 1 0 | (1 0) (1 0)
8080 19:22:58.203696 0 13 0 | B1->B0 | 3434 2323 | 0 0 | (0 1) (1 0)
8081 19:22:58.210479 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8082 19:22:58.213577 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8083 19:22:58.216633 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8084 19:22:58.223847 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8085 19:22:58.226690 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8086 19:22:58.230119 0 13 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8087 19:22:58.236422 0 13 28 | B1->B0 | 2323 3f3f | 0 0 | (0 0) (0 0)
8088 19:22:58.239951 0 14 0 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
8089 19:22:58.242985 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8090 19:22:58.250435 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8091 19:22:58.253243 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8092 19:22:58.256606 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8093 19:22:58.263524 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8094 19:22:58.266597 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8095 19:22:58.269758 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8096 19:22:58.276992 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8097 19:22:58.279698 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8098 19:22:58.283219 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 19:22:58.289554 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8100 19:22:58.293386 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8101 19:22:58.296273 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8102 19:22:58.302901 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8103 19:22:58.306448 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8104 19:22:58.309893 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8105 19:22:58.316087 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8106 19:22:58.319398 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8107 19:22:58.322385 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8108 19:22:58.329782 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8109 19:22:58.333284 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8110 19:22:58.336377 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8111 19:22:58.342763 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8112 19:22:58.343327 Total UI for P1: 0, mck2ui 16
8113 19:22:58.345903 best dqsien dly found for B0: ( 1, 0, 24)
8114 19:22:58.352643 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8115 19:22:58.355636 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8116 19:22:58.359541 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8117 19:22:58.362346 Total UI for P1: 0, mck2ui 16
8118 19:22:58.365781 best dqsien dly found for B1: ( 1, 1, 0)
8119 19:22:58.372677 best DQS0 dly(MCK, UI, PI) = (1, 0, 24)
8120 19:22:58.375784 best DQS1 dly(MCK, UI, PI) = (1, 1, 0)
8121 19:22:58.376347
8122 19:22:58.379061 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 24)
8123 19:22:58.382176 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 0)
8124 19:22:58.385764 [Gating] SW calibration Done
8125 19:22:58.386465 ==
8126 19:22:58.388594 Dram Type= 6, Freq= 0, CH_1, rank 0
8127 19:22:58.392055 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8128 19:22:58.392678 ==
8129 19:22:58.395210 RX Vref Scan: 0
8130 19:22:58.395666
8131 19:22:58.396033 RX Vref 0 -> 0, step: 1
8132 19:22:58.396377
8133 19:22:58.398552 RX Delay 0 -> 252, step: 8
8134 19:22:58.402264 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8135 19:22:58.405606 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8136 19:22:58.412115 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8137 19:22:58.415238 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8138 19:22:58.418977 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8139 19:22:58.422085 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8140 19:22:58.425735 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8141 19:22:58.431860 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8142 19:22:58.435658 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8143 19:22:58.438215 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8144 19:22:58.441905 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8145 19:22:58.445707 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8146 19:22:58.452337 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8147 19:22:58.454936 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8148 19:22:58.458482 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8149 19:22:58.461979 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8150 19:22:58.462600 ==
8151 19:22:58.465209 Dram Type= 6, Freq= 0, CH_1, rank 0
8152 19:22:58.472044 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8153 19:22:58.472609 ==
8154 19:22:58.472981 DQS Delay:
8155 19:22:58.474831 DQS0 = 0, DQS1 = 0
8156 19:22:58.475290 DQM Delay:
8157 19:22:58.478230 DQM0 = 129, DQM1 = 125
8158 19:22:58.478789 DQ Delay:
8159 19:22:58.481453 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =127
8160 19:22:58.484541 DQ4 =131, DQ5 =139, DQ6 =135, DQ7 =127
8161 19:22:58.487969 DQ8 =107, DQ9 =119, DQ10 =127, DQ11 =115
8162 19:22:58.491496 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =135
8163 19:22:58.492060
8164 19:22:58.492451
8165 19:22:58.492817 ==
8166 19:22:58.494526 Dram Type= 6, Freq= 0, CH_1, rank 0
8167 19:22:58.501615 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8168 19:22:58.502228 ==
8169 19:22:58.502627
8170 19:22:58.502978
8171 19:22:58.503309 TX Vref Scan disable
8172 19:22:58.505175 == TX Byte 0 ==
8173 19:22:58.507930 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8174 19:22:58.514615 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8175 19:22:58.515193 == TX Byte 1 ==
8176 19:22:58.518132 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8177 19:22:58.524517 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8178 19:22:58.524980 ==
8179 19:22:58.528168 Dram Type= 6, Freq= 0, CH_1, rank 0
8180 19:22:58.531536 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8181 19:22:58.532098 ==
8182 19:22:58.543588
8183 19:22:58.546781 TX Vref early break, caculate TX vref
8184 19:22:58.550172 TX Vref=16, minBit 1, minWin=21, winSum=364
8185 19:22:58.553753 TX Vref=18, minBit 3, minWin=22, winSum=376
8186 19:22:58.557137 TX Vref=20, minBit 0, minWin=23, winSum=383
8187 19:22:58.560349 TX Vref=22, minBit 3, minWin=23, winSum=393
8188 19:22:58.563583 TX Vref=24, minBit 3, minWin=23, winSum=403
8189 19:22:58.570360 TX Vref=26, minBit 3, minWin=24, winSum=410
8190 19:22:58.573750 TX Vref=28, minBit 3, minWin=24, winSum=413
8191 19:22:58.577305 TX Vref=30, minBit 3, minWin=24, winSum=405
8192 19:22:58.579988 TX Vref=32, minBit 0, minWin=24, winSum=396
8193 19:22:58.583873 TX Vref=34, minBit 9, minWin=23, winSum=385
8194 19:22:58.590294 [TxChooseVref] Worse bit 3, Min win 24, Win sum 413, Final Vref 28
8195 19:22:58.590856
8196 19:22:58.593368 Final TX Range 0 Vref 28
8197 19:22:58.593942
8198 19:22:58.594426 ==
8199 19:22:58.596579 Dram Type= 6, Freq= 0, CH_1, rank 0
8200 19:22:58.600174 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8201 19:22:58.600737 ==
8202 19:22:58.601107
8203 19:22:58.601447
8204 19:22:58.603175 TX Vref Scan disable
8205 19:22:58.609968 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8206 19:22:58.610568 == TX Byte 0 ==
8207 19:22:58.613533 u2DelayCellOfst[0]=18 cells (5 PI)
8208 19:22:58.616517 u2DelayCellOfst[1]=10 cells (3 PI)
8209 19:22:58.620043 u2DelayCellOfst[2]=0 cells (0 PI)
8210 19:22:58.623337 u2DelayCellOfst[3]=7 cells (2 PI)
8211 19:22:58.626774 u2DelayCellOfst[4]=10 cells (3 PI)
8212 19:22:58.630157 u2DelayCellOfst[5]=18 cells (5 PI)
8213 19:22:58.633279 u2DelayCellOfst[6]=18 cells (5 PI)
8214 19:22:58.633903 u2DelayCellOfst[7]=7 cells (2 PI)
8215 19:22:58.639841 Update DQ dly =971 (3 ,6, 11) DQ OEN =(3 ,3)
8216 19:22:58.643303 Update DQM dly =973 (3 ,6, 13) DQM OEN =(3 ,3)
8217 19:22:58.643771 == TX Byte 1 ==
8218 19:22:58.646269 u2DelayCellOfst[8]=0 cells (0 PI)
8219 19:22:58.649855 u2DelayCellOfst[9]=7 cells (2 PI)
8220 19:22:58.653284 u2DelayCellOfst[10]=10 cells (3 PI)
8221 19:22:58.656629 u2DelayCellOfst[11]=3 cells (1 PI)
8222 19:22:58.660057 u2DelayCellOfst[12]=18 cells (5 PI)
8223 19:22:58.662978 u2DelayCellOfst[13]=21 cells (6 PI)
8224 19:22:58.666445 u2DelayCellOfst[14]=21 cells (6 PI)
8225 19:22:58.670018 u2DelayCellOfst[15]=21 cells (6 PI)
8226 19:22:58.673237 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8227 19:22:58.679451 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8228 19:22:58.680028 DramC Write-DBI on
8229 19:22:58.680409 ==
8230 19:22:58.682991 Dram Type= 6, Freq= 0, CH_1, rank 0
8231 19:22:58.686322 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8232 19:22:58.689262 ==
8233 19:22:58.689725
8234 19:22:58.690158
8235 19:22:58.690508 TX Vref Scan disable
8236 19:22:58.692842 == TX Byte 0 ==
8237 19:22:58.695939 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8238 19:22:58.699419 == TX Byte 1 ==
8239 19:22:58.702744 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8240 19:22:58.706269 DramC Write-DBI off
8241 19:22:58.706830
8242 19:22:58.707200 [DATLAT]
8243 19:22:58.707538 Freq=1600, CH1 RK0
8244 19:22:58.707869
8245 19:22:58.709660 DATLAT Default: 0xf
8246 19:22:58.710159 0, 0xFFFF, sum = 0
8247 19:22:58.713237 1, 0xFFFF, sum = 0
8248 19:22:58.715876 2, 0xFFFF, sum = 0
8249 19:22:58.716384 3, 0xFFFF, sum = 0
8250 19:22:58.719363 4, 0xFFFF, sum = 0
8251 19:22:58.719847 5, 0xFFFF, sum = 0
8252 19:22:58.722703 6, 0xFFFF, sum = 0
8253 19:22:58.723170 7, 0xFFFF, sum = 0
8254 19:22:58.726193 8, 0xFFFF, sum = 0
8255 19:22:58.726761 9, 0xFFFF, sum = 0
8256 19:22:58.729943 10, 0xFFFF, sum = 0
8257 19:22:58.730768 11, 0xFFFF, sum = 0
8258 19:22:58.732287 12, 0xF7F, sum = 0
8259 19:22:58.732761 13, 0x0, sum = 1
8260 19:22:58.736600 14, 0x0, sum = 2
8261 19:22:58.737193 15, 0x0, sum = 3
8262 19:22:58.739318 16, 0x0, sum = 4
8263 19:22:58.739786 best_step = 14
8264 19:22:58.740291
8265 19:22:58.740942 ==
8266 19:22:58.742250 Dram Type= 6, Freq= 0, CH_1, rank 0
8267 19:22:58.746075 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8268 19:22:58.749204 ==
8269 19:22:58.749762 RX Vref Scan: 1
8270 19:22:58.750189
8271 19:22:58.752242 Set Vref Range= 24 -> 127
8272 19:22:58.752700
8273 19:22:58.755467 RX Vref 24 -> 127, step: 1
8274 19:22:58.755928
8275 19:22:58.756291 RX Delay 3 -> 252, step: 4
8276 19:22:58.756630
8277 19:22:58.758612 Set Vref, RX VrefLevel [Byte0]: 24
8278 19:22:58.762260 [Byte1]: 24
8279 19:22:58.766074
8280 19:22:58.766638 Set Vref, RX VrefLevel [Byte0]: 25
8281 19:22:58.769653 [Byte1]: 25
8282 19:22:58.773444
8283 19:22:58.773902 Set Vref, RX VrefLevel [Byte0]: 26
8284 19:22:58.776936 [Byte1]: 26
8285 19:22:58.781383
8286 19:22:58.781962 Set Vref, RX VrefLevel [Byte0]: 27
8287 19:22:58.784801 [Byte1]: 27
8288 19:22:58.788622
8289 19:22:58.789083 Set Vref, RX VrefLevel [Byte0]: 28
8290 19:22:58.792223 [Byte1]: 28
8291 19:22:58.796654
8292 19:22:58.797211 Set Vref, RX VrefLevel [Byte0]: 29
8293 19:22:58.799692 [Byte1]: 29
8294 19:22:58.804107
8295 19:22:58.804664 Set Vref, RX VrefLevel [Byte0]: 30
8296 19:22:58.807409 [Byte1]: 30
8297 19:22:58.811958
8298 19:22:58.812525 Set Vref, RX VrefLevel [Byte0]: 31
8299 19:22:58.815170 [Byte1]: 31
8300 19:22:58.819630
8301 19:22:58.820087 Set Vref, RX VrefLevel [Byte0]: 32
8302 19:22:58.822583 [Byte1]: 32
8303 19:22:58.827352
8304 19:22:58.827807 Set Vref, RX VrefLevel [Byte0]: 33
8305 19:22:58.833501 [Byte1]: 33
8306 19:22:58.833914
8307 19:22:58.836787 Set Vref, RX VrefLevel [Byte0]: 34
8308 19:22:58.840232 [Byte1]: 34
8309 19:22:58.840646
8310 19:22:58.843642 Set Vref, RX VrefLevel [Byte0]: 35
8311 19:22:58.846609 [Byte1]: 35
8312 19:22:58.849898
8313 19:22:58.850298 Set Vref, RX VrefLevel [Byte0]: 36
8314 19:22:58.853713 [Byte1]: 36
8315 19:22:58.857511
8316 19:22:58.857957 Set Vref, RX VrefLevel [Byte0]: 37
8317 19:22:58.860927 [Byte1]: 37
8318 19:22:58.865501
8319 19:22:58.866115 Set Vref, RX VrefLevel [Byte0]: 38
8320 19:22:58.868614 [Byte1]: 38
8321 19:22:58.873102
8322 19:22:58.873616 Set Vref, RX VrefLevel [Byte0]: 39
8323 19:22:58.876440 [Byte1]: 39
8324 19:22:58.880628
8325 19:22:58.881043 Set Vref, RX VrefLevel [Byte0]: 40
8326 19:22:58.883879 [Byte1]: 40
8327 19:22:58.888674
8328 19:22:58.889190 Set Vref, RX VrefLevel [Byte0]: 41
8329 19:22:58.891770 [Byte1]: 41
8330 19:22:58.896121
8331 19:22:58.896643 Set Vref, RX VrefLevel [Byte0]: 42
8332 19:22:58.899282 [Byte1]: 42
8333 19:22:58.904069
8334 19:22:58.904600 Set Vref, RX VrefLevel [Byte0]: 43
8335 19:22:58.906848 [Byte1]: 43
8336 19:22:58.911590
8337 19:22:58.912115 Set Vref, RX VrefLevel [Byte0]: 44
8338 19:22:58.914679 [Byte1]: 44
8339 19:22:58.918929
8340 19:22:58.919447 Set Vref, RX VrefLevel [Byte0]: 45
8341 19:22:58.922196 [Byte1]: 45
8342 19:22:58.926895
8343 19:22:58.927460 Set Vref, RX VrefLevel [Byte0]: 46
8344 19:22:58.930661 [Byte1]: 46
8345 19:22:58.934590
8346 19:22:58.935154 Set Vref, RX VrefLevel [Byte0]: 47
8347 19:22:58.937816 [Byte1]: 47
8348 19:22:58.942407
8349 19:22:58.942971 Set Vref, RX VrefLevel [Byte0]: 48
8350 19:22:58.945257 [Byte1]: 48
8351 19:22:58.949806
8352 19:22:58.950428 Set Vref, RX VrefLevel [Byte0]: 49
8353 19:22:58.953107 [Byte1]: 49
8354 19:22:58.957835
8355 19:22:58.958458 Set Vref, RX VrefLevel [Byte0]: 50
8356 19:22:58.960427 [Byte1]: 50
8357 19:22:58.964728
8358 19:22:58.965308 Set Vref, RX VrefLevel [Byte0]: 51
8359 19:22:58.968316 [Byte1]: 51
8360 19:22:58.972724
8361 19:22:58.973293 Set Vref, RX VrefLevel [Byte0]: 52
8362 19:22:58.975861 [Byte1]: 52
8363 19:22:58.980391
8364 19:22:58.980977 Set Vref, RX VrefLevel [Byte0]: 53
8365 19:22:58.984062 [Byte1]: 53
8366 19:22:58.987834
8367 19:22:58.988295 Set Vref, RX VrefLevel [Byte0]: 54
8368 19:22:58.991159 [Byte1]: 54
8369 19:22:58.995416
8370 19:22:58.998980 Set Vref, RX VrefLevel [Byte0]: 55
8371 19:22:59.001940 [Byte1]: 55
8372 19:22:59.002559
8373 19:22:59.005390 Set Vref, RX VrefLevel [Byte0]: 56
8374 19:22:59.008570 [Byte1]: 56
8375 19:22:59.009132
8376 19:22:59.012032 Set Vref, RX VrefLevel [Byte0]: 57
8377 19:22:59.015477 [Byte1]: 57
8378 19:22:59.016047
8379 19:22:59.018626 Set Vref, RX VrefLevel [Byte0]: 58
8380 19:22:59.022206 [Byte1]: 58
8381 19:22:59.026586
8382 19:22:59.027147 Set Vref, RX VrefLevel [Byte0]: 59
8383 19:22:59.029489 [Byte1]: 59
8384 19:22:59.033824
8385 19:22:59.034442 Set Vref, RX VrefLevel [Byte0]: 60
8386 19:22:59.037644 [Byte1]: 60
8387 19:22:59.041486
8388 19:22:59.042157 Set Vref, RX VrefLevel [Byte0]: 61
8389 19:22:59.045041 [Byte1]: 61
8390 19:22:59.049077
8391 19:22:59.049646 Set Vref, RX VrefLevel [Byte0]: 62
8392 19:22:59.052546 [Byte1]: 62
8393 19:22:59.056853
8394 19:22:59.057419 Set Vref, RX VrefLevel [Byte0]: 63
8395 19:22:59.060219 [Byte1]: 63
8396 19:22:59.064443
8397 19:22:59.065006 Set Vref, RX VrefLevel [Byte0]: 64
8398 19:22:59.067839 [Byte1]: 64
8399 19:22:59.072000
8400 19:22:59.072469 Set Vref, RX VrefLevel [Byte0]: 65
8401 19:22:59.075559 [Byte1]: 65
8402 19:22:59.079924
8403 19:22:59.080511 Set Vref, RX VrefLevel [Byte0]: 66
8404 19:22:59.082852 [Byte1]: 66
8405 19:22:59.087579
8406 19:22:59.088037 Set Vref, RX VrefLevel [Byte0]: 67
8407 19:22:59.090699 [Byte1]: 67
8408 19:22:59.094754
8409 19:22:59.095213 Set Vref, RX VrefLevel [Byte0]: 68
8410 19:22:59.098361 [Byte1]: 68
8411 19:22:59.102765
8412 19:22:59.103348 Set Vref, RX VrefLevel [Byte0]: 69
8413 19:22:59.106413 [Byte1]: 69
8414 19:22:59.110263
8415 19:22:59.110729 Set Vref, RX VrefLevel [Byte0]: 70
8416 19:22:59.113423 [Byte1]: 70
8417 19:22:59.118322
8418 19:22:59.118887 Set Vref, RX VrefLevel [Byte0]: 71
8419 19:22:59.121914 [Byte1]: 71
8420 19:22:59.125874
8421 19:22:59.126490 Set Vref, RX VrefLevel [Byte0]: 72
8422 19:22:59.129073 [Byte1]: 72
8423 19:22:59.133734
8424 19:22:59.134357 Set Vref, RX VrefLevel [Byte0]: 73
8425 19:22:59.136796 [Byte1]: 73
8426 19:22:59.141103
8427 19:22:59.141670 Set Vref, RX VrefLevel [Byte0]: 74
8428 19:22:59.144288 [Byte1]: 74
8429 19:22:59.149156
8430 19:22:59.149725 Set Vref, RX VrefLevel [Byte0]: 75
8431 19:22:59.151893 [Byte1]: 75
8432 19:22:59.156452
8433 19:22:59.157023 Final RX Vref Byte 0 = 63 to rank0
8434 19:22:59.159630 Final RX Vref Byte 1 = 54 to rank0
8435 19:22:59.162724 Final RX Vref Byte 0 = 63 to rank1
8436 19:22:59.166257 Final RX Vref Byte 1 = 54 to rank1==
8437 19:22:59.169438 Dram Type= 6, Freq= 0, CH_1, rank 0
8438 19:22:59.176131 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8439 19:22:59.176711 ==
8440 19:22:59.177084 DQS Delay:
8441 19:22:59.179128 DQS0 = 0, DQS1 = 0
8442 19:22:59.179590 DQM Delay:
8443 19:22:59.179959 DQM0 = 128, DQM1 = 123
8444 19:22:59.182924 DQ Delay:
8445 19:22:59.186179 DQ0 =132, DQ1 =122, DQ2 =116, DQ3 =126
8446 19:22:59.189423 DQ4 =128, DQ5 =138, DQ6 =138, DQ7 =126
8447 19:22:59.192956 DQ8 =106, DQ9 =114, DQ10 =124, DQ11 =114
8448 19:22:59.195959 DQ12 =130, DQ13 =134, DQ14 =134, DQ15 =134
8449 19:22:59.196525
8450 19:22:59.196934
8451 19:22:59.197488
8452 19:22:59.199237 [DramC_TX_OE_Calibration] TA2
8453 19:22:59.202246 Original DQ_B0 (3 6) =30, OEN = 27
8454 19:22:59.205672 Original DQ_B1 (3 6) =30, OEN = 27
8455 19:22:59.209265 24, 0x0, End_B0=24 End_B1=24
8456 19:22:59.209836 25, 0x0, End_B0=25 End_B1=25
8457 19:22:59.212218 26, 0x0, End_B0=26 End_B1=26
8458 19:22:59.215698 27, 0x0, End_B0=27 End_B1=27
8459 19:22:59.218676 28, 0x0, End_B0=28 End_B1=28
8460 19:22:59.221976 29, 0x0, End_B0=29 End_B1=29
8461 19:22:59.222520 30, 0x0, End_B0=30 End_B1=30
8462 19:22:59.225591 31, 0x4141, End_B0=30 End_B1=30
8463 19:22:59.229147 Byte0 end_step=30 best_step=27
8464 19:22:59.232035 Byte1 end_step=30 best_step=27
8465 19:22:59.235745 Byte0 TX OE(2T, 0.5T) = (3, 3)
8466 19:22:59.238995 Byte1 TX OE(2T, 0.5T) = (3, 3)
8467 19:22:59.239457
8468 19:22:59.239827
8469 19:22:59.245716 [DQSOSCAuto] RK0, (LSB)MR18= 0x2525, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
8470 19:22:59.248841 CH1 RK0: MR19=303, MR18=2525
8471 19:22:59.255637 CH1_RK0: MR19=0x303, MR18=0x2525, DQSOSC=391, MR23=63, INC=24, DEC=16
8472 19:22:59.256149
8473 19:22:59.259084 ----->DramcWriteLeveling(PI) begin...
8474 19:22:59.259606 ==
8475 19:22:59.261798 Dram Type= 6, Freq= 0, CH_1, rank 1
8476 19:22:59.265274 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8477 19:22:59.265693 ==
8478 19:22:59.268774 Write leveling (Byte 0): 22 => 22
8479 19:22:59.272085 Write leveling (Byte 1): 21 => 21
8480 19:22:59.275328 DramcWriteLeveling(PI) end<-----
8481 19:22:59.276048
8482 19:22:59.276398 ==
8483 19:22:59.278469 Dram Type= 6, Freq= 0, CH_1, rank 1
8484 19:22:59.281941 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8485 19:22:59.282415 ==
8486 19:22:59.284976 [Gating] SW mode calibration
8487 19:22:59.291667 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8488 19:22:59.298269 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8489 19:22:59.301527 0 12 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
8490 19:22:59.308254 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8491 19:22:59.311757 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8492 19:22:59.315196 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8493 19:22:59.321797 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8494 19:22:59.324924 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8495 19:22:59.328226 0 12 24 | B1->B0 | 3434 2525 | 1 0 | (1 1) (1 0)
8496 19:22:59.334689 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8497 19:22:59.338149 0 13 0 | B1->B0 | 2b2b 2323 | 0 0 | (0 1) (0 0)
8498 19:22:59.341593 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8499 19:22:59.348091 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8500 19:22:59.351463 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8501 19:22:59.354960 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8502 19:22:59.361547 0 13 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8503 19:22:59.365037 0 13 24 | B1->B0 | 2323 3838 | 0 0 | (0 0) (1 1)
8504 19:22:59.368289 0 13 28 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
8505 19:22:59.374947 0 14 0 | B1->B0 | 3f3f 4646 | 0 0 | (1 1) (0 0)
8506 19:22:59.378095 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8507 19:22:59.381773 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8508 19:22:59.384532 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8509 19:22:59.391464 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8510 19:22:59.394760 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8511 19:22:59.401012 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8512 19:22:59.404685 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8513 19:22:59.407546 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8514 19:22:59.411204 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8515 19:22:59.417490 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8516 19:22:59.421012 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8517 19:22:59.424090 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8518 19:22:59.430987 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8519 19:22:59.433993 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8520 19:22:59.440675 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8521 19:22:59.444099 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8522 19:22:59.447149 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8523 19:22:59.450439 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8524 19:22:59.457158 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8525 19:22:59.460364 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8526 19:22:59.463774 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8527 19:22:59.470594 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8528 19:22:59.473763 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8529 19:22:59.476930 Total UI for P1: 0, mck2ui 16
8530 19:22:59.480120 best dqsien dly found for B0: ( 1, 0, 24)
8531 19:22:59.483716 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8532 19:22:59.486384 Total UI for P1: 0, mck2ui 16
8533 19:22:59.490368 best dqsien dly found for B1: ( 1, 0, 30)
8534 19:22:59.493336 best DQS0 dly(MCK, UI, PI) = (1, 0, 24)
8535 19:22:59.500301 best DQS1 dly(MCK, UI, PI) = (1, 0, 30)
8536 19:22:59.500984
8537 19:22:59.503467 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 24)
8538 19:22:59.507207 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 30)
8539 19:22:59.509807 [Gating] SW calibration Done
8540 19:22:59.510300 ==
8541 19:22:59.513466 Dram Type= 6, Freq= 0, CH_1, rank 1
8542 19:22:59.516631 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8543 19:22:59.517200 ==
8544 19:22:59.519504 RX Vref Scan: 0
8545 19:22:59.519976
8546 19:22:59.520341 RX Vref 0 -> 0, step: 1
8547 19:22:59.520689
8548 19:22:59.522877 RX Delay 0 -> 252, step: 8
8549 19:22:59.526473 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8550 19:22:59.529754 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8551 19:22:59.536266 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8552 19:22:59.539250 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8553 19:22:59.542985 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8554 19:22:59.546156 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8555 19:22:59.549510 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8556 19:22:59.555855 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8557 19:22:59.559235 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8558 19:22:59.562819 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8559 19:22:59.566016 iDelay=200, Bit 10, Center 127 (64 ~ 191) 128
8560 19:22:59.572383 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8561 19:22:59.575856 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8562 19:22:59.579027 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8563 19:22:59.582588 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8564 19:22:59.585800 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8565 19:22:59.588782 ==
8566 19:22:59.592300 Dram Type= 6, Freq= 0, CH_1, rank 1
8567 19:22:59.595452 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8568 19:22:59.595759 ==
8569 19:22:59.595999 DQS Delay:
8570 19:22:59.598751 DQS0 = 0, DQS1 = 0
8571 19:22:59.599052 DQM Delay:
8572 19:22:59.601948 DQM0 = 130, DQM1 = 125
8573 19:22:59.602266 DQ Delay:
8574 19:22:59.605730 DQ0 =131, DQ1 =123, DQ2 =119, DQ3 =127
8575 19:22:59.608521 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8576 19:22:59.611815 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115
8577 19:22:59.615445 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =131
8578 19:22:59.615748
8579 19:22:59.615989
8580 19:22:59.616212 ==
8581 19:22:59.618712 Dram Type= 6, Freq= 0, CH_1, rank 1
8582 19:22:59.624970 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8583 19:22:59.625275 ==
8584 19:22:59.625516
8585 19:22:59.625741
8586 19:22:59.628197 TX Vref Scan disable
8587 19:22:59.628499 == TX Byte 0 ==
8588 19:22:59.631534 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8589 19:22:59.638637 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8590 19:22:59.638940 == TX Byte 1 ==
8591 19:22:59.641709 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8592 19:22:59.648253 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8593 19:22:59.648646 ==
8594 19:22:59.651757 Dram Type= 6, Freq= 0, CH_1, rank 1
8595 19:22:59.655322 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8596 19:22:59.655724 ==
8597 19:22:59.669043
8598 19:22:59.671899 TX Vref early break, caculate TX vref
8599 19:22:59.675338 TX Vref=16, minBit 0, minWin=22, winSum=376
8600 19:22:59.678699 TX Vref=18, minBit 6, minWin=22, winSum=385
8601 19:22:59.682195 TX Vref=20, minBit 5, minWin=23, winSum=395
8602 19:22:59.685395 TX Vref=22, minBit 2, minWin=24, winSum=406
8603 19:22:59.688738 TX Vref=24, minBit 5, minWin=24, winSum=408
8604 19:22:59.695316 TX Vref=26, minBit 0, minWin=25, winSum=417
8605 19:22:59.698237 TX Vref=28, minBit 4, minWin=25, winSum=418
8606 19:22:59.702195 TX Vref=30, minBit 0, minWin=24, winSum=413
8607 19:22:59.705449 TX Vref=32, minBit 0, minWin=23, winSum=407
8608 19:22:59.708056 TX Vref=34, minBit 0, minWin=23, winSum=401
8609 19:22:59.711832 TX Vref=36, minBit 0, minWin=23, winSum=391
8610 19:22:59.718319 [TxChooseVref] Worse bit 4, Min win 25, Win sum 418, Final Vref 28
8611 19:22:59.718897
8612 19:22:59.721392 Final TX Range 0 Vref 28
8613 19:22:59.721854
8614 19:22:59.722283 ==
8615 19:22:59.724776 Dram Type= 6, Freq= 0, CH_1, rank 1
8616 19:22:59.728436 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8617 19:22:59.729000 ==
8618 19:22:59.731504
8619 19:22:59.731988
8620 19:22:59.732357 TX Vref Scan disable
8621 19:22:59.737919 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8622 19:22:59.738534 == TX Byte 0 ==
8623 19:22:59.741218 u2DelayCellOfst[0]=18 cells (5 PI)
8624 19:22:59.744930 u2DelayCellOfst[1]=10 cells (3 PI)
8625 19:22:59.747905 u2DelayCellOfst[2]=0 cells (0 PI)
8626 19:22:59.751065 u2DelayCellOfst[3]=7 cells (2 PI)
8627 19:22:59.754455 u2DelayCellOfst[4]=10 cells (3 PI)
8628 19:22:59.757757 u2DelayCellOfst[5]=18 cells (5 PI)
8629 19:22:59.761506 u2DelayCellOfst[6]=18 cells (5 PI)
8630 19:22:59.764297 u2DelayCellOfst[7]=7 cells (2 PI)
8631 19:22:59.767849 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8632 19:22:59.770873 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8633 19:22:59.774459 == TX Byte 1 ==
8634 19:22:59.777600 u2DelayCellOfst[8]=0 cells (0 PI)
8635 19:22:59.781091 u2DelayCellOfst[9]=3 cells (1 PI)
8636 19:22:59.784353 u2DelayCellOfst[10]=10 cells (3 PI)
8637 19:22:59.787173 u2DelayCellOfst[11]=0 cells (0 PI)
8638 19:22:59.790428 u2DelayCellOfst[12]=14 cells (4 PI)
8639 19:22:59.794192 u2DelayCellOfst[13]=18 cells (5 PI)
8640 19:22:59.797268 u2DelayCellOfst[14]=18 cells (5 PI)
8641 19:22:59.797839 u2DelayCellOfst[15]=18 cells (5 PI)
8642 19:22:59.804134 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8643 19:22:59.807281 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8644 19:22:59.810254 DramC Write-DBI on
8645 19:22:59.810714 ==
8646 19:22:59.813786 Dram Type= 6, Freq= 0, CH_1, rank 1
8647 19:22:59.817594 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8648 19:22:59.818208 ==
8649 19:22:59.818633
8650 19:22:59.818993
8651 19:22:59.820196 TX Vref Scan disable
8652 19:22:59.820630 == TX Byte 0 ==
8653 19:22:59.827553 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
8654 19:22:59.828307 == TX Byte 1 ==
8655 19:22:59.830140 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8656 19:22:59.833649 DramC Write-DBI off
8657 19:22:59.834253
8658 19:22:59.834637 [DATLAT]
8659 19:22:59.836764 Freq=1600, CH1 RK1
8660 19:22:59.837325
8661 19:22:59.837700 DATLAT Default: 0xe
8662 19:22:59.840206 0, 0xFFFF, sum = 0
8663 19:22:59.840680 1, 0xFFFF, sum = 0
8664 19:22:59.843459 2, 0xFFFF, sum = 0
8665 19:22:59.846841 3, 0xFFFF, sum = 0
8666 19:22:59.847706 4, 0xFFFF, sum = 0
8667 19:22:59.849759 5, 0xFFFF, sum = 0
8668 19:22:59.850288 6, 0xFFFF, sum = 0
8669 19:22:59.853270 7, 0xFFFF, sum = 0
8670 19:22:59.853839 8, 0xFFFF, sum = 0
8671 19:22:59.856835 9, 0xFFFF, sum = 0
8672 19:22:59.857412 10, 0xFFFF, sum = 0
8673 19:22:59.860068 11, 0xFFFF, sum = 0
8674 19:22:59.860635 12, 0xF7F, sum = 0
8675 19:22:59.863283 13, 0x0, sum = 1
8676 19:22:59.863801 14, 0x0, sum = 2
8677 19:22:59.866577 15, 0x0, sum = 3
8678 19:22:59.867046 16, 0x0, sum = 4
8679 19:22:59.869873 best_step = 14
8680 19:22:59.870392
8681 19:22:59.870765 ==
8682 19:22:59.872877 Dram Type= 6, Freq= 0, CH_1, rank 1
8683 19:22:59.876623 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8684 19:22:59.877185 ==
8685 19:22:59.879703 RX Vref Scan: 0
8686 19:22:59.880263
8687 19:22:59.880635 RX Vref 0 -> 0, step: 1
8688 19:22:59.880984
8689 19:22:59.882974 RX Delay 3 -> 252, step: 4
8690 19:22:59.886636 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8691 19:22:59.893001 iDelay=195, Bit 1, Center 122 (67 ~ 178) 112
8692 19:22:59.896249 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8693 19:22:59.899586 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8694 19:22:59.902650 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8695 19:22:59.905860 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8696 19:22:59.912996 iDelay=195, Bit 6, Center 134 (79 ~ 190) 112
8697 19:22:59.915760 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8698 19:22:59.919402 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
8699 19:22:59.922927 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8700 19:22:59.926121 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8701 19:22:59.932594 iDelay=195, Bit 11, Center 112 (55 ~ 170) 116
8702 19:22:59.936110 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116
8703 19:22:59.939266 iDelay=195, Bit 13, Center 134 (83 ~ 186) 104
8704 19:22:59.942350 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
8705 19:22:59.948885 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8706 19:22:59.949433 ==
8707 19:22:59.952219 Dram Type= 6, Freq= 0, CH_1, rank 1
8708 19:22:59.955418 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8709 19:22:59.955882 ==
8710 19:22:59.956253 DQS Delay:
8711 19:22:59.959171 DQS0 = 0, DQS1 = 0
8712 19:22:59.959727 DQM Delay:
8713 19:22:59.962090 DQM0 = 126, DQM1 = 123
8714 19:22:59.962553 DQ Delay:
8715 19:22:59.965512 DQ0 =128, DQ1 =122, DQ2 =116, DQ3 =124
8716 19:22:59.969074 DQ4 =126, DQ5 =138, DQ6 =134, DQ7 =126
8717 19:22:59.972470 DQ8 =106, DQ9 =110, DQ10 =124, DQ11 =112
8718 19:22:59.975894 DQ12 =132, DQ13 =134, DQ14 =134, DQ15 =132
8719 19:22:59.976519
8720 19:22:59.979235
8721 19:22:59.979795
8722 19:22:59.980164 [DramC_TX_OE_Calibration] TA2
8723 19:22:59.982141 Original DQ_B0 (3 6) =30, OEN = 27
8724 19:22:59.985904 Original DQ_B1 (3 6) =30, OEN = 27
8725 19:22:59.989029 24, 0x0, End_B0=24 End_B1=24
8726 19:22:59.992138 25, 0x0, End_B0=25 End_B1=25
8727 19:22:59.995591 26, 0x0, End_B0=26 End_B1=26
8728 19:22:59.996247 27, 0x0, End_B0=27 End_B1=27
8729 19:22:59.998569 28, 0x0, End_B0=28 End_B1=28
8730 19:23:00.001968 29, 0x0, End_B0=29 End_B1=29
8731 19:23:00.005155 30, 0x0, End_B0=30 End_B1=30
8732 19:23:00.009017 31, 0x4545, End_B0=30 End_B1=30
8733 19:23:00.009614 Byte0 end_step=30 best_step=27
8734 19:23:00.011885 Byte1 end_step=30 best_step=27
8735 19:23:00.015507 Byte0 TX OE(2T, 0.5T) = (3, 3)
8736 19:23:00.018929 Byte1 TX OE(2T, 0.5T) = (3, 3)
8737 19:23:00.019518
8738 19:23:00.019893
8739 19:23:00.028230 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d1d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
8740 19:23:00.028701 CH1 RK1: MR19=303, MR18=1D1D
8741 19:23:00.035123 CH1_RK1: MR19=0x303, MR18=0x1D1D, DQSOSC=395, MR23=63, INC=23, DEC=15
8742 19:23:00.038501 [RxdqsGatingPostProcess] freq 1600
8743 19:23:00.045120 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8744 19:23:00.047994 Pre-setting of DQS Precalculation
8745 19:23:00.051421 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8746 19:23:00.058433 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8747 19:23:00.068227 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8748 19:23:00.068793
8749 19:23:00.069165
8750 19:23:00.071443 [Calibration Summary] 3200 Mbps
8751 19:23:00.071964 CH 0, Rank 0
8752 19:23:00.074706 SW Impedance : PASS
8753 19:23:00.075268 DUTY Scan : NO K
8754 19:23:00.077922 ZQ Calibration : PASS
8755 19:23:00.078429 Jitter Meter : NO K
8756 19:23:00.081315 CBT Training : PASS
8757 19:23:00.084591 Write leveling : PASS
8758 19:23:00.085159 RX DQS gating : PASS
8759 19:23:00.087859 RX DQ/DQS(RDDQC) : PASS
8760 19:23:00.091248 TX DQ/DQS : PASS
8761 19:23:00.091726 RX DATLAT : PASS
8762 19:23:00.094755 RX DQ/DQS(Engine): PASS
8763 19:23:00.097846 TX OE : PASS
8764 19:23:00.098450 All Pass.
8765 19:23:00.098823
8766 19:23:00.099170 CH 0, Rank 1
8767 19:23:00.101050 SW Impedance : PASS
8768 19:23:00.104603 DUTY Scan : NO K
8769 19:23:00.105066 ZQ Calibration : PASS
8770 19:23:00.108219 Jitter Meter : NO K
8771 19:23:00.111495 CBT Training : PASS
8772 19:23:00.112054 Write leveling : PASS
8773 19:23:00.114790 RX DQS gating : PASS
8774 19:23:00.117935 RX DQ/DQS(RDDQC) : PASS
8775 19:23:00.118541 TX DQ/DQS : PASS
8776 19:23:00.121220 RX DATLAT : PASS
8777 19:23:00.124199 RX DQ/DQS(Engine): PASS
8778 19:23:00.124666 TX OE : PASS
8779 19:23:00.127238 All Pass.
8780 19:23:00.127700
8781 19:23:00.128073 CH 1, Rank 0
8782 19:23:00.130665 SW Impedance : PASS
8783 19:23:00.131128 DUTY Scan : NO K
8784 19:23:00.134162 ZQ Calibration : PASS
8785 19:23:00.137427 Jitter Meter : NO K
8786 19:23:00.137988 CBT Training : PASS
8787 19:23:00.140961 Write leveling : PASS
8788 19:23:00.144040 RX DQS gating : PASS
8789 19:23:00.144602 RX DQ/DQS(RDDQC) : PASS
8790 19:23:00.147357 TX DQ/DQS : PASS
8791 19:23:00.150681 RX DATLAT : PASS
8792 19:23:00.151143 RX DQ/DQS(Engine): PASS
8793 19:23:00.153658 TX OE : PASS
8794 19:23:00.154161 All Pass.
8795 19:23:00.154539
8796 19:23:00.157008 CH 1, Rank 1
8797 19:23:00.157472 SW Impedance : PASS
8798 19:23:00.160908 DUTY Scan : NO K
8799 19:23:00.161475 ZQ Calibration : PASS
8800 19:23:00.163900 Jitter Meter : NO K
8801 19:23:00.167350 CBT Training : PASS
8802 19:23:00.167812 Write leveling : PASS
8803 19:23:00.170146 RX DQS gating : PASS
8804 19:23:00.173455 RX DQ/DQS(RDDQC) : PASS
8805 19:23:00.173918 TX DQ/DQS : PASS
8806 19:23:00.177013 RX DATLAT : PASS
8807 19:23:00.180489 RX DQ/DQS(Engine): PASS
8808 19:23:00.181050 TX OE : PASS
8809 19:23:00.183386 All Pass.
8810 19:23:00.183850
8811 19:23:00.184223 DramC Write-DBI on
8812 19:23:00.186593 PER_BANK_REFRESH: Hybrid Mode
8813 19:23:00.190184 TX_TRACKING: ON
8814 19:23:00.196329 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8815 19:23:00.206731 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8816 19:23:00.213833 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8817 19:23:00.216859 [FAST_K] Save calibration result to emmc
8818 19:23:00.219673 sync common calibartion params.
8819 19:23:00.220137 sync cbt_mode0:0, 1:0
8820 19:23:00.223355 dram_init: ddr_geometry: 0
8821 19:23:00.227373 dram_init: ddr_geometry: 0
8822 19:23:00.229656 dram_init: ddr_geometry: 0
8823 19:23:00.230254 0:dram_rank_size:80000000
8824 19:23:00.233081 1:dram_rank_size:80000000
8825 19:23:00.239883 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8826 19:23:00.240446 DFS_SHUFFLE_HW_MODE: ON
8827 19:23:00.243175 dramc_set_vcore_voltage set vcore to 725000
8828 19:23:00.246228 Read voltage for 1600, 0
8829 19:23:00.246786 Vio18 = 0
8830 19:23:00.249604 Vcore = 725000
8831 19:23:00.250296 Vdram = 0
8832 19:23:00.250680 Vddq = 0
8833 19:23:00.252782 Vmddr = 0
8834 19:23:00.253246 switch to 3200 Mbps bootup
8835 19:23:00.255864 [DramcRunTimeConfig]
8836 19:23:00.256420 PHYPLL
8837 19:23:00.259247 DPM_CONTROL_AFTERK: ON
8838 19:23:00.259824 PER_BANK_REFRESH: ON
8839 19:23:00.262439 REFRESH_OVERHEAD_REDUCTION: ON
8840 19:23:00.266370 CMD_PICG_NEW_MODE: OFF
8841 19:23:00.266985 XRTWTW_NEW_MODE: ON
8842 19:23:00.269703 XRTRTR_NEW_MODE: ON
8843 19:23:00.270320 TX_TRACKING: ON
8844 19:23:00.272787 RDSEL_TRACKING: OFF
8845 19:23:00.275711 DQS Precalculation for DVFS: ON
8846 19:23:00.276180 RX_TRACKING: OFF
8847 19:23:00.279451 HW_GATING DBG: ON
8848 19:23:00.280021 ZQCS_ENABLE_LP4: ON
8849 19:23:00.282283 RX_PICG_NEW_MODE: ON
8850 19:23:00.282746 TX_PICG_NEW_MODE: ON
8851 19:23:00.285580 ENABLE_RX_DCM_DPHY: ON
8852 19:23:00.289586 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8853 19:23:00.292560 DUMMY_READ_FOR_TRACKING: OFF
8854 19:23:00.295674 !!! SPM_CONTROL_AFTERK: OFF
8855 19:23:00.296179 !!! SPM could not control APHY
8856 19:23:00.298847 IMPEDANCE_TRACKING: ON
8857 19:23:00.299265 TEMP_SENSOR: ON
8858 19:23:00.302388 HW_SAVE_FOR_SR: OFF
8859 19:23:00.305815 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8860 19:23:00.309139 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8861 19:23:00.312308 Read ODT Tracking: ON
8862 19:23:00.312871 Refresh Rate DeBounce: ON
8863 19:23:00.315807 DFS_NO_QUEUE_FLUSH: ON
8864 19:23:00.318978 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8865 19:23:00.322174 ENABLE_DFS_RUNTIME_MRW: OFF
8866 19:23:00.322736 DDR_RESERVE_NEW_MODE: ON
8867 19:23:00.325424 MR_CBT_SWITCH_FREQ: ON
8868 19:23:00.328464 =========================
8869 19:23:00.346516 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8870 19:23:00.349295 dram_init: ddr_geometry: 0
8871 19:23:00.367634 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8872 19:23:00.370775 dram_init: dram init end (result: 0)
8873 19:23:00.377862 DRAM-K: Full calibration passed in 23440 msecs
8874 19:23:00.380732 MRC: failed to locate region type 0.
8875 19:23:00.381204 DRAM rank0 size:0x80000000,
8876 19:23:00.384162 DRAM rank1 size=0x80000000
8877 19:23:00.394550 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8878 19:23:00.400765 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8879 19:23:00.407461 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8880 19:23:00.414661 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8881 19:23:00.417607 DRAM rank0 size:0x80000000,
8882 19:23:00.420629 DRAM rank1 size=0x80000000
8883 19:23:00.421095 CBMEM:
8884 19:23:00.423938 IMD: root @ 0xfffff000 254 entries.
8885 19:23:00.427463 IMD: root @ 0xffffec00 62 entries.
8886 19:23:00.430886 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8887 19:23:00.434529 WARNING: RO_VPD is uninitialized or empty.
8888 19:23:00.440742 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8889 19:23:00.447382 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8890 19:23:00.460480 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
8891 19:23:00.471840 BS: romstage times (exec / console): total (unknown) / 22978 ms
8892 19:23:00.472408
8893 19:23:00.472779
8894 19:23:00.481471 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8895 19:23:00.484921 ARM64: Exception handlers installed.
8896 19:23:00.487802 ARM64: Testing exception
8897 19:23:00.491316 ARM64: Done test exception
8898 19:23:00.491784 Enumerating buses...
8899 19:23:00.494530 Show all devs... Before device enumeration.
8900 19:23:00.497765 Root Device: enabled 1
8901 19:23:00.501285 CPU_CLUSTER: 0: enabled 1
8902 19:23:00.501857 CPU: 00: enabled 1
8903 19:23:00.504603 Compare with tree...
8904 19:23:00.505068 Root Device: enabled 1
8905 19:23:00.508154 CPU_CLUSTER: 0: enabled 1
8906 19:23:00.510973 CPU: 00: enabled 1
8907 19:23:00.511435 Root Device scanning...
8908 19:23:00.514531 scan_static_bus for Root Device
8909 19:23:00.518319 CPU_CLUSTER: 0 enabled
8910 19:23:00.521286 scan_static_bus for Root Device done
8911 19:23:00.524515 scan_bus: bus Root Device finished in 8 msecs
8912 19:23:00.525040 done
8913 19:23:00.531352 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8914 19:23:00.534564 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8915 19:23:00.541317 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8916 19:23:00.544471 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8917 19:23:00.547539 Allocating resources...
8918 19:23:00.551099 Reading resources...
8919 19:23:00.554248 Root Device read_resources bus 0 link: 0
8920 19:23:00.554722 DRAM rank0 size:0x80000000,
8921 19:23:00.557841 DRAM rank1 size=0x80000000
8922 19:23:00.560944 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8923 19:23:00.563907 CPU: 00 missing read_resources
8924 19:23:00.570829 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8925 19:23:00.573656 Root Device read_resources bus 0 link: 0 done
8926 19:23:00.574161 Done reading resources.
8927 19:23:00.580771 Show resources in subtree (Root Device)...After reading.
8928 19:23:00.584104 Root Device child on link 0 CPU_CLUSTER: 0
8929 19:23:00.587259 CPU_CLUSTER: 0 child on link 0 CPU: 00
8930 19:23:00.597147 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8931 19:23:00.597703 CPU: 00
8932 19:23:00.600388 Root Device assign_resources, bus 0 link: 0
8933 19:23:00.603485 CPU_CLUSTER: 0 missing set_resources
8934 19:23:00.610297 Root Device assign_resources, bus 0 link: 0 done
8935 19:23:00.610846 Done setting resources.
8936 19:23:00.617325 Show resources in subtree (Root Device)...After assigning values.
8937 19:23:00.620494 Root Device child on link 0 CPU_CLUSTER: 0
8938 19:23:00.623614 CPU_CLUSTER: 0 child on link 0 CPU: 00
8939 19:23:00.633713 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8940 19:23:00.634329 CPU: 00
8941 19:23:00.636997 Done allocating resources.
8942 19:23:00.643382 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
8943 19:23:00.643949 Enabling resources...
8944 19:23:00.644322 done.
8945 19:23:00.650324 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
8946 19:23:00.650889 Initializing devices...
8947 19:23:00.653479 Root Device init
8948 19:23:00.656790 init hardware done!
8949 19:23:00.657354 0x00000018: ctrlr->caps
8950 19:23:00.660213 52.000 MHz: ctrlr->f_max
8951 19:23:00.663092 0.400 MHz: ctrlr->f_min
8952 19:23:00.663666 0x40ff8080: ctrlr->voltages
8953 19:23:00.666490 sclk: 390625
8954 19:23:00.666952 Bus Width = 1
8955 19:23:00.667320 sclk: 390625
8956 19:23:00.670464 Bus Width = 1
8957 19:23:00.671021 Early init status = 3
8958 19:23:00.676551 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
8959 19:23:00.680067 in-header: 03 fc 00 00 01 00 00 00
8960 19:23:00.683135 in-data: 00
8961 19:23:00.686413 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
8962 19:23:00.692635 in-header: 03 fd 00 00 00 00 00 00
8963 19:23:00.695384 in-data:
8964 19:23:00.698756 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
8965 19:23:00.703131 in-header: 03 fc 00 00 01 00 00 00
8966 19:23:00.706456 in-data: 00
8967 19:23:00.709608 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
8968 19:23:00.715746 in-header: 03 fd 00 00 00 00 00 00
8969 19:23:00.718542 in-data:
8970 19:23:00.722106 [SSUSB] Setting up USB HOST controller...
8971 19:23:00.725308 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
8972 19:23:00.729061 [SSUSB] phy power-on done.
8973 19:23:00.732710 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
8974 19:23:00.738924 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
8975 19:23:00.742084 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
8976 19:23:00.748830 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
8977 19:23:00.755164 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
8978 19:23:00.762067 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
8979 19:23:00.768603 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
8980 19:23:00.775302 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
8981 19:23:00.778628 SPM: binary array size = 0x9dc
8982 19:23:00.782182 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
8983 19:23:00.788659 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
8984 19:23:00.794970 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
8985 19:23:00.798843 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
8986 19:23:00.805263 configure_display: Starting display init
8987 19:23:00.839325 anx7625_power_on_init: Init interface.
8988 19:23:00.841918 anx7625_disable_pd_protocol: Disabled PD feature.
8989 19:23:00.845539 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
8990 19:23:00.872843 anx7625_start_dp_work: Secure OCM version=00
8991 19:23:00.876441 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
8992 19:23:00.891961 sp_tx_get_edid_block: EDID Block = 1
8993 19:23:00.993898 Extracted contents:
8994 19:23:00.997365 header: 00 ff ff ff ff ff ff 00
8995 19:23:01.000290 serial number: 26 cf 7d 05 00 00 00 00 00 1e
8996 19:23:01.003627 version: 01 04
8997 19:23:01.006944 basic params: 95 1f 11 78 0a
8998 19:23:01.010340 chroma info: 76 90 94 55 54 90 27 21 50 54
8999 19:23:01.013463 established: 00 00 00
9000 19:23:01.020194 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9001 19:23:01.026584 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9002 19:23:01.030080 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9003 19:23:01.036670 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9004 19:23:01.043100 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9005 19:23:01.046743 extensions: 00
9006 19:23:01.047310 checksum: fb
9007 19:23:01.047683
9008 19:23:01.053211 Manufacturer: IVO Model 57d Serial Number 0
9009 19:23:01.053887 Made week 0 of 2020
9010 19:23:01.056319 EDID version: 1.4
9011 19:23:01.056783 Digital display
9012 19:23:01.059738 6 bits per primary color channel
9013 19:23:01.060308 DisplayPort interface
9014 19:23:01.063170 Maximum image size: 31 cm x 17 cm
9015 19:23:01.066367 Gamma: 220%
9016 19:23:01.066926 Check DPMS levels
9017 19:23:01.069588 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9018 19:23:01.076480 First detailed timing is preferred timing
9019 19:23:01.077044 Established timings supported:
9020 19:23:01.079964 Standard timings supported:
9021 19:23:01.082827 Detailed timings
9022 19:23:01.086253 Hex of detail: 383680a07038204018303c0035ae10000019
9023 19:23:01.092722 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9024 19:23:01.096167 0780 0798 07c8 0820 hborder 0
9025 19:23:01.099539 0438 043b 0447 0458 vborder 0
9026 19:23:01.102910 -hsync -vsync
9027 19:23:01.103465 Did detailed timing
9028 19:23:01.109414 Hex of detail: 000000000000000000000000000000000000
9029 19:23:01.112349 Manufacturer-specified data, tag 0
9030 19:23:01.115782 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9031 19:23:01.119415 ASCII string: InfoVision
9032 19:23:01.122807 Hex of detail: 000000fe00523134304e574635205248200a
9033 19:23:01.126122 ASCII string: R140NWF5 RH
9034 19:23:01.126677 Checksum
9035 19:23:01.129200 Checksum: 0xfb (valid)
9036 19:23:01.132500 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9037 19:23:01.136284 DSI data_rate: 832800000 bps
9038 19:23:01.142547 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9039 19:23:01.145912 anx7625_parse_edid: pixelclock(138800).
9040 19:23:01.149355 hactive(1920), hsync(48), hfp(24), hbp(88)
9041 19:23:01.152959 vactive(1080), vsync(12), vfp(3), vbp(17)
9042 19:23:01.155817 anx7625_dsi_config: config dsi.
9043 19:23:01.162371 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9044 19:23:01.176159 anx7625_dsi_config: success to config DSI
9045 19:23:01.179130 anx7625_dp_start: MIPI phy setup OK.
9046 19:23:01.182465 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9047 19:23:01.185777 mtk_ddp_mode_set invalid vrefresh 60
9048 19:23:01.189318 main_disp_path_setup
9049 19:23:01.189877 ovl_layer_smi_id_en
9050 19:23:01.192486 ovl_layer_smi_id_en
9051 19:23:01.193065 ccorr_config
9052 19:23:01.193464 aal_config
9053 19:23:01.195670 gamma_config
9054 19:23:01.196129 postmask_config
9055 19:23:01.198678 dither_config
9056 19:23:01.202326 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9057 19:23:01.209172 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9058 19:23:01.212142 Root Device init finished in 555 msecs
9059 19:23:01.215200 CPU_CLUSTER: 0 init
9060 19:23:01.222169 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9061 19:23:01.228778 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9062 19:23:01.229341 APU_MBOX 0x190000b0 = 0x10001
9063 19:23:01.231867 APU_MBOX 0x190001b0 = 0x10001
9064 19:23:01.235951 APU_MBOX 0x190005b0 = 0x10001
9065 19:23:01.238990 APU_MBOX 0x190006b0 = 0x10001
9066 19:23:01.245041 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9067 19:23:01.254958 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9068 19:23:01.267108 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9069 19:23:01.273889 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9070 19:23:01.285427 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9071 19:23:01.294968 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9072 19:23:01.297974 CPU_CLUSTER: 0 init finished in 81 msecs
9073 19:23:01.301051 Devices initialized
9074 19:23:01.304854 Show all devs... After init.
9075 19:23:01.305418 Root Device: enabled 1
9076 19:23:01.307738 CPU_CLUSTER: 0: enabled 1
9077 19:23:01.311027 CPU: 00: enabled 1
9078 19:23:01.314250 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9079 19:23:01.317759 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9080 19:23:01.320639 ELOG: NV offset 0x57f000 size 0x1000
9081 19:23:01.327859 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9082 19:23:01.334339 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9083 19:23:01.337990 ELOG: Event(17) added with size 13 at 2024-04-18 19:23:00 UTC
9084 19:23:01.344541 out: cmd=0x121: 03 db 21 01 00 00 00 00
9085 19:23:01.347750 in-header: 03 d9 00 00 2c 00 00 00
9086 19:23:01.357546 in-data: 89 65 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9087 19:23:01.364261 ELOG: Event(A1) added with size 10 at 2024-04-18 19:23:00 UTC
9088 19:23:01.370554 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9089 19:23:01.377356 ELOG: Event(A0) added with size 9 at 2024-04-18 19:23:00 UTC
9090 19:23:01.381150 elog_add_boot_reason: Logged dev mode boot
9091 19:23:01.387156 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9092 19:23:01.387680 Finalize devices...
9093 19:23:01.390371 Devices finalized
9094 19:23:01.393966 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9095 19:23:01.397298 Writing coreboot table at 0xffe64000
9096 19:23:01.400435 0. 000000000010a000-0000000000113fff: RAMSTAGE
9097 19:23:01.404041 1. 0000000040000000-00000000400fffff: RAM
9098 19:23:01.410522 2. 0000000040100000-000000004032afff: RAMSTAGE
9099 19:23:01.414165 3. 000000004032b000-00000000545fffff: RAM
9100 19:23:01.417535 4. 0000000054600000-000000005465ffff: BL31
9101 19:23:01.420691 5. 0000000054660000-00000000ffe63fff: RAM
9102 19:23:01.426732 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9103 19:23:01.430247 7. 0000000100000000-000000013fffffff: RAM
9104 19:23:01.433685 Passing 5 GPIOs to payload:
9105 19:23:01.437107 NAME | PORT | POLARITY | VALUE
9106 19:23:01.440425 EC in RW | 0x000000aa | low | undefined
9107 19:23:01.446999 EC interrupt | 0x00000005 | low | undefined
9108 19:23:01.450187 TPM interrupt | 0x000000ab | high | undefined
9109 19:23:01.456874 SD card detect | 0x00000011 | high | undefined
9110 19:23:01.460383 speaker enable | 0x00000093 | high | undefined
9111 19:23:01.463593 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9112 19:23:01.466700 in-header: 03 f8 00 00 02 00 00 00
9113 19:23:01.469807 in-data: 03 00
9114 19:23:01.470374 ADC[4]: Raw value=668590 ID=5
9115 19:23:01.473526 ADC[3]: Raw value=212549 ID=1
9116 19:23:01.476735 RAM Code: 0x51
9117 19:23:01.480326 ADC[6]: Raw value=74410 ID=0
9118 19:23:01.480891 ADC[5]: Raw value=211812 ID=1
9119 19:23:01.483381 SKU Code: 0x1
9120 19:23:01.486784 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 336d
9121 19:23:01.489667 coreboot table: 964 bytes.
9122 19:23:01.493116 IMD ROOT 0. 0xfffff000 0x00001000
9123 19:23:01.496765 IMD SMALL 1. 0xffffe000 0x00001000
9124 19:23:01.499960 RO MCACHE 2. 0xffffc000 0x00001104
9125 19:23:01.502868 CONSOLE 3. 0xfff7c000 0x00080000
9126 19:23:01.506273 FMAP 4. 0xfff7b000 0x00000452
9127 19:23:01.509869 TIME STAMP 5. 0xfff7a000 0x00000910
9128 19:23:01.513216 VBOOT WORK 6. 0xfff66000 0x00014000
9129 19:23:01.516348 RAMOOPS 7. 0xffe66000 0x00100000
9130 19:23:01.519660 COREBOOT 8. 0xffe64000 0x00002000
9131 19:23:01.522831 IMD small region:
9132 19:23:01.526182 IMD ROOT 0. 0xffffec00 0x00000400
9133 19:23:01.529714 VPD 1. 0xffffeb80 0x0000006c
9134 19:23:01.532668 MMC STATUS 2. 0xffffeb60 0x00000004
9135 19:23:01.535724 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9136 19:23:01.539352 Probing TPM: done!
9137 19:23:01.542870 Connected to device vid:did:rid of 1ae0:0028:00
9138 19:23:01.553790 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
9139 19:23:01.556840 Initialized TPM device CR50 revision 0
9140 19:23:01.559913 Checking cr50 for pending updates
9141 19:23:01.564516 Reading cr50 TPM mode
9142 19:23:01.572582 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9143 19:23:01.579263 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9144 19:23:01.619373 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9145 19:23:01.623007 Checking segment from ROM address 0x40100000
9146 19:23:01.626149 Checking segment from ROM address 0x4010001c
9147 19:23:01.632919 Loading segment from ROM address 0x40100000
9148 19:23:01.633449 code (compression=0)
9149 19:23:01.643171 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9150 19:23:01.649406 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9151 19:23:01.649964 it's not compressed!
9152 19:23:01.655819 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9153 19:23:01.662518 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9154 19:23:01.679914 Loading segment from ROM address 0x4010001c
9155 19:23:01.680446 Entry Point 0x80000000
9156 19:23:01.682939 Loaded segments
9157 19:23:01.686757 BS: BS_PAYLOAD_LOAD run times (exec / console): 49 / 61 ms
9158 19:23:01.693372 Jumping to boot code at 0x80000000(0xffe64000)
9159 19:23:01.699923 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9160 19:23:01.706494 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9161 19:23:01.714381 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9162 19:23:01.717599 Checking segment from ROM address 0x40100000
9163 19:23:01.720824 Checking segment from ROM address 0x4010001c
9164 19:23:01.727412 Loading segment from ROM address 0x40100000
9165 19:23:01.727909 code (compression=1)
9166 19:23:01.734292 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9167 19:23:01.744178 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9168 19:23:01.744806 using LZMA
9169 19:23:01.752719 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9170 19:23:01.759621 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9171 19:23:01.762647 Loading segment from ROM address 0x4010001c
9172 19:23:01.763115 Entry Point 0x54601000
9173 19:23:01.765853 Loaded segments
9174 19:23:01.769092 NOTICE: MT8192 bl31_setup
9175 19:23:01.776425 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9176 19:23:01.779646 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9177 19:23:01.782920 WARNING: region 0:
9178 19:23:01.786386 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9179 19:23:01.786856 WARNING: region 1:
9180 19:23:01.792918 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9181 19:23:01.796197 WARNING: region 2:
9182 19:23:01.799192 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9183 19:23:01.802790 WARNING: region 3:
9184 19:23:01.806325 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9185 19:23:01.809444 WARNING: region 4:
9186 19:23:01.816575 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9187 19:23:01.817283 WARNING: region 5:
9188 19:23:01.819431 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9189 19:23:01.822604 WARNING: region 6:
9190 19:23:01.826273 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9191 19:23:01.829923 WARNING: region 7:
9192 19:23:01.833081 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9193 19:23:01.839420 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9194 19:23:01.842805 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9195 19:23:01.846439 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9196 19:23:01.852732 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9197 19:23:01.856355 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9198 19:23:01.859541 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9199 19:23:01.866611 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9200 19:23:01.869517 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9201 19:23:01.876665 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9202 19:23:01.879585 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9203 19:23:01.883367 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9204 19:23:01.889525 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9205 19:23:01.893048 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9206 19:23:01.896284 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9207 19:23:01.902903 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9208 19:23:01.906194 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9209 19:23:01.909878 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9210 19:23:01.916255 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9211 19:23:01.919843 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9212 19:23:01.926068 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9213 19:23:01.929395 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9214 19:23:01.933456 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9215 19:23:01.939627 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9216 19:23:01.943184 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9217 19:23:01.950094 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9218 19:23:01.952866 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9219 19:23:01.956283 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9220 19:23:01.962832 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9221 19:23:01.966622 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9222 19:23:01.969598 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9223 19:23:01.976209 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9224 19:23:01.979848 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9225 19:23:01.983080 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9226 19:23:01.989757 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9227 19:23:01.993008 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9228 19:23:01.996397 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9229 19:23:01.999718 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9230 19:23:02.006705 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9231 19:23:02.009984 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9232 19:23:02.013328 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9233 19:23:02.016435 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9234 19:23:02.023125 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9235 19:23:02.026502 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9236 19:23:02.029851 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9237 19:23:02.033143 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9238 19:23:02.039755 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9239 19:23:02.043057 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9240 19:23:02.046311 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9241 19:23:02.053181 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9242 19:23:02.056731 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9243 19:23:02.063115 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9244 19:23:02.066514 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9245 19:23:02.069615 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9246 19:23:02.076582 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9247 19:23:02.079919 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9248 19:23:02.086647 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9249 19:23:02.089852 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9250 19:23:02.092894 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9251 19:23:02.099856 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9252 19:23:02.103505 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9253 19:23:02.109865 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9254 19:23:02.112899 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9255 19:23:02.119673 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9256 19:23:02.122892 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9257 19:23:02.130267 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9258 19:23:02.133429 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9259 19:23:02.136314 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9260 19:23:02.143260 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9261 19:23:02.146541 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9262 19:23:02.153521 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9263 19:23:02.156162 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9264 19:23:02.163245 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9265 19:23:02.166391 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9266 19:23:02.169600 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9267 19:23:02.176013 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9268 19:23:02.179925 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9269 19:23:02.186234 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9270 19:23:02.189889 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9271 19:23:02.196392 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9272 19:23:02.199447 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9273 19:23:02.206558 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9274 19:23:02.209356 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9275 19:23:02.212988 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9276 19:23:02.219631 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9277 19:23:02.222971 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9278 19:23:02.229239 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9279 19:23:02.232893 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9280 19:23:02.235982 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9281 19:23:02.242945 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9282 19:23:02.246791 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9283 19:23:02.253410 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9284 19:23:02.256695 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9285 19:23:02.263312 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9286 19:23:02.266748 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9287 19:23:02.273056 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9288 19:23:02.276587 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9289 19:23:02.279827 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9290 19:23:02.282969 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9291 19:23:02.289814 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9292 19:23:02.292787 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9293 19:23:02.296528 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9294 19:23:02.303145 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9295 19:23:02.306783 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9296 19:23:02.312665 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9297 19:23:02.315903 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9298 19:23:02.319198 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9299 19:23:02.325850 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9300 19:23:02.328990 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9301 19:23:02.335911 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9302 19:23:02.339050 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9303 19:23:02.342239 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9304 19:23:02.349480 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9305 19:23:02.352320 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9306 19:23:02.359176 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9307 19:23:02.362616 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9308 19:23:02.365693 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9309 19:23:02.369231 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9310 19:23:02.375452 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9311 19:23:02.379004 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9312 19:23:02.382355 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9313 19:23:02.389117 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9314 19:23:02.392304 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9315 19:23:02.395743 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9316 19:23:02.398884 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9317 19:23:02.405390 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9318 19:23:02.408948 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9319 19:23:02.415680 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9320 19:23:02.419190 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9321 19:23:02.422455 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9322 19:23:02.428828 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9323 19:23:02.432639 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9324 19:23:02.439414 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9325 19:23:02.442758 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9326 19:23:02.445675 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9327 19:23:02.452288 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9328 19:23:02.455586 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9329 19:23:02.461993 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9330 19:23:02.465522 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9331 19:23:02.468593 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9332 19:23:02.475239 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9333 19:23:02.479156 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9334 19:23:02.482253 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9335 19:23:02.488889 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9336 19:23:02.492812 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9337 19:23:02.498546 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9338 19:23:02.502340 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9339 19:23:02.505437 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9340 19:23:02.512232 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9341 19:23:02.515479 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9342 19:23:02.522562 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9343 19:23:02.525462 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9344 19:23:02.528987 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9345 19:23:02.535436 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9346 19:23:02.539054 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9347 19:23:02.545597 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9348 19:23:02.548424 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9349 19:23:02.552497 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9350 19:23:02.558726 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9351 19:23:02.561906 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9352 19:23:02.565723 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9353 19:23:02.571851 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9354 19:23:02.575232 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9355 19:23:02.582615 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9356 19:23:02.585627 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9357 19:23:02.588280 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9358 19:23:02.594958 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9359 19:23:02.598529 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9360 19:23:02.605503 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9361 19:23:02.608561 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9362 19:23:02.611984 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9363 19:23:02.618567 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9364 19:23:02.621252 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9365 19:23:02.627999 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9366 19:23:02.631499 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9367 19:23:02.634640 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9368 19:23:02.641534 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9369 19:23:02.644968 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9370 19:23:02.651516 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9371 19:23:02.654474 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9372 19:23:02.658003 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9373 19:23:02.664547 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9374 19:23:02.667848 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9375 19:23:02.674338 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9376 19:23:02.677535 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9377 19:23:02.680947 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9378 19:23:02.688147 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9379 19:23:02.691074 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9380 19:23:02.697676 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9381 19:23:02.700604 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9382 19:23:02.704113 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9383 19:23:02.710684 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9384 19:23:02.714018 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9385 19:23:02.721042 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9386 19:23:02.723803 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9387 19:23:02.727288 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9388 19:23:02.734145 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9389 19:23:02.737042 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9390 19:23:02.743813 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9391 19:23:02.746997 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9392 19:23:02.754326 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9393 19:23:02.757096 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9394 19:23:02.760823 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9395 19:23:02.767091 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9396 19:23:02.770122 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9397 19:23:02.777007 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9398 19:23:02.780512 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9399 19:23:02.786783 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9400 19:23:02.790321 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9401 19:23:02.793781 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9402 19:23:02.800050 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9403 19:23:02.803353 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9404 19:23:02.810185 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9405 19:23:02.813180 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9406 19:23:02.820360 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9407 19:23:02.823575 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9408 19:23:02.826586 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9409 19:23:02.833579 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9410 19:23:02.836755 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9411 19:23:02.843378 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9412 19:23:02.846827 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9413 19:23:02.849900 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9414 19:23:02.856390 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9415 19:23:02.859961 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9416 19:23:02.866489 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9417 19:23:02.869840 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9418 19:23:02.876365 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9419 19:23:02.879636 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9420 19:23:02.882918 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9421 19:23:02.889818 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9422 19:23:02.893033 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9423 19:23:02.896284 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9424 19:23:02.899435 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9425 19:23:02.906340 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9426 19:23:02.909420 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9427 19:23:02.912942 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9428 19:23:02.919731 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9429 19:23:02.922687 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9430 19:23:02.928959 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9431 19:23:02.932808 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9432 19:23:02.935900 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9433 19:23:02.942563 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9434 19:23:02.946189 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9435 19:23:02.949027 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9436 19:23:02.955779 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9437 19:23:02.959066 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9438 19:23:02.962278 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9439 19:23:02.969104 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9440 19:23:02.972468 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9441 19:23:02.975469 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9442 19:23:02.982278 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9443 19:23:02.985430 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9444 19:23:02.991993 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9445 19:23:02.995526 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9446 19:23:02.998749 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9447 19:23:03.005523 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9448 19:23:03.008825 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9449 19:23:03.012350 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9450 19:23:03.018722 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9451 19:23:03.022372 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9452 19:23:03.028826 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9453 19:23:03.032229 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9454 19:23:03.035262 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9455 19:23:03.041973 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9456 19:23:03.045289 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9457 19:23:03.048630 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9458 19:23:03.055053 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9459 19:23:03.058622 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9460 19:23:03.064932 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9461 19:23:03.068433 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9462 19:23:03.071660 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9463 19:23:03.074810 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9464 19:23:03.078384 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9465 19:23:03.085055 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9466 19:23:03.088787 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9467 19:23:03.091131 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9468 19:23:03.094874 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9469 19:23:03.101091 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9470 19:23:03.105035 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9471 19:23:03.107802 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9472 19:23:03.111312 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9473 19:23:03.117779 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9474 19:23:03.121455 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9475 19:23:03.128276 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9476 19:23:03.131262 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9477 19:23:03.134368 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9478 19:23:03.141402 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9479 19:23:03.144418 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9480 19:23:03.150867 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9481 19:23:03.154615 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9482 19:23:03.157788 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9483 19:23:03.164145 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9484 19:23:03.167586 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9485 19:23:03.174166 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9486 19:23:03.177648 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9487 19:23:03.184603 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9488 19:23:03.187383 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9489 19:23:03.191046 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9490 19:23:03.197671 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9491 19:23:03.200726 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9492 19:23:03.207496 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9493 19:23:03.210898 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9494 19:23:03.213917 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9495 19:23:03.220394 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9496 19:23:03.223642 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9497 19:23:03.230170 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9498 19:23:03.233582 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9499 19:23:03.236827 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9500 19:23:03.243575 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9501 19:23:03.246831 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9502 19:23:03.253738 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9503 19:23:03.257194 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9504 19:23:03.263637 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9505 19:23:03.266663 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9506 19:23:03.270158 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9507 19:23:03.276522 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9508 19:23:03.280113 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9509 19:23:03.286622 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9510 19:23:03.289978 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9511 19:23:03.293029 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9512 19:23:03.299984 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9513 19:23:03.303018 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9514 19:23:03.306789 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9515 19:23:03.313306 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9516 19:23:03.316545 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9517 19:23:03.323339 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9518 19:23:03.326090 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9519 19:23:03.332849 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9520 19:23:03.336147 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9521 19:23:03.339906 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9522 19:23:03.345991 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9523 19:23:03.349654 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9524 19:23:03.356211 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9525 19:23:03.359881 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9526 19:23:03.365962 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9527 19:23:03.369438 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9528 19:23:03.372757 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9529 19:23:03.379433 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9530 19:23:03.382773 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9531 19:23:03.389952 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9532 19:23:03.392649 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9533 19:23:03.396486 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9534 19:23:03.403132 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9535 19:23:03.406148 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9536 19:23:03.412965 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9537 19:23:03.416385 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9538 19:23:03.419181 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9539 19:23:03.426199 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9540 19:23:03.429578 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9541 19:23:03.436234 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9542 19:23:03.439672 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9543 19:23:03.446073 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9544 19:23:03.449321 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9545 19:23:03.452626 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9546 19:23:03.458943 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9547 19:23:03.462512 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9548 19:23:03.469274 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9549 19:23:03.472715 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9550 19:23:03.475703 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9551 19:23:03.482679 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9552 19:23:03.485981 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9553 19:23:03.492786 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9554 19:23:03.495854 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9555 19:23:03.502020 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9556 19:23:03.505583 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9557 19:23:03.509491 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9558 19:23:03.515800 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9559 19:23:03.518559 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9560 19:23:03.525629 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9561 19:23:03.528819 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9562 19:23:03.535730 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9563 19:23:03.538583 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9564 19:23:03.541880 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9565 19:23:03.548552 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9566 19:23:03.552144 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9567 19:23:03.559480 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9568 19:23:03.561764 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9569 19:23:03.568929 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9570 19:23:03.571884 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9571 19:23:03.578405 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9572 19:23:03.581803 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9573 19:23:03.588434 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9574 19:23:03.591617 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9575 19:23:03.594774 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9576 19:23:03.601532 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9577 19:23:03.604623 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9578 19:23:03.611405 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9579 19:23:03.614760 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9580 19:23:03.621474 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9581 19:23:03.624914 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9582 19:23:03.631531 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9583 19:23:03.634917 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9584 19:23:03.638161 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9585 19:23:03.644645 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9586 19:23:03.647932 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9587 19:23:03.654740 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9588 19:23:03.657812 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9589 19:23:03.664668 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9590 19:23:03.667824 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9591 19:23:03.671501 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9592 19:23:03.677965 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9593 19:23:03.681168 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9594 19:23:03.687555 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9595 19:23:03.691019 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9596 19:23:03.694501 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9597 19:23:03.700896 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9598 19:23:03.704239 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9599 19:23:03.710797 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9600 19:23:03.714149 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9601 19:23:03.720589 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9602 19:23:03.724119 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9603 19:23:03.730499 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9604 19:23:03.733779 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9605 19:23:03.740283 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9606 19:23:03.743643 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9607 19:23:03.750481 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9608 19:23:03.754017 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9609 19:23:03.760319 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9610 19:23:03.763921 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9611 19:23:03.770774 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9612 19:23:03.773437 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9613 19:23:03.780750 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9614 19:23:03.783624 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9615 19:23:03.790273 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9616 19:23:03.793403 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9617 19:23:03.800421 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9618 19:23:03.803701 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9619 19:23:03.809948 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9620 19:23:03.813369 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9621 19:23:03.819475 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9622 19:23:03.822707 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9623 19:23:03.830079 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9624 19:23:03.832998 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9625 19:23:03.839634 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9626 19:23:03.842694 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9627 19:23:03.849307 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9628 19:23:03.849883 INFO: [APUAPC] vio 0
9629 19:23:03.856270 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9630 19:23:03.859868 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9631 19:23:03.862905 INFO: [APUAPC] D0_APC_0: 0x400510
9632 19:23:03.866219 INFO: [APUAPC] D0_APC_1: 0x0
9633 19:23:03.869394 INFO: [APUAPC] D0_APC_2: 0x1540
9634 19:23:03.872906 INFO: [APUAPC] D0_APC_3: 0x0
9635 19:23:03.876291 INFO: [APUAPC] D1_APC_0: 0xffffffff
9636 19:23:03.879198 INFO: [APUAPC] D1_APC_1: 0xffffffff
9637 19:23:03.882665 INFO: [APUAPC] D1_APC_2: 0x3fffff
9638 19:23:03.885639 INFO: [APUAPC] D1_APC_3: 0x0
9639 19:23:03.889138 INFO: [APUAPC] D2_APC_0: 0xffffffff
9640 19:23:03.892534 INFO: [APUAPC] D2_APC_1: 0xffffffff
9641 19:23:03.896410 INFO: [APUAPC] D2_APC_2: 0x3fffff
9642 19:23:03.899667 INFO: [APUAPC] D2_APC_3: 0x0
9643 19:23:03.902558 INFO: [APUAPC] D3_APC_0: 0xffffffff
9644 19:23:03.906073 INFO: [APUAPC] D3_APC_1: 0xffffffff
9645 19:23:03.909186 INFO: [APUAPC] D3_APC_2: 0x3fffff
9646 19:23:03.912796 INFO: [APUAPC] D3_APC_3: 0x0
9647 19:23:03.915911 INFO: [APUAPC] D4_APC_0: 0xffffffff
9648 19:23:03.919123 INFO: [APUAPC] D4_APC_1: 0xffffffff
9649 19:23:03.922620 INFO: [APUAPC] D4_APC_2: 0x3fffff
9650 19:23:03.923190 INFO: [APUAPC] D4_APC_3: 0x0
9651 19:23:03.929342 INFO: [APUAPC] D5_APC_0: 0xffffffff
9652 19:23:03.932380 INFO: [APUAPC] D5_APC_1: 0xffffffff
9653 19:23:03.935404 INFO: [APUAPC] D5_APC_2: 0x3fffff
9654 19:23:03.935870 INFO: [APUAPC] D5_APC_3: 0x0
9655 19:23:03.938860 INFO: [APUAPC] D6_APC_0: 0xffffffff
9656 19:23:03.945632 INFO: [APUAPC] D6_APC_1: 0xffffffff
9657 19:23:03.946255 INFO: [APUAPC] D6_APC_2: 0x3fffff
9658 19:23:03.949051 INFO: [APUAPC] D6_APC_3: 0x0
9659 19:23:03.952335 INFO: [APUAPC] D7_APC_0: 0xffffffff
9660 19:23:03.956009 INFO: [APUAPC] D7_APC_1: 0xffffffff
9661 19:23:03.959292 INFO: [APUAPC] D7_APC_2: 0x3fffff
9662 19:23:03.962008 INFO: [APUAPC] D7_APC_3: 0x0
9663 19:23:03.965962 INFO: [APUAPC] D8_APC_0: 0xffffffff
9664 19:23:03.968888 INFO: [APUAPC] D8_APC_1: 0xffffffff
9665 19:23:03.972373 INFO: [APUAPC] D8_APC_2: 0x3fffff
9666 19:23:03.975446 INFO: [APUAPC] D8_APC_3: 0x0
9667 19:23:03.978988 INFO: [APUAPC] D9_APC_0: 0xffffffff
9668 19:23:03.981924 INFO: [APUAPC] D9_APC_1: 0xffffffff
9669 19:23:03.985071 INFO: [APUAPC] D9_APC_2: 0x3fffff
9670 19:23:03.988643 INFO: [APUAPC] D9_APC_3: 0x0
9671 19:23:03.991885 INFO: [APUAPC] D10_APC_0: 0xffffffff
9672 19:23:03.995060 INFO: [APUAPC] D10_APC_1: 0xffffffff
9673 19:23:03.998502 INFO: [APUAPC] D10_APC_2: 0x3fffff
9674 19:23:04.001817 INFO: [APUAPC] D10_APC_3: 0x0
9675 19:23:04.005037 INFO: [APUAPC] D11_APC_0: 0xffffffff
9676 19:23:04.008556 INFO: [APUAPC] D11_APC_1: 0xffffffff
9677 19:23:04.012536 INFO: [APUAPC] D11_APC_2: 0x3fffff
9678 19:23:04.015141 INFO: [APUAPC] D11_APC_3: 0x0
9679 19:23:04.018582 INFO: [APUAPC] D12_APC_0: 0xffffffff
9680 19:23:04.021932 INFO: [APUAPC] D12_APC_1: 0xffffffff
9681 19:23:04.025461 INFO: [APUAPC] D12_APC_2: 0x3fffff
9682 19:23:04.028366 INFO: [APUAPC] D12_APC_3: 0x0
9683 19:23:04.031694 INFO: [APUAPC] D13_APC_0: 0xffffffff
9684 19:23:04.035243 INFO: [APUAPC] D13_APC_1: 0xffffffff
9685 19:23:04.038634 INFO: [APUAPC] D13_APC_2: 0x3fffff
9686 19:23:04.041884 INFO: [APUAPC] D13_APC_3: 0x0
9687 19:23:04.045162 INFO: [APUAPC] D14_APC_0: 0xffffffff
9688 19:23:04.048675 INFO: [APUAPC] D14_APC_1: 0xffffffff
9689 19:23:04.051795 INFO: [APUAPC] D14_APC_2: 0x3fffff
9690 19:23:04.055169 INFO: [APUAPC] D14_APC_3: 0x0
9691 19:23:04.058278 INFO: [APUAPC] D15_APC_0: 0xffffffff
9692 19:23:04.061718 INFO: [APUAPC] D15_APC_1: 0xffffffff
9693 19:23:04.065064 INFO: [APUAPC] D15_APC_2: 0x3fffff
9694 19:23:04.068151 INFO: [APUAPC] D15_APC_3: 0x0
9695 19:23:04.071569 INFO: [APUAPC] APC_CON: 0x4
9696 19:23:04.075048 INFO: [NOCDAPC] D0_APC_0: 0x0
9697 19:23:04.078009 INFO: [NOCDAPC] D0_APC_1: 0x0
9698 19:23:04.081637 INFO: [NOCDAPC] D1_APC_0: 0x0
9699 19:23:04.085256 INFO: [NOCDAPC] D1_APC_1: 0xfff
9700 19:23:04.087972 INFO: [NOCDAPC] D2_APC_0: 0x0
9701 19:23:04.091136 INFO: [NOCDAPC] D2_APC_1: 0xfff
9702 19:23:04.094175 INFO: [NOCDAPC] D3_APC_0: 0x0
9703 19:23:04.094643 INFO: [NOCDAPC] D3_APC_1: 0xfff
9704 19:23:04.098166 INFO: [NOCDAPC] D4_APC_0: 0x0
9705 19:23:04.101168 INFO: [NOCDAPC] D4_APC_1: 0xfff
9706 19:23:04.104391 INFO: [NOCDAPC] D5_APC_0: 0x0
9707 19:23:04.107962 INFO: [NOCDAPC] D5_APC_1: 0xfff
9708 19:23:04.110779 INFO: [NOCDAPC] D6_APC_0: 0x0
9709 19:23:04.114442 INFO: [NOCDAPC] D6_APC_1: 0xfff
9710 19:23:04.117803 INFO: [NOCDAPC] D7_APC_0: 0x0
9711 19:23:04.121200 INFO: [NOCDAPC] D7_APC_1: 0xfff
9712 19:23:04.124369 INFO: [NOCDAPC] D8_APC_0: 0x0
9713 19:23:04.127469 INFO: [NOCDAPC] D8_APC_1: 0xfff
9714 19:23:04.127938 INFO: [NOCDAPC] D9_APC_0: 0x0
9715 19:23:04.130983 INFO: [NOCDAPC] D9_APC_1: 0xfff
9716 19:23:04.134713 INFO: [NOCDAPC] D10_APC_0: 0x0
9717 19:23:04.137760 INFO: [NOCDAPC] D10_APC_1: 0xfff
9718 19:23:04.141202 INFO: [NOCDAPC] D11_APC_0: 0x0
9719 19:23:04.144469 INFO: [NOCDAPC] D11_APC_1: 0xfff
9720 19:23:04.147556 INFO: [NOCDAPC] D12_APC_0: 0x0
9721 19:23:04.151029 INFO: [NOCDAPC] D12_APC_1: 0xfff
9722 19:23:04.154071 INFO: [NOCDAPC] D13_APC_0: 0x0
9723 19:23:04.157479 INFO: [NOCDAPC] D13_APC_1: 0xfff
9724 19:23:04.160677 INFO: [NOCDAPC] D14_APC_0: 0x0
9725 19:23:04.164162 INFO: [NOCDAPC] D14_APC_1: 0xfff
9726 19:23:04.167385 INFO: [NOCDAPC] D15_APC_0: 0x0
9727 19:23:04.170632 INFO: [NOCDAPC] D15_APC_1: 0xfff
9728 19:23:04.171368 INFO: [NOCDAPC] APC_CON: 0x4
9729 19:23:04.174323 INFO: [APUAPC] set_apusys_apc done
9730 19:23:04.177370 INFO: [DEVAPC] devapc_init done
9731 19:23:04.184118 INFO: GICv3 without legacy support detected.
9732 19:23:04.187451 INFO: ARM GICv3 driver initialized in EL3
9733 19:23:04.190719 INFO: Maximum SPI INTID supported: 639
9734 19:23:04.193571 INFO: BL31: Initializing runtime services
9735 19:23:04.200672 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9736 19:23:04.203928 INFO: SPM: enable CPC mode
9737 19:23:04.207716 INFO: mcdi ready for mcusys-off-idle and system suspend
9738 19:23:04.214126 INFO: BL31: Preparing for EL3 exit to normal world
9739 19:23:04.217384 INFO: Entry point address = 0x80000000
9740 19:23:04.217855 INFO: SPSR = 0x8
9741 19:23:04.224321
9742 19:23:04.224884
9743 19:23:04.225256
9744 19:23:04.227505 Starting depthcharge on Spherion...
9745 19:23:04.227966
9746 19:23:04.228361 Wipe memory regions:
9747 19:23:04.228705
9748 19:23:04.230970 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
9749 19:23:04.231503 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
9750 19:23:04.231943 Setting prompt string to ['asurada:']
9751 19:23:04.232423 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
9752 19:23:04.233191 [0x00000040000000, 0x00000054600000)
9753 19:23:04.353693
9754 19:23:04.354277 [0x00000054660000, 0x00000080000000)
9755 19:23:04.613545
9756 19:23:04.613839 [0x000000821a7280, 0x000000ffe64000)
9757 19:23:05.358683
9758 19:23:05.359248 [0x00000100000000, 0x00000140000000)
9759 19:23:05.739571
9760 19:23:05.742827 Initializing XHCI USB controller at 0x11200000.
9761 19:23:06.781237
9762 19:23:06.784219 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9763 19:23:06.784719
9764 19:23:06.785329
9765 19:23:06.785704
9766 19:23:06.786561 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9768 19:23:06.887989 asurada: tftpboot 192.168.201.1 13420363/tftp-deploy-v5h0r7fo/kernel/image.itb 13420363/tftp-deploy-v5h0r7fo/kernel/cmdline
9769 19:23:06.888659 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9770 19:23:06.889124 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:23)
9771 19:23:06.893877 tftpboot 192.168.201.1 13420363/tftp-deploy-v5h0r7fo/kernel/image.itp-deploy-v5h0r7fo/kernel/cmdline
9772 19:23:06.894502
9773 19:23:06.894875 Waiting for link
9774 19:23:07.052242
9775 19:23:07.052811 R8152: Initializing
9776 19:23:07.053177
9777 19:23:07.055437 Version 9 (ocp_data = 6010)
9778 19:23:07.056001
9779 19:23:07.058376 R8152: Done initializing
9780 19:23:07.058838
9781 19:23:07.059207 Adding net device
9782 19:23:09.068616
9783 19:23:09.069182 done.
9784 19:23:09.069547
9785 19:23:09.069944 MAC: 00:e0:4c:68:03:bd
9786 19:23:09.070337
9787 19:23:09.071843 Sending DHCP discover... done.
9788 19:23:09.072299
9789 19:23:12.651129 Waiting for reply... done.
9790 19:23:12.651659
9791 19:23:12.652024 Sending DHCP request... done.
9792 19:23:12.654287
9793 19:23:12.657713 Waiting for reply... done.
9794 19:23:12.658364
9795 19:23:12.658745 My ip is 192.168.201.16
9796 19:23:12.659190
9797 19:23:12.660851 The DHCP server ip is 192.168.201.1
9798 19:23:12.661323
9799 19:23:12.664262 TFTP server IP predefined by user: 192.168.201.1
9800 19:23:12.664876
9801 19:23:12.670966 Bootfile predefined by user: 13420363/tftp-deploy-v5h0r7fo/kernel/image.itb
9802 19:23:12.671580
9803 19:23:12.674136 Sending tftp read request... done.
9804 19:23:12.674686
9805 19:23:12.683549 Waiting for the transfer...
9806 19:23:12.684019
9807 19:23:13.050853 00000000 ################################################################
9808 19:23:13.051041
9809 19:23:13.413008 00080000 ################################################################
9810 19:23:13.413554
9811 19:23:13.799103 00100000 ################################################################
9812 19:23:13.799826
9813 19:23:14.174510 00180000 ################################################################
9814 19:23:14.175154
9815 19:23:14.546779 00200000 ################################################################
9816 19:23:14.547313
9817 19:23:14.853293 00280000 ################################################################
9818 19:23:14.853429
9819 19:23:15.118581 00300000 ################################################################
9820 19:23:15.118720
9821 19:23:15.416603 00380000 ################################################################
9822 19:23:15.416740
9823 19:23:15.701797 00400000 ################################################################
9824 19:23:15.701935
9825 19:23:15.964059 00480000 ################################################################
9826 19:23:15.964197
9827 19:23:16.216833 00500000 ################################################################
9828 19:23:16.216988
9829 19:23:16.480759 00580000 ################################################################
9830 19:23:16.480939
9831 19:23:16.739705 00600000 ################################################################
9832 19:23:16.739850
9833 19:23:16.987646 00680000 ################################################################
9834 19:23:16.987796
9835 19:23:17.239652 00700000 ################################################################
9836 19:23:17.239836
9837 19:23:17.500068 00780000 ################################################################
9838 19:23:17.500227
9839 19:23:17.753037 00800000 ################################################################
9840 19:23:17.753179
9841 19:23:18.013107 00880000 ################################################################
9842 19:23:18.013244
9843 19:23:18.276692 00900000 ################################################################
9844 19:23:18.276827
9845 19:23:18.535094 00980000 ################################################################
9846 19:23:18.535255
9847 19:23:18.824762 00a00000 ################################################################
9848 19:23:18.824911
9849 19:23:19.121384 00a80000 ################################################################
9850 19:23:19.121532
9851 19:23:19.413449 00b00000 ################################################################
9852 19:23:19.413580
9853 19:23:19.692065 00b80000 ################################################################
9854 19:23:19.692204
9855 19:23:19.957343 00c00000 ################################################################
9856 19:23:19.957485
9857 19:23:20.231766 00c80000 ################################################################
9858 19:23:20.231898
9859 19:23:20.498425 00d00000 ################################################################
9860 19:23:20.498566
9861 19:23:20.776125 00d80000 ################################################################
9862 19:23:20.776301
9863 19:23:21.118065 00e00000 ################################################################
9864 19:23:21.118213
9865 19:23:21.374503 00e80000 ################################################################
9866 19:23:21.374653
9867 19:23:21.639688 00f00000 ################################################################
9868 19:23:21.639832
9869 19:23:21.911616 00f80000 ################################################################
9870 19:23:21.911751
9871 19:23:22.182872 01000000 ################################################################
9872 19:23:22.183025
9873 19:23:22.467153 01080000 ################################################################
9874 19:23:22.467307
9875 19:23:22.767352 01100000 ################################################################
9876 19:23:22.767492
9877 19:23:23.058130 01180000 ################################################################
9878 19:23:23.058277
9879 19:23:23.307550 01200000 ################################################################
9880 19:23:23.307698
9881 19:23:23.558431 01280000 ################################################################
9882 19:23:23.558647
9883 19:23:23.817153 01300000 ################################################################
9884 19:23:23.817288
9885 19:23:24.085368 01380000 ################################################################
9886 19:23:24.085506
9887 19:23:24.352754 01400000 ################################################################
9888 19:23:24.352905
9889 19:23:24.642754 01480000 ################################################################
9890 19:23:24.642895
9891 19:23:24.904491 01500000 ################################################################
9892 19:23:24.904636
9893 19:23:25.198339 01580000 ################################################################
9894 19:23:25.198482
9895 19:23:25.472824 01600000 ################################################################
9896 19:23:25.472976
9897 19:23:25.728432 01680000 ################################################################
9898 19:23:25.728570
9899 19:23:25.978825 01700000 ################################################################
9900 19:23:25.978982
9901 19:23:26.275811 01780000 ################################################################
9902 19:23:26.275980
9903 19:23:26.561838 01800000 ################################################################
9904 19:23:26.562013
9905 19:23:26.849294 01880000 ################################################################
9906 19:23:26.849436
9907 19:23:27.146381 01900000 ################################################################
9908 19:23:27.146524
9909 19:23:27.443795 01980000 ################################################################
9910 19:23:27.443929
9911 19:23:27.735247 01a00000 ################################################################
9912 19:23:27.735394
9913 19:23:28.029669 01a80000 ################################################################
9914 19:23:28.029825
9915 19:23:28.289726 01b00000 ################################################################
9916 19:23:28.289875
9917 19:23:28.568505 01b80000 ################################################################
9918 19:23:28.568648
9919 19:23:28.860049 01c00000 ################################################################
9920 19:23:28.860198
9921 19:23:29.157089 01c80000 ################################################################
9922 19:23:29.157228
9923 19:23:29.452340 01d00000 ################################################################
9924 19:23:29.452483
9925 19:23:29.752417 01d80000 ################################################################
9926 19:23:29.752554
9927 19:23:30.059913 01e00000 ################################################################
9928 19:23:30.060504
9929 19:23:30.435551 01e80000 ################################################################
9930 19:23:30.436068
9931 19:23:30.812845 01f00000 ################################################################
9932 19:23:30.813402
9933 19:23:31.187248 01f80000 ################################################################
9934 19:23:31.187765
9935 19:23:31.514137 02000000 ################################################################
9936 19:23:31.514284
9937 19:23:31.814713 02080000 ################################################################
9938 19:23:31.814858
9939 19:23:32.112697 02100000 ################################################################
9940 19:23:32.112845
9941 19:23:32.396780 02180000 ################################################################
9942 19:23:32.396932
9943 19:23:32.660665 02200000 ################################################################
9944 19:23:32.660801
9945 19:23:32.945367 02280000 ################################################################
9946 19:23:32.945510
9947 19:23:33.241871 02300000 ################################################################
9948 19:23:33.242041
9949 19:23:33.608591 02380000 ################################################################
9950 19:23:33.608736
9951 19:23:33.952300 02400000 ################################################################
9952 19:23:33.952855
9953 19:23:34.329030 02480000 ################################################################
9954 19:23:34.329539
9955 19:23:34.707209 02500000 ################################################################
9956 19:23:34.707727
9957 19:23:35.080179 02580000 ################################################################
9958 19:23:35.080698
9959 19:23:35.447571 02600000 ################################################################
9960 19:23:35.448130
9961 19:23:35.825623 02680000 ################################################################
9962 19:23:35.825782
9963 19:23:36.114243 02700000 ################################################################
9964 19:23:36.114384
9965 19:23:36.409090 02780000 ################################################################
9966 19:23:36.409231
9967 19:23:36.702890 02800000 ################################################################
9968 19:23:36.703029
9969 19:23:36.967938 02880000 ################################################################
9970 19:23:36.968079
9971 19:23:37.255544 02900000 ################################################################
9972 19:23:37.255685
9973 19:23:37.552266 02980000 ################################################################
9974 19:23:37.552406
9975 19:23:37.849966 02a00000 ################################################################
9976 19:23:37.850109
9977 19:23:38.134345 02a80000 ################################################################
9978 19:23:38.134490
9979 19:23:38.417208 02b00000 ################################################################
9980 19:23:38.417351
9981 19:23:38.687959 02b80000 ################################################################
9982 19:23:38.688096
9983 19:23:38.984758 02c00000 ################################################################
9984 19:23:38.984919
9985 19:23:39.280317 02c80000 ################################################################
9986 19:23:39.280465
9987 19:23:39.571909 02d00000 ################################################################
9988 19:23:39.572059
9989 19:23:39.829901 02d80000 ################################################################
9990 19:23:39.830070
9991 19:23:40.110880 02e00000 ################################################################
9992 19:23:40.111025
9993 19:23:40.375218 02e80000 ################################################################
9994 19:23:40.375365
9995 19:23:40.640949 02f00000 ################################################################
9996 19:23:40.641087
9997 19:23:40.920352 02f80000 ################################################################
9998 19:23:40.920492
9999 19:23:41.214975 03000000 ################################################################
10000 19:23:41.215115
10001 19:23:41.509817 03080000 ################################################################
10002 19:23:41.509981
10003 19:23:41.780177 03100000 ################################################################
10004 19:23:41.780361
10005 19:23:42.077133 03180000 ################################################################
10006 19:23:42.077300
10007 19:23:42.374443 03200000 ################################################################
10008 19:23:42.374596
10009 19:23:42.636215 03280000 ################################################################
10010 19:23:42.636367
10011 19:23:42.912414 03300000 ################################################################
10012 19:23:42.912563
10013 19:23:43.163003 03380000 ################################################################
10014 19:23:43.163150
10015 19:23:43.427117 03400000 ################################################################
10016 19:23:43.427262
10017 19:23:43.711581 03480000 ################################################################
10018 19:23:43.711736
10019 19:23:43.972415 03500000 ################################################################
10020 19:23:43.972562
10021 19:23:44.267871 03580000 ################################################################
10022 19:23:44.268027
10023 19:23:44.565344 03600000 ################################################################
10024 19:23:44.565498
10025 19:23:44.846817 03680000 ################################################################
10026 19:23:44.846960
10027 19:23:45.108333 03700000 ################################################################
10028 19:23:45.108576
10029 19:23:45.359041 03780000 ################################################################
10030 19:23:45.359187
10031 19:23:45.609694 03800000 ################################################################
10032 19:23:45.609844
10033 19:23:45.877293 03880000 ################################################################
10034 19:23:45.877444
10035 19:23:46.144386 03900000 ################################################################
10036 19:23:46.144615
10037 19:23:46.394291 03980000 ################################################################
10038 19:23:46.394437
10039 19:23:46.675146 03a00000 ################################################################
10040 19:23:46.675295
10041 19:23:46.949577 03a80000 ################################################################
10042 19:23:46.949732
10043 19:23:47.226079 03b00000 ################################################################
10044 19:23:47.226222
10045 19:23:47.498575 03b80000 ################################################################
10046 19:23:47.498753
10047 19:23:47.778884 03c00000 ################################################################
10048 19:23:47.779029
10049 19:23:48.053108 03c80000 ################################################################
10050 19:23:48.053257
10051 19:23:48.349845 03d00000 ################################################################
10052 19:23:48.350011
10053 19:23:48.608824 03d80000 ################################################################
10054 19:23:48.608991
10055 19:23:48.859496 03e00000 ################################################################
10056 19:23:48.859643
10057 19:23:49.119977 03e80000 ################################################################
10058 19:23:49.120123
10059 19:23:49.416765 03f00000 ################################################################
10060 19:23:49.416915
10061 19:23:49.686183 03f80000 ################################################################
10062 19:23:49.686348
10063 19:23:49.959893 04000000 ################################################################
10064 19:23:49.960044
10065 19:23:50.230770 04080000 ################################################################
10066 19:23:50.230942
10067 19:23:50.526933 04100000 ################################################################
10068 19:23:50.527079
10069 19:23:50.799003 04180000 ################################################################
10070 19:23:50.799152
10071 19:23:51.093444 04200000 ################################################################
10072 19:23:51.093594
10073 19:23:51.379243 04280000 ################################################################
10074 19:23:51.379395
10075 19:23:51.644666 04300000 ################################################################
10076 19:23:51.644820
10077 19:23:51.936975 04380000 ################################################################
10078 19:23:51.937129
10079 19:23:52.205635 04400000 ################################################################
10080 19:23:52.205791
10081 19:23:52.461064 04480000 ################################################################
10082 19:23:52.461219
10083 19:23:52.730415 04500000 ################################################################
10084 19:23:52.730570
10085 19:23:52.997943 04580000 ################################################################
10086 19:23:52.998178
10087 19:23:53.256340 04600000 ################################################################
10088 19:23:53.256498
10089 19:23:53.525229 04680000 ################################################################
10090 19:23:53.525387
10091 19:23:53.793979 04700000 ################################################################
10092 19:23:53.794198
10093 19:23:54.079776 04780000 ################################################################
10094 19:23:54.079931
10095 19:23:54.338356 04800000 ################################################################
10096 19:23:54.338512
10097 19:23:54.594556 04880000 ################################################################
10098 19:23:54.594712
10099 19:23:54.858766 04900000 ################################################################
10100 19:23:54.858922
10101 19:23:55.132558 04980000 ################################################################
10102 19:23:55.132710
10103 19:23:55.412982 04a00000 ################################################################
10104 19:23:55.413133
10105 19:23:55.697756 04a80000 ################################################################
10106 19:23:55.697939
10107 19:23:55.957481 04b00000 ################################################################
10108 19:23:55.957636
10109 19:23:56.223972 04b80000 ################################################################
10110 19:23:56.224127
10111 19:23:56.510377 04c00000 ################################################################
10112 19:23:56.510536
10113 19:23:56.796857 04c80000 ################################################################
10114 19:23:56.797012
10115 19:23:57.090062 04d00000 ################################################################
10116 19:23:57.090232
10117 19:23:57.386569 04d80000 ################################################################
10118 19:23:57.386726
10119 19:23:57.674343 04e00000 ################################################################
10120 19:23:57.674499
10121 19:23:57.959158 04e80000 ################################################################
10122 19:23:57.959315
10123 19:23:58.256304 04f00000 ################################################################
10124 19:23:58.256457
10125 19:23:58.553891 04f80000 ################################################################
10126 19:23:58.554066
10127 19:23:58.826509 05000000 ################################################################
10128 19:23:58.826663
10129 19:23:59.116955 05080000 ################################################################
10130 19:23:59.117103
10131 19:23:59.413800 05100000 ################################################################
10132 19:23:59.413972
10133 19:23:59.711328 05180000 ################################################################
10134 19:23:59.711488
10135 19:24:00.007628 05200000 ################################################################
10136 19:24:00.007782
10137 19:24:00.297613 05280000 ################################################################
10138 19:24:00.297768
10139 19:24:00.596733 05300000 ################################################################
10140 19:24:00.596886
10141 19:24:00.881516 05380000 ################################################################
10142 19:24:00.881671
10143 19:24:01.176931 05400000 ################################################################
10144 19:24:01.177085
10145 19:24:01.471061 05480000 ################################################################
10146 19:24:01.471217
10147 19:24:01.768131 05500000 ################################################################
10148 19:24:01.768284
10149 19:24:02.040754 05580000 ################################################################
10150 19:24:02.040907
10151 19:24:02.331503 05600000 ################################################################
10152 19:24:02.331658
10153 19:24:02.628882 05680000 ################################################################
10154 19:24:02.629062
10155 19:24:02.925951 05700000 ################################################################
10156 19:24:02.926149
10157 19:24:03.223615 05780000 ################################################################
10158 19:24:03.223767
10159 19:24:03.495116 05800000 ################################################################
10160 19:24:03.495270
10161 19:24:03.793325 05880000 ################################################################
10162 19:24:03.793507
10163 19:24:04.091134 05900000 ################################################################
10164 19:24:04.091316
10165 19:24:04.387133 05980000 ################################################################
10166 19:24:04.387307
10167 19:24:04.682526 05a00000 ################################################################
10168 19:24:04.682689
10169 19:24:04.936579 05a80000 ################################################################
10170 19:24:04.936755
10171 19:24:05.229670 05b00000 ################################################################
10172 19:24:05.229819
10173 19:24:05.511685 05b80000 ################################################################
10174 19:24:05.511835
10175 19:24:05.769189 05c00000 ################################################################
10176 19:24:05.769361
10177 19:24:06.029948 05c80000 ################################################################
10178 19:24:06.030134
10179 19:24:06.280547 05d00000 ################################################################
10180 19:24:06.280706
10181 19:24:06.531072 05d80000 ################################################################
10182 19:24:06.531229
10183 19:24:06.802569 05e00000 ################################################################
10184 19:24:06.802709
10185 19:24:07.087828 05e80000 ################################################################
10186 19:24:07.087962
10187 19:24:07.351106 05f00000 ################################################################
10188 19:24:07.351238
10189 19:24:07.635100 05f80000 ################################################################
10190 19:24:07.635621
10191 19:24:07.996947 06000000 ################################################################
10192 19:24:07.997472
10193 19:24:08.357694 06080000 ################################################################
10194 19:24:08.358359
10195 19:24:08.726537 06100000 ################################################################
10196 19:24:08.727054
10197 19:24:09.104255 06180000 ################################################################
10198 19:24:09.104784
10199 19:24:09.486555 06200000 ################################################################
10200 19:24:09.487200
10201 19:24:09.864302 06280000 ################################################################
10202 19:24:09.864821
10203 19:24:10.247519 06300000 ################################################################
10204 19:24:10.248176
10205 19:24:10.549045 06380000 ################################################################
10206 19:24:10.549192
10207 19:24:10.828910 06400000 ################################################################
10208 19:24:10.829047
10209 19:24:11.105417 06480000 ################################################################
10210 19:24:11.105550
10211 19:24:11.397833 06500000 ################################################################
10212 19:24:11.397972
10213 19:24:11.652430 06580000 ################################################################
10214 19:24:11.652568
10215 19:24:11.918068 06600000 ################################################################
10216 19:24:11.918194
10217 19:24:12.205977 06680000 ################################################################
10218 19:24:12.206176
10219 19:24:12.467489 06700000 ################################################################
10220 19:24:12.467620
10221 19:24:12.741519 06780000 ################################################################
10222 19:24:12.741677
10223 19:24:12.994931 06800000 ################################################################
10224 19:24:12.995060
10225 19:24:13.287057 06880000 ################################################################
10226 19:24:13.287192
10227 19:24:13.548243 06900000 ################################################################
10228 19:24:13.548394
10229 19:24:13.800493 06980000 ################################################################
10230 19:24:13.800645
10231 19:24:14.088063 06a00000 ################################################################
10232 19:24:14.088197
10233 19:24:14.376670 06a80000 ################################################################
10234 19:24:14.376801
10235 19:24:14.639547 06b00000 ################################################################
10236 19:24:14.639683
10237 19:24:14.915942 06b80000 ################################################################
10238 19:24:14.916081
10239 19:24:15.192252 06c00000 ################################################################
10240 19:24:15.192391
10241 19:24:15.474126 06c80000 ################################################################
10242 19:24:15.474290
10243 19:24:15.725015 06d00000 ################################################################
10244 19:24:15.725149
10245 19:24:15.979712 06d80000 ################################################################
10246 19:24:15.979848
10247 19:24:16.236480 06e00000 ################################################################
10248 19:24:16.236613
10249 19:24:16.487520 06e80000 ################################################################
10250 19:24:16.487655
10251 19:24:16.735384 06f00000 ################################################################
10252 19:24:16.735549
10253 19:24:16.984559 06f80000 ################################################################
10254 19:24:16.984696
10255 19:24:17.242996 07000000 ################################################################
10256 19:24:17.243132
10257 19:24:17.507801 07080000 ################################################################
10258 19:24:17.507962
10259 19:24:17.777728 07100000 ################################################################
10260 19:24:17.777862
10261 19:24:18.031174 07180000 ################################################################
10262 19:24:18.031309
10263 19:24:18.281819 07200000 ################################################################
10264 19:24:18.281983
10265 19:24:18.544246 07280000 ################################################################
10266 19:24:18.544384
10267 19:24:18.805925 07300000 ################################################################
10268 19:24:18.806086
10269 19:24:19.058878 07380000 ################################################################
10270 19:24:19.059010
10271 19:24:19.223724 07400000 ########################################### done.
10272 19:24:19.223850
10273 19:24:19.227599 The bootfile was 121981618 bytes long.
10274 19:24:19.227674
10275 19:24:19.230437 Sending tftp read request... done.
10276 19:24:19.230511
10277 19:24:19.233950 Waiting for the transfer...
10278 19:24:19.234042
10279 19:24:19.234124 00000000 # done.
10280 19:24:19.234185
10281 19:24:19.243896 Command line loaded dynamically from TFTP file: 13420363/tftp-deploy-v5h0r7fo/kernel/cmdline
10282 19:24:19.243980
10283 19:24:19.257034 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10284 19:24:19.257119
10285 19:24:19.257184 Loading FIT.
10286 19:24:19.257247
10287 19:24:19.260509 Image ramdisk-1 has 109022000 bytes.
10288 19:24:19.260577
10289 19:24:19.263615 Image fdt-1 has 47230 bytes.
10290 19:24:19.263685
10291 19:24:19.267048 Image kernel-1 has 12910355 bytes.
10292 19:24:19.267118
10293 19:24:19.276879 Compat preference: google,spherion-rev3-sku1 google,spherion-rev3 google,spherion-sku1 google,spherion
10294 19:24:19.276956
10295 19:24:19.293581 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 (match) google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10296 19:24:19.293657
10297 19:24:19.296734 Choosing best match conf-1 for compat google,spherion-rev3.
10298 19:24:19.302318
10299 19:24:19.307025 Connected to device vid:did:rid of 1ae0:0028:00
10300 19:24:19.313803
10301 19:24:19.317350 tpm_get_response: command 0x17b, return code 0x0
10302 19:24:19.317430
10303 19:24:19.320447 ec_init: CrosEC protocol v3 supported (256, 248)
10304 19:24:19.325847
10305 19:24:19.328876 tpm_cleanup: add release locality here.
10306 19:24:19.328950
10307 19:24:19.329015 Shutting down all USB controllers.
10308 19:24:19.332455
10309 19:24:19.332542 Removing current net device
10310 19:24:19.332603
10311 19:24:19.338952 Exiting depthcharge with code 4 at timestamp: 103397042
10312 19:24:19.339024
10313 19:24:19.342147 LZMA decompressing kernel-1 to 0x821a6718
10314 19:24:19.342226
10315 19:24:19.345635 LZMA decompressing kernel-1 to 0x40000000
10316 19:24:20.939787
10317 19:24:20.939924 jumping to kernel
10318 19:24:20.940489 end: 2.2.4 bootloader-commands (duration 00:01:17) [common]
10319 19:24:20.940592 start: 2.2.5 auto-login-action (timeout 00:03:09) [common]
10320 19:24:20.940672 Setting prompt string to ['Linux version [0-9]']
10321 19:24:20.940742 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10322 19:24:20.940811 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10323 19:24:20.990009
10324 19:24:20.993213 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10325 19:24:20.996684 start: 2.2.5.1 login-action (timeout 00:03:09) [common]
10326 19:24:20.996782 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10327 19:24:20.996857 Setting prompt string to []
10328 19:24:20.996947 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10329 19:24:20.997026 Using line separator: #'\n'#
10330 19:24:20.997089 No login prompt set.
10331 19:24:20.997153 Parsing kernel messages
10332 19:24:20.997216 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10333 19:24:20.997320 [login-action] Waiting for messages, (timeout 00:03:09)
10334 19:24:20.997388 Waiting using forced prompt support (timeout 00:01:35)
10335 19:24:21.016251 [ 0.000000] Linux version 6.1.86-cip19 (KernelCI@build-j170728-arm64-gcc-10-defconfig-arm64-chromebook-wrkxq) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Apr 18 19:05:54 UTC 2024
10336 19:24:21.019636 [ 0.000000] random: crng init done
10337 19:24:21.026471 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10338 19:24:21.029537 [ 0.000000] efi: UEFI not found.
10339 19:24:21.036245 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10340 19:24:21.046190 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10341 19:24:21.052868 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10342 19:24:21.062670 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10343 19:24:21.070119 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10344 19:24:21.076202 [ 0.000000] printk: bootconsole [mtk8250] enabled
10345 19:24:21.082444 [ 0.000000] NUMA: No NUMA configuration found
10346 19:24:21.089077 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10347 19:24:21.092146 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d5a00-0x13f7d7fff]
10348 19:24:21.095750 [ 0.000000] Zone ranges:
10349 19:24:21.102048 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10350 19:24:21.105425 [ 0.000000] DMA32 empty
10351 19:24:21.112036 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10352 19:24:21.115345 [ 0.000000] Movable zone start for each node
10353 19:24:21.118428 [ 0.000000] Early memory node ranges
10354 19:24:21.125208 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10355 19:24:21.132144 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10356 19:24:21.138574 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10357 19:24:21.145091 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10358 19:24:21.151729 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10359 19:24:21.157997 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10360 19:24:21.188447 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10361 19:24:21.194769 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10362 19:24:21.201339 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10363 19:24:21.204797 [ 0.000000] psci: probing for conduit method from DT.
10364 19:24:21.211197 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10365 19:24:21.214366 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10366 19:24:21.221032 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10367 19:24:21.224365 [ 0.000000] psci: SMC Calling Convention v1.2
10368 19:24:21.231036 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10369 19:24:21.234419 [ 0.000000] Detected VIPT I-cache on CPU0
10370 19:24:21.241038 [ 0.000000] CPU features: detected: GIC system register CPU interface
10371 19:24:21.247423 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10372 19:24:21.254049 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10373 19:24:21.260930 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10374 19:24:21.267385 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10375 19:24:21.277245 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10376 19:24:21.280567 [ 0.000000] alternatives: applying boot alternatives
10377 19:24:21.287656 [ 0.000000] Fallback order for Node 0: 0
10378 19:24:21.293845 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10379 19:24:21.297324 [ 0.000000] Policy zone: Normal
10380 19:24:21.310460 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10381 19:24:21.320194 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10382 19:24:21.330783 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10383 19:24:21.340642 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10384 19:24:21.347293 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10385 19:24:21.350856 <6>[ 0.000000] software IO TLB: area num 8.
10386 19:24:21.406202 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10387 19:24:21.486378 <6>[ 0.000000] Memory: 3743688K/4191232K available (18048K kernel code, 4118K rwdata, 22288K rodata, 8448K init, 616K bss, 414776K reserved, 32768K cma-reserved)
10388 19:24:21.493066 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10389 19:24:21.499626 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10390 19:24:21.502655 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10391 19:24:21.509589 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10392 19:24:21.515914 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10393 19:24:21.519333 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10394 19:24:21.529259 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10395 19:24:21.536142 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10396 19:24:21.542611 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10397 19:24:21.549042 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10398 19:24:21.552432 <6>[ 0.000000] GICv3: 608 SPIs implemented
10399 19:24:21.555413 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10400 19:24:21.561931 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10401 19:24:21.565302 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10402 19:24:21.572144 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10403 19:24:21.585509 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10404 19:24:21.598364 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10405 19:24:21.604819 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10406 19:24:21.612833 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10407 19:24:21.626263 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10408 19:24:21.632655 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10409 19:24:21.639712 <6>[ 0.009175] Console: colour dummy device 80x25
10410 19:24:21.649297 <6>[ 0.013932] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10411 19:24:21.656460 <6>[ 0.024374] pid_max: default: 32768 minimum: 301
10412 19:24:21.659229 <6>[ 0.029246] LSM: Security Framework initializing
10413 19:24:21.666064 <6>[ 0.034189] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10414 19:24:21.675561 <6>[ 0.041843] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10415 19:24:21.682222 <6>[ 0.051076] cblist_init_generic: Setting adjustable number of callback queues.
10416 19:24:21.688764 <6>[ 0.058518] cblist_init_generic: Setting shift to 3 and lim to 1.
10417 19:24:21.698861 <6>[ 0.064895] cblist_init_generic: Setting adjustable number of callback queues.
10418 19:24:21.705376 <6>[ 0.072321] cblist_init_generic: Setting shift to 3 and lim to 1.
10419 19:24:21.708898 <6>[ 0.078720] rcu: Hierarchical SRCU implementation.
10420 19:24:21.715259 <6>[ 0.083735] rcu: Max phase no-delay instances is 1000.
10421 19:24:21.721870 <6>[ 0.090751] EFI services will not be available.
10422 19:24:21.725297 <6>[ 0.095701] smp: Bringing up secondary CPUs ...
10423 19:24:21.733204 <6>[ 0.100775] Detected VIPT I-cache on CPU1
10424 19:24:21.740130 <6>[ 0.100843] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10425 19:24:21.746313 <6>[ 0.100874] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10426 19:24:21.749675 <6>[ 0.101205] Detected VIPT I-cache on CPU2
10427 19:24:21.756440 <6>[ 0.101258] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10428 19:24:21.766129 <6>[ 0.101275] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10429 19:24:21.770067 <6>[ 0.101529] Detected VIPT I-cache on CPU3
10430 19:24:21.776151 <6>[ 0.101577] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10431 19:24:21.782761 <6>[ 0.101592] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10432 19:24:21.786234 <6>[ 0.101895] CPU features: detected: Spectre-v4
10433 19:24:21.792709 <6>[ 0.101901] CPU features: detected: Spectre-BHB
10434 19:24:21.796069 <6>[ 0.101906] Detected PIPT I-cache on CPU4
10435 19:24:21.802633 <6>[ 0.101964] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10436 19:24:21.809248 <6>[ 0.101981] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10437 19:24:21.816322 <6>[ 0.102273] Detected PIPT I-cache on CPU5
10438 19:24:21.822653 <6>[ 0.102334] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10439 19:24:21.829144 <6>[ 0.102350] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10440 19:24:21.832243 <6>[ 0.102626] Detected PIPT I-cache on CPU6
10441 19:24:21.839280 <6>[ 0.102688] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10442 19:24:21.845886 <6>[ 0.102705] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10443 19:24:21.852496 <6>[ 0.103001] Detected PIPT I-cache on CPU7
10444 19:24:21.858729 <6>[ 0.103066] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10445 19:24:21.865448 <6>[ 0.103082] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10446 19:24:21.868841 <6>[ 0.103129] smp: Brought up 1 node, 8 CPUs
10447 19:24:21.875240 <6>[ 0.244463] SMP: Total of 8 processors activated.
10448 19:24:21.878898 <6>[ 0.249384] CPU features: detected: 32-bit EL0 Support
10449 19:24:21.888442 <6>[ 0.254780] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10450 19:24:21.895135 <6>[ 0.263635] CPU features: detected: Common not Private translations
10451 19:24:21.901538 <6>[ 0.270111] CPU features: detected: CRC32 instructions
10452 19:24:21.908404 <6>[ 0.275495] CPU features: detected: RCpc load-acquire (LDAPR)
10453 19:24:21.911503 <6>[ 0.281455] CPU features: detected: LSE atomic instructions
10454 19:24:21.917983 <6>[ 0.287272] CPU features: detected: Privileged Access Never
10455 19:24:21.924658 <6>[ 0.293052] CPU features: detected: RAS Extension Support
10456 19:24:21.931169 <6>[ 0.298661] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10457 19:24:21.934788 <6>[ 0.305925] CPU: All CPU(s) started at EL2
10458 19:24:21.940974 <6>[ 0.310242] alternatives: applying system-wide alternatives
10459 19:24:21.950128 <6>[ 0.320198] devtmpfs: initialized
10460 19:24:21.965146 <6>[ 0.328361] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10461 19:24:21.971539 <6>[ 0.338319] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10462 19:24:21.978208 <6>[ 0.346424] pinctrl core: initialized pinctrl subsystem
10463 19:24:21.981247 <6>[ 0.353068] DMI not present or invalid.
10464 19:24:21.988017 <6>[ 0.357474] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10465 19:24:21.997786 <6>[ 0.364330] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10466 19:24:22.004762 <6>[ 0.371774] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10467 19:24:22.014376 <6>[ 0.379862] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10468 19:24:22.017754 <6>[ 0.388016] audit: initializing netlink subsys (disabled)
10469 19:24:22.027702 <5>[ 0.393713] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10470 19:24:22.034095 <6>[ 0.394406] thermal_sys: Registered thermal governor 'step_wise'
10471 19:24:22.040749 <6>[ 0.401679] thermal_sys: Registered thermal governor 'power_allocator'
10472 19:24:22.044102 <6>[ 0.407932] cpuidle: using governor menu
10473 19:24:22.050532 <6>[ 0.418886] NET: Registered PF_QIPCRTR protocol family
10474 19:24:22.057048 <6>[ 0.424373] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10475 19:24:22.063602 <6>[ 0.431477] ASID allocator initialised with 32768 entries
10476 19:24:22.066841 <6>[ 0.438012] Serial: AMBA PL011 UART driver
10477 19:24:22.076674 <4>[ 0.446729] Trying to register duplicate clock ID: 134
10478 19:24:22.130827 <6>[ 0.504265] KASLR enabled
10479 19:24:22.145504 <6>[ 0.511960] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10480 19:24:22.152143 <6>[ 0.518975] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10481 19:24:22.159098 <6>[ 0.525465] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10482 19:24:22.165184 <6>[ 0.532471] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10483 19:24:22.171650 <6>[ 0.538956] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10484 19:24:22.178555 <6>[ 0.545960] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10485 19:24:22.184890 <6>[ 0.552445] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10486 19:24:22.191744 <6>[ 0.559448] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10487 19:24:22.194967 <6>[ 0.566930] ACPI: Interpreter disabled.
10488 19:24:22.203367 <6>[ 0.573329] iommu: Default domain type: Translated
10489 19:24:22.209966 <6>[ 0.578441] iommu: DMA domain TLB invalidation policy: strict mode
10490 19:24:22.213643 <5>[ 0.585103] SCSI subsystem initialized
10491 19:24:22.219903 <6>[ 0.589274] usbcore: registered new interface driver usbfs
10492 19:24:22.226391 <6>[ 0.595006] usbcore: registered new interface driver hub
10493 19:24:22.229814 <6>[ 0.600558] usbcore: registered new device driver usb
10494 19:24:22.236738 <6>[ 0.606648] pps_core: LinuxPPS API ver. 1 registered
10495 19:24:22.246983 <6>[ 0.611840] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10496 19:24:22.250202 <6>[ 0.621188] PTP clock support registered
10497 19:24:22.253049 <6>[ 0.625429] EDAC MC: Ver: 3.0.0
10498 19:24:22.260656 <6>[ 0.630542] FPGA manager framework
10499 19:24:22.267238 <6>[ 0.634218] Advanced Linux Sound Architecture Driver Initialized.
10500 19:24:22.270550 <6>[ 0.640989] vgaarb: loaded
10501 19:24:22.277322 <6>[ 0.644154] clocksource: Switched to clocksource arch_sys_counter
10502 19:24:22.280287 <5>[ 0.650593] VFS: Disk quotas dquot_6.6.0
10503 19:24:22.286967 <6>[ 0.654778] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10504 19:24:22.290109 <6>[ 0.661964] pnp: PnP ACPI: disabled
10505 19:24:22.299110 <6>[ 0.668616] NET: Registered PF_INET protocol family
10506 19:24:22.305206 <6>[ 0.673998] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10507 19:24:22.317466 <6>[ 0.684010] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10508 19:24:22.327270 <6>[ 0.692797] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10509 19:24:22.334220 <6>[ 0.700761] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10510 19:24:22.340779 <6>[ 0.709164] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10511 19:24:22.351219 <6>[ 0.717815] TCP: Hash tables configured (established 32768 bind 32768)
10512 19:24:22.357639 <6>[ 0.724669] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10513 19:24:22.364516 <6>[ 0.731688] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10514 19:24:22.370799 <6>[ 0.739207] NET: Registered PF_UNIX/PF_LOCAL protocol family
10515 19:24:22.377398 <6>[ 0.745348] RPC: Registered named UNIX socket transport module.
10516 19:24:22.380824 <6>[ 0.751500] RPC: Registered udp transport module.
10517 19:24:22.387357 <6>[ 0.756433] RPC: Registered tcp transport module.
10518 19:24:22.394145 <6>[ 0.761364] RPC: Registered tcp NFSv4.1 backchannel transport module.
10519 19:24:22.397319 <6>[ 0.768027] PCI: CLS 0 bytes, default 64
10520 19:24:22.400853 <6>[ 0.772387] Unpacking initramfs...
10521 19:24:22.410491 <6>[ 0.776502] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10522 19:24:22.417130 <6>[ 0.785140] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10523 19:24:22.423852 <6>[ 0.793972] kvm [1]: IPA Size Limit: 40 bits
10524 19:24:22.427383 <6>[ 0.798500] kvm [1]: GICv3: no GICV resource entry
10525 19:24:22.434013 <6>[ 0.803520] kvm [1]: disabling GICv2 emulation
10526 19:24:22.440516 <6>[ 0.808207] kvm [1]: GIC system register CPU interface enabled
10527 19:24:22.443711 <6>[ 0.814367] kvm [1]: vgic interrupt IRQ18
10528 19:24:22.450514 <6>[ 0.818729] kvm [1]: VHE mode initialized successfully
10529 19:24:22.453657 <5>[ 0.825212] Initialise system trusted keyrings
10530 19:24:22.460538 <6>[ 0.830003] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10531 19:24:22.469927 <6>[ 0.839988] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10532 19:24:22.476838 <5>[ 0.846377] NFS: Registering the id_resolver key type
10533 19:24:22.480082 <5>[ 0.851677] Key type id_resolver registered
10534 19:24:22.486941 <5>[ 0.856090] Key type id_legacy registered
10535 19:24:22.493154 <6>[ 0.860370] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10536 19:24:22.499835 <6>[ 0.867292] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10537 19:24:22.506713 <6>[ 0.874985] 9p: Installing v9fs 9p2000 file system support
10538 19:24:22.542875 <5>[ 0.912962] Key type asymmetric registered
10539 19:24:22.546295 <5>[ 0.917294] Asymmetric key parser 'x509' registered
10540 19:24:22.556207 <6>[ 0.922431] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10541 19:24:22.560015 <6>[ 0.930046] io scheduler mq-deadline registered
10542 19:24:22.562670 <6>[ 0.934808] io scheduler kyber registered
10543 19:24:22.581867 <6>[ 0.951689] EINJ: ACPI disabled.
10544 19:24:22.614099 <4>[ 0.977485] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10545 19:24:22.623995 <4>[ 0.988172] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10546 19:24:22.639064 <6>[ 1.008640] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10547 19:24:22.646638 <6>[ 1.016555] printk: console [ttyS0] disabled
10548 19:24:22.674617 <6>[ 1.041190] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10549 19:24:22.681035 <6>[ 1.050662] printk: console [ttyS0] enabled
10550 19:24:22.684640 <6>[ 1.050662] printk: console [ttyS0] enabled
10551 19:24:22.690969 <6>[ 1.059558] printk: bootconsole [mtk8250] disabled
10552 19:24:22.694273 <6>[ 1.059558] printk: bootconsole [mtk8250] disabled
10553 19:24:22.701286 <6>[ 1.070611] SuperH (H)SCI(F) driver initialized
10554 19:24:22.704375 <6>[ 1.075871] msm_serial: driver initialized
10555 19:24:22.718296 <6>[ 1.084766] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10556 19:24:22.727915 <6>[ 1.093311] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10557 19:24:22.734711 <6>[ 1.101853] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10558 19:24:22.744676 <6>[ 1.110481] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10559 19:24:22.754943 <6>[ 1.119186] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10560 19:24:22.761350 <6>[ 1.127900] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10561 19:24:22.771166 <6>[ 1.136445] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10562 19:24:22.777793 <6>[ 1.145238] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10563 19:24:22.787547 <6>[ 1.153784] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10564 19:24:22.799062 <6>[ 1.169017] loop: module loaded
10565 19:24:22.805715 <6>[ 1.174850] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10566 19:24:22.828078 <4>[ 1.198025] mtk-pmic-keys: Failed to locate of_node [id: -1]
10567 19:24:22.834804 <6>[ 1.204814] megasas: 07.719.03.00-rc1
10568 19:24:22.844670 <6>[ 1.214429] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10569 19:24:22.853539 <6>[ 1.223538] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10570 19:24:22.870357 <6>[ 1.240288] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10571 19:24:22.927261 <6>[ 1.290373] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10572 19:24:27.032178 <6>[ 5.402286] Freeing initrd memory: 106464K
10573 19:24:27.043687 <6>[ 5.414002] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10574 19:24:27.054685 <6>[ 5.425057] tun: Universal TUN/TAP device driver, 1.6
10575 19:24:27.057963 <6>[ 5.431130] thunder_xcv, ver 1.0
10576 19:24:27.061546 <6>[ 5.434635] thunder_bgx, ver 1.0
10577 19:24:27.064948 <6>[ 5.438131] nicpf, ver 1.0
10578 19:24:27.075325 <6>[ 5.442162] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10579 19:24:27.078499 <6>[ 5.449638] hns3: Copyright (c) 2017 Huawei Corporation.
10580 19:24:27.085423 <6>[ 5.455225] hclge is initializing
10581 19:24:27.088741 <6>[ 5.458806] e1000: Intel(R) PRO/1000 Network Driver
10582 19:24:27.095209 <6>[ 5.463936] e1000: Copyright (c) 1999-2006 Intel Corporation.
10583 19:24:27.098924 <6>[ 5.469951] e1000e: Intel(R) PRO/1000 Network Driver
10584 19:24:27.105070 <6>[ 5.475166] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10585 19:24:27.111774 <6>[ 5.481353] igb: Intel(R) Gigabit Ethernet Network Driver
10586 19:24:27.118625 <6>[ 5.487003] igb: Copyright (c) 2007-2014 Intel Corporation.
10587 19:24:27.125226 <6>[ 5.492840] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10588 19:24:27.131801 <6>[ 5.499358] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10589 19:24:27.135483 <6>[ 5.505845] sky2: driver version 1.30
10590 19:24:27.141707 <6>[ 5.510839] VFIO - User Level meta-driver version: 0.3
10591 19:24:27.148904 <6>[ 5.519065] usbcore: registered new interface driver usb-storage
10592 19:24:27.155461 <6>[ 5.525513] usbcore: registered new device driver onboard-usb-hub
10593 19:24:27.165021 <6>[ 5.534701] mt6397-rtc mt6359-rtc: registered as rtc0
10594 19:24:27.174951 <6>[ 5.540169] mt6397-rtc mt6359-rtc: setting system clock to 2024-04-18T19:24:26 UTC (1713468266)
10595 19:24:27.177943 <6>[ 5.549734] i2c_dev: i2c /dev entries driver
10596 19:24:27.195141 <6>[ 5.561568] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10597 19:24:27.201347 <4>[ 5.570316] cpu cpu0: supply cpu not found, using dummy regulator
10598 19:24:27.207928 <4>[ 5.576735] cpu cpu1: supply cpu not found, using dummy regulator
10599 19:24:27.214458 <4>[ 5.583135] cpu cpu2: supply cpu not found, using dummy regulator
10600 19:24:27.221310 <4>[ 5.589553] cpu cpu3: supply cpu not found, using dummy regulator
10601 19:24:27.227773 <4>[ 5.595948] cpu cpu4: supply cpu not found, using dummy regulator
10602 19:24:27.234393 <4>[ 5.602348] cpu cpu5: supply cpu not found, using dummy regulator
10603 19:24:27.240800 <4>[ 5.608742] cpu cpu6: supply cpu not found, using dummy regulator
10604 19:24:27.247218 <4>[ 5.615134] cpu cpu7: supply cpu not found, using dummy regulator
10605 19:24:27.266682 <6>[ 5.636814] cpu cpu0: EM: created perf domain
10606 19:24:27.269829 <6>[ 5.641732] cpu cpu4: EM: created perf domain
10607 19:24:27.276817 <6>[ 5.647286] sdhci: Secure Digital Host Controller Interface driver
10608 19:24:27.283524 <6>[ 5.653717] sdhci: Copyright(c) Pierre Ossman
10609 19:24:27.290064 <6>[ 5.658632] Synopsys Designware Multimedia Card Interface Driver
10610 19:24:27.296823 <6>[ 5.665233] sdhci-pltfm: SDHCI platform and OF driver helper
10611 19:24:27.300046 <6>[ 5.665380] mmc0: CQHCI version 5.10
10612 19:24:27.306622 <6>[ 5.675308] ledtrig-cpu: registered to indicate activity on CPUs
10613 19:24:27.313343 <6>[ 5.682391] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10614 19:24:27.319859 <6>[ 5.689420] usbcore: registered new interface driver usbhid
10615 19:24:27.323355 <6>[ 5.695243] usbhid: USB HID core driver
10616 19:24:27.329798 <6>[ 5.699443] spi_master spi0: will run message pump with realtime priority
10617 19:24:27.376756 <6>[ 5.740466] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10618 19:24:27.396307 <6>[ 5.756354] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10619 19:24:27.399690 <6>[ 5.769930] mmc0: Command Queue Engine enabled
10620 19:24:27.406631 <6>[ 5.771261] cros-ec-spi spi0.0: Chrome EC device registered
10621 19:24:27.413560 <6>[ 5.774665] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10622 19:24:27.416467 <6>[ 5.787778] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10623 19:24:27.427809 <6>[ 5.794829] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10624 19:24:27.434509 <6>[ 5.802773] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10625 19:24:27.441362 <6>[ 5.805119] NET: Registered PF_PACKET protocol family
10626 19:24:27.444580 <6>[ 5.811368] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10627 19:24:27.451209 <6>[ 5.815428] 9pnet: Installing 9P2000 support
10628 19:24:27.454543 <6>[ 5.821263] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10629 19:24:27.460966 <5>[ 5.825117] Key type dns_resolver registered
10630 19:24:27.467608 <6>[ 5.830955] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10631 19:24:27.471233 <6>[ 5.835341] registered taskstats version 1
10632 19:24:27.474292 <5>[ 5.845753] Loading compiled-in X.509 certificates
10633 19:24:27.503061 <4>[ 5.866564] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10634 19:24:27.513042 <4>[ 5.877292] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10635 19:24:27.519595 <3>[ 5.887821] debugfs: File 'uA_load' in directory '/' already present!
10636 19:24:27.526274 <3>[ 5.894520] debugfs: File 'min_uV' in directory '/' already present!
10637 19:24:27.532688 <3>[ 5.901186] debugfs: File 'max_uV' in directory '/' already present!
10638 19:24:27.539512 <3>[ 5.907801] debugfs: File 'constraint_flags' in directory '/' already present!
10639 19:24:27.550303 <3>[ 5.917387] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10640 19:24:27.559171 <6>[ 5.929227] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10641 19:24:27.566325 <6>[ 5.936098] xhci-mtk 11200000.usb: xHCI Host Controller
10642 19:24:27.572616 <6>[ 5.941589] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10643 19:24:27.582699 <6>[ 5.949419] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10644 19:24:27.589242 <6>[ 5.958839] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10645 19:24:27.595686 <6>[ 5.964914] xhci-mtk 11200000.usb: xHCI Host Controller
10646 19:24:27.602448 <6>[ 5.970394] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10647 19:24:27.608942 <6>[ 5.978038] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10648 19:24:27.615499 <6>[ 5.985659] hub 1-0:1.0: USB hub found
10649 19:24:27.619064 <6>[ 5.989666] hub 1-0:1.0: 1 port detected
10650 19:24:27.625127 <6>[ 5.993935] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10651 19:24:27.632123 <6>[ 6.002577] hub 2-0:1.0: USB hub found
10652 19:24:27.635541 <6>[ 6.006597] hub 2-0:1.0: 1 port detected
10653 19:24:27.644112 <6>[ 6.014713] mtk-msdc 11f70000.mmc: Got CD GPIO
10654 19:24:27.656387 <6>[ 6.023504] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10655 19:24:27.663152 <6>[ 6.031524] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10656 19:24:27.672906 <4>[ 6.039428] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10657 19:24:27.682699 <6>[ 6.048947] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10658 19:24:27.689370 <6>[ 6.057024] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10659 19:24:27.695805 <6>[ 6.065182] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10660 19:24:27.705899 <6>[ 6.073140] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10661 19:24:27.713281 <6>[ 6.080959] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10662 19:24:27.722416 <6>[ 6.088776] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10663 19:24:27.732327 <6>[ 6.099156] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10664 19:24:27.739024 <6>[ 6.107538] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10665 19:24:27.748706 <6>[ 6.115877] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10666 19:24:27.755310 <6>[ 6.124216] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10667 19:24:27.765586 <6>[ 6.132556] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10668 19:24:27.775476 <6>[ 6.140896] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10669 19:24:27.782403 <6>[ 6.149234] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10670 19:24:27.791884 <6>[ 6.157571] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10671 19:24:27.798310 <6>[ 6.165907] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10672 19:24:27.808219 <6>[ 6.174244] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10673 19:24:27.814856 <6>[ 6.182587] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10674 19:24:27.824683 <6>[ 6.190924] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10675 19:24:27.831655 <6>[ 6.199262] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10676 19:24:27.841185 <6>[ 6.207598] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10677 19:24:27.847763 <6>[ 6.215936] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10678 19:24:27.854382 <6>[ 6.224694] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10679 19:24:27.861302 <6>[ 6.231851] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10680 19:24:27.868267 <6>[ 6.238592] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10681 19:24:27.877983 <6>[ 6.245334] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10682 19:24:27.884748 <6>[ 6.252234] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10683 19:24:27.891284 <6>[ 6.259072] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10684 19:24:27.901000 <6>[ 6.268200] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10685 19:24:27.910990 <6>[ 6.277321] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10686 19:24:27.920934 <6>[ 6.286616] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10687 19:24:27.930694 <6>[ 6.296085] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10688 19:24:27.940720 <6>[ 6.305551] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10689 19:24:27.947604 <6>[ 6.314670] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10690 19:24:27.957374 <6>[ 6.324136] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10691 19:24:27.967100 <6>[ 6.333258] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10692 19:24:27.977017 <6>[ 6.342552] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10693 19:24:27.986855 <6>[ 6.352711] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10694 19:24:27.997583 <6>[ 6.364693] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10695 19:24:28.025167 <6>[ 6.392502] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10696 19:24:28.053544 <6>[ 6.423897] hub 2-1:1.0: USB hub found
10697 19:24:28.056720 <6>[ 6.428357] hub 2-1:1.0: 3 ports detected
10698 19:24:28.065705 <6>[ 6.435676] hub 2-1:1.0: USB hub found
10699 19:24:28.068310 <6>[ 6.440028] hub 2-1:1.0: 3 ports detected
10700 19:24:28.177278 <6>[ 6.544417] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10701 19:24:28.331911 <6>[ 6.702442] hub 1-1:1.0: USB hub found
10702 19:24:28.335011 <6>[ 6.706949] hub 1-1:1.0: 4 ports detected
10703 19:24:28.345092 <6>[ 6.715333] hub 1-1:1.0: USB hub found
10704 19:24:28.348034 <6>[ 6.719687] hub 1-1:1.0: 4 ports detected
10705 19:24:28.409500 <6>[ 6.776726] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10706 19:24:28.669107 <6>[ 7.036465] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10707 19:24:28.801343 <6>[ 7.172030] hub 1-1.4:1.0: USB hub found
10708 19:24:28.804722 <6>[ 7.176709] hub 1-1.4:1.0: 2 ports detected
10709 19:24:28.814122 <6>[ 7.184675] hub 1-1.4:1.0: USB hub found
10710 19:24:28.817228 <6>[ 7.189410] hub 1-1.4:1.0: 2 ports detected
10711 19:24:29.112955 <6>[ 7.480437] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10712 19:24:29.304952 <6>[ 7.672433] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10713 19:24:40.270496 <6>[ 18.645510] ALSA device list:
10714 19:24:40.276742 <6>[ 18.648798] No soundcards found.
10715 19:24:40.284621 <6>[ 18.656596] Freeing unused kernel memory: 8448K
10716 19:24:40.288003 <6>[ 18.662135] Run /init as init process
10717 19:24:40.322639 <6>[ 18.694191] NET: Registered PF_INET6 protocol family
10718 19:24:40.329001 <6>[ 18.700688] Segment Routing with IPv6
10719 19:24:40.332138 <6>[ 18.704643] In-situ OAM (IOAM) with IPv6
10720 19:24:40.377271 <30>[ 18.722410] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10721 19:24:40.383623 <30>[ 18.755481] systemd[1]: Detected architecture arm64.
10722 19:24:40.384128
10723 19:24:40.390430 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10724 19:24:40.390853
10725 19:24:40.391203
10726 19:24:40.404776 <30>[ 18.776427] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10727 19:24:40.538112 <30>[ 18.906123] systemd[1]: Queued start job for default target graphical.target.
10728 19:24:40.577589 <30>[ 18.945929] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10729 19:24:40.584160 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10730 19:24:40.584713
10731 19:24:40.604475 <30>[ 18.972834] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10732 19:24:40.611186 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10733 19:24:40.614298
10734 19:24:40.633575 <30>[ 19.001790] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10735 19:24:40.643563 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10736 19:24:40.644019
10737 19:24:40.660780 <30>[ 19.029145] systemd[1]: Created slice user.slice - User and Session Slice.
10738 19:24:40.667301 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10739 19:24:40.667741
10740 19:24:40.687278 <30>[ 19.052494] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10741 19:24:40.693688 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10742 19:24:40.693798
10743 19:24:40.715629 <30>[ 19.080943] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10744 19:24:40.721972 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10745 19:24:40.722108
10746 19:24:40.749966 <30>[ 19.108766] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10747 19:24:40.759805 <30>[ 19.128607] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10748 19:24:40.766205 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10749 19:24:40.766309
10750 19:24:40.784078 <30>[ 19.152721] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10751 19:24:40.790802 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10752 19:24:40.790889
10753 19:24:40.807623 <30>[ 19.176380] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10754 19:24:40.817659 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10755 19:24:40.817810
10756 19:24:40.833082 <30>[ 19.204915] systemd[1]: Reached target paths.target - Path Units.
10757 19:24:40.839955 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10758 19:24:40.843262
10759 19:24:40.860292 <30>[ 19.228898] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10760 19:24:40.867114 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10761 19:24:40.867192
10762 19:24:40.880418 <30>[ 19.252437] systemd[1]: Reached target slices.target - Slice Units.
10763 19:24:40.890633 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10764 19:24:40.890713
10765 19:24:40.905008 <30>[ 19.276935] systemd[1]: Reached target swap.target - Swaps.
10766 19:24:40.911552 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10767 19:24:40.911632
10768 19:24:40.932405 <30>[ 19.300940] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10769 19:24:40.942231 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10770 19:24:40.942321
10771 19:24:40.960675 <30>[ 19.328947] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10772 19:24:40.970130 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10773 19:24:40.970212
10774 19:24:40.990387 <30>[ 19.358616] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10775 19:24:40.999852 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10776 19:24:40.999944
10777 19:24:41.016418 <30>[ 19.385236] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10778 19:24:41.026432 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10779 19:24:41.026514
10780 19:24:41.044282 <30>[ 19.413068] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10781 19:24:41.050996 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10782 19:24:41.051097
10783 19:24:41.068769 <30>[ 19.437085] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10784 19:24:41.078436 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10785 19:24:41.078515
10786 19:24:41.096227 <30>[ 19.464931] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10787 19:24:41.105819 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10788 19:24:41.105923
10789 19:24:41.147726 <30>[ 19.516618] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10790 19:24:41.154188 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10791 19:24:41.154265
10792 19:24:41.175841 <30>[ 19.544680] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10793 19:24:41.182506 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10794 19:24:41.182581
10795 19:24:41.207818 <30>[ 19.576824] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10796 19:24:41.214411 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10797 19:24:41.214493
10798 19:24:41.238124 <30>[ 19.600560] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10799 19:24:41.268035 <30>[ 19.636900] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10800 19:24:41.277802 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10801 19:24:41.277907
10802 19:24:41.300617 <30>[ 19.669150] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10803 19:24:41.307182 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10804 19:24:41.307260
10805 19:24:41.360100 <30>[ 19.728895] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10806 19:24:41.370002 Startin<6>[ 19.738123] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10807 19:24:41.376745 g [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10808 19:24:41.376824
10809 19:24:41.397914 <30>[ 19.766965] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10810 19:24:41.404483 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10811 19:24:41.404561
10812 19:24:41.430669 <30>[ 19.799557] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10813 19:24:41.437169 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10814 19:24:41.437248
10815 19:24:41.464973 <30>[ 19.833750] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10816 19:24:41.471766 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10817 19:24:41.471846
10818 19:24:41.504573 <30>[ 19.873424] systemd[1]: Starting systemd-journald.service - Journal Service...
10819 19:24:41.511064 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10820 19:24:41.511143
10821 19:24:41.530430 <30>[ 19.899144] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10822 19:24:41.536952 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10823 19:24:41.537057
10824 19:24:41.595880 <30>[ 19.961079] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10825 19:24:41.602309 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10826 19:24:41.602389
10827 19:24:41.628626 <30>[ 19.997552] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10828 19:24:41.638529 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10829 19:24:41.638609
10830 19:24:41.661415 <30>[ 20.030359] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10831 19:24:41.668150 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10832 19:24:41.668229
10833 19:24:41.695870 <30>[ 20.064473] systemd[1]: Started systemd-journald.service - Journal Service.
10834 19:24:41.702146 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10835 19:24:41.702225
10836 19:24:41.723709 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10837 19:24:41.723789
10838 19:24:41.740686 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10839 19:24:41.740768
10840 19:24:41.760574 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10841 19:24:41.760660
10842 19:24:41.781059 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10843 19:24:41.781143
10844 19:24:41.801932 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10845 19:24:41.802069
10846 19:24:41.822340 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10847 19:24:41.822437
10848 19:24:41.842243 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10849 19:24:41.842323
10850 19:24:41.863411 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10851 19:24:41.863495
10852 19:24:41.882021 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10853 19:24:41.882140
10854 19:24:41.905111 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10855 19:24:41.905197
10856 19:24:41.925209 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10857 19:24:41.925293
10858 19:24:41.946108 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10859 19:24:41.946192
10860 19:24:41.960257 See 'systemctl status systemd-remount-fs.service' for details.
10861 19:24:41.960341
10862 19:24:41.970784 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10863 19:24:41.970862
10864 19:24:41.990761 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10865 19:24:41.990860
10866 19:24:42.031999 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10867 19:24:42.032114
10868 19:24:42.050223 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10869 19:24:42.050329
10870 19:24:42.062218 <46>[ 20.431267] systemd-journald[189]: Received client request to flush runtime journal.
10871 19:24:42.074452 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10872 19:24:42.074561
10873 19:24:42.099805 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10874 19:24:42.099919
10875 19:24:42.125230 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10876 19:24:42.125327
10877 19:24:42.157310 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10878 19:24:42.157430
10879 19:24:42.176841 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10880 19:24:42.176956
10881 19:24:42.200938 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10882 19:24:42.201024
10883 19:24:42.221075 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10884 19:24:42.221159
10885 19:24:42.244990 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10886 19:24:42.245072
10887 19:24:42.296243 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10888 19:24:42.296332
10889 19:24:42.318966 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10890 19:24:42.319050
10891 19:24:42.336227 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10892 19:24:42.336310
10893 19:24:42.351685 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10894 19:24:42.351776
10895 19:24:42.416684 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10896 19:24:42.416801
10897 19:24:42.441756 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10898 19:24:42.441865
10899 19:24:42.467077 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10900 19:24:42.467158
10901 19:24:42.507307 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10902 19:24:42.507421
10903 19:24:42.531652 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10904 19:24:42.531731
10905 19:24:42.552251 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10906 19:24:42.552359
10907 19:24:42.581025 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10908 19:24:42.581107
10909 19:24:42.613932 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10910 19:24:42.614079
10911 19:24:42.637436 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10912 19:24:42.637540
10913 19:24:42.729646 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10914 19:24:42.729773
10915 19:24:42.748754 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10916 19:24:42.748832
10917 19:24:42.768692 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10918 19:24:42.768795
10919 19:24:42.788970 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10920 19:24:42.789072
10921 19:24:42.808677 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10922 19:24:42.808784
10923 19:24:42.818554 <6>[ 21.186790] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10924 19:24:42.824842 <6>[ 21.195045] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10925 19:24:42.834903 <3>[ 21.197597] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10926 19:24:42.844763 <6>[ 21.203776] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10927 19:24:42.851519 <3>[ 21.220922] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10928 19:24:42.858234 <6>[ 21.222550] usbcore: registered new device driver r8152-cfgselector
10929 19:24:42.864653 <6>[ 21.222845] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10930 19:24:42.871119 [[0;32m OK [<6>[ 21.225216] remoteproc remoteproc0: scp is available
10931 19:24:42.877852 0m] Listening on<6>[ 21.225289] remoteproc remoteproc0: powering up scp
10932 19:24:42.888025 <6>[ 21.225293] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10933 19:24:42.894572 <6>[ 21.225308] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10934 19:24:42.901160 <3>[ 21.229199] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10935 19:24:42.904692 <6>[ 21.270511] mc: Linux media interface: v0.10
10936 19:24:42.914198 <3>[ 21.278446] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10937 19:24:42.917770 <6>[ 21.279007] Bluetooth: Core ver 2.22
10938 19:24:42.924355 <6>[ 21.279064] NET: Registered PF_BLUETOOTH protocol family
10939 19:24:42.930860 [0;1;39mdbus.s<6>[ 21.279065] Bluetooth: HCI device and connection manager initialized
10940 19:24:42.937804 <6>[ 21.279079] Bluetooth: HCI socket layer initialized
10941 19:24:42.940677 <6>[ 21.279084] Bluetooth: L2CAP socket layer initialized
10942 19:24:42.947339 <6>[ 21.279090] Bluetooth: SCO socket layer initialized
10943 19:24:42.950789 <6>[ 21.295250] videodev: Linux video capture interface: v2.00
10944 19:24:42.960639 ocket[…- D-Bu<4>[ 21.295830] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10945 19:24:42.970893 s System Message<4>[ 21.296070] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10946 19:24:42.970971 Bus Socket.
10947 19:24:42.971035
10948 19:24:42.980504 <3>[ 21.300321] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10949 19:24:42.987039 <3>[ 21.300328] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10950 19:24:42.993714 <3>[ 21.300344] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10951 19:24:43.004398 <6>[ 21.324942] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10952 19:24:43.011013 <6>[ 21.325903] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10953 19:24:43.017527 <6>[ 21.326389] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10954 19:24:43.024032 <6>[ 21.326401] pci_bus 0000:00: root bus resource [bus 00-ff]
10955 19:24:43.030749 <6>[ 21.326410] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10956 19:24:43.041059 <6>[ 21.326414] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10957 19:24:43.047602 <6>[ 21.326470] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10958 19:24:43.054434 <6>[ 21.326491] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10959 19:24:43.057710 <6>[ 21.326575] pci 0000:00:00.0: supports D1 D2
10960 19:24:43.067512 <6>[ 21.326579] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10961 19:24:43.074422 <6>[ 21.327567] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10962 19:24:43.080692 <6>[ 21.327739] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10963 19:24:43.087386 <6>[ 21.327764] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10964 19:24:43.097432 <6>[ 21.327783] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10965 19:24:43.103807 <6>[ 21.327799] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10966 19:24:43.107383 <6>[ 21.327915] pci 0000:01:00.0: supports D1 D2
10967 19:24:43.113925 <6>[ 21.327916] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10968 19:24:43.124490 <3>[ 21.329612] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10969 19:24:43.131497 <3>[ 21.329688] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10970 19:24:43.138822 <6>[ 21.340325] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10971 19:24:43.145131 <3>[ 21.347079] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10972 19:24:43.154898 <6>[ 21.350570] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10973 19:24:43.161706 <6>[ 21.350581] remoteproc remoteproc0: remote processor scp is now up
10974 19:24:43.168219 <6>[ 21.350583] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10975 19:24:43.174948 <6>[ 21.356856] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10976 19:24:43.185286 <4>[ 21.363293] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10977 19:24:43.192153 <4>[ 21.363302] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10978 19:24:43.202498 <3>[ 21.364494] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10979 19:24:43.209061 <3>[ 21.364497] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10980 19:24:43.218582 <3>[ 21.364557] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10981 19:24:43.225416 <4>[ 21.365568] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10982 19:24:43.231964 <4>[ 21.365568] Fallback method does not support PEC.
10983 19:24:43.238421 <6>[ 21.365859] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10984 19:24:43.248355 <6>[ 21.367744] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10985 19:24:43.255347 <6>[ 21.372591] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10986 19:24:43.265608 <3>[ 21.380541] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10987 19:24:43.272365 <3>[ 21.380929] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10988 19:24:43.281985 <3>[ 21.380933] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10989 19:24:43.288943 <6>[ 21.388584] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10990 19:24:43.296390 <3>[ 21.395437] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10991 19:24:43.305935 <6>[ 21.401181] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10992 19:24:43.312647 <3>[ 21.408293] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10993 19:24:43.319197 <3>[ 21.408314] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10994 19:24:43.329387 <6>[ 21.408588] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10995 19:24:43.335959 <6>[ 21.412297] r8152 2-1.3:1.0 eth0: v1.12.13
10996 19:24:43.339417 <6>[ 21.412394] usbcore: registered new interface driver r8152
10997 19:24:43.346510 <6>[ 21.418261] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10998 19:24:43.353294 <6>[ 21.418275] pci 0000:00:00.0: PCI bridge to [bus 01]
10999 19:24:43.359783 <6>[ 21.418281] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11000 19:24:43.373121 <6>[ 21.421102] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
11001 19:24:43.379629 <6>[ 21.421378] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
11002 19:24:43.389847 <3>[ 21.426987] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11003 19:24:43.396557 <6>[ 21.432316] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11004 19:24:43.406302 <3>[ 21.438275] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11005 19:24:43.409410 <6>[ 21.444397] usbcore: registered new interface driver cdc_ether
11006 19:24:43.416089 <6>[ 21.446347] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
11007 19:24:43.422446 <6>[ 21.446623] pcieport 0000:00:00.0: AER: enabled with IRQ 282
11008 19:24:43.429214 <6>[ 21.454630] usbcore: registered new interface driver btusb
11009 19:24:43.439098 <4>[ 21.455232] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11010 19:24:43.445626 <3>[ 21.455259] Bluetooth: hci0: Failed to load firmware file (-2)
11011 19:24:43.452196 <3>[ 21.455262] Bluetooth: hci0: Failed to set up firmware (-2)
11012 19:24:43.462910 <4>[ 21.455265] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11013 19:24:43.466233 <6>[ 21.466205] usbcore: registered new interface driver r8153_ecm
11014 19:24:43.473035 <6>[ 21.466464] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11015 19:24:43.483112 <5>[ 21.467985] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11016 19:24:43.493706 <6>[ 21.468447] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11017 19:24:43.500201 <6>[ 21.468657] usbcore: registered new interface driver uvcvideo
11018 19:24:43.506987 <5>[ 21.487614] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11019 19:24:43.514099 <6>[ 21.493035] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11020 19:24:43.523898 <5>[ 21.500442] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
11021 19:24:43.526972 <6>[ 21.503105] r8152 2-1.3:1.0 enx00e04c6803bd: renamed from eth0
11022 19:24:43.537750 <3>[ 21.514399] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11023 19:24:43.544296 <3>[ 21.515716] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11024 19:24:43.554588 <4>[ 21.531934] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11025 19:24:43.564055 <3>[ 21.538516] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11026 19:24:43.567845 <6>[ 21.545353] cfg80211: failed to load regulatory.db
11027 19:24:43.577672 <3>[ 21.560949] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11028 19:24:43.583814 <6>[ 21.613642] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11029 19:24:43.593856 <3>[ 21.638019] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11030 19:24:43.600358 <6>[ 21.641943] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11031 19:24:43.607013 <3>[ 21.668390] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11032 19:24:43.613616 <6>[ 21.694438] mt7921e 0000:01:00.0: ASIC revision: 79610010
11033 19:24:43.623509 <3>[ 21.722881] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11034 19:24:43.630015 <6>[ 21.818812] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
11035 19:24:43.633432 <6>[ 21.818812]
11036 19:24:43.640143 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11037 19:24:43.640227
11038 19:24:43.659991 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11039 19:24:43.660075
11040 19:24:43.697158 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11041 19:24:43.697240
11042 19:24:43.726053 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11043 19:24:43.726167
11044 19:24:43.749708 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11045 19:24:43.749820
11046 19:24:43.770590 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11047 19:24:43.770675
11048 19:24:43.801909 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11049 19:24:43.802038
11050 19:24:43.858805 <46>[ 22.214243] systemd-journald[189]: Data hash table of /var/log/journal/6cfa758ce87d4acd800e1258fdce5dda/system.journal has a fill level at 75.0 (1536 of 2047 items, 524288 file size, 341 bytes per hash table item), suggesting rotation.
11051 19:24:43.871657 <46>[ 22.235488] systemd-journald[189]: /var/log/journal/6cfa758ce87d4acd800e1258fdce5dda/system.journal: Journal header limits reached or header out-of-date, rotating.
11052 19:24:43.881742 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11053 19:24:43.881850
11054 19:24:43.901842 <6>[ 22.270964] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
11055 19:24:43.911837 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11056 19:24:43.911927
11057 19:24:43.928676 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11058 19:24:43.928780
11059 19:24:43.948109 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11060 19:24:43.948216
11061 19:24:44.013340 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11062 19:24:44.013457
11063 19:24:44.034628 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11064 19:24:44.034712
11065 19:24:44.053129 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11066 19:24:44.053234
11067 19:24:44.068139 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11068 19:24:44.068218
11069 19:24:44.088145 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11070 19:24:44.088225
11071 19:24:44.141368 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11072 19:24:44.141456
11073 19:24:44.166644 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11074 19:24:44.166750
11075 19:24:44.191473 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11076 19:24:44.191578
11077 19:24:44.262260 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11078 19:24:44.262373
11079 19:24:44.281951 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11080 19:24:44.282086
11081 19:24:44.306922 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11082 19:24:44.307011
11083 19:24:44.349047
11084 19:24:44.349137
11085 19:24:44.352552 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11086 19:24:44.352652
11087 19:24:44.355753 debian-bookworm-arm64 login: root (automatic login)
11088 19:24:44.355858
11089 19:24:44.355949
11090 19:24:44.369298 Linux debian-bookworm-arm64 6.1.86-cip19 #1 SMP PREEMPT Thu Apr 18 19:05:54 UTC 2024 aarch64
11091 19:24:44.369382
11092 19:24:44.376346 The programs included with the Debian GNU/Linux system are free software;
11093 19:24:44.382656 the exact distribution terms for each program are described in the
11094 19:24:44.385760 individual files in /usr/share/doc/*/copyright.
11095 19:24:44.385846
11096 19:24:44.392631 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11097 19:24:44.396007 permitted by applicable law.
11098 19:24:44.396619 Matched prompt #10: / #
11100 19:24:44.396925 Setting prompt string to ['/ #']
11101 19:24:44.397046 end: 2.2.5.1 login-action (duration 00:00:23) [common]
11103 19:24:44.397262 end: 2.2.5 auto-login-action (duration 00:00:23) [common]
11104 19:24:44.397346 start: 2.2.6 expect-shell-connection (timeout 00:02:46) [common]
11105 19:24:44.397420 Setting prompt string to ['/ #']
11106 19:24:44.397481 Forcing a shell prompt, looking for ['/ #']
11108 19:24:44.447691 / #
11109 19:24:44.447789 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11110 19:24:44.447861 Waiting using forced prompt support (timeout 00:02:30)
11111 19:24:44.452424
11112 19:24:44.452709 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11113 19:24:44.452824 start: 2.2.7 export-device-env (timeout 00:02:46) [common]
11114 19:24:44.452942 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11115 19:24:44.453059 end: 2.2 depthcharge-retry (duration 00:02:14) [common]
11116 19:24:44.453182 end: 2 depthcharge-action (duration 00:02:14) [common]
11117 19:24:44.453298 start: 3 lava-test-retry (timeout 00:05:00) [common]
11118 19:24:44.453383 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11119 19:24:44.453455 Using namespace: common
11121 19:24:44.553730 / # #
11122 19:24:44.553871 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11123 19:24:44.558771 #
11124 19:24:44.559027 Using /lava-13420363
11126 19:24:44.659329 / # export SHELL=/bin/sh
11127 19:24:44.664941 export SHELL=/bin/sh
11129 19:24:44.766103 / # . /lava-13420363/environment
11130 19:24:44.766735 . /lava-13420363/environment<6>[ 23.128422] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11131 19:24:44.771663
11133 19:24:44.873085 / # /lava-13420363/bin/lava-test-runner /lava-13420363/0
11134 19:24:44.873585 Test shell timeout: 10s (minimum of the action and connection timeout)
11135 19:24:44.879646 /lava-13420363/bin/lava-test-runner /lava-13420363/0
11136 19:24:44.897370 + export TESTRUN_ID=0_sleep
11137 19:24:44.900876 + cd /lava-13420363/0/tests/0_sleep
11138 19:24:44.904048 + cat uuid
11139 19:24:44.904426 + UUID=13420363_1.5.2.3.1
11140 19:24:44.907507 + set +x
11141 19:24:44.910714 <LAVA_SIGNAL_STARTRUN 0_sleep 13420363_1.5.2.3.1>
11142 19:24:44.911347 Received signal: <STARTRUN> 0_sleep 13420363_1.5.2.3.1
11143 19:24:44.911706 Starting test lava.0_sleep (13420363_1.5.2.3.1)
11144 19:24:44.912122 Skipping test definition patterns.
11145 19:24:44.913829 + ./config/lava/sleep/sleep.sh mem
11146 19:24:44.917113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-exist RESULT=pass>
11147 19:24:44.917910 Received signal: <TESTCASE> TEST_CASE_ID=rtc-exist RESULT=pass
11149 19:24:44.923843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass>
11150 19:24:44.924604 Received signal: <TESTCASE> TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass
11152 19:24:44.927010 rtcwake: assuming RTC uses UTC ...
11153 19:24:44.933845 rtcwake: wakeup from "mem" using rtc0 at Thu Apr 18 19:24:50 2024
11154 19:24:44.936965 <6>[ 23.311183] PM: suspend entry (deep)
11155 19:24:44.943679 <6>[ 23.315112] Filesystems sync: 0.000 seconds
11156 19:24:44.947032 <6>[ 23.320661] Freezing user space processes
11157 19:24:44.957699 <6>[ 23.326441] Freezing user space processes completed (elapsed 0.001 seconds)
11158 19:24:44.960664 <6>[ 23.333720] OOM killer disabled.
11159 19:24:44.964715 <6>[ 23.337201] Freezing remaining freezable tasks
11160 19:24:44.974247 <6>[ 23.343070] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11161 19:24:44.980623 <6>[ 23.350723] printk: Suspending console(s) (use no_console_suspend to debug)
11162 19:24:50.732466 <6>[ 23.472446] Disabling non-boot CPUs ...
11163 19:24:50.735253 <4>[ 23.473328] IRQ282: set affinity failed(-22).
11164 19:24:50.742052 <4>[ 23.473343] IRQ284: set affinity failed(-22).
11165 19:24:50.745167 <6>[ 23.474424] psci: CPU1 killed (polled 0 ms)
11166 19:24:50.748655 <4>[ 23.475523] IRQ282: set affinity failed(-22).
11167 19:24:50.755139 <4>[ 23.475535] IRQ284: set affinity failed(-22).
11168 19:24:50.758403 <6>[ 23.476183] psci: CPU2 killed (polled 4 ms)
11169 19:24:50.761718 <4>[ 23.477163] IRQ282: set affinity failed(-22).
11170 19:24:50.768333 <4>[ 23.477174] IRQ284: set affinity failed(-22).
11171 19:24:50.771601 <6>[ 23.478237] psci: CPU3 killed (polled 0 ms)
11172 19:24:50.775005 <4>[ 23.478916] IRQ282: set affinity failed(-22).
11173 19:24:50.781804 <4>[ 23.478919] IRQ284: set affinity failed(-22).
11174 19:24:50.785099 <6>[ 23.478952] psci: CPU4 killed (polled 0 ms)
11175 19:24:50.791656 <4>[ 23.479642] IRQ282: set affinity failed(-22).
11176 19:24:50.794924 <4>[ 23.479647] IRQ284: set affinity failed(-22).
11177 19:24:50.798281 <6>[ 23.479682] psci: CPU5 killed (polled 0 ms)
11178 19:24:50.805099 <6>[ 23.480540] psci: CPU6 killed (polled 0 ms)
11179 19:24:50.808201 <6>[ 23.481256] psci: CPU7 killed (polled 0 ms)
11180 19:24:50.811664 <6>[ 23.481745] Enabling non-boot CPUs ...
11181 19:24:50.814700 <6>[ 23.481966] Detected VIPT I-cache on CPU1
11182 19:24:50.824737 <6>[ 23.482049] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11183 19:24:50.831505 <6>[ 23.482107] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11184 19:24:50.834863 <6>[ 23.482679] CPU1 is up
11185 19:24:50.837890 <6>[ 23.482816] Detected VIPT I-cache on CPU2
11186 19:24:50.844487 <6>[ 23.482871] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11187 19:24:50.851323 <6>[ 23.482907] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11188 19:24:50.854620 <6>[ 23.483371] CPU2 is up
11189 19:24:50.857765 <6>[ 23.483504] Detected VIPT I-cache on CPU3
11190 19:24:50.864427 <6>[ 23.483559] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11191 19:24:50.870957 <6>[ 23.483595] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11192 19:24:50.874416 <6>[ 23.484068] CPU3 is up
11193 19:24:50.881119 <6>[ 23.484222] CPU features: detected: Hardware dirty bit management
11194 19:24:50.884361 <6>[ 23.484237] Detected PIPT I-cache on CPU4
11195 19:24:50.894301 <6>[ 23.484255] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11196 19:24:50.900724 <6>[ 23.484268] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11197 19:24:50.900807 <6>[ 23.484515] CPU4 is up
11198 19:24:50.907304 <6>[ 23.484633] Detected PIPT I-cache on CPU5
11199 19:24:50.913999 <6>[ 23.484653] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11200 19:24:50.920531 <6>[ 23.484666] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11201 19:24:50.924180 <6>[ 23.484887] CPU5 is up
11202 19:24:50.927214 <6>[ 23.485003] Detected PIPT I-cache on CPU6
11203 19:24:50.933856 <6>[ 23.485023] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11204 19:24:50.940388 <6>[ 23.485036] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11205 19:24:50.943608 <6>[ 23.485260] CPU6 is up
11206 19:24:50.946975 <6>[ 23.485377] Detected PIPT I-cache on CPU7
11207 19:24:50.957471 <6>[ 23.485397] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11208 19:24:50.963568 <6>[ 23.485409] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11209 19:24:50.963651 <6>[ 23.485642] CPU7 is up
11210 19:24:50.974059 <4>[ 23.622096] typec port0-partner: PM: parent port0 should not be sleeping
11211 19:24:50.976940 <6>[ 24.083422] OOM killer enabled.
11212 19:24:50.980006 <6>[ 24.086812] Restarting tasks ... done.
11213 19:24:50.987149 <5>[ 24.091155] random: crng reseeded on system resumption
11214 19:24:50.989902 <6>[ 24.097660] PM: suspend exit
11215 19:24:50.997908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-1 RESULT=pass>
11216 19:24:50.998193 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-1 RESULT=pass
11218 19:24:51.000956 rtcwake: assuming RTC uses UTC ...
11219 19:24:51.007556 rtcwake: wakeup from "mem" using rtc0 at Thu Apr 18 19:24:56 2024
11220 19:24:51.019515 <6>[ 24.125829] PM: suspend entry (deep)
11221 19:24:51.022794 <6>[ 24.129688] Filesystems sync: 0.000 seconds
11222 19:24:51.026219 <6>[ 24.134429] Freezing user space processes
11223 19:24:51.036969 <6>[ 24.140003] Freezing user space processes completed (elapsed 0.001 seconds)
11224 19:24:51.040308 <6>[ 24.147221] OOM killer disabled.
11225 19:24:51.043820 <6>[ 24.150702] Freezing remaining freezable tasks
11226 19:24:51.053651 <6>[ 24.156131] Freezing remaining freezable tasks completed (elapsed 0.000 seconds)
11227 19:24:51.060359 <6>[ 24.163777] printk: Suspending console(s) (use no_console_suspend to debug)
11228 19:24:56.729733 <6>[ 24.254086] Disabling non-boot CPUs ...
11229 19:24:56.732833 <6>[ 24.254781] psci: CPU1 killed (polled 0 ms)
11230 19:24:56.735932 <6>[ 24.255435] psci: CPU2 killed (polled 0 ms)
11231 19:24:56.742820 <6>[ 24.257063] psci: CPU3 killed (polled 4 ms)
11232 19:24:56.745974 <6>[ 24.257468] psci: CPU4 killed (polled 0 ms)
11233 19:24:56.749308 <6>[ 24.257908] psci: CPU5 killed (polled 0 ms)
11234 19:24:56.755990 <6>[ 24.258363] psci: CPU6 killed (polled 0 ms)
11235 19:24:56.759133 <6>[ 24.258849] psci: CPU7 killed (polled 0 ms)
11236 19:24:56.762487 <6>[ 24.259120] Enabling non-boot CPUs ...
11237 19:24:56.769710 <6>[ 24.259306] Detected VIPT I-cache on CPU1
11238 19:24:56.775866 <6>[ 24.259370] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11239 19:24:56.782444 <6>[ 24.259416] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11240 19:24:56.785673 <6>[ 24.259879] CPU1 is up
11241 19:24:56.789299 <6>[ 24.259980] Detected VIPT I-cache on CPU2
11242 19:24:56.796054 <6>[ 24.260018] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11243 19:24:56.802262 <6>[ 24.260043] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11244 19:24:56.805628 <6>[ 24.260423] CPU2 is up
11245 19:24:56.809378 <6>[ 24.260521] Detected VIPT I-cache on CPU3
11246 19:24:56.815579 <6>[ 24.260560] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11247 19:24:56.825523 <6>[ 24.260585] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11248 19:24:56.825603 <6>[ 24.260929] CPU3 is up
11249 19:24:56.831890 <6>[ 24.261030] Detected PIPT I-cache on CPU4
11250 19:24:56.838926 <6>[ 24.261048] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11251 19:24:56.845335 <6>[ 24.261059] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11252 19:24:56.848583 <6>[ 24.261295] CPU4 is up
11253 19:24:56.852072 <6>[ 24.261391] Detected PIPT I-cache on CPU5
11254 19:24:56.858581 <6>[ 24.261408] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11255 19:24:56.865145 <6>[ 24.261419] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11256 19:24:56.868469 <6>[ 24.261607] CPU5 is up
11257 19:24:56.871748 <6>[ 24.261711] Detected PIPT I-cache on CPU6
11258 19:24:56.878691 <6>[ 24.261728] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11259 19:24:56.885318 <6>[ 24.261739] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11260 19:24:56.888461 <6>[ 24.261930] CPU6 is up
11261 19:24:56.895069 <6>[ 24.262026] Detected PIPT I-cache on CPU7
11262 19:24:56.901688 <6>[ 24.262044] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11263 19:24:56.908213 <6>[ 24.262055] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11264 19:24:56.911605 <6>[ 24.262255] CPU7 is up
11265 19:24:56.914930 <6>[ 24.799913] OOM killer enabled.
11266 19:24:56.918020 <6>[ 24.803304] Restarting tasks ... done.
11267 19:24:56.925108 <5>[ 24.807666] random: crng reseeded on system resumption
11268 19:24:56.927845 <6>[ 24.814559] PM: suspend exit
11269 19:24:56.937151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-2 RESULT=pass>
11270 19:24:56.937436 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-2 RESULT=pass
11272 19:24:56.940332 rtcwake: assuming RTC uses UTC ...
11273 19:24:56.946876 rtcwake: wakeup from "mem" using rtc0 at Thu Apr 18 19:25:02 2024
11274 19:24:56.959566 <6>[ 24.844281] PM: suspend entry (deep)
11275 19:24:56.963072 <6>[ 24.848142] Filesystems sync: 0.000 seconds
11276 19:24:56.966529 <6>[ 24.852865] Freezing user space processes
11277 19:24:56.977291 <6>[ 24.858401] Freezing user space processes completed (elapsed 0.001 seconds)
11278 19:24:56.980368 <6>[ 24.865630] OOM killer disabled.
11279 19:24:56.983791 <6>[ 24.869110] Freezing remaining freezable tasks
11280 19:24:56.993672 <6>[ 24.874902] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11281 19:24:56.999984 <6>[ 24.882551] printk: Suspending console(s) (use no_console_suspend to debug)
11282 19:25:02.730508 <6>[ 24.954857] Disabling non-boot CPUs ...
11283 19:25:02.733450 <6>[ 24.955680] psci: CPU1 killed (polled 0 ms)
11284 19:25:02.736564 <6>[ 24.957750] psci: CPU2 killed (polled 0 ms)
11285 19:25:02.743403 <6>[ 24.959633] psci: CPU3 killed (polled 0 ms)
11286 19:25:02.746585 <6>[ 24.960133] psci: CPU4 killed (polled 0 ms)
11287 19:25:02.750106 <6>[ 24.960712] psci: CPU5 killed (polled 0 ms)
11288 19:25:02.757379 <6>[ 24.961282] psci: CPU6 killed (polled 0 ms)
11289 19:25:02.760171 <6>[ 24.961839] psci: CPU7 killed (polled 0 ms)
11290 19:25:02.763300 <6>[ 24.962154] Enabling non-boot CPUs ...
11291 19:25:02.770063 <6>[ 24.962364] Detected VIPT I-cache on CPU1
11292 19:25:02.776556 <6>[ 24.962441] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11293 19:25:02.783160 <6>[ 24.962495] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11294 19:25:02.786473 <6>[ 24.963057] CPU1 is up
11295 19:25:02.790097 <6>[ 24.963180] Detected VIPT I-cache on CPU2
11296 19:25:02.796399 <6>[ 24.963230] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11297 19:25:02.803479 <6>[ 24.963263] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11298 19:25:02.806412 <6>[ 24.963704] CPU2 is up
11299 19:25:02.809812 <6>[ 24.963827] Detected VIPT I-cache on CPU3
11300 19:25:02.816569 <6>[ 24.963876] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11301 19:25:02.823294 <6>[ 24.963909] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11302 19:25:02.826575 <6>[ 24.964384] CPU3 is up
11303 19:25:02.833201 <6>[ 24.964503] Detected PIPT I-cache on CPU4
11304 19:25:02.839718 <6>[ 24.964523] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11305 19:25:02.846422 <6>[ 24.964536] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11306 19:25:02.849704 <6>[ 24.964781] CPU4 is up
11307 19:25:02.853029 <6>[ 24.964897] Detected PIPT I-cache on CPU5
11308 19:25:02.860056 <6>[ 24.964917] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11309 19:25:02.865966 <6>[ 24.964930] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11310 19:25:02.869542 <6>[ 24.965142] CPU5 is up
11311 19:25:02.872964 <6>[ 24.965253] Detected PIPT I-cache on CPU6
11312 19:25:02.879034 <6>[ 24.965273] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11313 19:25:02.885820 <6>[ 24.965286] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11314 19:25:02.889547 <6>[ 24.965504] CPU6 is up
11315 19:25:02.896175 <6>[ 24.965619] Detected PIPT I-cache on CPU7
11316 19:25:02.902625 <6>[ 24.965646] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11317 19:25:02.909037 <6>[ 24.965658] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11318 19:25:02.912548 <6>[ 24.965895] CPU7 is up
11319 19:25:02.915743 <6>[ 25.504088] OOM killer enabled.
11320 19:25:02.919023 <6>[ 25.507478] Restarting tasks ... done.
11321 19:25:02.925712 <5>[ 25.511817] random: crng reseeded on system resumption
11322 19:25:02.928745 <6>[ 25.518713] PM: suspend exit
11323 19:25:02.936985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-3 RESULT=pass>
11324 19:25:02.937866 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-3 RESULT=pass
11326 19:25:02.940270 rtcwake: assuming RTC uses UTC ...
11327 19:25:02.947026 rtcwake: wakeup from "mem" using rtc0 at Thu Apr 18 19:25:08 2024
11328 19:25:02.958790 <6>[ 25.546985] PM: suspend entry (deep)
11329 19:25:02.962237 <6>[ 25.550852] Filesystems sync: 0.000 seconds
11330 19:25:02.965561 <6>[ 25.555562] Freezing user space processes
11331 19:25:02.976450 <6>[ 25.561207] Freezing user space processes completed (elapsed 0.001 seconds)
11332 19:25:02.980266 <6>[ 25.568438] OOM killer disabled.
11333 19:25:02.982971 <6>[ 25.571914] Freezing remaining freezable tasks
11334 19:25:02.993379 <6>[ 25.577804] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11335 19:25:02.999634 <6>[ 25.585472] printk: Suspending console(s) (use no_console_suspend to debug)
11336 19:25:08.727244 <6>[ 25.670630] Disabling non-boot CPUs ...
11337 19:25:08.731444 <6>[ 25.671359] psci: CPU1 killed (polled 0 ms)
11338 19:25:08.734510 <6>[ 25.672007] psci: CPU2 killed (polled 0 ms)
11339 19:25:08.740378 <6>[ 25.673737] psci: CPU3 killed (polled 0 ms)
11340 19:25:08.744116 <6>[ 25.674132] psci: CPU4 killed (polled 0 ms)
11341 19:25:08.747432 <6>[ 25.674642] psci: CPU5 killed (polled 0 ms)
11342 19:25:08.754130 <6>[ 25.675164] psci: CPU6 killed (polled 0 ms)
11343 19:25:08.757306 <6>[ 25.675586] psci: CPU7 killed (polled 0 ms)
11344 19:25:08.760400 <6>[ 25.675842] Enabling non-boot CPUs ...
11345 19:25:08.767312 <6>[ 25.676035] Detected VIPT I-cache on CPU1
11346 19:25:08.774066 <6>[ 25.676102] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11347 19:25:08.780269 <6>[ 25.676150] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11348 19:25:08.783583 <6>[ 25.676631] CPU1 is up
11349 19:25:08.786914 <6>[ 25.676741] Detected VIPT I-cache on CPU2
11350 19:25:08.793751 <6>[ 25.676782] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11351 19:25:08.799979 <6>[ 25.676810] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11352 19:25:08.803558 <6>[ 25.677181] CPU2 is up
11353 19:25:08.807238 <6>[ 25.677288] Detected VIPT I-cache on CPU3
11354 19:25:08.813432 <6>[ 25.677330] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11355 19:25:08.823311 <6>[ 25.677356] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11356 19:25:08.824010 <6>[ 25.677732] CPU3 is up
11357 19:25:08.829663 <6>[ 25.677836] Detected PIPT I-cache on CPU4
11358 19:25:08.836713 <6>[ 25.677855] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11359 19:25:08.843335 <6>[ 25.677867] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11360 19:25:08.846563 <6>[ 25.678104] CPU4 is up
11361 19:25:08.850082 <6>[ 25.678213] Detected PIPT I-cache on CPU5
11362 19:25:08.856500 <6>[ 25.678232] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11363 19:25:08.863054 <6>[ 25.678244] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11364 19:25:08.866499 <6>[ 25.678443] CPU5 is up
11365 19:25:08.869920 <6>[ 25.678544] Detected PIPT I-cache on CPU6
11366 19:25:08.876795 <6>[ 25.678563] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11367 19:25:08.886704 <6>[ 25.678575] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11368 19:25:08.887321 <6>[ 25.678776] CPU6 is up
11369 19:25:08.893406 <6>[ 25.678877] Detected PIPT I-cache on CPU7
11370 19:25:08.899340 <6>[ 25.678901] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11371 19:25:08.905980 <6>[ 25.678912] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11372 19:25:08.909927 <6>[ 25.679124] CPU7 is up
11373 19:25:08.913165 <6>[ 26.215799] OOM killer enabled.
11374 19:25:08.916295 <6>[ 26.219191] Restarting tasks ... done.
11375 19:25:08.922669 <5>[ 26.223513] random: crng reseeded on system resumption
11376 19:25:08.925829 <6>[ 26.230838] PM: suspend exit
11377 19:25:08.935300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-4 RESULT=pass>
11378 19:25:08.936164 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-4 RESULT=pass
11380 19:25:08.938849 rtcwake: assuming RTC uses UTC ...
11381 19:25:08.945194 rtcwake: wakeup from "mem" using rtc0 at Thu Apr 18 19:25:14 2024
11382 19:25:08.958003 <6>[ 26.260389] PM: suspend entry (deep)
11383 19:25:08.961370 <6>[ 26.264247] Filesystems sync: 0.000 seconds
11384 19:25:08.964888 <6>[ 26.268956] Freezing user space processes
11385 19:25:08.975546 <6>[ 26.274585] Freezing user space processes completed (elapsed 0.001 seconds)
11386 19:25:08.978590 <6>[ 26.281814] OOM killer disabled.
11387 19:25:08.981970 <6>[ 26.285296] Freezing remaining freezable tasks
11388 19:25:08.992529 <6>[ 26.291187] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11389 19:25:08.998347 <6>[ 26.298854] printk: Suspending console(s) (use no_console_suspend to debug)
11390 19:25:14.732182 <6>[ 26.371394] Disabling non-boot CPUs ...
11391 19:25:14.735540 <6>[ 26.372154] psci: CPU1 killed (polled 0 ms)
11392 19:25:14.738992 <6>[ 26.374078] psci: CPU2 killed (polled 0 ms)
11393 19:25:14.745467 <6>[ 26.375723] psci: CPU3 killed (polled 0 ms)
11394 19:25:14.748786 <6>[ 26.376131] psci: CPU4 killed (polled 0 ms)
11395 19:25:14.752459 <6>[ 26.376652] psci: CPU5 killed (polled 0 ms)
11396 19:25:14.758881 <6>[ 26.377141] psci: CPU6 killed (polled 0 ms)
11397 19:25:14.762550 <6>[ 26.377614] psci: CPU7 killed (polled 0 ms)
11398 19:25:14.765768 <6>[ 26.377903] Enabling non-boot CPUs ...
11399 19:25:14.771932 <6>[ 26.378095] Detected VIPT I-cache on CPU1
11400 19:25:14.778658 <6>[ 26.378159] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11401 19:25:14.785306 <6>[ 26.378206] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11402 19:25:14.788900 <6>[ 26.378675] CPU1 is up
11403 19:25:14.791923 <6>[ 26.378778] Detected VIPT I-cache on CPU2
11404 19:25:14.798872 <6>[ 26.378816] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11405 19:25:14.805375 <6>[ 26.378843] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11406 19:25:14.808490 <6>[ 26.379192] CPU2 is up
11407 19:25:14.811969 <6>[ 26.379294] Detected VIPT I-cache on CPU3
11408 19:25:14.818480 <6>[ 26.379334] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11409 19:25:14.825094 <6>[ 26.379360] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11410 19:25:14.828682 <6>[ 26.379712] CPU3 is up
11411 19:25:14.835245 <6>[ 26.379815] Detected PIPT I-cache on CPU4
11412 19:25:14.841730 <6>[ 26.379835] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11413 19:25:14.848762 <6>[ 26.379848] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11414 19:25:14.852093 <6>[ 26.380114] CPU4 is up
11415 19:25:14.855196 <6>[ 26.380219] Detected PIPT I-cache on CPU5
11416 19:25:14.861755 <6>[ 26.380239] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11417 19:25:14.868325 <6>[ 26.380252] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11418 19:25:14.871585 <6>[ 26.380459] CPU5 is up
11419 19:25:14.875104 <6>[ 26.380558] Detected PIPT I-cache on CPU6
11420 19:25:14.881792 <6>[ 26.380578] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11421 19:25:14.888293 <6>[ 26.380591] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11422 19:25:14.891850 <6>[ 26.380798] CPU6 is up
11423 19:25:14.898398 <6>[ 26.380902] Detected PIPT I-cache on CPU7
11424 19:25:14.904693 <6>[ 26.380928] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11425 19:25:14.911247 <6>[ 26.380941] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11426 19:25:14.914414 <6>[ 26.381169] CPU7 is up
11427 19:25:14.917720 <6>[ 26.923754] OOM killer enabled.
11428 19:25:14.921752 <6>[ 26.927144] Restarting tasks ... done.
11429 19:25:14.927908 <5>[ 26.931508] random: crng reseeded on system resumption
11430 19:25:14.930877 <6>[ 26.938223] PM: suspend exit
11431 19:25:14.941579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-5 RESULT=pass>
11432 19:25:14.942494 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-5 RESULT=pass
11434 19:25:14.944455 rtcwake: assuming RTC uses UTC ...
11435 19:25:14.950618 rtcwake: wakeup from "mem" using rtc0 at Thu Apr 18 19:25:20 2024
11436 19:25:14.963825 <6>[ 26.969194] PM: suspend entry (deep)
11437 19:25:14.967300 <6>[ 26.973059] Filesystems sync: 0.000 seconds
11438 19:25:14.970347 <6>[ 26.977783] Freezing user space processes
11439 19:25:14.981082 <6>[ 26.983499] Freezing user space processes completed (elapsed 0.001 seconds)
11440 19:25:14.984783 <6>[ 26.990724] OOM killer disabled.
11441 19:25:14.987670 <6>[ 26.994206] Freezing remaining freezable tasks
11442 19:25:14.998404 <6>[ 27.000090] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11443 19:25:15.004653 <6>[ 27.007749] printk: Suspending console(s) (use no_console_suspend to debug)
11444 19:25:20.732579 <6>[ 27.085270] Disabling non-boot CPUs ...
11445 19:25:20.735764 <6>[ 27.086252] psci: CPU1 killed (polled 0 ms)
11446 19:25:20.739312 <6>[ 27.088283] psci: CPU2 killed (polled 4 ms)
11447 19:25:20.746004 <6>[ 27.090294] psci: CPU3 killed (polled 0 ms)
11448 19:25:20.749473 <6>[ 27.090865] psci: CPU4 killed (polled 0 ms)
11449 19:25:20.752451 <6>[ 27.091439] psci: CPU5 killed (polled 0 ms)
11450 19:25:20.759069 <6>[ 27.092028] psci: CPU6 killed (polled 0 ms)
11451 19:25:20.762283 <6>[ 27.092563] psci: CPU7 killed (polled 0 ms)
11452 19:25:20.765659 <6>[ 27.092871] Enabling non-boot CPUs ...
11453 19:25:20.772481 <6>[ 27.093093] Detected VIPT I-cache on CPU1
11454 19:25:20.778878 <6>[ 27.093176] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11455 19:25:20.785309 <6>[ 27.093234] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11456 19:25:20.789109 <6>[ 27.093863] CPU1 is up
11457 19:25:20.792325 <6>[ 27.093998] Detected VIPT I-cache on CPU2
11458 19:25:20.798739 <6>[ 27.094052] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11459 19:25:20.805823 <6>[ 27.094088] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11460 19:25:20.808613 <6>[ 27.094591] CPU2 is up
11461 19:25:20.812004 <6>[ 27.094726] Detected VIPT I-cache on CPU3
11462 19:25:20.818751 <6>[ 27.094782] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11463 19:25:20.828769 <6>[ 27.094818] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11464 19:25:20.829300 <6>[ 27.095323] CPU3 is up
11465 19:25:20.835329 <6>[ 27.095442] Detected PIPT I-cache on CPU4
11466 19:25:20.842094 <6>[ 27.095462] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11467 19:25:20.848537 <6>[ 27.095475] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11468 19:25:20.851537 <6>[ 27.095721] CPU4 is up
11469 19:25:20.855018 <6>[ 27.095840] Detected PIPT I-cache on CPU5
11470 19:25:20.861513 <6>[ 27.095860] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11471 19:25:20.868427 <6>[ 27.095873] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11472 19:25:20.871371 <6>[ 27.096122] CPU5 is up
11473 19:25:20.875083 <6>[ 27.096249] Detected PIPT I-cache on CPU6
11474 19:25:20.881562 <6>[ 27.096269] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11475 19:25:20.891558 <6>[ 27.096282] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11476 19:25:20.892129 <6>[ 27.096504] CPU6 is up
11477 19:25:20.898367 <6>[ 27.096620] Detected PIPT I-cache on CPU7
11478 19:25:20.904894 <6>[ 27.096646] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11479 19:25:20.911351 <6>[ 27.096659] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11480 19:25:20.914557 <6>[ 27.096893] CPU7 is up
11481 19:25:20.917859 <6>[ 27.639928] OOM killer enabled.
11482 19:25:20.921153 <6>[ 27.643317] Restarting tasks ... done.
11483 19:25:20.927732 <5>[ 27.647686] random: crng reseeded on system resumption
11484 19:25:20.931158 <6>[ 27.654938] PM: suspend exit
11485 19:25:20.939740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-6 RESULT=pass>
11486 19:25:20.940511 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-6 RESULT=pass
11488 19:25:20.942735 rtcwake: assuming RTC uses UTC ...
11489 19:25:20.949420 rtcwake: wakeup from "mem" using rtc0 at Thu Apr 18 19:25:26 2024
11490 19:25:20.962969 <6>[ 27.683948] PM: suspend entry (deep)
11491 19:25:20.965735 <6>[ 27.687801] Filesystems sync: 0.000 seconds
11492 19:25:20.969091 <6>[ 27.692522] Freezing user space processes
11493 19:25:20.980099 <6>[ 27.698172] Freezing user space processes completed (elapsed 0.001 seconds)
11494 19:25:20.983129 <6>[ 27.705397] OOM killer disabled.
11495 19:25:20.986412 <6>[ 27.708880] Freezing remaining freezable tasks
11496 19:25:20.996806 <6>[ 27.714779] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11497 19:25:21.003316 <6>[ 27.722444] printk: Suspending console(s) (use no_console_suspend to debug)
11498 19:25:26.722948 <6>[ 27.795974] Disabling non-boot CPUs ...
11499 19:25:26.726402 <6>[ 27.796721] psci: CPU1 killed (polled 0 ms)
11500 19:25:26.729350 <6>[ 27.797342] psci: CPU2 killed (polled 0 ms)
11501 19:25:26.736265 <6>[ 27.799053] psci: CPU3 killed (polled 0 ms)
11502 19:25:26.739694 <6>[ 27.799510] psci: CPU4 killed (polled 0 ms)
11503 19:25:26.742843 <6>[ 27.800024] psci: CPU5 killed (polled 0 ms)
11504 19:25:26.749392 <6>[ 27.800503] psci: CPU6 killed (polled 0 ms)
11505 19:25:26.752802 <6>[ 27.801012] psci: CPU7 killed (polled 0 ms)
11506 19:25:26.756122 <6>[ 27.801294] Enabling non-boot CPUs ...
11507 19:25:26.763291 <6>[ 27.801484] Detected VIPT I-cache on CPU1
11508 19:25:26.769525 <6>[ 27.801548] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11509 19:25:26.776125 <6>[ 27.801596] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11510 19:25:26.779479 <6>[ 27.802066] CPU1 is up
11511 19:25:26.782791 <6>[ 27.802173] Detected VIPT I-cache on CPU2
11512 19:25:26.789320 <6>[ 27.802212] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11513 19:25:26.795725 <6>[ 27.802238] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11514 19:25:26.799298 <6>[ 27.802585] CPU2 is up
11515 19:25:26.802361 <6>[ 27.802686] Detected VIPT I-cache on CPU3
11516 19:25:26.809202 <6>[ 27.802726] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11517 19:25:26.815584 <6>[ 27.802751] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11518 19:25:26.819502 <6>[ 27.803102] CPU3 is up
11519 19:25:26.825823 <6>[ 27.803205] Detected PIPT I-cache on CPU4
11520 19:25:26.832259 <6>[ 27.803225] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11521 19:25:26.839109 <6>[ 27.803238] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11522 19:25:26.842412 <6>[ 27.803466] CPU4 is up
11523 19:25:26.845977 <6>[ 27.803577] Detected PIPT I-cache on CPU5
11524 19:25:26.852329 <6>[ 27.803597] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11525 19:25:26.858955 <6>[ 27.803610] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11526 19:25:26.862362 <6>[ 27.803821] CPU5 is up
11527 19:25:26.865642 <6>[ 27.803961] Detected PIPT I-cache on CPU6
11528 19:25:26.871939 <6>[ 27.803981] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11529 19:25:26.878635 <6>[ 27.803994] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11530 19:25:26.882125 <6>[ 27.804204] CPU6 is up
11531 19:25:26.888762 <6>[ 27.804311] Detected PIPT I-cache on CPU7
11532 19:25:26.895301 <6>[ 27.804337] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11533 19:25:26.901699 <6>[ 27.804350] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11534 19:25:26.905208 <6>[ 27.804580] CPU7 is up
11535 19:25:26.908530 <6>[ 28.339566] OOM killer enabled.
11536 19:25:26.911994 <6>[ 28.342957] Restarting tasks ... done.
11537 19:25:26.918385 <5>[ 28.347284] random: crng reseeded on system resumption
11538 19:25:26.922191 <6>[ 28.353799] PM: suspend exit
11539 19:25:26.930223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-7 RESULT=pass>
11540 19:25:26.931099 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-7 RESULT=pass
11542 19:25:26.934212 rtcwake: assuming RTC uses UTC ...
11543 19:25:26.939673 rtcwake: wakeup from "mem" using rtc0 at Thu Apr 18 19:25:32 2024
11544 19:25:26.953008 <6>[ 28.383741] PM: suspend entry (deep)
11545 19:25:26.956416 <6>[ 28.387601] Filesystems sync: 0.000 seconds
11546 19:25:26.959723 <6>[ 28.392351] Freezing user space processes
11547 19:25:26.970472 <6>[ 28.397961] Freezing user space processes completed (elapsed 0.001 seconds)
11548 19:25:26.973738 <6>[ 28.405187] OOM killer disabled.
11549 19:25:26.977196 <6>[ 28.408675] Freezing remaining freezable tasks
11550 19:25:26.987353 <6>[ 28.414588] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11551 19:25:26.993515 <6>[ 28.422254] printk: Suspending console(s) (use no_console_suspend to debug)
11552 19:25:32.729982 <6>[ 28.494639] Disabling non-boot CPUs ...
11553 19:25:32.733230 <4>[ 28.495375] migrate_one_irq: 88 callbacks suppressed
11554 19:25:32.739832 <4>[ 28.495386] IRQ282: set affinity failed(-22).
11555 19:25:32.743150 <4>[ 28.495393] IRQ284: set affinity failed(-22).
11556 19:25:32.746213 <6>[ 28.495465] psci: CPU1 killed (polled 0 ms)
11557 19:25:32.753228 <4>[ 28.496461] IRQ282: set affinity failed(-22).
11558 19:25:32.756548 <4>[ 28.496470] IRQ284: set affinity failed(-22).
11559 19:25:32.763139 <6>[ 28.497524] psci: CPU2 killed (polled 0 ms)
11560 19:25:32.766288 <4>[ 28.498219] IRQ282: set affinity failed(-22).
11561 19:25:32.770101 <4>[ 28.498229] IRQ284: set affinity failed(-22).
11562 19:25:32.776798 <6>[ 28.499281] psci: CPU3 killed (polled 0 ms)
11563 19:25:32.779856 <4>[ 28.499728] IRQ282: set affinity failed(-22).
11564 19:25:32.782977 <4>[ 28.499731] IRQ284: set affinity failed(-22).
11565 19:25:32.789764 <6>[ 28.499759] psci: CPU4 killed (polled 0 ms)
11566 19:25:32.793129 <4>[ 28.500285] IRQ282: set affinity failed(-22).
11567 19:25:32.799641 <4>[ 28.500290] IRQ284: set affinity failed(-22).
11568 19:25:32.802940 <6>[ 28.500339] psci: CPU5 killed (polled 0 ms)
11569 19:25:32.806740 <6>[ 28.500882] psci: CPU6 killed (polled 0 ms)
11570 19:25:32.813185 <6>[ 28.501365] psci: CPU7 killed (polled 0 ms)
11571 19:25:32.815982 <6>[ 28.501649] Enabling non-boot CPUs ...
11572 19:25:32.819554 <6>[ 28.501850] Detected VIPT I-cache on CPU1
11573 19:25:32.825938 <6>[ 28.501921] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11574 19:25:32.832924 <6>[ 28.501973] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11575 19:25:32.835793 <6>[ 28.502499] CPU1 is up
11576 19:25:32.839058 <6>[ 28.502616] Detected VIPT I-cache on CPU2
11577 19:25:32.849258 <6>[ 28.502661] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11578 19:25:32.856046 <6>[ 28.502691] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11579 19:25:32.856623 <6>[ 28.503103] CPU2 is up
11580 19:25:32.862610 <6>[ 28.503218] Detected VIPT I-cache on CPU3
11581 19:25:32.869070 <6>[ 28.503264] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11582 19:25:32.875795 <6>[ 28.503294] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11583 19:25:32.878637 <6>[ 28.503697] CPU3 is up
11584 19:25:32.882299 <6>[ 28.503806] Detected PIPT I-cache on CPU4
11585 19:25:32.889122 <6>[ 28.503826] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11586 19:25:32.895403 <6>[ 28.503838] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11587 19:25:32.899400 <6>[ 28.504107] CPU4 is up
11588 19:25:32.902625 <6>[ 28.504223] Detected PIPT I-cache on CPU5
11589 19:25:32.912425 <6>[ 28.504243] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11590 19:25:32.918738 <6>[ 28.504256] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11591 19:25:32.919321 <6>[ 28.504473] CPU5 is up
11592 19:25:32.925368 <6>[ 28.504581] Detected PIPT I-cache on CPU6
11593 19:25:32.931793 <6>[ 28.504602] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11594 19:25:32.938484 <6>[ 28.504614] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11595 19:25:32.941730 <6>[ 28.504836] CPU6 is up
11596 19:25:32.945060 <6>[ 28.504941] Detected PIPT I-cache on CPU7
11597 19:25:32.952031 <6>[ 28.504968] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11598 19:25:32.958513 <6>[ 28.504980] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11599 19:25:32.961718 <6>[ 28.505211] CPU7 is up
11600 19:25:32.965257 <6>[ 29.099100] OOM killer enabled.
11601 19:25:32.968659 <6>[ 29.102492] Restarting tasks ... done.
11602 19:25:32.975126 <5>[ 29.106807] random: crng reseeded on system resumption
11603 19:25:32.978402 <6>[ 29.113811] PM: suspend exit
11604 19:25:32.988857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-8 RESULT=pass>
11605 19:25:32.989752 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-8 RESULT=pass
11607 19:25:32.991715 rtcwake: assuming RTC uses UTC ...
11608 19:25:32.998604 rtcwake: wakeup from "mem" using rtc0 at Thu Apr 18 19:25:38 2024
11609 19:25:33.011403 <6>[ 29.143471] PM: suspend entry (deep)
11610 19:25:33.014814 <6>[ 29.147333] Filesystems sync: 0.000 seconds
11611 19:25:33.018111 <6>[ 29.152051] Freezing user space processes
11612 19:25:33.028803 <6>[ 29.157641] Freezing user space processes completed (elapsed 0.001 seconds)
11613 19:25:33.032303 <6>[ 29.164871] OOM killer disabled.
11614 19:25:33.035552 <6>[ 29.168354] Freezing remaining freezable tasks
11615 19:25:33.045260 <6>[ 29.174252] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11616 19:25:33.051986 <6>[ 29.181918] printk: Suspending console(s) (use no_console_suspend to debug)
11617 19:25:38.724466 <6>[ 29.255289] Disabling non-boot CPUs ...
11618 19:25:38.727774 <6>[ 29.256099] psci: CPU1 killed (polled 0 ms)
11619 19:25:38.731000 <6>[ 29.257946] psci: CPU2 killed (polled 0 ms)
11620 19:25:38.737978 <6>[ 29.259609] psci: CPU3 killed (polled 0 ms)
11621 19:25:38.741133 <6>[ 29.260164] psci: CPU4 killed (polled 0 ms)
11622 19:25:38.744303 <6>[ 29.260668] psci: CPU5 killed (polled 0 ms)
11623 19:25:38.750981 <6>[ 29.261147] psci: CPU6 killed (polled 0 ms)
11624 19:25:38.754208 <6>[ 29.261617] psci: CPU7 killed (polled 0 ms)
11625 19:25:38.757266 <6>[ 29.261891] Enabling non-boot CPUs ...
11626 19:25:38.764281 <6>[ 29.262085] Detected VIPT I-cache on CPU1
11627 19:25:38.770692 <6>[ 29.262154] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11628 19:25:38.777312 <6>[ 29.262203] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11629 19:25:38.780849 <6>[ 29.262704] CPU1 is up
11630 19:25:38.784370 <6>[ 29.262813] Detected VIPT I-cache on CPU2
11631 19:25:38.790513 <6>[ 29.262855] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11632 19:25:38.797069 <6>[ 29.262883] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11633 19:25:38.800492 <6>[ 29.263257] CPU2 is up
11634 19:25:38.804432 <6>[ 29.263368] Detected VIPT I-cache on CPU3
11635 19:25:38.813746 <6>[ 29.263411] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11636 19:25:38.820621 <6>[ 29.263438] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11637 19:25:38.821204 <6>[ 29.263835] CPU3 is up
11638 19:25:38.827121 <6>[ 29.263941] Detected PIPT I-cache on CPU4
11639 19:25:38.833636 <6>[ 29.263961] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11640 19:25:38.840269 <6>[ 29.263974] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11641 19:25:38.843577 <6>[ 29.264228] CPU4 is up
11642 19:25:38.847030 <6>[ 29.264331] Detected PIPT I-cache on CPU5
11643 19:25:38.853537 <6>[ 29.264351] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11644 19:25:38.860143 <6>[ 29.264364] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11645 19:25:38.863224 <6>[ 29.264570] CPU5 is up
11646 19:25:38.866532 <6>[ 29.264680] Detected PIPT I-cache on CPU6
11647 19:25:38.873318 <6>[ 29.264700] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11648 19:25:38.883372 <6>[ 29.264712] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11649 19:25:38.883973 <6>[ 29.264920] CPU6 is up
11650 19:25:38.889854 <6>[ 29.265022] Detected PIPT I-cache on CPU7
11651 19:25:38.896403 <6>[ 29.265047] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11652 19:25:38.903320 <6>[ 29.265060] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11653 19:25:38.906456 <6>[ 29.265289] CPU7 is up
11654 19:25:38.909913 <6>[ 29.803464] OOM killer enabled.
11655 19:25:38.913557 <6>[ 29.806855] Restarting tasks ... done.
11656 19:25:38.919701 <5>[ 29.811192] random: crng reseeded on system resumption
11657 19:25:38.923003 <6>[ 29.818376] PM: suspend exit
11658 19:25:38.933398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-9 RESULT=pass>
11659 19:25:38.934279 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-9 RESULT=pass
11661 19:25:38.936815 rtcwake: assuming RTC uses UTC ...
11662 19:25:38.943102 rtcwake: wakeup from "mem" using rtc0 at Thu Apr 18 19:25:44 2024
11663 19:25:38.956642 <6>[ 29.849720] PM: suspend entry (deep)
11664 19:25:38.959938 <6>[ 29.853584] Filesystems sync: 0.000 seconds
11665 19:25:38.963715 <6>[ 29.858308] Freezing user space processes
11666 19:25:38.974060 <6>[ 29.863981] Freezing user space processes completed (elapsed 0.001 seconds)
11667 19:25:38.977143 <6>[ 29.871197] OOM killer disabled.
11668 19:25:38.980813 <6>[ 29.874678] Freezing remaining freezable tasks
11669 19:25:38.990912 <6>[ 29.880499] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11670 19:25:38.997251 <6>[ 29.888154] printk: Suspending console(s) (use no_console_suspend to debug)
11671 19:25:44.731755 <6>[ 29.967443] Disabling non-boot CPUs ...
11672 19:25:44.734961 <6>[ 29.968470] psci: CPU1 killed (polled 0 ms)
11673 19:25:44.738443 <6>[ 29.969640] psci: CPU2 killed (polled 0 ms)
11674 19:25:44.745056 <6>[ 29.971503] psci: CPU3 killed (polled 0 ms)
11675 19:25:44.748647 <6>[ 29.972010] psci: CPU4 killed (polled 0 ms)
11676 19:25:44.751636 <6>[ 29.972648] psci: CPU5 killed (polled 0 ms)
11677 19:25:44.758618 <6>[ 29.973202] psci: CPU6 killed (polled 0 ms)
11678 19:25:44.761809 <6>[ 29.973741] psci: CPU7 killed (polled 0 ms)
11679 19:25:44.765018 <6>[ 29.974049] Enabling non-boot CPUs ...
11680 19:25:44.771881 <6>[ 29.974273] Detected VIPT I-cache on CPU1
11681 19:25:44.778579 <6>[ 29.974354] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11682 19:25:44.784920 <6>[ 29.974412] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11683 19:25:44.788174 <6>[ 29.975040] CPU1 is up
11684 19:25:44.791700 <6>[ 29.975176] Detected VIPT I-cache on CPU2
11685 19:25:44.797941 <6>[ 29.975231] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11686 19:25:44.804913 <6>[ 29.975268] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11687 19:25:44.807881 <6>[ 29.975815] CPU2 is up
11688 19:25:44.811209 <6>[ 29.975953] Detected VIPT I-cache on CPU3
11689 19:25:44.817899 <6>[ 29.976008] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11690 19:25:44.827965 <6>[ 29.976044] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11691 19:25:44.828549 <6>[ 29.976543] CPU3 is up
11692 19:25:44.834604 <6>[ 29.976662] Detected PIPT I-cache on CPU4
11693 19:25:44.841266 <6>[ 29.976683] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11694 19:25:44.847477 <6>[ 29.976696] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11695 19:25:44.851378 <6>[ 29.976968] CPU4 is up
11696 19:25:44.854319 <6>[ 29.977097] Detected PIPT I-cache on CPU5
11697 19:25:44.860911 <6>[ 29.977117] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11698 19:25:44.867423 <6>[ 29.977130] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11699 19:25:44.870805 <6>[ 29.977350] CPU5 is up
11700 19:25:44.874447 <6>[ 29.977467] Detected PIPT I-cache on CPU6
11701 19:25:44.883828 <6>[ 29.977487] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11702 19:25:44.890615 <6>[ 29.977500] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11703 19:25:44.891297 <6>[ 29.977719] CPU6 is up
11704 19:25:44.897297 <6>[ 29.977836] Detected PIPT I-cache on CPU7
11705 19:25:44.904173 <6>[ 29.977862] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11706 19:25:44.910683 <6>[ 29.977874] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11707 19:25:44.914198 <6>[ 29.978109] CPU7 is up
11708 19:25:44.917434 <6>[ 30.523949] OOM killer enabled.
11709 19:25:44.920686 <6>[ 30.527338] Restarting tasks ... done.
11710 19:25:44.927001 <5>[ 30.531669] random: crng reseeded on system resumption
11711 19:25:44.930511 <6>[ 30.538161] PM: suspend exit
11712 19:25:44.937384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-10 RESULT=pass>
11713 19:25:44.937964 + set +x
11714 19:25:44.938839 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-10 RESULT=pass
11716 19:25:44.943943 <LAVA_SIGNAL_ENDRUN 0_sleep 13420363_1.5.2.3.1>
11717 19:25:44.944431 <LAVA_TEST_RUNNER EXIT>
11718 19:25:44.945196 Received signal: <ENDRUN> 0_sleep 13420363_1.5.2.3.1
11719 19:25:44.945679 Ending use of test pattern.
11720 19:25:44.946140 Ending test lava.0_sleep (13420363_1.5.2.3.1), duration 60.03
11722 19:25:44.947625 ok: lava_test_shell seems to have completed
11723 19:25:44.948518 rtc-exist: pass
rtc-wakeup-enabled: pass
rtcwake-mem-1: pass
rtcwake-mem-10: pass
rtcwake-mem-2: pass
rtcwake-mem-3: pass
rtcwake-mem-4: pass
rtcwake-mem-5: pass
rtcwake-mem-6: pass
rtcwake-mem-7: pass
rtcwake-mem-8: pass
rtcwake-mem-9: pass
11724 19:25:44.949047 end: 3.1 lava-test-shell (duration 00:01:00) [common]
11725 19:25:44.949596 end: 3 lava-test-retry (duration 00:01:00) [common]
11726 19:25:44.950209 start: 4 finalize (timeout 00:06:12) [common]
11727 19:25:44.950791 start: 4.1 power-off (timeout 00:00:30) [common]
11728 19:25:44.951702 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=off'
11729 19:25:45.077680 >> Command sent successfully.
11730 19:25:45.081551 Returned 0 in 0 seconds
11731 19:25:45.182540 end: 4.1 power-off (duration 00:00:00) [common]
11733 19:25:45.184248 start: 4.2 read-feedback (timeout 00:06:12) [common]
11734 19:25:45.185604 Listened to connection for namespace 'common' for up to 1s
11735 19:25:46.186304 Finalising connection for namespace 'common'
11736 19:25:46.187059 Disconnecting from shell: Finalise
11737 19:25:46.187581 / #
11738 19:25:46.288785 end: 4.2 read-feedback (duration 00:00:01) [common]
11739 19:25:46.289529 end: 4 finalize (duration 00:00:01) [common]
11740 19:25:46.290331 Cleaning after the job
11741 19:25:46.290911 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13420363/tftp-deploy-v5h0r7fo/ramdisk
11742 19:25:46.304256 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13420363/tftp-deploy-v5h0r7fo/kernel
11743 19:25:46.323897 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13420363/tftp-deploy-v5h0r7fo/dtb
11744 19:25:46.324127 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13420363/tftp-deploy-v5h0r7fo/modules
11745 19:25:46.329860 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/13420363
11746 19:25:46.485278 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/13420363
11747 19:25:46.485465 Job finished correctly