Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 25
- Errors: 0
- Kernel Errors: 39
- Boot result: PASS
1 22:53:08.177015 lava-dispatcher, installed at version: 2024.01
2 22:53:08.177218 start: 0 validate
3 22:53:08.177385 Start time: 2024-05-07 22:53:08.177378+00:00 (UTC)
4 22:53:08.177527 Using caching service: 'http://localhost/cache/?uri=%s'
5 22:53:08.177655 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 22:53:08.431157 Using caching service: 'http://localhost/cache/?uri=%s'
7 22:53:08.431778 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.90-cip20%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 22:53:08.692056 Using caching service: 'http://localhost/cache/?uri=%s'
9 22:53:08.692222 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.90-cip20%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 22:53:08.942333 Using caching service: 'http://localhost/cache/?uri=%s'
11 22:53:08.942516 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 22:53:09.199653 Using caching service: 'http://localhost/cache/?uri=%s'
13 22:53:09.199876 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.90-cip20%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 22:53:09.460166 validate duration: 1.28
16 22:53:09.460420 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 22:53:09.460512 start: 1.1 download-retry (timeout 00:10:00) [common]
18 22:53:09.460594 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 22:53:09.460712 Not decompressing ramdisk as can be used compressed.
20 22:53:09.460794 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 22:53:09.460856 saving as /var/lib/lava/dispatcher/tmp/13683732/tftp-deploy-ew_mgp1_/ramdisk/initrd.cpio.gz
22 22:53:09.460922 total size: 5628169 (5 MB)
23 22:53:09.462014 progress 0 % (0 MB)
24 22:53:09.463728 progress 5 % (0 MB)
25 22:53:09.465324 progress 10 % (0 MB)
26 22:53:09.466725 progress 15 % (0 MB)
27 22:53:09.468299 progress 20 % (1 MB)
28 22:53:09.469744 progress 25 % (1 MB)
29 22:53:09.471278 progress 30 % (1 MB)
30 22:53:09.472802 progress 35 % (1 MB)
31 22:53:09.474201 progress 40 % (2 MB)
32 22:53:09.475732 progress 45 % (2 MB)
33 22:53:09.477086 progress 50 % (2 MB)
34 22:53:09.478604 progress 55 % (2 MB)
35 22:53:09.480107 progress 60 % (3 MB)
36 22:53:09.481481 progress 65 % (3 MB)
37 22:53:09.483003 progress 70 % (3 MB)
38 22:53:09.484382 progress 75 % (4 MB)
39 22:53:09.485940 progress 80 % (4 MB)
40 22:53:09.487290 progress 85 % (4 MB)
41 22:53:09.488817 progress 90 % (4 MB)
42 22:53:09.490443 progress 95 % (5 MB)
43 22:53:09.491864 progress 100 % (5 MB)
44 22:53:09.492072 5 MB downloaded in 0.03 s (172.32 MB/s)
45 22:53:09.492228 end: 1.1.1 http-download (duration 00:00:00) [common]
47 22:53:09.492469 end: 1.1 download-retry (duration 00:00:00) [common]
48 22:53:09.492554 start: 1.2 download-retry (timeout 00:10:00) [common]
49 22:53:09.492636 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 22:53:09.492766 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.90-cip20/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 22:53:09.492834 saving as /var/lib/lava/dispatcher/tmp/13683732/tftp-deploy-ew_mgp1_/kernel/Image
52 22:53:09.492897 total size: 54682112 (52 MB)
53 22:53:09.492958 No compression specified
54 22:53:09.494061 progress 0 % (0 MB)
55 22:53:09.507717 progress 5 % (2 MB)
56 22:53:09.521256 progress 10 % (5 MB)
57 22:53:09.535260 progress 15 % (7 MB)
58 22:53:09.549017 progress 20 % (10 MB)
59 22:53:09.563052 progress 25 % (13 MB)
60 22:53:09.576765 progress 30 % (15 MB)
61 22:53:09.590722 progress 35 % (18 MB)
62 22:53:09.604330 progress 40 % (20 MB)
63 22:53:09.617966 progress 45 % (23 MB)
64 22:53:09.632012 progress 50 % (26 MB)
65 22:53:09.645883 progress 55 % (28 MB)
66 22:53:09.659751 progress 60 % (31 MB)
67 22:53:09.673474 progress 65 % (33 MB)
68 22:53:09.687484 progress 70 % (36 MB)
69 22:53:09.701679 progress 75 % (39 MB)
70 22:53:09.715425 progress 80 % (41 MB)
71 22:53:09.729077 progress 85 % (44 MB)
72 22:53:09.742678 progress 90 % (46 MB)
73 22:53:09.756332 progress 95 % (49 MB)
74 22:53:09.769811 progress 100 % (52 MB)
75 22:53:09.770045 52 MB downloaded in 0.28 s (188.17 MB/s)
76 22:53:09.770197 end: 1.2.1 http-download (duration 00:00:00) [common]
78 22:53:09.770431 end: 1.2 download-retry (duration 00:00:00) [common]
79 22:53:09.770515 start: 1.3 download-retry (timeout 00:10:00) [common]
80 22:53:09.770599 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 22:53:09.770733 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.90-cip20/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 22:53:09.770800 saving as /var/lib/lava/dispatcher/tmp/13683732/tftp-deploy-ew_mgp1_/dtb/mt8192-asurada-spherion-r0.dtb
83 22:53:09.770860 total size: 47258 (0 MB)
84 22:53:09.770920 No compression specified
85 22:53:09.772021 progress 69 % (0 MB)
86 22:53:09.772290 progress 100 % (0 MB)
87 22:53:09.772442 0 MB downloaded in 0.00 s (28.53 MB/s)
88 22:53:09.772562 end: 1.3.1 http-download (duration 00:00:00) [common]
90 22:53:09.772777 end: 1.3 download-retry (duration 00:00:00) [common]
91 22:53:09.772898 start: 1.4 download-retry (timeout 00:10:00) [common]
92 22:53:09.772980 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 22:53:09.773090 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 22:53:09.773157 saving as /var/lib/lava/dispatcher/tmp/13683732/tftp-deploy-ew_mgp1_/nfsrootfs/full.rootfs.tar
95 22:53:09.773217 total size: 120894716 (115 MB)
96 22:53:09.773277 Using unxz to decompress xz
97 22:53:09.777414 progress 0 % (0 MB)
98 22:53:10.128333 progress 5 % (5 MB)
99 22:53:10.483266 progress 10 % (11 MB)
100 22:53:10.829856 progress 15 % (17 MB)
101 22:53:11.159697 progress 20 % (23 MB)
102 22:53:11.457691 progress 25 % (28 MB)
103 22:53:11.818056 progress 30 % (34 MB)
104 22:53:12.160063 progress 35 % (40 MB)
105 22:53:12.328746 progress 40 % (46 MB)
106 22:53:12.509416 progress 45 % (51 MB)
107 22:53:12.825154 progress 50 % (57 MB)
108 22:53:13.200650 progress 55 % (63 MB)
109 22:53:13.549308 progress 60 % (69 MB)
110 22:53:13.894883 progress 65 % (74 MB)
111 22:53:14.240179 progress 70 % (80 MB)
112 22:53:14.593975 progress 75 % (86 MB)
113 22:53:14.933013 progress 80 % (92 MB)
114 22:53:15.270510 progress 85 % (98 MB)
115 22:53:15.625742 progress 90 % (103 MB)
116 22:53:15.955039 progress 95 % (109 MB)
117 22:53:16.310533 progress 100 % (115 MB)
118 22:53:16.315874 115 MB downloaded in 6.54 s (17.62 MB/s)
119 22:53:16.316137 end: 1.4.1 http-download (duration 00:00:07) [common]
121 22:53:16.316401 end: 1.4 download-retry (duration 00:00:07) [common]
122 22:53:16.316489 start: 1.5 download-retry (timeout 00:09:53) [common]
123 22:53:16.316576 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 22:53:16.316712 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.90-cip20/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 22:53:16.316782 saving as /var/lib/lava/dispatcher/tmp/13683732/tftp-deploy-ew_mgp1_/modules/modules.tar
126 22:53:16.316842 total size: 8594396 (8 MB)
127 22:53:16.316906 Using unxz to decompress xz
128 22:53:16.320982 progress 0 % (0 MB)
129 22:53:16.339940 progress 5 % (0 MB)
130 22:53:16.364487 progress 10 % (0 MB)
131 22:53:16.388115 progress 15 % (1 MB)
132 22:53:16.411490 progress 20 % (1 MB)
133 22:53:16.436363 progress 25 % (2 MB)
134 22:53:16.460041 progress 30 % (2 MB)
135 22:53:16.483624 progress 35 % (2 MB)
136 22:53:16.508430 progress 40 % (3 MB)
137 22:53:16.533793 progress 45 % (3 MB)
138 22:53:16.558890 progress 50 % (4 MB)
139 22:53:16.584297 progress 55 % (4 MB)
140 22:53:16.610410 progress 60 % (4 MB)
141 22:53:16.635337 progress 65 % (5 MB)
142 22:53:16.660450 progress 70 % (5 MB)
143 22:53:16.685981 progress 75 % (6 MB)
144 22:53:16.711788 progress 80 % (6 MB)
145 22:53:16.737475 progress 85 % (6 MB)
146 22:53:16.766258 progress 90 % (7 MB)
147 22:53:16.795254 progress 95 % (7 MB)
148 22:53:16.821240 progress 100 % (8 MB)
149 22:53:16.826395 8 MB downloaded in 0.51 s (16.09 MB/s)
150 22:53:16.826638 end: 1.5.1 http-download (duration 00:00:01) [common]
152 22:53:16.826906 end: 1.5 download-retry (duration 00:00:01) [common]
153 22:53:16.826999 start: 1.6 prepare-tftp-overlay (timeout 00:09:53) [common]
154 22:53:16.827094 start: 1.6.1 extract-nfsrootfs (timeout 00:09:53) [common]
155 22:53:20.375746 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/13683732/extract-nfsrootfs-j2ki1x35
156 22:53:20.375947 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 22:53:20.376052 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 22:53:20.376215 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/13683732/lava-overlay-a7l9t264
159 22:53:20.376345 makedir: /var/lib/lava/dispatcher/tmp/13683732/lava-overlay-a7l9t264/lava-13683732/bin
160 22:53:20.376445 makedir: /var/lib/lava/dispatcher/tmp/13683732/lava-overlay-a7l9t264/lava-13683732/tests
161 22:53:20.376546 makedir: /var/lib/lava/dispatcher/tmp/13683732/lava-overlay-a7l9t264/lava-13683732/results
162 22:53:20.376648 Creating /var/lib/lava/dispatcher/tmp/13683732/lava-overlay-a7l9t264/lava-13683732/bin/lava-add-keys
163 22:53:20.376807 Creating /var/lib/lava/dispatcher/tmp/13683732/lava-overlay-a7l9t264/lava-13683732/bin/lava-add-sources
164 22:53:20.376948 Creating /var/lib/lava/dispatcher/tmp/13683732/lava-overlay-a7l9t264/lava-13683732/bin/lava-background-process-start
165 22:53:20.377071 Creating /var/lib/lava/dispatcher/tmp/13683732/lava-overlay-a7l9t264/lava-13683732/bin/lava-background-process-stop
166 22:53:20.377194 Creating /var/lib/lava/dispatcher/tmp/13683732/lava-overlay-a7l9t264/lava-13683732/bin/lava-common-functions
167 22:53:20.377314 Creating /var/lib/lava/dispatcher/tmp/13683732/lava-overlay-a7l9t264/lava-13683732/bin/lava-echo-ipv4
168 22:53:20.377469 Creating /var/lib/lava/dispatcher/tmp/13683732/lava-overlay-a7l9t264/lava-13683732/bin/lava-install-packages
169 22:53:20.377589 Creating /var/lib/lava/dispatcher/tmp/13683732/lava-overlay-a7l9t264/lava-13683732/bin/lava-installed-packages
170 22:53:20.377709 Creating /var/lib/lava/dispatcher/tmp/13683732/lava-overlay-a7l9t264/lava-13683732/bin/lava-os-build
171 22:53:20.377830 Creating /var/lib/lava/dispatcher/tmp/13683732/lava-overlay-a7l9t264/lava-13683732/bin/lava-probe-channel
172 22:53:20.377951 Creating /var/lib/lava/dispatcher/tmp/13683732/lava-overlay-a7l9t264/lava-13683732/bin/lava-probe-ip
173 22:53:20.378071 Creating /var/lib/lava/dispatcher/tmp/13683732/lava-overlay-a7l9t264/lava-13683732/bin/lava-target-ip
174 22:53:20.378190 Creating /var/lib/lava/dispatcher/tmp/13683732/lava-overlay-a7l9t264/lava-13683732/bin/lava-target-mac
175 22:53:20.378308 Creating /var/lib/lava/dispatcher/tmp/13683732/lava-overlay-a7l9t264/lava-13683732/bin/lava-target-storage
176 22:53:20.378430 Creating /var/lib/lava/dispatcher/tmp/13683732/lava-overlay-a7l9t264/lava-13683732/bin/lava-test-case
177 22:53:20.378550 Creating /var/lib/lava/dispatcher/tmp/13683732/lava-overlay-a7l9t264/lava-13683732/bin/lava-test-event
178 22:53:20.378668 Creating /var/lib/lava/dispatcher/tmp/13683732/lava-overlay-a7l9t264/lava-13683732/bin/lava-test-feedback
179 22:53:20.378788 Creating /var/lib/lava/dispatcher/tmp/13683732/lava-overlay-a7l9t264/lava-13683732/bin/lava-test-raise
180 22:53:20.378907 Creating /var/lib/lava/dispatcher/tmp/13683732/lava-overlay-a7l9t264/lava-13683732/bin/lava-test-reference
181 22:53:20.379026 Creating /var/lib/lava/dispatcher/tmp/13683732/lava-overlay-a7l9t264/lava-13683732/bin/lava-test-runner
182 22:53:20.379146 Creating /var/lib/lava/dispatcher/tmp/13683732/lava-overlay-a7l9t264/lava-13683732/bin/lava-test-set
183 22:53:20.379264 Creating /var/lib/lava/dispatcher/tmp/13683732/lava-overlay-a7l9t264/lava-13683732/bin/lava-test-shell
184 22:53:20.379385 Updating /var/lib/lava/dispatcher/tmp/13683732/lava-overlay-a7l9t264/lava-13683732/bin/lava-add-keys (debian)
185 22:53:20.379530 Updating /var/lib/lava/dispatcher/tmp/13683732/lava-overlay-a7l9t264/lava-13683732/bin/lava-add-sources (debian)
186 22:53:20.379680 Updating /var/lib/lava/dispatcher/tmp/13683732/lava-overlay-a7l9t264/lava-13683732/bin/lava-install-packages (debian)
187 22:53:20.379820 Updating /var/lib/lava/dispatcher/tmp/13683732/lava-overlay-a7l9t264/lava-13683732/bin/lava-installed-packages (debian)
188 22:53:20.379961 Updating /var/lib/lava/dispatcher/tmp/13683732/lava-overlay-a7l9t264/lava-13683732/bin/lava-os-build (debian)
189 22:53:20.380078 Creating /var/lib/lava/dispatcher/tmp/13683732/lava-overlay-a7l9t264/lava-13683732/environment
190 22:53:20.380174 LAVA metadata
191 22:53:20.380244 - LAVA_JOB_ID=13683732
192 22:53:20.380305 - LAVA_DISPATCHER_IP=192.168.201.1
193 22:53:20.380402 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
194 22:53:20.380467 skipped lava-vland-overlay
195 22:53:20.380539 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 22:53:20.380616 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
197 22:53:20.380675 skipped lava-multinode-overlay
198 22:53:20.380745 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 22:53:20.380821 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
200 22:53:20.380892 Loading test definitions
201 22:53:20.380977 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
202 22:53:20.381044 Using /lava-13683732 at stage 0
203 22:53:20.381321 uuid=13683732_1.6.2.3.1 testdef=None
204 22:53:20.381439 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 22:53:20.381521 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
206 22:53:20.381960 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 22:53:20.382178 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
209 22:53:20.382718 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 22:53:20.382943 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
212 22:53:20.383466 runner path: /var/lib/lava/dispatcher/tmp/13683732/lava-overlay-a7l9t264/lava-13683732/0/tests/0_timesync-off test_uuid 13683732_1.6.2.3.1
213 22:53:20.383618 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 22:53:20.383838 start: 1.6.2.3.5 git-repo-action (timeout 00:09:49) [common]
216 22:53:20.383907 Using /lava-13683732 at stage 0
217 22:53:20.384000 Fetching tests from https://github.com/kernelci/test-definitions.git
218 22:53:20.384082 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/13683732/lava-overlay-a7l9t264/lava-13683732/0/tests/1_kselftest-dt'
219 22:53:22.223078 Running '/usr/bin/git checkout kernelci.org
220 22:53:22.366800 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/13683732/lava-overlay-a7l9t264/lava-13683732/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
221 22:53:22.367534 uuid=13683732_1.6.2.3.5 testdef=None
222 22:53:22.367697 end: 1.6.2.3.5 git-repo-action (duration 00:00:02) [common]
224 22:53:22.367944 start: 1.6.2.3.6 test-overlay (timeout 00:09:47) [common]
225 22:53:22.368820 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 22:53:22.369097 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:47) [common]
228 22:53:22.370132 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 22:53:22.370374 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:47) [common]
231 22:53:22.371391 runner path: /var/lib/lava/dispatcher/tmp/13683732/lava-overlay-a7l9t264/lava-13683732/0/tests/1_kselftest-dt test_uuid 13683732_1.6.2.3.5
232 22:53:22.371496 BOARD='mt8192-asurada-spherion-r0'
233 22:53:22.371590 BRANCH='cip'
234 22:53:22.371663 SKIPFILE='/dev/null'
235 22:53:22.371737 SKIP_INSTALL='True'
236 22:53:22.371824 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.90-cip20/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 22:53:22.371914 TST_CASENAME=''
238 22:53:22.371972 TST_CMDFILES='dt'
239 22:53:22.372122 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 22:53:22.372343 Creating lava-test-runner.conf files
242 22:53:22.372404 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/13683732/lava-overlay-a7l9t264/lava-13683732/0 for stage 0
243 22:53:22.372495 - 0_timesync-off
244 22:53:22.372562 - 1_kselftest-dt
245 22:53:22.372655 end: 1.6.2.3 test-definition (duration 00:00:02) [common]
246 22:53:22.372742 start: 1.6.2.4 compress-overlay (timeout 00:09:47) [common]
247 22:53:29.837135 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 22:53:29.837294 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:40) [common]
249 22:53:29.837430 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 22:53:29.837528 end: 1.6.2 lava-overlay (duration 00:00:09) [common]
251 22:53:29.837617 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:40) [common]
252 22:53:30.000279 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 22:53:30.000664 start: 1.6.4 extract-modules (timeout 00:09:39) [common]
254 22:53:30.000780 extracting modules file /var/lib/lava/dispatcher/tmp/13683732/tftp-deploy-ew_mgp1_/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13683732/extract-nfsrootfs-j2ki1x35
255 22:53:30.224512 extracting modules file /var/lib/lava/dispatcher/tmp/13683732/tftp-deploy-ew_mgp1_/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13683732/extract-overlay-ramdisk-hh971o4b/ramdisk
256 22:53:30.440041 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 22:53:30.440206 start: 1.6.5 apply-overlay-tftp (timeout 00:09:39) [common]
258 22:53:30.440303 [common] Applying overlay to NFS
259 22:53:30.440369 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13683732/compress-overlay-7lqv6rhf/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/13683732/extract-nfsrootfs-j2ki1x35
260 22:53:31.345503 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 22:53:31.345672 start: 1.6.6 configure-preseed-file (timeout 00:09:38) [common]
262 22:53:31.345765 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 22:53:31.345851 start: 1.6.7 compress-ramdisk (timeout 00:09:38) [common]
264 22:53:31.345929 Building ramdisk /var/lib/lava/dispatcher/tmp/13683732/extract-overlay-ramdisk-hh971o4b/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/13683732/extract-overlay-ramdisk-hh971o4b/ramdisk
265 22:53:31.771494 >> 130327 blocks
266 22:53:33.842971 rename /var/lib/lava/dispatcher/tmp/13683732/extract-overlay-ramdisk-hh971o4b/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/13683732/tftp-deploy-ew_mgp1_/ramdisk/ramdisk.cpio.gz
267 22:53:33.843430 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 22:53:33.843547 start: 1.6.8 prepare-kernel (timeout 00:09:36) [common]
269 22:53:33.843655 start: 1.6.8.1 prepare-fit (timeout 00:09:36) [common]
270 22:53:33.843759 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/13683732/tftp-deploy-ew_mgp1_/kernel/Image'
271 22:53:46.748601 Returned 0 in 12 seconds
272 22:53:46.849582 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/13683732/tftp-deploy-ew_mgp1_/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/13683732/tftp-deploy-ew_mgp1_/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/13683732/tftp-deploy-ew_mgp1_/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/13683732/tftp-deploy-ew_mgp1_/kernel/image.itb
273 22:53:47.239107 output: FIT description: Kernel Image image with one or more FDT blobs
274 22:53:47.239478 output: Created: Tue May 7 23:53:47 2024
275 22:53:47.239552 output: Image 0 (kernel-1)
276 22:53:47.239615 output: Description:
277 22:53:47.239677 output: Created: Tue May 7 23:53:47 2024
278 22:53:47.239737 output: Type: Kernel Image
279 22:53:47.239794 output: Compression: lzma compressed
280 22:53:47.239850 output: Data Size: 13059555 Bytes = 12753.47 KiB = 12.45 MiB
281 22:53:47.239909 output: Architecture: AArch64
282 22:53:47.239966 output: OS: Linux
283 22:53:47.240021 output: Load Address: 0x00000000
284 22:53:47.240078 output: Entry Point: 0x00000000
285 22:53:47.240137 output: Hash algo: crc32
286 22:53:47.240194 output: Hash value: 727ee7c6
287 22:53:47.240250 output: Image 1 (fdt-1)
288 22:53:47.240306 output: Description: mt8192-asurada-spherion-r0
289 22:53:47.240358 output: Created: Tue May 7 23:53:47 2024
290 22:53:47.240411 output: Type: Flat Device Tree
291 22:53:47.240462 output: Compression: uncompressed
292 22:53:47.240515 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 22:53:47.240585 output: Architecture: AArch64
294 22:53:47.240644 output: Hash algo: crc32
295 22:53:47.240698 output: Hash value: 0f8e4d2e
296 22:53:47.240750 output: Image 2 (ramdisk-1)
297 22:53:47.240802 output: Description: unavailable
298 22:53:47.240854 output: Created: Tue May 7 23:53:47 2024
299 22:53:47.240906 output: Type: RAMDisk Image
300 22:53:47.240957 output: Compression: Unknown Compression
301 22:53:47.241009 output: Data Size: 18731331 Bytes = 18292.32 KiB = 17.86 MiB
302 22:53:47.241061 output: Architecture: AArch64
303 22:53:47.241113 output: OS: Linux
304 22:53:47.241164 output: Load Address: unavailable
305 22:53:47.241215 output: Entry Point: unavailable
306 22:53:47.241267 output: Hash algo: crc32
307 22:53:47.241318 output: Hash value: b4848525
308 22:53:47.241415 output: Default Configuration: 'conf-1'
309 22:53:47.241467 output: Configuration 0 (conf-1)
310 22:53:47.241525 output: Description: mt8192-asurada-spherion-r0
311 22:53:47.241578 output: Kernel: kernel-1
312 22:53:47.241630 output: Init Ramdisk: ramdisk-1
313 22:53:47.241681 output: FDT: fdt-1
314 22:53:47.241733 output: Loadables: kernel-1
315 22:53:47.241784 output:
316 22:53:47.241986 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 22:53:47.242114 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 22:53:47.242258 end: 1.6 prepare-tftp-overlay (duration 00:00:30) [common]
319 22:53:47.242356 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:22) [common]
320 22:53:47.242442 No LXC device requested
321 22:53:47.242526 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 22:53:47.242653 start: 1.8 deploy-device-env (timeout 00:09:22) [common]
323 22:53:47.242735 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 22:53:47.242807 Checking files for TFTP limit of 4294967296 bytes.
325 22:53:47.243310 end: 1 tftp-deploy (duration 00:00:38) [common]
326 22:53:47.243416 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 22:53:47.243504 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 22:53:47.243633 substitutions:
329 22:53:47.243700 - {DTB}: 13683732/tftp-deploy-ew_mgp1_/dtb/mt8192-asurada-spherion-r0.dtb
330 22:53:47.243765 - {INITRD}: 13683732/tftp-deploy-ew_mgp1_/ramdisk/ramdisk.cpio.gz
331 22:53:47.243823 - {KERNEL}: 13683732/tftp-deploy-ew_mgp1_/kernel/Image
332 22:53:47.243879 - {LAVA_MAC}: None
333 22:53:47.243934 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/13683732/extract-nfsrootfs-j2ki1x35
334 22:53:47.243989 - {NFS_SERVER_IP}: 192.168.201.1
335 22:53:47.244042 - {PRESEED_CONFIG}: None
336 22:53:47.244095 - {PRESEED_LOCAL}: None
337 22:53:47.244148 - {RAMDISK}: 13683732/tftp-deploy-ew_mgp1_/ramdisk/ramdisk.cpio.gz
338 22:53:47.244202 - {ROOT_PART}: None
339 22:53:47.244255 - {ROOT}: None
340 22:53:47.244307 - {SERVER_IP}: 192.168.201.1
341 22:53:47.244360 - {TEE}: None
342 22:53:47.244412 Parsed boot commands:
343 22:53:47.244483 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 22:53:47.244657 Parsed boot commands: tftpboot 192.168.201.1 13683732/tftp-deploy-ew_mgp1_/kernel/image.itb 13683732/tftp-deploy-ew_mgp1_/kernel/cmdline
345 22:53:47.244744 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 22:53:47.244828 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 22:53:47.244916 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 22:53:47.245001 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 22:53:47.245079 Not connected, no need to disconnect.
350 22:53:47.245152 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 22:53:47.245230 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 22:53:47.245296 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
353 22:53:47.249472 Setting prompt string to ['lava-test: # ']
354 22:53:47.249940 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 22:53:47.250124 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 22:53:47.250259 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 22:53:47.250388 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 22:53:47.250675 Calling: '/usr/local/bin/chromebook-reboot.sh' 'mt8192-asurada-spherion-r0-cbg-9'
359 22:54:01.377999 Returned 0 in 14 seconds
360 22:54:01.479263 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
362 22:54:01.480835 end: 2.2.2 reset-device (duration 00:00:14) [common]
363 22:54:01.481393 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
364 22:54:01.481897 Setting prompt string to 'Starting depthcharge on Spherion...'
365 22:54:01.482278 Changing prompt to 'Starting depthcharge on Spherion...'
366 22:54:01.482644 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
367 22:54:01.484032 [Enter `^Ec?' for help]
368 22:54:01.484482
369 22:54:01.484845 F0: 102B 0000
370 22:54:01.485195
371 22:54:01.485594 F3: 1001 0000 [0200]
372 22:54:01.485938
373 22:54:01.486260 F3: 1001 0000
374 22:54:01.486573
375 22:54:01.486880 F7: 102D 0000
376 22:54:01.487188
377 22:54:01.487488 F1: 0000 0000
378 22:54:01.487791
379 22:54:01.488091 V0: 0000 0000 [0001]
380 22:54:01.488401
381 22:54:01.488698 00: 0007 8000
382 22:54:01.489034
383 22:54:01.489312 01: 0000 0000
384 22:54:01.489658
385 22:54:01.489938 BP: 0C00 0209 [0000]
386 22:54:01.490212
387 22:54:01.490485 G0: 1182 0000
388 22:54:01.490762
389 22:54:01.491039 EC: 0000 0021 [4000]
390 22:54:01.491525
391 22:54:01.492003 S7: 0000 0000 [0000]
392 22:54:01.492315
393 22:54:01.492601 CC: 0000 0000 [0001]
394 22:54:01.492883
395 22:54:01.493160 T0: 0000 0040 [010F]
396 22:54:01.493498
397 22:54:01.493787 Jump to BL
398 22:54:01.494064
399 22:54:01.494338
400 22:54:01.494614
401 22:54:01.494915
402 22:54:01.495418 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
403 22:54:01.495875 ARM64: Exception handlers installed.
404 22:54:01.496176 ARM64: Testing exception
405 22:54:01.496462 ARM64: Done test exception
406 22:54:01.496742 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
407 22:54:01.497024 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
408 22:54:01.497310 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
409 22:54:01.497676 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
410 22:54:01.498190 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
411 22:54:01.498540 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
412 22:54:01.498829 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
413 22:54:01.499112 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
414 22:54:01.499395 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
415 22:54:01.499675 WDT: Last reset was cold boot
416 22:54:01.499953 SPI1(PAD0) initialized at 2873684 Hz
417 22:54:01.500228 SPI5(PAD0) initialized at 992727 Hz
418 22:54:01.500502 VBOOT: Loading verstage.
419 22:54:01.500775 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
420 22:54:01.501054 FMAP: Found "FLASH" version 1.1 at 0x20000.
421 22:54:01.501347 FMAP: base = 0x0 size = 0x800000 #areas = 25
422 22:54:01.501632 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
423 22:54:01.501912 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
424 22:54:01.502193 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
425 22:54:01.502471 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
426 22:54:01.502744
427 22:54:01.503187
428 22:54:01.503674 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
429 22:54:01.503989 ARM64: Exception handlers installed.
430 22:54:01.504272 ARM64: Testing exception
431 22:54:01.504552 ARM64: Done test exception
432 22:54:01.504831 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
433 22:54:01.505109 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
434 22:54:01.505422 Probing TPM: . done!
435 22:54:01.505707 TPM ready after 0 ms
436 22:54:01.505987 Connected to device vid:did:rid of 1ae0:0028:00
437 22:54:01.506266 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
438 22:54:01.506547 Initialized TPM device CR50 revision 0
439 22:54:01.506823 tlcl_send_startup: Startup return code is 0
440 22:54:01.507101 TPM: setup succeeded
441 22:54:01.507374 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
442 22:54:01.507650 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
443 22:54:01.507927 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
444 22:54:01.508206 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 22:54:01.508481 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
446 22:54:01.508759 in-header: 03 07 00 00 08 00 00 00
447 22:54:01.509034 in-data: aa e4 47 04 13 02 00 00
448 22:54:01.509309 Chrome EC: UHEPI supported
449 22:54:01.509623 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
450 22:54:01.509906 in-header: 03 a9 00 00 08 00 00 00
451 22:54:01.510135 in-data: 84 60 60 08 00 00 00 00
452 22:54:01.510333 Phase 1
453 22:54:01.510529 FMAP: area GBB found @ 3f5000 (12032 bytes)
454 22:54:01.510729 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
455 22:54:01.510926 VB2:vb2_check_recovery() Recovery was requested manually
456 22:54:01.511123 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
457 22:54:01.511318 Recovery requested (1009000e)
458 22:54:01.511513 TPM: Extending digest for VBOOT: boot mode into PCR 0
459 22:54:01.511710 tlcl_extend: response is 0
460 22:54:01.511904 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
461 22:54:01.512102 tlcl_extend: response is 0
462 22:54:01.512297 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
463 22:54:01.512494 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
464 22:54:01.512690 BS: bootblock times (exec / console): total (unknown) / 148 ms
465 22:54:01.512886
466 22:54:01.513092
467 22:54:01.513288 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
468 22:54:01.513503 ARM64: Exception handlers installed.
469 22:54:01.513700 ARM64: Testing exception
470 22:54:01.513896 ARM64: Done test exception
471 22:54:01.514090 pmic_efuse_setting: Set efuses in 11 msecs
472 22:54:01.514285 pmwrap_interface_init: Select PMIF_VLD_RDY
473 22:54:01.514481 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
474 22:54:01.514963 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
475 22:54:01.515151 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
476 22:54:01.515303 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
477 22:54:01.515453 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
478 22:54:01.515601 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
479 22:54:01.515750 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
480 22:54:01.515955 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
481 22:54:01.516239 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
482 22:54:01.516413 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
483 22:54:01.516568 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
484 22:54:01.516719 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
485 22:54:01.516876 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
486 22:54:01.517028 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
487 22:54:01.517179 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
488 22:54:01.517347 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
489 22:54:01.517504 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
490 22:54:01.517654 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
491 22:54:01.517804 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
492 22:54:01.517956 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
493 22:54:01.518104 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
494 22:54:01.518252 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
495 22:54:01.518400 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
496 22:54:01.518549 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
497 22:54:01.518698 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
498 22:54:01.518849 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
499 22:54:01.518997 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
500 22:54:01.519148 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
501 22:54:01.519427 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
502 22:54:01.519593 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
503 22:54:01.519745 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
504 22:54:01.519898 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
505 22:54:01.520037 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
506 22:54:01.520157 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
507 22:54:01.520324 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
508 22:54:01.520547 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
509 22:54:01.520757 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
510 22:54:01.520889 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
511 22:54:01.521012 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
512 22:54:01.521135 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
513 22:54:01.521256 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
514 22:54:01.521393 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
515 22:54:01.521517 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
516 22:54:01.521636 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
517 22:54:01.521754 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
518 22:54:01.521873 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
519 22:54:01.521991 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
520 22:54:01.522109 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
521 22:54:01.522227 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
522 22:54:01.522346 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
523 22:54:01.522464 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
524 22:54:01.522582 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
525 22:54:01.522703 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
526 22:54:01.522823 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
527 22:54:01.522941 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
528 22:54:01.523061 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
529 22:54:01.523179 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
530 22:54:01.523298 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
531 22:54:01.523416 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 22:54:01.523536 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x1b
533 22:54:01.523656 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
534 22:54:01.523775 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
535 22:54:01.523893 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
536 22:54:01.524013 [RTC]rtc_get_frequency_meter,154: input=15, output=835
537 22:54:01.524131 [RTC]rtc_get_frequency_meter,154: input=7, output=709
538 22:54:01.524248 [RTC]rtc_get_frequency_meter,154: input=11, output=772
539 22:54:01.524367 [RTC]rtc_get_frequency_meter,154: input=13, output=803
540 22:54:01.524487 [RTC]rtc_get_frequency_meter,154: input=12, output=787
541 22:54:01.524605 [RTC]rtc_get_frequency_meter,154: input=12, output=788
542 22:54:01.524722 [RTC]rtc_get_frequency_meter,154: input=13, output=803
543 22:54:01.524840 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
544 22:54:01.525178 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
545 22:54:01.525290 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
546 22:54:01.525421 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
547 22:54:01.525524 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
548 22:54:01.525625 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
549 22:54:01.525724 ADC[4]: Raw value=902291 ID=7
550 22:54:01.525824 ADC[3]: Raw value=214021 ID=1
551 22:54:01.525923 RAM Code: 0x71
552 22:54:01.526022 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
553 22:54:01.526123 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
554 22:54:01.526223 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
555 22:54:01.526324 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
556 22:54:01.526423 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
557 22:54:01.526524 in-header: 03 07 00 00 08 00 00 00
558 22:54:01.526621 in-data: aa e4 47 04 13 02 00 00
559 22:54:01.526720 Chrome EC: UHEPI supported
560 22:54:01.526818 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
561 22:54:01.526919 in-header: 03 a9 00 00 08 00 00 00
562 22:54:01.527018 in-data: 84 60 60 08 00 00 00 00
563 22:54:01.527116 MRC: failed to locate region type 0.
564 22:54:01.527215 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
565 22:54:01.527314 DRAM-K: Running full calibration
566 22:54:01.527413 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
567 22:54:01.527512 header.status = 0x0
568 22:54:01.527611 header.version = 0x6 (expected: 0x6)
569 22:54:01.527715 header.size = 0xd00 (expected: 0xd00)
570 22:54:01.527814 header.flags = 0x0
571 22:54:01.527912 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
572 22:54:01.528012 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
573 22:54:01.528120 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
574 22:54:01.528238 dram_init: ddr_geometry: 2
575 22:54:01.528339 [EMI] MDL number = 2
576 22:54:01.528438 [EMI] Get MDL freq = 0
577 22:54:01.528536 dram_init: ddr_type: 0
578 22:54:01.528635 is_discrete_lpddr4: 1
579 22:54:01.528733 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
580 22:54:01.528831
581 22:54:01.528931
582 22:54:01.529028 [Bian_co] ETT version 0.0.0.1
583 22:54:01.529128 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
584 22:54:01.529227
585 22:54:01.529326 dramc_set_vcore_voltage set vcore to 650000
586 22:54:01.529437 Read voltage for 800, 4
587 22:54:01.529536 Vio18 = 0
588 22:54:01.529636 Vcore = 650000
589 22:54:01.529735 Vdram = 0
590 22:54:01.529834 Vddq = 0
591 22:54:01.529945 Vmddr = 0
592 22:54:01.530029 dram_init: config_dvfs: 1
593 22:54:01.530115 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
594 22:54:01.530201 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
595 22:54:01.530286 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
596 22:54:01.530372 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
597 22:54:01.530458 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
598 22:54:01.530542 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
599 22:54:01.530627 MEM_TYPE=3, freq_sel=18
600 22:54:01.530712 sv_algorithm_assistance_LP4_1600
601 22:54:01.530797 ============ PULL DRAM RESETB DOWN ============
602 22:54:01.530885 ========== PULL DRAM RESETB DOWN end =========
603 22:54:01.530971 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
604 22:54:01.531057 ===================================
605 22:54:01.531141 LPDDR4 DRAM CONFIGURATION
606 22:54:01.531225 ===================================
607 22:54:01.531309 EX_ROW_EN[0] = 0x0
608 22:54:01.531393 EX_ROW_EN[1] = 0x0
609 22:54:01.531477 LP4Y_EN = 0x0
610 22:54:01.531561 WORK_FSP = 0x0
611 22:54:01.531646 WL = 0x2
612 22:54:01.531731 RL = 0x2
613 22:54:01.531815 BL = 0x2
614 22:54:01.531899 RPST = 0x0
615 22:54:01.531983 RD_PRE = 0x0
616 22:54:01.532066 WR_PRE = 0x1
617 22:54:01.532149 WR_PST = 0x0
618 22:54:01.532233 DBI_WR = 0x0
619 22:54:01.532317 DBI_RD = 0x0
620 22:54:01.532401 OTF = 0x1
621 22:54:01.532486 ===================================
622 22:54:01.532571 ===================================
623 22:54:01.532674 ANA top config
624 22:54:01.532823 ===================================
625 22:54:01.532987 DLL_ASYNC_EN = 0
626 22:54:01.533131 ALL_SLAVE_EN = 1
627 22:54:01.533266 NEW_RANK_MODE = 1
628 22:54:01.533399 DLL_IDLE_MODE = 1
629 22:54:01.533488 LP45_APHY_COMB_EN = 1
630 22:54:01.533575 TX_ODT_DIS = 1
631 22:54:01.533661 NEW_8X_MODE = 1
632 22:54:01.533746 ===================================
633 22:54:01.533832 ===================================
634 22:54:01.533918 data_rate = 1600
635 22:54:01.534003 CKR = 1
636 22:54:01.534088 DQ_P2S_RATIO = 8
637 22:54:01.534173 ===================================
638 22:54:01.534258 CA_P2S_RATIO = 8
639 22:54:01.534342 DQ_CA_OPEN = 0
640 22:54:01.534427 DQ_SEMI_OPEN = 0
641 22:54:01.534512 CA_SEMI_OPEN = 0
642 22:54:01.534596 CA_FULL_RATE = 0
643 22:54:01.534680 DQ_CKDIV4_EN = 1
644 22:54:01.534764 CA_CKDIV4_EN = 1
645 22:54:01.534848 CA_PREDIV_EN = 0
646 22:54:01.534931 PH8_DLY = 0
647 22:54:01.535022 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
648 22:54:01.535096 DQ_AAMCK_DIV = 4
649 22:54:01.535169 CA_AAMCK_DIV = 4
650 22:54:01.535242 CA_ADMCK_DIV = 4
651 22:54:01.535315 DQ_TRACK_CA_EN = 0
652 22:54:01.535388 CA_PICK = 800
653 22:54:01.535463 CA_MCKIO = 800
654 22:54:01.535536 MCKIO_SEMI = 0
655 22:54:01.535610 PLL_FREQ = 3068
656 22:54:01.535683 DQ_UI_PI_RATIO = 32
657 22:54:01.535757 CA_UI_PI_RATIO = 0
658 22:54:01.535830 ===================================
659 22:54:01.535905 ===================================
660 22:54:01.535978 memory_type:LPDDR4
661 22:54:01.536052 GP_NUM : 10
662 22:54:01.536125 SRAM_EN : 1
663 22:54:01.536199 MD32_EN : 0
664 22:54:01.536502 ===================================
665 22:54:01.536586 [ANA_INIT] >>>>>>>>>>>>>>
666 22:54:01.536664 <<<<<< [CONFIGURE PHASE]: ANA_TX
667 22:54:01.536742 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
668 22:54:01.536818 ===================================
669 22:54:01.536892 data_rate = 1600,PCW = 0X7600
670 22:54:01.536967 ===================================
671 22:54:01.537042 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
672 22:54:01.537117 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
673 22:54:01.537192 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 22:54:01.537268 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
675 22:54:01.537359 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
676 22:54:01.537437 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
677 22:54:01.537512 [ANA_INIT] flow start
678 22:54:01.537587 [ANA_INIT] PLL >>>>>>>>
679 22:54:01.537661 [ANA_INIT] PLL <<<<<<<<
680 22:54:01.537735 [ANA_INIT] MIDPI >>>>>>>>
681 22:54:01.537810 [ANA_INIT] MIDPI <<<<<<<<
682 22:54:01.537883 [ANA_INIT] DLL >>>>>>>>
683 22:54:01.537957 [ANA_INIT] flow end
684 22:54:01.538031 ============ LP4 DIFF to SE enter ============
685 22:54:01.538106 ============ LP4 DIFF to SE exit ============
686 22:54:01.538180 [ANA_INIT] <<<<<<<<<<<<<
687 22:54:01.538254 [Flow] Enable top DCM control >>>>>
688 22:54:01.538328 [Flow] Enable top DCM control <<<<<
689 22:54:01.538403 Enable DLL master slave shuffle
690 22:54:01.538477 ==============================================================
691 22:54:01.538552 Gating Mode config
692 22:54:01.538626 ==============================================================
693 22:54:01.538701 Config description:
694 22:54:01.538775 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
695 22:54:01.538851 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
696 22:54:01.538927 SELPH_MODE 0: By rank 1: By Phase
697 22:54:01.539002 ==============================================================
698 22:54:01.539077 GAT_TRACK_EN = 1
699 22:54:01.539151 RX_GATING_MODE = 2
700 22:54:01.539226 RX_GATING_TRACK_MODE = 2
701 22:54:01.539300 SELPH_MODE = 1
702 22:54:01.539374 PICG_EARLY_EN = 1
703 22:54:01.539447 VALID_LAT_VALUE = 1
704 22:54:01.539521 ==============================================================
705 22:54:01.539596 Enter into Gating configuration >>>>
706 22:54:01.539670 Exit from Gating configuration <<<<
707 22:54:01.539743 Enter into DVFS_PRE_config >>>>>
708 22:54:01.539817 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
709 22:54:01.539896 Exit from DVFS_PRE_config <<<<<
710 22:54:01.539983 Enter into PICG configuration >>>>
711 22:54:01.540049 Exit from PICG configuration <<<<
712 22:54:01.540115 [RX_INPUT] configuration >>>>>
713 22:54:01.540181 [RX_INPUT] configuration <<<<<
714 22:54:01.540246 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
715 22:54:01.540312 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
716 22:54:01.540379 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
717 22:54:01.540445 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
718 22:54:01.540511 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
719 22:54:01.540577 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
720 22:54:01.540643 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
721 22:54:01.540710 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
722 22:54:01.540776 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
723 22:54:01.540842 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
724 22:54:01.540908 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
725 22:54:01.540974 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
726 22:54:01.541040 ===================================
727 22:54:01.541106 LPDDR4 DRAM CONFIGURATION
728 22:54:01.541172 ===================================
729 22:54:01.541237 EX_ROW_EN[0] = 0x0
730 22:54:01.541303 EX_ROW_EN[1] = 0x0
731 22:54:01.541404 LP4Y_EN = 0x0
732 22:54:01.541475 WORK_FSP = 0x0
733 22:54:01.541541 WL = 0x2
734 22:54:01.541607 RL = 0x2
735 22:54:01.541673 BL = 0x2
736 22:54:01.541739 RPST = 0x0
737 22:54:01.541804 RD_PRE = 0x0
738 22:54:01.541870 WR_PRE = 0x1
739 22:54:01.541935 WR_PST = 0x0
740 22:54:01.542001 DBI_WR = 0x0
741 22:54:01.542066 DBI_RD = 0x0
742 22:54:01.542131 OTF = 0x1
743 22:54:01.542198 ===================================
744 22:54:01.542264 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
745 22:54:01.542330 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
746 22:54:01.542396 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
747 22:54:01.542462 ===================================
748 22:54:01.542528 LPDDR4 DRAM CONFIGURATION
749 22:54:01.542594 ===================================
750 22:54:01.542660 EX_ROW_EN[0] = 0x10
751 22:54:01.542725 EX_ROW_EN[1] = 0x0
752 22:54:01.542791 LP4Y_EN = 0x0
753 22:54:01.542856 WORK_FSP = 0x0
754 22:54:01.542922 WL = 0x2
755 22:54:01.542987 RL = 0x2
756 22:54:01.543053 BL = 0x2
757 22:54:01.543118 RPST = 0x0
758 22:54:01.543183 RD_PRE = 0x0
759 22:54:01.543249 WR_PRE = 0x1
760 22:54:01.543314 WR_PST = 0x0
761 22:54:01.543379 DBI_WR = 0x0
762 22:54:01.543444 DBI_RD = 0x0
763 22:54:01.543509 OTF = 0x1
764 22:54:01.543576 ===================================
765 22:54:01.543641 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
766 22:54:01.543708 nWR fixed to 40
767 22:54:01.543775 [ModeRegInit_LP4] CH0 RK0
768 22:54:01.543840 [ModeRegInit_LP4] CH0 RK1
769 22:54:01.543919 [ModeRegInit_LP4] CH1 RK0
770 22:54:01.543986 [ModeRegInit_LP4] CH1 RK1
771 22:54:01.544052 match AC timing 13
772 22:54:01.544322 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
773 22:54:01.544402 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
774 22:54:01.544470 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
775 22:54:01.544537 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
776 22:54:01.544604 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
777 22:54:01.544670 [EMI DOE] emi_dcm 0
778 22:54:01.544736 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
779 22:54:01.544802 ==
780 22:54:01.544870 Dram Type= 6, Freq= 0, CH_0, rank 0
781 22:54:01.544936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 22:54:01.545008 ==
783 22:54:01.545068 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
784 22:54:01.545128 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
785 22:54:01.545188 [CA 0] Center 37 (6~68) winsize 63
786 22:54:01.545248 [CA 1] Center 37 (6~68) winsize 63
787 22:54:01.545307 [CA 2] Center 34 (4~65) winsize 62
788 22:54:01.545377 [CA 3] Center 34 (4~65) winsize 62
789 22:54:01.545438 [CA 4] Center 34 (4~64) winsize 61
790 22:54:01.545497 [CA 5] Center 33 (3~64) winsize 62
791 22:54:01.545556
792 22:54:01.545616 [CmdBusTrainingLP45] Vref(ca) range 1: 32
793 22:54:01.545675
794 22:54:01.545735 [CATrainingPosCal] consider 1 rank data
795 22:54:01.545795 u2DelayCellTimex100 = 270/100 ps
796 22:54:01.545854 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
797 22:54:01.545914 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
798 22:54:01.545973 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
799 22:54:01.546032 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
800 22:54:01.546092 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
801 22:54:01.546150 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
802 22:54:01.546209
803 22:54:01.546268 CA PerBit enable=1, Macro0, CA PI delay=33
804 22:54:01.546328
805 22:54:01.546386 [CBTSetCACLKResult] CA Dly = 33
806 22:54:01.546446 CS Dly: 6 (0~37)
807 22:54:01.546505 ==
808 22:54:01.546564 Dram Type= 6, Freq= 0, CH_0, rank 1
809 22:54:01.546623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
810 22:54:01.546683 ==
811 22:54:01.546742 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
812 22:54:01.546802 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
813 22:54:01.546861 [CA 0] Center 37 (6~68) winsize 63
814 22:54:01.546920 [CA 1] Center 37 (7~68) winsize 62
815 22:54:01.546979 [CA 2] Center 34 (4~65) winsize 62
816 22:54:01.547038 [CA 3] Center 34 (4~65) winsize 62
817 22:54:01.547097 [CA 4] Center 33 (3~64) winsize 62
818 22:54:01.547155 [CA 5] Center 33 (3~64) winsize 62
819 22:54:01.547214
820 22:54:01.547273 [CmdBusTrainingLP45] Vref(ca) range 1: 34
821 22:54:01.547333
822 22:54:01.547392 [CATrainingPosCal] consider 2 rank data
823 22:54:01.547451 u2DelayCellTimex100 = 270/100 ps
824 22:54:01.547511 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
825 22:54:01.547570 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
826 22:54:01.547630 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
827 22:54:01.547689 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
828 22:54:01.547748 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
829 22:54:01.547808 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
830 22:54:01.547866
831 22:54:01.547925 CA PerBit enable=1, Macro0, CA PI delay=33
832 22:54:01.547984
833 22:54:01.548044 [CBTSetCACLKResult] CA Dly = 33
834 22:54:01.548103 CS Dly: 6 (0~38)
835 22:54:01.548162
836 22:54:01.548221 ----->DramcWriteLeveling(PI) begin...
837 22:54:01.548285 ==
838 22:54:01.548344 Dram Type= 6, Freq= 0, CH_0, rank 0
839 22:54:01.548404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
840 22:54:01.548463 ==
841 22:54:01.548523 Write leveling (Byte 0): 34 => 34
842 22:54:01.548583 Write leveling (Byte 1): 31 => 31
843 22:54:01.548642 DramcWriteLeveling(PI) end<-----
844 22:54:01.548701
845 22:54:01.548760 ==
846 22:54:01.548819 Dram Type= 6, Freq= 0, CH_0, rank 0
847 22:54:01.548878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
848 22:54:01.548938 ==
849 22:54:01.548998 [Gating] SW mode calibration
850 22:54:01.549056 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
851 22:54:01.549116 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
852 22:54:01.549175 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
853 22:54:01.549235 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 22:54:01.549294 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
855 22:54:01.549366 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 22:54:01.549428 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 22:54:01.549488 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 22:54:01.549548 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 22:54:01.549607 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 22:54:01.549667 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 22:54:01.549726 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 22:54:01.549785 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 22:54:01.549844 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 22:54:01.549904 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 22:54:01.549975 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 22:54:01.550029 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 22:54:01.550083 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 22:54:01.550137 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 22:54:01.550190 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
870 22:54:01.550244 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
871 22:54:01.550298 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 22:54:01.550352 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 22:54:01.550406 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 22:54:01.550459 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 22:54:01.550513 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 22:54:01.550567 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 22:54:01.550621 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 22:54:01.550675 0 9 8 | B1->B0 | 2323 2828 | 0 1 | (1 1) (1 1)
879 22:54:01.550729 0 9 12 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
880 22:54:01.550975 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 22:54:01.551036 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 22:54:01.551092 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 22:54:01.551147 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 22:54:01.551201 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 22:54:01.551256 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
886 22:54:01.551311 0 10 8 | B1->B0 | 3333 2525 | 0 0 | (0 1) (0 0)
887 22:54:01.551365 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
888 22:54:01.551419 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 22:54:01.551473 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 22:54:01.551527 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 22:54:01.551580 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 22:54:01.551635 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 22:54:01.551689 0 11 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
894 22:54:01.551743 0 11 8 | B1->B0 | 2524 3838 | 1 0 | (0 0) (1 1)
895 22:54:01.551797 0 11 12 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
896 22:54:01.551852 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 22:54:01.551906 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 22:54:01.551960 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 22:54:01.552014 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 22:54:01.552068 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 22:54:01.552122 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
902 22:54:01.552175 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
903 22:54:01.552229 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
904 22:54:01.552283 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 22:54:01.552337 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 22:54:01.552390 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 22:54:01.552445 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 22:54:01.552499 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 22:54:01.552552 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 22:54:01.552606 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 22:54:01.552660 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 22:54:01.552717 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 22:54:01.552771 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 22:54:01.552825 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 22:54:01.552879 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 22:54:01.552933 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 22:54:01.552988 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 22:54:01.553041 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
919 22:54:01.553095 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
920 22:54:01.553149 Total UI for P1: 0, mck2ui 16
921 22:54:01.553203 best dqsien dly found for B0: ( 0, 14, 8)
922 22:54:01.553257 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
923 22:54:01.553312 Total UI for P1: 0, mck2ui 16
924 22:54:01.553372 best dqsien dly found for B1: ( 0, 14, 12)
925 22:54:01.553427 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
926 22:54:01.553480 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
927 22:54:01.553535
928 22:54:01.553589 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
929 22:54:01.553644 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
930 22:54:01.553698 [Gating] SW calibration Done
931 22:54:01.553752 ==
932 22:54:01.553806 Dram Type= 6, Freq= 0, CH_0, rank 0
933 22:54:01.553861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 22:54:01.553915 ==
935 22:54:01.553969 RX Vref Scan: 0
936 22:54:01.554022
937 22:54:01.554076 RX Vref 0 -> 0, step: 1
938 22:54:01.554129
939 22:54:01.554182 RX Delay -130 -> 252, step: 16
940 22:54:01.554236 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
941 22:54:01.554290 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
942 22:54:01.554344 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
943 22:54:01.554397 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
944 22:54:01.554451 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
945 22:54:01.554505 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
946 22:54:01.554558 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
947 22:54:01.554612 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
948 22:54:01.554666 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
949 22:54:01.554719 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
950 22:54:01.554773 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
951 22:54:01.554826 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
952 22:54:01.554880 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
953 22:54:01.554933 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
954 22:54:01.554999 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
955 22:54:01.555051 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
956 22:54:01.555104 ==
957 22:54:01.555157 Dram Type= 6, Freq= 0, CH_0, rank 0
958 22:54:01.555209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 22:54:01.555262 ==
960 22:54:01.555315 DQS Delay:
961 22:54:01.555368 DQS0 = 0, DQS1 = 0
962 22:54:01.555420 DQM Delay:
963 22:54:01.555472 DQM0 = 86, DQM1 = 77
964 22:54:01.555525 DQ Delay:
965 22:54:01.555577 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
966 22:54:01.555630 DQ4 =85, DQ5 =77, DQ6 =93, DQ7 =93
967 22:54:01.555683 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
968 22:54:01.555736 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
969 22:54:01.555789
970 22:54:01.555841
971 22:54:01.555893 ==
972 22:54:01.555946 Dram Type= 6, Freq= 0, CH_0, rank 0
973 22:54:01.555999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 22:54:01.556052 ==
975 22:54:01.556104
976 22:54:01.556156
977 22:54:01.556208 TX Vref Scan disable
978 22:54:01.556261 == TX Byte 0 ==
979 22:54:01.556314 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
980 22:54:01.556367 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
981 22:54:01.556421 == TX Byte 1 ==
982 22:54:01.556473 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
983 22:54:01.556526 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
984 22:54:01.556579 ==
985 22:54:01.556632 Dram Type= 6, Freq= 0, CH_0, rank 0
986 22:54:01.556685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 22:54:01.556737 ==
988 22:54:01.556978 TX Vref=22, minBit 2, minWin=27, winSum=441
989 22:54:01.557037 TX Vref=24, minBit 3, minWin=27, winSum=441
990 22:54:01.557091 TX Vref=26, minBit 12, minWin=27, winSum=447
991 22:54:01.557145 TX Vref=28, minBit 10, minWin=27, winSum=447
992 22:54:01.557198 TX Vref=30, minBit 7, minWin=27, winSum=450
993 22:54:01.557251 TX Vref=32, minBit 4, minWin=27, winSum=447
994 22:54:01.557304 [TxChooseVref] Worse bit 7, Min win 27, Win sum 450, Final Vref 30
995 22:54:01.557386
996 22:54:01.557467 Final TX Range 1 Vref 30
997 22:54:01.557520
998 22:54:01.557572 ==
999 22:54:01.557629 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 22:54:01.557682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 22:54:01.557735 ==
1002 22:54:01.557787
1003 22:54:01.557849
1004 22:54:01.557954 TX Vref Scan disable
1005 22:54:01.558025 == TX Byte 0 ==
1006 22:54:01.558081 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1007 22:54:01.558135 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1008 22:54:01.558189 == TX Byte 1 ==
1009 22:54:01.558243 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1010 22:54:01.558296 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1011 22:54:01.558350
1012 22:54:01.558404 [DATLAT]
1013 22:54:01.558457 Freq=800, CH0 RK0
1014 22:54:01.558511
1015 22:54:01.558563 DATLAT Default: 0xa
1016 22:54:01.558616 0, 0xFFFF, sum = 0
1017 22:54:01.558670 1, 0xFFFF, sum = 0
1018 22:54:01.558724 2, 0xFFFF, sum = 0
1019 22:54:01.558778 3, 0xFFFF, sum = 0
1020 22:54:01.558831 4, 0xFFFF, sum = 0
1021 22:54:01.558885 5, 0xFFFF, sum = 0
1022 22:54:01.558939 6, 0xFFFF, sum = 0
1023 22:54:01.558992 7, 0xFFFF, sum = 0
1024 22:54:01.559045 8, 0xFFFF, sum = 0
1025 22:54:01.559106 9, 0x0, sum = 1
1026 22:54:01.559165 10, 0x0, sum = 2
1027 22:54:01.559219 11, 0x0, sum = 3
1028 22:54:01.559272 12, 0x0, sum = 4
1029 22:54:01.559325 best_step = 10
1030 22:54:01.559376
1031 22:54:01.559429 ==
1032 22:54:01.559481 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 22:54:01.559534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 22:54:01.559586 ==
1035 22:54:01.559639 RX Vref Scan: 1
1036 22:54:01.559691
1037 22:54:01.559743 Set Vref Range= 32 -> 127
1038 22:54:01.559795
1039 22:54:01.559847 RX Vref 32 -> 127, step: 1
1040 22:54:01.559900
1041 22:54:01.559951 RX Delay -95 -> 252, step: 8
1042 22:54:01.560004
1043 22:54:01.560055 Set Vref, RX VrefLevel [Byte0]: 32
1044 22:54:01.560108 [Byte1]: 32
1045 22:54:01.560159
1046 22:54:01.560211 Set Vref, RX VrefLevel [Byte0]: 33
1047 22:54:01.560263 [Byte1]: 33
1048 22:54:01.560315
1049 22:54:01.560366 Set Vref, RX VrefLevel [Byte0]: 34
1050 22:54:01.560418 [Byte1]: 34
1051 22:54:01.560470
1052 22:54:01.560521 Set Vref, RX VrefLevel [Byte0]: 35
1053 22:54:01.560573 [Byte1]: 35
1054 22:54:01.560624
1055 22:54:01.560675 Set Vref, RX VrefLevel [Byte0]: 36
1056 22:54:01.560727 [Byte1]: 36
1057 22:54:01.560814
1058 22:54:01.560909 Set Vref, RX VrefLevel [Byte0]: 37
1059 22:54:01.560990 [Byte1]: 37
1060 22:54:01.561046
1061 22:54:01.561099 Set Vref, RX VrefLevel [Byte0]: 38
1062 22:54:01.561152 [Byte1]: 38
1063 22:54:01.561205
1064 22:54:01.561256 Set Vref, RX VrefLevel [Byte0]: 39
1065 22:54:01.561309 [Byte1]: 39
1066 22:54:01.561370
1067 22:54:01.561428 Set Vref, RX VrefLevel [Byte0]: 40
1068 22:54:01.561481 [Byte1]: 40
1069 22:54:01.561534
1070 22:54:01.561585 Set Vref, RX VrefLevel [Byte0]: 41
1071 22:54:01.561637 [Byte1]: 41
1072 22:54:01.561690
1073 22:54:01.561741 Set Vref, RX VrefLevel [Byte0]: 42
1074 22:54:01.561793 [Byte1]: 42
1075 22:54:01.561845
1076 22:54:01.561897 Set Vref, RX VrefLevel [Byte0]: 43
1077 22:54:01.561949 [Byte1]: 43
1078 22:54:01.562001
1079 22:54:01.562053 Set Vref, RX VrefLevel [Byte0]: 44
1080 22:54:01.562105 [Byte1]: 44
1081 22:54:01.562156
1082 22:54:01.562208 Set Vref, RX VrefLevel [Byte0]: 45
1083 22:54:01.562259 [Byte1]: 45
1084 22:54:01.562311
1085 22:54:01.562363 Set Vref, RX VrefLevel [Byte0]: 46
1086 22:54:01.562415 [Byte1]: 46
1087 22:54:01.562467
1088 22:54:01.562519 Set Vref, RX VrefLevel [Byte0]: 47
1089 22:54:01.562571 [Byte1]: 47
1090 22:54:01.562623
1091 22:54:01.562674 Set Vref, RX VrefLevel [Byte0]: 48
1092 22:54:01.562726 [Byte1]: 48
1093 22:54:01.562777
1094 22:54:01.562829 Set Vref, RX VrefLevel [Byte0]: 49
1095 22:54:01.562882 [Byte1]: 49
1096 22:54:01.562933
1097 22:54:01.562985 Set Vref, RX VrefLevel [Byte0]: 50
1098 22:54:01.563037 [Byte1]: 50
1099 22:54:01.563089
1100 22:54:01.563140 Set Vref, RX VrefLevel [Byte0]: 51
1101 22:54:01.563192 [Byte1]: 51
1102 22:54:01.563244
1103 22:54:01.563295 Set Vref, RX VrefLevel [Byte0]: 52
1104 22:54:01.563347 [Byte1]: 52
1105 22:54:01.563398
1106 22:54:01.563449 Set Vref, RX VrefLevel [Byte0]: 53
1107 22:54:01.563501 [Byte1]: 53
1108 22:54:01.563552
1109 22:54:01.563604 Set Vref, RX VrefLevel [Byte0]: 54
1110 22:54:01.563656 [Byte1]: 54
1111 22:54:01.563708
1112 22:54:01.563759 Set Vref, RX VrefLevel [Byte0]: 55
1113 22:54:01.563812 [Byte1]: 55
1114 22:54:01.563863
1115 22:54:01.563915 Set Vref, RX VrefLevel [Byte0]: 56
1116 22:54:01.563967 [Byte1]: 56
1117 22:54:01.564018
1118 22:54:01.564069 Set Vref, RX VrefLevel [Byte0]: 57
1119 22:54:01.564121 [Byte1]: 57
1120 22:54:01.564173
1121 22:54:01.564225 Set Vref, RX VrefLevel [Byte0]: 58
1122 22:54:01.564277 [Byte1]: 58
1123 22:54:01.564328
1124 22:54:01.564379 Set Vref, RX VrefLevel [Byte0]: 59
1125 22:54:01.564431 [Byte1]: 59
1126 22:54:01.564483
1127 22:54:01.564534 Set Vref, RX VrefLevel [Byte0]: 60
1128 22:54:01.564585 [Byte1]: 60
1129 22:54:01.564637
1130 22:54:01.564689 Set Vref, RX VrefLevel [Byte0]: 61
1131 22:54:01.564741 [Byte1]: 61
1132 22:54:01.564792
1133 22:54:01.564843 Set Vref, RX VrefLevel [Byte0]: 62
1134 22:54:01.564895 [Byte1]: 62
1135 22:54:01.564947
1136 22:54:01.564998 Set Vref, RX VrefLevel [Byte0]: 63
1137 22:54:01.565050 [Byte1]: 63
1138 22:54:01.565101
1139 22:54:01.565153 Set Vref, RX VrefLevel [Byte0]: 64
1140 22:54:01.565204 [Byte1]: 64
1141 22:54:01.565256
1142 22:54:01.565307 Set Vref, RX VrefLevel [Byte0]: 65
1143 22:54:01.565363 [Byte1]: 65
1144 22:54:01.565416
1145 22:54:01.565467 Set Vref, RX VrefLevel [Byte0]: 66
1146 22:54:01.565519 [Byte1]: 66
1147 22:54:01.565571
1148 22:54:01.565622 Set Vref, RX VrefLevel [Byte0]: 67
1149 22:54:01.565673 [Byte1]: 67
1150 22:54:01.565725
1151 22:54:01.565777 Set Vref, RX VrefLevel [Byte0]: 68
1152 22:54:01.565831 [Byte1]: 68
1153 22:54:01.565883
1154 22:54:01.565935 Set Vref, RX VrefLevel [Byte0]: 69
1155 22:54:01.566183 [Byte1]: 69
1156 22:54:01.566244
1157 22:54:01.566297 Set Vref, RX VrefLevel [Byte0]: 70
1158 22:54:01.566350 [Byte1]: 70
1159 22:54:01.566402
1160 22:54:01.566454 Set Vref, RX VrefLevel [Byte0]: 71
1161 22:54:01.566506 [Byte1]: 71
1162 22:54:01.566558
1163 22:54:01.566610 Set Vref, RX VrefLevel [Byte0]: 72
1164 22:54:01.566662 [Byte1]: 72
1165 22:54:01.566714
1166 22:54:01.566765 Set Vref, RX VrefLevel [Byte0]: 73
1167 22:54:01.566818 [Byte1]: 73
1168 22:54:01.566869
1169 22:54:01.566921 Set Vref, RX VrefLevel [Byte0]: 74
1170 22:54:01.566973 [Byte1]: 74
1171 22:54:01.567025
1172 22:54:01.567076 Set Vref, RX VrefLevel [Byte0]: 75
1173 22:54:01.567128 [Byte1]: 75
1174 22:54:01.567179
1175 22:54:01.567231 Set Vref, RX VrefLevel [Byte0]: 76
1176 22:54:01.567282 [Byte1]: 76
1177 22:54:01.567334
1178 22:54:01.567386 Set Vref, RX VrefLevel [Byte0]: 77
1179 22:54:01.567437 [Byte1]: 77
1180 22:54:01.567489
1181 22:54:01.567540 Set Vref, RX VrefLevel [Byte0]: 78
1182 22:54:01.567592 [Byte1]: 78
1183 22:54:01.567643
1184 22:54:01.567695 Set Vref, RX VrefLevel [Byte0]: 79
1185 22:54:01.567746 [Byte1]: 79
1186 22:54:01.567798
1187 22:54:01.567850 Set Vref, RX VrefLevel [Byte0]: 80
1188 22:54:01.567902 [Byte1]: 80
1189 22:54:01.567954
1190 22:54:01.568005 Final RX Vref Byte 0 = 65 to rank0
1191 22:54:01.568058 Final RX Vref Byte 1 = 50 to rank0
1192 22:54:01.568110 Final RX Vref Byte 0 = 65 to rank1
1193 22:54:01.568162 Final RX Vref Byte 1 = 50 to rank1==
1194 22:54:01.568214 Dram Type= 6, Freq= 0, CH_0, rank 0
1195 22:54:01.568266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1196 22:54:01.568318 ==
1197 22:54:01.568370 DQS Delay:
1198 22:54:01.568422 DQS0 = 0, DQS1 = 0
1199 22:54:01.568475 DQM Delay:
1200 22:54:01.568527 DQM0 = 87, DQM1 = 76
1201 22:54:01.568578 DQ Delay:
1202 22:54:01.568630 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =84
1203 22:54:01.568682 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1204 22:54:01.568734 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1205 22:54:01.568785 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1206 22:54:01.568837
1207 22:54:01.568888
1208 22:54:01.568940 [DQSOSCAuto] RK0, (LSB)MR18= 0x4829, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 391 ps
1209 22:54:01.568993 CH0 RK0: MR19=606, MR18=4829
1210 22:54:01.569046 CH0_RK0: MR19=0x606, MR18=0x4829, DQSOSC=391, MR23=63, INC=96, DEC=64
1211 22:54:01.569098
1212 22:54:01.569150 ----->DramcWriteLeveling(PI) begin...
1213 22:54:01.569203 ==
1214 22:54:01.569255 Dram Type= 6, Freq= 0, CH_0, rank 1
1215 22:54:01.569308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1216 22:54:01.569374 ==
1217 22:54:01.569427 Write leveling (Byte 0): 32 => 32
1218 22:54:01.569480 Write leveling (Byte 1): 31 => 31
1219 22:54:01.569532 DramcWriteLeveling(PI) end<-----
1220 22:54:01.569584
1221 22:54:01.569638 ==
1222 22:54:01.569690 Dram Type= 6, Freq= 0, CH_0, rank 1
1223 22:54:01.569743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1224 22:54:01.569795 ==
1225 22:54:01.569847 [Gating] SW mode calibration
1226 22:54:01.569899 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1227 22:54:01.569963 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1228 22:54:01.570016 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1229 22:54:01.570069 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1230 22:54:01.570121 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1231 22:54:01.570174 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 22:54:01.570226 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 22:54:01.570278 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 22:54:01.570329 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 22:54:01.570381 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 22:54:01.570434 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 22:54:01.570486 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 22:54:01.570537 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 22:54:01.570589 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 22:54:01.570641 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 22:54:01.570692 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 22:54:01.570744 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 22:54:01.570796 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 22:54:01.570848 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 22:54:01.570900 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1246 22:54:01.570952 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1247 22:54:01.571004 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 22:54:01.571056 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 22:54:01.571107 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 22:54:01.571159 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 22:54:01.571211 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 22:54:01.571263 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 22:54:01.571315 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 22:54:01.571367 0 9 8 | B1->B0 | 2424 2e2d | 1 1 | (1 1) (0 0)
1255 22:54:01.571419 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (1 1) (1 1)
1256 22:54:01.571470 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1257 22:54:01.571522 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1258 22:54:01.571575 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1259 22:54:01.571626 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1260 22:54:01.571678 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1261 22:54:01.571730 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
1262 22:54:01.571782 0 10 8 | B1->B0 | 3030 2c2c | 1 1 | (1 1) (1 0)
1263 22:54:01.571834 0 10 12 | B1->B0 | 2626 2323 | 1 0 | (1 0) (0 0)
1264 22:54:01.571886 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1265 22:54:01.571939 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1266 22:54:01.571990 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1267 22:54:01.572042 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1268 22:54:01.572283 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1269 22:54:01.572341 0 11 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (1 1)
1270 22:54:01.572394 0 11 8 | B1->B0 | 2e2e 3939 | 0 0 | (0 0) (0 0)
1271 22:54:01.572447 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1272 22:54:01.572499 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1273 22:54:01.572551 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1274 22:54:01.572603 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1275 22:54:01.572655 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1276 22:54:01.572706 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1277 22:54:01.572758 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1278 22:54:01.572810 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1279 22:54:01.572862 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1280 22:54:01.572914 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 22:54:01.572965 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 22:54:01.573018 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 22:54:01.573070 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 22:54:01.573122 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 22:54:01.573173 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1286 22:54:01.573225 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1287 22:54:01.573277 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1288 22:54:01.573336 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1289 22:54:01.573390 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1290 22:54:01.573443 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1291 22:54:01.573495 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1292 22:54:01.573547 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1293 22:54:01.573599 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1294 22:54:01.573651 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1295 22:54:01.573702 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1296 22:54:01.573754 Total UI for P1: 0, mck2ui 16
1297 22:54:01.573807 best dqsien dly found for B0: ( 0, 14, 8)
1298 22:54:01.573859 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1299 22:54:01.573911 Total UI for P1: 0, mck2ui 16
1300 22:54:01.573963 best dqsien dly found for B1: ( 0, 14, 12)
1301 22:54:01.574015 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1302 22:54:01.574068 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
1303 22:54:01.574120
1304 22:54:01.574171 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1305 22:54:01.574224 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
1306 22:54:01.574276 [Gating] SW calibration Done
1307 22:54:01.574328 ==
1308 22:54:01.574380 Dram Type= 6, Freq= 0, CH_0, rank 1
1309 22:54:01.574432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1310 22:54:01.574485 ==
1311 22:54:01.574537 RX Vref Scan: 0
1312 22:54:01.574588
1313 22:54:01.574640 RX Vref 0 -> 0, step: 1
1314 22:54:01.574693
1315 22:54:01.574744 RX Delay -130 -> 252, step: 16
1316 22:54:01.574797 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1317 22:54:01.574849 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1318 22:54:01.574901 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1319 22:54:01.574953 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1320 22:54:01.575005 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1321 22:54:01.575056 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1322 22:54:01.575108 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1323 22:54:01.575160 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1324 22:54:01.575212 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1325 22:54:01.575303 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1326 22:54:01.575380 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1327 22:54:01.575477 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1328 22:54:01.575543 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1329 22:54:01.575598 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1330 22:54:01.575651 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1331 22:54:01.575705 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1332 22:54:01.575757 ==
1333 22:54:01.575809 Dram Type= 6, Freq= 0, CH_0, rank 1
1334 22:54:01.575862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1335 22:54:01.575914 ==
1336 22:54:01.575967 DQS Delay:
1337 22:54:01.576019 DQS0 = 0, DQS1 = 0
1338 22:54:01.576071 DQM Delay:
1339 22:54:01.576122 DQM0 = 84, DQM1 = 76
1340 22:54:01.576174 DQ Delay:
1341 22:54:01.576225 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
1342 22:54:01.576277 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =101
1343 22:54:01.576329 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1344 22:54:01.576380 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =77
1345 22:54:01.576432
1346 22:54:01.576496
1347 22:54:01.576551 ==
1348 22:54:01.576604 Dram Type= 6, Freq= 0, CH_0, rank 1
1349 22:54:01.576656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1350 22:54:01.576709 ==
1351 22:54:01.576761
1352 22:54:01.576812
1353 22:54:01.576863 TX Vref Scan disable
1354 22:54:01.576915 == TX Byte 0 ==
1355 22:54:01.576967 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1356 22:54:01.577019 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1357 22:54:01.577072 == TX Byte 1 ==
1358 22:54:01.577123 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1359 22:54:01.577176 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1360 22:54:01.577227 ==
1361 22:54:01.577279 Dram Type= 6, Freq= 0, CH_0, rank 1
1362 22:54:01.577335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1363 22:54:01.577388 ==
1364 22:54:01.577439 TX Vref=22, minBit 4, minWin=27, winSum=443
1365 22:54:01.577492 TX Vref=24, minBit 8, minWin=27, winSum=443
1366 22:54:01.577544 TX Vref=26, minBit 8, minWin=27, winSum=448
1367 22:54:01.577596 TX Vref=28, minBit 9, minWin=27, winSum=446
1368 22:54:01.577647 TX Vref=30, minBit 9, minWin=27, winSum=446
1369 22:54:01.577699 TX Vref=32, minBit 9, minWin=27, winSum=446
1370 22:54:01.577751 [TxChooseVref] Worse bit 8, Min win 27, Win sum 448, Final Vref 26
1371 22:54:01.577803
1372 22:54:01.577853 Final TX Range 1 Vref 26
1373 22:54:01.577904
1374 22:54:01.577956 ==
1375 22:54:01.578034 Dram Type= 6, Freq= 0, CH_0, rank 1
1376 22:54:01.578102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1377 22:54:01.578154 ==
1378 22:54:01.578205
1379 22:54:01.578256
1380 22:54:01.578306 TX Vref Scan disable
1381 22:54:01.578358 == TX Byte 0 ==
1382 22:54:01.578409 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1383 22:54:01.578650 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1384 22:54:01.578709 == TX Byte 1 ==
1385 22:54:01.578762 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1386 22:54:01.578814 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1387 22:54:01.578866
1388 22:54:01.578918 [DATLAT]
1389 22:54:01.578969 Freq=800, CH0 RK1
1390 22:54:01.579022
1391 22:54:01.579074 DATLAT Default: 0xa
1392 22:54:01.579126 0, 0xFFFF, sum = 0
1393 22:54:01.579180 1, 0xFFFF, sum = 0
1394 22:54:01.579232 2, 0xFFFF, sum = 0
1395 22:54:01.579284 3, 0xFFFF, sum = 0
1396 22:54:01.579336 4, 0xFFFF, sum = 0
1397 22:54:01.579388 5, 0xFFFF, sum = 0
1398 22:54:01.579441 6, 0xFFFF, sum = 0
1399 22:54:01.579493 7, 0xFFFF, sum = 0
1400 22:54:01.579545 8, 0xFFFF, sum = 0
1401 22:54:01.579597 9, 0x0, sum = 1
1402 22:54:01.579649 10, 0x0, sum = 2
1403 22:54:01.579701 11, 0x0, sum = 3
1404 22:54:01.579755 12, 0x0, sum = 4
1405 22:54:01.579807 best_step = 10
1406 22:54:01.579858
1407 22:54:01.579909 ==
1408 22:54:01.579961 Dram Type= 6, Freq= 0, CH_0, rank 1
1409 22:54:01.580047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1410 22:54:01.580098 ==
1411 22:54:01.580150 RX Vref Scan: 0
1412 22:54:01.580201
1413 22:54:01.580252 RX Vref 0 -> 0, step: 1
1414 22:54:01.580303
1415 22:54:01.580354 RX Delay -111 -> 252, step: 8
1416 22:54:01.580405 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1417 22:54:01.580457 iDelay=217, Bit 1, Center 92 (-23 ~ 208) 232
1418 22:54:01.580509 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
1419 22:54:01.580560 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1420 22:54:01.580612 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1421 22:54:01.580663 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1422 22:54:01.580715 iDelay=217, Bit 6, Center 96 (-15 ~ 208) 224
1423 22:54:01.580766 iDelay=217, Bit 7, Center 100 (-15 ~ 216) 232
1424 22:54:01.580818 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1425 22:54:01.580869 iDelay=217, Bit 9, Center 64 (-47 ~ 176) 224
1426 22:54:01.580921 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1427 22:54:01.580972 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1428 22:54:01.581023 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1429 22:54:01.581074 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1430 22:54:01.581126 iDelay=217, Bit 14, Center 88 (-23 ~ 200) 224
1431 22:54:01.581177 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1432 22:54:01.581228 ==
1433 22:54:01.581280 Dram Type= 6, Freq= 0, CH_0, rank 1
1434 22:54:01.581340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1435 22:54:01.581395 ==
1436 22:54:01.581447 DQS Delay:
1437 22:54:01.581514 DQS0 = 0, DQS1 = 0
1438 22:54:01.581568 DQM Delay:
1439 22:54:01.581620 DQM0 = 86, DQM1 = 76
1440 22:54:01.581671 DQ Delay:
1441 22:54:01.581723 DQ0 =84, DQ1 =92, DQ2 =76, DQ3 =84
1442 22:54:01.581775 DQ4 =84, DQ5 =76, DQ6 =96, DQ7 =100
1443 22:54:01.581827 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
1444 22:54:01.581879 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =84
1445 22:54:01.581931
1446 22:54:01.581982
1447 22:54:01.582033 [DQSOSCAuto] RK1, (LSB)MR18= 0x4008, (MSB)MR19= 0x606, tDQSOscB0 = 408 ps tDQSOscB1 = 393 ps
1448 22:54:01.582085 CH0 RK1: MR19=606, MR18=4008
1449 22:54:01.582137 CH0_RK1: MR19=0x606, MR18=0x4008, DQSOSC=393, MR23=63, INC=95, DEC=63
1450 22:54:01.582190 [RxdqsGatingPostProcess] freq 800
1451 22:54:01.582241 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1452 22:54:01.582293 Pre-setting of DQS Precalculation
1453 22:54:01.582345 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1454 22:54:01.582397 ==
1455 22:54:01.582449 Dram Type= 6, Freq= 0, CH_1, rank 0
1456 22:54:01.582501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1457 22:54:01.582552 ==
1458 22:54:01.582604 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1459 22:54:01.582655 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1460 22:54:01.582707 [CA 0] Center 36 (6~67) winsize 62
1461 22:54:01.582758 [CA 1] Center 36 (6~67) winsize 62
1462 22:54:01.582810 [CA 2] Center 34 (4~65) winsize 62
1463 22:54:01.582860 [CA 3] Center 34 (3~65) winsize 63
1464 22:54:01.582911 [CA 4] Center 34 (4~65) winsize 62
1465 22:54:01.582962 [CA 5] Center 34 (4~65) winsize 62
1466 22:54:01.583013
1467 22:54:01.583064 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1468 22:54:01.583116
1469 22:54:01.583167 [CATrainingPosCal] consider 1 rank data
1470 22:54:01.583218 u2DelayCellTimex100 = 270/100 ps
1471 22:54:01.583270 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1472 22:54:01.583321 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1473 22:54:01.583372 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1474 22:54:01.583423 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1475 22:54:01.583474 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1476 22:54:01.583525 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1477 22:54:01.583576
1478 22:54:01.583627 CA PerBit enable=1, Macro0, CA PI delay=34
1479 22:54:01.583677
1480 22:54:01.583728 [CBTSetCACLKResult] CA Dly = 34
1481 22:54:01.583780 CS Dly: 5 (0~36)
1482 22:54:01.583832 ==
1483 22:54:01.583883 Dram Type= 6, Freq= 0, CH_1, rank 1
1484 22:54:01.583934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1485 22:54:01.583986 ==
1486 22:54:01.584056 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1487 22:54:01.584155 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1488 22:54:01.584236 [CA 0] Center 36 (6~67) winsize 62
1489 22:54:01.584290 [CA 1] Center 37 (6~68) winsize 63
1490 22:54:01.584343 [CA 2] Center 34 (4~65) winsize 62
1491 22:54:01.584394 [CA 3] Center 34 (3~65) winsize 63
1492 22:54:01.584446 [CA 4] Center 34 (4~65) winsize 62
1493 22:54:01.584498 [CA 5] Center 34 (4~65) winsize 62
1494 22:54:01.584562
1495 22:54:01.584645 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1496 22:54:01.584739
1497 22:54:01.584807 [CATrainingPosCal] consider 2 rank data
1498 22:54:01.584862 u2DelayCellTimex100 = 270/100 ps
1499 22:54:01.584914 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1500 22:54:01.584967 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1501 22:54:01.585019 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1502 22:54:01.585071 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1503 22:54:01.585122 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1504 22:54:01.585174 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1505 22:54:01.585226
1506 22:54:01.585278 CA PerBit enable=1, Macro0, CA PI delay=34
1507 22:54:01.585336
1508 22:54:01.585390 [CBTSetCACLKResult] CA Dly = 34
1509 22:54:01.585443 CS Dly: 5 (0~37)
1510 22:54:01.585494
1511 22:54:01.585546 ----->DramcWriteLeveling(PI) begin...
1512 22:54:01.585599 ==
1513 22:54:01.585651 Dram Type= 6, Freq= 0, CH_1, rank 0
1514 22:54:01.585703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1515 22:54:01.585755 ==
1516 22:54:01.585806 Write leveling (Byte 0): 26 => 26
1517 22:54:01.586084 Write leveling (Byte 1): 27 => 27
1518 22:54:01.586185 DramcWriteLeveling(PI) end<-----
1519 22:54:01.586238
1520 22:54:01.586291 ==
1521 22:54:01.586343 Dram Type= 6, Freq= 0, CH_1, rank 0
1522 22:54:01.586395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1523 22:54:01.586449 ==
1524 22:54:01.586501 [Gating] SW mode calibration
1525 22:54:01.586553 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1526 22:54:01.586606 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1527 22:54:01.586658 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1528 22:54:01.586710 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1529 22:54:01.586762 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 22:54:01.586814 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 22:54:01.586866 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 22:54:01.586918 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 22:54:01.586969 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 22:54:01.587021 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 22:54:01.587072 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 22:54:01.587124 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 22:54:01.587175 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 22:54:01.587227 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 22:54:01.587278 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 22:54:01.587329 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 22:54:01.587380 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 22:54:01.587432 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 22:54:01.587483 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 22:54:01.587535 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1545 22:54:01.587586 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 22:54:01.587638 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 22:54:01.587689 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 22:54:01.587741 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 22:54:01.587792 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 22:54:01.587843 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 22:54:01.587895 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 22:54:01.587947 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
1553 22:54:01.587998 0 9 8 | B1->B0 | 2d2d 2f2f | 0 1 | (0 0) (1 1)
1554 22:54:01.588050 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1555 22:54:01.588101 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1556 22:54:01.588152 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1557 22:54:01.588205 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1558 22:54:01.588256 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1559 22:54:01.588308 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1560 22:54:01.588359 0 10 4 | B1->B0 | 3333 3434 | 1 0 | (1 1) (0 1)
1561 22:54:01.588410 0 10 8 | B1->B0 | 2c2c 2525 | 1 0 | (1 0) (0 0)
1562 22:54:01.588462 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1563 22:54:01.588513 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1564 22:54:01.588565 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1565 22:54:01.588616 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1566 22:54:01.588668 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1567 22:54:01.588720 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1568 22:54:01.588771 0 11 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1569 22:54:01.588823 0 11 8 | B1->B0 | 3939 3f3f | 0 1 | (1 1) (1 1)
1570 22:54:01.588874 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1571 22:54:01.588926 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1572 22:54:01.588977 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1573 22:54:01.589029 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1574 22:54:01.589080 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1575 22:54:01.589132 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1576 22:54:01.589184 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1577 22:54:01.589235 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 22:54:01.589287 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 22:54:01.589371 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 22:54:01.589452 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 22:54:01.589505 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 22:54:01.589556 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 22:54:01.589608 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1584 22:54:01.589660 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1585 22:54:01.589712 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1586 22:54:01.589763 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1587 22:54:01.589815 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1588 22:54:01.589867 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1589 22:54:01.589918 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1590 22:54:01.589971 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1591 22:54:01.590022 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1592 22:54:01.590074 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1593 22:54:01.590126 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1594 22:54:01.590177 Total UI for P1: 0, mck2ui 16
1595 22:54:01.590229 best dqsien dly found for B0: ( 0, 14, 2)
1596 22:54:01.590281 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1597 22:54:01.590333 Total UI for P1: 0, mck2ui 16
1598 22:54:01.590385 best dqsien dly found for B1: ( 0, 14, 8)
1599 22:54:01.590436 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1600 22:54:01.590488 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1601 22:54:01.590539
1602 22:54:01.590590 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1603 22:54:01.590831 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1604 22:54:01.590889 [Gating] SW calibration Done
1605 22:54:01.590941 ==
1606 22:54:01.590994 Dram Type= 6, Freq= 0, CH_1, rank 0
1607 22:54:01.591046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1608 22:54:01.591099 ==
1609 22:54:01.591150 RX Vref Scan: 0
1610 22:54:01.591202
1611 22:54:01.591253 RX Vref 0 -> 0, step: 1
1612 22:54:01.591304
1613 22:54:01.591355 RX Delay -130 -> 252, step: 16
1614 22:54:01.591407 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1615 22:54:01.591458 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1616 22:54:01.591510 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1617 22:54:01.591562 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1618 22:54:01.591613 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1619 22:54:01.591665 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1620 22:54:01.591716 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1621 22:54:01.591768 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1622 22:54:01.591819 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1623 22:54:01.591871 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1624 22:54:01.591922 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1625 22:54:01.591973 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1626 22:54:01.592025 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1627 22:54:01.592076 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1628 22:54:01.592128 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1629 22:54:01.592180 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1630 22:54:01.592231 ==
1631 22:54:01.592283 Dram Type= 6, Freq= 0, CH_1, rank 0
1632 22:54:01.592334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1633 22:54:01.592386 ==
1634 22:54:01.592438 DQS Delay:
1635 22:54:01.592489 DQS0 = 0, DQS1 = 0
1636 22:54:01.592541 DQM Delay:
1637 22:54:01.592592 DQM0 = 89, DQM1 = 78
1638 22:54:01.592644 DQ Delay:
1639 22:54:01.592696 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1640 22:54:01.592748 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1641 22:54:01.592799 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1642 22:54:01.592851 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1643 22:54:01.592903
1644 22:54:01.592953
1645 22:54:01.593004 ==
1646 22:54:01.593056 Dram Type= 6, Freq= 0, CH_1, rank 0
1647 22:54:01.593108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1648 22:54:01.593159 ==
1649 22:54:01.593211
1650 22:54:01.593262
1651 22:54:01.593313 TX Vref Scan disable
1652 22:54:01.593409 == TX Byte 0 ==
1653 22:54:01.593462 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1654 22:54:01.593514 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1655 22:54:01.593565 == TX Byte 1 ==
1656 22:54:01.593617 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1657 22:54:01.593669 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1658 22:54:01.593720 ==
1659 22:54:01.593772 Dram Type= 6, Freq= 0, CH_1, rank 0
1660 22:54:01.593823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1661 22:54:01.593875 ==
1662 22:54:01.593927 TX Vref=22, minBit 10, minWin=26, winSum=442
1663 22:54:01.593979 TX Vref=24, minBit 10, minWin=27, winSum=447
1664 22:54:01.594031 TX Vref=26, minBit 12, minWin=27, winSum=449
1665 22:54:01.594083 TX Vref=28, minBit 9, minWin=27, winSum=451
1666 22:54:01.594135 TX Vref=30, minBit 15, minWin=27, winSum=451
1667 22:54:01.594186 TX Vref=32, minBit 9, minWin=27, winSum=447
1668 22:54:01.594238 [TxChooseVref] Worse bit 9, Min win 27, Win sum 451, Final Vref 28
1669 22:54:01.594292
1670 22:54:01.594343 Final TX Range 1 Vref 28
1671 22:54:01.594396
1672 22:54:01.594447 ==
1673 22:54:01.594499 Dram Type= 6, Freq= 0, CH_1, rank 0
1674 22:54:01.594550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1675 22:54:01.594602 ==
1676 22:54:01.594653
1677 22:54:01.594704
1678 22:54:01.594755 TX Vref Scan disable
1679 22:54:01.594807 == TX Byte 0 ==
1680 22:54:01.594858 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1681 22:54:01.594910 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1682 22:54:01.594962 == TX Byte 1 ==
1683 22:54:01.595013 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1684 22:54:01.595065 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1685 22:54:01.595116
1686 22:54:01.595178 [DATLAT]
1687 22:54:01.595263 Freq=800, CH1 RK0
1688 22:54:01.595357
1689 22:54:01.595439 DATLAT Default: 0xa
1690 22:54:01.595496 0, 0xFFFF, sum = 0
1691 22:54:01.595551 1, 0xFFFF, sum = 0
1692 22:54:01.595605 2, 0xFFFF, sum = 0
1693 22:54:01.595658 3, 0xFFFF, sum = 0
1694 22:54:01.595711 4, 0xFFFF, sum = 0
1695 22:54:01.595763 5, 0xFFFF, sum = 0
1696 22:54:01.595816 6, 0xFFFF, sum = 0
1697 22:54:01.595868 7, 0xFFFF, sum = 0
1698 22:54:01.595921 8, 0xFFFF, sum = 0
1699 22:54:01.595973 9, 0x0, sum = 1
1700 22:54:01.596025 10, 0x0, sum = 2
1701 22:54:01.596077 11, 0x0, sum = 3
1702 22:54:01.596129 12, 0x0, sum = 4
1703 22:54:01.596181 best_step = 10
1704 22:54:01.596233
1705 22:54:01.596284 ==
1706 22:54:01.596336 Dram Type= 6, Freq= 0, CH_1, rank 0
1707 22:54:01.596388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1708 22:54:01.596440 ==
1709 22:54:01.596492 RX Vref Scan: 1
1710 22:54:01.596544
1711 22:54:01.596595 Set Vref Range= 32 -> 127
1712 22:54:01.596646
1713 22:54:01.596698 RX Vref 32 -> 127, step: 1
1714 22:54:01.596750
1715 22:54:01.596802 RX Delay -95 -> 252, step: 8
1716 22:54:01.596854
1717 22:54:01.596905 Set Vref, RX VrefLevel [Byte0]: 32
1718 22:54:01.596957 [Byte1]: 32
1719 22:54:01.597009
1720 22:54:01.597060 Set Vref, RX VrefLevel [Byte0]: 33
1721 22:54:01.597111 [Byte1]: 33
1722 22:54:01.597163
1723 22:54:01.597213 Set Vref, RX VrefLevel [Byte0]: 34
1724 22:54:01.597265 [Byte1]: 34
1725 22:54:01.597316
1726 22:54:01.597400 Set Vref, RX VrefLevel [Byte0]: 35
1727 22:54:01.597466 [Byte1]: 35
1728 22:54:01.597517
1729 22:54:01.597568 Set Vref, RX VrefLevel [Byte0]: 36
1730 22:54:01.597620 [Byte1]: 36
1731 22:54:01.597671
1732 22:54:01.597723 Set Vref, RX VrefLevel [Byte0]: 37
1733 22:54:01.597774 [Byte1]: 37
1734 22:54:01.597826
1735 22:54:01.597876 Set Vref, RX VrefLevel [Byte0]: 38
1736 22:54:01.597928 [Byte1]: 38
1737 22:54:01.597979
1738 22:54:01.598030 Set Vref, RX VrefLevel [Byte0]: 39
1739 22:54:01.598082 [Byte1]: 39
1740 22:54:01.598133
1741 22:54:01.598185 Set Vref, RX VrefLevel [Byte0]: 40
1742 22:54:01.598236 [Byte1]: 40
1743 22:54:01.598287
1744 22:54:01.598338 Set Vref, RX VrefLevel [Byte0]: 41
1745 22:54:01.598389 [Byte1]: 41
1746 22:54:01.598440
1747 22:54:01.598491 Set Vref, RX VrefLevel [Byte0]: 42
1748 22:54:01.598543 [Byte1]: 42
1749 22:54:01.598594
1750 22:54:01.598679 Set Vref, RX VrefLevel [Byte0]: 43
1751 22:54:01.598766 [Byte1]: 43
1752 22:54:01.598855
1753 22:54:01.598912 Set Vref, RX VrefLevel [Byte0]: 44
1754 22:54:01.598965 [Byte1]: 44
1755 22:54:01.599017
1756 22:54:01.599069 Set Vref, RX VrefLevel [Byte0]: 45
1757 22:54:01.599123 [Byte1]: 45
1758 22:54:01.599174
1759 22:54:01.599226 Set Vref, RX VrefLevel [Byte0]: 46
1760 22:54:01.599472 [Byte1]: 46
1761 22:54:01.599533
1762 22:54:01.599585 Set Vref, RX VrefLevel [Byte0]: 47
1763 22:54:01.599638 [Byte1]: 47
1764 22:54:01.599691
1765 22:54:01.599742 Set Vref, RX VrefLevel [Byte0]: 48
1766 22:54:01.599794 [Byte1]: 48
1767 22:54:01.599845
1768 22:54:01.599896 Set Vref, RX VrefLevel [Byte0]: 49
1769 22:54:01.599948 [Byte1]: 49
1770 22:54:01.599999
1771 22:54:01.600050 Set Vref, RX VrefLevel [Byte0]: 50
1772 22:54:01.600102 [Byte1]: 50
1773 22:54:01.600153
1774 22:54:01.600204 Set Vref, RX VrefLevel [Byte0]: 51
1775 22:54:01.600255 [Byte1]: 51
1776 22:54:01.600307
1777 22:54:01.600358 Set Vref, RX VrefLevel [Byte0]: 52
1778 22:54:01.600410 [Byte1]: 52
1779 22:54:01.600461
1780 22:54:01.600512 Set Vref, RX VrefLevel [Byte0]: 53
1781 22:54:01.600564 [Byte1]: 53
1782 22:54:01.600615
1783 22:54:01.600666 Set Vref, RX VrefLevel [Byte0]: 54
1784 22:54:01.600717 [Byte1]: 54
1785 22:54:01.600769
1786 22:54:01.600820 Set Vref, RX VrefLevel [Byte0]: 55
1787 22:54:01.600872 [Byte1]: 55
1788 22:54:01.600923
1789 22:54:01.600974 Set Vref, RX VrefLevel [Byte0]: 56
1790 22:54:01.601026 [Byte1]: 56
1791 22:54:01.601077
1792 22:54:01.601128 Set Vref, RX VrefLevel [Byte0]: 57
1793 22:54:01.601179 [Byte1]: 57
1794 22:54:01.601230
1795 22:54:01.601281 Set Vref, RX VrefLevel [Byte0]: 58
1796 22:54:01.601345 [Byte1]: 58
1797 22:54:01.601437
1798 22:54:01.601489 Set Vref, RX VrefLevel [Byte0]: 59
1799 22:54:01.601542 [Byte1]: 59
1800 22:54:01.601594
1801 22:54:01.601645 Set Vref, RX VrefLevel [Byte0]: 60
1802 22:54:01.601697 [Byte1]: 60
1803 22:54:01.601748
1804 22:54:01.601800 Set Vref, RX VrefLevel [Byte0]: 61
1805 22:54:01.601851 [Byte1]: 61
1806 22:54:01.601902
1807 22:54:01.601953 Set Vref, RX VrefLevel [Byte0]: 62
1808 22:54:01.602005 [Byte1]: 62
1809 22:54:01.602056
1810 22:54:01.602147 Set Vref, RX VrefLevel [Byte0]: 63
1811 22:54:01.602243 [Byte1]: 63
1812 22:54:01.602318
1813 22:54:01.602372 Set Vref, RX VrefLevel [Byte0]: 64
1814 22:54:01.602425 [Byte1]: 64
1815 22:54:01.602477
1816 22:54:01.602529 Set Vref, RX VrefLevel [Byte0]: 65
1817 22:54:01.602581 [Byte1]: 65
1818 22:54:01.602632
1819 22:54:01.602684 Set Vref, RX VrefLevel [Byte0]: 66
1820 22:54:01.602735 [Byte1]: 66
1821 22:54:01.602787
1822 22:54:01.602838 Set Vref, RX VrefLevel [Byte0]: 67
1823 22:54:01.602890 [Byte1]: 67
1824 22:54:01.602941
1825 22:54:01.602992 Set Vref, RX VrefLevel [Byte0]: 68
1826 22:54:01.603043 [Byte1]: 68
1827 22:54:01.603095
1828 22:54:01.603146 Set Vref, RX VrefLevel [Byte0]: 69
1829 22:54:01.603198 [Byte1]: 69
1830 22:54:01.603250
1831 22:54:01.603300 Set Vref, RX VrefLevel [Byte0]: 70
1832 22:54:01.603352 [Byte1]: 70
1833 22:54:01.603404
1834 22:54:01.603455 Set Vref, RX VrefLevel [Byte0]: 71
1835 22:54:01.603507 [Byte1]: 71
1836 22:54:01.603558
1837 22:54:01.603609 Set Vref, RX VrefLevel [Byte0]: 72
1838 22:54:01.603661 [Byte1]: 72
1839 22:54:01.603712
1840 22:54:01.603764 Set Vref, RX VrefLevel [Byte0]: 73
1841 22:54:01.603817 [Byte1]: 73
1842 22:54:01.603869
1843 22:54:01.603920 Set Vref, RX VrefLevel [Byte0]: 74
1844 22:54:01.603970 [Byte1]: 74
1845 22:54:01.604022
1846 22:54:01.604073 Final RX Vref Byte 0 = 58 to rank0
1847 22:54:01.604125 Final RX Vref Byte 1 = 64 to rank0
1848 22:54:01.604176 Final RX Vref Byte 0 = 58 to rank1
1849 22:54:01.604228 Final RX Vref Byte 1 = 64 to rank1==
1850 22:54:01.604280 Dram Type= 6, Freq= 0, CH_1, rank 0
1851 22:54:01.604331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1852 22:54:01.604383 ==
1853 22:54:01.604435 DQS Delay:
1854 22:54:01.604486 DQS0 = 0, DQS1 = 0
1855 22:54:01.604537 DQM Delay:
1856 22:54:01.604588 DQM0 = 86, DQM1 = 79
1857 22:54:01.604640 DQ Delay:
1858 22:54:01.604691 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1859 22:54:01.604744 DQ4 =80, DQ5 =100, DQ6 =96, DQ7 =80
1860 22:54:01.604795 DQ8 =68, DQ9 =68, DQ10 =84, DQ11 =68
1861 22:54:01.604847 DQ12 =88, DQ13 =84, DQ14 =88, DQ15 =88
1862 22:54:01.604899
1863 22:54:01.604950
1864 22:54:01.605001 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e1b, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 398 ps
1865 22:54:01.605053 CH1 RK0: MR19=606, MR18=2E1B
1866 22:54:01.605105 CH1_RK0: MR19=0x606, MR18=0x2E1B, DQSOSC=398, MR23=63, INC=93, DEC=62
1867 22:54:01.605157
1868 22:54:01.605208 ----->DramcWriteLeveling(PI) begin...
1869 22:54:01.605261 ==
1870 22:54:01.605313 Dram Type= 6, Freq= 0, CH_1, rank 1
1871 22:54:01.605398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1872 22:54:01.605463 ==
1873 22:54:01.605515 Write leveling (Byte 0): 26 => 26
1874 22:54:01.605567 Write leveling (Byte 1): 28 => 28
1875 22:54:01.605619 DramcWriteLeveling(PI) end<-----
1876 22:54:01.605670
1877 22:54:01.605721 ==
1878 22:54:01.605772 Dram Type= 6, Freq= 0, CH_1, rank 1
1879 22:54:01.605823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1880 22:54:01.605875 ==
1881 22:54:01.605926 [Gating] SW mode calibration
1882 22:54:01.605979 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1883 22:54:01.606031 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1884 22:54:01.606083 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1885 22:54:01.606135 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1886 22:54:01.606187 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1887 22:54:01.606238 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 22:54:01.606289 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 22:54:01.606341 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 22:54:01.606392 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 22:54:01.606443 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 22:54:01.606494 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 22:54:01.606546 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 22:54:01.606597 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 22:54:01.606652 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 22:54:01.606737 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 22:54:01.606827 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 22:54:01.606913 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 22:54:01.607160 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 22:54:01.607220 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 22:54:01.607274 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1902 22:54:01.607326 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1903 22:54:01.607379 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 22:54:01.607431 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 22:54:01.607483 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 22:54:01.607534 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 22:54:01.607586 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 22:54:01.607638 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 22:54:01.607690 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 22:54:01.607741 0 9 8 | B1->B0 | 3232 2828 | 1 0 | (0 0) (0 0)
1911 22:54:01.607793 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1912 22:54:01.607844 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1913 22:54:01.607896 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1914 22:54:01.607947 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1915 22:54:01.607999 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1916 22:54:01.608051 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1917 22:54:01.608103 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
1918 22:54:01.608154 0 10 8 | B1->B0 | 2929 2e2e | 0 1 | (1 0) (1 0)
1919 22:54:01.608206 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1920 22:54:01.608258 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1921 22:54:01.608310 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1922 22:54:01.608362 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1923 22:54:01.608413 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1924 22:54:01.608465 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1925 22:54:01.608517 0 11 4 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
1926 22:54:01.608568 0 11 8 | B1->B0 | 3b3b 3a3a | 1 0 | (0 0) (1 1)
1927 22:54:01.608620 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1928 22:54:01.608672 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1929 22:54:01.608723 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1930 22:54:01.608774 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1931 22:54:01.608826 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1932 22:54:01.608877 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1933 22:54:01.608928 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1934 22:54:01.608979 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 22:54:01.609031 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 22:54:01.609082 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 22:54:01.609133 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 22:54:01.609185 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 22:54:01.609236 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 22:54:01.609287 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 22:54:01.609346 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 22:54:01.609439 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 22:54:01.609490 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1944 22:54:01.609541 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1945 22:54:01.609593 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1946 22:54:01.609645 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1947 22:54:01.609696 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1948 22:54:01.609753 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1949 22:54:01.609805 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1950 22:54:01.609857 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1951 22:54:01.609908 Total UI for P1: 0, mck2ui 16
1952 22:54:01.609960 best dqsien dly found for B0: ( 0, 14, 4)
1953 22:54:01.610012 Total UI for P1: 0, mck2ui 16
1954 22:54:01.610064 best dqsien dly found for B1: ( 0, 14, 4)
1955 22:54:01.610116 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1956 22:54:01.610167 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1957 22:54:01.610218
1958 22:54:01.610269 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1959 22:54:01.610321 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1960 22:54:01.610372 [Gating] SW calibration Done
1961 22:54:01.610423 ==
1962 22:54:01.610475 Dram Type= 6, Freq= 0, CH_1, rank 1
1963 22:54:01.610526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1964 22:54:01.610578 ==
1965 22:54:01.610629 RX Vref Scan: 0
1966 22:54:01.610681
1967 22:54:01.610731 RX Vref 0 -> 0, step: 1
1968 22:54:01.610783
1969 22:54:01.610834 RX Delay -130 -> 252, step: 16
1970 22:54:01.610885 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1971 22:54:01.610937 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1972 22:54:01.610988 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1973 22:54:01.611040 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1974 22:54:01.611091 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1975 22:54:01.611142 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1976 22:54:01.611193 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1977 22:54:01.611244 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1978 22:54:01.611295 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1979 22:54:01.611347 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1980 22:54:01.611398 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1981 22:54:01.611449 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1982 22:54:01.611501 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1983 22:54:01.611552 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1984 22:54:01.611604 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1985 22:54:01.611656 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1986 22:54:01.759666 ==
1987 22:54:01.760141 Dram Type= 6, Freq= 0, CH_1, rank 1
1988 22:54:01.760467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1989 22:54:01.760771 ==
1990 22:54:01.761077 DQS Delay:
1991 22:54:01.761443 DQS0 = 0, DQS1 = 0
1992 22:54:01.761746 DQM Delay:
1993 22:54:01.762027 DQM0 = 88, DQM1 = 79
1994 22:54:01.762351 DQ Delay:
1995 22:54:01.763027 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1996 22:54:01.763342 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1997 22:54:01.763624 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1998 22:54:01.763901 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1999 22:54:01.764174
2000 22:54:01.764445
2001 22:54:01.764911 ==
2002 22:54:01.765192 Dram Type= 6, Freq= 0, CH_1, rank 1
2003 22:54:01.765500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2004 22:54:01.765871 ==
2005 22:54:01.766146
2006 22:54:01.766414
2007 22:54:01.766681 TX Vref Scan disable
2008 22:54:01.766950 == TX Byte 0 ==
2009 22:54:01.767395 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2010 22:54:01.767868 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2011 22:54:01.768207 == TX Byte 1 ==
2012 22:54:01.768487 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2013 22:54:01.768760 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2014 22:54:01.769029 ==
2015 22:54:01.769549 Dram Type= 6, Freq= 0, CH_1, rank 1
2016 22:54:01.770023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2017 22:54:01.770798 ==
2018 22:54:01.771275 TX Vref=22, minBit 8, minWin=27, winSum=446
2019 22:54:01.771667 TX Vref=24, minBit 1, minWin=27, winSum=449
2020 22:54:01.772073 TX Vref=26, minBit 15, minWin=27, winSum=452
2021 22:54:01.772364 TX Vref=28, minBit 13, minWin=27, winSum=454
2022 22:54:01.772644 TX Vref=30, minBit 13, minWin=27, winSum=452
2023 22:54:01.772999 TX Vref=32, minBit 8, minWin=27, winSum=445
2024 22:54:01.773356 [TxChooseVref] Worse bit 13, Min win 27, Win sum 454, Final Vref 28
2025 22:54:01.773649
2026 22:54:01.773919 Final TX Range 1 Vref 28
2027 22:54:01.774195
2028 22:54:01.774463 ==
2029 22:54:01.774799 Dram Type= 6, Freq= 0, CH_1, rank 1
2030 22:54:01.775079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2031 22:54:01.775354 ==
2032 22:54:01.775622
2033 22:54:01.775888
2034 22:54:01.776155 TX Vref Scan disable
2035 22:54:01.776423 == TX Byte 0 ==
2036 22:54:01.776691 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2037 22:54:01.777038 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2038 22:54:01.777319 == TX Byte 1 ==
2039 22:54:01.777656 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2040 22:54:01.777929 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2041 22:54:01.778220
2042 22:54:01.778502 [DATLAT]
2043 22:54:01.778770 Freq=800, CH1 RK1
2044 22:54:01.779060
2045 22:54:01.779346 DATLAT Default: 0xa
2046 22:54:01.779616 0, 0xFFFF, sum = 0
2047 22:54:01.779891 1, 0xFFFF, sum = 0
2048 22:54:01.780176 2, 0xFFFF, sum = 0
2049 22:54:01.780462 3, 0xFFFF, sum = 0
2050 22:54:01.780739 4, 0xFFFF, sum = 0
2051 22:54:01.781131 5, 0xFFFF, sum = 0
2052 22:54:01.781699 6, 0xFFFF, sum = 0
2053 22:54:01.782077 7, 0xFFFF, sum = 0
2054 22:54:01.782360 8, 0xFFFF, sum = 0
2055 22:54:01.782634 9, 0x0, sum = 1
2056 22:54:01.782905 10, 0x0, sum = 2
2057 22:54:01.783177 11, 0x0, sum = 3
2058 22:54:01.783446 12, 0x0, sum = 4
2059 22:54:01.783716 best_step = 10
2060 22:54:01.783982
2061 22:54:01.784273 ==
2062 22:54:01.784741 Dram Type= 6, Freq= 0, CH_1, rank 1
2063 22:54:01.785169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2064 22:54:01.785496 ==
2065 22:54:01.785705 RX Vref Scan: 0
2066 22:54:01.785904
2067 22:54:01.786099 RX Vref 0 -> 0, step: 1
2068 22:54:01.786292
2069 22:54:01.786483 RX Delay -95 -> 252, step: 8
2070 22:54:01.786811 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2071 22:54:01.787017 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2072 22:54:01.787210 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
2073 22:54:01.787404 iDelay=217, Bit 3, Center 88 (-23 ~ 200) 224
2074 22:54:01.787692 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2075 22:54:01.787894 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2076 22:54:01.788086 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2077 22:54:01.788303 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2078 22:54:01.788558 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2079 22:54:01.788867 iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232
2080 22:54:01.789102 iDelay=217, Bit 10, Center 84 (-31 ~ 200) 232
2081 22:54:01.789474 iDelay=217, Bit 11, Center 72 (-39 ~ 184) 224
2082 22:54:01.789761 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
2083 22:54:01.789974 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2084 22:54:01.790120 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2085 22:54:01.790267 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2086 22:54:01.790411 ==
2087 22:54:01.790557 Dram Type= 6, Freq= 0, CH_1, rank 1
2088 22:54:01.790703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2089 22:54:01.790849 ==
2090 22:54:01.790993 DQS Delay:
2091 22:54:01.791139 DQS0 = 0, DQS1 = 0
2092 22:54:01.791282 DQM Delay:
2093 22:54:01.791425 DQM0 = 87, DQM1 = 79
2094 22:54:01.791568 DQ Delay:
2095 22:54:01.791711 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =88
2096 22:54:01.791854 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2097 22:54:01.791998 DQ8 =68, DQ9 =68, DQ10 =84, DQ11 =72
2098 22:54:01.792141 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
2099 22:54:01.792283
2100 22:54:01.792426
2101 22:54:01.792570 [DQSOSCAuto] RK1, (LSB)MR18= 0x1910, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
2102 22:54:01.792717 CH1 RK1: MR19=606, MR18=1910
2103 22:54:01.792861 CH1_RK1: MR19=0x606, MR18=0x1910, DQSOSC=403, MR23=63, INC=90, DEC=60
2104 22:54:01.793005 [RxdqsGatingPostProcess] freq 800
2105 22:54:01.793148 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2106 22:54:01.793292 Pre-setting of DQS Precalculation
2107 22:54:01.793456 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2108 22:54:01.793603 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2109 22:54:01.793751 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2110 22:54:01.793898
2111 22:54:01.794040
2112 22:54:01.794183 [Calibration Summary] 1600 Mbps
2113 22:54:01.794328 CH 0, Rank 0
2114 22:54:01.794472 SW Impedance : PASS
2115 22:54:01.794615 DUTY Scan : NO K
2116 22:54:01.794759 ZQ Calibration : PASS
2117 22:54:01.794906 Jitter Meter : NO K
2118 22:54:01.795044 CBT Training : PASS
2119 22:54:01.795160 Write leveling : PASS
2120 22:54:01.795274 RX DQS gating : PASS
2121 22:54:01.795389 RX DQ/DQS(RDDQC) : PASS
2122 22:54:01.795504 TX DQ/DQS : PASS
2123 22:54:01.795621 RX DATLAT : PASS
2124 22:54:01.795736 RX DQ/DQS(Engine): PASS
2125 22:54:01.795851 TX OE : NO K
2126 22:54:01.795967 All Pass.
2127 22:54:01.796112
2128 22:54:01.796230 CH 0, Rank 1
2129 22:54:01.796347 SW Impedance : PASS
2130 22:54:01.796465 DUTY Scan : NO K
2131 22:54:01.796581 ZQ Calibration : PASS
2132 22:54:01.796696 Jitter Meter : NO K
2133 22:54:01.796812 CBT Training : PASS
2134 22:54:01.796928 Write leveling : PASS
2135 22:54:01.797044 RX DQS gating : PASS
2136 22:54:01.797160 RX DQ/DQS(RDDQC) : PASS
2137 22:54:01.797274 TX DQ/DQS : PASS
2138 22:54:01.797400 RX DATLAT : PASS
2139 22:54:01.797517 RX DQ/DQS(Engine): PASS
2140 22:54:01.797886 TX OE : NO K
2141 22:54:01.798018 All Pass.
2142 22:54:01.798138
2143 22:54:01.798296 CH 1, Rank 0
2144 22:54:01.798462 SW Impedance : PASS
2145 22:54:01.798581 DUTY Scan : NO K
2146 22:54:01.798698 ZQ Calibration : PASS
2147 22:54:01.798813 Jitter Meter : NO K
2148 22:54:01.798973 CBT Training : PASS
2149 22:54:01.799091 Write leveling : PASS
2150 22:54:01.799207 RX DQS gating : PASS
2151 22:54:01.799322 RX DQ/DQS(RDDQC) : PASS
2152 22:54:01.799438 TX DQ/DQS : PASS
2153 22:54:01.799553 RX DATLAT : PASS
2154 22:54:01.799669 RX DQ/DQS(Engine): PASS
2155 22:54:01.799785 TX OE : NO K
2156 22:54:01.799901 All Pass.
2157 22:54:01.800022
2158 22:54:01.800119 CH 1, Rank 1
2159 22:54:01.800217 SW Impedance : PASS
2160 22:54:01.800314 DUTY Scan : NO K
2161 22:54:01.800410 ZQ Calibration : PASS
2162 22:54:01.800505 Jitter Meter : NO K
2163 22:54:01.800601 CBT Training : PASS
2164 22:54:01.800698 Write leveling : PASS
2165 22:54:01.800794 RX DQS gating : PASS
2166 22:54:01.800890 RX DQ/DQS(RDDQC) : PASS
2167 22:54:01.800987 TX DQ/DQS : PASS
2168 22:54:01.801083 RX DATLAT : PASS
2169 22:54:01.801180 RX DQ/DQS(Engine): PASS
2170 22:54:01.801277 TX OE : NO K
2171 22:54:01.801385 All Pass.
2172 22:54:01.801483
2173 22:54:01.801579 DramC Write-DBI off
2174 22:54:01.801676 PER_BANK_REFRESH: Hybrid Mode
2175 22:54:01.801773 TX_TRACKING: ON
2176 22:54:01.801870 [GetDramInforAfterCalByMRR] Vendor 6.
2177 22:54:01.801967 [GetDramInforAfterCalByMRR] Revision 606.
2178 22:54:01.802065 [GetDramInforAfterCalByMRR] Revision 2 0.
2179 22:54:01.802161 MR0 0x3b3b
2180 22:54:01.802257 MR8 0x5151
2181 22:54:01.802354 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2182 22:54:01.802451
2183 22:54:01.802547 MR0 0x3b3b
2184 22:54:01.802643 MR8 0x5151
2185 22:54:01.802740 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2186 22:54:01.802837
2187 22:54:01.802934 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2188 22:54:01.803031 [FAST_K] Save calibration result to emmc
2189 22:54:01.803128 [FAST_K] Save calibration result to emmc
2190 22:54:01.803224 dram_init: config_dvfs: 1
2191 22:54:01.803321 dramc_set_vcore_voltage set vcore to 662500
2192 22:54:01.803417 Read voltage for 1200, 2
2193 22:54:01.803513 Vio18 = 0
2194 22:54:01.803609 Vcore = 662500
2195 22:54:01.803706 Vdram = 0
2196 22:54:01.803829 Vddq = 0
2197 22:54:01.803947 Vmddr = 0
2198 22:54:01.804065 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2199 22:54:01.804164 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2200 22:54:01.804262 MEM_TYPE=3, freq_sel=15
2201 22:54:01.804359 sv_algorithm_assistance_LP4_1600
2202 22:54:01.804456 ============ PULL DRAM RESETB DOWN ============
2203 22:54:01.804590 ========== PULL DRAM RESETB DOWN end =========
2204 22:54:01.804754 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2205 22:54:01.804925 ===================================
2206 22:54:01.805095 LPDDR4 DRAM CONFIGURATION
2207 22:54:01.805188 ===================================
2208 22:54:01.805275 EX_ROW_EN[0] = 0x0
2209 22:54:01.805373 EX_ROW_EN[1] = 0x0
2210 22:54:01.805459 LP4Y_EN = 0x0
2211 22:54:01.805544 WORK_FSP = 0x0
2212 22:54:01.805629 WL = 0x4
2213 22:54:01.805712 RL = 0x4
2214 22:54:01.805796 BL = 0x2
2215 22:54:01.805879 RPST = 0x0
2216 22:54:01.805962 RD_PRE = 0x0
2217 22:54:01.806045 WR_PRE = 0x1
2218 22:54:01.806128 WR_PST = 0x0
2219 22:54:01.806209 DBI_WR = 0x0
2220 22:54:01.806292 DBI_RD = 0x0
2221 22:54:01.806374 OTF = 0x1
2222 22:54:01.806458 ===================================
2223 22:54:01.806542 ===================================
2224 22:54:01.806625 ANA top config
2225 22:54:01.806708 ===================================
2226 22:54:01.806791 DLL_ASYNC_EN = 0
2227 22:54:01.806874 ALL_SLAVE_EN = 0
2228 22:54:01.806956 NEW_RANK_MODE = 1
2229 22:54:01.807040 DLL_IDLE_MODE = 1
2230 22:54:01.807122 LP45_APHY_COMB_EN = 1
2231 22:54:01.807205 TX_ODT_DIS = 1
2232 22:54:01.807287 NEW_8X_MODE = 1
2233 22:54:01.807371 ===================================
2234 22:54:01.807455 ===================================
2235 22:54:01.807538 data_rate = 2400
2236 22:54:01.807621 CKR = 1
2237 22:54:01.807721 DQ_P2S_RATIO = 8
2238 22:54:01.807864 ===================================
2239 22:54:01.808023 CA_P2S_RATIO = 8
2240 22:54:01.808126 DQ_CA_OPEN = 0
2241 22:54:01.808212 DQ_SEMI_OPEN = 0
2242 22:54:01.808296 CA_SEMI_OPEN = 0
2243 22:54:01.808381 CA_FULL_RATE = 0
2244 22:54:01.808465 DQ_CKDIV4_EN = 0
2245 22:54:01.808549 CA_CKDIV4_EN = 0
2246 22:54:01.808632 CA_PREDIV_EN = 0
2247 22:54:01.808715 PH8_DLY = 17
2248 22:54:01.808798 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2249 22:54:01.808882 DQ_AAMCK_DIV = 4
2250 22:54:01.808965 CA_AAMCK_DIV = 4
2251 22:54:01.809048 CA_ADMCK_DIV = 4
2252 22:54:01.809130 DQ_TRACK_CA_EN = 0
2253 22:54:01.809213 CA_PICK = 1200
2254 22:54:01.809296 CA_MCKIO = 1200
2255 22:54:01.809393 MCKIO_SEMI = 0
2256 22:54:01.809478 PLL_FREQ = 2366
2257 22:54:01.809562 DQ_UI_PI_RATIO = 32
2258 22:54:01.809646 CA_UI_PI_RATIO = 0
2259 22:54:01.809729 ===================================
2260 22:54:01.809813 ===================================
2261 22:54:01.809897 memory_type:LPDDR4
2262 22:54:01.809987 GP_NUM : 10
2263 22:54:01.810060 SRAM_EN : 1
2264 22:54:01.810132 MD32_EN : 0
2265 22:54:01.810204 ===================================
2266 22:54:01.810278 [ANA_INIT] >>>>>>>>>>>>>>
2267 22:54:01.810351 <<<<<< [CONFIGURE PHASE]: ANA_TX
2268 22:54:01.810426 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2269 22:54:01.810500 ===================================
2270 22:54:01.810573 data_rate = 2400,PCW = 0X5b00
2271 22:54:01.810646 ===================================
2272 22:54:01.810720 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2273 22:54:01.810795 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2274 22:54:01.810884 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2275 22:54:01.811009 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2276 22:54:01.811146 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2277 22:54:01.811236 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2278 22:54:01.811312 [ANA_INIT] flow start
2279 22:54:01.811387 [ANA_INIT] PLL >>>>>>>>
2280 22:54:01.811460 [ANA_INIT] PLL <<<<<<<<
2281 22:54:01.811745 [ANA_INIT] MIDPI >>>>>>>>
2282 22:54:01.811828 [ANA_INIT] MIDPI <<<<<<<<
2283 22:54:01.811903 [ANA_INIT] DLL >>>>>>>>
2284 22:54:01.811977 [ANA_INIT] DLL <<<<<<<<
2285 22:54:01.812050 [ANA_INIT] flow end
2286 22:54:01.812124 ============ LP4 DIFF to SE enter ============
2287 22:54:01.812199 ============ LP4 DIFF to SE exit ============
2288 22:54:01.812273 [ANA_INIT] <<<<<<<<<<<<<
2289 22:54:01.812347 [Flow] Enable top DCM control >>>>>
2290 22:54:01.812421 [Flow] Enable top DCM control <<<<<
2291 22:54:01.812494 Enable DLL master slave shuffle
2292 22:54:01.812567 ==============================================================
2293 22:54:01.812640 Gating Mode config
2294 22:54:01.812713 ==============================================================
2295 22:54:01.812786 Config description:
2296 22:54:01.812859 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2297 22:54:01.812932 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2298 22:54:01.813006 SELPH_MODE 0: By rank 1: By Phase
2299 22:54:01.813080 ==============================================================
2300 22:54:01.813154 GAT_TRACK_EN = 1
2301 22:54:01.813226 RX_GATING_MODE = 2
2302 22:54:01.813299 RX_GATING_TRACK_MODE = 2
2303 22:54:01.813385 SELPH_MODE = 1
2304 22:54:01.813459 PICG_EARLY_EN = 1
2305 22:54:01.813531 VALID_LAT_VALUE = 1
2306 22:54:01.813605 ==============================================================
2307 22:54:01.813679 Enter into Gating configuration >>>>
2308 22:54:01.813752 Exit from Gating configuration <<<<
2309 22:54:01.813825 Enter into DVFS_PRE_config >>>>>
2310 22:54:01.813898 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2311 22:54:01.813974 Exit from DVFS_PRE_config <<<<<
2312 22:54:01.814047 Enter into PICG configuration >>>>
2313 22:54:01.814120 Exit from PICG configuration <<<<
2314 22:54:01.814192 [RX_INPUT] configuration >>>>>
2315 22:54:01.814265 [RX_INPUT] configuration <<<<<
2316 22:54:01.814338 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2317 22:54:01.814411 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2318 22:54:01.814484 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2319 22:54:01.814558 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2320 22:54:01.814631 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2321 22:54:01.814705 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2322 22:54:01.814778 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2323 22:54:01.814851 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2324 22:54:01.814924 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2325 22:54:01.815005 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2326 22:54:01.815070 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2327 22:54:01.815135 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2328 22:54:01.815200 ===================================
2329 22:54:01.815265 LPDDR4 DRAM CONFIGURATION
2330 22:54:01.815330 ===================================
2331 22:54:01.815395 EX_ROW_EN[0] = 0x0
2332 22:54:01.815460 EX_ROW_EN[1] = 0x0
2333 22:54:01.815524 LP4Y_EN = 0x0
2334 22:54:01.815588 WORK_FSP = 0x0
2335 22:54:01.815653 WL = 0x4
2336 22:54:01.815717 RL = 0x4
2337 22:54:01.815782 BL = 0x2
2338 22:54:01.815847 RPST = 0x0
2339 22:54:01.815911 RD_PRE = 0x0
2340 22:54:01.816000 WR_PRE = 0x1
2341 22:54:01.816102 WR_PST = 0x0
2342 22:54:01.816223 DBI_WR = 0x0
2343 22:54:01.816304 DBI_RD = 0x0
2344 22:54:01.816371 OTF = 0x1
2345 22:54:01.816437 ===================================
2346 22:54:01.816503 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2347 22:54:01.816570 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2348 22:54:01.816635 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2349 22:54:01.816701 ===================================
2350 22:54:01.816765 LPDDR4 DRAM CONFIGURATION
2351 22:54:01.816831 ===================================
2352 22:54:01.816896 EX_ROW_EN[0] = 0x10
2353 22:54:01.816961 EX_ROW_EN[1] = 0x0
2354 22:54:01.817026 LP4Y_EN = 0x0
2355 22:54:01.817091 WORK_FSP = 0x0
2356 22:54:01.817156 WL = 0x4
2357 22:54:01.817220 RL = 0x4
2358 22:54:01.817285 BL = 0x2
2359 22:54:01.817363 RPST = 0x0
2360 22:54:01.817430 RD_PRE = 0x0
2361 22:54:01.817495 WR_PRE = 0x1
2362 22:54:01.817560 WR_PST = 0x0
2363 22:54:01.817624 DBI_WR = 0x0
2364 22:54:01.817688 DBI_RD = 0x0
2365 22:54:01.817752 OTF = 0x1
2366 22:54:01.817817 ===================================
2367 22:54:01.817883 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2368 22:54:01.817948 ==
2369 22:54:01.818013 Dram Type= 6, Freq= 0, CH_0, rank 0
2370 22:54:01.818078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2371 22:54:01.818144 ==
2372 22:54:01.818208 [Duty_Offset_Calibration]
2373 22:54:01.818273 B0:1 B1:-1 CA:0
2374 22:54:01.818338
2375 22:54:01.818405 [DutyScan_Calibration_Flow] k_type=0
2376 22:54:01.818470
2377 22:54:01.818534 ==CLK 0==
2378 22:54:01.818599 Final CLK duty delay cell = 0
2379 22:54:01.818665 [0] MAX Duty = 5094%(X100), DQS PI = 16
2380 22:54:01.818730 [0] MIN Duty = 4875%(X100), DQS PI = 8
2381 22:54:01.818794 [0] AVG Duty = 4984%(X100)
2382 22:54:01.818859
2383 22:54:01.818924 CH0 CLK Duty spec in!! Max-Min= 219%
2384 22:54:01.818989 [DutyScan_Calibration_Flow] ====Done====
2385 22:54:01.819052
2386 22:54:01.819116 [DutyScan_Calibration_Flow] k_type=1
2387 22:54:01.819181
2388 22:54:01.819244 ==DQS 0 ==
2389 22:54:01.819309 Final DQS duty delay cell = -4
2390 22:54:01.819374 [-4] MAX Duty = 5062%(X100), DQS PI = 18
2391 22:54:01.819440 [-4] MIN Duty = 4875%(X100), DQS PI = 8
2392 22:54:01.819504 [-4] AVG Duty = 4968%(X100)
2393 22:54:01.819569
2394 22:54:01.819633 ==DQS 1 ==
2395 22:54:01.819697 Final DQS duty delay cell = 0
2396 22:54:01.819762 [0] MAX Duty = 5124%(X100), DQS PI = 6
2397 22:54:01.819827 [0] MIN Duty = 5000%(X100), DQS PI = 22
2398 22:54:01.819891 [0] AVG Duty = 5062%(X100)
2399 22:54:01.819956
2400 22:54:01.820242 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2401 22:54:01.820347
2402 22:54:01.820412 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2403 22:54:01.820473 [DutyScan_Calibration_Flow] ====Done====
2404 22:54:01.820535
2405 22:54:01.820594 [DutyScan_Calibration_Flow] k_type=3
2406 22:54:01.820653
2407 22:54:01.820711 ==DQM 0 ==
2408 22:54:01.820770 Final DQM duty delay cell = 0
2409 22:54:01.820829 [0] MAX Duty = 5062%(X100), DQS PI = 16
2410 22:54:01.820887 [0] MIN Duty = 4875%(X100), DQS PI = 8
2411 22:54:01.820946 [0] AVG Duty = 4968%(X100)
2412 22:54:01.821004
2413 22:54:01.821061 ==DQM 1 ==
2414 22:54:01.821120 Final DQM duty delay cell = 4
2415 22:54:01.821178 [4] MAX Duty = 5187%(X100), DQS PI = 14
2416 22:54:01.821237 [4] MIN Duty = 5000%(X100), DQS PI = 24
2417 22:54:01.821294 [4] AVG Duty = 5093%(X100)
2418 22:54:01.821362
2419 22:54:01.821422 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2420 22:54:01.821481
2421 22:54:01.821539 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2422 22:54:01.821596 [DutyScan_Calibration_Flow] ====Done====
2423 22:54:01.821655
2424 22:54:01.821712 [DutyScan_Calibration_Flow] k_type=2
2425 22:54:01.821770
2426 22:54:01.821827 ==DQ 0 ==
2427 22:54:01.821885 Final DQ duty delay cell = -4
2428 22:54:01.821944 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2429 22:54:01.822002 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2430 22:54:01.822060 [-4] AVG Duty = 4969%(X100)
2431 22:54:01.822118
2432 22:54:01.822176 ==DQ 1 ==
2433 22:54:01.822235 Final DQ duty delay cell = -4
2434 22:54:01.822294 [-4] MAX Duty = 4969%(X100), DQS PI = 52
2435 22:54:01.822352 [-4] MIN Duty = 4876%(X100), DQS PI = 16
2436 22:54:01.822410 [-4] AVG Duty = 4922%(X100)
2437 22:54:01.822468
2438 22:54:01.822526 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2439 22:54:01.822583
2440 22:54:01.822641 CH0 DQ 1 Duty spec in!! Max-Min= 93%
2441 22:54:01.822699 [DutyScan_Calibration_Flow] ====Done====
2442 22:54:01.822757 ==
2443 22:54:01.822815 Dram Type= 6, Freq= 0, CH_1, rank 0
2444 22:54:01.822873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2445 22:54:01.822932 ==
2446 22:54:01.822990 [Duty_Offset_Calibration]
2447 22:54:01.823049 B0:-1 B1:1 CA:1
2448 22:54:01.823107
2449 22:54:01.823165 [DutyScan_Calibration_Flow] k_type=0
2450 22:54:01.823223
2451 22:54:01.823280 ==CLK 0==
2452 22:54:01.823338 Final CLK duty delay cell = 0
2453 22:54:01.823397 [0] MAX Duty = 5156%(X100), DQS PI = 4
2454 22:54:01.823455 [0] MIN Duty = 5000%(X100), DQS PI = 28
2455 22:54:01.823513 [0] AVG Duty = 5078%(X100)
2456 22:54:01.823571
2457 22:54:01.823629 CH1 CLK Duty spec in!! Max-Min= 156%
2458 22:54:01.823687 [DutyScan_Calibration_Flow] ====Done====
2459 22:54:01.823745
2460 22:54:01.823802 [DutyScan_Calibration_Flow] k_type=1
2461 22:54:01.823860
2462 22:54:01.823918 ==DQS 0 ==
2463 22:54:01.823976 Final DQS duty delay cell = 0
2464 22:54:01.824034 [0] MAX Duty = 5125%(X100), DQS PI = 16
2465 22:54:01.824092 [0] MIN Duty = 4875%(X100), DQS PI = 38
2466 22:54:01.824150 [0] AVG Duty = 5000%(X100)
2467 22:54:01.824208
2468 22:54:01.824265 ==DQS 1 ==
2469 22:54:01.824323 Final DQS duty delay cell = 0
2470 22:54:01.824381 [0] MAX Duty = 5094%(X100), DQS PI = 42
2471 22:54:01.824439 [0] MIN Duty = 4969%(X100), DQS PI = 26
2472 22:54:01.824496 [0] AVG Duty = 5031%(X100)
2473 22:54:01.824554
2474 22:54:01.824611 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2475 22:54:01.824668
2476 22:54:01.824726 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2477 22:54:01.824783 [DutyScan_Calibration_Flow] ====Done====
2478 22:54:01.824841
2479 22:54:01.824898 [DutyScan_Calibration_Flow] k_type=3
2480 22:54:01.824955
2481 22:54:01.825021 ==DQM 0 ==
2482 22:54:01.825074 Final DQM duty delay cell = 0
2483 22:54:01.825127 [0] MAX Duty = 5187%(X100), DQS PI = 2
2484 22:54:01.825180 [0] MIN Duty = 5000%(X100), DQS PI = 38
2485 22:54:01.825233 [0] AVG Duty = 5093%(X100)
2486 22:54:01.825285
2487 22:54:01.825344 ==DQM 1 ==
2488 22:54:01.825398 Final DQM duty delay cell = 0
2489 22:54:01.825451 [0] MAX Duty = 5187%(X100), DQS PI = 38
2490 22:54:01.825505 [0] MIN Duty = 4969%(X100), DQS PI = 0
2491 22:54:01.825558 [0] AVG Duty = 5078%(X100)
2492 22:54:01.825610
2493 22:54:01.825662 CH1 DQM 0 Duty spec in!! Max-Min= 187%
2494 22:54:01.825714
2495 22:54:01.825767 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2496 22:54:01.825819 [DutyScan_Calibration_Flow] ====Done====
2497 22:54:01.825872
2498 22:54:01.825924 [DutyScan_Calibration_Flow] k_type=2
2499 22:54:01.825977
2500 22:54:01.826029 ==DQ 0 ==
2501 22:54:01.826081 Final DQ duty delay cell = 0
2502 22:54:01.826134 [0] MAX Duty = 5156%(X100), DQS PI = 60
2503 22:54:01.826187 [0] MIN Duty = 4907%(X100), DQS PI = 38
2504 22:54:01.826239 [0] AVG Duty = 5031%(X100)
2505 22:54:01.826292
2506 22:54:01.826344 ==DQ 1 ==
2507 22:54:01.826397 Final DQ duty delay cell = 0
2508 22:54:01.826449 [0] MAX Duty = 5124%(X100), DQS PI = 42
2509 22:54:01.826502 [0] MIN Duty = 4969%(X100), DQS PI = 0
2510 22:54:01.826555 [0] AVG Duty = 5046%(X100)
2511 22:54:01.826607
2512 22:54:01.826659 CH1 DQ 0 Duty spec in!! Max-Min= 249%
2513 22:54:01.826712
2514 22:54:01.826764 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2515 22:54:01.826816 [DutyScan_Calibration_Flow] ====Done====
2516 22:54:01.826868 nWR fixed to 30
2517 22:54:01.826922 [ModeRegInit_LP4] CH0 RK0
2518 22:54:01.826975 [ModeRegInit_LP4] CH0 RK1
2519 22:54:01.827027 [ModeRegInit_LP4] CH1 RK0
2520 22:54:01.827080 [ModeRegInit_LP4] CH1 RK1
2521 22:54:01.827132 match AC timing 7
2522 22:54:01.827185 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2523 22:54:01.827238 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2524 22:54:01.827290 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2525 22:54:01.827343 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2526 22:54:01.827397 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2527 22:54:01.827449 ==
2528 22:54:01.827502 Dram Type= 6, Freq= 0, CH_0, rank 0
2529 22:54:01.827555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2530 22:54:01.827608 ==
2531 22:54:01.827661 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2532 22:54:01.827714 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2533 22:54:01.827767 [CA 0] Center 39 (9~70) winsize 62
2534 22:54:01.827820 [CA 1] Center 39 (9~70) winsize 62
2535 22:54:01.827873 [CA 2] Center 35 (5~66) winsize 62
2536 22:54:01.827925 [CA 3] Center 35 (5~65) winsize 61
2537 22:54:01.827978 [CA 4] Center 33 (3~64) winsize 62
2538 22:54:01.828031 [CA 5] Center 33 (4~63) winsize 60
2539 22:54:01.828083
2540 22:54:01.828135 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2541 22:54:01.828188
2542 22:54:01.828240 [CATrainingPosCal] consider 1 rank data
2543 22:54:01.828293 u2DelayCellTimex100 = 270/100 ps
2544 22:54:01.828346 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2545 22:54:01.828398 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2546 22:54:01.828451 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2547 22:54:01.828504 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2548 22:54:01.828557 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2549 22:54:01.828804 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2550 22:54:01.828865
2551 22:54:01.828919 CA PerBit enable=1, Macro0, CA PI delay=33
2552 22:54:01.828972
2553 22:54:01.829025 [CBTSetCACLKResult] CA Dly = 33
2554 22:54:01.829078 CS Dly: 8 (0~39)
2555 22:54:01.829131 ==
2556 22:54:01.829183 Dram Type= 6, Freq= 0, CH_0, rank 1
2557 22:54:01.829236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2558 22:54:01.829289 ==
2559 22:54:01.829350 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2560 22:54:01.829405 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2561 22:54:01.829478 [CA 0] Center 39 (9~70) winsize 62
2562 22:54:01.829575 [CA 1] Center 39 (9~70) winsize 62
2563 22:54:01.829670 [CA 2] Center 35 (5~66) winsize 62
2564 22:54:01.829737 [CA 3] Center 34 (4~65) winsize 62
2565 22:54:01.829792 [CA 4] Center 33 (3~64) winsize 62
2566 22:54:01.829846 [CA 5] Center 33 (3~63) winsize 61
2567 22:54:01.829898
2568 22:54:01.829964 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2569 22:54:01.830016
2570 22:54:01.830069 [CATrainingPosCal] consider 2 rank data
2571 22:54:01.830121 u2DelayCellTimex100 = 270/100 ps
2572 22:54:01.830173 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2573 22:54:01.830225 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2574 22:54:01.830277 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2575 22:54:01.830329 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2576 22:54:01.830380 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2577 22:54:01.830432 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2578 22:54:01.830483
2579 22:54:01.830534 CA PerBit enable=1, Macro0, CA PI delay=33
2580 22:54:01.830586
2581 22:54:01.830637 [CBTSetCACLKResult] CA Dly = 33
2582 22:54:01.830688 CS Dly: 9 (0~41)
2583 22:54:01.830740
2584 22:54:01.830792 ----->DramcWriteLeveling(PI) begin...
2585 22:54:01.830844 ==
2586 22:54:01.830896 Dram Type= 6, Freq= 0, CH_0, rank 0
2587 22:54:01.830948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2588 22:54:01.831000 ==
2589 22:54:01.831052 Write leveling (Byte 0): 32 => 32
2590 22:54:01.831103 Write leveling (Byte 1): 29 => 29
2591 22:54:01.831155 DramcWriteLeveling(PI) end<-----
2592 22:54:01.831206
2593 22:54:01.831257 ==
2594 22:54:01.831309 Dram Type= 6, Freq= 0, CH_0, rank 0
2595 22:54:01.831361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2596 22:54:01.831413 ==
2597 22:54:01.831464 [Gating] SW mode calibration
2598 22:54:01.831516 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2599 22:54:01.831568 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2600 22:54:01.831620 0 15 0 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
2601 22:54:01.831672 0 15 4 | B1->B0 | 2323 3434 | 1 1 | (0 0) (1 1)
2602 22:54:01.831724 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2603 22:54:01.831776 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2604 22:54:01.831827 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2605 22:54:01.831879 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2606 22:54:01.831930 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2607 22:54:01.831980 0 15 28 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (1 0)
2608 22:54:01.832032 1 0 0 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
2609 22:54:01.832085 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2610 22:54:01.832136 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2611 22:54:01.832188 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2612 22:54:01.832240 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2613 22:54:01.832291 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2614 22:54:01.832343 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2615 22:54:01.832394 1 0 28 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
2616 22:54:01.832446 1 1 0 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
2617 22:54:01.832498 1 1 4 | B1->B0 | 3e3d 4646 | 1 0 | (0 0) (0 0)
2618 22:54:01.832550 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2619 22:54:01.832601 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2620 22:54:01.832652 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2621 22:54:01.832703 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2622 22:54:01.832774 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2623 22:54:01.832839 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
2624 22:54:01.832890 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2625 22:54:01.832942 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2626 22:54:01.832994 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 22:54:01.833045 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 22:54:01.833097 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 22:54:01.833148 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 22:54:01.833200 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 22:54:01.833251 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 22:54:01.833302 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2633 22:54:01.833422 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2634 22:54:01.833504 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2635 22:54:01.833598 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2636 22:54:01.833657 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2637 22:54:01.833710 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2638 22:54:01.833763 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2639 22:54:01.833815 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2640 22:54:01.833866 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2641 22:54:01.833918 Total UI for P1: 0, mck2ui 16
2642 22:54:01.833971 best dqsien dly found for B0: ( 1, 3, 28)
2643 22:54:01.834024 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2644 22:54:01.834077 Total UI for P1: 0, mck2ui 16
2645 22:54:01.834129 best dqsien dly found for B1: ( 1, 4, 0)
2646 22:54:01.834181 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2647 22:54:01.834233 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2648 22:54:01.834285
2649 22:54:01.834337 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2650 22:54:01.834389 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2651 22:54:01.834441 [Gating] SW calibration Done
2652 22:54:01.834493 ==
2653 22:54:01.834544 Dram Type= 6, Freq= 0, CH_0, rank 0
2654 22:54:01.834794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2655 22:54:01.834852 ==
2656 22:54:01.834905 RX Vref Scan: 0
2657 22:54:01.834957
2658 22:54:01.835008 RX Vref 0 -> 0, step: 1
2659 22:54:01.835060
2660 22:54:01.835111 RX Delay -40 -> 252, step: 8
2661 22:54:01.835163 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2662 22:54:01.835215 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2663 22:54:01.835267 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2664 22:54:01.835318 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2665 22:54:01.835369 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2666 22:54:01.835421 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2667 22:54:01.835472 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2668 22:54:01.835523 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2669 22:54:01.835574 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2670 22:54:01.835626 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2671 22:54:01.835677 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2672 22:54:01.835729 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2673 22:54:01.835781 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2674 22:54:01.835832 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2675 22:54:01.835884 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2676 22:54:01.835935 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2677 22:54:01.835986 ==
2678 22:54:01.836037 Dram Type= 6, Freq= 0, CH_0, rank 0
2679 22:54:01.836089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2680 22:54:01.836141 ==
2681 22:54:01.836193 DQS Delay:
2682 22:54:01.836245 DQS0 = 0, DQS1 = 0
2683 22:54:01.836297 DQM Delay:
2684 22:54:01.836347 DQM0 = 119, DQM1 = 106
2685 22:54:01.836399 DQ Delay:
2686 22:54:01.836451 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2687 22:54:01.836503 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2688 22:54:01.836555 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2689 22:54:01.836606 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2690 22:54:01.836658
2691 22:54:01.836709
2692 22:54:01.836761 ==
2693 22:54:01.836812 Dram Type= 6, Freq= 0, CH_0, rank 0
2694 22:54:01.836864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2695 22:54:01.836916 ==
2696 22:54:01.836968
2697 22:54:01.837018
2698 22:54:01.837069 TX Vref Scan disable
2699 22:54:01.837121 == TX Byte 0 ==
2700 22:54:01.837172 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2701 22:54:01.837224 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2702 22:54:01.837275 == TX Byte 1 ==
2703 22:54:01.837326 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2704 22:54:01.837419 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2705 22:54:01.837471 ==
2706 22:54:01.837522 Dram Type= 6, Freq= 0, CH_0, rank 0
2707 22:54:01.837574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2708 22:54:01.837626 ==
2709 22:54:01.837678 TX Vref=22, minBit 1, minWin=25, winSum=419
2710 22:54:01.837730 TX Vref=24, minBit 13, minWin=25, winSum=423
2711 22:54:01.837782 TX Vref=26, minBit 1, minWin=26, winSum=431
2712 22:54:01.837834 TX Vref=28, minBit 4, minWin=26, winSum=434
2713 22:54:01.837886 TX Vref=30, minBit 5, minWin=26, winSum=433
2714 22:54:01.837938 TX Vref=32, minBit 5, minWin=26, winSum=434
2715 22:54:01.837990 [TxChooseVref] Worse bit 4, Min win 26, Win sum 434, Final Vref 28
2716 22:54:01.838043
2717 22:54:01.838094 Final TX Range 1 Vref 28
2718 22:54:01.838146
2719 22:54:01.838197 ==
2720 22:54:01.838248 Dram Type= 6, Freq= 0, CH_0, rank 0
2721 22:54:01.838299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2722 22:54:01.838351 ==
2723 22:54:01.838403
2724 22:54:01.838454
2725 22:54:01.838506 TX Vref Scan disable
2726 22:54:01.838557 == TX Byte 0 ==
2727 22:54:01.838608 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2728 22:54:01.838660 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2729 22:54:01.838712 == TX Byte 1 ==
2730 22:54:01.838763 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2731 22:54:01.838814 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2732 22:54:01.838864
2733 22:54:01.838915 [DATLAT]
2734 22:54:01.838966 Freq=1200, CH0 RK0
2735 22:54:01.839018
2736 22:54:01.839069 DATLAT Default: 0xd
2737 22:54:01.839121 0, 0xFFFF, sum = 0
2738 22:54:01.839174 1, 0xFFFF, sum = 0
2739 22:54:01.839227 2, 0xFFFF, sum = 0
2740 22:54:01.839279 3, 0xFFFF, sum = 0
2741 22:54:01.839331 4, 0xFFFF, sum = 0
2742 22:54:01.839383 5, 0xFFFF, sum = 0
2743 22:54:01.839436 6, 0xFFFF, sum = 0
2744 22:54:01.839488 7, 0xFFFF, sum = 0
2745 22:54:01.839540 8, 0xFFFF, sum = 0
2746 22:54:01.839593 9, 0xFFFF, sum = 0
2747 22:54:01.839645 10, 0xFFFF, sum = 0
2748 22:54:01.839698 11, 0xFFFF, sum = 0
2749 22:54:01.839750 12, 0x0, sum = 1
2750 22:54:01.839802 13, 0x0, sum = 2
2751 22:54:01.839854 14, 0x0, sum = 3
2752 22:54:01.839906 15, 0x0, sum = 4
2753 22:54:01.839959 best_step = 13
2754 22:54:01.840010
2755 22:54:01.840061 ==
2756 22:54:01.840112 Dram Type= 6, Freq= 0, CH_0, rank 0
2757 22:54:01.840164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2758 22:54:01.840216 ==
2759 22:54:01.840267 RX Vref Scan: 1
2760 22:54:01.840319
2761 22:54:01.840371 Set Vref Range= 32 -> 127
2762 22:54:01.840422
2763 22:54:01.840474 RX Vref 32 -> 127, step: 1
2764 22:54:01.840525
2765 22:54:01.840576 RX Delay -21 -> 252, step: 4
2766 22:54:01.840627
2767 22:54:01.840679 Set Vref, RX VrefLevel [Byte0]: 32
2768 22:54:01.840731 [Byte1]: 32
2769 22:54:01.840783
2770 22:54:01.840834 Set Vref, RX VrefLevel [Byte0]: 33
2771 22:54:01.840886 [Byte1]: 33
2772 22:54:01.840938
2773 22:54:01.840989 Set Vref, RX VrefLevel [Byte0]: 34
2774 22:54:01.841040 [Byte1]: 34
2775 22:54:01.841091
2776 22:54:01.841142 Set Vref, RX VrefLevel [Byte0]: 35
2777 22:54:01.841194 [Byte1]: 35
2778 22:54:01.841245
2779 22:54:01.841296 Set Vref, RX VrefLevel [Byte0]: 36
2780 22:54:01.841387 [Byte1]: 36
2781 22:54:01.841482
2782 22:54:01.841563 Set Vref, RX VrefLevel [Byte0]: 37
2783 22:54:01.841644 [Byte1]: 37
2784 22:54:01.841715
2785 22:54:01.841768 Set Vref, RX VrefLevel [Byte0]: 38
2786 22:54:01.841820 [Byte1]: 38
2787 22:54:01.841873
2788 22:54:01.841924 Set Vref, RX VrefLevel [Byte0]: 39
2789 22:54:01.841976 [Byte1]: 39
2790 22:54:01.842028
2791 22:54:01.842079 Set Vref, RX VrefLevel [Byte0]: 40
2792 22:54:01.842131 [Byte1]: 40
2793 22:54:01.842183
2794 22:54:01.842234 Set Vref, RX VrefLevel [Byte0]: 41
2795 22:54:01.842286 [Byte1]: 41
2796 22:54:01.842337
2797 22:54:01.842388 Set Vref, RX VrefLevel [Byte0]: 42
2798 22:54:01.842440 [Byte1]: 42
2799 22:54:01.842491
2800 22:54:01.842542 Set Vref, RX VrefLevel [Byte0]: 43
2801 22:54:01.842594 [Byte1]: 43
2802 22:54:01.842646
2803 22:54:01.842697 Set Vref, RX VrefLevel [Byte0]: 44
2804 22:54:01.842748 [Byte1]: 44
2805 22:54:01.842800
2806 22:54:01.842851 Set Vref, RX VrefLevel [Byte0]: 45
2807 22:54:01.842903 [Byte1]: 45
2808 22:54:01.842954
2809 22:54:01.843005 Set Vref, RX VrefLevel [Byte0]: 46
2810 22:54:01.843057 [Byte1]: 46
2811 22:54:01.843109
2812 22:54:01.843349 Set Vref, RX VrefLevel [Byte0]: 47
2813 22:54:01.843407 [Byte1]: 47
2814 22:54:01.843460
2815 22:54:01.843512 Set Vref, RX VrefLevel [Byte0]: 48
2816 22:54:01.843564 [Byte1]: 48
2817 22:54:01.843616
2818 22:54:01.843667 Set Vref, RX VrefLevel [Byte0]: 49
2819 22:54:01.843719 [Byte1]: 49
2820 22:54:01.843770
2821 22:54:01.843822 Set Vref, RX VrefLevel [Byte0]: 50
2822 22:54:01.843873 [Byte1]: 50
2823 22:54:01.843924
2824 22:54:01.843975 Set Vref, RX VrefLevel [Byte0]: 51
2825 22:54:01.844027 [Byte1]: 51
2826 22:54:01.844078
2827 22:54:01.844130 Set Vref, RX VrefLevel [Byte0]: 52
2828 22:54:01.844181 [Byte1]: 52
2829 22:54:01.844232
2830 22:54:01.844283 Set Vref, RX VrefLevel [Byte0]: 53
2831 22:54:01.844335 [Byte1]: 53
2832 22:54:01.844386
2833 22:54:01.844438 Set Vref, RX VrefLevel [Byte0]: 54
2834 22:54:01.844490 [Byte1]: 54
2835 22:54:01.844542
2836 22:54:01.844593 Set Vref, RX VrefLevel [Byte0]: 55
2837 22:54:01.844657 [Byte1]: 55
2838 22:54:01.844710
2839 22:54:01.844761 Set Vref, RX VrefLevel [Byte0]: 56
2840 22:54:01.844813 [Byte1]: 56
2841 22:54:01.844866
2842 22:54:01.844917 Set Vref, RX VrefLevel [Byte0]: 57
2843 22:54:01.844968 [Byte1]: 57
2844 22:54:01.845020
2845 22:54:01.845071 Set Vref, RX VrefLevel [Byte0]: 58
2846 22:54:01.845123 [Byte1]: 58
2847 22:54:01.845174
2848 22:54:01.845226 Set Vref, RX VrefLevel [Byte0]: 59
2849 22:54:01.845277 [Byte1]: 59
2850 22:54:01.845335
2851 22:54:01.845422 Set Vref, RX VrefLevel [Byte0]: 60
2852 22:54:01.845475 [Byte1]: 60
2853 22:54:01.845527
2854 22:54:01.845578 Set Vref, RX VrefLevel [Byte0]: 61
2855 22:54:01.845630 [Byte1]: 61
2856 22:54:01.845682
2857 22:54:01.845733 Set Vref, RX VrefLevel [Byte0]: 62
2858 22:54:01.845785 [Byte1]: 62
2859 22:54:01.845836
2860 22:54:01.845887 Set Vref, RX VrefLevel [Byte0]: 63
2861 22:54:01.845938 [Byte1]: 63
2862 22:54:01.845989
2863 22:54:01.846040 Set Vref, RX VrefLevel [Byte0]: 64
2864 22:54:01.846091 [Byte1]: 64
2865 22:54:01.846143
2866 22:54:01.846194 Set Vref, RX VrefLevel [Byte0]: 65
2867 22:54:01.846277 [Byte1]: 65
2868 22:54:01.846345
2869 22:54:01.846438 Set Vref, RX VrefLevel [Byte0]: 66
2870 22:54:01.846512 [Byte1]: 66
2871 22:54:01.846567
2872 22:54:01.846620 Set Vref, RX VrefLevel [Byte0]: 67
2873 22:54:01.846673 [Byte1]: 67
2874 22:54:01.846725
2875 22:54:01.846777 Set Vref, RX VrefLevel [Byte0]: 68
2876 22:54:01.846828 [Byte1]: 68
2877 22:54:01.846879
2878 22:54:01.846931 Set Vref, RX VrefLevel [Byte0]: 69
2879 22:54:01.846983 [Byte1]: 69
2880 22:54:01.847034
2881 22:54:01.847086 Set Vref, RX VrefLevel [Byte0]: 70
2882 22:54:01.847137 [Byte1]: 70
2883 22:54:01.847189
2884 22:54:01.847240 Set Vref, RX VrefLevel [Byte0]: 71
2885 22:54:01.847292 [Byte1]: 71
2886 22:54:01.847344
2887 22:54:01.847395 Set Vref, RX VrefLevel [Byte0]: 72
2888 22:54:01.847446 [Byte1]: 72
2889 22:54:01.847498
2890 22:54:01.847549 Set Vref, RX VrefLevel [Byte0]: 73
2891 22:54:01.847600 [Byte1]: 73
2892 22:54:01.847652
2893 22:54:01.847703 Set Vref, RX VrefLevel [Byte0]: 74
2894 22:54:01.847755 [Byte1]: 74
2895 22:54:01.847807
2896 22:54:01.847858 Set Vref, RX VrefLevel [Byte0]: 75
2897 22:54:01.847909 [Byte1]: 75
2898 22:54:01.847961
2899 22:54:01.848012 Set Vref, RX VrefLevel [Byte0]: 76
2900 22:54:01.848064 [Byte1]: 76
2901 22:54:01.848115
2902 22:54:01.848167 Set Vref, RX VrefLevel [Byte0]: 77
2903 22:54:01.848218 [Byte1]: 77
2904 22:54:01.848269
2905 22:54:01.848320 Final RX Vref Byte 0 = 56 to rank0
2906 22:54:01.848373 Final RX Vref Byte 1 = 50 to rank0
2907 22:54:01.848425 Final RX Vref Byte 0 = 56 to rank1
2908 22:54:01.848477 Final RX Vref Byte 1 = 50 to rank1==
2909 22:54:01.848529 Dram Type= 6, Freq= 0, CH_0, rank 0
2910 22:54:01.848581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2911 22:54:01.848633 ==
2912 22:54:01.848685 DQS Delay:
2913 22:54:01.848736 DQS0 = 0, DQS1 = 0
2914 22:54:01.848788 DQM Delay:
2915 22:54:01.848840 DQM0 = 118, DQM1 = 107
2916 22:54:01.848891 DQ Delay:
2917 22:54:01.848943 DQ0 =116, DQ1 =120, DQ2 =116, DQ3 =114
2918 22:54:01.848995 DQ4 =120, DQ5 =110, DQ6 =126, DQ7 =126
2919 22:54:01.849046 DQ8 =98, DQ9 =94, DQ10 =108, DQ11 =100
2920 22:54:01.849097 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =116
2921 22:54:01.849148
2922 22:54:01.849199
2923 22:54:01.849251 [DQSOSCAuto] RK0, (LSB)MR18= 0x12fe, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 403 ps
2924 22:54:01.849304 CH0 RK0: MR19=403, MR18=12FE
2925 22:54:01.849394 CH0_RK0: MR19=0x403, MR18=0x12FE, DQSOSC=403, MR23=63, INC=40, DEC=26
2926 22:54:01.849461
2927 22:54:01.849512 ----->DramcWriteLeveling(PI) begin...
2928 22:54:01.849566 ==
2929 22:54:01.849618 Dram Type= 6, Freq= 0, CH_0, rank 1
2930 22:54:01.849670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2931 22:54:01.849722 ==
2932 22:54:01.849773 Write leveling (Byte 0): 32 => 32
2933 22:54:01.849824 Write leveling (Byte 1): 30 => 30
2934 22:54:01.849876 DramcWriteLeveling(PI) end<-----
2935 22:54:01.849928
2936 22:54:01.849980 ==
2937 22:54:01.850031 Dram Type= 6, Freq= 0, CH_0, rank 1
2938 22:54:01.850083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2939 22:54:01.850135 ==
2940 22:54:01.850186 [Gating] SW mode calibration
2941 22:54:01.850238 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2942 22:54:01.850290 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2943 22:54:01.850342 0 15 0 | B1->B0 | 2423 3333 | 1 1 | (0 0) (1 1)
2944 22:54:01.850393 0 15 4 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
2945 22:54:01.850445 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2946 22:54:01.850496 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2947 22:54:01.850547 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2948 22:54:01.850598 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2949 22:54:01.850650 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2950 22:54:01.850701 0 15 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2951 22:54:01.850752 1 0 0 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (1 0)
2952 22:54:01.850803 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2953 22:54:01.850855 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2954 22:54:01.851097 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2955 22:54:01.851157 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2956 22:54:01.851210 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2957 22:54:01.851262 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2958 22:54:01.851313 1 0 28 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
2959 22:54:01.851365 1 1 0 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
2960 22:54:01.851417 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2961 22:54:01.851469 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2962 22:54:01.851521 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2963 22:54:01.851573 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2964 22:54:01.851625 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2965 22:54:01.851677 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2966 22:54:01.851728 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2967 22:54:01.851780 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2968 22:54:01.851832 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2969 22:54:01.851884 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2970 22:54:01.851937 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2971 22:54:01.851989 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2972 22:54:01.852041 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2973 22:54:01.852093 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2974 22:54:01.852144 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2975 22:54:01.852196 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2976 22:54:01.852247 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2977 22:54:01.852299 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2978 22:54:01.852351 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2979 22:54:01.852403 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2980 22:54:01.852454 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2981 22:54:01.852506 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2982 22:54:01.852557 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2983 22:54:01.852609 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2984 22:54:01.852661 Total UI for P1: 0, mck2ui 16
2985 22:54:01.852713 best dqsien dly found for B0: ( 1, 3, 26)
2986 22:54:01.852765 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2987 22:54:01.852817 Total UI for P1: 0, mck2ui 16
2988 22:54:01.852869 best dqsien dly found for B1: ( 1, 4, 0)
2989 22:54:01.852921 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2990 22:54:01.852972 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2991 22:54:01.853024
2992 22:54:01.853075 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2993 22:54:01.853127 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2994 22:54:01.853179 [Gating] SW calibration Done
2995 22:54:01.853231 ==
2996 22:54:01.853282 Dram Type= 6, Freq= 0, CH_0, rank 1
2997 22:54:01.853340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2998 22:54:01.853393 ==
2999 22:54:01.853444 RX Vref Scan: 0
3000 22:54:01.853496
3001 22:54:01.853548 RX Vref 0 -> 0, step: 1
3002 22:54:01.853600
3003 22:54:01.853652 RX Delay -40 -> 252, step: 8
3004 22:54:01.853703 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
3005 22:54:01.853754 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
3006 22:54:01.853806 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
3007 22:54:02.079991 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3008 22:54:02.080649 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3009 22:54:02.081018 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
3010 22:54:02.081388 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3011 22:54:02.081725 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
3012 22:54:02.082044 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3013 22:54:02.082354 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3014 22:54:02.082793 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3015 22:54:02.083114 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3016 22:54:02.083419 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3017 22:54:02.083724 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3018 22:54:02.084025 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3019 22:54:02.084325 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3020 22:54:02.084658 ==
3021 22:54:02.084962 Dram Type= 6, Freq= 0, CH_0, rank 1
3022 22:54:02.085265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3023 22:54:02.085618 ==
3024 22:54:02.085921 DQS Delay:
3025 22:54:02.086217 DQS0 = 0, DQS1 = 0
3026 22:54:02.086554 DQM Delay:
3027 22:54:02.086856 DQM0 = 117, DQM1 = 108
3028 22:54:02.087154 DQ Delay:
3029 22:54:02.087449 DQ0 =115, DQ1 =119, DQ2 =111, DQ3 =115
3030 22:54:02.087744 DQ4 =119, DQ5 =111, DQ6 =127, DQ7 =123
3031 22:54:02.088038 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
3032 22:54:02.088333 DQ12 =111, DQ13 =119, DQ14 =119, DQ15 =111
3033 22:54:02.088629
3034 22:54:02.088921
3035 22:54:02.089212 ==
3036 22:54:02.089552 Dram Type= 6, Freq= 0, CH_0, rank 1
3037 22:54:02.089852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3038 22:54:02.090145 ==
3039 22:54:02.090480
3040 22:54:02.090966
3041 22:54:02.091284 TX Vref Scan disable
3042 22:54:02.091587 == TX Byte 0 ==
3043 22:54:02.091885 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3044 22:54:02.092186 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3045 22:54:02.092482 == TX Byte 1 ==
3046 22:54:02.092812 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3047 22:54:02.093122 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3048 22:54:02.093460 ==
3049 22:54:02.093768 Dram Type= 6, Freq= 0, CH_0, rank 1
3050 22:54:02.094066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3051 22:54:02.094364 ==
3052 22:54:02.094659 TX Vref=22, minBit 5, minWin=25, winSum=424
3053 22:54:02.094962 TX Vref=24, minBit 1, minWin=26, winSum=426
3054 22:54:02.095260 TX Vref=26, minBit 0, minWin=26, winSum=431
3055 22:54:02.095556 TX Vref=28, minBit 1, minWin=26, winSum=429
3056 22:54:02.095853 TX Vref=30, minBit 3, minWin=27, winSum=438
3057 22:54:02.096148 TX Vref=32, minBit 10, minWin=26, winSum=436
3058 22:54:02.096464 [TxChooseVref] Worse bit 3, Min win 27, Win sum 438, Final Vref 30
3059 22:54:02.096805
3060 22:54:02.097209 Final TX Range 1 Vref 30
3061 22:54:02.097564
3062 22:54:02.098014 ==
3063 22:54:02.098350 Dram Type= 6, Freq= 0, CH_0, rank 1
3064 22:54:02.098655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3065 22:54:02.098953 ==
3066 22:54:02.099249
3067 22:54:02.099541
3068 22:54:02.100266 TX Vref Scan disable
3069 22:54:02.100600 == TX Byte 0 ==
3070 22:54:02.100902 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3071 22:54:02.101410 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3072 22:54:02.101730 == TX Byte 1 ==
3073 22:54:02.102026 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3074 22:54:02.102324 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3075 22:54:02.102623
3076 22:54:02.102917 [DATLAT]
3077 22:54:02.103205 Freq=1200, CH0 RK1
3078 22:54:02.103474
3079 22:54:02.103741 DATLAT Default: 0xd
3080 22:54:02.104008 0, 0xFFFF, sum = 0
3081 22:54:02.104444 1, 0xFFFF, sum = 0
3082 22:54:02.104745 2, 0xFFFF, sum = 0
3083 22:54:02.105017 3, 0xFFFF, sum = 0
3084 22:54:02.105213 4, 0xFFFF, sum = 0
3085 22:54:02.105424 5, 0xFFFF, sum = 0
3086 22:54:02.105623 6, 0xFFFF, sum = 0
3087 22:54:02.105814 7, 0xFFFF, sum = 0
3088 22:54:02.106007 8, 0xFFFF, sum = 0
3089 22:54:02.106200 9, 0xFFFF, sum = 0
3090 22:54:02.106393 10, 0xFFFF, sum = 0
3091 22:54:02.106586 11, 0xFFFF, sum = 0
3092 22:54:02.106782 12, 0x0, sum = 1
3093 22:54:02.106975 13, 0x0, sum = 2
3094 22:54:02.107169 14, 0x0, sum = 3
3095 22:54:02.107362 15, 0x0, sum = 4
3096 22:54:02.107554 best_step = 13
3097 22:54:02.107743
3098 22:54:02.107931 ==
3099 22:54:02.108124 Dram Type= 6, Freq= 0, CH_0, rank 1
3100 22:54:02.108316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3101 22:54:02.108508 ==
3102 22:54:02.108697 RX Vref Scan: 0
3103 22:54:02.108887
3104 22:54:02.109078 RX Vref 0 -> 0, step: 1
3105 22:54:02.109269
3106 22:54:02.109473 RX Delay -21 -> 252, step: 4
3107 22:54:02.109666 iDelay=195, Bit 0, Center 112 (47 ~ 178) 132
3108 22:54:02.109858 iDelay=195, Bit 1, Center 118 (47 ~ 190) 144
3109 22:54:02.110034 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3110 22:54:02.110177 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3111 22:54:02.110322 iDelay=195, Bit 4, Center 116 (47 ~ 186) 140
3112 22:54:02.110467 iDelay=195, Bit 5, Center 110 (43 ~ 178) 136
3113 22:54:02.110613 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
3114 22:54:02.110757 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3115 22:54:02.110900 iDelay=195, Bit 8, Center 96 (27 ~ 166) 140
3116 22:54:02.111045 iDelay=195, Bit 9, Center 94 (27 ~ 162) 136
3117 22:54:02.111189 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3118 22:54:02.111333 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3119 22:54:02.111477 iDelay=195, Bit 12, Center 114 (47 ~ 182) 136
3120 22:54:02.111620 iDelay=195, Bit 13, Center 114 (47 ~ 182) 136
3121 22:54:02.111764 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3122 22:54:02.111909 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3123 22:54:02.112052 ==
3124 22:54:02.112195 Dram Type= 6, Freq= 0, CH_0, rank 1
3125 22:54:02.112340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3126 22:54:02.112486 ==
3127 22:54:02.112632 DQS Delay:
3128 22:54:02.112775 DQS0 = 0, DQS1 = 0
3129 22:54:02.112922 DQM Delay:
3130 22:54:02.113066 DQM0 = 116, DQM1 = 107
3131 22:54:02.113211 DQ Delay:
3132 22:54:02.113365 DQ0 =112, DQ1 =118, DQ2 =110, DQ3 =114
3133 22:54:02.113512 DQ4 =116, DQ5 =110, DQ6 =124, DQ7 =124
3134 22:54:02.113657 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =100
3135 22:54:02.113802 DQ12 =114, DQ13 =114, DQ14 =118, DQ15 =116
3136 22:54:02.113946
3137 22:54:02.114089
3138 22:54:02.114234 [DQSOSCAuto] RK1, (LSB)MR18= 0xfea, (MSB)MR19= 0x403, tDQSOscB0 = 419 ps tDQSOscB1 = 404 ps
3139 22:54:02.114382 CH0 RK1: MR19=403, MR18=FEA
3140 22:54:02.114529 CH0_RK1: MR19=0x403, MR18=0xFEA, DQSOSC=404, MR23=63, INC=40, DEC=26
3141 22:54:02.114675 [RxdqsGatingPostProcess] freq 1200
3142 22:54:02.114821 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3143 22:54:02.114972 best DQS0 dly(2T, 0.5T) = (0, 11)
3144 22:54:02.115088 best DQS1 dly(2T, 0.5T) = (0, 12)
3145 22:54:02.115204 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3146 22:54:02.115320 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3147 22:54:02.115437 best DQS0 dly(2T, 0.5T) = (0, 11)
3148 22:54:02.115552 best DQS1 dly(2T, 0.5T) = (0, 12)
3149 22:54:02.115667 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3150 22:54:02.115784 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3151 22:54:02.115901 Pre-setting of DQS Precalculation
3152 22:54:02.116017 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3153 22:54:02.116134 ==
3154 22:54:02.116249 Dram Type= 6, Freq= 0, CH_1, rank 0
3155 22:54:02.116366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3156 22:54:02.116483 ==
3157 22:54:02.116599 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3158 22:54:02.116715 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3159 22:54:02.116831 [CA 0] Center 37 (7~68) winsize 62
3160 22:54:02.116948 [CA 1] Center 38 (8~68) winsize 61
3161 22:54:02.117064 [CA 2] Center 34 (4~64) winsize 61
3162 22:54:02.117178 [CA 3] Center 33 (3~64) winsize 62
3163 22:54:02.117293 [CA 4] Center 34 (4~64) winsize 61
3164 22:54:02.117419 [CA 5] Center 33 (3~64) winsize 62
3165 22:54:02.117534
3166 22:54:02.117650 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3167 22:54:02.117766
3168 22:54:02.117917 [CATrainingPosCal] consider 1 rank data
3169 22:54:02.118074 u2DelayCellTimex100 = 270/100 ps
3170 22:54:02.118194 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3171 22:54:02.118313 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3172 22:54:02.118429 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3173 22:54:02.118546 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3174 22:54:02.118663 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3175 22:54:02.118779 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3176 22:54:02.118895
3177 22:54:02.119011 CA PerBit enable=1, Macro0, CA PI delay=33
3178 22:54:02.119127
3179 22:54:02.119244 [CBTSetCACLKResult] CA Dly = 33
3180 22:54:02.119360 CS Dly: 6 (0~37)
3181 22:54:02.119477 ==
3182 22:54:02.119593 Dram Type= 6, Freq= 0, CH_1, rank 1
3183 22:54:02.119710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3184 22:54:02.119829 ==
3185 22:54:02.119959 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3186 22:54:02.120057 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3187 22:54:02.120154 [CA 0] Center 37 (7~68) winsize 62
3188 22:54:02.120252 [CA 1] Center 38 (8~68) winsize 61
3189 22:54:02.120350 [CA 2] Center 34 (4~65) winsize 62
3190 22:54:02.120447 [CA 3] Center 33 (3~64) winsize 62
3191 22:54:02.120543 [CA 4] Center 34 (4~65) winsize 62
3192 22:54:02.120640 [CA 5] Center 33 (3~64) winsize 62
3193 22:54:02.120737
3194 22:54:02.120838 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3195 22:54:02.120937
3196 22:54:02.121035 [CATrainingPosCal] consider 2 rank data
3197 22:54:02.121155 u2DelayCellTimex100 = 270/100 ps
3198 22:54:02.121341 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3199 22:54:02.121679 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3200 22:54:02.121789 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3201 22:54:02.121888 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3202 22:54:02.121987 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3203 22:54:02.122102 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3204 22:54:02.122251
3205 22:54:02.122353 CA PerBit enable=1, Macro0, CA PI delay=33
3206 22:54:02.122453
3207 22:54:02.122551 [CBTSetCACLKResult] CA Dly = 33
3208 22:54:02.122650 CS Dly: 7 (0~40)
3209 22:54:02.122748
3210 22:54:02.122845 ----->DramcWriteLeveling(PI) begin...
3211 22:54:02.122957 ==
3212 22:54:02.123055 Dram Type= 6, Freq= 0, CH_1, rank 0
3213 22:54:02.123153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3214 22:54:02.123251 ==
3215 22:54:02.123348 Write leveling (Byte 0): 23 => 23
3216 22:54:02.123445 Write leveling (Byte 1): 28 => 28
3217 22:54:02.123542 DramcWriteLeveling(PI) end<-----
3218 22:54:02.123639
3219 22:54:02.123736 ==
3220 22:54:02.123833 Dram Type= 6, Freq= 0, CH_1, rank 0
3221 22:54:02.123929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3222 22:54:02.124026 ==
3223 22:54:02.124122 [Gating] SW mode calibration
3224 22:54:02.124219 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3225 22:54:02.124318 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3226 22:54:02.124417 0 15 0 | B1->B0 | 3131 3434 | 0 1 | (1 1) (1 1)
3227 22:54:02.124515 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3228 22:54:02.124675 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3229 22:54:02.124779 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3230 22:54:02.124878 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3231 22:54:02.124987 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3232 22:54:02.125071 0 15 24 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 0)
3233 22:54:02.125155 0 15 28 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (1 0)
3234 22:54:02.125239 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3235 22:54:02.125323 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3236 22:54:02.125421 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3237 22:54:02.125506 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3238 22:54:02.125590 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3239 22:54:02.125675 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3240 22:54:02.125758 1 0 24 | B1->B0 | 2525 3838 | 0 0 | (0 0) (0 0)
3241 22:54:02.125842 1 0 28 | B1->B0 | 3f3f 4646 | 0 0 | (1 1) (0 0)
3242 22:54:02.125925 1 1 0 | B1->B0 | 4444 4646 | 0 0 | (1 1) (0 0)
3243 22:54:02.126009 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3244 22:54:02.126093 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3245 22:54:02.126177 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3246 22:54:02.126261 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3247 22:54:02.126345 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3248 22:54:02.126428 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3249 22:54:02.126512 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3250 22:54:02.126594 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3251 22:54:02.126678 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3252 22:54:02.126761 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3253 22:54:02.126844 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3254 22:54:02.126927 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3255 22:54:02.127011 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3256 22:54:02.127094 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3257 22:54:02.127177 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3258 22:54:02.127262 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3259 22:54:02.127346 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3260 22:54:02.127429 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3261 22:54:02.127512 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3262 22:54:02.127596 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3263 22:54:02.127680 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3264 22:54:02.127763 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3265 22:54:02.127847 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3266 22:54:02.127930 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3267 22:54:02.128014 Total UI for P1: 0, mck2ui 16
3268 22:54:02.128099 best dqsien dly found for B0: ( 1, 3, 26)
3269 22:54:02.128183 Total UI for P1: 0, mck2ui 16
3270 22:54:02.128267 best dqsien dly found for B1: ( 1, 3, 26)
3271 22:54:02.128351 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3272 22:54:02.128435 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3273 22:54:02.128518
3274 22:54:02.128602 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3275 22:54:02.128686 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3276 22:54:02.128770 [Gating] SW calibration Done
3277 22:54:02.128853 ==
3278 22:54:02.128937 Dram Type= 6, Freq= 0, CH_1, rank 0
3279 22:54:02.129022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3280 22:54:02.129106 ==
3281 22:54:02.129189 RX Vref Scan: 0
3282 22:54:02.129309
3283 22:54:02.129413 RX Vref 0 -> 0, step: 1
3284 22:54:02.129499
3285 22:54:02.129582 RX Delay -40 -> 252, step: 8
3286 22:54:02.129667 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3287 22:54:02.129751 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3288 22:54:02.129835 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
3289 22:54:02.129919 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3290 22:54:02.130039 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3291 22:54:02.130136 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3292 22:54:02.130211 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3293 22:54:02.130285 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3294 22:54:02.130358 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3295 22:54:02.130432 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3296 22:54:02.130505 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3297 22:54:02.130578 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3298 22:54:02.130652 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3299 22:54:02.130725 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3300 22:54:02.131005 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3301 22:54:02.131087 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3302 22:54:02.131162 ==
3303 22:54:02.131236 Dram Type= 6, Freq= 0, CH_1, rank 0
3304 22:54:02.131309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3305 22:54:02.131384 ==
3306 22:54:02.131458 DQS Delay:
3307 22:54:02.131531 DQS0 = 0, DQS1 = 0
3308 22:54:02.131605 DQM Delay:
3309 22:54:02.131678 DQM0 = 118, DQM1 = 110
3310 22:54:02.131751 DQ Delay:
3311 22:54:02.131823 DQ0 =119, DQ1 =115, DQ2 =111, DQ3 =119
3312 22:54:02.131895 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =115
3313 22:54:02.131968 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =99
3314 22:54:02.132041 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3315 22:54:02.132114
3316 22:54:02.132187
3317 22:54:02.132260 ==
3318 22:54:02.132333 Dram Type= 6, Freq= 0, CH_1, rank 0
3319 22:54:02.132406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3320 22:54:02.132480 ==
3321 22:54:02.132553
3322 22:54:02.132625
3323 22:54:02.132697 TX Vref Scan disable
3324 22:54:02.132770 == TX Byte 0 ==
3325 22:54:02.132843 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3326 22:54:02.132917 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3327 22:54:02.132989 == TX Byte 1 ==
3328 22:54:02.133062 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3329 22:54:02.133136 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3330 22:54:02.133208 ==
3331 22:54:02.133281 Dram Type= 6, Freq= 0, CH_1, rank 0
3332 22:54:02.133366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3333 22:54:02.133442 ==
3334 22:54:02.133514 TX Vref=22, minBit 2, minWin=25, winSum=418
3335 22:54:02.133589 TX Vref=24, minBit 0, minWin=26, winSum=425
3336 22:54:02.133662 TX Vref=26, minBit 0, minWin=26, winSum=426
3337 22:54:02.133735 TX Vref=28, minBit 1, minWin=26, winSum=431
3338 22:54:02.133808 TX Vref=30, minBit 1, minWin=26, winSum=431
3339 22:54:02.133881 TX Vref=32, minBit 10, minWin=25, winSum=425
3340 22:54:02.133954 [TxChooseVref] Worse bit 1, Min win 26, Win sum 431, Final Vref 28
3341 22:54:02.134027
3342 22:54:02.134099 Final TX Range 1 Vref 28
3343 22:54:02.134174
3344 22:54:02.134246 ==
3345 22:54:02.134320 Dram Type= 6, Freq= 0, CH_1, rank 0
3346 22:54:02.134393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3347 22:54:02.134466 ==
3348 22:54:02.134538
3349 22:54:02.134610
3350 22:54:02.134682 TX Vref Scan disable
3351 22:54:02.134755 == TX Byte 0 ==
3352 22:54:02.134827 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3353 22:54:02.134900 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3354 22:54:02.134986 == TX Byte 1 ==
3355 22:54:02.135050 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3356 22:54:02.135115 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3357 22:54:02.135180
3358 22:54:02.135244 [DATLAT]
3359 22:54:02.135308 Freq=1200, CH1 RK0
3360 22:54:02.135374
3361 22:54:02.135438 DATLAT Default: 0xd
3362 22:54:02.135503 0, 0xFFFF, sum = 0
3363 22:54:02.135569 1, 0xFFFF, sum = 0
3364 22:54:02.135634 2, 0xFFFF, sum = 0
3365 22:54:02.135700 3, 0xFFFF, sum = 0
3366 22:54:02.135766 4, 0xFFFF, sum = 0
3367 22:54:02.135831 5, 0xFFFF, sum = 0
3368 22:54:02.135896 6, 0xFFFF, sum = 0
3369 22:54:02.135961 7, 0xFFFF, sum = 0
3370 22:54:02.136025 8, 0xFFFF, sum = 0
3371 22:54:02.136090 9, 0xFFFF, sum = 0
3372 22:54:02.136155 10, 0xFFFF, sum = 0
3373 22:54:02.136221 11, 0xFFFF, sum = 0
3374 22:54:02.136287 12, 0x0, sum = 1
3375 22:54:02.136351 13, 0x0, sum = 2
3376 22:54:02.136416 14, 0x0, sum = 3
3377 22:54:02.136481 15, 0x0, sum = 4
3378 22:54:02.136546 best_step = 13
3379 22:54:02.136609
3380 22:54:02.136673 ==
3381 22:54:02.136737 Dram Type= 6, Freq= 0, CH_1, rank 0
3382 22:54:02.136803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3383 22:54:02.136868 ==
3384 22:54:02.136932 RX Vref Scan: 1
3385 22:54:02.136997
3386 22:54:02.137061 Set Vref Range= 32 -> 127
3387 22:54:02.137125
3388 22:54:02.137189 RX Vref 32 -> 127, step: 1
3389 22:54:02.137253
3390 22:54:02.137317 RX Delay -21 -> 252, step: 4
3391 22:54:02.137391
3392 22:54:02.137456 Set Vref, RX VrefLevel [Byte0]: 32
3393 22:54:02.137520 [Byte1]: 32
3394 22:54:02.137585
3395 22:54:02.137649 Set Vref, RX VrefLevel [Byte0]: 33
3396 22:54:02.137713 [Byte1]: 33
3397 22:54:02.137777
3398 22:54:02.137841 Set Vref, RX VrefLevel [Byte0]: 34
3399 22:54:02.137906 [Byte1]: 34
3400 22:54:02.137971
3401 22:54:02.138034 Set Vref, RX VrefLevel [Byte0]: 35
3402 22:54:02.138099 [Byte1]: 35
3403 22:54:02.138163
3404 22:54:02.138227 Set Vref, RX VrefLevel [Byte0]: 36
3405 22:54:02.138291 [Byte1]: 36
3406 22:54:02.138357
3407 22:54:02.138422 Set Vref, RX VrefLevel [Byte0]: 37
3408 22:54:02.138487 [Byte1]: 37
3409 22:54:02.138552
3410 22:54:02.138615 Set Vref, RX VrefLevel [Byte0]: 38
3411 22:54:02.138680 [Byte1]: 38
3412 22:54:02.138745
3413 22:54:02.138810 Set Vref, RX VrefLevel [Byte0]: 39
3414 22:54:02.138874 [Byte1]: 39
3415 22:54:02.138938
3416 22:54:02.139002 Set Vref, RX VrefLevel [Byte0]: 40
3417 22:54:02.139067 [Byte1]: 40
3418 22:54:02.139131
3419 22:54:02.139195 Set Vref, RX VrefLevel [Byte0]: 41
3420 22:54:02.139259 [Byte1]: 41
3421 22:54:02.139324
3422 22:54:02.139387 Set Vref, RX VrefLevel [Byte0]: 42
3423 22:54:02.139451 [Byte1]: 42
3424 22:54:02.139515
3425 22:54:02.139578 Set Vref, RX VrefLevel [Byte0]: 43
3426 22:54:02.139642 [Byte1]: 43
3427 22:54:02.139722
3428 22:54:02.139788 Set Vref, RX VrefLevel [Byte0]: 44
3429 22:54:02.139852 [Byte1]: 44
3430 22:54:02.139928
3431 22:54:02.140003 Set Vref, RX VrefLevel [Byte0]: 45
3432 22:54:02.140061 [Byte1]: 45
3433 22:54:02.140120
3434 22:54:02.140177 Set Vref, RX VrefLevel [Byte0]: 46
3435 22:54:02.140235 [Byte1]: 46
3436 22:54:02.140292
3437 22:54:02.140350 Set Vref, RX VrefLevel [Byte0]: 47
3438 22:54:02.140408 [Byte1]: 47
3439 22:54:02.140467
3440 22:54:02.140524 Set Vref, RX VrefLevel [Byte0]: 48
3441 22:54:02.140582 [Byte1]: 48
3442 22:54:02.140640
3443 22:54:02.140697 Set Vref, RX VrefLevel [Byte0]: 49
3444 22:54:02.140755 [Byte1]: 49
3445 22:54:02.140813
3446 22:54:02.140870 Set Vref, RX VrefLevel [Byte0]: 50
3447 22:54:02.140928 [Byte1]: 50
3448 22:54:02.140987
3449 22:54:02.141045 Set Vref, RX VrefLevel [Byte0]: 51
3450 22:54:02.141103 [Byte1]: 51
3451 22:54:02.141160
3452 22:54:02.141218 Set Vref, RX VrefLevel [Byte0]: 52
3453 22:54:02.141276 [Byte1]: 52
3454 22:54:02.141340
3455 22:54:02.141400 Set Vref, RX VrefLevel [Byte0]: 53
3456 22:54:02.141459 [Byte1]: 53
3457 22:54:02.141517
3458 22:54:02.141574 Set Vref, RX VrefLevel [Byte0]: 54
3459 22:54:02.141632 [Byte1]: 54
3460 22:54:02.141690
3461 22:54:02.141747 Set Vref, RX VrefLevel [Byte0]: 55
3462 22:54:02.141805 [Byte1]: 55
3463 22:54:02.141863
3464 22:54:02.141922 Set Vref, RX VrefLevel [Byte0]: 56
3465 22:54:02.141980 [Byte1]: 56
3466 22:54:02.142038
3467 22:54:02.142096 Set Vref, RX VrefLevel [Byte0]: 57
3468 22:54:02.142360 [Byte1]: 57
3469 22:54:02.142429
3470 22:54:02.142489 Set Vref, RX VrefLevel [Byte0]: 58
3471 22:54:02.142548 [Byte1]: 58
3472 22:54:02.142644
3473 22:54:02.142708 Set Vref, RX VrefLevel [Byte0]: 59
3474 22:54:02.142768 [Byte1]: 59
3475 22:54:02.142827
3476 22:54:02.142885 Set Vref, RX VrefLevel [Byte0]: 60
3477 22:54:02.142943 [Byte1]: 60
3478 22:54:02.143001
3479 22:54:02.143059 Set Vref, RX VrefLevel [Byte0]: 61
3480 22:54:02.143117 [Byte1]: 61
3481 22:54:02.143175
3482 22:54:02.143233 Set Vref, RX VrefLevel [Byte0]: 62
3483 22:54:02.143291 [Byte1]: 62
3484 22:54:02.143349
3485 22:54:02.143407 Set Vref, RX VrefLevel [Byte0]: 63
3486 22:54:02.143464 [Byte1]: 63
3487 22:54:02.143523
3488 22:54:02.143581 Set Vref, RX VrefLevel [Byte0]: 64
3489 22:54:02.143639 [Byte1]: 64
3490 22:54:02.143698
3491 22:54:02.143756 Set Vref, RX VrefLevel [Byte0]: 65
3492 22:54:02.143814 [Byte1]: 65
3493 22:54:02.143871
3494 22:54:02.143929 Set Vref, RX VrefLevel [Byte0]: 66
3495 22:54:02.143986 [Byte1]: 66
3496 22:54:02.144044
3497 22:54:02.144101 Final RX Vref Byte 0 = 50 to rank0
3498 22:54:02.144160 Final RX Vref Byte 1 = 52 to rank0
3499 22:54:02.144218 Final RX Vref Byte 0 = 50 to rank1
3500 22:54:02.144277 Final RX Vref Byte 1 = 52 to rank1==
3501 22:54:02.144335 Dram Type= 6, Freq= 0, CH_1, rank 0
3502 22:54:02.144392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3503 22:54:02.144451 ==
3504 22:54:02.144509 DQS Delay:
3505 22:54:02.144568 DQS0 = 0, DQS1 = 0
3506 22:54:02.144625 DQM Delay:
3507 22:54:02.144683 DQM0 = 117, DQM1 = 110
3508 22:54:02.144741 DQ Delay:
3509 22:54:02.144798 DQ0 =122, DQ1 =112, DQ2 =110, DQ3 =112
3510 22:54:02.144857 DQ4 =114, DQ5 =128, DQ6 =126, DQ7 =114
3511 22:54:02.144915 DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =98
3512 22:54:02.144981 DQ12 =118, DQ13 =116, DQ14 =120, DQ15 =120
3513 22:54:02.145034
3514 22:54:02.145087
3515 22:54:02.145152 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f5, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 409 ps
3516 22:54:02.145208 CH1 RK0: MR19=403, MR18=1F5
3517 22:54:02.145261 CH1_RK0: MR19=0x403, MR18=0x1F5, DQSOSC=409, MR23=63, INC=39, DEC=26
3518 22:54:02.145315
3519 22:54:02.145374 ----->DramcWriteLeveling(PI) begin...
3520 22:54:02.145429 ==
3521 22:54:02.145483 Dram Type= 6, Freq= 0, CH_1, rank 1
3522 22:54:02.145536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3523 22:54:02.145589 ==
3524 22:54:02.145641 Write leveling (Byte 0): 24 => 24
3525 22:54:02.145695 Write leveling (Byte 1): 28 => 28
3526 22:54:02.145748 DramcWriteLeveling(PI) end<-----
3527 22:54:02.145800
3528 22:54:02.145852 ==
3529 22:54:02.145905 Dram Type= 6, Freq= 0, CH_1, rank 1
3530 22:54:02.145958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3531 22:54:02.146012 ==
3532 22:54:02.146065 [Gating] SW mode calibration
3533 22:54:02.146118 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3534 22:54:02.146171 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3535 22:54:02.146224 0 15 0 | B1->B0 | 3333 3333 | 1 1 | (1 1) (1 1)
3536 22:54:02.146277 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3537 22:54:02.146330 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3538 22:54:02.146383 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3539 22:54:02.146436 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3540 22:54:02.146488 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3541 22:54:02.146542 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
3542 22:54:02.146594 0 15 28 | B1->B0 | 2424 2929 | 0 0 | (0 0) (0 0)
3543 22:54:02.146647 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3544 22:54:02.146737 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3545 22:54:02.146795 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3546 22:54:02.146849 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3547 22:54:02.146902 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3548 22:54:02.146956 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3549 22:54:02.147009 1 0 24 | B1->B0 | 2c2c 2424 | 0 0 | (0 0) (0 0)
3550 22:54:02.147062 1 0 28 | B1->B0 | 4444 3e3e | 0 1 | (0 0) (0 0)
3551 22:54:02.147115 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3552 22:54:02.147168 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3553 22:54:02.147221 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3554 22:54:02.147274 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3555 22:54:02.147327 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3556 22:54:02.147381 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3557 22:54:02.147434 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3558 22:54:02.147486 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3559 22:54:02.147539 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3560 22:54:02.147592 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3561 22:54:02.147645 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3562 22:54:02.147697 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3563 22:54:02.147750 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3564 22:54:02.147803 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3565 22:54:02.147857 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3566 22:54:02.147910 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3567 22:54:02.147963 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3568 22:54:02.148016 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3569 22:54:02.148069 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3570 22:54:02.148122 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3571 22:54:02.148174 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3572 22:54:02.148227 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3573 22:54:02.148280 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3574 22:54:02.148333 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3575 22:54:02.148385 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3576 22:54:02.148438 Total UI for P1: 0, mck2ui 16
3577 22:54:02.148492 best dqsien dly found for B0: ( 1, 3, 28)
3578 22:54:02.148545 Total UI for P1: 0, mck2ui 16
3579 22:54:02.148790 best dqsien dly found for B1: ( 1, 3, 26)
3580 22:54:02.148850 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3581 22:54:02.148904 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3582 22:54:02.148958
3583 22:54:02.149011 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3584 22:54:02.149064 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3585 22:54:02.149118 [Gating] SW calibration Done
3586 22:54:02.149171 ==
3587 22:54:02.149224 Dram Type= 6, Freq= 0, CH_1, rank 1
3588 22:54:02.149277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3589 22:54:02.149335 ==
3590 22:54:02.149389 RX Vref Scan: 0
3591 22:54:02.149442
3592 22:54:02.149495 RX Vref 0 -> 0, step: 1
3593 22:54:02.149548
3594 22:54:02.149600 RX Delay -40 -> 252, step: 8
3595 22:54:02.149654 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
3596 22:54:02.149706 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3597 22:54:02.149759 iDelay=208, Bit 2, Center 107 (40 ~ 175) 136
3598 22:54:02.149812 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3599 22:54:02.149865 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3600 22:54:02.149918 iDelay=208, Bit 5, Center 127 (56 ~ 199) 144
3601 22:54:02.149972 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
3602 22:54:02.150037 iDelay=208, Bit 7, Center 119 (48 ~ 191) 144
3603 22:54:02.150088 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3604 22:54:02.150140 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3605 22:54:02.150192 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3606 22:54:02.150243 iDelay=208, Bit 11, Center 103 (32 ~ 175) 144
3607 22:54:02.150295 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3608 22:54:02.150346 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3609 22:54:02.150398 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3610 22:54:02.150450 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3611 22:54:02.150501 ==
3612 22:54:02.150553 Dram Type= 6, Freq= 0, CH_1, rank 1
3613 22:54:02.150605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3614 22:54:02.150657 ==
3615 22:54:02.150708 DQS Delay:
3616 22:54:02.150759 DQS0 = 0, DQS1 = 0
3617 22:54:02.150811 DQM Delay:
3618 22:54:02.150863 DQM0 = 118, DQM1 = 110
3619 22:54:02.150914 DQ Delay:
3620 22:54:02.150966 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =115
3621 22:54:02.151018 DQ4 =115, DQ5 =127, DQ6 =131, DQ7 =119
3622 22:54:02.151070 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
3623 22:54:02.151122 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3624 22:54:02.151174
3625 22:54:02.151224
3626 22:54:02.151276 ==
3627 22:54:02.151327 Dram Type= 6, Freq= 0, CH_1, rank 1
3628 22:54:02.151379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3629 22:54:02.151431 ==
3630 22:54:02.151483
3631 22:54:02.151534
3632 22:54:02.151585 TX Vref Scan disable
3633 22:54:02.151637 == TX Byte 0 ==
3634 22:54:02.151689 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3635 22:54:02.151741 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3636 22:54:02.151793 == TX Byte 1 ==
3637 22:54:02.151845 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3638 22:54:02.151897 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3639 22:54:02.151948 ==
3640 22:54:02.152000 Dram Type= 6, Freq= 0, CH_1, rank 1
3641 22:54:02.152051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3642 22:54:02.152104 ==
3643 22:54:02.152156 TX Vref=22, minBit 0, minWin=26, winSum=422
3644 22:54:02.152208 TX Vref=24, minBit 0, minWin=26, winSum=428
3645 22:54:02.152260 TX Vref=26, minBit 9, minWin=26, winSum=435
3646 22:54:02.152312 TX Vref=28, minBit 5, minWin=26, winSum=433
3647 22:54:02.152365 TX Vref=30, minBit 5, minWin=26, winSum=429
3648 22:54:02.152416 TX Vref=32, minBit 0, minWin=26, winSum=428
3649 22:54:02.152468 [TxChooseVref] Worse bit 9, Min win 26, Win sum 435, Final Vref 26
3650 22:54:02.152520
3651 22:54:02.152571 Final TX Range 1 Vref 26
3652 22:54:02.152623
3653 22:54:02.152674 ==
3654 22:54:02.152726 Dram Type= 6, Freq= 0, CH_1, rank 1
3655 22:54:02.152778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3656 22:54:02.152830 ==
3657 22:54:02.152882
3658 22:54:02.152933
3659 22:54:02.152985 TX Vref Scan disable
3660 22:54:02.153037 == TX Byte 0 ==
3661 22:54:02.153088 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3662 22:54:02.153140 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3663 22:54:02.153192 == TX Byte 1 ==
3664 22:54:02.153243 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3665 22:54:02.153295 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3666 22:54:02.153376
3667 22:54:02.153442 [DATLAT]
3668 22:54:02.153493 Freq=1200, CH1 RK1
3669 22:54:02.153545
3670 22:54:02.153597 DATLAT Default: 0xd
3671 22:54:02.153648 0, 0xFFFF, sum = 0
3672 22:54:02.153701 1, 0xFFFF, sum = 0
3673 22:54:02.153755 2, 0xFFFF, sum = 0
3674 22:54:02.153807 3, 0xFFFF, sum = 0
3675 22:54:02.153860 4, 0xFFFF, sum = 0
3676 22:54:02.153912 5, 0xFFFF, sum = 0
3677 22:54:02.153964 6, 0xFFFF, sum = 0
3678 22:54:02.154016 7, 0xFFFF, sum = 0
3679 22:54:02.154068 8, 0xFFFF, sum = 0
3680 22:54:02.154120 9, 0xFFFF, sum = 0
3681 22:54:02.154171 10, 0xFFFF, sum = 0
3682 22:54:02.154224 11, 0xFFFF, sum = 0
3683 22:54:02.154276 12, 0x0, sum = 1
3684 22:54:02.154329 13, 0x0, sum = 2
3685 22:54:02.154382 14, 0x0, sum = 3
3686 22:54:02.154434 15, 0x0, sum = 4
3687 22:54:02.154486 best_step = 13
3688 22:54:02.154537
3689 22:54:02.154588 ==
3690 22:54:02.154640 Dram Type= 6, Freq= 0, CH_1, rank 1
3691 22:54:02.154692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3692 22:54:02.154744 ==
3693 22:54:02.154796 RX Vref Scan: 0
3694 22:54:02.154847
3695 22:54:02.154899 RX Vref 0 -> 0, step: 1
3696 22:54:02.154950
3697 22:54:02.155001 RX Delay -21 -> 252, step: 4
3698 22:54:02.155052 iDelay=199, Bit 0, Center 120 (51 ~ 190) 140
3699 22:54:02.155104 iDelay=199, Bit 1, Center 112 (47 ~ 178) 132
3700 22:54:02.155156 iDelay=199, Bit 2, Center 110 (47 ~ 174) 128
3701 22:54:02.155208 iDelay=199, Bit 3, Center 114 (51 ~ 178) 128
3702 22:54:02.155259 iDelay=199, Bit 4, Center 118 (51 ~ 186) 136
3703 22:54:02.155311 iDelay=199, Bit 5, Center 126 (59 ~ 194) 136
3704 22:54:02.155362 iDelay=199, Bit 6, Center 130 (63 ~ 198) 136
3705 22:54:02.155414 iDelay=199, Bit 7, Center 116 (51 ~ 182) 132
3706 22:54:02.155465 iDelay=199, Bit 8, Center 98 (35 ~ 162) 128
3707 22:54:02.155516 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3708 22:54:02.155568 iDelay=199, Bit 10, Center 112 (47 ~ 178) 132
3709 22:54:02.155619 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3710 22:54:02.155671 iDelay=199, Bit 12, Center 120 (55 ~ 186) 132
3711 22:54:02.155722 iDelay=199, Bit 13, Center 120 (55 ~ 186) 132
3712 22:54:02.155773 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
3713 22:54:02.155825 iDelay=199, Bit 15, Center 118 (51 ~ 186) 136
3714 22:54:02.155876 ==
3715 22:54:02.155928 Dram Type= 6, Freq= 0, CH_1, rank 1
3716 22:54:02.155980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3717 22:54:02.156032 ==
3718 22:54:02.156083 DQS Delay:
3719 22:54:02.156134 DQS0 = 0, DQS1 = 0
3720 22:54:02.156377 DQM Delay:
3721 22:54:02.156434 DQM0 = 118, DQM1 = 110
3722 22:54:02.156487 DQ Delay:
3723 22:54:02.156539 DQ0 =120, DQ1 =112, DQ2 =110, DQ3 =114
3724 22:54:02.156591 DQ4 =118, DQ5 =126, DQ6 =130, DQ7 =116
3725 22:54:02.156644 DQ8 =98, DQ9 =100, DQ10 =112, DQ11 =100
3726 22:54:02.156696 DQ12 =120, DQ13 =120, DQ14 =118, DQ15 =118
3727 22:54:02.156748
3728 22:54:02.156800
3729 22:54:02.156851 [DQSOSCAuto] RK1, (LSB)MR18= 0xf6f0, (MSB)MR19= 0x303, tDQSOscB0 = 416 ps tDQSOscB1 = 414 ps
3730 22:54:02.156904 CH1 RK1: MR19=303, MR18=F6F0
3731 22:54:02.156956 CH1_RK1: MR19=0x303, MR18=0xF6F0, DQSOSC=414, MR23=63, INC=38, DEC=25
3732 22:54:02.157009 [RxdqsGatingPostProcess] freq 1200
3733 22:54:02.157061 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3734 22:54:02.157113 best DQS0 dly(2T, 0.5T) = (0, 11)
3735 22:54:02.157164 best DQS1 dly(2T, 0.5T) = (0, 11)
3736 22:54:02.157215 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3737 22:54:02.157267 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3738 22:54:02.157318 best DQS0 dly(2T, 0.5T) = (0, 11)
3739 22:54:02.157415 best DQS1 dly(2T, 0.5T) = (0, 11)
3740 22:54:02.157467 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3741 22:54:02.157518 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3742 22:54:02.157569 Pre-setting of DQS Precalculation
3743 22:54:02.157621 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3744 22:54:02.157673 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3745 22:54:02.157726 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3746 22:54:02.157778
3747 22:54:02.157829
3748 22:54:02.157880 [Calibration Summary] 2400 Mbps
3749 22:54:02.157932 CH 0, Rank 0
3750 22:54:02.157983 SW Impedance : PASS
3751 22:54:02.158035 DUTY Scan : NO K
3752 22:54:02.158087 ZQ Calibration : PASS
3753 22:54:02.158138 Jitter Meter : NO K
3754 22:54:02.158190 CBT Training : PASS
3755 22:54:02.158242 Write leveling : PASS
3756 22:54:02.158293 RX DQS gating : PASS
3757 22:54:02.158345 RX DQ/DQS(RDDQC) : PASS
3758 22:54:02.158397 TX DQ/DQS : PASS
3759 22:54:02.158449 RX DATLAT : PASS
3760 22:54:02.158501 RX DQ/DQS(Engine): PASS
3761 22:54:02.158553 TX OE : NO K
3762 22:54:02.158605 All Pass.
3763 22:54:02.158657
3764 22:54:02.158709 CH 0, Rank 1
3765 22:54:02.158760 SW Impedance : PASS
3766 22:54:02.158812 DUTY Scan : NO K
3767 22:54:02.158864 ZQ Calibration : PASS
3768 22:54:02.158915 Jitter Meter : NO K
3769 22:54:02.158967 CBT Training : PASS
3770 22:54:02.159018 Write leveling : PASS
3771 22:54:02.159070 RX DQS gating : PASS
3772 22:54:02.159121 RX DQ/DQS(RDDQC) : PASS
3773 22:54:02.159173 TX DQ/DQS : PASS
3774 22:54:02.159223 RX DATLAT : PASS
3775 22:54:02.159275 RX DQ/DQS(Engine): PASS
3776 22:54:02.159326 TX OE : NO K
3777 22:54:02.159378 All Pass.
3778 22:54:02.159429
3779 22:54:02.159480 CH 1, Rank 0
3780 22:54:02.159533 SW Impedance : PASS
3781 22:54:02.159584 DUTY Scan : NO K
3782 22:54:02.159672 ZQ Calibration : PASS
3783 22:54:02.159729 Jitter Meter : NO K
3784 22:54:02.159781 CBT Training : PASS
3785 22:54:02.159833 Write leveling : PASS
3786 22:54:02.159885 RX DQS gating : PASS
3787 22:54:02.159937 RX DQ/DQS(RDDQC) : PASS
3788 22:54:02.159988 TX DQ/DQS : PASS
3789 22:54:02.160040 RX DATLAT : PASS
3790 22:54:02.160091 RX DQ/DQS(Engine): PASS
3791 22:54:02.160143 TX OE : NO K
3792 22:54:02.160195 All Pass.
3793 22:54:02.160246
3794 22:54:02.160298 CH 1, Rank 1
3795 22:54:02.160349 SW Impedance : PASS
3796 22:54:02.160400 DUTY Scan : NO K
3797 22:54:02.160451 ZQ Calibration : PASS
3798 22:54:02.160503 Jitter Meter : NO K
3799 22:54:02.160554 CBT Training : PASS
3800 22:54:02.160605 Write leveling : PASS
3801 22:54:02.160656 RX DQS gating : PASS
3802 22:54:02.160708 RX DQ/DQS(RDDQC) : PASS
3803 22:54:02.160759 TX DQ/DQS : PASS
3804 22:54:02.160811 RX DATLAT : PASS
3805 22:54:02.160862 RX DQ/DQS(Engine): PASS
3806 22:54:02.160914 TX OE : NO K
3807 22:54:02.160966 All Pass.
3808 22:54:02.161017
3809 22:54:02.161069 DramC Write-DBI off
3810 22:54:02.161121 PER_BANK_REFRESH: Hybrid Mode
3811 22:54:02.161173 TX_TRACKING: ON
3812 22:54:02.161224 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3813 22:54:02.161277 [FAST_K] Save calibration result to emmc
3814 22:54:02.161334 dramc_set_vcore_voltage set vcore to 650000
3815 22:54:02.161426 Read voltage for 600, 5
3816 22:54:02.161477 Vio18 = 0
3817 22:54:02.161528 Vcore = 650000
3818 22:54:02.161579 Vdram = 0
3819 22:54:02.161630 Vddq = 0
3820 22:54:02.161682 Vmddr = 0
3821 22:54:02.161733 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3822 22:54:02.161785 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3823 22:54:02.161837 MEM_TYPE=3, freq_sel=19
3824 22:54:02.161890 sv_algorithm_assistance_LP4_1600
3825 22:54:02.161942 ============ PULL DRAM RESETB DOWN ============
3826 22:54:02.161994 ========== PULL DRAM RESETB DOWN end =========
3827 22:54:02.162046 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3828 22:54:02.162098 ===================================
3829 22:54:02.162149 LPDDR4 DRAM CONFIGURATION
3830 22:54:02.162201 ===================================
3831 22:54:02.162253 EX_ROW_EN[0] = 0x0
3832 22:54:02.162304 EX_ROW_EN[1] = 0x0
3833 22:54:02.162356 LP4Y_EN = 0x0
3834 22:54:02.162407 WORK_FSP = 0x0
3835 22:54:02.162459 WL = 0x2
3836 22:54:02.162510 RL = 0x2
3837 22:54:02.162562 BL = 0x2
3838 22:54:02.162613 RPST = 0x0
3839 22:54:02.162664 RD_PRE = 0x0
3840 22:54:02.162716 WR_PRE = 0x1
3841 22:54:02.162768 WR_PST = 0x0
3842 22:54:02.162819 DBI_WR = 0x0
3843 22:54:02.162871 DBI_RD = 0x0
3844 22:54:02.162922 OTF = 0x1
3845 22:54:02.162973 ===================================
3846 22:54:02.163025 ===================================
3847 22:54:02.163076 ANA top config
3848 22:54:02.163127 ===================================
3849 22:54:02.163180 DLL_ASYNC_EN = 0
3850 22:54:02.163231 ALL_SLAVE_EN = 1
3851 22:54:02.163282 NEW_RANK_MODE = 1
3852 22:54:02.163334 DLL_IDLE_MODE = 1
3853 22:54:02.163385 LP45_APHY_COMB_EN = 1
3854 22:54:02.163437 TX_ODT_DIS = 1
3855 22:54:02.163489 NEW_8X_MODE = 1
3856 22:54:02.163541 ===================================
3857 22:54:02.163592 ===================================
3858 22:54:02.163645 data_rate = 1200
3859 22:54:02.163696 CKR = 1
3860 22:54:02.163748 DQ_P2S_RATIO = 8
3861 22:54:02.163800 ===================================
3862 22:54:02.163852 CA_P2S_RATIO = 8
3863 22:54:02.163903 DQ_CA_OPEN = 0
3864 22:54:02.164143 DQ_SEMI_OPEN = 0
3865 22:54:02.164201 CA_SEMI_OPEN = 0
3866 22:54:02.164253 CA_FULL_RATE = 0
3867 22:54:02.164305 DQ_CKDIV4_EN = 1
3868 22:54:02.164356 CA_CKDIV4_EN = 1
3869 22:54:02.164408 CA_PREDIV_EN = 0
3870 22:54:02.164460 PH8_DLY = 0
3871 22:54:02.164511 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3872 22:54:02.164562 DQ_AAMCK_DIV = 4
3873 22:54:02.164613 CA_AAMCK_DIV = 4
3874 22:54:02.164665 CA_ADMCK_DIV = 4
3875 22:54:02.164716 DQ_TRACK_CA_EN = 0
3876 22:54:02.164767 CA_PICK = 600
3877 22:54:02.164818 CA_MCKIO = 600
3878 22:54:02.164870 MCKIO_SEMI = 0
3879 22:54:02.164930 PLL_FREQ = 2288
3880 22:54:02.164993 DQ_UI_PI_RATIO = 32
3881 22:54:02.165045 CA_UI_PI_RATIO = 0
3882 22:54:02.165097 ===================================
3883 22:54:02.165149 ===================================
3884 22:54:02.165201 memory_type:LPDDR4
3885 22:54:02.165253 GP_NUM : 10
3886 22:54:02.165304 SRAM_EN : 1
3887 22:54:02.165396 MD32_EN : 0
3888 22:54:02.165449 ===================================
3889 22:54:02.165501 [ANA_INIT] >>>>>>>>>>>>>>
3890 22:54:02.165554 <<<<<< [CONFIGURE PHASE]: ANA_TX
3891 22:54:02.165606 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3892 22:54:02.165658 ===================================
3893 22:54:02.165711 data_rate = 1200,PCW = 0X5800
3894 22:54:02.165763 ===================================
3895 22:54:02.165815 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3896 22:54:02.165893 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3897 22:54:02.165960 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3898 22:54:02.166012 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3899 22:54:02.166064 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3900 22:54:02.166115 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3901 22:54:02.166166 [ANA_INIT] flow start
3902 22:54:02.166217 [ANA_INIT] PLL >>>>>>>>
3903 22:54:02.166269 [ANA_INIT] PLL <<<<<<<<
3904 22:54:02.166320 [ANA_INIT] MIDPI >>>>>>>>
3905 22:54:02.166372 [ANA_INIT] MIDPI <<<<<<<<
3906 22:54:02.166422 [ANA_INIT] DLL >>>>>>>>
3907 22:54:02.166474 [ANA_INIT] flow end
3908 22:54:02.166525 ============ LP4 DIFF to SE enter ============
3909 22:54:02.166577 ============ LP4 DIFF to SE exit ============
3910 22:54:02.166640 [ANA_INIT] <<<<<<<<<<<<<
3911 22:54:02.166694 [Flow] Enable top DCM control >>>>>
3912 22:54:02.166746 [Flow] Enable top DCM control <<<<<
3913 22:54:02.166809 Enable DLL master slave shuffle
3914 22:54:02.166891 ==============================================================
3915 22:54:02.166946 Gating Mode config
3916 22:54:02.166999 ==============================================================
3917 22:54:02.167052 Config description:
3918 22:54:02.167103 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3919 22:54:02.167170 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3920 22:54:02.167224 SELPH_MODE 0: By rank 1: By Phase
3921 22:54:02.167281 ==============================================================
3922 22:54:02.167359 GAT_TRACK_EN = 1
3923 22:54:02.167414 RX_GATING_MODE = 2
3924 22:54:02.167466 RX_GATING_TRACK_MODE = 2
3925 22:54:02.167519 SELPH_MODE = 1
3926 22:54:02.167582 PICG_EARLY_EN = 1
3927 22:54:02.167635 VALID_LAT_VALUE = 1
3928 22:54:02.167695 ==============================================================
3929 22:54:02.167771 Enter into Gating configuration >>>>
3930 22:54:02.167825 Exit from Gating configuration <<<<
3931 22:54:02.167877 Enter into DVFS_PRE_config >>>>>
3932 22:54:02.167975 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3933 22:54:02.168030 Exit from DVFS_PRE_config <<<<<
3934 22:54:02.168106 Enter into PICG configuration >>>>
3935 22:54:02.168207 Exit from PICG configuration <<<<
3936 22:54:02.168690 [RX_INPUT] configuration >>>>>
3937 22:54:02.172102 [RX_INPUT] configuration <<<<<
3938 22:54:02.175615 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3939 22:54:02.181904 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3940 22:54:02.188270 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3941 22:54:02.195348 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3942 22:54:02.198190 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3943 22:54:02.205321 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3944 22:54:02.208959 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3945 22:54:02.215046 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3946 22:54:02.218014 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3947 22:54:02.221257 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3948 22:54:02.224813 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3949 22:54:02.231692 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3950 22:54:02.234732 ===================================
3951 22:54:02.237638 LPDDR4 DRAM CONFIGURATION
3952 22:54:02.241388 ===================================
3953 22:54:02.241586 EX_ROW_EN[0] = 0x0
3954 22:54:02.244529 EX_ROW_EN[1] = 0x0
3955 22:54:02.244753 LP4Y_EN = 0x0
3956 22:54:02.247724 WORK_FSP = 0x0
3957 22:54:02.247991 WL = 0x2
3958 22:54:02.250932 RL = 0x2
3959 22:54:02.251211 BL = 0x2
3960 22:54:02.254605 RPST = 0x0
3961 22:54:02.254886 RD_PRE = 0x0
3962 22:54:02.257763 WR_PRE = 0x1
3963 22:54:02.261208 WR_PST = 0x0
3964 22:54:02.261631 DBI_WR = 0x0
3965 22:54:02.264495 DBI_RD = 0x0
3966 22:54:02.264920 OTF = 0x1
3967 22:54:02.267614 ===================================
3968 22:54:02.271089 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3969 22:54:02.277985 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3970 22:54:02.281069 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3971 22:54:02.284613 ===================================
3972 22:54:02.287431 LPDDR4 DRAM CONFIGURATION
3973 22:54:02.290937 ===================================
3974 22:54:02.291484 EX_ROW_EN[0] = 0x10
3975 22:54:02.293948 EX_ROW_EN[1] = 0x0
3976 22:54:02.294487 LP4Y_EN = 0x0
3977 22:54:02.297325 WORK_FSP = 0x0
3978 22:54:02.297912 WL = 0x2
3979 22:54:02.300541 RL = 0x2
3980 22:54:02.300996 BL = 0x2
3981 22:54:02.303867 RPST = 0x0
3982 22:54:02.307368 RD_PRE = 0x0
3983 22:54:02.307982 WR_PRE = 0x1
3984 22:54:02.310261 WR_PST = 0x0
3985 22:54:02.310738 DBI_WR = 0x0
3986 22:54:02.313653 DBI_RD = 0x0
3987 22:54:02.314108 OTF = 0x1
3988 22:54:02.317390 ===================================
3989 22:54:02.323579 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3990 22:54:02.327292 nWR fixed to 30
3991 22:54:02.330525 [ModeRegInit_LP4] CH0 RK0
3992 22:54:02.330936 [ModeRegInit_LP4] CH0 RK1
3993 22:54:02.333955 [ModeRegInit_LP4] CH1 RK0
3994 22:54:02.337412 [ModeRegInit_LP4] CH1 RK1
3995 22:54:02.337708 match AC timing 17
3996 22:54:02.344298 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3997 22:54:02.347131 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3998 22:54:02.350508 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3999 22:54:02.356808 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
4000 22:54:02.360399 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
4001 22:54:02.360788 ==
4002 22:54:02.363777 Dram Type= 6, Freq= 0, CH_0, rank 0
4003 22:54:02.366973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4004 22:54:02.367364 ==
4005 22:54:02.373472 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4006 22:54:02.380160 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4007 22:54:02.383693 [CA 0] Center 36 (6~66) winsize 61
4008 22:54:02.386761 [CA 1] Center 36 (6~66) winsize 61
4009 22:54:02.390069 [CA 2] Center 34 (4~65) winsize 62
4010 22:54:02.393804 [CA 3] Center 34 (4~65) winsize 62
4011 22:54:02.396838 [CA 4] Center 33 (3~64) winsize 62
4012 22:54:02.400303 [CA 5] Center 33 (3~64) winsize 62
4013 22:54:02.400878
4014 22:54:02.403122 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4015 22:54:02.403580
4016 22:54:02.406505 [CATrainingPosCal] consider 1 rank data
4017 22:54:02.410314 u2DelayCellTimex100 = 270/100 ps
4018 22:54:02.413619 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4019 22:54:02.416494 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4020 22:54:02.419658 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4021 22:54:02.423382 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4022 22:54:02.429997 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4023 22:54:02.432964 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4024 22:54:02.433540
4025 22:54:02.436404 CA PerBit enable=1, Macro0, CA PI delay=33
4026 22:54:02.436909
4027 22:54:02.439843 [CBTSetCACLKResult] CA Dly = 33
4028 22:54:02.440257 CS Dly: 4 (0~35)
4029 22:54:02.440678 ==
4030 22:54:02.443019 Dram Type= 6, Freq= 0, CH_0, rank 1
4031 22:54:02.449319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4032 22:54:02.449794 ==
4033 22:54:02.453698 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4034 22:54:02.459944 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4035 22:54:02.463642 [CA 0] Center 36 (6~66) winsize 61
4036 22:54:02.466365 [CA 1] Center 36 (6~66) winsize 61
4037 22:54:02.469200 [CA 2] Center 33 (3~64) winsize 62
4038 22:54:02.472796 [CA 3] Center 34 (4~64) winsize 61
4039 22:54:02.475826 [CA 4] Center 33 (2~64) winsize 63
4040 22:54:02.479256 [CA 5] Center 33 (2~64) winsize 63
4041 22:54:02.479714
4042 22:54:02.482626 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4043 22:54:02.483087
4044 22:54:02.486172 [CATrainingPosCal] consider 2 rank data
4045 22:54:02.489570 u2DelayCellTimex100 = 270/100 ps
4046 22:54:02.492446 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4047 22:54:02.498867 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4048 22:54:02.502346 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4049 22:54:02.505701 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4050 22:54:02.509371 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4051 22:54:02.512231 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4052 22:54:02.512686
4053 22:54:02.515468 CA PerBit enable=1, Macro0, CA PI delay=33
4054 22:54:02.516123
4055 22:54:02.518761 [CBTSetCACLKResult] CA Dly = 33
4056 22:54:02.522212 CS Dly: 5 (0~37)
4057 22:54:02.522950
4058 22:54:02.525469 ----->DramcWriteLeveling(PI) begin...
4059 22:54:02.525904 ==
4060 22:54:02.528599 Dram Type= 6, Freq= 0, CH_0, rank 0
4061 22:54:02.532497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4062 22:54:02.533015 ==
4063 22:54:02.535719 Write leveling (Byte 0): 31 => 31
4064 22:54:02.538761 Write leveling (Byte 1): 30 => 30
4065 22:54:02.541927 DramcWriteLeveling(PI) end<-----
4066 22:54:02.542364
4067 22:54:02.542685 ==
4068 22:54:02.545136 Dram Type= 6, Freq= 0, CH_0, rank 0
4069 22:54:02.548659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4070 22:54:02.549429 ==
4071 22:54:02.551701 [Gating] SW mode calibration
4072 22:54:02.559197 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4073 22:54:02.565261 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4074 22:54:02.568760 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4075 22:54:02.571947 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4076 22:54:02.578252 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4077 22:54:02.581896 0 9 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
4078 22:54:02.584937 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
4079 22:54:02.591436 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4080 22:54:02.594888 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4081 22:54:02.597877 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4082 22:54:02.604973 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4083 22:54:02.608223 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4084 22:54:02.611731 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4085 22:54:02.617786 0 10 12 | B1->B0 | 2625 2f2f | 1 1 | (0 0) (0 0)
4086 22:54:02.620998 0 10 16 | B1->B0 | 3333 4343 | 0 1 | (0 0) (0 0)
4087 22:54:02.624571 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4088 22:54:02.630838 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4089 22:54:02.634754 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4090 22:54:02.637680 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4091 22:54:02.643829 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4092 22:54:02.647379 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4093 22:54:02.651031 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4094 22:54:02.657107 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4095 22:54:02.660865 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4096 22:54:02.664188 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4097 22:54:02.670754 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4098 22:54:02.673750 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4099 22:54:02.677529 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4100 22:54:02.684067 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4101 22:54:02.687259 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4102 22:54:02.690920 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4103 22:54:02.697428 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4104 22:54:02.700395 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4105 22:54:02.704041 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4106 22:54:02.710334 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4107 22:54:02.713366 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4108 22:54:02.716766 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4109 22:54:02.723410 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4110 22:54:02.726495 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4111 22:54:02.729947 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4112 22:54:02.733518 Total UI for P1: 0, mck2ui 16
4113 22:54:02.736692 best dqsien dly found for B0: ( 0, 13, 14)
4114 22:54:02.740252 Total UI for P1: 0, mck2ui 16
4115 22:54:02.743904 best dqsien dly found for B1: ( 0, 13, 18)
4116 22:54:02.746416 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4117 22:54:02.749927 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4118 22:54:02.753384
4119 22:54:02.756618 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4120 22:54:02.759651 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4121 22:54:02.763254 [Gating] SW calibration Done
4122 22:54:02.763976 ==
4123 22:54:02.766394 Dram Type= 6, Freq= 0, CH_0, rank 0
4124 22:54:02.770020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4125 22:54:02.770515 ==
4126 22:54:02.770881 RX Vref Scan: 0
4127 22:54:02.771216
4128 22:54:02.772697 RX Vref 0 -> 0, step: 1
4129 22:54:02.773154
4130 22:54:02.776195 RX Delay -230 -> 252, step: 16
4131 22:54:02.779857 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4132 22:54:02.786445 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4133 22:54:02.789483 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4134 22:54:02.792973 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4135 22:54:02.796224 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4136 22:54:02.799808 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4137 22:54:02.806319 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4138 22:54:02.809292 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4139 22:54:02.812437 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4140 22:54:02.815952 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4141 22:54:02.822362 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4142 22:54:02.825644 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4143 22:54:02.829215 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4144 22:54:02.832132 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4145 22:54:02.838742 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4146 22:54:02.841907 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4147 22:54:02.842343 ==
4148 22:54:02.845255 Dram Type= 6, Freq= 0, CH_0, rank 0
4149 22:54:02.848564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4150 22:54:02.848985 ==
4151 22:54:02.851966 DQS Delay:
4152 22:54:02.852384 DQS0 = 0, DQS1 = 0
4153 22:54:02.855700 DQM Delay:
4154 22:54:02.856220 DQM0 = 40, DQM1 = 29
4155 22:54:02.856549 DQ Delay:
4156 22:54:02.858704 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4157 22:54:02.862246 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4158 22:54:02.865088 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4159 22:54:02.868340 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4160 22:54:02.868762
4161 22:54:02.869088
4162 22:54:02.869424 ==
4163 22:54:02.872036 Dram Type= 6, Freq= 0, CH_0, rank 0
4164 22:54:02.878395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4165 22:54:02.878816 ==
4166 22:54:02.879147
4167 22:54:02.879618
4168 22:54:02.881580 TX Vref Scan disable
4169 22:54:02.882059 == TX Byte 0 ==
4170 22:54:02.885302 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4171 22:54:02.891743 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4172 22:54:02.892216 == TX Byte 1 ==
4173 22:54:02.898535 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4174 22:54:02.901317 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4175 22:54:02.901797 ==
4176 22:54:02.904957 Dram Type= 6, Freq= 0, CH_0, rank 0
4177 22:54:02.908045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4178 22:54:02.908524 ==
4179 22:54:02.908868
4180 22:54:02.909206
4181 22:54:02.911476 TX Vref Scan disable
4182 22:54:02.914618 == TX Byte 0 ==
4183 22:54:02.917981 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4184 22:54:02.920992 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4185 22:54:02.924689 == TX Byte 1 ==
4186 22:54:02.927886 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4187 22:54:02.931196 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4188 22:54:02.931616
4189 22:54:02.934603 [DATLAT]
4190 22:54:02.935102 Freq=600, CH0 RK0
4191 22:54:02.935543
4192 22:54:02.937591 DATLAT Default: 0x9
4193 22:54:02.938194 0, 0xFFFF, sum = 0
4194 22:54:02.941185 1, 0xFFFF, sum = 0
4195 22:54:02.941821 2, 0xFFFF, sum = 0
4196 22:54:02.944190 3, 0xFFFF, sum = 0
4197 22:54:02.944708 4, 0xFFFF, sum = 0
4198 22:54:02.947786 5, 0xFFFF, sum = 0
4199 22:54:02.948208 6, 0xFFFF, sum = 0
4200 22:54:02.950858 7, 0xFFFF, sum = 0
4201 22:54:02.951276 8, 0x0, sum = 1
4202 22:54:02.954488 9, 0x0, sum = 2
4203 22:54:02.954983 10, 0x0, sum = 3
4204 22:54:02.957848 11, 0x0, sum = 4
4205 22:54:02.958268 best_step = 9
4206 22:54:02.958594
4207 22:54:02.958897 ==
4208 22:54:02.960812 Dram Type= 6, Freq= 0, CH_0, rank 0
4209 22:54:02.967420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4210 22:54:02.967840 ==
4211 22:54:02.968167 RX Vref Scan: 1
4212 22:54:02.968472
4213 22:54:02.970819 RX Vref 0 -> 0, step: 1
4214 22:54:02.971266
4215 22:54:02.973900 RX Delay -195 -> 252, step: 8
4216 22:54:02.974343
4217 22:54:02.977366 Set Vref, RX VrefLevel [Byte0]: 56
4218 22:54:02.980663 [Byte1]: 50
4219 22:54:02.981096
4220 22:54:02.983816 Final RX Vref Byte 0 = 56 to rank0
4221 22:54:02.987301 Final RX Vref Byte 1 = 50 to rank0
4222 22:54:02.990583 Final RX Vref Byte 0 = 56 to rank1
4223 22:54:02.993888 Final RX Vref Byte 1 = 50 to rank1==
4224 22:54:02.997217 Dram Type= 6, Freq= 0, CH_0, rank 0
4225 22:54:03.000845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4226 22:54:03.001265 ==
4227 22:54:03.003846 DQS Delay:
4228 22:54:03.004280 DQS0 = 0, DQS1 = 0
4229 22:54:03.006908 DQM Delay:
4230 22:54:03.007335 DQM0 = 44, DQM1 = 32
4231 22:54:03.007762 DQ Delay:
4232 22:54:03.010069 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =44
4233 22:54:03.013279 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =52
4234 22:54:03.016749 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =24
4235 22:54:03.020807 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =40
4236 22:54:03.021401
4237 22:54:03.021768
4238 22:54:03.030034 [DQSOSCAuto] RK0, (LSB)MR18= 0x6a41, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 389 ps
4239 22:54:03.033508 CH0 RK0: MR19=808, MR18=6A41
4240 22:54:03.039987 CH0_RK0: MR19=0x808, MR18=0x6A41, DQSOSC=389, MR23=63, INC=173, DEC=115
4241 22:54:03.040402
4242 22:54:03.043200 ----->DramcWriteLeveling(PI) begin...
4243 22:54:03.043645 ==
4244 22:54:03.046852 Dram Type= 6, Freq= 0, CH_0, rank 1
4245 22:54:03.050061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4246 22:54:03.050480 ==
4247 22:54:03.053424 Write leveling (Byte 0): 35 => 35
4248 22:54:03.056533 Write leveling (Byte 1): 34 => 34
4249 22:54:03.059944 DramcWriteLeveling(PI) end<-----
4250 22:54:03.060358
4251 22:54:03.060684 ==
4252 22:54:03.063231 Dram Type= 6, Freq= 0, CH_0, rank 1
4253 22:54:03.066418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4254 22:54:03.066838 ==
4255 22:54:03.069832 [Gating] SW mode calibration
4256 22:54:03.076307 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4257 22:54:03.083203 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4258 22:54:03.086542 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4259 22:54:03.090033 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4260 22:54:03.096162 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4261 22:54:03.099689 0 9 12 | B1->B0 | 3232 3333 | 1 1 | (1 0) (1 0)
4262 22:54:03.103351 0 9 16 | B1->B0 | 2f2f 2a2a | 1 1 | (1 0) (0 0)
4263 22:54:03.109201 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4264 22:54:03.112921 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4265 22:54:03.115815 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4266 22:54:03.122393 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4267 22:54:03.125670 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4268 22:54:03.128897 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4269 22:54:03.135645 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4270 22:54:03.138846 0 10 16 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
4271 22:54:03.142354 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4272 22:54:03.148642 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4273 22:54:03.152295 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4274 22:54:03.155685 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4275 22:54:03.161861 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4276 22:54:03.164901 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4277 22:54:03.168181 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4278 22:54:03.174730 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4279 22:54:03.178751 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4280 22:54:03.181750 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4281 22:54:03.188062 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4282 22:54:03.191861 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4283 22:54:03.194630 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4284 22:54:03.201381 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4285 22:54:03.205226 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4286 22:54:03.207694 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4287 22:54:03.214846 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4288 22:54:03.218166 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4289 22:54:03.220871 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4290 22:54:03.227988 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4291 22:54:03.231406 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4292 22:54:03.234246 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4293 22:54:03.240880 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4294 22:54:03.244045 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4295 22:54:03.247186 Total UI for P1: 0, mck2ui 16
4296 22:54:03.250957 best dqsien dly found for B0: ( 0, 13, 12)
4297 22:54:03.254135 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4298 22:54:03.257433 Total UI for P1: 0, mck2ui 16
4299 22:54:03.260875 best dqsien dly found for B1: ( 0, 13, 14)
4300 22:54:03.267274 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4301 22:54:03.270189 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4302 22:54:03.270647
4303 22:54:03.273828 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4304 22:54:03.277381 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4305 22:54:03.280744 [Gating] SW calibration Done
4306 22:54:03.281288 ==
4307 22:54:03.283849 Dram Type= 6, Freq= 0, CH_0, rank 1
4308 22:54:03.286977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4309 22:54:03.287543 ==
4310 22:54:03.290141 RX Vref Scan: 0
4311 22:54:03.290680
4312 22:54:03.291071 RX Vref 0 -> 0, step: 1
4313 22:54:03.291404
4314 22:54:03.293492 RX Delay -230 -> 252, step: 16
4315 22:54:03.299772 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4316 22:54:03.303577 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4317 22:54:03.307027 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4318 22:54:03.310132 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4319 22:54:03.313293 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4320 22:54:03.319891 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4321 22:54:03.323436 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4322 22:54:03.326808 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4323 22:54:03.329795 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4324 22:54:03.336302 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4325 22:54:03.340203 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4326 22:54:03.343247 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4327 22:54:03.346121 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4328 22:54:03.353315 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4329 22:54:03.356360 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4330 22:54:03.359737 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4331 22:54:03.360287 ==
4332 22:54:03.363293 Dram Type= 6, Freq= 0, CH_0, rank 1
4333 22:54:03.366179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4334 22:54:03.366644 ==
4335 22:54:03.369447 DQS Delay:
4336 22:54:03.369998 DQS0 = 0, DQS1 = 0
4337 22:54:03.372754 DQM Delay:
4338 22:54:03.373208 DQM0 = 44, DQM1 = 40
4339 22:54:03.376077 DQ Delay:
4340 22:54:03.376529 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =33
4341 22:54:03.379466 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =57
4342 22:54:03.382529 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4343 22:54:03.386212 DQ12 =49, DQ13 =57, DQ14 =57, DQ15 =49
4344 22:54:03.386763
4345 22:54:03.388931
4346 22:54:03.389519 ==
4347 22:54:03.392749 Dram Type= 6, Freq= 0, CH_0, rank 1
4348 22:54:03.396056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4349 22:54:03.396608 ==
4350 22:54:03.396967
4351 22:54:03.397299
4352 22:54:03.399052 TX Vref Scan disable
4353 22:54:03.399505 == TX Byte 0 ==
4354 22:54:03.405988 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4355 22:54:03.409195 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4356 22:54:03.409790 == TX Byte 1 ==
4357 22:54:03.415440 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4358 22:54:03.419075 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4359 22:54:03.419597 ==
4360 22:54:03.422254 Dram Type= 6, Freq= 0, CH_0, rank 1
4361 22:54:03.425261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4362 22:54:03.425751 ==
4363 22:54:03.426112
4364 22:54:03.426445
4365 22:54:03.428494 TX Vref Scan disable
4366 22:54:03.432225 == TX Byte 0 ==
4367 22:54:03.435172 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4368 22:54:03.438784 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4369 22:54:03.441910 == TX Byte 1 ==
4370 22:54:03.445211 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4371 22:54:03.451670 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4372 22:54:03.452176
4373 22:54:03.452495 [DATLAT]
4374 22:54:03.452791 Freq=600, CH0 RK1
4375 22:54:03.453081
4376 22:54:03.455712 DATLAT Default: 0x9
4377 22:54:03.456226 0, 0xFFFF, sum = 0
4378 22:54:03.458733 1, 0xFFFF, sum = 0
4379 22:54:03.459150 2, 0xFFFF, sum = 0
4380 22:54:03.462073 3, 0xFFFF, sum = 0
4381 22:54:03.465483 4, 0xFFFF, sum = 0
4382 22:54:03.466002 5, 0xFFFF, sum = 0
4383 22:54:03.468849 6, 0xFFFF, sum = 0
4384 22:54:03.469267 7, 0xFFFF, sum = 0
4385 22:54:03.471937 8, 0x0, sum = 1
4386 22:54:03.472476 9, 0x0, sum = 2
4387 22:54:03.472812 10, 0x0, sum = 3
4388 22:54:03.475078 11, 0x0, sum = 4
4389 22:54:03.475496 best_step = 9
4390 22:54:03.475832
4391 22:54:03.476128 ==
4392 22:54:03.478262 Dram Type= 6, Freq= 0, CH_0, rank 1
4393 22:54:03.484681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4394 22:54:03.485133 ==
4395 22:54:03.485488 RX Vref Scan: 0
4396 22:54:03.485791
4397 22:54:03.488092 RX Vref 0 -> 0, step: 1
4398 22:54:03.488510
4399 22:54:03.491697 RX Delay -179 -> 252, step: 8
4400 22:54:03.494637 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4401 22:54:03.501292 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4402 22:54:03.504695 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4403 22:54:03.508598 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4404 22:54:03.511783 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4405 22:54:03.517813 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4406 22:54:03.521488 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4407 22:54:03.524734 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4408 22:54:03.528143 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4409 22:54:03.534332 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4410 22:54:03.537666 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4411 22:54:03.541023 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4412 22:54:03.544144 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4413 22:54:03.551324 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4414 22:54:03.553889 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4415 22:54:03.557463 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4416 22:54:03.558015 ==
4417 22:54:03.560927 Dram Type= 6, Freq= 0, CH_0, rank 1
4418 22:54:03.564188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4419 22:54:03.564739 ==
4420 22:54:03.567399 DQS Delay:
4421 22:54:03.567952 DQS0 = 0, DQS1 = 0
4422 22:54:03.570475 DQM Delay:
4423 22:54:03.570925 DQM0 = 41, DQM1 = 37
4424 22:54:03.574030 DQ Delay:
4425 22:54:03.574615 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4426 22:54:03.577025 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4427 22:54:03.580663 DQ8 =28, DQ9 =20, DQ10 =40, DQ11 =28
4428 22:54:03.583693 DQ12 =44, DQ13 =44, DQ14 =48, DQ15 =44
4429 22:54:03.584149
4430 22:54:03.587205
4431 22:54:03.593748 [DQSOSCAuto] RK1, (LSB)MR18= 0x6216, (MSB)MR19= 0x808, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
4432 22:54:03.596768 CH0 RK1: MR19=808, MR18=6216
4433 22:54:03.604022 CH0_RK1: MR19=0x808, MR18=0x6216, DQSOSC=391, MR23=63, INC=171, DEC=114
4434 22:54:03.606862 [RxdqsGatingPostProcess] freq 600
4435 22:54:03.610513 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4436 22:54:03.613842 Pre-setting of DQS Precalculation
4437 22:54:03.619811 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4438 22:54:03.620433 ==
4439 22:54:03.623364 Dram Type= 6, Freq= 0, CH_1, rank 0
4440 22:54:03.626588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4441 22:54:03.627049 ==
4442 22:54:03.632957 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4443 22:54:03.636393 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4444 22:54:03.640829 [CA 0] Center 36 (6~66) winsize 61
4445 22:54:03.643924 [CA 1] Center 35 (5~66) winsize 62
4446 22:54:03.647474 [CA 2] Center 34 (4~65) winsize 62
4447 22:54:03.650793 [CA 3] Center 33 (3~64) winsize 62
4448 22:54:03.654215 [CA 4] Center 34 (4~65) winsize 62
4449 22:54:03.657714 [CA 5] Center 33 (3~64) winsize 62
4450 22:54:03.658265
4451 22:54:03.660530 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4452 22:54:03.660992
4453 22:54:03.664163 [CATrainingPosCal] consider 1 rank data
4454 22:54:03.667412 u2DelayCellTimex100 = 270/100 ps
4455 22:54:03.670330 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4456 22:54:03.676735 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4457 22:54:03.680200 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4458 22:54:03.684129 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4459 22:54:03.687100 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4460 22:54:03.689948 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4461 22:54:03.690426
4462 22:54:03.693863 CA PerBit enable=1, Macro0, CA PI delay=33
4463 22:54:03.694409
4464 22:54:03.696891 [CBTSetCACLKResult] CA Dly = 33
4465 22:54:03.700244 CS Dly: 4 (0~35)
4466 22:54:03.700721 ==
4467 22:54:03.703221 Dram Type= 6, Freq= 0, CH_1, rank 1
4468 22:54:03.706870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4469 22:54:03.707456 ==
4470 22:54:03.713415 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4471 22:54:03.716767 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4472 22:54:03.721373 [CA 0] Center 35 (5~66) winsize 62
4473 22:54:03.724312 [CA 1] Center 36 (6~66) winsize 61
4474 22:54:03.727862 [CA 2] Center 34 (4~65) winsize 62
4475 22:54:03.730657 [CA 3] Center 34 (3~65) winsize 63
4476 22:54:03.734095 [CA 4] Center 34 (4~65) winsize 62
4477 22:54:03.737913 [CA 5] Center 34 (3~65) winsize 63
4478 22:54:03.738469
4479 22:54:03.740743 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4480 22:54:03.741292
4481 22:54:03.744147 [CATrainingPosCal] consider 2 rank data
4482 22:54:03.747597 u2DelayCellTimex100 = 270/100 ps
4483 22:54:03.750735 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4484 22:54:03.757506 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4485 22:54:03.760846 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4486 22:54:03.764323 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4487 22:54:03.767560 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4488 22:54:03.770504 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4489 22:54:03.770966
4490 22:54:03.773696 CA PerBit enable=1, Macro0, CA PI delay=33
4491 22:54:03.774157
4492 22:54:03.777412 [CBTSetCACLKResult] CA Dly = 33
4493 22:54:03.780801 CS Dly: 5 (0~38)
4494 22:54:03.781398
4495 22:54:03.783594 ----->DramcWriteLeveling(PI) begin...
4496 22:54:03.784057 ==
4497 22:54:03.787054 Dram Type= 6, Freq= 0, CH_1, rank 0
4498 22:54:03.789986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4499 22:54:03.790450 ==
4500 22:54:03.793874 Write leveling (Byte 0): 29 => 29
4501 22:54:03.796899 Write leveling (Byte 1): 29 => 29
4502 22:54:03.800531 DramcWriteLeveling(PI) end<-----
4503 22:54:03.801075
4504 22:54:03.801483 ==
4505 22:54:03.803319 Dram Type= 6, Freq= 0, CH_1, rank 0
4506 22:54:03.806770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4507 22:54:03.807326 ==
4508 22:54:03.810115 [Gating] SW mode calibration
4509 22:54:03.816641 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4510 22:54:03.823400 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4511 22:54:03.826189 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4512 22:54:03.829502 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4513 22:54:03.836813 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4514 22:54:03.839700 0 9 12 | B1->B0 | 3131 2f2f | 0 0 | (0 0) (0 1)
4515 22:54:03.843142 0 9 16 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
4516 22:54:03.849456 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4517 22:54:03.853072 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4518 22:54:03.855999 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4519 22:54:03.863013 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4520 22:54:03.866212 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4521 22:54:03.869449 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4522 22:54:03.876110 0 10 12 | B1->B0 | 3030 3939 | 0 0 | (0 0) (0 0)
4523 22:54:03.879500 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4524 22:54:03.882625 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4525 22:54:03.889468 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4526 22:54:03.892781 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4527 22:54:03.896017 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4528 22:54:03.902514 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4529 22:54:03.906060 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4530 22:54:03.909122 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4531 22:54:03.915340 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4532 22:54:03.918523 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4533 22:54:03.922099 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4534 22:54:03.928812 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4535 22:54:03.931976 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4536 22:54:03.934948 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4537 22:54:03.941928 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4538 22:54:03.945076 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4539 22:54:03.948837 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4540 22:54:03.955163 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4541 22:54:03.958442 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4542 22:54:03.961382 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4543 22:54:03.968106 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4544 22:54:03.971253 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4545 22:54:03.974653 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4546 22:54:03.981547 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4547 22:54:03.984768 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4548 22:54:03.988107 Total UI for P1: 0, mck2ui 16
4549 22:54:03.991101 best dqsien dly found for B0: ( 0, 13, 12)
4550 22:54:03.994691 Total UI for P1: 0, mck2ui 16
4551 22:54:03.997534 best dqsien dly found for B1: ( 0, 13, 12)
4552 22:54:04.001261 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4553 22:54:04.004456 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4554 22:54:04.004914
4555 22:54:04.007885 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4556 22:54:04.014337 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4557 22:54:04.014781 [Gating] SW calibration Done
4558 22:54:04.015261 ==
4559 22:54:04.017800 Dram Type= 6, Freq= 0, CH_1, rank 0
4560 22:54:04.024037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4561 22:54:04.024511 ==
4562 22:54:04.024919 RX Vref Scan: 0
4563 22:54:04.025383
4564 22:54:04.027678 RX Vref 0 -> 0, step: 1
4565 22:54:04.028095
4566 22:54:04.030472 RX Delay -230 -> 252, step: 16
4567 22:54:04.034080 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4568 22:54:04.036998 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4569 22:54:04.043803 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4570 22:54:04.047059 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4571 22:54:04.050365 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4572 22:54:04.054002 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4573 22:54:04.057169 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4574 22:54:04.063887 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4575 22:54:04.067432 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4576 22:54:04.070398 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4577 22:54:04.073308 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4578 22:54:04.079875 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4579 22:54:04.083812 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4580 22:54:04.086829 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4581 22:54:04.089910 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4582 22:54:04.096585 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4583 22:54:04.097160 ==
4584 22:54:04.100011 Dram Type= 6, Freq= 0, CH_1, rank 0
4585 22:54:04.103528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4586 22:54:04.103967 ==
4587 22:54:04.104308 DQS Delay:
4588 22:54:04.106376 DQS0 = 0, DQS1 = 0
4589 22:54:04.106795 DQM Delay:
4590 22:54:04.109924 DQM0 = 45, DQM1 = 37
4591 22:54:04.110549 DQ Delay:
4592 22:54:04.113032 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4593 22:54:04.116607 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4594 22:54:04.119947 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4595 22:54:04.123281 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4596 22:54:04.123700
4597 22:54:04.124025
4598 22:54:04.124472 ==
4599 22:54:04.126242 Dram Type= 6, Freq= 0, CH_1, rank 0
4600 22:54:04.132700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4601 22:54:04.133162 ==
4602 22:54:04.133544
4603 22:54:04.133850
4604 22:54:04.134150 TX Vref Scan disable
4605 22:54:04.136300 == TX Byte 0 ==
4606 22:54:04.139340 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4607 22:54:04.145880 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4608 22:54:04.146299 == TX Byte 1 ==
4609 22:54:04.148892 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4610 22:54:04.155655 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4611 22:54:04.156071 ==
4612 22:54:04.159220 Dram Type= 6, Freq= 0, CH_1, rank 0
4613 22:54:04.162187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4614 22:54:04.162788 ==
4615 22:54:04.163201
4616 22:54:04.163701
4617 22:54:04.165608 TX Vref Scan disable
4618 22:54:04.168940 == TX Byte 0 ==
4619 22:54:04.172428 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4620 22:54:04.175609 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4621 22:54:04.178492 == TX Byte 1 ==
4622 22:54:04.181803 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4623 22:54:04.185455 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4624 22:54:04.185872
4625 22:54:04.188940 [DATLAT]
4626 22:54:04.189390 Freq=600, CH1 RK0
4627 22:54:04.189730
4628 22:54:04.191795 DATLAT Default: 0x9
4629 22:54:04.192208 0, 0xFFFF, sum = 0
4630 22:54:04.195189 1, 0xFFFF, sum = 0
4631 22:54:04.195636 2, 0xFFFF, sum = 0
4632 22:54:04.198256 3, 0xFFFF, sum = 0
4633 22:54:04.198677 4, 0xFFFF, sum = 0
4634 22:54:04.201535 5, 0xFFFF, sum = 0
4635 22:54:04.201953 6, 0xFFFF, sum = 0
4636 22:54:04.205445 7, 0xFFFF, sum = 0
4637 22:54:04.205963 8, 0x0, sum = 1
4638 22:54:04.208451 9, 0x0, sum = 2
4639 22:54:04.208955 10, 0x0, sum = 3
4640 22:54:04.211473 11, 0x0, sum = 4
4641 22:54:04.212040 best_step = 9
4642 22:54:04.212374
4643 22:54:04.212681 ==
4644 22:54:04.214959 Dram Type= 6, Freq= 0, CH_1, rank 0
4645 22:54:04.218092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4646 22:54:04.221882 ==
4647 22:54:04.222300 RX Vref Scan: 1
4648 22:54:04.222627
4649 22:54:04.224529 RX Vref 0 -> 0, step: 1
4650 22:54:04.224947
4651 22:54:04.227783 RX Delay -195 -> 252, step: 8
4652 22:54:04.228202
4653 22:54:04.231585 Set Vref, RX VrefLevel [Byte0]: 50
4654 22:54:04.234462 [Byte1]: 52
4655 22:54:04.234882
4656 22:54:04.237685 Final RX Vref Byte 0 = 50 to rank0
4657 22:54:04.241553 Final RX Vref Byte 1 = 52 to rank0
4658 22:54:04.244369 Final RX Vref Byte 0 = 50 to rank1
4659 22:54:04.248062 Final RX Vref Byte 1 = 52 to rank1==
4660 22:54:04.251319 Dram Type= 6, Freq= 0, CH_1, rank 0
4661 22:54:04.254300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4662 22:54:04.254742 ==
4663 22:54:04.257642 DQS Delay:
4664 22:54:04.258058 DQS0 = 0, DQS1 = 0
4665 22:54:04.258384 DQM Delay:
4666 22:54:04.260813 DQM0 = 48, DQM1 = 36
4667 22:54:04.261320 DQ Delay:
4668 22:54:04.264540 DQ0 =56, DQ1 =44, DQ2 =40, DQ3 =44
4669 22:54:04.267622 DQ4 =44, DQ5 =56, DQ6 =56, DQ7 =44
4670 22:54:04.270766 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4671 22:54:04.274033 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =48
4672 22:54:04.274478
4673 22:54:04.274919
4674 22:54:04.284148 [DQSOSCAuto] RK0, (LSB)MR18= 0x4e33, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 395 ps
4675 22:54:04.287348 CH1 RK0: MR19=808, MR18=4E33
4676 22:54:04.293960 CH1_RK0: MR19=0x808, MR18=0x4E33, DQSOSC=395, MR23=63, INC=168, DEC=112
4677 22:54:04.294422
4678 22:54:04.297492 ----->DramcWriteLeveling(PI) begin...
4679 22:54:04.298054 ==
4680 22:54:04.300492 Dram Type= 6, Freq= 0, CH_1, rank 1
4681 22:54:04.303655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4682 22:54:04.304214 ==
4683 22:54:04.306932 Write leveling (Byte 0): 30 => 30
4684 22:54:04.310441 Write leveling (Byte 1): 30 => 30
4685 22:54:04.313781 DramcWriteLeveling(PI) end<-----
4686 22:54:04.314331
4687 22:54:04.314693 ==
4688 22:54:04.317034 Dram Type= 6, Freq= 0, CH_1, rank 1
4689 22:54:04.319803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4690 22:54:04.320274 ==
4691 22:54:04.323026 [Gating] SW mode calibration
4692 22:54:04.330096 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4693 22:54:04.336643 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4694 22:54:04.339711 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4695 22:54:04.343248 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4696 22:54:04.349699 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4697 22:54:04.353110 0 9 12 | B1->B0 | 2f2f 3333 | 0 1 | (0 1) (0 1)
4698 22:54:04.356651 0 9 16 | B1->B0 | 2424 2d2d | 0 1 | (0 0) (0 0)
4699 22:54:04.363154 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4700 22:54:04.366537 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4701 22:54:04.369749 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4702 22:54:04.375987 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4703 22:54:04.379680 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4704 22:54:04.382616 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4705 22:54:04.389322 0 10 12 | B1->B0 | 3232 2b2b | 0 0 | (0 0) (1 1)
4706 22:54:04.392943 0 10 16 | B1->B0 | 4646 4040 | 0 1 | (0 0) (0 0)
4707 22:54:04.395700 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4708 22:54:04.402261 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4709 22:54:04.405909 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4710 22:54:04.409255 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4711 22:54:04.415981 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4712 22:54:04.419196 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4713 22:54:04.422082 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4714 22:54:04.428942 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4715 22:54:04.432006 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4716 22:54:04.435165 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4717 22:54:04.441816 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4718 22:54:04.445141 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4719 22:54:04.449085 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4720 22:54:04.455394 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4721 22:54:04.458431 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4722 22:54:04.461958 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4723 22:54:04.468358 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4724 22:54:04.472079 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4725 22:54:04.475123 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4726 22:54:04.481671 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4727 22:54:04.484941 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4728 22:54:04.488303 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4729 22:54:04.494895 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4730 22:54:04.498103 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4731 22:54:04.501281 Total UI for P1: 0, mck2ui 16
4732 22:54:04.504668 best dqsien dly found for B0: ( 0, 13, 14)
4733 22:54:04.508426 Total UI for P1: 0, mck2ui 16
4734 22:54:04.511072 best dqsien dly found for B1: ( 0, 13, 12)
4735 22:54:04.514812 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4736 22:54:04.517939 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4737 22:54:04.518535
4738 22:54:04.520970 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4739 22:54:04.527607 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4740 22:54:04.528163 [Gating] SW calibration Done
4741 22:54:04.530979 ==
4742 22:54:04.531440 Dram Type= 6, Freq= 0, CH_1, rank 1
4743 22:54:04.537320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4744 22:54:04.537839 ==
4745 22:54:04.538201 RX Vref Scan: 0
4746 22:54:04.538543
4747 22:54:04.540366 RX Vref 0 -> 0, step: 1
4748 22:54:04.540826
4749 22:54:04.544051 RX Delay -230 -> 252, step: 16
4750 22:54:04.547208 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4751 22:54:04.550514 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4752 22:54:04.556923 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4753 22:54:04.560517 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4754 22:54:04.563715 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4755 22:54:04.567387 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4756 22:54:04.573768 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4757 22:54:04.576838 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4758 22:54:04.580087 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4759 22:54:04.583961 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4760 22:54:04.590207 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4761 22:54:04.593577 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4762 22:54:04.596688 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4763 22:54:04.599563 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4764 22:54:04.606667 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4765 22:54:04.609579 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4766 22:54:04.610135 ==
4767 22:54:04.613037 Dram Type= 6, Freq= 0, CH_1, rank 1
4768 22:54:04.616282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4769 22:54:04.616744 ==
4770 22:54:04.619806 DQS Delay:
4771 22:54:04.620356 DQS0 = 0, DQS1 = 0
4772 22:54:04.620719 DQM Delay:
4773 22:54:04.622688 DQM0 = 43, DQM1 = 39
4774 22:54:04.623147 DQ Delay:
4775 22:54:04.626328 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4776 22:54:04.629488 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4777 22:54:04.633030 DQ8 =17, DQ9 =33, DQ10 =41, DQ11 =33
4778 22:54:04.636352 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4779 22:54:04.636809
4780 22:54:04.637164
4781 22:54:04.637560 ==
4782 22:54:04.639628 Dram Type= 6, Freq= 0, CH_1, rank 1
4783 22:54:04.646416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4784 22:54:04.646888 ==
4785 22:54:04.647447
4786 22:54:04.647846
4787 22:54:04.648396 TX Vref Scan disable
4788 22:54:04.649583 == TX Byte 0 ==
4789 22:54:04.652622 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4790 22:54:04.659899 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4791 22:54:04.660451 == TX Byte 1 ==
4792 22:54:04.662663 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4793 22:54:04.669503 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4794 22:54:04.669967 ==
4795 22:54:04.672899 Dram Type= 6, Freq= 0, CH_1, rank 1
4796 22:54:04.675868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4797 22:54:04.676335 ==
4798 22:54:04.676695
4799 22:54:04.677025
4800 22:54:04.679097 TX Vref Scan disable
4801 22:54:04.682641 == TX Byte 0 ==
4802 22:54:04.685640 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4803 22:54:04.688983 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4804 22:54:04.692521 == TX Byte 1 ==
4805 22:54:04.695705 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4806 22:54:04.698920 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4807 22:54:04.699383
4808 22:54:04.701822 [DATLAT]
4809 22:54:04.702294 Freq=600, CH1 RK1
4810 22:54:04.702658
4811 22:54:04.705320 DATLAT Default: 0x9
4812 22:54:04.705856 0, 0xFFFF, sum = 0
4813 22:54:04.709117 1, 0xFFFF, sum = 0
4814 22:54:04.709768 2, 0xFFFF, sum = 0
4815 22:54:04.712196 3, 0xFFFF, sum = 0
4816 22:54:04.712759 4, 0xFFFF, sum = 0
4817 22:54:04.714898 5, 0xFFFF, sum = 0
4818 22:54:04.715370 6, 0xFFFF, sum = 0
4819 22:54:04.718278 7, 0xFFFF, sum = 0
4820 22:54:04.718807 8, 0x0, sum = 1
4821 22:54:04.722079 9, 0x0, sum = 2
4822 22:54:04.722601 10, 0x0, sum = 3
4823 22:54:04.725454 11, 0x0, sum = 4
4824 22:54:04.725924 best_step = 9
4825 22:54:04.726286
4826 22:54:04.726622 ==
4827 22:54:04.728813 Dram Type= 6, Freq= 0, CH_1, rank 1
4828 22:54:04.731519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4829 22:54:04.735043 ==
4830 22:54:04.735506 RX Vref Scan: 0
4831 22:54:04.735873
4832 22:54:04.738141 RX Vref 0 -> 0, step: 1
4833 22:54:04.738604
4834 22:54:04.741957 RX Delay -195 -> 252, step: 8
4835 22:54:04.744686 iDelay=213, Bit 0, Center 48 (-99 ~ 196) 296
4836 22:54:04.751674 iDelay=213, Bit 1, Center 40 (-107 ~ 188) 296
4837 22:54:04.754571 iDelay=213, Bit 2, Center 32 (-115 ~ 180) 296
4838 22:54:04.757858 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4839 22:54:04.760872 iDelay=213, Bit 4, Center 44 (-107 ~ 196) 304
4840 22:54:04.764497 iDelay=213, Bit 5, Center 56 (-91 ~ 204) 296
4841 22:54:04.771025 iDelay=213, Bit 6, Center 60 (-91 ~ 212) 304
4842 22:54:04.774117 iDelay=213, Bit 7, Center 44 (-107 ~ 196) 304
4843 22:54:04.777864 iDelay=213, Bit 8, Center 24 (-131 ~ 180) 312
4844 22:54:04.780793 iDelay=213, Bit 9, Center 24 (-131 ~ 180) 312
4845 22:54:04.787654 iDelay=213, Bit 10, Center 36 (-115 ~ 188) 304
4846 22:54:04.790682 iDelay=213, Bit 11, Center 28 (-123 ~ 180) 304
4847 22:54:04.794287 iDelay=213, Bit 12, Center 48 (-107 ~ 204) 312
4848 22:54:04.797539 iDelay=213, Bit 13, Center 44 (-107 ~ 196) 304
4849 22:54:04.804276 iDelay=213, Bit 14, Center 44 (-107 ~ 196) 304
4850 22:54:04.807580 iDelay=213, Bit 15, Center 48 (-107 ~ 204) 312
4851 22:54:04.808112 ==
4852 22:54:04.810273 Dram Type= 6, Freq= 0, CH_1, rank 1
4853 22:54:04.813851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4854 22:54:04.814273 ==
4855 22:54:04.817440 DQS Delay:
4856 22:54:04.817948 DQS0 = 0, DQS1 = 0
4857 22:54:04.818277 DQM Delay:
4858 22:54:04.820569 DQM0 = 45, DQM1 = 37
4859 22:54:04.820984 DQ Delay:
4860 22:54:04.824683 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4861 22:54:04.827444 DQ4 =44, DQ5 =56, DQ6 =60, DQ7 =44
4862 22:54:04.830838 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =28
4863 22:54:04.833814 DQ12 =48, DQ13 =44, DQ14 =44, DQ15 =48
4864 22:54:04.834359
4865 22:54:04.834799
4866 22:54:04.843860 [DQSOSCAuto] RK1, (LSB)MR18= 0x2c21, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 401 ps
4867 22:54:04.847142 CH1 RK1: MR19=808, MR18=2C21
4868 22:54:04.850459 CH1_RK1: MR19=0x808, MR18=0x2C21, DQSOSC=401, MR23=63, INC=163, DEC=108
4869 22:54:04.853499 [RxdqsGatingPostProcess] freq 600
4870 22:54:04.859997 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4871 22:54:04.863533 Pre-setting of DQS Precalculation
4872 22:54:04.866864 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4873 22:54:04.876913 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4874 22:54:04.883570 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4875 22:54:04.884393
4876 22:54:04.884849
4877 22:54:04.886244 [Calibration Summary] 1200 Mbps
4878 22:54:04.886709 CH 0, Rank 0
4879 22:54:04.889847 SW Impedance : PASS
4880 22:54:04.890312 DUTY Scan : NO K
4881 22:54:04.893036 ZQ Calibration : PASS
4882 22:54:04.896340 Jitter Meter : NO K
4883 22:54:04.896937 CBT Training : PASS
4884 22:54:04.899440 Write leveling : PASS
4885 22:54:04.903148 RX DQS gating : PASS
4886 22:54:04.903608 RX DQ/DQS(RDDQC) : PASS
4887 22:54:04.906275 TX DQ/DQS : PASS
4888 22:54:04.909576 RX DATLAT : PASS
4889 22:54:04.910142 RX DQ/DQS(Engine): PASS
4890 22:54:04.913210 TX OE : NO K
4891 22:54:04.913813 All Pass.
4892 22:54:04.914180
4893 22:54:04.915927 CH 0, Rank 1
4894 22:54:04.916386 SW Impedance : PASS
4895 22:54:04.919715 DUTY Scan : NO K
4896 22:54:04.922637 ZQ Calibration : PASS
4897 22:54:04.923137 Jitter Meter : NO K
4898 22:54:04.926192 CBT Training : PASS
4899 22:54:04.929511 Write leveling : PASS
4900 22:54:04.929971 RX DQS gating : PASS
4901 22:54:04.932579 RX DQ/DQS(RDDQC) : PASS
4902 22:54:04.936025 TX DQ/DQS : PASS
4903 22:54:04.936490 RX DATLAT : PASS
4904 22:54:04.939437 RX DQ/DQS(Engine): PASS
4905 22:54:04.939981 TX OE : NO K
4906 22:54:04.942168 All Pass.
4907 22:54:04.942622
4908 22:54:04.942981 CH 1, Rank 0
4909 22:54:04.945988 SW Impedance : PASS
4910 22:54:04.946447 DUTY Scan : NO K
4911 22:54:04.948964 ZQ Calibration : PASS
4912 22:54:04.952413 Jitter Meter : NO K
4913 22:54:04.952969 CBT Training : PASS
4914 22:54:04.956264 Write leveling : PASS
4915 22:54:04.959391 RX DQS gating : PASS
4916 22:54:04.959939 RX DQ/DQS(RDDQC) : PASS
4917 22:54:04.962494 TX DQ/DQS : PASS
4918 22:54:04.965746 RX DATLAT : PASS
4919 22:54:04.966297 RX DQ/DQS(Engine): PASS
4920 22:54:04.969163 TX OE : NO K
4921 22:54:04.969769 All Pass.
4922 22:54:04.970139
4923 22:54:04.972258 CH 1, Rank 1
4924 22:54:04.972809 SW Impedance : PASS
4925 22:54:04.975994 DUTY Scan : NO K
4926 22:54:04.978719 ZQ Calibration : PASS
4927 22:54:04.979185 Jitter Meter : NO K
4928 22:54:04.982179 CBT Training : PASS
4929 22:54:04.985267 Write leveling : PASS
4930 22:54:04.985758 RX DQS gating : PASS
4931 22:54:04.988851 RX DQ/DQS(RDDQC) : PASS
4932 22:54:04.992284 TX DQ/DQS : PASS
4933 22:54:04.993036 RX DATLAT : PASS
4934 22:54:04.995211 RX DQ/DQS(Engine): PASS
4935 22:54:04.998669 TX OE : NO K
4936 22:54:04.999223 All Pass.
4937 22:54:04.999584
4938 22:54:04.999917 DramC Write-DBI off
4939 22:54:05.001734 PER_BANK_REFRESH: Hybrid Mode
4940 22:54:05.005071 TX_TRACKING: ON
4941 22:54:05.011963 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4942 22:54:05.015556 [FAST_K] Save calibration result to emmc
4943 22:54:05.021656 dramc_set_vcore_voltage set vcore to 662500
4944 22:54:05.022116 Read voltage for 933, 3
4945 22:54:05.024995 Vio18 = 0
4946 22:54:05.025591 Vcore = 662500
4947 22:54:05.025960 Vdram = 0
4948 22:54:05.028718 Vddq = 0
4949 22:54:05.029271 Vmddr = 0
4950 22:54:05.031651 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4951 22:54:05.038115 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4952 22:54:05.041431 MEM_TYPE=3, freq_sel=17
4953 22:54:05.044720 sv_algorithm_assistance_LP4_1600
4954 22:54:05.048162 ============ PULL DRAM RESETB DOWN ============
4955 22:54:05.051332 ========== PULL DRAM RESETB DOWN end =========
4956 22:54:05.054918 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4957 22:54:05.058012 ===================================
4958 22:54:05.061368 LPDDR4 DRAM CONFIGURATION
4959 22:54:05.064670 ===================================
4960 22:54:05.067698 EX_ROW_EN[0] = 0x0
4961 22:54:05.068254 EX_ROW_EN[1] = 0x0
4962 22:54:05.071366 LP4Y_EN = 0x0
4963 22:54:05.071824 WORK_FSP = 0x0
4964 22:54:05.074402 WL = 0x3
4965 22:54:05.074861 RL = 0x3
4966 22:54:05.078152 BL = 0x2
4967 22:54:05.081317 RPST = 0x0
4968 22:54:05.082139 RD_PRE = 0x0
4969 22:54:05.084439 WR_PRE = 0x1
4970 22:54:05.084992 WR_PST = 0x0
4971 22:54:05.087788 DBI_WR = 0x0
4972 22:54:05.088423 DBI_RD = 0x0
4973 22:54:05.091304 OTF = 0x1
4974 22:54:05.094739 ===================================
4975 22:54:05.098116 ===================================
4976 22:54:05.098670 ANA top config
4977 22:54:05.101150 ===================================
4978 22:54:05.104075 DLL_ASYNC_EN = 0
4979 22:54:05.107524 ALL_SLAVE_EN = 1
4980 22:54:05.107985 NEW_RANK_MODE = 1
4981 22:54:05.110850 DLL_IDLE_MODE = 1
4982 22:54:05.114003 LP45_APHY_COMB_EN = 1
4983 22:54:05.117398 TX_ODT_DIS = 1
4984 22:54:05.121177 NEW_8X_MODE = 1
4985 22:54:05.123790 ===================================
4986 22:54:05.124290 ===================================
4987 22:54:05.127063 data_rate = 1866
4988 22:54:05.130534 CKR = 1
4989 22:54:05.134014 DQ_P2S_RATIO = 8
4990 22:54:05.137452 ===================================
4991 22:54:05.140901 CA_P2S_RATIO = 8
4992 22:54:05.143690 DQ_CA_OPEN = 0
4993 22:54:05.147265 DQ_SEMI_OPEN = 0
4994 22:54:05.147796 CA_SEMI_OPEN = 0
4995 22:54:05.150741 CA_FULL_RATE = 0
4996 22:54:05.153712 DQ_CKDIV4_EN = 1
4997 22:54:05.156754 CA_CKDIV4_EN = 1
4998 22:54:05.160374 CA_PREDIV_EN = 0
4999 22:54:05.163593 PH8_DLY = 0
5000 22:54:05.164014 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
5001 22:54:05.166976 DQ_AAMCK_DIV = 4
5002 22:54:05.170508 CA_AAMCK_DIV = 4
5003 22:54:05.173410 CA_ADMCK_DIV = 4
5004 22:54:05.176894 DQ_TRACK_CA_EN = 0
5005 22:54:05.180125 CA_PICK = 933
5006 22:54:05.183024 CA_MCKIO = 933
5007 22:54:05.183442 MCKIO_SEMI = 0
5008 22:54:05.186881 PLL_FREQ = 3732
5009 22:54:05.189854 DQ_UI_PI_RATIO = 32
5010 22:54:05.193432 CA_UI_PI_RATIO = 0
5011 22:54:05.196859 ===================================
5012 22:54:05.199748 ===================================
5013 22:54:05.202723 memory_type:LPDDR4
5014 22:54:05.203175 GP_NUM : 10
5015 22:54:05.206434 SRAM_EN : 1
5016 22:54:05.209626 MD32_EN : 0
5017 22:54:05.212892 ===================================
5018 22:54:05.213510 [ANA_INIT] >>>>>>>>>>>>>>
5019 22:54:05.216063 <<<<<< [CONFIGURE PHASE]: ANA_TX
5020 22:54:05.219207 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5021 22:54:05.222652 ===================================
5022 22:54:05.226054 data_rate = 1866,PCW = 0X8f00
5023 22:54:05.229361 ===================================
5024 22:54:05.232823 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5025 22:54:05.239083 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5026 22:54:05.245613 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5027 22:54:05.249020 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5028 22:54:05.252103 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5029 22:54:05.255556 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5030 22:54:05.258686 [ANA_INIT] flow start
5031 22:54:05.259100 [ANA_INIT] PLL >>>>>>>>
5032 22:54:05.261933 [ANA_INIT] PLL <<<<<<<<
5033 22:54:05.265516 [ANA_INIT] MIDPI >>>>>>>>
5034 22:54:05.266209 [ANA_INIT] MIDPI <<<<<<<<
5035 22:54:05.269031 [ANA_INIT] DLL >>>>>>>>
5036 22:54:05.272045 [ANA_INIT] flow end
5037 22:54:05.275391 ============ LP4 DIFF to SE enter ============
5038 22:54:05.278655 ============ LP4 DIFF to SE exit ============
5039 22:54:05.282090 [ANA_INIT] <<<<<<<<<<<<<
5040 22:54:05.285105 [Flow] Enable top DCM control >>>>>
5041 22:54:05.288333 [Flow] Enable top DCM control <<<<<
5042 22:54:05.291670 Enable DLL master slave shuffle
5043 22:54:05.294925 ==============================================================
5044 22:54:05.298375 Gating Mode config
5045 22:54:05.305168 ==============================================================
5046 22:54:05.305632 Config description:
5047 22:54:05.315280 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5048 22:54:05.321662 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5049 22:54:05.328498 SELPH_MODE 0: By rank 1: By Phase
5050 22:54:05.331110 ==============================================================
5051 22:54:05.334530 GAT_TRACK_EN = 1
5052 22:54:05.337932 RX_GATING_MODE = 2
5053 22:54:05.341375 RX_GATING_TRACK_MODE = 2
5054 22:54:05.344390 SELPH_MODE = 1
5055 22:54:05.347598 PICG_EARLY_EN = 1
5056 22:54:05.351039 VALID_LAT_VALUE = 1
5057 22:54:05.357405 ==============================================================
5058 22:54:05.361058 Enter into Gating configuration >>>>
5059 22:54:05.364365 Exit from Gating configuration <<<<
5060 22:54:05.367907 Enter into DVFS_PRE_config >>>>>
5061 22:54:05.377584 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5062 22:54:05.380386 Exit from DVFS_PRE_config <<<<<
5063 22:54:05.383654 Enter into PICG configuration >>>>
5064 22:54:05.387650 Exit from PICG configuration <<<<
5065 22:54:05.390598 [RX_INPUT] configuration >>>>>
5066 22:54:05.391205 [RX_INPUT] configuration <<<<<
5067 22:54:05.397774 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5068 22:54:05.403621 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5069 22:54:05.407139 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5070 22:54:05.413658 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5071 22:54:05.420187 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5072 22:54:05.426991 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5073 22:54:05.430421 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5074 22:54:05.433576 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5075 22:54:05.439924 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5076 22:54:05.443079 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5077 22:54:05.446623 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5078 22:54:05.452963 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5079 22:54:05.456369 ===================================
5080 22:54:05.456924 LPDDR4 DRAM CONFIGURATION
5081 22:54:05.460097 ===================================
5082 22:54:05.462991 EX_ROW_EN[0] = 0x0
5083 22:54:05.466869 EX_ROW_EN[1] = 0x0
5084 22:54:05.467432 LP4Y_EN = 0x0
5085 22:54:05.469774 WORK_FSP = 0x0
5086 22:54:05.470231 WL = 0x3
5087 22:54:05.473002 RL = 0x3
5088 22:54:05.473588 BL = 0x2
5089 22:54:05.476330 RPST = 0x0
5090 22:54:05.476889 RD_PRE = 0x0
5091 22:54:05.479829 WR_PRE = 0x1
5092 22:54:05.480287 WR_PST = 0x0
5093 22:54:05.482651 DBI_WR = 0x0
5094 22:54:05.483108 DBI_RD = 0x0
5095 22:54:05.486274 OTF = 0x1
5096 22:54:05.489271 ===================================
5097 22:54:05.493026 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5098 22:54:05.495808 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5099 22:54:05.502475 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5100 22:54:05.505893 ===================================
5101 22:54:05.506349 LPDDR4 DRAM CONFIGURATION
5102 22:54:05.509006 ===================================
5103 22:54:05.512469 EX_ROW_EN[0] = 0x10
5104 22:54:05.516048 EX_ROW_EN[1] = 0x0
5105 22:54:05.516503 LP4Y_EN = 0x0
5106 22:54:05.519275 WORK_FSP = 0x0
5107 22:54:05.519733 WL = 0x3
5108 22:54:05.522577 RL = 0x3
5109 22:54:05.523036 BL = 0x2
5110 22:54:05.525606 RPST = 0x0
5111 22:54:05.526061 RD_PRE = 0x0
5112 22:54:05.529145 WR_PRE = 0x1
5113 22:54:05.529645 WR_PST = 0x0
5114 22:54:05.532298 DBI_WR = 0x0
5115 22:54:05.532799 DBI_RD = 0x0
5116 22:54:05.535471 OTF = 0x1
5117 22:54:05.539055 ===================================
5118 22:54:05.545312 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5119 22:54:05.548450 nWR fixed to 30
5120 22:54:05.552109 [ModeRegInit_LP4] CH0 RK0
5121 22:54:05.552519 [ModeRegInit_LP4] CH0 RK1
5122 22:54:05.555288 [ModeRegInit_LP4] CH1 RK0
5123 22:54:05.558252 [ModeRegInit_LP4] CH1 RK1
5124 22:54:05.558693 match AC timing 9
5125 22:54:05.565173 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5126 22:54:05.568046 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5127 22:54:05.571491 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5128 22:54:05.578015 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5129 22:54:05.581218 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5130 22:54:05.581393 ==
5131 22:54:05.584754 Dram Type= 6, Freq= 0, CH_0, rank 0
5132 22:54:05.587899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5133 22:54:05.588015 ==
5134 22:54:05.594110 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5135 22:54:05.600939 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5136 22:54:05.604434 [CA 0] Center 37 (7~68) winsize 62
5137 22:54:05.607774 [CA 1] Center 37 (7~68) winsize 62
5138 22:54:05.610993 [CA 2] Center 34 (4~65) winsize 62
5139 22:54:05.614390 [CA 3] Center 35 (5~65) winsize 61
5140 22:54:05.617683 [CA 4] Center 34 (4~64) winsize 61
5141 22:54:05.620896 [CA 5] Center 33 (4~63) winsize 60
5142 22:54:05.621309
5143 22:54:05.623844 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5144 22:54:05.624125
5145 22:54:05.627149 [CATrainingPosCal] consider 1 rank data
5146 22:54:05.630964 u2DelayCellTimex100 = 270/100 ps
5147 22:54:05.633995 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5148 22:54:05.637184 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5149 22:54:05.640350 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5150 22:54:05.647363 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5151 22:54:05.650297 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5152 22:54:05.653475 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5153 22:54:05.653794
5154 22:54:05.657407 CA PerBit enable=1, Macro0, CA PI delay=33
5155 22:54:05.657834
5156 22:54:05.660225 [CBTSetCACLKResult] CA Dly = 33
5157 22:54:05.660542 CS Dly: 7 (0~38)
5158 22:54:05.660790 ==
5159 22:54:05.663824 Dram Type= 6, Freq= 0, CH_0, rank 1
5160 22:54:05.670488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5161 22:54:05.670819 ==
5162 22:54:05.673550 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5163 22:54:05.679990 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5164 22:54:05.683929 [CA 0] Center 37 (7~68) winsize 62
5165 22:54:05.686794 [CA 1] Center 37 (7~68) winsize 62
5166 22:54:05.690010 [CA 2] Center 34 (4~65) winsize 62
5167 22:54:05.693710 [CA 3] Center 35 (5~65) winsize 61
5168 22:54:05.696954 [CA 4] Center 33 (3~64) winsize 62
5169 22:54:05.700571 [CA 5] Center 33 (3~63) winsize 61
5170 22:54:05.701125
5171 22:54:05.703229 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5172 22:54:05.703705
5173 22:54:05.706707 [CATrainingPosCal] consider 2 rank data
5174 22:54:05.710253 u2DelayCellTimex100 = 270/100 ps
5175 22:54:05.713699 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5176 22:54:05.719861 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5177 22:54:05.723182 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5178 22:54:05.726564 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5179 22:54:05.729513 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5180 22:54:05.733475 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5181 22:54:05.734035
5182 22:54:05.736564 CA PerBit enable=1, Macro0, CA PI delay=33
5183 22:54:05.737024
5184 22:54:05.739354 [CBTSetCACLKResult] CA Dly = 33
5185 22:54:05.742694 CS Dly: 7 (0~39)
5186 22:54:05.743157
5187 22:54:05.746255 ----->DramcWriteLeveling(PI) begin...
5188 22:54:05.746722 ==
5189 22:54:05.749460 Dram Type= 6, Freq= 0, CH_0, rank 0
5190 22:54:05.753039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5191 22:54:05.753675 ==
5192 22:54:05.756368 Write leveling (Byte 0): 33 => 33
5193 22:54:05.759915 Write leveling (Byte 1): 31 => 31
5194 22:54:05.763051 DramcWriteLeveling(PI) end<-----
5195 22:54:05.763611
5196 22:54:05.763971 ==
5197 22:54:05.766008 Dram Type= 6, Freq= 0, CH_0, rank 0
5198 22:54:05.769464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5199 22:54:05.770091 ==
5200 22:54:05.772654 [Gating] SW mode calibration
5201 22:54:05.779280 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5202 22:54:05.785855 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5203 22:54:05.789414 0 14 0 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
5204 22:54:05.792669 0 14 4 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
5205 22:54:05.798754 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5206 22:54:05.802341 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5207 22:54:05.805373 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5208 22:54:05.812489 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5209 22:54:05.815242 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5210 22:54:05.818884 0 14 28 | B1->B0 | 3434 2b2b | 1 1 | (1 1) (1 0)
5211 22:54:05.825675 0 15 0 | B1->B0 | 3131 2323 | 0 0 | (0 1) (0 0)
5212 22:54:05.828616 0 15 4 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
5213 22:54:05.831788 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5214 22:54:05.838797 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5215 22:54:05.842154 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5216 22:54:05.845077 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5217 22:54:05.851924 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5218 22:54:05.855424 0 15 28 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
5219 22:54:05.858298 1 0 0 | B1->B0 | 2f2f 3e3e | 0 0 | (0 0) (0 0)
5220 22:54:05.865091 1 0 4 | B1->B0 | 4444 4646 | 1 0 | (0 0) (0 0)
5221 22:54:05.868626 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5222 22:54:05.872123 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5223 22:54:05.878033 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5224 22:54:05.881390 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5225 22:54:05.884993 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5226 22:54:05.891036 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5227 22:54:05.894413 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5228 22:54:05.901152 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5229 22:54:05.904308 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5230 22:54:05.907850 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5231 22:54:05.914260 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5232 22:54:05.918027 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5233 22:54:05.920918 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5234 22:54:05.927576 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5235 22:54:05.930693 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5236 22:54:05.933846 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5237 22:54:05.940498 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5238 22:54:05.944106 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5239 22:54:05.947038 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5240 22:54:05.953683 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5241 22:54:05.957498 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5242 22:54:05.960777 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5243 22:54:05.967035 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5244 22:54:05.967600 Total UI for P1: 0, mck2ui 16
5245 22:54:05.973598 best dqsien dly found for B0: ( 1, 2, 30)
5246 22:54:05.976826 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5247 22:54:05.980086 Total UI for P1: 0, mck2ui 16
5248 22:54:05.983954 best dqsien dly found for B1: ( 1, 3, 0)
5249 22:54:05.986643 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5250 22:54:05.990558 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5251 22:54:05.991106
5252 22:54:05.993499 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5253 22:54:05.996614 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5254 22:54:06.000161 [Gating] SW calibration Done
5255 22:54:06.000717 ==
5256 22:54:06.003691 Dram Type= 6, Freq= 0, CH_0, rank 0
5257 22:54:06.006554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5258 22:54:06.007016 ==
5259 22:54:06.010277 RX Vref Scan: 0
5260 22:54:06.010830
5261 22:54:06.013024 RX Vref 0 -> 0, step: 1
5262 22:54:06.013507
5263 22:54:06.013866 RX Delay -80 -> 252, step: 8
5264 22:54:06.019779 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5265 22:54:06.023354 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5266 22:54:06.026200 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5267 22:54:06.029559 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5268 22:54:06.032756 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5269 22:54:06.039527 iDelay=208, Bit 5, Center 87 (-16 ~ 191) 208
5270 22:54:06.042501 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5271 22:54:06.045865 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5272 22:54:06.049235 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5273 22:54:06.052970 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5274 22:54:06.059164 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5275 22:54:06.062053 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5276 22:54:06.065900 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5277 22:54:06.068988 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5278 22:54:06.071907 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5279 22:54:06.078849 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5280 22:54:06.079400 ==
5281 22:54:06.082044 Dram Type= 6, Freq= 0, CH_0, rank 0
5282 22:54:06.085094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5283 22:54:06.085588 ==
5284 22:54:06.085986 DQS Delay:
5285 22:54:06.088391 DQS0 = 0, DQS1 = 0
5286 22:54:06.088844 DQM Delay:
5287 22:54:06.092145 DQM0 = 97, DQM1 = 85
5288 22:54:06.092693 DQ Delay:
5289 22:54:06.094958 DQ0 =99, DQ1 =99, DQ2 =91, DQ3 =91
5290 22:54:06.098581 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5291 22:54:06.101442 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5292 22:54:06.105142 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5293 22:54:06.105755
5294 22:54:06.106134
5295 22:54:06.106464 ==
5296 22:54:06.108393 Dram Type= 6, Freq= 0, CH_0, rank 0
5297 22:54:06.111463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5298 22:54:06.115083 ==
5299 22:54:06.115632
5300 22:54:06.115991
5301 22:54:06.116322 TX Vref Scan disable
5302 22:54:06.117837 == TX Byte 0 ==
5303 22:54:06.121394 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5304 22:54:06.124507 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5305 22:54:06.128183 == TX Byte 1 ==
5306 22:54:06.131170 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5307 22:54:06.137817 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5308 22:54:06.138272 ==
5309 22:54:06.141197 Dram Type= 6, Freq= 0, CH_0, rank 0
5310 22:54:06.144677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5311 22:54:06.145135 ==
5312 22:54:06.145545
5313 22:54:06.145902
5314 22:54:06.147581 TX Vref Scan disable
5315 22:54:06.147993 == TX Byte 0 ==
5316 22:54:06.154197 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5317 22:54:06.157387 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5318 22:54:06.160837 == TX Byte 1 ==
5319 22:54:06.164046 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5320 22:54:06.167180 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5321 22:54:06.167595
5322 22:54:06.167963 [DATLAT]
5323 22:54:06.170908 Freq=933, CH0 RK0
5324 22:54:06.171419
5325 22:54:06.173693 DATLAT Default: 0xd
5326 22:54:06.174108 0, 0xFFFF, sum = 0
5327 22:54:06.177485 1, 0xFFFF, sum = 0
5328 22:54:06.178005 2, 0xFFFF, sum = 0
5329 22:54:06.180405 3, 0xFFFF, sum = 0
5330 22:54:06.180825 4, 0xFFFF, sum = 0
5331 22:54:06.183640 5, 0xFFFF, sum = 0
5332 22:54:06.184057 6, 0xFFFF, sum = 0
5333 22:54:06.186778 7, 0xFFFF, sum = 0
5334 22:54:06.187209 8, 0xFFFF, sum = 0
5335 22:54:06.190172 9, 0xFFFF, sum = 0
5336 22:54:06.190696 10, 0x0, sum = 1
5337 22:54:06.193425 11, 0x0, sum = 2
5338 22:54:06.193844 12, 0x0, sum = 3
5339 22:54:06.197307 13, 0x0, sum = 4
5340 22:54:06.197873 best_step = 11
5341 22:54:06.198198
5342 22:54:06.198499 ==
5343 22:54:06.200275 Dram Type= 6, Freq= 0, CH_0, rank 0
5344 22:54:06.203710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5345 22:54:06.206701 ==
5346 22:54:06.207115 RX Vref Scan: 1
5347 22:54:06.207438
5348 22:54:06.209855 RX Vref 0 -> 0, step: 1
5349 22:54:06.210268
5350 22:54:06.213594 RX Delay -69 -> 252, step: 4
5351 22:54:06.214148
5352 22:54:06.216350 Set Vref, RX VrefLevel [Byte0]: 56
5353 22:54:06.220185 [Byte1]: 50
5354 22:54:06.220808
5355 22:54:06.223370 Final RX Vref Byte 0 = 56 to rank0
5356 22:54:06.226205 Final RX Vref Byte 1 = 50 to rank0
5357 22:54:06.230124 Final RX Vref Byte 0 = 56 to rank1
5358 22:54:06.233031 Final RX Vref Byte 1 = 50 to rank1==
5359 22:54:06.236310 Dram Type= 6, Freq= 0, CH_0, rank 0
5360 22:54:06.239712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5361 22:54:06.240183 ==
5362 22:54:06.242764 DQS Delay:
5363 22:54:06.243342 DQS0 = 0, DQS1 = 0
5364 22:54:06.246131 DQM Delay:
5365 22:54:06.246598 DQM0 = 96, DQM1 = 85
5366 22:54:06.247140 DQ Delay:
5367 22:54:06.249353 DQ0 =96, DQ1 =96, DQ2 =90, DQ3 =92
5368 22:54:06.252380 DQ4 =98, DQ5 =88, DQ6 =104, DQ7 =106
5369 22:54:06.255801 DQ8 =80, DQ9 =74, DQ10 =84, DQ11 =80
5370 22:54:06.259581 DQ12 =90, DQ13 =88, DQ14 =98, DQ15 =90
5371 22:54:06.259987
5372 22:54:06.260303
5373 22:54:06.268953 [DQSOSCAuto] RK0, (LSB)MR18= 0x270e, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 409 ps
5374 22:54:06.272057 CH0 RK0: MR19=505, MR18=270E
5375 22:54:06.279127 CH0_RK0: MR19=0x505, MR18=0x270E, DQSOSC=409, MR23=63, INC=64, DEC=43
5376 22:54:06.279629
5377 22:54:06.282142 ----->DramcWriteLeveling(PI) begin...
5378 22:54:06.282557 ==
5379 22:54:06.285783 Dram Type= 6, Freq= 0, CH_0, rank 1
5380 22:54:06.289013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5381 22:54:06.289572 ==
5382 22:54:06.291893 Write leveling (Byte 0): 32 => 32
5383 22:54:06.295209 Write leveling (Byte 1): 31 => 31
5384 22:54:06.298780 DramcWriteLeveling(PI) end<-----
5385 22:54:06.299185
5386 22:54:06.299505 ==
5387 22:54:06.301673 Dram Type= 6, Freq= 0, CH_0, rank 1
5388 22:54:06.305101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5389 22:54:06.305542 ==
5390 22:54:06.308306 [Gating] SW mode calibration
5391 22:54:06.315169 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5392 22:54:06.321425 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5393 22:54:06.324907 0 14 0 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
5394 22:54:06.331087 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5395 22:54:06.334890 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5396 22:54:06.337869 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5397 22:54:06.344318 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5398 22:54:06.347907 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5399 22:54:06.350974 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5400 22:54:06.357481 0 14 28 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
5401 22:54:06.360899 0 15 0 | B1->B0 | 2f2f 2626 | 1 0 | (1 0) (1 0)
5402 22:54:06.364340 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5403 22:54:06.371090 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5404 22:54:06.374372 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5405 22:54:06.377305 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5406 22:54:06.384085 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5407 22:54:06.387367 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5408 22:54:06.390938 0 15 28 | B1->B0 | 2525 3333 | 0 0 | (0 0) (0 0)
5409 22:54:06.397277 1 0 0 | B1->B0 | 3f3f 4444 | 0 0 | (0 0) (0 0)
5410 22:54:06.400427 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5411 22:54:06.404320 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5412 22:54:06.410230 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5413 22:54:06.413783 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5414 22:54:06.416944 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5415 22:54:06.423795 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5416 22:54:06.427006 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5417 22:54:06.430382 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5418 22:54:06.436427 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5419 22:54:06.440296 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5420 22:54:06.443251 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5421 22:54:06.449969 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5422 22:54:06.453210 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5423 22:54:06.456480 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5424 22:54:06.463487 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5425 22:54:06.466164 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5426 22:54:06.469379 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5427 22:54:06.476030 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5428 22:54:06.479240 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5429 22:54:06.482694 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5430 22:54:06.489418 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5431 22:54:06.492623 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5432 22:54:06.495851 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5433 22:54:06.502685 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5434 22:54:06.505918 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5435 22:54:06.508966 Total UI for P1: 0, mck2ui 16
5436 22:54:06.512708 best dqsien dly found for B0: ( 1, 3, 0)
5437 22:54:06.515771 Total UI for P1: 0, mck2ui 16
5438 22:54:06.518720 best dqsien dly found for B1: ( 1, 3, 0)
5439 22:54:06.522301 best DQS0 dly(MCK, UI, PI) = (1, 3, 0)
5440 22:54:06.525165 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5441 22:54:06.525658
5442 22:54:06.528811 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 0)
5443 22:54:06.531639 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5444 22:54:06.535306 [Gating] SW calibration Done
5445 22:54:06.535788 ==
5446 22:54:06.538819 Dram Type= 6, Freq= 0, CH_0, rank 1
5447 22:54:06.542055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5448 22:54:06.545189 ==
5449 22:54:06.545679 RX Vref Scan: 0
5450 22:54:06.546038
5451 22:54:06.548490 RX Vref 0 -> 0, step: 1
5452 22:54:06.548902
5453 22:54:06.551446 RX Delay -80 -> 252, step: 8
5454 22:54:06.554911 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5455 22:54:06.558474 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5456 22:54:06.561694 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5457 22:54:06.564756 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5458 22:54:06.567923 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5459 22:54:06.574597 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5460 22:54:06.577947 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5461 22:54:06.581471 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5462 22:54:06.584998 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5463 22:54:06.588164 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5464 22:54:06.594996 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5465 22:54:06.598050 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5466 22:54:06.601360 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5467 22:54:06.604517 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5468 22:54:06.608007 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5469 22:54:06.611582 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5470 22:54:06.614890 ==
5471 22:54:06.617710 Dram Type= 6, Freq= 0, CH_0, rank 1
5472 22:54:06.620945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5473 22:54:06.621408 ==
5474 22:54:06.621953 DQS Delay:
5475 22:54:06.624323 DQS0 = 0, DQS1 = 0
5476 22:54:06.624735 DQM Delay:
5477 22:54:06.627387 DQM0 = 96, DQM1 = 89
5478 22:54:06.627801 DQ Delay:
5479 22:54:06.630584 DQ0 =95, DQ1 =99, DQ2 =87, DQ3 =91
5480 22:54:06.634183 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5481 22:54:06.637062 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5482 22:54:06.640700 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5483 22:54:06.641220
5484 22:54:06.641606
5485 22:54:06.641925 ==
5486 22:54:06.643631 Dram Type= 6, Freq= 0, CH_0, rank 1
5487 22:54:06.646991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5488 22:54:06.647408 ==
5489 22:54:06.650098
5490 22:54:06.650562
5491 22:54:06.650893 TX Vref Scan disable
5492 22:54:06.653645 == TX Byte 0 ==
5493 22:54:06.656993 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5494 22:54:06.660528 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5495 22:54:06.663537 == TX Byte 1 ==
5496 22:54:06.667024 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5497 22:54:06.670549 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5498 22:54:06.673558 ==
5499 22:54:06.674106 Dram Type= 6, Freq= 0, CH_0, rank 1
5500 22:54:06.680211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5501 22:54:06.680735 ==
5502 22:54:06.681068
5503 22:54:06.681404
5504 22:54:06.683524 TX Vref Scan disable
5505 22:54:06.683940 == TX Byte 0 ==
5506 22:54:06.689868 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5507 22:54:06.693394 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5508 22:54:06.693811 == TX Byte 1 ==
5509 22:54:06.699572 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5510 22:54:06.703260 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5511 22:54:06.703776
5512 22:54:06.704104 [DATLAT]
5513 22:54:06.706345 Freq=933, CH0 RK1
5514 22:54:06.706777
5515 22:54:06.707099 DATLAT Default: 0xb
5516 22:54:06.709609 0, 0xFFFF, sum = 0
5517 22:54:06.710355 1, 0xFFFF, sum = 0
5518 22:54:06.712689 2, 0xFFFF, sum = 0
5519 22:54:06.713468 3, 0xFFFF, sum = 0
5520 22:54:06.716590 4, 0xFFFF, sum = 0
5521 22:54:06.719745 5, 0xFFFF, sum = 0
5522 22:54:06.720263 6, 0xFFFF, sum = 0
5523 22:54:06.722934 7, 0xFFFF, sum = 0
5524 22:54:06.723356 8, 0xFFFF, sum = 0
5525 22:54:06.726404 9, 0xFFFF, sum = 0
5526 22:54:06.727104 10, 0x0, sum = 1
5527 22:54:06.729599 11, 0x0, sum = 2
5528 22:54:06.730130 12, 0x0, sum = 3
5529 22:54:06.732666 13, 0x0, sum = 4
5530 22:54:06.733088 best_step = 11
5531 22:54:06.733447
5532 22:54:06.733755 ==
5533 22:54:06.736469 Dram Type= 6, Freq= 0, CH_0, rank 1
5534 22:54:06.739385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5535 22:54:06.739808 ==
5536 22:54:06.742546 RX Vref Scan: 0
5537 22:54:06.742962
5538 22:54:06.745788 RX Vref 0 -> 0, step: 1
5539 22:54:06.746201
5540 22:54:06.746521 RX Delay -61 -> 252, step: 4
5541 22:54:06.753429 iDelay=199, Bit 0, Center 92 (3 ~ 182) 180
5542 22:54:06.756735 iDelay=199, Bit 1, Center 98 (3 ~ 194) 192
5543 22:54:06.760077 iDelay=199, Bit 2, Center 90 (-1 ~ 182) 184
5544 22:54:06.763321 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5545 22:54:06.766537 iDelay=199, Bit 4, Center 94 (3 ~ 186) 184
5546 22:54:06.772932 iDelay=199, Bit 5, Center 86 (-9 ~ 182) 192
5547 22:54:06.776246 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5548 22:54:06.779755 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5549 22:54:06.782826 iDelay=199, Bit 8, Center 78 (-13 ~ 170) 184
5550 22:54:06.785998 iDelay=199, Bit 9, Center 76 (-13 ~ 166) 180
5551 22:54:06.792705 iDelay=199, Bit 10, Center 86 (-9 ~ 182) 192
5552 22:54:06.796232 iDelay=199, Bit 11, Center 78 (-13 ~ 170) 184
5553 22:54:06.799820 iDelay=199, Bit 12, Center 92 (-1 ~ 186) 188
5554 22:54:06.802943 iDelay=199, Bit 13, Center 94 (3 ~ 186) 184
5555 22:54:06.806249 iDelay=199, Bit 14, Center 94 (3 ~ 186) 184
5556 22:54:06.812851 iDelay=199, Bit 15, Center 94 (3 ~ 186) 184
5557 22:54:06.813492 ==
5558 22:54:06.816427 Dram Type= 6, Freq= 0, CH_0, rank 1
5559 22:54:06.819857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5560 22:54:06.820378 ==
5561 22:54:06.820709 DQS Delay:
5562 22:54:06.822519 DQS0 = 0, DQS1 = 0
5563 22:54:06.822931 DQM Delay:
5564 22:54:06.825689 DQM0 = 95, DQM1 = 86
5565 22:54:06.826207 DQ Delay:
5566 22:54:06.829142 DQ0 =92, DQ1 =98, DQ2 =90, DQ3 =94
5567 22:54:06.832412 DQ4 =94, DQ5 =86, DQ6 =104, DQ7 =104
5568 22:54:06.835647 DQ8 =78, DQ9 =76, DQ10 =86, DQ11 =78
5569 22:54:06.839101 DQ12 =92, DQ13 =94, DQ14 =94, DQ15 =94
5570 22:54:06.839517
5571 22:54:06.839840
5572 22:54:06.848907 [DQSOSCAuto] RK1, (LSB)MR18= 0x25f6, (MSB)MR19= 0x504, tDQSOscB0 = 425 ps tDQSOscB1 = 410 ps
5573 22:54:06.849326 CH0 RK1: MR19=504, MR18=25F6
5574 22:54:06.855395 CH0_RK1: MR19=0x504, MR18=0x25F6, DQSOSC=410, MR23=63, INC=64, DEC=42
5575 22:54:06.858332 [RxdqsGatingPostProcess] freq 933
5576 22:54:06.865318 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5577 22:54:06.868305 best DQS0 dly(2T, 0.5T) = (0, 10)
5578 22:54:06.871799 best DQS1 dly(2T, 0.5T) = (0, 11)
5579 22:54:06.875268 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5580 22:54:06.878814 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5581 22:54:06.881808 best DQS0 dly(2T, 0.5T) = (0, 11)
5582 22:54:06.882272 best DQS1 dly(2T, 0.5T) = (0, 11)
5583 22:54:06.884684 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5584 22:54:06.888516 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5585 22:54:06.891545 Pre-setting of DQS Precalculation
5586 22:54:06.897881 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5587 22:54:06.898421 ==
5588 22:54:06.901030 Dram Type= 6, Freq= 0, CH_1, rank 0
5589 22:54:06.904798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5590 22:54:06.905405 ==
5591 22:54:06.911321 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5592 22:54:06.917980 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5593 22:54:06.921014 [CA 0] Center 37 (7~67) winsize 61
5594 22:54:06.924529 [CA 1] Center 36 (6~67) winsize 62
5595 22:54:06.927288 [CA 2] Center 34 (4~65) winsize 62
5596 22:54:06.931503 [CA 3] Center 33 (3~64) winsize 62
5597 22:54:06.934260 [CA 4] Center 34 (4~64) winsize 61
5598 22:54:06.937698 [CA 5] Center 33 (3~64) winsize 62
5599 22:54:06.938263
5600 22:54:06.940975 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5601 22:54:06.941560
5602 22:54:06.944456 [CATrainingPosCal] consider 1 rank data
5603 22:54:06.947619 u2DelayCellTimex100 = 270/100 ps
5604 22:54:06.951008 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5605 22:54:06.953955 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5606 22:54:06.957324 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5607 22:54:06.960955 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5608 22:54:06.964208 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5609 22:54:06.970912 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5610 22:54:06.971474
5611 22:54:06.973750 CA PerBit enable=1, Macro0, CA PI delay=33
5612 22:54:06.974209
5613 22:54:06.977499 [CBTSetCACLKResult] CA Dly = 33
5614 22:54:06.978078 CS Dly: 6 (0~37)
5615 22:54:06.978452 ==
5616 22:54:06.980737 Dram Type= 6, Freq= 0, CH_1, rank 1
5617 22:54:06.984172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5618 22:54:06.987556 ==
5619 22:54:06.990481 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5620 22:54:06.996930 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5621 22:54:07.000344 [CA 0] Center 36 (6~67) winsize 62
5622 22:54:07.003875 [CA 1] Center 37 (7~68) winsize 62
5623 22:54:07.007002 [CA 2] Center 34 (4~65) winsize 62
5624 22:54:07.010192 [CA 3] Center 33 (3~64) winsize 62
5625 22:54:07.013695 [CA 4] Center 34 (3~65) winsize 63
5626 22:54:07.016869 [CA 5] Center 33 (3~64) winsize 62
5627 22:54:07.017502
5628 22:54:07.020135 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5629 22:54:07.020696
5630 22:54:07.023135 [CATrainingPosCal] consider 2 rank data
5631 22:54:07.027059 u2DelayCellTimex100 = 270/100 ps
5632 22:54:07.030536 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5633 22:54:07.033369 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5634 22:54:07.036789 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5635 22:54:07.043223 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5636 22:54:07.046345 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5637 22:54:07.049853 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5638 22:54:07.050269
5639 22:54:07.052865 CA PerBit enable=1, Macro0, CA PI delay=33
5640 22:54:07.053359
5641 22:54:07.056751 [CBTSetCACLKResult] CA Dly = 33
5642 22:54:07.057367 CS Dly: 7 (0~39)
5643 22:54:07.057743
5644 22:54:07.060147 ----->DramcWriteLeveling(PI) begin...
5645 22:54:07.063437 ==
5646 22:54:07.064180 Dram Type= 6, Freq= 0, CH_1, rank 0
5647 22:54:07.069722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5648 22:54:07.070215 ==
5649 22:54:07.073297 Write leveling (Byte 0): 25 => 25
5650 22:54:07.076286 Write leveling (Byte 1): 27 => 27
5651 22:54:07.079567 DramcWriteLeveling(PI) end<-----
5652 22:54:07.080142
5653 22:54:07.080506 ==
5654 22:54:07.083061 Dram Type= 6, Freq= 0, CH_1, rank 0
5655 22:54:07.086012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5656 22:54:07.086472 ==
5657 22:54:07.089137 [Gating] SW mode calibration
5658 22:54:07.095804 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5659 22:54:07.102826 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5660 22:54:07.105801 0 14 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5661 22:54:07.109127 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5662 22:54:07.116191 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5663 22:54:07.119216 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5664 22:54:07.122774 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5665 22:54:07.128789 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5666 22:54:07.132126 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
5667 22:54:07.135688 0 14 28 | B1->B0 | 2c2c 2929 | 0 0 | (1 0) (0 0)
5668 22:54:07.142596 0 15 0 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
5669 22:54:07.145758 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5670 22:54:07.148913 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5671 22:54:07.155057 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5672 22:54:07.158550 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5673 22:54:07.162423 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5674 22:54:07.168656 0 15 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5675 22:54:07.171818 0 15 28 | B1->B0 | 2e2e 3838 | 0 0 | (0 0) (0 0)
5676 22:54:07.174862 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5677 22:54:07.181838 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5678 22:54:07.184833 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5679 22:54:07.188318 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5680 22:54:07.194733 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5681 22:54:07.198150 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5682 22:54:07.201254 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5683 22:54:07.207729 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5684 22:54:07.211164 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5685 22:54:07.214721 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5686 22:54:07.221452 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5687 22:54:07.224547 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5688 22:54:07.227630 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5689 22:54:07.234275 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5690 22:54:07.237655 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5691 22:54:07.240413 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5692 22:54:07.247315 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5693 22:54:07.250679 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5694 22:54:07.254168 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5695 22:54:07.260475 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5696 22:54:07.263896 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5697 22:54:07.266976 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5698 22:54:07.273838 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5699 22:54:07.276863 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5700 22:54:07.280359 Total UI for P1: 0, mck2ui 16
5701 22:54:07.283727 best dqsien dly found for B0: ( 1, 2, 26)
5702 22:54:07.286853 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5703 22:54:07.290172 Total UI for P1: 0, mck2ui 16
5704 22:54:07.293586 best dqsien dly found for B1: ( 1, 2, 28)
5705 22:54:07.296604 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5706 22:54:07.299880 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5707 22:54:07.300341
5708 22:54:07.306332 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5709 22:54:07.310337 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5710 22:54:07.313628 [Gating] SW calibration Done
5711 22:54:07.314088 ==
5712 22:54:07.316404 Dram Type= 6, Freq= 0, CH_1, rank 0
5713 22:54:07.319731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5714 22:54:07.320381 ==
5715 22:54:07.321001 RX Vref Scan: 0
5716 22:54:07.321612
5717 22:54:07.323041 RX Vref 0 -> 0, step: 1
5718 22:54:07.323497
5719 22:54:07.326553 RX Delay -80 -> 252, step: 8
5720 22:54:07.329846 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5721 22:54:07.332961 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5722 22:54:07.339653 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5723 22:54:07.342906 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5724 22:54:07.346164 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5725 22:54:07.349479 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5726 22:54:07.352546 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5727 22:54:07.355963 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5728 22:54:07.362838 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5729 22:54:07.366485 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5730 22:54:07.369388 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5731 22:54:07.372684 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5732 22:54:07.376257 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5733 22:54:07.382571 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5734 22:54:07.385643 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5735 22:54:07.388992 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5736 22:54:07.389602 ==
5737 22:54:07.392532 Dram Type= 6, Freq= 0, CH_1, rank 0
5738 22:54:07.395725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5739 22:54:07.396190 ==
5740 22:54:07.399073 DQS Delay:
5741 22:54:07.399534 DQS0 = 0, DQS1 = 0
5742 22:54:07.399893 DQM Delay:
5743 22:54:07.402148 DQM0 = 100, DQM1 = 90
5744 22:54:07.402609 DQ Delay:
5745 22:54:07.405375 DQ0 =103, DQ1 =95, DQ2 =95, DQ3 =99
5746 22:54:07.409073 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5747 22:54:07.412191 DQ8 =75, DQ9 =83, DQ10 =91, DQ11 =79
5748 22:54:07.415746 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5749 22:54:07.416306
5750 22:54:07.416668
5751 22:54:07.418468 ==
5752 22:54:07.421755 Dram Type= 6, Freq= 0, CH_1, rank 0
5753 22:54:07.425813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5754 22:54:07.426333 ==
5755 22:54:07.426705
5756 22:54:07.427035
5757 22:54:07.428754 TX Vref Scan disable
5758 22:54:07.429317 == TX Byte 0 ==
5759 22:54:07.435050 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5760 22:54:07.438512 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5761 22:54:07.439092 == TX Byte 1 ==
5762 22:54:07.445056 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5763 22:54:07.448262 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5764 22:54:07.448731 ==
5765 22:54:07.451393 Dram Type= 6, Freq= 0, CH_1, rank 0
5766 22:54:07.455060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5767 22:54:07.455522 ==
5768 22:54:07.455906
5769 22:54:07.456278
5770 22:54:07.458193 TX Vref Scan disable
5771 22:54:07.461080 == TX Byte 0 ==
5772 22:54:07.464876 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5773 22:54:07.468356 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5774 22:54:07.471531 == TX Byte 1 ==
5775 22:54:07.474714 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5776 22:54:07.477939 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5777 22:54:07.478400
5778 22:54:07.480915 [DATLAT]
5779 22:54:07.481541 Freq=933, CH1 RK0
5780 22:54:07.482030
5781 22:54:07.484426 DATLAT Default: 0xd
5782 22:54:07.485005 0, 0xFFFF, sum = 0
5783 22:54:07.487898 1, 0xFFFF, sum = 0
5784 22:54:07.488418 2, 0xFFFF, sum = 0
5785 22:54:07.490942 3, 0xFFFF, sum = 0
5786 22:54:07.491443 4, 0xFFFF, sum = 0
5787 22:54:07.494305 5, 0xFFFF, sum = 0
5788 22:54:07.494742 6, 0xFFFF, sum = 0
5789 22:54:07.497620 7, 0xFFFF, sum = 0
5790 22:54:07.498115 8, 0xFFFF, sum = 0
5791 22:54:07.500689 9, 0xFFFF, sum = 0
5792 22:54:07.501112 10, 0x0, sum = 1
5793 22:54:07.504378 11, 0x0, sum = 2
5794 22:54:07.504802 12, 0x0, sum = 3
5795 22:54:07.507580 13, 0x0, sum = 4
5796 22:54:07.508003 best_step = 11
5797 22:54:07.508329
5798 22:54:07.508633 ==
5799 22:54:07.510557 Dram Type= 6, Freq= 0, CH_1, rank 0
5800 22:54:07.517643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5801 22:54:07.518147 ==
5802 22:54:07.518475 RX Vref Scan: 1
5803 22:54:07.518780
5804 22:54:07.520180 RX Vref 0 -> 0, step: 1
5805 22:54:07.520600
5806 22:54:07.524129 RX Delay -69 -> 252, step: 4
5807 22:54:07.524553
5808 22:54:07.527165 Set Vref, RX VrefLevel [Byte0]: 50
5809 22:54:07.530100 [Byte1]: 52
5810 22:54:07.530542
5811 22:54:07.533560 Final RX Vref Byte 0 = 50 to rank0
5812 22:54:07.536648 Final RX Vref Byte 1 = 52 to rank0
5813 22:54:07.539886 Final RX Vref Byte 0 = 50 to rank1
5814 22:54:07.543832 Final RX Vref Byte 1 = 52 to rank1==
5815 22:54:07.546710 Dram Type= 6, Freq= 0, CH_1, rank 0
5816 22:54:07.553050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5817 22:54:07.553518 ==
5818 22:54:07.553857 DQS Delay:
5819 22:54:07.554162 DQS0 = 0, DQS1 = 0
5820 22:54:07.556425 DQM Delay:
5821 22:54:07.556837 DQM0 = 100, DQM1 = 94
5822 22:54:07.560163 DQ Delay:
5823 22:54:07.563144 DQ0 =106, DQ1 =96, DQ2 =92, DQ3 =98
5824 22:54:07.566372 DQ4 =98, DQ5 =112, DQ6 =108, DQ7 =96
5825 22:54:07.570080 DQ8 =80, DQ9 =84, DQ10 =96, DQ11 =82
5826 22:54:07.572909 DQ12 =100, DQ13 =100, DQ14 =106, DQ15 =104
5827 22:54:07.573428
5828 22:54:07.573772
5829 22:54:07.579793 [DQSOSCAuto] RK0, (LSB)MR18= 0x1707, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 414 ps
5830 22:54:07.582830 CH1 RK0: MR19=505, MR18=1707
5831 22:54:07.589722 CH1_RK0: MR19=0x505, MR18=0x1707, DQSOSC=414, MR23=63, INC=63, DEC=42
5832 22:54:07.590265
5833 22:54:07.592856 ----->DramcWriteLeveling(PI) begin...
5834 22:54:07.593287 ==
5835 22:54:07.596022 Dram Type= 6, Freq= 0, CH_1, rank 1
5836 22:54:07.599286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5837 22:54:07.599847 ==
5838 22:54:07.603135 Write leveling (Byte 0): 28 => 28
5839 22:54:07.605780 Write leveling (Byte 1): 28 => 28
5840 22:54:07.609195 DramcWriteLeveling(PI) end<-----
5841 22:54:07.609669
5842 22:54:07.609998 ==
5843 22:54:07.612303 Dram Type= 6, Freq= 0, CH_1, rank 1
5844 22:54:07.619486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5845 22:54:07.620016 ==
5846 22:54:07.620354 [Gating] SW mode calibration
5847 22:54:07.629389 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5848 22:54:07.632571 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5849 22:54:07.638740 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5850 22:54:07.642147 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5851 22:54:07.645638 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5852 22:54:07.652052 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5853 22:54:07.655598 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5854 22:54:07.658934 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5855 22:54:07.665457 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5856 22:54:07.668866 0 14 28 | B1->B0 | 2929 2d2d | 0 0 | (0 0) (0 1)
5857 22:54:07.672279 0 15 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5858 22:54:07.678617 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5859 22:54:07.682098 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5860 22:54:07.685197 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5861 22:54:07.688670 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5862 22:54:07.695387 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5863 22:54:07.698561 0 15 24 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
5864 22:54:07.701829 0 15 28 | B1->B0 | 3636 3131 | 0 0 | (0 0) (0 0)
5865 22:54:07.708529 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5866 22:54:07.711948 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5867 22:54:07.715206 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5868 22:54:07.721982 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5869 22:54:07.724577 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5870 22:54:07.728228 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5871 22:54:07.734854 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5872 22:54:07.738038 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5873 22:54:07.744441 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5874 22:54:07.748036 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5875 22:54:07.751447 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5876 22:54:07.754808 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5877 22:54:07.761159 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5878 22:54:07.764762 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5879 22:54:07.770673 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5880 22:54:07.774329 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5881 22:54:07.777309 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5882 22:54:07.784262 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5883 22:54:07.787955 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5884 22:54:07.790471 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5885 22:54:07.794535 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5886 22:54:07.800600 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5887 22:54:07.804103 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5888 22:54:07.807269 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5889 22:54:07.810626 Total UI for P1: 0, mck2ui 16
5890 22:54:07.814317 best dqsien dly found for B1: ( 1, 2, 26)
5891 22:54:07.820431 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5892 22:54:07.824146 Total UI for P1: 0, mck2ui 16
5893 22:54:07.827077 best dqsien dly found for B0: ( 1, 2, 26)
5894 22:54:07.830228 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5895 22:54:07.833704 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5896 22:54:07.834192
5897 22:54:07.837190 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5898 22:54:07.840311 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5899 22:54:07.843352 [Gating] SW calibration Done
5900 22:54:07.843809 ==
5901 22:54:07.846548 Dram Type= 6, Freq= 0, CH_1, rank 1
5902 22:54:07.850194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5903 22:54:07.850617 ==
5904 22:54:07.853702 RX Vref Scan: 0
5905 22:54:07.854116
5906 22:54:07.856387 RX Vref 0 -> 0, step: 1
5907 22:54:07.856803
5908 22:54:07.857128 RX Delay -80 -> 252, step: 8
5909 22:54:07.863012 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5910 22:54:07.866589 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5911 22:54:07.870048 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5912 22:54:07.873426 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5913 22:54:07.876285 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5914 22:54:07.879558 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5915 22:54:07.886330 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5916 22:54:07.889260 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5917 22:54:07.893036 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5918 22:54:07.896743 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5919 22:54:07.899591 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5920 22:54:07.905904 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5921 22:54:07.909281 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5922 22:54:07.912366 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5923 22:54:07.916158 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5924 22:54:07.918937 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5925 22:54:07.922392 ==
5926 22:54:07.922910 Dram Type= 6, Freq= 0, CH_1, rank 1
5927 22:54:07.929125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5928 22:54:07.929576 ==
5929 22:54:07.929907 DQS Delay:
5930 22:54:07.932064 DQS0 = 0, DQS1 = 0
5931 22:54:07.932475 DQM Delay:
5932 22:54:07.935606 DQM0 = 100, DQM1 = 91
5933 22:54:07.936128 DQ Delay:
5934 22:54:07.938792 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5935 22:54:07.942654 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5936 22:54:07.945002 DQ8 =79, DQ9 =79, DQ10 =95, DQ11 =83
5937 22:54:07.948642 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =99
5938 22:54:07.949260
5939 22:54:07.949672
5940 22:54:07.949986 ==
5941 22:54:07.952087 Dram Type= 6, Freq= 0, CH_1, rank 1
5942 22:54:07.955308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5943 22:54:07.955864 ==
5944 22:54:07.958473
5945 22:54:07.958931
5946 22:54:07.959291 TX Vref Scan disable
5947 22:54:07.962160 == TX Byte 0 ==
5948 22:54:07.964789 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5949 22:54:07.968422 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5950 22:54:07.972111 == TX Byte 1 ==
5951 22:54:07.975453 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5952 22:54:07.978499 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5953 22:54:07.978963 ==
5954 22:54:07.981526 Dram Type= 6, Freq= 0, CH_1, rank 1
5955 22:54:07.988483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5956 22:54:07.989034 ==
5957 22:54:07.989442
5958 22:54:07.989784
5959 22:54:07.990267 TX Vref Scan disable
5960 22:54:07.992394 == TX Byte 0 ==
5961 22:54:07.995916 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5962 22:54:08.002520 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5963 22:54:08.003076 == TX Byte 1 ==
5964 22:54:08.005873 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5965 22:54:08.011967 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5966 22:54:08.012432
5967 22:54:08.012804 [DATLAT]
5968 22:54:08.013141 Freq=933, CH1 RK1
5969 22:54:08.013531
5970 22:54:08.016073 DATLAT Default: 0xb
5971 22:54:08.019303 0, 0xFFFF, sum = 0
5972 22:54:08.019861 1, 0xFFFF, sum = 0
5973 22:54:08.022117 2, 0xFFFF, sum = 0
5974 22:54:08.022584 3, 0xFFFF, sum = 0
5975 22:54:08.025442 4, 0xFFFF, sum = 0
5976 22:54:08.025912 5, 0xFFFF, sum = 0
5977 22:54:08.028778 6, 0xFFFF, sum = 0
5978 22:54:08.029246 7, 0xFFFF, sum = 0
5979 22:54:08.031762 8, 0xFFFF, sum = 0
5980 22:54:08.032229 9, 0xFFFF, sum = 0
5981 22:54:08.036017 10, 0x0, sum = 1
5982 22:54:08.036586 11, 0x0, sum = 2
5983 22:54:08.038787 12, 0x0, sum = 3
5984 22:54:08.039259 13, 0x0, sum = 4
5985 22:54:08.042106 best_step = 11
5986 22:54:08.042564
5987 22:54:08.042925 ==
5988 22:54:08.045945 Dram Type= 6, Freq= 0, CH_1, rank 1
5989 22:54:08.048588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5990 22:54:08.049246 ==
5991 22:54:08.049840 RX Vref Scan: 0
5992 22:54:08.050200
5993 22:54:08.051975 RX Vref 0 -> 0, step: 1
5994 22:54:08.052432
5995 22:54:08.054823 RX Delay -61 -> 252, step: 4
5996 22:54:08.061413 iDelay=207, Bit 0, Center 104 (15 ~ 194) 180
5997 22:54:08.065704 iDelay=207, Bit 1, Center 94 (7 ~ 182) 176
5998 22:54:08.068458 iDelay=207, Bit 2, Center 90 (3 ~ 178) 176
5999 22:54:08.071790 iDelay=207, Bit 3, Center 98 (15 ~ 182) 168
6000 22:54:08.075376 iDelay=207, Bit 4, Center 100 (11 ~ 190) 180
6001 22:54:08.082006 iDelay=207, Bit 5, Center 110 (23 ~ 198) 176
6002 22:54:08.084575 iDelay=207, Bit 6, Center 112 (19 ~ 206) 188
6003 22:54:08.088217 iDelay=207, Bit 7, Center 98 (7 ~ 190) 184
6004 22:54:08.091540 iDelay=207, Bit 8, Center 82 (-5 ~ 170) 176
6005 22:54:08.094634 iDelay=207, Bit 9, Center 84 (-5 ~ 174) 180
6006 22:54:08.098117 iDelay=207, Bit 10, Center 94 (3 ~ 186) 184
6007 22:54:08.104777 iDelay=207, Bit 11, Center 84 (-5 ~ 174) 180
6008 22:54:08.108285 iDelay=207, Bit 12, Center 104 (15 ~ 194) 180
6009 22:54:08.110963 iDelay=207, Bit 13, Center 98 (7 ~ 190) 184
6010 22:54:08.114484 iDelay=207, Bit 14, Center 98 (7 ~ 190) 184
6011 22:54:08.118028 iDelay=207, Bit 15, Center 102 (11 ~ 194) 184
6012 22:54:08.121434 ==
6013 22:54:08.124649 Dram Type= 6, Freq= 0, CH_1, rank 1
6014 22:54:08.127545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6015 22:54:08.128020 ==
6016 22:54:08.128379 DQS Delay:
6017 22:54:08.131134 DQS0 = 0, DQS1 = 0
6018 22:54:08.131590 DQM Delay:
6019 22:54:08.133881 DQM0 = 100, DQM1 = 93
6020 22:54:08.134342 DQ Delay:
6021 22:54:08.137621 DQ0 =104, DQ1 =94, DQ2 =90, DQ3 =98
6022 22:54:08.140659 DQ4 =100, DQ5 =110, DQ6 =112, DQ7 =98
6023 22:54:08.143967 DQ8 =82, DQ9 =84, DQ10 =94, DQ11 =84
6024 22:54:08.147498 DQ12 =104, DQ13 =98, DQ14 =98, DQ15 =102
6025 22:54:08.147914
6026 22:54:08.148238
6027 22:54:08.157450 [DQSOSCAuto] RK1, (LSB)MR18= 0x5ff, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 420 ps
6028 22:54:08.157873 CH1 RK1: MR19=504, MR18=5FF
6029 22:54:08.164056 CH1_RK1: MR19=0x504, MR18=0x5FF, DQSOSC=420, MR23=63, INC=61, DEC=40
6030 22:54:08.167233 [RxdqsGatingPostProcess] freq 933
6031 22:54:08.173872 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6032 22:54:08.177300 best DQS0 dly(2T, 0.5T) = (0, 10)
6033 22:54:08.180259 best DQS1 dly(2T, 0.5T) = (0, 10)
6034 22:54:08.184170 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6035 22:54:08.187020 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6036 22:54:08.187481 best DQS0 dly(2T, 0.5T) = (0, 10)
6037 22:54:08.190746 best DQS1 dly(2T, 0.5T) = (0, 10)
6038 22:54:08.193665 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6039 22:54:08.197395 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6040 22:54:08.200167 Pre-setting of DQS Precalculation
6041 22:54:08.206680 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6042 22:54:08.213123 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6043 22:54:08.220217 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6044 22:54:08.220815
6045 22:54:08.221178
6046 22:54:08.223440 [Calibration Summary] 1866 Mbps
6047 22:54:08.223896 CH 0, Rank 0
6048 22:54:08.227033 SW Impedance : PASS
6049 22:54:08.230020 DUTY Scan : NO K
6050 22:54:08.230476 ZQ Calibration : PASS
6051 22:54:08.233491 Jitter Meter : NO K
6052 22:54:08.236540 CBT Training : PASS
6053 22:54:08.236997 Write leveling : PASS
6054 22:54:08.239469 RX DQS gating : PASS
6055 22:54:08.242847 RX DQ/DQS(RDDQC) : PASS
6056 22:54:08.243303 TX DQ/DQS : PASS
6057 22:54:08.246107 RX DATLAT : PASS
6058 22:54:08.249628 RX DQ/DQS(Engine): PASS
6059 22:54:08.250104 TX OE : NO K
6060 22:54:08.253036 All Pass.
6061 22:54:08.253536
6062 22:54:08.253916 CH 0, Rank 1
6063 22:54:08.256752 SW Impedance : PASS
6064 22:54:08.257211 DUTY Scan : NO K
6065 22:54:08.259589 ZQ Calibration : PASS
6066 22:54:08.262789 Jitter Meter : NO K
6067 22:54:08.263249 CBT Training : PASS
6068 22:54:08.266040 Write leveling : PASS
6069 22:54:08.269497 RX DQS gating : PASS
6070 22:54:08.270024 RX DQ/DQS(RDDQC) : PASS
6071 22:54:08.272791 TX DQ/DQS : PASS
6072 22:54:08.276090 RX DATLAT : PASS
6073 22:54:08.276639 RX DQ/DQS(Engine): PASS
6074 22:54:08.279863 TX OE : NO K
6075 22:54:08.280413 All Pass.
6076 22:54:08.280775
6077 22:54:08.282468 CH 1, Rank 0
6078 22:54:08.282928 SW Impedance : PASS
6079 22:54:08.286119 DUTY Scan : NO K
6080 22:54:08.289211 ZQ Calibration : PASS
6081 22:54:08.289706 Jitter Meter : NO K
6082 22:54:08.292589 CBT Training : PASS
6083 22:54:08.293119 Write leveling : PASS
6084 22:54:08.295884 RX DQS gating : PASS
6085 22:54:08.299486 RX DQ/DQS(RDDQC) : PASS
6086 22:54:08.300050 TX DQ/DQS : PASS
6087 22:54:08.302213 RX DATLAT : PASS
6088 22:54:08.305528 RX DQ/DQS(Engine): PASS
6089 22:54:08.306015 TX OE : NO K
6090 22:54:08.309041 All Pass.
6091 22:54:08.309492
6092 22:54:08.309823 CH 1, Rank 1
6093 22:54:08.311902 SW Impedance : PASS
6094 22:54:08.312321 DUTY Scan : NO K
6095 22:54:08.315348 ZQ Calibration : PASS
6096 22:54:08.318756 Jitter Meter : NO K
6097 22:54:08.319368 CBT Training : PASS
6098 22:54:08.322490 Write leveling : PASS
6099 22:54:08.325162 RX DQS gating : PASS
6100 22:54:08.325724 RX DQ/DQS(RDDQC) : PASS
6101 22:54:08.328472 TX DQ/DQS : PASS
6102 22:54:08.331678 RX DATLAT : PASS
6103 22:54:08.332192 RX DQ/DQS(Engine): PASS
6104 22:54:08.335092 TX OE : NO K
6105 22:54:08.335525 All Pass.
6106 22:54:08.335853
6107 22:54:08.339347 DramC Write-DBI off
6108 22:54:08.341837 PER_BANK_REFRESH: Hybrid Mode
6109 22:54:08.342303 TX_TRACKING: ON
6110 22:54:08.351462 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6111 22:54:08.354901 [FAST_K] Save calibration result to emmc
6112 22:54:08.358542 dramc_set_vcore_voltage set vcore to 650000
6113 22:54:08.361508 Read voltage for 400, 6
6114 22:54:08.361931 Vio18 = 0
6115 22:54:08.362259 Vcore = 650000
6116 22:54:08.364882 Vdram = 0
6117 22:54:08.365296 Vddq = 0
6118 22:54:08.365675 Vmddr = 0
6119 22:54:08.371830 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6120 22:54:08.374741 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6121 22:54:08.378205 MEM_TYPE=3, freq_sel=20
6122 22:54:08.382065 sv_algorithm_assistance_LP4_800
6123 22:54:08.385013 ============ PULL DRAM RESETB DOWN ============
6124 22:54:08.391064 ========== PULL DRAM RESETB DOWN end =========
6125 22:54:08.394557 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6126 22:54:08.398107 ===================================
6127 22:54:08.401658 LPDDR4 DRAM CONFIGURATION
6128 22:54:08.404512 ===================================
6129 22:54:08.405046 EX_ROW_EN[0] = 0x0
6130 22:54:08.407706 EX_ROW_EN[1] = 0x0
6131 22:54:08.408123 LP4Y_EN = 0x0
6132 22:54:08.411323 WORK_FSP = 0x0
6133 22:54:08.411741 WL = 0x2
6134 22:54:08.415058 RL = 0x2
6135 22:54:08.415581 BL = 0x2
6136 22:54:08.417816 RPST = 0x0
6137 22:54:08.420594 RD_PRE = 0x0
6138 22:54:08.421123 WR_PRE = 0x1
6139 22:54:08.424567 WR_PST = 0x0
6140 22:54:08.425073 DBI_WR = 0x0
6141 22:54:08.427700 DBI_RD = 0x0
6142 22:54:08.428213 OTF = 0x1
6143 22:54:08.430600 ===================================
6144 22:54:08.434111 ===================================
6145 22:54:08.437642 ANA top config
6146 22:54:08.440823 ===================================
6147 22:54:08.441623 DLL_ASYNC_EN = 0
6148 22:54:08.444042 ALL_SLAVE_EN = 1
6149 22:54:08.447166 NEW_RANK_MODE = 1
6150 22:54:08.450881 DLL_IDLE_MODE = 1
6151 22:54:08.451559 LP45_APHY_COMB_EN = 1
6152 22:54:08.454095 TX_ODT_DIS = 1
6153 22:54:08.457055 NEW_8X_MODE = 1
6154 22:54:08.460187 ===================================
6155 22:54:08.463951 ===================================
6156 22:54:08.467095 data_rate = 800
6157 22:54:08.470013 CKR = 1
6158 22:54:08.473430 DQ_P2S_RATIO = 4
6159 22:54:08.477066 ===================================
6160 22:54:08.477620 CA_P2S_RATIO = 4
6161 22:54:08.480381 DQ_CA_OPEN = 0
6162 22:54:08.483455 DQ_SEMI_OPEN = 1
6163 22:54:08.486996 CA_SEMI_OPEN = 1
6164 22:54:08.489953 CA_FULL_RATE = 0
6165 22:54:08.493386 DQ_CKDIV4_EN = 0
6166 22:54:08.493846 CA_CKDIV4_EN = 1
6167 22:54:08.496755 CA_PREDIV_EN = 0
6168 22:54:08.499953 PH8_DLY = 0
6169 22:54:08.503327 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6170 22:54:08.506694 DQ_AAMCK_DIV = 0
6171 22:54:08.509808 CA_AAMCK_DIV = 0
6172 22:54:08.510272 CA_ADMCK_DIV = 4
6173 22:54:08.512925 DQ_TRACK_CA_EN = 0
6174 22:54:08.516796 CA_PICK = 800
6175 22:54:08.519919 CA_MCKIO = 400
6176 22:54:08.523246 MCKIO_SEMI = 400
6177 22:54:08.526404 PLL_FREQ = 3016
6178 22:54:08.529470 DQ_UI_PI_RATIO = 32
6179 22:54:08.532953 CA_UI_PI_RATIO = 32
6180 22:54:08.536059 ===================================
6181 22:54:08.539490 ===================================
6182 22:54:08.540014 memory_type:LPDDR4
6183 22:54:08.542545 GP_NUM : 10
6184 22:54:08.546197 SRAM_EN : 1
6185 22:54:08.546655 MD32_EN : 0
6186 22:54:08.549445 ===================================
6187 22:54:08.552440 [ANA_INIT] >>>>>>>>>>>>>>
6188 22:54:08.555998 <<<<<< [CONFIGURE PHASE]: ANA_TX
6189 22:54:08.559279 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6190 22:54:08.562952 ===================================
6191 22:54:08.565750 data_rate = 800,PCW = 0X7400
6192 22:54:08.569417 ===================================
6193 22:54:08.572757 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6194 22:54:08.575526 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6195 22:54:08.588792 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6196 22:54:08.592132 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6197 22:54:08.595324 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6198 22:54:08.599239 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6199 22:54:08.601890 [ANA_INIT] flow start
6200 22:54:08.605321 [ANA_INIT] PLL >>>>>>>>
6201 22:54:08.605910 [ANA_INIT] PLL <<<<<<<<
6202 22:54:08.608507 [ANA_INIT] MIDPI >>>>>>>>
6203 22:54:08.612394 [ANA_INIT] MIDPI <<<<<<<<
6204 22:54:08.612851 [ANA_INIT] DLL >>>>>>>>
6205 22:54:08.615491 [ANA_INIT] flow end
6206 22:54:08.618391 ============ LP4 DIFF to SE enter ============
6207 22:54:08.625005 ============ LP4 DIFF to SE exit ============
6208 22:54:08.625601 [ANA_INIT] <<<<<<<<<<<<<
6209 22:54:08.628334 [Flow] Enable top DCM control >>>>>
6210 22:54:08.631407 [Flow] Enable top DCM control <<<<<
6211 22:54:08.634738 Enable DLL master slave shuffle
6212 22:54:08.641599 ==============================================================
6213 22:54:08.642033 Gating Mode config
6214 22:54:08.648055 ==============================================================
6215 22:54:08.651283 Config description:
6216 22:54:08.661197 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6217 22:54:08.667738 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6218 22:54:08.670936 SELPH_MODE 0: By rank 1: By Phase
6219 22:54:08.677787 ==============================================================
6220 22:54:08.681023 GAT_TRACK_EN = 0
6221 22:54:08.684330 RX_GATING_MODE = 2
6222 22:54:08.684843 RX_GATING_TRACK_MODE = 2
6223 22:54:08.687494 SELPH_MODE = 1
6224 22:54:08.690699 PICG_EARLY_EN = 1
6225 22:54:08.694742 VALID_LAT_VALUE = 1
6226 22:54:08.700769 ==============================================================
6227 22:54:08.704455 Enter into Gating configuration >>>>
6228 22:54:08.707495 Exit from Gating configuration <<<<
6229 22:54:08.710711 Enter into DVFS_PRE_config >>>>>
6230 22:54:08.720856 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6231 22:54:08.723747 Exit from DVFS_PRE_config <<<<<
6232 22:54:08.727005 Enter into PICG configuration >>>>
6233 22:54:08.730657 Exit from PICG configuration <<<<
6234 22:54:08.733680 [RX_INPUT] configuration >>>>>
6235 22:54:08.737109 [RX_INPUT] configuration <<<<<
6236 22:54:08.740385 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6237 22:54:08.746759 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6238 22:54:08.753172 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6239 22:54:08.760065 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6240 22:54:08.766653 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6241 22:54:08.770289 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6242 22:54:08.776968 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6243 22:54:08.779960 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6244 22:54:08.783033 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6245 22:54:08.786844 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6246 22:54:08.793516 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6247 22:54:08.796095 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6248 22:54:08.799775 ===================================
6249 22:54:08.802623 LPDDR4 DRAM CONFIGURATION
6250 22:54:08.806560 ===================================
6251 22:54:08.807109 EX_ROW_EN[0] = 0x0
6252 22:54:08.809222 EX_ROW_EN[1] = 0x0
6253 22:54:08.809732 LP4Y_EN = 0x0
6254 22:54:08.812614 WORK_FSP = 0x0
6255 22:54:08.813101 WL = 0x2
6256 22:54:08.816063 RL = 0x2
6257 22:54:08.819366 BL = 0x2
6258 22:54:08.819894 RPST = 0x0
6259 22:54:08.822972 RD_PRE = 0x0
6260 22:54:08.823565 WR_PRE = 0x1
6261 22:54:08.825929 WR_PST = 0x0
6262 22:54:08.826386 DBI_WR = 0x0
6263 22:54:08.829095 DBI_RD = 0x0
6264 22:54:08.829552 OTF = 0x1
6265 22:54:08.832684 ===================================
6266 22:54:08.835792 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6267 22:54:08.842645 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6268 22:54:08.845622 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6269 22:54:08.849553 ===================================
6270 22:54:08.852042 LPDDR4 DRAM CONFIGURATION
6271 22:54:08.855420 ===================================
6272 22:54:08.855841 EX_ROW_EN[0] = 0x10
6273 22:54:08.859077 EX_ROW_EN[1] = 0x0
6274 22:54:08.859498 LP4Y_EN = 0x0
6275 22:54:08.862566 WORK_FSP = 0x0
6276 22:54:08.863090 WL = 0x2
6277 22:54:08.865557 RL = 0x2
6278 22:54:08.869360 BL = 0x2
6279 22:54:08.869894 RPST = 0x0
6280 22:54:08.872981 RD_PRE = 0x0
6281 22:54:08.873552 WR_PRE = 0x1
6282 22:54:08.875994 WR_PST = 0x0
6283 22:54:08.876516 DBI_WR = 0x0
6284 22:54:08.878689 DBI_RD = 0x0
6285 22:54:08.879108 OTF = 0x1
6286 22:54:08.882250 ===================================
6287 22:54:08.888604 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6288 22:54:08.892710 nWR fixed to 30
6289 22:54:08.895885 [ModeRegInit_LP4] CH0 RK0
6290 22:54:08.896317 [ModeRegInit_LP4] CH0 RK1
6291 22:54:08.899398 [ModeRegInit_LP4] CH1 RK0
6292 22:54:08.902451 [ModeRegInit_LP4] CH1 RK1
6293 22:54:08.902875 match AC timing 19
6294 22:54:08.909019 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6295 22:54:08.912558 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6296 22:54:08.915717 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6297 22:54:08.922125 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6298 22:54:08.925664 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6299 22:54:08.926089 ==
6300 22:54:08.928817 Dram Type= 6, Freq= 0, CH_0, rank 0
6301 22:54:08.932269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6302 22:54:08.935516 ==
6303 22:54:08.938289 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6304 22:54:08.945164 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6305 22:54:08.948617 [CA 0] Center 36 (8~64) winsize 57
6306 22:54:08.951626 [CA 1] Center 36 (8~64) winsize 57
6307 22:54:08.955042 [CA 2] Center 36 (8~64) winsize 57
6308 22:54:08.958424 [CA 3] Center 36 (8~64) winsize 57
6309 22:54:08.961545 [CA 4] Center 36 (8~64) winsize 57
6310 22:54:08.965096 [CA 5] Center 36 (8~64) winsize 57
6311 22:54:08.965687
6312 22:54:08.968304 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6313 22:54:08.968824
6314 22:54:08.971799 [CATrainingPosCal] consider 1 rank data
6315 22:54:08.975233 u2DelayCellTimex100 = 270/100 ps
6316 22:54:08.978554 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6317 22:54:08.981833 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6318 22:54:08.984794 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6319 22:54:08.988192 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6320 22:54:08.991408 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6321 22:54:08.994924 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6322 22:54:08.995345
6323 22:54:09.001245 CA PerBit enable=1, Macro0, CA PI delay=36
6324 22:54:09.001788
6325 22:54:09.002152 [CBTSetCACLKResult] CA Dly = 36
6326 22:54:09.004666 CS Dly: 1 (0~32)
6327 22:54:09.005080 ==
6328 22:54:09.007873 Dram Type= 6, Freq= 0, CH_0, rank 1
6329 22:54:09.011155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6330 22:54:09.011577 ==
6331 22:54:09.018219 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6332 22:54:09.024230 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6333 22:54:09.028141 [CA 0] Center 36 (8~64) winsize 57
6334 22:54:09.030591 [CA 1] Center 36 (8~64) winsize 57
6335 22:54:09.034056 [CA 2] Center 36 (8~64) winsize 57
6336 22:54:09.037513 [CA 3] Center 36 (8~64) winsize 57
6337 22:54:09.040676 [CA 4] Center 36 (8~64) winsize 57
6338 22:54:09.041095 [CA 5] Center 36 (8~64) winsize 57
6339 22:54:09.044264
6340 22:54:09.047238 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6341 22:54:09.047813
6342 22:54:09.050407 [CATrainingPosCal] consider 2 rank data
6343 22:54:09.053729 u2DelayCellTimex100 = 270/100 ps
6344 22:54:09.057190 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6345 22:54:09.060638 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6346 22:54:09.063988 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6347 22:54:09.067463 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6348 22:54:09.070733 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6349 22:54:09.073839 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6350 22:54:09.074293
6351 22:54:09.077575 CA PerBit enable=1, Macro0, CA PI delay=36
6352 22:54:09.080698
6353 22:54:09.081246 [CBTSetCACLKResult] CA Dly = 36
6354 22:54:09.083758 CS Dly: 1 (0~32)
6355 22:54:09.084309
6356 22:54:09.086812 ----->DramcWriteLeveling(PI) begin...
6357 22:54:09.087284 ==
6358 22:54:09.090148 Dram Type= 6, Freq= 0, CH_0, rank 0
6359 22:54:09.093285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6360 22:54:09.093774 ==
6361 22:54:09.097305 Write leveling (Byte 0): 40 => 8
6362 22:54:09.100447 Write leveling (Byte 1): 32 => 0
6363 22:54:09.103212 DramcWriteLeveling(PI) end<-----
6364 22:54:09.103714
6365 22:54:09.104076 ==
6366 22:54:09.106428 Dram Type= 6, Freq= 0, CH_0, rank 0
6367 22:54:09.110245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6368 22:54:09.113075 ==
6369 22:54:09.113706 [Gating] SW mode calibration
6370 22:54:09.123000 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6371 22:54:09.125870 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6372 22:54:09.129364 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6373 22:54:09.135709 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6374 22:54:09.139364 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6375 22:54:09.142344 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6376 22:54:09.149054 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6377 22:54:09.153065 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6378 22:54:09.155825 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6379 22:54:09.162020 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6380 22:54:09.165841 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6381 22:54:09.168567 Total UI for P1: 0, mck2ui 16
6382 22:54:09.172101 best dqsien dly found for B0: ( 0, 14, 24)
6383 22:54:09.175221 Total UI for P1: 0, mck2ui 16
6384 22:54:09.179075 best dqsien dly found for B1: ( 0, 14, 24)
6385 22:54:09.182327 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6386 22:54:09.185559 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6387 22:54:09.185969
6388 22:54:09.188845 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6389 22:54:09.195102 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6390 22:54:09.195526 [Gating] SW calibration Done
6391 22:54:09.198401 ==
6392 22:54:09.198826 Dram Type= 6, Freq= 0, CH_0, rank 0
6393 22:54:09.205277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6394 22:54:09.205731 ==
6395 22:54:09.206076 RX Vref Scan: 0
6396 22:54:09.206379
6397 22:54:09.208179 RX Vref 0 -> 0, step: 1
6398 22:54:09.208589
6399 22:54:09.211588 RX Delay -410 -> 252, step: 16
6400 22:54:09.215205 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6401 22:54:09.218112 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6402 22:54:09.224640 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6403 22:54:09.227893 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6404 22:54:09.231234 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6405 22:54:09.234554 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6406 22:54:09.241662 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6407 22:54:09.244605 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6408 22:54:09.247987 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6409 22:54:09.254531 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6410 22:54:09.257729 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6411 22:54:09.261112 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6412 22:54:09.264431 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6413 22:54:09.271024 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6414 22:54:09.274232 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6415 22:54:09.277861 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6416 22:54:09.278274 ==
6417 22:54:09.280639 Dram Type= 6, Freq= 0, CH_0, rank 0
6418 22:54:09.287436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6419 22:54:09.287852 ==
6420 22:54:09.288171 DQS Delay:
6421 22:54:09.290962 DQS0 = 43, DQS1 = 59
6422 22:54:09.291465 DQM Delay:
6423 22:54:09.291793 DQM0 = 10, DQM1 = 13
6424 22:54:09.294225 DQ Delay:
6425 22:54:09.297684 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6426 22:54:09.298212 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6427 22:54:09.300529 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6428 22:54:09.303781 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6429 22:54:09.304206
6430 22:54:09.307460
6431 22:54:09.307961 ==
6432 22:54:09.310663 Dram Type= 6, Freq= 0, CH_0, rank 0
6433 22:54:09.314014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6434 22:54:09.314431 ==
6435 22:54:09.314755
6436 22:54:09.315054
6437 22:54:09.317296 TX Vref Scan disable
6438 22:54:09.317831 == TX Byte 0 ==
6439 22:54:09.320844 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6440 22:54:09.326961 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6441 22:54:09.327449 == TX Byte 1 ==
6442 22:54:09.330566 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6443 22:54:09.336790 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6444 22:54:09.337296 ==
6445 22:54:09.340170 Dram Type= 6, Freq= 0, CH_0, rank 0
6446 22:54:09.343728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6447 22:54:09.344145 ==
6448 22:54:09.344465
6449 22:54:09.344763
6450 22:54:09.347175 TX Vref Scan disable
6451 22:54:09.347633 == TX Byte 0 ==
6452 22:54:09.353098 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6453 22:54:09.356624 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6454 22:54:09.357072 == TX Byte 1 ==
6455 22:54:09.363268 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6456 22:54:09.366507 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6457 22:54:09.366917
6458 22:54:09.367234 [DATLAT]
6459 22:54:09.369671 Freq=400, CH0 RK0
6460 22:54:09.370080
6461 22:54:09.370397 DATLAT Default: 0xf
6462 22:54:09.372773 0, 0xFFFF, sum = 0
6463 22:54:09.373189 1, 0xFFFF, sum = 0
6464 22:54:09.376357 2, 0xFFFF, sum = 0
6465 22:54:09.376772 3, 0xFFFF, sum = 0
6466 22:54:09.379915 4, 0xFFFF, sum = 0
6467 22:54:09.380433 5, 0xFFFF, sum = 0
6468 22:54:09.382980 6, 0xFFFF, sum = 0
6469 22:54:09.383497 7, 0xFFFF, sum = 0
6470 22:54:09.386437 8, 0xFFFF, sum = 0
6471 22:54:09.389525 9, 0xFFFF, sum = 0
6472 22:54:09.389968 10, 0xFFFF, sum = 0
6473 22:54:09.393617 11, 0xFFFF, sum = 0
6474 22:54:09.394151 12, 0xFFFF, sum = 0
6475 22:54:09.396513 13, 0x0, sum = 1
6476 22:54:09.396945 14, 0x0, sum = 2
6477 22:54:09.399823 15, 0x0, sum = 3
6478 22:54:09.400359 16, 0x0, sum = 4
6479 22:54:09.400810 best_step = 14
6480 22:54:09.402971
6481 22:54:09.403397 ==
6482 22:54:09.405983 Dram Type= 6, Freq= 0, CH_0, rank 0
6483 22:54:09.409762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6484 22:54:09.410236 ==
6485 22:54:09.410711 RX Vref Scan: 1
6486 22:54:09.411158
6487 22:54:09.412992 RX Vref 0 -> 0, step: 1
6488 22:54:09.413502
6489 22:54:09.415774 RX Delay -359 -> 252, step: 8
6490 22:54:09.416245
6491 22:54:09.419755 Set Vref, RX VrefLevel [Byte0]: 56
6492 22:54:09.422705 [Byte1]: 50
6493 22:54:09.426567
6494 22:54:09.427086 Final RX Vref Byte 0 = 56 to rank0
6495 22:54:09.429989 Final RX Vref Byte 1 = 50 to rank0
6496 22:54:09.433857 Final RX Vref Byte 0 = 56 to rank1
6497 22:54:09.436748 Final RX Vref Byte 1 = 50 to rank1==
6498 22:54:09.439762 Dram Type= 6, Freq= 0, CH_0, rank 0
6499 22:54:09.446606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6500 22:54:09.447052 ==
6501 22:54:09.447483 DQS Delay:
6502 22:54:09.449502 DQS0 = 44, DQS1 = 60
6503 22:54:09.449932 DQM Delay:
6504 22:54:09.450368 DQM0 = 8, DQM1 = 12
6505 22:54:09.452782 DQ Delay:
6506 22:54:09.456100 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =4
6507 22:54:09.456532 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6508 22:54:09.459467 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6509 22:54:09.462859 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6510 22:54:09.463385
6511 22:54:09.466498
6512 22:54:09.472538 [DQSOSCAuto] RK0, (LSB)MR18= 0xc184, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 385 ps
6513 22:54:09.476220 CH0 RK0: MR19=C0C, MR18=C184
6514 22:54:09.483103 CH0_RK0: MR19=0xC0C, MR18=0xC184, DQSOSC=385, MR23=63, INC=398, DEC=265
6515 22:54:09.483652 ==
6516 22:54:09.485734 Dram Type= 6, Freq= 0, CH_0, rank 1
6517 22:54:09.489644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6518 22:54:09.490201 ==
6519 22:54:09.492490 [Gating] SW mode calibration
6520 22:54:09.499486 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6521 22:54:09.505730 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6522 22:54:09.508900 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6523 22:54:09.512378 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6524 22:54:09.519090 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6525 22:54:09.522173 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6526 22:54:09.525513 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6527 22:54:09.532120 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6528 22:54:09.535624 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6529 22:54:09.538550 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6530 22:54:09.544892 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6531 22:54:09.548531 Total UI for P1: 0, mck2ui 16
6532 22:54:09.552236 best dqsien dly found for B0: ( 0, 14, 24)
6533 22:54:09.552714 Total UI for P1: 0, mck2ui 16
6534 22:54:09.558155 best dqsien dly found for B1: ( 0, 14, 24)
6535 22:54:09.561903 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6536 22:54:09.564964 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6537 22:54:09.565576
6538 22:54:09.568533 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6539 22:54:09.571295 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6540 22:54:09.575040 [Gating] SW calibration Done
6541 22:54:09.575514 ==
6542 22:54:09.577887 Dram Type= 6, Freq= 0, CH_0, rank 1
6543 22:54:09.581351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6544 22:54:09.581834 ==
6545 22:54:09.584418 RX Vref Scan: 0
6546 22:54:09.584891
6547 22:54:09.587794 RX Vref 0 -> 0, step: 1
6548 22:54:09.588284
6549 22:54:09.588755 RX Delay -410 -> 252, step: 16
6550 22:54:09.595046 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6551 22:54:09.598250 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6552 22:54:09.601265 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6553 22:54:09.608222 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6554 22:54:09.611325 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6555 22:54:09.614463 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6556 22:54:09.618261 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6557 22:54:09.624377 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6558 22:54:09.627490 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6559 22:54:09.630658 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6560 22:54:09.634191 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6561 22:54:09.640393 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6562 22:54:09.643984 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6563 22:54:09.647279 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6564 22:54:09.650291 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6565 22:54:09.657421 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6566 22:54:09.658044 ==
6567 22:54:09.660781 Dram Type= 6, Freq= 0, CH_0, rank 1
6568 22:54:09.664010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6569 22:54:09.664575 ==
6570 22:54:09.667386 DQS Delay:
6571 22:54:09.667948 DQS0 = 43, DQS1 = 59
6572 22:54:09.668316 DQM Delay:
6573 22:54:09.670754 DQM0 = 12, DQM1 = 16
6574 22:54:09.671332 DQ Delay:
6575 22:54:09.673927 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6576 22:54:09.677030 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6577 22:54:09.680151 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6578 22:54:09.683739 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6579 22:54:09.684198
6580 22:54:09.684554
6581 22:54:09.684888 ==
6582 22:54:09.686732 Dram Type= 6, Freq= 0, CH_0, rank 1
6583 22:54:09.690012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6584 22:54:09.690479 ==
6585 22:54:09.693761
6586 22:54:09.694216
6587 22:54:09.694578 TX Vref Scan disable
6588 22:54:09.696661 == TX Byte 0 ==
6589 22:54:09.700306 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6590 22:54:09.703664 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6591 22:54:09.706602 == TX Byte 1 ==
6592 22:54:09.710311 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6593 22:54:09.713494 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6594 22:54:09.714057 ==
6595 22:54:09.716617 Dram Type= 6, Freq= 0, CH_0, rank 1
6596 22:54:09.720143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6597 22:54:09.723121 ==
6598 22:54:09.723688
6599 22:54:09.724170
6600 22:54:09.724612 TX Vref Scan disable
6601 22:54:09.726395 == TX Byte 0 ==
6602 22:54:09.729729 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6603 22:54:09.733513 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6604 22:54:09.736601 == TX Byte 1 ==
6605 22:54:09.739983 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6606 22:54:09.742818 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6607 22:54:09.743287
6608 22:54:09.746624 [DATLAT]
6609 22:54:09.747188 Freq=400, CH0 RK1
6610 22:54:09.747676
6611 22:54:09.749490 DATLAT Default: 0xe
6612 22:54:09.749961 0, 0xFFFF, sum = 0
6613 22:54:09.753380 1, 0xFFFF, sum = 0
6614 22:54:09.753872 2, 0xFFFF, sum = 0
6615 22:54:09.756202 3, 0xFFFF, sum = 0
6616 22:54:09.756679 4, 0xFFFF, sum = 0
6617 22:54:09.759341 5, 0xFFFF, sum = 0
6618 22:54:09.759833 6, 0xFFFF, sum = 0
6619 22:54:09.763055 7, 0xFFFF, sum = 0
6620 22:54:09.763631 8, 0xFFFF, sum = 0
6621 22:54:09.766242 9, 0xFFFF, sum = 0
6622 22:54:09.766767 10, 0xFFFF, sum = 0
6623 22:54:09.769172 11, 0xFFFF, sum = 0
6624 22:54:09.772580 12, 0xFFFF, sum = 0
6625 22:54:09.773155 13, 0x0, sum = 1
6626 22:54:09.773698 14, 0x0, sum = 2
6627 22:54:09.776200 15, 0x0, sum = 3
6628 22:54:09.776772 16, 0x0, sum = 4
6629 22:54:09.779028 best_step = 14
6630 22:54:09.779538
6631 22:54:09.780010 ==
6632 22:54:09.782478 Dram Type= 6, Freq= 0, CH_0, rank 1
6633 22:54:09.785852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6634 22:54:09.786325 ==
6635 22:54:09.789224 RX Vref Scan: 0
6636 22:54:09.789749
6637 22:54:09.790379 RX Vref 0 -> 0, step: 1
6638 22:54:09.792219
6639 22:54:09.792639 RX Delay -359 -> 252, step: 8
6640 22:54:09.801001 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6641 22:54:09.804208 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6642 22:54:09.807597 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6643 22:54:09.810727 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6644 22:54:09.817098 iDelay=217, Bit 4, Center -40 (-279 ~ 200) 480
6645 22:54:09.820756 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6646 22:54:09.823890 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6647 22:54:09.830593 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6648 22:54:09.834037 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6649 22:54:09.836815 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6650 22:54:09.840171 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6651 22:54:09.847139 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6652 22:54:09.850409 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6653 22:54:09.853475 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6654 22:54:09.856896 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6655 22:54:09.863427 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6656 22:54:09.863859 ==
6657 22:54:09.866262 Dram Type= 6, Freq= 0, CH_0, rank 1
6658 22:54:09.870017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6659 22:54:09.870434 ==
6660 22:54:09.873166 DQS Delay:
6661 22:54:09.873624 DQS0 = 44, DQS1 = 60
6662 22:54:09.873953 DQM Delay:
6663 22:54:09.876954 DQM0 = 7, DQM1 = 14
6664 22:54:09.877403 DQ Delay:
6665 22:54:09.880337 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =8
6666 22:54:09.883418 DQ4 =4, DQ5 =0, DQ6 =16, DQ7 =16
6667 22:54:09.886131 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6668 22:54:09.889614 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6669 22:54:09.890029
6670 22:54:09.890349
6671 22:54:09.896510 [DQSOSCAuto] RK1, (LSB)MR18= 0xb744, (MSB)MR19= 0xc0c, tDQSOscB0 = 401 ps tDQSOscB1 = 387 ps
6672 22:54:09.899328 CH0 RK1: MR19=C0C, MR18=B744
6673 22:54:09.906366 CH0_RK1: MR19=0xC0C, MR18=0xB744, DQSOSC=387, MR23=63, INC=394, DEC=262
6674 22:54:09.909401 [RxdqsGatingPostProcess] freq 400
6675 22:54:09.915722 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6676 22:54:09.919143 best DQS0 dly(2T, 0.5T) = (0, 10)
6677 22:54:09.922495 best DQS1 dly(2T, 0.5T) = (0, 10)
6678 22:54:09.925704 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6679 22:54:09.928854 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6680 22:54:09.932394 best DQS0 dly(2T, 0.5T) = (0, 10)
6681 22:54:09.932827 best DQS1 dly(2T, 0.5T) = (0, 10)
6682 22:54:09.935501 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6683 22:54:09.938949 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6684 22:54:09.942557 Pre-setting of DQS Precalculation
6685 22:54:09.948650 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6686 22:54:09.949089 ==
6687 22:54:09.952394 Dram Type= 6, Freq= 0, CH_1, rank 0
6688 22:54:09.955146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6689 22:54:09.955560 ==
6690 22:54:09.962032 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6691 22:54:09.968325 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6692 22:54:09.971805 [CA 0] Center 36 (8~64) winsize 57
6693 22:54:09.975110 [CA 1] Center 36 (8~64) winsize 57
6694 22:54:09.978531 [CA 2] Center 36 (8~64) winsize 57
6695 22:54:09.981501 [CA 3] Center 36 (8~64) winsize 57
6696 22:54:09.981914 [CA 4] Center 36 (8~64) winsize 57
6697 22:54:09.985420 [CA 5] Center 36 (8~64) winsize 57
6698 22:54:09.985933
6699 22:54:09.991433 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6700 22:54:09.991850
6701 22:54:09.995123 [CATrainingPosCal] consider 1 rank data
6702 22:54:09.998187 u2DelayCellTimex100 = 270/100 ps
6703 22:54:10.001787 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6704 22:54:10.004792 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6705 22:54:10.008064 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6706 22:54:10.011463 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6707 22:54:10.014989 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6708 22:54:10.018015 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6709 22:54:10.018573
6710 22:54:10.021733 CA PerBit enable=1, Macro0, CA PI delay=36
6711 22:54:10.022298
6712 22:54:10.024607 [CBTSetCACLKResult] CA Dly = 36
6713 22:54:10.027914 CS Dly: 1 (0~32)
6714 22:54:10.028487 ==
6715 22:54:10.030931 Dram Type= 6, Freq= 0, CH_1, rank 1
6716 22:54:10.034894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6717 22:54:10.035354 ==
6718 22:54:10.040926 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6719 22:54:10.047690 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6720 22:54:10.050935 [CA 0] Center 36 (8~64) winsize 57
6721 22:54:10.054305 [CA 1] Center 36 (8~64) winsize 57
6722 22:54:10.057516 [CA 2] Center 36 (8~64) winsize 57
6723 22:54:10.057977 [CA 3] Center 36 (8~64) winsize 57
6724 22:54:10.060681 [CA 4] Center 36 (8~64) winsize 57
6725 22:54:10.064011 [CA 5] Center 36 (8~64) winsize 57
6726 22:54:10.064568
6727 22:54:10.070821 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6728 22:54:10.071413
6729 22:54:10.073919 [CATrainingPosCal] consider 2 rank data
6730 22:54:10.077367 u2DelayCellTimex100 = 270/100 ps
6731 22:54:10.080330 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6732 22:54:10.084055 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6733 22:54:10.087192 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6734 22:54:10.090500 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6735 22:54:10.093930 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6736 22:54:10.097101 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6737 22:54:10.097748
6738 22:54:10.100277 CA PerBit enable=1, Macro0, CA PI delay=36
6739 22:54:10.100769
6740 22:54:10.103937 [CBTSetCACLKResult] CA Dly = 36
6741 22:54:10.106964 CS Dly: 1 (0~32)
6742 22:54:10.107473
6743 22:54:10.110662 ----->DramcWriteLeveling(PI) begin...
6744 22:54:10.111314 ==
6745 22:54:10.113548 Dram Type= 6, Freq= 0, CH_1, rank 0
6746 22:54:10.116893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6747 22:54:10.117376 ==
6748 22:54:10.121059 Write leveling (Byte 0): 40 => 8
6749 22:54:10.123572 Write leveling (Byte 1): 32 => 0
6750 22:54:10.126799 DramcWriteLeveling(PI) end<-----
6751 22:54:10.127263
6752 22:54:10.127673 ==
6753 22:54:10.130167 Dram Type= 6, Freq= 0, CH_1, rank 0
6754 22:54:10.133878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6755 22:54:10.134379 ==
6756 22:54:10.137080 [Gating] SW mode calibration
6757 22:54:10.143289 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6758 22:54:10.149948 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6759 22:54:10.153005 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6760 22:54:10.156305 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6761 22:54:10.162706 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6762 22:54:10.166342 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6763 22:54:10.172816 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6764 22:54:10.176459 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6765 22:54:10.179751 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6766 22:54:10.186521 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6767 22:54:10.189262 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6768 22:54:10.192794 Total UI for P1: 0, mck2ui 16
6769 22:54:10.195951 best dqsien dly found for B0: ( 0, 14, 24)
6770 22:54:10.199128 Total UI for P1: 0, mck2ui 16
6771 22:54:10.203194 best dqsien dly found for B1: ( 0, 14, 24)
6772 22:54:10.206008 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6773 22:54:10.209217 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6774 22:54:10.209801
6775 22:54:10.212472 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6776 22:54:10.215438 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6777 22:54:10.219159 [Gating] SW calibration Done
6778 22:54:10.219677 ==
6779 22:54:10.222327 Dram Type= 6, Freq= 0, CH_1, rank 0
6780 22:54:10.228484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6781 22:54:10.228997 ==
6782 22:54:10.229349 RX Vref Scan: 0
6783 22:54:10.229672
6784 22:54:10.231849 RX Vref 0 -> 0, step: 1
6785 22:54:10.232374
6786 22:54:10.235426 RX Delay -410 -> 252, step: 16
6787 22:54:10.238487 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6788 22:54:10.241523 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6789 22:54:10.248295 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6790 22:54:10.251381 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6791 22:54:10.254991 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6792 22:54:10.258126 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6793 22:54:10.264585 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6794 22:54:10.268302 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6795 22:54:10.271271 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6796 22:54:10.274973 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6797 22:54:10.281707 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6798 22:54:10.284808 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6799 22:54:10.288167 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6800 22:54:10.291045 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6801 22:54:10.297705 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6802 22:54:10.301026 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6803 22:54:10.301525 ==
6804 22:54:10.304230 Dram Type= 6, Freq= 0, CH_1, rank 0
6805 22:54:10.307585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6806 22:54:10.308141 ==
6807 22:54:10.311314 DQS Delay:
6808 22:54:10.311873 DQS0 = 43, DQS1 = 51
6809 22:54:10.314094 DQM Delay:
6810 22:54:10.314640 DQM0 = 12, DQM1 = 14
6811 22:54:10.317610 DQ Delay:
6812 22:54:10.318138 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6813 22:54:10.320672 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6814 22:54:10.324403 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6815 22:54:10.327144 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6816 22:54:10.327697
6817 22:54:10.328057
6818 22:54:10.328388 ==
6819 22:54:10.330570 Dram Type= 6, Freq= 0, CH_1, rank 0
6820 22:54:10.337177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6821 22:54:10.337786 ==
6822 22:54:10.338155
6823 22:54:10.338485
6824 22:54:10.338803 TX Vref Scan disable
6825 22:54:10.340242 == TX Byte 0 ==
6826 22:54:10.343534 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6827 22:54:10.347271 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6828 22:54:10.350765 == TX Byte 1 ==
6829 22:54:10.353740 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6830 22:54:10.357410 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6831 22:54:10.360735 ==
6832 22:54:10.363364 Dram Type= 6, Freq= 0, CH_1, rank 0
6833 22:54:10.367000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6834 22:54:10.367461 ==
6835 22:54:10.367849
6836 22:54:10.368182
6837 22:54:10.370384 TX Vref Scan disable
6838 22:54:10.370872 == TX Byte 0 ==
6839 22:54:10.373498 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6840 22:54:10.379950 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6841 22:54:10.380500 == TX Byte 1 ==
6842 22:54:10.383309 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6843 22:54:10.389598 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6844 22:54:10.390141
6845 22:54:10.390498 [DATLAT]
6846 22:54:10.393306 Freq=400, CH1 RK0
6847 22:54:10.393828
6848 22:54:10.394188 DATLAT Default: 0xf
6849 22:54:10.396252 0, 0xFFFF, sum = 0
6850 22:54:10.396712 1, 0xFFFF, sum = 0
6851 22:54:10.399907 2, 0xFFFF, sum = 0
6852 22:54:10.400471 3, 0xFFFF, sum = 0
6853 22:54:10.403168 4, 0xFFFF, sum = 0
6854 22:54:10.403729 5, 0xFFFF, sum = 0
6855 22:54:10.406106 6, 0xFFFF, sum = 0
6856 22:54:10.406697 7, 0xFFFF, sum = 0
6857 22:54:10.409644 8, 0xFFFF, sum = 0
6858 22:54:10.410113 9, 0xFFFF, sum = 0
6859 22:54:10.412633 10, 0xFFFF, sum = 0
6860 22:54:10.413100 11, 0xFFFF, sum = 0
6861 22:54:10.415921 12, 0xFFFF, sum = 0
6862 22:54:10.416387 13, 0x0, sum = 1
6863 22:54:10.419424 14, 0x0, sum = 2
6864 22:54:10.419894 15, 0x0, sum = 3
6865 22:54:10.422917 16, 0x0, sum = 4
6866 22:54:10.423575 best_step = 14
6867 22:54:10.423949
6868 22:54:10.424285 ==
6869 22:54:10.425888 Dram Type= 6, Freq= 0, CH_1, rank 0
6870 22:54:10.432562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6871 22:54:10.433026 ==
6872 22:54:10.433417 RX Vref Scan: 1
6873 22:54:10.433762
6874 22:54:10.436174 RX Vref 0 -> 0, step: 1
6875 22:54:10.436743
6876 22:54:10.439103 RX Delay -343 -> 252, step: 8
6877 22:54:10.439567
6878 22:54:10.442746 Set Vref, RX VrefLevel [Byte0]: 50
6879 22:54:10.445654 [Byte1]: 52
6880 22:54:10.449259
6881 22:54:10.449861 Final RX Vref Byte 0 = 50 to rank0
6882 22:54:10.452531 Final RX Vref Byte 1 = 52 to rank0
6883 22:54:10.456205 Final RX Vref Byte 0 = 50 to rank1
6884 22:54:10.459142 Final RX Vref Byte 1 = 52 to rank1==
6885 22:54:10.462044 Dram Type= 6, Freq= 0, CH_1, rank 0
6886 22:54:10.469117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6887 22:54:10.469752 ==
6888 22:54:10.470129 DQS Delay:
6889 22:54:10.472207 DQS0 = 44, DQS1 = 56
6890 22:54:10.472666 DQM Delay:
6891 22:54:10.473026 DQM0 = 7, DQM1 = 12
6892 22:54:10.475472 DQ Delay:
6893 22:54:10.478800 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6894 22:54:10.482018 DQ4 =4, DQ5 =16, DQ6 =16, DQ7 =4
6895 22:54:10.482482 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6896 22:54:10.485133 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =20
6897 22:54:10.488464
6898 22:54:10.488934
6899 22:54:10.495414 [DQSOSCAuto] RK0, (LSB)MR18= 0x956c, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 391 ps
6900 22:54:10.498946 CH1 RK0: MR19=C0C, MR18=956C
6901 22:54:10.505577 CH1_RK0: MR19=0xC0C, MR18=0x956C, DQSOSC=391, MR23=63, INC=386, DEC=257
6902 22:54:10.506131 ==
6903 22:54:10.508729 Dram Type= 6, Freq= 0, CH_1, rank 1
6904 22:54:10.512096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6905 22:54:10.512661 ==
6906 22:54:10.515121 [Gating] SW mode calibration
6907 22:54:10.521934 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6908 22:54:10.528564 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6909 22:54:10.531869 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6910 22:54:10.535220 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6911 22:54:10.541962 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6912 22:54:10.544860 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6913 22:54:10.548648 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6914 22:54:10.555344 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6915 22:54:10.558337 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6916 22:54:10.561949 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6917 22:54:10.568046 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6918 22:54:10.568512 Total UI for P1: 0, mck2ui 16
6919 22:54:10.574697 best dqsien dly found for B0: ( 0, 14, 24)
6920 22:54:10.575159 Total UI for P1: 0, mck2ui 16
6921 22:54:10.581193 best dqsien dly found for B1: ( 0, 14, 24)
6922 22:54:10.584720 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6923 22:54:10.587658 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6924 22:54:10.588119
6925 22:54:10.590812 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6926 22:54:10.594276 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6927 22:54:10.597353 [Gating] SW calibration Done
6928 22:54:10.597817 ==
6929 22:54:10.600931 Dram Type= 6, Freq= 0, CH_1, rank 1
6930 22:54:10.604173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6931 22:54:10.604703 ==
6932 22:54:10.607497 RX Vref Scan: 0
6933 22:54:10.607954
6934 22:54:10.608314 RX Vref 0 -> 0, step: 1
6935 22:54:10.610924
6936 22:54:10.611417 RX Delay -410 -> 252, step: 16
6937 22:54:10.617496 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6938 22:54:10.620431 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6939 22:54:10.624433 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6940 22:54:10.627587 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6941 22:54:10.633880 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6942 22:54:10.637179 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6943 22:54:10.640783 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6944 22:54:10.644275 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6945 22:54:10.650353 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6946 22:54:10.653518 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6947 22:54:10.656998 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6948 22:54:10.663375 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6949 22:54:10.666633 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6950 22:54:10.670407 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6951 22:54:10.673535 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6952 22:54:10.679965 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6953 22:54:10.680530 ==
6954 22:54:10.683432 Dram Type= 6, Freq= 0, CH_1, rank 1
6955 22:54:10.687267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6956 22:54:10.687831 ==
6957 22:54:10.688196 DQS Delay:
6958 22:54:10.689716 DQS0 = 43, DQS1 = 51
6959 22:54:10.690177 DQM Delay:
6960 22:54:10.693428 DQM0 = 12, DQM1 = 12
6961 22:54:10.693888 DQ Delay:
6962 22:54:10.696532 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6963 22:54:10.699817 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6964 22:54:10.703037 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6965 22:54:10.706208 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6966 22:54:10.706771
6967 22:54:10.707130
6968 22:54:10.707463 ==
6969 22:54:10.709931 Dram Type= 6, Freq= 0, CH_1, rank 1
6970 22:54:10.712826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6971 22:54:10.713286 ==
6972 22:54:10.713681
6973 22:54:10.714012
6974 22:54:10.716581 TX Vref Scan disable
6975 22:54:10.719776 == TX Byte 0 ==
6976 22:54:10.723080 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6977 22:54:10.726521 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6978 22:54:10.729203 == TX Byte 1 ==
6979 22:54:10.733108 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6980 22:54:10.736355 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6981 22:54:10.736815 ==
6982 22:54:10.739387 Dram Type= 6, Freq= 0, CH_1, rank 1
6983 22:54:10.742774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6984 22:54:10.743242 ==
6985 22:54:10.745922
6986 22:54:10.746457
6987 22:54:10.746827 TX Vref Scan disable
6988 22:54:10.749047 == TX Byte 0 ==
6989 22:54:10.752789 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6990 22:54:10.756083 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6991 22:54:10.759357 == TX Byte 1 ==
6992 22:54:10.762595 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6993 22:54:10.765608 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6994 22:54:10.766101
6995 22:54:10.766459 [DATLAT]
6996 22:54:10.769558 Freq=400, CH1 RK1
6997 22:54:10.770113
6998 22:54:10.772580 DATLAT Default: 0xe
6999 22:54:10.773145 0, 0xFFFF, sum = 0
7000 22:54:10.775845 1, 0xFFFF, sum = 0
7001 22:54:10.776418 2, 0xFFFF, sum = 0
7002 22:54:10.779164 3, 0xFFFF, sum = 0
7003 22:54:10.779755 4, 0xFFFF, sum = 0
7004 22:54:10.781999 5, 0xFFFF, sum = 0
7005 22:54:10.782472 6, 0xFFFF, sum = 0
7006 22:54:10.785819 7, 0xFFFF, sum = 0
7007 22:54:10.786282 8, 0xFFFF, sum = 0
7008 22:54:10.788503 9, 0xFFFF, sum = 0
7009 22:54:10.788964 10, 0xFFFF, sum = 0
7010 22:54:10.792235 11, 0xFFFF, sum = 0
7011 22:54:10.792697 12, 0xFFFF, sum = 0
7012 22:54:10.795540 13, 0x0, sum = 1
7013 22:54:10.796002 14, 0x0, sum = 2
7014 22:54:10.798562 15, 0x0, sum = 3
7015 22:54:10.799023 16, 0x0, sum = 4
7016 22:54:10.802146 best_step = 14
7017 22:54:10.802556
7018 22:54:10.802877 ==
7019 22:54:10.805308 Dram Type= 6, Freq= 0, CH_1, rank 1
7020 22:54:10.808394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7021 22:54:10.808810 ==
7022 22:54:10.812325 RX Vref Scan: 0
7023 22:54:10.812836
7024 22:54:10.813161 RX Vref 0 -> 0, step: 1
7025 22:54:10.813527
7026 22:54:10.815316 RX Delay -343 -> 252, step: 8
7027 22:54:10.823314 iDelay=225, Bit 0, Center -28 (-271 ~ 216) 488
7028 22:54:10.826670 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
7029 22:54:10.829905 iDelay=225, Bit 2, Center -44 (-287 ~ 200) 488
7030 22:54:10.836560 iDelay=225, Bit 3, Center -40 (-279 ~ 200) 480
7031 22:54:10.839652 iDelay=225, Bit 4, Center -40 (-287 ~ 208) 496
7032 22:54:10.842839 iDelay=225, Bit 5, Center -28 (-271 ~ 216) 488
7033 22:54:10.846254 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
7034 22:54:10.852989 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
7035 22:54:10.856330 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
7036 22:54:10.859510 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
7037 22:54:10.862856 iDelay=225, Bit 10, Center -48 (-295 ~ 200) 496
7038 22:54:10.869356 iDelay=225, Bit 11, Center -52 (-295 ~ 192) 488
7039 22:54:10.872708 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
7040 22:54:10.876193 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
7041 22:54:10.879630 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
7042 22:54:10.886540 iDelay=225, Bit 15, Center -36 (-287 ~ 216) 504
7043 22:54:10.887133 ==
7044 22:54:10.889531 Dram Type= 6, Freq= 0, CH_1, rank 1
7045 22:54:10.892844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7046 22:54:10.893492 ==
7047 22:54:10.893870 DQS Delay:
7048 22:54:10.896045 DQS0 = 44, DQS1 = 56
7049 22:54:10.896603 DQM Delay:
7050 22:54:10.899092 DQM0 = 8, DQM1 = 10
7051 22:54:10.899549 DQ Delay:
7052 22:54:10.902753 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =4
7053 22:54:10.905923 DQ4 =4, DQ5 =16, DQ6 =20, DQ7 =4
7054 22:54:10.908972 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
7055 22:54:10.912166 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
7056 22:54:10.912625
7057 22:54:10.912986
7058 22:54:10.919123 [DQSOSCAuto] RK1, (LSB)MR18= 0x6455, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 397 ps
7059 22:54:10.922712 CH1 RK1: MR19=C0C, MR18=6455
7060 22:54:10.929196 CH1_RK1: MR19=0xC0C, MR18=0x6455, DQSOSC=397, MR23=63, INC=374, DEC=249
7061 22:54:10.932646 [RxdqsGatingPostProcess] freq 400
7062 22:54:10.938989 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7063 22:54:10.942195 best DQS0 dly(2T, 0.5T) = (0, 10)
7064 22:54:10.945105 best DQS1 dly(2T, 0.5T) = (0, 10)
7065 22:54:10.948894 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7066 22:54:10.951667 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7067 22:54:10.952127 best DQS0 dly(2T, 0.5T) = (0, 10)
7068 22:54:10.954970 best DQS1 dly(2T, 0.5T) = (0, 10)
7069 22:54:10.958450 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7070 22:54:10.962003 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7071 22:54:10.965544 Pre-setting of DQS Precalculation
7072 22:54:10.971384 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7073 22:54:10.978425 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7074 22:54:10.984979 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7075 22:54:10.985451
7076 22:54:10.985785
7077 22:54:10.988157 [Calibration Summary] 800 Mbps
7078 22:54:10.988574 CH 0, Rank 0
7079 22:54:10.991551 SW Impedance : PASS
7080 22:54:10.994470 DUTY Scan : NO K
7081 22:54:10.994888 ZQ Calibration : PASS
7082 22:54:10.997888 Jitter Meter : NO K
7083 22:54:11.001192 CBT Training : PASS
7084 22:54:11.001660 Write leveling : PASS
7085 22:54:11.004344 RX DQS gating : PASS
7086 22:54:11.007860 RX DQ/DQS(RDDQC) : PASS
7087 22:54:11.008275 TX DQ/DQS : PASS
7088 22:54:11.011118 RX DATLAT : PASS
7089 22:54:11.014399 RX DQ/DQS(Engine): PASS
7090 22:54:11.014817 TX OE : NO K
7091 22:54:11.017359 All Pass.
7092 22:54:11.017779
7093 22:54:11.018103 CH 0, Rank 1
7094 22:54:11.020901 SW Impedance : PASS
7095 22:54:11.021317 DUTY Scan : NO K
7096 22:54:11.024306 ZQ Calibration : PASS
7097 22:54:11.027403 Jitter Meter : NO K
7098 22:54:11.027821 CBT Training : PASS
7099 22:54:11.031022 Write leveling : NO K
7100 22:54:11.034114 RX DQS gating : PASS
7101 22:54:11.034582 RX DQ/DQS(RDDQC) : PASS
7102 22:54:11.037262 TX DQ/DQS : PASS
7103 22:54:11.040525 RX DATLAT : PASS
7104 22:54:11.040945 RX DQ/DQS(Engine): PASS
7105 22:54:11.043783 TX OE : NO K
7106 22:54:11.044202 All Pass.
7107 22:54:11.044528
7108 22:54:11.047290 CH 1, Rank 0
7109 22:54:11.047705 SW Impedance : PASS
7110 22:54:11.050185 DUTY Scan : NO K
7111 22:54:11.053736 ZQ Calibration : PASS
7112 22:54:11.054149 Jitter Meter : NO K
7113 22:54:11.057380 CBT Training : PASS
7114 22:54:11.060439 Write leveling : PASS
7115 22:54:11.060852 RX DQS gating : PASS
7116 22:54:11.063584 RX DQ/DQS(RDDQC) : PASS
7117 22:54:11.063999 TX DQ/DQS : PASS
7118 22:54:11.066907 RX DATLAT : PASS
7119 22:54:11.070275 RX DQ/DQS(Engine): PASS
7120 22:54:11.070741 TX OE : NO K
7121 22:54:11.073287 All Pass.
7122 22:54:11.073748
7123 22:54:11.074079 CH 1, Rank 1
7124 22:54:11.076737 SW Impedance : PASS
7125 22:54:11.077148 DUTY Scan : NO K
7126 22:54:11.079842 ZQ Calibration : PASS
7127 22:54:11.083524 Jitter Meter : NO K
7128 22:54:11.083966 CBT Training : PASS
7129 22:54:11.086993 Write leveling : NO K
7130 22:54:11.090063 RX DQS gating : PASS
7131 22:54:11.090474 RX DQ/DQS(RDDQC) : PASS
7132 22:54:11.093214 TX DQ/DQS : PASS
7133 22:54:11.096555 RX DATLAT : PASS
7134 22:54:11.097133 RX DQ/DQS(Engine): PASS
7135 22:54:11.099995 TX OE : NO K
7136 22:54:11.100404 All Pass.
7137 22:54:11.100726
7138 22:54:11.103183 DramC Write-DBI off
7139 22:54:11.106264 PER_BANK_REFRESH: Hybrid Mode
7140 22:54:11.106716 TX_TRACKING: ON
7141 22:54:11.116193 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7142 22:54:11.119487 [FAST_K] Save calibration result to emmc
7143 22:54:11.123042 dramc_set_vcore_voltage set vcore to 725000
7144 22:54:11.126366 Read voltage for 1600, 0
7145 22:54:11.126796 Vio18 = 0
7146 22:54:11.129149 Vcore = 725000
7147 22:54:11.129642 Vdram = 0
7148 22:54:11.129977 Vddq = 0
7149 22:54:11.130285 Vmddr = 0
7150 22:54:11.135957 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7151 22:54:11.142657 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7152 22:54:11.143074 MEM_TYPE=3, freq_sel=13
7153 22:54:11.146010 sv_algorithm_assistance_LP4_3733
7154 22:54:11.149046 ============ PULL DRAM RESETB DOWN ============
7155 22:54:11.155501 ========== PULL DRAM RESETB DOWN end =========
7156 22:54:11.159017 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7157 22:54:11.162130 ===================================
7158 22:54:11.165368 LPDDR4 DRAM CONFIGURATION
7159 22:54:11.168308 ===================================
7160 22:54:11.168727 EX_ROW_EN[0] = 0x0
7161 22:54:11.171657 EX_ROW_EN[1] = 0x0
7162 22:54:11.175194 LP4Y_EN = 0x0
7163 22:54:11.175708 WORK_FSP = 0x1
7164 22:54:11.178914 WL = 0x5
7165 22:54:11.179432 RL = 0x5
7166 22:54:11.181787 BL = 0x2
7167 22:54:11.182197 RPST = 0x0
7168 22:54:11.185273 RD_PRE = 0x0
7169 22:54:11.185837 WR_PRE = 0x1
7170 22:54:11.188335 WR_PST = 0x1
7171 22:54:11.188818 DBI_WR = 0x0
7172 22:54:11.191505 DBI_RD = 0x0
7173 22:54:11.191928 OTF = 0x1
7174 22:54:11.195261 ===================================
7175 22:54:11.198077 ===================================
7176 22:54:11.201692 ANA top config
7177 22:54:11.205192 ===================================
7178 22:54:11.208367 DLL_ASYNC_EN = 0
7179 22:54:11.208785 ALL_SLAVE_EN = 0
7180 22:54:11.211831 NEW_RANK_MODE = 1
7181 22:54:11.214452 DLL_IDLE_MODE = 1
7182 22:54:11.218084 LP45_APHY_COMB_EN = 1
7183 22:54:11.218503 TX_ODT_DIS = 0
7184 22:54:11.221444 NEW_8X_MODE = 1
7185 22:54:11.224984 ===================================
7186 22:54:11.227691 ===================================
7187 22:54:11.230963 data_rate = 3200
7188 22:54:11.234799 CKR = 1
7189 22:54:11.238079 DQ_P2S_RATIO = 8
7190 22:54:11.241613 ===================================
7191 22:54:11.244392 CA_P2S_RATIO = 8
7192 22:54:11.244855 DQ_CA_OPEN = 0
7193 22:54:11.247580 DQ_SEMI_OPEN = 0
7194 22:54:11.251346 CA_SEMI_OPEN = 0
7195 22:54:11.254210 CA_FULL_RATE = 0
7196 22:54:11.257641 DQ_CKDIV4_EN = 0
7197 22:54:11.261152 CA_CKDIV4_EN = 0
7198 22:54:11.264135 CA_PREDIV_EN = 0
7199 22:54:11.264595 PH8_DLY = 12
7200 22:54:11.267610 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7201 22:54:11.270808 DQ_AAMCK_DIV = 4
7202 22:54:11.274007 CA_AAMCK_DIV = 4
7203 22:54:11.277186 CA_ADMCK_DIV = 4
7204 22:54:11.280780 DQ_TRACK_CA_EN = 0
7205 22:54:11.281247 CA_PICK = 1600
7206 22:54:11.284286 CA_MCKIO = 1600
7207 22:54:11.287323 MCKIO_SEMI = 0
7208 22:54:11.290468 PLL_FREQ = 3068
7209 22:54:11.293933 DQ_UI_PI_RATIO = 32
7210 22:54:11.297238 CA_UI_PI_RATIO = 0
7211 22:54:11.300517 ===================================
7212 22:54:11.303936 ===================================
7213 22:54:11.307092 memory_type:LPDDR4
7214 22:54:11.307655 GP_NUM : 10
7215 22:54:11.311056 SRAM_EN : 1
7216 22:54:11.311621 MD32_EN : 0
7217 22:54:11.313574 ===================================
7218 22:54:11.316637 [ANA_INIT] >>>>>>>>>>>>>>
7219 22:54:11.319944 <<<<<< [CONFIGURE PHASE]: ANA_TX
7220 22:54:11.323122 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7221 22:54:11.326780 ===================================
7222 22:54:11.329888 data_rate = 3200,PCW = 0X7600
7223 22:54:11.333576 ===================================
7224 22:54:11.336794 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7225 22:54:11.342981 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7226 22:54:11.346170 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7227 22:54:11.352933 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7228 22:54:11.356018 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7229 22:54:11.359268 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7230 22:54:11.359728 [ANA_INIT] flow start
7231 22:54:11.362972 [ANA_INIT] PLL >>>>>>>>
7232 22:54:11.366366 [ANA_INIT] PLL <<<<<<<<
7233 22:54:11.369455 [ANA_INIT] MIDPI >>>>>>>>
7234 22:54:11.369917 [ANA_INIT] MIDPI <<<<<<<<
7235 22:54:11.372970 [ANA_INIT] DLL >>>>>>>>
7236 22:54:11.376148 [ANA_INIT] DLL <<<<<<<<
7237 22:54:11.376710 [ANA_INIT] flow end
7238 22:54:11.379475 ============ LP4 DIFF to SE enter ============
7239 22:54:11.385739 ============ LP4 DIFF to SE exit ============
7240 22:54:11.386336 [ANA_INIT] <<<<<<<<<<<<<
7241 22:54:11.389278 [Flow] Enable top DCM control >>>>>
7242 22:54:11.392571 [Flow] Enable top DCM control <<<<<
7243 22:54:11.395780 Enable DLL master slave shuffle
7244 22:54:11.402388 ==============================================================
7245 22:54:11.405957 Gating Mode config
7246 22:54:11.408948 ==============================================================
7247 22:54:11.412244 Config description:
7248 22:54:11.421960 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7249 22:54:11.428871 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7250 22:54:11.431903 SELPH_MODE 0: By rank 1: By Phase
7251 22:54:11.438359 ==============================================================
7252 22:54:11.441941 GAT_TRACK_EN = 1
7253 22:54:11.444888 RX_GATING_MODE = 2
7254 22:54:11.448626 RX_GATING_TRACK_MODE = 2
7255 22:54:11.452092 SELPH_MODE = 1
7256 22:54:11.452751 PICG_EARLY_EN = 1
7257 22:54:11.455257 VALID_LAT_VALUE = 1
7258 22:54:11.461573 ==============================================================
7259 22:54:11.464973 Enter into Gating configuration >>>>
7260 22:54:11.468266 Exit from Gating configuration <<<<
7261 22:54:11.471542 Enter into DVFS_PRE_config >>>>>
7262 22:54:11.481299 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7263 22:54:11.484822 Exit from DVFS_PRE_config <<<<<
7264 22:54:11.487908 Enter into PICG configuration >>>>
7265 22:54:11.491842 Exit from PICG configuration <<<<
7266 22:54:11.494765 [RX_INPUT] configuration >>>>>
7267 22:54:11.497882 [RX_INPUT] configuration <<<<<
7268 22:54:11.501089 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7269 22:54:11.507955 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7270 22:54:11.514623 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7271 22:54:11.520910 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7272 22:54:11.527313 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7273 22:54:11.534479 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7274 22:54:11.537520 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7275 22:54:11.541254 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7276 22:54:11.544397 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7277 22:54:11.550940 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7278 22:54:11.554144 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7279 22:54:11.557475 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7280 22:54:11.560377 ===================================
7281 22:54:11.563673 LPDDR4 DRAM CONFIGURATION
7282 22:54:11.567189 ===================================
7283 22:54:11.567874 EX_ROW_EN[0] = 0x0
7284 22:54:11.570675 EX_ROW_EN[1] = 0x0
7285 22:54:11.573693 LP4Y_EN = 0x0
7286 22:54:11.574144 WORK_FSP = 0x1
7287 22:54:11.577251 WL = 0x5
7288 22:54:11.577833 RL = 0x5
7289 22:54:11.580734 BL = 0x2
7290 22:54:11.581209 RPST = 0x0
7291 22:54:11.583823 RD_PRE = 0x0
7292 22:54:11.584374 WR_PRE = 0x1
7293 22:54:11.586846 WR_PST = 0x1
7294 22:54:11.587371 DBI_WR = 0x0
7295 22:54:11.590365 DBI_RD = 0x0
7296 22:54:11.590821 OTF = 0x1
7297 22:54:11.593443 ===================================
7298 22:54:11.596731 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7299 22:54:11.603676 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7300 22:54:11.607344 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7301 22:54:11.610222 ===================================
7302 22:54:11.613592 LPDDR4 DRAM CONFIGURATION
7303 22:54:11.616487 ===================================
7304 22:54:11.616943 EX_ROW_EN[0] = 0x10
7305 22:54:11.620400 EX_ROW_EN[1] = 0x0
7306 22:54:11.623081 LP4Y_EN = 0x0
7307 22:54:11.623639 WORK_FSP = 0x1
7308 22:54:11.626435 WL = 0x5
7309 22:54:11.627000 RL = 0x5
7310 22:54:11.630178 BL = 0x2
7311 22:54:11.630740 RPST = 0x0
7312 22:54:11.633038 RD_PRE = 0x0
7313 22:54:11.633547 WR_PRE = 0x1
7314 22:54:11.636587 WR_PST = 0x1
7315 22:54:11.637148 DBI_WR = 0x0
7316 22:54:11.639662 DBI_RD = 0x0
7317 22:54:11.640119 OTF = 0x1
7318 22:54:11.643508 ===================================
7319 22:54:11.649575 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7320 22:54:11.650125 ==
7321 22:54:11.653134 Dram Type= 6, Freq= 0, CH_0, rank 0
7322 22:54:11.659677 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7323 22:54:11.660246 ==
7324 22:54:11.660611 [Duty_Offset_Calibration]
7325 22:54:11.662928 B0:1 B1:-1 CA:0
7326 22:54:11.663388
7327 22:54:11.666152 [DutyScan_Calibration_Flow] k_type=0
7328 22:54:11.675281
7329 22:54:11.675839 ==CLK 0==
7330 22:54:11.678474 Final CLK duty delay cell = 0
7331 22:54:11.682104 [0] MAX Duty = 5093%(X100), DQS PI = 20
7332 22:54:11.685610 [0] MIN Duty = 4875%(X100), DQS PI = 10
7333 22:54:11.686171 [0] AVG Duty = 4984%(X100)
7334 22:54:11.688614
7335 22:54:11.691675 CH0 CLK Duty spec in!! Max-Min= 218%
7336 22:54:11.694962 [DutyScan_Calibration_Flow] ====Done====
7337 22:54:11.695424
7338 22:54:11.698127 [DutyScan_Calibration_Flow] k_type=1
7339 22:54:11.714501
7340 22:54:11.715058 ==DQS 0 ==
7341 22:54:11.718092 Final DQS duty delay cell = -4
7342 22:54:11.721417 [-4] MAX Duty = 4969%(X100), DQS PI = 18
7343 22:54:11.724288 [-4] MIN Duty = 4844%(X100), DQS PI = 48
7344 22:54:11.727517 [-4] AVG Duty = 4906%(X100)
7345 22:54:11.728071
7346 22:54:11.728422 ==DQS 1 ==
7347 22:54:11.731156 Final DQS duty delay cell = 0
7348 22:54:11.734611 [0] MAX Duty = 5156%(X100), DQS PI = 2
7349 22:54:11.737362 [0] MIN Duty = 5000%(X100), DQS PI = 20
7350 22:54:11.740830 [0] AVG Duty = 5078%(X100)
7351 22:54:11.741289
7352 22:54:11.744265 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7353 22:54:11.744842
7354 22:54:11.747124 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7355 22:54:11.751153 [DutyScan_Calibration_Flow] ====Done====
7356 22:54:11.751716
7357 22:54:11.753959 [DutyScan_Calibration_Flow] k_type=3
7358 22:54:11.771957
7359 22:54:11.772503 ==DQM 0 ==
7360 22:54:11.774977 Final DQM duty delay cell = 0
7361 22:54:11.778065 [0] MAX Duty = 5124%(X100), DQS PI = 20
7362 22:54:11.781414 [0] MIN Duty = 4875%(X100), DQS PI = 10
7363 22:54:11.784819 [0] AVG Duty = 4999%(X100)
7364 22:54:11.785297
7365 22:54:11.785702 ==DQM 1 ==
7366 22:54:11.788513 Final DQM duty delay cell = 0
7367 22:54:11.791471 [0] MAX Duty = 5031%(X100), DQS PI = 54
7368 22:54:11.794936 [0] MIN Duty = 4813%(X100), DQS PI = 20
7369 22:54:11.798403 [0] AVG Duty = 4922%(X100)
7370 22:54:11.798700
7371 22:54:11.801234 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7372 22:54:11.801580
7373 22:54:11.804772 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7374 22:54:11.808098 [DutyScan_Calibration_Flow] ====Done====
7375 22:54:11.808486
7376 22:54:11.811471 [DutyScan_Calibration_Flow] k_type=2
7377 22:54:11.828382
7378 22:54:11.828876 ==DQ 0 ==
7379 22:54:11.831608 Final DQ duty delay cell = -4
7380 22:54:11.834946 [-4] MAX Duty = 5031%(X100), DQS PI = 26
7381 22:54:11.838184 [-4] MIN Duty = 4876%(X100), DQS PI = 50
7382 22:54:11.841496 [-4] AVG Duty = 4953%(X100)
7383 22:54:11.841960
7384 22:54:11.842320 ==DQ 1 ==
7385 22:54:11.844374 Final DQ duty delay cell = 0
7386 22:54:11.847774 [0] MAX Duty = 5125%(X100), DQS PI = 48
7387 22:54:11.851639 [0] MIN Duty = 5000%(X100), DQS PI = 36
7388 22:54:11.854416 [0] AVG Duty = 5062%(X100)
7389 22:54:11.854870
7390 22:54:11.857554 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7391 22:54:11.858125
7392 22:54:11.860856 CH0 DQ 1 Duty spec in!! Max-Min= 125%
7393 22:54:11.864345 [DutyScan_Calibration_Flow] ====Done====
7394 22:54:11.864802 ==
7395 22:54:11.867363 Dram Type= 6, Freq= 0, CH_1, rank 0
7396 22:54:11.870747 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7397 22:54:11.871181 ==
7398 22:54:11.874022 [Duty_Offset_Calibration]
7399 22:54:11.877408 B0:-1 B1:1 CA:2
7400 22:54:11.877882
7401 22:54:11.880808 [DutyScan_Calibration_Flow] k_type=0
7402 22:54:11.889190
7403 22:54:11.889641 ==CLK 0==
7404 22:54:11.892255 Final CLK duty delay cell = 0
7405 22:54:11.895616 [0] MAX Duty = 5187%(X100), DQS PI = 24
7406 22:54:11.898886 [0] MIN Duty = 4969%(X100), DQS PI = 0
7407 22:54:11.899407 [0] AVG Duty = 5078%(X100)
7408 22:54:11.902125
7409 22:54:11.905755 CH1 CLK Duty spec in!! Max-Min= 218%
7410 22:54:11.908814 [DutyScan_Calibration_Flow] ====Done====
7411 22:54:11.909232
7412 22:54:11.912610 [DutyScan_Calibration_Flow] k_type=1
7413 22:54:11.928693
7414 22:54:11.929253 ==DQS 0 ==
7415 22:54:11.932147 Final DQS duty delay cell = 0
7416 22:54:11.935878 [0] MAX Duty = 5125%(X100), DQS PI = 18
7417 22:54:11.938610 [0] MIN Duty = 4907%(X100), DQS PI = 10
7418 22:54:11.941991 [0] AVG Duty = 5016%(X100)
7419 22:54:11.942449
7420 22:54:11.942803 ==DQS 1 ==
7421 22:54:11.945025 Final DQS duty delay cell = 0
7422 22:54:11.948308 [0] MAX Duty = 5062%(X100), DQS PI = 2
7423 22:54:11.951923 [0] MIN Duty = 4969%(X100), DQS PI = 54
7424 22:54:11.954952 [0] AVG Duty = 5015%(X100)
7425 22:54:11.955409
7426 22:54:11.958379 CH1 DQS 0 Duty spec in!! Max-Min= 218%
7427 22:54:11.958838
7428 22:54:11.961274 CH1 DQS 1 Duty spec in!! Max-Min= 93%
7429 22:54:11.964645 [DutyScan_Calibration_Flow] ====Done====
7430 22:54:11.965317
7431 22:54:11.968092 [DutyScan_Calibration_Flow] k_type=3
7432 22:54:11.985370
7433 22:54:11.985924 ==DQM 0 ==
7434 22:54:11.988514 Final DQM duty delay cell = 0
7435 22:54:11.991968 [0] MAX Duty = 5218%(X100), DQS PI = 18
7436 22:54:11.994994 [0] MIN Duty = 4969%(X100), DQS PI = 10
7437 22:54:11.998506 [0] AVG Duty = 5093%(X100)
7438 22:54:11.998953
7439 22:54:11.999302 ==DQM 1 ==
7440 22:54:12.001899 Final DQM duty delay cell = 0
7441 22:54:12.005066 [0] MAX Duty = 5156%(X100), DQS PI = 2
7442 22:54:12.008511 [0] MIN Duty = 4938%(X100), DQS PI = 34
7443 22:54:12.011901 [0] AVG Duty = 5047%(X100)
7444 22:54:12.012351
7445 22:54:12.015047 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7446 22:54:12.015504
7447 22:54:12.018229 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7448 22:54:12.022079 [DutyScan_Calibration_Flow] ====Done====
7449 22:54:12.022651
7450 22:54:12.024913 [DutyScan_Calibration_Flow] k_type=2
7451 22:54:12.042542
7452 22:54:12.043080 ==DQ 0 ==
7453 22:54:12.045445 Final DQ duty delay cell = 0
7454 22:54:12.049118 [0] MAX Duty = 5156%(X100), DQS PI = 30
7455 22:54:12.052015 [0] MIN Duty = 4906%(X100), DQS PI = 8
7456 22:54:12.052472 [0] AVG Duty = 5031%(X100)
7457 22:54:12.052822
7458 22:54:12.055515 ==DQ 1 ==
7459 22:54:12.058785 Final DQ duty delay cell = 0
7460 22:54:12.062091 [0] MAX Duty = 5156%(X100), DQS PI = 8
7461 22:54:12.065458 [0] MIN Duty = 4969%(X100), DQS PI = 54
7462 22:54:12.065957 [0] AVG Duty = 5062%(X100)
7463 22:54:12.066316
7464 22:54:12.068733 CH1 DQ 0 Duty spec in!! Max-Min= 250%
7465 22:54:12.072113
7466 22:54:12.075286 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7467 22:54:12.078506 [DutyScan_Calibration_Flow] ====Done====
7468 22:54:12.081824 nWR fixed to 30
7469 22:54:12.082276 [ModeRegInit_LP4] CH0 RK0
7470 22:54:12.085318 [ModeRegInit_LP4] CH0 RK1
7471 22:54:12.088637 [ModeRegInit_LP4] CH1 RK0
7472 22:54:12.091490 [ModeRegInit_LP4] CH1 RK1
7473 22:54:12.091943 match AC timing 5
7474 22:54:12.098340 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7475 22:54:12.101465 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7476 22:54:12.105123 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7477 22:54:12.111837 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7478 22:54:12.114527 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7479 22:54:12.114990 [MiockJmeterHQA]
7480 22:54:12.115338
7481 22:54:12.117976 [DramcMiockJmeter] u1RxGatingPI = 0
7482 22:54:12.121452 0 : 4363, 4137
7483 22:54:12.121867 4 : 4252, 4026
7484 22:54:12.124594 8 : 4363, 4137
7485 22:54:12.125007 12 : 4252, 4027
7486 22:54:12.125358 16 : 4252, 4027
7487 22:54:12.128087 20 : 4253, 4027
7488 22:54:12.128525 24 : 4365, 4140
7489 22:54:12.131054 28 : 4252, 4027
7490 22:54:12.131419 32 : 4255, 4029
7491 22:54:12.134347 36 : 4252, 4027
7492 22:54:12.134763 40 : 4363, 4138
7493 22:54:12.137637 44 : 4252, 4027
7494 22:54:12.138052 48 : 4360, 4137
7495 22:54:12.138377 52 : 4250, 4027
7496 22:54:12.141204 56 : 4250, 4027
7497 22:54:12.141664 60 : 4250, 4027
7498 22:54:12.144507 64 : 4253, 4029
7499 22:54:12.145090 68 : 4250, 4027
7500 22:54:12.147630 72 : 4250, 4027
7501 22:54:12.148058 76 : 4363, 4140
7502 22:54:12.150843 80 : 4250, 4027
7503 22:54:12.151261 84 : 4252, 4029
7504 22:54:12.154480 88 : 4250, 4026
7505 22:54:12.154897 92 : 4360, 269
7506 22:54:12.155225 96 : 4250, 0
7507 22:54:12.157511 100 : 4250, 0
7508 22:54:12.157937 104 : 4361, 0
7509 22:54:12.158325 108 : 4361, 0
7510 22:54:12.160857 112 : 4364, 0
7511 22:54:12.161271 116 : 4250, 0
7512 22:54:12.163990 120 : 4250, 0
7513 22:54:12.164416 124 : 4250, 0
7514 22:54:12.164745 128 : 4252, 0
7515 22:54:12.167425 132 : 4250, 0
7516 22:54:12.167938 136 : 4250, 0
7517 22:54:12.170684 140 : 4252, 0
7518 22:54:12.171144 144 : 4250, 0
7519 22:54:12.171683 148 : 4250, 0
7520 22:54:12.173653 152 : 4252, 0
7521 22:54:12.174078 156 : 4361, 0
7522 22:54:12.177769 160 : 4361, 0
7523 22:54:12.178287 164 : 4363, 0
7524 22:54:12.178621 168 : 4250, 0
7525 22:54:12.180420 172 : 4360, 0
7526 22:54:12.180844 176 : 4361, 0
7527 22:54:12.183917 180 : 4247, 0
7528 22:54:12.184435 184 : 4250, 0
7529 22:54:12.184777 188 : 4250, 0
7530 22:54:12.187150 192 : 4250, 0
7531 22:54:12.187572 196 : 4360, 0
7532 22:54:12.190568 200 : 4250, 0
7533 22:54:12.191084 204 : 4250, 0
7534 22:54:12.191452 208 : 4361, 0
7535 22:54:12.193925 212 : 4361, 0
7536 22:54:12.194352 216 : 4362, 0
7537 22:54:12.194738 220 : 4250, 0
7538 22:54:12.196897 224 : 4250, 345
7539 22:54:12.197320 228 : 4252, 3530
7540 22:54:12.200435 232 : 4361, 4137
7541 22:54:12.200859 236 : 4252, 4029
7542 22:54:12.203818 240 : 4250, 4027
7543 22:54:12.204338 244 : 4250, 4027
7544 22:54:12.206759 248 : 4252, 4029
7545 22:54:12.207184 252 : 4249, 4027
7546 22:54:12.210039 256 : 4250, 4027
7547 22:54:12.210464 260 : 4250, 4027
7548 22:54:12.213639 264 : 4253, 4029
7549 22:54:12.214077 268 : 4250, 4026
7550 22:54:12.216609 272 : 4360, 4138
7551 22:54:12.217030 276 : 4360, 4138
7552 22:54:12.219976 280 : 4249, 4027
7553 22:54:12.220460 284 : 4363, 4140
7554 22:54:12.220799 288 : 4360, 4137
7555 22:54:12.223353 292 : 4250, 4027
7556 22:54:12.224040 296 : 4250, 4027
7557 22:54:12.226576 300 : 4253, 4029
7558 22:54:12.227084 304 : 4250, 4027
7559 22:54:12.229806 308 : 4250, 4027
7560 22:54:12.230229 312 : 4250, 4027
7561 22:54:12.233375 316 : 4250, 4027
7562 22:54:12.234040 320 : 4250, 4026
7563 22:54:12.236835 324 : 4360, 4137
7564 22:54:12.237556 328 : 4360, 4138
7565 22:54:12.239666 332 : 4250, 4027
7566 22:54:12.240088 336 : 4363, 3872
7567 22:54:12.243110 340 : 4360, 1845
7568 22:54:12.243536
7569 22:54:12.243862 MIOCK jitter meter ch=0
7570 22:54:12.244169
7571 22:54:12.246379 1T = (340-92) = 248 dly cells
7572 22:54:12.253456 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps
7573 22:54:12.254083 ==
7574 22:54:12.256209 Dram Type= 6, Freq= 0, CH_0, rank 0
7575 22:54:12.259659 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7576 22:54:12.260089 ==
7577 22:54:12.266465 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7578 22:54:12.270012 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7579 22:54:12.272880 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7580 22:54:12.279374 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7581 22:54:12.289211 [CA 0] Center 43 (13~74) winsize 62
7582 22:54:12.292662 [CA 1] Center 43 (13~74) winsize 62
7583 22:54:12.296133 [CA 2] Center 39 (10~69) winsize 60
7584 22:54:12.299353 [CA 3] Center 38 (9~68) winsize 60
7585 22:54:12.302668 [CA 4] Center 37 (8~66) winsize 59
7586 22:54:12.306004 [CA 5] Center 36 (7~66) winsize 60
7587 22:54:12.306422
7588 22:54:12.308916 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7589 22:54:12.309368
7590 22:54:12.315558 [CATrainingPosCal] consider 1 rank data
7591 22:54:12.316050 u2DelayCellTimex100 = 262/100 ps
7592 22:54:12.321893 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7593 22:54:12.325659 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7594 22:54:12.328522 CA2 delay=39 (10~69),Diff = 3 PI (11 cell)
7595 22:54:12.331947 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7596 22:54:12.335133 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7597 22:54:12.338628 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7598 22:54:12.339048
7599 22:54:12.341629 CA PerBit enable=1, Macro0, CA PI delay=36
7600 22:54:12.342254
7601 22:54:12.345159 [CBTSetCACLKResult] CA Dly = 36
7602 22:54:12.348408 CS Dly: 12 (0~43)
7603 22:54:12.351961 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7604 22:54:12.355487 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7605 22:54:12.355905 ==
7606 22:54:12.358710 Dram Type= 6, Freq= 0, CH_0, rank 1
7607 22:54:12.364913 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7608 22:54:12.365485 ==
7609 22:54:12.368870 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7610 22:54:12.374675 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7611 22:54:12.378038 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7612 22:54:12.384868 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7613 22:54:12.393094 [CA 0] Center 43 (13~74) winsize 62
7614 22:54:12.396536 [CA 1] Center 44 (14~74) winsize 61
7615 22:54:12.399768 [CA 2] Center 38 (9~68) winsize 60
7616 22:54:12.402663 [CA 3] Center 38 (9~68) winsize 60
7617 22:54:12.406206 [CA 4] Center 36 (7~66) winsize 60
7618 22:54:12.409234 [CA 5] Center 36 (7~66) winsize 60
7619 22:54:12.409779
7620 22:54:12.412690 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7621 22:54:12.413182
7622 22:54:12.419377 [CATrainingPosCal] consider 2 rank data
7623 22:54:12.419924 u2DelayCellTimex100 = 262/100 ps
7624 22:54:12.426192 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7625 22:54:12.428742 CA1 delay=44 (14~74),Diff = 8 PI (29 cell)
7626 22:54:12.432497 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7627 22:54:12.435877 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7628 22:54:12.439151 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7629 22:54:12.442539 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7630 22:54:12.443032
7631 22:54:12.445418 CA PerBit enable=1, Macro0, CA PI delay=36
7632 22:54:12.445881
7633 22:54:12.448701 [CBTSetCACLKResult] CA Dly = 36
7634 22:54:12.452325 CS Dly: 12 (0~43)
7635 22:54:12.455304 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7636 22:54:12.458742 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7637 22:54:12.459329
7638 22:54:12.461933 ----->DramcWriteLeveling(PI) begin...
7639 22:54:12.462402 ==
7640 22:54:12.465156 Dram Type= 6, Freq= 0, CH_0, rank 0
7641 22:54:12.472060 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7642 22:54:12.472559 ==
7643 22:54:12.475213 Write leveling (Byte 0): 34 => 34
7644 22:54:12.479967 Write leveling (Byte 1): 29 => 29
7645 22:54:12.481898 DramcWriteLeveling(PI) end<-----
7646 22:54:12.482355
7647 22:54:12.482713 ==
7648 22:54:12.485242 Dram Type= 6, Freq= 0, CH_0, rank 0
7649 22:54:12.488809 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7650 22:54:12.489268 ==
7651 22:54:12.491832 [Gating] SW mode calibration
7652 22:54:12.498528 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7653 22:54:12.505495 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7654 22:54:12.508156 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7655 22:54:12.511558 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7656 22:54:12.518222 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7657 22:54:12.521158 1 4 12 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)
7658 22:54:12.524851 1 4 16 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
7659 22:54:12.531348 1 4 20 | B1->B0 | 2625 3434 | 1 1 | (0 0) (1 1)
7660 22:54:12.534952 1 4 24 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
7661 22:54:12.537834 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7662 22:54:12.544641 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7663 22:54:12.547860 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7664 22:54:12.551062 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7665 22:54:12.557519 1 5 12 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (1 0)
7666 22:54:12.561079 1 5 16 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
7667 22:54:12.563985 1 5 20 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7668 22:54:12.570554 1 5 24 | B1->B0 | 2626 2323 | 1 0 | (1 0) (0 0)
7669 22:54:12.574089 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7670 22:54:12.577558 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7671 22:54:12.584155 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7672 22:54:12.587910 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7673 22:54:12.590940 1 6 12 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
7674 22:54:12.597175 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7675 22:54:12.600523 1 6 20 | B1->B0 | 2525 4646 | 1 0 | (0 0) (0 0)
7676 22:54:12.603998 1 6 24 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
7677 22:54:12.610830 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7678 22:54:12.613888 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7679 22:54:12.617005 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7680 22:54:12.623283 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7681 22:54:12.626835 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7682 22:54:12.630262 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7683 22:54:12.636872 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7684 22:54:12.640313 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7685 22:54:12.643252 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7686 22:54:12.650124 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7687 22:54:12.653291 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7688 22:54:12.656136 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7689 22:54:12.663224 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7690 22:54:12.666047 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7691 22:54:12.669893 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7692 22:54:12.676465 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7693 22:54:12.679317 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7694 22:54:12.683121 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7695 22:54:12.689264 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7696 22:54:12.692923 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7697 22:54:12.696198 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7698 22:54:12.702589 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7699 22:54:12.703053 Total UI for P1: 0, mck2ui 16
7700 22:54:12.708980 best dqsien dly found for B0: ( 1, 9, 12)
7701 22:54:12.712159 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7702 22:54:12.715721 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7703 22:54:12.718690 Total UI for P1: 0, mck2ui 16
7704 22:54:12.722090 best dqsien dly found for B1: ( 1, 9, 18)
7705 22:54:12.725298 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7706 22:54:12.728709 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7707 22:54:12.729372
7708 22:54:12.735081 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7709 22:54:12.738556 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7710 22:54:12.742207 [Gating] SW calibration Done
7711 22:54:12.742754 ==
7712 22:54:12.745325 Dram Type= 6, Freq= 0, CH_0, rank 0
7713 22:54:12.748284 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7714 22:54:12.748768 ==
7715 22:54:12.749125 RX Vref Scan: 0
7716 22:54:12.749502
7717 22:54:12.752382 RX Vref 0 -> 0, step: 1
7718 22:54:12.752836
7719 22:54:12.754852 RX Delay 0 -> 252, step: 8
7720 22:54:12.758664 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7721 22:54:12.762012 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7722 22:54:12.768779 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7723 22:54:12.772098 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7724 22:54:12.774571 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7725 22:54:12.778166 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7726 22:54:12.781585 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
7727 22:54:12.787711 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
7728 22:54:12.791847 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7729 22:54:12.794779 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7730 22:54:12.797901 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7731 22:54:12.801252 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7732 22:54:12.808045 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7733 22:54:12.811358 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7734 22:54:12.815187 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7735 22:54:12.817685 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7736 22:54:12.818140 ==
7737 22:54:12.821049 Dram Type= 6, Freq= 0, CH_0, rank 0
7738 22:54:12.828204 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7739 22:54:12.828759 ==
7740 22:54:12.829136 DQS Delay:
7741 22:54:12.831191 DQS0 = 0, DQS1 = 0
7742 22:54:12.831678 DQM Delay:
7743 22:54:12.834555 DQM0 = 133, DQM1 = 125
7744 22:54:12.835008 DQ Delay:
7745 22:54:12.837794 DQ0 =131, DQ1 =139, DQ2 =131, DQ3 =131
7746 22:54:12.840862 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =143
7747 22:54:12.843945 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =119
7748 22:54:12.847532 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =131
7749 22:54:12.848066
7750 22:54:12.848579
7751 22:54:12.848964 ==
7752 22:54:12.850903 Dram Type= 6, Freq= 0, CH_0, rank 0
7753 22:54:12.857086 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7754 22:54:12.857610 ==
7755 22:54:12.857973
7756 22:54:12.858304
7757 22:54:12.858620 TX Vref Scan disable
7758 22:54:12.860733 == TX Byte 0 ==
7759 22:54:12.864353 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7760 22:54:12.871261 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7761 22:54:12.871815 == TX Byte 1 ==
7762 22:54:12.873871 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7763 22:54:12.880748 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7764 22:54:12.881296 ==
7765 22:54:12.883796 Dram Type= 6, Freq= 0, CH_0, rank 0
7766 22:54:12.886778 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7767 22:54:12.887400 ==
7768 22:54:12.900313
7769 22:54:12.903513 TX Vref early break, caculate TX vref
7770 22:54:12.906309 TX Vref=16, minBit 5, minWin=22, winSum=374
7771 22:54:12.909773 TX Vref=18, minBit 1, minWin=23, winSum=384
7772 22:54:12.913413 TX Vref=20, minBit 6, minWin=23, winSum=391
7773 22:54:12.916306 TX Vref=22, minBit 4, minWin=23, winSum=405
7774 22:54:12.919861 TX Vref=24, minBit 7, minWin=24, winSum=413
7775 22:54:12.926179 TX Vref=26, minBit 6, minWin=25, winSum=421
7776 22:54:12.929408 TX Vref=28, minBit 4, minWin=25, winSum=425
7777 22:54:12.932938 TX Vref=30, minBit 5, minWin=23, winSum=411
7778 22:54:12.935815 TX Vref=32, minBit 0, minWin=24, winSum=404
7779 22:54:12.939303 TX Vref=34, minBit 4, minWin=23, winSum=391
7780 22:54:12.946010 [TxChooseVref] Worse bit 4, Min win 25, Win sum 425, Final Vref 28
7781 22:54:12.946565
7782 22:54:12.949405 Final TX Range 0 Vref 28
7783 22:54:12.949868
7784 22:54:12.950369 ==
7785 22:54:12.952645 Dram Type= 6, Freq= 0, CH_0, rank 0
7786 22:54:12.955517 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7787 22:54:12.956121 ==
7788 22:54:12.956599
7789 22:54:12.957039
7790 22:54:12.958890 TX Vref Scan disable
7791 22:54:12.965407 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
7792 22:54:12.965862 == TX Byte 0 ==
7793 22:54:12.969240 u2DelayCellOfst[0]=14 cells (4 PI)
7794 22:54:12.972723 u2DelayCellOfst[1]=18 cells (5 PI)
7795 22:54:12.975352 u2DelayCellOfst[2]=14 cells (4 PI)
7796 22:54:12.978868 u2DelayCellOfst[3]=14 cells (4 PI)
7797 22:54:12.982236 u2DelayCellOfst[4]=11 cells (3 PI)
7798 22:54:12.985644 u2DelayCellOfst[5]=0 cells (0 PI)
7799 22:54:12.988870 u2DelayCellOfst[6]=18 cells (5 PI)
7800 22:54:12.991969 u2DelayCellOfst[7]=22 cells (6 PI)
7801 22:54:12.995246 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7802 22:54:12.998428 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7803 22:54:13.002257 == TX Byte 1 ==
7804 22:54:13.004914 u2DelayCellOfst[8]=0 cells (0 PI)
7805 22:54:13.008586 u2DelayCellOfst[9]=0 cells (0 PI)
7806 22:54:13.011808 u2DelayCellOfst[10]=7 cells (2 PI)
7807 22:54:13.015158 u2DelayCellOfst[11]=0 cells (0 PI)
7808 22:54:13.018464 u2DelayCellOfst[12]=11 cells (3 PI)
7809 22:54:13.018923 u2DelayCellOfst[13]=11 cells (3 PI)
7810 22:54:13.021521 u2DelayCellOfst[14]=14 cells (4 PI)
7811 22:54:13.024804 u2DelayCellOfst[15]=11 cells (3 PI)
7812 22:54:13.031388 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7813 22:54:13.034920 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7814 22:54:13.038558 DramC Write-DBI on
7815 22:54:13.039107 ==
7816 22:54:13.041609 Dram Type= 6, Freq= 0, CH_0, rank 0
7817 22:54:13.044974 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7818 22:54:13.045475 ==
7819 22:54:13.045843
7820 22:54:13.046173
7821 22:54:13.047871 TX Vref Scan disable
7822 22:54:13.048327 == TX Byte 0 ==
7823 22:54:13.054813 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7824 22:54:13.055363 == TX Byte 1 ==
7825 22:54:13.057785 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7826 22:54:13.061076 DramC Write-DBI off
7827 22:54:13.061576
7828 22:54:13.061934 [DATLAT]
7829 22:54:13.064657 Freq=1600, CH0 RK0
7830 22:54:13.065176
7831 22:54:13.065604 DATLAT Default: 0xf
7832 22:54:13.068247 0, 0xFFFF, sum = 0
7833 22:54:13.068839 1, 0xFFFF, sum = 0
7834 22:54:13.071253 2, 0xFFFF, sum = 0
7835 22:54:13.071711 3, 0xFFFF, sum = 0
7836 22:54:13.074415 4, 0xFFFF, sum = 0
7837 22:54:13.078204 5, 0xFFFF, sum = 0
7838 22:54:13.078756 6, 0xFFFF, sum = 0
7839 22:54:13.080917 7, 0xFFFF, sum = 0
7840 22:54:13.081445 8, 0xFFFF, sum = 0
7841 22:54:13.084432 9, 0xFFFF, sum = 0
7842 22:54:13.084914 10, 0xFFFF, sum = 0
7843 22:54:13.087894 11, 0xFFFF, sum = 0
7844 22:54:13.088354 12, 0xFFFF, sum = 0
7845 22:54:13.091030 13, 0xFFFF, sum = 0
7846 22:54:13.091589 14, 0x0, sum = 1
7847 22:54:13.094046 15, 0x0, sum = 2
7848 22:54:13.094506 16, 0x0, sum = 3
7849 22:54:13.097518 17, 0x0, sum = 4
7850 22:54:13.098054 best_step = 15
7851 22:54:13.098529
7852 22:54:13.098995 ==
7853 22:54:13.101560 Dram Type= 6, Freq= 0, CH_0, rank 0
7854 22:54:13.104071 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7855 22:54:13.107679 ==
7856 22:54:13.108281 RX Vref Scan: 1
7857 22:54:13.108767
7858 22:54:13.111087 Set Vref Range= 24 -> 127
7859 22:54:13.111608
7860 22:54:13.113924 RX Vref 24 -> 127, step: 1
7861 22:54:13.114400
7862 22:54:13.114760 RX Delay 11 -> 252, step: 4
7863 22:54:13.115099
7864 22:54:13.117125 Set Vref, RX VrefLevel [Byte0]: 24
7865 22:54:13.120607 [Byte1]: 24
7866 22:54:13.124666
7867 22:54:13.125221 Set Vref, RX VrefLevel [Byte0]: 25
7868 22:54:13.127892 [Byte1]: 25
7869 22:54:13.132182
7870 22:54:13.132731 Set Vref, RX VrefLevel [Byte0]: 26
7871 22:54:13.135249 [Byte1]: 26
7872 22:54:13.139851
7873 22:54:13.140454 Set Vref, RX VrefLevel [Byte0]: 27
7874 22:54:13.143097 [Byte1]: 27
7875 22:54:13.147292
7876 22:54:13.147746 Set Vref, RX VrefLevel [Byte0]: 28
7877 22:54:13.150565 [Byte1]: 28
7878 22:54:13.154967
7879 22:54:13.155520 Set Vref, RX VrefLevel [Byte0]: 29
7880 22:54:13.158473 [Byte1]: 29
7881 22:54:13.162726
7882 22:54:13.163179 Set Vref, RX VrefLevel [Byte0]: 30
7883 22:54:13.165967 [Byte1]: 30
7884 22:54:13.170338
7885 22:54:13.170882 Set Vref, RX VrefLevel [Byte0]: 31
7886 22:54:13.173486 [Byte1]: 31
7887 22:54:13.177757
7888 22:54:13.178213 Set Vref, RX VrefLevel [Byte0]: 32
7889 22:54:13.181169 [Byte1]: 32
7890 22:54:13.185407
7891 22:54:13.185863 Set Vref, RX VrefLevel [Byte0]: 33
7892 22:54:13.188913 [Byte1]: 33
7893 22:54:13.193514
7894 22:54:13.194083 Set Vref, RX VrefLevel [Byte0]: 34
7895 22:54:13.196910 [Byte1]: 34
7896 22:54:13.200688
7897 22:54:13.201229 Set Vref, RX VrefLevel [Byte0]: 35
7898 22:54:13.203763 [Byte1]: 35
7899 22:54:13.208776
7900 22:54:13.209324 Set Vref, RX VrefLevel [Byte0]: 36
7901 22:54:13.211998 [Byte1]: 36
7902 22:54:13.215983
7903 22:54:13.216537 Set Vref, RX VrefLevel [Byte0]: 37
7904 22:54:13.219698 [Byte1]: 37
7905 22:54:13.223507
7906 22:54:13.224075 Set Vref, RX VrefLevel [Byte0]: 38
7907 22:54:13.226888 [Byte1]: 38
7908 22:54:13.231553
7909 22:54:13.232104 Set Vref, RX VrefLevel [Byte0]: 39
7910 22:54:13.234554 [Byte1]: 39
7911 22:54:13.238733
7912 22:54:13.239279 Set Vref, RX VrefLevel [Byte0]: 40
7913 22:54:13.241814 [Byte1]: 40
7914 22:54:13.246088
7915 22:54:13.246541 Set Vref, RX VrefLevel [Byte0]: 41
7916 22:54:13.249891 [Byte1]: 41
7917 22:54:13.254081
7918 22:54:13.254536 Set Vref, RX VrefLevel [Byte0]: 42
7919 22:54:13.257278 [Byte1]: 42
7920 22:54:13.261577
7921 22:54:13.262033 Set Vref, RX VrefLevel [Byte0]: 43
7922 22:54:13.264662 [Byte1]: 43
7923 22:54:13.268915
7924 22:54:13.269413 Set Vref, RX VrefLevel [Byte0]: 44
7925 22:54:13.272712 [Byte1]: 44
7926 22:54:13.277118
7927 22:54:13.277683 Set Vref, RX VrefLevel [Byte0]: 45
7928 22:54:13.280195 [Byte1]: 45
7929 22:54:13.284668
7930 22:54:13.285125 Set Vref, RX VrefLevel [Byte0]: 46
7931 22:54:13.288483 [Byte1]: 46
7932 22:54:13.292224
7933 22:54:13.292781 Set Vref, RX VrefLevel [Byte0]: 47
7934 22:54:13.295430 [Byte1]: 47
7935 22:54:13.299927
7936 22:54:13.300662 Set Vref, RX VrefLevel [Byte0]: 48
7937 22:54:13.303070 [Byte1]: 48
7938 22:54:13.307672
7939 22:54:13.308236 Set Vref, RX VrefLevel [Byte0]: 49
7940 22:54:13.310959 [Byte1]: 49
7941 22:54:13.314840
7942 22:54:13.315392 Set Vref, RX VrefLevel [Byte0]: 50
7943 22:54:13.318148 [Byte1]: 50
7944 22:54:13.322802
7945 22:54:13.323348 Set Vref, RX VrefLevel [Byte0]: 51
7946 22:54:13.325450 [Byte1]: 51
7947 22:54:13.329890
7948 22:54:13.330433 Set Vref, RX VrefLevel [Byte0]: 52
7949 22:54:13.333904 [Byte1]: 52
7950 22:54:13.338059
7951 22:54:13.338614 Set Vref, RX VrefLevel [Byte0]: 53
7952 22:54:13.340983 [Byte1]: 53
7953 22:54:13.345451
7954 22:54:13.345908 Set Vref, RX VrefLevel [Byte0]: 54
7955 22:54:13.348526 [Byte1]: 54
7956 22:54:13.352811
7957 22:54:13.353264 Set Vref, RX VrefLevel [Byte0]: 55
7958 22:54:13.356294 [Byte1]: 55
7959 22:54:13.360479
7960 22:54:13.360933 Set Vref, RX VrefLevel [Byte0]: 56
7961 22:54:13.363809 [Byte1]: 56
7962 22:54:13.368264
7963 22:54:13.368720 Set Vref, RX VrefLevel [Byte0]: 57
7964 22:54:13.371587 [Byte1]: 57
7965 22:54:13.375587
7966 22:54:13.376058 Set Vref, RX VrefLevel [Byte0]: 58
7967 22:54:13.379022 [Byte1]: 58
7968 22:54:13.383294
7969 22:54:13.383842 Set Vref, RX VrefLevel [Byte0]: 59
7970 22:54:13.386750 [Byte1]: 59
7971 22:54:13.391001
7972 22:54:13.391460 Set Vref, RX VrefLevel [Byte0]: 60
7973 22:54:13.394368 [Byte1]: 60
7974 22:54:13.398426
7975 22:54:13.398965 Set Vref, RX VrefLevel [Byte0]: 61
7976 22:54:13.401875 [Byte1]: 61
7977 22:54:13.406545
7978 22:54:13.407104 Set Vref, RX VrefLevel [Byte0]: 62
7979 22:54:13.410018 [Byte1]: 62
7980 22:54:13.413650
7981 22:54:13.414105 Set Vref, RX VrefLevel [Byte0]: 63
7982 22:54:13.417185 [Byte1]: 63
7983 22:54:13.421383
7984 22:54:13.422096 Set Vref, RX VrefLevel [Byte0]: 64
7985 22:54:13.424555 [Byte1]: 64
7986 22:54:13.428959
7987 22:54:13.429639 Set Vref, RX VrefLevel [Byte0]: 65
7988 22:54:13.431999 [Byte1]: 65
7989 22:54:13.436588
7990 22:54:13.437003 Set Vref, RX VrefLevel [Byte0]: 66
7991 22:54:13.440026 [Byte1]: 66
7992 22:54:13.444161
7993 22:54:13.444572 Set Vref, RX VrefLevel [Byte0]: 67
7994 22:54:13.447608 [Byte1]: 67
7995 22:54:13.451931
7996 22:54:13.452320 Set Vref, RX VrefLevel [Byte0]: 68
7997 22:54:13.454986 [Byte1]: 68
7998 22:54:13.459307
7999 22:54:13.459717 Set Vref, RX VrefLevel [Byte0]: 69
8000 22:54:13.462586 [Byte1]: 69
8001 22:54:13.467189
8002 22:54:13.467598 Set Vref, RX VrefLevel [Byte0]: 70
8003 22:54:13.470528 [Byte1]: 70
8004 22:54:13.474755
8005 22:54:13.475169 Set Vref, RX VrefLevel [Byte0]: 71
8006 22:54:13.477650 [Byte1]: 71
8007 22:54:13.482184
8008 22:54:13.482651 Set Vref, RX VrefLevel [Byte0]: 72
8009 22:54:13.485695 [Byte1]: 72
8010 22:54:13.489810
8011 22:54:13.490315 Set Vref, RX VrefLevel [Byte0]: 73
8012 22:54:13.492879 [Byte1]: 73
8013 22:54:13.497398
8014 22:54:13.497814 Set Vref, RX VrefLevel [Byte0]: 74
8015 22:54:13.500546 [Byte1]: 74
8016 22:54:13.505320
8017 22:54:13.505773 Set Vref, RX VrefLevel [Byte0]: 75
8018 22:54:13.508818 [Byte1]: 75
8019 22:54:13.512945
8020 22:54:13.513500 Set Vref, RX VrefLevel [Byte0]: 76
8021 22:54:13.516281 [Byte1]: 76
8022 22:54:13.520522
8023 22:54:13.520935 Set Vref, RX VrefLevel [Byte0]: 77
8024 22:54:13.526792 [Byte1]: 77
8025 22:54:13.527260
8026 22:54:13.530209 Set Vref, RX VrefLevel [Byte0]: 78
8027 22:54:13.533535 [Byte1]: 78
8028 22:54:13.533948
8029 22:54:13.536854 Set Vref, RX VrefLevel [Byte0]: 79
8030 22:54:13.539928 [Byte1]: 79
8031 22:54:13.543115
8032 22:54:13.543578 Set Vref, RX VrefLevel [Byte0]: 80
8033 22:54:13.546260 [Byte1]: 80
8034 22:54:13.550664
8035 22:54:13.551075 Final RX Vref Byte 0 = 61 to rank0
8036 22:54:13.553919 Final RX Vref Byte 1 = 60 to rank0
8037 22:54:13.557307 Final RX Vref Byte 0 = 61 to rank1
8038 22:54:13.560970 Final RX Vref Byte 1 = 60 to rank1==
8039 22:54:13.564231 Dram Type= 6, Freq= 0, CH_0, rank 0
8040 22:54:13.570404 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8041 22:54:13.570822 ==
8042 22:54:13.571149 DQS Delay:
8043 22:54:13.571624 DQS0 = 0, DQS1 = 0
8044 22:54:13.573759 DQM Delay:
8045 22:54:13.574172 DQM0 = 132, DQM1 = 123
8046 22:54:13.577376 DQ Delay:
8047 22:54:13.580625 DQ0 =130, DQ1 =132, DQ2 =128, DQ3 =130
8048 22:54:13.584325 DQ4 =132, DQ5 =122, DQ6 =140, DQ7 =142
8049 22:54:13.587544 DQ8 =114, DQ9 =112, DQ10 =124, DQ11 =120
8050 22:54:13.591247 DQ12 =128, DQ13 =126, DQ14 =134, DQ15 =128
8051 22:54:13.591756
8052 22:54:13.592081
8053 22:54:13.592376
8054 22:54:13.593468 [DramC_TX_OE_Calibration] TA2
8055 22:54:13.597066 Original DQ_B0 (3 6) =30, OEN = 27
8056 22:54:13.600018 Original DQ_B1 (3 6) =30, OEN = 27
8057 22:54:13.603941 24, 0x0, End_B0=24 End_B1=24
8058 22:54:13.604457 25, 0x0, End_B0=25 End_B1=25
8059 22:54:13.606933 26, 0x0, End_B0=26 End_B1=26
8060 22:54:13.610378 27, 0x0, End_B0=27 End_B1=27
8061 22:54:13.613762 28, 0x0, End_B0=28 End_B1=28
8062 22:54:13.617115 29, 0x0, End_B0=29 End_B1=29
8063 22:54:13.617696 30, 0x0, End_B0=30 End_B1=30
8064 22:54:13.620642 31, 0x4141, End_B0=30 End_B1=30
8065 22:54:13.623202 Byte0 end_step=30 best_step=27
8066 22:54:13.626322 Byte1 end_step=30 best_step=27
8067 22:54:13.630177 Byte0 TX OE(2T, 0.5T) = (3, 3)
8068 22:54:13.633165 Byte1 TX OE(2T, 0.5T) = (3, 3)
8069 22:54:13.633730
8070 22:54:13.634054
8071 22:54:13.639574 [DQSOSCAuto] RK0, (LSB)MR18= 0x2315, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 392 ps
8072 22:54:13.643486 CH0 RK0: MR19=303, MR18=2315
8073 22:54:13.649950 CH0_RK0: MR19=0x303, MR18=0x2315, DQSOSC=392, MR23=63, INC=24, DEC=16
8074 22:54:13.650503
8075 22:54:13.652979 ----->DramcWriteLeveling(PI) begin...
8076 22:54:13.653637 ==
8077 22:54:13.656258 Dram Type= 6, Freq= 0, CH_0, rank 1
8078 22:54:13.659210 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8079 22:54:13.659667 ==
8080 22:54:13.662839 Write leveling (Byte 0): 33 => 33
8081 22:54:13.666362 Write leveling (Byte 1): 27 => 27
8082 22:54:13.669871 DramcWriteLeveling(PI) end<-----
8083 22:54:13.670498
8084 22:54:13.671024 ==
8085 22:54:13.672615 Dram Type= 6, Freq= 0, CH_0, rank 1
8086 22:54:13.679213 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8087 22:54:13.679670 ==
8088 22:54:13.680029 [Gating] SW mode calibration
8089 22:54:13.689114 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8090 22:54:13.692539 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8091 22:54:13.699246 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8092 22:54:13.702599 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8093 22:54:13.705623 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8094 22:54:13.709107 1 4 12 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
8095 22:54:13.715628 1 4 16 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
8096 22:54:13.718756 1 4 20 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
8097 22:54:13.725009 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8098 22:54:13.729158 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8099 22:54:13.732122 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8100 22:54:13.738357 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8101 22:54:13.741419 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8102 22:54:13.744974 1 5 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8103 22:54:13.751439 1 5 16 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 1)
8104 22:54:13.754645 1 5 20 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
8105 22:54:13.757679 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8106 22:54:13.764486 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8107 22:54:13.768076 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8108 22:54:13.771475 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8109 22:54:13.777649 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8110 22:54:13.780966 1 6 12 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
8111 22:54:13.784081 1 6 16 | B1->B0 | 2424 4545 | 1 0 | (0 0) (0 0)
8112 22:54:13.790609 1 6 20 | B1->B0 | 3e3e 4646 | 1 0 | (0 0) (0 0)
8113 22:54:13.794578 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8114 22:54:13.797497 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8115 22:54:13.804160 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8116 22:54:13.807310 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8117 22:54:13.810628 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8118 22:54:13.817114 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8119 22:54:13.820200 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8120 22:54:13.823515 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8121 22:54:13.830715 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8122 22:54:13.834024 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8123 22:54:13.836735 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8124 22:54:13.843680 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8125 22:54:13.846523 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8126 22:54:13.850225 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8127 22:54:13.856879 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8128 22:54:13.860192 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8129 22:54:13.862870 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8130 22:54:13.869555 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8131 22:54:13.873001 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8132 22:54:13.876458 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8133 22:54:13.882549 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8134 22:54:13.885867 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8135 22:54:13.889515 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8136 22:54:13.893007 Total UI for P1: 0, mck2ui 16
8137 22:54:13.896420 best dqsien dly found for B0: ( 1, 9, 12)
8138 22:54:13.902601 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8139 22:54:13.905855 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8140 22:54:13.909435 Total UI for P1: 0, mck2ui 16
8141 22:54:13.913054 best dqsien dly found for B1: ( 1, 9, 18)
8142 22:54:13.915762 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8143 22:54:13.919137 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8144 22:54:13.919595
8145 22:54:13.922856 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8146 22:54:13.928790 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8147 22:54:13.929298 [Gating] SW calibration Done
8148 22:54:13.929702 ==
8149 22:54:13.932041 Dram Type= 6, Freq= 0, CH_0, rank 1
8150 22:54:13.938662 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8151 22:54:13.939119 ==
8152 22:54:13.939471 RX Vref Scan: 0
8153 22:54:13.939819
8154 22:54:13.942283 RX Vref 0 -> 0, step: 1
8155 22:54:13.942784
8156 22:54:13.945256 RX Delay 0 -> 252, step: 8
8157 22:54:13.949394 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8158 22:54:13.952129 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8159 22:54:13.955449 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8160 22:54:13.958467 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8161 22:54:13.965268 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8162 22:54:13.968594 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8163 22:54:13.972947 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8164 22:54:13.975323 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8165 22:54:13.981970 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8166 22:54:13.985116 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8167 22:54:13.988451 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8168 22:54:13.991783 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8169 22:54:13.994805 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8170 22:54:14.001450 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8171 22:54:14.005083 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8172 22:54:14.007935 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8173 22:54:14.008442 ==
8174 22:54:14.011239 Dram Type= 6, Freq= 0, CH_0, rank 1
8175 22:54:14.014896 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8176 22:54:14.018236 ==
8177 22:54:14.018698 DQS Delay:
8178 22:54:14.019055 DQS0 = 0, DQS1 = 0
8179 22:54:14.021541 DQM Delay:
8180 22:54:14.022097 DQM0 = 133, DQM1 = 127
8181 22:54:14.024731 DQ Delay:
8182 22:54:14.028281 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =131
8183 22:54:14.031534 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8184 22:54:14.034168 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8185 22:54:14.037774 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
8186 22:54:14.038330
8187 22:54:14.038691
8188 22:54:14.039021 ==
8189 22:54:14.040845 Dram Type= 6, Freq= 0, CH_0, rank 1
8190 22:54:14.044612 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8191 22:54:14.045170 ==
8192 22:54:14.047827
8193 22:54:14.048279
8194 22:54:14.048637 TX Vref Scan disable
8195 22:54:14.050633 == TX Byte 0 ==
8196 22:54:14.054045 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8197 22:54:14.057323 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8198 22:54:14.060819 == TX Byte 1 ==
8199 22:54:14.064097 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8200 22:54:14.067373 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8201 22:54:14.071173 ==
8202 22:54:14.071887 Dram Type= 6, Freq= 0, CH_0, rank 1
8203 22:54:14.077400 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8204 22:54:14.077953 ==
8205 22:54:14.089976
8206 22:54:14.093092 TX Vref early break, caculate TX vref
8207 22:54:14.096183 TX Vref=16, minBit 3, minWin=22, winSum=377
8208 22:54:14.099991 TX Vref=18, minBit 1, minWin=22, winSum=386
8209 22:54:14.102912 TX Vref=20, minBit 1, minWin=23, winSum=389
8210 22:54:14.106391 TX Vref=22, minBit 1, minWin=23, winSum=401
8211 22:54:14.109154 TX Vref=24, minBit 1, minWin=24, winSum=410
8212 22:54:14.116258 TX Vref=26, minBit 0, minWin=25, winSum=412
8213 22:54:14.119279 TX Vref=28, minBit 1, minWin=24, winSum=410
8214 22:54:14.122656 TX Vref=30, minBit 0, minWin=24, winSum=400
8215 22:54:14.125909 TX Vref=32, minBit 4, minWin=23, winSum=396
8216 22:54:14.129712 TX Vref=34, minBit 2, minWin=23, winSum=389
8217 22:54:14.135907 [TxChooseVref] Worse bit 0, Min win 25, Win sum 412, Final Vref 26
8218 22:54:14.136464
8219 22:54:14.139120 Final TX Range 0 Vref 26
8220 22:54:14.139587
8221 22:54:14.140054 ==
8222 22:54:14.142104 Dram Type= 6, Freq= 0, CH_0, rank 1
8223 22:54:14.145504 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8224 22:54:14.145975 ==
8225 22:54:14.146444
8226 22:54:14.147006
8227 22:54:14.149517 TX Vref Scan disable
8228 22:54:14.155547 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8229 22:54:14.156017 == TX Byte 0 ==
8230 22:54:14.158853 u2DelayCellOfst[0]=18 cells (5 PI)
8231 22:54:14.161909 u2DelayCellOfst[1]=22 cells (6 PI)
8232 22:54:14.165683 u2DelayCellOfst[2]=14 cells (4 PI)
8233 22:54:14.168907 u2DelayCellOfst[3]=18 cells (5 PI)
8234 22:54:14.172057 u2DelayCellOfst[4]=11 cells (3 PI)
8235 22:54:14.175428 u2DelayCellOfst[5]=0 cells (0 PI)
8236 22:54:14.178698 u2DelayCellOfst[6]=22 cells (6 PI)
8237 22:54:14.181907 u2DelayCellOfst[7]=22 cells (6 PI)
8238 22:54:14.185432 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8239 22:54:14.188629 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8240 22:54:14.191902 == TX Byte 1 ==
8241 22:54:14.195481 u2DelayCellOfst[8]=0 cells (0 PI)
8242 22:54:14.198385 u2DelayCellOfst[9]=7 cells (2 PI)
8243 22:54:14.201494 u2DelayCellOfst[10]=11 cells (3 PI)
8244 22:54:14.205082 u2DelayCellOfst[11]=7 cells (2 PI)
8245 22:54:14.208210 u2DelayCellOfst[12]=14 cells (4 PI)
8246 22:54:14.208662 u2DelayCellOfst[13]=14 cells (4 PI)
8247 22:54:14.211500 u2DelayCellOfst[14]=22 cells (6 PI)
8248 22:54:14.214799 u2DelayCellOfst[15]=14 cells (4 PI)
8249 22:54:14.221518 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8250 22:54:14.224558 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8251 22:54:14.228353 DramC Write-DBI on
8252 22:54:14.228899 ==
8253 22:54:14.231747 Dram Type= 6, Freq= 0, CH_0, rank 1
8254 22:54:14.235112 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8255 22:54:14.235600 ==
8256 22:54:14.236010
8257 22:54:14.236347
8258 22:54:14.238358 TX Vref Scan disable
8259 22:54:14.238807 == TX Byte 0 ==
8260 22:54:14.245008 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8261 22:54:14.245594 == TX Byte 1 ==
8262 22:54:14.247606 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8263 22:54:14.251083 DramC Write-DBI off
8264 22:54:14.251636
8265 22:54:14.251993 [DATLAT]
8266 22:54:14.254172 Freq=1600, CH0 RK1
8267 22:54:14.254645
8268 22:54:14.255021 DATLAT Default: 0xf
8269 22:54:14.257674 0, 0xFFFF, sum = 0
8270 22:54:14.260556 1, 0xFFFF, sum = 0
8271 22:54:14.261014 2, 0xFFFF, sum = 0
8272 22:54:14.264029 3, 0xFFFF, sum = 0
8273 22:54:14.264487 4, 0xFFFF, sum = 0
8274 22:54:14.267431 5, 0xFFFF, sum = 0
8275 22:54:14.267935 6, 0xFFFF, sum = 0
8276 22:54:14.270547 7, 0xFFFF, sum = 0
8277 22:54:14.271020 8, 0xFFFF, sum = 0
8278 22:54:14.274311 9, 0xFFFF, sum = 0
8279 22:54:14.274878 10, 0xFFFF, sum = 0
8280 22:54:14.276983 11, 0xFFFF, sum = 0
8281 22:54:14.277486 12, 0xFFFF, sum = 0
8282 22:54:14.280527 13, 0xFFFF, sum = 0
8283 22:54:14.281032 14, 0x0, sum = 1
8284 22:54:14.283618 15, 0x0, sum = 2
8285 22:54:14.284109 16, 0x0, sum = 3
8286 22:54:14.287594 17, 0x0, sum = 4
8287 22:54:14.288149 best_step = 15
8288 22:54:14.288508
8289 22:54:14.288838 ==
8290 22:54:14.290647 Dram Type= 6, Freq= 0, CH_0, rank 1
8291 22:54:14.296936 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8292 22:54:14.297541 ==
8293 22:54:14.297913 RX Vref Scan: 0
8294 22:54:14.298297
8295 22:54:14.299950 RX Vref 0 -> 0, step: 1
8296 22:54:14.300404
8297 22:54:14.303582 RX Delay 11 -> 252, step: 4
8298 22:54:14.306931 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8299 22:54:14.309839 iDelay=195, Bit 1, Center 134 (83 ~ 186) 104
8300 22:54:14.316766 iDelay=195, Bit 2, Center 126 (75 ~ 178) 104
8301 22:54:14.320332 iDelay=195, Bit 3, Center 126 (71 ~ 182) 112
8302 22:54:14.323965 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8303 22:54:14.326237 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8304 22:54:14.329924 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8305 22:54:14.336304 iDelay=195, Bit 7, Center 138 (87 ~ 190) 104
8306 22:54:14.340387 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8307 22:54:14.343022 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8308 22:54:14.346188 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8309 22:54:14.349321 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8310 22:54:14.356172 iDelay=195, Bit 12, Center 128 (75 ~ 182) 108
8311 22:54:14.359770 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8312 22:54:14.362823 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8313 22:54:14.366187 iDelay=195, Bit 15, Center 130 (79 ~ 182) 104
8314 22:54:14.366834 ==
8315 22:54:14.369261 Dram Type= 6, Freq= 0, CH_0, rank 1
8316 22:54:14.376384 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8317 22:54:14.376940 ==
8318 22:54:14.377301 DQS Delay:
8319 22:54:14.379445 DQS0 = 0, DQS1 = 0
8320 22:54:14.379992 DQM Delay:
8321 22:54:14.382166 DQM0 = 130, DQM1 = 125
8322 22:54:14.382625 DQ Delay:
8323 22:54:14.385625 DQ0 =128, DQ1 =134, DQ2 =126, DQ3 =126
8324 22:54:14.388936 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =138
8325 22:54:14.392492 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =120
8326 22:54:14.395770 DQ12 =128, DQ13 =132, DQ14 =136, DQ15 =130
8327 22:54:14.396323
8328 22:54:14.396680
8329 22:54:14.397010
8330 22:54:14.399111 [DramC_TX_OE_Calibration] TA2
8331 22:54:14.402525 Original DQ_B0 (3 6) =30, OEN = 27
8332 22:54:14.405619 Original DQ_B1 (3 6) =30, OEN = 27
8333 22:54:14.408749 24, 0x0, End_B0=24 End_B1=24
8334 22:54:14.412291 25, 0x0, End_B0=25 End_B1=25
8335 22:54:14.412866 26, 0x0, End_B0=26 End_B1=26
8336 22:54:14.415779 27, 0x0, End_B0=27 End_B1=27
8337 22:54:14.418882 28, 0x0, End_B0=28 End_B1=28
8338 22:54:14.422260 29, 0x0, End_B0=29 End_B1=29
8339 22:54:14.425512 30, 0x0, End_B0=30 End_B1=30
8340 22:54:14.425993 31, 0x4141, End_B0=30 End_B1=30
8341 22:54:14.428237 Byte0 end_step=30 best_step=27
8342 22:54:14.431762 Byte1 end_step=30 best_step=27
8343 22:54:14.434802 Byte0 TX OE(2T, 0.5T) = (3, 3)
8344 22:54:14.438185 Byte1 TX OE(2T, 0.5T) = (3, 3)
8345 22:54:14.438651
8346 22:54:14.439119
8347 22:54:14.445555 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d01, (MSB)MR19= 0x303, tDQSOscB0 = 409 ps tDQSOscB1 = 395 ps
8348 22:54:14.448308 CH0 RK1: MR19=303, MR18=1D01
8349 22:54:14.455222 CH0_RK1: MR19=0x303, MR18=0x1D01, DQSOSC=395, MR23=63, INC=23, DEC=15
8350 22:54:14.458289 [RxdqsGatingPostProcess] freq 1600
8351 22:54:14.464752 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8352 22:54:14.468433 best DQS0 dly(2T, 0.5T) = (1, 1)
8353 22:54:14.468901 best DQS1 dly(2T, 0.5T) = (1, 1)
8354 22:54:14.471608 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8355 22:54:14.474697 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8356 22:54:14.478166 best DQS0 dly(2T, 0.5T) = (1, 1)
8357 22:54:14.481518 best DQS1 dly(2T, 0.5T) = (1, 1)
8358 22:54:14.484390 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8359 22:54:14.488068 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8360 22:54:14.491004 Pre-setting of DQS Precalculation
8361 22:54:14.497430 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8362 22:54:14.497882 ==
8363 22:54:14.500926 Dram Type= 6, Freq= 0, CH_1, rank 0
8364 22:54:14.504751 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8365 22:54:14.505205 ==
8366 22:54:14.510946 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8367 22:54:14.514525 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8368 22:54:14.517277 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8369 22:54:14.524020 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8370 22:54:14.532689 [CA 0] Center 41 (12~71) winsize 60
8371 22:54:14.535590 [CA 1] Center 42 (12~72) winsize 61
8372 22:54:14.539316 [CA 2] Center 37 (8~66) winsize 59
8373 22:54:14.542852 [CA 3] Center 35 (6~65) winsize 60
8374 22:54:14.545749 [CA 4] Center 36 (7~66) winsize 60
8375 22:54:14.549074 [CA 5] Center 36 (7~66) winsize 60
8376 22:54:14.549513
8377 22:54:14.552486 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8378 22:54:14.552893
8379 22:54:14.555765 [CATrainingPosCal] consider 1 rank data
8380 22:54:14.559197 u2DelayCellTimex100 = 262/100 ps
8381 22:54:14.562279 CA0 delay=41 (12~71),Diff = 6 PI (22 cell)
8382 22:54:14.568712 CA1 delay=42 (12~72),Diff = 7 PI (26 cell)
8383 22:54:14.572069 CA2 delay=37 (8~66),Diff = 2 PI (7 cell)
8384 22:54:14.575647 CA3 delay=35 (6~65),Diff = 0 PI (0 cell)
8385 22:54:14.579142 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
8386 22:54:14.581994 CA5 delay=36 (7~66),Diff = 1 PI (3 cell)
8387 22:54:14.582411
8388 22:54:14.585764 CA PerBit enable=1, Macro0, CA PI delay=35
8389 22:54:14.586172
8390 22:54:14.588584 [CBTSetCACLKResult] CA Dly = 35
8391 22:54:14.591826 CS Dly: 9 (0~40)
8392 22:54:14.595907 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8393 22:54:14.598715 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8394 22:54:14.599132 ==
8395 22:54:14.602398 Dram Type= 6, Freq= 0, CH_1, rank 1
8396 22:54:14.605316 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8397 22:54:14.608493 ==
8398 22:54:14.611815 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8399 22:54:14.614939 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8400 22:54:14.621954 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8401 22:54:14.628005 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8402 22:54:14.635427 [CA 0] Center 43 (14~72) winsize 59
8403 22:54:14.638752 [CA 1] Center 42 (13~72) winsize 60
8404 22:54:14.641886 [CA 2] Center 37 (8~67) winsize 60
8405 22:54:14.645573 [CA 3] Center 37 (7~67) winsize 61
8406 22:54:14.648627 [CA 4] Center 38 (9~67) winsize 59
8407 22:54:14.651837 [CA 5] Center 37 (8~67) winsize 60
8408 22:54:14.652251
8409 22:54:14.655162 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8410 22:54:14.655664
8411 22:54:14.661768 [CATrainingPosCal] consider 2 rank data
8412 22:54:14.662307 u2DelayCellTimex100 = 262/100 ps
8413 22:54:14.668503 CA0 delay=42 (14~71),Diff = 6 PI (22 cell)
8414 22:54:14.671721 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8415 22:54:14.675214 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8416 22:54:14.678602 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8417 22:54:14.681429 CA4 delay=37 (9~66),Diff = 1 PI (3 cell)
8418 22:54:14.684729 CA5 delay=37 (8~66),Diff = 1 PI (3 cell)
8419 22:54:14.685144
8420 22:54:14.688668 CA PerBit enable=1, Macro0, CA PI delay=36
8421 22:54:14.689083
8422 22:54:14.691598 [CBTSetCACLKResult] CA Dly = 36
8423 22:54:14.694785 CS Dly: 10 (0~43)
8424 22:54:14.697832 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8425 22:54:14.701615 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8426 22:54:14.702058
8427 22:54:14.704514 ----->DramcWriteLeveling(PI) begin...
8428 22:54:14.704933 ==
8429 22:54:14.707817 Dram Type= 6, Freq= 0, CH_1, rank 0
8430 22:54:14.714280 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8431 22:54:14.714697 ==
8432 22:54:14.717869 Write leveling (Byte 0): 23 => 23
8433 22:54:14.720961 Write leveling (Byte 1): 26 => 26
8434 22:54:14.724007 DramcWriteLeveling(PI) end<-----
8435 22:54:14.724535
8436 22:54:14.724959 ==
8437 22:54:14.727551 Dram Type= 6, Freq= 0, CH_1, rank 0
8438 22:54:14.731006 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8439 22:54:14.731514 ==
8440 22:54:14.734483 [Gating] SW mode calibration
8441 22:54:14.740558 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8442 22:54:14.747378 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8443 22:54:14.751007 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8444 22:54:14.753994 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8445 22:54:14.760728 1 4 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
8446 22:54:14.764078 1 4 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8447 22:54:14.767090 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8448 22:54:14.774236 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8449 22:54:14.777264 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8450 22:54:14.780631 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8451 22:54:14.787437 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8452 22:54:14.790538 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8453 22:54:14.793634 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8454 22:54:14.800207 1 5 12 | B1->B0 | 2828 2424 | 0 0 | (1 0) (1 0)
8455 22:54:14.803296 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8456 22:54:14.806839 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8457 22:54:14.813571 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8458 22:54:14.816970 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8459 22:54:14.820228 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8460 22:54:14.826915 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8461 22:54:14.830163 1 6 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8462 22:54:14.833485 1 6 12 | B1->B0 | 3130 4343 | 1 0 | (0 0) (0 0)
8463 22:54:14.839813 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8464 22:54:14.843323 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8465 22:54:14.846948 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8466 22:54:14.853487 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8467 22:54:14.856457 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8468 22:54:14.859320 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8469 22:54:14.866313 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8470 22:54:14.869500 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8471 22:54:14.873022 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8472 22:54:14.876072 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8473 22:54:14.882770 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8474 22:54:14.886167 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8475 22:54:14.889265 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8476 22:54:14.896343 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8477 22:54:14.899256 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8478 22:54:14.902454 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8479 22:54:14.909181 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8480 22:54:14.912999 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8481 22:54:14.916152 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8482 22:54:14.922887 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8483 22:54:14.926031 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8484 22:54:14.929546 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8485 22:54:14.935860 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8486 22:54:14.939157 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8487 22:54:14.942346 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8488 22:54:14.945493 Total UI for P1: 0, mck2ui 16
8489 22:54:14.949053 best dqsien dly found for B0: ( 1, 9, 10)
8490 22:54:14.952333 Total UI for P1: 0, mck2ui 16
8491 22:54:14.955437 best dqsien dly found for B1: ( 1, 9, 12)
8492 22:54:14.958517 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8493 22:54:14.965003 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8494 22:54:14.965505
8495 22:54:14.968399 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8496 22:54:14.971749 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8497 22:54:14.975097 [Gating] SW calibration Done
8498 22:54:14.975552 ==
8499 22:54:14.978656 Dram Type= 6, Freq= 0, CH_1, rank 0
8500 22:54:14.982200 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8501 22:54:14.982759 ==
8502 22:54:14.984710 RX Vref Scan: 0
8503 22:54:14.985173
8504 22:54:14.985598 RX Vref 0 -> 0, step: 1
8505 22:54:14.985957
8506 22:54:14.988342 RX Delay 0 -> 252, step: 8
8507 22:54:14.992001 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8508 22:54:14.998096 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8509 22:54:15.001252 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8510 22:54:15.005032 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8511 22:54:15.007941 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8512 22:54:15.011538 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8513 22:54:15.017803 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8514 22:54:15.021572 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8515 22:54:15.024807 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8516 22:54:15.027822 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8517 22:54:15.031825 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8518 22:54:15.037681 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8519 22:54:15.041023 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8520 22:54:15.044781 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8521 22:54:15.047793 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8522 22:54:15.051108 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8523 22:54:15.054456 ==
8524 22:54:15.057466 Dram Type= 6, Freq= 0, CH_1, rank 0
8525 22:54:15.061519 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8526 22:54:15.062081 ==
8527 22:54:15.062446 DQS Delay:
8528 22:54:15.064410 DQS0 = 0, DQS1 = 0
8529 22:54:15.064869 DQM Delay:
8530 22:54:15.068070 DQM0 = 136, DQM1 = 128
8531 22:54:15.068662 DQ Delay:
8532 22:54:15.070622 DQ0 =139, DQ1 =131, DQ2 =127, DQ3 =135
8533 22:54:15.074281 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8534 22:54:15.077304 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8535 22:54:15.080442 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =135
8536 22:54:15.080901
8537 22:54:15.081260
8538 22:54:15.084331 ==
8539 22:54:15.087093 Dram Type= 6, Freq= 0, CH_1, rank 0
8540 22:54:15.090193 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8541 22:54:15.090660 ==
8542 22:54:15.091127
8543 22:54:15.091714
8544 22:54:15.093723 TX Vref Scan disable
8545 22:54:15.094179 == TX Byte 0 ==
8546 22:54:15.100262 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8547 22:54:15.103236 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8548 22:54:15.103743 == TX Byte 1 ==
8549 22:54:15.110160 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8550 22:54:15.113426 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8551 22:54:15.113875 ==
8552 22:54:15.117005 Dram Type= 6, Freq= 0, CH_1, rank 0
8553 22:54:15.119897 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8554 22:54:15.120379 ==
8555 22:54:15.133819
8556 22:54:15.136836 TX Vref early break, caculate TX vref
8557 22:54:15.140075 TX Vref=16, minBit 0, minWin=21, winSum=375
8558 22:54:15.143218 TX Vref=18, minBit 0, minWin=22, winSum=384
8559 22:54:15.146337 TX Vref=20, minBit 0, minWin=22, winSum=388
8560 22:54:15.149720 TX Vref=22, minBit 0, minWin=23, winSum=405
8561 22:54:15.153368 TX Vref=24, minBit 0, minWin=23, winSum=411
8562 22:54:15.159990 TX Vref=26, minBit 0, minWin=25, winSum=418
8563 22:54:15.162920 TX Vref=28, minBit 5, minWin=24, winSum=421
8564 22:54:15.166187 TX Vref=30, minBit 1, minWin=24, winSum=411
8565 22:54:15.169772 TX Vref=32, minBit 0, minWin=24, winSum=403
8566 22:54:15.172774 TX Vref=34, minBit 5, minWin=22, winSum=393
8567 22:54:15.179375 [TxChooseVref] Worse bit 0, Min win 25, Win sum 418, Final Vref 26
8568 22:54:15.179836
8569 22:54:15.183217 Final TX Range 0 Vref 26
8570 22:54:15.183637
8571 22:54:15.183968 ==
8572 22:54:15.186090 Dram Type= 6, Freq= 0, CH_1, rank 0
8573 22:54:15.189428 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8574 22:54:15.189851 ==
8575 22:54:15.190178
8576 22:54:15.190483
8577 22:54:15.192470 TX Vref Scan disable
8578 22:54:15.199188 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8579 22:54:15.199714 == TX Byte 0 ==
8580 22:54:15.202488 u2DelayCellOfst[0]=14 cells (4 PI)
8581 22:54:15.206121 u2DelayCellOfst[1]=11 cells (3 PI)
8582 22:54:15.209129 u2DelayCellOfst[2]=0 cells (0 PI)
8583 22:54:15.212898 u2DelayCellOfst[3]=3 cells (1 PI)
8584 22:54:15.216143 u2DelayCellOfst[4]=7 cells (2 PI)
8585 22:54:15.219421 u2DelayCellOfst[5]=18 cells (5 PI)
8586 22:54:15.222361 u2DelayCellOfst[6]=18 cells (5 PI)
8587 22:54:15.225594 u2DelayCellOfst[7]=3 cells (1 PI)
8588 22:54:15.229121 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8589 22:54:15.231927 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8590 22:54:15.235448 == TX Byte 1 ==
8591 22:54:15.239143 u2DelayCellOfst[8]=0 cells (0 PI)
8592 22:54:15.242242 u2DelayCellOfst[9]=3 cells (1 PI)
8593 22:54:15.242798 u2DelayCellOfst[10]=11 cells (3 PI)
8594 22:54:15.245135 u2DelayCellOfst[11]=3 cells (1 PI)
8595 22:54:15.248553 u2DelayCellOfst[12]=14 cells (4 PI)
8596 22:54:15.252510 u2DelayCellOfst[13]=14 cells (4 PI)
8597 22:54:15.255434 u2DelayCellOfst[14]=18 cells (5 PI)
8598 22:54:15.258371 u2DelayCellOfst[15]=18 cells (5 PI)
8599 22:54:15.264966 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8600 22:54:15.268645 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8601 22:54:15.269181 DramC Write-DBI on
8602 22:54:15.271695 ==
8603 22:54:15.272114 Dram Type= 6, Freq= 0, CH_1, rank 0
8604 22:54:15.278511 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8605 22:54:15.279038 ==
8606 22:54:15.279373
8607 22:54:15.279680
8608 22:54:15.281605 TX Vref Scan disable
8609 22:54:15.282027 == TX Byte 0 ==
8610 22:54:15.288232 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8611 22:54:15.288756 == TX Byte 1 ==
8612 22:54:15.291682 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8613 22:54:15.294460 DramC Write-DBI off
8614 22:54:15.294879
8615 22:54:15.295265 [DATLAT]
8616 22:54:15.297923 Freq=1600, CH1 RK0
8617 22:54:15.298342
8618 22:54:15.298669 DATLAT Default: 0xf
8619 22:54:15.301239 0, 0xFFFF, sum = 0
8620 22:54:15.301885 1, 0xFFFF, sum = 0
8621 22:54:15.304722 2, 0xFFFF, sum = 0
8622 22:54:15.305140 3, 0xFFFF, sum = 0
8623 22:54:15.308025 4, 0xFFFF, sum = 0
8624 22:54:15.308442 5, 0xFFFF, sum = 0
8625 22:54:15.311399 6, 0xFFFF, sum = 0
8626 22:54:15.314185 7, 0xFFFF, sum = 0
8627 22:54:15.314651 8, 0xFFFF, sum = 0
8628 22:54:15.317858 9, 0xFFFF, sum = 0
8629 22:54:15.318424 10, 0xFFFF, sum = 0
8630 22:54:15.321474 11, 0xFFFF, sum = 0
8631 22:54:15.321940 12, 0xFFFF, sum = 0
8632 22:54:15.324334 13, 0xFFFF, sum = 0
8633 22:54:15.324798 14, 0x0, sum = 1
8634 22:54:15.327611 15, 0x0, sum = 2
8635 22:54:15.328080 16, 0x0, sum = 3
8636 22:54:15.331576 17, 0x0, sum = 4
8637 22:54:15.332148 best_step = 15
8638 22:54:15.332515
8639 22:54:15.332854 ==
8640 22:54:15.334494 Dram Type= 6, Freq= 0, CH_1, rank 0
8641 22:54:15.338051 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8642 22:54:15.341015 ==
8643 22:54:15.341510 RX Vref Scan: 1
8644 22:54:15.341944
8645 22:54:15.344438 Set Vref Range= 24 -> 127
8646 22:54:15.345003
8647 22:54:15.345423 RX Vref 24 -> 127, step: 1
8648 22:54:15.347491
8649 22:54:15.347983 RX Delay 11 -> 252, step: 4
8650 22:54:15.348484
8651 22:54:15.351171 Set Vref, RX VrefLevel [Byte0]: 24
8652 22:54:15.354122 [Byte1]: 24
8653 22:54:15.357846
8654 22:54:15.358320 Set Vref, RX VrefLevel [Byte0]: 25
8655 22:54:15.361484 [Byte1]: 25
8656 22:54:15.365646
8657 22:54:15.366125 Set Vref, RX VrefLevel [Byte0]: 26
8658 22:54:15.368653 [Byte1]: 26
8659 22:54:15.373113
8660 22:54:15.373731 Set Vref, RX VrefLevel [Byte0]: 27
8661 22:54:15.376415 [Byte1]: 27
8662 22:54:15.380958
8663 22:54:15.381594 Set Vref, RX VrefLevel [Byte0]: 28
8664 22:54:15.384484 [Byte1]: 28
8665 22:54:15.388494
8666 22:54:15.388979 Set Vref, RX VrefLevel [Byte0]: 29
8667 22:54:15.391272 [Byte1]: 29
8668 22:54:15.396156
8669 22:54:15.396729 Set Vref, RX VrefLevel [Byte0]: 30
8670 22:54:15.399080 [Byte1]: 30
8671 22:54:15.403860
8672 22:54:15.404418 Set Vref, RX VrefLevel [Byte0]: 31
8673 22:54:15.406381 [Byte1]: 31
8674 22:54:15.411216
8675 22:54:15.411790 Set Vref, RX VrefLevel [Byte0]: 32
8676 22:54:15.414768 [Byte1]: 32
8677 22:54:15.418944
8678 22:54:15.419520 Set Vref, RX VrefLevel [Byte0]: 33
8679 22:54:15.421923 [Byte1]: 33
8680 22:54:15.426328
8681 22:54:15.426922 Set Vref, RX VrefLevel [Byte0]: 34
8682 22:54:15.429830 [Byte1]: 34
8683 22:54:15.434001
8684 22:54:15.434594 Set Vref, RX VrefLevel [Byte0]: 35
8685 22:54:15.440453 [Byte1]: 35
8686 22:54:15.441192
8687 22:54:15.443809 Set Vref, RX VrefLevel [Byte0]: 36
8688 22:54:15.446910 [Byte1]: 36
8689 22:54:15.447477
8690 22:54:15.450047 Set Vref, RX VrefLevel [Byte0]: 37
8691 22:54:15.453136 [Byte1]: 37
8692 22:54:15.457046
8693 22:54:15.457556 Set Vref, RX VrefLevel [Byte0]: 38
8694 22:54:15.460049 [Byte1]: 38
8695 22:54:15.464036
8696 22:54:15.464493 Set Vref, RX VrefLevel [Byte0]: 39
8697 22:54:15.467786 [Byte1]: 39
8698 22:54:15.471970
8699 22:54:15.472433 Set Vref, RX VrefLevel [Byte0]: 40
8700 22:54:15.475490 [Byte1]: 40
8701 22:54:15.479907
8702 22:54:15.480475 Set Vref, RX VrefLevel [Byte0]: 41
8703 22:54:15.483100 [Byte1]: 41
8704 22:54:15.487186
8705 22:54:15.487846 Set Vref, RX VrefLevel [Byte0]: 42
8706 22:54:15.490393 [Byte1]: 42
8707 22:54:15.494692
8708 22:54:15.495151 Set Vref, RX VrefLevel [Byte0]: 43
8709 22:54:15.498323 [Byte1]: 43
8710 22:54:15.502718
8711 22:54:15.503175 Set Vref, RX VrefLevel [Byte0]: 44
8712 22:54:15.505958 [Byte1]: 44
8713 22:54:15.510112
8714 22:54:15.510911 Set Vref, RX VrefLevel [Byte0]: 45
8715 22:54:15.513298 [Byte1]: 45
8716 22:54:15.517773
8717 22:54:15.518332 Set Vref, RX VrefLevel [Byte0]: 46
8718 22:54:15.521367 [Byte1]: 46
8719 22:54:15.525257
8720 22:54:15.525857 Set Vref, RX VrefLevel [Byte0]: 47
8721 22:54:15.528675 [Byte1]: 47
8722 22:54:15.533157
8723 22:54:15.533770 Set Vref, RX VrefLevel [Byte0]: 48
8724 22:54:15.539658 [Byte1]: 48
8725 22:54:15.540213
8726 22:54:15.542589 Set Vref, RX VrefLevel [Byte0]: 49
8727 22:54:15.546034 [Byte1]: 49
8728 22:54:15.546616
8729 22:54:15.549189 Set Vref, RX VrefLevel [Byte0]: 50
8730 22:54:15.552778 [Byte1]: 50
8731 22:54:15.555759
8732 22:54:15.556309 Set Vref, RX VrefLevel [Byte0]: 51
8733 22:54:15.558886 [Byte1]: 51
8734 22:54:15.563669
8735 22:54:15.564125 Set Vref, RX VrefLevel [Byte0]: 52
8736 22:54:15.566643 [Byte1]: 52
8737 22:54:15.571077
8738 22:54:15.571631 Set Vref, RX VrefLevel [Byte0]: 53
8739 22:54:15.574082 [Byte1]: 53
8740 22:54:15.578646
8741 22:54:15.579105 Set Vref, RX VrefLevel [Byte0]: 54
8742 22:54:15.582250 [Byte1]: 54
8743 22:54:15.586292
8744 22:54:15.586841 Set Vref, RX VrefLevel [Byte0]: 55
8745 22:54:15.589155 [Byte1]: 55
8746 22:54:15.594103
8747 22:54:15.594661 Set Vref, RX VrefLevel [Byte0]: 56
8748 22:54:15.597217 [Byte1]: 56
8749 22:54:15.601948
8750 22:54:15.602590 Set Vref, RX VrefLevel [Byte0]: 57
8751 22:54:15.604499 [Byte1]: 57
8752 22:54:15.609498
8753 22:54:15.610067 Set Vref, RX VrefLevel [Byte0]: 58
8754 22:54:15.612628 [Byte1]: 58
8755 22:54:15.616695
8756 22:54:15.617250 Set Vref, RX VrefLevel [Byte0]: 59
8757 22:54:15.619678 [Byte1]: 59
8758 22:54:15.624477
8759 22:54:15.625033 Set Vref, RX VrefLevel [Byte0]: 60
8760 22:54:15.627283 [Byte1]: 60
8761 22:54:15.632145
8762 22:54:15.632703 Set Vref, RX VrefLevel [Byte0]: 61
8763 22:54:15.638249 [Byte1]: 61
8764 22:54:15.638854
8765 22:54:15.641837 Set Vref, RX VrefLevel [Byte0]: 62
8766 22:54:15.644625 [Byte1]: 62
8767 22:54:15.645087
8768 22:54:15.648044 Set Vref, RX VrefLevel [Byte0]: 63
8769 22:54:15.651622 [Byte1]: 63
8770 22:54:15.654473
8771 22:54:15.654930 Set Vref, RX VrefLevel [Byte0]: 64
8772 22:54:15.658301 [Byte1]: 64
8773 22:54:15.662285
8774 22:54:15.662848 Set Vref, RX VrefLevel [Byte0]: 65
8775 22:54:15.665395 [Byte1]: 65
8776 22:54:15.670034
8777 22:54:15.670585 Set Vref, RX VrefLevel [Byte0]: 66
8778 22:54:15.673585 [Byte1]: 66
8779 22:54:15.677696
8780 22:54:15.678255 Set Vref, RX VrefLevel [Byte0]: 67
8781 22:54:15.680701 [Byte1]: 67
8782 22:54:15.685402
8783 22:54:15.685957 Set Vref, RX VrefLevel [Byte0]: 68
8784 22:54:15.688821 [Byte1]: 68
8785 22:54:15.692510
8786 22:54:15.692967 Set Vref, RX VrefLevel [Byte0]: 69
8787 22:54:15.695787 [Byte1]: 69
8788 22:54:15.700571
8789 22:54:15.701028 Set Vref, RX VrefLevel [Byte0]: 70
8790 22:54:15.703881 [Byte1]: 70
8791 22:54:15.707873
8792 22:54:15.708353 Set Vref, RX VrefLevel [Byte0]: 71
8793 22:54:15.711277 [Byte1]: 71
8794 22:54:15.715826
8795 22:54:15.716287 Set Vref, RX VrefLevel [Byte0]: 72
8796 22:54:15.719001 [Byte1]: 72
8797 22:54:15.723298
8798 22:54:15.724091 Set Vref, RX VrefLevel [Byte0]: 73
8799 22:54:15.726727 [Byte1]: 73
8800 22:54:15.730519
8801 22:54:15.731080 Set Vref, RX VrefLevel [Byte0]: 74
8802 22:54:15.736958 [Byte1]: 74
8803 22:54:15.737522
8804 22:54:15.740359 Final RX Vref Byte 0 = 55 to rank0
8805 22:54:15.743735 Final RX Vref Byte 1 = 59 to rank0
8806 22:54:15.746741 Final RX Vref Byte 0 = 55 to rank1
8807 22:54:15.750247 Final RX Vref Byte 1 = 59 to rank1==
8808 22:54:15.753664 Dram Type= 6, Freq= 0, CH_1, rank 0
8809 22:54:15.757071 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8810 22:54:15.757705 ==
8811 22:54:15.758045 DQS Delay:
8812 22:54:15.760392 DQS0 = 0, DQS1 = 0
8813 22:54:15.760865 DQM Delay:
8814 22:54:15.763438 DQM0 = 133, DQM1 = 127
8815 22:54:15.763853 DQ Delay:
8816 22:54:15.766802 DQ0 =138, DQ1 =126, DQ2 =124, DQ3 =130
8817 22:54:15.770193 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =128
8818 22:54:15.773504 DQ8 =114, DQ9 =116, DQ10 =130, DQ11 =116
8819 22:54:15.776822 DQ12 =136, DQ13 =136, DQ14 =136, DQ15 =138
8820 22:54:15.777240
8821 22:54:15.780223
8822 22:54:15.780638
8823 22:54:15.780967 [DramC_TX_OE_Calibration] TA2
8824 22:54:15.783548 Original DQ_B0 (3 6) =30, OEN = 27
8825 22:54:15.786590 Original DQ_B1 (3 6) =30, OEN = 27
8826 22:54:15.789923 24, 0x0, End_B0=24 End_B1=24
8827 22:54:15.793497 25, 0x0, End_B0=25 End_B1=25
8828 22:54:15.796168 26, 0x0, End_B0=26 End_B1=26
8829 22:54:15.796654 27, 0x0, End_B0=27 End_B1=27
8830 22:54:15.799859 28, 0x0, End_B0=28 End_B1=28
8831 22:54:15.803049 29, 0x0, End_B0=29 End_B1=29
8832 22:54:15.806195 30, 0x0, End_B0=30 End_B1=30
8833 22:54:15.809878 31, 0x4141, End_B0=30 End_B1=30
8834 22:54:15.812842 Byte0 end_step=30 best_step=27
8835 22:54:15.813253 Byte1 end_step=30 best_step=27
8836 22:54:15.816457 Byte0 TX OE(2T, 0.5T) = (3, 3)
8837 22:54:15.819618 Byte1 TX OE(2T, 0.5T) = (3, 3)
8838 22:54:15.820034
8839 22:54:15.820354
8840 22:54:15.829240 [DQSOSCAuto] RK0, (LSB)MR18= 0x170c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 398 ps
8841 22:54:15.829711 CH1 RK0: MR19=303, MR18=170C
8842 22:54:15.836071 CH1_RK0: MR19=0x303, MR18=0x170C, DQSOSC=398, MR23=63, INC=23, DEC=15
8843 22:54:15.836487
8844 22:54:15.839184 ----->DramcWriteLeveling(PI) begin...
8845 22:54:15.839611 ==
8846 22:54:15.842549 Dram Type= 6, Freq= 0, CH_1, rank 1
8847 22:54:15.849033 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8848 22:54:15.849634 ==
8849 22:54:15.852854 Write leveling (Byte 0): 24 => 24
8850 22:54:15.855565 Write leveling (Byte 1): 26 => 26
8851 22:54:15.858728 DramcWriteLeveling(PI) end<-----
8852 22:54:15.859152
8853 22:54:15.859509 ==
8854 22:54:15.862171 Dram Type= 6, Freq= 0, CH_1, rank 1
8855 22:54:15.865709 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8856 22:54:15.866133 ==
8857 22:54:15.868576 [Gating] SW mode calibration
8858 22:54:15.875294 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8859 22:54:15.881743 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8860 22:54:15.885013 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8861 22:54:15.888903 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8862 22:54:15.895644 1 4 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8863 22:54:15.898512 1 4 12 | B1->B0 | 3434 2322 | 0 1 | (0 0) (0 0)
8864 22:54:15.901742 1 4 16 | B1->B0 | 3434 3433 | 1 1 | (1 1) (1 1)
8865 22:54:15.908830 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8866 22:54:15.911802 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8867 22:54:15.915217 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8868 22:54:15.919067 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8869 22:54:15.925135 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8870 22:54:15.928293 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8871 22:54:15.931496 1 5 12 | B1->B0 | 2424 3434 | 0 1 | (1 0) (1 0)
8872 22:54:15.938115 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8873 22:54:15.941634 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8874 22:54:15.945176 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8875 22:54:15.951722 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8876 22:54:15.954488 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8877 22:54:15.958035 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8878 22:54:15.964814 1 6 8 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
8879 22:54:15.967784 1 6 12 | B1->B0 | 4545 2424 | 1 0 | (0 0) (0 0)
8880 22:54:15.971245 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8881 22:54:15.977853 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8882 22:54:15.981453 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8883 22:54:15.984787 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8884 22:54:15.991209 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8885 22:54:15.994296 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8886 22:54:15.997439 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8887 22:54:16.003941 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8888 22:54:16.008236 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8889 22:54:16.010605 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8890 22:54:16.017420 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8891 22:54:16.021085 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8892 22:54:16.023858 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8893 22:54:16.030257 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8894 22:54:16.033640 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8895 22:54:16.040134 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8896 22:54:16.043524 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8897 22:54:16.047074 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8898 22:54:16.050133 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8899 22:54:16.056767 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8900 22:54:16.060414 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8901 22:54:16.063750 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8902 22:54:16.070173 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8903 22:54:16.073697 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8904 22:54:16.076869 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8905 22:54:16.080300 Total UI for P1: 0, mck2ui 16
8906 22:54:16.083018 best dqsien dly found for B0: ( 1, 9, 10)
8907 22:54:16.086578 Total UI for P1: 0, mck2ui 16
8908 22:54:16.089869 best dqsien dly found for B1: ( 1, 9, 10)
8909 22:54:16.096269 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8910 22:54:16.099846 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8911 22:54:16.100437
8912 22:54:16.102850 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8913 22:54:16.106462 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8914 22:54:16.109695 [Gating] SW calibration Done
8915 22:54:16.110155 ==
8916 22:54:16.112912 Dram Type= 6, Freq= 0, CH_1, rank 1
8917 22:54:16.116194 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8918 22:54:16.116750 ==
8919 22:54:16.119311 RX Vref Scan: 0
8920 22:54:16.119767
8921 22:54:16.120123 RX Vref 0 -> 0, step: 1
8922 22:54:16.120458
8923 22:54:16.122519 RX Delay 0 -> 252, step: 8
8924 22:54:16.125935 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8925 22:54:16.132715 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8926 22:54:16.136336 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8927 22:54:16.139399 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8928 22:54:16.142708 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8929 22:54:16.145578 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8930 22:54:16.152503 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8931 22:54:16.155538 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8932 22:54:16.159003 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8933 22:54:16.162523 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8934 22:54:16.165488 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8935 22:54:16.172348 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8936 22:54:16.175178 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8937 22:54:16.178602 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8938 22:54:16.182227 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8939 22:54:16.188505 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8940 22:54:16.189055 ==
8941 22:54:16.191870 Dram Type= 6, Freq= 0, CH_1, rank 1
8942 22:54:16.194894 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8943 22:54:16.195353 ==
8944 22:54:16.195712 DQS Delay:
8945 22:54:16.198550 DQS0 = 0, DQS1 = 0
8946 22:54:16.199100 DQM Delay:
8947 22:54:16.201802 DQM0 = 136, DQM1 = 129
8948 22:54:16.202262 DQ Delay:
8949 22:54:16.205460 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8950 22:54:16.208603 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8951 22:54:16.211500 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8952 22:54:16.215625 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8953 22:54:16.216184
8954 22:54:16.218138
8955 22:54:16.218592 ==
8956 22:54:16.221691 Dram Type= 6, Freq= 0, CH_1, rank 1
8957 22:54:16.225039 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8958 22:54:16.225653 ==
8959 22:54:16.226047
8960 22:54:16.226651
8961 22:54:16.227984 TX Vref Scan disable
8962 22:54:16.228454 == TX Byte 0 ==
8963 22:54:16.235103 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8964 22:54:16.238295 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8965 22:54:16.238856 == TX Byte 1 ==
8966 22:54:16.244907 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8967 22:54:16.248194 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8968 22:54:16.248755 ==
8969 22:54:16.251338 Dram Type= 6, Freq= 0, CH_1, rank 1
8970 22:54:16.255107 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8971 22:54:16.255677 ==
8972 22:54:16.268991
8973 22:54:16.272370 TX Vref early break, caculate TX vref
8974 22:54:16.275830 TX Vref=16, minBit 1, minWin=22, winSum=383
8975 22:54:16.278597 TX Vref=18, minBit 0, minWin=24, winSum=394
8976 22:54:16.282177 TX Vref=20, minBit 1, minWin=24, winSum=404
8977 22:54:16.285384 TX Vref=22, minBit 1, minWin=25, winSum=412
8978 22:54:16.289139 TX Vref=24, minBit 0, minWin=25, winSum=420
8979 22:54:16.295597 TX Vref=26, minBit 0, minWin=25, winSum=425
8980 22:54:16.298981 TX Vref=28, minBit 0, minWin=24, winSum=423
8981 22:54:16.302049 TX Vref=30, minBit 1, minWin=24, winSum=416
8982 22:54:16.305312 TX Vref=32, minBit 1, minWin=24, winSum=412
8983 22:54:16.308604 TX Vref=34, minBit 0, minWin=23, winSum=403
8984 22:54:16.315710 TX Vref=36, minBit 0, minWin=23, winSum=392
8985 22:54:16.318849 [TxChooseVref] Worse bit 0, Min win 25, Win sum 425, Final Vref 26
8986 22:54:16.319418
8987 22:54:16.321839 Final TX Range 0 Vref 26
8988 22:54:16.322296
8989 22:54:16.322727 ==
8990 22:54:16.324959 Dram Type= 6, Freq= 0, CH_1, rank 1
8991 22:54:16.328149 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8992 22:54:16.331242 ==
8993 22:54:16.331698
8994 22:54:16.332056
8995 22:54:16.332400 TX Vref Scan disable
8996 22:54:16.338295 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8997 22:54:16.338872 == TX Byte 0 ==
8998 22:54:16.341390 u2DelayCellOfst[0]=22 cells (6 PI)
8999 22:54:16.344667 u2DelayCellOfst[1]=11 cells (3 PI)
9000 22:54:16.348113 u2DelayCellOfst[2]=0 cells (0 PI)
9001 22:54:16.351418 u2DelayCellOfst[3]=3 cells (1 PI)
9002 22:54:16.354768 u2DelayCellOfst[4]=7 cells (2 PI)
9003 22:54:16.358180 u2DelayCellOfst[5]=22 cells (6 PI)
9004 22:54:16.361554 u2DelayCellOfst[6]=22 cells (6 PI)
9005 22:54:16.364996 u2DelayCellOfst[7]=3 cells (1 PI)
9006 22:54:16.367841 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
9007 22:54:16.371095 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
9008 22:54:16.374255 == TX Byte 1 ==
9009 22:54:16.378270 u2DelayCellOfst[8]=0 cells (0 PI)
9010 22:54:16.381636 u2DelayCellOfst[9]=7 cells (2 PI)
9011 22:54:16.384814 u2DelayCellOfst[10]=11 cells (3 PI)
9012 22:54:16.388006 u2DelayCellOfst[11]=7 cells (2 PI)
9013 22:54:16.391078 u2DelayCellOfst[12]=14 cells (4 PI)
9014 22:54:16.391753 u2DelayCellOfst[13]=18 cells (5 PI)
9015 22:54:16.394344 u2DelayCellOfst[14]=18 cells (5 PI)
9016 22:54:16.397708 u2DelayCellOfst[15]=18 cells (5 PI)
9017 22:54:16.404513 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
9018 22:54:16.407300 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
9019 22:54:16.411348 DramC Write-DBI on
9020 22:54:16.411803 ==
9021 22:54:16.414429 Dram Type= 6, Freq= 0, CH_1, rank 1
9022 22:54:16.417906 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9023 22:54:16.418459 ==
9024 22:54:16.418821
9025 22:54:16.419151
9026 22:54:16.420928 TX Vref Scan disable
9027 22:54:16.421425 == TX Byte 0 ==
9028 22:54:16.427163 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
9029 22:54:16.427641 == TX Byte 1 ==
9030 22:54:16.430710 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
9031 22:54:16.433833 DramC Write-DBI off
9032 22:54:16.434403
9033 22:54:16.434765 [DATLAT]
9034 22:54:16.437171 Freq=1600, CH1 RK1
9035 22:54:16.437664
9036 22:54:16.438023 DATLAT Default: 0xf
9037 22:54:16.440862 0, 0xFFFF, sum = 0
9038 22:54:16.441324 1, 0xFFFF, sum = 0
9039 22:54:16.444228 2, 0xFFFF, sum = 0
9040 22:54:16.444957 3, 0xFFFF, sum = 0
9041 22:54:16.447233 4, 0xFFFF, sum = 0
9042 22:54:16.450448 5, 0xFFFF, sum = 0
9043 22:54:16.451045 6, 0xFFFF, sum = 0
9044 22:54:16.454300 7, 0xFFFF, sum = 0
9045 22:54:16.454867 8, 0xFFFF, sum = 0
9046 22:54:16.457091 9, 0xFFFF, sum = 0
9047 22:54:16.457603 10, 0xFFFF, sum = 0
9048 22:54:16.460411 11, 0xFFFF, sum = 0
9049 22:54:16.460871 12, 0xFFFF, sum = 0
9050 22:54:16.464186 13, 0xFFFF, sum = 0
9051 22:54:16.464754 14, 0x0, sum = 1
9052 22:54:16.467045 15, 0x0, sum = 2
9053 22:54:16.467524 16, 0x0, sum = 3
9054 22:54:16.470738 17, 0x0, sum = 4
9055 22:54:16.471202 best_step = 15
9056 22:54:16.471558
9057 22:54:16.471894 ==
9058 22:54:16.473566 Dram Type= 6, Freq= 0, CH_1, rank 1
9059 22:54:16.480641 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9060 22:54:16.481220 ==
9061 22:54:16.481622 RX Vref Scan: 0
9062 22:54:16.481960
9063 22:54:16.483679 RX Vref 0 -> 0, step: 1
9064 22:54:16.484133
9065 22:54:16.486772 RX Delay 11 -> 252, step: 4
9066 22:54:16.489926 iDelay=203, Bit 0, Center 138 (83 ~ 194) 112
9067 22:54:16.493277 iDelay=203, Bit 1, Center 128 (75 ~ 182) 108
9068 22:54:16.496917 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9069 22:54:16.503528 iDelay=203, Bit 3, Center 130 (79 ~ 182) 104
9070 22:54:16.506030 iDelay=203, Bit 4, Center 134 (79 ~ 190) 112
9071 22:54:16.510052 iDelay=203, Bit 5, Center 142 (91 ~ 194) 104
9072 22:54:16.513260 iDelay=203, Bit 6, Center 146 (91 ~ 202) 112
9073 22:54:16.516144 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9074 22:54:16.522722 iDelay=203, Bit 8, Center 112 (55 ~ 170) 116
9075 22:54:16.525716 iDelay=203, Bit 9, Center 116 (63 ~ 170) 108
9076 22:54:16.529508 iDelay=203, Bit 10, Center 126 (71 ~ 182) 112
9077 22:54:16.532225 iDelay=203, Bit 11, Center 116 (63 ~ 170) 108
9078 22:54:16.539500 iDelay=203, Bit 12, Center 134 (79 ~ 190) 112
9079 22:54:16.542775 iDelay=203, Bit 13, Center 134 (79 ~ 190) 112
9080 22:54:16.545663 iDelay=203, Bit 14, Center 134 (79 ~ 190) 112
9081 22:54:16.549029 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9082 22:54:16.549519 ==
9083 22:54:16.552166 Dram Type= 6, Freq= 0, CH_1, rank 1
9084 22:54:16.558416 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9085 22:54:16.558877 ==
9086 22:54:16.559233 DQS Delay:
9087 22:54:16.562037 DQS0 = 0, DQS1 = 0
9088 22:54:16.562532 DQM Delay:
9089 22:54:16.564904 DQM0 = 133, DQM1 = 126
9090 22:54:16.565405 DQ Delay:
9091 22:54:16.568454 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130
9092 22:54:16.572062 DQ4 =134, DQ5 =142, DQ6 =146, DQ7 =130
9093 22:54:16.575117 DQ8 =112, DQ9 =116, DQ10 =126, DQ11 =116
9094 22:54:16.578697 DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =138
9095 22:54:16.579251
9096 22:54:16.579610
9097 22:54:16.579945
9098 22:54:16.582177 [DramC_TX_OE_Calibration] TA2
9099 22:54:16.585240 Original DQ_B0 (3 6) =30, OEN = 27
9100 22:54:16.588427 Original DQ_B1 (3 6) =30, OEN = 27
9101 22:54:16.592163 24, 0x0, End_B0=24 End_B1=24
9102 22:54:16.595028 25, 0x0, End_B0=25 End_B1=25
9103 22:54:16.595496 26, 0x0, End_B0=26 End_B1=26
9104 22:54:16.598299 27, 0x0, End_B0=27 End_B1=27
9105 22:54:16.601643 28, 0x0, End_B0=28 End_B1=28
9106 22:54:16.605189 29, 0x0, End_B0=29 End_B1=29
9107 22:54:16.608162 30, 0x0, End_B0=30 End_B1=30
9108 22:54:16.608725 31, 0x4141, End_B0=30 End_B1=30
9109 22:54:16.611303 Byte0 end_step=30 best_step=27
9110 22:54:16.614671 Byte1 end_step=30 best_step=27
9111 22:54:16.617638 Byte0 TX OE(2T, 0.5T) = (3, 3)
9112 22:54:16.621507 Byte1 TX OE(2T, 0.5T) = (3, 3)
9113 22:54:16.621978
9114 22:54:16.622336
9115 22:54:16.628196 [DQSOSCAuto] RK1, (LSB)MR18= 0xe0a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 402 ps
9116 22:54:16.631585 CH1 RK1: MR19=303, MR18=E0A
9117 22:54:16.637856 CH1_RK1: MR19=0x303, MR18=0xE0A, DQSOSC=402, MR23=63, INC=22, DEC=15
9118 22:54:16.641534 [RxdqsGatingPostProcess] freq 1600
9119 22:54:16.648153 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9120 22:54:16.648722 best DQS0 dly(2T, 0.5T) = (1, 1)
9121 22:54:16.651053 best DQS1 dly(2T, 0.5T) = (1, 1)
9122 22:54:16.654699 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9123 22:54:16.657667 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9124 22:54:16.660733 best DQS0 dly(2T, 0.5T) = (1, 1)
9125 22:54:16.664471 best DQS1 dly(2T, 0.5T) = (1, 1)
9126 22:54:16.667205 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9127 22:54:16.670663 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9128 22:54:16.673911 Pre-setting of DQS Precalculation
9129 22:54:16.677122 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9130 22:54:16.687247 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9131 22:54:16.693801 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9132 22:54:16.694369
9133 22:54:16.694727
9134 22:54:16.697014 [Calibration Summary] 3200 Mbps
9135 22:54:16.697515 CH 0, Rank 0
9136 22:54:16.700271 SW Impedance : PASS
9137 22:54:16.700828 DUTY Scan : NO K
9138 22:54:16.703879 ZQ Calibration : PASS
9139 22:54:16.706848 Jitter Meter : NO K
9140 22:54:16.707308 CBT Training : PASS
9141 22:54:16.710004 Write leveling : PASS
9142 22:54:16.713314 RX DQS gating : PASS
9143 22:54:16.713807 RX DQ/DQS(RDDQC) : PASS
9144 22:54:16.717087 TX DQ/DQS : PASS
9145 22:54:16.720020 RX DATLAT : PASS
9146 22:54:16.720594 RX DQ/DQS(Engine): PASS
9147 22:54:16.723125 TX OE : PASS
9148 22:54:16.723805 All Pass.
9149 22:54:16.724283
9150 22:54:16.726735 CH 0, Rank 1
9151 22:54:16.727292 SW Impedance : PASS
9152 22:54:16.729683 DUTY Scan : NO K
9153 22:54:16.732962 ZQ Calibration : PASS
9154 22:54:16.733578 Jitter Meter : NO K
9155 22:54:16.737048 CBT Training : PASS
9156 22:54:16.739840 Write leveling : PASS
9157 22:54:16.740300 RX DQS gating : PASS
9158 22:54:16.743125 RX DQ/DQS(RDDQC) : PASS
9159 22:54:16.746540 TX DQ/DQS : PASS
9160 22:54:16.747002 RX DATLAT : PASS
9161 22:54:16.749254 RX DQ/DQS(Engine): PASS
9162 22:54:16.752643 TX OE : PASS
9163 22:54:16.753098 All Pass.
9164 22:54:16.753495
9165 22:54:16.753837 CH 1, Rank 0
9166 22:54:16.756457 SW Impedance : PASS
9167 22:54:16.759547 DUTY Scan : NO K
9168 22:54:16.760010 ZQ Calibration : PASS
9169 22:54:16.762668 Jitter Meter : NO K
9170 22:54:16.765859 CBT Training : PASS
9171 22:54:16.766438 Write leveling : PASS
9172 22:54:16.769133 RX DQS gating : PASS
9173 22:54:16.772761 RX DQ/DQS(RDDQC) : PASS
9174 22:54:16.773255 TX DQ/DQS : PASS
9175 22:54:16.776014 RX DATLAT : PASS
9176 22:54:16.776569 RX DQ/DQS(Engine): PASS
9177 22:54:16.779972 TX OE : PASS
9178 22:54:16.780551 All Pass.
9179 22:54:16.780918
9180 22:54:16.782512 CH 1, Rank 1
9181 22:54:16.785968 SW Impedance : PASS
9182 22:54:16.786472 DUTY Scan : NO K
9183 22:54:16.789367 ZQ Calibration : PASS
9184 22:54:16.789826 Jitter Meter : NO K
9185 22:54:16.792318 CBT Training : PASS
9186 22:54:16.795933 Write leveling : PASS
9187 22:54:16.796394 RX DQS gating : PASS
9188 22:54:16.798822 RX DQ/DQS(RDDQC) : PASS
9189 22:54:16.802280 TX DQ/DQS : PASS
9190 22:54:16.802813 RX DATLAT : PASS
9191 22:54:16.805634 RX DQ/DQS(Engine): PASS
9192 22:54:16.809185 TX OE : PASS
9193 22:54:16.809794 All Pass.
9194 22:54:16.810157
9195 22:54:16.812062 DramC Write-DBI on
9196 22:54:16.812517 PER_BANK_REFRESH: Hybrid Mode
9197 22:54:16.815686 TX_TRACKING: ON
9198 22:54:16.825650 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9199 22:54:16.832371 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9200 22:54:16.838414 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9201 22:54:16.841654 [FAST_K] Save calibration result to emmc
9202 22:54:16.845176 sync common calibartion params.
9203 22:54:16.848555 sync cbt_mode0:1, 1:1
9204 22:54:16.851477 dram_init: ddr_geometry: 2
9205 22:54:16.851953 dram_init: ddr_geometry: 2
9206 22:54:16.854749 dram_init: ddr_geometry: 2
9207 22:54:16.858358 0:dram_rank_size:100000000
9208 22:54:16.858828 1:dram_rank_size:100000000
9209 22:54:16.864502 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9210 22:54:16.867669 DFS_SHUFFLE_HW_MODE: ON
9211 22:54:16.871322 dramc_set_vcore_voltage set vcore to 725000
9212 22:54:16.874511 Read voltage for 1600, 0
9213 22:54:16.874984 Vio18 = 0
9214 22:54:16.875343 Vcore = 725000
9215 22:54:16.878284 Vdram = 0
9216 22:54:16.878839 Vddq = 0
9217 22:54:16.879200 Vmddr = 0
9218 22:54:16.881123 switch to 3200 Mbps bootup
9219 22:54:16.884803 [DramcRunTimeConfig]
9220 22:54:16.885262 PHYPLL
9221 22:54:16.885652 DPM_CONTROL_AFTERK: ON
9222 22:54:16.887831 PER_BANK_REFRESH: ON
9223 22:54:16.891683 REFRESH_OVERHEAD_REDUCTION: ON
9224 22:54:16.892187 CMD_PICG_NEW_MODE: OFF
9225 22:54:16.894231 XRTWTW_NEW_MODE: ON
9226 22:54:16.894784 XRTRTR_NEW_MODE: ON
9227 22:54:16.897824 TX_TRACKING: ON
9228 22:54:16.898282 RDSEL_TRACKING: OFF
9229 22:54:16.900823 DQS Precalculation for DVFS: ON
9230 22:54:16.904449 RX_TRACKING: OFF
9231 22:54:16.904908 HW_GATING DBG: ON
9232 22:54:16.908145 ZQCS_ENABLE_LP4: ON
9233 22:54:16.908604 RX_PICG_NEW_MODE: ON
9234 22:54:16.910878 TX_PICG_NEW_MODE: ON
9235 22:54:16.914254 ENABLE_RX_DCM_DPHY: ON
9236 22:54:16.917738 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9237 22:54:16.918150 DUMMY_READ_FOR_TRACKING: OFF
9238 22:54:16.920568 !!! SPM_CONTROL_AFTERK: OFF
9239 22:54:16.924201 !!! SPM could not control APHY
9240 22:54:16.927351 IMPEDANCE_TRACKING: ON
9241 22:54:16.927763 TEMP_SENSOR: ON
9242 22:54:16.930624 HW_SAVE_FOR_SR: OFF
9243 22:54:16.931070 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9244 22:54:16.936980 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9245 22:54:16.937426 Read ODT Tracking: ON
9246 22:54:16.940536 Refresh Rate DeBounce: ON
9247 22:54:16.944122 DFS_NO_QUEUE_FLUSH: ON
9248 22:54:16.947150 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9249 22:54:16.947658 ENABLE_DFS_RUNTIME_MRW: OFF
9250 22:54:16.950207 DDR_RESERVE_NEW_MODE: ON
9251 22:54:16.953558 MR_CBT_SWITCH_FREQ: ON
9252 22:54:16.953970 =========================
9253 22:54:16.973410 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9254 22:54:16.976518 dram_init: ddr_geometry: 2
9255 22:54:16.995361 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9256 22:54:16.997954 dram_init: dram init end (result: 0)
9257 22:54:17.005222 DRAM-K: Full calibration passed in 24613 msecs
9258 22:54:17.008366 MRC: failed to locate region type 0.
9259 22:54:17.008831 DRAM rank0 size:0x100000000,
9260 22:54:17.011773 DRAM rank1 size=0x100000000
9261 22:54:17.021226 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9262 22:54:17.027970 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9263 22:54:17.034462 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9264 22:54:17.044293 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9265 22:54:17.044755 DRAM rank0 size:0x100000000,
9266 22:54:17.048241 DRAM rank1 size=0x100000000
9267 22:54:17.048802 CBMEM:
9268 22:54:17.051431 IMD: root @ 0xfffff000 254 entries.
9269 22:54:17.054414 IMD: root @ 0xffffec00 62 entries.
9270 22:54:17.057482 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9271 22:54:17.064290 WARNING: RO_VPD is uninitialized or empty.
9272 22:54:17.067756 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9273 22:54:17.075038 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9274 22:54:17.088385 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9275 22:54:17.099411 BS: romstage times (exec / console): total (unknown) / 24109 ms
9276 22:54:17.099844
9277 22:54:17.100168
9278 22:54:17.109355 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9279 22:54:17.112753 ARM64: Exception handlers installed.
9280 22:54:17.115451 ARM64: Testing exception
9281 22:54:17.119028 ARM64: Done test exception
9282 22:54:17.119438 Enumerating buses...
9283 22:54:17.121866 Show all devs... Before device enumeration.
9284 22:54:17.125150 Root Device: enabled 1
9285 22:54:17.128616 CPU_CLUSTER: 0: enabled 1
9286 22:54:17.129028 CPU: 00: enabled 1
9287 22:54:17.132305 Compare with tree...
9288 22:54:17.132840 Root Device: enabled 1
9289 22:54:17.135396 CPU_CLUSTER: 0: enabled 1
9290 22:54:17.138654 CPU: 00: enabled 1
9291 22:54:17.139088 Root Device scanning...
9292 22:54:17.141828 scan_static_bus for Root Device
9293 22:54:17.145078 CPU_CLUSTER: 0 enabled
9294 22:54:17.148661 scan_static_bus for Root Device done
9295 22:54:17.151908 scan_bus: bus Root Device finished in 8 msecs
9296 22:54:17.152547 done
9297 22:54:17.158430 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9298 22:54:17.161591 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9299 22:54:17.168048 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9300 22:54:17.174946 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9301 22:54:17.175487 Allocating resources...
9302 22:54:17.178228 Reading resources...
9303 22:54:17.181303 Root Device read_resources bus 0 link: 0
9304 22:54:17.184859 DRAM rank0 size:0x100000000,
9305 22:54:17.185469 DRAM rank1 size=0x100000000
9306 22:54:17.191361 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9307 22:54:17.191798 CPU: 00 missing read_resources
9308 22:54:17.197988 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9309 22:54:17.201189 Root Device read_resources bus 0 link: 0 done
9310 22:54:17.204543 Done reading resources.
9311 22:54:17.208116 Show resources in subtree (Root Device)...After reading.
9312 22:54:17.211764 Root Device child on link 0 CPU_CLUSTER: 0
9313 22:54:17.214612 CPU_CLUSTER: 0 child on link 0 CPU: 00
9314 22:54:17.224475 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9315 22:54:17.225059 CPU: 00
9316 22:54:17.230953 Root Device assign_resources, bus 0 link: 0
9317 22:54:17.234349 CPU_CLUSTER: 0 missing set_resources
9318 22:54:17.238286 Root Device assign_resources, bus 0 link: 0 done
9319 22:54:17.238879 Done setting resources.
9320 22:54:17.244043 Show resources in subtree (Root Device)...After assigning values.
9321 22:54:17.247249 Root Device child on link 0 CPU_CLUSTER: 0
9322 22:54:17.254009 CPU_CLUSTER: 0 child on link 0 CPU: 00
9323 22:54:17.260879 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9324 22:54:17.261539 CPU: 00
9325 22:54:17.264147 Done allocating resources.
9326 22:54:17.270665 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9327 22:54:17.271248 Enabling resources...
9328 22:54:17.274390 done.
9329 22:54:17.277445 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9330 22:54:17.281511 Initializing devices...
9331 22:54:17.282097 Root Device init
9332 22:54:17.284387 init hardware done!
9333 22:54:17.284967 0x00000018: ctrlr->caps
9334 22:54:17.287413 52.000 MHz: ctrlr->f_max
9335 22:54:17.290674 0.400 MHz: ctrlr->f_min
9336 22:54:17.291262 0x40ff8080: ctrlr->voltages
9337 22:54:17.293781 sclk: 390625
9338 22:54:17.294257 Bus Width = 1
9339 22:54:17.297112 sclk: 390625
9340 22:54:17.297640 Bus Width = 1
9341 22:54:17.300236 Early init status = 3
9342 22:54:17.303994 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9343 22:54:17.307344 in-header: 03 fc 00 00 01 00 00 00
9344 22:54:17.311250 in-data: 00
9345 22:54:17.314188 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9346 22:54:17.320638 in-header: 03 fd 00 00 00 00 00 00
9347 22:54:17.323437 in-data:
9348 22:54:17.326466 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9349 22:54:17.331246 in-header: 03 fc 00 00 01 00 00 00
9350 22:54:17.334167 in-data: 00
9351 22:54:17.337667 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9352 22:54:17.343360 in-header: 03 fd 00 00 00 00 00 00
9353 22:54:17.346791 in-data:
9354 22:54:17.350005 [SSUSB] Setting up USB HOST controller...
9355 22:54:17.353369 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9356 22:54:17.356461 [SSUSB] phy power-on done.
9357 22:54:17.360022 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9358 22:54:17.366276 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9359 22:54:17.369846 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9360 22:54:17.376330 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9361 22:54:17.382967 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9362 22:54:17.389283 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9363 22:54:17.396329 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9364 22:54:17.402508 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9365 22:54:17.406134 SPM: binary array size = 0x9dc
9366 22:54:17.409173 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9367 22:54:17.415876 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9368 22:54:17.422491 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9369 22:54:17.428565 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9370 22:54:17.432275 configure_display: Starting display init
9371 22:54:17.466397 anx7625_power_on_init: Init interface.
9372 22:54:17.469915 anx7625_disable_pd_protocol: Disabled PD feature.
9373 22:54:17.473291 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9374 22:54:17.500987 anx7625_start_dp_work: Secure OCM version=00
9375 22:54:17.504389 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9376 22:54:17.518968 sp_tx_get_edid_block: EDID Block = 1
9377 22:54:17.621797 Extracted contents:
9378 22:54:17.625028 header: 00 ff ff ff ff ff ff 00
9379 22:54:17.628426 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9380 22:54:17.631625 version: 01 04
9381 22:54:17.635023 basic params: 95 1f 11 78 0a
9382 22:54:17.638063 chroma info: 76 90 94 55 54 90 27 21 50 54
9383 22:54:17.641471 established: 00 00 00
9384 22:54:17.648434 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9385 22:54:17.651360 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9386 22:54:17.658239 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9387 22:54:17.664360 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9388 22:54:17.671083 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9389 22:54:17.674447 extensions: 00
9390 22:54:17.675032 checksum: fb
9391 22:54:17.675565
9392 22:54:17.677816 Manufacturer: IVO Model 57d Serial Number 0
9393 22:54:17.681134 Made week 0 of 2020
9394 22:54:17.684632 EDID version: 1.4
9395 22:54:17.685095 Digital display
9396 22:54:17.688069 6 bits per primary color channel
9397 22:54:17.688631 DisplayPort interface
9398 22:54:17.691132 Maximum image size: 31 cm x 17 cm
9399 22:54:17.694003 Gamma: 220%
9400 22:54:17.694503 Check DPMS levels
9401 22:54:17.697271 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9402 22:54:17.704130 First detailed timing is preferred timing
9403 22:54:17.704613 Established timings supported:
9404 22:54:17.707151 Standard timings supported:
9405 22:54:17.710525 Detailed timings
9406 22:54:17.714279 Hex of detail: 383680a07038204018303c0035ae10000019
9407 22:54:17.721006 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9408 22:54:17.723895 0780 0798 07c8 0820 hborder 0
9409 22:54:17.727029 0438 043b 0447 0458 vborder 0
9410 22:54:17.730260 -hsync -vsync
9411 22:54:17.730723 Did detailed timing
9412 22:54:17.736964 Hex of detail: 000000000000000000000000000000000000
9413 22:54:17.740482 Manufacturer-specified data, tag 0
9414 22:54:17.743314 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9415 22:54:17.747325 ASCII string: InfoVision
9416 22:54:17.750170 Hex of detail: 000000fe00523134304e574635205248200a
9417 22:54:17.753684 ASCII string: R140NWF5 RH
9418 22:54:17.754252 Checksum
9419 22:54:17.757021 Checksum: 0xfb (valid)
9420 22:54:17.760560 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9421 22:54:17.763268 DSI data_rate: 832800000 bps
9422 22:54:17.770041 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9423 22:54:17.773933 anx7625_parse_edid: pixelclock(138800).
9424 22:54:17.776883 hactive(1920), hsync(48), hfp(24), hbp(88)
9425 22:54:17.780092 vactive(1080), vsync(12), vfp(3), vbp(17)
9426 22:54:17.783609 anx7625_dsi_config: config dsi.
9427 22:54:17.789810 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9428 22:54:17.803958 anx7625_dsi_config: success to config DSI
9429 22:54:17.807148 anx7625_dp_start: MIPI phy setup OK.
9430 22:54:17.810147 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9431 22:54:17.813425 mtk_ddp_mode_set invalid vrefresh 60
9432 22:54:17.816583 main_disp_path_setup
9433 22:54:17.817060 ovl_layer_smi_id_en
9434 22:54:17.820139 ovl_layer_smi_id_en
9435 22:54:17.820721 ccorr_config
9436 22:54:17.821209 aal_config
9437 22:54:17.823172 gamma_config
9438 22:54:17.823649 postmask_config
9439 22:54:17.826430 dither_config
9440 22:54:17.830018 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9441 22:54:17.836271 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9442 22:54:17.839911 Root Device init finished in 555 msecs
9443 22:54:17.843343 CPU_CLUSTER: 0 init
9444 22:54:17.850260 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9445 22:54:17.856426 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9446 22:54:17.857009 APU_MBOX 0x190000b0 = 0x10001
9447 22:54:17.859913 APU_MBOX 0x190001b0 = 0x10001
9448 22:54:17.863131 APU_MBOX 0x190005b0 = 0x10001
9449 22:54:17.866813 APU_MBOX 0x190006b0 = 0x10001
9450 22:54:17.873054 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9451 22:54:17.882859 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9452 22:54:17.895089 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9453 22:54:17.902295 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9454 22:54:17.913316 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9455 22:54:17.922423 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9456 22:54:17.925448 CPU_CLUSTER: 0 init finished in 81 msecs
9457 22:54:17.929005 Devices initialized
9458 22:54:17.932358 Show all devs... After init.
9459 22:54:17.932838 Root Device: enabled 1
9460 22:54:17.935876 CPU_CLUSTER: 0: enabled 1
9461 22:54:17.939384 CPU: 00: enabled 1
9462 22:54:17.942005 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9463 22:54:17.945956 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9464 22:54:17.948964 ELOG: NV offset 0x57f000 size 0x1000
9465 22:54:17.955933 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9466 22:54:17.962586 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9467 22:54:17.965364 ELOG: Event(17) added with size 13 at 2024-05-07 22:54:18 UTC
9468 22:54:17.972113 out: cmd=0x121: 03 db 21 01 00 00 00 00
9469 22:54:17.975153 in-header: 03 3c 00 00 2c 00 00 00
9470 22:54:17.985205 in-data: 00 73 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9471 22:54:17.991850 ELOG: Event(A1) added with size 10 at 2024-05-07 22:54:18 UTC
9472 22:54:17.998498 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9473 22:54:18.005299 ELOG: Event(A0) added with size 9 at 2024-05-07 22:54:18 UTC
9474 22:54:18.008588 elog_add_boot_reason: Logged dev mode boot
9475 22:54:18.014933 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9476 22:54:18.015502 Finalize devices...
9477 22:54:18.018532 Devices finalized
9478 22:54:18.021572 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9479 22:54:18.024711 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9480 22:54:18.027976 in-header: 03 07 00 00 08 00 00 00
9481 22:54:18.031653 in-data: aa e4 47 04 13 02 00 00
9482 22:54:18.035072 Chrome EC: UHEPI supported
9483 22:54:18.041619 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9484 22:54:18.044318 in-header: 03 a9 00 00 08 00 00 00
9485 22:54:18.047768 in-data: 84 60 60 08 00 00 00 00
9486 22:54:18.054331 ELOG: Event(91) added with size 10 at 2024-05-07 22:54:18 UTC
9487 22:54:18.058308 Chrome EC: clear events_b mask to 0x0000000020004000
9488 22:54:18.064357 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9489 22:54:18.068155 in-header: 03 fd 00 00 00 00 00 00
9490 22:54:18.068637 in-data:
9491 22:54:18.074311 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9492 22:54:18.077870 Writing coreboot table at 0xffe64000
9493 22:54:18.080997 0. 000000000010a000-0000000000113fff: RAMSTAGE
9494 22:54:18.084420 1. 0000000040000000-00000000400fffff: RAM
9495 22:54:18.091184 2. 0000000040100000-000000004032afff: RAMSTAGE
9496 22:54:18.094602 3. 000000004032b000-00000000545fffff: RAM
9497 22:54:18.097465 4. 0000000054600000-000000005465ffff: BL31
9498 22:54:18.101078 5. 0000000054660000-00000000ffe63fff: RAM
9499 22:54:18.107789 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9500 22:54:18.111198 7. 0000000100000000-000000023fffffff: RAM
9501 22:54:18.114001 Passing 5 GPIOs to payload:
9502 22:54:18.117625 NAME | PORT | POLARITY | VALUE
9503 22:54:18.124110 EC in RW | 0x000000aa | low | undefined
9504 22:54:18.127366 EC interrupt | 0x00000005 | low | undefined
9505 22:54:18.130770 TPM interrupt | 0x000000ab | high | undefined
9506 22:54:18.137649 SD card detect | 0x00000011 | high | undefined
9507 22:54:18.140764 speaker enable | 0x00000093 | high | undefined
9508 22:54:18.144384 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9509 22:54:18.147710 in-header: 03 f9 00 00 02 00 00 00
9510 22:54:18.150758 in-data: 02 00
9511 22:54:18.153845 ADC[4]: Raw value=904509 ID=7
9512 22:54:18.154346 ADC[3]: Raw value=214021 ID=1
9513 22:54:18.157266 RAM Code: 0x71
9514 22:54:18.160422 ADC[6]: Raw value=75036 ID=0
9515 22:54:18.160937 ADC[5]: Raw value=212912 ID=1
9516 22:54:18.163910 SKU Code: 0x1
9517 22:54:18.167238 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 47a9
9518 22:54:18.170278 coreboot table: 964 bytes.
9519 22:54:18.173636 IMD ROOT 0. 0xfffff000 0x00001000
9520 22:54:18.177170 IMD SMALL 1. 0xffffe000 0x00001000
9521 22:54:18.180705 RO MCACHE 2. 0xffffc000 0x00001104
9522 22:54:18.184145 CONSOLE 3. 0xfff7c000 0x00080000
9523 22:54:18.187059 FMAP 4. 0xfff7b000 0x00000452
9524 22:54:18.190392 TIME STAMP 5. 0xfff7a000 0x00000910
9525 22:54:18.193325 VBOOT WORK 6. 0xfff66000 0x00014000
9526 22:54:18.197305 RAMOOPS 7. 0xffe66000 0x00100000
9527 22:54:18.199987 COREBOOT 8. 0xffe64000 0x00002000
9528 22:54:18.203147 IMD small region:
9529 22:54:18.206861 IMD ROOT 0. 0xffffec00 0x00000400
9530 22:54:18.210088 VPD 1. 0xffffeb80 0x0000006c
9531 22:54:18.213235 MMC STATUS 2. 0xffffeb60 0x00000004
9532 22:54:18.217071 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9533 22:54:18.223829 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9534 22:54:18.264341 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9535 22:54:18.267214 Checking segment from ROM address 0x40100000
9536 22:54:18.270946 Checking segment from ROM address 0x4010001c
9537 22:54:18.277035 Loading segment from ROM address 0x40100000
9538 22:54:18.277563 code (compression=0)
9539 22:54:18.287390 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9540 22:54:18.293884 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9541 22:54:18.294350 it's not compressed!
9542 22:54:18.300274 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9543 22:54:18.307375 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9544 22:54:18.324968 Loading segment from ROM address 0x4010001c
9545 22:54:18.325571 Entry Point 0x80000000
9546 22:54:18.327996 Loaded segments
9547 22:54:18.331182 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9548 22:54:18.337868 Jumping to boot code at 0x80000000(0xffe64000)
9549 22:54:18.344766 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9550 22:54:18.350688 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9551 22:54:18.359335 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9552 22:54:18.362335 Checking segment from ROM address 0x40100000
9553 22:54:18.365811 Checking segment from ROM address 0x4010001c
9554 22:54:18.372574 Loading segment from ROM address 0x40100000
9555 22:54:18.373053 code (compression=1)
9556 22:54:18.379162 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9557 22:54:18.388649 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9558 22:54:18.389230 using LZMA
9559 22:54:18.397871 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9560 22:54:18.403949 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9561 22:54:18.407393 Loading segment from ROM address 0x4010001c
9562 22:54:18.407876 Entry Point 0x54601000
9563 22:54:18.410709 Loaded segments
9564 22:54:18.413796 NOTICE: MT8192 bl31_setup
9565 22:54:18.421102 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9566 22:54:18.424714 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9567 22:54:18.427470 WARNING: region 0:
9568 22:54:18.430890 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9569 22:54:18.431361 WARNING: region 1:
9570 22:54:18.437807 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9571 22:54:18.440834 WARNING: region 2:
9572 22:54:18.444497 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9573 22:54:18.447861 WARNING: region 3:
9574 22:54:18.451338 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9575 22:54:18.454033 WARNING: region 4:
9576 22:54:18.461100 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9577 22:54:18.461699 WARNING: region 5:
9578 22:54:18.463999 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9579 22:54:18.467591 WARNING: region 6:
9580 22:54:18.470561 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9581 22:54:18.474121 WARNING: region 7:
9582 22:54:18.477580 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9583 22:54:18.484049 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9584 22:54:18.487416 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9585 22:54:18.493440 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9586 22:54:18.496741 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9587 22:54:18.500124 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9588 22:54:18.507093 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9589 22:54:18.509942 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9590 22:54:18.513522 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9591 22:54:18.520280 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9592 22:54:18.524059 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9593 22:54:18.530078 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9594 22:54:18.533191 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9595 22:54:18.536513 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9596 22:54:18.543361 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9597 22:54:18.546707 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9598 22:54:18.550117 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9599 22:54:18.556926 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9600 22:54:18.560161 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9601 22:54:18.566752 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9602 22:54:18.570117 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9603 22:54:18.572911 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9604 22:54:18.580037 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9605 22:54:18.583262 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9606 22:54:18.589701 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9607 22:54:18.593150 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9608 22:54:18.595935 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9609 22:54:18.602492 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9610 22:54:18.606129 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9611 22:54:18.612474 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9612 22:54:18.616083 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9613 22:54:18.622372 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9614 22:54:18.625843 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9615 22:54:18.629520 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9616 22:54:18.632571 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9617 22:54:18.639484 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9618 22:54:18.642293 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9619 22:54:18.645803 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9620 22:54:18.648998 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9621 22:54:18.655961 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9622 22:54:18.659464 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9623 22:54:18.662240 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9624 22:54:18.665191 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9625 22:54:18.671876 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9626 22:54:18.675581 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9627 22:54:18.678423 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9628 22:54:18.685172 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9629 22:54:18.688843 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9630 22:54:18.691883 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9631 22:54:18.698278 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9632 22:54:18.702015 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9633 22:54:18.704722 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9634 22:54:18.711257 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9635 22:54:18.714985 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9636 22:54:18.721596 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9637 22:54:18.724296 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9638 22:54:18.730929 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9639 22:54:18.733998 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9640 22:54:18.737657 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9641 22:54:18.744232 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9642 22:54:18.747780 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9643 22:54:18.754707 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9644 22:54:18.757551 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9645 22:54:18.764313 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9646 22:54:18.767430 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9647 22:54:18.774499 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9648 22:54:18.777832 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9649 22:54:18.781356 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9650 22:54:18.788146 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9651 22:54:18.790825 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9652 22:54:18.797671 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9653 22:54:18.800827 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9654 22:54:18.807752 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9655 22:54:18.810766 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9656 22:54:18.813996 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9657 22:54:18.820542 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9658 22:54:18.824065 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9659 22:54:18.830645 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9660 22:54:18.833775 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9661 22:54:18.840870 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9662 22:54:18.843956 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9663 22:54:18.850565 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9664 22:54:18.853901 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9665 22:54:18.860194 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9666 22:54:18.863869 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9667 22:54:18.867048 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9668 22:54:18.873433 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9669 22:54:18.877026 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9670 22:54:18.883187 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9671 22:54:18.886897 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9672 22:54:18.893237 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9673 22:54:18.897006 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9674 22:54:18.903878 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9675 22:54:18.906529 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9676 22:54:18.910067 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9677 22:54:18.916689 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9678 22:54:18.919788 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9679 22:54:18.926641 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9680 22:54:18.929925 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9681 22:54:18.933019 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9682 22:54:18.936135 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9683 22:54:18.943115 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9684 22:54:18.946271 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9685 22:54:18.952765 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9686 22:54:18.956390 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9687 22:54:18.959330 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9688 22:54:18.965816 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9689 22:54:18.969044 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9690 22:54:18.976017 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9691 22:54:18.979375 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9692 22:54:18.982569 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9693 22:54:18.988889 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9694 22:54:18.992217 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9695 22:54:18.998979 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9696 22:54:19.002412 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9697 22:54:19.005603 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9698 22:54:19.011997 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9699 22:54:19.015282 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9700 22:54:19.018897 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9701 22:54:19.025139 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9702 22:54:19.028997 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9703 22:54:19.032472 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9704 22:54:19.035306 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9705 22:54:19.042058 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9706 22:54:19.045379 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9707 22:54:19.048543 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9708 22:54:19.054545 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9709 22:54:19.058085 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9710 22:54:19.065042 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9711 22:54:19.068250 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9712 22:54:19.071977 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9713 22:54:19.078257 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9714 22:54:19.081590 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9715 22:54:19.088048 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9716 22:54:19.091698 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9717 22:54:19.094692 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9718 22:54:19.101605 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9719 22:54:19.104881 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9720 22:54:19.108230 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9721 22:54:19.114831 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9722 22:54:19.118194 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9723 22:54:19.124587 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9724 22:54:19.128460 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9725 22:54:19.134548 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9726 22:54:19.138018 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9727 22:54:19.141271 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9728 22:54:19.147992 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9729 22:54:19.151794 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9730 22:54:19.154578 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9731 22:54:19.161390 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9732 22:54:19.164505 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9733 22:54:19.170990 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9734 22:54:19.174108 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9735 22:54:19.177972 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9736 22:54:19.184355 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9737 22:54:19.188109 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9738 22:54:19.194076 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9739 22:54:19.197921 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9740 22:54:19.204235 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9741 22:54:19.207358 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9742 22:54:19.210502 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9743 22:54:19.217010 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9744 22:54:19.220709 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9745 22:54:19.224338 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9746 22:54:19.230606 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9747 22:54:19.233942 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9748 22:54:19.241003 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9749 22:54:19.243900 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9750 22:54:19.247190 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9751 22:54:19.254236 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9752 22:54:19.257229 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9753 22:54:19.263797 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9754 22:54:19.267483 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9755 22:54:19.270441 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9756 22:54:19.277218 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9757 22:54:19.279902 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9758 22:54:19.286849 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9759 22:54:19.290048 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9760 22:54:19.293639 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9761 22:54:19.299569 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9762 22:54:19.302840 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9763 22:54:19.309580 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9764 22:54:19.312737 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9765 22:54:19.316162 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9766 22:54:19.322431 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9767 22:54:19.326090 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9768 22:54:19.332498 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9769 22:54:19.336363 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9770 22:54:19.339076 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9771 22:54:19.346346 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9772 22:54:19.348923 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9773 22:54:19.355985 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9774 22:54:19.358965 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9775 22:54:19.365203 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9776 22:54:19.368666 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9777 22:54:19.371933 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9778 22:54:19.379038 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9779 22:54:19.382053 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9780 22:54:19.388484 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9781 22:54:19.391984 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9782 22:54:19.398736 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9783 22:54:19.401861 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9784 22:54:19.404745 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9785 22:54:19.411759 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9786 22:54:19.414783 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9787 22:54:19.421237 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9788 22:54:19.424965 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9789 22:54:19.430984 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9790 22:54:19.434274 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9791 22:54:19.441138 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9792 22:54:19.444410 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9793 22:54:19.447574 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9794 22:54:19.454283 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9795 22:54:19.457791 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9796 22:54:19.463965 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9797 22:54:19.467396 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9798 22:54:19.470483 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9799 22:54:19.477444 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9800 22:54:19.480778 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9801 22:54:19.487526 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9802 22:54:19.491035 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9803 22:54:19.497194 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9804 22:54:19.500460 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9805 22:54:19.503785 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9806 22:54:19.510265 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9807 22:54:19.513904 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9808 22:54:19.520461 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9809 22:54:19.523579 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9810 22:54:19.530469 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9811 22:54:19.533891 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9812 22:54:19.536867 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9813 22:54:19.540507 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9814 22:54:19.546721 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9815 22:54:19.550543 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9816 22:54:19.553203 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9817 22:54:19.556927 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9818 22:54:19.563594 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9819 22:54:19.566691 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9820 22:54:19.573218 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9821 22:54:19.576617 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9822 22:54:19.579977 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9823 22:54:19.586472 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9824 22:54:19.589683 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9825 22:54:19.596210 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9826 22:54:19.599601 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9827 22:54:19.603277 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9828 22:54:19.609800 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9829 22:54:19.613023 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9830 22:54:19.616164 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9831 22:54:19.622885 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9832 22:54:19.626287 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9833 22:54:19.629447 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9834 22:54:19.636396 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9835 22:54:19.639203 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9836 22:54:19.646143 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9837 22:54:19.649577 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9838 22:54:19.652518 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9839 22:54:19.659649 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9840 22:54:19.662479 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9841 22:54:19.665661 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9842 22:54:19.672414 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9843 22:54:19.676172 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9844 22:54:19.682665 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9845 22:54:19.685998 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9846 22:54:19.688976 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9847 22:54:19.695748 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9848 22:54:19.698973 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9849 22:54:19.701838 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9850 22:54:19.708333 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9851 22:54:19.711863 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9852 22:54:19.715120 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9853 22:54:19.722284 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9854 22:54:19.725428 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9855 22:54:19.728771 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9856 22:54:19.731964 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9857 22:54:19.735483 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9858 22:54:19.741742 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9859 22:54:19.745114 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9860 22:54:19.748560 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9861 22:54:19.754734 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9862 22:54:19.758221 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9863 22:54:19.761394 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9864 22:54:19.764885 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9865 22:54:19.771373 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9866 22:54:19.775297 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9867 22:54:19.781459 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9868 22:54:19.785045 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9869 22:54:19.791580 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9870 22:54:19.795280 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9871 22:54:19.798678 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9872 22:54:19.804771 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9873 22:54:19.808091 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9874 22:54:19.814557 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9875 22:54:19.818082 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9876 22:54:19.821379 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9877 22:54:19.828218 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9878 22:54:19.831235 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9879 22:54:19.838047 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9880 22:54:19.841553 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9881 22:54:19.844835 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9882 22:54:19.851276 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9883 22:54:19.854835 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9884 22:54:19.860641 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9885 22:54:19.864089 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9886 22:54:19.870721 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9887 22:54:19.874447 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9888 22:54:19.877559 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9889 22:54:19.884208 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9890 22:54:19.887754 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9891 22:54:19.894318 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9892 22:54:19.897475 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9893 22:54:19.901031 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9894 22:54:19.907436 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9895 22:54:19.910396 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9896 22:54:19.917516 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9897 22:54:19.920191 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9898 22:54:19.923834 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9899 22:54:19.930425 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9900 22:54:19.933323 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9901 22:54:19.940526 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9902 22:54:19.943738 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9903 22:54:19.949889 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9904 22:54:19.953138 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9905 22:54:19.957401 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9906 22:54:19.963076 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9907 22:54:19.966632 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9908 22:54:19.973372 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9909 22:54:19.976143 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9910 22:54:19.982968 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9911 22:54:19.986323 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9912 22:54:19.989907 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9913 22:54:19.996345 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9914 22:54:19.999641 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9915 22:54:20.006288 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9916 22:54:20.009547 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9917 22:54:20.012639 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9918 22:54:20.019334 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9919 22:54:20.022793 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9920 22:54:20.029216 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9921 22:54:20.032223 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9922 22:54:20.035933 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9923 22:54:20.042003 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9924 22:54:20.045838 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9925 22:54:20.052259 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9926 22:54:20.055586 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9927 22:54:20.061853 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9928 22:54:20.065310 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9929 22:54:20.068802 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9930 22:54:20.075089 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9931 22:54:20.078412 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9932 22:54:20.085044 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9933 22:54:20.088755 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9934 22:54:20.094983 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9935 22:54:20.098154 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9936 22:54:20.101812 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9937 22:54:20.108427 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9938 22:54:20.111522 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9939 22:54:20.117926 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9940 22:54:20.121445 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9941 22:54:20.128496 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9942 22:54:20.131476 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9943 22:54:20.135044 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9944 22:54:20.141626 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9945 22:54:20.144622 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9946 22:54:20.151704 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9947 22:54:20.154574 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9948 22:54:20.161440 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9949 22:54:20.164545 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9950 22:54:20.171325 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9951 22:54:20.174360 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9952 22:54:20.177877 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9953 22:54:20.184307 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9954 22:54:20.188120 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9955 22:54:20.194460 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9956 22:54:20.197855 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9957 22:54:20.204254 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9958 22:54:20.207604 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9959 22:54:20.214063 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9960 22:54:20.217253 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9961 22:54:20.220712 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9962 22:54:20.227821 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9963 22:54:20.230602 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9964 22:54:20.237130 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9965 22:54:20.240706 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9966 22:54:20.247097 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9967 22:54:20.250551 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9968 22:54:20.253803 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9969 22:54:20.260861 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9970 22:54:20.263804 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9971 22:54:20.270532 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9972 22:54:20.273972 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9973 22:54:20.280351 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9974 22:54:20.283544 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9975 22:54:20.290375 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9976 22:54:20.293839 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9977 22:54:20.296952 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9978 22:54:20.303500 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9979 22:54:20.306918 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9980 22:54:20.313284 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9981 22:54:20.316425 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9982 22:54:20.323093 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9983 22:54:20.326638 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9984 22:54:20.330013 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9985 22:54:20.336538 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9986 22:54:20.339605 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9987 22:54:20.346492 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9988 22:54:20.349930 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9989 22:54:20.356432 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9990 22:54:20.359723 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9991 22:54:20.366279 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9992 22:54:20.369552 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9993 22:54:20.376607 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9994 22:54:20.379490 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9995 22:54:20.386732 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9996 22:54:20.389790 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9997 22:54:20.395966 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9998 22:54:20.399617 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9999 22:54:20.406060 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
10000 22:54:20.409562 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
10001 22:54:20.412694 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
10002 22:54:20.418990 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
10003 22:54:20.422193 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
10004 22:54:20.429123 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
10005 22:54:20.432529 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
10006 22:54:20.439115 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
10007 22:54:20.442426 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
10008 22:54:20.448729 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
10009 22:54:20.452143 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
10010 22:54:20.458924 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
10011 22:54:20.461980 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
10012 22:54:20.468729 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
10013 22:54:20.475252 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
10014 22:54:20.478866 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
10015 22:54:20.485498 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
10016 22:54:20.488892 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
10017 22:54:20.492158 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
10018 22:54:20.495547 INFO: [APUAPC] vio 0
10019 22:54:20.498667 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
10020 22:54:20.506038 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
10021 22:54:20.508748 INFO: [APUAPC] D0_APC_0: 0x400510
10022 22:54:20.512112 INFO: [APUAPC] D0_APC_1: 0x0
10023 22:54:20.515362 INFO: [APUAPC] D0_APC_2: 0x1540
10024 22:54:20.515825 INFO: [APUAPC] D0_APC_3: 0x0
10025 22:54:20.518836 INFO: [APUAPC] D1_APC_0: 0xffffffff
10026 22:54:20.525313 INFO: [APUAPC] D1_APC_1: 0xffffffff
10027 22:54:20.528385 INFO: [APUAPC] D1_APC_2: 0x3fffff
10028 22:54:20.528843 INFO: [APUAPC] D1_APC_3: 0x0
10029 22:54:20.531549 INFO: [APUAPC] D2_APC_0: 0xffffffff
10030 22:54:20.535027 INFO: [APUAPC] D2_APC_1: 0xffffffff
10031 22:54:20.538351 INFO: [APUAPC] D2_APC_2: 0x3fffff
10032 22:54:20.541861 INFO: [APUAPC] D2_APC_3: 0x0
10033 22:54:20.544711 INFO: [APUAPC] D3_APC_0: 0xffffffff
10034 22:54:20.548076 INFO: [APUAPC] D3_APC_1: 0xffffffff
10035 22:54:20.551854 INFO: [APUAPC] D3_APC_2: 0x3fffff
10036 22:54:20.554678 INFO: [APUAPC] D3_APC_3: 0x0
10037 22:54:20.558278 INFO: [APUAPC] D4_APC_0: 0xffffffff
10038 22:54:20.561497 INFO: [APUAPC] D4_APC_1: 0xffffffff
10039 22:54:20.564621 INFO: [APUAPC] D4_APC_2: 0x3fffff
10040 22:54:20.567968 INFO: [APUAPC] D4_APC_3: 0x0
10041 22:54:20.571467 INFO: [APUAPC] D5_APC_0: 0xffffffff
10042 22:54:20.574355 INFO: [APUAPC] D5_APC_1: 0xffffffff
10043 22:54:20.578257 INFO: [APUAPC] D5_APC_2: 0x3fffff
10044 22:54:20.581413 INFO: [APUAPC] D5_APC_3: 0x0
10045 22:54:20.584389 INFO: [APUAPC] D6_APC_0: 0xffffffff
10046 22:54:20.588096 INFO: [APUAPC] D6_APC_1: 0xffffffff
10047 22:54:20.591067 INFO: [APUAPC] D6_APC_2: 0x3fffff
10048 22:54:20.594495 INFO: [APUAPC] D6_APC_3: 0x0
10049 22:54:20.597817 INFO: [APUAPC] D7_APC_0: 0xffffffff
10050 22:54:20.600999 INFO: [APUAPC] D7_APC_1: 0xffffffff
10051 22:54:20.603992 INFO: [APUAPC] D7_APC_2: 0x3fffff
10052 22:54:20.607654 INFO: [APUAPC] D7_APC_3: 0x0
10053 22:54:20.611113 INFO: [APUAPC] D8_APC_0: 0xffffffff
10054 22:54:20.614039 INFO: [APUAPC] D8_APC_1: 0xffffffff
10055 22:54:20.617198 INFO: [APUAPC] D8_APC_2: 0x3fffff
10056 22:54:20.620385 INFO: [APUAPC] D8_APC_3: 0x0
10057 22:54:20.624053 INFO: [APUAPC] D9_APC_0: 0xffffffff
10058 22:54:20.627583 INFO: [APUAPC] D9_APC_1: 0xffffffff
10059 22:54:20.630331 INFO: [APUAPC] D9_APC_2: 0x3fffff
10060 22:54:20.634030 INFO: [APUAPC] D9_APC_3: 0x0
10061 22:54:20.636865 INFO: [APUAPC] D10_APC_0: 0xffffffff
10062 22:54:20.640430 INFO: [APUAPC] D10_APC_1: 0xffffffff
10063 22:54:20.643964 INFO: [APUAPC] D10_APC_2: 0x3fffff
10064 22:54:20.647414 INFO: [APUAPC] D10_APC_3: 0x0
10065 22:54:20.650241 INFO: [APUAPC] D11_APC_0: 0xffffffff
10066 22:54:20.653426 INFO: [APUAPC] D11_APC_1: 0xffffffff
10067 22:54:20.657014 INFO: [APUAPC] D11_APC_2: 0x3fffff
10068 22:54:20.660112 INFO: [APUAPC] D11_APC_3: 0x0
10069 22:54:20.663458 INFO: [APUAPC] D12_APC_0: 0xffffffff
10070 22:54:20.666647 INFO: [APUAPC] D12_APC_1: 0xffffffff
10071 22:54:20.670555 INFO: [APUAPC] D12_APC_2: 0x3fffff
10072 22:54:20.673668 INFO: [APUAPC] D12_APC_3: 0x0
10073 22:54:20.676518 INFO: [APUAPC] D13_APC_0: 0xffffffff
10074 22:54:20.680049 INFO: [APUAPC] D13_APC_1: 0xffffffff
10075 22:54:20.683538 INFO: [APUAPC] D13_APC_2: 0x3fffff
10076 22:54:20.686676 INFO: [APUAPC] D13_APC_3: 0x0
10077 22:54:20.689939 INFO: [APUAPC] D14_APC_0: 0xffffffff
10078 22:54:20.693131 INFO: [APUAPC] D14_APC_1: 0xffffffff
10079 22:54:20.696696 INFO: [APUAPC] D14_APC_2: 0x3fffff
10080 22:54:20.699701 INFO: [APUAPC] D14_APC_3: 0x0
10081 22:54:20.702746 INFO: [APUAPC] D15_APC_0: 0xffffffff
10082 22:54:20.706945 INFO: [APUAPC] D15_APC_1: 0xffffffff
10083 22:54:20.709766 INFO: [APUAPC] D15_APC_2: 0x3fffff
10084 22:54:20.712776 INFO: [APUAPC] D15_APC_3: 0x0
10085 22:54:20.716565 INFO: [APUAPC] APC_CON: 0x4
10086 22:54:20.719264 INFO: [NOCDAPC] D0_APC_0: 0x0
10087 22:54:20.722825 INFO: [NOCDAPC] D0_APC_1: 0x0
10088 22:54:20.726097 INFO: [NOCDAPC] D1_APC_0: 0x0
10089 22:54:20.729506 INFO: [NOCDAPC] D1_APC_1: 0xfff
10090 22:54:20.732893 INFO: [NOCDAPC] D2_APC_0: 0x0
10091 22:54:20.736287 INFO: [NOCDAPC] D2_APC_1: 0xfff
10092 22:54:20.736770 INFO: [NOCDAPC] D3_APC_0: 0x0
10093 22:54:20.739380 INFO: [NOCDAPC] D3_APC_1: 0xfff
10094 22:54:20.742511 INFO: [NOCDAPC] D4_APC_0: 0x0
10095 22:54:20.745907 INFO: [NOCDAPC] D4_APC_1: 0xfff
10096 22:54:20.749313 INFO: [NOCDAPC] D5_APC_0: 0x0
10097 22:54:20.752868 INFO: [NOCDAPC] D5_APC_1: 0xfff
10098 22:54:20.755854 INFO: [NOCDAPC] D6_APC_0: 0x0
10099 22:54:20.759379 INFO: [NOCDAPC] D6_APC_1: 0xfff
10100 22:54:20.762570 INFO: [NOCDAPC] D7_APC_0: 0x0
10101 22:54:20.765830 INFO: [NOCDAPC] D7_APC_1: 0xfff
10102 22:54:20.769247 INFO: [NOCDAPC] D8_APC_0: 0x0
10103 22:54:20.769728 INFO: [NOCDAPC] D8_APC_1: 0xfff
10104 22:54:20.772565 INFO: [NOCDAPC] D9_APC_0: 0x0
10105 22:54:20.775521 INFO: [NOCDAPC] D9_APC_1: 0xfff
10106 22:54:20.779285 INFO: [NOCDAPC] D10_APC_0: 0x0
10107 22:54:20.782485 INFO: [NOCDAPC] D10_APC_1: 0xfff
10108 22:54:20.786030 INFO: [NOCDAPC] D11_APC_0: 0x0
10109 22:54:20.788911 INFO: [NOCDAPC] D11_APC_1: 0xfff
10110 22:54:20.791898 INFO: [NOCDAPC] D12_APC_0: 0x0
10111 22:54:20.795350 INFO: [NOCDAPC] D12_APC_1: 0xfff
10112 22:54:20.798777 INFO: [NOCDAPC] D13_APC_0: 0x0
10113 22:54:20.801909 INFO: [NOCDAPC] D13_APC_1: 0xfff
10114 22:54:20.805877 INFO: [NOCDAPC] D14_APC_0: 0x0
10115 22:54:20.808897 INFO: [NOCDAPC] D14_APC_1: 0xfff
10116 22:54:20.812208 INFO: [NOCDAPC] D15_APC_0: 0x0
10117 22:54:20.815373 INFO: [NOCDAPC] D15_APC_1: 0xfff
10118 22:54:20.816009 INFO: [NOCDAPC] APC_CON: 0x4
10119 22:54:20.818895 INFO: [APUAPC] set_apusys_apc done
10120 22:54:20.822166 INFO: [DEVAPC] devapc_init done
10121 22:54:20.828836 INFO: GICv3 without legacy support detected.
10122 22:54:20.832377 INFO: ARM GICv3 driver initialized in EL3
10123 22:54:20.835407 INFO: Maximum SPI INTID supported: 639
10124 22:54:20.838960 INFO: BL31: Initializing runtime services
10125 22:54:20.845304 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10126 22:54:20.848654 INFO: SPM: enable CPC mode
10127 22:54:20.852047 INFO: mcdi ready for mcusys-off-idle and system suspend
10128 22:54:20.858895 INFO: BL31: Preparing for EL3 exit to normal world
10129 22:54:20.861839 INFO: Entry point address = 0x80000000
10130 22:54:20.862404 INFO: SPSR = 0x8
10131 22:54:20.869085
10132 22:54:20.869678
10133 22:54:20.870039
10134 22:54:20.872069 Starting depthcharge on Spherion...
10135 22:54:20.872630
10136 22:54:20.872991 Wipe memory regions:
10137 22:54:20.873327
10138 22:54:20.875772 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
10139 22:54:20.876317 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
10140 22:54:20.876751 Setting prompt string to ['asurada:']
10141 22:54:20.877187 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
10142 22:54:20.877934 [0x00000040000000, 0x00000054600000)
10143 22:54:20.997892
10144 22:54:20.998446 [0x00000054660000, 0x00000080000000)
10145 22:54:21.258814
10146 22:54:21.259372 [0x000000821a7280, 0x000000ffe64000)
10147 22:54:22.003986
10148 22:54:22.004541 [0x00000100000000, 0x00000240000000)
10149 22:54:23.893570
10150 22:54:23.897240 Initializing XHCI USB controller at 0x11200000.
10151 22:54:24.935262
10152 22:54:24.938216 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10153 22:54:24.938713
10154 22:54:24.939193
10155 22:54:24.939641
10156 22:54:24.940665 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10158 22:54:25.042221 asurada: tftpboot 192.168.201.1 13683732/tftp-deploy-ew_mgp1_/kernel/image.itb 13683732/tftp-deploy-ew_mgp1_/kernel/cmdline
10159 22:54:25.042917 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10160 22:54:25.043455 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:22)
10161 22:54:25.047991 tftpboot 192.168.201.1 13683732/tftp-deploy-ew_mgp1_/kernel/image.ittp-deploy-ew_mgp1_/kernel/cmdline
10162 22:54:25.048506
10163 22:54:25.048981 Waiting for link
10164 22:54:25.206287
10165 22:54:25.206852 R8152: Initializing
10166 22:54:25.207333
10167 22:54:25.209489 Version 6 (ocp_data = 5c30)
10168 22:54:25.209946
10169 22:54:25.213169 R8152: Done initializing
10170 22:54:25.213767
10171 22:54:25.214128 Adding net device
10172 22:54:27.114421
10173 22:54:27.115003 done.
10174 22:54:27.115366
10175 22:54:27.115699 MAC: 00:e0:4c:68:02:81
10176 22:54:27.116024
10177 22:54:27.117537 Sending DHCP discover... done.
10178 22:54:27.117999
10179 22:54:27.120898 Waiting for reply... done.
10180 22:54:27.121518
10181 22:54:27.124049 Sending DHCP request... done.
10182 22:54:27.124525
10183 22:54:27.127460 Waiting for reply... done.
10184 22:54:27.127920
10185 22:54:27.128278 My ip is 192.168.201.14
10186 22:54:27.128614
10187 22:54:27.130607 The DHCP server ip is 192.168.201.1
10188 22:54:27.131170
10189 22:54:27.137546 TFTP server IP predefined by user: 192.168.201.1
10190 22:54:27.138101
10191 22:54:27.143619 Bootfile predefined by user: 13683732/tftp-deploy-ew_mgp1_/kernel/image.itb
10192 22:54:27.144163
10193 22:54:27.147203 Sending tftp read request... done.
10194 22:54:27.147662
10195 22:54:27.154028 Waiting for the transfer...
10196 22:54:27.154539
10197 22:54:27.857438 00000000 ################################################################
10198 22:54:27.857972
10199 22:54:28.518120 00080000 ################################################################
10200 22:54:28.518654
10201 22:54:29.220148 00100000 ################################################################
10202 22:54:29.220681
10203 22:54:29.928800 00180000 ################################################################
10204 22:54:29.928969
10205 22:54:30.628278 00200000 ################################################################
10206 22:54:30.628838
10207 22:54:31.327232 00280000 ################################################################
10208 22:54:31.327761
10209 22:54:32.046783 00300000 ################################################################
10210 22:54:32.047438
10211 22:54:32.741258 00380000 ################################################################
10212 22:54:32.741913
10213 22:54:33.440895 00400000 ################################################################
10214 22:54:33.441452
10215 22:54:34.136933 00480000 ################################################################
10216 22:54:34.137487
10217 22:54:34.834500 00500000 ################################################################
10218 22:54:34.835027
10219 22:54:35.536008 00580000 ################################################################
10220 22:54:35.536650
10221 22:54:36.228624 00600000 ################################################################
10222 22:54:36.229137
10223 22:54:36.920660 00680000 ################################################################
10224 22:54:36.921173
10225 22:54:37.609016 00700000 ################################################################
10226 22:54:37.609622
10227 22:54:38.307144 00780000 ################################################################
10228 22:54:38.307753
10229 22:54:39.001546 00800000 ################################################################
10230 22:54:39.002068
10231 22:54:39.698120 00880000 ################################################################
10232 22:54:39.698632
10233 22:54:40.395878 00900000 ################################################################
10234 22:54:40.396428
10235 22:54:41.093778 00980000 ################################################################
10236 22:54:41.094290
10237 22:54:41.792441 00a00000 ################################################################
10238 22:54:41.792944
10239 22:54:42.505858 00a80000 ################################################################
10240 22:54:42.506369
10241 22:54:43.210795 00b00000 ################################################################
10242 22:54:43.211354
10243 22:54:43.925205 00b80000 ################################################################
10244 22:54:43.925834
10245 22:54:44.633286 00c00000 ################################################################
10246 22:54:44.633868
10247 22:54:45.346524 00c80000 ################################################################
10248 22:54:45.347049
10249 22:54:46.047792 00d00000 ################################################################
10250 22:54:46.048340
10251 22:54:46.761953 00d80000 ################################################################
10252 22:54:46.762459
10253 22:54:47.477632 00e00000 ################################################################
10254 22:54:47.478134
10255 22:54:48.173168 00e80000 ################################################################
10256 22:54:48.173778
10257 22:54:48.853768 00f00000 ################################################################
10258 22:54:48.854316
10259 22:54:49.520272 00f80000 ################################################################
10260 22:54:49.520757
10261 22:54:50.217806 01000000 ################################################################
10262 22:54:50.218325
10263 22:54:50.917615 01080000 ################################################################
10264 22:54:50.918150
10265 22:54:51.611947 01100000 ################################################################
10266 22:54:51.612480
10267 22:54:52.332130 01180000 ################################################################
10268 22:54:52.332751
10269 22:54:53.009359 01200000 ################################################################
10270 22:54:53.009950
10271 22:54:53.715331 01280000 ################################################################
10272 22:54:53.715876
10273 22:54:54.418738 01300000 ################################################################
10274 22:54:54.419249
10275 22:54:55.118128 01380000 ################################################################
10276 22:54:55.118648
10277 22:54:55.826703 01400000 ################################################################
10278 22:54:55.827254
10279 22:54:56.535852 01480000 ################################################################
10280 22:54:56.536447
10281 22:54:57.239795 01500000 ################################################################
10282 22:54:57.240385
10283 22:54:57.929762 01580000 ################################################################
10284 22:54:57.930331
10285 22:54:58.643305 01600000 ################################################################
10286 22:54:58.643812
10287 22:54:59.359242 01680000 ################################################################
10288 22:54:59.359762
10289 22:55:00.063986 01700000 ################################################################
10290 22:55:00.064495
10291 22:55:00.779538 01780000 ################################################################
10292 22:55:00.780091
10293 22:55:01.484532 01800000 ################################################################
10294 22:55:01.485067
10295 22:55:02.189020 01880000 ################################################################
10296 22:55:02.189640
10297 22:55:02.895973 01900000 ################################################################
10298 22:55:02.896566
10299 22:55:03.596418 01980000 ################################################################
10300 22:55:03.596924
10301 22:55:04.286573 01a00000 ################################################################
10302 22:55:04.287096
10303 22:55:04.962027 01a80000 ################################################################
10304 22:55:04.962171
10305 22:55:05.620919 01b00000 ################################################################
10306 22:55:05.621494
10307 22:55:06.312232 01b80000 ################################################################
10308 22:55:06.312805
10309 22:55:07.010672 01c00000 ################################################################
10310 22:55:07.011222
10311 22:55:07.703230 01c80000 ################################################################
10312 22:55:07.703773
10313 22:55:08.386520 01d00000 ################################################################
10314 22:55:08.387063
10315 22:55:09.085027 01d80000 ################################################################
10316 22:55:09.085554
10317 22:55:09.583213 01e00000 ############################################### done.
10318 22:55:09.583727
10319 22:55:09.586687 The bootfile was 31840178 bytes long.
10320 22:55:09.587108
10321 22:55:09.589879 Sending tftp read request... done.
10322 22:55:09.590294
10323 22:55:09.593660 Waiting for the transfer...
10324 22:55:09.594073
10325 22:55:09.594398 00000000 # done.
10326 22:55:09.594712
10327 22:55:09.600273 Command line loaded dynamically from TFTP file: 13683732/tftp-deploy-ew_mgp1_/kernel/cmdline
10328 22:55:09.603160
10329 22:55:09.623311 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/13683732/extract-nfsrootfs-j2ki1x35,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10330 22:55:09.623922
10331 22:55:09.626661 Loading FIT.
10332 22:55:09.627113
10333 22:55:09.629399 Image ramdisk-1 has 18731331 bytes.
10334 22:55:09.629846
10335 22:55:09.630169 Image fdt-1 has 47258 bytes.
10336 22:55:09.630469
10337 22:55:09.633021 Image kernel-1 has 13059555 bytes.
10338 22:55:09.633569
10339 22:55:09.643037 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10340 22:55:09.643546
10341 22:55:09.659101 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10342 22:55:09.659635
10343 22:55:09.665259 Choosing best match conf-1 for compat google,spherion-rev2.
10344 22:55:09.669731
10345 22:55:09.674144 Connected to device vid:did:rid of 1ae0:0028:00
10346 22:55:09.681218
10347 22:55:09.684601 tpm_get_response: command 0x17b, return code 0x0
10348 22:55:09.685020
10349 22:55:09.687725 ec_init: CrosEC protocol v3 supported (256, 248)
10350 22:55:09.692381
10351 22:55:09.695212 tpm_cleanup: add release locality here.
10352 22:55:09.695735
10353 22:55:09.698537 Shutting down all USB controllers.
10354 22:55:09.699053
10355 22:55:09.699380 Removing current net device
10356 22:55:09.699684
10357 22:55:09.705168 Exiting depthcharge with code 4 at timestamp: 78268158
10358 22:55:09.705605
10359 22:55:09.707938 LZMA decompressing kernel-1 to 0x821a6718
10360 22:55:09.708389
10361 22:55:09.711546 LZMA decompressing kernel-1 to 0x40000000
10362 22:55:11.323160
10363 22:55:11.323716 jumping to kernel
10364 22:55:11.325520 end: 2.2.4 bootloader-commands (duration 00:00:50) [common]
10365 22:55:11.326104 start: 2.2.5 auto-login-action (timeout 00:03:36) [common]
10366 22:55:11.326521 Setting prompt string to ['Linux version [0-9]']
10367 22:55:11.326901 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10368 22:55:11.327273 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10369 22:55:11.404823
10370 22:55:11.408222 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10371 22:55:11.412427 start: 2.2.5.1 login-action (timeout 00:03:36) [common]
10372 22:55:11.413024 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10373 22:55:11.413470 Setting prompt string to []
10374 22:55:11.413888 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10375 22:55:11.414303 Using line separator: #'\n'#
10376 22:55:11.414635 No login prompt set.
10377 22:55:11.414957 Parsing kernel messages
10378 22:55:11.415264 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10379 22:55:11.415823 [login-action] Waiting for messages, (timeout 00:03:36)
10380 22:55:11.416176 Waiting using forced prompt support (timeout 00:01:48)
10381 22:55:11.431056 [ 0.000000] Linux version 6.1.90-cip20 (KernelCI@build-j189066-arm64-gcc-10-defconfig-arm64-chromebook-glbz2) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue May 7 22:33:59 UTC 2024
10382 22:55:11.434294 [ 0.000000] random: crng init done
10383 22:55:11.440880 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10384 22:55:11.444521 [ 0.000000] efi: UEFI not found.
10385 22:55:11.450795 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10386 22:55:11.460860 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10387 22:55:11.470759 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10388 22:55:11.477427 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10389 22:55:11.483902 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10390 22:55:11.490339 [ 0.000000] printk: bootconsole [mtk8250] enabled
10391 22:55:11.497314 [ 0.000000] NUMA: No NUMA configuration found
10392 22:55:11.503868 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10393 22:55:11.509939 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10394 22:55:11.510578 [ 0.000000] Zone ranges:
10395 22:55:11.516683 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10396 22:55:11.519697 [ 0.000000] DMA32 empty
10397 22:55:11.526612 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10398 22:55:11.529573 [ 0.000000] Movable zone start for each node
10399 22:55:11.533221 [ 0.000000] Early memory node ranges
10400 22:55:11.539557 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10401 22:55:11.546203 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10402 22:55:11.553136 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10403 22:55:11.559498 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10404 22:55:11.566162 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10405 22:55:11.572704 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10406 22:55:11.629889 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10407 22:55:11.636504 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10408 22:55:11.643268 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10409 22:55:11.646016 [ 0.000000] psci: probing for conduit method from DT.
10410 22:55:11.652673 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10411 22:55:11.656442 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10412 22:55:11.662689 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10413 22:55:11.666124 [ 0.000000] psci: SMC Calling Convention v1.2
10414 22:55:11.672576 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10415 22:55:11.676010 [ 0.000000] Detected VIPT I-cache on CPU0
10416 22:55:11.682401 [ 0.000000] CPU features: detected: GIC system register CPU interface
10417 22:55:11.689429 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10418 22:55:11.695777 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10419 22:55:11.702423 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10420 22:55:11.712157 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10421 22:55:11.718795 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10422 22:55:11.721599 [ 0.000000] alternatives: applying boot alternatives
10423 22:55:11.728721 [ 0.000000] Fallback order for Node 0: 0
10424 22:55:11.735466 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10425 22:55:11.738610 [ 0.000000] Policy zone: Normal
10426 22:55:11.761873 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/13683732/extract-nfsrootfs-j2ki1x35,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10427 22:55:11.771233 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10428 22:55:11.782070 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10429 22:55:11.791566 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10430 22:55:11.798027 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10431 22:55:11.801259 <6>[ 0.000000] software IO TLB: area num 8.
10432 22:55:11.857882 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10433 22:55:12.007625 <6>[ 0.000000] Memory: 7945892K/8385536K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 406876K reserved, 32768K cma-reserved)
10434 22:55:12.013809 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10435 22:55:12.020465 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10436 22:55:12.024071 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10437 22:55:12.030429 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10438 22:55:12.037070 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10439 22:55:12.040415 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10440 22:55:12.050439 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10441 22:55:12.056638 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10442 22:55:12.063392 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10443 22:55:12.070119 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10444 22:55:12.073136 <6>[ 0.000000] GICv3: 608 SPIs implemented
10445 22:55:12.076892 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10446 22:55:12.083445 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10447 22:55:12.086438 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10448 22:55:12.093699 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10449 22:55:12.106667 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10450 22:55:12.119775 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10451 22:55:12.126045 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10452 22:55:12.133796 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10453 22:55:12.146613 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10454 22:55:12.153542 <6>[ 0.000001] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10455 22:55:12.161355 <6>[ 0.009178] Console: colour dummy device 80x25
10456 22:55:12.169879 <6>[ 0.013906] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10457 22:55:12.176380 <6>[ 0.024412] pid_max: default: 32768 minimum: 301
10458 22:55:12.179745 <6>[ 0.029284] LSM: Security Framework initializing
10459 22:55:12.186216 <6>[ 0.034223] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10460 22:55:12.196191 <6>[ 0.042037] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10461 22:55:12.206480 <6>[ 0.051522] cblist_init_generic: Setting adjustable number of callback queues.
10462 22:55:12.212835 <6>[ 0.058968] cblist_init_generic: Setting shift to 3 and lim to 1.
10463 22:55:12.219549 <6>[ 0.065306] cblist_init_generic: Setting adjustable number of callback queues.
10464 22:55:12.226028 <6>[ 0.072732] cblist_init_generic: Setting shift to 3 and lim to 1.
10465 22:55:12.229243 <6>[ 0.079171] rcu: Hierarchical SRCU implementation.
10466 22:55:12.236119 <6>[ 0.084186] rcu: Max phase no-delay instances is 1000.
10467 22:55:12.242926 <6>[ 0.091241] EFI services will not be available.
10468 22:55:12.246188 <6>[ 0.096200] smp: Bringing up secondary CPUs ...
10469 22:55:12.254747 <6>[ 0.101279] Detected VIPT I-cache on CPU1
10470 22:55:12.261392 <6>[ 0.101352] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10471 22:55:12.267829 <6>[ 0.101384] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10472 22:55:12.270924 <6>[ 0.101725] Detected VIPT I-cache on CPU2
10473 22:55:12.280978 <6>[ 0.101776] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10474 22:55:12.287452 <6>[ 0.101792] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10475 22:55:12.290893 <6>[ 0.102057] Detected VIPT I-cache on CPU3
10476 22:55:12.297153 <6>[ 0.102103] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10477 22:55:12.304089 <6>[ 0.102117] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10478 22:55:12.310522 <6>[ 0.102420] CPU features: detected: Spectre-v4
10479 22:55:12.314279 <6>[ 0.102426] CPU features: detected: Spectre-BHB
10480 22:55:12.317544 <6>[ 0.102432] Detected PIPT I-cache on CPU4
10481 22:55:12.323935 <6>[ 0.102491] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10482 22:55:12.333294 <6>[ 0.102508] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10483 22:55:12.336990 <6>[ 0.102803] Detected PIPT I-cache on CPU5
10484 22:55:12.343911 <6>[ 0.102864] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10485 22:55:12.349878 <6>[ 0.102880] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10486 22:55:12.353445 <6>[ 0.103163] Detected PIPT I-cache on CPU6
10487 22:55:12.363368 <6>[ 0.103228] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10488 22:55:12.370170 <6>[ 0.103244] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10489 22:55:12.372987 <6>[ 0.103543] Detected PIPT I-cache on CPU7
10490 22:55:12.379725 <6>[ 0.103608] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10491 22:55:12.386360 <6>[ 0.103623] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10492 22:55:12.389552 <6>[ 0.103671] smp: Brought up 1 node, 8 CPUs
10493 22:55:12.396114 <6>[ 0.244957] SMP: Total of 8 processors activated.
10494 22:55:12.402539 <6>[ 0.249878] CPU features: detected: 32-bit EL0 Support
10495 22:55:12.409088 <6>[ 0.255241] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10496 22:55:12.415602 <6>[ 0.264096] CPU features: detected: Common not Private translations
10497 22:55:12.422541 <6>[ 0.270571] CPU features: detected: CRC32 instructions
10498 22:55:12.428818 <6>[ 0.275922] CPU features: detected: RCpc load-acquire (LDAPR)
10499 22:55:12.432826 <6>[ 0.281919] CPU features: detected: LSE atomic instructions
10500 22:55:12.438828 <6>[ 0.287701] CPU features: detected: Privileged Access Never
10501 22:55:12.445439 <6>[ 0.293480] CPU features: detected: RAS Extension Support
10502 22:55:12.451982 <6>[ 0.299089] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10503 22:55:12.455108 <6>[ 0.306309] CPU: All CPU(s) started at EL2
10504 22:55:12.461617 <6>[ 0.310625] alternatives: applying system-wide alternatives
10505 22:55:12.472498 <6>[ 0.321472] devtmpfs: initialized
10506 22:55:12.488404 <6>[ 0.330469] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10507 22:55:12.494904 <6>[ 0.340431] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10508 22:55:12.501660 <6>[ 0.348630] pinctrl core: initialized pinctrl subsystem
10509 22:55:12.504665 <6>[ 0.355285] DMI not present or invalid.
10510 22:55:12.511494 <6>[ 0.359703] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10511 22:55:12.521588 <6>[ 0.366581] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10512 22:55:12.528006 <6>[ 0.374169] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10513 22:55:12.537664 <6>[ 0.382399] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10514 22:55:12.541195 <6>[ 0.390642] audit: initializing netlink subsys (disabled)
10515 22:55:12.551364 <5>[ 0.396323] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10516 22:55:12.557396 <6>[ 0.397004] thermal_sys: Registered thermal governor 'step_wise'
10517 22:55:12.564516 <6>[ 0.404291] thermal_sys: Registered thermal governor 'power_allocator'
10518 22:55:12.567523 <6>[ 0.410546] cpuidle: using governor menu
10519 22:55:12.573734 <6>[ 0.421505] NET: Registered PF_QIPCRTR protocol family
10520 22:55:12.580635 <6>[ 0.426993] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10521 22:55:12.587287 <6>[ 0.434095] ASID allocator initialised with 32768 entries
10522 22:55:12.590554 <6>[ 0.440666] Serial: AMBA PL011 UART driver
10523 22:55:12.599923 <4>[ 0.449384] Trying to register duplicate clock ID: 134
10524 22:55:12.658722 <6>[ 0.511040] KASLR enabled
10525 22:55:12.673116 <6>[ 0.518866] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10526 22:55:12.679746 <6>[ 0.525880] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10527 22:55:12.686440 <6>[ 0.532370] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10528 22:55:12.692559 <6>[ 0.539373] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10529 22:55:12.699425 <6>[ 0.545860] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10530 22:55:12.705938 <6>[ 0.552862] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10531 22:55:12.713216 <6>[ 0.559350] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10532 22:55:12.719592 <6>[ 0.566353] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10533 22:55:12.722702 <6>[ 0.573879] ACPI: Interpreter disabled.
10534 22:55:12.731144 <6>[ 0.580320] iommu: Default domain type: Translated
10535 22:55:12.738293 <6>[ 0.585434] iommu: DMA domain TLB invalidation policy: strict mode
10536 22:55:12.741081 <5>[ 0.592096] SCSI subsystem initialized
10537 22:55:12.747987 <6>[ 0.596261] usbcore: registered new interface driver usbfs
10538 22:55:12.755074 <6>[ 0.601993] usbcore: registered new interface driver hub
10539 22:55:12.757550 <6>[ 0.607544] usbcore: registered new device driver usb
10540 22:55:12.764855 <6>[ 0.613643] pps_core: LinuxPPS API ver. 1 registered
10541 22:55:12.774315 <6>[ 0.618836] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10542 22:55:12.777691 <6>[ 0.628182] PTP clock support registered
10543 22:55:12.780973 <6>[ 0.632427] EDAC MC: Ver: 3.0.0
10544 22:55:12.788761 <6>[ 0.637584] FPGA manager framework
10545 22:55:12.794934 <6>[ 0.641272] Advanced Linux Sound Architecture Driver Initialized.
10546 22:55:12.798379 <6>[ 0.647978] vgaarb: loaded
10547 22:55:12.804838 <6>[ 0.651144] clocksource: Switched to clocksource arch_sys_counter
10548 22:55:12.808351 <5>[ 0.657586] VFS: Disk quotas dquot_6.6.0
10549 22:55:12.814830 <6>[ 0.661772] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10550 22:55:12.818474 <6>[ 0.668962] pnp: PnP ACPI: disabled
10551 22:55:12.826549 <6>[ 0.675701] NET: Registered PF_INET protocol family
10552 22:55:12.833236 <6>[ 0.681096] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10553 22:55:12.847893 <6>[ 0.693438] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10554 22:55:12.857364 <6>[ 0.702245] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10555 22:55:12.864088 <6>[ 0.710214] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10556 22:55:12.873600 <6>[ 0.718911] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10557 22:55:12.881142 <6>[ 0.728668] TCP: Hash tables configured (established 65536 bind 65536)
10558 22:55:12.887229 <6>[ 0.735534] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10559 22:55:12.897062 <6>[ 0.742736] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10560 22:55:12.903641 <6>[ 0.750440] NET: Registered PF_UNIX/PF_LOCAL protocol family
10561 22:55:12.910144 <6>[ 0.756589] RPC: Registered named UNIX socket transport module.
10562 22:55:12.913966 <6>[ 0.762744] RPC: Registered udp transport module.
10563 22:55:12.920513 <6>[ 0.767677] RPC: Registered tcp transport module.
10564 22:55:12.926658 <6>[ 0.772610] RPC: Registered tcp NFSv4.1 backchannel transport module.
10565 22:55:12.929806 <6>[ 0.779273] PCI: CLS 0 bytes, default 64
10566 22:55:12.933542 <6>[ 0.783588] Unpacking initramfs...
10567 22:55:12.950232 <6>[ 0.795664] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10568 22:55:12.959621 <6>[ 0.804334] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10569 22:55:12.963370 <6>[ 0.813186] kvm [1]: IPA Size Limit: 40 bits
10570 22:55:12.969555 <6>[ 0.817714] kvm [1]: GICv3: no GICV resource entry
10571 22:55:12.973047 <6>[ 0.822734] kvm [1]: disabling GICv2 emulation
10572 22:55:12.979625 <6>[ 0.827423] kvm [1]: GIC system register CPU interface enabled
10573 22:55:12.982766 <6>[ 0.833605] kvm [1]: vgic interrupt IRQ18
10574 22:55:12.989524 <6>[ 0.837962] kvm [1]: VHE mode initialized successfully
10575 22:55:12.996160 <5>[ 0.844357] Initialise system trusted keyrings
10576 22:55:13.002598 <6>[ 0.849140] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10577 22:55:13.009914 <6>[ 0.859200] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10578 22:55:13.017158 <5>[ 0.865571] NFS: Registering the id_resolver key type
10579 22:55:13.019907 <5>[ 0.870886] Key type id_resolver registered
10580 22:55:13.026692 <5>[ 0.875300] Key type id_legacy registered
10581 22:55:13.033083 <6>[ 0.879582] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10582 22:55:13.040118 <6>[ 0.886501] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10583 22:55:13.046034 <6>[ 0.894221] 9p: Installing v9fs 9p2000 file system support
10584 22:55:13.083608 <5>[ 0.932563] Key type asymmetric registered
10585 22:55:13.086717 <5>[ 0.936895] Asymmetric key parser 'x509' registered
10586 22:55:13.096689 <6>[ 0.942041] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10587 22:55:13.100370 <6>[ 0.949651] io scheduler mq-deadline registered
10588 22:55:13.102997 <6>[ 0.954430] io scheduler kyber registered
10589 22:55:13.122766 <6>[ 0.971495] EINJ: ACPI disabled.
10590 22:55:13.155932 <4>[ 0.998200] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10591 22:55:13.165393 <4>[ 1.008841] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10592 22:55:13.180849 <6>[ 1.030019] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10593 22:55:13.189070 <6>[ 1.038127] printk: console [ttyS0] disabled
10594 22:55:13.217187 <6>[ 1.062781] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10595 22:55:13.223774 <6>[ 1.072259] printk: console [ttyS0] enabled
10596 22:55:13.227029 <6>[ 1.072259] printk: console [ttyS0] enabled
10597 22:55:13.233466 <6>[ 1.081159] printk: bootconsole [mtk8250] disabled
10598 22:55:13.236556 <6>[ 1.081159] printk: bootconsole [mtk8250] disabled
10599 22:55:13.243327 <6>[ 1.092481] SuperH (H)SCI(F) driver initialized
10600 22:55:13.246690 <6>[ 1.097771] msm_serial: driver initialized
10601 22:55:13.260805 <6>[ 1.106715] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10602 22:55:13.270790 <6>[ 1.115271] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10603 22:55:13.277240 <6>[ 1.123812] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10604 22:55:13.287201 <6>[ 1.132439] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10605 22:55:13.297216 <6>[ 1.141145] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10606 22:55:13.304132 <6>[ 1.149864] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10607 22:55:13.313716 <6>[ 1.158403] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10608 22:55:13.320248 <6>[ 1.167200] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10609 22:55:13.329723 <6>[ 1.175742] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10610 22:55:13.342190 <6>[ 1.191231] loop: module loaded
10611 22:55:13.348438 <6>[ 1.197241] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10612 22:55:13.371725 <4>[ 1.220613] mtk-pmic-keys: Failed to locate of_node [id: -1]
10613 22:55:13.377966 <6>[ 1.227483] megasas: 07.719.03.00-rc1
10614 22:55:13.388274 <6>[ 1.237066] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10615 22:55:13.401538 <6>[ 1.250513] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10616 22:55:13.417656 <6>[ 1.266869] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10617 22:55:13.477973 <6>[ 1.320633] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10618 22:55:13.726023 <6>[ 1.575067] Freeing initrd memory: 18288K
10619 22:55:13.737239 <6>[ 1.586673] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10620 22:55:13.748640 <6>[ 1.597824] tun: Universal TUN/TAP device driver, 1.6
10621 22:55:13.752026 <6>[ 1.603887] thunder_xcv, ver 1.0
10622 22:55:13.755164 <6>[ 1.607393] thunder_bgx, ver 1.0
10623 22:55:13.758839 <6>[ 1.610882] nicpf, ver 1.0
10624 22:55:13.769064 <6>[ 1.614909] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10625 22:55:13.772624 <6>[ 1.622386] hns3: Copyright (c) 2017 Huawei Corporation.
10626 22:55:13.778867 <6>[ 1.627974] hclge is initializing
10627 22:55:13.782078 <6>[ 1.631555] e1000: Intel(R) PRO/1000 Network Driver
10628 22:55:13.788847 <6>[ 1.636685] e1000: Copyright (c) 1999-2006 Intel Corporation.
10629 22:55:13.795593 <6>[ 1.642700] e1000e: Intel(R) PRO/1000 Network Driver
10630 22:55:13.798996 <6>[ 1.647915] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10631 22:55:13.805261 <6>[ 1.654100] igb: Intel(R) Gigabit Ethernet Network Driver
10632 22:55:13.811860 <6>[ 1.659750] igb: Copyright (c) 2007-2014 Intel Corporation.
10633 22:55:13.817970 <6>[ 1.665587] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10634 22:55:13.824782 <6>[ 1.672105] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10635 22:55:13.828168 <6>[ 1.678565] sky2: driver version 1.30
10636 22:55:13.834661 <6>[ 1.683500] usbcore: registered new device driver r8152-cfgselector
10637 22:55:13.841586 <6>[ 1.690035] usbcore: registered new interface driver r8152
10638 22:55:13.848015 <6>[ 1.695858] VFIO - User Level meta-driver version: 0.3
10639 22:55:13.855058 <6>[ 1.704079] usbcore: registered new interface driver usb-storage
10640 22:55:13.861535 <6>[ 1.710525] usbcore: registered new device driver onboard-usb-hub
10641 22:55:13.870260 <6>[ 1.719686] mt6397-rtc mt6359-rtc: registered as rtc0
10642 22:55:13.880391 <6>[ 1.725145] mt6397-rtc mt6359-rtc: setting system clock to 2024-05-07T22:55:14 UTC (1715122514)
10643 22:55:13.883425 <6>[ 1.734711] i2c_dev: i2c /dev entries driver
10644 22:55:13.900707 <6>[ 1.746503] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10645 22:55:13.907216 <4>[ 1.755238] cpu cpu0: supply cpu not found, using dummy regulator
10646 22:55:13.914175 <4>[ 1.761660] cpu cpu1: supply cpu not found, using dummy regulator
10647 22:55:13.920725 <4>[ 1.768063] cpu cpu2: supply cpu not found, using dummy regulator
10648 22:55:13.927595 <4>[ 1.774470] cpu cpu3: supply cpu not found, using dummy regulator
10649 22:55:13.933872 <4>[ 1.780871] cpu cpu4: supply cpu not found, using dummy regulator
10650 22:55:13.940322 <4>[ 1.787268] cpu cpu5: supply cpu not found, using dummy regulator
10651 22:55:13.946906 <4>[ 1.793665] cpu cpu6: supply cpu not found, using dummy regulator
10652 22:55:13.953512 <4>[ 1.800063] cpu cpu7: supply cpu not found, using dummy regulator
10653 22:55:13.971410 <6>[ 1.820672] cpu cpu0: EM: created perf domain
10654 22:55:13.974650 <6>[ 1.825623] cpu cpu4: EM: created perf domain
10655 22:55:13.982101 <6>[ 1.831270] sdhci: Secure Digital Host Controller Interface driver
10656 22:55:13.988726 <6>[ 1.837699] sdhci: Copyright(c) Pierre Ossman
10657 22:55:13.995696 <6>[ 1.842661] Synopsys Designware Multimedia Card Interface Driver
10658 22:55:14.001920 <6>[ 1.849299] sdhci-pltfm: SDHCI platform and OF driver helper
10659 22:55:14.005187 <6>[ 1.849433] mmc0: CQHCI version 5.10
10660 22:55:14.012242 <6>[ 1.859311] ledtrig-cpu: registered to indicate activity on CPUs
10661 22:55:14.018656 <6>[ 1.866295] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10662 22:55:14.025148 <6>[ 1.873362] usbcore: registered new interface driver usbhid
10663 22:55:14.028550 <6>[ 1.879184] usbhid: USB HID core driver
10664 22:55:14.035066 <6>[ 1.883373] spi_master spi0: will run message pump with realtime priority
10665 22:55:14.078014 <6>[ 1.921069] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10666 22:55:14.096804 <6>[ 1.936126] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10667 22:55:14.100913 <6>[ 1.949735] mmc0: Command Queue Engine enabled
10668 22:55:14.107123 <6>[ 1.954495] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10669 22:55:14.114039 <6>[ 1.961436] cros-ec-spi spi0.0: Chrome EC device registered
10670 22:55:14.117444 <6>[ 1.961800] mmcblk0: mmc0:0001 DA4128 116 GiB
10671 22:55:14.134341 <6>[ 1.983418] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10672 22:55:14.144031 <6>[ 1.984464] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10673 22:55:14.151004 <6>[ 1.990644] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10674 22:55:14.154517 <6>[ 1.999921] NET: Registered PF_PACKET protocol family
10675 22:55:14.160593 <6>[ 2.004552] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10676 22:55:14.164198 <6>[ 2.009255] 9pnet: Installing 9P2000 support
10677 22:55:14.170702 <6>[ 2.015044] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10678 22:55:14.177269 <5>[ 2.018946] Key type dns_resolver registered
10679 22:55:14.180380 <6>[ 2.030399] registered taskstats version 1
10680 22:55:14.187010 <5>[ 2.034774] Loading compiled-in X.509 certificates
10681 22:55:14.214251 <4>[ 2.056638] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10682 22:55:14.224227 <4>[ 2.067438] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10683 22:55:14.230744 <3>[ 2.077969] debugfs: File 'uA_load' in directory '/' already present!
10684 22:55:14.237548 <3>[ 2.084674] debugfs: File 'min_uV' in directory '/' already present!
10685 22:55:14.243874 <3>[ 2.091344] debugfs: File 'max_uV' in directory '/' already present!
10686 22:55:14.250499 <3>[ 2.097961] debugfs: File 'constraint_flags' in directory '/' already present!
10687 22:55:14.264641 <6>[ 2.113611] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10688 22:55:14.271827 <6>[ 2.120555] xhci-mtk 11200000.usb: xHCI Host Controller
10689 22:55:14.278043 <6>[ 2.126101] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10690 22:55:14.288224 <6>[ 2.134019] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10691 22:55:14.294735 <6>[ 2.143478] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10692 22:55:14.301548 <6>[ 2.149530] xhci-mtk 11200000.usb: xHCI Host Controller
10693 22:55:14.308093 <6>[ 2.155008] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10694 22:55:14.314834 <6>[ 2.162660] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10695 22:55:14.321487 <6>[ 2.170466] hub 1-0:1.0: USB hub found
10696 22:55:14.324912 <6>[ 2.174497] hub 1-0:1.0: 1 port detected
10697 22:55:14.334878 <6>[ 2.178767] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10698 22:55:14.338086 <6>[ 2.187506] hub 2-0:1.0: USB hub found
10699 22:55:14.340997 <6>[ 2.191524] hub 2-0:1.0: 1 port detected
10700 22:55:14.350076 <6>[ 2.198882] mtk-msdc 11f70000.mmc: Got CD GPIO
10701 22:55:14.360744 <6>[ 2.206320] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10702 22:55:14.367207 <6>[ 2.214332] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10703 22:55:14.376907 <4>[ 2.222237] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10704 22:55:14.386906 <6>[ 2.231763] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10705 22:55:14.393991 <6>[ 2.239841] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10706 22:55:14.400322 <6>[ 2.247953] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10707 22:55:14.410799 <6>[ 2.255886] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10708 22:55:14.416946 <6>[ 2.263703] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10709 22:55:14.427050 <6>[ 2.271519] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10710 22:55:14.436496 <6>[ 2.281947] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10711 22:55:14.443835 <6>[ 2.290313] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10712 22:55:14.452940 <6>[ 2.298654] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10713 22:55:14.460011 <6>[ 2.306992] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10714 22:55:14.469579 <6>[ 2.315332] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10715 22:55:14.476472 <6>[ 2.323671] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10716 22:55:14.486226 <6>[ 2.332009] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10717 22:55:14.496292 <6>[ 2.340346] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10718 22:55:14.502659 <6>[ 2.348684] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10719 22:55:14.512384 <6>[ 2.357021] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10720 22:55:14.519736 <6>[ 2.365359] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10721 22:55:14.528883 <6>[ 2.373697] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10722 22:55:14.535643 <6>[ 2.382048] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10723 22:55:14.545810 <6>[ 2.390389] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10724 22:55:14.552570 <6>[ 2.398727] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10725 22:55:14.558836 <6>[ 2.407336] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10726 22:55:14.565837 <6>[ 2.414510] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10727 22:55:14.572110 <6>[ 2.421272] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10728 22:55:14.582247 <6>[ 2.428027] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10729 22:55:14.588961 <6>[ 2.434962] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10730 22:55:14.595320 <6>[ 2.441829] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10731 22:55:14.605105 <6>[ 2.450958] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10732 22:55:14.615045 <6>[ 2.460077] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10733 22:55:14.624763 <6>[ 2.469371] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10734 22:55:14.634950 <6>[ 2.478838] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10735 22:55:14.644636 <6>[ 2.488305] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10736 22:55:14.651372 <6>[ 2.497424] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10737 22:55:14.661698 <6>[ 2.506891] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10738 22:55:14.671329 <6>[ 2.516011] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10739 22:55:14.681037 <6>[ 2.525305] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10740 22:55:14.690592 <6>[ 2.535465] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10741 22:55:14.700615 <6>[ 2.546882] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10742 22:55:14.707630 <6>[ 2.556562] Trying to probe devices needed for running init ...
10743 22:55:14.753690 <6>[ 2.599422] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10744 22:55:14.908162 <6>[ 2.757500] hub 1-1:1.0: USB hub found
10745 22:55:14.911517 <6>[ 2.762019] hub 1-1:1.0: 4 ports detected
10746 22:55:14.921474 <6>[ 2.770677] hub 1-1:1.0: USB hub found
10747 22:55:14.924663 <6>[ 2.775015] hub 1-1:1.0: 4 ports detected
10748 22:55:15.033643 <6>[ 2.879780] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10749 22:55:15.059275 <6>[ 2.908577] hub 2-1:1.0: USB hub found
10750 22:55:15.062424 <6>[ 2.913074] hub 2-1:1.0: 3 ports detected
10751 22:55:15.071777 <6>[ 2.921072] hub 2-1:1.0: USB hub found
10752 22:55:15.075117 <6>[ 2.925587] hub 2-1:1.0: 3 ports detected
10753 22:55:15.249315 <6>[ 3.095294] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10754 22:55:15.382155 <6>[ 3.231333] hub 1-1.4:1.0: USB hub found
10755 22:55:15.385269 <6>[ 3.236007] hub 1-1.4:1.0: 2 ports detected
10756 22:55:15.395053 <6>[ 3.244196] hub 1-1.4:1.0: USB hub found
10757 22:55:15.398165 <6>[ 3.248749] hub 1-1.4:1.0: 2 ports detected
10758 22:55:15.461659 <6>[ 3.307656] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10759 22:55:15.570260 <6>[ 3.416109] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10760 22:55:15.606028 <4>[ 3.452168] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10761 22:55:15.615890 <4>[ 3.461257] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10762 22:55:15.651683 <6>[ 3.501035] r8152 2-1.3:1.0 eth0: v1.12.13
10763 22:55:15.693187 <6>[ 3.539502] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10764 22:55:15.885134 <6>[ 3.731300] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10765 22:55:17.250812 <6>[ 5.100599] r8152 2-1.3:1.0 eth0: carrier on
10766 22:55:20.149959 <5>[ 5.127255] Sending DHCP requests .., OK
10767 22:55:20.156121 <6>[ 8.003592] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10768 22:55:20.158989 <6>[ 8.011889] IP-Config: Complete:
10769 22:55:20.172694 <6>[ 8.015387] device=eth0, hwaddr=00:e0:4c:68:02:81, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10770 22:55:20.179673 <6>[ 8.026098] host=mt8192-asurada-spherion-r0-cbg-9, domain=lava-rack, nis-domain=(none)
10771 22:55:20.186068 <6>[ 8.034716] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10772 22:55:20.192275 <6>[ 8.034726] nameserver0=192.168.201.1
10773 22:55:20.195694 <6>[ 8.046875] clk: Disabling unused clocks
10774 22:55:20.199208 <6>[ 8.052229] ALSA device list:
10775 22:55:20.205644 <6>[ 8.055625] No soundcards found.
10776 22:55:20.213470 <6>[ 8.063395] Freeing unused kernel memory: 8512K
10777 22:55:20.216821 <6>[ 8.068300] Run /init as init process
10778 22:55:20.226193 Loading, please wait...
10779 22:55:20.252744 Starting systemd-udevd version 252.22-1~deb12u1
10780 22:55:20.253302
10781 22:55:20.481992 <6>[ 8.328527] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10782 22:55:20.492738 <6>[ 8.339309] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10783 22:55:20.502570 <6>[ 8.348057] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10784 22:55:20.532442 <4>[ 8.378882] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10785 22:55:20.547569 <4>[ 8.394364] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10786 22:55:20.562822 <3>[ 8.409141] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10787 22:55:20.569125 <3>[ 8.417493] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10788 22:55:20.576104 <6>[ 8.419565] mc: Linux media interface: v0.10
10789 22:55:20.582582 <3>[ 8.425609] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10790 22:55:20.592336 <3>[ 8.429807] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10791 22:55:20.599142 <6>[ 8.444250] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10792 22:55:20.608795 <3>[ 8.446454] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10793 22:55:20.615795 <3>[ 8.462191] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10794 22:55:20.622035 <3>[ 8.470351] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10795 22:55:20.632209 <4>[ 8.475990] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10796 22:55:20.638472 <4>[ 8.475990] Fallback method does not support PEC.
10797 22:55:20.644968 <3>[ 8.478461] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10798 22:55:20.655078 <6>[ 8.487979] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10799 22:55:20.664822 <6>[ 8.488905] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10800 22:55:20.672082 <6>[ 8.494348] videodev: Linux video capture interface: v2.00
10801 22:55:20.678537 <6>[ 8.499839] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10802 22:55:20.681615 <6>[ 8.499848] pci_bus 0000:00: root bus resource [bus 00-ff]
10803 22:55:20.688850 <6>[ 8.499855] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10804 22:55:20.698675 <6>[ 8.499858] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10805 22:55:20.706298 <6>[ 8.499918] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10806 22:55:20.715818 <6>[ 8.499939] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10807 22:55:20.718752 <6>[ 8.500036] pci 0000:00:00.0: supports D1 D2
10808 22:55:20.725428 <6>[ 8.500042] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10809 22:55:20.732208 <3>[ 8.500884] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10810 22:55:20.742388 <6>[ 8.501408] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10811 22:55:20.748702 <6>[ 8.501528] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10812 22:55:20.755176 <6>[ 8.501557] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10813 22:55:20.761937 <6>[ 8.501577] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10814 22:55:20.771907 <6>[ 8.501592] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10815 22:55:20.775214 <6>[ 8.501713] pci 0000:01:00.0: supports D1 D2
10816 22:55:20.781781 <6>[ 8.501715] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10817 22:55:20.791837 <6>[ 8.510435] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10818 22:55:20.798545 <6>[ 8.515396] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10819 22:55:20.805070 <6>[ 8.515427] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10820 22:55:20.815523 <6>[ 8.515430] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10821 22:55:20.821767 <6>[ 8.515439] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10822 22:55:20.832403 <6>[ 8.515452] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10823 22:55:20.838212 <6>[ 8.515466] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10824 22:55:20.845410 <6>[ 8.515479] pci 0000:00:00.0: PCI bridge to [bus 01]
10825 22:55:20.851735 <6>[ 8.515485] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10826 22:55:20.858057 <6>[ 8.515629] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10827 22:55:20.864532 <6>[ 8.516130] pcieport 0000:00:00.0: PME: Signaling with IRQ 281
10828 22:55:20.871761 <6>[ 8.516458] pcieport 0000:00:00.0: AER: enabled with IRQ 281
10829 22:55:20.878026 <3>[ 8.519485] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10830 22:55:20.884908 <6>[ 8.532883] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10831 22:55:20.894554 <3>[ 8.537808] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10832 22:55:20.897942 <6>[ 8.550983] remoteproc remoteproc0: scp is available
10833 22:55:20.908387 <3>[ 8.554889] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10834 22:55:20.914030 <3>[ 8.555031] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10835 22:55:20.924393 <3>[ 8.555047] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10836 22:55:20.930793 <3>[ 8.555051] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10837 22:55:20.940916 <3>[ 8.555057] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10838 22:55:20.947595 <3>[ 8.555062] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10839 22:55:20.954048 <3>[ 8.555103] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10840 22:55:20.960324 <6>[ 8.555948] Bluetooth: Core ver 2.22
10841 22:55:20.964034 <6>[ 8.561831] remoteproc remoteproc0: powering up scp
10842 22:55:20.970228 <6>[ 8.569158] NET: Registered PF_BLUETOOTH protocol family
10843 22:55:20.980329 <3>[ 8.571157] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10844 22:55:20.986881 <6>[ 8.572074] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10845 22:55:20.993399 <5>[ 8.572455] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10846 22:55:21.003458 <6>[ 8.573632] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10847 22:55:21.006588 <6>[ 8.573651] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10848 22:55:21.019922 <6>[ 8.574641] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10849 22:55:21.026685 <6>[ 8.580581] Bluetooth: HCI device and connection manager initialized
10850 22:55:21.033544 <6>[ 8.580596] Bluetooth: HCI socket layer initialized
10851 22:55:21.036383 <6>[ 8.580600] Bluetooth: L2CAP socket layer initialized
10852 22:55:21.042834 <6>[ 8.580609] Bluetooth: SCO socket layer initialized
10853 22:55:21.049304 <6>[ 8.598797] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10854 22:55:21.056230 <5>[ 8.601131] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10855 22:55:21.062812 <5>[ 8.601367] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10856 22:55:21.073032 <4>[ 8.601433] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10857 22:55:21.079152 <6>[ 8.601438] cfg80211: failed to load regulatory.db
10858 22:55:21.082373 <6>[ 8.605164] usbcore: registered new interface driver uvcvideo
10859 22:55:21.089327 <6>[ 8.631251] usbcore: registered new interface driver btusb
10860 22:55:21.099215 <4>[ 8.632396] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10861 22:55:21.105871 <3>[ 8.632403] Bluetooth: hci0: Failed to load firmware file (-2)
10862 22:55:21.112209 <3>[ 8.632405] Bluetooth: hci0: Failed to set up firmware (-2)
10863 22:55:21.122243 <4>[ 8.632407] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10864 22:55:21.132170 <3>[ 8.662500] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10865 22:55:21.138314 <6>[ 8.696990] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10866 22:55:21.145156 <6>[ 8.698928] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10867 22:55:21.155065 <6>[ 8.698949] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10868 22:55:21.161760 <6>[ 8.698956] remoteproc remoteproc0: remote processor scp is now up
10869 22:55:21.168238 <6>[ 8.706799] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10870 22:55:21.175226 <6>[ 8.726583] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10871 22:55:21.181323 <6>[ 8.753570] mt7921e 0000:01:00.0: ASIC revision: 79610010
10872 22:55:21.188096 <6>[ 8.755231] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10873 22:55:21.197975 <6>[ 8.854019] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10874 22:55:21.198524 <6>[ 8.854019]
10875 22:55:21.201285 Begin: Loading essential drivers ... done.
10876 22:55:21.207841 Begin: Running /scripts/init-premount ... done.
10877 22:55:21.214628 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10878 22:55:21.224651 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10879 22:55:21.225176 Device /sys/class/net/eth0 found
10880 22:55:21.227846 done.
10881 22:55:21.234051 Begin: Waiting up to 180 secs for any network device to become available ... done.
10882 22:55:21.285491 IP-Config: eth0 hardware address 00:e0:4c:68:02:81 mtu 1500 DHCP
10883 22:55:21.292023 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10884 22:55:21.299007 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10885 22:55:21.305360 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10886 22:55:21.311788 host : mt8192-asurada-spherion-r0-cbg-9
10887 22:55:21.318432 domain : lava-rack
10888 22:55:21.321752 rootserver: 192.168.201.1 rootpath:
10889 22:55:21.324971 filename :
10890 22:55:21.463206 <6>[ 9.310559] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10891 22:55:21.470989 done.
10892 22:55:21.480067 Begin: Running /scripts/nfs-bottom ... done.
10893 22:55:21.497162 Begin: Running /scripts/init-bottom ... done.
10894 22:55:22.883517 <6>[ 10.734377] NET: Registered PF_INET6 protocol family
10895 22:55:22.891394 <6>[ 10.741926] Segment Routing with IPv6
10896 22:55:22.894420 <6>[ 10.745929] In-situ OAM (IOAM) with IPv6
10897 22:55:23.076920 <30>[ 10.900460] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10898 22:55:23.083071 <30>[ 10.933645] systemd[1]: Detected architecture arm64.
10899 22:55:23.094602
10900 22:55:23.097759 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10901 22:55:23.098296
10902 22:55:23.098630
10903 22:55:23.127868 <30>[ 10.977946] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10904 22:55:24.291941 <30>[ 12.139028] systemd[1]: Queued start job for default target graphical.target.
10905 22:55:24.345936 <30>[ 12.192609] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10906 22:55:24.352342 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10907 22:55:24.352829
10908 22:55:24.374230 <30>[ 12.221289] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10909 22:55:24.383959 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10910 22:55:24.384518
10911 22:55:24.402305 <30>[ 12.249216] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10912 22:55:24.411680 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10913 22:55:24.412319
10914 22:55:24.429654 <30>[ 12.276854] systemd[1]: Created slice user.slice - User and Session Slice.
10915 22:55:24.436811 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10916 22:55:24.437543
10917 22:55:24.460542 <30>[ 12.303817] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10918 22:55:24.466717 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10919 22:55:24.469865
10920 22:55:24.488072 <30>[ 12.331713] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10921 22:55:24.494544 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10922 22:55:24.495007
10923 22:55:24.522672 <30>[ 12.360100] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10924 22:55:24.533036 <30>[ 12.380032] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10925 22:55:24.539446 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10926 22:55:24.539998
10927 22:55:24.557090 <30>[ 12.403826] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10928 22:55:24.566760 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10929 22:55:24.567394
10930 22:55:24.584760 <30>[ 12.431537] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10931 22:55:24.594104 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10932 22:55:24.594785
10933 22:55:24.609731 <30>[ 12.460020] systemd[1]: Reached target paths.target - Path Units.
10934 22:55:24.616500 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10935 22:55:24.619692
10936 22:55:24.637046 <30>[ 12.483932] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10937 22:55:24.643292 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10938 22:55:24.643862
10939 22:55:24.657117 <30>[ 12.507411] systemd[1]: Reached target slices.target - Slice Units.
10940 22:55:24.666976 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10941 22:55:24.667543
10942 22:55:24.682011 <30>[ 12.531951] systemd[1]: Reached target swap.target - Swaps.
10943 22:55:24.688017 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10944 22:55:24.688551
10945 22:55:24.709168 <30>[ 12.555989] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10946 22:55:24.718327 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10947 22:55:24.719091
10948 22:55:24.736795 <30>[ 12.583961] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10949 22:55:24.746480 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10950 22:55:24.746948
10951 22:55:24.767676 <30>[ 12.614871] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10952 22:55:24.777596 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10953 22:55:24.778016
10954 22:55:24.793814 <30>[ 12.641104] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10955 22:55:24.803792 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10956 22:55:24.804301
10957 22:55:24.821244 <30>[ 12.668192] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10958 22:55:24.827479 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10959 22:55:24.828019
10960 22:55:24.845790 <30>[ 12.693106] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10961 22:55:24.855687 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10962 22:55:24.856161
10963 22:55:24.876341 <30>[ 12.723657] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10964 22:55:24.886166 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10965 22:55:24.886824
10966 22:55:24.904565 <30>[ 12.751952] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10967 22:55:24.914457 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10968 22:55:24.915008
10969 22:55:24.972904 <30>[ 12.819903] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10970 22:55:24.979549 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10971 22:55:24.980009
10972 22:55:25.003557 <30>[ 12.850483] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10973 22:55:25.009765 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10974 22:55:25.010230
10975 22:55:25.031903 <30>[ 12.878839] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10976 22:55:25.038246 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10977 22:55:25.038720
10978 22:55:25.063311 <30>[ 12.903920] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10979 22:55:25.079036 <30>[ 12.926156] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10980 22:55:25.089821 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10981 22:55:25.090244
10982 22:55:25.114268 <30>[ 12.961176] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10983 22:55:25.123770 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10984 22:55:25.124196
10985 22:55:25.146241 <30>[ 12.993308] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10986 22:55:25.155938 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10987 22:55:25.156413
10988 22:55:25.194071 <6>[ 13.041294] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10989 22:55:25.213880 <30>[ 13.060488] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10990 22:55:25.219844 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10991 22:55:25.220307
10992 22:55:25.245771 <30>[ 13.093191] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10993 22:55:25.255765 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10994 22:55:25.256335
10995 22:55:25.316857 <30>[ 13.164295] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10996 22:55:25.323731 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10997 22:55:25.324195
10998 22:55:25.348113 <30>[ 13.195484] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10999 22:55:25.354732 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
11000 22:55:25.355151
11001 22:55:25.361206 <6>[ 13.210927] fuse: init (API version 7.37)
11002 22:55:25.381438 <30>[ 13.228589] systemd[1]: Starting systemd-journald.service - Journal Service...
11003 22:55:25.388025 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
11004 22:55:25.388575
11005 22:55:25.422097 <30>[ 13.269255] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
11006 22:55:25.428669 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
11007 22:55:25.429096
11008 22:55:25.457796 <30>[ 13.301746] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
11009 22:55:25.464270 Starting [0;1;39msystemd-network-g… units from Kernel command line...
11010 22:55:25.464727
11011 22:55:25.490148 <30>[ 13.337617] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
11012 22:55:25.500602 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
11013 22:55:25.501049
11014 22:55:25.521014 <30>[ 13.368151] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
11015 22:55:25.527536 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
11016 22:55:25.527960
11017 22:55:25.552260 <3>[ 13.399723] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11018 22:55:25.559179 <30>[ 13.402128] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
11019 22:55:25.568842 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
11020 22:55:25.569264
11021 22:55:25.584698 <3>[ 13.431707] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11022 22:55:25.594211 <30>[ 13.432448] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
11023 22:55:25.600969 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
11024 22:55:25.601430
11025 22:55:25.621012 <30>[ 13.467951] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
11026 22:55:25.627835 <3>[ 13.470648] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11027 22:55:25.637496 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
11028 22:55:25.637921
11029 22:55:25.657055 <30>[ 13.503948] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
11030 22:55:25.667018 <3>[ 13.505894] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11031 22:55:25.673450 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
11032 22:55:25.673899
11033 22:55:25.694550 <30>[ 13.541036] systemd[1]: modprobe@configfs.service: Deactivated successfully.
11034 22:55:25.700621 <3>[ 13.542997] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11035 22:55:25.710439 <30>[ 13.549048] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
11036 22:55:25.717206 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
11037 22:55:25.717800
11038 22:55:25.730968 <3>[ 13.578364] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11039 22:55:25.741405 <30>[ 13.588791] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
11040 22:55:25.748677 <30>[ 13.597127] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
11041 22:55:25.764979 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Mo<3>[ 13.612104] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11042 22:55:25.768366 dule dm_mod.
11043 22:55:25.768819
11044 22:55:25.786221 <30>[ 13.632936] systemd[1]: modprobe@drm.service: Deactivated successfully.
11045 22:55:25.792801 <30>[ 13.640685] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
11046 22:55:25.802991 <3>[ 13.644723] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11047 22:55:25.809143 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
11048 22:55:25.809769
11049 22:55:25.829626 <30>[ 13.676727] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
11050 22:55:25.836425 <3>[ 13.679827] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11051 22:55:25.846840 <30>[ 13.685240] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
11052 22:55:25.856377 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
11053 22:55:25.856939
11054 22:55:25.871264 <3>[ 13.717835] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11055 22:55:25.882005 <30>[ 13.729340] systemd[1]: modprobe@fuse.service: Deactivated successfully.
11056 22:55:25.888763 <30>[ 13.736967] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
11057 22:55:25.902599 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m <3>[ 13.749548] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11058 22:55:25.905710 - Load Kernel Module fuse.
11059 22:55:25.906286
11060 22:55:25.923381 <30>[ 13.773531] systemd[1]: modprobe@loop.service: Deactivated successfully.
11061 22:55:25.933798 <30>[ 13.781201] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
11062 22:55:25.944117 <3>[ 13.783403] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11063 22:55:25.950432 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
11064 22:55:25.950970
11065 22:55:25.969924 <30>[ 13.816975] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.
11066 22:55:25.977011 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
11067 22:55:25.977663
11068 22:55:25.986880 <3>[ 13.832447] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11069 22:55:25.997732 <3>[ 13.833373] power_supply sbs-5-000b: driver failed to report `capacity_error_margin' property: -6
11070 22:55:26.010459 <4>[ 13.842328] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
11071 22:55:26.020068 <3>[ 13.842331] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
11072 22:55:26.030688 <30>[ 13.854122] systemd[1]: Finished systemd-network-generator.service - Generate network units from Kernel command line.
11073 22:55:26.043649 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk uni<3>[ 13.890820] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11074 22:55:26.046987 ts from Kernel command line.
11075 22:55:26.047493
11076 22:55:26.065805 <30>[ 13.912478] systemd[1]: Finished systemd-remount-fs.service - Remount Root and Kernel File Systems.
11077 22:55:26.075601 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
11078 22:55:26.076037
11079 22:55:26.094229 <30>[ 13.940783] systemd[1]: Finished systemd-udev-trigger.service - Coldplug All udev Devices.
11080 22:55:26.100707 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
11081 22:55:26.101133
11082 22:55:26.121424 <30>[ 13.968208] systemd[1]: Reached target network-pre.target - Preparation for Network.
11083 22:55:26.127832 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
11084 22:55:26.128267
11085 22:55:26.180710 <30>[ 14.027982] systemd[1]: Mounting sys-fs-fuse-connections.mount - FUSE Control File System...
11086 22:55:26.187533 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
11087 22:55:26.188035
11088 22:55:26.213808 <30>[ 14.060667] systemd[1]: Mounting sys-kernel-config.mount - Kernel Configuration File System...
11089 22:55:26.223277 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
11090 22:55:26.223700
11091 22:55:26.243929 <30>[ 14.087767] systemd[1]: systemd-firstboot.service - First Boot Wizard was skipped because of an unmet condition check (ConditionFirstBoot=yes).
11092 22:55:26.260750 <30>[ 14.101396] systemd[1]: systemd-pstore.service - Platform Persistent Storage Archival was skipped because of an unmet condition check (ConditionDirectoryNotEmpty=/sys/fs/pstore).
11093 22:55:26.275165 <30>[ 14.122609] systemd[1]: Starting systemd-random-seed.service - Load/Save Random Seed...
11094 22:55:26.282149 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
11095 22:55:26.282586
11096 22:55:26.307636 <30>[ 14.151786] systemd[1]: systemd-repart.service - Repartition Root Disk was skipped because no trigger condition checks were met.
11097 22:55:26.349443 <30>[ 14.196447] systemd[1]: Starting systemd-sysctl.service - Apply Kernel Variables...
11098 22:55:26.355703 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
11099 22:55:26.356171
11100 22:55:26.380629 <30>[ 14.227979] systemd[1]: Starting systemd-sysusers.service - Create System Users...
11101 22:55:26.387573 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
11102 22:55:26.388011
11103 22:55:26.416464 <30>[ 14.263872] systemd[1]: Started systemd-journald.service - Journal Service.
11104 22:55:26.423214 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
11105 22:55:26.423730
11106 22:55:26.445868 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
11107 22:55:26.446311
11108 22:55:26.464523 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
11109 22:55:26.464944
11110 22:55:26.482083 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
11111 22:55:26.482644
11112 22:55:26.501828 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
11113 22:55:26.502425
11114 22:55:26.521633 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
11115 22:55:26.522207
11116 22:55:26.561858 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
11117 22:55:26.562408
11118 22:55:26.582705 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
11119 22:55:26.582789
11120 22:55:26.633998 <46>[ 14.481593] systemd-journald[309]: Received client request to flush runtime journal.
11121 22:55:27.739019 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11122 22:55:27.739194
11123 22:55:27.756975 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11124 22:55:27.757118
11125 22:55:27.775673 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11126 22:55:27.775757
11127 22:55:28.049100 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11128 22:55:28.049262
11129 22:55:28.070146 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11130 22:55:28.070365
11131 22:55:28.093956 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11132 22:55:28.094353
11133 22:55:28.251393 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11134 22:55:28.251531
11135 22:55:28.306122 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11136 22:55:28.306217
11137 22:55:28.375519 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11138 22:55:28.375971
11139 22:55:28.679937 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11140 22:55:28.680446
11141 22:55:28.709160 <6>[ 16.559826] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11142 22:55:28.721468 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11143 22:55:28.721896
11144 22:55:28.764457 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11145 22:55:28.764901
11146 22:55:28.848261 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11147 22:55:28.848851
11148 22:55:28.868454 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11149 22:55:28.868539
11150 22:55:28.928070 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11151 22:55:28.928170
11152 22:55:28.948024 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11153 22:55:28.948120
11154 22:55:28.974343 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11155 22:55:28.974428
11156 22:55:29.020846 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11157 22:55:29.021364
11158 22:55:29.092287 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11159 22:55:29.092870
11160 22:55:29.118190 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11161 22:55:29.118668
11162 22:55:29.140300 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11163 22:55:29.140732
11164 22:55:29.178021 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11165 22:55:29.178531
11166 22:55:29.329076 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11167 22:55:29.329637
11168 22:55:29.348707 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11169 22:55:29.349278
11170 22:55:29.364567 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11171 22:55:29.365112
11172 22:55:29.380472 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11173 22:55:29.381038
11174 22:55:29.408610 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11175 22:55:29.409363
11176 22:55:29.428627 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11177 22:55:29.429194
11178 22:55:29.444143 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11179 22:55:29.444757
11180 22:55:29.464774 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11181 22:55:29.465322
11182 22:55:29.488663 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11183 22:55:29.489228
11184 22:55:29.507926 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11185 22:55:29.508467
11186 22:55:29.526560 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11187 22:55:29.527108
11188 22:55:29.543621 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11189 22:55:29.544090
11190 22:55:29.560307 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11191 22:55:29.560900
11192 22:55:29.606711 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11193 22:55:29.607359
11194 22:55:29.686232 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11195 22:55:29.686740
11196 22:55:29.786303 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11197 22:55:29.786811
11198 22:55:29.814706 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11199 22:55:29.815213
11200 22:55:29.943747 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11201 22:55:29.944276
11202 22:55:30.001073 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11203 22:55:30.001575
11204 22:55:30.021109 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11205 22:55:30.021197
11206 22:55:30.039739 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11207 22:55:30.039840
11208 22:55:30.058415 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11209 22:55:30.058633
11210 22:55:30.074880 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11211 22:55:30.075030
11212 22:55:30.128045 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11213 22:55:30.128623
11214 22:55:30.145930 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11215 22:55:30.146516
11216 22:55:30.165284 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11217 22:55:30.165913
11218 22:55:30.225907 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11219 22:55:30.226454
11220 22:55:30.278478 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11221 22:55:30.278809
11222 22:55:30.364393
11223 22:55:30.364920
11224 22:55:30.367777 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11225 22:55:30.368195
11226 22:55:30.370498 debian-bookworm-arm64 login: root (automatic login)
11227 22:55:30.370918
11228 22:55:30.371243
11229 22:55:30.708640 Linux debian-bookworm-arm64 6.1.90-cip20 #1 SMP PREEMPT Tue May 7 22:33:59 UTC 2024 aarch64
11230 22:55:30.709183
11231 22:55:30.715278 The programs included with the Debian GNU/Linux system are free software;
11232 22:55:30.722041 the exact distribution terms for each program are described in the
11233 22:55:30.725325 individual files in /usr/share/doc/*/copyright.
11234 22:55:30.725792
11235 22:55:30.731608 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11236 22:55:30.735197 permitted by applicable law.
11237 22:55:31.878321 Matched prompt #10: / #
11239 22:55:31.880025 Setting prompt string to ['/ #']
11240 22:55:31.880686 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11242 22:55:31.882175 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
11243 22:55:31.882646 start: 2.2.6 expect-shell-connection (timeout 00:03:15) [common]
11244 22:55:31.883291 Setting prompt string to ['/ #']
11245 22:55:31.883765 Forcing a shell prompt, looking for ['/ #']
11247 22:55:31.934517 / #
11248 22:55:31.935223 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11249 22:55:31.935729 Waiting using forced prompt support (timeout 00:02:30)
11250 22:55:31.940700
11251 22:55:31.941597 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11252 22:55:31.942237 start: 2.2.7 export-device-env (timeout 00:03:15) [common]
11254 22:55:32.043402 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/13683732/extract-nfsrootfs-j2ki1x35'
11255 22:55:32.049416 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/13683732/extract-nfsrootfs-j2ki1x35'
11257 22:55:32.151408 / # export NFS_SERVER_IP='192.168.201.1'
11258 22:55:32.158057 export NFS_SERVER_IP='192.168.201.1'
11259 22:55:32.158871 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11260 22:55:32.159410 end: 2.2 depthcharge-retry (duration 00:01:45) [common]
11261 22:55:32.159937 end: 2 depthcharge-action (duration 00:01:45) [common]
11262 22:55:32.160508 start: 3 lava-test-retry (timeout 00:07:37) [common]
11263 22:55:32.160992 start: 3.1 lava-test-shell (timeout 00:07:37) [common]
11264 22:55:32.161432 Using namespace: common
11266 22:55:32.262676 / # #
11267 22:55:32.263275 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11268 22:55:32.269500 #
11269 22:55:32.270346 Using /lava-13683732
11271 22:55:32.371864 / # export SHELL=/bin/bash
11272 22:55:32.378042 export SHELL=/bin/bash
11274 22:55:32.479933 / # . /lava-13683732/environment
11275 22:55:32.486209 . /lava-13683732/environment
11277 22:55:32.594288 / # /lava-13683732/bin/lava-test-runner /lava-13683732/0
11278 22:55:32.594956 Test shell timeout: 10s (minimum of the action and connection timeout)
11279 22:55:32.600667 /lava-13683732/bin/lava-test-runner /lava-13683732/0
11280 22:55:32.920950 + export TESTRUN_ID=0_timesync-off
11281 22:55:32.924009 + TESTRUN_ID=0_timesync-off
11282 22:55:32.927558 + cd /lava-13683732/0/tests/0_timesync-off
11283 22:55:32.930454 ++ cat uuid
11284 22:55:32.939028 + UUID=13683732_1.6.2.3.1
11285 22:55:32.939439 + set +x
11286 22:55:32.945515 <LAVA_SIGNAL_STARTRUN 0_timesync-off 13683732_1.6.2.3.1>
11287 22:55:32.946210 Received signal: <STARTRUN> 0_timesync-off 13683732_1.6.2.3.1
11288 22:55:32.946630 Starting test lava.0_timesync-off (13683732_1.6.2.3.1)
11289 22:55:32.947088 Skipping test definition patterns.
11290 22:55:32.948876 + systemctl stop systemd-timesyncd
11291 22:55:33.033563 + set +x
11292 22:55:33.036319 <LAVA_SIGNAL_ENDRUN 0_timesync-off 13683732_1.6.2.3.1>
11293 22:55:33.036991 Received signal: <ENDRUN> 0_timesync-off 13683732_1.6.2.3.1
11294 22:55:33.037419 Ending use of test pattern.
11295 22:55:33.037746 Ending test lava.0_timesync-off (13683732_1.6.2.3.1), duration 0.09
11297 22:55:33.142998 + export TESTRUN_ID=1_kselftest-dt
11298 22:55:33.146343 + TESTRUN_ID=1_kselftest-dt
11299 22:55:33.149429 + cd /lava-13683732/0/tests/1_kselftest-dt
11300 22:55:33.152709 ++ cat uuid
11301 22:55:33.163421 + UUID=13683732_1.6.2.3.5
11302 22:55:33.163843 + set +x
11303 22:55:33.170058 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 13683732_1.6.2.3.5>
11304 22:55:33.170764 Received signal: <STARTRUN> 1_kselftest-dt 13683732_1.6.2.3.5
11305 22:55:33.171141 Starting test lava.1_kselftest-dt (13683732_1.6.2.3.5)
11306 22:55:33.171653 Skipping test definition patterns.
11307 22:55:33.173214 + cd ./automated/linux/kselftest/
11308 22:55:33.196422 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.90-cip20/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11309 22:55:33.258809 INFO: install_deps skipped
11310 22:55:33.774342 --2024-05-07 22:55:34-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.90-cip20/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11311 22:55:33.796548 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11312 22:55:33.925928 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11313 22:55:34.054744 HTTP request sent, awaiting response... 200 OK
11314 22:55:34.057543 Length: 1651624 (1.6M) [application/octet-stream]
11315 22:55:34.061495 Saving to: 'kselftest_armhf.tar.gz'
11316 22:55:34.061966
11317 22:55:34.062433
11318 22:55:34.312894 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11319 22:55:34.569638 kselftest_armhf.tar 2%[ ] 47.81K 186KB/s
11320 22:55:35.006083 kselftest_armhf.tar 13%[=> ] 214.67K 417KB/s
11321 22:55:35.012726 kselftest_armhf.tar 50%[=========> ] 807.16K 849KB/s
11322 22:55:35.019146 kselftest_armhf.tar 100%[===================>] 1.57M 1.64MB/s in 1.0s
11323 22:55:35.019621
11324 22:55:35.166337 2024-05-07 22:55:35 (1.64 MB/s) - 'kselftest_armhf.tar.gz' saved [1651624/1651624]
11325 22:55:35.166921
11326 22:55:41.101603 skiplist:
11327 22:55:41.105069 ========================================
11328 22:55:41.107733 ========================================
11329 22:55:41.194464 ============== Tests to run ===============
11330 22:55:41.201133 ===========End Tests to run ===============
11331 22:55:41.207175 shardfile-dt fail
11332 22:55:41.236049 ./kselftest.sh: 131: cannot open /lava-13683732/0/tests/1_kselftest-dt/automated/linux/kselftest/output/kselftest.txt: No such file
11333 22:55:41.239023 + ../../utils/send-to-lava.sh ./output/result.txt
11334 22:55:41.334558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=fail>
11335 22:55:41.335109 + set +x
11336 22:55:41.335882 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=fail
11338 22:55:41.340933 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 13683732_1.6.2.3.5>
11339 22:55:41.341830 Received signal: <ENDRUN> 1_kselftest-dt 13683732_1.6.2.3.5
11340 22:55:41.342267 Ending use of test pattern.
11341 22:55:41.342701 Ending test lava.1_kselftest-dt (13683732_1.6.2.3.5), duration 8.17
11343 22:55:41.344147 ok: lava_test_shell seems to have completed
11344 22:55:41.344753 shardfile-dt: fail
11345 22:55:41.345257 end: 3.1 lava-test-shell (duration 00:00:09) [common]
11346 22:55:41.345832 end: 3 lava-test-retry (duration 00:00:09) [common]
11347 22:55:41.346486 start: 4 finalize (timeout 00:07:28) [common]
11348 22:55:41.347068 start: 4.1 power-off (timeout 00:00:30) [common]
11349 22:55:41.347966 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=off'
11350 22:55:41.598700 >> Command sent successfully.
11351 22:55:41.612090 Returned 0 in 0 seconds
11352 22:55:41.713279 end: 4.1 power-off (duration 00:00:00) [common]
11354 22:55:41.714786 start: 4.2 read-feedback (timeout 00:07:28) [common]
11356 22:55:41.716937 Listened to connection for namespace 'common' for up to 1s
11357 22:55:42.716931 Finalising connection for namespace 'common'
11358 22:55:42.717734 Disconnecting from shell: Finalise
11359 22:55:42.718253 / #
11360 22:55:42.819472 end: 4.2 read-feedback (duration 00:00:01) [common]
11361 22:55:42.820160 end: 4 finalize (duration 00:00:01) [common]
11362 22:55:42.820837 Cleaning after the job
11363 22:55:42.821412 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13683732/tftp-deploy-ew_mgp1_/ramdisk
11364 22:55:42.830655 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13683732/tftp-deploy-ew_mgp1_/kernel
11365 22:55:42.863032 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13683732/tftp-deploy-ew_mgp1_/dtb
11366 22:55:42.863395 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13683732/tftp-deploy-ew_mgp1_/nfsrootfs
11367 22:55:42.928005 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13683732/tftp-deploy-ew_mgp1_/modules
11368 22:55:42.933805 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/13683732
11369 22:55:43.472318 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/13683732
11370 22:55:43.472501 Job finished correctly