Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 24
- Errors: 0
- Kernel Errors: 26
- Boot result: PASS
1 22:52:57.179005 lava-dispatcher, installed at version: 2024.01
2 22:52:57.179186 start: 0 validate
3 22:52:57.179313 Start time: 2024-05-07 22:52:57.179306+00:00 (UTC)
4 22:52:57.179427 Using caching service: 'http://localhost/cache/?uri=%s'
5 22:52:57.179552 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 22:52:57.439897 Using caching service: 'http://localhost/cache/?uri=%s'
7 22:52:57.440637 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.90-cip20%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 22:52:57.694819 Using caching service: 'http://localhost/cache/?uri=%s'
9 22:52:57.695540 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.90-cip20%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 22:52:57.956589 Using caching service: 'http://localhost/cache/?uri=%s'
11 22:52:57.957380 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.90-cip20%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 22:52:58.225041 validate duration: 1.05
14 22:52:58.226449 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 22:52:58.227081 start: 1.1 download-retry (timeout 00:10:00) [common]
16 22:52:58.227622 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 22:52:58.228219 Not decompressing ramdisk as can be used compressed.
18 22:52:58.228686 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 22:52:58.229067 saving as /var/lib/lava/dispatcher/tmp/13683720/tftp-deploy-2rfxgyld/ramdisk/rootfs.cpio.gz
20 22:52:58.229447 total size: 8181887 (7 MB)
21 22:52:58.234596 progress 0 % (0 MB)
22 22:52:58.247102 progress 5 % (0 MB)
23 22:52:58.255439 progress 10 % (0 MB)
24 22:52:58.261460 progress 15 % (1 MB)
25 22:52:58.265865 progress 20 % (1 MB)
26 22:52:58.269986 progress 25 % (1 MB)
27 22:52:58.273348 progress 30 % (2 MB)
28 22:52:58.276763 progress 35 % (2 MB)
29 22:52:58.279755 progress 40 % (3 MB)
30 22:52:58.282620 progress 45 % (3 MB)
31 22:52:58.285194 progress 50 % (3 MB)
32 22:52:58.287715 progress 55 % (4 MB)
33 22:52:58.289988 progress 60 % (4 MB)
34 22:52:58.292251 progress 65 % (5 MB)
35 22:52:58.294393 progress 70 % (5 MB)
36 22:52:58.296664 progress 75 % (5 MB)
37 22:52:58.298732 progress 80 % (6 MB)
38 22:52:58.301098 progress 85 % (6 MB)
39 22:52:58.303185 progress 90 % (7 MB)
40 22:52:58.305481 progress 95 % (7 MB)
41 22:52:58.307449 progress 100 % (7 MB)
42 22:52:58.307646 7 MB downloaded in 0.08 s (99.76 MB/s)
43 22:52:58.307804 end: 1.1.1 http-download (duration 00:00:00) [common]
45 22:52:58.308041 end: 1.1 download-retry (duration 00:00:00) [common]
46 22:52:58.308130 start: 1.2 download-retry (timeout 00:10:00) [common]
47 22:52:58.308212 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 22:52:58.308338 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.90-cip20/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 22:52:58.308407 saving as /var/lib/lava/dispatcher/tmp/13683720/tftp-deploy-2rfxgyld/kernel/Image
50 22:52:58.308466 total size: 54682112 (52 MB)
51 22:52:58.308526 No compression specified
52 22:52:58.309620 progress 0 % (0 MB)
53 22:52:58.323272 progress 5 % (2 MB)
54 22:52:58.336966 progress 10 % (5 MB)
55 22:52:58.350716 progress 15 % (7 MB)
56 22:52:58.364329 progress 20 % (10 MB)
57 22:52:58.378189 progress 25 % (13 MB)
58 22:52:58.391935 progress 30 % (15 MB)
59 22:52:58.406089 progress 35 % (18 MB)
60 22:52:58.419798 progress 40 % (20 MB)
61 22:52:58.433415 progress 45 % (23 MB)
62 22:52:58.447192 progress 50 % (26 MB)
63 22:52:58.460798 progress 55 % (28 MB)
64 22:52:58.474514 progress 60 % (31 MB)
65 22:52:58.488128 progress 65 % (33 MB)
66 22:52:58.502163 progress 70 % (36 MB)
67 22:52:58.515907 progress 75 % (39 MB)
68 22:52:58.529845 progress 80 % (41 MB)
69 22:52:58.543396 progress 85 % (44 MB)
70 22:52:58.556969 progress 90 % (46 MB)
71 22:52:58.570624 progress 95 % (49 MB)
72 22:52:58.583978 progress 100 % (52 MB)
73 22:52:58.584224 52 MB downloaded in 0.28 s (189.11 MB/s)
74 22:52:58.584377 end: 1.2.1 http-download (duration 00:00:00) [common]
76 22:52:58.584610 end: 1.2 download-retry (duration 00:00:00) [common]
77 22:52:58.584700 start: 1.3 download-retry (timeout 00:10:00) [common]
78 22:52:58.584787 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 22:52:58.584923 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.90-cip20/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 22:52:58.584993 saving as /var/lib/lava/dispatcher/tmp/13683720/tftp-deploy-2rfxgyld/dtb/mt8192-asurada-spherion-r0.dtb
81 22:52:58.585054 total size: 47258 (0 MB)
82 22:52:58.585116 No compression specified
83 22:52:58.586207 progress 69 % (0 MB)
84 22:52:58.586481 progress 100 % (0 MB)
85 22:52:58.586636 0 MB downloaded in 0.00 s (28.52 MB/s)
86 22:52:58.586758 end: 1.3.1 http-download (duration 00:00:00) [common]
88 22:52:58.586978 end: 1.3 download-retry (duration 00:00:00) [common]
89 22:52:58.587063 start: 1.4 download-retry (timeout 00:10:00) [common]
90 22:52:58.587145 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 22:52:58.587255 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.90-cip20/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 22:52:58.587323 saving as /var/lib/lava/dispatcher/tmp/13683720/tftp-deploy-2rfxgyld/modules/modules.tar
93 22:52:58.587383 total size: 8594396 (8 MB)
94 22:52:58.587445 Using unxz to decompress xz
95 22:52:58.591095 progress 0 % (0 MB)
96 22:52:58.610227 progress 5 % (0 MB)
97 22:52:58.635018 progress 10 % (0 MB)
98 22:52:58.658977 progress 15 % (1 MB)
99 22:52:58.681953 progress 20 % (1 MB)
100 22:52:58.706817 progress 25 % (2 MB)
101 22:52:58.730495 progress 30 % (2 MB)
102 22:52:58.754174 progress 35 % (2 MB)
103 22:52:58.779069 progress 40 % (3 MB)
104 22:52:58.804393 progress 45 % (3 MB)
105 22:52:58.829228 progress 50 % (4 MB)
106 22:52:58.853768 progress 55 % (4 MB)
107 22:52:58.879485 progress 60 % (4 MB)
108 22:52:58.904489 progress 65 % (5 MB)
109 22:52:58.929613 progress 70 % (5 MB)
110 22:52:58.953636 progress 75 % (6 MB)
111 22:52:58.978762 progress 80 % (6 MB)
112 22:52:59.004282 progress 85 % (6 MB)
113 22:52:59.032986 progress 90 % (7 MB)
114 22:52:59.061822 progress 95 % (7 MB)
115 22:52:59.087644 progress 100 % (8 MB)
116 22:52:59.092867 8 MB downloaded in 0.51 s (16.21 MB/s)
117 22:52:59.093106 end: 1.4.1 http-download (duration 00:00:01) [common]
119 22:52:59.093373 end: 1.4 download-retry (duration 00:00:01) [common]
120 22:52:59.093469 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 22:52:59.093564 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 22:52:59.093647 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 22:52:59.093733 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 22:52:59.093949 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/13683720/lava-overlay-3ayqg931
125 22:52:59.094078 makedir: /var/lib/lava/dispatcher/tmp/13683720/lava-overlay-3ayqg931/lava-13683720/bin
126 22:52:59.094180 makedir: /var/lib/lava/dispatcher/tmp/13683720/lava-overlay-3ayqg931/lava-13683720/tests
127 22:52:59.094275 makedir: /var/lib/lava/dispatcher/tmp/13683720/lava-overlay-3ayqg931/lava-13683720/results
128 22:52:59.094388 Creating /var/lib/lava/dispatcher/tmp/13683720/lava-overlay-3ayqg931/lava-13683720/bin/lava-add-keys
129 22:52:59.094530 Creating /var/lib/lava/dispatcher/tmp/13683720/lava-overlay-3ayqg931/lava-13683720/bin/lava-add-sources
130 22:52:59.094657 Creating /var/lib/lava/dispatcher/tmp/13683720/lava-overlay-3ayqg931/lava-13683720/bin/lava-background-process-start
131 22:52:59.094783 Creating /var/lib/lava/dispatcher/tmp/13683720/lava-overlay-3ayqg931/lava-13683720/bin/lava-background-process-stop
132 22:52:59.094904 Creating /var/lib/lava/dispatcher/tmp/13683720/lava-overlay-3ayqg931/lava-13683720/bin/lava-common-functions
133 22:52:59.095022 Creating /var/lib/lava/dispatcher/tmp/13683720/lava-overlay-3ayqg931/lava-13683720/bin/lava-echo-ipv4
134 22:52:59.095145 Creating /var/lib/lava/dispatcher/tmp/13683720/lava-overlay-3ayqg931/lava-13683720/bin/lava-install-packages
135 22:52:59.095265 Creating /var/lib/lava/dispatcher/tmp/13683720/lava-overlay-3ayqg931/lava-13683720/bin/lava-installed-packages
136 22:52:59.095386 Creating /var/lib/lava/dispatcher/tmp/13683720/lava-overlay-3ayqg931/lava-13683720/bin/lava-os-build
137 22:52:59.095504 Creating /var/lib/lava/dispatcher/tmp/13683720/lava-overlay-3ayqg931/lava-13683720/bin/lava-probe-channel
138 22:52:59.095622 Creating /var/lib/lava/dispatcher/tmp/13683720/lava-overlay-3ayqg931/lava-13683720/bin/lava-probe-ip
139 22:52:59.095738 Creating /var/lib/lava/dispatcher/tmp/13683720/lava-overlay-3ayqg931/lava-13683720/bin/lava-target-ip
140 22:52:59.095855 Creating /var/lib/lava/dispatcher/tmp/13683720/lava-overlay-3ayqg931/lava-13683720/bin/lava-target-mac
141 22:52:59.095998 Creating /var/lib/lava/dispatcher/tmp/13683720/lava-overlay-3ayqg931/lava-13683720/bin/lava-target-storage
142 22:52:59.096171 Creating /var/lib/lava/dispatcher/tmp/13683720/lava-overlay-3ayqg931/lava-13683720/bin/lava-test-case
143 22:52:59.096318 Creating /var/lib/lava/dispatcher/tmp/13683720/lava-overlay-3ayqg931/lava-13683720/bin/lava-test-event
144 22:52:59.096441 Creating /var/lib/lava/dispatcher/tmp/13683720/lava-overlay-3ayqg931/lava-13683720/bin/lava-test-feedback
145 22:52:59.096562 Creating /var/lib/lava/dispatcher/tmp/13683720/lava-overlay-3ayqg931/lava-13683720/bin/lava-test-raise
146 22:52:59.096684 Creating /var/lib/lava/dispatcher/tmp/13683720/lava-overlay-3ayqg931/lava-13683720/bin/lava-test-reference
147 22:52:59.096801 Creating /var/lib/lava/dispatcher/tmp/13683720/lava-overlay-3ayqg931/lava-13683720/bin/lava-test-runner
148 22:52:59.096920 Creating /var/lib/lava/dispatcher/tmp/13683720/lava-overlay-3ayqg931/lava-13683720/bin/lava-test-set
149 22:52:59.097041 Creating /var/lib/lava/dispatcher/tmp/13683720/lava-overlay-3ayqg931/lava-13683720/bin/lava-test-shell
150 22:52:59.097163 Updating /var/lib/lava/dispatcher/tmp/13683720/lava-overlay-3ayqg931/lava-13683720/bin/lava-install-packages (oe)
151 22:52:59.097353 Updating /var/lib/lava/dispatcher/tmp/13683720/lava-overlay-3ayqg931/lava-13683720/bin/lava-installed-packages (oe)
152 22:52:59.097475 Creating /var/lib/lava/dispatcher/tmp/13683720/lava-overlay-3ayqg931/lava-13683720/environment
153 22:52:59.097577 LAVA metadata
154 22:52:59.097653 - LAVA_JOB_ID=13683720
155 22:52:59.097716 - LAVA_DISPATCHER_IP=192.168.201.1
156 22:52:59.097818 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 22:52:59.097886 skipped lava-vland-overlay
158 22:52:59.097960 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 22:52:59.098040 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 22:52:59.098104 skipped lava-multinode-overlay
161 22:52:59.098178 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 22:52:59.098263 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 22:52:59.098335 Loading test definitions
164 22:52:59.098426 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 22:52:59.098499 Using /lava-13683720 at stage 0
166 22:52:59.098801 uuid=13683720_1.5.2.3.1 testdef=None
167 22:52:59.098889 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 22:52:59.098976 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 22:52:59.099503 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 22:52:59.099725 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 22:52:59.100351 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 22:52:59.100583 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 22:52:59.101193 runner path: /var/lib/lava/dispatcher/tmp/13683720/lava-overlay-3ayqg931/lava-13683720/0/tests/0_dmesg test_uuid 13683720_1.5.2.3.1
176 22:52:59.101381 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 22:52:59.101592 Creating lava-test-runner.conf files
179 22:52:59.101656 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/13683720/lava-overlay-3ayqg931/lava-13683720/0 for stage 0
180 22:52:59.101743 - 0_dmesg
181 22:52:59.101837 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 22:52:59.101926 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 22:52:59.108902 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 22:52:59.109008 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 22:52:59.109097 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 22:52:59.109188 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 22:52:59.109275 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 22:52:59.345767 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
189 22:52:59.346127 start: 1.5.4 extract-modules (timeout 00:09:59) [common]
190 22:52:59.346239 extracting modules file /var/lib/lava/dispatcher/tmp/13683720/tftp-deploy-2rfxgyld/modules/modules.tar to /var/lib/lava/dispatcher/tmp/13683720/extract-overlay-ramdisk-_sp741iw/ramdisk
191 22:52:59.545982 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 22:52:59.546151 start: 1.5.5 apply-overlay-tftp (timeout 00:09:59) [common]
193 22:52:59.546248 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13683720/compress-overlay-qmi781aq/overlay-1.5.2.4.tar.gz to ramdisk
194 22:52:59.546323 [common] Applying overlay /var/lib/lava/dispatcher/tmp/13683720/compress-overlay-qmi781aq/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/13683720/extract-overlay-ramdisk-_sp741iw/ramdisk
195 22:52:59.552739 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 22:52:59.552854 start: 1.5.6 configure-preseed-file (timeout 00:09:59) [common]
197 22:52:59.552948 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 22:52:59.553036 start: 1.5.7 compress-ramdisk (timeout 00:09:59) [common]
199 22:52:59.553118 Building ramdisk /var/lib/lava/dispatcher/tmp/13683720/extract-overlay-ramdisk-_sp741iw/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/13683720/extract-overlay-ramdisk-_sp741iw/ramdisk
200 22:52:59.926589 >> 145109 blocks
201 22:53:02.175531 rename /var/lib/lava/dispatcher/tmp/13683720/extract-overlay-ramdisk-_sp741iw/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/13683720/tftp-deploy-2rfxgyld/ramdisk/ramdisk.cpio.gz
202 22:53:02.175955 end: 1.5.7 compress-ramdisk (duration 00:00:03) [common]
203 22:53:02.176085 start: 1.5.8 prepare-kernel (timeout 00:09:56) [common]
204 22:53:02.176188 start: 1.5.8.1 prepare-fit (timeout 00:09:56) [common]
205 22:53:02.176293 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/13683720/tftp-deploy-2rfxgyld/kernel/Image'
206 22:53:15.552282 Returned 0 in 13 seconds
207 22:53:15.652919 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/13683720/tftp-deploy-2rfxgyld/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/13683720/tftp-deploy-2rfxgyld/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/13683720/tftp-deploy-2rfxgyld/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/13683720/tftp-deploy-2rfxgyld/kernel/image.itb
208 22:53:16.055374 output: FIT description: Kernel Image image with one or more FDT blobs
209 22:53:16.055725 output: Created: Tue May 7 23:53:15 2024
210 22:53:16.055798 output: Image 0 (kernel-1)
211 22:53:16.055867 output: Description:
212 22:53:16.055930 output: Created: Tue May 7 23:53:15 2024
213 22:53:16.055994 output: Type: Kernel Image
214 22:53:16.056053 output: Compression: lzma compressed
215 22:53:16.056113 output: Data Size: 13059555 Bytes = 12753.47 KiB = 12.45 MiB
216 22:53:16.056176 output: Architecture: AArch64
217 22:53:16.056234 output: OS: Linux
218 22:53:16.056289 output: Load Address: 0x00000000
219 22:53:16.056345 output: Entry Point: 0x00000000
220 22:53:16.056403 output: Hash algo: crc32
221 22:53:16.056460 output: Hash value: 727ee7c6
222 22:53:16.056516 output: Image 1 (fdt-1)
223 22:53:16.056573 output: Description: mt8192-asurada-spherion-r0
224 22:53:16.056627 output: Created: Tue May 7 23:53:15 2024
225 22:53:16.056681 output: Type: Flat Device Tree
226 22:53:16.056735 output: Compression: uncompressed
227 22:53:16.056789 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 22:53:16.056843 output: Architecture: AArch64
229 22:53:16.056896 output: Hash algo: crc32
230 22:53:16.056950 output: Hash value: 0f8e4d2e
231 22:53:16.057003 output: Image 2 (ramdisk-1)
232 22:53:16.057057 output: Description: unavailable
233 22:53:16.057110 output: Created: Tue May 7 23:53:15 2024
234 22:53:16.057164 output: Type: RAMDisk Image
235 22:53:16.057217 output: Compression: Unknown Compression
236 22:53:16.057270 output: Data Size: 21363773 Bytes = 20863.06 KiB = 20.37 MiB
237 22:53:16.057335 output: Architecture: AArch64
238 22:53:16.057389 output: OS: Linux
239 22:53:16.057442 output: Load Address: unavailable
240 22:53:16.057496 output: Entry Point: unavailable
241 22:53:16.057549 output: Hash algo: crc32
242 22:53:16.057602 output: Hash value: b9bef3fc
243 22:53:16.057656 output: Default Configuration: 'conf-1'
244 22:53:16.057709 output: Configuration 0 (conf-1)
245 22:53:16.057762 output: Description: mt8192-asurada-spherion-r0
246 22:53:16.057815 output: Kernel: kernel-1
247 22:53:16.057869 output: Init Ramdisk: ramdisk-1
248 22:53:16.057922 output: FDT: fdt-1
249 22:53:16.057975 output: Loadables: kernel-1
250 22:53:16.058028 output:
251 22:53:16.058219 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 22:53:16.058322 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 22:53:16.058431 end: 1.5 prepare-tftp-overlay (duration 00:00:17) [common]
254 22:53:16.058527 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:42) [common]
255 22:53:16.058607 No LXC device requested
256 22:53:16.058687 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 22:53:16.058771 start: 1.7 deploy-device-env (timeout 00:09:42) [common]
258 22:53:16.058850 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 22:53:16.058919 Checking files for TFTP limit of 4294967296 bytes.
260 22:53:16.059409 end: 1 tftp-deploy (duration 00:00:18) [common]
261 22:53:16.059512 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 22:53:16.059606 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 22:53:16.059731 substitutions:
264 22:53:16.059798 - {DTB}: 13683720/tftp-deploy-2rfxgyld/dtb/mt8192-asurada-spherion-r0.dtb
265 22:53:16.059864 - {INITRD}: 13683720/tftp-deploy-2rfxgyld/ramdisk/ramdisk.cpio.gz
266 22:53:16.059924 - {KERNEL}: 13683720/tftp-deploy-2rfxgyld/kernel/Image
267 22:53:16.059982 - {LAVA_MAC}: None
268 22:53:16.060039 - {PRESEED_CONFIG}: None
269 22:53:16.060095 - {PRESEED_LOCAL}: None
270 22:53:16.060151 - {RAMDISK}: 13683720/tftp-deploy-2rfxgyld/ramdisk/ramdisk.cpio.gz
271 22:53:16.060206 - {ROOT_PART}: None
272 22:53:16.060260 - {ROOT}: None
273 22:53:16.060316 - {SERVER_IP}: 192.168.201.1
274 22:53:16.060370 - {TEE}: None
275 22:53:16.060424 Parsed boot commands:
276 22:53:16.060477 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 22:53:16.060648 Parsed boot commands: tftpboot 192.168.201.1 13683720/tftp-deploy-2rfxgyld/kernel/image.itb 13683720/tftp-deploy-2rfxgyld/kernel/cmdline
278 22:53:16.060740 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 22:53:16.060827 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 22:53:16.060915 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 22:53:16.061003 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 22:53:16.061074 Not connected, no need to disconnect.
283 22:53:16.061148 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 22:53:16.061232 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 22:53:16.061303 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
286 22:53:16.064720 Setting prompt string to ['lava-test: # ']
287 22:53:16.065046 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 22:53:16.065153 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 22:53:16.065251 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 22:53:16.065368 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 22:53:16.065565 Calling: '/usr/local/bin/chromebook-reboot.sh' 'mt8192-asurada-spherion-r0-cbg-1'
292 22:53:29.614420 Returned 0 in 13 seconds
293 22:53:29.715651 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
295 22:53:29.718329 end: 2.2.2 reset-device (duration 00:00:14) [common]
296 22:53:29.718868 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
297 22:53:29.719455 Setting prompt string to 'Starting depthcharge on Spherion...'
298 22:53:29.719856 Changing prompt to 'Starting depthcharge on Spherion...'
299 22:53:29.720239 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
300 22:53:29.721632 [Enter `^Ec?' for help]
301 22:53:29.722092
302 22:53:29.722589
303 22:53:29.722958 F0: 102B 0000
304 22:53:29.723308
305 22:53:29.723640 F3: 1001 0000 [0200]
306 22:53:29.723978
307 22:53:29.724312 F3: 1001 0000
308 22:53:29.724627
309 22:53:29.724942 F7: 102D 0000
310 22:53:29.725253
311 22:53:29.725586 F1: 0000 0000
312 22:53:29.726019
313 22:53:29.726340 V0: 0000 0000 [0001]
314 22:53:29.726655
315 22:53:29.726965 00: 0007 8000
316 22:53:29.727256
317 22:53:29.727534 01: 0000 0000
318 22:53:29.727864
319 22:53:29.728171 BP: 0C00 0209 [0000]
320 22:53:29.728481
321 22:53:29.728793 G0: 1182 0000
322 22:53:29.729091
323 22:53:29.729460 EC: 0000 0021 [4000]
324 22:53:29.729749
325 22:53:29.730028 S7: 0000 0000 [0000]
326 22:53:29.730306
327 22:53:29.730583 CC: 0000 0000 [0001]
328 22:53:29.730861
329 22:53:29.731141 T0: 0000 0040 [010F]
330 22:53:29.731423
331 22:53:29.731699 Jump to BL
332 22:53:29.731974
333 22:53:29.732251
334 22:53:29.732590
335 22:53:29.732899
336 22:53:29.733178 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
337 22:53:29.733511 ARM64: Exception handlers installed.
338 22:53:29.733794 ARM64: Testing exception
339 22:53:29.734073 ARM64: Done test exception
340 22:53:29.734355 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
341 22:53:29.734637 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
342 22:53:29.734919 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
343 22:53:29.735200 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
344 22:53:29.735488 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
345 22:53:29.735772 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
346 22:53:29.736158 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
347 22:53:29.736455 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
348 22:53:29.736737 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
349 22:53:29.737021 WDT: Last reset was cold boot
350 22:53:29.737319 SPI1(PAD0) initialized at 2873684 Hz
351 22:53:29.737603 SPI5(PAD0) initialized at 992727 Hz
352 22:53:29.737881 VBOOT: Loading verstage.
353 22:53:29.738157 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
354 22:53:29.738437 FMAP: Found "FLASH" version 1.1 at 0x20000.
355 22:53:29.738716 FMAP: base = 0x0 size = 0x800000 #areas = 25
356 22:53:29.738996 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
357 22:53:29.739371 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
358 22:53:29.739669 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
359 22:53:29.739951 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
360 22:53:29.740236
361 22:53:29.740510
362 22:53:29.740787 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
363 22:53:29.741071 ARM64: Exception handlers installed.
364 22:53:29.741390 ARM64: Testing exception
365 22:53:29.741680 ARM64: Done test exception
366 22:53:29.741956 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
367 22:53:29.742253 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
368 22:53:29.742615 Probing TPM: . done!
369 22:53:29.742918 TPM ready after 0 ms
370 22:53:29.743205 Connected to device vid:did:rid of 1ae0:0028:00
371 22:53:29.743487 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
372 22:53:29.743773 Initialized TPM device CR50 revision 0
373 22:53:29.744055 tlcl_send_startup: Startup return code is 0
374 22:53:29.744334 TPM: setup succeeded
375 22:53:29.744610 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
376 22:53:29.744844 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
377 22:53:29.745045 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
378 22:53:29.745314 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
379 22:53:29.745539 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
380 22:53:29.745744 in-header: 03 07 00 00 08 00 00 00
381 22:53:29.745943 in-data: aa e4 47 04 13 02 00 00
382 22:53:29.746143 Chrome EC: UHEPI supported
383 22:53:29.746343 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
384 22:53:29.746546 in-header: 03 a9 00 00 08 00 00 00
385 22:53:29.746745 in-data: 84 60 60 08 00 00 00 00
386 22:53:29.746943 Phase 1
387 22:53:29.747143 FMAP: area GBB found @ 3f5000 (12032 bytes)
388 22:53:29.747345 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
389 22:53:29.747546 VB2:vb2_check_recovery() Recovery was requested manually
390 22:53:29.747744 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
391 22:53:29.747944 Recovery requested (1009000e)
392 22:53:29.748141 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 22:53:29.748342 tlcl_extend: response is 0
394 22:53:29.748542 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 22:53:29.748743 tlcl_extend: response is 0
396 22:53:29.749025 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 22:53:29.749235 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 22:53:29.749465 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 22:53:29.749675
400 22:53:29.749825
401 22:53:29.749974 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 22:53:29.750125 ARM64: Exception handlers installed.
403 22:53:29.750275 ARM64: Testing exception
404 22:53:29.750425 ARM64: Done test exception
405 22:53:29.750573 pmic_efuse_setting: Set efuses in 11 msecs
406 22:53:29.750722 pmwrap_interface_init: Select PMIF_VLD_RDY
407 22:53:29.750873 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 22:53:29.751024 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 22:53:29.751422 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 22:53:29.751592 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 22:53:29.751746 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 22:53:29.751897 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 22:53:29.752091 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 22:53:29.752260 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 22:53:29.752411 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 22:53:29.752561 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 22:53:29.752712 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 22:53:29.752861 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 22:53:29.753012 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 22:53:29.753164 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 22:53:29.753339 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 22:53:29.753497 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 22:53:29.753646 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 22:53:29.753797 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 22:53:29.753948 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 22:53:29.754097 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 22:53:29.754251 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 22:53:29.754402 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 22:53:29.754552 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 22:53:29.754700 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 22:53:29.754820 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 22:53:29.754940 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 22:53:29.755061 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 22:53:29.755180 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 22:53:29.755299 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 22:53:29.755418 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 22:53:29.755550 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 22:53:29.755697 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 22:53:29.755820 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 22:53:29.755940 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 22:53:29.756059 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 22:53:29.756179 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 22:53:29.756299 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 22:53:29.756419 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 22:53:29.756538 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 22:53:29.756657 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 22:53:29.756776 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 22:53:29.756896 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 22:53:29.757014 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 22:53:29.757136 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 22:53:29.757255 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 22:53:29.757395 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 22:53:29.757516 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 22:53:29.757637 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 22:53:29.757757 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 22:53:29.757877 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 22:53:29.757996 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 22:53:29.758116 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
459 22:53:29.758239 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 22:53:29.758361 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 22:53:29.758480 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 22:53:29.758602 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 22:53:29.758723 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 22:53:29.758842 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 22:53:29.759007 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 22:53:29.759133 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
467 22:53:29.759254 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 22:53:29.759376 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 22:53:29.759498 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 22:53:29.759618 [RTC]rtc_get_frequency_meter,154: input=15, output=772
471 22:53:29.759733 [RTC]rtc_get_frequency_meter,154: input=23, output=957
472 22:53:29.759833 [RTC]rtc_get_frequency_meter,154: input=19, output=866
473 22:53:29.759933 [RTC]rtc_get_frequency_meter,154: input=17, output=817
474 22:53:29.760033 [RTC]rtc_get_frequency_meter,154: input=16, output=795
475 22:53:29.760133 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
476 22:53:29.760233 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
477 22:53:29.760333 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
478 22:53:29.760433 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
479 22:53:29.760755 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
480 22:53:29.760878 ADC[4]: Raw value=902876 ID=7
481 22:53:29.760982 ADC[3]: Raw value=213179 ID=1
482 22:53:29.761084 RAM Code: 0x71
483 22:53:29.761185 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
484 22:53:29.761288 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
485 22:53:29.761406 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
486 22:53:29.761510 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
487 22:53:29.761613 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
488 22:53:29.761714 in-header: 03 07 00 00 08 00 00 00
489 22:53:29.761838 in-data: aa e4 47 04 13 02 00 00
490 22:53:29.761948 Chrome EC: UHEPI supported
491 22:53:29.762049 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
492 22:53:29.762151 in-header: 03 a9 00 00 08 00 00 00
493 22:53:29.762252 in-data: 84 60 60 08 00 00 00 00
494 22:53:29.762352 MRC: failed to locate region type 0.
495 22:53:29.762454 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
496 22:53:29.762556 DRAM-K: Running full calibration
497 22:53:29.762657 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
498 22:53:29.762757 header.status = 0x0
499 22:53:29.762857 header.version = 0x6 (expected: 0x6)
500 22:53:29.762957 header.size = 0xd00 (expected: 0xd00)
501 22:53:29.763057 header.flags = 0x0
502 22:53:29.763157 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
503 22:53:29.763259 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
504 22:53:29.763361 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
505 22:53:29.763462 dram_init: ddr_geometry: 2
506 22:53:29.763562 [EMI] MDL number = 2
507 22:53:29.763663 [EMI] Get MDL freq = 0
508 22:53:29.763762 dram_init: ddr_type: 0
509 22:53:29.763861 is_discrete_lpddr4: 1
510 22:53:29.763961 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
511 22:53:29.764060
512 22:53:29.764159
513 22:53:29.764260 [Bian_co] ETT version 0.0.0.1
514 22:53:29.764361 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
515 22:53:29.764461
516 22:53:29.764560 dramc_set_vcore_voltage set vcore to 650000
517 22:53:29.764670 Read voltage for 800, 4
518 22:53:29.764756 Vio18 = 0
519 22:53:29.764841 Vcore = 650000
520 22:53:29.764927 Vdram = 0
521 22:53:29.765012 Vddq = 0
522 22:53:29.765097 Vmddr = 0
523 22:53:29.765181 dram_init: config_dvfs: 1
524 22:53:29.765268 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
525 22:53:29.765403 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
526 22:53:29.765495 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
527 22:53:29.765583 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
528 22:53:29.765674 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
529 22:53:29.765761 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
530 22:53:29.765848 MEM_TYPE=3, freq_sel=18
531 22:53:29.765935 sv_algorithm_assistance_LP4_1600
532 22:53:29.766021 ============ PULL DRAM RESETB DOWN ============
533 22:53:29.766111 ========== PULL DRAM RESETB DOWN end =========
534 22:53:29.766198 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
535 22:53:29.766285 ===================================
536 22:53:29.766371 LPDDR4 DRAM CONFIGURATION
537 22:53:29.766458 ===================================
538 22:53:29.766543 EX_ROW_EN[0] = 0x0
539 22:53:29.766629 EX_ROW_EN[1] = 0x0
540 22:53:29.766715 LP4Y_EN = 0x0
541 22:53:29.766801 WORK_FSP = 0x0
542 22:53:29.766886 WL = 0x2
543 22:53:29.766971 RL = 0x2
544 22:53:29.767057 BL = 0x2
545 22:53:29.767141 RPST = 0x0
546 22:53:29.767226 RD_PRE = 0x0
547 22:53:29.767312 WR_PRE = 0x1
548 22:53:29.767397 WR_PST = 0x0
549 22:53:29.767482 DBI_WR = 0x0
550 22:53:29.767567 DBI_RD = 0x0
551 22:53:29.767651 OTF = 0x1
552 22:53:29.767756 ===================================
553 22:53:29.767846 ===================================
554 22:53:29.767933 ANA top config
555 22:53:29.768019 ===================================
556 22:53:29.768105 DLL_ASYNC_EN = 0
557 22:53:29.768191 ALL_SLAVE_EN = 1
558 22:53:29.768276 NEW_RANK_MODE = 1
559 22:53:29.768362 DLL_IDLE_MODE = 1
560 22:53:29.768448 LP45_APHY_COMB_EN = 1
561 22:53:29.768534 TX_ODT_DIS = 1
562 22:53:29.768620 NEW_8X_MODE = 1
563 22:53:29.768706 ===================================
564 22:53:29.768811 ===================================
565 22:53:29.768905 data_rate = 1600
566 22:53:29.768991 CKR = 1
567 22:53:29.769077 DQ_P2S_RATIO = 8
568 22:53:29.769163 ===================================
569 22:53:29.769248 CA_P2S_RATIO = 8
570 22:53:29.769349 DQ_CA_OPEN = 0
571 22:53:29.769435 DQ_SEMI_OPEN = 0
572 22:53:29.769520 CA_SEMI_OPEN = 0
573 22:53:29.769605 CA_FULL_RATE = 0
574 22:53:29.769694 DQ_CKDIV4_EN = 1
575 22:53:29.769768 CA_CKDIV4_EN = 1
576 22:53:29.769843 CA_PREDIV_EN = 0
577 22:53:29.769918 PH8_DLY = 0
578 22:53:29.769992 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
579 22:53:29.770067 DQ_AAMCK_DIV = 4
580 22:53:29.770142 CA_AAMCK_DIV = 4
581 22:53:29.770217 CA_ADMCK_DIV = 4
582 22:53:29.770291 DQ_TRACK_CA_EN = 0
583 22:53:29.770366 CA_PICK = 800
584 22:53:29.770441 CA_MCKIO = 800
585 22:53:29.770515 MCKIO_SEMI = 0
586 22:53:29.770591 PLL_FREQ = 3068
587 22:53:29.770665 DQ_UI_PI_RATIO = 32
588 22:53:29.770740 CA_UI_PI_RATIO = 0
589 22:53:29.770814 ===================================
590 22:53:29.770890 ===================================
591 22:53:29.770965 memory_type:LPDDR4
592 22:53:29.771040 GP_NUM : 10
593 22:53:29.771114 SRAM_EN : 1
594 22:53:29.771189 MD32_EN : 0
595 22:53:29.771263 ===================================
596 22:53:29.771339 [ANA_INIT] >>>>>>>>>>>>>>
597 22:53:29.771414 <<<<<< [CONFIGURE PHASE]: ANA_TX
598 22:53:29.771495 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
599 22:53:29.771570 ===================================
600 22:53:29.771863 data_rate = 1600,PCW = 0X7600
601 22:53:29.771947 ===================================
602 22:53:29.772056 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
603 22:53:29.772137 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
604 22:53:29.772215 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
605 22:53:29.772292 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
606 22:53:29.772369 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
607 22:53:29.772445 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
608 22:53:29.772521 [ANA_INIT] flow start
609 22:53:29.772597 [ANA_INIT] PLL >>>>>>>>
610 22:53:29.772672 [ANA_INIT] PLL <<<<<<<<
611 22:53:29.772747 [ANA_INIT] MIDPI >>>>>>>>
612 22:53:29.772822 [ANA_INIT] MIDPI <<<<<<<<
613 22:53:29.772897 [ANA_INIT] DLL >>>>>>>>
614 22:53:29.772971 [ANA_INIT] flow end
615 22:53:29.773047 ============ LP4 DIFF to SE enter ============
616 22:53:29.773123 ============ LP4 DIFF to SE exit ============
617 22:53:29.773200 [ANA_INIT] <<<<<<<<<<<<<
618 22:53:29.773275 [Flow] Enable top DCM control >>>>>
619 22:53:29.773365 [Flow] Enable top DCM control <<<<<
620 22:53:29.773441 Enable DLL master slave shuffle
621 22:53:29.773516 ==============================================================
622 22:53:29.773592 Gating Mode config
623 22:53:29.773667 ==============================================================
624 22:53:29.773743 Config description:
625 22:53:29.773819 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
626 22:53:29.773895 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
627 22:53:29.773973 SELPH_MODE 0: By rank 1: By Phase
628 22:53:29.774049 ==============================================================
629 22:53:29.774125 GAT_TRACK_EN = 1
630 22:53:29.774201 RX_GATING_MODE = 2
631 22:53:29.774277 RX_GATING_TRACK_MODE = 2
632 22:53:29.774353 SELPH_MODE = 1
633 22:53:29.774428 PICG_EARLY_EN = 1
634 22:53:29.774503 VALID_LAT_VALUE = 1
635 22:53:29.774579 ==============================================================
636 22:53:29.774664 Enter into Gating configuration >>>>
637 22:53:29.774742 Exit from Gating configuration <<<<
638 22:53:29.774813 Enter into DVFS_PRE_config >>>>>
639 22:53:29.774881 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
640 22:53:29.774953 Exit from DVFS_PRE_config <<<<<
641 22:53:29.775020 Enter into PICG configuration >>>>
642 22:53:29.775087 Exit from PICG configuration <<<<
643 22:53:29.775155 [RX_INPUT] configuration >>>>>
644 22:53:29.775223 [RX_INPUT] configuration <<<<<
645 22:53:29.775290 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
646 22:53:29.775358 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
647 22:53:29.775426 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
648 22:53:29.775518 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
649 22:53:29.775588 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
650 22:53:29.775656 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
651 22:53:29.775724 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
652 22:53:29.775791 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
653 22:53:29.775859 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
654 22:53:29.775927 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
655 22:53:29.775995 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
656 22:53:29.776062 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
657 22:53:29.776130 ===================================
658 22:53:29.776199 LPDDR4 DRAM CONFIGURATION
659 22:53:29.776266 ===================================
660 22:53:29.776334 EX_ROW_EN[0] = 0x0
661 22:53:29.776402 EX_ROW_EN[1] = 0x0
662 22:53:29.776468 LP4Y_EN = 0x0
663 22:53:29.776535 WORK_FSP = 0x0
664 22:53:29.776602 WL = 0x2
665 22:53:29.776669 RL = 0x2
666 22:53:29.776736 BL = 0x2
667 22:53:29.776802 RPST = 0x0
668 22:53:29.776869 RD_PRE = 0x0
669 22:53:29.776936 WR_PRE = 0x1
670 22:53:29.777004 WR_PST = 0x0
671 22:53:29.777070 DBI_WR = 0x0
672 22:53:29.777137 DBI_RD = 0x0
673 22:53:29.777204 OTF = 0x1
674 22:53:29.777273 ===================================
675 22:53:29.777352 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
676 22:53:29.777421 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
677 22:53:29.777489 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
678 22:53:29.777557 ===================================
679 22:53:29.777623 LPDDR4 DRAM CONFIGURATION
680 22:53:29.777690 ===================================
681 22:53:29.777758 EX_ROW_EN[0] = 0x10
682 22:53:29.777825 EX_ROW_EN[1] = 0x0
683 22:53:29.777892 LP4Y_EN = 0x0
684 22:53:29.777959 WORK_FSP = 0x0
685 22:53:29.778025 WL = 0x2
686 22:53:29.778091 RL = 0x2
687 22:53:29.778158 BL = 0x2
688 22:53:29.778225 RPST = 0x0
689 22:53:29.778291 RD_PRE = 0x0
690 22:53:29.778358 WR_PRE = 0x1
691 22:53:29.778425 WR_PST = 0x0
692 22:53:29.778492 DBI_WR = 0x0
693 22:53:29.778558 DBI_RD = 0x0
694 22:53:29.778625 OTF = 0x1
695 22:53:29.778692 ===================================
696 22:53:29.778759 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
697 22:53:29.778843 nWR fixed to 40
698 22:53:29.778917 [ModeRegInit_LP4] CH0 RK0
699 22:53:29.778985 [ModeRegInit_LP4] CH0 RK1
700 22:53:29.779052 [ModeRegInit_LP4] CH1 RK0
701 22:53:29.779119 [ModeRegInit_LP4] CH1 RK1
702 22:53:29.779185 match AC timing 13
703 22:53:29.779251 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
704 22:53:29.779320 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
705 22:53:29.779388 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
706 22:53:29.779454 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
707 22:53:29.779729 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
708 22:53:29.779800 [EMI DOE] emi_dcm 0
709 22:53:29.779863 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
710 22:53:29.779925 ==
711 22:53:29.779986 Dram Type= 6, Freq= 0, CH_0, rank 0
712 22:53:29.780048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
713 22:53:29.780109 ==
714 22:53:29.780171 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
715 22:53:29.780233 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
716 22:53:29.780295 [CA 0] Center 37 (7~68) winsize 62
717 22:53:29.780355 [CA 1] Center 38 (7~69) winsize 63
718 22:53:29.780416 [CA 2] Center 35 (5~66) winsize 62
719 22:53:29.780476 [CA 3] Center 35 (5~66) winsize 62
720 22:53:29.780537 [CA 4] Center 34 (4~65) winsize 62
721 22:53:29.780596 [CA 5] Center 34 (3~65) winsize 63
722 22:53:29.780657
723 22:53:29.780717 [CmdBusTrainingLP45] Vref(ca) range 1: 34
724 22:53:29.780778
725 22:53:29.780837 [CATrainingPosCal] consider 1 rank data
726 22:53:29.780898 u2DelayCellTimex100 = 270/100 ps
727 22:53:29.780958 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
728 22:53:29.781018 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
729 22:53:29.781078 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
730 22:53:29.781138 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
731 22:53:29.781198 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
732 22:53:29.781259 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
733 22:53:29.781328
734 22:53:29.781390 CA PerBit enable=1, Macro0, CA PI delay=34
735 22:53:29.781450
736 22:53:29.781510 [CBTSetCACLKResult] CA Dly = 34
737 22:53:29.781571 CS Dly: 5 (0~36)
738 22:53:29.781631 ==
739 22:53:29.781691 Dram Type= 6, Freq= 0, CH_0, rank 1
740 22:53:29.781752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
741 22:53:29.781813 ==
742 22:53:29.781873 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
743 22:53:29.781934 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
744 22:53:29.782018 [CA 0] Center 38 (7~69) winsize 63
745 22:53:29.782081 [CA 1] Center 38 (8~69) winsize 62
746 22:53:29.782142 [CA 2] Center 36 (6~67) winsize 62
747 22:53:29.782203 [CA 3] Center 36 (5~67) winsize 63
748 22:53:29.782264 [CA 4] Center 35 (4~66) winsize 63
749 22:53:29.782324 [CA 5] Center 34 (4~65) winsize 62
750 22:53:29.782385
751 22:53:29.782445 [CmdBusTrainingLP45] Vref(ca) range 1: 34
752 22:53:29.782506
753 22:53:29.782566 [CATrainingPosCal] consider 2 rank data
754 22:53:29.782627 u2DelayCellTimex100 = 270/100 ps
755 22:53:29.782688 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
756 22:53:29.782748 CA1 delay=38 (8~69),Diff = 4 PI (28 cell)
757 22:53:29.782809 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
758 22:53:29.782870 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
759 22:53:29.782932 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
760 22:53:29.782992 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
761 22:53:29.783053
762 22:53:29.783113 CA PerBit enable=1, Macro0, CA PI delay=34
763 22:53:29.783174
764 22:53:29.783235 [CBTSetCACLKResult] CA Dly = 34
765 22:53:29.783296 CS Dly: 6 (0~38)
766 22:53:29.783356
767 22:53:29.783416 ----->DramcWriteLeveling(PI) begin...
768 22:53:29.783477 ==
769 22:53:29.783539 Dram Type= 6, Freq= 0, CH_0, rank 0
770 22:53:29.783600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
771 22:53:29.783661 ==
772 22:53:29.783722 Write leveling (Byte 0): 32 => 32
773 22:53:29.783783 Write leveling (Byte 1): 32 => 32
774 22:53:29.783844 DramcWriteLeveling(PI) end<-----
775 22:53:29.783905
776 22:53:29.783964 ==
777 22:53:29.784025 Dram Type= 6, Freq= 0, CH_0, rank 0
778 22:53:29.784085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
779 22:53:29.784146 ==
780 22:53:29.784207 [Gating] SW mode calibration
781 22:53:29.784268 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
782 22:53:29.784330 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
783 22:53:29.784391 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
784 22:53:29.784453 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
785 22:53:29.784514 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
786 22:53:29.784575 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 22:53:29.784648 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 22:53:29.784704 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 22:53:29.784759 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 22:53:29.784815 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 22:53:29.784870 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 22:53:29.784925 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 22:53:29.784979 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 22:53:29.785034 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 22:53:29.785089 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 22:53:29.785144 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 22:53:29.785203 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 22:53:29.785304 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 22:53:29.785365 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 22:53:29.785421 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
801 22:53:29.785477 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
802 22:53:29.785532 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 22:53:29.785587 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 22:53:29.785643 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 22:53:29.785699 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 22:53:29.785754 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 22:53:29.785810 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 22:53:29.785865 0 9 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
809 22:53:29.785920 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
810 22:53:29.785976 0 9 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
811 22:53:29.786031 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 22:53:29.786086 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 22:53:29.786142 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 22:53:29.786197 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 22:53:29.786447 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 22:53:29.786512 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
817 22:53:29.786570 0 10 8 | B1->B0 | 3030 2323 | 0 0 | (0 1) (1 0)
818 22:53:29.786627 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 22:53:29.786722 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 22:53:29.786803 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 22:53:29.786862 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 22:53:29.786918 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 22:53:29.786974 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 22:53:29.787031 0 11 4 | B1->B0 | 2323 3535 | 0 0 | (0 0) (1 1)
825 22:53:29.787086 0 11 8 | B1->B0 | 2a2a 4545 | 0 0 | (0 0) (0 0)
826 22:53:29.787141 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
827 22:53:29.787200 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 22:53:29.787255 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 22:53:29.787311 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 22:53:29.787365 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 22:53:29.787420 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 22:53:29.787475 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
833 22:53:29.787530 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
834 22:53:29.787585 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 22:53:29.787640 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 22:53:29.787695 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 22:53:29.787750 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 22:53:29.787805 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 22:53:29.787860 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 22:53:29.787915 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 22:53:29.787970 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 22:53:29.788024 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 22:53:29.788079 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 22:53:29.788133 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 22:53:29.788188 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 22:53:29.788243 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 22:53:29.788299 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 22:53:29.788354 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
849 22:53:29.788410 Total UI for P1: 0, mck2ui 16
850 22:53:29.788479 best dqsien dly found for B0: ( 0, 14, 2)
851 22:53:29.788540 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 22:53:29.788596 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
853 22:53:29.788651 Total UI for P1: 0, mck2ui 16
854 22:53:29.788708 best dqsien dly found for B1: ( 0, 14, 10)
855 22:53:29.788764 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
856 22:53:29.788819 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
857 22:53:29.788875
858 22:53:29.788930 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
859 22:53:29.788985 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
860 22:53:29.789040 [Gating] SW calibration Done
861 22:53:29.789095 ==
862 22:53:29.789150 Dram Type= 6, Freq= 0, CH_0, rank 0
863 22:53:29.789206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
864 22:53:29.789262 ==
865 22:53:29.789328 RX Vref Scan: 0
866 22:53:29.789384
867 22:53:29.789440 RX Vref 0 -> 0, step: 1
868 22:53:29.789495
869 22:53:29.789549 RX Delay -130 -> 252, step: 16
870 22:53:29.789604 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
871 22:53:29.789671 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
872 22:53:29.789724 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
873 22:53:29.789777 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
874 22:53:29.789859 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
875 22:53:29.789944 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
876 22:53:29.789996 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
877 22:53:29.790050 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
878 22:53:29.790102 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
879 22:53:29.790154 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
880 22:53:29.790208 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
881 22:53:29.790260 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
882 22:53:29.790313 iDelay=222, Bit 12, Center 85 (-18 ~ 189) 208
883 22:53:29.790366 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
884 22:53:29.790435 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
885 22:53:29.790517 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
886 22:53:29.790571 ==
887 22:53:29.790624 Dram Type= 6, Freq= 0, CH_0, rank 0
888 22:53:29.790678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
889 22:53:29.790732 ==
890 22:53:29.790786 DQS Delay:
891 22:53:29.790839 DQS0 = 0, DQS1 = 0
892 22:53:29.790905 DQM Delay:
893 22:53:29.790958 DQM0 = 93, DQM1 = 81
894 22:53:29.791011 DQ Delay:
895 22:53:29.791063 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
896 22:53:29.791116 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
897 22:53:29.791169 DQ8 =77, DQ9 =61, DQ10 =85, DQ11 =77
898 22:53:29.791222 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
899 22:53:29.791273
900 22:53:29.791326
901 22:53:29.791378 ==
902 22:53:29.791431 Dram Type= 6, Freq= 0, CH_0, rank 0
903 22:53:29.791483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
904 22:53:29.791537 ==
905 22:53:29.791589
906 22:53:29.791642
907 22:53:29.791694 TX Vref Scan disable
908 22:53:29.791747 == TX Byte 0 ==
909 22:53:29.791815 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
910 22:53:29.791869 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
911 22:53:29.791922 == TX Byte 1 ==
912 22:53:29.791995 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
913 22:53:29.792065 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
914 22:53:29.792119 ==
915 22:53:29.792173 Dram Type= 6, Freq= 0, CH_0, rank 0
916 22:53:29.792227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
917 22:53:29.792281 ==
918 22:53:29.792333 TX Vref=22, minBit 7, minWin=27, winSum=440
919 22:53:29.792387 TX Vref=24, minBit 8, minWin=27, winSum=448
920 22:53:29.792441 TX Vref=26, minBit 8, minWin=27, winSum=450
921 22:53:29.792494 TX Vref=28, minBit 6, minWin=28, winSum=458
922 22:53:29.792547 TX Vref=30, minBit 5, minWin=28, winSum=457
923 22:53:29.792806 TX Vref=32, minBit 8, minWin=27, winSum=453
924 22:53:29.792868 [TxChooseVref] Worse bit 6, Min win 28, Win sum 458, Final Vref 28
925 22:53:29.792924
926 22:53:29.792978 Final TX Range 1 Vref 28
927 22:53:29.793033
928 22:53:29.793087 ==
929 22:53:29.793141 Dram Type= 6, Freq= 0, CH_0, rank 0
930 22:53:29.793195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
931 22:53:29.793250 ==
932 22:53:29.793328
933 22:53:29.793410
934 22:53:29.793463 TX Vref Scan disable
935 22:53:29.793516 == TX Byte 0 ==
936 22:53:29.793569 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
937 22:53:29.793638 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
938 22:53:29.793693 == TX Byte 1 ==
939 22:53:29.793758 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
940 22:53:29.793812 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
941 22:53:29.793864
942 22:53:29.793917 [DATLAT]
943 22:53:29.793974 Freq=800, CH0 RK0
944 22:53:29.794028
945 22:53:29.794080 DATLAT Default: 0xa
946 22:53:29.794133 0, 0xFFFF, sum = 0
947 22:53:29.794187 1, 0xFFFF, sum = 0
948 22:53:29.794241 2, 0xFFFF, sum = 0
949 22:53:29.794294 3, 0xFFFF, sum = 0
950 22:53:29.794350 4, 0xFFFF, sum = 0
951 22:53:29.794404 5, 0xFFFF, sum = 0
952 22:53:29.794457 6, 0xFFFF, sum = 0
953 22:53:29.794511 7, 0xFFFF, sum = 0
954 22:53:29.794565 8, 0xFFFF, sum = 0
955 22:53:29.794619 9, 0x0, sum = 1
956 22:53:29.794674 10, 0x0, sum = 2
957 22:53:29.794728 11, 0x0, sum = 3
958 22:53:29.794782 12, 0x0, sum = 4
959 22:53:29.794835 best_step = 10
960 22:53:29.794888
961 22:53:29.794940 ==
962 22:53:29.794993 Dram Type= 6, Freq= 0, CH_0, rank 0
963 22:53:29.795047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
964 22:53:29.795100 ==
965 22:53:29.795153 RX Vref Scan: 1
966 22:53:29.795205
967 22:53:29.795258 Set Vref Range= 32 -> 127
968 22:53:29.795310
969 22:53:29.795362 RX Vref 32 -> 127, step: 1
970 22:53:29.795415
971 22:53:29.795467 RX Delay -95 -> 252, step: 8
972 22:53:29.795519
973 22:53:29.795572 Set Vref, RX VrefLevel [Byte0]: 32
974 22:53:29.795625 [Byte1]: 32
975 22:53:29.795724
976 22:53:29.795780 Set Vref, RX VrefLevel [Byte0]: 33
977 22:53:29.795833 [Byte1]: 33
978 22:53:29.795886
979 22:53:29.795939 Set Vref, RX VrefLevel [Byte0]: 34
980 22:53:29.795992 [Byte1]: 34
981 22:53:29.796045
982 22:53:29.796098 Set Vref, RX VrefLevel [Byte0]: 35
983 22:53:29.796152 [Byte1]: 35
984 22:53:29.796205
985 22:53:29.796257 Set Vref, RX VrefLevel [Byte0]: 36
986 22:53:29.796310 [Byte1]: 36
987 22:53:29.796364
988 22:53:29.796416 Set Vref, RX VrefLevel [Byte0]: 37
989 22:53:29.796469 [Byte1]: 37
990 22:53:29.796522
991 22:53:29.796575 Set Vref, RX VrefLevel [Byte0]: 38
992 22:53:29.796632 [Byte1]: 38
993 22:53:29.796685
994 22:53:29.796738 Set Vref, RX VrefLevel [Byte0]: 39
995 22:53:29.796791 [Byte1]: 39
996 22:53:29.796843
997 22:53:29.796895 Set Vref, RX VrefLevel [Byte0]: 40
998 22:53:29.796964 [Byte1]: 40
999 22:53:29.797030
1000 22:53:29.797097 Set Vref, RX VrefLevel [Byte0]: 41
1001 22:53:29.797151 [Byte1]: 41
1002 22:53:29.797205
1003 22:53:29.797258 Set Vref, RX VrefLevel [Byte0]: 42
1004 22:53:29.797335 [Byte1]: 42
1005 22:53:29.797416
1006 22:53:29.797469 Set Vref, RX VrefLevel [Byte0]: 43
1007 22:53:29.797521 [Byte1]: 43
1008 22:53:29.797573
1009 22:53:29.797626 Set Vref, RX VrefLevel [Byte0]: 44
1010 22:53:29.797679 [Byte1]: 44
1011 22:53:29.797731
1012 22:53:29.797783 Set Vref, RX VrefLevel [Byte0]: 45
1013 22:53:29.797836 [Byte1]: 45
1014 22:53:29.797888
1015 22:53:29.797940 Set Vref, RX VrefLevel [Byte0]: 46
1016 22:53:29.797993 [Byte1]: 46
1017 22:53:29.798047
1018 22:53:29.798100 Set Vref, RX VrefLevel [Byte0]: 47
1019 22:53:29.798154 [Byte1]: 47
1020 22:53:29.798207
1021 22:53:29.798260 Set Vref, RX VrefLevel [Byte0]: 48
1022 22:53:29.798313 [Byte1]: 48
1023 22:53:29.798366
1024 22:53:29.798419 Set Vref, RX VrefLevel [Byte0]: 49
1025 22:53:29.798478 [Byte1]: 49
1026 22:53:29.798534
1027 22:53:29.798590 Set Vref, RX VrefLevel [Byte0]: 50
1028 22:53:29.798673 [Byte1]: 50
1029 22:53:29.798726
1030 22:53:29.798824 Set Vref, RX VrefLevel [Byte0]: 51
1031 22:53:29.798880 [Byte1]: 51
1032 22:53:29.798934
1033 22:53:29.798987 Set Vref, RX VrefLevel [Byte0]: 52
1034 22:53:29.799040 [Byte1]: 52
1035 22:53:29.799093
1036 22:53:29.799145 Set Vref, RX VrefLevel [Byte0]: 53
1037 22:53:29.799197 [Byte1]: 53
1038 22:53:29.799250
1039 22:53:29.799301 Set Vref, RX VrefLevel [Byte0]: 54
1040 22:53:29.799354 [Byte1]: 54
1041 22:53:29.799405
1042 22:53:29.799457 Set Vref, RX VrefLevel [Byte0]: 55
1043 22:53:29.799509 [Byte1]: 55
1044 22:53:29.799561
1045 22:53:29.799612 Set Vref, RX VrefLevel [Byte0]: 56
1046 22:53:29.799664 [Byte1]: 56
1047 22:53:29.799716
1048 22:53:29.799768 Set Vref, RX VrefLevel [Byte0]: 57
1049 22:53:29.799820 [Byte1]: 57
1050 22:53:29.799872
1051 22:53:29.799924 Set Vref, RX VrefLevel [Byte0]: 58
1052 22:53:29.799976 [Byte1]: 58
1053 22:53:29.800029
1054 22:53:29.800080 Set Vref, RX VrefLevel [Byte0]: 59
1055 22:53:29.800132 [Byte1]: 59
1056 22:53:29.800184
1057 22:53:29.800236 Set Vref, RX VrefLevel [Byte0]: 60
1058 22:53:29.800346 [Byte1]: 60
1059 22:53:29.800454
1060 22:53:29.800507 Set Vref, RX VrefLevel [Byte0]: 61
1061 22:53:29.800559 [Byte1]: 61
1062 22:53:29.800625
1063 22:53:29.800678 Set Vref, RX VrefLevel [Byte0]: 62
1064 22:53:29.800744 [Byte1]: 62
1065 22:53:29.800796
1066 22:53:29.800848 Set Vref, RX VrefLevel [Byte0]: 63
1067 22:53:29.800899 [Byte1]: 63
1068 22:53:29.800951
1069 22:53:29.801003 Set Vref, RX VrefLevel [Byte0]: 64
1070 22:53:29.801056 [Byte1]: 64
1071 22:53:29.801108
1072 22:53:29.801160 Set Vref, RX VrefLevel [Byte0]: 65
1073 22:53:29.801213 [Byte1]: 65
1074 22:53:29.801265
1075 22:53:29.801348 Set Vref, RX VrefLevel [Byte0]: 66
1076 22:53:29.801428 [Byte1]: 66
1077 22:53:29.801480
1078 22:53:29.801532 Set Vref, RX VrefLevel [Byte0]: 67
1079 22:53:29.801584 [Byte1]: 67
1080 22:53:29.801636
1081 22:53:29.801688 Set Vref, RX VrefLevel [Byte0]: 68
1082 22:53:29.801740 [Byte1]: 68
1083 22:53:29.801792
1084 22:53:29.801844 Set Vref, RX VrefLevel [Byte0]: 69
1085 22:53:29.801896 [Byte1]: 69
1086 22:53:29.801949
1087 22:53:29.802001 Set Vref, RX VrefLevel [Byte0]: 70
1088 22:53:29.802054 [Byte1]: 70
1089 22:53:29.802106
1090 22:53:29.802158 Set Vref, RX VrefLevel [Byte0]: 71
1091 22:53:29.802211 [Byte1]: 71
1092 22:53:29.802310
1093 22:53:29.802366 Set Vref, RX VrefLevel [Byte0]: 72
1094 22:53:29.802611 [Byte1]: 72
1095 22:53:29.802723
1096 22:53:29.802778 Set Vref, RX VrefLevel [Byte0]: 73
1097 22:53:29.802833 [Byte1]: 73
1098 22:53:29.802886
1099 22:53:29.802939 Set Vref, RX VrefLevel [Byte0]: 74
1100 22:53:29.802993 [Byte1]: 74
1101 22:53:29.803046
1102 22:53:29.803099 Set Vref, RX VrefLevel [Byte0]: 75
1103 22:53:29.803165 [Byte1]: 75
1104 22:53:29.803217
1105 22:53:29.803269 Set Vref, RX VrefLevel [Byte0]: 76
1106 22:53:29.803322 [Byte1]: 76
1107 22:53:29.803375
1108 22:53:29.803442 Set Vref, RX VrefLevel [Byte0]: 77
1109 22:53:29.803495 [Byte1]: 77
1110 22:53:29.803548
1111 22:53:29.803629 Set Vref, RX VrefLevel [Byte0]: 78
1112 22:53:29.803696 [Byte1]: 78
1113 22:53:29.803772
1114 22:53:29.803839 Set Vref, RX VrefLevel [Byte0]: 79
1115 22:53:29.803890 [Byte1]: 79
1116 22:53:29.803941
1117 22:53:29.803992 Set Vref, RX VrefLevel [Byte0]: 80
1118 22:53:29.804043 [Byte1]: 80
1119 22:53:29.804095
1120 22:53:29.804147 Final RX Vref Byte 0 = 62 to rank0
1121 22:53:29.804200 Final RX Vref Byte 1 = 57 to rank0
1122 22:53:29.804252 Final RX Vref Byte 0 = 62 to rank1
1123 22:53:29.804304 Final RX Vref Byte 1 = 57 to rank1==
1124 22:53:29.804357 Dram Type= 6, Freq= 0, CH_0, rank 0
1125 22:53:29.804409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1126 22:53:29.804462 ==
1127 22:53:29.804515 DQS Delay:
1128 22:53:29.804567 DQS0 = 0, DQS1 = 0
1129 22:53:29.804619 DQM Delay:
1130 22:53:29.804671 DQM0 = 93, DQM1 = 83
1131 22:53:29.804723 DQ Delay:
1132 22:53:29.804776 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1133 22:53:29.804828 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1134 22:53:29.804880 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =80
1135 22:53:29.804932 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =92
1136 22:53:29.804984
1137 22:53:29.805036
1138 22:53:29.805089 [DQSOSCAuto] RK0, (LSB)MR18= 0x3d38, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
1139 22:53:29.805142 CH0 RK0: MR19=606, MR18=3D38
1140 22:53:29.805227 CH0_RK0: MR19=0x606, MR18=0x3D38, DQSOSC=394, MR23=63, INC=95, DEC=63
1141 22:53:29.805351
1142 22:53:29.805421 ----->DramcWriteLeveling(PI) begin...
1143 22:53:29.805476 ==
1144 22:53:29.805530 Dram Type= 6, Freq= 0, CH_0, rank 1
1145 22:53:29.805582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1146 22:53:29.805636 ==
1147 22:53:29.805688 Write leveling (Byte 0): 31 => 31
1148 22:53:29.805741 Write leveling (Byte 1): 29 => 29
1149 22:53:29.805794 DramcWriteLeveling(PI) end<-----
1150 22:53:29.805847
1151 22:53:29.805898 ==
1152 22:53:29.805951 Dram Type= 6, Freq= 0, CH_0, rank 1
1153 22:53:29.806003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1154 22:53:29.806056 ==
1155 22:53:29.806109 [Gating] SW mode calibration
1156 22:53:29.806162 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1157 22:53:29.806215 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1158 22:53:29.806269 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1159 22:53:29.806321 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1160 22:53:29.806374 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1161 22:53:29.806426 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 22:53:29.806479 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 22:53:29.806531 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 22:53:29.806584 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 22:53:29.806636 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 22:53:29.806689 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 22:53:29.806741 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 22:53:29.806794 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 22:53:29.806846 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 22:53:29.806915 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 22:53:29.806996 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 22:53:29.807091 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 22:53:29.807159 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 22:53:29.807239 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 22:53:29.807291 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1176 22:53:29.807374 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 22:53:29.807440 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 22:53:29.807492 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 22:53:29.807545 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 22:53:29.807597 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 22:53:29.807650 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 22:53:29.807703 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 22:53:29.807756 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1184 22:53:29.807808 0 9 8 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (0 0)
1185 22:53:29.807861 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 22:53:29.807913 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 22:53:29.807965 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1188 22:53:29.808017 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1189 22:53:29.808070 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1190 22:53:29.808122 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1191 22:53:29.808174 0 10 4 | B1->B0 | 3333 3030 | 1 0 | (1 0) (0 0)
1192 22:53:29.808227 0 10 8 | B1->B0 | 2e2e 2323 | 0 0 | (1 1) (0 0)
1193 22:53:29.808279 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 22:53:29.808332 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 22:53:29.808385 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 22:53:29.808437 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 22:53:29.808490 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 22:53:29.808543 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 22:53:29.808596 0 11 4 | B1->B0 | 2525 3130 | 1 1 | (0 0) (0 0)
1200 22:53:29.808685 0 11 8 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
1201 22:53:29.808746 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 22:53:29.808800 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 22:53:29.809057 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 22:53:29.809145 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1205 22:53:29.809230 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1206 22:53:29.809339 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1207 22:53:29.809411 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1208 22:53:29.809467 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1209 22:53:29.809521 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 22:53:29.809587 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 22:53:29.809640 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 22:53:29.809694 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 22:53:29.809747 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 22:53:29.809799 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 22:53:29.809852 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 22:53:29.809905 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 22:53:29.809957 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 22:53:29.810010 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 22:53:29.810090 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 22:53:29.810157 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 22:53:29.810211 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 22:53:29.810268 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 22:53:29.810322 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1224 22:53:29.810438 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1225 22:53:29.810493 Total UI for P1: 0, mck2ui 16
1226 22:53:29.810547 best dqsien dly found for B0: ( 0, 14, 4)
1227 22:53:29.810600 Total UI for P1: 0, mck2ui 16
1228 22:53:29.810653 best dqsien dly found for B1: ( 0, 14, 6)
1229 22:53:29.810707 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1230 22:53:29.810759 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1231 22:53:29.810812
1232 22:53:29.810864 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1233 22:53:29.810916 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1234 22:53:29.810968 [Gating] SW calibration Done
1235 22:53:29.811020 ==
1236 22:53:29.811073 Dram Type= 6, Freq= 0, CH_0, rank 1
1237 22:53:29.811125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1238 22:53:29.811179 ==
1239 22:53:29.811231 RX Vref Scan: 0
1240 22:53:29.811283
1241 22:53:29.811335 RX Vref 0 -> 0, step: 1
1242 22:53:29.811388
1243 22:53:29.811439 RX Delay -130 -> 252, step: 16
1244 22:53:29.811492 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1245 22:53:29.811544 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1246 22:53:29.811597 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
1247 22:53:29.811650 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1248 22:53:29.811702 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1249 22:53:29.811755 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1250 22:53:29.811807 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1251 22:53:29.811860 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1252 22:53:29.811912 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
1253 22:53:29.811965 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1254 22:53:29.812017 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1255 22:53:29.812070 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1256 22:53:29.812122 iDelay=206, Bit 12, Center 77 (-34 ~ 189) 224
1257 22:53:29.812190 iDelay=206, Bit 13, Center 77 (-34 ~ 189) 224
1258 22:53:29.812264 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1259 22:53:29.812333 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1260 22:53:29.812385 ==
1261 22:53:29.812438 Dram Type= 6, Freq= 0, CH_0, rank 1
1262 22:53:29.812491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1263 22:53:29.812544 ==
1264 22:53:29.812597 DQS Delay:
1265 22:53:29.812649 DQS0 = 0, DQS1 = 0
1266 22:53:29.812701 DQM Delay:
1267 22:53:29.812753 DQM0 = 87, DQM1 = 77
1268 22:53:29.812805 DQ Delay:
1269 22:53:29.812857 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =77
1270 22:53:29.812910 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1271 22:53:29.812963 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
1272 22:53:29.813015 DQ12 =77, DQ13 =77, DQ14 =85, DQ15 =85
1273 22:53:29.813067
1274 22:53:29.813119
1275 22:53:29.813171 ==
1276 22:53:29.813223 Dram Type= 6, Freq= 0, CH_0, rank 1
1277 22:53:29.813275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1278 22:53:29.813381 ==
1279 22:53:29.813463
1280 22:53:29.813515
1281 22:53:29.813597 TX Vref Scan disable
1282 22:53:29.813650 == TX Byte 0 ==
1283 22:53:29.813702 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1284 22:53:29.813755 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1285 22:53:29.813808 == TX Byte 1 ==
1286 22:53:29.813861 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1287 22:53:29.813913 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1288 22:53:29.813966 ==
1289 22:53:29.814019 Dram Type= 6, Freq= 0, CH_0, rank 1
1290 22:53:29.814072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1291 22:53:29.814125 ==
1292 22:53:29.814177 TX Vref=22, minBit 8, minWin=27, winSum=448
1293 22:53:29.814231 TX Vref=24, minBit 8, minWin=27, winSum=451
1294 22:53:29.814282 TX Vref=26, minBit 8, minWin=27, winSum=451
1295 22:53:29.814334 TX Vref=28, minBit 8, minWin=27, winSum=453
1296 22:53:29.814385 TX Vref=30, minBit 8, minWin=28, winSum=456
1297 22:53:29.814436 TX Vref=32, minBit 8, minWin=28, winSum=456
1298 22:53:29.814487 [TxChooseVref] Worse bit 8, Min win 28, Win sum 456, Final Vref 30
1299 22:53:29.814538
1300 22:53:29.814589 Final TX Range 1 Vref 30
1301 22:53:29.814640
1302 22:53:29.814690 ==
1303 22:53:29.814741 Dram Type= 6, Freq= 0, CH_0, rank 1
1304 22:53:29.814792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1305 22:53:29.814843 ==
1306 22:53:29.814894
1307 22:53:29.814944
1308 22:53:29.814994 TX Vref Scan disable
1309 22:53:29.815045 == TX Byte 0 ==
1310 22:53:29.815096 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1311 22:53:29.815147 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1312 22:53:29.815199 == TX Byte 1 ==
1313 22:53:29.815250 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1314 22:53:29.815301 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1315 22:53:29.815352
1316 22:53:29.815403 [DATLAT]
1317 22:53:29.815454 Freq=800, CH0 RK1
1318 22:53:29.815505
1319 22:53:29.815556 DATLAT Default: 0xa
1320 22:53:29.815607 0, 0xFFFF, sum = 0
1321 22:53:29.815679 1, 0xFFFF, sum = 0
1322 22:53:29.815732 2, 0xFFFF, sum = 0
1323 22:53:29.815785 3, 0xFFFF, sum = 0
1324 22:53:29.815837 4, 0xFFFF, sum = 0
1325 22:53:29.815889 5, 0xFFFF, sum = 0
1326 22:53:29.815941 6, 0xFFFF, sum = 0
1327 22:53:29.815992 7, 0xFFFF, sum = 0
1328 22:53:29.816234 8, 0xFFFF, sum = 0
1329 22:53:29.816345 9, 0x0, sum = 1
1330 22:53:29.816400 10, 0x0, sum = 2
1331 22:53:29.816453 11, 0x0, sum = 3
1332 22:53:29.816507 12, 0x0, sum = 4
1333 22:53:29.816560 best_step = 10
1334 22:53:29.816612
1335 22:53:29.816664 ==
1336 22:53:29.816717 Dram Type= 6, Freq= 0, CH_0, rank 1
1337 22:53:29.816771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1338 22:53:29.816836 ==
1339 22:53:29.816903 RX Vref Scan: 0
1340 22:53:29.816955
1341 22:53:29.817018 RX Vref 0 -> 0, step: 1
1342 22:53:29.817069
1343 22:53:29.817119 RX Delay -95 -> 252, step: 8
1344 22:53:29.817170 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1345 22:53:29.817221 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1346 22:53:29.817272 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1347 22:53:29.817365 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1348 22:53:29.817430 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1349 22:53:29.817481 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1350 22:53:29.817532 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1351 22:53:29.817583 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1352 22:53:29.817634 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1353 22:53:29.817684 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1354 22:53:29.817735 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1355 22:53:29.817786 iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208
1356 22:53:29.817837 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1357 22:53:29.817888 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1358 22:53:29.817939 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1359 22:53:29.817990 iDelay=209, Bit 15, Center 88 (-15 ~ 192) 208
1360 22:53:29.818041 ==
1361 22:53:29.818092 Dram Type= 6, Freq= 0, CH_0, rank 1
1362 22:53:29.818144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1363 22:53:29.818195 ==
1364 22:53:29.818245 DQS Delay:
1365 22:53:29.818296 DQS0 = 0, DQS1 = 0
1366 22:53:29.818346 DQM Delay:
1367 22:53:29.818397 DQM0 = 90, DQM1 = 81
1368 22:53:29.818447 DQ Delay:
1369 22:53:29.818498 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =84
1370 22:53:29.818550 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1371 22:53:29.818601 DQ8 =72, DQ9 =68, DQ10 =80, DQ11 =80
1372 22:53:29.818652 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =88
1373 22:53:29.818702
1374 22:53:29.818753
1375 22:53:29.818804 [DQSOSCAuto] RK1, (LSB)MR18= 0x4821, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 391 ps
1376 22:53:29.818904 CH0 RK1: MR19=606, MR18=4821
1377 22:53:29.818959 CH0_RK1: MR19=0x606, MR18=0x4821, DQSOSC=391, MR23=63, INC=96, DEC=64
1378 22:53:29.819029 [RxdqsGatingPostProcess] freq 800
1379 22:53:29.819093 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1380 22:53:29.819145 Pre-setting of DQS Precalculation
1381 22:53:29.819197 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1382 22:53:29.819248 ==
1383 22:53:29.819300 Dram Type= 6, Freq= 0, CH_1, rank 0
1384 22:53:29.819351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1385 22:53:29.819402 ==
1386 22:53:29.819453 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1387 22:53:29.819505 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1388 22:53:29.819557 [CA 0] Center 36 (6~67) winsize 62
1389 22:53:29.819661 [CA 1] Center 36 (6~67) winsize 62
1390 22:53:29.819725 [CA 2] Center 34 (4~65) winsize 62
1391 22:53:29.819777 [CA 3] Center 34 (3~65) winsize 63
1392 22:53:29.819856 [CA 4] Center 34 (4~65) winsize 62
1393 22:53:29.819922 [CA 5] Center 33 (3~64) winsize 62
1394 22:53:29.820002
1395 22:53:29.820065 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1396 22:53:29.820117
1397 22:53:29.820189 [CATrainingPosCal] consider 1 rank data
1398 22:53:29.820253 u2DelayCellTimex100 = 270/100 ps
1399 22:53:29.820304 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1400 22:53:29.820355 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1401 22:53:29.820406 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1402 22:53:29.820457 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1403 22:53:29.820508 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1404 22:53:29.820558 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1405 22:53:29.820609
1406 22:53:29.820660 CA PerBit enable=1, Macro0, CA PI delay=33
1407 22:53:29.820710
1408 22:53:29.820761 [CBTSetCACLKResult] CA Dly = 33
1409 22:53:29.820811 CS Dly: 5 (0~36)
1410 22:53:29.820862 ==
1411 22:53:29.820911 Dram Type= 6, Freq= 0, CH_1, rank 1
1412 22:53:29.820962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1413 22:53:29.821014 ==
1414 22:53:29.821081 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1415 22:53:29.821134 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1416 22:53:29.821186 [CA 0] Center 37 (6~68) winsize 63
1417 22:53:29.821238 [CA 1] Center 37 (6~68) winsize 63
1418 22:53:29.821290 [CA 2] Center 35 (5~66) winsize 62
1419 22:53:29.821347 [CA 3] Center 34 (4~65) winsize 62
1420 22:53:29.821411 [CA 4] Center 34 (4~65) winsize 62
1421 22:53:29.821463 [CA 5] Center 34 (4~64) winsize 61
1422 22:53:29.821514
1423 22:53:29.821564 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1424 22:53:29.821615
1425 22:53:29.821666 [CATrainingPosCal] consider 2 rank data
1426 22:53:29.821716 u2DelayCellTimex100 = 270/100 ps
1427 22:53:29.821767 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1428 22:53:29.821818 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1429 22:53:29.821869 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1430 22:53:29.821920 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1431 22:53:29.822020 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1432 22:53:29.822075 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1433 22:53:29.822126
1434 22:53:29.822177 CA PerBit enable=1, Macro0, CA PI delay=34
1435 22:53:29.822229
1436 22:53:29.822279 [CBTSetCACLKResult] CA Dly = 34
1437 22:53:29.822330 CS Dly: 6 (0~38)
1438 22:53:29.822380
1439 22:53:29.822430 ----->DramcWriteLeveling(PI) begin...
1440 22:53:29.822483 ==
1441 22:53:29.822533 Dram Type= 6, Freq= 0, CH_1, rank 0
1442 22:53:29.822585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1443 22:53:29.822636 ==
1444 22:53:29.822687 Write leveling (Byte 0): 29 => 29
1445 22:53:29.822737 Write leveling (Byte 1): 30 => 30
1446 22:53:29.822788 DramcWriteLeveling(PI) end<-----
1447 22:53:29.822839
1448 22:53:29.822889 ==
1449 22:53:29.822941 Dram Type= 6, Freq= 0, CH_1, rank 0
1450 22:53:29.822991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1451 22:53:29.823043 ==
1452 22:53:29.823094 [Gating] SW mode calibration
1453 22:53:29.823173 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1454 22:53:29.823225 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1455 22:53:29.823470 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1456 22:53:29.823563 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1457 22:53:29.823616 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 22:53:29.823669 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 22:53:29.823720 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 22:53:29.823772 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 22:53:29.823823 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 22:53:29.823875 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 22:53:29.823926 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 22:53:29.823978 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 22:53:29.824029 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 22:53:29.824080 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 22:53:29.824132 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 22:53:29.824183 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 22:53:29.824234 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 22:53:29.824286 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 22:53:29.824337 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1472 22:53:29.824389 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 22:53:29.824440 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 22:53:29.824491 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 22:53:29.824543 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 22:53:29.824594 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 22:53:29.824646 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 22:53:29.824697 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 22:53:29.824748 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 22:53:29.824800 0 9 4 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
1481 22:53:29.824851 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 22:53:29.824902 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 22:53:29.824953 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 22:53:29.825004 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 22:53:29.825056 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1486 22:53:29.825106 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1487 22:53:29.825158 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1488 22:53:29.825209 0 10 4 | B1->B0 | 2e2e 2a2a | 1 0 | (1 0) (1 0)
1489 22:53:29.825260 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1490 22:53:29.825341 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 22:53:29.825421 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 22:53:29.825472 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 22:53:29.825523 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 22:53:29.825574 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 22:53:29.825625 0 11 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 1)
1496 22:53:29.825676 0 11 4 | B1->B0 | 2f2f 3939 | 0 0 | (0 0) (0 0)
1497 22:53:29.825744 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 22:53:29.825828 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 22:53:29.825881 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 22:53:29.825932 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 22:53:29.825983 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 22:53:29.826034 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1503 22:53:29.826085 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1504 22:53:29.826137 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1505 22:53:29.826189 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 22:53:29.826240 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 22:53:29.826291 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 22:53:29.826343 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 22:53:29.826394 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 22:53:29.826445 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 22:53:29.826496 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 22:53:29.826547 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 22:53:29.826598 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 22:53:29.826649 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 22:53:29.826701 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 22:53:29.826752 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 22:53:29.826803 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 22:53:29.826855 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 22:53:29.826906 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1520 22:53:29.826958 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1521 22:53:29.827010 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1522 22:53:29.827061 Total UI for P1: 0, mck2ui 16
1523 22:53:29.827113 best dqsien dly found for B0: ( 0, 14, 2)
1524 22:53:29.827164 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1525 22:53:29.827216 Total UI for P1: 0, mck2ui 16
1526 22:53:29.827268 best dqsien dly found for B1: ( 0, 14, 6)
1527 22:53:29.827319 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1528 22:53:29.827370 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1529 22:53:29.827421
1530 22:53:29.827472 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1531 22:53:29.827523 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1532 22:53:29.827575 [Gating] SW calibration Done
1533 22:53:29.827626 ==
1534 22:53:29.827677 Dram Type= 6, Freq= 0, CH_1, rank 0
1535 22:53:29.827728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1536 22:53:29.827779 ==
1537 22:53:29.827831 RX Vref Scan: 0
1538 22:53:29.827881
1539 22:53:29.827932 RX Vref 0 -> 0, step: 1
1540 22:53:29.827983
1541 22:53:29.828033 RX Delay -130 -> 252, step: 16
1542 22:53:29.828085 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1543 22:53:29.828136 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1544 22:53:29.828187 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1545 22:53:29.828479 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1546 22:53:29.828577 iDelay=206, Bit 4, Center 85 (-18 ~ 189) 208
1547 22:53:29.828633 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1548 22:53:29.828700 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1549 22:53:29.828757 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1550 22:53:29.828811 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1551 22:53:29.828864 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1552 22:53:29.828916 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1553 22:53:29.828969 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1554 22:53:29.829022 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1555 22:53:29.829074 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1556 22:53:29.829127 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1557 22:53:29.829179 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1558 22:53:29.829232 ==
1559 22:53:29.829285 Dram Type= 6, Freq= 0, CH_1, rank 0
1560 22:53:29.829392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1561 22:53:29.829445 ==
1562 22:53:29.829496 DQS Delay:
1563 22:53:29.829548 DQS0 = 0, DQS1 = 0
1564 22:53:29.829599 DQM Delay:
1565 22:53:29.829650 DQM0 = 87, DQM1 = 80
1566 22:53:29.829701 DQ Delay:
1567 22:53:29.829752 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =85
1568 22:53:29.829802 DQ4 =85, DQ5 =101, DQ6 =93, DQ7 =85
1569 22:53:29.829853 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1570 22:53:29.829904 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1571 22:53:29.829955
1572 22:53:29.830005
1573 22:53:29.830056 ==
1574 22:53:29.830107 Dram Type= 6, Freq= 0, CH_1, rank 0
1575 22:53:29.830158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1576 22:53:29.830209 ==
1577 22:53:29.830259
1578 22:53:29.830309
1579 22:53:29.830359 TX Vref Scan disable
1580 22:53:29.830410 == TX Byte 0 ==
1581 22:53:29.830461 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1582 22:53:29.830513 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1583 22:53:29.830564 == TX Byte 1 ==
1584 22:53:29.830615 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1585 22:53:29.830667 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1586 22:53:29.830718 ==
1587 22:53:29.830769 Dram Type= 6, Freq= 0, CH_1, rank 0
1588 22:53:29.830820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1589 22:53:29.830871 ==
1590 22:53:29.830922 TX Vref=22, minBit 8, minWin=27, winSum=449
1591 22:53:29.830974 TX Vref=24, minBit 15, minWin=27, winSum=454
1592 22:53:29.831026 TX Vref=26, minBit 1, minWin=28, winSum=459
1593 22:53:29.831078 TX Vref=28, minBit 15, minWin=27, winSum=455
1594 22:53:29.831130 TX Vref=30, minBit 8, minWin=28, winSum=459
1595 22:53:29.831193 TX Vref=32, minBit 15, minWin=27, winSum=456
1596 22:53:29.831246 [TxChooseVref] Worse bit 1, Min win 28, Win sum 459, Final Vref 26
1597 22:53:29.831298
1598 22:53:29.831349 Final TX Range 1 Vref 26
1599 22:53:29.831401
1600 22:53:29.831453 ==
1601 22:53:29.831504 Dram Type= 6, Freq= 0, CH_1, rank 0
1602 22:53:29.831556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1603 22:53:29.831608 ==
1604 22:53:29.831659
1605 22:53:29.831710
1606 22:53:29.831762 TX Vref Scan disable
1607 22:53:29.831813 == TX Byte 0 ==
1608 22:53:29.831865 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1609 22:53:29.831917 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1610 22:53:29.831969 == TX Byte 1 ==
1611 22:53:29.832021 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1612 22:53:29.832073 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1613 22:53:29.832124
1614 22:53:29.832175 [DATLAT]
1615 22:53:29.832227 Freq=800, CH1 RK0
1616 22:53:29.832279
1617 22:53:29.832352 DATLAT Default: 0xa
1618 22:53:29.832406 0, 0xFFFF, sum = 0
1619 22:53:29.832460 1, 0xFFFF, sum = 0
1620 22:53:29.832513 2, 0xFFFF, sum = 0
1621 22:53:29.832565 3, 0xFFFF, sum = 0
1622 22:53:29.832618 4, 0xFFFF, sum = 0
1623 22:53:29.832671 5, 0xFFFF, sum = 0
1624 22:53:29.832723 6, 0xFFFF, sum = 0
1625 22:53:29.832776 7, 0xFFFF, sum = 0
1626 22:53:29.832829 8, 0xFFFF, sum = 0
1627 22:53:29.832881 9, 0x0, sum = 1
1628 22:53:29.832934 10, 0x0, sum = 2
1629 22:53:29.832987 11, 0x0, sum = 3
1630 22:53:29.833040 12, 0x0, sum = 4
1631 22:53:29.833093 best_step = 10
1632 22:53:29.833145
1633 22:53:29.833196 ==
1634 22:53:29.833248 Dram Type= 6, Freq= 0, CH_1, rank 0
1635 22:53:29.833312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1636 22:53:29.833404 ==
1637 22:53:29.833456 RX Vref Scan: 1
1638 22:53:29.833508
1639 22:53:29.833559 Set Vref Range= 32 -> 127
1640 22:53:29.833611
1641 22:53:29.833662 RX Vref 32 -> 127, step: 1
1642 22:53:29.833714
1643 22:53:29.833765 RX Delay -95 -> 252, step: 8
1644 22:53:29.833819
1645 22:53:29.833870 Set Vref, RX VrefLevel [Byte0]: 32
1646 22:53:29.833922 [Byte1]: 32
1647 22:53:29.833974
1648 22:53:29.834025 Set Vref, RX VrefLevel [Byte0]: 33
1649 22:53:29.834077 [Byte1]: 33
1650 22:53:29.834128
1651 22:53:29.834180 Set Vref, RX VrefLevel [Byte0]: 34
1652 22:53:29.834231 [Byte1]: 34
1653 22:53:29.834282
1654 22:53:29.834334 Set Vref, RX VrefLevel [Byte0]: 35
1655 22:53:29.834386 [Byte1]: 35
1656 22:53:29.834438
1657 22:53:29.834489 Set Vref, RX VrefLevel [Byte0]: 36
1658 22:53:29.834540 [Byte1]: 36
1659 22:53:29.834592
1660 22:53:29.834643 Set Vref, RX VrefLevel [Byte0]: 37
1661 22:53:29.834694 [Byte1]: 37
1662 22:53:29.834746
1663 22:53:29.834797 Set Vref, RX VrefLevel [Byte0]: 38
1664 22:53:29.834848 [Byte1]: 38
1665 22:53:29.834899
1666 22:53:29.834950 Set Vref, RX VrefLevel [Byte0]: 39
1667 22:53:29.835002 [Byte1]: 39
1668 22:53:29.835053
1669 22:53:29.835104 Set Vref, RX VrefLevel [Byte0]: 40
1670 22:53:29.835156 [Byte1]: 40
1671 22:53:29.835207
1672 22:53:29.835258 Set Vref, RX VrefLevel [Byte0]: 41
1673 22:53:29.835309 [Byte1]: 41
1674 22:53:29.835360
1675 22:53:29.835411 Set Vref, RX VrefLevel [Byte0]: 42
1676 22:53:29.835462 [Byte1]: 42
1677 22:53:29.835521
1678 22:53:29.835583 Set Vref, RX VrefLevel [Byte0]: 43
1679 22:53:29.835635 [Byte1]: 43
1680 22:53:29.835687
1681 22:53:29.835738 Set Vref, RX VrefLevel [Byte0]: 44
1682 22:53:29.835790 [Byte1]: 44
1683 22:53:29.835841
1684 22:53:29.835893 Set Vref, RX VrefLevel [Byte0]: 45
1685 22:53:29.835945 [Byte1]: 45
1686 22:53:29.835997
1687 22:53:29.836049 Set Vref, RX VrefLevel [Byte0]: 46
1688 22:53:29.836100 [Byte1]: 46
1689 22:53:29.836151
1690 22:53:29.836203 Set Vref, RX VrefLevel [Byte0]: 47
1691 22:53:29.836254 [Byte1]: 47
1692 22:53:29.836305
1693 22:53:29.836357 Set Vref, RX VrefLevel [Byte0]: 48
1694 22:53:29.836409 [Byte1]: 48
1695 22:53:29.836461
1696 22:53:29.836512 Set Vref, RX VrefLevel [Byte0]: 49
1697 22:53:29.836564 [Byte1]: 49
1698 22:53:29.836615
1699 22:53:29.836666 Set Vref, RX VrefLevel [Byte0]: 50
1700 22:53:29.836719 [Byte1]: 50
1701 22:53:29.836770
1702 22:53:29.837011 Set Vref, RX VrefLevel [Byte0]: 51
1703 22:53:29.837070 [Byte1]: 51
1704 22:53:29.837125
1705 22:53:29.837177 Set Vref, RX VrefLevel [Byte0]: 52
1706 22:53:29.837229 [Byte1]: 52
1707 22:53:29.837282
1708 22:53:29.837342 Set Vref, RX VrefLevel [Byte0]: 53
1709 22:53:29.837395 [Byte1]: 53
1710 22:53:29.837447
1711 22:53:29.837499 Set Vref, RX VrefLevel [Byte0]: 54
1712 22:53:29.837550 [Byte1]: 54
1713 22:53:29.837637
1714 22:53:29.837695 Set Vref, RX VrefLevel [Byte0]: 55
1715 22:53:29.837756 [Byte1]: 55
1716 22:53:29.837841
1717 22:53:29.837904 Set Vref, RX VrefLevel [Byte0]: 56
1718 22:53:29.837957 [Byte1]: 56
1719 22:53:29.838009
1720 22:53:29.838062 Set Vref, RX VrefLevel [Byte0]: 57
1721 22:53:29.838114 [Byte1]: 57
1722 22:53:29.838166
1723 22:53:29.838217 Set Vref, RX VrefLevel [Byte0]: 58
1724 22:53:29.838269 [Byte1]: 58
1725 22:53:29.838321
1726 22:53:29.838372 Set Vref, RX VrefLevel [Byte0]: 59
1727 22:53:29.838425 [Byte1]: 59
1728 22:53:29.838477
1729 22:53:29.838528 Set Vref, RX VrefLevel [Byte0]: 60
1730 22:53:29.838580 [Byte1]: 60
1731 22:53:29.838631
1732 22:53:29.838683 Set Vref, RX VrefLevel [Byte0]: 61
1733 22:53:29.838734 [Byte1]: 61
1734 22:53:29.838786
1735 22:53:29.838837 Set Vref, RX VrefLevel [Byte0]: 62
1736 22:53:29.838889 [Byte1]: 62
1737 22:53:29.838940
1738 22:53:29.838991 Set Vref, RX VrefLevel [Byte0]: 63
1739 22:53:29.839046 [Byte1]: 63
1740 22:53:29.839111
1741 22:53:29.839163 Set Vref, RX VrefLevel [Byte0]: 64
1742 22:53:29.839215 [Byte1]: 64
1743 22:53:29.839267
1744 22:53:29.839318 Set Vref, RX VrefLevel [Byte0]: 65
1745 22:53:29.839370 [Byte1]: 65
1746 22:53:29.839421
1747 22:53:29.839472 Set Vref, RX VrefLevel [Byte0]: 66
1748 22:53:29.839524 [Byte1]: 66
1749 22:53:29.839576
1750 22:53:29.839628 Set Vref, RX VrefLevel [Byte0]: 67
1751 22:53:29.839679 [Byte1]: 67
1752 22:53:29.839730
1753 22:53:29.839782 Set Vref, RX VrefLevel [Byte0]: 68
1754 22:53:29.839834 [Byte1]: 68
1755 22:53:29.839885
1756 22:53:29.839936 Set Vref, RX VrefLevel [Byte0]: 69
1757 22:53:29.839988 [Byte1]: 69
1758 22:53:29.840040
1759 22:53:29.840091 Set Vref, RX VrefLevel [Byte0]: 70
1760 22:53:29.840143 [Byte1]: 70
1761 22:53:29.840195
1762 22:53:29.840246 Set Vref, RX VrefLevel [Byte0]: 71
1763 22:53:29.840298 [Byte1]: 71
1764 22:53:29.840350
1765 22:53:29.840401 Set Vref, RX VrefLevel [Byte0]: 72
1766 22:53:29.840452 [Byte1]: 72
1767 22:53:29.840504
1768 22:53:29.840556 Set Vref, RX VrefLevel [Byte0]: 73
1769 22:53:29.840608 [Byte1]: 73
1770 22:53:29.840660
1771 22:53:29.840711 Set Vref, RX VrefLevel [Byte0]: 74
1772 22:53:29.840762 [Byte1]: 74
1773 22:53:29.840814
1774 22:53:29.840866 Set Vref, RX VrefLevel [Byte0]: 75
1775 22:53:29.840917 [Byte1]: 75
1776 22:53:29.840969
1777 22:53:29.841021 Set Vref, RX VrefLevel [Byte0]: 76
1778 22:53:29.841072 [Byte1]: 76
1779 22:53:29.841124
1780 22:53:29.841175 Set Vref, RX VrefLevel [Byte0]: 77
1781 22:53:29.841227 [Byte1]: 77
1782 22:53:29.841278
1783 22:53:29.841349 Set Vref, RX VrefLevel [Byte0]: 78
1784 22:53:29.841402 [Byte1]: 78
1785 22:53:29.841454
1786 22:53:29.841505 Final RX Vref Byte 0 = 55 to rank0
1787 22:53:29.841557 Final RX Vref Byte 1 = 63 to rank0
1788 22:53:29.841609 Final RX Vref Byte 0 = 55 to rank1
1789 22:53:29.841661 Final RX Vref Byte 1 = 63 to rank1==
1790 22:53:29.841713 Dram Type= 6, Freq= 0, CH_1, rank 0
1791 22:53:29.841765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1792 22:53:29.841817 ==
1793 22:53:29.841870 DQS Delay:
1794 22:53:29.841921 DQS0 = 0, DQS1 = 0
1795 22:53:29.841973 DQM Delay:
1796 22:53:29.842024 DQM0 = 90, DQM1 = 82
1797 22:53:29.842075 DQ Delay:
1798 22:53:29.842126 DQ0 =92, DQ1 =84, DQ2 =84, DQ3 =88
1799 22:53:29.842178 DQ4 =88, DQ5 =96, DQ6 =100, DQ7 =88
1800 22:53:29.842229 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =76
1801 22:53:29.842300 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
1802 22:53:29.842355
1803 22:53:29.842407
1804 22:53:29.842458 [DQSOSCAuto] RK0, (LSB)MR18= 0x314f, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
1805 22:53:29.842512 CH1 RK0: MR19=606, MR18=314F
1806 22:53:29.842564 CH1_RK0: MR19=0x606, MR18=0x314F, DQSOSC=390, MR23=63, INC=97, DEC=64
1807 22:53:29.842616
1808 22:53:29.842668 ----->DramcWriteLeveling(PI) begin...
1809 22:53:29.842720 ==
1810 22:53:29.842773 Dram Type= 6, Freq= 0, CH_1, rank 1
1811 22:53:29.842826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1812 22:53:29.842879 ==
1813 22:53:29.842930 Write leveling (Byte 0): 28 => 28
1814 22:53:29.842983 Write leveling (Byte 1): 29 => 29
1815 22:53:29.843035 DramcWriteLeveling(PI) end<-----
1816 22:53:29.843086
1817 22:53:29.843137 ==
1818 22:53:29.843189 Dram Type= 6, Freq= 0, CH_1, rank 1
1819 22:53:29.843241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1820 22:53:29.843293 ==
1821 22:53:29.843345 [Gating] SW mode calibration
1822 22:53:29.843397 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1823 22:53:29.843449 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1824 22:53:29.843501 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1825 22:53:29.843554 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1826 22:53:29.843605 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 22:53:29.843657 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 22:53:29.843709 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 22:53:29.843761 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 22:53:29.843813 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 22:53:29.843865 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 22:53:29.843916 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 22:53:29.843968 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 22:53:29.844019 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 22:53:29.844071 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 22:53:29.844122 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 22:53:29.844174 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 22:53:29.844225 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 22:53:29.844277 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 22:53:29.844521 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1841 22:53:29.844582 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1842 22:53:29.844635 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1843 22:53:29.844686 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 22:53:29.844738 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 22:53:29.844790 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 22:53:29.844843 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 22:53:29.844895 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 22:53:29.844946 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 22:53:29.844998 0 9 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1850 22:53:29.845049 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1851 22:53:29.845100 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1852 22:53:29.845152 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1853 22:53:29.845204 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1854 22:53:29.845255 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1855 22:53:29.845313 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1856 22:53:29.845366 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1857 22:53:29.845418 0 10 4 | B1->B0 | 2c2c 2e2e | 0 1 | (0 0) (1 0)
1858 22:53:29.845469 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 22:53:29.845521 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 22:53:29.845573 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 22:53:29.845627 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 22:53:29.845696 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 22:53:29.845749 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 22:53:29.845801 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 22:53:29.845854 0 11 4 | B1->B0 | 3434 3232 | 0 0 | (1 1) (1 1)
1866 22:53:29.845906 0 11 8 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1867 22:53:29.845958 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1868 22:53:29.846010 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1869 22:53:29.846062 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1870 22:53:29.846114 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1871 22:53:29.846166 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1872 22:53:29.846217 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1873 22:53:29.846270 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1874 22:53:29.846322 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 22:53:29.846388 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 22:53:29.846460 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 22:53:29.846516 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 22:53:29.846589 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 22:53:29.846645 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 22:53:29.846698 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 22:53:29.846750 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 22:53:29.846802 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 22:53:29.846853 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 22:53:29.846918 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 22:53:29.846979 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1886 22:53:29.847052 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1887 22:53:29.847114 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1888 22:53:29.847177 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1889 22:53:29.847244 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1890 22:53:29.847307 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1891 22:53:29.847367 Total UI for P1: 0, mck2ui 16
1892 22:53:29.847428 best dqsien dly found for B1: ( 0, 14, 2)
1893 22:53:29.847483 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1894 22:53:29.847534 Total UI for P1: 0, mck2ui 16
1895 22:53:29.847586 best dqsien dly found for B0: ( 0, 14, 6)
1896 22:53:29.847638 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1897 22:53:29.847690 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1898 22:53:29.847741
1899 22:53:29.847793 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1900 22:53:29.847845 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1901 22:53:29.847897 [Gating] SW calibration Done
1902 22:53:29.847949 ==
1903 22:53:29.848000 Dram Type= 6, Freq= 0, CH_1, rank 1
1904 22:53:29.848053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1905 22:53:29.848106 ==
1906 22:53:29.848157 RX Vref Scan: 0
1907 22:53:29.848209
1908 22:53:29.848260 RX Vref 0 -> 0, step: 1
1909 22:53:29.848311
1910 22:53:29.848363 RX Delay -130 -> 252, step: 16
1911 22:53:29.848415 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1912 22:53:29.848467 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1913 22:53:29.848520 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1914 22:53:29.848571 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1915 22:53:29.848623 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1916 22:53:29.990635 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1917 22:53:29.991147 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1918 22:53:29.991624 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1919 22:53:29.991821 iDelay=206, Bit 8, Center 61 (-50 ~ 173) 224
1920 22:53:29.991906 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1921 22:53:29.991992 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1922 22:53:29.992073 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1923 22:53:29.992130 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1924 22:53:29.992185 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1925 22:53:29.992239 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1926 22:53:29.992293 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1927 22:53:29.992345 ==
1928 22:53:29.992398 Dram Type= 6, Freq= 0, CH_1, rank 1
1929 22:53:29.992451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1930 22:53:29.992505 ==
1931 22:53:29.992557 DQS Delay:
1932 22:53:29.992609 DQS0 = 0, DQS1 = 0
1933 22:53:29.992661 DQM Delay:
1934 22:53:29.992712 DQM0 = 89, DQM1 = 82
1935 22:53:29.992763 DQ Delay:
1936 22:53:29.993017 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1937 22:53:29.993126 DQ4 =93, DQ5 =93, DQ6 =93, DQ7 =85
1938 22:53:29.993206 DQ8 =61, DQ9 =77, DQ10 =85, DQ11 =77
1939 22:53:29.993258 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =85
1940 22:53:29.993356
1941 22:53:29.993412
1942 22:53:29.993464 ==
1943 22:53:29.993516 Dram Type= 6, Freq= 0, CH_1, rank 1
1944 22:53:29.993569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1945 22:53:29.993635 ==
1946 22:53:29.993686
1947 22:53:29.993737
1948 22:53:29.993787 TX Vref Scan disable
1949 22:53:29.993838 == TX Byte 0 ==
1950 22:53:29.993890 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1951 22:53:29.993942 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1952 22:53:29.994008 == TX Byte 1 ==
1953 22:53:29.994072 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1954 22:53:29.994124 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1955 22:53:29.994190 ==
1956 22:53:29.994243 Dram Type= 6, Freq= 0, CH_1, rank 1
1957 22:53:29.994307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1958 22:53:29.994359 ==
1959 22:53:29.994459 TX Vref=22, minBit 13, minWin=27, winSum=450
1960 22:53:29.994517 TX Vref=24, minBit 13, minWin=27, winSum=452
1961 22:53:29.994569 TX Vref=26, minBit 13, minWin=27, winSum=457
1962 22:53:29.994621 TX Vref=28, minBit 8, minWin=28, winSum=459
1963 22:53:29.994688 TX Vref=30, minBit 8, minWin=28, winSum=461
1964 22:53:29.994762 TX Vref=32, minBit 9, minWin=27, winSum=456
1965 22:53:29.994848 [TxChooseVref] Worse bit 8, Min win 28, Win sum 461, Final Vref 30
1966 22:53:29.994968
1967 22:53:29.995052 Final TX Range 1 Vref 30
1968 22:53:29.995123
1969 22:53:29.995178 ==
1970 22:53:29.995231 Dram Type= 6, Freq= 0, CH_1, rank 1
1971 22:53:29.995282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1972 22:53:29.995335 ==
1973 22:53:29.995386
1974 22:53:29.995437
1975 22:53:29.995487 TX Vref Scan disable
1976 22:53:29.995538 == TX Byte 0 ==
1977 22:53:29.995590 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1978 22:53:29.995642 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1979 22:53:29.995693 == TX Byte 1 ==
1980 22:53:29.995745 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1981 22:53:29.995796 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1982 22:53:29.995848
1983 22:53:29.995899 [DATLAT]
1984 22:53:29.995949 Freq=800, CH1 RK1
1985 22:53:29.996001
1986 22:53:29.996051 DATLAT Default: 0xa
1987 22:53:29.996102 0, 0xFFFF, sum = 0
1988 22:53:29.996154 1, 0xFFFF, sum = 0
1989 22:53:29.996222 2, 0xFFFF, sum = 0
1990 22:53:29.996275 3, 0xFFFF, sum = 0
1991 22:53:29.996368 4, 0xFFFF, sum = 0
1992 22:53:29.996436 5, 0xFFFF, sum = 0
1993 22:53:29.996501 6, 0xFFFF, sum = 0
1994 22:53:29.996553 7, 0xFFFF, sum = 0
1995 22:53:29.996605 8, 0xFFFF, sum = 0
1996 22:53:29.996656 9, 0x0, sum = 1
1997 22:53:29.996708 10, 0x0, sum = 2
1998 22:53:29.996760 11, 0x0, sum = 3
1999 22:53:29.996812 12, 0x0, sum = 4
2000 22:53:29.996864 best_step = 10
2001 22:53:29.996915
2002 22:53:29.996966 ==
2003 22:53:29.997017 Dram Type= 6, Freq= 0, CH_1, rank 1
2004 22:53:29.997068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2005 22:53:29.997119 ==
2006 22:53:29.997170 RX Vref Scan: 0
2007 22:53:29.997221
2008 22:53:29.997271 RX Vref 0 -> 0, step: 1
2009 22:53:29.997378
2010 22:53:29.997445 RX Delay -95 -> 252, step: 8
2011 22:53:29.997497 iDelay=209, Bit 0, Center 96 (-7 ~ 200) 208
2012 22:53:29.997550 iDelay=209, Bit 1, Center 88 (-15 ~ 192) 208
2013 22:53:29.997602 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2014 22:53:29.997655 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2015 22:53:29.997706 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
2016 22:53:29.997758 iDelay=209, Bit 5, Center 104 (1 ~ 208) 208
2017 22:53:29.997810 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
2018 22:53:29.997862 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2019 22:53:29.997914 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2020 22:53:29.997966 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
2021 22:53:29.998068 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
2022 22:53:29.998123 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2023 22:53:29.998176 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2024 22:53:29.998229 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
2025 22:53:29.998282 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2026 22:53:29.998365 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
2027 22:53:29.998417 ==
2028 22:53:29.998593 Dram Type= 6, Freq= 0, CH_1, rank 1
2029 22:53:29.998686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2030 22:53:29.998771 ==
2031 22:53:29.998854 DQS Delay:
2032 22:53:29.998911 DQS0 = 0, DQS1 = 0
2033 22:53:29.998965 DQM Delay:
2034 22:53:29.999018 DQM0 = 92, DQM1 = 84
2035 22:53:29.999070 DQ Delay:
2036 22:53:29.999124 DQ0 =96, DQ1 =88, DQ2 =80, DQ3 =88
2037 22:53:29.999177 DQ4 =92, DQ5 =104, DQ6 =100, DQ7 =88
2038 22:53:29.999229 DQ8 =68, DQ9 =76, DQ10 =88, DQ11 =80
2039 22:53:29.999282 DQ12 =92, DQ13 =92, DQ14 =88, DQ15 =92
2040 22:53:29.999335
2041 22:53:29.999387
2042 22:53:29.999439 [DQSOSCAuto] RK1, (LSB)MR18= 0x3a0e, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 395 ps
2043 22:53:29.999493 CH1 RK1: MR19=606, MR18=3A0E
2044 22:53:29.999546 CH1_RK1: MR19=0x606, MR18=0x3A0E, DQSOSC=395, MR23=63, INC=94, DEC=63
2045 22:53:29.999599 [RxdqsGatingPostProcess] freq 800
2046 22:53:29.999651 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2047 22:53:29.999704 Pre-setting of DQS Precalculation
2048 22:53:29.999756 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2049 22:53:29.999809 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2050 22:53:29.999863 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2051 22:53:29.999916
2052 22:53:29.999967
2053 22:53:30.000019 [Calibration Summary] 1600 Mbps
2054 22:53:30.000072 CH 0, Rank 0
2055 22:53:30.000124 SW Impedance : PASS
2056 22:53:30.000176 DUTY Scan : NO K
2057 22:53:30.000229 ZQ Calibration : PASS
2058 22:53:30.000282 Jitter Meter : NO K
2059 22:53:30.000334 CBT Training : PASS
2060 22:53:30.000386 Write leveling : PASS
2061 22:53:30.000438 RX DQS gating : PASS
2062 22:53:30.000490 RX DQ/DQS(RDDQC) : PASS
2063 22:53:30.000542 TX DQ/DQS : PASS
2064 22:53:30.000611 RX DATLAT : PASS
2065 22:53:30.000691 RX DQ/DQS(Engine): PASS
2066 22:53:30.000785 TX OE : NO K
2067 22:53:30.000838 All Pass.
2068 22:53:30.000890
2069 22:53:30.000942 CH 0, Rank 1
2070 22:53:30.000994 SW Impedance : PASS
2071 22:53:30.001046 DUTY Scan : NO K
2072 22:53:30.001099 ZQ Calibration : PASS
2073 22:53:30.001150 Jitter Meter : NO K
2074 22:53:30.001202 CBT Training : PASS
2075 22:53:30.001269 Write leveling : PASS
2076 22:53:30.001394 RX DQS gating : PASS
2077 22:53:30.001448 RX DQ/DQS(RDDQC) : PASS
2078 22:53:30.001501 TX DQ/DQS : PASS
2079 22:53:30.001554 RX DATLAT : PASS
2080 22:53:30.001607 RX DQ/DQS(Engine): PASS
2081 22:53:30.001893 TX OE : NO K
2082 22:53:30.001996 All Pass.
2083 22:53:30.002082
2084 22:53:30.002171 CH 1, Rank 0
2085 22:53:30.002231 SW Impedance : PASS
2086 22:53:30.002286 DUTY Scan : NO K
2087 22:53:30.002340 ZQ Calibration : PASS
2088 22:53:30.002394 Jitter Meter : NO K
2089 22:53:30.002448 CBT Training : PASS
2090 22:53:30.002502 Write leveling : PASS
2091 22:53:30.002555 RX DQS gating : PASS
2092 22:53:30.002609 RX DQ/DQS(RDDQC) : PASS
2093 22:53:30.002662 TX DQ/DQS : PASS
2094 22:53:30.002716 RX DATLAT : PASS
2095 22:53:30.002769 RX DQ/DQS(Engine): PASS
2096 22:53:30.002822 TX OE : NO K
2097 22:53:30.002876 All Pass.
2098 22:53:30.002928
2099 22:53:30.002982 CH 1, Rank 1
2100 22:53:30.003035 SW Impedance : PASS
2101 22:53:30.003117 DUTY Scan : NO K
2102 22:53:30.003170 ZQ Calibration : PASS
2103 22:53:30.003236 Jitter Meter : NO K
2104 22:53:30.003289 CBT Training : PASS
2105 22:53:30.003341 Write leveling : PASS
2106 22:53:30.003394 RX DQS gating : PASS
2107 22:53:30.003446 RX DQ/DQS(RDDQC) : PASS
2108 22:53:30.003499 TX DQ/DQS : PASS
2109 22:53:30.003551 RX DATLAT : PASS
2110 22:53:30.003604 RX DQ/DQS(Engine): PASS
2111 22:53:30.003657 TX OE : NO K
2112 22:53:30.003709 All Pass.
2113 22:53:30.003762
2114 22:53:30.003814 DramC Write-DBI off
2115 22:53:30.003867 PER_BANK_REFRESH: Hybrid Mode
2116 22:53:30.003919 TX_TRACKING: ON
2117 22:53:30.003987 [GetDramInforAfterCalByMRR] Vendor 6.
2118 22:53:30.004053 [GetDramInforAfterCalByMRR] Revision 606.
2119 22:53:30.004105 [GetDramInforAfterCalByMRR] Revision 2 0.
2120 22:53:30.004157 MR0 0x3b3b
2121 22:53:30.004210 MR8 0x5151
2122 22:53:30.004262 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2123 22:53:30.004314
2124 22:53:30.004366 MR0 0x3b3b
2125 22:53:30.004418 MR8 0x5151
2126 22:53:30.004471 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2127 22:53:30.004524
2128 22:53:30.004576 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2129 22:53:30.004629 [FAST_K] Save calibration result to emmc
2130 22:53:30.004698 [FAST_K] Save calibration result to emmc
2131 22:53:30.004784 dram_init: config_dvfs: 1
2132 22:53:30.004839 dramc_set_vcore_voltage set vcore to 662500
2133 22:53:30.004893 Read voltage for 1200, 2
2134 22:53:30.004945 Vio18 = 0
2135 22:53:30.005013 Vcore = 662500
2136 22:53:30.005102 Vdram = 0
2137 22:53:30.005189 Vddq = 0
2138 22:53:30.005278 Vmddr = 0
2139 22:53:30.005415 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2140 22:53:30.005472 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2141 22:53:30.005555 MEM_TYPE=3, freq_sel=15
2142 22:53:30.005639 sv_algorithm_assistance_LP4_1600
2143 22:53:30.005720 ============ PULL DRAM RESETB DOWN ============
2144 22:53:30.005788 ========== PULL DRAM RESETB DOWN end =========
2145 22:53:30.005856 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2146 22:53:30.005911 ===================================
2147 22:53:30.005965 LPDDR4 DRAM CONFIGURATION
2148 22:53:30.006019 ===================================
2149 22:53:30.006072 EX_ROW_EN[0] = 0x0
2150 22:53:30.006126 EX_ROW_EN[1] = 0x0
2151 22:53:30.006180 LP4Y_EN = 0x0
2152 22:53:30.006234 WORK_FSP = 0x0
2153 22:53:30.006287 WL = 0x4
2154 22:53:30.006340 RL = 0x4
2155 22:53:30.006393 BL = 0x2
2156 22:53:30.006447 RPST = 0x0
2157 22:53:30.006500 RD_PRE = 0x0
2158 22:53:30.006553 WR_PRE = 0x1
2159 22:53:30.006606 WR_PST = 0x0
2160 22:53:30.006659 DBI_WR = 0x0
2161 22:53:30.006712 DBI_RD = 0x0
2162 22:53:30.006765 OTF = 0x1
2163 22:53:30.006818 ===================================
2164 22:53:30.006872 ===================================
2165 22:53:30.006925 ANA top config
2166 22:53:30.006979 ===================================
2167 22:53:30.007033 DLL_ASYNC_EN = 0
2168 22:53:30.007087 ALL_SLAVE_EN = 0
2169 22:53:30.007140 NEW_RANK_MODE = 1
2170 22:53:30.007194 DLL_IDLE_MODE = 1
2171 22:53:30.007246 LP45_APHY_COMB_EN = 1
2172 22:53:30.007299 TX_ODT_DIS = 1
2173 22:53:30.007353 NEW_8X_MODE = 1
2174 22:53:30.007406 ===================================
2175 22:53:30.007460 ===================================
2176 22:53:30.007513 data_rate = 2400
2177 22:53:30.007566 CKR = 1
2178 22:53:30.007623 DQ_P2S_RATIO = 8
2179 22:53:30.007689 ===================================
2180 22:53:30.007744 CA_P2S_RATIO = 8
2181 22:53:30.007797 DQ_CA_OPEN = 0
2182 22:53:30.007851 DQ_SEMI_OPEN = 0
2183 22:53:30.007904 CA_SEMI_OPEN = 0
2184 22:53:30.007957 CA_FULL_RATE = 0
2185 22:53:30.008010 DQ_CKDIV4_EN = 0
2186 22:53:30.008063 CA_CKDIV4_EN = 0
2187 22:53:30.008116 CA_PREDIV_EN = 0
2188 22:53:30.008169 PH8_DLY = 17
2189 22:53:30.008223 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2190 22:53:30.008276 DQ_AAMCK_DIV = 4
2191 22:53:30.008329 CA_AAMCK_DIV = 4
2192 22:53:30.008387 CA_ADMCK_DIV = 4
2193 22:53:30.008476 DQ_TRACK_CA_EN = 0
2194 22:53:30.008572 CA_PICK = 1200
2195 22:53:30.008659 CA_MCKIO = 1200
2196 22:53:30.008732 MCKIO_SEMI = 0
2197 22:53:30.008789 PLL_FREQ = 2366
2198 22:53:30.008844 DQ_UI_PI_RATIO = 32
2199 22:53:30.008899 CA_UI_PI_RATIO = 0
2200 22:53:30.008953 ===================================
2201 22:53:30.009007 ===================================
2202 22:53:30.009061 memory_type:LPDDR4
2203 22:53:30.009115 GP_NUM : 10
2204 22:53:30.009169 SRAM_EN : 1
2205 22:53:30.009222 MD32_EN : 0
2206 22:53:30.009276 ===================================
2207 22:53:30.009391 [ANA_INIT] >>>>>>>>>>>>>>
2208 22:53:30.009471 <<<<<< [CONFIGURE PHASE]: ANA_TX
2209 22:53:30.009527 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2210 22:53:30.009582 ===================================
2211 22:53:30.009637 data_rate = 2400,PCW = 0X5b00
2212 22:53:30.009690 ===================================
2213 22:53:30.009745 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2214 22:53:30.009798 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2215 22:53:30.009852 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2216 22:53:30.009906 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2217 22:53:30.009960 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2218 22:53:30.010013 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2219 22:53:30.010067 [ANA_INIT] flow start
2220 22:53:30.010121 [ANA_INIT] PLL >>>>>>>>
2221 22:53:30.010174 [ANA_INIT] PLL <<<<<<<<
2222 22:53:30.010418 [ANA_INIT] MIDPI >>>>>>>>
2223 22:53:30.010478 [ANA_INIT] MIDPI <<<<<<<<
2224 22:53:30.010532 [ANA_INIT] DLL >>>>>>>>
2225 22:53:30.010636 [ANA_INIT] DLL <<<<<<<<
2226 22:53:30.010722 [ANA_INIT] flow end
2227 22:53:30.010778 ============ LP4 DIFF to SE enter ============
2228 22:53:30.010833 ============ LP4 DIFF to SE exit ============
2229 22:53:30.010887 [ANA_INIT] <<<<<<<<<<<<<
2230 22:53:30.010941 [Flow] Enable top DCM control >>>>>
2231 22:53:30.010994 [Flow] Enable top DCM control <<<<<
2232 22:53:30.011048 Enable DLL master slave shuffle
2233 22:53:30.011102 ==============================================================
2234 22:53:30.011156 Gating Mode config
2235 22:53:30.011209 ==============================================================
2236 22:53:30.011263 Config description:
2237 22:53:30.011317 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2238 22:53:30.011387 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2239 22:53:30.011445 SELPH_MODE 0: By rank 1: By Phase
2240 22:53:30.011501 ==============================================================
2241 22:53:30.011554 GAT_TRACK_EN = 1
2242 22:53:30.011608 RX_GATING_MODE = 2
2243 22:53:30.011662 RX_GATING_TRACK_MODE = 2
2244 22:53:30.011735 SELPH_MODE = 1
2245 22:53:30.011821 PICG_EARLY_EN = 1
2246 22:53:30.011909 VALID_LAT_VALUE = 1
2247 22:53:30.011968 ==============================================================
2248 22:53:30.012023 Enter into Gating configuration >>>>
2249 22:53:30.012077 Exit from Gating configuration <<<<
2250 22:53:30.012131 Enter into DVFS_PRE_config >>>>>
2251 22:53:30.012185 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2252 22:53:30.012240 Exit from DVFS_PRE_config <<<<<
2253 22:53:30.012294 Enter into PICG configuration >>>>
2254 22:53:30.012348 Exit from PICG configuration <<<<
2255 22:53:30.012400 [RX_INPUT] configuration >>>>>
2256 22:53:30.012454 [RX_INPUT] configuration <<<<<
2257 22:53:30.012508 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2258 22:53:30.012562 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2259 22:53:30.012615 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2260 22:53:30.012669 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2261 22:53:30.012723 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2262 22:53:30.012777 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2263 22:53:30.012830 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2264 22:53:30.012884 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2265 22:53:30.012937 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2266 22:53:30.012992 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2267 22:53:30.013045 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2268 22:53:30.013099 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2269 22:53:30.013153 ===================================
2270 22:53:30.013207 LPDDR4 DRAM CONFIGURATION
2271 22:53:30.013261 ===================================
2272 22:53:30.013321 EX_ROW_EN[0] = 0x0
2273 22:53:30.013375 EX_ROW_EN[1] = 0x0
2274 22:53:30.013428 LP4Y_EN = 0x0
2275 22:53:30.013482 WORK_FSP = 0x0
2276 22:53:30.013535 WL = 0x4
2277 22:53:30.013588 RL = 0x4
2278 22:53:30.013641 BL = 0x2
2279 22:53:30.013694 RPST = 0x0
2280 22:53:30.013747 RD_PRE = 0x0
2281 22:53:30.013799 WR_PRE = 0x1
2282 22:53:30.013852 WR_PST = 0x0
2283 22:53:30.013905 DBI_WR = 0x0
2284 22:53:30.013959 DBI_RD = 0x0
2285 22:53:30.014012 OTF = 0x1
2286 22:53:30.014066 ===================================
2287 22:53:30.014119 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2288 22:53:30.014173 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2289 22:53:30.014226 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2290 22:53:30.014286 ===================================
2291 22:53:30.014352 LPDDR4 DRAM CONFIGURATION
2292 22:53:30.014407 ===================================
2293 22:53:30.014461 EX_ROW_EN[0] = 0x10
2294 22:53:30.014514 EX_ROW_EN[1] = 0x0
2295 22:53:30.014566 LP4Y_EN = 0x0
2296 22:53:30.014618 WORK_FSP = 0x0
2297 22:53:30.014669 WL = 0x4
2298 22:53:30.014720 RL = 0x4
2299 22:53:30.014772 BL = 0x2
2300 22:53:30.014824 RPST = 0x0
2301 22:53:30.014875 RD_PRE = 0x0
2302 22:53:30.014927 WR_PRE = 0x1
2303 22:53:30.014978 WR_PST = 0x0
2304 22:53:30.015067 DBI_WR = 0x0
2305 22:53:30.015149 DBI_RD = 0x0
2306 22:53:30.015224 OTF = 0x1
2307 22:53:30.015279 ===================================
2308 22:53:30.015332 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2309 22:53:30.015386 ==
2310 22:53:30.015438 Dram Type= 6, Freq= 0, CH_0, rank 0
2311 22:53:30.015490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2312 22:53:30.015544 ==
2313 22:53:30.015596 [Duty_Offset_Calibration]
2314 22:53:30.015648 B0:2 B1:0 CA:1
2315 22:53:30.015700
2316 22:53:30.015752 [DutyScan_Calibration_Flow] k_type=0
2317 22:53:30.015803
2318 22:53:30.015855 ==CLK 0==
2319 22:53:30.015908 Final CLK duty delay cell = -4
2320 22:53:30.015960 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2321 22:53:30.016013 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2322 22:53:30.016064 [-4] AVG Duty = 4953%(X100)
2323 22:53:30.016116
2324 22:53:30.016167 CH0 CLK Duty spec in!! Max-Min= 156%
2325 22:53:30.016220 [DutyScan_Calibration_Flow] ====Done====
2326 22:53:30.016272
2327 22:53:30.016323 [DutyScan_Calibration_Flow] k_type=1
2328 22:53:30.016375
2329 22:53:30.016426 ==DQS 0 ==
2330 22:53:30.016477 Final DQS duty delay cell = 0
2331 22:53:30.016530 [0] MAX Duty = 5187%(X100), DQS PI = 30
2332 22:53:30.016582 [0] MIN Duty = 4938%(X100), DQS PI = 0
2333 22:53:30.016635 [0] AVG Duty = 5062%(X100)
2334 22:53:30.016686
2335 22:53:30.016737 ==DQS 1 ==
2336 22:53:30.016790 Final DQS duty delay cell = -4
2337 22:53:30.016843 [-4] MAX Duty = 5124%(X100), DQS PI = 34
2338 22:53:30.016895 [-4] MIN Duty = 4907%(X100), DQS PI = 8
2339 22:53:30.016946 [-4] AVG Duty = 5015%(X100)
2340 22:53:30.016997
2341 22:53:30.017241 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2342 22:53:30.017306
2343 22:53:30.017361 CH0 DQS 1 Duty spec in!! Max-Min= 217%
2344 22:53:30.017415 [DutyScan_Calibration_Flow] ====Done====
2345 22:53:30.017467
2346 22:53:30.017519 [DutyScan_Calibration_Flow] k_type=3
2347 22:53:30.017571
2348 22:53:30.017623 ==DQM 0 ==
2349 22:53:30.017675 Final DQM duty delay cell = 0
2350 22:53:30.017729 [0] MAX Duty = 5062%(X100), DQS PI = 24
2351 22:53:30.017781 [0] MIN Duty = 4813%(X100), DQS PI = 0
2352 22:53:30.017833 [0] AVG Duty = 4937%(X100)
2353 22:53:30.017885
2354 22:53:30.017957 ==DQM 1 ==
2355 22:53:30.018012 Final DQM duty delay cell = 0
2356 22:53:30.018064 [0] MAX Duty = 5187%(X100), DQS PI = 48
2357 22:53:30.018117 [0] MIN Duty = 5000%(X100), DQS PI = 12
2358 22:53:30.018169 [0] AVG Duty = 5093%(X100)
2359 22:53:30.018220
2360 22:53:30.018272 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2361 22:53:30.018324
2362 22:53:30.018379 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2363 22:53:30.018466 [DutyScan_Calibration_Flow] ====Done====
2364 22:53:30.018557
2365 22:53:30.018642 [DutyScan_Calibration_Flow] k_type=2
2366 22:53:30.018723
2367 22:53:30.018779 ==DQ 0 ==
2368 22:53:30.018833 Final DQ duty delay cell = -4
2369 22:53:30.018886 [-4] MAX Duty = 5031%(X100), DQS PI = 34
2370 22:53:30.018939 [-4] MIN Duty = 4875%(X100), DQS PI = 14
2371 22:53:30.018992 [-4] AVG Duty = 4953%(X100)
2372 22:53:30.019045
2373 22:53:30.019097 ==DQ 1 ==
2374 22:53:30.019149 Final DQ duty delay cell = 4
2375 22:53:30.019202 [4] MAX Duty = 5093%(X100), DQS PI = 6
2376 22:53:30.019254 [4] MIN Duty = 5031%(X100), DQS PI = 0
2377 22:53:30.019307 [4] AVG Duty = 5062%(X100)
2378 22:53:30.019358
2379 22:53:30.019411 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2380 22:53:30.019464
2381 22:53:30.019516 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2382 22:53:30.019568 [DutyScan_Calibration_Flow] ====Done====
2383 22:53:30.019620 ==
2384 22:53:30.019672 Dram Type= 6, Freq= 0, CH_1, rank 0
2385 22:53:30.019724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2386 22:53:30.019777 ==
2387 22:53:30.019829 [Duty_Offset_Calibration]
2388 22:53:30.019880 B0:0 B1:-1 CA:2
2389 22:53:30.019932
2390 22:53:30.019984 [DutyScan_Calibration_Flow] k_type=0
2391 22:53:30.020036
2392 22:53:30.020087 ==CLK 0==
2393 22:53:30.020139 Final CLK duty delay cell = 0
2394 22:53:30.020192 [0] MAX Duty = 5156%(X100), DQS PI = 16
2395 22:53:30.020244 [0] MIN Duty = 4938%(X100), DQS PI = 46
2396 22:53:30.020295 [0] AVG Duty = 5047%(X100)
2397 22:53:30.020347
2398 22:53:30.020399 CH1 CLK Duty spec in!! Max-Min= 218%
2399 22:53:30.020451 [DutyScan_Calibration_Flow] ====Done====
2400 22:53:30.020502
2401 22:53:30.020553 [DutyScan_Calibration_Flow] k_type=1
2402 22:53:30.020605
2403 22:53:30.020656 ==DQS 0 ==
2404 22:53:30.020708 Final DQS duty delay cell = 0
2405 22:53:30.020760 [0] MAX Duty = 5093%(X100), DQS PI = 24
2406 22:53:30.020812 [0] MIN Duty = 4969%(X100), DQS PI = 0
2407 22:53:30.020864 [0] AVG Duty = 5031%(X100)
2408 22:53:30.020916
2409 22:53:30.020967 ==DQS 1 ==
2410 22:53:30.021019 Final DQS duty delay cell = 0
2411 22:53:30.021070 [0] MAX Duty = 5156%(X100), DQS PI = 0
2412 22:53:30.021122 [0] MIN Duty = 4813%(X100), DQS PI = 36
2413 22:53:30.021174 [0] AVG Duty = 4984%(X100)
2414 22:53:30.021247
2415 22:53:30.021308 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2416 22:53:30.021362
2417 22:53:30.021414 CH1 DQS 1 Duty spec in!! Max-Min= 343%
2418 22:53:30.021466 [DutyScan_Calibration_Flow] ====Done====
2419 22:53:30.021518
2420 22:53:30.021570 [DutyScan_Calibration_Flow] k_type=3
2421 22:53:30.021621
2422 22:53:30.021673 ==DQM 0 ==
2423 22:53:30.021726 Final DQM duty delay cell = 4
2424 22:53:30.021810 [4] MAX Duty = 5093%(X100), DQS PI = 22
2425 22:53:30.021909 [4] MIN Duty = 4938%(X100), DQS PI = 30
2426 22:53:30.022029 [4] AVG Duty = 5015%(X100)
2427 22:53:30.022111
2428 22:53:30.022183 ==DQM 1 ==
2429 22:53:30.022237 Final DQM duty delay cell = -4
2430 22:53:30.022290 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2431 22:53:30.022342 [-4] MIN Duty = 4720%(X100), DQS PI = 36
2432 22:53:30.022393 [-4] AVG Duty = 4860%(X100)
2433 22:53:30.022444
2434 22:53:30.022495 CH1 DQM 0 Duty spec in!! Max-Min= 155%
2435 22:53:30.022546
2436 22:53:30.022596 CH1 DQM 1 Duty spec in!! Max-Min= 280%
2437 22:53:30.022648 [DutyScan_Calibration_Flow] ====Done====
2438 22:53:30.022698
2439 22:53:30.022749 [DutyScan_Calibration_Flow] k_type=2
2440 22:53:30.022799
2441 22:53:30.022850 ==DQ 0 ==
2442 22:53:30.022902 Final DQ duty delay cell = 0
2443 22:53:30.022953 [0] MAX Duty = 5031%(X100), DQS PI = 16
2444 22:53:30.023004 [0] MIN Duty = 4938%(X100), DQS PI = 30
2445 22:53:30.023055 [0] AVG Duty = 4984%(X100)
2446 22:53:30.023105
2447 22:53:30.023155 ==DQ 1 ==
2448 22:53:30.023207 Final DQ duty delay cell = 0
2449 22:53:30.023258 [0] MAX Duty = 5031%(X100), DQS PI = 2
2450 22:53:30.023309 [0] MIN Duty = 4813%(X100), DQS PI = 34
2451 22:53:30.023360 [0] AVG Duty = 4922%(X100)
2452 22:53:30.023411
2453 22:53:30.023461 CH1 DQ 0 Duty spec in!! Max-Min= 93%
2454 22:53:30.023512
2455 22:53:30.023562 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2456 22:53:30.023613 [DutyScan_Calibration_Flow] ====Done====
2457 22:53:30.023664 nWR fixed to 30
2458 22:53:30.023716 [ModeRegInit_LP4] CH0 RK0
2459 22:53:30.023767 [ModeRegInit_LP4] CH0 RK1
2460 22:53:30.023818 [ModeRegInit_LP4] CH1 RK0
2461 22:53:30.023869 [ModeRegInit_LP4] CH1 RK1
2462 22:53:30.023919 match AC timing 7
2463 22:53:30.023970 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2464 22:53:30.024022 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2465 22:53:30.024074 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2466 22:53:30.024125 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2467 22:53:30.024176 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2468 22:53:30.024243 ==
2469 22:53:30.024304 Dram Type= 6, Freq= 0, CH_0, rank 0
2470 22:53:30.024377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2471 22:53:30.024430 ==
2472 22:53:30.024481 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2473 22:53:30.024532 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2474 22:53:30.024584 [CA 0] Center 38 (7~69) winsize 63
2475 22:53:30.024635 [CA 1] Center 38 (8~69) winsize 62
2476 22:53:30.024686 [CA 2] Center 35 (5~66) winsize 62
2477 22:53:30.024738 [CA 3] Center 35 (4~66) winsize 63
2478 22:53:30.024788 [CA 4] Center 34 (4~65) winsize 62
2479 22:53:30.024838 [CA 5] Center 33 (3~64) winsize 62
2480 22:53:30.024904
2481 22:53:30.024956 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2482 22:53:30.025050
2483 22:53:30.025132 [CATrainingPosCal] consider 1 rank data
2484 22:53:30.025219 u2DelayCellTimex100 = 270/100 ps
2485 22:53:30.025325 CA0 delay=38 (7~69),Diff = 5 PI (24 cell)
2486 22:53:30.025398 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2487 22:53:30.025451 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2488 22:53:30.025502 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2489 22:53:30.025553 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2490 22:53:30.025604 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2491 22:53:30.025655
2492 22:53:30.025915 CA PerBit enable=1, Macro0, CA PI delay=33
2493 22:53:30.025986
2494 22:53:30.026038 [CBTSetCACLKResult] CA Dly = 33
2495 22:53:30.026088 CS Dly: 6 (0~37)
2496 22:53:30.026139 ==
2497 22:53:30.026190 Dram Type= 6, Freq= 0, CH_0, rank 1
2498 22:53:30.026241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2499 22:53:30.026293 ==
2500 22:53:30.026344 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2501 22:53:30.026395 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2502 22:53:30.026448 [CA 0] Center 39 (8~70) winsize 63
2503 22:53:30.026500 [CA 1] Center 38 (8~69) winsize 62
2504 22:53:30.026551 [CA 2] Center 35 (5~66) winsize 62
2505 22:53:30.026601 [CA 3] Center 35 (5~66) winsize 62
2506 22:53:30.026651 [CA 4] Center 34 (4~65) winsize 62
2507 22:53:30.026702 [CA 5] Center 34 (4~64) winsize 61
2508 22:53:30.026753
2509 22:53:30.026804 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2510 22:53:30.026855
2511 22:53:30.026905 [CATrainingPosCal] consider 2 rank data
2512 22:53:30.026956 u2DelayCellTimex100 = 270/100 ps
2513 22:53:30.027007 CA0 delay=38 (8~69),Diff = 4 PI (19 cell)
2514 22:53:30.027057 CA1 delay=38 (8~69),Diff = 4 PI (19 cell)
2515 22:53:30.027108 CA2 delay=35 (5~66),Diff = 1 PI (4 cell)
2516 22:53:30.027159 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2517 22:53:30.027210 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2518 22:53:30.027261 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2519 22:53:30.027312
2520 22:53:30.027363 CA PerBit enable=1, Macro0, CA PI delay=34
2521 22:53:30.027413
2522 22:53:30.027464 [CBTSetCACLKResult] CA Dly = 34
2523 22:53:30.027515 CS Dly: 7 (0~39)
2524 22:53:30.027565
2525 22:53:30.027615 ----->DramcWriteLeveling(PI) begin...
2526 22:53:30.027683 ==
2527 22:53:30.027785 Dram Type= 6, Freq= 0, CH_0, rank 0
2528 22:53:30.027847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2529 22:53:30.027916 ==
2530 22:53:30.027977 Write leveling (Byte 0): 33 => 33
2531 22:53:30.028031 Write leveling (Byte 1): 31 => 31
2532 22:53:30.028122 DramcWriteLeveling(PI) end<-----
2533 22:53:30.028181
2534 22:53:30.028239 ==
2535 22:53:30.028297 Dram Type= 6, Freq= 0, CH_0, rank 0
2536 22:53:30.028350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2537 22:53:30.028413 ==
2538 22:53:30.028504 [Gating] SW mode calibration
2539 22:53:30.028589 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2540 22:53:30.028696 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2541 22:53:30.028794 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2542 22:53:30.028875 0 15 4 | B1->B0 | 2c2c 3434 | 1 1 | (0 0) (1 1)
2543 22:53:30.028930 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2544 22:53:30.028988 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2545 22:53:30.029042 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2546 22:53:30.029099 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2547 22:53:30.029152 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2548 22:53:30.029217 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
2549 22:53:30.029270 1 0 0 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
2550 22:53:30.029380 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2551 22:53:30.029434 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2552 22:53:30.029486 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2553 22:53:30.029537 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2554 22:53:30.029589 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2555 22:53:30.029641 1 0 24 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
2556 22:53:30.029692 1 0 28 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
2557 22:53:30.029744 1 1 0 | B1->B0 | 3232 4646 | 1 0 | (1 1) (0 0)
2558 22:53:30.029795 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2559 22:53:30.029846 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2560 22:53:30.029897 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2561 22:53:30.029956 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2562 22:53:30.030007 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2563 22:53:30.030058 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2564 22:53:30.030110 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2565 22:53:30.030169 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2566 22:53:30.030228 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 22:53:30.030285 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 22:53:30.030337 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 22:53:30.030388 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 22:53:30.030445 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 22:53:30.030498 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 22:53:30.030549 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 22:53:30.030600 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 22:53:30.030659 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 22:53:30.030714 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2576 22:53:30.030772 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2577 22:53:30.030831 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2578 22:53:30.030892 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2579 22:53:30.030952 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2580 22:53:30.031011 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2581 22:53:30.031063 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2582 22:53:30.031114 Total UI for P1: 0, mck2ui 16
2583 22:53:30.031194 best dqsien dly found for B0: ( 1, 3, 26)
2584 22:53:30.031251 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2585 22:53:30.031304 Total UI for P1: 0, mck2ui 16
2586 22:53:30.031357 best dqsien dly found for B1: ( 1, 3, 30)
2587 22:53:30.031410 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2588 22:53:30.031462 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2589 22:53:30.031543
2590 22:53:30.031626 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2591 22:53:30.031707 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2592 22:53:30.031763 [Gating] SW calibration Done
2593 22:53:30.031817 ==
2594 22:53:30.031870 Dram Type= 6, Freq= 0, CH_0, rank 0
2595 22:53:30.032115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2596 22:53:30.032176 ==
2597 22:53:30.032230 RX Vref Scan: 0
2598 22:53:30.032283
2599 22:53:30.032335 RX Vref 0 -> 0, step: 1
2600 22:53:30.032388
2601 22:53:30.032439 RX Delay -40 -> 252, step: 8
2602 22:53:30.032492 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
2603 22:53:30.032544 iDelay=208, Bit 1, Center 123 (48 ~ 199) 152
2604 22:53:30.032596 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2605 22:53:30.032648 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2606 22:53:30.032700 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2607 22:53:30.032752 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2608 22:53:30.032804 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2609 22:53:30.032855 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2610 22:53:30.032907 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
2611 22:53:30.032958 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2612 22:53:30.033011 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2613 22:53:30.033063 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2614 22:53:30.033115 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2615 22:53:30.033166 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2616 22:53:30.033218 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2617 22:53:30.033270 iDelay=208, Bit 15, Center 119 (56 ~ 183) 128
2618 22:53:30.033357 ==
2619 22:53:30.033424 Dram Type= 6, Freq= 0, CH_0, rank 0
2620 22:53:30.033476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2621 22:53:30.033529 ==
2622 22:53:30.033581 DQS Delay:
2623 22:53:30.033633 DQS0 = 0, DQS1 = 0
2624 22:53:30.033685 DQM Delay:
2625 22:53:30.033736 DQM0 = 123, DQM1 = 110
2626 22:53:30.033788 DQ Delay:
2627 22:53:30.033841 DQ0 =123, DQ1 =123, DQ2 =119, DQ3 =119
2628 22:53:30.033892 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2629 22:53:30.033944 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2630 22:53:30.033997 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =119
2631 22:53:30.034049
2632 22:53:30.034100
2633 22:53:30.034151 ==
2634 22:53:30.034203 Dram Type= 6, Freq= 0, CH_0, rank 0
2635 22:53:30.034255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2636 22:53:30.034307 ==
2637 22:53:30.034358
2638 22:53:30.034409
2639 22:53:30.034483 TX Vref Scan disable
2640 22:53:30.034538 == TX Byte 0 ==
2641 22:53:30.034590 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2642 22:53:30.034642 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2643 22:53:30.034695 == TX Byte 1 ==
2644 22:53:30.034747 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2645 22:53:30.034799 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2646 22:53:30.034851 ==
2647 22:53:30.034903 Dram Type= 6, Freq= 0, CH_0, rank 0
2648 22:53:30.034955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2649 22:53:30.035008 ==
2650 22:53:30.035080 TX Vref=22, minBit 7, minWin=24, winSum=409
2651 22:53:30.035169 TX Vref=24, minBit 0, minWin=25, winSum=417
2652 22:53:30.035257 TX Vref=26, minBit 0, minWin=24, winSum=417
2653 22:53:30.035351 TX Vref=28, minBit 1, minWin=25, winSum=417
2654 22:53:30.035411 TX Vref=30, minBit 1, minWin=25, winSum=425
2655 22:53:30.035465 TX Vref=32, minBit 1, minWin=25, winSum=422
2656 22:53:30.035518 [TxChooseVref] Worse bit 1, Min win 25, Win sum 425, Final Vref 30
2657 22:53:30.035572
2658 22:53:30.035624 Final TX Range 1 Vref 30
2659 22:53:30.035676
2660 22:53:30.035728 ==
2661 22:53:30.035780 Dram Type= 6, Freq= 0, CH_0, rank 0
2662 22:53:30.035832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2663 22:53:30.035885 ==
2664 22:53:30.035937
2665 22:53:30.035989
2666 22:53:30.036040 TX Vref Scan disable
2667 22:53:30.036093 == TX Byte 0 ==
2668 22:53:30.036145 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2669 22:53:30.036197 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2670 22:53:30.036249 == TX Byte 1 ==
2671 22:53:30.036301 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2672 22:53:30.036353 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2673 22:53:30.036405
2674 22:53:30.036456 [DATLAT]
2675 22:53:30.036508 Freq=1200, CH0 RK0
2676 22:53:30.036560
2677 22:53:30.036612 DATLAT Default: 0xd
2678 22:53:30.036664 0, 0xFFFF, sum = 0
2679 22:53:30.036717 1, 0xFFFF, sum = 0
2680 22:53:30.036770 2, 0xFFFF, sum = 0
2681 22:53:30.036822 3, 0xFFFF, sum = 0
2682 22:53:30.036875 4, 0xFFFF, sum = 0
2683 22:53:30.036928 5, 0xFFFF, sum = 0
2684 22:53:30.036980 6, 0xFFFF, sum = 0
2685 22:53:30.037032 7, 0xFFFF, sum = 0
2686 22:53:30.037085 8, 0xFFFF, sum = 0
2687 22:53:30.037138 9, 0xFFFF, sum = 0
2688 22:53:30.037190 10, 0xFFFF, sum = 0
2689 22:53:30.037243 11, 0xFFFF, sum = 0
2690 22:53:30.037300 12, 0x0, sum = 1
2691 22:53:30.037354 13, 0x0, sum = 2
2692 22:53:30.037407 14, 0x0, sum = 3
2693 22:53:30.037459 15, 0x0, sum = 4
2694 22:53:30.037512 best_step = 13
2695 22:53:30.037564
2696 22:53:30.037616 ==
2697 22:53:30.037668 Dram Type= 6, Freq= 0, CH_0, rank 0
2698 22:53:30.037720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2699 22:53:30.037773 ==
2700 22:53:30.037825 RX Vref Scan: 1
2701 22:53:30.037877
2702 22:53:30.037928 Set Vref Range= 32 -> 127
2703 22:53:30.037980
2704 22:53:30.038031 RX Vref 32 -> 127, step: 1
2705 22:53:30.038082
2706 22:53:30.038155 RX Delay -13 -> 252, step: 4
2707 22:53:30.038210
2708 22:53:30.038263 Set Vref, RX VrefLevel [Byte0]: 32
2709 22:53:30.038315 [Byte1]: 32
2710 22:53:30.038368
2711 22:53:30.038420 Set Vref, RX VrefLevel [Byte0]: 33
2712 22:53:30.038510 [Byte1]: 33
2713 22:53:30.038593
2714 22:53:30.038665 Set Vref, RX VrefLevel [Byte0]: 34
2715 22:53:30.038720 [Byte1]: 34
2716 22:53:30.038772
2717 22:53:30.038824 Set Vref, RX VrefLevel [Byte0]: 35
2718 22:53:30.038876 [Byte1]: 35
2719 22:53:30.038928
2720 22:53:30.038980 Set Vref, RX VrefLevel [Byte0]: 36
2721 22:53:30.039032 [Byte1]: 36
2722 22:53:30.039084
2723 22:53:30.039135 Set Vref, RX VrefLevel [Byte0]: 37
2724 22:53:30.039187 [Byte1]: 37
2725 22:53:30.039238
2726 22:53:30.039290 Set Vref, RX VrefLevel [Byte0]: 38
2727 22:53:30.039341 [Byte1]: 38
2728 22:53:30.039393
2729 22:53:30.039445 Set Vref, RX VrefLevel [Byte0]: 39
2730 22:53:30.039497 [Byte1]: 39
2731 22:53:30.039548
2732 22:53:30.039599 Set Vref, RX VrefLevel [Byte0]: 40
2733 22:53:30.039651 [Byte1]: 40
2734 22:53:30.039702
2735 22:53:30.039754 Set Vref, RX VrefLevel [Byte0]: 41
2736 22:53:30.039806 [Byte1]: 41
2737 22:53:30.039858
2738 22:53:30.039908 Set Vref, RX VrefLevel [Byte0]: 42
2739 22:53:30.039960 [Byte1]: 42
2740 22:53:30.040013
2741 22:53:30.040064 Set Vref, RX VrefLevel [Byte0]: 43
2742 22:53:30.040117 [Byte1]: 43
2743 22:53:30.040168
2744 22:53:30.040220 Set Vref, RX VrefLevel [Byte0]: 44
2745 22:53:30.040272 [Byte1]: 44
2746 22:53:30.040323
2747 22:53:30.040375 Set Vref, RX VrefLevel [Byte0]: 45
2748 22:53:30.040427 [Byte1]: 45
2749 22:53:30.040478
2750 22:53:30.040530 Set Vref, RX VrefLevel [Byte0]: 46
2751 22:53:30.040582 [Byte1]: 46
2752 22:53:30.040634
2753 22:53:30.040878 Set Vref, RX VrefLevel [Byte0]: 47
2754 22:53:30.040936 [Byte1]: 47
2755 22:53:30.040990
2756 22:53:30.041042 Set Vref, RX VrefLevel [Byte0]: 48
2757 22:53:30.041094 [Byte1]: 48
2758 22:53:30.041146
2759 22:53:30.041197 Set Vref, RX VrefLevel [Byte0]: 49
2760 22:53:30.041250 [Byte1]: 49
2761 22:53:30.041337
2762 22:53:30.041424 Set Vref, RX VrefLevel [Byte0]: 50
2763 22:53:30.041478 [Byte1]: 50
2764 22:53:30.041531
2765 22:53:30.041583 Set Vref, RX VrefLevel [Byte0]: 51
2766 22:53:30.041635 [Byte1]: 51
2767 22:53:30.041688
2768 22:53:30.041740 Set Vref, RX VrefLevel [Byte0]: 52
2769 22:53:30.041815 [Byte1]: 52
2770 22:53:30.041903
2771 22:53:30.041989 Set Vref, RX VrefLevel [Byte0]: 53
2772 22:53:30.042080 [Byte1]: 53
2773 22:53:30.042138
2774 22:53:30.042191 Set Vref, RX VrefLevel [Byte0]: 54
2775 22:53:30.042244 [Byte1]: 54
2776 22:53:30.042297
2777 22:53:30.042349 Set Vref, RX VrefLevel [Byte0]: 55
2778 22:53:30.042401 [Byte1]: 55
2779 22:53:30.042452
2780 22:53:30.042504 Set Vref, RX VrefLevel [Byte0]: 56
2781 22:53:30.042556 [Byte1]: 56
2782 22:53:30.042608
2783 22:53:30.042660 Set Vref, RX VrefLevel [Byte0]: 57
2784 22:53:30.042712 [Byte1]: 57
2785 22:53:30.042763
2786 22:53:30.042814 Set Vref, RX VrefLevel [Byte0]: 58
2787 22:53:30.042866 [Byte1]: 58
2788 22:53:30.042918
2789 22:53:30.042969 Set Vref, RX VrefLevel [Byte0]: 59
2790 22:53:30.043021 [Byte1]: 59
2791 22:53:30.043072
2792 22:53:30.043123 Set Vref, RX VrefLevel [Byte0]: 60
2793 22:53:30.043175 [Byte1]: 60
2794 22:53:30.043227
2795 22:53:30.043278 Set Vref, RX VrefLevel [Byte0]: 61
2796 22:53:30.043330 [Byte1]: 61
2797 22:53:30.043381
2798 22:53:30.043433 Set Vref, RX VrefLevel [Byte0]: 62
2799 22:53:30.043485 [Byte1]: 62
2800 22:53:30.043536
2801 22:53:30.043588 Set Vref, RX VrefLevel [Byte0]: 63
2802 22:53:30.043640 [Byte1]: 63
2803 22:53:30.043692
2804 22:53:30.043743 Set Vref, RX VrefLevel [Byte0]: 64
2805 22:53:30.043794 [Byte1]: 64
2806 22:53:30.043846
2807 22:53:30.043897 Set Vref, RX VrefLevel [Byte0]: 65
2808 22:53:30.043949 [Byte1]: 65
2809 22:53:30.044000
2810 22:53:30.044052 Set Vref, RX VrefLevel [Byte0]: 66
2811 22:53:30.044103 [Byte1]: 66
2812 22:53:30.044155
2813 22:53:30.044206 Set Vref, RX VrefLevel [Byte0]: 67
2814 22:53:30.044258 [Byte1]: 67
2815 22:53:30.044310
2816 22:53:30.044361 Set Vref, RX VrefLevel [Byte0]: 68
2817 22:53:30.044434 [Byte1]: 68
2818 22:53:30.044488
2819 22:53:30.044540 Set Vref, RX VrefLevel [Byte0]: 69
2820 22:53:30.044593 [Byte1]: 69
2821 22:53:30.044644
2822 22:53:30.044696 Final RX Vref Byte 0 = 58 to rank0
2823 22:53:30.044760 Final RX Vref Byte 1 = 48 to rank0
2824 22:53:30.044848 Final RX Vref Byte 0 = 58 to rank1
2825 22:53:30.044939 Final RX Vref Byte 1 = 48 to rank1==
2826 22:53:30.045028 Dram Type= 6, Freq= 0, CH_0, rank 0
2827 22:53:30.045092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2828 22:53:30.045146 ==
2829 22:53:30.045199 DQS Delay:
2830 22:53:30.045252 DQS0 = 0, DQS1 = 0
2831 22:53:30.045312 DQM Delay:
2832 22:53:30.045403 DQM0 = 122, DQM1 = 108
2833 22:53:30.045455 DQ Delay:
2834 22:53:30.045508 DQ0 =122, DQ1 =122, DQ2 =118, DQ3 =120
2835 22:53:30.045560 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2836 22:53:30.045612 DQ8 =100, DQ9 =94, DQ10 =110, DQ11 =104
2837 22:53:30.045664 DQ12 =114, DQ13 =110, DQ14 =122, DQ15 =116
2838 22:53:30.045716
2839 22:53:30.045768
2840 22:53:30.045820 [DQSOSCAuto] RK0, (LSB)MR18= 0xb08, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 405 ps
2841 22:53:30.045873 CH0 RK0: MR19=404, MR18=B08
2842 22:53:30.045925 CH0_RK0: MR19=0x404, MR18=0xB08, DQSOSC=405, MR23=63, INC=39, DEC=26
2843 22:53:30.045978
2844 22:53:30.046029 ----->DramcWriteLeveling(PI) begin...
2845 22:53:30.046083 ==
2846 22:53:30.046135 Dram Type= 6, Freq= 0, CH_0, rank 1
2847 22:53:30.046187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2848 22:53:30.046240 ==
2849 22:53:30.046291 Write leveling (Byte 0): 34 => 34
2850 22:53:30.046344 Write leveling (Byte 1): 30 => 30
2851 22:53:30.046396 DramcWriteLeveling(PI) end<-----
2852 22:53:30.046448
2853 22:53:30.046500 ==
2854 22:53:30.046552 Dram Type= 6, Freq= 0, CH_0, rank 1
2855 22:53:30.046603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2856 22:53:30.046656 ==
2857 22:53:30.046707 [Gating] SW mode calibration
2858 22:53:30.046759 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2859 22:53:30.046812 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2860 22:53:30.046865 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2861 22:53:30.046917 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2862 22:53:30.046970 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2863 22:53:30.047023 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2864 22:53:30.047076 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2865 22:53:30.047128 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2866 22:53:30.047180 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2867 22:53:30.047232 0 15 28 | B1->B0 | 2f2f 2c2c | 1 1 | (1 0) (1 0)
2868 22:53:30.047284 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2869 22:53:30.047336 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2870 22:53:30.047388 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2871 22:53:30.047440 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2872 22:53:30.047492 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2873 22:53:30.047544 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2874 22:53:30.047617 1 0 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
2875 22:53:30.047672 1 0 28 | B1->B0 | 3f3f 4343 | 0 0 | (0 0) (0 0)
2876 22:53:30.047725 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2877 22:53:30.047777 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2878 22:53:30.047830 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2879 22:53:30.047882 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2880 22:53:30.047935 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2881 22:53:30.047987 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2882 22:53:30.048069 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2883 22:53:30.048353 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2884 22:53:30.048419 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 22:53:30.048475 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 22:53:30.048529 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 22:53:30.048583 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 22:53:30.048636 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 22:53:30.048689 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 22:53:30.048742 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 22:53:30.048794 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 22:53:30.048846 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 22:53:30.048898 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 22:53:30.048951 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 22:53:30.049003 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 22:53:30.049056 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2897 22:53:30.049109 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2898 22:53:30.049161 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2899 22:53:30.049213 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2900 22:53:30.049265 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2901 22:53:30.049362 Total UI for P1: 0, mck2ui 16
2902 22:53:30.049417 best dqsien dly found for B0: ( 1, 3, 26)
2903 22:53:30.049469 Total UI for P1: 0, mck2ui 16
2904 22:53:30.049522 best dqsien dly found for B1: ( 1, 3, 26)
2905 22:53:30.049574 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2906 22:53:30.049626 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
2907 22:53:30.049678
2908 22:53:30.049730 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2909 22:53:30.049782 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
2910 22:53:30.049834 [Gating] SW calibration Done
2911 22:53:30.049886 ==
2912 22:53:30.049938 Dram Type= 6, Freq= 0, CH_0, rank 1
2913 22:53:30.049991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2914 22:53:30.050044 ==
2915 22:53:30.050095 RX Vref Scan: 0
2916 22:53:30.050147
2917 22:53:30.050198 RX Vref 0 -> 0, step: 1
2918 22:53:30.050250
2919 22:53:30.050301 RX Delay -40 -> 252, step: 8
2920 22:53:30.050353 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2921 22:53:30.050406 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2922 22:53:30.050458 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2923 22:53:30.050510 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2924 22:53:30.050562 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2925 22:53:30.050614 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2926 22:53:30.050666 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2927 22:53:30.050717 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2928 22:53:30.050769 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2929 22:53:30.050820 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2930 22:53:30.050873 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2931 22:53:30.050933 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2932 22:53:30.050995 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2933 22:53:30.051048 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2934 22:53:30.274921 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2935 22:53:30.275425 iDelay=200, Bit 15, Center 111 (48 ~ 175) 128
2936 22:53:30.275985 ==
2937 22:53:30.276342 Dram Type= 6, Freq= 0, CH_0, rank 1
2938 22:53:30.276677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2939 22:53:30.277001 ==
2940 22:53:30.277351 DQS Delay:
2941 22:53:30.277669 DQS0 = 0, DQS1 = 0
2942 22:53:30.277976 DQM Delay:
2943 22:53:30.278279 DQM0 = 120, DQM1 = 108
2944 22:53:30.278583 DQ Delay:
2945 22:53:30.279068 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2946 22:53:30.279622 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2947 22:53:30.279992 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2948 22:53:30.280306 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2949 22:53:30.280614
2950 22:53:30.280915
2951 22:53:30.281211 ==
2952 22:53:30.281556 Dram Type= 6, Freq= 0, CH_0, rank 1
2953 22:53:30.281895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2954 22:53:30.282417 ==
2955 22:53:30.282923
2956 22:53:30.283246
2957 22:53:30.283549 TX Vref Scan disable
2958 22:53:30.283848 == TX Byte 0 ==
2959 22:53:30.284148 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2960 22:53:30.284455 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2961 22:53:30.284753 == TX Byte 1 ==
2962 22:53:30.285094 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2963 22:53:30.285639 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2964 22:53:30.286149 ==
2965 22:53:30.286475 Dram Type= 6, Freq= 0, CH_0, rank 1
2966 22:53:30.286786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2967 22:53:30.287091 ==
2968 22:53:30.287392 TX Vref=22, minBit 1, minWin=24, winSum=412
2969 22:53:30.287709 TX Vref=24, minBit 1, minWin=24, winSum=412
2970 22:53:30.287985 TX Vref=26, minBit 7, minWin=24, winSum=422
2971 22:53:30.288259 TX Vref=28, minBit 0, minWin=25, winSum=419
2972 22:53:30.288735 TX Vref=30, minBit 1, minWin=24, winSum=424
2973 22:53:30.289280 TX Vref=32, minBit 2, minWin=25, winSum=418
2974 22:53:30.289649 [TxChooseVref] Worse bit 0, Min win 25, Win sum 419, Final Vref 28
2975 22:53:30.289960
2976 22:53:30.290260 Final TX Range 1 Vref 28
2977 22:53:30.290563
2978 22:53:30.290859 ==
2979 22:53:30.291129 Dram Type= 6, Freq= 0, CH_0, rank 1
2980 22:53:30.291399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2981 22:53:30.291672 ==
2982 22:53:30.291940
2983 22:53:30.292203
2984 22:53:30.292467 TX Vref Scan disable
2985 22:53:30.292736 == TX Byte 0 ==
2986 22:53:30.293031 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2987 22:53:30.293340 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2988 22:53:30.293622 == TX Byte 1 ==
2989 22:53:30.293889 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2990 22:53:30.294161 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2991 22:53:30.294430
2992 22:53:30.294696 [DATLAT]
2993 22:53:30.294963 Freq=1200, CH0 RK1
2994 22:53:30.295350
2995 22:53:30.295767 DATLAT Default: 0xd
2996 22:53:30.296054 0, 0xFFFF, sum = 0
2997 22:53:30.296334 1, 0xFFFF, sum = 0
2998 22:53:30.296610 2, 0xFFFF, sum = 0
2999 22:53:30.296836 3, 0xFFFF, sum = 0
3000 22:53:30.297030 4, 0xFFFF, sum = 0
3001 22:53:30.297224 5, 0xFFFF, sum = 0
3002 22:53:30.297451 6, 0xFFFF, sum = 0
3003 22:53:30.297648 7, 0xFFFF, sum = 0
3004 22:53:30.297923 8, 0xFFFF, sum = 0
3005 22:53:30.298181 9, 0xFFFF, sum = 0
3006 22:53:30.298432 10, 0xFFFF, sum = 0
3007 22:53:30.298631 11, 0xFFFF, sum = 0
3008 22:53:30.298827 12, 0x0, sum = 1
3009 22:53:30.299049 13, 0x0, sum = 2
3010 22:53:30.299299 14, 0x0, sum = 3
3011 22:53:30.299497 15, 0x0, sum = 4
3012 22:53:30.299693 best_step = 13
3013 22:53:30.299884
3014 22:53:30.300072 ==
3015 22:53:30.300263 Dram Type= 6, Freq= 0, CH_0, rank 1
3016 22:53:30.300779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3017 22:53:30.300999 ==
3018 22:53:30.301195 RX Vref Scan: 0
3019 22:53:30.301435
3020 22:53:30.301633 RX Vref 0 -> 0, step: 1
3021 22:53:30.301814
3022 22:53:30.301958 RX Delay -21 -> 252, step: 4
3023 22:53:30.302116 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3024 22:53:30.302263 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3025 22:53:30.302408 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3026 22:53:30.302552 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3027 22:53:30.302713 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3028 22:53:30.302859 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3029 22:53:30.303015 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3030 22:53:30.303159 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3031 22:53:30.303303 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3032 22:53:30.303448 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3033 22:53:30.303592 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3034 22:53:30.303737 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3035 22:53:30.303881 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3036 22:53:30.304031 iDelay=195, Bit 13, Center 108 (47 ~ 170) 124
3037 22:53:30.304182 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3038 22:53:30.304331 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3039 22:53:30.304479 ==
3040 22:53:30.304638 Dram Type= 6, Freq= 0, CH_0, rank 1
3041 22:53:30.304787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3042 22:53:30.304937 ==
3043 22:53:30.305150 DQS Delay:
3044 22:53:30.305502 DQS0 = 0, DQS1 = 0
3045 22:53:30.305672 DQM Delay:
3046 22:53:30.305883 DQM0 = 119, DQM1 = 107
3047 22:53:30.306043 DQ Delay:
3048 22:53:30.306190 DQ0 =118, DQ1 =122, DQ2 =118, DQ3 =114
3049 22:53:30.306338 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =124
3050 22:53:30.306490 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =106
3051 22:53:30.306640 DQ12 =114, DQ13 =108, DQ14 =118, DQ15 =114
3052 22:53:30.306783
3053 22:53:30.306902
3054 22:53:30.307029 [DQSOSCAuto] RK1, (LSB)MR18= 0x11f8, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 403 ps
3055 22:53:30.307152 CH0 RK1: MR19=403, MR18=11F8
3056 22:53:30.307279 CH0_RK1: MR19=0x403, MR18=0x11F8, DQSOSC=403, MR23=63, INC=40, DEC=26
3057 22:53:30.307401 [RxdqsGatingPostProcess] freq 1200
3058 22:53:30.307531 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3059 22:53:30.307661 best DQS0 dly(2T, 0.5T) = (0, 11)
3060 22:53:30.307781 best DQS1 dly(2T, 0.5T) = (0, 11)
3061 22:53:30.307899 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3062 22:53:30.308017 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3063 22:53:30.308142 best DQS0 dly(2T, 0.5T) = (0, 11)
3064 22:53:30.308267 best DQS1 dly(2T, 0.5T) = (0, 11)
3065 22:53:30.308385 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3066 22:53:30.308510 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3067 22:53:30.308636 Pre-setting of DQS Precalculation
3068 22:53:30.308847 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3069 22:53:30.309016 ==
3070 22:53:30.309141 Dram Type= 6, Freq= 0, CH_1, rank 0
3071 22:53:30.309263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3072 22:53:30.309405 ==
3073 22:53:30.309526 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3074 22:53:30.309649 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3075 22:53:30.309770 [CA 0] Center 37 (7~68) winsize 62
3076 22:53:30.309914 [CA 1] Center 37 (7~68) winsize 62
3077 22:53:30.310038 [CA 2] Center 35 (5~65) winsize 61
3078 22:53:30.310195 [CA 3] Center 34 (4~65) winsize 62
3079 22:53:30.310373 [CA 4] Center 34 (3~65) winsize 63
3080 22:53:30.310558 [CA 5] Center 33 (3~64) winsize 62
3081 22:53:30.310682
3082 22:53:30.310801 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3083 22:53:30.310964
3084 22:53:30.311121 [CATrainingPosCal] consider 1 rank data
3085 22:53:30.311248 u2DelayCellTimex100 = 270/100 ps
3086 22:53:30.311369 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3087 22:53:30.311490 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3088 22:53:30.311608 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3089 22:53:30.311731 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3090 22:53:30.311831 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
3091 22:53:30.311989 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3092 22:53:30.312158
3093 22:53:30.312330 CA PerBit enable=1, Macro0, CA PI delay=33
3094 22:53:30.312444
3095 22:53:30.312545 [CBTSetCACLKResult] CA Dly = 33
3096 22:53:30.312648 CS Dly: 5 (0~36)
3097 22:53:30.312750 ==
3098 22:53:30.312850 Dram Type= 6, Freq= 0, CH_1, rank 1
3099 22:53:30.312950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3100 22:53:30.313053 ==
3101 22:53:30.313153 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3102 22:53:30.313255 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3103 22:53:30.313371 [CA 0] Center 38 (8~68) winsize 61
3104 22:53:30.313472 [CA 1] Center 38 (7~69) winsize 63
3105 22:53:30.313571 [CA 2] Center 35 (5~66) winsize 62
3106 22:53:30.313672 [CA 3] Center 35 (5~65) winsize 61
3107 22:53:30.313771 [CA 4] Center 35 (5~65) winsize 61
3108 22:53:30.313871 [CA 5] Center 34 (4~64) winsize 61
3109 22:53:30.313969
3110 22:53:30.314068 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3111 22:53:30.314168
3112 22:53:30.314266 [CATrainingPosCal] consider 2 rank data
3113 22:53:30.314366 u2DelayCellTimex100 = 270/100 ps
3114 22:53:30.314465 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3115 22:53:30.314565 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3116 22:53:30.314664 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3117 22:53:30.314764 CA3 delay=35 (5~65),Diff = 1 PI (4 cell)
3118 22:53:30.314864 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
3119 22:53:30.314963 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3120 22:53:30.315063
3121 22:53:30.315162 CA PerBit enable=1, Macro0, CA PI delay=34
3122 22:53:30.315262
3123 22:53:30.315367 [CBTSetCACLKResult] CA Dly = 34
3124 22:53:30.315534 CS Dly: 6 (0~39)
3125 22:53:30.315708
3126 22:53:30.315862 ----->DramcWriteLeveling(PI) begin...
3127 22:53:30.315973 ==
3128 22:53:30.316077 Dram Type= 6, Freq= 0, CH_1, rank 0
3129 22:53:30.316180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3130 22:53:30.316283 ==
3131 22:53:30.316384 Write leveling (Byte 0): 25 => 25
3132 22:53:30.316520 Write leveling (Byte 1): 27 => 27
3133 22:53:30.316665 DramcWriteLeveling(PI) end<-----
3134 22:53:30.316769
3135 22:53:30.316855 ==
3136 22:53:30.316941 Dram Type= 6, Freq= 0, CH_1, rank 0
3137 22:53:30.317029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3138 22:53:30.317116 ==
3139 22:53:30.317234 [Gating] SW mode calibration
3140 22:53:30.317558 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3141 22:53:30.317658 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3142 22:53:30.317749 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3143 22:53:30.317837 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3144 22:53:30.317924 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3145 22:53:30.318010 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3146 22:53:30.318097 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3147 22:53:30.318184 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3148 22:53:30.318302 0 15 24 | B1->B0 | 2b2b 2525 | 0 0 | (0 0) (0 1)
3149 22:53:30.318407 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3150 22:53:30.318532 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3151 22:53:30.318675 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3152 22:53:30.318825 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3153 22:53:30.318982 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3154 22:53:30.319079 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3155 22:53:30.319169 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3156 22:53:30.319259 1 0 24 | B1->B0 | 3d3d 4545 | 0 0 | (0 0) (0 0)
3157 22:53:30.319346 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 22:53:30.319432 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3159 22:53:30.319518 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 22:53:30.319604 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3161 22:53:30.319690 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3162 22:53:30.319775 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3163 22:53:30.319860 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3164 22:53:30.319946 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3165 22:53:30.320032 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3166 22:53:30.320118 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 22:53:30.320204 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 22:53:30.320290 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 22:53:30.320376 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 22:53:30.320462 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 22:53:30.320547 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 22:53:30.320633 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 22:53:30.320719 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 22:53:30.320804 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 22:53:30.320890 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 22:53:30.320976 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 22:53:30.321061 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 22:53:30.321147 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3179 22:53:30.321232 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3180 22:53:30.321330 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3181 22:53:30.321419 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3182 22:53:30.321505 Total UI for P1: 0, mck2ui 16
3183 22:53:30.321592 best dqsien dly found for B0: ( 1, 3, 22)
3184 22:53:30.321690 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3185 22:53:30.321764 Total UI for P1: 0, mck2ui 16
3186 22:53:30.321840 best dqsien dly found for B1: ( 1, 3, 26)
3187 22:53:30.321914 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3188 22:53:30.321990 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3189 22:53:30.322065
3190 22:53:30.322140 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3191 22:53:30.322215 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3192 22:53:30.322291 [Gating] SW calibration Done
3193 22:53:30.322365 ==
3194 22:53:30.322440 Dram Type= 6, Freq= 0, CH_1, rank 0
3195 22:53:30.322516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3196 22:53:30.322591 ==
3197 22:53:30.322666 RX Vref Scan: 0
3198 22:53:30.322743
3199 22:53:30.322817 RX Vref 0 -> 0, step: 1
3200 22:53:30.322892
3201 22:53:30.322966 RX Delay -40 -> 252, step: 8
3202 22:53:30.323042 iDelay=200, Bit 0, Center 119 (56 ~ 183) 128
3203 22:53:30.323118 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3204 22:53:30.323192 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3205 22:53:30.323268 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3206 22:53:30.323348 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3207 22:53:30.323454 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3208 22:53:30.323558 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3209 22:53:30.323635 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3210 22:53:30.323711 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3211 22:53:30.323793 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3212 22:53:30.323871 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3213 22:53:30.323960 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3214 22:53:30.324055 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3215 22:53:30.324131 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3216 22:53:30.324205 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3217 22:53:30.324280 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3218 22:53:30.324355 ==
3219 22:53:30.324430 Dram Type= 6, Freq= 0, CH_1, rank 0
3220 22:53:30.324506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3221 22:53:30.324582 ==
3222 22:53:30.324657 DQS Delay:
3223 22:53:30.324731 DQS0 = 0, DQS1 = 0
3224 22:53:30.324806 DQM Delay:
3225 22:53:30.324880 DQM0 = 119, DQM1 = 112
3226 22:53:30.324954 DQ Delay:
3227 22:53:30.325050 DQ0 =119, DQ1 =115, DQ2 =111, DQ3 =123
3228 22:53:30.325129 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =119
3229 22:53:30.325233 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3230 22:53:30.325320 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3231 22:53:30.325395
3232 22:53:30.325469
3233 22:53:30.325542 ==
3234 22:53:30.325625 Dram Type= 6, Freq= 0, CH_1, rank 0
3235 22:53:30.325721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3236 22:53:30.325799 ==
3237 22:53:30.325874
3238 22:53:30.325949
3239 22:53:30.326024 TX Vref Scan disable
3240 22:53:30.326099 == TX Byte 0 ==
3241 22:53:30.326175 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3242 22:53:30.326251 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3243 22:53:30.326325 == TX Byte 1 ==
3244 22:53:30.326610 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3245 22:53:30.326707 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3246 22:53:30.326775 ==
3247 22:53:30.326842 Dram Type= 6, Freq= 0, CH_1, rank 0
3248 22:53:30.326910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3249 22:53:30.326977 ==
3250 22:53:30.327044 TX Vref=22, minBit 1, minWin=24, winSum=404
3251 22:53:30.327112 TX Vref=24, minBit 10, minWin=24, winSum=408
3252 22:53:30.327180 TX Vref=26, minBit 1, minWin=25, winSum=414
3253 22:53:30.327247 TX Vref=28, minBit 8, minWin=25, winSum=420
3254 22:53:30.327314 TX Vref=30, minBit 10, minWin=25, winSum=422
3255 22:53:30.327381 TX Vref=32, minBit 9, minWin=25, winSum=420
3256 22:53:30.327449 [TxChooseVref] Worse bit 10, Min win 25, Win sum 422, Final Vref 30
3257 22:53:30.327515
3258 22:53:30.327582 Final TX Range 1 Vref 30
3259 22:53:30.327648
3260 22:53:30.327714 ==
3261 22:53:30.327781 Dram Type= 6, Freq= 0, CH_1, rank 0
3262 22:53:30.327847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3263 22:53:30.327915 ==
3264 22:53:30.327981
3265 22:53:30.328047
3266 22:53:30.328112 TX Vref Scan disable
3267 22:53:30.328179 == TX Byte 0 ==
3268 22:53:30.328245 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3269 22:53:30.328313 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3270 22:53:30.328379 == TX Byte 1 ==
3271 22:53:30.328446 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3272 22:53:30.328512 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3273 22:53:30.328579
3274 22:53:30.328644 [DATLAT]
3275 22:53:30.328710 Freq=1200, CH1 RK0
3276 22:53:30.328777
3277 22:53:30.328843 DATLAT Default: 0xd
3278 22:53:30.328909 0, 0xFFFF, sum = 0
3279 22:53:30.328977 1, 0xFFFF, sum = 0
3280 22:53:30.329045 2, 0xFFFF, sum = 0
3281 22:53:30.329112 3, 0xFFFF, sum = 0
3282 22:53:30.329180 4, 0xFFFF, sum = 0
3283 22:53:30.329247 5, 0xFFFF, sum = 0
3284 22:53:30.329327 6, 0xFFFF, sum = 0
3285 22:53:30.329396 7, 0xFFFF, sum = 0
3286 22:53:30.329463 8, 0xFFFF, sum = 0
3287 22:53:30.329531 9, 0xFFFF, sum = 0
3288 22:53:30.329598 10, 0xFFFF, sum = 0
3289 22:53:30.329666 11, 0xFFFF, sum = 0
3290 22:53:30.329734 12, 0x0, sum = 1
3291 22:53:30.329801 13, 0x0, sum = 2
3292 22:53:30.329869 14, 0x0, sum = 3
3293 22:53:30.329936 15, 0x0, sum = 4
3294 22:53:30.330003 best_step = 13
3295 22:53:30.330068
3296 22:53:30.330133 ==
3297 22:53:30.330198 Dram Type= 6, Freq= 0, CH_1, rank 0
3298 22:53:30.330263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3299 22:53:30.330328 ==
3300 22:53:30.330392 RX Vref Scan: 1
3301 22:53:30.330458
3302 22:53:30.330522 Set Vref Range= 32 -> 127
3303 22:53:30.330587
3304 22:53:30.330651 RX Vref 32 -> 127, step: 1
3305 22:53:30.330715
3306 22:53:30.330779 RX Delay -13 -> 252, step: 4
3307 22:53:30.330844
3308 22:53:30.330908 Set Vref, RX VrefLevel [Byte0]: 32
3309 22:53:30.330973 [Byte1]: 32
3310 22:53:30.331038
3311 22:53:30.331102 Set Vref, RX VrefLevel [Byte0]: 33
3312 22:53:30.331166 [Byte1]: 33
3313 22:53:30.331231
3314 22:53:30.331296 Set Vref, RX VrefLevel [Byte0]: 34
3315 22:53:30.331361 [Byte1]: 34
3316 22:53:30.331424
3317 22:53:30.331488 Set Vref, RX VrefLevel [Byte0]: 35
3318 22:53:30.331552 [Byte1]: 35
3319 22:53:30.331616
3320 22:53:30.331691 Set Vref, RX VrefLevel [Byte0]: 36
3321 22:53:30.331748 [Byte1]: 36
3322 22:53:30.331806
3323 22:53:30.331863 Set Vref, RX VrefLevel [Byte0]: 37
3324 22:53:30.331921 [Byte1]: 37
3325 22:53:30.331978
3326 22:53:30.332036 Set Vref, RX VrefLevel [Byte0]: 38
3327 22:53:30.332094 [Byte1]: 38
3328 22:53:30.332152
3329 22:53:30.332208 Set Vref, RX VrefLevel [Byte0]: 39
3330 22:53:30.332267 [Byte1]: 39
3331 22:53:30.332325
3332 22:53:30.332383 Set Vref, RX VrefLevel [Byte0]: 40
3333 22:53:30.332440 [Byte1]: 40
3334 22:53:30.332498
3335 22:53:30.332555 Set Vref, RX VrefLevel [Byte0]: 41
3336 22:53:30.332614 [Byte1]: 41
3337 22:53:30.332672
3338 22:53:30.332731 Set Vref, RX VrefLevel [Byte0]: 42
3339 22:53:30.332789 [Byte1]: 42
3340 22:53:30.332847
3341 22:53:30.332905 Set Vref, RX VrefLevel [Byte0]: 43
3342 22:53:30.332962 [Byte1]: 43
3343 22:53:30.333020
3344 22:53:30.333078 Set Vref, RX VrefLevel [Byte0]: 44
3345 22:53:30.333135 [Byte1]: 44
3346 22:53:30.333192
3347 22:53:30.333250 Set Vref, RX VrefLevel [Byte0]: 45
3348 22:53:30.333319 [Byte1]: 45
3349 22:53:30.333379
3350 22:53:30.333437 Set Vref, RX VrefLevel [Byte0]: 46
3351 22:53:30.333495 [Byte1]: 46
3352 22:53:30.333553
3353 22:53:30.333610 Set Vref, RX VrefLevel [Byte0]: 47
3354 22:53:30.333669 [Byte1]: 47
3355 22:53:30.333726
3356 22:53:30.333784 Set Vref, RX VrefLevel [Byte0]: 48
3357 22:53:30.333842 [Byte1]: 48
3358 22:53:30.333900
3359 22:53:30.333958 Set Vref, RX VrefLevel [Byte0]: 49
3360 22:53:30.334016 [Byte1]: 49
3361 22:53:30.334074
3362 22:53:30.334131 Set Vref, RX VrefLevel [Byte0]: 50
3363 22:53:30.334189 [Byte1]: 50
3364 22:53:30.334246
3365 22:53:30.334304 Set Vref, RX VrefLevel [Byte0]: 51
3366 22:53:30.334362 [Byte1]: 51
3367 22:53:30.334420
3368 22:53:30.334477 Set Vref, RX VrefLevel [Byte0]: 52
3369 22:53:30.334535 [Byte1]: 52
3370 22:53:30.334593
3371 22:53:30.334650 Set Vref, RX VrefLevel [Byte0]: 53
3372 22:53:30.334708 [Byte1]: 53
3373 22:53:30.334766
3374 22:53:30.334824 Set Vref, RX VrefLevel [Byte0]: 54
3375 22:53:30.334882 [Byte1]: 54
3376 22:53:30.334941
3377 22:53:30.334997 Set Vref, RX VrefLevel [Byte0]: 55
3378 22:53:30.335055 [Byte1]: 55
3379 22:53:30.335113
3380 22:53:30.335172 Set Vref, RX VrefLevel [Byte0]: 56
3381 22:53:30.335230 [Byte1]: 56
3382 22:53:30.335289
3383 22:53:30.335346 Set Vref, RX VrefLevel [Byte0]: 57
3384 22:53:30.335404 [Byte1]: 57
3385 22:53:30.335462
3386 22:53:30.335519 Set Vref, RX VrefLevel [Byte0]: 58
3387 22:53:30.335577 [Byte1]: 58
3388 22:53:30.335634
3389 22:53:30.335692 Set Vref, RX VrefLevel [Byte0]: 59
3390 22:53:30.335749 [Byte1]: 59
3391 22:53:30.335806
3392 22:53:30.335864 Set Vref, RX VrefLevel [Byte0]: 60
3393 22:53:30.335922 [Byte1]: 60
3394 22:53:30.335979
3395 22:53:30.336036 Set Vref, RX VrefLevel [Byte0]: 61
3396 22:53:30.336094 [Byte1]: 61
3397 22:53:30.336152
3398 22:53:30.336208 Set Vref, RX VrefLevel [Byte0]: 62
3399 22:53:30.336265 [Byte1]: 62
3400 22:53:30.336323
3401 22:53:30.336380 Set Vref, RX VrefLevel [Byte0]: 63
3402 22:53:30.336438 [Byte1]: 63
3403 22:53:30.336495
3404 22:53:30.336552 Set Vref, RX VrefLevel [Byte0]: 64
3405 22:53:30.336610 [Byte1]: 64
3406 22:53:30.336667
3407 22:53:30.336736 Set Vref, RX VrefLevel [Byte0]: 65
3408 22:53:30.336788 [Byte1]: 65
3409 22:53:30.336840
3410 22:53:30.337088 Set Vref, RX VrefLevel [Byte0]: 66
3411 22:53:30.337151 [Byte1]: 66
3412 22:53:30.337206
3413 22:53:30.337259 Set Vref, RX VrefLevel [Byte0]: 67
3414 22:53:30.337319 [Byte1]: 67
3415 22:53:30.337373
3416 22:53:30.337426 Final RX Vref Byte 0 = 53 to rank0
3417 22:53:30.337479 Final RX Vref Byte 1 = 50 to rank0
3418 22:53:30.337533 Final RX Vref Byte 0 = 53 to rank1
3419 22:53:30.337586 Final RX Vref Byte 1 = 50 to rank1==
3420 22:53:30.337639 Dram Type= 6, Freq= 0, CH_1, rank 0
3421 22:53:30.337693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3422 22:53:30.337746 ==
3423 22:53:30.337800 DQS Delay:
3424 22:53:30.337853 DQS0 = 0, DQS1 = 0
3425 22:53:30.337906 DQM Delay:
3426 22:53:30.337959 DQM0 = 119, DQM1 = 111
3427 22:53:30.338012 DQ Delay:
3428 22:53:30.338064 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =118
3429 22:53:30.338117 DQ4 =118, DQ5 =126, DQ6 =130, DQ7 =116
3430 22:53:30.338170 DQ8 =100, DQ9 =100, DQ10 =114, DQ11 =104
3431 22:53:30.338223 DQ12 =122, DQ13 =116, DQ14 =118, DQ15 =116
3432 22:53:30.338276
3433 22:53:30.338328
3434 22:53:30.338381 [DQSOSCAuto] RK0, (LSB)MR18= 0x61a, (MSB)MR19= 0x404, tDQSOscB0 = 400 ps tDQSOscB1 = 407 ps
3435 22:53:30.338435 CH1 RK0: MR19=404, MR18=61A
3436 22:53:30.338488 CH1_RK0: MR19=0x404, MR18=0x61A, DQSOSC=400, MR23=63, INC=40, DEC=27
3437 22:53:30.338542
3438 22:53:30.338594 ----->DramcWriteLeveling(PI) begin...
3439 22:53:30.338648 ==
3440 22:53:30.338701 Dram Type= 6, Freq= 0, CH_1, rank 1
3441 22:53:30.338755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3442 22:53:30.338808 ==
3443 22:53:30.338861 Write leveling (Byte 0): 26 => 26
3444 22:53:30.338915 Write leveling (Byte 1): 30 => 30
3445 22:53:30.338968 DramcWriteLeveling(PI) end<-----
3446 22:53:30.339021
3447 22:53:30.339073 ==
3448 22:53:30.339126 Dram Type= 6, Freq= 0, CH_1, rank 1
3449 22:53:30.339179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3450 22:53:30.339232 ==
3451 22:53:30.339285 [Gating] SW mode calibration
3452 22:53:30.339338 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3453 22:53:30.339392 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3454 22:53:30.339446 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3455 22:53:30.339500 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3456 22:53:30.339553 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3457 22:53:30.339606 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3458 22:53:30.339659 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3459 22:53:30.339712 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3460 22:53:30.339765 0 15 24 | B1->B0 | 2828 3434 | 0 0 | (0 1) (0 1)
3461 22:53:30.339817 0 15 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
3462 22:53:30.339871 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3463 22:53:30.339924 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3464 22:53:30.339977 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3465 22:53:30.340030 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3466 22:53:30.340083 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3467 22:53:30.340136 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3468 22:53:30.340189 1 0 24 | B1->B0 | 3c3c 2626 | 1 0 | (0 0) (0 0)
3469 22:53:30.340241 1 0 28 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
3470 22:53:30.340294 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3471 22:53:30.340347 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3472 22:53:30.340400 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3473 22:53:30.340453 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3474 22:53:30.340506 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3475 22:53:30.340558 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3476 22:53:30.340611 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3477 22:53:30.340664 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3478 22:53:30.340717 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 22:53:30.340769 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 22:53:30.340822 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 22:53:30.340874 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 22:53:30.340927 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 22:53:30.340979 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 22:53:30.341032 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 22:53:30.341085 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 22:53:30.341138 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 22:53:30.341192 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 22:53:30.341244 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 22:53:30.341301 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 22:53:30.341355 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 22:53:30.341408 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 22:53:30.341461 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3493 22:53:30.341514 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3494 22:53:30.341566 Total UI for P1: 0, mck2ui 16
3495 22:53:30.341620 best dqsien dly found for B0: ( 1, 3, 24)
3496 22:53:30.341673 Total UI for P1: 0, mck2ui 16
3497 22:53:30.341739 best dqsien dly found for B1: ( 1, 3, 24)
3498 22:53:30.341791 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3499 22:53:30.341843 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3500 22:53:30.341894
3501 22:53:30.341946 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3502 22:53:30.341998 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3503 22:53:30.342050 [Gating] SW calibration Done
3504 22:53:30.342101 ==
3505 22:53:30.342153 Dram Type= 6, Freq= 0, CH_1, rank 1
3506 22:53:30.342204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3507 22:53:30.342257 ==
3508 22:53:30.342308 RX Vref Scan: 0
3509 22:53:30.342360
3510 22:53:30.342411 RX Vref 0 -> 0, step: 1
3511 22:53:30.342463
3512 22:53:30.342515 RX Delay -40 -> 252, step: 8
3513 22:53:30.342566 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3514 22:53:30.342619 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3515 22:53:30.342670 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3516 22:53:30.342722 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3517 22:53:30.342963 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3518 22:53:30.343022 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3519 22:53:30.343074 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3520 22:53:30.343127 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3521 22:53:30.343178 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3522 22:53:30.343231 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3523 22:53:30.343283 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3524 22:53:30.343335 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3525 22:53:30.343387 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3526 22:53:30.343439 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3527 22:53:30.343490 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3528 22:53:30.343542 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3529 22:53:30.343593 ==
3530 22:53:30.343645 Dram Type= 6, Freq= 0, CH_1, rank 1
3531 22:53:30.343697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3532 22:53:30.343750 ==
3533 22:53:30.343801 DQS Delay:
3534 22:53:30.343853 DQS0 = 0, DQS1 = 0
3535 22:53:30.343915 DQM Delay:
3536 22:53:30.343974 DQM0 = 120, DQM1 = 114
3537 22:53:30.344042 DQ Delay:
3538 22:53:30.344101 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =123
3539 22:53:30.344160 DQ4 =119, DQ5 =131, DQ6 =123, DQ7 =115
3540 22:53:30.344220 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107
3541 22:53:30.344280 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =123
3542 22:53:30.344334
3543 22:53:30.344386
3544 22:53:30.344444 ==
3545 22:53:30.344496 Dram Type= 6, Freq= 0, CH_1, rank 1
3546 22:53:30.344554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3547 22:53:30.344613 ==
3548 22:53:30.344672
3549 22:53:30.344723
3550 22:53:30.344781 TX Vref Scan disable
3551 22:53:30.344841 == TX Byte 0 ==
3552 22:53:30.344893 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3553 22:53:30.344954 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3554 22:53:30.345014 == TX Byte 1 ==
3555 22:53:30.345080 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3556 22:53:30.345134 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3557 22:53:30.345193 ==
3558 22:53:30.345247 Dram Type= 6, Freq= 0, CH_1, rank 1
3559 22:53:30.345303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3560 22:53:30.345357 ==
3561 22:53:30.345409 TX Vref=22, minBit 1, minWin=25, winSum=416
3562 22:53:30.345474 TX Vref=24, minBit 1, minWin=25, winSum=421
3563 22:53:30.345535 TX Vref=26, minBit 1, minWin=26, winSum=424
3564 22:53:30.345595 TX Vref=28, minBit 3, minWin=26, winSum=427
3565 22:53:30.345655 TX Vref=30, minBit 1, minWin=26, winSum=429
3566 22:53:30.345718 TX Vref=32, minBit 7, minWin=26, winSum=428
3567 22:53:30.345773 [TxChooseVref] Worse bit 1, Min win 26, Win sum 429, Final Vref 30
3568 22:53:30.345825
3569 22:53:30.345883 Final TX Range 1 Vref 30
3570 22:53:30.345936
3571 22:53:30.345987 ==
3572 22:53:30.346039 Dram Type= 6, Freq= 0, CH_1, rank 1
3573 22:53:30.346091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3574 22:53:30.346149 ==
3575 22:53:30.346206
3576 22:53:30.346267
3577 22:53:30.346321 TX Vref Scan disable
3578 22:53:30.346390 == TX Byte 0 ==
3579 22:53:30.346449 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3580 22:53:30.346509 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3581 22:53:30.346574 == TX Byte 1 ==
3582 22:53:30.346634 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3583 22:53:30.346693 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3584 22:53:30.346747
3585 22:53:30.346799 [DATLAT]
3586 22:53:30.346856 Freq=1200, CH1 RK1
3587 22:53:30.346915
3588 22:53:30.346967 DATLAT Default: 0xd
3589 22:53:30.347019 0, 0xFFFF, sum = 0
3590 22:53:30.347084 1, 0xFFFF, sum = 0
3591 22:53:30.347143 2, 0xFFFF, sum = 0
3592 22:53:30.347202 3, 0xFFFF, sum = 0
3593 22:53:30.347264 4, 0xFFFF, sum = 0
3594 22:53:30.347330 5, 0xFFFF, sum = 0
3595 22:53:30.347391 6, 0xFFFF, sum = 0
3596 22:53:30.347446 7, 0xFFFF, sum = 0
3597 22:53:30.347499 8, 0xFFFF, sum = 0
3598 22:53:30.347551 9, 0xFFFF, sum = 0
3599 22:53:30.347603 10, 0xFFFF, sum = 0
3600 22:53:30.347656 11, 0xFFFF, sum = 0
3601 22:53:30.347709 12, 0x0, sum = 1
3602 22:53:30.347762 13, 0x0, sum = 2
3603 22:53:30.347814 14, 0x0, sum = 3
3604 22:53:30.347867 15, 0x0, sum = 4
3605 22:53:30.347919 best_step = 13
3606 22:53:30.347970
3607 22:53:30.348021 ==
3608 22:53:30.348073 Dram Type= 6, Freq= 0, CH_1, rank 1
3609 22:53:30.348125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3610 22:53:30.348178 ==
3611 22:53:30.348229 RX Vref Scan: 0
3612 22:53:30.348281
3613 22:53:30.348332 RX Vref 0 -> 0, step: 1
3614 22:53:30.348384
3615 22:53:30.348435 RX Delay -13 -> 252, step: 4
3616 22:53:30.348487 iDelay=191, Bit 0, Center 122 (63 ~ 182) 120
3617 22:53:30.348539 iDelay=191, Bit 1, Center 114 (55 ~ 174) 120
3618 22:53:30.348590 iDelay=191, Bit 2, Center 108 (51 ~ 166) 116
3619 22:53:30.348642 iDelay=191, Bit 3, Center 118 (59 ~ 178) 120
3620 22:53:30.348694 iDelay=191, Bit 4, Center 122 (63 ~ 182) 120
3621 22:53:30.348746 iDelay=191, Bit 5, Center 128 (67 ~ 190) 124
3622 22:53:30.348798 iDelay=191, Bit 6, Center 126 (67 ~ 186) 120
3623 22:53:30.348850 iDelay=191, Bit 7, Center 116 (55 ~ 178) 124
3624 22:53:30.348902 iDelay=191, Bit 8, Center 98 (35 ~ 162) 128
3625 22:53:30.348954 iDelay=191, Bit 9, Center 100 (35 ~ 166) 132
3626 22:53:30.349005 iDelay=191, Bit 10, Center 114 (51 ~ 178) 128
3627 22:53:30.349057 iDelay=191, Bit 11, Center 106 (43 ~ 170) 128
3628 22:53:30.349109 iDelay=191, Bit 12, Center 122 (59 ~ 186) 128
3629 22:53:30.349161 iDelay=191, Bit 13, Center 118 (55 ~ 182) 128
3630 22:53:30.349213 iDelay=191, Bit 14, Center 122 (59 ~ 186) 128
3631 22:53:30.349265 iDelay=191, Bit 15, Center 122 (59 ~ 186) 128
3632 22:53:30.349352 ==
3633 22:53:30.349418 Dram Type= 6, Freq= 0, CH_1, rank 1
3634 22:53:30.349471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3635 22:53:30.349523 ==
3636 22:53:30.349574 DQS Delay:
3637 22:53:30.349625 DQS0 = 0, DQS1 = 0
3638 22:53:30.349677 DQM Delay:
3639 22:53:30.349728 DQM0 = 119, DQM1 = 112
3640 22:53:30.349780 DQ Delay:
3641 22:53:30.349831 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =118
3642 22:53:30.349883 DQ4 =122, DQ5 =128, DQ6 =126, DQ7 =116
3643 22:53:30.349935 DQ8 =98, DQ9 =100, DQ10 =114, DQ11 =106
3644 22:53:30.349986 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =122
3645 22:53:30.350037
3646 22:53:30.350088
3647 22:53:30.350139 [DQSOSCAuto] RK1, (LSB)MR18= 0xdf2, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 405 ps
3648 22:53:30.350192 CH1 RK1: MR19=403, MR18=DF2
3649 22:53:30.350243 CH1_RK1: MR19=0x403, MR18=0xDF2, DQSOSC=405, MR23=63, INC=39, DEC=26
3650 22:53:30.350295 [RxdqsGatingPostProcess] freq 1200
3651 22:53:30.350347 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3652 22:53:30.350399 best DQS0 dly(2T, 0.5T) = (0, 11)
3653 22:53:30.350451 best DQS1 dly(2T, 0.5T) = (0, 11)
3654 22:53:30.350503 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3655 22:53:30.350748 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3656 22:53:30.350807 best DQS0 dly(2T, 0.5T) = (0, 11)
3657 22:53:30.350860 best DQS1 dly(2T, 0.5T) = (0, 11)
3658 22:53:30.350913 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3659 22:53:30.350966 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3660 22:53:30.351018 Pre-setting of DQS Precalculation
3661 22:53:30.351070 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3662 22:53:30.351122 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3663 22:53:30.351175 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3664 22:53:30.351227
3665 22:53:30.351278
3666 22:53:30.351330 [Calibration Summary] 2400 Mbps
3667 22:53:30.351381 CH 0, Rank 0
3668 22:53:30.351433 SW Impedance : PASS
3669 22:53:30.351485 DUTY Scan : NO K
3670 22:53:30.351536 ZQ Calibration : PASS
3671 22:53:30.351588 Jitter Meter : NO K
3672 22:53:30.351639 CBT Training : PASS
3673 22:53:30.351691 Write leveling : PASS
3674 22:53:30.351742 RX DQS gating : PASS
3675 22:53:30.351794 RX DQ/DQS(RDDQC) : PASS
3676 22:53:30.351845 TX DQ/DQS : PASS
3677 22:53:30.351897 RX DATLAT : PASS
3678 22:53:30.351947 RX DQ/DQS(Engine): PASS
3679 22:53:30.351998 TX OE : NO K
3680 22:53:30.352051 All Pass.
3681 22:53:30.352102
3682 22:53:30.352154 CH 0, Rank 1
3683 22:53:30.352205 SW Impedance : PASS
3684 22:53:30.352256 DUTY Scan : NO K
3685 22:53:30.352308 ZQ Calibration : PASS
3686 22:53:30.352359 Jitter Meter : NO K
3687 22:53:30.352410 CBT Training : PASS
3688 22:53:30.352462 Write leveling : PASS
3689 22:53:30.352514 RX DQS gating : PASS
3690 22:53:30.352565 RX DQ/DQS(RDDQC) : PASS
3691 22:53:30.352616 TX DQ/DQS : PASS
3692 22:53:30.352668 RX DATLAT : PASS
3693 22:53:30.352720 RX DQ/DQS(Engine): PASS
3694 22:53:30.352771 TX OE : NO K
3695 22:53:30.352823 All Pass.
3696 22:53:30.352874
3697 22:53:30.352925 CH 1, Rank 0
3698 22:53:30.352976 SW Impedance : PASS
3699 22:53:30.353027 DUTY Scan : NO K
3700 22:53:30.353079 ZQ Calibration : PASS
3701 22:53:30.353131 Jitter Meter : NO K
3702 22:53:30.353183 CBT Training : PASS
3703 22:53:30.353235 Write leveling : PASS
3704 22:53:30.353287 RX DQS gating : PASS
3705 22:53:30.353376 RX DQ/DQS(RDDQC) : PASS
3706 22:53:30.353428 TX DQ/DQS : PASS
3707 22:53:30.353484 RX DATLAT : PASS
3708 22:53:30.353536 RX DQ/DQS(Engine): PASS
3709 22:53:30.353588 TX OE : NO K
3710 22:53:30.353640 All Pass.
3711 22:53:30.353691
3712 22:53:30.353742 CH 1, Rank 1
3713 22:53:30.353794 SW Impedance : PASS
3714 22:53:30.353845 DUTY Scan : NO K
3715 22:53:30.353897 ZQ Calibration : PASS
3716 22:53:30.353948 Jitter Meter : NO K
3717 22:53:30.354000 CBT Training : PASS
3718 22:53:30.354051 Write leveling : PASS
3719 22:53:30.354103 RX DQS gating : PASS
3720 22:53:30.354154 RX DQ/DQS(RDDQC) : PASS
3721 22:53:30.354206 TX DQ/DQS : PASS
3722 22:53:30.354258 RX DATLAT : PASS
3723 22:53:30.354310 RX DQ/DQS(Engine): PASS
3724 22:53:30.354361 TX OE : NO K
3725 22:53:30.354413 All Pass.
3726 22:53:30.354464
3727 22:53:30.354515 DramC Write-DBI off
3728 22:53:30.354566 PER_BANK_REFRESH: Hybrid Mode
3729 22:53:30.354618 TX_TRACKING: ON
3730 22:53:30.354670 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3731 22:53:30.354723 [FAST_K] Save calibration result to emmc
3732 22:53:30.354775 dramc_set_vcore_voltage set vcore to 650000
3733 22:53:30.354826 Read voltage for 600, 5
3734 22:53:30.354878 Vio18 = 0
3735 22:53:30.354930 Vcore = 650000
3736 22:53:30.354982 Vdram = 0
3737 22:53:30.355033 Vddq = 0
3738 22:53:30.355085 Vmddr = 0
3739 22:53:30.355136 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3740 22:53:30.355189 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3741 22:53:30.355241 MEM_TYPE=3, freq_sel=19
3742 22:53:30.355293 sv_algorithm_assistance_LP4_1600
3743 22:53:30.355346 ============ PULL DRAM RESETB DOWN ============
3744 22:53:30.355398 ========== PULL DRAM RESETB DOWN end =========
3745 22:53:30.355451 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3746 22:53:30.355503 ===================================
3747 22:53:30.355555 LPDDR4 DRAM CONFIGURATION
3748 22:53:30.355606 ===================================
3749 22:53:30.355658 EX_ROW_EN[0] = 0x0
3750 22:53:30.355710 EX_ROW_EN[1] = 0x0
3751 22:53:30.355761 LP4Y_EN = 0x0
3752 22:53:30.355813 WORK_FSP = 0x0
3753 22:53:30.355864 WL = 0x2
3754 22:53:30.355915 RL = 0x2
3755 22:53:30.355967 BL = 0x2
3756 22:53:30.356018 RPST = 0x0
3757 22:53:30.356069 RD_PRE = 0x0
3758 22:53:30.356121 WR_PRE = 0x1
3759 22:53:30.356172 WR_PST = 0x0
3760 22:53:30.356223 DBI_WR = 0x0
3761 22:53:30.356275 DBI_RD = 0x0
3762 22:53:30.356325 OTF = 0x1
3763 22:53:30.356377 ===================================
3764 22:53:30.356429 ===================================
3765 22:53:30.356481 ANA top config
3766 22:53:30.356532 ===================================
3767 22:53:30.356585 DLL_ASYNC_EN = 0
3768 22:53:30.356637 ALL_SLAVE_EN = 1
3769 22:53:30.356688 NEW_RANK_MODE = 1
3770 22:53:30.356741 DLL_IDLE_MODE = 1
3771 22:53:30.356792 LP45_APHY_COMB_EN = 1
3772 22:53:30.356844 TX_ODT_DIS = 1
3773 22:53:30.356896 NEW_8X_MODE = 1
3774 22:53:30.356948 ===================================
3775 22:53:30.357000 ===================================
3776 22:53:30.357052 data_rate = 1200
3777 22:53:30.357104 CKR = 1
3778 22:53:30.357156 DQ_P2S_RATIO = 8
3779 22:53:30.357208 ===================================
3780 22:53:30.357260 CA_P2S_RATIO = 8
3781 22:53:30.357316 DQ_CA_OPEN = 0
3782 22:53:30.357408 DQ_SEMI_OPEN = 0
3783 22:53:30.357460 CA_SEMI_OPEN = 0
3784 22:53:30.357512 CA_FULL_RATE = 0
3785 22:53:30.357564 DQ_CKDIV4_EN = 1
3786 22:53:30.357615 CA_CKDIV4_EN = 1
3787 22:53:30.357666 CA_PREDIV_EN = 0
3788 22:53:30.357718 PH8_DLY = 0
3789 22:53:30.357769 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3790 22:53:30.357821 DQ_AAMCK_DIV = 4
3791 22:53:30.357872 CA_AAMCK_DIV = 4
3792 22:53:30.357924 CA_ADMCK_DIV = 4
3793 22:53:30.357975 DQ_TRACK_CA_EN = 0
3794 22:53:30.358027 CA_PICK = 600
3795 22:53:30.358079 CA_MCKIO = 600
3796 22:53:30.358130 MCKIO_SEMI = 0
3797 22:53:30.358182 PLL_FREQ = 2288
3798 22:53:30.358233 DQ_UI_PI_RATIO = 32
3799 22:53:30.358285 CA_UI_PI_RATIO = 0
3800 22:53:30.358337 ===================================
3801 22:53:30.358580 ===================================
3802 22:53:30.358642 memory_type:LPDDR4
3803 22:53:30.358696 GP_NUM : 10
3804 22:53:30.358748 SRAM_EN : 1
3805 22:53:30.358800 MD32_EN : 0
3806 22:53:30.358852 ===================================
3807 22:53:30.358905 [ANA_INIT] >>>>>>>>>>>>>>
3808 22:53:30.358957 <<<<<< [CONFIGURE PHASE]: ANA_TX
3809 22:53:30.359010 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3810 22:53:30.359062 ===================================
3811 22:53:30.359114 data_rate = 1200,PCW = 0X5800
3812 22:53:30.359166 ===================================
3813 22:53:30.359218 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3814 22:53:30.359270 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3815 22:53:30.359322 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3816 22:53:30.359374 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3817 22:53:30.359427 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3818 22:53:30.359479 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3819 22:53:30.359531 [ANA_INIT] flow start
3820 22:53:30.359582 [ANA_INIT] PLL >>>>>>>>
3821 22:53:30.359634 [ANA_INIT] PLL <<<<<<<<
3822 22:53:30.359686 [ANA_INIT] MIDPI >>>>>>>>
3823 22:53:30.359738 [ANA_INIT] MIDPI <<<<<<<<
3824 22:53:30.359790 [ANA_INIT] DLL >>>>>>>>
3825 22:53:30.359841 [ANA_INIT] flow end
3826 22:53:30.359893 ============ LP4 DIFF to SE enter ============
3827 22:53:30.359946 ============ LP4 DIFF to SE exit ============
3828 22:53:30.359998 [ANA_INIT] <<<<<<<<<<<<<
3829 22:53:30.360050 [Flow] Enable top DCM control >>>>>
3830 22:53:30.360102 [Flow] Enable top DCM control <<<<<
3831 22:53:30.360153 Enable DLL master slave shuffle
3832 22:53:30.360205 ==============================================================
3833 22:53:30.360257 Gating Mode config
3834 22:53:30.360309 ==============================================================
3835 22:53:30.360361 Config description:
3836 22:53:30.360414 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3837 22:53:30.360467 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3838 22:53:30.360519 SELPH_MODE 0: By rank 1: By Phase
3839 22:53:30.360571 ==============================================================
3840 22:53:30.360624 GAT_TRACK_EN = 1
3841 22:53:30.360675 RX_GATING_MODE = 2
3842 22:53:30.360726 RX_GATING_TRACK_MODE = 2
3843 22:53:30.360778 SELPH_MODE = 1
3844 22:53:30.360830 PICG_EARLY_EN = 1
3845 22:53:30.360881 VALID_LAT_VALUE = 1
3846 22:53:30.360933 ==============================================================
3847 22:53:30.360985 Enter into Gating configuration >>>>
3848 22:53:30.361037 Exit from Gating configuration <<<<
3849 22:53:30.361088 Enter into DVFS_PRE_config >>>>>
3850 22:53:30.361140 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3851 22:53:30.361193 Exit from DVFS_PRE_config <<<<<
3852 22:53:30.361245 Enter into PICG configuration >>>>
3853 22:53:30.361302 Exit from PICG configuration <<<<
3854 22:53:30.361354 [RX_INPUT] configuration >>>>>
3855 22:53:30.361406 [RX_INPUT] configuration <<<<<
3856 22:53:30.361457 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3857 22:53:30.361510 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3858 22:53:30.361575 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3859 22:53:30.363537 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3860 22:53:30.370326 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3861 22:53:30.377150 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3862 22:53:30.380587 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3863 22:53:30.383891 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3864 22:53:30.390371 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3865 22:53:30.393737 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3866 22:53:30.396988 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3867 22:53:30.403496 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3868 22:53:30.406867 ===================================
3869 22:53:30.407032 LPDDR4 DRAM CONFIGURATION
3870 22:53:30.410293 ===================================
3871 22:53:30.413475 EX_ROW_EN[0] = 0x0
3872 22:53:30.413628 EX_ROW_EN[1] = 0x0
3873 22:53:30.417313 LP4Y_EN = 0x0
3874 22:53:30.417488 WORK_FSP = 0x0
3875 22:53:30.420358 WL = 0x2
3876 22:53:30.423770 RL = 0x2
3877 22:53:30.423956 BL = 0x2
3878 22:53:30.426938 RPST = 0x0
3879 22:53:30.427147 RD_PRE = 0x0
3880 22:53:30.430617 WR_PRE = 0x1
3881 22:53:30.430814 WR_PST = 0x0
3882 22:53:30.433813 DBI_WR = 0x0
3883 22:53:30.434026 DBI_RD = 0x0
3884 22:53:30.437264 OTF = 0x1
3885 22:53:30.440617 ===================================
3886 22:53:30.443895 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3887 22:53:30.447339 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3888 22:53:30.450218 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3889 22:53:30.453690 ===================================
3890 22:53:30.457636 LPDDR4 DRAM CONFIGURATION
3891 22:53:30.460513 ===================================
3892 22:53:30.463820 EX_ROW_EN[0] = 0x10
3893 22:53:30.464261 EX_ROW_EN[1] = 0x0
3894 22:53:30.467514 LP4Y_EN = 0x0
3895 22:53:30.468008 WORK_FSP = 0x0
3896 22:53:30.470332 WL = 0x2
3897 22:53:30.470742 RL = 0x2
3898 22:53:30.473620 BL = 0x2
3899 22:53:30.474030 RPST = 0x0
3900 22:53:30.476775 RD_PRE = 0x0
3901 22:53:30.477184 WR_PRE = 0x1
3902 22:53:30.480376 WR_PST = 0x0
3903 22:53:30.484080 DBI_WR = 0x0
3904 22:53:30.484592 DBI_RD = 0x0
3905 22:53:30.486859 OTF = 0x1
3906 22:53:30.490135 ===================================
3907 22:53:30.493722 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3908 22:53:30.498779 nWR fixed to 30
3909 22:53:30.502535 [ModeRegInit_LP4] CH0 RK0
3910 22:53:30.502949 [ModeRegInit_LP4] CH0 RK1
3911 22:53:30.505344 [ModeRegInit_LP4] CH1 RK0
3912 22:53:30.508779 [ModeRegInit_LP4] CH1 RK1
3913 22:53:30.509188 match AC timing 17
3914 22:53:30.515561 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3915 22:53:30.518639 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3916 22:53:30.522362 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3917 22:53:30.529236 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3918 22:53:30.532632 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3919 22:53:30.533148 ==
3920 22:53:30.535601 Dram Type= 6, Freq= 0, CH_0, rank 0
3921 22:53:30.539084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3922 22:53:30.539612 ==
3923 22:53:30.545772 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3924 22:53:30.552268 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3925 22:53:30.555791 [CA 0] Center 36 (6~67) winsize 62
3926 22:53:30.558987 [CA 1] Center 36 (6~67) winsize 62
3927 22:53:30.562388 [CA 2] Center 34 (4~65) winsize 62
3928 22:53:30.565958 [CA 3] Center 34 (3~65) winsize 63
3929 22:53:30.568707 [CA 4] Center 33 (3~64) winsize 62
3930 22:53:30.572232 [CA 5] Center 33 (2~64) winsize 63
3931 22:53:30.572656
3932 22:53:30.575400 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3933 22:53:30.575822
3934 22:53:30.578829 [CATrainingPosCal] consider 1 rank data
3935 22:53:30.581781 u2DelayCellTimex100 = 270/100 ps
3936 22:53:30.585737 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3937 22:53:30.588832 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3938 22:53:30.591871 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3939 22:53:30.595559 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3940 22:53:30.598818 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3941 22:53:30.601958 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
3942 22:53:30.605158
3943 22:53:30.608583 CA PerBit enable=1, Macro0, CA PI delay=33
3944 22:53:30.609005
3945 22:53:30.612297 [CBTSetCACLKResult] CA Dly = 33
3946 22:53:30.612720 CS Dly: 6 (0~37)
3947 22:53:30.613056 ==
3948 22:53:30.615506 Dram Type= 6, Freq= 0, CH_0, rank 1
3949 22:53:30.618236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3950 22:53:30.618664 ==
3951 22:53:30.625315 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3952 22:53:30.631851 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3953 22:53:30.635456 [CA 0] Center 36 (6~67) winsize 62
3954 22:53:30.638747 [CA 1] Center 36 (6~67) winsize 62
3955 22:53:30.641782 [CA 2] Center 35 (5~66) winsize 62
3956 22:53:30.645434 [CA 3] Center 35 (4~66) winsize 63
3957 22:53:30.648498 [CA 4] Center 34 (3~65) winsize 63
3958 22:53:30.651997 [CA 5] Center 33 (3~64) winsize 62
3959 22:53:30.652521
3960 22:53:30.655123 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3961 22:53:30.655547
3962 22:53:30.658487 [CATrainingPosCal] consider 2 rank data
3963 22:53:30.661912 u2DelayCellTimex100 = 270/100 ps
3964 22:53:30.665066 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3965 22:53:30.668246 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3966 22:53:30.671877 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
3967 22:53:30.675104 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3968 22:53:30.682153 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3969 22:53:30.685236 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3970 22:53:30.685653
3971 22:53:30.688073 CA PerBit enable=1, Macro0, CA PI delay=33
3972 22:53:30.688498
3973 22:53:30.691642 [CBTSetCACLKResult] CA Dly = 33
3974 22:53:30.692048 CS Dly: 5 (0~36)
3975 22:53:30.692383
3976 22:53:30.695031 ----->DramcWriteLeveling(PI) begin...
3977 22:53:30.695460 ==
3978 22:53:30.698423 Dram Type= 6, Freq= 0, CH_0, rank 0
3979 22:53:30.704941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3980 22:53:30.705424 ==
3981 22:53:30.708144 Write leveling (Byte 0): 33 => 33
3982 22:53:30.711465 Write leveling (Byte 1): 33 => 33
3983 22:53:30.711888 DramcWriteLeveling(PI) end<-----
3984 22:53:30.712271
3985 22:53:30.714489 ==
3986 22:53:30.717805 Dram Type= 6, Freq= 0, CH_0, rank 0
3987 22:53:30.721350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3988 22:53:30.721774 ==
3989 22:53:30.724828 [Gating] SW mode calibration
3990 22:53:30.731222 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3991 22:53:30.734552 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3992 22:53:30.741238 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3993 22:53:30.745146 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3994 22:53:30.748197 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3995 22:53:30.755022 0 9 12 | B1->B0 | 3232 2c2c | 0 0 | (0 0) (0 0)
3996 22:53:30.758254 0 9 16 | B1->B0 | 2b2b 2323 | 1 0 | (1 1) (0 0)
3997 22:53:30.761673 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3998 22:53:30.768328 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3999 22:53:30.771588 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4000 22:53:30.774812 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4001 22:53:30.781225 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4002 22:53:30.784677 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4003 22:53:30.787919 0 10 12 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
4004 22:53:30.791332 0 10 16 | B1->B0 | 3e3e 4646 | 0 0 | (1 1) (0 0)
4005 22:53:30.798188 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4006 22:53:30.800999 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4007 22:53:30.804500 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4008 22:53:30.811108 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4009 22:53:30.814162 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4010 22:53:30.817578 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4011 22:53:30.824532 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4012 22:53:30.827566 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4013 22:53:30.831054 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 22:53:30.837734 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 22:53:30.840784 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 22:53:30.844628 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 22:53:30.851112 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 22:53:30.854337 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 22:53:30.857495 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 22:53:30.864307 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 22:53:30.867916 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 22:53:30.870911 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 22:53:30.877722 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 22:53:30.881255 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 22:53:30.884750 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 22:53:30.891063 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 22:53:30.894301 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4028 22:53:30.897554 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4029 22:53:30.900919 Total UI for P1: 0, mck2ui 16
4030 22:53:30.904482 best dqsien dly found for B0: ( 0, 13, 12)
4031 22:53:30.907797 Total UI for P1: 0, mck2ui 16
4032 22:53:30.911071 best dqsien dly found for B1: ( 0, 13, 12)
4033 22:53:30.914129 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4034 22:53:30.917184 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4035 22:53:30.917704
4036 22:53:30.923986 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4037 22:53:30.927354 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4038 22:53:30.927826 [Gating] SW calibration Done
4039 22:53:30.930714 ==
4040 22:53:30.933873 Dram Type= 6, Freq= 0, CH_0, rank 0
4041 22:53:30.937293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4042 22:53:30.937863 ==
4043 22:53:30.938232 RX Vref Scan: 0
4044 22:53:30.938572
4045 22:53:30.940532 RX Vref 0 -> 0, step: 1
4046 22:53:30.940999
4047 22:53:30.944435 RX Delay -230 -> 252, step: 16
4048 22:53:30.947467 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4049 22:53:30.950664 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4050 22:53:30.957329 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4051 22:53:30.960688 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4052 22:53:30.964003 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4053 22:53:30.967435 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4054 22:53:30.970655 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4055 22:53:30.977605 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4056 22:53:30.980706 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4057 22:53:30.984531 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4058 22:53:30.987534 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4059 22:53:30.994459 iDelay=218, Bit 11, Center 41 (-102 ~ 185) 288
4060 22:53:30.997524 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4061 22:53:31.000690 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4062 22:53:31.003882 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4063 22:53:31.007767 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4064 22:53:31.010568 ==
4065 22:53:31.013967 Dram Type= 6, Freq= 0, CH_0, rank 0
4066 22:53:31.017219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4067 22:53:31.017740 ==
4068 22:53:31.018108 DQS Delay:
4069 22:53:31.020956 DQS0 = 0, DQS1 = 0
4070 22:53:31.021569 DQM Delay:
4071 22:53:31.023956 DQM0 = 53, DQM1 = 44
4072 22:53:31.024606 DQ Delay:
4073 22:53:31.027617 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4074 22:53:31.030847 DQ4 =57, DQ5 =49, DQ6 =57, DQ7 =57
4075 22:53:31.034465 DQ8 =33, DQ9 =25, DQ10 =49, DQ11 =41
4076 22:53:31.037732 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4077 22:53:31.038289
4078 22:53:31.038658
4079 22:53:31.038997 ==
4080 22:53:31.040753 Dram Type= 6, Freq= 0, CH_0, rank 0
4081 22:53:31.044520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4082 22:53:31.045091 ==
4083 22:53:31.045526
4084 22:53:31.045878
4085 22:53:31.047271 TX Vref Scan disable
4086 22:53:31.051045 == TX Byte 0 ==
4087 22:53:31.053856 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4088 22:53:31.057644 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4089 22:53:31.061091 == TX Byte 1 ==
4090 22:53:31.063795 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4091 22:53:31.067770 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4092 22:53:31.068336 ==
4093 22:53:31.070701 Dram Type= 6, Freq= 0, CH_0, rank 0
4094 22:53:31.074038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4095 22:53:31.077234 ==
4096 22:53:31.077807
4097 22:53:31.078176
4098 22:53:31.078518 TX Vref Scan disable
4099 22:53:31.081172 == TX Byte 0 ==
4100 22:53:31.084530 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4101 22:53:31.091452 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4102 22:53:31.092014 == TX Byte 1 ==
4103 22:53:31.094293 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4104 22:53:31.101483 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4105 22:53:31.102047
4106 22:53:31.102417 [DATLAT]
4107 22:53:31.102766 Freq=600, CH0 RK0
4108 22:53:31.103100
4109 22:53:31.104472 DATLAT Default: 0x9
4110 22:53:31.104983 0, 0xFFFF, sum = 0
4111 22:53:31.107490 1, 0xFFFF, sum = 0
4112 22:53:31.111495 2, 0xFFFF, sum = 0
4113 22:53:31.112059 3, 0xFFFF, sum = 0
4114 22:53:31.114741 4, 0xFFFF, sum = 0
4115 22:53:31.115216 5, 0xFFFF, sum = 0
4116 22:53:31.117901 6, 0xFFFF, sum = 0
4117 22:53:31.118371 7, 0xFFFF, sum = 0
4118 22:53:31.120934 8, 0x0, sum = 1
4119 22:53:31.121534 9, 0x0, sum = 2
4120 22:53:31.121917 10, 0x0, sum = 3
4121 22:53:31.124687 11, 0x0, sum = 4
4122 22:53:31.125264 best_step = 9
4123 22:53:31.125676
4124 22:53:31.126022 ==
4125 22:53:31.127802 Dram Type= 6, Freq= 0, CH_0, rank 0
4126 22:53:31.134472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4127 22:53:31.135042 ==
4128 22:53:31.135417 RX Vref Scan: 1
4129 22:53:31.135758
4130 22:53:31.137544 RX Vref 0 -> 0, step: 1
4131 22:53:31.138009
4132 22:53:31.140952 RX Delay -179 -> 252, step: 8
4133 22:53:31.141559
4134 22:53:31.144383 Set Vref, RX VrefLevel [Byte0]: 58
4135 22:53:31.147509 [Byte1]: 48
4136 22:53:31.148057
4137 22:53:31.150840 Final RX Vref Byte 0 = 58 to rank0
4138 22:53:31.154011 Final RX Vref Byte 1 = 48 to rank0
4139 22:53:31.157792 Final RX Vref Byte 0 = 58 to rank1
4140 22:53:31.160651 Final RX Vref Byte 1 = 48 to rank1==
4141 22:53:31.164591 Dram Type= 6, Freq= 0, CH_0, rank 0
4142 22:53:31.167480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4143 22:53:31.168029 ==
4144 22:53:31.170948 DQS Delay:
4145 22:53:31.171410 DQS0 = 0, DQS1 = 0
4146 22:53:31.171779 DQM Delay:
4147 22:53:31.174117 DQM0 = 48, DQM1 = 40
4148 22:53:31.174678 DQ Delay:
4149 22:53:31.177335 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4150 22:53:31.180635 DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =56
4151 22:53:31.184099 DQ8 =36, DQ9 =24, DQ10 =36, DQ11 =36
4152 22:53:31.187340 DQ12 =44, DQ13 =44, DQ14 =52, DQ15 =48
4153 22:53:31.187896
4154 22:53:31.188264
4155 22:53:31.197489 [DQSOSCAuto] RK0, (LSB)MR18= 0x5953, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
4156 22:53:31.200764 CH0 RK0: MR19=808, MR18=5953
4157 22:53:31.204087 CH0_RK0: MR19=0x808, MR18=0x5953, DQSOSC=393, MR23=63, INC=169, DEC=113
4158 22:53:31.207400
4159 22:53:31.210800 ----->DramcWriteLeveling(PI) begin...
4160 22:53:31.211273 ==
4161 22:53:31.213884 Dram Type= 6, Freq= 0, CH_0, rank 1
4162 22:53:31.217107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4163 22:53:31.217624 ==
4164 22:53:31.220770 Write leveling (Byte 0): 33 => 33
4165 22:53:31.224187 Write leveling (Byte 1): 30 => 30
4166 22:53:31.227229 DramcWriteLeveling(PI) end<-----
4167 22:53:31.227765
4168 22:53:31.228128 ==
4169 22:53:31.230655 Dram Type= 6, Freq= 0, CH_0, rank 1
4170 22:53:31.234061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4171 22:53:31.234529 ==
4172 22:53:31.236999 [Gating] SW mode calibration
4173 22:53:31.243950 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4174 22:53:31.250628 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4175 22:53:31.253823 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4176 22:53:31.257363 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4177 22:53:31.263686 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4178 22:53:31.267469 0 9 12 | B1->B0 | 3030 3131 | 1 0 | (1 1) (0 0)
4179 22:53:31.270635 0 9 16 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
4180 22:53:31.277099 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4181 22:53:31.280671 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4182 22:53:31.283571 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4183 22:53:31.287355 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4184 22:53:31.293883 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4185 22:53:31.297171 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4186 22:53:31.300532 0 10 12 | B1->B0 | 2e2e 3333 | 0 1 | (1 1) (0 0)
4187 22:53:31.307459 0 10 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4188 22:53:31.310342 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4189 22:53:31.313936 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4190 22:53:31.320536 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4191 22:53:31.323885 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4192 22:53:31.327838 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4193 22:53:31.333697 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4194 22:53:31.337432 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4195 22:53:31.340371 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 22:53:31.347376 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 22:53:31.350712 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 22:53:31.353999 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 22:53:31.360523 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 22:53:31.363632 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 22:53:31.367363 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 22:53:31.370570 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 22:53:31.376915 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 22:53:31.380300 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 22:53:31.384040 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 22:53:31.390746 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 22:53:31.393826 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 22:53:31.397248 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 22:53:31.403633 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 22:53:31.407310 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4211 22:53:31.410097 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4212 22:53:31.413423 Total UI for P1: 0, mck2ui 16
4213 22:53:31.416704 best dqsien dly found for B0: ( 0, 13, 14)
4214 22:53:31.420303 Total UI for P1: 0, mck2ui 16
4215 22:53:31.423338 best dqsien dly found for B1: ( 0, 13, 12)
4216 22:53:31.426821 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4217 22:53:31.430664 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4218 22:53:31.433172
4219 22:53:31.436649 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4220 22:53:31.440196 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4221 22:53:31.443173 [Gating] SW calibration Done
4222 22:53:31.443638 ==
4223 22:53:31.446739 Dram Type= 6, Freq= 0, CH_0, rank 1
4224 22:53:31.450177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4225 22:53:31.450746 ==
4226 22:53:31.451247 RX Vref Scan: 0
4227 22:53:31.453723
4228 22:53:31.454206 RX Vref 0 -> 0, step: 1
4229 22:53:31.454687
4230 22:53:31.456795 RX Delay -230 -> 252, step: 16
4231 22:53:31.459977 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4232 22:53:31.466501 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4233 22:53:31.470042 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4234 22:53:31.473350 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4235 22:53:31.476472 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4236 22:53:31.479699 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4237 22:53:31.486621 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4238 22:53:31.489820 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4239 22:53:31.493273 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4240 22:53:31.496454 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4241 22:53:31.503336 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4242 22:53:31.506644 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4243 22:53:31.510066 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4244 22:53:31.513403 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4245 22:53:31.519615 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4246 22:53:31.523013 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4247 22:53:31.523485 ==
4248 22:53:31.526703 Dram Type= 6, Freq= 0, CH_0, rank 1
4249 22:53:31.529784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4250 22:53:31.530346 ==
4251 22:53:31.532954 DQS Delay:
4252 22:53:31.533443 DQS0 = 0, DQS1 = 0
4253 22:53:31.533815 DQM Delay:
4254 22:53:31.536350 DQM0 = 47, DQM1 = 41
4255 22:53:31.536887 DQ Delay:
4256 22:53:31.539468 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4257 22:53:31.543050 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4258 22:53:31.546262 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4259 22:53:31.549285 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =49
4260 22:53:31.549809
4261 22:53:31.550290
4262 22:53:31.550742 ==
4263 22:53:31.553179 Dram Type= 6, Freq= 0, CH_0, rank 1
4264 22:53:31.559509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4265 22:53:31.559969 ==
4266 22:53:31.560305
4267 22:53:31.560615
4268 22:53:31.560916 TX Vref Scan disable
4269 22:53:31.562656 == TX Byte 0 ==
4270 22:53:31.566399 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4271 22:53:31.573023 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4272 22:53:31.573587 == TX Byte 1 ==
4273 22:53:31.576155 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4274 22:53:31.582917 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4275 22:53:31.583484 ==
4276 22:53:31.586562 Dram Type= 6, Freq= 0, CH_0, rank 1
4277 22:53:31.589817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4278 22:53:31.590386 ==
4279 22:53:31.590758
4280 22:53:31.591100
4281 22:53:31.593034 TX Vref Scan disable
4282 22:53:31.596375 == TX Byte 0 ==
4283 22:53:31.599664 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4284 22:53:31.602965 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4285 22:53:31.605942 == TX Byte 1 ==
4286 22:53:31.609456 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4287 22:53:31.612936 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4288 22:53:31.613507
4289 22:53:31.613876 [DATLAT]
4290 22:53:31.615935 Freq=600, CH0 RK1
4291 22:53:31.616406
4292 22:53:31.619546 DATLAT Default: 0x9
4293 22:53:31.620119 0, 0xFFFF, sum = 0
4294 22:53:31.622419 1, 0xFFFF, sum = 0
4295 22:53:31.622885 2, 0xFFFF, sum = 0
4296 22:53:31.625873 3, 0xFFFF, sum = 0
4297 22:53:31.626362 4, 0xFFFF, sum = 0
4298 22:53:31.628840 5, 0xFFFF, sum = 0
4299 22:53:31.629340 6, 0xFFFF, sum = 0
4300 22:53:31.632558 7, 0xFFFF, sum = 0
4301 22:53:31.633035 8, 0x0, sum = 1
4302 22:53:31.635746 9, 0x0, sum = 2
4303 22:53:31.636211 10, 0x0, sum = 3
4304 22:53:31.639023 11, 0x0, sum = 4
4305 22:53:31.639447 best_step = 9
4306 22:53:31.639780
4307 22:53:31.640086 ==
4308 22:53:31.642161 Dram Type= 6, Freq= 0, CH_0, rank 1
4309 22:53:31.645860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4310 22:53:31.646281 ==
4311 22:53:31.649342 RX Vref Scan: 0
4312 22:53:31.649871
4313 22:53:31.652500 RX Vref 0 -> 0, step: 1
4314 22:53:31.653047
4315 22:53:31.653420 RX Delay -179 -> 252, step: 8
4316 22:53:31.660411 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4317 22:53:31.663424 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4318 22:53:31.666693 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4319 22:53:31.670042 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4320 22:53:31.673102 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4321 22:53:31.680462 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4322 22:53:31.683249 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4323 22:53:31.686997 iDelay=205, Bit 7, Center 52 (-91 ~ 196) 288
4324 22:53:31.690119 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4325 22:53:31.696469 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4326 22:53:31.699963 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4327 22:53:31.703702 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4328 22:53:31.706723 iDelay=205, Bit 12, Center 44 (-99 ~ 188) 288
4329 22:53:31.710479 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4330 22:53:31.716890 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4331 22:53:31.720022 iDelay=205, Bit 15, Center 44 (-99 ~ 188) 288
4332 22:53:31.720572 ==
4333 22:53:31.723239 Dram Type= 6, Freq= 0, CH_0, rank 1
4334 22:53:31.727001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4335 22:53:31.727562 ==
4336 22:53:31.730017 DQS Delay:
4337 22:53:31.730471 DQS0 = 0, DQS1 = 0
4338 22:53:31.730832 DQM Delay:
4339 22:53:31.733445 DQM0 = 48, DQM1 = 39
4340 22:53:31.734182 DQ Delay:
4341 22:53:31.736540 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4342 22:53:31.740148 DQ4 =48, DQ5 =40, DQ6 =60, DQ7 =52
4343 22:53:31.743355 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =32
4344 22:53:31.746885 DQ12 =44, DQ13 =44, DQ14 =48, DQ15 =44
4345 22:53:31.747613
4346 22:53:31.748163
4347 22:53:31.756299 [DQSOSCAuto] RK1, (LSB)MR18= 0x6532, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 390 ps
4348 22:53:31.756908 CH0 RK1: MR19=808, MR18=6532
4349 22:53:31.763165 CH0_RK1: MR19=0x808, MR18=0x6532, DQSOSC=390, MR23=63, INC=172, DEC=114
4350 22:53:31.766648 [RxdqsGatingPostProcess] freq 600
4351 22:53:31.773136 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4352 22:53:31.776178 Pre-setting of DQS Precalculation
4353 22:53:31.779674 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4354 22:53:31.780135 ==
4355 22:53:31.782975 Dram Type= 6, Freq= 0, CH_1, rank 0
4356 22:53:31.790226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4357 22:53:31.790956 ==
4358 22:53:31.793388 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4359 22:53:31.799629 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4360 22:53:31.803306 [CA 0] Center 35 (5~66) winsize 62
4361 22:53:31.806279 [CA 1] Center 35 (5~66) winsize 62
4362 22:53:31.809847 [CA 2] Center 34 (4~65) winsize 62
4363 22:53:31.813065 [CA 3] Center 33 (3~64) winsize 62
4364 22:53:31.816335 [CA 4] Center 33 (3~64) winsize 62
4365 22:53:31.819616 [CA 5] Center 33 (3~64) winsize 62
4366 22:53:31.820089
4367 22:53:31.822919 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4368 22:53:31.823494
4369 22:53:31.825987 [CATrainingPosCal] consider 1 rank data
4370 22:53:31.829828 u2DelayCellTimex100 = 270/100 ps
4371 22:53:31.832842 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4372 22:53:31.836178 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4373 22:53:31.843021 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4374 22:53:31.846107 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4375 22:53:31.849465 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4376 22:53:31.853140 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4377 22:53:31.853824
4378 22:53:31.856012 CA PerBit enable=1, Macro0, CA PI delay=33
4379 22:53:31.856564
4380 22:53:31.859363 [CBTSetCACLKResult] CA Dly = 33
4381 22:53:31.859997 CS Dly: 4 (0~35)
4382 22:53:31.860556 ==
4383 22:53:31.862603 Dram Type= 6, Freq= 0, CH_1, rank 1
4384 22:53:31.870078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4385 22:53:31.870719 ==
4386 22:53:31.872939 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4387 22:53:31.879199 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4388 22:53:31.882700 [CA 0] Center 35 (5~66) winsize 62
4389 22:53:31.886306 [CA 1] Center 35 (5~66) winsize 62
4390 22:53:31.889634 [CA 2] Center 34 (4~65) winsize 62
4391 22:53:31.892407 [CA 3] Center 34 (4~65) winsize 62
4392 22:53:31.895739 [CA 4] Center 34 (4~64) winsize 61
4393 22:53:31.899163 [CA 5] Center 33 (3~64) winsize 62
4394 22:53:31.899627
4395 22:53:31.902453 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4396 22:53:31.902918
4397 22:53:31.905889 [CATrainingPosCal] consider 2 rank data
4398 22:53:31.908965 u2DelayCellTimex100 = 270/100 ps
4399 22:53:31.912710 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4400 22:53:31.919330 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4401 22:53:31.922886 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4402 22:53:31.926046 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4403 22:53:31.929502 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4404 22:53:31.932819 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4405 22:53:31.933365
4406 22:53:31.936194 CA PerBit enable=1, Macro0, CA PI delay=33
4407 22:53:31.936719
4408 22:53:31.939585 [CBTSetCACLKResult] CA Dly = 33
4409 22:53:31.940113 CS Dly: 4 (0~36)
4410 22:53:31.940450
4411 22:53:31.942491 ----->DramcWriteLeveling(PI) begin...
4412 22:53:31.946370 ==
4413 22:53:31.949074 Dram Type= 6, Freq= 0, CH_1, rank 0
4414 22:53:31.952874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4415 22:53:31.953318 ==
4416 22:53:31.956123 Write leveling (Byte 0): 28 => 28
4417 22:53:31.958950 Write leveling (Byte 1): 31 => 31
4418 22:53:31.962795 DramcWriteLeveling(PI) end<-----
4419 22:53:31.963420
4420 22:53:31.963820 ==
4421 22:53:31.965949 Dram Type= 6, Freq= 0, CH_1, rank 0
4422 22:53:31.968998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4423 22:53:31.969629 ==
4424 22:53:31.972535 [Gating] SW mode calibration
4425 22:53:31.979296 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4426 22:53:31.982705 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4427 22:53:31.988886 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4428 22:53:31.992382 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4429 22:53:31.995689 0 9 8 | B1->B0 | 3434 3333 | 0 1 | (0 0) (1 1)
4430 22:53:32.003154 0 9 12 | B1->B0 | 2929 2e2e | 0 0 | (0 0) (0 0)
4431 22:53:32.005685 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4432 22:53:32.008796 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4433 22:53:32.015388 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4434 22:53:32.018964 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4435 22:53:32.022031 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4436 22:53:32.028547 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4437 22:53:32.032481 0 10 8 | B1->B0 | 2727 2b2b | 0 0 | (0 0) (0 0)
4438 22:53:32.035623 0 10 12 | B1->B0 | 3d3d 3d3d | 0 0 | (1 1) (0 0)
4439 22:53:32.042283 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4440 22:53:32.045948 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4441 22:53:32.048979 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4442 22:53:32.055920 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4443 22:53:32.058655 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4444 22:53:32.062352 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4445 22:53:32.068843 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4446 22:53:32.071815 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 22:53:32.075354 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4448 22:53:32.082422 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 22:53:32.085537 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 22:53:32.089098 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 22:53:32.095505 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 22:53:32.098644 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 22:53:32.102039 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 22:53:32.108753 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 22:53:32.112155 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 22:53:32.115294 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 22:53:32.119121 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 22:53:32.125533 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 22:53:32.129060 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 22:53:32.132617 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 22:53:32.139309 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 22:53:32.142087 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4463 22:53:32.145662 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4464 22:53:32.149099 Total UI for P1: 0, mck2ui 16
4465 22:53:32.152191 best dqsien dly found for B0: ( 0, 13, 12)
4466 22:53:32.155542 Total UI for P1: 0, mck2ui 16
4467 22:53:32.159113 best dqsien dly found for B1: ( 0, 13, 12)
4468 22:53:32.161933 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4469 22:53:32.165528 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4470 22:53:32.168889
4471 22:53:32.172229 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4472 22:53:32.175589 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4473 22:53:32.178666 [Gating] SW calibration Done
4474 22:53:32.179133 ==
4475 22:53:32.181987 Dram Type= 6, Freq= 0, CH_1, rank 0
4476 22:53:32.185374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4477 22:53:32.185847 ==
4478 22:53:32.186220 RX Vref Scan: 0
4479 22:53:32.188515
4480 22:53:32.188979 RX Vref 0 -> 0, step: 1
4481 22:53:32.189389
4482 22:53:32.191737 RX Delay -230 -> 252, step: 16
4483 22:53:32.195707 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4484 22:53:32.201791 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4485 22:53:32.205169 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4486 22:53:32.208550 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4487 22:53:32.212545 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4488 22:53:32.215036 iDelay=218, Bit 5, Center 57 (-86 ~ 201) 288
4489 22:53:32.221851 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4490 22:53:32.225201 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4491 22:53:32.228621 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4492 22:53:32.231992 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4493 22:53:32.235249 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4494 22:53:32.241677 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4495 22:53:32.245412 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4496 22:53:32.248669 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4497 22:53:32.251719 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4498 22:53:32.258569 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4499 22:53:32.259135 ==
4500 22:53:32.261969 Dram Type= 6, Freq= 0, CH_1, rank 0
4501 22:53:32.264994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4502 22:53:32.265495 ==
4503 22:53:32.265863 DQS Delay:
4504 22:53:32.268385 DQS0 = 0, DQS1 = 0
4505 22:53:32.268850 DQM Delay:
4506 22:53:32.271642 DQM0 = 51, DQM1 = 45
4507 22:53:32.272144 DQ Delay:
4508 22:53:32.275151 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4509 22:53:32.278405 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4510 22:53:32.281434 DQ8 =25, DQ9 =33, DQ10 =49, DQ11 =41
4511 22:53:32.285162 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =49
4512 22:53:32.285729
4513 22:53:32.286103
4514 22:53:32.286533 ==
4515 22:53:32.288430 Dram Type= 6, Freq= 0, CH_1, rank 0
4516 22:53:32.291567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4517 22:53:32.295051 ==
4518 22:53:32.295710
4519 22:53:32.296085
4520 22:53:32.296426 TX Vref Scan disable
4521 22:53:32.298413 == TX Byte 0 ==
4522 22:53:32.301444 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4523 22:53:32.304832 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4524 22:53:32.308285 == TX Byte 1 ==
4525 22:53:32.311795 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4526 22:53:32.314948 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4527 22:53:32.318509 ==
4528 22:53:32.318980 Dram Type= 6, Freq= 0, CH_1, rank 0
4529 22:53:32.324768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4530 22:53:32.325363 ==
4531 22:53:32.325739
4532 22:53:32.326080
4533 22:53:32.328246 TX Vref Scan disable
4534 22:53:32.328805 == TX Byte 0 ==
4535 22:53:32.334840 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4536 22:53:32.338611 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4537 22:53:32.339177 == TX Byte 1 ==
4538 22:53:32.345088 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4539 22:53:32.348242 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4540 22:53:32.348806
4541 22:53:32.349172 [DATLAT]
4542 22:53:32.351339 Freq=600, CH1 RK0
4543 22:53:32.351821
4544 22:53:32.352183 DATLAT Default: 0x9
4545 22:53:32.354680 0, 0xFFFF, sum = 0
4546 22:53:32.355149 1, 0xFFFF, sum = 0
4547 22:53:32.357768 2, 0xFFFF, sum = 0
4548 22:53:32.358233 3, 0xFFFF, sum = 0
4549 22:53:32.361578 4, 0xFFFF, sum = 0
4550 22:53:32.364625 5, 0xFFFF, sum = 0
4551 22:53:32.365196 6, 0xFFFF, sum = 0
4552 22:53:32.368213 7, 0xFFFF, sum = 0
4553 22:53:32.368784 8, 0x0, sum = 1
4554 22:53:32.369213 9, 0x0, sum = 2
4555 22:53:32.370911 10, 0x0, sum = 3
4556 22:53:32.371404 11, 0x0, sum = 4
4557 22:53:32.374433 best_step = 9
4558 22:53:32.374895
4559 22:53:32.375260 ==
4560 22:53:32.377546 Dram Type= 6, Freq= 0, CH_1, rank 0
4561 22:53:32.381175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4562 22:53:32.381693 ==
4563 22:53:32.384271 RX Vref Scan: 1
4564 22:53:32.384732
4565 22:53:32.385183 RX Vref 0 -> 0, step: 1
4566 22:53:32.385573
4567 22:53:32.387883 RX Delay -179 -> 252, step: 8
4568 22:53:32.388438
4569 22:53:32.391276 Set Vref, RX VrefLevel [Byte0]: 53
4570 22:53:32.394163 [Byte1]: 50
4571 22:53:32.398093
4572 22:53:32.398572 Final RX Vref Byte 0 = 53 to rank0
4573 22:53:32.401729 Final RX Vref Byte 1 = 50 to rank0
4574 22:53:32.404873 Final RX Vref Byte 0 = 53 to rank1
4575 22:53:32.408224 Final RX Vref Byte 1 = 50 to rank1==
4576 22:53:32.411515 Dram Type= 6, Freq= 0, CH_1, rank 0
4577 22:53:32.418272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4578 22:53:32.418740 ==
4579 22:53:32.419084 DQS Delay:
4580 22:53:32.419401 DQS0 = 0, DQS1 = 0
4581 22:53:32.421412 DQM Delay:
4582 22:53:32.421839 DQM0 = 48, DQM1 = 41
4583 22:53:32.425025 DQ Delay:
4584 22:53:32.428166 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4585 22:53:32.428592 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =44
4586 22:53:32.431779 DQ8 =28, DQ9 =28, DQ10 =44, DQ11 =36
4587 22:53:32.438436 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =48
4588 22:53:32.438999
4589 22:53:32.439368
4590 22:53:32.444900 [DQSOSCAuto] RK0, (LSB)MR18= 0x4870, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 396 ps
4591 22:53:32.448384 CH1 RK0: MR19=808, MR18=4870
4592 22:53:32.455146 CH1_RK0: MR19=0x808, MR18=0x4870, DQSOSC=388, MR23=63, INC=174, DEC=116
4593 22:53:32.455620
4594 22:53:32.458466 ----->DramcWriteLeveling(PI) begin...
4595 22:53:32.458943 ==
4596 22:53:32.461604 Dram Type= 6, Freq= 0, CH_1, rank 1
4597 22:53:32.465353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4598 22:53:32.466003 ==
4599 22:53:32.468325 Write leveling (Byte 0): 30 => 30
4600 22:53:32.471553 Write leveling (Byte 1): 29 => 29
4601 22:53:32.474912 DramcWriteLeveling(PI) end<-----
4602 22:53:32.475338
4603 22:53:32.475673 ==
4604 22:53:32.478242 Dram Type= 6, Freq= 0, CH_1, rank 1
4605 22:53:32.481598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4606 22:53:32.482025 ==
4607 22:53:32.484905 [Gating] SW mode calibration
4608 22:53:32.491311 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4609 22:53:32.498092 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4610 22:53:32.501326 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4611 22:53:32.504701 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4612 22:53:32.511410 0 9 8 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
4613 22:53:32.514933 0 9 12 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 0)
4614 22:53:32.517966 0 9 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4615 22:53:32.525071 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4616 22:53:32.528269 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4617 22:53:32.531726 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4618 22:53:32.538014 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4619 22:53:32.541455 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4620 22:53:32.544947 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (1 1) (0 0)
4621 22:53:32.551611 0 10 12 | B1->B0 | 3d3d 2e2e | 0 0 | (0 0) (0 0)
4622 22:53:32.554480 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4623 22:53:32.557669 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4624 22:53:32.564232 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4625 22:53:32.568126 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4626 22:53:32.571055 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4627 22:53:32.577812 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4628 22:53:32.580809 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4629 22:53:32.584208 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4630 22:53:32.590863 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 22:53:32.594449 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 22:53:32.597759 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 22:53:32.604107 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 22:53:32.607703 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 22:53:32.611268 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 22:53:32.617881 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 22:53:32.621000 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 22:53:32.624684 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 22:53:32.631335 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 22:53:32.634633 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 22:53:32.638127 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 22:53:32.641046 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 22:53:32.647817 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 22:53:32.651047 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 22:53:32.654197 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4646 22:53:32.657414 Total UI for P1: 0, mck2ui 16
4647 22:53:32.660929 best dqsien dly found for B1: ( 0, 13, 10)
4648 22:53:32.667586 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4649 22:53:32.670986 Total UI for P1: 0, mck2ui 16
4650 22:53:32.674057 best dqsien dly found for B0: ( 0, 13, 12)
4651 22:53:32.677271 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4652 22:53:32.680896 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4653 22:53:32.681396
4654 22:53:32.684017 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4655 22:53:32.687250 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4656 22:53:32.690940 [Gating] SW calibration Done
4657 22:53:32.691495 ==
4658 22:53:32.693794 Dram Type= 6, Freq= 0, CH_1, rank 1
4659 22:53:32.697135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4660 22:53:32.697699 ==
4661 22:53:32.700616 RX Vref Scan: 0
4662 22:53:32.701079
4663 22:53:32.703764 RX Vref 0 -> 0, step: 1
4664 22:53:32.704229
4665 22:53:32.704600 RX Delay -230 -> 252, step: 16
4666 22:53:32.710549 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4667 22:53:32.713868 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4668 22:53:32.716861 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4669 22:53:32.720332 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4670 22:53:32.727398 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4671 22:53:32.730680 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4672 22:53:32.733705 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4673 22:53:32.737190 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4674 22:53:32.740861 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4675 22:53:32.747389 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4676 22:53:32.750812 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4677 22:53:32.754149 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4678 22:53:32.757622 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4679 22:53:32.763908 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4680 22:53:32.767427 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4681 22:53:32.770460 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4682 22:53:32.771033 ==
4683 22:53:32.773722 Dram Type= 6, Freq= 0, CH_1, rank 1
4684 22:53:32.777229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4685 22:53:32.777840 ==
4686 22:53:32.780062 DQS Delay:
4687 22:53:32.780531 DQS0 = 0, DQS1 = 0
4688 22:53:32.783832 DQM Delay:
4689 22:53:32.784391 DQM0 = 52, DQM1 = 44
4690 22:53:32.784765 DQ Delay:
4691 22:53:32.786959 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4692 22:53:32.790580 DQ4 =49, DQ5 =65, DQ6 =65, DQ7 =49
4693 22:53:32.793705 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4694 22:53:32.797354 DQ12 =57, DQ13 =49, DQ14 =41, DQ15 =57
4695 22:53:32.797925
4696 22:53:32.798296
4697 22:53:32.800435 ==
4698 22:53:32.803288 Dram Type= 6, Freq= 0, CH_1, rank 1
4699 22:53:32.807198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4700 22:53:32.807767 ==
4701 22:53:32.808144
4702 22:53:32.808486
4703 22:53:32.810303 TX Vref Scan disable
4704 22:53:32.810792 == TX Byte 0 ==
4705 22:53:32.816788 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4706 22:53:32.820407 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4707 22:53:32.820975 == TX Byte 1 ==
4708 22:53:32.826769 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4709 22:53:32.830205 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4710 22:53:32.830770 ==
4711 22:53:32.833345 Dram Type= 6, Freq= 0, CH_1, rank 1
4712 22:53:32.836901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4713 22:53:32.837410 ==
4714 22:53:32.837786
4715 22:53:32.838182
4716 22:53:32.840406 TX Vref Scan disable
4717 22:53:32.844023 == TX Byte 0 ==
4718 22:53:32.846653 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4719 22:53:32.849879 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4720 22:53:32.853279 == TX Byte 1 ==
4721 22:53:32.856691 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4722 22:53:32.859816 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4723 22:53:32.860285
4724 22:53:32.863563 [DATLAT]
4725 22:53:32.864125 Freq=600, CH1 RK1
4726 22:53:32.864500
4727 22:53:32.867088 DATLAT Default: 0x9
4728 22:53:32.867652 0, 0xFFFF, sum = 0
4729 22:53:32.870145 1, 0xFFFF, sum = 0
4730 22:53:32.870714 2, 0xFFFF, sum = 0
4731 22:53:32.873231 3, 0xFFFF, sum = 0
4732 22:53:32.873781 4, 0xFFFF, sum = 0
4733 22:53:32.876670 5, 0xFFFF, sum = 0
4734 22:53:32.877239 6, 0xFFFF, sum = 0
4735 22:53:32.879836 7, 0xFFFF, sum = 0
4736 22:53:32.880327 8, 0x0, sum = 1
4737 22:53:32.883190 9, 0x0, sum = 2
4738 22:53:32.883761 10, 0x0, sum = 3
4739 22:53:32.886498 11, 0x0, sum = 4
4740 22:53:32.886970 best_step = 9
4741 22:53:32.887341
4742 22:53:32.887681 ==
4743 22:53:32.889762 Dram Type= 6, Freq= 0, CH_1, rank 1
4744 22:53:32.893716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4745 22:53:32.896390 ==
4746 22:53:32.896853 RX Vref Scan: 0
4747 22:53:32.897221
4748 22:53:32.899893 RX Vref 0 -> 0, step: 1
4749 22:53:32.900458
4750 22:53:32.903422 RX Delay -163 -> 252, step: 8
4751 22:53:32.906654 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4752 22:53:32.909803 iDelay=205, Bit 1, Center 40 (-99 ~ 180) 280
4753 22:53:32.916740 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4754 22:53:32.919847 iDelay=205, Bit 3, Center 48 (-91 ~ 188) 280
4755 22:53:32.923400 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4756 22:53:32.926273 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4757 22:53:32.929658 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4758 22:53:32.936238 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4759 22:53:32.939472 iDelay=205, Bit 8, Center 28 (-115 ~ 172) 288
4760 22:53:32.943154 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4761 22:53:32.945998 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4762 22:53:32.949405 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4763 22:53:32.956192 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4764 22:53:32.959574 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4765 22:53:32.963025 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4766 22:53:32.966280 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4767 22:53:32.966818 ==
4768 22:53:32.969466 Dram Type= 6, Freq= 0, CH_1, rank 1
4769 22:53:32.976253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4770 22:53:32.976812 ==
4771 22:53:32.977183 DQS Delay:
4772 22:53:32.979193 DQS0 = 0, DQS1 = 0
4773 22:53:32.979673 DQM Delay:
4774 22:53:32.980037 DQM0 = 49, DQM1 = 42
4775 22:53:32.982645 DQ Delay:
4776 22:53:32.986303 DQ0 =56, DQ1 =40, DQ2 =36, DQ3 =48
4777 22:53:32.989466 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4778 22:53:32.993035 DQ8 =28, DQ9 =36, DQ10 =44, DQ11 =36
4779 22:53:32.996493 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =52
4780 22:53:32.997077
4781 22:53:32.997511
4782 22:53:33.002536 [DQSOSCAuto] RK1, (LSB)MR18= 0x581f, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
4783 22:53:33.006427 CH1 RK1: MR19=808, MR18=581F
4784 22:53:33.012630 CH1_RK1: MR19=0x808, MR18=0x581F, DQSOSC=393, MR23=63, INC=169, DEC=113
4785 22:53:33.015754 [RxdqsGatingPostProcess] freq 600
4786 22:53:33.019027 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4787 22:53:33.022404 Pre-setting of DQS Precalculation
4788 22:53:33.029077 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4789 22:53:33.035762 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4790 22:53:33.042479 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4791 22:53:33.043053
4792 22:53:33.043424
4793 22:53:33.045753 [Calibration Summary] 1200 Mbps
4794 22:53:33.046219 CH 0, Rank 0
4795 22:53:33.049545 SW Impedance : PASS
4796 22:53:33.052372 DUTY Scan : NO K
4797 22:53:33.052942 ZQ Calibration : PASS
4798 22:53:33.056101 Jitter Meter : NO K
4799 22:53:33.059206 CBT Training : PASS
4800 22:53:33.059784 Write leveling : PASS
4801 22:53:33.062458 RX DQS gating : PASS
4802 22:53:33.066187 RX DQ/DQS(RDDQC) : PASS
4803 22:53:33.066758 TX DQ/DQS : PASS
4804 22:53:33.069001 RX DATLAT : PASS
4805 22:53:33.072656 RX DQ/DQS(Engine): PASS
4806 22:53:33.073268 TX OE : NO K
4807 22:53:33.075800 All Pass.
4808 22:53:33.076362
4809 22:53:33.076733 CH 0, Rank 1
4810 22:53:33.078805 SW Impedance : PASS
4811 22:53:33.079273 DUTY Scan : NO K
4812 22:53:33.082449 ZQ Calibration : PASS
4813 22:53:33.085902 Jitter Meter : NO K
4814 22:53:33.086472 CBT Training : PASS
4815 22:53:33.089115 Write leveling : PASS
4816 22:53:33.089615 RX DQS gating : PASS
4817 22:53:33.092381 RX DQ/DQS(RDDQC) : PASS
4818 22:53:33.095928 TX DQ/DQS : PASS
4819 22:53:33.096503 RX DATLAT : PASS
4820 22:53:33.099555 RX DQ/DQS(Engine): PASS
4821 22:53:33.102498 TX OE : NO K
4822 22:53:33.102970 All Pass.
4823 22:53:33.103342
4824 22:53:33.103704 CH 1, Rank 0
4825 22:53:33.105526 SW Impedance : PASS
4826 22:53:33.109162 DUTY Scan : NO K
4827 22:53:33.109759 ZQ Calibration : PASS
4828 22:53:33.112338 Jitter Meter : NO K
4829 22:53:33.115589 CBT Training : PASS
4830 22:53:33.116048 Write leveling : PASS
4831 22:53:33.119106 RX DQS gating : PASS
4832 22:53:33.122648 RX DQ/DQS(RDDQC) : PASS
4833 22:53:33.123144 TX DQ/DQS : PASS
4834 22:53:33.125407 RX DATLAT : PASS
4835 22:53:33.129140 RX DQ/DQS(Engine): PASS
4836 22:53:33.129741 TX OE : NO K
4837 22:53:33.130119 All Pass.
4838 22:53:33.130464
4839 22:53:33.132284 CH 1, Rank 1
4840 22:53:33.132746 SW Impedance : PASS
4841 22:53:33.135755 DUTY Scan : NO K
4842 22:53:33.138991 ZQ Calibration : PASS
4843 22:53:33.139457 Jitter Meter : NO K
4844 22:53:33.142668 CBT Training : PASS
4845 22:53:33.145658 Write leveling : PASS
4846 22:53:33.146168 RX DQS gating : PASS
4847 22:53:33.149198 RX DQ/DQS(RDDQC) : PASS
4848 22:53:33.152735 TX DQ/DQS : PASS
4849 22:53:33.153331 RX DATLAT : PASS
4850 22:53:33.155834 RX DQ/DQS(Engine): PASS
4851 22:53:33.159018 TX OE : NO K
4852 22:53:33.159481 All Pass.
4853 22:53:33.159845
4854 22:53:33.160183 DramC Write-DBI off
4855 22:53:33.162374 PER_BANK_REFRESH: Hybrid Mode
4856 22:53:33.165538 TX_TRACKING: ON
4857 22:53:33.172298 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4858 22:53:33.175726 [FAST_K] Save calibration result to emmc
4859 22:53:33.182056 dramc_set_vcore_voltage set vcore to 662500
4860 22:53:33.182517 Read voltage for 933, 3
4861 22:53:33.186023 Vio18 = 0
4862 22:53:33.186592 Vcore = 662500
4863 22:53:33.186966 Vdram = 0
4864 22:53:33.187310 Vddq = 0
4865 22:53:33.188853 Vmddr = 0
4866 22:53:33.192425 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4867 22:53:33.198748 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4868 22:53:33.201958 MEM_TYPE=3, freq_sel=17
4869 22:53:33.202420 sv_algorithm_assistance_LP4_1600
4870 22:53:33.208985 ============ PULL DRAM RESETB DOWN ============
4871 22:53:33.212189 ========== PULL DRAM RESETB DOWN end =========
4872 22:53:33.215850 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4873 22:53:33.218863 ===================================
4874 22:53:33.221950 LPDDR4 DRAM CONFIGURATION
4875 22:53:33.225445 ===================================
4876 22:53:33.229148 EX_ROW_EN[0] = 0x0
4877 22:53:33.229722 EX_ROW_EN[1] = 0x0
4878 22:53:33.232098 LP4Y_EN = 0x0
4879 22:53:33.232563 WORK_FSP = 0x0
4880 22:53:33.235378 WL = 0x3
4881 22:53:33.235952 RL = 0x3
4882 22:53:33.238702 BL = 0x2
4883 22:53:33.239165 RPST = 0x0
4884 22:53:33.242273 RD_PRE = 0x0
4885 22:53:33.242737 WR_PRE = 0x1
4886 22:53:33.245663 WR_PST = 0x0
4887 22:53:33.246233 DBI_WR = 0x0
4888 22:53:33.248974 DBI_RD = 0x0
4889 22:53:33.249573 OTF = 0x1
4890 22:53:33.252253 ===================================
4891 22:53:33.255919 ===================================
4892 22:53:33.258614 ANA top config
4893 22:53:33.262178 ===================================
4894 22:53:33.265825 DLL_ASYNC_EN = 0
4895 22:53:33.266393 ALL_SLAVE_EN = 1
4896 22:53:33.269404 NEW_RANK_MODE = 1
4897 22:53:33.272220 DLL_IDLE_MODE = 1
4898 22:53:33.275882 LP45_APHY_COMB_EN = 1
4899 22:53:33.276446 TX_ODT_DIS = 1
4900 22:53:33.279002 NEW_8X_MODE = 1
4901 22:53:33.282092 ===================================
4902 22:53:33.285571 ===================================
4903 22:53:33.289092 data_rate = 1866
4904 22:53:33.292337 CKR = 1
4905 22:53:33.295507 DQ_P2S_RATIO = 8
4906 22:53:33.298753 ===================================
4907 22:53:33.302083 CA_P2S_RATIO = 8
4908 22:53:33.302647 DQ_CA_OPEN = 0
4909 22:53:33.305016 DQ_SEMI_OPEN = 0
4910 22:53:33.308606 CA_SEMI_OPEN = 0
4911 22:53:33.311715 CA_FULL_RATE = 0
4912 22:53:33.315387 DQ_CKDIV4_EN = 1
4913 22:53:33.318305 CA_CKDIV4_EN = 1
4914 22:53:33.318819 CA_PREDIV_EN = 0
4915 22:53:33.322130 PH8_DLY = 0
4916 22:53:33.325184 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4917 22:53:33.328531 DQ_AAMCK_DIV = 4
4918 22:53:33.331945 CA_AAMCK_DIV = 4
4919 22:53:33.334913 CA_ADMCK_DIV = 4
4920 22:53:33.335435 DQ_TRACK_CA_EN = 0
4921 22:53:33.338397 CA_PICK = 933
4922 22:53:33.341782 CA_MCKIO = 933
4923 22:53:33.345051 MCKIO_SEMI = 0
4924 22:53:33.348660 PLL_FREQ = 3732
4925 22:53:33.351776 DQ_UI_PI_RATIO = 32
4926 22:53:33.355520 CA_UI_PI_RATIO = 0
4927 22:53:33.358672 ===================================
4928 22:53:33.361499 ===================================
4929 22:53:33.361965 memory_type:LPDDR4
4930 22:53:33.365157 GP_NUM : 10
4931 22:53:33.368199 SRAM_EN : 1
4932 22:53:33.368659 MD32_EN : 0
4933 22:53:33.371747 ===================================
4934 22:53:33.375162 [ANA_INIT] >>>>>>>>>>>>>>
4935 22:53:33.378542 <<<<<< [CONFIGURE PHASE]: ANA_TX
4936 22:53:33.381851 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4937 22:53:33.385254 ===================================
4938 22:53:33.388238 data_rate = 1866,PCW = 0X8f00
4939 22:53:33.391490 ===================================
4940 22:53:33.394996 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4941 22:53:33.398356 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4942 22:53:33.405039 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4943 22:53:33.408051 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4944 22:53:33.411537 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4945 22:53:33.414639 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4946 22:53:33.417921 [ANA_INIT] flow start
4947 22:53:33.421410 [ANA_INIT] PLL >>>>>>>>
4948 22:53:33.421915 [ANA_INIT] PLL <<<<<<<<
4949 22:53:33.424705 [ANA_INIT] MIDPI >>>>>>>>
4950 22:53:33.427963 [ANA_INIT] MIDPI <<<<<<<<
4951 22:53:33.428424 [ANA_INIT] DLL >>>>>>>>
4952 22:53:33.431141 [ANA_INIT] flow end
4953 22:53:33.434671 ============ LP4 DIFF to SE enter ============
4954 22:53:33.441384 ============ LP4 DIFF to SE exit ============
4955 22:53:33.441884 [ANA_INIT] <<<<<<<<<<<<<
4956 22:53:33.444674 [Flow] Enable top DCM control >>>>>
4957 22:53:33.448185 [Flow] Enable top DCM control <<<<<
4958 22:53:33.451729 Enable DLL master slave shuffle
4959 22:53:33.457922 ==============================================================
4960 22:53:33.458498 Gating Mode config
4961 22:53:33.464991 ==============================================================
4962 22:53:33.468599 Config description:
4963 22:53:33.474686 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4964 22:53:33.482031 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4965 22:53:33.488095 SELPH_MODE 0: By rank 1: By Phase
4966 22:53:33.495128 ==============================================================
4967 22:53:33.495718 GAT_TRACK_EN = 1
4968 22:53:33.498024 RX_GATING_MODE = 2
4969 22:53:33.501696 RX_GATING_TRACK_MODE = 2
4970 22:53:33.505257 SELPH_MODE = 1
4971 22:53:33.508063 PICG_EARLY_EN = 1
4972 22:53:33.511530 VALID_LAT_VALUE = 1
4973 22:53:33.517844 ==============================================================
4974 22:53:33.521403 Enter into Gating configuration >>>>
4975 22:53:33.525060 Exit from Gating configuration <<<<
4976 22:53:33.528082 Enter into DVFS_PRE_config >>>>>
4977 22:53:33.537825 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4978 22:53:33.541564 Exit from DVFS_PRE_config <<<<<
4979 22:53:33.544849 Enter into PICG configuration >>>>
4980 22:53:33.547883 Exit from PICG configuration <<<<
4981 22:53:33.551524 [RX_INPUT] configuration >>>>>
4982 22:53:33.552090 [RX_INPUT] configuration <<<<<
4983 22:53:33.557985 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4984 22:53:33.564572 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4985 22:53:33.567990 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4986 22:53:33.574489 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4987 22:53:33.581256 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4988 22:53:33.588094 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4989 22:53:33.591372 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4990 22:53:33.594698 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4991 22:53:33.601599 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4992 22:53:33.604587 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4993 22:53:33.607508 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4994 22:53:33.610953 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4995 22:53:33.614528 ===================================
4996 22:53:33.617546 LPDDR4 DRAM CONFIGURATION
4997 22:53:33.621258 ===================================
4998 22:53:33.624328 EX_ROW_EN[0] = 0x0
4999 22:53:33.624910 EX_ROW_EN[1] = 0x0
5000 22:53:33.627633 LP4Y_EN = 0x0
5001 22:53:33.628204 WORK_FSP = 0x0
5002 22:53:33.631732 WL = 0x3
5003 22:53:33.632307 RL = 0x3
5004 22:53:33.634568 BL = 0x2
5005 22:53:33.635038 RPST = 0x0
5006 22:53:33.638131 RD_PRE = 0x0
5007 22:53:33.638700 WR_PRE = 0x1
5008 22:53:33.641608 WR_PST = 0x0
5009 22:53:33.642173 DBI_WR = 0x0
5010 22:53:33.644464 DBI_RD = 0x0
5011 22:53:33.647979 OTF = 0x1
5012 22:53:33.648550 ===================================
5013 22:53:33.654566 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5014 22:53:33.657598 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5015 22:53:33.661448 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5016 22:53:33.664909 ===================================
5017 22:53:33.667876 LPDDR4 DRAM CONFIGURATION
5018 22:53:33.671061 ===================================
5019 22:53:33.674759 EX_ROW_EN[0] = 0x10
5020 22:53:33.675220 EX_ROW_EN[1] = 0x0
5021 22:53:33.678294 LP4Y_EN = 0x0
5022 22:53:33.678871 WORK_FSP = 0x0
5023 22:53:33.681733 WL = 0x3
5024 22:53:33.682317 RL = 0x3
5025 22:53:33.684501 BL = 0x2
5026 22:53:33.684975 RPST = 0x0
5027 22:53:33.687921 RD_PRE = 0x0
5028 22:53:33.688425 WR_PRE = 0x1
5029 22:53:33.691231 WR_PST = 0x0
5030 22:53:33.691705 DBI_WR = 0x0
5031 22:53:33.694748 DBI_RD = 0x0
5032 22:53:33.695324 OTF = 0x1
5033 22:53:33.697978 ===================================
5034 22:53:33.704466 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5035 22:53:33.709091 nWR fixed to 30
5036 22:53:33.712545 [ModeRegInit_LP4] CH0 RK0
5037 22:53:33.713073 [ModeRegInit_LP4] CH0 RK1
5038 22:53:33.715918 [ModeRegInit_LP4] CH1 RK0
5039 22:53:33.718890 [ModeRegInit_LP4] CH1 RK1
5040 22:53:33.719399 match AC timing 9
5041 22:53:33.725453 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5042 22:53:33.729269 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5043 22:53:33.732426 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5044 22:53:33.739253 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5045 22:53:33.742488 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5046 22:53:33.743172 ==
5047 22:53:33.745693 Dram Type= 6, Freq= 0, CH_0, rank 0
5048 22:53:33.748617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5049 22:53:33.749084 ==
5050 22:53:33.755890 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5051 22:53:33.762292 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5052 22:53:33.765702 [CA 0] Center 37 (7~68) winsize 62
5053 22:53:33.768663 [CA 1] Center 38 (7~69) winsize 63
5054 22:53:33.772339 [CA 2] Center 35 (5~66) winsize 62
5055 22:53:33.775213 [CA 3] Center 34 (4~65) winsize 62
5056 22:53:33.778594 [CA 4] Center 34 (4~64) winsize 61
5057 22:53:33.782039 [CA 5] Center 33 (3~64) winsize 62
5058 22:53:33.782503
5059 22:53:33.784965 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5060 22:53:33.785467
5061 22:53:33.788778 [CATrainingPosCal] consider 1 rank data
5062 22:53:33.792006 u2DelayCellTimex100 = 270/100 ps
5063 22:53:33.795843 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5064 22:53:33.798713 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5065 22:53:33.802019 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5066 22:53:33.805379 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5067 22:53:33.808375 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5068 22:53:33.812052 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5069 22:53:33.815515
5070 22:53:33.818943 CA PerBit enable=1, Macro0, CA PI delay=33
5071 22:53:33.819519
5072 22:53:33.821971 [CBTSetCACLKResult] CA Dly = 33
5073 22:53:33.822429 CS Dly: 7 (0~38)
5074 22:53:33.822791 ==
5075 22:53:33.825472 Dram Type= 6, Freq= 0, CH_0, rank 1
5076 22:53:33.828492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5077 22:53:33.829016 ==
5078 22:53:33.835673 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5079 22:53:33.842000 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5080 22:53:33.845546 [CA 0] Center 38 (7~69) winsize 63
5081 22:53:33.848440 [CA 1] Center 38 (8~69) winsize 62
5082 22:53:33.852074 [CA 2] Center 36 (6~66) winsize 61
5083 22:53:33.855017 [CA 3] Center 35 (5~66) winsize 62
5084 22:53:33.858340 [CA 4] Center 34 (4~65) winsize 62
5085 22:53:33.861789 [CA 5] Center 34 (4~65) winsize 62
5086 22:53:33.862344
5087 22:53:33.865187 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5088 22:53:33.865711
5089 22:53:33.868930 [CATrainingPosCal] consider 2 rank data
5090 22:53:33.872023 u2DelayCellTimex100 = 270/100 ps
5091 22:53:33.875081 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5092 22:53:33.878419 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5093 22:53:33.881836 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5094 22:53:33.885218 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5095 22:53:33.888552 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5096 22:53:33.895350 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5097 22:53:33.895913
5098 22:53:33.898623 CA PerBit enable=1, Macro0, CA PI delay=34
5099 22:53:33.899177
5100 22:53:33.902053 [CBTSetCACLKResult] CA Dly = 34
5101 22:53:33.902603 CS Dly: 7 (0~39)
5102 22:53:33.902968
5103 22:53:33.905358 ----->DramcWriteLeveling(PI) begin...
5104 22:53:33.905919 ==
5105 22:53:33.908416 Dram Type= 6, Freq= 0, CH_0, rank 0
5106 22:53:33.915120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5107 22:53:33.915676 ==
5108 22:53:33.918454 Write leveling (Byte 0): 35 => 35
5109 22:53:33.919007 Write leveling (Byte 1): 29 => 29
5110 22:53:33.921426 DramcWriteLeveling(PI) end<-----
5111 22:53:33.921884
5112 22:53:33.922245 ==
5113 22:53:33.925069 Dram Type= 6, Freq= 0, CH_0, rank 0
5114 22:53:33.931607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5115 22:53:33.932150 ==
5116 22:53:33.935407 [Gating] SW mode calibration
5117 22:53:33.941813 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5118 22:53:33.945236 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5119 22:53:33.951994 0 14 0 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
5120 22:53:33.954806 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5121 22:53:33.958241 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5122 22:53:33.965030 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5123 22:53:33.968479 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5124 22:53:33.971691 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5125 22:53:33.974750 0 14 24 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
5126 22:53:33.981740 0 14 28 | B1->B0 | 3131 2323 | 1 0 | (1 0) (1 0)
5127 22:53:33.985488 0 15 0 | B1->B0 | 2626 2323 | 1 0 | (1 0) (0 0)
5128 22:53:33.988678 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5129 22:53:33.995370 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5130 22:53:33.998752 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5131 22:53:34.002003 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5132 22:53:34.008785 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5133 22:53:34.011790 0 15 24 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
5134 22:53:34.014907 0 15 28 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
5135 22:53:34.021235 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5136 22:53:34.025446 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5137 22:53:34.028529 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5138 22:53:34.035315 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5139 22:53:34.038261 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5140 22:53:34.041574 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5141 22:53:34.048507 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5142 22:53:34.051749 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5143 22:53:34.054642 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5144 22:53:34.061155 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 22:53:34.064882 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 22:53:34.068328 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 22:53:34.074836 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 22:53:34.077943 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 22:53:34.081501 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 22:53:34.084752 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 22:53:34.091550 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 22:53:34.095079 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 22:53:34.098020 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 22:53:34.104776 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 22:53:34.108177 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 22:53:34.111594 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 22:53:34.118136 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5158 22:53:34.121350 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5159 22:53:34.124726 Total UI for P1: 0, mck2ui 16
5160 22:53:34.128012 best dqsien dly found for B0: ( 1, 2, 24)
5161 22:53:34.130961 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5162 22:53:34.137888 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5163 22:53:34.138464 Total UI for P1: 0, mck2ui 16
5164 22:53:34.144394 best dqsien dly found for B1: ( 1, 2, 30)
5165 22:53:34.147516 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5166 22:53:34.151117 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5167 22:53:34.151585
5168 22:53:34.154083 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5169 22:53:34.158086 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5170 22:53:34.160839 [Gating] SW calibration Done
5171 22:53:34.161339 ==
5172 22:53:34.164453 Dram Type= 6, Freq= 0, CH_0, rank 0
5173 22:53:34.167618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5174 22:53:34.168195 ==
5175 22:53:34.171312 RX Vref Scan: 0
5176 22:53:34.171880
5177 22:53:34.172254 RX Vref 0 -> 0, step: 1
5178 22:53:34.174513
5179 22:53:34.175084 RX Delay -80 -> 252, step: 8
5180 22:53:34.181180 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5181 22:53:34.184065 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5182 22:53:34.187251 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5183 22:53:34.190995 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5184 22:53:34.194045 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5185 22:53:34.197257 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5186 22:53:34.204215 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5187 22:53:34.207988 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5188 22:53:34.210923 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5189 22:53:34.214318 iDelay=208, Bit 9, Center 83 (0 ~ 167) 168
5190 22:53:34.217479 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5191 22:53:34.220963 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5192 22:53:34.227610 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5193 22:53:34.230941 iDelay=208, Bit 13, Center 95 (8 ~ 183) 176
5194 22:53:34.234411 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5195 22:53:34.237788 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5196 22:53:34.238259 ==
5197 22:53:34.240979 Dram Type= 6, Freq= 0, CH_0, rank 0
5198 22:53:34.244209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5199 22:53:34.244677 ==
5200 22:53:34.247391 DQS Delay:
5201 22:53:34.247855 DQS0 = 0, DQS1 = 0
5202 22:53:34.250653 DQM Delay:
5203 22:53:34.251119 DQM0 = 106, DQM1 = 91
5204 22:53:34.254119 DQ Delay:
5205 22:53:34.257168 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =103
5206 22:53:34.260566 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5207 22:53:34.263976 DQ8 =87, DQ9 =83, DQ10 =91, DQ11 =87
5208 22:53:34.267243 DQ12 =91, DQ13 =95, DQ14 =99, DQ15 =99
5209 22:53:34.267712
5210 22:53:34.268076
5211 22:53:34.268415 ==
5212 22:53:34.270490 Dram Type= 6, Freq= 0, CH_0, rank 0
5213 22:53:34.273586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5214 22:53:34.274191 ==
5215 22:53:34.274571
5216 22:53:34.274918
5217 22:53:34.276922 TX Vref Scan disable
5218 22:53:34.277426 == TX Byte 0 ==
5219 22:53:34.283239 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5220 22:53:34.286852 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5221 22:53:34.287096 == TX Byte 1 ==
5222 22:53:34.293130 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5223 22:53:34.296773 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5224 22:53:34.296933 ==
5225 22:53:34.300013 Dram Type= 6, Freq= 0, CH_0, rank 0
5226 22:53:34.303127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5227 22:53:34.303267 ==
5228 22:53:34.303376
5229 22:53:34.306380
5230 22:53:34.306499 TX Vref Scan disable
5231 22:53:34.309636 == TX Byte 0 ==
5232 22:53:34.313007 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5233 22:53:34.316241 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5234 22:53:34.319690 == TX Byte 1 ==
5235 22:53:34.323518 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5236 22:53:34.326470 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5237 22:53:34.330154
5238 22:53:34.330272 [DATLAT]
5239 22:53:34.330366 Freq=933, CH0 RK0
5240 22:53:34.330455
5241 22:53:34.333043 DATLAT Default: 0xd
5242 22:53:34.333162 0, 0xFFFF, sum = 0
5243 22:53:34.336818 1, 0xFFFF, sum = 0
5244 22:53:34.337038 2, 0xFFFF, sum = 0
5245 22:53:34.339738 3, 0xFFFF, sum = 0
5246 22:53:34.339902 4, 0xFFFF, sum = 0
5247 22:53:34.343302 5, 0xFFFF, sum = 0
5248 22:53:34.346773 6, 0xFFFF, sum = 0
5249 22:53:34.347032 7, 0xFFFF, sum = 0
5250 22:53:34.349641 8, 0xFFFF, sum = 0
5251 22:53:34.349855 9, 0xFFFF, sum = 0
5252 22:53:34.352943 10, 0x0, sum = 1
5253 22:53:34.353139 11, 0x0, sum = 2
5254 22:53:34.353294 12, 0x0, sum = 3
5255 22:53:34.356379 13, 0x0, sum = 4
5256 22:53:34.356609 best_step = 11
5257 22:53:34.356790
5258 22:53:34.360088 ==
5259 22:53:34.360369 Dram Type= 6, Freq= 0, CH_0, rank 0
5260 22:53:34.366909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5261 22:53:34.367274 ==
5262 22:53:34.367557 RX Vref Scan: 1
5263 22:53:34.367824
5264 22:53:34.369940 RX Vref 0 -> 0, step: 1
5265 22:53:34.370304
5266 22:53:34.373129 RX Delay -45 -> 252, step: 4
5267 22:53:34.373521
5268 22:53:34.376438 Set Vref, RX VrefLevel [Byte0]: 58
5269 22:53:34.379807 [Byte1]: 48
5270 22:53:34.380169
5271 22:53:34.383294 Final RX Vref Byte 0 = 58 to rank0
5272 22:53:34.386656 Final RX Vref Byte 1 = 48 to rank0
5273 22:53:34.389896 Final RX Vref Byte 0 = 58 to rank1
5274 22:53:34.393211 Final RX Vref Byte 1 = 48 to rank1==
5275 22:53:34.396438 Dram Type= 6, Freq= 0, CH_0, rank 0
5276 22:53:34.399852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5277 22:53:34.400325 ==
5278 22:53:34.403290 DQS Delay:
5279 22:53:34.403650 DQS0 = 0, DQS1 = 0
5280 22:53:34.406213 DQM Delay:
5281 22:53:34.406576 DQM0 = 107, DQM1 = 91
5282 22:53:34.406864 DQ Delay:
5283 22:53:34.409564 DQ0 =106, DQ1 =108, DQ2 =104, DQ3 =106
5284 22:53:34.416402 DQ4 =108, DQ5 =98, DQ6 =118, DQ7 =114
5285 22:53:34.416771 DQ8 =84, DQ9 =78, DQ10 =90, DQ11 =90
5286 22:53:34.422734 DQ12 =96, DQ13 =96, DQ14 =100, DQ15 =100
5287 22:53:34.422996
5288 22:53:34.423201
5289 22:53:34.429189 [DQSOSCAuto] RK0, (LSB)MR18= 0x2521, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 410 ps
5290 22:53:34.432549 CH0 RK0: MR19=505, MR18=2521
5291 22:53:34.439470 CH0_RK0: MR19=0x505, MR18=0x2521, DQSOSC=410, MR23=63, INC=64, DEC=42
5292 22:53:34.439673
5293 22:53:34.442474 ----->DramcWriteLeveling(PI) begin...
5294 22:53:34.442598 ==
5295 22:53:34.445865 Dram Type= 6, Freq= 0, CH_0, rank 1
5296 22:53:34.449107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5297 22:53:34.449217 ==
5298 22:53:34.452408 Write leveling (Byte 0): 33 => 33
5299 22:53:34.455746 Write leveling (Byte 1): 30 => 30
5300 22:53:34.459085 DramcWriteLeveling(PI) end<-----
5301 22:53:34.459173
5302 22:53:34.459241 ==
5303 22:53:34.462566 Dram Type= 6, Freq= 0, CH_0, rank 1
5304 22:53:34.465856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5305 22:53:34.465939 ==
5306 22:53:34.469242 [Gating] SW mode calibration
5307 22:53:34.476083 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5308 22:53:34.482543 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5309 22:53:34.485902 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5310 22:53:34.489072 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5311 22:53:34.495874 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5312 22:53:34.499417 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5313 22:53:34.502742 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5314 22:53:34.509414 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5315 22:53:34.512403 0 14 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
5316 22:53:34.515908 0 14 28 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (1 0)
5317 22:53:34.522589 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5318 22:53:34.526142 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5319 22:53:34.529065 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5320 22:53:34.536206 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5321 22:53:34.538943 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5322 22:53:34.542534 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5323 22:53:34.549264 0 15 24 | B1->B0 | 2626 2929 | 0 1 | (0 0) (0 0)
5324 22:53:34.552688 0 15 28 | B1->B0 | 3838 4545 | 1 0 | (0 0) (0 0)
5325 22:53:34.555936 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5326 22:53:34.562525 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5327 22:53:34.565988 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5328 22:53:34.569086 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5329 22:53:34.575975 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5330 22:53:34.578987 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5331 22:53:34.582216 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5332 22:53:34.588775 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5333 22:53:34.591978 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 22:53:34.595688 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 22:53:34.602094 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 22:53:34.605407 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 22:53:34.608753 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 22:53:34.615337 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 22:53:34.618560 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 22:53:34.622359 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 22:53:34.629026 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 22:53:34.632180 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 22:53:34.635608 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 22:53:34.642106 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 22:53:34.645532 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 22:53:34.648869 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 22:53:34.652023 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5348 22:53:34.658605 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5349 22:53:34.662323 Total UI for P1: 0, mck2ui 16
5350 22:53:34.665229 best dqsien dly found for B1: ( 1, 2, 24)
5351 22:53:34.668665 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5352 22:53:34.671695 Total UI for P1: 0, mck2ui 16
5353 22:53:34.675091 best dqsien dly found for B0: ( 1, 2, 26)
5354 22:53:34.678822 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5355 22:53:34.682241 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5356 22:53:34.682537
5357 22:53:34.685646 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5358 22:53:34.688575 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5359 22:53:34.692158 [Gating] SW calibration Done
5360 22:53:34.692376 ==
5361 22:53:34.694983 Dram Type= 6, Freq= 0, CH_0, rank 1
5362 22:53:34.701520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5363 22:53:34.701745 ==
5364 22:53:34.701918 RX Vref Scan: 0
5365 22:53:34.702080
5366 22:53:34.705184 RX Vref 0 -> 0, step: 1
5367 22:53:34.705441
5368 22:53:34.708385 RX Delay -80 -> 252, step: 8
5369 22:53:34.711667 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5370 22:53:34.714837 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5371 22:53:34.718578 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5372 22:53:34.721846 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5373 22:53:34.728450 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5374 22:53:34.731687 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5375 22:53:34.735669 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5376 22:53:34.738417 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5377 22:53:34.741981 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5378 22:53:34.745366 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5379 22:53:34.752253 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5380 22:53:34.755491 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5381 22:53:34.758602 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5382 22:53:34.761641 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5383 22:53:34.764969 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5384 22:53:34.768697 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5385 22:53:34.771772 ==
5386 22:53:34.775084 Dram Type= 6, Freq= 0, CH_0, rank 1
5387 22:53:34.778091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5388 22:53:34.778332 ==
5389 22:53:34.778520 DQS Delay:
5390 22:53:34.781342 DQS0 = 0, DQS1 = 0
5391 22:53:34.781531 DQM Delay:
5392 22:53:34.784898 DQM0 = 104, DQM1 = 89
5393 22:53:34.785139 DQ Delay:
5394 22:53:34.787915 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5395 22:53:34.791691 DQ4 =107, DQ5 =91, DQ6 =115, DQ7 =111
5396 22:53:34.794814 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5397 22:53:34.798329 DQ12 =91, DQ13 =91, DQ14 =99, DQ15 =95
5398 22:53:34.798504
5399 22:53:34.798627
5400 22:53:34.798741 ==
5401 22:53:34.801714 Dram Type= 6, Freq= 0, CH_0, rank 1
5402 22:53:34.805238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5403 22:53:34.805787 ==
5404 22:53:34.806156
5405 22:53:34.806498
5406 22:53:34.808154 TX Vref Scan disable
5407 22:53:34.811821 == TX Byte 0 ==
5408 22:53:34.814914 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5409 22:53:34.819025 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5410 22:53:34.821810 == TX Byte 1 ==
5411 22:53:34.824743 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5412 22:53:34.828142 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5413 22:53:34.828608 ==
5414 22:53:34.831599 Dram Type= 6, Freq= 0, CH_0, rank 1
5415 22:53:34.838493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5416 22:53:34.839062 ==
5417 22:53:34.839429
5418 22:53:34.839787
5419 22:53:34.840112 TX Vref Scan disable
5420 22:53:34.842272 == TX Byte 0 ==
5421 22:53:34.846185 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5422 22:53:34.849189 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5423 22:53:34.852515 == TX Byte 1 ==
5424 22:53:34.855854 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5425 22:53:34.862226 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5426 22:53:34.862784
5427 22:53:34.863154 [DATLAT]
5428 22:53:34.863498 Freq=933, CH0 RK1
5429 22:53:34.863827
5430 22:53:34.865757 DATLAT Default: 0xb
5431 22:53:34.866215 0, 0xFFFF, sum = 0
5432 22:53:34.869057 1, 0xFFFF, sum = 0
5433 22:53:34.869694 2, 0xFFFF, sum = 0
5434 22:53:34.872460 3, 0xFFFF, sum = 0
5435 22:53:34.875805 4, 0xFFFF, sum = 0
5436 22:53:34.876348 5, 0xFFFF, sum = 0
5437 22:53:34.878638 6, 0xFFFF, sum = 0
5438 22:53:34.879111 7, 0xFFFF, sum = 0
5439 22:53:34.882433 8, 0xFFFF, sum = 0
5440 22:53:34.883033 9, 0xFFFF, sum = 0
5441 22:53:34.885634 10, 0x0, sum = 1
5442 22:53:34.886269 11, 0x0, sum = 2
5443 22:53:34.888850 12, 0x0, sum = 3
5444 22:53:34.889473 13, 0x0, sum = 4
5445 22:53:34.889863 best_step = 11
5446 22:53:34.890204
5447 22:53:34.892338 ==
5448 22:53:34.892801 Dram Type= 6, Freq= 0, CH_0, rank 1
5449 22:53:34.899219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5450 22:53:34.899764 ==
5451 22:53:34.900132 RX Vref Scan: 0
5452 22:53:34.900474
5453 22:53:34.901948 RX Vref 0 -> 0, step: 1
5454 22:53:34.902409
5455 22:53:34.905435 RX Delay -53 -> 252, step: 4
5456 22:53:34.908988 iDelay=199, Bit 0, Center 104 (19 ~ 190) 172
5457 22:53:34.915493 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5458 22:53:34.918531 iDelay=199, Bit 2, Center 100 (15 ~ 186) 172
5459 22:53:34.922189 iDelay=199, Bit 3, Center 98 (15 ~ 182) 168
5460 22:53:34.925347 iDelay=199, Bit 4, Center 104 (19 ~ 190) 172
5461 22:53:34.928749 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5462 22:53:34.935368 iDelay=199, Bit 6, Center 110 (23 ~ 198) 176
5463 22:53:34.938598 iDelay=199, Bit 7, Center 110 (23 ~ 198) 176
5464 22:53:34.941898 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5465 22:53:34.945267 iDelay=199, Bit 9, Center 78 (-5 ~ 162) 168
5466 22:53:34.948643 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5467 22:53:34.951962 iDelay=199, Bit 11, Center 90 (7 ~ 174) 168
5468 22:53:34.958601 iDelay=199, Bit 12, Center 96 (11 ~ 182) 172
5469 22:53:34.961833 iDelay=199, Bit 13, Center 94 (11 ~ 178) 168
5470 22:53:34.965413 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5471 22:53:34.968379 iDelay=199, Bit 15, Center 100 (19 ~ 182) 164
5472 22:53:34.968933 ==
5473 22:53:34.972004 Dram Type= 6, Freq= 0, CH_0, rank 1
5474 22:53:34.978872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5475 22:53:34.979485 ==
5476 22:53:34.979861 DQS Delay:
5477 22:53:34.981927 DQS0 = 0, DQS1 = 0
5478 22:53:34.982389 DQM Delay:
5479 22:53:34.982751 DQM0 = 103, DQM1 = 92
5480 22:53:34.984938 DQ Delay:
5481 22:53:34.988569 DQ0 =104, DQ1 =106, DQ2 =100, DQ3 =98
5482 22:53:34.991653 DQ4 =104, DQ5 =98, DQ6 =110, DQ7 =110
5483 22:53:34.995212 DQ8 =84, DQ9 =78, DQ10 =94, DQ11 =90
5484 22:53:34.998666 DQ12 =96, DQ13 =94, DQ14 =100, DQ15 =100
5485 22:53:34.999233
5486 22:53:34.999597
5487 22:53:35.005255 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e0f, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 407 ps
5488 22:53:35.008706 CH0 RK1: MR19=505, MR18=2E0F
5489 22:53:35.014929 CH0_RK1: MR19=0x505, MR18=0x2E0F, DQSOSC=407, MR23=63, INC=65, DEC=43
5490 22:53:35.018692 [RxdqsGatingPostProcess] freq 933
5491 22:53:35.024926 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5492 22:53:35.025507 best DQS0 dly(2T, 0.5T) = (0, 10)
5493 22:53:35.028361 best DQS1 dly(2T, 0.5T) = (0, 10)
5494 22:53:35.031540 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5495 22:53:35.035506 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5496 22:53:35.038633 best DQS0 dly(2T, 0.5T) = (0, 10)
5497 22:53:35.041773 best DQS1 dly(2T, 0.5T) = (0, 10)
5498 22:53:35.045377 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5499 22:53:35.048302 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5500 22:53:35.051671 Pre-setting of DQS Precalculation
5501 22:53:35.055243 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5502 22:53:35.058593 ==
5503 22:53:35.061975 Dram Type= 6, Freq= 0, CH_1, rank 0
5504 22:53:35.065346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5505 22:53:35.065920 ==
5506 22:53:35.068591 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5507 22:53:35.075385 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5508 22:53:35.078922 [CA 0] Center 37 (7~68) winsize 62
5509 22:53:35.082166 [CA 1] Center 38 (8~68) winsize 61
5510 22:53:35.085857 [CA 2] Center 36 (6~66) winsize 61
5511 22:53:35.088928 [CA 3] Center 35 (5~65) winsize 61
5512 22:53:35.092047 [CA 4] Center 35 (5~66) winsize 62
5513 22:53:35.095251 [CA 5] Center 34 (4~65) winsize 62
5514 22:53:35.095775
5515 22:53:35.098607 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5516 22:53:35.099175
5517 22:53:35.102313 [CATrainingPosCal] consider 1 rank data
5518 22:53:35.105045 u2DelayCellTimex100 = 270/100 ps
5519 22:53:35.108574 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5520 22:53:35.112252 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5521 22:53:35.118930 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5522 22:53:35.121829 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5523 22:53:35.125221 CA4 delay=35 (5~66),Diff = 1 PI (6 cell)
5524 22:53:35.128496 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5525 22:53:35.129051
5526 22:53:35.132230 CA PerBit enable=1, Macro0, CA PI delay=34
5527 22:53:35.132696
5528 22:53:35.135440 [CBTSetCACLKResult] CA Dly = 34
5529 22:53:35.135999 CS Dly: 6 (0~37)
5530 22:53:35.136366 ==
5531 22:53:35.138922 Dram Type= 6, Freq= 0, CH_1, rank 1
5532 22:53:35.145517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5533 22:53:35.146095 ==
5534 22:53:35.148619 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5535 22:53:35.155394 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5536 22:53:35.158840 [CA 0] Center 38 (8~69) winsize 62
5537 22:53:35.162375 [CA 1] Center 38 (7~69) winsize 63
5538 22:53:35.165569 [CA 2] Center 36 (6~66) winsize 61
5539 22:53:35.168783 [CA 3] Center 35 (5~65) winsize 61
5540 22:53:35.171969 [CA 4] Center 36 (6~66) winsize 61
5541 22:53:35.175519 [CA 5] Center 35 (5~65) winsize 61
5542 22:53:35.176077
5543 22:53:35.179142 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5544 22:53:35.179698
5545 22:53:35.181864 [CATrainingPosCal] consider 2 rank data
5546 22:53:35.185089 u2DelayCellTimex100 = 270/100 ps
5547 22:53:35.188290 CA0 delay=38 (8~68),Diff = 3 PI (18 cell)
5548 22:53:35.195210 CA1 delay=38 (8~68),Diff = 3 PI (18 cell)
5549 22:53:35.198235 CA2 delay=36 (6~66),Diff = 1 PI (6 cell)
5550 22:53:35.201870 CA3 delay=35 (5~65),Diff = 0 PI (0 cell)
5551 22:53:35.205167 CA4 delay=36 (6~66),Diff = 1 PI (6 cell)
5552 22:53:35.208464 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
5553 22:53:35.209025
5554 22:53:35.211820 CA PerBit enable=1, Macro0, CA PI delay=35
5555 22:53:35.212382
5556 22:53:35.214781 [CBTSetCACLKResult] CA Dly = 35
5557 22:53:35.218107 CS Dly: 7 (0~39)
5558 22:53:35.218573
5559 22:53:35.221745 ----->DramcWriteLeveling(PI) begin...
5560 22:53:35.222305 ==
5561 22:53:35.225257 Dram Type= 6, Freq= 0, CH_1, rank 0
5562 22:53:35.228231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5563 22:53:35.228813 ==
5564 22:53:35.231565 Write leveling (Byte 0): 25 => 25
5565 22:53:35.234925 Write leveling (Byte 1): 30 => 30
5566 22:53:35.238169 DramcWriteLeveling(PI) end<-----
5567 22:53:35.238666
5568 22:53:35.239038 ==
5569 22:53:35.241381 Dram Type= 6, Freq= 0, CH_1, rank 0
5570 22:53:35.244819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5571 22:53:35.245536 ==
5572 22:53:35.248067 [Gating] SW mode calibration
5573 22:53:35.254554 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5574 22:53:35.261403 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5575 22:53:35.264802 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5576 22:53:35.267915 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5577 22:53:35.274461 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5578 22:53:35.277685 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5579 22:53:35.280953 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5580 22:53:35.288038 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5581 22:53:35.291335 0 14 24 | B1->B0 | 3131 3333 | 1 0 | (1 0) (0 1)
5582 22:53:35.294698 0 14 28 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
5583 22:53:35.301667 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5584 22:53:35.304752 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5585 22:53:35.307397 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5586 22:53:35.314342 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5587 22:53:35.317569 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5588 22:53:35.320855 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5589 22:53:35.328010 0 15 24 | B1->B0 | 2929 2f2f | 1 0 | (0 0) (1 1)
5590 22:53:35.330824 0 15 28 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
5591 22:53:35.334136 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5592 22:53:35.340978 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5593 22:53:35.344012 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5594 22:53:35.347171 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5595 22:53:35.353973 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5596 22:53:35.357229 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5597 22:53:35.360607 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5598 22:53:35.367216 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 22:53:35.370304 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 22:53:35.373918 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 22:53:35.380266 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 22:53:35.383651 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 22:53:35.387207 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 22:53:35.390577 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 22:53:35.396971 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 22:53:35.400023 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 22:53:35.406806 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 22:53:35.409933 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 22:53:35.413264 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 22:53:35.420084 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 22:53:35.423235 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 22:53:35.426849 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 22:53:35.429981 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5614 22:53:35.436839 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5615 22:53:35.439803 Total UI for P1: 0, mck2ui 16
5616 22:53:35.443605 best dqsien dly found for B0: ( 1, 2, 24)
5617 22:53:35.446699 Total UI for P1: 0, mck2ui 16
5618 22:53:35.449884 best dqsien dly found for B1: ( 1, 2, 24)
5619 22:53:35.453700 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5620 22:53:35.456470 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5621 22:53:35.456931
5622 22:53:35.460077 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5623 22:53:35.463101 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5624 22:53:35.466241 [Gating] SW calibration Done
5625 22:53:35.466716 ==
5626 22:53:35.469460 Dram Type= 6, Freq= 0, CH_1, rank 0
5627 22:53:35.472932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5628 22:53:35.473376 ==
5629 22:53:35.476234 RX Vref Scan: 0
5630 22:53:35.476648
5631 22:53:35.479492 RX Vref 0 -> 0, step: 1
5632 22:53:35.480032
5633 22:53:35.480377 RX Delay -80 -> 252, step: 8
5634 22:53:35.486148 iDelay=208, Bit 0, Center 103 (16 ~ 191) 176
5635 22:53:35.489644 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5636 22:53:35.493067 iDelay=208, Bit 2, Center 95 (8 ~ 183) 176
5637 22:53:35.496264 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5638 22:53:35.499241 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5639 22:53:35.502921 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5640 22:53:35.509592 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5641 22:53:35.513020 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5642 22:53:35.516320 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5643 22:53:35.519931 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5644 22:53:35.522561 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5645 22:53:35.526254 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5646 22:53:35.533051 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5647 22:53:35.536284 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5648 22:53:35.539639 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5649 22:53:35.543220 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5650 22:53:35.543739 ==
5651 22:53:35.546067 Dram Type= 6, Freq= 0, CH_1, rank 0
5652 22:53:35.549789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5653 22:53:35.552763 ==
5654 22:53:35.553177 DQS Delay:
5655 22:53:35.553546 DQS0 = 0, DQS1 = 0
5656 22:53:35.556072 DQM Delay:
5657 22:53:35.556486 DQM0 = 101, DQM1 = 95
5658 22:53:35.559477 DQ Delay:
5659 22:53:35.562519 DQ0 =103, DQ1 =95, DQ2 =95, DQ3 =99
5660 22:53:35.566277 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5661 22:53:35.569380 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =91
5662 22:53:35.572893 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =99
5663 22:53:35.573454
5664 22:53:35.573792
5665 22:53:35.574105 ==
5666 22:53:35.576154 Dram Type= 6, Freq= 0, CH_1, rank 0
5667 22:53:35.579128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5668 22:53:35.579549 ==
5669 22:53:35.579875
5670 22:53:35.580186
5671 22:53:35.582868 TX Vref Scan disable
5672 22:53:35.583386 == TX Byte 0 ==
5673 22:53:35.589118 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5674 22:53:35.592834 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5675 22:53:35.593253 == TX Byte 1 ==
5676 22:53:35.599295 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5677 22:53:35.602681 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5678 22:53:35.603203 ==
5679 22:53:35.606206 Dram Type= 6, Freq= 0, CH_1, rank 0
5680 22:53:35.608974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5681 22:53:35.609526 ==
5682 22:53:35.612417
5683 22:53:35.612829
5684 22:53:35.613148 TX Vref Scan disable
5685 22:53:35.615476 == TX Byte 0 ==
5686 22:53:35.619219 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5687 22:53:35.625630 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5688 22:53:35.626052 == TX Byte 1 ==
5689 22:53:35.629394 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5690 22:53:35.632761 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5691 22:53:35.635693
5692 22:53:35.636209 [DATLAT]
5693 22:53:35.636543 Freq=933, CH1 RK0
5694 22:53:35.636848
5695 22:53:35.638762 DATLAT Default: 0xd
5696 22:53:35.639174 0, 0xFFFF, sum = 0
5697 22:53:35.642236 1, 0xFFFF, sum = 0
5698 22:53:35.642663 2, 0xFFFF, sum = 0
5699 22:53:35.645904 3, 0xFFFF, sum = 0
5700 22:53:35.646325 4, 0xFFFF, sum = 0
5701 22:53:35.649126 5, 0xFFFF, sum = 0
5702 22:53:35.652692 6, 0xFFFF, sum = 0
5703 22:53:35.653219 7, 0xFFFF, sum = 0
5704 22:53:35.656085 8, 0xFFFF, sum = 0
5705 22:53:35.656607 9, 0xFFFF, sum = 0
5706 22:53:35.659038 10, 0x0, sum = 1
5707 22:53:35.659463 11, 0x0, sum = 2
5708 22:53:35.659796 12, 0x0, sum = 3
5709 22:53:35.662386 13, 0x0, sum = 4
5710 22:53:35.662808 best_step = 11
5711 22:53:35.663135
5712 22:53:35.665652 ==
5713 22:53:35.666068 Dram Type= 6, Freq= 0, CH_1, rank 0
5714 22:53:35.672304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5715 22:53:35.672770 ==
5716 22:53:35.673113 RX Vref Scan: 1
5717 22:53:35.673452
5718 22:53:35.675643 RX Vref 0 -> 0, step: 1
5719 22:53:35.676057
5720 22:53:35.679291 RX Delay -53 -> 252, step: 4
5721 22:53:35.679709
5722 22:53:35.682099 Set Vref, RX VrefLevel [Byte0]: 53
5723 22:53:35.685655 [Byte1]: 50
5724 22:53:35.686072
5725 22:53:35.689102 Final RX Vref Byte 0 = 53 to rank0
5726 22:53:35.692095 Final RX Vref Byte 1 = 50 to rank0
5727 22:53:35.695399 Final RX Vref Byte 0 = 53 to rank1
5728 22:53:35.699351 Final RX Vref Byte 1 = 50 to rank1==
5729 22:53:35.702442 Dram Type= 6, Freq= 0, CH_1, rank 0
5730 22:53:35.705556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5731 22:53:35.706080 ==
5732 22:53:35.709179 DQS Delay:
5733 22:53:35.709725 DQS0 = 0, DQS1 = 0
5734 22:53:35.712091 DQM Delay:
5735 22:53:35.712503 DQM0 = 104, DQM1 = 98
5736 22:53:35.712830 DQ Delay:
5737 22:53:35.715443 DQ0 =110, DQ1 =98, DQ2 =96, DQ3 =102
5738 22:53:35.718742 DQ4 =104, DQ5 =112, DQ6 =112, DQ7 =102
5739 22:53:35.722244 DQ8 =86, DQ9 =88, DQ10 =102, DQ11 =92
5740 22:53:35.728974 DQ12 =108, DQ13 =102, DQ14 =102, DQ15 =104
5741 22:53:35.729531
5742 22:53:35.729867
5743 22:53:35.735575 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a32, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
5744 22:53:35.739195 CH1 RK0: MR19=505, MR18=1A32
5745 22:53:35.745800 CH1_RK0: MR19=0x505, MR18=0x1A32, DQSOSC=406, MR23=63, INC=65, DEC=43
5746 22:53:35.746316
5747 22:53:35.748903 ----->DramcWriteLeveling(PI) begin...
5748 22:53:35.749469 ==
5749 22:53:35.752046 Dram Type= 6, Freq= 0, CH_1, rank 1
5750 22:53:35.755761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5751 22:53:35.756277 ==
5752 22:53:35.758940 Write leveling (Byte 0): 29 => 29
5753 22:53:35.762752 Write leveling (Byte 1): 29 => 29
5754 22:53:35.765411 DramcWriteLeveling(PI) end<-----
5755 22:53:35.765829
5756 22:53:35.766152 ==
5757 22:53:35.769181 Dram Type= 6, Freq= 0, CH_1, rank 1
5758 22:53:35.772327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5759 22:53:35.772849 ==
5760 22:53:35.775419 [Gating] SW mode calibration
5761 22:53:35.782343 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5762 22:53:35.789131 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5763 22:53:35.792545 0 14 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5764 22:53:35.795188 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5765 22:53:35.802067 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5766 22:53:35.805443 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5767 22:53:35.808895 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5768 22:53:35.815689 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5769 22:53:35.818771 0 14 24 | B1->B0 | 2f2f 3333 | 1 0 | (1 1) (0 0)
5770 22:53:35.822033 0 14 28 | B1->B0 | 2626 2c2c | 0 0 | (0 0) (1 0)
5771 22:53:35.829018 0 15 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5772 22:53:35.832473 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5773 22:53:35.835351 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5774 22:53:35.842153 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5775 22:53:35.845288 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5776 22:53:35.848788 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5777 22:53:35.855874 0 15 24 | B1->B0 | 2d2d 2525 | 1 0 | (0 0) (0 0)
5778 22:53:35.859261 0 15 28 | B1->B0 | 3e3e 3939 | 0 0 | (0 0) (0 0)
5779 22:53:35.862209 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5780 22:53:35.868793 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5781 22:53:35.872192 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5782 22:53:35.875629 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5783 22:53:35.882115 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5784 22:53:35.892039 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5785 22:53:35.892618 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5786 22:53:35.895699 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5787 22:53:35.898766 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 22:53:35.901798 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 22:53:35.905411 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 22:53:35.912078 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 22:53:35.915753 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 22:53:35.918492 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 22:53:35.925484 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 22:53:35.928891 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 22:53:35.932144 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 22:53:35.938770 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 22:53:35.941798 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 22:53:35.945490 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 22:53:35.952126 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 22:53:35.955266 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 22:53:35.958663 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5802 22:53:35.965372 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5803 22:53:35.968441 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5804 22:53:35.971852 Total UI for P1: 0, mck2ui 16
5805 22:53:35.975124 best dqsien dly found for B0: ( 1, 2, 28)
5806 22:53:35.978308 Total UI for P1: 0, mck2ui 16
5807 22:53:35.981522 best dqsien dly found for B1: ( 1, 2, 26)
5808 22:53:35.985406 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5809 22:53:35.988808 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5810 22:53:35.989421
5811 22:53:35.991592 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5812 22:53:35.995951 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5813 22:53:35.998262 [Gating] SW calibration Done
5814 22:53:35.998728 ==
5815 22:53:36.001543 Dram Type= 6, Freq= 0, CH_1, rank 1
5816 22:53:36.005167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5817 22:53:36.008013 ==
5818 22:53:36.008573 RX Vref Scan: 0
5819 22:53:36.008938
5820 22:53:36.011627 RX Vref 0 -> 0, step: 1
5821 22:53:36.012109
5822 22:53:36.014793 RX Delay -80 -> 252, step: 8
5823 22:53:36.018155 iDelay=200, Bit 0, Center 103 (16 ~ 191) 176
5824 22:53:36.021421 iDelay=200, Bit 1, Center 95 (8 ~ 183) 176
5825 22:53:36.024864 iDelay=200, Bit 2, Center 87 (0 ~ 175) 176
5826 22:53:36.028346 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5827 22:53:36.031819 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5828 22:53:36.037964 iDelay=200, Bit 5, Center 107 (16 ~ 199) 184
5829 22:53:36.041742 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5830 22:53:36.044810 iDelay=200, Bit 7, Center 99 (8 ~ 191) 184
5831 22:53:36.048285 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5832 22:53:36.051711 iDelay=200, Bit 9, Center 87 (0 ~ 175) 176
5833 22:53:36.055197 iDelay=200, Bit 10, Center 95 (8 ~ 183) 176
5834 22:53:36.061594 iDelay=200, Bit 11, Center 91 (0 ~ 183) 184
5835 22:53:36.064626 iDelay=200, Bit 12, Center 103 (8 ~ 199) 192
5836 22:53:36.068261 iDelay=200, Bit 13, Center 99 (8 ~ 191) 184
5837 22:53:36.071641 iDelay=200, Bit 14, Center 103 (8 ~ 199) 192
5838 22:53:36.075223 iDelay=200, Bit 15, Center 103 (8 ~ 199) 192
5839 22:53:36.075785 ==
5840 22:53:36.077800 Dram Type= 6, Freq= 0, CH_1, rank 1
5841 22:53:36.084596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5842 22:53:36.085162 ==
5843 22:53:36.085588 DQS Delay:
5844 22:53:36.088099 DQS0 = 0, DQS1 = 0
5845 22:53:36.088681 DQM Delay:
5846 22:53:36.091264 DQM0 = 100, DQM1 = 95
5847 22:53:36.091733 DQ Delay:
5848 22:53:36.094882 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =99
5849 22:53:36.097872 DQ4 =103, DQ5 =107, DQ6 =107, DQ7 =99
5850 22:53:36.101257 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =91
5851 22:53:36.104178 DQ12 =103, DQ13 =99, DQ14 =103, DQ15 =103
5852 22:53:36.104644
5853 22:53:36.105002
5854 22:53:36.105368 ==
5855 22:53:36.108209 Dram Type= 6, Freq= 0, CH_1, rank 1
5856 22:53:36.111182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5857 22:53:36.111744 ==
5858 22:53:36.112111
5859 22:53:36.112448
5860 22:53:36.114575 TX Vref Scan disable
5861 22:53:36.117531 == TX Byte 0 ==
5862 22:53:36.121083 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5863 22:53:36.124278 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5864 22:53:36.127777 == TX Byte 1 ==
5865 22:53:36.130959 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5866 22:53:36.134165 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5867 22:53:36.134634 ==
5868 22:53:36.137475 Dram Type= 6, Freq= 0, CH_1, rank 1
5869 22:53:36.144674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5870 22:53:36.145242 ==
5871 22:53:36.145649
5872 22:53:36.145991
5873 22:53:36.146317 TX Vref Scan disable
5874 22:53:36.148271 == TX Byte 0 ==
5875 22:53:36.151659 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5876 22:53:36.155102 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5877 22:53:36.158398 == TX Byte 1 ==
5878 22:53:36.161866 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5879 22:53:36.165010 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5880 22:53:36.168430
5881 22:53:36.168986 [DATLAT]
5882 22:53:36.169388 Freq=933, CH1 RK1
5883 22:53:36.169737
5884 22:53:36.171980 DATLAT Default: 0xb
5885 22:53:36.172539 0, 0xFFFF, sum = 0
5886 22:53:36.174954 1, 0xFFFF, sum = 0
5887 22:53:36.175522 2, 0xFFFF, sum = 0
5888 22:53:36.178073 3, 0xFFFF, sum = 0
5889 22:53:36.181472 4, 0xFFFF, sum = 0
5890 22:53:36.182037 5, 0xFFFF, sum = 0
5891 22:53:36.185223 6, 0xFFFF, sum = 0
5892 22:53:36.185827 7, 0xFFFF, sum = 0
5893 22:53:36.187984 8, 0xFFFF, sum = 0
5894 22:53:36.188450 9, 0xFFFF, sum = 0
5895 22:53:36.191148 10, 0x0, sum = 1
5896 22:53:36.191636 11, 0x0, sum = 2
5897 22:53:36.192009 12, 0x0, sum = 3
5898 22:53:36.194851 13, 0x0, sum = 4
5899 22:53:36.195419 best_step = 11
5900 22:53:36.195787
5901 22:53:36.197894 ==
5902 22:53:36.198453 Dram Type= 6, Freq= 0, CH_1, rank 1
5903 22:53:36.204742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5904 22:53:36.205332 ==
5905 22:53:36.205713 RX Vref Scan: 0
5906 22:53:36.206056
5907 22:53:36.208064 RX Vref 0 -> 0, step: 1
5908 22:53:36.208626
5909 22:53:36.211481 RX Delay -53 -> 252, step: 4
5910 22:53:36.215413 iDelay=199, Bit 0, Center 110 (35 ~ 186) 152
5911 22:53:36.221191 iDelay=199, Bit 1, Center 98 (19 ~ 178) 160
5912 22:53:36.224915 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5913 22:53:36.228088 iDelay=199, Bit 3, Center 102 (19 ~ 186) 168
5914 22:53:36.231251 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5915 22:53:36.234570 iDelay=199, Bit 5, Center 114 (31 ~ 198) 168
5916 22:53:36.241124 iDelay=199, Bit 6, Center 114 (35 ~ 194) 160
5917 22:53:36.244746 iDelay=199, Bit 7, Center 102 (23 ~ 182) 160
5918 22:53:36.247959 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5919 22:53:36.251354 iDelay=199, Bit 9, Center 88 (7 ~ 170) 164
5920 22:53:36.254764 iDelay=199, Bit 10, Center 98 (15 ~ 182) 168
5921 22:53:36.258234 iDelay=199, Bit 11, Center 94 (11 ~ 178) 168
5922 22:53:36.264908 iDelay=199, Bit 12, Center 106 (19 ~ 194) 176
5923 22:53:36.268456 iDelay=199, Bit 13, Center 104 (19 ~ 190) 172
5924 22:53:36.271525 iDelay=199, Bit 14, Center 104 (19 ~ 190) 172
5925 22:53:36.274945 iDelay=199, Bit 15, Center 108 (23 ~ 194) 172
5926 22:53:36.275532 ==
5927 22:53:36.278223 Dram Type= 6, Freq= 0, CH_1, rank 1
5928 22:53:36.284911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5929 22:53:36.285505 ==
5930 22:53:36.285877 DQS Delay:
5931 22:53:36.286214 DQS0 = 0, DQS1 = 0
5932 22:53:36.287877 DQM Delay:
5933 22:53:36.288339 DQM0 = 105, DQM1 = 98
5934 22:53:36.291314 DQ Delay:
5935 22:53:36.294826 DQ0 =110, DQ1 =98, DQ2 =94, DQ3 =102
5936 22:53:36.298088 DQ4 =106, DQ5 =114, DQ6 =114, DQ7 =102
5937 22:53:36.301523 DQ8 =86, DQ9 =88, DQ10 =98, DQ11 =94
5938 22:53:36.304744 DQ12 =106, DQ13 =104, DQ14 =104, DQ15 =108
5939 22:53:36.305323
5940 22:53:36.305695
5941 22:53:36.311415 [DQSOSCAuto] RK1, (LSB)MR18= 0x20fe, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 411 ps
5942 22:53:36.314742 CH1 RK1: MR19=504, MR18=20FE
5943 22:53:36.321468 CH1_RK1: MR19=0x504, MR18=0x20FE, DQSOSC=411, MR23=63, INC=64, DEC=42
5944 22:53:36.324517 [RxdqsGatingPostProcess] freq 933
5945 22:53:36.331258 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5946 22:53:36.331810 best DQS0 dly(2T, 0.5T) = (0, 10)
5947 22:53:36.334467 best DQS1 dly(2T, 0.5T) = (0, 10)
5948 22:53:36.338163 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5949 22:53:36.341162 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5950 22:53:36.344565 best DQS0 dly(2T, 0.5T) = (0, 10)
5951 22:53:36.348120 best DQS1 dly(2T, 0.5T) = (0, 10)
5952 22:53:36.351062 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5953 22:53:36.354711 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5954 22:53:36.357869 Pre-setting of DQS Precalculation
5955 22:53:36.364531 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5956 22:53:36.371412 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5957 22:53:36.377756 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5958 22:53:36.378321
5959 22:53:36.378685
5960 22:53:36.381454 [Calibration Summary] 1866 Mbps
5961 22:53:36.382016 CH 0, Rank 0
5962 22:53:36.384240 SW Impedance : PASS
5963 22:53:36.387539 DUTY Scan : NO K
5964 22:53:36.388098 ZQ Calibration : PASS
5965 22:53:36.390935 Jitter Meter : NO K
5966 22:53:36.391507 CBT Training : PASS
5967 22:53:36.394223 Write leveling : PASS
5968 22:53:36.397450 RX DQS gating : PASS
5969 22:53:36.398013 RX DQ/DQS(RDDQC) : PASS
5970 22:53:36.400862 TX DQ/DQS : PASS
5971 22:53:36.404035 RX DATLAT : PASS
5972 22:53:36.404594 RX DQ/DQS(Engine): PASS
5973 22:53:36.407357 TX OE : NO K
5974 22:53:36.407914 All Pass.
5975 22:53:36.408283
5976 22:53:36.410665 CH 0, Rank 1
5977 22:53:36.411226 SW Impedance : PASS
5978 22:53:36.414393 DUTY Scan : NO K
5979 22:53:36.417450 ZQ Calibration : PASS
5980 22:53:36.418119 Jitter Meter : NO K
5981 22:53:36.420608 CBT Training : PASS
5982 22:53:36.423799 Write leveling : PASS
5983 22:53:36.424262 RX DQS gating : PASS
5984 22:53:36.427200 RX DQ/DQS(RDDQC) : PASS
5985 22:53:36.430162 TX DQ/DQS : PASS
5986 22:53:36.430624 RX DATLAT : PASS
5987 22:53:36.433695 RX DQ/DQS(Engine): PASS
5988 22:53:36.436987 TX OE : NO K
5989 22:53:36.437606 All Pass.
5990 22:53:36.437980
5991 22:53:36.438317 CH 1, Rank 0
5992 22:53:36.440514 SW Impedance : PASS
5993 22:53:36.443741 DUTY Scan : NO K
5994 22:53:36.444295 ZQ Calibration : PASS
5995 22:53:36.447011 Jitter Meter : NO K
5996 22:53:36.450259 CBT Training : PASS
5997 22:53:36.450741 Write leveling : PASS
5998 22:53:36.453737 RX DQS gating : PASS
5999 22:53:36.454293 RX DQ/DQS(RDDQC) : PASS
6000 22:53:36.456909 TX DQ/DQS : PASS
6001 22:53:36.460290 RX DATLAT : PASS
6002 22:53:36.460852 RX DQ/DQS(Engine): PASS
6003 22:53:36.463627 TX OE : NO K
6004 22:53:36.464188 All Pass.
6005 22:53:36.464557
6006 22:53:36.467252 CH 1, Rank 1
6007 22:53:36.467816 SW Impedance : PASS
6008 22:53:36.470011 DUTY Scan : NO K
6009 22:53:36.473435 ZQ Calibration : PASS
6010 22:53:36.473897 Jitter Meter : NO K
6011 22:53:36.476942 CBT Training : PASS
6012 22:53:36.480243 Write leveling : PASS
6013 22:53:36.480771 RX DQS gating : PASS
6014 22:53:36.483691 RX DQ/DQS(RDDQC) : PASS
6015 22:53:36.487006 TX DQ/DQS : PASS
6016 22:53:36.487566 RX DATLAT : PASS
6017 22:53:36.490193 RX DQ/DQS(Engine): PASS
6018 22:53:36.493465 TX OE : NO K
6019 22:53:36.494025 All Pass.
6020 22:53:36.494392
6021 22:53:36.494729 DramC Write-DBI off
6022 22:53:36.496740 PER_BANK_REFRESH: Hybrid Mode
6023 22:53:36.499939 TX_TRACKING: ON
6024 22:53:36.506896 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6025 22:53:36.510308 [FAST_K] Save calibration result to emmc
6026 22:53:36.516701 dramc_set_vcore_voltage set vcore to 650000
6027 22:53:36.517248 Read voltage for 400, 6
6028 22:53:36.519962 Vio18 = 0
6029 22:53:36.520422 Vcore = 650000
6030 22:53:36.520783 Vdram = 0
6031 22:53:36.521201 Vddq = 0
6032 22:53:36.523302 Vmddr = 0
6033 22:53:36.526831 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6034 22:53:36.533437 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6035 22:53:36.536759 MEM_TYPE=3, freq_sel=20
6036 22:53:36.537467 sv_algorithm_assistance_LP4_800
6037 22:53:36.543264 ============ PULL DRAM RESETB DOWN ============
6038 22:53:36.546512 ========== PULL DRAM RESETB DOWN end =========
6039 22:53:36.549741 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6040 22:53:36.553482 ===================================
6041 22:53:36.556575 LPDDR4 DRAM CONFIGURATION
6042 22:53:36.560049 ===================================
6043 22:53:36.562996 EX_ROW_EN[0] = 0x0
6044 22:53:36.563416 EX_ROW_EN[1] = 0x0
6045 22:53:36.566287 LP4Y_EN = 0x0
6046 22:53:36.566705 WORK_FSP = 0x0
6047 22:53:36.569701 WL = 0x2
6048 22:53:36.570166 RL = 0x2
6049 22:53:36.573024 BL = 0x2
6050 22:53:36.573552 RPST = 0x0
6051 22:53:36.576415 RD_PRE = 0x0
6052 22:53:36.576921 WR_PRE = 0x1
6053 22:53:36.579819 WR_PST = 0x0
6054 22:53:36.580281 DBI_WR = 0x0
6055 22:53:36.583420 DBI_RD = 0x0
6056 22:53:36.584010 OTF = 0x1
6057 22:53:36.586526 ===================================
6058 22:53:36.589804 ===================================
6059 22:53:36.593436 ANA top config
6060 22:53:36.596376 ===================================
6061 22:53:36.600567 DLL_ASYNC_EN = 0
6062 22:53:36.601119 ALL_SLAVE_EN = 1
6063 22:53:36.603699 NEW_RANK_MODE = 1
6064 22:53:36.606962 DLL_IDLE_MODE = 1
6065 22:53:36.609936 LP45_APHY_COMB_EN = 1
6066 22:53:36.610493 TX_ODT_DIS = 1
6067 22:53:36.613276 NEW_8X_MODE = 1
6068 22:53:36.616577 ===================================
6069 22:53:36.620158 ===================================
6070 22:53:36.623117 data_rate = 800
6071 22:53:36.626615 CKR = 1
6072 22:53:36.629787 DQ_P2S_RATIO = 4
6073 22:53:36.633216 ===================================
6074 22:53:36.636452 CA_P2S_RATIO = 4
6075 22:53:36.637032 DQ_CA_OPEN = 0
6076 22:53:36.639831 DQ_SEMI_OPEN = 1
6077 22:53:36.643154 CA_SEMI_OPEN = 1
6078 22:53:36.646474 CA_FULL_RATE = 0
6079 22:53:36.650114 DQ_CKDIV4_EN = 0
6080 22:53:36.653270 CA_CKDIV4_EN = 1
6081 22:53:36.653915 CA_PREDIV_EN = 0
6082 22:53:36.656617 PH8_DLY = 0
6083 22:53:36.659820 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6084 22:53:36.662999 DQ_AAMCK_DIV = 0
6085 22:53:36.666375 CA_AAMCK_DIV = 0
6086 22:53:36.669668 CA_ADMCK_DIV = 4
6087 22:53:36.670248 DQ_TRACK_CA_EN = 0
6088 22:53:36.672896 CA_PICK = 800
6089 22:53:36.676396 CA_MCKIO = 400
6090 22:53:36.680050 MCKIO_SEMI = 400
6091 22:53:36.682986 PLL_FREQ = 3016
6092 22:53:36.686508 DQ_UI_PI_RATIO = 32
6093 22:53:36.689571 CA_UI_PI_RATIO = 32
6094 22:53:36.693156 ===================================
6095 22:53:36.696587 ===================================
6096 22:53:36.697148 memory_type:LPDDR4
6097 22:53:36.699618 GP_NUM : 10
6098 22:53:36.703197 SRAM_EN : 1
6099 22:53:36.703753 MD32_EN : 0
6100 22:53:36.706305 ===================================
6101 22:53:36.709690 [ANA_INIT] >>>>>>>>>>>>>>
6102 22:53:36.712962 <<<<<< [CONFIGURE PHASE]: ANA_TX
6103 22:53:36.716286 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6104 22:53:36.719379 ===================================
6105 22:53:36.722744 data_rate = 800,PCW = 0X7400
6106 22:53:36.726210 ===================================
6107 22:53:36.729187 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6108 22:53:36.732689 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6109 22:53:36.745958 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6110 22:53:36.749332 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6111 22:53:36.752923 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6112 22:53:36.756275 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6113 22:53:36.759288 [ANA_INIT] flow start
6114 22:53:36.762341 [ANA_INIT] PLL >>>>>>>>
6115 22:53:36.762983 [ANA_INIT] PLL <<<<<<<<
6116 22:53:36.765918 [ANA_INIT] MIDPI >>>>>>>>
6117 22:53:36.769275 [ANA_INIT] MIDPI <<<<<<<<
6118 22:53:36.769773 [ANA_INIT] DLL >>>>>>>>
6119 22:53:36.772745 [ANA_INIT] flow end
6120 22:53:36.775890 ============ LP4 DIFF to SE enter ============
6121 22:53:36.779080 ============ LP4 DIFF to SE exit ============
6122 22:53:36.782601 [ANA_INIT] <<<<<<<<<<<<<
6123 22:53:36.785684 [Flow] Enable top DCM control >>>>>
6124 22:53:36.788991 [Flow] Enable top DCM control <<<<<
6125 22:53:36.792379 Enable DLL master slave shuffle
6126 22:53:36.799562 ==============================================================
6127 22:53:36.800180 Gating Mode config
6128 22:53:36.805850 ==============================================================
6129 22:53:36.806416 Config description:
6130 22:53:36.815848 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6131 22:53:36.822267 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6132 22:53:36.829178 SELPH_MODE 0: By rank 1: By Phase
6133 22:53:36.832439 ==============================================================
6134 22:53:36.835805 GAT_TRACK_EN = 0
6135 22:53:36.838978 RX_GATING_MODE = 2
6136 22:53:36.842375 RX_GATING_TRACK_MODE = 2
6137 22:53:36.845852 SELPH_MODE = 1
6138 22:53:36.849291 PICG_EARLY_EN = 1
6139 22:53:36.852311 VALID_LAT_VALUE = 1
6140 22:53:36.855571 ==============================================================
6141 22:53:36.862119 Enter into Gating configuration >>>>
6142 22:53:36.865707 Exit from Gating configuration <<<<
6143 22:53:36.866287 Enter into DVFS_PRE_config >>>>>
6144 22:53:36.878948 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6145 22:53:36.882344 Exit from DVFS_PRE_config <<<<<
6146 22:53:36.885451 Enter into PICG configuration >>>>
6147 22:53:36.888758 Exit from PICG configuration <<<<
6148 22:53:36.889293 [RX_INPUT] configuration >>>>>
6149 22:53:36.892334 [RX_INPUT] configuration <<<<<
6150 22:53:36.898534 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6151 22:53:36.901952 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6152 22:53:36.908881 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6153 22:53:36.915668 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6154 22:53:36.922078 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6155 22:53:36.928824 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6156 22:53:36.932159 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6157 22:53:36.935613 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6158 22:53:36.938427 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6159 22:53:36.945750 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6160 22:53:36.948945 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6161 22:53:36.951911 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6162 22:53:36.955642 ===================================
6163 22:53:36.959038 LPDDR4 DRAM CONFIGURATION
6164 22:53:36.962403 ===================================
6165 22:53:36.965784 EX_ROW_EN[0] = 0x0
6166 22:53:36.966350 EX_ROW_EN[1] = 0x0
6167 22:53:36.968918 LP4Y_EN = 0x0
6168 22:53:36.969511 WORK_FSP = 0x0
6169 22:53:36.972578 WL = 0x2
6170 22:53:36.973135 RL = 0x2
6171 22:53:36.975694 BL = 0x2
6172 22:53:36.976254 RPST = 0x0
6173 22:53:36.978909 RD_PRE = 0x0
6174 22:53:36.979370 WR_PRE = 0x1
6175 22:53:36.981939 WR_PST = 0x0
6176 22:53:36.982442 DBI_WR = 0x0
6177 22:53:36.985631 DBI_RD = 0x0
6178 22:53:36.986192 OTF = 0x1
6179 22:53:36.988953 ===================================
6180 22:53:36.992219 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6181 22:53:36.998897 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6182 22:53:37.002414 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6183 22:53:37.005382 ===================================
6184 22:53:37.008506 LPDDR4 DRAM CONFIGURATION
6185 22:53:37.011951 ===================================
6186 22:53:37.012448 EX_ROW_EN[0] = 0x10
6187 22:53:37.015401 EX_ROW_EN[1] = 0x0
6188 22:53:37.018599 LP4Y_EN = 0x0
6189 22:53:37.019141 WORK_FSP = 0x0
6190 22:53:37.022371 WL = 0x2
6191 22:53:37.022998 RL = 0x2
6192 22:53:37.025433 BL = 0x2
6193 22:53:37.026032 RPST = 0x0
6194 22:53:37.028390 RD_PRE = 0x0
6195 22:53:37.028965 WR_PRE = 0x1
6196 22:53:37.031736 WR_PST = 0x0
6197 22:53:37.032215 DBI_WR = 0x0
6198 22:53:37.035234 DBI_RD = 0x0
6199 22:53:37.035711 OTF = 0x1
6200 22:53:37.038796 ===================================
6201 22:53:37.045242 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6202 22:53:37.049274 nWR fixed to 30
6203 22:53:37.053129 [ModeRegInit_LP4] CH0 RK0
6204 22:53:37.053614 [ModeRegInit_LP4] CH0 RK1
6205 22:53:37.056014 [ModeRegInit_LP4] CH1 RK0
6206 22:53:37.059557 [ModeRegInit_LP4] CH1 RK1
6207 22:53:37.060092 match AC timing 19
6208 22:53:37.066024 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6209 22:53:37.069850 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6210 22:53:37.073053 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6211 22:53:37.079677 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6212 22:53:37.082925 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6213 22:53:37.083381 ==
6214 22:53:37.086746 Dram Type= 6, Freq= 0, CH_0, rank 0
6215 22:53:37.089726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6216 22:53:37.090262 ==
6217 22:53:37.095928 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6218 22:53:37.102727 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6219 22:53:37.106255 [CA 0] Center 36 (8~64) winsize 57
6220 22:53:37.109529 [CA 1] Center 36 (8~64) winsize 57
6221 22:53:37.112990 [CA 2] Center 36 (8~64) winsize 57
6222 22:53:37.113539 [CA 3] Center 36 (8~64) winsize 57
6223 22:53:37.116121 [CA 4] Center 36 (8~64) winsize 57
6224 22:53:37.119154 [CA 5] Center 36 (8~64) winsize 57
6225 22:53:37.119577
6226 22:53:37.126163 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6227 22:53:37.126584
6228 22:53:37.129239 [CATrainingPosCal] consider 1 rank data
6229 22:53:37.132835 u2DelayCellTimex100 = 270/100 ps
6230 22:53:37.136184 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6231 22:53:37.139395 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6232 22:53:37.142620 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6233 22:53:37.145816 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6234 22:53:37.149390 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6235 22:53:37.152874 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6236 22:53:37.153466
6237 22:53:37.156344 CA PerBit enable=1, Macro0, CA PI delay=36
6238 22:53:37.156905
6239 22:53:37.159624 [CBTSetCACLKResult] CA Dly = 36
6240 22:53:37.162471 CS Dly: 1 (0~32)
6241 22:53:37.163029 ==
6242 22:53:37.166139 Dram Type= 6, Freq= 0, CH_0, rank 1
6243 22:53:37.169252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6244 22:53:37.169851 ==
6245 22:53:37.175934 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6246 22:53:37.179065 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6247 22:53:37.182909 [CA 0] Center 36 (8~64) winsize 57
6248 22:53:37.186033 [CA 1] Center 36 (8~64) winsize 57
6249 22:53:37.189638 [CA 2] Center 36 (8~64) winsize 57
6250 22:53:37.192661 [CA 3] Center 36 (8~64) winsize 57
6251 22:53:37.195989 [CA 4] Center 36 (8~64) winsize 57
6252 22:53:37.199418 [CA 5] Center 36 (8~64) winsize 57
6253 22:53:37.200019
6254 22:53:37.202414 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6255 22:53:37.202876
6256 22:53:37.205644 [CATrainingPosCal] consider 2 rank data
6257 22:53:37.209137 u2DelayCellTimex100 = 270/100 ps
6258 22:53:37.212805 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6259 22:53:37.215746 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6260 22:53:37.219093 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6261 22:53:37.225718 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6262 22:53:37.228804 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6263 22:53:37.232595 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6264 22:53:37.233164
6265 22:53:37.235960 CA PerBit enable=1, Macro0, CA PI delay=36
6266 22:53:37.236520
6267 22:53:37.239546 [CBTSetCACLKResult] CA Dly = 36
6268 22:53:37.240108 CS Dly: 1 (0~32)
6269 22:53:37.240474
6270 22:53:37.242551 ----->DramcWriteLeveling(PI) begin...
6271 22:53:37.243116 ==
6272 22:53:37.245735 Dram Type= 6, Freq= 0, CH_0, rank 0
6273 22:53:37.252530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6274 22:53:37.253094 ==
6275 22:53:37.255669 Write leveling (Byte 0): 40 => 8
6276 22:53:37.259078 Write leveling (Byte 1): 32 => 0
6277 22:53:37.259645 DramcWriteLeveling(PI) end<-----
6278 22:53:37.260011
6279 22:53:37.262398 ==
6280 22:53:37.262856 Dram Type= 6, Freq= 0, CH_0, rank 0
6281 22:53:37.269251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6282 22:53:37.269859 ==
6283 22:53:37.272701 [Gating] SW mode calibration
6284 22:53:37.279133 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6285 22:53:37.282229 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6286 22:53:37.289022 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6287 22:53:37.292365 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6288 22:53:37.295552 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6289 22:53:37.302584 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6290 22:53:37.305830 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6291 22:53:37.309228 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6292 22:53:37.315425 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6293 22:53:37.318675 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6294 22:53:37.322019 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6295 22:53:37.325237 Total UI for P1: 0, mck2ui 16
6296 22:53:37.328801 best dqsien dly found for B0: ( 0, 14, 24)
6297 22:53:37.332225 Total UI for P1: 0, mck2ui 16
6298 22:53:37.335365 best dqsien dly found for B1: ( 0, 14, 24)
6299 22:53:37.338633 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6300 22:53:37.342460 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6301 22:53:37.342910
6302 22:53:37.345471 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6303 22:53:37.352255 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6304 22:53:37.352803 [Gating] SW calibration Done
6305 22:53:37.353163 ==
6306 22:53:37.355692 Dram Type= 6, Freq= 0, CH_0, rank 0
6307 22:53:37.361905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6308 22:53:37.362479 ==
6309 22:53:37.362836 RX Vref Scan: 0
6310 22:53:37.363163
6311 22:53:37.365530 RX Vref 0 -> 0, step: 1
6312 22:53:37.365976
6313 22:53:37.368983 RX Delay -410 -> 252, step: 16
6314 22:53:37.372442 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6315 22:53:37.375801 iDelay=230, Bit 1, Center -3 (-234 ~ 229) 464
6316 22:53:37.382362 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6317 22:53:37.385560 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6318 22:53:37.388790 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6319 22:53:37.391940 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6320 22:53:37.398930 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6321 22:53:37.402475 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6322 22:53:37.405225 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6323 22:53:37.408861 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6324 22:53:37.415342 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6325 22:53:37.418379 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6326 22:53:37.421821 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6327 22:53:37.425209 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6328 22:53:37.431710 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6329 22:53:37.435134 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6330 22:53:37.435688 ==
6331 22:53:37.438430 Dram Type= 6, Freq= 0, CH_0, rank 0
6332 22:53:37.441751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6333 22:53:37.442209 ==
6334 22:53:37.445096 DQS Delay:
6335 22:53:37.445713 DQS0 = 27, DQS1 = 43
6336 22:53:37.448320 DQM Delay:
6337 22:53:37.448867 DQM0 = 14, DQM1 = 13
6338 22:53:37.449232 DQ Delay:
6339 22:53:37.451636 DQ0 =8, DQ1 =24, DQ2 =8, DQ3 =8
6340 22:53:37.455242 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6341 22:53:37.458489 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6342 22:53:37.462063 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6343 22:53:37.462611
6344 22:53:37.462972
6345 22:53:37.463302 ==
6346 22:53:37.465034 Dram Type= 6, Freq= 0, CH_0, rank 0
6347 22:53:37.471741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6348 22:53:37.472298 ==
6349 22:53:37.472661
6350 22:53:37.472994
6351 22:53:37.473339 TX Vref Scan disable
6352 22:53:37.474669 == TX Byte 0 ==
6353 22:53:37.478434 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6354 22:53:37.481599 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6355 22:53:37.484895 == TX Byte 1 ==
6356 22:53:37.488498 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6357 22:53:37.491489 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6358 22:53:37.492042 ==
6359 22:53:37.494844 Dram Type= 6, Freq= 0, CH_0, rank 0
6360 22:53:37.501493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6361 22:53:37.502029 ==
6362 22:53:37.502384
6363 22:53:37.502711
6364 22:53:37.503023 TX Vref Scan disable
6365 22:53:37.504902 == TX Byte 0 ==
6366 22:53:37.508290 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6367 22:53:37.511677 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6368 22:53:37.514689 == TX Byte 1 ==
6369 22:53:37.518366 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6370 22:53:37.521113 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6371 22:53:37.524570
6372 22:53:37.525029 [DATLAT]
6373 22:53:37.525430 Freq=400, CH0 RK0
6374 22:53:37.525773
6375 22:53:37.527733 DATLAT Default: 0xf
6376 22:53:37.528317 0, 0xFFFF, sum = 0
6377 22:53:37.531163 1, 0xFFFF, sum = 0
6378 22:53:37.531629 2, 0xFFFF, sum = 0
6379 22:53:37.534850 3, 0xFFFF, sum = 0
6380 22:53:37.535414 4, 0xFFFF, sum = 0
6381 22:53:37.537963 5, 0xFFFF, sum = 0
6382 22:53:37.541331 6, 0xFFFF, sum = 0
6383 22:53:37.541911 7, 0xFFFF, sum = 0
6384 22:53:37.544649 8, 0xFFFF, sum = 0
6385 22:53:37.545131 9, 0xFFFF, sum = 0
6386 22:53:37.547715 10, 0xFFFF, sum = 0
6387 22:53:37.548207 11, 0xFFFF, sum = 0
6388 22:53:37.550946 12, 0xFFFF, sum = 0
6389 22:53:37.551414 13, 0x0, sum = 1
6390 22:53:37.554561 14, 0x0, sum = 2
6391 22:53:37.555023 15, 0x0, sum = 3
6392 22:53:37.557489 16, 0x0, sum = 4
6393 22:53:37.557953 best_step = 14
6394 22:53:37.558314
6395 22:53:37.558869 ==
6396 22:53:37.560917 Dram Type= 6, Freq= 0, CH_0, rank 0
6397 22:53:37.564387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6398 22:53:37.564863 ==
6399 22:53:37.567620 RX Vref Scan: 1
6400 22:53:37.568089
6401 22:53:37.571403 RX Vref 0 -> 0, step: 1
6402 22:53:37.571824
6403 22:53:37.572155 RX Delay -327 -> 252, step: 8
6404 22:53:37.572516
6405 22:53:37.574075 Set Vref, RX VrefLevel [Byte0]: 58
6406 22:53:37.577487 [Byte1]: 48
6407 22:53:37.583448
6408 22:53:37.584018 Final RX Vref Byte 0 = 58 to rank0
6409 22:53:37.586574 Final RX Vref Byte 1 = 48 to rank0
6410 22:53:37.590185 Final RX Vref Byte 0 = 58 to rank1
6411 22:53:37.593475 Final RX Vref Byte 1 = 48 to rank1==
6412 22:53:37.596797 Dram Type= 6, Freq= 0, CH_0, rank 0
6413 22:53:37.599741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6414 22:53:37.603444 ==
6415 22:53:37.604018 DQS Delay:
6416 22:53:37.604390 DQS0 = 28, DQS1 = 48
6417 22:53:37.606702 DQM Delay:
6418 22:53:37.607244 DQM0 = 12, DQM1 = 16
6419 22:53:37.609809 DQ Delay:
6420 22:53:37.613536 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6421 22:53:37.614107 DQ4 =12, DQ5 =0, DQ6 =24, DQ7 =20
6422 22:53:37.616180 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =12
6423 22:53:37.620112 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =24
6424 22:53:37.620687
6425 22:53:37.623195
6426 22:53:37.629554 [DQSOSCAuto] RK0, (LSB)MR18= 0xb3aa, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 387 ps
6427 22:53:37.633352 CH0 RK0: MR19=C0C, MR18=B3AA
6428 22:53:37.639903 CH0_RK0: MR19=0xC0C, MR18=0xB3AA, DQSOSC=387, MR23=63, INC=394, DEC=262
6429 22:53:37.640461 ==
6430 22:53:37.643301 Dram Type= 6, Freq= 0, CH_0, rank 1
6431 22:53:37.646084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6432 22:53:37.646560 ==
6433 22:53:37.649487 [Gating] SW mode calibration
6434 22:53:37.656294 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6435 22:53:37.663226 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6436 22:53:37.666109 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6437 22:53:37.669879 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6438 22:53:37.673516 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6439 22:53:37.679665 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6440 22:53:37.682896 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6441 22:53:37.686187 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6442 22:53:37.693158 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6443 22:53:37.696706 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6444 22:53:37.699909 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6445 22:53:37.702846 Total UI for P1: 0, mck2ui 16
6446 22:53:37.706440 best dqsien dly found for B0: ( 0, 14, 24)
6447 22:53:37.709447 Total UI for P1: 0, mck2ui 16
6448 22:53:37.713026 best dqsien dly found for B1: ( 0, 14, 24)
6449 22:53:37.716247 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6450 22:53:37.723014 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6451 22:53:37.723577
6452 22:53:37.726131 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6453 22:53:37.729166 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6454 22:53:37.732545 [Gating] SW calibration Done
6455 22:53:37.733016 ==
6456 22:53:37.735915 Dram Type= 6, Freq= 0, CH_0, rank 1
6457 22:53:37.739479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6458 22:53:37.740055 ==
6459 22:53:37.740427 RX Vref Scan: 0
6460 22:53:37.742337
6461 22:53:37.742800 RX Vref 0 -> 0, step: 1
6462 22:53:37.743165
6463 22:53:37.745954 RX Delay -410 -> 252, step: 16
6464 22:53:37.749445 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6465 22:53:37.756085 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6466 22:53:37.759020 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6467 22:53:37.763124 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6468 22:53:37.765952 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6469 22:53:37.772706 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6470 22:53:37.776187 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6471 22:53:37.779187 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6472 22:53:37.782612 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6473 22:53:37.789359 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6474 22:53:37.792753 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6475 22:53:37.795932 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6476 22:53:37.799068 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6477 22:53:37.805711 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6478 22:53:37.809437 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6479 22:53:37.812191 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6480 22:53:37.812757 ==
6481 22:53:37.815850 Dram Type= 6, Freq= 0, CH_0, rank 1
6482 22:53:37.822517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6483 22:53:37.822992 ==
6484 22:53:37.823359 DQS Delay:
6485 22:53:37.825553 DQS0 = 27, DQS1 = 43
6486 22:53:37.826019 DQM Delay:
6487 22:53:37.826391 DQM0 = 9, DQM1 = 16
6488 22:53:37.828754 DQ Delay:
6489 22:53:37.832418 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6490 22:53:37.832991 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6491 22:53:37.835706 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =16
6492 22:53:37.838643 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6493 22:53:37.839109
6494 22:53:37.839468
6495 22:53:37.842318 ==
6496 22:53:37.845370 Dram Type= 6, Freq= 0, CH_0, rank 1
6497 22:53:37.848752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6498 22:53:37.849364 ==
6499 22:53:37.849748
6500 22:53:37.850092
6501 22:53:37.852148 TX Vref Scan disable
6502 22:53:37.852608 == TX Byte 0 ==
6503 22:53:37.855269 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6504 22:53:37.862160 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6505 22:53:37.862731 == TX Byte 1 ==
6506 22:53:37.865223 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6507 22:53:37.872225 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6508 22:53:37.872789 ==
6509 22:53:37.875460 Dram Type= 6, Freq= 0, CH_0, rank 1
6510 22:53:37.878568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6511 22:53:37.879035 ==
6512 22:53:37.879400
6513 22:53:37.879734
6514 22:53:37.882000 TX Vref Scan disable
6515 22:53:37.882560 == TX Byte 0 ==
6516 22:53:37.885579 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6517 22:53:37.892103 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6518 22:53:37.892725 == TX Byte 1 ==
6519 22:53:37.895282 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6520 22:53:37.902228 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6521 22:53:37.902789
6522 22:53:37.903151 [DATLAT]
6523 22:53:37.903490 Freq=400, CH0 RK1
6524 22:53:37.903817
6525 22:53:37.905042 DATLAT Default: 0xe
6526 22:53:37.908315 0, 0xFFFF, sum = 0
6527 22:53:37.908786 1, 0xFFFF, sum = 0
6528 22:53:37.911904 2, 0xFFFF, sum = 0
6529 22:53:37.912470 3, 0xFFFF, sum = 0
6530 22:53:37.915762 4, 0xFFFF, sum = 0
6531 22:53:37.916326 5, 0xFFFF, sum = 0
6532 22:53:37.918509 6, 0xFFFF, sum = 0
6533 22:53:37.919088 7, 0xFFFF, sum = 0
6534 22:53:37.921999 8, 0xFFFF, sum = 0
6535 22:53:37.922654 9, 0xFFFF, sum = 0
6536 22:53:37.924906 10, 0xFFFF, sum = 0
6537 22:53:37.925438 11, 0xFFFF, sum = 0
6538 22:53:37.928284 12, 0xFFFF, sum = 0
6539 22:53:37.928753 13, 0x0, sum = 1
6540 22:53:37.931629 14, 0x0, sum = 2
6541 22:53:37.932098 15, 0x0, sum = 3
6542 22:53:37.935379 16, 0x0, sum = 4
6543 22:53:37.935951 best_step = 14
6544 22:53:37.936317
6545 22:53:37.936654 ==
6546 22:53:37.938341 Dram Type= 6, Freq= 0, CH_0, rank 1
6547 22:53:37.941458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6548 22:53:37.944989 ==
6549 22:53:37.945475 RX Vref Scan: 0
6550 22:53:37.945843
6551 22:53:37.948147 RX Vref 0 -> 0, step: 1
6552 22:53:37.948608
6553 22:53:37.951551 RX Delay -327 -> 252, step: 8
6554 22:53:37.955180 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6555 22:53:37.961662 iDelay=217, Bit 1, Center -20 (-247 ~ 208) 456
6556 22:53:37.964962 iDelay=217, Bit 2, Center -20 (-239 ~ 200) 440
6557 22:53:37.968442 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6558 22:53:37.971786 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6559 22:53:37.978147 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6560 22:53:37.981633 iDelay=217, Bit 6, Center -12 (-239 ~ 216) 456
6561 22:53:37.985046 iDelay=217, Bit 7, Center -12 (-239 ~ 216) 456
6562 22:53:37.988272 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6563 22:53:37.995125 iDelay=217, Bit 9, Center -40 (-263 ~ 184) 448
6564 22:53:37.998511 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6565 22:53:38.002084 iDelay=217, Bit 11, Center -36 (-263 ~ 192) 456
6566 22:53:38.004985 iDelay=217, Bit 12, Center -28 (-255 ~ 200) 456
6567 22:53:38.011816 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6568 22:53:38.015083 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6569 22:53:38.018209 iDelay=217, Bit 15, Center -24 (-247 ~ 200) 448
6570 22:53:38.018772 ==
6571 22:53:38.021369 Dram Type= 6, Freq= 0, CH_0, rank 1
6572 22:53:38.028190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6573 22:53:38.028757 ==
6574 22:53:38.029131 DQS Delay:
6575 22:53:38.031526 DQS0 = 28, DQS1 = 40
6576 22:53:38.031988 DQM Delay:
6577 22:53:38.032356 DQM0 = 9, DQM1 = 11
6578 22:53:38.034729 DQ Delay:
6579 22:53:38.038050 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =4
6580 22:53:38.038512 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6581 22:53:38.041180 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6582 22:53:38.044838 DQ12 =12, DQ13 =16, DQ14 =24, DQ15 =16
6583 22:53:38.045455
6584 22:53:38.047781
6585 22:53:38.054536 [DQSOSCAuto] RK1, (LSB)MR18= 0xb86c, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 386 ps
6586 22:53:38.057613 CH0 RK1: MR19=C0C, MR18=B86C
6587 22:53:38.064375 CH0_RK1: MR19=0xC0C, MR18=0xB86C, DQSOSC=386, MR23=63, INC=396, DEC=264
6588 22:53:38.067628 [RxdqsGatingPostProcess] freq 400
6589 22:53:38.071021 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6590 22:53:38.074476 best DQS0 dly(2T, 0.5T) = (0, 10)
6591 22:53:38.078247 best DQS1 dly(2T, 0.5T) = (0, 10)
6592 22:53:38.081352 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6593 22:53:38.084789 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6594 22:53:38.087662 best DQS0 dly(2T, 0.5T) = (0, 10)
6595 22:53:38.090864 best DQS1 dly(2T, 0.5T) = (0, 10)
6596 22:53:38.094803 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6597 22:53:38.097654 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6598 22:53:38.100804 Pre-setting of DQS Precalculation
6599 22:53:38.104398 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6600 22:53:38.104959 ==
6601 22:53:38.107476 Dram Type= 6, Freq= 0, CH_1, rank 0
6602 22:53:38.114579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6603 22:53:38.115155 ==
6604 22:53:38.117791 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6605 22:53:38.124177 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6606 22:53:38.127450 [CA 0] Center 36 (8~64) winsize 57
6607 22:53:38.130691 [CA 1] Center 36 (8~64) winsize 57
6608 22:53:38.134165 [CA 2] Center 36 (8~64) winsize 57
6609 22:53:38.137571 [CA 3] Center 36 (8~64) winsize 57
6610 22:53:38.140643 [CA 4] Center 36 (8~64) winsize 57
6611 22:53:38.144070 [CA 5] Center 36 (8~64) winsize 57
6612 22:53:38.144484
6613 22:53:38.147590 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6614 22:53:38.148004
6615 22:53:38.151106 [CATrainingPosCal] consider 1 rank data
6616 22:53:38.154660 u2DelayCellTimex100 = 270/100 ps
6617 22:53:38.157490 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6618 22:53:38.160753 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6619 22:53:38.163960 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6620 22:53:38.167387 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6621 22:53:38.170476 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6622 22:53:38.174167 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6623 22:53:38.174693
6624 22:53:38.181109 CA PerBit enable=1, Macro0, CA PI delay=36
6625 22:53:38.181722
6626 22:53:38.183715 [CBTSetCACLKResult] CA Dly = 36
6627 22:53:38.184195 CS Dly: 1 (0~32)
6628 22:53:38.184569 ==
6629 22:53:38.187387 Dram Type= 6, Freq= 0, CH_1, rank 1
6630 22:53:38.190546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6631 22:53:38.191112 ==
6632 22:53:38.197827 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6633 22:53:38.204186 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6634 22:53:38.207299 [CA 0] Center 36 (8~64) winsize 57
6635 22:53:38.210387 [CA 1] Center 36 (8~64) winsize 57
6636 22:53:38.214189 [CA 2] Center 36 (8~64) winsize 57
6637 22:53:38.214697 [CA 3] Center 36 (8~64) winsize 57
6638 22:53:38.217212 [CA 4] Center 36 (8~64) winsize 57
6639 22:53:38.220762 [CA 5] Center 36 (8~64) winsize 57
6640 22:53:38.221219
6641 22:53:38.227242 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6642 22:53:38.227747
6643 22:53:38.230295 [CATrainingPosCal] consider 2 rank data
6644 22:53:38.233767 u2DelayCellTimex100 = 270/100 ps
6645 22:53:38.236906 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6646 22:53:38.240322 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6647 22:53:38.243671 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6648 22:53:38.246805 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6649 22:53:38.250484 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6650 22:53:38.253452 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6651 22:53:38.253884
6652 22:53:38.257398 CA PerBit enable=1, Macro0, CA PI delay=36
6653 22:53:38.257918
6654 22:53:38.260487 [CBTSetCACLKResult] CA Dly = 36
6655 22:53:38.263989 CS Dly: 1 (0~32)
6656 22:53:38.264547
6657 22:53:38.266915 ----->DramcWriteLeveling(PI) begin...
6658 22:53:38.267479 ==
6659 22:53:38.270381 Dram Type= 6, Freq= 0, CH_1, rank 0
6660 22:53:38.273407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6661 22:53:38.273871 ==
6662 22:53:38.276498 Write leveling (Byte 0): 40 => 8
6663 22:53:38.279995 Write leveling (Byte 1): 32 => 0
6664 22:53:38.283331 DramcWriteLeveling(PI) end<-----
6665 22:53:38.283793
6666 22:53:38.284156 ==
6667 22:53:38.286570 Dram Type= 6, Freq= 0, CH_1, rank 0
6668 22:53:38.289906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6669 22:53:38.290346 ==
6670 22:53:38.293120 [Gating] SW mode calibration
6671 22:53:38.300012 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6672 22:53:38.306366 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6673 22:53:38.309626 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6674 22:53:38.316266 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6675 22:53:38.319462 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6676 22:53:38.322664 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6677 22:53:38.326171 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6678 22:53:38.332889 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6679 22:53:38.335925 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6680 22:53:38.343042 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6681 22:53:38.346415 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6682 22:53:38.349270 Total UI for P1: 0, mck2ui 16
6683 22:53:38.353386 best dqsien dly found for B0: ( 0, 14, 24)
6684 22:53:38.356355 Total UI for P1: 0, mck2ui 16
6685 22:53:38.359540 best dqsien dly found for B1: ( 0, 14, 24)
6686 22:53:38.363127 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6687 22:53:38.366381 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6688 22:53:38.366954
6689 22:53:38.369519 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6690 22:53:38.372998 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6691 22:53:38.376253 [Gating] SW calibration Done
6692 22:53:38.376838 ==
6693 22:53:38.379278 Dram Type= 6, Freq= 0, CH_1, rank 0
6694 22:53:38.382661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6695 22:53:38.383133 ==
6696 22:53:38.385996 RX Vref Scan: 0
6697 22:53:38.386570
6698 22:53:38.389515 RX Vref 0 -> 0, step: 1
6699 22:53:38.389984
6700 22:53:38.390353 RX Delay -410 -> 252, step: 16
6701 22:53:38.396252 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6702 22:53:38.399699 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6703 22:53:38.402895 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6704 22:53:38.406224 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6705 22:53:38.413268 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6706 22:53:38.416430 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6707 22:53:38.419750 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6708 22:53:38.422744 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6709 22:53:38.429513 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6710 22:53:38.432345 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6711 22:53:38.436396 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6712 22:53:38.439466 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6713 22:53:38.445731 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6714 22:53:38.448861 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6715 22:53:38.452303 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6716 22:53:38.459277 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6717 22:53:38.459775 ==
6718 22:53:38.462331 Dram Type= 6, Freq= 0, CH_1, rank 0
6719 22:53:38.465691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6720 22:53:38.466118 ==
6721 22:53:38.466455 DQS Delay:
6722 22:53:38.469404 DQS0 = 27, DQS1 = 43
6723 22:53:38.469866 DQM Delay:
6724 22:53:38.472369 DQM0 = 8, DQM1 = 15
6725 22:53:38.472792 DQ Delay:
6726 22:53:38.475813 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6727 22:53:38.478881 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =0
6728 22:53:38.482226 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6729 22:53:38.485761 DQ12 =32, DQ13 =16, DQ14 =16, DQ15 =24
6730 22:53:38.486184
6731 22:53:38.486517
6732 22:53:38.486822 ==
6733 22:53:38.489000 Dram Type= 6, Freq= 0, CH_1, rank 0
6734 22:53:38.492814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6735 22:53:38.493426 ==
6736 22:53:38.493829
6737 22:53:38.494150
6738 22:53:38.495783 TX Vref Scan disable
6739 22:53:38.496206 == TX Byte 0 ==
6740 22:53:38.502360 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6741 22:53:38.505578 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6742 22:53:38.506066 == TX Byte 1 ==
6743 22:53:38.512078 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6744 22:53:38.515408 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6745 22:53:38.515492 ==
6746 22:53:38.518553 Dram Type= 6, Freq= 0, CH_1, rank 0
6747 22:53:38.521902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6748 22:53:38.521984 ==
6749 22:53:38.522049
6750 22:53:38.522108
6751 22:53:38.525488 TX Vref Scan disable
6752 22:53:38.525602 == TX Byte 0 ==
6753 22:53:38.532201 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6754 22:53:38.535119 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6755 22:53:38.535203 == TX Byte 1 ==
6756 22:53:38.541887 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6757 22:53:38.545151 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6758 22:53:38.545276
6759 22:53:38.545375 [DATLAT]
6760 22:53:38.548740 Freq=400, CH1 RK0
6761 22:53:38.548848
6762 22:53:38.548941 DATLAT Default: 0xf
6763 22:53:38.552124 0, 0xFFFF, sum = 0
6764 22:53:38.552236 1, 0xFFFF, sum = 0
6765 22:53:38.555221 2, 0xFFFF, sum = 0
6766 22:53:38.555332 3, 0xFFFF, sum = 0
6767 22:53:38.558527 4, 0xFFFF, sum = 0
6768 22:53:38.558601 5, 0xFFFF, sum = 0
6769 22:53:38.561725 6, 0xFFFF, sum = 0
6770 22:53:38.561809 7, 0xFFFF, sum = 0
6771 22:53:38.565410 8, 0xFFFF, sum = 0
6772 22:53:38.568629 9, 0xFFFF, sum = 0
6773 22:53:38.568719 10, 0xFFFF, sum = 0
6774 22:53:38.571868 11, 0xFFFF, sum = 0
6775 22:53:38.571957 12, 0xFFFF, sum = 0
6776 22:53:38.575387 13, 0x0, sum = 1
6777 22:53:38.575483 14, 0x0, sum = 2
6778 22:53:38.578691 15, 0x0, sum = 3
6779 22:53:38.578795 16, 0x0, sum = 4
6780 22:53:38.578878 best_step = 14
6781 22:53:38.578953
6782 22:53:38.581936 ==
6783 22:53:38.584909 Dram Type= 6, Freq= 0, CH_1, rank 0
6784 22:53:38.588683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6785 22:53:38.588808 ==
6786 22:53:38.588904 RX Vref Scan: 1
6787 22:53:38.588996
6788 22:53:38.591780 RX Vref 0 -> 0, step: 1
6789 22:53:38.591929
6790 22:53:38.595262 RX Delay -327 -> 252, step: 8
6791 22:53:38.595399
6792 22:53:38.598483 Set Vref, RX VrefLevel [Byte0]: 53
6793 22:53:38.601922 [Byte1]: 50
6794 22:53:38.605335
6795 22:53:38.605509 Final RX Vref Byte 0 = 53 to rank0
6796 22:53:38.608541 Final RX Vref Byte 1 = 50 to rank0
6797 22:53:38.612036 Final RX Vref Byte 0 = 53 to rank1
6798 22:53:38.615540 Final RX Vref Byte 1 = 50 to rank1==
6799 22:53:38.618806 Dram Type= 6, Freq= 0, CH_1, rank 0
6800 22:53:38.625413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6801 22:53:38.625807 ==
6802 22:53:38.626118 DQS Delay:
6803 22:53:38.629064 DQS0 = 28, DQS1 = 40
6804 22:53:38.629522 DQM Delay:
6805 22:53:38.629860 DQM0 = 8, DQM1 = 13
6806 22:53:38.632243 DQ Delay:
6807 22:53:38.635787 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6808 22:53:38.636212 DQ4 =4, DQ5 =16, DQ6 =16, DQ7 =4
6809 22:53:38.639107 DQ8 =0, DQ9 =0, DQ10 =20, DQ11 =4
6810 22:53:38.642023 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6811 22:53:38.642446
6812 22:53:38.642777
6813 22:53:38.652458 [DQSOSCAuto] RK0, (LSB)MR18= 0x9ad5, (MSB)MR19= 0xc0c, tDQSOscB0 = 383 ps tDQSOscB1 = 390 ps
6814 22:53:38.655391 CH1 RK0: MR19=C0C, MR18=9AD5
6815 22:53:38.661974 CH1_RK0: MR19=0xC0C, MR18=0x9AD5, DQSOSC=383, MR23=63, INC=402, DEC=268
6816 22:53:38.662494 ==
6817 22:53:38.665360 Dram Type= 6, Freq= 0, CH_1, rank 1
6818 22:53:38.669136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6819 22:53:38.669603 ==
6820 22:53:38.672069 [Gating] SW mode calibration
6821 22:53:38.678949 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6822 22:53:38.682323 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6823 22:53:38.688797 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6824 22:53:38.692158 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6825 22:53:38.695178 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6826 22:53:38.701920 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6827 22:53:38.705701 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6828 22:53:38.708704 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6829 22:53:38.715677 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6830 22:53:38.718511 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6831 22:53:38.722462 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6832 22:53:38.725120 Total UI for P1: 0, mck2ui 16
6833 22:53:38.729102 best dqsien dly found for B0: ( 0, 14, 24)
6834 22:53:38.731997 Total UI for P1: 0, mck2ui 16
6835 22:53:38.735400 best dqsien dly found for B1: ( 0, 14, 24)
6836 22:53:38.738949 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6837 22:53:38.741944 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6838 22:53:38.745458
6839 22:53:38.748841 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6840 22:53:38.752220 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6841 22:53:38.755616 [Gating] SW calibration Done
6842 22:53:38.756174 ==
6843 22:53:38.758955 Dram Type= 6, Freq= 0, CH_1, rank 1
6844 22:53:38.761940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6845 22:53:38.762507 ==
6846 22:53:38.762876 RX Vref Scan: 0
6847 22:53:38.763219
6848 22:53:38.765402 RX Vref 0 -> 0, step: 1
6849 22:53:38.765865
6850 22:53:38.768868 RX Delay -410 -> 252, step: 16
6851 22:53:38.772509 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6852 22:53:38.775783 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6853 22:53:38.782347 iDelay=230, Bit 2, Center -27 (-250 ~ 197) 448
6854 22:53:38.785266 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6855 22:53:38.788917 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6856 22:53:38.792059 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6857 22:53:38.798779 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6858 22:53:38.802170 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6859 22:53:38.805439 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6860 22:53:38.809023 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6861 22:53:38.815096 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6862 22:53:38.818234 iDelay=230, Bit 11, Center -19 (-250 ~ 213) 464
6863 22:53:38.821638 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6864 22:53:38.828138 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6865 22:53:38.832000 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6866 22:53:38.834989 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6867 22:53:38.835177 ==
6868 22:53:38.838190 Dram Type= 6, Freq= 0, CH_1, rank 1
6869 22:53:38.841640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6870 22:53:38.841846 ==
6871 22:53:38.845062 DQS Delay:
6872 22:53:38.845223 DQS0 = 27, DQS1 = 43
6873 22:53:38.848253 DQM Delay:
6874 22:53:38.848335 DQM0 = 9, DQM1 = 21
6875 22:53:38.848400 DQ Delay:
6876 22:53:38.851558 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6877 22:53:38.854804 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6878 22:53:38.858206 DQ8 =0, DQ9 =8, DQ10 =24, DQ11 =24
6879 22:53:38.861673 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =32
6880 22:53:38.861756
6881 22:53:38.861821
6882 22:53:38.861879 ==
6883 22:53:38.864846 Dram Type= 6, Freq= 0, CH_1, rank 1
6884 22:53:38.871830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6885 22:53:38.872004 ==
6886 22:53:38.872098
6887 22:53:38.872185
6888 22:53:38.872259 TX Vref Scan disable
6889 22:53:38.875208 == TX Byte 0 ==
6890 22:53:38.878196 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6891 22:53:38.881748 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6892 22:53:38.885166 == TX Byte 1 ==
6893 22:53:38.888351 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6894 22:53:38.891476 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6895 22:53:38.891613 ==
6896 22:53:38.895004 Dram Type= 6, Freq= 0, CH_1, rank 1
6897 22:53:38.901427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6898 22:53:38.901601 ==
6899 22:53:38.901738
6900 22:53:38.901865
6901 22:53:38.901986 TX Vref Scan disable
6902 22:53:38.905029 == TX Byte 0 ==
6903 22:53:38.908057 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6904 22:53:38.911522 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6905 22:53:38.914898 == TX Byte 1 ==
6906 22:53:38.918474 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6907 22:53:38.921955 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6908 22:53:38.922343
6909 22:53:38.925009 [DATLAT]
6910 22:53:38.925468 Freq=400, CH1 RK1
6911 22:53:38.925807
6912 22:53:38.928501 DATLAT Default: 0xe
6913 22:53:38.928920 0, 0xFFFF, sum = 0
6914 22:53:38.931998 1, 0xFFFF, sum = 0
6915 22:53:38.932424 2, 0xFFFF, sum = 0
6916 22:53:38.935251 3, 0xFFFF, sum = 0
6917 22:53:38.935680 4, 0xFFFF, sum = 0
6918 22:53:38.938716 5, 0xFFFF, sum = 0
6919 22:53:38.939144 6, 0xFFFF, sum = 0
6920 22:53:38.941853 7, 0xFFFF, sum = 0
6921 22:53:38.942279 8, 0xFFFF, sum = 0
6922 22:53:38.944964 9, 0xFFFF, sum = 0
6923 22:53:38.945421 10, 0xFFFF, sum = 0
6924 22:53:38.948301 11, 0xFFFF, sum = 0
6925 22:53:38.948728 12, 0xFFFF, sum = 0
6926 22:53:38.951627 13, 0x0, sum = 1
6927 22:53:38.952053 14, 0x0, sum = 2
6928 22:53:38.954898 15, 0x0, sum = 3
6929 22:53:38.955325 16, 0x0, sum = 4
6930 22:53:38.958280 best_step = 14
6931 22:53:38.958699
6932 22:53:38.959029 ==
6933 22:53:38.961416 Dram Type= 6, Freq= 0, CH_1, rank 1
6934 22:53:38.964842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6935 22:53:38.965265 ==
6936 22:53:38.968486 RX Vref Scan: 0
6937 22:53:38.968905
6938 22:53:38.969234 RX Vref 0 -> 0, step: 1
6939 22:53:38.969599
6940 22:53:38.971576 RX Delay -327 -> 252, step: 8
6941 22:53:38.979336 iDelay=217, Bit 0, Center -16 (-231 ~ 200) 432
6942 22:53:38.982450 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6943 22:53:38.985851 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6944 22:53:38.989426 iDelay=217, Bit 3, Center -20 (-247 ~ 208) 456
6945 22:53:38.996070 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6946 22:53:38.999323 iDelay=217, Bit 5, Center -12 (-239 ~ 216) 456
6947 22:53:39.002683 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6948 22:53:39.006115 iDelay=217, Bit 7, Center -24 (-247 ~ 200) 448
6949 22:53:39.012876 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6950 22:53:39.016100 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6951 22:53:39.019297 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
6952 22:53:39.022799 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6953 22:53:39.029585 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6954 22:53:39.032486 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
6955 22:53:39.035970 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6956 22:53:39.042506 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6957 22:53:39.042944 ==
6958 22:53:39.046029 Dram Type= 6, Freq= 0, CH_1, rank 1
6959 22:53:39.049212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6960 22:53:39.049677 ==
6961 22:53:39.050013 DQS Delay:
6962 22:53:39.052635 DQS0 = 32, DQS1 = 36
6963 22:53:39.053054 DQM Delay:
6964 22:53:39.055803 DQM0 = 12, DQM1 = 12
6965 22:53:39.056220 DQ Delay:
6966 22:53:39.059085 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6967 22:53:39.062417 DQ4 =16, DQ5 =20, DQ6 =20, DQ7 =8
6968 22:53:39.065967 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =8
6969 22:53:39.069464 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =24
6970 22:53:39.069888
6971 22:53:39.070218
6972 22:53:39.075857 [DQSOSCAuto] RK1, (LSB)MR18= 0xb057, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 387 ps
6973 22:53:39.079165 CH1 RK1: MR19=C0C, MR18=B057
6974 22:53:39.085537 CH1_RK1: MR19=0xC0C, MR18=0xB057, DQSOSC=387, MR23=63, INC=394, DEC=262
6975 22:53:39.088802 [RxdqsGatingPostProcess] freq 400
6976 22:53:39.095443 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6977 22:53:39.098992 best DQS0 dly(2T, 0.5T) = (0, 10)
6978 22:53:39.099491 best DQS1 dly(2T, 0.5T) = (0, 10)
6979 22:53:39.102490 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6980 22:53:39.105507 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6981 22:53:39.108760 best DQS0 dly(2T, 0.5T) = (0, 10)
6982 22:53:39.112131 best DQS1 dly(2T, 0.5T) = (0, 10)
6983 22:53:39.115117 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6984 22:53:39.118576 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6985 22:53:39.122107 Pre-setting of DQS Precalculation
6986 22:53:39.128590 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6987 22:53:39.134870 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6988 22:53:39.141927 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6989 22:53:39.142009
6990 22:53:39.142073
6991 22:53:39.145078 [Calibration Summary] 800 Mbps
6992 22:53:39.145159 CH 0, Rank 0
6993 22:53:39.148809 SW Impedance : PASS
6994 22:53:39.151658 DUTY Scan : NO K
6995 22:53:39.151739 ZQ Calibration : PASS
6996 22:53:39.155014 Jitter Meter : NO K
6997 22:53:39.158532 CBT Training : PASS
6998 22:53:39.158615 Write leveling : PASS
6999 22:53:39.162060 RX DQS gating : PASS
7000 22:53:39.164693 RX DQ/DQS(RDDQC) : PASS
7001 22:53:39.164781 TX DQ/DQS : PASS
7002 22:53:39.168493 RX DATLAT : PASS
7003 22:53:39.168579 RX DQ/DQS(Engine): PASS
7004 22:53:39.171256 TX OE : NO K
7005 22:53:39.171351 All Pass.
7006 22:53:39.171424
7007 22:53:39.175352 CH 0, Rank 1
7008 22:53:39.175487 SW Impedance : PASS
7009 22:53:39.177966 DUTY Scan : NO K
7010 22:53:39.181396 ZQ Calibration : PASS
7011 22:53:39.181507 Jitter Meter : NO K
7012 22:53:39.184603 CBT Training : PASS
7013 22:53:39.188274 Write leveling : NO K
7014 22:53:39.188397 RX DQS gating : PASS
7015 22:53:39.191212 RX DQ/DQS(RDDQC) : PASS
7016 22:53:39.194497 TX DQ/DQS : PASS
7017 22:53:39.194650 RX DATLAT : PASS
7018 22:53:39.198098 RX DQ/DQS(Engine): PASS
7019 22:53:39.201112 TX OE : NO K
7020 22:53:39.201284 All Pass.
7021 22:53:39.201431
7022 22:53:39.201557 CH 1, Rank 0
7023 22:53:39.204699 SW Impedance : PASS
7024 22:53:39.208088 DUTY Scan : NO K
7025 22:53:39.208288 ZQ Calibration : PASS
7026 22:53:39.211535 Jitter Meter : NO K
7027 22:53:39.214762 CBT Training : PASS
7028 22:53:39.215061 Write leveling : PASS
7029 22:53:39.218199 RX DQS gating : PASS
7030 22:53:39.221378 RX DQ/DQS(RDDQC) : PASS
7031 22:53:39.221784 TX DQ/DQS : PASS
7032 22:53:39.224711 RX DATLAT : PASS
7033 22:53:39.227744 RX DQ/DQS(Engine): PASS
7034 22:53:39.228161 TX OE : NO K
7035 22:53:39.228491 All Pass.
7036 22:53:39.231150
7037 22:53:39.231567 CH 1, Rank 1
7038 22:53:39.234360 SW Impedance : PASS
7039 22:53:39.234796 DUTY Scan : NO K
7040 22:53:39.237667 ZQ Calibration : PASS
7041 22:53:39.238079 Jitter Meter : NO K
7042 22:53:39.241170 CBT Training : PASS
7043 22:53:39.244729 Write leveling : NO K
7044 22:53:39.245143 RX DQS gating : PASS
7045 22:53:39.248357 RX DQ/DQS(RDDQC) : PASS
7046 22:53:39.251478 TX DQ/DQS : PASS
7047 22:53:39.251999 RX DATLAT : PASS
7048 22:53:39.254449 RX DQ/DQS(Engine): PASS
7049 22:53:39.258143 TX OE : NO K
7050 22:53:39.258660 All Pass.
7051 22:53:39.258990
7052 22:53:39.261506 DramC Write-DBI off
7053 22:53:39.262071 PER_BANK_REFRESH: Hybrid Mode
7054 22:53:39.264886 TX_TRACKING: ON
7055 22:53:39.271211 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7056 22:53:39.277916 [FAST_K] Save calibration result to emmc
7057 22:53:39.281617 dramc_set_vcore_voltage set vcore to 725000
7058 22:53:39.282177 Read voltage for 1600, 0
7059 22:53:39.284841 Vio18 = 0
7060 22:53:39.285342 Vcore = 725000
7061 22:53:39.285747 Vdram = 0
7062 22:53:39.288048 Vddq = 0
7063 22:53:39.288605 Vmddr = 0
7064 22:53:39.291374 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7065 22:53:39.297822 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7066 22:53:39.300925 MEM_TYPE=3, freq_sel=13
7067 22:53:39.304690 sv_algorithm_assistance_LP4_3733
7068 22:53:39.307978 ============ PULL DRAM RESETB DOWN ============
7069 22:53:39.311238 ========== PULL DRAM RESETB DOWN end =========
7070 22:53:39.317656 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7071 22:53:39.321115 ===================================
7072 22:53:39.321706 LPDDR4 DRAM CONFIGURATION
7073 22:53:39.324214 ===================================
7074 22:53:39.327634 EX_ROW_EN[0] = 0x0
7075 22:53:39.330897 EX_ROW_EN[1] = 0x0
7076 22:53:39.331357 LP4Y_EN = 0x0
7077 22:53:39.334258 WORK_FSP = 0x1
7078 22:53:39.334830 WL = 0x5
7079 22:53:39.337061 RL = 0x5
7080 22:53:39.337555 BL = 0x2
7081 22:53:39.340515 RPST = 0x0
7082 22:53:39.340973 RD_PRE = 0x0
7083 22:53:39.343632 WR_PRE = 0x1
7084 22:53:39.344111 WR_PST = 0x1
7085 22:53:39.347431 DBI_WR = 0x0
7086 22:53:39.347991 DBI_RD = 0x0
7087 22:53:39.350814 OTF = 0x1
7088 22:53:39.353917 ===================================
7089 22:53:39.356947 ===================================
7090 22:53:39.357453 ANA top config
7091 22:53:39.360651 ===================================
7092 22:53:39.363902 DLL_ASYNC_EN = 0
7093 22:53:39.367123 ALL_SLAVE_EN = 0
7094 22:53:39.367688 NEW_RANK_MODE = 1
7095 22:53:39.370805 DLL_IDLE_MODE = 1
7096 22:53:39.373555 LP45_APHY_COMB_EN = 1
7097 22:53:39.377003 TX_ODT_DIS = 0
7098 22:53:39.380451 NEW_8X_MODE = 1
7099 22:53:39.383849 ===================================
7100 22:53:39.387533 ===================================
7101 22:53:39.388101 data_rate = 3200
7102 22:53:39.390576 CKR = 1
7103 22:53:39.393883 DQ_P2S_RATIO = 8
7104 22:53:39.396758 ===================================
7105 22:53:39.400325 CA_P2S_RATIO = 8
7106 22:53:39.403620 DQ_CA_OPEN = 0
7107 22:53:39.406866 DQ_SEMI_OPEN = 0
7108 22:53:39.407424 CA_SEMI_OPEN = 0
7109 22:53:39.410309 CA_FULL_RATE = 0
7110 22:53:39.413866 DQ_CKDIV4_EN = 0
7111 22:53:39.416810 CA_CKDIV4_EN = 0
7112 22:53:39.419926 CA_PREDIV_EN = 0
7113 22:53:39.423294 PH8_DLY = 12
7114 22:53:39.423753 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7115 22:53:39.426967 DQ_AAMCK_DIV = 4
7116 22:53:39.430183 CA_AAMCK_DIV = 4
7117 22:53:39.433932 CA_ADMCK_DIV = 4
7118 22:53:39.436685 DQ_TRACK_CA_EN = 0
7119 22:53:39.440070 CA_PICK = 1600
7120 22:53:39.443356 CA_MCKIO = 1600
7121 22:53:39.443837 MCKIO_SEMI = 0
7122 22:53:39.447085 PLL_FREQ = 3068
7123 22:53:39.450373 DQ_UI_PI_RATIO = 32
7124 22:53:39.453243 CA_UI_PI_RATIO = 0
7125 22:53:39.457191 ===================================
7126 22:53:39.460065 ===================================
7127 22:53:39.463835 memory_type:LPDDR4
7128 22:53:39.464393 GP_NUM : 10
7129 22:53:39.466729 SRAM_EN : 1
7130 22:53:39.467194 MD32_EN : 0
7131 22:53:39.470123 ===================================
7132 22:53:39.474021 [ANA_INIT] >>>>>>>>>>>>>>
7133 22:53:39.477362 <<<<<< [CONFIGURE PHASE]: ANA_TX
7134 22:53:39.480576 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7135 22:53:39.484005 ===================================
7136 22:53:39.487029 data_rate = 3200,PCW = 0X7600
7137 22:53:39.490434 ===================================
7138 22:53:39.493725 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7139 22:53:39.500320 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7140 22:53:39.503666 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7141 22:53:39.510072 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7142 22:53:39.513446 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7143 22:53:39.516654 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7144 22:53:39.517115 [ANA_INIT] flow start
7145 22:53:39.519940 [ANA_INIT] PLL >>>>>>>>
7146 22:53:39.523646 [ANA_INIT] PLL <<<<<<<<
7147 22:53:39.524261 [ANA_INIT] MIDPI >>>>>>>>
7148 22:53:39.526686 [ANA_INIT] MIDPI <<<<<<<<
7149 22:53:39.530258 [ANA_INIT] DLL >>>>>>>>
7150 22:53:39.530826 [ANA_INIT] DLL <<<<<<<<
7151 22:53:39.533393 [ANA_INIT] flow end
7152 22:53:39.536964 ============ LP4 DIFF to SE enter ============
7153 22:53:39.543619 ============ LP4 DIFF to SE exit ============
7154 22:53:39.544187 [ANA_INIT] <<<<<<<<<<<<<
7155 22:53:39.546729 [Flow] Enable top DCM control >>>>>
7156 22:53:39.550096 [Flow] Enable top DCM control <<<<<
7157 22:53:39.553265 Enable DLL master slave shuffle
7158 22:53:39.559846 ==============================================================
7159 22:53:39.560312 Gating Mode config
7160 22:53:39.566392 ==============================================================
7161 22:53:39.569788 Config description:
7162 22:53:39.576473 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7163 22:53:39.583233 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7164 22:53:39.589730 SELPH_MODE 0: By rank 1: By Phase
7165 22:53:39.596495 ==============================================================
7166 22:53:39.596917 GAT_TRACK_EN = 1
7167 22:53:39.599500 RX_GATING_MODE = 2
7168 22:53:39.603041 RX_GATING_TRACK_MODE = 2
7169 22:53:39.606140 SELPH_MODE = 1
7170 22:53:39.609771 PICG_EARLY_EN = 1
7171 22:53:39.612905 VALID_LAT_VALUE = 1
7172 22:53:39.619457 ==============================================================
7173 22:53:39.622884 Enter into Gating configuration >>>>
7174 22:53:39.625976 Exit from Gating configuration <<<<
7175 22:53:39.629702 Enter into DVFS_PRE_config >>>>>
7176 22:53:39.639451 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7177 22:53:39.642625 Exit from DVFS_PRE_config <<<<<
7178 22:53:39.646300 Enter into PICG configuration >>>>
7179 22:53:39.649365 Exit from PICG configuration <<<<
7180 22:53:39.649448 [RX_INPUT] configuration >>>>>
7181 22:53:39.652608 [RX_INPUT] configuration <<<<<
7182 22:53:39.659250 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7183 22:53:39.666047 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7184 22:53:39.669529 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7185 22:53:39.675916 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7186 22:53:39.682709 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7187 22:53:39.689274 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7188 22:53:39.692359 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7189 22:53:39.695821 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7190 22:53:39.702399 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7191 22:53:39.705709 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7192 22:53:39.709203 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7193 22:53:39.715567 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7194 22:53:39.719290 ===================================
7195 22:53:39.719369 LPDDR4 DRAM CONFIGURATION
7196 22:53:39.723114 ===================================
7197 22:53:39.725910 EX_ROW_EN[0] = 0x0
7198 22:53:39.726049 EX_ROW_EN[1] = 0x0
7199 22:53:39.728895 LP4Y_EN = 0x0
7200 22:53:39.729037 WORK_FSP = 0x1
7201 22:53:39.732448 WL = 0x5
7202 22:53:39.732615 RL = 0x5
7203 22:53:39.735803 BL = 0x2
7204 22:53:39.735886 RPST = 0x0
7205 22:53:39.738973 RD_PRE = 0x0
7206 22:53:39.742349 WR_PRE = 0x1
7207 22:53:39.742432 WR_PST = 0x1
7208 22:53:39.745578 DBI_WR = 0x0
7209 22:53:39.745661 DBI_RD = 0x0
7210 22:53:39.748794 OTF = 0x1
7211 22:53:39.752315 ===================================
7212 22:53:39.755784 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7213 22:53:39.759062 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7214 22:53:39.762156 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7215 22:53:39.765626 ===================================
7216 22:53:39.769163 LPDDR4 DRAM CONFIGURATION
7217 22:53:39.772087 ===================================
7218 22:53:39.775538 EX_ROW_EN[0] = 0x10
7219 22:53:39.775619 EX_ROW_EN[1] = 0x0
7220 22:53:39.779068 LP4Y_EN = 0x0
7221 22:53:39.779172 WORK_FSP = 0x1
7222 22:53:39.782451 WL = 0x5
7223 22:53:39.782540 RL = 0x5
7224 22:53:39.785690 BL = 0x2
7225 22:53:39.785770 RPST = 0x0
7226 22:53:39.788826 RD_PRE = 0x0
7227 22:53:39.788907 WR_PRE = 0x1
7228 22:53:39.791949 WR_PST = 0x1
7229 22:53:39.795458 DBI_WR = 0x0
7230 22:53:39.795539 DBI_RD = 0x0
7231 22:53:39.798743 OTF = 0x1
7232 22:53:39.801783 ===================================
7233 22:53:39.805549 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7234 22:53:39.805631 ==
7235 22:53:39.808523 Dram Type= 6, Freq= 0, CH_0, rank 0
7236 22:53:39.815401 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7237 22:53:39.815484 ==
7238 22:53:39.818593 [Duty_Offset_Calibration]
7239 22:53:39.818674 B0:2 B1:0 CA:1
7240 22:53:39.818737
7241 22:53:39.822017 [DutyScan_Calibration_Flow] k_type=0
7242 22:53:39.830779
7243 22:53:39.830859 ==CLK 0==
7244 22:53:39.833907 Final CLK duty delay cell = -4
7245 22:53:39.837395 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7246 22:53:39.840595 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7247 22:53:39.843872 [-4] AVG Duty = 4922%(X100)
7248 22:53:39.843954
7249 22:53:39.847041 CH0 CLK Duty spec in!! Max-Min= 156%
7250 22:53:39.850554 [DutyScan_Calibration_Flow] ====Done====
7251 22:53:39.850634
7252 22:53:39.853907 [DutyScan_Calibration_Flow] k_type=1
7253 22:53:39.870172
7254 22:53:39.870258 ==DQS 0 ==
7255 22:53:39.873306 Final DQS duty delay cell = 0
7256 22:53:39.877011 [0] MAX Duty = 5249%(X100), DQS PI = 32
7257 22:53:39.880235 [0] MIN Duty = 4938%(X100), DQS PI = 60
7258 22:53:39.884074 [0] AVG Duty = 5093%(X100)
7259 22:53:39.884551
7260 22:53:39.884917 ==DQS 1 ==
7261 22:53:39.887387 Final DQS duty delay cell = -4
7262 22:53:39.890486 [-4] MAX Duty = 5094%(X100), DQS PI = 28
7263 22:53:39.893590 [-4] MIN Duty = 4844%(X100), DQS PI = 6
7264 22:53:39.896950 [-4] AVG Duty = 4969%(X100)
7265 22:53:39.897427
7266 22:53:39.900498 CH0 DQS 0 Duty spec in!! Max-Min= 311%
7267 22:53:39.901027
7268 22:53:39.904017 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7269 22:53:39.906933 [DutyScan_Calibration_Flow] ====Done====
7270 22:53:39.907016
7271 22:53:39.909941 [DutyScan_Calibration_Flow] k_type=3
7272 22:53:39.927657
7273 22:53:39.927779 ==DQM 0 ==
7274 22:53:39.931110 Final DQM duty delay cell = 0
7275 22:53:39.934659 [0] MAX Duty = 5062%(X100), DQS PI = 12
7276 22:53:39.937767 [0] MIN Duty = 4813%(X100), DQS PI = 50
7277 22:53:39.940970 [0] AVG Duty = 4937%(X100)
7278 22:53:39.941105
7279 22:53:39.941211 ==DQM 1 ==
7280 22:53:39.944068 Final DQM duty delay cell = 0
7281 22:53:39.947793 [0] MAX Duty = 5249%(X100), DQS PI = 30
7282 22:53:39.951030 [0] MIN Duty = 5031%(X100), DQS PI = 6
7283 22:53:39.954414 [0] AVG Duty = 5140%(X100)
7284 22:53:39.954697
7285 22:53:39.957618 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7286 22:53:39.957906
7287 22:53:39.961091 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7288 22:53:39.964898 [DutyScan_Calibration_Flow] ====Done====
7289 22:53:39.965520
7290 22:53:39.967774 [DutyScan_Calibration_Flow] k_type=2
7291 22:53:39.985124
7292 22:53:39.985586 ==DQ 0 ==
7293 22:53:39.988275 Final DQ duty delay cell = 0
7294 22:53:39.991907 [0] MAX Duty = 5124%(X100), DQS PI = 34
7295 22:53:39.995241 [0] MIN Duty = 5000%(X100), DQS PI = 0
7296 22:53:39.995647 [0] AVG Duty = 5062%(X100)
7297 22:53:39.995967
7298 22:53:39.998234 ==DQ 1 ==
7299 22:53:40.001705 Final DQ duty delay cell = 0
7300 22:53:40.005178 [0] MAX Duty = 4969%(X100), DQS PI = 44
7301 22:53:40.008139 [0] MIN Duty = 4875%(X100), DQS PI = 10
7302 22:53:40.008548 [0] AVG Duty = 4922%(X100)
7303 22:53:40.008869
7304 22:53:40.011466 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7305 22:53:40.015223
7306 22:53:40.018194 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7307 22:53:40.021894 [DutyScan_Calibration_Flow] ====Done====
7308 22:53:40.022413 ==
7309 22:53:40.025134 Dram Type= 6, Freq= 0, CH_1, rank 0
7310 22:53:40.028390 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7311 22:53:40.028821 ==
7312 22:53:40.031428 [Duty_Offset_Calibration]
7313 22:53:40.031853 B0:0 B1:-1 CA:2
7314 22:53:40.032176
7315 22:53:40.034925 [DutyScan_Calibration_Flow] k_type=0
7316 22:53:40.045256
7317 22:53:40.045741 ==CLK 0==
7318 22:53:40.048473 Final CLK duty delay cell = 0
7319 22:53:40.051990 [0] MAX Duty = 5156%(X100), DQS PI = 12
7320 22:53:40.055409 [0] MIN Duty = 4938%(X100), DQS PI = 44
7321 22:53:40.055818 [0] AVG Duty = 5047%(X100)
7322 22:53:40.058858
7323 22:53:40.062003 CH1 CLK Duty spec in!! Max-Min= 218%
7324 22:53:40.064991 [DutyScan_Calibration_Flow] ====Done====
7325 22:53:40.065551
7326 22:53:40.068331 [DutyScan_Calibration_Flow] k_type=1
7327 22:53:40.085086
7328 22:53:40.085522 ==DQS 0 ==
7329 22:53:40.088512 Final DQS duty delay cell = 0
7330 22:53:40.091421 [0] MAX Duty = 5124%(X100), DQS PI = 26
7331 22:53:40.095094 [0] MIN Duty = 5000%(X100), DQS PI = 0
7332 22:53:40.095603 [0] AVG Duty = 5062%(X100)
7333 22:53:40.098418
7334 22:53:40.098864 ==DQS 1 ==
7335 22:53:40.101728 Final DQS duty delay cell = 0
7336 22:53:40.104663 [0] MAX Duty = 5156%(X100), DQS PI = 0
7337 22:53:40.108149 [0] MIN Duty = 4844%(X100), DQS PI = 34
7338 22:53:40.111051 [0] AVG Duty = 5000%(X100)
7339 22:53:40.111129
7340 22:53:40.114873 CH1 DQS 0 Duty spec in!! Max-Min= 124%
7341 22:53:40.114955
7342 22:53:40.117969 CH1 DQS 1 Duty spec in!! Max-Min= 312%
7343 22:53:40.121206 [DutyScan_Calibration_Flow] ====Done====
7344 22:53:40.121291
7345 22:53:40.124707 [DutyScan_Calibration_Flow] k_type=3
7346 22:53:40.142521
7347 22:53:40.142665 ==DQM 0 ==
7348 22:53:40.146088 Final DQM duty delay cell = 4
7349 22:53:40.148939 [4] MAX Duty = 5125%(X100), DQS PI = 22
7350 22:53:40.152234 [4] MIN Duty = 4969%(X100), DQS PI = 34
7351 22:53:40.155965 [4] AVG Duty = 5047%(X100)
7352 22:53:40.156222
7353 22:53:40.156369 ==DQM 1 ==
7354 22:53:40.159207 Final DQM duty delay cell = 0
7355 22:53:40.162654 [0] MAX Duty = 5281%(X100), DQS PI = 58
7356 22:53:40.165942 [0] MIN Duty = 4876%(X100), DQS PI = 34
7357 22:53:40.168759 [0] AVG Duty = 5078%(X100)
7358 22:53:40.169085
7359 22:53:40.172080 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7360 22:53:40.172381
7361 22:53:40.175834 CH1 DQM 1 Duty spec in!! Max-Min= 405%
7362 22:53:40.178877 [DutyScan_Calibration_Flow] ====Done====
7363 22:53:40.179281
7364 22:53:40.182667 [DutyScan_Calibration_Flow] k_type=2
7365 22:53:40.199795
7366 22:53:40.200348 ==DQ 0 ==
7367 22:53:40.203329 Final DQ duty delay cell = 0
7368 22:53:40.206237 [0] MAX Duty = 5062%(X100), DQS PI = 22
7369 22:53:40.209622 [0] MIN Duty = 4969%(X100), DQS PI = 0
7370 22:53:40.210184 [0] AVG Duty = 5015%(X100)
7371 22:53:40.210547
7372 22:53:40.213215 ==DQ 1 ==
7373 22:53:40.216537 Final DQ duty delay cell = 0
7374 22:53:40.219644 [0] MAX Duty = 5062%(X100), DQS PI = 2
7375 22:53:40.223084 [0] MIN Duty = 4813%(X100), DQS PI = 34
7376 22:53:40.223647 [0] AVG Duty = 4937%(X100)
7377 22:53:40.224015
7378 22:53:40.226165 CH1 DQ 0 Duty spec in!! Max-Min= 93%
7379 22:53:40.226630
7380 22:53:40.229566 CH1 DQ 1 Duty spec in!! Max-Min= 249%
7381 22:53:40.236079 [DutyScan_Calibration_Flow] ====Done====
7382 22:53:40.239643 nWR fixed to 30
7383 22:53:40.240112 [ModeRegInit_LP4] CH0 RK0
7384 22:53:40.243232 [ModeRegInit_LP4] CH0 RK1
7385 22:53:40.246555 [ModeRegInit_LP4] CH1 RK0
7386 22:53:40.247124 [ModeRegInit_LP4] CH1 RK1
7387 22:53:40.249616 match AC timing 5
7388 22:53:40.252940 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7389 22:53:40.256175 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7390 22:53:40.262810 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7391 22:53:40.265978 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7392 22:53:40.272888 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7393 22:53:40.273469 [MiockJmeterHQA]
7394 22:53:40.273844
7395 22:53:40.276148 [DramcMiockJmeter] u1RxGatingPI = 0
7396 22:53:40.279373 0 : 4255, 4027
7397 22:53:40.279850 4 : 4368, 4139
7398 22:53:40.280225 8 : 4255, 4027
7399 22:53:40.282357 12 : 4257, 4029
7400 22:53:40.282830 16 : 4362, 4137
7401 22:53:40.285816 20 : 4252, 4027
7402 22:53:40.286287 24 : 4253, 4026
7403 22:53:40.289466 28 : 4366, 4140
7404 22:53:40.289941 32 : 4363, 4138
7405 22:53:40.290315 36 : 4363, 4138
7406 22:53:40.292630 40 : 4255, 4029
7407 22:53:40.293199 44 : 4363, 4137
7408 22:53:40.295784 48 : 4252, 4027
7409 22:53:40.296256 52 : 4255, 4029
7410 22:53:40.298991 56 : 4254, 4029
7411 22:53:40.299516 60 : 4252, 4027
7412 22:53:40.302638 64 : 4252, 4030
7413 22:53:40.303206 68 : 4250, 4027
7414 22:53:40.303581 72 : 4250, 4027
7415 22:53:40.305969 76 : 4250, 4027
7416 22:53:40.306438 80 : 4363, 4140
7417 22:53:40.309811 84 : 4249, 4027
7418 22:53:40.310385 88 : 4253, 3673
7419 22:53:40.312539 92 : 4250, 0
7420 22:53:40.313109 96 : 4250, 0
7421 22:53:40.313547 100 : 4363, 0
7422 22:53:40.315940 104 : 4250, 0
7423 22:53:40.316509 108 : 4252, 0
7424 22:53:40.316888 112 : 4250, 0
7425 22:53:40.319110 116 : 4250, 0
7426 22:53:40.319582 120 : 4250, 0
7427 22:53:40.322624 124 : 4250, 0
7428 22:53:40.323196 128 : 4250, 0
7429 22:53:40.323570 132 : 4252, 0
7430 22:53:40.326041 136 : 4361, 0
7431 22:53:40.326511 140 : 4360, 0
7432 22:53:40.329243 144 : 4249, 0
7433 22:53:40.329756 148 : 4250, 0
7434 22:53:40.330136 152 : 4250, 0
7435 22:53:40.332351 156 : 4360, 0
7436 22:53:40.332821 160 : 4250, 0
7437 22:53:40.335633 164 : 4250, 0
7438 22:53:40.336107 168 : 4250, 0
7439 22:53:40.336482 172 : 4250, 0
7440 22:53:40.339030 176 : 4250, 0
7441 22:53:40.339733 180 : 4250, 0
7442 22:53:40.340124 184 : 4250, 0
7443 22:53:40.342550 188 : 4361, 0
7444 22:53:40.343128 192 : 4360, 0
7445 22:53:40.346000 196 : 4250, 0
7446 22:53:40.346583 200 : 4250, 8
7447 22:53:40.346963 204 : 4250, 2655
7448 22:53:40.349203 208 : 4250, 4027
7449 22:53:40.349806 212 : 4250, 4027
7450 22:53:40.352355 216 : 4361, 4137
7451 22:53:40.352826 220 : 4360, 4137
7452 22:53:40.356235 224 : 4363, 4139
7453 22:53:40.356815 228 : 4250, 4027
7454 22:53:40.359306 232 : 4249, 4027
7455 22:53:40.359783 236 : 4250, 4026
7456 22:53:40.362457 240 : 4250, 4026
7457 22:53:40.363041 244 : 4250, 4027
7458 22:53:40.365982 248 : 4360, 4138
7459 22:53:40.366564 252 : 4250, 4027
7460 22:53:40.369017 256 : 4250, 4026
7461 22:53:40.369511 260 : 4250, 4027
7462 22:53:40.372432 264 : 4250, 4027
7463 22:53:40.372906 268 : 4360, 4137
7464 22:53:40.373278 272 : 4250, 4026
7465 22:53:40.375839 276 : 4361, 4137
7466 22:53:40.376419 280 : 4250, 4027
7467 22:53:40.379340 284 : 4249, 4027
7468 22:53:40.379927 288 : 4250, 4026
7469 22:53:40.382297 292 : 4250, 4026
7470 22:53:40.382773 296 : 4255, 4029
7471 22:53:40.385429 300 : 4360, 4138
7472 22:53:40.385900 304 : 4249, 4027
7473 22:53:40.389294 308 : 4250, 4026
7474 22:53:40.389916 312 : 4255, 3912
7475 22:53:40.392298 316 : 4250, 1715
7476 22:53:40.392877
7477 22:53:40.393249 MIOCK jitter meter ch=0
7478 22:53:40.393629
7479 22:53:40.395419 1T = (316-92) = 224 dly cells
7480 22:53:40.401967 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7481 22:53:40.402525 ==
7482 22:53:40.405576 Dram Type= 6, Freq= 0, CH_0, rank 0
7483 22:53:40.409291 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7484 22:53:40.409885 ==
7485 22:53:40.415632 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7486 22:53:40.418855 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7487 22:53:40.422048 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7488 22:53:40.428853 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7489 22:53:40.438503 [CA 0] Center 43 (13~73) winsize 61
7490 22:53:40.441877 [CA 1] Center 43 (13~73) winsize 61
7491 22:53:40.445139 [CA 2] Center 38 (8~68) winsize 61
7492 22:53:40.448329 [CA 3] Center 37 (8~67) winsize 60
7493 22:53:40.452051 [CA 4] Center 36 (6~66) winsize 61
7494 22:53:40.455225 [CA 5] Center 35 (5~66) winsize 62
7495 22:53:40.455797
7496 22:53:40.457974 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7497 22:53:40.458442
7498 22:53:40.461513 [CATrainingPosCal] consider 1 rank data
7499 22:53:40.465051 u2DelayCellTimex100 = 290/100 ps
7500 22:53:40.468532 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7501 22:53:40.474818 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7502 22:53:40.478194 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7503 22:53:40.481803 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7504 22:53:40.485014 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7505 22:53:40.488380 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
7506 22:53:40.488969
7507 22:53:40.491538 CA PerBit enable=1, Macro0, CA PI delay=35
7508 22:53:40.492006
7509 22:53:40.494628 [CBTSetCACLKResult] CA Dly = 35
7510 22:53:40.497859 CS Dly: 9 (0~40)
7511 22:53:40.501656 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7512 22:53:40.505140 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7513 22:53:40.505764 ==
7514 22:53:40.508078 Dram Type= 6, Freq= 0, CH_0, rank 1
7515 22:53:40.511634 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7516 22:53:40.514536 ==
7517 22:53:40.517822 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7518 22:53:40.521554 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7519 22:53:40.528160 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7520 22:53:40.531704 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7521 22:53:40.541618 [CA 0] Center 43 (13~73) winsize 61
7522 22:53:40.545017 [CA 1] Center 43 (13~73) winsize 61
7523 22:53:40.548485 [CA 2] Center 38 (9~67) winsize 59
7524 22:53:40.551818 [CA 3] Center 38 (8~68) winsize 61
7525 22:53:40.554807 [CA 4] Center 37 (7~67) winsize 61
7526 22:53:40.558043 [CA 5] Center 36 (6~66) winsize 61
7527 22:53:40.558515
7528 22:53:40.561604 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7529 22:53:40.562175
7530 22:53:40.564982 [CATrainingPosCal] consider 2 rank data
7531 22:53:40.567852 u2DelayCellTimex100 = 290/100 ps
7532 22:53:40.571474 CA0 delay=43 (13~73),Diff = 7 PI (23 cell)
7533 22:53:40.578230 CA1 delay=43 (13~73),Diff = 7 PI (23 cell)
7534 22:53:40.581664 CA2 delay=38 (9~67),Diff = 2 PI (6 cell)
7535 22:53:40.584683 CA3 delay=37 (8~67),Diff = 1 PI (3 cell)
7536 22:53:40.587959 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7537 22:53:40.590944 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7538 22:53:40.591414
7539 22:53:40.594751 CA PerBit enable=1, Macro0, CA PI delay=36
7540 22:53:40.595318
7541 22:53:40.598037 [CBTSetCACLKResult] CA Dly = 36
7542 22:53:40.601152 CS Dly: 10 (0~43)
7543 22:53:40.604524 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7544 22:53:40.608165 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7545 22:53:40.608736
7546 22:53:40.611357 ----->DramcWriteLeveling(PI) begin...
7547 22:53:40.611938 ==
7548 22:53:40.614497 Dram Type= 6, Freq= 0, CH_0, rank 0
7549 22:53:40.621229 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7550 22:53:40.621847 ==
7551 22:53:40.624481 Write leveling (Byte 0): 37 => 37
7552 22:53:40.625050 Write leveling (Byte 1): 31 => 31
7553 22:53:40.627632 DramcWriteLeveling(PI) end<-----
7554 22:53:40.628096
7555 22:53:40.628459 ==
7556 22:53:40.631096 Dram Type= 6, Freq= 0, CH_0, rank 0
7557 22:53:40.637691 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7558 22:53:40.638191 ==
7559 22:53:40.640965 [Gating] SW mode calibration
7560 22:53:40.646932 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7561 22:53:40.650847 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7562 22:53:40.656965 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7563 22:53:40.660943 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7564 22:53:40.664300 1 4 8 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
7565 22:53:40.670680 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7566 22:53:40.673856 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7567 22:53:40.677428 1 4 20 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
7568 22:53:40.684021 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7569 22:53:40.687267 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7570 22:53:40.690453 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7571 22:53:40.697094 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7572 22:53:40.700372 1 5 8 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 0)
7573 22:53:40.704232 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7574 22:53:40.710717 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7575 22:53:40.713772 1 5 20 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
7576 22:53:40.717071 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7577 22:53:40.723612 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7578 22:53:40.727224 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7579 22:53:40.730443 1 6 4 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
7580 22:53:40.737408 1 6 8 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
7581 22:53:40.740399 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7582 22:53:40.743725 1 6 16 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
7583 22:53:40.746976 1 6 20 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
7584 22:53:40.753675 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7585 22:53:40.756795 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7586 22:53:40.760371 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7587 22:53:40.767025 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7588 22:53:40.770294 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7589 22:53:40.773710 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7590 22:53:40.780465 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7591 22:53:40.783554 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7592 22:53:40.787035 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7593 22:53:40.793628 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7594 22:53:40.796733 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7595 22:53:40.800417 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7596 22:53:40.806851 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7597 22:53:40.810070 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7598 22:53:40.813757 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7599 22:53:40.820109 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7600 22:53:40.823516 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7601 22:53:40.826951 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7602 22:53:40.833549 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7603 22:53:40.837040 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7604 22:53:40.840478 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7605 22:53:40.846654 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7606 22:53:40.849871 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7607 22:53:40.853545 Total UI for P1: 0, mck2ui 16
7608 22:53:40.856347 best dqsien dly found for B0: ( 1, 9, 10)
7609 22:53:40.859919 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7610 22:53:40.866807 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7611 22:53:40.867361 Total UI for P1: 0, mck2ui 16
7612 22:53:40.870033 best dqsien dly found for B1: ( 1, 9, 18)
7613 22:53:40.876452 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7614 22:53:40.879805 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7615 22:53:40.880366
7616 22:53:40.882922 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7617 22:53:40.886188 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7618 22:53:40.889569 [Gating] SW calibration Done
7619 22:53:40.890034 ==
7620 22:53:40.892906 Dram Type= 6, Freq= 0, CH_0, rank 0
7621 22:53:40.896214 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7622 22:53:40.896772 ==
7623 22:53:40.899587 RX Vref Scan: 0
7624 22:53:40.900055
7625 22:53:40.900442 RX Vref 0 -> 0, step: 1
7626 22:53:40.900781
7627 22:53:40.903353 RX Delay 0 -> 252, step: 8
7628 22:53:40.906546 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
7629 22:53:40.913044 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7630 22:53:40.916365 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7631 22:53:40.919743 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7632 22:53:40.923235 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7633 22:53:40.926758 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7634 22:53:40.929403 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7635 22:53:40.935944 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7636 22:53:40.939690 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7637 22:53:40.943002 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7638 22:53:40.946306 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7639 22:53:40.949679 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
7640 22:53:40.956276 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7641 22:53:40.959500 iDelay=200, Bit 13, Center 127 (80 ~ 175) 96
7642 22:53:40.963031 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7643 22:53:40.966056 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7644 22:53:40.966531 ==
7645 22:53:40.969625 Dram Type= 6, Freq= 0, CH_0, rank 0
7646 22:53:40.976592 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7647 22:53:40.977165 ==
7648 22:53:40.977586 DQS Delay:
7649 22:53:40.977932 DQS0 = 0, DQS1 = 0
7650 22:53:40.979859 DQM Delay:
7651 22:53:40.980453 DQM0 = 138, DQM1 = 126
7652 22:53:40.983269 DQ Delay:
7653 22:53:40.986266 DQ0 =139, DQ1 =139, DQ2 =135, DQ3 =135
7654 22:53:40.989443 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =147
7655 22:53:40.993292 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =123
7656 22:53:40.996405 DQ12 =131, DQ13 =127, DQ14 =139, DQ15 =135
7657 22:53:40.996989
7658 22:53:40.997403
7659 22:53:40.997750 ==
7660 22:53:40.999693 Dram Type= 6, Freq= 0, CH_0, rank 0
7661 22:53:41.002580 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7662 22:53:41.006308 ==
7663 22:53:41.006883
7664 22:53:41.007252
7665 22:53:41.007599 TX Vref Scan disable
7666 22:53:41.009331 == TX Byte 0 ==
7667 22:53:41.012893 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7668 22:53:41.016389 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7669 22:53:41.019532 == TX Byte 1 ==
7670 22:53:41.023137 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7671 22:53:41.026042 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7672 22:53:41.029417 ==
7673 22:53:41.030010 Dram Type= 6, Freq= 0, CH_0, rank 0
7674 22:53:41.035665 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7675 22:53:41.036225 ==
7676 22:53:41.048247
7677 22:53:41.051706 TX Vref early break, caculate TX vref
7678 22:53:41.055277 TX Vref=16, minBit 12, minWin=22, winSum=376
7679 22:53:41.058252 TX Vref=18, minBit 6, minWin=23, winSum=388
7680 22:53:41.061460 TX Vref=20, minBit 6, minWin=24, winSum=397
7681 22:53:41.065016 TX Vref=22, minBit 7, minWin=24, winSum=405
7682 22:53:41.068390 TX Vref=24, minBit 7, minWin=24, winSum=414
7683 22:53:41.075092 TX Vref=26, minBit 7, minWin=25, winSum=423
7684 22:53:41.078456 TX Vref=28, minBit 0, minWin=26, winSum=434
7685 22:53:41.081243 TX Vref=30, minBit 0, minWin=26, winSum=422
7686 22:53:41.084748 TX Vref=32, minBit 0, minWin=25, winSum=414
7687 22:53:41.088184 TX Vref=34, minBit 7, minWin=24, winSum=406
7688 22:53:41.095272 [TxChooseVref] Worse bit 0, Min win 26, Win sum 434, Final Vref 28
7689 22:53:41.095842
7690 22:53:41.098214 Final TX Range 0 Vref 28
7691 22:53:41.098684
7692 22:53:41.099049 ==
7693 22:53:41.101406 Dram Type= 6, Freq= 0, CH_0, rank 0
7694 22:53:41.104763 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7695 22:53:41.105373 ==
7696 22:53:41.105756
7697 22:53:41.106196
7698 22:53:41.108392 TX Vref Scan disable
7699 22:53:41.115117 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7700 22:53:41.115691 == TX Byte 0 ==
7701 22:53:41.118026 u2DelayCellOfst[0]=13 cells (4 PI)
7702 22:53:41.121761 u2DelayCellOfst[1]=20 cells (6 PI)
7703 22:53:41.124662 u2DelayCellOfst[2]=13 cells (4 PI)
7704 22:53:41.128032 u2DelayCellOfst[3]=13 cells (4 PI)
7705 22:53:41.131293 u2DelayCellOfst[4]=10 cells (3 PI)
7706 22:53:41.134748 u2DelayCellOfst[5]=0 cells (0 PI)
7707 22:53:41.137944 u2DelayCellOfst[6]=20 cells (6 PI)
7708 22:53:41.141573 u2DelayCellOfst[7]=16 cells (5 PI)
7709 22:53:41.144480 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7710 22:53:41.147924 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7711 22:53:41.151435 == TX Byte 1 ==
7712 22:53:41.152007 u2DelayCellOfst[8]=0 cells (0 PI)
7713 22:53:41.154781 u2DelayCellOfst[9]=0 cells (0 PI)
7714 22:53:41.158329 u2DelayCellOfst[10]=6 cells (2 PI)
7715 22:53:41.161110 u2DelayCellOfst[11]=3 cells (1 PI)
7716 22:53:41.164588 u2DelayCellOfst[12]=13 cells (4 PI)
7717 22:53:41.167895 u2DelayCellOfst[13]=10 cells (3 PI)
7718 22:53:41.171351 u2DelayCellOfst[14]=13 cells (4 PI)
7719 22:53:41.174575 u2DelayCellOfst[15]=10 cells (3 PI)
7720 22:53:41.177921 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7721 22:53:41.184581 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7722 22:53:41.185164 DramC Write-DBI on
7723 22:53:41.185683 ==
7724 22:53:41.187776 Dram Type= 6, Freq= 0, CH_0, rank 0
7725 22:53:41.191201 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7726 22:53:41.194755 ==
7727 22:53:41.195331
7728 22:53:41.195806
7729 22:53:41.196247 TX Vref Scan disable
7730 22:53:41.197742 == TX Byte 0 ==
7731 22:53:41.201393 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7732 22:53:41.204459 == TX Byte 1 ==
7733 22:53:41.207627 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7734 22:53:41.211321 DramC Write-DBI off
7735 22:53:41.211892
7736 22:53:41.212366 [DATLAT]
7737 22:53:41.212813 Freq=1600, CH0 RK0
7738 22:53:41.213243
7739 22:53:41.214192 DATLAT Default: 0xf
7740 22:53:41.214644 0, 0xFFFF, sum = 0
7741 22:53:41.217889 1, 0xFFFF, sum = 0
7742 22:53:41.218460 2, 0xFFFF, sum = 0
7743 22:53:41.221213 3, 0xFFFF, sum = 0
7744 22:53:41.224243 4, 0xFFFF, sum = 0
7745 22:53:41.224706 5, 0xFFFF, sum = 0
7746 22:53:41.227803 6, 0xFFFF, sum = 0
7747 22:53:41.228428 7, 0xFFFF, sum = 0
7748 22:53:41.231069 8, 0xFFFF, sum = 0
7749 22:53:41.231535 9, 0xFFFF, sum = 0
7750 22:53:41.234546 10, 0xFFFF, sum = 0
7751 22:53:41.235116 11, 0xFFFF, sum = 0
7752 22:53:41.237826 12, 0xFFFF, sum = 0
7753 22:53:41.238406 13, 0xFFFF, sum = 0
7754 22:53:41.241449 14, 0x0, sum = 1
7755 22:53:41.242052 15, 0x0, sum = 2
7756 22:53:41.244254 16, 0x0, sum = 3
7757 22:53:41.244817 17, 0x0, sum = 4
7758 22:53:41.247965 best_step = 15
7759 22:53:41.248526
7760 22:53:41.248890 ==
7761 22:53:41.251594 Dram Type= 6, Freq= 0, CH_0, rank 0
7762 22:53:41.254779 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7763 22:53:41.255350 ==
7764 22:53:41.255719 RX Vref Scan: 1
7765 22:53:41.257618
7766 22:53:41.258075 Set Vref Range= 24 -> 127
7767 22:53:41.258437
7768 22:53:41.260794 RX Vref 24 -> 127, step: 1
7769 22:53:41.261254
7770 22:53:41.264396 RX Delay 19 -> 252, step: 4
7771 22:53:41.264961
7772 22:53:41.268229 Set Vref, RX VrefLevel [Byte0]: 24
7773 22:53:41.271566 [Byte1]: 24
7774 22:53:41.272137
7775 22:53:41.274553 Set Vref, RX VrefLevel [Byte0]: 25
7776 22:53:41.277993 [Byte1]: 25
7777 22:53:41.278679
7778 22:53:41.280979 Set Vref, RX VrefLevel [Byte0]: 26
7779 22:53:41.284649 [Byte1]: 26
7780 22:53:41.288338
7781 22:53:41.288924 Set Vref, RX VrefLevel [Byte0]: 27
7782 22:53:41.291848 [Byte1]: 27
7783 22:53:41.296147
7784 22:53:41.296715 Set Vref, RX VrefLevel [Byte0]: 28
7785 22:53:41.298892 [Byte1]: 28
7786 22:53:41.303747
7787 22:53:41.304315 Set Vref, RX VrefLevel [Byte0]: 29
7788 22:53:41.306680 [Byte1]: 29
7789 22:53:41.311063
7790 22:53:41.311627 Set Vref, RX VrefLevel [Byte0]: 30
7791 22:53:41.314448 [Byte1]: 30
7792 22:53:41.318569
7793 22:53:41.319124 Set Vref, RX VrefLevel [Byte0]: 31
7794 22:53:41.321479 [Byte1]: 31
7795 22:53:41.325971
7796 22:53:41.326432 Set Vref, RX VrefLevel [Byte0]: 32
7797 22:53:41.329645 [Byte1]: 32
7798 22:53:41.333903
7799 22:53:41.334472 Set Vref, RX VrefLevel [Byte0]: 33
7800 22:53:41.336809 [Byte1]: 33
7801 22:53:41.341327
7802 22:53:41.344569 Set Vref, RX VrefLevel [Byte0]: 34
7803 22:53:41.347460 [Byte1]: 34
7804 22:53:41.347929
7805 22:53:41.350856 Set Vref, RX VrefLevel [Byte0]: 35
7806 22:53:41.354539 [Byte1]: 35
7807 22:53:41.355110
7808 22:53:41.358207 Set Vref, RX VrefLevel [Byte0]: 36
7809 22:53:41.361353 [Byte1]: 36
7810 22:53:41.361922
7811 22:53:41.364729 Set Vref, RX VrefLevel [Byte0]: 37
7812 22:53:41.367687 [Byte1]: 37
7813 22:53:41.371471
7814 22:53:41.372033 Set Vref, RX VrefLevel [Byte0]: 38
7815 22:53:41.374693 [Byte1]: 38
7816 22:53:41.379361
7817 22:53:41.379929 Set Vref, RX VrefLevel [Byte0]: 39
7818 22:53:41.382604 [Byte1]: 39
7819 22:53:41.386427
7820 22:53:41.386892 Set Vref, RX VrefLevel [Byte0]: 40
7821 22:53:41.390079 [Byte1]: 40
7822 22:53:41.394437
7823 22:53:41.395005 Set Vref, RX VrefLevel [Byte0]: 41
7824 22:53:41.397598 [Byte1]: 41
7825 22:53:41.402127
7826 22:53:41.402690 Set Vref, RX VrefLevel [Byte0]: 42
7827 22:53:41.405159 [Byte1]: 42
7828 22:53:41.409465
7829 22:53:41.410029 Set Vref, RX VrefLevel [Byte0]: 43
7830 22:53:41.412797 [Byte1]: 43
7831 22:53:41.416959
7832 22:53:41.417567 Set Vref, RX VrefLevel [Byte0]: 44
7833 22:53:41.420628 [Byte1]: 44
7834 22:53:41.424799
7835 22:53:41.425435 Set Vref, RX VrefLevel [Byte0]: 45
7836 22:53:41.427931 [Byte1]: 45
7837 22:53:41.432385
7838 22:53:41.432957 Set Vref, RX VrefLevel [Byte0]: 46
7839 22:53:41.435303 [Byte1]: 46
7840 22:53:41.439567
7841 22:53:41.440028 Set Vref, RX VrefLevel [Byte0]: 47
7842 22:53:41.442967 [Byte1]: 47
7843 22:53:41.447346
7844 22:53:41.447806 Set Vref, RX VrefLevel [Byte0]: 48
7845 22:53:41.450764 [Byte1]: 48
7846 22:53:41.454720
7847 22:53:41.455282 Set Vref, RX VrefLevel [Byte0]: 49
7848 22:53:41.457970 [Byte1]: 49
7849 22:53:41.462395
7850 22:53:41.462959 Set Vref, RX VrefLevel [Byte0]: 50
7851 22:53:41.465519 [Byte1]: 50
7852 22:53:41.470097
7853 22:53:41.470664 Set Vref, RX VrefLevel [Byte0]: 51
7854 22:53:41.472957 [Byte1]: 51
7855 22:53:41.477680
7856 22:53:41.478426 Set Vref, RX VrefLevel [Byte0]: 52
7857 22:53:41.480646 [Byte1]: 52
7858 22:53:41.485334
7859 22:53:41.485899 Set Vref, RX VrefLevel [Byte0]: 53
7860 22:53:41.488482 [Byte1]: 53
7861 22:53:41.492747
7862 22:53:41.493209 Set Vref, RX VrefLevel [Byte0]: 54
7863 22:53:41.496125 [Byte1]: 54
7864 22:53:41.500520
7865 22:53:41.501089 Set Vref, RX VrefLevel [Byte0]: 55
7866 22:53:41.503840 [Byte1]: 55
7867 22:53:41.507507
7868 22:53:41.507972 Set Vref, RX VrefLevel [Byte0]: 56
7869 22:53:41.510848 [Byte1]: 56
7870 22:53:41.515591
7871 22:53:41.516167 Set Vref, RX VrefLevel [Byte0]: 57
7872 22:53:41.518748 [Byte1]: 57
7873 22:53:41.523117
7874 22:53:41.523685 Set Vref, RX VrefLevel [Byte0]: 58
7875 22:53:41.526185 [Byte1]: 58
7876 22:53:41.530325
7877 22:53:41.530845 Set Vref, RX VrefLevel [Byte0]: 59
7878 22:53:41.533862 [Byte1]: 59
7879 22:53:41.538026
7880 22:53:41.538491 Set Vref, RX VrefLevel [Byte0]: 60
7881 22:53:41.541521 [Byte1]: 60
7882 22:53:41.545738
7883 22:53:41.546230 Set Vref, RX VrefLevel [Byte0]: 61
7884 22:53:41.548663 [Byte1]: 61
7885 22:53:41.553273
7886 22:53:41.553786 Set Vref, RX VrefLevel [Byte0]: 62
7887 22:53:41.556535 [Byte1]: 62
7888 22:53:41.561030
7889 22:53:41.561649 Set Vref, RX VrefLevel [Byte0]: 63
7890 22:53:41.564388 [Byte1]: 63
7891 22:53:41.568548
7892 22:53:41.569103 Set Vref, RX VrefLevel [Byte0]: 64
7893 22:53:41.571920 [Byte1]: 64
7894 22:53:41.576320
7895 22:53:41.576881 Set Vref, RX VrefLevel [Byte0]: 65
7896 22:53:41.579516 [Byte1]: 65
7897 22:53:41.583514
7898 22:53:41.583975 Set Vref, RX VrefLevel [Byte0]: 66
7899 22:53:41.586431 [Byte1]: 66
7900 22:53:41.590964
7901 22:53:41.591527 Set Vref, RX VrefLevel [Byte0]: 67
7902 22:53:41.594543 [Byte1]: 67
7903 22:53:41.598818
7904 22:53:41.599419 Set Vref, RX VrefLevel [Byte0]: 68
7905 22:53:41.601812 [Byte1]: 68
7906 22:53:41.605923
7907 22:53:41.606386 Set Vref, RX VrefLevel [Byte0]: 69
7908 22:53:41.609454 [Byte1]: 69
7909 22:53:41.614146
7910 22:53:41.614705 Set Vref, RX VrefLevel [Byte0]: 70
7911 22:53:41.617030 [Byte1]: 70
7912 22:53:41.621477
7913 22:53:41.622035 Set Vref, RX VrefLevel [Byte0]: 71
7914 22:53:41.624717 [Byte1]: 71
7915 22:53:41.628930
7916 22:53:41.629519 Set Vref, RX VrefLevel [Byte0]: 72
7917 22:53:41.632464 [Byte1]: 72
7918 22:53:41.636719
7919 22:53:41.637377 Set Vref, RX VrefLevel [Byte0]: 73
7920 22:53:41.639685 [Byte1]: 73
7921 22:53:41.644212
7922 22:53:41.644673 Set Vref, RX VrefLevel [Byte0]: 74
7923 22:53:41.647266 [Byte1]: 74
7924 22:53:41.652126
7925 22:53:41.652692 Set Vref, RX VrefLevel [Byte0]: 75
7926 22:53:41.655209 [Byte1]: 75
7927 22:53:41.659636
7928 22:53:41.660195 Set Vref, RX VrefLevel [Byte0]: 76
7929 22:53:41.662509 [Byte1]: 76
7930 22:53:41.666794
7931 22:53:41.667273 Set Vref, RX VrefLevel [Byte0]: 77
7932 22:53:41.670215 [Byte1]: 77
7933 22:53:41.674481
7934 22:53:41.675459 Final RX Vref Byte 0 = 65 to rank0
7935 22:53:41.677567 Final RX Vref Byte 1 = 62 to rank0
7936 22:53:41.681266 Final RX Vref Byte 0 = 65 to rank1
7937 22:53:41.684442 Final RX Vref Byte 1 = 62 to rank1==
7938 22:53:41.687876 Dram Type= 6, Freq= 0, CH_0, rank 0
7939 22:53:41.691398 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7940 22:53:41.694535 ==
7941 22:53:41.695093 DQS Delay:
7942 22:53:41.695454 DQS0 = 0, DQS1 = 0
7943 22:53:41.697996 DQM Delay:
7944 22:53:41.698453 DQM0 = 135, DQM1 = 123
7945 22:53:41.701521 DQ Delay:
7946 22:53:41.704865 DQ0 =134, DQ1 =136, DQ2 =132, DQ3 =134
7947 22:53:41.708154 DQ4 =138, DQ5 =126, DQ6 =144, DQ7 =142
7948 22:53:41.711184 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =118
7949 22:53:41.714875 DQ12 =126, DQ13 =128, DQ14 =136, DQ15 =132
7950 22:53:41.715435
7951 22:53:41.715797
7952 22:53:41.716130
7953 22:53:41.717824 [DramC_TX_OE_Calibration] TA2
7954 22:53:41.720983 Original DQ_B0 (3 6) =30, OEN = 27
7955 22:53:41.724426 Original DQ_B1 (3 6) =30, OEN = 27
7956 22:53:41.727604 24, 0x0, End_B0=24 End_B1=24
7957 22:53:41.728174 25, 0x0, End_B0=25 End_B1=25
7958 22:53:41.731162 26, 0x0, End_B0=26 End_B1=26
7959 22:53:41.734511 27, 0x0, End_B0=27 End_B1=27
7960 22:53:41.737744 28, 0x0, End_B0=28 End_B1=28
7961 22:53:41.738219 29, 0x0, End_B0=29 End_B1=29
7962 22:53:41.741167 30, 0x0, End_B0=30 End_B1=30
7963 22:53:41.744526 31, 0x4141, End_B0=30 End_B1=30
7964 22:53:41.747478 Byte0 end_step=30 best_step=27
7965 22:53:41.751333 Byte1 end_step=30 best_step=27
7966 22:53:41.754253 Byte0 TX OE(2T, 0.5T) = (3, 3)
7967 22:53:41.754724 Byte1 TX OE(2T, 0.5T) = (3, 3)
7968 22:53:41.755096
7969 22:53:41.757800
7970 22:53:41.764667 [DQSOSCAuto] RK0, (LSB)MR18= 0x201e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
7971 22:53:41.767543 CH0 RK0: MR19=303, MR18=201E
7972 22:53:41.774507 CH0_RK0: MR19=0x303, MR18=0x201E, DQSOSC=393, MR23=63, INC=23, DEC=15
7973 22:53:41.775084
7974 22:53:41.777950 ----->DramcWriteLeveling(PI) begin...
7975 22:53:41.778530 ==
7976 22:53:41.781165 Dram Type= 6, Freq= 0, CH_0, rank 1
7977 22:53:41.784507 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7978 22:53:41.785082 ==
7979 22:53:41.787849 Write leveling (Byte 0): 39 => 39
7980 22:53:41.790928 Write leveling (Byte 1): 28 => 28
7981 22:53:41.794471 DramcWriteLeveling(PI) end<-----
7982 22:53:41.795047
7983 22:53:41.795531 ==
7984 22:53:41.797348 Dram Type= 6, Freq= 0, CH_0, rank 1
7985 22:53:41.800984 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7986 22:53:41.801646 ==
7987 22:53:41.804486 [Gating] SW mode calibration
7988 22:53:41.811139 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7989 22:53:41.817952 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7990 22:53:41.821224 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7991 22:53:41.824513 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7992 22:53:41.831229 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7993 22:53:41.834461 1 4 12 | B1->B0 | 2626 3232 | 0 0 | (0 0) (0 0)
7994 22:53:41.837758 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7995 22:53:41.844339 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7996 22:53:41.847399 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7997 22:53:41.850970 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7998 22:53:41.857448 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7999 22:53:41.861285 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8000 22:53:41.864521 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8001 22:53:41.870708 1 5 12 | B1->B0 | 3434 2b2b | 1 1 | (1 0) (1 0)
8002 22:53:41.874288 1 5 16 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
8003 22:53:41.877509 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8004 22:53:41.884098 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8005 22:53:41.887537 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8006 22:53:41.890890 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8007 22:53:41.894029 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8008 22:53:41.900700 1 6 8 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
8009 22:53:41.904062 1 6 12 | B1->B0 | 2d2d 4242 | 0 1 | (0 0) (0 0)
8010 22:53:41.907542 1 6 16 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
8011 22:53:41.913924 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8012 22:53:41.917745 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8013 22:53:41.920947 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8014 22:53:41.927397 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8015 22:53:41.930443 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8016 22:53:41.933791 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8017 22:53:41.940433 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8018 22:53:41.943902 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8019 22:53:41.946959 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8020 22:53:41.954062 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8021 22:53:41.956983 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8022 22:53:41.960336 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8023 22:53:41.967336 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8024 22:53:41.970477 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8025 22:53:41.973501 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8026 22:53:41.980181 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8027 22:53:41.983568 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8028 22:53:41.986781 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8029 22:53:41.993697 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8030 22:53:41.996880 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8031 22:53:42.000356 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8032 22:53:42.006915 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8033 22:53:42.010663 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8034 22:53:42.013914 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8035 22:53:42.017160 Total UI for P1: 0, mck2ui 16
8036 22:53:42.020497 best dqsien dly found for B0: ( 1, 9, 10)
8037 22:53:42.023761 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8038 22:53:42.027036 Total UI for P1: 0, mck2ui 16
8039 22:53:42.030587 best dqsien dly found for B1: ( 1, 9, 14)
8040 22:53:42.033680 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8041 22:53:42.037158 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8042 22:53:42.037673
8043 22:53:42.043653 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8044 22:53:42.047093 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8045 22:53:42.050318 [Gating] SW calibration Done
8046 22:53:42.050778 ==
8047 22:53:42.053722 Dram Type= 6, Freq= 0, CH_0, rank 1
8048 22:53:42.057096 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8049 22:53:42.057604 ==
8050 22:53:42.057968 RX Vref Scan: 0
8051 22:53:42.060259
8052 22:53:42.060818 RX Vref 0 -> 0, step: 1
8053 22:53:42.061183
8054 22:53:42.063934 RX Delay 0 -> 252, step: 8
8055 22:53:42.067077 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8056 22:53:42.070182 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8057 22:53:42.076839 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8058 22:53:42.079718 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8059 22:53:42.083419 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8060 22:53:42.087080 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
8061 22:53:42.090147 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8062 22:53:42.096952 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8063 22:53:42.100291 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8064 22:53:42.103382 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8065 22:53:42.106626 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8066 22:53:42.109866 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8067 22:53:42.117018 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8068 22:53:42.120577 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8069 22:53:42.123630 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8070 22:53:42.126839 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8071 22:53:42.127396 ==
8072 22:53:42.130103 Dram Type= 6, Freq= 0, CH_0, rank 1
8073 22:53:42.137023 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8074 22:53:42.137723 ==
8075 22:53:42.138199 DQS Delay:
8076 22:53:42.138615 DQS0 = 0, DQS1 = 0
8077 22:53:42.139737 DQM Delay:
8078 22:53:42.140190 DQM0 = 136, DQM1 = 125
8079 22:53:42.143167 DQ Delay:
8080 22:53:42.146783 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =131
8081 22:53:42.149935 DQ4 =139, DQ5 =123, DQ6 =143, DQ7 =143
8082 22:53:42.153474 DQ8 =119, DQ9 =111, DQ10 =123, DQ11 =123
8083 22:53:42.156627 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8084 22:53:42.157111
8085 22:53:42.157542
8086 22:53:42.157886 ==
8087 22:53:42.160433 Dram Type= 6, Freq= 0, CH_0, rank 1
8088 22:53:42.163302 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8089 22:53:42.163805 ==
8090 22:53:42.166530
8091 22:53:42.167008
8092 22:53:42.167366 TX Vref Scan disable
8093 22:53:42.169971 == TX Byte 0 ==
8094 22:53:42.173063 Update DQ dly =995 (3 ,6, 35) DQ OEN =(3 ,3)
8095 22:53:42.176583 Update DQM dly =995 (3 ,6, 35) DQM OEN =(3 ,3)
8096 22:53:42.180044 == TX Byte 1 ==
8097 22:53:42.183313 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8098 22:53:42.186392 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8099 22:53:42.186894 ==
8100 22:53:42.190010 Dram Type= 6, Freq= 0, CH_0, rank 1
8101 22:53:42.196703 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8102 22:53:42.197264 ==
8103 22:53:42.211145
8104 22:53:42.214688 TX Vref early break, caculate TX vref
8105 22:53:42.217604 TX Vref=16, minBit 12, minWin=23, winSum=390
8106 22:53:42.220948 TX Vref=18, minBit 8, minWin=23, winSum=397
8107 22:53:42.224633 TX Vref=20, minBit 8, minWin=24, winSum=407
8108 22:53:42.227681 TX Vref=22, minBit 8, minWin=24, winSum=411
8109 22:53:42.231197 TX Vref=24, minBit 0, minWin=25, winSum=419
8110 22:53:42.237554 TX Vref=26, minBit 0, minWin=25, winSum=427
8111 22:53:42.241180 TX Vref=28, minBit 4, minWin=25, winSum=428
8112 22:53:42.244473 TX Vref=30, minBit 0, minWin=26, winSum=427
8113 22:53:42.247730 TX Vref=32, minBit 2, minWin=25, winSum=418
8114 22:53:42.250762 TX Vref=34, minBit 0, minWin=25, winSum=412
8115 22:53:42.254123 TX Vref=36, minBit 12, minWin=24, winSum=403
8116 22:53:42.261188 [TxChooseVref] Worse bit 0, Min win 26, Win sum 427, Final Vref 30
8117 22:53:42.261799
8118 22:53:42.264452 Final TX Range 0 Vref 30
8119 22:53:42.265029
8120 22:53:42.265462 ==
8121 22:53:42.267781 Dram Type= 6, Freq= 0, CH_0, rank 1
8122 22:53:42.271076 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8123 22:53:42.271547 ==
8124 22:53:42.271917
8125 22:53:42.272264
8126 22:53:42.274438 TX Vref Scan disable
8127 22:53:42.280897 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8128 22:53:42.281474 == TX Byte 0 ==
8129 22:53:42.284374 u2DelayCellOfst[0]=13 cells (4 PI)
8130 22:53:42.287579 u2DelayCellOfst[1]=20 cells (6 PI)
8131 22:53:42.290851 u2DelayCellOfst[2]=13 cells (4 PI)
8132 22:53:42.294467 u2DelayCellOfst[3]=13 cells (4 PI)
8133 22:53:42.297678 u2DelayCellOfst[4]=10 cells (3 PI)
8134 22:53:42.301054 u2DelayCellOfst[5]=0 cells (0 PI)
8135 22:53:42.304253 u2DelayCellOfst[6]=20 cells (6 PI)
8136 22:53:42.308089 u2DelayCellOfst[7]=16 cells (5 PI)
8137 22:53:42.311044 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8138 22:53:42.314256 Update DQM dly =995 (3 ,6, 35) DQM OEN =(3 ,3)
8139 22:53:42.317493 == TX Byte 1 ==
8140 22:53:42.321106 u2DelayCellOfst[8]=0 cells (0 PI)
8141 22:53:42.324301 u2DelayCellOfst[9]=3 cells (1 PI)
8142 22:53:42.324883 u2DelayCellOfst[10]=6 cells (2 PI)
8143 22:53:42.327506 u2DelayCellOfst[11]=3 cells (1 PI)
8144 22:53:42.330774 u2DelayCellOfst[12]=13 cells (4 PI)
8145 22:53:42.334095 u2DelayCellOfst[13]=13 cells (4 PI)
8146 22:53:42.337259 u2DelayCellOfst[14]=13 cells (4 PI)
8147 22:53:42.340914 u2DelayCellOfst[15]=10 cells (3 PI)
8148 22:53:42.347140 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8149 22:53:42.350522 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8150 22:53:42.351247 DramC Write-DBI on
8151 22:53:42.351720 ==
8152 22:53:42.354334 Dram Type= 6, Freq= 0, CH_0, rank 1
8153 22:53:42.360704 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8154 22:53:42.361257 ==
8155 22:53:42.361787
8156 22:53:42.362233
8157 22:53:42.362671 TX Vref Scan disable
8158 22:53:42.364567 == TX Byte 0 ==
8159 22:53:42.367985 Update DQM dly =738 (2 ,6, 34) DQM OEN =(3 ,3)
8160 22:53:42.371062 == TX Byte 1 ==
8161 22:53:42.374672 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8162 22:53:42.377834 DramC Write-DBI off
8163 22:53:42.378303
8164 22:53:42.378671 [DATLAT]
8165 22:53:42.379014 Freq=1600, CH0 RK1
8166 22:53:42.379344
8167 22:53:42.381215 DATLAT Default: 0xf
8168 22:53:42.381719 0, 0xFFFF, sum = 0
8169 22:53:42.384393 1, 0xFFFF, sum = 0
8170 22:53:42.387678 2, 0xFFFF, sum = 0
8171 22:53:42.388154 3, 0xFFFF, sum = 0
8172 22:53:42.391137 4, 0xFFFF, sum = 0
8173 22:53:42.391613 5, 0xFFFF, sum = 0
8174 22:53:42.394411 6, 0xFFFF, sum = 0
8175 22:53:42.394887 7, 0xFFFF, sum = 0
8176 22:53:42.398165 8, 0xFFFF, sum = 0
8177 22:53:42.398929 9, 0xFFFF, sum = 0
8178 22:53:42.401206 10, 0xFFFF, sum = 0
8179 22:53:42.401737 11, 0xFFFF, sum = 0
8180 22:53:42.404377 12, 0xFFFF, sum = 0
8181 22:53:42.404851 13, 0xFFFF, sum = 0
8182 22:53:42.408000 14, 0x0, sum = 1
8183 22:53:42.408577 15, 0x0, sum = 2
8184 22:53:42.411777 16, 0x0, sum = 3
8185 22:53:42.412353 17, 0x0, sum = 4
8186 22:53:42.414756 best_step = 15
8187 22:53:42.415336
8188 22:53:42.415709 ==
8189 22:53:42.417936 Dram Type= 6, Freq= 0, CH_0, rank 1
8190 22:53:42.421383 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8191 22:53:42.421952 ==
8192 22:53:42.422326 RX Vref Scan: 0
8193 22:53:42.424667
8194 22:53:42.425420 RX Vref 0 -> 0, step: 1
8195 22:53:42.425879
8196 22:53:42.428250 RX Delay 11 -> 252, step: 4
8197 22:53:42.431104 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8198 22:53:42.437969 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8199 22:53:42.441414 iDelay=191, Bit 2, Center 132 (83 ~ 182) 100
8200 22:53:42.444643 iDelay=191, Bit 3, Center 128 (79 ~ 178) 100
8201 22:53:42.447872 iDelay=191, Bit 4, Center 134 (83 ~ 186) 104
8202 22:53:42.450917 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8203 22:53:42.457793 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8204 22:53:42.461361 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8205 22:53:42.464618 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8206 22:53:42.467872 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8207 22:53:42.471345 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8208 22:53:42.477805 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8209 22:53:42.481389 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8210 22:53:42.484790 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8211 22:53:42.488333 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8212 22:53:42.491216 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8213 22:53:42.491685 ==
8214 22:53:42.494857 Dram Type= 6, Freq= 0, CH_0, rank 1
8215 22:53:42.501351 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8216 22:53:42.501911 ==
8217 22:53:42.502288 DQS Delay:
8218 22:53:42.504596 DQS0 = 0, DQS1 = 0
8219 22:53:42.505063 DQM Delay:
8220 22:53:42.508291 DQM0 = 133, DQM1 = 123
8221 22:53:42.508859 DQ Delay:
8222 22:53:42.511603 DQ0 =132, DQ1 =136, DQ2 =132, DQ3 =128
8223 22:53:42.514785 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =138
8224 22:53:42.517840 DQ8 =116, DQ9 =110, DQ10 =124, DQ11 =120
8225 22:53:42.521652 DQ12 =126, DQ13 =128, DQ14 =132, DQ15 =128
8226 22:53:42.522224
8227 22:53:42.522600
8228 22:53:42.522945
8229 22:53:42.524376 [DramC_TX_OE_Calibration] TA2
8230 22:53:42.528170 Original DQ_B0 (3 6) =30, OEN = 27
8231 22:53:42.531625 Original DQ_B1 (3 6) =30, OEN = 27
8232 22:53:42.534294 24, 0x0, End_B0=24 End_B1=24
8233 22:53:42.537922 25, 0x0, End_B0=25 End_B1=25
8234 22:53:42.538505 26, 0x0, End_B0=26 End_B1=26
8235 22:53:42.541164 27, 0x0, End_B0=27 End_B1=27
8236 22:53:42.544535 28, 0x0, End_B0=28 End_B1=28
8237 22:53:42.548016 29, 0x0, End_B0=29 End_B1=29
8238 22:53:42.548595 30, 0x0, End_B0=30 End_B1=30
8239 22:53:42.551010 31, 0x5151, End_B0=30 End_B1=30
8240 22:53:42.554588 Byte0 end_step=30 best_step=27
8241 22:53:42.557939 Byte1 end_step=30 best_step=27
8242 22:53:42.561050 Byte0 TX OE(2T, 0.5T) = (3, 3)
8243 22:53:42.564640 Byte1 TX OE(2T, 0.5T) = (3, 3)
8244 22:53:42.565198
8245 22:53:42.565634
8246 22:53:42.571468 [DQSOSCAuto] RK1, (LSB)MR18= 0x210e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 393 ps
8247 22:53:42.574356 CH0 RK1: MR19=303, MR18=210E
8248 22:53:42.580855 CH0_RK1: MR19=0x303, MR18=0x210E, DQSOSC=393, MR23=63, INC=23, DEC=15
8249 22:53:42.584684 [RxdqsGatingPostProcess] freq 1600
8250 22:53:42.587987 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8251 22:53:42.590981 best DQS0 dly(2T, 0.5T) = (1, 1)
8252 22:53:42.594231 best DQS1 dly(2T, 0.5T) = (1, 1)
8253 22:53:42.597542 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8254 22:53:42.600829 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8255 22:53:42.604469 best DQS0 dly(2T, 0.5T) = (1, 1)
8256 22:53:42.607810 best DQS1 dly(2T, 0.5T) = (1, 1)
8257 22:53:42.610973 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8258 22:53:42.614198 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8259 22:53:42.617854 Pre-setting of DQS Precalculation
8260 22:53:42.621086 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8261 22:53:42.621690 ==
8262 22:53:42.624346 Dram Type= 6, Freq= 0, CH_1, rank 0
8263 22:53:42.627507 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8264 22:53:42.631223 ==
8265 22:53:42.634193 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8266 22:53:42.637359 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8267 22:53:42.644025 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8268 22:53:42.647660 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8269 22:53:42.657936 [CA 0] Center 41 (12~71) winsize 60
8270 22:53:42.661362 [CA 1] Center 42 (12~72) winsize 61
8271 22:53:42.664828 [CA 2] Center 38 (9~68) winsize 60
8272 22:53:42.667837 [CA 3] Center 37 (8~67) winsize 60
8273 22:53:42.671654 [CA 4] Center 37 (8~67) winsize 60
8274 22:53:42.674553 [CA 5] Center 37 (7~67) winsize 61
8275 22:53:42.675107
8276 22:53:42.677767 [CmdBusTrainingLP45] Vref(ca) range 0: 28
8277 22:53:42.678239
8278 22:53:42.681564 [CATrainingPosCal] consider 1 rank data
8279 22:53:42.684802 u2DelayCellTimex100 = 290/100 ps
8280 22:53:42.687840 CA0 delay=41 (12~71),Diff = 4 PI (13 cell)
8281 22:53:42.694541 CA1 delay=42 (12~72),Diff = 5 PI (16 cell)
8282 22:53:42.697752 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8283 22:53:42.700819 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8284 22:53:42.704460 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8285 22:53:42.707986 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8286 22:53:42.708763
8287 22:53:42.711062 CA PerBit enable=1, Macro0, CA PI delay=37
8288 22:53:42.711699
8289 22:53:42.714181 [CBTSetCACLKResult] CA Dly = 37
8290 22:53:42.714643 CS Dly: 8 (0~39)
8291 22:53:42.721198 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8292 22:53:42.724924 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8293 22:53:42.725531 ==
8294 22:53:42.727961 Dram Type= 6, Freq= 0, CH_1, rank 1
8295 22:53:42.730876 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8296 22:53:42.731328 ==
8297 22:53:42.737680 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8298 22:53:42.740929 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8299 22:53:42.747726 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8300 22:53:42.751037 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8301 22:53:42.760986 [CA 0] Center 41 (12~71) winsize 60
8302 22:53:42.764686 [CA 1] Center 41 (12~71) winsize 60
8303 22:53:42.767651 [CA 2] Center 38 (9~67) winsize 59
8304 22:53:42.770548 [CA 3] Center 37 (8~67) winsize 60
8305 22:53:42.773866 [CA 4] Center 37 (8~67) winsize 60
8306 22:53:42.777241 [CA 5] Center 37 (7~67) winsize 61
8307 22:53:42.777817
8308 22:53:42.780902 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8309 22:53:42.781391
8310 22:53:42.784244 [CATrainingPosCal] consider 2 rank data
8311 22:53:42.787449 u2DelayCellTimex100 = 290/100 ps
8312 22:53:42.790671 CA0 delay=41 (12~71),Diff = 4 PI (13 cell)
8313 22:53:42.797587 CA1 delay=41 (12~71),Diff = 4 PI (13 cell)
8314 22:53:42.801462 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8315 22:53:42.804146 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8316 22:53:42.807640 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8317 22:53:42.810804 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8318 22:53:42.811355
8319 22:53:42.814421 CA PerBit enable=1, Macro0, CA PI delay=37
8320 22:53:42.815016
8321 22:53:42.817427 [CBTSetCACLKResult] CA Dly = 37
8322 22:53:42.820970 CS Dly: 9 (0~42)
8323 22:53:42.824513 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8324 22:53:42.827191 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8325 22:53:42.827742
8326 22:53:42.830493 ----->DramcWriteLeveling(PI) begin...
8327 22:53:42.831051 ==
8328 22:53:42.833884 Dram Type= 6, Freq= 0, CH_1, rank 0
8329 22:53:42.840196 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8330 22:53:42.840651 ==
8331 22:53:42.843579 Write leveling (Byte 0): 26 => 26
8332 22:53:42.844028 Write leveling (Byte 1): 28 => 28
8333 22:53:42.847247 DramcWriteLeveling(PI) end<-----
8334 22:53:42.847794
8335 22:53:42.848145 ==
8336 22:53:42.850417 Dram Type= 6, Freq= 0, CH_1, rank 0
8337 22:53:42.857275 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8338 22:53:42.857864 ==
8339 22:53:42.860426 [Gating] SW mode calibration
8340 22:53:42.867074 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8341 22:53:42.870233 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8342 22:53:42.876880 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8343 22:53:42.880292 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8344 22:53:42.883396 1 4 8 | B1->B0 | 2d2d 3232 | 0 1 | (0 0) (1 1)
8345 22:53:42.890122 1 4 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8346 22:53:42.893344 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8347 22:53:42.896654 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8348 22:53:42.903679 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8349 22:53:42.906675 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8350 22:53:42.910438 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8351 22:53:42.913245 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8352 22:53:42.920391 1 5 8 | B1->B0 | 2d2d 2c2c | 1 1 | (1 0) (1 0)
8353 22:53:42.923670 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8354 22:53:42.926891 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8355 22:53:42.933748 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8356 22:53:42.936942 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8357 22:53:42.939899 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8358 22:53:42.946908 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8359 22:53:42.949866 1 6 4 | B1->B0 | 2424 2929 | 0 0 | (0 0) (0 0)
8360 22:53:42.953349 1 6 8 | B1->B0 | 4141 4545 | 0 0 | (0 0) (0 0)
8361 22:53:42.960562 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8362 22:53:42.963474 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8363 22:53:42.966884 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8364 22:53:42.973689 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8365 22:53:42.976633 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8366 22:53:42.980078 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8367 22:53:42.986879 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8368 22:53:42.990112 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8369 22:53:42.993420 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8370 22:53:42.999725 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8371 22:53:43.003041 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8372 22:53:43.006526 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8373 22:53:43.013347 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8374 22:53:43.016762 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8375 22:53:43.020284 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8376 22:53:43.026554 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8377 22:53:43.029726 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8378 22:53:43.033398 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8379 22:53:43.039893 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8380 22:53:43.043478 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8381 22:53:43.046701 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8382 22:53:43.052788 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8383 22:53:43.056368 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8384 22:53:43.059918 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8385 22:53:43.063315 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8386 22:53:43.066667 Total UI for P1: 0, mck2ui 16
8387 22:53:43.069810 best dqsien dly found for B0: ( 1, 9, 6)
8388 22:53:43.076430 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8389 22:53:43.079480 Total UI for P1: 0, mck2ui 16
8390 22:53:43.082825 best dqsien dly found for B1: ( 1, 9, 10)
8391 22:53:43.086321 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8392 22:53:43.089229 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8393 22:53:43.089759
8394 22:53:43.092734 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8395 22:53:43.096161 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8396 22:53:43.099141 [Gating] SW calibration Done
8397 22:53:43.099611 ==
8398 22:53:43.102894 Dram Type= 6, Freq= 0, CH_1, rank 0
8399 22:53:43.105907 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8400 22:53:43.106388 ==
8401 22:53:43.109734 RX Vref Scan: 0
8402 22:53:43.110295
8403 22:53:43.112952 RX Vref 0 -> 0, step: 1
8404 22:53:43.113659
8405 22:53:43.114036 RX Delay 0 -> 252, step: 8
8406 22:53:43.116164 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8407 22:53:43.122717 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8408 22:53:43.125905 iDelay=200, Bit 2, Center 127 (80 ~ 175) 96
8409 22:53:43.129261 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8410 22:53:43.132894 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8411 22:53:43.136354 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8412 22:53:43.143172 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8413 22:53:43.145926 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8414 22:53:43.149444 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8415 22:53:43.152512 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8416 22:53:43.155867 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8417 22:53:43.162496 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8418 22:53:43.166007 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8419 22:53:43.169252 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8420 22:53:43.172535 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8421 22:53:43.176270 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8422 22:53:43.179407 ==
8423 22:53:43.179968 Dram Type= 6, Freq= 0, CH_1, rank 0
8424 22:53:43.185761 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8425 22:53:43.186320 ==
8426 22:53:43.186692 DQS Delay:
8427 22:53:43.189069 DQS0 = 0, DQS1 = 0
8428 22:53:43.189673 DQM Delay:
8429 22:53:43.192274 DQM0 = 138, DQM1 = 130
8430 22:53:43.192944 DQ Delay:
8431 22:53:43.195819 DQ0 =143, DQ1 =131, DQ2 =127, DQ3 =139
8432 22:53:43.199085 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8433 22:53:43.202145 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =127
8434 22:53:43.205742 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =135
8435 22:53:43.206202
8436 22:53:43.206737
8437 22:53:43.207091 ==
8438 22:53:43.209161 Dram Type= 6, Freq= 0, CH_1, rank 0
8439 22:53:43.215525 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8440 22:53:43.216093 ==
8441 22:53:43.216462
8442 22:53:43.216799
8443 22:53:43.217118 TX Vref Scan disable
8444 22:53:43.219056 == TX Byte 0 ==
8445 22:53:43.222342 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8446 22:53:43.229258 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8447 22:53:43.229909 == TX Byte 1 ==
8448 22:53:43.232515 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8449 22:53:43.239206 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8450 22:53:43.239764 ==
8451 22:53:43.242875 Dram Type= 6, Freq= 0, CH_1, rank 0
8452 22:53:43.245872 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8453 22:53:43.246440 ==
8454 22:53:43.257735
8455 22:53:43.261285 TX Vref early break, caculate TX vref
8456 22:53:43.264503 TX Vref=16, minBit 10, minWin=21, winSum=367
8457 22:53:43.268016 TX Vref=18, minBit 8, minWin=22, winSum=376
8458 22:53:43.271602 TX Vref=20, minBit 8, minWin=22, winSum=388
8459 22:53:43.274884 TX Vref=22, minBit 10, minWin=23, winSum=396
8460 22:53:43.277856 TX Vref=24, minBit 10, minWin=24, winSum=407
8461 22:53:43.284423 TX Vref=26, minBit 15, minWin=24, winSum=415
8462 22:53:43.287687 TX Vref=28, minBit 9, minWin=25, winSum=418
8463 22:53:43.290924 TX Vref=30, minBit 13, minWin=24, winSum=412
8464 22:53:43.294664 TX Vref=32, minBit 8, minWin=24, winSum=403
8465 22:53:43.297861 TX Vref=34, minBit 11, minWin=23, winSum=394
8466 22:53:43.303996 [TxChooseVref] Worse bit 9, Min win 25, Win sum 418, Final Vref 28
8467 22:53:43.304590
8468 22:53:43.307230 Final TX Range 0 Vref 28
8469 22:53:43.307762
8470 22:53:43.308247 ==
8471 22:53:43.310695 Dram Type= 6, Freq= 0, CH_1, rank 0
8472 22:53:43.313770 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8473 22:53:43.314449 ==
8474 22:53:43.315057
8475 22:53:43.315612
8476 22:53:43.317393 TX Vref Scan disable
8477 22:53:43.324209 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8478 22:53:43.324908 == TX Byte 0 ==
8479 22:53:43.327392 u2DelayCellOfst[0]=13 cells (4 PI)
8480 22:53:43.330654 u2DelayCellOfst[1]=6 cells (2 PI)
8481 22:53:43.334035 u2DelayCellOfst[2]=0 cells (0 PI)
8482 22:53:43.337418 u2DelayCellOfst[3]=3 cells (1 PI)
8483 22:53:43.340431 u2DelayCellOfst[4]=6 cells (2 PI)
8484 22:53:43.343968 u2DelayCellOfst[5]=16 cells (5 PI)
8485 22:53:43.347276 u2DelayCellOfst[6]=16 cells (5 PI)
8486 22:53:43.350428 u2DelayCellOfst[7]=3 cells (1 PI)
8487 22:53:43.353931 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8488 22:53:43.356931 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8489 22:53:43.360248 == TX Byte 1 ==
8490 22:53:43.363777 u2DelayCellOfst[8]=0 cells (0 PI)
8491 22:53:43.363940 u2DelayCellOfst[9]=3 cells (1 PI)
8492 22:53:43.366795 u2DelayCellOfst[10]=13 cells (4 PI)
8493 22:53:43.370274 u2DelayCellOfst[11]=3 cells (1 PI)
8494 22:53:43.373339 u2DelayCellOfst[12]=16 cells (5 PI)
8495 22:53:43.376626 u2DelayCellOfst[13]=20 cells (6 PI)
8496 22:53:43.380261 u2DelayCellOfst[14]=20 cells (6 PI)
8497 22:53:43.383598 u2DelayCellOfst[15]=16 cells (5 PI)
8498 22:53:43.387141 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8499 22:53:43.393533 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8500 22:53:43.393697 DramC Write-DBI on
8501 22:53:43.393772 ==
8502 22:53:43.397227 Dram Type= 6, Freq= 0, CH_1, rank 0
8503 22:53:43.400824 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8504 22:53:43.403791 ==
8505 22:53:43.403957
8506 22:53:43.404034
8507 22:53:43.404106 TX Vref Scan disable
8508 22:53:43.406932 == TX Byte 0 ==
8509 22:53:43.410880 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8510 22:53:43.414084 == TX Byte 1 ==
8511 22:53:43.416952 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8512 22:53:43.420443 DramC Write-DBI off
8513 22:53:43.420636
8514 22:53:43.420737 [DATLAT]
8515 22:53:43.420829 Freq=1600, CH1 RK0
8516 22:53:43.420915
8517 22:53:43.423561 DATLAT Default: 0xf
8518 22:53:43.423682 0, 0xFFFF, sum = 0
8519 22:53:43.427053 1, 0xFFFF, sum = 0
8520 22:53:43.427268 2, 0xFFFF, sum = 0
8521 22:53:43.430710 3, 0xFFFF, sum = 0
8522 22:53:43.434079 4, 0xFFFF, sum = 0
8523 22:53:43.434287 5, 0xFFFF, sum = 0
8524 22:53:43.437181 6, 0xFFFF, sum = 0
8525 22:53:43.437462 7, 0xFFFF, sum = 0
8526 22:53:43.440324 8, 0xFFFF, sum = 0
8527 22:53:43.440604 9, 0xFFFF, sum = 0
8528 22:53:43.443823 10, 0xFFFF, sum = 0
8529 22:53:43.444101 11, 0xFFFF, sum = 0
8530 22:53:43.447083 12, 0xFFFF, sum = 0
8531 22:53:43.447398 13, 0xFFFF, sum = 0
8532 22:53:43.450315 14, 0x0, sum = 1
8533 22:53:43.450693 15, 0x0, sum = 2
8534 22:53:43.453686 16, 0x0, sum = 3
8535 22:53:43.454056 17, 0x0, sum = 4
8536 22:53:43.457267 best_step = 15
8537 22:53:43.457700
8538 22:53:43.458069 ==
8539 22:53:43.460589 Dram Type= 6, Freq= 0, CH_1, rank 0
8540 22:53:43.463990 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8541 22:53:43.464581 ==
8542 22:53:43.465069 RX Vref Scan: 1
8543 22:53:43.467813
8544 22:53:43.468379 Set Vref Range= 24 -> 127
8545 22:53:43.468746
8546 22:53:43.470883 RX Vref 24 -> 127, step: 1
8547 22:53:43.471448
8548 22:53:43.474111 RX Delay 19 -> 252, step: 4
8549 22:53:43.474568
8550 22:53:43.477208 Set Vref, RX VrefLevel [Byte0]: 24
8551 22:53:43.480457 [Byte1]: 24
8552 22:53:43.480916
8553 22:53:43.483722 Set Vref, RX VrefLevel [Byte0]: 25
8554 22:53:43.487043 [Byte1]: 25
8555 22:53:43.487502
8556 22:53:43.490222 Set Vref, RX VrefLevel [Byte0]: 26
8557 22:53:43.493611 [Byte1]: 26
8558 22:53:43.497664
8559 22:53:43.498121 Set Vref, RX VrefLevel [Byte0]: 27
8560 22:53:43.500800 [Byte1]: 27
8561 22:53:43.504900
8562 22:53:43.505220 Set Vref, RX VrefLevel [Byte0]: 28
8563 22:53:43.508309 [Byte1]: 28
8564 22:53:43.512316
8565 22:53:43.512554 Set Vref, RX VrefLevel [Byte0]: 29
8566 22:53:43.515788 [Byte1]: 29
8567 22:53:43.520226
8568 22:53:43.520381 Set Vref, RX VrefLevel [Byte0]: 30
8569 22:53:43.523699 [Byte1]: 30
8570 22:53:43.527563
8571 22:53:43.527697 Set Vref, RX VrefLevel [Byte0]: 31
8572 22:53:43.530903 [Byte1]: 31
8573 22:53:43.535041
8574 22:53:43.535154 Set Vref, RX VrefLevel [Byte0]: 32
8575 22:53:43.538641 [Byte1]: 32
8576 22:53:43.542761
8577 22:53:43.542855 Set Vref, RX VrefLevel [Byte0]: 33
8578 22:53:43.545919 [Byte1]: 33
8579 22:53:43.550357
8580 22:53:43.550530 Set Vref, RX VrefLevel [Byte0]: 34
8581 22:53:43.553878 [Byte1]: 34
8582 22:53:43.558390
8583 22:53:43.558562 Set Vref, RX VrefLevel [Byte0]: 35
8584 22:53:43.561118 [Byte1]: 35
8585 22:53:43.565785
8586 22:53:43.565958 Set Vref, RX VrefLevel [Byte0]: 36
8587 22:53:43.569040 [Byte1]: 36
8588 22:53:43.572993
8589 22:53:43.573167 Set Vref, RX VrefLevel [Byte0]: 37
8590 22:53:43.576459 [Byte1]: 37
8591 22:53:43.580493
8592 22:53:43.580668 Set Vref, RX VrefLevel [Byte0]: 38
8593 22:53:43.583803 [Byte1]: 38
8594 22:53:43.588198
8595 22:53:43.588465 Set Vref, RX VrefLevel [Byte0]: 39
8596 22:53:43.591482 [Byte1]: 39
8597 22:53:43.595874
8598 22:53:43.596092 Set Vref, RX VrefLevel [Byte0]: 40
8599 22:53:43.599096 [Byte1]: 40
8600 22:53:43.603493
8601 22:53:43.603711 Set Vref, RX VrefLevel [Byte0]: 41
8602 22:53:43.606848 [Byte1]: 41
8603 22:53:43.611327
8604 22:53:43.611717 Set Vref, RX VrefLevel [Byte0]: 42
8605 22:53:43.614530 [Byte1]: 42
8606 22:53:43.618921
8607 22:53:43.619480 Set Vref, RX VrefLevel [Byte0]: 43
8608 22:53:43.622220 [Byte1]: 43
8609 22:53:43.626898
8610 22:53:43.627522 Set Vref, RX VrefLevel [Byte0]: 44
8611 22:53:43.629840 [Byte1]: 44
8612 22:53:43.633744
8613 22:53:43.634231 Set Vref, RX VrefLevel [Byte0]: 45
8614 22:53:43.637292 [Byte1]: 45
8615 22:53:43.641420
8616 22:53:43.641972 Set Vref, RX VrefLevel [Byte0]: 46
8617 22:53:43.644477 [Byte1]: 46
8618 22:53:43.649043
8619 22:53:43.649544 Set Vref, RX VrefLevel [Byte0]: 47
8620 22:53:43.652551 [Byte1]: 47
8621 22:53:43.656717
8622 22:53:43.657271 Set Vref, RX VrefLevel [Byte0]: 48
8623 22:53:43.659822 [Byte1]: 48
8624 22:53:43.664365
8625 22:53:43.664897 Set Vref, RX VrefLevel [Byte0]: 49
8626 22:53:43.667626 [Byte1]: 49
8627 22:53:43.671906
8628 22:53:43.672476 Set Vref, RX VrefLevel [Byte0]: 50
8629 22:53:43.674913 [Byte1]: 50
8630 22:53:43.679137
8631 22:53:43.679600 Set Vref, RX VrefLevel [Byte0]: 51
8632 22:53:43.682589 [Byte1]: 51
8633 22:53:43.687497
8634 22:53:43.688056 Set Vref, RX VrefLevel [Byte0]: 52
8635 22:53:43.690792 [Byte1]: 52
8636 22:53:43.695022
8637 22:53:43.695580 Set Vref, RX VrefLevel [Byte0]: 53
8638 22:53:43.697735 [Byte1]: 53
8639 22:53:43.702483
8640 22:53:43.703038 Set Vref, RX VrefLevel [Byte0]: 54
8641 22:53:43.705894 [Byte1]: 54
8642 22:53:43.710040
8643 22:53:43.710660 Set Vref, RX VrefLevel [Byte0]: 55
8644 22:53:43.713367 [Byte1]: 55
8645 22:53:43.717438
8646 22:53:43.717988 Set Vref, RX VrefLevel [Byte0]: 56
8647 22:53:43.720350 [Byte1]: 56
8648 22:53:43.725182
8649 22:53:43.725789 Set Vref, RX VrefLevel [Byte0]: 57
8650 22:53:43.728338 [Byte1]: 57
8651 22:53:43.732361
8652 22:53:43.732836 Set Vref, RX VrefLevel [Byte0]: 58
8653 22:53:43.735588 [Byte1]: 58
8654 22:53:43.740046
8655 22:53:43.740652 Set Vref, RX VrefLevel [Byte0]: 59
8656 22:53:43.743378 [Byte1]: 59
8657 22:53:43.747293
8658 22:53:43.747750 Set Vref, RX VrefLevel [Byte0]: 60
8659 22:53:43.751029 [Byte1]: 60
8660 22:53:43.754978
8661 22:53:43.755433 Set Vref, RX VrefLevel [Byte0]: 61
8662 22:53:43.758139 [Byte1]: 61
8663 22:53:43.762454
8664 22:53:43.762908 Set Vref, RX VrefLevel [Byte0]: 62
8665 22:53:43.766154 [Byte1]: 62
8666 22:53:43.770250
8667 22:53:43.770799 Set Vref, RX VrefLevel [Byte0]: 63
8668 22:53:43.773332 [Byte1]: 63
8669 22:53:43.777891
8670 22:53:43.778417 Set Vref, RX VrefLevel [Byte0]: 64
8671 22:53:43.781228 [Byte1]: 64
8672 22:53:43.785378
8673 22:53:43.785983 Set Vref, RX VrefLevel [Byte0]: 65
8674 22:53:43.788455 [Byte1]: 65
8675 22:53:43.793114
8676 22:53:43.793705 Set Vref, RX VrefLevel [Byte0]: 66
8677 22:53:43.796316 [Byte1]: 66
8678 22:53:43.800729
8679 22:53:43.801333 Set Vref, RX VrefLevel [Byte0]: 67
8680 22:53:43.804257 [Byte1]: 67
8681 22:53:43.807904
8682 22:53:43.808362 Set Vref, RX VrefLevel [Byte0]: 68
8683 22:53:43.811194 [Byte1]: 68
8684 22:53:43.815801
8685 22:53:43.816371 Set Vref, RX VrefLevel [Byte0]: 69
8686 22:53:43.819368 [Byte1]: 69
8687 22:53:43.823542
8688 22:53:43.824100 Set Vref, RX VrefLevel [Byte0]: 70
8689 22:53:43.826676 [Byte1]: 70
8690 22:53:43.831033
8691 22:53:43.831592 Set Vref, RX VrefLevel [Byte0]: 71
8692 22:53:43.834296 [Byte1]: 71
8693 22:53:43.838221
8694 22:53:43.838720 Set Vref, RX VrefLevel [Byte0]: 72
8695 22:53:43.841393 [Byte1]: 72
8696 22:53:43.845909
8697 22:53:43.846369 Set Vref, RX VrefLevel [Byte0]: 73
8698 22:53:43.849116 [Byte1]: 73
8699 22:53:43.854024
8700 22:53:43.854586 Set Vref, RX VrefLevel [Byte0]: 74
8701 22:53:43.856896 [Byte1]: 74
8702 22:53:43.861175
8703 22:53:43.861689 Final RX Vref Byte 0 = 53 to rank0
8704 22:53:43.864318 Final RX Vref Byte 1 = 62 to rank0
8705 22:53:43.867614 Final RX Vref Byte 0 = 53 to rank1
8706 22:53:43.871387 Final RX Vref Byte 1 = 62 to rank1==
8707 22:53:43.874441 Dram Type= 6, Freq= 0, CH_1, rank 0
8708 22:53:43.880924 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8709 22:53:43.881435 ==
8710 22:53:43.881806 DQS Delay:
8711 22:53:43.882139 DQS0 = 0, DQS1 = 0
8712 22:53:43.884220 DQM Delay:
8713 22:53:43.884674 DQM0 = 133, DQM1 = 129
8714 22:53:43.887393 DQ Delay:
8715 22:53:43.891262 DQ0 =136, DQ1 =130, DQ2 =122, DQ3 =132
8716 22:53:43.894412 DQ4 =132, DQ5 =144, DQ6 =144, DQ7 =130
8717 22:53:43.897445 DQ8 =116, DQ9 =120, DQ10 =132, DQ11 =122
8718 22:53:43.900832 DQ12 =140, DQ13 =134, DQ14 =136, DQ15 =136
8719 22:53:43.901290
8720 22:53:43.901680
8721 22:53:43.902011
8722 22:53:43.904382 [DramC_TX_OE_Calibration] TA2
8723 22:53:43.907591 Original DQ_B0 (3 6) =30, OEN = 27
8724 22:53:43.910675 Original DQ_B1 (3 6) =30, OEN = 27
8725 22:53:43.914187 24, 0x0, End_B0=24 End_B1=24
8726 22:53:43.914769 25, 0x0, End_B0=25 End_B1=25
8727 22:53:43.917528 26, 0x0, End_B0=26 End_B1=26
8728 22:53:43.921083 27, 0x0, End_B0=27 End_B1=27
8729 22:53:43.924140 28, 0x0, End_B0=28 End_B1=28
8730 22:53:43.927684 29, 0x0, End_B0=29 End_B1=29
8731 22:53:43.928259 30, 0x0, End_B0=30 End_B1=30
8732 22:53:43.931107 31, 0x4141, End_B0=30 End_B1=30
8733 22:53:43.933932 Byte0 end_step=30 best_step=27
8734 22:53:43.937562 Byte1 end_step=30 best_step=27
8735 22:53:43.940798 Byte0 TX OE(2T, 0.5T) = (3, 3)
8736 22:53:43.944088 Byte1 TX OE(2T, 0.5T) = (3, 3)
8737 22:53:43.944647
8738 22:53:43.945013
8739 22:53:43.950670 [DQSOSCAuto] RK0, (LSB)MR18= 0x1826, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8740 22:53:43.954040 CH1 RK0: MR19=303, MR18=1826
8741 22:53:43.960825 CH1_RK0: MR19=0x303, MR18=0x1826, DQSOSC=390, MR23=63, INC=24, DEC=16
8742 22:53:43.961289
8743 22:53:43.964270 ----->DramcWriteLeveling(PI) begin...
8744 22:53:43.964863 ==
8745 22:53:43.966965 Dram Type= 6, Freq= 0, CH_1, rank 1
8746 22:53:43.970587 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8747 22:53:43.971119 ==
8748 22:53:43.973801 Write leveling (Byte 0): 25 => 25
8749 22:53:43.977260 Write leveling (Byte 1): 28 => 28
8750 22:53:43.980749 DramcWriteLeveling(PI) end<-----
8751 22:53:43.981345
8752 22:53:43.981718 ==
8753 22:53:43.984220 Dram Type= 6, Freq= 0, CH_1, rank 1
8754 22:53:43.986917 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8755 22:53:43.987382 ==
8756 22:53:43.990830 [Gating] SW mode calibration
8757 22:53:43.997197 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8758 22:53:44.003970 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8759 22:53:44.007336 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8760 22:53:44.010335 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8761 22:53:44.017508 1 4 8 | B1->B0 | 3030 2323 | 1 0 | (1 1) (0 0)
8762 22:53:44.020364 1 4 12 | B1->B0 | 3434 2f2e | 1 1 | (1 1) (1 1)
8763 22:53:44.023685 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8764 22:53:44.030474 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8765 22:53:44.033620 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8766 22:53:44.036676 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8767 22:53:44.043458 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8768 22:53:44.047354 1 5 4 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 0)
8769 22:53:44.050226 1 5 8 | B1->B0 | 2626 3434 | 0 1 | (1 0) (1 0)
8770 22:53:44.056951 1 5 12 | B1->B0 | 2323 3030 | 0 0 | (1 0) (1 0)
8771 22:53:44.059952 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8772 22:53:44.063301 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8773 22:53:44.070139 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8774 22:53:44.073422 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8775 22:53:44.076969 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8776 22:53:44.083664 1 6 4 | B1->B0 | 2727 2323 | 1 0 | (0 0) (0 0)
8777 22:53:44.086910 1 6 8 | B1->B0 | 4443 2424 | 1 1 | (0 0) (0 0)
8778 22:53:44.089866 1 6 12 | B1->B0 | 4646 4242 | 0 1 | (0 0) (0 0)
8779 22:53:44.096959 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8780 22:53:44.100127 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8781 22:53:44.103728 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8782 22:53:44.110338 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8783 22:53:44.113569 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8784 22:53:44.116827 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8785 22:53:44.123646 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8786 22:53:44.126923 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8787 22:53:44.130161 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8788 22:53:44.137055 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8789 22:53:44.139722 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8790 22:53:44.143095 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8791 22:53:44.149964 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8792 22:53:44.153395 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8793 22:53:44.156651 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8794 22:53:44.160033 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8795 22:53:44.166834 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8796 22:53:44.169882 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8797 22:53:44.173486 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 22:53:44.179593 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 22:53:44.183240 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 22:53:44.186383 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 22:53:44.193371 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8802 22:53:44.196719 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8803 22:53:44.199712 Total UI for P1: 0, mck2ui 16
8804 22:53:44.203172 best dqsien dly found for B1: ( 1, 9, 8)
8805 22:53:44.206270 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8806 22:53:44.209518 Total UI for P1: 0, mck2ui 16
8807 22:53:44.213194 best dqsien dly found for B0: ( 1, 9, 10)
8808 22:53:44.216798 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8809 22:53:44.220053 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8810 22:53:44.220608
8811 22:53:44.226233 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8812 22:53:44.230129 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8813 22:53:44.233077 [Gating] SW calibration Done
8814 22:53:44.233668 ==
8815 22:53:44.236179 Dram Type= 6, Freq= 0, CH_1, rank 1
8816 22:53:44.239639 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8817 22:53:44.240102 ==
8818 22:53:44.240466 RX Vref Scan: 0
8819 22:53:44.240799
8820 22:53:44.242819 RX Vref 0 -> 0, step: 1
8821 22:53:44.243296
8822 22:53:44.246169 RX Delay 0 -> 252, step: 8
8823 22:53:44.249542 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8824 22:53:44.252885 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8825 22:53:44.256175 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8826 22:53:44.263005 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8827 22:53:44.266273 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8828 22:53:44.269502 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8829 22:53:44.273253 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8830 22:53:44.276220 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8831 22:53:44.282890 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8832 22:53:44.286718 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8833 22:53:44.289610 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8834 22:53:44.293093 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8835 22:53:44.296449 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8836 22:53:44.302940 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8837 22:53:44.306338 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8838 22:53:44.309761 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8839 22:53:44.310221 ==
8840 22:53:44.312748 Dram Type= 6, Freq= 0, CH_1, rank 1
8841 22:53:44.315959 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8842 22:53:44.316525 ==
8843 22:53:44.319336 DQS Delay:
8844 22:53:44.319889 DQS0 = 0, DQS1 = 0
8845 22:53:44.322884 DQM Delay:
8846 22:53:44.323438 DQM0 = 136, DQM1 = 132
8847 22:53:44.325926 DQ Delay:
8848 22:53:44.329352 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8849 22:53:44.332791 DQ4 =139, DQ5 =147, DQ6 =143, DQ7 =135
8850 22:53:44.335759 DQ8 =115, DQ9 =119, DQ10 =135, DQ11 =127
8851 22:53:44.339562 DQ12 =143, DQ13 =139, DQ14 =139, DQ15 =143
8852 22:53:44.340021
8853 22:53:44.340378
8854 22:53:44.340711 ==
8855 22:53:44.342399 Dram Type= 6, Freq= 0, CH_1, rank 1
8856 22:53:44.346243 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8857 22:53:44.346814 ==
8858 22:53:44.347181
8859 22:53:44.347518
8860 22:53:44.349428 TX Vref Scan disable
8861 22:53:44.352772 == TX Byte 0 ==
8862 22:53:44.355906 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8863 22:53:44.359476 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8864 22:53:44.362929 == TX Byte 1 ==
8865 22:53:44.365866 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8866 22:53:44.369272 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8867 22:53:44.369770 ==
8868 22:53:44.372614 Dram Type= 6, Freq= 0, CH_1, rank 1
8869 22:53:44.375848 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8870 22:53:44.379254 ==
8871 22:53:44.390528
8872 22:53:44.394062 TX Vref early break, caculate TX vref
8873 22:53:44.397077 TX Vref=16, minBit 12, minWin=22, winSum=385
8874 22:53:44.400488 TX Vref=18, minBit 9, minWin=23, winSum=390
8875 22:53:44.403314 TX Vref=20, minBit 9, minWin=23, winSum=398
8876 22:53:44.406978 TX Vref=22, minBit 9, minWin=23, winSum=407
8877 22:53:44.410556 TX Vref=24, minBit 13, minWin=24, winSum=418
8878 22:53:44.417035 TX Vref=26, minBit 9, minWin=25, winSum=418
8879 22:53:44.420764 TX Vref=28, minBit 8, minWin=25, winSum=420
8880 22:53:44.423504 TX Vref=30, minBit 10, minWin=24, winSum=416
8881 22:53:44.427280 TX Vref=32, minBit 9, minWin=24, winSum=403
8882 22:53:44.430597 TX Vref=34, minBit 9, minWin=23, winSum=397
8883 22:53:44.436766 [TxChooseVref] Worse bit 8, Min win 25, Win sum 420, Final Vref 28
8884 22:53:44.437332
8885 22:53:44.440224 Final TX Range 0 Vref 28
8886 22:53:44.440725
8887 22:53:44.441089 ==
8888 22:53:44.443219 Dram Type= 6, Freq= 0, CH_1, rank 1
8889 22:53:44.446659 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8890 22:53:44.447120 ==
8891 22:53:44.447481
8892 22:53:44.447813
8893 22:53:44.450406 TX Vref Scan disable
8894 22:53:44.456643 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8895 22:53:44.457267 == TX Byte 0 ==
8896 22:53:44.459955 u2DelayCellOfst[0]=16 cells (5 PI)
8897 22:53:44.463223 u2DelayCellOfst[1]=13 cells (4 PI)
8898 22:53:44.466944 u2DelayCellOfst[2]=0 cells (0 PI)
8899 22:53:44.470032 u2DelayCellOfst[3]=6 cells (2 PI)
8900 22:53:44.473226 u2DelayCellOfst[4]=10 cells (3 PI)
8901 22:53:44.476625 u2DelayCellOfst[5]=20 cells (6 PI)
8902 22:53:44.480100 u2DelayCellOfst[6]=20 cells (6 PI)
8903 22:53:44.483323 u2DelayCellOfst[7]=6 cells (2 PI)
8904 22:53:44.486988 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8905 22:53:44.489766 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8906 22:53:44.493104 == TX Byte 1 ==
8907 22:53:44.493693 u2DelayCellOfst[8]=0 cells (0 PI)
8908 22:53:44.496213 u2DelayCellOfst[9]=3 cells (1 PI)
8909 22:53:44.499793 u2DelayCellOfst[10]=10 cells (3 PI)
8910 22:53:44.503098 u2DelayCellOfst[11]=3 cells (1 PI)
8911 22:53:44.506485 u2DelayCellOfst[12]=13 cells (4 PI)
8912 22:53:44.509642 u2DelayCellOfst[13]=20 cells (6 PI)
8913 22:53:44.512902 u2DelayCellOfst[14]=20 cells (6 PI)
8914 22:53:44.516554 u2DelayCellOfst[15]=20 cells (6 PI)
8915 22:53:44.519797 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8916 22:53:44.526133 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8917 22:53:44.526684 DramC Write-DBI on
8918 22:53:44.527050 ==
8919 22:53:44.529651 Dram Type= 6, Freq= 0, CH_1, rank 1
8920 22:53:44.536320 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8921 22:53:44.536884 ==
8922 22:53:44.537339
8923 22:53:44.537701
8924 22:53:44.538025 TX Vref Scan disable
8925 22:53:44.540348 == TX Byte 0 ==
8926 22:53:44.543436 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8927 22:53:44.546595 == TX Byte 1 ==
8928 22:53:44.549869 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8929 22:53:44.553262 DramC Write-DBI off
8930 22:53:44.553862
8931 22:53:44.554226 [DATLAT]
8932 22:53:44.554560 Freq=1600, CH1 RK1
8933 22:53:44.554880
8934 22:53:44.556508 DATLAT Default: 0xf
8935 22:53:44.556963 0, 0xFFFF, sum = 0
8936 22:53:44.559703 1, 0xFFFF, sum = 0
8937 22:53:44.563238 2, 0xFFFF, sum = 0
8938 22:53:44.563702 3, 0xFFFF, sum = 0
8939 22:53:44.566625 4, 0xFFFF, sum = 0
8940 22:53:44.567093 5, 0xFFFF, sum = 0
8941 22:53:44.569785 6, 0xFFFF, sum = 0
8942 22:53:44.570251 7, 0xFFFF, sum = 0
8943 22:53:44.573253 8, 0xFFFF, sum = 0
8944 22:53:44.573759 9, 0xFFFF, sum = 0
8945 22:53:44.576273 10, 0xFFFF, sum = 0
8946 22:53:44.576734 11, 0xFFFF, sum = 0
8947 22:53:44.580173 12, 0xFFFF, sum = 0
8948 22:53:44.580786 13, 0xFFFF, sum = 0
8949 22:53:44.582766 14, 0x0, sum = 1
8950 22:53:44.583230 15, 0x0, sum = 2
8951 22:53:44.586789 16, 0x0, sum = 3
8952 22:53:44.587356 17, 0x0, sum = 4
8953 22:53:44.589601 best_step = 15
8954 22:53:44.590109
8955 22:53:44.590472 ==
8956 22:53:44.592788 Dram Type= 6, Freq= 0, CH_1, rank 1
8957 22:53:44.596545 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8958 22:53:44.597176 ==
8959 22:53:44.599879 RX Vref Scan: 0
8960 22:53:44.600436
8961 22:53:44.600799 RX Vref 0 -> 0, step: 1
8962 22:53:44.601131
8963 22:53:44.602834 RX Delay 19 -> 252, step: 4
8964 22:53:44.606367 iDelay=195, Bit 0, Center 136 (95 ~ 178) 84
8965 22:53:44.613288 iDelay=195, Bit 1, Center 132 (87 ~ 178) 92
8966 22:53:44.616220 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
8967 22:53:44.619335 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8968 22:53:44.623357 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
8969 22:53:44.626271 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8970 22:53:44.629639 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
8971 22:53:44.636468 iDelay=195, Bit 7, Center 132 (87 ~ 178) 92
8972 22:53:44.639721 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
8973 22:53:44.642543 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8974 22:53:44.646044 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
8975 22:53:44.652756 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
8976 22:53:44.655954 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
8977 22:53:44.659135 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8978 22:53:44.662755 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
8979 22:53:44.665821 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
8980 22:53:44.666284 ==
8981 22:53:44.668989 Dram Type= 6, Freq= 0, CH_1, rank 1
8982 22:53:44.676138 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8983 22:53:44.676708 ==
8984 22:53:44.677080 DQS Delay:
8985 22:53:44.678988 DQS0 = 0, DQS1 = 0
8986 22:53:44.679450 DQM Delay:
8987 22:53:44.682602 DQM0 = 134, DQM1 = 129
8988 22:53:44.683068 DQ Delay:
8989 22:53:44.685914 DQ0 =136, DQ1 =132, DQ2 =120, DQ3 =130
8990 22:53:44.689223 DQ4 =134, DQ5 =146, DQ6 =142, DQ7 =132
8991 22:53:44.692934 DQ8 =112, DQ9 =118, DQ10 =130, DQ11 =126
8992 22:53:44.695842 DQ12 =138, DQ13 =136, DQ14 =138, DQ15 =140
8993 22:53:44.696311
8994 22:53:44.696674
8995 22:53:44.697013
8996 22:53:44.699208 [DramC_TX_OE_Calibration] TA2
8997 22:53:44.702368 Original DQ_B0 (3 6) =30, OEN = 27
8998 22:53:44.705458 Original DQ_B1 (3 6) =30, OEN = 27
8999 22:53:44.709034 24, 0x0, End_B0=24 End_B1=24
9000 22:53:44.712051 25, 0x0, End_B0=25 End_B1=25
9001 22:53:44.712530 26, 0x0, End_B0=26 End_B1=26
9002 22:53:44.715181 27, 0x0, End_B0=27 End_B1=27
9003 22:53:44.719179 28, 0x0, End_B0=28 End_B1=28
9004 22:53:44.722403 29, 0x0, End_B0=29 End_B1=29
9005 22:53:44.723042 30, 0x0, End_B0=30 End_B1=30
9006 22:53:44.725345 31, 0x5151, End_B0=30 End_B1=30
9007 22:53:44.728756 Byte0 end_step=30 best_step=27
9008 22:53:44.732096 Byte1 end_step=30 best_step=27
9009 22:53:44.735332 Byte0 TX OE(2T, 0.5T) = (3, 3)
9010 22:53:44.738740 Byte1 TX OE(2T, 0.5T) = (3, 3)
9011 22:53:44.739268
9012 22:53:44.739705
9013 22:53:44.745565 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c07, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 395 ps
9014 22:53:44.749272 CH1 RK1: MR19=303, MR18=1C07
9015 22:53:44.755265 CH1_RK1: MR19=0x303, MR18=0x1C07, DQSOSC=395, MR23=63, INC=23, DEC=15
9016 22:53:44.758527 [RxdqsGatingPostProcess] freq 1600
9017 22:53:44.761667 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9018 22:53:44.765353 best DQS0 dly(2T, 0.5T) = (1, 1)
9019 22:53:44.769188 best DQS1 dly(2T, 0.5T) = (1, 1)
9020 22:53:44.771972 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9021 22:53:44.775672 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9022 22:53:44.779271 best DQS0 dly(2T, 0.5T) = (1, 1)
9023 22:53:44.782227 best DQS1 dly(2T, 0.5T) = (1, 1)
9024 22:53:44.785460 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9025 22:53:44.788882 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9026 22:53:44.791862 Pre-setting of DQS Precalculation
9027 22:53:44.795402 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9028 22:53:44.802112 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9029 22:53:44.808812 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9030 22:53:44.811933
9031 22:53:44.812013
9032 22:53:44.812077 [Calibration Summary] 3200 Mbps
9033 22:53:44.814997 CH 0, Rank 0
9034 22:53:44.815079 SW Impedance : PASS
9035 22:53:44.818189 DUTY Scan : NO K
9036 22:53:44.821921 ZQ Calibration : PASS
9037 22:53:44.822002 Jitter Meter : NO K
9038 22:53:44.824783 CBT Training : PASS
9039 22:53:44.828283 Write leveling : PASS
9040 22:53:44.828364 RX DQS gating : PASS
9041 22:53:44.831777 RX DQ/DQS(RDDQC) : PASS
9042 22:53:44.835021 TX DQ/DQS : PASS
9043 22:53:44.835103 RX DATLAT : PASS
9044 22:53:44.838220 RX DQ/DQS(Engine): PASS
9045 22:53:44.841826 TX OE : PASS
9046 22:53:44.841908 All Pass.
9047 22:53:44.841972
9048 22:53:44.842031 CH 0, Rank 1
9049 22:53:44.844878 SW Impedance : PASS
9050 22:53:44.848154 DUTY Scan : NO K
9051 22:53:44.848236 ZQ Calibration : PASS
9052 22:53:44.851451 Jitter Meter : NO K
9053 22:53:44.854682 CBT Training : PASS
9054 22:53:44.854764 Write leveling : PASS
9055 22:53:44.857948 RX DQS gating : PASS
9056 22:53:44.858029 RX DQ/DQS(RDDQC) : PASS
9057 22:53:44.861909 TX DQ/DQS : PASS
9058 22:53:44.865152 RX DATLAT : PASS
9059 22:53:44.865234 RX DQ/DQS(Engine): PASS
9060 22:53:44.868270 TX OE : PASS
9061 22:53:44.868351 All Pass.
9062 22:53:44.868415
9063 22:53:44.871324 CH 1, Rank 0
9064 22:53:44.871405 SW Impedance : PASS
9065 22:53:44.874968 DUTY Scan : NO K
9066 22:53:44.878382 ZQ Calibration : PASS
9067 22:53:44.878464 Jitter Meter : NO K
9068 22:53:44.881593 CBT Training : PASS
9069 22:53:44.884792 Write leveling : PASS
9070 22:53:44.884877 RX DQS gating : PASS
9071 22:53:44.888220 RX DQ/DQS(RDDQC) : PASS
9072 22:53:44.891307 TX DQ/DQS : PASS
9073 22:53:44.891401 RX DATLAT : PASS
9074 22:53:44.894840 RX DQ/DQS(Engine): PASS
9075 22:53:44.898108 TX OE : PASS
9076 22:53:44.898190 All Pass.
9077 22:53:44.898254
9078 22:53:44.898313 CH 1, Rank 1
9079 22:53:44.901254 SW Impedance : PASS
9080 22:53:44.904732 DUTY Scan : NO K
9081 22:53:44.904815 ZQ Calibration : PASS
9082 22:53:44.908268 Jitter Meter : NO K
9083 22:53:44.908349 CBT Training : PASS
9084 22:53:44.911300 Write leveling : PASS
9085 22:53:44.914763 RX DQS gating : PASS
9086 22:53:44.914845 RX DQ/DQS(RDDQC) : PASS
9087 22:53:44.918395 TX DQ/DQS : PASS
9088 22:53:44.921409 RX DATLAT : PASS
9089 22:53:44.921491 RX DQ/DQS(Engine): PASS
9090 22:53:44.924611 TX OE : PASS
9091 22:53:44.924692 All Pass.
9092 22:53:44.924756
9093 22:53:44.927980 DramC Write-DBI on
9094 22:53:44.931217 PER_BANK_REFRESH: Hybrid Mode
9095 22:53:44.931301 TX_TRACKING: ON
9096 22:53:44.941220 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9097 22:53:44.947718 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9098 22:53:44.954440 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9099 22:53:44.961207 [FAST_K] Save calibration result to emmc
9100 22:53:44.961289 sync common calibartion params.
9101 22:53:44.964347 sync cbt_mode0:1, 1:1
9102 22:53:44.967704 dram_init: ddr_geometry: 2
9103 22:53:44.967796 dram_init: ddr_geometry: 2
9104 22:53:44.971201 dram_init: ddr_geometry: 2
9105 22:53:44.974356 0:dram_rank_size:100000000
9106 22:53:44.977657 1:dram_rank_size:100000000
9107 22:53:44.981241 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9108 22:53:44.984254 DFS_SHUFFLE_HW_MODE: ON
9109 22:53:44.987545 dramc_set_vcore_voltage set vcore to 725000
9110 22:53:44.990944 Read voltage for 1600, 0
9111 22:53:44.991026 Vio18 = 0
9112 22:53:44.991091 Vcore = 725000
9113 22:53:44.994464 Vdram = 0
9114 22:53:44.994546 Vddq = 0
9115 22:53:44.994611 Vmddr = 0
9116 22:53:44.997801 switch to 3200 Mbps bootup
9117 22:53:45.001191 [DramcRunTimeConfig]
9118 22:53:45.001273 PHYPLL
9119 22:53:45.001348 DPM_CONTROL_AFTERK: ON
9120 22:53:45.004351 PER_BANK_REFRESH: ON
9121 22:53:45.007795 REFRESH_OVERHEAD_REDUCTION: ON
9122 22:53:45.007877 CMD_PICG_NEW_MODE: OFF
9123 22:53:45.011126 XRTWTW_NEW_MODE: ON
9124 22:53:45.014347 XRTRTR_NEW_MODE: ON
9125 22:53:45.014429 TX_TRACKING: ON
9126 22:53:45.017581 RDSEL_TRACKING: OFF
9127 22:53:45.017664 DQS Precalculation for DVFS: ON
9128 22:53:45.020885 RX_TRACKING: OFF
9129 22:53:45.020967 HW_GATING DBG: ON
9130 22:53:45.024565 ZQCS_ENABLE_LP4: ON
9131 22:53:45.024648 RX_PICG_NEW_MODE: ON
9132 22:53:45.027884 TX_PICG_NEW_MODE: ON
9133 22:53:45.031172 ENABLE_RX_DCM_DPHY: ON
9134 22:53:45.034422 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9135 22:53:45.034507 DUMMY_READ_FOR_TRACKING: OFF
9136 22:53:45.037748 !!! SPM_CONTROL_AFTERK: OFF
9137 22:53:45.041190 !!! SPM could not control APHY
9138 22:53:45.044413 IMPEDANCE_TRACKING: ON
9139 22:53:45.044495 TEMP_SENSOR: ON
9140 22:53:45.047645 HW_SAVE_FOR_SR: OFF
9141 22:53:45.047727 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9142 22:53:45.054469 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9143 22:53:45.054551 Read ODT Tracking: ON
9144 22:53:45.057658 Refresh Rate DeBounce: ON
9145 22:53:45.057740 DFS_NO_QUEUE_FLUSH: ON
9146 22:53:45.061081 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9147 22:53:45.064686 ENABLE_DFS_RUNTIME_MRW: OFF
9148 22:53:45.067689 DDR_RESERVE_NEW_MODE: ON
9149 22:53:45.067771 MR_CBT_SWITCH_FREQ: ON
9150 22:53:45.070982 =========================
9151 22:53:45.090419 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9152 22:53:45.093569 dram_init: ddr_geometry: 2
9153 22:53:45.111919 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9154 22:53:45.115076 dram_init: dram init end (result: 0)
9155 22:53:45.121778 DRAM-K: Full calibration passed in 24513 msecs
9156 22:53:45.125116 MRC: failed to locate region type 0.
9157 22:53:45.125216 DRAM rank0 size:0x100000000,
9158 22:53:45.128553 DRAM rank1 size=0x100000000
9159 22:53:45.138100 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9160 22:53:45.144986 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9161 22:53:45.151591 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9162 22:53:45.158101 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9163 22:53:45.161415 DRAM rank0 size:0x100000000,
9164 22:53:45.164576 DRAM rank1 size=0x100000000
9165 22:53:45.164664 CBMEM:
9166 22:53:45.168589 IMD: root @ 0xfffff000 254 entries.
9167 22:53:45.171688 IMD: root @ 0xffffec00 62 entries.
9168 22:53:45.174994 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9169 22:53:45.178135 WARNING: RO_VPD is uninitialized or empty.
9170 22:53:45.184794 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9171 22:53:45.192048 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9172 22:53:45.204421 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9173 22:53:45.215865 BS: romstage times (exec / console): total (unknown) / 24012 ms
9174 22:53:45.215971
9175 22:53:45.216103
9176 22:53:45.225911 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9177 22:53:45.229174 ARM64: Exception handlers installed.
9178 22:53:45.232376 ARM64: Testing exception
9179 22:53:45.235712 ARM64: Done test exception
9180 22:53:45.235814 Enumerating buses...
9181 22:53:45.239135 Show all devs... Before device enumeration.
9182 22:53:45.242436 Root Device: enabled 1
9183 22:53:45.245996 CPU_CLUSTER: 0: enabled 1
9184 22:53:45.246078 CPU: 00: enabled 1
9185 22:53:45.249217 Compare with tree...
9186 22:53:45.249325 Root Device: enabled 1
9187 22:53:45.252337 CPU_CLUSTER: 0: enabled 1
9188 22:53:45.256107 CPU: 00: enabled 1
9189 22:53:45.256176 Root Device scanning...
9190 22:53:45.259031 scan_static_bus for Root Device
9191 22:53:45.262701 CPU_CLUSTER: 0 enabled
9192 22:53:45.266176 scan_static_bus for Root Device done
9193 22:53:45.269426 scan_bus: bus Root Device finished in 8 msecs
9194 22:53:45.269496 done
9195 22:53:45.276201 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9196 22:53:45.279268 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9197 22:53:45.285686 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9198 22:53:45.289207 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9199 22:53:45.292529 Allocating resources...
9200 22:53:45.292635 Reading resources...
9201 22:53:45.299270 Root Device read_resources bus 0 link: 0
9202 22:53:45.299344 DRAM rank0 size:0x100000000,
9203 22:53:45.302550 DRAM rank1 size=0x100000000
9204 22:53:45.305612 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9205 22:53:45.309213 CPU: 00 missing read_resources
9206 22:53:45.312277 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9207 22:53:45.318965 Root Device read_resources bus 0 link: 0 done
9208 22:53:45.319039 Done reading resources.
9209 22:53:45.325669 Show resources in subtree (Root Device)...After reading.
9210 22:53:45.328893 Root Device child on link 0 CPU_CLUSTER: 0
9211 22:53:45.332204 CPU_CLUSTER: 0 child on link 0 CPU: 00
9212 22:53:45.342134 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9213 22:53:45.342210 CPU: 00
9214 22:53:45.345772 Root Device assign_resources, bus 0 link: 0
9215 22:53:45.348869 CPU_CLUSTER: 0 missing set_resources
9216 22:53:45.352105 Root Device assign_resources, bus 0 link: 0 done
9217 22:53:45.355606 Done setting resources.
9218 22:53:45.362062 Show resources in subtree (Root Device)...After assigning values.
9219 22:53:45.365493 Root Device child on link 0 CPU_CLUSTER: 0
9220 22:53:45.368818 CPU_CLUSTER: 0 child on link 0 CPU: 00
9221 22:53:45.378889 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9222 22:53:45.378993 CPU: 00
9223 22:53:45.382142 Done allocating resources.
9224 22:53:45.385264 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9225 22:53:45.389011 Enabling resources...
9226 22:53:45.389082 done.
9227 22:53:45.395149 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9228 22:53:45.395227 Initializing devices...
9229 22:53:45.398546 Root Device init
9230 22:53:45.398643 init hardware done!
9231 22:53:45.402038 0x00000018: ctrlr->caps
9232 22:53:45.405213 52.000 MHz: ctrlr->f_max
9233 22:53:45.405346 0.400 MHz: ctrlr->f_min
9234 22:53:45.408670 0x40ff8080: ctrlr->voltages
9235 22:53:45.408769 sclk: 390625
9236 22:53:45.411742 Bus Width = 1
9237 22:53:45.411841 sclk: 390625
9238 22:53:45.415235 Bus Width = 1
9239 22:53:45.415308 Early init status = 3
9240 22:53:45.421627 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9241 22:53:45.424919 in-header: 03 fc 00 00 01 00 00 00
9242 22:53:45.424990 in-data: 00
9243 22:53:45.431835 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9244 22:53:45.435240 in-header: 03 fd 00 00 00 00 00 00
9245 22:53:45.438280 in-data:
9246 22:53:45.441436 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9247 22:53:45.444769 in-header: 03 fc 00 00 01 00 00 00
9248 22:53:45.448035 in-data: 00
9249 22:53:45.451700 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9250 22:53:45.456914 in-header: 03 fd 00 00 00 00 00 00
9251 22:53:45.460372 in-data:
9252 22:53:45.463331 [SSUSB] Setting up USB HOST controller...
9253 22:53:45.466823 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9254 22:53:45.470227 [SSUSB] phy power-on done.
9255 22:53:45.473446 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9256 22:53:45.480098 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9257 22:53:45.483621 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9258 22:53:45.490227 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9259 22:53:45.496994 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9260 22:53:45.503265 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9261 22:53:45.510230 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9262 22:53:45.516663 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9263 22:53:45.520080 SPM: binary array size = 0x9dc
9264 22:53:45.523661 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9265 22:53:45.529911 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9266 22:53:45.536842 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9267 22:53:45.540051 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9268 22:53:45.543668 configure_display: Starting display init
9269 22:53:45.580189 anx7625_power_on_init: Init interface.
9270 22:53:45.583372 anx7625_disable_pd_protocol: Disabled PD feature.
9271 22:53:45.586672 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9272 22:53:45.614752 anx7625_start_dp_work: Secure OCM version=00
9273 22:53:45.617870 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9274 22:53:45.632821 sp_tx_get_edid_block: EDID Block = 1
9275 22:53:45.735174 Extracted contents:
9276 22:53:45.738750 header: 00 ff ff ff ff ff ff 00
9277 22:53:45.741998 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9278 22:53:45.745352 version: 01 04
9279 22:53:45.748736 basic params: 95 1f 11 78 0a
9280 22:53:45.751682 chroma info: 76 90 94 55 54 90 27 21 50 54
9281 22:53:45.755030 established: 00 00 00
9282 22:53:45.761686 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9283 22:53:45.765158 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9284 22:53:45.771803 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9285 22:53:45.778679 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9286 22:53:45.784920 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9287 22:53:45.788215 extensions: 00
9288 22:53:45.788317 checksum: fb
9289 22:53:45.788382
9290 22:53:45.791387 Manufacturer: IVO Model 57d Serial Number 0
9291 22:53:45.794867 Made week 0 of 2020
9292 22:53:45.794949 EDID version: 1.4
9293 22:53:45.798097 Digital display
9294 22:53:45.801540 6 bits per primary color channel
9295 22:53:45.801623 DisplayPort interface
9296 22:53:45.804993 Maximum image size: 31 cm x 17 cm
9297 22:53:45.808223 Gamma: 220%
9298 22:53:45.808309 Check DPMS levels
9299 22:53:45.811911 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9300 22:53:45.815000 First detailed timing is preferred timing
9301 22:53:45.818079 Established timings supported:
9302 22:53:45.821584 Standard timings supported:
9303 22:53:45.824896 Detailed timings
9304 22:53:45.827940 Hex of detail: 383680a07038204018303c0035ae10000019
9305 22:53:45.831603 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9306 22:53:45.838170 0780 0798 07c8 0820 hborder 0
9307 22:53:45.841348 0438 043b 0447 0458 vborder 0
9308 22:53:45.845131 -hsync -vsync
9309 22:53:45.845211 Did detailed timing
9310 22:53:45.848386 Hex of detail: 000000000000000000000000000000000000
9311 22:53:45.851823 Manufacturer-specified data, tag 0
9312 22:53:45.858135 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9313 22:53:45.858216 ASCII string: InfoVision
9314 22:53:45.864845 Hex of detail: 000000fe00523134304e574635205248200a
9315 22:53:45.867968 ASCII string: R140NWF5 RH
9316 22:53:45.868048 Checksum
9317 22:53:45.868111 Checksum: 0xfb (valid)
9318 22:53:45.874973 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9319 22:53:45.878149 DSI data_rate: 832800000 bps
9320 22:53:45.881320 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9321 22:53:45.887860 anx7625_parse_edid: pixelclock(138800).
9322 22:53:45.891360 hactive(1920), hsync(48), hfp(24), hbp(88)
9323 22:53:45.894824 vactive(1080), vsync(12), vfp(3), vbp(17)
9324 22:53:45.898040 anx7625_dsi_config: config dsi.
9325 22:53:45.904479 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9326 22:53:45.917308 anx7625_dsi_config: success to config DSI
9327 22:53:45.920679 anx7625_dp_start: MIPI phy setup OK.
9328 22:53:45.923908 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9329 22:53:45.927271 mtk_ddp_mode_set invalid vrefresh 60
9330 22:53:45.930718 main_disp_path_setup
9331 22:53:45.930797 ovl_layer_smi_id_en
9332 22:53:45.934170 ovl_layer_smi_id_en
9333 22:53:45.934249 ccorr_config
9334 22:53:45.934311 aal_config
9335 22:53:45.937332 gamma_config
9336 22:53:45.937411 postmask_config
9337 22:53:45.940385 dither_config
9338 22:53:45.943961 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9339 22:53:45.950581 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9340 22:53:45.954235 Root Device init finished in 552 msecs
9341 22:53:45.954315 CPU_CLUSTER: 0 init
9342 22:53:45.964186 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9343 22:53:45.967291 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9344 22:53:45.970741 APU_MBOX 0x190000b0 = 0x10001
9345 22:53:45.973874 APU_MBOX 0x190001b0 = 0x10001
9346 22:53:45.977229 APU_MBOX 0x190005b0 = 0x10001
9347 22:53:45.980566 APU_MBOX 0x190006b0 = 0x10001
9348 22:53:45.983756 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9349 22:53:45.996472 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9350 22:53:46.008710 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9351 22:53:46.015722 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9352 22:53:46.027015 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9353 22:53:46.036242 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9354 22:53:46.039387 CPU_CLUSTER: 0 init finished in 81 msecs
9355 22:53:46.042566 Devices initialized
9356 22:53:46.046145 Show all devs... After init.
9357 22:53:46.046225 Root Device: enabled 1
9358 22:53:46.049399 CPU_CLUSTER: 0: enabled 1
9359 22:53:46.052704 CPU: 00: enabled 1
9360 22:53:46.055769 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9361 22:53:46.059171 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9362 22:53:46.062414 ELOG: NV offset 0x57f000 size 0x1000
9363 22:53:46.068938 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9364 22:53:46.075696 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9365 22:53:46.079046 ELOG: Event(17) added with size 13 at 2024-05-07 22:52:34 UTC
9366 22:53:46.082579 out: cmd=0x121: 03 db 21 01 00 00 00 00
9367 22:53:46.086456 in-header: 03 65 00 00 2c 00 00 00
9368 22:53:46.099845 in-data: da 70 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9369 22:53:46.106114 ELOG: Event(A1) added with size 10 at 2024-05-07 22:52:34 UTC
9370 22:53:46.112816 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9371 22:53:46.119420 ELOG: Event(A0) added with size 9 at 2024-05-07 22:52:34 UTC
9372 22:53:46.122887 elog_add_boot_reason: Logged dev mode boot
9373 22:53:46.126231 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9374 22:53:46.129764 Finalize devices...
9375 22:53:46.129874 Devices finalized
9376 22:53:46.136151 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9377 22:53:46.139642 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9378 22:53:46.142857 in-header: 03 07 00 00 08 00 00 00
9379 22:53:46.145979 in-data: aa e4 47 04 13 02 00 00
9380 22:53:46.149483 Chrome EC: UHEPI supported
9381 22:53:46.155804 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9382 22:53:46.159138 in-header: 03 a9 00 00 08 00 00 00
9383 22:53:46.162659 in-data: 84 60 60 08 00 00 00 00
9384 22:53:46.165711 ELOG: Event(91) added with size 10 at 2024-05-07 22:52:34 UTC
9385 22:53:46.172660 Chrome EC: clear events_b mask to 0x0000000020004000
9386 22:53:46.179399 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9387 22:53:46.183119 in-header: 03 fd 00 00 00 00 00 00
9388 22:53:46.183202 in-data:
9389 22:53:46.189552 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9390 22:53:46.193191 Writing coreboot table at 0xffe64000
9391 22:53:46.196377 0. 000000000010a000-0000000000113fff: RAMSTAGE
9392 22:53:46.199872 1. 0000000040000000-00000000400fffff: RAM
9393 22:53:46.203197 2. 0000000040100000-000000004032afff: RAMSTAGE
9394 22:53:46.206455 3. 000000004032b000-00000000545fffff: RAM
9395 22:53:46.212893 4. 0000000054600000-000000005465ffff: BL31
9396 22:53:46.215993 5. 0000000054660000-00000000ffe63fff: RAM
9397 22:53:46.219214 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9398 22:53:46.226335 7. 0000000100000000-000000023fffffff: RAM
9399 22:53:46.226405 Passing 5 GPIOs to payload:
9400 22:53:46.232603 NAME | PORT | POLARITY | VALUE
9401 22:53:46.236063 EC in RW | 0x000000aa | low | undefined
9402 22:53:46.239241 EC interrupt | 0x00000005 | low | undefined
9403 22:53:46.246142 TPM interrupt | 0x000000ab | high | undefined
9404 22:53:46.249152 SD card detect | 0x00000011 | high | undefined
9405 22:53:46.256015 speaker enable | 0x00000093 | high | undefined
9406 22:53:46.259016 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9407 22:53:46.262270 in-header: 03 f9 00 00 02 00 00 00
9408 22:53:46.262337 in-data: 02 00
9409 22:53:46.266013 ADC[4]: Raw value=900663 ID=7
9410 22:53:46.269008 ADC[3]: Raw value=212810 ID=1
9411 22:53:46.269085 RAM Code: 0x71
9412 22:53:46.272410 ADC[6]: Raw value=74502 ID=0
9413 22:53:46.275855 ADC[5]: Raw value=212441 ID=1
9414 22:53:46.275921 SKU Code: 0x1
9415 22:53:46.282463 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a882
9416 22:53:46.285847 coreboot table: 964 bytes.
9417 22:53:46.288912 IMD ROOT 0. 0xfffff000 0x00001000
9418 22:53:46.292561 IMD SMALL 1. 0xffffe000 0x00001000
9419 22:53:46.295687 RO MCACHE 2. 0xffffc000 0x00001104
9420 22:53:46.298964 CONSOLE 3. 0xfff7c000 0x00080000
9421 22:53:46.302746 FMAP 4. 0xfff7b000 0x00000452
9422 22:53:46.305600 TIME STAMP 5. 0xfff7a000 0x00000910
9423 22:53:46.309161 VBOOT WORK 6. 0xfff66000 0x00014000
9424 22:53:46.312203 RAMOOPS 7. 0xffe66000 0x00100000
9425 22:53:46.315720 COREBOOT 8. 0xffe64000 0x00002000
9426 22:53:46.315794 IMD small region:
9427 22:53:46.319069 IMD ROOT 0. 0xffffec00 0x00000400
9428 22:53:46.322442 VPD 1. 0xffffeb80 0x0000006c
9429 22:53:46.325739 MMC STATUS 2. 0xffffeb60 0x00000004
9430 22:53:46.332314 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9431 22:53:46.338679 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9432 22:53:46.377948 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9433 22:53:46.381268 Checking segment from ROM address 0x40100000
9434 22:53:46.384834 Checking segment from ROM address 0x4010001c
9435 22:53:46.391536 Loading segment from ROM address 0x40100000
9436 22:53:46.391619 code (compression=0)
9437 22:53:46.401180 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9438 22:53:46.407885 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9439 22:53:46.407970 it's not compressed!
9440 22:53:46.414410 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9441 22:53:46.421042 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9442 22:53:46.438485 Loading segment from ROM address 0x4010001c
9443 22:53:46.438591 Entry Point 0x80000000
9444 22:53:46.441682 Loaded segments
9445 22:53:46.445002 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9446 22:53:46.451845 Jumping to boot code at 0x80000000(0xffe64000)
9447 22:53:46.458400 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9448 22:53:46.464911 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9449 22:53:46.472827 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9450 22:53:46.476347 Checking segment from ROM address 0x40100000
9451 22:53:46.479623 Checking segment from ROM address 0x4010001c
9452 22:53:46.486422 Loading segment from ROM address 0x40100000
9453 22:53:46.486506 code (compression=1)
9454 22:53:46.492743 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9455 22:53:46.502754 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9456 22:53:46.502837 using LZMA
9457 22:53:46.511020 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9458 22:53:46.517918 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9459 22:53:46.521478 Loading segment from ROM address 0x4010001c
9460 22:53:46.521561 Entry Point 0x54601000
9461 22:53:46.524419 Loaded segments
9462 22:53:46.527821 NOTICE: MT8192 bl31_setup
9463 22:53:46.534867 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9464 22:53:46.538213 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9465 22:53:46.541207 WARNING: region 0:
9466 22:53:46.544925 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9467 22:53:46.545008 WARNING: region 1:
9468 22:53:46.551496 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9469 22:53:46.554893 WARNING: region 2:
9470 22:53:46.558126 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9471 22:53:46.561276 WARNING: region 3:
9472 22:53:46.564506 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9473 22:53:46.567812 WARNING: region 4:
9474 22:53:46.574429 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9475 22:53:46.574512 WARNING: region 5:
9476 22:53:46.578330 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9477 22:53:46.581210 WARNING: region 6:
9478 22:53:46.584990 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9479 22:53:46.587828 WARNING: region 7:
9480 22:53:46.591532 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9481 22:53:46.598041 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9482 22:53:46.601258 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9483 22:53:46.604494 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9484 22:53:46.611130 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9485 22:53:46.614623 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9486 22:53:46.618071 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9487 22:53:46.624594 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9488 22:53:46.627792 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9489 22:53:46.634226 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9490 22:53:46.637775 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9491 22:53:46.640873 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9492 22:53:46.647848 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9493 22:53:46.650938 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9494 22:53:46.654313 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9495 22:53:46.660825 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9496 22:53:46.664197 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9497 22:53:46.670842 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9498 22:53:46.674077 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9499 22:53:46.677709 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9500 22:53:46.684095 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9501 22:53:46.687652 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9502 22:53:46.690890 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9503 22:53:46.697666 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9504 22:53:46.701179 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9505 22:53:46.707659 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9506 22:53:46.710876 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9507 22:53:46.714277 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9508 22:53:46.721275 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9509 22:53:46.724250 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9510 22:53:46.731125 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9511 22:53:46.734398 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9512 22:53:46.737517 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9513 22:53:46.744456 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9514 22:53:46.747949 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9515 22:53:46.751000 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9516 22:53:46.754806 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9517 22:53:46.761035 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9518 22:53:46.764373 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9519 22:53:46.768036 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9520 22:53:46.771400 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9521 22:53:46.778210 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9522 22:53:46.781275 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9523 22:53:46.784507 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9524 22:53:46.787770 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9525 22:53:46.794569 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9526 22:53:46.797835 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9527 22:53:46.800924 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9528 22:53:46.804480 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9529 22:53:46.811006 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9530 22:53:46.814387 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9531 22:53:46.821186 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9532 22:53:46.824640 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9533 22:53:46.831013 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9534 22:53:46.834507 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9535 22:53:46.837720 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9536 22:53:46.844606 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9537 22:53:46.847825 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9538 22:53:46.854230 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9539 22:53:46.857759 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9540 22:53:46.864214 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9541 22:53:46.867684 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9542 22:53:46.870698 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9543 22:53:46.877579 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9544 22:53:46.880672 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9545 22:53:46.887407 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9546 22:53:46.890598 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9547 22:53:46.897612 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9548 22:53:46.900774 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9549 22:53:46.907692 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9550 22:53:46.911130 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9551 22:53:46.914115 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9552 22:53:46.920773 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9553 22:53:46.924022 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9554 22:53:46.930801 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9555 22:53:46.933976 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9556 22:53:46.940743 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9557 22:53:46.944032 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9558 22:53:46.947392 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9559 22:53:46.954119 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9560 22:53:46.957676 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9561 22:53:46.964011 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9562 22:53:46.967022 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9563 22:53:46.974013 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9564 22:53:46.977225 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9565 22:53:46.980662 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9566 22:53:46.987493 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9567 22:53:46.990588 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9568 22:53:46.997240 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9569 22:53:47.000525 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9570 22:53:47.007387 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9571 22:53:47.010611 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9572 22:53:47.014120 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9573 22:53:47.020457 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9574 22:53:47.023852 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9575 22:53:47.030400 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9576 22:53:47.033898 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9577 22:53:47.040630 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9578 22:53:47.043943 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9579 22:53:47.047084 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9580 22:53:47.050179 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9581 22:53:47.057034 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9582 22:53:47.060196 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9583 22:53:47.063493 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9584 22:53:47.070462 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9585 22:53:47.073630 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9586 22:53:47.077197 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9587 22:53:47.083867 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9588 22:53:47.086905 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9589 22:53:47.093653 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9590 22:53:47.096854 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9591 22:53:47.100315 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9592 22:53:47.106935 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9593 22:53:47.110497 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9594 22:53:47.116890 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9595 22:53:47.120653 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9596 22:53:47.123900 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9597 22:53:47.130260 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9598 22:53:47.134034 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9599 22:53:47.137111 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9600 22:53:47.143719 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9601 22:53:47.146914 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9602 22:53:47.150591 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9603 22:53:47.153819 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9604 22:53:47.160694 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9605 22:53:47.164002 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9606 22:53:47.166934 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9607 22:53:47.173684 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9608 22:53:47.177183 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9609 22:53:47.183632 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9610 22:53:47.187233 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9611 22:53:47.190444 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9612 22:53:47.197283 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9613 22:53:47.200973 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9614 22:53:47.204020 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9615 22:53:47.210264 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9616 22:53:47.213826 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9617 22:53:47.220703 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9618 22:53:47.223952 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9619 22:53:47.226805 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9620 22:53:47.234037 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9621 22:53:47.237392 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9622 22:53:47.243877 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9623 22:53:47.246959 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9624 22:53:47.250179 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9625 22:53:47.256757 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9626 22:53:47.260092 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9627 22:53:47.266944 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9628 22:53:47.270072 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9629 22:53:47.273460 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9630 22:53:47.280197 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9631 22:53:47.283102 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9632 22:53:47.286627 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9633 22:53:47.293366 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9634 22:53:47.296919 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9635 22:53:47.303450 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9636 22:53:47.306750 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9637 22:53:47.310105 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9638 22:53:47.316775 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9639 22:53:47.320186 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9640 22:53:47.326673 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9641 22:53:47.330066 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9642 22:53:47.333622 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9643 22:53:47.339961 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9644 22:53:47.343333 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9645 22:53:47.349579 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9646 22:53:47.352969 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9647 22:53:47.356572 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9648 22:53:47.362791 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9649 22:53:47.366818 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9650 22:53:47.373273 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9651 22:53:47.376544 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9652 22:53:47.379546 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9653 22:53:47.386483 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9654 22:53:47.389567 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9655 22:53:47.396189 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9656 22:53:47.399486 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9657 22:53:47.402784 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9658 22:53:47.409513 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9659 22:53:47.412783 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9660 22:53:47.415969 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9661 22:53:47.422909 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9662 22:53:47.425801 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9663 22:53:47.432590 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9664 22:53:47.435948 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9665 22:53:47.439215 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9666 22:53:47.445909 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9667 22:53:47.449110 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9668 22:53:47.455618 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9669 22:53:47.459090 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9670 22:53:47.462440 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9671 22:53:47.469077 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9672 22:53:47.472155 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9673 22:53:47.479025 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9674 22:53:47.482292 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9675 22:53:47.488783 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9676 22:53:47.492254 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9677 22:53:47.495625 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9678 22:53:47.502608 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9679 22:53:47.505577 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9680 22:53:47.512226 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9681 22:53:47.515581 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9682 22:53:47.519300 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9683 22:53:47.525757 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9684 22:53:47.529083 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9685 22:53:47.535842 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9686 22:53:47.538709 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9687 22:53:47.545825 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9688 22:53:47.548957 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9689 22:53:47.552130 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9690 22:53:47.559036 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9691 22:53:47.562762 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9692 22:53:47.569225 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9693 22:53:47.572179 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9694 22:53:47.575976 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9695 22:53:47.582371 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9696 22:53:47.585452 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9697 22:53:47.592122 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9698 22:53:47.595419 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9699 22:53:47.599083 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9700 22:53:47.605388 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9701 22:53:47.609158 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9702 22:53:47.615805 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9703 22:53:47.619125 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9704 22:53:47.622412 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9705 22:53:47.628624 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9706 22:53:47.632357 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9707 22:53:47.638879 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9708 22:53:47.642374 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9709 22:53:47.648770 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9710 22:53:47.652016 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9711 22:53:47.655410 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9712 22:53:47.658672 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9713 22:53:47.662365 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9714 22:53:47.668645 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9715 22:53:47.672087 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9716 22:53:47.675450 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9717 22:53:47.682138 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9718 22:53:47.685235 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9719 22:53:47.688761 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9720 22:53:47.695372 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9721 22:53:47.698564 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9722 22:53:47.705178 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9723 22:53:47.708524 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9724 22:53:47.711716 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9725 22:53:47.718730 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9726 22:53:47.722092 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9727 22:53:47.725414 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9728 22:53:47.731690 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9729 22:53:47.735338 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9730 22:53:47.738915 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9731 22:53:47.745316 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9732 22:53:47.748583 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9733 22:53:47.755192 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9734 22:53:47.758518 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9735 22:53:47.761860 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9736 22:53:47.768832 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9737 22:53:47.771690 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9738 22:53:47.775411 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9739 22:53:47.781806 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9740 22:53:47.785039 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9741 22:53:47.791675 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9742 22:53:47.795042 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9743 22:53:47.798215 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9744 22:53:47.804972 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9745 22:53:47.808305 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9746 22:53:47.811569 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9747 22:53:47.818158 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9748 22:53:47.821843 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9749 22:53:47.825014 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9750 22:53:47.831567 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9751 22:53:47.834712 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9752 22:53:47.838122 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9753 22:53:47.841501 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9754 22:53:47.845234 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9755 22:53:47.851618 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9756 22:53:47.855196 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9757 22:53:47.858343 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9758 22:53:47.861545 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9759 22:53:47.868351 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9760 22:53:47.871585 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9761 22:53:47.874858 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9762 22:53:47.881379 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9763 22:53:47.885263 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9764 22:53:47.888242 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9765 22:53:47.894978 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9766 22:53:47.897955 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9767 22:53:47.904869 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9768 22:53:47.907840 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9769 22:53:47.914625 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9770 22:53:47.917696 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9771 22:53:47.921143 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9772 22:53:47.927816 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9773 22:53:47.931012 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9774 22:53:47.938031 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9775 22:53:47.941030 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9776 22:53:47.944273 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9777 22:53:47.950732 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9778 22:53:47.954227 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9779 22:53:47.960804 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9780 22:53:47.964306 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9781 22:53:47.967801 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9782 22:53:47.974326 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9783 22:53:47.977287 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9784 22:53:47.984107 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9785 22:53:47.987258 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9786 22:53:47.990716 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9787 22:53:47.997587 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9788 22:53:48.000713 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9789 22:53:48.007328 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9790 22:53:48.010316 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9791 22:53:48.017121 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9792 22:53:48.020607 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9793 22:53:48.023840 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9794 22:53:48.030364 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9795 22:53:48.033664 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9796 22:53:48.040822 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9797 22:53:48.043667 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9798 22:53:48.047329 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9799 22:53:48.053907 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9800 22:53:48.057038 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9801 22:53:48.063893 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9802 22:53:48.067282 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9803 22:53:48.070291 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9804 22:53:48.076823 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9805 22:53:48.080188 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9806 22:53:48.086812 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9807 22:53:48.089965 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9808 22:53:48.096566 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9809 22:53:48.099974 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9810 22:53:48.103478 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9811 22:53:48.110063 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9812 22:53:48.113326 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9813 22:53:48.119843 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9814 22:53:48.123409 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9815 22:53:48.126472 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9816 22:53:48.133221 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9817 22:53:48.136414 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9818 22:53:48.143279 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9819 22:53:48.146449 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9820 22:53:48.149743 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9821 22:53:48.156522 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9822 22:53:48.159839 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9823 22:53:48.166687 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9824 22:53:48.169701 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9825 22:53:48.176253 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9826 22:53:48.179723 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9827 22:53:48.183137 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9828 22:53:48.189759 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9829 22:53:48.192923 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9830 22:53:48.199975 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9831 22:53:48.203152 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9832 22:53:48.206397 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9833 22:53:48.212776 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9834 22:53:48.216113 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9835 22:53:48.222846 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9836 22:53:48.226398 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9837 22:53:48.229343 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9838 22:53:48.235964 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9839 22:53:48.239479 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9840 22:53:48.246050 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9841 22:53:48.249929 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9842 22:53:48.255919 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9843 22:53:48.259656 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9844 22:53:48.262871 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9845 22:53:48.269573 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9846 22:53:48.272813 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9847 22:53:48.279574 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9848 22:53:48.282673 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9849 22:53:48.289149 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9850 22:53:48.292814 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9851 22:53:48.296312 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9852 22:53:48.302704 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9853 22:53:48.306112 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9854 22:53:48.312723 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9855 22:53:48.316131 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9856 22:53:48.322731 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9857 22:53:48.325826 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9858 22:53:48.329117 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9859 22:53:48.335744 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9860 22:53:48.339107 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9861 22:53:48.345762 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9862 22:53:48.348973 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9863 22:53:48.355731 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9864 22:53:48.359083 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9865 22:53:48.365644 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9866 22:53:48.369102 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9867 22:53:48.372370 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9868 22:53:48.378857 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9869 22:53:48.382241 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9870 22:53:48.388949 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9871 22:53:48.392508 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9872 22:53:48.399023 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9873 22:53:48.402067 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9874 22:53:48.405588 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9875 22:53:48.412665 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9876 22:53:48.415443 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9877 22:53:48.422160 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9878 22:53:48.425369 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9879 22:53:48.432439 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9880 22:53:48.435533 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9881 22:53:48.442103 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9882 22:53:48.445497 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9883 22:53:48.448856 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9884 22:53:48.455752 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9885 22:53:48.458593 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9886 22:53:48.465236 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9887 22:53:48.468863 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9888 22:53:48.475444 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9889 22:53:48.478514 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9890 22:53:48.485076 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9891 22:53:48.488411 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9892 22:53:48.495109 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9893 22:53:48.498709 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9894 22:53:48.501752 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9895 22:53:48.508497 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9896 22:53:48.511748 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9897 22:53:48.518577 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9898 22:53:48.521811 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9899 22:53:48.528800 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9900 22:53:48.532087 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9901 22:53:48.538519 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9902 22:53:48.541755 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9903 22:53:48.548342 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9904 22:53:48.551637 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9905 22:53:48.558692 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9906 22:53:48.561766 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9907 22:53:48.568617 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9908 22:53:48.572117 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9909 22:53:48.578393 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9910 22:53:48.581845 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9911 22:53:48.588672 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9912 22:53:48.591988 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9913 22:53:48.598469 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9914 22:53:48.602158 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9915 22:53:48.605285 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9916 22:53:48.608786 INFO: [APUAPC] vio 0
9917 22:53:48.615279 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9918 22:53:48.618462 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9919 22:53:48.622104 INFO: [APUAPC] D0_APC_0: 0x400510
9920 22:53:48.625141 INFO: [APUAPC] D0_APC_1: 0x0
9921 22:53:48.628698 INFO: [APUAPC] D0_APC_2: 0x1540
9922 22:53:48.631689 INFO: [APUAPC] D0_APC_3: 0x0
9923 22:53:48.635223 INFO: [APUAPC] D1_APC_0: 0xffffffff
9924 22:53:48.638965 INFO: [APUAPC] D1_APC_1: 0xffffffff
9925 22:53:48.642102 INFO: [APUAPC] D1_APC_2: 0x3fffff
9926 22:53:48.642184 INFO: [APUAPC] D1_APC_3: 0x0
9927 22:53:48.648382 INFO: [APUAPC] D2_APC_0: 0xffffffff
9928 22:53:48.651754 INFO: [APUAPC] D2_APC_1: 0xffffffff
9929 22:53:48.655389 INFO: [APUAPC] D2_APC_2: 0x3fffff
9930 22:53:48.655471 INFO: [APUAPC] D2_APC_3: 0x0
9931 22:53:48.658849 INFO: [APUAPC] D3_APC_0: 0xffffffff
9932 22:53:48.662013 INFO: [APUAPC] D3_APC_1: 0xffffffff
9933 22:53:48.665060 INFO: [APUAPC] D3_APC_2: 0x3fffff
9934 22:53:48.668828 INFO: [APUAPC] D3_APC_3: 0x0
9935 22:53:48.672042 INFO: [APUAPC] D4_APC_0: 0xffffffff
9936 22:53:48.675478 INFO: [APUAPC] D4_APC_1: 0xffffffff
9937 22:53:48.678842 INFO: [APUAPC] D4_APC_2: 0x3fffff
9938 22:53:48.682116 INFO: [APUAPC] D4_APC_3: 0x0
9939 22:53:48.685480 INFO: [APUAPC] D5_APC_0: 0xffffffff
9940 22:53:48.688934 INFO: [APUAPC] D5_APC_1: 0xffffffff
9941 22:53:48.691950 INFO: [APUAPC] D5_APC_2: 0x3fffff
9942 22:53:48.695454 INFO: [APUAPC] D5_APC_3: 0x0
9943 22:53:48.698987 INFO: [APUAPC] D6_APC_0: 0xffffffff
9944 22:53:48.701978 INFO: [APUAPC] D6_APC_1: 0xffffffff
9945 22:53:48.705201 INFO: [APUAPC] D6_APC_2: 0x3fffff
9946 22:53:48.708967 INFO: [APUAPC] D6_APC_3: 0x0
9947 22:53:48.711914 INFO: [APUAPC] D7_APC_0: 0xffffffff
9948 22:53:48.715543 INFO: [APUAPC] D7_APC_1: 0xffffffff
9949 22:53:48.718767 INFO: [APUAPC] D7_APC_2: 0x3fffff
9950 22:53:48.722132 INFO: [APUAPC] D7_APC_3: 0x0
9951 22:53:48.725488 INFO: [APUAPC] D8_APC_0: 0xffffffff
9952 22:53:48.728642 INFO: [APUAPC] D8_APC_1: 0xffffffff
9953 22:53:48.731803 INFO: [APUAPC] D8_APC_2: 0x3fffff
9954 22:53:48.735073 INFO: [APUAPC] D8_APC_3: 0x0
9955 22:53:48.738462 INFO: [APUAPC] D9_APC_0: 0xffffffff
9956 22:53:48.741679 INFO: [APUAPC] D9_APC_1: 0xffffffff
9957 22:53:48.745587 INFO: [APUAPC] D9_APC_2: 0x3fffff
9958 22:53:48.748334 INFO: [APUAPC] D9_APC_3: 0x0
9959 22:53:48.752232 INFO: [APUAPC] D10_APC_0: 0xffffffff
9960 22:53:48.755415 INFO: [APUAPC] D10_APC_1: 0xffffffff
9961 22:53:48.758613 INFO: [APUAPC] D10_APC_2: 0x3fffff
9962 22:53:48.761981 INFO: [APUAPC] D10_APC_3: 0x0
9963 22:53:48.765417 INFO: [APUAPC] D11_APC_0: 0xffffffff
9964 22:53:48.768321 INFO: [APUAPC] D11_APC_1: 0xffffffff
9965 22:53:48.772142 INFO: [APUAPC] D11_APC_2: 0x3fffff
9966 22:53:48.775474 INFO: [APUAPC] D11_APC_3: 0x0
9967 22:53:48.778894 INFO: [APUAPC] D12_APC_0: 0xffffffff
9968 22:53:48.782193 INFO: [APUAPC] D12_APC_1: 0xffffffff
9969 22:53:48.785516 INFO: [APUAPC] D12_APC_2: 0x3fffff
9970 22:53:48.788338 INFO: [APUAPC] D12_APC_3: 0x0
9971 22:53:48.791912 INFO: [APUAPC] D13_APC_0: 0xffffffff
9972 22:53:48.795441 INFO: [APUAPC] D13_APC_1: 0xffffffff
9973 22:53:48.798459 INFO: [APUAPC] D13_APC_2: 0x3fffff
9974 22:53:48.802182 INFO: [APUAPC] D13_APC_3: 0x0
9975 22:53:48.805510 INFO: [APUAPC] D14_APC_0: 0xffffffff
9976 22:53:48.808796 INFO: [APUAPC] D14_APC_1: 0xffffffff
9977 22:53:48.811741 INFO: [APUAPC] D14_APC_2: 0x3fffff
9978 22:53:48.815166 INFO: [APUAPC] D14_APC_3: 0x0
9979 22:53:48.818545 INFO: [APUAPC] D15_APC_0: 0xffffffff
9980 22:53:48.822059 INFO: [APUAPC] D15_APC_1: 0xffffffff
9981 22:53:48.825345 INFO: [APUAPC] D15_APC_2: 0x3fffff
9982 22:53:48.828578 INFO: [APUAPC] D15_APC_3: 0x0
9983 22:53:48.831976 INFO: [APUAPC] APC_CON: 0x4
9984 22:53:48.832058 INFO: [NOCDAPC] D0_APC_0: 0x0
9985 22:53:48.835516 INFO: [NOCDAPC] D0_APC_1: 0x0
9986 22:53:48.838493 INFO: [NOCDAPC] D1_APC_0: 0x0
9987 22:53:48.842042 INFO: [NOCDAPC] D1_APC_1: 0xfff
9988 22:53:48.845031 INFO: [NOCDAPC] D2_APC_0: 0x0
9989 22:53:48.848208 INFO: [NOCDAPC] D2_APC_1: 0xfff
9990 22:53:48.851673 INFO: [NOCDAPC] D3_APC_0: 0x0
9991 22:53:48.855117 INFO: [NOCDAPC] D3_APC_1: 0xfff
9992 22:53:48.858339 INFO: [NOCDAPC] D4_APC_0: 0x0
9993 22:53:48.861580 INFO: [NOCDAPC] D4_APC_1: 0xfff
9994 22:53:48.865148 INFO: [NOCDAPC] D5_APC_0: 0x0
9995 22:53:48.865230 INFO: [NOCDAPC] D5_APC_1: 0xfff
9996 22:53:48.868369 INFO: [NOCDAPC] D6_APC_0: 0x0
9997 22:53:48.871873 INFO: [NOCDAPC] D6_APC_1: 0xfff
9998 22:53:48.875347 INFO: [NOCDAPC] D7_APC_0: 0x0
9999 22:53:48.878799 INFO: [NOCDAPC] D7_APC_1: 0xfff
10000 22:53:48.881614 INFO: [NOCDAPC] D8_APC_0: 0x0
10001 22:53:48.885276 INFO: [NOCDAPC] D8_APC_1: 0xfff
10002 22:53:48.888690 INFO: [NOCDAPC] D9_APC_0: 0x0
10003 22:53:48.891519 INFO: [NOCDAPC] D9_APC_1: 0xfff
10004 22:53:48.895003 INFO: [NOCDAPC] D10_APC_0: 0x0
10005 22:53:48.898245 INFO: [NOCDAPC] D10_APC_1: 0xfff
10006 22:53:48.898339 INFO: [NOCDAPC] D11_APC_0: 0x0
10007 22:53:48.901770 INFO: [NOCDAPC] D11_APC_1: 0xfff
10008 22:53:48.905059 INFO: [NOCDAPC] D12_APC_0: 0x0
10009 22:53:48.908066 INFO: [NOCDAPC] D12_APC_1: 0xfff
10010 22:53:48.911594 INFO: [NOCDAPC] D13_APC_0: 0x0
10011 22:53:48.914722 INFO: [NOCDAPC] D13_APC_1: 0xfff
10012 22:53:48.918212 INFO: [NOCDAPC] D14_APC_0: 0x0
10013 22:53:48.921897 INFO: [NOCDAPC] D14_APC_1: 0xfff
10014 22:53:48.924817 INFO: [NOCDAPC] D15_APC_0: 0x0
10015 22:53:48.928043 INFO: [NOCDAPC] D15_APC_1: 0xfff
10016 22:53:48.931496 INFO: [NOCDAPC] APC_CON: 0x4
10017 22:53:48.934939 INFO: [APUAPC] set_apusys_apc done
10018 22:53:48.938181 INFO: [DEVAPC] devapc_init done
10019 22:53:48.941824 INFO: GICv3 without legacy support detected.
10020 22:53:48.945024 INFO: ARM GICv3 driver initialized in EL3
10021 22:53:48.948028 INFO: Maximum SPI INTID supported: 639
10022 22:53:48.951727 INFO: BL31: Initializing runtime services
10023 22:53:48.958142 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10024 22:53:48.961757 INFO: SPM: enable CPC mode
10025 22:53:48.968144 INFO: mcdi ready for mcusys-off-idle and system suspend
10026 22:53:48.971445 INFO: BL31: Preparing for EL3 exit to normal world
10027 22:53:48.974414 INFO: Entry point address = 0x80000000
10028 22:53:48.978008 INFO: SPSR = 0x8
10029 22:53:48.982633
10030 22:53:48.982704
10031 22:53:48.982775
10032 22:53:48.986215 Starting depthcharge on Spherion...
10033 22:53:48.986286
10034 22:53:48.986346 Wipe memory regions:
10035 22:53:48.986419
10036 22:53:48.987003 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
10037 22:53:48.987101 start: 2.2.4 bootloader-commands (timeout 00:04:27) [common]
10038 22:53:48.987192 Setting prompt string to ['asurada:']
10039 22:53:48.987271 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:27)
10040 22:53:48.989605 [0x00000040000000, 0x00000054600000)
10041 22:53:49.111619
10042 22:53:49.111752 [0x00000054660000, 0x00000080000000)
10043 22:53:49.372396
10044 22:53:49.372528 [0x000000821a7280, 0x000000ffe64000)
10045 22:53:50.117261
10046 22:53:50.117427 [0x00000100000000, 0x00000240000000)
10047 22:53:52.007591
10048 22:53:52.010970 Initializing XHCI USB controller at 0x11200000.
10049 22:53:53.049057
10050 22:53:53.052641 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10051 22:53:53.052736
10052 22:53:53.052801
10053 22:53:53.052862
10054 22:53:53.053145 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10056 22:53:53.153466 asurada: tftpboot 192.168.201.1 13683720/tftp-deploy-2rfxgyld/kernel/image.itb 13683720/tftp-deploy-2rfxgyld/kernel/cmdline
10057 22:53:53.153587 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10058 22:53:53.153711 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:23)
10059 22:53:53.157612 tftpboot 192.168.201.1 13683720/tftp-deploy-2rfxgyld/kernel/image.itp-deploy-2rfxgyld/kernel/cmdline
10060 22:53:53.157698
10061 22:53:53.157763 Waiting for link
10062 22:53:53.316216
10063 22:53:53.316332 R8152: Initializing
10064 22:53:53.316400
10065 22:53:53.319160 Version 9 (ocp_data = 6010)
10066 22:53:53.319243
10067 22:53:53.322329 R8152: Done initializing
10068 22:53:53.322412
10069 22:53:53.322478 Adding net device
10070 22:53:55.207421
10071 22:53:55.207568 done.
10072 22:53:55.207637
10073 22:53:55.207698 MAC: 00:e0:4c:72:2d:d6
10074 22:53:55.207756
10075 22:53:55.210829 Sending DHCP discover... done.
10076 22:53:55.210912
10077 22:54:05.534560 Waiting for reply... R8152: Bulk read error 0xffffffbf
10078 22:54:05.535068
10079 22:54:05.538386 Receive failed.
10080 22:54:05.538871
10081 22:54:05.539244 done.
10082 22:54:05.539553
10083 22:54:05.541375 Sending DHCP request... done.
10084 22:54:05.541790
10085 22:54:05.544374 Waiting for reply... done.
10086 22:54:05.544669
10087 22:54:05.547353 My ip is 192.168.201.21
10088 22:54:05.547575
10089 22:54:05.550879 The DHCP server ip is 192.168.201.1
10090 22:54:05.551103
10091 22:54:05.554036 TFTP server IP predefined by user: 192.168.201.1
10092 22:54:05.554260
10093 22:54:05.560546 Bootfile predefined by user: 13683720/tftp-deploy-2rfxgyld/kernel/image.itb
10094 22:54:05.560628
10095 22:54:05.563823 Sending tftp read request... done.
10096 22:54:05.563905
10097 22:54:05.567102 Waiting for the transfer...
10098 22:54:05.567183
10099 22:54:05.820205 00000000 ################################################################
10100 22:54:05.820338
10101 22:54:06.069544 00080000 ################################################################
10102 22:54:06.069662
10103 22:54:06.319369 00100000 ################################################################
10104 22:54:06.319490
10105 22:54:06.568718 00180000 ################################################################
10106 22:54:06.568848
10107 22:54:06.822327 00200000 ################################################################
10108 22:54:06.822449
10109 22:54:07.071295 00280000 ################################################################
10110 22:54:07.071449
10111 22:54:07.320684 00300000 ################################################################
10112 22:54:07.320808
10113 22:54:07.569309 00380000 ################################################################
10114 22:54:07.569444
10115 22:54:07.818255 00400000 ################################################################
10116 22:54:07.818383
10117 22:54:08.067888 00480000 ################################################################
10118 22:54:08.068068
10119 22:54:08.325058 00500000 ################################################################
10120 22:54:08.325209
10121 22:54:08.590615 00580000 ################################################################
10122 22:54:08.590758
10123 22:54:08.839366 00600000 ################################################################
10124 22:54:08.839491
10125 22:54:09.088398 00680000 ################################################################
10126 22:54:09.088513
10127 22:54:09.353669 00700000 ################################################################
10128 22:54:09.353799
10129 22:54:09.625683 00780000 ################################################################
10130 22:54:09.625817
10131 22:54:09.890413 00800000 ################################################################
10132 22:54:09.890541
10133 22:54:10.142198 00880000 ################################################################
10134 22:54:10.142319
10135 22:54:10.391890 00900000 ################################################################
10136 22:54:10.392015
10137 22:54:10.640152 00980000 ################################################################
10138 22:54:10.640298
10139 22:54:10.889789 00a00000 ################################################################
10140 22:54:10.889913
10141 22:54:11.139083 00a80000 ################################################################
10142 22:54:11.139203
10143 22:54:11.388093 00b00000 ################################################################
10144 22:54:11.388211
10145 22:54:11.639188 00b80000 ################################################################
10146 22:54:11.639318
10147 22:54:11.888584 00c00000 ################################################################
10148 22:54:11.888704
10149 22:54:12.137655 00c80000 ################################################################
10150 22:54:12.137777
10151 22:54:12.386695 00d00000 ################################################################
10152 22:54:12.386813
10153 22:54:12.635781 00d80000 ################################################################
10154 22:54:12.635911
10155 22:54:12.884852 00e00000 ################################################################
10156 22:54:12.884975
10157 22:54:13.134829 00e80000 ################################################################
10158 22:54:13.134946
10159 22:54:13.384341 00f00000 ################################################################
10160 22:54:13.384459
10161 22:54:13.633913 00f80000 ################################################################
10162 22:54:13.634039
10163 22:54:13.882017 01000000 ################################################################
10164 22:54:13.882151
10165 22:54:14.131668 01080000 ################################################################
10166 22:54:14.131794
10167 22:54:14.385055 01100000 ################################################################
10168 22:54:14.385184
10169 22:54:14.634274 01180000 ################################################################
10170 22:54:14.634402
10171 22:54:14.884316 01200000 ################################################################
10172 22:54:14.884482
10173 22:54:15.133474 01280000 ################################################################
10174 22:54:15.133599
10175 22:54:15.383378 01300000 ################################################################
10176 22:54:15.383504
10177 22:54:15.653966 01380000 ################################################################
10178 22:54:15.654084
10179 22:54:15.911298 01400000 ################################################################
10180 22:54:15.911467
10181 22:54:16.162293 01480000 ################################################################
10182 22:54:16.162423
10183 22:54:16.411383 01500000 ################################################################
10184 22:54:16.411526
10185 22:54:16.660393 01580000 ################################################################
10186 22:54:16.660513
10187 22:54:16.909387 01600000 ################################################################
10188 22:54:16.909523
10189 22:54:17.158555 01680000 ################################################################
10190 22:54:17.158701
10191 22:54:17.407508 01700000 ################################################################
10192 22:54:17.407668
10193 22:54:17.661010 01780000 ################################################################
10194 22:54:17.661171
10195 22:54:17.910496 01800000 ################################################################
10196 22:54:17.910639
10197 22:54:18.161751 01880000 ################################################################
10198 22:54:18.161876
10199 22:54:18.417776 01900000 ################################################################
10200 22:54:18.417924
10201 22:54:18.667379 01980000 ################################################################
10202 22:54:18.667527
10203 22:54:18.926659 01a00000 ################################################################
10204 22:54:18.926788
10205 22:54:19.175482 01a80000 ################################################################
10206 22:54:19.175614
10207 22:54:19.425501 01b00000 ################################################################
10208 22:54:19.425632
10209 22:54:19.677106 01b80000 ################################################################
10210 22:54:19.677274
10211 22:54:19.925548 01c00000 ################################################################
10212 22:54:19.925669
10213 22:54:20.180060 01c80000 ################################################################
10214 22:54:20.180190
10215 22:54:20.433129 01d00000 ################################################################
10216 22:54:20.433270
10217 22:54:20.685136 01d80000 ################################################################
10218 22:54:20.685279
10219 22:54:20.934775 01e00000 ################################################################
10220 22:54:20.934933
10221 22:54:21.183881 01e80000 ################################################################
10222 22:54:21.184035
10223 22:54:21.445002 01f00000 ################################################################
10224 22:54:21.445160
10225 22:54:21.693696 01f80000 ################################################################
10226 22:54:21.693821
10227 22:54:21.943461 02000000 ################################################################
10228 22:54:21.943623
10229 22:54:22.134449 02080000 ################################################# done.
10230 22:54:22.134923
10231 22:54:22.137432 The bootfile was 34472622 bytes long.
10232 22:54:22.137898
10233 22:54:22.140805 Sending tftp read request... done.
10234 22:54:22.141262
10235 22:54:22.143819 Waiting for the transfer...
10236 22:54:22.144277
10237 22:54:22.144638 00000000 # done.
10238 22:54:22.144982
10239 22:54:22.150377 Command line loaded dynamically from TFTP file: 13683720/tftp-deploy-2rfxgyld/kernel/cmdline
10240 22:54:22.153614
10241 22:54:22.167115 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10242 22:54:22.167541
10243 22:54:22.167867 Loading FIT.
10244 22:54:22.168173
10245 22:54:22.170363 Image ramdisk-1 has 21363773 bytes.
10246 22:54:22.170780
10247 22:54:22.173517 Image fdt-1 has 47258 bytes.
10248 22:54:22.173929
10249 22:54:22.176913 Image kernel-1 has 13059555 bytes.
10250 22:54:22.177376
10251 22:54:22.183870 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10252 22:54:22.184289
10253 22:54:22.203473 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10254 22:54:22.203918
10255 22:54:22.206761 Choosing best match conf-1 for compat google,spherion-rev2.
10256 22:54:22.211488
10257 22:54:22.216582 Connected to device vid:did:rid of 1ae0:0028:00
10258 22:54:22.224467
10259 22:54:22.227714 tpm_get_response: command 0x17b, return code 0x0
10260 22:54:22.228133
10261 22:54:22.234446 ec_init: CrosEC protocol v3 supported (256, 248)
10262 22:54:22.234865
10263 22:54:22.237527 tpm_cleanup: add release locality here.
10264 22:54:22.237942
10265 22:54:22.240800 Shutting down all USB controllers.
10266 22:54:22.241216
10267 22:54:22.244144 Removing current net device
10268 22:54:22.244556
10269 22:54:22.247484 Exiting depthcharge with code 4 at timestamp: 62579426
10270 22:54:22.247902
10271 22:54:22.254073 LZMA decompressing kernel-1 to 0x821a6718
10272 22:54:22.254598
10273 22:54:22.257517 LZMA decompressing kernel-1 to 0x40000000
10274 22:54:23.867889
10275 22:54:23.868198 jumping to kernel
10276 22:54:23.869380 end: 2.2.4 bootloader-commands (duration 00:00:35) [common]
10277 22:54:23.869637 start: 2.2.5 auto-login-action (timeout 00:03:52) [common]
10278 22:54:23.869819 Setting prompt string to ['Linux version [0-9]']
10279 22:54:23.870005 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10280 22:54:23.870171 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10281 22:54:23.950242
10282 22:54:23.953376 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10283 22:54:23.957068 start: 2.2.5.1 login-action (timeout 00:03:52) [common]
10284 22:54:23.957720 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10285 22:54:23.958183 Setting prompt string to []
10286 22:54:23.958737 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10287 22:54:23.959170 Using line separator: #'\n'#
10288 22:54:23.959523 No login prompt set.
10289 22:54:23.960123 Parsing kernel messages
10290 22:54:23.960605 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10291 22:54:23.961529 [login-action] Waiting for messages, (timeout 00:03:52)
10292 22:54:23.961989 Waiting using forced prompt support (timeout 00:01:56)
10293 22:54:23.976470 [ 0.000000] Linux version 6.1.90-cip20 (KernelCI@build-j189066-arm64-gcc-10-defconfig-arm64-chromebook-glbz2) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue May 7 22:33:59 UTC 2024
10294 22:54:23.979885 [ 0.000000] random: crng init done
10295 22:54:23.986931 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10296 22:54:23.989993 [ 0.000000] efi: UEFI not found.
10297 22:54:23.996798 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10298 22:54:24.003620 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10299 22:54:24.013377 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10300 22:54:24.023964 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10301 22:54:24.030057 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10302 22:54:24.036651 [ 0.000000] printk: bootconsole [mtk8250] enabled
10303 22:54:24.043401 [ 0.000000] NUMA: No NUMA configuration found
10304 22:54:24.049990 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10305 22:54:24.053256 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10306 22:54:24.056673 [ 0.000000] Zone ranges:
10307 22:54:24.063239 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10308 22:54:24.066771 [ 0.000000] DMA32 empty
10309 22:54:24.073207 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10310 22:54:24.076304 [ 0.000000] Movable zone start for each node
10311 22:54:24.079560 [ 0.000000] Early memory node ranges
10312 22:54:24.086718 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10313 22:54:24.093355 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10314 22:54:24.099873 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10315 22:54:24.103182 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10316 22:54:24.110024 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10317 22:54:24.116396 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10318 22:54:24.175235 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10319 22:54:24.181979 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10320 22:54:24.188856 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10321 22:54:24.191808 [ 0.000000] psci: probing for conduit method from DT.
10322 22:54:24.198601 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10323 22:54:24.202150 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10324 22:54:24.208420 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10325 22:54:24.211215 [ 0.000000] psci: SMC Calling Convention v1.2
10326 22:54:24.218343 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10327 22:54:24.221809 [ 0.000000] Detected VIPT I-cache on CPU0
10328 22:54:24.228174 [ 0.000000] CPU features: detected: GIC system register CPU interface
10329 22:54:24.234967 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10330 22:54:24.241556 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10331 22:54:24.248078 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10332 22:54:24.254455 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10333 22:54:24.261155 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10334 22:54:24.268320 [ 0.000000] alternatives: applying boot alternatives
10335 22:54:24.271158 [ 0.000000] Fallback order for Node 0: 0
10336 22:54:24.281203 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10337 22:54:24.284263 [ 0.000000] Policy zone: Normal
10338 22:54:24.297654 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10339 22:54:24.307481 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10340 22:54:24.319214 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10341 22:54:24.329743 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10342 22:54:24.336005 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10343 22:54:24.339777 <6>[ 0.000000] software IO TLB: area num 8.
10344 22:54:24.396211 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10345 22:54:24.545653 <6>[ 0.000000] Memory: 7943328K/8385536K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 409440K reserved, 32768K cma-reserved)
10346 22:54:24.552210 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10347 22:54:24.558794 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10348 22:54:24.562014 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10349 22:54:24.568855 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10350 22:54:24.575357 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10351 22:54:24.578999 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10352 22:54:24.588895 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10353 22:54:24.595482 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10354 22:54:24.598889 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10355 22:54:24.606723 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10356 22:54:24.610229 <6>[ 0.000000] GICv3: 608 SPIs implemented
10357 22:54:24.616404 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10358 22:54:24.620037 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10359 22:54:24.623366 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10360 22:54:24.633105 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10361 22:54:24.642887 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10362 22:54:24.656378 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10363 22:54:24.663054 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10364 22:54:24.672365 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10365 22:54:24.685042 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10366 22:54:24.691784 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10367 22:54:24.698620 <6>[ 0.009186] Console: colour dummy device 80x25
10368 22:54:24.708620 <6>[ 0.013913] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10369 22:54:24.711804 <6>[ 0.024419] pid_max: default: 32768 minimum: 301
10370 22:54:24.718560 <6>[ 0.029320] LSM: Security Framework initializing
10371 22:54:24.725077 <6>[ 0.034255] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10372 22:54:24.735490 <6>[ 0.042069] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10373 22:54:24.741844 <6>[ 0.051496] cblist_init_generic: Setting adjustable number of callback queues.
10374 22:54:24.748650 <6>[ 0.058986] cblist_init_generic: Setting shift to 3 and lim to 1.
10375 22:54:24.758426 <6>[ 0.065364] cblist_init_generic: Setting adjustable number of callback queues.
10376 22:54:24.765284 <6>[ 0.072791] cblist_init_generic: Setting shift to 3 and lim to 1.
10377 22:54:24.768341 <6>[ 0.079189] rcu: Hierarchical SRCU implementation.
10378 22:54:24.775144 <6>[ 0.084203] rcu: Max phase no-delay instances is 1000.
10379 22:54:24.781590 <6>[ 0.091257] EFI services will not be available.
10380 22:54:24.785034 <6>[ 0.096242] smp: Bringing up secondary CPUs ...
10381 22:54:24.793128 <6>[ 0.101294] Detected VIPT I-cache on CPU1
10382 22:54:24.799798 <6>[ 0.101366] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10383 22:54:24.806526 <6>[ 0.101397] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10384 22:54:24.809600 <6>[ 0.101731] Detected VIPT I-cache on CPU2
10385 22:54:24.816219 <6>[ 0.101780] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10386 22:54:24.826054 <6>[ 0.101795] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10387 22:54:24.829649 <6>[ 0.102061] Detected VIPT I-cache on CPU3
10388 22:54:24.836183 <6>[ 0.102109] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10389 22:54:24.842847 <6>[ 0.102122] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10390 22:54:24.846027 <6>[ 0.102431] CPU features: detected: Spectre-v4
10391 22:54:24.852756 <6>[ 0.102438] CPU features: detected: Spectre-BHB
10392 22:54:24.855904 <6>[ 0.102442] Detected PIPT I-cache on CPU4
10393 22:54:24.862705 <6>[ 0.102503] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10394 22:54:24.869404 <6>[ 0.102521] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10395 22:54:24.875834 <6>[ 0.102817] Detected PIPT I-cache on CPU5
10396 22:54:24.882578 <6>[ 0.102882] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10397 22:54:24.889197 <6>[ 0.102898] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10398 22:54:24.892562 <6>[ 0.103168] Detected PIPT I-cache on CPU6
10399 22:54:24.898989 <6>[ 0.103228] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10400 22:54:24.905426 <6>[ 0.103243] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10401 22:54:24.913030 <6>[ 0.103539] Detected PIPT I-cache on CPU7
10402 22:54:24.918738 <6>[ 0.103605] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10403 22:54:24.925905 <6>[ 0.103621] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10404 22:54:24.928570 <6>[ 0.103668] smp: Brought up 1 node, 8 CPUs
10405 22:54:24.935378 <6>[ 0.245027] SMP: Total of 8 processors activated.
10406 22:54:24.938616 <6>[ 0.249979] CPU features: detected: 32-bit EL0 Support
10407 22:54:24.948829 <6>[ 0.255375] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10408 22:54:24.955251 <6>[ 0.264176] CPU features: detected: Common not Private translations
10409 22:54:24.962081 <6>[ 0.270691] CPU features: detected: CRC32 instructions
10410 22:54:24.965145 <6>[ 0.276076] CPU features: detected: RCpc load-acquire (LDAPR)
10411 22:54:24.972193 <6>[ 0.282036] CPU features: detected: LSE atomic instructions
10412 22:54:24.978418 <6>[ 0.287818] CPU features: detected: Privileged Access Never
10413 22:54:24.984961 <6>[ 0.293633] CPU features: detected: RAS Extension Support
10414 22:54:24.991852 <6>[ 0.299276] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10415 22:54:24.995062 <6>[ 0.306495] CPU: All CPU(s) started at EL2
10416 22:54:25.001487 <6>[ 0.310812] alternatives: applying system-wide alternatives
10417 22:54:25.010857 <6>[ 0.321689] devtmpfs: initialized
10418 22:54:25.023411 <6>[ 0.330676] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10419 22:54:25.033232 <6>[ 0.340638] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10420 22:54:25.039894 <6>[ 0.348838] pinctrl core: initialized pinctrl subsystem
10421 22:54:25.043322 <6>[ 0.355679] DMI not present or invalid.
10422 22:54:25.049997 <6>[ 0.360096] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10423 22:54:25.059692 <6>[ 0.366977] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10424 22:54:25.066747 <6>[ 0.374560] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10425 22:54:25.076293 <6>[ 0.382791] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10426 22:54:25.079551 <6>[ 0.391033] audit: initializing netlink subsys (disabled)
10427 22:54:25.089612 <5>[ 0.396728] audit: type=2000 audit(0.284:1): state=initialized audit_enabled=0 res=1
10428 22:54:25.096445 <6>[ 0.397492] thermal_sys: Registered thermal governor 'step_wise'
10429 22:54:25.102979 <6>[ 0.404695] thermal_sys: Registered thermal governor 'power_allocator'
10430 22:54:25.106394 <6>[ 0.410951] cpuidle: using governor menu
10431 22:54:25.112762 <6>[ 0.421912] NET: Registered PF_QIPCRTR protocol family
10432 22:54:25.119683 <6>[ 0.427391] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10433 22:54:25.125612 <6>[ 0.434492] ASID allocator initialised with 32768 entries
10434 22:54:25.129211 <6>[ 0.441155] Serial: AMBA PL011 UART driver
10435 22:54:25.139848 <4>[ 0.450244] Trying to register duplicate clock ID: 134
10436 22:54:25.199811 <6>[ 0.513992] KASLR enabled
10437 22:54:25.214625 <6>[ 0.521811] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10438 22:54:25.221088 <6>[ 0.528824] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10439 22:54:25.227877 <6>[ 0.535312] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10440 22:54:25.234296 <6>[ 0.542319] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10441 22:54:25.241131 <6>[ 0.548807] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10442 22:54:25.247792 <6>[ 0.555813] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10443 22:54:25.254328 <6>[ 0.562299] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10444 22:54:25.261026 <6>[ 0.569302] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10445 22:54:25.264329 <6>[ 0.576834] ACPI: Interpreter disabled.
10446 22:54:25.272996 <6>[ 0.583331] iommu: Default domain type: Translated
10447 22:54:25.279899 <6>[ 0.588445] iommu: DMA domain TLB invalidation policy: strict mode
10448 22:54:25.282526 <5>[ 0.595109] SCSI subsystem initialized
10449 22:54:25.289557 <6>[ 0.599276] usbcore: registered new interface driver usbfs
10450 22:54:25.295694 <6>[ 0.605008] usbcore: registered new interface driver hub
10451 22:54:25.298985 <6>[ 0.610561] usbcore: registered new device driver usb
10452 22:54:25.305854 <6>[ 0.616694] pps_core: LinuxPPS API ver. 1 registered
10453 22:54:25.315598 <6>[ 0.621890] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10454 22:54:25.318789 <6>[ 0.631236] PTP clock support registered
10455 22:54:25.322213 <6>[ 0.635479] EDAC MC: Ver: 3.0.0
10456 22:54:25.330218 <6>[ 0.640669] FPGA manager framework
10457 22:54:25.336280 <6>[ 0.644357] Advanced Linux Sound Architecture Driver Initialized.
10458 22:54:25.339555 <6>[ 0.651144] vgaarb: loaded
10459 22:54:25.346130 <6>[ 0.654295] clocksource: Switched to clocksource arch_sys_counter
10460 22:54:25.349450 <5>[ 0.660739] VFS: Disk quotas dquot_6.6.0
10461 22:54:25.356237 <6>[ 0.664923] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10462 22:54:25.359476 <6>[ 0.672113] pnp: PnP ACPI: disabled
10463 22:54:25.368757 <6>[ 0.678841] NET: Registered PF_INET protocol family
10464 22:54:25.377896 <6>[ 0.684439] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10465 22:54:25.389647 <6>[ 0.696777] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10466 22:54:25.399627 <6>[ 0.705592] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10467 22:54:25.406057 <6>[ 0.713562] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10468 22:54:25.412845 <6>[ 0.722263] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10469 22:54:25.425478 <6>[ 0.732020] TCP: Hash tables configured (established 65536 bind 65536)
10470 22:54:25.431421 <6>[ 0.738882] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10471 22:54:25.437941 <6>[ 0.746082] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10472 22:54:25.444770 <6>[ 0.753785] NET: Registered PF_UNIX/PF_LOCAL protocol family
10473 22:54:25.451739 <6>[ 0.759943] RPC: Registered named UNIX socket transport module.
10474 22:54:25.455208 <6>[ 0.766096] RPC: Registered udp transport module.
10475 22:54:25.461583 <6>[ 0.771027] RPC: Registered tcp transport module.
10476 22:54:25.468242 <6>[ 0.775959] RPC: Registered tcp NFSv4.1 backchannel transport module.
10477 22:54:25.471221 <6>[ 0.782623] PCI: CLS 0 bytes, default 64
10478 22:54:25.474410 <6>[ 0.786955] Unpacking initramfs...
10479 22:54:25.499230 <6>[ 0.806411] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10480 22:54:25.508916 <6>[ 0.815087] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10481 22:54:25.512544 <6>[ 0.823879] kvm [1]: IPA Size Limit: 40 bits
10482 22:54:25.519004 <6>[ 0.828406] kvm [1]: GICv3: no GICV resource entry
10483 22:54:25.522572 <6>[ 0.833427] kvm [1]: disabling GICv2 emulation
10484 22:54:25.529145 <6>[ 0.838116] kvm [1]: GIC system register CPU interface enabled
10485 22:54:25.531979 <6>[ 0.844278] kvm [1]: vgic interrupt IRQ18
10486 22:54:25.538926 <6>[ 0.848662] kvm [1]: VHE mode initialized successfully
10487 22:54:25.545214 <5>[ 0.855153] Initialise system trusted keyrings
10488 22:54:25.552151 <6>[ 0.859987] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10489 22:54:25.559720 <6>[ 0.870075] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10490 22:54:25.566157 <5>[ 0.876475] NFS: Registering the id_resolver key type
10491 22:54:25.569395 <5>[ 0.881787] Key type id_resolver registered
10492 22:54:25.576304 <5>[ 0.886202] Key type id_legacy registered
10493 22:54:25.583060 <6>[ 0.890483] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10494 22:54:25.589264 <6>[ 0.897407] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10495 22:54:25.596054 <6>[ 0.905127] 9p: Installing v9fs 9p2000 file system support
10496 22:54:25.632319 <5>[ 0.943137] Key type asymmetric registered
10497 22:54:25.635646 <5>[ 0.947467] Asymmetric key parser 'x509' registered
10498 22:54:25.645817 <6>[ 0.952603] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10499 22:54:25.649129 <6>[ 0.960219] io scheduler mq-deadline registered
10500 22:54:25.652469 <6>[ 0.964996] io scheduler kyber registered
10501 22:54:25.671733 <6>[ 0.982246] EINJ: ACPI disabled.
10502 22:54:25.704331 <4>[ 1.008379] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10503 22:54:25.714292 <4>[ 1.019032] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10504 22:54:25.729358 <6>[ 1.040045] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10505 22:54:25.737401 <6>[ 1.048035] printk: console [ttyS0] disabled
10506 22:54:25.765294 <6>[ 1.072667] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10507 22:54:25.771996 <6>[ 1.082138] printk: console [ttyS0] enabled
10508 22:54:25.775220 <6>[ 1.082138] printk: console [ttyS0] enabled
10509 22:54:25.781920 <6>[ 1.091035] printk: bootconsole [mtk8250] disabled
10510 22:54:25.785329 <6>[ 1.091035] printk: bootconsole [mtk8250] disabled
10511 22:54:25.791787 <6>[ 1.102087] SuperH (H)SCI(F) driver initialized
10512 22:54:25.795255 <6>[ 1.107369] msm_serial: driver initialized
10513 22:54:25.809040 <6>[ 1.116465] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10514 22:54:25.818979 <6>[ 1.125011] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10515 22:54:25.826091 <6>[ 1.133553] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10516 22:54:25.835538 <6>[ 1.142180] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10517 22:54:25.845475 <6>[ 1.150887] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10518 22:54:25.852001 <6>[ 1.159602] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10519 22:54:25.862291 <6>[ 1.168148] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10520 22:54:25.868810 <6>[ 1.176953] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10521 22:54:25.878109 <6>[ 1.185496] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10522 22:54:25.890046 <6>[ 1.201112] loop: module loaded
10523 22:54:25.896816 <6>[ 1.207088] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10524 22:54:25.919529 <4>[ 1.230423] mtk-pmic-keys: Failed to locate of_node [id: -1]
10525 22:54:25.926172 <6>[ 1.237233] megasas: 07.719.03.00-rc1
10526 22:54:25.935781 <6>[ 1.246935] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10527 22:54:25.942802 <6>[ 1.253724] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10528 22:54:25.959437 <6>[ 1.270277] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10529 22:54:26.016277 <6>[ 1.320334] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10530 22:54:26.379321 <6>[ 1.689809] Freeing initrd memory: 20856K
10531 22:54:26.394810 <6>[ 1.705410] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10532 22:54:26.405415 <6>[ 1.716172] tun: Universal TUN/TAP device driver, 1.6
10533 22:54:26.409001 <6>[ 1.722253] thunder_xcv, ver 1.0
10534 22:54:26.412234 <6>[ 1.725754] thunder_bgx, ver 1.0
10535 22:54:26.415290 <6>[ 1.729251] nicpf, ver 1.0
10536 22:54:26.426052 <6>[ 1.733295] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10537 22:54:26.429165 <6>[ 1.740770] hns3: Copyright (c) 2017 Huawei Corporation.
10538 22:54:26.432512 <6>[ 1.746357] hclge is initializing
10539 22:54:26.439436 <6>[ 1.749927] e1000: Intel(R) PRO/1000 Network Driver
10540 22:54:26.446307 <6>[ 1.755056] e1000: Copyright (c) 1999-2006 Intel Corporation.
10541 22:54:26.449568 <6>[ 1.761068] e1000e: Intel(R) PRO/1000 Network Driver
10542 22:54:26.456095 <6>[ 1.766285] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10543 22:54:26.462880 <6>[ 1.772473] igb: Intel(R) Gigabit Ethernet Network Driver
10544 22:54:26.469499 <6>[ 1.778124] igb: Copyright (c) 2007-2014 Intel Corporation.
10545 22:54:26.475942 <6>[ 1.783960] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10546 22:54:26.479203 <6>[ 1.790478] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10547 22:54:26.486092 <6>[ 1.796943] sky2: driver version 1.30
10548 22:54:26.493023 <6>[ 1.801907] usbcore: registered new device driver r8152-cfgselector
10549 22:54:26.499915 <6>[ 1.808441] usbcore: registered new interface driver r8152
10550 22:54:26.502941 <6>[ 1.814253] VFIO - User Level meta-driver version: 0.3
10551 22:54:26.512130 <6>[ 1.822571] usbcore: registered new interface driver usb-storage
10552 22:54:26.518528 <6>[ 1.829017] usbcore: registered new device driver onboard-usb-hub
10553 22:54:26.527974 <6>[ 1.838217] mt6397-rtc mt6359-rtc: registered as rtc0
10554 22:54:26.537803 <6>[ 1.843680] mt6397-rtc mt6359-rtc: setting system clock to 2024-05-07T22:53:15 UTC (1715122395)
10555 22:54:26.541013 <6>[ 1.853265] i2c_dev: i2c /dev entries driver
10556 22:54:26.557874 <6>[ 1.865252] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10557 22:54:26.564428 <4>[ 1.874015] cpu cpu0: supply cpu not found, using dummy regulator
10558 22:54:26.571246 <4>[ 1.880441] cpu cpu1: supply cpu not found, using dummy regulator
10559 22:54:26.577815 <4>[ 1.886851] cpu cpu2: supply cpu not found, using dummy regulator
10560 22:54:26.584482 <4>[ 1.893269] cpu cpu3: supply cpu not found, using dummy regulator
10561 22:54:26.591060 <4>[ 1.899666] cpu cpu4: supply cpu not found, using dummy regulator
10562 22:54:26.598212 <4>[ 1.906079] cpu cpu5: supply cpu not found, using dummy regulator
10563 22:54:26.604575 <4>[ 1.912477] cpu cpu6: supply cpu not found, using dummy regulator
10564 22:54:26.607898 <4>[ 1.918872] cpu cpu7: supply cpu not found, using dummy regulator
10565 22:54:26.628531 <6>[ 1.939522] cpu cpu0: EM: created perf domain
10566 22:54:26.631951 <6>[ 1.944470] cpu cpu4: EM: created perf domain
10567 22:54:26.639178 <6>[ 1.950065] sdhci: Secure Digital Host Controller Interface driver
10568 22:54:26.645800 <6>[ 1.956498] sdhci: Copyright(c) Pierre Ossman
10569 22:54:26.652665 <6>[ 1.961460] Synopsys Designware Multimedia Card Interface Driver
10570 22:54:26.659199 <6>[ 1.968106] sdhci-pltfm: SDHCI platform and OF driver helper
10571 22:54:26.662315 <6>[ 1.968180] mmc0: CQHCI version 5.10
10572 22:54:26.669193 <6>[ 1.978031] ledtrig-cpu: registered to indicate activity on CPUs
10573 22:54:26.675916 <6>[ 1.985034] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10574 22:54:26.682600 <6>[ 1.992088] usbcore: registered new interface driver usbhid
10575 22:54:26.685947 <6>[ 1.997910] usbhid: USB HID core driver
10576 22:54:26.692692 <6>[ 2.002132] spi_master spi0: will run message pump with realtime priority
10577 22:54:26.737540 <6>[ 2.041449] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10578 22:54:26.753783 <6>[ 2.057451] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10579 22:54:26.760809 <6>[ 2.071031] mmc0: Command Queue Engine enabled
10580 22:54:26.767661 <6>[ 2.075784] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10581 22:54:26.774163 <6>[ 2.082727] cros-ec-spi spi0.0: Chrome EC device registered
10582 22:54:26.777398 <6>[ 2.083018] mmcblk0: mmc0:0001 DA4128 116 GiB
10583 22:54:26.793808 <6>[ 2.104259] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10584 22:54:26.803672 <6>[ 2.105838] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10585 22:54:26.810324 <6>[ 2.111481] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10586 22:54:26.813658 <6>[ 2.120812] NET: Registered PF_PACKET protocol family
10587 22:54:26.820392 <6>[ 2.125402] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10588 22:54:26.823601 <6>[ 2.130089] 9pnet: Installing 9P2000 support
10589 22:54:26.830751 <6>[ 2.135888] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10590 22:54:26.833544 <5>[ 2.139791] Key type dns_resolver registered
10591 22:54:26.840820 <6>[ 2.151210] registered taskstats version 1
10592 22:54:26.843861 <5>[ 2.155591] Loading compiled-in X.509 certificates
10593 22:54:26.875051 <4>[ 2.179179] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10594 22:54:26.884889 <4>[ 2.189902] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10595 22:54:26.891755 <3>[ 2.200438] debugfs: File 'uA_load' in directory '/' already present!
10596 22:54:26.898329 <3>[ 2.207193] debugfs: File 'min_uV' in directory '/' already present!
10597 22:54:26.905382 <3>[ 2.213812] debugfs: File 'max_uV' in directory '/' already present!
10598 22:54:26.912157 <3>[ 2.220424] debugfs: File 'constraint_flags' in directory '/' already present!
10599 22:54:26.923984 <6>[ 2.234733] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10600 22:54:26.931615 <6>[ 2.241863] xhci-mtk 11200000.usb: xHCI Host Controller
10601 22:54:26.937954 <6>[ 2.247391] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10602 22:54:26.948259 <6>[ 2.255330] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10603 22:54:26.954729 <6>[ 2.264757] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10604 22:54:26.961418 <6>[ 2.270829] xhci-mtk 11200000.usb: xHCI Host Controller
10605 22:54:26.968656 <6>[ 2.276305] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10606 22:54:26.975031 <6>[ 2.283951] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10607 22:54:26.981082 <6>[ 2.291771] hub 1-0:1.0: USB hub found
10608 22:54:26.984383 <6>[ 2.295789] hub 1-0:1.0: 1 port detected
10609 22:54:26.991065 <6>[ 2.300063] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10610 22:54:26.998213 <6>[ 2.308809] hub 2-0:1.0: USB hub found
10611 22:54:27.001452 <6>[ 2.312829] hub 2-0:1.0: 1 port detected
10612 22:54:27.010114 <6>[ 2.320791] mtk-msdc 11f70000.mmc: Got CD GPIO
10613 22:54:27.020245 <6>[ 2.327804] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10614 22:54:27.027016 <6>[ 2.335830] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10615 22:54:27.036890 <4>[ 2.343730] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10616 22:54:27.047107 <6>[ 2.353263] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10617 22:54:27.053327 <6>[ 2.361340] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10618 22:54:27.063235 <6>[ 2.369434] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10619 22:54:27.070111 <6>[ 2.377369] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10620 22:54:27.076367 <6>[ 2.385187] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10621 22:54:27.086261 <6>[ 2.393005] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10622 22:54:27.096332 <6>[ 2.403540] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10623 22:54:27.103117 <6>[ 2.411917] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10624 22:54:27.112843 <6>[ 2.420258] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10625 22:54:27.119766 <6>[ 2.428595] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10626 22:54:27.129752 <6>[ 2.436932] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10627 22:54:27.139564 <6>[ 2.445272] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10628 22:54:27.146206 <6>[ 2.453609] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10629 22:54:27.156257 <6>[ 2.461948] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10630 22:54:27.162460 <6>[ 2.470284] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10631 22:54:27.172549 <6>[ 2.478622] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10632 22:54:27.179162 <6>[ 2.486961] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10633 22:54:27.189504 <6>[ 2.495298] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10634 22:54:27.195417 <6>[ 2.503646] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10635 22:54:27.205746 <6>[ 2.511985] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10636 22:54:27.212265 <6>[ 2.520322] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10637 22:54:27.218625 <6>[ 2.529179] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10638 22:54:27.225841 <6>[ 2.536398] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10639 22:54:27.232859 <6>[ 2.543171] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10640 22:54:27.242741 <6>[ 2.549925] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10641 22:54:27.249166 <6>[ 2.556860] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10642 22:54:27.255765 <6>[ 2.563736] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10643 22:54:27.265735 <6>[ 2.572867] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10644 22:54:27.276168 <6>[ 2.581986] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10645 22:54:27.285665 <6>[ 2.591280] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10646 22:54:27.295710 <6>[ 2.600764] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10647 22:54:27.305250 <6>[ 2.610231] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10648 22:54:27.311945 <6>[ 2.619354] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10649 22:54:27.321843 <6>[ 2.628821] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10650 22:54:27.332412 <6>[ 2.637944] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10651 22:54:27.342034 <6>[ 2.647239] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10652 22:54:27.351860 <6>[ 2.657399] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10653 22:54:27.361876 <6>[ 2.669313] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10654 22:54:27.391389 <6>[ 2.698788] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10655 22:54:27.419271 <6>[ 2.729949] hub 2-1:1.0: USB hub found
10656 22:54:27.422353 <6>[ 2.734404] hub 2-1:1.0: 3 ports detected
10657 22:54:27.431131 <6>[ 2.741760] hub 2-1:1.0: USB hub found
10658 22:54:27.434344 <6>[ 2.746145] hub 2-1:1.0: 3 ports detected
10659 22:54:27.542811 <6>[ 2.850567] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10660 22:54:27.697706 <6>[ 3.008448] hub 1-1:1.0: USB hub found
10661 22:54:27.700981 <6>[ 3.012921] hub 1-1:1.0: 4 ports detected
10662 22:54:27.709693 <6>[ 3.020668] hub 1-1:1.0: USB hub found
10663 22:54:27.713147 <6>[ 3.025012] hub 1-1:1.0: 4 ports detected
10664 22:54:27.782947 <6>[ 3.090641] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10665 22:54:27.892126 <6>[ 3.199271] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10666 22:54:27.927425 <4>[ 3.235178] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10667 22:54:27.937354 <4>[ 3.244272] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10668 22:54:27.976280 <6>[ 3.287407] r8152 2-1.3:1.0 eth0: v1.12.13
10669 22:54:28.034873 <6>[ 3.342545] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10670 22:54:28.167381 <6>[ 3.478185] hub 1-1.4:1.0: USB hub found
10671 22:54:28.170850 <6>[ 3.482873] hub 1-1.4:1.0: 2 ports detected
10672 22:54:28.181145 <6>[ 3.491776] hub 1-1.4:1.0: USB hub found
10673 22:54:28.184912 <6>[ 3.496378] hub 1-1.4:1.0: 2 ports detected
10674 22:54:28.483105 <6>[ 3.790572] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10675 22:54:28.675003 <6>[ 3.982423] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10676 22:54:29.609219 <6>[ 4.920226] r8152 2-1.3:1.0 eth0: carrier on
10677 22:54:32.242950 <5>[ 4.946418] Sending DHCP requests .., OK
10678 22:54:32.249607 <6>[ 7.558754] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.21
10679 22:54:32.253174 <6>[ 7.567047] IP-Config: Complete:
10680 22:54:32.266356 <6>[ 7.570546] device=eth0, hwaddr=00:e0:4c:72:2d:d6, ipaddr=192.168.201.21, mask=255.255.255.0, gw=192.168.201.1
10681 22:54:32.272822 <6>[ 7.581266] host=mt8192-asurada-spherion-r0-cbg-1, domain=lava-rack, nis-domain=(none)
10682 22:54:32.279877 <6>[ 7.589885] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10683 22:54:32.286745 <6>[ 7.589895] nameserver0=192.168.201.1
10684 22:54:32.289391 <6>[ 7.602072] clk: Disabling unused clocks
10685 22:54:32.293057 <6>[ 7.607565] ALSA device list:
10686 22:54:32.299808 <6>[ 7.610834] No soundcards found.
10687 22:54:32.306837 <6>[ 7.618051] Freeing unused kernel memory: 8512K
10688 22:54:32.310131 <6>[ 7.623015] Run /init as init process
10689 22:54:32.333714 Starting syslogd: OK
10690 22:54:32.338202 Starting klogd: OK
10691 22:54:32.347074 Running sysctl: OK
10692 22:54:32.353504 Populating /dev using udev: <30>[ 7.665784] udevd[193]: starting version 3.2.9
10693 22:54:32.361452 <27>[ 7.672792] udevd[193]: specified user 'tss' unknown
10694 22:54:32.368351 <27>[ 7.678152] udevd[193]: specified group 'tss' unknown
10695 22:54:32.371608 <30>[ 7.684347] udevd[194]: starting eudev-3.2.9
10696 22:54:32.404958 <27>[ 7.715778] udevd[194]: specified user 'tss' unknown
10697 22:54:32.411232 <27>[ 7.721152] udevd[194]: specified group 'tss' unknown
10698 22:54:32.530163 <6>[ 7.837978] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10699 22:54:32.536384 <6>[ 7.845784] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10700 22:54:32.552902 <6>[ 7.861060] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10701 22:54:32.564025 <6>[ 7.872244] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10702 22:54:32.592246 <6>[ 7.903200] remoteproc remoteproc0: scp is available
10703 22:54:32.601580 <3>[ 7.903451] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10704 22:54:32.605079 <6>[ 7.908536] remoteproc remoteproc0: powering up scp
10705 22:54:32.615126 <3>[ 7.916821] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10706 22:54:32.621577 <6>[ 7.921721] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10707 22:54:32.628328 <6>[ 7.921772] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10708 22:54:32.634632 <3>[ 7.930024] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10709 22:54:32.641360 <6>[ 7.947891] mc: Linux media interface: v0.10
10710 22:54:32.648330 <3>[ 7.952178] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10711 22:54:32.658088 <3>[ 7.964706] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10712 22:54:32.664659 <6>[ 7.967599] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10713 22:54:32.670871 <4>[ 7.969023] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10714 22:54:32.677612 <4>[ 7.969181] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10715 22:54:32.687303 <3>[ 7.972790] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10716 22:54:32.694038 <3>[ 7.972797] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10717 22:54:32.704435 <3>[ 7.972804] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10718 22:54:32.710661 <3>[ 7.972843] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10719 22:54:32.716988 <6>[ 7.995795] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10720 22:54:32.724372 <6>[ 7.995995] videodev: Linux video capture interface: v2.00
10721 22:54:32.730986 <3>[ 8.003181] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10722 22:54:32.741234 <4>[ 8.011283] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10723 22:54:32.744672 <4>[ 8.011283] Fallback method does not support PEC.
10724 22:54:32.751133 <6>[ 8.011771] pci_bus 0000:00: root bus resource [bus 00-ff]
10725 22:54:32.757777 <6>[ 8.011789] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10726 22:54:32.767873 <6>[ 8.011797] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10727 22:54:32.775078 <6>[ 8.011855] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10728 22:54:32.781785 <6>[ 8.011875] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10729 22:54:32.784802 <6>[ 8.011959] pci 0000:00:00.0: supports D1 D2
10730 22:54:32.791995 <6>[ 8.011963] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10731 22:54:32.802088 <6>[ 8.013537] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10732 22:54:32.808813 <6>[ 8.013644] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10733 22:54:32.815160 <6>[ 8.013675] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10734 22:54:32.821916 <6>[ 8.013695] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10735 22:54:32.831994 <6>[ 8.013714] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10736 22:54:32.834984 <6>[ 8.013829] pci 0000:01:00.0: supports D1 D2
10737 22:54:32.841642 <6>[ 8.013832] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10738 22:54:32.851707 <6>[ 8.018905] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10739 22:54:32.861832 <3>[ 8.019305] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10740 22:54:32.868238 <6>[ 8.019310] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10741 22:54:32.874922 <6>[ 8.022377] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10742 22:54:32.884838 <6>[ 8.022417] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10743 22:54:32.891433 <6>[ 8.022420] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10744 22:54:32.901342 <6>[ 8.022429] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10745 22:54:32.908438 <6>[ 8.022442] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10746 22:54:32.914739 <6>[ 8.022454] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10747 22:54:32.921231 <6>[ 8.022467] pci 0000:00:00.0: PCI bridge to [bus 01]
10748 22:54:32.928433 <6>[ 8.022472] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10749 22:54:32.934521 <6>[ 8.022767] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10750 22:54:32.941203 <6>[ 8.023415] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10751 22:54:32.948358 <6>[ 8.023801] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10752 22:54:32.957985 <3>[ 8.043378] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10753 22:54:32.964679 <3>[ 8.048075] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10754 22:54:32.971117 <3>[ 8.048164] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10755 22:54:32.980945 <6>[ 8.063616] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10756 22:54:32.987728 <6>[ 8.063665] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10757 22:54:32.993989 <6>[ 8.063672] remoteproc remoteproc0: remote processor scp is now up
10758 22:54:33.003961 <3>[ 8.067494] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10759 22:54:33.010707 <3>[ 8.067498] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10760 22:54:33.017473 <3>[ 8.067503] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10761 22:54:33.027331 <3>[ 8.067508] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10762 22:54:33.037487 <6>[ 8.078986] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10763 22:54:33.043798 <3>[ 8.084545] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10764 22:54:33.054175 <5>[ 8.115417] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10765 22:54:33.060366 <3>[ 8.118700] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10766 22:54:33.070314 <6>[ 8.120503] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10767 22:54:33.077054 <6>[ 8.123313] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10768 22:54:33.080559 <6>[ 8.132359] Bluetooth: Core ver 2.22
10769 22:54:33.086905 <5>[ 8.148656] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10770 22:54:33.093650 <6>[ 8.151302] NET: Registered PF_BLUETOOTH protocol family
10771 22:54:33.100424 <6>[ 8.152462] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10772 22:54:33.113264 <6>[ 8.153443] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10773 22:54:33.119603 <6>[ 8.153558] usbcore: registered new interface driver uvcvideo
10774 22:54:33.126582 <5>[ 8.158856] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10775 22:54:33.133043 <6>[ 8.168252] Bluetooth: HCI device and connection manager initialized
10776 22:54:33.139523 <6>[ 8.168270] Bluetooth: HCI socket layer initialized
10777 22:54:33.149514 <4>[ 8.176540] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10778 22:54:33.153128 <6>[ 8.185380] Bluetooth: L2CAP socket layer initialized
10779 22:54:33.159815 <6>[ 8.185397] Bluetooth: SCO socket layer initialized
10780 22:54:33.166155 <6>[ 8.188390] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10781 22:54:33.169438 <6>[ 8.192269] cfg80211: failed to load regulatory.db
10782 22:54:33.176258 <6>[ 8.238016] usbcore: registered new interface driver btusb
10783 22:54:33.185994 <4>[ 8.238881] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10784 22:54:33.192685 <3>[ 8.238889] Bluetooth: hci0: Failed to load firmware file (-2)
10785 22:54:33.199040 <3>[ 8.238891] Bluetooth: hci0: Failed to set up firmware (-2)
10786 22:54:33.209253 <4>[ 8.238893] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10787 22:54:33.215559 <6>[ 8.279251] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10788 22:54:33.222011 <6>[ 8.532501] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10789 22:54:33.247035 <6>[ 8.558577] mt7921e 0000:01:00.0: ASIC revision: 79610010
10790 22:54:33.349919 <6>[ 8.657985] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10791 22:54:33.353437 <6>[ 8.657985]
10792 22:54:33.353989 done
10793 22:54:33.365844 Saving random seed: OK
10794 22:54:33.378209 Starting network: ip: RTNETLINK answers: File exists
10795 22:54:33.381677 FAIL
10796 22:54:33.414916 Starting dropbear sshd: <6>[ 8.725858] NET: Registered PF_INET6 protocol family
10797 22:54:33.421046 <6>[ 8.732355] Segment Routing with IPv6
10798 22:54:33.424541 <6>[ 8.736348] In-situ OAM (IOAM) with IPv6
10799 22:54:33.428088 OK
10800 22:54:33.438509 /bin/sh: can't access tty; job control turned off
10801 22:54:33.439813 Matched prompt #10: / #
10803 22:54:33.441095 Setting prompt string to ['/ #']
10804 22:54:33.441603 end: 2.2.5.1 login-action (duration 00:00:09) [common]
10806 22:54:33.442649 end: 2.2.5 auto-login-action (duration 00:00:10) [common]
10807 22:54:33.443125 start: 2.2.6 expect-shell-connection (timeout 00:03:43) [common]
10808 22:54:33.443503 Setting prompt string to ['/ #']
10809 22:54:33.443837 Forcing a shell prompt, looking for ['/ #']
10811 22:54:33.494752 / #
10812 22:54:33.495394 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10813 22:54:33.495817 Waiting using forced prompt support (timeout 00:02:30)
10814 22:54:33.501088
10815 22:54:33.502048 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10816 22:54:33.502584 start: 2.2.7 export-device-env (timeout 00:03:43) [common]
10817 22:54:33.503081 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10818 22:54:33.503538 end: 2.2 depthcharge-retry (duration 00:01:17) [common]
10819 22:54:33.503986 end: 2 depthcharge-action (duration 00:01:17) [common]
10820 22:54:33.504451 start: 3 lava-test-retry (timeout 00:01:00) [common]
10821 22:54:33.504911 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10822 22:54:33.505293 Using namespace: common
10824 22:54:33.606575 / # #
10825 22:54:33.607216 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10826 22:54:33.619067 #<6>[ 8.927074] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10827 22:54:33.619626
10828 22:54:33.620308 Using /lava-13683720
10830 22:54:33.721511 / # export SHELL=/bin/sh
10831 22:54:33.728488 export SHELL=/bin/sh
10833 22:54:33.830323 / # . /lava-13683720/environment
10834 22:54:33.837251 . /lava-13683720/environment
10836 22:54:33.939051 / # /lava-13683720/bin/lava-test-runner /lava-13683720/0
10837 22:54:33.939696 Test shell timeout: 10s (minimum of the action and connection timeout)
10838 22:54:33.952019 /lava-13683720/bin/lava-test-runner /lava-13683720/0
10839 22:54:33.965270 + export 'TESTRUN_ID=0_dmesg'
10840 22:54:33.971904 +<8>[ 9.282283] <LAVA_SIGNAL_STARTRUN 0_dmesg 13683720_1.5.2.3.1>
10841 22:54:33.972764 Received signal: <STARTRUN> 0_dmesg 13683720_1.5.2.3.1
10842 22:54:33.973210 Starting test lava.0_dmesg (13683720_1.5.2.3.1)
10843 22:54:33.973710 Skipping test definition patterns.
10844 22:54:33.974861 cd /lava-13683720/0/tests/0_dmesg
10845 22:54:33.975396 + cat uuid
10846 22:54:33.978405 + UUID=13683720_1.5.2.3.1
10847 22:54:33.978967 + set +x
10848 22:54:33.984903 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10849 22:54:33.994810 <8>[ 9.301985] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10850 22:54:33.995639 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10852 22:54:34.011908 <8>[ 9.320363] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10853 22:54:34.012717 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10855 22:54:34.034289 <8>[ 9.342130] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10856 22:54:34.035122 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10858 22:54:34.037452 + set +x
10859 22:54:34.040597 <8>[ 9.351445] <LAVA_SIGNAL_ENDRUN 0_dmesg 13683720_1.5.2.3.1>
10860 22:54:34.041434 Received signal: <ENDRUN> 0_dmesg 13683720_1.5.2.3.1
10861 22:54:34.041901 Ending use of test pattern.
10862 22:54:34.042254 Ending test lava.0_dmesg (13683720_1.5.2.3.1), duration 0.07
10864 22:54:34.044257 <LAVA_TEST_RUNNER EXIT>
10865 22:54:34.045040 ok: lava_test_shell seems to have completed
10866 22:54:34.045657 alert: pass
crit: pass
emerg: pass
10867 22:54:34.046101 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10868 22:54:34.046551 end: 3 lava-test-retry (duration 00:00:01) [common]
10869 22:54:34.047040 start: 4 finalize (timeout 00:08:24) [common]
10870 22:54:34.047508 start: 4.1 power-off (timeout 00:00:30) [common]
10871 22:54:34.047784 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
10872 22:54:34.245490 >> Command sent successfully.
10873 22:54:34.247698 Returned 0 in 0 seconds
10874 22:54:34.348162 end: 4.1 power-off (duration 00:00:00) [common]
10876 22:54:34.348592 start: 4.2 read-feedback (timeout 00:08:24) [common]
10877 22:54:34.348950 Listened to connection for namespace 'common' for up to 1s
10878 22:54:35.349729 Finalising connection for namespace 'common'
10879 22:54:35.350474 Disconnecting from shell: Finalise
10880 22:54:35.350936 / #
10881 22:54:35.452142 end: 4.2 read-feedback (duration 00:00:01) [common]
10882 22:54:35.452897 end: 4 finalize (duration 00:00:01) [common]
10883 22:54:35.453591 Cleaning after the job
10884 22:54:35.454124 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13683720/tftp-deploy-2rfxgyld/ramdisk
10885 22:54:35.465732 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13683720/tftp-deploy-2rfxgyld/kernel
10886 22:54:35.493918 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13683720/tftp-deploy-2rfxgyld/dtb
10887 22:54:35.494347 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/13683720/tftp-deploy-2rfxgyld/modules
10888 22:54:35.504743 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/13683720
10889 22:54:35.546912 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/13683720
10890 22:54:35.547096 Job finished correctly